1 /****************************************************************************** 2 3 Copyright (c) 2001-2008, Intel Corporation 4 All rights reserved. 5 6 Redistribution and use in source and binary forms, with or without 7 modification, are permitted provided that the following conditions are met: 8 9 1. Redistributions of source code must retain the above copyright notice, 10 this list of conditions and the following disclaimer. 11 12 2. Redistributions in binary form must reproduce the above copyright 13 notice, this list of conditions and the following disclaimer in the 14 documentation and/or other materials provided with the distribution. 15 16 3. Neither the name of the Intel Corporation nor the names of its 17 contributors may be used to endorse or promote products derived from 18 this software without specific prior written permission. 19 20 THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 21 AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 22 IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 23 ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE 24 LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 25 CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 26 SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 27 INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 28 CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 29 ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 30 POSSIBILITY OF SUCH DAMAGE. 31 32 ******************************************************************************/ 33 /*$FreeBSD$*/ 34 35 #include "ixgbe_common.h" 36 #include "ixgbe_api.h" 37 38 static s32 ixgbe_poll_eeprom_eerd_done(struct ixgbe_hw *hw); 39 static s32 ixgbe_acquire_eeprom(struct ixgbe_hw *hw); 40 static s32 ixgbe_get_eeprom_semaphore(struct ixgbe_hw *hw); 41 static void ixgbe_release_eeprom_semaphore(struct ixgbe_hw *hw); 42 static s32 ixgbe_ready_eeprom(struct ixgbe_hw *hw); 43 static void ixgbe_standby_eeprom(struct ixgbe_hw *hw); 44 static void ixgbe_shift_out_eeprom_bits(struct ixgbe_hw *hw, u16 data, 45 u16 count); 46 static u16 ixgbe_shift_in_eeprom_bits(struct ixgbe_hw *hw, u16 count); 47 static void ixgbe_raise_eeprom_clk(struct ixgbe_hw *hw, u32 *eec); 48 static void ixgbe_lower_eeprom_clk(struct ixgbe_hw *hw, u32 *eec); 49 static void ixgbe_release_eeprom(struct ixgbe_hw *hw); 50 static u16 ixgbe_calc_eeprom_checksum(struct ixgbe_hw *hw); 51 52 static void ixgbe_enable_rar(struct ixgbe_hw *hw, u32 index); 53 static void ixgbe_disable_rar(struct ixgbe_hw *hw, u32 index); 54 static s32 ixgbe_mta_vector(struct ixgbe_hw *hw, u8 *mc_addr); 55 void ixgbe_add_mc_addr(struct ixgbe_hw *hw, u8 *mc_addr); 56 void ixgbe_add_uc_addr(struct ixgbe_hw *hw, u8 *addr, u32 vmdq); 57 58 /** 59 * ixgbe_init_ops_generic - Inits function ptrs 60 * @hw: pointer to the hardware structure 61 * 62 * Initialize the function pointers. 63 **/ 64 s32 ixgbe_init_ops_generic(struct ixgbe_hw *hw) 65 { 66 struct ixgbe_eeprom_info *eeprom = &hw->eeprom; 67 struct ixgbe_mac_info *mac = &hw->mac; 68 u32 eec = IXGBE_READ_REG(hw, IXGBE_EEC); 69 70 /* EEPROM */ 71 eeprom->ops.init_params = &ixgbe_init_eeprom_params_generic; 72 /* If EEPROM is valid (bit 8 = 1), use EERD otherwise use bit bang */ 73 if (eec & (1 << 8)) 74 eeprom->ops.read = &ixgbe_read_eeprom_generic; 75 else 76 eeprom->ops.read = &ixgbe_read_eeprom_bit_bang_generic; 77 eeprom->ops.write = &ixgbe_write_eeprom_generic; 78 eeprom->ops.validate_checksum = 79 &ixgbe_validate_eeprom_checksum_generic; 80 eeprom->ops.update_checksum = &ixgbe_update_eeprom_checksum_generic; 81 82 /* MAC */ 83 mac->ops.init_hw = &ixgbe_init_hw_generic; 84 mac->ops.reset_hw = NULL; 85 mac->ops.start_hw = &ixgbe_start_hw_generic; 86 mac->ops.clear_hw_cntrs = &ixgbe_clear_hw_cntrs_generic; 87 mac->ops.get_media_type = NULL; 88 mac->ops.get_mac_addr = &ixgbe_get_mac_addr_generic; 89 mac->ops.stop_adapter = &ixgbe_stop_adapter_generic; 90 mac->ops.get_bus_info = &ixgbe_get_bus_info_generic; 91 mac->ops.read_analog_reg8 = &ixgbe_read_analog_reg8_generic; 92 mac->ops.write_analog_reg8 = &ixgbe_write_analog_reg8_generic; 93 94 /* LEDs */ 95 mac->ops.led_on = &ixgbe_led_on_generic; 96 mac->ops.led_off = &ixgbe_led_off_generic; 97 mac->ops.blink_led_start = NULL; 98 mac->ops.blink_led_stop = NULL; 99 100 /* RAR, Multicast, VLAN */ 101 mac->ops.set_rar = &ixgbe_set_rar_generic; 102 mac->ops.clear_rar = &ixgbe_clear_rar_generic; 103 mac->ops.set_vmdq = NULL; 104 mac->ops.clear_vmdq = NULL; 105 mac->ops.init_rx_addrs = &ixgbe_init_rx_addrs_generic; 106 mac->ops.update_uc_addr_list = &ixgbe_update_uc_addr_list_generic; 107 mac->ops.update_mc_addr_list = &ixgbe_update_mc_addr_list_generic; 108 mac->ops.enable_mc = &ixgbe_enable_mc_generic; 109 mac->ops.disable_mc = &ixgbe_disable_mc_generic; 110 mac->ops.clear_vfta = NULL; 111 mac->ops.set_vfta = NULL; 112 mac->ops.init_uta_tables = NULL; 113 114 /* Flow Control */ 115 mac->ops.setup_fc = NULL; 116 117 /* Link */ 118 mac->ops.get_link_capabilities = NULL; 119 mac->ops.setup_link = NULL; 120 mac->ops.setup_link_speed = NULL; 121 mac->ops.check_link = NULL; 122 123 return IXGBE_SUCCESS; 124 } 125 126 /** 127 * ixgbe_start_hw_generic - Prepare hardware for Tx/Rx 128 * @hw: pointer to hardware structure 129 * 130 * Starts the hardware by filling the bus info structure and media type, clears 131 * all on chip counters, initializes receive address registers, multicast 132 * table, VLAN filter table, calls routine to set up link and flow control 133 * settings, and leaves transmit and receive units disabled and uninitialized 134 **/ 135 s32 ixgbe_start_hw_generic(struct ixgbe_hw *hw) 136 { 137 u32 ctrl_ext; 138 139 /* Set the media type */ 140 hw->phy.media_type = hw->mac.ops.get_media_type(hw); 141 142 /* Set bus info */ 143 hw->mac.ops.get_bus_info(hw); 144 145 /* Identify the PHY */ 146 hw->phy.ops.identify(hw); 147 148 /* 149 * Store MAC address from RAR0, clear receive address registers, and 150 * clear the multicast table 151 */ 152 hw->mac.ops.init_rx_addrs(hw); 153 154 /* Clear the VLAN filter table */ 155 hw->mac.ops.clear_vfta(hw); 156 157 /* Set up link */ 158 hw->mac.ops.setup_link(hw); 159 160 /* Clear statistics registers */ 161 hw->mac.ops.clear_hw_cntrs(hw); 162 163 /* Set No Snoop Disable */ 164 ctrl_ext = IXGBE_READ_REG(hw, IXGBE_CTRL_EXT); 165 ctrl_ext |= IXGBE_CTRL_EXT_NS_DIS; 166 IXGBE_WRITE_REG(hw, IXGBE_CTRL_EXT, ctrl_ext); 167 IXGBE_WRITE_FLUSH(hw); 168 169 /* Clear adapter stopped flag */ 170 hw->adapter_stopped = FALSE; 171 172 return IXGBE_SUCCESS; 173 } 174 175 /** 176 * ixgbe_init_hw_generic - Generic hardware initialization 177 * @hw: pointer to hardware structure 178 * 179 * Initialize the hardware by resetting the hardware, filling the bus info 180 * structure and media type, clears all on chip counters, initializes receive 181 * address registers, multicast table, VLAN filter table, calls routine to set 182 * up link and flow control settings, and leaves transmit and receive units 183 * disabled and uninitialized 184 **/ 185 s32 ixgbe_init_hw_generic(struct ixgbe_hw *hw) 186 { 187 /* Reset the hardware */ 188 hw->mac.ops.reset_hw(hw); 189 190 /* Start the HW */ 191 hw->mac.ops.start_hw(hw); 192 193 return IXGBE_SUCCESS; 194 } 195 196 /** 197 * ixgbe_clear_hw_cntrs_generic - Generic clear hardware counters 198 * @hw: pointer to hardware structure 199 * 200 * Clears all hardware statistics counters by reading them from the hardware 201 * Statistics counters are clear on read. 202 **/ 203 s32 ixgbe_clear_hw_cntrs_generic(struct ixgbe_hw *hw) 204 { 205 u16 i = 0; 206 207 IXGBE_READ_REG(hw, IXGBE_CRCERRS); 208 IXGBE_READ_REG(hw, IXGBE_ILLERRC); 209 IXGBE_READ_REG(hw, IXGBE_ERRBC); 210 IXGBE_READ_REG(hw, IXGBE_MSPDC); 211 for (i = 0; i < 8; i++) 212 IXGBE_READ_REG(hw, IXGBE_MPC(i)); 213 214 IXGBE_READ_REG(hw, IXGBE_MLFC); 215 IXGBE_READ_REG(hw, IXGBE_MRFC); 216 IXGBE_READ_REG(hw, IXGBE_RLEC); 217 IXGBE_READ_REG(hw, IXGBE_LXONTXC); 218 IXGBE_READ_REG(hw, IXGBE_LXONRXC); 219 IXGBE_READ_REG(hw, IXGBE_LXOFFTXC); 220 IXGBE_READ_REG(hw, IXGBE_LXOFFRXC); 221 222 for (i = 0; i < 8; i++) { 223 IXGBE_READ_REG(hw, IXGBE_PXONTXC(i)); 224 IXGBE_READ_REG(hw, IXGBE_PXONRXC(i)); 225 IXGBE_READ_REG(hw, IXGBE_PXOFFTXC(i)); 226 IXGBE_READ_REG(hw, IXGBE_PXOFFRXC(i)); 227 } 228 229 IXGBE_READ_REG(hw, IXGBE_PRC64); 230 IXGBE_READ_REG(hw, IXGBE_PRC127); 231 IXGBE_READ_REG(hw, IXGBE_PRC255); 232 IXGBE_READ_REG(hw, IXGBE_PRC511); 233 IXGBE_READ_REG(hw, IXGBE_PRC1023); 234 IXGBE_READ_REG(hw, IXGBE_PRC1522); 235 IXGBE_READ_REG(hw, IXGBE_GPRC); 236 IXGBE_READ_REG(hw, IXGBE_BPRC); 237 IXGBE_READ_REG(hw, IXGBE_MPRC); 238 IXGBE_READ_REG(hw, IXGBE_GPTC); 239 IXGBE_READ_REG(hw, IXGBE_GORCL); 240 IXGBE_READ_REG(hw, IXGBE_GORCH); 241 IXGBE_READ_REG(hw, IXGBE_GOTCL); 242 IXGBE_READ_REG(hw, IXGBE_GOTCH); 243 for (i = 0; i < 8; i++) 244 IXGBE_READ_REG(hw, IXGBE_RNBC(i)); 245 IXGBE_READ_REG(hw, IXGBE_RUC); 246 IXGBE_READ_REG(hw, IXGBE_RFC); 247 IXGBE_READ_REG(hw, IXGBE_ROC); 248 IXGBE_READ_REG(hw, IXGBE_RJC); 249 IXGBE_READ_REG(hw, IXGBE_MNGPRC); 250 IXGBE_READ_REG(hw, IXGBE_MNGPDC); 251 IXGBE_READ_REG(hw, IXGBE_MNGPTC); 252 IXGBE_READ_REG(hw, IXGBE_TORL); 253 IXGBE_READ_REG(hw, IXGBE_TORH); 254 IXGBE_READ_REG(hw, IXGBE_TPR); 255 IXGBE_READ_REG(hw, IXGBE_TPT); 256 IXGBE_READ_REG(hw, IXGBE_PTC64); 257 IXGBE_READ_REG(hw, IXGBE_PTC127); 258 IXGBE_READ_REG(hw, IXGBE_PTC255); 259 IXGBE_READ_REG(hw, IXGBE_PTC511); 260 IXGBE_READ_REG(hw, IXGBE_PTC1023); 261 IXGBE_READ_REG(hw, IXGBE_PTC1522); 262 IXGBE_READ_REG(hw, IXGBE_MPTC); 263 IXGBE_READ_REG(hw, IXGBE_BPTC); 264 for (i = 0; i < 16; i++) { 265 IXGBE_READ_REG(hw, IXGBE_QPRC(i)); 266 IXGBE_READ_REG(hw, IXGBE_QBRC(i)); 267 IXGBE_READ_REG(hw, IXGBE_QPTC(i)); 268 IXGBE_READ_REG(hw, IXGBE_QBTC(i)); 269 } 270 271 return IXGBE_SUCCESS; 272 } 273 274 /** 275 * ixgbe_read_pba_num - Reads part number from EEPROM 276 * @hw: pointer to hardware structure 277 * @pba_num: stores the part number from the EEPROM 278 * 279 * Reads the part number from the EEPROM. 280 **/ 281 s32 ixgbe_read_pba_num_generic(struct ixgbe_hw *hw, u32 *pba_num) 282 { 283 s32 ret_val; 284 u16 data; 285 286 DEBUGFUNC("ixgbe_read_pba_num_generic"); 287 288 ret_val = hw->eeprom.ops.read(hw, IXGBE_PBANUM0_PTR, &data); 289 if (ret_val) { 290 DEBUGOUT("NVM Read Error\n"); 291 return ret_val; 292 } 293 *pba_num = (u32)(data << 16); 294 295 ret_val = hw->eeprom.ops.read(hw, IXGBE_PBANUM1_PTR, &data); 296 if (ret_val) { 297 DEBUGOUT("NVM Read Error\n"); 298 return ret_val; 299 } 300 *pba_num |= data; 301 302 return IXGBE_SUCCESS; 303 } 304 305 /** 306 * ixgbe_get_mac_addr_generic - Generic get MAC address 307 * @hw: pointer to hardware structure 308 * @mac_addr: Adapter MAC address 309 * 310 * Reads the adapter's MAC address from first Receive Address Register (RAR0) 311 * A reset of the adapter must be performed prior to calling this function 312 * in order for the MAC address to have been loaded from the EEPROM into RAR0 313 **/ 314 s32 ixgbe_get_mac_addr_generic(struct ixgbe_hw *hw, u8 *mac_addr) 315 { 316 u32 rar_high; 317 u32 rar_low; 318 u16 i; 319 320 rar_high = IXGBE_READ_REG(hw, IXGBE_RAH(0)); 321 rar_low = IXGBE_READ_REG(hw, IXGBE_RAL(0)); 322 323 for (i = 0; i < 4; i++) 324 mac_addr[i] = (u8)(rar_low >> (i*8)); 325 326 for (i = 0; i < 2; i++) 327 mac_addr[i+4] = (u8)(rar_high >> (i*8)); 328 329 return IXGBE_SUCCESS; 330 } 331 332 /** 333 * ixgbe_get_bus_info_generic - Generic set PCI bus info 334 * @hw: pointer to hardware structure 335 * 336 * Sets the PCI bus info (speed, width, type) within the ixgbe_hw structure 337 **/ 338 s32 ixgbe_get_bus_info_generic(struct ixgbe_hw *hw) 339 { 340 u16 link_status; 341 342 hw->bus.type = ixgbe_bus_type_pci_express; 343 344 /* Get the negotiated link width and speed from PCI config space */ 345 link_status = IXGBE_READ_PCIE_WORD(hw, IXGBE_PCI_LINK_STATUS); 346 347 switch (link_status & IXGBE_PCI_LINK_WIDTH) { 348 case IXGBE_PCI_LINK_WIDTH_1: 349 hw->bus.width = ixgbe_bus_width_pcie_x1; 350 break; 351 case IXGBE_PCI_LINK_WIDTH_2: 352 hw->bus.width = ixgbe_bus_width_pcie_x2; 353 break; 354 case IXGBE_PCI_LINK_WIDTH_4: 355 hw->bus.width = ixgbe_bus_width_pcie_x4; 356 break; 357 case IXGBE_PCI_LINK_WIDTH_8: 358 hw->bus.width = ixgbe_bus_width_pcie_x8; 359 break; 360 default: 361 hw->bus.width = ixgbe_bus_width_unknown; 362 break; 363 } 364 365 switch (link_status & IXGBE_PCI_LINK_SPEED) { 366 case IXGBE_PCI_LINK_SPEED_2500: 367 hw->bus.speed = ixgbe_bus_speed_2500; 368 break; 369 case IXGBE_PCI_LINK_SPEED_5000: 370 hw->bus.speed = ixgbe_bus_speed_5000; 371 break; 372 default: 373 hw->bus.speed = ixgbe_bus_speed_unknown; 374 break; 375 } 376 377 return IXGBE_SUCCESS; 378 } 379 380 /** 381 * ixgbe_stop_adapter_generic - Generic stop Tx/Rx units 382 * @hw: pointer to hardware structure 383 * 384 * Sets the adapter_stopped flag within ixgbe_hw struct. Clears interrupts, 385 * disables transmit and receive units. The adapter_stopped flag is used by 386 * the shared code and drivers to determine if the adapter is in a stopped 387 * state and should not touch the hardware. 388 **/ 389 s32 ixgbe_stop_adapter_generic(struct ixgbe_hw *hw) 390 { 391 u32 number_of_queues; 392 u32 reg_val; 393 u16 i; 394 395 /* 396 * Set the adapter_stopped flag so other driver functions stop touching 397 * the hardware 398 */ 399 hw->adapter_stopped = TRUE; 400 401 /* Disable the receive unit */ 402 reg_val = IXGBE_READ_REG(hw, IXGBE_RXCTRL); 403 reg_val &= ~(IXGBE_RXCTRL_RXEN); 404 IXGBE_WRITE_REG(hw, IXGBE_RXCTRL, reg_val); 405 IXGBE_WRITE_FLUSH(hw); 406 msec_delay(2); 407 408 /* Clear interrupt mask to stop from interrupts being generated */ 409 IXGBE_WRITE_REG(hw, IXGBE_EIMC, IXGBE_IRQ_CLEAR_MASK); 410 411 /* Clear any pending interrupts */ 412 IXGBE_READ_REG(hw, IXGBE_EICR); 413 414 /* Disable the transmit unit. Each queue must be disabled. */ 415 number_of_queues = hw->mac.max_tx_queues; 416 for (i = 0; i < number_of_queues; i++) { 417 reg_val = IXGBE_READ_REG(hw, IXGBE_TXDCTL(i)); 418 if (reg_val & IXGBE_TXDCTL_ENABLE) { 419 reg_val &= ~IXGBE_TXDCTL_ENABLE; 420 IXGBE_WRITE_REG(hw, IXGBE_TXDCTL(i), reg_val); 421 } 422 } 423 424 /* 425 * Prevent the PCI-E bus from from hanging by disabling PCI-E master 426 * access and verify no pending requests 427 */ 428 if (ixgbe_disable_pcie_master(hw) != IXGBE_SUCCESS) { 429 DEBUGOUT("PCI-E Master disable polling has failed.\n"); 430 } 431 432 return IXGBE_SUCCESS; 433 } 434 435 /** 436 * ixgbe_led_on_generic - Turns on the software controllable LEDs. 437 * @hw: pointer to hardware structure 438 * @index: led number to turn on 439 **/ 440 s32 ixgbe_led_on_generic(struct ixgbe_hw *hw, u32 index) 441 { 442 u32 led_reg = IXGBE_READ_REG(hw, IXGBE_LEDCTL); 443 444 /* To turn on the LED, set mode to ON. */ 445 led_reg &= ~IXGBE_LED_MODE_MASK(index); 446 led_reg |= IXGBE_LED_ON << IXGBE_LED_MODE_SHIFT(index); 447 IXGBE_WRITE_REG(hw, IXGBE_LEDCTL, led_reg); 448 IXGBE_WRITE_FLUSH(hw); 449 450 return IXGBE_SUCCESS; 451 } 452 453 /** 454 * ixgbe_led_off_generic - Turns off the software controllable LEDs. 455 * @hw: pointer to hardware structure 456 * @index: led number to turn off 457 **/ 458 s32 ixgbe_led_off_generic(struct ixgbe_hw *hw, u32 index) 459 { 460 u32 led_reg = IXGBE_READ_REG(hw, IXGBE_LEDCTL); 461 462 /* To turn off the LED, set mode to OFF. */ 463 led_reg &= ~IXGBE_LED_MODE_MASK(index); 464 led_reg |= IXGBE_LED_OFF << IXGBE_LED_MODE_SHIFT(index); 465 IXGBE_WRITE_REG(hw, IXGBE_LEDCTL, led_reg); 466 IXGBE_WRITE_FLUSH(hw); 467 468 return IXGBE_SUCCESS; 469 } 470 471 /** 472 * ixgbe_init_eeprom_params_generic - Initialize EEPROM params 473 * @hw: pointer to hardware structure 474 * 475 * Initializes the EEPROM parameters ixgbe_eeprom_info within the 476 * ixgbe_hw struct in order to set up EEPROM access. 477 **/ 478 s32 ixgbe_init_eeprom_params_generic(struct ixgbe_hw *hw) 479 { 480 struct ixgbe_eeprom_info *eeprom = &hw->eeprom; 481 u32 eec; 482 u16 eeprom_size; 483 484 if (eeprom->type == ixgbe_eeprom_uninitialized) { 485 eeprom->type = ixgbe_eeprom_none; 486 /* Set default semaphore delay to 10ms which is a well 487 * tested value */ 488 eeprom->semaphore_delay = 10; 489 490 /* 491 * Check for EEPROM present first. 492 * If not present leave as none 493 */ 494 eec = IXGBE_READ_REG(hw, IXGBE_EEC); 495 if (eec & IXGBE_EEC_PRES) { 496 eeprom->type = ixgbe_eeprom_spi; 497 498 /* 499 * SPI EEPROM is assumed here. This code would need to 500 * change if a future EEPROM is not SPI. 501 */ 502 eeprom_size = (u16)((eec & IXGBE_EEC_SIZE) >> 503 IXGBE_EEC_SIZE_SHIFT); 504 eeprom->word_size = 1 << (eeprom_size + 505 IXGBE_EEPROM_WORD_SIZE_SHIFT); 506 } 507 508 if (eec & IXGBE_EEC_ADDR_SIZE) 509 eeprom->address_bits = 16; 510 else 511 eeprom->address_bits = 8; 512 DEBUGOUT3("Eeprom params: type = %d, size = %d, address bits: " 513 "%d\n", eeprom->type, eeprom->word_size, 514 eeprom->address_bits); 515 } 516 517 return IXGBE_SUCCESS; 518 } 519 520 /** 521 * ixgbe_write_eeprom_generic - Writes 16 bit value to EEPROM 522 * @hw: pointer to hardware structure 523 * @offset: offset within the EEPROM to be written to 524 * @data: 16 bit word to be written to the EEPROM 525 * 526 * If ixgbe_eeprom_update_checksum is not called after this function, the 527 * EEPROM will most likely contain an invalid checksum. 528 **/ 529 s32 ixgbe_write_eeprom_generic(struct ixgbe_hw *hw, u16 offset, u16 data) 530 { 531 s32 status; 532 u8 write_opcode = IXGBE_EEPROM_WRITE_OPCODE_SPI; 533 534 hw->eeprom.ops.init_params(hw); 535 536 if (offset >= hw->eeprom.word_size) { 537 status = IXGBE_ERR_EEPROM; 538 goto out; 539 } 540 541 /* Prepare the EEPROM for writing */ 542 status = ixgbe_acquire_eeprom(hw); 543 544 if (status == IXGBE_SUCCESS) { 545 if (ixgbe_ready_eeprom(hw) != IXGBE_SUCCESS) { 546 ixgbe_release_eeprom(hw); 547 status = IXGBE_ERR_EEPROM; 548 } 549 } 550 551 if (status == IXGBE_SUCCESS) { 552 ixgbe_standby_eeprom(hw); 553 554 /* Send the WRITE ENABLE command (8 bit opcode ) */ 555 ixgbe_shift_out_eeprom_bits(hw, IXGBE_EEPROM_WREN_OPCODE_SPI, 556 IXGBE_EEPROM_OPCODE_BITS); 557 558 ixgbe_standby_eeprom(hw); 559 560 /* 561 * Some SPI eeproms use the 8th address bit embedded in the 562 * opcode 563 */ 564 if ((hw->eeprom.address_bits == 8) && (offset >= 128)) 565 write_opcode |= IXGBE_EEPROM_A8_OPCODE_SPI; 566 567 /* Send the Write command (8-bit opcode + addr) */ 568 ixgbe_shift_out_eeprom_bits(hw, write_opcode, 569 IXGBE_EEPROM_OPCODE_BITS); 570 ixgbe_shift_out_eeprom_bits(hw, (u16)(offset*2), 571 hw->eeprom.address_bits); 572 573 /* Send the data */ 574 data = (data >> 8) | (data << 8); 575 ixgbe_shift_out_eeprom_bits(hw, data, 16); 576 ixgbe_standby_eeprom(hw); 577 578 msec_delay(hw->eeprom.semaphore_delay); 579 /* Done with writing - release the EEPROM */ 580 ixgbe_release_eeprom(hw); 581 } 582 583 out: 584 return status; 585 } 586 587 /** 588 * ixgbe_read_eeprom_bit_bang_generic - Read EEPROM word using bit-bang 589 * @hw: pointer to hardware structure 590 * @offset: offset within the EEPROM to be read 591 * @data: read 16 bit value from EEPROM 592 * 593 * Reads 16 bit value from EEPROM through bit-bang method 594 **/ 595 s32 ixgbe_read_eeprom_bit_bang_generic(struct ixgbe_hw *hw, u16 offset, 596 u16 *data) 597 { 598 s32 status; 599 u16 word_in; 600 u8 read_opcode = IXGBE_EEPROM_READ_OPCODE_SPI; 601 602 hw->eeprom.ops.init_params(hw); 603 604 if (offset >= hw->eeprom.word_size) { 605 status = IXGBE_ERR_EEPROM; 606 goto out; 607 } 608 609 /* Prepare the EEPROM for reading */ 610 status = ixgbe_acquire_eeprom(hw); 611 612 if (status == IXGBE_SUCCESS) { 613 if (ixgbe_ready_eeprom(hw) != IXGBE_SUCCESS) { 614 ixgbe_release_eeprom(hw); 615 status = IXGBE_ERR_EEPROM; 616 } 617 } 618 619 if (status == IXGBE_SUCCESS) { 620 ixgbe_standby_eeprom(hw); 621 622 /* 623 * Some SPI eeproms use the 8th address bit embedded in the 624 * opcode 625 */ 626 if ((hw->eeprom.address_bits == 8) && (offset >= 128)) 627 read_opcode |= IXGBE_EEPROM_A8_OPCODE_SPI; 628 629 /* Send the READ command (opcode + addr) */ 630 ixgbe_shift_out_eeprom_bits(hw, read_opcode, 631 IXGBE_EEPROM_OPCODE_BITS); 632 ixgbe_shift_out_eeprom_bits(hw, (u16)(offset*2), 633 hw->eeprom.address_bits); 634 635 /* Read the data. */ 636 word_in = ixgbe_shift_in_eeprom_bits(hw, 16); 637 *data = (word_in >> 8) | (word_in << 8); 638 639 /* End this read operation */ 640 ixgbe_release_eeprom(hw); 641 } 642 643 out: 644 return status; 645 } 646 647 /** 648 * ixgbe_read_eeprom_generic - Read EEPROM word using EERD 649 * @hw: pointer to hardware structure 650 * @offset: offset of word in the EEPROM to read 651 * @data: word read from the EEPROM 652 * 653 * Reads a 16 bit word from the EEPROM using the EERD register. 654 **/ 655 s32 ixgbe_read_eeprom_generic(struct ixgbe_hw *hw, u16 offset, u16 *data) 656 { 657 u32 eerd; 658 s32 status; 659 660 hw->eeprom.ops.init_params(hw); 661 662 if (offset >= hw->eeprom.word_size) { 663 status = IXGBE_ERR_EEPROM; 664 goto out; 665 } 666 667 eerd = (offset << IXGBE_EEPROM_READ_ADDR_SHIFT) + 668 IXGBE_EEPROM_READ_REG_START; 669 670 IXGBE_WRITE_REG(hw, IXGBE_EERD, eerd); 671 status = ixgbe_poll_eeprom_eerd_done(hw); 672 673 if (status == IXGBE_SUCCESS) 674 *data = (IXGBE_READ_REG(hw, IXGBE_EERD) >> 675 IXGBE_EEPROM_READ_REG_DATA); 676 else 677 DEBUGOUT("Eeprom read timed out\n"); 678 679 out: 680 return status; 681 } 682 683 /** 684 * ixgbe_poll_eeprom_eerd_done - Poll EERD status 685 * @hw: pointer to hardware structure 686 * 687 * Polls the status bit (bit 1) of the EERD to determine when the read is done. 688 **/ 689 static s32 ixgbe_poll_eeprom_eerd_done(struct ixgbe_hw *hw) 690 { 691 u32 i; 692 u32 reg; 693 s32 status = IXGBE_ERR_EEPROM; 694 695 for (i = 0; i < IXGBE_EERD_ATTEMPTS; i++) { 696 reg = IXGBE_READ_REG(hw, IXGBE_EERD); 697 if (reg & IXGBE_EEPROM_READ_REG_DONE) { 698 status = IXGBE_SUCCESS; 699 break; 700 } 701 usec_delay(5); 702 } 703 return status; 704 } 705 706 /** 707 * ixgbe_acquire_eeprom - Acquire EEPROM using bit-bang 708 * @hw: pointer to hardware structure 709 * 710 * Prepares EEPROM for access using bit-bang method. This function should 711 * be called before issuing a command to the EEPROM. 712 **/ 713 static s32 ixgbe_acquire_eeprom(struct ixgbe_hw *hw) 714 { 715 s32 status = IXGBE_SUCCESS; 716 u32 eec; 717 u32 i; 718 719 if (ixgbe_acquire_swfw_sync(hw, IXGBE_GSSR_EEP_SM) != IXGBE_SUCCESS) 720 status = IXGBE_ERR_SWFW_SYNC; 721 722 if (status == IXGBE_SUCCESS) { 723 eec = IXGBE_READ_REG(hw, IXGBE_EEC); 724 725 /* Request EEPROM Access */ 726 eec |= IXGBE_EEC_REQ; 727 IXGBE_WRITE_REG(hw, IXGBE_EEC, eec); 728 729 for (i = 0; i < IXGBE_EEPROM_GRANT_ATTEMPTS; i++) { 730 eec = IXGBE_READ_REG(hw, IXGBE_EEC); 731 if (eec & IXGBE_EEC_GNT) 732 break; 733 usec_delay(5); 734 } 735 736 /* Release if grant not acquired */ 737 if (!(eec & IXGBE_EEC_GNT)) { 738 eec &= ~IXGBE_EEC_REQ; 739 IXGBE_WRITE_REG(hw, IXGBE_EEC, eec); 740 DEBUGOUT("Could not acquire EEPROM grant\n"); 741 742 ixgbe_release_swfw_sync(hw, IXGBE_GSSR_EEP_SM); 743 status = IXGBE_ERR_EEPROM; 744 } 745 } 746 747 /* Setup EEPROM for Read/Write */ 748 if (status == IXGBE_SUCCESS) { 749 /* Clear CS and SK */ 750 eec &= ~(IXGBE_EEC_CS | IXGBE_EEC_SK); 751 IXGBE_WRITE_REG(hw, IXGBE_EEC, eec); 752 IXGBE_WRITE_FLUSH(hw); 753 usec_delay(1); 754 } 755 return status; 756 } 757 758 /** 759 * ixgbe_get_eeprom_semaphore - Get hardware semaphore 760 * @hw: pointer to hardware structure 761 * 762 * Sets the hardware semaphores so EEPROM access can occur for bit-bang method 763 **/ 764 static s32 ixgbe_get_eeprom_semaphore(struct ixgbe_hw *hw) 765 { 766 s32 status = IXGBE_ERR_EEPROM; 767 u32 timeout; 768 u32 i; 769 u32 swsm; 770 771 /* Set timeout value based on size of EEPROM */ 772 timeout = hw->eeprom.word_size + 1; 773 774 /* Get SMBI software semaphore between device drivers first */ 775 for (i = 0; i < timeout; i++) { 776 /* 777 * If the SMBI bit is 0 when we read it, then the bit will be 778 * set and we have the semaphore 779 */ 780 swsm = IXGBE_READ_REG(hw, IXGBE_SWSM); 781 if (!(swsm & IXGBE_SWSM_SMBI)) { 782 status = IXGBE_SUCCESS; 783 break; 784 } 785 msec_delay(1); 786 } 787 788 /* Now get the semaphore between SW/FW through the SWESMBI bit */ 789 if (status == IXGBE_SUCCESS) { 790 for (i = 0; i < timeout; i++) { 791 swsm = IXGBE_READ_REG(hw, IXGBE_SWSM); 792 793 /* Set the SW EEPROM semaphore bit to request access */ 794 swsm |= IXGBE_SWSM_SWESMBI; 795 IXGBE_WRITE_REG(hw, IXGBE_SWSM, swsm); 796 797 /* 798 * If we set the bit successfully then we got the 799 * semaphore. 800 */ 801 swsm = IXGBE_READ_REG(hw, IXGBE_SWSM); 802 if (swsm & IXGBE_SWSM_SWESMBI) 803 break; 804 805 usec_delay(50); 806 } 807 808 /* 809 * Release semaphores and return error if SW EEPROM semaphore 810 * was not granted because we don't have access to the EEPROM 811 */ 812 if (i >= timeout) { 813 DEBUGOUT("Driver can't access the Eeprom - Semaphore " 814 "not granted.\n"); 815 ixgbe_release_eeprom_semaphore(hw); 816 status = IXGBE_ERR_EEPROM; 817 } 818 } 819 820 return status; 821 } 822 823 /** 824 * ixgbe_release_eeprom_semaphore - Release hardware semaphore 825 * @hw: pointer to hardware structure 826 * 827 * This function clears hardware semaphore bits. 828 **/ 829 static void ixgbe_release_eeprom_semaphore(struct ixgbe_hw *hw) 830 { 831 u32 swsm; 832 833 swsm = IXGBE_READ_REG(hw, IXGBE_SWSM); 834 835 /* Release both semaphores by writing 0 to the bits SWESMBI and SMBI */ 836 swsm &= ~(IXGBE_SWSM_SWESMBI | IXGBE_SWSM_SMBI); 837 IXGBE_WRITE_REG(hw, IXGBE_SWSM, swsm); 838 IXGBE_WRITE_FLUSH(hw); 839 } 840 841 /** 842 * ixgbe_ready_eeprom - Polls for EEPROM ready 843 * @hw: pointer to hardware structure 844 **/ 845 static s32 ixgbe_ready_eeprom(struct ixgbe_hw *hw) 846 { 847 s32 status = IXGBE_SUCCESS; 848 u16 i; 849 u8 spi_stat_reg; 850 851 /* 852 * Read "Status Register" repeatedly until the LSB is cleared. The 853 * EEPROM will signal that the command has been completed by clearing 854 * bit 0 of the internal status register. If it's not cleared within 855 * 5 milliseconds, then error out. 856 */ 857 for (i = 0; i < IXGBE_EEPROM_MAX_RETRY_SPI; i += 5) { 858 ixgbe_shift_out_eeprom_bits(hw, IXGBE_EEPROM_RDSR_OPCODE_SPI, 859 IXGBE_EEPROM_OPCODE_BITS); 860 spi_stat_reg = (u8)ixgbe_shift_in_eeprom_bits(hw, 8); 861 if (!(spi_stat_reg & IXGBE_EEPROM_STATUS_RDY_SPI)) 862 break; 863 864 usec_delay(5); 865 ixgbe_standby_eeprom(hw); 866 }; 867 868 /* 869 * On some parts, SPI write time could vary from 0-20mSec on 3.3V 870 * devices (and only 0-5mSec on 5V devices) 871 */ 872 if (i >= IXGBE_EEPROM_MAX_RETRY_SPI) { 873 DEBUGOUT("SPI EEPROM Status error\n"); 874 status = IXGBE_ERR_EEPROM; 875 } 876 877 return status; 878 } 879 880 /** 881 * ixgbe_standby_eeprom - Returns EEPROM to a "standby" state 882 * @hw: pointer to hardware structure 883 **/ 884 static void ixgbe_standby_eeprom(struct ixgbe_hw *hw) 885 { 886 u32 eec; 887 888 eec = IXGBE_READ_REG(hw, IXGBE_EEC); 889 890 /* Toggle CS to flush commands */ 891 eec |= IXGBE_EEC_CS; 892 IXGBE_WRITE_REG(hw, IXGBE_EEC, eec); 893 IXGBE_WRITE_FLUSH(hw); 894 usec_delay(1); 895 eec &= ~IXGBE_EEC_CS; 896 IXGBE_WRITE_REG(hw, IXGBE_EEC, eec); 897 IXGBE_WRITE_FLUSH(hw); 898 usec_delay(1); 899 } 900 901 /** 902 * ixgbe_shift_out_eeprom_bits - Shift data bits out to the EEPROM. 903 * @hw: pointer to hardware structure 904 * @data: data to send to the EEPROM 905 * @count: number of bits to shift out 906 **/ 907 static void ixgbe_shift_out_eeprom_bits(struct ixgbe_hw *hw, u16 data, 908 u16 count) 909 { 910 u32 eec; 911 u32 mask; 912 u32 i; 913 914 eec = IXGBE_READ_REG(hw, IXGBE_EEC); 915 916 /* 917 * Mask is used to shift "count" bits of "data" out to the EEPROM 918 * one bit at a time. Determine the starting bit based on count 919 */ 920 mask = 0x01 << (count - 1); 921 922 for (i = 0; i < count; i++) { 923 /* 924 * A "1" is shifted out to the EEPROM by setting bit "DI" to a 925 * "1", and then raising and then lowering the clock (the SK 926 * bit controls the clock input to the EEPROM). A "0" is 927 * shifted out to the EEPROM by setting "DI" to "0" and then 928 * raising and then lowering the clock. 929 */ 930 if (data & mask) 931 eec |= IXGBE_EEC_DI; 932 else 933 eec &= ~IXGBE_EEC_DI; 934 935 IXGBE_WRITE_REG(hw, IXGBE_EEC, eec); 936 IXGBE_WRITE_FLUSH(hw); 937 938 usec_delay(1); 939 940 ixgbe_raise_eeprom_clk(hw, &eec); 941 ixgbe_lower_eeprom_clk(hw, &eec); 942 943 /* 944 * Shift mask to signify next bit of data to shift in to the 945 * EEPROM 946 */ 947 mask = mask >> 1; 948 }; 949 950 /* We leave the "DI" bit set to "0" when we leave this routine. */ 951 eec &= ~IXGBE_EEC_DI; 952 IXGBE_WRITE_REG(hw, IXGBE_EEC, eec); 953 IXGBE_WRITE_FLUSH(hw); 954 } 955 956 /** 957 * ixgbe_shift_in_eeprom_bits - Shift data bits in from the EEPROM 958 * @hw: pointer to hardware structure 959 **/ 960 static u16 ixgbe_shift_in_eeprom_bits(struct ixgbe_hw *hw, u16 count) 961 { 962 u32 eec; 963 u32 i; 964 u16 data = 0; 965 966 /* 967 * In order to read a register from the EEPROM, we need to shift 968 * 'count' bits in from the EEPROM. Bits are "shifted in" by raising 969 * the clock input to the EEPROM (setting the SK bit), and then reading 970 * the value of the "DO" bit. During this "shifting in" process the 971 * "DI" bit should always be clear. 972 */ 973 eec = IXGBE_READ_REG(hw, IXGBE_EEC); 974 975 eec &= ~(IXGBE_EEC_DO | IXGBE_EEC_DI); 976 977 for (i = 0; i < count; i++) { 978 data = data << 1; 979 ixgbe_raise_eeprom_clk(hw, &eec); 980 981 eec = IXGBE_READ_REG(hw, IXGBE_EEC); 982 983 eec &= ~(IXGBE_EEC_DI); 984 if (eec & IXGBE_EEC_DO) 985 data |= 1; 986 987 ixgbe_lower_eeprom_clk(hw, &eec); 988 } 989 990 return data; 991 } 992 993 /** 994 * ixgbe_raise_eeprom_clk - Raises the EEPROM's clock input. 995 * @hw: pointer to hardware structure 996 * @eec: EEC register's current value 997 **/ 998 static void ixgbe_raise_eeprom_clk(struct ixgbe_hw *hw, u32 *eec) 999 { 1000 /* 1001 * Raise the clock input to the EEPROM 1002 * (setting the SK bit), then delay 1003 */ 1004 *eec = *eec | IXGBE_EEC_SK; 1005 IXGBE_WRITE_REG(hw, IXGBE_EEC, *eec); 1006 IXGBE_WRITE_FLUSH(hw); 1007 usec_delay(1); 1008 } 1009 1010 /** 1011 * ixgbe_lower_eeprom_clk - Lowers the EEPROM's clock input. 1012 * @hw: pointer to hardware structure 1013 * @eecd: EECD's current value 1014 **/ 1015 static void ixgbe_lower_eeprom_clk(struct ixgbe_hw *hw, u32 *eec) 1016 { 1017 /* 1018 * Lower the clock input to the EEPROM (clearing the SK bit), then 1019 * delay 1020 */ 1021 *eec = *eec & ~IXGBE_EEC_SK; 1022 IXGBE_WRITE_REG(hw, IXGBE_EEC, *eec); 1023 IXGBE_WRITE_FLUSH(hw); 1024 usec_delay(1); 1025 } 1026 1027 /** 1028 * ixgbe_release_eeprom - Release EEPROM, release semaphores 1029 * @hw: pointer to hardware structure 1030 **/ 1031 static void ixgbe_release_eeprom(struct ixgbe_hw *hw) 1032 { 1033 u32 eec; 1034 1035 eec = IXGBE_READ_REG(hw, IXGBE_EEC); 1036 1037 eec |= IXGBE_EEC_CS; /* Pull CS high */ 1038 eec &= ~IXGBE_EEC_SK; /* Lower SCK */ 1039 1040 IXGBE_WRITE_REG(hw, IXGBE_EEC, eec); 1041 IXGBE_WRITE_FLUSH(hw); 1042 1043 usec_delay(1); 1044 1045 /* Stop requesting EEPROM access */ 1046 eec &= ~IXGBE_EEC_REQ; 1047 IXGBE_WRITE_REG(hw, IXGBE_EEC, eec); 1048 1049 ixgbe_release_swfw_sync(hw, IXGBE_GSSR_EEP_SM); 1050 } 1051 1052 /** 1053 * ixgbe_calc_eeprom_checksum - Calculates and returns the checksum 1054 * @hw: pointer to hardware structure 1055 **/ 1056 static u16 ixgbe_calc_eeprom_checksum(struct ixgbe_hw *hw) 1057 { 1058 u16 i; 1059 u16 j; 1060 u16 checksum = 0; 1061 u16 length = 0; 1062 u16 pointer = 0; 1063 u16 word = 0; 1064 1065 /* Include 0x0-0x3F in the checksum */ 1066 for (i = 0; i < IXGBE_EEPROM_CHECKSUM; i++) { 1067 if (hw->eeprom.ops.read(hw, i, &word) != IXGBE_SUCCESS) { 1068 DEBUGOUT("EEPROM read failed\n"); 1069 break; 1070 } 1071 checksum += word; 1072 } 1073 1074 /* Include all data from pointers except for the fw pointer */ 1075 for (i = IXGBE_PCIE_ANALOG_PTR; i < IXGBE_FW_PTR; i++) { 1076 hw->eeprom.ops.read(hw, i, &pointer); 1077 1078 /* Make sure the pointer seems valid */ 1079 if (pointer != 0xFFFF && pointer != 0) { 1080 hw->eeprom.ops.read(hw, pointer, &length); 1081 1082 if (length != 0xFFFF && length != 0) { 1083 for (j = pointer+1; j <= pointer+length; j++) { 1084 hw->eeprom.ops.read(hw, j, &word); 1085 checksum += word; 1086 } 1087 } 1088 } 1089 } 1090 1091 checksum = (u16)IXGBE_EEPROM_SUM - checksum; 1092 1093 return checksum; 1094 } 1095 1096 /** 1097 * ixgbe_validate_eeprom_checksum_generic - Validate EEPROM checksum 1098 * @hw: pointer to hardware structure 1099 * @checksum_val: calculated checksum 1100 * 1101 * Performs checksum calculation and validates the EEPROM checksum. If the 1102 * caller does not need checksum_val, the value can be NULL. 1103 **/ 1104 s32 ixgbe_validate_eeprom_checksum_generic(struct ixgbe_hw *hw, 1105 u16 *checksum_val) 1106 { 1107 s32 status; 1108 u16 checksum; 1109 u16 read_checksum = 0; 1110 1111 /* 1112 * Read the first word from the EEPROM. If this times out or fails, do 1113 * not continue or we could be in for a very long wait while every 1114 * EEPROM read fails 1115 */ 1116 status = hw->eeprom.ops.read(hw, 0, &checksum); 1117 1118 if (status == IXGBE_SUCCESS) { 1119 checksum = ixgbe_calc_eeprom_checksum(hw); 1120 1121 hw->eeprom.ops.read(hw, IXGBE_EEPROM_CHECKSUM, &read_checksum); 1122 1123 /* 1124 * Verify read checksum from EEPROM is the same as 1125 * calculated checksum 1126 */ 1127 if (read_checksum != checksum) 1128 status = IXGBE_ERR_EEPROM_CHECKSUM; 1129 1130 /* If the user cares, return the calculated checksum */ 1131 if (checksum_val) 1132 *checksum_val = checksum; 1133 } else { 1134 DEBUGOUT("EEPROM read failed\n"); 1135 } 1136 1137 return status; 1138 } 1139 1140 /** 1141 * ixgbe_update_eeprom_checksum_generic - Updates the EEPROM checksum 1142 * @hw: pointer to hardware structure 1143 **/ 1144 s32 ixgbe_update_eeprom_checksum_generic(struct ixgbe_hw *hw) 1145 { 1146 s32 status; 1147 u16 checksum; 1148 1149 /* 1150 * Read the first word from the EEPROM. If this times out or fails, do 1151 * not continue or we could be in for a very long wait while every 1152 * EEPROM read fails 1153 */ 1154 status = hw->eeprom.ops.read(hw, 0, &checksum); 1155 1156 if (status == IXGBE_SUCCESS) { 1157 checksum = ixgbe_calc_eeprom_checksum(hw); 1158 status = hw->eeprom.ops.write(hw, IXGBE_EEPROM_CHECKSUM, 1159 checksum); 1160 } else { 1161 DEBUGOUT("EEPROM read failed\n"); 1162 } 1163 1164 return status; 1165 } 1166 1167 /** 1168 * ixgbe_validate_mac_addr - Validate MAC address 1169 * @mac_addr: pointer to MAC address. 1170 * 1171 * Tests a MAC address to ensure it is a valid Individual Address 1172 **/ 1173 s32 ixgbe_validate_mac_addr(u8 *mac_addr) 1174 { 1175 s32 status = IXGBE_SUCCESS; 1176 1177 /* Make sure it is not a multicast address */ 1178 if (IXGBE_IS_MULTICAST(mac_addr)) { 1179 DEBUGOUT("MAC address is multicast\n"); 1180 status = IXGBE_ERR_INVALID_MAC_ADDR; 1181 /* Not a broadcast address */ 1182 } else if (IXGBE_IS_BROADCAST(mac_addr)) { 1183 DEBUGOUT("MAC address is broadcast\n"); 1184 status = IXGBE_ERR_INVALID_MAC_ADDR; 1185 /* Reject the zero address */ 1186 } else if (mac_addr[0] == 0 && mac_addr[1] == 0 && mac_addr[2] == 0 && 1187 mac_addr[3] == 0 && mac_addr[4] == 0 && mac_addr[5] == 0) { 1188 DEBUGOUT("MAC address is all zeros\n"); 1189 status = IXGBE_ERR_INVALID_MAC_ADDR; 1190 } 1191 return status; 1192 } 1193 1194 /** 1195 * ixgbe_set_rar_generic - Set Rx address register 1196 * @hw: pointer to hardware structure 1197 * @index: Receive address register to write 1198 * @addr: Address to put into receive address register 1199 * @vmdq: VMDq "set" or "pool" index 1200 * @enable_addr: set flag that address is active 1201 * 1202 * Puts an ethernet address into a receive address register. 1203 **/ 1204 s32 ixgbe_set_rar_generic(struct ixgbe_hw *hw, u32 index, u8 *addr, u32 vmdq, 1205 u32 enable_addr) 1206 { 1207 u32 rar_low, rar_high; 1208 u32 rar_entries = hw->mac.num_rar_entries; 1209 1210 /* setup VMDq pool selection before this RAR gets enabled */ 1211 hw->mac.ops.set_vmdq(hw, index, vmdq); 1212 1213 /* Make sure we are using a valid rar index range */ 1214 if (index < rar_entries) { 1215 /* 1216 * HW expects these in little endian so we reverse the byte 1217 * order from network order (big endian) to little endian 1218 */ 1219 rar_low = ((u32)addr[0] | 1220 ((u32)addr[1] << 8) | 1221 ((u32)addr[2] << 16) | 1222 ((u32)addr[3] << 24)); 1223 /* 1224 * Some parts put the VMDq setting in the extra RAH bits, 1225 * so save everything except the lower 16 bits that hold part 1226 * of the address and the address valid bit. 1227 */ 1228 rar_high = IXGBE_READ_REG(hw, IXGBE_RAH(index)); 1229 rar_high &= ~(0x0000FFFF | IXGBE_RAH_AV); 1230 rar_high |= ((u32)addr[4] | ((u32)addr[5] << 8)); 1231 1232 if (enable_addr != 0) 1233 rar_high |= IXGBE_RAH_AV; 1234 1235 IXGBE_WRITE_REG(hw, IXGBE_RAL(index), rar_low); 1236 IXGBE_WRITE_REG(hw, IXGBE_RAH(index), rar_high); 1237 } else { 1238 DEBUGOUT1("RAR index %d is out of range.\n", index); 1239 } 1240 1241 return IXGBE_SUCCESS; 1242 } 1243 1244 /** 1245 * ixgbe_clear_rar_generic - Remove Rx address register 1246 * @hw: pointer to hardware structure 1247 * @index: Receive address register to write 1248 * 1249 * Clears an ethernet address from a receive address register. 1250 **/ 1251 s32 ixgbe_clear_rar_generic(struct ixgbe_hw *hw, u32 index) 1252 { 1253 u32 rar_high; 1254 u32 rar_entries = hw->mac.num_rar_entries; 1255 1256 /* Make sure we are using a valid rar index range */ 1257 if (index < rar_entries) { 1258 /* 1259 * Some parts put the VMDq setting in the extra RAH bits, 1260 * so save everything except the lower 16 bits that hold part 1261 * of the address and the address valid bit. 1262 */ 1263 rar_high = IXGBE_READ_REG(hw, IXGBE_RAH(index)); 1264 rar_high &= ~(0x0000FFFF | IXGBE_RAH_AV); 1265 1266 IXGBE_WRITE_REG(hw, IXGBE_RAL(index), 0); 1267 IXGBE_WRITE_REG(hw, IXGBE_RAH(index), rar_high); 1268 } else { 1269 DEBUGOUT1("RAR index %d is out of range.\n", index); 1270 } 1271 1272 /* clear VMDq pool/queue selection for this RAR */ 1273 hw->mac.ops.clear_vmdq(hw, index, IXGBE_CLEAR_VMDQ_ALL); 1274 1275 return IXGBE_SUCCESS; 1276 } 1277 1278 /** 1279 * ixgbe_enable_rar - Enable Rx address register 1280 * @hw: pointer to hardware structure 1281 * @index: index into the RAR table 1282 * 1283 * Enables the select receive address register. 1284 **/ 1285 static void ixgbe_enable_rar(struct ixgbe_hw *hw, u32 index) 1286 { 1287 u32 rar_high; 1288 1289 rar_high = IXGBE_READ_REG(hw, IXGBE_RAH(index)); 1290 rar_high |= IXGBE_RAH_AV; 1291 IXGBE_WRITE_REG(hw, IXGBE_RAH(index), rar_high); 1292 } 1293 1294 /** 1295 * ixgbe_disable_rar - Disable Rx address register 1296 * @hw: pointer to hardware structure 1297 * @index: index into the RAR table 1298 * 1299 * Disables the select receive address register. 1300 **/ 1301 static void ixgbe_disable_rar(struct ixgbe_hw *hw, u32 index) 1302 { 1303 u32 rar_high; 1304 1305 rar_high = IXGBE_READ_REG(hw, IXGBE_RAH(index)); 1306 rar_high &= (~IXGBE_RAH_AV); 1307 IXGBE_WRITE_REG(hw, IXGBE_RAH(index), rar_high); 1308 } 1309 1310 /** 1311 * ixgbe_init_rx_addrs_generic - Initializes receive address filters. 1312 * @hw: pointer to hardware structure 1313 * 1314 * Places the MAC address in receive address register 0 and clears the rest 1315 * of the receive address registers. Clears the multicast table. Assumes 1316 * the receiver is in reset when the routine is called. 1317 **/ 1318 s32 ixgbe_init_rx_addrs_generic(struct ixgbe_hw *hw) 1319 { 1320 u32 i; 1321 u32 rar_entries = hw->mac.num_rar_entries; 1322 1323 /* 1324 * If the current mac address is valid, assume it is a software override 1325 * to the permanent address. 1326 * Otherwise, use the permanent address from the eeprom. 1327 */ 1328 if (ixgbe_validate_mac_addr(hw->mac.addr) == 1329 IXGBE_ERR_INVALID_MAC_ADDR) { 1330 /* Get the MAC address from the RAR0 for later reference */ 1331 hw->mac.ops.get_mac_addr(hw, hw->mac.addr); 1332 1333 DEBUGOUT3(" Keeping Current RAR0 Addr =%.2X %.2X %.2X ", 1334 hw->mac.addr[0], hw->mac.addr[1], 1335 hw->mac.addr[2]); 1336 DEBUGOUT3("%.2X %.2X %.2X\n", hw->mac.addr[3], 1337 hw->mac.addr[4], hw->mac.addr[5]); 1338 } else { 1339 /* Setup the receive address. */ 1340 DEBUGOUT("Overriding MAC Address in RAR[0]\n"); 1341 DEBUGOUT3(" New MAC Addr =%.2X %.2X %.2X ", 1342 hw->mac.addr[0], hw->mac.addr[1], 1343 hw->mac.addr[2]); 1344 DEBUGOUT3("%.2X %.2X %.2X\n", hw->mac.addr[3], 1345 hw->mac.addr[4], hw->mac.addr[5]); 1346 1347 hw->mac.ops.set_rar(hw, 0, hw->mac.addr, 0, IXGBE_RAH_AV); 1348 } 1349 hw->addr_ctrl.overflow_promisc = 0; 1350 1351 hw->addr_ctrl.rar_used_count = 1; 1352 1353 /* Zero out the other receive addresses. */ 1354 DEBUGOUT1("Clearing RAR[1-%d]\n", rar_entries - 1); 1355 for (i = 1; i < rar_entries; i++) { 1356 IXGBE_WRITE_REG(hw, IXGBE_RAL(i), 0); 1357 IXGBE_WRITE_REG(hw, IXGBE_RAH(i), 0); 1358 } 1359 1360 /* Clear the MTA */ 1361 hw->addr_ctrl.mc_addr_in_rar_count = 0; 1362 hw->addr_ctrl.mta_in_use = 0; 1363 IXGBE_WRITE_REG(hw, IXGBE_MCSTCTRL, hw->mac.mc_filter_type); 1364 1365 DEBUGOUT(" Clearing MTA\n"); 1366 for (i = 0; i < hw->mac.mcft_size; i++) 1367 IXGBE_WRITE_REG(hw, IXGBE_MTA(i), 0); 1368 1369 ixgbe_init_uta_tables(hw); 1370 1371 return IXGBE_SUCCESS; 1372 } 1373 1374 /** 1375 * ixgbe_add_uc_addr - Adds a secondary unicast address. 1376 * @hw: pointer to hardware structure 1377 * @addr: new address 1378 * 1379 * Adds it to unused receive address register or goes into promiscuous mode. 1380 **/ 1381 void ixgbe_add_uc_addr(struct ixgbe_hw *hw, u8 *addr, u32 vmdq) 1382 { 1383 u32 rar_entries = hw->mac.num_rar_entries; 1384 u32 rar; 1385 1386 DEBUGOUT6(" UC Addr = %.2X %.2X %.2X %.2X %.2X %.2X\n", 1387 addr[0], addr[1], addr[2], addr[3], addr[4], addr[5]); 1388 1389 /* 1390 * Place this address in the RAR if there is room, 1391 * else put the controller into promiscuous mode 1392 */ 1393 if (hw->addr_ctrl.rar_used_count < rar_entries) { 1394 rar = hw->addr_ctrl.rar_used_count - 1395 hw->addr_ctrl.mc_addr_in_rar_count; 1396 hw->mac.ops.set_rar(hw, rar, addr, vmdq, IXGBE_RAH_AV); 1397 DEBUGOUT1("Added a secondary address to RAR[%d]\n", rar); 1398 hw->addr_ctrl.rar_used_count++; 1399 } else { 1400 hw->addr_ctrl.overflow_promisc++; 1401 } 1402 1403 DEBUGOUT("ixgbe_add_uc_addr Complete\n"); 1404 } 1405 1406 /** 1407 * ixgbe_update_uc_addr_list_generic - Updates MAC list of secondary addresses 1408 * @hw: pointer to hardware structure 1409 * @addr_list: the list of new addresses 1410 * @addr_count: number of addresses 1411 * @next: iterator function to walk the address list 1412 * 1413 * The given list replaces any existing list. Clears the secondary addrs from 1414 * receive address registers. Uses unused receive address registers for the 1415 * first secondary addresses, and falls back to promiscuous mode as needed. 1416 * 1417 * Drivers using secondary unicast addresses must set user_set_promisc when 1418 * manually putting the device into promiscuous mode. 1419 **/ 1420 s32 ixgbe_update_uc_addr_list_generic(struct ixgbe_hw *hw, u8 *addr_list, 1421 u32 addr_count, ixgbe_mc_addr_itr next) 1422 { 1423 u8 *addr; 1424 u32 i; 1425 u32 old_promisc_setting = hw->addr_ctrl.overflow_promisc; 1426 u32 uc_addr_in_use; 1427 u32 fctrl; 1428 u32 vmdq; 1429 1430 /* 1431 * Clear accounting of old secondary address list, 1432 * don't count RAR[0] 1433 */ 1434 uc_addr_in_use = hw->addr_ctrl.rar_used_count - 1435 hw->addr_ctrl.mc_addr_in_rar_count - 1; 1436 hw->addr_ctrl.rar_used_count -= uc_addr_in_use; 1437 hw->addr_ctrl.overflow_promisc = 0; 1438 1439 /* Zero out the other receive addresses */ 1440 DEBUGOUT1("Clearing RAR[1-%d]\n", uc_addr_in_use); 1441 for (i = 1; i <= uc_addr_in_use; i++) { 1442 IXGBE_WRITE_REG(hw, IXGBE_RAL(i), 0); 1443 IXGBE_WRITE_REG(hw, IXGBE_RAH(i), 0); 1444 } 1445 1446 /* Add the new addresses */ 1447 for (i = 0; i < addr_count; i++) { 1448 DEBUGOUT(" Adding the secondary addresses:\n"); 1449 addr = next(hw, &addr_list, &vmdq); 1450 ixgbe_add_uc_addr(hw, addr, vmdq); 1451 } 1452 1453 if (hw->addr_ctrl.overflow_promisc) { 1454 /* enable promisc if not already in overflow or set by user */ 1455 if (!old_promisc_setting && !hw->addr_ctrl.user_set_promisc) { 1456 DEBUGOUT( " Entering address overflow promisc mode\n"); 1457 fctrl = IXGBE_READ_REG(hw, IXGBE_FCTRL); 1458 fctrl |= IXGBE_FCTRL_UPE; 1459 IXGBE_WRITE_REG(hw, IXGBE_FCTRL, fctrl); 1460 } 1461 } else { 1462 /* only disable if set by overflow, not by user */ 1463 if (old_promisc_setting && !hw->addr_ctrl.user_set_promisc) { 1464 DEBUGOUT(" Leaving address overflow promisc mode\n"); 1465 fctrl = IXGBE_READ_REG(hw, IXGBE_FCTRL); 1466 fctrl &= ~IXGBE_FCTRL_UPE; 1467 IXGBE_WRITE_REG(hw, IXGBE_FCTRL, fctrl); 1468 } 1469 } 1470 1471 DEBUGOUT("ixgbe_update_uc_addr_list_generic Complete\n"); 1472 return IXGBE_SUCCESS; 1473 } 1474 1475 /** 1476 * ixgbe_mta_vector - Determines bit-vector in multicast table to set 1477 * @hw: pointer to hardware structure 1478 * @mc_addr: the multicast address 1479 * 1480 * Extracts the 12 bits, from a multicast address, to determine which 1481 * bit-vector to set in the multicast table. The hardware uses 12 bits, from 1482 * incoming rx multicast addresses, to determine the bit-vector to check in 1483 * the MTA. Which of the 4 combination, of 12-bits, the hardware uses is set 1484 * by the MO field of the MCSTCTRL. The MO field is set during initialization 1485 * to mc_filter_type. 1486 **/ 1487 static s32 ixgbe_mta_vector(struct ixgbe_hw *hw, u8 *mc_addr) 1488 { 1489 u32 vector = 0; 1490 1491 switch (hw->mac.mc_filter_type) { 1492 case 0: /* use bits [47:36] of the address */ 1493 vector = ((mc_addr[4] >> 4) | (((u16)mc_addr[5]) << 4)); 1494 break; 1495 case 1: /* use bits [46:35] of the address */ 1496 vector = ((mc_addr[4] >> 3) | (((u16)mc_addr[5]) << 5)); 1497 break; 1498 case 2: /* use bits [45:34] of the address */ 1499 vector = ((mc_addr[4] >> 2) | (((u16)mc_addr[5]) << 6)); 1500 break; 1501 case 3: /* use bits [43:32] of the address */ 1502 vector = ((mc_addr[4]) | (((u16)mc_addr[5]) << 8)); 1503 break; 1504 default: /* Invalid mc_filter_type */ 1505 DEBUGOUT("MC filter type param set incorrectly\n"); 1506 ASSERT(0); 1507 break; 1508 } 1509 1510 /* vector can only be 12-bits or boundary will be exceeded */ 1511 vector &= 0xFFF; 1512 return vector; 1513 } 1514 1515 /** 1516 * ixgbe_set_mta - Set bit-vector in multicast table 1517 * @hw: pointer to hardware structure 1518 * @hash_value: Multicast address hash value 1519 * 1520 * Sets the bit-vector in the multicast table. 1521 **/ 1522 void ixgbe_set_mta(struct ixgbe_hw *hw, u8 *mc_addr) 1523 { 1524 u32 vector; 1525 u32 vector_bit; 1526 u32 vector_reg; 1527 u32 mta_reg; 1528 1529 hw->addr_ctrl.mta_in_use++; 1530 1531 vector = ixgbe_mta_vector(hw, mc_addr); 1532 DEBUGOUT1(" bit-vector = 0x%03X\n", vector); 1533 1534 /* 1535 * The MTA is a register array of 128 32-bit registers. It is treated 1536 * like an array of 4096 bits. We want to set bit 1537 * BitArray[vector_value]. So we figure out what register the bit is 1538 * in, read it, OR in the new bit, then write back the new value. The 1539 * register is determined by the upper 7 bits of the vector value and 1540 * the bit within that register are determined by the lower 5 bits of 1541 * the value. 1542 */ 1543 vector_reg = (vector >> 5) & 0x7F; 1544 vector_bit = vector & 0x1F; 1545 mta_reg = IXGBE_READ_REG(hw, IXGBE_MTA(vector_reg)); 1546 mta_reg |= (1 << vector_bit); 1547 IXGBE_WRITE_REG(hw, IXGBE_MTA(vector_reg), mta_reg); 1548 } 1549 1550 /** 1551 * ixgbe_add_mc_addr - Adds a multicast address. 1552 * @hw: pointer to hardware structure 1553 * @mc_addr: new multicast address 1554 * 1555 * Adds it to unused receive address register or to the multicast table. 1556 **/ 1557 void ixgbe_add_mc_addr(struct ixgbe_hw *hw, u8 *mc_addr) 1558 { 1559 u32 rar_entries = hw->mac.num_rar_entries; 1560 u32 rar; 1561 1562 DEBUGOUT6(" MC Addr =%.2X %.2X %.2X %.2X %.2X %.2X\n", 1563 mc_addr[0], mc_addr[1], mc_addr[2], 1564 mc_addr[3], mc_addr[4], mc_addr[5]); 1565 1566 /* 1567 * Place this multicast address in the RAR if there is room, 1568 * else put it in the MTA 1569 */ 1570 if (hw->addr_ctrl.rar_used_count < rar_entries) { 1571 /* use RAR from the end up for multicast */ 1572 rar = rar_entries - hw->addr_ctrl.mc_addr_in_rar_count - 1; 1573 hw->mac.ops.set_rar(hw, rar, mc_addr, 0, IXGBE_RAH_AV); 1574 DEBUGOUT1("Added a multicast address to RAR[%d]\n", rar); 1575 hw->addr_ctrl.rar_used_count++; 1576 hw->addr_ctrl.mc_addr_in_rar_count++; 1577 } else { 1578 ixgbe_set_mta(hw, mc_addr); 1579 } 1580 1581 DEBUGOUT("ixgbe_add_mc_addr Complete\n"); 1582 } 1583 1584 /** 1585 * ixgbe_update_mc_addr_list_generic - Updates MAC list of multicast addresses 1586 * @hw: pointer to hardware structure 1587 * @mc_addr_list: the list of new multicast addresses 1588 * @mc_addr_count: number of addresses 1589 * @next: iterator function to walk the multicast address list 1590 * 1591 * The given list replaces any existing list. Clears the MC addrs from receive 1592 * address registers and the multicast table. Uses unused receive address 1593 * registers for the first multicast addresses, and hashes the rest into the 1594 * multicast table. 1595 **/ 1596 s32 ixgbe_update_mc_addr_list_generic(struct ixgbe_hw *hw, u8 *mc_addr_list, 1597 u32 mc_addr_count, ixgbe_mc_addr_itr next) 1598 { 1599 u32 i; 1600 u32 rar_entries = hw->mac.num_rar_entries; 1601 u32 vmdq; 1602 1603 /* 1604 * Set the new number of MC addresses that we are being requested to 1605 * use. 1606 */ 1607 hw->addr_ctrl.num_mc_addrs = mc_addr_count; 1608 hw->addr_ctrl.rar_used_count -= hw->addr_ctrl.mc_addr_in_rar_count; 1609 hw->addr_ctrl.mc_addr_in_rar_count = 0; 1610 hw->addr_ctrl.mta_in_use = 0; 1611 1612 /* Zero out the other receive addresses. */ 1613 DEBUGOUT2("Clearing RAR[%d-%d]\n", hw->addr_ctrl.rar_used_count, 1614 rar_entries - 1); 1615 for (i = hw->addr_ctrl.rar_used_count; i < rar_entries; i++) { 1616 IXGBE_WRITE_REG(hw, IXGBE_RAL(i), 0); 1617 IXGBE_WRITE_REG(hw, IXGBE_RAH(i), 0); 1618 } 1619 1620 /* Clear the MTA */ 1621 DEBUGOUT(" Clearing MTA\n"); 1622 for (i = 0; i < hw->mac.mcft_size; i++) 1623 IXGBE_WRITE_REG(hw, IXGBE_MTA(i), 0); 1624 1625 /* Add the new addresses */ 1626 for (i = 0; i < mc_addr_count; i++) { 1627 DEBUGOUT(" Adding the multicast addresses:\n"); 1628 ixgbe_add_mc_addr(hw, next(hw, &mc_addr_list, &vmdq)); 1629 } 1630 1631 /* Enable mta */ 1632 if (hw->addr_ctrl.mta_in_use > 0) 1633 IXGBE_WRITE_REG(hw, IXGBE_MCSTCTRL, 1634 IXGBE_MCSTCTRL_MFE | hw->mac.mc_filter_type); 1635 1636 DEBUGOUT("ixgbe_update_mc_addr_list_generic Complete\n"); 1637 return IXGBE_SUCCESS; 1638 } 1639 1640 /** 1641 * ixgbe_enable_mc_generic - Enable multicast address in RAR 1642 * @hw: pointer to hardware structure 1643 * 1644 * Enables multicast address in RAR and the use of the multicast hash table. 1645 **/ 1646 s32 ixgbe_enable_mc_generic(struct ixgbe_hw *hw) 1647 { 1648 u32 i; 1649 u32 rar_entries = hw->mac.num_rar_entries; 1650 struct ixgbe_addr_filter_info *a = &hw->addr_ctrl; 1651 1652 if (a->mc_addr_in_rar_count > 0) 1653 for (i = (rar_entries - a->mc_addr_in_rar_count); 1654 i < rar_entries; i++) 1655 ixgbe_enable_rar(hw, i); 1656 1657 if (a->mta_in_use > 0) 1658 IXGBE_WRITE_REG(hw, IXGBE_MCSTCTRL, IXGBE_MCSTCTRL_MFE | 1659 hw->mac.mc_filter_type); 1660 1661 return IXGBE_SUCCESS; 1662 } 1663 1664 /** 1665 * ixgbe_disable_mc_generic - Disable multicast address in RAR 1666 * @hw: pointer to hardware structure 1667 * 1668 * Disables multicast address in RAR and the use of the multicast hash table. 1669 **/ 1670 s32 ixgbe_disable_mc_generic(struct ixgbe_hw *hw) 1671 { 1672 u32 i; 1673 u32 rar_entries = hw->mac.num_rar_entries; 1674 struct ixgbe_addr_filter_info *a = &hw->addr_ctrl; 1675 1676 if (a->mc_addr_in_rar_count > 0) 1677 for (i = (rar_entries - a->mc_addr_in_rar_count); 1678 i < rar_entries; i++) 1679 ixgbe_disable_rar(hw, i); 1680 1681 if (a->mta_in_use > 0) 1682 IXGBE_WRITE_REG(hw, IXGBE_MCSTCTRL, hw->mac.mc_filter_type); 1683 1684 return IXGBE_SUCCESS; 1685 } 1686 1687 /** 1688 * ixgbe_disable_pcie_master - Disable PCI-express master access 1689 * @hw: pointer to hardware structure 1690 * 1691 * Disables PCI-Express master access and verifies there are no pending 1692 * requests. IXGBE_ERR_MASTER_REQUESTS_PENDING is returned if master disable 1693 * bit hasn't caused the master requests to be disabled, else IXGBE_SUCCESS 1694 * is returned signifying master requests disabled. 1695 **/ 1696 s32 ixgbe_disable_pcie_master(struct ixgbe_hw *hw) 1697 { 1698 u32 i; 1699 u32 reg_val; 1700 u32 number_of_queues; 1701 s32 status = IXGBE_ERR_MASTER_REQUESTS_PENDING; 1702 1703 /* Disable the receive unit by stopping each queue */ 1704 number_of_queues = hw->mac.max_rx_queues; 1705 for (i = 0; i < number_of_queues; i++) { 1706 reg_val = IXGBE_READ_REG(hw, IXGBE_RXDCTL(i)); 1707 if (reg_val & IXGBE_RXDCTL_ENABLE) { 1708 reg_val &= ~IXGBE_RXDCTL_ENABLE; 1709 IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(i), reg_val); 1710 } 1711 } 1712 1713 reg_val = IXGBE_READ_REG(hw, IXGBE_CTRL); 1714 reg_val |= IXGBE_CTRL_GIO_DIS; 1715 IXGBE_WRITE_REG(hw, IXGBE_CTRL, reg_val); 1716 1717 for (i = 0; i < IXGBE_PCI_MASTER_DISABLE_TIMEOUT; i++) { 1718 if (!(IXGBE_READ_REG(hw, IXGBE_STATUS) & IXGBE_STATUS_GIO)) { 1719 status = IXGBE_SUCCESS; 1720 break; 1721 } 1722 usec_delay(100); 1723 } 1724 1725 return status; 1726 } 1727 1728 1729 /** 1730 * ixgbe_acquire_swfw_sync - Acquire SWFW semaphore 1731 * @hw: pointer to hardware structure 1732 * @mask: Mask to specify which semaphore to acquire 1733 * 1734 * Acquires the SWFW semaphore thought the GSSR register for the specified 1735 * function (CSR, PHY0, PHY1, EEPROM, Flash) 1736 **/ 1737 s32 ixgbe_acquire_swfw_sync(struct ixgbe_hw *hw, u16 mask) 1738 { 1739 u32 gssr; 1740 u32 swmask = mask; 1741 u32 fwmask = mask << 5; 1742 s32 timeout = 200; 1743 1744 while (timeout) { 1745 if (ixgbe_get_eeprom_semaphore(hw)) 1746 return -IXGBE_ERR_SWFW_SYNC; 1747 1748 gssr = IXGBE_READ_REG(hw, IXGBE_GSSR); 1749 if (!(gssr & (fwmask | swmask))) 1750 break; 1751 1752 /* 1753 * Firmware currently using resource (fwmask) or other software 1754 * thread currently using resource (swmask) 1755 */ 1756 ixgbe_release_eeprom_semaphore(hw); 1757 msec_delay(5); 1758 timeout--; 1759 } 1760 1761 if (!timeout) { 1762 DEBUGOUT("Driver can't access resource, GSSR timeout.\n"); 1763 return -IXGBE_ERR_SWFW_SYNC; 1764 } 1765 1766 gssr |= swmask; 1767 IXGBE_WRITE_REG(hw, IXGBE_GSSR, gssr); 1768 1769 ixgbe_release_eeprom_semaphore(hw); 1770 return IXGBE_SUCCESS; 1771 } 1772 1773 /** 1774 * ixgbe_release_swfw_sync - Release SWFW semaphore 1775 * @hw: pointer to hardware structure 1776 * @mask: Mask to specify which semaphore to release 1777 * 1778 * Releases the SWFW semaphore thought the GSSR register for the specified 1779 * function (CSR, PHY0, PHY1, EEPROM, Flash) 1780 **/ 1781 void ixgbe_release_swfw_sync(struct ixgbe_hw *hw, u16 mask) 1782 { 1783 u32 gssr; 1784 u32 swmask = mask; 1785 1786 ixgbe_get_eeprom_semaphore(hw); 1787 1788 gssr = IXGBE_READ_REG(hw, IXGBE_GSSR); 1789 gssr &= ~swmask; 1790 IXGBE_WRITE_REG(hw, IXGBE_GSSR, gssr); 1791 1792 ixgbe_release_eeprom_semaphore(hw); 1793 } 1794 1795 /** 1796 * ixgbe_read_analog_reg8_generic - Reads 8 bit Atlas analog register 1797 * @hw: pointer to hardware structure 1798 * @reg: analog register to read 1799 * @val: read value 1800 * 1801 * Performs read operation to Atlas analog register specified. 1802 **/ 1803 s32 ixgbe_read_analog_reg8_generic(struct ixgbe_hw *hw, u32 reg, u8 *val) 1804 { 1805 u32 atlas_ctl; 1806 1807 IXGBE_WRITE_REG(hw, IXGBE_ATLASCTL, IXGBE_ATLASCTL_WRITE_CMD | (reg << 8)); 1808 IXGBE_WRITE_FLUSH(hw); 1809 usec_delay(10); 1810 atlas_ctl = IXGBE_READ_REG(hw, IXGBE_ATLASCTL); 1811 *val = (u8)atlas_ctl; 1812 1813 return IXGBE_SUCCESS; 1814 } 1815 1816 /** 1817 * ixgbe_write_analog_reg8_generic - Writes 8 bit Atlas analog register 1818 * @hw: pointer to hardware structure 1819 * @reg: atlas register to write 1820 * @val: value to write 1821 * 1822 * Performs write operation to Atlas analog register specified. 1823 **/ 1824 s32 ixgbe_write_analog_reg8_generic(struct ixgbe_hw *hw, u32 reg, u8 val) 1825 { 1826 u32 atlas_ctl; 1827 1828 atlas_ctl = (reg << 8) | val; 1829 IXGBE_WRITE_REG(hw, IXGBE_ATLASCTL, atlas_ctl); 1830 IXGBE_WRITE_FLUSH(hw); 1831 usec_delay(10); 1832 1833 return IXGBE_SUCCESS; 1834 } 1835 1836