1 /****************************************************************************** 2 3 Copyright (c) 2001-2009, Intel Corporation 4 All rights reserved. 5 6 Redistribution and use in source and binary forms, with or without 7 modification, are permitted provided that the following conditions are met: 8 9 1. Redistributions of source code must retain the above copyright notice, 10 this list of conditions and the following disclaimer. 11 12 2. Redistributions in binary form must reproduce the above copyright 13 notice, this list of conditions and the following disclaimer in the 14 documentation and/or other materials provided with the distribution. 15 16 3. Neither the name of the Intel Corporation nor the names of its 17 contributors may be used to endorse or promote products derived from 18 this software without specific prior written permission. 19 20 THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 21 AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 22 IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 23 ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE 24 LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 25 CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 26 SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 27 INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 28 CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 29 ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 30 POSSIBILITY OF SUCH DAMAGE. 31 32 ******************************************************************************/ 33 /*$FreeBSD$*/ 34 35 #include "ixgbe_common.h" 36 #include "ixgbe_api.h" 37 38 static s32 ixgbe_poll_eeprom_eerd_done(struct ixgbe_hw *hw); 39 static s32 ixgbe_acquire_eeprom(struct ixgbe_hw *hw); 40 static s32 ixgbe_get_eeprom_semaphore(struct ixgbe_hw *hw); 41 static void ixgbe_release_eeprom_semaphore(struct ixgbe_hw *hw); 42 static s32 ixgbe_ready_eeprom(struct ixgbe_hw *hw); 43 static void ixgbe_standby_eeprom(struct ixgbe_hw *hw); 44 static void ixgbe_shift_out_eeprom_bits(struct ixgbe_hw *hw, u16 data, 45 u16 count); 46 static u16 ixgbe_shift_in_eeprom_bits(struct ixgbe_hw *hw, u16 count); 47 static void ixgbe_raise_eeprom_clk(struct ixgbe_hw *hw, u32 *eec); 48 static void ixgbe_lower_eeprom_clk(struct ixgbe_hw *hw, u32 *eec); 49 static void ixgbe_release_eeprom(struct ixgbe_hw *hw); 50 static u16 ixgbe_calc_eeprom_checksum(struct ixgbe_hw *hw); 51 52 static s32 ixgbe_mta_vector(struct ixgbe_hw *hw, u8 *mc_addr); 53 54 /** 55 * ixgbe_init_ops_generic - Inits function ptrs 56 * @hw: pointer to the hardware structure 57 * 58 * Initialize the function pointers. 59 **/ 60 s32 ixgbe_init_ops_generic(struct ixgbe_hw *hw) 61 { 62 struct ixgbe_eeprom_info *eeprom = &hw->eeprom; 63 struct ixgbe_mac_info *mac = &hw->mac; 64 u32 eec = IXGBE_READ_REG(hw, IXGBE_EEC); 65 66 /* EEPROM */ 67 eeprom->ops.init_params = &ixgbe_init_eeprom_params_generic; 68 /* If EEPROM is valid (bit 8 = 1), use EERD otherwise use bit bang */ 69 if (eec & (1 << 8)) 70 eeprom->ops.read = &ixgbe_read_eeprom_generic; 71 else 72 eeprom->ops.read = &ixgbe_read_eeprom_bit_bang_generic; 73 eeprom->ops.write = &ixgbe_write_eeprom_generic; 74 eeprom->ops.validate_checksum = 75 &ixgbe_validate_eeprom_checksum_generic; 76 eeprom->ops.update_checksum = &ixgbe_update_eeprom_checksum_generic; 77 78 /* MAC */ 79 mac->ops.init_hw = &ixgbe_init_hw_generic; 80 mac->ops.reset_hw = NULL; 81 mac->ops.start_hw = &ixgbe_start_hw_generic; 82 mac->ops.clear_hw_cntrs = &ixgbe_clear_hw_cntrs_generic; 83 mac->ops.get_media_type = NULL; 84 mac->ops.get_supported_physical_layer = NULL; 85 mac->ops.enable_rx_dma = &ixgbe_enable_rx_dma_generic; 86 mac->ops.get_mac_addr = &ixgbe_get_mac_addr_generic; 87 mac->ops.stop_adapter = &ixgbe_stop_adapter_generic; 88 mac->ops.get_bus_info = &ixgbe_get_bus_info_generic; 89 mac->ops.set_lan_id = &ixgbe_set_lan_id_multi_port_pcie; 90 mac->ops.acquire_swfw_sync = &ixgbe_acquire_swfw_sync; 91 mac->ops.release_swfw_sync = &ixgbe_release_swfw_sync; 92 93 /* LEDs */ 94 mac->ops.led_on = &ixgbe_led_on_generic; 95 mac->ops.led_off = &ixgbe_led_off_generic; 96 mac->ops.blink_led_start = &ixgbe_blink_led_start_generic; 97 mac->ops.blink_led_stop = &ixgbe_blink_led_stop_generic; 98 99 /* RAR, Multicast, VLAN */ 100 mac->ops.set_rar = &ixgbe_set_rar_generic; 101 mac->ops.clear_rar = &ixgbe_clear_rar_generic; 102 mac->ops.insert_mac_addr = NULL; 103 mac->ops.set_vmdq = NULL; 104 mac->ops.clear_vmdq = NULL; 105 mac->ops.init_rx_addrs = &ixgbe_init_rx_addrs_generic; 106 mac->ops.update_uc_addr_list = &ixgbe_update_uc_addr_list_generic; 107 mac->ops.update_mc_addr_list = &ixgbe_update_mc_addr_list_generic; 108 mac->ops.enable_mc = &ixgbe_enable_mc_generic; 109 mac->ops.disable_mc = &ixgbe_disable_mc_generic; 110 mac->ops.clear_vfta = NULL; 111 mac->ops.set_vfta = NULL; 112 mac->ops.init_uta_tables = NULL; 113 114 /* Flow Control */ 115 mac->ops.fc_enable = &ixgbe_fc_enable_generic; 116 117 /* Link */ 118 mac->ops.get_link_capabilities = NULL; 119 mac->ops.setup_link = NULL; 120 mac->ops.setup_link_speed = NULL; 121 mac->ops.check_link = NULL; 122 123 return IXGBE_SUCCESS; 124 } 125 126 /** 127 * ixgbe_start_hw_generic - Prepare hardware for Tx/Rx 128 * @hw: pointer to hardware structure 129 * 130 * Starts the hardware by filling the bus info structure and media type, clears 131 * all on chip counters, initializes receive address registers, multicast 132 * table, VLAN filter table, calls routine to set up link and flow control 133 * settings, and leaves transmit and receive units disabled and uninitialized 134 **/ 135 s32 ixgbe_start_hw_generic(struct ixgbe_hw *hw) 136 { 137 u32 ctrl_ext; 138 s32 ret_val = IXGBE_SUCCESS; 139 140 /* Set the media type */ 141 hw->phy.media_type = hw->mac.ops.get_media_type(hw); 142 143 /* PHY ops initialization must be done in reset_hw() */ 144 145 /* Clear the VLAN filter table */ 146 hw->mac.ops.clear_vfta(hw); 147 148 /* Clear statistics registers */ 149 hw->mac.ops.clear_hw_cntrs(hw); 150 151 /* Set No Snoop Disable */ 152 ctrl_ext = IXGBE_READ_REG(hw, IXGBE_CTRL_EXT); 153 ctrl_ext |= IXGBE_CTRL_EXT_NS_DIS; 154 IXGBE_WRITE_REG(hw, IXGBE_CTRL_EXT, ctrl_ext); 155 IXGBE_WRITE_FLUSH(hw); 156 157 /* Setup flow control */ 158 ixgbe_setup_fc(hw, 0); 159 160 /* Clear adapter stopped flag */ 161 hw->adapter_stopped = FALSE; 162 163 return ret_val; 164 } 165 166 /** 167 * ixgbe_init_hw_generic - Generic hardware initialization 168 * @hw: pointer to hardware structure 169 * 170 * Initialize the hardware by resetting the hardware, filling the bus info 171 * structure and media type, clears all on chip counters, initializes receive 172 * address registers, multicast table, VLAN filter table, calls routine to set 173 * up link and flow control settings, and leaves transmit and receive units 174 * disabled and uninitialized 175 **/ 176 s32 ixgbe_init_hw_generic(struct ixgbe_hw *hw) 177 { 178 s32 status = IXGBE_SUCCESS; 179 180 /* Reset the hardware */ 181 status = hw->mac.ops.reset_hw(hw); 182 183 if (status == IXGBE_SUCCESS) { 184 /* Start the HW */ 185 status = hw->mac.ops.start_hw(hw); 186 } 187 188 return status; 189 } 190 191 /** 192 * ixgbe_clear_hw_cntrs_generic - Generic clear hardware counters 193 * @hw: pointer to hardware structure 194 * 195 * Clears all hardware statistics counters by reading them from the hardware 196 * Statistics counters are clear on read. 197 **/ 198 s32 ixgbe_clear_hw_cntrs_generic(struct ixgbe_hw *hw) 199 { 200 u16 i = 0; 201 202 IXGBE_READ_REG(hw, IXGBE_CRCERRS); 203 IXGBE_READ_REG(hw, IXGBE_ILLERRC); 204 IXGBE_READ_REG(hw, IXGBE_ERRBC); 205 IXGBE_READ_REG(hw, IXGBE_MSPDC); 206 for (i = 0; i < 8; i++) 207 IXGBE_READ_REG(hw, IXGBE_MPC(i)); 208 209 IXGBE_READ_REG(hw, IXGBE_MLFC); 210 IXGBE_READ_REG(hw, IXGBE_MRFC); 211 IXGBE_READ_REG(hw, IXGBE_RLEC); 212 IXGBE_READ_REG(hw, IXGBE_LXONTXC); 213 IXGBE_READ_REG(hw, IXGBE_LXOFFTXC); 214 if (hw->mac.type >= ixgbe_mac_82599EB) { 215 IXGBE_READ_REG(hw, IXGBE_LXONRXCNT); 216 IXGBE_READ_REG(hw, IXGBE_LXOFFRXCNT); 217 } else { 218 IXGBE_READ_REG(hw, IXGBE_LXONRXC); 219 IXGBE_READ_REG(hw, IXGBE_LXOFFRXC); 220 } 221 222 for (i = 0; i < 8; i++) { 223 IXGBE_READ_REG(hw, IXGBE_PXONTXC(i)); 224 IXGBE_READ_REG(hw, IXGBE_PXOFFTXC(i)); 225 if (hw->mac.type >= ixgbe_mac_82599EB) { 226 IXGBE_READ_REG(hw, IXGBE_PXONRXCNT(i)); 227 IXGBE_READ_REG(hw, IXGBE_PXOFFRXCNT(i)); 228 } else { 229 IXGBE_READ_REG(hw, IXGBE_PXONRXC(i)); 230 IXGBE_READ_REG(hw, IXGBE_PXOFFRXC(i)); 231 } 232 } 233 if (hw->mac.type >= ixgbe_mac_82599EB) 234 for (i = 0; i < 8; i++) 235 IXGBE_READ_REG(hw, IXGBE_PXON2OFFCNT(i)); 236 IXGBE_READ_REG(hw, IXGBE_PRC64); 237 IXGBE_READ_REG(hw, IXGBE_PRC127); 238 IXGBE_READ_REG(hw, IXGBE_PRC255); 239 IXGBE_READ_REG(hw, IXGBE_PRC511); 240 IXGBE_READ_REG(hw, IXGBE_PRC1023); 241 IXGBE_READ_REG(hw, IXGBE_PRC1522); 242 IXGBE_READ_REG(hw, IXGBE_GPRC); 243 IXGBE_READ_REG(hw, IXGBE_BPRC); 244 IXGBE_READ_REG(hw, IXGBE_MPRC); 245 IXGBE_READ_REG(hw, IXGBE_GPTC); 246 IXGBE_READ_REG(hw, IXGBE_GORCL); 247 IXGBE_READ_REG(hw, IXGBE_GORCH); 248 IXGBE_READ_REG(hw, IXGBE_GOTCL); 249 IXGBE_READ_REG(hw, IXGBE_GOTCH); 250 for (i = 0; i < 8; i++) 251 IXGBE_READ_REG(hw, IXGBE_RNBC(i)); 252 IXGBE_READ_REG(hw, IXGBE_RUC); 253 IXGBE_READ_REG(hw, IXGBE_RFC); 254 IXGBE_READ_REG(hw, IXGBE_ROC); 255 IXGBE_READ_REG(hw, IXGBE_RJC); 256 IXGBE_READ_REG(hw, IXGBE_MNGPRC); 257 IXGBE_READ_REG(hw, IXGBE_MNGPDC); 258 IXGBE_READ_REG(hw, IXGBE_MNGPTC); 259 IXGBE_READ_REG(hw, IXGBE_TORL); 260 IXGBE_READ_REG(hw, IXGBE_TORH); 261 IXGBE_READ_REG(hw, IXGBE_TPR); 262 IXGBE_READ_REG(hw, IXGBE_TPT); 263 IXGBE_READ_REG(hw, IXGBE_PTC64); 264 IXGBE_READ_REG(hw, IXGBE_PTC127); 265 IXGBE_READ_REG(hw, IXGBE_PTC255); 266 IXGBE_READ_REG(hw, IXGBE_PTC511); 267 IXGBE_READ_REG(hw, IXGBE_PTC1023); 268 IXGBE_READ_REG(hw, IXGBE_PTC1522); 269 IXGBE_READ_REG(hw, IXGBE_MPTC); 270 IXGBE_READ_REG(hw, IXGBE_BPTC); 271 for (i = 0; i < 16; i++) { 272 IXGBE_READ_REG(hw, IXGBE_QPRC(i)); 273 IXGBE_READ_REG(hw, IXGBE_QBRC(i)); 274 IXGBE_READ_REG(hw, IXGBE_QPTC(i)); 275 IXGBE_READ_REG(hw, IXGBE_QBTC(i)); 276 } 277 278 return IXGBE_SUCCESS; 279 } 280 281 /** 282 * ixgbe_read_pba_num_generic - Reads part number from EEPROM 283 * @hw: pointer to hardware structure 284 * @pba_num: stores the part number from the EEPROM 285 * 286 * Reads the part number from the EEPROM. 287 **/ 288 s32 ixgbe_read_pba_num_generic(struct ixgbe_hw *hw, u32 *pba_num) 289 { 290 s32 ret_val; 291 u16 data; 292 293 DEBUGFUNC("ixgbe_read_pba_num_generic"); 294 295 ret_val = hw->eeprom.ops.read(hw, IXGBE_PBANUM0_PTR, &data); 296 if (ret_val) { 297 DEBUGOUT("NVM Read Error\n"); 298 return ret_val; 299 } 300 *pba_num = (u32)(data << 16); 301 302 ret_val = hw->eeprom.ops.read(hw, IXGBE_PBANUM1_PTR, &data); 303 if (ret_val) { 304 DEBUGOUT("NVM Read Error\n"); 305 return ret_val; 306 } 307 *pba_num |= data; 308 309 return IXGBE_SUCCESS; 310 } 311 312 /** 313 * ixgbe_get_mac_addr_generic - Generic get MAC address 314 * @hw: pointer to hardware structure 315 * @mac_addr: Adapter MAC address 316 * 317 * Reads the adapter's MAC address from first Receive Address Register (RAR0) 318 * A reset of the adapter must be performed prior to calling this function 319 * in order for the MAC address to have been loaded from the EEPROM into RAR0 320 **/ 321 s32 ixgbe_get_mac_addr_generic(struct ixgbe_hw *hw, u8 *mac_addr) 322 { 323 u32 rar_high; 324 u32 rar_low; 325 u16 i; 326 327 rar_high = IXGBE_READ_REG(hw, IXGBE_RAH(0)); 328 rar_low = IXGBE_READ_REG(hw, IXGBE_RAL(0)); 329 330 for (i = 0; i < 4; i++) 331 mac_addr[i] = (u8)(rar_low >> (i*8)); 332 333 for (i = 0; i < 2; i++) 334 mac_addr[i+4] = (u8)(rar_high >> (i*8)); 335 336 return IXGBE_SUCCESS; 337 } 338 339 /** 340 * ixgbe_get_bus_info_generic - Generic set PCI bus info 341 * @hw: pointer to hardware structure 342 * 343 * Sets the PCI bus info (speed, width, type) within the ixgbe_hw structure 344 **/ 345 s32 ixgbe_get_bus_info_generic(struct ixgbe_hw *hw) 346 { 347 struct ixgbe_mac_info *mac = &hw->mac; 348 u16 link_status; 349 350 hw->bus.type = ixgbe_bus_type_pci_express; 351 352 /* Get the negotiated link width and speed from PCI config space */ 353 link_status = IXGBE_READ_PCIE_WORD(hw, IXGBE_PCI_LINK_STATUS); 354 355 switch (link_status & IXGBE_PCI_LINK_WIDTH) { 356 case IXGBE_PCI_LINK_WIDTH_1: 357 hw->bus.width = ixgbe_bus_width_pcie_x1; 358 break; 359 case IXGBE_PCI_LINK_WIDTH_2: 360 hw->bus.width = ixgbe_bus_width_pcie_x2; 361 break; 362 case IXGBE_PCI_LINK_WIDTH_4: 363 hw->bus.width = ixgbe_bus_width_pcie_x4; 364 break; 365 case IXGBE_PCI_LINK_WIDTH_8: 366 hw->bus.width = ixgbe_bus_width_pcie_x8; 367 break; 368 default: 369 hw->bus.width = ixgbe_bus_width_unknown; 370 break; 371 } 372 373 switch (link_status & IXGBE_PCI_LINK_SPEED) { 374 case IXGBE_PCI_LINK_SPEED_2500: 375 hw->bus.speed = ixgbe_bus_speed_2500; 376 break; 377 case IXGBE_PCI_LINK_SPEED_5000: 378 hw->bus.speed = ixgbe_bus_speed_5000; 379 break; 380 default: 381 hw->bus.speed = ixgbe_bus_speed_unknown; 382 break; 383 } 384 385 mac->ops.set_lan_id(hw); 386 387 return IXGBE_SUCCESS; 388 } 389 390 /** 391 * ixgbe_set_lan_id_multi_port_pcie - Set LAN id for PCIe multiple port devices 392 * @hw: pointer to the HW structure 393 * 394 * Determines the LAN function id by reading memory-mapped registers 395 * and swaps the port value if requested. 396 **/ 397 void ixgbe_set_lan_id_multi_port_pcie(struct ixgbe_hw *hw) 398 { 399 struct ixgbe_bus_info *bus = &hw->bus; 400 u32 reg; 401 402 reg = IXGBE_READ_REG(hw, IXGBE_STATUS); 403 bus->func = (reg & IXGBE_STATUS_LAN_ID) >> IXGBE_STATUS_LAN_ID_SHIFT; 404 bus->lan_id = bus->func; 405 406 /* check for a port swap */ 407 reg = IXGBE_READ_REG(hw, IXGBE_FACTPS); 408 if (reg & IXGBE_FACTPS_LFS) 409 bus->func ^= 0x1; 410 } 411 412 /** 413 * ixgbe_stop_adapter_generic - Generic stop Tx/Rx units 414 * @hw: pointer to hardware structure 415 * 416 * Sets the adapter_stopped flag within ixgbe_hw struct. Clears interrupts, 417 * disables transmit and receive units. The adapter_stopped flag is used by 418 * the shared code and drivers to determine if the adapter is in a stopped 419 * state and should not touch the hardware. 420 **/ 421 s32 ixgbe_stop_adapter_generic(struct ixgbe_hw *hw) 422 { 423 u32 number_of_queues; 424 u32 reg_val; 425 u16 i; 426 427 /* 428 * Set the adapter_stopped flag so other driver functions stop touching 429 * the hardware 430 */ 431 hw->adapter_stopped = TRUE; 432 433 /* Disable the receive unit */ 434 reg_val = IXGBE_READ_REG(hw, IXGBE_RXCTRL); 435 reg_val &= ~(IXGBE_RXCTRL_RXEN); 436 IXGBE_WRITE_REG(hw, IXGBE_RXCTRL, reg_val); 437 IXGBE_WRITE_FLUSH(hw); 438 msec_delay(2); 439 440 /* Clear interrupt mask to stop from interrupts being generated */ 441 IXGBE_WRITE_REG(hw, IXGBE_EIMC, IXGBE_IRQ_CLEAR_MASK); 442 443 /* Clear any pending interrupts */ 444 IXGBE_READ_REG(hw, IXGBE_EICR); 445 446 /* Disable the transmit unit. Each queue must be disabled. */ 447 number_of_queues = hw->mac.max_tx_queues; 448 for (i = 0; i < number_of_queues; i++) { 449 reg_val = IXGBE_READ_REG(hw, IXGBE_TXDCTL(i)); 450 if (reg_val & IXGBE_TXDCTL_ENABLE) { 451 reg_val &= ~IXGBE_TXDCTL_ENABLE; 452 IXGBE_WRITE_REG(hw, IXGBE_TXDCTL(i), reg_val); 453 } 454 } 455 456 /* 457 * Prevent the PCI-E bus from from hanging by disabling PCI-E master 458 * access and verify no pending requests 459 */ 460 if (ixgbe_disable_pcie_master(hw) != IXGBE_SUCCESS) 461 DEBUGOUT("PCI-E Master disable polling has failed.\n"); 462 463 return IXGBE_SUCCESS; 464 } 465 466 /** 467 * ixgbe_led_on_generic - Turns on the software controllable LEDs. 468 * @hw: pointer to hardware structure 469 * @index: led number to turn on 470 **/ 471 s32 ixgbe_led_on_generic(struct ixgbe_hw *hw, u32 index) 472 { 473 u32 led_reg = IXGBE_READ_REG(hw, IXGBE_LEDCTL); 474 475 /* To turn on the LED, set mode to ON. */ 476 led_reg &= ~IXGBE_LED_MODE_MASK(index); 477 led_reg |= IXGBE_LED_ON << IXGBE_LED_MODE_SHIFT(index); 478 IXGBE_WRITE_REG(hw, IXGBE_LEDCTL, led_reg); 479 IXGBE_WRITE_FLUSH(hw); 480 481 return IXGBE_SUCCESS; 482 } 483 484 /** 485 * ixgbe_led_off_generic - Turns off the software controllable LEDs. 486 * @hw: pointer to hardware structure 487 * @index: led number to turn off 488 **/ 489 s32 ixgbe_led_off_generic(struct ixgbe_hw *hw, u32 index) 490 { 491 u32 led_reg = IXGBE_READ_REG(hw, IXGBE_LEDCTL); 492 493 /* To turn off the LED, set mode to OFF. */ 494 led_reg &= ~IXGBE_LED_MODE_MASK(index); 495 led_reg |= IXGBE_LED_OFF << IXGBE_LED_MODE_SHIFT(index); 496 IXGBE_WRITE_REG(hw, IXGBE_LEDCTL, led_reg); 497 IXGBE_WRITE_FLUSH(hw); 498 499 return IXGBE_SUCCESS; 500 } 501 502 /** 503 * ixgbe_init_eeprom_params_generic - Initialize EEPROM params 504 * @hw: pointer to hardware structure 505 * 506 * Initializes the EEPROM parameters ixgbe_eeprom_info within the 507 * ixgbe_hw struct in order to set up EEPROM access. 508 **/ 509 s32 ixgbe_init_eeprom_params_generic(struct ixgbe_hw *hw) 510 { 511 struct ixgbe_eeprom_info *eeprom = &hw->eeprom; 512 u32 eec; 513 u16 eeprom_size; 514 515 if (eeprom->type == ixgbe_eeprom_uninitialized) { 516 eeprom->type = ixgbe_eeprom_none; 517 /* Set default semaphore delay to 10ms which is a well 518 * tested value */ 519 eeprom->semaphore_delay = 10; 520 521 /* 522 * Check for EEPROM present first. 523 * If not present leave as none 524 */ 525 eec = IXGBE_READ_REG(hw, IXGBE_EEC); 526 if (eec & IXGBE_EEC_PRES) { 527 eeprom->type = ixgbe_eeprom_spi; 528 529 /* 530 * SPI EEPROM is assumed here. This code would need to 531 * change if a future EEPROM is not SPI. 532 */ 533 eeprom_size = (u16)((eec & IXGBE_EEC_SIZE) >> 534 IXGBE_EEC_SIZE_SHIFT); 535 eeprom->word_size = 1 << (eeprom_size + 536 IXGBE_EEPROM_WORD_SIZE_SHIFT); 537 } 538 539 if (eec & IXGBE_EEC_ADDR_SIZE) 540 eeprom->address_bits = 16; 541 else 542 eeprom->address_bits = 8; 543 DEBUGOUT3("Eeprom params: type = %d, size = %d, address bits: " 544 "%d\n", eeprom->type, eeprom->word_size, 545 eeprom->address_bits); 546 } 547 548 return IXGBE_SUCCESS; 549 } 550 551 /** 552 * ixgbe_write_eeprom_generic - Writes 16 bit value to EEPROM 553 * @hw: pointer to hardware structure 554 * @offset: offset within the EEPROM to be written to 555 * @data: 16 bit word to be written to the EEPROM 556 * 557 * If ixgbe_eeprom_update_checksum is not called after this function, the 558 * EEPROM will most likely contain an invalid checksum. 559 **/ 560 s32 ixgbe_write_eeprom_generic(struct ixgbe_hw *hw, u16 offset, u16 data) 561 { 562 s32 status; 563 u8 write_opcode = IXGBE_EEPROM_WRITE_OPCODE_SPI; 564 565 hw->eeprom.ops.init_params(hw); 566 567 if (offset >= hw->eeprom.word_size) { 568 status = IXGBE_ERR_EEPROM; 569 goto out; 570 } 571 572 /* Prepare the EEPROM for writing */ 573 status = ixgbe_acquire_eeprom(hw); 574 575 if (status == IXGBE_SUCCESS) { 576 if (ixgbe_ready_eeprom(hw) != IXGBE_SUCCESS) { 577 ixgbe_release_eeprom(hw); 578 status = IXGBE_ERR_EEPROM; 579 } 580 } 581 582 if (status == IXGBE_SUCCESS) { 583 ixgbe_standby_eeprom(hw); 584 585 /* Send the WRITE ENABLE command (8 bit opcode ) */ 586 ixgbe_shift_out_eeprom_bits(hw, IXGBE_EEPROM_WREN_OPCODE_SPI, 587 IXGBE_EEPROM_OPCODE_BITS); 588 589 ixgbe_standby_eeprom(hw); 590 591 /* 592 * Some SPI eeproms use the 8th address bit embedded in the 593 * opcode 594 */ 595 if ((hw->eeprom.address_bits == 8) && (offset >= 128)) 596 write_opcode |= IXGBE_EEPROM_A8_OPCODE_SPI; 597 598 /* Send the Write command (8-bit opcode + addr) */ 599 ixgbe_shift_out_eeprom_bits(hw, write_opcode, 600 IXGBE_EEPROM_OPCODE_BITS); 601 ixgbe_shift_out_eeprom_bits(hw, (u16)(offset*2), 602 hw->eeprom.address_bits); 603 604 /* Send the data */ 605 data = (data >> 8) | (data << 8); 606 ixgbe_shift_out_eeprom_bits(hw, data, 16); 607 ixgbe_standby_eeprom(hw); 608 609 /* Done with writing - release the EEPROM */ 610 ixgbe_release_eeprom(hw); 611 } 612 613 out: 614 return status; 615 } 616 617 /** 618 * ixgbe_read_eeprom_bit_bang_generic - Read EEPROM word using bit-bang 619 * @hw: pointer to hardware structure 620 * @offset: offset within the EEPROM to be read 621 * @data: read 16 bit value from EEPROM 622 * 623 * Reads 16 bit value from EEPROM through bit-bang method 624 **/ 625 s32 ixgbe_read_eeprom_bit_bang_generic(struct ixgbe_hw *hw, u16 offset, 626 u16 *data) 627 { 628 s32 status; 629 u16 word_in; 630 u8 read_opcode = IXGBE_EEPROM_READ_OPCODE_SPI; 631 632 hw->eeprom.ops.init_params(hw); 633 634 if (offset >= hw->eeprom.word_size) { 635 status = IXGBE_ERR_EEPROM; 636 goto out; 637 } 638 639 /* Prepare the EEPROM for reading */ 640 status = ixgbe_acquire_eeprom(hw); 641 642 if (status == IXGBE_SUCCESS) { 643 if (ixgbe_ready_eeprom(hw) != IXGBE_SUCCESS) { 644 ixgbe_release_eeprom(hw); 645 status = IXGBE_ERR_EEPROM; 646 } 647 } 648 649 if (status == IXGBE_SUCCESS) { 650 ixgbe_standby_eeprom(hw); 651 652 /* 653 * Some SPI eeproms use the 8th address bit embedded in the 654 * opcode 655 */ 656 if ((hw->eeprom.address_bits == 8) && (offset >= 128)) 657 read_opcode |= IXGBE_EEPROM_A8_OPCODE_SPI; 658 659 /* Send the READ command (opcode + addr) */ 660 ixgbe_shift_out_eeprom_bits(hw, read_opcode, 661 IXGBE_EEPROM_OPCODE_BITS); 662 ixgbe_shift_out_eeprom_bits(hw, (u16)(offset*2), 663 hw->eeprom.address_bits); 664 665 /* Read the data. */ 666 word_in = ixgbe_shift_in_eeprom_bits(hw, 16); 667 *data = (word_in >> 8) | (word_in << 8); 668 669 /* End this read operation */ 670 ixgbe_release_eeprom(hw); 671 } 672 673 out: 674 return status; 675 } 676 677 /** 678 * ixgbe_read_eeprom_generic - Read EEPROM word using EERD 679 * @hw: pointer to hardware structure 680 * @offset: offset of word in the EEPROM to read 681 * @data: word read from the EEPROM 682 * 683 * Reads a 16 bit word from the EEPROM using the EERD register. 684 **/ 685 s32 ixgbe_read_eeprom_generic(struct ixgbe_hw *hw, u16 offset, u16 *data) 686 { 687 u32 eerd; 688 s32 status; 689 690 hw->eeprom.ops.init_params(hw); 691 692 if (offset >= hw->eeprom.word_size) { 693 status = IXGBE_ERR_EEPROM; 694 goto out; 695 } 696 697 eerd = (offset << IXGBE_EEPROM_READ_ADDR_SHIFT) + 698 IXGBE_EEPROM_READ_REG_START; 699 700 IXGBE_WRITE_REG(hw, IXGBE_EERD, eerd); 701 status = ixgbe_poll_eeprom_eerd_done(hw); 702 703 if (status == IXGBE_SUCCESS) 704 *data = (IXGBE_READ_REG(hw, IXGBE_EERD) >> 705 IXGBE_EEPROM_READ_REG_DATA); 706 else 707 DEBUGOUT("Eeprom read timed out\n"); 708 709 out: 710 return status; 711 } 712 713 /** 714 * ixgbe_poll_eeprom_eerd_done - Poll EERD status 715 * @hw: pointer to hardware structure 716 * 717 * Polls the status bit (bit 1) of the EERD to determine when the read is done. 718 **/ 719 static s32 ixgbe_poll_eeprom_eerd_done(struct ixgbe_hw *hw) 720 { 721 u32 i; 722 u32 reg; 723 s32 status = IXGBE_ERR_EEPROM; 724 725 for (i = 0; i < IXGBE_EERD_ATTEMPTS; i++) { 726 reg = IXGBE_READ_REG(hw, IXGBE_EERD); 727 if (reg & IXGBE_EEPROM_READ_REG_DONE) { 728 status = IXGBE_SUCCESS; 729 break; 730 } 731 usec_delay(5); 732 } 733 return status; 734 } 735 736 /** 737 * ixgbe_acquire_eeprom - Acquire EEPROM using bit-bang 738 * @hw: pointer to hardware structure 739 * 740 * Prepares EEPROM for access using bit-bang method. This function should 741 * be called before issuing a command to the EEPROM. 742 **/ 743 static s32 ixgbe_acquire_eeprom(struct ixgbe_hw *hw) 744 { 745 s32 status = IXGBE_SUCCESS; 746 u32 eec; 747 u32 i; 748 749 if (ixgbe_acquire_swfw_sync(hw, IXGBE_GSSR_EEP_SM) != IXGBE_SUCCESS) 750 status = IXGBE_ERR_SWFW_SYNC; 751 752 if (status == IXGBE_SUCCESS) { 753 eec = IXGBE_READ_REG(hw, IXGBE_EEC); 754 755 /* Request EEPROM Access */ 756 eec |= IXGBE_EEC_REQ; 757 IXGBE_WRITE_REG(hw, IXGBE_EEC, eec); 758 759 for (i = 0; i < IXGBE_EEPROM_GRANT_ATTEMPTS; i++) { 760 eec = IXGBE_READ_REG(hw, IXGBE_EEC); 761 if (eec & IXGBE_EEC_GNT) 762 break; 763 usec_delay(5); 764 } 765 766 /* Release if grant not acquired */ 767 if (!(eec & IXGBE_EEC_GNT)) { 768 eec &= ~IXGBE_EEC_REQ; 769 IXGBE_WRITE_REG(hw, IXGBE_EEC, eec); 770 DEBUGOUT("Could not acquire EEPROM grant\n"); 771 772 ixgbe_release_swfw_sync(hw, IXGBE_GSSR_EEP_SM); 773 status = IXGBE_ERR_EEPROM; 774 } 775 } 776 777 /* Setup EEPROM for Read/Write */ 778 if (status == IXGBE_SUCCESS) { 779 /* Clear CS and SK */ 780 eec &= ~(IXGBE_EEC_CS | IXGBE_EEC_SK); 781 IXGBE_WRITE_REG(hw, IXGBE_EEC, eec); 782 IXGBE_WRITE_FLUSH(hw); 783 usec_delay(1); 784 } 785 return status; 786 } 787 788 /** 789 * ixgbe_get_eeprom_semaphore - Get hardware semaphore 790 * @hw: pointer to hardware structure 791 * 792 * Sets the hardware semaphores so EEPROM access can occur for bit-bang method 793 **/ 794 static s32 ixgbe_get_eeprom_semaphore(struct ixgbe_hw *hw) 795 { 796 s32 status = IXGBE_ERR_EEPROM; 797 u32 timeout = 2000; 798 u32 i; 799 u32 swsm; 800 801 /* Get SMBI software semaphore between device drivers first */ 802 for (i = 0; i < timeout; i++) { 803 /* 804 * If the SMBI bit is 0 when we read it, then the bit will be 805 * set and we have the semaphore 806 */ 807 swsm = IXGBE_READ_REG(hw, IXGBE_SWSM); 808 if (!(swsm & IXGBE_SWSM_SMBI)) { 809 status = IXGBE_SUCCESS; 810 break; 811 } 812 usec_delay(50); 813 } 814 815 /* Now get the semaphore between SW/FW through the SWESMBI bit */ 816 if (status == IXGBE_SUCCESS) { 817 for (i = 0; i < timeout; i++) { 818 swsm = IXGBE_READ_REG(hw, IXGBE_SWSM); 819 820 /* Set the SW EEPROM semaphore bit to request access */ 821 swsm |= IXGBE_SWSM_SWESMBI; 822 IXGBE_WRITE_REG(hw, IXGBE_SWSM, swsm); 823 824 /* 825 * If we set the bit successfully then we got the 826 * semaphore. 827 */ 828 swsm = IXGBE_READ_REG(hw, IXGBE_SWSM); 829 if (swsm & IXGBE_SWSM_SWESMBI) 830 break; 831 832 usec_delay(50); 833 } 834 835 /* 836 * Release semaphores and return error if SW EEPROM semaphore 837 * was not granted because we don't have access to the EEPROM 838 */ 839 if (i >= timeout) { 840 DEBUGOUT("SWESMBI Software EEPROM semaphore " 841 "not granted.\n"); 842 ixgbe_release_eeprom_semaphore(hw); 843 status = IXGBE_ERR_EEPROM; 844 } 845 } else { 846 DEBUGOUT("Software semaphore SMBI between device drivers " 847 "not granted.\n"); 848 } 849 850 return status; 851 } 852 853 /** 854 * ixgbe_release_eeprom_semaphore - Release hardware semaphore 855 * @hw: pointer to hardware structure 856 * 857 * This function clears hardware semaphore bits. 858 **/ 859 static void ixgbe_release_eeprom_semaphore(struct ixgbe_hw *hw) 860 { 861 u32 swsm; 862 863 swsm = IXGBE_READ_REG(hw, IXGBE_SWSM); 864 865 /* Release both semaphores by writing 0 to the bits SWESMBI and SMBI */ 866 swsm &= ~(IXGBE_SWSM_SWESMBI | IXGBE_SWSM_SMBI); 867 IXGBE_WRITE_REG(hw, IXGBE_SWSM, swsm); 868 IXGBE_WRITE_FLUSH(hw); 869 } 870 871 /** 872 * ixgbe_ready_eeprom - Polls for EEPROM ready 873 * @hw: pointer to hardware structure 874 **/ 875 static s32 ixgbe_ready_eeprom(struct ixgbe_hw *hw) 876 { 877 s32 status = IXGBE_SUCCESS; 878 u16 i; 879 u8 spi_stat_reg; 880 881 /* 882 * Read "Status Register" repeatedly until the LSB is cleared. The 883 * EEPROM will signal that the command has been completed by clearing 884 * bit 0 of the internal status register. If it's not cleared within 885 * 5 milliseconds, then error out. 886 */ 887 for (i = 0; i < IXGBE_EEPROM_MAX_RETRY_SPI; i += 5) { 888 ixgbe_shift_out_eeprom_bits(hw, IXGBE_EEPROM_RDSR_OPCODE_SPI, 889 IXGBE_EEPROM_OPCODE_BITS); 890 spi_stat_reg = (u8)ixgbe_shift_in_eeprom_bits(hw, 8); 891 if (!(spi_stat_reg & IXGBE_EEPROM_STATUS_RDY_SPI)) 892 break; 893 894 usec_delay(5); 895 ixgbe_standby_eeprom(hw); 896 }; 897 898 /* 899 * On some parts, SPI write time could vary from 0-20mSec on 3.3V 900 * devices (and only 0-5mSec on 5V devices) 901 */ 902 if (i >= IXGBE_EEPROM_MAX_RETRY_SPI) { 903 DEBUGOUT("SPI EEPROM Status error\n"); 904 status = IXGBE_ERR_EEPROM; 905 } 906 907 return status; 908 } 909 910 /** 911 * ixgbe_standby_eeprom - Returns EEPROM to a "standby" state 912 * @hw: pointer to hardware structure 913 **/ 914 static void ixgbe_standby_eeprom(struct ixgbe_hw *hw) 915 { 916 u32 eec; 917 918 eec = IXGBE_READ_REG(hw, IXGBE_EEC); 919 920 /* Toggle CS to flush commands */ 921 eec |= IXGBE_EEC_CS; 922 IXGBE_WRITE_REG(hw, IXGBE_EEC, eec); 923 IXGBE_WRITE_FLUSH(hw); 924 usec_delay(1); 925 eec &= ~IXGBE_EEC_CS; 926 IXGBE_WRITE_REG(hw, IXGBE_EEC, eec); 927 IXGBE_WRITE_FLUSH(hw); 928 usec_delay(1); 929 } 930 931 /** 932 * ixgbe_shift_out_eeprom_bits - Shift data bits out to the EEPROM. 933 * @hw: pointer to hardware structure 934 * @data: data to send to the EEPROM 935 * @count: number of bits to shift out 936 **/ 937 static void ixgbe_shift_out_eeprom_bits(struct ixgbe_hw *hw, u16 data, 938 u16 count) 939 { 940 u32 eec; 941 u32 mask; 942 u32 i; 943 944 eec = IXGBE_READ_REG(hw, IXGBE_EEC); 945 946 /* 947 * Mask is used to shift "count" bits of "data" out to the EEPROM 948 * one bit at a time. Determine the starting bit based on count 949 */ 950 mask = 0x01 << (count - 1); 951 952 for (i = 0; i < count; i++) { 953 /* 954 * A "1" is shifted out to the EEPROM by setting bit "DI" to a 955 * "1", and then raising and then lowering the clock (the SK 956 * bit controls the clock input to the EEPROM). A "0" is 957 * shifted out to the EEPROM by setting "DI" to "0" and then 958 * raising and then lowering the clock. 959 */ 960 if (data & mask) 961 eec |= IXGBE_EEC_DI; 962 else 963 eec &= ~IXGBE_EEC_DI; 964 965 IXGBE_WRITE_REG(hw, IXGBE_EEC, eec); 966 IXGBE_WRITE_FLUSH(hw); 967 968 usec_delay(1); 969 970 ixgbe_raise_eeprom_clk(hw, &eec); 971 ixgbe_lower_eeprom_clk(hw, &eec); 972 973 /* 974 * Shift mask to signify next bit of data to shift in to the 975 * EEPROM 976 */ 977 mask = mask >> 1; 978 }; 979 980 /* We leave the "DI" bit set to "0" when we leave this routine. */ 981 eec &= ~IXGBE_EEC_DI; 982 IXGBE_WRITE_REG(hw, IXGBE_EEC, eec); 983 IXGBE_WRITE_FLUSH(hw); 984 } 985 986 /** 987 * ixgbe_shift_in_eeprom_bits - Shift data bits in from the EEPROM 988 * @hw: pointer to hardware structure 989 **/ 990 static u16 ixgbe_shift_in_eeprom_bits(struct ixgbe_hw *hw, u16 count) 991 { 992 u32 eec; 993 u32 i; 994 u16 data = 0; 995 996 /* 997 * In order to read a register from the EEPROM, we need to shift 998 * 'count' bits in from the EEPROM. Bits are "shifted in" by raising 999 * the clock input to the EEPROM (setting the SK bit), and then reading 1000 * the value of the "DO" bit. During this "shifting in" process the 1001 * "DI" bit should always be clear. 1002 */ 1003 eec = IXGBE_READ_REG(hw, IXGBE_EEC); 1004 1005 eec &= ~(IXGBE_EEC_DO | IXGBE_EEC_DI); 1006 1007 for (i = 0; i < count; i++) { 1008 data = data << 1; 1009 ixgbe_raise_eeprom_clk(hw, &eec); 1010 1011 eec = IXGBE_READ_REG(hw, IXGBE_EEC); 1012 1013 eec &= ~(IXGBE_EEC_DI); 1014 if (eec & IXGBE_EEC_DO) 1015 data |= 1; 1016 1017 ixgbe_lower_eeprom_clk(hw, &eec); 1018 } 1019 1020 return data; 1021 } 1022 1023 /** 1024 * ixgbe_raise_eeprom_clk - Raises the EEPROM's clock input. 1025 * @hw: pointer to hardware structure 1026 * @eec: EEC register's current value 1027 **/ 1028 static void ixgbe_raise_eeprom_clk(struct ixgbe_hw *hw, u32 *eec) 1029 { 1030 /* 1031 * Raise the clock input to the EEPROM 1032 * (setting the SK bit), then delay 1033 */ 1034 *eec = *eec | IXGBE_EEC_SK; 1035 IXGBE_WRITE_REG(hw, IXGBE_EEC, *eec); 1036 IXGBE_WRITE_FLUSH(hw); 1037 usec_delay(1); 1038 } 1039 1040 /** 1041 * ixgbe_lower_eeprom_clk - Lowers the EEPROM's clock input. 1042 * @hw: pointer to hardware structure 1043 * @eecd: EECD's current value 1044 **/ 1045 static void ixgbe_lower_eeprom_clk(struct ixgbe_hw *hw, u32 *eec) 1046 { 1047 /* 1048 * Lower the clock input to the EEPROM (clearing the SK bit), then 1049 * delay 1050 */ 1051 *eec = *eec & ~IXGBE_EEC_SK; 1052 IXGBE_WRITE_REG(hw, IXGBE_EEC, *eec); 1053 IXGBE_WRITE_FLUSH(hw); 1054 usec_delay(1); 1055 } 1056 1057 /** 1058 * ixgbe_release_eeprom - Release EEPROM, release semaphores 1059 * @hw: pointer to hardware structure 1060 **/ 1061 static void ixgbe_release_eeprom(struct ixgbe_hw *hw) 1062 { 1063 u32 eec; 1064 1065 eec = IXGBE_READ_REG(hw, IXGBE_EEC); 1066 1067 eec |= IXGBE_EEC_CS; /* Pull CS high */ 1068 eec &= ~IXGBE_EEC_SK; /* Lower SCK */ 1069 1070 IXGBE_WRITE_REG(hw, IXGBE_EEC, eec); 1071 IXGBE_WRITE_FLUSH(hw); 1072 1073 usec_delay(1); 1074 1075 /* Stop requesting EEPROM access */ 1076 eec &= ~IXGBE_EEC_REQ; 1077 IXGBE_WRITE_REG(hw, IXGBE_EEC, eec); 1078 1079 ixgbe_release_swfw_sync(hw, IXGBE_GSSR_EEP_SM); 1080 1081 /* Delay before attempt to obtain semaphore again to allow FW access */ 1082 msec_delay(hw->eeprom.semaphore_delay); 1083 } 1084 1085 /** 1086 * ixgbe_calc_eeprom_checksum - Calculates and returns the checksum 1087 * @hw: pointer to hardware structure 1088 **/ 1089 static u16 ixgbe_calc_eeprom_checksum(struct ixgbe_hw *hw) 1090 { 1091 u16 i; 1092 u16 j; 1093 u16 checksum = 0; 1094 u16 length = 0; 1095 u16 pointer = 0; 1096 u16 word = 0; 1097 1098 /* Include 0x0-0x3F in the checksum */ 1099 for (i = 0; i < IXGBE_EEPROM_CHECKSUM; i++) { 1100 if (hw->eeprom.ops.read(hw, i, &word) != IXGBE_SUCCESS) { 1101 DEBUGOUT("EEPROM read failed\n"); 1102 break; 1103 } 1104 checksum += word; 1105 } 1106 1107 /* Include all data from pointers except for the fw pointer */ 1108 for (i = IXGBE_PCIE_ANALOG_PTR; i < IXGBE_FW_PTR; i++) { 1109 hw->eeprom.ops.read(hw, i, &pointer); 1110 1111 /* Make sure the pointer seems valid */ 1112 if (pointer != 0xFFFF && pointer != 0) { 1113 hw->eeprom.ops.read(hw, pointer, &length); 1114 1115 if (length != 0xFFFF && length != 0) { 1116 for (j = pointer+1; j <= pointer+length; j++) { 1117 hw->eeprom.ops.read(hw, j, &word); 1118 checksum += word; 1119 } 1120 } 1121 } 1122 } 1123 1124 checksum = (u16)IXGBE_EEPROM_SUM - checksum; 1125 1126 return checksum; 1127 } 1128 1129 /** 1130 * ixgbe_validate_eeprom_checksum_generic - Validate EEPROM checksum 1131 * @hw: pointer to hardware structure 1132 * @checksum_val: calculated checksum 1133 * 1134 * Performs checksum calculation and validates the EEPROM checksum. If the 1135 * caller does not need checksum_val, the value can be NULL. 1136 **/ 1137 s32 ixgbe_validate_eeprom_checksum_generic(struct ixgbe_hw *hw, 1138 u16 *checksum_val) 1139 { 1140 s32 status; 1141 u16 checksum; 1142 u16 read_checksum = 0; 1143 1144 /* 1145 * Read the first word from the EEPROM. If this times out or fails, do 1146 * not continue or we could be in for a very long wait while every 1147 * EEPROM read fails 1148 */ 1149 status = hw->eeprom.ops.read(hw, 0, &checksum); 1150 1151 if (status == IXGBE_SUCCESS) { 1152 checksum = ixgbe_calc_eeprom_checksum(hw); 1153 1154 hw->eeprom.ops.read(hw, IXGBE_EEPROM_CHECKSUM, &read_checksum); 1155 1156 /* 1157 * Verify read checksum from EEPROM is the same as 1158 * calculated checksum 1159 */ 1160 if (read_checksum != checksum) 1161 status = IXGBE_ERR_EEPROM_CHECKSUM; 1162 1163 /* If the user cares, return the calculated checksum */ 1164 if (checksum_val) 1165 *checksum_val = checksum; 1166 } else { 1167 DEBUGOUT("EEPROM read failed\n"); 1168 } 1169 1170 return status; 1171 } 1172 1173 /** 1174 * ixgbe_update_eeprom_checksum_generic - Updates the EEPROM checksum 1175 * @hw: pointer to hardware structure 1176 **/ 1177 s32 ixgbe_update_eeprom_checksum_generic(struct ixgbe_hw *hw) 1178 { 1179 s32 status; 1180 u16 checksum; 1181 1182 /* 1183 * Read the first word from the EEPROM. If this times out or fails, do 1184 * not continue or we could be in for a very long wait while every 1185 * EEPROM read fails 1186 */ 1187 status = hw->eeprom.ops.read(hw, 0, &checksum); 1188 1189 if (status == IXGBE_SUCCESS) { 1190 checksum = ixgbe_calc_eeprom_checksum(hw); 1191 status = hw->eeprom.ops.write(hw, IXGBE_EEPROM_CHECKSUM, 1192 checksum); 1193 } else { 1194 DEBUGOUT("EEPROM read failed\n"); 1195 } 1196 1197 return status; 1198 } 1199 1200 /** 1201 * ixgbe_validate_mac_addr - Validate MAC address 1202 * @mac_addr: pointer to MAC address. 1203 * 1204 * Tests a MAC address to ensure it is a valid Individual Address 1205 **/ 1206 s32 ixgbe_validate_mac_addr(u8 *mac_addr) 1207 { 1208 s32 status = IXGBE_SUCCESS; 1209 1210 /* Make sure it is not a multicast address */ 1211 if (IXGBE_IS_MULTICAST(mac_addr)) { 1212 DEBUGOUT("MAC address is multicast\n"); 1213 status = IXGBE_ERR_INVALID_MAC_ADDR; 1214 /* Not a broadcast address */ 1215 } else if (IXGBE_IS_BROADCAST(mac_addr)) { 1216 DEBUGOUT("MAC address is broadcast\n"); 1217 status = IXGBE_ERR_INVALID_MAC_ADDR; 1218 /* Reject the zero address */ 1219 } else if (mac_addr[0] == 0 && mac_addr[1] == 0 && mac_addr[2] == 0 && 1220 mac_addr[3] == 0 && mac_addr[4] == 0 && mac_addr[5] == 0) { 1221 DEBUGOUT("MAC address is all zeros\n"); 1222 status = IXGBE_ERR_INVALID_MAC_ADDR; 1223 } 1224 return status; 1225 } 1226 1227 /** 1228 * ixgbe_set_rar_generic - Set Rx address register 1229 * @hw: pointer to hardware structure 1230 * @index: Receive address register to write 1231 * @addr: Address to put into receive address register 1232 * @vmdq: VMDq "set" or "pool" index 1233 * @enable_addr: set flag that address is active 1234 * 1235 * Puts an ethernet address into a receive address register. 1236 **/ 1237 s32 ixgbe_set_rar_generic(struct ixgbe_hw *hw, u32 index, u8 *addr, u32 vmdq, 1238 u32 enable_addr) 1239 { 1240 u32 rar_low, rar_high; 1241 u32 rar_entries = hw->mac.num_rar_entries; 1242 1243 /* setup VMDq pool selection before this RAR gets enabled */ 1244 hw->mac.ops.set_vmdq(hw, index, vmdq); 1245 1246 /* Make sure we are using a valid rar index range */ 1247 if (index < rar_entries) { 1248 /* 1249 * HW expects these in little endian so we reverse the byte 1250 * order from network order (big endian) to little endian 1251 */ 1252 rar_low = ((u32)addr[0] | 1253 ((u32)addr[1] << 8) | 1254 ((u32)addr[2] << 16) | 1255 ((u32)addr[3] << 24)); 1256 /* 1257 * Some parts put the VMDq setting in the extra RAH bits, 1258 * so save everything except the lower 16 bits that hold part 1259 * of the address and the address valid bit. 1260 */ 1261 rar_high = IXGBE_READ_REG(hw, IXGBE_RAH(index)); 1262 rar_high &= ~(0x0000FFFF | IXGBE_RAH_AV); 1263 rar_high |= ((u32)addr[4] | ((u32)addr[5] << 8)); 1264 1265 if (enable_addr != 0) 1266 rar_high |= IXGBE_RAH_AV; 1267 1268 IXGBE_WRITE_REG(hw, IXGBE_RAL(index), rar_low); 1269 IXGBE_WRITE_REG(hw, IXGBE_RAH(index), rar_high); 1270 } else { 1271 DEBUGOUT1("RAR index %d is out of range.\n", index); 1272 } 1273 1274 return IXGBE_SUCCESS; 1275 } 1276 1277 /** 1278 * ixgbe_clear_rar_generic - Remove Rx address register 1279 * @hw: pointer to hardware structure 1280 * @index: Receive address register to write 1281 * 1282 * Clears an ethernet address from a receive address register. 1283 **/ 1284 s32 ixgbe_clear_rar_generic(struct ixgbe_hw *hw, u32 index) 1285 { 1286 u32 rar_high; 1287 u32 rar_entries = hw->mac.num_rar_entries; 1288 1289 /* Make sure we are using a valid rar index range */ 1290 if (index < rar_entries) { 1291 /* 1292 * Some parts put the VMDq setting in the extra RAH bits, 1293 * so save everything except the lower 16 bits that hold part 1294 * of the address and the address valid bit. 1295 */ 1296 rar_high = IXGBE_READ_REG(hw, IXGBE_RAH(index)); 1297 rar_high &= ~(0x0000FFFF | IXGBE_RAH_AV); 1298 1299 IXGBE_WRITE_REG(hw, IXGBE_RAL(index), 0); 1300 IXGBE_WRITE_REG(hw, IXGBE_RAH(index), rar_high); 1301 } else { 1302 DEBUGOUT1("RAR index %d is out of range.\n", index); 1303 } 1304 1305 /* clear VMDq pool/queue selection for this RAR */ 1306 hw->mac.ops.clear_vmdq(hw, index, IXGBE_CLEAR_VMDQ_ALL); 1307 1308 return IXGBE_SUCCESS; 1309 } 1310 1311 /** 1312 * ixgbe_init_rx_addrs_generic - Initializes receive address filters. 1313 * @hw: pointer to hardware structure 1314 * 1315 * Places the MAC address in receive address register 0 and clears the rest 1316 * of the receive address registers. Clears the multicast table. Assumes 1317 * the receiver is in reset when the routine is called. 1318 **/ 1319 s32 ixgbe_init_rx_addrs_generic(struct ixgbe_hw *hw) 1320 { 1321 u32 i; 1322 u32 rar_entries = hw->mac.num_rar_entries; 1323 1324 /* 1325 * If the current mac address is valid, assume it is a software override 1326 * to the permanent address. 1327 * Otherwise, use the permanent address from the eeprom. 1328 */ 1329 if (ixgbe_validate_mac_addr(hw->mac.addr) == 1330 IXGBE_ERR_INVALID_MAC_ADDR) { 1331 /* Get the MAC address from the RAR0 for later reference */ 1332 hw->mac.ops.get_mac_addr(hw, hw->mac.addr); 1333 1334 DEBUGOUT3(" Keeping Current RAR0 Addr =%.2X %.2X %.2X ", 1335 hw->mac.addr[0], hw->mac.addr[1], 1336 hw->mac.addr[2]); 1337 DEBUGOUT3("%.2X %.2X %.2X\n", hw->mac.addr[3], 1338 hw->mac.addr[4], hw->mac.addr[5]); 1339 } else { 1340 /* Setup the receive address. */ 1341 DEBUGOUT("Overriding MAC Address in RAR[0]\n"); 1342 DEBUGOUT3(" New MAC Addr =%.2X %.2X %.2X ", 1343 hw->mac.addr[0], hw->mac.addr[1], 1344 hw->mac.addr[2]); 1345 DEBUGOUT3("%.2X %.2X %.2X\n", hw->mac.addr[3], 1346 hw->mac.addr[4], hw->mac.addr[5]); 1347 1348 hw->mac.ops.set_rar(hw, 0, hw->mac.addr, 0, IXGBE_RAH_AV); 1349 } 1350 hw->addr_ctrl.overflow_promisc = 0; 1351 1352 hw->addr_ctrl.rar_used_count = 1; 1353 1354 /* Zero out the other receive addresses. */ 1355 DEBUGOUT1("Clearing RAR[1-%d]\n", rar_entries - 1); 1356 for (i = 1; i < rar_entries; i++) { 1357 IXGBE_WRITE_REG(hw, IXGBE_RAL(i), 0); 1358 IXGBE_WRITE_REG(hw, IXGBE_RAH(i), 0); 1359 } 1360 1361 /* Clear the MTA */ 1362 hw->addr_ctrl.mta_in_use = 0; 1363 IXGBE_WRITE_REG(hw, IXGBE_MCSTCTRL, hw->mac.mc_filter_type); 1364 1365 DEBUGOUT(" Clearing MTA\n"); 1366 for (i = 0; i < hw->mac.mcft_size; i++) 1367 IXGBE_WRITE_REG(hw, IXGBE_MTA(i), 0); 1368 1369 ixgbe_init_uta_tables(hw); 1370 1371 return IXGBE_SUCCESS; 1372 } 1373 1374 /** 1375 * ixgbe_add_uc_addr - Adds a secondary unicast address. 1376 * @hw: pointer to hardware structure 1377 * @addr: new address 1378 * 1379 * Adds it to unused receive address register or goes into promiscuous mode. 1380 **/ 1381 void ixgbe_add_uc_addr(struct ixgbe_hw *hw, u8 *addr, u32 vmdq) 1382 { 1383 u32 rar_entries = hw->mac.num_rar_entries; 1384 u32 rar; 1385 1386 DEBUGOUT6(" UC Addr = %.2X %.2X %.2X %.2X %.2X %.2X\n", 1387 addr[0], addr[1], addr[2], addr[3], addr[4], addr[5]); 1388 1389 /* 1390 * Place this address in the RAR if there is room, 1391 * else put the controller into promiscuous mode 1392 */ 1393 if (hw->addr_ctrl.rar_used_count < rar_entries) { 1394 rar = hw->addr_ctrl.rar_used_count; 1395 hw->mac.ops.set_rar(hw, rar, addr, vmdq, IXGBE_RAH_AV); 1396 DEBUGOUT1("Added a secondary address to RAR[%d]\n", rar); 1397 hw->addr_ctrl.rar_used_count++; 1398 } else { 1399 hw->addr_ctrl.overflow_promisc++; 1400 } 1401 1402 DEBUGOUT("ixgbe_add_uc_addr Complete\n"); 1403 } 1404 1405 /** 1406 * ixgbe_update_uc_addr_list_generic - Updates MAC list of secondary addresses 1407 * @hw: pointer to hardware structure 1408 * @addr_list: the list of new addresses 1409 * @addr_count: number of addresses 1410 * @next: iterator function to walk the address list 1411 * 1412 * The given list replaces any existing list. Clears the secondary addrs from 1413 * receive address registers. Uses unused receive address registers for the 1414 * first secondary addresses, and falls back to promiscuous mode as needed. 1415 * 1416 * Drivers using secondary unicast addresses must set user_set_promisc when 1417 * manually putting the device into promiscuous mode. 1418 **/ 1419 s32 ixgbe_update_uc_addr_list_generic(struct ixgbe_hw *hw, u8 *addr_list, 1420 u32 addr_count, ixgbe_mc_addr_itr next) 1421 { 1422 u8 *addr; 1423 u32 i; 1424 u32 old_promisc_setting = hw->addr_ctrl.overflow_promisc; 1425 u32 uc_addr_in_use; 1426 u32 fctrl; 1427 u32 vmdq; 1428 1429 /* 1430 * Clear accounting of old secondary address list, 1431 * don't count RAR[0] 1432 */ 1433 uc_addr_in_use = hw->addr_ctrl.rar_used_count - 1; 1434 hw->addr_ctrl.rar_used_count -= uc_addr_in_use; 1435 hw->addr_ctrl.overflow_promisc = 0; 1436 1437 /* Zero out the other receive addresses */ 1438 DEBUGOUT1("Clearing RAR[1-%d]\n", hw->addr_ctrl.rar_used_count); 1439 for (i = 1; i <= hw->addr_ctrl.rar_used_count; i++) { 1440 IXGBE_WRITE_REG(hw, IXGBE_RAL(i), 0); 1441 IXGBE_WRITE_REG(hw, IXGBE_RAH(i), 0); 1442 } 1443 1444 /* Add the new addresses */ 1445 for (i = 0; i < addr_count; i++) { 1446 DEBUGOUT(" Adding the secondary addresses:\n"); 1447 addr = next(hw, &addr_list, &vmdq); 1448 ixgbe_add_uc_addr(hw, addr, vmdq); 1449 } 1450 1451 if (hw->addr_ctrl.overflow_promisc) { 1452 /* enable promisc if not already in overflow or set by user */ 1453 if (!old_promisc_setting && !hw->addr_ctrl.user_set_promisc) { 1454 DEBUGOUT(" Entering address overflow promisc mode\n"); 1455 fctrl = IXGBE_READ_REG(hw, IXGBE_FCTRL); 1456 fctrl |= IXGBE_FCTRL_UPE; 1457 IXGBE_WRITE_REG(hw, IXGBE_FCTRL, fctrl); 1458 } 1459 } else { 1460 /* only disable if set by overflow, not by user */ 1461 if (old_promisc_setting && !hw->addr_ctrl.user_set_promisc) { 1462 DEBUGOUT(" Leaving address overflow promisc mode\n"); 1463 fctrl = IXGBE_READ_REG(hw, IXGBE_FCTRL); 1464 fctrl &= ~IXGBE_FCTRL_UPE; 1465 IXGBE_WRITE_REG(hw, IXGBE_FCTRL, fctrl); 1466 } 1467 } 1468 1469 DEBUGOUT("ixgbe_update_uc_addr_list_generic Complete\n"); 1470 return IXGBE_SUCCESS; 1471 } 1472 1473 /** 1474 * ixgbe_mta_vector - Determines bit-vector in multicast table to set 1475 * @hw: pointer to hardware structure 1476 * @mc_addr: the multicast address 1477 * 1478 * Extracts the 12 bits, from a multicast address, to determine which 1479 * bit-vector to set in the multicast table. The hardware uses 12 bits, from 1480 * incoming rx multicast addresses, to determine the bit-vector to check in 1481 * the MTA. Which of the 4 combination, of 12-bits, the hardware uses is set 1482 * by the MO field of the MCSTCTRL. The MO field is set during initialization 1483 * to mc_filter_type. 1484 **/ 1485 static s32 ixgbe_mta_vector(struct ixgbe_hw *hw, u8 *mc_addr) 1486 { 1487 u32 vector = 0; 1488 1489 switch (hw->mac.mc_filter_type) { 1490 case 0: /* use bits [47:36] of the address */ 1491 vector = ((mc_addr[4] >> 4) | (((u16)mc_addr[5]) << 4)); 1492 break; 1493 case 1: /* use bits [46:35] of the address */ 1494 vector = ((mc_addr[4] >> 3) | (((u16)mc_addr[5]) << 5)); 1495 break; 1496 case 2: /* use bits [45:34] of the address */ 1497 vector = ((mc_addr[4] >> 2) | (((u16)mc_addr[5]) << 6)); 1498 break; 1499 case 3: /* use bits [43:32] of the address */ 1500 vector = ((mc_addr[4]) | (((u16)mc_addr[5]) << 8)); 1501 break; 1502 default: /* Invalid mc_filter_type */ 1503 DEBUGOUT("MC filter type param set incorrectly\n"); 1504 ASSERT(0); 1505 break; 1506 } 1507 1508 /* vector can only be 12-bits or boundary will be exceeded */ 1509 vector &= 0xFFF; 1510 return vector; 1511 } 1512 1513 /** 1514 * ixgbe_set_mta - Set bit-vector in multicast table 1515 * @hw: pointer to hardware structure 1516 * @hash_value: Multicast address hash value 1517 * 1518 * Sets the bit-vector in the multicast table. 1519 **/ 1520 void ixgbe_set_mta(struct ixgbe_hw *hw, u8 *mc_addr) 1521 { 1522 u32 vector; 1523 u32 vector_bit; 1524 u32 vector_reg; 1525 u32 mta_reg; 1526 1527 hw->addr_ctrl.mta_in_use++; 1528 1529 vector = ixgbe_mta_vector(hw, mc_addr); 1530 DEBUGOUT1(" bit-vector = 0x%03X\n", vector); 1531 1532 /* 1533 * The MTA is a register array of 128 32-bit registers. It is treated 1534 * like an array of 4096 bits. We want to set bit 1535 * BitArray[vector_value]. So we figure out what register the bit is 1536 * in, read it, OR in the new bit, then write back the new value. The 1537 * register is determined by the upper 7 bits of the vector value and 1538 * the bit within that register are determined by the lower 5 bits of 1539 * the value. 1540 */ 1541 vector_reg = (vector >> 5) & 0x7F; 1542 vector_bit = vector & 0x1F; 1543 mta_reg = IXGBE_READ_REG(hw, IXGBE_MTA(vector_reg)); 1544 mta_reg |= (1 << vector_bit); 1545 IXGBE_WRITE_REG(hw, IXGBE_MTA(vector_reg), mta_reg); 1546 } 1547 1548 /** 1549 * ixgbe_update_mc_addr_list_generic - Updates MAC list of multicast addresses 1550 * @hw: pointer to hardware structure 1551 * @mc_addr_list: the list of new multicast addresses 1552 * @mc_addr_count: number of addresses 1553 * @next: iterator function to walk the multicast address list 1554 * 1555 * The given list replaces any existing list. Clears the MC addrs from receive 1556 * address registers and the multicast table. Uses unused receive address 1557 * registers for the first multicast addresses, and hashes the rest into the 1558 * multicast table. 1559 **/ 1560 s32 ixgbe_update_mc_addr_list_generic(struct ixgbe_hw *hw, u8 *mc_addr_list, 1561 u32 mc_addr_count, ixgbe_mc_addr_itr next) 1562 { 1563 u32 i; 1564 u32 vmdq; 1565 1566 /* 1567 * Set the new number of MC addresses that we are being requested to 1568 * use. 1569 */ 1570 hw->addr_ctrl.num_mc_addrs = mc_addr_count; 1571 hw->addr_ctrl.mta_in_use = 0; 1572 1573 /* Clear the MTA */ 1574 DEBUGOUT(" Clearing MTA\n"); 1575 for (i = 0; i < hw->mac.mcft_size; i++) 1576 IXGBE_WRITE_REG(hw, IXGBE_MTA(i), 0); 1577 1578 /* Add the new addresses */ 1579 for (i = 0; i < mc_addr_count; i++) { 1580 DEBUGOUT(" Adding the multicast addresses:\n"); 1581 ixgbe_set_mta(hw, next(hw, &mc_addr_list, &vmdq)); 1582 } 1583 1584 /* Enable mta */ 1585 if (hw->addr_ctrl.mta_in_use > 0) 1586 IXGBE_WRITE_REG(hw, IXGBE_MCSTCTRL, 1587 IXGBE_MCSTCTRL_MFE | hw->mac.mc_filter_type); 1588 1589 DEBUGOUT("ixgbe_update_mc_addr_list_generic Complete\n"); 1590 return IXGBE_SUCCESS; 1591 } 1592 1593 /** 1594 * ixgbe_enable_mc_generic - Enable multicast address in RAR 1595 * @hw: pointer to hardware structure 1596 * 1597 * Enables multicast address in RAR and the use of the multicast hash table. 1598 **/ 1599 s32 ixgbe_enable_mc_generic(struct ixgbe_hw *hw) 1600 { 1601 struct ixgbe_addr_filter_info *a = &hw->addr_ctrl; 1602 1603 if (a->mta_in_use > 0) 1604 IXGBE_WRITE_REG(hw, IXGBE_MCSTCTRL, IXGBE_MCSTCTRL_MFE | 1605 hw->mac.mc_filter_type); 1606 1607 return IXGBE_SUCCESS; 1608 } 1609 1610 /** 1611 * ixgbe_disable_mc_generic - Disable multicast address in RAR 1612 * @hw: pointer to hardware structure 1613 * 1614 * Disables multicast address in RAR and the use of the multicast hash table. 1615 **/ 1616 s32 ixgbe_disable_mc_generic(struct ixgbe_hw *hw) 1617 { 1618 struct ixgbe_addr_filter_info *a = &hw->addr_ctrl; 1619 1620 if (a->mta_in_use > 0) 1621 IXGBE_WRITE_REG(hw, IXGBE_MCSTCTRL, hw->mac.mc_filter_type); 1622 1623 return IXGBE_SUCCESS; 1624 } 1625 1626 /** 1627 * ixgbe_fc_enable_generic - Enable flow control 1628 * @hw: pointer to hardware structure 1629 * @packetbuf_num: packet buffer number (0-7) 1630 * 1631 * Enable flow control according to the current settings. 1632 **/ 1633 s32 ixgbe_fc_enable_generic(struct ixgbe_hw *hw, s32 packetbuf_num) 1634 { 1635 s32 ret_val = IXGBE_SUCCESS; 1636 u32 mflcn_reg, fccfg_reg; 1637 u32 reg; 1638 u32 rx_pba_size; 1639 1640 DEBUGFUNC("ixgbe_fc_enable_generic"); 1641 1642 /* Negotiate the fc mode to use */ 1643 ret_val = ixgbe_fc_autoneg(hw); 1644 if (ret_val) 1645 goto out; 1646 1647 /* Disable any previous flow control settings */ 1648 mflcn_reg = IXGBE_READ_REG(hw, IXGBE_MFLCN); 1649 mflcn_reg &= ~(IXGBE_MFLCN_RFCE | IXGBE_MFLCN_RPFCE); 1650 1651 fccfg_reg = IXGBE_READ_REG(hw, IXGBE_FCCFG); 1652 fccfg_reg &= ~(IXGBE_FCCFG_TFCE_802_3X | IXGBE_FCCFG_TFCE_PRIORITY); 1653 1654 /* 1655 * The possible values of fc.current_mode are: 1656 * 0: Flow control is completely disabled 1657 * 1: Rx flow control is enabled (we can receive pause frames, 1658 * but not send pause frames). 1659 * 2: Tx flow control is enabled (we can send pause frames but 1660 * we do not support receiving pause frames). 1661 * 3: Both Rx and Tx flow control (symmetric) are enabled. 1662 * other: Invalid. 1663 */ 1664 switch (hw->fc.current_mode) { 1665 case ixgbe_fc_none: 1666 /* Flow control is disabled by software override or autoneg. 1667 * The code below will actually disable it in the HW. 1668 */ 1669 break; 1670 case ixgbe_fc_rx_pause: 1671 /* 1672 * Rx Flow control is enabled and Tx Flow control is 1673 * disabled by software override. Since there really 1674 * isn't a way to advertise that we are capable of RX 1675 * Pause ONLY, we will advertise that we support both 1676 * symmetric and asymmetric Rx PAUSE. Later, we will 1677 * disable the adapter's ability to send PAUSE frames. 1678 */ 1679 mflcn_reg |= IXGBE_MFLCN_RFCE; 1680 break; 1681 case ixgbe_fc_tx_pause: 1682 /* 1683 * Tx Flow control is enabled, and Rx Flow control is 1684 * disabled by software override. 1685 */ 1686 fccfg_reg |= IXGBE_FCCFG_TFCE_802_3X; 1687 break; 1688 case ixgbe_fc_full: 1689 /* Flow control (both Rx and Tx) is enabled by SW override. */ 1690 mflcn_reg |= IXGBE_MFLCN_RFCE; 1691 fccfg_reg |= IXGBE_FCCFG_TFCE_802_3X; 1692 break; 1693 default: 1694 DEBUGOUT("Flow control param set incorrectly\n"); 1695 ret_val = -IXGBE_ERR_CONFIG; 1696 goto out; 1697 break; 1698 } 1699 1700 /* Set 802.3x based flow control settings. */ 1701 mflcn_reg |= IXGBE_MFLCN_DPF; 1702 IXGBE_WRITE_REG(hw, IXGBE_MFLCN, mflcn_reg); 1703 IXGBE_WRITE_REG(hw, IXGBE_FCCFG, fccfg_reg); 1704 1705 reg = IXGBE_READ_REG(hw, IXGBE_MTQC); 1706 /* Thresholds are different for link flow control when in DCB mode */ 1707 if (reg & IXGBE_MTQC_RT_ENA) { 1708 rx_pba_size = IXGBE_READ_REG(hw, IXGBE_RXPBSIZE(packetbuf_num)); 1709 1710 /* Always disable XON for LFC when in DCB mode */ 1711 reg = (rx_pba_size >> 5) & 0xFFE0; 1712 IXGBE_WRITE_REG(hw, IXGBE_FCRTL_82599(packetbuf_num), reg); 1713 1714 reg = (rx_pba_size >> 2) & 0xFFE0; 1715 if (hw->fc.current_mode & ixgbe_fc_tx_pause) 1716 reg |= IXGBE_FCRTH_FCEN; 1717 IXGBE_WRITE_REG(hw, IXGBE_FCRTH_82599(packetbuf_num), reg); 1718 } else { 1719 /* Set up and enable Rx high/low water mark thresholds, 1720 * enable XON. */ 1721 if (hw->fc.current_mode & ixgbe_fc_tx_pause) { 1722 if (hw->fc.send_xon) { 1723 IXGBE_WRITE_REG(hw, 1724 IXGBE_FCRTL_82599(packetbuf_num), 1725 (hw->fc.low_water | 1726 IXGBE_FCRTL_XONE)); 1727 } else { 1728 IXGBE_WRITE_REG(hw, 1729 IXGBE_FCRTL_82599(packetbuf_num), 1730 hw->fc.low_water); 1731 } 1732 1733 IXGBE_WRITE_REG(hw, IXGBE_FCRTH_82599(packetbuf_num), 1734 (hw->fc.high_water | IXGBE_FCRTH_FCEN)); 1735 } 1736 } 1737 1738 /* Configure pause time (2 TCs per register) */ 1739 reg = IXGBE_READ_REG(hw, IXGBE_FCTTV(packetbuf_num / 2)); 1740 if ((packetbuf_num & 1) == 0) 1741 reg = (reg & 0xFFFF0000) | hw->fc.pause_time; 1742 else 1743 reg = (reg & 0x0000FFFF) | (hw->fc.pause_time << 16); 1744 IXGBE_WRITE_REG(hw, IXGBE_FCTTV(packetbuf_num / 2), reg); 1745 1746 IXGBE_WRITE_REG(hw, IXGBE_FCRTV, (hw->fc.pause_time >> 1)); 1747 1748 out: 1749 return ret_val; 1750 } 1751 1752 /** 1753 * ixgbe_fc_autoneg - Configure flow control 1754 * @hw: pointer to hardware structure 1755 * 1756 * Compares our advertised flow control capabilities to those advertised by 1757 * our link partner, and determines the proper flow control mode to use. 1758 **/ 1759 s32 ixgbe_fc_autoneg(struct ixgbe_hw *hw) 1760 { 1761 s32 ret_val = IXGBE_SUCCESS; 1762 ixgbe_link_speed speed; 1763 u32 pcs_anadv_reg, pcs_lpab_reg, linkstat; 1764 bool link_up; 1765 1766 DEBUGFUNC("ixgbe_fc_autoneg"); 1767 1768 /* 1769 * AN should have completed when the cable was plugged in. 1770 * Look for reasons to bail out. Bail out if: 1771 * - FC autoneg is disabled, or if 1772 * - we don't have multispeed fiber, or if 1773 * - we're not running at 1G, or if 1774 * - link is not up, or if 1775 * - link is up but AN did not complete, or if 1776 * - link is up and AN completed but timed out 1777 * 1778 * Since we're being called from an LSC, link is already know to be up. 1779 * So use link_up_wait_to_complete=FALSE. 1780 */ 1781 hw->mac.ops.check_link(hw, &speed, &link_up, FALSE); 1782 linkstat = IXGBE_READ_REG(hw, IXGBE_PCS1GLSTA); 1783 1784 if (hw->fc.disable_fc_autoneg || 1785 !hw->phy.multispeed_fiber || 1786 (speed != IXGBE_LINK_SPEED_1GB_FULL) || 1787 !link_up || 1788 ((linkstat & IXGBE_PCS1GLSTA_AN_COMPLETE) == 0) || 1789 ((linkstat & IXGBE_PCS1GLSTA_AN_TIMED_OUT) == 1)) { 1790 hw->fc.fc_was_autonegged = FALSE; 1791 hw->fc.current_mode = hw->fc.requested_mode; 1792 DEBUGOUT("Autoneg FC was skipped.\n"); 1793 goto out; 1794 } 1795 1796 /* 1797 * Read the AN advertisement and LP ability registers and resolve 1798 * local flow control settings accordingly 1799 */ 1800 pcs_anadv_reg = IXGBE_READ_REG(hw, IXGBE_PCS1GANA); 1801 pcs_lpab_reg = IXGBE_READ_REG(hw, IXGBE_PCS1GANLP); 1802 if ((pcs_anadv_reg & IXGBE_PCS1GANA_SYM_PAUSE) && 1803 (pcs_lpab_reg & IXGBE_PCS1GANA_SYM_PAUSE)) { 1804 /* 1805 * Now we need to check if the user selected Rx ONLY 1806 * of pause frames. In this case, we had to advertise 1807 * FULL flow control because we could not advertise RX 1808 * ONLY. Hence, we must now check to see if we need to 1809 * turn OFF the TRANSMISSION of PAUSE frames. 1810 */ 1811 if (hw->fc.requested_mode == ixgbe_fc_full) { 1812 hw->fc.current_mode = ixgbe_fc_full; 1813 DEBUGOUT("Flow Control = FULL.\n"); 1814 } else { 1815 hw->fc.current_mode = ixgbe_fc_rx_pause; 1816 DEBUGOUT("Flow Control = RX PAUSE frames only.\n"); 1817 } 1818 } else if (!(pcs_anadv_reg & IXGBE_PCS1GANA_SYM_PAUSE) && 1819 (pcs_anadv_reg & IXGBE_PCS1GANA_ASM_PAUSE) && 1820 (pcs_lpab_reg & IXGBE_PCS1GANA_SYM_PAUSE) && 1821 (pcs_lpab_reg & IXGBE_PCS1GANA_ASM_PAUSE)) { 1822 hw->fc.current_mode = ixgbe_fc_tx_pause; 1823 DEBUGOUT("Flow Control = TX PAUSE frames only.\n"); 1824 } else if ((pcs_anadv_reg & IXGBE_PCS1GANA_SYM_PAUSE) && 1825 (pcs_anadv_reg & IXGBE_PCS1GANA_ASM_PAUSE) && 1826 !(pcs_lpab_reg & IXGBE_PCS1GANA_SYM_PAUSE) && 1827 (pcs_lpab_reg & IXGBE_PCS1GANA_ASM_PAUSE)) { 1828 hw->fc.current_mode = ixgbe_fc_rx_pause; 1829 DEBUGOUT("Flow Control = RX PAUSE frames only.\n"); 1830 } else { 1831 hw->fc.current_mode = ixgbe_fc_none; 1832 DEBUGOUT("Flow Control = NONE.\n"); 1833 } 1834 1835 /* Record that current_mode is the result of a successful autoneg */ 1836 hw->fc.fc_was_autonegged = TRUE; 1837 1838 out: 1839 return ret_val; 1840 } 1841 1842 /** 1843 * ixgbe_setup_fc - Set up flow control 1844 * @hw: pointer to hardware structure 1845 * 1846 * Called at init time to set up flow control. 1847 **/ 1848 s32 ixgbe_setup_fc(struct ixgbe_hw *hw, s32 packetbuf_num) 1849 { 1850 s32 ret_val = IXGBE_SUCCESS; 1851 u32 reg; 1852 1853 1854 /* Validate the packetbuf configuration */ 1855 if (packetbuf_num < 0 || packetbuf_num > 7) { 1856 DEBUGOUT1("Invalid packet buffer number [%d], expected range is" 1857 " 0-7\n", packetbuf_num); 1858 ret_val = IXGBE_ERR_INVALID_LINK_SETTINGS; 1859 goto out; 1860 } 1861 1862 /* 1863 * Validate the water mark configuration. Zero water marks are invalid 1864 * because it causes the controller to just blast out fc packets. 1865 */ 1866 if (!hw->fc.low_water || !hw->fc.high_water || !hw->fc.pause_time) { 1867 DEBUGOUT("Invalid water mark configuration\n"); 1868 ret_val = IXGBE_ERR_INVALID_LINK_SETTINGS; 1869 goto out; 1870 } 1871 1872 /* 1873 * Validate the requested mode. Strict IEEE mode does not allow 1874 * ixgbe_fc_rx_pause because it will cause us to fail at UNH. 1875 */ 1876 if (hw->fc.strict_ieee && hw->fc.requested_mode == ixgbe_fc_rx_pause) { 1877 DEBUGOUT("ixgbe_fc_rx_pause not valid in strict IEEE mode\n"); 1878 ret_val = IXGBE_ERR_INVALID_LINK_SETTINGS; 1879 goto out; 1880 } 1881 1882 /* 1883 * 10gig parts do not have a word in the EEPROM to determine the 1884 * default flow control setting, so we explicitly set it to full. 1885 */ 1886 if (hw->fc.requested_mode == ixgbe_fc_default) 1887 hw->fc.requested_mode = ixgbe_fc_full; 1888 1889 /* 1890 * Set up the 1G flow control advertisement registers so the HW will be 1891 * able to do fc autoneg once the cable is plugged in. If we end up 1892 * using 10g instead, this is harmless. 1893 */ 1894 reg = IXGBE_READ_REG(hw, IXGBE_PCS1GANA); 1895 1896 /* 1897 * The possible values of fc.requested_mode are: 1898 * 0: Flow control is completely disabled 1899 * 1: Rx flow control is enabled (we can receive pause frames, 1900 * but not send pause frames). 1901 * 2: Tx flow control is enabled (we can send pause frames but 1902 * we do not support receiving pause frames). 1903 * 3: Both Rx and Tx flow control (symmetric) are enabled. 1904 * other: Invalid. 1905 */ 1906 switch (hw->fc.requested_mode) { 1907 case ixgbe_fc_none: 1908 /* Flow control completely disabled by software override. */ 1909 reg &= ~(IXGBE_PCS1GANA_SYM_PAUSE | IXGBE_PCS1GANA_ASM_PAUSE); 1910 break; 1911 case ixgbe_fc_rx_pause: 1912 /* 1913 * Rx Flow control is enabled and Tx Flow control is 1914 * disabled by software override. Since there really 1915 * isn't a way to advertise that we are capable of RX 1916 * Pause ONLY, we will advertise that we support both 1917 * symmetric and asymmetric Rx PAUSE. Later, we will 1918 * disable the adapter's ability to send PAUSE frames. 1919 */ 1920 reg |= (IXGBE_PCS1GANA_SYM_PAUSE | IXGBE_PCS1GANA_ASM_PAUSE); 1921 break; 1922 case ixgbe_fc_tx_pause: 1923 /* 1924 * Tx Flow control is enabled, and Rx Flow control is 1925 * disabled by software override. 1926 */ 1927 reg |= (IXGBE_PCS1GANA_ASM_PAUSE); 1928 reg &= ~(IXGBE_PCS1GANA_SYM_PAUSE); 1929 break; 1930 case ixgbe_fc_full: 1931 /* Flow control (both Rx and Tx) is enabled by SW override. */ 1932 reg |= (IXGBE_PCS1GANA_SYM_PAUSE | IXGBE_PCS1GANA_ASM_PAUSE); 1933 break; 1934 default: 1935 DEBUGOUT("Flow control param set incorrectly\n"); 1936 ret_val = -IXGBE_ERR_CONFIG; 1937 goto out; 1938 break; 1939 } 1940 1941 IXGBE_WRITE_REG(hw, IXGBE_PCS1GANA, reg); 1942 reg = IXGBE_READ_REG(hw, IXGBE_PCS1GLCTL); 1943 1944 /* Enable and restart autoneg to inform the link partner */ 1945 reg |= IXGBE_PCS1GLCTL_AN_ENABLE | IXGBE_PCS1GLCTL_AN_RESTART; 1946 1947 /* Disable AN timeout */ 1948 if (hw->fc.strict_ieee) 1949 reg &= ~IXGBE_PCS1GLCTL_AN_1G_TIMEOUT_EN; 1950 1951 IXGBE_WRITE_REG(hw, IXGBE_PCS1GLCTL, reg); 1952 DEBUGOUT1("Set up FC; PCS1GLCTL = 0x%08X\n", reg); 1953 1954 out: 1955 return ret_val; 1956 } 1957 1958 /** 1959 * ixgbe_disable_pcie_master - Disable PCI-express master access 1960 * @hw: pointer to hardware structure 1961 * 1962 * Disables PCI-Express master access and verifies there are no pending 1963 * requests. IXGBE_ERR_MASTER_REQUESTS_PENDING is returned if master disable 1964 * bit hasn't caused the master requests to be disabled, else IXGBE_SUCCESS 1965 * is returned signifying master requests disabled. 1966 **/ 1967 s32 ixgbe_disable_pcie_master(struct ixgbe_hw *hw) 1968 { 1969 u32 i; 1970 u32 reg_val; 1971 u32 number_of_queues; 1972 s32 status = IXGBE_ERR_MASTER_REQUESTS_PENDING; 1973 1974 /* Disable the receive unit by stopping each queue */ 1975 number_of_queues = hw->mac.max_rx_queues; 1976 for (i = 0; i < number_of_queues; i++) { 1977 reg_val = IXGBE_READ_REG(hw, IXGBE_RXDCTL(i)); 1978 if (reg_val & IXGBE_RXDCTL_ENABLE) { 1979 reg_val &= ~IXGBE_RXDCTL_ENABLE; 1980 IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(i), reg_val); 1981 } 1982 } 1983 1984 reg_val = IXGBE_READ_REG(hw, IXGBE_CTRL); 1985 reg_val |= IXGBE_CTRL_GIO_DIS; 1986 IXGBE_WRITE_REG(hw, IXGBE_CTRL, reg_val); 1987 1988 for (i = 0; i < IXGBE_PCI_MASTER_DISABLE_TIMEOUT; i++) { 1989 if (!(IXGBE_READ_REG(hw, IXGBE_STATUS) & IXGBE_STATUS_GIO)) { 1990 status = IXGBE_SUCCESS; 1991 break; 1992 } 1993 usec_delay(100); 1994 } 1995 1996 return status; 1997 } 1998 1999 2000 /** 2001 * ixgbe_acquire_swfw_sync - Acquire SWFW semaphore 2002 * @hw: pointer to hardware structure 2003 * @mask: Mask to specify which semaphore to acquire 2004 * 2005 * Acquires the SWFW semaphore thought the GSSR register for the specified 2006 * function (CSR, PHY0, PHY1, EEPROM, Flash) 2007 **/ 2008 s32 ixgbe_acquire_swfw_sync(struct ixgbe_hw *hw, u16 mask) 2009 { 2010 u32 gssr; 2011 u32 swmask = mask; 2012 u32 fwmask = mask << 5; 2013 s32 timeout = 200; 2014 2015 while (timeout) { 2016 /* 2017 * SW EEPROM semaphore bit is used for access to all 2018 * SW_FW_SYNC/GSSR bits (not just EEPROM) 2019 */ 2020 if (ixgbe_get_eeprom_semaphore(hw)) 2021 return -IXGBE_ERR_SWFW_SYNC; 2022 2023 gssr = IXGBE_READ_REG(hw, IXGBE_GSSR); 2024 if (!(gssr & (fwmask | swmask))) 2025 break; 2026 2027 /* 2028 * Firmware currently using resource (fwmask) or other software 2029 * thread currently using resource (swmask) 2030 */ 2031 ixgbe_release_eeprom_semaphore(hw); 2032 msec_delay(5); 2033 timeout--; 2034 } 2035 2036 if (!timeout) { 2037 DEBUGOUT("Driver can't access resource, SW_FW_SYNC timeout.\n"); 2038 return -IXGBE_ERR_SWFW_SYNC; 2039 } 2040 2041 gssr |= swmask; 2042 IXGBE_WRITE_REG(hw, IXGBE_GSSR, gssr); 2043 2044 ixgbe_release_eeprom_semaphore(hw); 2045 return IXGBE_SUCCESS; 2046 } 2047 2048 /** 2049 * ixgbe_release_swfw_sync - Release SWFW semaphore 2050 * @hw: pointer to hardware structure 2051 * @mask: Mask to specify which semaphore to release 2052 * 2053 * Releases the SWFW semaphore thought the GSSR register for the specified 2054 * function (CSR, PHY0, PHY1, EEPROM, Flash) 2055 **/ 2056 void ixgbe_release_swfw_sync(struct ixgbe_hw *hw, u16 mask) 2057 { 2058 u32 gssr; 2059 u32 swmask = mask; 2060 2061 ixgbe_get_eeprom_semaphore(hw); 2062 2063 gssr = IXGBE_READ_REG(hw, IXGBE_GSSR); 2064 gssr &= ~swmask; 2065 IXGBE_WRITE_REG(hw, IXGBE_GSSR, gssr); 2066 2067 ixgbe_release_eeprom_semaphore(hw); 2068 } 2069 2070 /** 2071 * ixgbe_enable_rx_dma_generic - Enable the Rx DMA unit 2072 * @hw: pointer to hardware structure 2073 * @regval: register value to write to RXCTRL 2074 * 2075 * Enables the Rx DMA unit 2076 **/ 2077 s32 ixgbe_enable_rx_dma_generic(struct ixgbe_hw *hw, u32 regval) 2078 { 2079 IXGBE_WRITE_REG(hw, IXGBE_RXCTRL, regval); 2080 2081 return IXGBE_SUCCESS; 2082 } 2083 2084 /** 2085 * ixgbe_blink_led_start_generic - Blink LED based on index. 2086 * @hw: pointer to hardware structure 2087 * @index: led number to blink 2088 **/ 2089 s32 ixgbe_blink_led_start_generic(struct ixgbe_hw *hw, u32 index) 2090 { 2091 ixgbe_link_speed speed = 0; 2092 bool link_up = 0; 2093 u32 autoc_reg = IXGBE_READ_REG(hw, IXGBE_AUTOC); 2094 u32 led_reg = IXGBE_READ_REG(hw, IXGBE_LEDCTL); 2095 2096 /* 2097 * Link must be up to auto-blink the LEDs; 2098 * Force it if link is down. 2099 */ 2100 hw->mac.ops.check_link(hw, &speed, &link_up, FALSE); 2101 2102 if (!link_up) { 2103 2104 autoc_reg |= IXGBE_AUTOC_AN_RESTART; 2105 autoc_reg |= IXGBE_AUTOC_FLU; 2106 IXGBE_WRITE_REG(hw, IXGBE_AUTOC, autoc_reg); 2107 msec_delay(10); 2108 } 2109 2110 led_reg &= ~IXGBE_LED_MODE_MASK(index); 2111 led_reg |= IXGBE_LED_BLINK(index); 2112 IXGBE_WRITE_REG(hw, IXGBE_LEDCTL, led_reg); 2113 IXGBE_WRITE_FLUSH(hw); 2114 2115 return IXGBE_SUCCESS; 2116 } 2117 2118 /** 2119 * ixgbe_blink_led_stop_generic - Stop blinking LED based on index. 2120 * @hw: pointer to hardware structure 2121 * @index: led number to stop blinking 2122 **/ 2123 s32 ixgbe_blink_led_stop_generic(struct ixgbe_hw *hw, u32 index) 2124 { 2125 u32 autoc_reg = IXGBE_READ_REG(hw, IXGBE_AUTOC); 2126 u32 led_reg = IXGBE_READ_REG(hw, IXGBE_LEDCTL); 2127 2128 2129 autoc_reg &= ~IXGBE_AUTOC_FLU; 2130 autoc_reg |= IXGBE_AUTOC_AN_RESTART; 2131 IXGBE_WRITE_REG(hw, IXGBE_AUTOC, autoc_reg); 2132 2133 led_reg &= ~IXGBE_LED_MODE_MASK(index); 2134 led_reg &= ~IXGBE_LED_BLINK(index); 2135 led_reg |= IXGBE_LED_LINK_ACTIVE << IXGBE_LED_MODE_SHIFT(index); 2136 IXGBE_WRITE_REG(hw, IXGBE_LEDCTL, led_reg); 2137 IXGBE_WRITE_FLUSH(hw); 2138 2139 return IXGBE_SUCCESS; 2140 } 2141 2142