1 /******************************************************************************* 2 3 Copyright (c) 2001-2007, Intel Corporation 4 All rights reserved. 5 6 Redistribution and use in source and binary forms, with or without 7 modification, are permitted provided that the following conditions are met: 8 9 1. Redistributions of source code must retain the above copyright notice, 10 this list of conditions and the following disclaimer. 11 12 2. Redistributions in binary form must reproduce the above copyright 13 notice, this list of conditions and the following disclaimer in the 14 documentation and/or other materials provided with the distribution. 15 16 3. Neither the name of the Intel Corporation nor the names of its 17 contributors may be used to endorse or promote products derived from 18 this software without specific prior written permission. 19 20 THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 21 AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 22 IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 23 ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE 24 LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 25 CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 26 SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 27 INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 28 CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 29 ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 30 POSSIBILITY OF SUCH DAMAGE. 31 32 *******************************************************************************/ 33 /* $FreeBSD$ */ 34 35 36 #include "ixgbe_common.h" 37 #include "ixgbe_api.h" 38 39 static s32 ixgbe_poll_eeprom_eerd_done(struct ixgbe_hw *hw); 40 static s32 ixgbe_acquire_eeprom(struct ixgbe_hw *hw); 41 static s32 ixgbe_get_eeprom_semaphore(struct ixgbe_hw *hw); 42 static void ixgbe_release_eeprom_semaphore(struct ixgbe_hw *hw); 43 static s32 ixgbe_ready_eeprom(struct ixgbe_hw *hw); 44 static void ixgbe_standby_eeprom(struct ixgbe_hw *hw); 45 static void ixgbe_shift_out_eeprom_bits(struct ixgbe_hw *hw, u16 data, 46 u16 count); 47 static u16 ixgbe_shift_in_eeprom_bits(struct ixgbe_hw *hw, u16 count); 48 static void ixgbe_raise_eeprom_clk(struct ixgbe_hw *hw, u32 *eec); 49 static void ixgbe_lower_eeprom_clk(struct ixgbe_hw *hw, u32 *eec); 50 static void ixgbe_release_eeprom(struct ixgbe_hw *hw); 51 static u16 ixgbe_calc_eeprom_checksum(struct ixgbe_hw *hw); 52 53 static void ixgbe_enable_rar(struct ixgbe_hw *hw, u32 index); 54 static void ixgbe_disable_rar(struct ixgbe_hw *hw, u32 index); 55 static s32 ixgbe_mta_vector(struct ixgbe_hw *hw, u8 *mc_addr); 56 void ixgbe_add_mc_addr(struct ixgbe_hw *hw, u8 *mc_addr); 57 58 /** 59 * ixgbe_assign_func_pointers_generic - Set generic func ptrs 60 * @hw: pointer to hardware structure 61 * 62 * Assigns generic function pointers. Adapter-specific functions can 63 * override the assignment of generic function pointers by assigning 64 * their own adapter-specific function pointers. 65 **/ 66 s32 ixgbe_assign_func_pointers_generic(struct ixgbe_hw *hw) 67 { 68 struct ixgbe_functions *f = &hw->func; 69 70 f->ixgbe_func_init_hw = &ixgbe_init_hw_generic; 71 f->ixgbe_func_start_hw = &ixgbe_start_hw_generic; 72 f->ixgbe_func_clear_hw_cntrs = &ixgbe_clear_hw_cntrs_generic; 73 f->ixgbe_func_get_mac_addr = &ixgbe_get_mac_addr_generic; 74 f->ixgbe_func_stop_adapter = &ixgbe_stop_adapter_generic; 75 f->ixgbe_func_get_bus_info = &ixgbe_get_bus_info_generic; 76 /* LED */ 77 f->ixgbe_func_led_on = &ixgbe_led_on_generic; 78 f->ixgbe_func_led_off = &ixgbe_led_off_generic; 79 /* EEPROM */ 80 f->ixgbe_func_init_eeprom_params = &ixgbe_init_eeprom_params_generic; 81 f->ixgbe_func_read_eeprom = &ixgbe_read_eeprom_bit_bang_generic; 82 f->ixgbe_func_write_eeprom = &ixgbe_write_eeprom_generic; 83 f->ixgbe_func_validate_eeprom_checksum = 84 &ixgbe_validate_eeprom_checksum_generic; 85 f->ixgbe_func_update_eeprom_checksum = 86 &ixgbe_update_eeprom_checksum_generic; 87 /* RAR, Multicast, VLAN */ 88 f->ixgbe_func_set_rar = &ixgbe_set_rar_generic; 89 f->ixgbe_func_init_rx_addrs = &ixgbe_init_rx_addrs_generic; 90 f->ixgbe_func_update_mc_addr_list = &ixgbe_update_mc_addr_list_generic; 91 f->ixgbe_func_enable_mc = &ixgbe_enable_mc_generic; 92 f->ixgbe_func_disable_mc = &ixgbe_disable_mc_generic; 93 f->ixgbe_func_clear_vfta = &ixgbe_clear_vfta_generic; 94 f->ixgbe_func_set_vfta = &ixgbe_set_vfta_generic; 95 f->ixgbe_func_setup_fc = &ixgbe_setup_fc_generic; 96 97 return IXGBE_SUCCESS; 98 } 99 100 /** 101 * ixgbe_start_hw_generic - Prepare hardware for TX/RX 102 * @hw: pointer to hardware structure 103 * 104 * Starts the hardware by filling the bus info structure and media type, clears 105 * all on chip counters, initializes receive address registers, multicast 106 * table, VLAN filter table, calls routine to set up link and flow control 107 * settings, and leaves transmit and receive units disabled and uninitialized 108 **/ 109 s32 ixgbe_start_hw_generic(struct ixgbe_hw *hw) 110 { 111 u32 ctrl_ext; 112 113 /* Set the media type */ 114 hw->phy.media_type = ixgbe_get_media_type(hw); 115 116 /* Set bus info */ 117 ixgbe_get_bus_info(hw); 118 119 /* Identify the PHY */ 120 ixgbe_identify_phy(hw); 121 122 /* 123 * Store MAC address from RAR0, clear receive address registers, and 124 * clear the multicast table 125 */ 126 ixgbe_init_rx_addrs(hw); 127 128 /* Clear the VLAN filter table */ 129 ixgbe_clear_vfta(hw); 130 131 /* Set up link */ 132 ixgbe_setup_link(hw); 133 134 /* Clear statistics registers */ 135 ixgbe_clear_hw_cntrs(hw); 136 137 /* Set No Snoop Disable */ 138 ctrl_ext = IXGBE_READ_REG(hw, IXGBE_CTRL_EXT); 139 ctrl_ext |= IXGBE_CTRL_EXT_NS_DIS; 140 IXGBE_WRITE_REG(hw, IXGBE_CTRL_EXT, ctrl_ext); 141 142 /* Clear adapter stopped flag */ 143 hw->adapter_stopped = FALSE; 144 145 return IXGBE_SUCCESS; 146 } 147 148 /** 149 * ixgbe_init_hw_generic - Generic hardware initialization 150 * @hw: pointer to hardware structure 151 * 152 * Initialize the hardware by reseting the hardware, filling the bus info 153 * structure and media type, clears all on chip counters, initializes receive 154 * address registers, multicast table, VLAN filter table, calls routine to set 155 * up link and flow control settings, and leaves transmit and receive units 156 * disabled and uninitialized 157 **/ 158 s32 ixgbe_init_hw_generic(struct ixgbe_hw *hw) 159 { 160 /* Reset the hardware */ 161 ixgbe_reset_hw(hw); 162 163 /* Start the HW */ 164 ixgbe_start_hw(hw); 165 166 return IXGBE_SUCCESS; 167 } 168 169 /** 170 * ixgbe_clear_hw_cntrs_generic - Generic clear hardware counters 171 * @hw: pointer to hardware structure 172 * 173 * Clears all hardware statistics counters by reading them from the hardware 174 * Statistics counters are clear on read. 175 **/ 176 s32 ixgbe_clear_hw_cntrs_generic(struct ixgbe_hw *hw) 177 { 178 u16 i = 0; 179 180 IXGBE_READ_REG(hw, IXGBE_CRCERRS); 181 IXGBE_READ_REG(hw, IXGBE_ILLERRC); 182 IXGBE_READ_REG(hw, IXGBE_ERRBC); 183 IXGBE_READ_REG(hw, IXGBE_MSPDC); 184 for (i = 0; i < 8; i++) 185 IXGBE_READ_REG(hw, IXGBE_MPC(i)); 186 187 IXGBE_READ_REG(hw, IXGBE_MLFC); 188 IXGBE_READ_REG(hw, IXGBE_MRFC); 189 IXGBE_READ_REG(hw, IXGBE_RLEC); 190 IXGBE_READ_REG(hw, IXGBE_LXONTXC); 191 IXGBE_READ_REG(hw, IXGBE_LXONRXC); 192 IXGBE_READ_REG(hw, IXGBE_LXOFFTXC); 193 IXGBE_READ_REG(hw, IXGBE_LXOFFRXC); 194 195 for (i = 0; i < 8; i++) { 196 IXGBE_READ_REG(hw, IXGBE_PXONTXC(i)); 197 IXGBE_READ_REG(hw, IXGBE_PXONRXC(i)); 198 IXGBE_READ_REG(hw, IXGBE_PXOFFTXC(i)); 199 IXGBE_READ_REG(hw, IXGBE_PXOFFRXC(i)); 200 } 201 202 IXGBE_READ_REG(hw, IXGBE_PRC64); 203 IXGBE_READ_REG(hw, IXGBE_PRC127); 204 IXGBE_READ_REG(hw, IXGBE_PRC255); 205 IXGBE_READ_REG(hw, IXGBE_PRC511); 206 IXGBE_READ_REG(hw, IXGBE_PRC1023); 207 IXGBE_READ_REG(hw, IXGBE_PRC1522); 208 IXGBE_READ_REG(hw, IXGBE_GPRC); 209 IXGBE_READ_REG(hw, IXGBE_BPRC); 210 IXGBE_READ_REG(hw, IXGBE_MPRC); 211 IXGBE_READ_REG(hw, IXGBE_GPTC); 212 IXGBE_READ_REG(hw, IXGBE_GORCL); 213 IXGBE_READ_REG(hw, IXGBE_GORCH); 214 IXGBE_READ_REG(hw, IXGBE_GOTCL); 215 IXGBE_READ_REG(hw, IXGBE_GOTCH); 216 for (i = 0; i < 8; i++) 217 IXGBE_READ_REG(hw, IXGBE_RNBC(i)); 218 IXGBE_READ_REG(hw, IXGBE_RUC); 219 IXGBE_READ_REG(hw, IXGBE_RFC); 220 IXGBE_READ_REG(hw, IXGBE_ROC); 221 IXGBE_READ_REG(hw, IXGBE_RJC); 222 IXGBE_READ_REG(hw, IXGBE_MNGPRC); 223 IXGBE_READ_REG(hw, IXGBE_MNGPDC); 224 IXGBE_READ_REG(hw, IXGBE_MNGPTC); 225 IXGBE_READ_REG(hw, IXGBE_TORL); 226 IXGBE_READ_REG(hw, IXGBE_TORH); 227 IXGBE_READ_REG(hw, IXGBE_TPR); 228 IXGBE_READ_REG(hw, IXGBE_TPT); 229 IXGBE_READ_REG(hw, IXGBE_PTC64); 230 IXGBE_READ_REG(hw, IXGBE_PTC127); 231 IXGBE_READ_REG(hw, IXGBE_PTC255); 232 IXGBE_READ_REG(hw, IXGBE_PTC511); 233 IXGBE_READ_REG(hw, IXGBE_PTC1023); 234 IXGBE_READ_REG(hw, IXGBE_PTC1522); 235 IXGBE_READ_REG(hw, IXGBE_MPTC); 236 IXGBE_READ_REG(hw, IXGBE_BPTC); 237 for (i = 0; i < 16; i++) { 238 IXGBE_READ_REG(hw, IXGBE_QPRC(i)); 239 IXGBE_READ_REG(hw, IXGBE_QBRC(i)); 240 IXGBE_READ_REG(hw, IXGBE_QPTC(i)); 241 IXGBE_READ_REG(hw, IXGBE_QBTC(i)); 242 } 243 244 return IXGBE_SUCCESS; 245 } 246 247 /** 248 * ixgbe_get_mac_addr_generic - Generic get MAC address 249 * @hw: pointer to hardware structure 250 * @mac_addr: Adapter MAC address 251 * 252 * Reads the adapter's MAC address from first Receive Address Register (RAR0) 253 * A reset of the adapter must be performed prior to calling this function 254 * in order for the MAC address to have been loaded from the EEPROM into RAR0 255 **/ 256 s32 ixgbe_get_mac_addr_generic(struct ixgbe_hw *hw, u8 *mac_addr) 257 { 258 u32 rar_high; 259 u32 rar_low; 260 u16 i; 261 262 rar_high = IXGBE_READ_REG(hw, IXGBE_RAH(0)); 263 rar_low = IXGBE_READ_REG(hw, IXGBE_RAL(0)); 264 265 for (i = 0; i < 4; i++) 266 mac_addr[i] = (u8)(rar_low >> (i*8)); 267 268 for (i = 0; i < 2; i++) 269 mac_addr[i+4] = (u8)(rar_high >> (i*8)); 270 271 return IXGBE_SUCCESS; 272 } 273 274 /** 275 * ixgbe_get_bus_info_generic - Generic set PCI bus info 276 * @hw: pointer to hardware structure 277 * 278 * Sets the PCI bus info (speed, width, type) within the ixgbe_hw structure 279 **/ 280 s32 ixgbe_get_bus_info_generic(struct ixgbe_hw *hw) 281 { 282 u16 link_status; 283 284 hw->bus.type = ixgbe_bus_type_pci_express; 285 286 /* Get the negotiated link width and speed from PCI config space */ 287 link_status = IXGBE_READ_PCIE_WORD(hw, IXGBE_PCI_LINK_STATUS); 288 289 switch (link_status & IXGBE_PCI_LINK_WIDTH) { 290 case IXGBE_PCI_LINK_WIDTH_1: 291 hw->bus.width = ixgbe_bus_width_pcie_x1; 292 break; 293 case IXGBE_PCI_LINK_WIDTH_2: 294 hw->bus.width = ixgbe_bus_width_pcie_x2; 295 break; 296 case IXGBE_PCI_LINK_WIDTH_4: 297 hw->bus.width = ixgbe_bus_width_pcie_x4; 298 break; 299 case IXGBE_PCI_LINK_WIDTH_8: 300 hw->bus.width = ixgbe_bus_width_pcie_x8; 301 break; 302 default: 303 hw->bus.width = ixgbe_bus_width_unknown; 304 break; 305 } 306 307 switch (link_status & IXGBE_PCI_LINK_SPEED) { 308 case IXGBE_PCI_LINK_SPEED_2500: 309 hw->bus.speed = ixgbe_bus_speed_2500; 310 break; 311 case IXGBE_PCI_LINK_SPEED_5000: 312 hw->bus.speed = ixgbe_bus_speed_5000; 313 break; 314 default: 315 hw->bus.speed = ixgbe_bus_speed_unknown; 316 break; 317 } 318 319 return IXGBE_SUCCESS; 320 } 321 322 /** 323 * ixgbe_stop_adapter_generic - Generic stop TX/RX units 324 * @hw: pointer to hardware structure 325 * 326 * Sets the adapter_stopped flag within ixgbe_hw struct. Clears interrupts, 327 * disables transmit and receive units. The adapter_stopped flag is used by 328 * the shared code and drivers to determine if the adapter is in a stopped 329 * state and should not touch the hardware. 330 **/ 331 s32 ixgbe_stop_adapter_generic(struct ixgbe_hw *hw) 332 { 333 u32 number_of_queues; 334 u32 reg_val; 335 u16 i; 336 337 /* 338 * Set the adapter_stopped flag so other driver functions stop touching 339 * the hardware 340 */ 341 hw->adapter_stopped = TRUE; 342 343 /* Disable the receive unit */ 344 reg_val = IXGBE_READ_REG(hw, IXGBE_RXCTRL); 345 reg_val &= ~(IXGBE_RXCTRL_RXEN); 346 IXGBE_WRITE_REG(hw, IXGBE_RXCTRL, reg_val); 347 msec_delay(2); 348 349 /* Clear interrupt mask to stop from interrupts being generated */ 350 IXGBE_WRITE_REG(hw, IXGBE_EIMC, IXGBE_IRQ_CLEAR_MASK); 351 352 /* Clear any pending interrupts */ 353 IXGBE_READ_REG(hw, IXGBE_EICR); 354 355 /* Disable the transmit unit. Each queue must be disabled. */ 356 number_of_queues = ixgbe_get_num_of_tx_queues(hw); 357 for (i = 0; i < number_of_queues; i++) { 358 reg_val = IXGBE_READ_REG(hw, IXGBE_TXDCTL(i)); 359 if (reg_val & IXGBE_TXDCTL_ENABLE) { 360 reg_val &= ~IXGBE_TXDCTL_ENABLE; 361 IXGBE_WRITE_REG(hw, IXGBE_TXDCTL(i), reg_val); 362 } 363 } 364 365 return IXGBE_SUCCESS; 366 } 367 368 /** 369 * ixgbe_led_on_generic - Turns on the software controllable LEDs. 370 * @hw: pointer to hardware structure 371 * @index: led number to turn on 372 **/ 373 s32 ixgbe_led_on_generic(struct ixgbe_hw *hw, u32 index) 374 { 375 u32 led_reg = IXGBE_READ_REG(hw, IXGBE_LEDCTL); 376 377 /* To turn on the LED, set mode to ON. */ 378 led_reg &= ~IXGBE_LED_MODE_MASK(index); 379 led_reg |= IXGBE_LED_ON << IXGBE_LED_MODE_SHIFT(index); 380 IXGBE_WRITE_REG(hw, IXGBE_LEDCTL, led_reg); 381 382 return IXGBE_SUCCESS; 383 } 384 385 /** 386 * ixgbe_led_off_generic - Turns off the software controllable LEDs. 387 * @hw: pointer to hardware structure 388 * @index: led number to turn off 389 **/ 390 s32 ixgbe_led_off_generic(struct ixgbe_hw *hw, u32 index) 391 { 392 u32 led_reg = IXGBE_READ_REG(hw, IXGBE_LEDCTL); 393 394 /* To turn off the LED, set mode to OFF. */ 395 led_reg &= ~IXGBE_LED_MODE_MASK(index); 396 led_reg |= IXGBE_LED_OFF << IXGBE_LED_MODE_SHIFT(index); 397 IXGBE_WRITE_REG(hw, IXGBE_LEDCTL, led_reg); 398 399 return IXGBE_SUCCESS; 400 } 401 402 403 /** 404 * ixgbe_blink_led_start_generic - Blink LED based on index. 405 * @hw: pointer to hardware structure 406 * @index: led number to blink 407 **/ 408 s32 ixgbe_blink_led_start_generic(struct ixgbe_hw *hw, u32 index) 409 { 410 u32 led_reg = IXGBE_READ_REG(hw, IXGBE_LEDCTL); 411 412 led_reg |= IXGBE_LED_BLINK(index); 413 IXGBE_WRITE_REG(hw, IXGBE_LEDCTL, led_reg); 414 415 return IXGBE_SUCCESS; 416 } 417 418 /** 419 * ixgbe_blink_led_stop_generic - Stop blinking LED based on index. 420 * @hw: pointer to hardware structure 421 * @index: led number to stop blinking 422 **/ 423 s32 ixgbe_blink_led_stop_generic(struct ixgbe_hw *hw, u32 index) 424 { 425 u32 led_reg = IXGBE_READ_REG(hw, IXGBE_LEDCTL); 426 427 led_reg &= ~IXGBE_LED_BLINK(index); 428 IXGBE_WRITE_REG(hw, IXGBE_LEDCTL, led_reg); 429 430 return IXGBE_SUCCESS; 431 } 432 433 /** 434 * ixgbe_init_eeprom_params_generic - Initialize EEPROM params 435 * @hw: pointer to hardware structure 436 * 437 * Initializes the EEPROM parameters ixgbe_eeprom_info within the 438 * ixgbe_hw struct in order to set up EEPROM access. 439 **/ 440 s32 ixgbe_init_eeprom_params_generic(struct ixgbe_hw *hw) 441 { 442 struct ixgbe_eeprom_info *eeprom = &hw->eeprom; 443 u32 eec; 444 u16 eeprom_size; 445 446 if (eeprom->type == ixgbe_eeprom_uninitialized) { 447 eeprom->type = ixgbe_eeprom_none; 448 449 /* 450 * Check for EEPROM present first. 451 * If not present leave as none 452 */ 453 eec = IXGBE_READ_REG(hw, IXGBE_EEC); 454 if (eec & IXGBE_EEC_PRES) { 455 eeprom->type = ixgbe_eeprom_spi; 456 457 /* 458 * SPI EEPROM is assumed here. This code would need to 459 * change if a future EEPROM is not SPI. 460 */ 461 eeprom_size = (u16)((eec & IXGBE_EEC_SIZE) >> 462 IXGBE_EEC_SIZE_SHIFT); 463 eeprom->word_size = 1 << (eeprom_size + 464 IXGBE_EEPROM_WORD_SIZE_SHIFT); 465 } 466 467 if (eec & IXGBE_EEC_ADDR_SIZE) 468 eeprom->address_bits = 16; 469 else 470 eeprom->address_bits = 8; 471 DEBUGOUT3("Eeprom params: type = %d, size = %d, address bits: " 472 "%d\n", eeprom->type, eeprom->word_size, 473 eeprom->address_bits); 474 } 475 476 return IXGBE_SUCCESS; 477 } 478 479 /** 480 * ixgbe_write_eeprom_generic - Writes 16 bit value to EEPROM 481 * @hw: pointer to hardware structure 482 * @offset: offset within the EEPROM to be written to 483 * @data: 16 bit word to be written to the EEPROM 484 * 485 * If ixgbe_eeprom_update_checksum is not called after this function, the 486 * EEPROM will most likely contain an invalid checksum. 487 **/ 488 s32 ixgbe_write_eeprom_generic(struct ixgbe_hw *hw, u16 offset, u16 data) 489 { 490 s32 status; 491 u8 write_opcode = IXGBE_EEPROM_WRITE_OPCODE_SPI; 492 493 /* Prepare the EEPROM for writing */ 494 status = ixgbe_acquire_eeprom(hw); 495 496 if (status == IXGBE_SUCCESS) { 497 if (ixgbe_ready_eeprom(hw) != IXGBE_SUCCESS) { 498 ixgbe_release_eeprom(hw); 499 status = IXGBE_ERR_EEPROM; 500 } 501 } 502 503 if (status == IXGBE_SUCCESS) { 504 ixgbe_standby_eeprom(hw); 505 506 /* Send the WRITE ENABLE command (8 bit opcode ) */ 507 ixgbe_shift_out_eeprom_bits(hw, IXGBE_EEPROM_WREN_OPCODE_SPI, 508 IXGBE_EEPROM_OPCODE_BITS); 509 510 ixgbe_standby_eeprom(hw); 511 512 /* 513 * Some SPI eeproms use the 8th address bit embedded in the 514 * opcode 515 */ 516 if ((hw->eeprom.address_bits == 8) && (offset >= 128)) 517 write_opcode |= IXGBE_EEPROM_A8_OPCODE_SPI; 518 519 /* Send the Write command (8-bit opcode + addr) */ 520 ixgbe_shift_out_eeprom_bits(hw, write_opcode, 521 IXGBE_EEPROM_OPCODE_BITS); 522 ixgbe_shift_out_eeprom_bits(hw, (u16)(offset*2), 523 hw->eeprom.address_bits); 524 525 /* Send the data */ 526 data = (data >> 8) | (data << 8); 527 ixgbe_shift_out_eeprom_bits(hw, data, 16); 528 ixgbe_standby_eeprom(hw); 529 530 msec_delay(10); 531 532 /* Done with writing - release the EEPROM */ 533 ixgbe_release_eeprom(hw); 534 } 535 536 return status; 537 } 538 539 /** 540 * ixgbe_read_eeprom_bit_bang_generic - Read EEPROM word using bit-bang 541 * @hw: pointer to hardware structure 542 * @offset: offset within the EEPROM to be read 543 * @data: read 16 bit value from EEPROM 544 * 545 * Reads 16 bit value from EEPROM through bit-bang method 546 **/ 547 s32 ixgbe_read_eeprom_bit_bang_generic(struct ixgbe_hw *hw, u16 offset, 548 u16 *data) 549 { 550 s32 status; 551 u16 word_in; 552 u8 read_opcode = IXGBE_EEPROM_READ_OPCODE_SPI; 553 554 /* Prepare the EEPROM for reading */ 555 status = ixgbe_acquire_eeprom(hw); 556 557 if (status == IXGBE_SUCCESS) { 558 if (ixgbe_ready_eeprom(hw) != IXGBE_SUCCESS) { 559 ixgbe_release_eeprom(hw); 560 status = IXGBE_ERR_EEPROM; 561 } 562 } 563 564 if (status == IXGBE_SUCCESS) { 565 ixgbe_standby_eeprom(hw); 566 567 /* 568 * Some SPI eeproms use the 8th address bit embedded in the 569 * opcode 570 */ 571 if ((hw->eeprom.address_bits == 8) && (offset >= 128)) 572 read_opcode |= IXGBE_EEPROM_A8_OPCODE_SPI; 573 574 /* Send the READ command (opcode + addr) */ 575 ixgbe_shift_out_eeprom_bits(hw, read_opcode, 576 IXGBE_EEPROM_OPCODE_BITS); 577 ixgbe_shift_out_eeprom_bits(hw, (u16)(offset*2), 578 hw->eeprom.address_bits); 579 580 /* Read the data. */ 581 word_in = ixgbe_shift_in_eeprom_bits(hw, 16); 582 *data = (word_in >> 8) | (word_in << 8); 583 584 /* End this read operation */ 585 ixgbe_release_eeprom(hw); 586 } 587 588 return status; 589 } 590 591 /** 592 * ixgbe_read_eeprom_generic - Read EEPROM word using EERD 593 * @hw: pointer to hardware structure 594 * @offset: offset of word in the EEPROM to read 595 * @data: word read from the EEPROM 596 * 597 * Reads a 16 bit word from the EEPROM using the EERD register. 598 **/ 599 s32 ixgbe_read_eeprom_generic(struct ixgbe_hw *hw, u16 offset, u16 *data) 600 { 601 u32 eerd; 602 s32 status; 603 604 eerd = (offset << IXGBE_EEPROM_READ_ADDR_SHIFT) + 605 IXGBE_EEPROM_READ_REG_START; 606 607 IXGBE_WRITE_REG(hw, IXGBE_EERD, eerd); 608 status = ixgbe_poll_eeprom_eerd_done(hw); 609 610 if (status == IXGBE_SUCCESS) 611 *data = (IXGBE_READ_REG(hw, IXGBE_EERD) >> 612 IXGBE_EEPROM_READ_REG_DATA); 613 else 614 DEBUGOUT("Eeprom read timed out\n"); 615 616 return status; 617 } 618 619 /** 620 * ixgbe_poll_eeprom_eerd_done - Poll EERD status 621 * @hw: pointer to hardware structure 622 * 623 * Polls the status bit (bit 1) of the EERD to determine when the read is done. 624 **/ 625 static s32 ixgbe_poll_eeprom_eerd_done(struct ixgbe_hw *hw) 626 { 627 u32 i; 628 u32 reg; 629 s32 status = IXGBE_ERR_EEPROM; 630 631 for (i = 0; i < IXGBE_EERD_ATTEMPTS; i++) { 632 reg = IXGBE_READ_REG(hw, IXGBE_EERD); 633 if (reg & IXGBE_EEPROM_READ_REG_DONE) { 634 status = IXGBE_SUCCESS; 635 break; 636 } 637 usec_delay(5); 638 } 639 return status; 640 } 641 642 /** 643 * ixgbe_acquire_eeprom - Acquire EEPROM using bit-bang 644 * @hw: pointer to hardware structure 645 * 646 * Prepares EEPROM for access using bit-bang method. This function should 647 * be called before issuing a command to the EEPROM. 648 **/ 649 static s32 ixgbe_acquire_eeprom(struct ixgbe_hw *hw) 650 { 651 s32 status = IXGBE_SUCCESS; 652 u32 eec; 653 u32 i; 654 655 if (ixgbe_acquire_swfw_sync(hw, IXGBE_GSSR_EEP_SM) != IXGBE_SUCCESS) 656 status = IXGBE_ERR_SWFW_SYNC; 657 658 if (status == IXGBE_SUCCESS) { 659 eec = IXGBE_READ_REG(hw, IXGBE_EEC); 660 661 /* Request EEPROM Access */ 662 eec |= IXGBE_EEC_REQ; 663 IXGBE_WRITE_REG(hw, IXGBE_EEC, eec); 664 665 for (i = 0; i < IXGBE_EEPROM_GRANT_ATTEMPTS; i++) { 666 eec = IXGBE_READ_REG(hw, IXGBE_EEC); 667 if (eec & IXGBE_EEC_GNT) 668 break; 669 usec_delay(5); 670 } 671 672 /* Release if grant not aquired */ 673 if (!(eec & IXGBE_EEC_GNT)) { 674 eec &= ~IXGBE_EEC_REQ; 675 IXGBE_WRITE_REG(hw, IXGBE_EEC, eec); 676 DEBUGOUT("Could not acquire EEPROM grant\n"); 677 678 ixgbe_release_swfw_sync(hw, IXGBE_GSSR_EEP_SM); 679 status = IXGBE_ERR_EEPROM; 680 } 681 } 682 683 /* Setup EEPROM for Read/Write */ 684 if (status == IXGBE_SUCCESS) { 685 /* Clear CS and SK */ 686 eec &= ~(IXGBE_EEC_CS | IXGBE_EEC_SK); 687 IXGBE_WRITE_REG(hw, IXGBE_EEC, eec); 688 IXGBE_WRITE_FLUSH(hw); 689 usec_delay(1); 690 } 691 return status; 692 } 693 694 /** 695 * ixgbe_get_eeprom_semaphore - Get hardware semaphore 696 * @hw: pointer to hardware structure 697 * 698 * Sets the hardware semaphores so EEPROM access can occur for bit-bang method 699 **/ 700 static s32 ixgbe_get_eeprom_semaphore(struct ixgbe_hw *hw) 701 { 702 s32 status = IXGBE_ERR_EEPROM; 703 u32 timeout; 704 u32 i; 705 u32 swsm; 706 707 /* Set timeout value based on size of EEPROM */ 708 timeout = hw->eeprom.word_size + 1; 709 710 /* Get SMBI software semaphore between device drivers first */ 711 for (i = 0; i < timeout; i++) { 712 /* 713 * If the SMBI bit is 0 when we read it, then the bit will be 714 * set and we have the semaphore 715 */ 716 swsm = IXGBE_READ_REG(hw, IXGBE_SWSM); 717 if (!(swsm & IXGBE_SWSM_SMBI)) { 718 status = IXGBE_SUCCESS; 719 break; 720 } 721 msec_delay(1); 722 } 723 724 /* Now get the semaphore between SW/FW through the SWESMBI bit */ 725 if (status == IXGBE_SUCCESS) { 726 for (i = 0; i < timeout; i++) { 727 swsm = IXGBE_READ_REG(hw, IXGBE_SWSM); 728 729 /* Set the SW EEPROM semaphore bit to request access */ 730 swsm |= IXGBE_SWSM_SWESMBI; 731 IXGBE_WRITE_REG(hw, IXGBE_SWSM, swsm); 732 733 /* 734 * If we set the bit successfully then we got the 735 * semaphore. 736 */ 737 swsm = IXGBE_READ_REG(hw, IXGBE_SWSM); 738 if (swsm & IXGBE_SWSM_SWESMBI) 739 break; 740 741 usec_delay(50); 742 } 743 744 /* 745 * Release semaphores and return error if SW EEPROM semaphore 746 * was not granted because we don't have access to the EEPROM 747 */ 748 if (i >= timeout) { 749 DEBUGOUT("Driver can't access the Eeprom - Semaphore " 750 "not granted.\n"); 751 ixgbe_release_eeprom_semaphore(hw); 752 status = IXGBE_ERR_EEPROM; 753 } 754 } 755 756 return status; 757 } 758 759 /** 760 * ixgbe_release_eeprom_semaphore - Release hardware semaphore 761 * @hw: pointer to hardware structure 762 * 763 * This function clears hardware semaphore bits. 764 **/ 765 static void ixgbe_release_eeprom_semaphore(struct ixgbe_hw *hw) 766 { 767 u32 swsm; 768 769 swsm = IXGBE_READ_REG(hw, IXGBE_SWSM); 770 771 /* Release both semaphores by writing 0 to the bits SWESMBI and SMBI */ 772 swsm &= ~(IXGBE_SWSM_SWESMBI | IXGBE_SWSM_SMBI); 773 IXGBE_WRITE_REG(hw, IXGBE_SWSM, swsm); 774 } 775 776 /** 777 * ixgbe_ready_eeprom - Polls for EEPROM ready 778 * @hw: pointer to hardware structure 779 **/ 780 static s32 ixgbe_ready_eeprom(struct ixgbe_hw *hw) 781 { 782 s32 status = IXGBE_SUCCESS; 783 u16 i; 784 u8 spi_stat_reg; 785 786 /* 787 * Read "Status Register" repeatedly until the LSB is cleared. The 788 * EEPROM will signal that the command has been completed by clearing 789 * bit 0 of the internal status register. If it's not cleared within 790 * 5 milliseconds, then error out. 791 */ 792 for (i = 0; i < IXGBE_EEPROM_MAX_RETRY_SPI; i += 5) { 793 ixgbe_shift_out_eeprom_bits(hw, IXGBE_EEPROM_RDSR_OPCODE_SPI, 794 IXGBE_EEPROM_OPCODE_BITS); 795 spi_stat_reg = (u8)ixgbe_shift_in_eeprom_bits(hw, 8); 796 if (!(spi_stat_reg & IXGBE_EEPROM_STATUS_RDY_SPI)) 797 break; 798 799 usec_delay(5); 800 ixgbe_standby_eeprom(hw); 801 }; 802 803 /* 804 * On some parts, SPI write time could vary from 0-20mSec on 3.3V 805 * devices (and only 0-5mSec on 5V devices) 806 */ 807 if (i >= IXGBE_EEPROM_MAX_RETRY_SPI) { 808 DEBUGOUT("SPI EEPROM Status error\n"); 809 status = IXGBE_ERR_EEPROM; 810 } 811 812 return status; 813 } 814 815 /** 816 * ixgbe_standby_eeprom - Returns EEPROM to a "standby" state 817 * @hw: pointer to hardware structure 818 **/ 819 static void ixgbe_standby_eeprom(struct ixgbe_hw *hw) 820 { 821 u32 eec; 822 823 eec = IXGBE_READ_REG(hw, IXGBE_EEC); 824 825 /* Toggle CS to flush commands */ 826 eec |= IXGBE_EEC_CS; 827 IXGBE_WRITE_REG(hw, IXGBE_EEC, eec); 828 IXGBE_WRITE_FLUSH(hw); 829 usec_delay(1); 830 eec &= ~IXGBE_EEC_CS; 831 IXGBE_WRITE_REG(hw, IXGBE_EEC, eec); 832 IXGBE_WRITE_FLUSH(hw); 833 usec_delay(1); 834 } 835 836 /** 837 * ixgbe_shift_out_eeprom_bits - Shift data bits out to the EEPROM. 838 * @hw: pointer to hardware structure 839 * @data: data to send to the EEPROM 840 * @count: number of bits to shift out 841 **/ 842 static void ixgbe_shift_out_eeprom_bits(struct ixgbe_hw *hw, u16 data, 843 u16 count) 844 { 845 u32 eec; 846 u32 mask; 847 u32 i; 848 849 eec = IXGBE_READ_REG(hw, IXGBE_EEC); 850 851 /* 852 * Mask is used to shift "count" bits of "data" out to the EEPROM 853 * one bit at a time. Determine the starting bit based on count 854 */ 855 mask = 0x01 << (count - 1); 856 857 for (i = 0; i < count; i++) { 858 /* 859 * A "1" is shifted out to the EEPROM by setting bit "DI" to a 860 * "1", and then raising and then lowering the clock (the SK 861 * bit controls the clock input to the EEPROM). A "0" is 862 * shifted out to the EEPROM by setting "DI" to "0" and then 863 * raising and then lowering the clock. 864 */ 865 if (data & mask) 866 eec |= IXGBE_EEC_DI; 867 else 868 eec &= ~IXGBE_EEC_DI; 869 870 IXGBE_WRITE_REG(hw, IXGBE_EEC, eec); 871 IXGBE_WRITE_FLUSH(hw); 872 873 usec_delay(1); 874 875 ixgbe_raise_eeprom_clk(hw, &eec); 876 ixgbe_lower_eeprom_clk(hw, &eec); 877 878 /* 879 * Shift mask to signify next bit of data to shift in to the 880 * EEPROM 881 */ 882 mask = mask >> 1; 883 }; 884 885 /* We leave the "DI" bit set to "0" when we leave this routine. */ 886 eec &= ~IXGBE_EEC_DI; 887 IXGBE_WRITE_REG(hw, IXGBE_EEC, eec); 888 IXGBE_WRITE_FLUSH(hw); 889 } 890 891 /** 892 * ixgbe_shift_in_eeprom_bits - Shift data bits in from the EEPROM 893 * @hw: pointer to hardware structure 894 **/ 895 static u16 ixgbe_shift_in_eeprom_bits(struct ixgbe_hw *hw, u16 count) 896 { 897 u32 eec; 898 u32 i; 899 u16 data = 0; 900 901 /* 902 * In order to read a register from the EEPROM, we need to shift 903 * 'count' bits in from the EEPROM. Bits are "shifted in" by raising 904 * the clock input to the EEPROM (setting the SK bit), and then reading 905 * the value of the "DO" bit. During this "shifting in" process the 906 * "DI" bit should always be clear. 907 */ 908 eec = IXGBE_READ_REG(hw, IXGBE_EEC); 909 910 eec &= ~(IXGBE_EEC_DO | IXGBE_EEC_DI); 911 912 for (i = 0; i < count; i++) { 913 data = data << 1; 914 ixgbe_raise_eeprom_clk(hw, &eec); 915 916 eec = IXGBE_READ_REG(hw, IXGBE_EEC); 917 918 eec &= ~(IXGBE_EEC_DI); 919 if (eec & IXGBE_EEC_DO) 920 data |= 1; 921 922 ixgbe_lower_eeprom_clk(hw, &eec); 923 } 924 925 return data; 926 } 927 928 /** 929 * ixgbe_raise_eeprom_clk - Raises the EEPROM's clock input. 930 * @hw: pointer to hardware structure 931 * @eec: EEC register's current value 932 **/ 933 static void ixgbe_raise_eeprom_clk(struct ixgbe_hw *hw, u32 *eec) 934 { 935 /* 936 * Raise the clock input to the EEPROM 937 * (setting the SK bit), then delay 938 */ 939 *eec = *eec | IXGBE_EEC_SK; 940 IXGBE_WRITE_REG(hw, IXGBE_EEC, *eec); 941 IXGBE_WRITE_FLUSH(hw); 942 usec_delay(1); 943 } 944 945 /** 946 * ixgbe_lower_eeprom_clk - Lowers the EEPROM's clock input. 947 * @hw: pointer to hardware structure 948 * @eecd: EECD's current value 949 **/ 950 static void ixgbe_lower_eeprom_clk(struct ixgbe_hw *hw, u32 *eec) 951 { 952 /* 953 * Lower the clock input to the EEPROM (clearing the SK bit), then 954 * delay 955 */ 956 *eec = *eec & ~IXGBE_EEC_SK; 957 IXGBE_WRITE_REG(hw, IXGBE_EEC, *eec); 958 IXGBE_WRITE_FLUSH(hw); 959 usec_delay(1); 960 } 961 962 /** 963 * ixgbe_release_eeprom - Release EEPROM, release semaphores 964 * @hw: pointer to hardware structure 965 **/ 966 static void ixgbe_release_eeprom(struct ixgbe_hw *hw) 967 { 968 u32 eec; 969 970 eec = IXGBE_READ_REG(hw, IXGBE_EEC); 971 972 eec |= IXGBE_EEC_CS; /* Pull CS high */ 973 eec &= ~IXGBE_EEC_SK; /* Lower SCK */ 974 975 IXGBE_WRITE_REG(hw, IXGBE_EEC, eec); 976 IXGBE_WRITE_FLUSH(hw); 977 978 usec_delay(1); 979 980 /* Stop requesting EEPROM access */ 981 eec &= ~IXGBE_EEC_REQ; 982 IXGBE_WRITE_REG(hw, IXGBE_EEC, eec); 983 984 ixgbe_release_swfw_sync(hw, IXGBE_GSSR_EEP_SM); 985 } 986 987 /** 988 * ixgbe_calc_eeprom_checksum - Calculates and returns the checksum 989 * @hw: pointer to hardware structure 990 **/ 991 static u16 ixgbe_calc_eeprom_checksum(struct ixgbe_hw *hw) 992 { 993 u16 i; 994 u16 j; 995 u16 checksum = 0; 996 u16 length = 0; 997 u16 pointer = 0; 998 u16 word = 0; 999 1000 /* Include 0x0-0x3F in the checksum */ 1001 for (i = 0; i < IXGBE_EEPROM_CHECKSUM; i++) { 1002 if (ixgbe_read_eeprom(hw, i, &word) != IXGBE_SUCCESS) { 1003 DEBUGOUT("EEPROM read failed\n"); 1004 break; 1005 } 1006 checksum += word; 1007 } 1008 1009 /* Include all data from pointers except for the fw pointer */ 1010 for (i = IXGBE_PCIE_ANALOG_PTR; i < IXGBE_FW_PTR; i++) { 1011 ixgbe_read_eeprom(hw, i, &pointer); 1012 1013 /* Make sure the pointer seems valid */ 1014 if (pointer != 0xFFFF && pointer != 0) { 1015 ixgbe_read_eeprom(hw, pointer, &length); 1016 1017 if (length != 0xFFFF && length != 0) { 1018 for (j = pointer+1; j <= pointer+length; j++) { 1019 ixgbe_read_eeprom(hw, j, &word); 1020 checksum += word; 1021 } 1022 } 1023 } 1024 } 1025 1026 checksum = (u16)IXGBE_EEPROM_SUM - checksum; 1027 1028 return checksum; 1029 } 1030 1031 /** 1032 * ixgbe_validate_eeprom_checksum_generic - Validate EEPROM checksum 1033 * @hw: pointer to hardware structure 1034 * @checksum_val: calculated checksum 1035 * 1036 * Performs checksum calculation and validates the EEPROM checksum. If the 1037 * caller does not need checksum_val, the value can be NULL. 1038 **/ 1039 s32 ixgbe_validate_eeprom_checksum_generic(struct ixgbe_hw *hw, 1040 u16 *checksum_val) 1041 { 1042 s32 status; 1043 u16 checksum; 1044 u16 read_checksum = 0; 1045 1046 /* 1047 * Read the first word from the EEPROM. If this times out or fails, do 1048 * not continue or we could be in for a very long wait while every 1049 * EEPROM read fails 1050 */ 1051 status = ixgbe_read_eeprom(hw, 0, &checksum); 1052 1053 if (status == IXGBE_SUCCESS) { 1054 checksum = ixgbe_calc_eeprom_checksum(hw); 1055 1056 ixgbe_read_eeprom(hw, IXGBE_EEPROM_CHECKSUM, &read_checksum); 1057 1058 /* 1059 * Verify read checksum from EEPROM is the same as 1060 * calculated checksum 1061 */ 1062 if (read_checksum != checksum) { 1063 status = IXGBE_ERR_EEPROM_CHECKSUM; 1064 } 1065 1066 /* If the user cares, return the calculated checksum */ 1067 if (checksum_val) { 1068 *checksum_val = checksum; 1069 } 1070 } else { 1071 DEBUGOUT("EEPROM read failed\n"); 1072 } 1073 1074 return status; 1075 } 1076 1077 /** 1078 * ixgbe_update_eeprom_checksum_generic - Updates the EEPROM checksm 1079 * @hw: pointer to hardware structure 1080 **/ 1081 s32 ixgbe_update_eeprom_checksum_generic(struct ixgbe_hw *hw) 1082 { 1083 s32 status; 1084 u16 checksum; 1085 1086 /* 1087 * Read the first word from the EEPROM. If this times out or fails, do 1088 * not continue or we could be in for a very long wait while every 1089 * EEPROM read fails 1090 */ 1091 status = ixgbe_read_eeprom(hw, 0, &checksum); 1092 1093 if (status == IXGBE_SUCCESS) { 1094 checksum = ixgbe_calc_eeprom_checksum(hw); 1095 status = ixgbe_write_eeprom(hw, IXGBE_EEPROM_CHECKSUM, 1096 checksum); 1097 } else { 1098 DEBUGOUT("EEPROM read failed\n"); 1099 } 1100 1101 return status; 1102 } 1103 1104 /** 1105 * ixgbe_validate_mac_addr - Validate MAC address 1106 * @mac_addr: pointer to MAC address. 1107 * 1108 * Tests a MAC address to ensure it is a valid Individual Address 1109 **/ 1110 s32 ixgbe_validate_mac_addr(u8 *mac_addr) 1111 { 1112 s32 status = IXGBE_SUCCESS; 1113 1114 /* Make sure it is not a multicast address */ 1115 if (IXGBE_IS_MULTICAST(mac_addr)) { 1116 DEBUGOUT("MAC address is multicast\n"); 1117 status = IXGBE_ERR_INVALID_MAC_ADDR; 1118 /* Not a broadcast address */ 1119 } else if (IXGBE_IS_BROADCAST(mac_addr)) { 1120 DEBUGOUT("MAC address is broadcast\n"); 1121 status = IXGBE_ERR_INVALID_MAC_ADDR; 1122 /* Reject the zero address */ 1123 } else if (mac_addr[0] == 0 && mac_addr[1] == 0 && mac_addr[2] == 0 && 1124 mac_addr[3] == 0 && mac_addr[4] == 0 && mac_addr[5] == 0) { 1125 DEBUGOUT("MAC address is all zeros\n"); 1126 status = IXGBE_ERR_INVALID_MAC_ADDR; 1127 } 1128 return status; 1129 } 1130 1131 /** 1132 * ixgbe_set_rar_generic - Set RX address register 1133 * @hw: pointer to hardware structure 1134 * @addr: Address to put into receive address register 1135 * @index: Receive address register to write 1136 * @vind: Vind to set RAR to 1137 * @enable_addr: set flag that address is active 1138 * 1139 * Puts an ethernet address into a receive address register. 1140 **/ 1141 s32 ixgbe_set_rar_generic(struct ixgbe_hw *hw, u32 index, u8 *addr, u32 vind, 1142 u32 enable_addr) 1143 { 1144 u32 rar_low, rar_high; 1145 1146 /* 1147 * HW expects these in little endian so we reverse the byte order from 1148 * network order (big endian) to little endian 1149 */ 1150 rar_low = ((u32)addr[0] | 1151 ((u32)addr[1] << 8) | 1152 ((u32)addr[2] << 16) | 1153 ((u32)addr[3] << 24)); 1154 1155 rar_high = ((u32)addr[4] | 1156 ((u32)addr[5] << 8) | 1157 ((vind << IXGBE_RAH_VIND_SHIFT) & IXGBE_RAH_VIND_MASK)); 1158 1159 if (enable_addr != 0) 1160 rar_high |= IXGBE_RAH_AV; 1161 1162 IXGBE_WRITE_REG(hw, IXGBE_RAL(index), rar_low); 1163 IXGBE_WRITE_REG(hw, IXGBE_RAH(index), rar_high); 1164 1165 return IXGBE_SUCCESS; 1166 } 1167 1168 /** 1169 * ixgbe_enable_rar - Enable RX address register 1170 * @hw: pointer to hardware structure 1171 * @index: index into the RAR table 1172 * 1173 * Enables the select receive address register. 1174 **/ 1175 static void ixgbe_enable_rar(struct ixgbe_hw *hw, u32 index) 1176 { 1177 u32 rar_high; 1178 1179 rar_high = IXGBE_READ_REG(hw, IXGBE_RAH(index)); 1180 rar_high |= IXGBE_RAH_AV; 1181 IXGBE_WRITE_REG(hw, IXGBE_RAH(index), rar_high); 1182 } 1183 1184 /** 1185 * ixgbe_disable_rar - Disable RX address register 1186 * @hw: pointer to hardware structure 1187 * @index: index into the RAR table 1188 * 1189 * Disables the select receive address register. 1190 **/ 1191 static void ixgbe_disable_rar(struct ixgbe_hw *hw, u32 index) 1192 { 1193 u32 rar_high; 1194 1195 rar_high = IXGBE_READ_REG(hw, IXGBE_RAH(index)); 1196 rar_high &= (~IXGBE_RAH_AV); 1197 IXGBE_WRITE_REG(hw, IXGBE_RAH(index), rar_high); 1198 } 1199 1200 /** 1201 * ixgbe_init_rx_addrs_generic - Initializes receive address filters. 1202 * @hw: pointer to hardware structure 1203 * 1204 * Places the MAC address in receive address register 0 and clears the rest 1205 * of the receive addresss registers. Clears the multicast table. Assumes 1206 * the receiver is in reset when the routine is called. 1207 **/ 1208 s32 ixgbe_init_rx_addrs_generic(struct ixgbe_hw *hw) 1209 { 1210 u32 i; 1211 u32 rar_entries = ixgbe_get_num_rx_addrs(hw); 1212 1213 /* 1214 * If the current mac address is valid, assume it is a software override 1215 * to the permanent address. 1216 * Otherwise, use the permanent address from the eeprom. 1217 */ 1218 if (ixgbe_validate_mac_addr(hw->mac.addr) == 1219 IXGBE_ERR_INVALID_MAC_ADDR) { 1220 /* Get the MAC address from the RAR0 for later reference */ 1221 ixgbe_get_mac_addr(hw, hw->mac.addr); 1222 1223 DEBUGOUT3(" Keeping Current RAR0 Addr =%.2X %.2X %.2X ", 1224 hw->mac.addr[0], hw->mac.addr[1], 1225 hw->mac.addr[2]); 1226 DEBUGOUT3("%.2X %.2X %.2X\n", hw->mac.addr[3], 1227 hw->mac.addr[4], hw->mac.addr[5]); 1228 } else { 1229 /* Setup the receive address. */ 1230 DEBUGOUT("Overriding MAC Address in RAR[0]\n"); 1231 DEBUGOUT3(" New MAC Addr =%.2X %.2X %.2X ", 1232 hw->mac.addr[0], hw->mac.addr[1], 1233 hw->mac.addr[2]); 1234 DEBUGOUT3("%.2X %.2X %.2X\n", hw->mac.addr[3], 1235 hw->mac.addr[4], hw->mac.addr[5]); 1236 1237 ixgbe_set_rar(hw, 0, hw->mac.addr, 0, IXGBE_RAH_AV); 1238 } 1239 1240 hw->addr_ctrl.rar_used_count = 1; 1241 1242 /* Zero out the other receive addresses. */ 1243 DEBUGOUT("Clearing RAR[1-15]\n"); 1244 for (i = 1; i < rar_entries; i++) { 1245 IXGBE_WRITE_REG(hw, IXGBE_RAL(i), 0); 1246 IXGBE_WRITE_REG(hw, IXGBE_RAH(i), 0); 1247 } 1248 1249 /* Clear the MTA */ 1250 hw->addr_ctrl.mc_addr_in_rar_count = 0; 1251 hw->addr_ctrl.mta_in_use = 0; 1252 IXGBE_WRITE_REG(hw, IXGBE_MCSTCTRL, hw->mac.mc_filter_type); 1253 1254 DEBUGOUT(" Clearing MTA\n"); 1255 for (i = 0; i < IXGBE_MC_TBL_SIZE; i++) 1256 IXGBE_WRITE_REG(hw, IXGBE_MTA(i), 0); 1257 1258 return IXGBE_SUCCESS; 1259 } 1260 1261 /** 1262 * ixgbe_mta_vector - Determines bit-vector in multicast table to set 1263 * @hw: pointer to hardware structure 1264 * @mc_addr: the multicast address 1265 * 1266 * Extracts the 12 bits, from a multicast address, to determine which 1267 * bit-vector to set in the multicast table. The hardware uses 12 bits, from 1268 * incoming rx multicast addresses, to determine the bit-vector to check in 1269 * the MTA. Which of the 4 combination, of 12-bits, the hardware uses is set 1270 * by the MO field of the MCSTCTRL. The MO field is set during initalization 1271 * to mc_filter_type. 1272 **/ 1273 static s32 ixgbe_mta_vector(struct ixgbe_hw *hw, u8 *mc_addr) 1274 { 1275 u32 vector = 0; 1276 1277 switch (hw->mac.mc_filter_type) { 1278 case 0: /* use bits [47:36] of the address */ 1279 vector = ((mc_addr[4] >> 4) | (((u16)mc_addr[5]) << 4)); 1280 break; 1281 case 1: /* use bits [46:35] of the address */ 1282 vector = ((mc_addr[4] >> 3) | (((u16)mc_addr[5]) << 5)); 1283 break; 1284 case 2: /* use bits [45:34] of the address */ 1285 vector = ((mc_addr[4] >> 2) | (((u16)mc_addr[5]) << 6)); 1286 break; 1287 case 3: /* use bits [43:32] of the address */ 1288 vector = ((mc_addr[4]) | (((u16)mc_addr[5]) << 8)); 1289 break; 1290 default: /* Invalid mc_filter_type */ 1291 DEBUGOUT("MC filter type param set incorrectly\n"); 1292 ASSERT(0); 1293 break; 1294 } 1295 1296 /* vector can only be 12-bits or boundary will be exceeded */ 1297 vector &= 0xFFF; 1298 return vector; 1299 } 1300 1301 /** 1302 * ixgbe_set_mta - Set bit-vector in multicast table 1303 * @hw: pointer to hardware structure 1304 * @hash_value: Multicast address hash value 1305 * 1306 * Sets the bit-vector in the multicast table. 1307 **/ 1308 void ixgbe_set_mta(struct ixgbe_hw *hw, u8 *mc_addr) 1309 { 1310 u32 vector; 1311 u32 vector_bit; 1312 u32 vector_reg; 1313 u32 mta_reg; 1314 1315 hw->addr_ctrl.mta_in_use++; 1316 1317 vector = ixgbe_mta_vector(hw, mc_addr); 1318 DEBUGOUT1(" bit-vector = 0x%03X\n", vector); 1319 1320 /* 1321 * The MTA is a register array of 128 32-bit registers. It is treated 1322 * like an array of 4096 bits. We want to set bit 1323 * BitArray[vector_value]. So we figure out what register the bit is 1324 * in, read it, OR in the new bit, then write back the new value. The 1325 * register is determined by the upper 7 bits of the vector value and 1326 * the bit within that register are determined by the lower 5 bits of 1327 * the value. 1328 */ 1329 vector_reg = (vector >> 5) & 0x7F; 1330 vector_bit = vector & 0x1F; 1331 mta_reg = IXGBE_READ_REG(hw, IXGBE_MTA(vector_reg)); 1332 mta_reg |= (1 << vector_bit); 1333 IXGBE_WRITE_REG(hw, IXGBE_MTA(vector_reg), mta_reg); 1334 } 1335 1336 /** 1337 * ixgbe_add_mc_addr - Adds a multicast address. 1338 * @hw: pointer to hardware structure 1339 * @mc_addr: new multicast address 1340 * 1341 * Adds it to unused receive address register or to the multicast table. 1342 **/ 1343 void ixgbe_add_mc_addr(struct ixgbe_hw *hw, u8 *mc_addr) 1344 { 1345 u32 rar_entries = ixgbe_get_num_rx_addrs(hw); 1346 1347 DEBUGOUT6(" MC Addr =%.2X %.2X %.2X %.2X %.2X %.2X\n", 1348 mc_addr[0], mc_addr[1], mc_addr[2], 1349 mc_addr[3], mc_addr[4], mc_addr[5]); 1350 1351 /* 1352 * Place this multicast address in the RAR if there is room, 1353 * else put it in the MTA 1354 */ 1355 if (hw->addr_ctrl.rar_used_count < rar_entries) { 1356 ixgbe_set_rar(hw, hw->addr_ctrl.rar_used_count, 1357 mc_addr, 0, IXGBE_RAH_AV); 1358 DEBUGOUT1("Added a multicast address to RAR[%d]\n", 1359 hw->addr_ctrl.rar_used_count); 1360 hw->addr_ctrl.rar_used_count++; 1361 hw->addr_ctrl.mc_addr_in_rar_count++; 1362 } else { 1363 ixgbe_set_mta(hw, mc_addr); 1364 } 1365 1366 DEBUGOUT("ixgbe_add_mc_addr Complete\n"); 1367 } 1368 1369 /** 1370 * ixgbe_update_mc_addr_list_generic - Updates MAC list of multicast addresses 1371 * @hw: pointer to hardware structure 1372 * @mc_addr_list: the list of new multicast addresses 1373 * @mc_addr_count: number of addresses 1374 * @pad: number of bytes between addresses in the list 1375 * 1376 * The given list replaces any existing list. Clears the MC addrs from receive 1377 * address registers and the multicast table. Uses unsed receive address 1378 * registers for the first multicast addresses, and hashes the rest into the 1379 * multicast table. 1380 **/ 1381 s32 ixgbe_update_mc_addr_list_generic(struct ixgbe_hw *hw, u8 *mc_addr_list, 1382 u32 mc_addr_count, u32 pad) 1383 { 1384 u32 i; 1385 u32 rar_entries = ixgbe_get_num_rx_addrs(hw); 1386 1387 /* 1388 * Set the new number of MC addresses that we are being requested to 1389 * use. 1390 */ 1391 hw->addr_ctrl.num_mc_addrs = mc_addr_count; 1392 hw->addr_ctrl.rar_used_count -= hw->addr_ctrl.mc_addr_in_rar_count; 1393 hw->addr_ctrl.mc_addr_in_rar_count = 0; 1394 hw->addr_ctrl.mta_in_use = 0; 1395 1396 /* Zero out the other receive addresses. */ 1397 DEBUGOUT("Clearing RAR[1-15]\n"); 1398 for (i = hw->addr_ctrl.rar_used_count; i < rar_entries; i++) { 1399 IXGBE_WRITE_REG(hw, IXGBE_RAL(i), 0); 1400 IXGBE_WRITE_REG(hw, IXGBE_RAH(i), 0); 1401 } 1402 1403 /* Clear the MTA */ 1404 DEBUGOUT(" Clearing MTA\n"); 1405 for (i = 0; i < IXGBE_MC_TBL_SIZE; i++) 1406 IXGBE_WRITE_REG(hw, IXGBE_MTA(i), 0); 1407 1408 /* Add the new addresses */ 1409 for (i = 0; i < mc_addr_count; i++) { 1410 DEBUGOUT(" Adding the multicast addresses:\n"); 1411 ixgbe_add_mc_addr(hw, mc_addr_list + 1412 (i * (IXGBE_ETH_LENGTH_OF_ADDRESS + pad))); 1413 } 1414 1415 /* Enable mta */ 1416 if (hw->addr_ctrl.mta_in_use > 0) 1417 IXGBE_WRITE_REG(hw, IXGBE_MCSTCTRL, 1418 IXGBE_MCSTCTRL_MFE | hw->mac.mc_filter_type); 1419 1420 DEBUGOUT("ixgbe_update_mc_addr_list_generic Complete\n"); 1421 return IXGBE_SUCCESS; 1422 } 1423 1424 /** 1425 * ixgbe_enable_mc_generic - Enable multicast address in RAR 1426 * @hw: pointer to hardware structure 1427 * 1428 * Enables multicast address in RAR and the use of the multicast hash table. 1429 **/ 1430 s32 ixgbe_enable_mc_generic(struct ixgbe_hw *hw) 1431 { 1432 u32 i; 1433 struct ixgbe_addr_filter_info *a = &hw->addr_ctrl; 1434 1435 if (a->mc_addr_in_rar_count > 0) 1436 for (i = (a->rar_used_count - a->mc_addr_in_rar_count); 1437 i < a->rar_used_count; i++) 1438 ixgbe_enable_rar(hw, i); 1439 1440 if (a->mta_in_use > 0) 1441 IXGBE_WRITE_REG(hw, IXGBE_MCSTCTRL, IXGBE_MCSTCTRL_MFE | 1442 hw->mac.mc_filter_type); 1443 1444 return IXGBE_SUCCESS; 1445 } 1446 1447 /** 1448 * ixgbe_disable_mc_generic - Disable mutlicast address in RAR 1449 * @hw: pointer to hardware structure 1450 * 1451 * Disables multicast address in RAR and the use of the multicast hash table. 1452 **/ 1453 s32 ixgbe_disable_mc_generic(struct ixgbe_hw *hw) 1454 { 1455 u32 i; 1456 struct ixgbe_addr_filter_info *a = &hw->addr_ctrl; 1457 1458 if (a->mc_addr_in_rar_count > 0) 1459 for (i = (a->rar_used_count - a->mc_addr_in_rar_count); 1460 i < a->rar_used_count; i++) 1461 ixgbe_disable_rar(hw, i); 1462 1463 if (a->mta_in_use > 0) 1464 IXGBE_WRITE_REG(hw, IXGBE_MCSTCTRL, hw->mac.mc_filter_type); 1465 1466 return IXGBE_SUCCESS; 1467 } 1468 1469 /** 1470 * ixgbe_clear_vfta_generic - Clear VLAN filter table 1471 * @hw: pointer to hardware structure 1472 * 1473 * Clears the VLAN filer table, and the VMDq index associated with the filter 1474 **/ 1475 s32 ixgbe_clear_vfta_generic(struct ixgbe_hw *hw) 1476 { 1477 u32 offset; 1478 u32 vlanbyte; 1479 1480 for (offset = 0; offset < IXGBE_VLAN_FILTER_TBL_SIZE; offset++) 1481 IXGBE_WRITE_REG(hw, IXGBE_VFTA(offset), 0); 1482 1483 for (vlanbyte = 0; vlanbyte < 4; vlanbyte++) 1484 for (offset = 0; offset < IXGBE_VLAN_FILTER_TBL_SIZE; offset++) 1485 IXGBE_WRITE_REG(hw, IXGBE_VFTAVIND(vlanbyte, offset), 1486 0); 1487 1488 return IXGBE_SUCCESS; 1489 } 1490 1491 /** 1492 * ixgbe_set_vfta_generic - Set VLAN filter table 1493 * @hw: pointer to hardware structure 1494 * @vlan: VLAN id to write to VLAN filter 1495 * @vind: VMDq output index that maps queue to VLAN id in VFTA 1496 * @vlan_on: boolean flag to turn on/off VLAN in VFTA 1497 * 1498 * Turn on/off specified VLAN in the VLAN filter table. 1499 **/ 1500 s32 ixgbe_set_vfta_generic(struct ixgbe_hw *hw, u32 vlan, u32 vind, 1501 bool vlan_on) 1502 { 1503 u32 VftaIndex; 1504 u32 BitOffset; 1505 u32 VftaReg; 1506 u32 VftaByte; 1507 1508 /* Determine 32-bit word position in array */ 1509 VftaIndex = (vlan >> 5) & 0x7F; /* upper seven bits */ 1510 1511 /* Determine the location of the (VMD) queue index */ 1512 VftaByte = ((vlan >> 3) & 0x03); /* bits (4:3) indicating byte array */ 1513 BitOffset = (vlan & 0x7) << 2; /* lower 3 bits indicate nibble */ 1514 1515 /* Set the nibble for VMD queue index */ 1516 VftaReg = IXGBE_READ_REG(hw, IXGBE_VFTAVIND(VftaByte, VftaIndex)); 1517 VftaReg &= (~(0x0F << BitOffset)); 1518 VftaReg |= (vind << BitOffset); 1519 IXGBE_WRITE_REG(hw, IXGBE_VFTAVIND(VftaByte, VftaIndex), VftaReg); 1520 1521 /* Determine the location of the bit for this VLAN id */ 1522 BitOffset = vlan & 0x1F; /* lower five bits */ 1523 1524 VftaReg = IXGBE_READ_REG(hw, IXGBE_VFTA(VftaIndex)); 1525 if (vlan_on) 1526 /* Turn on this VLAN id */ 1527 VftaReg |= (1 << BitOffset); 1528 else 1529 /* Turn off this VLAN id */ 1530 VftaReg &= ~(1 << BitOffset); 1531 IXGBE_WRITE_REG(hw, IXGBE_VFTA(VftaIndex), VftaReg); 1532 1533 return IXGBE_SUCCESS; 1534 } 1535 1536 /** 1537 * ixgbe_setup_fc_generic - Configure flow control settings 1538 * @hw: pointer to hardware structure 1539 * @packetbuf_num: packet buffer number (0-7) 1540 * 1541 * Configures the flow control settings based on SW configuration. 1542 * This function is used for 802.3x flow control configuration only. 1543 **/ 1544 s32 ixgbe_setup_fc_generic(struct ixgbe_hw *hw, s32 packetbuf_num) 1545 { 1546 u32 frctl_reg; 1547 u32 rmcs_reg; 1548 1549 if (packetbuf_num < 0 || packetbuf_num > 7) { 1550 DEBUGOUT1("Invalid packet buffer number [%d], expected range is" 1551 " 0-7\n", packetbuf_num); 1552 ASSERT(0); 1553 } 1554 1555 frctl_reg = IXGBE_READ_REG(hw, IXGBE_FCTRL); 1556 frctl_reg &= ~(IXGBE_FCTRL_RFCE | IXGBE_FCTRL_RPFCE); 1557 1558 rmcs_reg = IXGBE_READ_REG(hw, IXGBE_RMCS); 1559 rmcs_reg &= ~(IXGBE_RMCS_TFCE_PRIORITY | IXGBE_RMCS_TFCE_802_3X); 1560 1561 /* 1562 * We want to save off the original Flow Control configuration just in 1563 * case we get disconnected and then reconnected into a different hub 1564 * or switch with different Flow Control capabilities. 1565 */ 1566 hw->fc.type = hw->fc.original_type; 1567 1568 /* 1569 * The possible values of the "flow_control" parameter are: 1570 * 0: Flow control is completely disabled 1571 * 1: Rx flow control is enabled (we can receive pause frames but not 1572 * send pause frames). 1573 * 2: Tx flow control is enabled (we can send pause frames but we do not 1574 * support receiving pause frames) 1575 * 3: Both Rx and TX flow control (symmetric) are enabled. 1576 * other: Invalid. 1577 */ 1578 switch (hw->fc.type) { 1579 case ixgbe_fc_none: 1580 break; 1581 case ixgbe_fc_rx_pause: 1582 /* 1583 * RX Flow control is enabled, 1584 * and TX Flow control is disabled. 1585 */ 1586 frctl_reg |= IXGBE_FCTRL_RFCE; 1587 break; 1588 case ixgbe_fc_tx_pause: 1589 /* 1590 * TX Flow control is enabled, and RX Flow control is disabled, 1591 * by a software over-ride. 1592 */ 1593 rmcs_reg |= IXGBE_RMCS_TFCE_802_3X; 1594 break; 1595 case ixgbe_fc_full: 1596 /* 1597 * Flow control (both RX and TX) is enabled by a software 1598 * over-ride. 1599 */ 1600 frctl_reg |= IXGBE_FCTRL_RFCE; 1601 rmcs_reg |= IXGBE_RMCS_TFCE_802_3X; 1602 break; 1603 default: 1604 /* We should never get here. The value should be 0-3. */ 1605 DEBUGOUT("Flow control param set incorrectly\n"); 1606 ASSERT(0); 1607 break; 1608 } 1609 1610 /* Enable 802.3x based flow control settings. */ 1611 IXGBE_WRITE_REG(hw, IXGBE_FCTRL, frctl_reg); 1612 IXGBE_WRITE_REG(hw, IXGBE_RMCS, rmcs_reg); 1613 1614 /* 1615 * We need to set up the Receive Threshold high and low water 1616 * marks as well as (optionally) enabling the transmission of 1617 * XON frames. 1618 */ 1619 if (hw->fc.type & ixgbe_fc_tx_pause) { 1620 if (hw->fc.send_xon) { 1621 IXGBE_WRITE_REG(hw, IXGBE_FCRTL(packetbuf_num), 1622 (hw->fc.low_water | IXGBE_FCRTL_XONE)); 1623 } else { 1624 IXGBE_WRITE_REG(hw, IXGBE_FCRTL(packetbuf_num), 1625 hw->fc.low_water); 1626 } 1627 IXGBE_WRITE_REG(hw, IXGBE_FCRTH(packetbuf_num), 1628 (hw->fc.high_water)|IXGBE_FCRTH_FCEN); 1629 } 1630 1631 IXGBE_WRITE_REG(hw, IXGBE_FCTTV(0), hw->fc.pause_time); 1632 IXGBE_WRITE_REG(hw, IXGBE_FCRTV, (hw->fc.pause_time >> 1)); 1633 1634 return IXGBE_SUCCESS; 1635 } 1636 1637 /** 1638 * ixgbe_disable_pcie_master - Disable PCI-express master access 1639 * @hw: pointer to hardware structure 1640 * 1641 * Disables PCI-Express master access and verifies there are no pending 1642 * requests. IXGBE_ERR_MASTER_REQUESTS_PENDING is returned if master disable 1643 * bit hasn't caused the master requests to be disabled, else IXGBE_SUCCESS 1644 * is returned signifying master requests disabled. 1645 **/ 1646 s32 ixgbe_disable_pcie_master(struct ixgbe_hw *hw) 1647 { 1648 u32 ctrl; 1649 s32 i; 1650 s32 status = IXGBE_ERR_MASTER_REQUESTS_PENDING; 1651 1652 ctrl = IXGBE_READ_REG(hw, IXGBE_CTRL); 1653 ctrl |= IXGBE_CTRL_GIO_DIS; 1654 IXGBE_WRITE_REG(hw, IXGBE_CTRL, ctrl); 1655 1656 for (i = 0; i < IXGBE_PCI_MASTER_DISABLE_TIMEOUT; i++) { 1657 if (!(IXGBE_READ_REG(hw, IXGBE_STATUS) & IXGBE_STATUS_GIO)) { 1658 status = IXGBE_SUCCESS; 1659 break; 1660 } 1661 usec_delay(100); 1662 } 1663 1664 return status; 1665 } 1666 1667 1668 /** 1669 * ixgbe_acquire_swfw_sync - Aquire SWFW semaphore 1670 * @hw: pointer to hardware structure 1671 * @mask: Mask to specify wich semaphore to acquire 1672 * 1673 * Aquires the SWFW semaphore throught the GSSR register for the specified 1674 * function (CSR, PHY0, PHY1, EEPROM, Flash) 1675 **/ 1676 s32 ixgbe_acquire_swfw_sync(struct ixgbe_hw *hw, u16 mask) 1677 { 1678 u32 gssr; 1679 u32 swmask = mask; 1680 u32 fwmask = mask << 5; 1681 s32 timeout = 200; 1682 1683 while (timeout) { 1684 if (ixgbe_get_eeprom_semaphore(hw)) 1685 return -IXGBE_ERR_SWFW_SYNC; 1686 1687 gssr = IXGBE_READ_REG(hw, IXGBE_GSSR); 1688 if (!(gssr & (fwmask | swmask))) 1689 break; 1690 1691 /* 1692 * Firmware currently using resource (fwmask) or other software 1693 * thread currently using resource (swmask) 1694 */ 1695 ixgbe_release_eeprom_semaphore(hw); 1696 msec_delay(5); 1697 timeout--; 1698 } 1699 1700 if (!timeout) { 1701 DEBUGOUT("Driver can't access resource, GSSR timeout.\n"); 1702 return -IXGBE_ERR_SWFW_SYNC; 1703 } 1704 1705 gssr |= swmask; 1706 IXGBE_WRITE_REG(hw, IXGBE_GSSR, gssr); 1707 1708 ixgbe_release_eeprom_semaphore(hw); 1709 return IXGBE_SUCCESS; 1710 } 1711 1712 /** 1713 * ixgbe_release_swfw_sync - Release SWFW semaphore 1714 * @hw: pointer to hardware structure 1715 * @mask: Mask to specify wich semaphore to release 1716 * 1717 * Releases the SWFW semaphore throught the GSSR register for the specified 1718 * function (CSR, PHY0, PHY1, EEPROM, Flash) 1719 **/ 1720 void ixgbe_release_swfw_sync(struct ixgbe_hw *hw, u16 mask) 1721 { 1722 u32 gssr; 1723 u32 swmask = mask; 1724 1725 ixgbe_get_eeprom_semaphore(hw); 1726 1727 gssr = IXGBE_READ_REG(hw, IXGBE_GSSR); 1728 gssr &= ~swmask; 1729 IXGBE_WRITE_REG(hw, IXGBE_GSSR, gssr); 1730 1731 ixgbe_release_eeprom_semaphore(hw); 1732 } 1733 1734