1 /****************************************************************************** 2 3 Copyright (c) 2001-2009, Intel Corporation 4 All rights reserved. 5 6 Redistribution and use in source and binary forms, with or without 7 modification, are permitted provided that the following conditions are met: 8 9 1. Redistributions of source code must retain the above copyright notice, 10 this list of conditions and the following disclaimer. 11 12 2. Redistributions in binary form must reproduce the above copyright 13 notice, this list of conditions and the following disclaimer in the 14 documentation and/or other materials provided with the distribution. 15 16 3. Neither the name of the Intel Corporation nor the names of its 17 contributors may be used to endorse or promote products derived from 18 this software without specific prior written permission. 19 20 THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 21 AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 22 IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 23 ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE 24 LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 25 CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 26 SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 27 INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 28 CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 29 ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 30 POSSIBILITY OF SUCH DAMAGE. 31 32 ******************************************************************************/ 33 /*$FreeBSD$*/ 34 35 #include "ixgbe_api.h" 36 #include "ixgbe_common.h" 37 38 extern s32 ixgbe_init_ops_82598(struct ixgbe_hw *hw); 39 extern s32 ixgbe_init_ops_82599(struct ixgbe_hw *hw); 40 41 /** 42 * ixgbe_init_shared_code - Initialize the shared code 43 * @hw: pointer to hardware structure 44 * 45 * This will assign function pointers and assign the MAC type and PHY code. 46 * Does not touch the hardware. This function must be called prior to any 47 * other function in the shared code. The ixgbe_hw structure should be 48 * memset to 0 prior to calling this function. The following fields in 49 * hw structure should be filled in prior to calling this function: 50 * hw_addr, back, device_id, vendor_id, subsystem_device_id, 51 * subsystem_vendor_id, and revision_id 52 **/ 53 s32 ixgbe_init_shared_code(struct ixgbe_hw *hw) 54 { 55 s32 status; 56 57 DEBUGFUNC("ixgbe_init_shared_code"); 58 59 /* 60 * Set the mac type 61 */ 62 ixgbe_set_mac_type(hw); 63 64 switch (hw->mac.type) { 65 case ixgbe_mac_82598EB: 66 status = ixgbe_init_ops_82598(hw); 67 break; 68 case ixgbe_mac_82599EB: 69 status = ixgbe_init_ops_82599(hw); 70 break; 71 default: 72 status = IXGBE_ERR_DEVICE_NOT_SUPPORTED; 73 break; 74 } 75 76 return status; 77 } 78 79 /** 80 * ixgbe_set_mac_type - Sets MAC type 81 * @hw: pointer to the HW structure 82 * 83 * This function sets the mac type of the adapter based on the 84 * vendor ID and device ID stored in the hw structure. 85 **/ 86 s32 ixgbe_set_mac_type(struct ixgbe_hw *hw) 87 { 88 s32 ret_val = IXGBE_SUCCESS; 89 90 DEBUGFUNC("ixgbe_set_mac_type\n"); 91 92 if (hw->vendor_id == IXGBE_INTEL_VENDOR_ID) { 93 switch (hw->device_id) { 94 case IXGBE_DEV_ID_82598: 95 case IXGBE_DEV_ID_82598_BX: 96 case IXGBE_DEV_ID_82598AF_SINGLE_PORT: 97 case IXGBE_DEV_ID_82598AF_DUAL_PORT: 98 case IXGBE_DEV_ID_82598AT: 99 case IXGBE_DEV_ID_82598AT2: 100 case IXGBE_DEV_ID_82598EB_CX4: 101 case IXGBE_DEV_ID_82598_CX4_DUAL_PORT: 102 case IXGBE_DEV_ID_82598_DA_DUAL_PORT: 103 case IXGBE_DEV_ID_82598_SR_DUAL_PORT_EM: 104 case IXGBE_DEV_ID_82598EB_XF_LR: 105 case IXGBE_DEV_ID_82598EB_SFP_LOM: 106 hw->mac.type = ixgbe_mac_82598EB; 107 break; 108 case IXGBE_DEV_ID_82599_KX4: 109 case IXGBE_DEV_ID_82599_KX4_MEZZ: 110 case IXGBE_DEV_ID_82599_XAUI_LOM: 111 case IXGBE_DEV_ID_82599_COMBO_BACKPLANE: 112 case IXGBE_DEV_ID_82599_SFP: 113 case IXGBE_DEV_ID_82599_CX4: 114 hw->mac.type = ixgbe_mac_82599EB; 115 break; 116 default: 117 ret_val = IXGBE_ERR_DEVICE_NOT_SUPPORTED; 118 break; 119 } 120 } else { 121 ret_val = IXGBE_ERR_DEVICE_NOT_SUPPORTED; 122 } 123 124 DEBUGOUT2("ixgbe_set_mac_type found mac: %d, returns: %d\n", 125 hw->mac.type, ret_val); 126 return ret_val; 127 } 128 129 /** 130 * ixgbe_init_hw - Initialize the hardware 131 * @hw: pointer to hardware structure 132 * 133 * Initialize the hardware by resetting and then starting the hardware 134 **/ 135 s32 ixgbe_init_hw(struct ixgbe_hw *hw) 136 { 137 return ixgbe_call_func(hw, hw->mac.ops.init_hw, (hw), 138 IXGBE_NOT_IMPLEMENTED); 139 } 140 141 /** 142 * ixgbe_reset_hw - Performs a hardware reset 143 * @hw: pointer to hardware structure 144 * 145 * Resets the hardware by resetting the transmit and receive units, masks and 146 * clears all interrupts, performs a PHY reset, and performs a MAC reset 147 **/ 148 s32 ixgbe_reset_hw(struct ixgbe_hw *hw) 149 { 150 return ixgbe_call_func(hw, hw->mac.ops.reset_hw, (hw), 151 IXGBE_NOT_IMPLEMENTED); 152 } 153 154 /** 155 * ixgbe_start_hw - Prepares hardware for Rx/Tx 156 * @hw: pointer to hardware structure 157 * 158 * Starts the hardware by filling the bus info structure and media type, 159 * clears all on chip counters, initializes receive address registers, 160 * multicast table, VLAN filter table, calls routine to setup link and 161 * flow control settings, and leaves transmit and receive units disabled 162 * and uninitialized. 163 **/ 164 s32 ixgbe_start_hw(struct ixgbe_hw *hw) 165 { 166 return ixgbe_call_func(hw, hw->mac.ops.start_hw, (hw), 167 IXGBE_NOT_IMPLEMENTED); 168 } 169 170 /** 171 * ixgbe_clear_hw_cntrs - Clear hardware counters 172 * @hw: pointer to hardware structure 173 * 174 * Clears all hardware statistics counters by reading them from the hardware 175 * Statistics counters are clear on read. 176 **/ 177 s32 ixgbe_clear_hw_cntrs(struct ixgbe_hw *hw) 178 { 179 return ixgbe_call_func(hw, hw->mac.ops.clear_hw_cntrs, (hw), 180 IXGBE_NOT_IMPLEMENTED); 181 } 182 183 /** 184 * ixgbe_get_media_type - Get media type 185 * @hw: pointer to hardware structure 186 * 187 * Returns the media type (fiber, copper, backplane) 188 **/ 189 enum ixgbe_media_type ixgbe_get_media_type(struct ixgbe_hw *hw) 190 { 191 return ixgbe_call_func(hw, hw->mac.ops.get_media_type, (hw), 192 ixgbe_media_type_unknown); 193 } 194 195 /** 196 * ixgbe_get_mac_addr - Get MAC address 197 * @hw: pointer to hardware structure 198 * @mac_addr: Adapter MAC address 199 * 200 * Reads the adapter's MAC address from the first Receive Address Register 201 * (RAR0) A reset of the adapter must have been performed prior to calling 202 * this function in order for the MAC address to have been loaded from the 203 * EEPROM into RAR0 204 **/ 205 s32 ixgbe_get_mac_addr(struct ixgbe_hw *hw, u8 *mac_addr) 206 { 207 return ixgbe_call_func(hw, hw->mac.ops.get_mac_addr, 208 (hw, mac_addr), IXGBE_NOT_IMPLEMENTED); 209 } 210 211 /** 212 * ixgbe_get_san_mac_addr - Get SAN MAC address 213 * @hw: pointer to hardware structure 214 * @san_mac_addr: SAN MAC address 215 * 216 * Reads the SAN MAC address from the EEPROM, if it's available. This is 217 * per-port, so set_lan_id() must be called before reading the addresses. 218 **/ 219 s32 ixgbe_get_san_mac_addr(struct ixgbe_hw *hw, u8 *san_mac_addr) 220 { 221 return ixgbe_call_func(hw, hw->mac.ops.get_san_mac_addr, 222 (hw, san_mac_addr), IXGBE_NOT_IMPLEMENTED); 223 } 224 225 /** 226 * ixgbe_set_san_mac_addr - Write a SAN MAC address 227 * @hw: pointer to hardware structure 228 * @san_mac_addr: SAN MAC address 229 * 230 * Writes A SAN MAC address to the EEPROM. 231 **/ 232 s32 ixgbe_set_san_mac_addr(struct ixgbe_hw *hw, u8 *san_mac_addr) 233 { 234 return ixgbe_call_func(hw, hw->mac.ops.set_san_mac_addr, 235 (hw, san_mac_addr), IXGBE_NOT_IMPLEMENTED); 236 } 237 238 /** 239 * ixgbe_get_device_caps - Get additional device capabilities 240 * @hw: pointer to hardware structure 241 * @device_caps: the EEPROM word for device capabilities 242 * 243 * Reads the extra device capabilities from the EEPROM 244 **/ 245 s32 ixgbe_get_device_caps(struct ixgbe_hw *hw, u16 *device_caps) 246 { 247 return ixgbe_call_func(hw, hw->mac.ops.get_device_caps, 248 (hw, device_caps), IXGBE_NOT_IMPLEMENTED); 249 } 250 251 /** 252 * ixgbe_get_wwn_prefix - Get alternative WWNN/WWPN prefix from the EEPROM 253 * @hw: pointer to hardware structure 254 * @wwnn_prefix: the alternative WWNN prefix 255 * @wwpn_prefix: the alternative WWPN prefix 256 * 257 * This function will read the EEPROM from the alternative SAN MAC address 258 * block to check the support for the alternative WWNN/WWPN prefix support. 259 **/ 260 s32 ixgbe_get_wwn_prefix(struct ixgbe_hw *hw, u16 *wwnn_prefix, 261 u16 *wwpn_prefix) 262 { 263 return ixgbe_call_func(hw, hw->mac.ops.get_wwn_prefix, 264 (hw, wwnn_prefix, wwpn_prefix), 265 IXGBE_NOT_IMPLEMENTED); 266 } 267 268 /** 269 * ixgbe_get_bus_info - Set PCI bus info 270 * @hw: pointer to hardware structure 271 * 272 * Sets the PCI bus info (speed, width, type) within the ixgbe_hw structure 273 **/ 274 s32 ixgbe_get_bus_info(struct ixgbe_hw *hw) 275 { 276 return ixgbe_call_func(hw, hw->mac.ops.get_bus_info, (hw), 277 IXGBE_NOT_IMPLEMENTED); 278 } 279 280 /** 281 * ixgbe_get_num_of_tx_queues - Get Tx queues 282 * @hw: pointer to hardware structure 283 * 284 * Returns the number of transmit queues for the given adapter. 285 **/ 286 u32 ixgbe_get_num_of_tx_queues(struct ixgbe_hw *hw) 287 { 288 return hw->mac.max_tx_queues; 289 } 290 291 /** 292 * ixgbe_get_num_of_rx_queues - Get Rx queues 293 * @hw: pointer to hardware structure 294 * 295 * Returns the number of receive queues for the given adapter. 296 **/ 297 u32 ixgbe_get_num_of_rx_queues(struct ixgbe_hw *hw) 298 { 299 return hw->mac.max_rx_queues; 300 } 301 302 /** 303 * ixgbe_stop_adapter - Disable Rx/Tx units 304 * @hw: pointer to hardware structure 305 * 306 * Sets the adapter_stopped flag within ixgbe_hw struct. Clears interrupts, 307 * disables transmit and receive units. The adapter_stopped flag is used by 308 * the shared code and drivers to determine if the adapter is in a stopped 309 * state and should not touch the hardware. 310 **/ 311 s32 ixgbe_stop_adapter(struct ixgbe_hw *hw) 312 { 313 return ixgbe_call_func(hw, hw->mac.ops.stop_adapter, (hw), 314 IXGBE_NOT_IMPLEMENTED); 315 } 316 317 /** 318 * ixgbe_read_pba_num - Reads part number from EEPROM 319 * @hw: pointer to hardware structure 320 * @pba_num: stores the part number from the EEPROM 321 * 322 * Reads the part number from the EEPROM. 323 **/ 324 s32 ixgbe_read_pba_num(struct ixgbe_hw *hw, u32 *pba_num) 325 { 326 return ixgbe_read_pba_num_generic(hw, pba_num); 327 } 328 329 /** 330 * ixgbe_identify_phy - Get PHY type 331 * @hw: pointer to hardware structure 332 * 333 * Determines the physical layer module found on the current adapter. 334 **/ 335 s32 ixgbe_identify_phy(struct ixgbe_hw *hw) 336 { 337 s32 status = IXGBE_SUCCESS; 338 339 if (hw->phy.type == ixgbe_phy_unknown) { 340 status = ixgbe_call_func(hw, 341 hw->phy.ops.identify, 342 (hw), 343 IXGBE_NOT_IMPLEMENTED); 344 } 345 346 return status; 347 } 348 349 /** 350 * ixgbe_reset_phy - Perform a PHY reset 351 * @hw: pointer to hardware structure 352 **/ 353 s32 ixgbe_reset_phy(struct ixgbe_hw *hw) 354 { 355 s32 status = IXGBE_SUCCESS; 356 357 if (hw->phy.type == ixgbe_phy_unknown) { 358 if (ixgbe_identify_phy(hw) != IXGBE_SUCCESS) 359 status = IXGBE_ERR_PHY; 360 } 361 362 if (status == IXGBE_SUCCESS) { 363 status = ixgbe_call_func(hw, hw->phy.ops.reset, (hw), 364 IXGBE_NOT_IMPLEMENTED); 365 } 366 return status; 367 } 368 369 /** 370 * ixgbe_get_phy_firmware_version - 371 * @hw: pointer to hardware structure 372 * @firmware_version: pointer to firmware version 373 **/ 374 s32 ixgbe_get_phy_firmware_version(struct ixgbe_hw *hw, u16 *firmware_version) 375 { 376 s32 status = IXGBE_SUCCESS; 377 378 status = ixgbe_call_func(hw, hw->phy.ops.get_firmware_version, 379 (hw, firmware_version), 380 IXGBE_NOT_IMPLEMENTED); 381 return status; 382 } 383 384 /** 385 * ixgbe_read_phy_reg - Read PHY register 386 * @hw: pointer to hardware structure 387 * @reg_addr: 32 bit address of PHY register to read 388 * @phy_data: Pointer to read data from PHY register 389 * 390 * Reads a value from a specified PHY register 391 **/ 392 s32 ixgbe_read_phy_reg(struct ixgbe_hw *hw, u32 reg_addr, u32 device_type, 393 u16 *phy_data) 394 { 395 if (hw->phy.id == 0) 396 ixgbe_identify_phy(hw); 397 398 return ixgbe_call_func(hw, hw->phy.ops.read_reg, (hw, reg_addr, 399 device_type, phy_data), IXGBE_NOT_IMPLEMENTED); 400 } 401 402 /** 403 * ixgbe_write_phy_reg - Write PHY register 404 * @hw: pointer to hardware structure 405 * @reg_addr: 32 bit PHY register to write 406 * @phy_data: Data to write to the PHY register 407 * 408 * Writes a value to specified PHY register 409 **/ 410 s32 ixgbe_write_phy_reg(struct ixgbe_hw *hw, u32 reg_addr, u32 device_type, 411 u16 phy_data) 412 { 413 if (hw->phy.id == 0) 414 ixgbe_identify_phy(hw); 415 416 return ixgbe_call_func(hw, hw->phy.ops.write_reg, (hw, reg_addr, 417 device_type, phy_data), IXGBE_NOT_IMPLEMENTED); 418 } 419 420 /** 421 * ixgbe_setup_phy_link - Restart PHY autoneg 422 * @hw: pointer to hardware structure 423 * 424 * Restart autonegotiation and PHY and waits for completion. 425 **/ 426 s32 ixgbe_setup_phy_link(struct ixgbe_hw *hw) 427 { 428 return ixgbe_call_func(hw, hw->phy.ops.setup_link, (hw), 429 IXGBE_NOT_IMPLEMENTED); 430 } 431 432 /** 433 * ixgbe_check_phy_link - Determine link and speed status 434 * @hw: pointer to hardware structure 435 * 436 * Reads a PHY register to determine if link is up and the current speed for 437 * the PHY. 438 **/ 439 s32 ixgbe_check_phy_link(struct ixgbe_hw *hw, ixgbe_link_speed *speed, 440 bool *link_up) 441 { 442 return ixgbe_call_func(hw, hw->phy.ops.check_link, (hw, speed, 443 link_up), IXGBE_NOT_IMPLEMENTED); 444 } 445 446 /** 447 * ixgbe_setup_phy_link_speed - Set auto advertise 448 * @hw: pointer to hardware structure 449 * @speed: new link speed 450 * @autoneg: TRUE if autonegotiation enabled 451 * 452 * Sets the auto advertised capabilities 453 **/ 454 s32 ixgbe_setup_phy_link_speed(struct ixgbe_hw *hw, ixgbe_link_speed speed, 455 bool autoneg, 456 bool autoneg_wait_to_complete) 457 { 458 return ixgbe_call_func(hw, hw->phy.ops.setup_link_speed, (hw, speed, 459 autoneg, autoneg_wait_to_complete), 460 IXGBE_NOT_IMPLEMENTED); 461 } 462 463 /** 464 * ixgbe_check_link - Get link and speed status 465 * @hw: pointer to hardware structure 466 * 467 * Reads the links register to determine if link is up and the current speed 468 **/ 469 s32 ixgbe_check_link(struct ixgbe_hw *hw, ixgbe_link_speed *speed, 470 bool *link_up, bool link_up_wait_to_complete) 471 { 472 return ixgbe_call_func(hw, hw->mac.ops.check_link, (hw, speed, 473 link_up, link_up_wait_to_complete), 474 IXGBE_NOT_IMPLEMENTED); 475 } 476 477 /** 478 * ixgbe_setup_link - Set link speed 479 * @hw: pointer to hardware structure 480 * @speed: new link speed 481 * @autoneg: TRUE if autonegotiation enabled 482 * 483 * Configures link settings. Restarts the link. 484 * Performs autonegotiation if needed. 485 **/ 486 s32 ixgbe_setup_link(struct ixgbe_hw *hw, ixgbe_link_speed speed, 487 bool autoneg, 488 bool autoneg_wait_to_complete) 489 { 490 return ixgbe_call_func(hw, hw->mac.ops.setup_link, (hw, speed, 491 autoneg, autoneg_wait_to_complete), 492 IXGBE_NOT_IMPLEMENTED); 493 } 494 495 /** 496 * ixgbe_get_link_capabilities - Returns link capabilities 497 * @hw: pointer to hardware structure 498 * 499 * Determines the link capabilities of the current configuration. 500 **/ 501 s32 ixgbe_get_link_capabilities(struct ixgbe_hw *hw, ixgbe_link_speed *speed, 502 bool *autoneg) 503 { 504 return ixgbe_call_func(hw, hw->mac.ops.get_link_capabilities, (hw, 505 speed, autoneg), IXGBE_NOT_IMPLEMENTED); 506 } 507 508 /** 509 * ixgbe_led_on - Turn on LEDs 510 * @hw: pointer to hardware structure 511 * @index: led number to turn on 512 * 513 * Turns on the software controllable LEDs. 514 **/ 515 s32 ixgbe_led_on(struct ixgbe_hw *hw, u32 index) 516 { 517 return ixgbe_call_func(hw, hw->mac.ops.led_on, (hw, index), 518 IXGBE_NOT_IMPLEMENTED); 519 } 520 521 /** 522 * ixgbe_led_off - Turn off LEDs 523 * @hw: pointer to hardware structure 524 * @index: led number to turn off 525 * 526 * Turns off the software controllable LEDs. 527 **/ 528 s32 ixgbe_led_off(struct ixgbe_hw *hw, u32 index) 529 { 530 return ixgbe_call_func(hw, hw->mac.ops.led_off, (hw, index), 531 IXGBE_NOT_IMPLEMENTED); 532 } 533 534 /** 535 * ixgbe_blink_led_start - Blink LEDs 536 * @hw: pointer to hardware structure 537 * @index: led number to blink 538 * 539 * Blink LED based on index. 540 **/ 541 s32 ixgbe_blink_led_start(struct ixgbe_hw *hw, u32 index) 542 { 543 return ixgbe_call_func(hw, hw->mac.ops.blink_led_start, (hw, index), 544 IXGBE_NOT_IMPLEMENTED); 545 } 546 547 /** 548 * ixgbe_blink_led_stop - Stop blinking LEDs 549 * @hw: pointer to hardware structure 550 * 551 * Stop blinking LED based on index. 552 **/ 553 s32 ixgbe_blink_led_stop(struct ixgbe_hw *hw, u32 index) 554 { 555 return ixgbe_call_func(hw, hw->mac.ops.blink_led_stop, (hw, index), 556 IXGBE_NOT_IMPLEMENTED); 557 } 558 559 /** 560 * ixgbe_init_eeprom_params - Initialize EEPROM parameters 561 * @hw: pointer to hardware structure 562 * 563 * Initializes the EEPROM parameters ixgbe_eeprom_info within the 564 * ixgbe_hw struct in order to set up EEPROM access. 565 **/ 566 s32 ixgbe_init_eeprom_params(struct ixgbe_hw *hw) 567 { 568 return ixgbe_call_func(hw, hw->eeprom.ops.init_params, (hw), 569 IXGBE_NOT_IMPLEMENTED); 570 } 571 572 573 /** 574 * ixgbe_write_eeprom - Write word to EEPROM 575 * @hw: pointer to hardware structure 576 * @offset: offset within the EEPROM to be written to 577 * @data: 16 bit word to be written to the EEPROM 578 * 579 * Writes 16 bit value to EEPROM. If ixgbe_eeprom_update_checksum is not 580 * called after this function, the EEPROM will most likely contain an 581 * invalid checksum. 582 **/ 583 s32 ixgbe_write_eeprom(struct ixgbe_hw *hw, u16 offset, u16 data) 584 { 585 return ixgbe_call_func(hw, hw->eeprom.ops.write, (hw, offset, data), 586 IXGBE_NOT_IMPLEMENTED); 587 } 588 589 /** 590 * ixgbe_read_eeprom - Read word from EEPROM 591 * @hw: pointer to hardware structure 592 * @offset: offset within the EEPROM to be read 593 * @data: read 16 bit value from EEPROM 594 * 595 * Reads 16 bit value from EEPROM 596 **/ 597 s32 ixgbe_read_eeprom(struct ixgbe_hw *hw, u16 offset, u16 *data) 598 { 599 return ixgbe_call_func(hw, hw->eeprom.ops.read, (hw, offset, data), 600 IXGBE_NOT_IMPLEMENTED); 601 } 602 603 /** 604 * ixgbe_validate_eeprom_checksum - Validate EEPROM checksum 605 * @hw: pointer to hardware structure 606 * @checksum_val: calculated checksum 607 * 608 * Performs checksum calculation and validates the EEPROM checksum 609 **/ 610 s32 ixgbe_validate_eeprom_checksum(struct ixgbe_hw *hw, u16 *checksum_val) 611 { 612 return ixgbe_call_func(hw, hw->eeprom.ops.validate_checksum, 613 (hw, checksum_val), IXGBE_NOT_IMPLEMENTED); 614 } 615 616 /** 617 * ixgbe_eeprom_update_checksum - Updates the EEPROM checksum 618 * @hw: pointer to hardware structure 619 **/ 620 s32 ixgbe_update_eeprom_checksum(struct ixgbe_hw *hw) 621 { 622 return ixgbe_call_func(hw, hw->eeprom.ops.update_checksum, (hw), 623 IXGBE_NOT_IMPLEMENTED); 624 } 625 626 /** 627 * ixgbe_insert_mac_addr - Find a RAR for this mac address 628 * @hw: pointer to hardware structure 629 * @addr: Address to put into receive address register 630 * @vmdq: VMDq pool to assign 631 * 632 * Puts an ethernet address into a receive address register, or 633 * finds the rar that it is aleady in; adds to the pool list 634 **/ 635 s32 ixgbe_insert_mac_addr(struct ixgbe_hw *hw, u8 *addr, u32 vmdq) 636 { 637 return ixgbe_call_func(hw, hw->mac.ops.insert_mac_addr, 638 (hw, addr, vmdq), 639 IXGBE_NOT_IMPLEMENTED); 640 } 641 642 /** 643 * ixgbe_set_rar - Set Rx address register 644 * @hw: pointer to hardware structure 645 * @index: Receive address register to write 646 * @addr: Address to put into receive address register 647 * @vmdq: VMDq "set" 648 * @enable_addr: set flag that address is active 649 * 650 * Puts an ethernet address into a receive address register. 651 **/ 652 s32 ixgbe_set_rar(struct ixgbe_hw *hw, u32 index, u8 *addr, u32 vmdq, 653 u32 enable_addr) 654 { 655 return ixgbe_call_func(hw, hw->mac.ops.set_rar, (hw, index, addr, vmdq, 656 enable_addr), IXGBE_NOT_IMPLEMENTED); 657 } 658 659 /** 660 * ixgbe_clear_rar - Clear Rx address register 661 * @hw: pointer to hardware structure 662 * @index: Receive address register to write 663 * 664 * Puts an ethernet address into a receive address register. 665 **/ 666 s32 ixgbe_clear_rar(struct ixgbe_hw *hw, u32 index) 667 { 668 return ixgbe_call_func(hw, hw->mac.ops.clear_rar, (hw, index), 669 IXGBE_NOT_IMPLEMENTED); 670 } 671 672 /** 673 * ixgbe_set_vmdq - Associate a VMDq index with a receive address 674 * @hw: pointer to hardware structure 675 * @rar: receive address register index to associate with VMDq index 676 * @vmdq: VMDq set or pool index 677 **/ 678 s32 ixgbe_set_vmdq(struct ixgbe_hw *hw, u32 rar, u32 vmdq) 679 { 680 return ixgbe_call_func(hw, hw->mac.ops.set_vmdq, (hw, rar, vmdq), 681 IXGBE_NOT_IMPLEMENTED); 682 } 683 684 /** 685 * ixgbe_clear_vmdq - Disassociate a VMDq index from a receive address 686 * @hw: pointer to hardware structure 687 * @rar: receive address register index to disassociate with VMDq index 688 * @vmdq: VMDq set or pool index 689 **/ 690 s32 ixgbe_clear_vmdq(struct ixgbe_hw *hw, u32 rar, u32 vmdq) 691 { 692 return ixgbe_call_func(hw, hw->mac.ops.clear_vmdq, (hw, rar, vmdq), 693 IXGBE_NOT_IMPLEMENTED); 694 } 695 696 /** 697 * ixgbe_init_rx_addrs - Initializes receive address filters. 698 * @hw: pointer to hardware structure 699 * 700 * Places the MAC address in receive address register 0 and clears the rest 701 * of the receive address registers. Clears the multicast table. Assumes 702 * the receiver is in reset when the routine is called. 703 **/ 704 s32 ixgbe_init_rx_addrs(struct ixgbe_hw *hw) 705 { 706 return ixgbe_call_func(hw, hw->mac.ops.init_rx_addrs, (hw), 707 IXGBE_NOT_IMPLEMENTED); 708 } 709 710 /** 711 * ixgbe_get_num_rx_addrs - Returns the number of RAR entries. 712 * @hw: pointer to hardware structure 713 **/ 714 u32 ixgbe_get_num_rx_addrs(struct ixgbe_hw *hw) 715 { 716 return hw->mac.num_rar_entries; 717 } 718 719 /** 720 * ixgbe_update_uc_addr_list - Updates the MAC's list of secondary addresses 721 * @hw: pointer to hardware structure 722 * @addr_list: the list of new multicast addresses 723 * @addr_count: number of addresses 724 * @func: iterator function to walk the multicast address list 725 * 726 * The given list replaces any existing list. Clears the secondary addrs from 727 * receive address registers. Uses unused receive address registers for the 728 * first secondary addresses, and falls back to promiscuous mode as needed. 729 **/ 730 s32 ixgbe_update_uc_addr_list(struct ixgbe_hw *hw, u8 *addr_list, 731 u32 addr_count, ixgbe_mc_addr_itr func) 732 { 733 return ixgbe_call_func(hw, hw->mac.ops.update_uc_addr_list, (hw, 734 addr_list, addr_count, func), 735 IXGBE_NOT_IMPLEMENTED); 736 } 737 738 /** 739 * ixgbe_update_mc_addr_list - Updates the MAC's list of multicast addresses 740 * @hw: pointer to hardware structure 741 * @mc_addr_list: the list of new multicast addresses 742 * @mc_addr_count: number of addresses 743 * @func: iterator function to walk the multicast address list 744 * 745 * The given list replaces any existing list. Clears the MC addrs from receive 746 * address registers and the multicast table. Uses unused receive address 747 * registers for the first multicast addresses, and hashes the rest into the 748 * multicast table. 749 **/ 750 s32 ixgbe_update_mc_addr_list(struct ixgbe_hw *hw, u8 *mc_addr_list, 751 u32 mc_addr_count, ixgbe_mc_addr_itr func) 752 { 753 return ixgbe_call_func(hw, hw->mac.ops.update_mc_addr_list, (hw, 754 mc_addr_list, mc_addr_count, func), 755 IXGBE_NOT_IMPLEMENTED); 756 } 757 758 /** 759 * ixgbe_enable_mc - Enable multicast address in RAR 760 * @hw: pointer to hardware structure 761 * 762 * Enables multicast address in RAR and the use of the multicast hash table. 763 **/ 764 s32 ixgbe_enable_mc(struct ixgbe_hw *hw) 765 { 766 return ixgbe_call_func(hw, hw->mac.ops.enable_mc, (hw), 767 IXGBE_NOT_IMPLEMENTED); 768 } 769 770 /** 771 * ixgbe_disable_mc - Disable multicast address in RAR 772 * @hw: pointer to hardware structure 773 * 774 * Disables multicast address in RAR and the use of the multicast hash table. 775 **/ 776 s32 ixgbe_disable_mc(struct ixgbe_hw *hw) 777 { 778 return ixgbe_call_func(hw, hw->mac.ops.disable_mc, (hw), 779 IXGBE_NOT_IMPLEMENTED); 780 } 781 782 /** 783 * ixgbe_clear_vfta - Clear VLAN filter table 784 * @hw: pointer to hardware structure 785 * 786 * Clears the VLAN filer table, and the VMDq index associated with the filter 787 **/ 788 s32 ixgbe_clear_vfta(struct ixgbe_hw *hw) 789 { 790 return ixgbe_call_func(hw, hw->mac.ops.clear_vfta, (hw), 791 IXGBE_NOT_IMPLEMENTED); 792 } 793 794 /** 795 * ixgbe_set_vfta - Set VLAN filter table 796 * @hw: pointer to hardware structure 797 * @vlan: VLAN id to write to VLAN filter 798 * @vind: VMDq output index that maps queue to VLAN id in VFTA 799 * @vlan_on: boolean flag to turn on/off VLAN in VFTA 800 * 801 * Turn on/off specified VLAN in the VLAN filter table. 802 **/ 803 s32 ixgbe_set_vfta(struct ixgbe_hw *hw, u32 vlan, u32 vind, bool vlan_on) 804 { 805 return ixgbe_call_func(hw, hw->mac.ops.set_vfta, (hw, vlan, vind, 806 vlan_on), IXGBE_NOT_IMPLEMENTED); 807 } 808 809 /** 810 * ixgbe_fc_enable - Enable flow control 811 * @hw: pointer to hardware structure 812 * @packetbuf_num: packet buffer number (0-7) 813 * 814 * Configures the flow control settings based on SW configuration. 815 **/ 816 s32 ixgbe_fc_enable(struct ixgbe_hw *hw, s32 packetbuf_num) 817 { 818 return ixgbe_call_func(hw, hw->mac.ops.fc_enable, (hw, packetbuf_num), 819 IXGBE_NOT_IMPLEMENTED); 820 } 821 822 /** 823 * ixgbe_read_analog_reg8 - Reads 8 bit analog register 824 * @hw: pointer to hardware structure 825 * @reg: analog register to read 826 * @val: read value 827 * 828 * Performs write operation to analog register specified. 829 **/ 830 s32 ixgbe_read_analog_reg8(struct ixgbe_hw *hw, u32 reg, u8 *val) 831 { 832 return ixgbe_call_func(hw, hw->mac.ops.read_analog_reg8, (hw, reg, 833 val), IXGBE_NOT_IMPLEMENTED); 834 } 835 836 /** 837 * ixgbe_write_analog_reg8 - Writes 8 bit analog register 838 * @hw: pointer to hardware structure 839 * @reg: analog register to write 840 * @val: value to write 841 * 842 * Performs write operation to Atlas analog register specified. 843 **/ 844 s32 ixgbe_write_analog_reg8(struct ixgbe_hw *hw, u32 reg, u8 val) 845 { 846 return ixgbe_call_func(hw, hw->mac.ops.write_analog_reg8, (hw, reg, 847 val), IXGBE_NOT_IMPLEMENTED); 848 } 849 850 /** 851 * ixgbe_init_uta_tables - Initializes Unicast Table Arrays. 852 * @hw: pointer to hardware structure 853 * 854 * Initializes the Unicast Table Arrays to zero on device load. This 855 * is part of the Rx init addr execution path. 856 **/ 857 s32 ixgbe_init_uta_tables(struct ixgbe_hw *hw) 858 { 859 return ixgbe_call_func(hw, hw->mac.ops.init_uta_tables, (hw), 860 IXGBE_NOT_IMPLEMENTED); 861 } 862 863 /** 864 * ixgbe_read_i2c_byte - Reads 8 bit word over I2C at specified device address 865 * @hw: pointer to hardware structure 866 * @byte_offset: byte offset to read 867 * @data: value read 868 * 869 * Performs byte read operation to SFP module's EEPROM over I2C interface. 870 **/ 871 s32 ixgbe_read_i2c_byte(struct ixgbe_hw *hw, u8 byte_offset, u8 dev_addr, 872 u8 *data) 873 { 874 return ixgbe_call_func(hw, hw->phy.ops.read_i2c_byte, (hw, byte_offset, 875 dev_addr, data), IXGBE_NOT_IMPLEMENTED); 876 } 877 878 /** 879 * ixgbe_write_i2c_byte - Writes 8 bit word over I2C 880 * @hw: pointer to hardware structure 881 * @byte_offset: byte offset to write 882 * @data: value to write 883 * 884 * Performs byte write operation to SFP module's EEPROM over I2C interface 885 * at a specified device address. 886 **/ 887 s32 ixgbe_write_i2c_byte(struct ixgbe_hw *hw, u8 byte_offset, u8 dev_addr, 888 u8 data) 889 { 890 return ixgbe_call_func(hw, hw->phy.ops.write_i2c_byte, (hw, byte_offset, 891 dev_addr, data), IXGBE_NOT_IMPLEMENTED); 892 } 893 894 /** 895 * ixgbe_write_i2c_eeprom - Writes 8 bit EEPROM word over I2C interface 896 * @hw: pointer to hardware structure 897 * @byte_offset: EEPROM byte offset to write 898 * @eeprom_data: value to write 899 * 900 * Performs byte write operation to SFP module's EEPROM over I2C interface. 901 **/ 902 s32 ixgbe_write_i2c_eeprom(struct ixgbe_hw *hw, 903 u8 byte_offset, u8 eeprom_data) 904 { 905 return ixgbe_call_func(hw, hw->phy.ops.write_i2c_eeprom, 906 (hw, byte_offset, eeprom_data), 907 IXGBE_NOT_IMPLEMENTED); 908 } 909 910 /** 911 * ixgbe_read_i2c_eeprom - Reads 8 bit EEPROM word over I2C interface 912 * @hw: pointer to hardware structure 913 * @byte_offset: EEPROM byte offset to read 914 * @eeprom_data: value read 915 * 916 * Performs byte read operation to SFP module's EEPROM over I2C interface. 917 **/ 918 s32 ixgbe_read_i2c_eeprom(struct ixgbe_hw *hw, u8 byte_offset, u8 *eeprom_data) 919 { 920 return ixgbe_call_func(hw, hw->phy.ops.read_i2c_eeprom, 921 (hw, byte_offset, eeprom_data), 922 IXGBE_NOT_IMPLEMENTED); 923 } 924 925 /** 926 * ixgbe_get_supported_physical_layer - Returns physical layer type 927 * @hw: pointer to hardware structure 928 * 929 * Determines physical layer capabilities of the current configuration. 930 **/ 931 u32 ixgbe_get_supported_physical_layer(struct ixgbe_hw *hw) 932 { 933 return ixgbe_call_func(hw, hw->mac.ops.get_supported_physical_layer, 934 (hw), IXGBE_PHYSICAL_LAYER_UNKNOWN); 935 } 936 937 /** 938 * ixgbe_enable_rx_dma - Enables Rx DMA unit, dependant on device specifics 939 * @hw: pointer to hardware structure 940 * @regval: bitfield to write to the Rx DMA register 941 * 942 * Enables the Rx DMA unit of the device. 943 **/ 944 s32 ixgbe_enable_rx_dma(struct ixgbe_hw *hw, u32 regval) 945 { 946 return ixgbe_call_func(hw, hw->mac.ops.enable_rx_dma, 947 (hw, regval), IXGBE_NOT_IMPLEMENTED); 948 } 949 950 /** 951 * ixgbe_acquire_swfw_semaphore - Acquire SWFW semaphore 952 * @hw: pointer to hardware structure 953 * @mask: Mask to specify which semaphore to acquire 954 * 955 * Acquires the SWFW semaphore through SW_FW_SYNC register for the specified 956 * function (CSR, PHY0, PHY1, EEPROM, Flash) 957 **/ 958 s32 ixgbe_acquire_swfw_semaphore(struct ixgbe_hw *hw, u16 mask) 959 { 960 return ixgbe_call_func(hw, hw->mac.ops.acquire_swfw_sync, 961 (hw, mask), IXGBE_NOT_IMPLEMENTED); 962 } 963 964 /** 965 * ixgbe_release_swfw_semaphore - Release SWFW semaphore 966 * @hw: pointer to hardware structure 967 * @mask: Mask to specify which semaphore to release 968 * 969 * Releases the SWFW semaphore through SW_FW_SYNC register for the specified 970 * function (CSR, PHY0, PHY1, EEPROM, Flash) 971 **/ 972 void ixgbe_release_swfw_semaphore(struct ixgbe_hw *hw, u16 mask) 973 { 974 if (hw->mac.ops.release_swfw_sync) 975 hw->mac.ops.release_swfw_sync(hw, mask); 976 } 977 978