1 /****************************************************************************** 2 SPDX-License-Identifier: BSD-3-Clause 3 4 Copyright (c) 2001-2020, Intel Corporation 5 All rights reserved. 6 7 Redistribution and use in source and binary forms, with or without 8 modification, are permitted provided that the following conditions are met: 9 10 1. Redistributions of source code must retain the above copyright notice, 11 this list of conditions and the following disclaimer. 12 13 2. Redistributions in binary form must reproduce the above copyright 14 notice, this list of conditions and the following disclaimer in the 15 documentation and/or other materials provided with the distribution. 16 17 3. Neither the name of the Intel Corporation nor the names of its 18 contributors may be used to endorse or promote products derived from 19 this software without specific prior written permission. 20 21 THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 22 AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 23 IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 24 ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE 25 LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 26 CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 27 SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 28 INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 29 CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 30 ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 31 POSSIBILITY OF SUCH DAMAGE. 32 33 ******************************************************************************/ 34 35 #include "ixgbe_api.h" 36 #include "ixgbe_common.h" 37 38 #define IXGBE_EMPTY_PARAM 39 40 static const u32 ixgbe_mvals_base[IXGBE_MVALS_IDX_LIMIT] = { 41 IXGBE_MVALS_INIT(IXGBE_EMPTY_PARAM) 42 }; 43 44 static const u32 ixgbe_mvals_X540[IXGBE_MVALS_IDX_LIMIT] = { 45 IXGBE_MVALS_INIT(_X540) 46 }; 47 48 static const u32 ixgbe_mvals_X550[IXGBE_MVALS_IDX_LIMIT] = { 49 IXGBE_MVALS_INIT(_X550) 50 }; 51 52 static const u32 ixgbe_mvals_X550EM_x[IXGBE_MVALS_IDX_LIMIT] = { 53 IXGBE_MVALS_INIT(_X550EM_x) 54 }; 55 56 static const u32 ixgbe_mvals_X550EM_a[IXGBE_MVALS_IDX_LIMIT] = { 57 IXGBE_MVALS_INIT(_X550EM_a) 58 }; 59 60 /** 61 * ixgbe_dcb_get_rtrup2tc - read rtrup2tc reg 62 * @hw: pointer to hardware structure 63 * @map: pointer to u8 arr for returning map 64 * 65 * Read the rtrup2tc HW register and resolve its content into map 66 **/ 67 void ixgbe_dcb_get_rtrup2tc(struct ixgbe_hw *hw, u8 *map) 68 { 69 if (hw->mac.ops.get_rtrup2tc) 70 hw->mac.ops.get_rtrup2tc(hw, map); 71 } 72 73 /** 74 * ixgbe_init_shared_code - Initialize the shared code 75 * @hw: pointer to hardware structure 76 * 77 * This will assign function pointers and assign the MAC type and PHY code. 78 * Does not touch the hardware. This function must be called prior to any 79 * other function in the shared code. The ixgbe_hw structure should be 80 * memset to 0 prior to calling this function. The following fields in 81 * hw structure should be filled in prior to calling this function: 82 * hw_addr, back, device_id, vendor_id, subsystem_device_id, 83 * subsystem_vendor_id, and revision_id 84 **/ 85 s32 ixgbe_init_shared_code(struct ixgbe_hw *hw) 86 { 87 s32 status; 88 89 DEBUGFUNC("ixgbe_init_shared_code"); 90 91 /* 92 * Set the mac type 93 */ 94 ixgbe_set_mac_type(hw); 95 96 switch (hw->mac.type) { 97 case ixgbe_mac_82598EB: 98 status = ixgbe_init_ops_82598(hw); 99 break; 100 case ixgbe_mac_82599EB: 101 status = ixgbe_init_ops_82599(hw); 102 break; 103 case ixgbe_mac_X540: 104 status = ixgbe_init_ops_X540(hw); 105 break; 106 case ixgbe_mac_X550: 107 status = ixgbe_init_ops_X550(hw); 108 break; 109 case ixgbe_mac_X550EM_x: 110 status = ixgbe_init_ops_X550EM_x(hw); 111 break; 112 case ixgbe_mac_X550EM_a: 113 status = ixgbe_init_ops_X550EM_a(hw); 114 break; 115 case ixgbe_mac_E610: 116 status = ixgbe_init_ops_E610(hw); 117 break; 118 case ixgbe_mac_82599_vf: 119 case ixgbe_mac_X540_vf: 120 case ixgbe_mac_X550_vf: 121 case ixgbe_mac_X550EM_x_vf: 122 case ixgbe_mac_X550EM_a_vf: 123 case ixgbe_mac_E610_vf: 124 status = ixgbe_init_ops_vf(hw); 125 break; 126 default: 127 status = IXGBE_ERR_DEVICE_NOT_SUPPORTED; 128 break; 129 } 130 hw->mac.max_link_up_time = IXGBE_LINK_UP_TIME; 131 132 return status; 133 } 134 135 /** 136 * ixgbe_set_mac_type - Sets MAC type 137 * @hw: pointer to the HW structure 138 * 139 * This function sets the mac type of the adapter based on the 140 * vendor ID and device ID stored in the hw structure. 141 **/ 142 s32 ixgbe_set_mac_type(struct ixgbe_hw *hw) 143 { 144 s32 ret_val = IXGBE_SUCCESS; 145 146 DEBUGFUNC("ixgbe_set_mac_type\n"); 147 148 if (hw->vendor_id != IXGBE_INTEL_VENDOR_ID) { 149 ERROR_REPORT2(IXGBE_ERROR_UNSUPPORTED, 150 "Unsupported vendor id: %x", hw->vendor_id); 151 return IXGBE_ERR_DEVICE_NOT_SUPPORTED; 152 } 153 154 hw->mvals = ixgbe_mvals_base; 155 156 switch (hw->device_id) { 157 case IXGBE_DEV_ID_82598: 158 case IXGBE_DEV_ID_82598_BX: 159 case IXGBE_DEV_ID_82598AF_SINGLE_PORT: 160 case IXGBE_DEV_ID_82598AF_DUAL_PORT: 161 case IXGBE_DEV_ID_82598AT: 162 case IXGBE_DEV_ID_82598AT2: 163 case IXGBE_DEV_ID_82598EB_CX4: 164 case IXGBE_DEV_ID_82598_CX4_DUAL_PORT: 165 case IXGBE_DEV_ID_82598_DA_DUAL_PORT: 166 case IXGBE_DEV_ID_82598_SR_DUAL_PORT_EM: 167 case IXGBE_DEV_ID_82598EB_XF_LR: 168 case IXGBE_DEV_ID_82598EB_SFP_LOM: 169 hw->mac.type = ixgbe_mac_82598EB; 170 break; 171 case IXGBE_DEV_ID_82599_KX4: 172 case IXGBE_DEV_ID_82599_KX4_MEZZ: 173 case IXGBE_DEV_ID_82599_XAUI_LOM: 174 case IXGBE_DEV_ID_82599_COMBO_BACKPLANE: 175 case IXGBE_DEV_ID_82599_KR: 176 case IXGBE_DEV_ID_82599_SFP: 177 case IXGBE_DEV_ID_82599_BACKPLANE_FCOE: 178 case IXGBE_DEV_ID_82599_SFP_FCOE: 179 case IXGBE_DEV_ID_82599_SFP_EM: 180 case IXGBE_DEV_ID_82599_SFP_SF2: 181 case IXGBE_DEV_ID_82599_SFP_SF_QP: 182 case IXGBE_DEV_ID_82599_QSFP_SF_QP: 183 case IXGBE_DEV_ID_82599EN_SFP: 184 case IXGBE_DEV_ID_82599_CX4: 185 case IXGBE_DEV_ID_82599_BYPASS: 186 case IXGBE_DEV_ID_82599_T3_LOM: 187 hw->mac.type = ixgbe_mac_82599EB; 188 break; 189 case IXGBE_DEV_ID_82599_VF: 190 case IXGBE_DEV_ID_82599_VF_HV: 191 hw->mac.type = ixgbe_mac_82599_vf; 192 break; 193 case IXGBE_DEV_ID_X540_VF: 194 case IXGBE_DEV_ID_X540_VF_HV: 195 hw->mac.type = ixgbe_mac_X540_vf; 196 hw->mvals = ixgbe_mvals_X540; 197 break; 198 case IXGBE_DEV_ID_X540T: 199 case IXGBE_DEV_ID_X540T1: 200 case IXGBE_DEV_ID_X540_BYPASS: 201 hw->mac.type = ixgbe_mac_X540; 202 hw->mvals = ixgbe_mvals_X540; 203 break; 204 case IXGBE_DEV_ID_X550T: 205 case IXGBE_DEV_ID_X550T1: 206 hw->mac.type = ixgbe_mac_X550; 207 hw->mvals = ixgbe_mvals_X550; 208 break; 209 case IXGBE_DEV_ID_X550EM_X_KX4: 210 case IXGBE_DEV_ID_X550EM_X_KR: 211 case IXGBE_DEV_ID_X550EM_X_10G_T: 212 case IXGBE_DEV_ID_X550EM_X_1G_T: 213 case IXGBE_DEV_ID_X550EM_X_SFP: 214 case IXGBE_DEV_ID_X550EM_X_XFI: 215 hw->mac.type = ixgbe_mac_X550EM_x; 216 hw->mvals = ixgbe_mvals_X550EM_x; 217 break; 218 case IXGBE_DEV_ID_X550EM_A_KR: 219 case IXGBE_DEV_ID_X550EM_A_KR_L: 220 case IXGBE_DEV_ID_X550EM_A_SFP_N: 221 case IXGBE_DEV_ID_X550EM_A_SGMII: 222 case IXGBE_DEV_ID_X550EM_A_SGMII_L: 223 case IXGBE_DEV_ID_X550EM_A_1G_T: 224 case IXGBE_DEV_ID_X550EM_A_1G_T_L: 225 case IXGBE_DEV_ID_X550EM_A_10G_T: 226 case IXGBE_DEV_ID_X550EM_A_QSFP: 227 case IXGBE_DEV_ID_X550EM_A_QSFP_N: 228 case IXGBE_DEV_ID_X550EM_A_SFP: 229 hw->mac.type = ixgbe_mac_X550EM_a; 230 hw->mvals = ixgbe_mvals_X550EM_a; 231 break; 232 case IXGBE_DEV_ID_X550_VF: 233 case IXGBE_DEV_ID_X550_VF_HV: 234 hw->mac.type = ixgbe_mac_X550_vf; 235 hw->mvals = ixgbe_mvals_X550; 236 break; 237 case IXGBE_DEV_ID_X550EM_X_VF: 238 case IXGBE_DEV_ID_X550EM_X_VF_HV: 239 hw->mac.type = ixgbe_mac_X550EM_x_vf; 240 hw->mvals = ixgbe_mvals_X550EM_x; 241 break; 242 case IXGBE_DEV_ID_X550EM_A_VF: 243 case IXGBE_DEV_ID_X550EM_A_VF_HV: 244 hw->mac.type = ixgbe_mac_X550EM_a_vf; 245 hw->mvals = ixgbe_mvals_X550EM_a; 246 break; 247 case IXGBE_DEV_ID_E610_BACKPLANE: 248 case IXGBE_DEV_ID_E610_SFP: 249 case IXGBE_DEV_ID_E610_10G_T: 250 case IXGBE_DEV_ID_E610_2_5G_T: 251 case IXGBE_DEV_ID_E610_SGMII: 252 hw->mac.type = ixgbe_mac_E610; 253 hw->mvals = ixgbe_mvals_X550EM_a; 254 break; 255 case IXGBE_DEV_ID_E610_VF: 256 hw->mac.type = ixgbe_mac_E610_vf; 257 hw->mvals = ixgbe_mvals_X550EM_a; 258 break; 259 default: 260 ret_val = IXGBE_ERR_DEVICE_NOT_SUPPORTED; 261 ERROR_REPORT2(IXGBE_ERROR_UNSUPPORTED, 262 "Unsupported device id: %x", 263 hw->device_id); 264 break; 265 } 266 267 DEBUGOUT2("ixgbe_set_mac_type found mac: %d, returns: %d\n", 268 hw->mac.type, ret_val); 269 return ret_val; 270 } 271 272 /** 273 * ixgbe_init_hw - Initialize the hardware 274 * @hw: pointer to hardware structure 275 * 276 * Initialize the hardware by resetting and then starting the hardware 277 **/ 278 s32 ixgbe_init_hw(struct ixgbe_hw *hw) 279 { 280 return ixgbe_call_func(hw, hw->mac.ops.init_hw, (hw), 281 IXGBE_NOT_IMPLEMENTED); 282 } 283 284 /** 285 * ixgbe_reset_hw - Performs a hardware reset 286 * @hw: pointer to hardware structure 287 * 288 * Resets the hardware by resetting the transmit and receive units, masks and 289 * clears all interrupts, performs a PHY reset, and performs a MAC reset 290 **/ 291 s32 ixgbe_reset_hw(struct ixgbe_hw *hw) 292 { 293 return ixgbe_call_func(hw, hw->mac.ops.reset_hw, (hw), 294 IXGBE_NOT_IMPLEMENTED); 295 } 296 297 /** 298 * ixgbe_start_hw - Prepares hardware for Rx/Tx 299 * @hw: pointer to hardware structure 300 * 301 * Starts the hardware by filling the bus info structure and media type, 302 * clears all on chip counters, initializes receive address registers, 303 * multicast table, VLAN filter table, calls routine to setup link and 304 * flow control settings, and leaves transmit and receive units disabled 305 * and uninitialized. 306 **/ 307 s32 ixgbe_start_hw(struct ixgbe_hw *hw) 308 { 309 return ixgbe_call_func(hw, hw->mac.ops.start_hw, (hw), 310 IXGBE_NOT_IMPLEMENTED); 311 } 312 313 /** 314 * ixgbe_enable_relaxed_ordering - Enables tx relaxed ordering, 315 * which is disabled by default in ixgbe_start_hw(); 316 * 317 * @hw: pointer to hardware structure 318 * 319 * Enable relaxed ordering; 320 **/ 321 void ixgbe_enable_relaxed_ordering(struct ixgbe_hw *hw) 322 { 323 if (hw->mac.ops.enable_relaxed_ordering) 324 hw->mac.ops.enable_relaxed_ordering(hw); 325 } 326 327 /** 328 * ixgbe_clear_hw_cntrs - Clear hardware counters 329 * @hw: pointer to hardware structure 330 * 331 * Clears all hardware statistics counters by reading them from the hardware 332 * Statistics counters are clear on read. 333 **/ 334 s32 ixgbe_clear_hw_cntrs(struct ixgbe_hw *hw) 335 { 336 return ixgbe_call_func(hw, hw->mac.ops.clear_hw_cntrs, (hw), 337 IXGBE_NOT_IMPLEMENTED); 338 } 339 340 /** 341 * ixgbe_get_media_type - Get media type 342 * @hw: pointer to hardware structure 343 * 344 * Returns the media type (fiber, copper, backplane) 345 **/ 346 enum ixgbe_media_type ixgbe_get_media_type(struct ixgbe_hw *hw) 347 { 348 return ixgbe_call_func(hw, hw->mac.ops.get_media_type, (hw), 349 ixgbe_media_type_unknown); 350 } 351 352 /** 353 * ixgbe_get_mac_addr - Get MAC address 354 * @hw: pointer to hardware structure 355 * @mac_addr: Adapter MAC address 356 * 357 * Reads the adapter's MAC address from the first Receive Address Register 358 * (RAR0) A reset of the adapter must have been performed prior to calling 359 * this function in order for the MAC address to have been loaded from the 360 * EEPROM into RAR0 361 **/ 362 s32 ixgbe_get_mac_addr(struct ixgbe_hw *hw, u8 *mac_addr) 363 { 364 return ixgbe_call_func(hw, hw->mac.ops.get_mac_addr, 365 (hw, mac_addr), IXGBE_NOT_IMPLEMENTED); 366 } 367 368 /** 369 * ixgbe_get_san_mac_addr - Get SAN MAC address 370 * @hw: pointer to hardware structure 371 * @san_mac_addr: SAN MAC address 372 * 373 * Reads the SAN MAC address from the EEPROM, if it's available. This is 374 * per-port, so set_lan_id() must be called before reading the addresses. 375 **/ 376 s32 ixgbe_get_san_mac_addr(struct ixgbe_hw *hw, u8 *san_mac_addr) 377 { 378 return ixgbe_call_func(hw, hw->mac.ops.get_san_mac_addr, 379 (hw, san_mac_addr), IXGBE_NOT_IMPLEMENTED); 380 } 381 382 /** 383 * ixgbe_set_san_mac_addr - Write a SAN MAC address 384 * @hw: pointer to hardware structure 385 * @san_mac_addr: SAN MAC address 386 * 387 * Writes A SAN MAC address to the EEPROM. 388 **/ 389 s32 ixgbe_set_san_mac_addr(struct ixgbe_hw *hw, u8 *san_mac_addr) 390 { 391 return ixgbe_call_func(hw, hw->mac.ops.set_san_mac_addr, 392 (hw, san_mac_addr), IXGBE_NOT_IMPLEMENTED); 393 } 394 395 /** 396 * ixgbe_get_device_caps - Get additional device capabilities 397 * @hw: pointer to hardware structure 398 * @device_caps: the EEPROM word for device capabilities 399 * 400 * Reads the extra device capabilities from the EEPROM 401 **/ 402 s32 ixgbe_get_device_caps(struct ixgbe_hw *hw, u16 *device_caps) 403 { 404 return ixgbe_call_func(hw, hw->mac.ops.get_device_caps, 405 (hw, device_caps), IXGBE_NOT_IMPLEMENTED); 406 } 407 408 /** 409 * ixgbe_get_wwn_prefix - Get alternative WWNN/WWPN prefix from the EEPROM 410 * @hw: pointer to hardware structure 411 * @wwnn_prefix: the alternative WWNN prefix 412 * @wwpn_prefix: the alternative WWPN prefix 413 * 414 * This function will read the EEPROM from the alternative SAN MAC address 415 * block to check the support for the alternative WWNN/WWPN prefix support. 416 **/ 417 s32 ixgbe_get_wwn_prefix(struct ixgbe_hw *hw, u16 *wwnn_prefix, 418 u16 *wwpn_prefix) 419 { 420 return ixgbe_call_func(hw, hw->mac.ops.get_wwn_prefix, 421 (hw, wwnn_prefix, wwpn_prefix), 422 IXGBE_NOT_IMPLEMENTED); 423 } 424 425 /** 426 * ixgbe_get_fcoe_boot_status - Get FCOE boot status from EEPROM 427 * @hw: pointer to hardware structure 428 * @bs: the fcoe boot status 429 * 430 * This function will read the FCOE boot status from the iSCSI FCOE block 431 **/ 432 s32 ixgbe_get_fcoe_boot_status(struct ixgbe_hw *hw, u16 *bs) 433 { 434 return ixgbe_call_func(hw, hw->mac.ops.get_fcoe_boot_status, 435 (hw, bs), 436 IXGBE_NOT_IMPLEMENTED); 437 } 438 439 /** 440 * ixgbe_get_bus_info - Set PCI bus info 441 * @hw: pointer to hardware structure 442 * 443 * Sets the PCI bus info (speed, width, type) within the ixgbe_hw structure 444 **/ 445 s32 ixgbe_get_bus_info(struct ixgbe_hw *hw) 446 { 447 return ixgbe_call_func(hw, hw->mac.ops.get_bus_info, (hw), 448 IXGBE_NOT_IMPLEMENTED); 449 } 450 451 /** 452 * ixgbe_get_num_of_tx_queues - Get Tx queues 453 * @hw: pointer to hardware structure 454 * 455 * Returns the number of transmit queues for the given adapter. 456 **/ 457 u32 ixgbe_get_num_of_tx_queues(struct ixgbe_hw *hw) 458 { 459 return hw->mac.max_tx_queues; 460 } 461 462 /** 463 * ixgbe_get_num_of_rx_queues - Get Rx queues 464 * @hw: pointer to hardware structure 465 * 466 * Returns the number of receive queues for the given adapter. 467 **/ 468 u32 ixgbe_get_num_of_rx_queues(struct ixgbe_hw *hw) 469 { 470 return hw->mac.max_rx_queues; 471 } 472 473 /** 474 * ixgbe_stop_adapter - Disable Rx/Tx units 475 * @hw: pointer to hardware structure 476 * 477 * Sets the adapter_stopped flag within ixgbe_hw struct. Clears interrupts, 478 * disables transmit and receive units. The adapter_stopped flag is used by 479 * the shared code and drivers to determine if the adapter is in a stopped 480 * state and should not touch the hardware. 481 **/ 482 s32 ixgbe_stop_adapter(struct ixgbe_hw *hw) 483 { 484 return ixgbe_call_func(hw, hw->mac.ops.stop_adapter, (hw), 485 IXGBE_NOT_IMPLEMENTED); 486 } 487 488 /** 489 * ixgbe_read_pba_string - Reads part number string from EEPROM 490 * @hw: pointer to hardware structure 491 * @pba_num: stores the part number string from the EEPROM 492 * @pba_num_size: part number string buffer length 493 * 494 * Reads the part number string from the EEPROM. 495 **/ 496 s32 ixgbe_read_pba_string(struct ixgbe_hw *hw, u8 *pba_num, u32 pba_num_size) 497 { 498 return ixgbe_call_func(hw, hw->eeprom.ops.read_pba_string, 499 (hw, pba_num, pba_num_size), 500 IXGBE_NOT_IMPLEMENTED); 501 } 502 503 /** 504 * ixgbe_read_pba_num - Reads part number from EEPROM 505 * @hw: pointer to hardware structure 506 * @pba_num: stores the part number from the EEPROM 507 * 508 * Reads the part number from the EEPROM. 509 **/ 510 s32 ixgbe_read_pba_num(struct ixgbe_hw *hw, u32 *pba_num) 511 { 512 return ixgbe_read_pba_num_generic(hw, pba_num); 513 } 514 515 /** 516 * ixgbe_identify_phy - Get PHY type 517 * @hw: pointer to hardware structure 518 * 519 * Determines the physical layer module found on the current adapter. 520 **/ 521 s32 ixgbe_identify_phy(struct ixgbe_hw *hw) 522 { 523 s32 status = IXGBE_SUCCESS; 524 525 if (hw->phy.type == ixgbe_phy_unknown) { 526 status = ixgbe_call_func(hw, hw->phy.ops.identify, (hw), 527 IXGBE_NOT_IMPLEMENTED); 528 } 529 530 return status; 531 } 532 533 /** 534 * ixgbe_reset_phy - Perform a PHY reset 535 * @hw: pointer to hardware structure 536 **/ 537 s32 ixgbe_reset_phy(struct ixgbe_hw *hw) 538 { 539 s32 status = IXGBE_SUCCESS; 540 541 if (hw->phy.type == ixgbe_phy_unknown) { 542 if (ixgbe_identify_phy(hw) != IXGBE_SUCCESS) 543 status = IXGBE_ERR_PHY; 544 } 545 546 if (status == IXGBE_SUCCESS) { 547 status = ixgbe_call_func(hw, hw->phy.ops.reset, (hw), 548 IXGBE_NOT_IMPLEMENTED); 549 } 550 return status; 551 } 552 553 /** 554 * ixgbe_get_phy_firmware_version - 555 * @hw: pointer to hardware structure 556 * @firmware_version: pointer to firmware version 557 **/ 558 s32 ixgbe_get_phy_firmware_version(struct ixgbe_hw *hw, u16 *firmware_version) 559 { 560 s32 status = IXGBE_SUCCESS; 561 562 status = ixgbe_call_func(hw, hw->phy.ops.get_firmware_version, 563 (hw, firmware_version), 564 IXGBE_NOT_IMPLEMENTED); 565 return status; 566 } 567 568 /** 569 * ixgbe_read_phy_reg - Read PHY register 570 * @hw: pointer to hardware structure 571 * @reg_addr: 32 bit address of PHY register to read 572 * @device_type: type of device you want to communicate with 573 * @phy_data: Pointer to read data from PHY register 574 * 575 * Reads a value from a specified PHY register 576 **/ 577 s32 ixgbe_read_phy_reg(struct ixgbe_hw *hw, u32 reg_addr, u32 device_type, 578 u16 *phy_data) 579 { 580 if (hw->phy.id == 0) 581 ixgbe_identify_phy(hw); 582 583 return ixgbe_call_func(hw, hw->phy.ops.read_reg, (hw, reg_addr, 584 device_type, phy_data), IXGBE_NOT_IMPLEMENTED); 585 } 586 587 /** 588 * ixgbe_write_phy_reg - Write PHY register 589 * @hw: pointer to hardware structure 590 * @reg_addr: 32 bit PHY register to write 591 * @device_type: type of device you want to communicate with 592 * @phy_data: Data to write to the PHY register 593 * 594 * Writes a value to specified PHY register 595 **/ 596 s32 ixgbe_write_phy_reg(struct ixgbe_hw *hw, u32 reg_addr, u32 device_type, 597 u16 phy_data) 598 { 599 if (hw->phy.id == 0) 600 ixgbe_identify_phy(hw); 601 602 return ixgbe_call_func(hw, hw->phy.ops.write_reg, (hw, reg_addr, 603 device_type, phy_data), IXGBE_NOT_IMPLEMENTED); 604 } 605 606 /** 607 * ixgbe_setup_phy_link - Restart PHY autoneg 608 * @hw: pointer to hardware structure 609 * 610 * Restart autonegotiation and PHY and waits for completion. 611 **/ 612 s32 ixgbe_setup_phy_link(struct ixgbe_hw *hw) 613 { 614 return ixgbe_call_func(hw, hw->phy.ops.setup_link, (hw), 615 IXGBE_NOT_IMPLEMENTED); 616 } 617 618 /** 619 * ixgbe_setup_internal_phy - Configure integrated PHY 620 * @hw: pointer to hardware structure 621 * 622 * Reconfigure the integrated PHY in order to enable talk to the external PHY. 623 * Returns success if not implemented, since nothing needs to be done in this 624 * case. 625 */ 626 s32 ixgbe_setup_internal_phy(struct ixgbe_hw *hw) 627 { 628 return ixgbe_call_func(hw, hw->phy.ops.setup_internal_link, (hw), 629 IXGBE_SUCCESS); 630 } 631 632 /** 633 * ixgbe_check_phy_link - Determine link and speed status 634 * @hw: pointer to hardware structure 635 * @speed: link speed 636 * @link_up: true when link is up 637 * 638 * Reads a PHY register to determine if link is up and the current speed for 639 * the PHY. 640 **/ 641 s32 ixgbe_check_phy_link(struct ixgbe_hw *hw, ixgbe_link_speed *speed, 642 bool *link_up) 643 { 644 return ixgbe_call_func(hw, hw->phy.ops.check_link, (hw, speed, 645 link_up), IXGBE_NOT_IMPLEMENTED); 646 } 647 648 /** 649 * ixgbe_setup_phy_link_speed - Set auto advertise 650 * @hw: pointer to hardware structure 651 * @speed: new link speed 652 * @autoneg_wait_to_complete: true when waiting for completion is needed 653 * 654 * Sets the auto advertised capabilities 655 **/ 656 s32 ixgbe_setup_phy_link_speed(struct ixgbe_hw *hw, ixgbe_link_speed speed, 657 bool autoneg_wait_to_complete) 658 { 659 return ixgbe_call_func(hw, hw->phy.ops.setup_link_speed, (hw, speed, 660 autoneg_wait_to_complete), 661 IXGBE_NOT_IMPLEMENTED); 662 } 663 664 /** 665 * ixgbe_set_phy_power - Control the phy power state 666 * @hw: pointer to hardware structure 667 * @on: true for on, false for off 668 */ 669 s32 ixgbe_set_phy_power(struct ixgbe_hw *hw, bool on) 670 { 671 return ixgbe_call_func(hw, hw->phy.ops.set_phy_power, (hw, on), 672 IXGBE_NOT_IMPLEMENTED); 673 } 674 675 /** 676 * ixgbe_check_link - Get link and speed status 677 * @hw: pointer to hardware structure 678 * @speed: pointer to link speed 679 * @link_up: true when link is up 680 * @link_up_wait_to_complete: bool used to wait for link up or not 681 * 682 * Reads the links register to determine if link is up and the current speed 683 **/ 684 s32 ixgbe_check_link(struct ixgbe_hw *hw, ixgbe_link_speed *speed, 685 bool *link_up, bool link_up_wait_to_complete) 686 { 687 return ixgbe_call_func(hw, hw->mac.ops.check_link, (hw, speed, 688 link_up, link_up_wait_to_complete), 689 IXGBE_NOT_IMPLEMENTED); 690 } 691 692 /** 693 * ixgbe_disable_tx_laser - Disable Tx laser 694 * @hw: pointer to hardware structure 695 * 696 * If the driver needs to disable the laser on SFI optics. 697 **/ 698 void ixgbe_disable_tx_laser(struct ixgbe_hw *hw) 699 { 700 if (hw->mac.ops.disable_tx_laser) 701 hw->mac.ops.disable_tx_laser(hw); 702 } 703 704 /** 705 * ixgbe_enable_tx_laser - Enable Tx laser 706 * @hw: pointer to hardware structure 707 * 708 * If the driver needs to enable the laser on SFI optics. 709 **/ 710 void ixgbe_enable_tx_laser(struct ixgbe_hw *hw) 711 { 712 if (hw->mac.ops.enable_tx_laser) 713 hw->mac.ops.enable_tx_laser(hw); 714 } 715 716 /** 717 * ixgbe_flap_tx_laser - flap Tx laser to start autotry process 718 * @hw: pointer to hardware structure 719 * 720 * When the driver changes the link speeds that it can support then 721 * flap the tx laser to alert the link partner to start autotry 722 * process on its end. 723 **/ 724 void ixgbe_flap_tx_laser(struct ixgbe_hw *hw) 725 { 726 if (hw->mac.ops.flap_tx_laser) 727 hw->mac.ops.flap_tx_laser(hw); 728 } 729 730 /** 731 * ixgbe_setup_link - Set link speed 732 * @hw: pointer to hardware structure 733 * @speed: new link speed 734 * @autoneg_wait_to_complete: true when waiting for completion is needed 735 * 736 * Configures link settings. Restarts the link. 737 * Performs autonegotiation if needed. 738 **/ 739 s32 ixgbe_setup_link(struct ixgbe_hw *hw, ixgbe_link_speed speed, 740 bool autoneg_wait_to_complete) 741 { 742 return ixgbe_call_func(hw, hw->mac.ops.setup_link, (hw, speed, 743 autoneg_wait_to_complete), 744 IXGBE_NOT_IMPLEMENTED); 745 } 746 747 /** 748 * ixgbe_setup_mac_link - Set link speed 749 * @hw: pointer to hardware structure 750 * @speed: new link speed 751 * @autoneg_wait_to_complete: true when waiting for completion is needed 752 * 753 * Configures link settings. Restarts the link. 754 * Performs autonegotiation if needed. 755 **/ 756 s32 ixgbe_setup_mac_link(struct ixgbe_hw *hw, ixgbe_link_speed speed, 757 bool autoneg_wait_to_complete) 758 { 759 return ixgbe_call_func(hw, hw->mac.ops.setup_mac_link, (hw, speed, 760 autoneg_wait_to_complete), 761 IXGBE_NOT_IMPLEMENTED); 762 } 763 764 /** 765 * ixgbe_get_link_capabilities - Returns link capabilities 766 * @hw: pointer to hardware structure 767 * @speed: link speed capabilities 768 * @autoneg: true when autoneg or autotry is enabled 769 * 770 * Determines the link capabilities of the current configuration. 771 **/ 772 s32 ixgbe_get_link_capabilities(struct ixgbe_hw *hw, ixgbe_link_speed *speed, 773 bool *autoneg) 774 { 775 return ixgbe_call_func(hw, hw->mac.ops.get_link_capabilities, (hw, 776 speed, autoneg), IXGBE_NOT_IMPLEMENTED); 777 } 778 779 /** 780 * ixgbe_led_on - Turn on LEDs 781 * @hw: pointer to hardware structure 782 * @index: led number to turn on 783 * 784 * Turns on the software controllable LEDs. 785 **/ 786 s32 ixgbe_led_on(struct ixgbe_hw *hw, u32 index) 787 { 788 return ixgbe_call_func(hw, hw->mac.ops.led_on, (hw, index), 789 IXGBE_NOT_IMPLEMENTED); 790 } 791 792 /** 793 * ixgbe_led_off - Turn off LEDs 794 * @hw: pointer to hardware structure 795 * @index: led number to turn off 796 * 797 * Turns off the software controllable LEDs. 798 **/ 799 s32 ixgbe_led_off(struct ixgbe_hw *hw, u32 index) 800 { 801 return ixgbe_call_func(hw, hw->mac.ops.led_off, (hw, index), 802 IXGBE_NOT_IMPLEMENTED); 803 } 804 805 /** 806 * ixgbe_blink_led_start - Blink LEDs 807 * @hw: pointer to hardware structure 808 * @index: led number to blink 809 * 810 * Blink LED based on index. 811 **/ 812 s32 ixgbe_blink_led_start(struct ixgbe_hw *hw, u32 index) 813 { 814 return ixgbe_call_func(hw, hw->mac.ops.blink_led_start, (hw, index), 815 IXGBE_NOT_IMPLEMENTED); 816 } 817 818 /** 819 * ixgbe_blink_led_stop - Stop blinking LEDs 820 * @hw: pointer to hardware structure 821 * @index: led number to stop 822 * 823 * Stop blinking LED based on index. 824 **/ 825 s32 ixgbe_blink_led_stop(struct ixgbe_hw *hw, u32 index) 826 { 827 return ixgbe_call_func(hw, hw->mac.ops.blink_led_stop, (hw, index), 828 IXGBE_NOT_IMPLEMENTED); 829 } 830 831 /** 832 * ixgbe_init_eeprom_params - Initialize EEPROM parameters 833 * @hw: pointer to hardware structure 834 * 835 * Initializes the EEPROM parameters ixgbe_eeprom_info within the 836 * ixgbe_hw struct in order to set up EEPROM access. 837 **/ 838 s32 ixgbe_init_eeprom_params(struct ixgbe_hw *hw) 839 { 840 return ixgbe_call_func(hw, hw->eeprom.ops.init_params, (hw), 841 IXGBE_NOT_IMPLEMENTED); 842 } 843 844 845 /** 846 * ixgbe_write_eeprom - Write word to EEPROM 847 * @hw: pointer to hardware structure 848 * @offset: offset within the EEPROM to be written to 849 * @data: 16 bit word to be written to the EEPROM 850 * 851 * Writes 16 bit value to EEPROM. If ixgbe_eeprom_update_checksum is not 852 * called after this function, the EEPROM will most likely contain an 853 * invalid checksum. 854 **/ 855 s32 ixgbe_write_eeprom(struct ixgbe_hw *hw, u16 offset, u16 data) 856 { 857 return ixgbe_call_func(hw, hw->eeprom.ops.write, (hw, offset, data), 858 IXGBE_NOT_IMPLEMENTED); 859 } 860 861 /** 862 * ixgbe_write_eeprom_buffer - Write word(s) to EEPROM 863 * @hw: pointer to hardware structure 864 * @offset: offset within the EEPROM to be written to 865 * @data: 16 bit word(s) to be written to the EEPROM 866 * @words: number of words 867 * 868 * Writes 16 bit word(s) to EEPROM. If ixgbe_eeprom_update_checksum is not 869 * called after this function, the EEPROM will most likely contain an 870 * invalid checksum. 871 **/ 872 s32 ixgbe_write_eeprom_buffer(struct ixgbe_hw *hw, u16 offset, u16 words, 873 u16 *data) 874 { 875 return ixgbe_call_func(hw, hw->eeprom.ops.write_buffer, 876 (hw, offset, words, data), 877 IXGBE_NOT_IMPLEMENTED); 878 } 879 880 /** 881 * ixgbe_read_eeprom - Read word from EEPROM 882 * @hw: pointer to hardware structure 883 * @offset: offset within the EEPROM to be read 884 * @data: read 16 bit value from EEPROM 885 * 886 * Reads 16 bit value from EEPROM 887 **/ 888 s32 ixgbe_read_eeprom(struct ixgbe_hw *hw, u16 offset, u16 *data) 889 { 890 return ixgbe_call_func(hw, hw->eeprom.ops.read, (hw, offset, data), 891 IXGBE_NOT_IMPLEMENTED); 892 } 893 894 /** 895 * ixgbe_read_eeprom_buffer - Read word(s) from EEPROM 896 * @hw: pointer to hardware structure 897 * @offset: offset within the EEPROM to be read 898 * @data: read 16 bit word(s) from EEPROM 899 * @words: number of words 900 * 901 * Reads 16 bit word(s) from EEPROM 902 **/ 903 s32 ixgbe_read_eeprom_buffer(struct ixgbe_hw *hw, u16 offset, 904 u16 words, u16 *data) 905 { 906 return ixgbe_call_func(hw, hw->eeprom.ops.read_buffer, 907 (hw, offset, words, data), 908 IXGBE_NOT_IMPLEMENTED); 909 } 910 911 /** 912 * ixgbe_validate_eeprom_checksum - Validate EEPROM checksum 913 * @hw: pointer to hardware structure 914 * @checksum_val: calculated checksum 915 * 916 * Performs checksum calculation and validates the EEPROM checksum 917 **/ 918 s32 ixgbe_validate_eeprom_checksum(struct ixgbe_hw *hw, u16 *checksum_val) 919 { 920 return ixgbe_call_func(hw, hw->eeprom.ops.validate_checksum, 921 (hw, checksum_val), IXGBE_NOT_IMPLEMENTED); 922 } 923 924 /** 925 * ixgbe_update_eeprom_checksum - Updates the EEPROM checksum 926 * @hw: pointer to hardware structure 927 **/ 928 s32 ixgbe_update_eeprom_checksum(struct ixgbe_hw *hw) 929 { 930 return ixgbe_call_func(hw, hw->eeprom.ops.update_checksum, (hw), 931 IXGBE_NOT_IMPLEMENTED); 932 } 933 934 /** 935 * ixgbe_insert_mac_addr - Find a RAR for this mac address 936 * @hw: pointer to hardware structure 937 * @addr: Address to put into receive address register 938 * @vmdq: VMDq pool to assign 939 * 940 * Puts an ethernet address into a receive address register, or 941 * finds the rar that it is already in; adds to the pool list 942 **/ 943 s32 ixgbe_insert_mac_addr(struct ixgbe_hw *hw, u8 *addr, u32 vmdq) 944 { 945 return ixgbe_call_func(hw, hw->mac.ops.insert_mac_addr, 946 (hw, addr, vmdq), 947 IXGBE_NOT_IMPLEMENTED); 948 } 949 950 /** 951 * ixgbe_set_rar - Set Rx address register 952 * @hw: pointer to hardware structure 953 * @index: Receive address register to write 954 * @addr: Address to put into receive address register 955 * @vmdq: VMDq "set" 956 * @enable_addr: set flag that address is active 957 * 958 * Puts an ethernet address into a receive address register. 959 **/ 960 s32 ixgbe_set_rar(struct ixgbe_hw *hw, u32 index, u8 *addr, u32 vmdq, 961 u32 enable_addr) 962 { 963 return ixgbe_call_func(hw, hw->mac.ops.set_rar, (hw, index, addr, vmdq, 964 enable_addr), IXGBE_NOT_IMPLEMENTED); 965 } 966 967 /** 968 * ixgbe_clear_rar - Clear Rx address register 969 * @hw: pointer to hardware structure 970 * @index: Receive address register to write 971 * 972 * Puts an ethernet address into a receive address register. 973 **/ 974 s32 ixgbe_clear_rar(struct ixgbe_hw *hw, u32 index) 975 { 976 return ixgbe_call_func(hw, hw->mac.ops.clear_rar, (hw, index), 977 IXGBE_NOT_IMPLEMENTED); 978 } 979 980 /** 981 * ixgbe_set_vmdq - Associate a VMDq index with a receive address 982 * @hw: pointer to hardware structure 983 * @rar: receive address register index to associate with VMDq index 984 * @vmdq: VMDq set or pool index 985 **/ 986 s32 ixgbe_set_vmdq(struct ixgbe_hw *hw, u32 rar, u32 vmdq) 987 { 988 return ixgbe_call_func(hw, hw->mac.ops.set_vmdq, (hw, rar, vmdq), 989 IXGBE_NOT_IMPLEMENTED); 990 991 } 992 993 /** 994 * ixgbe_set_vmdq_san_mac - Associate VMDq index 127 with a receive address 995 * @hw: pointer to hardware structure 996 * @vmdq: VMDq default pool index 997 **/ 998 s32 ixgbe_set_vmdq_san_mac(struct ixgbe_hw *hw, u32 vmdq) 999 { 1000 return ixgbe_call_func(hw, hw->mac.ops.set_vmdq_san_mac, 1001 (hw, vmdq), IXGBE_NOT_IMPLEMENTED); 1002 } 1003 1004 /** 1005 * ixgbe_clear_vmdq - Disassociate a VMDq index from a receive address 1006 * @hw: pointer to hardware structure 1007 * @rar: receive address register index to disassociate with VMDq index 1008 * @vmdq: VMDq set or pool index 1009 **/ 1010 s32 ixgbe_clear_vmdq(struct ixgbe_hw *hw, u32 rar, u32 vmdq) 1011 { 1012 return ixgbe_call_func(hw, hw->mac.ops.clear_vmdq, (hw, rar, vmdq), 1013 IXGBE_NOT_IMPLEMENTED); 1014 } 1015 1016 /** 1017 * ixgbe_init_rx_addrs - Initializes receive address filters. 1018 * @hw: pointer to hardware structure 1019 * 1020 * Places the MAC address in receive address register 0 and clears the rest 1021 * of the receive address registers. Clears the multicast table. Assumes 1022 * the receiver is in reset when the routine is called. 1023 **/ 1024 s32 ixgbe_init_rx_addrs(struct ixgbe_hw *hw) 1025 { 1026 return ixgbe_call_func(hw, hw->mac.ops.init_rx_addrs, (hw), 1027 IXGBE_NOT_IMPLEMENTED); 1028 } 1029 1030 /** 1031 * ixgbe_get_num_rx_addrs - Returns the number of RAR entries. 1032 * @hw: pointer to hardware structure 1033 **/ 1034 u32 ixgbe_get_num_rx_addrs(struct ixgbe_hw *hw) 1035 { 1036 return hw->mac.num_rar_entries; 1037 } 1038 1039 /** 1040 * ixgbe_update_uc_addr_list - Updates the MAC's list of secondary addresses 1041 * @hw: pointer to hardware structure 1042 * @addr_list: the list of new multicast addresses 1043 * @addr_count: number of addresses 1044 * @func: iterator function to walk the multicast address list 1045 * 1046 * The given list replaces any existing list. Clears the secondary addrs from 1047 * receive address registers. Uses unused receive address registers for the 1048 * first secondary addresses, and falls back to promiscuous mode as needed. 1049 **/ 1050 s32 ixgbe_update_uc_addr_list(struct ixgbe_hw *hw, u8 *addr_list, 1051 u32 addr_count, ixgbe_mc_addr_itr func) 1052 { 1053 return ixgbe_call_func(hw, hw->mac.ops.update_uc_addr_list, (hw, 1054 addr_list, addr_count, func), 1055 IXGBE_NOT_IMPLEMENTED); 1056 } 1057 1058 /** 1059 * ixgbe_update_mc_addr_list - Updates the MAC's list of multicast addresses 1060 * @hw: pointer to hardware structure 1061 * @mc_addr_list: the list of new multicast addresses 1062 * @mc_addr_count: number of addresses 1063 * @func: iterator function to walk the multicast address list 1064 * @clear: flag, when set clears the table beforehand 1065 * 1066 * The given list replaces any existing list. Clears the MC addrs from receive 1067 * address registers and the multicast table. Uses unused receive address 1068 * registers for the first multicast addresses, and hashes the rest into the 1069 * multicast table. 1070 **/ 1071 s32 ixgbe_update_mc_addr_list(struct ixgbe_hw *hw, u8 *mc_addr_list, 1072 u32 mc_addr_count, ixgbe_mc_addr_itr func, 1073 bool clear) 1074 { 1075 return ixgbe_call_func(hw, hw->mac.ops.update_mc_addr_list, (hw, 1076 mc_addr_list, mc_addr_count, func, clear), 1077 IXGBE_NOT_IMPLEMENTED); 1078 } 1079 1080 /** 1081 * ixgbe_enable_mc - Enable multicast address in RAR 1082 * @hw: pointer to hardware structure 1083 * 1084 * Enables multicast address in RAR and the use of the multicast hash table. 1085 **/ 1086 s32 ixgbe_enable_mc(struct ixgbe_hw *hw) 1087 { 1088 return ixgbe_call_func(hw, hw->mac.ops.enable_mc, (hw), 1089 IXGBE_NOT_IMPLEMENTED); 1090 } 1091 1092 /** 1093 * ixgbe_disable_mc - Disable multicast address in RAR 1094 * @hw: pointer to hardware structure 1095 * 1096 * Disables multicast address in RAR and the use of the multicast hash table. 1097 **/ 1098 s32 ixgbe_disable_mc(struct ixgbe_hw *hw) 1099 { 1100 return ixgbe_call_func(hw, hw->mac.ops.disable_mc, (hw), 1101 IXGBE_NOT_IMPLEMENTED); 1102 } 1103 1104 /** 1105 * ixgbe_clear_vfta - Clear VLAN filter table 1106 * @hw: pointer to hardware structure 1107 * 1108 * Clears the VLAN filter table, and the VMDq index associated with the filter 1109 **/ 1110 s32 ixgbe_clear_vfta(struct ixgbe_hw *hw) 1111 { 1112 return ixgbe_call_func(hw, hw->mac.ops.clear_vfta, (hw), 1113 IXGBE_NOT_IMPLEMENTED); 1114 } 1115 1116 /** 1117 * ixgbe_set_vfta - Set VLAN filter table 1118 * @hw: pointer to hardware structure 1119 * @vlan: VLAN id to write to VLAN filter 1120 * @vind: VMDq output index that maps queue to VLAN id in VLVFB 1121 * @vlan_on: boolean flag to turn on/off VLAN 1122 * @vlvf_bypass: boolean flag indicating updating the default pool is okay 1123 * 1124 * Turn on/off specified VLAN in the VLAN filter table. 1125 **/ 1126 s32 ixgbe_set_vfta(struct ixgbe_hw *hw, u32 vlan, u32 vind, bool vlan_on, 1127 bool vlvf_bypass) 1128 { 1129 return ixgbe_call_func(hw, hw->mac.ops.set_vfta, (hw, vlan, vind, 1130 vlan_on, vlvf_bypass), IXGBE_NOT_IMPLEMENTED); 1131 } 1132 1133 /** 1134 * ixgbe_set_vlvf - Set VLAN Pool Filter 1135 * @hw: pointer to hardware structure 1136 * @vlan: VLAN id to write to VLAN filter 1137 * @vind: VMDq output index that maps queue to VLAN id in VLVFB 1138 * @vlan_on: boolean flag to turn on/off VLAN in VLVF 1139 * @vfta_delta: pointer to the difference between the current value of VFTA 1140 * and the desired value 1141 * @vfta: the desired value of the VFTA 1142 * @vlvf_bypass: boolean flag indicating updating the default pool is okay 1143 * 1144 * Turn on/off specified bit in VLVF table. 1145 **/ 1146 s32 ixgbe_set_vlvf(struct ixgbe_hw *hw, u32 vlan, u32 vind, bool vlan_on, 1147 u32 *vfta_delta, u32 vfta, bool vlvf_bypass) 1148 { 1149 return ixgbe_call_func(hw, hw->mac.ops.set_vlvf, (hw, vlan, vind, 1150 vlan_on, vfta_delta, vfta, vlvf_bypass), 1151 IXGBE_NOT_IMPLEMENTED); 1152 } 1153 1154 /** 1155 * ixgbe_toggle_txdctl - Toggle VF's queues 1156 * @hw: pointer to hardware structure 1157 * @vf_number: VF number 1158 * 1159 * Enable and disable each queue in VF. 1160 */ 1161 s32 ixgbe_toggle_txdctl(struct ixgbe_hw *hw, u32 vf_number) 1162 { 1163 return ixgbe_call_func(hw, hw->mac.ops.toggle_txdctl, (hw, 1164 vf_number), IXGBE_NOT_IMPLEMENTED); 1165 } 1166 1167 /** 1168 * ixgbe_fc_enable - Enable flow control 1169 * @hw: pointer to hardware structure 1170 * 1171 * Configures the flow control settings based on SW configuration. 1172 **/ 1173 s32 ixgbe_fc_enable(struct ixgbe_hw *hw) 1174 { 1175 return ixgbe_call_func(hw, hw->mac.ops.fc_enable, (hw), 1176 IXGBE_NOT_IMPLEMENTED); 1177 } 1178 1179 /** 1180 * ixgbe_setup_fc - Set up flow control 1181 * @hw: pointer to hardware structure 1182 * 1183 * Called at init time to set up flow control. 1184 **/ 1185 s32 ixgbe_setup_fc(struct ixgbe_hw *hw) 1186 { 1187 return ixgbe_call_func(hw, hw->mac.ops.setup_fc, (hw), 1188 IXGBE_NOT_IMPLEMENTED); 1189 } 1190 1191 /** 1192 * ixgbe_set_fw_drv_ver - Try to send the driver version number FW 1193 * @hw: pointer to hardware structure 1194 * @maj: driver major number to be sent to firmware 1195 * @min: driver minor number to be sent to firmware 1196 * @build: driver build number to be sent to firmware 1197 * @ver: driver version number to be sent to firmware 1198 * @len: length of driver_ver string 1199 * @driver_ver: driver string 1200 **/ 1201 s32 ixgbe_set_fw_drv_ver(struct ixgbe_hw *hw, u8 maj, u8 min, u8 build, 1202 u8 ver, u16 len, char *driver_ver) 1203 { 1204 return ixgbe_call_func(hw, hw->mac.ops.set_fw_drv_ver, (hw, maj, min, 1205 build, ver, len, driver_ver), 1206 IXGBE_NOT_IMPLEMENTED); 1207 } 1208 1209 1210 /** 1211 * ixgbe_get_thermal_sensor_data - Gathers thermal sensor data 1212 * @hw: pointer to hardware structure 1213 * 1214 * Updates the temperatures in mac.thermal_sensor_data 1215 **/ 1216 s32 ixgbe_get_thermal_sensor_data(struct ixgbe_hw *hw) 1217 { 1218 return ixgbe_call_func(hw, hw->mac.ops.get_thermal_sensor_data, (hw), 1219 IXGBE_NOT_IMPLEMENTED); 1220 } 1221 1222 /** 1223 * ixgbe_init_thermal_sensor_thresh - Inits thermal sensor thresholds 1224 * @hw: pointer to hardware structure 1225 * 1226 * Inits the thermal sensor thresholds according to the NVM map 1227 **/ 1228 s32 ixgbe_init_thermal_sensor_thresh(struct ixgbe_hw *hw) 1229 { 1230 return ixgbe_call_func(hw, hw->mac.ops.init_thermal_sensor_thresh, (hw), 1231 IXGBE_NOT_IMPLEMENTED); 1232 } 1233 1234 /** 1235 * ixgbe_dmac_config - Configure DMA Coalescing registers. 1236 * @hw: pointer to hardware structure 1237 * 1238 * Configure DMA coalescing. If enabling dmac, dmac is activated. 1239 * When disabling dmac, dmac enable dmac bit is cleared. 1240 **/ 1241 s32 ixgbe_dmac_config(struct ixgbe_hw *hw) 1242 { 1243 return ixgbe_call_func(hw, hw->mac.ops.dmac_config, (hw), 1244 IXGBE_NOT_IMPLEMENTED); 1245 } 1246 1247 /** 1248 * ixgbe_dmac_update_tcs - Configure DMA Coalescing registers. 1249 * @hw: pointer to hardware structure 1250 * 1251 * Disables dmac, updates per TC settings, and then enable dmac. 1252 **/ 1253 s32 ixgbe_dmac_update_tcs(struct ixgbe_hw *hw) 1254 { 1255 return ixgbe_call_func(hw, hw->mac.ops.dmac_update_tcs, (hw), 1256 IXGBE_NOT_IMPLEMENTED); 1257 } 1258 1259 /** 1260 * ixgbe_dmac_config_tcs - Configure DMA Coalescing registers. 1261 * @hw: pointer to hardware structure 1262 * 1263 * Configure DMA coalescing threshold per TC and set high priority bit for 1264 * FCOE TC. The dmac enable bit must be cleared before configuring. 1265 **/ 1266 s32 ixgbe_dmac_config_tcs(struct ixgbe_hw *hw) 1267 { 1268 return ixgbe_call_func(hw, hw->mac.ops.dmac_config_tcs, (hw), 1269 IXGBE_NOT_IMPLEMENTED); 1270 } 1271 1272 /** 1273 * ixgbe_setup_eee - Enable/disable EEE support 1274 * @hw: pointer to the HW structure 1275 * @enable_eee: boolean flag to enable EEE 1276 * 1277 * Enable/disable EEE based on enable_ee flag. 1278 * Auto-negotiation must be started after BASE-T EEE bits in PHY register 7.3C 1279 * are modified. 1280 * 1281 **/ 1282 s32 ixgbe_setup_eee(struct ixgbe_hw *hw, bool enable_eee) 1283 { 1284 return ixgbe_call_func(hw, hw->mac.ops.setup_eee, (hw, enable_eee), 1285 IXGBE_NOT_IMPLEMENTED); 1286 } 1287 1288 /** 1289 * ixgbe_set_source_address_pruning - Enable/Disable source address pruning 1290 * @hw: pointer to hardware structure 1291 * @enable: enable or disable source address pruning 1292 * @pool: Rx pool - Rx pool to toggle source address pruning 1293 **/ 1294 void ixgbe_set_source_address_pruning(struct ixgbe_hw *hw, bool enable, 1295 unsigned int pool) 1296 { 1297 if (hw->mac.ops.set_source_address_pruning) 1298 hw->mac.ops.set_source_address_pruning(hw, enable, pool); 1299 } 1300 1301 /** 1302 * ixgbe_set_ethertype_anti_spoofing - Enable/Disable Ethertype anti-spoofing 1303 * @hw: pointer to hardware structure 1304 * @enable: enable or disable switch for Ethertype anti-spoofing 1305 * @vf: Virtual Function pool - VF Pool to set for Ethertype anti-spoofing 1306 * 1307 **/ 1308 void ixgbe_set_ethertype_anti_spoofing(struct ixgbe_hw *hw, bool enable, int vf) 1309 { 1310 if (hw->mac.ops.set_ethertype_anti_spoofing) 1311 hw->mac.ops.set_ethertype_anti_spoofing(hw, enable, vf); 1312 } 1313 1314 /** 1315 * ixgbe_read_iosf_sb_reg - Read 32 bit PHY register 1316 * @hw: pointer to hardware structure 1317 * @reg_addr: 32 bit address of PHY register to read 1318 * @device_type: type of device you want to communicate with 1319 * @phy_data: Pointer to read data from PHY register 1320 * 1321 * Reads a value from a specified PHY register 1322 **/ 1323 s32 ixgbe_read_iosf_sb_reg(struct ixgbe_hw *hw, u32 reg_addr, 1324 u32 device_type, u32 *phy_data) 1325 { 1326 return ixgbe_call_func(hw, hw->mac.ops.read_iosf_sb_reg, (hw, reg_addr, 1327 device_type, phy_data), IXGBE_NOT_IMPLEMENTED); 1328 } 1329 1330 /** 1331 * ixgbe_write_iosf_sb_reg - Write 32 bit register through IOSF Sideband 1332 * @hw: pointer to hardware structure 1333 * @reg_addr: 32 bit PHY register to write 1334 * @device_type: type of device you want to communicate with 1335 * @phy_data: Data to write to the PHY register 1336 * 1337 * Writes a value to specified PHY register 1338 **/ 1339 s32 ixgbe_write_iosf_sb_reg(struct ixgbe_hw *hw, u32 reg_addr, 1340 u32 device_type, u32 phy_data) 1341 { 1342 return ixgbe_call_func(hw, hw->mac.ops.write_iosf_sb_reg, (hw, reg_addr, 1343 device_type, phy_data), IXGBE_NOT_IMPLEMENTED); 1344 } 1345 1346 /** 1347 * ixgbe_disable_mdd - Disable malicious driver detection 1348 * @hw: pointer to hardware structure 1349 * 1350 **/ 1351 void ixgbe_disable_mdd(struct ixgbe_hw *hw) 1352 { 1353 if (hw->mac.ops.disable_mdd) 1354 hw->mac.ops.disable_mdd(hw); 1355 } 1356 1357 /** 1358 * ixgbe_enable_mdd - Enable malicious driver detection 1359 * @hw: pointer to hardware structure 1360 * 1361 **/ 1362 void ixgbe_enable_mdd(struct ixgbe_hw *hw) 1363 { 1364 if (hw->mac.ops.enable_mdd) 1365 hw->mac.ops.enable_mdd(hw); 1366 } 1367 1368 /** 1369 * ixgbe_mdd_event - Handle malicious driver detection event 1370 * @hw: pointer to hardware structure 1371 * @vf_bitmap: vf bitmap of malicious vfs 1372 * 1373 **/ 1374 void ixgbe_mdd_event(struct ixgbe_hw *hw, u32 *vf_bitmap) 1375 { 1376 if (hw->mac.ops.mdd_event) 1377 hw->mac.ops.mdd_event(hw, vf_bitmap); 1378 } 1379 1380 /** 1381 * ixgbe_restore_mdd_vf - Restore VF that was disabled during malicious driver 1382 * detection event 1383 * @hw: pointer to hardware structure 1384 * @vf: vf index 1385 * 1386 **/ 1387 void ixgbe_restore_mdd_vf(struct ixgbe_hw *hw, u32 vf) 1388 { 1389 if (hw->mac.ops.restore_mdd_vf) 1390 hw->mac.ops.restore_mdd_vf(hw, vf); 1391 } 1392 1393 /** 1394 * ixgbe_fw_recovery_mode - Check if in FW NVM recovery mode 1395 * @hw: pointer to hardware structure 1396 * 1397 **/ 1398 bool ixgbe_fw_recovery_mode(struct ixgbe_hw *hw) 1399 { 1400 if (hw->mac.ops.fw_recovery_mode) 1401 return hw->mac.ops.fw_recovery_mode(hw); 1402 return false; 1403 } 1404 1405 /** 1406 * ixgbe_enter_lplu - Transition to low power states 1407 * @hw: pointer to hardware structure 1408 * 1409 * Configures Low Power Link Up on transition to low power states 1410 * (from D0 to non-D0). 1411 **/ 1412 s32 ixgbe_enter_lplu(struct ixgbe_hw *hw) 1413 { 1414 return ixgbe_call_func(hw, hw->phy.ops.enter_lplu, (hw), 1415 IXGBE_NOT_IMPLEMENTED); 1416 } 1417 1418 /** 1419 * ixgbe_handle_lasi - Handle external Base T PHY interrupt 1420 * @hw: pointer to hardware structure 1421 * 1422 * Handle external Base T PHY interrupt. If high temperature 1423 * failure alarm then return error, else if link status change 1424 * then setup internal/external PHY link 1425 * 1426 * Return IXGBE_ERR_OVERTEMP if interrupt is high temperature 1427 * failure alarm, else return PHY access status. 1428 */ 1429 s32 ixgbe_handle_lasi(struct ixgbe_hw *hw) 1430 { 1431 return ixgbe_call_func(hw, hw->phy.ops.handle_lasi, (hw), 1432 IXGBE_NOT_IMPLEMENTED); 1433 } 1434 1435 /** 1436 * ixgbe_bypass_rw - Bit bang data into by_pass FW 1437 * @hw: pointer to hardware structure 1438 * @cmd: Command we send to the FW 1439 * @status: The reply from the FW 1440 * 1441 * Bit-bangs the cmd to the by_pass FW status points to what is returned. 1442 **/ 1443 s32 ixgbe_bypass_rw(struct ixgbe_hw *hw, u32 cmd, u32 *status) 1444 { 1445 return ixgbe_call_func(hw, hw->mac.ops.bypass_rw, (hw, cmd, status), 1446 IXGBE_NOT_IMPLEMENTED); 1447 } 1448 1449 /** 1450 * ixgbe_bypass_valid_rd - Verify valid return from bit-bang. 1451 * @hw: pointer to hardware structure 1452 * @in_reg: The register cmd for the bit-bang read. 1453 * @out_reg: The register returned from a bit-bang read. 1454 * 1455 * If we send a write we can't be sure it took until we can read back 1456 * that same register. It can be a problem as some of the fields may 1457 * for valid reasons change inbetween the time wrote the register and 1458 * we read it again to verify. So this function check everything we 1459 * can check and then assumes it worked. 1460 **/ 1461 bool ixgbe_bypass_valid_rd(struct ixgbe_hw *hw, u32 in_reg, u32 out_reg) 1462 { 1463 return ixgbe_call_func(hw, hw->mac.ops.bypass_valid_rd, 1464 (in_reg, out_reg), IXGBE_NOT_IMPLEMENTED); 1465 } 1466 1467 /** 1468 * ixgbe_bypass_set - Set a bypass field in the FW CTRL Regiter. 1469 * @hw: pointer to hardware structure 1470 * @cmd: The control word we are setting. 1471 * @event: The event we are setting in the FW. This also happens to 1472 * be the mask for the event we are setting (handy) 1473 * @action: The action we set the event to in the FW. This is in a 1474 * bit field that happens to be what we want to put in 1475 * the event spot (also handy) 1476 * 1477 * Writes to the cmd control the bits in actions. 1478 **/ 1479 s32 ixgbe_bypass_set(struct ixgbe_hw *hw, u32 cmd, u32 event, u32 action) 1480 { 1481 return ixgbe_call_func(hw, hw->mac.ops.bypass_set, 1482 (hw, cmd, event, action), 1483 IXGBE_NOT_IMPLEMENTED); 1484 } 1485 1486 /** 1487 * ixgbe_bypass_rd_eep - Read the bypass FW eeprom address 1488 * @hw: pointer to hardware structure 1489 * @addr: The bypass eeprom address to read. 1490 * @value: The 8b of data at the address above. 1491 **/ 1492 s32 ixgbe_bypass_rd_eep(struct ixgbe_hw *hw, u32 addr, u8 *value) 1493 { 1494 return ixgbe_call_func(hw, hw->mac.ops.bypass_rd_eep, 1495 (hw, addr, value), IXGBE_NOT_IMPLEMENTED); 1496 } 1497 1498 /** 1499 * ixgbe_read_analog_reg8 - Reads 8 bit analog register 1500 * @hw: pointer to hardware structure 1501 * @reg: analog register to read 1502 * @val: read value 1503 * 1504 * Performs write operation to analog register specified. 1505 **/ 1506 s32 ixgbe_read_analog_reg8(struct ixgbe_hw *hw, u32 reg, u8 *val) 1507 { 1508 return ixgbe_call_func(hw, hw->mac.ops.read_analog_reg8, (hw, reg, 1509 val), IXGBE_NOT_IMPLEMENTED); 1510 } 1511 1512 /** 1513 * ixgbe_write_analog_reg8 - Writes 8 bit analog register 1514 * @hw: pointer to hardware structure 1515 * @reg: analog register to write 1516 * @val: value to write 1517 * 1518 * Performs write operation to Atlas analog register specified. 1519 **/ 1520 s32 ixgbe_write_analog_reg8(struct ixgbe_hw *hw, u32 reg, u8 val) 1521 { 1522 return ixgbe_call_func(hw, hw->mac.ops.write_analog_reg8, (hw, reg, 1523 val), IXGBE_NOT_IMPLEMENTED); 1524 } 1525 1526 /** 1527 * ixgbe_init_uta_tables - Initializes Unicast Table Arrays. 1528 * @hw: pointer to hardware structure 1529 * 1530 * Initializes the Unicast Table Arrays to zero on device load. This 1531 * is part of the Rx init addr execution path. 1532 **/ 1533 s32 ixgbe_init_uta_tables(struct ixgbe_hw *hw) 1534 { 1535 return ixgbe_call_func(hw, hw->mac.ops.init_uta_tables, (hw), 1536 IXGBE_NOT_IMPLEMENTED); 1537 } 1538 1539 /** 1540 * ixgbe_read_i2c_byte - Reads 8 bit word over I2C at specified device address 1541 * @hw: pointer to hardware structure 1542 * @byte_offset: byte offset to read 1543 * @dev_addr: I2C bus address to read from 1544 * @data: value read 1545 * 1546 * Performs byte read operation to SFP module's EEPROM over I2C interface. 1547 **/ 1548 s32 ixgbe_read_i2c_byte(struct ixgbe_hw *hw, u8 byte_offset, u8 dev_addr, 1549 u8 *data) 1550 { 1551 return ixgbe_call_func(hw, hw->phy.ops.read_i2c_byte, (hw, byte_offset, 1552 dev_addr, data), IXGBE_NOT_IMPLEMENTED); 1553 } 1554 1555 /** 1556 * ixgbe_read_i2c_byte_unlocked - Reads 8 bit word via I2C from device address 1557 * @hw: pointer to hardware structure 1558 * @byte_offset: byte offset to read 1559 * @dev_addr: I2C bus address to read from 1560 * @data: value read 1561 * 1562 * Performs byte read operation to SFP module's EEPROM over I2C interface. 1563 **/ 1564 s32 ixgbe_read_i2c_byte_unlocked(struct ixgbe_hw *hw, u8 byte_offset, 1565 u8 dev_addr, u8 *data) 1566 { 1567 return ixgbe_call_func(hw, hw->phy.ops.read_i2c_byte_unlocked, 1568 (hw, byte_offset, dev_addr, data), 1569 IXGBE_NOT_IMPLEMENTED); 1570 } 1571 1572 /** 1573 * ixgbe_read_link - Perform read operation on link device 1574 * @hw: pointer to the hardware structure 1575 * @addr: bus address to read from 1576 * @reg: device register to read from 1577 * @val: pointer to location to receive read value 1578 * 1579 * Returns an error code on error. 1580 */ 1581 s32 ixgbe_read_link(struct ixgbe_hw *hw, u8 addr, u16 reg, u16 *val) 1582 { 1583 return ixgbe_call_func(hw, hw->link.ops.read_link, (hw, addr, 1584 reg, val), IXGBE_NOT_IMPLEMENTED); 1585 } 1586 1587 /** 1588 * ixgbe_read_link_unlocked - Perform read operation on link device 1589 * @hw: pointer to the hardware structure 1590 * @addr: bus address to read from 1591 * @reg: device register to read from 1592 * @val: pointer to location to receive read value 1593 * 1594 * Returns an error code on error. 1595 **/ 1596 s32 ixgbe_read_link_unlocked(struct ixgbe_hw *hw, u8 addr, u16 reg, u16 *val) 1597 { 1598 return ixgbe_call_func(hw, hw->link.ops.read_link_unlocked, 1599 (hw, addr, reg, val), IXGBE_NOT_IMPLEMENTED); 1600 } 1601 1602 /** 1603 * ixgbe_write_i2c_byte - Writes 8 bit word over I2C 1604 * @hw: pointer to hardware structure 1605 * @byte_offset: byte offset to write 1606 * @dev_addr: I2C bus address to write to 1607 * @data: value to write 1608 * 1609 * Performs byte write operation to SFP module's EEPROM over I2C interface 1610 * at a specified device address. 1611 **/ 1612 s32 ixgbe_write_i2c_byte(struct ixgbe_hw *hw, u8 byte_offset, u8 dev_addr, 1613 u8 data) 1614 { 1615 return ixgbe_call_func(hw, hw->phy.ops.write_i2c_byte, (hw, byte_offset, 1616 dev_addr, data), IXGBE_NOT_IMPLEMENTED); 1617 } 1618 1619 /** 1620 * ixgbe_write_i2c_byte_unlocked - Writes 8 bit word over I2C 1621 * @hw: pointer to hardware structure 1622 * @byte_offset: byte offset to write 1623 * @dev_addr: I2C bus address to write to 1624 * @data: value to write 1625 * 1626 * Performs byte write operation to SFP module's EEPROM over I2C interface 1627 * at a specified device address. 1628 **/ 1629 s32 ixgbe_write_i2c_byte_unlocked(struct ixgbe_hw *hw, u8 byte_offset, 1630 u8 dev_addr, u8 data) 1631 { 1632 return ixgbe_call_func(hw, hw->phy.ops.write_i2c_byte_unlocked, 1633 (hw, byte_offset, dev_addr, data), 1634 IXGBE_NOT_IMPLEMENTED); 1635 } 1636 1637 /** 1638 * ixgbe_write_link - Perform write operation on link device 1639 * @hw: pointer to the hardware structure 1640 * @addr: bus address to write to 1641 * @reg: device register to write to 1642 * @val: value to write 1643 * 1644 * Returns an error code on error. 1645 */ 1646 s32 ixgbe_write_link(struct ixgbe_hw *hw, u8 addr, u16 reg, u16 val) 1647 { 1648 return ixgbe_call_func(hw, hw->link.ops.write_link, 1649 (hw, addr, reg, val), IXGBE_NOT_IMPLEMENTED); 1650 } 1651 1652 /** 1653 * ixgbe_write_link_unlocked - Perform write operation on link device 1654 * @hw: pointer to the hardware structure 1655 * @addr: bus address to write to 1656 * @reg: device register to write to 1657 * @val: value to write 1658 * 1659 * Returns an error code on error. 1660 **/ 1661 s32 ixgbe_write_link_unlocked(struct ixgbe_hw *hw, u8 addr, u16 reg, u16 val) 1662 { 1663 return ixgbe_call_func(hw, hw->link.ops.write_link_unlocked, 1664 (hw, addr, reg, val), IXGBE_NOT_IMPLEMENTED); 1665 } 1666 1667 /** 1668 * ixgbe_write_i2c_eeprom - Writes 8 bit EEPROM word over I2C interface 1669 * @hw: pointer to hardware structure 1670 * @byte_offset: EEPROM byte offset to write 1671 * @eeprom_data: value to write 1672 * 1673 * Performs byte write operation to SFP module's EEPROM over I2C interface. 1674 **/ 1675 s32 ixgbe_write_i2c_eeprom(struct ixgbe_hw *hw, 1676 u8 byte_offset, u8 eeprom_data) 1677 { 1678 return ixgbe_call_func(hw, hw->phy.ops.write_i2c_eeprom, 1679 (hw, byte_offset, eeprom_data), 1680 IXGBE_NOT_IMPLEMENTED); 1681 } 1682 1683 /** 1684 * ixgbe_read_i2c_eeprom - Reads 8 bit EEPROM word over I2C interface 1685 * @hw: pointer to hardware structure 1686 * @byte_offset: EEPROM byte offset to read 1687 * @eeprom_data: value read 1688 * 1689 * Performs byte read operation to SFP module's EEPROM over I2C interface. 1690 **/ 1691 s32 ixgbe_read_i2c_eeprom(struct ixgbe_hw *hw, u8 byte_offset, u8 *eeprom_data) 1692 { 1693 return ixgbe_call_func(hw, hw->phy.ops.read_i2c_eeprom, 1694 (hw, byte_offset, eeprom_data), 1695 IXGBE_NOT_IMPLEMENTED); 1696 } 1697 1698 /** 1699 * ixgbe_get_supported_physical_layer - Returns physical layer type 1700 * @hw: pointer to hardware structure 1701 * 1702 * Determines physical layer capabilities of the current configuration. 1703 **/ 1704 u64 ixgbe_get_supported_physical_layer(struct ixgbe_hw *hw) 1705 { 1706 return ixgbe_call_func(hw, hw->mac.ops.get_supported_physical_layer, 1707 (hw), IXGBE_PHYSICAL_LAYER_UNKNOWN); 1708 } 1709 1710 /** 1711 * ixgbe_enable_rx_dma - Enables Rx DMA unit, dependent on device specifics 1712 * @hw: pointer to hardware structure 1713 * @regval: bitfield to write to the Rx DMA register 1714 * 1715 * Enables the Rx DMA unit of the device. 1716 **/ 1717 s32 ixgbe_enable_rx_dma(struct ixgbe_hw *hw, u32 regval) 1718 { 1719 return ixgbe_call_func(hw, hw->mac.ops.enable_rx_dma, 1720 (hw, regval), IXGBE_NOT_IMPLEMENTED); 1721 } 1722 1723 /** 1724 * ixgbe_disable_sec_rx_path - Stops the receive data path 1725 * @hw: pointer to hardware structure 1726 * 1727 * Stops the receive data path. 1728 **/ 1729 s32 ixgbe_disable_sec_rx_path(struct ixgbe_hw *hw) 1730 { 1731 return ixgbe_call_func(hw, hw->mac.ops.disable_sec_rx_path, 1732 (hw), IXGBE_NOT_IMPLEMENTED); 1733 } 1734 1735 /** 1736 * ixgbe_enable_sec_rx_path - Enables the receive data path 1737 * @hw: pointer to hardware structure 1738 * 1739 * Enables the receive data path. 1740 **/ 1741 s32 ixgbe_enable_sec_rx_path(struct ixgbe_hw *hw) 1742 { 1743 return ixgbe_call_func(hw, hw->mac.ops.enable_sec_rx_path, 1744 (hw), IXGBE_NOT_IMPLEMENTED); 1745 } 1746 1747 /** 1748 * ixgbe_acquire_swfw_semaphore - Acquire SWFW semaphore 1749 * @hw: pointer to hardware structure 1750 * @mask: Mask to specify which semaphore to acquire 1751 * 1752 * Acquires the SWFW semaphore through SW_FW_SYNC register for the specified 1753 * function (CSR, PHY0, PHY1, EEPROM, Flash) 1754 **/ 1755 s32 ixgbe_acquire_swfw_semaphore(struct ixgbe_hw *hw, u32 mask) 1756 { 1757 return ixgbe_call_func(hw, hw->mac.ops.acquire_swfw_sync, 1758 (hw, mask), IXGBE_NOT_IMPLEMENTED); 1759 } 1760 1761 /** 1762 * ixgbe_release_swfw_semaphore - Release SWFW semaphore 1763 * @hw: pointer to hardware structure 1764 * @mask: Mask to specify which semaphore to release 1765 * 1766 * Releases the SWFW semaphore through SW_FW_SYNC register for the specified 1767 * function (CSR, PHY0, PHY1, EEPROM, Flash) 1768 **/ 1769 void ixgbe_release_swfw_semaphore(struct ixgbe_hw *hw, u32 mask) 1770 { 1771 if (hw->mac.ops.release_swfw_sync) 1772 hw->mac.ops.release_swfw_sync(hw, mask); 1773 } 1774 1775 /** 1776 * ixgbe_init_swfw_semaphore - Clean up SWFW semaphore 1777 * @hw: pointer to hardware structure 1778 * 1779 * Attempts to acquire the SWFW semaphore through SW_FW_SYNC register. 1780 * Regardless of whether is succeeds or not it then release the semaphore. 1781 * This is function is called to recover from catastrophic failures that 1782 * may have left the semaphore locked. 1783 **/ 1784 void ixgbe_init_swfw_semaphore(struct ixgbe_hw *hw) 1785 { 1786 if (hw->mac.ops.init_swfw_sync) 1787 hw->mac.ops.init_swfw_sync(hw); 1788 } 1789 1790 1791 void ixgbe_disable_rx(struct ixgbe_hw *hw) 1792 { 1793 if (hw->mac.ops.disable_rx) 1794 hw->mac.ops.disable_rx(hw); 1795 } 1796 1797 void ixgbe_enable_rx(struct ixgbe_hw *hw) 1798 { 1799 if (hw->mac.ops.enable_rx) 1800 hw->mac.ops.enable_rx(hw); 1801 } 1802 1803 /** 1804 * ixgbe_set_rate_select_speed - Set module link speed 1805 * @hw: pointer to hardware structure 1806 * @speed: link speed to set 1807 * 1808 * Set module link speed via the rate select. 1809 */ 1810 void ixgbe_set_rate_select_speed(struct ixgbe_hw *hw, ixgbe_link_speed speed) 1811 { 1812 if (hw->mac.ops.set_rate_select_speed) 1813 hw->mac.ops.set_rate_select_speed(hw, speed); 1814 } 1815