1 /****************************************************************************** 2 SPDX-License-Identifier: BSD-3-Clause 3 4 Copyright (c) 2001-2020, Intel Corporation 5 All rights reserved. 6 7 Redistribution and use in source and binary forms, with or without 8 modification, are permitted provided that the following conditions are met: 9 10 1. Redistributions of source code must retain the above copyright notice, 11 this list of conditions and the following disclaimer. 12 13 2. Redistributions in binary form must reproduce the above copyright 14 notice, this list of conditions and the following disclaimer in the 15 documentation and/or other materials provided with the distribution. 16 17 3. Neither the name of the Intel Corporation nor the names of its 18 contributors may be used to endorse or promote products derived from 19 this software without specific prior written permission. 20 21 THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 22 AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 23 IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 24 ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE 25 LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 26 CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 27 SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 28 INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 29 CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 30 ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 31 POSSIBILITY OF SUCH DAMAGE. 32 33 ******************************************************************************/ 34 35 #include "ixgbe_api.h" 36 #include "ixgbe_common.h" 37 38 #define IXGBE_EMPTY_PARAM 39 40 static const u32 ixgbe_mvals_base[IXGBE_MVALS_IDX_LIMIT] = { 41 IXGBE_MVALS_INIT(IXGBE_EMPTY_PARAM) 42 }; 43 44 static const u32 ixgbe_mvals_X540[IXGBE_MVALS_IDX_LIMIT] = { 45 IXGBE_MVALS_INIT(_X540) 46 }; 47 48 static const u32 ixgbe_mvals_X550[IXGBE_MVALS_IDX_LIMIT] = { 49 IXGBE_MVALS_INIT(_X550) 50 }; 51 52 static const u32 ixgbe_mvals_X550EM_x[IXGBE_MVALS_IDX_LIMIT] = { 53 IXGBE_MVALS_INIT(_X550EM_x) 54 }; 55 56 static const u32 ixgbe_mvals_X550EM_a[IXGBE_MVALS_IDX_LIMIT] = { 57 IXGBE_MVALS_INIT(_X550EM_a) 58 }; 59 60 /** 61 * ixgbe_dcb_get_rtrup2tc - read rtrup2tc reg 62 * @hw: pointer to hardware structure 63 * @map: pointer to u8 arr for returning map 64 * 65 * Read the rtrup2tc HW register and resolve its content into map 66 **/ 67 void ixgbe_dcb_get_rtrup2tc(struct ixgbe_hw *hw, u8 *map) 68 { 69 if (hw->mac.ops.get_rtrup2tc) 70 hw->mac.ops.get_rtrup2tc(hw, map); 71 } 72 73 /** 74 * ixgbe_init_shared_code - Initialize the shared code 75 * @hw: pointer to hardware structure 76 * 77 * This will assign function pointers and assign the MAC type and PHY code. 78 * Does not touch the hardware. This function must be called prior to any 79 * other function in the shared code. The ixgbe_hw structure should be 80 * memset to 0 prior to calling this function. The following fields in 81 * hw structure should be filled in prior to calling this function: 82 * hw_addr, back, device_id, vendor_id, subsystem_device_id, 83 * subsystem_vendor_id, and revision_id 84 **/ 85 s32 ixgbe_init_shared_code(struct ixgbe_hw *hw) 86 { 87 s32 status; 88 89 DEBUGFUNC("ixgbe_init_shared_code"); 90 91 /* 92 * Set the mac type 93 */ 94 ixgbe_set_mac_type(hw); 95 96 switch (hw->mac.type) { 97 case ixgbe_mac_82598EB: 98 status = ixgbe_init_ops_82598(hw); 99 break; 100 case ixgbe_mac_82599EB: 101 status = ixgbe_init_ops_82599(hw); 102 break; 103 case ixgbe_mac_X540: 104 status = ixgbe_init_ops_X540(hw); 105 break; 106 case ixgbe_mac_X550: 107 status = ixgbe_init_ops_X550(hw); 108 break; 109 case ixgbe_mac_X550EM_x: 110 status = ixgbe_init_ops_X550EM_x(hw); 111 break; 112 case ixgbe_mac_X550EM_a: 113 status = ixgbe_init_ops_X550EM_a(hw); 114 break; 115 case ixgbe_mac_E610: 116 status = ixgbe_init_ops_E610(hw); 117 break; 118 case ixgbe_mac_82599_vf: 119 case ixgbe_mac_X540_vf: 120 case ixgbe_mac_X550_vf: 121 case ixgbe_mac_X550EM_x_vf: 122 case ixgbe_mac_X550EM_a_vf: 123 case ixgbe_mac_E610_vf: 124 status = ixgbe_init_ops_vf(hw); 125 break; 126 default: 127 status = IXGBE_ERR_DEVICE_NOT_SUPPORTED; 128 break; 129 } 130 hw->mac.max_link_up_time = IXGBE_LINK_UP_TIME; 131 132 return status; 133 } 134 135 /** 136 * ixgbe_set_mac_type - Sets MAC type 137 * @hw: pointer to the HW structure 138 * 139 * This function sets the mac type of the adapter based on the 140 * vendor ID and device ID stored in the hw structure. 141 **/ 142 s32 ixgbe_set_mac_type(struct ixgbe_hw *hw) 143 { 144 s32 ret_val = IXGBE_SUCCESS; 145 146 DEBUGFUNC("ixgbe_set_mac_type\n"); 147 148 if (hw->vendor_id != IXGBE_INTEL_VENDOR_ID) { 149 ERROR_REPORT2(IXGBE_ERROR_UNSUPPORTED, 150 "Unsupported vendor id: %x", hw->vendor_id); 151 return IXGBE_ERR_DEVICE_NOT_SUPPORTED; 152 } 153 154 hw->mvals = ixgbe_mvals_base; 155 156 switch (hw->device_id) { 157 case IXGBE_DEV_ID_82598: 158 case IXGBE_DEV_ID_82598_BX: 159 case IXGBE_DEV_ID_82598AF_SINGLE_PORT: 160 case IXGBE_DEV_ID_82598AF_DUAL_PORT: 161 case IXGBE_DEV_ID_82598AT: 162 case IXGBE_DEV_ID_82598AT2: 163 case IXGBE_DEV_ID_82598EB_CX4: 164 case IXGBE_DEV_ID_82598_CX4_DUAL_PORT: 165 case IXGBE_DEV_ID_82598_DA_DUAL_PORT: 166 case IXGBE_DEV_ID_82598_SR_DUAL_PORT_EM: 167 case IXGBE_DEV_ID_82598EB_XF_LR: 168 case IXGBE_DEV_ID_82598EB_SFP_LOM: 169 hw->mac.type = ixgbe_mac_82598EB; 170 break; 171 case IXGBE_DEV_ID_82599_KX4: 172 case IXGBE_DEV_ID_82599_KX4_MEZZ: 173 case IXGBE_DEV_ID_82599_XAUI_LOM: 174 case IXGBE_DEV_ID_82599_COMBO_BACKPLANE: 175 case IXGBE_DEV_ID_82599_KR: 176 case IXGBE_DEV_ID_82599_SFP: 177 case IXGBE_DEV_ID_82599_BACKPLANE_FCOE: 178 case IXGBE_DEV_ID_82599_SFP_FCOE: 179 case IXGBE_DEV_ID_82599_SFP_EM: 180 case IXGBE_DEV_ID_82599_SFP_SF2: 181 case IXGBE_DEV_ID_82599_SFP_SF_QP: 182 case IXGBE_DEV_ID_82599_QSFP_SF_QP: 183 case IXGBE_DEV_ID_82599EN_SFP: 184 case IXGBE_DEV_ID_82599_CX4: 185 case IXGBE_DEV_ID_82599_BYPASS: 186 case IXGBE_DEV_ID_82599_T3_LOM: 187 hw->mac.type = ixgbe_mac_82599EB; 188 break; 189 case IXGBE_DEV_ID_82599_VF: 190 case IXGBE_DEV_ID_82599_VF_HV: 191 hw->mac.type = ixgbe_mac_82599_vf; 192 break; 193 case IXGBE_DEV_ID_X540_VF: 194 case IXGBE_DEV_ID_X540_VF_HV: 195 hw->mac.type = ixgbe_mac_X540_vf; 196 hw->mvals = ixgbe_mvals_X540; 197 break; 198 case IXGBE_DEV_ID_X540T: 199 case IXGBE_DEV_ID_X540T1: 200 case IXGBE_DEV_ID_X540_BYPASS: 201 hw->mac.type = ixgbe_mac_X540; 202 hw->mvals = ixgbe_mvals_X540; 203 break; 204 case IXGBE_DEV_ID_X550T: 205 case IXGBE_DEV_ID_X550T1: 206 hw->mac.type = ixgbe_mac_X550; 207 hw->mvals = ixgbe_mvals_X550; 208 break; 209 case IXGBE_DEV_ID_X550EM_X_KX4: 210 case IXGBE_DEV_ID_X550EM_X_KR: 211 case IXGBE_DEV_ID_X550EM_X_10G_T: 212 case IXGBE_DEV_ID_X550EM_X_1G_T: 213 case IXGBE_DEV_ID_X550EM_X_SFP: 214 case IXGBE_DEV_ID_X550EM_X_XFI: 215 hw->mac.type = ixgbe_mac_X550EM_x; 216 hw->mvals = ixgbe_mvals_X550EM_x; 217 break; 218 case IXGBE_DEV_ID_X550EM_A_KR: 219 case IXGBE_DEV_ID_X550EM_A_KR_L: 220 case IXGBE_DEV_ID_X550EM_A_SFP_N: 221 case IXGBE_DEV_ID_X550EM_A_SGMII: 222 case IXGBE_DEV_ID_X550EM_A_SGMII_L: 223 case IXGBE_DEV_ID_X550EM_A_1G_T: 224 case IXGBE_DEV_ID_X550EM_A_1G_T_L: 225 case IXGBE_DEV_ID_X550EM_A_10G_T: 226 case IXGBE_DEV_ID_X550EM_A_QSFP: 227 case IXGBE_DEV_ID_X550EM_A_QSFP_N: 228 case IXGBE_DEV_ID_X550EM_A_SFP: 229 hw->mac.type = ixgbe_mac_X550EM_a; 230 hw->mvals = ixgbe_mvals_X550EM_a; 231 break; 232 case IXGBE_DEV_ID_X550_VF: 233 case IXGBE_DEV_ID_X550_VF_HV: 234 hw->mac.type = ixgbe_mac_X550_vf; 235 hw->mvals = ixgbe_mvals_X550; 236 break; 237 case IXGBE_DEV_ID_X550EM_X_VF: 238 case IXGBE_DEV_ID_X550EM_X_VF_HV: 239 hw->mac.type = ixgbe_mac_X550EM_x_vf; 240 hw->mvals = ixgbe_mvals_X550EM_x; 241 break; 242 case IXGBE_DEV_ID_X550EM_A_VF: 243 case IXGBE_DEV_ID_X550EM_A_VF_HV: 244 hw->mac.type = ixgbe_mac_X550EM_a_vf; 245 hw->mvals = ixgbe_mvals_X550EM_a; 246 break; 247 case IXGBE_DEV_ID_E610_BACKPLANE: 248 case IXGBE_DEV_ID_E610_SFP: 249 case IXGBE_DEV_ID_E610_10G_T: 250 case IXGBE_DEV_ID_E610_2_5G_T: 251 case IXGBE_DEV_ID_E610_SGMII: 252 hw->mac.type = ixgbe_mac_E610; 253 hw->mvals = ixgbe_mvals_X550EM_a; 254 break; 255 case IXGBE_DEV_ID_E610_VF: 256 hw->mac.type = ixgbe_mac_E610_vf; 257 hw->mvals = ixgbe_mvals_X550EM_a; 258 break; 259 default: 260 ret_val = IXGBE_ERR_DEVICE_NOT_SUPPORTED; 261 ERROR_REPORT2(IXGBE_ERROR_UNSUPPORTED, 262 "Unsupported device id: %x", 263 hw->device_id); 264 break; 265 } 266 267 DEBUGOUT2("ixgbe_set_mac_type found mac: %d, returns: %d\n", 268 hw->mac.type, ret_val); 269 return ret_val; 270 } 271 272 /** 273 * ixgbe_init_hw - Initialize the hardware 274 * @hw: pointer to hardware structure 275 * 276 * Initialize the hardware by resetting and then starting the hardware 277 **/ 278 s32 ixgbe_init_hw(struct ixgbe_hw *hw) 279 { 280 return ixgbe_call_func(hw, hw->mac.ops.init_hw, (hw), 281 IXGBE_NOT_IMPLEMENTED); 282 } 283 284 /** 285 * ixgbe_reset_hw - Performs a hardware reset 286 * @hw: pointer to hardware structure 287 * 288 * Resets the hardware by resetting the transmit and receive units, masks and 289 * clears all interrupts, performs a PHY reset, and performs a MAC reset 290 **/ 291 s32 ixgbe_reset_hw(struct ixgbe_hw *hw) 292 { 293 return ixgbe_call_func(hw, hw->mac.ops.reset_hw, (hw), 294 IXGBE_NOT_IMPLEMENTED); 295 } 296 297 /** 298 * ixgbe_start_hw - Prepares hardware for Rx/Tx 299 * @hw: pointer to hardware structure 300 * 301 * Starts the hardware by filling the bus info structure and media type, 302 * clears all on chip counters, initializes receive address registers, 303 * multicast table, VLAN filter table, calls routine to setup link and 304 * flow control settings, and leaves transmit and receive units disabled 305 * and uninitialized. 306 **/ 307 s32 ixgbe_start_hw(struct ixgbe_hw *hw) 308 { 309 return ixgbe_call_func(hw, hw->mac.ops.start_hw, (hw), 310 IXGBE_NOT_IMPLEMENTED); 311 } 312 313 /** 314 * ixgbe_enable_relaxed_ordering - Enables tx relaxed ordering, 315 * which is disabled by default in ixgbe_start_hw(); 316 * 317 * @hw: pointer to hardware structure 318 * 319 * Enable relaxed ordering; 320 **/ 321 void ixgbe_enable_relaxed_ordering(struct ixgbe_hw *hw) 322 { 323 if (hw->mac.ops.enable_relaxed_ordering) 324 hw->mac.ops.enable_relaxed_ordering(hw); 325 } 326 327 /** 328 * ixgbe_clear_hw_cntrs - Clear hardware counters 329 * @hw: pointer to hardware structure 330 * 331 * Clears all hardware statistics counters by reading them from the hardware 332 * Statistics counters are clear on read. 333 **/ 334 s32 ixgbe_clear_hw_cntrs(struct ixgbe_hw *hw) 335 { 336 return ixgbe_call_func(hw, hw->mac.ops.clear_hw_cntrs, (hw), 337 IXGBE_NOT_IMPLEMENTED); 338 } 339 340 /** 341 * ixgbe_get_media_type - Get media type 342 * @hw: pointer to hardware structure 343 * 344 * Returns the media type (fiber, copper, backplane) 345 **/ 346 enum ixgbe_media_type ixgbe_get_media_type(struct ixgbe_hw *hw) 347 { 348 return ixgbe_call_func(hw, hw->mac.ops.get_media_type, (hw), 349 ixgbe_media_type_unknown); 350 } 351 352 /** 353 * ixgbe_get_mac_addr - Get MAC address 354 * @hw: pointer to hardware structure 355 * @mac_addr: Adapter MAC address 356 * 357 * Reads the adapter's MAC address from the first Receive Address Register 358 * (RAR0) A reset of the adapter must have been performed prior to calling 359 * this function in order for the MAC address to have been loaded from the 360 * EEPROM into RAR0 361 **/ 362 s32 ixgbe_get_mac_addr(struct ixgbe_hw *hw, u8 *mac_addr) 363 { 364 return ixgbe_call_func(hw, hw->mac.ops.get_mac_addr, 365 (hw, mac_addr), IXGBE_NOT_IMPLEMENTED); 366 } 367 368 /** 369 * ixgbe_get_san_mac_addr - Get SAN MAC address 370 * @hw: pointer to hardware structure 371 * @san_mac_addr: SAN MAC address 372 * 373 * Reads the SAN MAC address from the EEPROM, if it's available. This is 374 * per-port, so set_lan_id() must be called before reading the addresses. 375 **/ 376 s32 ixgbe_get_san_mac_addr(struct ixgbe_hw *hw, u8 *san_mac_addr) 377 { 378 return ixgbe_call_func(hw, hw->mac.ops.get_san_mac_addr, 379 (hw, san_mac_addr), IXGBE_NOT_IMPLEMENTED); 380 } 381 382 /** 383 * ixgbe_set_san_mac_addr - Write a SAN MAC address 384 * @hw: pointer to hardware structure 385 * @san_mac_addr: SAN MAC address 386 * 387 * Writes A SAN MAC address to the EEPROM. 388 **/ 389 s32 ixgbe_set_san_mac_addr(struct ixgbe_hw *hw, u8 *san_mac_addr) 390 { 391 return ixgbe_call_func(hw, hw->mac.ops.set_san_mac_addr, 392 (hw, san_mac_addr), IXGBE_NOT_IMPLEMENTED); 393 } 394 395 /** 396 * ixgbe_get_device_caps - Get additional device capabilities 397 * @hw: pointer to hardware structure 398 * @device_caps: the EEPROM word for device capabilities 399 * 400 * Reads the extra device capabilities from the EEPROM 401 **/ 402 s32 ixgbe_get_device_caps(struct ixgbe_hw *hw, u16 *device_caps) 403 { 404 return ixgbe_call_func(hw, hw->mac.ops.get_device_caps, 405 (hw, device_caps), IXGBE_NOT_IMPLEMENTED); 406 } 407 408 /** 409 * ixgbe_get_wwn_prefix - Get alternative WWNN/WWPN prefix from the EEPROM 410 * @hw: pointer to hardware structure 411 * @wwnn_prefix: the alternative WWNN prefix 412 * @wwpn_prefix: the alternative WWPN prefix 413 * 414 * This function will read the EEPROM from the alternative SAN MAC address 415 * block to check the support for the alternative WWNN/WWPN prefix support. 416 **/ 417 s32 ixgbe_get_wwn_prefix(struct ixgbe_hw *hw, u16 *wwnn_prefix, 418 u16 *wwpn_prefix) 419 { 420 return ixgbe_call_func(hw, hw->mac.ops.get_wwn_prefix, 421 (hw, wwnn_prefix, wwpn_prefix), 422 IXGBE_NOT_IMPLEMENTED); 423 } 424 425 /** 426 * ixgbe_get_fcoe_boot_status - Get FCOE boot status from EEPROM 427 * @hw: pointer to hardware structure 428 * @bs: the fcoe boot status 429 * 430 * This function will read the FCOE boot status from the iSCSI FCOE block 431 **/ 432 s32 ixgbe_get_fcoe_boot_status(struct ixgbe_hw *hw, u16 *bs) 433 { 434 return ixgbe_call_func(hw, hw->mac.ops.get_fcoe_boot_status, 435 (hw, bs), 436 IXGBE_NOT_IMPLEMENTED); 437 } 438 439 /** 440 * ixgbe_get_bus_info - Set PCI bus info 441 * @hw: pointer to hardware structure 442 * 443 * Sets the PCI bus info (speed, width, type) within the ixgbe_hw structure 444 **/ 445 s32 ixgbe_get_bus_info(struct ixgbe_hw *hw) 446 { 447 return ixgbe_call_func(hw, hw->mac.ops.get_bus_info, (hw), 448 IXGBE_NOT_IMPLEMENTED); 449 } 450 451 /** 452 * ixgbe_get_num_of_tx_queues - Get Tx queues 453 * @hw: pointer to hardware structure 454 * 455 * Returns the number of transmit queues for the given adapter. 456 **/ 457 u32 ixgbe_get_num_of_tx_queues(struct ixgbe_hw *hw) 458 { 459 return hw->mac.max_tx_queues; 460 } 461 462 /** 463 * ixgbe_get_num_of_rx_queues - Get Rx queues 464 * @hw: pointer to hardware structure 465 * 466 * Returns the number of receive queues for the given adapter. 467 **/ 468 u32 ixgbe_get_num_of_rx_queues(struct ixgbe_hw *hw) 469 { 470 return hw->mac.max_rx_queues; 471 } 472 473 /** 474 * ixgbe_stop_adapter - Disable Rx/Tx units 475 * @hw: pointer to hardware structure 476 * 477 * Sets the adapter_stopped flag within ixgbe_hw struct. Clears interrupts, 478 * disables transmit and receive units. The adapter_stopped flag is used by 479 * the shared code and drivers to determine if the adapter is in a stopped 480 * state and should not touch the hardware. 481 **/ 482 s32 ixgbe_stop_adapter(struct ixgbe_hw *hw) 483 { 484 return ixgbe_call_func(hw, hw->mac.ops.stop_adapter, (hw), 485 IXGBE_NOT_IMPLEMENTED); 486 } 487 488 /** 489 * ixgbe_read_pba_string - Reads part number string from EEPROM 490 * @hw: pointer to hardware structure 491 * @pba_num: stores the part number string from the EEPROM 492 * @pba_num_size: part number string buffer length 493 * 494 * Reads the part number string from the EEPROM. 495 **/ 496 s32 ixgbe_read_pba_string(struct ixgbe_hw *hw, u8 *pba_num, u32 pba_num_size) 497 { 498 return ixgbe_read_pba_string_generic(hw, pba_num, pba_num_size); 499 } 500 501 /** 502 * ixgbe_read_pba_num - Reads part number from EEPROM 503 * @hw: pointer to hardware structure 504 * @pba_num: stores the part number from the EEPROM 505 * 506 * Reads the part number from the EEPROM. 507 **/ 508 s32 ixgbe_read_pba_num(struct ixgbe_hw *hw, u32 *pba_num) 509 { 510 return ixgbe_read_pba_num_generic(hw, pba_num); 511 } 512 513 /** 514 * ixgbe_identify_phy - Get PHY type 515 * @hw: pointer to hardware structure 516 * 517 * Determines the physical layer module found on the current adapter. 518 **/ 519 s32 ixgbe_identify_phy(struct ixgbe_hw *hw) 520 { 521 s32 status = IXGBE_SUCCESS; 522 523 if (hw->phy.type == ixgbe_phy_unknown) { 524 status = ixgbe_call_func(hw, hw->phy.ops.identify, (hw), 525 IXGBE_NOT_IMPLEMENTED); 526 } 527 528 return status; 529 } 530 531 /** 532 * ixgbe_reset_phy - Perform a PHY reset 533 * @hw: pointer to hardware structure 534 **/ 535 s32 ixgbe_reset_phy(struct ixgbe_hw *hw) 536 { 537 s32 status = IXGBE_SUCCESS; 538 539 if (hw->phy.type == ixgbe_phy_unknown) { 540 if (ixgbe_identify_phy(hw) != IXGBE_SUCCESS) 541 status = IXGBE_ERR_PHY; 542 } 543 544 if (status == IXGBE_SUCCESS) { 545 status = ixgbe_call_func(hw, hw->phy.ops.reset, (hw), 546 IXGBE_NOT_IMPLEMENTED); 547 } 548 return status; 549 } 550 551 /** 552 * ixgbe_get_phy_firmware_version - 553 * @hw: pointer to hardware structure 554 * @firmware_version: pointer to firmware version 555 **/ 556 s32 ixgbe_get_phy_firmware_version(struct ixgbe_hw *hw, u16 *firmware_version) 557 { 558 s32 status = IXGBE_SUCCESS; 559 560 status = ixgbe_call_func(hw, hw->phy.ops.get_firmware_version, 561 (hw, firmware_version), 562 IXGBE_NOT_IMPLEMENTED); 563 return status; 564 } 565 566 /** 567 * ixgbe_read_phy_reg - Read PHY register 568 * @hw: pointer to hardware structure 569 * @reg_addr: 32 bit address of PHY register to read 570 * @device_type: type of device you want to communicate with 571 * @phy_data: Pointer to read data from PHY register 572 * 573 * Reads a value from a specified PHY register 574 **/ 575 s32 ixgbe_read_phy_reg(struct ixgbe_hw *hw, u32 reg_addr, u32 device_type, 576 u16 *phy_data) 577 { 578 if (hw->phy.id == 0) 579 ixgbe_identify_phy(hw); 580 581 return ixgbe_call_func(hw, hw->phy.ops.read_reg, (hw, reg_addr, 582 device_type, phy_data), IXGBE_NOT_IMPLEMENTED); 583 } 584 585 /** 586 * ixgbe_write_phy_reg - Write PHY register 587 * @hw: pointer to hardware structure 588 * @reg_addr: 32 bit PHY register to write 589 * @device_type: type of device you want to communicate with 590 * @phy_data: Data to write to the PHY register 591 * 592 * Writes a value to specified PHY register 593 **/ 594 s32 ixgbe_write_phy_reg(struct ixgbe_hw *hw, u32 reg_addr, u32 device_type, 595 u16 phy_data) 596 { 597 if (hw->phy.id == 0) 598 ixgbe_identify_phy(hw); 599 600 return ixgbe_call_func(hw, hw->phy.ops.write_reg, (hw, reg_addr, 601 device_type, phy_data), IXGBE_NOT_IMPLEMENTED); 602 } 603 604 /** 605 * ixgbe_setup_phy_link - Restart PHY autoneg 606 * @hw: pointer to hardware structure 607 * 608 * Restart autonegotiation and PHY and waits for completion. 609 **/ 610 s32 ixgbe_setup_phy_link(struct ixgbe_hw *hw) 611 { 612 return ixgbe_call_func(hw, hw->phy.ops.setup_link, (hw), 613 IXGBE_NOT_IMPLEMENTED); 614 } 615 616 /** 617 * ixgbe_setup_internal_phy - Configure integrated PHY 618 * @hw: pointer to hardware structure 619 * 620 * Reconfigure the integrated PHY in order to enable talk to the external PHY. 621 * Returns success if not implemented, since nothing needs to be done in this 622 * case. 623 */ 624 s32 ixgbe_setup_internal_phy(struct ixgbe_hw *hw) 625 { 626 return ixgbe_call_func(hw, hw->phy.ops.setup_internal_link, (hw), 627 IXGBE_SUCCESS); 628 } 629 630 /** 631 * ixgbe_check_phy_link - Determine link and speed status 632 * @hw: pointer to hardware structure 633 * @speed: link speed 634 * @link_up: true when link is up 635 * 636 * Reads a PHY register to determine if link is up and the current speed for 637 * the PHY. 638 **/ 639 s32 ixgbe_check_phy_link(struct ixgbe_hw *hw, ixgbe_link_speed *speed, 640 bool *link_up) 641 { 642 return ixgbe_call_func(hw, hw->phy.ops.check_link, (hw, speed, 643 link_up), IXGBE_NOT_IMPLEMENTED); 644 } 645 646 /** 647 * ixgbe_setup_phy_link_speed - Set auto advertise 648 * @hw: pointer to hardware structure 649 * @speed: new link speed 650 * @autoneg_wait_to_complete: true when waiting for completion is needed 651 * 652 * Sets the auto advertised capabilities 653 **/ 654 s32 ixgbe_setup_phy_link_speed(struct ixgbe_hw *hw, ixgbe_link_speed speed, 655 bool autoneg_wait_to_complete) 656 { 657 return ixgbe_call_func(hw, hw->phy.ops.setup_link_speed, (hw, speed, 658 autoneg_wait_to_complete), 659 IXGBE_NOT_IMPLEMENTED); 660 } 661 662 /** 663 * ixgbe_set_phy_power - Control the phy power state 664 * @hw: pointer to hardware structure 665 * @on: true for on, false for off 666 */ 667 s32 ixgbe_set_phy_power(struct ixgbe_hw *hw, bool on) 668 { 669 return ixgbe_call_func(hw, hw->phy.ops.set_phy_power, (hw, on), 670 IXGBE_NOT_IMPLEMENTED); 671 } 672 673 /** 674 * ixgbe_check_link - Get link and speed status 675 * @hw: pointer to hardware structure 676 * @speed: pointer to link speed 677 * @link_up: true when link is up 678 * @link_up_wait_to_complete: bool used to wait for link up or not 679 * 680 * Reads the links register to determine if link is up and the current speed 681 **/ 682 s32 ixgbe_check_link(struct ixgbe_hw *hw, ixgbe_link_speed *speed, 683 bool *link_up, bool link_up_wait_to_complete) 684 { 685 return ixgbe_call_func(hw, hw->mac.ops.check_link, (hw, speed, 686 link_up, link_up_wait_to_complete), 687 IXGBE_NOT_IMPLEMENTED); 688 } 689 690 /** 691 * ixgbe_disable_tx_laser - Disable Tx laser 692 * @hw: pointer to hardware structure 693 * 694 * If the driver needs to disable the laser on SFI optics. 695 **/ 696 void ixgbe_disable_tx_laser(struct ixgbe_hw *hw) 697 { 698 if (hw->mac.ops.disable_tx_laser) 699 hw->mac.ops.disable_tx_laser(hw); 700 } 701 702 /** 703 * ixgbe_enable_tx_laser - Enable Tx laser 704 * @hw: pointer to hardware structure 705 * 706 * If the driver needs to enable the laser on SFI optics. 707 **/ 708 void ixgbe_enable_tx_laser(struct ixgbe_hw *hw) 709 { 710 if (hw->mac.ops.enable_tx_laser) 711 hw->mac.ops.enable_tx_laser(hw); 712 } 713 714 /** 715 * ixgbe_flap_tx_laser - flap Tx laser to start autotry process 716 * @hw: pointer to hardware structure 717 * 718 * When the driver changes the link speeds that it can support then 719 * flap the tx laser to alert the link partner to start autotry 720 * process on its end. 721 **/ 722 void ixgbe_flap_tx_laser(struct ixgbe_hw *hw) 723 { 724 if (hw->mac.ops.flap_tx_laser) 725 hw->mac.ops.flap_tx_laser(hw); 726 } 727 728 /** 729 * ixgbe_setup_link - Set link speed 730 * @hw: pointer to hardware structure 731 * @speed: new link speed 732 * @autoneg_wait_to_complete: true when waiting for completion is needed 733 * 734 * Configures link settings. Restarts the link. 735 * Performs autonegotiation if needed. 736 **/ 737 s32 ixgbe_setup_link(struct ixgbe_hw *hw, ixgbe_link_speed speed, 738 bool autoneg_wait_to_complete) 739 { 740 return ixgbe_call_func(hw, hw->mac.ops.setup_link, (hw, speed, 741 autoneg_wait_to_complete), 742 IXGBE_NOT_IMPLEMENTED); 743 } 744 745 /** 746 * ixgbe_setup_mac_link - Set link speed 747 * @hw: pointer to hardware structure 748 * @speed: new link speed 749 * @autoneg_wait_to_complete: true when waiting for completion is needed 750 * 751 * Configures link settings. Restarts the link. 752 * Performs autonegotiation if needed. 753 **/ 754 s32 ixgbe_setup_mac_link(struct ixgbe_hw *hw, ixgbe_link_speed speed, 755 bool autoneg_wait_to_complete) 756 { 757 return ixgbe_call_func(hw, hw->mac.ops.setup_mac_link, (hw, speed, 758 autoneg_wait_to_complete), 759 IXGBE_NOT_IMPLEMENTED); 760 } 761 762 /** 763 * ixgbe_get_link_capabilities - Returns link capabilities 764 * @hw: pointer to hardware structure 765 * @speed: link speed capabilities 766 * @autoneg: true when autoneg or autotry is enabled 767 * 768 * Determines the link capabilities of the current configuration. 769 **/ 770 s32 ixgbe_get_link_capabilities(struct ixgbe_hw *hw, ixgbe_link_speed *speed, 771 bool *autoneg) 772 { 773 return ixgbe_call_func(hw, hw->mac.ops.get_link_capabilities, (hw, 774 speed, autoneg), IXGBE_NOT_IMPLEMENTED); 775 } 776 777 /** 778 * ixgbe_led_on - Turn on LEDs 779 * @hw: pointer to hardware structure 780 * @index: led number to turn on 781 * 782 * Turns on the software controllable LEDs. 783 **/ 784 s32 ixgbe_led_on(struct ixgbe_hw *hw, u32 index) 785 { 786 return ixgbe_call_func(hw, hw->mac.ops.led_on, (hw, index), 787 IXGBE_NOT_IMPLEMENTED); 788 } 789 790 /** 791 * ixgbe_led_off - Turn off LEDs 792 * @hw: pointer to hardware structure 793 * @index: led number to turn off 794 * 795 * Turns off the software controllable LEDs. 796 **/ 797 s32 ixgbe_led_off(struct ixgbe_hw *hw, u32 index) 798 { 799 return ixgbe_call_func(hw, hw->mac.ops.led_off, (hw, index), 800 IXGBE_NOT_IMPLEMENTED); 801 } 802 803 /** 804 * ixgbe_blink_led_start - Blink LEDs 805 * @hw: pointer to hardware structure 806 * @index: led number to blink 807 * 808 * Blink LED based on index. 809 **/ 810 s32 ixgbe_blink_led_start(struct ixgbe_hw *hw, u32 index) 811 { 812 return ixgbe_call_func(hw, hw->mac.ops.blink_led_start, (hw, index), 813 IXGBE_NOT_IMPLEMENTED); 814 } 815 816 /** 817 * ixgbe_blink_led_stop - Stop blinking LEDs 818 * @hw: pointer to hardware structure 819 * @index: led number to stop 820 * 821 * Stop blinking LED based on index. 822 **/ 823 s32 ixgbe_blink_led_stop(struct ixgbe_hw *hw, u32 index) 824 { 825 return ixgbe_call_func(hw, hw->mac.ops.blink_led_stop, (hw, index), 826 IXGBE_NOT_IMPLEMENTED); 827 } 828 829 /** 830 * ixgbe_init_eeprom_params - Initialize EEPROM parameters 831 * @hw: pointer to hardware structure 832 * 833 * Initializes the EEPROM parameters ixgbe_eeprom_info within the 834 * ixgbe_hw struct in order to set up EEPROM access. 835 **/ 836 s32 ixgbe_init_eeprom_params(struct ixgbe_hw *hw) 837 { 838 return ixgbe_call_func(hw, hw->eeprom.ops.init_params, (hw), 839 IXGBE_NOT_IMPLEMENTED); 840 } 841 842 843 /** 844 * ixgbe_write_eeprom - Write word to EEPROM 845 * @hw: pointer to hardware structure 846 * @offset: offset within the EEPROM to be written to 847 * @data: 16 bit word to be written to the EEPROM 848 * 849 * Writes 16 bit value to EEPROM. If ixgbe_eeprom_update_checksum is not 850 * called after this function, the EEPROM will most likely contain an 851 * invalid checksum. 852 **/ 853 s32 ixgbe_write_eeprom(struct ixgbe_hw *hw, u16 offset, u16 data) 854 { 855 return ixgbe_call_func(hw, hw->eeprom.ops.write, (hw, offset, data), 856 IXGBE_NOT_IMPLEMENTED); 857 } 858 859 /** 860 * ixgbe_write_eeprom_buffer - Write word(s) to EEPROM 861 * @hw: pointer to hardware structure 862 * @offset: offset within the EEPROM to be written to 863 * @data: 16 bit word(s) to be written to the EEPROM 864 * @words: number of words 865 * 866 * Writes 16 bit word(s) to EEPROM. If ixgbe_eeprom_update_checksum is not 867 * called after this function, the EEPROM will most likely contain an 868 * invalid checksum. 869 **/ 870 s32 ixgbe_write_eeprom_buffer(struct ixgbe_hw *hw, u16 offset, u16 words, 871 u16 *data) 872 { 873 return ixgbe_call_func(hw, hw->eeprom.ops.write_buffer, 874 (hw, offset, words, data), 875 IXGBE_NOT_IMPLEMENTED); 876 } 877 878 /** 879 * ixgbe_read_eeprom - Read word from EEPROM 880 * @hw: pointer to hardware structure 881 * @offset: offset within the EEPROM to be read 882 * @data: read 16 bit value from EEPROM 883 * 884 * Reads 16 bit value from EEPROM 885 **/ 886 s32 ixgbe_read_eeprom(struct ixgbe_hw *hw, u16 offset, u16 *data) 887 { 888 return ixgbe_call_func(hw, hw->eeprom.ops.read, (hw, offset, data), 889 IXGBE_NOT_IMPLEMENTED); 890 } 891 892 /** 893 * ixgbe_read_eeprom_buffer - Read word(s) from EEPROM 894 * @hw: pointer to hardware structure 895 * @offset: offset within the EEPROM to be read 896 * @data: read 16 bit word(s) from EEPROM 897 * @words: number of words 898 * 899 * Reads 16 bit word(s) from EEPROM 900 **/ 901 s32 ixgbe_read_eeprom_buffer(struct ixgbe_hw *hw, u16 offset, 902 u16 words, u16 *data) 903 { 904 return ixgbe_call_func(hw, hw->eeprom.ops.read_buffer, 905 (hw, offset, words, data), 906 IXGBE_NOT_IMPLEMENTED); 907 } 908 909 /** 910 * ixgbe_validate_eeprom_checksum - Validate EEPROM checksum 911 * @hw: pointer to hardware structure 912 * @checksum_val: calculated checksum 913 * 914 * Performs checksum calculation and validates the EEPROM checksum 915 **/ 916 s32 ixgbe_validate_eeprom_checksum(struct ixgbe_hw *hw, u16 *checksum_val) 917 { 918 return ixgbe_call_func(hw, hw->eeprom.ops.validate_checksum, 919 (hw, checksum_val), IXGBE_NOT_IMPLEMENTED); 920 } 921 922 /** 923 * ixgbe_update_eeprom_checksum - Updates the EEPROM checksum 924 * @hw: pointer to hardware structure 925 **/ 926 s32 ixgbe_update_eeprom_checksum(struct ixgbe_hw *hw) 927 { 928 return ixgbe_call_func(hw, hw->eeprom.ops.update_checksum, (hw), 929 IXGBE_NOT_IMPLEMENTED); 930 } 931 932 /** 933 * ixgbe_insert_mac_addr - Find a RAR for this mac address 934 * @hw: pointer to hardware structure 935 * @addr: Address to put into receive address register 936 * @vmdq: VMDq pool to assign 937 * 938 * Puts an ethernet address into a receive address register, or 939 * finds the rar that it is already in; adds to the pool list 940 **/ 941 s32 ixgbe_insert_mac_addr(struct ixgbe_hw *hw, u8 *addr, u32 vmdq) 942 { 943 return ixgbe_call_func(hw, hw->mac.ops.insert_mac_addr, 944 (hw, addr, vmdq), 945 IXGBE_NOT_IMPLEMENTED); 946 } 947 948 /** 949 * ixgbe_set_rar - Set Rx address register 950 * @hw: pointer to hardware structure 951 * @index: Receive address register to write 952 * @addr: Address to put into receive address register 953 * @vmdq: VMDq "set" 954 * @enable_addr: set flag that address is active 955 * 956 * Puts an ethernet address into a receive address register. 957 **/ 958 s32 ixgbe_set_rar(struct ixgbe_hw *hw, u32 index, u8 *addr, u32 vmdq, 959 u32 enable_addr) 960 { 961 return ixgbe_call_func(hw, hw->mac.ops.set_rar, (hw, index, addr, vmdq, 962 enable_addr), IXGBE_NOT_IMPLEMENTED); 963 } 964 965 /** 966 * ixgbe_clear_rar - Clear Rx address register 967 * @hw: pointer to hardware structure 968 * @index: Receive address register to write 969 * 970 * Puts an ethernet address into a receive address register. 971 **/ 972 s32 ixgbe_clear_rar(struct ixgbe_hw *hw, u32 index) 973 { 974 return ixgbe_call_func(hw, hw->mac.ops.clear_rar, (hw, index), 975 IXGBE_NOT_IMPLEMENTED); 976 } 977 978 /** 979 * ixgbe_set_vmdq - Associate a VMDq index with a receive address 980 * @hw: pointer to hardware structure 981 * @rar: receive address register index to associate with VMDq index 982 * @vmdq: VMDq set or pool index 983 **/ 984 s32 ixgbe_set_vmdq(struct ixgbe_hw *hw, u32 rar, u32 vmdq) 985 { 986 return ixgbe_call_func(hw, hw->mac.ops.set_vmdq, (hw, rar, vmdq), 987 IXGBE_NOT_IMPLEMENTED); 988 989 } 990 991 /** 992 * ixgbe_set_vmdq_san_mac - Associate VMDq index 127 with a receive address 993 * @hw: pointer to hardware structure 994 * @vmdq: VMDq default pool index 995 **/ 996 s32 ixgbe_set_vmdq_san_mac(struct ixgbe_hw *hw, u32 vmdq) 997 { 998 return ixgbe_call_func(hw, hw->mac.ops.set_vmdq_san_mac, 999 (hw, vmdq), IXGBE_NOT_IMPLEMENTED); 1000 } 1001 1002 /** 1003 * ixgbe_clear_vmdq - Disassociate a VMDq index from a receive address 1004 * @hw: pointer to hardware structure 1005 * @rar: receive address register index to disassociate with VMDq index 1006 * @vmdq: VMDq set or pool index 1007 **/ 1008 s32 ixgbe_clear_vmdq(struct ixgbe_hw *hw, u32 rar, u32 vmdq) 1009 { 1010 return ixgbe_call_func(hw, hw->mac.ops.clear_vmdq, (hw, rar, vmdq), 1011 IXGBE_NOT_IMPLEMENTED); 1012 } 1013 1014 /** 1015 * ixgbe_init_rx_addrs - Initializes receive address filters. 1016 * @hw: pointer to hardware structure 1017 * 1018 * Places the MAC address in receive address register 0 and clears the rest 1019 * of the receive address registers. Clears the multicast table. Assumes 1020 * the receiver is in reset when the routine is called. 1021 **/ 1022 s32 ixgbe_init_rx_addrs(struct ixgbe_hw *hw) 1023 { 1024 return ixgbe_call_func(hw, hw->mac.ops.init_rx_addrs, (hw), 1025 IXGBE_NOT_IMPLEMENTED); 1026 } 1027 1028 /** 1029 * ixgbe_get_num_rx_addrs - Returns the number of RAR entries. 1030 * @hw: pointer to hardware structure 1031 **/ 1032 u32 ixgbe_get_num_rx_addrs(struct ixgbe_hw *hw) 1033 { 1034 return hw->mac.num_rar_entries; 1035 } 1036 1037 /** 1038 * ixgbe_update_uc_addr_list - Updates the MAC's list of secondary addresses 1039 * @hw: pointer to hardware structure 1040 * @addr_list: the list of new multicast addresses 1041 * @addr_count: number of addresses 1042 * @func: iterator function to walk the multicast address list 1043 * 1044 * The given list replaces any existing list. Clears the secondary addrs from 1045 * receive address registers. Uses unused receive address registers for the 1046 * first secondary addresses, and falls back to promiscuous mode as needed. 1047 **/ 1048 s32 ixgbe_update_uc_addr_list(struct ixgbe_hw *hw, u8 *addr_list, 1049 u32 addr_count, ixgbe_mc_addr_itr func) 1050 { 1051 return ixgbe_call_func(hw, hw->mac.ops.update_uc_addr_list, (hw, 1052 addr_list, addr_count, func), 1053 IXGBE_NOT_IMPLEMENTED); 1054 } 1055 1056 /** 1057 * ixgbe_update_mc_addr_list - Updates the MAC's list of multicast addresses 1058 * @hw: pointer to hardware structure 1059 * @mc_addr_list: the list of new multicast addresses 1060 * @mc_addr_count: number of addresses 1061 * @func: iterator function to walk the multicast address list 1062 * @clear: flag, when set clears the table beforehand 1063 * 1064 * The given list replaces any existing list. Clears the MC addrs from receive 1065 * address registers and the multicast table. Uses unused receive address 1066 * registers for the first multicast addresses, and hashes the rest into the 1067 * multicast table. 1068 **/ 1069 s32 ixgbe_update_mc_addr_list(struct ixgbe_hw *hw, u8 *mc_addr_list, 1070 u32 mc_addr_count, ixgbe_mc_addr_itr func, 1071 bool clear) 1072 { 1073 return ixgbe_call_func(hw, hw->mac.ops.update_mc_addr_list, (hw, 1074 mc_addr_list, mc_addr_count, func, clear), 1075 IXGBE_NOT_IMPLEMENTED); 1076 } 1077 1078 /** 1079 * ixgbe_enable_mc - Enable multicast address in RAR 1080 * @hw: pointer to hardware structure 1081 * 1082 * Enables multicast address in RAR and the use of the multicast hash table. 1083 **/ 1084 s32 ixgbe_enable_mc(struct ixgbe_hw *hw) 1085 { 1086 return ixgbe_call_func(hw, hw->mac.ops.enable_mc, (hw), 1087 IXGBE_NOT_IMPLEMENTED); 1088 } 1089 1090 /** 1091 * ixgbe_disable_mc - Disable multicast address in RAR 1092 * @hw: pointer to hardware structure 1093 * 1094 * Disables multicast address in RAR and the use of the multicast hash table. 1095 **/ 1096 s32 ixgbe_disable_mc(struct ixgbe_hw *hw) 1097 { 1098 return ixgbe_call_func(hw, hw->mac.ops.disable_mc, (hw), 1099 IXGBE_NOT_IMPLEMENTED); 1100 } 1101 1102 /** 1103 * ixgbe_clear_vfta - Clear VLAN filter table 1104 * @hw: pointer to hardware structure 1105 * 1106 * Clears the VLAN filter table, and the VMDq index associated with the filter 1107 **/ 1108 s32 ixgbe_clear_vfta(struct ixgbe_hw *hw) 1109 { 1110 return ixgbe_call_func(hw, hw->mac.ops.clear_vfta, (hw), 1111 IXGBE_NOT_IMPLEMENTED); 1112 } 1113 1114 /** 1115 * ixgbe_set_vfta - Set VLAN filter table 1116 * @hw: pointer to hardware structure 1117 * @vlan: VLAN id to write to VLAN filter 1118 * @vind: VMDq output index that maps queue to VLAN id in VLVFB 1119 * @vlan_on: boolean flag to turn on/off VLAN 1120 * @vlvf_bypass: boolean flag indicating updating the default pool is okay 1121 * 1122 * Turn on/off specified VLAN in the VLAN filter table. 1123 **/ 1124 s32 ixgbe_set_vfta(struct ixgbe_hw *hw, u32 vlan, u32 vind, bool vlan_on, 1125 bool vlvf_bypass) 1126 { 1127 return ixgbe_call_func(hw, hw->mac.ops.set_vfta, (hw, vlan, vind, 1128 vlan_on, vlvf_bypass), IXGBE_NOT_IMPLEMENTED); 1129 } 1130 1131 /** 1132 * ixgbe_set_vlvf - Set VLAN Pool Filter 1133 * @hw: pointer to hardware structure 1134 * @vlan: VLAN id to write to VLAN filter 1135 * @vind: VMDq output index that maps queue to VLAN id in VLVFB 1136 * @vlan_on: boolean flag to turn on/off VLAN in VLVF 1137 * @vfta_delta: pointer to the difference between the current value of VFTA 1138 * and the desired value 1139 * @vfta: the desired value of the VFTA 1140 * @vlvf_bypass: boolean flag indicating updating the default pool is okay 1141 * 1142 * Turn on/off specified bit in VLVF table. 1143 **/ 1144 s32 ixgbe_set_vlvf(struct ixgbe_hw *hw, u32 vlan, u32 vind, bool vlan_on, 1145 u32 *vfta_delta, u32 vfta, bool vlvf_bypass) 1146 { 1147 return ixgbe_call_func(hw, hw->mac.ops.set_vlvf, (hw, vlan, vind, 1148 vlan_on, vfta_delta, vfta, vlvf_bypass), 1149 IXGBE_NOT_IMPLEMENTED); 1150 } 1151 1152 /** 1153 * ixgbe_toggle_txdctl - Toggle VF's queues 1154 * @hw: pointer to hardware structure 1155 * @vind: VMDq pool index 1156 * 1157 * Enable and disable each queue in VF. 1158 */ 1159 s32 ixgbe_toggle_txdctl(struct ixgbe_hw *hw, u32 vind) 1160 { 1161 return ixgbe_call_func(hw, hw->mac.ops.toggle_txdctl, (hw, 1162 vind), IXGBE_NOT_IMPLEMENTED); 1163 } 1164 1165 /** 1166 * ixgbe_fc_enable - Enable flow control 1167 * @hw: pointer to hardware structure 1168 * 1169 * Configures the flow control settings based on SW configuration. 1170 **/ 1171 s32 ixgbe_fc_enable(struct ixgbe_hw *hw) 1172 { 1173 return ixgbe_call_func(hw, hw->mac.ops.fc_enable, (hw), 1174 IXGBE_NOT_IMPLEMENTED); 1175 } 1176 1177 /** 1178 * ixgbe_setup_fc - Set up flow control 1179 * @hw: pointer to hardware structure 1180 * 1181 * Called at init time to set up flow control. 1182 **/ 1183 s32 ixgbe_setup_fc(struct ixgbe_hw *hw) 1184 { 1185 return ixgbe_call_func(hw, hw->mac.ops.setup_fc, (hw), 1186 IXGBE_NOT_IMPLEMENTED); 1187 } 1188 1189 /** 1190 * ixgbe_set_fw_drv_ver - Try to send the driver version number FW 1191 * @hw: pointer to hardware structure 1192 * @maj: driver major number to be sent to firmware 1193 * @min: driver minor number to be sent to firmware 1194 * @build: driver build number to be sent to firmware 1195 * @ver: driver version number to be sent to firmware 1196 * @len: length of driver_ver string 1197 * @driver_ver: driver string 1198 **/ 1199 s32 ixgbe_set_fw_drv_ver(struct ixgbe_hw *hw, u8 maj, u8 min, u8 build, 1200 u8 ver, u16 len, char *driver_ver) 1201 { 1202 return ixgbe_call_func(hw, hw->mac.ops.set_fw_drv_ver, (hw, maj, min, 1203 build, ver, len, driver_ver), 1204 IXGBE_NOT_IMPLEMENTED); 1205 } 1206 1207 1208 /** 1209 * ixgbe_get_thermal_sensor_data - Gathers thermal sensor data 1210 * @hw: pointer to hardware structure 1211 * 1212 * Updates the temperatures in mac.thermal_sensor_data 1213 **/ 1214 s32 ixgbe_get_thermal_sensor_data(struct ixgbe_hw *hw) 1215 { 1216 return ixgbe_call_func(hw, hw->mac.ops.get_thermal_sensor_data, (hw), 1217 IXGBE_NOT_IMPLEMENTED); 1218 } 1219 1220 /** 1221 * ixgbe_init_thermal_sensor_thresh - Inits thermal sensor thresholds 1222 * @hw: pointer to hardware structure 1223 * 1224 * Inits the thermal sensor thresholds according to the NVM map 1225 **/ 1226 s32 ixgbe_init_thermal_sensor_thresh(struct ixgbe_hw *hw) 1227 { 1228 return ixgbe_call_func(hw, hw->mac.ops.init_thermal_sensor_thresh, (hw), 1229 IXGBE_NOT_IMPLEMENTED); 1230 } 1231 1232 /** 1233 * ixgbe_dmac_config - Configure DMA Coalescing registers. 1234 * @hw: pointer to hardware structure 1235 * 1236 * Configure DMA coalescing. If enabling dmac, dmac is activated. 1237 * When disabling dmac, dmac enable dmac bit is cleared. 1238 **/ 1239 s32 ixgbe_dmac_config(struct ixgbe_hw *hw) 1240 { 1241 return ixgbe_call_func(hw, hw->mac.ops.dmac_config, (hw), 1242 IXGBE_NOT_IMPLEMENTED); 1243 } 1244 1245 /** 1246 * ixgbe_dmac_update_tcs - Configure DMA Coalescing registers. 1247 * @hw: pointer to hardware structure 1248 * 1249 * Disables dmac, updates per TC settings, and then enable dmac. 1250 **/ 1251 s32 ixgbe_dmac_update_tcs(struct ixgbe_hw *hw) 1252 { 1253 return ixgbe_call_func(hw, hw->mac.ops.dmac_update_tcs, (hw), 1254 IXGBE_NOT_IMPLEMENTED); 1255 } 1256 1257 /** 1258 * ixgbe_dmac_config_tcs - Configure DMA Coalescing registers. 1259 * @hw: pointer to hardware structure 1260 * 1261 * Configure DMA coalescing threshold per TC and set high priority bit for 1262 * FCOE TC. The dmac enable bit must be cleared before configuring. 1263 **/ 1264 s32 ixgbe_dmac_config_tcs(struct ixgbe_hw *hw) 1265 { 1266 return ixgbe_call_func(hw, hw->mac.ops.dmac_config_tcs, (hw), 1267 IXGBE_NOT_IMPLEMENTED); 1268 } 1269 1270 /** 1271 * ixgbe_setup_eee - Enable/disable EEE support 1272 * @hw: pointer to the HW structure 1273 * @enable_eee: boolean flag to enable EEE 1274 * 1275 * Enable/disable EEE based on enable_ee flag. 1276 * Auto-negotiation must be started after BASE-T EEE bits in PHY register 7.3C 1277 * are modified. 1278 * 1279 **/ 1280 s32 ixgbe_setup_eee(struct ixgbe_hw *hw, bool enable_eee) 1281 { 1282 return ixgbe_call_func(hw, hw->mac.ops.setup_eee, (hw, enable_eee), 1283 IXGBE_NOT_IMPLEMENTED); 1284 } 1285 1286 /** 1287 * ixgbe_set_source_address_pruning - Enable/Disable source address pruning 1288 * @hw: pointer to hardware structure 1289 * @enable: enable or disable source address pruning 1290 * @pool: Rx pool - Rx pool to toggle source address pruning 1291 **/ 1292 void ixgbe_set_source_address_pruning(struct ixgbe_hw *hw, bool enable, 1293 unsigned int pool) 1294 { 1295 if (hw->mac.ops.set_source_address_pruning) 1296 hw->mac.ops.set_source_address_pruning(hw, enable, pool); 1297 } 1298 1299 /** 1300 * ixgbe_set_ethertype_anti_spoofing - Enable/Disable Ethertype anti-spoofing 1301 * @hw: pointer to hardware structure 1302 * @enable: enable or disable switch for Ethertype anti-spoofing 1303 * @vf: Virtual Function pool - VF Pool to set for Ethertype anti-spoofing 1304 * 1305 **/ 1306 void ixgbe_set_ethertype_anti_spoofing(struct ixgbe_hw *hw, bool enable, int vf) 1307 { 1308 if (hw->mac.ops.set_ethertype_anti_spoofing) 1309 hw->mac.ops.set_ethertype_anti_spoofing(hw, enable, vf); 1310 } 1311 1312 /** 1313 * ixgbe_read_iosf_sb_reg - Read 32 bit PHY register 1314 * @hw: pointer to hardware structure 1315 * @reg_addr: 32 bit address of PHY register to read 1316 * @device_type: type of device you want to communicate with 1317 * @phy_data: Pointer to read data from PHY register 1318 * 1319 * Reads a value from a specified PHY register 1320 **/ 1321 s32 ixgbe_read_iosf_sb_reg(struct ixgbe_hw *hw, u32 reg_addr, 1322 u32 device_type, u32 *phy_data) 1323 { 1324 return ixgbe_call_func(hw, hw->mac.ops.read_iosf_sb_reg, (hw, reg_addr, 1325 device_type, phy_data), IXGBE_NOT_IMPLEMENTED); 1326 } 1327 1328 /** 1329 * ixgbe_write_iosf_sb_reg - Write 32 bit register through IOSF Sideband 1330 * @hw: pointer to hardware structure 1331 * @reg_addr: 32 bit PHY register to write 1332 * @device_type: type of device you want to communicate with 1333 * @phy_data: Data to write to the PHY register 1334 * 1335 * Writes a value to specified PHY register 1336 **/ 1337 s32 ixgbe_write_iosf_sb_reg(struct ixgbe_hw *hw, u32 reg_addr, 1338 u32 device_type, u32 phy_data) 1339 { 1340 return ixgbe_call_func(hw, hw->mac.ops.write_iosf_sb_reg, (hw, reg_addr, 1341 device_type, phy_data), IXGBE_NOT_IMPLEMENTED); 1342 } 1343 1344 /** 1345 * ixgbe_disable_mdd - Disable malicious driver detection 1346 * @hw: pointer to hardware structure 1347 * 1348 **/ 1349 void ixgbe_disable_mdd(struct ixgbe_hw *hw) 1350 { 1351 if (hw->mac.ops.disable_mdd) 1352 hw->mac.ops.disable_mdd(hw); 1353 } 1354 1355 /** 1356 * ixgbe_enable_mdd - Enable malicious driver detection 1357 * @hw: pointer to hardware structure 1358 * 1359 **/ 1360 void ixgbe_enable_mdd(struct ixgbe_hw *hw) 1361 { 1362 if (hw->mac.ops.enable_mdd) 1363 hw->mac.ops.enable_mdd(hw); 1364 } 1365 1366 /** 1367 * ixgbe_mdd_event - Handle malicious driver detection event 1368 * @hw: pointer to hardware structure 1369 * @vf_bitmap: vf bitmap of malicious vfs 1370 * 1371 **/ 1372 void ixgbe_mdd_event(struct ixgbe_hw *hw, u32 *vf_bitmap) 1373 { 1374 if (hw->mac.ops.mdd_event) 1375 hw->mac.ops.mdd_event(hw, vf_bitmap); 1376 } 1377 1378 /** 1379 * ixgbe_restore_mdd_vf - Restore VF that was disabled during malicious driver 1380 * detection event 1381 * @hw: pointer to hardware structure 1382 * @vf: vf index 1383 * 1384 **/ 1385 void ixgbe_restore_mdd_vf(struct ixgbe_hw *hw, u32 vf) 1386 { 1387 if (hw->mac.ops.restore_mdd_vf) 1388 hw->mac.ops.restore_mdd_vf(hw, vf); 1389 } 1390 1391 /** 1392 * ixgbe_fw_recovery_mode - Check if in FW NVM recovery mode 1393 * @hw: pointer to hardware structure 1394 * 1395 **/ 1396 bool ixgbe_fw_recovery_mode(struct ixgbe_hw *hw) 1397 { 1398 if (hw->mac.ops.fw_recovery_mode) 1399 return hw->mac.ops.fw_recovery_mode(hw); 1400 return false; 1401 } 1402 1403 /** 1404 * ixgbe_enter_lplu - Transition to low power states 1405 * @hw: pointer to hardware structure 1406 * 1407 * Configures Low Power Link Up on transition to low power states 1408 * (from D0 to non-D0). 1409 **/ 1410 s32 ixgbe_enter_lplu(struct ixgbe_hw *hw) 1411 { 1412 return ixgbe_call_func(hw, hw->phy.ops.enter_lplu, (hw), 1413 IXGBE_NOT_IMPLEMENTED); 1414 } 1415 1416 /** 1417 * ixgbe_handle_lasi - Handle external Base T PHY interrupt 1418 * @hw: pointer to hardware structure 1419 * 1420 * Handle external Base T PHY interrupt. If high temperature 1421 * failure alarm then return error, else if link status change 1422 * then setup internal/external PHY link 1423 * 1424 * Return IXGBE_ERR_OVERTEMP if interrupt is high temperature 1425 * failure alarm, else return PHY access status. 1426 */ 1427 s32 ixgbe_handle_lasi(struct ixgbe_hw *hw) 1428 { 1429 return ixgbe_call_func(hw, hw->phy.ops.handle_lasi, (hw), 1430 IXGBE_NOT_IMPLEMENTED); 1431 } 1432 1433 /** 1434 * ixgbe_bypass_rw - Bit bang data into by_pass FW 1435 * @hw: pointer to hardware structure 1436 * @cmd: Command we send to the FW 1437 * @status: The reply from the FW 1438 * 1439 * Bit-bangs the cmd to the by_pass FW status points to what is returned. 1440 **/ 1441 s32 ixgbe_bypass_rw(struct ixgbe_hw *hw, u32 cmd, u32 *status) 1442 { 1443 return ixgbe_call_func(hw, hw->mac.ops.bypass_rw, (hw, cmd, status), 1444 IXGBE_NOT_IMPLEMENTED); 1445 } 1446 1447 /** 1448 * ixgbe_bypass_valid_rd - Verify valid return from bit-bang. 1449 * @hw: pointer to hardware structure 1450 * @in_reg: The register cmd for the bit-bang read. 1451 * @out_reg: The register returned from a bit-bang read. 1452 * 1453 * If we send a write we can't be sure it took until we can read back 1454 * that same register. It can be a problem as some of the fields may 1455 * for valid reasons change inbetween the time wrote the register and 1456 * we read it again to verify. So this function check everything we 1457 * can check and then assumes it worked. 1458 **/ 1459 bool ixgbe_bypass_valid_rd(struct ixgbe_hw *hw, u32 in_reg, u32 out_reg) 1460 { 1461 return ixgbe_call_func(hw, hw->mac.ops.bypass_valid_rd, 1462 (in_reg, out_reg), IXGBE_NOT_IMPLEMENTED); 1463 } 1464 1465 /** 1466 * ixgbe_bypass_set - Set a bypass field in the FW CTRL Regiter. 1467 * @hw: pointer to hardware structure 1468 * @cmd: The control word we are setting. 1469 * @event: The event we are setting in the FW. This also happens to 1470 * be the mask for the event we are setting (handy) 1471 * @action: The action we set the event to in the FW. This is in a 1472 * bit field that happens to be what we want to put in 1473 * the event spot (also handy) 1474 * 1475 * Writes to the cmd control the bits in actions. 1476 **/ 1477 s32 ixgbe_bypass_set(struct ixgbe_hw *hw, u32 cmd, u32 event, u32 action) 1478 { 1479 return ixgbe_call_func(hw, hw->mac.ops.bypass_set, 1480 (hw, cmd, event, action), 1481 IXGBE_NOT_IMPLEMENTED); 1482 } 1483 1484 /** 1485 * ixgbe_bypass_rd_eep - Read the bypass FW eeprom address 1486 * @hw: pointer to hardware structure 1487 * @addr: The bypass eeprom address to read. 1488 * @value: The 8b of data at the address above. 1489 **/ 1490 s32 ixgbe_bypass_rd_eep(struct ixgbe_hw *hw, u32 addr, u8 *value) 1491 { 1492 return ixgbe_call_func(hw, hw->mac.ops.bypass_rd_eep, 1493 (hw, addr, value), IXGBE_NOT_IMPLEMENTED); 1494 } 1495 1496 /** 1497 * ixgbe_read_analog_reg8 - Reads 8 bit analog register 1498 * @hw: pointer to hardware structure 1499 * @reg: analog register to read 1500 * @val: read value 1501 * 1502 * Performs write operation to analog register specified. 1503 **/ 1504 s32 ixgbe_read_analog_reg8(struct ixgbe_hw *hw, u32 reg, u8 *val) 1505 { 1506 return ixgbe_call_func(hw, hw->mac.ops.read_analog_reg8, (hw, reg, 1507 val), IXGBE_NOT_IMPLEMENTED); 1508 } 1509 1510 /** 1511 * ixgbe_write_analog_reg8 - Writes 8 bit analog register 1512 * @hw: pointer to hardware structure 1513 * @reg: analog register to write 1514 * @val: value to write 1515 * 1516 * Performs write operation to Atlas analog register specified. 1517 **/ 1518 s32 ixgbe_write_analog_reg8(struct ixgbe_hw *hw, u32 reg, u8 val) 1519 { 1520 return ixgbe_call_func(hw, hw->mac.ops.write_analog_reg8, (hw, reg, 1521 val), IXGBE_NOT_IMPLEMENTED); 1522 } 1523 1524 /** 1525 * ixgbe_init_uta_tables - Initializes Unicast Table Arrays. 1526 * @hw: pointer to hardware structure 1527 * 1528 * Initializes the Unicast Table Arrays to zero on device load. This 1529 * is part of the Rx init addr execution path. 1530 **/ 1531 s32 ixgbe_init_uta_tables(struct ixgbe_hw *hw) 1532 { 1533 return ixgbe_call_func(hw, hw->mac.ops.init_uta_tables, (hw), 1534 IXGBE_NOT_IMPLEMENTED); 1535 } 1536 1537 /** 1538 * ixgbe_read_i2c_byte - Reads 8 bit word over I2C at specified device address 1539 * @hw: pointer to hardware structure 1540 * @byte_offset: byte offset to read 1541 * @dev_addr: I2C bus address to read from 1542 * @data: value read 1543 * 1544 * Performs byte read operation to SFP module's EEPROM over I2C interface. 1545 **/ 1546 s32 ixgbe_read_i2c_byte(struct ixgbe_hw *hw, u8 byte_offset, u8 dev_addr, 1547 u8 *data) 1548 { 1549 return ixgbe_call_func(hw, hw->phy.ops.read_i2c_byte, (hw, byte_offset, 1550 dev_addr, data), IXGBE_NOT_IMPLEMENTED); 1551 } 1552 1553 /** 1554 * ixgbe_read_i2c_byte_unlocked - Reads 8 bit word via I2C from device address 1555 * @hw: pointer to hardware structure 1556 * @byte_offset: byte offset to read 1557 * @dev_addr: I2C bus address to read from 1558 * @data: value read 1559 * 1560 * Performs byte read operation to SFP module's EEPROM over I2C interface. 1561 **/ 1562 s32 ixgbe_read_i2c_byte_unlocked(struct ixgbe_hw *hw, u8 byte_offset, 1563 u8 dev_addr, u8 *data) 1564 { 1565 return ixgbe_call_func(hw, hw->phy.ops.read_i2c_byte_unlocked, 1566 (hw, byte_offset, dev_addr, data), 1567 IXGBE_NOT_IMPLEMENTED); 1568 } 1569 1570 /** 1571 * ixgbe_read_link - Perform read operation on link device 1572 * @hw: pointer to the hardware structure 1573 * @addr: bus address to read from 1574 * @reg: device register to read from 1575 * @val: pointer to location to receive read value 1576 * 1577 * Returns an error code on error. 1578 */ 1579 s32 ixgbe_read_link(struct ixgbe_hw *hw, u8 addr, u16 reg, u16 *val) 1580 { 1581 return ixgbe_call_func(hw, hw->link.ops.read_link, (hw, addr, 1582 reg, val), IXGBE_NOT_IMPLEMENTED); 1583 } 1584 1585 /** 1586 * ixgbe_read_link_unlocked - Perform read operation on link device 1587 * @hw: pointer to the hardware structure 1588 * @addr: bus address to read from 1589 * @reg: device register to read from 1590 * @val: pointer to location to receive read value 1591 * 1592 * Returns an error code on error. 1593 **/ 1594 s32 ixgbe_read_link_unlocked(struct ixgbe_hw *hw, u8 addr, u16 reg, u16 *val) 1595 { 1596 return ixgbe_call_func(hw, hw->link.ops.read_link_unlocked, 1597 (hw, addr, reg, val), IXGBE_NOT_IMPLEMENTED); 1598 } 1599 1600 /** 1601 * ixgbe_write_i2c_byte - Writes 8 bit word over I2C 1602 * @hw: pointer to hardware structure 1603 * @byte_offset: byte offset to write 1604 * @dev_addr: I2C bus address to write to 1605 * @data: value to write 1606 * 1607 * Performs byte write operation to SFP module's EEPROM over I2C interface 1608 * at a specified device address. 1609 **/ 1610 s32 ixgbe_write_i2c_byte(struct ixgbe_hw *hw, u8 byte_offset, u8 dev_addr, 1611 u8 data) 1612 { 1613 return ixgbe_call_func(hw, hw->phy.ops.write_i2c_byte, (hw, byte_offset, 1614 dev_addr, data), IXGBE_NOT_IMPLEMENTED); 1615 } 1616 1617 /** 1618 * ixgbe_write_i2c_byte_unlocked - Writes 8 bit word over I2C 1619 * @hw: pointer to hardware structure 1620 * @byte_offset: byte offset to write 1621 * @dev_addr: I2C bus address to write to 1622 * @data: value to write 1623 * 1624 * Performs byte write operation to SFP module's EEPROM over I2C interface 1625 * at a specified device address. 1626 **/ 1627 s32 ixgbe_write_i2c_byte_unlocked(struct ixgbe_hw *hw, u8 byte_offset, 1628 u8 dev_addr, u8 data) 1629 { 1630 return ixgbe_call_func(hw, hw->phy.ops.write_i2c_byte_unlocked, 1631 (hw, byte_offset, dev_addr, data), 1632 IXGBE_NOT_IMPLEMENTED); 1633 } 1634 1635 /** 1636 * ixgbe_write_link - Perform write operation on link device 1637 * @hw: pointer to the hardware structure 1638 * @addr: bus address to write to 1639 * @reg: device register to write to 1640 * @val: value to write 1641 * 1642 * Returns an error code on error. 1643 */ 1644 s32 ixgbe_write_link(struct ixgbe_hw *hw, u8 addr, u16 reg, u16 val) 1645 { 1646 return ixgbe_call_func(hw, hw->link.ops.write_link, 1647 (hw, addr, reg, val), IXGBE_NOT_IMPLEMENTED); 1648 } 1649 1650 /** 1651 * ixgbe_write_link_unlocked - Perform write operation on link device 1652 * @hw: pointer to the hardware structure 1653 * @addr: bus address to write to 1654 * @reg: device register to write to 1655 * @val: value to write 1656 * 1657 * Returns an error code on error. 1658 **/ 1659 s32 ixgbe_write_link_unlocked(struct ixgbe_hw *hw, u8 addr, u16 reg, u16 val) 1660 { 1661 return ixgbe_call_func(hw, hw->link.ops.write_link_unlocked, 1662 (hw, addr, reg, val), IXGBE_NOT_IMPLEMENTED); 1663 } 1664 1665 /** 1666 * ixgbe_write_i2c_eeprom - Writes 8 bit EEPROM word over I2C interface 1667 * @hw: pointer to hardware structure 1668 * @byte_offset: EEPROM byte offset to write 1669 * @eeprom_data: value to write 1670 * 1671 * Performs byte write operation to SFP module's EEPROM over I2C interface. 1672 **/ 1673 s32 ixgbe_write_i2c_eeprom(struct ixgbe_hw *hw, 1674 u8 byte_offset, u8 eeprom_data) 1675 { 1676 return ixgbe_call_func(hw, hw->phy.ops.write_i2c_eeprom, 1677 (hw, byte_offset, eeprom_data), 1678 IXGBE_NOT_IMPLEMENTED); 1679 } 1680 1681 /** 1682 * ixgbe_read_i2c_eeprom - Reads 8 bit EEPROM word over I2C interface 1683 * @hw: pointer to hardware structure 1684 * @byte_offset: EEPROM byte offset to read 1685 * @eeprom_data: value read 1686 * 1687 * Performs byte read operation to SFP module's EEPROM over I2C interface. 1688 **/ 1689 s32 ixgbe_read_i2c_eeprom(struct ixgbe_hw *hw, u8 byte_offset, u8 *eeprom_data) 1690 { 1691 return ixgbe_call_func(hw, hw->phy.ops.read_i2c_eeprom, 1692 (hw, byte_offset, eeprom_data), 1693 IXGBE_NOT_IMPLEMENTED); 1694 } 1695 1696 /** 1697 * ixgbe_get_supported_physical_layer - Returns physical layer type 1698 * @hw: pointer to hardware structure 1699 * 1700 * Determines physical layer capabilities of the current configuration. 1701 **/ 1702 u64 ixgbe_get_supported_physical_layer(struct ixgbe_hw *hw) 1703 { 1704 return ixgbe_call_func(hw, hw->mac.ops.get_supported_physical_layer, 1705 (hw), IXGBE_PHYSICAL_LAYER_UNKNOWN); 1706 } 1707 1708 /** 1709 * ixgbe_enable_rx_dma - Enables Rx DMA unit, dependent on device specifics 1710 * @hw: pointer to hardware structure 1711 * @regval: bitfield to write to the Rx DMA register 1712 * 1713 * Enables the Rx DMA unit of the device. 1714 **/ 1715 s32 ixgbe_enable_rx_dma(struct ixgbe_hw *hw, u32 regval) 1716 { 1717 return ixgbe_call_func(hw, hw->mac.ops.enable_rx_dma, 1718 (hw, regval), IXGBE_NOT_IMPLEMENTED); 1719 } 1720 1721 /** 1722 * ixgbe_disable_sec_rx_path - Stops the receive data path 1723 * @hw: pointer to hardware structure 1724 * 1725 * Stops the receive data path. 1726 **/ 1727 s32 ixgbe_disable_sec_rx_path(struct ixgbe_hw *hw) 1728 { 1729 return ixgbe_call_func(hw, hw->mac.ops.disable_sec_rx_path, 1730 (hw), IXGBE_NOT_IMPLEMENTED); 1731 } 1732 1733 /** 1734 * ixgbe_enable_sec_rx_path - Enables the receive data path 1735 * @hw: pointer to hardware structure 1736 * 1737 * Enables the receive data path. 1738 **/ 1739 s32 ixgbe_enable_sec_rx_path(struct ixgbe_hw *hw) 1740 { 1741 return ixgbe_call_func(hw, hw->mac.ops.enable_sec_rx_path, 1742 (hw), IXGBE_NOT_IMPLEMENTED); 1743 } 1744 1745 /** 1746 * ixgbe_acquire_swfw_semaphore - Acquire SWFW semaphore 1747 * @hw: pointer to hardware structure 1748 * @mask: Mask to specify which semaphore to acquire 1749 * 1750 * Acquires the SWFW semaphore through SW_FW_SYNC register for the specified 1751 * function (CSR, PHY0, PHY1, EEPROM, Flash) 1752 **/ 1753 s32 ixgbe_acquire_swfw_semaphore(struct ixgbe_hw *hw, u32 mask) 1754 { 1755 return ixgbe_call_func(hw, hw->mac.ops.acquire_swfw_sync, 1756 (hw, mask), IXGBE_NOT_IMPLEMENTED); 1757 } 1758 1759 /** 1760 * ixgbe_release_swfw_semaphore - Release SWFW semaphore 1761 * @hw: pointer to hardware structure 1762 * @mask: Mask to specify which semaphore to release 1763 * 1764 * Releases the SWFW semaphore through SW_FW_SYNC register for the specified 1765 * function (CSR, PHY0, PHY1, EEPROM, Flash) 1766 **/ 1767 void ixgbe_release_swfw_semaphore(struct ixgbe_hw *hw, u32 mask) 1768 { 1769 if (hw->mac.ops.release_swfw_sync) 1770 hw->mac.ops.release_swfw_sync(hw, mask); 1771 } 1772 1773 /** 1774 * ixgbe_init_swfw_semaphore - Clean up SWFW semaphore 1775 * @hw: pointer to hardware structure 1776 * 1777 * Attempts to acquire the SWFW semaphore through SW_FW_SYNC register. 1778 * Regardless of whether is succeeds or not it then release the semaphore. 1779 * This is function is called to recover from catastrophic failures that 1780 * may have left the semaphore locked. 1781 **/ 1782 void ixgbe_init_swfw_semaphore(struct ixgbe_hw *hw) 1783 { 1784 if (hw->mac.ops.init_swfw_sync) 1785 hw->mac.ops.init_swfw_sync(hw); 1786 } 1787 1788 1789 void ixgbe_disable_rx(struct ixgbe_hw *hw) 1790 { 1791 if (hw->mac.ops.disable_rx) 1792 hw->mac.ops.disable_rx(hw); 1793 } 1794 1795 void ixgbe_enable_rx(struct ixgbe_hw *hw) 1796 { 1797 if (hw->mac.ops.enable_rx) 1798 hw->mac.ops.enable_rx(hw); 1799 } 1800 1801 /** 1802 * ixgbe_set_rate_select_speed - Set module link speed 1803 * @hw: pointer to hardware structure 1804 * @speed: link speed to set 1805 * 1806 * Set module link speed via the rate select. 1807 */ 1808 void ixgbe_set_rate_select_speed(struct ixgbe_hw *hw, ixgbe_link_speed speed) 1809 { 1810 if (hw->mac.ops.set_rate_select_speed) 1811 hw->mac.ops.set_rate_select_speed(hw, speed); 1812 } 1813