1 /****************************************************************************** 2 3 Copyright (c) 2001-2010, Intel Corporation 4 All rights reserved. 5 6 Redistribution and use in source and binary forms, with or without 7 modification, are permitted provided that the following conditions are met: 8 9 1. Redistributions of source code must retain the above copyright notice, 10 this list of conditions and the following disclaimer. 11 12 2. Redistributions in binary form must reproduce the above copyright 13 notice, this list of conditions and the following disclaimer in the 14 documentation and/or other materials provided with the distribution. 15 16 3. Neither the name of the Intel Corporation nor the names of its 17 contributors may be used to endorse or promote products derived from 18 this software without specific prior written permission. 19 20 THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 21 AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 22 IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 23 ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE 24 LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 25 CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 26 SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 27 INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 28 CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 29 ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 30 POSSIBILITY OF SUCH DAMAGE. 31 32 ******************************************************************************/ 33 /*$FreeBSD$*/ 34 35 #include "ixgbe_api.h" 36 #include "ixgbe_common.h" 37 38 extern s32 ixgbe_init_ops_82598(struct ixgbe_hw *hw); 39 extern s32 ixgbe_init_ops_82599(struct ixgbe_hw *hw); 40 41 /** 42 * ixgbe_init_shared_code - Initialize the shared code 43 * @hw: pointer to hardware structure 44 * 45 * This will assign function pointers and assign the MAC type and PHY code. 46 * Does not touch the hardware. This function must be called prior to any 47 * other function in the shared code. The ixgbe_hw structure should be 48 * memset to 0 prior to calling this function. The following fields in 49 * hw structure should be filled in prior to calling this function: 50 * hw_addr, back, device_id, vendor_id, subsystem_device_id, 51 * subsystem_vendor_id, and revision_id 52 **/ 53 s32 ixgbe_init_shared_code(struct ixgbe_hw *hw) 54 { 55 s32 status; 56 57 DEBUGFUNC("ixgbe_init_shared_code"); 58 59 /* 60 * Set the mac type 61 */ 62 ixgbe_set_mac_type(hw); 63 64 switch (hw->mac.type) { 65 case ixgbe_mac_82598EB: 66 status = ixgbe_init_ops_82598(hw); 67 break; 68 case ixgbe_mac_82599EB: 69 status = ixgbe_init_ops_82599(hw); 70 break; 71 default: 72 status = IXGBE_ERR_DEVICE_NOT_SUPPORTED; 73 break; 74 } 75 76 return status; 77 } 78 79 /** 80 * ixgbe_set_mac_type - Sets MAC type 81 * @hw: pointer to the HW structure 82 * 83 * This function sets the mac type of the adapter based on the 84 * vendor ID and device ID stored in the hw structure. 85 **/ 86 s32 ixgbe_set_mac_type(struct ixgbe_hw *hw) 87 { 88 s32 ret_val = IXGBE_SUCCESS; 89 90 DEBUGFUNC("ixgbe_set_mac_type\n"); 91 92 if (hw->vendor_id == IXGBE_INTEL_VENDOR_ID) { 93 switch (hw->device_id) { 94 case IXGBE_DEV_ID_82598: 95 case IXGBE_DEV_ID_82598_BX: 96 case IXGBE_DEV_ID_82598AF_SINGLE_PORT: 97 case IXGBE_DEV_ID_82598AF_DUAL_PORT: 98 case IXGBE_DEV_ID_82598AT: 99 case IXGBE_DEV_ID_82598AT2: 100 case IXGBE_DEV_ID_82598EB_CX4: 101 case IXGBE_DEV_ID_82598_CX4_DUAL_PORT: 102 case IXGBE_DEV_ID_82598_DA_DUAL_PORT: 103 case IXGBE_DEV_ID_82598_SR_DUAL_PORT_EM: 104 case IXGBE_DEV_ID_82598EB_XF_LR: 105 case IXGBE_DEV_ID_82598EB_SFP_LOM: 106 hw->mac.type = ixgbe_mac_82598EB; 107 break; 108 case IXGBE_DEV_ID_82599_KX4: 109 case IXGBE_DEV_ID_82599_KX4_MEZZ: 110 case IXGBE_DEV_ID_82599_XAUI_LOM: 111 case IXGBE_DEV_ID_82599_COMBO_BACKPLANE: 112 case IXGBE_DEV_ID_82599_SFP: 113 case IXGBE_DEV_ID_82599_CX4: 114 case IXGBE_DEV_ID_82599_T3_LOM: 115 hw->mac.type = ixgbe_mac_82599EB; 116 break; 117 default: 118 ret_val = IXGBE_ERR_DEVICE_NOT_SUPPORTED; 119 break; 120 } 121 } else { 122 ret_val = IXGBE_ERR_DEVICE_NOT_SUPPORTED; 123 } 124 125 DEBUGOUT2("ixgbe_set_mac_type found mac: %d, returns: %d\n", 126 hw->mac.type, ret_val); 127 return ret_val; 128 } 129 130 /** 131 * ixgbe_init_hw - Initialize the hardware 132 * @hw: pointer to hardware structure 133 * 134 * Initialize the hardware by resetting and then starting the hardware 135 **/ 136 s32 ixgbe_init_hw(struct ixgbe_hw *hw) 137 { 138 return ixgbe_call_func(hw, hw->mac.ops.init_hw, (hw), 139 IXGBE_NOT_IMPLEMENTED); 140 } 141 142 /** 143 * ixgbe_reset_hw - Performs a hardware reset 144 * @hw: pointer to hardware structure 145 * 146 * Resets the hardware by resetting the transmit and receive units, masks and 147 * clears all interrupts, performs a PHY reset, and performs a MAC reset 148 **/ 149 s32 ixgbe_reset_hw(struct ixgbe_hw *hw) 150 { 151 return ixgbe_call_func(hw, hw->mac.ops.reset_hw, (hw), 152 IXGBE_NOT_IMPLEMENTED); 153 } 154 155 /** 156 * ixgbe_start_hw - Prepares hardware for Rx/Tx 157 * @hw: pointer to hardware structure 158 * 159 * Starts the hardware by filling the bus info structure and media type, 160 * clears all on chip counters, initializes receive address registers, 161 * multicast table, VLAN filter table, calls routine to setup link and 162 * flow control settings, and leaves transmit and receive units disabled 163 * and uninitialized. 164 **/ 165 s32 ixgbe_start_hw(struct ixgbe_hw *hw) 166 { 167 return ixgbe_call_func(hw, hw->mac.ops.start_hw, (hw), 168 IXGBE_NOT_IMPLEMENTED); 169 } 170 171 /** 172 * ixgbe_enable_relaxed_ordering - Enables tx relaxed ordering, 173 * which is disabled by default in ixgbe_start_hw(); 174 * 175 * @hw: pointer to hardware structure 176 * 177 * Enable relaxed ordering; 178 **/ 179 void ixgbe_enable_relaxed_ordering(struct ixgbe_hw *hw) 180 { 181 if (hw->mac.ops.enable_relaxed_ordering) 182 hw->mac.ops.enable_relaxed_ordering(hw); 183 } 184 185 /** 186 * ixgbe_clear_hw_cntrs - Clear hardware counters 187 * @hw: pointer to hardware structure 188 * 189 * Clears all hardware statistics counters by reading them from the hardware 190 * Statistics counters are clear on read. 191 **/ 192 s32 ixgbe_clear_hw_cntrs(struct ixgbe_hw *hw) 193 { 194 return ixgbe_call_func(hw, hw->mac.ops.clear_hw_cntrs, (hw), 195 IXGBE_NOT_IMPLEMENTED); 196 } 197 198 /** 199 * ixgbe_get_media_type - Get media type 200 * @hw: pointer to hardware structure 201 * 202 * Returns the media type (fiber, copper, backplane) 203 **/ 204 enum ixgbe_media_type ixgbe_get_media_type(struct ixgbe_hw *hw) 205 { 206 return ixgbe_call_func(hw, hw->mac.ops.get_media_type, (hw), 207 ixgbe_media_type_unknown); 208 } 209 210 /** 211 * ixgbe_get_mac_addr - Get MAC address 212 * @hw: pointer to hardware structure 213 * @mac_addr: Adapter MAC address 214 * 215 * Reads the adapter's MAC address from the first Receive Address Register 216 * (RAR0) A reset of the adapter must have been performed prior to calling 217 * this function in order for the MAC address to have been loaded from the 218 * EEPROM into RAR0 219 **/ 220 s32 ixgbe_get_mac_addr(struct ixgbe_hw *hw, u8 *mac_addr) 221 { 222 return ixgbe_call_func(hw, hw->mac.ops.get_mac_addr, 223 (hw, mac_addr), IXGBE_NOT_IMPLEMENTED); 224 } 225 226 /** 227 * ixgbe_get_san_mac_addr - Get SAN MAC address 228 * @hw: pointer to hardware structure 229 * @san_mac_addr: SAN MAC address 230 * 231 * Reads the SAN MAC address from the EEPROM, if it's available. This is 232 * per-port, so set_lan_id() must be called before reading the addresses. 233 **/ 234 s32 ixgbe_get_san_mac_addr(struct ixgbe_hw *hw, u8 *san_mac_addr) 235 { 236 return ixgbe_call_func(hw, hw->mac.ops.get_san_mac_addr, 237 (hw, san_mac_addr), IXGBE_NOT_IMPLEMENTED); 238 } 239 240 /** 241 * ixgbe_set_san_mac_addr - Write a SAN MAC address 242 * @hw: pointer to hardware structure 243 * @san_mac_addr: SAN MAC address 244 * 245 * Writes A SAN MAC address to the EEPROM. 246 **/ 247 s32 ixgbe_set_san_mac_addr(struct ixgbe_hw *hw, u8 *san_mac_addr) 248 { 249 return ixgbe_call_func(hw, hw->mac.ops.set_san_mac_addr, 250 (hw, san_mac_addr), IXGBE_NOT_IMPLEMENTED); 251 } 252 253 /** 254 * ixgbe_get_device_caps - Get additional device capabilities 255 * @hw: pointer to hardware structure 256 * @device_caps: the EEPROM word for device capabilities 257 * 258 * Reads the extra device capabilities from the EEPROM 259 **/ 260 s32 ixgbe_get_device_caps(struct ixgbe_hw *hw, u16 *device_caps) 261 { 262 return ixgbe_call_func(hw, hw->mac.ops.get_device_caps, 263 (hw, device_caps), IXGBE_NOT_IMPLEMENTED); 264 } 265 266 /** 267 * ixgbe_get_wwn_prefix - Get alternative WWNN/WWPN prefix from the EEPROM 268 * @hw: pointer to hardware structure 269 * @wwnn_prefix: the alternative WWNN prefix 270 * @wwpn_prefix: the alternative WWPN prefix 271 * 272 * This function will read the EEPROM from the alternative SAN MAC address 273 * block to check the support for the alternative WWNN/WWPN prefix support. 274 **/ 275 s32 ixgbe_get_wwn_prefix(struct ixgbe_hw *hw, u16 *wwnn_prefix, 276 u16 *wwpn_prefix) 277 { 278 return ixgbe_call_func(hw, hw->mac.ops.get_wwn_prefix, 279 (hw, wwnn_prefix, wwpn_prefix), 280 IXGBE_NOT_IMPLEMENTED); 281 } 282 283 /** 284 * ixgbe_get_bus_info - Set PCI bus info 285 * @hw: pointer to hardware structure 286 * 287 * Sets the PCI bus info (speed, width, type) within the ixgbe_hw structure 288 **/ 289 s32 ixgbe_get_bus_info(struct ixgbe_hw *hw) 290 { 291 return ixgbe_call_func(hw, hw->mac.ops.get_bus_info, (hw), 292 IXGBE_NOT_IMPLEMENTED); 293 } 294 295 /** 296 * ixgbe_get_num_of_tx_queues - Get Tx queues 297 * @hw: pointer to hardware structure 298 * 299 * Returns the number of transmit queues for the given adapter. 300 **/ 301 u32 ixgbe_get_num_of_tx_queues(struct ixgbe_hw *hw) 302 { 303 return hw->mac.max_tx_queues; 304 } 305 306 /** 307 * ixgbe_get_num_of_rx_queues - Get Rx queues 308 * @hw: pointer to hardware structure 309 * 310 * Returns the number of receive queues for the given adapter. 311 **/ 312 u32 ixgbe_get_num_of_rx_queues(struct ixgbe_hw *hw) 313 { 314 return hw->mac.max_rx_queues; 315 } 316 317 /** 318 * ixgbe_stop_adapter - Disable Rx/Tx units 319 * @hw: pointer to hardware structure 320 * 321 * Sets the adapter_stopped flag within ixgbe_hw struct. Clears interrupts, 322 * disables transmit and receive units. The adapter_stopped flag is used by 323 * the shared code and drivers to determine if the adapter is in a stopped 324 * state and should not touch the hardware. 325 **/ 326 s32 ixgbe_stop_adapter(struct ixgbe_hw *hw) 327 { 328 return ixgbe_call_func(hw, hw->mac.ops.stop_adapter, (hw), 329 IXGBE_NOT_IMPLEMENTED); 330 } 331 332 /** 333 * ixgbe_read_pba_num - Reads part number from EEPROM 334 * @hw: pointer to hardware structure 335 * @pba_num: stores the part number from the EEPROM 336 * 337 * Reads the part number from the EEPROM. 338 **/ 339 s32 ixgbe_read_pba_num(struct ixgbe_hw *hw, u32 *pba_num) 340 { 341 return ixgbe_read_pba_num_generic(hw, pba_num); 342 } 343 344 /** 345 * ixgbe_identify_phy - Get PHY type 346 * @hw: pointer to hardware structure 347 * 348 * Determines the physical layer module found on the current adapter. 349 **/ 350 s32 ixgbe_identify_phy(struct ixgbe_hw *hw) 351 { 352 s32 status = IXGBE_SUCCESS; 353 354 if (hw->phy.type == ixgbe_phy_unknown) { 355 status = ixgbe_call_func(hw, 356 hw->phy.ops.identify, 357 (hw), 358 IXGBE_NOT_IMPLEMENTED); 359 } 360 361 return status; 362 } 363 364 /** 365 * ixgbe_reset_phy - Perform a PHY reset 366 * @hw: pointer to hardware structure 367 **/ 368 s32 ixgbe_reset_phy(struct ixgbe_hw *hw) 369 { 370 s32 status = IXGBE_SUCCESS; 371 372 if (hw->phy.type == ixgbe_phy_unknown) { 373 if (ixgbe_identify_phy(hw) != IXGBE_SUCCESS) 374 status = IXGBE_ERR_PHY; 375 } 376 377 if (status == IXGBE_SUCCESS) { 378 status = ixgbe_call_func(hw, hw->phy.ops.reset, (hw), 379 IXGBE_NOT_IMPLEMENTED); 380 } 381 return status; 382 } 383 384 /** 385 * ixgbe_get_phy_firmware_version - 386 * @hw: pointer to hardware structure 387 * @firmware_version: pointer to firmware version 388 **/ 389 s32 ixgbe_get_phy_firmware_version(struct ixgbe_hw *hw, u16 *firmware_version) 390 { 391 s32 status = IXGBE_SUCCESS; 392 393 status = ixgbe_call_func(hw, hw->phy.ops.get_firmware_version, 394 (hw, firmware_version), 395 IXGBE_NOT_IMPLEMENTED); 396 return status; 397 } 398 399 /** 400 * ixgbe_read_phy_reg - Read PHY register 401 * @hw: pointer to hardware structure 402 * @reg_addr: 32 bit address of PHY register to read 403 * @phy_data: Pointer to read data from PHY register 404 * 405 * Reads a value from a specified PHY register 406 **/ 407 s32 ixgbe_read_phy_reg(struct ixgbe_hw *hw, u32 reg_addr, u32 device_type, 408 u16 *phy_data) 409 { 410 if (hw->phy.id == 0) 411 ixgbe_identify_phy(hw); 412 413 return ixgbe_call_func(hw, hw->phy.ops.read_reg, (hw, reg_addr, 414 device_type, phy_data), IXGBE_NOT_IMPLEMENTED); 415 } 416 417 /** 418 * ixgbe_write_phy_reg - Write PHY register 419 * @hw: pointer to hardware structure 420 * @reg_addr: 32 bit PHY register to write 421 * @phy_data: Data to write to the PHY register 422 * 423 * Writes a value to specified PHY register 424 **/ 425 s32 ixgbe_write_phy_reg(struct ixgbe_hw *hw, u32 reg_addr, u32 device_type, 426 u16 phy_data) 427 { 428 if (hw->phy.id == 0) 429 ixgbe_identify_phy(hw); 430 431 return ixgbe_call_func(hw, hw->phy.ops.write_reg, (hw, reg_addr, 432 device_type, phy_data), IXGBE_NOT_IMPLEMENTED); 433 } 434 435 /** 436 * ixgbe_setup_phy_link - Restart PHY autoneg 437 * @hw: pointer to hardware structure 438 * 439 * Restart autonegotiation and PHY and waits for completion. 440 **/ 441 s32 ixgbe_setup_phy_link(struct ixgbe_hw *hw) 442 { 443 return ixgbe_call_func(hw, hw->phy.ops.setup_link, (hw), 444 IXGBE_NOT_IMPLEMENTED); 445 } 446 447 /** 448 * ixgbe_check_phy_link - Determine link and speed status 449 * @hw: pointer to hardware structure 450 * 451 * Reads a PHY register to determine if link is up and the current speed for 452 * the PHY. 453 **/ 454 s32 ixgbe_check_phy_link(struct ixgbe_hw *hw, ixgbe_link_speed *speed, 455 bool *link_up) 456 { 457 return ixgbe_call_func(hw, hw->phy.ops.check_link, (hw, speed, 458 link_up), IXGBE_NOT_IMPLEMENTED); 459 } 460 461 /** 462 * ixgbe_setup_phy_link_speed - Set auto advertise 463 * @hw: pointer to hardware structure 464 * @speed: new link speed 465 * @autoneg: TRUE if autonegotiation enabled 466 * 467 * Sets the auto advertised capabilities 468 **/ 469 s32 ixgbe_setup_phy_link_speed(struct ixgbe_hw *hw, ixgbe_link_speed speed, 470 bool autoneg, 471 bool autoneg_wait_to_complete) 472 { 473 return ixgbe_call_func(hw, hw->phy.ops.setup_link_speed, (hw, speed, 474 autoneg, autoneg_wait_to_complete), 475 IXGBE_NOT_IMPLEMENTED); 476 } 477 478 /** 479 * ixgbe_check_link - Get link and speed status 480 * @hw: pointer to hardware structure 481 * 482 * Reads the links register to determine if link is up and the current speed 483 **/ 484 s32 ixgbe_check_link(struct ixgbe_hw *hw, ixgbe_link_speed *speed, 485 bool *link_up, bool link_up_wait_to_complete) 486 { 487 return ixgbe_call_func(hw, hw->mac.ops.check_link, (hw, speed, 488 link_up, link_up_wait_to_complete), 489 IXGBE_NOT_IMPLEMENTED); 490 } 491 492 /** 493 * ixgbe_setup_link - Set link speed 494 * @hw: pointer to hardware structure 495 * @speed: new link speed 496 * @autoneg: TRUE if autonegotiation enabled 497 * 498 * Configures link settings. Restarts the link. 499 * Performs autonegotiation if needed. 500 **/ 501 s32 ixgbe_setup_link(struct ixgbe_hw *hw, ixgbe_link_speed speed, 502 bool autoneg, 503 bool autoneg_wait_to_complete) 504 { 505 return ixgbe_call_func(hw, hw->mac.ops.setup_link, (hw, speed, 506 autoneg, autoneg_wait_to_complete), 507 IXGBE_NOT_IMPLEMENTED); 508 } 509 510 /** 511 * ixgbe_get_link_capabilities - Returns link capabilities 512 * @hw: pointer to hardware structure 513 * 514 * Determines the link capabilities of the current configuration. 515 **/ 516 s32 ixgbe_get_link_capabilities(struct ixgbe_hw *hw, ixgbe_link_speed *speed, 517 bool *autoneg) 518 { 519 return ixgbe_call_func(hw, hw->mac.ops.get_link_capabilities, (hw, 520 speed, autoneg), IXGBE_NOT_IMPLEMENTED); 521 } 522 523 /** 524 * ixgbe_led_on - Turn on LEDs 525 * @hw: pointer to hardware structure 526 * @index: led number to turn on 527 * 528 * Turns on the software controllable LEDs. 529 **/ 530 s32 ixgbe_led_on(struct ixgbe_hw *hw, u32 index) 531 { 532 return ixgbe_call_func(hw, hw->mac.ops.led_on, (hw, index), 533 IXGBE_NOT_IMPLEMENTED); 534 } 535 536 /** 537 * ixgbe_led_off - Turn off LEDs 538 * @hw: pointer to hardware structure 539 * @index: led number to turn off 540 * 541 * Turns off the software controllable LEDs. 542 **/ 543 s32 ixgbe_led_off(struct ixgbe_hw *hw, u32 index) 544 { 545 return ixgbe_call_func(hw, hw->mac.ops.led_off, (hw, index), 546 IXGBE_NOT_IMPLEMENTED); 547 } 548 549 /** 550 * ixgbe_blink_led_start - Blink LEDs 551 * @hw: pointer to hardware structure 552 * @index: led number to blink 553 * 554 * Blink LED based on index. 555 **/ 556 s32 ixgbe_blink_led_start(struct ixgbe_hw *hw, u32 index) 557 { 558 return ixgbe_call_func(hw, hw->mac.ops.blink_led_start, (hw, index), 559 IXGBE_NOT_IMPLEMENTED); 560 } 561 562 /** 563 * ixgbe_blink_led_stop - Stop blinking LEDs 564 * @hw: pointer to hardware structure 565 * 566 * Stop blinking LED based on index. 567 **/ 568 s32 ixgbe_blink_led_stop(struct ixgbe_hw *hw, u32 index) 569 { 570 return ixgbe_call_func(hw, hw->mac.ops.blink_led_stop, (hw, index), 571 IXGBE_NOT_IMPLEMENTED); 572 } 573 574 /** 575 * ixgbe_init_eeprom_params - Initialize EEPROM parameters 576 * @hw: pointer to hardware structure 577 * 578 * Initializes the EEPROM parameters ixgbe_eeprom_info within the 579 * ixgbe_hw struct in order to set up EEPROM access. 580 **/ 581 s32 ixgbe_init_eeprom_params(struct ixgbe_hw *hw) 582 { 583 return ixgbe_call_func(hw, hw->eeprom.ops.init_params, (hw), 584 IXGBE_NOT_IMPLEMENTED); 585 } 586 587 588 /** 589 * ixgbe_write_eeprom - Write word to EEPROM 590 * @hw: pointer to hardware structure 591 * @offset: offset within the EEPROM to be written to 592 * @data: 16 bit word to be written to the EEPROM 593 * 594 * Writes 16 bit value to EEPROM. If ixgbe_eeprom_update_checksum is not 595 * called after this function, the EEPROM will most likely contain an 596 * invalid checksum. 597 **/ 598 s32 ixgbe_write_eeprom(struct ixgbe_hw *hw, u16 offset, u16 data) 599 { 600 return ixgbe_call_func(hw, hw->eeprom.ops.write, (hw, offset, data), 601 IXGBE_NOT_IMPLEMENTED); 602 } 603 604 /** 605 * ixgbe_read_eeprom - Read word from EEPROM 606 * @hw: pointer to hardware structure 607 * @offset: offset within the EEPROM to be read 608 * @data: read 16 bit value from EEPROM 609 * 610 * Reads 16 bit value from EEPROM 611 **/ 612 s32 ixgbe_read_eeprom(struct ixgbe_hw *hw, u16 offset, u16 *data) 613 { 614 return ixgbe_call_func(hw, hw->eeprom.ops.read, (hw, offset, data), 615 IXGBE_NOT_IMPLEMENTED); 616 } 617 618 /** 619 * ixgbe_validate_eeprom_checksum - Validate EEPROM checksum 620 * @hw: pointer to hardware structure 621 * @checksum_val: calculated checksum 622 * 623 * Performs checksum calculation and validates the EEPROM checksum 624 **/ 625 s32 ixgbe_validate_eeprom_checksum(struct ixgbe_hw *hw, u16 *checksum_val) 626 { 627 return ixgbe_call_func(hw, hw->eeprom.ops.validate_checksum, 628 (hw, checksum_val), IXGBE_NOT_IMPLEMENTED); 629 } 630 631 /** 632 * ixgbe_eeprom_update_checksum - Updates the EEPROM checksum 633 * @hw: pointer to hardware structure 634 **/ 635 s32 ixgbe_update_eeprom_checksum(struct ixgbe_hw *hw) 636 { 637 return ixgbe_call_func(hw, hw->eeprom.ops.update_checksum, (hw), 638 IXGBE_NOT_IMPLEMENTED); 639 } 640 641 /** 642 * ixgbe_insert_mac_addr - Find a RAR for this mac address 643 * @hw: pointer to hardware structure 644 * @addr: Address to put into receive address register 645 * @vmdq: VMDq pool to assign 646 * 647 * Puts an ethernet address into a receive address register, or 648 * finds the rar that it is aleady in; adds to the pool list 649 **/ 650 s32 ixgbe_insert_mac_addr(struct ixgbe_hw *hw, u8 *addr, u32 vmdq) 651 { 652 return ixgbe_call_func(hw, hw->mac.ops.insert_mac_addr, 653 (hw, addr, vmdq), 654 IXGBE_NOT_IMPLEMENTED); 655 } 656 657 /** 658 * ixgbe_set_rar - Set Rx address register 659 * @hw: pointer to hardware structure 660 * @index: Receive address register to write 661 * @addr: Address to put into receive address register 662 * @vmdq: VMDq "set" 663 * @enable_addr: set flag that address is active 664 * 665 * Puts an ethernet address into a receive address register. 666 **/ 667 s32 ixgbe_set_rar(struct ixgbe_hw *hw, u32 index, u8 *addr, u32 vmdq, 668 u32 enable_addr) 669 { 670 return ixgbe_call_func(hw, hw->mac.ops.set_rar, (hw, index, addr, vmdq, 671 enable_addr), IXGBE_NOT_IMPLEMENTED); 672 } 673 674 /** 675 * ixgbe_clear_rar - Clear Rx address register 676 * @hw: pointer to hardware structure 677 * @index: Receive address register to write 678 * 679 * Puts an ethernet address into a receive address register. 680 **/ 681 s32 ixgbe_clear_rar(struct ixgbe_hw *hw, u32 index) 682 { 683 return ixgbe_call_func(hw, hw->mac.ops.clear_rar, (hw, index), 684 IXGBE_NOT_IMPLEMENTED); 685 } 686 687 /** 688 * ixgbe_set_vmdq - Associate a VMDq index with a receive address 689 * @hw: pointer to hardware structure 690 * @rar: receive address register index to associate with VMDq index 691 * @vmdq: VMDq set or pool index 692 **/ 693 s32 ixgbe_set_vmdq(struct ixgbe_hw *hw, u32 rar, u32 vmdq) 694 { 695 return ixgbe_call_func(hw, hw->mac.ops.set_vmdq, (hw, rar, vmdq), 696 IXGBE_NOT_IMPLEMENTED); 697 } 698 699 /** 700 * ixgbe_clear_vmdq - Disassociate a VMDq index from a receive address 701 * @hw: pointer to hardware structure 702 * @rar: receive address register index to disassociate with VMDq index 703 * @vmdq: VMDq set or pool index 704 **/ 705 s32 ixgbe_clear_vmdq(struct ixgbe_hw *hw, u32 rar, u32 vmdq) 706 { 707 return ixgbe_call_func(hw, hw->mac.ops.clear_vmdq, (hw, rar, vmdq), 708 IXGBE_NOT_IMPLEMENTED); 709 } 710 711 /** 712 * ixgbe_init_rx_addrs - Initializes receive address filters. 713 * @hw: pointer to hardware structure 714 * 715 * Places the MAC address in receive address register 0 and clears the rest 716 * of the receive address registers. Clears the multicast table. Assumes 717 * the receiver is in reset when the routine is called. 718 **/ 719 s32 ixgbe_init_rx_addrs(struct ixgbe_hw *hw) 720 { 721 return ixgbe_call_func(hw, hw->mac.ops.init_rx_addrs, (hw), 722 IXGBE_NOT_IMPLEMENTED); 723 } 724 725 /** 726 * ixgbe_get_num_rx_addrs - Returns the number of RAR entries. 727 * @hw: pointer to hardware structure 728 **/ 729 u32 ixgbe_get_num_rx_addrs(struct ixgbe_hw *hw) 730 { 731 return hw->mac.num_rar_entries; 732 } 733 734 /** 735 * ixgbe_update_uc_addr_list - Updates the MAC's list of secondary addresses 736 * @hw: pointer to hardware structure 737 * @addr_list: the list of new multicast addresses 738 * @addr_count: number of addresses 739 * @func: iterator function to walk the multicast address list 740 * 741 * The given list replaces any existing list. Clears the secondary addrs from 742 * receive address registers. Uses unused receive address registers for the 743 * first secondary addresses, and falls back to promiscuous mode as needed. 744 **/ 745 s32 ixgbe_update_uc_addr_list(struct ixgbe_hw *hw, u8 *addr_list, 746 u32 addr_count, ixgbe_mc_addr_itr func) 747 { 748 return ixgbe_call_func(hw, hw->mac.ops.update_uc_addr_list, (hw, 749 addr_list, addr_count, func), 750 IXGBE_NOT_IMPLEMENTED); 751 } 752 753 /** 754 * ixgbe_update_mc_addr_list - Updates the MAC's list of multicast addresses 755 * @hw: pointer to hardware structure 756 * @mc_addr_list: the list of new multicast addresses 757 * @mc_addr_count: number of addresses 758 * @func: iterator function to walk the multicast address list 759 * 760 * The given list replaces any existing list. Clears the MC addrs from receive 761 * address registers and the multicast table. Uses unused receive address 762 * registers for the first multicast addresses, and hashes the rest into the 763 * multicast table. 764 **/ 765 s32 ixgbe_update_mc_addr_list(struct ixgbe_hw *hw, u8 *mc_addr_list, 766 u32 mc_addr_count, ixgbe_mc_addr_itr func) 767 { 768 return ixgbe_call_func(hw, hw->mac.ops.update_mc_addr_list, (hw, 769 mc_addr_list, mc_addr_count, func), 770 IXGBE_NOT_IMPLEMENTED); 771 } 772 773 /** 774 * ixgbe_enable_mc - Enable multicast address in RAR 775 * @hw: pointer to hardware structure 776 * 777 * Enables multicast address in RAR and the use of the multicast hash table. 778 **/ 779 s32 ixgbe_enable_mc(struct ixgbe_hw *hw) 780 { 781 return ixgbe_call_func(hw, hw->mac.ops.enable_mc, (hw), 782 IXGBE_NOT_IMPLEMENTED); 783 } 784 785 /** 786 * ixgbe_disable_mc - Disable multicast address in RAR 787 * @hw: pointer to hardware structure 788 * 789 * Disables multicast address in RAR and the use of the multicast hash table. 790 **/ 791 s32 ixgbe_disable_mc(struct ixgbe_hw *hw) 792 { 793 return ixgbe_call_func(hw, hw->mac.ops.disable_mc, (hw), 794 IXGBE_NOT_IMPLEMENTED); 795 } 796 797 /** 798 * ixgbe_clear_vfta - Clear VLAN filter table 799 * @hw: pointer to hardware structure 800 * 801 * Clears the VLAN filer table, and the VMDq index associated with the filter 802 **/ 803 s32 ixgbe_clear_vfta(struct ixgbe_hw *hw) 804 { 805 return ixgbe_call_func(hw, hw->mac.ops.clear_vfta, (hw), 806 IXGBE_NOT_IMPLEMENTED); 807 } 808 809 /** 810 * ixgbe_set_vfta - Set VLAN filter table 811 * @hw: pointer to hardware structure 812 * @vlan: VLAN id to write to VLAN filter 813 * @vind: VMDq output index that maps queue to VLAN id in VFTA 814 * @vlan_on: boolean flag to turn on/off VLAN in VFTA 815 * 816 * Turn on/off specified VLAN in the VLAN filter table. 817 **/ 818 s32 ixgbe_set_vfta(struct ixgbe_hw *hw, u32 vlan, u32 vind, bool vlan_on) 819 { 820 return ixgbe_call_func(hw, hw->mac.ops.set_vfta, (hw, vlan, vind, 821 vlan_on), IXGBE_NOT_IMPLEMENTED); 822 } 823 824 /** 825 * ixgbe_fc_enable - Enable flow control 826 * @hw: pointer to hardware structure 827 * @packetbuf_num: packet buffer number (0-7) 828 * 829 * Configures the flow control settings based on SW configuration. 830 **/ 831 s32 ixgbe_fc_enable(struct ixgbe_hw *hw, s32 packetbuf_num) 832 { 833 return ixgbe_call_func(hw, hw->mac.ops.fc_enable, (hw, packetbuf_num), 834 IXGBE_NOT_IMPLEMENTED); 835 } 836 837 /** 838 * ixgbe_read_analog_reg8 - Reads 8 bit analog register 839 * @hw: pointer to hardware structure 840 * @reg: analog register to read 841 * @val: read value 842 * 843 * Performs write operation to analog register specified. 844 **/ 845 s32 ixgbe_read_analog_reg8(struct ixgbe_hw *hw, u32 reg, u8 *val) 846 { 847 return ixgbe_call_func(hw, hw->mac.ops.read_analog_reg8, (hw, reg, 848 val), IXGBE_NOT_IMPLEMENTED); 849 } 850 851 /** 852 * ixgbe_write_analog_reg8 - Writes 8 bit analog register 853 * @hw: pointer to hardware structure 854 * @reg: analog register to write 855 * @val: value to write 856 * 857 * Performs write operation to Atlas analog register specified. 858 **/ 859 s32 ixgbe_write_analog_reg8(struct ixgbe_hw *hw, u32 reg, u8 val) 860 { 861 return ixgbe_call_func(hw, hw->mac.ops.write_analog_reg8, (hw, reg, 862 val), IXGBE_NOT_IMPLEMENTED); 863 } 864 865 /** 866 * ixgbe_init_uta_tables - Initializes Unicast Table Arrays. 867 * @hw: pointer to hardware structure 868 * 869 * Initializes the Unicast Table Arrays to zero on device load. This 870 * is part of the Rx init addr execution path. 871 **/ 872 s32 ixgbe_init_uta_tables(struct ixgbe_hw *hw) 873 { 874 return ixgbe_call_func(hw, hw->mac.ops.init_uta_tables, (hw), 875 IXGBE_NOT_IMPLEMENTED); 876 } 877 878 /** 879 * ixgbe_read_i2c_byte - Reads 8 bit word over I2C at specified device address 880 * @hw: pointer to hardware structure 881 * @byte_offset: byte offset to read 882 * @data: value read 883 * 884 * Performs byte read operation to SFP module's EEPROM over I2C interface. 885 **/ 886 s32 ixgbe_read_i2c_byte(struct ixgbe_hw *hw, u8 byte_offset, u8 dev_addr, 887 u8 *data) 888 { 889 return ixgbe_call_func(hw, hw->phy.ops.read_i2c_byte, (hw, byte_offset, 890 dev_addr, data), IXGBE_NOT_IMPLEMENTED); 891 } 892 893 /** 894 * ixgbe_write_i2c_byte - Writes 8 bit word over I2C 895 * @hw: pointer to hardware structure 896 * @byte_offset: byte offset to write 897 * @data: value to write 898 * 899 * Performs byte write operation to SFP module's EEPROM over I2C interface 900 * at a specified device address. 901 **/ 902 s32 ixgbe_write_i2c_byte(struct ixgbe_hw *hw, u8 byte_offset, u8 dev_addr, 903 u8 data) 904 { 905 return ixgbe_call_func(hw, hw->phy.ops.write_i2c_byte, (hw, byte_offset, 906 dev_addr, data), IXGBE_NOT_IMPLEMENTED); 907 } 908 909 /** 910 * ixgbe_write_i2c_eeprom - Writes 8 bit EEPROM word over I2C interface 911 * @hw: pointer to hardware structure 912 * @byte_offset: EEPROM byte offset to write 913 * @eeprom_data: value to write 914 * 915 * Performs byte write operation to SFP module's EEPROM over I2C interface. 916 **/ 917 s32 ixgbe_write_i2c_eeprom(struct ixgbe_hw *hw, 918 u8 byte_offset, u8 eeprom_data) 919 { 920 return ixgbe_call_func(hw, hw->phy.ops.write_i2c_eeprom, 921 (hw, byte_offset, eeprom_data), 922 IXGBE_NOT_IMPLEMENTED); 923 } 924 925 /** 926 * ixgbe_read_i2c_eeprom - Reads 8 bit EEPROM word over I2C interface 927 * @hw: pointer to hardware structure 928 * @byte_offset: EEPROM byte offset to read 929 * @eeprom_data: value read 930 * 931 * Performs byte read operation to SFP module's EEPROM over I2C interface. 932 **/ 933 s32 ixgbe_read_i2c_eeprom(struct ixgbe_hw *hw, u8 byte_offset, u8 *eeprom_data) 934 { 935 return ixgbe_call_func(hw, hw->phy.ops.read_i2c_eeprom, 936 (hw, byte_offset, eeprom_data), 937 IXGBE_NOT_IMPLEMENTED); 938 } 939 940 /** 941 * ixgbe_get_supported_physical_layer - Returns physical layer type 942 * @hw: pointer to hardware structure 943 * 944 * Determines physical layer capabilities of the current configuration. 945 **/ 946 u32 ixgbe_get_supported_physical_layer(struct ixgbe_hw *hw) 947 { 948 return ixgbe_call_func(hw, hw->mac.ops.get_supported_physical_layer, 949 (hw), IXGBE_PHYSICAL_LAYER_UNKNOWN); 950 } 951 952 /** 953 * ixgbe_enable_rx_dma - Enables Rx DMA unit, dependant on device specifics 954 * @hw: pointer to hardware structure 955 * @regval: bitfield to write to the Rx DMA register 956 * 957 * Enables the Rx DMA unit of the device. 958 **/ 959 s32 ixgbe_enable_rx_dma(struct ixgbe_hw *hw, u32 regval) 960 { 961 return ixgbe_call_func(hw, hw->mac.ops.enable_rx_dma, 962 (hw, regval), IXGBE_NOT_IMPLEMENTED); 963 } 964 965 /** 966 * ixgbe_acquire_swfw_semaphore - Acquire SWFW semaphore 967 * @hw: pointer to hardware structure 968 * @mask: Mask to specify which semaphore to acquire 969 * 970 * Acquires the SWFW semaphore through SW_FW_SYNC register for the specified 971 * function (CSR, PHY0, PHY1, EEPROM, Flash) 972 **/ 973 s32 ixgbe_acquire_swfw_semaphore(struct ixgbe_hw *hw, u16 mask) 974 { 975 return ixgbe_call_func(hw, hw->mac.ops.acquire_swfw_sync, 976 (hw, mask), IXGBE_NOT_IMPLEMENTED); 977 } 978 979 /** 980 * ixgbe_release_swfw_semaphore - Release SWFW semaphore 981 * @hw: pointer to hardware structure 982 * @mask: Mask to specify which semaphore to release 983 * 984 * Releases the SWFW semaphore through SW_FW_SYNC register for the specified 985 * function (CSR, PHY0, PHY1, EEPROM, Flash) 986 **/ 987 void ixgbe_release_swfw_semaphore(struct ixgbe_hw *hw, u16 mask) 988 { 989 if (hw->mac.ops.release_swfw_sync) 990 hw->mac.ops.release_swfw_sync(hw, mask); 991 } 992 993