1 /****************************************************************************** 2 SPDX-License-Identifier: BSD-3-Clause 3 4 Copyright (c) 2001-2020, Intel Corporation 5 All rights reserved. 6 7 Redistribution and use in source and binary forms, with or without 8 modification, are permitted provided that the following conditions are met: 9 10 1. Redistributions of source code must retain the above copyright notice, 11 this list of conditions and the following disclaimer. 12 13 2. Redistributions in binary form must reproduce the above copyright 14 notice, this list of conditions and the following disclaimer in the 15 documentation and/or other materials provided with the distribution. 16 17 3. Neither the name of the Intel Corporation nor the names of its 18 contributors may be used to endorse or promote products derived from 19 this software without specific prior written permission. 20 21 THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 22 AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 23 IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 24 ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE 25 LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 26 CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 27 SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 28 INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 29 CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 30 ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 31 POSSIBILITY OF SUCH DAMAGE. 32 33 ******************************************************************************/ 34 35 #include "ixgbe_api.h" 36 #include "ixgbe_common.h" 37 38 #define IXGBE_EMPTY_PARAM 39 40 static const u32 ixgbe_mvals_base[IXGBE_MVALS_IDX_LIMIT] = { 41 IXGBE_MVALS_INIT(IXGBE_EMPTY_PARAM) 42 }; 43 44 static const u32 ixgbe_mvals_X540[IXGBE_MVALS_IDX_LIMIT] = { 45 IXGBE_MVALS_INIT(_X540) 46 }; 47 48 static const u32 ixgbe_mvals_X550[IXGBE_MVALS_IDX_LIMIT] = { 49 IXGBE_MVALS_INIT(_X550) 50 }; 51 52 static const u32 ixgbe_mvals_X550EM_x[IXGBE_MVALS_IDX_LIMIT] = { 53 IXGBE_MVALS_INIT(_X550EM_x) 54 }; 55 56 static const u32 ixgbe_mvals_X550EM_a[IXGBE_MVALS_IDX_LIMIT] = { 57 IXGBE_MVALS_INIT(_X550EM_a) 58 }; 59 60 /** 61 * ixgbe_dcb_get_rtrup2tc - read rtrup2tc reg 62 * @hw: pointer to hardware structure 63 * @map: pointer to u8 arr for returning map 64 * 65 * Read the rtrup2tc HW register and resolve its content into map 66 **/ 67 void ixgbe_dcb_get_rtrup2tc(struct ixgbe_hw *hw, u8 *map) 68 { 69 if (hw->mac.ops.get_rtrup2tc) 70 hw->mac.ops.get_rtrup2tc(hw, map); 71 } 72 73 /** 74 * ixgbe_init_shared_code - Initialize the shared code 75 * @hw: pointer to hardware structure 76 * 77 * This will assign function pointers and assign the MAC type and PHY code. 78 * Does not touch the hardware. This function must be called prior to any 79 * other function in the shared code. The ixgbe_hw structure should be 80 * memset to 0 prior to calling this function. The following fields in 81 * hw structure should be filled in prior to calling this function: 82 * hw_addr, back, device_id, vendor_id, subsystem_device_id, 83 * subsystem_vendor_id, and revision_id 84 **/ 85 s32 ixgbe_init_shared_code(struct ixgbe_hw *hw) 86 { 87 s32 status; 88 89 DEBUGFUNC("ixgbe_init_shared_code"); 90 91 /* 92 * Set the mac type 93 */ 94 ixgbe_set_mac_type(hw); 95 96 switch (hw->mac.type) { 97 case ixgbe_mac_82598EB: 98 status = ixgbe_init_ops_82598(hw); 99 break; 100 case ixgbe_mac_82599EB: 101 status = ixgbe_init_ops_82599(hw); 102 break; 103 case ixgbe_mac_X540: 104 status = ixgbe_init_ops_X540(hw); 105 break; 106 case ixgbe_mac_X550: 107 status = ixgbe_init_ops_X550(hw); 108 break; 109 case ixgbe_mac_X550EM_x: 110 status = ixgbe_init_ops_X550EM_x(hw); 111 break; 112 case ixgbe_mac_X550EM_a: 113 status = ixgbe_init_ops_X550EM_a(hw); 114 break; 115 case ixgbe_mac_82599_vf: 116 case ixgbe_mac_X540_vf: 117 case ixgbe_mac_X550_vf: 118 case ixgbe_mac_X550EM_x_vf: 119 case ixgbe_mac_X550EM_a_vf: 120 status = ixgbe_init_ops_vf(hw); 121 break; 122 default: 123 status = IXGBE_ERR_DEVICE_NOT_SUPPORTED; 124 break; 125 } 126 hw->mac.max_link_up_time = IXGBE_LINK_UP_TIME; 127 128 return status; 129 } 130 131 /** 132 * ixgbe_set_mac_type - Sets MAC type 133 * @hw: pointer to the HW structure 134 * 135 * This function sets the mac type of the adapter based on the 136 * vendor ID and device ID stored in the hw structure. 137 **/ 138 s32 ixgbe_set_mac_type(struct ixgbe_hw *hw) 139 { 140 s32 ret_val = IXGBE_SUCCESS; 141 142 DEBUGFUNC("ixgbe_set_mac_type\n"); 143 144 if (hw->vendor_id != IXGBE_INTEL_VENDOR_ID) { 145 ERROR_REPORT2(IXGBE_ERROR_UNSUPPORTED, 146 "Unsupported vendor id: %x", hw->vendor_id); 147 return IXGBE_ERR_DEVICE_NOT_SUPPORTED; 148 } 149 150 hw->mvals = ixgbe_mvals_base; 151 152 switch (hw->device_id) { 153 case IXGBE_DEV_ID_82598: 154 case IXGBE_DEV_ID_82598_BX: 155 case IXGBE_DEV_ID_82598AF_SINGLE_PORT: 156 case IXGBE_DEV_ID_82598AF_DUAL_PORT: 157 case IXGBE_DEV_ID_82598AT: 158 case IXGBE_DEV_ID_82598AT2: 159 case IXGBE_DEV_ID_82598EB_CX4: 160 case IXGBE_DEV_ID_82598_CX4_DUAL_PORT: 161 case IXGBE_DEV_ID_82598_DA_DUAL_PORT: 162 case IXGBE_DEV_ID_82598_SR_DUAL_PORT_EM: 163 case IXGBE_DEV_ID_82598EB_XF_LR: 164 case IXGBE_DEV_ID_82598EB_SFP_LOM: 165 hw->mac.type = ixgbe_mac_82598EB; 166 break; 167 case IXGBE_DEV_ID_82599_KX4: 168 case IXGBE_DEV_ID_82599_KX4_MEZZ: 169 case IXGBE_DEV_ID_82599_XAUI_LOM: 170 case IXGBE_DEV_ID_82599_COMBO_BACKPLANE: 171 case IXGBE_DEV_ID_82599_KR: 172 case IXGBE_DEV_ID_82599_SFP: 173 case IXGBE_DEV_ID_82599_BACKPLANE_FCOE: 174 case IXGBE_DEV_ID_82599_SFP_FCOE: 175 case IXGBE_DEV_ID_82599_SFP_EM: 176 case IXGBE_DEV_ID_82599_SFP_SF2: 177 case IXGBE_DEV_ID_82599_SFP_SF_QP: 178 case IXGBE_DEV_ID_82599_QSFP_SF_QP: 179 case IXGBE_DEV_ID_82599EN_SFP: 180 case IXGBE_DEV_ID_82599_CX4: 181 case IXGBE_DEV_ID_82599_BYPASS: 182 case IXGBE_DEV_ID_82599_T3_LOM: 183 hw->mac.type = ixgbe_mac_82599EB; 184 break; 185 case IXGBE_DEV_ID_82599_VF: 186 case IXGBE_DEV_ID_82599_VF_HV: 187 hw->mac.type = ixgbe_mac_82599_vf; 188 break; 189 case IXGBE_DEV_ID_X540_VF: 190 case IXGBE_DEV_ID_X540_VF_HV: 191 hw->mac.type = ixgbe_mac_X540_vf; 192 hw->mvals = ixgbe_mvals_X540; 193 break; 194 case IXGBE_DEV_ID_X540T: 195 case IXGBE_DEV_ID_X540T1: 196 case IXGBE_DEV_ID_X540_BYPASS: 197 hw->mac.type = ixgbe_mac_X540; 198 hw->mvals = ixgbe_mvals_X540; 199 break; 200 case IXGBE_DEV_ID_X550T: 201 case IXGBE_DEV_ID_X550T1: 202 hw->mac.type = ixgbe_mac_X550; 203 hw->mvals = ixgbe_mvals_X550; 204 break; 205 case IXGBE_DEV_ID_X550EM_X_KX4: 206 case IXGBE_DEV_ID_X550EM_X_KR: 207 case IXGBE_DEV_ID_X550EM_X_10G_T: 208 case IXGBE_DEV_ID_X550EM_X_1G_T: 209 case IXGBE_DEV_ID_X550EM_X_SFP: 210 case IXGBE_DEV_ID_X550EM_X_XFI: 211 hw->mac.type = ixgbe_mac_X550EM_x; 212 hw->mvals = ixgbe_mvals_X550EM_x; 213 break; 214 case IXGBE_DEV_ID_X550EM_A_KR: 215 case IXGBE_DEV_ID_X550EM_A_KR_L: 216 case IXGBE_DEV_ID_X550EM_A_SFP_N: 217 case IXGBE_DEV_ID_X550EM_A_SGMII: 218 case IXGBE_DEV_ID_X550EM_A_SGMII_L: 219 case IXGBE_DEV_ID_X550EM_A_1G_T: 220 case IXGBE_DEV_ID_X550EM_A_1G_T_L: 221 case IXGBE_DEV_ID_X550EM_A_10G_T: 222 case IXGBE_DEV_ID_X550EM_A_QSFP: 223 case IXGBE_DEV_ID_X550EM_A_QSFP_N: 224 case IXGBE_DEV_ID_X550EM_A_SFP: 225 hw->mac.type = ixgbe_mac_X550EM_a; 226 hw->mvals = ixgbe_mvals_X550EM_a; 227 break; 228 case IXGBE_DEV_ID_X550_VF: 229 case IXGBE_DEV_ID_X550_VF_HV: 230 hw->mac.type = ixgbe_mac_X550_vf; 231 hw->mvals = ixgbe_mvals_X550; 232 break; 233 case IXGBE_DEV_ID_X550EM_X_VF: 234 case IXGBE_DEV_ID_X550EM_X_VF_HV: 235 hw->mac.type = ixgbe_mac_X550EM_x_vf; 236 hw->mvals = ixgbe_mvals_X550EM_x; 237 break; 238 case IXGBE_DEV_ID_X550EM_A_VF: 239 case IXGBE_DEV_ID_X550EM_A_VF_HV: 240 hw->mac.type = ixgbe_mac_X550EM_a_vf; 241 hw->mvals = ixgbe_mvals_X550EM_a; 242 break; 243 default: 244 ret_val = IXGBE_ERR_DEVICE_NOT_SUPPORTED; 245 ERROR_REPORT2(IXGBE_ERROR_UNSUPPORTED, 246 "Unsupported device id: %x", 247 hw->device_id); 248 break; 249 } 250 251 DEBUGOUT2("ixgbe_set_mac_type found mac: %d, returns: %d\n", 252 hw->mac.type, ret_val); 253 return ret_val; 254 } 255 256 /** 257 * ixgbe_init_hw - Initialize the hardware 258 * @hw: pointer to hardware structure 259 * 260 * Initialize the hardware by resetting and then starting the hardware 261 **/ 262 s32 ixgbe_init_hw(struct ixgbe_hw *hw) 263 { 264 return ixgbe_call_func(hw, hw->mac.ops.init_hw, (hw), 265 IXGBE_NOT_IMPLEMENTED); 266 } 267 268 /** 269 * ixgbe_reset_hw - Performs a hardware reset 270 * @hw: pointer to hardware structure 271 * 272 * Resets the hardware by resetting the transmit and receive units, masks and 273 * clears all interrupts, performs a PHY reset, and performs a MAC reset 274 **/ 275 s32 ixgbe_reset_hw(struct ixgbe_hw *hw) 276 { 277 return ixgbe_call_func(hw, hw->mac.ops.reset_hw, (hw), 278 IXGBE_NOT_IMPLEMENTED); 279 } 280 281 /** 282 * ixgbe_start_hw - Prepares hardware for Rx/Tx 283 * @hw: pointer to hardware structure 284 * 285 * Starts the hardware by filling the bus info structure and media type, 286 * clears all on chip counters, initializes receive address registers, 287 * multicast table, VLAN filter table, calls routine to setup link and 288 * flow control settings, and leaves transmit and receive units disabled 289 * and uninitialized. 290 **/ 291 s32 ixgbe_start_hw(struct ixgbe_hw *hw) 292 { 293 return ixgbe_call_func(hw, hw->mac.ops.start_hw, (hw), 294 IXGBE_NOT_IMPLEMENTED); 295 } 296 297 /** 298 * ixgbe_enable_relaxed_ordering - Enables tx relaxed ordering, 299 * which is disabled by default in ixgbe_start_hw(); 300 * 301 * @hw: pointer to hardware structure 302 * 303 * Enable relaxed ordering; 304 **/ 305 void ixgbe_enable_relaxed_ordering(struct ixgbe_hw *hw) 306 { 307 if (hw->mac.ops.enable_relaxed_ordering) 308 hw->mac.ops.enable_relaxed_ordering(hw); 309 } 310 311 /** 312 * ixgbe_clear_hw_cntrs - Clear hardware counters 313 * @hw: pointer to hardware structure 314 * 315 * Clears all hardware statistics counters by reading them from the hardware 316 * Statistics counters are clear on read. 317 **/ 318 s32 ixgbe_clear_hw_cntrs(struct ixgbe_hw *hw) 319 { 320 return ixgbe_call_func(hw, hw->mac.ops.clear_hw_cntrs, (hw), 321 IXGBE_NOT_IMPLEMENTED); 322 } 323 324 /** 325 * ixgbe_get_media_type - Get media type 326 * @hw: pointer to hardware structure 327 * 328 * Returns the media type (fiber, copper, backplane) 329 **/ 330 enum ixgbe_media_type ixgbe_get_media_type(struct ixgbe_hw *hw) 331 { 332 return ixgbe_call_func(hw, hw->mac.ops.get_media_type, (hw), 333 ixgbe_media_type_unknown); 334 } 335 336 /** 337 * ixgbe_get_mac_addr - Get MAC address 338 * @hw: pointer to hardware structure 339 * @mac_addr: Adapter MAC address 340 * 341 * Reads the adapter's MAC address from the first Receive Address Register 342 * (RAR0) A reset of the adapter must have been performed prior to calling 343 * this function in order for the MAC address to have been loaded from the 344 * EEPROM into RAR0 345 **/ 346 s32 ixgbe_get_mac_addr(struct ixgbe_hw *hw, u8 *mac_addr) 347 { 348 return ixgbe_call_func(hw, hw->mac.ops.get_mac_addr, 349 (hw, mac_addr), IXGBE_NOT_IMPLEMENTED); 350 } 351 352 /** 353 * ixgbe_get_san_mac_addr - Get SAN MAC address 354 * @hw: pointer to hardware structure 355 * @san_mac_addr: SAN MAC address 356 * 357 * Reads the SAN MAC address from the EEPROM, if it's available. This is 358 * per-port, so set_lan_id() must be called before reading the addresses. 359 **/ 360 s32 ixgbe_get_san_mac_addr(struct ixgbe_hw *hw, u8 *san_mac_addr) 361 { 362 return ixgbe_call_func(hw, hw->mac.ops.get_san_mac_addr, 363 (hw, san_mac_addr), IXGBE_NOT_IMPLEMENTED); 364 } 365 366 /** 367 * ixgbe_set_san_mac_addr - Write a SAN MAC address 368 * @hw: pointer to hardware structure 369 * @san_mac_addr: SAN MAC address 370 * 371 * Writes A SAN MAC address to the EEPROM. 372 **/ 373 s32 ixgbe_set_san_mac_addr(struct ixgbe_hw *hw, u8 *san_mac_addr) 374 { 375 return ixgbe_call_func(hw, hw->mac.ops.set_san_mac_addr, 376 (hw, san_mac_addr), IXGBE_NOT_IMPLEMENTED); 377 } 378 379 /** 380 * ixgbe_get_device_caps - Get additional device capabilities 381 * @hw: pointer to hardware structure 382 * @device_caps: the EEPROM word for device capabilities 383 * 384 * Reads the extra device capabilities from the EEPROM 385 **/ 386 s32 ixgbe_get_device_caps(struct ixgbe_hw *hw, u16 *device_caps) 387 { 388 return ixgbe_call_func(hw, hw->mac.ops.get_device_caps, 389 (hw, device_caps), IXGBE_NOT_IMPLEMENTED); 390 } 391 392 /** 393 * ixgbe_get_wwn_prefix - Get alternative WWNN/WWPN prefix from the EEPROM 394 * @hw: pointer to hardware structure 395 * @wwnn_prefix: the alternative WWNN prefix 396 * @wwpn_prefix: the alternative WWPN prefix 397 * 398 * This function will read the EEPROM from the alternative SAN MAC address 399 * block to check the support for the alternative WWNN/WWPN prefix support. 400 **/ 401 s32 ixgbe_get_wwn_prefix(struct ixgbe_hw *hw, u16 *wwnn_prefix, 402 u16 *wwpn_prefix) 403 { 404 return ixgbe_call_func(hw, hw->mac.ops.get_wwn_prefix, 405 (hw, wwnn_prefix, wwpn_prefix), 406 IXGBE_NOT_IMPLEMENTED); 407 } 408 409 /** 410 * ixgbe_get_fcoe_boot_status - Get FCOE boot status from EEPROM 411 * @hw: pointer to hardware structure 412 * @bs: the fcoe boot status 413 * 414 * This function will read the FCOE boot status from the iSCSI FCOE block 415 **/ 416 s32 ixgbe_get_fcoe_boot_status(struct ixgbe_hw *hw, u16 *bs) 417 { 418 return ixgbe_call_func(hw, hw->mac.ops.get_fcoe_boot_status, 419 (hw, bs), 420 IXGBE_NOT_IMPLEMENTED); 421 } 422 423 /** 424 * ixgbe_get_bus_info - Set PCI bus info 425 * @hw: pointer to hardware structure 426 * 427 * Sets the PCI bus info (speed, width, type) within the ixgbe_hw structure 428 **/ 429 s32 ixgbe_get_bus_info(struct ixgbe_hw *hw) 430 { 431 return ixgbe_call_func(hw, hw->mac.ops.get_bus_info, (hw), 432 IXGBE_NOT_IMPLEMENTED); 433 } 434 435 /** 436 * ixgbe_get_num_of_tx_queues - Get Tx queues 437 * @hw: pointer to hardware structure 438 * 439 * Returns the number of transmit queues for the given adapter. 440 **/ 441 u32 ixgbe_get_num_of_tx_queues(struct ixgbe_hw *hw) 442 { 443 return hw->mac.max_tx_queues; 444 } 445 446 /** 447 * ixgbe_get_num_of_rx_queues - Get Rx queues 448 * @hw: pointer to hardware structure 449 * 450 * Returns the number of receive queues for the given adapter. 451 **/ 452 u32 ixgbe_get_num_of_rx_queues(struct ixgbe_hw *hw) 453 { 454 return hw->mac.max_rx_queues; 455 } 456 457 /** 458 * ixgbe_stop_adapter - Disable Rx/Tx units 459 * @hw: pointer to hardware structure 460 * 461 * Sets the adapter_stopped flag within ixgbe_hw struct. Clears interrupts, 462 * disables transmit and receive units. The adapter_stopped flag is used by 463 * the shared code and drivers to determine if the adapter is in a stopped 464 * state and should not touch the hardware. 465 **/ 466 s32 ixgbe_stop_adapter(struct ixgbe_hw *hw) 467 { 468 return ixgbe_call_func(hw, hw->mac.ops.stop_adapter, (hw), 469 IXGBE_NOT_IMPLEMENTED); 470 } 471 472 /** 473 * ixgbe_read_pba_string - Reads part number string from EEPROM 474 * @hw: pointer to hardware structure 475 * @pba_num: stores the part number string from the EEPROM 476 * @pba_num_size: part number string buffer length 477 * 478 * Reads the part number string from the EEPROM. 479 **/ 480 s32 ixgbe_read_pba_string(struct ixgbe_hw *hw, u8 *pba_num, u32 pba_num_size) 481 { 482 return ixgbe_read_pba_string_generic(hw, pba_num, pba_num_size); 483 } 484 485 /** 486 * ixgbe_read_pba_num - Reads part number from EEPROM 487 * @hw: pointer to hardware structure 488 * @pba_num: stores the part number from the EEPROM 489 * 490 * Reads the part number from the EEPROM. 491 **/ 492 s32 ixgbe_read_pba_num(struct ixgbe_hw *hw, u32 *pba_num) 493 { 494 return ixgbe_read_pba_num_generic(hw, pba_num); 495 } 496 497 /** 498 * ixgbe_identify_phy - Get PHY type 499 * @hw: pointer to hardware structure 500 * 501 * Determines the physical layer module found on the current adapter. 502 **/ 503 s32 ixgbe_identify_phy(struct ixgbe_hw *hw) 504 { 505 s32 status = IXGBE_SUCCESS; 506 507 if (hw->phy.type == ixgbe_phy_unknown) { 508 status = ixgbe_call_func(hw, hw->phy.ops.identify, (hw), 509 IXGBE_NOT_IMPLEMENTED); 510 } 511 512 return status; 513 } 514 515 /** 516 * ixgbe_reset_phy - Perform a PHY reset 517 * @hw: pointer to hardware structure 518 **/ 519 s32 ixgbe_reset_phy(struct ixgbe_hw *hw) 520 { 521 s32 status = IXGBE_SUCCESS; 522 523 if (hw->phy.type == ixgbe_phy_unknown) { 524 if (ixgbe_identify_phy(hw) != IXGBE_SUCCESS) 525 status = IXGBE_ERR_PHY; 526 } 527 528 if (status == IXGBE_SUCCESS) { 529 status = ixgbe_call_func(hw, hw->phy.ops.reset, (hw), 530 IXGBE_NOT_IMPLEMENTED); 531 } 532 return status; 533 } 534 535 /** 536 * ixgbe_get_phy_firmware_version - 537 * @hw: pointer to hardware structure 538 * @firmware_version: pointer to firmware version 539 **/ 540 s32 ixgbe_get_phy_firmware_version(struct ixgbe_hw *hw, u16 *firmware_version) 541 { 542 s32 status = IXGBE_SUCCESS; 543 544 status = ixgbe_call_func(hw, hw->phy.ops.get_firmware_version, 545 (hw, firmware_version), 546 IXGBE_NOT_IMPLEMENTED); 547 return status; 548 } 549 550 /** 551 * ixgbe_read_phy_reg - Read PHY register 552 * @hw: pointer to hardware structure 553 * @reg_addr: 32 bit address of PHY register to read 554 * @device_type: type of device you want to communicate with 555 * @phy_data: Pointer to read data from PHY register 556 * 557 * Reads a value from a specified PHY register 558 **/ 559 s32 ixgbe_read_phy_reg(struct ixgbe_hw *hw, u32 reg_addr, u32 device_type, 560 u16 *phy_data) 561 { 562 if (hw->phy.id == 0) 563 ixgbe_identify_phy(hw); 564 565 return ixgbe_call_func(hw, hw->phy.ops.read_reg, (hw, reg_addr, 566 device_type, phy_data), IXGBE_NOT_IMPLEMENTED); 567 } 568 569 /** 570 * ixgbe_write_phy_reg - Write PHY register 571 * @hw: pointer to hardware structure 572 * @reg_addr: 32 bit PHY register to write 573 * @device_type: type of device you want to communicate with 574 * @phy_data: Data to write to the PHY register 575 * 576 * Writes a value to specified PHY register 577 **/ 578 s32 ixgbe_write_phy_reg(struct ixgbe_hw *hw, u32 reg_addr, u32 device_type, 579 u16 phy_data) 580 { 581 if (hw->phy.id == 0) 582 ixgbe_identify_phy(hw); 583 584 return ixgbe_call_func(hw, hw->phy.ops.write_reg, (hw, reg_addr, 585 device_type, phy_data), IXGBE_NOT_IMPLEMENTED); 586 } 587 588 /** 589 * ixgbe_setup_phy_link - Restart PHY autoneg 590 * @hw: pointer to hardware structure 591 * 592 * Restart autonegotiation and PHY and waits for completion. 593 **/ 594 s32 ixgbe_setup_phy_link(struct ixgbe_hw *hw) 595 { 596 return ixgbe_call_func(hw, hw->phy.ops.setup_link, (hw), 597 IXGBE_NOT_IMPLEMENTED); 598 } 599 600 /** 601 * ixgbe_setup_internal_phy - Configure integrated PHY 602 * @hw: pointer to hardware structure 603 * 604 * Reconfigure the integrated PHY in order to enable talk to the external PHY. 605 * Returns success if not implemented, since nothing needs to be done in this 606 * case. 607 */ 608 s32 ixgbe_setup_internal_phy(struct ixgbe_hw *hw) 609 { 610 return ixgbe_call_func(hw, hw->phy.ops.setup_internal_link, (hw), 611 IXGBE_SUCCESS); 612 } 613 614 /** 615 * ixgbe_check_phy_link - Determine link and speed status 616 * @hw: pointer to hardware structure 617 * @speed: link speed 618 * @link_up: true when link is up 619 * 620 * Reads a PHY register to determine if link is up and the current speed for 621 * the PHY. 622 **/ 623 s32 ixgbe_check_phy_link(struct ixgbe_hw *hw, ixgbe_link_speed *speed, 624 bool *link_up) 625 { 626 return ixgbe_call_func(hw, hw->phy.ops.check_link, (hw, speed, 627 link_up), IXGBE_NOT_IMPLEMENTED); 628 } 629 630 /** 631 * ixgbe_setup_phy_link_speed - Set auto advertise 632 * @hw: pointer to hardware structure 633 * @speed: new link speed 634 * @autoneg_wait_to_complete: true when waiting for completion is needed 635 * 636 * Sets the auto advertised capabilities 637 **/ 638 s32 ixgbe_setup_phy_link_speed(struct ixgbe_hw *hw, ixgbe_link_speed speed, 639 bool autoneg_wait_to_complete) 640 { 641 return ixgbe_call_func(hw, hw->phy.ops.setup_link_speed, (hw, speed, 642 autoneg_wait_to_complete), 643 IXGBE_NOT_IMPLEMENTED); 644 } 645 646 /** 647 * ixgbe_set_phy_power - Control the phy power state 648 * @hw: pointer to hardware structure 649 * @on: true for on, false for off 650 */ 651 s32 ixgbe_set_phy_power(struct ixgbe_hw *hw, bool on) 652 { 653 return ixgbe_call_func(hw, hw->phy.ops.set_phy_power, (hw, on), 654 IXGBE_NOT_IMPLEMENTED); 655 } 656 657 /** 658 * ixgbe_check_link - Get link and speed status 659 * @hw: pointer to hardware structure 660 * @speed: pointer to link speed 661 * @link_up: true when link is up 662 * @link_up_wait_to_complete: bool used to wait for link up or not 663 * 664 * Reads the links register to determine if link is up and the current speed 665 **/ 666 s32 ixgbe_check_link(struct ixgbe_hw *hw, ixgbe_link_speed *speed, 667 bool *link_up, bool link_up_wait_to_complete) 668 { 669 return ixgbe_call_func(hw, hw->mac.ops.check_link, (hw, speed, 670 link_up, link_up_wait_to_complete), 671 IXGBE_NOT_IMPLEMENTED); 672 } 673 674 /** 675 * ixgbe_disable_tx_laser - Disable Tx laser 676 * @hw: pointer to hardware structure 677 * 678 * If the driver needs to disable the laser on SFI optics. 679 **/ 680 void ixgbe_disable_tx_laser(struct ixgbe_hw *hw) 681 { 682 if (hw->mac.ops.disable_tx_laser) 683 hw->mac.ops.disable_tx_laser(hw); 684 } 685 686 /** 687 * ixgbe_enable_tx_laser - Enable Tx laser 688 * @hw: pointer to hardware structure 689 * 690 * If the driver needs to enable the laser on SFI optics. 691 **/ 692 void ixgbe_enable_tx_laser(struct ixgbe_hw *hw) 693 { 694 if (hw->mac.ops.enable_tx_laser) 695 hw->mac.ops.enable_tx_laser(hw); 696 } 697 698 /** 699 * ixgbe_flap_tx_laser - flap Tx laser to start autotry process 700 * @hw: pointer to hardware structure 701 * 702 * When the driver changes the link speeds that it can support then 703 * flap the tx laser to alert the link partner to start autotry 704 * process on its end. 705 **/ 706 void ixgbe_flap_tx_laser(struct ixgbe_hw *hw) 707 { 708 if (hw->mac.ops.flap_tx_laser) 709 hw->mac.ops.flap_tx_laser(hw); 710 } 711 712 /** 713 * ixgbe_setup_link - Set link speed 714 * @hw: pointer to hardware structure 715 * @speed: new link speed 716 * @autoneg_wait_to_complete: true when waiting for completion is needed 717 * 718 * Configures link settings. Restarts the link. 719 * Performs autonegotiation if needed. 720 **/ 721 s32 ixgbe_setup_link(struct ixgbe_hw *hw, ixgbe_link_speed speed, 722 bool autoneg_wait_to_complete) 723 { 724 return ixgbe_call_func(hw, hw->mac.ops.setup_link, (hw, speed, 725 autoneg_wait_to_complete), 726 IXGBE_NOT_IMPLEMENTED); 727 } 728 729 /** 730 * ixgbe_setup_mac_link - Set link speed 731 * @hw: pointer to hardware structure 732 * @speed: new link speed 733 * @autoneg_wait_to_complete: true when waiting for completion is needed 734 * 735 * Configures link settings. Restarts the link. 736 * Performs autonegotiation if needed. 737 **/ 738 s32 ixgbe_setup_mac_link(struct ixgbe_hw *hw, ixgbe_link_speed speed, 739 bool autoneg_wait_to_complete) 740 { 741 return ixgbe_call_func(hw, hw->mac.ops.setup_mac_link, (hw, speed, 742 autoneg_wait_to_complete), 743 IXGBE_NOT_IMPLEMENTED); 744 } 745 746 /** 747 * ixgbe_get_link_capabilities - Returns link capabilities 748 * @hw: pointer to hardware structure 749 * @speed: link speed capabilities 750 * @autoneg: true when autoneg or autotry is enabled 751 * 752 * Determines the link capabilities of the current configuration. 753 **/ 754 s32 ixgbe_get_link_capabilities(struct ixgbe_hw *hw, ixgbe_link_speed *speed, 755 bool *autoneg) 756 { 757 return ixgbe_call_func(hw, hw->mac.ops.get_link_capabilities, (hw, 758 speed, autoneg), IXGBE_NOT_IMPLEMENTED); 759 } 760 761 /** 762 * ixgbe_led_on - Turn on LEDs 763 * @hw: pointer to hardware structure 764 * @index: led number to turn on 765 * 766 * Turns on the software controllable LEDs. 767 **/ 768 s32 ixgbe_led_on(struct ixgbe_hw *hw, u32 index) 769 { 770 return ixgbe_call_func(hw, hw->mac.ops.led_on, (hw, index), 771 IXGBE_NOT_IMPLEMENTED); 772 } 773 774 /** 775 * ixgbe_led_off - Turn off LEDs 776 * @hw: pointer to hardware structure 777 * @index: led number to turn off 778 * 779 * Turns off the software controllable LEDs. 780 **/ 781 s32 ixgbe_led_off(struct ixgbe_hw *hw, u32 index) 782 { 783 return ixgbe_call_func(hw, hw->mac.ops.led_off, (hw, index), 784 IXGBE_NOT_IMPLEMENTED); 785 } 786 787 /** 788 * ixgbe_blink_led_start - Blink LEDs 789 * @hw: pointer to hardware structure 790 * @index: led number to blink 791 * 792 * Blink LED based on index. 793 **/ 794 s32 ixgbe_blink_led_start(struct ixgbe_hw *hw, u32 index) 795 { 796 return ixgbe_call_func(hw, hw->mac.ops.blink_led_start, (hw, index), 797 IXGBE_NOT_IMPLEMENTED); 798 } 799 800 /** 801 * ixgbe_blink_led_stop - Stop blinking LEDs 802 * @hw: pointer to hardware structure 803 * @index: led number to stop 804 * 805 * Stop blinking LED based on index. 806 **/ 807 s32 ixgbe_blink_led_stop(struct ixgbe_hw *hw, u32 index) 808 { 809 return ixgbe_call_func(hw, hw->mac.ops.blink_led_stop, (hw, index), 810 IXGBE_NOT_IMPLEMENTED); 811 } 812 813 /** 814 * ixgbe_init_eeprom_params - Initialize EEPROM parameters 815 * @hw: pointer to hardware structure 816 * 817 * Initializes the EEPROM parameters ixgbe_eeprom_info within the 818 * ixgbe_hw struct in order to set up EEPROM access. 819 **/ 820 s32 ixgbe_init_eeprom_params(struct ixgbe_hw *hw) 821 { 822 return ixgbe_call_func(hw, hw->eeprom.ops.init_params, (hw), 823 IXGBE_NOT_IMPLEMENTED); 824 } 825 826 827 /** 828 * ixgbe_write_eeprom - Write word to EEPROM 829 * @hw: pointer to hardware structure 830 * @offset: offset within the EEPROM to be written to 831 * @data: 16 bit word to be written to the EEPROM 832 * 833 * Writes 16 bit value to EEPROM. If ixgbe_eeprom_update_checksum is not 834 * called after this function, the EEPROM will most likely contain an 835 * invalid checksum. 836 **/ 837 s32 ixgbe_write_eeprom(struct ixgbe_hw *hw, u16 offset, u16 data) 838 { 839 return ixgbe_call_func(hw, hw->eeprom.ops.write, (hw, offset, data), 840 IXGBE_NOT_IMPLEMENTED); 841 } 842 843 /** 844 * ixgbe_write_eeprom_buffer - Write word(s) to EEPROM 845 * @hw: pointer to hardware structure 846 * @offset: offset within the EEPROM to be written to 847 * @data: 16 bit word(s) to be written to the EEPROM 848 * @words: number of words 849 * 850 * Writes 16 bit word(s) to EEPROM. If ixgbe_eeprom_update_checksum is not 851 * called after this function, the EEPROM will most likely contain an 852 * invalid checksum. 853 **/ 854 s32 ixgbe_write_eeprom_buffer(struct ixgbe_hw *hw, u16 offset, u16 words, 855 u16 *data) 856 { 857 return ixgbe_call_func(hw, hw->eeprom.ops.write_buffer, 858 (hw, offset, words, data), 859 IXGBE_NOT_IMPLEMENTED); 860 } 861 862 /** 863 * ixgbe_read_eeprom - Read word from EEPROM 864 * @hw: pointer to hardware structure 865 * @offset: offset within the EEPROM to be read 866 * @data: read 16 bit value from EEPROM 867 * 868 * Reads 16 bit value from EEPROM 869 **/ 870 s32 ixgbe_read_eeprom(struct ixgbe_hw *hw, u16 offset, u16 *data) 871 { 872 return ixgbe_call_func(hw, hw->eeprom.ops.read, (hw, offset, data), 873 IXGBE_NOT_IMPLEMENTED); 874 } 875 876 /** 877 * ixgbe_read_eeprom_buffer - Read word(s) from EEPROM 878 * @hw: pointer to hardware structure 879 * @offset: offset within the EEPROM to be read 880 * @data: read 16 bit word(s) from EEPROM 881 * @words: number of words 882 * 883 * Reads 16 bit word(s) from EEPROM 884 **/ 885 s32 ixgbe_read_eeprom_buffer(struct ixgbe_hw *hw, u16 offset, 886 u16 words, u16 *data) 887 { 888 return ixgbe_call_func(hw, hw->eeprom.ops.read_buffer, 889 (hw, offset, words, data), 890 IXGBE_NOT_IMPLEMENTED); 891 } 892 893 /** 894 * ixgbe_validate_eeprom_checksum - Validate EEPROM checksum 895 * @hw: pointer to hardware structure 896 * @checksum_val: calculated checksum 897 * 898 * Performs checksum calculation and validates the EEPROM checksum 899 **/ 900 s32 ixgbe_validate_eeprom_checksum(struct ixgbe_hw *hw, u16 *checksum_val) 901 { 902 return ixgbe_call_func(hw, hw->eeprom.ops.validate_checksum, 903 (hw, checksum_val), IXGBE_NOT_IMPLEMENTED); 904 } 905 906 /** 907 * ixgbe_update_eeprom_checksum - Updates the EEPROM checksum 908 * @hw: pointer to hardware structure 909 **/ 910 s32 ixgbe_update_eeprom_checksum(struct ixgbe_hw *hw) 911 { 912 return ixgbe_call_func(hw, hw->eeprom.ops.update_checksum, (hw), 913 IXGBE_NOT_IMPLEMENTED); 914 } 915 916 /** 917 * ixgbe_insert_mac_addr - Find a RAR for this mac address 918 * @hw: pointer to hardware structure 919 * @addr: Address to put into receive address register 920 * @vmdq: VMDq pool to assign 921 * 922 * Puts an ethernet address into a receive address register, or 923 * finds the rar that it is already in; adds to the pool list 924 **/ 925 s32 ixgbe_insert_mac_addr(struct ixgbe_hw *hw, u8 *addr, u32 vmdq) 926 { 927 return ixgbe_call_func(hw, hw->mac.ops.insert_mac_addr, 928 (hw, addr, vmdq), 929 IXGBE_NOT_IMPLEMENTED); 930 } 931 932 /** 933 * ixgbe_set_rar - Set Rx address register 934 * @hw: pointer to hardware structure 935 * @index: Receive address register to write 936 * @addr: Address to put into receive address register 937 * @vmdq: VMDq "set" 938 * @enable_addr: set flag that address is active 939 * 940 * Puts an ethernet address into a receive address register. 941 **/ 942 s32 ixgbe_set_rar(struct ixgbe_hw *hw, u32 index, u8 *addr, u32 vmdq, 943 u32 enable_addr) 944 { 945 return ixgbe_call_func(hw, hw->mac.ops.set_rar, (hw, index, addr, vmdq, 946 enable_addr), IXGBE_NOT_IMPLEMENTED); 947 } 948 949 /** 950 * ixgbe_clear_rar - Clear Rx address register 951 * @hw: pointer to hardware structure 952 * @index: Receive address register to write 953 * 954 * Puts an ethernet address into a receive address register. 955 **/ 956 s32 ixgbe_clear_rar(struct ixgbe_hw *hw, u32 index) 957 { 958 return ixgbe_call_func(hw, hw->mac.ops.clear_rar, (hw, index), 959 IXGBE_NOT_IMPLEMENTED); 960 } 961 962 /** 963 * ixgbe_set_vmdq - Associate a VMDq index with a receive address 964 * @hw: pointer to hardware structure 965 * @rar: receive address register index to associate with VMDq index 966 * @vmdq: VMDq set or pool index 967 **/ 968 s32 ixgbe_set_vmdq(struct ixgbe_hw *hw, u32 rar, u32 vmdq) 969 { 970 return ixgbe_call_func(hw, hw->mac.ops.set_vmdq, (hw, rar, vmdq), 971 IXGBE_NOT_IMPLEMENTED); 972 973 } 974 975 /** 976 * ixgbe_set_vmdq_san_mac - Associate VMDq index 127 with a receive address 977 * @hw: pointer to hardware structure 978 * @vmdq: VMDq default pool index 979 **/ 980 s32 ixgbe_set_vmdq_san_mac(struct ixgbe_hw *hw, u32 vmdq) 981 { 982 return ixgbe_call_func(hw, hw->mac.ops.set_vmdq_san_mac, 983 (hw, vmdq), IXGBE_NOT_IMPLEMENTED); 984 } 985 986 /** 987 * ixgbe_clear_vmdq - Disassociate a VMDq index from a receive address 988 * @hw: pointer to hardware structure 989 * @rar: receive address register index to disassociate with VMDq index 990 * @vmdq: VMDq set or pool index 991 **/ 992 s32 ixgbe_clear_vmdq(struct ixgbe_hw *hw, u32 rar, u32 vmdq) 993 { 994 return ixgbe_call_func(hw, hw->mac.ops.clear_vmdq, (hw, rar, vmdq), 995 IXGBE_NOT_IMPLEMENTED); 996 } 997 998 /** 999 * ixgbe_init_rx_addrs - Initializes receive address filters. 1000 * @hw: pointer to hardware structure 1001 * 1002 * Places the MAC address in receive address register 0 and clears the rest 1003 * of the receive address registers. Clears the multicast table. Assumes 1004 * the receiver is in reset when the routine is called. 1005 **/ 1006 s32 ixgbe_init_rx_addrs(struct ixgbe_hw *hw) 1007 { 1008 return ixgbe_call_func(hw, hw->mac.ops.init_rx_addrs, (hw), 1009 IXGBE_NOT_IMPLEMENTED); 1010 } 1011 1012 /** 1013 * ixgbe_get_num_rx_addrs - Returns the number of RAR entries. 1014 * @hw: pointer to hardware structure 1015 **/ 1016 u32 ixgbe_get_num_rx_addrs(struct ixgbe_hw *hw) 1017 { 1018 return hw->mac.num_rar_entries; 1019 } 1020 1021 /** 1022 * ixgbe_update_uc_addr_list - Updates the MAC's list of secondary addresses 1023 * @hw: pointer to hardware structure 1024 * @addr_list: the list of new multicast addresses 1025 * @addr_count: number of addresses 1026 * @func: iterator function to walk the multicast address list 1027 * 1028 * The given list replaces any existing list. Clears the secondary addrs from 1029 * receive address registers. Uses unused receive address registers for the 1030 * first secondary addresses, and falls back to promiscuous mode as needed. 1031 **/ 1032 s32 ixgbe_update_uc_addr_list(struct ixgbe_hw *hw, u8 *addr_list, 1033 u32 addr_count, ixgbe_mc_addr_itr func) 1034 { 1035 return ixgbe_call_func(hw, hw->mac.ops.update_uc_addr_list, (hw, 1036 addr_list, addr_count, func), 1037 IXGBE_NOT_IMPLEMENTED); 1038 } 1039 1040 /** 1041 * ixgbe_update_mc_addr_list - Updates the MAC's list of multicast addresses 1042 * @hw: pointer to hardware structure 1043 * @mc_addr_list: the list of new multicast addresses 1044 * @mc_addr_count: number of addresses 1045 * @func: iterator function to walk the multicast address list 1046 * @clear: flag, when set clears the table beforehand 1047 * 1048 * The given list replaces any existing list. Clears the MC addrs from receive 1049 * address registers and the multicast table. Uses unused receive address 1050 * registers for the first multicast addresses, and hashes the rest into the 1051 * multicast table. 1052 **/ 1053 s32 ixgbe_update_mc_addr_list(struct ixgbe_hw *hw, u8 *mc_addr_list, 1054 u32 mc_addr_count, ixgbe_mc_addr_itr func, 1055 bool clear) 1056 { 1057 return ixgbe_call_func(hw, hw->mac.ops.update_mc_addr_list, (hw, 1058 mc_addr_list, mc_addr_count, func, clear), 1059 IXGBE_NOT_IMPLEMENTED); 1060 } 1061 1062 /** 1063 * ixgbe_enable_mc - Enable multicast address in RAR 1064 * @hw: pointer to hardware structure 1065 * 1066 * Enables multicast address in RAR and the use of the multicast hash table. 1067 **/ 1068 s32 ixgbe_enable_mc(struct ixgbe_hw *hw) 1069 { 1070 return ixgbe_call_func(hw, hw->mac.ops.enable_mc, (hw), 1071 IXGBE_NOT_IMPLEMENTED); 1072 } 1073 1074 /** 1075 * ixgbe_disable_mc - Disable multicast address in RAR 1076 * @hw: pointer to hardware structure 1077 * 1078 * Disables multicast address in RAR and the use of the multicast hash table. 1079 **/ 1080 s32 ixgbe_disable_mc(struct ixgbe_hw *hw) 1081 { 1082 return ixgbe_call_func(hw, hw->mac.ops.disable_mc, (hw), 1083 IXGBE_NOT_IMPLEMENTED); 1084 } 1085 1086 /** 1087 * ixgbe_clear_vfta - Clear VLAN filter table 1088 * @hw: pointer to hardware structure 1089 * 1090 * Clears the VLAN filter table, and the VMDq index associated with the filter 1091 **/ 1092 s32 ixgbe_clear_vfta(struct ixgbe_hw *hw) 1093 { 1094 return ixgbe_call_func(hw, hw->mac.ops.clear_vfta, (hw), 1095 IXGBE_NOT_IMPLEMENTED); 1096 } 1097 1098 /** 1099 * ixgbe_set_vfta - Set VLAN filter table 1100 * @hw: pointer to hardware structure 1101 * @vlan: VLAN id to write to VLAN filter 1102 * @vind: VMDq output index that maps queue to VLAN id in VLVFB 1103 * @vlan_on: boolean flag to turn on/off VLAN 1104 * @vlvf_bypass: boolean flag indicating updating the default pool is okay 1105 * 1106 * Turn on/off specified VLAN in the VLAN filter table. 1107 **/ 1108 s32 ixgbe_set_vfta(struct ixgbe_hw *hw, u32 vlan, u32 vind, bool vlan_on, 1109 bool vlvf_bypass) 1110 { 1111 return ixgbe_call_func(hw, hw->mac.ops.set_vfta, (hw, vlan, vind, 1112 vlan_on, vlvf_bypass), IXGBE_NOT_IMPLEMENTED); 1113 } 1114 1115 /** 1116 * ixgbe_set_vlvf - Set VLAN Pool Filter 1117 * @hw: pointer to hardware structure 1118 * @vlan: VLAN id to write to VLAN filter 1119 * @vind: VMDq output index that maps queue to VLAN id in VLVFB 1120 * @vlan_on: boolean flag to turn on/off VLAN in VLVF 1121 * @vfta_delta: pointer to the difference between the current value of VFTA 1122 * and the desired value 1123 * @vfta: the desired value of the VFTA 1124 * @vlvf_bypass: boolean flag indicating updating the default pool is okay 1125 * 1126 * Turn on/off specified bit in VLVF table. 1127 **/ 1128 s32 ixgbe_set_vlvf(struct ixgbe_hw *hw, u32 vlan, u32 vind, bool vlan_on, 1129 u32 *vfta_delta, u32 vfta, bool vlvf_bypass) 1130 { 1131 return ixgbe_call_func(hw, hw->mac.ops.set_vlvf, (hw, vlan, vind, 1132 vlan_on, vfta_delta, vfta, vlvf_bypass), 1133 IXGBE_NOT_IMPLEMENTED); 1134 } 1135 1136 /** 1137 * ixgbe_toggle_txdctl - Toggle VF's queues 1138 * @hw: pointer to hardware structure 1139 * @vind: VMDq pool index 1140 * 1141 * Enable and disable each queue in VF. 1142 */ 1143 s32 ixgbe_toggle_txdctl(struct ixgbe_hw *hw, u32 vind) 1144 { 1145 return ixgbe_call_func(hw, hw->mac.ops.toggle_txdctl, (hw, 1146 vind), IXGBE_NOT_IMPLEMENTED); 1147 } 1148 1149 /** 1150 * ixgbe_fc_enable - Enable flow control 1151 * @hw: pointer to hardware structure 1152 * 1153 * Configures the flow control settings based on SW configuration. 1154 **/ 1155 s32 ixgbe_fc_enable(struct ixgbe_hw *hw) 1156 { 1157 return ixgbe_call_func(hw, hw->mac.ops.fc_enable, (hw), 1158 IXGBE_NOT_IMPLEMENTED); 1159 } 1160 1161 /** 1162 * ixgbe_setup_fc - Set up flow control 1163 * @hw: pointer to hardware structure 1164 * 1165 * Called at init time to set up flow control. 1166 **/ 1167 s32 ixgbe_setup_fc(struct ixgbe_hw *hw) 1168 { 1169 return ixgbe_call_func(hw, hw->mac.ops.setup_fc, (hw), 1170 IXGBE_NOT_IMPLEMENTED); 1171 } 1172 1173 /** 1174 * ixgbe_set_fw_drv_ver - Try to send the driver version number FW 1175 * @hw: pointer to hardware structure 1176 * @maj: driver major number to be sent to firmware 1177 * @min: driver minor number to be sent to firmware 1178 * @build: driver build number to be sent to firmware 1179 * @ver: driver version number to be sent to firmware 1180 * @len: length of driver_ver string 1181 * @driver_ver: driver string 1182 **/ 1183 s32 ixgbe_set_fw_drv_ver(struct ixgbe_hw *hw, u8 maj, u8 min, u8 build, 1184 u8 ver, u16 len, char *driver_ver) 1185 { 1186 return ixgbe_call_func(hw, hw->mac.ops.set_fw_drv_ver, (hw, maj, min, 1187 build, ver, len, driver_ver), 1188 IXGBE_NOT_IMPLEMENTED); 1189 } 1190 1191 1192 /** 1193 * ixgbe_get_thermal_sensor_data - Gathers thermal sensor data 1194 * @hw: pointer to hardware structure 1195 * 1196 * Updates the temperatures in mac.thermal_sensor_data 1197 **/ 1198 s32 ixgbe_get_thermal_sensor_data(struct ixgbe_hw *hw) 1199 { 1200 return ixgbe_call_func(hw, hw->mac.ops.get_thermal_sensor_data, (hw), 1201 IXGBE_NOT_IMPLEMENTED); 1202 } 1203 1204 /** 1205 * ixgbe_init_thermal_sensor_thresh - Inits thermal sensor thresholds 1206 * @hw: pointer to hardware structure 1207 * 1208 * Inits the thermal sensor thresholds according to the NVM map 1209 **/ 1210 s32 ixgbe_init_thermal_sensor_thresh(struct ixgbe_hw *hw) 1211 { 1212 return ixgbe_call_func(hw, hw->mac.ops.init_thermal_sensor_thresh, (hw), 1213 IXGBE_NOT_IMPLEMENTED); 1214 } 1215 1216 /** 1217 * ixgbe_dmac_config - Configure DMA Coalescing registers. 1218 * @hw: pointer to hardware structure 1219 * 1220 * Configure DMA coalescing. If enabling dmac, dmac is activated. 1221 * When disabling dmac, dmac enable dmac bit is cleared. 1222 **/ 1223 s32 ixgbe_dmac_config(struct ixgbe_hw *hw) 1224 { 1225 return ixgbe_call_func(hw, hw->mac.ops.dmac_config, (hw), 1226 IXGBE_NOT_IMPLEMENTED); 1227 } 1228 1229 /** 1230 * ixgbe_dmac_update_tcs - Configure DMA Coalescing registers. 1231 * @hw: pointer to hardware structure 1232 * 1233 * Disables dmac, updates per TC settings, and then enable dmac. 1234 **/ 1235 s32 ixgbe_dmac_update_tcs(struct ixgbe_hw *hw) 1236 { 1237 return ixgbe_call_func(hw, hw->mac.ops.dmac_update_tcs, (hw), 1238 IXGBE_NOT_IMPLEMENTED); 1239 } 1240 1241 /** 1242 * ixgbe_dmac_config_tcs - Configure DMA Coalescing registers. 1243 * @hw: pointer to hardware structure 1244 * 1245 * Configure DMA coalescing threshold per TC and set high priority bit for 1246 * FCOE TC. The dmac enable bit must be cleared before configuring. 1247 **/ 1248 s32 ixgbe_dmac_config_tcs(struct ixgbe_hw *hw) 1249 { 1250 return ixgbe_call_func(hw, hw->mac.ops.dmac_config_tcs, (hw), 1251 IXGBE_NOT_IMPLEMENTED); 1252 } 1253 1254 /** 1255 * ixgbe_setup_eee - Enable/disable EEE support 1256 * @hw: pointer to the HW structure 1257 * @enable_eee: boolean flag to enable EEE 1258 * 1259 * Enable/disable EEE based on enable_ee flag. 1260 * Auto-negotiation must be started after BASE-T EEE bits in PHY register 7.3C 1261 * are modified. 1262 * 1263 **/ 1264 s32 ixgbe_setup_eee(struct ixgbe_hw *hw, bool enable_eee) 1265 { 1266 return ixgbe_call_func(hw, hw->mac.ops.setup_eee, (hw, enable_eee), 1267 IXGBE_NOT_IMPLEMENTED); 1268 } 1269 1270 /** 1271 * ixgbe_set_source_address_pruning - Enable/Disable source address pruning 1272 * @hw: pointer to hardware structure 1273 * @enable: enable or disable source address pruning 1274 * @pool: Rx pool - Rx pool to toggle source address pruning 1275 **/ 1276 void ixgbe_set_source_address_pruning(struct ixgbe_hw *hw, bool enable, 1277 unsigned int pool) 1278 { 1279 if (hw->mac.ops.set_source_address_pruning) 1280 hw->mac.ops.set_source_address_pruning(hw, enable, pool); 1281 } 1282 1283 /** 1284 * ixgbe_set_ethertype_anti_spoofing - Enable/Disable Ethertype anti-spoofing 1285 * @hw: pointer to hardware structure 1286 * @enable: enable or disable switch for Ethertype anti-spoofing 1287 * @vf: Virtual Function pool - VF Pool to set for Ethertype anti-spoofing 1288 * 1289 **/ 1290 void ixgbe_set_ethertype_anti_spoofing(struct ixgbe_hw *hw, bool enable, int vf) 1291 { 1292 if (hw->mac.ops.set_ethertype_anti_spoofing) 1293 hw->mac.ops.set_ethertype_anti_spoofing(hw, enable, vf); 1294 } 1295 1296 /** 1297 * ixgbe_read_iosf_sb_reg - Read 32 bit PHY register 1298 * @hw: pointer to hardware structure 1299 * @reg_addr: 32 bit address of PHY register to read 1300 * @device_type: type of device you want to communicate with 1301 * @phy_data: Pointer to read data from PHY register 1302 * 1303 * Reads a value from a specified PHY register 1304 **/ 1305 s32 ixgbe_read_iosf_sb_reg(struct ixgbe_hw *hw, u32 reg_addr, 1306 u32 device_type, u32 *phy_data) 1307 { 1308 return ixgbe_call_func(hw, hw->mac.ops.read_iosf_sb_reg, (hw, reg_addr, 1309 device_type, phy_data), IXGBE_NOT_IMPLEMENTED); 1310 } 1311 1312 /** 1313 * ixgbe_write_iosf_sb_reg - Write 32 bit register through IOSF Sideband 1314 * @hw: pointer to hardware structure 1315 * @reg_addr: 32 bit PHY register to write 1316 * @device_type: type of device you want to communicate with 1317 * @phy_data: Data to write to the PHY register 1318 * 1319 * Writes a value to specified PHY register 1320 **/ 1321 s32 ixgbe_write_iosf_sb_reg(struct ixgbe_hw *hw, u32 reg_addr, 1322 u32 device_type, u32 phy_data) 1323 { 1324 return ixgbe_call_func(hw, hw->mac.ops.write_iosf_sb_reg, (hw, reg_addr, 1325 device_type, phy_data), IXGBE_NOT_IMPLEMENTED); 1326 } 1327 1328 /** 1329 * ixgbe_disable_mdd - Disable malicious driver detection 1330 * @hw: pointer to hardware structure 1331 * 1332 **/ 1333 void ixgbe_disable_mdd(struct ixgbe_hw *hw) 1334 { 1335 if (hw->mac.ops.disable_mdd) 1336 hw->mac.ops.disable_mdd(hw); 1337 } 1338 1339 /** 1340 * ixgbe_enable_mdd - Enable malicious driver detection 1341 * @hw: pointer to hardware structure 1342 * 1343 **/ 1344 void ixgbe_enable_mdd(struct ixgbe_hw *hw) 1345 { 1346 if (hw->mac.ops.enable_mdd) 1347 hw->mac.ops.enable_mdd(hw); 1348 } 1349 1350 /** 1351 * ixgbe_mdd_event - Handle malicious driver detection event 1352 * @hw: pointer to hardware structure 1353 * @vf_bitmap: vf bitmap of malicious vfs 1354 * 1355 **/ 1356 void ixgbe_mdd_event(struct ixgbe_hw *hw, u32 *vf_bitmap) 1357 { 1358 if (hw->mac.ops.mdd_event) 1359 hw->mac.ops.mdd_event(hw, vf_bitmap); 1360 } 1361 1362 /** 1363 * ixgbe_restore_mdd_vf - Restore VF that was disabled during malicious driver 1364 * detection event 1365 * @hw: pointer to hardware structure 1366 * @vf: vf index 1367 * 1368 **/ 1369 void ixgbe_restore_mdd_vf(struct ixgbe_hw *hw, u32 vf) 1370 { 1371 if (hw->mac.ops.restore_mdd_vf) 1372 hw->mac.ops.restore_mdd_vf(hw, vf); 1373 } 1374 1375 /** 1376 * ixgbe_fw_recovery_mode - Check if in FW NVM recovery mode 1377 * @hw: pointer to hardware structure 1378 * 1379 **/ 1380 bool ixgbe_fw_recovery_mode(struct ixgbe_hw *hw) 1381 { 1382 if (hw->mac.ops.fw_recovery_mode) 1383 return hw->mac.ops.fw_recovery_mode(hw); 1384 return false; 1385 } 1386 1387 /** 1388 * ixgbe_enter_lplu - Transition to low power states 1389 * @hw: pointer to hardware structure 1390 * 1391 * Configures Low Power Link Up on transition to low power states 1392 * (from D0 to non-D0). 1393 **/ 1394 s32 ixgbe_enter_lplu(struct ixgbe_hw *hw) 1395 { 1396 return ixgbe_call_func(hw, hw->phy.ops.enter_lplu, (hw), 1397 IXGBE_NOT_IMPLEMENTED); 1398 } 1399 1400 /** 1401 * ixgbe_handle_lasi - Handle external Base T PHY interrupt 1402 * @hw: pointer to hardware structure 1403 * 1404 * Handle external Base T PHY interrupt. If high temperature 1405 * failure alarm then return error, else if link status change 1406 * then setup internal/external PHY link 1407 * 1408 * Return IXGBE_ERR_OVERTEMP if interrupt is high temperature 1409 * failure alarm, else return PHY access status. 1410 */ 1411 s32 ixgbe_handle_lasi(struct ixgbe_hw *hw) 1412 { 1413 return ixgbe_call_func(hw, hw->phy.ops.handle_lasi, (hw), 1414 IXGBE_NOT_IMPLEMENTED); 1415 } 1416 1417 /** 1418 * ixgbe_bypass_rw - Bit bang data into by_pass FW 1419 * @hw: pointer to hardware structure 1420 * @cmd: Command we send to the FW 1421 * @status: The reply from the FW 1422 * 1423 * Bit-bangs the cmd to the by_pass FW status points to what is returned. 1424 **/ 1425 s32 ixgbe_bypass_rw(struct ixgbe_hw *hw, u32 cmd, u32 *status) 1426 { 1427 return ixgbe_call_func(hw, hw->mac.ops.bypass_rw, (hw, cmd, status), 1428 IXGBE_NOT_IMPLEMENTED); 1429 } 1430 1431 /** 1432 * ixgbe_bypass_valid_rd - Verify valid return from bit-bang. 1433 * @hw: pointer to hardware structure 1434 * @in_reg: The register cmd for the bit-bang read. 1435 * @out_reg: The register returned from a bit-bang read. 1436 * 1437 * If we send a write we can't be sure it took until we can read back 1438 * that same register. It can be a problem as some of the fields may 1439 * for valid reasons change inbetween the time wrote the register and 1440 * we read it again to verify. So this function check everything we 1441 * can check and then assumes it worked. 1442 **/ 1443 bool ixgbe_bypass_valid_rd(struct ixgbe_hw *hw, u32 in_reg, u32 out_reg) 1444 { 1445 return ixgbe_call_func(hw, hw->mac.ops.bypass_valid_rd, 1446 (in_reg, out_reg), IXGBE_NOT_IMPLEMENTED); 1447 } 1448 1449 /** 1450 * ixgbe_bypass_set - Set a bypass field in the FW CTRL Regiter. 1451 * @hw: pointer to hardware structure 1452 * @cmd: The control word we are setting. 1453 * @event: The event we are setting in the FW. This also happens to 1454 * be the mask for the event we are setting (handy) 1455 * @action: The action we set the event to in the FW. This is in a 1456 * bit field that happens to be what we want to put in 1457 * the event spot (also handy) 1458 * 1459 * Writes to the cmd control the bits in actions. 1460 **/ 1461 s32 ixgbe_bypass_set(struct ixgbe_hw *hw, u32 cmd, u32 event, u32 action) 1462 { 1463 return ixgbe_call_func(hw, hw->mac.ops.bypass_set, 1464 (hw, cmd, event, action), 1465 IXGBE_NOT_IMPLEMENTED); 1466 } 1467 1468 /** 1469 * ixgbe_bypass_rd_eep - Read the bypass FW eeprom address 1470 * @hw: pointer to hardware structure 1471 * @addr: The bypass eeprom address to read. 1472 * @value: The 8b of data at the address above. 1473 **/ 1474 s32 ixgbe_bypass_rd_eep(struct ixgbe_hw *hw, u32 addr, u8 *value) 1475 { 1476 return ixgbe_call_func(hw, hw->mac.ops.bypass_rd_eep, 1477 (hw, addr, value), IXGBE_NOT_IMPLEMENTED); 1478 } 1479 1480 /** 1481 * ixgbe_read_analog_reg8 - Reads 8 bit analog register 1482 * @hw: pointer to hardware structure 1483 * @reg: analog register to read 1484 * @val: read value 1485 * 1486 * Performs write operation to analog register specified. 1487 **/ 1488 s32 ixgbe_read_analog_reg8(struct ixgbe_hw *hw, u32 reg, u8 *val) 1489 { 1490 return ixgbe_call_func(hw, hw->mac.ops.read_analog_reg8, (hw, reg, 1491 val), IXGBE_NOT_IMPLEMENTED); 1492 } 1493 1494 /** 1495 * ixgbe_write_analog_reg8 - Writes 8 bit analog register 1496 * @hw: pointer to hardware structure 1497 * @reg: analog register to write 1498 * @val: value to write 1499 * 1500 * Performs write operation to Atlas analog register specified. 1501 **/ 1502 s32 ixgbe_write_analog_reg8(struct ixgbe_hw *hw, u32 reg, u8 val) 1503 { 1504 return ixgbe_call_func(hw, hw->mac.ops.write_analog_reg8, (hw, reg, 1505 val), IXGBE_NOT_IMPLEMENTED); 1506 } 1507 1508 /** 1509 * ixgbe_init_uta_tables - Initializes Unicast Table Arrays. 1510 * @hw: pointer to hardware structure 1511 * 1512 * Initializes the Unicast Table Arrays to zero on device load. This 1513 * is part of the Rx init addr execution path. 1514 **/ 1515 s32 ixgbe_init_uta_tables(struct ixgbe_hw *hw) 1516 { 1517 return ixgbe_call_func(hw, hw->mac.ops.init_uta_tables, (hw), 1518 IXGBE_NOT_IMPLEMENTED); 1519 } 1520 1521 /** 1522 * ixgbe_read_i2c_byte - Reads 8 bit word over I2C at specified device address 1523 * @hw: pointer to hardware structure 1524 * @byte_offset: byte offset to read 1525 * @dev_addr: I2C bus address to read from 1526 * @data: value read 1527 * 1528 * Performs byte read operation to SFP module's EEPROM over I2C interface. 1529 **/ 1530 s32 ixgbe_read_i2c_byte(struct ixgbe_hw *hw, u8 byte_offset, u8 dev_addr, 1531 u8 *data) 1532 { 1533 return ixgbe_call_func(hw, hw->phy.ops.read_i2c_byte, (hw, byte_offset, 1534 dev_addr, data), IXGBE_NOT_IMPLEMENTED); 1535 } 1536 1537 /** 1538 * ixgbe_read_i2c_byte_unlocked - Reads 8 bit word via I2C from device address 1539 * @hw: pointer to hardware structure 1540 * @byte_offset: byte offset to read 1541 * @dev_addr: I2C bus address to read from 1542 * @data: value read 1543 * 1544 * Performs byte read operation to SFP module's EEPROM over I2C interface. 1545 **/ 1546 s32 ixgbe_read_i2c_byte_unlocked(struct ixgbe_hw *hw, u8 byte_offset, 1547 u8 dev_addr, u8 *data) 1548 { 1549 return ixgbe_call_func(hw, hw->phy.ops.read_i2c_byte_unlocked, 1550 (hw, byte_offset, dev_addr, data), 1551 IXGBE_NOT_IMPLEMENTED); 1552 } 1553 1554 /** 1555 * ixgbe_read_link - Perform read operation on link device 1556 * @hw: pointer to the hardware structure 1557 * @addr: bus address to read from 1558 * @reg: device register to read from 1559 * @val: pointer to location to receive read value 1560 * 1561 * Returns an error code on error. 1562 */ 1563 s32 ixgbe_read_link(struct ixgbe_hw *hw, u8 addr, u16 reg, u16 *val) 1564 { 1565 return ixgbe_call_func(hw, hw->link.ops.read_link, (hw, addr, 1566 reg, val), IXGBE_NOT_IMPLEMENTED); 1567 } 1568 1569 /** 1570 * ixgbe_read_link_unlocked - Perform read operation on link device 1571 * @hw: pointer to the hardware structure 1572 * @addr: bus address to read from 1573 * @reg: device register to read from 1574 * @val: pointer to location to receive read value 1575 * 1576 * Returns an error code on error. 1577 **/ 1578 s32 ixgbe_read_link_unlocked(struct ixgbe_hw *hw, u8 addr, u16 reg, u16 *val) 1579 { 1580 return ixgbe_call_func(hw, hw->link.ops.read_link_unlocked, 1581 (hw, addr, reg, val), IXGBE_NOT_IMPLEMENTED); 1582 } 1583 1584 /** 1585 * ixgbe_write_i2c_byte - Writes 8 bit word over I2C 1586 * @hw: pointer to hardware structure 1587 * @byte_offset: byte offset to write 1588 * @dev_addr: I2C bus address to write to 1589 * @data: value to write 1590 * 1591 * Performs byte write operation to SFP module's EEPROM over I2C interface 1592 * at a specified device address. 1593 **/ 1594 s32 ixgbe_write_i2c_byte(struct ixgbe_hw *hw, u8 byte_offset, u8 dev_addr, 1595 u8 data) 1596 { 1597 return ixgbe_call_func(hw, hw->phy.ops.write_i2c_byte, (hw, byte_offset, 1598 dev_addr, data), IXGBE_NOT_IMPLEMENTED); 1599 } 1600 1601 /** 1602 * ixgbe_write_i2c_byte_unlocked - Writes 8 bit word over I2C 1603 * @hw: pointer to hardware structure 1604 * @byte_offset: byte offset to write 1605 * @dev_addr: I2C bus address to write to 1606 * @data: value to write 1607 * 1608 * Performs byte write operation to SFP module's EEPROM over I2C interface 1609 * at a specified device address. 1610 **/ 1611 s32 ixgbe_write_i2c_byte_unlocked(struct ixgbe_hw *hw, u8 byte_offset, 1612 u8 dev_addr, u8 data) 1613 { 1614 return ixgbe_call_func(hw, hw->phy.ops.write_i2c_byte_unlocked, 1615 (hw, byte_offset, dev_addr, data), 1616 IXGBE_NOT_IMPLEMENTED); 1617 } 1618 1619 /** 1620 * ixgbe_write_link - Perform write operation on link device 1621 * @hw: pointer to the hardware structure 1622 * @addr: bus address to write to 1623 * @reg: device register to write to 1624 * @val: value to write 1625 * 1626 * Returns an error code on error. 1627 */ 1628 s32 ixgbe_write_link(struct ixgbe_hw *hw, u8 addr, u16 reg, u16 val) 1629 { 1630 return ixgbe_call_func(hw, hw->link.ops.write_link, 1631 (hw, addr, reg, val), IXGBE_NOT_IMPLEMENTED); 1632 } 1633 1634 /** 1635 * ixgbe_write_link_unlocked - Perform write operation on link device 1636 * @hw: pointer to the hardware structure 1637 * @addr: bus address to write to 1638 * @reg: device register to write to 1639 * @val: value to write 1640 * 1641 * Returns an error code on error. 1642 **/ 1643 s32 ixgbe_write_link_unlocked(struct ixgbe_hw *hw, u8 addr, u16 reg, u16 val) 1644 { 1645 return ixgbe_call_func(hw, hw->link.ops.write_link_unlocked, 1646 (hw, addr, reg, val), IXGBE_NOT_IMPLEMENTED); 1647 } 1648 1649 /** 1650 * ixgbe_write_i2c_eeprom - Writes 8 bit EEPROM word over I2C interface 1651 * @hw: pointer to hardware structure 1652 * @byte_offset: EEPROM byte offset to write 1653 * @eeprom_data: value to write 1654 * 1655 * Performs byte write operation to SFP module's EEPROM over I2C interface. 1656 **/ 1657 s32 ixgbe_write_i2c_eeprom(struct ixgbe_hw *hw, 1658 u8 byte_offset, u8 eeprom_data) 1659 { 1660 return ixgbe_call_func(hw, hw->phy.ops.write_i2c_eeprom, 1661 (hw, byte_offset, eeprom_data), 1662 IXGBE_NOT_IMPLEMENTED); 1663 } 1664 1665 /** 1666 * ixgbe_read_i2c_eeprom - Reads 8 bit EEPROM word over I2C interface 1667 * @hw: pointer to hardware structure 1668 * @byte_offset: EEPROM byte offset to read 1669 * @eeprom_data: value read 1670 * 1671 * Performs byte read operation to SFP module's EEPROM over I2C interface. 1672 **/ 1673 s32 ixgbe_read_i2c_eeprom(struct ixgbe_hw *hw, u8 byte_offset, u8 *eeprom_data) 1674 { 1675 return ixgbe_call_func(hw, hw->phy.ops.read_i2c_eeprom, 1676 (hw, byte_offset, eeprom_data), 1677 IXGBE_NOT_IMPLEMENTED); 1678 } 1679 1680 /** 1681 * ixgbe_get_supported_physical_layer - Returns physical layer type 1682 * @hw: pointer to hardware structure 1683 * 1684 * Determines physical layer capabilities of the current configuration. 1685 **/ 1686 u64 ixgbe_get_supported_physical_layer(struct ixgbe_hw *hw) 1687 { 1688 return ixgbe_call_func(hw, hw->mac.ops.get_supported_physical_layer, 1689 (hw), IXGBE_PHYSICAL_LAYER_UNKNOWN); 1690 } 1691 1692 /** 1693 * ixgbe_enable_rx_dma - Enables Rx DMA unit, dependent on device specifics 1694 * @hw: pointer to hardware structure 1695 * @regval: bitfield to write to the Rx DMA register 1696 * 1697 * Enables the Rx DMA unit of the device. 1698 **/ 1699 s32 ixgbe_enable_rx_dma(struct ixgbe_hw *hw, u32 regval) 1700 { 1701 return ixgbe_call_func(hw, hw->mac.ops.enable_rx_dma, 1702 (hw, regval), IXGBE_NOT_IMPLEMENTED); 1703 } 1704 1705 /** 1706 * ixgbe_disable_sec_rx_path - Stops the receive data path 1707 * @hw: pointer to hardware structure 1708 * 1709 * Stops the receive data path. 1710 **/ 1711 s32 ixgbe_disable_sec_rx_path(struct ixgbe_hw *hw) 1712 { 1713 return ixgbe_call_func(hw, hw->mac.ops.disable_sec_rx_path, 1714 (hw), IXGBE_NOT_IMPLEMENTED); 1715 } 1716 1717 /** 1718 * ixgbe_enable_sec_rx_path - Enables the receive data path 1719 * @hw: pointer to hardware structure 1720 * 1721 * Enables the receive data path. 1722 **/ 1723 s32 ixgbe_enable_sec_rx_path(struct ixgbe_hw *hw) 1724 { 1725 return ixgbe_call_func(hw, hw->mac.ops.enable_sec_rx_path, 1726 (hw), IXGBE_NOT_IMPLEMENTED); 1727 } 1728 1729 /** 1730 * ixgbe_acquire_swfw_semaphore - Acquire SWFW semaphore 1731 * @hw: pointer to hardware structure 1732 * @mask: Mask to specify which semaphore to acquire 1733 * 1734 * Acquires the SWFW semaphore through SW_FW_SYNC register for the specified 1735 * function (CSR, PHY0, PHY1, EEPROM, Flash) 1736 **/ 1737 s32 ixgbe_acquire_swfw_semaphore(struct ixgbe_hw *hw, u32 mask) 1738 { 1739 return ixgbe_call_func(hw, hw->mac.ops.acquire_swfw_sync, 1740 (hw, mask), IXGBE_NOT_IMPLEMENTED); 1741 } 1742 1743 /** 1744 * ixgbe_release_swfw_semaphore - Release SWFW semaphore 1745 * @hw: pointer to hardware structure 1746 * @mask: Mask to specify which semaphore to release 1747 * 1748 * Releases the SWFW semaphore through SW_FW_SYNC register for the specified 1749 * function (CSR, PHY0, PHY1, EEPROM, Flash) 1750 **/ 1751 void ixgbe_release_swfw_semaphore(struct ixgbe_hw *hw, u32 mask) 1752 { 1753 if (hw->mac.ops.release_swfw_sync) 1754 hw->mac.ops.release_swfw_sync(hw, mask); 1755 } 1756 1757 /** 1758 * ixgbe_init_swfw_semaphore - Clean up SWFW semaphore 1759 * @hw: pointer to hardware structure 1760 * 1761 * Attempts to acquire the SWFW semaphore through SW_FW_SYNC register. 1762 * Regardless of whether is succeeds or not it then release the semaphore. 1763 * This is function is called to recover from catastrophic failures that 1764 * may have left the semaphore locked. 1765 **/ 1766 void ixgbe_init_swfw_semaphore(struct ixgbe_hw *hw) 1767 { 1768 if (hw->mac.ops.init_swfw_sync) 1769 hw->mac.ops.init_swfw_sync(hw); 1770 } 1771 1772 1773 void ixgbe_disable_rx(struct ixgbe_hw *hw) 1774 { 1775 if (hw->mac.ops.disable_rx) 1776 hw->mac.ops.disable_rx(hw); 1777 } 1778 1779 void ixgbe_enable_rx(struct ixgbe_hw *hw) 1780 { 1781 if (hw->mac.ops.enable_rx) 1782 hw->mac.ops.enable_rx(hw); 1783 } 1784 1785 /** 1786 * ixgbe_set_rate_select_speed - Set module link speed 1787 * @hw: pointer to hardware structure 1788 * @speed: link speed to set 1789 * 1790 * Set module link speed via the rate select. 1791 */ 1792 void ixgbe_set_rate_select_speed(struct ixgbe_hw *hw, ixgbe_link_speed speed) 1793 { 1794 if (hw->mac.ops.set_rate_select_speed) 1795 hw->mac.ops.set_rate_select_speed(hw, speed); 1796 } 1797