1 /****************************************************************************** 2 3 Copyright (c) 2001-2012, Intel Corporation 4 All rights reserved. 5 6 Redistribution and use in source and binary forms, with or without 7 modification, are permitted provided that the following conditions are met: 8 9 1. Redistributions of source code must retain the above copyright notice, 10 this list of conditions and the following disclaimer. 11 12 2. Redistributions in binary form must reproduce the above copyright 13 notice, this list of conditions and the following disclaimer in the 14 documentation and/or other materials provided with the distribution. 15 16 3. Neither the name of the Intel Corporation nor the names of its 17 contributors may be used to endorse or promote products derived from 18 this software without specific prior written permission. 19 20 THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 21 AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 22 IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 23 ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE 24 LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 25 CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 26 SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 27 INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 28 CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 29 ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 30 POSSIBILITY OF SUCH DAMAGE. 31 32 ******************************************************************************/ 33 /*$FreeBSD$*/ 34 35 #include "ixgbe_api.h" 36 #include "ixgbe_common.h" 37 38 /** 39 * ixgbe_init_shared_code - Initialize the shared code 40 * @hw: pointer to hardware structure 41 * 42 * This will assign function pointers and assign the MAC type and PHY code. 43 * Does not touch the hardware. This function must be called prior to any 44 * other function in the shared code. The ixgbe_hw structure should be 45 * memset to 0 prior to calling this function. The following fields in 46 * hw structure should be filled in prior to calling this function: 47 * hw_addr, back, device_id, vendor_id, subsystem_device_id, 48 * subsystem_vendor_id, and revision_id 49 **/ 50 s32 ixgbe_init_shared_code(struct ixgbe_hw *hw) 51 { 52 s32 status; 53 54 DEBUGFUNC("ixgbe_init_shared_code"); 55 56 /* 57 * Set the mac type 58 */ 59 ixgbe_set_mac_type(hw); 60 61 switch (hw->mac.type) { 62 case ixgbe_mac_82598EB: 63 status = ixgbe_init_ops_82598(hw); 64 break; 65 case ixgbe_mac_82599EB: 66 status = ixgbe_init_ops_82599(hw); 67 break; 68 case ixgbe_mac_82599_vf: 69 case ixgbe_mac_X540_vf: 70 status = ixgbe_init_ops_vf(hw); 71 break; 72 case ixgbe_mac_X540: 73 status = ixgbe_init_ops_X540(hw); 74 break; 75 default: 76 status = IXGBE_ERR_DEVICE_NOT_SUPPORTED; 77 break; 78 } 79 80 return status; 81 } 82 83 /** 84 * ixgbe_set_mac_type - Sets MAC type 85 * @hw: pointer to the HW structure 86 * 87 * This function sets the mac type of the adapter based on the 88 * vendor ID and device ID stored in the hw structure. 89 **/ 90 s32 ixgbe_set_mac_type(struct ixgbe_hw *hw) 91 { 92 s32 ret_val = IXGBE_SUCCESS; 93 94 DEBUGFUNC("ixgbe_set_mac_type\n"); 95 96 if (hw->vendor_id == IXGBE_INTEL_VENDOR_ID) { 97 switch (hw->device_id) { 98 case IXGBE_DEV_ID_82598: 99 case IXGBE_DEV_ID_82598_BX: 100 case IXGBE_DEV_ID_82598AF_SINGLE_PORT: 101 case IXGBE_DEV_ID_82598AF_DUAL_PORT: 102 case IXGBE_DEV_ID_82598AT: 103 case IXGBE_DEV_ID_82598AT2: 104 case IXGBE_DEV_ID_82598EB_CX4: 105 case IXGBE_DEV_ID_82598_CX4_DUAL_PORT: 106 case IXGBE_DEV_ID_82598_DA_DUAL_PORT: 107 case IXGBE_DEV_ID_82598_SR_DUAL_PORT_EM: 108 case IXGBE_DEV_ID_82598EB_XF_LR: 109 case IXGBE_DEV_ID_82598EB_SFP_LOM: 110 hw->mac.type = ixgbe_mac_82598EB; 111 break; 112 case IXGBE_DEV_ID_82599_KX4: 113 case IXGBE_DEV_ID_82599_KX4_MEZZ: 114 case IXGBE_DEV_ID_82599_XAUI_LOM: 115 case IXGBE_DEV_ID_82599_COMBO_BACKPLANE: 116 case IXGBE_DEV_ID_82599_KR: 117 case IXGBE_DEV_ID_82599_SFP: 118 case IXGBE_DEV_ID_82599_BACKPLANE_FCOE: 119 case IXGBE_DEV_ID_82599_SFP_FCOE: 120 case IXGBE_DEV_ID_82599_SFP_EM: 121 case IXGBE_DEV_ID_82599EN_SFP: 122 case IXGBE_DEV_ID_82599_CX4: 123 case IXGBE_DEV_ID_82599_T3_LOM: 124 hw->mac.type = ixgbe_mac_82599EB; 125 break; 126 case IXGBE_DEV_ID_82599_VF: 127 hw->mac.type = ixgbe_mac_82599_vf; 128 break; 129 case IXGBE_DEV_ID_X540_VF: 130 hw->mac.type = ixgbe_mac_X540_vf; 131 break; 132 case IXGBE_DEV_ID_X540T: 133 hw->mac.type = ixgbe_mac_X540; 134 break; 135 default: 136 ret_val = IXGBE_ERR_DEVICE_NOT_SUPPORTED; 137 break; 138 } 139 } else { 140 ret_val = IXGBE_ERR_DEVICE_NOT_SUPPORTED; 141 } 142 143 DEBUGOUT2("ixgbe_set_mac_type found mac: %d, returns: %d\n", 144 hw->mac.type, ret_val); 145 return ret_val; 146 } 147 148 /** 149 * ixgbe_init_hw - Initialize the hardware 150 * @hw: pointer to hardware structure 151 * 152 * Initialize the hardware by resetting and then starting the hardware 153 **/ 154 s32 ixgbe_init_hw(struct ixgbe_hw *hw) 155 { 156 return ixgbe_call_func(hw, hw->mac.ops.init_hw, (hw), 157 IXGBE_NOT_IMPLEMENTED); 158 } 159 160 /** 161 * ixgbe_reset_hw - Performs a hardware reset 162 * @hw: pointer to hardware structure 163 * 164 * Resets the hardware by resetting the transmit and receive units, masks and 165 * clears all interrupts, performs a PHY reset, and performs a MAC reset 166 **/ 167 s32 ixgbe_reset_hw(struct ixgbe_hw *hw) 168 { 169 return ixgbe_call_func(hw, hw->mac.ops.reset_hw, (hw), 170 IXGBE_NOT_IMPLEMENTED); 171 } 172 173 /** 174 * ixgbe_start_hw - Prepares hardware for Rx/Tx 175 * @hw: pointer to hardware structure 176 * 177 * Starts the hardware by filling the bus info structure and media type, 178 * clears all on chip counters, initializes receive address registers, 179 * multicast table, VLAN filter table, calls routine to setup link and 180 * flow control settings, and leaves transmit and receive units disabled 181 * and uninitialized. 182 **/ 183 s32 ixgbe_start_hw(struct ixgbe_hw *hw) 184 { 185 return ixgbe_call_func(hw, hw->mac.ops.start_hw, (hw), 186 IXGBE_NOT_IMPLEMENTED); 187 } 188 189 /** 190 * ixgbe_enable_relaxed_ordering - Enables tx relaxed ordering, 191 * which is disabled by default in ixgbe_start_hw(); 192 * 193 * @hw: pointer to hardware structure 194 * 195 * Enable relaxed ordering; 196 **/ 197 void ixgbe_enable_relaxed_ordering(struct ixgbe_hw *hw) 198 { 199 if (hw->mac.ops.enable_relaxed_ordering) 200 hw->mac.ops.enable_relaxed_ordering(hw); 201 } 202 203 /** 204 * ixgbe_clear_hw_cntrs - Clear hardware counters 205 * @hw: pointer to hardware structure 206 * 207 * Clears all hardware statistics counters by reading them from the hardware 208 * Statistics counters are clear on read. 209 **/ 210 s32 ixgbe_clear_hw_cntrs(struct ixgbe_hw *hw) 211 { 212 return ixgbe_call_func(hw, hw->mac.ops.clear_hw_cntrs, (hw), 213 IXGBE_NOT_IMPLEMENTED); 214 } 215 216 /** 217 * ixgbe_get_media_type - Get media type 218 * @hw: pointer to hardware structure 219 * 220 * Returns the media type (fiber, copper, backplane) 221 **/ 222 enum ixgbe_media_type ixgbe_get_media_type(struct ixgbe_hw *hw) 223 { 224 return ixgbe_call_func(hw, hw->mac.ops.get_media_type, (hw), 225 ixgbe_media_type_unknown); 226 } 227 228 /** 229 * ixgbe_get_mac_addr - Get MAC address 230 * @hw: pointer to hardware structure 231 * @mac_addr: Adapter MAC address 232 * 233 * Reads the adapter's MAC address from the first Receive Address Register 234 * (RAR0) A reset of the adapter must have been performed prior to calling 235 * this function in order for the MAC address to have been loaded from the 236 * EEPROM into RAR0 237 **/ 238 s32 ixgbe_get_mac_addr(struct ixgbe_hw *hw, u8 *mac_addr) 239 { 240 return ixgbe_call_func(hw, hw->mac.ops.get_mac_addr, 241 (hw, mac_addr), IXGBE_NOT_IMPLEMENTED); 242 } 243 244 /** 245 * ixgbe_get_san_mac_addr - Get SAN MAC address 246 * @hw: pointer to hardware structure 247 * @san_mac_addr: SAN MAC address 248 * 249 * Reads the SAN MAC address from the EEPROM, if it's available. This is 250 * per-port, so set_lan_id() must be called before reading the addresses. 251 **/ 252 s32 ixgbe_get_san_mac_addr(struct ixgbe_hw *hw, u8 *san_mac_addr) 253 { 254 return ixgbe_call_func(hw, hw->mac.ops.get_san_mac_addr, 255 (hw, san_mac_addr), IXGBE_NOT_IMPLEMENTED); 256 } 257 258 /** 259 * ixgbe_set_san_mac_addr - Write a SAN MAC address 260 * @hw: pointer to hardware structure 261 * @san_mac_addr: SAN MAC address 262 * 263 * Writes A SAN MAC address to the EEPROM. 264 **/ 265 s32 ixgbe_set_san_mac_addr(struct ixgbe_hw *hw, u8 *san_mac_addr) 266 { 267 return ixgbe_call_func(hw, hw->mac.ops.set_san_mac_addr, 268 (hw, san_mac_addr), IXGBE_NOT_IMPLEMENTED); 269 } 270 271 /** 272 * ixgbe_get_device_caps - Get additional device capabilities 273 * @hw: pointer to hardware structure 274 * @device_caps: the EEPROM word for device capabilities 275 * 276 * Reads the extra device capabilities from the EEPROM 277 **/ 278 s32 ixgbe_get_device_caps(struct ixgbe_hw *hw, u16 *device_caps) 279 { 280 return ixgbe_call_func(hw, hw->mac.ops.get_device_caps, 281 (hw, device_caps), IXGBE_NOT_IMPLEMENTED); 282 } 283 284 /** 285 * ixgbe_get_wwn_prefix - Get alternative WWNN/WWPN prefix from the EEPROM 286 * @hw: pointer to hardware structure 287 * @wwnn_prefix: the alternative WWNN prefix 288 * @wwpn_prefix: the alternative WWPN prefix 289 * 290 * This function will read the EEPROM from the alternative SAN MAC address 291 * block to check the support for the alternative WWNN/WWPN prefix support. 292 **/ 293 s32 ixgbe_get_wwn_prefix(struct ixgbe_hw *hw, u16 *wwnn_prefix, 294 u16 *wwpn_prefix) 295 { 296 return ixgbe_call_func(hw, hw->mac.ops.get_wwn_prefix, 297 (hw, wwnn_prefix, wwpn_prefix), 298 IXGBE_NOT_IMPLEMENTED); 299 } 300 301 /** 302 * ixgbe_get_fcoe_boot_status - Get FCOE boot status from EEPROM 303 * @hw: pointer to hardware structure 304 * @bs: the fcoe boot status 305 * 306 * This function will read the FCOE boot status from the iSCSI FCOE block 307 **/ 308 s32 ixgbe_get_fcoe_boot_status(struct ixgbe_hw *hw, u16 *bs) 309 { 310 return ixgbe_call_func(hw, hw->mac.ops.get_fcoe_boot_status, 311 (hw, bs), 312 IXGBE_NOT_IMPLEMENTED); 313 } 314 315 /** 316 * ixgbe_get_bus_info - Set PCI bus info 317 * @hw: pointer to hardware structure 318 * 319 * Sets the PCI bus info (speed, width, type) within the ixgbe_hw structure 320 **/ 321 s32 ixgbe_get_bus_info(struct ixgbe_hw *hw) 322 { 323 return ixgbe_call_func(hw, hw->mac.ops.get_bus_info, (hw), 324 IXGBE_NOT_IMPLEMENTED); 325 } 326 327 /** 328 * ixgbe_get_num_of_tx_queues - Get Tx queues 329 * @hw: pointer to hardware structure 330 * 331 * Returns the number of transmit queues for the given adapter. 332 **/ 333 u32 ixgbe_get_num_of_tx_queues(struct ixgbe_hw *hw) 334 { 335 return hw->mac.max_tx_queues; 336 } 337 338 /** 339 * ixgbe_get_num_of_rx_queues - Get Rx queues 340 * @hw: pointer to hardware structure 341 * 342 * Returns the number of receive queues for the given adapter. 343 **/ 344 u32 ixgbe_get_num_of_rx_queues(struct ixgbe_hw *hw) 345 { 346 return hw->mac.max_rx_queues; 347 } 348 349 /** 350 * ixgbe_stop_adapter - Disable Rx/Tx units 351 * @hw: pointer to hardware structure 352 * 353 * Sets the adapter_stopped flag within ixgbe_hw struct. Clears interrupts, 354 * disables transmit and receive units. The adapter_stopped flag is used by 355 * the shared code and drivers to determine if the adapter is in a stopped 356 * state and should not touch the hardware. 357 **/ 358 s32 ixgbe_stop_adapter(struct ixgbe_hw *hw) 359 { 360 return ixgbe_call_func(hw, hw->mac.ops.stop_adapter, (hw), 361 IXGBE_NOT_IMPLEMENTED); 362 } 363 364 /** 365 * ixgbe_read_pba_string - Reads part number string from EEPROM 366 * @hw: pointer to hardware structure 367 * @pba_num: stores the part number string from the EEPROM 368 * @pba_num_size: part number string buffer length 369 * 370 * Reads the part number string from the EEPROM. 371 **/ 372 s32 ixgbe_read_pba_string(struct ixgbe_hw *hw, u8 *pba_num, u32 pba_num_size) 373 { 374 return ixgbe_read_pba_string_generic(hw, pba_num, pba_num_size); 375 } 376 377 /** 378 * ixgbe_read_pba_num - Reads part number from EEPROM 379 * @hw: pointer to hardware structure 380 * @pba_num: stores the part number from the EEPROM 381 * 382 * Reads the part number from the EEPROM. 383 **/ 384 s32 ixgbe_read_pba_num(struct ixgbe_hw *hw, u32 *pba_num) 385 { 386 return ixgbe_read_pba_num_generic(hw, pba_num); 387 } 388 389 /** 390 * ixgbe_identify_phy - Get PHY type 391 * @hw: pointer to hardware structure 392 * 393 * Determines the physical layer module found on the current adapter. 394 **/ 395 s32 ixgbe_identify_phy(struct ixgbe_hw *hw) 396 { 397 s32 status = IXGBE_SUCCESS; 398 399 if (hw->phy.type == ixgbe_phy_unknown) { 400 status = ixgbe_call_func(hw, hw->phy.ops.identify, (hw), 401 IXGBE_NOT_IMPLEMENTED); 402 } 403 404 return status; 405 } 406 407 /** 408 * ixgbe_reset_phy - Perform a PHY reset 409 * @hw: pointer to hardware structure 410 **/ 411 s32 ixgbe_reset_phy(struct ixgbe_hw *hw) 412 { 413 s32 status = IXGBE_SUCCESS; 414 415 if (hw->phy.type == ixgbe_phy_unknown) { 416 if (ixgbe_identify_phy(hw) != IXGBE_SUCCESS) 417 status = IXGBE_ERR_PHY; 418 } 419 420 if (status == IXGBE_SUCCESS) { 421 status = ixgbe_call_func(hw, hw->phy.ops.reset, (hw), 422 IXGBE_NOT_IMPLEMENTED); 423 } 424 return status; 425 } 426 427 /** 428 * ixgbe_get_phy_firmware_version - 429 * @hw: pointer to hardware structure 430 * @firmware_version: pointer to firmware version 431 **/ 432 s32 ixgbe_get_phy_firmware_version(struct ixgbe_hw *hw, u16 *firmware_version) 433 { 434 s32 status = IXGBE_SUCCESS; 435 436 status = ixgbe_call_func(hw, hw->phy.ops.get_firmware_version, 437 (hw, firmware_version), 438 IXGBE_NOT_IMPLEMENTED); 439 return status; 440 } 441 442 /** 443 * ixgbe_read_phy_reg - Read PHY register 444 * @hw: pointer to hardware structure 445 * @reg_addr: 32 bit address of PHY register to read 446 * @phy_data: Pointer to read data from PHY register 447 * 448 * Reads a value from a specified PHY register 449 **/ 450 s32 ixgbe_read_phy_reg(struct ixgbe_hw *hw, u32 reg_addr, u32 device_type, 451 u16 *phy_data) 452 { 453 if (hw->phy.id == 0) 454 ixgbe_identify_phy(hw); 455 456 return ixgbe_call_func(hw, hw->phy.ops.read_reg, (hw, reg_addr, 457 device_type, phy_data), IXGBE_NOT_IMPLEMENTED); 458 } 459 460 /** 461 * ixgbe_write_phy_reg - Write PHY register 462 * @hw: pointer to hardware structure 463 * @reg_addr: 32 bit PHY register to write 464 * @phy_data: Data to write to the PHY register 465 * 466 * Writes a value to specified PHY register 467 **/ 468 s32 ixgbe_write_phy_reg(struct ixgbe_hw *hw, u32 reg_addr, u32 device_type, 469 u16 phy_data) 470 { 471 if (hw->phy.id == 0) 472 ixgbe_identify_phy(hw); 473 474 return ixgbe_call_func(hw, hw->phy.ops.write_reg, (hw, reg_addr, 475 device_type, phy_data), IXGBE_NOT_IMPLEMENTED); 476 } 477 478 /** 479 * ixgbe_setup_phy_link - Restart PHY autoneg 480 * @hw: pointer to hardware structure 481 * 482 * Restart autonegotiation and PHY and waits for completion. 483 **/ 484 s32 ixgbe_setup_phy_link(struct ixgbe_hw *hw) 485 { 486 return ixgbe_call_func(hw, hw->phy.ops.setup_link, (hw), 487 IXGBE_NOT_IMPLEMENTED); 488 } 489 490 /** 491 * ixgbe_check_phy_link - Determine link and speed status 492 * @hw: pointer to hardware structure 493 * 494 * Reads a PHY register to determine if link is up and the current speed for 495 * the PHY. 496 **/ 497 s32 ixgbe_check_phy_link(struct ixgbe_hw *hw, ixgbe_link_speed *speed, 498 bool *link_up) 499 { 500 return ixgbe_call_func(hw, hw->phy.ops.check_link, (hw, speed, 501 link_up), IXGBE_NOT_IMPLEMENTED); 502 } 503 504 /** 505 * ixgbe_setup_phy_link_speed - Set auto advertise 506 * @hw: pointer to hardware structure 507 * @speed: new link speed 508 * @autoneg: TRUE if autonegotiation enabled 509 * 510 * Sets the auto advertised capabilities 511 **/ 512 s32 ixgbe_setup_phy_link_speed(struct ixgbe_hw *hw, ixgbe_link_speed speed, 513 bool autoneg, 514 bool autoneg_wait_to_complete) 515 { 516 return ixgbe_call_func(hw, hw->phy.ops.setup_link_speed, (hw, speed, 517 autoneg, autoneg_wait_to_complete), 518 IXGBE_NOT_IMPLEMENTED); 519 } 520 521 /** 522 * ixgbe_check_link - Get link and speed status 523 * @hw: pointer to hardware structure 524 * 525 * Reads the links register to determine if link is up and the current speed 526 **/ 527 s32 ixgbe_check_link(struct ixgbe_hw *hw, ixgbe_link_speed *speed, 528 bool *link_up, bool link_up_wait_to_complete) 529 { 530 return ixgbe_call_func(hw, hw->mac.ops.check_link, (hw, speed, 531 link_up, link_up_wait_to_complete), 532 IXGBE_NOT_IMPLEMENTED); 533 } 534 535 /** 536 * ixgbe_disable_tx_laser - Disable Tx laser 537 * @hw: pointer to hardware structure 538 * 539 * If the driver needs to disable the laser on SFI optics. 540 **/ 541 void ixgbe_disable_tx_laser(struct ixgbe_hw *hw) 542 { 543 if (hw->mac.ops.disable_tx_laser) 544 hw->mac.ops.disable_tx_laser(hw); 545 } 546 547 /** 548 * ixgbe_enable_tx_laser - Enable Tx laser 549 * @hw: pointer to hardware structure 550 * 551 * If the driver needs to enable the laser on SFI optics. 552 **/ 553 void ixgbe_enable_tx_laser(struct ixgbe_hw *hw) 554 { 555 if (hw->mac.ops.enable_tx_laser) 556 hw->mac.ops.enable_tx_laser(hw); 557 } 558 559 /** 560 * ixgbe_flap_tx_laser - flap Tx laser to start autotry process 561 * @hw: pointer to hardware structure 562 * 563 * When the driver changes the link speeds that it can support then 564 * flap the tx laser to alert the link partner to start autotry 565 * process on its end. 566 **/ 567 void ixgbe_flap_tx_laser(struct ixgbe_hw *hw) 568 { 569 if (hw->mac.ops.flap_tx_laser) 570 hw->mac.ops.flap_tx_laser(hw); 571 } 572 573 /** 574 * ixgbe_setup_link - Set link speed 575 * @hw: pointer to hardware structure 576 * @speed: new link speed 577 * @autoneg: TRUE if autonegotiation enabled 578 * 579 * Configures link settings. Restarts the link. 580 * Performs autonegotiation if needed. 581 **/ 582 s32 ixgbe_setup_link(struct ixgbe_hw *hw, ixgbe_link_speed speed, 583 bool autoneg, 584 bool autoneg_wait_to_complete) 585 { 586 return ixgbe_call_func(hw, hw->mac.ops.setup_link, (hw, speed, 587 autoneg, autoneg_wait_to_complete), 588 IXGBE_NOT_IMPLEMENTED); 589 } 590 591 /** 592 * ixgbe_get_link_capabilities - Returns link capabilities 593 * @hw: pointer to hardware structure 594 * 595 * Determines the link capabilities of the current configuration. 596 **/ 597 s32 ixgbe_get_link_capabilities(struct ixgbe_hw *hw, ixgbe_link_speed *speed, 598 bool *autoneg) 599 { 600 return ixgbe_call_func(hw, hw->mac.ops.get_link_capabilities, (hw, 601 speed, autoneg), IXGBE_NOT_IMPLEMENTED); 602 } 603 604 /** 605 * ixgbe_led_on - Turn on LEDs 606 * @hw: pointer to hardware structure 607 * @index: led number to turn on 608 * 609 * Turns on the software controllable LEDs. 610 **/ 611 s32 ixgbe_led_on(struct ixgbe_hw *hw, u32 index) 612 { 613 return ixgbe_call_func(hw, hw->mac.ops.led_on, (hw, index), 614 IXGBE_NOT_IMPLEMENTED); 615 } 616 617 /** 618 * ixgbe_led_off - Turn off LEDs 619 * @hw: pointer to hardware structure 620 * @index: led number to turn off 621 * 622 * Turns off the software controllable LEDs. 623 **/ 624 s32 ixgbe_led_off(struct ixgbe_hw *hw, u32 index) 625 { 626 return ixgbe_call_func(hw, hw->mac.ops.led_off, (hw, index), 627 IXGBE_NOT_IMPLEMENTED); 628 } 629 630 /** 631 * ixgbe_blink_led_start - Blink LEDs 632 * @hw: pointer to hardware structure 633 * @index: led number to blink 634 * 635 * Blink LED based on index. 636 **/ 637 s32 ixgbe_blink_led_start(struct ixgbe_hw *hw, u32 index) 638 { 639 return ixgbe_call_func(hw, hw->mac.ops.blink_led_start, (hw, index), 640 IXGBE_NOT_IMPLEMENTED); 641 } 642 643 /** 644 * ixgbe_blink_led_stop - Stop blinking LEDs 645 * @hw: pointer to hardware structure 646 * 647 * Stop blinking LED based on index. 648 **/ 649 s32 ixgbe_blink_led_stop(struct ixgbe_hw *hw, u32 index) 650 { 651 return ixgbe_call_func(hw, hw->mac.ops.blink_led_stop, (hw, index), 652 IXGBE_NOT_IMPLEMENTED); 653 } 654 655 /** 656 * ixgbe_init_eeprom_params - Initialize EEPROM parameters 657 * @hw: pointer to hardware structure 658 * 659 * Initializes the EEPROM parameters ixgbe_eeprom_info within the 660 * ixgbe_hw struct in order to set up EEPROM access. 661 **/ 662 s32 ixgbe_init_eeprom_params(struct ixgbe_hw *hw) 663 { 664 return ixgbe_call_func(hw, hw->eeprom.ops.init_params, (hw), 665 IXGBE_NOT_IMPLEMENTED); 666 } 667 668 669 /** 670 * ixgbe_write_eeprom - Write word to EEPROM 671 * @hw: pointer to hardware structure 672 * @offset: offset within the EEPROM to be written to 673 * @data: 16 bit word to be written to the EEPROM 674 * 675 * Writes 16 bit value to EEPROM. If ixgbe_eeprom_update_checksum is not 676 * called after this function, the EEPROM will most likely contain an 677 * invalid checksum. 678 **/ 679 s32 ixgbe_write_eeprom(struct ixgbe_hw *hw, u16 offset, u16 data) 680 { 681 return ixgbe_call_func(hw, hw->eeprom.ops.write, (hw, offset, data), 682 IXGBE_NOT_IMPLEMENTED); 683 } 684 685 /** 686 * ixgbe_write_eeprom_buffer - Write word(s) to EEPROM 687 * @hw: pointer to hardware structure 688 * @offset: offset within the EEPROM to be written to 689 * @data: 16 bit word(s) to be written to the EEPROM 690 * @words: number of words 691 * 692 * Writes 16 bit word(s) to EEPROM. If ixgbe_eeprom_update_checksum is not 693 * called after this function, the EEPROM will most likely contain an 694 * invalid checksum. 695 **/ 696 s32 ixgbe_write_eeprom_buffer(struct ixgbe_hw *hw, u16 offset, u16 words, 697 u16 *data) 698 { 699 return ixgbe_call_func(hw, hw->eeprom.ops.write_buffer, 700 (hw, offset, words, data), 701 IXGBE_NOT_IMPLEMENTED); 702 } 703 704 /** 705 * ixgbe_read_eeprom - Read word from EEPROM 706 * @hw: pointer to hardware structure 707 * @offset: offset within the EEPROM to be read 708 * @data: read 16 bit value from EEPROM 709 * 710 * Reads 16 bit value from EEPROM 711 **/ 712 s32 ixgbe_read_eeprom(struct ixgbe_hw *hw, u16 offset, u16 *data) 713 { 714 return ixgbe_call_func(hw, hw->eeprom.ops.read, (hw, offset, data), 715 IXGBE_NOT_IMPLEMENTED); 716 } 717 718 /** 719 * ixgbe_read_eeprom_buffer - Read word(s) from EEPROM 720 * @hw: pointer to hardware structure 721 * @offset: offset within the EEPROM to be read 722 * @data: read 16 bit word(s) from EEPROM 723 * @words: number of words 724 * 725 * Reads 16 bit word(s) from EEPROM 726 **/ 727 s32 ixgbe_read_eeprom_buffer(struct ixgbe_hw *hw, u16 offset, 728 u16 words, u16 *data) 729 { 730 return ixgbe_call_func(hw, hw->eeprom.ops.read_buffer, 731 (hw, offset, words, data), 732 IXGBE_NOT_IMPLEMENTED); 733 } 734 735 /** 736 * ixgbe_validate_eeprom_checksum - Validate EEPROM checksum 737 * @hw: pointer to hardware structure 738 * @checksum_val: calculated checksum 739 * 740 * Performs checksum calculation and validates the EEPROM checksum 741 **/ 742 s32 ixgbe_validate_eeprom_checksum(struct ixgbe_hw *hw, u16 *checksum_val) 743 { 744 return ixgbe_call_func(hw, hw->eeprom.ops.validate_checksum, 745 (hw, checksum_val), IXGBE_NOT_IMPLEMENTED); 746 } 747 748 /** 749 * ixgbe_eeprom_update_checksum - Updates the EEPROM checksum 750 * @hw: pointer to hardware structure 751 **/ 752 s32 ixgbe_update_eeprom_checksum(struct ixgbe_hw *hw) 753 { 754 return ixgbe_call_func(hw, hw->eeprom.ops.update_checksum, (hw), 755 IXGBE_NOT_IMPLEMENTED); 756 } 757 758 /** 759 * ixgbe_insert_mac_addr - Find a RAR for this mac address 760 * @hw: pointer to hardware structure 761 * @addr: Address to put into receive address register 762 * @vmdq: VMDq pool to assign 763 * 764 * Puts an ethernet address into a receive address register, or 765 * finds the rar that it is aleady in; adds to the pool list 766 **/ 767 s32 ixgbe_insert_mac_addr(struct ixgbe_hw *hw, u8 *addr, u32 vmdq) 768 { 769 return ixgbe_call_func(hw, hw->mac.ops.insert_mac_addr, 770 (hw, addr, vmdq), 771 IXGBE_NOT_IMPLEMENTED); 772 } 773 774 /** 775 * ixgbe_set_rar - Set Rx address register 776 * @hw: pointer to hardware structure 777 * @index: Receive address register to write 778 * @addr: Address to put into receive address register 779 * @vmdq: VMDq "set" 780 * @enable_addr: set flag that address is active 781 * 782 * Puts an ethernet address into a receive address register. 783 **/ 784 s32 ixgbe_set_rar(struct ixgbe_hw *hw, u32 index, u8 *addr, u32 vmdq, 785 u32 enable_addr) 786 { 787 return ixgbe_call_func(hw, hw->mac.ops.set_rar, (hw, index, addr, vmdq, 788 enable_addr), IXGBE_NOT_IMPLEMENTED); 789 } 790 791 /** 792 * ixgbe_clear_rar - Clear Rx address register 793 * @hw: pointer to hardware structure 794 * @index: Receive address register to write 795 * 796 * Puts an ethernet address into a receive address register. 797 **/ 798 s32 ixgbe_clear_rar(struct ixgbe_hw *hw, u32 index) 799 { 800 return ixgbe_call_func(hw, hw->mac.ops.clear_rar, (hw, index), 801 IXGBE_NOT_IMPLEMENTED); 802 } 803 804 /** 805 * ixgbe_set_vmdq - Associate a VMDq index with a receive address 806 * @hw: pointer to hardware structure 807 * @rar: receive address register index to associate with VMDq index 808 * @vmdq: VMDq set or pool index 809 **/ 810 s32 ixgbe_set_vmdq(struct ixgbe_hw *hw, u32 rar, u32 vmdq) 811 { 812 return ixgbe_call_func(hw, hw->mac.ops.set_vmdq, (hw, rar, vmdq), 813 IXGBE_NOT_IMPLEMENTED); 814 } 815 816 /** 817 * ixgbe_clear_vmdq - Disassociate a VMDq index from a receive address 818 * @hw: pointer to hardware structure 819 * @rar: receive address register index to disassociate with VMDq index 820 * @vmdq: VMDq set or pool index 821 **/ 822 s32 ixgbe_clear_vmdq(struct ixgbe_hw *hw, u32 rar, u32 vmdq) 823 { 824 return ixgbe_call_func(hw, hw->mac.ops.clear_vmdq, (hw, rar, vmdq), 825 IXGBE_NOT_IMPLEMENTED); 826 } 827 828 /** 829 * ixgbe_init_rx_addrs - Initializes receive address filters. 830 * @hw: pointer to hardware structure 831 * 832 * Places the MAC address in receive address register 0 and clears the rest 833 * of the receive address registers. Clears the multicast table. Assumes 834 * the receiver is in reset when the routine is called. 835 **/ 836 s32 ixgbe_init_rx_addrs(struct ixgbe_hw *hw) 837 { 838 return ixgbe_call_func(hw, hw->mac.ops.init_rx_addrs, (hw), 839 IXGBE_NOT_IMPLEMENTED); 840 } 841 842 /** 843 * ixgbe_get_num_rx_addrs - Returns the number of RAR entries. 844 * @hw: pointer to hardware structure 845 **/ 846 u32 ixgbe_get_num_rx_addrs(struct ixgbe_hw *hw) 847 { 848 return hw->mac.num_rar_entries; 849 } 850 851 /** 852 * ixgbe_update_uc_addr_list - Updates the MAC's list of secondary addresses 853 * @hw: pointer to hardware structure 854 * @addr_list: the list of new multicast addresses 855 * @addr_count: number of addresses 856 * @func: iterator function to walk the multicast address list 857 * 858 * The given list replaces any existing list. Clears the secondary addrs from 859 * receive address registers. Uses unused receive address registers for the 860 * first secondary addresses, and falls back to promiscuous mode as needed. 861 **/ 862 s32 ixgbe_update_uc_addr_list(struct ixgbe_hw *hw, u8 *addr_list, 863 u32 addr_count, ixgbe_mc_addr_itr func) 864 { 865 return ixgbe_call_func(hw, hw->mac.ops.update_uc_addr_list, (hw, 866 addr_list, addr_count, func), 867 IXGBE_NOT_IMPLEMENTED); 868 } 869 870 /** 871 * ixgbe_update_mc_addr_list - Updates the MAC's list of multicast addresses 872 * @hw: pointer to hardware structure 873 * @mc_addr_list: the list of new multicast addresses 874 * @mc_addr_count: number of addresses 875 * @func: iterator function to walk the multicast address list 876 * 877 * The given list replaces any existing list. Clears the MC addrs from receive 878 * address registers and the multicast table. Uses unused receive address 879 * registers for the first multicast addresses, and hashes the rest into the 880 * multicast table. 881 **/ 882 s32 ixgbe_update_mc_addr_list(struct ixgbe_hw *hw, u8 *mc_addr_list, 883 u32 mc_addr_count, ixgbe_mc_addr_itr func, 884 bool clear) 885 { 886 return ixgbe_call_func(hw, hw->mac.ops.update_mc_addr_list, (hw, 887 mc_addr_list, mc_addr_count, func, clear), 888 IXGBE_NOT_IMPLEMENTED); 889 } 890 891 /** 892 * ixgbe_enable_mc - Enable multicast address in RAR 893 * @hw: pointer to hardware structure 894 * 895 * Enables multicast address in RAR and the use of the multicast hash table. 896 **/ 897 s32 ixgbe_enable_mc(struct ixgbe_hw *hw) 898 { 899 return ixgbe_call_func(hw, hw->mac.ops.enable_mc, (hw), 900 IXGBE_NOT_IMPLEMENTED); 901 } 902 903 /** 904 * ixgbe_disable_mc - Disable multicast address in RAR 905 * @hw: pointer to hardware structure 906 * 907 * Disables multicast address in RAR and the use of the multicast hash table. 908 **/ 909 s32 ixgbe_disable_mc(struct ixgbe_hw *hw) 910 { 911 return ixgbe_call_func(hw, hw->mac.ops.disable_mc, (hw), 912 IXGBE_NOT_IMPLEMENTED); 913 } 914 915 /** 916 * ixgbe_clear_vfta - Clear VLAN filter table 917 * @hw: pointer to hardware structure 918 * 919 * Clears the VLAN filer table, and the VMDq index associated with the filter 920 **/ 921 s32 ixgbe_clear_vfta(struct ixgbe_hw *hw) 922 { 923 return ixgbe_call_func(hw, hw->mac.ops.clear_vfta, (hw), 924 IXGBE_NOT_IMPLEMENTED); 925 } 926 927 /** 928 * ixgbe_set_vfta - Set VLAN filter table 929 * @hw: pointer to hardware structure 930 * @vlan: VLAN id to write to VLAN filter 931 * @vind: VMDq output index that maps queue to VLAN id in VFTA 932 * @vlan_on: boolean flag to turn on/off VLAN in VFTA 933 * 934 * Turn on/off specified VLAN in the VLAN filter table. 935 **/ 936 s32 ixgbe_set_vfta(struct ixgbe_hw *hw, u32 vlan, u32 vind, bool vlan_on) 937 { 938 return ixgbe_call_func(hw, hw->mac.ops.set_vfta, (hw, vlan, vind, 939 vlan_on), IXGBE_NOT_IMPLEMENTED); 940 } 941 942 /** 943 * ixgbe_set_vlvf - Set VLAN Pool Filter 944 * @hw: pointer to hardware structure 945 * @vlan: VLAN id to write to VLAN filter 946 * @vind: VMDq output index that maps queue to VLAN id in VFVFB 947 * @vlan_on: boolean flag to turn on/off VLAN in VFVF 948 * @vfta_changed: pointer to boolean flag which indicates whether VFTA 949 * should be changed 950 * 951 * Turn on/off specified bit in VLVF table. 952 **/ 953 s32 ixgbe_set_vlvf(struct ixgbe_hw *hw, u32 vlan, u32 vind, bool vlan_on, 954 bool *vfta_changed) 955 { 956 return ixgbe_call_func(hw, hw->mac.ops.set_vlvf, (hw, vlan, vind, 957 vlan_on, vfta_changed), IXGBE_NOT_IMPLEMENTED); 958 } 959 960 /** 961 * ixgbe_fc_enable - Enable flow control 962 * @hw: pointer to hardware structure 963 * @packetbuf_num: packet buffer number (0-7) 964 * 965 * Configures the flow control settings based on SW configuration. 966 **/ 967 s32 ixgbe_fc_enable(struct ixgbe_hw *hw, s32 packetbuf_num) 968 { 969 return ixgbe_call_func(hw, hw->mac.ops.fc_enable, (hw, packetbuf_num), 970 IXGBE_NOT_IMPLEMENTED); 971 } 972 973 /** 974 * ixgbe_set_fw_drv_ver - Try to send the driver version number FW 975 * @hw: pointer to hardware structure 976 * @maj: driver major number to be sent to firmware 977 * @min: driver minor number to be sent to firmware 978 * @build: driver build number to be sent to firmware 979 * @ver: driver version number to be sent to firmware 980 **/ 981 s32 ixgbe_set_fw_drv_ver(struct ixgbe_hw *hw, u8 maj, u8 min, u8 build, 982 u8 ver) 983 { 984 return ixgbe_call_func(hw, hw->mac.ops.set_fw_drv_ver, (hw, maj, min, 985 build, ver), IXGBE_NOT_IMPLEMENTED); 986 } 987 988 989 /** 990 * ixgbe_read_analog_reg8 - Reads 8 bit analog register 991 * @hw: pointer to hardware structure 992 * @reg: analog register to read 993 * @val: read value 994 * 995 * Performs write operation to analog register specified. 996 **/ 997 s32 ixgbe_read_analog_reg8(struct ixgbe_hw *hw, u32 reg, u8 *val) 998 { 999 return ixgbe_call_func(hw, hw->mac.ops.read_analog_reg8, (hw, reg, 1000 val), IXGBE_NOT_IMPLEMENTED); 1001 } 1002 1003 /** 1004 * ixgbe_write_analog_reg8 - Writes 8 bit analog register 1005 * @hw: pointer to hardware structure 1006 * @reg: analog register to write 1007 * @val: value to write 1008 * 1009 * Performs write operation to Atlas analog register specified. 1010 **/ 1011 s32 ixgbe_write_analog_reg8(struct ixgbe_hw *hw, u32 reg, u8 val) 1012 { 1013 return ixgbe_call_func(hw, hw->mac.ops.write_analog_reg8, (hw, reg, 1014 val), IXGBE_NOT_IMPLEMENTED); 1015 } 1016 1017 /** 1018 * ixgbe_init_uta_tables - Initializes Unicast Table Arrays. 1019 * @hw: pointer to hardware structure 1020 * 1021 * Initializes the Unicast Table Arrays to zero on device load. This 1022 * is part of the Rx init addr execution path. 1023 **/ 1024 s32 ixgbe_init_uta_tables(struct ixgbe_hw *hw) 1025 { 1026 return ixgbe_call_func(hw, hw->mac.ops.init_uta_tables, (hw), 1027 IXGBE_NOT_IMPLEMENTED); 1028 } 1029 1030 /** 1031 * ixgbe_read_i2c_byte - Reads 8 bit word over I2C at specified device address 1032 * @hw: pointer to hardware structure 1033 * @byte_offset: byte offset to read 1034 * @data: value read 1035 * 1036 * Performs byte read operation to SFP module's EEPROM over I2C interface. 1037 **/ 1038 s32 ixgbe_read_i2c_byte(struct ixgbe_hw *hw, u8 byte_offset, u8 dev_addr, 1039 u8 *data) 1040 { 1041 return ixgbe_call_func(hw, hw->phy.ops.read_i2c_byte, (hw, byte_offset, 1042 dev_addr, data), IXGBE_NOT_IMPLEMENTED); 1043 } 1044 1045 /** 1046 * ixgbe_write_i2c_byte - Writes 8 bit word over I2C 1047 * @hw: pointer to hardware structure 1048 * @byte_offset: byte offset to write 1049 * @data: value to write 1050 * 1051 * Performs byte write operation to SFP module's EEPROM over I2C interface 1052 * at a specified device address. 1053 **/ 1054 s32 ixgbe_write_i2c_byte(struct ixgbe_hw *hw, u8 byte_offset, u8 dev_addr, 1055 u8 data) 1056 { 1057 return ixgbe_call_func(hw, hw->phy.ops.write_i2c_byte, (hw, byte_offset, 1058 dev_addr, data), IXGBE_NOT_IMPLEMENTED); 1059 } 1060 1061 /** 1062 * ixgbe_write_i2c_eeprom - Writes 8 bit EEPROM word over I2C interface 1063 * @hw: pointer to hardware structure 1064 * @byte_offset: EEPROM byte offset to write 1065 * @eeprom_data: value to write 1066 * 1067 * Performs byte write operation to SFP module's EEPROM over I2C interface. 1068 **/ 1069 s32 ixgbe_write_i2c_eeprom(struct ixgbe_hw *hw, 1070 u8 byte_offset, u8 eeprom_data) 1071 { 1072 return ixgbe_call_func(hw, hw->phy.ops.write_i2c_eeprom, 1073 (hw, byte_offset, eeprom_data), 1074 IXGBE_NOT_IMPLEMENTED); 1075 } 1076 1077 /** 1078 * ixgbe_read_i2c_eeprom - Reads 8 bit EEPROM word over I2C interface 1079 * @hw: pointer to hardware structure 1080 * @byte_offset: EEPROM byte offset to read 1081 * @eeprom_data: value read 1082 * 1083 * Performs byte read operation to SFP module's EEPROM over I2C interface. 1084 **/ 1085 s32 ixgbe_read_i2c_eeprom(struct ixgbe_hw *hw, u8 byte_offset, u8 *eeprom_data) 1086 { 1087 return ixgbe_call_func(hw, hw->phy.ops.read_i2c_eeprom, 1088 (hw, byte_offset, eeprom_data), 1089 IXGBE_NOT_IMPLEMENTED); 1090 } 1091 1092 /** 1093 * ixgbe_get_supported_physical_layer - Returns physical layer type 1094 * @hw: pointer to hardware structure 1095 * 1096 * Determines physical layer capabilities of the current configuration. 1097 **/ 1098 u32 ixgbe_get_supported_physical_layer(struct ixgbe_hw *hw) 1099 { 1100 return ixgbe_call_func(hw, hw->mac.ops.get_supported_physical_layer, 1101 (hw), IXGBE_PHYSICAL_LAYER_UNKNOWN); 1102 } 1103 1104 /** 1105 * ixgbe_enable_rx_dma - Enables Rx DMA unit, dependant on device specifics 1106 * @hw: pointer to hardware structure 1107 * @regval: bitfield to write to the Rx DMA register 1108 * 1109 * Enables the Rx DMA unit of the device. 1110 **/ 1111 s32 ixgbe_enable_rx_dma(struct ixgbe_hw *hw, u32 regval) 1112 { 1113 return ixgbe_call_func(hw, hw->mac.ops.enable_rx_dma, 1114 (hw, regval), IXGBE_NOT_IMPLEMENTED); 1115 } 1116 1117 /** 1118 * ixgbe_disable_sec_rx_path - Stops the receive data path 1119 * @hw: pointer to hardware structure 1120 * 1121 * Stops the receive data path. 1122 **/ 1123 s32 ixgbe_disable_sec_rx_path(struct ixgbe_hw *hw) 1124 { 1125 return ixgbe_call_func(hw, hw->mac.ops.disable_sec_rx_path, 1126 (hw), IXGBE_NOT_IMPLEMENTED); 1127 } 1128 1129 /** 1130 * ixgbe_enable_sec_rx_path - Enables the receive data path 1131 * @hw: pointer to hardware structure 1132 * 1133 * Enables the receive data path. 1134 **/ 1135 s32 ixgbe_enable_sec_rx_path(struct ixgbe_hw *hw) 1136 { 1137 return ixgbe_call_func(hw, hw->mac.ops.enable_sec_rx_path, 1138 (hw), IXGBE_NOT_IMPLEMENTED); 1139 } 1140 1141 /** 1142 * ixgbe_acquire_swfw_semaphore - Acquire SWFW semaphore 1143 * @hw: pointer to hardware structure 1144 * @mask: Mask to specify which semaphore to acquire 1145 * 1146 * Acquires the SWFW semaphore through SW_FW_SYNC register for the specified 1147 * function (CSR, PHY0, PHY1, EEPROM, Flash) 1148 **/ 1149 s32 ixgbe_acquire_swfw_semaphore(struct ixgbe_hw *hw, u16 mask) 1150 { 1151 return ixgbe_call_func(hw, hw->mac.ops.acquire_swfw_sync, 1152 (hw, mask), IXGBE_NOT_IMPLEMENTED); 1153 } 1154 1155 /** 1156 * ixgbe_release_swfw_semaphore - Release SWFW semaphore 1157 * @hw: pointer to hardware structure 1158 * @mask: Mask to specify which semaphore to release 1159 * 1160 * Releases the SWFW semaphore through SW_FW_SYNC register for the specified 1161 * function (CSR, PHY0, PHY1, EEPROM, Flash) 1162 **/ 1163 void ixgbe_release_swfw_semaphore(struct ixgbe_hw *hw, u16 mask) 1164 { 1165 if (hw->mac.ops.release_swfw_sync) 1166 hw->mac.ops.release_swfw_sync(hw, mask); 1167 } 1168 1169