1 /****************************************************************************** 2 SPDX-License-Identifier: BSD-3-Clause 3 4 Copyright (c) 2001-2020, Intel Corporation 5 All rights reserved. 6 7 Redistribution and use in source and binary forms, with or without 8 modification, are permitted provided that the following conditions are met: 9 10 1. Redistributions of source code must retain the above copyright notice, 11 this list of conditions and the following disclaimer. 12 13 2. Redistributions in binary form must reproduce the above copyright 14 notice, this list of conditions and the following disclaimer in the 15 documentation and/or other materials provided with the distribution. 16 17 3. Neither the name of the Intel Corporation nor the names of its 18 contributors may be used to endorse or promote products derived from 19 this software without specific prior written permission. 20 21 THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 22 AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 23 IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 24 ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE 25 LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 26 CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 27 SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 28 INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 29 CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 30 ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 31 POSSIBILITY OF SUCH DAMAGE. 32 33 ******************************************************************************/ 34 /*$FreeBSD$*/ 35 36 #include "ixgbe_api.h" 37 #include "ixgbe_common.h" 38 39 #define IXGBE_EMPTY_PARAM 40 41 static const u32 ixgbe_mvals_base[IXGBE_MVALS_IDX_LIMIT] = { 42 IXGBE_MVALS_INIT(IXGBE_EMPTY_PARAM) 43 }; 44 45 static const u32 ixgbe_mvals_X540[IXGBE_MVALS_IDX_LIMIT] = { 46 IXGBE_MVALS_INIT(_X540) 47 }; 48 49 static const u32 ixgbe_mvals_X550[IXGBE_MVALS_IDX_LIMIT] = { 50 IXGBE_MVALS_INIT(_X550) 51 }; 52 53 static const u32 ixgbe_mvals_X550EM_x[IXGBE_MVALS_IDX_LIMIT] = { 54 IXGBE_MVALS_INIT(_X550EM_x) 55 }; 56 57 static const u32 ixgbe_mvals_X550EM_a[IXGBE_MVALS_IDX_LIMIT] = { 58 IXGBE_MVALS_INIT(_X550EM_a) 59 }; 60 61 /** 62 * ixgbe_dcb_get_rtrup2tc - read rtrup2tc reg 63 * @hw: pointer to hardware structure 64 * @map: pointer to u8 arr for returning map 65 * 66 * Read the rtrup2tc HW register and resolve its content into map 67 **/ 68 void ixgbe_dcb_get_rtrup2tc(struct ixgbe_hw *hw, u8 *map) 69 { 70 if (hw->mac.ops.get_rtrup2tc) 71 hw->mac.ops.get_rtrup2tc(hw, map); 72 } 73 74 /** 75 * ixgbe_init_shared_code - Initialize the shared code 76 * @hw: pointer to hardware structure 77 * 78 * This will assign function pointers and assign the MAC type and PHY code. 79 * Does not touch the hardware. This function must be called prior to any 80 * other function in the shared code. The ixgbe_hw structure should be 81 * memset to 0 prior to calling this function. The following fields in 82 * hw structure should be filled in prior to calling this function: 83 * hw_addr, back, device_id, vendor_id, subsystem_device_id, 84 * subsystem_vendor_id, and revision_id 85 **/ 86 s32 ixgbe_init_shared_code(struct ixgbe_hw *hw) 87 { 88 s32 status; 89 90 DEBUGFUNC("ixgbe_init_shared_code"); 91 92 /* 93 * Set the mac type 94 */ 95 ixgbe_set_mac_type(hw); 96 97 switch (hw->mac.type) { 98 case ixgbe_mac_82598EB: 99 status = ixgbe_init_ops_82598(hw); 100 break; 101 case ixgbe_mac_82599EB: 102 status = ixgbe_init_ops_82599(hw); 103 break; 104 case ixgbe_mac_X540: 105 status = ixgbe_init_ops_X540(hw); 106 break; 107 case ixgbe_mac_X550: 108 status = ixgbe_init_ops_X550(hw); 109 break; 110 case ixgbe_mac_X550EM_x: 111 status = ixgbe_init_ops_X550EM_x(hw); 112 break; 113 case ixgbe_mac_X550EM_a: 114 status = ixgbe_init_ops_X550EM_a(hw); 115 break; 116 case ixgbe_mac_82599_vf: 117 case ixgbe_mac_X540_vf: 118 case ixgbe_mac_X550_vf: 119 case ixgbe_mac_X550EM_x_vf: 120 case ixgbe_mac_X550EM_a_vf: 121 status = ixgbe_init_ops_vf(hw); 122 break; 123 default: 124 status = IXGBE_ERR_DEVICE_NOT_SUPPORTED; 125 break; 126 } 127 hw->mac.max_link_up_time = IXGBE_LINK_UP_TIME; 128 129 return status; 130 } 131 132 /** 133 * ixgbe_set_mac_type - Sets MAC type 134 * @hw: pointer to the HW structure 135 * 136 * This function sets the mac type of the adapter based on the 137 * vendor ID and device ID stored in the hw structure. 138 **/ 139 s32 ixgbe_set_mac_type(struct ixgbe_hw *hw) 140 { 141 s32 ret_val = IXGBE_SUCCESS; 142 143 DEBUGFUNC("ixgbe_set_mac_type\n"); 144 145 if (hw->vendor_id != IXGBE_INTEL_VENDOR_ID) { 146 ERROR_REPORT2(IXGBE_ERROR_UNSUPPORTED, 147 "Unsupported vendor id: %x", hw->vendor_id); 148 return IXGBE_ERR_DEVICE_NOT_SUPPORTED; 149 } 150 151 hw->mvals = ixgbe_mvals_base; 152 153 switch (hw->device_id) { 154 case IXGBE_DEV_ID_82598: 155 case IXGBE_DEV_ID_82598_BX: 156 case IXGBE_DEV_ID_82598AF_SINGLE_PORT: 157 case IXGBE_DEV_ID_82598AF_DUAL_PORT: 158 case IXGBE_DEV_ID_82598AT: 159 case IXGBE_DEV_ID_82598AT2: 160 case IXGBE_DEV_ID_82598EB_CX4: 161 case IXGBE_DEV_ID_82598_CX4_DUAL_PORT: 162 case IXGBE_DEV_ID_82598_DA_DUAL_PORT: 163 case IXGBE_DEV_ID_82598_SR_DUAL_PORT_EM: 164 case IXGBE_DEV_ID_82598EB_XF_LR: 165 case IXGBE_DEV_ID_82598EB_SFP_LOM: 166 hw->mac.type = ixgbe_mac_82598EB; 167 break; 168 case IXGBE_DEV_ID_82599_KX4: 169 case IXGBE_DEV_ID_82599_KX4_MEZZ: 170 case IXGBE_DEV_ID_82599_XAUI_LOM: 171 case IXGBE_DEV_ID_82599_COMBO_BACKPLANE: 172 case IXGBE_DEV_ID_82599_KR: 173 case IXGBE_DEV_ID_82599_SFP: 174 case IXGBE_DEV_ID_82599_BACKPLANE_FCOE: 175 case IXGBE_DEV_ID_82599_SFP_FCOE: 176 case IXGBE_DEV_ID_82599_SFP_EM: 177 case IXGBE_DEV_ID_82599_SFP_SF2: 178 case IXGBE_DEV_ID_82599_SFP_SF_QP: 179 case IXGBE_DEV_ID_82599_QSFP_SF_QP: 180 case IXGBE_DEV_ID_82599EN_SFP: 181 case IXGBE_DEV_ID_82599_CX4: 182 case IXGBE_DEV_ID_82599_BYPASS: 183 case IXGBE_DEV_ID_82599_T3_LOM: 184 hw->mac.type = ixgbe_mac_82599EB; 185 break; 186 case IXGBE_DEV_ID_82599_VF: 187 case IXGBE_DEV_ID_82599_VF_HV: 188 hw->mac.type = ixgbe_mac_82599_vf; 189 break; 190 case IXGBE_DEV_ID_X540_VF: 191 case IXGBE_DEV_ID_X540_VF_HV: 192 hw->mac.type = ixgbe_mac_X540_vf; 193 hw->mvals = ixgbe_mvals_X540; 194 break; 195 case IXGBE_DEV_ID_X540T: 196 case IXGBE_DEV_ID_X540T1: 197 case IXGBE_DEV_ID_X540_BYPASS: 198 hw->mac.type = ixgbe_mac_X540; 199 hw->mvals = ixgbe_mvals_X540; 200 break; 201 case IXGBE_DEV_ID_X550T: 202 case IXGBE_DEV_ID_X550T1: 203 hw->mac.type = ixgbe_mac_X550; 204 hw->mvals = ixgbe_mvals_X550; 205 break; 206 case IXGBE_DEV_ID_X550EM_X_KX4: 207 case IXGBE_DEV_ID_X550EM_X_KR: 208 case IXGBE_DEV_ID_X550EM_X_10G_T: 209 case IXGBE_DEV_ID_X550EM_X_1G_T: 210 case IXGBE_DEV_ID_X550EM_X_SFP: 211 case IXGBE_DEV_ID_X550EM_X_XFI: 212 hw->mac.type = ixgbe_mac_X550EM_x; 213 hw->mvals = ixgbe_mvals_X550EM_x; 214 break; 215 case IXGBE_DEV_ID_X550EM_A_KR: 216 case IXGBE_DEV_ID_X550EM_A_KR_L: 217 case IXGBE_DEV_ID_X550EM_A_SFP_N: 218 case IXGBE_DEV_ID_X550EM_A_SGMII: 219 case IXGBE_DEV_ID_X550EM_A_SGMII_L: 220 case IXGBE_DEV_ID_X550EM_A_1G_T: 221 case IXGBE_DEV_ID_X550EM_A_1G_T_L: 222 case IXGBE_DEV_ID_X550EM_A_10G_T: 223 case IXGBE_DEV_ID_X550EM_A_QSFP: 224 case IXGBE_DEV_ID_X550EM_A_QSFP_N: 225 case IXGBE_DEV_ID_X550EM_A_SFP: 226 hw->mac.type = ixgbe_mac_X550EM_a; 227 hw->mvals = ixgbe_mvals_X550EM_a; 228 break; 229 case IXGBE_DEV_ID_X550_VF: 230 case IXGBE_DEV_ID_X550_VF_HV: 231 hw->mac.type = ixgbe_mac_X550_vf; 232 hw->mvals = ixgbe_mvals_X550; 233 break; 234 case IXGBE_DEV_ID_X550EM_X_VF: 235 case IXGBE_DEV_ID_X550EM_X_VF_HV: 236 hw->mac.type = ixgbe_mac_X550EM_x_vf; 237 hw->mvals = ixgbe_mvals_X550EM_x; 238 break; 239 case IXGBE_DEV_ID_X550EM_A_VF: 240 case IXGBE_DEV_ID_X550EM_A_VF_HV: 241 hw->mac.type = ixgbe_mac_X550EM_a_vf; 242 hw->mvals = ixgbe_mvals_X550EM_a; 243 break; 244 default: 245 ret_val = IXGBE_ERR_DEVICE_NOT_SUPPORTED; 246 ERROR_REPORT2(IXGBE_ERROR_UNSUPPORTED, 247 "Unsupported device id: %x", 248 hw->device_id); 249 break; 250 } 251 252 DEBUGOUT2("ixgbe_set_mac_type found mac: %d, returns: %d\n", 253 hw->mac.type, ret_val); 254 return ret_val; 255 } 256 257 /** 258 * ixgbe_init_hw - Initialize the hardware 259 * @hw: pointer to hardware structure 260 * 261 * Initialize the hardware by resetting and then starting the hardware 262 **/ 263 s32 ixgbe_init_hw(struct ixgbe_hw *hw) 264 { 265 return ixgbe_call_func(hw, hw->mac.ops.init_hw, (hw), 266 IXGBE_NOT_IMPLEMENTED); 267 } 268 269 /** 270 * ixgbe_reset_hw - Performs a hardware reset 271 * @hw: pointer to hardware structure 272 * 273 * Resets the hardware by resetting the transmit and receive units, masks and 274 * clears all interrupts, performs a PHY reset, and performs a MAC reset 275 **/ 276 s32 ixgbe_reset_hw(struct ixgbe_hw *hw) 277 { 278 return ixgbe_call_func(hw, hw->mac.ops.reset_hw, (hw), 279 IXGBE_NOT_IMPLEMENTED); 280 } 281 282 /** 283 * ixgbe_start_hw - Prepares hardware for Rx/Tx 284 * @hw: pointer to hardware structure 285 * 286 * Starts the hardware by filling the bus info structure and media type, 287 * clears all on chip counters, initializes receive address registers, 288 * multicast table, VLAN filter table, calls routine to setup link and 289 * flow control settings, and leaves transmit and receive units disabled 290 * and uninitialized. 291 **/ 292 s32 ixgbe_start_hw(struct ixgbe_hw *hw) 293 { 294 return ixgbe_call_func(hw, hw->mac.ops.start_hw, (hw), 295 IXGBE_NOT_IMPLEMENTED); 296 } 297 298 /** 299 * ixgbe_enable_relaxed_ordering - Enables tx relaxed ordering, 300 * which is disabled by default in ixgbe_start_hw(); 301 * 302 * @hw: pointer to hardware structure 303 * 304 * Enable relaxed ordering; 305 **/ 306 void ixgbe_enable_relaxed_ordering(struct ixgbe_hw *hw) 307 { 308 if (hw->mac.ops.enable_relaxed_ordering) 309 hw->mac.ops.enable_relaxed_ordering(hw); 310 } 311 312 /** 313 * ixgbe_clear_hw_cntrs - Clear hardware counters 314 * @hw: pointer to hardware structure 315 * 316 * Clears all hardware statistics counters by reading them from the hardware 317 * Statistics counters are clear on read. 318 **/ 319 s32 ixgbe_clear_hw_cntrs(struct ixgbe_hw *hw) 320 { 321 return ixgbe_call_func(hw, hw->mac.ops.clear_hw_cntrs, (hw), 322 IXGBE_NOT_IMPLEMENTED); 323 } 324 325 /** 326 * ixgbe_get_media_type - Get media type 327 * @hw: pointer to hardware structure 328 * 329 * Returns the media type (fiber, copper, backplane) 330 **/ 331 enum ixgbe_media_type ixgbe_get_media_type(struct ixgbe_hw *hw) 332 { 333 return ixgbe_call_func(hw, hw->mac.ops.get_media_type, (hw), 334 ixgbe_media_type_unknown); 335 } 336 337 /** 338 * ixgbe_get_mac_addr - Get MAC address 339 * @hw: pointer to hardware structure 340 * @mac_addr: Adapter MAC address 341 * 342 * Reads the adapter's MAC address from the first Receive Address Register 343 * (RAR0) A reset of the adapter must have been performed prior to calling 344 * this function in order for the MAC address to have been loaded from the 345 * EEPROM into RAR0 346 **/ 347 s32 ixgbe_get_mac_addr(struct ixgbe_hw *hw, u8 *mac_addr) 348 { 349 return ixgbe_call_func(hw, hw->mac.ops.get_mac_addr, 350 (hw, mac_addr), IXGBE_NOT_IMPLEMENTED); 351 } 352 353 /** 354 * ixgbe_get_san_mac_addr - Get SAN MAC address 355 * @hw: pointer to hardware structure 356 * @san_mac_addr: SAN MAC address 357 * 358 * Reads the SAN MAC address from the EEPROM, if it's available. This is 359 * per-port, so set_lan_id() must be called before reading the addresses. 360 **/ 361 s32 ixgbe_get_san_mac_addr(struct ixgbe_hw *hw, u8 *san_mac_addr) 362 { 363 return ixgbe_call_func(hw, hw->mac.ops.get_san_mac_addr, 364 (hw, san_mac_addr), IXGBE_NOT_IMPLEMENTED); 365 } 366 367 /** 368 * ixgbe_set_san_mac_addr - Write a SAN MAC address 369 * @hw: pointer to hardware structure 370 * @san_mac_addr: SAN MAC address 371 * 372 * Writes A SAN MAC address to the EEPROM. 373 **/ 374 s32 ixgbe_set_san_mac_addr(struct ixgbe_hw *hw, u8 *san_mac_addr) 375 { 376 return ixgbe_call_func(hw, hw->mac.ops.set_san_mac_addr, 377 (hw, san_mac_addr), IXGBE_NOT_IMPLEMENTED); 378 } 379 380 /** 381 * ixgbe_get_device_caps - Get additional device capabilities 382 * @hw: pointer to hardware structure 383 * @device_caps: the EEPROM word for device capabilities 384 * 385 * Reads the extra device capabilities from the EEPROM 386 **/ 387 s32 ixgbe_get_device_caps(struct ixgbe_hw *hw, u16 *device_caps) 388 { 389 return ixgbe_call_func(hw, hw->mac.ops.get_device_caps, 390 (hw, device_caps), IXGBE_NOT_IMPLEMENTED); 391 } 392 393 /** 394 * ixgbe_get_wwn_prefix - Get alternative WWNN/WWPN prefix from the EEPROM 395 * @hw: pointer to hardware structure 396 * @wwnn_prefix: the alternative WWNN prefix 397 * @wwpn_prefix: the alternative WWPN prefix 398 * 399 * This function will read the EEPROM from the alternative SAN MAC address 400 * block to check the support for the alternative WWNN/WWPN prefix support. 401 **/ 402 s32 ixgbe_get_wwn_prefix(struct ixgbe_hw *hw, u16 *wwnn_prefix, 403 u16 *wwpn_prefix) 404 { 405 return ixgbe_call_func(hw, hw->mac.ops.get_wwn_prefix, 406 (hw, wwnn_prefix, wwpn_prefix), 407 IXGBE_NOT_IMPLEMENTED); 408 } 409 410 /** 411 * ixgbe_get_fcoe_boot_status - Get FCOE boot status from EEPROM 412 * @hw: pointer to hardware structure 413 * @bs: the fcoe boot status 414 * 415 * This function will read the FCOE boot status from the iSCSI FCOE block 416 **/ 417 s32 ixgbe_get_fcoe_boot_status(struct ixgbe_hw *hw, u16 *bs) 418 { 419 return ixgbe_call_func(hw, hw->mac.ops.get_fcoe_boot_status, 420 (hw, bs), 421 IXGBE_NOT_IMPLEMENTED); 422 } 423 424 /** 425 * ixgbe_get_bus_info - Set PCI bus info 426 * @hw: pointer to hardware structure 427 * 428 * Sets the PCI bus info (speed, width, type) within the ixgbe_hw structure 429 **/ 430 s32 ixgbe_get_bus_info(struct ixgbe_hw *hw) 431 { 432 return ixgbe_call_func(hw, hw->mac.ops.get_bus_info, (hw), 433 IXGBE_NOT_IMPLEMENTED); 434 } 435 436 /** 437 * ixgbe_get_num_of_tx_queues - Get Tx queues 438 * @hw: pointer to hardware structure 439 * 440 * Returns the number of transmit queues for the given adapter. 441 **/ 442 u32 ixgbe_get_num_of_tx_queues(struct ixgbe_hw *hw) 443 { 444 return hw->mac.max_tx_queues; 445 } 446 447 /** 448 * ixgbe_get_num_of_rx_queues - Get Rx queues 449 * @hw: pointer to hardware structure 450 * 451 * Returns the number of receive queues for the given adapter. 452 **/ 453 u32 ixgbe_get_num_of_rx_queues(struct ixgbe_hw *hw) 454 { 455 return hw->mac.max_rx_queues; 456 } 457 458 /** 459 * ixgbe_stop_adapter - Disable Rx/Tx units 460 * @hw: pointer to hardware structure 461 * 462 * Sets the adapter_stopped flag within ixgbe_hw struct. Clears interrupts, 463 * disables transmit and receive units. The adapter_stopped flag is used by 464 * the shared code and drivers to determine if the adapter is in a stopped 465 * state and should not touch the hardware. 466 **/ 467 s32 ixgbe_stop_adapter(struct ixgbe_hw *hw) 468 { 469 return ixgbe_call_func(hw, hw->mac.ops.stop_adapter, (hw), 470 IXGBE_NOT_IMPLEMENTED); 471 } 472 473 /** 474 * ixgbe_read_pba_string - Reads part number string from EEPROM 475 * @hw: pointer to hardware structure 476 * @pba_num: stores the part number string from the EEPROM 477 * @pba_num_size: part number string buffer length 478 * 479 * Reads the part number string from the EEPROM. 480 **/ 481 s32 ixgbe_read_pba_string(struct ixgbe_hw *hw, u8 *pba_num, u32 pba_num_size) 482 { 483 return ixgbe_read_pba_string_generic(hw, pba_num, pba_num_size); 484 } 485 486 /** 487 * ixgbe_read_pba_num - Reads part number from EEPROM 488 * @hw: pointer to hardware structure 489 * @pba_num: stores the part number from the EEPROM 490 * 491 * Reads the part number from the EEPROM. 492 **/ 493 s32 ixgbe_read_pba_num(struct ixgbe_hw *hw, u32 *pba_num) 494 { 495 return ixgbe_read_pba_num_generic(hw, pba_num); 496 } 497 498 /** 499 * ixgbe_identify_phy - Get PHY type 500 * @hw: pointer to hardware structure 501 * 502 * Determines the physical layer module found on the current adapter. 503 **/ 504 s32 ixgbe_identify_phy(struct ixgbe_hw *hw) 505 { 506 s32 status = IXGBE_SUCCESS; 507 508 if (hw->phy.type == ixgbe_phy_unknown) { 509 status = ixgbe_call_func(hw, hw->phy.ops.identify, (hw), 510 IXGBE_NOT_IMPLEMENTED); 511 } 512 513 return status; 514 } 515 516 /** 517 * ixgbe_reset_phy - Perform a PHY reset 518 * @hw: pointer to hardware structure 519 **/ 520 s32 ixgbe_reset_phy(struct ixgbe_hw *hw) 521 { 522 s32 status = IXGBE_SUCCESS; 523 524 if (hw->phy.type == ixgbe_phy_unknown) { 525 if (ixgbe_identify_phy(hw) != IXGBE_SUCCESS) 526 status = IXGBE_ERR_PHY; 527 } 528 529 if (status == IXGBE_SUCCESS) { 530 status = ixgbe_call_func(hw, hw->phy.ops.reset, (hw), 531 IXGBE_NOT_IMPLEMENTED); 532 } 533 return status; 534 } 535 536 /** 537 * ixgbe_get_phy_firmware_version - 538 * @hw: pointer to hardware structure 539 * @firmware_version: pointer to firmware version 540 **/ 541 s32 ixgbe_get_phy_firmware_version(struct ixgbe_hw *hw, u16 *firmware_version) 542 { 543 s32 status = IXGBE_SUCCESS; 544 545 status = ixgbe_call_func(hw, hw->phy.ops.get_firmware_version, 546 (hw, firmware_version), 547 IXGBE_NOT_IMPLEMENTED); 548 return status; 549 } 550 551 /** 552 * ixgbe_read_phy_reg - Read PHY register 553 * @hw: pointer to hardware structure 554 * @reg_addr: 32 bit address of PHY register to read 555 * @device_type: type of device you want to communicate with 556 * @phy_data: Pointer to read data from PHY register 557 * 558 * Reads a value from a specified PHY register 559 **/ 560 s32 ixgbe_read_phy_reg(struct ixgbe_hw *hw, u32 reg_addr, u32 device_type, 561 u16 *phy_data) 562 { 563 if (hw->phy.id == 0) 564 ixgbe_identify_phy(hw); 565 566 return ixgbe_call_func(hw, hw->phy.ops.read_reg, (hw, reg_addr, 567 device_type, phy_data), IXGBE_NOT_IMPLEMENTED); 568 } 569 570 /** 571 * ixgbe_write_phy_reg - Write PHY register 572 * @hw: pointer to hardware structure 573 * @reg_addr: 32 bit PHY register to write 574 * @device_type: type of device you want to communicate with 575 * @phy_data: Data to write to the PHY register 576 * 577 * Writes a value to specified PHY register 578 **/ 579 s32 ixgbe_write_phy_reg(struct ixgbe_hw *hw, u32 reg_addr, u32 device_type, 580 u16 phy_data) 581 { 582 if (hw->phy.id == 0) 583 ixgbe_identify_phy(hw); 584 585 return ixgbe_call_func(hw, hw->phy.ops.write_reg, (hw, reg_addr, 586 device_type, phy_data), IXGBE_NOT_IMPLEMENTED); 587 } 588 589 /** 590 * ixgbe_setup_phy_link - Restart PHY autoneg 591 * @hw: pointer to hardware structure 592 * 593 * Restart autonegotiation and PHY and waits for completion. 594 **/ 595 s32 ixgbe_setup_phy_link(struct ixgbe_hw *hw) 596 { 597 return ixgbe_call_func(hw, hw->phy.ops.setup_link, (hw), 598 IXGBE_NOT_IMPLEMENTED); 599 } 600 601 /** 602 * ixgbe_setup_internal_phy - Configure integrated PHY 603 * @hw: pointer to hardware structure 604 * 605 * Reconfigure the integrated PHY in order to enable talk to the external PHY. 606 * Returns success if not implemented, since nothing needs to be done in this 607 * case. 608 */ 609 s32 ixgbe_setup_internal_phy(struct ixgbe_hw *hw) 610 { 611 return ixgbe_call_func(hw, hw->phy.ops.setup_internal_link, (hw), 612 IXGBE_SUCCESS); 613 } 614 615 /** 616 * ixgbe_check_phy_link - Determine link and speed status 617 * @hw: pointer to hardware structure 618 * @speed: link speed 619 * @link_up: true when link is up 620 * 621 * Reads a PHY register to determine if link is up and the current speed for 622 * the PHY. 623 **/ 624 s32 ixgbe_check_phy_link(struct ixgbe_hw *hw, ixgbe_link_speed *speed, 625 bool *link_up) 626 { 627 return ixgbe_call_func(hw, hw->phy.ops.check_link, (hw, speed, 628 link_up), IXGBE_NOT_IMPLEMENTED); 629 } 630 631 /** 632 * ixgbe_setup_phy_link_speed - Set auto advertise 633 * @hw: pointer to hardware structure 634 * @speed: new link speed 635 * @autoneg_wait_to_complete: true when waiting for completion is needed 636 * 637 * Sets the auto advertised capabilities 638 **/ 639 s32 ixgbe_setup_phy_link_speed(struct ixgbe_hw *hw, ixgbe_link_speed speed, 640 bool autoneg_wait_to_complete) 641 { 642 return ixgbe_call_func(hw, hw->phy.ops.setup_link_speed, (hw, speed, 643 autoneg_wait_to_complete), 644 IXGBE_NOT_IMPLEMENTED); 645 } 646 647 /** 648 * ixgbe_set_phy_power - Control the phy power state 649 * @hw: pointer to hardware structure 650 * @on: true for on, false for off 651 */ 652 s32 ixgbe_set_phy_power(struct ixgbe_hw *hw, bool on) 653 { 654 return ixgbe_call_func(hw, hw->phy.ops.set_phy_power, (hw, on), 655 IXGBE_NOT_IMPLEMENTED); 656 } 657 658 /** 659 * ixgbe_check_link - Get link and speed status 660 * @hw: pointer to hardware structure 661 * @speed: pointer to link speed 662 * @link_up: true when link is up 663 * @link_up_wait_to_complete: bool used to wait for link up or not 664 * 665 * Reads the links register to determine if link is up and the current speed 666 **/ 667 s32 ixgbe_check_link(struct ixgbe_hw *hw, ixgbe_link_speed *speed, 668 bool *link_up, bool link_up_wait_to_complete) 669 { 670 return ixgbe_call_func(hw, hw->mac.ops.check_link, (hw, speed, 671 link_up, link_up_wait_to_complete), 672 IXGBE_NOT_IMPLEMENTED); 673 } 674 675 /** 676 * ixgbe_disable_tx_laser - Disable Tx laser 677 * @hw: pointer to hardware structure 678 * 679 * If the driver needs to disable the laser on SFI optics. 680 **/ 681 void ixgbe_disable_tx_laser(struct ixgbe_hw *hw) 682 { 683 if (hw->mac.ops.disable_tx_laser) 684 hw->mac.ops.disable_tx_laser(hw); 685 } 686 687 /** 688 * ixgbe_enable_tx_laser - Enable Tx laser 689 * @hw: pointer to hardware structure 690 * 691 * If the driver needs to enable the laser on SFI optics. 692 **/ 693 void ixgbe_enable_tx_laser(struct ixgbe_hw *hw) 694 { 695 if (hw->mac.ops.enable_tx_laser) 696 hw->mac.ops.enable_tx_laser(hw); 697 } 698 699 /** 700 * ixgbe_flap_tx_laser - flap Tx laser to start autotry process 701 * @hw: pointer to hardware structure 702 * 703 * When the driver changes the link speeds that it can support then 704 * flap the tx laser to alert the link partner to start autotry 705 * process on its end. 706 **/ 707 void ixgbe_flap_tx_laser(struct ixgbe_hw *hw) 708 { 709 if (hw->mac.ops.flap_tx_laser) 710 hw->mac.ops.flap_tx_laser(hw); 711 } 712 713 /** 714 * ixgbe_setup_link - Set link speed 715 * @hw: pointer to hardware structure 716 * @speed: new link speed 717 * @autoneg_wait_to_complete: true when waiting for completion is needed 718 * 719 * Configures link settings. Restarts the link. 720 * Performs autonegotiation if needed. 721 **/ 722 s32 ixgbe_setup_link(struct ixgbe_hw *hw, ixgbe_link_speed speed, 723 bool autoneg_wait_to_complete) 724 { 725 return ixgbe_call_func(hw, hw->mac.ops.setup_link, (hw, speed, 726 autoneg_wait_to_complete), 727 IXGBE_NOT_IMPLEMENTED); 728 } 729 730 /** 731 * ixgbe_setup_mac_link - Set link speed 732 * @hw: pointer to hardware structure 733 * @speed: new link speed 734 * @autoneg_wait_to_complete: true when waiting for completion is needed 735 * 736 * Configures link settings. Restarts the link. 737 * Performs autonegotiation if needed. 738 **/ 739 s32 ixgbe_setup_mac_link(struct ixgbe_hw *hw, ixgbe_link_speed speed, 740 bool autoneg_wait_to_complete) 741 { 742 return ixgbe_call_func(hw, hw->mac.ops.setup_mac_link, (hw, speed, 743 autoneg_wait_to_complete), 744 IXGBE_NOT_IMPLEMENTED); 745 } 746 747 /** 748 * ixgbe_get_link_capabilities - Returns link capabilities 749 * @hw: pointer to hardware structure 750 * @speed: link speed capabilities 751 * @autoneg: true when autoneg or autotry is enabled 752 * 753 * Determines the link capabilities of the current configuration. 754 **/ 755 s32 ixgbe_get_link_capabilities(struct ixgbe_hw *hw, ixgbe_link_speed *speed, 756 bool *autoneg) 757 { 758 return ixgbe_call_func(hw, hw->mac.ops.get_link_capabilities, (hw, 759 speed, autoneg), IXGBE_NOT_IMPLEMENTED); 760 } 761 762 /** 763 * ixgbe_led_on - Turn on LEDs 764 * @hw: pointer to hardware structure 765 * @index: led number to turn on 766 * 767 * Turns on the software controllable LEDs. 768 **/ 769 s32 ixgbe_led_on(struct ixgbe_hw *hw, u32 index) 770 { 771 return ixgbe_call_func(hw, hw->mac.ops.led_on, (hw, index), 772 IXGBE_NOT_IMPLEMENTED); 773 } 774 775 /** 776 * ixgbe_led_off - Turn off LEDs 777 * @hw: pointer to hardware structure 778 * @index: led number to turn off 779 * 780 * Turns off the software controllable LEDs. 781 **/ 782 s32 ixgbe_led_off(struct ixgbe_hw *hw, u32 index) 783 { 784 return ixgbe_call_func(hw, hw->mac.ops.led_off, (hw, index), 785 IXGBE_NOT_IMPLEMENTED); 786 } 787 788 /** 789 * ixgbe_blink_led_start - Blink LEDs 790 * @hw: pointer to hardware structure 791 * @index: led number to blink 792 * 793 * Blink LED based on index. 794 **/ 795 s32 ixgbe_blink_led_start(struct ixgbe_hw *hw, u32 index) 796 { 797 return ixgbe_call_func(hw, hw->mac.ops.blink_led_start, (hw, index), 798 IXGBE_NOT_IMPLEMENTED); 799 } 800 801 /** 802 * ixgbe_blink_led_stop - Stop blinking LEDs 803 * @hw: pointer to hardware structure 804 * @index: led number to stop 805 * 806 * Stop blinking LED based on index. 807 **/ 808 s32 ixgbe_blink_led_stop(struct ixgbe_hw *hw, u32 index) 809 { 810 return ixgbe_call_func(hw, hw->mac.ops.blink_led_stop, (hw, index), 811 IXGBE_NOT_IMPLEMENTED); 812 } 813 814 /** 815 * ixgbe_init_eeprom_params - Initialize EEPROM parameters 816 * @hw: pointer to hardware structure 817 * 818 * Initializes the EEPROM parameters ixgbe_eeprom_info within the 819 * ixgbe_hw struct in order to set up EEPROM access. 820 **/ 821 s32 ixgbe_init_eeprom_params(struct ixgbe_hw *hw) 822 { 823 return ixgbe_call_func(hw, hw->eeprom.ops.init_params, (hw), 824 IXGBE_NOT_IMPLEMENTED); 825 } 826 827 828 /** 829 * ixgbe_write_eeprom - Write word to EEPROM 830 * @hw: pointer to hardware structure 831 * @offset: offset within the EEPROM to be written to 832 * @data: 16 bit word to be written to the EEPROM 833 * 834 * Writes 16 bit value to EEPROM. If ixgbe_eeprom_update_checksum is not 835 * called after this function, the EEPROM will most likely contain an 836 * invalid checksum. 837 **/ 838 s32 ixgbe_write_eeprom(struct ixgbe_hw *hw, u16 offset, u16 data) 839 { 840 return ixgbe_call_func(hw, hw->eeprom.ops.write, (hw, offset, data), 841 IXGBE_NOT_IMPLEMENTED); 842 } 843 844 /** 845 * ixgbe_write_eeprom_buffer - Write word(s) to EEPROM 846 * @hw: pointer to hardware structure 847 * @offset: offset within the EEPROM to be written to 848 * @data: 16 bit word(s) to be written to the EEPROM 849 * @words: number of words 850 * 851 * Writes 16 bit word(s) to EEPROM. If ixgbe_eeprom_update_checksum is not 852 * called after this function, the EEPROM will most likely contain an 853 * invalid checksum. 854 **/ 855 s32 ixgbe_write_eeprom_buffer(struct ixgbe_hw *hw, u16 offset, u16 words, 856 u16 *data) 857 { 858 return ixgbe_call_func(hw, hw->eeprom.ops.write_buffer, 859 (hw, offset, words, data), 860 IXGBE_NOT_IMPLEMENTED); 861 } 862 863 /** 864 * ixgbe_read_eeprom - Read word from EEPROM 865 * @hw: pointer to hardware structure 866 * @offset: offset within the EEPROM to be read 867 * @data: read 16 bit value from EEPROM 868 * 869 * Reads 16 bit value from EEPROM 870 **/ 871 s32 ixgbe_read_eeprom(struct ixgbe_hw *hw, u16 offset, u16 *data) 872 { 873 return ixgbe_call_func(hw, hw->eeprom.ops.read, (hw, offset, data), 874 IXGBE_NOT_IMPLEMENTED); 875 } 876 877 /** 878 * ixgbe_read_eeprom_buffer - Read word(s) from EEPROM 879 * @hw: pointer to hardware structure 880 * @offset: offset within the EEPROM to be read 881 * @data: read 16 bit word(s) from EEPROM 882 * @words: number of words 883 * 884 * Reads 16 bit word(s) from EEPROM 885 **/ 886 s32 ixgbe_read_eeprom_buffer(struct ixgbe_hw *hw, u16 offset, 887 u16 words, u16 *data) 888 { 889 return ixgbe_call_func(hw, hw->eeprom.ops.read_buffer, 890 (hw, offset, words, data), 891 IXGBE_NOT_IMPLEMENTED); 892 } 893 894 /** 895 * ixgbe_validate_eeprom_checksum - Validate EEPROM checksum 896 * @hw: pointer to hardware structure 897 * @checksum_val: calculated checksum 898 * 899 * Performs checksum calculation and validates the EEPROM checksum 900 **/ 901 s32 ixgbe_validate_eeprom_checksum(struct ixgbe_hw *hw, u16 *checksum_val) 902 { 903 return ixgbe_call_func(hw, hw->eeprom.ops.validate_checksum, 904 (hw, checksum_val), IXGBE_NOT_IMPLEMENTED); 905 } 906 907 /** 908 * ixgbe_eeprom_update_checksum - Updates the EEPROM checksum 909 * @hw: pointer to hardware structure 910 **/ 911 s32 ixgbe_update_eeprom_checksum(struct ixgbe_hw *hw) 912 { 913 return ixgbe_call_func(hw, hw->eeprom.ops.update_checksum, (hw), 914 IXGBE_NOT_IMPLEMENTED); 915 } 916 917 /** 918 * ixgbe_insert_mac_addr - Find a RAR for this mac address 919 * @hw: pointer to hardware structure 920 * @addr: Address to put into receive address register 921 * @vmdq: VMDq pool to assign 922 * 923 * Puts an ethernet address into a receive address register, or 924 * finds the rar that it is already in; adds to the pool list 925 **/ 926 s32 ixgbe_insert_mac_addr(struct ixgbe_hw *hw, u8 *addr, u32 vmdq) 927 { 928 return ixgbe_call_func(hw, hw->mac.ops.insert_mac_addr, 929 (hw, addr, vmdq), 930 IXGBE_NOT_IMPLEMENTED); 931 } 932 933 /** 934 * ixgbe_set_rar - Set Rx address register 935 * @hw: pointer to hardware structure 936 * @index: Receive address register to write 937 * @addr: Address to put into receive address register 938 * @vmdq: VMDq "set" 939 * @enable_addr: set flag that address is active 940 * 941 * Puts an ethernet address into a receive address register. 942 **/ 943 s32 ixgbe_set_rar(struct ixgbe_hw *hw, u32 index, u8 *addr, u32 vmdq, 944 u32 enable_addr) 945 { 946 return ixgbe_call_func(hw, hw->mac.ops.set_rar, (hw, index, addr, vmdq, 947 enable_addr), IXGBE_NOT_IMPLEMENTED); 948 } 949 950 /** 951 * ixgbe_clear_rar - Clear Rx address register 952 * @hw: pointer to hardware structure 953 * @index: Receive address register to write 954 * 955 * Puts an ethernet address into a receive address register. 956 **/ 957 s32 ixgbe_clear_rar(struct ixgbe_hw *hw, u32 index) 958 { 959 return ixgbe_call_func(hw, hw->mac.ops.clear_rar, (hw, index), 960 IXGBE_NOT_IMPLEMENTED); 961 } 962 963 /** 964 * ixgbe_set_vmdq - Associate a VMDq index with a receive address 965 * @hw: pointer to hardware structure 966 * @rar: receive address register index to associate with VMDq index 967 * @vmdq: VMDq set or pool index 968 **/ 969 s32 ixgbe_set_vmdq(struct ixgbe_hw *hw, u32 rar, u32 vmdq) 970 { 971 return ixgbe_call_func(hw, hw->mac.ops.set_vmdq, (hw, rar, vmdq), 972 IXGBE_NOT_IMPLEMENTED); 973 974 } 975 976 /** 977 * ixgbe_set_vmdq_san_mac - Associate VMDq index 127 with a receive address 978 * @hw: pointer to hardware structure 979 * @vmdq: VMDq default pool index 980 **/ 981 s32 ixgbe_set_vmdq_san_mac(struct ixgbe_hw *hw, u32 vmdq) 982 { 983 return ixgbe_call_func(hw, hw->mac.ops.set_vmdq_san_mac, 984 (hw, vmdq), IXGBE_NOT_IMPLEMENTED); 985 } 986 987 /** 988 * ixgbe_clear_vmdq - Disassociate a VMDq index from a receive address 989 * @hw: pointer to hardware structure 990 * @rar: receive address register index to disassociate with VMDq index 991 * @vmdq: VMDq set or pool index 992 **/ 993 s32 ixgbe_clear_vmdq(struct ixgbe_hw *hw, u32 rar, u32 vmdq) 994 { 995 return ixgbe_call_func(hw, hw->mac.ops.clear_vmdq, (hw, rar, vmdq), 996 IXGBE_NOT_IMPLEMENTED); 997 } 998 999 /** 1000 * ixgbe_init_rx_addrs - Initializes receive address filters. 1001 * @hw: pointer to hardware structure 1002 * 1003 * Places the MAC address in receive address register 0 and clears the rest 1004 * of the receive address registers. Clears the multicast table. Assumes 1005 * the receiver is in reset when the routine is called. 1006 **/ 1007 s32 ixgbe_init_rx_addrs(struct ixgbe_hw *hw) 1008 { 1009 return ixgbe_call_func(hw, hw->mac.ops.init_rx_addrs, (hw), 1010 IXGBE_NOT_IMPLEMENTED); 1011 } 1012 1013 /** 1014 * ixgbe_get_num_rx_addrs - Returns the number of RAR entries. 1015 * @hw: pointer to hardware structure 1016 **/ 1017 u32 ixgbe_get_num_rx_addrs(struct ixgbe_hw *hw) 1018 { 1019 return hw->mac.num_rar_entries; 1020 } 1021 1022 /** 1023 * ixgbe_update_uc_addr_list - Updates the MAC's list of secondary addresses 1024 * @hw: pointer to hardware structure 1025 * @addr_list: the list of new multicast addresses 1026 * @addr_count: number of addresses 1027 * @func: iterator function to walk the multicast address list 1028 * 1029 * The given list replaces any existing list. Clears the secondary addrs from 1030 * receive address registers. Uses unused receive address registers for the 1031 * first secondary addresses, and falls back to promiscuous mode as needed. 1032 **/ 1033 s32 ixgbe_update_uc_addr_list(struct ixgbe_hw *hw, u8 *addr_list, 1034 u32 addr_count, ixgbe_mc_addr_itr func) 1035 { 1036 return ixgbe_call_func(hw, hw->mac.ops.update_uc_addr_list, (hw, 1037 addr_list, addr_count, func), 1038 IXGBE_NOT_IMPLEMENTED); 1039 } 1040 1041 /** 1042 * ixgbe_update_mc_addr_list - Updates the MAC's list of multicast addresses 1043 * @hw: pointer to hardware structure 1044 * @mc_addr_list: the list of new multicast addresses 1045 * @mc_addr_count: number of addresses 1046 * @func: iterator function to walk the multicast address list 1047 * @clear: flag, when set clears the table beforehand 1048 * 1049 * The given list replaces any existing list. Clears the MC addrs from receive 1050 * address registers and the multicast table. Uses unused receive address 1051 * registers for the first multicast addresses, and hashes the rest into the 1052 * multicast table. 1053 **/ 1054 s32 ixgbe_update_mc_addr_list(struct ixgbe_hw *hw, u8 *mc_addr_list, 1055 u32 mc_addr_count, ixgbe_mc_addr_itr func, 1056 bool clear) 1057 { 1058 return ixgbe_call_func(hw, hw->mac.ops.update_mc_addr_list, (hw, 1059 mc_addr_list, mc_addr_count, func, clear), 1060 IXGBE_NOT_IMPLEMENTED); 1061 } 1062 1063 /** 1064 * ixgbe_enable_mc - Enable multicast address in RAR 1065 * @hw: pointer to hardware structure 1066 * 1067 * Enables multicast address in RAR and the use of the multicast hash table. 1068 **/ 1069 s32 ixgbe_enable_mc(struct ixgbe_hw *hw) 1070 { 1071 return ixgbe_call_func(hw, hw->mac.ops.enable_mc, (hw), 1072 IXGBE_NOT_IMPLEMENTED); 1073 } 1074 1075 /** 1076 * ixgbe_disable_mc - Disable multicast address in RAR 1077 * @hw: pointer to hardware structure 1078 * 1079 * Disables multicast address in RAR and the use of the multicast hash table. 1080 **/ 1081 s32 ixgbe_disable_mc(struct ixgbe_hw *hw) 1082 { 1083 return ixgbe_call_func(hw, hw->mac.ops.disable_mc, (hw), 1084 IXGBE_NOT_IMPLEMENTED); 1085 } 1086 1087 /** 1088 * ixgbe_clear_vfta - Clear VLAN filter table 1089 * @hw: pointer to hardware structure 1090 * 1091 * Clears the VLAN filer table, and the VMDq index associated with the filter 1092 **/ 1093 s32 ixgbe_clear_vfta(struct ixgbe_hw *hw) 1094 { 1095 return ixgbe_call_func(hw, hw->mac.ops.clear_vfta, (hw), 1096 IXGBE_NOT_IMPLEMENTED); 1097 } 1098 1099 /** 1100 * ixgbe_set_vfta - Set VLAN filter table 1101 * @hw: pointer to hardware structure 1102 * @vlan: VLAN id to write to VLAN filter 1103 * @vind: VMDq output index that maps queue to VLAN id in VLVFB 1104 * @vlan_on: boolean flag to turn on/off VLAN 1105 * @vlvf_bypass: boolean flag indicating updating the default pool is okay 1106 * 1107 * Turn on/off specified VLAN in the VLAN filter table. 1108 **/ 1109 s32 ixgbe_set_vfta(struct ixgbe_hw *hw, u32 vlan, u32 vind, bool vlan_on, 1110 bool vlvf_bypass) 1111 { 1112 return ixgbe_call_func(hw, hw->mac.ops.set_vfta, (hw, vlan, vind, 1113 vlan_on, vlvf_bypass), IXGBE_NOT_IMPLEMENTED); 1114 } 1115 1116 /** 1117 * ixgbe_set_vlvf - Set VLAN Pool Filter 1118 * @hw: pointer to hardware structure 1119 * @vlan: VLAN id to write to VLAN filter 1120 * @vind: VMDq output index that maps queue to VLAN id in VLVFB 1121 * @vlan_on: boolean flag to turn on/off VLAN in VLVF 1122 * @vfta_delta: pointer to the difference between the current value of VFTA 1123 * and the desired value 1124 * @vfta: the desired value of the VFTA 1125 * @vlvf_bypass: boolean flag indicating updating the default pool is okay 1126 * 1127 * Turn on/off specified bit in VLVF table. 1128 **/ 1129 s32 ixgbe_set_vlvf(struct ixgbe_hw *hw, u32 vlan, u32 vind, bool vlan_on, 1130 u32 *vfta_delta, u32 vfta, bool vlvf_bypass) 1131 { 1132 return ixgbe_call_func(hw, hw->mac.ops.set_vlvf, (hw, vlan, vind, 1133 vlan_on, vfta_delta, vfta, vlvf_bypass), 1134 IXGBE_NOT_IMPLEMENTED); 1135 } 1136 1137 /** 1138 * ixgbe_fc_enable - Enable flow control 1139 * @hw: pointer to hardware structure 1140 * 1141 * Configures the flow control settings based on SW configuration. 1142 **/ 1143 s32 ixgbe_fc_enable(struct ixgbe_hw *hw) 1144 { 1145 return ixgbe_call_func(hw, hw->mac.ops.fc_enable, (hw), 1146 IXGBE_NOT_IMPLEMENTED); 1147 } 1148 1149 /** 1150 * ixgbe_setup_fc - Set up flow control 1151 * @hw: pointer to hardware structure 1152 * 1153 * Called at init time to set up flow control. 1154 **/ 1155 s32 ixgbe_setup_fc(struct ixgbe_hw *hw) 1156 { 1157 return ixgbe_call_func(hw, hw->mac.ops.setup_fc, (hw), 1158 IXGBE_NOT_IMPLEMENTED); 1159 } 1160 1161 /** 1162 * ixgbe_set_fw_drv_ver - Try to send the driver version number FW 1163 * @hw: pointer to hardware structure 1164 * @maj: driver major number to be sent to firmware 1165 * @min: driver minor number to be sent to firmware 1166 * @build: driver build number to be sent to firmware 1167 * @ver: driver version number to be sent to firmware 1168 * @len: length of driver_ver string 1169 * @driver_ver: driver string 1170 **/ 1171 s32 ixgbe_set_fw_drv_ver(struct ixgbe_hw *hw, u8 maj, u8 min, u8 build, 1172 u8 ver, u16 len, char *driver_ver) 1173 { 1174 return ixgbe_call_func(hw, hw->mac.ops.set_fw_drv_ver, (hw, maj, min, 1175 build, ver, len, driver_ver), 1176 IXGBE_NOT_IMPLEMENTED); 1177 } 1178 1179 1180 /** 1181 * ixgbe_get_thermal_sensor_data - Gathers thermal sensor data 1182 * @hw: pointer to hardware structure 1183 * 1184 * Updates the temperatures in mac.thermal_sensor_data 1185 **/ 1186 s32 ixgbe_get_thermal_sensor_data(struct ixgbe_hw *hw) 1187 { 1188 return ixgbe_call_func(hw, hw->mac.ops.get_thermal_sensor_data, (hw), 1189 IXGBE_NOT_IMPLEMENTED); 1190 } 1191 1192 /** 1193 * ixgbe_init_thermal_sensor_thresh - Inits thermal sensor thresholds 1194 * @hw: pointer to hardware structure 1195 * 1196 * Inits the thermal sensor thresholds according to the NVM map 1197 **/ 1198 s32 ixgbe_init_thermal_sensor_thresh(struct ixgbe_hw *hw) 1199 { 1200 return ixgbe_call_func(hw, hw->mac.ops.init_thermal_sensor_thresh, (hw), 1201 IXGBE_NOT_IMPLEMENTED); 1202 } 1203 1204 /** 1205 * ixgbe_dmac_config - Configure DMA Coalescing registers. 1206 * @hw: pointer to hardware structure 1207 * 1208 * Configure DMA coalescing. If enabling dmac, dmac is activated. 1209 * When disabling dmac, dmac enable dmac bit is cleared. 1210 **/ 1211 s32 ixgbe_dmac_config(struct ixgbe_hw *hw) 1212 { 1213 return ixgbe_call_func(hw, hw->mac.ops.dmac_config, (hw), 1214 IXGBE_NOT_IMPLEMENTED); 1215 } 1216 1217 /** 1218 * ixgbe_dmac_update_tcs - Configure DMA Coalescing registers. 1219 * @hw: pointer to hardware structure 1220 * 1221 * Disables dmac, updates per TC settings, and then enable dmac. 1222 **/ 1223 s32 ixgbe_dmac_update_tcs(struct ixgbe_hw *hw) 1224 { 1225 return ixgbe_call_func(hw, hw->mac.ops.dmac_update_tcs, (hw), 1226 IXGBE_NOT_IMPLEMENTED); 1227 } 1228 1229 /** 1230 * ixgbe_dmac_config_tcs - Configure DMA Coalescing registers. 1231 * @hw: pointer to hardware structure 1232 * 1233 * Configure DMA coalescing threshold per TC and set high priority bit for 1234 * FCOE TC. The dmac enable bit must be cleared before configuring. 1235 **/ 1236 s32 ixgbe_dmac_config_tcs(struct ixgbe_hw *hw) 1237 { 1238 return ixgbe_call_func(hw, hw->mac.ops.dmac_config_tcs, (hw), 1239 IXGBE_NOT_IMPLEMENTED); 1240 } 1241 1242 /** 1243 * ixgbe_setup_eee - Enable/disable EEE support 1244 * @hw: pointer to the HW structure 1245 * @enable_eee: boolean flag to enable EEE 1246 * 1247 * Enable/disable EEE based on enable_ee flag. 1248 * Auto-negotiation must be started after BASE-T EEE bits in PHY register 7.3C 1249 * are modified. 1250 * 1251 **/ 1252 s32 ixgbe_setup_eee(struct ixgbe_hw *hw, bool enable_eee) 1253 { 1254 return ixgbe_call_func(hw, hw->mac.ops.setup_eee, (hw, enable_eee), 1255 IXGBE_NOT_IMPLEMENTED); 1256 } 1257 1258 /** 1259 * ixgbe_set_source_address_pruning - Enable/Disable source address pruning 1260 * @hw: pointer to hardware structure 1261 * @enable: enable or disable source address pruning 1262 * @pool: Rx pool - Rx pool to toggle source address pruning 1263 **/ 1264 void ixgbe_set_source_address_pruning(struct ixgbe_hw *hw, bool enable, 1265 unsigned int pool) 1266 { 1267 if (hw->mac.ops.set_source_address_pruning) 1268 hw->mac.ops.set_source_address_pruning(hw, enable, pool); 1269 } 1270 1271 /** 1272 * ixgbe_set_ethertype_anti_spoofing - Enable/Disable Ethertype anti-spoofing 1273 * @hw: pointer to hardware structure 1274 * @enable: enable or disable switch for Ethertype anti-spoofing 1275 * @vf: Virtual Function pool - VF Pool to set for Ethertype anti-spoofing 1276 * 1277 **/ 1278 void ixgbe_set_ethertype_anti_spoofing(struct ixgbe_hw *hw, bool enable, int vf) 1279 { 1280 if (hw->mac.ops.set_ethertype_anti_spoofing) 1281 hw->mac.ops.set_ethertype_anti_spoofing(hw, enable, vf); 1282 } 1283 1284 /** 1285 * ixgbe_read_iosf_sb_reg - Read 32 bit PHY register 1286 * @hw: pointer to hardware structure 1287 * @reg_addr: 32 bit address of PHY register to read 1288 * @device_type: type of device you want to communicate with 1289 * @phy_data: Pointer to read data from PHY register 1290 * 1291 * Reads a value from a specified PHY register 1292 **/ 1293 s32 ixgbe_read_iosf_sb_reg(struct ixgbe_hw *hw, u32 reg_addr, 1294 u32 device_type, u32 *phy_data) 1295 { 1296 return ixgbe_call_func(hw, hw->mac.ops.read_iosf_sb_reg, (hw, reg_addr, 1297 device_type, phy_data), IXGBE_NOT_IMPLEMENTED); 1298 } 1299 1300 /** 1301 * ixgbe_write_iosf_sb_reg - Write 32 bit register through IOSF Sideband 1302 * @hw: pointer to hardware structure 1303 * @reg_addr: 32 bit PHY register to write 1304 * @device_type: type of device you want to communicate with 1305 * @phy_data: Data to write to the PHY register 1306 * 1307 * Writes a value to specified PHY register 1308 **/ 1309 s32 ixgbe_write_iosf_sb_reg(struct ixgbe_hw *hw, u32 reg_addr, 1310 u32 device_type, u32 phy_data) 1311 { 1312 return ixgbe_call_func(hw, hw->mac.ops.write_iosf_sb_reg, (hw, reg_addr, 1313 device_type, phy_data), IXGBE_NOT_IMPLEMENTED); 1314 } 1315 1316 /** 1317 * ixgbe_disable_mdd - Disable malicious driver detection 1318 * @hw: pointer to hardware structure 1319 * 1320 **/ 1321 void ixgbe_disable_mdd(struct ixgbe_hw *hw) 1322 { 1323 if (hw->mac.ops.disable_mdd) 1324 hw->mac.ops.disable_mdd(hw); 1325 } 1326 1327 /** 1328 * ixgbe_enable_mdd - Enable malicious driver detection 1329 * @hw: pointer to hardware structure 1330 * 1331 **/ 1332 void ixgbe_enable_mdd(struct ixgbe_hw *hw) 1333 { 1334 if (hw->mac.ops.enable_mdd) 1335 hw->mac.ops.enable_mdd(hw); 1336 } 1337 1338 /** 1339 * ixgbe_mdd_event - Handle malicious driver detection event 1340 * @hw: pointer to hardware structure 1341 * @vf_bitmap: vf bitmap of malicious vfs 1342 * 1343 **/ 1344 void ixgbe_mdd_event(struct ixgbe_hw *hw, u32 *vf_bitmap) 1345 { 1346 if (hw->mac.ops.mdd_event) 1347 hw->mac.ops.mdd_event(hw, vf_bitmap); 1348 } 1349 1350 /** 1351 * ixgbe_restore_mdd_vf - Restore VF that was disabled during malicious driver 1352 * detection event 1353 * @hw: pointer to hardware structure 1354 * @vf: vf index 1355 * 1356 **/ 1357 void ixgbe_restore_mdd_vf(struct ixgbe_hw *hw, u32 vf) 1358 { 1359 if (hw->mac.ops.restore_mdd_vf) 1360 hw->mac.ops.restore_mdd_vf(hw, vf); 1361 } 1362 1363 /** 1364 * ixgbe_fw_recovery_mode - Check if in FW NVM recovery mode 1365 * @hw: pointer to hardware structure 1366 * 1367 **/ 1368 bool ixgbe_fw_recovery_mode(struct ixgbe_hw *hw) 1369 { 1370 if (hw->mac.ops.fw_recovery_mode) 1371 return hw->mac.ops.fw_recovery_mode(hw); 1372 return false; 1373 } 1374 1375 /** 1376 * ixgbe_enter_lplu - Transition to low power states 1377 * @hw: pointer to hardware structure 1378 * 1379 * Configures Low Power Link Up on transition to low power states 1380 * (from D0 to non-D0). 1381 **/ 1382 s32 ixgbe_enter_lplu(struct ixgbe_hw *hw) 1383 { 1384 return ixgbe_call_func(hw, hw->phy.ops.enter_lplu, (hw), 1385 IXGBE_NOT_IMPLEMENTED); 1386 } 1387 1388 /** 1389 * ixgbe_handle_lasi - Handle external Base T PHY interrupt 1390 * @hw: pointer to hardware structure 1391 * 1392 * Handle external Base T PHY interrupt. If high temperature 1393 * failure alarm then return error, else if link status change 1394 * then setup internal/external PHY link 1395 * 1396 * Return IXGBE_ERR_OVERTEMP if interrupt is high temperature 1397 * failure alarm, else return PHY access status. 1398 */ 1399 s32 ixgbe_handle_lasi(struct ixgbe_hw *hw) 1400 { 1401 return ixgbe_call_func(hw, hw->phy.ops.handle_lasi, (hw), 1402 IXGBE_NOT_IMPLEMENTED); 1403 } 1404 1405 /** 1406 * ixgbe_bypass_rw - Bit bang data into by_pass FW 1407 * @hw: pointer to hardware structure 1408 * @cmd: Command we send to the FW 1409 * @status: The reply from the FW 1410 * 1411 * Bit-bangs the cmd to the by_pass FW status points to what is returned. 1412 **/ 1413 s32 ixgbe_bypass_rw(struct ixgbe_hw *hw, u32 cmd, u32 *status) 1414 { 1415 return ixgbe_call_func(hw, hw->mac.ops.bypass_rw, (hw, cmd, status), 1416 IXGBE_NOT_IMPLEMENTED); 1417 } 1418 1419 /** 1420 * ixgbe_bypass_valid_rd - Verify valid return from bit-bang. 1421 * 1422 * If we send a write we can't be sure it took until we can read back 1423 * that same register. It can be a problem as some of the feilds may 1424 * for valid reasons change inbetween the time wrote the register and 1425 * we read it again to verify. So this function check everything we 1426 * can check and then assumes it worked. 1427 * 1428 * @u32 in_reg - The register cmd for the bit-bang read. 1429 * @u32 out_reg - The register returned from a bit-bang read. 1430 **/ 1431 bool ixgbe_bypass_valid_rd(struct ixgbe_hw *hw, u32 in_reg, u32 out_reg) 1432 { 1433 return ixgbe_call_func(hw, hw->mac.ops.bypass_valid_rd, 1434 (in_reg, out_reg), IXGBE_NOT_IMPLEMENTED); 1435 } 1436 1437 /** 1438 * ixgbe_bypass_set - Set a bypass field in the FW CTRL Regiter. 1439 * @hw: pointer to hardware structure 1440 * @cmd: The control word we are setting. 1441 * @event: The event we are setting in the FW. This also happens to 1442 * be the mask for the event we are setting (handy) 1443 * @action: The action we set the event to in the FW. This is in a 1444 * bit field that happens to be what we want to put in 1445 * the event spot (also handy) 1446 * 1447 * Writes to the cmd control the bits in actions. 1448 **/ 1449 s32 ixgbe_bypass_set(struct ixgbe_hw *hw, u32 cmd, u32 event, u32 action) 1450 { 1451 return ixgbe_call_func(hw, hw->mac.ops.bypass_set, 1452 (hw, cmd, event, action), 1453 IXGBE_NOT_IMPLEMENTED); 1454 } 1455 1456 /** 1457 * ixgbe_bypass_rd_eep - Read the bypass FW eeprom address 1458 * @hw: pointer to hardware structure 1459 * @addr: The bypass eeprom address to read. 1460 * @value: The 8b of data at the address above. 1461 **/ 1462 s32 ixgbe_bypass_rd_eep(struct ixgbe_hw *hw, u32 addr, u8 *value) 1463 { 1464 return ixgbe_call_func(hw, hw->mac.ops.bypass_rd_eep, 1465 (hw, addr, value), IXGBE_NOT_IMPLEMENTED); 1466 } 1467 1468 /** 1469 * ixgbe_read_analog_reg8 - Reads 8 bit analog register 1470 * @hw: pointer to hardware structure 1471 * @reg: analog register to read 1472 * @val: read value 1473 * 1474 * Performs write operation to analog register specified. 1475 **/ 1476 s32 ixgbe_read_analog_reg8(struct ixgbe_hw *hw, u32 reg, u8 *val) 1477 { 1478 return ixgbe_call_func(hw, hw->mac.ops.read_analog_reg8, (hw, reg, 1479 val), IXGBE_NOT_IMPLEMENTED); 1480 } 1481 1482 /** 1483 * ixgbe_write_analog_reg8 - Writes 8 bit analog register 1484 * @hw: pointer to hardware structure 1485 * @reg: analog register to write 1486 * @val: value to write 1487 * 1488 * Performs write operation to Atlas analog register specified. 1489 **/ 1490 s32 ixgbe_write_analog_reg8(struct ixgbe_hw *hw, u32 reg, u8 val) 1491 { 1492 return ixgbe_call_func(hw, hw->mac.ops.write_analog_reg8, (hw, reg, 1493 val), IXGBE_NOT_IMPLEMENTED); 1494 } 1495 1496 /** 1497 * ixgbe_init_uta_tables - Initializes Unicast Table Arrays. 1498 * @hw: pointer to hardware structure 1499 * 1500 * Initializes the Unicast Table Arrays to zero on device load. This 1501 * is part of the Rx init addr execution path. 1502 **/ 1503 s32 ixgbe_init_uta_tables(struct ixgbe_hw *hw) 1504 { 1505 return ixgbe_call_func(hw, hw->mac.ops.init_uta_tables, (hw), 1506 IXGBE_NOT_IMPLEMENTED); 1507 } 1508 1509 /** 1510 * ixgbe_read_i2c_byte - Reads 8 bit word over I2C at specified device address 1511 * @hw: pointer to hardware structure 1512 * @byte_offset: byte offset to read 1513 * @dev_addr: I2C bus address to read from 1514 * @data: value read 1515 * 1516 * Performs byte read operation to SFP module's EEPROM over I2C interface. 1517 **/ 1518 s32 ixgbe_read_i2c_byte(struct ixgbe_hw *hw, u8 byte_offset, u8 dev_addr, 1519 u8 *data) 1520 { 1521 return ixgbe_call_func(hw, hw->phy.ops.read_i2c_byte, (hw, byte_offset, 1522 dev_addr, data), IXGBE_NOT_IMPLEMENTED); 1523 } 1524 1525 /** 1526 * ixgbe_read_i2c_byte_unlocked - Reads 8 bit word via I2C from device address 1527 * @hw: pointer to hardware structure 1528 * @byte_offset: byte offset to read 1529 * @dev_addr: I2C bus address to read from 1530 * @data: value read 1531 * 1532 * Performs byte read operation to SFP module's EEPROM over I2C interface. 1533 **/ 1534 s32 ixgbe_read_i2c_byte_unlocked(struct ixgbe_hw *hw, u8 byte_offset, 1535 u8 dev_addr, u8 *data) 1536 { 1537 return ixgbe_call_func(hw, hw->phy.ops.read_i2c_byte_unlocked, 1538 (hw, byte_offset, dev_addr, data), 1539 IXGBE_NOT_IMPLEMENTED); 1540 } 1541 1542 /** 1543 * ixgbe_read_link - Perform read operation on link device 1544 * @hw: pointer to the hardware structure 1545 * @addr: bus address to read from 1546 * @reg: device register to read from 1547 * @val: pointer to location to receive read value 1548 * 1549 * Returns an error code on error. 1550 */ 1551 s32 ixgbe_read_link(struct ixgbe_hw *hw, u8 addr, u16 reg, u16 *val) 1552 { 1553 return ixgbe_call_func(hw, hw->link.ops.read_link, (hw, addr, 1554 reg, val), IXGBE_NOT_IMPLEMENTED); 1555 } 1556 1557 /** 1558 * ixgbe_read_link_unlocked - Perform read operation on link device 1559 * @hw: pointer to the hardware structure 1560 * @addr: bus address to read from 1561 * @reg: device register to read from 1562 * @val: pointer to location to receive read value 1563 * 1564 * Returns an error code on error. 1565 **/ 1566 s32 ixgbe_read_link_unlocked(struct ixgbe_hw *hw, u8 addr, u16 reg, u16 *val) 1567 { 1568 return ixgbe_call_func(hw, hw->link.ops.read_link_unlocked, 1569 (hw, addr, reg, val), IXGBE_NOT_IMPLEMENTED); 1570 } 1571 1572 /** 1573 * ixgbe_write_i2c_byte - Writes 8 bit word over I2C 1574 * @hw: pointer to hardware structure 1575 * @byte_offset: byte offset to write 1576 * @dev_addr: I2C bus address to write to 1577 * @data: value to write 1578 * 1579 * Performs byte write operation to SFP module's EEPROM over I2C interface 1580 * at a specified device address. 1581 **/ 1582 s32 ixgbe_write_i2c_byte(struct ixgbe_hw *hw, u8 byte_offset, u8 dev_addr, 1583 u8 data) 1584 { 1585 return ixgbe_call_func(hw, hw->phy.ops.write_i2c_byte, (hw, byte_offset, 1586 dev_addr, data), IXGBE_NOT_IMPLEMENTED); 1587 } 1588 1589 /** 1590 * ixgbe_write_i2c_byte_unlocked - Writes 8 bit word over I2C 1591 * @hw: pointer to hardware structure 1592 * @byte_offset: byte offset to write 1593 * @dev_addr: I2C bus address to write to 1594 * @data: value to write 1595 * 1596 * Performs byte write operation to SFP module's EEPROM over I2C interface 1597 * at a specified device address. 1598 **/ 1599 s32 ixgbe_write_i2c_byte_unlocked(struct ixgbe_hw *hw, u8 byte_offset, 1600 u8 dev_addr, u8 data) 1601 { 1602 return ixgbe_call_func(hw, hw->phy.ops.write_i2c_byte_unlocked, 1603 (hw, byte_offset, dev_addr, data), 1604 IXGBE_NOT_IMPLEMENTED); 1605 } 1606 1607 /** 1608 * ixgbe_write_link - Perform write operation on link device 1609 * @hw: pointer to the hardware structure 1610 * @addr: bus address to write to 1611 * @reg: device register to write to 1612 * @val: value to write 1613 * 1614 * Returns an error code on error. 1615 */ 1616 s32 ixgbe_write_link(struct ixgbe_hw *hw, u8 addr, u16 reg, u16 val) 1617 { 1618 return ixgbe_call_func(hw, hw->link.ops.write_link, 1619 (hw, addr, reg, val), IXGBE_NOT_IMPLEMENTED); 1620 } 1621 1622 /** 1623 * ixgbe_write_link_unlocked - Perform write operation on link device 1624 * @hw: pointer to the hardware structure 1625 * @addr: bus address to write to 1626 * @reg: device register to write to 1627 * @val: value to write 1628 * 1629 * Returns an error code on error. 1630 **/ 1631 s32 ixgbe_write_link_unlocked(struct ixgbe_hw *hw, u8 addr, u16 reg, u16 val) 1632 { 1633 return ixgbe_call_func(hw, hw->link.ops.write_link_unlocked, 1634 (hw, addr, reg, val), IXGBE_NOT_IMPLEMENTED); 1635 } 1636 1637 /** 1638 * ixgbe_write_i2c_eeprom - Writes 8 bit EEPROM word over I2C interface 1639 * @hw: pointer to hardware structure 1640 * @byte_offset: EEPROM byte offset to write 1641 * @eeprom_data: value to write 1642 * 1643 * Performs byte write operation to SFP module's EEPROM over I2C interface. 1644 **/ 1645 s32 ixgbe_write_i2c_eeprom(struct ixgbe_hw *hw, 1646 u8 byte_offset, u8 eeprom_data) 1647 { 1648 return ixgbe_call_func(hw, hw->phy.ops.write_i2c_eeprom, 1649 (hw, byte_offset, eeprom_data), 1650 IXGBE_NOT_IMPLEMENTED); 1651 } 1652 1653 /** 1654 * ixgbe_read_i2c_eeprom - Reads 8 bit EEPROM word over I2C interface 1655 * @hw: pointer to hardware structure 1656 * @byte_offset: EEPROM byte offset to read 1657 * @eeprom_data: value read 1658 * 1659 * Performs byte read operation to SFP module's EEPROM over I2C interface. 1660 **/ 1661 s32 ixgbe_read_i2c_eeprom(struct ixgbe_hw *hw, u8 byte_offset, u8 *eeprom_data) 1662 { 1663 return ixgbe_call_func(hw, hw->phy.ops.read_i2c_eeprom, 1664 (hw, byte_offset, eeprom_data), 1665 IXGBE_NOT_IMPLEMENTED); 1666 } 1667 1668 /** 1669 * ixgbe_get_supported_physical_layer - Returns physical layer type 1670 * @hw: pointer to hardware structure 1671 * 1672 * Determines physical layer capabilities of the current configuration. 1673 **/ 1674 u64 ixgbe_get_supported_physical_layer(struct ixgbe_hw *hw) 1675 { 1676 return ixgbe_call_func(hw, hw->mac.ops.get_supported_physical_layer, 1677 (hw), IXGBE_PHYSICAL_LAYER_UNKNOWN); 1678 } 1679 1680 /** 1681 * ixgbe_enable_rx_dma - Enables Rx DMA unit, dependent on device specifics 1682 * @hw: pointer to hardware structure 1683 * @regval: bitfield to write to the Rx DMA register 1684 * 1685 * Enables the Rx DMA unit of the device. 1686 **/ 1687 s32 ixgbe_enable_rx_dma(struct ixgbe_hw *hw, u32 regval) 1688 { 1689 return ixgbe_call_func(hw, hw->mac.ops.enable_rx_dma, 1690 (hw, regval), IXGBE_NOT_IMPLEMENTED); 1691 } 1692 1693 /** 1694 * ixgbe_disable_sec_rx_path - Stops the receive data path 1695 * @hw: pointer to hardware structure 1696 * 1697 * Stops the receive data path. 1698 **/ 1699 s32 ixgbe_disable_sec_rx_path(struct ixgbe_hw *hw) 1700 { 1701 return ixgbe_call_func(hw, hw->mac.ops.disable_sec_rx_path, 1702 (hw), IXGBE_NOT_IMPLEMENTED); 1703 } 1704 1705 /** 1706 * ixgbe_enable_sec_rx_path - Enables the receive data path 1707 * @hw: pointer to hardware structure 1708 * 1709 * Enables the receive data path. 1710 **/ 1711 s32 ixgbe_enable_sec_rx_path(struct ixgbe_hw *hw) 1712 { 1713 return ixgbe_call_func(hw, hw->mac.ops.enable_sec_rx_path, 1714 (hw), IXGBE_NOT_IMPLEMENTED); 1715 } 1716 1717 /** 1718 * ixgbe_acquire_swfw_semaphore - Acquire SWFW semaphore 1719 * @hw: pointer to hardware structure 1720 * @mask: Mask to specify which semaphore to acquire 1721 * 1722 * Acquires the SWFW semaphore through SW_FW_SYNC register for the specified 1723 * function (CSR, PHY0, PHY1, EEPROM, Flash) 1724 **/ 1725 s32 ixgbe_acquire_swfw_semaphore(struct ixgbe_hw *hw, u32 mask) 1726 { 1727 return ixgbe_call_func(hw, hw->mac.ops.acquire_swfw_sync, 1728 (hw, mask), IXGBE_NOT_IMPLEMENTED); 1729 } 1730 1731 /** 1732 * ixgbe_release_swfw_semaphore - Release SWFW semaphore 1733 * @hw: pointer to hardware structure 1734 * @mask: Mask to specify which semaphore to release 1735 * 1736 * Releases the SWFW semaphore through SW_FW_SYNC register for the specified 1737 * function (CSR, PHY0, PHY1, EEPROM, Flash) 1738 **/ 1739 void ixgbe_release_swfw_semaphore(struct ixgbe_hw *hw, u32 mask) 1740 { 1741 if (hw->mac.ops.release_swfw_sync) 1742 hw->mac.ops.release_swfw_sync(hw, mask); 1743 } 1744 1745 /** 1746 * ixgbe_init_swfw_semaphore - Clean up SWFW semaphore 1747 * @hw: pointer to hardware structure 1748 * 1749 * Attempts to acquire the SWFW semaphore through SW_FW_SYNC register. 1750 * Regardless of whether is succeeds or not it then release the semaphore. 1751 * This is function is called to recover from catastrophic failures that 1752 * may have left the semaphore locked. 1753 **/ 1754 void ixgbe_init_swfw_semaphore(struct ixgbe_hw *hw) 1755 { 1756 if (hw->mac.ops.init_swfw_sync) 1757 hw->mac.ops.init_swfw_sync(hw); 1758 } 1759 1760 1761 void ixgbe_disable_rx(struct ixgbe_hw *hw) 1762 { 1763 if (hw->mac.ops.disable_rx) 1764 hw->mac.ops.disable_rx(hw); 1765 } 1766 1767 void ixgbe_enable_rx(struct ixgbe_hw *hw) 1768 { 1769 if (hw->mac.ops.enable_rx) 1770 hw->mac.ops.enable_rx(hw); 1771 } 1772 1773 /** 1774 * ixgbe_set_rate_select_speed - Set module link speed 1775 * @hw: pointer to hardware structure 1776 * @speed: link speed to set 1777 * 1778 * Set module link speed via the rate select. 1779 */ 1780 void ixgbe_set_rate_select_speed(struct ixgbe_hw *hw, ixgbe_link_speed speed) 1781 { 1782 if (hw->mac.ops.set_rate_select_speed) 1783 hw->mac.ops.set_rate_select_speed(hw, speed); 1784 } 1785