1 /****************************************************************************** 2 3 Copyright (c) 2001-2010, Intel Corporation 4 All rights reserved. 5 6 Redistribution and use in source and binary forms, with or without 7 modification, are permitted provided that the following conditions are met: 8 9 1. Redistributions of source code must retain the above copyright notice, 10 this list of conditions and the following disclaimer. 11 12 2. Redistributions in binary form must reproduce the above copyright 13 notice, this list of conditions and the following disclaimer in the 14 documentation and/or other materials provided with the distribution. 15 16 3. Neither the name of the Intel Corporation nor the names of its 17 contributors may be used to endorse or promote products derived from 18 this software without specific prior written permission. 19 20 THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 21 AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 22 IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 23 ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE 24 LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 25 CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 26 SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 27 INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 28 CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 29 ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 30 POSSIBILITY OF SUCH DAMAGE. 31 32 ******************************************************************************/ 33 /*$FreeBSD$*/ 34 35 #include "ixgbe_type.h" 36 #include "ixgbe_api.h" 37 #include "ixgbe_common.h" 38 #include "ixgbe_phy.h" 39 40 s32 ixgbe_init_ops_82599(struct ixgbe_hw *hw); 41 s32 ixgbe_get_link_capabilities_82599(struct ixgbe_hw *hw, 42 ixgbe_link_speed *speed, 43 bool *autoneg); 44 enum ixgbe_media_type ixgbe_get_media_type_82599(struct ixgbe_hw *hw); 45 void ixgbe_disable_tx_laser_multispeed_fiber(struct ixgbe_hw *hw); 46 void ixgbe_enable_tx_laser_multispeed_fiber(struct ixgbe_hw *hw); 47 void ixgbe_flap_tx_laser_multispeed_fiber(struct ixgbe_hw *hw); 48 s32 ixgbe_setup_mac_link_multispeed_fiber(struct ixgbe_hw *hw, 49 ixgbe_link_speed speed, bool autoneg, 50 bool autoneg_wait_to_complete); 51 s32 ixgbe_setup_mac_link_smartspeed(struct ixgbe_hw *hw, 52 ixgbe_link_speed speed, bool autoneg, 53 bool autoneg_wait_to_complete); 54 s32 ixgbe_start_mac_link_82599(struct ixgbe_hw *hw, 55 bool autoneg_wait_to_complete); 56 s32 ixgbe_setup_mac_link_82599(struct ixgbe_hw *hw, 57 ixgbe_link_speed speed, 58 bool autoneg, 59 bool autoneg_wait_to_complete); 60 static s32 ixgbe_setup_copper_link_82599(struct ixgbe_hw *hw, 61 ixgbe_link_speed speed, 62 bool autoneg, 63 bool autoneg_wait_to_complete); 64 s32 ixgbe_setup_sfp_modules_82599(struct ixgbe_hw *hw); 65 void ixgbe_init_mac_link_ops_82599(struct ixgbe_hw *hw); 66 s32 ixgbe_reset_hw_82599(struct ixgbe_hw *hw); 67 s32 ixgbe_read_analog_reg8_82599(struct ixgbe_hw *hw, u32 reg, u8 *val); 68 s32 ixgbe_write_analog_reg8_82599(struct ixgbe_hw *hw, u32 reg, u8 val); 69 s32 ixgbe_start_hw_rev_1_82599(struct ixgbe_hw *hw); 70 s32 ixgbe_identify_phy_82599(struct ixgbe_hw *hw); 71 s32 ixgbe_init_phy_ops_82599(struct ixgbe_hw *hw); 72 u32 ixgbe_get_supported_physical_layer_82599(struct ixgbe_hw *hw); 73 s32 ixgbe_enable_rx_dma_82599(struct ixgbe_hw *hw, u32 regval); 74 static s32 ixgbe_verify_fw_version_82599(struct ixgbe_hw *hw); 75 bool ixgbe_verify_lesm_fw_enabled_82599(struct ixgbe_hw *hw); 76 77 78 void ixgbe_init_mac_link_ops_82599(struct ixgbe_hw *hw) 79 { 80 struct ixgbe_mac_info *mac = &hw->mac; 81 82 DEBUGFUNC("ixgbe_init_mac_link_ops_82599"); 83 84 /* enable the laser control functions for SFP+ fiber */ 85 if (mac->ops.get_media_type(hw) == ixgbe_media_type_fiber) { 86 mac->ops.disable_tx_laser = 87 &ixgbe_disable_tx_laser_multispeed_fiber; 88 mac->ops.enable_tx_laser = 89 &ixgbe_enable_tx_laser_multispeed_fiber; 90 mac->ops.flap_tx_laser = &ixgbe_flap_tx_laser_multispeed_fiber; 91 92 } else { 93 mac->ops.disable_tx_laser = NULL; 94 mac->ops.enable_tx_laser = NULL; 95 mac->ops.flap_tx_laser = NULL; 96 } 97 98 if (hw->phy.multispeed_fiber) { 99 /* Set up dual speed SFP+ support */ 100 mac->ops.setup_link = &ixgbe_setup_mac_link_multispeed_fiber; 101 } else { 102 if ((ixgbe_get_media_type(hw) == ixgbe_media_type_backplane) && 103 (hw->phy.smart_speed == ixgbe_smart_speed_auto || 104 hw->phy.smart_speed == ixgbe_smart_speed_on) && 105 !ixgbe_verify_lesm_fw_enabled_82599(hw)) { 106 mac->ops.setup_link = &ixgbe_setup_mac_link_smartspeed; 107 } else { 108 mac->ops.setup_link = &ixgbe_setup_mac_link_82599; 109 } 110 } 111 } 112 113 /** 114 * ixgbe_init_phy_ops_82599 - PHY/SFP specific init 115 * @hw: pointer to hardware structure 116 * 117 * Initialize any function pointers that were not able to be 118 * set during init_shared_code because the PHY/SFP type was 119 * not known. Perform the SFP init if necessary. 120 * 121 **/ 122 s32 ixgbe_init_phy_ops_82599(struct ixgbe_hw *hw) 123 { 124 struct ixgbe_mac_info *mac = &hw->mac; 125 struct ixgbe_phy_info *phy = &hw->phy; 126 s32 ret_val = IXGBE_SUCCESS; 127 128 DEBUGFUNC("ixgbe_init_phy_ops_82599"); 129 130 /* Identify the PHY or SFP module */ 131 ret_val = phy->ops.identify(hw); 132 if (ret_val == IXGBE_ERR_SFP_NOT_SUPPORTED) 133 goto init_phy_ops_out; 134 135 /* Setup function pointers based on detected SFP module and speeds */ 136 ixgbe_init_mac_link_ops_82599(hw); 137 if (hw->phy.sfp_type != ixgbe_sfp_type_unknown) 138 hw->phy.ops.reset = NULL; 139 140 /* If copper media, overwrite with copper function pointers */ 141 if (mac->ops.get_media_type(hw) == ixgbe_media_type_copper) { 142 mac->ops.setup_link = &ixgbe_setup_copper_link_82599; 143 mac->ops.get_link_capabilities = 144 &ixgbe_get_copper_link_capabilities_generic; 145 } 146 147 /* Set necessary function pointers based on phy type */ 148 switch (hw->phy.type) { 149 case ixgbe_phy_tn: 150 phy->ops.setup_link = &ixgbe_setup_phy_link_tnx; 151 phy->ops.check_link = &ixgbe_check_phy_link_tnx; 152 phy->ops.get_firmware_version = 153 &ixgbe_get_phy_firmware_version_tnx; 154 break; 155 case ixgbe_phy_aq: 156 phy->ops.get_firmware_version = 157 &ixgbe_get_phy_firmware_version_generic; 158 break; 159 default: 160 break; 161 } 162 init_phy_ops_out: 163 return ret_val; 164 } 165 166 s32 ixgbe_setup_sfp_modules_82599(struct ixgbe_hw *hw) 167 { 168 s32 ret_val = IXGBE_SUCCESS; 169 u32 reg_anlp1 = 0; 170 u32 i = 0; 171 u16 list_offset, data_offset, data_value; 172 173 DEBUGFUNC("ixgbe_setup_sfp_modules_82599"); 174 175 if (hw->phy.sfp_type != ixgbe_sfp_type_unknown) { 176 ixgbe_init_mac_link_ops_82599(hw); 177 178 hw->phy.ops.reset = NULL; 179 180 ret_val = ixgbe_get_sfp_init_sequence_offsets(hw, &list_offset, 181 &data_offset); 182 if (ret_val != IXGBE_SUCCESS) 183 goto setup_sfp_out; 184 185 /* PHY config will finish before releasing the semaphore */ 186 ret_val = ixgbe_acquire_swfw_sync(hw, IXGBE_GSSR_MAC_CSR_SM); 187 if (ret_val != IXGBE_SUCCESS) { 188 ret_val = IXGBE_ERR_SWFW_SYNC; 189 goto setup_sfp_out; 190 } 191 192 hw->eeprom.ops.read(hw, ++data_offset, &data_value); 193 while (data_value != 0xffff) { 194 IXGBE_WRITE_REG(hw, IXGBE_CORECTL, data_value); 195 IXGBE_WRITE_FLUSH(hw); 196 hw->eeprom.ops.read(hw, ++data_offset, &data_value); 197 } 198 199 /* Release the semaphore */ 200 ixgbe_release_swfw_sync(hw, IXGBE_GSSR_MAC_CSR_SM); 201 /* Delay obtaining semaphore again to allow FW access */ 202 msec_delay(hw->eeprom.semaphore_delay); 203 204 /* Now restart DSP by setting Restart_AN and clearing LMS */ 205 IXGBE_WRITE_REG(hw, IXGBE_AUTOC, ((IXGBE_READ_REG(hw, 206 IXGBE_AUTOC) & ~IXGBE_AUTOC_LMS_MASK) | 207 IXGBE_AUTOC_AN_RESTART)); 208 209 /* Wait for AN to leave state 0 */ 210 for (i = 0; i < 10; i++) { 211 msec_delay(4); 212 reg_anlp1 = IXGBE_READ_REG(hw, IXGBE_ANLP1); 213 if (reg_anlp1 & IXGBE_ANLP1_AN_STATE_MASK) 214 break; 215 } 216 if (!(reg_anlp1 & IXGBE_ANLP1_AN_STATE_MASK)) { 217 DEBUGOUT("sfp module setup not complete\n"); 218 ret_val = IXGBE_ERR_SFP_SETUP_NOT_COMPLETE; 219 goto setup_sfp_out; 220 } 221 222 /* Restart DSP by setting Restart_AN and return to SFI mode */ 223 IXGBE_WRITE_REG(hw, IXGBE_AUTOC, (IXGBE_READ_REG(hw, 224 IXGBE_AUTOC) | IXGBE_AUTOC_LMS_10G_SERIAL | 225 IXGBE_AUTOC_AN_RESTART)); 226 } 227 228 setup_sfp_out: 229 return ret_val; 230 } 231 232 /** 233 * ixgbe_init_ops_82599 - Inits func ptrs and MAC type 234 * @hw: pointer to hardware structure 235 * 236 * Initialize the function pointers and assign the MAC type for 82599. 237 * Does not touch the hardware. 238 **/ 239 240 s32 ixgbe_init_ops_82599(struct ixgbe_hw *hw) 241 { 242 struct ixgbe_mac_info *mac = &hw->mac; 243 struct ixgbe_phy_info *phy = &hw->phy; 244 s32 ret_val; 245 246 DEBUGFUNC("ixgbe_init_ops_82599"); 247 248 ret_val = ixgbe_init_phy_ops_generic(hw); 249 ret_val = ixgbe_init_ops_generic(hw); 250 251 /* PHY */ 252 phy->ops.identify = &ixgbe_identify_phy_82599; 253 phy->ops.init = &ixgbe_init_phy_ops_82599; 254 255 /* MAC */ 256 mac->ops.reset_hw = &ixgbe_reset_hw_82599; 257 mac->ops.enable_relaxed_ordering = &ixgbe_enable_relaxed_ordering_gen2; 258 mac->ops.get_media_type = &ixgbe_get_media_type_82599; 259 mac->ops.get_supported_physical_layer = 260 &ixgbe_get_supported_physical_layer_82599; 261 mac->ops.enable_rx_dma = &ixgbe_enable_rx_dma_82599; 262 mac->ops.read_analog_reg8 = &ixgbe_read_analog_reg8_82599; 263 mac->ops.write_analog_reg8 = &ixgbe_write_analog_reg8_82599; 264 mac->ops.start_hw = &ixgbe_start_hw_rev_1_82599; 265 mac->ops.get_san_mac_addr = &ixgbe_get_san_mac_addr_generic; 266 mac->ops.set_san_mac_addr = &ixgbe_set_san_mac_addr_generic; 267 mac->ops.get_device_caps = &ixgbe_get_device_caps_generic; 268 mac->ops.get_wwn_prefix = &ixgbe_get_wwn_prefix_generic; 269 mac->ops.get_fcoe_boot_status = &ixgbe_get_fcoe_boot_status_generic; 270 271 /* RAR, Multicast, VLAN */ 272 mac->ops.set_vmdq = &ixgbe_set_vmdq_generic; 273 mac->ops.clear_vmdq = &ixgbe_clear_vmdq_generic; 274 mac->ops.insert_mac_addr = &ixgbe_insert_mac_addr_generic; 275 mac->rar_highwater = 1; 276 mac->ops.set_vfta = &ixgbe_set_vfta_generic; 277 mac->ops.clear_vfta = &ixgbe_clear_vfta_generic; 278 mac->ops.init_uta_tables = &ixgbe_init_uta_tables_generic; 279 mac->ops.setup_sfp = &ixgbe_setup_sfp_modules_82599; 280 mac->ops.set_mac_anti_spoofing = &ixgbe_set_mac_anti_spoofing; 281 mac->ops.set_vlan_anti_spoofing = &ixgbe_set_vlan_anti_spoofing; 282 283 /* Link */ 284 mac->ops.get_link_capabilities = &ixgbe_get_link_capabilities_82599; 285 mac->ops.check_link = &ixgbe_check_mac_link_generic; 286 ixgbe_init_mac_link_ops_82599(hw); 287 288 mac->mcft_size = 128; 289 mac->vft_size = 128; 290 mac->num_rar_entries = 128; 291 mac->rx_pb_size = 512; 292 mac->max_tx_queues = 128; 293 mac->max_rx_queues = 128; 294 mac->max_msix_vectors = ixgbe_get_pcie_msix_count_generic(hw); 295 296 hw->mbx.ops.init_params = ixgbe_init_mbx_params_pf; 297 298 return ret_val; 299 } 300 301 /** 302 * ixgbe_get_link_capabilities_82599 - Determines link capabilities 303 * @hw: pointer to hardware structure 304 * @speed: pointer to link speed 305 * @negotiation: TRUE when autoneg or autotry is enabled 306 * 307 * Determines the link capabilities by reading the AUTOC register. 308 **/ 309 s32 ixgbe_get_link_capabilities_82599(struct ixgbe_hw *hw, 310 ixgbe_link_speed *speed, 311 bool *negotiation) 312 { 313 s32 status = IXGBE_SUCCESS; 314 u32 autoc = 0; 315 316 DEBUGFUNC("ixgbe_get_link_capabilities_82599"); 317 318 319 /* Check if 1G SFP module. */ 320 if (hw->phy.sfp_type == ixgbe_sfp_type_1g_cu_core0 || 321 hw->phy.sfp_type == ixgbe_sfp_type_1g_cu_core1) { 322 *speed = IXGBE_LINK_SPEED_1GB_FULL; 323 *negotiation = TRUE; 324 goto out; 325 } 326 327 /* 328 * Determine link capabilities based on the stored value of AUTOC, 329 * which represents EEPROM defaults. If AUTOC value has not 330 * been stored, use the current register values. 331 */ 332 if (hw->mac.orig_link_settings_stored) 333 autoc = hw->mac.orig_autoc; 334 else 335 autoc = IXGBE_READ_REG(hw, IXGBE_AUTOC); 336 337 switch (autoc & IXGBE_AUTOC_LMS_MASK) { 338 case IXGBE_AUTOC_LMS_1G_LINK_NO_AN: 339 *speed = IXGBE_LINK_SPEED_1GB_FULL; 340 *negotiation = FALSE; 341 break; 342 343 case IXGBE_AUTOC_LMS_10G_LINK_NO_AN: 344 *speed = IXGBE_LINK_SPEED_10GB_FULL; 345 *negotiation = FALSE; 346 break; 347 348 case IXGBE_AUTOC_LMS_1G_AN: 349 *speed = IXGBE_LINK_SPEED_1GB_FULL; 350 *negotiation = TRUE; 351 break; 352 353 case IXGBE_AUTOC_LMS_10G_SERIAL: 354 *speed = IXGBE_LINK_SPEED_10GB_FULL; 355 *negotiation = FALSE; 356 break; 357 358 case IXGBE_AUTOC_LMS_KX4_KX_KR: 359 case IXGBE_AUTOC_LMS_KX4_KX_KR_1G_AN: 360 *speed = IXGBE_LINK_SPEED_UNKNOWN; 361 if (autoc & IXGBE_AUTOC_KR_SUPP) 362 *speed |= IXGBE_LINK_SPEED_10GB_FULL; 363 if (autoc & IXGBE_AUTOC_KX4_SUPP) 364 *speed |= IXGBE_LINK_SPEED_10GB_FULL; 365 if (autoc & IXGBE_AUTOC_KX_SUPP) 366 *speed |= IXGBE_LINK_SPEED_1GB_FULL; 367 *negotiation = TRUE; 368 break; 369 370 case IXGBE_AUTOC_LMS_KX4_KX_KR_SGMII: 371 *speed = IXGBE_LINK_SPEED_100_FULL; 372 if (autoc & IXGBE_AUTOC_KR_SUPP) 373 *speed |= IXGBE_LINK_SPEED_10GB_FULL; 374 if (autoc & IXGBE_AUTOC_KX4_SUPP) 375 *speed |= IXGBE_LINK_SPEED_10GB_FULL; 376 if (autoc & IXGBE_AUTOC_KX_SUPP) 377 *speed |= IXGBE_LINK_SPEED_1GB_FULL; 378 *negotiation = TRUE; 379 break; 380 381 case IXGBE_AUTOC_LMS_SGMII_1G_100M: 382 *speed = IXGBE_LINK_SPEED_1GB_FULL | IXGBE_LINK_SPEED_100_FULL; 383 *negotiation = FALSE; 384 break; 385 386 default: 387 status = IXGBE_ERR_LINK_SETUP; 388 goto out; 389 break; 390 } 391 392 if (hw->phy.multispeed_fiber) { 393 *speed |= IXGBE_LINK_SPEED_10GB_FULL | 394 IXGBE_LINK_SPEED_1GB_FULL; 395 *negotiation = TRUE; 396 } 397 398 out: 399 return status; 400 } 401 402 /** 403 * ixgbe_get_media_type_82599 - Get media type 404 * @hw: pointer to hardware structure 405 * 406 * Returns the media type (fiber, copper, backplane) 407 **/ 408 enum ixgbe_media_type ixgbe_get_media_type_82599(struct ixgbe_hw *hw) 409 { 410 enum ixgbe_media_type media_type; 411 412 DEBUGFUNC("ixgbe_get_media_type_82599"); 413 414 /* Detect if there is a copper PHY attached. */ 415 switch (hw->phy.type) { 416 case ixgbe_phy_cu_unknown: 417 case ixgbe_phy_tn: 418 case ixgbe_phy_aq: 419 media_type = ixgbe_media_type_copper; 420 goto out; 421 default: 422 break; 423 } 424 425 switch (hw->device_id) { 426 case IXGBE_DEV_ID_82599_KX4: 427 case IXGBE_DEV_ID_82599_KX4_MEZZ: 428 case IXGBE_DEV_ID_82599_COMBO_BACKPLANE: 429 case IXGBE_DEV_ID_82599_BACKPLANE_FCOE: 430 case IXGBE_DEV_ID_82599_XAUI_LOM: 431 /* Default device ID is mezzanine card KX/KX4 */ 432 media_type = ixgbe_media_type_backplane; 433 break; 434 case IXGBE_DEV_ID_82599_SFP: 435 case IXGBE_DEV_ID_82599_SFP_FCOE: 436 media_type = ixgbe_media_type_fiber; 437 break; 438 case IXGBE_DEV_ID_82599_CX4: 439 media_type = ixgbe_media_type_cx4; 440 break; 441 case IXGBE_DEV_ID_82599_T3_LOM: 442 media_type = ixgbe_media_type_copper; 443 break; 444 default: 445 media_type = ixgbe_media_type_unknown; 446 break; 447 } 448 out: 449 return media_type; 450 } 451 452 /** 453 * ixgbe_start_mac_link_82599 - Setup MAC link settings 454 * @hw: pointer to hardware structure 455 * @autoneg_wait_to_complete: TRUE when waiting for completion is needed 456 * 457 * Configures link settings based on values in the ixgbe_hw struct. 458 * Restarts the link. Performs autonegotiation if needed. 459 **/ 460 s32 ixgbe_start_mac_link_82599(struct ixgbe_hw *hw, 461 bool autoneg_wait_to_complete) 462 { 463 u32 autoc_reg; 464 u32 links_reg; 465 u32 i; 466 s32 status = IXGBE_SUCCESS; 467 468 DEBUGFUNC("ixgbe_start_mac_link_82599"); 469 470 471 /* Restart link */ 472 autoc_reg = IXGBE_READ_REG(hw, IXGBE_AUTOC); 473 autoc_reg |= IXGBE_AUTOC_AN_RESTART; 474 IXGBE_WRITE_REG(hw, IXGBE_AUTOC, autoc_reg); 475 476 /* Only poll for autoneg to complete if specified to do so */ 477 if (autoneg_wait_to_complete) { 478 if ((autoc_reg & IXGBE_AUTOC_LMS_MASK) == 479 IXGBE_AUTOC_LMS_KX4_KX_KR || 480 (autoc_reg & IXGBE_AUTOC_LMS_MASK) == 481 IXGBE_AUTOC_LMS_KX4_KX_KR_1G_AN || 482 (autoc_reg & IXGBE_AUTOC_LMS_MASK) == 483 IXGBE_AUTOC_LMS_KX4_KX_KR_SGMII) { 484 links_reg = 0; /* Just in case Autoneg time = 0 */ 485 for (i = 0; i < IXGBE_AUTO_NEG_TIME; i++) { 486 links_reg = IXGBE_READ_REG(hw, IXGBE_LINKS); 487 if (links_reg & IXGBE_LINKS_KX_AN_COMP) 488 break; 489 msec_delay(100); 490 } 491 if (!(links_reg & IXGBE_LINKS_KX_AN_COMP)) { 492 status = IXGBE_ERR_AUTONEG_NOT_COMPLETE; 493 DEBUGOUT("Autoneg did not complete.\n"); 494 } 495 } 496 } 497 498 /* Add delay to filter out noises during initial link setup */ 499 msec_delay(50); 500 501 return status; 502 } 503 504 /** 505 * ixgbe_disable_tx_laser_multispeed_fiber - Disable Tx laser 506 * @hw: pointer to hardware structure 507 * 508 * The base drivers may require better control over SFP+ module 509 * PHY states. This includes selectively shutting down the Tx 510 * laser on the PHY, effectively halting physical link. 511 **/ 512 void ixgbe_disable_tx_laser_multispeed_fiber(struct ixgbe_hw *hw) 513 { 514 u32 esdp_reg = IXGBE_READ_REG(hw, IXGBE_ESDP); 515 516 /* Disable tx laser; allow 100us to go dark per spec */ 517 esdp_reg |= IXGBE_ESDP_SDP3; 518 IXGBE_WRITE_REG(hw, IXGBE_ESDP, esdp_reg); 519 IXGBE_WRITE_FLUSH(hw); 520 usec_delay(100); 521 } 522 523 /** 524 * ixgbe_enable_tx_laser_multispeed_fiber - Enable Tx laser 525 * @hw: pointer to hardware structure 526 * 527 * The base drivers may require better control over SFP+ module 528 * PHY states. This includes selectively turning on the Tx 529 * laser on the PHY, effectively starting physical link. 530 **/ 531 void ixgbe_enable_tx_laser_multispeed_fiber(struct ixgbe_hw *hw) 532 { 533 u32 esdp_reg = IXGBE_READ_REG(hw, IXGBE_ESDP); 534 535 /* Enable tx laser; allow 100ms to light up */ 536 esdp_reg &= ~IXGBE_ESDP_SDP3; 537 IXGBE_WRITE_REG(hw, IXGBE_ESDP, esdp_reg); 538 IXGBE_WRITE_FLUSH(hw); 539 msec_delay(100); 540 } 541 542 /** 543 * ixgbe_flap_tx_laser_multispeed_fiber - Flap Tx laser 544 * @hw: pointer to hardware structure 545 * 546 * When the driver changes the link speeds that it can support, 547 * it sets autotry_restart to TRUE to indicate that we need to 548 * initiate a new autotry session with the link partner. To do 549 * so, we set the speed then disable and re-enable the tx laser, to 550 * alert the link partner that it also needs to restart autotry on its 551 * end. This is consistent with TRUE clause 37 autoneg, which also 552 * involves a loss of signal. 553 **/ 554 void ixgbe_flap_tx_laser_multispeed_fiber(struct ixgbe_hw *hw) 555 { 556 DEBUGFUNC("ixgbe_flap_tx_laser_multispeed_fiber"); 557 558 if (hw->mac.autotry_restart) { 559 ixgbe_disable_tx_laser_multispeed_fiber(hw); 560 ixgbe_enable_tx_laser_multispeed_fiber(hw); 561 hw->mac.autotry_restart = FALSE; 562 } 563 } 564 565 /** 566 * ixgbe_setup_mac_link_multispeed_fiber - Set MAC link speed 567 * @hw: pointer to hardware structure 568 * @speed: new link speed 569 * @autoneg: TRUE if autonegotiation enabled 570 * @autoneg_wait_to_complete: TRUE when waiting for completion is needed 571 * 572 * Set the link speed in the AUTOC register and restarts link. 573 **/ 574 s32 ixgbe_setup_mac_link_multispeed_fiber(struct ixgbe_hw *hw, 575 ixgbe_link_speed speed, bool autoneg, 576 bool autoneg_wait_to_complete) 577 { 578 s32 status = IXGBE_SUCCESS; 579 ixgbe_link_speed link_speed = IXGBE_LINK_SPEED_UNKNOWN; 580 ixgbe_link_speed highest_link_speed = IXGBE_LINK_SPEED_UNKNOWN; 581 u32 speedcnt = 0; 582 u32 esdp_reg = IXGBE_READ_REG(hw, IXGBE_ESDP); 583 u32 i = 0; 584 bool link_up = FALSE; 585 bool negotiation; 586 587 DEBUGFUNC("ixgbe_setup_mac_link_multispeed_fiber"); 588 589 /* Mask off requested but non-supported speeds */ 590 status = ixgbe_get_link_capabilities(hw, &link_speed, &negotiation); 591 if (status != IXGBE_SUCCESS) 592 return status; 593 594 speed &= link_speed; 595 596 /* 597 * Try each speed one by one, highest priority first. We do this in 598 * software because 10gb fiber doesn't support speed autonegotiation. 599 */ 600 if (speed & IXGBE_LINK_SPEED_10GB_FULL) { 601 speedcnt++; 602 highest_link_speed = IXGBE_LINK_SPEED_10GB_FULL; 603 604 /* If we already have link at this speed, just jump out */ 605 status = ixgbe_check_link(hw, &link_speed, &link_up, FALSE); 606 if (status != IXGBE_SUCCESS) 607 return status; 608 609 if ((link_speed == IXGBE_LINK_SPEED_10GB_FULL) && link_up) 610 goto out; 611 612 /* Set the module link speed */ 613 esdp_reg |= (IXGBE_ESDP_SDP5_DIR | IXGBE_ESDP_SDP5); 614 IXGBE_WRITE_REG(hw, IXGBE_ESDP, esdp_reg); 615 IXGBE_WRITE_FLUSH(hw); 616 617 /* Allow module to change analog characteristics (1G->10G) */ 618 msec_delay(40); 619 620 status = ixgbe_setup_mac_link_82599(hw, 621 IXGBE_LINK_SPEED_10GB_FULL, 622 autoneg, 623 autoneg_wait_to_complete); 624 if (status != IXGBE_SUCCESS) 625 return status; 626 627 /* Flap the tx laser if it has not already been done */ 628 ixgbe_flap_tx_laser(hw); 629 630 /* 631 * Wait for the controller to acquire link. Per IEEE 802.3ap, 632 * Section 73.10.2, we may have to wait up to 500ms if KR is 633 * attempted. 82599 uses the same timing for 10g SFI. 634 */ 635 for (i = 0; i < 5; i++) { 636 /* Wait for the link partner to also set speed */ 637 msec_delay(100); 638 639 /* If we have link, just jump out */ 640 status = ixgbe_check_link(hw, &link_speed, 641 &link_up, FALSE); 642 if (status != IXGBE_SUCCESS) 643 return status; 644 645 if (link_up) 646 goto out; 647 } 648 } 649 650 if (speed & IXGBE_LINK_SPEED_1GB_FULL) { 651 speedcnt++; 652 if (highest_link_speed == IXGBE_LINK_SPEED_UNKNOWN) 653 highest_link_speed = IXGBE_LINK_SPEED_1GB_FULL; 654 655 /* If we already have link at this speed, just jump out */ 656 status = ixgbe_check_link(hw, &link_speed, &link_up, FALSE); 657 if (status != IXGBE_SUCCESS) 658 return status; 659 660 if ((link_speed == IXGBE_LINK_SPEED_1GB_FULL) && link_up) 661 goto out; 662 663 /* Set the module link speed */ 664 esdp_reg &= ~IXGBE_ESDP_SDP5; 665 esdp_reg |= IXGBE_ESDP_SDP5_DIR; 666 IXGBE_WRITE_REG(hw, IXGBE_ESDP, esdp_reg); 667 IXGBE_WRITE_FLUSH(hw); 668 669 /* Allow module to change analog characteristics (10G->1G) */ 670 msec_delay(40); 671 672 status = ixgbe_setup_mac_link_82599(hw, 673 IXGBE_LINK_SPEED_1GB_FULL, 674 autoneg, 675 autoneg_wait_to_complete); 676 if (status != IXGBE_SUCCESS) 677 return status; 678 679 /* Flap the tx laser if it has not already been done */ 680 ixgbe_flap_tx_laser(hw); 681 682 /* Wait for the link partner to also set speed */ 683 msec_delay(100); 684 685 /* If we have link, just jump out */ 686 status = ixgbe_check_link(hw, &link_speed, &link_up, FALSE); 687 if (status != IXGBE_SUCCESS) 688 return status; 689 690 if (link_up) 691 goto out; 692 } 693 694 /* 695 * We didn't get link. Configure back to the highest speed we tried, 696 * (if there was more than one). We call ourselves back with just the 697 * single highest speed that the user requested. 698 */ 699 if (speedcnt > 1) 700 status = ixgbe_setup_mac_link_multispeed_fiber(hw, 701 highest_link_speed, autoneg, autoneg_wait_to_complete); 702 703 out: 704 /* Set autoneg_advertised value based on input link speed */ 705 hw->phy.autoneg_advertised = 0; 706 707 if (speed & IXGBE_LINK_SPEED_10GB_FULL) 708 hw->phy.autoneg_advertised |= IXGBE_LINK_SPEED_10GB_FULL; 709 710 if (speed & IXGBE_LINK_SPEED_1GB_FULL) 711 hw->phy.autoneg_advertised |= IXGBE_LINK_SPEED_1GB_FULL; 712 713 return status; 714 } 715 716 /** 717 * ixgbe_setup_mac_link_smartspeed - Set MAC link speed using SmartSpeed 718 * @hw: pointer to hardware structure 719 * @speed: new link speed 720 * @autoneg: TRUE if autonegotiation enabled 721 * @autoneg_wait_to_complete: TRUE when waiting for completion is needed 722 * 723 * Implements the Intel SmartSpeed algorithm. 724 **/ 725 s32 ixgbe_setup_mac_link_smartspeed(struct ixgbe_hw *hw, 726 ixgbe_link_speed speed, bool autoneg, 727 bool autoneg_wait_to_complete) 728 { 729 s32 status = IXGBE_SUCCESS; 730 ixgbe_link_speed link_speed = IXGBE_LINK_SPEED_UNKNOWN; 731 s32 i, j; 732 bool link_up = FALSE; 733 u32 autoc_reg = IXGBE_READ_REG(hw, IXGBE_AUTOC); 734 735 DEBUGFUNC("ixgbe_setup_mac_link_smartspeed"); 736 737 /* Set autoneg_advertised value based on input link speed */ 738 hw->phy.autoneg_advertised = 0; 739 740 if (speed & IXGBE_LINK_SPEED_10GB_FULL) 741 hw->phy.autoneg_advertised |= IXGBE_LINK_SPEED_10GB_FULL; 742 743 if (speed & IXGBE_LINK_SPEED_1GB_FULL) 744 hw->phy.autoneg_advertised |= IXGBE_LINK_SPEED_1GB_FULL; 745 746 if (speed & IXGBE_LINK_SPEED_100_FULL) 747 hw->phy.autoneg_advertised |= IXGBE_LINK_SPEED_100_FULL; 748 749 /* 750 * Implement Intel SmartSpeed algorithm. SmartSpeed will reduce the 751 * autoneg advertisement if link is unable to be established at the 752 * highest negotiated rate. This can sometimes happen due to integrity 753 * issues with the physical media connection. 754 */ 755 756 /* First, try to get link with full advertisement */ 757 hw->phy.smart_speed_active = FALSE; 758 for (j = 0; j < IXGBE_SMARTSPEED_MAX_RETRIES; j++) { 759 status = ixgbe_setup_mac_link_82599(hw, speed, autoneg, 760 autoneg_wait_to_complete); 761 if (status != IXGBE_SUCCESS) 762 goto out; 763 764 /* 765 * Wait for the controller to acquire link. Per IEEE 802.3ap, 766 * Section 73.10.2, we may have to wait up to 500ms if KR is 767 * attempted, or 200ms if KX/KX4/BX/BX4 is attempted, per 768 * Table 9 in the AN MAS. 769 */ 770 for (i = 0; i < 5; i++) { 771 msec_delay(100); 772 773 /* If we have link, just jump out */ 774 status = ixgbe_check_link(hw, &link_speed, &link_up, 775 FALSE); 776 if (status != IXGBE_SUCCESS) 777 goto out; 778 779 if (link_up) 780 goto out; 781 } 782 } 783 784 /* 785 * We didn't get link. If we advertised KR plus one of KX4/KX 786 * (or BX4/BX), then disable KR and try again. 787 */ 788 if (((autoc_reg & IXGBE_AUTOC_KR_SUPP) == 0) || 789 ((autoc_reg & IXGBE_AUTOC_KX4_KX_SUPP_MASK) == 0)) 790 goto out; 791 792 /* Turn SmartSpeed on to disable KR support */ 793 hw->phy.smart_speed_active = TRUE; 794 status = ixgbe_setup_mac_link_82599(hw, speed, autoneg, 795 autoneg_wait_to_complete); 796 if (status != IXGBE_SUCCESS) 797 goto out; 798 799 /* 800 * Wait for the controller to acquire link. 600ms will allow for 801 * the AN link_fail_inhibit_timer as well for multiple cycles of 802 * parallel detect, both 10g and 1g. This allows for the maximum 803 * connect attempts as defined in the AN MAS table 73-7. 804 */ 805 for (i = 0; i < 6; i++) { 806 msec_delay(100); 807 808 /* If we have link, just jump out */ 809 status = ixgbe_check_link(hw, &link_speed, &link_up, FALSE); 810 if (status != IXGBE_SUCCESS) 811 goto out; 812 813 if (link_up) 814 goto out; 815 } 816 817 /* We didn't get link. Turn SmartSpeed back off. */ 818 hw->phy.smart_speed_active = FALSE; 819 status = ixgbe_setup_mac_link_82599(hw, speed, autoneg, 820 autoneg_wait_to_complete); 821 822 out: 823 if (link_up && (link_speed == IXGBE_LINK_SPEED_1GB_FULL)) 824 DEBUGOUT("Smartspeed has downgraded the link speed " 825 "from the maximum advertised\n"); 826 return status; 827 } 828 829 /** 830 * ixgbe_setup_mac_link_82599 - Set MAC link speed 831 * @hw: pointer to hardware structure 832 * @speed: new link speed 833 * @autoneg: TRUE if autonegotiation enabled 834 * @autoneg_wait_to_complete: TRUE when waiting for completion is needed 835 * 836 * Set the link speed in the AUTOC register and restarts link. 837 **/ 838 s32 ixgbe_setup_mac_link_82599(struct ixgbe_hw *hw, 839 ixgbe_link_speed speed, bool autoneg, 840 bool autoneg_wait_to_complete) 841 { 842 s32 status = IXGBE_SUCCESS; 843 u32 autoc = IXGBE_READ_REG(hw, IXGBE_AUTOC); 844 u32 autoc2 = IXGBE_READ_REG(hw, IXGBE_AUTOC2); 845 u32 start_autoc = autoc; 846 u32 orig_autoc = 0; 847 u32 link_mode = autoc & IXGBE_AUTOC_LMS_MASK; 848 u32 pma_pmd_1g = autoc & IXGBE_AUTOC_1G_PMA_PMD_MASK; 849 u32 pma_pmd_10g_serial = autoc2 & IXGBE_AUTOC2_10G_SERIAL_PMA_PMD_MASK; 850 u32 links_reg; 851 u32 i; 852 ixgbe_link_speed link_capabilities = IXGBE_LINK_SPEED_UNKNOWN; 853 854 DEBUGFUNC("ixgbe_setup_mac_link_82599"); 855 856 /* Check to see if speed passed in is supported. */ 857 status = ixgbe_get_link_capabilities(hw, &link_capabilities, &autoneg); 858 if (status != IXGBE_SUCCESS) 859 goto out; 860 861 speed &= link_capabilities; 862 863 if (speed == IXGBE_LINK_SPEED_UNKNOWN) { 864 status = IXGBE_ERR_LINK_SETUP; 865 goto out; 866 } 867 868 /* Use stored value (EEPROM defaults) of AUTOC to find KR/KX4 support*/ 869 if (hw->mac.orig_link_settings_stored) 870 orig_autoc = hw->mac.orig_autoc; 871 else 872 orig_autoc = autoc; 873 874 if (link_mode == IXGBE_AUTOC_LMS_KX4_KX_KR || 875 link_mode == IXGBE_AUTOC_LMS_KX4_KX_KR_1G_AN || 876 link_mode == IXGBE_AUTOC_LMS_KX4_KX_KR_SGMII) { 877 /* Set KX4/KX/KR support according to speed requested */ 878 autoc &= ~(IXGBE_AUTOC_KX4_KX_SUPP_MASK | IXGBE_AUTOC_KR_SUPP); 879 if (speed & IXGBE_LINK_SPEED_10GB_FULL) 880 if (orig_autoc & IXGBE_AUTOC_KX4_SUPP) 881 autoc |= IXGBE_AUTOC_KX4_SUPP; 882 if ((orig_autoc & IXGBE_AUTOC_KR_SUPP) && 883 (hw->phy.smart_speed_active == FALSE)) 884 autoc |= IXGBE_AUTOC_KR_SUPP; 885 if (speed & IXGBE_LINK_SPEED_1GB_FULL) 886 autoc |= IXGBE_AUTOC_KX_SUPP; 887 } else if ((pma_pmd_1g == IXGBE_AUTOC_1G_SFI) && 888 (link_mode == IXGBE_AUTOC_LMS_1G_LINK_NO_AN || 889 link_mode == IXGBE_AUTOC_LMS_1G_AN)) { 890 /* Switch from 1G SFI to 10G SFI if requested */ 891 if ((speed == IXGBE_LINK_SPEED_10GB_FULL) && 892 (pma_pmd_10g_serial == IXGBE_AUTOC2_10G_SFI)) { 893 autoc &= ~IXGBE_AUTOC_LMS_MASK; 894 autoc |= IXGBE_AUTOC_LMS_10G_SERIAL; 895 } 896 } else if ((pma_pmd_10g_serial == IXGBE_AUTOC2_10G_SFI) && 897 (link_mode == IXGBE_AUTOC_LMS_10G_SERIAL)) { 898 /* Switch from 10G SFI to 1G SFI if requested */ 899 if ((speed == IXGBE_LINK_SPEED_1GB_FULL) && 900 (pma_pmd_1g == IXGBE_AUTOC_1G_SFI)) { 901 autoc &= ~IXGBE_AUTOC_LMS_MASK; 902 if (autoneg) 903 autoc |= IXGBE_AUTOC_LMS_1G_AN; 904 else 905 autoc |= IXGBE_AUTOC_LMS_1G_LINK_NO_AN; 906 } 907 } 908 909 if (autoc != start_autoc) { 910 /* Restart link */ 911 autoc |= IXGBE_AUTOC_AN_RESTART; 912 IXGBE_WRITE_REG(hw, IXGBE_AUTOC, autoc); 913 914 /* Only poll for autoneg to complete if specified to do so */ 915 if (autoneg_wait_to_complete) { 916 if (link_mode == IXGBE_AUTOC_LMS_KX4_KX_KR || 917 link_mode == IXGBE_AUTOC_LMS_KX4_KX_KR_1G_AN || 918 link_mode == IXGBE_AUTOC_LMS_KX4_KX_KR_SGMII) { 919 links_reg = 0; /*Just in case Autoneg time=0*/ 920 for (i = 0; i < IXGBE_AUTO_NEG_TIME; i++) { 921 links_reg = 922 IXGBE_READ_REG(hw, IXGBE_LINKS); 923 if (links_reg & IXGBE_LINKS_KX_AN_COMP) 924 break; 925 msec_delay(100); 926 } 927 if (!(links_reg & IXGBE_LINKS_KX_AN_COMP)) { 928 status = 929 IXGBE_ERR_AUTONEG_NOT_COMPLETE; 930 DEBUGOUT("Autoneg did not complete.\n"); 931 } 932 } 933 } 934 935 /* Add delay to filter out noises during initial link setup */ 936 msec_delay(50); 937 } 938 939 out: 940 return status; 941 } 942 943 /** 944 * ixgbe_setup_copper_link_82599 - Set the PHY autoneg advertised field 945 * @hw: pointer to hardware structure 946 * @speed: new link speed 947 * @autoneg: TRUE if autonegotiation enabled 948 * @autoneg_wait_to_complete: TRUE if waiting is needed to complete 949 * 950 * Restarts link on PHY and MAC based on settings passed in. 951 **/ 952 static s32 ixgbe_setup_copper_link_82599(struct ixgbe_hw *hw, 953 ixgbe_link_speed speed, 954 bool autoneg, 955 bool autoneg_wait_to_complete) 956 { 957 s32 status; 958 959 DEBUGFUNC("ixgbe_setup_copper_link_82599"); 960 961 /* Setup the PHY according to input speed */ 962 status = hw->phy.ops.setup_link_speed(hw, speed, autoneg, 963 autoneg_wait_to_complete); 964 /* Set up MAC */ 965 ixgbe_start_mac_link_82599(hw, autoneg_wait_to_complete); 966 967 return status; 968 } 969 970 /** 971 * ixgbe_reset_hw_82599 - Perform hardware reset 972 * @hw: pointer to hardware structure 973 * 974 * Resets the hardware by resetting the transmit and receive units, masks 975 * and clears all interrupts, perform a PHY reset, and perform a link (MAC) 976 * reset. 977 **/ 978 s32 ixgbe_reset_hw_82599(struct ixgbe_hw *hw) 979 { 980 s32 status = IXGBE_SUCCESS; 981 u32 ctrl; 982 u32 i; 983 u32 autoc; 984 u32 autoc2; 985 986 DEBUGFUNC("ixgbe_reset_hw_82599"); 987 988 /* Call adapter stop to disable tx/rx and clear interrupts */ 989 hw->mac.ops.stop_adapter(hw); 990 991 /* PHY ops must be identified and initialized prior to reset */ 992 993 /* Identify PHY and related function pointers */ 994 status = hw->phy.ops.init(hw); 995 996 if (status == IXGBE_ERR_SFP_NOT_SUPPORTED) 997 goto reset_hw_out; 998 999 /* Setup SFP module if there is one present. */ 1000 if (hw->phy.sfp_setup_needed) { 1001 status = hw->mac.ops.setup_sfp(hw); 1002 hw->phy.sfp_setup_needed = FALSE; 1003 } 1004 1005 if (status == IXGBE_ERR_SFP_NOT_SUPPORTED) 1006 goto reset_hw_out; 1007 1008 /* Reset PHY */ 1009 if (hw->phy.reset_disable == FALSE && hw->phy.ops.reset != NULL) 1010 hw->phy.ops.reset(hw); 1011 1012 /* 1013 * Prevent the PCI-E bus from from hanging by disabling PCI-E master 1014 * access and verify no pending requests before reset 1015 */ 1016 ixgbe_disable_pcie_master(hw); 1017 1018 mac_reset_top: 1019 /* 1020 * Issue global reset to the MAC. This needs to be a SW reset. 1021 * If link reset is used, it might reset the MAC when mng is using it 1022 */ 1023 ctrl = IXGBE_READ_REG(hw, IXGBE_CTRL); 1024 IXGBE_WRITE_REG(hw, IXGBE_CTRL, (ctrl | IXGBE_CTRL_RST)); 1025 IXGBE_WRITE_FLUSH(hw); 1026 1027 /* Poll for reset bit to self-clear indicating reset is complete */ 1028 for (i = 0; i < 10; i++) { 1029 usec_delay(1); 1030 ctrl = IXGBE_READ_REG(hw, IXGBE_CTRL); 1031 if (!(ctrl & IXGBE_CTRL_RST)) 1032 break; 1033 } 1034 if (ctrl & IXGBE_CTRL_RST) { 1035 status = IXGBE_ERR_RESET_FAILED; 1036 DEBUGOUT("Reset polling failed to complete.\n"); 1037 } 1038 1039 /* 1040 * Double resets are required for recovery from certain error 1041 * conditions. Between resets, it is necessary to stall to allow time 1042 * for any pending HW events to complete. We use 1usec since that is 1043 * what is needed for ixgbe_disable_pcie_master(). The second reset 1044 * then clears out any effects of those events. 1045 */ 1046 if (hw->mac.flags & IXGBE_FLAGS_DOUBLE_RESET_REQUIRED) { 1047 hw->mac.flags &= ~IXGBE_FLAGS_DOUBLE_RESET_REQUIRED; 1048 usec_delay(1); 1049 goto mac_reset_top; 1050 } 1051 1052 msec_delay(50); 1053 1054 /* 1055 * Store the original AUTOC/AUTOC2 values if they have not been 1056 * stored off yet. Otherwise restore the stored original 1057 * values since the reset operation sets back to defaults. 1058 */ 1059 autoc = IXGBE_READ_REG(hw, IXGBE_AUTOC); 1060 autoc2 = IXGBE_READ_REG(hw, IXGBE_AUTOC2); 1061 if (hw->mac.orig_link_settings_stored == FALSE) { 1062 hw->mac.orig_autoc = autoc; 1063 hw->mac.orig_autoc2 = autoc2; 1064 hw->mac.orig_link_settings_stored = TRUE; 1065 } else { 1066 if (autoc != hw->mac.orig_autoc) 1067 IXGBE_WRITE_REG(hw, IXGBE_AUTOC, (hw->mac.orig_autoc | 1068 IXGBE_AUTOC_AN_RESTART)); 1069 1070 if ((autoc2 & IXGBE_AUTOC2_UPPER_MASK) != 1071 (hw->mac.orig_autoc2 & IXGBE_AUTOC2_UPPER_MASK)) { 1072 autoc2 &= ~IXGBE_AUTOC2_UPPER_MASK; 1073 autoc2 |= (hw->mac.orig_autoc2 & 1074 IXGBE_AUTOC2_UPPER_MASK); 1075 IXGBE_WRITE_REG(hw, IXGBE_AUTOC2, autoc2); 1076 } 1077 } 1078 1079 /* Store the permanent mac address */ 1080 hw->mac.ops.get_mac_addr(hw, hw->mac.perm_addr); 1081 1082 /* 1083 * Store MAC address from RAR0, clear receive address registers, and 1084 * clear the multicast table. Also reset num_rar_entries to 128, 1085 * since we modify this value when programming the SAN MAC address. 1086 */ 1087 hw->mac.num_rar_entries = 128; 1088 hw->mac.ops.init_rx_addrs(hw); 1089 1090 /* Store the permanent SAN mac address */ 1091 hw->mac.ops.get_san_mac_addr(hw, hw->mac.san_addr); 1092 1093 /* Add the SAN MAC address to the RAR only if it's a valid address */ 1094 if (ixgbe_validate_mac_addr(hw->mac.san_addr) == 0) { 1095 hw->mac.ops.set_rar(hw, hw->mac.num_rar_entries - 1, 1096 hw->mac.san_addr, 0, IXGBE_RAH_AV); 1097 1098 /* Reserve the last RAR for the SAN MAC address */ 1099 hw->mac.num_rar_entries--; 1100 } 1101 1102 /* Store the alternative WWNN/WWPN prefix */ 1103 hw->mac.ops.get_wwn_prefix(hw, &hw->mac.wwnn_prefix, 1104 &hw->mac.wwpn_prefix); 1105 1106 reset_hw_out: 1107 return status; 1108 } 1109 1110 /** 1111 * ixgbe_reinit_fdir_tables_82599 - Reinitialize Flow Director tables. 1112 * @hw: pointer to hardware structure 1113 **/ 1114 s32 ixgbe_reinit_fdir_tables_82599(struct ixgbe_hw *hw) 1115 { 1116 int i; 1117 u32 fdirctrl = IXGBE_READ_REG(hw, IXGBE_FDIRCTRL); 1118 fdirctrl &= ~IXGBE_FDIRCTRL_INIT_DONE; 1119 1120 DEBUGFUNC("ixgbe_reinit_fdir_tables_82599"); 1121 1122 /* 1123 * Before starting reinitialization process, 1124 * FDIRCMD.CMD must be zero. 1125 */ 1126 for (i = 0; i < IXGBE_FDIRCMD_CMD_POLL; i++) { 1127 if (!(IXGBE_READ_REG(hw, IXGBE_FDIRCMD) & 1128 IXGBE_FDIRCMD_CMD_MASK)) 1129 break; 1130 usec_delay(10); 1131 } 1132 if (i >= IXGBE_FDIRCMD_CMD_POLL) { 1133 DEBUGOUT("Flow Director previous command isn't complete, " 1134 "aborting table re-initialization. \n"); 1135 return IXGBE_ERR_FDIR_REINIT_FAILED; 1136 } 1137 1138 IXGBE_WRITE_REG(hw, IXGBE_FDIRFREE, 0); 1139 IXGBE_WRITE_FLUSH(hw); 1140 /* 1141 * 82599 adapters flow director init flow cannot be restarted, 1142 * Workaround 82599 silicon errata by performing the following steps 1143 * before re-writing the FDIRCTRL control register with the same value. 1144 * - write 1 to bit 8 of FDIRCMD register & 1145 * - write 0 to bit 8 of FDIRCMD register 1146 */ 1147 IXGBE_WRITE_REG(hw, IXGBE_FDIRCMD, 1148 (IXGBE_READ_REG(hw, IXGBE_FDIRCMD) | 1149 IXGBE_FDIRCMD_CLEARHT)); 1150 IXGBE_WRITE_FLUSH(hw); 1151 IXGBE_WRITE_REG(hw, IXGBE_FDIRCMD, 1152 (IXGBE_READ_REG(hw, IXGBE_FDIRCMD) & 1153 ~IXGBE_FDIRCMD_CLEARHT)); 1154 IXGBE_WRITE_FLUSH(hw); 1155 /* 1156 * Clear FDIR Hash register to clear any leftover hashes 1157 * waiting to be programmed. 1158 */ 1159 IXGBE_WRITE_REG(hw, IXGBE_FDIRHASH, 0x00); 1160 IXGBE_WRITE_FLUSH(hw); 1161 1162 IXGBE_WRITE_REG(hw, IXGBE_FDIRCTRL, fdirctrl); 1163 IXGBE_WRITE_FLUSH(hw); 1164 1165 /* Poll init-done after we write FDIRCTRL register */ 1166 for (i = 0; i < IXGBE_FDIR_INIT_DONE_POLL; i++) { 1167 if (IXGBE_READ_REG(hw, IXGBE_FDIRCTRL) & 1168 IXGBE_FDIRCTRL_INIT_DONE) 1169 break; 1170 usec_delay(10); 1171 } 1172 if (i >= IXGBE_FDIR_INIT_DONE_POLL) { 1173 DEBUGOUT("Flow Director Signature poll time exceeded!\n"); 1174 return IXGBE_ERR_FDIR_REINIT_FAILED; 1175 } 1176 1177 /* Clear FDIR statistics registers (read to clear) */ 1178 IXGBE_READ_REG(hw, IXGBE_FDIRUSTAT); 1179 IXGBE_READ_REG(hw, IXGBE_FDIRFSTAT); 1180 IXGBE_READ_REG(hw, IXGBE_FDIRMATCH); 1181 IXGBE_READ_REG(hw, IXGBE_FDIRMISS); 1182 IXGBE_READ_REG(hw, IXGBE_FDIRLEN); 1183 1184 return IXGBE_SUCCESS; 1185 } 1186 1187 /** 1188 * ixgbe_init_fdir_signature_82599 - Initialize Flow Director signature filters 1189 * @hw: pointer to hardware structure 1190 * @pballoc: which mode to allocate filters with 1191 **/ 1192 s32 ixgbe_init_fdir_signature_82599(struct ixgbe_hw *hw, u32 pballoc) 1193 { 1194 u32 fdirctrl = 0; 1195 u32 pbsize; 1196 int i; 1197 1198 DEBUGFUNC("ixgbe_init_fdir_signature_82599"); 1199 1200 /* 1201 * Before enabling Flow Director, the Rx Packet Buffer size 1202 * must be reduced. The new value is the current size minus 1203 * flow director memory usage size. 1204 */ 1205 pbsize = (1 << (IXGBE_FDIR_PBALLOC_SIZE_SHIFT + pballoc)); 1206 IXGBE_WRITE_REG(hw, IXGBE_RXPBSIZE(0), 1207 (IXGBE_READ_REG(hw, IXGBE_RXPBSIZE(0)) - pbsize)); 1208 1209 /* 1210 * The defaults in the HW for RX PB 1-7 are not zero and so should be 1211 * intialized to zero for non DCB mode otherwise actual total RX PB 1212 * would be bigger than programmed and filter space would run into 1213 * the PB 0 region. 1214 */ 1215 for (i = 1; i < 8; i++) 1216 IXGBE_WRITE_REG(hw, IXGBE_RXPBSIZE(i), 0); 1217 1218 /* Send interrupt when 64 filters are left */ 1219 fdirctrl |= 4 << IXGBE_FDIRCTRL_FULL_THRESH_SHIFT; 1220 1221 /* Set the maximum length per hash bucket to 0xA filters */ 1222 fdirctrl |= 0xA << IXGBE_FDIRCTRL_MAX_LENGTH_SHIFT; 1223 1224 switch (pballoc) { 1225 case IXGBE_FDIR_PBALLOC_64K: 1226 /* 8k - 1 signature filters */ 1227 fdirctrl |= IXGBE_FDIRCTRL_PBALLOC_64K; 1228 break; 1229 case IXGBE_FDIR_PBALLOC_128K: 1230 /* 16k - 1 signature filters */ 1231 fdirctrl |= IXGBE_FDIRCTRL_PBALLOC_128K; 1232 break; 1233 case IXGBE_FDIR_PBALLOC_256K: 1234 /* 32k - 1 signature filters */ 1235 fdirctrl |= IXGBE_FDIRCTRL_PBALLOC_256K; 1236 break; 1237 default: 1238 /* bad value */ 1239 return IXGBE_ERR_CONFIG; 1240 }; 1241 1242 /* Move the flexible bytes to use the ethertype - shift 6 words */ 1243 fdirctrl |= (0x6 << IXGBE_FDIRCTRL_FLEX_SHIFT); 1244 1245 1246 /* Prime the keys for hashing */ 1247 IXGBE_WRITE_REG(hw, IXGBE_FDIRHKEY, IXGBE_ATR_BUCKET_HASH_KEY); 1248 IXGBE_WRITE_REG(hw, IXGBE_FDIRSKEY, IXGBE_ATR_SIGNATURE_HASH_KEY); 1249 1250 /* 1251 * Poll init-done after we write the register. Estimated times: 1252 * 10G: PBALLOC = 11b, timing is 60us 1253 * 1G: PBALLOC = 11b, timing is 600us 1254 * 100M: PBALLOC = 11b, timing is 6ms 1255 * 1256 * Multiple these timings by 4 if under full Rx load 1257 * 1258 * So we'll poll for IXGBE_FDIR_INIT_DONE_POLL times, sleeping for 1259 * 1 msec per poll time. If we're at line rate and drop to 100M, then 1260 * this might not finish in our poll time, but we can live with that 1261 * for now. 1262 */ 1263 IXGBE_WRITE_REG(hw, IXGBE_FDIRCTRL, fdirctrl); 1264 IXGBE_WRITE_FLUSH(hw); 1265 for (i = 0; i < IXGBE_FDIR_INIT_DONE_POLL; i++) { 1266 if (IXGBE_READ_REG(hw, IXGBE_FDIRCTRL) & 1267 IXGBE_FDIRCTRL_INIT_DONE) 1268 break; 1269 msec_delay(1); 1270 } 1271 if (i >= IXGBE_FDIR_INIT_DONE_POLL) 1272 DEBUGOUT("Flow Director Signature poll time exceeded!\n"); 1273 1274 return IXGBE_SUCCESS; 1275 } 1276 1277 /** 1278 * ixgbe_init_fdir_perfect_82599 - Initialize Flow Director perfect filters 1279 * @hw: pointer to hardware structure 1280 * @pballoc: which mode to allocate filters with 1281 **/ 1282 s32 ixgbe_init_fdir_perfect_82599(struct ixgbe_hw *hw, u32 pballoc) 1283 { 1284 u32 fdirctrl = 0; 1285 u32 pbsize; 1286 int i; 1287 1288 DEBUGFUNC("ixgbe_init_fdir_perfect_82599"); 1289 1290 /* 1291 * Before enabling Flow Director, the Rx Packet Buffer size 1292 * must be reduced. The new value is the current size minus 1293 * flow director memory usage size. 1294 */ 1295 pbsize = (1 << (IXGBE_FDIR_PBALLOC_SIZE_SHIFT + pballoc)); 1296 IXGBE_WRITE_REG(hw, IXGBE_RXPBSIZE(0), 1297 (IXGBE_READ_REG(hw, IXGBE_RXPBSIZE(0)) - pbsize)); 1298 1299 /* 1300 * The defaults in the HW for RX PB 1-7 are not zero and so should be 1301 * intialized to zero for non DCB mode otherwise actual total RX PB 1302 * would be bigger than programmed and filter space would run into 1303 * the PB 0 region. 1304 */ 1305 for (i = 1; i < 8; i++) 1306 IXGBE_WRITE_REG(hw, IXGBE_RXPBSIZE(i), 0); 1307 1308 /* Send interrupt when 64 filters are left */ 1309 fdirctrl |= 4 << IXGBE_FDIRCTRL_FULL_THRESH_SHIFT; 1310 1311 /* Initialize the drop queue to Rx queue 127 */ 1312 fdirctrl |= (127 << IXGBE_FDIRCTRL_DROP_Q_SHIFT); 1313 1314 switch (pballoc) { 1315 case IXGBE_FDIR_PBALLOC_64K: 1316 /* 2k - 1 perfect filters */ 1317 fdirctrl |= IXGBE_FDIRCTRL_PBALLOC_64K; 1318 break; 1319 case IXGBE_FDIR_PBALLOC_128K: 1320 /* 4k - 1 perfect filters */ 1321 fdirctrl |= IXGBE_FDIRCTRL_PBALLOC_128K; 1322 break; 1323 case IXGBE_FDIR_PBALLOC_256K: 1324 /* 8k - 1 perfect filters */ 1325 fdirctrl |= IXGBE_FDIRCTRL_PBALLOC_256K; 1326 break; 1327 default: 1328 /* bad value */ 1329 return IXGBE_ERR_CONFIG; 1330 }; 1331 1332 /* Turn perfect match filtering on */ 1333 fdirctrl |= IXGBE_FDIRCTRL_PERFECT_MATCH; 1334 fdirctrl |= IXGBE_FDIRCTRL_REPORT_STATUS; 1335 1336 /* Move the flexible bytes to use the ethertype - shift 6 words */ 1337 fdirctrl |= (0x6 << IXGBE_FDIRCTRL_FLEX_SHIFT); 1338 1339 /* Prime the keys for hashing */ 1340 IXGBE_WRITE_REG(hw, IXGBE_FDIRHKEY, IXGBE_ATR_BUCKET_HASH_KEY); 1341 IXGBE_WRITE_REG(hw, IXGBE_FDIRSKEY,IXGBE_ATR_SIGNATURE_HASH_KEY); 1342 1343 /* 1344 * Poll init-done after we write the register. Estimated times: 1345 * 10G: PBALLOC = 11b, timing is 60us 1346 * 1G: PBALLOC = 11b, timing is 600us 1347 * 100M: PBALLOC = 11b, timing is 6ms 1348 * 1349 * Multiple these timings by 4 if under full Rx load 1350 * 1351 * So we'll poll for IXGBE_FDIR_INIT_DONE_POLL times, sleeping for 1352 * 1 msec per poll time. If we're at line rate and drop to 100M, then 1353 * this might not finish in our poll time, but we can live with that 1354 * for now. 1355 */ 1356 1357 /* Set the maximum length per hash bucket to 0xA filters */ 1358 fdirctrl |= (0xA << IXGBE_FDIRCTRL_MAX_LENGTH_SHIFT); 1359 1360 IXGBE_WRITE_REG(hw, IXGBE_FDIRCTRL, fdirctrl); 1361 IXGBE_WRITE_FLUSH(hw); 1362 for (i = 0; i < IXGBE_FDIR_INIT_DONE_POLL; i++) { 1363 if (IXGBE_READ_REG(hw, IXGBE_FDIRCTRL) & 1364 IXGBE_FDIRCTRL_INIT_DONE) 1365 break; 1366 msec_delay(1); 1367 } 1368 if (i >= IXGBE_FDIR_INIT_DONE_POLL) 1369 DEBUGOUT("Flow Director Perfect poll time exceeded!\n"); 1370 1371 return IXGBE_SUCCESS; 1372 } 1373 1374 /** 1375 * ixgbe_atr_compute_hash_82599 - Compute the hashes for SW ATR 1376 * @stream: input bitstream to compute the hash on 1377 * @key: 32-bit hash key 1378 **/ 1379 u32 ixgbe_atr_compute_hash_82599(union ixgbe_atr_input *atr_input, 1380 u32 key) 1381 { 1382 /* 1383 * The algorithm is as follows: 1384 * Hash[15:0] = Sum { S[n] x K[n+16] }, n = 0...350 1385 * where Sum {A[n]}, n = 0...n is bitwise XOR of A[0], A[1]...A[n] 1386 * and A[n] x B[n] is bitwise AND between same length strings 1387 * 1388 * K[n] is 16 bits, defined as: 1389 * for n modulo 32 >= 15, K[n] = K[n % 32 : (n % 32) - 15] 1390 * for n modulo 32 < 15, K[n] = 1391 * K[(n % 32:0) | (31:31 - (14 - (n % 32)))] 1392 * 1393 * S[n] is 16 bits, defined as: 1394 * for n >= 15, S[n] = S[n:n - 15] 1395 * for n < 15, S[n] = S[(n:0) | (350:350 - (14 - n))] 1396 * 1397 * To simplify for programming, the algorithm is implemented 1398 * in software this way: 1399 * 1400 * key[31:0], hi_hash_dword[31:0], lo_hash_dword[31:0], hash[15:0] 1401 * 1402 * for (i = 0; i < 352; i+=32) 1403 * hi_hash_dword[31:0] ^= Stream[(i+31):i]; 1404 * 1405 * lo_hash_dword[15:0] ^= Stream[15:0]; 1406 * lo_hash_dword[15:0] ^= hi_hash_dword[31:16]; 1407 * lo_hash_dword[31:16] ^= hi_hash_dword[15:0]; 1408 * 1409 * hi_hash_dword[31:0] ^= Stream[351:320]; 1410 * 1411 * if(key[0]) 1412 * hash[15:0] ^= Stream[15:0]; 1413 * 1414 * for (i = 0; i < 16; i++) { 1415 * if (key[i]) 1416 * hash[15:0] ^= lo_hash_dword[(i+15):i]; 1417 * if (key[i + 16]) 1418 * hash[15:0] ^= hi_hash_dword[(i+15):i]; 1419 * } 1420 * 1421 */ 1422 __be32 common_hash_dword = 0; 1423 u32 hi_hash_dword, lo_hash_dword, flow_vm_vlan; 1424 u32 hash_result = 0; 1425 u8 i; 1426 1427 /* record the flow_vm_vlan bits as they are a key part to the hash */ 1428 flow_vm_vlan = IXGBE_NTOHL(atr_input->dword_stream[0]); 1429 1430 /* generate common hash dword */ 1431 for (i = 10; i; i -= 2) 1432 common_hash_dword ^= atr_input->dword_stream[i] ^ 1433 atr_input->dword_stream[i - 1]; 1434 1435 hi_hash_dword = IXGBE_NTOHL(common_hash_dword); 1436 1437 /* low dword is word swapped version of common */ 1438 lo_hash_dword = (hi_hash_dword >> 16) | (hi_hash_dword << 16); 1439 1440 /* apply flow ID/VM pool/VLAN ID bits to hash words */ 1441 hi_hash_dword ^= flow_vm_vlan ^ (flow_vm_vlan >> 16); 1442 1443 /* Process bits 0 and 16 */ 1444 if (key & 0x0001) hash_result ^= lo_hash_dword; 1445 if (key & 0x00010000) hash_result ^= hi_hash_dword; 1446 1447 /* 1448 * apply flow ID/VM pool/VLAN ID bits to lo hash dword, we had to 1449 * delay this because bit 0 of the stream should not be processed 1450 * so we do not add the vlan until after bit 0 was processed 1451 */ 1452 lo_hash_dword ^= flow_vm_vlan ^ (flow_vm_vlan << 16); 1453 1454 1455 /* process the remaining 30 bits in the key 2 bits at a time */ 1456 for (i = 15; i; i-- ) { 1457 if (key & (0x0001 << i)) hash_result ^= lo_hash_dword >> i; 1458 if (key & (0x00010000 << i)) hash_result ^= hi_hash_dword >> i; 1459 } 1460 1461 return hash_result & IXGBE_ATR_HASH_MASK; 1462 } 1463 1464 /* 1465 * These defines allow us to quickly generate all of the necessary instructions 1466 * in the function below by simply calling out IXGBE_COMPUTE_SIG_HASH_ITERATION 1467 * for values 0 through 15 1468 */ 1469 #define IXGBE_ATR_COMMON_HASH_KEY \ 1470 (IXGBE_ATR_BUCKET_HASH_KEY & IXGBE_ATR_SIGNATURE_HASH_KEY) 1471 #define IXGBE_COMPUTE_SIG_HASH_ITERATION(_n) \ 1472 do { \ 1473 u32 n = (_n); \ 1474 if (IXGBE_ATR_COMMON_HASH_KEY & (0x01 << n)) \ 1475 common_hash ^= lo_hash_dword >> n; \ 1476 else if (IXGBE_ATR_BUCKET_HASH_KEY & (0x01 << n)) \ 1477 bucket_hash ^= lo_hash_dword >> n; \ 1478 else if (IXGBE_ATR_SIGNATURE_HASH_KEY & (0x01 << n)) \ 1479 sig_hash ^= lo_hash_dword << (16 - n); \ 1480 if (IXGBE_ATR_COMMON_HASH_KEY & (0x01 << (n + 16))) \ 1481 common_hash ^= hi_hash_dword >> n; \ 1482 else if (IXGBE_ATR_BUCKET_HASH_KEY & (0x01 << (n + 16))) \ 1483 bucket_hash ^= hi_hash_dword >> n; \ 1484 else if (IXGBE_ATR_SIGNATURE_HASH_KEY & (0x01 << (n + 16))) \ 1485 sig_hash ^= hi_hash_dword << (16 - n); \ 1486 } while (0); 1487 1488 /** 1489 * ixgbe_atr_compute_sig_hash_82599 - Compute the signature hash 1490 * @stream: input bitstream to compute the hash on 1491 * 1492 * This function is almost identical to the function above but contains 1493 * several optomizations such as unwinding all of the loops, letting the 1494 * compiler work out all of the conditional ifs since the keys are static 1495 * defines, and computing two keys at once since the hashed dword stream 1496 * will be the same for both keys. 1497 **/ 1498 static u32 ixgbe_atr_compute_sig_hash_82599(union ixgbe_atr_hash_dword input, 1499 union ixgbe_atr_hash_dword common) 1500 { 1501 u32 hi_hash_dword, lo_hash_dword, flow_vm_vlan; 1502 u32 sig_hash = 0, bucket_hash = 0, common_hash = 0; 1503 1504 /* record the flow_vm_vlan bits as they are a key part to the hash */ 1505 flow_vm_vlan = IXGBE_NTOHL(input.dword); 1506 1507 /* generate common hash dword */ 1508 hi_hash_dword = IXGBE_NTOHL(common.dword); 1509 1510 /* low dword is word swapped version of common */ 1511 lo_hash_dword = (hi_hash_dword >> 16) | (hi_hash_dword << 16); 1512 1513 /* apply flow ID/VM pool/VLAN ID bits to hash words */ 1514 hi_hash_dword ^= flow_vm_vlan ^ (flow_vm_vlan >> 16); 1515 1516 /* Process bits 0 and 16 */ 1517 IXGBE_COMPUTE_SIG_HASH_ITERATION(0); 1518 1519 /* 1520 * apply flow ID/VM pool/VLAN ID bits to lo hash dword, we had to 1521 * delay this because bit 0 of the stream should not be processed 1522 * so we do not add the vlan until after bit 0 was processed 1523 */ 1524 lo_hash_dword ^= flow_vm_vlan ^ (flow_vm_vlan << 16); 1525 1526 /* Process remaining 30 bit of the key */ 1527 IXGBE_COMPUTE_SIG_HASH_ITERATION(1); 1528 IXGBE_COMPUTE_SIG_HASH_ITERATION(2); 1529 IXGBE_COMPUTE_SIG_HASH_ITERATION(3); 1530 IXGBE_COMPUTE_SIG_HASH_ITERATION(4); 1531 IXGBE_COMPUTE_SIG_HASH_ITERATION(5); 1532 IXGBE_COMPUTE_SIG_HASH_ITERATION(6); 1533 IXGBE_COMPUTE_SIG_HASH_ITERATION(7); 1534 IXGBE_COMPUTE_SIG_HASH_ITERATION(8); 1535 IXGBE_COMPUTE_SIG_HASH_ITERATION(9); 1536 IXGBE_COMPUTE_SIG_HASH_ITERATION(10); 1537 IXGBE_COMPUTE_SIG_HASH_ITERATION(11); 1538 IXGBE_COMPUTE_SIG_HASH_ITERATION(12); 1539 IXGBE_COMPUTE_SIG_HASH_ITERATION(13); 1540 IXGBE_COMPUTE_SIG_HASH_ITERATION(14); 1541 IXGBE_COMPUTE_SIG_HASH_ITERATION(15); 1542 1543 /* combine common_hash result with signature and bucket hashes */ 1544 bucket_hash ^= common_hash; 1545 bucket_hash &= IXGBE_ATR_HASH_MASK; 1546 1547 sig_hash ^= common_hash << 16; 1548 sig_hash &= IXGBE_ATR_HASH_MASK << 16; 1549 1550 /* return completed signature hash */ 1551 return sig_hash ^ bucket_hash; 1552 } 1553 1554 /** 1555 * ixgbe_atr_add_signature_filter_82599 - Adds a signature hash filter 1556 * @hw: pointer to hardware structure 1557 * @stream: input bitstream 1558 * @queue: queue index to direct traffic to 1559 **/ 1560 s32 ixgbe_fdir_add_signature_filter_82599(struct ixgbe_hw *hw, 1561 union ixgbe_atr_hash_dword input, 1562 union ixgbe_atr_hash_dword common, 1563 u8 queue) 1564 { 1565 u64 fdirhashcmd; 1566 u32 fdircmd; 1567 1568 DEBUGFUNC("ixgbe_fdir_add_signature_filter_82599"); 1569 1570 /* 1571 * Get the flow_type in order to program FDIRCMD properly 1572 * lowest 2 bits are FDIRCMD.L4TYPE, third lowest bit is FDIRCMD.IPV6 1573 */ 1574 switch (input.formatted.flow_type) { 1575 case IXGBE_ATR_FLOW_TYPE_TCPV4: 1576 case IXGBE_ATR_FLOW_TYPE_UDPV4: 1577 case IXGBE_ATR_FLOW_TYPE_SCTPV4: 1578 case IXGBE_ATR_FLOW_TYPE_TCPV6: 1579 case IXGBE_ATR_FLOW_TYPE_UDPV6: 1580 case IXGBE_ATR_FLOW_TYPE_SCTPV6: 1581 break; 1582 default: 1583 DEBUGOUT(" Error on flow type input\n"); 1584 return IXGBE_ERR_CONFIG; 1585 } 1586 1587 /* configure FDIRCMD register */ 1588 fdircmd = IXGBE_FDIRCMD_CMD_ADD_FLOW | IXGBE_FDIRCMD_FILTER_UPDATE | 1589 IXGBE_FDIRCMD_LAST | IXGBE_FDIRCMD_QUEUE_EN; 1590 fdircmd |= input.formatted.flow_type << IXGBE_FDIRCMD_FLOW_TYPE_SHIFT; 1591 fdircmd |= (u32)queue << IXGBE_FDIRCMD_RX_QUEUE_SHIFT; 1592 1593 /* 1594 * The lower 32-bits of fdirhashcmd is for FDIRHASH, the upper 32-bits 1595 * is for FDIRCMD. Then do a 64-bit register write from FDIRHASH. 1596 */ 1597 fdirhashcmd = (u64)fdircmd << 32; 1598 fdirhashcmd |= ixgbe_atr_compute_sig_hash_82599(input, common); 1599 IXGBE_WRITE_REG64(hw, IXGBE_FDIRHASH, fdirhashcmd); 1600 1601 DEBUGOUT2("Tx Queue=%x hash=%x\n", queue, (u32)fdirhashcmd); 1602 1603 return IXGBE_SUCCESS; 1604 } 1605 1606 /** 1607 * ixgbe_get_fdirtcpm_82599 - generate a tcp port from atr_input_masks 1608 * @input_mask: mask to be bit swapped 1609 * 1610 * The source and destination port masks for flow director are bit swapped 1611 * in that bit 15 effects bit 0, 14 effects 1, 13, 2 etc. In order to 1612 * generate a correctly swapped value we need to bit swap the mask and that 1613 * is what is accomplished by this function. 1614 **/ 1615 static u32 ixgbe_get_fdirtcpm_82599(struct ixgbe_atr_input_masks *input_masks) 1616 { 1617 u32 mask = IXGBE_NTOHS(input_masks->dst_port_mask); 1618 mask <<= IXGBE_FDIRTCPM_DPORTM_SHIFT; 1619 mask |= IXGBE_NTOHS(input_masks->src_port_mask); 1620 mask = ((mask & 0x55555555) << 1) | ((mask & 0xAAAAAAAA) >> 1); 1621 mask = ((mask & 0x33333333) << 2) | ((mask & 0xCCCCCCCC) >> 2); 1622 mask = ((mask & 0x0F0F0F0F) << 4) | ((mask & 0xF0F0F0F0) >> 4); 1623 return ((mask & 0x00FF00FF) << 8) | ((mask & 0xFF00FF00) >> 8); 1624 } 1625 1626 /* 1627 * These two macros are meant to address the fact that we have registers 1628 * that are either all or in part big-endian. As a result on big-endian 1629 * systems we will end up byte swapping the value to little-endian before 1630 * it is byte swapped again and written to the hardware in the original 1631 * big-endian format. 1632 */ 1633 #define IXGBE_STORE_AS_BE32(_value) \ 1634 (((u32)(_value) >> 24) | (((u32)(_value) & 0x00FF0000) >> 8) | \ 1635 (((u32)(_value) & 0x0000FF00) << 8) | ((u32)(_value) << 24)) 1636 1637 #define IXGBE_WRITE_REG_BE32(a, reg, value) \ 1638 IXGBE_WRITE_REG((a), (reg), IXGBE_STORE_AS_BE32(IXGBE_NTOHL(value))) 1639 1640 #define IXGBE_STORE_AS_BE16(_value) \ 1641 (((u16)(_value) >> 8) | ((u16)(_value) << 8)) 1642 1643 1644 /** 1645 * ixgbe_fdir_add_perfect_filter_82599 - Adds a perfect filter 1646 * @hw: pointer to hardware structure 1647 * @input: input bitstream 1648 * @input_masks: masks for the input bitstream 1649 * @soft_id: software index for the filters 1650 * @queue: queue index to direct traffic to 1651 * 1652 * Note that the caller to this function must lock before calling, since the 1653 * hardware writes must be protected from one another. 1654 **/ 1655 s32 ixgbe_fdir_add_perfect_filter_82599(struct ixgbe_hw *hw, 1656 union ixgbe_atr_input *input, 1657 struct ixgbe_atr_input_masks *input_masks, 1658 u16 soft_id, u8 queue) 1659 { 1660 u32 fdirhash; 1661 u32 fdircmd; 1662 u32 fdirport, fdirtcpm; 1663 u32 fdirvlan; 1664 /* start with VLAN, flex bytes, VM pool, and IPv6 destination masked */ 1665 u32 fdirm = IXGBE_FDIRM_VLANID | IXGBE_FDIRM_VLANP | IXGBE_FDIRM_FLEX | 1666 IXGBE_FDIRM_POOL | IXGBE_FDIRM_DIPv6; 1667 1668 DEBUGFUNC("ixgbe_fdir_add_perfect_filter_82599"); 1669 1670 /* 1671 * Check flow_type formatting, and bail out before we touch the hardware 1672 * if there's a configuration issue 1673 */ 1674 switch (input->formatted.flow_type) { 1675 case IXGBE_ATR_FLOW_TYPE_IPV4: 1676 /* use the L4 protocol mask for raw IPv4/IPv6 traffic */ 1677 fdirm |= IXGBE_FDIRM_L4P; 1678 case IXGBE_ATR_FLOW_TYPE_SCTPV4: 1679 if (input_masks->dst_port_mask || input_masks->src_port_mask) { 1680 DEBUGOUT(" Error on src/dst port mask\n"); 1681 return IXGBE_ERR_CONFIG; 1682 } 1683 case IXGBE_ATR_FLOW_TYPE_TCPV4: 1684 case IXGBE_ATR_FLOW_TYPE_UDPV4: 1685 break; 1686 default: 1687 DEBUGOUT(" Error on flow type input\n"); 1688 return IXGBE_ERR_CONFIG; 1689 } 1690 1691 /* 1692 * Program the relevant mask registers. If src/dst_port or src/dst_addr 1693 * are zero, then assume a full mask for that field. Also assume that 1694 * a VLAN of 0 is unspecified, so mask that out as well. L4type 1695 * cannot be masked out in this implementation. 1696 * 1697 * This also assumes IPv4 only. IPv6 masking isn't supported at this 1698 * point in time. 1699 */ 1700 1701 /* Program FDIRM */ 1702 switch (IXGBE_NTOHS(input_masks->vlan_id_mask) & 0xEFFF) { 1703 case 0xEFFF: 1704 /* Unmask VLAN ID - bit 0 and fall through to unmask prio */ 1705 fdirm &= ~IXGBE_FDIRM_VLANID; 1706 case 0xE000: 1707 /* Unmask VLAN prio - bit 1 */ 1708 fdirm &= ~IXGBE_FDIRM_VLANP; 1709 break; 1710 case 0x0FFF: 1711 /* Unmask VLAN ID - bit 0 */ 1712 fdirm &= ~IXGBE_FDIRM_VLANID; 1713 break; 1714 case 0x0000: 1715 /* do nothing, vlans already masked */ 1716 break; 1717 default: 1718 DEBUGOUT(" Error on VLAN mask\n"); 1719 return IXGBE_ERR_CONFIG; 1720 } 1721 1722 if (input_masks->flex_mask & 0xFFFF) { 1723 if ((input_masks->flex_mask & 0xFFFF) != 0xFFFF) { 1724 DEBUGOUT(" Error on flexible byte mask\n"); 1725 return IXGBE_ERR_CONFIG; 1726 } 1727 /* Unmask Flex Bytes - bit 4 */ 1728 fdirm &= ~IXGBE_FDIRM_FLEX; 1729 } 1730 1731 /* Now mask VM pool and destination IPv6 - bits 5 and 2 */ 1732 IXGBE_WRITE_REG(hw, IXGBE_FDIRM, fdirm); 1733 1734 /* store the TCP/UDP port masks, bit reversed from port layout */ 1735 fdirtcpm = ixgbe_get_fdirtcpm_82599(input_masks); 1736 1737 /* write both the same so that UDP and TCP use the same mask */ 1738 IXGBE_WRITE_REG(hw, IXGBE_FDIRTCPM, ~fdirtcpm); 1739 IXGBE_WRITE_REG(hw, IXGBE_FDIRUDPM, ~fdirtcpm); 1740 1741 /* store source and destination IP masks (big-enian) */ 1742 IXGBE_WRITE_REG_BE32(hw, IXGBE_FDIRSIP4M, 1743 ~input_masks->src_ip_mask[0]); 1744 IXGBE_WRITE_REG_BE32(hw, IXGBE_FDIRDIP4M, 1745 ~input_masks->dst_ip_mask[0]); 1746 1747 /* Apply masks to input data */ 1748 input->formatted.vlan_id &= input_masks->vlan_id_mask; 1749 input->formatted.flex_bytes &= input_masks->flex_mask; 1750 input->formatted.src_port &= input_masks->src_port_mask; 1751 input->formatted.dst_port &= input_masks->dst_port_mask; 1752 input->formatted.src_ip[0] &= input_masks->src_ip_mask[0]; 1753 input->formatted.dst_ip[0] &= input_masks->dst_ip_mask[0]; 1754 1755 /* record vlan (little-endian) and flex_bytes(big-endian) */ 1756 fdirvlan = 1757 IXGBE_STORE_AS_BE16(IXGBE_NTOHS(input->formatted.flex_bytes)); 1758 fdirvlan <<= IXGBE_FDIRVLAN_FLEX_SHIFT; 1759 fdirvlan |= IXGBE_NTOHS(input->formatted.vlan_id); 1760 IXGBE_WRITE_REG(hw, IXGBE_FDIRVLAN, fdirvlan); 1761 1762 /* record source and destination port (little-endian)*/ 1763 fdirport = IXGBE_NTOHS(input->formatted.dst_port); 1764 fdirport <<= IXGBE_FDIRPORT_DESTINATION_SHIFT; 1765 fdirport |= IXGBE_NTOHS(input->formatted.src_port); 1766 IXGBE_WRITE_REG(hw, IXGBE_FDIRPORT, fdirport); 1767 1768 /* record the first 32 bits of the destination address (big-endian) */ 1769 IXGBE_WRITE_REG_BE32(hw, IXGBE_FDIRIPDA, input->formatted.dst_ip[0]); 1770 1771 /* record the source address (big-endian) */ 1772 IXGBE_WRITE_REG_BE32(hw, IXGBE_FDIRIPSA, input->formatted.src_ip[0]); 1773 1774 /* configure FDIRCMD register */ 1775 fdircmd = IXGBE_FDIRCMD_CMD_ADD_FLOW | IXGBE_FDIRCMD_FILTER_UPDATE | 1776 IXGBE_FDIRCMD_LAST | IXGBE_FDIRCMD_QUEUE_EN; 1777 fdircmd |= input->formatted.flow_type << IXGBE_FDIRCMD_FLOW_TYPE_SHIFT; 1778 fdircmd |= (u32)queue << IXGBE_FDIRCMD_RX_QUEUE_SHIFT; 1779 1780 /* we only want the bucket hash so drop the upper 16 bits */ 1781 fdirhash = ixgbe_atr_compute_hash_82599(input, 1782 IXGBE_ATR_BUCKET_HASH_KEY); 1783 fdirhash |= soft_id << IXGBE_FDIRHASH_SIG_SW_INDEX_SHIFT; 1784 1785 IXGBE_WRITE_REG(hw, IXGBE_FDIRHASH, fdirhash); 1786 IXGBE_WRITE_REG(hw, IXGBE_FDIRCMD, fdircmd); 1787 1788 return IXGBE_SUCCESS; 1789 } 1790 1791 /** 1792 * ixgbe_read_analog_reg8_82599 - Reads 8 bit Omer analog register 1793 * @hw: pointer to hardware structure 1794 * @reg: analog register to read 1795 * @val: read value 1796 * 1797 * Performs read operation to Omer analog register specified. 1798 **/ 1799 s32 ixgbe_read_analog_reg8_82599(struct ixgbe_hw *hw, u32 reg, u8 *val) 1800 { 1801 u32 core_ctl; 1802 1803 DEBUGFUNC("ixgbe_read_analog_reg8_82599"); 1804 1805 IXGBE_WRITE_REG(hw, IXGBE_CORECTL, IXGBE_CORECTL_WRITE_CMD | 1806 (reg << 8)); 1807 IXGBE_WRITE_FLUSH(hw); 1808 usec_delay(10); 1809 core_ctl = IXGBE_READ_REG(hw, IXGBE_CORECTL); 1810 *val = (u8)core_ctl; 1811 1812 return IXGBE_SUCCESS; 1813 } 1814 1815 /** 1816 * ixgbe_write_analog_reg8_82599 - Writes 8 bit Omer analog register 1817 * @hw: pointer to hardware structure 1818 * @reg: atlas register to write 1819 * @val: value to write 1820 * 1821 * Performs write operation to Omer analog register specified. 1822 **/ 1823 s32 ixgbe_write_analog_reg8_82599(struct ixgbe_hw *hw, u32 reg, u8 val) 1824 { 1825 u32 core_ctl; 1826 1827 DEBUGFUNC("ixgbe_write_analog_reg8_82599"); 1828 1829 core_ctl = (reg << 8) | val; 1830 IXGBE_WRITE_REG(hw, IXGBE_CORECTL, core_ctl); 1831 IXGBE_WRITE_FLUSH(hw); 1832 usec_delay(10); 1833 1834 return IXGBE_SUCCESS; 1835 } 1836 1837 /** 1838 * ixgbe_start_hw_rev_1_82599 - Prepare hardware for Tx/Rx 1839 * @hw: pointer to hardware structure 1840 * 1841 * Starts the hardware using the generic start_hw function 1842 * and the generation start_hw function. 1843 * Then performs revision-specific operations, if any. 1844 **/ 1845 s32 ixgbe_start_hw_rev_1_82599(struct ixgbe_hw *hw) 1846 { 1847 s32 ret_val = IXGBE_SUCCESS; 1848 1849 DEBUGFUNC("ixgbe_start_hw_rev_1__82599"); 1850 1851 ret_val = ixgbe_start_hw_generic(hw); 1852 if (ret_val != IXGBE_SUCCESS) 1853 goto out; 1854 1855 ret_val = ixgbe_start_hw_gen2(hw); 1856 if (ret_val != IXGBE_SUCCESS) 1857 goto out; 1858 1859 /* We need to run link autotry after the driver loads */ 1860 hw->mac.autotry_restart = TRUE; 1861 1862 if (ret_val == IXGBE_SUCCESS) 1863 ret_val = ixgbe_verify_fw_version_82599(hw); 1864 out: 1865 return ret_val; 1866 } 1867 1868 /** 1869 * ixgbe_identify_phy_82599 - Get physical layer module 1870 * @hw: pointer to hardware structure 1871 * 1872 * Determines the physical layer module found on the current adapter. 1873 * If PHY already detected, maintains current PHY type in hw struct, 1874 * otherwise executes the PHY detection routine. 1875 **/ 1876 s32 ixgbe_identify_phy_82599(struct ixgbe_hw *hw) 1877 { 1878 s32 status = IXGBE_ERR_PHY_ADDR_INVALID; 1879 1880 DEBUGFUNC("ixgbe_identify_phy_82599"); 1881 1882 /* Detect PHY if not unknown - returns success if already detected. */ 1883 status = ixgbe_identify_phy_generic(hw); 1884 if (status != IXGBE_SUCCESS) { 1885 /* 82599 10GBASE-T requires an external PHY */ 1886 if (hw->mac.ops.get_media_type(hw) == ixgbe_media_type_copper) 1887 goto out; 1888 else 1889 status = ixgbe_identify_sfp_module_generic(hw); 1890 } 1891 1892 /* Set PHY type none if no PHY detected */ 1893 if (hw->phy.type == ixgbe_phy_unknown) { 1894 hw->phy.type = ixgbe_phy_none; 1895 status = IXGBE_SUCCESS; 1896 } 1897 1898 /* Return error if SFP module has been detected but is not supported */ 1899 if (hw->phy.type == ixgbe_phy_sfp_unsupported) 1900 status = IXGBE_ERR_SFP_NOT_SUPPORTED; 1901 1902 out: 1903 return status; 1904 } 1905 1906 /** 1907 * ixgbe_get_supported_physical_layer_82599 - Returns physical layer type 1908 * @hw: pointer to hardware structure 1909 * 1910 * Determines physical layer capabilities of the current configuration. 1911 **/ 1912 u32 ixgbe_get_supported_physical_layer_82599(struct ixgbe_hw *hw) 1913 { 1914 u32 physical_layer = IXGBE_PHYSICAL_LAYER_UNKNOWN; 1915 u32 autoc = IXGBE_READ_REG(hw, IXGBE_AUTOC); 1916 u32 autoc2 = IXGBE_READ_REG(hw, IXGBE_AUTOC2); 1917 u32 pma_pmd_10g_serial = autoc2 & IXGBE_AUTOC2_10G_SERIAL_PMA_PMD_MASK; 1918 u32 pma_pmd_10g_parallel = autoc & IXGBE_AUTOC_10G_PMA_PMD_MASK; 1919 u32 pma_pmd_1g = autoc & IXGBE_AUTOC_1G_PMA_PMD_MASK; 1920 u16 ext_ability = 0; 1921 u8 comp_codes_10g = 0; 1922 u8 comp_codes_1g = 0; 1923 1924 DEBUGFUNC("ixgbe_get_support_physical_layer_82599"); 1925 1926 hw->phy.ops.identify(hw); 1927 1928 switch (hw->phy.type) { 1929 case ixgbe_phy_tn: 1930 case ixgbe_phy_aq: 1931 case ixgbe_phy_cu_unknown: 1932 hw->phy.ops.read_reg(hw, IXGBE_MDIO_PHY_EXT_ABILITY, 1933 IXGBE_MDIO_PMA_PMD_DEV_TYPE, &ext_ability); 1934 if (ext_ability & IXGBE_MDIO_PHY_10GBASET_ABILITY) 1935 physical_layer |= IXGBE_PHYSICAL_LAYER_10GBASE_T; 1936 if (ext_ability & IXGBE_MDIO_PHY_1000BASET_ABILITY) 1937 physical_layer |= IXGBE_PHYSICAL_LAYER_1000BASE_T; 1938 if (ext_ability & IXGBE_MDIO_PHY_100BASETX_ABILITY) 1939 physical_layer |= IXGBE_PHYSICAL_LAYER_100BASE_TX; 1940 goto out; 1941 default: 1942 break; 1943 } 1944 1945 switch (autoc & IXGBE_AUTOC_LMS_MASK) { 1946 case IXGBE_AUTOC_LMS_1G_AN: 1947 case IXGBE_AUTOC_LMS_1G_LINK_NO_AN: 1948 if (pma_pmd_1g == IXGBE_AUTOC_1G_KX_BX) { 1949 physical_layer = IXGBE_PHYSICAL_LAYER_1000BASE_KX | 1950 IXGBE_PHYSICAL_LAYER_1000BASE_BX; 1951 goto out; 1952 } else 1953 /* SFI mode so read SFP module */ 1954 goto sfp_check; 1955 break; 1956 case IXGBE_AUTOC_LMS_10G_LINK_NO_AN: 1957 if (pma_pmd_10g_parallel == IXGBE_AUTOC_10G_CX4) 1958 physical_layer = IXGBE_PHYSICAL_LAYER_10GBASE_CX4; 1959 else if (pma_pmd_10g_parallel == IXGBE_AUTOC_10G_KX4) 1960 physical_layer = IXGBE_PHYSICAL_LAYER_10GBASE_KX4; 1961 else if (pma_pmd_10g_parallel == IXGBE_AUTOC_10G_XAUI) 1962 physical_layer = IXGBE_PHYSICAL_LAYER_10GBASE_XAUI; 1963 goto out; 1964 break; 1965 case IXGBE_AUTOC_LMS_10G_SERIAL: 1966 if (pma_pmd_10g_serial == IXGBE_AUTOC2_10G_KR) { 1967 physical_layer = IXGBE_PHYSICAL_LAYER_10GBASE_KR; 1968 goto out; 1969 } else if (pma_pmd_10g_serial == IXGBE_AUTOC2_10G_SFI) 1970 goto sfp_check; 1971 break; 1972 case IXGBE_AUTOC_LMS_KX4_KX_KR: 1973 case IXGBE_AUTOC_LMS_KX4_KX_KR_1G_AN: 1974 if (autoc & IXGBE_AUTOC_KX_SUPP) 1975 physical_layer |= IXGBE_PHYSICAL_LAYER_1000BASE_KX; 1976 if (autoc & IXGBE_AUTOC_KX4_SUPP) 1977 physical_layer |= IXGBE_PHYSICAL_LAYER_10GBASE_KX4; 1978 if (autoc & IXGBE_AUTOC_KR_SUPP) 1979 physical_layer |= IXGBE_PHYSICAL_LAYER_10GBASE_KR; 1980 goto out; 1981 break; 1982 default: 1983 goto out; 1984 break; 1985 } 1986 1987 sfp_check: 1988 /* SFP check must be done last since DA modules are sometimes used to 1989 * test KR mode - we need to id KR mode correctly before SFP module. 1990 * Call identify_sfp because the pluggable module may have changed */ 1991 hw->phy.ops.identify_sfp(hw); 1992 if (hw->phy.sfp_type == ixgbe_sfp_type_not_present) 1993 goto out; 1994 1995 switch (hw->phy.type) { 1996 case ixgbe_phy_sfp_passive_tyco: 1997 case ixgbe_phy_sfp_passive_unknown: 1998 physical_layer = IXGBE_PHYSICAL_LAYER_SFP_PLUS_CU; 1999 break; 2000 case ixgbe_phy_sfp_ftl_active: 2001 case ixgbe_phy_sfp_active_unknown: 2002 physical_layer = IXGBE_PHYSICAL_LAYER_SFP_ACTIVE_DA; 2003 break; 2004 case ixgbe_phy_sfp_avago: 2005 case ixgbe_phy_sfp_ftl: 2006 case ixgbe_phy_sfp_intel: 2007 case ixgbe_phy_sfp_unknown: 2008 hw->phy.ops.read_i2c_eeprom(hw, 2009 IXGBE_SFF_1GBE_COMP_CODES, &comp_codes_1g); 2010 hw->phy.ops.read_i2c_eeprom(hw, 2011 IXGBE_SFF_10GBE_COMP_CODES, &comp_codes_10g); 2012 if (comp_codes_10g & IXGBE_SFF_10GBASESR_CAPABLE) 2013 physical_layer = IXGBE_PHYSICAL_LAYER_10GBASE_SR; 2014 else if (comp_codes_10g & IXGBE_SFF_10GBASELR_CAPABLE) 2015 physical_layer = IXGBE_PHYSICAL_LAYER_10GBASE_LR; 2016 else if (comp_codes_1g & IXGBE_SFF_1GBASET_CAPABLE) 2017 physical_layer = IXGBE_PHYSICAL_LAYER_1000BASE_T; 2018 break; 2019 default: 2020 break; 2021 } 2022 2023 out: 2024 return physical_layer; 2025 } 2026 2027 /** 2028 * ixgbe_enable_rx_dma_82599 - Enable the Rx DMA unit on 82599 2029 * @hw: pointer to hardware structure 2030 * @regval: register value to write to RXCTRL 2031 * 2032 * Enables the Rx DMA unit for 82599 2033 **/ 2034 s32 ixgbe_enable_rx_dma_82599(struct ixgbe_hw *hw, u32 regval) 2035 { 2036 #define IXGBE_MAX_SECRX_POLL 30 2037 int i; 2038 int secrxreg; 2039 2040 DEBUGFUNC("ixgbe_enable_rx_dma_82599"); 2041 2042 /* 2043 * Workaround for 82599 silicon errata when enabling the Rx datapath. 2044 * If traffic is incoming before we enable the Rx unit, it could hang 2045 * the Rx DMA unit. Therefore, make sure the security engine is 2046 * completely disabled prior to enabling the Rx unit. 2047 */ 2048 secrxreg = IXGBE_READ_REG(hw, IXGBE_SECRXCTRL); 2049 secrxreg |= IXGBE_SECRXCTRL_RX_DIS; 2050 IXGBE_WRITE_REG(hw, IXGBE_SECRXCTRL, secrxreg); 2051 for (i = 0; i < IXGBE_MAX_SECRX_POLL; i++) { 2052 secrxreg = IXGBE_READ_REG(hw, IXGBE_SECRXSTAT); 2053 if (secrxreg & IXGBE_SECRXSTAT_SECRX_RDY) 2054 break; 2055 else 2056 /* Use interrupt-safe sleep just in case */ 2057 usec_delay(10); 2058 } 2059 2060 /* For informational purposes only */ 2061 if (i >= IXGBE_MAX_SECRX_POLL) 2062 DEBUGOUT("Rx unit being enabled before security " 2063 "path fully disabled. Continuing with init.\n"); 2064 2065 IXGBE_WRITE_REG(hw, IXGBE_RXCTRL, regval); 2066 secrxreg = IXGBE_READ_REG(hw, IXGBE_SECRXCTRL); 2067 secrxreg &= ~IXGBE_SECRXCTRL_RX_DIS; 2068 IXGBE_WRITE_REG(hw, IXGBE_SECRXCTRL, secrxreg); 2069 IXGBE_WRITE_FLUSH(hw); 2070 2071 return IXGBE_SUCCESS; 2072 } 2073 2074 /** 2075 * ixgbe_verify_fw_version_82599 - verify fw version for 82599 2076 * @hw: pointer to hardware structure 2077 * 2078 * Verifies that installed the firmware version is 0.6 or higher 2079 * for SFI devices. All 82599 SFI devices should have version 0.6 or higher. 2080 * 2081 * Returns IXGBE_ERR_EEPROM_VERSION if the FW is not present or 2082 * if the FW version is not supported. 2083 **/ 2084 static s32 ixgbe_verify_fw_version_82599(struct ixgbe_hw *hw) 2085 { 2086 s32 status = IXGBE_ERR_EEPROM_VERSION; 2087 u16 fw_offset, fw_ptp_cfg_offset; 2088 u16 fw_version = 0; 2089 2090 DEBUGFUNC("ixgbe_verify_fw_version_82599"); 2091 2092 /* firmware check is only necessary for SFI devices */ 2093 if (hw->phy.media_type != ixgbe_media_type_fiber) { 2094 status = IXGBE_SUCCESS; 2095 goto fw_version_out; 2096 } 2097 2098 /* get the offset to the Firmware Module block */ 2099 hw->eeprom.ops.read(hw, IXGBE_FW_PTR, &fw_offset); 2100 2101 if ((fw_offset == 0) || (fw_offset == 0xFFFF)) 2102 goto fw_version_out; 2103 2104 /* get the offset to the Pass Through Patch Configuration block */ 2105 hw->eeprom.ops.read(hw, (fw_offset + 2106 IXGBE_FW_PASSTHROUGH_PATCH_CONFIG_PTR), 2107 &fw_ptp_cfg_offset); 2108 2109 if ((fw_ptp_cfg_offset == 0) || (fw_ptp_cfg_offset == 0xFFFF)) 2110 goto fw_version_out; 2111 2112 /* get the firmware version */ 2113 hw->eeprom.ops.read(hw, (fw_ptp_cfg_offset + 2114 IXGBE_FW_PATCH_VERSION_4), 2115 &fw_version); 2116 2117 if (fw_version > 0x5) 2118 status = IXGBE_SUCCESS; 2119 2120 fw_version_out: 2121 return status; 2122 } 2123 2124 /** 2125 * ixgbe_verify_lesm_fw_enabled_82599 - Checks LESM FW module state. 2126 * @hw: pointer to hardware structure 2127 * 2128 * Returns TRUE if the LESM FW module is present and enabled. Otherwise 2129 * returns FALSE. Smart Speed must be disabled if LESM FW module is enabled. 2130 **/ 2131 bool ixgbe_verify_lesm_fw_enabled_82599(struct ixgbe_hw *hw) 2132 { 2133 bool lesm_enabled = FALSE; 2134 u16 fw_offset, fw_lesm_param_offset, fw_lesm_state; 2135 s32 status; 2136 2137 DEBUGFUNC("ixgbe_verify_lesm_fw_enabled_82599"); 2138 2139 /* get the offset to the Firmware Module block */ 2140 status = hw->eeprom.ops.read(hw, IXGBE_FW_PTR, &fw_offset); 2141 2142 if ((status != IXGBE_SUCCESS) || 2143 (fw_offset == 0) || (fw_offset == 0xFFFF)) 2144 goto out; 2145 2146 /* get the offset to the LESM Parameters block */ 2147 status = hw->eeprom.ops.read(hw, (fw_offset + 2148 IXGBE_FW_LESM_PARAMETERS_PTR), 2149 &fw_lesm_param_offset); 2150 2151 if ((status != IXGBE_SUCCESS) || 2152 (fw_lesm_param_offset == 0) || (fw_lesm_param_offset == 0xFFFF)) 2153 goto out; 2154 2155 /* get the lesm state word */ 2156 status = hw->eeprom.ops.read(hw, (fw_lesm_param_offset + 2157 IXGBE_FW_LESM_STATE_1), 2158 &fw_lesm_state); 2159 2160 if ((status == IXGBE_SUCCESS) && 2161 (fw_lesm_state & IXGBE_FW_LESM_STATE_ENABLED)) 2162 lesm_enabled = TRUE; 2163 2164 out: 2165 return lesm_enabled; 2166 } 2167 2168 2169