1 /****************************************************************************** 2 SPDX-License-Identifier: BSD-3-Clause 3 4 Copyright (c) 2001-2020, Intel Corporation 5 All rights reserved. 6 7 Redistribution and use in source and binary forms, with or without 8 modification, are permitted provided that the following conditions are met: 9 10 1. Redistributions of source code must retain the above copyright notice, 11 this list of conditions and the following disclaimer. 12 13 2. Redistributions in binary form must reproduce the above copyright 14 notice, this list of conditions and the following disclaimer in the 15 documentation and/or other materials provided with the distribution. 16 17 3. Neither the name of the Intel Corporation nor the names of its 18 contributors may be used to endorse or promote products derived from 19 this software without specific prior written permission. 20 21 THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 22 AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 23 IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 24 ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE 25 LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 26 CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 27 SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 28 INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 29 CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 30 ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 31 POSSIBILITY OF SUCH DAMAGE. 32 33 ******************************************************************************/ 34 35 #include "ixgbe_type.h" 36 #include "ixgbe_82599.h" 37 #include "ixgbe_api.h" 38 #include "ixgbe_common.h" 39 #include "ixgbe_phy.h" 40 41 #define IXGBE_82599_MAX_TX_QUEUES 128 42 #define IXGBE_82599_MAX_RX_QUEUES 128 43 #define IXGBE_82599_RAR_ENTRIES 128 44 #define IXGBE_82599_MC_TBL_SIZE 128 45 #define IXGBE_82599_VFT_TBL_SIZE 128 46 #define IXGBE_82599_RX_PB_SIZE 512 47 48 static s32 ixgbe_setup_copper_link_82599(struct ixgbe_hw *hw, 49 ixgbe_link_speed speed, 50 bool autoneg_wait_to_complete); 51 static s32 ixgbe_verify_fw_version_82599(struct ixgbe_hw *hw); 52 static s32 ixgbe_read_eeprom_82599(struct ixgbe_hw *hw, 53 u16 offset, u16 *data); 54 static s32 ixgbe_read_eeprom_buffer_82599(struct ixgbe_hw *hw, u16 offset, 55 u16 words, u16 *data); 56 static s32 ixgbe_read_i2c_byte_82599(struct ixgbe_hw *hw, u8 byte_offset, 57 u8 dev_addr, u8 *data); 58 static s32 ixgbe_write_i2c_byte_82599(struct ixgbe_hw *hw, u8 byte_offset, 59 u8 dev_addr, u8 data); 60 61 void ixgbe_init_mac_link_ops_82599(struct ixgbe_hw *hw) 62 { 63 struct ixgbe_mac_info *mac = &hw->mac; 64 65 DEBUGFUNC("ixgbe_init_mac_link_ops_82599"); 66 67 /* 68 * enable the laser control functions for SFP+ fiber 69 * and MNG not enabled 70 */ 71 if ((mac->ops.get_media_type(hw) == ixgbe_media_type_fiber) && 72 !ixgbe_mng_enabled(hw)) { 73 mac->ops.disable_tx_laser = 74 ixgbe_disable_tx_laser_multispeed_fiber; 75 mac->ops.enable_tx_laser = 76 ixgbe_enable_tx_laser_multispeed_fiber; 77 mac->ops.flap_tx_laser = ixgbe_flap_tx_laser_multispeed_fiber; 78 79 } else { 80 mac->ops.disable_tx_laser = NULL; 81 mac->ops.enable_tx_laser = NULL; 82 mac->ops.flap_tx_laser = NULL; 83 } 84 85 if (hw->phy.multispeed_fiber) { 86 /* Set up dual speed SFP+ support */ 87 mac->ops.setup_link = ixgbe_setup_mac_link_multispeed_fiber; 88 mac->ops.setup_mac_link = ixgbe_setup_mac_link_82599; 89 mac->ops.set_rate_select_speed = 90 ixgbe_set_hard_rate_select_speed; 91 if (ixgbe_get_media_type(hw) == ixgbe_media_type_fiber_fixed) 92 mac->ops.set_rate_select_speed = 93 ixgbe_set_soft_rate_select_speed; 94 } else { 95 if ((ixgbe_get_media_type(hw) == ixgbe_media_type_backplane) && 96 (hw->phy.smart_speed == ixgbe_smart_speed_auto || 97 hw->phy.smart_speed == ixgbe_smart_speed_on) && 98 !ixgbe_verify_lesm_fw_enabled_82599(hw)) { 99 mac->ops.setup_link = ixgbe_setup_mac_link_smartspeed; 100 } else { 101 mac->ops.setup_link = ixgbe_setup_mac_link_82599; 102 } 103 } 104 } 105 106 /** 107 * ixgbe_init_phy_ops_82599 - PHY/SFP specific init 108 * @hw: pointer to hardware structure 109 * 110 * Initialize any function pointers that were not able to be 111 * set during init_shared_code because the PHY/SFP type was 112 * not known. Perform the SFP init if necessary. 113 * 114 **/ 115 s32 ixgbe_init_phy_ops_82599(struct ixgbe_hw *hw) 116 { 117 struct ixgbe_mac_info *mac = &hw->mac; 118 struct ixgbe_phy_info *phy = &hw->phy; 119 s32 ret_val = IXGBE_SUCCESS; 120 u32 esdp; 121 122 DEBUGFUNC("ixgbe_init_phy_ops_82599"); 123 124 if (hw->device_id == IXGBE_DEV_ID_82599_QSFP_SF_QP) { 125 /* Store flag indicating I2C bus access control unit. */ 126 hw->phy.qsfp_shared_i2c_bus = true; 127 128 /* Initialize access to QSFP+ I2C bus */ 129 esdp = IXGBE_READ_REG(hw, IXGBE_ESDP); 130 esdp |= IXGBE_ESDP_SDP0_DIR; 131 esdp &= ~IXGBE_ESDP_SDP1_DIR; 132 esdp &= ~IXGBE_ESDP_SDP0; 133 esdp &= ~IXGBE_ESDP_SDP0_NATIVE; 134 esdp &= ~IXGBE_ESDP_SDP1_NATIVE; 135 IXGBE_WRITE_REG(hw, IXGBE_ESDP, esdp); 136 IXGBE_WRITE_FLUSH(hw); 137 138 phy->ops.read_i2c_byte = ixgbe_read_i2c_byte_82599; 139 phy->ops.write_i2c_byte = ixgbe_write_i2c_byte_82599; 140 } 141 /* Identify the PHY or SFP module */ 142 ret_val = phy->ops.identify(hw); 143 if (ret_val == IXGBE_ERR_SFP_NOT_SUPPORTED) 144 goto init_phy_ops_out; 145 146 /* Setup function pointers based on detected SFP module and speeds */ 147 ixgbe_init_mac_link_ops_82599(hw); 148 if (hw->phy.sfp_type != ixgbe_sfp_type_unknown) 149 hw->phy.ops.reset = NULL; 150 151 /* If copper media, overwrite with copper function pointers */ 152 if (mac->ops.get_media_type(hw) == ixgbe_media_type_copper) { 153 mac->ops.setup_link = ixgbe_setup_copper_link_82599; 154 mac->ops.get_link_capabilities = 155 ixgbe_get_copper_link_capabilities_generic; 156 } 157 158 /* Set necessary function pointers based on PHY type */ 159 switch (hw->phy.type) { 160 case ixgbe_phy_tn: 161 phy->ops.setup_link = ixgbe_setup_phy_link_tnx; 162 phy->ops.check_link = ixgbe_check_phy_link_tnx; 163 phy->ops.get_firmware_version = 164 ixgbe_get_phy_firmware_version_tnx; 165 break; 166 default: 167 break; 168 } 169 init_phy_ops_out: 170 return ret_val; 171 } 172 173 s32 ixgbe_setup_sfp_modules_82599(struct ixgbe_hw *hw) 174 { 175 s32 ret_val = IXGBE_SUCCESS; 176 u16 list_offset, data_offset, data_value; 177 178 DEBUGFUNC("ixgbe_setup_sfp_modules_82599"); 179 180 if (hw->phy.sfp_type != ixgbe_sfp_type_unknown) { 181 ixgbe_init_mac_link_ops_82599(hw); 182 183 hw->phy.ops.reset = NULL; 184 185 ret_val = ixgbe_get_sfp_init_sequence_offsets(hw, &list_offset, 186 &data_offset); 187 if (ret_val != IXGBE_SUCCESS) 188 goto setup_sfp_out; 189 190 /* PHY config will finish before releasing the semaphore */ 191 ret_val = hw->mac.ops.acquire_swfw_sync(hw, 192 IXGBE_GSSR_MAC_CSR_SM); 193 if (ret_val != IXGBE_SUCCESS) { 194 ret_val = IXGBE_ERR_SWFW_SYNC; 195 goto setup_sfp_out; 196 } 197 198 if (hw->eeprom.ops.read(hw, ++data_offset, &data_value)) 199 goto setup_sfp_err; 200 while (data_value != 0xffff) { 201 IXGBE_WRITE_REG(hw, IXGBE_CORECTL, data_value); 202 IXGBE_WRITE_FLUSH(hw); 203 if (hw->eeprom.ops.read(hw, ++data_offset, &data_value)) 204 goto setup_sfp_err; 205 } 206 207 /* Release the semaphore */ 208 hw->mac.ops.release_swfw_sync(hw, IXGBE_GSSR_MAC_CSR_SM); 209 /* Delay obtaining semaphore again to allow FW access 210 * prot_autoc_write uses the semaphore too. 211 */ 212 msec_delay(hw->eeprom.semaphore_delay); 213 214 /* Restart DSP and set SFI mode */ 215 ret_val = hw->mac.ops.prot_autoc_write(hw, 216 hw->mac.orig_autoc | IXGBE_AUTOC_LMS_10G_SERIAL, 217 false); 218 219 if (ret_val) { 220 DEBUGOUT("sfp module setup not complete\n"); 221 ret_val = IXGBE_ERR_SFP_SETUP_NOT_COMPLETE; 222 goto setup_sfp_out; 223 } 224 225 } 226 227 setup_sfp_out: 228 return ret_val; 229 230 setup_sfp_err: 231 /* Release the semaphore */ 232 hw->mac.ops.release_swfw_sync(hw, IXGBE_GSSR_MAC_CSR_SM); 233 /* Delay obtaining semaphore again to allow FW access */ 234 msec_delay(hw->eeprom.semaphore_delay); 235 ERROR_REPORT2(IXGBE_ERROR_INVALID_STATE, 236 "eeprom read at offset %d failed", data_offset); 237 return IXGBE_ERR_PHY; 238 } 239 240 /** 241 * prot_autoc_read_82599 - Hides MAC differences needed for AUTOC read 242 * @hw: pointer to hardware structure 243 * @locked: Return the if we locked for this read. 244 * @reg_val: Value we read from AUTOC 245 * 246 * For this part (82599) we need to wrap read-modify-writes with a possible 247 * FW/SW lock. It is assumed this lock will be freed with the next 248 * prot_autoc_write_82599(). 249 */ 250 s32 prot_autoc_read_82599(struct ixgbe_hw *hw, bool *locked, u32 *reg_val) 251 { 252 s32 ret_val; 253 254 *locked = false; 255 /* If LESM is on then we need to hold the SW/FW semaphore. */ 256 if (ixgbe_verify_lesm_fw_enabled_82599(hw)) { 257 ret_val = hw->mac.ops.acquire_swfw_sync(hw, 258 IXGBE_GSSR_MAC_CSR_SM); 259 if (ret_val != IXGBE_SUCCESS) 260 return IXGBE_ERR_SWFW_SYNC; 261 262 *locked = true; 263 } 264 265 *reg_val = IXGBE_READ_REG(hw, IXGBE_AUTOC); 266 return IXGBE_SUCCESS; 267 } 268 269 /** 270 * prot_autoc_write_82599 - Hides MAC differences needed for AUTOC write 271 * @hw: pointer to hardware structure 272 * @autoc: value to write to AUTOC 273 * @locked: bool to indicate whether the SW/FW lock was already taken by 274 * previous proc_autoc_read_82599. 275 * 276 * This part (82599) may need to hold the SW/FW lock around all writes to 277 * AUTOC. Likewise after a write we need to do a pipeline reset. 278 */ 279 s32 prot_autoc_write_82599(struct ixgbe_hw *hw, u32 autoc, bool locked) 280 { 281 s32 ret_val = IXGBE_SUCCESS; 282 283 /* Blocked by MNG FW so bail */ 284 if (ixgbe_check_reset_blocked(hw)) 285 goto out; 286 287 /* We only need to get the lock if: 288 * - We didn't do it already (in the read part of a read-modify-write) 289 * - LESM is enabled. 290 */ 291 if (!locked && ixgbe_verify_lesm_fw_enabled_82599(hw)) { 292 ret_val = hw->mac.ops.acquire_swfw_sync(hw, 293 IXGBE_GSSR_MAC_CSR_SM); 294 if (ret_val != IXGBE_SUCCESS) 295 return IXGBE_ERR_SWFW_SYNC; 296 297 locked = true; 298 } 299 300 IXGBE_WRITE_REG(hw, IXGBE_AUTOC, autoc); 301 ret_val = ixgbe_reset_pipeline_82599(hw); 302 303 out: 304 /* Free the SW/FW semaphore as we either grabbed it here or 305 * already had it when this function was called. 306 */ 307 if (locked) 308 hw->mac.ops.release_swfw_sync(hw, IXGBE_GSSR_MAC_CSR_SM); 309 310 return ret_val; 311 } 312 313 /** 314 * ixgbe_init_ops_82599 - Inits func ptrs and MAC type 315 * @hw: pointer to hardware structure 316 * 317 * Initialize the function pointers and assign the MAC type for 82599. 318 * Does not touch the hardware. 319 **/ 320 321 s32 ixgbe_init_ops_82599(struct ixgbe_hw *hw) 322 { 323 struct ixgbe_mac_info *mac = &hw->mac; 324 struct ixgbe_phy_info *phy = &hw->phy; 325 struct ixgbe_eeprom_info *eeprom = &hw->eeprom; 326 s32 ret_val; 327 u16 i; 328 329 DEBUGFUNC("ixgbe_init_ops_82599"); 330 331 ixgbe_init_phy_ops_generic(hw); 332 ret_val = ixgbe_init_ops_generic(hw); 333 334 /* PHY */ 335 phy->ops.identify = ixgbe_identify_phy_82599; 336 phy->ops.init = ixgbe_init_phy_ops_82599; 337 338 /* MAC */ 339 mac->ops.reset_hw = ixgbe_reset_hw_82599; 340 mac->ops.enable_relaxed_ordering = ixgbe_enable_relaxed_ordering_gen2; 341 mac->ops.get_media_type = ixgbe_get_media_type_82599; 342 mac->ops.get_supported_physical_layer = 343 ixgbe_get_supported_physical_layer_82599; 344 mac->ops.disable_sec_rx_path = ixgbe_disable_sec_rx_path_generic; 345 mac->ops.enable_sec_rx_path = ixgbe_enable_sec_rx_path_generic; 346 mac->ops.enable_rx_dma = ixgbe_enable_rx_dma_82599; 347 mac->ops.read_analog_reg8 = ixgbe_read_analog_reg8_82599; 348 mac->ops.write_analog_reg8 = ixgbe_write_analog_reg8_82599; 349 mac->ops.start_hw = ixgbe_start_hw_82599; 350 mac->ops.get_san_mac_addr = ixgbe_get_san_mac_addr_generic; 351 mac->ops.set_san_mac_addr = ixgbe_set_san_mac_addr_generic; 352 mac->ops.get_device_caps = ixgbe_get_device_caps_generic; 353 mac->ops.get_wwn_prefix = ixgbe_get_wwn_prefix_generic; 354 mac->ops.get_fcoe_boot_status = ixgbe_get_fcoe_boot_status_generic; 355 mac->ops.prot_autoc_read = prot_autoc_read_82599; 356 mac->ops.prot_autoc_write = prot_autoc_write_82599; 357 358 /* RAR, Multicast, VLAN */ 359 mac->ops.set_vmdq = ixgbe_set_vmdq_generic; 360 mac->ops.set_vmdq_san_mac = ixgbe_set_vmdq_san_mac_generic; 361 mac->ops.clear_vmdq = ixgbe_clear_vmdq_generic; 362 mac->ops.insert_mac_addr = ixgbe_insert_mac_addr_generic; 363 mac->rar_highwater = 1; 364 mac->ops.set_vfta = ixgbe_set_vfta_generic; 365 mac->ops.set_vlvf = ixgbe_set_vlvf_generic; 366 mac->ops.clear_vfta = ixgbe_clear_vfta_generic; 367 mac->ops.init_uta_tables = ixgbe_init_uta_tables_generic; 368 mac->ops.setup_sfp = ixgbe_setup_sfp_modules_82599; 369 mac->ops.set_mac_anti_spoofing = ixgbe_set_mac_anti_spoofing; 370 mac->ops.set_vlan_anti_spoofing = ixgbe_set_vlan_anti_spoofing; 371 372 /* Link */ 373 mac->ops.get_link_capabilities = ixgbe_get_link_capabilities_82599; 374 mac->ops.check_link = ixgbe_check_mac_link_generic; 375 mac->ops.setup_rxpba = ixgbe_set_rxpba_generic; 376 ixgbe_init_mac_link_ops_82599(hw); 377 378 mac->mcft_size = IXGBE_82599_MC_TBL_SIZE; 379 mac->vft_size = IXGBE_82599_VFT_TBL_SIZE; 380 mac->num_rar_entries = IXGBE_82599_RAR_ENTRIES; 381 mac->rx_pb_size = IXGBE_82599_RX_PB_SIZE; 382 mac->max_rx_queues = IXGBE_82599_MAX_RX_QUEUES; 383 mac->max_tx_queues = IXGBE_82599_MAX_TX_QUEUES; 384 mac->max_msix_vectors = ixgbe_get_pcie_msix_count_generic(hw); 385 386 mac->arc_subsystem_valid = !!(IXGBE_READ_REG(hw, IXGBE_FWSM_BY_MAC(hw)) 387 & IXGBE_FWSM_MODE_MASK); 388 389 for (i = 0; i < 64; i++) 390 hw->mbx.ops[i].init_params = ixgbe_init_mbx_params_pf; 391 392 /* EEPROM */ 393 eeprom->ops.read = ixgbe_read_eeprom_82599; 394 eeprom->ops.read_buffer = ixgbe_read_eeprom_buffer_82599; 395 396 /* Manageability interface */ 397 mac->ops.set_fw_drv_ver = ixgbe_set_fw_drv_ver_generic; 398 399 mac->ops.get_thermal_sensor_data = 400 ixgbe_get_thermal_sensor_data_generic; 401 mac->ops.init_thermal_sensor_thresh = 402 ixgbe_init_thermal_sensor_thresh_generic; 403 404 mac->ops.bypass_rw = ixgbe_bypass_rw_generic; 405 mac->ops.bypass_valid_rd = ixgbe_bypass_valid_rd_generic; 406 mac->ops.bypass_set = ixgbe_bypass_set_generic; 407 mac->ops.bypass_rd_eep = ixgbe_bypass_rd_eep_generic; 408 409 mac->ops.get_rtrup2tc = ixgbe_dcb_get_rtrup2tc_generic; 410 411 return ret_val; 412 } 413 414 /** 415 * ixgbe_get_link_capabilities_82599 - Determines link capabilities 416 * @hw: pointer to hardware structure 417 * @speed: pointer to link speed 418 * @autoneg: true when autoneg or autotry is enabled 419 * 420 * Determines the link capabilities by reading the AUTOC register. 421 **/ 422 s32 ixgbe_get_link_capabilities_82599(struct ixgbe_hw *hw, 423 ixgbe_link_speed *speed, 424 bool *autoneg) 425 { 426 s32 status = IXGBE_SUCCESS; 427 u32 autoc = 0; 428 429 DEBUGFUNC("ixgbe_get_link_capabilities_82599"); 430 431 432 /* Check if 1G SFP module. */ 433 if (hw->phy.sfp_type == ixgbe_sfp_type_1g_cu_core0 || 434 hw->phy.sfp_type == ixgbe_sfp_type_1g_cu_core1 || 435 hw->phy.sfp_type == ixgbe_sfp_type_1g_lx_core0 || 436 hw->phy.sfp_type == ixgbe_sfp_type_1g_lx_core1 || 437 hw->phy.sfp_type == ixgbe_sfp_type_1g_sx_core0 || 438 hw->phy.sfp_type == ixgbe_sfp_type_1g_sx_core1) { 439 *speed = IXGBE_LINK_SPEED_1GB_FULL; 440 *autoneg = true; 441 goto out; 442 } 443 444 /* 445 * Determine link capabilities based on the stored value of AUTOC, 446 * which represents EEPROM defaults. If AUTOC value has not 447 * been stored, use the current register values. 448 */ 449 if (hw->mac.orig_link_settings_stored) 450 autoc = hw->mac.orig_autoc; 451 else 452 autoc = IXGBE_READ_REG(hw, IXGBE_AUTOC); 453 454 switch (autoc & IXGBE_AUTOC_LMS_MASK) { 455 case IXGBE_AUTOC_LMS_1G_LINK_NO_AN: 456 *speed = IXGBE_LINK_SPEED_1GB_FULL; 457 *autoneg = false; 458 break; 459 460 case IXGBE_AUTOC_LMS_10G_LINK_NO_AN: 461 *speed = IXGBE_LINK_SPEED_10GB_FULL; 462 *autoneg = false; 463 break; 464 465 case IXGBE_AUTOC_LMS_1G_AN: 466 *speed = IXGBE_LINK_SPEED_1GB_FULL; 467 *autoneg = true; 468 break; 469 470 case IXGBE_AUTOC_LMS_10G_SERIAL: 471 *speed = IXGBE_LINK_SPEED_10GB_FULL; 472 *autoneg = false; 473 break; 474 475 case IXGBE_AUTOC_LMS_KX4_KX_KR: 476 case IXGBE_AUTOC_LMS_KX4_KX_KR_1G_AN: 477 *speed = IXGBE_LINK_SPEED_UNKNOWN; 478 if (autoc & IXGBE_AUTOC_KR_SUPP) 479 *speed |= IXGBE_LINK_SPEED_10GB_FULL; 480 if (autoc & IXGBE_AUTOC_KX4_SUPP) 481 *speed |= IXGBE_LINK_SPEED_10GB_FULL; 482 if (autoc & IXGBE_AUTOC_KX_SUPP) 483 *speed |= IXGBE_LINK_SPEED_1GB_FULL; 484 *autoneg = true; 485 break; 486 487 case IXGBE_AUTOC_LMS_KX4_KX_KR_SGMII: 488 *speed = IXGBE_LINK_SPEED_100_FULL; 489 if (autoc & IXGBE_AUTOC_KR_SUPP) 490 *speed |= IXGBE_LINK_SPEED_10GB_FULL; 491 if (autoc & IXGBE_AUTOC_KX4_SUPP) 492 *speed |= IXGBE_LINK_SPEED_10GB_FULL; 493 if (autoc & IXGBE_AUTOC_KX_SUPP) 494 *speed |= IXGBE_LINK_SPEED_1GB_FULL; 495 *autoneg = true; 496 break; 497 498 case IXGBE_AUTOC_LMS_SGMII_1G_100M: 499 *speed = IXGBE_LINK_SPEED_1GB_FULL | IXGBE_LINK_SPEED_100_FULL; 500 *autoneg = false; 501 break; 502 503 default: 504 status = IXGBE_ERR_LINK_SETUP; 505 goto out; 506 break; 507 } 508 509 if (hw->phy.multispeed_fiber) { 510 *speed |= IXGBE_LINK_SPEED_10GB_FULL | 511 IXGBE_LINK_SPEED_1GB_FULL; 512 513 /* QSFP must not enable full auto-negotiation 514 * Limited autoneg is enabled at 1G 515 */ 516 if (hw->phy.media_type == ixgbe_media_type_fiber_qsfp) 517 *autoneg = false; 518 else 519 *autoneg = true; 520 } 521 522 out: 523 return status; 524 } 525 526 /** 527 * ixgbe_get_media_type_82599 - Get media type 528 * @hw: pointer to hardware structure 529 * 530 * Returns the media type (fiber, copper, backplane) 531 **/ 532 enum ixgbe_media_type ixgbe_get_media_type_82599(struct ixgbe_hw *hw) 533 { 534 enum ixgbe_media_type media_type; 535 536 DEBUGFUNC("ixgbe_get_media_type_82599"); 537 538 /* Detect if there is a copper PHY attached. */ 539 switch (hw->phy.type) { 540 case ixgbe_phy_cu_unknown: 541 case ixgbe_phy_tn: 542 media_type = ixgbe_media_type_copper; 543 goto out; 544 default: 545 break; 546 } 547 548 switch (hw->device_id) { 549 case IXGBE_DEV_ID_82599_KX4: 550 case IXGBE_DEV_ID_82599_KX4_MEZZ: 551 case IXGBE_DEV_ID_82599_COMBO_BACKPLANE: 552 case IXGBE_DEV_ID_82599_KR: 553 case IXGBE_DEV_ID_82599_BACKPLANE_FCOE: 554 case IXGBE_DEV_ID_82599_XAUI_LOM: 555 /* Default device ID is mezzanine card KX/KX4 */ 556 media_type = ixgbe_media_type_backplane; 557 break; 558 case IXGBE_DEV_ID_82599_SFP: 559 case IXGBE_DEV_ID_82599_SFP_FCOE: 560 case IXGBE_DEV_ID_82599_SFP_EM: 561 case IXGBE_DEV_ID_82599_SFP_SF2: 562 case IXGBE_DEV_ID_82599_SFP_SF_QP: 563 case IXGBE_DEV_ID_82599EN_SFP: 564 media_type = ixgbe_media_type_fiber; 565 break; 566 case IXGBE_DEV_ID_82599_CX4: 567 media_type = ixgbe_media_type_cx4; 568 break; 569 case IXGBE_DEV_ID_82599_T3_LOM: 570 media_type = ixgbe_media_type_copper; 571 break; 572 case IXGBE_DEV_ID_82599_LS: 573 media_type = ixgbe_media_type_fiber_lco; 574 break; 575 case IXGBE_DEV_ID_82599_QSFP_SF_QP: 576 media_type = ixgbe_media_type_fiber_qsfp; 577 break; 578 case IXGBE_DEV_ID_82599_BYPASS: 579 media_type = ixgbe_media_type_fiber_fixed; 580 hw->phy.multispeed_fiber = true; 581 break; 582 default: 583 media_type = ixgbe_media_type_unknown; 584 break; 585 } 586 out: 587 return media_type; 588 } 589 590 /** 591 * ixgbe_stop_mac_link_on_d3_82599 - Disables link on D3 592 * @hw: pointer to hardware structure 593 * 594 * Disables link during D3 power down sequence. 595 * 596 **/ 597 void ixgbe_stop_mac_link_on_d3_82599(struct ixgbe_hw *hw) 598 { 599 u32 autoc2_reg; 600 u16 ee_ctrl_2 = 0; 601 602 DEBUGFUNC("ixgbe_stop_mac_link_on_d3_82599"); 603 ixgbe_read_eeprom(hw, IXGBE_EEPROM_CTRL_2, &ee_ctrl_2); 604 605 if (!ixgbe_mng_present(hw) && !hw->wol_enabled && 606 ee_ctrl_2 & IXGBE_EEPROM_CCD_BIT) { 607 autoc2_reg = IXGBE_READ_REG(hw, IXGBE_AUTOC2); 608 autoc2_reg |= IXGBE_AUTOC2_LINK_DISABLE_ON_D3_MASK; 609 IXGBE_WRITE_REG(hw, IXGBE_AUTOC2, autoc2_reg); 610 } 611 } 612 613 /** 614 * ixgbe_start_mac_link_82599 - Setup MAC link settings 615 * @hw: pointer to hardware structure 616 * @autoneg_wait_to_complete: true when waiting for completion is needed 617 * 618 * Configures link settings based on values in the ixgbe_hw struct. 619 * Restarts the link. Performs autonegotiation if needed. 620 **/ 621 s32 ixgbe_start_mac_link_82599(struct ixgbe_hw *hw, 622 bool autoneg_wait_to_complete) 623 { 624 u32 autoc_reg; 625 u32 links_reg; 626 u32 i; 627 s32 status = IXGBE_SUCCESS; 628 bool got_lock = false; 629 630 DEBUGFUNC("ixgbe_start_mac_link_82599"); 631 632 633 /* reset_pipeline requires us to hold this lock as it writes to 634 * AUTOC. 635 */ 636 if (ixgbe_verify_lesm_fw_enabled_82599(hw)) { 637 status = hw->mac.ops.acquire_swfw_sync(hw, 638 IXGBE_GSSR_MAC_CSR_SM); 639 if (status != IXGBE_SUCCESS) 640 goto out; 641 642 got_lock = true; 643 } 644 645 /* Restart link */ 646 ixgbe_reset_pipeline_82599(hw); 647 648 if (got_lock) 649 hw->mac.ops.release_swfw_sync(hw, IXGBE_GSSR_MAC_CSR_SM); 650 651 /* Only poll for autoneg to complete if specified to do so */ 652 if (autoneg_wait_to_complete) { 653 autoc_reg = IXGBE_READ_REG(hw, IXGBE_AUTOC); 654 if ((autoc_reg & IXGBE_AUTOC_LMS_MASK) == 655 IXGBE_AUTOC_LMS_KX4_KX_KR || 656 (autoc_reg & IXGBE_AUTOC_LMS_MASK) == 657 IXGBE_AUTOC_LMS_KX4_KX_KR_1G_AN || 658 (autoc_reg & IXGBE_AUTOC_LMS_MASK) == 659 IXGBE_AUTOC_LMS_KX4_KX_KR_SGMII) { 660 links_reg = 0; /* Just in case Autoneg time = 0 */ 661 for (i = 0; i < IXGBE_AUTO_NEG_TIME; i++) { 662 links_reg = IXGBE_READ_REG(hw, IXGBE_LINKS); 663 if (links_reg & IXGBE_LINKS_KX_AN_COMP) 664 break; 665 msec_delay(100); 666 } 667 if (!(links_reg & IXGBE_LINKS_KX_AN_COMP)) { 668 status = IXGBE_ERR_AUTONEG_NOT_COMPLETE; 669 DEBUGOUT("Autoneg did not complete.\n"); 670 } 671 } 672 } 673 674 /* Add delay to filter out noises during initial link setup */ 675 msec_delay(50); 676 677 out: 678 return status; 679 } 680 681 /** 682 * ixgbe_disable_tx_laser_multispeed_fiber - Disable Tx laser 683 * @hw: pointer to hardware structure 684 * 685 * The base drivers may require better control over SFP+ module 686 * PHY states. This includes selectively shutting down the Tx 687 * laser on the PHY, effectively halting physical link. 688 **/ 689 void ixgbe_disable_tx_laser_multispeed_fiber(struct ixgbe_hw *hw) 690 { 691 u32 esdp_reg = IXGBE_READ_REG(hw, IXGBE_ESDP); 692 693 /* Blocked by MNG FW so bail */ 694 if (ixgbe_check_reset_blocked(hw)) 695 return; 696 697 /* Disable Tx laser; allow 100us to go dark per spec */ 698 esdp_reg |= IXGBE_ESDP_SDP3; 699 IXGBE_WRITE_REG(hw, IXGBE_ESDP, esdp_reg); 700 IXGBE_WRITE_FLUSH(hw); 701 usec_delay(100); 702 } 703 704 /** 705 * ixgbe_enable_tx_laser_multispeed_fiber - Enable Tx laser 706 * @hw: pointer to hardware structure 707 * 708 * The base drivers may require better control over SFP+ module 709 * PHY states. This includes selectively turning on the Tx 710 * laser on the PHY, effectively starting physical link. 711 **/ 712 void ixgbe_enable_tx_laser_multispeed_fiber(struct ixgbe_hw *hw) 713 { 714 u32 esdp_reg = IXGBE_READ_REG(hw, IXGBE_ESDP); 715 716 /* Enable Tx laser; allow 100ms to light up */ 717 esdp_reg &= ~IXGBE_ESDP_SDP3; 718 IXGBE_WRITE_REG(hw, IXGBE_ESDP, esdp_reg); 719 IXGBE_WRITE_FLUSH(hw); 720 msec_delay(100); 721 } 722 723 /** 724 * ixgbe_flap_tx_laser_multispeed_fiber - Flap Tx laser 725 * @hw: pointer to hardware structure 726 * 727 * When the driver changes the link speeds that it can support, 728 * it sets autotry_restart to true to indicate that we need to 729 * initiate a new autotry session with the link partner. To do 730 * so, we set the speed then disable and re-enable the Tx laser, to 731 * alert the link partner that it also needs to restart autotry on its 732 * end. This is consistent with true clause 37 autoneg, which also 733 * involves a loss of signal. 734 **/ 735 void ixgbe_flap_tx_laser_multispeed_fiber(struct ixgbe_hw *hw) 736 { 737 DEBUGFUNC("ixgbe_flap_tx_laser_multispeed_fiber"); 738 739 /* Blocked by MNG FW so bail */ 740 if (ixgbe_check_reset_blocked(hw)) 741 return; 742 743 if (hw->mac.autotry_restart) { 744 ixgbe_disable_tx_laser_multispeed_fiber(hw); 745 ixgbe_enable_tx_laser_multispeed_fiber(hw); 746 hw->mac.autotry_restart = false; 747 } 748 } 749 750 /** 751 * ixgbe_set_hard_rate_select_speed - Set module link speed 752 * @hw: pointer to hardware structure 753 * @speed: link speed to set 754 * 755 * Set module link speed via RS0/RS1 rate select pins. 756 */ 757 void ixgbe_set_hard_rate_select_speed(struct ixgbe_hw *hw, 758 ixgbe_link_speed speed) 759 { 760 u32 esdp_reg = IXGBE_READ_REG(hw, IXGBE_ESDP); 761 762 switch (speed) { 763 case IXGBE_LINK_SPEED_10GB_FULL: 764 esdp_reg |= (IXGBE_ESDP_SDP5_DIR | IXGBE_ESDP_SDP5); 765 break; 766 case IXGBE_LINK_SPEED_1GB_FULL: 767 esdp_reg &= ~IXGBE_ESDP_SDP5; 768 esdp_reg |= IXGBE_ESDP_SDP5_DIR; 769 break; 770 default: 771 DEBUGOUT("Invalid fixed module speed\n"); 772 return; 773 } 774 775 IXGBE_WRITE_REG(hw, IXGBE_ESDP, esdp_reg); 776 IXGBE_WRITE_FLUSH(hw); 777 } 778 779 /** 780 * ixgbe_setup_mac_link_smartspeed - Set MAC link speed using SmartSpeed 781 * @hw: pointer to hardware structure 782 * @speed: new link speed 783 * @autoneg_wait_to_complete: true when waiting for completion is needed 784 * 785 * Implements the Intel SmartSpeed algorithm. 786 **/ 787 s32 ixgbe_setup_mac_link_smartspeed(struct ixgbe_hw *hw, 788 ixgbe_link_speed speed, 789 bool autoneg_wait_to_complete) 790 { 791 s32 status = IXGBE_SUCCESS; 792 ixgbe_link_speed link_speed = IXGBE_LINK_SPEED_UNKNOWN; 793 s32 i, j; 794 bool link_up = false; 795 u32 autoc_reg = IXGBE_READ_REG(hw, IXGBE_AUTOC); 796 797 DEBUGFUNC("ixgbe_setup_mac_link_smartspeed"); 798 799 /* Set autoneg_advertised value based on input link speed */ 800 hw->phy.autoneg_advertised = 0; 801 802 if (speed & IXGBE_LINK_SPEED_10GB_FULL) 803 hw->phy.autoneg_advertised |= IXGBE_LINK_SPEED_10GB_FULL; 804 805 if (speed & IXGBE_LINK_SPEED_1GB_FULL) 806 hw->phy.autoneg_advertised |= IXGBE_LINK_SPEED_1GB_FULL; 807 808 if (speed & IXGBE_LINK_SPEED_100_FULL) 809 hw->phy.autoneg_advertised |= IXGBE_LINK_SPEED_100_FULL; 810 811 /* 812 * Implement Intel SmartSpeed algorithm. SmartSpeed will reduce the 813 * autoneg advertisement if link is unable to be established at the 814 * highest negotiated rate. This can sometimes happen due to integrity 815 * issues with the physical media connection. 816 */ 817 818 /* First, try to get link with full advertisement */ 819 hw->phy.smart_speed_active = false; 820 for (j = 0; j < IXGBE_SMARTSPEED_MAX_RETRIES; j++) { 821 status = ixgbe_setup_mac_link_82599(hw, speed, 822 autoneg_wait_to_complete); 823 if (status != IXGBE_SUCCESS) 824 goto out; 825 826 /* 827 * Wait for the controller to acquire link. Per IEEE 802.3ap, 828 * Section 73.10.2, we may have to wait up to 500ms if KR is 829 * attempted, or 200ms if KX/KX4/BX/BX4 is attempted, per 830 * Table 9 in the AN MAS. 831 */ 832 for (i = 0; i < 5; i++) { 833 msec_delay(100); 834 835 /* If we have link, just jump out */ 836 status = ixgbe_check_link(hw, &link_speed, &link_up, 837 false); 838 if (status != IXGBE_SUCCESS) 839 goto out; 840 841 if (link_up) 842 goto out; 843 } 844 } 845 846 /* 847 * We didn't get link. If we advertised KR plus one of KX4/KX 848 * (or BX4/BX), then disable KR and try again. 849 */ 850 if (((autoc_reg & IXGBE_AUTOC_KR_SUPP) == 0) || 851 ((autoc_reg & IXGBE_AUTOC_KX4_KX_SUPP_MASK) == 0)) 852 goto out; 853 854 /* Turn SmartSpeed on to disable KR support */ 855 hw->phy.smart_speed_active = true; 856 status = ixgbe_setup_mac_link_82599(hw, speed, 857 autoneg_wait_to_complete); 858 if (status != IXGBE_SUCCESS) 859 goto out; 860 861 /* 862 * Wait for the controller to acquire link. 600ms will allow for 863 * the AN link_fail_inhibit_timer as well for multiple cycles of 864 * parallel detect, both 10g and 1g. This allows for the maximum 865 * connect attempts as defined in the AN MAS table 73-7. 866 */ 867 for (i = 0; i < 6; i++) { 868 msec_delay(100); 869 870 /* If we have link, just jump out */ 871 status = ixgbe_check_link(hw, &link_speed, &link_up, false); 872 if (status != IXGBE_SUCCESS) 873 goto out; 874 875 if (link_up) 876 goto out; 877 } 878 879 /* We didn't get link. Turn SmartSpeed back off. */ 880 hw->phy.smart_speed_active = false; 881 status = ixgbe_setup_mac_link_82599(hw, speed, 882 autoneg_wait_to_complete); 883 884 out: 885 if (link_up && (link_speed == IXGBE_LINK_SPEED_1GB_FULL)) 886 DEBUGOUT("Smartspeed has downgraded the link speed " 887 "from the maximum advertised\n"); 888 return status; 889 } 890 891 /** 892 * ixgbe_setup_mac_link_82599 - Set MAC link speed 893 * @hw: pointer to hardware structure 894 * @speed: new link speed 895 * @autoneg_wait_to_complete: true when waiting for completion is needed 896 * 897 * Set the link speed in the AUTOC register and restarts link. 898 **/ 899 s32 ixgbe_setup_mac_link_82599(struct ixgbe_hw *hw, 900 ixgbe_link_speed speed, 901 bool autoneg_wait_to_complete) 902 { 903 bool autoneg = false; 904 s32 status = IXGBE_SUCCESS; 905 u32 pma_pmd_1g, link_mode; 906 u32 current_autoc = IXGBE_READ_REG(hw, IXGBE_AUTOC); /* holds the value of AUTOC register at this current point in time */ 907 u32 orig_autoc = 0; /* holds the cached value of AUTOC register */ 908 u32 autoc = current_autoc; /* Temporary variable used for comparison purposes */ 909 u32 autoc2 = IXGBE_READ_REG(hw, IXGBE_AUTOC2); 910 u32 pma_pmd_10g_serial = autoc2 & IXGBE_AUTOC2_10G_SERIAL_PMA_PMD_MASK; 911 u32 links_reg; 912 u32 i; 913 ixgbe_link_speed link_capabilities = IXGBE_LINK_SPEED_UNKNOWN; 914 915 DEBUGFUNC("ixgbe_setup_mac_link_82599"); 916 917 /* Check to see if speed passed in is supported. */ 918 status = ixgbe_get_link_capabilities(hw, &link_capabilities, &autoneg); 919 if (status) 920 goto out; 921 922 speed &= link_capabilities; 923 924 if (speed == IXGBE_LINK_SPEED_UNKNOWN) { 925 status = IXGBE_ERR_LINK_SETUP; 926 goto out; 927 } 928 929 /* Use stored value (EEPROM defaults) of AUTOC to find KR/KX4 support*/ 930 if (hw->mac.orig_link_settings_stored) 931 orig_autoc = hw->mac.orig_autoc; 932 else 933 orig_autoc = autoc; 934 935 link_mode = autoc & IXGBE_AUTOC_LMS_MASK; 936 pma_pmd_1g = autoc & IXGBE_AUTOC_1G_PMA_PMD_MASK; 937 938 if (link_mode == IXGBE_AUTOC_LMS_KX4_KX_KR || 939 link_mode == IXGBE_AUTOC_LMS_KX4_KX_KR_1G_AN || 940 link_mode == IXGBE_AUTOC_LMS_KX4_KX_KR_SGMII) { 941 /* Set KX4/KX/KR support according to speed requested */ 942 autoc &= ~(IXGBE_AUTOC_KX4_KX_SUPP_MASK | IXGBE_AUTOC_KR_SUPP); 943 if (speed & IXGBE_LINK_SPEED_10GB_FULL) { 944 if (orig_autoc & IXGBE_AUTOC_KX4_SUPP) 945 autoc |= IXGBE_AUTOC_KX4_SUPP; 946 if ((orig_autoc & IXGBE_AUTOC_KR_SUPP) && 947 (hw->phy.smart_speed_active == false)) 948 autoc |= IXGBE_AUTOC_KR_SUPP; 949 } 950 if (speed & IXGBE_LINK_SPEED_1GB_FULL) 951 autoc |= IXGBE_AUTOC_KX_SUPP; 952 } else if ((pma_pmd_1g == IXGBE_AUTOC_1G_SFI) && 953 (link_mode == IXGBE_AUTOC_LMS_1G_LINK_NO_AN || 954 link_mode == IXGBE_AUTOC_LMS_1G_AN)) { 955 /* Switch from 1G SFI to 10G SFI if requested */ 956 if ((speed == IXGBE_LINK_SPEED_10GB_FULL) && 957 (pma_pmd_10g_serial == IXGBE_AUTOC2_10G_SFI)) { 958 autoc &= ~IXGBE_AUTOC_LMS_MASK; 959 autoc |= IXGBE_AUTOC_LMS_10G_SERIAL; 960 } 961 } else if ((pma_pmd_10g_serial == IXGBE_AUTOC2_10G_SFI) && 962 (link_mode == IXGBE_AUTOC_LMS_10G_SERIAL)) { 963 /* Switch from 10G SFI to 1G SFI if requested */ 964 if ((speed == IXGBE_LINK_SPEED_1GB_FULL) && 965 (pma_pmd_1g == IXGBE_AUTOC_1G_SFI)) { 966 autoc &= ~IXGBE_AUTOC_LMS_MASK; 967 if (autoneg || hw->phy.type == ixgbe_phy_qsfp_intel) 968 autoc |= IXGBE_AUTOC_LMS_1G_AN; 969 else 970 autoc |= IXGBE_AUTOC_LMS_1G_LINK_NO_AN; 971 } 972 } 973 974 if (autoc != current_autoc) { 975 /* Restart link */ 976 status = hw->mac.ops.prot_autoc_write(hw, autoc, false); 977 if (status != IXGBE_SUCCESS) 978 goto out; 979 980 /* Only poll for autoneg to complete if specified to do so */ 981 if (autoneg_wait_to_complete) { 982 if (link_mode == IXGBE_AUTOC_LMS_KX4_KX_KR || 983 link_mode == IXGBE_AUTOC_LMS_KX4_KX_KR_1G_AN || 984 link_mode == IXGBE_AUTOC_LMS_KX4_KX_KR_SGMII) { 985 links_reg = 0; /*Just in case Autoneg time=0*/ 986 for (i = 0; i < IXGBE_AUTO_NEG_TIME; i++) { 987 links_reg = 988 IXGBE_READ_REG(hw, IXGBE_LINKS); 989 if (links_reg & IXGBE_LINKS_KX_AN_COMP) 990 break; 991 msec_delay(100); 992 } 993 if (!(links_reg & IXGBE_LINKS_KX_AN_COMP)) { 994 status = 995 IXGBE_ERR_AUTONEG_NOT_COMPLETE; 996 DEBUGOUT("Autoneg did not complete.\n"); 997 } 998 } 999 } 1000 1001 /* Add delay to filter out noises during initial link setup */ 1002 msec_delay(50); 1003 } 1004 1005 out: 1006 return status; 1007 } 1008 1009 /** 1010 * ixgbe_setup_copper_link_82599 - Set the PHY autoneg advertised field 1011 * @hw: pointer to hardware structure 1012 * @speed: new link speed 1013 * @autoneg_wait_to_complete: true if waiting is needed to complete 1014 * 1015 * Restarts link on PHY and MAC based on settings passed in. 1016 **/ 1017 static s32 ixgbe_setup_copper_link_82599(struct ixgbe_hw *hw, 1018 ixgbe_link_speed speed, 1019 bool autoneg_wait_to_complete) 1020 { 1021 s32 status; 1022 1023 DEBUGFUNC("ixgbe_setup_copper_link_82599"); 1024 1025 /* Setup the PHY according to input speed */ 1026 status = hw->phy.ops.setup_link_speed(hw, speed, 1027 autoneg_wait_to_complete); 1028 /* Set up MAC */ 1029 ixgbe_start_mac_link_82599(hw, autoneg_wait_to_complete); 1030 1031 return status; 1032 } 1033 1034 /** 1035 * ixgbe_reset_hw_82599 - Perform hardware reset 1036 * @hw: pointer to hardware structure 1037 * 1038 * Resets the hardware by resetting the transmit and receive units, masks 1039 * and clears all interrupts, perform a PHY reset, and perform a link (MAC) 1040 * reset. 1041 **/ 1042 s32 ixgbe_reset_hw_82599(struct ixgbe_hw *hw) 1043 { 1044 ixgbe_link_speed link_speed; 1045 s32 status; 1046 u32 ctrl = 0; 1047 u32 i, autoc, autoc2; 1048 u32 curr_lms; 1049 bool link_up = false; 1050 1051 DEBUGFUNC("ixgbe_reset_hw_82599"); 1052 1053 /* Call adapter stop to disable tx/rx and clear interrupts */ 1054 status = hw->mac.ops.stop_adapter(hw); 1055 if (status != IXGBE_SUCCESS) 1056 goto reset_hw_out; 1057 1058 /* flush pending Tx transactions */ 1059 ixgbe_clear_tx_pending(hw); 1060 1061 /* PHY ops must be identified and initialized prior to reset */ 1062 1063 /* Identify PHY and related function pointers */ 1064 status = hw->phy.ops.init(hw); 1065 1066 if (status == IXGBE_ERR_SFP_NOT_SUPPORTED) 1067 goto reset_hw_out; 1068 1069 /* Setup SFP module if there is one present. */ 1070 if (hw->phy.sfp_setup_needed) { 1071 status = hw->mac.ops.setup_sfp(hw); 1072 hw->phy.sfp_setup_needed = false; 1073 } 1074 1075 if (status == IXGBE_ERR_SFP_NOT_SUPPORTED) 1076 goto reset_hw_out; 1077 1078 /* Reset PHY */ 1079 if (hw->phy.reset_disable == false && hw->phy.ops.reset != NULL) 1080 hw->phy.ops.reset(hw); 1081 1082 /* remember AUTOC from before we reset */ 1083 curr_lms = IXGBE_READ_REG(hw, IXGBE_AUTOC) & IXGBE_AUTOC_LMS_MASK; 1084 1085 mac_reset_top: 1086 /* 1087 * Issue global reset to the MAC. Needs to be SW reset if link is up. 1088 * If link reset is used when link is up, it might reset the PHY when 1089 * mng is using it. If link is down or the flag to force full link 1090 * reset is set, then perform link reset. 1091 */ 1092 ctrl = IXGBE_CTRL_LNK_RST; 1093 if (!hw->force_full_reset) { 1094 hw->mac.ops.check_link(hw, &link_speed, &link_up, false); 1095 if (link_up) 1096 ctrl = IXGBE_CTRL_RST; 1097 } 1098 1099 ctrl |= IXGBE_READ_REG(hw, IXGBE_CTRL); 1100 IXGBE_WRITE_REG(hw, IXGBE_CTRL, ctrl); 1101 IXGBE_WRITE_FLUSH(hw); 1102 1103 /* Poll for reset bit to self-clear meaning reset is complete */ 1104 for (i = 0; i < 10; i++) { 1105 usec_delay(1); 1106 ctrl = IXGBE_READ_REG(hw, IXGBE_CTRL); 1107 if (!(ctrl & IXGBE_CTRL_RST_MASK)) 1108 break; 1109 } 1110 1111 if (ctrl & IXGBE_CTRL_RST_MASK) { 1112 status = IXGBE_ERR_RESET_FAILED; 1113 DEBUGOUT("Reset polling failed to complete.\n"); 1114 } 1115 1116 msec_delay(50); 1117 1118 /* 1119 * Double resets are required for recovery from certain error 1120 * conditions. Between resets, it is necessary to stall to 1121 * allow time for any pending HW events to complete. 1122 */ 1123 if (hw->mac.flags & IXGBE_FLAGS_DOUBLE_RESET_REQUIRED) { 1124 hw->mac.flags &= ~IXGBE_FLAGS_DOUBLE_RESET_REQUIRED; 1125 goto mac_reset_top; 1126 } 1127 1128 /* 1129 * Store the original AUTOC/AUTOC2 values if they have not been 1130 * stored off yet. Otherwise restore the stored original 1131 * values since the reset operation sets back to defaults. 1132 */ 1133 autoc = IXGBE_READ_REG(hw, IXGBE_AUTOC); 1134 autoc2 = IXGBE_READ_REG(hw, IXGBE_AUTOC2); 1135 1136 /* Enable link if disabled in NVM */ 1137 if (autoc2 & IXGBE_AUTOC2_LINK_DISABLE_MASK) { 1138 autoc2 &= ~IXGBE_AUTOC2_LINK_DISABLE_MASK; 1139 IXGBE_WRITE_REG(hw, IXGBE_AUTOC2, autoc2); 1140 IXGBE_WRITE_FLUSH(hw); 1141 } 1142 1143 if (hw->mac.orig_link_settings_stored == false) { 1144 hw->mac.orig_autoc = autoc; 1145 hw->mac.orig_autoc2 = autoc2; 1146 hw->mac.orig_link_settings_stored = true; 1147 } else { 1148 1149 /* If MNG FW is running on a multi-speed device that 1150 * doesn't autoneg with out driver support we need to 1151 * leave LMS in the state it was before we MAC reset. 1152 * Likewise if we support WoL we don't want change the 1153 * LMS state. 1154 */ 1155 if ((hw->phy.multispeed_fiber && ixgbe_mng_enabled(hw)) || 1156 hw->wol_enabled) 1157 hw->mac.orig_autoc = 1158 (hw->mac.orig_autoc & ~IXGBE_AUTOC_LMS_MASK) | 1159 curr_lms; 1160 1161 if (autoc != hw->mac.orig_autoc) { 1162 status = hw->mac.ops.prot_autoc_write(hw, 1163 hw->mac.orig_autoc, 1164 false); 1165 if (status != IXGBE_SUCCESS) 1166 goto reset_hw_out; 1167 } 1168 1169 if ((autoc2 & IXGBE_AUTOC2_UPPER_MASK) != 1170 (hw->mac.orig_autoc2 & IXGBE_AUTOC2_UPPER_MASK)) { 1171 autoc2 &= ~IXGBE_AUTOC2_UPPER_MASK; 1172 autoc2 |= (hw->mac.orig_autoc2 & 1173 IXGBE_AUTOC2_UPPER_MASK); 1174 IXGBE_WRITE_REG(hw, IXGBE_AUTOC2, autoc2); 1175 } 1176 } 1177 1178 /* Store the permanent mac address */ 1179 hw->mac.ops.get_mac_addr(hw, hw->mac.perm_addr); 1180 1181 /* 1182 * Store MAC address from RAR0, clear receive address registers, and 1183 * clear the multicast table. Also reset num_rar_entries to 128, 1184 * since we modify this value when programming the SAN MAC address. 1185 */ 1186 hw->mac.num_rar_entries = 128; 1187 hw->mac.ops.init_rx_addrs(hw); 1188 1189 /* Store the permanent SAN mac address */ 1190 hw->mac.ops.get_san_mac_addr(hw, hw->mac.san_addr); 1191 1192 /* Add the SAN MAC address to the RAR only if it's a valid address */ 1193 if (ixgbe_validate_mac_addr(hw->mac.san_addr) == 0) { 1194 /* Save the SAN MAC RAR index */ 1195 hw->mac.san_mac_rar_index = hw->mac.num_rar_entries - 1; 1196 1197 hw->mac.ops.set_rar(hw, hw->mac.san_mac_rar_index, 1198 hw->mac.san_addr, 0, IXGBE_RAH_AV); 1199 1200 /* clear VMDq pool/queue selection for this RAR */ 1201 hw->mac.ops.clear_vmdq(hw, hw->mac.san_mac_rar_index, 1202 IXGBE_CLEAR_VMDQ_ALL); 1203 1204 /* Reserve the last RAR for the SAN MAC address */ 1205 hw->mac.num_rar_entries--; 1206 } 1207 1208 /* Store the alternative WWNN/WWPN prefix */ 1209 hw->mac.ops.get_wwn_prefix(hw, &hw->mac.wwnn_prefix, 1210 &hw->mac.wwpn_prefix); 1211 1212 reset_hw_out: 1213 return status; 1214 } 1215 1216 /** 1217 * ixgbe_fdir_check_cmd_complete - poll to check whether FDIRCMD is complete 1218 * @hw: pointer to hardware structure 1219 * @fdircmd: current value of FDIRCMD register 1220 */ 1221 static s32 ixgbe_fdir_check_cmd_complete(struct ixgbe_hw *hw, u32 *fdircmd) 1222 { 1223 int i; 1224 1225 for (i = 0; i < IXGBE_FDIRCMD_CMD_POLL; i++) { 1226 *fdircmd = IXGBE_READ_REG(hw, IXGBE_FDIRCMD); 1227 if (!(*fdircmd & IXGBE_FDIRCMD_CMD_MASK)) 1228 return IXGBE_SUCCESS; 1229 usec_delay(10); 1230 } 1231 1232 return IXGBE_ERR_FDIR_CMD_INCOMPLETE; 1233 } 1234 1235 /** 1236 * ixgbe_reinit_fdir_tables_82599 - Reinitialize Flow Director tables. 1237 * @hw: pointer to hardware structure 1238 **/ 1239 s32 ixgbe_reinit_fdir_tables_82599(struct ixgbe_hw *hw) 1240 { 1241 s32 err; 1242 int i; 1243 u32 fdirctrl = IXGBE_READ_REG(hw, IXGBE_FDIRCTRL); 1244 u32 fdircmd; 1245 fdirctrl &= ~IXGBE_FDIRCTRL_INIT_DONE; 1246 1247 DEBUGFUNC("ixgbe_reinit_fdir_tables_82599"); 1248 1249 /* 1250 * Before starting reinitialization process, 1251 * FDIRCMD.CMD must be zero. 1252 */ 1253 err = ixgbe_fdir_check_cmd_complete(hw, &fdircmd); 1254 if (err) { 1255 DEBUGOUT("Flow Director previous command did not complete, aborting table re-initialization.\n"); 1256 return err; 1257 } 1258 1259 IXGBE_WRITE_REG(hw, IXGBE_FDIRFREE, 0); 1260 IXGBE_WRITE_FLUSH(hw); 1261 /* 1262 * 82599 adapters flow director init flow cannot be restarted, 1263 * Workaround 82599 silicon errata by performing the following steps 1264 * before re-writing the FDIRCTRL control register with the same value. 1265 * - write 1 to bit 8 of FDIRCMD register & 1266 * - write 0 to bit 8 of FDIRCMD register 1267 */ 1268 IXGBE_WRITE_REG(hw, IXGBE_FDIRCMD, 1269 (IXGBE_READ_REG(hw, IXGBE_FDIRCMD) | 1270 IXGBE_FDIRCMD_CLEARHT)); 1271 IXGBE_WRITE_FLUSH(hw); 1272 IXGBE_WRITE_REG(hw, IXGBE_FDIRCMD, 1273 (IXGBE_READ_REG(hw, IXGBE_FDIRCMD) & 1274 ~IXGBE_FDIRCMD_CLEARHT)); 1275 IXGBE_WRITE_FLUSH(hw); 1276 /* 1277 * Clear FDIR Hash register to clear any leftover hashes 1278 * waiting to be programmed. 1279 */ 1280 IXGBE_WRITE_REG(hw, IXGBE_FDIRHASH, 0x00); 1281 IXGBE_WRITE_FLUSH(hw); 1282 1283 IXGBE_WRITE_REG(hw, IXGBE_FDIRCTRL, fdirctrl); 1284 IXGBE_WRITE_FLUSH(hw); 1285 1286 /* Poll init-done after we write FDIRCTRL register */ 1287 for (i = 0; i < IXGBE_FDIR_INIT_DONE_POLL; i++) { 1288 if (IXGBE_READ_REG(hw, IXGBE_FDIRCTRL) & 1289 IXGBE_FDIRCTRL_INIT_DONE) 1290 break; 1291 msec_delay(1); 1292 } 1293 if (i >= IXGBE_FDIR_INIT_DONE_POLL) { 1294 DEBUGOUT("Flow Director Signature poll time exceeded!\n"); 1295 return IXGBE_ERR_FDIR_REINIT_FAILED; 1296 } 1297 1298 /* Clear FDIR statistics registers (read to clear) */ 1299 IXGBE_READ_REG(hw, IXGBE_FDIRUSTAT); 1300 IXGBE_READ_REG(hw, IXGBE_FDIRFSTAT); 1301 IXGBE_READ_REG(hw, IXGBE_FDIRMATCH); 1302 IXGBE_READ_REG(hw, IXGBE_FDIRMISS); 1303 IXGBE_READ_REG(hw, IXGBE_FDIRLEN); 1304 1305 return IXGBE_SUCCESS; 1306 } 1307 1308 /** 1309 * ixgbe_fdir_enable_82599 - Initialize Flow Director control registers 1310 * @hw: pointer to hardware structure 1311 * @fdirctrl: value to write to flow director control register 1312 **/ 1313 static void ixgbe_fdir_enable_82599(struct ixgbe_hw *hw, u32 fdirctrl) 1314 { 1315 int i; 1316 1317 DEBUGFUNC("ixgbe_fdir_enable_82599"); 1318 1319 /* Prime the keys for hashing */ 1320 IXGBE_WRITE_REG(hw, IXGBE_FDIRHKEY, IXGBE_ATR_BUCKET_HASH_KEY); 1321 IXGBE_WRITE_REG(hw, IXGBE_FDIRSKEY, IXGBE_ATR_SIGNATURE_HASH_KEY); 1322 1323 /* 1324 * Poll init-done after we write the register. Estimated times: 1325 * 10G: PBALLOC = 11b, timing is 60us 1326 * 1G: PBALLOC = 11b, timing is 600us 1327 * 100M: PBALLOC = 11b, timing is 6ms 1328 * 1329 * Multiple these timings by 4 if under full Rx load 1330 * 1331 * So we'll poll for IXGBE_FDIR_INIT_DONE_POLL times, sleeping for 1332 * 1 msec per poll time. If we're at line rate and drop to 100M, then 1333 * this might not finish in our poll time, but we can live with that 1334 * for now. 1335 */ 1336 IXGBE_WRITE_REG(hw, IXGBE_FDIRCTRL, fdirctrl); 1337 IXGBE_WRITE_FLUSH(hw); 1338 for (i = 0; i < IXGBE_FDIR_INIT_DONE_POLL; i++) { 1339 if (IXGBE_READ_REG(hw, IXGBE_FDIRCTRL) & 1340 IXGBE_FDIRCTRL_INIT_DONE) 1341 break; 1342 msec_delay(1); 1343 } 1344 1345 if (i >= IXGBE_FDIR_INIT_DONE_POLL) 1346 DEBUGOUT("Flow Director poll time exceeded!\n"); 1347 } 1348 1349 /** 1350 * ixgbe_init_fdir_signature_82599 - Initialize Flow Director signature filters 1351 * @hw: pointer to hardware structure 1352 * @fdirctrl: value to write to flow director control register, initially 1353 * contains just the value of the Rx packet buffer allocation 1354 **/ 1355 s32 ixgbe_init_fdir_signature_82599(struct ixgbe_hw *hw, u32 fdirctrl) 1356 { 1357 DEBUGFUNC("ixgbe_init_fdir_signature_82599"); 1358 1359 /* 1360 * Continue setup of fdirctrl register bits: 1361 * Move the flexible bytes to use the ethertype - shift 6 words 1362 * Set the maximum length per hash bucket to 0xA filters 1363 * Send interrupt when 64 filters are left 1364 */ 1365 fdirctrl |= (0x6 << IXGBE_FDIRCTRL_FLEX_SHIFT) | 1366 (0xA << IXGBE_FDIRCTRL_MAX_LENGTH_SHIFT) | 1367 (4 << IXGBE_FDIRCTRL_FULL_THRESH_SHIFT); 1368 1369 /* write hashes and fdirctrl register, poll for completion */ 1370 ixgbe_fdir_enable_82599(hw, fdirctrl); 1371 1372 return IXGBE_SUCCESS; 1373 } 1374 1375 /** 1376 * ixgbe_init_fdir_perfect_82599 - Initialize Flow Director perfect filters 1377 * @hw: pointer to hardware structure 1378 * @fdirctrl: value to write to flow director control register, initially 1379 * contains just the value of the Rx packet buffer allocation 1380 * @cloud_mode: true - cloud mode, false - other mode 1381 **/ 1382 s32 ixgbe_init_fdir_perfect_82599(struct ixgbe_hw *hw, u32 fdirctrl, 1383 bool cloud_mode) 1384 { 1385 UNREFERENCED_1PARAMETER(cloud_mode); 1386 DEBUGFUNC("ixgbe_init_fdir_perfect_82599"); 1387 1388 /* 1389 * Continue setup of fdirctrl register bits: 1390 * Turn perfect match filtering on 1391 * Report hash in RSS field of Rx wb descriptor 1392 * Initialize the drop queue to queue 127 1393 * Move the flexible bytes to use the ethertype - shift 6 words 1394 * Set the maximum length per hash bucket to 0xA filters 1395 * Send interrupt when 64 (0x4 * 16) filters are left 1396 */ 1397 fdirctrl |= IXGBE_FDIRCTRL_PERFECT_MATCH | 1398 IXGBE_FDIRCTRL_REPORT_STATUS | 1399 (IXGBE_FDIR_DROP_QUEUE << IXGBE_FDIRCTRL_DROP_Q_SHIFT) | 1400 (0x6 << IXGBE_FDIRCTRL_FLEX_SHIFT) | 1401 (0xA << IXGBE_FDIRCTRL_MAX_LENGTH_SHIFT) | 1402 (4 << IXGBE_FDIRCTRL_FULL_THRESH_SHIFT); 1403 1404 if (cloud_mode) 1405 fdirctrl |=(IXGBE_FDIRCTRL_FILTERMODE_CLOUD << 1406 IXGBE_FDIRCTRL_FILTERMODE_SHIFT); 1407 1408 /* write hashes and fdirctrl register, poll for completion */ 1409 ixgbe_fdir_enable_82599(hw, fdirctrl); 1410 1411 return IXGBE_SUCCESS; 1412 } 1413 1414 /** 1415 * ixgbe_set_fdir_drop_queue_82599 - Set Flow Director drop queue 1416 * @hw: pointer to hardware structure 1417 * @dropqueue: Rx queue index used for the dropped packets 1418 **/ 1419 void ixgbe_set_fdir_drop_queue_82599(struct ixgbe_hw *hw, u8 dropqueue) 1420 { 1421 u32 fdirctrl; 1422 1423 DEBUGFUNC("ixgbe_set_fdir_drop_queue_82599"); 1424 /* Clear init done bit and drop queue field */ 1425 fdirctrl = IXGBE_READ_REG(hw, IXGBE_FDIRCTRL); 1426 fdirctrl &= ~(IXGBE_FDIRCTRL_DROP_Q_MASK | IXGBE_FDIRCTRL_INIT_DONE); 1427 1428 /* Set drop queue */ 1429 fdirctrl |= (dropqueue << IXGBE_FDIRCTRL_DROP_Q_SHIFT); 1430 if ((hw->mac.type == ixgbe_mac_X550) || 1431 (hw->mac.type == ixgbe_mac_X550EM_x) || 1432 (hw->mac.type == ixgbe_mac_X550EM_a)) 1433 fdirctrl |= IXGBE_FDIRCTRL_DROP_NO_MATCH; 1434 1435 IXGBE_WRITE_REG(hw, IXGBE_FDIRCMD, 1436 (IXGBE_READ_REG(hw, IXGBE_FDIRCMD) | 1437 IXGBE_FDIRCMD_CLEARHT)); 1438 IXGBE_WRITE_FLUSH(hw); 1439 IXGBE_WRITE_REG(hw, IXGBE_FDIRCMD, 1440 (IXGBE_READ_REG(hw, IXGBE_FDIRCMD) & 1441 ~IXGBE_FDIRCMD_CLEARHT)); 1442 IXGBE_WRITE_FLUSH(hw); 1443 1444 /* write hashes and fdirctrl register, poll for completion */ 1445 ixgbe_fdir_enable_82599(hw, fdirctrl); 1446 } 1447 1448 /* 1449 * These defines allow us to quickly generate all of the necessary instructions 1450 * in the function below by simply calling out IXGBE_COMPUTE_SIG_HASH_ITERATION 1451 * for values 0 through 15 1452 */ 1453 #define IXGBE_ATR_COMMON_HASH_KEY \ 1454 (IXGBE_ATR_BUCKET_HASH_KEY & IXGBE_ATR_SIGNATURE_HASH_KEY) 1455 #define IXGBE_COMPUTE_SIG_HASH_ITERATION(_n) \ 1456 do { \ 1457 u32 n = (_n); \ 1458 if (IXGBE_ATR_COMMON_HASH_KEY & (0x01 << n)) \ 1459 common_hash ^= lo_hash_dword >> n; \ 1460 else if (IXGBE_ATR_BUCKET_HASH_KEY & (0x01 << n)) \ 1461 bucket_hash ^= lo_hash_dword >> n; \ 1462 else if (IXGBE_ATR_SIGNATURE_HASH_KEY & (0x01 << n)) \ 1463 sig_hash ^= lo_hash_dword << (16 - n); \ 1464 if (IXGBE_ATR_COMMON_HASH_KEY & (0x01 << (n + 16))) \ 1465 common_hash ^= hi_hash_dword >> n; \ 1466 else if (IXGBE_ATR_BUCKET_HASH_KEY & (0x01 << (n + 16))) \ 1467 bucket_hash ^= hi_hash_dword >> n; \ 1468 else if (IXGBE_ATR_SIGNATURE_HASH_KEY & (0x01 << (n + 16))) \ 1469 sig_hash ^= hi_hash_dword << (16 - n); \ 1470 } while (0) 1471 1472 /** 1473 * ixgbe_atr_compute_sig_hash_82599 - Compute the signature hash 1474 * @input: input bitstream to compute the hash on 1475 * @common: compressed common input dword 1476 * 1477 * This function is almost identical to the function above but contains 1478 * several optimizations such as unwinding all of the loops, letting the 1479 * compiler work out all of the conditional ifs since the keys are static 1480 * defines, and computing two keys at once since the hashed dword stream 1481 * will be the same for both keys. 1482 **/ 1483 u32 ixgbe_atr_compute_sig_hash_82599(union ixgbe_atr_hash_dword input, 1484 union ixgbe_atr_hash_dword common) 1485 { 1486 u32 hi_hash_dword, lo_hash_dword, flow_vm_vlan; 1487 u32 sig_hash = 0, bucket_hash = 0, common_hash = 0; 1488 1489 /* record the flow_vm_vlan bits as they are a key part to the hash */ 1490 flow_vm_vlan = IXGBE_NTOHL(input.dword); 1491 1492 /* generate common hash dword */ 1493 hi_hash_dword = IXGBE_NTOHL(common.dword); 1494 1495 /* low dword is word swapped version of common */ 1496 lo_hash_dword = (hi_hash_dword >> 16) | (hi_hash_dword << 16); 1497 1498 /* apply flow ID/VM pool/VLAN ID bits to hash words */ 1499 hi_hash_dword ^= flow_vm_vlan ^ (flow_vm_vlan >> 16); 1500 1501 /* Process bits 0 and 16 */ 1502 IXGBE_COMPUTE_SIG_HASH_ITERATION(0); 1503 1504 /* 1505 * apply flow ID/VM pool/VLAN ID bits to lo hash dword, we had to 1506 * delay this because bit 0 of the stream should not be processed 1507 * so we do not add the VLAN until after bit 0 was processed 1508 */ 1509 lo_hash_dword ^= flow_vm_vlan ^ (flow_vm_vlan << 16); 1510 1511 /* Process remaining 30 bit of the key */ 1512 IXGBE_COMPUTE_SIG_HASH_ITERATION(1); 1513 IXGBE_COMPUTE_SIG_HASH_ITERATION(2); 1514 IXGBE_COMPUTE_SIG_HASH_ITERATION(3); 1515 IXGBE_COMPUTE_SIG_HASH_ITERATION(4); 1516 IXGBE_COMPUTE_SIG_HASH_ITERATION(5); 1517 IXGBE_COMPUTE_SIG_HASH_ITERATION(6); 1518 IXGBE_COMPUTE_SIG_HASH_ITERATION(7); 1519 IXGBE_COMPUTE_SIG_HASH_ITERATION(8); 1520 IXGBE_COMPUTE_SIG_HASH_ITERATION(9); 1521 IXGBE_COMPUTE_SIG_HASH_ITERATION(10); 1522 IXGBE_COMPUTE_SIG_HASH_ITERATION(11); 1523 IXGBE_COMPUTE_SIG_HASH_ITERATION(12); 1524 IXGBE_COMPUTE_SIG_HASH_ITERATION(13); 1525 IXGBE_COMPUTE_SIG_HASH_ITERATION(14); 1526 IXGBE_COMPUTE_SIG_HASH_ITERATION(15); 1527 1528 /* combine common_hash result with signature and bucket hashes */ 1529 bucket_hash ^= common_hash; 1530 bucket_hash &= IXGBE_ATR_HASH_MASK; 1531 1532 sig_hash ^= common_hash << 16; 1533 sig_hash &= IXGBE_ATR_HASH_MASK << 16; 1534 1535 /* return completed signature hash */ 1536 return sig_hash ^ bucket_hash; 1537 } 1538 1539 /** 1540 * ixgbe_fdir_add_signature_filter_82599 - Adds a signature hash filter 1541 * @hw: pointer to hardware structure 1542 * @input: unique input dword 1543 * @common: compressed common input dword 1544 * @queue: queue index to direct traffic to 1545 * 1546 * Note that the tunnel bit in input must not be set when the hardware 1547 * tunneling support does not exist. 1548 **/ 1549 void ixgbe_fdir_add_signature_filter_82599(struct ixgbe_hw *hw, 1550 union ixgbe_atr_hash_dword input, 1551 union ixgbe_atr_hash_dword common, 1552 u8 queue) 1553 { 1554 u64 fdirhashcmd; 1555 u8 flow_type; 1556 bool tunnel; 1557 u32 fdircmd; 1558 1559 DEBUGFUNC("ixgbe_fdir_add_signature_filter_82599"); 1560 1561 /* 1562 * Get the flow_type in order to program FDIRCMD properly 1563 * lowest 2 bits are FDIRCMD.L4TYPE, third lowest bit is FDIRCMD.IPV6 1564 * fifth is FDIRCMD.TUNNEL_FILTER 1565 */ 1566 tunnel = !!(input.formatted.flow_type & IXGBE_ATR_L4TYPE_TUNNEL_MASK); 1567 flow_type = input.formatted.flow_type & 1568 (IXGBE_ATR_L4TYPE_TUNNEL_MASK - 1); 1569 switch (flow_type) { 1570 case IXGBE_ATR_FLOW_TYPE_TCPV4: 1571 case IXGBE_ATR_FLOW_TYPE_UDPV4: 1572 case IXGBE_ATR_FLOW_TYPE_SCTPV4: 1573 case IXGBE_ATR_FLOW_TYPE_TCPV6: 1574 case IXGBE_ATR_FLOW_TYPE_UDPV6: 1575 case IXGBE_ATR_FLOW_TYPE_SCTPV6: 1576 break; 1577 default: 1578 DEBUGOUT(" Error on flow type input\n"); 1579 return; 1580 } 1581 1582 /* configure FDIRCMD register */ 1583 fdircmd = IXGBE_FDIRCMD_CMD_ADD_FLOW | IXGBE_FDIRCMD_FILTER_UPDATE | 1584 IXGBE_FDIRCMD_LAST | IXGBE_FDIRCMD_QUEUE_EN; 1585 fdircmd |= (u32)flow_type << IXGBE_FDIRCMD_FLOW_TYPE_SHIFT; 1586 fdircmd |= (u32)queue << IXGBE_FDIRCMD_RX_QUEUE_SHIFT; 1587 if (tunnel) 1588 fdircmd |= IXGBE_FDIRCMD_TUNNEL_FILTER; 1589 1590 /* 1591 * The lower 32-bits of fdirhashcmd is for FDIRHASH, the upper 32-bits 1592 * is for FDIRCMD. Then do a 64-bit register write from FDIRHASH. 1593 */ 1594 fdirhashcmd = (u64)fdircmd << 32; 1595 fdirhashcmd |= (u64)ixgbe_atr_compute_sig_hash_82599(input, common); 1596 IXGBE_WRITE_REG64(hw, IXGBE_FDIRHASH, fdirhashcmd); 1597 1598 DEBUGOUT2("Tx Queue=%x hash=%x\n", queue, (u32)fdirhashcmd); 1599 1600 return; 1601 } 1602 1603 #define IXGBE_COMPUTE_BKT_HASH_ITERATION(_n) \ 1604 do { \ 1605 u32 n = (_n); \ 1606 if (IXGBE_ATR_BUCKET_HASH_KEY & (0x01 << n)) \ 1607 bucket_hash ^= lo_hash_dword >> n; \ 1608 if (IXGBE_ATR_BUCKET_HASH_KEY & (0x01 << (n + 16))) \ 1609 bucket_hash ^= hi_hash_dword >> n; \ 1610 } while (0) 1611 1612 /** 1613 * ixgbe_atr_compute_perfect_hash_82599 - Compute the perfect filter hash 1614 * @input: input bitstream to compute the hash on 1615 * @input_mask: mask for the input bitstream 1616 * 1617 * This function serves two main purposes. First it applies the input_mask 1618 * to the atr_input resulting in a cleaned up atr_input data stream. 1619 * Secondly it computes the hash and stores it in the bkt_hash field at 1620 * the end of the input byte stream. This way it will be available for 1621 * future use without needing to recompute the hash. 1622 **/ 1623 void ixgbe_atr_compute_perfect_hash_82599(union ixgbe_atr_input *input, 1624 union ixgbe_atr_input *input_mask) 1625 { 1626 1627 u32 hi_hash_dword, lo_hash_dword, flow_vm_vlan; 1628 u32 bucket_hash = 0; 1629 u32 hi_dword = 0; 1630 u32 i = 0; 1631 1632 /* Apply masks to input data */ 1633 for (i = 0; i < 14; i++) 1634 input->dword_stream[i] &= input_mask->dword_stream[i]; 1635 1636 /* record the flow_vm_vlan bits as they are a key part to the hash */ 1637 flow_vm_vlan = IXGBE_NTOHL(input->dword_stream[0]); 1638 1639 /* generate common hash dword */ 1640 for (i = 1; i <= 13; i++) 1641 hi_dword ^= input->dword_stream[i]; 1642 hi_hash_dword = IXGBE_NTOHL(hi_dword); 1643 1644 /* low dword is word swapped version of common */ 1645 lo_hash_dword = (hi_hash_dword >> 16) | (hi_hash_dword << 16); 1646 1647 /* apply flow ID/VM pool/VLAN ID bits to hash words */ 1648 hi_hash_dword ^= flow_vm_vlan ^ (flow_vm_vlan >> 16); 1649 1650 /* Process bits 0 and 16 */ 1651 IXGBE_COMPUTE_BKT_HASH_ITERATION(0); 1652 1653 /* 1654 * apply flow ID/VM pool/VLAN ID bits to lo hash dword, we had to 1655 * delay this because bit 0 of the stream should not be processed 1656 * so we do not add the VLAN until after bit 0 was processed 1657 */ 1658 lo_hash_dword ^= flow_vm_vlan ^ (flow_vm_vlan << 16); 1659 1660 /* Process remaining 30 bit of the key */ 1661 for (i = 1; i <= 15; i++) 1662 IXGBE_COMPUTE_BKT_HASH_ITERATION(i); 1663 1664 /* 1665 * Limit hash to 13 bits since max bucket count is 8K. 1666 * Store result at the end of the input stream. 1667 */ 1668 input->formatted.bkt_hash = bucket_hash & 0x1FFF; 1669 } 1670 1671 /** 1672 * ixgbe_get_fdirtcpm_82599 - generate a TCP port from atr_input_masks 1673 * @input_mask: mask to be bit swapped 1674 * 1675 * The source and destination port masks for flow director are bit swapped 1676 * in that bit 15 effects bit 0, 14 effects 1, 13, 2 etc. In order to 1677 * generate a correctly swapped value we need to bit swap the mask and that 1678 * is what is accomplished by this function. 1679 **/ 1680 static u32 ixgbe_get_fdirtcpm_82599(union ixgbe_atr_input *input_mask) 1681 { 1682 u32 mask = IXGBE_NTOHS(input_mask->formatted.dst_port); 1683 mask <<= IXGBE_FDIRTCPM_DPORTM_SHIFT; 1684 mask |= (u32)IXGBE_NTOHS(input_mask->formatted.src_port); 1685 mask = ((mask & 0x55555555) << 1) | ((mask & 0xAAAAAAAA) >> 1); 1686 mask = ((mask & 0x33333333) << 2) | ((mask & 0xCCCCCCCC) >> 2); 1687 mask = ((mask & 0x0F0F0F0F) << 4) | ((mask & 0xF0F0F0F0) >> 4); 1688 return ((mask & 0x00FF00FF) << 8) | ((mask & 0xFF00FF00) >> 8); 1689 } 1690 1691 /* 1692 * These two macros are meant to address the fact that we have registers 1693 * that are either all or in part big-endian. As a result on big-endian 1694 * systems we will end up byte swapping the value to little-endian before 1695 * it is byte swapped again and written to the hardware in the original 1696 * big-endian format. 1697 */ 1698 #define IXGBE_STORE_AS_BE32(_value) \ 1699 (((u32)(_value) >> 24) | (((u32)(_value) & 0x00FF0000) >> 8) | \ 1700 (((u32)(_value) & 0x0000FF00) << 8) | ((u32)(_value) << 24)) 1701 1702 #define IXGBE_WRITE_REG_BE32(a, reg, value) \ 1703 IXGBE_WRITE_REG((a), (reg), IXGBE_STORE_AS_BE32(IXGBE_NTOHL(value))) 1704 1705 #define IXGBE_STORE_AS_BE16(_value) \ 1706 IXGBE_NTOHS(((u16)(_value) >> 8) | ((u16)(_value) << 8)) 1707 1708 s32 ixgbe_fdir_set_input_mask_82599(struct ixgbe_hw *hw, 1709 union ixgbe_atr_input *input_mask, bool cloud_mode) 1710 { 1711 /* mask IPv6 since it is currently not supported */ 1712 u32 fdirm = IXGBE_FDIRM_DIPv6; 1713 u32 fdirtcpm; 1714 u32 fdirip6m; 1715 UNREFERENCED_1PARAMETER(cloud_mode); 1716 DEBUGFUNC("ixgbe_fdir_set_atr_input_mask_82599"); 1717 1718 /* 1719 * Program the relevant mask registers. If src/dst_port or src/dst_addr 1720 * are zero, then assume a full mask for that field. Also assume that 1721 * a VLAN of 0 is unspecified, so mask that out as well. L4type 1722 * cannot be masked out in this implementation. 1723 * 1724 * This also assumes IPv4 only. IPv6 masking isn't supported at this 1725 * point in time. 1726 */ 1727 1728 /* verify bucket hash is cleared on hash generation */ 1729 if (input_mask->formatted.bkt_hash) 1730 DEBUGOUT(" bucket hash should always be 0 in mask\n"); 1731 1732 /* Program FDIRM and verify partial masks */ 1733 switch (input_mask->formatted.vm_pool & 0x7F) { 1734 case 0x0: 1735 fdirm |= IXGBE_FDIRM_POOL; 1736 case 0x7F: 1737 break; 1738 default: 1739 DEBUGOUT(" Error on vm pool mask\n"); 1740 return IXGBE_ERR_CONFIG; 1741 } 1742 1743 switch (input_mask->formatted.flow_type & IXGBE_ATR_L4TYPE_MASK) { 1744 case 0x0: 1745 fdirm |= IXGBE_FDIRM_L4P; 1746 if (input_mask->formatted.dst_port || 1747 input_mask->formatted.src_port) { 1748 DEBUGOUT(" Error on src/dst port mask\n"); 1749 return IXGBE_ERR_CONFIG; 1750 } 1751 case IXGBE_ATR_L4TYPE_MASK: 1752 break; 1753 default: 1754 DEBUGOUT(" Error on flow type mask\n"); 1755 return IXGBE_ERR_CONFIG; 1756 } 1757 1758 switch (IXGBE_NTOHS(input_mask->formatted.vlan_id) & 0xEFFF) { 1759 case 0x0000: 1760 /* mask VLAN ID */ 1761 fdirm |= IXGBE_FDIRM_VLANID; 1762 /* mask VLAN priority */ 1763 fdirm |= IXGBE_FDIRM_VLANP; 1764 break; 1765 case 0x0FFF: 1766 /* mask VLAN priority */ 1767 fdirm |= IXGBE_FDIRM_VLANP; 1768 break; 1769 case 0xE000: 1770 /* mask VLAN ID only */ 1771 fdirm |= IXGBE_FDIRM_VLANID; 1772 /* fall through */ 1773 case 0xEFFF: 1774 /* no VLAN fields masked */ 1775 break; 1776 default: 1777 DEBUGOUT(" Error on VLAN mask\n"); 1778 return IXGBE_ERR_CONFIG; 1779 } 1780 1781 switch (input_mask->formatted.flex_bytes & 0xFFFF) { 1782 case 0x0000: 1783 /* Mask Flex Bytes */ 1784 fdirm |= IXGBE_FDIRM_FLEX; 1785 /* fall through */ 1786 case 0xFFFF: 1787 break; 1788 default: 1789 DEBUGOUT(" Error on flexible byte mask\n"); 1790 return IXGBE_ERR_CONFIG; 1791 } 1792 1793 if (cloud_mode) { 1794 fdirm |= IXGBE_FDIRM_L3P; 1795 fdirip6m = ((u32) 0xFFFFU << IXGBE_FDIRIP6M_DIPM_SHIFT); 1796 fdirip6m |= IXGBE_FDIRIP6M_ALWAYS_MASK; 1797 1798 switch (input_mask->formatted.inner_mac[0] & 0xFF) { 1799 case 0x00: 1800 /* Mask inner MAC, fall through */ 1801 fdirip6m |= IXGBE_FDIRIP6M_INNER_MAC; 1802 case 0xFF: 1803 break; 1804 default: 1805 DEBUGOUT(" Error on inner_mac byte mask\n"); 1806 return IXGBE_ERR_CONFIG; 1807 } 1808 1809 switch (input_mask->formatted.tni_vni & 0xFFFFFFFF) { 1810 case 0x0: 1811 /* Mask vxlan id */ 1812 fdirip6m |= IXGBE_FDIRIP6M_TNI_VNI; 1813 break; 1814 case 0x00FFFFFF: 1815 fdirip6m |= IXGBE_FDIRIP6M_TNI_VNI_24; 1816 break; 1817 case 0xFFFFFFFF: 1818 break; 1819 default: 1820 DEBUGOUT(" Error on TNI/VNI byte mask\n"); 1821 return IXGBE_ERR_CONFIG; 1822 } 1823 1824 switch (input_mask->formatted.tunnel_type & 0xFFFF) { 1825 case 0x0: 1826 /* Mask turnnel type, fall through */ 1827 fdirip6m |= IXGBE_FDIRIP6M_TUNNEL_TYPE; 1828 case 0xFFFF: 1829 break; 1830 default: 1831 DEBUGOUT(" Error on tunnel type byte mask\n"); 1832 return IXGBE_ERR_CONFIG; 1833 } 1834 IXGBE_WRITE_REG_BE32(hw, IXGBE_FDIRIP6M, fdirip6m); 1835 1836 /* Set all bits in FDIRTCPM, FDIRUDPM, FDIRSCTPM, 1837 * FDIRSIP4M and FDIRDIP4M in cloud mode to allow 1838 * L3/L3 packets to tunnel. 1839 */ 1840 IXGBE_WRITE_REG(hw, IXGBE_FDIRTCPM, 0xFFFFFFFF); 1841 IXGBE_WRITE_REG(hw, IXGBE_FDIRUDPM, 0xFFFFFFFF); 1842 IXGBE_WRITE_REG_BE32(hw, IXGBE_FDIRDIP4M, 0xFFFFFFFF); 1843 IXGBE_WRITE_REG_BE32(hw, IXGBE_FDIRSIP4M, 0xFFFFFFFF); 1844 switch (hw->mac.type) { 1845 case ixgbe_mac_X550: 1846 case ixgbe_mac_X550EM_x: 1847 case ixgbe_mac_X550EM_a: 1848 IXGBE_WRITE_REG(hw, IXGBE_FDIRSCTPM, 0xFFFFFFFF); 1849 break; 1850 default: 1851 break; 1852 } 1853 } 1854 1855 /* Now mask VM pool and destination IPv6 - bits 5 and 2 */ 1856 IXGBE_WRITE_REG(hw, IXGBE_FDIRM, fdirm); 1857 1858 if (!cloud_mode) { 1859 /* store the TCP/UDP port masks, bit reversed from port 1860 * layout */ 1861 fdirtcpm = ixgbe_get_fdirtcpm_82599(input_mask); 1862 1863 /* write both the same so that UDP and TCP use the same mask */ 1864 IXGBE_WRITE_REG(hw, IXGBE_FDIRTCPM, ~fdirtcpm); 1865 IXGBE_WRITE_REG(hw, IXGBE_FDIRUDPM, ~fdirtcpm); 1866 /* also use it for SCTP */ 1867 switch (hw->mac.type) { 1868 case ixgbe_mac_X550: 1869 case ixgbe_mac_X550EM_x: 1870 case ixgbe_mac_X550EM_a: 1871 IXGBE_WRITE_REG(hw, IXGBE_FDIRSCTPM, ~fdirtcpm); 1872 break; 1873 default: 1874 break; 1875 } 1876 1877 /* store source and destination IP masks (big-enian) */ 1878 IXGBE_WRITE_REG_BE32(hw, IXGBE_FDIRSIP4M, 1879 ~input_mask->formatted.src_ip[0]); 1880 IXGBE_WRITE_REG_BE32(hw, IXGBE_FDIRDIP4M, 1881 ~input_mask->formatted.dst_ip[0]); 1882 IXGBE_WRITE_REG_BE32(hw, IXGBE_FDIRIP6M, 0xFFFFFFFF); 1883 } 1884 return IXGBE_SUCCESS; 1885 } 1886 1887 s32 ixgbe_fdir_write_perfect_filter_82599(struct ixgbe_hw *hw, 1888 union ixgbe_atr_input *input, 1889 u16 soft_id, u8 queue, bool cloud_mode) 1890 { 1891 u32 fdirport, fdirvlan, fdirhash, fdircmd; 1892 u32 addr_low, addr_high; 1893 u32 cloud_type = 0; 1894 s32 err; 1895 UNREFERENCED_1PARAMETER(cloud_mode); 1896 1897 DEBUGFUNC("ixgbe_fdir_write_perfect_filter_82599"); 1898 if (!cloud_mode) { 1899 /* currently IPv6 is not supported, must be programmed with 0 */ 1900 IXGBE_WRITE_REG_BE32(hw, IXGBE_FDIRSIPv6(0), 1901 input->formatted.src_ip[0]); 1902 IXGBE_WRITE_REG_BE32(hw, IXGBE_FDIRSIPv6(1), 1903 input->formatted.src_ip[1]); 1904 IXGBE_WRITE_REG_BE32(hw, IXGBE_FDIRSIPv6(2), 1905 input->formatted.src_ip[2]); 1906 1907 /* record the source address (big-endian) */ 1908 IXGBE_WRITE_REG_BE32(hw, IXGBE_FDIRIPSA, 1909 input->formatted.src_ip[0]); 1910 1911 /* record the first 32 bits of the destination address 1912 * (big-endian) */ 1913 IXGBE_WRITE_REG_BE32(hw, IXGBE_FDIRIPDA, 1914 input->formatted.dst_ip[0]); 1915 1916 /* record source and destination port (little-endian)*/ 1917 fdirport = IXGBE_NTOHS(input->formatted.dst_port); 1918 fdirport <<= IXGBE_FDIRPORT_DESTINATION_SHIFT; 1919 fdirport |= (u32)IXGBE_NTOHS(input->formatted.src_port); 1920 IXGBE_WRITE_REG(hw, IXGBE_FDIRPORT, fdirport); 1921 } 1922 1923 /* record VLAN (little-endian) and flex_bytes(big-endian) */ 1924 fdirvlan = IXGBE_STORE_AS_BE16(input->formatted.flex_bytes); 1925 fdirvlan <<= IXGBE_FDIRVLAN_FLEX_SHIFT; 1926 fdirvlan |= (u32)IXGBE_NTOHS(input->formatted.vlan_id); 1927 IXGBE_WRITE_REG(hw, IXGBE_FDIRVLAN, fdirvlan); 1928 1929 if (cloud_mode) { 1930 if (input->formatted.tunnel_type != 0) 1931 cloud_type = 0x80000000; 1932 1933 addr_low = ((u32)input->formatted.inner_mac[0] | 1934 ((u32)input->formatted.inner_mac[1] << 8) | 1935 ((u32)input->formatted.inner_mac[2] << 16) | 1936 ((u32)input->formatted.inner_mac[3] << 24)); 1937 addr_high = ((u32)input->formatted.inner_mac[4] | 1938 ((u32)input->formatted.inner_mac[5] << 8)); 1939 cloud_type |= addr_high; 1940 IXGBE_WRITE_REG_BE32(hw, IXGBE_FDIRSIPv6(0), addr_low); 1941 IXGBE_WRITE_REG_BE32(hw, IXGBE_FDIRSIPv6(1), cloud_type); 1942 IXGBE_WRITE_REG_BE32(hw, IXGBE_FDIRSIPv6(2), input->formatted.tni_vni); 1943 } 1944 1945 /* configure FDIRHASH register */ 1946 fdirhash = input->formatted.bkt_hash; 1947 fdirhash |= soft_id << IXGBE_FDIRHASH_SIG_SW_INDEX_SHIFT; 1948 IXGBE_WRITE_REG(hw, IXGBE_FDIRHASH, fdirhash); 1949 1950 /* 1951 * flush all previous writes to make certain registers are 1952 * programmed prior to issuing the command 1953 */ 1954 IXGBE_WRITE_FLUSH(hw); 1955 1956 /* configure FDIRCMD register */ 1957 fdircmd = IXGBE_FDIRCMD_CMD_ADD_FLOW | IXGBE_FDIRCMD_FILTER_UPDATE | 1958 IXGBE_FDIRCMD_LAST | IXGBE_FDIRCMD_QUEUE_EN; 1959 if (queue == IXGBE_FDIR_DROP_QUEUE) 1960 fdircmd |= IXGBE_FDIRCMD_DROP; 1961 if (input->formatted.flow_type & IXGBE_ATR_L4TYPE_TUNNEL_MASK) 1962 fdircmd |= IXGBE_FDIRCMD_TUNNEL_FILTER; 1963 fdircmd |= input->formatted.flow_type << IXGBE_FDIRCMD_FLOW_TYPE_SHIFT; 1964 fdircmd |= (u32)queue << IXGBE_FDIRCMD_RX_QUEUE_SHIFT; 1965 fdircmd |= (u32)input->formatted.vm_pool << IXGBE_FDIRCMD_VT_POOL_SHIFT; 1966 1967 IXGBE_WRITE_REG(hw, IXGBE_FDIRCMD, fdircmd); 1968 err = ixgbe_fdir_check_cmd_complete(hw, &fdircmd); 1969 if (err) { 1970 DEBUGOUT("Flow Director command did not complete!\n"); 1971 return err; 1972 } 1973 1974 return IXGBE_SUCCESS; 1975 } 1976 1977 s32 ixgbe_fdir_erase_perfect_filter_82599(struct ixgbe_hw *hw, 1978 union ixgbe_atr_input *input, 1979 u16 soft_id) 1980 { 1981 u32 fdirhash; 1982 u32 fdircmd; 1983 s32 err; 1984 1985 /* configure FDIRHASH register */ 1986 fdirhash = input->formatted.bkt_hash; 1987 fdirhash |= soft_id << IXGBE_FDIRHASH_SIG_SW_INDEX_SHIFT; 1988 IXGBE_WRITE_REG(hw, IXGBE_FDIRHASH, fdirhash); 1989 1990 /* flush hash to HW */ 1991 IXGBE_WRITE_FLUSH(hw); 1992 1993 /* Query if filter is present */ 1994 IXGBE_WRITE_REG(hw, IXGBE_FDIRCMD, IXGBE_FDIRCMD_CMD_QUERY_REM_FILT); 1995 1996 err = ixgbe_fdir_check_cmd_complete(hw, &fdircmd); 1997 if (err) { 1998 DEBUGOUT("Flow Director command did not complete!\n"); 1999 return err; 2000 } 2001 2002 /* if filter exists in hardware then remove it */ 2003 if (fdircmd & IXGBE_FDIRCMD_FILTER_VALID) { 2004 IXGBE_WRITE_REG(hw, IXGBE_FDIRHASH, fdirhash); 2005 IXGBE_WRITE_FLUSH(hw); 2006 IXGBE_WRITE_REG(hw, IXGBE_FDIRCMD, 2007 IXGBE_FDIRCMD_CMD_REMOVE_FLOW); 2008 } 2009 2010 return IXGBE_SUCCESS; 2011 } 2012 2013 /** 2014 * ixgbe_fdir_add_perfect_filter_82599 - Adds a perfect filter 2015 * @hw: pointer to hardware structure 2016 * @input: input bitstream 2017 * @input_mask: mask for the input bitstream 2018 * @soft_id: software index for the filters 2019 * @queue: queue index to direct traffic to 2020 * @cloud_mode: unused 2021 * 2022 * Note that the caller to this function must lock before calling, since the 2023 * hardware writes must be protected from one another. 2024 **/ 2025 s32 ixgbe_fdir_add_perfect_filter_82599(struct ixgbe_hw *hw, 2026 union ixgbe_atr_input *input, 2027 union ixgbe_atr_input *input_mask, 2028 u16 soft_id, u8 queue, bool cloud_mode) 2029 { 2030 s32 err = IXGBE_ERR_CONFIG; 2031 UNREFERENCED_1PARAMETER(cloud_mode); 2032 2033 DEBUGFUNC("ixgbe_fdir_add_perfect_filter_82599"); 2034 2035 /* 2036 * Check flow_type formatting, and bail out before we touch the hardware 2037 * if there's a configuration issue 2038 */ 2039 switch (input->formatted.flow_type) { 2040 case IXGBE_ATR_FLOW_TYPE_IPV4: 2041 case IXGBE_ATR_FLOW_TYPE_TUNNELED_IPV4: 2042 input_mask->formatted.flow_type = IXGBE_ATR_L4TYPE_IPV6_MASK; 2043 if (input->formatted.dst_port || input->formatted.src_port) { 2044 DEBUGOUT(" Error on src/dst port\n"); 2045 return IXGBE_ERR_CONFIG; 2046 } 2047 break; 2048 case IXGBE_ATR_FLOW_TYPE_SCTPV4: 2049 case IXGBE_ATR_FLOW_TYPE_TUNNELED_SCTPV4: 2050 if (input->formatted.dst_port || input->formatted.src_port) { 2051 DEBUGOUT(" Error on src/dst port\n"); 2052 return IXGBE_ERR_CONFIG; 2053 } 2054 input_mask->formatted.flow_type = IXGBE_ATR_L4TYPE_IPV6_MASK | 2055 IXGBE_ATR_L4TYPE_MASK; 2056 break; 2057 case IXGBE_ATR_FLOW_TYPE_TCPV4: 2058 case IXGBE_ATR_FLOW_TYPE_TUNNELED_TCPV4: 2059 case IXGBE_ATR_FLOW_TYPE_UDPV4: 2060 case IXGBE_ATR_FLOW_TYPE_TUNNELED_UDPV4: 2061 input_mask->formatted.flow_type = IXGBE_ATR_L4TYPE_IPV6_MASK | 2062 IXGBE_ATR_L4TYPE_MASK; 2063 break; 2064 default: 2065 DEBUGOUT(" Error on flow type input\n"); 2066 return err; 2067 } 2068 2069 /* program input mask into the HW */ 2070 err = ixgbe_fdir_set_input_mask_82599(hw, input_mask, cloud_mode); 2071 if (err) 2072 return err; 2073 2074 /* apply mask and compute/store hash */ 2075 ixgbe_atr_compute_perfect_hash_82599(input, input_mask); 2076 2077 /* program filters to filter memory */ 2078 return ixgbe_fdir_write_perfect_filter_82599(hw, input, 2079 soft_id, queue, cloud_mode); 2080 } 2081 2082 /** 2083 * ixgbe_read_analog_reg8_82599 - Reads 8 bit Omer analog register 2084 * @hw: pointer to hardware structure 2085 * @reg: analog register to read 2086 * @val: read value 2087 * 2088 * Performs read operation to Omer analog register specified. 2089 **/ 2090 s32 ixgbe_read_analog_reg8_82599(struct ixgbe_hw *hw, u32 reg, u8 *val) 2091 { 2092 u32 core_ctl; 2093 2094 DEBUGFUNC("ixgbe_read_analog_reg8_82599"); 2095 2096 IXGBE_WRITE_REG(hw, IXGBE_CORECTL, IXGBE_CORECTL_WRITE_CMD | 2097 (reg << 8)); 2098 IXGBE_WRITE_FLUSH(hw); 2099 usec_delay(10); 2100 core_ctl = IXGBE_READ_REG(hw, IXGBE_CORECTL); 2101 *val = (u8)core_ctl; 2102 2103 return IXGBE_SUCCESS; 2104 } 2105 2106 /** 2107 * ixgbe_write_analog_reg8_82599 - Writes 8 bit Omer analog register 2108 * @hw: pointer to hardware structure 2109 * @reg: atlas register to write 2110 * @val: value to write 2111 * 2112 * Performs write operation to Omer analog register specified. 2113 **/ 2114 s32 ixgbe_write_analog_reg8_82599(struct ixgbe_hw *hw, u32 reg, u8 val) 2115 { 2116 u32 core_ctl; 2117 2118 DEBUGFUNC("ixgbe_write_analog_reg8_82599"); 2119 2120 core_ctl = (reg << 8) | val; 2121 IXGBE_WRITE_REG(hw, IXGBE_CORECTL, core_ctl); 2122 IXGBE_WRITE_FLUSH(hw); 2123 usec_delay(10); 2124 2125 return IXGBE_SUCCESS; 2126 } 2127 2128 /** 2129 * ixgbe_start_hw_82599 - Prepare hardware for Tx/Rx 2130 * @hw: pointer to hardware structure 2131 * 2132 * Starts the hardware using the generic start_hw function 2133 * and the generation start_hw function. 2134 * Then performs revision-specific operations, if any. 2135 **/ 2136 s32 ixgbe_start_hw_82599(struct ixgbe_hw *hw) 2137 { 2138 s32 ret_val = IXGBE_SUCCESS; 2139 2140 DEBUGFUNC("ixgbe_start_hw_82599"); 2141 2142 ret_val = ixgbe_start_hw_generic(hw); 2143 if (ret_val != IXGBE_SUCCESS) 2144 goto out; 2145 2146 ixgbe_start_hw_gen2(hw); 2147 2148 /* We need to run link autotry after the driver loads */ 2149 hw->mac.autotry_restart = true; 2150 2151 if (ret_val == IXGBE_SUCCESS) 2152 ret_val = ixgbe_verify_fw_version_82599(hw); 2153 out: 2154 return ret_val; 2155 } 2156 2157 /** 2158 * ixgbe_identify_phy_82599 - Get physical layer module 2159 * @hw: pointer to hardware structure 2160 * 2161 * Determines the physical layer module found on the current adapter. 2162 * If PHY already detected, maintains current PHY type in hw struct, 2163 * otherwise executes the PHY detection routine. 2164 **/ 2165 s32 ixgbe_identify_phy_82599(struct ixgbe_hw *hw) 2166 { 2167 s32 status; 2168 2169 DEBUGFUNC("ixgbe_identify_phy_82599"); 2170 2171 /* Detect PHY if not unknown - returns success if already detected. */ 2172 status = ixgbe_identify_phy_generic(hw); 2173 if (status != IXGBE_SUCCESS) { 2174 /* 82599 10GBASE-T requires an external PHY */ 2175 if (hw->mac.ops.get_media_type(hw) == ixgbe_media_type_copper) 2176 return status; 2177 else 2178 status = ixgbe_identify_module_generic(hw); 2179 } 2180 2181 /* Set PHY type none if no PHY detected */ 2182 if (hw->phy.type == ixgbe_phy_unknown) { 2183 hw->phy.type = ixgbe_phy_none; 2184 return IXGBE_SUCCESS; 2185 } 2186 2187 /* Return error if SFP module has been detected but is not supported */ 2188 if (hw->phy.type == ixgbe_phy_sfp_unsupported) 2189 return IXGBE_ERR_SFP_NOT_SUPPORTED; 2190 2191 return status; 2192 } 2193 2194 /** 2195 * ixgbe_get_supported_physical_layer_82599 - Returns physical layer type 2196 * @hw: pointer to hardware structure 2197 * 2198 * Determines physical layer capabilities of the current configuration. 2199 **/ 2200 u64 ixgbe_get_supported_physical_layer_82599(struct ixgbe_hw *hw) 2201 { 2202 u64 physical_layer = IXGBE_PHYSICAL_LAYER_UNKNOWN; 2203 u32 autoc = IXGBE_READ_REG(hw, IXGBE_AUTOC); 2204 u32 autoc2 = IXGBE_READ_REG(hw, IXGBE_AUTOC2); 2205 u32 pma_pmd_10g_serial = autoc2 & IXGBE_AUTOC2_10G_SERIAL_PMA_PMD_MASK; 2206 u32 pma_pmd_10g_parallel = autoc & IXGBE_AUTOC_10G_PMA_PMD_MASK; 2207 u32 pma_pmd_1g = autoc & IXGBE_AUTOC_1G_PMA_PMD_MASK; 2208 u16 ext_ability = 0; 2209 2210 DEBUGFUNC("ixgbe_get_support_physical_layer_82599"); 2211 2212 hw->phy.ops.identify(hw); 2213 2214 switch (hw->phy.type) { 2215 case ixgbe_phy_tn: 2216 case ixgbe_phy_cu_unknown: 2217 hw->phy.ops.read_reg(hw, IXGBE_MDIO_PHY_EXT_ABILITY, 2218 IXGBE_MDIO_PMA_PMD_DEV_TYPE, &ext_ability); 2219 if (ext_ability & IXGBE_MDIO_PHY_10GBASET_ABILITY) 2220 physical_layer |= IXGBE_PHYSICAL_LAYER_10GBASE_T; 2221 if (ext_ability & IXGBE_MDIO_PHY_1000BASET_ABILITY) 2222 physical_layer |= IXGBE_PHYSICAL_LAYER_1000BASE_T; 2223 if (ext_ability & IXGBE_MDIO_PHY_100BASETX_ABILITY) 2224 physical_layer |= IXGBE_PHYSICAL_LAYER_100BASE_TX; 2225 goto out; 2226 default: 2227 break; 2228 } 2229 2230 switch (autoc & IXGBE_AUTOC_LMS_MASK) { 2231 case IXGBE_AUTOC_LMS_1G_AN: 2232 case IXGBE_AUTOC_LMS_1G_LINK_NO_AN: 2233 if (pma_pmd_1g == IXGBE_AUTOC_1G_KX_BX) { 2234 physical_layer = IXGBE_PHYSICAL_LAYER_1000BASE_KX | 2235 IXGBE_PHYSICAL_LAYER_1000BASE_BX; 2236 goto out; 2237 } else 2238 /* SFI mode so read SFP module */ 2239 goto sfp_check; 2240 break; 2241 case IXGBE_AUTOC_LMS_10G_LINK_NO_AN: 2242 if (pma_pmd_10g_parallel == IXGBE_AUTOC_10G_CX4) 2243 physical_layer = IXGBE_PHYSICAL_LAYER_10GBASE_CX4; 2244 else if (pma_pmd_10g_parallel == IXGBE_AUTOC_10G_KX4) 2245 physical_layer = IXGBE_PHYSICAL_LAYER_10GBASE_KX4; 2246 else if (pma_pmd_10g_parallel == IXGBE_AUTOC_10G_XAUI) 2247 physical_layer = IXGBE_PHYSICAL_LAYER_10GBASE_XAUI; 2248 goto out; 2249 break; 2250 case IXGBE_AUTOC_LMS_10G_SERIAL: 2251 if (pma_pmd_10g_serial == IXGBE_AUTOC2_10G_KR) { 2252 physical_layer = IXGBE_PHYSICAL_LAYER_10GBASE_KR; 2253 goto out; 2254 } else if (pma_pmd_10g_serial == IXGBE_AUTOC2_10G_SFI) 2255 goto sfp_check; 2256 break; 2257 case IXGBE_AUTOC_LMS_KX4_KX_KR: 2258 case IXGBE_AUTOC_LMS_KX4_KX_KR_1G_AN: 2259 if (autoc & IXGBE_AUTOC_KX_SUPP) 2260 physical_layer |= IXGBE_PHYSICAL_LAYER_1000BASE_KX; 2261 if (autoc & IXGBE_AUTOC_KX4_SUPP) 2262 physical_layer |= IXGBE_PHYSICAL_LAYER_10GBASE_KX4; 2263 if (autoc & IXGBE_AUTOC_KR_SUPP) 2264 physical_layer |= IXGBE_PHYSICAL_LAYER_10GBASE_KR; 2265 goto out; 2266 break; 2267 default: 2268 goto out; 2269 break; 2270 } 2271 2272 sfp_check: 2273 /* SFP check must be done last since DA modules are sometimes used to 2274 * test KR mode - we need to id KR mode correctly before SFP module. 2275 * Call identify_sfp because the pluggable module may have changed */ 2276 physical_layer = ixgbe_get_supported_phy_sfp_layer_generic(hw); 2277 out: 2278 return physical_layer; 2279 } 2280 2281 /** 2282 * ixgbe_enable_rx_dma_82599 - Enable the Rx DMA unit on 82599 2283 * @hw: pointer to hardware structure 2284 * @regval: register value to write to RXCTRL 2285 * 2286 * Enables the Rx DMA unit for 82599 2287 **/ 2288 s32 ixgbe_enable_rx_dma_82599(struct ixgbe_hw *hw, u32 regval) 2289 { 2290 2291 DEBUGFUNC("ixgbe_enable_rx_dma_82599"); 2292 2293 /* 2294 * Workaround for 82599 silicon errata when enabling the Rx datapath. 2295 * If traffic is incoming before we enable the Rx unit, it could hang 2296 * the Rx DMA unit. Therefore, make sure the security engine is 2297 * completely disabled prior to enabling the Rx unit. 2298 */ 2299 2300 hw->mac.ops.disable_sec_rx_path(hw); 2301 2302 if (regval & IXGBE_RXCTRL_RXEN) 2303 ixgbe_enable_rx(hw); 2304 else 2305 ixgbe_disable_rx(hw); 2306 2307 hw->mac.ops.enable_sec_rx_path(hw); 2308 2309 return IXGBE_SUCCESS; 2310 } 2311 2312 /** 2313 * ixgbe_verify_fw_version_82599 - verify FW version for 82599 2314 * @hw: pointer to hardware structure 2315 * 2316 * Verifies that installed the firmware version is 0.6 or higher 2317 * for SFI devices. All 82599 SFI devices should have version 0.6 or higher. 2318 * 2319 * Returns IXGBE_ERR_EEPROM_VERSION if the FW is not present or 2320 * if the FW version is not supported. 2321 **/ 2322 static s32 ixgbe_verify_fw_version_82599(struct ixgbe_hw *hw) 2323 { 2324 s32 status = IXGBE_ERR_EEPROM_VERSION; 2325 u16 fw_offset, fw_ptp_cfg_offset; 2326 u16 fw_version; 2327 2328 DEBUGFUNC("ixgbe_verify_fw_version_82599"); 2329 2330 /* firmware check is only necessary for SFI devices */ 2331 if (hw->phy.media_type != ixgbe_media_type_fiber) { 2332 status = IXGBE_SUCCESS; 2333 goto fw_version_out; 2334 } 2335 2336 /* get the offset to the Firmware Module block */ 2337 if (hw->eeprom.ops.read(hw, IXGBE_FW_PTR, &fw_offset)) { 2338 ERROR_REPORT2(IXGBE_ERROR_INVALID_STATE, 2339 "eeprom read at offset %d failed", IXGBE_FW_PTR); 2340 return IXGBE_ERR_EEPROM_VERSION; 2341 } 2342 2343 if ((fw_offset == 0) || (fw_offset == 0xFFFF)) 2344 goto fw_version_out; 2345 2346 /* get the offset to the Pass Through Patch Configuration block */ 2347 if (hw->eeprom.ops.read(hw, (fw_offset + 2348 IXGBE_FW_PASSTHROUGH_PATCH_CONFIG_PTR), 2349 &fw_ptp_cfg_offset)) { 2350 ERROR_REPORT2(IXGBE_ERROR_INVALID_STATE, 2351 "eeprom read at offset %d failed", 2352 fw_offset + 2353 IXGBE_FW_PASSTHROUGH_PATCH_CONFIG_PTR); 2354 return IXGBE_ERR_EEPROM_VERSION; 2355 } 2356 2357 if ((fw_ptp_cfg_offset == 0) || (fw_ptp_cfg_offset == 0xFFFF)) 2358 goto fw_version_out; 2359 2360 /* get the firmware version */ 2361 if (hw->eeprom.ops.read(hw, (fw_ptp_cfg_offset + 2362 IXGBE_FW_PATCH_VERSION_4), &fw_version)) { 2363 ERROR_REPORT2(IXGBE_ERROR_INVALID_STATE, 2364 "eeprom read at offset %d failed", 2365 fw_ptp_cfg_offset + IXGBE_FW_PATCH_VERSION_4); 2366 return IXGBE_ERR_EEPROM_VERSION; 2367 } 2368 2369 if (fw_version > 0x5) 2370 status = IXGBE_SUCCESS; 2371 2372 fw_version_out: 2373 return status; 2374 } 2375 2376 /** 2377 * ixgbe_verify_lesm_fw_enabled_82599 - Checks LESM FW module state. 2378 * @hw: pointer to hardware structure 2379 * 2380 * Returns true if the LESM FW module is present and enabled. Otherwise 2381 * returns false. Smart Speed must be disabled if LESM FW module is enabled. 2382 **/ 2383 bool ixgbe_verify_lesm_fw_enabled_82599(struct ixgbe_hw *hw) 2384 { 2385 bool lesm_enabled = false; 2386 u16 fw_offset, fw_lesm_param_offset, fw_lesm_state; 2387 s32 status; 2388 2389 DEBUGFUNC("ixgbe_verify_lesm_fw_enabled_82599"); 2390 2391 /* get the offset to the Firmware Module block */ 2392 status = hw->eeprom.ops.read(hw, IXGBE_FW_PTR, &fw_offset); 2393 2394 if ((status != IXGBE_SUCCESS) || 2395 (fw_offset == 0) || (fw_offset == 0xFFFF)) 2396 goto out; 2397 2398 /* get the offset to the LESM Parameters block */ 2399 status = hw->eeprom.ops.read(hw, (fw_offset + 2400 IXGBE_FW_LESM_PARAMETERS_PTR), 2401 &fw_lesm_param_offset); 2402 2403 if ((status != IXGBE_SUCCESS) || 2404 (fw_lesm_param_offset == 0) || (fw_lesm_param_offset == 0xFFFF)) 2405 goto out; 2406 2407 /* get the LESM state word */ 2408 status = hw->eeprom.ops.read(hw, (fw_lesm_param_offset + 2409 IXGBE_FW_LESM_STATE_1), 2410 &fw_lesm_state); 2411 2412 if ((status == IXGBE_SUCCESS) && 2413 (fw_lesm_state & IXGBE_FW_LESM_STATE_ENABLED)) 2414 lesm_enabled = true; 2415 2416 out: 2417 return lesm_enabled; 2418 } 2419 2420 /** 2421 * ixgbe_read_eeprom_buffer_82599 - Read EEPROM word(s) using 2422 * fastest available method 2423 * 2424 * @hw: pointer to hardware structure 2425 * @offset: offset of word in EEPROM to read 2426 * @words: number of words 2427 * @data: word(s) read from the EEPROM 2428 * 2429 * Retrieves 16 bit word(s) read from EEPROM 2430 **/ 2431 static s32 ixgbe_read_eeprom_buffer_82599(struct ixgbe_hw *hw, u16 offset, 2432 u16 words, u16 *data) 2433 { 2434 struct ixgbe_eeprom_info *eeprom = &hw->eeprom; 2435 s32 ret_val = IXGBE_ERR_CONFIG; 2436 2437 DEBUGFUNC("ixgbe_read_eeprom_buffer_82599"); 2438 2439 /* 2440 * If EEPROM is detected and can be addressed using 14 bits, 2441 * use EERD otherwise use bit bang 2442 */ 2443 if ((eeprom->type == ixgbe_eeprom_spi) && 2444 (offset + (words - 1) <= IXGBE_EERD_MAX_ADDR)) 2445 ret_val = ixgbe_read_eerd_buffer_generic(hw, offset, words, 2446 data); 2447 else 2448 ret_val = ixgbe_read_eeprom_buffer_bit_bang_generic(hw, offset, 2449 words, 2450 data); 2451 2452 return ret_val; 2453 } 2454 2455 /** 2456 * ixgbe_read_eeprom_82599 - Read EEPROM word using 2457 * fastest available method 2458 * 2459 * @hw: pointer to hardware structure 2460 * @offset: offset of word in the EEPROM to read 2461 * @data: word read from the EEPROM 2462 * 2463 * Reads a 16 bit word from the EEPROM 2464 **/ 2465 static s32 ixgbe_read_eeprom_82599(struct ixgbe_hw *hw, 2466 u16 offset, u16 *data) 2467 { 2468 struct ixgbe_eeprom_info *eeprom = &hw->eeprom; 2469 s32 ret_val = IXGBE_ERR_CONFIG; 2470 2471 DEBUGFUNC("ixgbe_read_eeprom_82599"); 2472 2473 /* 2474 * If EEPROM is detected and can be addressed using 14 bits, 2475 * use EERD otherwise use bit bang 2476 */ 2477 if ((eeprom->type == ixgbe_eeprom_spi) && 2478 (offset <= IXGBE_EERD_MAX_ADDR)) 2479 ret_val = ixgbe_read_eerd_generic(hw, offset, data); 2480 else 2481 ret_val = ixgbe_read_eeprom_bit_bang_generic(hw, offset, data); 2482 2483 return ret_val; 2484 } 2485 2486 /** 2487 * ixgbe_reset_pipeline_82599 - perform pipeline reset 2488 * 2489 * @hw: pointer to hardware structure 2490 * 2491 * Reset pipeline by asserting Restart_AN together with LMS change to ensure 2492 * full pipeline reset. This function assumes the SW/FW lock is held. 2493 **/ 2494 s32 ixgbe_reset_pipeline_82599(struct ixgbe_hw *hw) 2495 { 2496 s32 ret_val; 2497 u32 anlp1_reg = 0; 2498 u32 i, autoc_reg, autoc2_reg; 2499 2500 /* Enable link if disabled in NVM */ 2501 autoc2_reg = IXGBE_READ_REG(hw, IXGBE_AUTOC2); 2502 if (autoc2_reg & IXGBE_AUTOC2_LINK_DISABLE_MASK) { 2503 autoc2_reg &= ~IXGBE_AUTOC2_LINK_DISABLE_MASK; 2504 IXGBE_WRITE_REG(hw, IXGBE_AUTOC2, autoc2_reg); 2505 IXGBE_WRITE_FLUSH(hw); 2506 } 2507 2508 autoc_reg = IXGBE_READ_REG(hw, IXGBE_AUTOC); 2509 autoc_reg |= IXGBE_AUTOC_AN_RESTART; 2510 /* Write AUTOC register with toggled LMS[2] bit and Restart_AN */ 2511 IXGBE_WRITE_REG(hw, IXGBE_AUTOC, 2512 autoc_reg ^ (0x4 << IXGBE_AUTOC_LMS_SHIFT)); 2513 /* Wait for AN to leave state 0 */ 2514 for (i = 0; i < 10; i++) { 2515 msec_delay(4); 2516 anlp1_reg = IXGBE_READ_REG(hw, IXGBE_ANLP1); 2517 if (anlp1_reg & IXGBE_ANLP1_AN_STATE_MASK) 2518 break; 2519 } 2520 2521 if (!(anlp1_reg & IXGBE_ANLP1_AN_STATE_MASK)) { 2522 DEBUGOUT("auto negotiation not completed\n"); 2523 ret_val = IXGBE_ERR_RESET_FAILED; 2524 goto reset_pipeline_out; 2525 } 2526 2527 ret_val = IXGBE_SUCCESS; 2528 2529 reset_pipeline_out: 2530 /* Write AUTOC register with original LMS field and Restart_AN */ 2531 IXGBE_WRITE_REG(hw, IXGBE_AUTOC, autoc_reg); 2532 IXGBE_WRITE_FLUSH(hw); 2533 2534 return ret_val; 2535 } 2536 2537 /** 2538 * ixgbe_read_i2c_byte_82599 - Reads 8 bit word over I2C 2539 * @hw: pointer to hardware structure 2540 * @byte_offset: byte offset to read 2541 * @dev_addr: address to read from 2542 * @data: value read 2543 * 2544 * Performs byte read operation to SFP module's EEPROM over I2C interface at 2545 * a specified device address. 2546 **/ 2547 static s32 ixgbe_read_i2c_byte_82599(struct ixgbe_hw *hw, u8 byte_offset, 2548 u8 dev_addr, u8 *data) 2549 { 2550 u32 esdp; 2551 s32 status; 2552 s32 timeout = 200; 2553 2554 DEBUGFUNC("ixgbe_read_i2c_byte_82599"); 2555 2556 if (hw->phy.qsfp_shared_i2c_bus == true) { 2557 /* Acquire I2C bus ownership. */ 2558 esdp = IXGBE_READ_REG(hw, IXGBE_ESDP); 2559 esdp |= IXGBE_ESDP_SDP0; 2560 IXGBE_WRITE_REG(hw, IXGBE_ESDP, esdp); 2561 IXGBE_WRITE_FLUSH(hw); 2562 2563 while (timeout) { 2564 esdp = IXGBE_READ_REG(hw, IXGBE_ESDP); 2565 if (esdp & IXGBE_ESDP_SDP1) 2566 break; 2567 2568 msec_delay(5); 2569 timeout--; 2570 } 2571 2572 if (!timeout) { 2573 DEBUGOUT("Driver can't access resource," 2574 " acquiring I2C bus timeout.\n"); 2575 status = IXGBE_ERR_I2C; 2576 goto release_i2c_access; 2577 } 2578 } 2579 2580 status = ixgbe_read_i2c_byte_generic(hw, byte_offset, dev_addr, data); 2581 2582 release_i2c_access: 2583 2584 if (hw->phy.qsfp_shared_i2c_bus == true) { 2585 /* Release I2C bus ownership. */ 2586 esdp = IXGBE_READ_REG(hw, IXGBE_ESDP); 2587 esdp &= ~IXGBE_ESDP_SDP0; 2588 IXGBE_WRITE_REG(hw, IXGBE_ESDP, esdp); 2589 IXGBE_WRITE_FLUSH(hw); 2590 } 2591 2592 return status; 2593 } 2594 2595 /** 2596 * ixgbe_write_i2c_byte_82599 - Writes 8 bit word over I2C 2597 * @hw: pointer to hardware structure 2598 * @byte_offset: byte offset to write 2599 * @dev_addr: address to read from 2600 * @data: value to write 2601 * 2602 * Performs byte write operation to SFP module's EEPROM over I2C interface at 2603 * a specified device address. 2604 **/ 2605 static s32 ixgbe_write_i2c_byte_82599(struct ixgbe_hw *hw, u8 byte_offset, 2606 u8 dev_addr, u8 data) 2607 { 2608 u32 esdp; 2609 s32 status; 2610 s32 timeout = 200; 2611 2612 DEBUGFUNC("ixgbe_write_i2c_byte_82599"); 2613 2614 if (hw->phy.qsfp_shared_i2c_bus == true) { 2615 /* Acquire I2C bus ownership. */ 2616 esdp = IXGBE_READ_REG(hw, IXGBE_ESDP); 2617 esdp |= IXGBE_ESDP_SDP0; 2618 IXGBE_WRITE_REG(hw, IXGBE_ESDP, esdp); 2619 IXGBE_WRITE_FLUSH(hw); 2620 2621 while (timeout) { 2622 esdp = IXGBE_READ_REG(hw, IXGBE_ESDP); 2623 if (esdp & IXGBE_ESDP_SDP1) 2624 break; 2625 2626 msec_delay(5); 2627 timeout--; 2628 } 2629 2630 if (!timeout) { 2631 DEBUGOUT("Driver can't access resource," 2632 " acquiring I2C bus timeout.\n"); 2633 status = IXGBE_ERR_I2C; 2634 goto release_i2c_access; 2635 } 2636 } 2637 2638 status = ixgbe_write_i2c_byte_generic(hw, byte_offset, dev_addr, data); 2639 2640 release_i2c_access: 2641 2642 if (hw->phy.qsfp_shared_i2c_bus == true) { 2643 /* Release I2C bus ownership. */ 2644 esdp = IXGBE_READ_REG(hw, IXGBE_ESDP); 2645 esdp &= ~IXGBE_ESDP_SDP0; 2646 IXGBE_WRITE_REG(hw, IXGBE_ESDP, esdp); 2647 IXGBE_WRITE_FLUSH(hw); 2648 } 2649 2650 return status; 2651 } 2652