1 /****************************************************************************** 2 SPDX-License-Identifier: BSD-3-Clause 3 4 Copyright (c) 2001-2020, Intel Corporation 5 All rights reserved. 6 7 Redistribution and use in source and binary forms, with or without 8 modification, are permitted provided that the following conditions are met: 9 10 1. Redistributions of source code must retain the above copyright notice, 11 this list of conditions and the following disclaimer. 12 13 2. Redistributions in binary form must reproduce the above copyright 14 notice, this list of conditions and the following disclaimer in the 15 documentation and/or other materials provided with the distribution. 16 17 3. Neither the name of the Intel Corporation nor the names of its 18 contributors may be used to endorse or promote products derived from 19 this software without specific prior written permission. 20 21 THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 22 AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 23 IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 24 ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE 25 LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 26 CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 27 SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 28 INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 29 CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 30 ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 31 POSSIBILITY OF SUCH DAMAGE. 32 33 ******************************************************************************/ 34 /*$FreeBSD$*/ 35 36 #include "ixgbe_type.h" 37 #include "ixgbe_82599.h" 38 #include "ixgbe_api.h" 39 #include "ixgbe_common.h" 40 #include "ixgbe_phy.h" 41 42 #define IXGBE_82599_MAX_TX_QUEUES 128 43 #define IXGBE_82599_MAX_RX_QUEUES 128 44 #define IXGBE_82599_RAR_ENTRIES 128 45 #define IXGBE_82599_MC_TBL_SIZE 128 46 #define IXGBE_82599_VFT_TBL_SIZE 128 47 #define IXGBE_82599_RX_PB_SIZE 512 48 49 static s32 ixgbe_setup_copper_link_82599(struct ixgbe_hw *hw, 50 ixgbe_link_speed speed, 51 bool autoneg_wait_to_complete); 52 static s32 ixgbe_verify_fw_version_82599(struct ixgbe_hw *hw); 53 static s32 ixgbe_read_eeprom_82599(struct ixgbe_hw *hw, 54 u16 offset, u16 *data); 55 static s32 ixgbe_read_eeprom_buffer_82599(struct ixgbe_hw *hw, u16 offset, 56 u16 words, u16 *data); 57 static s32 ixgbe_read_i2c_byte_82599(struct ixgbe_hw *hw, u8 byte_offset, 58 u8 dev_addr, u8 *data); 59 static s32 ixgbe_write_i2c_byte_82599(struct ixgbe_hw *hw, u8 byte_offset, 60 u8 dev_addr, u8 data); 61 62 void ixgbe_init_mac_link_ops_82599(struct ixgbe_hw *hw) 63 { 64 struct ixgbe_mac_info *mac = &hw->mac; 65 66 DEBUGFUNC("ixgbe_init_mac_link_ops_82599"); 67 68 /* 69 * enable the laser control functions for SFP+ fiber 70 * and MNG not enabled 71 */ 72 if ((mac->ops.get_media_type(hw) == ixgbe_media_type_fiber) && 73 !ixgbe_mng_enabled(hw)) { 74 mac->ops.disable_tx_laser = 75 ixgbe_disable_tx_laser_multispeed_fiber; 76 mac->ops.enable_tx_laser = 77 ixgbe_enable_tx_laser_multispeed_fiber; 78 mac->ops.flap_tx_laser = ixgbe_flap_tx_laser_multispeed_fiber; 79 80 } else { 81 mac->ops.disable_tx_laser = NULL; 82 mac->ops.enable_tx_laser = NULL; 83 mac->ops.flap_tx_laser = NULL; 84 } 85 86 if (hw->phy.multispeed_fiber) { 87 /* Set up dual speed SFP+ support */ 88 mac->ops.setup_link = ixgbe_setup_mac_link_multispeed_fiber; 89 mac->ops.setup_mac_link = ixgbe_setup_mac_link_82599; 90 mac->ops.set_rate_select_speed = 91 ixgbe_set_hard_rate_select_speed; 92 if (ixgbe_get_media_type(hw) == ixgbe_media_type_fiber_fixed) 93 mac->ops.set_rate_select_speed = 94 ixgbe_set_soft_rate_select_speed; 95 } else { 96 if ((ixgbe_get_media_type(hw) == ixgbe_media_type_backplane) && 97 (hw->phy.smart_speed == ixgbe_smart_speed_auto || 98 hw->phy.smart_speed == ixgbe_smart_speed_on) && 99 !ixgbe_verify_lesm_fw_enabled_82599(hw)) { 100 mac->ops.setup_link = ixgbe_setup_mac_link_smartspeed; 101 } else { 102 mac->ops.setup_link = ixgbe_setup_mac_link_82599; 103 } 104 } 105 } 106 107 /** 108 * ixgbe_init_phy_ops_82599 - PHY/SFP specific init 109 * @hw: pointer to hardware structure 110 * 111 * Initialize any function pointers that were not able to be 112 * set during init_shared_code because the PHY/SFP type was 113 * not known. Perform the SFP init if necessary. 114 * 115 **/ 116 s32 ixgbe_init_phy_ops_82599(struct ixgbe_hw *hw) 117 { 118 struct ixgbe_mac_info *mac = &hw->mac; 119 struct ixgbe_phy_info *phy = &hw->phy; 120 s32 ret_val = IXGBE_SUCCESS; 121 u32 esdp; 122 123 DEBUGFUNC("ixgbe_init_phy_ops_82599"); 124 125 if (hw->device_id == IXGBE_DEV_ID_82599_QSFP_SF_QP) { 126 /* Store flag indicating I2C bus access control unit. */ 127 hw->phy.qsfp_shared_i2c_bus = true; 128 129 /* Initialize access to QSFP+ I2C bus */ 130 esdp = IXGBE_READ_REG(hw, IXGBE_ESDP); 131 esdp |= IXGBE_ESDP_SDP0_DIR; 132 esdp &= ~IXGBE_ESDP_SDP1_DIR; 133 esdp &= ~IXGBE_ESDP_SDP0; 134 esdp &= ~IXGBE_ESDP_SDP0_NATIVE; 135 esdp &= ~IXGBE_ESDP_SDP1_NATIVE; 136 IXGBE_WRITE_REG(hw, IXGBE_ESDP, esdp); 137 IXGBE_WRITE_FLUSH(hw); 138 139 phy->ops.read_i2c_byte = ixgbe_read_i2c_byte_82599; 140 phy->ops.write_i2c_byte = ixgbe_write_i2c_byte_82599; 141 } 142 /* Identify the PHY or SFP module */ 143 ret_val = phy->ops.identify(hw); 144 if (ret_val == IXGBE_ERR_SFP_NOT_SUPPORTED) 145 goto init_phy_ops_out; 146 147 /* Setup function pointers based on detected SFP module and speeds */ 148 ixgbe_init_mac_link_ops_82599(hw); 149 if (hw->phy.sfp_type != ixgbe_sfp_type_unknown) 150 hw->phy.ops.reset = NULL; 151 152 /* If copper media, overwrite with copper function pointers */ 153 if (mac->ops.get_media_type(hw) == ixgbe_media_type_copper) { 154 mac->ops.setup_link = ixgbe_setup_copper_link_82599; 155 mac->ops.get_link_capabilities = 156 ixgbe_get_copper_link_capabilities_generic; 157 } 158 159 /* Set necessary function pointers based on PHY type */ 160 switch (hw->phy.type) { 161 case ixgbe_phy_tn: 162 phy->ops.setup_link = ixgbe_setup_phy_link_tnx; 163 phy->ops.check_link = ixgbe_check_phy_link_tnx; 164 phy->ops.get_firmware_version = 165 ixgbe_get_phy_firmware_version_tnx; 166 break; 167 default: 168 break; 169 } 170 init_phy_ops_out: 171 return ret_val; 172 } 173 174 s32 ixgbe_setup_sfp_modules_82599(struct ixgbe_hw *hw) 175 { 176 s32 ret_val = IXGBE_SUCCESS; 177 u16 list_offset, data_offset, data_value; 178 179 DEBUGFUNC("ixgbe_setup_sfp_modules_82599"); 180 181 if (hw->phy.sfp_type != ixgbe_sfp_type_unknown) { 182 ixgbe_init_mac_link_ops_82599(hw); 183 184 hw->phy.ops.reset = NULL; 185 186 ret_val = ixgbe_get_sfp_init_sequence_offsets(hw, &list_offset, 187 &data_offset); 188 if (ret_val != IXGBE_SUCCESS) 189 goto setup_sfp_out; 190 191 /* PHY config will finish before releasing the semaphore */ 192 ret_val = hw->mac.ops.acquire_swfw_sync(hw, 193 IXGBE_GSSR_MAC_CSR_SM); 194 if (ret_val != IXGBE_SUCCESS) { 195 ret_val = IXGBE_ERR_SWFW_SYNC; 196 goto setup_sfp_out; 197 } 198 199 if (hw->eeprom.ops.read(hw, ++data_offset, &data_value)) 200 goto setup_sfp_err; 201 while (data_value != 0xffff) { 202 IXGBE_WRITE_REG(hw, IXGBE_CORECTL, data_value); 203 IXGBE_WRITE_FLUSH(hw); 204 if (hw->eeprom.ops.read(hw, ++data_offset, &data_value)) 205 goto setup_sfp_err; 206 } 207 208 /* Release the semaphore */ 209 hw->mac.ops.release_swfw_sync(hw, IXGBE_GSSR_MAC_CSR_SM); 210 /* Delay obtaining semaphore again to allow FW access 211 * prot_autoc_write uses the semaphore too. 212 */ 213 msec_delay(hw->eeprom.semaphore_delay); 214 215 /* Restart DSP and set SFI mode */ 216 ret_val = hw->mac.ops.prot_autoc_write(hw, 217 hw->mac.orig_autoc | IXGBE_AUTOC_LMS_10G_SERIAL, 218 false); 219 220 if (ret_val) { 221 DEBUGOUT("sfp module setup not complete\n"); 222 ret_val = IXGBE_ERR_SFP_SETUP_NOT_COMPLETE; 223 goto setup_sfp_out; 224 } 225 226 } 227 228 setup_sfp_out: 229 return ret_val; 230 231 setup_sfp_err: 232 /* Release the semaphore */ 233 hw->mac.ops.release_swfw_sync(hw, IXGBE_GSSR_MAC_CSR_SM); 234 /* Delay obtaining semaphore again to allow FW access */ 235 msec_delay(hw->eeprom.semaphore_delay); 236 ERROR_REPORT2(IXGBE_ERROR_INVALID_STATE, 237 "eeprom read at offset %d failed", data_offset); 238 return IXGBE_ERR_PHY; 239 } 240 241 /** 242 * prot_autoc_read_82599 - Hides MAC differences needed for AUTOC read 243 * @hw: pointer to hardware structure 244 * @locked: Return the if we locked for this read. 245 * @reg_val: Value we read from AUTOC 246 * 247 * For this part (82599) we need to wrap read-modify-writes with a possible 248 * FW/SW lock. It is assumed this lock will be freed with the next 249 * prot_autoc_write_82599(). 250 */ 251 s32 prot_autoc_read_82599(struct ixgbe_hw *hw, bool *locked, u32 *reg_val) 252 { 253 s32 ret_val; 254 255 *locked = false; 256 /* If LESM is on then we need to hold the SW/FW semaphore. */ 257 if (ixgbe_verify_lesm_fw_enabled_82599(hw)) { 258 ret_val = hw->mac.ops.acquire_swfw_sync(hw, 259 IXGBE_GSSR_MAC_CSR_SM); 260 if (ret_val != IXGBE_SUCCESS) 261 return IXGBE_ERR_SWFW_SYNC; 262 263 *locked = true; 264 } 265 266 *reg_val = IXGBE_READ_REG(hw, IXGBE_AUTOC); 267 return IXGBE_SUCCESS; 268 } 269 270 /** 271 * prot_autoc_write_82599 - Hides MAC differences needed for AUTOC write 272 * @hw: pointer to hardware structure 273 * @autoc: value to write to AUTOC 274 * @locked: bool to indicate whether the SW/FW lock was already taken by 275 * previous proc_autoc_read_82599. 276 * 277 * This part (82599) may need to hold the SW/FW lock around all writes to 278 * AUTOC. Likewise after a write we need to do a pipeline reset. 279 */ 280 s32 prot_autoc_write_82599(struct ixgbe_hw *hw, u32 autoc, bool locked) 281 { 282 s32 ret_val = IXGBE_SUCCESS; 283 284 /* Blocked by MNG FW so bail */ 285 if (ixgbe_check_reset_blocked(hw)) 286 goto out; 287 288 /* We only need to get the lock if: 289 * - We didn't do it already (in the read part of a read-modify-write) 290 * - LESM is enabled. 291 */ 292 if (!locked && ixgbe_verify_lesm_fw_enabled_82599(hw)) { 293 ret_val = hw->mac.ops.acquire_swfw_sync(hw, 294 IXGBE_GSSR_MAC_CSR_SM); 295 if (ret_val != IXGBE_SUCCESS) 296 return IXGBE_ERR_SWFW_SYNC; 297 298 locked = true; 299 } 300 301 IXGBE_WRITE_REG(hw, IXGBE_AUTOC, autoc); 302 ret_val = ixgbe_reset_pipeline_82599(hw); 303 304 out: 305 /* Free the SW/FW semaphore as we either grabbed it here or 306 * already had it when this function was called. 307 */ 308 if (locked) 309 hw->mac.ops.release_swfw_sync(hw, IXGBE_GSSR_MAC_CSR_SM); 310 311 return ret_val; 312 } 313 314 /** 315 * ixgbe_init_ops_82599 - Inits func ptrs and MAC type 316 * @hw: pointer to hardware structure 317 * 318 * Initialize the function pointers and assign the MAC type for 82599. 319 * Does not touch the hardware. 320 **/ 321 322 s32 ixgbe_init_ops_82599(struct ixgbe_hw *hw) 323 { 324 struct ixgbe_mac_info *mac = &hw->mac; 325 struct ixgbe_phy_info *phy = &hw->phy; 326 struct ixgbe_eeprom_info *eeprom = &hw->eeprom; 327 s32 ret_val; 328 329 DEBUGFUNC("ixgbe_init_ops_82599"); 330 331 ixgbe_init_phy_ops_generic(hw); 332 ret_val = ixgbe_init_ops_generic(hw); 333 334 /* PHY */ 335 phy->ops.identify = ixgbe_identify_phy_82599; 336 phy->ops.init = ixgbe_init_phy_ops_82599; 337 338 /* MAC */ 339 mac->ops.reset_hw = ixgbe_reset_hw_82599; 340 mac->ops.enable_relaxed_ordering = ixgbe_enable_relaxed_ordering_gen2; 341 mac->ops.get_media_type = ixgbe_get_media_type_82599; 342 mac->ops.get_supported_physical_layer = 343 ixgbe_get_supported_physical_layer_82599; 344 mac->ops.disable_sec_rx_path = ixgbe_disable_sec_rx_path_generic; 345 mac->ops.enable_sec_rx_path = ixgbe_enable_sec_rx_path_generic; 346 mac->ops.enable_rx_dma = ixgbe_enable_rx_dma_82599; 347 mac->ops.read_analog_reg8 = ixgbe_read_analog_reg8_82599; 348 mac->ops.write_analog_reg8 = ixgbe_write_analog_reg8_82599; 349 mac->ops.start_hw = ixgbe_start_hw_82599; 350 mac->ops.get_san_mac_addr = ixgbe_get_san_mac_addr_generic; 351 mac->ops.set_san_mac_addr = ixgbe_set_san_mac_addr_generic; 352 mac->ops.get_device_caps = ixgbe_get_device_caps_generic; 353 mac->ops.get_wwn_prefix = ixgbe_get_wwn_prefix_generic; 354 mac->ops.get_fcoe_boot_status = ixgbe_get_fcoe_boot_status_generic; 355 mac->ops.prot_autoc_read = prot_autoc_read_82599; 356 mac->ops.prot_autoc_write = prot_autoc_write_82599; 357 358 /* RAR, Multicast, VLAN */ 359 mac->ops.set_vmdq = ixgbe_set_vmdq_generic; 360 mac->ops.set_vmdq_san_mac = ixgbe_set_vmdq_san_mac_generic; 361 mac->ops.clear_vmdq = ixgbe_clear_vmdq_generic; 362 mac->ops.insert_mac_addr = ixgbe_insert_mac_addr_generic; 363 mac->rar_highwater = 1; 364 mac->ops.set_vfta = ixgbe_set_vfta_generic; 365 mac->ops.set_vlvf = ixgbe_set_vlvf_generic; 366 mac->ops.clear_vfta = ixgbe_clear_vfta_generic; 367 mac->ops.init_uta_tables = ixgbe_init_uta_tables_generic; 368 mac->ops.setup_sfp = ixgbe_setup_sfp_modules_82599; 369 mac->ops.set_mac_anti_spoofing = ixgbe_set_mac_anti_spoofing; 370 mac->ops.set_vlan_anti_spoofing = ixgbe_set_vlan_anti_spoofing; 371 372 /* Link */ 373 mac->ops.get_link_capabilities = ixgbe_get_link_capabilities_82599; 374 mac->ops.check_link = ixgbe_check_mac_link_generic; 375 mac->ops.setup_rxpba = ixgbe_set_rxpba_generic; 376 ixgbe_init_mac_link_ops_82599(hw); 377 378 mac->mcft_size = IXGBE_82599_MC_TBL_SIZE; 379 mac->vft_size = IXGBE_82599_VFT_TBL_SIZE; 380 mac->num_rar_entries = IXGBE_82599_RAR_ENTRIES; 381 mac->rx_pb_size = IXGBE_82599_RX_PB_SIZE; 382 mac->max_rx_queues = IXGBE_82599_MAX_RX_QUEUES; 383 mac->max_tx_queues = IXGBE_82599_MAX_TX_QUEUES; 384 mac->max_msix_vectors = ixgbe_get_pcie_msix_count_generic(hw); 385 386 mac->arc_subsystem_valid = !!(IXGBE_READ_REG(hw, IXGBE_FWSM_BY_MAC(hw)) 387 & IXGBE_FWSM_MODE_MASK); 388 389 hw->mbx.ops.init_params = ixgbe_init_mbx_params_pf; 390 391 /* EEPROM */ 392 eeprom->ops.read = ixgbe_read_eeprom_82599; 393 eeprom->ops.read_buffer = ixgbe_read_eeprom_buffer_82599; 394 395 /* Manageability interface */ 396 mac->ops.set_fw_drv_ver = ixgbe_set_fw_drv_ver_generic; 397 398 mac->ops.get_thermal_sensor_data = 399 ixgbe_get_thermal_sensor_data_generic; 400 mac->ops.init_thermal_sensor_thresh = 401 ixgbe_init_thermal_sensor_thresh_generic; 402 403 mac->ops.bypass_rw = ixgbe_bypass_rw_generic; 404 mac->ops.bypass_valid_rd = ixgbe_bypass_valid_rd_generic; 405 mac->ops.bypass_set = ixgbe_bypass_set_generic; 406 mac->ops.bypass_rd_eep = ixgbe_bypass_rd_eep_generic; 407 408 mac->ops.get_rtrup2tc = ixgbe_dcb_get_rtrup2tc_generic; 409 410 return ret_val; 411 } 412 413 /** 414 * ixgbe_get_link_capabilities_82599 - Determines link capabilities 415 * @hw: pointer to hardware structure 416 * @speed: pointer to link speed 417 * @autoneg: true when autoneg or autotry is enabled 418 * 419 * Determines the link capabilities by reading the AUTOC register. 420 **/ 421 s32 ixgbe_get_link_capabilities_82599(struct ixgbe_hw *hw, 422 ixgbe_link_speed *speed, 423 bool *autoneg) 424 { 425 s32 status = IXGBE_SUCCESS; 426 u32 autoc = 0; 427 428 DEBUGFUNC("ixgbe_get_link_capabilities_82599"); 429 430 431 /* Check if 1G SFP module. */ 432 if (hw->phy.sfp_type == ixgbe_sfp_type_1g_cu_core0 || 433 hw->phy.sfp_type == ixgbe_sfp_type_1g_cu_core1 || 434 hw->phy.sfp_type == ixgbe_sfp_type_1g_lx_core0 || 435 hw->phy.sfp_type == ixgbe_sfp_type_1g_lx_core1 || 436 hw->phy.sfp_type == ixgbe_sfp_type_1g_sx_core0 || 437 hw->phy.sfp_type == ixgbe_sfp_type_1g_sx_core1) { 438 *speed = IXGBE_LINK_SPEED_1GB_FULL; 439 *autoneg = true; 440 goto out; 441 } 442 443 /* 444 * Determine link capabilities based on the stored value of AUTOC, 445 * which represents EEPROM defaults. If AUTOC value has not 446 * been stored, use the current register values. 447 */ 448 if (hw->mac.orig_link_settings_stored) 449 autoc = hw->mac.orig_autoc; 450 else 451 autoc = IXGBE_READ_REG(hw, IXGBE_AUTOC); 452 453 switch (autoc & IXGBE_AUTOC_LMS_MASK) { 454 case IXGBE_AUTOC_LMS_1G_LINK_NO_AN: 455 *speed = IXGBE_LINK_SPEED_1GB_FULL; 456 *autoneg = false; 457 break; 458 459 case IXGBE_AUTOC_LMS_10G_LINK_NO_AN: 460 *speed = IXGBE_LINK_SPEED_10GB_FULL; 461 *autoneg = false; 462 break; 463 464 case IXGBE_AUTOC_LMS_1G_AN: 465 *speed = IXGBE_LINK_SPEED_1GB_FULL; 466 *autoneg = true; 467 break; 468 469 case IXGBE_AUTOC_LMS_10G_SERIAL: 470 *speed = IXGBE_LINK_SPEED_10GB_FULL; 471 *autoneg = false; 472 break; 473 474 case IXGBE_AUTOC_LMS_KX4_KX_KR: 475 case IXGBE_AUTOC_LMS_KX4_KX_KR_1G_AN: 476 *speed = IXGBE_LINK_SPEED_UNKNOWN; 477 if (autoc & IXGBE_AUTOC_KR_SUPP) 478 *speed |= IXGBE_LINK_SPEED_10GB_FULL; 479 if (autoc & IXGBE_AUTOC_KX4_SUPP) 480 *speed |= IXGBE_LINK_SPEED_10GB_FULL; 481 if (autoc & IXGBE_AUTOC_KX_SUPP) 482 *speed |= IXGBE_LINK_SPEED_1GB_FULL; 483 *autoneg = true; 484 break; 485 486 case IXGBE_AUTOC_LMS_KX4_KX_KR_SGMII: 487 *speed = IXGBE_LINK_SPEED_100_FULL; 488 if (autoc & IXGBE_AUTOC_KR_SUPP) 489 *speed |= IXGBE_LINK_SPEED_10GB_FULL; 490 if (autoc & IXGBE_AUTOC_KX4_SUPP) 491 *speed |= IXGBE_LINK_SPEED_10GB_FULL; 492 if (autoc & IXGBE_AUTOC_KX_SUPP) 493 *speed |= IXGBE_LINK_SPEED_1GB_FULL; 494 *autoneg = true; 495 break; 496 497 case IXGBE_AUTOC_LMS_SGMII_1G_100M: 498 *speed = IXGBE_LINK_SPEED_1GB_FULL | IXGBE_LINK_SPEED_100_FULL; 499 *autoneg = false; 500 break; 501 502 default: 503 status = IXGBE_ERR_LINK_SETUP; 504 goto out; 505 break; 506 } 507 508 if (hw->phy.multispeed_fiber) { 509 *speed |= IXGBE_LINK_SPEED_10GB_FULL | 510 IXGBE_LINK_SPEED_1GB_FULL; 511 512 /* QSFP must not enable full auto-negotiation 513 * Limited autoneg is enabled at 1G 514 */ 515 if (hw->phy.media_type == ixgbe_media_type_fiber_qsfp) 516 *autoneg = false; 517 else 518 *autoneg = true; 519 } 520 521 out: 522 return status; 523 } 524 525 /** 526 * ixgbe_get_media_type_82599 - Get media type 527 * @hw: pointer to hardware structure 528 * 529 * Returns the media type (fiber, copper, backplane) 530 **/ 531 enum ixgbe_media_type ixgbe_get_media_type_82599(struct ixgbe_hw *hw) 532 { 533 enum ixgbe_media_type media_type; 534 535 DEBUGFUNC("ixgbe_get_media_type_82599"); 536 537 /* Detect if there is a copper PHY attached. */ 538 switch (hw->phy.type) { 539 case ixgbe_phy_cu_unknown: 540 case ixgbe_phy_tn: 541 media_type = ixgbe_media_type_copper; 542 goto out; 543 default: 544 break; 545 } 546 547 switch (hw->device_id) { 548 case IXGBE_DEV_ID_82599_KX4: 549 case IXGBE_DEV_ID_82599_KX4_MEZZ: 550 case IXGBE_DEV_ID_82599_COMBO_BACKPLANE: 551 case IXGBE_DEV_ID_82599_KR: 552 case IXGBE_DEV_ID_82599_BACKPLANE_FCOE: 553 case IXGBE_DEV_ID_82599_XAUI_LOM: 554 /* Default device ID is mezzanine card KX/KX4 */ 555 media_type = ixgbe_media_type_backplane; 556 break; 557 case IXGBE_DEV_ID_82599_SFP: 558 case IXGBE_DEV_ID_82599_SFP_FCOE: 559 case IXGBE_DEV_ID_82599_SFP_EM: 560 case IXGBE_DEV_ID_82599_SFP_SF2: 561 case IXGBE_DEV_ID_82599_SFP_SF_QP: 562 case IXGBE_DEV_ID_82599EN_SFP: 563 media_type = ixgbe_media_type_fiber; 564 break; 565 case IXGBE_DEV_ID_82599_CX4: 566 media_type = ixgbe_media_type_cx4; 567 break; 568 case IXGBE_DEV_ID_82599_T3_LOM: 569 media_type = ixgbe_media_type_copper; 570 break; 571 case IXGBE_DEV_ID_82599_LS: 572 media_type = ixgbe_media_type_fiber_lco; 573 break; 574 case IXGBE_DEV_ID_82599_QSFP_SF_QP: 575 media_type = ixgbe_media_type_fiber_qsfp; 576 break; 577 case IXGBE_DEV_ID_82599_BYPASS: 578 media_type = ixgbe_media_type_fiber_fixed; 579 hw->phy.multispeed_fiber = true; 580 break; 581 default: 582 media_type = ixgbe_media_type_unknown; 583 break; 584 } 585 out: 586 return media_type; 587 } 588 589 /** 590 * ixgbe_stop_mac_link_on_d3_82599 - Disables link on D3 591 * @hw: pointer to hardware structure 592 * 593 * Disables link during D3 power down sequence. 594 * 595 **/ 596 void ixgbe_stop_mac_link_on_d3_82599(struct ixgbe_hw *hw) 597 { 598 u32 autoc2_reg; 599 u16 ee_ctrl_2 = 0; 600 601 DEBUGFUNC("ixgbe_stop_mac_link_on_d3_82599"); 602 ixgbe_read_eeprom(hw, IXGBE_EEPROM_CTRL_2, &ee_ctrl_2); 603 604 if (!ixgbe_mng_present(hw) && !hw->wol_enabled && 605 ee_ctrl_2 & IXGBE_EEPROM_CCD_BIT) { 606 autoc2_reg = IXGBE_READ_REG(hw, IXGBE_AUTOC2); 607 autoc2_reg |= IXGBE_AUTOC2_LINK_DISABLE_ON_D3_MASK; 608 IXGBE_WRITE_REG(hw, IXGBE_AUTOC2, autoc2_reg); 609 } 610 } 611 612 /** 613 * ixgbe_start_mac_link_82599 - Setup MAC link settings 614 * @hw: pointer to hardware structure 615 * @autoneg_wait_to_complete: true when waiting for completion is needed 616 * 617 * Configures link settings based on values in the ixgbe_hw struct. 618 * Restarts the link. Performs autonegotiation if needed. 619 **/ 620 s32 ixgbe_start_mac_link_82599(struct ixgbe_hw *hw, 621 bool autoneg_wait_to_complete) 622 { 623 u32 autoc_reg; 624 u32 links_reg; 625 u32 i; 626 s32 status = IXGBE_SUCCESS; 627 bool got_lock = false; 628 629 DEBUGFUNC("ixgbe_start_mac_link_82599"); 630 631 632 /* reset_pipeline requires us to hold this lock as it writes to 633 * AUTOC. 634 */ 635 if (ixgbe_verify_lesm_fw_enabled_82599(hw)) { 636 status = hw->mac.ops.acquire_swfw_sync(hw, 637 IXGBE_GSSR_MAC_CSR_SM); 638 if (status != IXGBE_SUCCESS) 639 goto out; 640 641 got_lock = true; 642 } 643 644 /* Restart link */ 645 ixgbe_reset_pipeline_82599(hw); 646 647 if (got_lock) 648 hw->mac.ops.release_swfw_sync(hw, IXGBE_GSSR_MAC_CSR_SM); 649 650 /* Only poll for autoneg to complete if specified to do so */ 651 if (autoneg_wait_to_complete) { 652 autoc_reg = IXGBE_READ_REG(hw, IXGBE_AUTOC); 653 if ((autoc_reg & IXGBE_AUTOC_LMS_MASK) == 654 IXGBE_AUTOC_LMS_KX4_KX_KR || 655 (autoc_reg & IXGBE_AUTOC_LMS_MASK) == 656 IXGBE_AUTOC_LMS_KX4_KX_KR_1G_AN || 657 (autoc_reg & IXGBE_AUTOC_LMS_MASK) == 658 IXGBE_AUTOC_LMS_KX4_KX_KR_SGMII) { 659 links_reg = 0; /* Just in case Autoneg time = 0 */ 660 for (i = 0; i < IXGBE_AUTO_NEG_TIME; i++) { 661 links_reg = IXGBE_READ_REG(hw, IXGBE_LINKS); 662 if (links_reg & IXGBE_LINKS_KX_AN_COMP) 663 break; 664 msec_delay(100); 665 } 666 if (!(links_reg & IXGBE_LINKS_KX_AN_COMP)) { 667 status = IXGBE_ERR_AUTONEG_NOT_COMPLETE; 668 DEBUGOUT("Autoneg did not complete.\n"); 669 } 670 } 671 } 672 673 /* Add delay to filter out noises during initial link setup */ 674 msec_delay(50); 675 676 out: 677 return status; 678 } 679 680 /** 681 * ixgbe_disable_tx_laser_multispeed_fiber - Disable Tx laser 682 * @hw: pointer to hardware structure 683 * 684 * The base drivers may require better control over SFP+ module 685 * PHY states. This includes selectively shutting down the Tx 686 * laser on the PHY, effectively halting physical link. 687 **/ 688 void ixgbe_disable_tx_laser_multispeed_fiber(struct ixgbe_hw *hw) 689 { 690 u32 esdp_reg = IXGBE_READ_REG(hw, IXGBE_ESDP); 691 692 /* Blocked by MNG FW so bail */ 693 if (ixgbe_check_reset_blocked(hw)) 694 return; 695 696 /* Disable Tx laser; allow 100us to go dark per spec */ 697 esdp_reg |= IXGBE_ESDP_SDP3; 698 IXGBE_WRITE_REG(hw, IXGBE_ESDP, esdp_reg); 699 IXGBE_WRITE_FLUSH(hw); 700 usec_delay(100); 701 } 702 703 /** 704 * ixgbe_enable_tx_laser_multispeed_fiber - Enable Tx laser 705 * @hw: pointer to hardware structure 706 * 707 * The base drivers may require better control over SFP+ module 708 * PHY states. This includes selectively turning on the Tx 709 * laser on the PHY, effectively starting physical link. 710 **/ 711 void ixgbe_enable_tx_laser_multispeed_fiber(struct ixgbe_hw *hw) 712 { 713 u32 esdp_reg = IXGBE_READ_REG(hw, IXGBE_ESDP); 714 715 /* Enable Tx laser; allow 100ms to light up */ 716 esdp_reg &= ~IXGBE_ESDP_SDP3; 717 IXGBE_WRITE_REG(hw, IXGBE_ESDP, esdp_reg); 718 IXGBE_WRITE_FLUSH(hw); 719 msec_delay(100); 720 } 721 722 /** 723 * ixgbe_flap_tx_laser_multispeed_fiber - Flap Tx laser 724 * @hw: pointer to hardware structure 725 * 726 * When the driver changes the link speeds that it can support, 727 * it sets autotry_restart to true to indicate that we need to 728 * initiate a new autotry session with the link partner. To do 729 * so, we set the speed then disable and re-enable the Tx laser, to 730 * alert the link partner that it also needs to restart autotry on its 731 * end. This is consistent with true clause 37 autoneg, which also 732 * involves a loss of signal. 733 **/ 734 void ixgbe_flap_tx_laser_multispeed_fiber(struct ixgbe_hw *hw) 735 { 736 DEBUGFUNC("ixgbe_flap_tx_laser_multispeed_fiber"); 737 738 /* Blocked by MNG FW so bail */ 739 if (ixgbe_check_reset_blocked(hw)) 740 return; 741 742 if (hw->mac.autotry_restart) { 743 ixgbe_disable_tx_laser_multispeed_fiber(hw); 744 ixgbe_enable_tx_laser_multispeed_fiber(hw); 745 hw->mac.autotry_restart = false; 746 } 747 } 748 749 /** 750 * ixgbe_set_hard_rate_select_speed - Set module link speed 751 * @hw: pointer to hardware structure 752 * @speed: link speed to set 753 * 754 * Set module link speed via RS0/RS1 rate select pins. 755 */ 756 void ixgbe_set_hard_rate_select_speed(struct ixgbe_hw *hw, 757 ixgbe_link_speed speed) 758 { 759 u32 esdp_reg = IXGBE_READ_REG(hw, IXGBE_ESDP); 760 761 switch (speed) { 762 case IXGBE_LINK_SPEED_10GB_FULL: 763 esdp_reg |= (IXGBE_ESDP_SDP5_DIR | IXGBE_ESDP_SDP5); 764 break; 765 case IXGBE_LINK_SPEED_1GB_FULL: 766 esdp_reg &= ~IXGBE_ESDP_SDP5; 767 esdp_reg |= IXGBE_ESDP_SDP5_DIR; 768 break; 769 default: 770 DEBUGOUT("Invalid fixed module speed\n"); 771 return; 772 } 773 774 IXGBE_WRITE_REG(hw, IXGBE_ESDP, esdp_reg); 775 IXGBE_WRITE_FLUSH(hw); 776 } 777 778 /** 779 * ixgbe_setup_mac_link_smartspeed - Set MAC link speed using SmartSpeed 780 * @hw: pointer to hardware structure 781 * @speed: new link speed 782 * @autoneg_wait_to_complete: true when waiting for completion is needed 783 * 784 * Implements the Intel SmartSpeed algorithm. 785 **/ 786 s32 ixgbe_setup_mac_link_smartspeed(struct ixgbe_hw *hw, 787 ixgbe_link_speed speed, 788 bool autoneg_wait_to_complete) 789 { 790 s32 status = IXGBE_SUCCESS; 791 ixgbe_link_speed link_speed = IXGBE_LINK_SPEED_UNKNOWN; 792 s32 i, j; 793 bool link_up = false; 794 u32 autoc_reg = IXGBE_READ_REG(hw, IXGBE_AUTOC); 795 796 DEBUGFUNC("ixgbe_setup_mac_link_smartspeed"); 797 798 /* Set autoneg_advertised value based on input link speed */ 799 hw->phy.autoneg_advertised = 0; 800 801 if (speed & IXGBE_LINK_SPEED_10GB_FULL) 802 hw->phy.autoneg_advertised |= IXGBE_LINK_SPEED_10GB_FULL; 803 804 if (speed & IXGBE_LINK_SPEED_1GB_FULL) 805 hw->phy.autoneg_advertised |= IXGBE_LINK_SPEED_1GB_FULL; 806 807 if (speed & IXGBE_LINK_SPEED_100_FULL) 808 hw->phy.autoneg_advertised |= IXGBE_LINK_SPEED_100_FULL; 809 810 /* 811 * Implement Intel SmartSpeed algorithm. SmartSpeed will reduce the 812 * autoneg advertisement if link is unable to be established at the 813 * highest negotiated rate. This can sometimes happen due to integrity 814 * issues with the physical media connection. 815 */ 816 817 /* First, try to get link with full advertisement */ 818 hw->phy.smart_speed_active = false; 819 for (j = 0; j < IXGBE_SMARTSPEED_MAX_RETRIES; j++) { 820 status = ixgbe_setup_mac_link_82599(hw, speed, 821 autoneg_wait_to_complete); 822 if (status != IXGBE_SUCCESS) 823 goto out; 824 825 /* 826 * Wait for the controller to acquire link. Per IEEE 802.3ap, 827 * Section 73.10.2, we may have to wait up to 500ms if KR is 828 * attempted, or 200ms if KX/KX4/BX/BX4 is attempted, per 829 * Table 9 in the AN MAS. 830 */ 831 for (i = 0; i < 5; i++) { 832 msec_delay(100); 833 834 /* If we have link, just jump out */ 835 status = ixgbe_check_link(hw, &link_speed, &link_up, 836 false); 837 if (status != IXGBE_SUCCESS) 838 goto out; 839 840 if (link_up) 841 goto out; 842 } 843 } 844 845 /* 846 * We didn't get link. If we advertised KR plus one of KX4/KX 847 * (or BX4/BX), then disable KR and try again. 848 */ 849 if (((autoc_reg & IXGBE_AUTOC_KR_SUPP) == 0) || 850 ((autoc_reg & IXGBE_AUTOC_KX4_KX_SUPP_MASK) == 0)) 851 goto out; 852 853 /* Turn SmartSpeed on to disable KR support */ 854 hw->phy.smart_speed_active = true; 855 status = ixgbe_setup_mac_link_82599(hw, speed, 856 autoneg_wait_to_complete); 857 if (status != IXGBE_SUCCESS) 858 goto out; 859 860 /* 861 * Wait for the controller to acquire link. 600ms will allow for 862 * the AN link_fail_inhibit_timer as well for multiple cycles of 863 * parallel detect, both 10g and 1g. This allows for the maximum 864 * connect attempts as defined in the AN MAS table 73-7. 865 */ 866 for (i = 0; i < 6; i++) { 867 msec_delay(100); 868 869 /* If we have link, just jump out */ 870 status = ixgbe_check_link(hw, &link_speed, &link_up, false); 871 if (status != IXGBE_SUCCESS) 872 goto out; 873 874 if (link_up) 875 goto out; 876 } 877 878 /* We didn't get link. Turn SmartSpeed back off. */ 879 hw->phy.smart_speed_active = false; 880 status = ixgbe_setup_mac_link_82599(hw, speed, 881 autoneg_wait_to_complete); 882 883 out: 884 if (link_up && (link_speed == IXGBE_LINK_SPEED_1GB_FULL)) 885 DEBUGOUT("Smartspeed has downgraded the link speed " 886 "from the maximum advertised\n"); 887 return status; 888 } 889 890 /** 891 * ixgbe_setup_mac_link_82599 - Set MAC link speed 892 * @hw: pointer to hardware structure 893 * @speed: new link speed 894 * @autoneg_wait_to_complete: true when waiting for completion is needed 895 * 896 * Set the link speed in the AUTOC register and restarts link. 897 **/ 898 s32 ixgbe_setup_mac_link_82599(struct ixgbe_hw *hw, 899 ixgbe_link_speed speed, 900 bool autoneg_wait_to_complete) 901 { 902 bool autoneg = false; 903 s32 status = IXGBE_SUCCESS; 904 u32 pma_pmd_1g, link_mode; 905 u32 current_autoc = IXGBE_READ_REG(hw, IXGBE_AUTOC); /* holds the value of AUTOC register at this current point in time */ 906 u32 orig_autoc = 0; /* holds the cached value of AUTOC register */ 907 u32 autoc = current_autoc; /* Temporary variable used for comparison purposes */ 908 u32 autoc2 = IXGBE_READ_REG(hw, IXGBE_AUTOC2); 909 u32 pma_pmd_10g_serial = autoc2 & IXGBE_AUTOC2_10G_SERIAL_PMA_PMD_MASK; 910 u32 links_reg; 911 u32 i; 912 ixgbe_link_speed link_capabilities = IXGBE_LINK_SPEED_UNKNOWN; 913 914 DEBUGFUNC("ixgbe_setup_mac_link_82599"); 915 916 /* Check to see if speed passed in is supported. */ 917 status = ixgbe_get_link_capabilities(hw, &link_capabilities, &autoneg); 918 if (status) 919 goto out; 920 921 speed &= link_capabilities; 922 923 if (speed == IXGBE_LINK_SPEED_UNKNOWN) { 924 status = IXGBE_ERR_LINK_SETUP; 925 goto out; 926 } 927 928 /* Use stored value (EEPROM defaults) of AUTOC to find KR/KX4 support*/ 929 if (hw->mac.orig_link_settings_stored) 930 orig_autoc = hw->mac.orig_autoc; 931 else 932 orig_autoc = autoc; 933 934 link_mode = autoc & IXGBE_AUTOC_LMS_MASK; 935 pma_pmd_1g = autoc & IXGBE_AUTOC_1G_PMA_PMD_MASK; 936 937 if (link_mode == IXGBE_AUTOC_LMS_KX4_KX_KR || 938 link_mode == IXGBE_AUTOC_LMS_KX4_KX_KR_1G_AN || 939 link_mode == IXGBE_AUTOC_LMS_KX4_KX_KR_SGMII) { 940 /* Set KX4/KX/KR support according to speed requested */ 941 autoc &= ~(IXGBE_AUTOC_KX4_KX_SUPP_MASK | IXGBE_AUTOC_KR_SUPP); 942 if (speed & IXGBE_LINK_SPEED_10GB_FULL) { 943 if (orig_autoc & IXGBE_AUTOC_KX4_SUPP) 944 autoc |= IXGBE_AUTOC_KX4_SUPP; 945 if ((orig_autoc & IXGBE_AUTOC_KR_SUPP) && 946 (hw->phy.smart_speed_active == false)) 947 autoc |= IXGBE_AUTOC_KR_SUPP; 948 } 949 if (speed & IXGBE_LINK_SPEED_1GB_FULL) 950 autoc |= IXGBE_AUTOC_KX_SUPP; 951 } else if ((pma_pmd_1g == IXGBE_AUTOC_1G_SFI) && 952 (link_mode == IXGBE_AUTOC_LMS_1G_LINK_NO_AN || 953 link_mode == IXGBE_AUTOC_LMS_1G_AN)) { 954 /* Switch from 1G SFI to 10G SFI if requested */ 955 if ((speed == IXGBE_LINK_SPEED_10GB_FULL) && 956 (pma_pmd_10g_serial == IXGBE_AUTOC2_10G_SFI)) { 957 autoc &= ~IXGBE_AUTOC_LMS_MASK; 958 autoc |= IXGBE_AUTOC_LMS_10G_SERIAL; 959 } 960 } else if ((pma_pmd_10g_serial == IXGBE_AUTOC2_10G_SFI) && 961 (link_mode == IXGBE_AUTOC_LMS_10G_SERIAL)) { 962 /* Switch from 10G SFI to 1G SFI if requested */ 963 if ((speed == IXGBE_LINK_SPEED_1GB_FULL) && 964 (pma_pmd_1g == IXGBE_AUTOC_1G_SFI)) { 965 autoc &= ~IXGBE_AUTOC_LMS_MASK; 966 if (autoneg || hw->phy.type == ixgbe_phy_qsfp_intel) 967 autoc |= IXGBE_AUTOC_LMS_1G_AN; 968 else 969 autoc |= IXGBE_AUTOC_LMS_1G_LINK_NO_AN; 970 } 971 } 972 973 if (autoc != current_autoc) { 974 /* Restart link */ 975 status = hw->mac.ops.prot_autoc_write(hw, autoc, false); 976 if (status != IXGBE_SUCCESS) 977 goto out; 978 979 /* Only poll for autoneg to complete if specified to do so */ 980 if (autoneg_wait_to_complete) { 981 if (link_mode == IXGBE_AUTOC_LMS_KX4_KX_KR || 982 link_mode == IXGBE_AUTOC_LMS_KX4_KX_KR_1G_AN || 983 link_mode == IXGBE_AUTOC_LMS_KX4_KX_KR_SGMII) { 984 links_reg = 0; /*Just in case Autoneg time=0*/ 985 for (i = 0; i < IXGBE_AUTO_NEG_TIME; i++) { 986 links_reg = 987 IXGBE_READ_REG(hw, IXGBE_LINKS); 988 if (links_reg & IXGBE_LINKS_KX_AN_COMP) 989 break; 990 msec_delay(100); 991 } 992 if (!(links_reg & IXGBE_LINKS_KX_AN_COMP)) { 993 status = 994 IXGBE_ERR_AUTONEG_NOT_COMPLETE; 995 DEBUGOUT("Autoneg did not complete.\n"); 996 } 997 } 998 } 999 1000 /* Add delay to filter out noises during initial link setup */ 1001 msec_delay(50); 1002 } 1003 1004 out: 1005 return status; 1006 } 1007 1008 /** 1009 * ixgbe_setup_copper_link_82599 - Set the PHY autoneg advertised field 1010 * @hw: pointer to hardware structure 1011 * @speed: new link speed 1012 * @autoneg_wait_to_complete: true if waiting is needed to complete 1013 * 1014 * Restarts link on PHY and MAC based on settings passed in. 1015 **/ 1016 static s32 ixgbe_setup_copper_link_82599(struct ixgbe_hw *hw, 1017 ixgbe_link_speed speed, 1018 bool autoneg_wait_to_complete) 1019 { 1020 s32 status; 1021 1022 DEBUGFUNC("ixgbe_setup_copper_link_82599"); 1023 1024 /* Setup the PHY according to input speed */ 1025 status = hw->phy.ops.setup_link_speed(hw, speed, 1026 autoneg_wait_to_complete); 1027 /* Set up MAC */ 1028 ixgbe_start_mac_link_82599(hw, autoneg_wait_to_complete); 1029 1030 return status; 1031 } 1032 1033 /** 1034 * ixgbe_reset_hw_82599 - Perform hardware reset 1035 * @hw: pointer to hardware structure 1036 * 1037 * Resets the hardware by resetting the transmit and receive units, masks 1038 * and clears all interrupts, perform a PHY reset, and perform a link (MAC) 1039 * reset. 1040 **/ 1041 s32 ixgbe_reset_hw_82599(struct ixgbe_hw *hw) 1042 { 1043 ixgbe_link_speed link_speed; 1044 s32 status; 1045 u32 ctrl = 0; 1046 u32 i, autoc, autoc2; 1047 u32 curr_lms; 1048 bool link_up = false; 1049 1050 DEBUGFUNC("ixgbe_reset_hw_82599"); 1051 1052 /* Call adapter stop to disable tx/rx and clear interrupts */ 1053 status = hw->mac.ops.stop_adapter(hw); 1054 if (status != IXGBE_SUCCESS) 1055 goto reset_hw_out; 1056 1057 /* flush pending Tx transactions */ 1058 ixgbe_clear_tx_pending(hw); 1059 1060 /* PHY ops must be identified and initialized prior to reset */ 1061 1062 /* Identify PHY and related function pointers */ 1063 status = hw->phy.ops.init(hw); 1064 1065 if (status == IXGBE_ERR_SFP_NOT_SUPPORTED) 1066 goto reset_hw_out; 1067 1068 /* Setup SFP module if there is one present. */ 1069 if (hw->phy.sfp_setup_needed) { 1070 status = hw->mac.ops.setup_sfp(hw); 1071 hw->phy.sfp_setup_needed = false; 1072 } 1073 1074 if (status == IXGBE_ERR_SFP_NOT_SUPPORTED) 1075 goto reset_hw_out; 1076 1077 /* Reset PHY */ 1078 if (hw->phy.reset_disable == false && hw->phy.ops.reset != NULL) 1079 hw->phy.ops.reset(hw); 1080 1081 /* remember AUTOC from before we reset */ 1082 curr_lms = IXGBE_READ_REG(hw, IXGBE_AUTOC) & IXGBE_AUTOC_LMS_MASK; 1083 1084 mac_reset_top: 1085 /* 1086 * Issue global reset to the MAC. Needs to be SW reset if link is up. 1087 * If link reset is used when link is up, it might reset the PHY when 1088 * mng is using it. If link is down or the flag to force full link 1089 * reset is set, then perform link reset. 1090 */ 1091 ctrl = IXGBE_CTRL_LNK_RST; 1092 if (!hw->force_full_reset) { 1093 hw->mac.ops.check_link(hw, &link_speed, &link_up, false); 1094 if (link_up) 1095 ctrl = IXGBE_CTRL_RST; 1096 } 1097 1098 ctrl |= IXGBE_READ_REG(hw, IXGBE_CTRL); 1099 IXGBE_WRITE_REG(hw, IXGBE_CTRL, ctrl); 1100 IXGBE_WRITE_FLUSH(hw); 1101 1102 /* Poll for reset bit to self-clear meaning reset is complete */ 1103 for (i = 0; i < 10; i++) { 1104 usec_delay(1); 1105 ctrl = IXGBE_READ_REG(hw, IXGBE_CTRL); 1106 if (!(ctrl & IXGBE_CTRL_RST_MASK)) 1107 break; 1108 } 1109 1110 if (ctrl & IXGBE_CTRL_RST_MASK) { 1111 status = IXGBE_ERR_RESET_FAILED; 1112 DEBUGOUT("Reset polling failed to complete.\n"); 1113 } 1114 1115 msec_delay(50); 1116 1117 /* 1118 * Double resets are required for recovery from certain error 1119 * conditions. Between resets, it is necessary to stall to 1120 * allow time for any pending HW events to complete. 1121 */ 1122 if (hw->mac.flags & IXGBE_FLAGS_DOUBLE_RESET_REQUIRED) { 1123 hw->mac.flags &= ~IXGBE_FLAGS_DOUBLE_RESET_REQUIRED; 1124 goto mac_reset_top; 1125 } 1126 1127 /* 1128 * Store the original AUTOC/AUTOC2 values if they have not been 1129 * stored off yet. Otherwise restore the stored original 1130 * values since the reset operation sets back to defaults. 1131 */ 1132 autoc = IXGBE_READ_REG(hw, IXGBE_AUTOC); 1133 autoc2 = IXGBE_READ_REG(hw, IXGBE_AUTOC2); 1134 1135 /* Enable link if disabled in NVM */ 1136 if (autoc2 & IXGBE_AUTOC2_LINK_DISABLE_MASK) { 1137 autoc2 &= ~IXGBE_AUTOC2_LINK_DISABLE_MASK; 1138 IXGBE_WRITE_REG(hw, IXGBE_AUTOC2, autoc2); 1139 IXGBE_WRITE_FLUSH(hw); 1140 } 1141 1142 if (hw->mac.orig_link_settings_stored == false) { 1143 hw->mac.orig_autoc = autoc; 1144 hw->mac.orig_autoc2 = autoc2; 1145 hw->mac.orig_link_settings_stored = true; 1146 } else { 1147 1148 /* If MNG FW is running on a multi-speed device that 1149 * doesn't autoneg with out driver support we need to 1150 * leave LMS in the state it was before we MAC reset. 1151 * Likewise if we support WoL we don't want change the 1152 * LMS state. 1153 */ 1154 if ((hw->phy.multispeed_fiber && ixgbe_mng_enabled(hw)) || 1155 hw->wol_enabled) 1156 hw->mac.orig_autoc = 1157 (hw->mac.orig_autoc & ~IXGBE_AUTOC_LMS_MASK) | 1158 curr_lms; 1159 1160 if (autoc != hw->mac.orig_autoc) { 1161 status = hw->mac.ops.prot_autoc_write(hw, 1162 hw->mac.orig_autoc, 1163 false); 1164 if (status != IXGBE_SUCCESS) 1165 goto reset_hw_out; 1166 } 1167 1168 if ((autoc2 & IXGBE_AUTOC2_UPPER_MASK) != 1169 (hw->mac.orig_autoc2 & IXGBE_AUTOC2_UPPER_MASK)) { 1170 autoc2 &= ~IXGBE_AUTOC2_UPPER_MASK; 1171 autoc2 |= (hw->mac.orig_autoc2 & 1172 IXGBE_AUTOC2_UPPER_MASK); 1173 IXGBE_WRITE_REG(hw, IXGBE_AUTOC2, autoc2); 1174 } 1175 } 1176 1177 /* Store the permanent mac address */ 1178 hw->mac.ops.get_mac_addr(hw, hw->mac.perm_addr); 1179 1180 /* 1181 * Store MAC address from RAR0, clear receive address registers, and 1182 * clear the multicast table. Also reset num_rar_entries to 128, 1183 * since we modify this value when programming the SAN MAC address. 1184 */ 1185 hw->mac.num_rar_entries = 128; 1186 hw->mac.ops.init_rx_addrs(hw); 1187 1188 /* Store the permanent SAN mac address */ 1189 hw->mac.ops.get_san_mac_addr(hw, hw->mac.san_addr); 1190 1191 /* Add the SAN MAC address to the RAR only if it's a valid address */ 1192 if (ixgbe_validate_mac_addr(hw->mac.san_addr) == 0) { 1193 /* Save the SAN MAC RAR index */ 1194 hw->mac.san_mac_rar_index = hw->mac.num_rar_entries - 1; 1195 1196 hw->mac.ops.set_rar(hw, hw->mac.san_mac_rar_index, 1197 hw->mac.san_addr, 0, IXGBE_RAH_AV); 1198 1199 /* clear VMDq pool/queue selection for this RAR */ 1200 hw->mac.ops.clear_vmdq(hw, hw->mac.san_mac_rar_index, 1201 IXGBE_CLEAR_VMDQ_ALL); 1202 1203 /* Reserve the last RAR for the SAN MAC address */ 1204 hw->mac.num_rar_entries--; 1205 } 1206 1207 /* Store the alternative WWNN/WWPN prefix */ 1208 hw->mac.ops.get_wwn_prefix(hw, &hw->mac.wwnn_prefix, 1209 &hw->mac.wwpn_prefix); 1210 1211 reset_hw_out: 1212 return status; 1213 } 1214 1215 /** 1216 * ixgbe_fdir_check_cmd_complete - poll to check whether FDIRCMD is complete 1217 * @hw: pointer to hardware structure 1218 * @fdircmd: current value of FDIRCMD register 1219 */ 1220 static s32 ixgbe_fdir_check_cmd_complete(struct ixgbe_hw *hw, u32 *fdircmd) 1221 { 1222 int i; 1223 1224 for (i = 0; i < IXGBE_FDIRCMD_CMD_POLL; i++) { 1225 *fdircmd = IXGBE_READ_REG(hw, IXGBE_FDIRCMD); 1226 if (!(*fdircmd & IXGBE_FDIRCMD_CMD_MASK)) 1227 return IXGBE_SUCCESS; 1228 usec_delay(10); 1229 } 1230 1231 return IXGBE_ERR_FDIR_CMD_INCOMPLETE; 1232 } 1233 1234 /** 1235 * ixgbe_reinit_fdir_tables_82599 - Reinitialize Flow Director tables. 1236 * @hw: pointer to hardware structure 1237 **/ 1238 s32 ixgbe_reinit_fdir_tables_82599(struct ixgbe_hw *hw) 1239 { 1240 s32 err; 1241 int i; 1242 u32 fdirctrl = IXGBE_READ_REG(hw, IXGBE_FDIRCTRL); 1243 u32 fdircmd; 1244 fdirctrl &= ~IXGBE_FDIRCTRL_INIT_DONE; 1245 1246 DEBUGFUNC("ixgbe_reinit_fdir_tables_82599"); 1247 1248 /* 1249 * Before starting reinitialization process, 1250 * FDIRCMD.CMD must be zero. 1251 */ 1252 err = ixgbe_fdir_check_cmd_complete(hw, &fdircmd); 1253 if (err) { 1254 DEBUGOUT("Flow Director previous command did not complete, aborting table re-initialization.\n"); 1255 return err; 1256 } 1257 1258 IXGBE_WRITE_REG(hw, IXGBE_FDIRFREE, 0); 1259 IXGBE_WRITE_FLUSH(hw); 1260 /* 1261 * 82599 adapters flow director init flow cannot be restarted, 1262 * Workaround 82599 silicon errata by performing the following steps 1263 * before re-writing the FDIRCTRL control register with the same value. 1264 * - write 1 to bit 8 of FDIRCMD register & 1265 * - write 0 to bit 8 of FDIRCMD register 1266 */ 1267 IXGBE_WRITE_REG(hw, IXGBE_FDIRCMD, 1268 (IXGBE_READ_REG(hw, IXGBE_FDIRCMD) | 1269 IXGBE_FDIRCMD_CLEARHT)); 1270 IXGBE_WRITE_FLUSH(hw); 1271 IXGBE_WRITE_REG(hw, IXGBE_FDIRCMD, 1272 (IXGBE_READ_REG(hw, IXGBE_FDIRCMD) & 1273 ~IXGBE_FDIRCMD_CLEARHT)); 1274 IXGBE_WRITE_FLUSH(hw); 1275 /* 1276 * Clear FDIR Hash register to clear any leftover hashes 1277 * waiting to be programmed. 1278 */ 1279 IXGBE_WRITE_REG(hw, IXGBE_FDIRHASH, 0x00); 1280 IXGBE_WRITE_FLUSH(hw); 1281 1282 IXGBE_WRITE_REG(hw, IXGBE_FDIRCTRL, fdirctrl); 1283 IXGBE_WRITE_FLUSH(hw); 1284 1285 /* Poll init-done after we write FDIRCTRL register */ 1286 for (i = 0; i < IXGBE_FDIR_INIT_DONE_POLL; i++) { 1287 if (IXGBE_READ_REG(hw, IXGBE_FDIRCTRL) & 1288 IXGBE_FDIRCTRL_INIT_DONE) 1289 break; 1290 msec_delay(1); 1291 } 1292 if (i >= IXGBE_FDIR_INIT_DONE_POLL) { 1293 DEBUGOUT("Flow Director Signature poll time exceeded!\n"); 1294 return IXGBE_ERR_FDIR_REINIT_FAILED; 1295 } 1296 1297 /* Clear FDIR statistics registers (read to clear) */ 1298 IXGBE_READ_REG(hw, IXGBE_FDIRUSTAT); 1299 IXGBE_READ_REG(hw, IXGBE_FDIRFSTAT); 1300 IXGBE_READ_REG(hw, IXGBE_FDIRMATCH); 1301 IXGBE_READ_REG(hw, IXGBE_FDIRMISS); 1302 IXGBE_READ_REG(hw, IXGBE_FDIRLEN); 1303 1304 return IXGBE_SUCCESS; 1305 } 1306 1307 /** 1308 * ixgbe_fdir_enable_82599 - Initialize Flow Director control registers 1309 * @hw: pointer to hardware structure 1310 * @fdirctrl: value to write to flow director control register 1311 **/ 1312 static void ixgbe_fdir_enable_82599(struct ixgbe_hw *hw, u32 fdirctrl) 1313 { 1314 int i; 1315 1316 DEBUGFUNC("ixgbe_fdir_enable_82599"); 1317 1318 /* Prime the keys for hashing */ 1319 IXGBE_WRITE_REG(hw, IXGBE_FDIRHKEY, IXGBE_ATR_BUCKET_HASH_KEY); 1320 IXGBE_WRITE_REG(hw, IXGBE_FDIRSKEY, IXGBE_ATR_SIGNATURE_HASH_KEY); 1321 1322 /* 1323 * Poll init-done after we write the register. Estimated times: 1324 * 10G: PBALLOC = 11b, timing is 60us 1325 * 1G: PBALLOC = 11b, timing is 600us 1326 * 100M: PBALLOC = 11b, timing is 6ms 1327 * 1328 * Multiple these timings by 4 if under full Rx load 1329 * 1330 * So we'll poll for IXGBE_FDIR_INIT_DONE_POLL times, sleeping for 1331 * 1 msec per poll time. If we're at line rate and drop to 100M, then 1332 * this might not finish in our poll time, but we can live with that 1333 * for now. 1334 */ 1335 IXGBE_WRITE_REG(hw, IXGBE_FDIRCTRL, fdirctrl); 1336 IXGBE_WRITE_FLUSH(hw); 1337 for (i = 0; i < IXGBE_FDIR_INIT_DONE_POLL; i++) { 1338 if (IXGBE_READ_REG(hw, IXGBE_FDIRCTRL) & 1339 IXGBE_FDIRCTRL_INIT_DONE) 1340 break; 1341 msec_delay(1); 1342 } 1343 1344 if (i >= IXGBE_FDIR_INIT_DONE_POLL) 1345 DEBUGOUT("Flow Director poll time exceeded!\n"); 1346 } 1347 1348 /** 1349 * ixgbe_init_fdir_signature_82599 - Initialize Flow Director signature filters 1350 * @hw: pointer to hardware structure 1351 * @fdirctrl: value to write to flow director control register, initially 1352 * contains just the value of the Rx packet buffer allocation 1353 **/ 1354 s32 ixgbe_init_fdir_signature_82599(struct ixgbe_hw *hw, u32 fdirctrl) 1355 { 1356 DEBUGFUNC("ixgbe_init_fdir_signature_82599"); 1357 1358 /* 1359 * Continue setup of fdirctrl register bits: 1360 * Move the flexible bytes to use the ethertype - shift 6 words 1361 * Set the maximum length per hash bucket to 0xA filters 1362 * Send interrupt when 64 filters are left 1363 */ 1364 fdirctrl |= (0x6 << IXGBE_FDIRCTRL_FLEX_SHIFT) | 1365 (0xA << IXGBE_FDIRCTRL_MAX_LENGTH_SHIFT) | 1366 (4 << IXGBE_FDIRCTRL_FULL_THRESH_SHIFT); 1367 1368 /* write hashes and fdirctrl register, poll for completion */ 1369 ixgbe_fdir_enable_82599(hw, fdirctrl); 1370 1371 return IXGBE_SUCCESS; 1372 } 1373 1374 /** 1375 * ixgbe_init_fdir_perfect_82599 - Initialize Flow Director perfect filters 1376 * @hw: pointer to hardware structure 1377 * @fdirctrl: value to write to flow director control register, initially 1378 * contains just the value of the Rx packet buffer allocation 1379 * @cloud_mode: true - cloud mode, false - other mode 1380 **/ 1381 s32 ixgbe_init_fdir_perfect_82599(struct ixgbe_hw *hw, u32 fdirctrl, 1382 bool cloud_mode) 1383 { 1384 UNREFERENCED_1PARAMETER(cloud_mode); 1385 DEBUGFUNC("ixgbe_init_fdir_perfect_82599"); 1386 1387 /* 1388 * Continue setup of fdirctrl register bits: 1389 * Turn perfect match filtering on 1390 * Report hash in RSS field of Rx wb descriptor 1391 * Initialize the drop queue to queue 127 1392 * Move the flexible bytes to use the ethertype - shift 6 words 1393 * Set the maximum length per hash bucket to 0xA filters 1394 * Send interrupt when 64 (0x4 * 16) filters are left 1395 */ 1396 fdirctrl |= IXGBE_FDIRCTRL_PERFECT_MATCH | 1397 IXGBE_FDIRCTRL_REPORT_STATUS | 1398 (IXGBE_FDIR_DROP_QUEUE << IXGBE_FDIRCTRL_DROP_Q_SHIFT) | 1399 (0x6 << IXGBE_FDIRCTRL_FLEX_SHIFT) | 1400 (0xA << IXGBE_FDIRCTRL_MAX_LENGTH_SHIFT) | 1401 (4 << IXGBE_FDIRCTRL_FULL_THRESH_SHIFT); 1402 1403 if (cloud_mode) 1404 fdirctrl |=(IXGBE_FDIRCTRL_FILTERMODE_CLOUD << 1405 IXGBE_FDIRCTRL_FILTERMODE_SHIFT); 1406 1407 /* write hashes and fdirctrl register, poll for completion */ 1408 ixgbe_fdir_enable_82599(hw, fdirctrl); 1409 1410 return IXGBE_SUCCESS; 1411 } 1412 1413 /** 1414 * ixgbe_set_fdir_drop_queue_82599 - Set Flow Director drop queue 1415 * @hw: pointer to hardware structure 1416 * @dropqueue: Rx queue index used for the dropped packets 1417 **/ 1418 void ixgbe_set_fdir_drop_queue_82599(struct ixgbe_hw *hw, u8 dropqueue) 1419 { 1420 u32 fdirctrl; 1421 1422 DEBUGFUNC("ixgbe_set_fdir_drop_queue_82599"); 1423 /* Clear init done bit and drop queue field */ 1424 fdirctrl = IXGBE_READ_REG(hw, IXGBE_FDIRCTRL); 1425 fdirctrl &= ~(IXGBE_FDIRCTRL_DROP_Q_MASK | IXGBE_FDIRCTRL_INIT_DONE); 1426 1427 /* Set drop queue */ 1428 fdirctrl |= (dropqueue << IXGBE_FDIRCTRL_DROP_Q_SHIFT); 1429 if ((hw->mac.type == ixgbe_mac_X550) || 1430 (hw->mac.type == ixgbe_mac_X550EM_x) || 1431 (hw->mac.type == ixgbe_mac_X550EM_a)) 1432 fdirctrl |= IXGBE_FDIRCTRL_DROP_NO_MATCH; 1433 1434 IXGBE_WRITE_REG(hw, IXGBE_FDIRCMD, 1435 (IXGBE_READ_REG(hw, IXGBE_FDIRCMD) | 1436 IXGBE_FDIRCMD_CLEARHT)); 1437 IXGBE_WRITE_FLUSH(hw); 1438 IXGBE_WRITE_REG(hw, IXGBE_FDIRCMD, 1439 (IXGBE_READ_REG(hw, IXGBE_FDIRCMD) & 1440 ~IXGBE_FDIRCMD_CLEARHT)); 1441 IXGBE_WRITE_FLUSH(hw); 1442 1443 /* write hashes and fdirctrl register, poll for completion */ 1444 ixgbe_fdir_enable_82599(hw, fdirctrl); 1445 } 1446 1447 /* 1448 * These defines allow us to quickly generate all of the necessary instructions 1449 * in the function below by simply calling out IXGBE_COMPUTE_SIG_HASH_ITERATION 1450 * for values 0 through 15 1451 */ 1452 #define IXGBE_ATR_COMMON_HASH_KEY \ 1453 (IXGBE_ATR_BUCKET_HASH_KEY & IXGBE_ATR_SIGNATURE_HASH_KEY) 1454 #define IXGBE_COMPUTE_SIG_HASH_ITERATION(_n) \ 1455 do { \ 1456 u32 n = (_n); \ 1457 if (IXGBE_ATR_COMMON_HASH_KEY & (0x01 << n)) \ 1458 common_hash ^= lo_hash_dword >> n; \ 1459 else if (IXGBE_ATR_BUCKET_HASH_KEY & (0x01 << n)) \ 1460 bucket_hash ^= lo_hash_dword >> n; \ 1461 else if (IXGBE_ATR_SIGNATURE_HASH_KEY & (0x01 << n)) \ 1462 sig_hash ^= lo_hash_dword << (16 - n); \ 1463 if (IXGBE_ATR_COMMON_HASH_KEY & (0x01 << (n + 16))) \ 1464 common_hash ^= hi_hash_dword >> n; \ 1465 else if (IXGBE_ATR_BUCKET_HASH_KEY & (0x01 << (n + 16))) \ 1466 bucket_hash ^= hi_hash_dword >> n; \ 1467 else if (IXGBE_ATR_SIGNATURE_HASH_KEY & (0x01 << (n + 16))) \ 1468 sig_hash ^= hi_hash_dword << (16 - n); \ 1469 } while (0) 1470 1471 /** 1472 * ixgbe_atr_compute_sig_hash_82599 - Compute the signature hash 1473 * @input: input bitstream to compute the hash on 1474 * @common: compressed common input dword 1475 * 1476 * This function is almost identical to the function above but contains 1477 * several optimizations such as unwinding all of the loops, letting the 1478 * compiler work out all of the conditional ifs since the keys are static 1479 * defines, and computing two keys at once since the hashed dword stream 1480 * will be the same for both keys. 1481 **/ 1482 u32 ixgbe_atr_compute_sig_hash_82599(union ixgbe_atr_hash_dword input, 1483 union ixgbe_atr_hash_dword common) 1484 { 1485 u32 hi_hash_dword, lo_hash_dword, flow_vm_vlan; 1486 u32 sig_hash = 0, bucket_hash = 0, common_hash = 0; 1487 1488 /* record the flow_vm_vlan bits as they are a key part to the hash */ 1489 flow_vm_vlan = IXGBE_NTOHL(input.dword); 1490 1491 /* generate common hash dword */ 1492 hi_hash_dword = IXGBE_NTOHL(common.dword); 1493 1494 /* low dword is word swapped version of common */ 1495 lo_hash_dword = (hi_hash_dword >> 16) | (hi_hash_dword << 16); 1496 1497 /* apply flow ID/VM pool/VLAN ID bits to hash words */ 1498 hi_hash_dword ^= flow_vm_vlan ^ (flow_vm_vlan >> 16); 1499 1500 /* Process bits 0 and 16 */ 1501 IXGBE_COMPUTE_SIG_HASH_ITERATION(0); 1502 1503 /* 1504 * apply flow ID/VM pool/VLAN ID bits to lo hash dword, we had to 1505 * delay this because bit 0 of the stream should not be processed 1506 * so we do not add the VLAN until after bit 0 was processed 1507 */ 1508 lo_hash_dword ^= flow_vm_vlan ^ (flow_vm_vlan << 16); 1509 1510 /* Process remaining 30 bit of the key */ 1511 IXGBE_COMPUTE_SIG_HASH_ITERATION(1); 1512 IXGBE_COMPUTE_SIG_HASH_ITERATION(2); 1513 IXGBE_COMPUTE_SIG_HASH_ITERATION(3); 1514 IXGBE_COMPUTE_SIG_HASH_ITERATION(4); 1515 IXGBE_COMPUTE_SIG_HASH_ITERATION(5); 1516 IXGBE_COMPUTE_SIG_HASH_ITERATION(6); 1517 IXGBE_COMPUTE_SIG_HASH_ITERATION(7); 1518 IXGBE_COMPUTE_SIG_HASH_ITERATION(8); 1519 IXGBE_COMPUTE_SIG_HASH_ITERATION(9); 1520 IXGBE_COMPUTE_SIG_HASH_ITERATION(10); 1521 IXGBE_COMPUTE_SIG_HASH_ITERATION(11); 1522 IXGBE_COMPUTE_SIG_HASH_ITERATION(12); 1523 IXGBE_COMPUTE_SIG_HASH_ITERATION(13); 1524 IXGBE_COMPUTE_SIG_HASH_ITERATION(14); 1525 IXGBE_COMPUTE_SIG_HASH_ITERATION(15); 1526 1527 /* combine common_hash result with signature and bucket hashes */ 1528 bucket_hash ^= common_hash; 1529 bucket_hash &= IXGBE_ATR_HASH_MASK; 1530 1531 sig_hash ^= common_hash << 16; 1532 sig_hash &= IXGBE_ATR_HASH_MASK << 16; 1533 1534 /* return completed signature hash */ 1535 return sig_hash ^ bucket_hash; 1536 } 1537 1538 /** 1539 * ixgbe_atr_add_signature_filter_82599 - Adds a signature hash filter 1540 * @hw: pointer to hardware structure 1541 * @input: unique input dword 1542 * @common: compressed common input dword 1543 * @queue: queue index to direct traffic to 1544 * 1545 * Note that the tunnel bit in input must not be set when the hardware 1546 * tunneling support does not exist. 1547 **/ 1548 void ixgbe_fdir_add_signature_filter_82599(struct ixgbe_hw *hw, 1549 union ixgbe_atr_hash_dword input, 1550 union ixgbe_atr_hash_dword common, 1551 u8 queue) 1552 { 1553 u64 fdirhashcmd; 1554 u8 flow_type; 1555 bool tunnel; 1556 u32 fdircmd; 1557 1558 DEBUGFUNC("ixgbe_fdir_add_signature_filter_82599"); 1559 1560 /* 1561 * Get the flow_type in order to program FDIRCMD properly 1562 * lowest 2 bits are FDIRCMD.L4TYPE, third lowest bit is FDIRCMD.IPV6 1563 * fifth is FDIRCMD.TUNNEL_FILTER 1564 */ 1565 tunnel = !!(input.formatted.flow_type & IXGBE_ATR_L4TYPE_TUNNEL_MASK); 1566 flow_type = input.formatted.flow_type & 1567 (IXGBE_ATR_L4TYPE_TUNNEL_MASK - 1); 1568 switch (flow_type) { 1569 case IXGBE_ATR_FLOW_TYPE_TCPV4: 1570 case IXGBE_ATR_FLOW_TYPE_UDPV4: 1571 case IXGBE_ATR_FLOW_TYPE_SCTPV4: 1572 case IXGBE_ATR_FLOW_TYPE_TCPV6: 1573 case IXGBE_ATR_FLOW_TYPE_UDPV6: 1574 case IXGBE_ATR_FLOW_TYPE_SCTPV6: 1575 break; 1576 default: 1577 DEBUGOUT(" Error on flow type input\n"); 1578 return; 1579 } 1580 1581 /* configure FDIRCMD register */ 1582 fdircmd = IXGBE_FDIRCMD_CMD_ADD_FLOW | IXGBE_FDIRCMD_FILTER_UPDATE | 1583 IXGBE_FDIRCMD_LAST | IXGBE_FDIRCMD_QUEUE_EN; 1584 fdircmd |= (u32)flow_type << IXGBE_FDIRCMD_FLOW_TYPE_SHIFT; 1585 fdircmd |= (u32)queue << IXGBE_FDIRCMD_RX_QUEUE_SHIFT; 1586 if (tunnel) 1587 fdircmd |= IXGBE_FDIRCMD_TUNNEL_FILTER; 1588 1589 /* 1590 * The lower 32-bits of fdirhashcmd is for FDIRHASH, the upper 32-bits 1591 * is for FDIRCMD. Then do a 64-bit register write from FDIRHASH. 1592 */ 1593 fdirhashcmd = (u64)fdircmd << 32; 1594 fdirhashcmd |= (u64)ixgbe_atr_compute_sig_hash_82599(input, common); 1595 IXGBE_WRITE_REG64(hw, IXGBE_FDIRHASH, fdirhashcmd); 1596 1597 DEBUGOUT2("Tx Queue=%x hash=%x\n", queue, (u32)fdirhashcmd); 1598 1599 return; 1600 } 1601 1602 #define IXGBE_COMPUTE_BKT_HASH_ITERATION(_n) \ 1603 do { \ 1604 u32 n = (_n); \ 1605 if (IXGBE_ATR_BUCKET_HASH_KEY & (0x01 << n)) \ 1606 bucket_hash ^= lo_hash_dword >> n; \ 1607 if (IXGBE_ATR_BUCKET_HASH_KEY & (0x01 << (n + 16))) \ 1608 bucket_hash ^= hi_hash_dword >> n; \ 1609 } while (0) 1610 1611 /** 1612 * ixgbe_atr_compute_perfect_hash_82599 - Compute the perfect filter hash 1613 * @input: input bitstream to compute the hash on 1614 * @input_mask: mask for the input bitstream 1615 * 1616 * This function serves two main purposes. First it applies the input_mask 1617 * to the atr_input resulting in a cleaned up atr_input data stream. 1618 * Secondly it computes the hash and stores it in the bkt_hash field at 1619 * the end of the input byte stream. This way it will be available for 1620 * future use without needing to recompute the hash. 1621 **/ 1622 void ixgbe_atr_compute_perfect_hash_82599(union ixgbe_atr_input *input, 1623 union ixgbe_atr_input *input_mask) 1624 { 1625 1626 u32 hi_hash_dword, lo_hash_dword, flow_vm_vlan; 1627 u32 bucket_hash = 0; 1628 u32 hi_dword = 0; 1629 u32 i = 0; 1630 1631 /* Apply masks to input data */ 1632 for (i = 0; i < 14; i++) 1633 input->dword_stream[i] &= input_mask->dword_stream[i]; 1634 1635 /* record the flow_vm_vlan bits as they are a key part to the hash */ 1636 flow_vm_vlan = IXGBE_NTOHL(input->dword_stream[0]); 1637 1638 /* generate common hash dword */ 1639 for (i = 1; i <= 13; i++) 1640 hi_dword ^= input->dword_stream[i]; 1641 hi_hash_dword = IXGBE_NTOHL(hi_dword); 1642 1643 /* low dword is word swapped version of common */ 1644 lo_hash_dword = (hi_hash_dword >> 16) | (hi_hash_dword << 16); 1645 1646 /* apply flow ID/VM pool/VLAN ID bits to hash words */ 1647 hi_hash_dword ^= flow_vm_vlan ^ (flow_vm_vlan >> 16); 1648 1649 /* Process bits 0 and 16 */ 1650 IXGBE_COMPUTE_BKT_HASH_ITERATION(0); 1651 1652 /* 1653 * apply flow ID/VM pool/VLAN ID bits to lo hash dword, we had to 1654 * delay this because bit 0 of the stream should not be processed 1655 * so we do not add the VLAN until after bit 0 was processed 1656 */ 1657 lo_hash_dword ^= flow_vm_vlan ^ (flow_vm_vlan << 16); 1658 1659 /* Process remaining 30 bit of the key */ 1660 for (i = 1; i <= 15; i++) 1661 IXGBE_COMPUTE_BKT_HASH_ITERATION(i); 1662 1663 /* 1664 * Limit hash to 13 bits since max bucket count is 8K. 1665 * Store result at the end of the input stream. 1666 */ 1667 input->formatted.bkt_hash = bucket_hash & 0x1FFF; 1668 } 1669 1670 /** 1671 * ixgbe_get_fdirtcpm_82599 - generate a TCP port from atr_input_masks 1672 * @input_mask: mask to be bit swapped 1673 * 1674 * The source and destination port masks for flow director are bit swapped 1675 * in that bit 15 effects bit 0, 14 effects 1, 13, 2 etc. In order to 1676 * generate a correctly swapped value we need to bit swap the mask and that 1677 * is what is accomplished by this function. 1678 **/ 1679 static u32 ixgbe_get_fdirtcpm_82599(union ixgbe_atr_input *input_mask) 1680 { 1681 u32 mask = IXGBE_NTOHS(input_mask->formatted.dst_port); 1682 mask <<= IXGBE_FDIRTCPM_DPORTM_SHIFT; 1683 mask |= (u32)IXGBE_NTOHS(input_mask->formatted.src_port); 1684 mask = ((mask & 0x55555555) << 1) | ((mask & 0xAAAAAAAA) >> 1); 1685 mask = ((mask & 0x33333333) << 2) | ((mask & 0xCCCCCCCC) >> 2); 1686 mask = ((mask & 0x0F0F0F0F) << 4) | ((mask & 0xF0F0F0F0) >> 4); 1687 return ((mask & 0x00FF00FF) << 8) | ((mask & 0xFF00FF00) >> 8); 1688 } 1689 1690 /* 1691 * These two macros are meant to address the fact that we have registers 1692 * that are either all or in part big-endian. As a result on big-endian 1693 * systems we will end up byte swapping the value to little-endian before 1694 * it is byte swapped again and written to the hardware in the original 1695 * big-endian format. 1696 */ 1697 #define IXGBE_STORE_AS_BE32(_value) \ 1698 (((u32)(_value) >> 24) | (((u32)(_value) & 0x00FF0000) >> 8) | \ 1699 (((u32)(_value) & 0x0000FF00) << 8) | ((u32)(_value) << 24)) 1700 1701 #define IXGBE_WRITE_REG_BE32(a, reg, value) \ 1702 IXGBE_WRITE_REG((a), (reg), IXGBE_STORE_AS_BE32(IXGBE_NTOHL(value))) 1703 1704 #define IXGBE_STORE_AS_BE16(_value) \ 1705 IXGBE_NTOHS(((u16)(_value) >> 8) | ((u16)(_value) << 8)) 1706 1707 s32 ixgbe_fdir_set_input_mask_82599(struct ixgbe_hw *hw, 1708 union ixgbe_atr_input *input_mask, bool cloud_mode) 1709 { 1710 /* mask IPv6 since it is currently not supported */ 1711 u32 fdirm = IXGBE_FDIRM_DIPv6; 1712 u32 fdirtcpm; 1713 u32 fdirip6m; 1714 UNREFERENCED_1PARAMETER(cloud_mode); 1715 DEBUGFUNC("ixgbe_fdir_set_atr_input_mask_82599"); 1716 1717 /* 1718 * Program the relevant mask registers. If src/dst_port or src/dst_addr 1719 * are zero, then assume a full mask for that field. Also assume that 1720 * a VLAN of 0 is unspecified, so mask that out as well. L4type 1721 * cannot be masked out in this implementation. 1722 * 1723 * This also assumes IPv4 only. IPv6 masking isn't supported at this 1724 * point in time. 1725 */ 1726 1727 /* verify bucket hash is cleared on hash generation */ 1728 if (input_mask->formatted.bkt_hash) 1729 DEBUGOUT(" bucket hash should always be 0 in mask\n"); 1730 1731 /* Program FDIRM and verify partial masks */ 1732 switch (input_mask->formatted.vm_pool & 0x7F) { 1733 case 0x0: 1734 fdirm |= IXGBE_FDIRM_POOL; 1735 case 0x7F: 1736 break; 1737 default: 1738 DEBUGOUT(" Error on vm pool mask\n"); 1739 return IXGBE_ERR_CONFIG; 1740 } 1741 1742 switch (input_mask->formatted.flow_type & IXGBE_ATR_L4TYPE_MASK) { 1743 case 0x0: 1744 fdirm |= IXGBE_FDIRM_L4P; 1745 if (input_mask->formatted.dst_port || 1746 input_mask->formatted.src_port) { 1747 DEBUGOUT(" Error on src/dst port mask\n"); 1748 return IXGBE_ERR_CONFIG; 1749 } 1750 case IXGBE_ATR_L4TYPE_MASK: 1751 break; 1752 default: 1753 DEBUGOUT(" Error on flow type mask\n"); 1754 return IXGBE_ERR_CONFIG; 1755 } 1756 1757 switch (IXGBE_NTOHS(input_mask->formatted.vlan_id) & 0xEFFF) { 1758 case 0x0000: 1759 /* mask VLAN ID */ 1760 fdirm |= IXGBE_FDIRM_VLANID; 1761 /* FALLTHROUGH */ 1762 case 0x0FFF: 1763 /* mask VLAN priority */ 1764 fdirm |= IXGBE_FDIRM_VLANP; 1765 break; 1766 case 0xE000: 1767 /* mask VLAN ID only */ 1768 fdirm |= IXGBE_FDIRM_VLANID; 1769 /* fall through */ 1770 case 0xEFFF: 1771 /* no VLAN fields masked */ 1772 break; 1773 default: 1774 DEBUGOUT(" Error on VLAN mask\n"); 1775 return IXGBE_ERR_CONFIG; 1776 } 1777 1778 switch (input_mask->formatted.flex_bytes & 0xFFFF) { 1779 case 0x0000: 1780 /* Mask Flex Bytes */ 1781 fdirm |= IXGBE_FDIRM_FLEX; 1782 /* fall through */ 1783 case 0xFFFF: 1784 break; 1785 default: 1786 DEBUGOUT(" Error on flexible byte mask\n"); 1787 return IXGBE_ERR_CONFIG; 1788 } 1789 1790 if (cloud_mode) { 1791 fdirm |= IXGBE_FDIRM_L3P; 1792 fdirip6m = ((u32) 0xFFFFU << IXGBE_FDIRIP6M_DIPM_SHIFT); 1793 fdirip6m |= IXGBE_FDIRIP6M_ALWAYS_MASK; 1794 1795 switch (input_mask->formatted.inner_mac[0] & 0xFF) { 1796 case 0x00: 1797 /* Mask inner MAC, fall through */ 1798 fdirip6m |= IXGBE_FDIRIP6M_INNER_MAC; 1799 case 0xFF: 1800 break; 1801 default: 1802 DEBUGOUT(" Error on inner_mac byte mask\n"); 1803 return IXGBE_ERR_CONFIG; 1804 } 1805 1806 switch (input_mask->formatted.tni_vni & 0xFFFFFFFF) { 1807 case 0x0: 1808 /* Mask vxlan id */ 1809 fdirip6m |= IXGBE_FDIRIP6M_TNI_VNI; 1810 break; 1811 case 0x00FFFFFF: 1812 fdirip6m |= IXGBE_FDIRIP6M_TNI_VNI_24; 1813 break; 1814 case 0xFFFFFFFF: 1815 break; 1816 default: 1817 DEBUGOUT(" Error on TNI/VNI byte mask\n"); 1818 return IXGBE_ERR_CONFIG; 1819 } 1820 1821 switch (input_mask->formatted.tunnel_type & 0xFFFF) { 1822 case 0x0: 1823 /* Mask turnnel type, fall through */ 1824 fdirip6m |= IXGBE_FDIRIP6M_TUNNEL_TYPE; 1825 case 0xFFFF: 1826 break; 1827 default: 1828 DEBUGOUT(" Error on tunnel type byte mask\n"); 1829 return IXGBE_ERR_CONFIG; 1830 } 1831 IXGBE_WRITE_REG_BE32(hw, IXGBE_FDIRIP6M, fdirip6m); 1832 1833 /* Set all bits in FDIRTCPM, FDIRUDPM, FDIRSCTPM, 1834 * FDIRSIP4M and FDIRDIP4M in cloud mode to allow 1835 * L3/L3 packets to tunnel. 1836 */ 1837 IXGBE_WRITE_REG(hw, IXGBE_FDIRTCPM, 0xFFFFFFFF); 1838 IXGBE_WRITE_REG(hw, IXGBE_FDIRUDPM, 0xFFFFFFFF); 1839 IXGBE_WRITE_REG_BE32(hw, IXGBE_FDIRDIP4M, 0xFFFFFFFF); 1840 IXGBE_WRITE_REG_BE32(hw, IXGBE_FDIRSIP4M, 0xFFFFFFFF); 1841 switch (hw->mac.type) { 1842 case ixgbe_mac_X550: 1843 case ixgbe_mac_X550EM_x: 1844 case ixgbe_mac_X550EM_a: 1845 IXGBE_WRITE_REG(hw, IXGBE_FDIRSCTPM, 0xFFFFFFFF); 1846 break; 1847 default: 1848 break; 1849 } 1850 } 1851 1852 /* Now mask VM pool and destination IPv6 - bits 5 and 2 */ 1853 IXGBE_WRITE_REG(hw, IXGBE_FDIRM, fdirm); 1854 1855 if (!cloud_mode) { 1856 /* store the TCP/UDP port masks, bit reversed from port 1857 * layout */ 1858 fdirtcpm = ixgbe_get_fdirtcpm_82599(input_mask); 1859 1860 /* write both the same so that UDP and TCP use the same mask */ 1861 IXGBE_WRITE_REG(hw, IXGBE_FDIRTCPM, ~fdirtcpm); 1862 IXGBE_WRITE_REG(hw, IXGBE_FDIRUDPM, ~fdirtcpm); 1863 /* also use it for SCTP */ 1864 switch (hw->mac.type) { 1865 case ixgbe_mac_X550: 1866 case ixgbe_mac_X550EM_x: 1867 case ixgbe_mac_X550EM_a: 1868 IXGBE_WRITE_REG(hw, IXGBE_FDIRSCTPM, ~fdirtcpm); 1869 break; 1870 default: 1871 break; 1872 } 1873 1874 /* store source and destination IP masks (big-enian) */ 1875 IXGBE_WRITE_REG_BE32(hw, IXGBE_FDIRSIP4M, 1876 ~input_mask->formatted.src_ip[0]); 1877 IXGBE_WRITE_REG_BE32(hw, IXGBE_FDIRDIP4M, 1878 ~input_mask->formatted.dst_ip[0]); 1879 IXGBE_WRITE_REG_BE32(hw, IXGBE_FDIRIP6M, 0xFFFFFFFF); 1880 } 1881 return IXGBE_SUCCESS; 1882 } 1883 1884 s32 ixgbe_fdir_write_perfect_filter_82599(struct ixgbe_hw *hw, 1885 union ixgbe_atr_input *input, 1886 u16 soft_id, u8 queue, bool cloud_mode) 1887 { 1888 u32 fdirport, fdirvlan, fdirhash, fdircmd; 1889 u32 addr_low, addr_high; 1890 u32 cloud_type = 0; 1891 s32 err; 1892 UNREFERENCED_1PARAMETER(cloud_mode); 1893 1894 DEBUGFUNC("ixgbe_fdir_write_perfect_filter_82599"); 1895 if (!cloud_mode) { 1896 /* currently IPv6 is not supported, must be programmed with 0 */ 1897 IXGBE_WRITE_REG_BE32(hw, IXGBE_FDIRSIPv6(0), 1898 input->formatted.src_ip[0]); 1899 IXGBE_WRITE_REG_BE32(hw, IXGBE_FDIRSIPv6(1), 1900 input->formatted.src_ip[1]); 1901 IXGBE_WRITE_REG_BE32(hw, IXGBE_FDIRSIPv6(2), 1902 input->formatted.src_ip[2]); 1903 1904 /* record the source address (big-endian) */ 1905 IXGBE_WRITE_REG_BE32(hw, IXGBE_FDIRIPSA, 1906 input->formatted.src_ip[0]); 1907 1908 /* record the first 32 bits of the destination address 1909 * (big-endian) */ 1910 IXGBE_WRITE_REG_BE32(hw, IXGBE_FDIRIPDA, 1911 input->formatted.dst_ip[0]); 1912 1913 /* record source and destination port (little-endian)*/ 1914 fdirport = IXGBE_NTOHS(input->formatted.dst_port); 1915 fdirport <<= IXGBE_FDIRPORT_DESTINATION_SHIFT; 1916 fdirport |= (u32)IXGBE_NTOHS(input->formatted.src_port); 1917 IXGBE_WRITE_REG(hw, IXGBE_FDIRPORT, fdirport); 1918 } 1919 1920 /* record VLAN (little-endian) and flex_bytes(big-endian) */ 1921 fdirvlan = IXGBE_STORE_AS_BE16(input->formatted.flex_bytes); 1922 fdirvlan <<= IXGBE_FDIRVLAN_FLEX_SHIFT; 1923 fdirvlan |= (u32)IXGBE_NTOHS(input->formatted.vlan_id); 1924 IXGBE_WRITE_REG(hw, IXGBE_FDIRVLAN, fdirvlan); 1925 1926 if (cloud_mode) { 1927 if (input->formatted.tunnel_type != 0) 1928 cloud_type = 0x80000000; 1929 1930 addr_low = ((u32)input->formatted.inner_mac[0] | 1931 ((u32)input->formatted.inner_mac[1] << 8) | 1932 ((u32)input->formatted.inner_mac[2] << 16) | 1933 ((u32)input->formatted.inner_mac[3] << 24)); 1934 addr_high = ((u32)input->formatted.inner_mac[4] | 1935 ((u32)input->formatted.inner_mac[5] << 8)); 1936 cloud_type |= addr_high; 1937 IXGBE_WRITE_REG_BE32(hw, IXGBE_FDIRSIPv6(0), addr_low); 1938 IXGBE_WRITE_REG_BE32(hw, IXGBE_FDIRSIPv6(1), cloud_type); 1939 IXGBE_WRITE_REG_BE32(hw, IXGBE_FDIRSIPv6(2), input->formatted.tni_vni); 1940 } 1941 1942 /* configure FDIRHASH register */ 1943 fdirhash = input->formatted.bkt_hash; 1944 fdirhash |= soft_id << IXGBE_FDIRHASH_SIG_SW_INDEX_SHIFT; 1945 IXGBE_WRITE_REG(hw, IXGBE_FDIRHASH, fdirhash); 1946 1947 /* 1948 * flush all previous writes to make certain registers are 1949 * programmed prior to issuing the command 1950 */ 1951 IXGBE_WRITE_FLUSH(hw); 1952 1953 /* configure FDIRCMD register */ 1954 fdircmd = IXGBE_FDIRCMD_CMD_ADD_FLOW | IXGBE_FDIRCMD_FILTER_UPDATE | 1955 IXGBE_FDIRCMD_LAST | IXGBE_FDIRCMD_QUEUE_EN; 1956 if (queue == IXGBE_FDIR_DROP_QUEUE) 1957 fdircmd |= IXGBE_FDIRCMD_DROP; 1958 if (input->formatted.flow_type & IXGBE_ATR_L4TYPE_TUNNEL_MASK) 1959 fdircmd |= IXGBE_FDIRCMD_TUNNEL_FILTER; 1960 fdircmd |= input->formatted.flow_type << IXGBE_FDIRCMD_FLOW_TYPE_SHIFT; 1961 fdircmd |= (u32)queue << IXGBE_FDIRCMD_RX_QUEUE_SHIFT; 1962 fdircmd |= (u32)input->formatted.vm_pool << IXGBE_FDIRCMD_VT_POOL_SHIFT; 1963 1964 IXGBE_WRITE_REG(hw, IXGBE_FDIRCMD, fdircmd); 1965 err = ixgbe_fdir_check_cmd_complete(hw, &fdircmd); 1966 if (err) { 1967 DEBUGOUT("Flow Director command did not complete!\n"); 1968 return err; 1969 } 1970 1971 return IXGBE_SUCCESS; 1972 } 1973 1974 s32 ixgbe_fdir_erase_perfect_filter_82599(struct ixgbe_hw *hw, 1975 union ixgbe_atr_input *input, 1976 u16 soft_id) 1977 { 1978 u32 fdirhash; 1979 u32 fdircmd; 1980 s32 err; 1981 1982 /* configure FDIRHASH register */ 1983 fdirhash = input->formatted.bkt_hash; 1984 fdirhash |= soft_id << IXGBE_FDIRHASH_SIG_SW_INDEX_SHIFT; 1985 IXGBE_WRITE_REG(hw, IXGBE_FDIRHASH, fdirhash); 1986 1987 /* flush hash to HW */ 1988 IXGBE_WRITE_FLUSH(hw); 1989 1990 /* Query if filter is present */ 1991 IXGBE_WRITE_REG(hw, IXGBE_FDIRCMD, IXGBE_FDIRCMD_CMD_QUERY_REM_FILT); 1992 1993 err = ixgbe_fdir_check_cmd_complete(hw, &fdircmd); 1994 if (err) { 1995 DEBUGOUT("Flow Director command did not complete!\n"); 1996 return err; 1997 } 1998 1999 /* if filter exists in hardware then remove it */ 2000 if (fdircmd & IXGBE_FDIRCMD_FILTER_VALID) { 2001 IXGBE_WRITE_REG(hw, IXGBE_FDIRHASH, fdirhash); 2002 IXGBE_WRITE_FLUSH(hw); 2003 IXGBE_WRITE_REG(hw, IXGBE_FDIRCMD, 2004 IXGBE_FDIRCMD_CMD_REMOVE_FLOW); 2005 } 2006 2007 return IXGBE_SUCCESS; 2008 } 2009 2010 /** 2011 * ixgbe_fdir_add_perfect_filter_82599 - Adds a perfect filter 2012 * @hw: pointer to hardware structure 2013 * @input: input bitstream 2014 * @input_mask: mask for the input bitstream 2015 * @soft_id: software index for the filters 2016 * @queue: queue index to direct traffic to 2017 * @cloud_mode: unused 2018 * 2019 * Note that the caller to this function must lock before calling, since the 2020 * hardware writes must be protected from one another. 2021 **/ 2022 s32 ixgbe_fdir_add_perfect_filter_82599(struct ixgbe_hw *hw, 2023 union ixgbe_atr_input *input, 2024 union ixgbe_atr_input *input_mask, 2025 u16 soft_id, u8 queue, bool cloud_mode) 2026 { 2027 s32 err = IXGBE_ERR_CONFIG; 2028 UNREFERENCED_1PARAMETER(cloud_mode); 2029 2030 DEBUGFUNC("ixgbe_fdir_add_perfect_filter_82599"); 2031 2032 /* 2033 * Check flow_type formatting, and bail out before we touch the hardware 2034 * if there's a configuration issue 2035 */ 2036 switch (input->formatted.flow_type) { 2037 case IXGBE_ATR_FLOW_TYPE_IPV4: 2038 case IXGBE_ATR_FLOW_TYPE_TUNNELED_IPV4: 2039 input_mask->formatted.flow_type = IXGBE_ATR_L4TYPE_IPV6_MASK; 2040 if (input->formatted.dst_port || input->formatted.src_port) { 2041 DEBUGOUT(" Error on src/dst port\n"); 2042 return IXGBE_ERR_CONFIG; 2043 } 2044 break; 2045 case IXGBE_ATR_FLOW_TYPE_SCTPV4: 2046 case IXGBE_ATR_FLOW_TYPE_TUNNELED_SCTPV4: 2047 if (input->formatted.dst_port || input->formatted.src_port) { 2048 DEBUGOUT(" Error on src/dst port\n"); 2049 return IXGBE_ERR_CONFIG; 2050 } 2051 /* FALLTHROUGH */ 2052 case IXGBE_ATR_FLOW_TYPE_TCPV4: 2053 case IXGBE_ATR_FLOW_TYPE_TUNNELED_TCPV4: 2054 case IXGBE_ATR_FLOW_TYPE_UDPV4: 2055 case IXGBE_ATR_FLOW_TYPE_TUNNELED_UDPV4: 2056 input_mask->formatted.flow_type = IXGBE_ATR_L4TYPE_IPV6_MASK | 2057 IXGBE_ATR_L4TYPE_MASK; 2058 break; 2059 default: 2060 DEBUGOUT(" Error on flow type input\n"); 2061 return err; 2062 } 2063 2064 /* program input mask into the HW */ 2065 err = ixgbe_fdir_set_input_mask_82599(hw, input_mask, cloud_mode); 2066 if (err) 2067 return err; 2068 2069 /* apply mask and compute/store hash */ 2070 ixgbe_atr_compute_perfect_hash_82599(input, input_mask); 2071 2072 /* program filters to filter memory */ 2073 return ixgbe_fdir_write_perfect_filter_82599(hw, input, 2074 soft_id, queue, cloud_mode); 2075 } 2076 2077 /** 2078 * ixgbe_read_analog_reg8_82599 - Reads 8 bit Omer analog register 2079 * @hw: pointer to hardware structure 2080 * @reg: analog register to read 2081 * @val: read value 2082 * 2083 * Performs read operation to Omer analog register specified. 2084 **/ 2085 s32 ixgbe_read_analog_reg8_82599(struct ixgbe_hw *hw, u32 reg, u8 *val) 2086 { 2087 u32 core_ctl; 2088 2089 DEBUGFUNC("ixgbe_read_analog_reg8_82599"); 2090 2091 IXGBE_WRITE_REG(hw, IXGBE_CORECTL, IXGBE_CORECTL_WRITE_CMD | 2092 (reg << 8)); 2093 IXGBE_WRITE_FLUSH(hw); 2094 usec_delay(10); 2095 core_ctl = IXGBE_READ_REG(hw, IXGBE_CORECTL); 2096 *val = (u8)core_ctl; 2097 2098 return IXGBE_SUCCESS; 2099 } 2100 2101 /** 2102 * ixgbe_write_analog_reg8_82599 - Writes 8 bit Omer analog register 2103 * @hw: pointer to hardware structure 2104 * @reg: atlas register to write 2105 * @val: value to write 2106 * 2107 * Performs write operation to Omer analog register specified. 2108 **/ 2109 s32 ixgbe_write_analog_reg8_82599(struct ixgbe_hw *hw, u32 reg, u8 val) 2110 { 2111 u32 core_ctl; 2112 2113 DEBUGFUNC("ixgbe_write_analog_reg8_82599"); 2114 2115 core_ctl = (reg << 8) | val; 2116 IXGBE_WRITE_REG(hw, IXGBE_CORECTL, core_ctl); 2117 IXGBE_WRITE_FLUSH(hw); 2118 usec_delay(10); 2119 2120 return IXGBE_SUCCESS; 2121 } 2122 2123 /** 2124 * ixgbe_start_hw_82599 - Prepare hardware for Tx/Rx 2125 * @hw: pointer to hardware structure 2126 * 2127 * Starts the hardware using the generic start_hw function 2128 * and the generation start_hw function. 2129 * Then performs revision-specific operations, if any. 2130 **/ 2131 s32 ixgbe_start_hw_82599(struct ixgbe_hw *hw) 2132 { 2133 s32 ret_val = IXGBE_SUCCESS; 2134 2135 DEBUGFUNC("ixgbe_start_hw_82599"); 2136 2137 ret_val = ixgbe_start_hw_generic(hw); 2138 if (ret_val != IXGBE_SUCCESS) 2139 goto out; 2140 2141 ixgbe_start_hw_gen2(hw); 2142 2143 /* We need to run link autotry after the driver loads */ 2144 hw->mac.autotry_restart = true; 2145 2146 if (ret_val == IXGBE_SUCCESS) 2147 ret_val = ixgbe_verify_fw_version_82599(hw); 2148 out: 2149 return ret_val; 2150 } 2151 2152 /** 2153 * ixgbe_identify_phy_82599 - Get physical layer module 2154 * @hw: pointer to hardware structure 2155 * 2156 * Determines the physical layer module found on the current adapter. 2157 * If PHY already detected, maintains current PHY type in hw struct, 2158 * otherwise executes the PHY detection routine. 2159 **/ 2160 s32 ixgbe_identify_phy_82599(struct ixgbe_hw *hw) 2161 { 2162 s32 status; 2163 2164 DEBUGFUNC("ixgbe_identify_phy_82599"); 2165 2166 /* Detect PHY if not unknown - returns success if already detected. */ 2167 status = ixgbe_identify_phy_generic(hw); 2168 if (status != IXGBE_SUCCESS) { 2169 /* 82599 10GBASE-T requires an external PHY */ 2170 if (hw->mac.ops.get_media_type(hw) == ixgbe_media_type_copper) 2171 return status; 2172 else 2173 status = ixgbe_identify_module_generic(hw); 2174 } 2175 2176 /* Set PHY type none if no PHY detected */ 2177 if (hw->phy.type == ixgbe_phy_unknown) { 2178 hw->phy.type = ixgbe_phy_none; 2179 return IXGBE_SUCCESS; 2180 } 2181 2182 /* Return error if SFP module has been detected but is not supported */ 2183 if (hw->phy.type == ixgbe_phy_sfp_unsupported) 2184 return IXGBE_ERR_SFP_NOT_SUPPORTED; 2185 2186 return status; 2187 } 2188 2189 /** 2190 * ixgbe_get_supported_physical_layer_82599 - Returns physical layer type 2191 * @hw: pointer to hardware structure 2192 * 2193 * Determines physical layer capabilities of the current configuration. 2194 **/ 2195 u64 ixgbe_get_supported_physical_layer_82599(struct ixgbe_hw *hw) 2196 { 2197 u64 physical_layer = IXGBE_PHYSICAL_LAYER_UNKNOWN; 2198 u32 autoc = IXGBE_READ_REG(hw, IXGBE_AUTOC); 2199 u32 autoc2 = IXGBE_READ_REG(hw, IXGBE_AUTOC2); 2200 u32 pma_pmd_10g_serial = autoc2 & IXGBE_AUTOC2_10G_SERIAL_PMA_PMD_MASK; 2201 u32 pma_pmd_10g_parallel = autoc & IXGBE_AUTOC_10G_PMA_PMD_MASK; 2202 u32 pma_pmd_1g = autoc & IXGBE_AUTOC_1G_PMA_PMD_MASK; 2203 u16 ext_ability = 0; 2204 2205 DEBUGFUNC("ixgbe_get_support_physical_layer_82599"); 2206 2207 hw->phy.ops.identify(hw); 2208 2209 switch (hw->phy.type) { 2210 case ixgbe_phy_tn: 2211 case ixgbe_phy_cu_unknown: 2212 hw->phy.ops.read_reg(hw, IXGBE_MDIO_PHY_EXT_ABILITY, 2213 IXGBE_MDIO_PMA_PMD_DEV_TYPE, &ext_ability); 2214 if (ext_ability & IXGBE_MDIO_PHY_10GBASET_ABILITY) 2215 physical_layer |= IXGBE_PHYSICAL_LAYER_10GBASE_T; 2216 if (ext_ability & IXGBE_MDIO_PHY_1000BASET_ABILITY) 2217 physical_layer |= IXGBE_PHYSICAL_LAYER_1000BASE_T; 2218 if (ext_ability & IXGBE_MDIO_PHY_100BASETX_ABILITY) 2219 physical_layer |= IXGBE_PHYSICAL_LAYER_100BASE_TX; 2220 goto out; 2221 default: 2222 break; 2223 } 2224 2225 switch (autoc & IXGBE_AUTOC_LMS_MASK) { 2226 case IXGBE_AUTOC_LMS_1G_AN: 2227 case IXGBE_AUTOC_LMS_1G_LINK_NO_AN: 2228 if (pma_pmd_1g == IXGBE_AUTOC_1G_KX_BX) { 2229 physical_layer = IXGBE_PHYSICAL_LAYER_1000BASE_KX | 2230 IXGBE_PHYSICAL_LAYER_1000BASE_BX; 2231 goto out; 2232 } else 2233 /* SFI mode so read SFP module */ 2234 goto sfp_check; 2235 break; 2236 case IXGBE_AUTOC_LMS_10G_LINK_NO_AN: 2237 if (pma_pmd_10g_parallel == IXGBE_AUTOC_10G_CX4) 2238 physical_layer = IXGBE_PHYSICAL_LAYER_10GBASE_CX4; 2239 else if (pma_pmd_10g_parallel == IXGBE_AUTOC_10G_KX4) 2240 physical_layer = IXGBE_PHYSICAL_LAYER_10GBASE_KX4; 2241 else if (pma_pmd_10g_parallel == IXGBE_AUTOC_10G_XAUI) 2242 physical_layer = IXGBE_PHYSICAL_LAYER_10GBASE_XAUI; 2243 goto out; 2244 break; 2245 case IXGBE_AUTOC_LMS_10G_SERIAL: 2246 if (pma_pmd_10g_serial == IXGBE_AUTOC2_10G_KR) { 2247 physical_layer = IXGBE_PHYSICAL_LAYER_10GBASE_KR; 2248 goto out; 2249 } else if (pma_pmd_10g_serial == IXGBE_AUTOC2_10G_SFI) 2250 goto sfp_check; 2251 break; 2252 case IXGBE_AUTOC_LMS_KX4_KX_KR: 2253 case IXGBE_AUTOC_LMS_KX4_KX_KR_1G_AN: 2254 if (autoc & IXGBE_AUTOC_KX_SUPP) 2255 physical_layer |= IXGBE_PHYSICAL_LAYER_1000BASE_KX; 2256 if (autoc & IXGBE_AUTOC_KX4_SUPP) 2257 physical_layer |= IXGBE_PHYSICAL_LAYER_10GBASE_KX4; 2258 if (autoc & IXGBE_AUTOC_KR_SUPP) 2259 physical_layer |= IXGBE_PHYSICAL_LAYER_10GBASE_KR; 2260 goto out; 2261 break; 2262 default: 2263 goto out; 2264 break; 2265 } 2266 2267 sfp_check: 2268 /* SFP check must be done last since DA modules are sometimes used to 2269 * test KR mode - we need to id KR mode correctly before SFP module. 2270 * Call identify_sfp because the pluggable module may have changed */ 2271 physical_layer = ixgbe_get_supported_phy_sfp_layer_generic(hw); 2272 out: 2273 return physical_layer; 2274 } 2275 2276 /** 2277 * ixgbe_enable_rx_dma_82599 - Enable the Rx DMA unit on 82599 2278 * @hw: pointer to hardware structure 2279 * @regval: register value to write to RXCTRL 2280 * 2281 * Enables the Rx DMA unit for 82599 2282 **/ 2283 s32 ixgbe_enable_rx_dma_82599(struct ixgbe_hw *hw, u32 regval) 2284 { 2285 2286 DEBUGFUNC("ixgbe_enable_rx_dma_82599"); 2287 2288 /* 2289 * Workaround for 82599 silicon errata when enabling the Rx datapath. 2290 * If traffic is incoming before we enable the Rx unit, it could hang 2291 * the Rx DMA unit. Therefore, make sure the security engine is 2292 * completely disabled prior to enabling the Rx unit. 2293 */ 2294 2295 hw->mac.ops.disable_sec_rx_path(hw); 2296 2297 if (regval & IXGBE_RXCTRL_RXEN) 2298 ixgbe_enable_rx(hw); 2299 else 2300 ixgbe_disable_rx(hw); 2301 2302 hw->mac.ops.enable_sec_rx_path(hw); 2303 2304 return IXGBE_SUCCESS; 2305 } 2306 2307 /** 2308 * ixgbe_verify_fw_version_82599 - verify FW version for 82599 2309 * @hw: pointer to hardware structure 2310 * 2311 * Verifies that installed the firmware version is 0.6 or higher 2312 * for SFI devices. All 82599 SFI devices should have version 0.6 or higher. 2313 * 2314 * Returns IXGBE_ERR_EEPROM_VERSION if the FW is not present or 2315 * if the FW version is not supported. 2316 **/ 2317 static s32 ixgbe_verify_fw_version_82599(struct ixgbe_hw *hw) 2318 { 2319 s32 status = IXGBE_ERR_EEPROM_VERSION; 2320 u16 fw_offset, fw_ptp_cfg_offset; 2321 u16 fw_version; 2322 2323 DEBUGFUNC("ixgbe_verify_fw_version_82599"); 2324 2325 /* firmware check is only necessary for SFI devices */ 2326 if (hw->phy.media_type != ixgbe_media_type_fiber) { 2327 status = IXGBE_SUCCESS; 2328 goto fw_version_out; 2329 } 2330 2331 /* get the offset to the Firmware Module block */ 2332 if (hw->eeprom.ops.read(hw, IXGBE_FW_PTR, &fw_offset)) { 2333 ERROR_REPORT2(IXGBE_ERROR_INVALID_STATE, 2334 "eeprom read at offset %d failed", IXGBE_FW_PTR); 2335 return IXGBE_ERR_EEPROM_VERSION; 2336 } 2337 2338 if ((fw_offset == 0) || (fw_offset == 0xFFFF)) 2339 goto fw_version_out; 2340 2341 /* get the offset to the Pass Through Patch Configuration block */ 2342 if (hw->eeprom.ops.read(hw, (fw_offset + 2343 IXGBE_FW_PASSTHROUGH_PATCH_CONFIG_PTR), 2344 &fw_ptp_cfg_offset)) { 2345 ERROR_REPORT2(IXGBE_ERROR_INVALID_STATE, 2346 "eeprom read at offset %d failed", 2347 fw_offset + 2348 IXGBE_FW_PASSTHROUGH_PATCH_CONFIG_PTR); 2349 return IXGBE_ERR_EEPROM_VERSION; 2350 } 2351 2352 if ((fw_ptp_cfg_offset == 0) || (fw_ptp_cfg_offset == 0xFFFF)) 2353 goto fw_version_out; 2354 2355 /* get the firmware version */ 2356 if (hw->eeprom.ops.read(hw, (fw_ptp_cfg_offset + 2357 IXGBE_FW_PATCH_VERSION_4), &fw_version)) { 2358 ERROR_REPORT2(IXGBE_ERROR_INVALID_STATE, 2359 "eeprom read at offset %d failed", 2360 fw_ptp_cfg_offset + IXGBE_FW_PATCH_VERSION_4); 2361 return IXGBE_ERR_EEPROM_VERSION; 2362 } 2363 2364 if (fw_version > 0x5) 2365 status = IXGBE_SUCCESS; 2366 2367 fw_version_out: 2368 return status; 2369 } 2370 2371 /** 2372 * ixgbe_verify_lesm_fw_enabled_82599 - Checks LESM FW module state. 2373 * @hw: pointer to hardware structure 2374 * 2375 * Returns true if the LESM FW module is present and enabled. Otherwise 2376 * returns false. Smart Speed must be disabled if LESM FW module is enabled. 2377 **/ 2378 bool ixgbe_verify_lesm_fw_enabled_82599(struct ixgbe_hw *hw) 2379 { 2380 bool lesm_enabled = false; 2381 u16 fw_offset, fw_lesm_param_offset, fw_lesm_state; 2382 s32 status; 2383 2384 DEBUGFUNC("ixgbe_verify_lesm_fw_enabled_82599"); 2385 2386 /* get the offset to the Firmware Module block */ 2387 status = hw->eeprom.ops.read(hw, IXGBE_FW_PTR, &fw_offset); 2388 2389 if ((status != IXGBE_SUCCESS) || 2390 (fw_offset == 0) || (fw_offset == 0xFFFF)) 2391 goto out; 2392 2393 /* get the offset to the LESM Parameters block */ 2394 status = hw->eeprom.ops.read(hw, (fw_offset + 2395 IXGBE_FW_LESM_PARAMETERS_PTR), 2396 &fw_lesm_param_offset); 2397 2398 if ((status != IXGBE_SUCCESS) || 2399 (fw_lesm_param_offset == 0) || (fw_lesm_param_offset == 0xFFFF)) 2400 goto out; 2401 2402 /* get the LESM state word */ 2403 status = hw->eeprom.ops.read(hw, (fw_lesm_param_offset + 2404 IXGBE_FW_LESM_STATE_1), 2405 &fw_lesm_state); 2406 2407 if ((status == IXGBE_SUCCESS) && 2408 (fw_lesm_state & IXGBE_FW_LESM_STATE_ENABLED)) 2409 lesm_enabled = true; 2410 2411 out: 2412 return lesm_enabled; 2413 } 2414 2415 /** 2416 * ixgbe_read_eeprom_buffer_82599 - Read EEPROM word(s) using 2417 * fastest available method 2418 * 2419 * @hw: pointer to hardware structure 2420 * @offset: offset of word in EEPROM to read 2421 * @words: number of words 2422 * @data: word(s) read from the EEPROM 2423 * 2424 * Retrieves 16 bit word(s) read from EEPROM 2425 **/ 2426 static s32 ixgbe_read_eeprom_buffer_82599(struct ixgbe_hw *hw, u16 offset, 2427 u16 words, u16 *data) 2428 { 2429 struct ixgbe_eeprom_info *eeprom = &hw->eeprom; 2430 s32 ret_val = IXGBE_ERR_CONFIG; 2431 2432 DEBUGFUNC("ixgbe_read_eeprom_buffer_82599"); 2433 2434 /* 2435 * If EEPROM is detected and can be addressed using 14 bits, 2436 * use EERD otherwise use bit bang 2437 */ 2438 if ((eeprom->type == ixgbe_eeprom_spi) && 2439 (offset + (words - 1) <= IXGBE_EERD_MAX_ADDR)) 2440 ret_val = ixgbe_read_eerd_buffer_generic(hw, offset, words, 2441 data); 2442 else 2443 ret_val = ixgbe_read_eeprom_buffer_bit_bang_generic(hw, offset, 2444 words, 2445 data); 2446 2447 return ret_val; 2448 } 2449 2450 /** 2451 * ixgbe_read_eeprom_82599 - Read EEPROM word using 2452 * fastest available method 2453 * 2454 * @hw: pointer to hardware structure 2455 * @offset: offset of word in the EEPROM to read 2456 * @data: word read from the EEPROM 2457 * 2458 * Reads a 16 bit word from the EEPROM 2459 **/ 2460 static s32 ixgbe_read_eeprom_82599(struct ixgbe_hw *hw, 2461 u16 offset, u16 *data) 2462 { 2463 struct ixgbe_eeprom_info *eeprom = &hw->eeprom; 2464 s32 ret_val = IXGBE_ERR_CONFIG; 2465 2466 DEBUGFUNC("ixgbe_read_eeprom_82599"); 2467 2468 /* 2469 * If EEPROM is detected and can be addressed using 14 bits, 2470 * use EERD otherwise use bit bang 2471 */ 2472 if ((eeprom->type == ixgbe_eeprom_spi) && 2473 (offset <= IXGBE_EERD_MAX_ADDR)) 2474 ret_val = ixgbe_read_eerd_generic(hw, offset, data); 2475 else 2476 ret_val = ixgbe_read_eeprom_bit_bang_generic(hw, offset, data); 2477 2478 return ret_val; 2479 } 2480 2481 /** 2482 * ixgbe_reset_pipeline_82599 - perform pipeline reset 2483 * 2484 * @hw: pointer to hardware structure 2485 * 2486 * Reset pipeline by asserting Restart_AN together with LMS change to ensure 2487 * full pipeline reset. This function assumes the SW/FW lock is held. 2488 **/ 2489 s32 ixgbe_reset_pipeline_82599(struct ixgbe_hw *hw) 2490 { 2491 s32 ret_val; 2492 u32 anlp1_reg = 0; 2493 u32 i, autoc_reg, autoc2_reg; 2494 2495 /* Enable link if disabled in NVM */ 2496 autoc2_reg = IXGBE_READ_REG(hw, IXGBE_AUTOC2); 2497 if (autoc2_reg & IXGBE_AUTOC2_LINK_DISABLE_MASK) { 2498 autoc2_reg &= ~IXGBE_AUTOC2_LINK_DISABLE_MASK; 2499 IXGBE_WRITE_REG(hw, IXGBE_AUTOC2, autoc2_reg); 2500 IXGBE_WRITE_FLUSH(hw); 2501 } 2502 2503 autoc_reg = IXGBE_READ_REG(hw, IXGBE_AUTOC); 2504 autoc_reg |= IXGBE_AUTOC_AN_RESTART; 2505 /* Write AUTOC register with toggled LMS[2] bit and Restart_AN */ 2506 IXGBE_WRITE_REG(hw, IXGBE_AUTOC, 2507 autoc_reg ^ (0x4 << IXGBE_AUTOC_LMS_SHIFT)); 2508 /* Wait for AN to leave state 0 */ 2509 for (i = 0; i < 10; i++) { 2510 msec_delay(4); 2511 anlp1_reg = IXGBE_READ_REG(hw, IXGBE_ANLP1); 2512 if (anlp1_reg & IXGBE_ANLP1_AN_STATE_MASK) 2513 break; 2514 } 2515 2516 if (!(anlp1_reg & IXGBE_ANLP1_AN_STATE_MASK)) { 2517 DEBUGOUT("auto negotiation not completed\n"); 2518 ret_val = IXGBE_ERR_RESET_FAILED; 2519 goto reset_pipeline_out; 2520 } 2521 2522 ret_val = IXGBE_SUCCESS; 2523 2524 reset_pipeline_out: 2525 /* Write AUTOC register with original LMS field and Restart_AN */ 2526 IXGBE_WRITE_REG(hw, IXGBE_AUTOC, autoc_reg); 2527 IXGBE_WRITE_FLUSH(hw); 2528 2529 return ret_val; 2530 } 2531 2532 /** 2533 * ixgbe_read_i2c_byte_82599 - Reads 8 bit word over I2C 2534 * @hw: pointer to hardware structure 2535 * @byte_offset: byte offset to read 2536 * @dev_addr: address to read from 2537 * @data: value read 2538 * 2539 * Performs byte read operation to SFP module's EEPROM over I2C interface at 2540 * a specified device address. 2541 **/ 2542 static s32 ixgbe_read_i2c_byte_82599(struct ixgbe_hw *hw, u8 byte_offset, 2543 u8 dev_addr, u8 *data) 2544 { 2545 u32 esdp; 2546 s32 status; 2547 s32 timeout = 200; 2548 2549 DEBUGFUNC("ixgbe_read_i2c_byte_82599"); 2550 2551 if (hw->phy.qsfp_shared_i2c_bus == true) { 2552 /* Acquire I2C bus ownership. */ 2553 esdp = IXGBE_READ_REG(hw, IXGBE_ESDP); 2554 esdp |= IXGBE_ESDP_SDP0; 2555 IXGBE_WRITE_REG(hw, IXGBE_ESDP, esdp); 2556 IXGBE_WRITE_FLUSH(hw); 2557 2558 while (timeout) { 2559 esdp = IXGBE_READ_REG(hw, IXGBE_ESDP); 2560 if (esdp & IXGBE_ESDP_SDP1) 2561 break; 2562 2563 msec_delay(5); 2564 timeout--; 2565 } 2566 2567 if (!timeout) { 2568 DEBUGOUT("Driver can't access resource," 2569 " acquiring I2C bus timeout.\n"); 2570 status = IXGBE_ERR_I2C; 2571 goto release_i2c_access; 2572 } 2573 } 2574 2575 status = ixgbe_read_i2c_byte_generic(hw, byte_offset, dev_addr, data); 2576 2577 release_i2c_access: 2578 2579 if (hw->phy.qsfp_shared_i2c_bus == true) { 2580 /* Release I2C bus ownership. */ 2581 esdp = IXGBE_READ_REG(hw, IXGBE_ESDP); 2582 esdp &= ~IXGBE_ESDP_SDP0; 2583 IXGBE_WRITE_REG(hw, IXGBE_ESDP, esdp); 2584 IXGBE_WRITE_FLUSH(hw); 2585 } 2586 2587 return status; 2588 } 2589 2590 /** 2591 * ixgbe_write_i2c_byte_82599 - Writes 8 bit word over I2C 2592 * @hw: pointer to hardware structure 2593 * @byte_offset: byte offset to write 2594 * @dev_addr: address to read from 2595 * @data: value to write 2596 * 2597 * Performs byte write operation to SFP module's EEPROM over I2C interface at 2598 * a specified device address. 2599 **/ 2600 static s32 ixgbe_write_i2c_byte_82599(struct ixgbe_hw *hw, u8 byte_offset, 2601 u8 dev_addr, u8 data) 2602 { 2603 u32 esdp; 2604 s32 status; 2605 s32 timeout = 200; 2606 2607 DEBUGFUNC("ixgbe_write_i2c_byte_82599"); 2608 2609 if (hw->phy.qsfp_shared_i2c_bus == true) { 2610 /* Acquire I2C bus ownership. */ 2611 esdp = IXGBE_READ_REG(hw, IXGBE_ESDP); 2612 esdp |= IXGBE_ESDP_SDP0; 2613 IXGBE_WRITE_REG(hw, IXGBE_ESDP, esdp); 2614 IXGBE_WRITE_FLUSH(hw); 2615 2616 while (timeout) { 2617 esdp = IXGBE_READ_REG(hw, IXGBE_ESDP); 2618 if (esdp & IXGBE_ESDP_SDP1) 2619 break; 2620 2621 msec_delay(5); 2622 timeout--; 2623 } 2624 2625 if (!timeout) { 2626 DEBUGOUT("Driver can't access resource," 2627 " acquiring I2C bus timeout.\n"); 2628 status = IXGBE_ERR_I2C; 2629 goto release_i2c_access; 2630 } 2631 } 2632 2633 status = ixgbe_write_i2c_byte_generic(hw, byte_offset, dev_addr, data); 2634 2635 release_i2c_access: 2636 2637 if (hw->phy.qsfp_shared_i2c_bus == true) { 2638 /* Release I2C bus ownership. */ 2639 esdp = IXGBE_READ_REG(hw, IXGBE_ESDP); 2640 esdp &= ~IXGBE_ESDP_SDP0; 2641 IXGBE_WRITE_REG(hw, IXGBE_ESDP, esdp); 2642 IXGBE_WRITE_FLUSH(hw); 2643 } 2644 2645 return status; 2646 } 2647