xref: /freebsd/sys/dev/ixgbe/ixgbe_82599.c (revision 39ee7a7a6bdd1557b1c3532abf60d139798ac88b)
1 /******************************************************************************
2 
3   Copyright (c) 2001-2015, Intel Corporation
4   All rights reserved.
5 
6   Redistribution and use in source and binary forms, with or without
7   modification, are permitted provided that the following conditions are met:
8 
9    1. Redistributions of source code must retain the above copyright notice,
10       this list of conditions and the following disclaimer.
11 
12    2. Redistributions in binary form must reproduce the above copyright
13       notice, this list of conditions and the following disclaimer in the
14       documentation and/or other materials provided with the distribution.
15 
16    3. Neither the name of the Intel Corporation nor the names of its
17       contributors may be used to endorse or promote products derived from
18       this software without specific prior written permission.
19 
20   THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
21   AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
22   IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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24   LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
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29   ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
30   POSSIBILITY OF SUCH DAMAGE.
31 
32 ******************************************************************************/
33 /*$FreeBSD$*/
34 
35 #include "ixgbe_type.h"
36 #include "ixgbe_82599.h"
37 #include "ixgbe_api.h"
38 #include "ixgbe_common.h"
39 #include "ixgbe_phy.h"
40 
41 #define IXGBE_82599_MAX_TX_QUEUES 128
42 #define IXGBE_82599_MAX_RX_QUEUES 128
43 #define IXGBE_82599_RAR_ENTRIES   128
44 #define IXGBE_82599_MC_TBL_SIZE   128
45 #define IXGBE_82599_VFT_TBL_SIZE  128
46 #define IXGBE_82599_RX_PB_SIZE	  512
47 
48 static s32 ixgbe_setup_copper_link_82599(struct ixgbe_hw *hw,
49 					 ixgbe_link_speed speed,
50 					 bool autoneg_wait_to_complete);
51 static s32 ixgbe_verify_fw_version_82599(struct ixgbe_hw *hw);
52 static s32 ixgbe_read_eeprom_82599(struct ixgbe_hw *hw,
53 				   u16 offset, u16 *data);
54 static s32 ixgbe_read_eeprom_buffer_82599(struct ixgbe_hw *hw, u16 offset,
55 					  u16 words, u16 *data);
56 static s32 ixgbe_read_i2c_byte_82599(struct ixgbe_hw *hw, u8 byte_offset,
57 					u8 dev_addr, u8 *data);
58 static s32 ixgbe_write_i2c_byte_82599(struct ixgbe_hw *hw, u8 byte_offset,
59 					u8 dev_addr, u8 data);
60 
61 void ixgbe_init_mac_link_ops_82599(struct ixgbe_hw *hw)
62 {
63 	struct ixgbe_mac_info *mac = &hw->mac;
64 
65 	DEBUGFUNC("ixgbe_init_mac_link_ops_82599");
66 
67 	/*
68 	 * enable the laser control functions for SFP+ fiber
69 	 * and MNG not enabled
70 	 */
71 	if ((mac->ops.get_media_type(hw) == ixgbe_media_type_fiber) &&
72 	    !ixgbe_mng_enabled(hw)) {
73 		mac->ops.disable_tx_laser =
74 				       ixgbe_disable_tx_laser_multispeed_fiber;
75 		mac->ops.enable_tx_laser =
76 					ixgbe_enable_tx_laser_multispeed_fiber;
77 		mac->ops.flap_tx_laser = ixgbe_flap_tx_laser_multispeed_fiber;
78 
79 	} else {
80 		mac->ops.disable_tx_laser = NULL;
81 		mac->ops.enable_tx_laser = NULL;
82 		mac->ops.flap_tx_laser = NULL;
83 	}
84 
85 	if (hw->phy.multispeed_fiber) {
86 		/* Set up dual speed SFP+ support */
87 		mac->ops.setup_link = ixgbe_setup_mac_link_multispeed_fiber;
88 		mac->ops.setup_mac_link = ixgbe_setup_mac_link_82599;
89 		mac->ops.set_rate_select_speed =
90 					       ixgbe_set_hard_rate_select_speed;
91 		if (ixgbe_get_media_type(hw) == ixgbe_media_type_fiber_fixed)
92 			mac->ops.set_rate_select_speed =
93 					       ixgbe_set_soft_rate_select_speed;
94 	} else {
95 		if ((ixgbe_get_media_type(hw) == ixgbe_media_type_backplane) &&
96 		     (hw->phy.smart_speed == ixgbe_smart_speed_auto ||
97 		      hw->phy.smart_speed == ixgbe_smart_speed_on) &&
98 		      !ixgbe_verify_lesm_fw_enabled_82599(hw)) {
99 			mac->ops.setup_link = ixgbe_setup_mac_link_smartspeed;
100 		} else {
101 			mac->ops.setup_link = ixgbe_setup_mac_link_82599;
102 		}
103 	}
104 }
105 
106 /**
107  *  ixgbe_init_phy_ops_82599 - PHY/SFP specific init
108  *  @hw: pointer to hardware structure
109  *
110  *  Initialize any function pointers that were not able to be
111  *  set during init_shared_code because the PHY/SFP type was
112  *  not known.  Perform the SFP init if necessary.
113  *
114  **/
115 s32 ixgbe_init_phy_ops_82599(struct ixgbe_hw *hw)
116 {
117 	struct ixgbe_mac_info *mac = &hw->mac;
118 	struct ixgbe_phy_info *phy = &hw->phy;
119 	s32 ret_val = IXGBE_SUCCESS;
120 	u32 esdp;
121 
122 	DEBUGFUNC("ixgbe_init_phy_ops_82599");
123 
124 	if (hw->device_id == IXGBE_DEV_ID_82599_QSFP_SF_QP) {
125 		/* Store flag indicating I2C bus access control unit. */
126 		hw->phy.qsfp_shared_i2c_bus = TRUE;
127 
128 		/* Initialize access to QSFP+ I2C bus */
129 		esdp = IXGBE_READ_REG(hw, IXGBE_ESDP);
130 		esdp |= IXGBE_ESDP_SDP0_DIR;
131 		esdp &= ~IXGBE_ESDP_SDP1_DIR;
132 		esdp &= ~IXGBE_ESDP_SDP0;
133 		esdp &= ~IXGBE_ESDP_SDP0_NATIVE;
134 		esdp &= ~IXGBE_ESDP_SDP1_NATIVE;
135 		IXGBE_WRITE_REG(hw, IXGBE_ESDP, esdp);
136 		IXGBE_WRITE_FLUSH(hw);
137 
138 		phy->ops.read_i2c_byte = ixgbe_read_i2c_byte_82599;
139 		phy->ops.write_i2c_byte = ixgbe_write_i2c_byte_82599;
140 	}
141 	/* Identify the PHY or SFP module */
142 	ret_val = phy->ops.identify(hw);
143 	if (ret_val == IXGBE_ERR_SFP_NOT_SUPPORTED)
144 		goto init_phy_ops_out;
145 
146 	/* Setup function pointers based on detected SFP module and speeds */
147 	ixgbe_init_mac_link_ops_82599(hw);
148 	if (hw->phy.sfp_type != ixgbe_sfp_type_unknown)
149 		hw->phy.ops.reset = NULL;
150 
151 	/* If copper media, overwrite with copper function pointers */
152 	if (mac->ops.get_media_type(hw) == ixgbe_media_type_copper) {
153 		mac->ops.setup_link = ixgbe_setup_copper_link_82599;
154 		mac->ops.get_link_capabilities =
155 				  ixgbe_get_copper_link_capabilities_generic;
156 	}
157 
158 	/* Set necessary function pointers based on PHY type */
159 	switch (hw->phy.type) {
160 	case ixgbe_phy_tn:
161 		phy->ops.setup_link = ixgbe_setup_phy_link_tnx;
162 		phy->ops.check_link = ixgbe_check_phy_link_tnx;
163 		phy->ops.get_firmware_version =
164 			     ixgbe_get_phy_firmware_version_tnx;
165 		break;
166 	default:
167 		break;
168 	}
169 init_phy_ops_out:
170 	return ret_val;
171 }
172 
173 s32 ixgbe_setup_sfp_modules_82599(struct ixgbe_hw *hw)
174 {
175 	s32 ret_val = IXGBE_SUCCESS;
176 	u16 list_offset, data_offset, data_value;
177 
178 	DEBUGFUNC("ixgbe_setup_sfp_modules_82599");
179 
180 	if (hw->phy.sfp_type != ixgbe_sfp_type_unknown) {
181 		ixgbe_init_mac_link_ops_82599(hw);
182 
183 		hw->phy.ops.reset = NULL;
184 
185 		ret_val = ixgbe_get_sfp_init_sequence_offsets(hw, &list_offset,
186 							      &data_offset);
187 		if (ret_val != IXGBE_SUCCESS)
188 			goto setup_sfp_out;
189 
190 		/* PHY config will finish before releasing the semaphore */
191 		ret_val = hw->mac.ops.acquire_swfw_sync(hw,
192 							IXGBE_GSSR_MAC_CSR_SM);
193 		if (ret_val != IXGBE_SUCCESS) {
194 			ret_val = IXGBE_ERR_SWFW_SYNC;
195 			goto setup_sfp_out;
196 		}
197 
198 		if (hw->eeprom.ops.read(hw, ++data_offset, &data_value))
199 			goto setup_sfp_err;
200 		while (data_value != 0xffff) {
201 			IXGBE_WRITE_REG(hw, IXGBE_CORECTL, data_value);
202 			IXGBE_WRITE_FLUSH(hw);
203 			if (hw->eeprom.ops.read(hw, ++data_offset, &data_value))
204 				goto setup_sfp_err;
205 		}
206 
207 		/* Release the semaphore */
208 		hw->mac.ops.release_swfw_sync(hw, IXGBE_GSSR_MAC_CSR_SM);
209 		/* Delay obtaining semaphore again to allow FW access
210 		 * prot_autoc_write uses the semaphore too.
211 		 */
212 		msec_delay(hw->eeprom.semaphore_delay);
213 
214 		/* Restart DSP and set SFI mode */
215 		ret_val = hw->mac.ops.prot_autoc_write(hw,
216 			hw->mac.orig_autoc | IXGBE_AUTOC_LMS_10G_SERIAL,
217 			FALSE);
218 
219 		if (ret_val) {
220 			DEBUGOUT("sfp module setup not complete\n");
221 			ret_val = IXGBE_ERR_SFP_SETUP_NOT_COMPLETE;
222 			goto setup_sfp_out;
223 		}
224 
225 	}
226 
227 setup_sfp_out:
228 	return ret_val;
229 
230 setup_sfp_err:
231 	/* Release the semaphore */
232 	hw->mac.ops.release_swfw_sync(hw, IXGBE_GSSR_MAC_CSR_SM);
233 	/* Delay obtaining semaphore again to allow FW access */
234 	msec_delay(hw->eeprom.semaphore_delay);
235 	ERROR_REPORT2(IXGBE_ERROR_INVALID_STATE,
236 		      "eeprom read at offset %d failed", data_offset);
237 	return IXGBE_ERR_PHY;
238 }
239 
240 /**
241  *  prot_autoc_read_82599 - Hides MAC differences needed for AUTOC read
242  *  @hw: pointer to hardware structure
243  *  @locked: Return the if we locked for this read.
244  *  @reg_val: Value we read from AUTOC
245  *
246  *  For this part (82599) we need to wrap read-modify-writes with a possible
247  *  FW/SW lock.  It is assumed this lock will be freed with the next
248  *  prot_autoc_write_82599().
249  */
250 s32 prot_autoc_read_82599(struct ixgbe_hw *hw, bool *locked, u32 *reg_val)
251 {
252 	s32 ret_val;
253 
254 	*locked = FALSE;
255 	 /* If LESM is on then we need to hold the SW/FW semaphore. */
256 	if (ixgbe_verify_lesm_fw_enabled_82599(hw)) {
257 		ret_val = hw->mac.ops.acquire_swfw_sync(hw,
258 					IXGBE_GSSR_MAC_CSR_SM);
259 		if (ret_val != IXGBE_SUCCESS)
260 			return IXGBE_ERR_SWFW_SYNC;
261 
262 		*locked = TRUE;
263 	}
264 
265 	*reg_val = IXGBE_READ_REG(hw, IXGBE_AUTOC);
266 	return IXGBE_SUCCESS;
267 }
268 
269 /**
270  * prot_autoc_write_82599 - Hides MAC differences needed for AUTOC write
271  * @hw: pointer to hardware structure
272  * @reg_val: value to write to AUTOC
273  * @locked: bool to indicate whether the SW/FW lock was already taken by
274  *           previous proc_autoc_read_82599.
275  *
276  * This part (82599) may need to hold the SW/FW lock around all writes to
277  * AUTOC. Likewise after a write we need to do a pipeline reset.
278  */
279 s32 prot_autoc_write_82599(struct ixgbe_hw *hw, u32 autoc, bool locked)
280 {
281 	s32 ret_val = IXGBE_SUCCESS;
282 
283 	/* Blocked by MNG FW so bail */
284 	if (ixgbe_check_reset_blocked(hw))
285 		goto out;
286 
287 	/* We only need to get the lock if:
288 	 *  - We didn't do it already (in the read part of a read-modify-write)
289 	 *  - LESM is enabled.
290 	 */
291 	if (!locked && ixgbe_verify_lesm_fw_enabled_82599(hw)) {
292 		ret_val = hw->mac.ops.acquire_swfw_sync(hw,
293 					IXGBE_GSSR_MAC_CSR_SM);
294 		if (ret_val != IXGBE_SUCCESS)
295 			return IXGBE_ERR_SWFW_SYNC;
296 
297 		locked = TRUE;
298 	}
299 
300 	IXGBE_WRITE_REG(hw, IXGBE_AUTOC, autoc);
301 	ret_val = ixgbe_reset_pipeline_82599(hw);
302 
303 out:
304 	/* Free the SW/FW semaphore as we either grabbed it here or
305 	 * already had it when this function was called.
306 	 */
307 	if (locked)
308 		hw->mac.ops.release_swfw_sync(hw, IXGBE_GSSR_MAC_CSR_SM);
309 
310 	return ret_val;
311 }
312 
313 /**
314  *  ixgbe_init_ops_82599 - Inits func ptrs and MAC type
315  *  @hw: pointer to hardware structure
316  *
317  *  Initialize the function pointers and assign the MAC type for 82599.
318  *  Does not touch the hardware.
319  **/
320 
321 s32 ixgbe_init_ops_82599(struct ixgbe_hw *hw)
322 {
323 	struct ixgbe_mac_info *mac = &hw->mac;
324 	struct ixgbe_phy_info *phy = &hw->phy;
325 	struct ixgbe_eeprom_info *eeprom = &hw->eeprom;
326 	s32 ret_val;
327 
328 	DEBUGFUNC("ixgbe_init_ops_82599");
329 
330 	ixgbe_init_phy_ops_generic(hw);
331 	ret_val = ixgbe_init_ops_generic(hw);
332 
333 	/* PHY */
334 	phy->ops.identify = ixgbe_identify_phy_82599;
335 	phy->ops.init = ixgbe_init_phy_ops_82599;
336 
337 	/* MAC */
338 	mac->ops.reset_hw = ixgbe_reset_hw_82599;
339 	mac->ops.enable_relaxed_ordering = ixgbe_enable_relaxed_ordering_gen2;
340 	mac->ops.get_media_type = ixgbe_get_media_type_82599;
341 	mac->ops.get_supported_physical_layer =
342 				    ixgbe_get_supported_physical_layer_82599;
343 	mac->ops.disable_sec_rx_path = ixgbe_disable_sec_rx_path_generic;
344 	mac->ops.enable_sec_rx_path = ixgbe_enable_sec_rx_path_generic;
345 	mac->ops.enable_rx_dma = ixgbe_enable_rx_dma_82599;
346 	mac->ops.read_analog_reg8 = ixgbe_read_analog_reg8_82599;
347 	mac->ops.write_analog_reg8 = ixgbe_write_analog_reg8_82599;
348 	mac->ops.start_hw = ixgbe_start_hw_82599;
349 	mac->ops.get_san_mac_addr = ixgbe_get_san_mac_addr_generic;
350 	mac->ops.set_san_mac_addr = ixgbe_set_san_mac_addr_generic;
351 	mac->ops.get_device_caps = ixgbe_get_device_caps_generic;
352 	mac->ops.get_wwn_prefix = ixgbe_get_wwn_prefix_generic;
353 	mac->ops.get_fcoe_boot_status = ixgbe_get_fcoe_boot_status_generic;
354 	mac->ops.prot_autoc_read = prot_autoc_read_82599;
355 	mac->ops.prot_autoc_write = prot_autoc_write_82599;
356 
357 	/* RAR, Multicast, VLAN */
358 	mac->ops.set_vmdq = ixgbe_set_vmdq_generic;
359 	mac->ops.set_vmdq_san_mac = ixgbe_set_vmdq_san_mac_generic;
360 	mac->ops.clear_vmdq = ixgbe_clear_vmdq_generic;
361 	mac->ops.insert_mac_addr = ixgbe_insert_mac_addr_generic;
362 	mac->rar_highwater = 1;
363 	mac->ops.set_vfta = ixgbe_set_vfta_generic;
364 	mac->ops.set_vlvf = ixgbe_set_vlvf_generic;
365 	mac->ops.clear_vfta = ixgbe_clear_vfta_generic;
366 	mac->ops.init_uta_tables = ixgbe_init_uta_tables_generic;
367 	mac->ops.setup_sfp = ixgbe_setup_sfp_modules_82599;
368 	mac->ops.set_mac_anti_spoofing = ixgbe_set_mac_anti_spoofing;
369 	mac->ops.set_vlan_anti_spoofing = ixgbe_set_vlan_anti_spoofing;
370 
371 	/* Link */
372 	mac->ops.get_link_capabilities = ixgbe_get_link_capabilities_82599;
373 	mac->ops.check_link = ixgbe_check_mac_link_generic;
374 	mac->ops.setup_rxpba = ixgbe_set_rxpba_generic;
375 	ixgbe_init_mac_link_ops_82599(hw);
376 
377 	mac->mcft_size		= IXGBE_82599_MC_TBL_SIZE;
378 	mac->vft_size		= IXGBE_82599_VFT_TBL_SIZE;
379 	mac->num_rar_entries	= IXGBE_82599_RAR_ENTRIES;
380 	mac->rx_pb_size		= IXGBE_82599_RX_PB_SIZE;
381 	mac->max_rx_queues	= IXGBE_82599_MAX_RX_QUEUES;
382 	mac->max_tx_queues	= IXGBE_82599_MAX_TX_QUEUES;
383 	mac->max_msix_vectors	= ixgbe_get_pcie_msix_count_generic(hw);
384 
385 	mac->arc_subsystem_valid = (IXGBE_READ_REG(hw, IXGBE_FWSM) &
386 				   IXGBE_FWSM_MODE_MASK) ? TRUE : FALSE;
387 
388 	hw->mbx.ops.init_params = ixgbe_init_mbx_params_pf;
389 
390 	/* EEPROM */
391 	eeprom->ops.read = ixgbe_read_eeprom_82599;
392 	eeprom->ops.read_buffer = ixgbe_read_eeprom_buffer_82599;
393 
394 	/* Manageability interface */
395 	mac->ops.set_fw_drv_ver = ixgbe_set_fw_drv_ver_generic;
396 
397 
398 	mac->ops.get_rtrup2tc = ixgbe_dcb_get_rtrup2tc_generic;
399 
400 	return ret_val;
401 }
402 
403 /**
404  *  ixgbe_get_link_capabilities_82599 - Determines link capabilities
405  *  @hw: pointer to hardware structure
406  *  @speed: pointer to link speed
407  *  @autoneg: TRUE when autoneg or autotry is enabled
408  *
409  *  Determines the link capabilities by reading the AUTOC register.
410  **/
411 s32 ixgbe_get_link_capabilities_82599(struct ixgbe_hw *hw,
412 				      ixgbe_link_speed *speed,
413 				      bool *autoneg)
414 {
415 	s32 status = IXGBE_SUCCESS;
416 	u32 autoc = 0;
417 
418 	DEBUGFUNC("ixgbe_get_link_capabilities_82599");
419 
420 
421 	/* Check if 1G SFP module. */
422 	if (hw->phy.sfp_type == ixgbe_sfp_type_1g_cu_core0 ||
423 	    hw->phy.sfp_type == ixgbe_sfp_type_1g_cu_core1 ||
424 	    hw->phy.sfp_type == ixgbe_sfp_type_1g_lx_core0 ||
425 	    hw->phy.sfp_type == ixgbe_sfp_type_1g_lx_core1 ||
426 	    hw->phy.sfp_type == ixgbe_sfp_type_1g_sx_core0 ||
427 	    hw->phy.sfp_type == ixgbe_sfp_type_1g_sx_core1) {
428 		*speed = IXGBE_LINK_SPEED_1GB_FULL;
429 		*autoneg = TRUE;
430 		goto out;
431 	}
432 
433 	/*
434 	 * Determine link capabilities based on the stored value of AUTOC,
435 	 * which represents EEPROM defaults.  If AUTOC value has not
436 	 * been stored, use the current register values.
437 	 */
438 	if (hw->mac.orig_link_settings_stored)
439 		autoc = hw->mac.orig_autoc;
440 	else
441 		autoc = IXGBE_READ_REG(hw, IXGBE_AUTOC);
442 
443 	switch (autoc & IXGBE_AUTOC_LMS_MASK) {
444 	case IXGBE_AUTOC_LMS_1G_LINK_NO_AN:
445 		*speed = IXGBE_LINK_SPEED_1GB_FULL;
446 		*autoneg = FALSE;
447 		break;
448 
449 	case IXGBE_AUTOC_LMS_10G_LINK_NO_AN:
450 		*speed = IXGBE_LINK_SPEED_10GB_FULL;
451 		*autoneg = FALSE;
452 		break;
453 
454 	case IXGBE_AUTOC_LMS_1G_AN:
455 		*speed = IXGBE_LINK_SPEED_1GB_FULL;
456 		*autoneg = TRUE;
457 		break;
458 
459 	case IXGBE_AUTOC_LMS_10G_SERIAL:
460 		*speed = IXGBE_LINK_SPEED_10GB_FULL;
461 		*autoneg = FALSE;
462 		break;
463 
464 	case IXGBE_AUTOC_LMS_KX4_KX_KR:
465 	case IXGBE_AUTOC_LMS_KX4_KX_KR_1G_AN:
466 		*speed = IXGBE_LINK_SPEED_UNKNOWN;
467 		if (autoc & IXGBE_AUTOC_KR_SUPP)
468 			*speed |= IXGBE_LINK_SPEED_10GB_FULL;
469 		if (autoc & IXGBE_AUTOC_KX4_SUPP)
470 			*speed |= IXGBE_LINK_SPEED_10GB_FULL;
471 		if (autoc & IXGBE_AUTOC_KX_SUPP)
472 			*speed |= IXGBE_LINK_SPEED_1GB_FULL;
473 		*autoneg = TRUE;
474 		break;
475 
476 	case IXGBE_AUTOC_LMS_KX4_KX_KR_SGMII:
477 		*speed = IXGBE_LINK_SPEED_100_FULL;
478 		if (autoc & IXGBE_AUTOC_KR_SUPP)
479 			*speed |= IXGBE_LINK_SPEED_10GB_FULL;
480 		if (autoc & IXGBE_AUTOC_KX4_SUPP)
481 			*speed |= IXGBE_LINK_SPEED_10GB_FULL;
482 		if (autoc & IXGBE_AUTOC_KX_SUPP)
483 			*speed |= IXGBE_LINK_SPEED_1GB_FULL;
484 		*autoneg = TRUE;
485 		break;
486 
487 	case IXGBE_AUTOC_LMS_SGMII_1G_100M:
488 		*speed = IXGBE_LINK_SPEED_1GB_FULL | IXGBE_LINK_SPEED_100_FULL;
489 		*autoneg = FALSE;
490 		break;
491 
492 	default:
493 		status = IXGBE_ERR_LINK_SETUP;
494 		goto out;
495 		break;
496 	}
497 
498 	if (hw->phy.multispeed_fiber) {
499 		*speed |= IXGBE_LINK_SPEED_10GB_FULL |
500 			  IXGBE_LINK_SPEED_1GB_FULL;
501 
502 		/* QSFP must not enable full auto-negotiation
503 		 * Limited autoneg is enabled at 1G
504 		 */
505 		if (hw->phy.media_type == ixgbe_media_type_fiber_qsfp)
506 			*autoneg = FALSE;
507 		else
508 			*autoneg = TRUE;
509 	}
510 
511 out:
512 	return status;
513 }
514 
515 /**
516  *  ixgbe_get_media_type_82599 - Get media type
517  *  @hw: pointer to hardware structure
518  *
519  *  Returns the media type (fiber, copper, backplane)
520  **/
521 enum ixgbe_media_type ixgbe_get_media_type_82599(struct ixgbe_hw *hw)
522 {
523 	enum ixgbe_media_type media_type;
524 
525 	DEBUGFUNC("ixgbe_get_media_type_82599");
526 
527 	/* Detect if there is a copper PHY attached. */
528 	switch (hw->phy.type) {
529 	case ixgbe_phy_cu_unknown:
530 	case ixgbe_phy_tn:
531 		media_type = ixgbe_media_type_copper;
532 		goto out;
533 	default:
534 		break;
535 	}
536 
537 	switch (hw->device_id) {
538 	case IXGBE_DEV_ID_82599_KX4:
539 	case IXGBE_DEV_ID_82599_KX4_MEZZ:
540 	case IXGBE_DEV_ID_82599_COMBO_BACKPLANE:
541 	case IXGBE_DEV_ID_82599_KR:
542 	case IXGBE_DEV_ID_82599_BACKPLANE_FCOE:
543 	case IXGBE_DEV_ID_82599_XAUI_LOM:
544 		/* Default device ID is mezzanine card KX/KX4 */
545 		media_type = ixgbe_media_type_backplane;
546 		break;
547 	case IXGBE_DEV_ID_82599_SFP:
548 	case IXGBE_DEV_ID_82599_SFP_FCOE:
549 	case IXGBE_DEV_ID_82599_SFP_EM:
550 	case IXGBE_DEV_ID_82599_SFP_SF2:
551 	case IXGBE_DEV_ID_82599_SFP_SF_QP:
552 	case IXGBE_DEV_ID_82599EN_SFP:
553 		media_type = ixgbe_media_type_fiber;
554 		break;
555 	case IXGBE_DEV_ID_82599_CX4:
556 		media_type = ixgbe_media_type_cx4;
557 		break;
558 	case IXGBE_DEV_ID_82599_T3_LOM:
559 		media_type = ixgbe_media_type_copper;
560 		break;
561 	case IXGBE_DEV_ID_82599_QSFP_SF_QP:
562 		media_type = ixgbe_media_type_fiber_qsfp;
563 		break;
564 	case IXGBE_DEV_ID_82599_BYPASS:
565 		media_type = ixgbe_media_type_fiber_fixed;
566 		hw->phy.multispeed_fiber = TRUE;
567 		break;
568 	default:
569 		media_type = ixgbe_media_type_unknown;
570 		break;
571 	}
572 out:
573 	return media_type;
574 }
575 
576 /**
577  *  ixgbe_stop_mac_link_on_d3_82599 - Disables link on D3
578  *  @hw: pointer to hardware structure
579  *
580  *  Disables link during D3 power down sequence.
581  *
582  **/
583 void ixgbe_stop_mac_link_on_d3_82599(struct ixgbe_hw *hw)
584 {
585 	u32 autoc2_reg;
586 	u16 ee_ctrl_2 = 0;
587 
588 	DEBUGFUNC("ixgbe_stop_mac_link_on_d3_82599");
589 	ixgbe_read_eeprom(hw, IXGBE_EEPROM_CTRL_2, &ee_ctrl_2);
590 
591 	if (!ixgbe_mng_present(hw) && !hw->wol_enabled &&
592 	    ee_ctrl_2 & IXGBE_EEPROM_CCD_BIT) {
593 		autoc2_reg = IXGBE_READ_REG(hw, IXGBE_AUTOC2);
594 		autoc2_reg |= IXGBE_AUTOC2_LINK_DISABLE_ON_D3_MASK;
595 		IXGBE_WRITE_REG(hw, IXGBE_AUTOC2, autoc2_reg);
596 	}
597 }
598 
599 /**
600  *  ixgbe_start_mac_link_82599 - Setup MAC link settings
601  *  @hw: pointer to hardware structure
602  *  @autoneg_wait_to_complete: TRUE when waiting for completion is needed
603  *
604  *  Configures link settings based on values in the ixgbe_hw struct.
605  *  Restarts the link.  Performs autonegotiation if needed.
606  **/
607 s32 ixgbe_start_mac_link_82599(struct ixgbe_hw *hw,
608 			       bool autoneg_wait_to_complete)
609 {
610 	u32 autoc_reg;
611 	u32 links_reg;
612 	u32 i;
613 	s32 status = IXGBE_SUCCESS;
614 	bool got_lock = FALSE;
615 
616 	DEBUGFUNC("ixgbe_start_mac_link_82599");
617 
618 
619 	/*  reset_pipeline requires us to hold this lock as it writes to
620 	 *  AUTOC.
621 	 */
622 	if (ixgbe_verify_lesm_fw_enabled_82599(hw)) {
623 		status = hw->mac.ops.acquire_swfw_sync(hw,
624 						       IXGBE_GSSR_MAC_CSR_SM);
625 		if (status != IXGBE_SUCCESS)
626 			goto out;
627 
628 		got_lock = TRUE;
629 	}
630 
631 	/* Restart link */
632 	ixgbe_reset_pipeline_82599(hw);
633 
634 	if (got_lock)
635 		hw->mac.ops.release_swfw_sync(hw, IXGBE_GSSR_MAC_CSR_SM);
636 
637 	/* Only poll for autoneg to complete if specified to do so */
638 	if (autoneg_wait_to_complete) {
639 		autoc_reg = IXGBE_READ_REG(hw, IXGBE_AUTOC);
640 		if ((autoc_reg & IXGBE_AUTOC_LMS_MASK) ==
641 		     IXGBE_AUTOC_LMS_KX4_KX_KR ||
642 		    (autoc_reg & IXGBE_AUTOC_LMS_MASK) ==
643 		     IXGBE_AUTOC_LMS_KX4_KX_KR_1G_AN ||
644 		    (autoc_reg & IXGBE_AUTOC_LMS_MASK) ==
645 		     IXGBE_AUTOC_LMS_KX4_KX_KR_SGMII) {
646 			links_reg = 0; /* Just in case Autoneg time = 0 */
647 			for (i = 0; i < IXGBE_AUTO_NEG_TIME; i++) {
648 				links_reg = IXGBE_READ_REG(hw, IXGBE_LINKS);
649 				if (links_reg & IXGBE_LINKS_KX_AN_COMP)
650 					break;
651 				msec_delay(100);
652 			}
653 			if (!(links_reg & IXGBE_LINKS_KX_AN_COMP)) {
654 				status = IXGBE_ERR_AUTONEG_NOT_COMPLETE;
655 				DEBUGOUT("Autoneg did not complete.\n");
656 			}
657 		}
658 	}
659 
660 	/* Add delay to filter out noises during initial link setup */
661 	msec_delay(50);
662 
663 out:
664 	return status;
665 }
666 
667 /**
668  *  ixgbe_disable_tx_laser_multispeed_fiber - Disable Tx laser
669  *  @hw: pointer to hardware structure
670  *
671  *  The base drivers may require better control over SFP+ module
672  *  PHY states.  This includes selectively shutting down the Tx
673  *  laser on the PHY, effectively halting physical link.
674  **/
675 void ixgbe_disable_tx_laser_multispeed_fiber(struct ixgbe_hw *hw)
676 {
677 	u32 esdp_reg = IXGBE_READ_REG(hw, IXGBE_ESDP);
678 
679 	/* Blocked by MNG FW so bail */
680 	if (ixgbe_check_reset_blocked(hw))
681 		return;
682 
683 	/* Disable Tx laser; allow 100us to go dark per spec */
684 	esdp_reg |= IXGBE_ESDP_SDP3;
685 	IXGBE_WRITE_REG(hw, IXGBE_ESDP, esdp_reg);
686 	IXGBE_WRITE_FLUSH(hw);
687 	usec_delay(100);
688 }
689 
690 /**
691  *  ixgbe_enable_tx_laser_multispeed_fiber - Enable Tx laser
692  *  @hw: pointer to hardware structure
693  *
694  *  The base drivers may require better control over SFP+ module
695  *  PHY states.  This includes selectively turning on the Tx
696  *  laser on the PHY, effectively starting physical link.
697  **/
698 void ixgbe_enable_tx_laser_multispeed_fiber(struct ixgbe_hw *hw)
699 {
700 	u32 esdp_reg = IXGBE_READ_REG(hw, IXGBE_ESDP);
701 
702 	/* Enable Tx laser; allow 100ms to light up */
703 	esdp_reg &= ~IXGBE_ESDP_SDP3;
704 	IXGBE_WRITE_REG(hw, IXGBE_ESDP, esdp_reg);
705 	IXGBE_WRITE_FLUSH(hw);
706 	msec_delay(100);
707 }
708 
709 /**
710  *  ixgbe_flap_tx_laser_multispeed_fiber - Flap Tx laser
711  *  @hw: pointer to hardware structure
712  *
713  *  When the driver changes the link speeds that it can support,
714  *  it sets autotry_restart to TRUE to indicate that we need to
715  *  initiate a new autotry session with the link partner.  To do
716  *  so, we set the speed then disable and re-enable the Tx laser, to
717  *  alert the link partner that it also needs to restart autotry on its
718  *  end.  This is consistent with TRUE clause 37 autoneg, which also
719  *  involves a loss of signal.
720  **/
721 void ixgbe_flap_tx_laser_multispeed_fiber(struct ixgbe_hw *hw)
722 {
723 	DEBUGFUNC("ixgbe_flap_tx_laser_multispeed_fiber");
724 
725 	/* Blocked by MNG FW so bail */
726 	if (ixgbe_check_reset_blocked(hw))
727 		return;
728 
729 	if (hw->mac.autotry_restart) {
730 		ixgbe_disable_tx_laser_multispeed_fiber(hw);
731 		ixgbe_enable_tx_laser_multispeed_fiber(hw);
732 		hw->mac.autotry_restart = FALSE;
733 	}
734 }
735 
736 /**
737  *  ixgbe_set_hard_rate_select_speed - Set module link speed
738  *  @hw: pointer to hardware structure
739  *  @speed: link speed to set
740  *
741  *  Set module link speed via RS0/RS1 rate select pins.
742  */
743 void ixgbe_set_hard_rate_select_speed(struct ixgbe_hw *hw,
744 					ixgbe_link_speed speed)
745 {
746 	u32 esdp_reg = IXGBE_READ_REG(hw, IXGBE_ESDP);
747 
748 	switch (speed) {
749 	case IXGBE_LINK_SPEED_10GB_FULL:
750 		esdp_reg |= (IXGBE_ESDP_SDP5_DIR | IXGBE_ESDP_SDP5);
751 		break;
752 	case IXGBE_LINK_SPEED_1GB_FULL:
753 		esdp_reg &= ~IXGBE_ESDP_SDP5;
754 		esdp_reg |= IXGBE_ESDP_SDP5_DIR;
755 		break;
756 	default:
757 		DEBUGOUT("Invalid fixed module speed\n");
758 		return;
759 	}
760 
761 	IXGBE_WRITE_REG(hw, IXGBE_ESDP, esdp_reg);
762 	IXGBE_WRITE_FLUSH(hw);
763 }
764 
765 /**
766  *  ixgbe_setup_mac_link_smartspeed - Set MAC link speed using SmartSpeed
767  *  @hw: pointer to hardware structure
768  *  @speed: new link speed
769  *  @autoneg_wait_to_complete: TRUE when waiting for completion is needed
770  *
771  *  Implements the Intel SmartSpeed algorithm.
772  **/
773 s32 ixgbe_setup_mac_link_smartspeed(struct ixgbe_hw *hw,
774 				    ixgbe_link_speed speed,
775 				    bool autoneg_wait_to_complete)
776 {
777 	s32 status = IXGBE_SUCCESS;
778 	ixgbe_link_speed link_speed = IXGBE_LINK_SPEED_UNKNOWN;
779 	s32 i, j;
780 	bool link_up = FALSE;
781 	u32 autoc_reg = IXGBE_READ_REG(hw, IXGBE_AUTOC);
782 
783 	DEBUGFUNC("ixgbe_setup_mac_link_smartspeed");
784 
785 	 /* Set autoneg_advertised value based on input link speed */
786 	hw->phy.autoneg_advertised = 0;
787 
788 	if (speed & IXGBE_LINK_SPEED_10GB_FULL)
789 		hw->phy.autoneg_advertised |= IXGBE_LINK_SPEED_10GB_FULL;
790 
791 	if (speed & IXGBE_LINK_SPEED_1GB_FULL)
792 		hw->phy.autoneg_advertised |= IXGBE_LINK_SPEED_1GB_FULL;
793 
794 	if (speed & IXGBE_LINK_SPEED_100_FULL)
795 		hw->phy.autoneg_advertised |= IXGBE_LINK_SPEED_100_FULL;
796 
797 	/*
798 	 * Implement Intel SmartSpeed algorithm.  SmartSpeed will reduce the
799 	 * autoneg advertisement if link is unable to be established at the
800 	 * highest negotiated rate.  This can sometimes happen due to integrity
801 	 * issues with the physical media connection.
802 	 */
803 
804 	/* First, try to get link with full advertisement */
805 	hw->phy.smart_speed_active = FALSE;
806 	for (j = 0; j < IXGBE_SMARTSPEED_MAX_RETRIES; j++) {
807 		status = ixgbe_setup_mac_link_82599(hw, speed,
808 						    autoneg_wait_to_complete);
809 		if (status != IXGBE_SUCCESS)
810 			goto out;
811 
812 		/*
813 		 * Wait for the controller to acquire link.  Per IEEE 802.3ap,
814 		 * Section 73.10.2, we may have to wait up to 500ms if KR is
815 		 * attempted, or 200ms if KX/KX4/BX/BX4 is attempted, per
816 		 * Table 9 in the AN MAS.
817 		 */
818 		for (i = 0; i < 5; i++) {
819 			msec_delay(100);
820 
821 			/* If we have link, just jump out */
822 			status = ixgbe_check_link(hw, &link_speed, &link_up,
823 						  FALSE);
824 			if (status != IXGBE_SUCCESS)
825 				goto out;
826 
827 			if (link_up)
828 				goto out;
829 		}
830 	}
831 
832 	/*
833 	 * We didn't get link.  If we advertised KR plus one of KX4/KX
834 	 * (or BX4/BX), then disable KR and try again.
835 	 */
836 	if (((autoc_reg & IXGBE_AUTOC_KR_SUPP) == 0) ||
837 	    ((autoc_reg & IXGBE_AUTOC_KX4_KX_SUPP_MASK) == 0))
838 		goto out;
839 
840 	/* Turn SmartSpeed on to disable KR support */
841 	hw->phy.smart_speed_active = TRUE;
842 	status = ixgbe_setup_mac_link_82599(hw, speed,
843 					    autoneg_wait_to_complete);
844 	if (status != IXGBE_SUCCESS)
845 		goto out;
846 
847 	/*
848 	 * Wait for the controller to acquire link.  600ms will allow for
849 	 * the AN link_fail_inhibit_timer as well for multiple cycles of
850 	 * parallel detect, both 10g and 1g. This allows for the maximum
851 	 * connect attempts as defined in the AN MAS table 73-7.
852 	 */
853 	for (i = 0; i < 6; i++) {
854 		msec_delay(100);
855 
856 		/* If we have link, just jump out */
857 		status = ixgbe_check_link(hw, &link_speed, &link_up, FALSE);
858 		if (status != IXGBE_SUCCESS)
859 			goto out;
860 
861 		if (link_up)
862 			goto out;
863 	}
864 
865 	/* We didn't get link.  Turn SmartSpeed back off. */
866 	hw->phy.smart_speed_active = FALSE;
867 	status = ixgbe_setup_mac_link_82599(hw, speed,
868 					    autoneg_wait_to_complete);
869 
870 out:
871 	if (link_up && (link_speed == IXGBE_LINK_SPEED_1GB_FULL))
872 		DEBUGOUT("Smartspeed has downgraded the link speed "
873 		"from the maximum advertised\n");
874 	return status;
875 }
876 
877 /**
878  *  ixgbe_setup_mac_link_82599 - Set MAC link speed
879  *  @hw: pointer to hardware structure
880  *  @speed: new link speed
881  *  @autoneg_wait_to_complete: TRUE when waiting for completion is needed
882  *
883  *  Set the link speed in the AUTOC register and restarts link.
884  **/
885 s32 ixgbe_setup_mac_link_82599(struct ixgbe_hw *hw,
886 			       ixgbe_link_speed speed,
887 			       bool autoneg_wait_to_complete)
888 {
889 	bool autoneg = FALSE;
890 	s32 status = IXGBE_SUCCESS;
891 	u32 pma_pmd_1g, link_mode;
892 	u32 current_autoc = IXGBE_READ_REG(hw, IXGBE_AUTOC); /* holds the value of AUTOC register at this current point in time */
893 	u32 orig_autoc = 0; /* holds the cached value of AUTOC register */
894 	u32 autoc = current_autoc; /* Temporary variable used for comparison purposes */
895 	u32 autoc2 = IXGBE_READ_REG(hw, IXGBE_AUTOC2);
896 	u32 pma_pmd_10g_serial = autoc2 & IXGBE_AUTOC2_10G_SERIAL_PMA_PMD_MASK;
897 	u32 links_reg;
898 	u32 i;
899 	ixgbe_link_speed link_capabilities = IXGBE_LINK_SPEED_UNKNOWN;
900 
901 	DEBUGFUNC("ixgbe_setup_mac_link_82599");
902 
903 	/* Check to see if speed passed in is supported. */
904 	status = ixgbe_get_link_capabilities(hw, &link_capabilities, &autoneg);
905 	if (status)
906 		goto out;
907 
908 	speed &= link_capabilities;
909 
910 	if (speed == IXGBE_LINK_SPEED_UNKNOWN) {
911 		status = IXGBE_ERR_LINK_SETUP;
912 		goto out;
913 	}
914 
915 	/* Use stored value (EEPROM defaults) of AUTOC to find KR/KX4 support*/
916 	if (hw->mac.orig_link_settings_stored)
917 		orig_autoc = hw->mac.orig_autoc;
918 	else
919 		orig_autoc = autoc;
920 
921 	link_mode = autoc & IXGBE_AUTOC_LMS_MASK;
922 	pma_pmd_1g = autoc & IXGBE_AUTOC_1G_PMA_PMD_MASK;
923 
924 	if (link_mode == IXGBE_AUTOC_LMS_KX4_KX_KR ||
925 	    link_mode == IXGBE_AUTOC_LMS_KX4_KX_KR_1G_AN ||
926 	    link_mode == IXGBE_AUTOC_LMS_KX4_KX_KR_SGMII) {
927 		/* Set KX4/KX/KR support according to speed requested */
928 		autoc &= ~(IXGBE_AUTOC_KX4_KX_SUPP_MASK | IXGBE_AUTOC_KR_SUPP);
929 		if (speed & IXGBE_LINK_SPEED_10GB_FULL) {
930 			if (orig_autoc & IXGBE_AUTOC_KX4_SUPP)
931 				autoc |= IXGBE_AUTOC_KX4_SUPP;
932 			if ((orig_autoc & IXGBE_AUTOC_KR_SUPP) &&
933 			    (hw->phy.smart_speed_active == FALSE))
934 				autoc |= IXGBE_AUTOC_KR_SUPP;
935 		}
936 		if (speed & IXGBE_LINK_SPEED_1GB_FULL)
937 			autoc |= IXGBE_AUTOC_KX_SUPP;
938 	} else if ((pma_pmd_1g == IXGBE_AUTOC_1G_SFI) &&
939 		   (link_mode == IXGBE_AUTOC_LMS_1G_LINK_NO_AN ||
940 		    link_mode == IXGBE_AUTOC_LMS_1G_AN)) {
941 		/* Switch from 1G SFI to 10G SFI if requested */
942 		if ((speed == IXGBE_LINK_SPEED_10GB_FULL) &&
943 		    (pma_pmd_10g_serial == IXGBE_AUTOC2_10G_SFI)) {
944 			autoc &= ~IXGBE_AUTOC_LMS_MASK;
945 			autoc |= IXGBE_AUTOC_LMS_10G_SERIAL;
946 		}
947 	} else if ((pma_pmd_10g_serial == IXGBE_AUTOC2_10G_SFI) &&
948 		   (link_mode == IXGBE_AUTOC_LMS_10G_SERIAL)) {
949 		/* Switch from 10G SFI to 1G SFI if requested */
950 		if ((speed == IXGBE_LINK_SPEED_1GB_FULL) &&
951 		    (pma_pmd_1g == IXGBE_AUTOC_1G_SFI)) {
952 			autoc &= ~IXGBE_AUTOC_LMS_MASK;
953 			if (autoneg || hw->phy.type == ixgbe_phy_qsfp_intel)
954 				autoc |= IXGBE_AUTOC_LMS_1G_AN;
955 			else
956 				autoc |= IXGBE_AUTOC_LMS_1G_LINK_NO_AN;
957 		}
958 	}
959 
960 	if (autoc != current_autoc) {
961 		/* Restart link */
962 		status = hw->mac.ops.prot_autoc_write(hw, autoc, FALSE);
963 		if (status != IXGBE_SUCCESS)
964 			goto out;
965 
966 		/* Only poll for autoneg to complete if specified to do so */
967 		if (autoneg_wait_to_complete) {
968 			if (link_mode == IXGBE_AUTOC_LMS_KX4_KX_KR ||
969 			    link_mode == IXGBE_AUTOC_LMS_KX4_KX_KR_1G_AN ||
970 			    link_mode == IXGBE_AUTOC_LMS_KX4_KX_KR_SGMII) {
971 				links_reg = 0; /*Just in case Autoneg time=0*/
972 				for (i = 0; i < IXGBE_AUTO_NEG_TIME; i++) {
973 					links_reg =
974 					       IXGBE_READ_REG(hw, IXGBE_LINKS);
975 					if (links_reg & IXGBE_LINKS_KX_AN_COMP)
976 						break;
977 					msec_delay(100);
978 				}
979 				if (!(links_reg & IXGBE_LINKS_KX_AN_COMP)) {
980 					status =
981 						IXGBE_ERR_AUTONEG_NOT_COMPLETE;
982 					DEBUGOUT("Autoneg did not complete.\n");
983 				}
984 			}
985 		}
986 
987 		/* Add delay to filter out noises during initial link setup */
988 		msec_delay(50);
989 	}
990 
991 out:
992 	return status;
993 }
994 
995 /**
996  *  ixgbe_setup_copper_link_82599 - Set the PHY autoneg advertised field
997  *  @hw: pointer to hardware structure
998  *  @speed: new link speed
999  *  @autoneg_wait_to_complete: TRUE if waiting is needed to complete
1000  *
1001  *  Restarts link on PHY and MAC based on settings passed in.
1002  **/
1003 static s32 ixgbe_setup_copper_link_82599(struct ixgbe_hw *hw,
1004 					 ixgbe_link_speed speed,
1005 					 bool autoneg_wait_to_complete)
1006 {
1007 	s32 status;
1008 
1009 	DEBUGFUNC("ixgbe_setup_copper_link_82599");
1010 
1011 	/* Setup the PHY according to input speed */
1012 	status = hw->phy.ops.setup_link_speed(hw, speed,
1013 					      autoneg_wait_to_complete);
1014 	/* Set up MAC */
1015 	ixgbe_start_mac_link_82599(hw, autoneg_wait_to_complete);
1016 
1017 	return status;
1018 }
1019 
1020 /**
1021  *  ixgbe_reset_hw_82599 - Perform hardware reset
1022  *  @hw: pointer to hardware structure
1023  *
1024  *  Resets the hardware by resetting the transmit and receive units, masks
1025  *  and clears all interrupts, perform a PHY reset, and perform a link (MAC)
1026  *  reset.
1027  **/
1028 s32 ixgbe_reset_hw_82599(struct ixgbe_hw *hw)
1029 {
1030 	ixgbe_link_speed link_speed;
1031 	s32 status;
1032 	u32 ctrl = 0;
1033 	u32 i, autoc, autoc2;
1034 	u32 curr_lms;
1035 	bool link_up = FALSE;
1036 
1037 	DEBUGFUNC("ixgbe_reset_hw_82599");
1038 
1039 	/* Call adapter stop to disable tx/rx and clear interrupts */
1040 	status = hw->mac.ops.stop_adapter(hw);
1041 	if (status != IXGBE_SUCCESS)
1042 		goto reset_hw_out;
1043 
1044 	/* flush pending Tx transactions */
1045 	ixgbe_clear_tx_pending(hw);
1046 
1047 	/* PHY ops must be identified and initialized prior to reset */
1048 
1049 	/* Identify PHY and related function pointers */
1050 	status = hw->phy.ops.init(hw);
1051 
1052 	if (status == IXGBE_ERR_SFP_NOT_SUPPORTED)
1053 		goto reset_hw_out;
1054 
1055 	/* Setup SFP module if there is one present. */
1056 	if (hw->phy.sfp_setup_needed) {
1057 		status = hw->mac.ops.setup_sfp(hw);
1058 		hw->phy.sfp_setup_needed = FALSE;
1059 	}
1060 
1061 	if (status == IXGBE_ERR_SFP_NOT_SUPPORTED)
1062 		goto reset_hw_out;
1063 
1064 	/* Reset PHY */
1065 	if (hw->phy.reset_disable == FALSE && hw->phy.ops.reset != NULL)
1066 		hw->phy.ops.reset(hw);
1067 
1068 	/* remember AUTOC from before we reset */
1069 	curr_lms = IXGBE_READ_REG(hw, IXGBE_AUTOC) & IXGBE_AUTOC_LMS_MASK;
1070 
1071 mac_reset_top:
1072 	/*
1073 	 * Issue global reset to the MAC.  Needs to be SW reset if link is up.
1074 	 * If link reset is used when link is up, it might reset the PHY when
1075 	 * mng is using it.  If link is down or the flag to force full link
1076 	 * reset is set, then perform link reset.
1077 	 */
1078 	ctrl = IXGBE_CTRL_LNK_RST;
1079 	if (!hw->force_full_reset) {
1080 		hw->mac.ops.check_link(hw, &link_speed, &link_up, FALSE);
1081 		if (link_up)
1082 			ctrl = IXGBE_CTRL_RST;
1083 	}
1084 
1085 	ctrl |= IXGBE_READ_REG(hw, IXGBE_CTRL);
1086 	IXGBE_WRITE_REG(hw, IXGBE_CTRL, ctrl);
1087 	IXGBE_WRITE_FLUSH(hw);
1088 
1089 	/* Poll for reset bit to self-clear meaning reset is complete */
1090 	for (i = 0; i < 10; i++) {
1091 		usec_delay(1);
1092 		ctrl = IXGBE_READ_REG(hw, IXGBE_CTRL);
1093 		if (!(ctrl & IXGBE_CTRL_RST_MASK))
1094 			break;
1095 	}
1096 
1097 	if (ctrl & IXGBE_CTRL_RST_MASK) {
1098 		status = IXGBE_ERR_RESET_FAILED;
1099 		DEBUGOUT("Reset polling failed to complete.\n");
1100 	}
1101 
1102 	msec_delay(50);
1103 
1104 	/*
1105 	 * Double resets are required for recovery from certain error
1106 	 * conditions.  Between resets, it is necessary to stall to
1107 	 * allow time for any pending HW events to complete.
1108 	 */
1109 	if (hw->mac.flags & IXGBE_FLAGS_DOUBLE_RESET_REQUIRED) {
1110 		hw->mac.flags &= ~IXGBE_FLAGS_DOUBLE_RESET_REQUIRED;
1111 		goto mac_reset_top;
1112 	}
1113 
1114 	/*
1115 	 * Store the original AUTOC/AUTOC2 values if they have not been
1116 	 * stored off yet.  Otherwise restore the stored original
1117 	 * values since the reset operation sets back to defaults.
1118 	 */
1119 	autoc = IXGBE_READ_REG(hw, IXGBE_AUTOC);
1120 	autoc2 = IXGBE_READ_REG(hw, IXGBE_AUTOC2);
1121 
1122 	/* Enable link if disabled in NVM */
1123 	if (autoc2 & IXGBE_AUTOC2_LINK_DISABLE_MASK) {
1124 		autoc2 &= ~IXGBE_AUTOC2_LINK_DISABLE_MASK;
1125 		IXGBE_WRITE_REG(hw, IXGBE_AUTOC2, autoc2);
1126 		IXGBE_WRITE_FLUSH(hw);
1127 	}
1128 
1129 	if (hw->mac.orig_link_settings_stored == FALSE) {
1130 		hw->mac.orig_autoc = autoc;
1131 		hw->mac.orig_autoc2 = autoc2;
1132 		hw->mac.orig_link_settings_stored = TRUE;
1133 	} else {
1134 
1135 		/* If MNG FW is running on a multi-speed device that
1136 		 * doesn't autoneg with out driver support we need to
1137 		 * leave LMS in the state it was before we MAC reset.
1138 		 * Likewise if we support WoL we don't want change the
1139 		 * LMS state.
1140 		 */
1141 		if ((hw->phy.multispeed_fiber && ixgbe_mng_enabled(hw)) ||
1142 		    hw->wol_enabled)
1143 			hw->mac.orig_autoc =
1144 				(hw->mac.orig_autoc & ~IXGBE_AUTOC_LMS_MASK) |
1145 				curr_lms;
1146 
1147 		if (autoc != hw->mac.orig_autoc) {
1148 			status = hw->mac.ops.prot_autoc_write(hw,
1149 							hw->mac.orig_autoc,
1150 							FALSE);
1151 			if (status != IXGBE_SUCCESS)
1152 				goto reset_hw_out;
1153 		}
1154 
1155 		if ((autoc2 & IXGBE_AUTOC2_UPPER_MASK) !=
1156 		    (hw->mac.orig_autoc2 & IXGBE_AUTOC2_UPPER_MASK)) {
1157 			autoc2 &= ~IXGBE_AUTOC2_UPPER_MASK;
1158 			autoc2 |= (hw->mac.orig_autoc2 &
1159 				   IXGBE_AUTOC2_UPPER_MASK);
1160 			IXGBE_WRITE_REG(hw, IXGBE_AUTOC2, autoc2);
1161 		}
1162 	}
1163 
1164 	/* Store the permanent mac address */
1165 	hw->mac.ops.get_mac_addr(hw, hw->mac.perm_addr);
1166 
1167 	/*
1168 	 * Store MAC address from RAR0, clear receive address registers, and
1169 	 * clear the multicast table.  Also reset num_rar_entries to 128,
1170 	 * since we modify this value when programming the SAN MAC address.
1171 	 */
1172 	hw->mac.num_rar_entries = 128;
1173 	hw->mac.ops.init_rx_addrs(hw);
1174 
1175 	/* Store the permanent SAN mac address */
1176 	hw->mac.ops.get_san_mac_addr(hw, hw->mac.san_addr);
1177 
1178 	/* Add the SAN MAC address to the RAR only if it's a valid address */
1179 	if (ixgbe_validate_mac_addr(hw->mac.san_addr) == 0) {
1180 		hw->mac.ops.set_rar(hw, hw->mac.num_rar_entries - 1,
1181 				    hw->mac.san_addr, 0, IXGBE_RAH_AV);
1182 
1183 		/* Save the SAN MAC RAR index */
1184 		hw->mac.san_mac_rar_index = hw->mac.num_rar_entries - 1;
1185 
1186 		/* Reserve the last RAR for the SAN MAC address */
1187 		hw->mac.num_rar_entries--;
1188 	}
1189 
1190 	/* Store the alternative WWNN/WWPN prefix */
1191 	hw->mac.ops.get_wwn_prefix(hw, &hw->mac.wwnn_prefix,
1192 				   &hw->mac.wwpn_prefix);
1193 
1194 reset_hw_out:
1195 	return status;
1196 }
1197 
1198 /**
1199  * ixgbe_fdir_check_cmd_complete - poll to check whether FDIRCMD is complete
1200  * @hw: pointer to hardware structure
1201  * @fdircmd: current value of FDIRCMD register
1202  */
1203 static s32 ixgbe_fdir_check_cmd_complete(struct ixgbe_hw *hw, u32 *fdircmd)
1204 {
1205 	int i;
1206 
1207 	for (i = 0; i < IXGBE_FDIRCMD_CMD_POLL; i++) {
1208 		*fdircmd = IXGBE_READ_REG(hw, IXGBE_FDIRCMD);
1209 		if (!(*fdircmd & IXGBE_FDIRCMD_CMD_MASK))
1210 			return IXGBE_SUCCESS;
1211 		usec_delay(10);
1212 	}
1213 
1214 	return IXGBE_ERR_FDIR_CMD_INCOMPLETE;
1215 }
1216 
1217 /**
1218  *  ixgbe_reinit_fdir_tables_82599 - Reinitialize Flow Director tables.
1219  *  @hw: pointer to hardware structure
1220  **/
1221 s32 ixgbe_reinit_fdir_tables_82599(struct ixgbe_hw *hw)
1222 {
1223 	s32 err;
1224 	int i;
1225 	u32 fdirctrl = IXGBE_READ_REG(hw, IXGBE_FDIRCTRL);
1226 	u32 fdircmd;
1227 	fdirctrl &= ~IXGBE_FDIRCTRL_INIT_DONE;
1228 
1229 	DEBUGFUNC("ixgbe_reinit_fdir_tables_82599");
1230 
1231 	/*
1232 	 * Before starting reinitialization process,
1233 	 * FDIRCMD.CMD must be zero.
1234 	 */
1235 	err = ixgbe_fdir_check_cmd_complete(hw, &fdircmd);
1236 	if (err) {
1237 		DEBUGOUT("Flow Director previous command did not complete, aborting table re-initialization.\n");
1238 		return err;
1239 	}
1240 
1241 	IXGBE_WRITE_REG(hw, IXGBE_FDIRFREE, 0);
1242 	IXGBE_WRITE_FLUSH(hw);
1243 	/*
1244 	 * 82599 adapters flow director init flow cannot be restarted,
1245 	 * Workaround 82599 silicon errata by performing the following steps
1246 	 * before re-writing the FDIRCTRL control register with the same value.
1247 	 * - write 1 to bit 8 of FDIRCMD register &
1248 	 * - write 0 to bit 8 of FDIRCMD register
1249 	 */
1250 	IXGBE_WRITE_REG(hw, IXGBE_FDIRCMD,
1251 			(IXGBE_READ_REG(hw, IXGBE_FDIRCMD) |
1252 			 IXGBE_FDIRCMD_CLEARHT));
1253 	IXGBE_WRITE_FLUSH(hw);
1254 	IXGBE_WRITE_REG(hw, IXGBE_FDIRCMD,
1255 			(IXGBE_READ_REG(hw, IXGBE_FDIRCMD) &
1256 			 ~IXGBE_FDIRCMD_CLEARHT));
1257 	IXGBE_WRITE_FLUSH(hw);
1258 	/*
1259 	 * Clear FDIR Hash register to clear any leftover hashes
1260 	 * waiting to be programmed.
1261 	 */
1262 	IXGBE_WRITE_REG(hw, IXGBE_FDIRHASH, 0x00);
1263 	IXGBE_WRITE_FLUSH(hw);
1264 
1265 	IXGBE_WRITE_REG(hw, IXGBE_FDIRCTRL, fdirctrl);
1266 	IXGBE_WRITE_FLUSH(hw);
1267 
1268 	/* Poll init-done after we write FDIRCTRL register */
1269 	for (i = 0; i < IXGBE_FDIR_INIT_DONE_POLL; i++) {
1270 		if (IXGBE_READ_REG(hw, IXGBE_FDIRCTRL) &
1271 				   IXGBE_FDIRCTRL_INIT_DONE)
1272 			break;
1273 		msec_delay(1);
1274 	}
1275 	if (i >= IXGBE_FDIR_INIT_DONE_POLL) {
1276 		DEBUGOUT("Flow Director Signature poll time exceeded!\n");
1277 		return IXGBE_ERR_FDIR_REINIT_FAILED;
1278 	}
1279 
1280 	/* Clear FDIR statistics registers (read to clear) */
1281 	IXGBE_READ_REG(hw, IXGBE_FDIRUSTAT);
1282 	IXGBE_READ_REG(hw, IXGBE_FDIRFSTAT);
1283 	IXGBE_READ_REG(hw, IXGBE_FDIRMATCH);
1284 	IXGBE_READ_REG(hw, IXGBE_FDIRMISS);
1285 	IXGBE_READ_REG(hw, IXGBE_FDIRLEN);
1286 
1287 	return IXGBE_SUCCESS;
1288 }
1289 
1290 /**
1291  *  ixgbe_fdir_enable_82599 - Initialize Flow Director control registers
1292  *  @hw: pointer to hardware structure
1293  *  @fdirctrl: value to write to flow director control register
1294  **/
1295 static void ixgbe_fdir_enable_82599(struct ixgbe_hw *hw, u32 fdirctrl)
1296 {
1297 	int i;
1298 
1299 	DEBUGFUNC("ixgbe_fdir_enable_82599");
1300 
1301 	/* Prime the keys for hashing */
1302 	IXGBE_WRITE_REG(hw, IXGBE_FDIRHKEY, IXGBE_ATR_BUCKET_HASH_KEY);
1303 	IXGBE_WRITE_REG(hw, IXGBE_FDIRSKEY, IXGBE_ATR_SIGNATURE_HASH_KEY);
1304 
1305 	/*
1306 	 * Poll init-done after we write the register.  Estimated times:
1307 	 *      10G: PBALLOC = 11b, timing is 60us
1308 	 *       1G: PBALLOC = 11b, timing is 600us
1309 	 *     100M: PBALLOC = 11b, timing is 6ms
1310 	 *
1311 	 *     Multiple these timings by 4 if under full Rx load
1312 	 *
1313 	 * So we'll poll for IXGBE_FDIR_INIT_DONE_POLL times, sleeping for
1314 	 * 1 msec per poll time.  If we're at line rate and drop to 100M, then
1315 	 * this might not finish in our poll time, but we can live with that
1316 	 * for now.
1317 	 */
1318 	IXGBE_WRITE_REG(hw, IXGBE_FDIRCTRL, fdirctrl);
1319 	IXGBE_WRITE_FLUSH(hw);
1320 	for (i = 0; i < IXGBE_FDIR_INIT_DONE_POLL; i++) {
1321 		if (IXGBE_READ_REG(hw, IXGBE_FDIRCTRL) &
1322 				   IXGBE_FDIRCTRL_INIT_DONE)
1323 			break;
1324 		msec_delay(1);
1325 	}
1326 
1327 	if (i >= IXGBE_FDIR_INIT_DONE_POLL)
1328 		DEBUGOUT("Flow Director poll time exceeded!\n");
1329 }
1330 
1331 /**
1332  *  ixgbe_init_fdir_signature_82599 - Initialize Flow Director signature filters
1333  *  @hw: pointer to hardware structure
1334  *  @fdirctrl: value to write to flow director control register, initially
1335  *	     contains just the value of the Rx packet buffer allocation
1336  **/
1337 s32 ixgbe_init_fdir_signature_82599(struct ixgbe_hw *hw, u32 fdirctrl)
1338 {
1339 	DEBUGFUNC("ixgbe_init_fdir_signature_82599");
1340 
1341 	/*
1342 	 * Continue setup of fdirctrl register bits:
1343 	 *  Move the flexible bytes to use the ethertype - shift 6 words
1344 	 *  Set the maximum length per hash bucket to 0xA filters
1345 	 *  Send interrupt when 64 filters are left
1346 	 */
1347 	fdirctrl |= (0x6 << IXGBE_FDIRCTRL_FLEX_SHIFT) |
1348 		    (0xA << IXGBE_FDIRCTRL_MAX_LENGTH_SHIFT) |
1349 		    (4 << IXGBE_FDIRCTRL_FULL_THRESH_SHIFT);
1350 
1351 	/* write hashes and fdirctrl register, poll for completion */
1352 	ixgbe_fdir_enable_82599(hw, fdirctrl);
1353 
1354 	return IXGBE_SUCCESS;
1355 }
1356 
1357 /**
1358  *  ixgbe_init_fdir_perfect_82599 - Initialize Flow Director perfect filters
1359  *  @hw: pointer to hardware structure
1360  *  @fdirctrl: value to write to flow director control register, initially
1361  *	     contains just the value of the Rx packet buffer allocation
1362  *  @cloud_mode: TRUE - cloud mode, FALSE - other mode
1363  **/
1364 s32 ixgbe_init_fdir_perfect_82599(struct ixgbe_hw *hw, u32 fdirctrl,
1365 			bool cloud_mode)
1366 {
1367 	DEBUGFUNC("ixgbe_init_fdir_perfect_82599");
1368 
1369 	/*
1370 	 * Continue setup of fdirctrl register bits:
1371 	 *  Turn perfect match filtering on
1372 	 *  Report hash in RSS field of Rx wb descriptor
1373 	 *  Initialize the drop queue
1374 	 *  Move the flexible bytes to use the ethertype - shift 6 words
1375 	 *  Set the maximum length per hash bucket to 0xA filters
1376 	 *  Send interrupt when 64 (0x4 * 16) filters are left
1377 	 */
1378 	fdirctrl |= IXGBE_FDIRCTRL_PERFECT_MATCH |
1379 		    IXGBE_FDIRCTRL_REPORT_STATUS |
1380 		    (IXGBE_FDIR_DROP_QUEUE << IXGBE_FDIRCTRL_DROP_Q_SHIFT) |
1381 		    (0x6 << IXGBE_FDIRCTRL_FLEX_SHIFT) |
1382 		    (0xA << IXGBE_FDIRCTRL_MAX_LENGTH_SHIFT) |
1383 		    (4 << IXGBE_FDIRCTRL_FULL_THRESH_SHIFT);
1384 
1385 	if (cloud_mode)
1386 		fdirctrl |=(IXGBE_FDIRCTRL_FILTERMODE_CLOUD <<
1387 					IXGBE_FDIRCTRL_FILTERMODE_SHIFT);
1388 
1389 	/* write hashes and fdirctrl register, poll for completion */
1390 	ixgbe_fdir_enable_82599(hw, fdirctrl);
1391 
1392 	return IXGBE_SUCCESS;
1393 }
1394 
1395 /*
1396  * These defines allow us to quickly generate all of the necessary instructions
1397  * in the function below by simply calling out IXGBE_COMPUTE_SIG_HASH_ITERATION
1398  * for values 0 through 15
1399  */
1400 #define IXGBE_ATR_COMMON_HASH_KEY \
1401 		(IXGBE_ATR_BUCKET_HASH_KEY & IXGBE_ATR_SIGNATURE_HASH_KEY)
1402 #define IXGBE_COMPUTE_SIG_HASH_ITERATION(_n) \
1403 do { \
1404 	u32 n = (_n); \
1405 	if (IXGBE_ATR_COMMON_HASH_KEY & (0x01 << n)) \
1406 		common_hash ^= lo_hash_dword >> n; \
1407 	else if (IXGBE_ATR_BUCKET_HASH_KEY & (0x01 << n)) \
1408 		bucket_hash ^= lo_hash_dword >> n; \
1409 	else if (IXGBE_ATR_SIGNATURE_HASH_KEY & (0x01 << n)) \
1410 		sig_hash ^= lo_hash_dword << (16 - n); \
1411 	if (IXGBE_ATR_COMMON_HASH_KEY & (0x01 << (n + 16))) \
1412 		common_hash ^= hi_hash_dword >> n; \
1413 	else if (IXGBE_ATR_BUCKET_HASH_KEY & (0x01 << (n + 16))) \
1414 		bucket_hash ^= hi_hash_dword >> n; \
1415 	else if (IXGBE_ATR_SIGNATURE_HASH_KEY & (0x01 << (n + 16))) \
1416 		sig_hash ^= hi_hash_dword << (16 - n); \
1417 } while (0)
1418 
1419 /**
1420  *  ixgbe_atr_compute_sig_hash_82599 - Compute the signature hash
1421  *  @stream: input bitstream to compute the hash on
1422  *
1423  *  This function is almost identical to the function above but contains
1424  *  several optimizations such as unwinding all of the loops, letting the
1425  *  compiler work out all of the conditional ifs since the keys are static
1426  *  defines, and computing two keys at once since the hashed dword stream
1427  *  will be the same for both keys.
1428  **/
1429 u32 ixgbe_atr_compute_sig_hash_82599(union ixgbe_atr_hash_dword input,
1430 				     union ixgbe_atr_hash_dword common)
1431 {
1432 	u32 hi_hash_dword, lo_hash_dword, flow_vm_vlan;
1433 	u32 sig_hash = 0, bucket_hash = 0, common_hash = 0;
1434 
1435 	/* record the flow_vm_vlan bits as they are a key part to the hash */
1436 	flow_vm_vlan = IXGBE_NTOHL(input.dword);
1437 
1438 	/* generate common hash dword */
1439 	hi_hash_dword = IXGBE_NTOHL(common.dword);
1440 
1441 	/* low dword is word swapped version of common */
1442 	lo_hash_dword = (hi_hash_dword >> 16) | (hi_hash_dword << 16);
1443 
1444 	/* apply flow ID/VM pool/VLAN ID bits to hash words */
1445 	hi_hash_dword ^= flow_vm_vlan ^ (flow_vm_vlan >> 16);
1446 
1447 	/* Process bits 0 and 16 */
1448 	IXGBE_COMPUTE_SIG_HASH_ITERATION(0);
1449 
1450 	/*
1451 	 * apply flow ID/VM pool/VLAN ID bits to lo hash dword, we had to
1452 	 * delay this because bit 0 of the stream should not be processed
1453 	 * so we do not add the VLAN until after bit 0 was processed
1454 	 */
1455 	lo_hash_dword ^= flow_vm_vlan ^ (flow_vm_vlan << 16);
1456 
1457 	/* Process remaining 30 bit of the key */
1458 	IXGBE_COMPUTE_SIG_HASH_ITERATION(1);
1459 	IXGBE_COMPUTE_SIG_HASH_ITERATION(2);
1460 	IXGBE_COMPUTE_SIG_HASH_ITERATION(3);
1461 	IXGBE_COMPUTE_SIG_HASH_ITERATION(4);
1462 	IXGBE_COMPUTE_SIG_HASH_ITERATION(5);
1463 	IXGBE_COMPUTE_SIG_HASH_ITERATION(6);
1464 	IXGBE_COMPUTE_SIG_HASH_ITERATION(7);
1465 	IXGBE_COMPUTE_SIG_HASH_ITERATION(8);
1466 	IXGBE_COMPUTE_SIG_HASH_ITERATION(9);
1467 	IXGBE_COMPUTE_SIG_HASH_ITERATION(10);
1468 	IXGBE_COMPUTE_SIG_HASH_ITERATION(11);
1469 	IXGBE_COMPUTE_SIG_HASH_ITERATION(12);
1470 	IXGBE_COMPUTE_SIG_HASH_ITERATION(13);
1471 	IXGBE_COMPUTE_SIG_HASH_ITERATION(14);
1472 	IXGBE_COMPUTE_SIG_HASH_ITERATION(15);
1473 
1474 	/* combine common_hash result with signature and bucket hashes */
1475 	bucket_hash ^= common_hash;
1476 	bucket_hash &= IXGBE_ATR_HASH_MASK;
1477 
1478 	sig_hash ^= common_hash << 16;
1479 	sig_hash &= IXGBE_ATR_HASH_MASK << 16;
1480 
1481 	/* return completed signature hash */
1482 	return sig_hash ^ bucket_hash;
1483 }
1484 
1485 /**
1486  *  ixgbe_atr_add_signature_filter_82599 - Adds a signature hash filter
1487  *  @hw: pointer to hardware structure
1488  *  @input: unique input dword
1489  *  @common: compressed common input dword
1490  *  @queue: queue index to direct traffic to
1491  *
1492  * Note that the tunnel bit in input must not be set when the hardware
1493  * tunneling support does not exist.
1494  **/
1495 s32 ixgbe_fdir_add_signature_filter_82599(struct ixgbe_hw *hw,
1496 					  union ixgbe_atr_hash_dword input,
1497 					  union ixgbe_atr_hash_dword common,
1498 					  u8 queue)
1499 {
1500 	u64 fdirhashcmd;
1501 	u8 flow_type;
1502 	bool tunnel;
1503 	u32 fdircmd;
1504 	s32 err;
1505 
1506 	DEBUGFUNC("ixgbe_fdir_add_signature_filter_82599");
1507 
1508 	/*
1509 	 * Get the flow_type in order to program FDIRCMD properly
1510 	 * lowest 2 bits are FDIRCMD.L4TYPE, third lowest bit is FDIRCMD.IPV6
1511 	 * fifth is FDIRCMD.TUNNEL_FILTER
1512 	 */
1513 	tunnel = !!(input.formatted.flow_type & IXGBE_ATR_L4TYPE_TUNNEL_MASK);
1514 	flow_type = input.formatted.flow_type &
1515 		    (IXGBE_ATR_L4TYPE_TUNNEL_MASK - 1);
1516 	switch (flow_type) {
1517 	case IXGBE_ATR_FLOW_TYPE_TCPV4:
1518 	case IXGBE_ATR_FLOW_TYPE_UDPV4:
1519 	case IXGBE_ATR_FLOW_TYPE_SCTPV4:
1520 	case IXGBE_ATR_FLOW_TYPE_TCPV6:
1521 	case IXGBE_ATR_FLOW_TYPE_UDPV6:
1522 	case IXGBE_ATR_FLOW_TYPE_SCTPV6:
1523 		break;
1524 	default:
1525 		DEBUGOUT(" Error on flow type input\n");
1526 		return IXGBE_ERR_CONFIG;
1527 	}
1528 
1529 	/* configure FDIRCMD register */
1530 	fdircmd = IXGBE_FDIRCMD_CMD_ADD_FLOW | IXGBE_FDIRCMD_FILTER_UPDATE |
1531 		  IXGBE_FDIRCMD_LAST | IXGBE_FDIRCMD_QUEUE_EN;
1532 	fdircmd |= (u32)flow_type << IXGBE_FDIRCMD_FLOW_TYPE_SHIFT;
1533 	fdircmd |= (u32)queue << IXGBE_FDIRCMD_RX_QUEUE_SHIFT;
1534 	if (tunnel)
1535 		fdircmd |= IXGBE_FDIRCMD_TUNNEL_FILTER;
1536 
1537 	/*
1538 	 * The lower 32-bits of fdirhashcmd is for FDIRHASH, the upper 32-bits
1539 	 * is for FDIRCMD.  Then do a 64-bit register write from FDIRHASH.
1540 	 */
1541 	fdirhashcmd = (u64)fdircmd << 32;
1542 	fdirhashcmd |= ixgbe_atr_compute_sig_hash_82599(input, common);
1543 	IXGBE_WRITE_REG64(hw, IXGBE_FDIRHASH, fdirhashcmd);
1544 
1545 	err = ixgbe_fdir_check_cmd_complete(hw, &fdircmd);
1546 	if (err) {
1547 		DEBUGOUT("Flow Director command did not complete!\n");
1548 		return err;
1549 	}
1550 
1551 	DEBUGOUT2("Tx Queue=%x hash=%x\n", queue, (u32)fdirhashcmd);
1552 
1553 	return IXGBE_SUCCESS;
1554 }
1555 
1556 #define IXGBE_COMPUTE_BKT_HASH_ITERATION(_n) \
1557 do { \
1558 	u32 n = (_n); \
1559 	if (IXGBE_ATR_BUCKET_HASH_KEY & (0x01 << n)) \
1560 		bucket_hash ^= lo_hash_dword >> n; \
1561 	if (IXGBE_ATR_BUCKET_HASH_KEY & (0x01 << (n + 16))) \
1562 		bucket_hash ^= hi_hash_dword >> n; \
1563 } while (0)
1564 
1565 /**
1566  *  ixgbe_atr_compute_perfect_hash_82599 - Compute the perfect filter hash
1567  *  @atr_input: input bitstream to compute the hash on
1568  *  @input_mask: mask for the input bitstream
1569  *
1570  *  This function serves two main purposes.  First it applies the input_mask
1571  *  to the atr_input resulting in a cleaned up atr_input data stream.
1572  *  Secondly it computes the hash and stores it in the bkt_hash field at
1573  *  the end of the input byte stream.  This way it will be available for
1574  *  future use without needing to recompute the hash.
1575  **/
1576 void ixgbe_atr_compute_perfect_hash_82599(union ixgbe_atr_input *input,
1577 					  union ixgbe_atr_input *input_mask)
1578 {
1579 
1580 	u32 hi_hash_dword, lo_hash_dword, flow_vm_vlan;
1581 	u32 bucket_hash = 0;
1582 	u32 hi_dword = 0;
1583 	u32 i = 0;
1584 
1585 	/* Apply masks to input data */
1586 	for (i = 0; i < 14; i++)
1587 		input->dword_stream[i]  &= input_mask->dword_stream[i];
1588 
1589 	/* record the flow_vm_vlan bits as they are a key part to the hash */
1590 	flow_vm_vlan = IXGBE_NTOHL(input->dword_stream[0]);
1591 
1592 	/* generate common hash dword */
1593 	for (i = 1; i <= 13; i++)
1594 		hi_dword ^= input->dword_stream[i];
1595 	hi_hash_dword = IXGBE_NTOHL(hi_dword);
1596 
1597 	/* low dword is word swapped version of common */
1598 	lo_hash_dword = (hi_hash_dword >> 16) | (hi_hash_dword << 16);
1599 
1600 	/* apply flow ID/VM pool/VLAN ID bits to hash words */
1601 	hi_hash_dword ^= flow_vm_vlan ^ (flow_vm_vlan >> 16);
1602 
1603 	/* Process bits 0 and 16 */
1604 	IXGBE_COMPUTE_BKT_HASH_ITERATION(0);
1605 
1606 	/*
1607 	 * apply flow ID/VM pool/VLAN ID bits to lo hash dword, we had to
1608 	 * delay this because bit 0 of the stream should not be processed
1609 	 * so we do not add the VLAN until after bit 0 was processed
1610 	 */
1611 	lo_hash_dword ^= flow_vm_vlan ^ (flow_vm_vlan << 16);
1612 
1613 	/* Process remaining 30 bit of the key */
1614 	for (i = 1; i <= 15; i++)
1615 		IXGBE_COMPUTE_BKT_HASH_ITERATION(i);
1616 
1617 	/*
1618 	 * Limit hash to 13 bits since max bucket count is 8K.
1619 	 * Store result at the end of the input stream.
1620 	 */
1621 	input->formatted.bkt_hash = bucket_hash & 0x1FFF;
1622 }
1623 
1624 /**
1625  *  ixgbe_get_fdirtcpm_82599 - generate a TCP port from atr_input_masks
1626  *  @input_mask: mask to be bit swapped
1627  *
1628  *  The source and destination port masks for flow director are bit swapped
1629  *  in that bit 15 effects bit 0, 14 effects 1, 13, 2 etc.  In order to
1630  *  generate a correctly swapped value we need to bit swap the mask and that
1631  *  is what is accomplished by this function.
1632  **/
1633 static u32 ixgbe_get_fdirtcpm_82599(union ixgbe_atr_input *input_mask)
1634 {
1635 	u32 mask = IXGBE_NTOHS(input_mask->formatted.dst_port);
1636 	mask <<= IXGBE_FDIRTCPM_DPORTM_SHIFT;
1637 	mask |= IXGBE_NTOHS(input_mask->formatted.src_port);
1638 	mask = ((mask & 0x55555555) << 1) | ((mask & 0xAAAAAAAA) >> 1);
1639 	mask = ((mask & 0x33333333) << 2) | ((mask & 0xCCCCCCCC) >> 2);
1640 	mask = ((mask & 0x0F0F0F0F) << 4) | ((mask & 0xF0F0F0F0) >> 4);
1641 	return ((mask & 0x00FF00FF) << 8) | ((mask & 0xFF00FF00) >> 8);
1642 }
1643 
1644 /*
1645  * These two macros are meant to address the fact that we have registers
1646  * that are either all or in part big-endian.  As a result on big-endian
1647  * systems we will end up byte swapping the value to little-endian before
1648  * it is byte swapped again and written to the hardware in the original
1649  * big-endian format.
1650  */
1651 #define IXGBE_STORE_AS_BE32(_value) \
1652 	(((u32)(_value) >> 24) | (((u32)(_value) & 0x00FF0000) >> 8) | \
1653 	 (((u32)(_value) & 0x0000FF00) << 8) | ((u32)(_value) << 24))
1654 
1655 #define IXGBE_WRITE_REG_BE32(a, reg, value) \
1656 	IXGBE_WRITE_REG((a), (reg), IXGBE_STORE_AS_BE32(IXGBE_NTOHL(value)))
1657 
1658 #define IXGBE_STORE_AS_BE16(_value) \
1659 	IXGBE_NTOHS(((u16)(_value) >> 8) | ((u16)(_value) << 8))
1660 
1661 s32 ixgbe_fdir_set_input_mask_82599(struct ixgbe_hw *hw,
1662 				    union ixgbe_atr_input *input_mask, bool cloud_mode)
1663 {
1664 	/* mask IPv6 since it is currently not supported */
1665 	u32 fdirm = IXGBE_FDIRM_DIPv6;
1666 	u32 fdirtcpm;
1667 	u32 fdirip6m;
1668 	DEBUGFUNC("ixgbe_fdir_set_atr_input_mask_82599");
1669 
1670 	/*
1671 	 * Program the relevant mask registers.  If src/dst_port or src/dst_addr
1672 	 * are zero, then assume a full mask for that field.  Also assume that
1673 	 * a VLAN of 0 is unspecified, so mask that out as well.  L4type
1674 	 * cannot be masked out in this implementation.
1675 	 *
1676 	 * This also assumes IPv4 only.  IPv6 masking isn't supported at this
1677 	 * point in time.
1678 	 */
1679 
1680 	/* verify bucket hash is cleared on hash generation */
1681 	if (input_mask->formatted.bkt_hash)
1682 		DEBUGOUT(" bucket hash should always be 0 in mask\n");
1683 
1684 	/* Program FDIRM and verify partial masks */
1685 	switch (input_mask->formatted.vm_pool & 0x7F) {
1686 	case 0x0:
1687 		fdirm |= IXGBE_FDIRM_POOL;
1688 	case 0x7F:
1689 		break;
1690 	default:
1691 		DEBUGOUT(" Error on vm pool mask\n");
1692 		return IXGBE_ERR_CONFIG;
1693 	}
1694 
1695 	switch (input_mask->formatted.flow_type & IXGBE_ATR_L4TYPE_MASK) {
1696 	case 0x0:
1697 		fdirm |= IXGBE_FDIRM_L4P;
1698 		if (input_mask->formatted.dst_port ||
1699 		    input_mask->formatted.src_port) {
1700 			DEBUGOUT(" Error on src/dst port mask\n");
1701 			return IXGBE_ERR_CONFIG;
1702 		}
1703 	case IXGBE_ATR_L4TYPE_MASK:
1704 		break;
1705 	default:
1706 		DEBUGOUT(" Error on flow type mask\n");
1707 		return IXGBE_ERR_CONFIG;
1708 	}
1709 
1710 	switch (IXGBE_NTOHS(input_mask->formatted.vlan_id) & 0xEFFF) {
1711 	case 0x0000:
1712 		/* mask VLAN ID, fall through to mask VLAN priority */
1713 		fdirm |= IXGBE_FDIRM_VLANID;
1714 	case 0x0FFF:
1715 		/* mask VLAN priority */
1716 		fdirm |= IXGBE_FDIRM_VLANP;
1717 		break;
1718 	case 0xE000:
1719 		/* mask VLAN ID only, fall through */
1720 		fdirm |= IXGBE_FDIRM_VLANID;
1721 	case 0xEFFF:
1722 		/* no VLAN fields masked */
1723 		break;
1724 	default:
1725 		DEBUGOUT(" Error on VLAN mask\n");
1726 		return IXGBE_ERR_CONFIG;
1727 	}
1728 
1729 	switch (input_mask->formatted.flex_bytes & 0xFFFF) {
1730 	case 0x0000:
1731 		/* Mask Flex Bytes, fall through */
1732 		fdirm |= IXGBE_FDIRM_FLEX;
1733 	case 0xFFFF:
1734 		break;
1735 	default:
1736 		DEBUGOUT(" Error on flexible byte mask\n");
1737 		return IXGBE_ERR_CONFIG;
1738 	}
1739 
1740 	if (cloud_mode) {
1741 		fdirm |= IXGBE_FDIRM_L3P;
1742 		fdirip6m = ((u32) 0xFFFFU << IXGBE_FDIRIP6M_DIPM_SHIFT);
1743 		fdirip6m |= IXGBE_FDIRIP6M_ALWAYS_MASK;
1744 
1745 		switch (input_mask->formatted.inner_mac[0] & 0xFF) {
1746 		case 0x00:
1747 			/* Mask inner MAC, fall through */
1748 			fdirip6m |= IXGBE_FDIRIP6M_INNER_MAC;
1749 		case 0xFF:
1750 			break;
1751 		default:
1752 			DEBUGOUT(" Error on inner_mac byte mask\n");
1753 			return IXGBE_ERR_CONFIG;
1754 		}
1755 
1756 		switch (input_mask->formatted.tni_vni & 0xFFFFFFFF) {
1757 		case 0x0:
1758 			/* Mask vxlan id */
1759 			fdirip6m |= IXGBE_FDIRIP6M_TNI_VNI;
1760 			break;
1761 		case 0x00FFFFFF:
1762 			fdirip6m |= IXGBE_FDIRIP6M_TNI_VNI_24;
1763 			break;
1764 		case 0xFFFFFFFF:
1765 			break;
1766 		default:
1767 			DEBUGOUT(" Error on TNI/VNI byte mask\n");
1768 			return IXGBE_ERR_CONFIG;
1769 		}
1770 
1771 		switch (input_mask->formatted.tunnel_type & 0xFFFF) {
1772 		case 0x0:
1773 			/* Mask turnnel type, fall through */
1774 			fdirip6m |= IXGBE_FDIRIP6M_TUNNEL_TYPE;
1775 		case 0xFFFF:
1776 			break;
1777 		default:
1778 			DEBUGOUT(" Error on tunnel type byte mask\n");
1779 			return IXGBE_ERR_CONFIG;
1780 		}
1781 		IXGBE_WRITE_REG_BE32(hw, IXGBE_FDIRIP6M, fdirip6m);
1782 
1783 		/* Set all bits in FDIRTCPM, FDIRUDPM, FDIRSIP4M and
1784 		 * FDIRDIP4M in cloud mode to allow L3/L3 packets to
1785 		 * tunnel.
1786 		 */
1787 		IXGBE_WRITE_REG(hw, IXGBE_FDIRTCPM, 0xFFFFFFFF);
1788 		IXGBE_WRITE_REG(hw, IXGBE_FDIRUDPM, 0xFFFFFFFF);
1789 		IXGBE_WRITE_REG_BE32(hw, IXGBE_FDIRDIP4M, 0xFFFFFFFF);
1790 		IXGBE_WRITE_REG_BE32(hw, IXGBE_FDIRSIP4M, 0xFFFFFFFF);
1791 	}
1792 
1793 	/* Now mask VM pool and destination IPv6 - bits 5 and 2 */
1794 	IXGBE_WRITE_REG(hw, IXGBE_FDIRM, fdirm);
1795 
1796 	if (!cloud_mode) {
1797 		/* store the TCP/UDP port masks, bit reversed from port
1798 		 * layout */
1799 		fdirtcpm = ixgbe_get_fdirtcpm_82599(input_mask);
1800 
1801 		/* write both the same so that UDP and TCP use the same mask */
1802 		IXGBE_WRITE_REG(hw, IXGBE_FDIRTCPM, ~fdirtcpm);
1803 		IXGBE_WRITE_REG(hw, IXGBE_FDIRUDPM, ~fdirtcpm);
1804 		/* also use it for SCTP */
1805 		switch (hw->mac.type) {
1806 		case ixgbe_mac_X550:
1807 		case ixgbe_mac_X550EM_x:
1808 			IXGBE_WRITE_REG(hw, IXGBE_FDIRSCTPM, ~fdirtcpm);
1809 			break;
1810 		default:
1811 			break;
1812 		}
1813 
1814 		/* store source and destination IP masks (big-enian) */
1815 		IXGBE_WRITE_REG_BE32(hw, IXGBE_FDIRSIP4M,
1816 				     ~input_mask->formatted.src_ip[0]);
1817 		IXGBE_WRITE_REG_BE32(hw, IXGBE_FDIRDIP4M,
1818 				     ~input_mask->formatted.dst_ip[0]);
1819 	}
1820 	return IXGBE_SUCCESS;
1821 }
1822 
1823 s32 ixgbe_fdir_write_perfect_filter_82599(struct ixgbe_hw *hw,
1824 					  union ixgbe_atr_input *input,
1825 					  u16 soft_id, u8 queue, bool cloud_mode)
1826 {
1827 	u32 fdirport, fdirvlan, fdirhash, fdircmd;
1828 	u32 addr_low, addr_high;
1829 	u32 cloud_type = 0;
1830 	s32 err;
1831 
1832 	DEBUGFUNC("ixgbe_fdir_write_perfect_filter_82599");
1833 	if (!cloud_mode) {
1834 		/* currently IPv6 is not supported, must be programmed with 0 */
1835 		IXGBE_WRITE_REG_BE32(hw, IXGBE_FDIRSIPv6(0),
1836 				     input->formatted.src_ip[0]);
1837 		IXGBE_WRITE_REG_BE32(hw, IXGBE_FDIRSIPv6(1),
1838 				     input->formatted.src_ip[1]);
1839 		IXGBE_WRITE_REG_BE32(hw, IXGBE_FDIRSIPv6(2),
1840 				     input->formatted.src_ip[2]);
1841 
1842 		/* record the source address (big-endian) */
1843 		IXGBE_WRITE_REG_BE32(hw, IXGBE_FDIRIPSA,
1844 			input->formatted.src_ip[0]);
1845 
1846 		/* record the first 32 bits of the destination address
1847 		 * (big-endian) */
1848 		IXGBE_WRITE_REG_BE32(hw, IXGBE_FDIRIPDA,
1849 			input->formatted.dst_ip[0]);
1850 
1851 		/* record source and destination port (little-endian)*/
1852 		fdirport = IXGBE_NTOHS(input->formatted.dst_port);
1853 		fdirport <<= IXGBE_FDIRPORT_DESTINATION_SHIFT;
1854 		fdirport |= IXGBE_NTOHS(input->formatted.src_port);
1855 		IXGBE_WRITE_REG(hw, IXGBE_FDIRPORT, fdirport);
1856 	}
1857 
1858 	/* record VLAN (little-endian) and flex_bytes(big-endian) */
1859 	fdirvlan = IXGBE_STORE_AS_BE16(input->formatted.flex_bytes);
1860 	fdirvlan <<= IXGBE_FDIRVLAN_FLEX_SHIFT;
1861 	fdirvlan |= IXGBE_NTOHS(input->formatted.vlan_id);
1862 	IXGBE_WRITE_REG(hw, IXGBE_FDIRVLAN, fdirvlan);
1863 
1864 	if (cloud_mode) {
1865 		if (input->formatted.tunnel_type != 0)
1866 			cloud_type = 0x80000000;
1867 
1868 		addr_low = ((u32)input->formatted.inner_mac[0] |
1869 				((u32)input->formatted.inner_mac[1] << 8) |
1870 				((u32)input->formatted.inner_mac[2] << 16) |
1871 				((u32)input->formatted.inner_mac[3] << 24));
1872 		addr_high = ((u32)input->formatted.inner_mac[4] |
1873 				((u32)input->formatted.inner_mac[5] << 8));
1874 		cloud_type |= addr_high;
1875 		IXGBE_WRITE_REG_BE32(hw, IXGBE_FDIRSIPv6(0), addr_low);
1876 		IXGBE_WRITE_REG_BE32(hw, IXGBE_FDIRSIPv6(1), cloud_type);
1877 		IXGBE_WRITE_REG_BE32(hw, IXGBE_FDIRSIPv6(2), input->formatted.tni_vni);
1878 	}
1879 
1880 	/* configure FDIRHASH register */
1881 	fdirhash = input->formatted.bkt_hash;
1882 	fdirhash |= soft_id << IXGBE_FDIRHASH_SIG_SW_INDEX_SHIFT;
1883 	IXGBE_WRITE_REG(hw, IXGBE_FDIRHASH, fdirhash);
1884 
1885 	/*
1886 	 * flush all previous writes to make certain registers are
1887 	 * programmed prior to issuing the command
1888 	 */
1889 	IXGBE_WRITE_FLUSH(hw);
1890 
1891 	/* configure FDIRCMD register */
1892 	fdircmd = IXGBE_FDIRCMD_CMD_ADD_FLOW | IXGBE_FDIRCMD_FILTER_UPDATE |
1893 		  IXGBE_FDIRCMD_LAST | IXGBE_FDIRCMD_QUEUE_EN;
1894 	if (queue == IXGBE_FDIR_DROP_QUEUE)
1895 		fdircmd |= IXGBE_FDIRCMD_DROP;
1896 	if (input->formatted.flow_type & IXGBE_ATR_L4TYPE_TUNNEL_MASK)
1897 		fdircmd |= IXGBE_FDIRCMD_TUNNEL_FILTER;
1898 	fdircmd |= input->formatted.flow_type << IXGBE_FDIRCMD_FLOW_TYPE_SHIFT;
1899 	fdircmd |= (u32)queue << IXGBE_FDIRCMD_RX_QUEUE_SHIFT;
1900 	fdircmd |= (u32)input->formatted.vm_pool << IXGBE_FDIRCMD_VT_POOL_SHIFT;
1901 
1902 	IXGBE_WRITE_REG(hw, IXGBE_FDIRCMD, fdircmd);
1903 	err = ixgbe_fdir_check_cmd_complete(hw, &fdircmd);
1904 	if (err) {
1905 		DEBUGOUT("Flow Director command did not complete!\n");
1906 		return err;
1907 	}
1908 
1909 	return IXGBE_SUCCESS;
1910 }
1911 
1912 s32 ixgbe_fdir_erase_perfect_filter_82599(struct ixgbe_hw *hw,
1913 					  union ixgbe_atr_input *input,
1914 					  u16 soft_id)
1915 {
1916 	u32 fdirhash;
1917 	u32 fdircmd;
1918 	s32 err;
1919 
1920 	/* configure FDIRHASH register */
1921 	fdirhash = input->formatted.bkt_hash;
1922 	fdirhash |= soft_id << IXGBE_FDIRHASH_SIG_SW_INDEX_SHIFT;
1923 	IXGBE_WRITE_REG(hw, IXGBE_FDIRHASH, fdirhash);
1924 
1925 	/* flush hash to HW */
1926 	IXGBE_WRITE_FLUSH(hw);
1927 
1928 	/* Query if filter is present */
1929 	IXGBE_WRITE_REG(hw, IXGBE_FDIRCMD, IXGBE_FDIRCMD_CMD_QUERY_REM_FILT);
1930 
1931 	err = ixgbe_fdir_check_cmd_complete(hw, &fdircmd);
1932 	if (err) {
1933 		DEBUGOUT("Flow Director command did not complete!\n");
1934 		return err;
1935 	}
1936 
1937 	/* if filter exists in hardware then remove it */
1938 	if (fdircmd & IXGBE_FDIRCMD_FILTER_VALID) {
1939 		IXGBE_WRITE_REG(hw, IXGBE_FDIRHASH, fdirhash);
1940 		IXGBE_WRITE_FLUSH(hw);
1941 		IXGBE_WRITE_REG(hw, IXGBE_FDIRCMD,
1942 				IXGBE_FDIRCMD_CMD_REMOVE_FLOW);
1943 	}
1944 
1945 	return IXGBE_SUCCESS;
1946 }
1947 
1948 /**
1949  *  ixgbe_fdir_add_perfect_filter_82599 - Adds a perfect filter
1950  *  @hw: pointer to hardware structure
1951  *  @input: input bitstream
1952  *  @input_mask: mask for the input bitstream
1953  *  @soft_id: software index for the filters
1954  *  @queue: queue index to direct traffic to
1955  *
1956  *  Note that the caller to this function must lock before calling, since the
1957  *  hardware writes must be protected from one another.
1958  **/
1959 s32 ixgbe_fdir_add_perfect_filter_82599(struct ixgbe_hw *hw,
1960 					union ixgbe_atr_input *input,
1961 					union ixgbe_atr_input *input_mask,
1962 					u16 soft_id, u8 queue, bool cloud_mode)
1963 {
1964 	s32 err = IXGBE_ERR_CONFIG;
1965 
1966 	DEBUGFUNC("ixgbe_fdir_add_perfect_filter_82599");
1967 
1968 	/*
1969 	 * Check flow_type formatting, and bail out before we touch the hardware
1970 	 * if there's a configuration issue
1971 	 */
1972 	switch (input->formatted.flow_type) {
1973 	case IXGBE_ATR_FLOW_TYPE_IPV4:
1974 	case IXGBE_ATR_FLOW_TYPE_TUNNELED_IPV4:
1975 		input_mask->formatted.flow_type = IXGBE_ATR_L4TYPE_IPV6_MASK;
1976 		if (input->formatted.dst_port || input->formatted.src_port) {
1977 			DEBUGOUT(" Error on src/dst port\n");
1978 			return IXGBE_ERR_CONFIG;
1979 		}
1980 		break;
1981 	case IXGBE_ATR_FLOW_TYPE_SCTPV4:
1982 	case IXGBE_ATR_FLOW_TYPE_TUNNELED_SCTPV4:
1983 		if (input->formatted.dst_port || input->formatted.src_port) {
1984 			DEBUGOUT(" Error on src/dst port\n");
1985 			return IXGBE_ERR_CONFIG;
1986 		}
1987 	case IXGBE_ATR_FLOW_TYPE_TCPV4:
1988 	case IXGBE_ATR_FLOW_TYPE_TUNNELED_TCPV4:
1989 	case IXGBE_ATR_FLOW_TYPE_UDPV4:
1990 	case IXGBE_ATR_FLOW_TYPE_TUNNELED_UDPV4:
1991 		input_mask->formatted.flow_type = IXGBE_ATR_L4TYPE_IPV6_MASK |
1992 						  IXGBE_ATR_L4TYPE_MASK;
1993 		break;
1994 	default:
1995 		DEBUGOUT(" Error on flow type input\n");
1996 		return err;
1997 	}
1998 
1999 	/* program input mask into the HW */
2000 	err = ixgbe_fdir_set_input_mask_82599(hw, input_mask, cloud_mode);
2001 	if (err)
2002 		return err;
2003 
2004 	/* apply mask and compute/store hash */
2005 	ixgbe_atr_compute_perfect_hash_82599(input, input_mask);
2006 
2007 	/* program filters to filter memory */
2008 	return ixgbe_fdir_write_perfect_filter_82599(hw, input,
2009 						     soft_id, queue, cloud_mode);
2010 }
2011 
2012 /**
2013  *  ixgbe_read_analog_reg8_82599 - Reads 8 bit Omer analog register
2014  *  @hw: pointer to hardware structure
2015  *  @reg: analog register to read
2016  *  @val: read value
2017  *
2018  *  Performs read operation to Omer analog register specified.
2019  **/
2020 s32 ixgbe_read_analog_reg8_82599(struct ixgbe_hw *hw, u32 reg, u8 *val)
2021 {
2022 	u32  core_ctl;
2023 
2024 	DEBUGFUNC("ixgbe_read_analog_reg8_82599");
2025 
2026 	IXGBE_WRITE_REG(hw, IXGBE_CORECTL, IXGBE_CORECTL_WRITE_CMD |
2027 			(reg << 8));
2028 	IXGBE_WRITE_FLUSH(hw);
2029 	usec_delay(10);
2030 	core_ctl = IXGBE_READ_REG(hw, IXGBE_CORECTL);
2031 	*val = (u8)core_ctl;
2032 
2033 	return IXGBE_SUCCESS;
2034 }
2035 
2036 /**
2037  *  ixgbe_write_analog_reg8_82599 - Writes 8 bit Omer analog register
2038  *  @hw: pointer to hardware structure
2039  *  @reg: atlas register to write
2040  *  @val: value to write
2041  *
2042  *  Performs write operation to Omer analog register specified.
2043  **/
2044 s32 ixgbe_write_analog_reg8_82599(struct ixgbe_hw *hw, u32 reg, u8 val)
2045 {
2046 	u32  core_ctl;
2047 
2048 	DEBUGFUNC("ixgbe_write_analog_reg8_82599");
2049 
2050 	core_ctl = (reg << 8) | val;
2051 	IXGBE_WRITE_REG(hw, IXGBE_CORECTL, core_ctl);
2052 	IXGBE_WRITE_FLUSH(hw);
2053 	usec_delay(10);
2054 
2055 	return IXGBE_SUCCESS;
2056 }
2057 
2058 /**
2059  *  ixgbe_start_hw_82599 - Prepare hardware for Tx/Rx
2060  *  @hw: pointer to hardware structure
2061  *
2062  *  Starts the hardware using the generic start_hw function
2063  *  and the generation start_hw function.
2064  *  Then performs revision-specific operations, if any.
2065  **/
2066 s32 ixgbe_start_hw_82599(struct ixgbe_hw *hw)
2067 {
2068 	s32 ret_val = IXGBE_SUCCESS;
2069 
2070 	DEBUGFUNC("ixgbe_start_hw_82599");
2071 
2072 	ret_val = ixgbe_start_hw_generic(hw);
2073 	if (ret_val != IXGBE_SUCCESS)
2074 		goto out;
2075 
2076 	ret_val = ixgbe_start_hw_gen2(hw);
2077 	if (ret_val != IXGBE_SUCCESS)
2078 		goto out;
2079 
2080 	/* We need to run link autotry after the driver loads */
2081 	hw->mac.autotry_restart = TRUE;
2082 
2083 	if (ret_val == IXGBE_SUCCESS)
2084 		ret_val = ixgbe_verify_fw_version_82599(hw);
2085 out:
2086 	return ret_val;
2087 }
2088 
2089 /**
2090  *  ixgbe_identify_phy_82599 - Get physical layer module
2091  *  @hw: pointer to hardware structure
2092  *
2093  *  Determines the physical layer module found on the current adapter.
2094  *  If PHY already detected, maintains current PHY type in hw struct,
2095  *  otherwise executes the PHY detection routine.
2096  **/
2097 s32 ixgbe_identify_phy_82599(struct ixgbe_hw *hw)
2098 {
2099 	s32 status;
2100 
2101 	DEBUGFUNC("ixgbe_identify_phy_82599");
2102 
2103 	/* Detect PHY if not unknown - returns success if already detected. */
2104 	status = ixgbe_identify_phy_generic(hw);
2105 	if (status != IXGBE_SUCCESS) {
2106 		/* 82599 10GBASE-T requires an external PHY */
2107 		if (hw->mac.ops.get_media_type(hw) == ixgbe_media_type_copper)
2108 			return status;
2109 		else
2110 			status = ixgbe_identify_module_generic(hw);
2111 	}
2112 
2113 	/* Set PHY type none if no PHY detected */
2114 	if (hw->phy.type == ixgbe_phy_unknown) {
2115 		hw->phy.type = ixgbe_phy_none;
2116 		return IXGBE_SUCCESS;
2117 	}
2118 
2119 	/* Return error if SFP module has been detected but is not supported */
2120 	if (hw->phy.type == ixgbe_phy_sfp_unsupported)
2121 		return IXGBE_ERR_SFP_NOT_SUPPORTED;
2122 
2123 	return status;
2124 }
2125 
2126 /**
2127  *  ixgbe_get_supported_physical_layer_82599 - Returns physical layer type
2128  *  @hw: pointer to hardware structure
2129  *
2130  *  Determines physical layer capabilities of the current configuration.
2131  **/
2132 u32 ixgbe_get_supported_physical_layer_82599(struct ixgbe_hw *hw)
2133 {
2134 	u32 physical_layer = IXGBE_PHYSICAL_LAYER_UNKNOWN;
2135 	u32 autoc = IXGBE_READ_REG(hw, IXGBE_AUTOC);
2136 	u32 autoc2 = IXGBE_READ_REG(hw, IXGBE_AUTOC2);
2137 	u32 pma_pmd_10g_serial = autoc2 & IXGBE_AUTOC2_10G_SERIAL_PMA_PMD_MASK;
2138 	u32 pma_pmd_10g_parallel = autoc & IXGBE_AUTOC_10G_PMA_PMD_MASK;
2139 	u32 pma_pmd_1g = autoc & IXGBE_AUTOC_1G_PMA_PMD_MASK;
2140 	u16 ext_ability = 0;
2141 
2142 	DEBUGFUNC("ixgbe_get_support_physical_layer_82599");
2143 
2144 	hw->phy.ops.identify(hw);
2145 
2146 	switch (hw->phy.type) {
2147 	case ixgbe_phy_tn:
2148 	case ixgbe_phy_cu_unknown:
2149 		hw->phy.ops.read_reg(hw, IXGBE_MDIO_PHY_EXT_ABILITY,
2150 		IXGBE_MDIO_PMA_PMD_DEV_TYPE, &ext_ability);
2151 		if (ext_ability & IXGBE_MDIO_PHY_10GBASET_ABILITY)
2152 			physical_layer |= IXGBE_PHYSICAL_LAYER_10GBASE_T;
2153 		if (ext_ability & IXGBE_MDIO_PHY_1000BASET_ABILITY)
2154 			physical_layer |= IXGBE_PHYSICAL_LAYER_1000BASE_T;
2155 		if (ext_ability & IXGBE_MDIO_PHY_100BASETX_ABILITY)
2156 			physical_layer |= IXGBE_PHYSICAL_LAYER_100BASE_TX;
2157 		goto out;
2158 	default:
2159 		break;
2160 	}
2161 
2162 	switch (autoc & IXGBE_AUTOC_LMS_MASK) {
2163 	case IXGBE_AUTOC_LMS_1G_AN:
2164 	case IXGBE_AUTOC_LMS_1G_LINK_NO_AN:
2165 		if (pma_pmd_1g == IXGBE_AUTOC_1G_KX_BX) {
2166 			physical_layer = IXGBE_PHYSICAL_LAYER_1000BASE_KX |
2167 			    IXGBE_PHYSICAL_LAYER_1000BASE_BX;
2168 			goto out;
2169 		} else
2170 			/* SFI mode so read SFP module */
2171 			goto sfp_check;
2172 		break;
2173 	case IXGBE_AUTOC_LMS_10G_LINK_NO_AN:
2174 		if (pma_pmd_10g_parallel == IXGBE_AUTOC_10G_CX4)
2175 			physical_layer = IXGBE_PHYSICAL_LAYER_10GBASE_CX4;
2176 		else if (pma_pmd_10g_parallel == IXGBE_AUTOC_10G_KX4)
2177 			physical_layer = IXGBE_PHYSICAL_LAYER_10GBASE_KX4;
2178 		else if (pma_pmd_10g_parallel == IXGBE_AUTOC_10G_XAUI)
2179 			physical_layer = IXGBE_PHYSICAL_LAYER_10GBASE_XAUI;
2180 		goto out;
2181 		break;
2182 	case IXGBE_AUTOC_LMS_10G_SERIAL:
2183 		if (pma_pmd_10g_serial == IXGBE_AUTOC2_10G_KR) {
2184 			physical_layer = IXGBE_PHYSICAL_LAYER_10GBASE_KR;
2185 			goto out;
2186 		} else if (pma_pmd_10g_serial == IXGBE_AUTOC2_10G_SFI)
2187 			goto sfp_check;
2188 		break;
2189 	case IXGBE_AUTOC_LMS_KX4_KX_KR:
2190 	case IXGBE_AUTOC_LMS_KX4_KX_KR_1G_AN:
2191 		if (autoc & IXGBE_AUTOC_KX_SUPP)
2192 			physical_layer |= IXGBE_PHYSICAL_LAYER_1000BASE_KX;
2193 		if (autoc & IXGBE_AUTOC_KX4_SUPP)
2194 			physical_layer |= IXGBE_PHYSICAL_LAYER_10GBASE_KX4;
2195 		if (autoc & IXGBE_AUTOC_KR_SUPP)
2196 			physical_layer |= IXGBE_PHYSICAL_LAYER_10GBASE_KR;
2197 		goto out;
2198 		break;
2199 	default:
2200 		goto out;
2201 		break;
2202 	}
2203 
2204 sfp_check:
2205 	/* SFP check must be done last since DA modules are sometimes used to
2206 	 * test KR mode -  we need to id KR mode correctly before SFP module.
2207 	 * Call identify_sfp because the pluggable module may have changed */
2208 	physical_layer = ixgbe_get_supported_phy_sfp_layer_generic(hw);
2209 out:
2210 	return physical_layer;
2211 }
2212 
2213 /**
2214  *  ixgbe_enable_rx_dma_82599 - Enable the Rx DMA unit on 82599
2215  *  @hw: pointer to hardware structure
2216  *  @regval: register value to write to RXCTRL
2217  *
2218  *  Enables the Rx DMA unit for 82599
2219  **/
2220 s32 ixgbe_enable_rx_dma_82599(struct ixgbe_hw *hw, u32 regval)
2221 {
2222 
2223 	DEBUGFUNC("ixgbe_enable_rx_dma_82599");
2224 
2225 	/*
2226 	 * Workaround for 82599 silicon errata when enabling the Rx datapath.
2227 	 * If traffic is incoming before we enable the Rx unit, it could hang
2228 	 * the Rx DMA unit.  Therefore, make sure the security engine is
2229 	 * completely disabled prior to enabling the Rx unit.
2230 	 */
2231 
2232 	hw->mac.ops.disable_sec_rx_path(hw);
2233 
2234 	if (regval & IXGBE_RXCTRL_RXEN)
2235 		ixgbe_enable_rx(hw);
2236 	else
2237 		ixgbe_disable_rx(hw);
2238 
2239 	hw->mac.ops.enable_sec_rx_path(hw);
2240 
2241 	return IXGBE_SUCCESS;
2242 }
2243 
2244 /**
2245  *  ixgbe_verify_fw_version_82599 - verify FW version for 82599
2246  *  @hw: pointer to hardware structure
2247  *
2248  *  Verifies that installed the firmware version is 0.6 or higher
2249  *  for SFI devices. All 82599 SFI devices should have version 0.6 or higher.
2250  *
2251  *  Returns IXGBE_ERR_EEPROM_VERSION if the FW is not present or
2252  *  if the FW version is not supported.
2253  **/
2254 static s32 ixgbe_verify_fw_version_82599(struct ixgbe_hw *hw)
2255 {
2256 	s32 status = IXGBE_ERR_EEPROM_VERSION;
2257 	u16 fw_offset, fw_ptp_cfg_offset;
2258 	u16 fw_version;
2259 
2260 	DEBUGFUNC("ixgbe_verify_fw_version_82599");
2261 
2262 	/* firmware check is only necessary for SFI devices */
2263 	if (hw->phy.media_type != ixgbe_media_type_fiber) {
2264 		status = IXGBE_SUCCESS;
2265 		goto fw_version_out;
2266 	}
2267 
2268 	/* get the offset to the Firmware Module block */
2269 	if (hw->eeprom.ops.read(hw, IXGBE_FW_PTR, &fw_offset)) {
2270 		ERROR_REPORT2(IXGBE_ERROR_INVALID_STATE,
2271 			      "eeprom read at offset %d failed", IXGBE_FW_PTR);
2272 		return IXGBE_ERR_EEPROM_VERSION;
2273 	}
2274 
2275 	if ((fw_offset == 0) || (fw_offset == 0xFFFF))
2276 		goto fw_version_out;
2277 
2278 	/* get the offset to the Pass Through Patch Configuration block */
2279 	if (hw->eeprom.ops.read(hw, (fw_offset +
2280 				 IXGBE_FW_PASSTHROUGH_PATCH_CONFIG_PTR),
2281 				 &fw_ptp_cfg_offset)) {
2282 		ERROR_REPORT2(IXGBE_ERROR_INVALID_STATE,
2283 			      "eeprom read at offset %d failed",
2284 			      fw_offset +
2285 			      IXGBE_FW_PASSTHROUGH_PATCH_CONFIG_PTR);
2286 		return IXGBE_ERR_EEPROM_VERSION;
2287 	}
2288 
2289 	if ((fw_ptp_cfg_offset == 0) || (fw_ptp_cfg_offset == 0xFFFF))
2290 		goto fw_version_out;
2291 
2292 	/* get the firmware version */
2293 	if (hw->eeprom.ops.read(hw, (fw_ptp_cfg_offset +
2294 			    IXGBE_FW_PATCH_VERSION_4), &fw_version)) {
2295 		ERROR_REPORT2(IXGBE_ERROR_INVALID_STATE,
2296 			      "eeprom read at offset %d failed",
2297 			      fw_ptp_cfg_offset + IXGBE_FW_PATCH_VERSION_4);
2298 		return IXGBE_ERR_EEPROM_VERSION;
2299 	}
2300 
2301 	if (fw_version > 0x5)
2302 		status = IXGBE_SUCCESS;
2303 
2304 fw_version_out:
2305 	return status;
2306 }
2307 
2308 /**
2309  *  ixgbe_verify_lesm_fw_enabled_82599 - Checks LESM FW module state.
2310  *  @hw: pointer to hardware structure
2311  *
2312  *  Returns TRUE if the LESM FW module is present and enabled. Otherwise
2313  *  returns FALSE. Smart Speed must be disabled if LESM FW module is enabled.
2314  **/
2315 bool ixgbe_verify_lesm_fw_enabled_82599(struct ixgbe_hw *hw)
2316 {
2317 	bool lesm_enabled = FALSE;
2318 	u16 fw_offset, fw_lesm_param_offset, fw_lesm_state;
2319 	s32 status;
2320 
2321 	DEBUGFUNC("ixgbe_verify_lesm_fw_enabled_82599");
2322 
2323 	/* get the offset to the Firmware Module block */
2324 	status = hw->eeprom.ops.read(hw, IXGBE_FW_PTR, &fw_offset);
2325 
2326 	if ((status != IXGBE_SUCCESS) ||
2327 	    (fw_offset == 0) || (fw_offset == 0xFFFF))
2328 		goto out;
2329 
2330 	/* get the offset to the LESM Parameters block */
2331 	status = hw->eeprom.ops.read(hw, (fw_offset +
2332 				     IXGBE_FW_LESM_PARAMETERS_PTR),
2333 				     &fw_lesm_param_offset);
2334 
2335 	if ((status != IXGBE_SUCCESS) ||
2336 	    (fw_lesm_param_offset == 0) || (fw_lesm_param_offset == 0xFFFF))
2337 		goto out;
2338 
2339 	/* get the LESM state word */
2340 	status = hw->eeprom.ops.read(hw, (fw_lesm_param_offset +
2341 				     IXGBE_FW_LESM_STATE_1),
2342 				     &fw_lesm_state);
2343 
2344 	if ((status == IXGBE_SUCCESS) &&
2345 	    (fw_lesm_state & IXGBE_FW_LESM_STATE_ENABLED))
2346 		lesm_enabled = TRUE;
2347 
2348 out:
2349 	return lesm_enabled;
2350 }
2351 
2352 /**
2353  *  ixgbe_read_eeprom_buffer_82599 - Read EEPROM word(s) using
2354  *  fastest available method
2355  *
2356  *  @hw: pointer to hardware structure
2357  *  @offset: offset of  word in EEPROM to read
2358  *  @words: number of words
2359  *  @data: word(s) read from the EEPROM
2360  *
2361  *  Retrieves 16 bit word(s) read from EEPROM
2362  **/
2363 static s32 ixgbe_read_eeprom_buffer_82599(struct ixgbe_hw *hw, u16 offset,
2364 					  u16 words, u16 *data)
2365 {
2366 	struct ixgbe_eeprom_info *eeprom = &hw->eeprom;
2367 	s32 ret_val = IXGBE_ERR_CONFIG;
2368 
2369 	DEBUGFUNC("ixgbe_read_eeprom_buffer_82599");
2370 
2371 	/*
2372 	 * If EEPROM is detected and can be addressed using 14 bits,
2373 	 * use EERD otherwise use bit bang
2374 	 */
2375 	if ((eeprom->type == ixgbe_eeprom_spi) &&
2376 	    (offset + (words - 1) <= IXGBE_EERD_MAX_ADDR))
2377 		ret_val = ixgbe_read_eerd_buffer_generic(hw, offset, words,
2378 							 data);
2379 	else
2380 		ret_val = ixgbe_read_eeprom_buffer_bit_bang_generic(hw, offset,
2381 								    words,
2382 								    data);
2383 
2384 	return ret_val;
2385 }
2386 
2387 /**
2388  *  ixgbe_read_eeprom_82599 - Read EEPROM word using
2389  *  fastest available method
2390  *
2391  *  @hw: pointer to hardware structure
2392  *  @offset: offset of  word in the EEPROM to read
2393  *  @data: word read from the EEPROM
2394  *
2395  *  Reads a 16 bit word from the EEPROM
2396  **/
2397 static s32 ixgbe_read_eeprom_82599(struct ixgbe_hw *hw,
2398 				   u16 offset, u16 *data)
2399 {
2400 	struct ixgbe_eeprom_info *eeprom = &hw->eeprom;
2401 	s32 ret_val = IXGBE_ERR_CONFIG;
2402 
2403 	DEBUGFUNC("ixgbe_read_eeprom_82599");
2404 
2405 	/*
2406 	 * If EEPROM is detected and can be addressed using 14 bits,
2407 	 * use EERD otherwise use bit bang
2408 	 */
2409 	if ((eeprom->type == ixgbe_eeprom_spi) &&
2410 	    (offset <= IXGBE_EERD_MAX_ADDR))
2411 		ret_val = ixgbe_read_eerd_generic(hw, offset, data);
2412 	else
2413 		ret_val = ixgbe_read_eeprom_bit_bang_generic(hw, offset, data);
2414 
2415 	return ret_val;
2416 }
2417 
2418 /**
2419  * ixgbe_reset_pipeline_82599 - perform pipeline reset
2420  *
2421  *  @hw: pointer to hardware structure
2422  *
2423  * Reset pipeline by asserting Restart_AN together with LMS change to ensure
2424  * full pipeline reset.  This function assumes the SW/FW lock is held.
2425  **/
2426 s32 ixgbe_reset_pipeline_82599(struct ixgbe_hw *hw)
2427 {
2428 	s32 ret_val;
2429 	u32 anlp1_reg = 0;
2430 	u32 i, autoc_reg, autoc2_reg;
2431 
2432 	/* Enable link if disabled in NVM */
2433 	autoc2_reg = IXGBE_READ_REG(hw, IXGBE_AUTOC2);
2434 	if (autoc2_reg & IXGBE_AUTOC2_LINK_DISABLE_MASK) {
2435 		autoc2_reg &= ~IXGBE_AUTOC2_LINK_DISABLE_MASK;
2436 		IXGBE_WRITE_REG(hw, IXGBE_AUTOC2, autoc2_reg);
2437 		IXGBE_WRITE_FLUSH(hw);
2438 	}
2439 
2440 	autoc_reg = IXGBE_READ_REG(hw, IXGBE_AUTOC);
2441 	autoc_reg |= IXGBE_AUTOC_AN_RESTART;
2442 	/* Write AUTOC register with toggled LMS[2] bit and Restart_AN */
2443 	IXGBE_WRITE_REG(hw, IXGBE_AUTOC,
2444 			autoc_reg ^ (0x4 << IXGBE_AUTOC_LMS_SHIFT));
2445 	/* Wait for AN to leave state 0 */
2446 	for (i = 0; i < 10; i++) {
2447 		msec_delay(4);
2448 		anlp1_reg = IXGBE_READ_REG(hw, IXGBE_ANLP1);
2449 		if (anlp1_reg & IXGBE_ANLP1_AN_STATE_MASK)
2450 			break;
2451 	}
2452 
2453 	if (!(anlp1_reg & IXGBE_ANLP1_AN_STATE_MASK)) {
2454 		DEBUGOUT("auto negotiation not completed\n");
2455 		ret_val = IXGBE_ERR_RESET_FAILED;
2456 		goto reset_pipeline_out;
2457 	}
2458 
2459 	ret_val = IXGBE_SUCCESS;
2460 
2461 reset_pipeline_out:
2462 	/* Write AUTOC register with original LMS field and Restart_AN */
2463 	IXGBE_WRITE_REG(hw, IXGBE_AUTOC, autoc_reg);
2464 	IXGBE_WRITE_FLUSH(hw);
2465 
2466 	return ret_val;
2467 }
2468 
2469 /**
2470  *  ixgbe_read_i2c_byte_82599 - Reads 8 bit word over I2C
2471  *  @hw: pointer to hardware structure
2472  *  @byte_offset: byte offset to read
2473  *  @data: value read
2474  *
2475  *  Performs byte read operation to SFP module's EEPROM over I2C interface at
2476  *  a specified device address.
2477  **/
2478 static s32 ixgbe_read_i2c_byte_82599(struct ixgbe_hw *hw, u8 byte_offset,
2479 				u8 dev_addr, u8 *data)
2480 {
2481 	u32 esdp;
2482 	s32 status;
2483 	s32 timeout = 200;
2484 
2485 	DEBUGFUNC("ixgbe_read_i2c_byte_82599");
2486 
2487 	if (hw->phy.qsfp_shared_i2c_bus == TRUE) {
2488 		/* Acquire I2C bus ownership. */
2489 		esdp = IXGBE_READ_REG(hw, IXGBE_ESDP);
2490 		esdp |= IXGBE_ESDP_SDP0;
2491 		IXGBE_WRITE_REG(hw, IXGBE_ESDP, esdp);
2492 		IXGBE_WRITE_FLUSH(hw);
2493 
2494 		while (timeout) {
2495 			esdp = IXGBE_READ_REG(hw, IXGBE_ESDP);
2496 			if (esdp & IXGBE_ESDP_SDP1)
2497 				break;
2498 
2499 			msec_delay(5);
2500 			timeout--;
2501 		}
2502 
2503 		if (!timeout) {
2504 			DEBUGOUT("Driver can't access resource,"
2505 				 " acquiring I2C bus timeout.\n");
2506 			status = IXGBE_ERR_I2C;
2507 			goto release_i2c_access;
2508 		}
2509 	}
2510 
2511 	status = ixgbe_read_i2c_byte_generic(hw, byte_offset, dev_addr, data);
2512 
2513 release_i2c_access:
2514 
2515 	if (hw->phy.qsfp_shared_i2c_bus == TRUE) {
2516 		/* Release I2C bus ownership. */
2517 		esdp = IXGBE_READ_REG(hw, IXGBE_ESDP);
2518 		esdp &= ~IXGBE_ESDP_SDP0;
2519 		IXGBE_WRITE_REG(hw, IXGBE_ESDP, esdp);
2520 		IXGBE_WRITE_FLUSH(hw);
2521 	}
2522 
2523 	return status;
2524 }
2525 
2526 /**
2527  *  ixgbe_write_i2c_byte_82599 - Writes 8 bit word over I2C
2528  *  @hw: pointer to hardware structure
2529  *  @byte_offset: byte offset to write
2530  *  @data: value to write
2531  *
2532  *  Performs byte write operation to SFP module's EEPROM over I2C interface at
2533  *  a specified device address.
2534  **/
2535 static s32 ixgbe_write_i2c_byte_82599(struct ixgbe_hw *hw, u8 byte_offset,
2536 				 u8 dev_addr, u8 data)
2537 {
2538 	u32 esdp;
2539 	s32 status;
2540 	s32 timeout = 200;
2541 
2542 	DEBUGFUNC("ixgbe_write_i2c_byte_82599");
2543 
2544 	if (hw->phy.qsfp_shared_i2c_bus == TRUE) {
2545 		/* Acquire I2C bus ownership. */
2546 		esdp = IXGBE_READ_REG(hw, IXGBE_ESDP);
2547 		esdp |= IXGBE_ESDP_SDP0;
2548 		IXGBE_WRITE_REG(hw, IXGBE_ESDP, esdp);
2549 		IXGBE_WRITE_FLUSH(hw);
2550 
2551 		while (timeout) {
2552 			esdp = IXGBE_READ_REG(hw, IXGBE_ESDP);
2553 			if (esdp & IXGBE_ESDP_SDP1)
2554 				break;
2555 
2556 			msec_delay(5);
2557 			timeout--;
2558 		}
2559 
2560 		if (!timeout) {
2561 			DEBUGOUT("Driver can't access resource,"
2562 				 " acquiring I2C bus timeout.\n");
2563 			status = IXGBE_ERR_I2C;
2564 			goto release_i2c_access;
2565 		}
2566 	}
2567 
2568 	status = ixgbe_write_i2c_byte_generic(hw, byte_offset, dev_addr, data);
2569 
2570 release_i2c_access:
2571 
2572 	if (hw->phy.qsfp_shared_i2c_bus == TRUE) {
2573 		/* Release I2C bus ownership. */
2574 		esdp = IXGBE_READ_REG(hw, IXGBE_ESDP);
2575 		esdp &= ~IXGBE_ESDP_SDP0;
2576 		IXGBE_WRITE_REG(hw, IXGBE_ESDP, esdp);
2577 		IXGBE_WRITE_FLUSH(hw);
2578 	}
2579 
2580 	return status;
2581 }
2582