1 /****************************************************************************** 2 3 Copyright (c) 2001-2008, Intel Corporation 4 All rights reserved. 5 6 Redistribution and use in source and binary forms, with or without 7 modification, are permitted provided that the following conditions are met: 8 9 1. Redistributions of source code must retain the above copyright notice, 10 this list of conditions and the following disclaimer. 11 12 2. Redistributions in binary form must reproduce the above copyright 13 notice, this list of conditions and the following disclaimer in the 14 documentation and/or other materials provided with the distribution. 15 16 3. Neither the name of the Intel Corporation nor the names of its 17 contributors may be used to endorse or promote products derived from 18 this software without specific prior written permission. 19 20 THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 21 AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 22 IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 23 ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE 24 LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 25 CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 26 SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 27 INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 28 CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 29 ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 30 POSSIBILITY OF SUCH DAMAGE. 31 32 ******************************************************************************/ 33 /*$FreeBSD$*/ 34 35 #include "ixgbe_type.h" 36 #include "ixgbe_api.h" 37 #include "ixgbe_common.h" 38 #include "ixgbe_phy.h" 39 40 s32 ixgbe_init_ops_82598(struct ixgbe_hw *hw); 41 s32 ixgbe_get_link_capabilities_82598(struct ixgbe_hw *hw, 42 ixgbe_link_speed *speed, 43 bool *autoneg); 44 s32 ixgbe_get_copper_link_capabilities_82598(struct ixgbe_hw *hw, 45 ixgbe_link_speed *speed, 46 bool *autoneg); 47 enum ixgbe_media_type ixgbe_get_media_type_82598(struct ixgbe_hw *hw); 48 s32 ixgbe_setup_fc_82598(struct ixgbe_hw *hw, s32 packetbuf_num); 49 s32 ixgbe_setup_mac_link_82598(struct ixgbe_hw *hw); 50 s32 ixgbe_check_mac_link_82598(struct ixgbe_hw *hw, 51 ixgbe_link_speed *speed, 52 bool *link_up, bool link_up_wait_to_complete); 53 s32 ixgbe_setup_mac_link_speed_82598(struct ixgbe_hw *hw, 54 ixgbe_link_speed speed, 55 bool autoneg, 56 bool autoneg_wait_to_complete); 57 s32 ixgbe_setup_copper_link_82598(struct ixgbe_hw *hw); 58 s32 ixgbe_setup_copper_link_speed_82598(struct ixgbe_hw *hw, 59 ixgbe_link_speed speed, 60 bool autoneg, 61 bool autoneg_wait_to_complete); 62 #ifndef NO_82598_A0_SUPPORT 63 s32 ixgbe_reset_hw_rev_0_82598(struct ixgbe_hw *hw); 64 #endif 65 s32 ixgbe_reset_hw_82598(struct ixgbe_hw *hw); 66 s32 ixgbe_configure_fiber_serdes_fc_82598(struct ixgbe_hw *hw); 67 s32 ixgbe_setup_fiber_serdes_link_82598(struct ixgbe_hw *hw); 68 s32 ixgbe_set_vmdq_82598(struct ixgbe_hw *hw, u32 rar, u32 vmdq); 69 s32 ixgbe_clear_vmdq_82598(struct ixgbe_hw *hw, u32 rar, u32 vmdq); 70 s32 ixgbe_set_vfta_82598(struct ixgbe_hw *hw, u32 vlan, 71 u32 vind, bool vlan_on); 72 s32 ixgbe_clear_vfta_82598(struct ixgbe_hw *hw); 73 s32 ixgbe_blink_led_stop_82598(struct ixgbe_hw *hw, u32 index); 74 s32 ixgbe_blink_led_start_82598(struct ixgbe_hw *hw, u32 index); 75 76 /** 77 * ixgbe_init_ops_82598 - Inits func ptrs and MAC type 78 * @hw: pointer to hardware structure 79 * 80 * Initialize the function pointers and assign the MAC type for 82598. 81 * Does not touch the hardware. 82 **/ 83 s32 ixgbe_init_ops_82598(struct ixgbe_hw *hw) 84 { 85 struct ixgbe_mac_info *mac = &hw->mac; 86 struct ixgbe_phy_info *phy = &hw->phy; 87 s32 ret_val; 88 89 ret_val = ixgbe_init_phy_ops_generic(hw); 90 ret_val = ixgbe_init_ops_generic(hw); 91 92 /* MAC */ 93 #ifndef NO_82598_A0_SUPPORT 94 if (hw->revision_id == 0) 95 mac->ops.reset_hw = &ixgbe_reset_hw_rev_0_82598; 96 else 97 mac->ops.reset_hw = &ixgbe_reset_hw_82598; 98 #else 99 mac->ops.reset_hw = &ixgbe_reset_hw_82598; 100 #endif 101 mac->ops.get_media_type = &ixgbe_get_media_type_82598; 102 103 /* LEDs */ 104 mac->ops.blink_led_start = &ixgbe_blink_led_start_82598; 105 mac->ops.blink_led_stop = &ixgbe_blink_led_stop_82598; 106 107 /* RAR, Multicast, VLAN */ 108 mac->ops.set_vmdq = &ixgbe_set_vmdq_82598; 109 mac->ops.clear_vmdq = &ixgbe_clear_vmdq_82598; 110 mac->ops.set_vfta = &ixgbe_set_vfta_82598; 111 mac->ops.clear_vfta = &ixgbe_clear_vfta_82598; 112 113 /* Flow Control */ 114 mac->ops.setup_fc = &ixgbe_setup_fc_82598; 115 116 /* Call PHY identify routine to get the phy type */ 117 phy->ops.identify(hw); 118 119 /* PHY Init */ 120 switch (hw->phy.type) { 121 case ixgbe_phy_tn: 122 phy->ops.check_link = &ixgbe_check_phy_link_tnx; 123 phy->ops.get_firmware_version = 124 &ixgbe_get_phy_firmware_version_tnx; 125 break; 126 default: 127 break; 128 } 129 130 /* Link */ 131 mac->ops.check_link = &ixgbe_check_mac_link_82598; 132 if (mac->ops.get_media_type(hw) == ixgbe_media_type_copper) { 133 mac->ops.setup_link = &ixgbe_setup_copper_link_82598; 134 mac->ops.setup_link_speed = 135 &ixgbe_setup_copper_link_speed_82598; 136 mac->ops.get_link_capabilities = 137 &ixgbe_get_copper_link_capabilities_82598; 138 } else { 139 mac->ops.setup_link = &ixgbe_setup_mac_link_82598; 140 mac->ops.setup_link_speed = &ixgbe_setup_mac_link_speed_82598; 141 mac->ops.get_link_capabilities = 142 &ixgbe_get_link_capabilities_82598; 143 } 144 145 mac->mcft_size = 128; 146 mac->vft_size = 128; 147 mac->num_rar_entries = 16; 148 mac->max_tx_queues = 32; 149 mac->max_rx_queues = 64; 150 151 return IXGBE_SUCCESS; 152 } 153 154 /** 155 * ixgbe_get_link_capabilities_82598 - Determines link capabilities 156 * @hw: pointer to hardware structure 157 * @speed: pointer to link speed 158 * @autoneg: boolean auto-negotiation value 159 * 160 * Determines the link capabilities by reading the AUTOC register. 161 **/ 162 s32 ixgbe_get_link_capabilities_82598(struct ixgbe_hw *hw, 163 ixgbe_link_speed *speed, 164 bool *autoneg) 165 { 166 s32 status = IXGBE_SUCCESS; 167 s32 autoc_reg; 168 169 autoc_reg = IXGBE_READ_REG(hw, IXGBE_AUTOC); 170 171 if (hw->mac.link_settings_loaded) { 172 autoc_reg &= ~IXGBE_AUTOC_LMS_ATTACH_TYPE; 173 autoc_reg &= ~IXGBE_AUTOC_LMS_MASK; 174 autoc_reg |= hw->mac.link_attach_type; 175 autoc_reg |= hw->mac.link_mode_select; 176 } 177 178 switch (autoc_reg & IXGBE_AUTOC_LMS_MASK) { 179 case IXGBE_AUTOC_LMS_1G_LINK_NO_AN: 180 *speed = IXGBE_LINK_SPEED_1GB_FULL; 181 *autoneg = FALSE; 182 break; 183 184 case IXGBE_AUTOC_LMS_10G_LINK_NO_AN: 185 *speed = IXGBE_LINK_SPEED_10GB_FULL; 186 *autoneg = FALSE; 187 break; 188 189 case IXGBE_AUTOC_LMS_1G_AN: 190 *speed = IXGBE_LINK_SPEED_1GB_FULL; 191 *autoneg = TRUE; 192 break; 193 194 case IXGBE_AUTOC_LMS_KX4_AN: 195 case IXGBE_AUTOC_LMS_KX4_AN_1G_AN: 196 *speed = IXGBE_LINK_SPEED_UNKNOWN; 197 if (autoc_reg & IXGBE_AUTOC_KX4_SUPP) 198 *speed |= IXGBE_LINK_SPEED_10GB_FULL; 199 if (autoc_reg & IXGBE_AUTOC_KX_SUPP) 200 *speed |= IXGBE_LINK_SPEED_1GB_FULL; 201 *autoneg = TRUE; 202 break; 203 204 default: 205 status = IXGBE_ERR_LINK_SETUP; 206 break; 207 } 208 209 return status; 210 } 211 212 /** 213 * ixgbe_get_copper_link_capabilities_82598 - Determines link capabilities 214 * @hw: pointer to hardware structure 215 * @speed: pointer to link speed 216 * @autoneg: boolean auto-negotiation value 217 * 218 * Determines the link capabilities by reading the AUTOC register. 219 **/ 220 s32 ixgbe_get_copper_link_capabilities_82598(struct ixgbe_hw *hw, 221 ixgbe_link_speed *speed, 222 bool *autoneg) 223 { 224 s32 status = IXGBE_ERR_LINK_SETUP; 225 u16 speed_ability; 226 227 *speed = 0; 228 *autoneg = TRUE; 229 230 status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_PHY_SPEED_ABILITY, 231 IXGBE_MDIO_PMA_PMD_DEV_TYPE, 232 &speed_ability); 233 234 if (status == IXGBE_SUCCESS) { 235 if (speed_ability & IXGBE_MDIO_PHY_SPEED_10G) 236 *speed |= IXGBE_LINK_SPEED_10GB_FULL; 237 if (speed_ability & IXGBE_MDIO_PHY_SPEED_1G) 238 *speed |= IXGBE_LINK_SPEED_1GB_FULL; 239 } 240 241 return status; 242 } 243 244 /** 245 * ixgbe_get_media_type_82598 - Determines media type 246 * @hw: pointer to hardware structure 247 * 248 * Returns the media type (fiber, copper, backplane) 249 **/ 250 enum ixgbe_media_type ixgbe_get_media_type_82598(struct ixgbe_hw *hw) 251 { 252 enum ixgbe_media_type media_type; 253 254 /* Media type for I82598 is based on device ID */ 255 switch (hw->device_id) { 256 case IXGBE_DEV_ID_82598AF_DUAL_PORT: 257 case IXGBE_DEV_ID_82598AF_SINGLE_PORT: 258 case IXGBE_DEV_ID_82598EB_CX4: 259 case IXGBE_DEV_ID_82598_CX4_DUAL_PORT: 260 case IXGBE_DEV_ID_82598EB_XF_LR: 261 media_type = ixgbe_media_type_fiber; 262 break; 263 case IXGBE_DEV_ID_82598AT: 264 media_type = ixgbe_media_type_copper; 265 break; 266 case IXGBE_DEV_ID_82598AT_DUAL_PORT: 267 media_type = ixgbe_media_type_copper; 268 break; 269 default: 270 media_type = ixgbe_media_type_unknown; 271 break; 272 } 273 274 return media_type; 275 } 276 277 /** 278 * ixgbe_setup_fc_82598 - Configure flow control settings 279 * @hw: pointer to hardware structure 280 * @packetbuf_num: packet buffer number (0-7) 281 * 282 * Configures the flow control settings based on SW configuration. This 283 * function is used for 802.3x flow control configuration only. 284 **/ 285 s32 ixgbe_setup_fc_82598(struct ixgbe_hw *hw, s32 packetbuf_num) 286 { 287 u32 frctl_reg; 288 u32 rmcs_reg; 289 290 if (packetbuf_num < 0 || packetbuf_num > 7) { 291 DEBUGOUT1("Invalid packet buffer number [%d], expected range is" 292 " 0-7\n", packetbuf_num); 293 ASSERT(0); 294 } 295 296 frctl_reg = IXGBE_READ_REG(hw, IXGBE_FCTRL); 297 frctl_reg &= ~(IXGBE_FCTRL_RFCE | IXGBE_FCTRL_RPFCE); 298 299 rmcs_reg = IXGBE_READ_REG(hw, IXGBE_RMCS); 300 rmcs_reg &= ~(IXGBE_RMCS_TFCE_PRIORITY | IXGBE_RMCS_TFCE_802_3X); 301 302 /* 303 * 10 gig parts do not have a word in the EEPROM to determine the 304 * default flow control setting, so we explicitly set it to full. 305 */ 306 if (hw->fc.type == ixgbe_fc_default) 307 hw->fc.type = ixgbe_fc_full; 308 309 /* 310 * We want to save off the original Flow Control configuration just in 311 * case we get disconnected and then reconnected into a different hub 312 * or switch with different Flow Control capabilities. 313 */ 314 hw->fc.original_type = hw->fc.type; 315 316 /* 317 * The possible values of the "flow_control" parameter are: 318 * 0: Flow control is completely disabled 319 * 1: Rx flow control is enabled (we can receive pause frames but not 320 * send pause frames). 321 * 2: Tx flow control is enabled (we can send pause frames but we do not 322 * support receiving pause frames) 323 * 3: Both Rx and Tx flow control (symmetric) are enabled. 324 * other: Invalid. 325 */ 326 switch (hw->fc.type) { 327 case ixgbe_fc_none: 328 break; 329 case ixgbe_fc_rx_pause: 330 /* 331 * Rx Flow control is enabled, 332 * and Tx Flow control is disabled. 333 */ 334 frctl_reg |= IXGBE_FCTRL_RFCE; 335 break; 336 case ixgbe_fc_tx_pause: 337 /* 338 * Tx Flow control is enabled, and Rx Flow control is disabled, 339 * by a software over-ride. 340 */ 341 rmcs_reg |= IXGBE_RMCS_TFCE_802_3X; 342 break; 343 case ixgbe_fc_full: 344 /* 345 * Flow control (both Rx and Tx) is enabled by a software 346 * over-ride. 347 */ 348 frctl_reg |= IXGBE_FCTRL_RFCE; 349 rmcs_reg |= IXGBE_RMCS_TFCE_802_3X; 350 break; 351 default: 352 /* We should never get here. The value should be 0-3. */ 353 DEBUGOUT("Flow control param set incorrectly\n"); 354 ASSERT(0); 355 break; 356 } 357 358 /* Enable 802.3x based flow control settings. */ 359 IXGBE_WRITE_REG(hw, IXGBE_FCTRL, frctl_reg); 360 IXGBE_WRITE_REG(hw, IXGBE_RMCS, rmcs_reg); 361 362 /* 363 * Check for invalid software configuration, zeros are completely 364 * invalid for all parameters used past this point, and if we enable 365 * flow control with zero water marks, we blast flow control packets. 366 */ 367 if (!hw->fc.low_water || !hw->fc.high_water || !hw->fc.pause_time) { 368 DEBUGOUT("Flow control structure initialized incorrectly\n"); 369 return IXGBE_ERR_INVALID_LINK_SETTINGS; 370 } 371 372 /* 373 * We need to set up the Receive Threshold high and low water 374 * marks as well as (optionally) enabling the transmission of 375 * XON frames. 376 */ 377 if (hw->fc.type & ixgbe_fc_tx_pause) { 378 if (hw->fc.send_xon) { 379 IXGBE_WRITE_REG(hw, IXGBE_FCRTL(packetbuf_num), 380 (hw->fc.low_water | IXGBE_FCRTL_XONE)); 381 } else { 382 IXGBE_WRITE_REG(hw, IXGBE_FCRTL(packetbuf_num), 383 hw->fc.low_water); 384 } 385 IXGBE_WRITE_REG(hw, IXGBE_FCRTH(packetbuf_num), 386 (hw->fc.high_water)|IXGBE_FCRTH_FCEN); 387 } 388 389 IXGBE_WRITE_REG(hw, IXGBE_FCTTV(0), hw->fc.pause_time); 390 IXGBE_WRITE_REG(hw, IXGBE_FCRTV, (hw->fc.pause_time >> 1)); 391 392 return IXGBE_SUCCESS; 393 } 394 395 /** 396 * ixgbe_setup_mac_link_82598 - Configures MAC link settings 397 * @hw: pointer to hardware structure 398 * 399 * Configures link settings based on values in the ixgbe_hw struct. 400 * Restarts the link. Performs autonegotiation if needed. 401 **/ 402 s32 ixgbe_setup_mac_link_82598(struct ixgbe_hw *hw) 403 { 404 ixgbe_link_speed speed; 405 bool link_up; 406 u32 autoc_reg; 407 u32 links_reg; 408 u32 i; 409 s32 status = IXGBE_SUCCESS; 410 411 autoc_reg = IXGBE_READ_REG(hw, IXGBE_AUTOC); 412 413 if (hw->mac.link_settings_loaded) { 414 autoc_reg &= ~IXGBE_AUTOC_LMS_ATTACH_TYPE; 415 autoc_reg &= ~IXGBE_AUTOC_LMS_MASK; 416 autoc_reg |= hw->mac.link_attach_type; 417 autoc_reg |= hw->mac.link_mode_select; 418 419 IXGBE_WRITE_REG(hw, IXGBE_AUTOC, autoc_reg); 420 IXGBE_WRITE_FLUSH(hw); 421 msec_delay(50); 422 } 423 424 /* Restart link */ 425 autoc_reg |= IXGBE_AUTOC_AN_RESTART; 426 IXGBE_WRITE_REG(hw, IXGBE_AUTOC, autoc_reg); 427 428 /* Only poll for autoneg to complete if specified to do so */ 429 if (hw->phy.autoneg_wait_to_complete) { 430 if (hw->mac.link_mode_select == IXGBE_AUTOC_LMS_KX4_AN || 431 hw->mac.link_mode_select == IXGBE_AUTOC_LMS_KX4_AN_1G_AN) { 432 links_reg = 0; /* Just in case Autoneg time = 0 */ 433 for (i = 0; i < IXGBE_AUTO_NEG_TIME; i++) { 434 links_reg = IXGBE_READ_REG(hw, IXGBE_LINKS); 435 if (links_reg & IXGBE_LINKS_KX_AN_COMP) 436 break; 437 msec_delay(100); 438 } 439 if (!(links_reg & IXGBE_LINKS_KX_AN_COMP)) { 440 status = IXGBE_ERR_AUTONEG_NOT_COMPLETE; 441 DEBUGOUT("Autonegotiation did not complete.\n"); 442 } 443 } 444 } 445 446 /* 447 * We want to save off the original Flow Control configuration just in 448 * case we get disconnected and then reconnected into a different hub 449 * or switch with different Flow Control capabilities. 450 */ 451 hw->fc.original_type = hw->fc.type; 452 /* 453 * Set up the SerDes link if in 1Gb mode, otherwise just set up 454 * 10Gb flow control. 455 */ 456 hw->mac.ops.check_link(hw, &speed, &link_up, FALSE); 457 if (speed == IXGBE_LINK_SPEED_1GB_FULL) 458 status = ixgbe_setup_fiber_serdes_link_82598(hw); 459 else 460 ixgbe_setup_fc_82598(hw, 0); 461 462 /* Add delay to filter out noises during initial link setup */ 463 msec_delay(50); 464 465 return status; 466 } 467 468 /** 469 * ixgbe_check_mac_link_82598 - Get link/speed status 470 * @hw: pointer to hardware structure 471 * @speed: pointer to link speed 472 * @link_up: TRUE is link is up, FALSE otherwise 473 * @link_up_wait_to_complete: bool used to wait for link up or not 474 * 475 * Reads the links register to determine if link is up and the current speed 476 **/ 477 s32 ixgbe_check_mac_link_82598(struct ixgbe_hw *hw, ixgbe_link_speed *speed, 478 bool *link_up, bool link_up_wait_to_complete) 479 { 480 u32 links_reg; 481 u32 i; 482 483 links_reg = IXGBE_READ_REG(hw, IXGBE_LINKS); 484 if (link_up_wait_to_complete) { 485 for (i = 0; i < IXGBE_LINK_UP_TIME; i++) { 486 if (links_reg & IXGBE_LINKS_UP) { 487 *link_up = TRUE; 488 break; 489 } else { 490 *link_up = FALSE; 491 } 492 msec_delay(100); 493 links_reg = IXGBE_READ_REG(hw, IXGBE_LINKS); 494 } 495 } else { 496 if (links_reg & IXGBE_LINKS_UP) 497 *link_up = TRUE; 498 else 499 *link_up = FALSE; 500 } 501 502 if (links_reg & IXGBE_LINKS_SPEED) 503 *speed = IXGBE_LINK_SPEED_10GB_FULL; 504 else 505 *speed = IXGBE_LINK_SPEED_1GB_FULL; 506 507 return IXGBE_SUCCESS; 508 } 509 510 /** 511 * ixgbe_configure_fiber_serdes_fc_82598 - Configure fiber flow control 512 * @hw: pointer to hardware structure 513 * 514 * Reads PCS registers and sets flow control settings, based on 515 * link-partner's abilities. 516 **/ 517 s32 ixgbe_configure_fiber_serdes_fc_82598(struct ixgbe_hw *hw) 518 { 519 s32 ret_val = IXGBE_SUCCESS; 520 u32 pcs_anadv_reg, pcs_lpab_reg, pcs_lstat_reg, i; 521 DEBUGFUNC("ixgbe_configure_fiber_serdes_fc_82598"); 522 523 /* Check that autonegotiation has completed */ 524 for (i = 0; i < FIBER_LINK_UP_LIMIT; i++) { 525 msec_delay(10); 526 pcs_lstat_reg = IXGBE_READ_REG(hw, IXGBE_PCS1GLSTA); 527 if (pcs_lstat_reg & IXGBE_PCS1GLSTA_LINK_OK) { 528 if (pcs_lstat_reg & IXGBE_PCS1GLSTA_AN_COMPLETE) { 529 if (!(pcs_lstat_reg & 530 (IXGBE_PCS1GLSTA_AN_TIMED_OUT))) 531 hw->mac.autoneg_failed = 0; 532 else 533 hw->mac.autoneg_failed = 1; 534 break; 535 } else { 536 hw->mac.autoneg_failed = 1; 537 break; 538 } 539 } 540 } 541 542 if (hw->mac.autoneg_failed) { 543 /* 544 * AutoNeg failed to achieve a link, so we will turn 545 * flow control off. 546 */ 547 hw->fc.type = ixgbe_fc_none; 548 DEBUGOUT("Flow Control = NONE.\n"); 549 ret_val = ixgbe_setup_fc_82598(hw, 0); 550 goto out; 551 } 552 553 /* 554 * Read the AN advertisement and LP ability registers and resolve 555 * local flow control settings accordingly 556 */ 557 pcs_anadv_reg = IXGBE_READ_REG(hw, IXGBE_PCS1GANA); 558 pcs_lpab_reg = IXGBE_READ_REG(hw, IXGBE_PCS1GANLP); 559 if ((pcs_anadv_reg & IXGBE_PCS1GANA_SYM_PAUSE) && 560 (pcs_lpab_reg & IXGBE_PCS1GANA_SYM_PAUSE)) { 561 /* 562 * Now we need to check if the user selected Rx ONLY 563 * of pause frames. In this case, we had to advertise 564 * FULL flow control because we could not advertise RX 565 * ONLY. Hence, we must now check to see if we need to 566 * turn OFF the TRANSMISSION of PAUSE frames. 567 */ 568 if (hw->fc.original_type == ixgbe_fc_full) { 569 hw->fc.type = ixgbe_fc_full; 570 DEBUGOUT("Flow Control = FULL.\n"); 571 } else { 572 hw->fc.type = ixgbe_fc_rx_pause; 573 DEBUGOUT("Flow Control = RX PAUSE frames only.\n"); 574 } 575 } else if (!(pcs_anadv_reg & IXGBE_PCS1GANA_SYM_PAUSE) && 576 (pcs_anadv_reg & IXGBE_PCS1GANA_ASM_PAUSE) && 577 (pcs_lpab_reg & IXGBE_PCS1GANA_SYM_PAUSE) && 578 (pcs_lpab_reg & IXGBE_PCS1GANA_ASM_PAUSE)) { 579 hw->fc.type = ixgbe_fc_tx_pause; 580 DEBUGOUT("Flow Control = TX PAUSE frames only.\n"); 581 } else if ((pcs_anadv_reg & IXGBE_PCS1GANA_SYM_PAUSE) && 582 (pcs_anadv_reg & IXGBE_PCS1GANA_ASM_PAUSE) && 583 !(pcs_lpab_reg & IXGBE_PCS1GANA_SYM_PAUSE) && 584 (pcs_lpab_reg & IXGBE_PCS1GANA_ASM_PAUSE)) { 585 hw->fc.type = ixgbe_fc_rx_pause; 586 DEBUGOUT("Flow Control = RX PAUSE frames only.\n"); 587 } else { 588 hw->fc.type = ixgbe_fc_none; 589 DEBUGOUT("Flow Control = NONE.\n"); 590 } 591 592 ret_val = ixgbe_setup_fc_82598(hw, 0); 593 if (ret_val) { 594 DEBUGOUT("Error forcing flow control settings\n"); 595 goto out; 596 } 597 598 out: 599 return ret_val; 600 } 601 602 /** 603 * ixgbe_setup_fiber_serdes_link_82598 - Configure fiber serdes link 604 * @hw: pointer to hardware structure 605 * 606 * Sets up PCS registers and sets flow control settings, based on 607 * link-partner's abilities. 608 **/ 609 s32 ixgbe_setup_fiber_serdes_link_82598(struct ixgbe_hw *hw) 610 { 611 u32 reg; 612 s32 ret_val; 613 614 DEBUGFUNC("ixgbe_setup_fiber_serdes_link_82598"); 615 616 /* 617 * 10 gig parts do not have a word in the EEPROM to determine the 618 * default flow control setting, so we explicitly set it to full. 619 */ 620 if (hw->fc.type == ixgbe_fc_default) 621 hw->fc.type = ixgbe_fc_full; 622 623 /* 624 * 82598 fiber/serdes devices require that flow control be resolved in 625 * software. 626 */ 627 reg = IXGBE_READ_REG(hw, IXGBE_PCS1GANA); 628 629 /* 630 * The possible values of the "fc" parameter are: 631 * 0: Flow control is completely disabled 632 * 1: Rx flow control is enabled (we can receive pause frames, 633 * but not send pause frames). 634 * 2: Tx flow control is enabled (we can send pause frames but 635 * we do not support receiving pause frames). 636 * 3: Both Rx and Tx flow control (symmetric) are enabled. 637 */ 638 switch (hw->fc.type) { 639 case ixgbe_fc_none: 640 /* 641 * Flow control completely disabled by a software 642 * over-ride. 643 */ 644 reg &= ~(IXGBE_PCS1GANA_SYM_PAUSE | IXGBE_PCS1GANA_ASM_PAUSE); 645 break; 646 case ixgbe_fc_rx_pause: 647 /* 648 * Rx Flow control is enabled and Tx Flow control is 649 * disabled by a software over-ride. Since there really 650 * isn't a way to advertise that we are capable of RX 651 * Pause ONLY, we will advertise that we support both 652 * symmetric and asymmetric Rx PAUSE. Later, we will 653 * disable the adapter's ability to send PAUSE frames. 654 */ 655 reg |= (IXGBE_PCS1GANA_SYM_PAUSE | IXGBE_PCS1GANA_ASM_PAUSE); 656 break; 657 case ixgbe_fc_tx_pause: 658 /* 659 * Tx Flow control is enabled, and Rx Flow control is 660 * disabled, by a software over-ride. 661 */ 662 reg |= (IXGBE_PCS1GANA_ASM_PAUSE); 663 reg &= ~(IXGBE_PCS1GANA_SYM_PAUSE); 664 break; 665 case ixgbe_fc_full: 666 /* 667 * Flow control (both Rx and Tx) is enabled by a 668 * software over-ride. 669 */ 670 reg |= (IXGBE_PCS1GANA_SYM_PAUSE | IXGBE_PCS1GANA_ASM_PAUSE); 671 break; 672 default: 673 DEBUGOUT("Flow control param set incorrectly\n"); 674 ret_val = -IXGBE_ERR_CONFIG; 675 goto out; 676 break; 677 } 678 679 IXGBE_WRITE_REG(hw, IXGBE_PCS1GANA, reg); 680 reg = IXGBE_READ_REG(hw, IXGBE_PCS1GLCTL); 681 682 /* Set PCS register for autoneg */ 683 /* Enable and restart autoneg */ 684 reg |= IXGBE_PCS1GLCTL_AN_ENABLE | IXGBE_PCS1GLCTL_AN_RESTART; 685 686 reg &= ~IXGBE_PCS1GLCTL_AN_1G_TIMEOUT_EN; /* Disable AN timeout */ 687 DEBUGOUT1("Configuring Autoneg; PCS_LCTL = 0x%08X\n", reg); 688 IXGBE_WRITE_REG(hw, IXGBE_PCS1GLCTL, reg); 689 690 /* 691 * Configure flow control. If we aren't auto-negotiating, 692 * just setup the flow control and do not worry about PCS autoneg. 693 */ 694 ixgbe_configure_fiber_serdes_fc_82598(hw); 695 696 out: 697 return IXGBE_SUCCESS; 698 } 699 700 /** 701 * ixgbe_setup_mac_link_speed_82598 - Set MAC link speed 702 * @hw: pointer to hardware structure 703 * @speed: new link speed 704 * @autoneg: TRUE if auto-negotiation enabled 705 * @autoneg_wait_to_complete: TRUE if waiting is needed to complete 706 * 707 * Set the link speed in the AUTOC register and restarts link. 708 **/ 709 s32 ixgbe_setup_mac_link_speed_82598(struct ixgbe_hw *hw, 710 ixgbe_link_speed speed, bool autoneg, 711 bool autoneg_wait_to_complete) 712 { 713 s32 status = IXGBE_SUCCESS; 714 715 /* If speed is 10G, then check for CX4 or XAUI. */ 716 if ((speed == IXGBE_LINK_SPEED_10GB_FULL) && 717 (!(hw->mac.link_attach_type & IXGBE_AUTOC_10G_KX4))) { 718 hw->mac.link_mode_select = IXGBE_AUTOC_LMS_10G_LINK_NO_AN; 719 } else if ((speed == IXGBE_LINK_SPEED_1GB_FULL) && (!autoneg)) { 720 hw->mac.link_mode_select = IXGBE_AUTOC_LMS_1G_LINK_NO_AN; 721 } else if (autoneg) { 722 /* BX mode - Autonegotiate 1G */ 723 if (!(hw->mac.link_attach_type & IXGBE_AUTOC_1G_PMA_PMD)) 724 hw->mac.link_mode_select = IXGBE_AUTOC_LMS_1G_AN; 725 else /* KX/KX4 mode */ 726 hw->mac.link_mode_select = IXGBE_AUTOC_LMS_KX4_AN_1G_AN; 727 } else { 728 status = IXGBE_ERR_LINK_SETUP; 729 } 730 731 if (status == IXGBE_SUCCESS) { 732 hw->phy.autoneg_wait_to_complete = autoneg_wait_to_complete; 733 734 hw->mac.link_settings_loaded = TRUE; 735 /* 736 * Setup and restart the link based on the new values in 737 * ixgbe_hw This will write the AUTOC register based on the new 738 * stored values 739 */ 740 ixgbe_setup_mac_link_82598(hw); 741 } 742 743 return status; 744 } 745 746 747 /** 748 * ixgbe_setup_copper_link_82598 - Setup copper link settings 749 * @hw: pointer to hardware structure 750 * 751 * Configures link settings based on values in the ixgbe_hw struct. 752 * Restarts the link. Performs autonegotiation if needed. Restart 753 * phy and wait for autonegotiate to finish. Then synchronize the 754 * MAC and PHY. 755 **/ 756 s32 ixgbe_setup_copper_link_82598(struct ixgbe_hw *hw) 757 { 758 s32 status; 759 760 /* Restart autonegotiation on PHY */ 761 status = hw->phy.ops.setup_link(hw); 762 763 /* Set MAC to KX/KX4 autoneg, which defaults to Parallel detection */ 764 hw->mac.link_attach_type = (IXGBE_AUTOC_10G_KX4 | IXGBE_AUTOC_1G_KX); 765 hw->mac.link_mode_select = IXGBE_AUTOC_LMS_KX4_AN; 766 767 /* Set up MAC */ 768 ixgbe_setup_mac_link_82598(hw); 769 770 return status; 771 } 772 773 /** 774 * ixgbe_setup_copper_link_speed_82598 - Set the PHY autoneg advertised field 775 * @hw: pointer to hardware structure 776 * @speed: new link speed 777 * @autoneg: TRUE if autonegotiation enabled 778 * @autoneg_wait_to_complete: TRUE if waiting is needed to complete 779 * 780 * Sets the link speed in the AUTOC register in the MAC and restarts link. 781 **/ 782 s32 ixgbe_setup_copper_link_speed_82598(struct ixgbe_hw *hw, 783 ixgbe_link_speed speed, 784 bool autoneg, 785 bool autoneg_wait_to_complete) 786 { 787 s32 status; 788 789 /* Setup the PHY according to input speed */ 790 status = hw->phy.ops.setup_link_speed(hw, speed, autoneg, 791 autoneg_wait_to_complete); 792 793 /* Set MAC to KX/KX4 autoneg, which defaults to Parallel detection */ 794 hw->mac.link_attach_type = (IXGBE_AUTOC_10G_KX4 | IXGBE_AUTOC_1G_KX); 795 hw->mac.link_mode_select = IXGBE_AUTOC_LMS_KX4_AN; 796 797 /* Set up MAC */ 798 ixgbe_setup_mac_link_82598(hw); 799 800 return status; 801 } 802 803 #ifndef NO_82598_A0_SUPPORT 804 /** 805 * ixgbe_reset_hw_rev_0_82598 - Performs hardware reset 806 * @hw: pointer to hardware structure 807 * 808 * Resets the hardware by resetting the transmit and receive units, masks and 809 * clears all interrupts, performing a PHY reset, and performing a link (MAC) 810 * reset. 811 **/ 812 s32 ixgbe_reset_hw_rev_0_82598(struct ixgbe_hw *hw) 813 { 814 s32 status = IXGBE_SUCCESS; 815 u32 ctrl; 816 u32 gheccr; 817 u32 autoc; 818 u32 i; 819 u32 resets; 820 821 /* Call adapter stop to disable tx/rx and clear interrupts */ 822 hw->mac.ops.stop_adapter(hw); 823 824 /* Reset PHY */ 825 hw->phy.ops.reset(hw); 826 827 for (resets = 0; resets < 10; resets++) { 828 /* 829 * Prevent the PCI-E bus from from hanging by disabling PCI-E 830 * master access and verify no pending requests before reset 831 */ 832 if (ixgbe_disable_pcie_master(hw) != IXGBE_SUCCESS) { 833 status = IXGBE_ERR_MASTER_REQUESTS_PENDING; 834 DEBUGOUT("PCI-E Master disable polling has failed.\n"); 835 } 836 837 /* 838 * Issue global reset to the MAC. This needs to be a SW reset. 839 * If link reset is used, it might reset the MAC when mng is 840 * using it. 841 */ 842 ctrl = IXGBE_READ_REG(hw, IXGBE_CTRL); 843 IXGBE_WRITE_REG(hw, IXGBE_CTRL, (ctrl | IXGBE_CTRL_RST)); 844 IXGBE_WRITE_FLUSH(hw); 845 846 /* 847 * Poll for reset bit to self-clear indicating reset is 848 * complete 849 */ 850 for (i = 0; i < 10; i++) { 851 usec_delay(1); 852 ctrl = IXGBE_READ_REG(hw, IXGBE_CTRL); 853 if (!(ctrl & IXGBE_CTRL_RST)) 854 break; 855 } 856 if (ctrl & IXGBE_CTRL_RST) { 857 status = IXGBE_ERR_RESET_FAILED; 858 DEBUGOUT("Reset polling failed to complete.\n"); 859 } 860 } 861 862 msec_delay(50); 863 864 gheccr = IXGBE_READ_REG(hw, IXGBE_GHECCR); 865 gheccr &= ~((1 << 21) | (1 << 18) | (1 << 9) | (1 << 6)); 866 IXGBE_WRITE_REG(hw, IXGBE_GHECCR, gheccr); 867 868 /* 869 * AUTOC register which stores link settings gets cleared 870 * and reloaded from EEPROM after reset. We need to restore 871 * our stored value from init in case SW changed the attach 872 * type or speed. If this is the first time and link settings 873 * have not been stored, store default settings from AUTOC. 874 */ 875 autoc = IXGBE_READ_REG(hw, IXGBE_AUTOC); 876 if (hw->mac.link_settings_loaded) { 877 autoc &= ~(IXGBE_AUTOC_LMS_ATTACH_TYPE); 878 autoc &= ~(IXGBE_AUTOC_LMS_MASK); 879 autoc |= hw->mac.link_attach_type; 880 autoc |= hw->mac.link_mode_select; 881 IXGBE_WRITE_REG(hw, IXGBE_AUTOC, autoc); 882 } else { 883 hw->mac.link_attach_type = 884 (autoc & IXGBE_AUTOC_LMS_ATTACH_TYPE); 885 hw->mac.link_mode_select = (autoc & IXGBE_AUTOC_LMS_MASK); 886 hw->mac.link_settings_loaded = TRUE; 887 } 888 889 /* Store the permanent mac address */ 890 hw->mac.ops.get_mac_addr(hw, hw->mac.perm_addr); 891 892 return status; 893 } 894 895 #endif /* NO_A0_SUPPORT */ 896 /** 897 * ixgbe_reset_hw_82598 - Performs hardware reset 898 * @hw: pointer to hardware structure 899 * 900 * Resets the hardware by resetting the transmit and receive units, masks and 901 * clears all interrupts, performing a PHY reset, and performing a link (MAC) 902 * reset. 903 **/ 904 s32 ixgbe_reset_hw_82598(struct ixgbe_hw *hw) 905 { 906 s32 status = IXGBE_SUCCESS; 907 u32 ctrl; 908 u32 gheccr; 909 u32 i; 910 u32 autoc; 911 u8 analog_val; 912 913 /* Call adapter stop to disable tx/rx and clear interrupts */ 914 hw->mac.ops.stop_adapter(hw); 915 916 /* 917 * Power up the Atlas Tx lanes if they are currently powered down. 918 * Atlas Tx lanes are powered down for MAC loopback tests, but 919 * they are not automatically restored on reset. 920 */ 921 hw->mac.ops.read_analog_reg8(hw, IXGBE_ATLAS_PDN_LPBK, &analog_val); 922 if (analog_val & IXGBE_ATLAS_PDN_TX_REG_EN) { 923 /* Enable Tx Atlas so packets can be transmitted again */ 924 hw->mac.ops.read_analog_reg8(hw, IXGBE_ATLAS_PDN_LPBK, 925 &analog_val); 926 analog_val &= ~IXGBE_ATLAS_PDN_TX_REG_EN; 927 hw->mac.ops.write_analog_reg8(hw, IXGBE_ATLAS_PDN_LPBK, 928 analog_val); 929 930 hw->mac.ops.read_analog_reg8(hw, IXGBE_ATLAS_PDN_10G, 931 &analog_val); 932 analog_val &= ~ IXGBE_ATLAS_PDN_TX_10G_QL_ALL; 933 hw->mac.ops.write_analog_reg8(hw, IXGBE_ATLAS_PDN_10G, 934 analog_val); 935 936 hw->mac.ops.read_analog_reg8(hw, IXGBE_ATLAS_PDN_1G, 937 &analog_val); 938 analog_val &= ~IXGBE_ATLAS_PDN_TX_1G_QL_ALL; 939 hw->mac.ops.write_analog_reg8(hw, IXGBE_ATLAS_PDN_1G, 940 analog_val); 941 942 hw->mac.ops.read_analog_reg8(hw, IXGBE_ATLAS_PDN_AN, 943 &analog_val); 944 analog_val &= ~IXGBE_ATLAS_PDN_TX_AN_QL_ALL; 945 hw->mac.ops.write_analog_reg8(hw, IXGBE_ATLAS_PDN_AN, 946 analog_val); 947 } 948 949 /* Reset PHY */ 950 if (hw->phy.reset_disable == FALSE) 951 hw->phy.ops.reset(hw); 952 953 /* 954 * Prevent the PCI-E bus from from hanging by disabling PCI-E master 955 * access and verify no pending requests before reset 956 */ 957 if (ixgbe_disable_pcie_master(hw) != IXGBE_SUCCESS) { 958 status = IXGBE_ERR_MASTER_REQUESTS_PENDING; 959 DEBUGOUT("PCI-E Master disable polling has failed.\n"); 960 } 961 962 /* 963 * Issue global reset to the MAC. This needs to be a SW reset. 964 * If link reset is used, it might reset the MAC when mng is using it 965 */ 966 ctrl = IXGBE_READ_REG(hw, IXGBE_CTRL); 967 IXGBE_WRITE_REG(hw, IXGBE_CTRL, (ctrl | IXGBE_CTRL_RST)); 968 IXGBE_WRITE_FLUSH(hw); 969 970 /* Poll for reset bit to self-clear indicating reset is complete */ 971 for (i = 0; i < 10; i++) { 972 usec_delay(1); 973 ctrl = IXGBE_READ_REG(hw, IXGBE_CTRL); 974 if (!(ctrl & IXGBE_CTRL_RST)) 975 break; 976 } 977 if (ctrl & IXGBE_CTRL_RST) { 978 status = IXGBE_ERR_RESET_FAILED; 979 DEBUGOUT("Reset polling failed to complete.\n"); 980 } 981 982 msec_delay(50); 983 984 gheccr = IXGBE_READ_REG(hw, IXGBE_GHECCR); 985 gheccr &= ~((1 << 21) | (1 << 18) | (1 << 9) | (1 << 6)); 986 IXGBE_WRITE_REG(hw, IXGBE_GHECCR, gheccr); 987 988 /* 989 * AUTOC register which stores link settings gets cleared 990 * and reloaded from EEPROM after reset. We need to restore 991 * our stored value from init in case SW changed the attach 992 * type or speed. If this is the first time and link settings 993 * have not been stored, store default settings from AUTOC. 994 */ 995 autoc = IXGBE_READ_REG(hw, IXGBE_AUTOC); 996 if (hw->mac.link_settings_loaded) { 997 autoc &= ~(IXGBE_AUTOC_LMS_ATTACH_TYPE); 998 autoc &= ~(IXGBE_AUTOC_LMS_MASK); 999 autoc |= hw->mac.link_attach_type; 1000 autoc |= hw->mac.link_mode_select; 1001 IXGBE_WRITE_REG(hw, IXGBE_AUTOC, autoc); 1002 } else { 1003 hw->mac.link_attach_type = 1004 (autoc & IXGBE_AUTOC_LMS_ATTACH_TYPE); 1005 hw->mac.link_mode_select = (autoc & IXGBE_AUTOC_LMS_MASK); 1006 hw->mac.link_settings_loaded = TRUE; 1007 } 1008 1009 /* Store the permanent mac address */ 1010 hw->mac.ops.get_mac_addr(hw, hw->mac.perm_addr); 1011 1012 return status; 1013 } 1014 1015 /** 1016 * ixgbe_set_vmdq_82598 - Associate a VMDq set index with a rx address 1017 * @hw: pointer to hardware struct 1018 * @rar: receive address register index to associate with a VMDq index 1019 * @vmdq: VMDq set index 1020 **/ 1021 s32 ixgbe_set_vmdq_82598(struct ixgbe_hw *hw, u32 rar, u32 vmdq) 1022 { 1023 u32 rar_high; 1024 1025 rar_high = IXGBE_READ_REG(hw, IXGBE_RAH(rar)); 1026 rar_high &= ~IXGBE_RAH_VIND_MASK; 1027 rar_high |= ((vmdq << IXGBE_RAH_VIND_SHIFT) & IXGBE_RAH_VIND_MASK); 1028 IXGBE_WRITE_REG(hw, IXGBE_RAH(rar), rar_high); 1029 return IXGBE_SUCCESS; 1030 } 1031 1032 /** 1033 * ixgbe_clear_vmdq_82598 - Disassociate a VMDq set index from an rx address 1034 * @hw: pointer to hardware struct 1035 * @rar: receive address register index to associate with a VMDq index 1036 * @vmdq: VMDq clear index (not used in 82598, but elsewhere) 1037 **/ 1038 s32 ixgbe_clear_vmdq_82598(struct ixgbe_hw *hw, u32 rar, u32 vmdq) 1039 { 1040 u32 rar_high; 1041 u32 rar_entries = hw->mac.num_rar_entries; 1042 1043 UNREFERENCED_PARAMETER(vmdq); 1044 1045 if (rar < rar_entries) { 1046 rar_high = IXGBE_READ_REG(hw, IXGBE_RAH(rar)); 1047 if (rar_high & IXGBE_RAH_VIND_MASK) { 1048 rar_high &= ~IXGBE_RAH_VIND_MASK; 1049 IXGBE_WRITE_REG(hw, IXGBE_RAH(rar), rar_high); 1050 } 1051 } else { 1052 DEBUGOUT1("RAR index %d is out of range.\n", rar); 1053 } 1054 1055 return IXGBE_SUCCESS; 1056 } 1057 1058 /** 1059 * ixgbe_set_vfta_82598 - Set VLAN filter table 1060 * @hw: pointer to hardware structure 1061 * @vlan: VLAN id to write to VLAN filter 1062 * @vind: VMDq output index that maps queue to VLAN id in VFTA 1063 * @vlan_on: boolean flag to turn on/off VLAN in VFTA 1064 * 1065 * Turn on/off specified VLAN in the VLAN filter table. 1066 **/ 1067 s32 ixgbe_set_vfta_82598(struct ixgbe_hw *hw, u32 vlan, u32 vind, 1068 bool vlan_on) 1069 { 1070 u32 regindex; 1071 u32 bitindex; 1072 u32 bits; 1073 u32 vftabyte; 1074 1075 if (vlan < 1 || vlan > 4095) 1076 return IXGBE_ERR_PARAM; 1077 1078 /* Determine 32-bit word position in array */ 1079 regindex = (vlan >> 5) & 0x7F; /* upper seven bits */ 1080 1081 /* Determine the location of the (VMD) queue index */ 1082 vftabyte = ((vlan >> 3) & 0x03); /* bits (4:3) indicating byte array */ 1083 bitindex = (vlan & 0x7) << 2; /* lower 3 bits indicate nibble */ 1084 1085 /* Set the nibble for VMD queue index */ 1086 bits = IXGBE_READ_REG(hw, IXGBE_VFTAVIND(vftabyte, regindex)); 1087 bits &= (~(0x0F << bitindex)); 1088 bits |= (vind << bitindex); 1089 IXGBE_WRITE_REG(hw, IXGBE_VFTAVIND(vftabyte, regindex), bits); 1090 1091 /* Determine the location of the bit for this VLAN id */ 1092 bitindex = vlan & 0x1F; /* lower five bits */ 1093 1094 bits = IXGBE_READ_REG(hw, IXGBE_VFTA(regindex)); 1095 if (vlan_on) 1096 /* Turn on this VLAN id */ 1097 bits |= (1 << bitindex); 1098 else 1099 /* Turn off this VLAN id */ 1100 bits &= ~(1 << bitindex); 1101 IXGBE_WRITE_REG(hw, IXGBE_VFTA(regindex), bits); 1102 1103 return IXGBE_SUCCESS; 1104 } 1105 1106 /** 1107 * ixgbe_clear_vfta_82598 - Clear VLAN filter table 1108 * @hw: pointer to hardware structure 1109 * 1110 * Clears the VLAN filer table, and the VMDq index associated with the filter 1111 **/ 1112 s32 ixgbe_clear_vfta_82598(struct ixgbe_hw *hw) 1113 { 1114 u32 offset; 1115 u32 vlanbyte; 1116 1117 for (offset = 0; offset < hw->mac.vft_size; offset++) 1118 IXGBE_WRITE_REG(hw, IXGBE_VFTA(offset), 0); 1119 1120 for (vlanbyte = 0; vlanbyte < 4; vlanbyte++) 1121 for (offset = 0; offset < hw->mac.vft_size; offset++) 1122 IXGBE_WRITE_REG(hw, IXGBE_VFTAVIND(vlanbyte, offset), 1123 0); 1124 1125 return IXGBE_SUCCESS; 1126 } 1127 1128 /** 1129 * ixgbe_blink_led_start_82598 - Blink LED based on index. 1130 * @hw: pointer to hardware structure 1131 * @index: led number to blink 1132 **/ 1133 s32 ixgbe_blink_led_start_82598(struct ixgbe_hw *hw, u32 index) 1134 { 1135 ixgbe_link_speed speed = 0; 1136 bool link_up = 0; 1137 u32 autoc_reg = IXGBE_READ_REG(hw, IXGBE_AUTOC); 1138 u32 led_reg = IXGBE_READ_REG(hw, IXGBE_LEDCTL); 1139 1140 /* 1141 * Link must be up to auto-blink the LEDs on the 82598EB MAC; 1142 * force it if link is down. 1143 */ 1144 hw->mac.ops.check_link(hw, &speed, &link_up, FALSE); 1145 1146 if (!link_up) { 1147 autoc_reg |= IXGBE_AUTOC_FLU; 1148 IXGBE_WRITE_REG(hw, IXGBE_AUTOC, autoc_reg); 1149 msec_delay(10); 1150 } 1151 1152 led_reg &= ~IXGBE_LED_MODE_MASK(index); 1153 led_reg |= IXGBE_LED_BLINK(index); 1154 IXGBE_WRITE_REG(hw, IXGBE_LEDCTL, led_reg); 1155 IXGBE_WRITE_FLUSH(hw); 1156 1157 return IXGBE_SUCCESS; 1158 } 1159 1160 /** 1161 * ixgbe_blink_led_stop_82598 - Stop blinking LED based on index. 1162 * @hw: pointer to hardware structure 1163 * @index: led number to stop blinking 1164 **/ 1165 s32 ixgbe_blink_led_stop_82598(struct ixgbe_hw *hw, u32 index) 1166 { 1167 u32 autoc_reg = IXGBE_READ_REG(hw, IXGBE_AUTOC); 1168 u32 led_reg = IXGBE_READ_REG(hw, IXGBE_LEDCTL); 1169 1170 autoc_reg &= ~IXGBE_AUTOC_FLU; 1171 IXGBE_WRITE_REG(hw, IXGBE_AUTOC, autoc_reg); 1172 1173 led_reg &= ~IXGBE_LED_MODE_MASK(index); 1174 led_reg &= ~IXGBE_LED_BLINK(index); 1175 IXGBE_WRITE_REG(hw, IXGBE_LEDCTL, led_reg); 1176 IXGBE_WRITE_FLUSH(hw); 1177 1178 return IXGBE_SUCCESS; 1179 } 1180