1 /****************************************************************************** 2 3 Copyright (c) 2001-2009, Intel Corporation 4 All rights reserved. 5 6 Redistribution and use in source and binary forms, with or without 7 modification, are permitted provided that the following conditions are met: 8 9 1. Redistributions of source code must retain the above copyright notice, 10 this list of conditions and the following disclaimer. 11 12 2. Redistributions in binary form must reproduce the above copyright 13 notice, this list of conditions and the following disclaimer in the 14 documentation and/or other materials provided with the distribution. 15 16 3. Neither the name of the Intel Corporation nor the names of its 17 contributors may be used to endorse or promote products derived from 18 this software without specific prior written permission. 19 20 THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 21 AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 22 IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 23 ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE 24 LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 25 CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 26 SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 27 INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 28 CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 29 ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 30 POSSIBILITY OF SUCH DAMAGE. 31 32 ******************************************************************************/ 33 /*$FreeBSD$*/ 34 35 #include "ixgbe_type.h" 36 #include "ixgbe_api.h" 37 #include "ixgbe_common.h" 38 #include "ixgbe_phy.h" 39 40 u32 ixgbe_get_pcie_msix_count_82598(struct ixgbe_hw *hw); 41 s32 ixgbe_init_ops_82598(struct ixgbe_hw *hw); 42 static s32 ixgbe_get_link_capabilities_82598(struct ixgbe_hw *hw, 43 ixgbe_link_speed *speed, 44 bool *autoneg); 45 static enum ixgbe_media_type ixgbe_get_media_type_82598(struct ixgbe_hw *hw); 46 s32 ixgbe_fc_enable_82598(struct ixgbe_hw *hw, s32 packetbuf_num); 47 static s32 ixgbe_setup_mac_link_82598(struct ixgbe_hw *hw); 48 static s32 ixgbe_check_mac_link_82598(struct ixgbe_hw *hw, 49 ixgbe_link_speed *speed, bool *link_up, 50 bool link_up_wait_to_complete); 51 static s32 ixgbe_setup_mac_link_speed_82598(struct ixgbe_hw *hw, 52 ixgbe_link_speed speed, 53 bool autoneg, 54 bool autoneg_wait_to_complete); 55 static s32 ixgbe_setup_copper_link_82598(struct ixgbe_hw *hw); 56 static s32 ixgbe_setup_copper_link_speed_82598(struct ixgbe_hw *hw, 57 ixgbe_link_speed speed, 58 bool autoneg, 59 bool autoneg_wait_to_complete); 60 static s32 ixgbe_reset_hw_82598(struct ixgbe_hw *hw); 61 s32 ixgbe_set_vmdq_82598(struct ixgbe_hw *hw, u32 rar, u32 vmdq); 62 static s32 ixgbe_clear_vmdq_82598(struct ixgbe_hw *hw, u32 rar, u32 vmdq); 63 s32 ixgbe_set_vfta_82598(struct ixgbe_hw *hw, u32 vlan, 64 u32 vind, bool vlan_on); 65 static s32 ixgbe_clear_vfta_82598(struct ixgbe_hw *hw); 66 s32 ixgbe_read_analog_reg8_82598(struct ixgbe_hw *hw, u32 reg, u8 *val); 67 s32 ixgbe_write_analog_reg8_82598(struct ixgbe_hw *hw, u32 reg, u8 val); 68 s32 ixgbe_read_i2c_eeprom_82598(struct ixgbe_hw *hw, u8 byte_offset, 69 u8 *eeprom_data); 70 u32 ixgbe_get_supported_physical_layer_82598(struct ixgbe_hw *hw); 71 s32 ixgbe_init_phy_ops_82598(struct ixgbe_hw *hw); 72 void ixgbe_set_lan_id_multi_port_pcie_82598(struct ixgbe_hw *hw); 73 74 75 /** 76 * ixgbe_get_pcie_msix_count_82598 - Gets MSI-X vector count 77 * @hw: pointer to hardware structure 78 * 79 * Read PCIe configuration space, and get the MSI-X vector count from 80 * the capabilities table. 81 **/ 82 u32 ixgbe_get_pcie_msix_count_82598(struct ixgbe_hw *hw) 83 { 84 u32 msix_count = 18; 85 86 if (hw->mac.msix_vectors_from_pcie) { 87 msix_count = IXGBE_READ_PCIE_WORD(hw, 88 IXGBE_PCIE_MSIX_82598_CAPS); 89 msix_count &= IXGBE_PCIE_MSIX_TBL_SZ_MASK; 90 91 /* MSI-X count is zero-based in HW, so increment to give 92 * proper value */ 93 msix_count++; 94 } 95 return msix_count; 96 } 97 98 /** 99 * ixgbe_init_ops_82598 - Inits func ptrs and MAC type 100 * @hw: pointer to hardware structure 101 * 102 * Initialize the function pointers and assign the MAC type for 82598. 103 * Does not touch the hardware. 104 **/ 105 s32 ixgbe_init_ops_82598(struct ixgbe_hw *hw) 106 { 107 struct ixgbe_mac_info *mac = &hw->mac; 108 struct ixgbe_phy_info *phy = &hw->phy; 109 s32 ret_val; 110 111 ret_val = ixgbe_init_phy_ops_generic(hw); 112 ret_val = ixgbe_init_ops_generic(hw); 113 114 /* PHY */ 115 phy->ops.init = &ixgbe_init_phy_ops_82598; 116 117 /* MAC */ 118 mac->ops.reset_hw = &ixgbe_reset_hw_82598; 119 mac->ops.get_media_type = &ixgbe_get_media_type_82598; 120 mac->ops.get_supported_physical_layer = 121 &ixgbe_get_supported_physical_layer_82598; 122 mac->ops.read_analog_reg8 = &ixgbe_read_analog_reg8_82598; 123 mac->ops.write_analog_reg8 = &ixgbe_write_analog_reg8_82598; 124 mac->ops.set_lan_id = &ixgbe_set_lan_id_multi_port_pcie_82598; 125 126 /* RAR, Multicast, VLAN */ 127 mac->ops.set_vmdq = &ixgbe_set_vmdq_82598; 128 mac->ops.clear_vmdq = &ixgbe_clear_vmdq_82598; 129 mac->ops.set_vfta = &ixgbe_set_vfta_82598; 130 mac->ops.clear_vfta = &ixgbe_clear_vfta_82598; 131 132 /* Flow Control */ 133 mac->ops.fc_enable = &ixgbe_fc_enable_82598; 134 135 mac->mcft_size = 128; 136 mac->vft_size = 128; 137 mac->num_rar_entries = 16; 138 mac->max_tx_queues = 32; 139 mac->max_rx_queues = 64; 140 mac->max_msix_vectors = ixgbe_get_pcie_msix_count_82598(hw); 141 142 /* SFP+ Module */ 143 phy->ops.read_i2c_eeprom = &ixgbe_read_i2c_eeprom_82598; 144 145 /* Link */ 146 mac->ops.check_link = &ixgbe_check_mac_link_82598; 147 mac->ops.setup_link = &ixgbe_setup_mac_link_82598; 148 mac->ops.setup_link_speed = &ixgbe_setup_mac_link_speed_82598; 149 mac->ops.get_link_capabilities = 150 &ixgbe_get_link_capabilities_82598; 151 152 return ret_val; 153 } 154 155 /** 156 * ixgbe_init_phy_ops_82598 - PHY/SFP specific init 157 * @hw: pointer to hardware structure 158 * 159 * Initialize any function pointers that were not able to be 160 * set during init_shared_code because the PHY/SFP type was 161 * not known. Perform the SFP init if necessary. 162 * 163 **/ 164 s32 ixgbe_init_phy_ops_82598(struct ixgbe_hw *hw) 165 { 166 struct ixgbe_mac_info *mac = &hw->mac; 167 struct ixgbe_phy_info *phy = &hw->phy; 168 s32 ret_val = IXGBE_SUCCESS; 169 u16 list_offset, data_offset; 170 171 172 /* Identify the PHY */ 173 phy->ops.identify(hw); 174 175 /* Overwrite the link function pointers if copper PHY */ 176 if (mac->ops.get_media_type(hw) == ixgbe_media_type_copper) { 177 mac->ops.setup_link = &ixgbe_setup_copper_link_82598; 178 mac->ops.setup_link_speed = 179 &ixgbe_setup_copper_link_speed_82598; 180 mac->ops.get_link_capabilities = 181 &ixgbe_get_copper_link_capabilities_generic; 182 } 183 184 switch (hw->phy.type) { 185 case ixgbe_phy_tn: 186 phy->ops.check_link = &ixgbe_check_phy_link_tnx; 187 phy->ops.get_firmware_version = 188 &ixgbe_get_phy_firmware_version_tnx; 189 break; 190 case ixgbe_phy_aq: 191 phy->ops.get_firmware_version = 192 &ixgbe_get_phy_firmware_version_aq; 193 break; 194 case ixgbe_phy_nl: 195 phy->ops.reset = &ixgbe_reset_phy_nl; 196 197 /* Call SFP+ identify routine to get the SFP+ module type */ 198 ret_val = phy->ops.identify_sfp(hw); 199 if (ret_val != IXGBE_SUCCESS) 200 goto out; 201 else if (hw->phy.sfp_type == ixgbe_sfp_type_unknown) { 202 ret_val = IXGBE_ERR_SFP_NOT_SUPPORTED; 203 goto out; 204 } 205 206 /* Check to see if SFP+ module is supported */ 207 ret_val = ixgbe_get_sfp_init_sequence_offsets(hw, 208 &list_offset, 209 &data_offset); 210 if (ret_val != IXGBE_SUCCESS) { 211 ret_val = IXGBE_ERR_SFP_NOT_SUPPORTED; 212 goto out; 213 } 214 break; 215 default: 216 break; 217 } 218 219 out: 220 return ret_val; 221 } 222 223 /** 224 * ixgbe_get_link_capabilities_82598 - Determines link capabilities 225 * @hw: pointer to hardware structure 226 * @speed: pointer to link speed 227 * @autoneg: boolean auto-negotiation value 228 * 229 * Determines the link capabilities by reading the AUTOC register. 230 **/ 231 static s32 ixgbe_get_link_capabilities_82598(struct ixgbe_hw *hw, 232 ixgbe_link_speed *speed, 233 bool *autoneg) 234 { 235 s32 status = IXGBE_SUCCESS; 236 u32 autoc = 0; 237 238 /* 239 * Determine link capabilities based on the stored value of AUTOC, 240 * which represents EEPROM defaults. If AUTOC value has not been 241 * stored, use the current register value. 242 */ 243 if (hw->mac.orig_link_settings_stored) 244 autoc = hw->mac.orig_autoc; 245 else 246 autoc = IXGBE_READ_REG(hw, IXGBE_AUTOC); 247 248 switch (autoc & IXGBE_AUTOC_LMS_MASK) { 249 case IXGBE_AUTOC_LMS_1G_LINK_NO_AN: 250 *speed = IXGBE_LINK_SPEED_1GB_FULL; 251 *autoneg = FALSE; 252 break; 253 254 case IXGBE_AUTOC_LMS_10G_LINK_NO_AN: 255 *speed = IXGBE_LINK_SPEED_10GB_FULL; 256 *autoneg = FALSE; 257 break; 258 259 case IXGBE_AUTOC_LMS_1G_AN: 260 *speed = IXGBE_LINK_SPEED_1GB_FULL; 261 *autoneg = TRUE; 262 break; 263 264 case IXGBE_AUTOC_LMS_KX4_AN: 265 case IXGBE_AUTOC_LMS_KX4_AN_1G_AN: 266 *speed = IXGBE_LINK_SPEED_UNKNOWN; 267 if (autoc & IXGBE_AUTOC_KX4_SUPP) 268 *speed |= IXGBE_LINK_SPEED_10GB_FULL; 269 if (autoc & IXGBE_AUTOC_KX_SUPP) 270 *speed |= IXGBE_LINK_SPEED_1GB_FULL; 271 *autoneg = TRUE; 272 break; 273 274 default: 275 status = IXGBE_ERR_LINK_SETUP; 276 break; 277 } 278 279 return status; 280 } 281 282 /** 283 * ixgbe_get_media_type_82598 - Determines media type 284 * @hw: pointer to hardware structure 285 * 286 * Returns the media type (fiber, copper, backplane) 287 **/ 288 static enum ixgbe_media_type ixgbe_get_media_type_82598(struct ixgbe_hw *hw) 289 { 290 enum ixgbe_media_type media_type; 291 292 /* Detect if there is a copper PHY attached. */ 293 if (hw->phy.type == ixgbe_phy_cu_unknown || 294 hw->phy.type == ixgbe_phy_tn || 295 hw->phy.type == ixgbe_phy_aq) { 296 media_type = ixgbe_media_type_copper; 297 goto out; 298 } 299 300 /* Media type for I82598 is based on device ID */ 301 switch (hw->device_id) { 302 case IXGBE_DEV_ID_82598: 303 case IXGBE_DEV_ID_82598_BX: 304 /* Default device ID is mezzanine card KX/KX4 */ 305 media_type = ixgbe_media_type_backplane; 306 break; 307 case IXGBE_DEV_ID_82598AF_DUAL_PORT: 308 case IXGBE_DEV_ID_82598AF_SINGLE_PORT: 309 case IXGBE_DEV_ID_82598EB_CX4: 310 case IXGBE_DEV_ID_82598_CX4_DUAL_PORT: 311 case IXGBE_DEV_ID_82598_DA_DUAL_PORT: 312 case IXGBE_DEV_ID_82598_SR_DUAL_PORT_EM: 313 case IXGBE_DEV_ID_82598EB_XF_LR: 314 case IXGBE_DEV_ID_82598EB_SFP_LOM: 315 media_type = ixgbe_media_type_fiber; 316 break; 317 case IXGBE_DEV_ID_82598AT: 318 media_type = ixgbe_media_type_copper; 319 break; 320 default: 321 media_type = ixgbe_media_type_unknown; 322 break; 323 } 324 out: 325 return media_type; 326 } 327 328 /** 329 * ixgbe_fc_enable_82598 - Enable flow control 330 * @hw: pointer to hardware structure 331 * @packetbuf_num: packet buffer number (0-7) 332 * 333 * Enable flow control according to the current settings. 334 **/ 335 s32 ixgbe_fc_enable_82598(struct ixgbe_hw *hw, s32 packetbuf_num) 336 { 337 s32 ret_val = IXGBE_SUCCESS; 338 u32 fctrl_reg; 339 u32 rmcs_reg; 340 u32 reg; 341 342 DEBUGFUNC("ixgbe_fc_enable_82598"); 343 344 /* Negotiate the fc mode to use */ 345 ret_val = ixgbe_fc_autoneg(hw); 346 if (ret_val) 347 goto out; 348 349 /* Disable any previous flow control settings */ 350 fctrl_reg = IXGBE_READ_REG(hw, IXGBE_FCTRL); 351 fctrl_reg &= ~(IXGBE_FCTRL_RFCE | IXGBE_FCTRL_RPFCE); 352 353 rmcs_reg = IXGBE_READ_REG(hw, IXGBE_RMCS); 354 rmcs_reg &= ~(IXGBE_RMCS_TFCE_PRIORITY | IXGBE_RMCS_TFCE_802_3X); 355 356 /* 357 * The possible values of fc.current_mode are: 358 * 0: Flow control is completely disabled 359 * 1: Rx flow control is enabled (we can receive pause frames, 360 * but not send pause frames). 361 * 2: Tx flow control is enabled (we can send pause frames but 362 * we do not support receiving pause frames). 363 * 3: Both Rx and Tx flow control (symmetric) are enabled. 364 * other: Invalid. 365 */ 366 switch (hw->fc.current_mode) { 367 case ixgbe_fc_none: 368 /* Flow control is disabled by software override or autoneg. 369 * The code below will actually disable it in the HW. 370 */ 371 break; 372 case ixgbe_fc_rx_pause: 373 /* 374 * Rx Flow control is enabled and Tx Flow control is 375 * disabled by software override. Since there really 376 * isn't a way to advertise that we are capable of RX 377 * Pause ONLY, we will advertise that we support both 378 * symmetric and asymmetric Rx PAUSE. Later, we will 379 * disable the adapter's ability to send PAUSE frames. 380 */ 381 fctrl_reg |= IXGBE_FCTRL_RFCE; 382 break; 383 case ixgbe_fc_tx_pause: 384 /* 385 * Tx Flow control is enabled, and Rx Flow control is 386 * disabled by software override. 387 */ 388 rmcs_reg |= IXGBE_RMCS_TFCE_802_3X; 389 break; 390 case ixgbe_fc_full: 391 /* Flow control (both Rx and Tx) is enabled by SW override. */ 392 fctrl_reg |= IXGBE_FCTRL_RFCE; 393 rmcs_reg |= IXGBE_RMCS_TFCE_802_3X; 394 break; 395 default: 396 DEBUGOUT("Flow control param set incorrectly\n"); 397 ret_val = -IXGBE_ERR_CONFIG; 398 goto out; 399 break; 400 } 401 402 /* Set 802.3x based flow control settings. */ 403 fctrl_reg |= IXGBE_FCTRL_DPF; 404 IXGBE_WRITE_REG(hw, IXGBE_FCTRL, fctrl_reg); 405 IXGBE_WRITE_REG(hw, IXGBE_RMCS, rmcs_reg); 406 407 /* Set up and enable Rx high/low water mark thresholds, enable XON. */ 408 if (hw->fc.current_mode & ixgbe_fc_tx_pause) { 409 if (hw->fc.send_xon) { 410 IXGBE_WRITE_REG(hw, IXGBE_FCRTL(packetbuf_num), 411 (hw->fc.low_water | IXGBE_FCRTL_XONE)); 412 } else { 413 IXGBE_WRITE_REG(hw, IXGBE_FCRTL(packetbuf_num), 414 hw->fc.low_water); 415 } 416 417 IXGBE_WRITE_REG(hw, IXGBE_FCRTH(packetbuf_num), 418 (hw->fc.high_water | IXGBE_FCRTH_FCEN)); 419 } 420 421 /* Configure pause time (2 TCs per register) */ 422 reg = IXGBE_READ_REG(hw, IXGBE_FCTTV(packetbuf_num / 2)); 423 if ((packetbuf_num & 1) == 0) 424 reg = (reg & 0xFFFF0000) | hw->fc.pause_time; 425 else 426 reg = (reg & 0x0000FFFF) | (hw->fc.pause_time << 16); 427 IXGBE_WRITE_REG(hw, IXGBE_FCTTV(packetbuf_num / 2), reg); 428 429 IXGBE_WRITE_REG(hw, IXGBE_FCRTV, (hw->fc.pause_time >> 1)); 430 431 out: 432 return ret_val; 433 } 434 435 /** 436 * ixgbe_setup_mac_link_82598 - Configures MAC link settings 437 * @hw: pointer to hardware structure 438 * 439 * Configures link settings based on values in the ixgbe_hw struct. 440 * Restarts the link. Performs autonegotiation if needed. 441 **/ 442 static s32 ixgbe_setup_mac_link_82598(struct ixgbe_hw *hw) 443 { 444 u32 autoc_reg; 445 u32 links_reg; 446 u32 i; 447 s32 status = IXGBE_SUCCESS; 448 449 /* Restart link */ 450 autoc_reg = IXGBE_READ_REG(hw, IXGBE_AUTOC); 451 autoc_reg |= IXGBE_AUTOC_AN_RESTART; 452 IXGBE_WRITE_REG(hw, IXGBE_AUTOC, autoc_reg); 453 454 /* Only poll for autoneg to complete if specified to do so */ 455 if (hw->phy.autoneg_wait_to_complete) { 456 if ((autoc_reg & IXGBE_AUTOC_LMS_MASK) == 457 IXGBE_AUTOC_LMS_KX4_AN || 458 (autoc_reg & IXGBE_AUTOC_LMS_MASK) == 459 IXGBE_AUTOC_LMS_KX4_AN_1G_AN) { 460 links_reg = 0; /* Just in case Autoneg time = 0 */ 461 for (i = 0; i < IXGBE_AUTO_NEG_TIME; i++) { 462 links_reg = IXGBE_READ_REG(hw, IXGBE_LINKS); 463 if (links_reg & IXGBE_LINKS_KX_AN_COMP) 464 break; 465 msec_delay(100); 466 } 467 if (!(links_reg & IXGBE_LINKS_KX_AN_COMP)) { 468 status = IXGBE_ERR_AUTONEG_NOT_COMPLETE; 469 DEBUGOUT("Autonegotiation did not complete.\n"); 470 } 471 } 472 } 473 474 /* Add delay to filter out noises during initial link setup */ 475 msec_delay(50); 476 477 return status; 478 } 479 480 /** 481 * ixgbe_check_mac_link_82598 - Get link/speed status 482 * @hw: pointer to hardware structure 483 * @speed: pointer to link speed 484 * @link_up: TRUE is link is up, FALSE otherwise 485 * @link_up_wait_to_complete: bool used to wait for link up or not 486 * 487 * Reads the links register to determine if link is up and the current speed 488 **/ 489 static s32 ixgbe_check_mac_link_82598(struct ixgbe_hw *hw, 490 ixgbe_link_speed *speed, bool *link_up, 491 bool link_up_wait_to_complete) 492 { 493 u32 links_reg; 494 u32 i; 495 u16 link_reg, adapt_comp_reg; 496 497 /* 498 * SERDES PHY requires us to read link status from undocumented 499 * register 0xC79F. Bit 0 set indicates link is up/ready; clear 500 * indicates link down. OxC00C is read to check that the XAUI lanes 501 * are active. Bit 0 clear indicates active; set indicates inactive. 502 */ 503 if (hw->phy.type == ixgbe_phy_nl) { 504 hw->phy.ops.read_reg(hw, 0xC79F, IXGBE_TWINAX_DEV, &link_reg); 505 hw->phy.ops.read_reg(hw, 0xC79F, IXGBE_TWINAX_DEV, &link_reg); 506 hw->phy.ops.read_reg(hw, 0xC00C, IXGBE_TWINAX_DEV, 507 &adapt_comp_reg); 508 if (link_up_wait_to_complete) { 509 for (i = 0; i < IXGBE_LINK_UP_TIME; i++) { 510 if ((link_reg & 1) && 511 ((adapt_comp_reg & 1) == 0)) { 512 *link_up = TRUE; 513 break; 514 } else { 515 *link_up = FALSE; 516 } 517 msec_delay(100); 518 hw->phy.ops.read_reg(hw, 0xC79F, 519 IXGBE_TWINAX_DEV, 520 &link_reg); 521 hw->phy.ops.read_reg(hw, 0xC00C, 522 IXGBE_TWINAX_DEV, 523 &adapt_comp_reg); 524 } 525 } else { 526 if ((link_reg & 1) && 527 ((adapt_comp_reg & 1) == 0)) 528 *link_up = TRUE; 529 else 530 *link_up = FALSE; 531 } 532 533 if (*link_up == FALSE) 534 goto out; 535 } 536 537 links_reg = IXGBE_READ_REG(hw, IXGBE_LINKS); 538 if (link_up_wait_to_complete) { 539 for (i = 0; i < IXGBE_LINK_UP_TIME; i++) { 540 if (links_reg & IXGBE_LINKS_UP) { 541 *link_up = TRUE; 542 break; 543 } else { 544 *link_up = FALSE; 545 } 546 msec_delay(100); 547 links_reg = IXGBE_READ_REG(hw, IXGBE_LINKS); 548 } 549 } else { 550 if (links_reg & IXGBE_LINKS_UP) 551 *link_up = TRUE; 552 else 553 *link_up = FALSE; 554 } 555 556 if (links_reg & IXGBE_LINKS_SPEED) 557 *speed = IXGBE_LINK_SPEED_10GB_FULL; 558 else 559 *speed = IXGBE_LINK_SPEED_1GB_FULL; 560 561 /* if link is down, zero out the current_mode */ 562 if (*link_up == FALSE) { 563 hw->fc.current_mode = ixgbe_fc_none; 564 hw->fc.fc_was_autonegged = FALSE; 565 } 566 out: 567 return IXGBE_SUCCESS; 568 } 569 570 /** 571 * ixgbe_setup_mac_link_speed_82598 - Set MAC link speed 572 * @hw: pointer to hardware structure 573 * @speed: new link speed 574 * @autoneg: TRUE if autonegotiation enabled 575 * @autoneg_wait_to_complete: TRUE when waiting for completion is needed 576 * 577 * Set the link speed in the AUTOC register and restarts link. 578 **/ 579 static s32 ixgbe_setup_mac_link_speed_82598(struct ixgbe_hw *hw, 580 ixgbe_link_speed speed, bool autoneg, 581 bool autoneg_wait_to_complete) 582 { 583 s32 status = IXGBE_SUCCESS; 584 ixgbe_link_speed link_capabilities = IXGBE_LINK_SPEED_UNKNOWN; 585 u32 curr_autoc = IXGBE_READ_REG(hw, IXGBE_AUTOC); 586 u32 autoc = curr_autoc; 587 u32 link_mode = autoc & IXGBE_AUTOC_LMS_MASK; 588 589 /* Check to see if speed passed in is supported. */ 590 ixgbe_get_link_capabilities(hw, &link_capabilities, &autoneg); 591 speed &= link_capabilities; 592 593 if (speed == IXGBE_LINK_SPEED_UNKNOWN) 594 status = IXGBE_ERR_LINK_SETUP; 595 596 /* Set KX4/KX support according to speed requested */ 597 else if (link_mode == IXGBE_AUTOC_LMS_KX4_AN || 598 link_mode == IXGBE_AUTOC_LMS_KX4_AN_1G_AN) { 599 autoc &= ~IXGBE_AUTOC_KX4_KX_SUPP_MASK; 600 if (speed & IXGBE_LINK_SPEED_10GB_FULL) 601 autoc |= IXGBE_AUTOC_KX4_SUPP; 602 if (speed & IXGBE_LINK_SPEED_1GB_FULL) 603 autoc |= IXGBE_AUTOC_KX_SUPP; 604 if (autoc != curr_autoc) 605 IXGBE_WRITE_REG(hw, IXGBE_AUTOC, autoc); 606 } 607 608 if (status == IXGBE_SUCCESS) { 609 hw->phy.autoneg_wait_to_complete = autoneg_wait_to_complete; 610 611 /* 612 * Setup and restart the link based on the new values in 613 * ixgbe_hw This will write the AUTOC register based on the new 614 * stored values 615 */ 616 status = ixgbe_setup_mac_link_82598(hw); 617 } 618 619 return status; 620 } 621 622 623 /** 624 * ixgbe_setup_copper_link_82598 - Setup copper link settings 625 * @hw: pointer to hardware structure 626 * 627 * Configures link settings based on values in the ixgbe_hw struct. 628 * Restarts the link. Performs autonegotiation if needed. Restart 629 * phy and wait for autonegotiate to finish. Then synchronize the 630 * MAC and PHY. 631 **/ 632 static s32 ixgbe_setup_copper_link_82598(struct ixgbe_hw *hw) 633 { 634 s32 status; 635 636 /* Restart autonegotiation on PHY */ 637 status = hw->phy.ops.setup_link(hw); 638 639 /* Set up MAC */ 640 ixgbe_setup_mac_link_82598(hw); 641 642 return status; 643 } 644 645 /** 646 * ixgbe_setup_copper_link_speed_82598 - Set the PHY autoneg advertised field 647 * @hw: pointer to hardware structure 648 * @speed: new link speed 649 * @autoneg: TRUE if autonegotiation enabled 650 * @autoneg_wait_to_complete: TRUE if waiting is needed to complete 651 * 652 * Sets the link speed in the AUTOC register in the MAC and restarts link. 653 **/ 654 static s32 ixgbe_setup_copper_link_speed_82598(struct ixgbe_hw *hw, 655 ixgbe_link_speed speed, 656 bool autoneg, 657 bool autoneg_wait_to_complete) 658 { 659 s32 status; 660 661 /* Setup the PHY according to input speed */ 662 status = hw->phy.ops.setup_link_speed(hw, speed, autoneg, 663 autoneg_wait_to_complete); 664 /* Set up MAC */ 665 ixgbe_setup_mac_link_82598(hw); 666 667 return status; 668 } 669 670 /** 671 * ixgbe_reset_hw_82598 - Performs hardware reset 672 * @hw: pointer to hardware structure 673 * 674 * Resets the hardware by resetting the transmit and receive units, masks and 675 * clears all interrupts, performing a PHY reset, and performing a link (MAC) 676 * reset. 677 **/ 678 static s32 ixgbe_reset_hw_82598(struct ixgbe_hw *hw) 679 { 680 s32 status = IXGBE_SUCCESS; 681 s32 phy_status = IXGBE_SUCCESS; 682 u32 ctrl; 683 u32 gheccr; 684 u32 i; 685 u32 autoc; 686 u8 analog_val; 687 688 /* Call adapter stop to disable tx/rx and clear interrupts */ 689 hw->mac.ops.stop_adapter(hw); 690 691 /* 692 * Power up the Atlas Tx lanes if they are currently powered down. 693 * Atlas Tx lanes are powered down for MAC loopback tests, but 694 * they are not automatically restored on reset. 695 */ 696 hw->mac.ops.read_analog_reg8(hw, IXGBE_ATLAS_PDN_LPBK, &analog_val); 697 if (analog_val & IXGBE_ATLAS_PDN_TX_REG_EN) { 698 /* Enable Tx Atlas so packets can be transmitted again */ 699 hw->mac.ops.read_analog_reg8(hw, IXGBE_ATLAS_PDN_LPBK, 700 &analog_val); 701 analog_val &= ~IXGBE_ATLAS_PDN_TX_REG_EN; 702 hw->mac.ops.write_analog_reg8(hw, IXGBE_ATLAS_PDN_LPBK, 703 analog_val); 704 705 hw->mac.ops.read_analog_reg8(hw, IXGBE_ATLAS_PDN_10G, 706 &analog_val); 707 analog_val &= ~IXGBE_ATLAS_PDN_TX_10G_QL_ALL; 708 hw->mac.ops.write_analog_reg8(hw, IXGBE_ATLAS_PDN_10G, 709 analog_val); 710 711 hw->mac.ops.read_analog_reg8(hw, IXGBE_ATLAS_PDN_1G, 712 &analog_val); 713 analog_val &= ~IXGBE_ATLAS_PDN_TX_1G_QL_ALL; 714 hw->mac.ops.write_analog_reg8(hw, IXGBE_ATLAS_PDN_1G, 715 analog_val); 716 717 hw->mac.ops.read_analog_reg8(hw, IXGBE_ATLAS_PDN_AN, 718 &analog_val); 719 analog_val &= ~IXGBE_ATLAS_PDN_TX_AN_QL_ALL; 720 hw->mac.ops.write_analog_reg8(hw, IXGBE_ATLAS_PDN_AN, 721 analog_val); 722 } 723 724 /* Reset PHY */ 725 if (hw->phy.reset_disable == FALSE) { 726 /* PHY ops must be identified and initialized prior to reset */ 727 728 /* Init PHY and function pointers, perform SFP setup */ 729 phy_status = hw->phy.ops.init(hw); 730 if (phy_status == IXGBE_ERR_SFP_NOT_SUPPORTED) 731 goto reset_hw_out; 732 else if (phy_status == IXGBE_ERR_SFP_NOT_PRESENT) 733 goto no_phy_reset; 734 735 hw->phy.ops.reset(hw); 736 } 737 738 no_phy_reset: 739 /* 740 * Prevent the PCI-E bus from from hanging by disabling PCI-E master 741 * access and verify no pending requests before reset 742 */ 743 status = ixgbe_disable_pcie_master(hw); 744 if (status != IXGBE_SUCCESS) { 745 status = IXGBE_ERR_MASTER_REQUESTS_PENDING; 746 DEBUGOUT("PCI-E Master disable polling has failed.\n"); 747 } 748 749 /* 750 * Issue global reset to the MAC. This needs to be a SW reset. 751 * If link reset is used, it might reset the MAC when mng is using it 752 */ 753 ctrl = IXGBE_READ_REG(hw, IXGBE_CTRL); 754 IXGBE_WRITE_REG(hw, IXGBE_CTRL, (ctrl | IXGBE_CTRL_RST)); 755 IXGBE_WRITE_FLUSH(hw); 756 757 /* Poll for reset bit to self-clear indicating reset is complete */ 758 for (i = 0; i < 10; i++) { 759 usec_delay(1); 760 ctrl = IXGBE_READ_REG(hw, IXGBE_CTRL); 761 if (!(ctrl & IXGBE_CTRL_RST)) 762 break; 763 } 764 if (ctrl & IXGBE_CTRL_RST) { 765 status = IXGBE_ERR_RESET_FAILED; 766 DEBUGOUT("Reset polling failed to complete.\n"); 767 } 768 769 msec_delay(50); 770 771 gheccr = IXGBE_READ_REG(hw, IXGBE_GHECCR); 772 gheccr &= ~((1 << 21) | (1 << 18) | (1 << 9) | (1 << 6)); 773 IXGBE_WRITE_REG(hw, IXGBE_GHECCR, gheccr); 774 775 /* 776 * Store the original AUTOC value if it has not been 777 * stored off yet. Otherwise restore the stored original 778 * AUTOC value since the reset operation sets back to deaults. 779 */ 780 autoc = IXGBE_READ_REG(hw, IXGBE_AUTOC); 781 if (hw->mac.orig_link_settings_stored == FALSE) { 782 hw->mac.orig_autoc = autoc; 783 hw->mac.orig_link_settings_stored = TRUE; 784 } else if (autoc != hw->mac.orig_autoc) 785 IXGBE_WRITE_REG(hw, IXGBE_AUTOC, hw->mac.orig_autoc); 786 787 /* Store the permanent mac address */ 788 hw->mac.ops.get_mac_addr(hw, hw->mac.perm_addr); 789 790 /* 791 * Store MAC address from RAR0, clear receive address registers, and 792 * clear the multicast table 793 */ 794 hw->mac.ops.init_rx_addrs(hw); 795 796 797 798 reset_hw_out: 799 if (phy_status != IXGBE_SUCCESS) 800 status = phy_status; 801 return status; 802 } 803 804 /** 805 * ixgbe_set_vmdq_82598 - Associate a VMDq set index with a rx address 806 * @hw: pointer to hardware struct 807 * @rar: receive address register index to associate with a VMDq index 808 * @vmdq: VMDq set index 809 **/ 810 s32 ixgbe_set_vmdq_82598(struct ixgbe_hw *hw, u32 rar, u32 vmdq) 811 { 812 u32 rar_high; 813 814 rar_high = IXGBE_READ_REG(hw, IXGBE_RAH(rar)); 815 rar_high &= ~IXGBE_RAH_VIND_MASK; 816 rar_high |= ((vmdq << IXGBE_RAH_VIND_SHIFT) & IXGBE_RAH_VIND_MASK); 817 IXGBE_WRITE_REG(hw, IXGBE_RAH(rar), rar_high); 818 return IXGBE_SUCCESS; 819 } 820 821 /** 822 * ixgbe_clear_vmdq_82598 - Disassociate a VMDq set index from an rx address 823 * @hw: pointer to hardware struct 824 * @rar: receive address register index to associate with a VMDq index 825 * @vmdq: VMDq clear index (not used in 82598, but elsewhere) 826 **/ 827 static s32 ixgbe_clear_vmdq_82598(struct ixgbe_hw *hw, u32 rar, u32 vmdq) 828 { 829 u32 rar_high; 830 u32 rar_entries = hw->mac.num_rar_entries; 831 832 UNREFERENCED_PARAMETER(vmdq); 833 834 if (rar < rar_entries) { 835 rar_high = IXGBE_READ_REG(hw, IXGBE_RAH(rar)); 836 if (rar_high & IXGBE_RAH_VIND_MASK) { 837 rar_high &= ~IXGBE_RAH_VIND_MASK; 838 IXGBE_WRITE_REG(hw, IXGBE_RAH(rar), rar_high); 839 } 840 } else { 841 DEBUGOUT1("RAR index %d is out of range.\n", rar); 842 } 843 844 return IXGBE_SUCCESS; 845 } 846 847 /** 848 * ixgbe_set_vfta_82598 - Set VLAN filter table 849 * @hw: pointer to hardware structure 850 * @vlan: VLAN id to write to VLAN filter 851 * @vind: VMDq output index that maps queue to VLAN id in VFTA 852 * @vlan_on: boolean flag to turn on/off VLAN in VFTA 853 * 854 * Turn on/off specified VLAN in the VLAN filter table. 855 **/ 856 s32 ixgbe_set_vfta_82598(struct ixgbe_hw *hw, u32 vlan, u32 vind, 857 bool vlan_on) 858 { 859 u32 regindex; 860 u32 bitindex; 861 u32 bits; 862 u32 vftabyte; 863 864 if (vlan > 4095) 865 return IXGBE_ERR_PARAM; 866 867 /* Determine 32-bit word position in array */ 868 regindex = (vlan >> 5) & 0x7F; /* upper seven bits */ 869 870 /* Determine the location of the (VMD) queue index */ 871 vftabyte = ((vlan >> 3) & 0x03); /* bits (4:3) indicating byte array */ 872 bitindex = (vlan & 0x7) << 2; /* lower 3 bits indicate nibble */ 873 874 /* Set the nibble for VMD queue index */ 875 bits = IXGBE_READ_REG(hw, IXGBE_VFTAVIND(vftabyte, regindex)); 876 bits &= (~(0x0F << bitindex)); 877 bits |= (vind << bitindex); 878 IXGBE_WRITE_REG(hw, IXGBE_VFTAVIND(vftabyte, regindex), bits); 879 880 /* Determine the location of the bit for this VLAN id */ 881 bitindex = vlan & 0x1F; /* lower five bits */ 882 883 bits = IXGBE_READ_REG(hw, IXGBE_VFTA(regindex)); 884 if (vlan_on) 885 /* Turn on this VLAN id */ 886 bits |= (1 << bitindex); 887 else 888 /* Turn off this VLAN id */ 889 bits &= ~(1 << bitindex); 890 IXGBE_WRITE_REG(hw, IXGBE_VFTA(regindex), bits); 891 892 return IXGBE_SUCCESS; 893 } 894 895 /** 896 * ixgbe_clear_vfta_82598 - Clear VLAN filter table 897 * @hw: pointer to hardware structure 898 * 899 * Clears the VLAN filer table, and the VMDq index associated with the filter 900 **/ 901 static s32 ixgbe_clear_vfta_82598(struct ixgbe_hw *hw) 902 { 903 u32 offset; 904 u32 vlanbyte; 905 906 for (offset = 0; offset < hw->mac.vft_size; offset++) 907 IXGBE_WRITE_REG(hw, IXGBE_VFTA(offset), 0); 908 909 for (vlanbyte = 0; vlanbyte < 4; vlanbyte++) 910 for (offset = 0; offset < hw->mac.vft_size; offset++) 911 IXGBE_WRITE_REG(hw, IXGBE_VFTAVIND(vlanbyte, offset), 912 0); 913 914 return IXGBE_SUCCESS; 915 } 916 917 /** 918 * ixgbe_read_analog_reg8_82598 - Reads 8 bit Atlas analog register 919 * @hw: pointer to hardware structure 920 * @reg: analog register to read 921 * @val: read value 922 * 923 * Performs read operation to Atlas analog register specified. 924 **/ 925 s32 ixgbe_read_analog_reg8_82598(struct ixgbe_hw *hw, u32 reg, u8 *val) 926 { 927 u32 atlas_ctl; 928 929 IXGBE_WRITE_REG(hw, IXGBE_ATLASCTL, 930 IXGBE_ATLASCTL_WRITE_CMD | (reg << 8)); 931 IXGBE_WRITE_FLUSH(hw); 932 usec_delay(10); 933 atlas_ctl = IXGBE_READ_REG(hw, IXGBE_ATLASCTL); 934 *val = (u8)atlas_ctl; 935 936 return IXGBE_SUCCESS; 937 } 938 939 /** 940 * ixgbe_write_analog_reg8_82598 - Writes 8 bit Atlas analog register 941 * @hw: pointer to hardware structure 942 * @reg: atlas register to write 943 * @val: value to write 944 * 945 * Performs write operation to Atlas analog register specified. 946 **/ 947 s32 ixgbe_write_analog_reg8_82598(struct ixgbe_hw *hw, u32 reg, u8 val) 948 { 949 u32 atlas_ctl; 950 951 atlas_ctl = (reg << 8) | val; 952 IXGBE_WRITE_REG(hw, IXGBE_ATLASCTL, atlas_ctl); 953 IXGBE_WRITE_FLUSH(hw); 954 usec_delay(10); 955 956 return IXGBE_SUCCESS; 957 } 958 959 /** 960 * ixgbe_read_i2c_eeprom_82598 - Reads 8 bit word over I2C interface. 961 * @hw: pointer to hardware structure 962 * @byte_offset: EEPROM byte offset to read 963 * @eeprom_data: value read 964 * 965 * Performs 8 byte read operation to SFP module's EEPROM over I2C interface. 966 **/ 967 s32 ixgbe_read_i2c_eeprom_82598(struct ixgbe_hw *hw, u8 byte_offset, 968 u8 *eeprom_data) 969 { 970 s32 status = IXGBE_SUCCESS; 971 u16 sfp_addr = 0; 972 u16 sfp_data = 0; 973 u16 sfp_stat = 0; 974 u32 i; 975 976 if (hw->phy.type == ixgbe_phy_nl) { 977 /* 978 * NetLogic phy SDA/SCL registers are at addresses 0xC30A to 979 * 0xC30D. These registers are used to talk to the SFP+ 980 * module's EEPROM through the SDA/SCL (I2C) interface. 981 */ 982 sfp_addr = (IXGBE_I2C_EEPROM_DEV_ADDR << 8) + byte_offset; 983 sfp_addr = (sfp_addr | IXGBE_I2C_EEPROM_READ_MASK); 984 hw->phy.ops.write_reg(hw, 985 IXGBE_MDIO_PMA_PMD_SDA_SCL_ADDR, 986 IXGBE_MDIO_PMA_PMD_DEV_TYPE, 987 sfp_addr); 988 989 /* Poll status */ 990 for (i = 0; i < 100; i++) { 991 hw->phy.ops.read_reg(hw, 992 IXGBE_MDIO_PMA_PMD_SDA_SCL_STAT, 993 IXGBE_MDIO_PMA_PMD_DEV_TYPE, 994 &sfp_stat); 995 sfp_stat = sfp_stat & IXGBE_I2C_EEPROM_STATUS_MASK; 996 if (sfp_stat != IXGBE_I2C_EEPROM_STATUS_IN_PROGRESS) 997 break; 998 msec_delay(10); 999 } 1000 1001 if (sfp_stat != IXGBE_I2C_EEPROM_STATUS_PASS) { 1002 DEBUGOUT("EEPROM read did not pass.\n"); 1003 status = IXGBE_ERR_SFP_NOT_PRESENT; 1004 goto out; 1005 } 1006 1007 /* Read data */ 1008 hw->phy.ops.read_reg(hw, IXGBE_MDIO_PMA_PMD_SDA_SCL_DATA, 1009 IXGBE_MDIO_PMA_PMD_DEV_TYPE, &sfp_data); 1010 1011 *eeprom_data = (u8)(sfp_data >> 8); 1012 } else { 1013 status = IXGBE_ERR_PHY; 1014 goto out; 1015 } 1016 1017 out: 1018 return status; 1019 } 1020 1021 /** 1022 * ixgbe_get_supported_physical_layer_82598 - Returns physical layer type 1023 * @hw: pointer to hardware structure 1024 * 1025 * Determines physical layer capabilities of the current configuration. 1026 **/ 1027 u32 ixgbe_get_supported_physical_layer_82598(struct ixgbe_hw *hw) 1028 { 1029 u32 physical_layer = IXGBE_PHYSICAL_LAYER_UNKNOWN; 1030 u32 autoc = IXGBE_READ_REG(hw, IXGBE_AUTOC); 1031 u32 pma_pmd_10g = autoc & IXGBE_AUTOC_10G_PMA_PMD_MASK; 1032 u32 pma_pmd_1g = autoc & IXGBE_AUTOC_1G_PMA_PMD_MASK; 1033 u16 ext_ability = 0; 1034 1035 hw->phy.ops.identify(hw); 1036 1037 /* Copper PHY must be checked before AUTOC LMS to determine correct 1038 * physical layer because 10GBase-T PHYs use LMS = KX4/KX */ 1039 if (hw->phy.type == ixgbe_phy_tn || 1040 hw->phy.type == ixgbe_phy_cu_unknown) { 1041 hw->phy.ops.read_reg(hw, IXGBE_MDIO_PHY_EXT_ABILITY, 1042 IXGBE_MDIO_PMA_PMD_DEV_TYPE, &ext_ability); 1043 if (ext_ability & IXGBE_MDIO_PHY_10GBASET_ABILITY) 1044 physical_layer |= IXGBE_PHYSICAL_LAYER_10GBASE_T; 1045 if (ext_ability & IXGBE_MDIO_PHY_1000BASET_ABILITY) 1046 physical_layer |= IXGBE_PHYSICAL_LAYER_1000BASE_T; 1047 if (ext_ability & IXGBE_MDIO_PHY_100BASETX_ABILITY) 1048 physical_layer |= IXGBE_PHYSICAL_LAYER_100BASE_TX; 1049 goto out; 1050 } 1051 1052 switch (autoc & IXGBE_AUTOC_LMS_MASK) { 1053 case IXGBE_AUTOC_LMS_1G_AN: 1054 case IXGBE_AUTOC_LMS_1G_LINK_NO_AN: 1055 if (pma_pmd_1g == IXGBE_AUTOC_1G_KX) 1056 physical_layer = IXGBE_PHYSICAL_LAYER_1000BASE_KX; 1057 else 1058 physical_layer = IXGBE_PHYSICAL_LAYER_1000BASE_BX; 1059 break; 1060 case IXGBE_AUTOC_LMS_10G_LINK_NO_AN: 1061 if (pma_pmd_10g == IXGBE_AUTOC_10G_CX4) 1062 physical_layer = IXGBE_PHYSICAL_LAYER_10GBASE_CX4; 1063 else if (pma_pmd_10g == IXGBE_AUTOC_10G_KX4) 1064 physical_layer = IXGBE_PHYSICAL_LAYER_10GBASE_KX4; 1065 else /* XAUI */ 1066 physical_layer = IXGBE_PHYSICAL_LAYER_UNKNOWN; 1067 break; 1068 case IXGBE_AUTOC_LMS_KX4_AN: 1069 case IXGBE_AUTOC_LMS_KX4_AN_1G_AN: 1070 if (autoc & IXGBE_AUTOC_KX_SUPP) 1071 physical_layer |= IXGBE_PHYSICAL_LAYER_1000BASE_KX; 1072 if (autoc & IXGBE_AUTOC_KX4_SUPP) 1073 physical_layer |= IXGBE_PHYSICAL_LAYER_10GBASE_KX4; 1074 break; 1075 default: 1076 break; 1077 } 1078 1079 if (hw->phy.type == ixgbe_phy_nl) { 1080 hw->phy.ops.identify_sfp(hw); 1081 1082 switch (hw->phy.sfp_type) { 1083 case ixgbe_sfp_type_da_cu: 1084 physical_layer = IXGBE_PHYSICAL_LAYER_SFP_PLUS_CU; 1085 break; 1086 case ixgbe_sfp_type_sr: 1087 physical_layer = IXGBE_PHYSICAL_LAYER_10GBASE_SR; 1088 break; 1089 case ixgbe_sfp_type_lr: 1090 physical_layer = IXGBE_PHYSICAL_LAYER_10GBASE_LR; 1091 break; 1092 default: 1093 physical_layer = IXGBE_PHYSICAL_LAYER_UNKNOWN; 1094 break; 1095 } 1096 } 1097 1098 switch (hw->device_id) { 1099 case IXGBE_DEV_ID_82598_DA_DUAL_PORT: 1100 physical_layer = IXGBE_PHYSICAL_LAYER_SFP_PLUS_CU; 1101 break; 1102 case IXGBE_DEV_ID_82598AF_DUAL_PORT: 1103 case IXGBE_DEV_ID_82598AF_SINGLE_PORT: 1104 case IXGBE_DEV_ID_82598_SR_DUAL_PORT_EM: 1105 physical_layer = IXGBE_PHYSICAL_LAYER_10GBASE_SR; 1106 break; 1107 case IXGBE_DEV_ID_82598EB_XF_LR: 1108 physical_layer = IXGBE_PHYSICAL_LAYER_10GBASE_LR; 1109 break; 1110 default: 1111 break; 1112 } 1113 1114 out: 1115 return physical_layer; 1116 } 1117 1118 /** 1119 * ixgbe_set_lan_id_multi_port_pcie_82598 - Set LAN id for PCIe multiple 1120 * port devices. 1121 * @hw: pointer to the HW structure 1122 * 1123 * Calls common function and corrects issue with some single port devices 1124 * that enable LAN1 but not LAN0. 1125 **/ 1126 void ixgbe_set_lan_id_multi_port_pcie_82598(struct ixgbe_hw *hw) 1127 { 1128 struct ixgbe_bus_info *bus = &hw->bus; 1129 u16 pci_gen, pci_ctrl2; 1130 1131 ixgbe_set_lan_id_multi_port_pcie(hw); 1132 1133 /* check if LAN0 is disabled */ 1134 hw->eeprom.ops.read(hw, IXGBE_PCIE_GENERAL_PTR, &pci_gen); 1135 if ((pci_gen != 0) && (pci_gen != 0xFFFF)) { 1136 1137 hw->eeprom.ops.read(hw, pci_gen + IXGBE_PCIE_CTRL2, &pci_ctrl2); 1138 1139 /* if LAN0 is completely disabled force function to 0 */ 1140 if ((pci_ctrl2 & IXGBE_PCIE_CTRL2_LAN_DISABLE) && 1141 !(pci_ctrl2 & IXGBE_PCIE_CTRL2_DISABLE_SELECT) && 1142 !(pci_ctrl2 & IXGBE_PCIE_CTRL2_DUMMY_ENABLE)) { 1143 1144 bus->func = 0; 1145 } 1146 } 1147 } 1148 1149 1150