1 /****************************************************************************** 2 3 Copyright (c) 2001-2008, Intel Corporation 4 All rights reserved. 5 6 Redistribution and use in source and binary forms, with or without 7 modification, are permitted provided that the following conditions are met: 8 9 1. Redistributions of source code must retain the above copyright notice, 10 this list of conditions and the following disclaimer. 11 12 2. Redistributions in binary form must reproduce the above copyright 13 notice, this list of conditions and the following disclaimer in the 14 documentation and/or other materials provided with the distribution. 15 16 3. Neither the name of the Intel Corporation nor the names of its 17 contributors may be used to endorse or promote products derived from 18 this software without specific prior written permission. 19 20 THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 21 AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 22 IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 23 ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE 24 LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 25 CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 26 SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 27 INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 28 CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 29 ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 30 POSSIBILITY OF SUCH DAMAGE. 31 32 ******************************************************************************/ 33 /*$FreeBSD$*/ 34 35 #include "ixgbe_type.h" 36 #include "ixgbe_api.h" 37 #include "ixgbe_common.h" 38 #include "ixgbe_phy.h" 39 40 s32 ixgbe_init_ops_82598(struct ixgbe_hw *hw); 41 static s32 ixgbe_get_link_capabilities_82598(struct ixgbe_hw *hw, 42 ixgbe_link_speed *speed, 43 bool *autoneg); 44 s32 ixgbe_get_copper_link_capabilities_82598(struct ixgbe_hw *hw, 45 ixgbe_link_speed *speed, 46 bool *autoneg); 47 static enum ixgbe_media_type ixgbe_get_media_type_82598(struct ixgbe_hw *hw); 48 s32 ixgbe_setup_fc_82598(struct ixgbe_hw *hw, s32 packetbuf_num); 49 s32 ixgbe_fc_enable_82598(struct ixgbe_hw *hw, s32 packetbuf_num); 50 static s32 ixgbe_setup_mac_link_82598(struct ixgbe_hw *hw); 51 static s32 ixgbe_check_mac_link_82598(struct ixgbe_hw *hw, 52 ixgbe_link_speed *speed, bool *link_up, 53 bool link_up_wait_to_complete); 54 static s32 ixgbe_setup_mac_link_speed_82598(struct ixgbe_hw *hw, 55 ixgbe_link_speed speed, 56 bool autoneg, 57 bool autoneg_wait_to_complete); 58 static s32 ixgbe_setup_copper_link_82598(struct ixgbe_hw *hw); 59 static s32 ixgbe_setup_copper_link_speed_82598(struct ixgbe_hw *hw, 60 ixgbe_link_speed speed, 61 bool autoneg, 62 bool autoneg_wait_to_complete); 63 #ifndef NO_82598_A0_SUPPORT 64 s32 ixgbe_reset_hw_rev_0_82598(struct ixgbe_hw *hw); 65 #endif 66 static s32 ixgbe_reset_hw_82598(struct ixgbe_hw *hw); 67 s32 ixgbe_set_vmdq_82598(struct ixgbe_hw *hw, u32 rar, u32 vmdq); 68 static s32 ixgbe_clear_vmdq_82598(struct ixgbe_hw *hw, u32 rar, u32 vmdq); 69 s32 ixgbe_set_vfta_82598(struct ixgbe_hw *hw, u32 vlan, 70 u32 vind, bool vlan_on); 71 static s32 ixgbe_clear_vfta_82598(struct ixgbe_hw *hw); 72 static s32 ixgbe_blink_led_stop_82598(struct ixgbe_hw *hw, u32 index); 73 static s32 ixgbe_blink_led_start_82598(struct ixgbe_hw *hw, u32 index); 74 s32 ixgbe_read_analog_reg8_82598(struct ixgbe_hw *hw, u32 reg, u8 *val); 75 s32 ixgbe_write_analog_reg8_82598(struct ixgbe_hw *hw, u32 reg, u8 val); 76 s32 ixgbe_read_i2c_eeprom_82598(struct ixgbe_hw *hw, u8 byte_offset, 77 u8 *eeprom_data); 78 u32 ixgbe_get_supported_physical_layer_82598(struct ixgbe_hw *hw); 79 80 /** 81 * ixgbe_init_ops_82598 - Inits func ptrs and MAC type 82 * @hw: pointer to hardware structure 83 * 84 * Initialize the function pointers and assign the MAC type for 82598. 85 * Does not touch the hardware. 86 **/ 87 s32 ixgbe_init_ops_82598(struct ixgbe_hw *hw) 88 { 89 struct ixgbe_mac_info *mac = &hw->mac; 90 struct ixgbe_phy_info *phy = &hw->phy; 91 s32 ret_val; 92 u16 list_offset, data_offset; 93 94 ret_val = ixgbe_init_phy_ops_generic(hw); 95 ret_val = ixgbe_init_ops_generic(hw); 96 97 /* MAC */ 98 #ifndef NO_82598_A0_SUPPORT 99 if (hw->revision_id == 0) 100 mac->ops.reset_hw = &ixgbe_reset_hw_rev_0_82598; 101 else 102 mac->ops.reset_hw = &ixgbe_reset_hw_82598; 103 #else 104 mac->ops.reset_hw = &ixgbe_reset_hw_82598; 105 #endif 106 mac->ops.get_media_type = &ixgbe_get_media_type_82598; 107 mac->ops.get_supported_physical_layer = 108 &ixgbe_get_supported_physical_layer_82598; 109 mac->ops.read_analog_reg8 = &ixgbe_read_analog_reg8_82598; 110 mac->ops.write_analog_reg8 = &ixgbe_write_analog_reg8_82598; 111 112 /* LEDs */ 113 mac->ops.blink_led_start = &ixgbe_blink_led_start_82598; 114 mac->ops.blink_led_stop = &ixgbe_blink_led_stop_82598; 115 116 /* RAR, Multicast, VLAN */ 117 mac->ops.set_vmdq = &ixgbe_set_vmdq_82598; 118 mac->ops.clear_vmdq = &ixgbe_clear_vmdq_82598; 119 mac->ops.set_vfta = &ixgbe_set_vfta_82598; 120 mac->ops.clear_vfta = &ixgbe_clear_vfta_82598; 121 122 /* Flow Control */ 123 mac->ops.setup_fc = &ixgbe_setup_fc_82598; 124 125 /* Link */ 126 mac->ops.check_link = &ixgbe_check_mac_link_82598; 127 if (mac->ops.get_media_type(hw) == ixgbe_media_type_copper) { 128 mac->ops.setup_link = &ixgbe_setup_copper_link_82598; 129 mac->ops.setup_link_speed = 130 &ixgbe_setup_copper_link_speed_82598; 131 mac->ops.get_link_capabilities = 132 &ixgbe_get_copper_link_capabilities_82598; 133 } else { 134 mac->ops.setup_link = &ixgbe_setup_mac_link_82598; 135 mac->ops.setup_link_speed = &ixgbe_setup_mac_link_speed_82598; 136 mac->ops.get_link_capabilities = 137 &ixgbe_get_link_capabilities_82598; 138 } 139 140 mac->mcft_size = 128; 141 mac->vft_size = 128; 142 mac->num_rar_entries = 16; 143 mac->max_tx_queues = 32; 144 mac->max_rx_queues = 64; 145 146 /* SFP+ Module */ 147 phy->ops.read_i2c_eeprom = &ixgbe_read_i2c_eeprom_82598; 148 149 /* Call PHY identify routine to get the phy type */ 150 phy->ops.identify(hw); 151 152 /* PHY Init */ 153 switch (hw->phy.type) { 154 case ixgbe_phy_tn: 155 phy->ops.check_link = &ixgbe_check_phy_link_tnx; 156 phy->ops.get_firmware_version = 157 &ixgbe_get_phy_firmware_version_tnx; 158 break; 159 case ixgbe_phy_nl: 160 phy->ops.reset = &ixgbe_reset_phy_nl; 161 162 /* Call SFP+ identify routine to get the SFP+ module type */ 163 ret_val = phy->ops.identify_sfp(hw); 164 if (ret_val != IXGBE_SUCCESS) 165 goto out; 166 else if (hw->phy.sfp_type == ixgbe_sfp_type_unknown) { 167 ret_val = IXGBE_ERR_SFP_NOT_SUPPORTED; 168 goto out; 169 } 170 171 /* Check to see if SFP+ module is supported */ 172 ret_val = ixgbe_get_sfp_init_sequence_offsets(hw, 173 &list_offset, 174 &data_offset); 175 if (ret_val != IXGBE_SUCCESS) { 176 ret_val = IXGBE_ERR_SFP_NOT_SUPPORTED; 177 goto out; 178 } 179 break; 180 default: 181 break; 182 } 183 184 out: 185 return ret_val; 186 } 187 188 /** 189 * ixgbe_get_link_capabilities_82598 - Determines link capabilities 190 * @hw: pointer to hardware structure 191 * @speed: pointer to link speed 192 * @autoneg: boolean auto-negotiation value 193 * 194 * Determines the link capabilities by reading the AUTOC register. 195 **/ 196 static s32 ixgbe_get_link_capabilities_82598(struct ixgbe_hw *hw, 197 ixgbe_link_speed *speed, 198 bool *autoneg) 199 { 200 s32 status = IXGBE_SUCCESS; 201 s32 autoc_reg; 202 203 autoc_reg = IXGBE_READ_REG(hw, IXGBE_AUTOC); 204 205 if (hw->mac.link_settings_loaded) { 206 autoc_reg &= ~IXGBE_AUTOC_LMS_ATTACH_TYPE; 207 autoc_reg &= ~IXGBE_AUTOC_LMS_MASK; 208 autoc_reg |= hw->mac.link_attach_type; 209 autoc_reg |= hw->mac.link_mode_select; 210 } 211 212 switch (autoc_reg & IXGBE_AUTOC_LMS_MASK) { 213 case IXGBE_AUTOC_LMS_1G_LINK_NO_AN: 214 *speed = IXGBE_LINK_SPEED_1GB_FULL; 215 *autoneg = FALSE; 216 break; 217 218 case IXGBE_AUTOC_LMS_10G_LINK_NO_AN: 219 *speed = IXGBE_LINK_SPEED_10GB_FULL; 220 *autoneg = FALSE; 221 break; 222 223 case IXGBE_AUTOC_LMS_1G_AN: 224 *speed = IXGBE_LINK_SPEED_1GB_FULL; 225 *autoneg = TRUE; 226 break; 227 228 case IXGBE_AUTOC_LMS_KX4_AN: 229 case IXGBE_AUTOC_LMS_KX4_AN_1G_AN: 230 *speed = IXGBE_LINK_SPEED_UNKNOWN; 231 if (autoc_reg & IXGBE_AUTOC_KX4_SUPP) 232 *speed |= IXGBE_LINK_SPEED_10GB_FULL; 233 if (autoc_reg & IXGBE_AUTOC_KX_SUPP) 234 *speed |= IXGBE_LINK_SPEED_1GB_FULL; 235 *autoneg = TRUE; 236 break; 237 238 default: 239 status = IXGBE_ERR_LINK_SETUP; 240 break; 241 } 242 243 return status; 244 } 245 246 /** 247 * ixgbe_get_copper_link_capabilities_82598 - Determines link capabilities 248 * @hw: pointer to hardware structure 249 * @speed: pointer to link speed 250 * @autoneg: boolean auto-negotiation value 251 * 252 * Determines the link capabilities by reading the AUTOC register. 253 **/ 254 s32 ixgbe_get_copper_link_capabilities_82598(struct ixgbe_hw *hw, 255 ixgbe_link_speed *speed, 256 bool *autoneg) 257 { 258 s32 status = IXGBE_ERR_LINK_SETUP; 259 u16 speed_ability; 260 261 *speed = 0; 262 *autoneg = TRUE; 263 264 status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_PHY_SPEED_ABILITY, 265 IXGBE_MDIO_PMA_PMD_DEV_TYPE, 266 &speed_ability); 267 268 if (status == IXGBE_SUCCESS) { 269 if (speed_ability & IXGBE_MDIO_PHY_SPEED_10G) 270 *speed |= IXGBE_LINK_SPEED_10GB_FULL; 271 if (speed_ability & IXGBE_MDIO_PHY_SPEED_1G) 272 *speed |= IXGBE_LINK_SPEED_1GB_FULL; 273 } 274 275 return status; 276 } 277 278 /** 279 * ixgbe_get_media_type_82598 - Determines media type 280 * @hw: pointer to hardware structure 281 * 282 * Returns the media type (fiber, copper, backplane) 283 **/ 284 static enum ixgbe_media_type ixgbe_get_media_type_82598(struct ixgbe_hw *hw) 285 { 286 enum ixgbe_media_type media_type; 287 288 /* Media type for I82598 is based on device ID */ 289 switch (hw->device_id) { 290 case IXGBE_DEV_ID_82598: 291 /* Default device ID is mezzanine card KX/KX4 */ 292 media_type = ixgbe_media_type_backplane; 293 break; 294 case IXGBE_DEV_ID_82598AF_DUAL_PORT: 295 case IXGBE_DEV_ID_82598AF_SINGLE_PORT: 296 case IXGBE_DEV_ID_82598EB_CX4: 297 case IXGBE_DEV_ID_82598_CX4_DUAL_PORT: 298 case IXGBE_DEV_ID_82598_DA_DUAL_PORT: 299 case IXGBE_DEV_ID_82598_SR_DUAL_PORT_EM: 300 case IXGBE_DEV_ID_82598EB_XF_LR: 301 case IXGBE_DEV_ID_82598EB_SFP_LOM: 302 media_type = ixgbe_media_type_fiber; 303 break; 304 case IXGBE_DEV_ID_82598AT: 305 media_type = ixgbe_media_type_copper; 306 break; 307 default: 308 media_type = ixgbe_media_type_unknown; 309 break; 310 } 311 312 return media_type; 313 } 314 315 /** 316 * ixgbe_fc_enable_82598 - Enable flow control 317 * @hw: pointer to hardware structure 318 * @packetbuf_num: packet buffer number (0-7) 319 * 320 * Enable flow control according to the current settings. 321 **/ 322 s32 ixgbe_fc_enable_82598(struct ixgbe_hw *hw, s32 packetbuf_num) 323 { 324 s32 ret_val = IXGBE_SUCCESS; 325 u32 fctrl_reg; 326 u32 rmcs_reg; 327 u32 reg; 328 329 DEBUGFUNC("ixgbe_fc_enable_82598"); 330 331 fctrl_reg = IXGBE_READ_REG(hw, IXGBE_FCTRL); 332 fctrl_reg &= ~(IXGBE_FCTRL_RFCE | IXGBE_FCTRL_RPFCE); 333 334 rmcs_reg = IXGBE_READ_REG(hw, IXGBE_RMCS); 335 rmcs_reg &= ~(IXGBE_RMCS_TFCE_PRIORITY | IXGBE_RMCS_TFCE_802_3X); 336 337 /* 338 * The possible values of fc.current_mode are: 339 * 0: Flow control is completely disabled 340 * 1: Rx flow control is enabled (we can receive pause frames, 341 * but not send pause frames). 342 * 2: Tx flow control is enabled (we can send pause frames but 343 * we do not support receiving pause frames). 344 * 3: Both Rx and Tx flow control (symmetric) are enabled. 345 * other: Invalid. 346 */ 347 switch (hw->fc.current_mode) { 348 case ixgbe_fc_none: 349 /* Flow control completely disabled by software override. */ 350 break; 351 case ixgbe_fc_rx_pause: 352 /* 353 * Rx Flow control is enabled and Tx Flow control is 354 * disabled by software override. Since there really 355 * isn't a way to advertise that we are capable of RX 356 * Pause ONLY, we will advertise that we support both 357 * symmetric and asymmetric Rx PAUSE. Later, we will 358 * disable the adapter's ability to send PAUSE frames. 359 */ 360 fctrl_reg |= IXGBE_FCTRL_RFCE; 361 break; 362 case ixgbe_fc_tx_pause: 363 /* 364 * Tx Flow control is enabled, and Rx Flow control is 365 * disabled by software override. 366 */ 367 rmcs_reg |= IXGBE_RMCS_TFCE_802_3X; 368 break; 369 case ixgbe_fc_full: 370 /* Flow control (both Rx and Tx) is enabled by SW override. */ 371 fctrl_reg |= IXGBE_FCTRL_RFCE; 372 rmcs_reg |= IXGBE_RMCS_TFCE_802_3X; 373 break; 374 default: 375 DEBUGOUT("Flow control param set incorrectly\n"); 376 ret_val = -IXGBE_ERR_CONFIG; 377 goto out; 378 break; 379 } 380 381 /* Enable 802.3x based flow control settings. */ 382 IXGBE_WRITE_REG(hw, IXGBE_FCTRL, fctrl_reg); 383 IXGBE_WRITE_REG(hw, IXGBE_RMCS, rmcs_reg); 384 385 /* Set up and enable Rx high/low water mark thresholds, enable XON. */ 386 if (hw->fc.current_mode & ixgbe_fc_tx_pause) { 387 if (hw->fc.send_xon) { 388 IXGBE_WRITE_REG(hw, IXGBE_FCRTL(packetbuf_num), 389 (hw->fc.low_water | IXGBE_FCRTL_XONE)); 390 } else { 391 IXGBE_WRITE_REG(hw, IXGBE_FCRTL(packetbuf_num), 392 hw->fc.low_water); 393 } 394 395 IXGBE_WRITE_REG(hw, IXGBE_FCRTH(packetbuf_num), 396 (hw->fc.high_water | IXGBE_FCRTH_FCEN)); 397 } 398 399 /* Configure pause time (2 TCs per register) */ 400 reg = IXGBE_READ_REG(hw, IXGBE_FCTTV(packetbuf_num)); 401 if ((packetbuf_num & 1) == 0) 402 reg = (reg & 0xFFFF0000) | hw->fc.pause_time; 403 else 404 reg = (reg & 0x0000FFFF) | (hw->fc.pause_time << 16); 405 IXGBE_WRITE_REG(hw, IXGBE_FCTTV(packetbuf_num / 2), reg); 406 407 IXGBE_WRITE_REG(hw, IXGBE_FCRTV, (hw->fc.pause_time >> 1)); 408 409 out: 410 return ret_val; 411 } 412 413 /** 414 * ixgbe_setup_fc_82598 - Set up flow control 415 * @hw: pointer to hardware structure 416 * 417 * Sets up flow control. 418 **/ 419 s32 ixgbe_setup_fc_82598(struct ixgbe_hw *hw, s32 packetbuf_num) 420 { 421 s32 ret_val = IXGBE_SUCCESS; 422 ixgbe_link_speed speed; 423 bool link_up; 424 425 /* Validate the packetbuf configuration */ 426 if (packetbuf_num < 0 || packetbuf_num > 7) { 427 DEBUGOUT1("Invalid packet buffer number [%d], expected range is" 428 " 0-7\n", packetbuf_num); 429 ret_val = IXGBE_ERR_INVALID_LINK_SETTINGS; 430 goto out; 431 } 432 433 /* 434 * Validate the water mark configuration. Zero water marks are invalid 435 * because it causes the controller to just blast out fc packets. 436 */ 437 if (!hw->fc.low_water || !hw->fc.high_water || !hw->fc.pause_time) { 438 DEBUGOUT("Invalid water mark configuration\n"); 439 ret_val = IXGBE_ERR_INVALID_LINK_SETTINGS; 440 goto out; 441 } 442 443 /* 444 * Validate the requested mode. Strict IEEE mode does not allow 445 * ixgbe_fc_rx_pause because it will cause testing anomalies. 446 */ 447 if (hw->fc.strict_ieee && hw->fc.requested_mode == ixgbe_fc_rx_pause) { 448 DEBUGOUT("ixgbe_fc_rx_pause not valid in strict IEEE mode\n"); 449 ret_val = IXGBE_ERR_INVALID_LINK_SETTINGS; 450 goto out; 451 } 452 453 /* 454 * 10gig parts do not have a word in the EEPROM to determine the 455 * default flow control setting, so we explicitly set it to full. 456 */ 457 if (hw->fc.requested_mode == ixgbe_fc_default) 458 hw->fc.requested_mode = ixgbe_fc_full; 459 460 /* 461 * Save off the requested flow control mode for use later. Depending 462 * on the link partner's capabilities, we may or may not use this mode. 463 */ 464 hw->fc.current_mode = hw->fc.requested_mode; 465 466 /* Decide whether to use autoneg or not. */ 467 hw->mac.ops.check_link(hw, &speed, &link_up, FALSE); 468 if (hw->phy.multispeed_fiber && (speed == IXGBE_LINK_SPEED_1GB_FULL)) 469 ret_val = ixgbe_fc_autoneg(hw); 470 471 if (ret_val) 472 goto out; 473 474 ret_val = ixgbe_fc_enable_82598(hw, packetbuf_num); 475 476 out: 477 return ret_val; 478 } 479 480 /** 481 * ixgbe_setup_mac_link_82598 - Configures MAC link settings 482 * @hw: pointer to hardware structure 483 * 484 * Configures link settings based on values in the ixgbe_hw struct. 485 * Restarts the link. Performs autonegotiation if needed. 486 **/ 487 static s32 ixgbe_setup_mac_link_82598(struct ixgbe_hw *hw) 488 { 489 u32 autoc_reg; 490 u32 links_reg; 491 u32 i; 492 s32 status = IXGBE_SUCCESS; 493 494 autoc_reg = IXGBE_READ_REG(hw, IXGBE_AUTOC); 495 496 if (hw->mac.link_settings_loaded) { 497 autoc_reg &= ~IXGBE_AUTOC_LMS_ATTACH_TYPE; 498 autoc_reg &= ~IXGBE_AUTOC_LMS_MASK; 499 autoc_reg |= hw->mac.link_attach_type; 500 autoc_reg |= hw->mac.link_mode_select; 501 502 IXGBE_WRITE_REG(hw, IXGBE_AUTOC, autoc_reg); 503 IXGBE_WRITE_FLUSH(hw); 504 msec_delay(50); 505 } 506 507 /* Restart link */ 508 autoc_reg |= IXGBE_AUTOC_AN_RESTART; 509 IXGBE_WRITE_REG(hw, IXGBE_AUTOC, autoc_reg); 510 511 /* Only poll for autoneg to complete if specified to do so */ 512 if (hw->phy.autoneg_wait_to_complete) { 513 if (hw->mac.link_mode_select == IXGBE_AUTOC_LMS_KX4_AN || 514 hw->mac.link_mode_select == IXGBE_AUTOC_LMS_KX4_AN_1G_AN) { 515 links_reg = 0; /* Just in case Autoneg time = 0 */ 516 for (i = 0; i < IXGBE_AUTO_NEG_TIME; i++) { 517 links_reg = IXGBE_READ_REG(hw, IXGBE_LINKS); 518 if (links_reg & IXGBE_LINKS_KX_AN_COMP) 519 break; 520 msec_delay(100); 521 } 522 if (!(links_reg & IXGBE_LINKS_KX_AN_COMP)) { 523 status = IXGBE_ERR_AUTONEG_NOT_COMPLETE; 524 DEBUGOUT("Autonegotiation did not complete.\n"); 525 } 526 } 527 } 528 529 /* Set up flow control */ 530 status = ixgbe_setup_fc_82598(hw, 0); 531 532 /* Add delay to filter out noises during initial link setup */ 533 msec_delay(50); 534 535 return status; 536 } 537 538 /** 539 * ixgbe_check_mac_link_82598 - Get link/speed status 540 * @hw: pointer to hardware structure 541 * @speed: pointer to link speed 542 * @link_up: TRUE is link is up, FALSE otherwise 543 * @link_up_wait_to_complete: bool used to wait for link up or not 544 * 545 * Reads the links register to determine if link is up and the current speed 546 **/ 547 static s32 ixgbe_check_mac_link_82598(struct ixgbe_hw *hw, 548 ixgbe_link_speed *speed, bool *link_up, 549 bool link_up_wait_to_complete) 550 { 551 u32 links_reg; 552 u32 i; 553 u16 link_reg, adapt_comp_reg; 554 555 /* 556 * SERDES PHY requires us to read link status from undocumented 557 * register 0xC79F. Bit 0 set indicates link is up/ready; clear 558 * indicates link down. OxC00C is read to check that the XAUI lanes 559 * are active. Bit 0 clear indicates active; set indicates inactive. 560 */ 561 if (hw->phy.type == ixgbe_phy_nl) { 562 hw->phy.ops.read_reg(hw, 0xC79F, IXGBE_TWINAX_DEV, &link_reg); 563 hw->phy.ops.read_reg(hw, 0xC79F, IXGBE_TWINAX_DEV, &link_reg); 564 hw->phy.ops.read_reg(hw, 0xC00C, IXGBE_TWINAX_DEV, 565 &adapt_comp_reg); 566 if (link_up_wait_to_complete) { 567 for (i = 0; i < IXGBE_LINK_UP_TIME; i++) { 568 if ((link_reg & 1) && 569 ((adapt_comp_reg & 1) == 0)) { 570 *link_up = TRUE; 571 break; 572 } else { 573 *link_up = FALSE; 574 } 575 msec_delay(100); 576 hw->phy.ops.read_reg(hw, 0xC79F, 577 IXGBE_TWINAX_DEV, 578 &link_reg); 579 hw->phy.ops.read_reg(hw, 0xC00C, 580 IXGBE_TWINAX_DEV, 581 &adapt_comp_reg); 582 } 583 } else { 584 if ((link_reg & 1) && 585 ((adapt_comp_reg & 1) == 0)) 586 *link_up = TRUE; 587 else 588 *link_up = FALSE; 589 } 590 591 if (*link_up == FALSE) 592 goto out; 593 } 594 595 links_reg = IXGBE_READ_REG(hw, IXGBE_LINKS); 596 if (link_up_wait_to_complete) { 597 for (i = 0; i < IXGBE_LINK_UP_TIME; i++) { 598 if (links_reg & IXGBE_LINKS_UP) { 599 *link_up = TRUE; 600 break; 601 } else { 602 *link_up = FALSE; 603 } 604 msec_delay(100); 605 links_reg = IXGBE_READ_REG(hw, IXGBE_LINKS); 606 } 607 } else { 608 if (links_reg & IXGBE_LINKS_UP) 609 *link_up = TRUE; 610 else 611 *link_up = FALSE; 612 } 613 614 if (links_reg & IXGBE_LINKS_SPEED) 615 *speed = IXGBE_LINK_SPEED_10GB_FULL; 616 else 617 *speed = IXGBE_LINK_SPEED_1GB_FULL; 618 619 out: 620 return IXGBE_SUCCESS; 621 } 622 623 /** 624 * ixgbe_setup_mac_link_speed_82598 - Set MAC link speed 625 * @hw: pointer to hardware structure 626 * @speed: new link speed 627 * @autoneg: TRUE if autonegotiation enabled 628 * @autoneg_wait_to_complete: TRUE when waiting for completion is needed 629 * 630 * Set the link speed in the AUTOC register and restarts link. 631 **/ 632 static s32 ixgbe_setup_mac_link_speed_82598(struct ixgbe_hw *hw, 633 ixgbe_link_speed speed, bool autoneg, 634 bool autoneg_wait_to_complete) 635 { 636 s32 status = IXGBE_SUCCESS; 637 638 /* If speed is 10G, then check for CX4 or XAUI. */ 639 if ((speed == IXGBE_LINK_SPEED_10GB_FULL) && 640 (!(hw->mac.link_attach_type & IXGBE_AUTOC_10G_KX4))) { 641 hw->mac.link_mode_select = IXGBE_AUTOC_LMS_10G_LINK_NO_AN; 642 } else if ((speed == IXGBE_LINK_SPEED_1GB_FULL) && (!autoneg)) { 643 hw->mac.link_mode_select = IXGBE_AUTOC_LMS_1G_LINK_NO_AN; 644 } else if (autoneg) { 645 /* BX mode - Autonegotiate 1G */ 646 if (!(hw->mac.link_attach_type & IXGBE_AUTOC_1G_PMA_PMD)) 647 hw->mac.link_mode_select = IXGBE_AUTOC_LMS_1G_AN; 648 else /* KX/KX4 mode */ 649 hw->mac.link_mode_select = IXGBE_AUTOC_LMS_KX4_AN_1G_AN; 650 } else { 651 status = IXGBE_ERR_LINK_SETUP; 652 } 653 654 if (status == IXGBE_SUCCESS) { 655 hw->phy.autoneg_wait_to_complete = autoneg_wait_to_complete; 656 657 hw->mac.link_settings_loaded = TRUE; 658 /* 659 * Setup and restart the link based on the new values in 660 * ixgbe_hw This will write the AUTOC register based on the new 661 * stored values 662 */ 663 status = ixgbe_setup_mac_link_82598(hw); 664 } 665 666 return status; 667 } 668 669 670 /** 671 * ixgbe_setup_copper_link_82598 - Setup copper link settings 672 * @hw: pointer to hardware structure 673 * 674 * Configures link settings based on values in the ixgbe_hw struct. 675 * Restarts the link. Performs autonegotiation if needed. Restart 676 * phy and wait for autonegotiate to finish. Then synchronize the 677 * MAC and PHY. 678 **/ 679 static s32 ixgbe_setup_copper_link_82598(struct ixgbe_hw *hw) 680 { 681 s32 status; 682 683 /* Restart autonegotiation on PHY */ 684 status = hw->phy.ops.setup_link(hw); 685 686 /* Set MAC to KX/KX4 autoneg, which defaults to Parallel detection */ 687 hw->mac.link_attach_type = (IXGBE_AUTOC_10G_KX4 | IXGBE_AUTOC_1G_KX); 688 hw->mac.link_mode_select = IXGBE_AUTOC_LMS_KX4_AN; 689 690 /* Set up MAC */ 691 ixgbe_setup_mac_link_82598(hw); 692 693 return status; 694 } 695 696 /** 697 * ixgbe_setup_copper_link_speed_82598 - Set the PHY autoneg advertised field 698 * @hw: pointer to hardware structure 699 * @speed: new link speed 700 * @autoneg: TRUE if autonegotiation enabled 701 * @autoneg_wait_to_complete: TRUE if waiting is needed to complete 702 * 703 * Sets the link speed in the AUTOC register in the MAC and restarts link. 704 **/ 705 static s32 ixgbe_setup_copper_link_speed_82598(struct ixgbe_hw *hw, 706 ixgbe_link_speed speed, 707 bool autoneg, 708 bool autoneg_wait_to_complete) 709 { 710 s32 status; 711 712 /* Setup the PHY according to input speed */ 713 status = hw->phy.ops.setup_link_speed(hw, speed, autoneg, 714 autoneg_wait_to_complete); 715 716 /* Set MAC to KX/KX4 autoneg, which defaults to Parallel detection */ 717 hw->mac.link_attach_type = (IXGBE_AUTOC_10G_KX4 | IXGBE_AUTOC_1G_KX); 718 hw->mac.link_mode_select = IXGBE_AUTOC_LMS_KX4_AN; 719 720 /* Set up MAC */ 721 ixgbe_setup_mac_link_82598(hw); 722 723 return status; 724 } 725 726 #ifndef NO_82598_A0_SUPPORT 727 /** 728 * ixgbe_reset_hw_rev_0_82598 - Performs hardware reset 729 * @hw: pointer to hardware structure 730 * 731 * Resets the hardware by resetting the transmit and receive units, masks and 732 * clears all interrupts, performing a PHY reset, and performing a link (MAC) 733 * reset. 734 **/ 735 s32 ixgbe_reset_hw_rev_0_82598(struct ixgbe_hw *hw) 736 { 737 s32 status = IXGBE_SUCCESS; 738 u32 ctrl; 739 u32 gheccr; 740 u32 autoc; 741 u32 i; 742 u32 resets; 743 744 /* Call adapter stop to disable tx/rx and clear interrupts */ 745 hw->mac.ops.stop_adapter(hw); 746 747 /* Reset PHY */ 748 hw->phy.ops.reset(hw); 749 750 for (resets = 0; resets < 10; resets++) { 751 /* 752 * Prevent the PCI-E bus from from hanging by disabling PCI-E 753 * master access and verify no pending requests before reset 754 */ 755 if (ixgbe_disable_pcie_master(hw) != IXGBE_SUCCESS) { 756 status = IXGBE_ERR_MASTER_REQUESTS_PENDING; 757 DEBUGOUT("PCI-E Master disable polling has failed.\n"); 758 } 759 760 /* 761 * Issue global reset to the MAC. This needs to be a SW reset. 762 * If link reset is used, it might reset the MAC when mng is 763 * using it. 764 */ 765 ctrl = IXGBE_READ_REG(hw, IXGBE_CTRL); 766 IXGBE_WRITE_REG(hw, IXGBE_CTRL, (ctrl | IXGBE_CTRL_RST)); 767 IXGBE_WRITE_FLUSH(hw); 768 769 /* 770 * Poll for reset bit to self-clear indicating reset is 771 * complete 772 */ 773 for (i = 0; i < 10; i++) { 774 usec_delay(1); 775 ctrl = IXGBE_READ_REG(hw, IXGBE_CTRL); 776 if (!(ctrl & IXGBE_CTRL_RST)) 777 break; 778 } 779 if (ctrl & IXGBE_CTRL_RST) { 780 status = IXGBE_ERR_RESET_FAILED; 781 DEBUGOUT("Reset polling failed to complete.\n"); 782 } 783 } 784 785 msec_delay(50); 786 787 gheccr = IXGBE_READ_REG(hw, IXGBE_GHECCR); 788 gheccr &= ~((1 << 21) | (1 << 18) | (1 << 9) | (1 << 6)); 789 IXGBE_WRITE_REG(hw, IXGBE_GHECCR, gheccr); 790 791 /* 792 * AUTOC register which stores link settings gets cleared 793 * and reloaded from EEPROM after reset. We need to restore 794 * our stored value from init in case SW changed the attach 795 * type or speed. If this is the first time and link settings 796 * have not been stored, store default settings from AUTOC. 797 */ 798 autoc = IXGBE_READ_REG(hw, IXGBE_AUTOC); 799 if (hw->mac.link_settings_loaded) { 800 autoc &= ~(IXGBE_AUTOC_LMS_ATTACH_TYPE); 801 autoc &= ~(IXGBE_AUTOC_LMS_MASK); 802 autoc |= hw->mac.link_attach_type; 803 autoc |= hw->mac.link_mode_select; 804 IXGBE_WRITE_REG(hw, IXGBE_AUTOC, autoc); 805 } else { 806 hw->mac.link_attach_type = 807 (autoc & IXGBE_AUTOC_LMS_ATTACH_TYPE); 808 hw->mac.link_mode_select = (autoc & IXGBE_AUTOC_LMS_MASK); 809 hw->mac.link_settings_loaded = TRUE; 810 } 811 812 /* Store the permanent mac address */ 813 hw->mac.ops.get_mac_addr(hw, hw->mac.perm_addr); 814 815 return status; 816 } 817 818 #endif /* NO_A0_SUPPORT */ 819 /** 820 * ixgbe_reset_hw_82598 - Performs hardware reset 821 * @hw: pointer to hardware structure 822 * 823 * Resets the hardware by resetting the transmit and receive units, masks and 824 * clears all interrupts, performing a PHY reset, and performing a link (MAC) 825 * reset. 826 **/ 827 static s32 ixgbe_reset_hw_82598(struct ixgbe_hw *hw) 828 { 829 s32 status = IXGBE_SUCCESS; 830 u32 ctrl; 831 u32 gheccr; 832 u32 i; 833 u32 autoc; 834 u8 analog_val; 835 836 /* Call adapter stop to disable tx/rx and clear interrupts */ 837 hw->mac.ops.stop_adapter(hw); 838 839 /* 840 * Power up the Atlas Tx lanes if they are currently powered down. 841 * Atlas Tx lanes are powered down for MAC loopback tests, but 842 * they are not automatically restored on reset. 843 */ 844 hw->mac.ops.read_analog_reg8(hw, IXGBE_ATLAS_PDN_LPBK, &analog_val); 845 if (analog_val & IXGBE_ATLAS_PDN_TX_REG_EN) { 846 /* Enable Tx Atlas so packets can be transmitted again */ 847 hw->mac.ops.read_analog_reg8(hw, IXGBE_ATLAS_PDN_LPBK, 848 &analog_val); 849 analog_val &= ~IXGBE_ATLAS_PDN_TX_REG_EN; 850 hw->mac.ops.write_analog_reg8(hw, IXGBE_ATLAS_PDN_LPBK, 851 analog_val); 852 853 hw->mac.ops.read_analog_reg8(hw, IXGBE_ATLAS_PDN_10G, 854 &analog_val); 855 analog_val &= ~IXGBE_ATLAS_PDN_TX_10G_QL_ALL; 856 hw->mac.ops.write_analog_reg8(hw, IXGBE_ATLAS_PDN_10G, 857 analog_val); 858 859 hw->mac.ops.read_analog_reg8(hw, IXGBE_ATLAS_PDN_1G, 860 &analog_val); 861 analog_val &= ~IXGBE_ATLAS_PDN_TX_1G_QL_ALL; 862 hw->mac.ops.write_analog_reg8(hw, IXGBE_ATLAS_PDN_1G, 863 analog_val); 864 865 hw->mac.ops.read_analog_reg8(hw, IXGBE_ATLAS_PDN_AN, 866 &analog_val); 867 analog_val &= ~IXGBE_ATLAS_PDN_TX_AN_QL_ALL; 868 hw->mac.ops.write_analog_reg8(hw, IXGBE_ATLAS_PDN_AN, 869 analog_val); 870 } 871 872 /* Reset PHY */ 873 if (hw->phy.reset_disable == FALSE) 874 hw->phy.ops.reset(hw); 875 876 /* 877 * Prevent the PCI-E bus from from hanging by disabling PCI-E master 878 * access and verify no pending requests before reset 879 */ 880 if (ixgbe_disable_pcie_master(hw) != IXGBE_SUCCESS) { 881 status = IXGBE_ERR_MASTER_REQUESTS_PENDING; 882 DEBUGOUT("PCI-E Master disable polling has failed.\n"); 883 } 884 885 /* 886 * Issue global reset to the MAC. This needs to be a SW reset. 887 * If link reset is used, it might reset the MAC when mng is using it 888 */ 889 ctrl = IXGBE_READ_REG(hw, IXGBE_CTRL); 890 IXGBE_WRITE_REG(hw, IXGBE_CTRL, (ctrl | IXGBE_CTRL_RST)); 891 IXGBE_WRITE_FLUSH(hw); 892 893 /* Poll for reset bit to self-clear indicating reset is complete */ 894 for (i = 0; i < 10; i++) { 895 usec_delay(1); 896 ctrl = IXGBE_READ_REG(hw, IXGBE_CTRL); 897 if (!(ctrl & IXGBE_CTRL_RST)) 898 break; 899 } 900 if (ctrl & IXGBE_CTRL_RST) { 901 status = IXGBE_ERR_RESET_FAILED; 902 DEBUGOUT("Reset polling failed to complete.\n"); 903 } 904 905 msec_delay(50); 906 907 gheccr = IXGBE_READ_REG(hw, IXGBE_GHECCR); 908 gheccr &= ~((1 << 21) | (1 << 18) | (1 << 9) | (1 << 6)); 909 IXGBE_WRITE_REG(hw, IXGBE_GHECCR, gheccr); 910 911 /* 912 * AUTOC register which stores link settings gets cleared 913 * and reloaded from EEPROM after reset. We need to restore 914 * our stored value from init in case SW changed the attach 915 * type or speed. If this is the first time and link settings 916 * have not been stored, store default settings from AUTOC. 917 */ 918 autoc = IXGBE_READ_REG(hw, IXGBE_AUTOC); 919 if (hw->mac.link_settings_loaded) { 920 autoc &= ~(IXGBE_AUTOC_LMS_ATTACH_TYPE); 921 autoc &= ~(IXGBE_AUTOC_LMS_MASK); 922 autoc |= hw->mac.link_attach_type; 923 autoc |= hw->mac.link_mode_select; 924 IXGBE_WRITE_REG(hw, IXGBE_AUTOC, autoc); 925 } else { 926 hw->mac.link_attach_type = 927 (autoc & IXGBE_AUTOC_LMS_ATTACH_TYPE); 928 hw->mac.link_mode_select = (autoc & IXGBE_AUTOC_LMS_MASK); 929 hw->mac.link_settings_loaded = TRUE; 930 } 931 932 /* Store the permanent mac address */ 933 hw->mac.ops.get_mac_addr(hw, hw->mac.perm_addr); 934 935 return status; 936 } 937 938 /** 939 * ixgbe_set_vmdq_82598 - Associate a VMDq set index with a rx address 940 * @hw: pointer to hardware struct 941 * @rar: receive address register index to associate with a VMDq index 942 * @vmdq: VMDq set index 943 **/ 944 s32 ixgbe_set_vmdq_82598(struct ixgbe_hw *hw, u32 rar, u32 vmdq) 945 { 946 u32 rar_high; 947 948 rar_high = IXGBE_READ_REG(hw, IXGBE_RAH(rar)); 949 rar_high &= ~IXGBE_RAH_VIND_MASK; 950 rar_high |= ((vmdq << IXGBE_RAH_VIND_SHIFT) & IXGBE_RAH_VIND_MASK); 951 IXGBE_WRITE_REG(hw, IXGBE_RAH(rar), rar_high); 952 return IXGBE_SUCCESS; 953 } 954 955 /** 956 * ixgbe_clear_vmdq_82598 - Disassociate a VMDq set index from an rx address 957 * @hw: pointer to hardware struct 958 * @rar: receive address register index to associate with a VMDq index 959 * @vmdq: VMDq clear index (not used in 82598, but elsewhere) 960 **/ 961 static s32 ixgbe_clear_vmdq_82598(struct ixgbe_hw *hw, u32 rar, u32 vmdq) 962 { 963 u32 rar_high; 964 u32 rar_entries = hw->mac.num_rar_entries; 965 966 UNREFERENCED_PARAMETER(vmdq); 967 968 if (rar < rar_entries) { 969 rar_high = IXGBE_READ_REG(hw, IXGBE_RAH(rar)); 970 if (rar_high & IXGBE_RAH_VIND_MASK) { 971 rar_high &= ~IXGBE_RAH_VIND_MASK; 972 IXGBE_WRITE_REG(hw, IXGBE_RAH(rar), rar_high); 973 } 974 } else { 975 DEBUGOUT1("RAR index %d is out of range.\n", rar); 976 } 977 978 return IXGBE_SUCCESS; 979 } 980 981 /** 982 * ixgbe_set_vfta_82598 - Set VLAN filter table 983 * @hw: pointer to hardware structure 984 * @vlan: VLAN id to write to VLAN filter 985 * @vind: VMDq output index that maps queue to VLAN id in VFTA 986 * @vlan_on: boolean flag to turn on/off VLAN in VFTA 987 * 988 * Turn on/off specified VLAN in the VLAN filter table. 989 **/ 990 s32 ixgbe_set_vfta_82598(struct ixgbe_hw *hw, u32 vlan, u32 vind, 991 bool vlan_on) 992 { 993 u32 regindex; 994 u32 bitindex; 995 u32 bits; 996 u32 vftabyte; 997 998 if (vlan > 4095) 999 return IXGBE_ERR_PARAM; 1000 1001 /* Determine 32-bit word position in array */ 1002 regindex = (vlan >> 5) & 0x7F; /* upper seven bits */ 1003 1004 /* Determine the location of the (VMD) queue index */ 1005 vftabyte = ((vlan >> 3) & 0x03); /* bits (4:3) indicating byte array */ 1006 bitindex = (vlan & 0x7) << 2; /* lower 3 bits indicate nibble */ 1007 1008 /* Set the nibble for VMD queue index */ 1009 bits = IXGBE_READ_REG(hw, IXGBE_VFTAVIND(vftabyte, regindex)); 1010 bits &= (~(0x0F << bitindex)); 1011 bits |= (vind << bitindex); 1012 IXGBE_WRITE_REG(hw, IXGBE_VFTAVIND(vftabyte, regindex), bits); 1013 1014 /* Determine the location of the bit for this VLAN id */ 1015 bitindex = vlan & 0x1F; /* lower five bits */ 1016 1017 bits = IXGBE_READ_REG(hw, IXGBE_VFTA(regindex)); 1018 if (vlan_on) 1019 /* Turn on this VLAN id */ 1020 bits |= (1 << bitindex); 1021 else 1022 /* Turn off this VLAN id */ 1023 bits &= ~(1 << bitindex); 1024 IXGBE_WRITE_REG(hw, IXGBE_VFTA(regindex), bits); 1025 1026 return IXGBE_SUCCESS; 1027 } 1028 1029 /** 1030 * ixgbe_clear_vfta_82598 - Clear VLAN filter table 1031 * @hw: pointer to hardware structure 1032 * 1033 * Clears the VLAN filer table, and the VMDq index associated with the filter 1034 **/ 1035 static s32 ixgbe_clear_vfta_82598(struct ixgbe_hw *hw) 1036 { 1037 u32 offset; 1038 u32 vlanbyte; 1039 1040 for (offset = 0; offset < hw->mac.vft_size; offset++) 1041 IXGBE_WRITE_REG(hw, IXGBE_VFTA(offset), 0); 1042 1043 for (vlanbyte = 0; vlanbyte < 4; vlanbyte++) 1044 for (offset = 0; offset < hw->mac.vft_size; offset++) 1045 IXGBE_WRITE_REG(hw, IXGBE_VFTAVIND(vlanbyte, offset), 1046 0); 1047 1048 return IXGBE_SUCCESS; 1049 } 1050 1051 /** 1052 * ixgbe_blink_led_start_82598 - Blink LED based on index. 1053 * @hw: pointer to hardware structure 1054 * @index: led number to blink 1055 **/ 1056 static s32 ixgbe_blink_led_start_82598(struct ixgbe_hw *hw, u32 index) 1057 { 1058 ixgbe_link_speed speed = 0; 1059 bool link_up = 0; 1060 u32 autoc_reg = IXGBE_READ_REG(hw, IXGBE_AUTOC); 1061 u32 led_reg = IXGBE_READ_REG(hw, IXGBE_LEDCTL); 1062 1063 /* 1064 * Link must be up to auto-blink the LEDs on the 82598EB MAC; 1065 * force it if link is down. 1066 */ 1067 hw->mac.ops.check_link(hw, &speed, &link_up, FALSE); 1068 1069 if (!link_up) { 1070 autoc_reg |= IXGBE_AUTOC_FLU; 1071 IXGBE_WRITE_REG(hw, IXGBE_AUTOC, autoc_reg); 1072 msec_delay(10); 1073 } 1074 1075 led_reg &= ~IXGBE_LED_MODE_MASK(index); 1076 led_reg |= IXGBE_LED_BLINK(index); 1077 IXGBE_WRITE_REG(hw, IXGBE_LEDCTL, led_reg); 1078 IXGBE_WRITE_FLUSH(hw); 1079 1080 return IXGBE_SUCCESS; 1081 } 1082 1083 /** 1084 * ixgbe_blink_led_stop_82598 - Stop blinking LED based on index. 1085 * @hw: pointer to hardware structure 1086 * @index: led number to stop blinking 1087 **/ 1088 static s32 ixgbe_blink_led_stop_82598(struct ixgbe_hw *hw, u32 index) 1089 { 1090 u32 autoc_reg = IXGBE_READ_REG(hw, IXGBE_AUTOC); 1091 u32 led_reg = IXGBE_READ_REG(hw, IXGBE_LEDCTL); 1092 1093 autoc_reg &= ~IXGBE_AUTOC_FLU; 1094 autoc_reg |= IXGBE_AUTOC_AN_RESTART; 1095 IXGBE_WRITE_REG(hw, IXGBE_AUTOC, autoc_reg); 1096 1097 led_reg &= ~IXGBE_LED_MODE_MASK(index); 1098 led_reg &= ~IXGBE_LED_BLINK(index); 1099 led_reg |= IXGBE_LED_LINK_ACTIVE << IXGBE_LED_MODE_SHIFT(index); 1100 IXGBE_WRITE_REG(hw, IXGBE_LEDCTL, led_reg); 1101 IXGBE_WRITE_FLUSH(hw); 1102 1103 return IXGBE_SUCCESS; 1104 } 1105 1106 /** 1107 * ixgbe_read_analog_reg8_82598 - Reads 8 bit Atlas analog register 1108 * @hw: pointer to hardware structure 1109 * @reg: analog register to read 1110 * @val: read value 1111 * 1112 * Performs read operation to Atlas analog register specified. 1113 **/ 1114 s32 ixgbe_read_analog_reg8_82598(struct ixgbe_hw *hw, u32 reg, u8 *val) 1115 { 1116 u32 atlas_ctl; 1117 1118 IXGBE_WRITE_REG(hw, IXGBE_ATLASCTL, 1119 IXGBE_ATLASCTL_WRITE_CMD | (reg << 8)); 1120 IXGBE_WRITE_FLUSH(hw); 1121 usec_delay(10); 1122 atlas_ctl = IXGBE_READ_REG(hw, IXGBE_ATLASCTL); 1123 *val = (u8)atlas_ctl; 1124 1125 return IXGBE_SUCCESS; 1126 } 1127 1128 /** 1129 * ixgbe_write_analog_reg8_82598 - Writes 8 bit Atlas analog register 1130 * @hw: pointer to hardware structure 1131 * @reg: atlas register to write 1132 * @val: value to write 1133 * 1134 * Performs write operation to Atlas analog register specified. 1135 **/ 1136 s32 ixgbe_write_analog_reg8_82598(struct ixgbe_hw *hw, u32 reg, u8 val) 1137 { 1138 u32 atlas_ctl; 1139 1140 atlas_ctl = (reg << 8) | val; 1141 IXGBE_WRITE_REG(hw, IXGBE_ATLASCTL, atlas_ctl); 1142 IXGBE_WRITE_FLUSH(hw); 1143 usec_delay(10); 1144 1145 return IXGBE_SUCCESS; 1146 } 1147 1148 /** 1149 * ixgbe_read_i2c_eeprom_82598 - Reads 8 bit word over I2C interface. 1150 * @hw: pointer to hardware structure 1151 * @byte_offset: EEPROM byte offset to read 1152 * @eeprom_data: value read 1153 * 1154 * Performs 8 byte read operation to SFP module's EEPROM over I2C interface. 1155 **/ 1156 s32 ixgbe_read_i2c_eeprom_82598(struct ixgbe_hw *hw, u8 byte_offset, 1157 u8 *eeprom_data) 1158 { 1159 s32 status = IXGBE_SUCCESS; 1160 u16 sfp_addr = 0; 1161 u16 sfp_data = 0; 1162 u16 sfp_stat = 0; 1163 u32 i; 1164 1165 if (hw->phy.type == ixgbe_phy_nl) { 1166 /* 1167 * NetLogic phy SDA/SCL registers are at addresses 0xC30A to 1168 * 0xC30D. These registers are used to talk to the SFP+ 1169 * module's EEPROM through the SDA/SCL (I2C) interface. 1170 */ 1171 sfp_addr = (IXGBE_I2C_EEPROM_DEV_ADDR << 8) + byte_offset; 1172 sfp_addr = (sfp_addr | IXGBE_I2C_EEPROM_READ_MASK); 1173 hw->phy.ops.write_reg(hw, 1174 IXGBE_MDIO_PMA_PMD_SDA_SCL_ADDR, 1175 IXGBE_MDIO_PMA_PMD_DEV_TYPE, 1176 sfp_addr); 1177 1178 /* Poll status */ 1179 for (i = 0; i < 100; i++) { 1180 hw->phy.ops.read_reg(hw, 1181 IXGBE_MDIO_PMA_PMD_SDA_SCL_STAT, 1182 IXGBE_MDIO_PMA_PMD_DEV_TYPE, 1183 &sfp_stat); 1184 sfp_stat = sfp_stat & IXGBE_I2C_EEPROM_STATUS_MASK; 1185 if (sfp_stat != IXGBE_I2C_EEPROM_STATUS_IN_PROGRESS) 1186 break; 1187 msec_delay(10); 1188 } 1189 1190 if (sfp_stat != IXGBE_I2C_EEPROM_STATUS_PASS) { 1191 DEBUGOUT("EEPROM read did not pass.\n"); 1192 status = IXGBE_ERR_SFP_NOT_PRESENT; 1193 goto out; 1194 } 1195 1196 /* Read data */ 1197 hw->phy.ops.read_reg(hw, IXGBE_MDIO_PMA_PMD_SDA_SCL_DATA, 1198 IXGBE_MDIO_PMA_PMD_DEV_TYPE, &sfp_data); 1199 1200 *eeprom_data = (u8)(sfp_data >> 8); 1201 } else { 1202 status = IXGBE_ERR_PHY; 1203 goto out; 1204 } 1205 1206 out: 1207 return status; 1208 } 1209 1210 /** 1211 * ixgbe_get_supported_physical_layer_82598 - Returns physical layer type 1212 * @hw: pointer to hardware structure 1213 * 1214 * Determines physical layer capabilities of the current configuration. 1215 **/ 1216 u32 ixgbe_get_supported_physical_layer_82598(struct ixgbe_hw *hw) 1217 { 1218 u32 physical_layer = IXGBE_PHYSICAL_LAYER_UNKNOWN; 1219 1220 switch (hw->device_id) { 1221 case IXGBE_DEV_ID_82598: 1222 /* Default device ID is mezzanine card KX/KX4 */ 1223 physical_layer = (IXGBE_PHYSICAL_LAYER_10GBASE_KX4 | 1224 IXGBE_PHYSICAL_LAYER_1000BASE_KX); 1225 break; 1226 case IXGBE_DEV_ID_82598EB_CX4: 1227 case IXGBE_DEV_ID_82598_CX4_DUAL_PORT: 1228 physical_layer = IXGBE_PHYSICAL_LAYER_10GBASE_CX4; 1229 break; 1230 case IXGBE_DEV_ID_82598_DA_DUAL_PORT: 1231 physical_layer = IXGBE_PHYSICAL_LAYER_SFP_PLUS_CU; 1232 break; 1233 case IXGBE_DEV_ID_82598AF_DUAL_PORT: 1234 case IXGBE_DEV_ID_82598AF_SINGLE_PORT: 1235 case IXGBE_DEV_ID_82598_SR_DUAL_PORT_EM: 1236 physical_layer = IXGBE_PHYSICAL_LAYER_10GBASE_SR; 1237 break; 1238 case IXGBE_DEV_ID_82598EB_XF_LR: 1239 physical_layer = IXGBE_PHYSICAL_LAYER_10GBASE_LR; 1240 break; 1241 case IXGBE_DEV_ID_82598AT: 1242 physical_layer = (IXGBE_PHYSICAL_LAYER_10GBASE_T | 1243 IXGBE_PHYSICAL_LAYER_1000BASE_T); 1244 break; 1245 case IXGBE_DEV_ID_82598EB_SFP_LOM: 1246 hw->phy.ops.identify_sfp(hw); 1247 1248 switch (hw->phy.sfp_type) { 1249 case ixgbe_sfp_type_da_cu: 1250 physical_layer = IXGBE_PHYSICAL_LAYER_SFP_PLUS_CU; 1251 break; 1252 case ixgbe_sfp_type_sr: 1253 physical_layer = IXGBE_PHYSICAL_LAYER_10GBASE_SR; 1254 break; 1255 case ixgbe_sfp_type_lr: 1256 physical_layer = IXGBE_PHYSICAL_LAYER_10GBASE_LR; 1257 break; 1258 default: 1259 physical_layer = IXGBE_PHYSICAL_LAYER_UNKNOWN; 1260 break; 1261 } 1262 break; 1263 1264 default: 1265 physical_layer = IXGBE_PHYSICAL_LAYER_UNKNOWN; 1266 break; 1267 } 1268 1269 return physical_layer; 1270 } 1271