xref: /freebsd/sys/dev/ixgbe/ixgbe_82598.c (revision 1e413cf93298b5b97441a21d9a50fdcd0ee9945e)
1 /*******************************************************************************
2 
3   Copyright (c) 2001-2007, Intel Corporation
4   All rights reserved.
5 
6   Redistribution and use in source and binary forms, with or without
7   modification, are permitted provided that the following conditions are met:
8 
9    1. Redistributions of source code must retain the above copyright notice,
10       this list of conditions and the following disclaimer.
11 
12    2. Redistributions in binary form must reproduce the above copyright
13       notice, this list of conditions and the following disclaimer in the
14       documentation and/or other materials provided with the distribution.
15 
16    3. Neither the name of the Intel Corporation nor the names of its
17       contributors may be used to endorse or promote products derived from
18       this software without specific prior written permission.
19 
20   THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
21   AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
22   IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
23   ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
24   LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
25   CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
26   SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
27   INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
28   CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
29   ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
30   POSSIBILITY OF SUCH DAMAGE.
31 
32 *******************************************************************************/
33 /* $FreeBSD$ */
34 
35 
36 #include "ixgbe_type.h"
37 #include "ixgbe_api.h"
38 #include "ixgbe_common.h"
39 #include "ixgbe_phy.h"
40 
41 #define IXGBE_82598_MAX_TX_QUEUES 32
42 #define IXGBE_82598_MAX_RX_QUEUES 64
43 #define IXGBE_82598_RAR_ENTRIES   16
44 
45 s32 ixgbe_init_shared_code_82598(struct ixgbe_hw *hw);
46 s32 ixgbe_assign_func_pointers_82598(struct ixgbe_hw *hw);
47 s32 ixgbe_get_link_settings_82598(struct ixgbe_hw *hw,
48 				  ixgbe_link_speed *speed,
49 				  bool *autoneg);
50 s32 ixgbe_get_copper_link_settings_82598(struct ixgbe_hw *hw,
51 					 ixgbe_link_speed *speed,
52 					 bool *autoneg);
53 enum ixgbe_media_type ixgbe_get_media_type_82598(struct ixgbe_hw *hw);
54 u32 ixgbe_get_num_of_tx_queues_82598(struct ixgbe_hw *hw);
55 u32 ixgbe_get_num_of_rx_queues_82598(struct ixgbe_hw *hw);
56 s32 ixgbe_setup_mac_link_82598(struct ixgbe_hw *hw);
57 s32 ixgbe_check_mac_link_82598(struct ixgbe_hw *hw,
58 			       ixgbe_link_speed *speed,
59 			       bool *link_up);
60 s32 ixgbe_setup_mac_link_speed_82598(struct ixgbe_hw *hw,
61 				     ixgbe_link_speed speed,
62 				     bool autoneg,
63 				     bool autoneg_wait_to_complete);
64 s32 ixgbe_setup_copper_link_82598(struct ixgbe_hw *hw);
65 s32 ixgbe_check_copper_link_82598(struct ixgbe_hw *hw,
66 				  ixgbe_link_speed *speed,
67 				  bool *link_up);
68 s32 ixgbe_setup_copper_link_speed_82598(struct ixgbe_hw *hw,
69 					ixgbe_link_speed speed,
70 					bool autoneg,
71 					bool autoneg_wait_to_complete);
72 #ifndef NO_82598_A0_SUPPORT
73 s32 ixgbe_reset_hw_rev_0_82598(struct ixgbe_hw *hw);
74 #endif
75 s32 ixgbe_reset_hw_82598(struct ixgbe_hw *hw);
76 u32 ixgbe_get_num_rx_addrs_82598(struct ixgbe_hw *hw);
77 s32 ixgbe_configure_fiber_serdes_fc_82598(struct ixgbe_hw *hw);
78 s32 ixgbe_setup_fiber_serdes_link_82598(struct ixgbe_hw *hw);
79 s32 ixgbe_read_analog_reg8_82598(struct ixgbe_hw *hw, u32 reg, u8 *val);
80 s32 ixgbe_write_analog_reg8_82598(struct ixgbe_hw *hw, u32 reg, u8 val);
81 
82 
83 /**
84  *  ixgbe_init_shared_code_82598 - Inits func ptrs and MAC type
85  *  @hw: pointer to hardware structure
86  *
87  *  Initialize the shared code for 82598. This will assign function pointers
88  *  and assign the MAC type.  Does not touch the hardware.
89  **/
90 s32 ixgbe_init_shared_code_82598(struct ixgbe_hw *hw)
91 {
92 	/* Assign function pointers */
93 	ixgbe_assign_func_pointers_82598(hw);
94 
95 	return IXGBE_SUCCESS;
96 }
97 
98 /**
99  *  ixgbe_assign_func_pointers_82598 - Assigns 82598-specific funtion pointers
100  *  @hw: pointer to hardware structure
101  *
102  *  Note - Generic function pointers have already been assigned, so the
103  *  function pointers set here are only for 82598-specific functions.
104  **/
105 s32 ixgbe_assign_func_pointers_82598(struct ixgbe_hw *hw)
106 {
107 
108 	hw->func.ixgbe_func_get_media_type =
109 			       &ixgbe_get_media_type_82598;
110 	hw->func.ixgbe_func_get_num_of_tx_queues =
111 			       &ixgbe_get_num_of_tx_queues_82598;
112 	hw->func.ixgbe_func_get_num_of_rx_queues =
113 			       &ixgbe_get_num_of_rx_queues_82598;
114 	hw->func.ixgbe_func_read_analog_reg8 =
115 			       &ixgbe_read_analog_reg8_82598;
116 	hw->func.ixgbe_func_write_analog_reg8 =
117 			       &ixgbe_write_analog_reg8_82598;
118 #ifndef NO_82598_A0_SUPPORT
119 	if (hw->revision_id == 0) {
120 		hw->func.ixgbe_func_reset_hw =
121 			       &ixgbe_reset_hw_rev_0_82598;
122 	} else {
123 		hw->func.ixgbe_func_reset_hw = &ixgbe_reset_hw_82598;
124 	}
125 #else
126 	hw->func.ixgbe_func_reset_hw = &ixgbe_reset_hw_82598;
127 #endif
128 
129 	hw->func.ixgbe_func_get_num_rx_addrs =
130 			       &ixgbe_get_num_rx_addrs_82598;
131 
132 	/* Link */
133 	if (ixgbe_get_media_type(hw) == ixgbe_media_type_copper) {
134 		hw->func.ixgbe_func_setup_link =
135 			       &ixgbe_setup_copper_link_82598;
136 		hw->func.ixgbe_func_check_link =
137 			       &ixgbe_check_copper_link_82598;
138 		hw->func.ixgbe_func_setup_link_speed =
139 			       &ixgbe_setup_copper_link_speed_82598;
140 		hw->func.ixgbe_func_get_link_settings =
141 			       &ixgbe_get_copper_link_settings_82598;
142 	} else {
143 		hw->func.ixgbe_func_setup_link =
144 			       &ixgbe_setup_mac_link_82598;
145 		hw->func.ixgbe_func_check_link =
146 			       &ixgbe_check_mac_link_82598;
147 		hw->func.ixgbe_func_setup_link_speed =
148 			       &ixgbe_setup_mac_link_speed_82598;
149 		hw->func.ixgbe_func_get_link_settings =
150 			       &ixgbe_get_link_settings_82598;
151 	}
152 
153 	return IXGBE_SUCCESS;
154 }
155 
156 /**
157  *  ixgbe_get_link_settings_82598 - Determines default link settings
158  *  @hw: pointer to hardware structure
159  *  @speed: pointer to link speed
160  *  @autoneg: boolean auto-negotiation value
161  *
162  *  Determines the default link settings by reading the AUTOC register.
163  **/
164 s32 ixgbe_get_link_settings_82598(struct ixgbe_hw *hw, ixgbe_link_speed *speed,
165 				  bool *autoneg)
166 {
167 	s32 status = IXGBE_SUCCESS;
168 	s32 autoc_reg;
169 
170 	autoc_reg = IXGBE_READ_REG(hw, IXGBE_AUTOC);
171 
172 	if (hw->mac.link_settings_loaded) {
173 		autoc_reg &= ~IXGBE_AUTOC_LMS_ATTACH_TYPE;
174 		autoc_reg &= ~IXGBE_AUTOC_LMS_MASK;
175 		autoc_reg |= hw->mac.link_attach_type;
176 		autoc_reg |= hw->mac.link_mode_select;
177 	}
178 
179 	switch (autoc_reg & IXGBE_AUTOC_LMS_MASK) {
180 	case IXGBE_AUTOC_LMS_1G_LINK_NO_AN:
181 		*speed = IXGBE_LINK_SPEED_1GB_FULL;
182 		*autoneg = FALSE;
183 		break;
184 
185 	case IXGBE_AUTOC_LMS_10G_LINK_NO_AN:
186 		*speed = IXGBE_LINK_SPEED_10GB_FULL;
187 		*autoneg = FALSE;
188 		break;
189 
190 	case IXGBE_AUTOC_LMS_1G_AN:
191 		*speed = IXGBE_LINK_SPEED_1GB_FULL;
192 		*autoneg = TRUE;
193 		break;
194 
195 	case IXGBE_AUTOC_LMS_KX4_AN:
196 	case IXGBE_AUTOC_LMS_KX4_AN_1G_AN:
197 		*speed = IXGBE_LINK_SPEED_UNKNOWN;
198 		if (autoc_reg & IXGBE_AUTOC_KX4_SUPP) {
199 			*speed |= IXGBE_LINK_SPEED_10GB_FULL;
200 		}
201 		if (autoc_reg & IXGBE_AUTOC_KX_SUPP) {
202 			*speed |= IXGBE_LINK_SPEED_1GB_FULL;
203 		}
204 		*autoneg = TRUE;
205 		break;
206 
207 	default:
208 		status = IXGBE_ERR_LINK_SETUP;
209 		break;
210 	}
211 
212 	return status;
213 }
214 
215 /**
216  *  ixgbe_get_copper_link_settings_82598 - Determines default link settings
217  *  @hw: pointer to hardware structure
218  *  @speed: pointer to link speed
219  *  @autoneg: boolean auto-negotiation value
220  *
221  *  Determines the default link settings by reading the AUTOC register.
222  **/
223 s32 ixgbe_get_copper_link_settings_82598(struct ixgbe_hw *hw,
224 					 ixgbe_link_speed *speed,
225 					 bool *autoneg)
226 {
227 	s32 status = IXGBE_ERR_LINK_SETUP;
228 	u16 speed_ability;
229 
230 	*speed = 0;
231 	*autoneg = TRUE;
232 
233 	status = ixgbe_read_phy_reg(hw, IXGBE_MDIO_PHY_SPEED_ABILITY,
234 				    IXGBE_MDIO_PMA_PMD_DEV_TYPE,
235 				    &speed_ability);
236 
237 	if (status == IXGBE_SUCCESS) {
238 		if (speed_ability & IXGBE_MDIO_PHY_SPEED_10G)
239 		    *speed |= IXGBE_LINK_SPEED_10GB_FULL;
240 		if (speed_ability & IXGBE_MDIO_PHY_SPEED_1G)
241 		    *speed |= IXGBE_LINK_SPEED_1GB_FULL;
242 	}
243 
244 	return status;
245 }
246 
247 /**
248  *  ixgbe_get_media_type_82598 - Determines media type
249  *  @hw: pointer to hardware structure
250  *
251  *  Returns the media type (fiber, copper, backplane)
252  **/
253 enum ixgbe_media_type ixgbe_get_media_type_82598(struct ixgbe_hw *hw)
254 {
255 	enum ixgbe_media_type media_type;
256 
257 	/* Media type for I82598 is based on device ID */
258 	switch (hw->device_id) {
259 	case IXGBE_DEV_ID_82598AF_DUAL_PORT:
260 	case IXGBE_DEV_ID_82598AF_SINGLE_PORT:
261 	case IXGBE_DEV_ID_82598EB_CX4:
262 		media_type = ixgbe_media_type_fiber;
263 		break;
264 	default:
265 		media_type = ixgbe_media_type_unknown;
266 		break;
267 	}
268 
269 	return media_type;
270 }
271 
272 /**
273  *  ixgbe_get_num_of_tx_queues_82598 - Get number of TX queues
274  *  @hw: pointer to hardware structure
275  *
276  *  Returns the number of transmit queues for the given adapter.
277  **/
278 u32 ixgbe_get_num_of_tx_queues_82598(struct ixgbe_hw *hw)
279 {
280 	return IXGBE_82598_MAX_TX_QUEUES;
281 }
282 
283 /**
284  *  ixgbe_get_num_of_rx_queues_82598 - Get number of RX queues
285  *  @hw: pointer to hardware structure
286  *
287  *  Returns the number of receive queues for the given adapter.
288  **/
289 u32 ixgbe_get_num_of_rx_queues_82598(struct ixgbe_hw *hw)
290 {
291 	return IXGBE_82598_MAX_RX_QUEUES;
292 }
293 
294 /**
295  *  ixgbe_setup_mac_link_82598 - Configures MAC link settings
296  *  @hw: pointer to hardware structure
297  *
298  *  Configures link settings based on values in the ixgbe_hw struct.
299  *  Restarts the link.  Performs autonegotiation if needed.
300  **/
301 s32 ixgbe_setup_mac_link_82598(struct ixgbe_hw *hw)
302 {
303 	ixgbe_link_speed speed;
304 	bool link_up;
305 	u32 autoc_reg;
306 	u32 links_reg;
307 	u32 i;
308 	s32 status = IXGBE_SUCCESS;
309 
310 	autoc_reg = IXGBE_READ_REG(hw, IXGBE_AUTOC);
311 
312 	if (hw->mac.link_settings_loaded) {
313 		autoc_reg &= ~IXGBE_AUTOC_LMS_ATTACH_TYPE;
314 		autoc_reg &= ~IXGBE_AUTOC_LMS_MASK;
315 		autoc_reg |= hw->mac.link_attach_type;
316 		autoc_reg |= hw->mac.link_mode_select;
317 
318 		IXGBE_WRITE_REG(hw, IXGBE_AUTOC, autoc_reg);
319 		msec_delay(50);
320 	}
321 
322 	/* Restart link */
323 	autoc_reg |= IXGBE_AUTOC_AN_RESTART;
324 	IXGBE_WRITE_REG(hw, IXGBE_AUTOC, autoc_reg);
325 
326 	/* Only poll for autoneg to complete if specified to do so */
327 	if (hw->phy.autoneg_wait_to_complete) {
328 		if (hw->mac.link_mode_select == IXGBE_AUTOC_LMS_KX4_AN ||
329 		    hw->mac.link_mode_select == IXGBE_AUTOC_LMS_KX4_AN_1G_AN) {
330 			links_reg = 0; /* Just in case Autoneg time = 0 */
331 			for (i = 0; i < IXGBE_AUTO_NEG_TIME; i++) {
332 				links_reg = IXGBE_READ_REG(hw, IXGBE_LINKS);
333 				if (links_reg & IXGBE_LINKS_KX_AN_COMP)
334 					break;
335 				msec_delay(100);
336 			}
337 			if (!(links_reg & IXGBE_LINKS_KX_AN_COMP)) {
338 				status = IXGBE_ERR_AUTONEG_NOT_COMPLETE;
339 				DEBUGOUT("Autonegotiation did not complete.\n");
340 			}
341 		}
342 	}
343 
344 	/*
345 	 * We want to save off the original Flow Control configuration just in
346 	 * case we get disconnected and then reconnected into a different hub
347 	 * or switch with different Flow Control capabilities.
348 	 */
349 	hw->fc.type = hw->fc.original_type;
350 	/*
351 	 * Set up the SerDes link if in 1Gb mode, otherwise just set up
352 	 * 10Gb flow control.
353 	 */
354 	ixgbe_check_link(hw, &speed, &link_up);
355 	if (speed == IXGBE_LINK_SPEED_1GB_FULL)
356 		status = ixgbe_setup_fiber_serdes_link_82598(hw);
357 	else
358 		ixgbe_setup_fc_generic(hw, 0);
359 
360 	/* Add delay to filter out noises during initial link setup */
361 	msec_delay(50);
362 
363 	return status;
364 }
365 
366 /**
367  *  ixgbe_check_mac_link_82598 - Get link/speed status
368  *  @hw: pointer to hardware structure
369  *  @speed: pointer to link speed
370  *  @link_up: TRUE is link is up, FALSE otherwise
371  *
372  *  Reads the links register to determine if link is up and the current speed
373  **/
374 s32 ixgbe_check_mac_link_82598(struct ixgbe_hw *hw, ixgbe_link_speed *speed,
375 			       bool *link_up)
376 {
377 	u32 links_reg;
378 
379 	links_reg = IXGBE_READ_REG(hw, IXGBE_LINKS);
380 
381 	if (links_reg & IXGBE_LINKS_UP)
382 		*link_up = TRUE;
383 	else
384 		*link_up = FALSE;
385 
386 	if (links_reg & IXGBE_LINKS_SPEED)
387 		*speed = IXGBE_LINK_SPEED_10GB_FULL;
388 	else
389 		*speed = IXGBE_LINK_SPEED_1GB_FULL;
390 
391 	return IXGBE_SUCCESS;
392 }
393 
394 /**
395  *  ixgbe_configure_fiber_serdes_fc_82598 - Configure fiber flow control
396  *  @hw: pointer to hardware structure
397  *
398  *  Reads PCS registers and sets flow control settings, based on
399  *  link-partner's abilities.
400  **/
401 s32 ixgbe_configure_fiber_serdes_fc_82598(struct ixgbe_hw *hw)
402 {
403 	s32 ret_val = IXGBE_SUCCESS;
404 	u32 delay = 300, pcs_anadv_reg, pcs_lpab_reg, pcs_lstat_reg, i;
405 
406 	DEBUGFUNC("ixgbe_configure_fiber_serdes_fc_82598");
407 
408 	/* Check that autonegotiation has completed */
409 	for (i = 0; i < FIBER_LINK_UP_LIMIT; i++) {
410 		/*
411 		 * Delay 300msec before reading PCS1GLSTA.  Reading PCS1GLSTA
412 		 * before then will sometimes result in AN_COMPLETE not being
413 		 * set.
414 		 */
415 		msec_delay(delay);
416 		pcs_lstat_reg = IXGBE_READ_REG(hw, IXGBE_PCS1GLSTA);
417 		if (pcs_lstat_reg & IXGBE_PCS1GLSTA_AN_COMPLETE) {
418 			if (pcs_lstat_reg & (IXGBE_PCS1GLSTA_LINK_OK)) {
419 				if (!(pcs_lstat_reg &
420 				    (IXGBE_PCS1GLSTA_AN_TIMED_OUT)))
421 					hw->mac.autoneg_failed = 0;
422 				else
423 					hw->mac.autoneg_failed = 1;
424 				break;
425 			} else {
426 				hw->mac.autoneg_failed = 1;
427 				break;
428 			}
429 		}
430 
431 		/*
432 		 * Increment the delay time by 50ms to wait before reading
433 		 * PCS1GLSTA again.
434 		 */
435 		delay += 50;
436 	}
437 
438 	if (i == FIBER_LINK_UP_LIMIT)
439 		hw->mac.autoneg_failed = 1;
440 
441 	if (hw->mac.autoneg_failed) {
442 		/*
443 		 * AutoNeg failed to achieve a link, so we will turn
444 		 * flow control off.
445 		 */
446 		hw->fc.type = ixgbe_fc_none;
447 		DEBUGOUT("Flow Control = NONE.\n");
448 		ret_val = ixgbe_setup_fc_generic(hw, 0);
449 		goto out;
450 	}
451 
452 	/*
453 	 * Read the AN advertisement and LP ability registers and resolve
454 	 * local flow control settings accordingly
455 	 */
456 	pcs_anadv_reg = IXGBE_READ_REG(hw, IXGBE_PCS1GANA);
457 	pcs_lpab_reg = IXGBE_READ_REG(hw, IXGBE_PCS1GANLP);
458 	if ((pcs_anadv_reg & IXGBE_PCS1GANA_SYM_PAUSE) &&
459 		(pcs_lpab_reg & IXGBE_PCS1GANA_SYM_PAUSE)) {
460 		/*
461 		 * Now we need to check if the user selected RX ONLY
462 		 * of pause frames.  In this case, we had to advertise
463 		 * FULL flow control because we could not advertise RX
464 		 * ONLY. Hence, we must now check to see if we need to
465 		 * turn OFF  the TRANSMISSION of PAUSE frames.
466 		 */
467 		if (hw->fc.original_type == ixgbe_fc_full) {
468 			hw->fc.type = ixgbe_fc_full;
469 			DEBUGOUT("Flow Control = FULL.\n");
470 		} else {
471 			hw->fc.type = ixgbe_fc_rx_pause;
472 			DEBUGOUT("Flow Control = RX PAUSE frames only.\n");
473 		}
474 	} else if (!(pcs_anadv_reg & IXGBE_PCS1GANA_SYM_PAUSE) &&
475 		  (pcs_anadv_reg & IXGBE_PCS1GANA_ASM_PAUSE) &&
476 		  (pcs_lpab_reg & IXGBE_PCS1GANA_SYM_PAUSE) &&
477 		  (pcs_lpab_reg & IXGBE_PCS1GANA_ASM_PAUSE)) {
478 		hw->fc.type = ixgbe_fc_tx_pause;
479 		DEBUGOUT("Flow Control = TX PAUSE frames only.\n");
480 	} else if ((pcs_anadv_reg & IXGBE_PCS1GANA_SYM_PAUSE) &&
481 		  (pcs_anadv_reg & IXGBE_PCS1GANA_ASM_PAUSE) &&
482 		  !(pcs_lpab_reg & IXGBE_PCS1GANA_SYM_PAUSE) &&
483 		  (pcs_lpab_reg & IXGBE_PCS1GANA_ASM_PAUSE)) {
484 		hw->fc.type = ixgbe_fc_rx_pause;
485 		DEBUGOUT("Flow Control = RX PAUSE frames only.\n");
486 	} else if ((hw->fc.original_type == ixgbe_fc_none ||
487 		  hw->fc.original_type == ixgbe_fc_tx_pause) ||
488 		  hw->fc.strict_ieee) {
489 		hw->fc.type = ixgbe_fc_none;
490 		DEBUGOUT("Flow Control = NONE.\n");
491 	} else {
492 		hw->fc.type = ixgbe_fc_rx_pause;
493 		DEBUGOUT("Flow Control = RX PAUSE frames only.\n");
494 	}
495 
496 	ret_val = ixgbe_setup_fc_generic(hw, 0);
497 	if (ret_val) {
498 		DEBUGOUT("Error forcing flow control settings\n");
499 		goto out;
500 	}
501 
502 out:
503 	return ret_val;
504 }
505 
506 /**
507  *  ixgbe_setup_fiber_serdes_link_82598 - Configure fiber serdes link
508  *  @hw: pointer to hardware structure
509  *
510  *  Sets up PCS registers and sets flow control settings, based on
511  *  link-partner's abilities.
512  **/
513 s32 ixgbe_setup_fiber_serdes_link_82598(struct ixgbe_hw *hw)
514 {
515 	u32 reg;
516 	s32 ret_val;
517 
518 	DEBUGFUNC("ixgbe_setup_fiber_serdes_link_82598");
519 
520 	/*
521 	 * 82598 fiber/serdes devices require that flow control be resolved in
522 	 * software.  Set up flow control advertisement if autoneg is enabled.
523 	 */
524 	if (hw->mac.autoneg) {
525 		reg = IXGBE_READ_REG(hw, IXGBE_PCS1GANA);
526 
527 		/*
528 		 * Check for a software override of the flow control settings,
529 		 * and setup the device accordingly.  If auto-negotiation is
530 		 * enabled, then software will have to set the "PAUSE" bits to
531 		 * the correct value and re-start auto- negotiation.  However,
532 		 * if auto-negotiation is disabled, then software will have to
533 		 * manually configure flow control.
534 		 *
535 		 * The possible values of the "fc" parameter are:
536 		 * 0:  Flow control is completely disabled
537 		 * 1:  Rx flow control is enabled (we can receive pause frames,
538 		 *     but not send pause frames).
539 		 * 2:  Tx flow control is enabled (we can send pause frames but
540 		 *     we do not support receiving pause frames).
541 		 * 3:  Both Rx and TX flow control (symmetric) are enabled.
542 		 */
543 
544 		switch (hw->fc.type) {
545 		case ixgbe_fc_none:
546 			/*
547 			 * Flow control completely disabled by a software
548 			 * over-ride.
549 			 */
550 			reg &= ~(IXGBE_PCS1GANA_SYM_PAUSE |
551 				IXGBE_PCS1GANA_ASM_PAUSE);
552 			break;
553 			case ixgbe_fc_rx_pause:
554 			/*
555 			 * RX Flow control is enabled and TX Flow control is
556 			 * disabled by a software over-ride. Since there really
557 			 * isn't a way to advertise that we are capable of RX
558 			 * Pause ONLY, we will advertise that we support both
559 			 * symmetric and asymmetric RX PAUSE.  Later, we will
560 			 * disable the adapter's ability to send PAUSE frames.
561 			 */
562 			reg |= (IXGBE_PCS1GANA_SYM_PAUSE |
563 				IXGBE_PCS1GANA_ASM_PAUSE);
564 			break;
565 		case ixgbe_fc_tx_pause:
566 			/*
567 			 * TX Flow control is enabled, and RX Flow control is
568 			 * disabled, by a software over-ride.
569 			 */
570 			reg |= (IXGBE_PCS1GANA_ASM_PAUSE);
571 			reg &= ~(IXGBE_PCS1GANA_SYM_PAUSE);
572 			break;
573 		case ixgbe_fc_full:
574 			/*
575 			 * Flow control (both RX and TX) is enabled by a
576 			 * software over-ride.
577 			 */
578 			reg |= (IXGBE_PCS1GANA_SYM_PAUSE |
579 				IXGBE_PCS1GANA_ASM_PAUSE);
580 			break;
581 		default:
582 			DEBUGOUT("Flow control param set incorrectly\n");
583 			ret_val = -IXGBE_ERR_CONFIG;
584 			goto out;
585 			break;
586 		}
587 
588 		IXGBE_WRITE_REG(hw, IXGBE_PCS1GANA, reg);
589 	}
590 
591 	/*
592 	 * New SerDes mode allows for forcing speed or autonegotiating speed
593 	 * at 1gb. Autoneg should be default set by most drivers. This is the
594 	 * mode that will be compatible with older link partners and switches.
595 	 * However, both are supported by the hardware and some drivers/tools.
596 	 */
597 	reg = IXGBE_READ_REG(hw, IXGBE_PCS1GLCTL);
598 	reg &= ~(IXGBE_PCS1GLCTL_AN_1G_TIMEOUT_EN);
599 
600 	if (hw->mac.autoneg) {
601 		/* Set PCS register for autoneg */
602 		reg |= IXGBE_PCS1GLCTL_AN_ENABLE |      /* Enable Autoneg */
603 			IXGBE_PCS1GLCTL_AN_RESTART;     /* Restart autoneg */
604 		DEBUGOUT1("Configuring Autoneg; PCS_LCTL = 0x%08X\n", reg);
605 	} else {
606 		/* Set PCS register for forced speed */
607 		reg |= IXGBE_PCS1GLCTL_FLV_LINK_UP |   /* Force link up */
608 			IXGBE_PCS1GLCTL_FORCE_LINK;    /* Force Link */
609 		DEBUGOUT1("Configuring Forced Link; PCS_LCTL = 0x%08X\n", reg);
610 	}
611 	IXGBE_WRITE_REG(hw, IXGBE_PCS1GLCTL, reg);
612 
613 	/*
614 	 * Configure flow control. If we aren't auto-negotiating,
615 	 * just setup the flow control and do not worry about PCS autoneg.
616 	 */
617 	if (hw->mac.autoneg)
618 		ixgbe_configure_fiber_serdes_fc_82598(hw);
619 
620 out:
621 	return IXGBE_SUCCESS;
622 }
623 
624 /**
625  *  ixgbe_setup_mac_link_speed_82598 - Set MAC link speed
626  *  @hw: pointer to hardware structure
627  *  @speed: new link speed
628  *  @autoneg: TRUE if auto-negotiation enabled
629  *  @autoneg_wait_to_complete: TRUE if waiting is needed to complete
630  *
631  *  Set the link speed in the AUTOC register and restarts link.
632  **/
633 s32 ixgbe_setup_mac_link_speed_82598(struct ixgbe_hw *hw,
634 				     ixgbe_link_speed speed, bool autoneg,
635 				     bool autoneg_wait_to_complete)
636 {
637 	s32 status = IXGBE_SUCCESS;
638 
639 	/* If speed is 10G, then check for CX4 or XAUI. */
640 	if ((speed == IXGBE_LINK_SPEED_10GB_FULL) &&
641 	    (!(hw->mac.link_attach_type & IXGBE_AUTOC_10G_KX4)))
642 		hw->mac.link_mode_select = IXGBE_AUTOC_LMS_10G_LINK_NO_AN;
643 	else if ((speed == IXGBE_LINK_SPEED_1GB_FULL) && (!autoneg))
644 		hw->mac.link_mode_select = IXGBE_AUTOC_LMS_1G_LINK_NO_AN;
645 	else if (autoneg) {
646 		/* BX mode - Autonegotiate 1G */
647 		if (!(hw->mac.link_attach_type & IXGBE_AUTOC_1G_PMA_PMD))
648 			hw->mac.link_mode_select = IXGBE_AUTOC_LMS_1G_AN;
649 		else /* KX/KX4 mode */
650 			hw->mac.link_mode_select = IXGBE_AUTOC_LMS_KX4_AN_1G_AN;
651 	} else {
652 		status = IXGBE_ERR_LINK_SETUP;
653 	}
654 
655 	if (status == IXGBE_SUCCESS) {
656 		hw->phy.autoneg_wait_to_complete = autoneg_wait_to_complete;
657 
658 		hw->mac.link_settings_loaded = TRUE;
659 		/*
660 		 * Setup and restart the link based on the new values in
661 		 * ixgbe_hw This will write the AUTOC register based on the new
662 		 * stored values
663 		 */
664 		ixgbe_setup_mac_link_82598(hw);
665 	}
666 
667 	return status;
668 }
669 
670 
671 /**
672  *  ixgbe_setup_copper_link_82598 - Setup copper link settings
673  *  @hw: pointer to hardware structure
674  *
675  *  Configures link settings based on values in the ixgbe_hw struct.
676  *  Restarts the link.  Performs autonegotiation if needed.  Restart
677  *  phy and wait for autonegotiate to finish.  Then synchronize the
678  *  MAC and PHY.
679  **/
680 s32 ixgbe_setup_copper_link_82598(struct ixgbe_hw *hw)
681 {
682 	s32 status;
683 	ixgbe_link_speed speed = 0;
684 	bool link_up = FALSE;
685 
686 	/* Set up MAC */
687 	ixgbe_setup_mac_link_82598(hw);
688 
689 	/* Restart autonegotiation on PHY */
690 	status = ixgbe_setup_phy_link(hw);
691 
692 	/* Synchronize MAC to PHY speed */
693 	if (status == IXGBE_SUCCESS)
694 		status = ixgbe_check_link(hw, &speed, &link_up);
695 
696 	return status;
697 }
698 
699 /**
700  *  ixgbe_check_copper_link_82598 - Syncs MAC & PHY link settings
701  *  @hw: pointer to hardware structure
702  *  @speed: pointer to link speed
703  *  @link_up: TRUE if link is up, FALSE otherwise
704  *
705  *  Reads the mac link, phy link, and synchronizes the MAC to PHY.
706  **/
707 s32 ixgbe_check_copper_link_82598(struct ixgbe_hw *hw, ixgbe_link_speed *speed,
708 				  bool *link_up)
709 {
710 	s32 status;
711 	ixgbe_link_speed phy_speed = 0;
712 	bool phy_link = FALSE;
713 
714 	/* This is the speed and link the MAC is set at */
715 	ixgbe_check_mac_link_82598(hw, speed, link_up);
716 
717 	/*
718 	 * Check current speed and link status of the PHY register.
719 	 * This is a vendor specific register and may have to
720 	 * be changed for other copper PHYs.
721 	 */
722 	status = ixgbe_check_phy_link(hw, &phy_speed, &phy_link);
723 
724 	if ((status == IXGBE_SUCCESS) && (phy_link)) {
725 		/*
726 		 * Check current link status of the MACs link's register
727 		 * matches that of the speed in the PHY register
728 		 */
729 		if (*speed != phy_speed) {
730 			/*
731 			 * The copper PHY requires 82598 attach type to be XAUI
732 			 * for 10G and BX for 1G
733 			 */
734 			hw->mac.link_attach_type =
735 				(IXGBE_AUTOC_10G_XAUI | IXGBE_AUTOC_1G_BX);
736 
737 			/* Synchronize the MAC speed to the PHY speed */
738 			status = ixgbe_setup_mac_link_speed_82598(hw, phy_speed,
739 								  FALSE, FALSE);
740 			if (status == IXGBE_SUCCESS)
741 				ixgbe_check_mac_link_82598(hw, speed, link_up);
742 			else
743 				status = IXGBE_ERR_LINK_SETUP;
744 		}
745 	} else {
746 		*link_up = phy_link;
747 	}
748 
749 	return status;
750 }
751 
752 /**
753  *  ixgbe_setup_copper_link_speed_82598 - Set the PHY autoneg advertised field
754  *  @hw: pointer to hardware structure
755  *  @speed: new link speed
756  *  @autoneg: TRUE if autonegotiation enabled
757  *  @autoneg_wait_to_complete: TRUE if waiting is needed to complete
758  *
759  *  Sets the link speed in the AUTOC register in the MAC and restarts link.
760  **/
761 s32 ixgbe_setup_copper_link_speed_82598(struct ixgbe_hw *hw,
762 					ixgbe_link_speed speed,
763 					bool autoneg,
764 					bool autoneg_wait_to_complete)
765 {
766 	s32 status;
767 	bool link_up = 0;
768 
769 	/* Setup the PHY according to input speed */
770 	status = ixgbe_setup_phy_link_speed(hw, speed, autoneg,
771 					    autoneg_wait_to_complete);
772 
773 	/* Synchronize MAC to PHY speed */
774 	if (status == IXGBE_SUCCESS)
775 		status = ixgbe_check_link(hw, &speed, &link_up);
776 
777 	return status;
778 }
779 
780 #ifndef NO_82598_A0_SUPPORT
781 /**
782  *  ixgbe_reset_hw_rev_0_82598 - Performs hardware reset
783  *  @hw: pointer to hardware structure
784  *
785  *  Resets the hardware by reseting the transmit and receive units, masks and
786  *  clears all interrupts, performing a PHY reset, and performing a link (MAC)
787  *  reset.
788  **/
789 s32 ixgbe_reset_hw_rev_0_82598(struct ixgbe_hw *hw)
790 {
791 	s32 status = IXGBE_SUCCESS;
792 	u32 ctrl;
793 	u32 gheccr;
794 	u32 autoc;
795 	u32 i;
796 	u32 resets;
797 
798 	/* Call adapter stop to disable tx/rx and clear interrupts */
799 	ixgbe_stop_adapter(hw);
800 
801 	/* Reset PHY */
802 	ixgbe_reset_phy(hw);
803 
804 	for (resets = 0; resets < 10; resets++) {
805 		/*
806 		 * Prevent the PCI-E bus from from hanging by disabling PCI-E
807 		 * master access and verify no pending requests before reset
808 		 */
809 		if (ixgbe_disable_pcie_master(hw) != IXGBE_SUCCESS) {
810 			status = IXGBE_ERR_MASTER_REQUESTS_PENDING;
811 			DEBUGOUT("PCI-E Master disable polling has failed.\n");
812 		}
813 
814 		/*
815 		 * Issue global reset to the MAC.  This needs to be a SW reset.
816 		 * If link reset is used, it might reset the MAC when mng is
817 		 * using it.
818 		 */
819 		ctrl = IXGBE_READ_REG(hw, IXGBE_CTRL);
820 		IXGBE_WRITE_REG(hw, IXGBE_CTRL, (ctrl | IXGBE_CTRL_RST));
821 		IXGBE_WRITE_FLUSH(hw);
822 
823 		/*
824 		 * Poll for reset bit to self-clear indicating reset is
825 		 * complete
826 		 */
827 		for (i = 0; i < 10; i++) {
828 			usec_delay(1);
829 			ctrl = IXGBE_READ_REG(hw, IXGBE_CTRL);
830 			if (!(ctrl & IXGBE_CTRL_RST))
831 				break;
832 		}
833 		if (ctrl & IXGBE_CTRL_RST) {
834 			status = IXGBE_ERR_RESET_FAILED;
835 			DEBUGOUT("Reset polling failed to complete.\n");
836 		}
837 	}
838 
839 	msec_delay(50);
840 
841 	gheccr = IXGBE_READ_REG(hw, IXGBE_GHECCR);
842 	gheccr &= ~((1 << 21) | (1 << 18) | (1 << 9) | (1 << 6));
843 	IXGBE_WRITE_REG(hw, IXGBE_GHECCR, gheccr);
844 
845 	/*
846 	 * AUTOC register which stores link settings gets cleared
847 	 * and reloaded from EEPROM after reset. We need to restore
848 	 * our stored value from init in case SW changed the attach
849 	 * type or speed.  If this is the first time and link settings
850 	 * have not been stored, store default settings from AUTOC.
851 	 */
852 	autoc = IXGBE_READ_REG(hw, IXGBE_AUTOC);
853 	if (hw->mac.link_settings_loaded) {
854 		autoc &= ~(IXGBE_AUTOC_LMS_ATTACH_TYPE);
855 		autoc &= ~(IXGBE_AUTOC_LMS_MASK);
856 		autoc |= hw->mac.link_attach_type;
857 		autoc |= hw->mac.link_mode_select;
858 		IXGBE_WRITE_REG(hw, IXGBE_AUTOC, autoc);
859 	} else {
860 		hw->mac.link_attach_type =
861 					 (autoc & IXGBE_AUTOC_LMS_ATTACH_TYPE);
862 		hw->mac.link_mode_select = (autoc & IXGBE_AUTOC_LMS_MASK);
863 		hw->mac.link_settings_loaded = TRUE;
864 	}
865 
866 	/* Store the permanent mac address */
867 	ixgbe_get_mac_addr(hw, hw->mac.perm_addr);
868 
869 	return status;
870 }
871 
872 #endif /* NO_A0_SUPPORT */
873 /**
874  *  ixgbe_reset_hw_82598 - Performs hardware reset
875  *  @hw: pointer to hardware structure
876  *
877  *  Resets the hardware by reseting the transmit and receive units, masks and
878  *  clears all interrupts, performing a PHY reset, and performing a link (MAC)
879  *  reset.
880  **/
881 s32 ixgbe_reset_hw_82598(struct ixgbe_hw *hw)
882 {
883 	s32 status = IXGBE_SUCCESS;
884 	u32 ctrl;
885 	u32 gheccr;
886 	u32 i;
887 	u32 autoc;
888 	u8  analog_val;
889 
890 	/* Call adapter stop to disable tx/rx and clear interrupts */
891 	ixgbe_stop_adapter(hw);
892 
893 	/*
894 	 * Power up the Atlas TX lanes if they are currently powered down.
895 	 * Atlas TX lanes are powered down for MAC loopback tests, but
896 	 * they are not automatically restored on reset.
897 	 */
898 	ixgbe_read_analog_reg8(hw, IXGBE_ATLAS_PDN_LPBK, &analog_val);
899 	if (analog_val & IXGBE_ATLAS_PDN_TX_REG_EN) {
900 		/* Enable TX Atlas so packets can be transmitted again */
901 		ixgbe_read_analog_reg8(hw, IXGBE_ATLAS_PDN_LPBK, &analog_val);
902 		analog_val &= ~IXGBE_ATLAS_PDN_TX_REG_EN;
903 		ixgbe_write_analog_reg8(hw, IXGBE_ATLAS_PDN_LPBK, analog_val);
904 
905 		ixgbe_read_analog_reg8(hw, IXGBE_ATLAS_PDN_10G, &analog_val);
906 		analog_val &= ~ IXGBE_ATLAS_PDN_TX_10G_QL_ALL;
907 		ixgbe_write_analog_reg8(hw, IXGBE_ATLAS_PDN_10G, analog_val);
908 
909 		ixgbe_read_analog_reg8(hw, IXGBE_ATLAS_PDN_1G, &analog_val);
910 		analog_val &= ~IXGBE_ATLAS_PDN_TX_1G_QL_ALL;
911 		ixgbe_write_analog_reg8(hw, IXGBE_ATLAS_PDN_1G, analog_val);
912 
913 		ixgbe_read_analog_reg8(hw, IXGBE_ATLAS_PDN_AN, &analog_val);
914 		analog_val &= ~IXGBE_ATLAS_PDN_TX_AN_QL_ALL;
915 		ixgbe_write_analog_reg8(hw, IXGBE_ATLAS_PDN_AN, analog_val);
916 	}
917 
918 	/* Reset PHY */
919 	ixgbe_reset_phy(hw);
920 
921 	/*
922 	 * Prevent the PCI-E bus from from hanging by disabling PCI-E master
923 	 * access and verify no pending requests before reset
924 	 */
925 	if (ixgbe_disable_pcie_master(hw) != IXGBE_SUCCESS) {
926 		status = IXGBE_ERR_MASTER_REQUESTS_PENDING;
927 		DEBUGOUT("PCI-E Master disable polling has failed.\n");
928 	}
929 
930 	/*
931 	 * Issue global reset to the MAC.  This needs to be a SW reset.
932 	 * If link reset is used, it might reset the MAC when mng is using it
933 	 */
934 	ctrl = IXGBE_READ_REG(hw, IXGBE_CTRL);
935 	IXGBE_WRITE_REG(hw, IXGBE_CTRL, (ctrl | IXGBE_CTRL_RST));
936 	IXGBE_WRITE_FLUSH(hw);
937 
938 	/* Poll for reset bit to self-clear indicating reset is complete */
939 	for (i = 0; i < 10; i++) {
940 		usec_delay(1);
941 		ctrl = IXGBE_READ_REG(hw, IXGBE_CTRL);
942 		if (!(ctrl & IXGBE_CTRL_RST))
943 			break;
944 	}
945 	if (ctrl & IXGBE_CTRL_RST) {
946 		status = IXGBE_ERR_RESET_FAILED;
947 		DEBUGOUT("Reset polling failed to complete.\n");
948 	}
949 
950 	msec_delay(50);
951 
952 	gheccr = IXGBE_READ_REG(hw, IXGBE_GHECCR);
953 	gheccr &= ~((1 << 21) | (1 << 18) | (1 << 9) | (1 << 6));
954 	IXGBE_WRITE_REG(hw, IXGBE_GHECCR, gheccr);
955 
956 	/*
957 	 * AUTOC register which stores link settings gets cleared
958 	 * and reloaded from EEPROM after reset. We need to restore
959 	 * our stored value from init in case SW changed the attach
960 	 * type or speed.  If this is the first time and link settings
961 	 * have not been stored, store default settings from AUTOC.
962 	 */
963 	autoc = IXGBE_READ_REG(hw, IXGBE_AUTOC);
964 	if (hw->mac.link_settings_loaded) {
965 		autoc &= ~(IXGBE_AUTOC_LMS_ATTACH_TYPE);
966 		autoc &= ~(IXGBE_AUTOC_LMS_MASK);
967 		autoc |= hw->mac.link_attach_type;
968 		autoc |= hw->mac.link_mode_select;
969 		IXGBE_WRITE_REG(hw, IXGBE_AUTOC, autoc);
970 	} else {
971 		hw->mac.link_attach_type =
972 					 (autoc & IXGBE_AUTOC_LMS_ATTACH_TYPE);
973 		hw->mac.link_mode_select = (autoc & IXGBE_AUTOC_LMS_MASK);
974 		hw->mac.link_settings_loaded = TRUE;
975 	}
976 
977 	/* Store the permanent mac address */
978 	ixgbe_get_mac_addr(hw, hw->mac.perm_addr);
979 
980 	return status;
981 }
982 
983 /**
984  *  ixgbe_read_analog_reg8_82598 - Reads 8 bit 82598 Atlas analog register
985  *  @hw: pointer to hardware structure
986  *  @reg: analog register to read
987  *  @val: read value
988  *
989  *  Performs write operation to analog register specified.
990  **/
991 s32 ixgbe_read_analog_reg8_82598(struct ixgbe_hw *hw, u32 reg, u8 *val)
992 {
993 	u32  atlas_ctl;
994 
995 	IXGBE_WRITE_REG(hw, IXGBE_ATLASCTL, IXGBE_ATLASCTL_WRITE_CMD | (reg << 8));
996 	IXGBE_WRITE_FLUSH(hw);
997 	usec_delay(10);
998 	atlas_ctl = IXGBE_READ_REG(hw, IXGBE_ATLASCTL);
999 	*val = (u8)atlas_ctl;
1000 
1001 	return IXGBE_SUCCESS;
1002 }
1003 
1004 /**
1005  *  ixgbe_write_analog_reg8_82598 - Writes 8 bit 82598 Atlas analog register
1006  *  @hw: pointer to hardware structure
1007  *  @reg: atlas register to write
1008  *  @val: value to write
1009  *
1010  *  Performs write operation to Atlas analog register specified.
1011  **/
1012 s32 ixgbe_write_analog_reg8_82598(struct ixgbe_hw *hw, u32 reg, u8 val)
1013 {
1014 	u32  atlas_ctl;
1015 
1016 	atlas_ctl = (reg << 8) | val;
1017 	IXGBE_WRITE_REG(hw, IXGBE_ATLASCTL, atlas_ctl);
1018 	IXGBE_WRITE_FLUSH(hw);
1019 	usec_delay(10);
1020 
1021 	return IXGBE_SUCCESS;
1022 }
1023 
1024 /**
1025  *  ixgbe_get_num_rx_addrs_82598 - Get RX address registers
1026  *  @hw: pointer to hardware structure
1027  *
1028  *  Returns the of RAR entries for the given adapter.
1029  **/
1030 u32 ixgbe_get_num_rx_addrs_82598(struct ixgbe_hw *hw)
1031 {
1032 	UNREFERENCED_PARAMETER(hw);
1033 
1034 	return IXGBE_82598_RAR_ENTRIES;
1035 }
1036 
1037