1 /****************************************************************************** 2 3 Copyright (c) 2001-2013, Intel Corporation 4 All rights reserved. 5 6 Redistribution and use in source and binary forms, with or without 7 modification, are permitted provided that the following conditions are met: 8 9 1. Redistributions of source code must retain the above copyright notice, 10 this list of conditions and the following disclaimer. 11 12 2. Redistributions in binary form must reproduce the above copyright 13 notice, this list of conditions and the following disclaimer in the 14 documentation and/or other materials provided with the distribution. 15 16 3. Neither the name of the Intel Corporation nor the names of its 17 contributors may be used to endorse or promote products derived from 18 this software without specific prior written permission. 19 20 THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 21 AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 22 IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 23 ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE 24 LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 25 CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 26 SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 27 INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 28 CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 29 ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 30 POSSIBILITY OF SUCH DAMAGE. 31 32 ******************************************************************************/ 33 /*$FreeBSD$*/ 34 35 36 #ifndef _IXGBE_H_ 37 #define _IXGBE_H_ 38 39 40 #include <sys/param.h> 41 #include <sys/systm.h> 42 #ifndef IXGBE_LEGACY_TX 43 #include <sys/buf_ring.h> 44 #endif 45 #include <sys/mbuf.h> 46 #include <sys/protosw.h> 47 #include <sys/socket.h> 48 #include <sys/malloc.h> 49 #include <sys/kernel.h> 50 #include <sys/module.h> 51 #include <sys/sockio.h> 52 #include <sys/eventhandler.h> 53 54 #include <net/if.h> 55 #include <net/if_var.h> 56 #include <net/if_arp.h> 57 #include <net/bpf.h> 58 #include <net/ethernet.h> 59 #include <net/if_dl.h> 60 #include <net/if_media.h> 61 62 #include <net/bpf.h> 63 #include <net/if_types.h> 64 #include <net/if_vlan_var.h> 65 66 #include <netinet/in_systm.h> 67 #include <netinet/in.h> 68 #include <netinet/if_ether.h> 69 #include <netinet/ip.h> 70 #include <netinet/ip6.h> 71 #include <netinet/tcp.h> 72 #include <netinet/tcp_lro.h> 73 #include <netinet/udp.h> 74 75 #include <machine/in_cksum.h> 76 77 #include <sys/bus.h> 78 #include <machine/bus.h> 79 #include <sys/rman.h> 80 #include <machine/resource.h> 81 #include <vm/vm.h> 82 #include <vm/pmap.h> 83 #include <machine/clock.h> 84 #include <dev/pci/pcivar.h> 85 #include <dev/pci/pcireg.h> 86 #include <sys/proc.h> 87 #include <sys/sysctl.h> 88 #include <sys/endian.h> 89 #include <sys/taskqueue.h> 90 #include <sys/pcpu.h> 91 #include <sys/smp.h> 92 #include <machine/smp.h> 93 94 #include "ixgbe_api.h" 95 96 /* Tunables */ 97 98 /* 99 * TxDescriptors Valid Range: 64-4096 Default Value: 256 This value is the 100 * number of transmit descriptors allocated by the driver. Increasing this 101 * value allows the driver to queue more transmits. Each descriptor is 16 102 * bytes. Performance tests have show the 2K value to be optimal for top 103 * performance. 104 */ 105 #define DEFAULT_TXD 1024 106 #define PERFORM_TXD 2048 107 #define MAX_TXD 4096 108 #define MIN_TXD 64 109 110 /* 111 * RxDescriptors Valid Range: 64-4096 Default Value: 256 This value is the 112 * number of receive descriptors allocated for each RX queue. Increasing this 113 * value allows the driver to buffer more incoming packets. Each descriptor 114 * is 16 bytes. A receive buffer is also allocated for each descriptor. 115 * 116 * Note: with 8 rings and a dual port card, it is possible to bump up 117 * against the system mbuf pool limit, you can tune nmbclusters 118 * to adjust for this. 119 */ 120 #define DEFAULT_RXD 1024 121 #define PERFORM_RXD 2048 122 #define MAX_RXD 4096 123 #define MIN_RXD 64 124 125 /* Alignment for rings */ 126 #define DBA_ALIGN 128 127 128 /* 129 * This parameter controls the maximum no of times the driver will loop in 130 * the isr. Minimum Value = 1 131 */ 132 #define MAX_LOOP 10 133 134 /* 135 * This is the max watchdog interval, ie. the time that can 136 * pass between any two TX clean operations, such only happening 137 * when the TX hardware is functioning. 138 */ 139 #define IXGBE_WATCHDOG (10 * hz) 140 141 /* 142 * This parameters control when the driver calls the routine to reclaim 143 * transmit descriptors. 144 */ 145 #define IXGBE_TX_CLEANUP_THRESHOLD (adapter->num_tx_desc / 8) 146 #define IXGBE_TX_OP_THRESHOLD (adapter->num_tx_desc / 32) 147 148 #define IXGBE_MAX_FRAME_SIZE 0x3F00 149 150 /* Flow control constants */ 151 #define IXGBE_FC_PAUSE 0xFFFF 152 #define IXGBE_FC_HI 0x20000 153 #define IXGBE_FC_LO 0x10000 154 155 /* 156 * Used for optimizing small rx mbufs. Effort is made to keep the copy 157 * small and aligned for the CPU L1 cache. 158 * 159 * MHLEN is typically 168 bytes, giving us 8-byte alignment. Getting 160 * 32 byte alignment needed for the fast bcopy results in 8 bytes being 161 * wasted. Getting 64 byte alignment, which _should_ be ideal for 162 * modern Intel CPUs, results in 40 bytes wasted and a significant drop 163 * in observed efficiency of the optimization, 97.9% -> 81.8%. 164 */ 165 #define IXGBE_RX_COPY_LEN 160 166 #define IXGBE_RX_COPY_ALIGN (MHLEN - IXGBE_RX_COPY_LEN) 167 168 /* Keep older OS drivers building... */ 169 #if !defined(SYSCTL_ADD_UQUAD) 170 #define SYSCTL_ADD_UQUAD SYSCTL_ADD_QUAD 171 #endif 172 173 /* Defines for printing debug information */ 174 #define DEBUG_INIT 0 175 #define DEBUG_IOCTL 0 176 #define DEBUG_HW 0 177 178 #define INIT_DEBUGOUT(S) if (DEBUG_INIT) printf(S "\n") 179 #define INIT_DEBUGOUT1(S, A) if (DEBUG_INIT) printf(S "\n", A) 180 #define INIT_DEBUGOUT2(S, A, B) if (DEBUG_INIT) printf(S "\n", A, B) 181 #define IOCTL_DEBUGOUT(S) if (DEBUG_IOCTL) printf(S "\n") 182 #define IOCTL_DEBUGOUT1(S, A) if (DEBUG_IOCTL) printf(S "\n", A) 183 #define IOCTL_DEBUGOUT2(S, A, B) if (DEBUG_IOCTL) printf(S "\n", A, B) 184 #define HW_DEBUGOUT(S) if (DEBUG_HW) printf(S "\n") 185 #define HW_DEBUGOUT1(S, A) if (DEBUG_HW) printf(S "\n", A) 186 #define HW_DEBUGOUT2(S, A, B) if (DEBUG_HW) printf(S "\n", A, B) 187 188 #define MAX_NUM_MULTICAST_ADDRESSES 128 189 #define IXGBE_82598_SCATTER 100 190 #define IXGBE_82599_SCATTER 32 191 #define MSIX_82598_BAR 3 192 #define MSIX_82599_BAR 4 193 #define IXGBE_TSO_SIZE 262140 194 #define IXGBE_TX_BUFFER_SIZE ((u32) 1514) 195 #define IXGBE_RX_HDR 128 196 #define IXGBE_VFTA_SIZE 128 197 #define IXGBE_BR_SIZE 4096 198 #define IXGBE_QUEUE_MIN_FREE 32 199 200 /* Offload bits in mbuf flag */ 201 #if __FreeBSD_version >= 800000 202 #define CSUM_OFFLOAD (CSUM_IP|CSUM_TCP|CSUM_UDP|CSUM_SCTP) 203 #else 204 #define CSUM_OFFLOAD (CSUM_IP|CSUM_TCP|CSUM_UDP) 205 #endif 206 207 /* 208 * Interrupt Moderation parameters 209 */ 210 #define IXGBE_LOW_LATENCY 128 211 #define IXGBE_AVE_LATENCY 400 212 #define IXGBE_BULK_LATENCY 1200 213 #define IXGBE_LINK_ITR 2000 214 215 216 /* 217 ***************************************************************************** 218 * vendor_info_array 219 * 220 * This array contains the list of Subvendor/Subdevice IDs on which the driver 221 * should load. 222 * 223 ***************************************************************************** 224 */ 225 typedef struct _ixgbe_vendor_info_t { 226 unsigned int vendor_id; 227 unsigned int device_id; 228 unsigned int subvendor_id; 229 unsigned int subdevice_id; 230 unsigned int index; 231 } ixgbe_vendor_info_t; 232 233 struct ixgbe_tx_buf { 234 union ixgbe_adv_tx_desc *eop; 235 struct mbuf *m_head; 236 bus_dmamap_t map; 237 }; 238 239 struct ixgbe_rx_buf { 240 struct mbuf *buf; 241 struct mbuf *fmp; 242 bus_dmamap_t pmap; 243 u_int flags; 244 #define IXGBE_RX_COPY 0x01 245 uint64_t addr; 246 }; 247 248 /* 249 * Bus dma allocation structure used by ixgbe_dma_malloc and ixgbe_dma_free. 250 */ 251 struct ixgbe_dma_alloc { 252 bus_addr_t dma_paddr; 253 caddr_t dma_vaddr; 254 bus_dma_tag_t dma_tag; 255 bus_dmamap_t dma_map; 256 bus_dma_segment_t dma_seg; 257 bus_size_t dma_size; 258 int dma_nseg; 259 }; 260 261 /* 262 ** Driver queue struct: this is the interrupt container 263 ** for the associated tx and rx ring. 264 */ 265 struct ix_queue { 266 struct adapter *adapter; 267 u32 msix; /* This queue's MSIX vector */ 268 u32 eims; /* This queue's EIMS bit */ 269 u32 eitr_setting; 270 struct resource *res; 271 void *tag; 272 struct tx_ring *txr; 273 struct rx_ring *rxr; 274 struct task que_task; 275 struct taskqueue *tq; 276 u64 irqs; 277 }; 278 279 /* 280 * The transmit ring, one per queue 281 */ 282 struct tx_ring { 283 struct adapter *adapter; 284 struct mtx tx_mtx; 285 u32 me; 286 int watchdog_time; 287 union ixgbe_adv_tx_desc *tx_base; 288 struct ixgbe_tx_buf *tx_buffers; 289 struct ixgbe_dma_alloc txdma; 290 volatile u16 tx_avail; 291 u16 next_avail_desc; 292 u16 next_to_clean; 293 u16 process_limit; 294 u16 num_desc; 295 enum { 296 IXGBE_QUEUE_IDLE, 297 IXGBE_QUEUE_WORKING, 298 IXGBE_QUEUE_HUNG, 299 } queue_status; 300 u32 txd_cmd; 301 bus_dma_tag_t txtag; 302 char mtx_name[16]; 303 #ifndef IXGBE_LEGACY_TX 304 struct buf_ring *br; 305 struct task txq_task; 306 #endif 307 #ifdef IXGBE_FDIR 308 u16 atr_sample; 309 u16 atr_count; 310 #endif 311 u32 bytes; /* used for AIM */ 312 u32 packets; 313 /* Soft Stats */ 314 unsigned long tso_tx; 315 unsigned long no_tx_map_avail; 316 unsigned long no_tx_dma_setup; 317 u64 no_desc_avail; 318 u64 total_packets; 319 }; 320 321 322 /* 323 * The Receive ring, one per rx queue 324 */ 325 struct rx_ring { 326 struct adapter *adapter; 327 struct mtx rx_mtx; 328 u32 me; 329 union ixgbe_adv_rx_desc *rx_base; 330 struct ixgbe_dma_alloc rxdma; 331 struct lro_ctrl lro; 332 bool lro_enabled; 333 bool hw_rsc; 334 bool vtag_strip; 335 u16 next_to_refresh; 336 u16 next_to_check; 337 u16 num_desc; 338 u16 mbuf_sz; 339 u16 process_limit; 340 char mtx_name[16]; 341 struct ixgbe_rx_buf *rx_buffers; 342 bus_dma_tag_t ptag; 343 344 u32 bytes; /* Used for AIM calc */ 345 u32 packets; 346 347 /* Soft stats */ 348 u64 rx_irq; 349 u64 rx_copies; 350 u64 rx_packets; 351 u64 rx_bytes; 352 u64 rx_discarded; 353 u64 rsc_num; 354 #ifdef IXGBE_FDIR 355 u64 flm; 356 #endif 357 }; 358 359 /* Our adapter structure */ 360 struct adapter { 361 struct ifnet *ifp; 362 struct ixgbe_hw hw; 363 364 struct ixgbe_osdep osdep; 365 struct device *dev; 366 367 struct resource *pci_mem; 368 struct resource *msix_mem; 369 370 /* 371 * Interrupt resources: this set is 372 * either used for legacy, or for Link 373 * when doing MSIX 374 */ 375 void *tag; 376 struct resource *res; 377 378 struct ifmedia media; 379 struct callout timer; 380 int msix; 381 int if_flags; 382 383 struct mtx core_mtx; 384 385 eventhandler_tag vlan_attach; 386 eventhandler_tag vlan_detach; 387 388 u16 num_vlans; 389 u16 num_queues; 390 391 /* 392 ** Shadow VFTA table, this is needed because 393 ** the real vlan filter table gets cleared during 394 ** a soft reset and the driver needs to be able 395 ** to repopulate it. 396 */ 397 u32 shadow_vfta[IXGBE_VFTA_SIZE]; 398 399 /* Info about the interface */ 400 u32 optics; 401 u32 fc; /* local flow ctrl setting */ 402 int advertise; /* link speeds */ 403 bool link_active; 404 u16 max_frame_size; 405 u16 num_segs; 406 u32 link_speed; 407 bool link_up; 408 u32 linkvec; 409 410 /* Mbuf cluster size */ 411 u32 rx_mbuf_sz; 412 413 /* Support for pluggable optics */ 414 bool sfp_probe; 415 struct task link_task; /* Link tasklet */ 416 struct task mod_task; /* SFP tasklet */ 417 struct task msf_task; /* Multispeed Fiber */ 418 #ifdef IXGBE_FDIR 419 int fdir_reinit; 420 struct task fdir_task; 421 #endif 422 struct taskqueue *tq; 423 424 /* 425 ** Queues: 426 ** This is the irq holder, it has 427 ** and RX/TX pair or rings associated 428 ** with it. 429 */ 430 struct ix_queue *queues; 431 432 /* 433 * Transmit rings: 434 * Allocated at run time, an array of rings. 435 */ 436 struct tx_ring *tx_rings; 437 u32 num_tx_desc; 438 439 /* 440 * Receive rings: 441 * Allocated at run time, an array of rings. 442 */ 443 struct rx_ring *rx_rings; 444 u64 que_mask; 445 u32 num_rx_desc; 446 447 /* Multicast array memory */ 448 u8 *mta; 449 450 451 /* Misc stats maintained by the driver */ 452 unsigned long dropped_pkts; 453 unsigned long mbuf_defrag_failed; 454 unsigned long mbuf_header_failed; 455 unsigned long mbuf_packet_failed; 456 unsigned long watchdog_events; 457 unsigned long link_irq; 458 459 struct ixgbe_hw_stats stats; 460 }; 461 462 463 /* Precision Time Sync (IEEE 1588) defines */ 464 #define ETHERTYPE_IEEE1588 0x88F7 465 #define PICOSECS_PER_TICK 20833 466 #define TSYNC_UDP_PORT 319 /* UDP port for the protocol */ 467 #define IXGBE_ADVTXD_TSTAMP 0x00080000 468 469 470 #define IXGBE_CORE_LOCK_INIT(_sc, _name) \ 471 mtx_init(&(_sc)->core_mtx, _name, "IXGBE Core Lock", MTX_DEF) 472 #define IXGBE_CORE_LOCK_DESTROY(_sc) mtx_destroy(&(_sc)->core_mtx) 473 #define IXGBE_TX_LOCK_DESTROY(_sc) mtx_destroy(&(_sc)->tx_mtx) 474 #define IXGBE_RX_LOCK_DESTROY(_sc) mtx_destroy(&(_sc)->rx_mtx) 475 #define IXGBE_CORE_LOCK(_sc) mtx_lock(&(_sc)->core_mtx) 476 #define IXGBE_TX_LOCK(_sc) mtx_lock(&(_sc)->tx_mtx) 477 #define IXGBE_TX_TRYLOCK(_sc) mtx_trylock(&(_sc)->tx_mtx) 478 #define IXGBE_RX_LOCK(_sc) mtx_lock(&(_sc)->rx_mtx) 479 #define IXGBE_CORE_UNLOCK(_sc) mtx_unlock(&(_sc)->core_mtx) 480 #define IXGBE_TX_UNLOCK(_sc) mtx_unlock(&(_sc)->tx_mtx) 481 #define IXGBE_RX_UNLOCK(_sc) mtx_unlock(&(_sc)->rx_mtx) 482 #define IXGBE_CORE_LOCK_ASSERT(_sc) mtx_assert(&(_sc)->core_mtx, MA_OWNED) 483 #define IXGBE_TX_LOCK_ASSERT(_sc) mtx_assert(&(_sc)->tx_mtx, MA_OWNED) 484 485 /* For backward compatibility */ 486 #if !defined(PCIER_LINK_STA) 487 #define PCIER_LINK_STA PCIR_EXPRESS_LINK_STA 488 #endif 489 490 static inline bool 491 ixgbe_is_sfp(struct ixgbe_hw *hw) 492 { 493 switch (hw->phy.type) { 494 case ixgbe_phy_sfp_avago: 495 case ixgbe_phy_sfp_ftl: 496 case ixgbe_phy_sfp_intel: 497 case ixgbe_phy_sfp_unknown: 498 case ixgbe_phy_sfp_passive_tyco: 499 case ixgbe_phy_sfp_passive_unknown: 500 return TRUE; 501 default: 502 return FALSE; 503 } 504 } 505 506 /* Workaround to make 8.0 buildable */ 507 #if __FreeBSD_version >= 800000 && __FreeBSD_version < 800504 508 static __inline int 509 drbr_needs_enqueue(struct ifnet *ifp, struct buf_ring *br) 510 { 511 #ifdef ALTQ 512 if (ALTQ_IS_ENABLED(&ifp->if_snd)) 513 return (1); 514 #endif 515 return (!buf_ring_empty(br)); 516 } 517 #endif 518 519 /* 520 ** Find the number of unrefreshed RX descriptors 521 */ 522 static inline u16 523 ixgbe_rx_unrefreshed(struct rx_ring *rxr) 524 { 525 if (rxr->next_to_check > rxr->next_to_refresh) 526 return (rxr->next_to_check - rxr->next_to_refresh - 1); 527 else 528 return ((rxr->num_desc + rxr->next_to_check) - 529 rxr->next_to_refresh - 1); 530 } 531 532 #endif /* _IXGBE_H_ */ 533