xref: /freebsd/sys/dev/ixgbe/ixgbe.h (revision 718519f4efc71096422fc71dab90b2a3369871ff)
1 /*****************************************************************************
2   SPDX-License-Identifier: BSD-3-Clause
3 
4   Copyright (c) 2001-2017, Intel Corporation
5   All rights reserved.
6 
7   Redistribution and use in source and binary forms, with or without
8   modification, are permitted provided that the following conditions are met:
9 
10    1. Redistributions of source code must retain the above copyright notice,
11       this list of conditions and the following disclaimer.
12 
13    2. Redistributions in binary form must reproduce the above copyright
14       notice, this list of conditions and the following disclaimer in the
15       documentation and/or other materials provided with the distribution.
16 
17    3. Neither the name of the Intel Corporation nor the names of its
18       contributors may be used to endorse or promote products derived from
19       this software without specific prior written permission.
20 
21   THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
22   AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
23   IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
24   ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
25   LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
26   CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
27   SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
28   INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
29   CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
30   ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
31   POSSIBILITY OF SUCH DAMAGE.
32 
33 *****************************************************************************/
34 
35 #ifndef _IXGBE_H_
36 #define _IXGBE_H_
37 
38 #include <sys/param.h>
39 #include <sys/systm.h>
40 #include <sys/buf_ring.h>
41 #include <sys/mbuf.h>
42 #include <sys/protosw.h>
43 #include <sys/socket.h>
44 #include <sys/malloc.h>
45 #include <sys/kernel.h>
46 #include <sys/module.h>
47 #include <sys/sockio.h>
48 #include <sys/eventhandler.h>
49 
50 #include <net/if.h>
51 #include <net/if_var.h>
52 #include <net/if_arp.h>
53 #include <net/bpf.h>
54 #include <net/ethernet.h>
55 #include <net/if_dl.h>
56 #include <net/if_media.h>
57 
58 #include <net/if_types.h>
59 #include <net/if_vlan_var.h>
60 #include <net/iflib.h>
61 
62 #include <netinet/in_systm.h>
63 #include <netinet/in.h>
64 #include <netinet/if_ether.h>
65 
66 #include <sys/bus.h>
67 #include <machine/bus.h>
68 #include <sys/rman.h>
69 #include <machine/resource.h>
70 #include <vm/vm.h>
71 #include <vm/pmap.h>
72 #include <machine/clock.h>
73 #include <dev/pci/pcivar.h>
74 #include <dev/pci/pcireg.h>
75 #include <sys/proc.h>
76 #include <sys/sysctl.h>
77 #include <sys/endian.h>
78 #include <sys/gtaskqueue.h>
79 #include <sys/pcpu.h>
80 #include <sys/smp.h>
81 #include <machine/smp.h>
82 #include <sys/sbuf.h>
83 
84 #include "ixgbe_api.h"
85 #include "ixgbe_common.h"
86 #include "ixgbe_phy.h"
87 #include "ixgbe_vf.h"
88 #include "ixgbe_features.h"
89 
90 /* Tunables */
91 
92 /*
93  * TxDescriptors Valid Range: 64-4096 Default Value: 256 This value is the
94  * number of transmit descriptors allocated by the driver. Increasing this
95  * value allows the driver to queue more transmits. Each descriptor is 16
96  * bytes. Performance tests have show the 2K value to be optimal for top
97  * performance.
98  */
99 #define DEFAULT_TXD		2048
100 #define PERFORM_TXD		2048
101 #define MAX_TXD			4096
102 #define MIN_TXD			64
103 
104 /*
105  * RxDescriptors Valid Range: 64-4096 Default Value: 256 This value is the
106  * number of receive descriptors allocated for each RX queue. Increasing this
107  * value allows the driver to buffer more incoming packets. Each descriptor
108  * is 16 bytes.  A receive buffer is also allocated for each descriptor.
109  *
110  * Note: with 8 rings and a dual port card, it is possible to bump up
111  *       against the system mbuf pool limit, you can tune nmbclusters
112  *       to adjust for this.
113  */
114 #define DEFAULT_RXD		2048
115 #define PERFORM_RXD		2048
116 #define MAX_RXD			4096
117 #define MIN_RXD			64
118 
119 /* Alignment for rings */
120 #define DBA_ALIGN		128
121 
122 /*
123  * This is the max watchdog interval, ie. the time that can
124  * pass between any two TX clean operations, such only happening
125  * when the TX hardware is functioning.
126  */
127 #define IXGBE_WATCHDOG	(10 * hz)
128 
129 /*
130  * This parameters control when the driver calls the routine to reclaim
131  * transmit descriptors.
132  */
133 #define IXGBE_TX_CLEANUP_THRESHOLD(_a)	((_a)->num_tx_desc / 8)
134 #define IXGBE_TX_OP_THRESHOLD(_a)	((_a)->num_tx_desc / 32)
135 
136 /* These defines are used in MTU calculations */
137 #define IXGBE_MAX_FRAME_SIZE	9728
138 #define IXGBE_MTU_HDR		(ETHER_HDR_LEN + ETHER_CRC_LEN)
139 #define IXGBE_MTU_HDR_VLAN	(ETHER_HDR_LEN + ETHER_CRC_LEN + \
140 							    ETHER_VLAN_ENCAP_LEN)
141 #define IXGBE_MAX_MTU		(IXGBE_MAX_FRAME_SIZE - IXGBE_MTU_HDR)
142 #define IXGBE_MAX_MTU_VLAN	(IXGBE_MAX_FRAME_SIZE - IXGBE_MTU_HDR_VLAN)
143 
144 /* Flow control constants */
145 #define IXGBE_FC_PAUSE		0xFFFF
146 #define IXGBE_FC_HI		0x20000
147 #define IXGBE_FC_LO		0x10000
148 
149 /*
150  * Used for optimizing small rx mbufs.  Effort is made to keep the copy
151  * small and aligned for the CPU L1 cache.
152  *
153  * MHLEN is typically 168 bytes, giving us 8-byte alignment.  Getting
154  * 32 byte alignment needed for the fast bcopy results in 8 bytes being
155  * wasted.  Getting 64 byte alignment, which _should_ be ideal for
156  * modern Intel CPUs, results in 40 bytes wasted and a significant drop
157  * in observed efficiency of the optimization, 97.9% -> 81.8%.
158  */
159 #define IXGBE_MPKTHSIZE		(sizeof(struct m_hdr) + sizeof(struct pkthdr))
160 
161 #define IXGBE_RX_COPY_HDR_PADDED	((((IXGBE_MPKTHSIZE - 1) / 32) + 1) * 32)
162 #define IXGBE_RX_COPY_LEN		(MSIZE - IXGBE_RX_COPY_HDR_PADDED)
163 #define IXGBE_RX_COPY_ALIGN		(IXGBE_RX_COPY_HDR_PADDED - IXGBE_MPKTHSIZE)
164 
165 /* Defines for printing debug information */
166 #define DEBUG_INIT		0
167 #define DEBUG_IOCTL		0
168 #define DEBUG_HW		0
169 
170 #define INIT_DEBUGOUT(S)		if (DEBUG_INIT)  printf(S "\n")
171 #define INIT_DEBUGOUT1(S, A)		if (DEBUG_INIT)  printf(S "\n", A)
172 #define INIT_DEBUGOUT2(S, A, B)		if (DEBUG_INIT)  printf(S "\n", A, B)
173 #define IOCTL_DEBUGOUT(S)		if (DEBUG_IOCTL) printf(S "\n")
174 #define IOCTL_DEBUGOUT1(S, A)		if (DEBUG_IOCTL) printf(S "\n", A)
175 #define IOCTL_DEBUGOUT2(S, A, B)	if (DEBUG_IOCTL) printf(S "\n", A, B)
176 #define HW_DEBUGOUT(S)			if (DEBUG_HW) printf(S "\n")
177 #define HW_DEBUGOUT1(S, A)		if (DEBUG_HW) printf(S "\n", A)
178 #define HW_DEBUGOUT2(S, A, B)		if (DEBUG_HW) printf(S "\n", A, B)
179 
180 #define MAX_NUM_MULTICAST_ADDRESSES	128
181 #define IXGBE_82598_SCATTER		100
182 #define IXGBE_82599_SCATTER		32
183 #define IXGBE_TSO_SIZE			262140
184 #define IXGBE_RX_HDR			128
185 #define IXGBE_VFTA_SIZE			128
186 #define IXGBE_BR_SIZE			4096
187 #define IXGBE_QUEUE_MIN_FREE		32
188 #define IXGBE_MAX_TX_BUSY		10
189 #define IXGBE_QUEUE_HUNG		0x80000000
190 
191 #define IXGBE_EITR_DEFAULT		128
192 
193 /* Supported offload bits in mbuf flag */
194 #define CSUM_OFFLOAD	(CSUM_IP_TSO|CSUM_IP6_TSO|CSUM_IP| \
195 			    CSUM_IP_UDP|CSUM_IP_TCP|CSUM_IP_SCTP| \
196 			    CSUM_IP6_UDP|CSUM_IP6_TCP|CSUM_IP6_SCTP)
197 
198 #define IXGBE_CAPS (IFCAP_HWCSUM | IFCAP_HWCSUM_IPV6 | IFCAP_TSO | \
199 		    IFCAP_LRO | IFCAP_VLAN_HWTAGGING | IFCAP_VLAN_HWTSO | \
200 		    IFCAP_VLAN_HWCSUM | IFCAP_JUMBO_MTU | IFCAP_VLAN_MTU | \
201 		    IFCAP_VLAN_HWFILTER | IFCAP_WOL)
202 
203 #ifndef DEVMETHOD_END
204 #define DEVMETHOD_END	{ NULL, NULL }
205 #endif
206 
207 /*
208  * Interrupt Moderation parameters
209  */
210 #define IXGBE_LOW_LATENCY		128
211 #define IXGBE_AVE_LATENCY		400
212 #define IXGBE_BULK_LATENCY		1200
213 
214 /* Using 1FF (the max value), the interval is ~1.05ms */
215 #define IXGBE_LINK_ITR_QUANTA	0x1FF
216 #define IXGBE_LINK_ITR		((IXGBE_LINK_ITR_QUANTA << 3) & \
217 				    IXGBE_EITR_ITR_INT_MASK)
218 
219 
220 /************************************************************************
221  * vendor_info_array
222  *
223  *   Contains the list of Subvendor/Subdevice IDs on
224  *   which the driver should load.
225  ************************************************************************/
226 typedef struct _ixgbe_vendor_info_t {
227 	unsigned int		vendor_id;
228 	unsigned int		device_id;
229 	unsigned int		subvendor_id;
230 	unsigned int		subdevice_id;
231 	unsigned int		index;
232 } ixgbe_vendor_info_t;
233 
234 struct ixgbe_bp_data {
235 	u32		low;
236 	u32		high;
237 	u32		log;
238 };
239 
240 
241 /*
242  */
243 struct ixgbe_dma_alloc {
244 	bus_addr_t		dma_paddr;
245 	caddr_t			dma_vaddr;
246 	bus_dma_tag_t		dma_tag;
247 	bus_dmamap_t		dma_map;
248 	bus_dma_segment_t 	dma_seg;
249 	bus_size_t		dma_size;
250 	int			dma_nseg;
251 };
252 
253 struct ixgbe_mc_addr {
254 	u8		addr[IXGBE_ETH_LENGTH_OF_ADDRESS];
255 	u32		vmdq;
256 };
257 
258 /*
259  * The transmit ring, one per queue
260  */
261 struct tx_ring {
262 	struct ixgbe_softc	*sc;
263 	union ixgbe_adv_tx_desc *tx_base;
264 	uint64_t		tx_paddr;
265 	u32			tail;
266 	qidx_t			*tx_rsq;
267 	qidx_t			tx_rs_cidx;
268 	qidx_t			tx_rs_pidx;
269 	qidx_t			tx_cidx_processed;
270 	uint8_t			me;
271 
272 	/* Flow Director */
273 	u16			atr_sample;
274 	u16			atr_count;
275 
276 	u32			bytes;	/* used for AIM */
277 	u32			packets;
278 	/* Soft Stats */
279 	u64			tso_tx;
280 	u64			total_packets;
281 };
282 
283 
284 /*
285  * The Receive ring, one per rx queue
286  */
287 struct rx_ring {
288 	struct ix_rx_queue	*que;
289 	struct ixgbe_softc	*sc;
290 	u32			me;
291 	u32			tail;
292 	union ixgbe_adv_rx_desc *rx_base;
293 	bool			hw_rsc;
294 	bool			vtag_strip;
295 	uint64_t		rx_paddr;
296 	bus_dma_tag_t		ptag;
297 
298 	u32			bytes;	/* Used for AIM calc */
299 	u32			packets;
300 
301 	/* Soft stats */
302 	u64			rx_irq;
303 	u64			rx_copies;
304 	u64			rx_packets;
305 	u64			rx_bytes;
306 	u64			rx_discarded;
307 	u64			rsc_num;
308 
309 	/* Flow Director */
310 	u64			flm;
311 };
312 
313 /*
314  * Driver queue struct: this is the interrupt container
315  *  for the associated tx and rx ring.
316  */
317 struct ix_rx_queue {
318 	struct ixgbe_softc	*sc;
319 	u32			msix;	/* This queue's MSIX vector */
320 	u32			eitr_setting;
321 	struct resource		*res;
322 	void			*tag;
323 	int			busy;
324 	struct rx_ring		rxr;
325 	struct if_irq		que_irq;
326 	u64			irqs;
327 };
328 
329 struct ix_tx_queue {
330 	struct ixgbe_softc	*sc;
331 	u32			msix;	/* This queue's MSIX vector */
332 	struct tx_ring		txr;
333 };
334 
335 #define IXGBE_MAX_VF_MC	30	/* Max number of multicast entries */
336 
337 struct ixgbe_vf {
338 	u_int		pool;
339 	u_int		rar_index;
340 	u_int		maximum_frame_size;
341 	uint32_t	flags;
342 	uint8_t		ether_addr[ETHER_ADDR_LEN];
343 	uint16_t	mc_hash[IXGBE_MAX_VF_MC];
344 	uint16_t	num_mc_hashes;
345 	uint16_t	default_vlan;
346 	uint16_t	vlan_tag;
347 	uint16_t	api_ver;
348 };
349 
350 /* Our softc structure */
351 struct ixgbe_softc {
352 	struct ixgbe_hw		hw;
353 	struct ixgbe_osdep	osdep;
354 	if_ctx_t		ctx;
355 	if_softc_ctx_t		shared;
356 #define num_tx_queues		shared->isc_ntxqsets
357 #define num_rx_queues		shared->isc_nrxqsets
358 #define max_frame_size		shared->isc_max_frame_size
359 #define intr_type		shared->isc_intr
360 
361 	device_t		dev;
362 	struct ifnet		*ifp;
363 
364 	struct resource		*pci_mem;
365 
366 	/*
367 	 * Interrupt resources: this set is
368 	 * either used for legacy, or for Link
369 	 * when doing MSI-X
370 	 */
371 	struct if_irq		irq;
372 	void			*tag;
373 	struct resource		*res;
374 
375 	struct ifmedia		*media;
376 	int			if_flags;
377 	int			msix;
378 
379 	u16			num_vlans;
380 
381 	/*
382 	 * Shadow VFTA table, this is needed because
383 	 * the real vlan filter table gets cleared during
384 	 * a soft reset and the driver needs to be able
385 	 * to repopulate it.
386 	 */
387 	u32			shadow_vfta[IXGBE_VFTA_SIZE];
388 
389 	/* Info about the interface */
390 	int			advertise;	/* link speeds */
391 	int			enable_aim;	/* adaptive interrupt moderation */
392 	bool			link_active;
393 	u16			num_segs;
394 	u32			link_speed;
395 	bool			link_up;
396 	bool			link_enabled;
397 	u32			vector;
398 	u16			dmac;
399 	u32			phy_layer;
400 
401 	/* Power management-related */
402 	bool			wol_support;
403 	u32			wufc;
404 
405 	/* Mbuf cluster size */
406 	u32			rx_mbuf_sz;
407 
408 	/* Support for pluggable optics */
409 	bool			sfp_probe;
410 
411 	/* Flow Director */
412 	int			fdir_reinit;
413 
414 	u32			task_requests;
415 
416 	/*
417 	 * Queues:
418 	 *   This is the irq holder, it has
419 	 *   and RX/TX pair or rings associated
420 	 *   with it.
421 	 */
422 	struct ix_tx_queue	*tx_queues;
423 	struct ix_rx_queue	*rx_queues;
424 
425 	/* Multicast array memory */
426 	struct ixgbe_mc_addr	*mta;
427 
428 	/* SR-IOV */
429 	int			iov_mode;
430 	int			num_vfs;
431 	int			pool;
432 	struct ixgbe_vf		*vfs;
433 
434 	/* Bypass */
435 	struct ixgbe_bp_data	bypass;
436 
437 	/* Firmware error check */
438 	int			recovery_mode;
439 	struct callout		fw_mode_timer;
440 
441 	/* Misc stats maintained by the driver */
442 	unsigned long		dropped_pkts;
443 	unsigned long		mbuf_header_failed;
444 	unsigned long		mbuf_packet_failed;
445 	unsigned long		watchdog_events;
446 	unsigned long		link_irq;
447 	union {
448 		struct ixgbe_hw_stats pf;
449 		struct ixgbevf_hw_stats vf;
450 	} stats;
451 
452 	/* counter(9) stats */
453 	u64			ipackets;
454 	u64			ierrors;
455 	u64			opackets;
456 	u64			oerrors;
457 	u64			ibytes;
458 	u64			obytes;
459 	u64			imcasts;
460 	u64			omcasts;
461 	u64			iqdrops;
462 	u64			noproto;
463 
464 	/* Feature capable/enabled flags.  See ixgbe_features.h */
465 	u32			feat_cap;
466 	u32			feat_en;
467 };
468 
469 /* Precision Time Sync (IEEE 1588) defines */
470 #define ETHERTYPE_IEEE1588		0x88F7
471 #define PICOSECS_PER_TICK		20833
472 #define TSYNC_UDP_PORT			319 /* UDP port for the protocol */
473 #define IXGBE_ADVTXD_TSTAMP		0x00080000
474 
475 /* Stats macros */
476 #define IXGBE_SET_IPACKETS(sc, count)	(sc)->ipackets = (count)
477 #define IXGBE_SET_IERRORS(sc, count)	(sc)->ierrors = (count)
478 #define IXGBE_SET_OPACKETS(sc, count)	(sc)->opackets = (count)
479 #define IXGBE_SET_OERRORS(sc, count)	(sc)->oerrors = (count)
480 #define IXGBE_SET_COLLISIONS(sc, count)
481 #define IXGBE_SET_IBYTES(sc, count)	(sc)->ibytes = (count)
482 #define IXGBE_SET_OBYTES(sc, count)	(sc)->obytes = (count)
483 #define IXGBE_SET_IMCASTS(sc, count)	(sc)->imcasts = (count)
484 #define IXGBE_SET_OMCASTS(sc, count)	(sc)->omcasts = (count)
485 #define IXGBE_SET_IQDROPS(sc, count)	(sc)->iqdrops = (count)
486 
487 /* External PHY register addresses */
488 #define IXGBE_PHY_CURRENT_TEMP		0xC820
489 #define IXGBE_PHY_OVERTEMP_STATUS	0xC830
490 
491 /* Sysctl help messages; displayed with sysctl -d */
492 #define IXGBE_SYSCTL_DESC_ADV_SPEED	\
493     "\nControl advertised link speed using these flags:\n" \
494     "\t0x1 - advertise 100M\n" \
495     "\t0x2 - advertise 1G\n" \
496     "\t0x4 - advertise 10G\n" \
497     "\t0x8 - advertise 10M\n\n" \
498     "\t0x10  - advertise 2.5G\n" \
499     "\t0x20  - advertise 5G\n\n" \
500     "\t100M and 10M are only supported on certain adapters.\n"
501 
502 #define IXGBE_SYSCTL_DESC_SET_FC	\
503     "\nSet flow control mode using these values:\n" \
504     "\t0 - off\n" \
505     "\t1 - rx pause\n" \
506     "\t2 - tx pause\n" \
507     "\t3 - tx and rx pause"
508 
509 #define IXGBE_SYSCTL_DESC_RX_ERRS	\
510     "\nSum of the following RX errors counters:\n" \
511     " * CRC errors,\n" \
512     " * illegal byte error count,\n" \
513     " * missed packet count,\n" \
514     " * length error count,\n" \
515     " * undersized packets count,\n" \
516     " * fragmented packets count,\n" \
517     " * oversized packets count,\n" \
518     " * jabber count."
519 
520 /*
521  * This checks for a zero mac addr, something that will be likely
522  * unless the Admin on the Host has created one.
523  */
524 static inline bool
525 ixv_check_ether_addr(u8 *addr)
526 {
527 	bool status = true;
528 
529 	if ((addr[0] == 0 && addr[1]== 0 && addr[2] == 0 &&
530 	    addr[3] == 0 && addr[4]== 0 && addr[5] == 0))
531 		status = false;
532 
533 	return (status);
534 }
535 
536 uint64_t ixgbe_link_speed_to_baudrate(ixgbe_link_speed speed);
537 
538 /* Shared Prototypes */
539 
540 int  ixgbe_allocate_queues(struct ixgbe_softc *);
541 int  ixgbe_setup_transmit_structures(struct ixgbe_softc *);
542 void ixgbe_free_transmit_structures(struct ixgbe_softc *);
543 int  ixgbe_setup_receive_structures(struct ixgbe_softc *);
544 void ixgbe_free_receive_structures(struct ixgbe_softc *);
545 int  ixgbe_get_regs(SYSCTL_HANDLER_ARGS);
546 
547 #include "ixgbe_bypass.h"
548 #include "ixgbe_fdir.h"
549 #include "ixgbe_rss.h"
550 
551 #endif /* _IXGBE_H_ */
552