1 /****************************************************************************** 2 3 Copyright (c) 2001-2010, Intel Corporation 4 All rights reserved. 5 6 Redistribution and use in source and binary forms, with or without 7 modification, are permitted provided that the following conditions are met: 8 9 1. Redistributions of source code must retain the above copyright notice, 10 this list of conditions and the following disclaimer. 11 12 2. Redistributions in binary form must reproduce the above copyright 13 notice, this list of conditions and the following disclaimer in the 14 documentation and/or other materials provided with the distribution. 15 16 3. Neither the name of the Intel Corporation nor the names of its 17 contributors may be used to endorse or promote products derived from 18 this software without specific prior written permission. 19 20 THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 21 AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 22 IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 23 ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE 24 LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 25 CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 26 SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 27 INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 28 CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 29 ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 30 POSSIBILITY OF SUCH DAMAGE. 31 32 ******************************************************************************/ 33 /*$FreeBSD$*/ 34 35 36 #ifndef _IXGBE_H_ 37 #define _IXGBE_H_ 38 39 40 #include <sys/param.h> 41 #include <sys/systm.h> 42 #if __FreeBSD_version >= 800000 43 #include <sys/buf_ring.h> 44 #endif 45 #include <sys/mbuf.h> 46 #include <sys/protosw.h> 47 #include <sys/socket.h> 48 #include <sys/malloc.h> 49 #include <sys/kernel.h> 50 #include <sys/module.h> 51 #include <sys/sockio.h> 52 53 #include <net/if.h> 54 #include <net/if_arp.h> 55 #include <net/bpf.h> 56 #include <net/ethernet.h> 57 #include <net/if_dl.h> 58 #include <net/if_media.h> 59 60 #include <net/bpf.h> 61 #include <net/if_types.h> 62 #include <net/if_vlan_var.h> 63 64 #include <netinet/in_systm.h> 65 #include <netinet/in.h> 66 #include <netinet/if_ether.h> 67 #include <netinet/ip.h> 68 #include <netinet/ip6.h> 69 #include <netinet/tcp.h> 70 #include <netinet/tcp_lro.h> 71 #include <netinet/udp.h> 72 73 #include <machine/in_cksum.h> 74 75 #include <sys/bus.h> 76 #include <machine/bus.h> 77 #include <sys/rman.h> 78 #include <machine/resource.h> 79 #include <vm/vm.h> 80 #include <vm/pmap.h> 81 #include <machine/clock.h> 82 #include <dev/pci/pcivar.h> 83 #include <dev/pci/pcireg.h> 84 #include <sys/proc.h> 85 #include <sys/sysctl.h> 86 #include <sys/endian.h> 87 #include <sys/taskqueue.h> 88 #include <sys/pcpu.h> 89 #include <sys/smp.h> 90 #include <machine/smp.h> 91 92 #ifdef IXGBE_IEEE1588 93 #include <sys/ieee1588.h> 94 #endif 95 96 #include "ixgbe_api.h" 97 98 /* Tunables */ 99 100 /* 101 * TxDescriptors Valid Range: 64-4096 Default Value: 256 This value is the 102 * number of transmit descriptors allocated by the driver. Increasing this 103 * value allows the driver to queue more transmits. Each descriptor is 16 104 * bytes. Performance tests have show the 2K value to be optimal for top 105 * performance. 106 */ 107 #define DEFAULT_TXD 1024 108 #define PERFORM_TXD 2048 109 #define MAX_TXD 4096 110 #define MIN_TXD 64 111 112 /* 113 * RxDescriptors Valid Range: 64-4096 Default Value: 256 This value is the 114 * number of receive descriptors allocated for each RX queue. Increasing this 115 * value allows the driver to buffer more incoming packets. Each descriptor 116 * is 16 bytes. A receive buffer is also allocated for each descriptor. 117 * 118 * Note: with 8 rings and a dual port card, it is possible to bump up 119 * against the system mbuf pool limit, you can tune nmbclusters 120 * to adjust for this. 121 */ 122 #define DEFAULT_RXD 1024 123 #define PERFORM_RXD 2048 124 #define MAX_RXD 4096 125 #define MIN_RXD 64 126 127 /* Alignment for rings */ 128 #define DBA_ALIGN 128 129 130 /* 131 * This parameter controls the maximum no of times the driver will loop in 132 * the isr. Minimum Value = 1 133 */ 134 #define MAX_LOOP 10 135 136 /* 137 * This is the max watchdog interval, ie. the time that can 138 * pass between any two TX clean operations, such only happening 139 * when the TX hardware is functioning. 140 */ 141 #define IXGBE_WATCHDOG (10 * hz) 142 143 /* 144 * This parameters control when the driver calls the routine to reclaim 145 * transmit descriptors. 146 */ 147 #define IXGBE_TX_CLEANUP_THRESHOLD (adapter->num_tx_desc / 8) 148 #define IXGBE_TX_OP_THRESHOLD (adapter->num_tx_desc / 32) 149 150 #define IXGBE_MAX_FRAME_SIZE 0x3F00 151 152 /* Flow control constants */ 153 #define IXGBE_FC_PAUSE 0xFFFF 154 #define IXGBE_FC_HI 0x20000 155 #define IXGBE_FC_LO 0x10000 156 157 /* Defines for printing debug information */ 158 #define DEBUG_INIT 0 159 #define DEBUG_IOCTL 0 160 #define DEBUG_HW 0 161 162 #define INIT_DEBUGOUT(S) if (DEBUG_INIT) printf(S "\n") 163 #define INIT_DEBUGOUT1(S, A) if (DEBUG_INIT) printf(S "\n", A) 164 #define INIT_DEBUGOUT2(S, A, B) if (DEBUG_INIT) printf(S "\n", A, B) 165 #define IOCTL_DEBUGOUT(S) if (DEBUG_IOCTL) printf(S "\n") 166 #define IOCTL_DEBUGOUT1(S, A) if (DEBUG_IOCTL) printf(S "\n", A) 167 #define IOCTL_DEBUGOUT2(S, A, B) if (DEBUG_IOCTL) printf(S "\n", A, B) 168 #define HW_DEBUGOUT(S) if (DEBUG_HW) printf(S "\n") 169 #define HW_DEBUGOUT1(S, A) if (DEBUG_HW) printf(S "\n", A) 170 #define HW_DEBUGOUT2(S, A, B) if (DEBUG_HW) printf(S "\n", A, B) 171 172 #define MAX_NUM_MULTICAST_ADDRESSES 128 173 #define IXGBE_82598_SCATTER 100 174 #define IXGBE_82599_SCATTER 32 175 #define MSIX_82598_BAR 3 176 #define MSIX_82599_BAR 4 177 #define IXGBE_TSO_SIZE 65535 178 #define IXGBE_TX_BUFFER_SIZE ((u32) 1514) 179 #define IXGBE_RX_HDR 128 180 #define IXGBE_VFTA_SIZE 128 181 #define IXGBE_BR_SIZE 4096 182 183 /* Offload bits in mbuf flag */ 184 #if __FreeBSD_version >= 800000 185 #define CSUM_OFFLOAD (CSUM_IP|CSUM_TCP|CSUM_UDP|CSUM_SCTP) 186 #else 187 #define CSUM_OFFLOAD (CSUM_IP|CSUM_TCP|CSUM_UDP) 188 #endif 189 190 /* For 6.X code compatibility */ 191 #if !defined(ETHER_BPF_MTAP) 192 #define ETHER_BPF_MTAP BPF_MTAP 193 #endif 194 195 #if __FreeBSD_version < 700000 196 #define CSUM_TSO 0 197 #define IFCAP_TSO4 0 198 #endif 199 200 /* 201 * Interrupt Moderation parameters 202 */ 203 #define IXGBE_LOW_LATENCY 128 204 #define IXGBE_AVE_LATENCY 400 205 #define IXGBE_BULK_LATENCY 1200 206 #define IXGBE_LINK_ITR 2000 207 208 /* Header split args for get_bug */ 209 #define IXGBE_CLEAN_HDR 1 210 #define IXGBE_CLEAN_PKT 2 211 #define IXGBE_CLEAN_ALL 3 212 213 /* 214 ***************************************************************************** 215 * vendor_info_array 216 * 217 * This array contains the list of Subvendor/Subdevice IDs on which the driver 218 * should load. 219 * 220 ***************************************************************************** 221 */ 222 typedef struct _ixgbe_vendor_info_t { 223 unsigned int vendor_id; 224 unsigned int device_id; 225 unsigned int subvendor_id; 226 unsigned int subdevice_id; 227 unsigned int index; 228 } ixgbe_vendor_info_t; 229 230 231 struct ixgbe_tx_buf { 232 u32 eop_index; 233 struct mbuf *m_head; 234 bus_dmamap_t map; 235 }; 236 237 struct ixgbe_rx_buf { 238 struct mbuf *m_head; 239 struct mbuf *m_pack; 240 struct mbuf *fmp; 241 bus_dmamap_t hmap; 242 bus_dmamap_t pmap; 243 }; 244 245 /* 246 * Bus dma allocation structure used by ixgbe_dma_malloc and ixgbe_dma_free. 247 */ 248 struct ixgbe_dma_alloc { 249 bus_addr_t dma_paddr; 250 caddr_t dma_vaddr; 251 bus_dma_tag_t dma_tag; 252 bus_dmamap_t dma_map; 253 bus_dma_segment_t dma_seg; 254 bus_size_t dma_size; 255 int dma_nseg; 256 }; 257 258 /* 259 ** Driver queue struct: this is the interrupt container 260 ** for the associated tx and rx ring. 261 */ 262 struct ix_queue { 263 struct adapter *adapter; 264 u32 msix; /* This queue's MSIX vector */ 265 u32 eims; /* This queue's EIMS bit */ 266 u32 eitr_setting; 267 struct resource *res; 268 void *tag; 269 struct tx_ring *txr; 270 struct rx_ring *rxr; 271 struct task que_task; 272 struct taskqueue *tq; 273 u64 irqs; 274 }; 275 276 /* 277 * The transmit ring, one per queue 278 */ 279 struct tx_ring { 280 struct adapter *adapter; 281 struct mtx tx_mtx; 282 u32 me; 283 bool watchdog_check; 284 int watchdog_time; 285 union ixgbe_adv_tx_desc *tx_base; 286 struct ixgbe_dma_alloc txdma; 287 u32 next_avail_desc; 288 u32 next_to_clean; 289 struct ixgbe_tx_buf *tx_buffers; 290 volatile u16 tx_avail; 291 u32 txd_cmd; 292 bus_dma_tag_t txtag; 293 char mtx_name[16]; 294 #if __FreeBSD_version >= 800000 295 struct buf_ring *br; 296 #endif 297 #ifdef IXGBE_FDIR 298 u16 atr_sample; 299 u16 atr_count; 300 #endif 301 u32 bytes; /* used for AIM */ 302 u32 packets; 303 /* Soft Stats */ 304 u64 no_desc_avail; 305 u64 total_packets; 306 }; 307 308 309 /* 310 * The Receive ring, one per rx queue 311 */ 312 struct rx_ring { 313 struct adapter *adapter; 314 struct mtx rx_mtx; 315 u32 me; 316 union ixgbe_adv_rx_desc *rx_base; 317 struct ixgbe_dma_alloc rxdma; 318 struct lro_ctrl lro; 319 bool lro_enabled; 320 bool hdr_split; 321 bool hw_rsc; 322 bool discard; 323 u32 next_to_refresh; 324 u32 next_to_check; 325 char mtx_name[16]; 326 struct ixgbe_rx_buf *rx_buffers; 327 bus_dma_tag_t htag; 328 bus_dma_tag_t ptag; 329 330 u32 bytes; /* Used for AIM calc */ 331 u32 packets; 332 333 /* Soft stats */ 334 u64 rx_irq; 335 u64 rx_split_packets; 336 u64 rx_packets; 337 u64 rx_bytes; 338 u64 rx_discarded; 339 u64 rsc_num; 340 #ifdef IXGBE_FDIR 341 u64 flm; 342 #endif 343 }; 344 345 /* Our adapter structure */ 346 struct adapter { 347 struct ifnet *ifp; 348 struct ixgbe_hw hw; 349 350 struct ixgbe_osdep osdep; 351 struct device *dev; 352 353 struct resource *pci_mem; 354 struct resource *msix_mem; 355 356 /* 357 * Interrupt resources: this set is 358 * either used for legacy, or for Link 359 * when doing MSIX 360 */ 361 void *tag; 362 struct resource *res; 363 364 struct ifmedia media; 365 struct callout timer; 366 int msix; 367 int if_flags; 368 369 struct mtx core_mtx; 370 371 eventhandler_tag vlan_attach; 372 eventhandler_tag vlan_detach; 373 374 u16 num_vlans; 375 u16 num_queues; 376 377 /* Info about the board itself */ 378 u32 optics; 379 int advertise; /* link speeds */ 380 bool link_active; 381 u16 max_frame_size; 382 u32 link_speed; 383 bool link_up; 384 u32 linkvec; 385 386 /* Mbuf cluster size */ 387 u32 rx_mbuf_sz; 388 389 /* Support for pluggable optics */ 390 bool sfp_probe; 391 struct task link_task; /* Link tasklet */ 392 struct task mod_task; /* SFP tasklet */ 393 struct task msf_task; /* Multispeed Fiber */ 394 #ifdef IXGBE_FDIR 395 int fdir_reinit; 396 struct task fdir_task; 397 #endif 398 struct taskqueue *tq; 399 400 /* 401 ** Queues: 402 ** This is the irq holder, it has 403 ** and RX/TX pair or rings associated 404 ** with it. 405 */ 406 struct ix_queue *queues; 407 408 /* 409 * Transmit rings: 410 * Allocated at run time, an array of rings. 411 */ 412 struct tx_ring *tx_rings; 413 int num_tx_desc; 414 415 /* 416 * Receive rings: 417 * Allocated at run time, an array of rings. 418 */ 419 struct rx_ring *rx_rings; 420 int num_rx_desc; 421 u64 que_mask; 422 u32 rx_process_limit; 423 424 /* Multicast array memory */ 425 u8 *mta; 426 /* Misc stats maintained by the driver */ 427 unsigned long dropped_pkts; 428 unsigned long mbuf_defrag_failed; 429 unsigned long mbuf_header_failed; 430 unsigned long mbuf_packet_failed; 431 unsigned long no_tx_map_avail; 432 unsigned long no_tx_dma_setup; 433 unsigned long watchdog_events; 434 unsigned long tso_tx; 435 unsigned long link_irq; 436 437 struct ixgbe_hw_stats stats; 438 }; 439 440 /* Precision Time Sync (IEEE 1588) defines */ 441 #define ETHERTYPE_IEEE1588 0x88F7 442 #define PICOSECS_PER_TICK 20833 443 #define TSYNC_UDP_PORT 319 /* UDP port for the protocol */ 444 #define IXGBE_ADVTXD_TSTAMP 0x00080000 445 446 447 #define IXGBE_CORE_LOCK_INIT(_sc, _name) \ 448 mtx_init(&(_sc)->core_mtx, _name, "IXGBE Core Lock", MTX_DEF) 449 #define IXGBE_CORE_LOCK_DESTROY(_sc) mtx_destroy(&(_sc)->core_mtx) 450 #define IXGBE_TX_LOCK_DESTROY(_sc) mtx_destroy(&(_sc)->tx_mtx) 451 #define IXGBE_RX_LOCK_DESTROY(_sc) mtx_destroy(&(_sc)->rx_mtx) 452 #define IXGBE_CORE_LOCK(_sc) mtx_lock(&(_sc)->core_mtx) 453 #define IXGBE_TX_LOCK(_sc) mtx_lock(&(_sc)->tx_mtx) 454 #define IXGBE_TX_TRYLOCK(_sc) mtx_trylock(&(_sc)->tx_mtx) 455 #define IXGBE_RX_LOCK(_sc) mtx_lock(&(_sc)->rx_mtx) 456 #define IXGBE_CORE_UNLOCK(_sc) mtx_unlock(&(_sc)->core_mtx) 457 #define IXGBE_TX_UNLOCK(_sc) mtx_unlock(&(_sc)->tx_mtx) 458 #define IXGBE_RX_UNLOCK(_sc) mtx_unlock(&(_sc)->rx_mtx) 459 #define IXGBE_CORE_LOCK_ASSERT(_sc) mtx_assert(&(_sc)->core_mtx, MA_OWNED) 460 #define IXGBE_TX_LOCK_ASSERT(_sc) mtx_assert(&(_sc)->tx_mtx, MA_OWNED) 461 462 463 static inline bool 464 ixgbe_is_sfp(struct ixgbe_hw *hw) 465 { 466 switch (hw->phy.type) { 467 case ixgbe_phy_sfp_avago: 468 case ixgbe_phy_sfp_ftl: 469 case ixgbe_phy_sfp_intel: 470 case ixgbe_phy_sfp_unknown: 471 case ixgbe_phy_sfp_passive_tyco: 472 case ixgbe_phy_sfp_passive_unknown: 473 return TRUE; 474 default: 475 return FALSE; 476 } 477 } 478 479 /* Workaround to make 8.0 buildable */ 480 #if __FreeBSD_version < 800504 481 static __inline int 482 drbr_needs_enqueue(struct ifnet *ifp, struct buf_ring *br) 483 { 484 #ifdef ALTQ 485 if (ALTQ_IS_ENABLED(&ifp->if_snd)) 486 return (1); 487 #endif 488 return (!buf_ring_empty(br)); 489 } 490 #endif 491 492 #endif /* _IXGBE_H_ */ 493