1 /***************************************************************************** 2 SPDX-License-Identifier: BSD-3-Clause 3 4 Copyright (c) 2001-2017, Intel Corporation 5 All rights reserved. 6 7 Redistribution and use in source and binary forms, with or without 8 modification, are permitted provided that the following conditions are met: 9 10 1. Redistributions of source code must retain the above copyright notice, 11 this list of conditions and the following disclaimer. 12 13 2. Redistributions in binary form must reproduce the above copyright 14 notice, this list of conditions and the following disclaimer in the 15 documentation and/or other materials provided with the distribution. 16 17 3. Neither the name of the Intel Corporation nor the names of its 18 contributors may be used to endorse or promote products derived from 19 this software without specific prior written permission. 20 21 THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 22 AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 23 IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 24 ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE 25 LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 26 CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 27 SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 28 INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 29 CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 30 ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 31 POSSIBILITY OF SUCH DAMAGE. 32 33 *****************************************************************************/ 34 35 #ifndef _IXGBE_H_ 36 #define _IXGBE_H_ 37 38 #include <sys/param.h> 39 #include <sys/systm.h> 40 #include <sys/buf_ring.h> 41 #include <sys/mbuf.h> 42 #include <sys/protosw.h> 43 #include <sys/socket.h> 44 #include <sys/malloc.h> 45 #include <sys/kernel.h> 46 #include <sys/module.h> 47 #include <sys/sockio.h> 48 #include <sys/eventhandler.h> 49 50 #include <net/if.h> 51 #include <net/if_var.h> 52 #include <net/if_arp.h> 53 #include <net/bpf.h> 54 #include <net/ethernet.h> 55 #include <net/if_dl.h> 56 #include <net/if_media.h> 57 58 #include <net/if_types.h> 59 #include <net/if_vlan_var.h> 60 #include <net/iflib.h> 61 62 #include <netinet/in_systm.h> 63 #include <netinet/in.h> 64 #include <netinet/if_ether.h> 65 66 #include <sys/bus.h> 67 #include <machine/bus.h> 68 #include <sys/rman.h> 69 #include <machine/resource.h> 70 #include <vm/vm.h> 71 #include <vm/pmap.h> 72 #include <machine/clock.h> 73 #include <dev/pci/pcivar.h> 74 #include <dev/pci/pcireg.h> 75 #include <sys/proc.h> 76 #include <sys/sysctl.h> 77 #include <sys/endian.h> 78 #include <sys/gtaskqueue.h> 79 #include <sys/pcpu.h> 80 #include <sys/smp.h> 81 #include <machine/smp.h> 82 #include <sys/sbuf.h> 83 84 #include "ixgbe_api.h" 85 #include "ixgbe_common.h" 86 #include "ixgbe_phy.h" 87 #include "ixgbe_vf.h" 88 #include "ixgbe_features.h" 89 #include "ixgbe_e610.h" 90 91 /* Tunables */ 92 93 /* 94 * TxDescriptors Valid Range: 64-4096 Default Value: 256 This value is the 95 * number of transmit descriptors allocated by the driver. Increasing this 96 * value allows the driver to queue more transmits. Each descriptor is 16 97 * bytes. Performance tests have show the 2K value to be optimal for top 98 * performance. 99 */ 100 #define DEFAULT_TXD 2048 101 #define PERFORM_TXD 2048 102 #define MAX_TXD 4096 103 #define MIN_TXD 64 104 105 /* 106 * RxDescriptors Valid Range: 64-4096 Default Value: 256 This value is the 107 * number of receive descriptors allocated for each RX queue. Increasing this 108 * value allows the driver to buffer more incoming packets. Each descriptor 109 * is 16 bytes. A receive buffer is also allocated for each descriptor. 110 * 111 * Note: with 8 rings and a dual port card, it is possible to bump up 112 * against the system mbuf pool limit, you can tune nmbclusters 113 * to adjust for this. 114 */ 115 #define DEFAULT_RXD 2048 116 #define PERFORM_RXD 2048 117 #define MAX_RXD 4096 118 #define MIN_RXD 64 119 120 /* Alignment for rings */ 121 #define DBA_ALIGN 128 122 123 /* 124 * This is the max watchdog interval, ie. the time that can 125 * pass between any two TX clean operations, such only happening 126 * when the TX hardware is functioning. 127 */ 128 #define IXGBE_WATCHDOG (10 * hz) 129 130 /* 131 * This parameters control when the driver calls the routine to reclaim 132 * transmit descriptors. 133 */ 134 #define IXGBE_TX_CLEANUP_THRESHOLD(_a) ((_a)->num_tx_desc / 8) 135 #define IXGBE_TX_OP_THRESHOLD(_a) ((_a)->num_tx_desc / 32) 136 137 /* These defines are used in MTU calculations */ 138 #define IXGBE_MAX_FRAME_SIZE 9728 139 #define IXGBE_MTU_HDR (ETHER_HDR_LEN + ETHER_CRC_LEN) 140 #define IXGBE_MTU_HDR_VLAN (ETHER_HDR_LEN + ETHER_CRC_LEN + \ 141 ETHER_VLAN_ENCAP_LEN) 142 #define IXGBE_MAX_MTU (IXGBE_MAX_FRAME_SIZE - IXGBE_MTU_HDR) 143 #define IXGBE_MAX_MTU_VLAN (IXGBE_MAX_FRAME_SIZE - IXGBE_MTU_HDR_VLAN) 144 145 /* Flow control constants */ 146 #define IXGBE_FC_PAUSE 0xFFFF 147 #define IXGBE_FC_HI 0x20000 148 #define IXGBE_FC_LO 0x10000 149 150 /* 151 * Used for optimizing small rx mbufs. Effort is made to keep the copy 152 * small and aligned for the CPU L1 cache. 153 * 154 * MHLEN is typically 168 bytes, giving us 8-byte alignment. Getting 155 * 32 byte alignment needed for the fast bcopy results in 8 bytes being 156 * wasted. Getting 64 byte alignment, which _should_ be ideal for 157 * modern Intel CPUs, results in 40 bytes wasted and a significant drop 158 * in observed efficiency of the optimization, 97.9% -> 81.8%. 159 */ 160 #define IXGBE_MPKTHSIZE (sizeof(struct m_hdr) + sizeof(struct pkthdr)) 161 162 #define IXGBE_RX_COPY_HDR_PADDED ((((IXGBE_MPKTHSIZE - 1) / 32) + 1) * 32) 163 #define IXGBE_RX_COPY_LEN (MSIZE - IXGBE_RX_COPY_HDR_PADDED) 164 #define IXGBE_RX_COPY_ALIGN (IXGBE_RX_COPY_HDR_PADDED - IXGBE_MPKTHSIZE) 165 166 /* Defines for printing debug information */ 167 #define DEBUG_INIT 0 168 #define DEBUG_IOCTL 0 169 #define DEBUG_HW 0 170 171 #define INIT_DEBUGOUT(S) if (DEBUG_INIT) printf(S "\n") 172 #define INIT_DEBUGOUT1(S, A) if (DEBUG_INIT) printf(S "\n", A) 173 #define INIT_DEBUGOUT2(S, A, B) if (DEBUG_INIT) printf(S "\n", A, B) 174 #define IOCTL_DEBUGOUT(S) if (DEBUG_IOCTL) printf(S "\n") 175 #define IOCTL_DEBUGOUT1(S, A) if (DEBUG_IOCTL) printf(S "\n", A) 176 #define IOCTL_DEBUGOUT2(S, A, B) if (DEBUG_IOCTL) printf(S "\n", A, B) 177 #define HW_DEBUGOUT(S) if (DEBUG_HW) printf(S "\n") 178 #define HW_DEBUGOUT1(S, A) if (DEBUG_HW) printf(S "\n", A) 179 #define HW_DEBUGOUT2(S, A, B) if (DEBUG_HW) printf(S "\n", A, B) 180 181 #define MAX_NUM_MULTICAST_ADDRESSES 128 182 #define IXGBE_82598_SCATTER 100 183 #define IXGBE_82599_SCATTER 32 184 #define IXGBE_TSO_SIZE 262140 185 #define IXGBE_RX_HDR 128 186 #define IXGBE_VFTA_SIZE 128 187 #define IXGBE_BR_SIZE 4096 188 #define IXGBE_QUEUE_MIN_FREE 32 189 #define IXGBE_MAX_TX_BUSY 10 190 #define IXGBE_QUEUE_HUNG 0x80000000 191 192 #define IXGBE_EITR_DEFAULT 128 193 194 /* Supported offload bits in mbuf flag */ 195 #define CSUM_OFFLOAD (CSUM_IP_TSO|CSUM_IP6_TSO|CSUM_IP| \ 196 CSUM_IP_UDP|CSUM_IP_TCP|CSUM_IP_SCTP| \ 197 CSUM_IP6_UDP|CSUM_IP6_TCP|CSUM_IP6_SCTP) 198 199 /* All BASE-T Physical layers */ 200 #define IXGBE_PHYSICAL_LAYERS_BASE_T_ALL \ 201 (IXGBE_PHYSICAL_LAYER_10GBASE_T |\ 202 IXGBE_PHYSICAL_LAYER_5000BASE_T |\ 203 IXGBE_PHYSICAL_LAYER_2500BASE_T |\ 204 IXGBE_PHYSICAL_LAYER_1000BASE_T |\ 205 IXGBE_PHYSICAL_LAYER_100BASE_TX |\ 206 IXGBE_PHYSICAL_LAYER_10BASE_T) 207 208 #define IXGBE_CAPS (IFCAP_HWCSUM | IFCAP_HWCSUM_IPV6 | IFCAP_TSO | \ 209 IFCAP_LRO | IFCAP_VLAN_HWTAGGING | IFCAP_VLAN_HWTSO | \ 210 IFCAP_VLAN_HWCSUM | IFCAP_JUMBO_MTU | IFCAP_VLAN_MTU | \ 211 IFCAP_VLAN_HWFILTER | IFCAP_WOL) 212 213 #ifndef DEVMETHOD_END 214 #define DEVMETHOD_END { NULL, NULL } 215 #endif 216 217 /* 218 * Interrupt Moderation parameters 219 */ 220 #define IXGBE_LOW_LATENCY 128 221 #define IXGBE_AVE_LATENCY 400 222 #define IXGBE_BULK_LATENCY 1200 223 224 /* Using 1FF (the max value), the interval is ~1.05ms */ 225 #define IXGBE_LINK_ITR_QUANTA 0x1FF 226 #define IXGBE_LINK_ITR ((IXGBE_LINK_ITR_QUANTA << 3) & \ 227 IXGBE_EITR_ITR_INT_MASK) 228 229 230 /************************************************************************ 231 * vendor_info_array 232 * 233 * Contains the list of Subvendor/Subdevice IDs on 234 * which the driver should load. 235 ************************************************************************/ 236 typedef struct _ixgbe_vendor_info_t { 237 unsigned int vendor_id; 238 unsigned int device_id; 239 unsigned int subvendor_id; 240 unsigned int subdevice_id; 241 unsigned int index; 242 } ixgbe_vendor_info_t; 243 244 struct ixgbe_bp_data { 245 u32 low; 246 u32 high; 247 u32 log; 248 }; 249 250 251 /* 252 */ 253 struct ixgbe_dma_alloc { 254 bus_addr_t dma_paddr; 255 caddr_t dma_vaddr; 256 bus_dma_tag_t dma_tag; 257 bus_dmamap_t dma_map; 258 bus_dma_segment_t dma_seg; 259 bus_size_t dma_size; 260 int dma_nseg; 261 }; 262 263 struct ixgbe_mc_addr { 264 u8 addr[IXGBE_ETH_LENGTH_OF_ADDRESS]; 265 u32 vmdq; 266 }; 267 268 /* 269 * The transmit ring, one per queue 270 */ 271 struct tx_ring { 272 struct ixgbe_softc *sc; 273 union ixgbe_adv_tx_desc *tx_base; 274 uint64_t tx_paddr; 275 u32 tail; 276 qidx_t *tx_rsq; 277 qidx_t tx_rs_cidx; 278 qidx_t tx_rs_pidx; 279 qidx_t tx_cidx_processed; 280 uint8_t me; 281 282 /* Flow Director */ 283 u16 atr_sample; 284 u16 atr_count; 285 286 u32 bytes; /* used for AIM */ 287 u32 packets; 288 /* Soft Stats */ 289 u64 tso_tx; 290 u64 total_packets; 291 }; 292 293 294 /* 295 * The Receive ring, one per rx queue 296 */ 297 struct rx_ring { 298 struct ix_rx_queue *que; 299 struct ixgbe_softc *sc; 300 u32 me; 301 u32 tail; 302 union ixgbe_adv_rx_desc *rx_base; 303 bool hw_rsc; 304 bool vtag_strip; 305 uint64_t rx_paddr; 306 bus_dma_tag_t ptag; 307 308 u32 bytes; /* Used for AIM calc */ 309 u32 packets; 310 311 /* Soft stats */ 312 u64 rx_irq; 313 u64 rx_copies; 314 u64 rx_packets; 315 u64 rx_bytes; 316 u64 rx_discarded; 317 u64 rsc_num; 318 319 /* Flow Director */ 320 u64 flm; 321 }; 322 323 /* 324 * Driver queue struct: this is the interrupt container 325 * for the associated tx and rx ring. 326 */ 327 struct ix_rx_queue { 328 struct ixgbe_softc *sc; 329 u32 msix; /* This queue's MSIX vector */ 330 u32 eitr_setting; 331 struct resource *res; 332 void *tag; 333 int busy; 334 struct rx_ring rxr; 335 struct if_irq que_irq; 336 u64 irqs; 337 }; 338 339 struct ix_tx_queue { 340 struct ixgbe_softc *sc; 341 u32 msix; /* This queue's MSIX vector */ 342 struct tx_ring txr; 343 }; 344 345 #define IXGBE_MAX_VF_MC 30 /* Max number of multicast entries */ 346 347 struct ixgbe_vf { 348 u_int pool; 349 u_int rar_index; 350 u_int maximum_frame_size; 351 uint32_t flags; 352 uint8_t ether_addr[ETHER_ADDR_LEN]; 353 uint16_t mc_hash[IXGBE_MAX_VF_MC]; 354 uint16_t num_mc_hashes; 355 uint16_t default_vlan; 356 uint16_t vlan_tag; 357 uint16_t api_ver; 358 }; 359 360 /* Our softc structure */ 361 struct ixgbe_softc { 362 struct ixgbe_hw hw; 363 struct ixgbe_osdep osdep; 364 if_ctx_t ctx; 365 if_softc_ctx_t shared; 366 #define num_tx_queues shared->isc_ntxqsets 367 #define num_rx_queues shared->isc_nrxqsets 368 #define max_frame_size shared->isc_max_frame_size 369 #define intr_type shared->isc_intr 370 371 device_t dev; 372 struct ifnet *ifp; 373 374 struct resource *pci_mem; 375 376 /* 377 * Interrupt resources: this set is 378 * either used for legacy, or for Link 379 * when doing MSI-X 380 */ 381 struct if_irq irq; 382 void *tag; 383 struct resource *res; 384 385 struct ifmedia *media; 386 int if_flags; 387 int msix; 388 389 u16 num_vlans; 390 391 /* 392 * Shadow VFTA table, this is needed because 393 * the real vlan filter table gets cleared during 394 * a soft reset and the driver needs to be able 395 * to repopulate it. 396 */ 397 u32 shadow_vfta[IXGBE_VFTA_SIZE]; 398 399 /* Info about the interface */ 400 int advertise; /* link speeds */ 401 int enable_aim; /* adaptive interrupt moderation */ 402 bool link_active; 403 u16 num_segs; 404 u32 link_speed; 405 bool link_up; 406 bool link_enabled; 407 u32 vector; 408 u16 dmac; 409 u32 phy_layer; 410 411 /* Power management-related */ 412 bool wol_support; 413 u32 wufc; 414 415 /* Mbuf cluster size */ 416 u32 rx_mbuf_sz; 417 418 /* Support for pluggable optics */ 419 bool sfp_probe; 420 421 /* Flow Director */ 422 int fdir_reinit; 423 424 u32 task_requests; 425 426 /* 427 * Queues: 428 * This is the irq holder, it has 429 * and RX/TX pair or rings associated 430 * with it. 431 */ 432 struct ix_tx_queue *tx_queues; 433 struct ix_rx_queue *rx_queues; 434 435 /* Multicast array memory */ 436 struct ixgbe_mc_addr *mta; 437 438 /* SR-IOV */ 439 int iov_mode; 440 int num_vfs; 441 int pool; 442 struct ixgbe_vf *vfs; 443 444 /* Bypass */ 445 struct ixgbe_bp_data bypass; 446 447 /* Firmware error check */ 448 int recovery_mode; 449 struct callout fw_mode_timer; 450 451 /* Misc stats maintained by the driver */ 452 unsigned long dropped_pkts; 453 unsigned long mbuf_header_failed; 454 unsigned long mbuf_packet_failed; 455 unsigned long watchdog_events; 456 unsigned long link_irq; 457 union { 458 struct ixgbe_hw_stats pf; 459 struct ixgbevf_hw_stats vf; 460 } stats; 461 462 /* counter(9) stats */ 463 u64 ipackets; 464 u64 ierrors; 465 u64 opackets; 466 u64 oerrors; 467 u64 ibytes; 468 u64 obytes; 469 u64 imcasts; 470 u64 omcasts; 471 u64 iqdrops; 472 u64 noproto; 473 474 /* Feature capable/enabled flags. See ixgbe_features.h */ 475 u32 feat_cap; 476 u32 feat_en; 477 u16 lse_mask; 478 }; 479 480 /* Precision Time Sync (IEEE 1588) defines */ 481 #define ETHERTYPE_IEEE1588 0x88F7 482 #define PICOSECS_PER_TICK 20833 483 #define TSYNC_UDP_PORT 319 /* UDP port for the protocol */ 484 #define IXGBE_ADVTXD_TSTAMP 0x00080000 485 486 /* Stats macros */ 487 #define IXGBE_SET_IPACKETS(sc, count) (sc)->ipackets = (count) 488 #define IXGBE_SET_IERRORS(sc, count) (sc)->ierrors = (count) 489 #define IXGBE_SET_OPACKETS(sc, count) (sc)->opackets = (count) 490 #define IXGBE_SET_OERRORS(sc, count) (sc)->oerrors = (count) 491 #define IXGBE_SET_COLLISIONS(sc, count) 492 #define IXGBE_SET_IBYTES(sc, count) (sc)->ibytes = (count) 493 #define IXGBE_SET_OBYTES(sc, count) (sc)->obytes = (count) 494 #define IXGBE_SET_IMCASTS(sc, count) (sc)->imcasts = (count) 495 #define IXGBE_SET_OMCASTS(sc, count) (sc)->omcasts = (count) 496 #define IXGBE_SET_IQDROPS(sc, count) (sc)->iqdrops = (count) 497 498 /* External PHY register addresses */ 499 #define IXGBE_PHY_CURRENT_TEMP 0xC820 500 #define IXGBE_PHY_OVERTEMP_STATUS 0xC830 501 502 /* Sysctl help messages; displayed with sysctl -d */ 503 #define IXGBE_SYSCTL_DESC_ADV_SPEED \ 504 "\nControl advertised link speed using these flags:\n" \ 505 "\t0x1 - advertise 100M\n" \ 506 "\t0x2 - advertise 1G\n" \ 507 "\t0x4 - advertise 10G\n" \ 508 "\t0x8 - advertise 10M\n\n" \ 509 "\t0x10 - advertise 2.5G\n" \ 510 "\t0x20 - advertise 5G\n\n" \ 511 "\t100M and 10M are only supported on certain adapters.\n" 512 513 #define IXGBE_SYSCTL_DESC_SET_FC \ 514 "\nSet flow control mode using these values:\n" \ 515 "\t0 - off\n" \ 516 "\t1 - rx pause\n" \ 517 "\t2 - tx pause\n" \ 518 "\t3 - tx and rx pause" 519 520 #define IXGBE_SYSCTL_DESC_RX_ERRS \ 521 "\nSum of the following RX errors counters:\n" \ 522 " * CRC errors,\n" \ 523 " * illegal byte error count,\n" \ 524 " * missed packet count,\n" \ 525 " * length error count,\n" \ 526 " * undersized packets count,\n" \ 527 " * fragmented packets count,\n" \ 528 " * oversized packets count,\n" \ 529 " * jabber count." 530 531 /* 532 * This checks for a zero mac addr, something that will be likely 533 * unless the Admin on the Host has created one. 534 */ 535 static inline bool 536 ixv_check_ether_addr(u8 *addr) 537 { 538 bool status = true; 539 540 if ((addr[0] == 0 && addr[1]== 0 && addr[2] == 0 && 541 addr[3] == 0 && addr[4]== 0 && addr[5] == 0)) 542 status = false; 543 544 return (status); 545 } 546 547 uint64_t ixgbe_link_speed_to_baudrate(ixgbe_link_speed speed); 548 549 /* Shared Prototypes */ 550 551 int ixgbe_allocate_queues(struct ixgbe_softc *); 552 int ixgbe_setup_transmit_structures(struct ixgbe_softc *); 553 void ixgbe_free_transmit_structures(struct ixgbe_softc *); 554 int ixgbe_setup_receive_structures(struct ixgbe_softc *); 555 void ixgbe_free_receive_structures(struct ixgbe_softc *); 556 int ixgbe_get_regs(SYSCTL_HANDLER_ARGS); 557 558 #include "ixgbe_bypass.h" 559 #include "ixgbe_fdir.h" 560 #include "ixgbe_rss.h" 561 562 #endif /* _IXGBE_H_ */ 563