1 /****************************************************************************** 2 3 Copyright (c) 2001-2017, Intel Corporation 4 All rights reserved. 5 6 Redistribution and use in source and binary forms, with or without 7 modification, are permitted provided that the following conditions are met: 8 9 1. Redistributions of source code must retain the above copyright notice, 10 this list of conditions and the following disclaimer. 11 12 2. Redistributions in binary form must reproduce the above copyright 13 notice, this list of conditions and the following disclaimer in the 14 documentation and/or other materials provided with the distribution. 15 16 3. Neither the name of the Intel Corporation nor the names of its 17 contributors may be used to endorse or promote products derived from 18 this software without specific prior written permission. 19 20 THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 21 AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 22 IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 23 ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE 24 LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 25 CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 26 SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 27 INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 28 CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 29 ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 30 POSSIBILITY OF SUCH DAMAGE. 31 32 ******************************************************************************/ 33 34 #include "ixgbe.h" 35 #include "ixgbe_sriov.h" 36 37 #ifdef PCI_IOV 38 39 #include <sys/iov.h> 40 #include <sys/ktr.h> 41 42 #include <net/if_vf_status.h> 43 44 MALLOC_DEFINE(M_IXGBE_SRIOV, "ix_sriov", "ix SR-IOV allocations"); 45 46 #define IXGBE_VF_MBX_CLEANUP_GRACE (2 * SBT_1S) 47 #define IXGBE_PRIMARY_ABORT_LIMIT 5 48 49 static const struct timeval ixgbe_mdd_log_interval = { 2, 0 }; 50 static const struct timeval ixgbe_dma_abort_log_interval = { 10, 0 }; 51 52 static bool 53 ixgbe_has_legacy_iov_recovery(const struct ixgbe_hw *hw) 54 { 55 56 return (hw->mac.type == ixgbe_mac_82599EB || 57 hw->mac.type == ixgbe_mac_X540); 58 } 59 60 /************************************************************************ 61 * ixgbe_define_iov_schemas 62 ************************************************************************/ 63 void 64 ixgbe_define_iov_schemas(struct ixgbe_softc *sc, int *error) 65 { 66 device_t dev; 67 nvlist_t *pf_schema, *vf_schema; 68 69 dev = sc->dev; 70 pf_schema = pci_iov_schema_alloc_node(); 71 vf_schema = pci_iov_schema_alloc_node(); 72 pci_iov_schema_add_unicast_mac(vf_schema, "mac-addr", 0, NULL); 73 pci_iov_schema_add_bool(vf_schema, "mac-anti-spoof", 74 IOV_SCHEMA_HASDEFAULT, true); 75 pci_iov_schema_add_bool(vf_schema, "allow-set-mac", 76 IOV_SCHEMA_HASDEFAULT, false); 77 pci_iov_schema_add_bool(vf_schema, "allow-promisc", 78 IOV_SCHEMA_HASDEFAULT, false); 79 pci_iov_schema_add_vlan(vf_schema, "vlan", IOV_SCHEMA_HASDEFAULT, 80 VF_VLAN_TRUNK); 81 *error = pci_iov_attach(dev, pf_schema, vf_schema); 82 if (*error != 0) { 83 device_printf(dev, 84 "Error %d setting up SR-IOV\n", *error); 85 } else { 86 sc->iov_attached = true; 87 } 88 } /* ixgbe_define_iov_schemas */ 89 90 /************************************************************************ 91 * ixgbe_align_all_queue_indices 92 ************************************************************************/ 93 inline void 94 ixgbe_align_all_queue_indices(struct ixgbe_softc *sc) 95 { 96 int i; 97 int index; 98 99 for (i = 0; i < sc->num_rx_queues; i++) { 100 index = ixgbe_vf_que_index(sc->iov_mode, sc->pool, i); 101 sc->rx_queues[i].rxr.me = index; 102 } 103 104 for (i = 0; i < sc->num_tx_queues; i++) { 105 index = ixgbe_vf_que_index(sc->iov_mode, sc->pool, i); 106 sc->tx_queues[i].txr.me = index; 107 } 108 } 109 110 /* Support functions for SR-IOV/VF management */ 111 static inline void 112 ixgbe_send_vf_msg(struct ixgbe_hw *hw, struct ixgbe_vf *vf, u32 msg) 113 { 114 if (vf->flags & IXGBE_VF_CTS) 115 msg |= IXGBE_VT_MSGTYPE_CTS; 116 117 ixgbe_write_mbx(hw, &msg, 1, vf->pool); 118 } 119 120 static inline void 121 ixgbe_send_vf_success(struct ixgbe_softc *sc, struct ixgbe_vf *vf, u32 msg) 122 { 123 msg &= IXGBE_VT_MSG_MASK; 124 ixgbe_send_vf_msg(&sc->hw, vf, msg | IXGBE_VT_MSGTYPE_SUCCESS); 125 } 126 127 static inline void 128 ixgbe_send_vf_failure(struct ixgbe_softc *sc, struct ixgbe_vf *vf, u32 msg) 129 { 130 msg &= IXGBE_VT_MSG_MASK; 131 ixgbe_send_vf_msg(&sc->hw, vf, msg | IXGBE_VT_MSGTYPE_FAILURE); 132 } 133 134 static inline void 135 ixgbe_process_vf_ack(struct ixgbe_softc *sc, struct ixgbe_vf *vf) 136 { 137 if (!(vf->flags & IXGBE_VF_CTS)) 138 ixgbe_send_vf_failure(sc, vf, 0); 139 } 140 141 static void 142 ixgbe_vf_set_anti_spoof(struct ixgbe_softc *sc, struct ixgbe_vf *vf) 143 { 144 struct ixgbe_hw *hw; 145 uint32_t reg; 146 bool enable; 147 148 hw = &sc->hw; 149 enable = (vf->flags & IXGBE_VF_ANTI_SPOOF) != 0; 150 if (hw->mac.ops.set_mac_anti_spoofing != NULL) 151 hw->mac.ops.set_mac_anti_spoofing(hw, enable, vf->pool); 152 if (hw->mac.ops.set_vlan_anti_spoofing != NULL) 153 hw->mac.ops.set_vlan_anti_spoofing(hw, enable, vf->pool); 154 if (hw->mac.ops.set_ethertype_anti_spoofing != NULL) { 155 if (enable) { 156 IXGBE_WRITE_REG(hw, IXGBE_ETQF(IXGBE_ETQF_FILTER_LLDP), 157 IXGBE_ETQF_FILTER_EN | IXGBE_ETQF_TX_ANTISPOOF | 158 ETHERTYPE_LLDP); 159 IXGBE_WRITE_REG(hw, IXGBE_ETQF(IXGBE_ETQF_FILTER_FC), 160 IXGBE_ETQF_FILTER_EN | IXGBE_ETQF_TX_ANTISPOOF | 161 ETHERTYPE_FLOWCONTROL); 162 } 163 hw->mac.ops.set_ethertype_anti_spoofing(hw, enable, 164 vf->pool); 165 } 166 167 reg = IXGBE_READ_REG(hw, IXGBE_VMECM(IXGBE_VF_INDEX(vf->pool))); 168 if (enable) 169 reg |= IXGBE_VF_BIT(vf->pool); 170 else 171 reg &= ~IXGBE_VF_BIT(vf->pool); 172 IXGBE_WRITE_REG(hw, IXGBE_VMECM(IXGBE_VF_INDEX(vf->pool)), reg); 173 } 174 175 static inline boolean_t 176 ixgbe_vf_mac_changed(struct ixgbe_vf *vf, const uint8_t *mac) 177 { 178 return (bcmp(mac, vf->ether_addr, ETHER_ADDR_LEN) != 0); 179 } 180 181 static bool 182 ixgbe_rar_mac_in_use(struct ixgbe_softc *sc, const uint8_t *mac, 183 int excluded_rar) 184 { 185 struct ixgbe_hw *hw; 186 uint32_t addr_high, addr_low, rah; 187 int i; 188 189 hw = &sc->hw; 190 addr_low = (uint32_t)mac[0] | ((uint32_t)mac[1] << 8) | 191 ((uint32_t)mac[2] << 16) | ((uint32_t)mac[3] << 24); 192 addr_high = (uint32_t)mac[4] | ((uint32_t)mac[5] << 8); 193 for (i = 0; i < hw->mac.num_rar_entries; i++) { 194 if (i == excluded_rar) 195 continue; 196 rah = IXGBE_READ_REG(hw, IXGBE_RAH(i)); 197 if ((rah & IXGBE_RAH_AV) != 0 && 198 (rah & 0xffff) == addr_high && 199 IXGBE_READ_REG(hw, IXGBE_RAL(i)) == addr_low) 200 return (true); 201 } 202 return (ixgbe_validate_mac_addr(hw->mac.san_addr) == IXGBE_SUCCESS && 203 bcmp(hw->mac.san_addr, mac, ETHER_ADDR_LEN) == 0); 204 } 205 206 static inline int 207 ixgbe_vf_queues(int mode) 208 { 209 switch (mode) { 210 case IXGBE_64_VM: 211 return (2); 212 case IXGBE_32_VM: 213 return (4); 214 case IXGBE_NO_VM: 215 default: 216 return (0); 217 } 218 } 219 220 inline int 221 ixgbe_vf_que_index(int mode, int vfnum, int num) 222 { 223 return ((vfnum * ixgbe_vf_queues(mode)) + num); 224 } 225 226 static inline void 227 ixgbe_update_max_frame(struct ixgbe_softc * sc, int max_frame) 228 { 229 if (sc->max_frame_size < max_frame) 230 sc->max_frame_size = max_frame; 231 } 232 233 inline u32 234 ixgbe_get_mrqc(int iov_mode) 235 { 236 u32 mrqc; 237 238 switch (iov_mode) { 239 case IXGBE_64_VM: 240 mrqc = IXGBE_MRQC_VMDQRSS64EN; 241 break; 242 case IXGBE_32_VM: 243 mrqc = IXGBE_MRQC_VMDQRSS32EN; 244 break; 245 case IXGBE_NO_VM: 246 mrqc = IXGBE_MRQC_RSSEN; 247 break; 248 default: 249 panic("Unexpected SR-IOV mode %d", iov_mode); 250 } 251 252 return mrqc; 253 } 254 255 256 inline u32 257 ixgbe_get_mtqc(int iov_mode) 258 { 259 uint32_t mtqc; 260 261 switch (iov_mode) { 262 case IXGBE_64_VM: 263 mtqc = IXGBE_MTQC_64VF | IXGBE_MTQC_VT_ENA; 264 break; 265 case IXGBE_32_VM: 266 mtqc = IXGBE_MTQC_32VF | IXGBE_MTQC_VT_ENA; 267 break; 268 case IXGBE_NO_VM: 269 mtqc = IXGBE_MTQC_64Q_1PB; 270 break; 271 default: 272 panic("Unexpected SR-IOV mode %d", iov_mode); 273 } 274 275 return mtqc; 276 } 277 278 void 279 ixgbe_ping_all_vfs(struct ixgbe_softc *sc) 280 { 281 struct ixgbe_vf *vf; 282 283 for (int i = 0; i < sc->num_vfs; i++) { 284 vf = &sc->vfs[i]; 285 if ((vf->flags & 286 (IXGBE_VF_ACTIVE | IXGBE_VF_TRAFFIC_DISABLED)) == 287 IXGBE_VF_ACTIVE) 288 ixgbe_send_vf_msg(&sc->hw, vf, IXGBE_PF_CONTROL_MSG); 289 } 290 } /* ixgbe_ping_all_vfs */ 291 292 /* 293 * Stop VF DMA before resetting the PF. A PF reset invalidates the VF queue 294 * state, so allowing an active VF to resume with its old rings can strand 295 * descriptors in both the VF and PF. Clearing CTS makes a cooperative VF 296 * renegotiate its state after the PF comes back; it is deliberately separate 297 * from IXGBE_VF_IO_DISABLED, which records a persistent administrative or 298 * recovery decision. 299 */ 300 void 301 ixgbe_quiesce_vfs(struct ixgbe_softc *sc) 302 { 303 struct ixgbe_hw *hw; 304 struct ixgbe_vf *vf; 305 uint32_t index, mask, vfre, vfte; 306 int i; 307 308 hw = &sc->hw; 309 for (i = 0; i < sc->num_vfs; i++) { 310 vf = &sc->vfs[i]; 311 if (!(vf->flags & IXGBE_VF_ACTIVE)) 312 continue; 313 314 vf->flags &= ~IXGBE_VF_CTS; 315 index = IXGBE_VF_INDEX(vf->pool); 316 mask = IXGBE_VF_BIT(vf->pool); 317 vfte = IXGBE_READ_REG(hw, IXGBE_VFTE(index)); 318 vfre = IXGBE_READ_REG(hw, IXGBE_VFRE(index)); 319 IXGBE_WRITE_REG(hw, IXGBE_VFTE(index), vfte & ~mask); 320 IXGBE_WRITE_REG(hw, IXGBE_VFRE(index), vfre & ~mask); 321 ixgbe_send_vf_msg(hw, vf, IXGBE_PF_CONTROL_MSG); 322 } 323 IXGBE_WRITE_FLUSH(hw); 324 } /* ixgbe_quiesce_vfs */ 325 326 327 static bool 328 ixgbe_pf_owns_vlan(struct ixgbe_softc *sc, uint16_t tag) 329 { 330 if_t ifp; 331 332 ifp = iflib_get_ifp(sc->ctx); 333 if ((if_getcapenable(ifp) & IFCAP_VLAN_HWFILTER) == 0) 334 return (true); 335 return ((sc->shadow_vfta[tag >> 5] & 336 (1U << (tag & 0x1f))) != 0); 337 } 338 339 static bool 340 ixgbe_vf_owns_vlan(const struct ixgbe_vf *vf, uint16_t tag) 341 { 342 343 return ((vf->vlans[tag >> 5] & (1U << (tag & 0x1f))) != 0); 344 } 345 346 static void 347 ixgbe_vf_vlan_release_pf_only(struct ixgbe_softc *sc, uint16_t tag) 348 { 349 struct ixgbe_hw *hw; 350 uint32_t bits[2]; 351 s32 slot; 352 353 hw = &sc->hw; 354 slot = ixgbe_find_vlvf_slot(hw, tag, true); 355 if (slot <= 0) 356 return; 357 bits[0] = IXGBE_READ_REG(hw, IXGBE_VLVFB(slot * 2)); 358 bits[1] = IXGBE_READ_REG(hw, IXGBE_VLVFB(slot * 2 + 1)); 359 bits[sc->pool / 32] &= ~(1U << (sc->pool % 32)); 360 if (bits[0] != 0 || bits[1] != 0) 361 return; 362 363 /* The VFTA bit still admits this VLAN to the PF's default pool. */ 364 IXGBE_WRITE_REG(hw, IXGBE_VLVF(slot), 0); 365 IXGBE_WRITE_REG(hw, IXGBE_VLVFB(slot * 2), 0); 366 IXGBE_WRITE_REG(hw, IXGBE_VLVFB(slot * 2 + 1), 0); 367 } 368 369 static s32 370 ixgbe_vf_vlan_hw_update(struct ixgbe_softc *sc, struct ixgbe_vf *vf, 371 uint16_t tag, bool enable) 372 { 373 struct ixgbe_hw *hw; 374 s32 error; 375 376 hw = &sc->hw; 377 if (!enable && 378 ixgbe_find_vlvf_slot(hw, tag, true) < IXGBE_SUCCESS) 379 return (IXGBE_SUCCESS); 380 /* 381 * Allocate the VLVF entry with the PF first when it also owns this 382 * VLAN. This guarantees that adding the VF cannot hide the VLAN from 383 * the PF when the shared VFTA bit becomes pool-selective. 384 */ 385 if (enable && ixgbe_pf_owns_vlan(sc, tag)) { 386 error = ixgbe_set_vfta(hw, tag, sc->pool, true, false); 387 if (error != IXGBE_SUCCESS) 388 return (error); 389 } 390 391 error = ixgbe_set_vfta(hw, tag, vf->pool, enable, false); 392 if (error != IXGBE_SUCCESS) 393 return (error); 394 395 /* Free a PF-only VLVF slot without removing the PF's VFTA bit. */ 396 if (!enable && ixgbe_pf_owns_vlan(sc, tag)) 397 ixgbe_vf_vlan_release_pf_only(sc, tag); 398 return (IXGBE_SUCCESS); 399 } 400 401 static void 402 ixgbe_vf_vlan_record(struct ixgbe_vf *vf, uint16_t tag, bool enable) 403 { 404 u32 mask; 405 406 mask = 1U << (tag & 0x1f); 407 if (enable) { 408 vf->vlans[tag >> 5] |= mask; 409 vf->num_vlans++; 410 } else { 411 vf->vlans[tag >> 5] &= ~mask; 412 vf->num_vlans--; 413 } 414 } 415 416 static void 417 ixgbe_vf_configure_vmolr(struct ixgbe_softc *sc, struct ixgbe_vf *vf) 418 { 419 struct ixgbe_hw *hw; 420 uint32_t vmolr, vmvir; 421 uint8_t xcast_mode; 422 uint16_t tag; 423 424 hw = &sc->hw; 425 tag = vf->default_vlan; 426 427 vmolr = IXGBE_READ_REG(hw, IXGBE_VMOLR(vf->pool)); 428 429 vmolr &= ~(IXGBE_VMOLR_UPE | IXGBE_VMOLR_ROMPE | 430 IXGBE_VMOLR_ROPE | IXGBE_VMOLR_MPE | IXGBE_VMOLR_VPE | 431 IXGBE_VMOLR_AUPE); 432 433 /* Accept broadcasts. */ 434 vmolr |= IXGBE_VMOLR_BAM; 435 436 if (tag == 0) { 437 /* Accept non-vlan tagged traffic. */ 438 vmolr |= IXGBE_VMOLR_AUPE; 439 440 /* Allow VM to tag outgoing traffic; no default tag. */ 441 vmvir = 0; 442 } else { 443 /* Require vlan-tagged traffic. */ 444 vmolr &= ~IXGBE_VMOLR_AUPE; 445 446 /* Tag all traffic with provided vlan tag. */ 447 vmvir = (tag | IXGBE_VMVIR_VLANA_DEFAULT); 448 } 449 450 xcast_mode = vf->xcast_mode; 451 if ((vf->api_ver == IXGBE_API_VER_UNKNOWN || 452 vf->api_ver < IXGBE_API_VER_1_2) && vf->num_mc_hashes != 0) 453 xcast_mode = IXGBEVF_XCAST_MODE_MULTI; 454 switch (xcast_mode) { 455 case IXGBEVF_XCAST_MODE_PROMISC: 456 vmolr |= IXGBE_VMOLR_UPE; 457 /* FALLTHROUGH */ 458 case IXGBEVF_XCAST_MODE_ALLMULTI: 459 vmolr |= IXGBE_VMOLR_MPE; 460 /* FALLTHROUGH */ 461 case IXGBEVF_XCAST_MODE_MULTI: 462 vmolr |= IXGBE_VMOLR_ROMPE; 463 break; 464 case IXGBEVF_XCAST_MODE_NONE: 465 default: 466 break; 467 } 468 IXGBE_WRITE_REG(hw, IXGBE_VMOLR(vf->pool), vmolr); 469 IXGBE_WRITE_REG(hw, IXGBE_VMVIR(vf->pool), vmvir); 470 } /* ixgbe_vf_configure_vmolr */ 471 472 static void 473 ixgbe_vf_clear_vlans(struct ixgbe_softc *sc, struct ixgbe_vf *vf, 474 bool clear_hw) 475 { 476 uint32_t bits; 477 int bit, index; 478 479 for (index = 0; index < IXGBE_VFTA_SIZE; index++) { 480 bits = vf->vlans[index]; 481 while (bits != 0) { 482 bit = ffs(bits) - 1; 483 if (clear_hw) 484 (void)ixgbe_vf_vlan_hw_update(sc, vf, 485 index * 32 + bit, false); 486 bits &= ~(1U << bit); 487 } 488 } 489 bzero(vf->vlans, sizeof(vf->vlans)); 490 vf->num_vlans = 0; 491 } 492 493 static s32 494 ixgbe_vf_reset_vlan(struct ixgbe_softc *sc, struct ixgbe_vf *vf, 495 bool clear_hw) 496 { 497 s32 error; 498 499 ixgbe_vf_clear_vlans(sc, vf, clear_hw); 500 if (vf->default_vlan == 0) { 501 /* VLAN 0 membership is implicit and not VF-removable. */ 502 error = ixgbe_vf_vlan_hw_update(sc, vf, 0, true); 503 } else { 504 error = ixgbe_vf_vlan_hw_update(sc, vf, vf->default_vlan, true); 505 if (error == IXGBE_SUCCESS) 506 ixgbe_vf_vlan_record(vf, vf->default_vlan, true); 507 } 508 ixgbe_vf_configure_vmolr(sc, vf); 509 return (error); 510 } 511 512 static void 513 ixgbe_vf_clear_mac_filters(struct ixgbe_softc *sc, struct ixgbe_vf *vf, 514 bool clear_hw) 515 { 516 struct ixgbe_vf_mac_filter *filter; 517 int i; 518 519 for (i = 0; i < sc->num_vf_mac_filters; i++) { 520 filter = &sc->vf_mac_filters[i]; 521 if (!filter->active || filter->pool != vf->pool) 522 continue; 523 if (clear_hw) 524 (void)ixgbe_clear_rar(&sc->hw, filter->rar_index); 525 filter->active = false; 526 bzero(filter->mac, sizeof(filter->mac)); 527 } 528 vf->num_mac_filters = 0; 529 } 530 531 static boolean_t 532 ixgbe_vf_frame_size_compatible(struct ixgbe_softc *sc, struct ixgbe_vf *vf) 533 { 534 if_t ifp; 535 bool pf_jumbo; 536 537 /* 538 * Frame size compatibility between PF and VF is only a problem on 539 * 82599-based cards. X540 and later support any combination of jumbo 540 * frames on PFs and VFs. 541 */ 542 if (sc->hw.mac.type != ixgbe_mac_82599EB) 543 return (true); 544 545 /* sc->max_frame_size includes VF requests; use the PF's actual MTU. */ 546 ifp = iflib_get_ifp(sc->ctx); 547 pf_jumbo = if_getmtu(ifp) > ETHERMTU; 548 549 switch (vf->api_ver) { 550 case IXGBE_API_VER_1_0: 551 case IXGBE_API_VER_UNKNOWN: 552 /* 553 * On legacy (1.0 and older) VF versions, we don't support 554 * jumbo frames on either the PF or the VF. 555 */ 556 if (pf_jumbo || vf->maximum_frame_size > ETHER_MAX_LEN) 557 return (false); 558 559 return (true); 560 561 break; 562 case IXGBE_API_VER_1_1: 563 default: 564 /* 565 * 1.1 or later VF versions always work if they aren't using 566 * jumbo frames. 567 */ 568 if (vf->maximum_frame_size <= ETHER_MAX_LEN) 569 return (true); 570 571 /* 572 * Jumbo frames only work with VFs if the PF is also using 573 * jumbo frames. 574 */ 575 return (pf_jumbo); 576 } 577 } /* ixgbe_vf_frame_size_compatible */ 578 579 580 static void 581 ixgbe_process_vf_reset(struct ixgbe_softc *sc, struct ixgbe_vf *vf) 582 { 583 struct ixgbe_hw *hw; 584 bool rebuild_mta; 585 s32 error; 586 int i, queue_count; 587 588 hw = &sc->hw; 589 vf->flags &= ~IXGBE_VF_CTS; 590 rebuild_mta = vf->num_mc_hashes != 0; 591 vf->xcast_mode = IXGBEVF_XCAST_MODE_NONE; 592 vf->num_mc_hashes = 0; 593 bzero(vf->mc_hash, sizeof(vf->mc_hash)); 594 error = ixgbe_vf_reset_vlan(sc, vf, true); 595 if (error != IXGBE_SUCCESS) 596 device_printf(sc->dev, 597 "VF %u default VLAN restore failed: %d\n", 598 vf->pool, error); 599 if (rebuild_mta) 600 ixgbe_iov_rebuild_mta(sc); 601 602 ixgbe_vf_clear_mac_filters(sc, vf, true); 603 ixgbe_clear_rar(hw, vf->rar_index); 604 ixgbe_vf_set_anti_spoof(sc, vf); 605 ixgbe_toggle_txdctl(hw, vf->pool); 606 607 /* VFLR does not clear transmit head write-back state. */ 608 queue_count = ixgbe_vf_queues(sc->iov_mode); 609 for (i = 0; i < queue_count; i++) { 610 IXGBE_WRITE_REG(hw, 611 IXGBE_PVFTDWBAHn(queue_count, vf->pool, i), 0); 612 IXGBE_WRITE_REG(hw, 613 IXGBE_PVFTDWBALn(queue_count, vf->pool, i), 0); 614 } 615 616 /* VFLR also leaves malicious-driver queue blocks asserted. */ 617 ixgbe_restore_mdd_vf(hw, vf->pool); 618 619 vf->flags &= ~(IXGBE_VF_INIT_DONE | IXGBE_VF_MDD_BLOCKED | 620 IXGBE_VF_MDD_NOTIFY_PENDING); 621 vf->api_ver = IXGBE_API_VER_UNKNOWN; 622 vf->recovery_tx_pending = 0; 623 } /* ixgbe_process_vf_reset */ 624 625 626 static void 627 ixgbe_vf_enable_transmit(struct ixgbe_softc *sc, struct ixgbe_vf *vf) 628 { 629 struct ixgbe_hw *hw; 630 uint32_t vf_index, vfte; 631 632 hw = &sc->hw; 633 634 vf_index = IXGBE_VF_INDEX(vf->pool); 635 vfte = IXGBE_READ_REG(hw, IXGBE_VFTE(vf_index)); 636 if (vf->flags & IXGBE_VF_TRAFFIC_DISABLED) 637 vfte &= ~IXGBE_VF_BIT(vf->pool); 638 else 639 vfte |= IXGBE_VF_BIT(vf->pool); 640 IXGBE_WRITE_REG(hw, IXGBE_VFTE(vf_index), vfte); 641 } /* ixgbe_vf_enable_transmit */ 642 643 644 static void 645 ixgbe_vf_set_rx_drop(struct ixgbe_softc *sc, struct ixgbe_vf *vf, 646 bool enable) 647 { 648 struct ixgbe_hw *hw; 649 u32 qde; 650 int i, queue_count; 651 652 hw = &sc->hw; 653 queue_count = ixgbe_vf_queues(sc->iov_mode); 654 for (i = 0; i < queue_count; i++) { 655 qde = IXGBE_QDE_WRITE | 656 (ixgbe_vf_que_index(sc->iov_mode, vf->pool, i) << 657 IXGBE_QDE_IDX_SHIFT); 658 if (enable) { 659 qde |= IXGBE_QDE_ENABLE; 660 if (vf->default_vlan != 0 && 661 hw->mac.type >= ixgbe_mac_X550) 662 qde |= IXGBE_QDE_HIDE_VLAN; 663 } 664 IXGBE_WRITE_REG(hw, IXGBE_QDE, qde); 665 IXGBE_WRITE_FLUSH(hw); 666 } 667 } 668 669 static void 670 ixgbe_vf_enable_receive(struct ixgbe_softc *sc, struct ixgbe_vf *vf) 671 { 672 struct ixgbe_hw *hw; 673 uint32_t vf_index, vfre; 674 675 hw = &sc->hw; 676 /* Keep one VF without receive descriptors from blocking its peers. */ 677 ixgbe_vf_set_rx_drop(sc, vf, true); 678 679 vf_index = IXGBE_VF_INDEX(vf->pool); 680 vfre = IXGBE_READ_REG(hw, IXGBE_VFRE(vf_index)); 681 if (!(vf->flags & IXGBE_VF_TRAFFIC_DISABLED) && 682 ixgbe_vf_frame_size_compatible(sc, vf)) 683 vfre |= IXGBE_VF_BIT(vf->pool); 684 else 685 vfre &= ~IXGBE_VF_BIT(vf->pool); 686 IXGBE_WRITE_REG(hw, IXGBE_VFRE(vf_index), vfre); 687 } /* ixgbe_vf_enable_receive */ 688 689 690 static void 691 ixgbe_find_vf_devices(struct ixgbe_softc *sc, int iov_pos, 692 device_t *vfdev, int num_vfs) 693 { 694 device_t *children; 695 u16 first_rid, rid_offset, rid_stride, vf_device_id; 696 int child_count, i, vfnum; 697 698 rid_offset = pci_read_config(sc->dev, 699 iov_pos + PCIR_SRIOV_VF_OFF, 2); 700 rid_stride = pci_read_config(sc->dev, 701 iov_pos + PCIR_SRIOV_VF_STRIDE, 2); 702 vf_device_id = pci_read_config(sc->dev, 703 iov_pos + PCIR_SRIOV_VF_DID, 2); 704 first_rid = pci_get_rid(sc->dev) + rid_offset; 705 if (device_get_children(device_get_parent(sc->dev), &children, 706 &child_count) != 0) 707 return; 708 for (i = 0; i < child_count; i++) { 709 if (pci_get_vendor(children[i]) != IXGBE_INTEL_VENDOR_ID || 710 pci_get_device(children[i]) != vf_device_id) 711 continue; 712 for (vfnum = 0; vfnum < num_vfs; vfnum++) { 713 if (pci_get_rid(children[i]) == 714 first_rid + vfnum * rid_stride) { 715 vfdev[vfnum] = children[i]; 716 break; 717 } 718 } 719 } 720 free(children, M_TEMP); 721 } 722 723 static void 724 ixgbe_vf_tx_sample_reset(struct ixgbe_vf *vf) 725 { 726 727 vf->recovery_tx_pending = 0; 728 } 729 730 /* 731 * TXDGPC is a clear-on-read, PF-wide counter. A zero sample says only that 732 * no packet completed during the interval; it does not distinguish an idle 733 * VF from a stalled one. Require a VF queue to have outstanding descriptors 734 * and an unchanged head across two consecutive zero-completion samples. 735 */ 736 static bool 737 ixgbe_vf_tx_stalled(struct ixgbe_softc *sc, struct ixgbe_vf *vf) 738 { 739 u32 head, pending, previous, tail; 740 int i, queue_count; 741 bool stalled; 742 743 queue_count = ixgbe_vf_queues(sc->iov_mode); 744 previous = vf->recovery_tx_pending; 745 pending = 0; 746 stalled = false; 747 for (i = 0; i < queue_count; i++) { 748 head = IXGBE_READ_REG(&sc->hw, 749 IXGBE_PVFTDHn(queue_count, vf->pool, i)); 750 tail = IXGBE_READ_REG(&sc->hw, 751 IXGBE_PVFTDTn(queue_count, vf->pool, i)); 752 if (head == UINT32_MAX || tail == UINT32_MAX) { 753 ixgbe_vf_tx_sample_reset(vf); 754 return (false); 755 } 756 if (head != tail) { 757 pending |= 1U << i; 758 if ((previous & (1U << i)) != 0 && 759 vf->recovery_tx_head[i] == head) 760 stalled = true; 761 } 762 vf->recovery_tx_head[i] = head; 763 } 764 vf->recovery_tx_pending = pending; 765 return (stalled); 766 } 767 768 static void 769 ixgbe_iov_recovery_task(void *context, int pending __unused) 770 { 771 if_ctx_t ctx; 772 device_t vfdev[IXGBE_64_VM] = {}; 773 struct ixgbe_softc *sc; 774 struct ixgbe_vf *vf; 775 struct sx *ctx_lock; 776 bool new_event, quarantined, report, scan, success; 777 u16 command, status; 778 u32 tx_good; 779 u64 recovery_vfs, stalled_vfs; 780 u_int flr_delay; 781 int i, iov_pos, n, num_vfs = 0, recovery_vf; 782 783 ctx = context; 784 if (iflib_in_detach(ctx)) 785 return; 786 sc = iflib_get_softc(ctx); 787 ctx_lock = iflib_ctx_lock_get(ctx); 788 789 /* Match PCI-IOV's topology-before-driver lock order. */ 790 bus_topo_lock(); 791 sx_xlock(ctx_lock); 792 if (sc->iov_recovery_stop || 793 !(sc->feat_en & IXGBE_FEATURE_SRIOV) || 794 !ixgbe_has_legacy_iov_recovery(&sc->hw) || 795 pci_find_extcap(sc->dev, PCIZ_SRIOV, &iov_pos) != 0) 796 goto out_unlock; 797 num_vfs = sc->num_vfs; 798 ixgbe_find_vf_devices(sc, iov_pos, vfdev, num_vfs); 799 for (i = 0; i < num_vfs; i++) { 800 if (vfdev[i] != NULL) 801 device_busy(vfdev[i]); 802 } 803 804 recovery_vfs = 0; 805 stalled_vfs = 0; 806 recovery_vf = -1; 807 new_event = false; 808 quarantined = false; 809 for (i = 0; i < num_vfs; i++) { 810 if (sc->vfs[i].flags & IXGBE_VF_DMA_ABORT_PENDING) 811 recovery_vfs |= 1ULL << i; 812 } 813 scan = false; 814 if (sc->link_up) { 815 tx_good = IXGBE_READ_REG(&sc->hw, IXGBE_TXDGPC); 816 scan = tx_good == 0; 817 if (tx_good == UINT32_MAX) 818 scan = false; 819 } 820 if (scan) { 821 for (i = 0; i < num_vfs; i++) { 822 vf = &sc->vfs[i]; 823 if (vfdev[i] == NULL || 824 !(vf->flags & IXGBE_VF_ACTIVE) || 825 (vf->flags & IXGBE_VF_IO_DISABLED)) { 826 ixgbe_vf_tx_sample_reset(vf); 827 continue; 828 } 829 if (ixgbe_vf_tx_stalled(sc, vf)) 830 stalled_vfs |= 1ULL << i; 831 } 832 } else { 833 for (i = 0; i < num_vfs; i++) 834 ixgbe_vf_tx_sample_reset(&sc->vfs[i]); 835 } 836 837 if (scan) { 838 for (n = 0; n < num_vfs; n++) { 839 i = (sc->iov_recovery_cursor + n) % num_vfs; 840 vf = &sc->vfs[i]; 841 if ((stalled_vfs & (1ULL << i)) == 0) 842 continue; 843 status = pci_read_config(vfdev[i], PCIR_STATUS, 2); 844 if (status == UINT16_MAX || 845 !(status & PCIM_STATUS_RMABORT)) 846 continue; 847 848 /* PCI status error bits are write-one-to-clear. */ 849 pci_write_config(vfdev[i], PCIR_STATUS, 850 PCIM_STATUS_RMABORT, 2); 851 ixgbe_vf_tx_sample_reset(vf); 852 vf->flags |= IXGBE_VF_DMA_ABORT_PENDING; 853 vf->flags &= ~IXGBE_VF_CTS; 854 vf->primary_abort_count++; 855 if (vf->primary_abort_count == 856 IXGBE_PRIMARY_ABORT_LIMIT) { 857 vf->flags |= IXGBE_VF_QUARANTINED; 858 sc->iov_dma_abort_quarantines++; 859 sc->iov_quarantined_vfs |= 1ULL << i; 860 quarantined = true; 861 } 862 ixgbe_vf_enable_transmit(sc, vf); 863 ixgbe_vf_enable_receive(sc, vf); 864 IXGBE_WRITE_FLUSH(&sc->hw); 865 sc->iov_dma_abort_events++; 866 recovery_vfs |= 1ULL << i; 867 recovery_vf = i; 868 new_event = true; 869 break; 870 } 871 } 872 if (recovery_vf == -1) { 873 for (n = 0; n < num_vfs; n++) { 874 i = (sc->iov_recovery_cursor + n) % num_vfs; 875 if ((recovery_vfs & (1ULL << i)) != 0 && 876 vfdev[i] != NULL) { 877 recovery_vf = i; 878 break; 879 } 880 } 881 } 882 if (recovery_vf == -1) 883 goto out_unlock; 884 /* Bound latency to one VF FLR per pass without starving other VFs. */ 885 sc->iov_recovery_cursor = (recovery_vf + 1) % num_vfs; 886 887 /* Busy references keep every VF child stable while Giant is dropped. */ 888 bus_topo_unlock(); 889 i = recovery_vf; 890 vf = &sc->vfs[i]; 891 flr_delay = MAX(pcie_get_max_completion_timeout(vfdev[i]) / 1000, 10); 892 command = pci_read_config(vfdev[i], PCIR_COMMAND, 2); 893 if (command != UINT16_MAX) { 894 if (!(vf->flags & IXGBE_VF_PCI_STATE_SAVED)) { 895 pci_save_state(vfdev[i]); 896 vf->pci_saved_command = command; 897 vf->flags |= IXGBE_VF_PCI_STATE_SAVED; 898 } 899 success = pcie_flr(vfdev[i], flr_delay, true); 900 } else 901 success = false; 902 if (success && !(vf->flags & IXGBE_VF_QUARANTINED)) { 903 /* Restore and verify the complete state for a usable VF. */ 904 pci_restore_state(vfdev[i]); 905 command = pci_read_config(vfdev[i], PCIR_COMMAND, 2); 906 success = command == vf->pci_saved_command; 907 } else if (success) { 908 /* 909 * Leave the function in post-FLR configuration. Ensure that 910 * decode and bus mastering remain disabled, then refresh the 911 * PCI layer's cached Command state so a later restore cannot 912 * re-enable them. 913 */ 914 command = pci_read_config(vfdev[i], PCIR_COMMAND, 2); 915 if (command != UINT16_MAX) { 916 command &= ~(PCIM_CMD_PORTEN | PCIM_CMD_MEMEN | 917 PCIM_CMD_BUSMASTEREN); 918 pci_write_config(vfdev[i], PCIR_COMMAND, command, 2); 919 command = pci_read_config(vfdev[i], PCIR_COMMAND, 2); 920 } 921 success = command != UINT16_MAX && 922 (command & (PCIM_CMD_PORTEN | PCIM_CMD_MEMEN | 923 PCIM_CMD_BUSMASTEREN)) == 0; 924 if (success) 925 pci_save_state(vfdev[i]); 926 } 927 if (success) { 928 vf->flags &= ~(IXGBE_VF_DMA_ABORT_PENDING | 929 IXGBE_VF_PCI_STATE_SAVED); 930 vf->pci_saved_command = 0; 931 } else 932 sc->iov_dma_abort_flr_failures++; 933 if (quarantined) { 934 device_printf(sc->dev, 935 "quarantined VF %u after %u invalid DMA targets%s\n", 936 vf->pool, IXGBE_PRIMARY_ABORT_LIMIT, 937 success ? "" : "; function-level reset failed"); 938 } else { 939 report = ratecheck(&vf->last_dma_abort_log, 940 &ixgbe_dma_abort_log_interval) != 0; 941 if (report && (new_event || !success)) { 942 if (success) 943 device_printf(sc->dev, 944 "invalid DMA target from VF %u; reset VF\n", 945 vf->pool); 946 else 947 device_printf(sc->dev, 948 "could not reset VF %u after an invalid DMA " 949 "target; VF remains disabled\n", vf->pool); 950 } 951 } 952 sx_xunlock(ctx_lock); 953 for (i = 0; i < num_vfs; i++) { 954 if (vfdev[i] != NULL) 955 device_unbusy(vfdev[i]); 956 } 957 return; 958 959 out_unlock: 960 for (i = 0; i < num_vfs; i++) { 961 if (vfdev[i] != NULL) 962 device_unbusy(vfdev[i]); 963 } 964 sx_xunlock(ctx_lock); 965 bus_topo_unlock(); 966 } 967 968 void 969 ixgbe_init_iov_recovery(struct ixgbe_softc *sc) 970 { 971 972 sc->iov_recovery_stop = false; 973 iflib_config_task_init(sc->ctx, &sc->iov_recovery_task, 974 ixgbe_iov_recovery_task); 975 } 976 977 void 978 ixgbe_schedule_iov_recovery(struct ixgbe_softc *sc) 979 { 980 bool pending; 981 sbintime_t now; 982 int i; 983 984 if (sc->iov_recovery_stop || 985 !(sc->feat_en & IXGBE_FEATURE_SRIOV) || 986 !ixgbe_has_legacy_iov_recovery(&sc->hw)) 987 return; 988 pending = false; 989 for (i = 0; i < sc->num_vfs; i++) { 990 if (sc->vfs[i].flags & IXGBE_VF_DMA_ABORT_PENDING) { 991 pending = true; 992 break; 993 } 994 } 995 if (!sc->link_up && !pending) 996 return; 997 now = sbinuptime(); 998 if (now < sc->iov_recovery_time) 999 return; 1000 sc->iov_recovery_time = now + 2 * SBT_1S; 1001 iflib_config_task_enqueue(sc->ctx, &sc->iov_recovery_task); 1002 } 1003 1004 1005 static void 1006 ixgbe_vf_reset_msg(struct ixgbe_softc *sc, struct ixgbe_vf *vf, uint32_t *msg) 1007 { 1008 struct ixgbe_hw *hw; 1009 uint32_t ack; 1010 uint32_t resp[IXGBE_VF_PERMADDR_MSG_LEN]; 1011 1012 hw = &sc->hw; 1013 if (vf->flags & IXGBE_VF_IO_DISABLED) { 1014 ixgbe_send_vf_failure(sc, vf, msg[0]); 1015 return; 1016 } 1017 1018 ixgbe_process_vf_reset(sc, vf); 1019 1020 if (ixgbe_validate_mac_addr(vf->ether_addr) == 0) { 1021 ixgbe_set_rar(&sc->hw, vf->rar_index, vf->ether_addr, 1022 vf->pool, true); 1023 ack = IXGBE_VT_MSGTYPE_SUCCESS; 1024 } else 1025 ack = IXGBE_VT_MSGTYPE_FAILURE; 1026 1027 ixgbe_vf_enable_transmit(sc, vf); 1028 ixgbe_vf_enable_receive(sc, vf); 1029 1030 vf->flags |= IXGBE_VF_CTS | IXGBE_VF_INIT_DONE; 1031 1032 resp[0] = IXGBE_VF_RESET | ack; 1033 bcopy(vf->ether_addr, &resp[1], ETHER_ADDR_LEN); 1034 resp[3] = hw->mac.mc_filter_type; 1035 ixgbe_write_mbx(hw, resp, IXGBE_VF_PERMADDR_MSG_LEN, vf->pool); 1036 } /* ixgbe_vf_reset_msg */ 1037 1038 1039 static void 1040 ixgbe_vf_set_mac(struct ixgbe_softc *sc, struct ixgbe_vf *vf, uint32_t *msg) 1041 { 1042 uint8_t *mac; 1043 1044 mac = (uint8_t*)&msg[1]; 1045 1046 /* Check that the VF has permission to change the MAC address. */ 1047 if (!(vf->flags & IXGBE_VF_CAP_MAC) && ixgbe_vf_mac_changed(vf, mac)) { 1048 ixgbe_send_vf_failure(sc, vf, msg[0]); 1049 return; 1050 } 1051 1052 if (ixgbe_validate_mac_addr(mac) != 0) { 1053 ixgbe_send_vf_failure(sc, vf, msg[0]); 1054 return; 1055 } 1056 if (ixgbe_vf_mac_changed(vf, mac) && 1057 ixgbe_rar_mac_in_use(sc, mac, vf->rar_index)) { 1058 ixgbe_send_vf_failure(sc, vf, msg[0]); 1059 return; 1060 } 1061 1062 bcopy(mac, vf->ether_addr, ETHER_ADDR_LEN); 1063 1064 ixgbe_set_rar(&sc->hw, vf->rar_index, vf->ether_addr, vf->pool, 1065 true); 1066 1067 ixgbe_send_vf_success(sc, vf, msg[0]); 1068 } /* ixgbe_vf_set_mac */ 1069 1070 1071 /* 1072 * VF multicast addresses are set by using the appropriate bit in 1073 * 1 of 128 32 bit addresses (4096 possible). 1074 */ 1075 static void 1076 ixgbe_vf_set_mc_addr(struct ixgbe_softc *sc, struct ixgbe_vf *vf, u32 *msg) 1077 { 1078 u16 *list = (u16*)&msg[1]; 1079 int entries; 1080 1081 entries = (msg[0] & IXGBE_VT_MSGINFO_MASK) >> 1082 IXGBE_VT_MSGINFO_SHIFT; 1083 entries = min(entries, IXGBE_MAX_VF_MC); 1084 1085 bzero(vf->mc_hash, sizeof(vf->mc_hash)); 1086 bcopy(list, vf->mc_hash, entries * sizeof(*list)); 1087 vf->num_mc_hashes = entries; 1088 if (entries != 0 && vf->xcast_mode == IXGBEVF_XCAST_MODE_NONE) 1089 vf->xcast_mode = IXGBEVF_XCAST_MODE_MULTI; 1090 else if (entries == 0 && 1091 vf->xcast_mode == IXGBEVF_XCAST_MODE_MULTI) 1092 vf->xcast_mode = IXGBEVF_XCAST_MODE_NONE; 1093 ixgbe_iov_rebuild_mta(sc); 1094 ixgbe_vf_configure_vmolr(sc, vf); 1095 ixgbe_send_vf_success(sc, vf, msg[0]); 1096 } /* ixgbe_vf_set_mc_addr */ 1097 1098 1099 static void 1100 ixgbe_vf_set_vlan(struct ixgbe_softc *sc, struct ixgbe_vf *vf, uint32_t *msg) 1101 { 1102 bool enable, present; 1103 s32 error; 1104 uint16_t tag; 1105 1106 enable = IXGBE_VT_MSGINFO(msg[0]) != 0; 1107 tag = msg[1] & IXGBE_VLVF_VLANID_MASK; 1108 1109 if (!(vf->flags & IXGBE_VF_CAP_VLAN) || vf->default_vlan != 0 || 1110 (msg[1] & ~IXGBE_VLVF_VLANID_MASK) != 0) { 1111 ixgbe_send_vf_failure(sc, vf, msg[0]); 1112 return; 1113 } 1114 1115 /* It is illegal to enable vlan tag 0. */ 1116 if (tag == 0 && enable) { 1117 ixgbe_send_vf_failure(sc, vf, msg[0]); 1118 return; 1119 } 1120 1121 present = ixgbe_vf_owns_vlan(vf, tag); 1122 if (enable == present) { 1123 ixgbe_send_vf_success(sc, vf, msg[0]); 1124 return; 1125 } 1126 1127 error = ixgbe_vf_vlan_hw_update(sc, vf, tag, enable); 1128 if (error != IXGBE_SUCCESS) { 1129 ixgbe_send_vf_failure(sc, vf, msg[0]); 1130 return; 1131 } 1132 ixgbe_vf_vlan_record(vf, tag, enable); 1133 ixgbe_send_vf_success(sc, vf, msg[0]); 1134 } /* ixgbe_vf_set_vlan */ 1135 1136 1137 static void 1138 ixgbe_vf_set_lpe(struct ixgbe_softc *sc, struct ixgbe_vf *vf, uint32_t *msg) 1139 { 1140 struct ixgbe_hw *hw; 1141 uint32_t vf_max_size, pf_max_size, mhadd; 1142 1143 hw = &sc->hw; 1144 vf_max_size = msg[1]; 1145 1146 if (vf_max_size < ETHER_CRC_LEN) { 1147 /* We intentionally ACK invalid LPE requests. */ 1148 ixgbe_send_vf_success(sc, vf, msg[0]); 1149 return; 1150 } 1151 1152 vf_max_size -= ETHER_CRC_LEN; 1153 1154 if (vf_max_size > IXGBE_MAX_FRAME_SIZE) { 1155 /* We intentionally ACK invalid LPE requests. */ 1156 ixgbe_send_vf_success(sc, vf, msg[0]); 1157 return; 1158 } 1159 1160 vf->maximum_frame_size = vf_max_size; 1161 ixgbe_recalculate_max_frame(sc); 1162 1163 /* 1164 * We might have to disable reception to this VF if the frame size is 1165 * not compatible with the config on the PF. 1166 */ 1167 ixgbe_vf_enable_receive(sc, vf); 1168 1169 mhadd = IXGBE_READ_REG(hw, IXGBE_MHADD); 1170 pf_max_size = (mhadd & IXGBE_MHADD_MFS_MASK) >> IXGBE_MHADD_MFS_SHIFT; 1171 1172 if (pf_max_size != sc->max_frame_size) { 1173 mhadd &= ~IXGBE_MHADD_MFS_MASK; 1174 mhadd |= sc->max_frame_size << IXGBE_MHADD_MFS_SHIFT; 1175 IXGBE_WRITE_REG(hw, IXGBE_MHADD, mhadd); 1176 } 1177 1178 ixgbe_send_vf_success(sc, vf, msg[0]); 1179 } /* ixgbe_vf_set_lpe */ 1180 1181 1182 static void 1183 ixgbe_vf_set_macvlan(struct ixgbe_softc *sc, struct ixgbe_vf *vf, 1184 uint32_t *msg) 1185 { 1186 struct ixgbe_vf_mac_filter *filter, *free_filter; 1187 struct ixgbe_hw *hw; 1188 uint8_t *mac; 1189 int i, index; 1190 1191 hw = &sc->hw; 1192 index = IXGBE_VT_MSGINFO(msg[0]); 1193 if (index == 0) { 1194 ixgbe_vf_clear_mac_filters(sc, vf, true); 1195 ixgbe_vf_set_anti_spoof(sc, vf); 1196 ixgbe_send_vf_success(sc, vf, msg[0]); 1197 return; 1198 } 1199 if (!(vf->flags & IXGBE_VF_CAP_MAC)) 1200 goto failure; 1201 /* This hardware can anti-spoof only the VF's primary source MAC. */ 1202 if ((vf->flags & IXGBE_VF_ANTI_SPOOF) != 0) 1203 goto failure; 1204 1205 mac = (uint8_t *)&msg[1]; 1206 if (ixgbe_validate_mac_addr(mac) != IXGBE_SUCCESS) 1207 goto failure; 1208 if (index == 1) 1209 ixgbe_vf_clear_mac_filters(sc, vf, true); 1210 if (bcmp(mac, vf->ether_addr, ETHER_ADDR_LEN) == 0) { 1211 ixgbe_vf_set_anti_spoof(sc, vf); 1212 ixgbe_send_vf_success(sc, vf, msg[0]); 1213 return; 1214 } 1215 1216 free_filter = NULL; 1217 for (i = 0; i < sc->num_vf_mac_filters; i++) { 1218 filter = &sc->vf_mac_filters[i]; 1219 if (!filter->active) { 1220 if (free_filter == NULL) 1221 free_filter = filter; 1222 continue; 1223 } 1224 if (bcmp(filter->mac, mac, ETHER_ADDR_LEN) != 0) 1225 continue; 1226 if (filter->pool != vf->pool) 1227 goto failure; 1228 ixgbe_send_vf_success(sc, vf, msg[0]); 1229 return; 1230 } 1231 if (vf->num_mac_filters >= IXGBE_MAX_VF_MAC_FILTERS || 1232 free_filter == NULL) 1233 goto failure; 1234 1235 /* Reject collisions with PF, VF-primary, or other reserved RARs. */ 1236 if (ixgbe_rar_mac_in_use(sc, mac, -1)) 1237 goto failure; 1238 1239 if (ixgbe_set_rar(hw, free_filter->rar_index, mac, vf->pool, 1240 true) != IXGBE_SUCCESS) 1241 goto failure; 1242 free_filter->active = true; 1243 free_filter->pool = vf->pool; 1244 bcopy(mac, free_filter->mac, ETHER_ADDR_LEN); 1245 vf->num_mac_filters++; 1246 /* MAC anti-spoofing accepts only the primary address on this family. */ 1247 ixgbe_vf_set_anti_spoof(sc, vf); 1248 ixgbe_send_vf_success(sc, vf, msg[0]); 1249 return; 1250 1251 failure: 1252 ixgbe_vf_set_anti_spoof(sc, vf); 1253 ixgbe_send_vf_failure(sc, vf, msg[0]); 1254 } /* ixgbe_vf_set_macvlan */ 1255 1256 1257 static void 1258 ixgbe_vf_api_negotiate(struct ixgbe_softc *sc, struct ixgbe_vf *vf, 1259 uint32_t *msg) 1260 { 1261 if (msg[1] == IXGBE_API_VER_1_6) { 1262 if (sc->hw.mac.type != ixgbe_mac_E610) 1263 goto failure; 1264 vf->api_ver = msg[1]; 1265 ixgbe_send_vf_success(sc, vf, msg[0]); 1266 return; 1267 } 1268 1269 switch (msg[1]) { 1270 case IXGBE_API_VER_1_0: 1271 case IXGBE_API_VER_1_1: 1272 case IXGBE_API_VER_1_2: 1273 case IXGBE_API_VER_1_3: 1274 vf->api_ver = msg[1]; 1275 ixgbe_send_vf_success(sc, vf, msg[0]); 1276 break; 1277 default: 1278 goto failure; 1279 } 1280 return; 1281 1282 failure: 1283 vf->api_ver = IXGBE_API_VER_UNKNOWN; 1284 ixgbe_send_vf_failure(sc, vf, msg[0]); 1285 } /* ixgbe_vf_api_negotiate */ 1286 1287 static void 1288 ixgbe_vf_update_xcast_mode(struct ixgbe_softc *sc, struct ixgbe_vf *vf, 1289 uint32_t *msg) 1290 { 1291 struct ixgbe_hw *hw; 1292 uint32_t mode; 1293 1294 hw = &sc->hw; 1295 mode = msg[1]; 1296 switch (vf->api_ver) { 1297 case IXGBE_API_VER_1_2: 1298 if (mode == IXGBEVF_XCAST_MODE_PROMISC) 1299 goto failure; 1300 break; 1301 case IXGBE_API_VER_1_3: 1302 case IXGBE_API_VER_1_6: 1303 break; 1304 default: 1305 goto failure; 1306 } 1307 if (mode > IXGBEVF_XCAST_MODE_PROMISC) 1308 goto failure; 1309 if (mode > IXGBEVF_XCAST_MODE_MULTI && 1310 !(vf->flags & IXGBE_VF_ALLOW_PROMISC)) 1311 goto failure; 1312 if (mode == IXGBEVF_XCAST_MODE_PROMISC && 1313 (hw->mac.type <= ixgbe_mac_82599EB || 1314 !(IXGBE_READ_REG(hw, IXGBE_FCTRL) & IXGBE_FCTRL_UPE))) 1315 goto failure; 1316 1317 vf->xcast_mode = mode; 1318 ixgbe_vf_configure_vmolr(sc, vf); 1319 msg[0] &= IXGBE_VT_MSG_MASK; 1320 msg[0] |= IXGBE_VT_MSGTYPE_SUCCESS | IXGBE_VT_MSGTYPE_CTS; 1321 msg[1] = mode; 1322 ixgbe_write_mbx(hw, msg, 2, vf->pool); 1323 return; 1324 1325 failure: 1326 ixgbe_send_vf_failure(sc, vf, msg[0]); 1327 } /* ixgbe_vf_update_xcast_mode */ 1328 1329 1330 static void 1331 ixgbe_vf_get_queues(struct ixgbe_softc *sc, struct ixgbe_vf *vf, 1332 uint32_t *msg) 1333 { 1334 struct ixgbe_hw *hw; 1335 uint32_t resp[IXGBE_VF_GET_QUEUES_RESP_LEN]; 1336 int num_queues; 1337 1338 hw = &sc->hw; 1339 1340 /* GET_QUEUES is not supported on pre-1.1 APIs. */ 1341 switch (vf->api_ver) { 1342 case IXGBE_API_VER_1_0: 1343 case IXGBE_API_VER_UNKNOWN: 1344 ixgbe_send_vf_failure(sc, vf, msg[0]); 1345 return; 1346 } 1347 1348 resp[0] = IXGBE_VF_GET_QUEUES | IXGBE_VT_MSGTYPE_SUCCESS | 1349 IXGBE_VT_MSGTYPE_CTS; 1350 1351 num_queues = ixgbe_vf_queues(sc->iov_mode); 1352 resp[IXGBE_VF_TX_QUEUES] = num_queues; 1353 resp[IXGBE_VF_RX_QUEUES] = num_queues; 1354 resp[IXGBE_VF_TRANS_VLAN] = (vf->default_vlan != 0); 1355 resp[IXGBE_VF_DEF_QUEUE] = 0; 1356 1357 ixgbe_write_mbx(hw, resp, IXGBE_VF_GET_QUEUES_RESP_LEN, vf->pool); 1358 } /* ixgbe_vf_get_queues */ 1359 1360 static void 1361 ixgbe_vf_get_link_state(struct ixgbe_softc *sc, struct ixgbe_vf *vf, 1362 uint32_t *msg) 1363 { 1364 switch (vf->api_ver) { 1365 case IXGBE_API_VER_1_2: 1366 case IXGBE_API_VER_1_3: 1367 case IXGBE_API_VER_1_6: 1368 break; 1369 default: 1370 ixgbe_send_vf_failure(sc, vf, msg[0]); 1371 return; 1372 } 1373 1374 msg[0] = IXGBE_VF_GET_LINK_STATE | IXGBE_VT_MSGTYPE_SUCCESS | 1375 IXGBE_VT_MSGTYPE_CTS; 1376 msg[1] = 1; 1377 ixgbe_write_mbx(&sc->hw, msg, 2, vf->pool); 1378 } /* ixgbe_vf_get_link_state */ 1379 1380 static void 1381 ixgbe_vf_get_pf_link_state(struct ixgbe_softc *sc, struct ixgbe_vf *vf, 1382 uint32_t *msg) 1383 { 1384 if (sc->hw.mac.type != ixgbe_mac_E610 || 1385 vf->api_ver != IXGBE_API_VER_1_6) { 1386 ixgbe_send_vf_failure(sc, vf, msg[0]); 1387 return; 1388 } 1389 1390 msg[0] = IXGBE_VF_GET_PF_LINK_STATE | IXGBE_VT_MSGTYPE_SUCCESS | 1391 IXGBE_VT_MSGTYPE_CTS; 1392 msg[1] = sc->link_speed; 1393 msg[2] = sc->link_up; 1394 ixgbe_write_mbx(&sc->hw, msg, 3, vf->pool); 1395 } /* ixgbe_vf_get_pf_link_state */ 1396 1397 1398 static bool 1399 ixgbe_process_vf_msg(if_ctx_t ctx, struct ixgbe_vf *vf, bool reset_pending) 1400 { 1401 struct ixgbe_softc *sc = iflib_get_softc(ctx); 1402 #ifdef KTR 1403 if_t ifp = iflib_get_ifp(ctx); 1404 #endif 1405 struct ixgbe_hw *hw; 1406 uint32_t msg[IXGBE_VFMAILBOX_SIZE]; 1407 bool cleanup_complete; 1408 int error; 1409 1410 hw = &sc->hw; 1411 cleanup_complete = true; 1412 1413 error = ixgbe_read_mbx(hw, msg, IXGBE_VFMAILBOX_SIZE, vf->pool); 1414 1415 if (error != 0) 1416 return (false); 1417 /* 1418 * Some devices do not clear VFMBMEM on VFLR. Copy a pending request 1419 * first because the VF posts its mailbox reset request after raising 1420 * the reset event. 1421 */ 1422 if (reset_pending || msg[0] == IXGBE_VF_RESET) 1423 cleanup_complete = 1424 ixgbe_clear_mbx(hw, vf->pool) == IXGBE_SUCCESS; 1425 /* The successful read ACKed the request; dispatch it even if not clear. */ 1426 1427 CTR3(KTR_MALLOC, "%s: received msg %x from %d", if_name(ifp), 1428 msg[0], vf->pool); 1429 if (msg[0] == IXGBE_VF_RESET) { 1430 ixgbe_vf_reset_msg(sc, vf, msg); 1431 return (cleanup_complete); 1432 } 1433 /* Discard requests from the mailbox session invalidated by VFLR. */ 1434 if (reset_pending) 1435 return (cleanup_complete); 1436 1437 if (!(vf->flags & IXGBE_VF_CTS)) { 1438 ixgbe_send_vf_failure(sc, vf, msg[0]); 1439 return (true); 1440 } 1441 1442 switch (msg[0] & IXGBE_VT_MSG_MASK) { 1443 case IXGBE_VF_SET_MAC_ADDR: 1444 ixgbe_vf_set_mac(sc, vf, msg); 1445 break; 1446 case IXGBE_VF_SET_MULTICAST: 1447 ixgbe_vf_set_mc_addr(sc, vf, msg); 1448 break; 1449 case IXGBE_VF_SET_VLAN: 1450 ixgbe_vf_set_vlan(sc, vf, msg); 1451 break; 1452 case IXGBE_VF_SET_LPE: 1453 ixgbe_vf_set_lpe(sc, vf, msg); 1454 break; 1455 case IXGBE_VF_SET_MACVLAN: 1456 ixgbe_vf_set_macvlan(sc, vf, msg); 1457 break; 1458 case IXGBE_VF_API_NEGOTIATE: 1459 ixgbe_vf_api_negotiate(sc, vf, msg); 1460 break; 1461 case IXGBE_VF_GET_QUEUES: 1462 ixgbe_vf_get_queues(sc, vf, msg); 1463 break; 1464 case IXGBE_VF_UPDATE_XCAST_MODE: 1465 ixgbe_vf_update_xcast_mode(sc, vf, msg); 1466 break; 1467 case IXGBE_VF_GET_LINK_STATE: 1468 ixgbe_vf_get_link_state(sc, vf, msg); 1469 break; 1470 case IXGBE_VF_GET_PF_LINK_STATE: 1471 ixgbe_vf_get_pf_link_state(sc, vf, msg); 1472 break; 1473 default: 1474 ixgbe_send_vf_failure(sc, vf, msg[0]); 1475 } 1476 return (true); 1477 } /* ixgbe_process_vf_msg */ 1478 1479 static void 1480 ixgbe_cleanup_vf_mbx(struct ixgbe_softc *sc, struct ixgbe_vf *vf) 1481 { 1482 struct ixgbe_hw *hw; 1483 sbintime_t now; 1484 1485 hw = &sc->hw; 1486 if (ixgbe_clear_mbx(hw, vf->pool) == IXGBE_SUCCESS) { 1487 vf->flags &= ~IXGBE_VF_MBX_CLEANUP; 1488 return; 1489 } 1490 1491 now = getsbinuptime(); 1492 if (now < vf->mbx_cleanup_deadline) 1493 return; 1494 1495 /* 1496 * A functioning VF posts VFREQ within the grace interval. Ownership 1497 * still held after that interval is residue from the old reset epoch. 1498 * The force-clear helper rechecks VFREQ before asserting RVFU. 1499 */ 1500 if (ixgbe_force_clear_mbx_pf(hw, vf->pool) == IXGBE_SUCCESS) { 1501 vf->flags &= ~IXGBE_VF_MBX_CLEANUP; 1502 return; 1503 } 1504 1505 /* A request raced the force-clear attempt; give it another interval. */ 1506 vf->mbx_cleanup_deadline = now + IXGBE_VF_MBX_CLEANUP_GRACE; 1507 } 1508 1509 static void 1510 ixgbe_notify_vf_mdd_reset(struct ixgbe_softc *sc, struct ixgbe_vf *vf) 1511 { 1512 u32 msg; 1513 int error; 1514 1515 msg = IXGBE_PF_CONTROL_MSG | IXGBE_VT_MSGTYPE_FAILURE; 1516 error = ixgbe_write_mbx(&sc->hw, &msg, 1, vf->pool); 1517 if (error == IXGBE_SUCCESS) { 1518 vf->flags &= ~IXGBE_VF_MDD_NOTIFY_PENDING; 1519 return; 1520 } 1521 1522 /* The periodic admin pass retries after any mailbox collision. */ 1523 if (ratecheck(&vf->last_mdd_log, &ixgbe_mdd_log_interval)) 1524 device_printf(sc->dev, 1525 "could not notify VF %u of malicious-driver reset: %d; " 1526 "will retry\n", vf->pool, error); 1527 } 1528 1529 static void 1530 ixgbe_handle_mdd(struct ixgbe_softc *sc) 1531 { 1532 struct ixgbe_hw *hw; 1533 struct ixgbe_vf *vf; 1534 bool pf_reset; 1535 u32 rx_cause, tx_cause; 1536 u32 vf_bitmap[2] = {}; 1537 int pool; 1538 1539 hw = &sc->hw; 1540 ixgbe_mdd_event(hw, vf_bitmap); 1541 if (vf_bitmap[0] != 0 || vf_bitmap[1] != 0) { 1542 tx_cause = IXGBE_READ_REG(hw, IXGBE_LVMMC_TX); 1543 rx_cause = IXGBE_READ_REG(hw, IXGBE_LVMMC_RX); 1544 } else { 1545 tx_cause = 0; 1546 rx_cause = 0; 1547 } 1548 pf_reset = false; 1549 for (pool = 0; pool < 64; pool++) { 1550 if ((vf_bitmap[pool / 32] & (1U << (pool % 32))) == 0) 1551 continue; 1552 1553 if (pool == sc->pool) { 1554 if (sc->iov_pf_mdd_reset_pending) 1555 continue; 1556 sc->iov_pf_mdd_reset_pending = true; 1557 pf_reset = true; 1558 if (ratecheck(&sc->iov_last_mdd_log, 1559 &ixgbe_mdd_log_interval)) 1560 device_printf(sc->dev, 1561 "malicious-driver event on PF pool " 1562 "(last tx cause %#x, last rx cause %#x); " 1563 "resetting PF\n", 1564 tx_cause, rx_cause); 1565 continue; 1566 } 1567 if (pool >= sc->num_vfs) { 1568 ixgbe_restore_mdd_vf(hw, pool); 1569 continue; 1570 } 1571 vf = &sc->vfs[pool]; 1572 if (!(vf->flags & IXGBE_VF_ACTIVE)) { 1573 ixgbe_restore_mdd_vf(hw, pool); 1574 continue; 1575 } 1576 1577 if ((vf->flags & IXGBE_VF_MDD_BLOCKED) != 0) 1578 continue; 1579 if (ratecheck(&vf->last_mdd_log, &ixgbe_mdd_log_interval)) 1580 device_printf(sc->dev, 1581 "malicious-driver event from VF %u " 1582 "(last tx cause %#x, last rx cause %#x); " 1583 "requesting VF reset\n", 1584 vf->pool, tx_cause, rx_cause); 1585 1586 /* 1587 * Keep both the pool gate and the per-queue WQBR block asserted. 1588 * PFVFTE stops packet-data fetches but can still allow descriptor 1589 * fetches into the internal queue, so releasing WQBR here would 1590 * leave a hostile VF able to retrigger MDD before it resets. 1591 * ixgbe_process_vf_reset() releases WQBR in the new reset epoch. 1592 */ 1593 vf->flags |= IXGBE_VF_MDD_BLOCKED; 1594 vf->flags &= ~IXGBE_VF_CTS; 1595 ixgbe_vf_enable_transmit(sc, vf); 1596 ixgbe_vf_enable_receive(sc, vf); 1597 IXGBE_WRITE_FLUSH(hw); 1598 vf->flags |= IXGBE_VF_MDD_NOTIFY_PENDING; 1599 } 1600 1601 if (pf_reset) { 1602 iflib_request_reset(sc->ctx); 1603 iflib_admin_intr_deferred(sc->ctx); 1604 } 1605 } 1606 1607 /* Tasklet for handling VF -> PF mailbox messages */ 1608 void 1609 ixgbe_handle_mbx(void *context) 1610 { 1611 if_ctx_t ctx = context; 1612 struct ixgbe_softc *sc = iflib_get_softc(ctx); 1613 struct ixgbe_hw *hw; 1614 struct ixgbe_vf *vf; 1615 bool cleanup_pending, mbx_activity, recovering, reset_pending; 1616 bool reset_seen; 1617 int i; 1618 1619 hw = &sc->hw; 1620 cleanup_pending = false; 1621 ixgbe_handle_mdd(sc); 1622 1623 for (i = 0; i < sc->num_vfs; i++) { 1624 vf = &sc->vfs[i]; 1625 mbx_activity = false; 1626 reset_seen = hw->mbx.ops[i].check_for_rst(hw, i) == 0; 1627 1628 if (!(vf->flags & IXGBE_VF_ACTIVE)) { 1629 if (hw->mbx.ops[i].check_for_msg(hw, i) == 0 || 1630 reset_seen) 1631 ixgbe_clear_mbx(hw, i); 1632 (void)hw->mbx.ops[i].check_for_ack(hw, i); 1633 continue; 1634 } 1635 1636 if (reset_seen) { 1637 /* A reset does not prove recovery succeeded. */ 1638 recovering = (vf->flags & 1639 IXGBE_VF_DMA_ABORT_PENDING) != 0; 1640 vf->flags |= IXGBE_VF_MBX_CLEANUP; 1641 vf->mbx_cleanup_deadline = getsbinuptime() + 1642 IXGBE_VF_MBX_CLEANUP_GRACE; 1643 ixgbe_process_vf_reset(sc, vf); 1644 if (!recovering) { 1645 vf->flags &= ~(IXGBE_VF_DMA_ABORT_PENDING | 1646 IXGBE_VF_PCI_STATE_SAVED); 1647 vf->pci_saved_command = 0; 1648 } 1649 } 1650 reset_pending = (vf->flags & IXGBE_VF_MBX_CLEANUP) != 0; 1651 1652 if (hw->mbx.ops[vf->pool].check_for_msg(hw, 1653 vf->pool) == 0) { 1654 mbx_activity = true; 1655 if (ixgbe_process_vf_msg(ctx, vf, reset_pending)) 1656 vf->flags &= ~IXGBE_VF_MBX_CLEANUP; 1657 } 1658 if (reset_pending && 1659 (vf->flags & IXGBE_VF_MBX_CLEANUP) != 0) 1660 ixgbe_cleanup_vf_mbx(sc, vf); 1661 1662 if (hw->mbx.ops[vf->pool].check_for_ack(hw, vf->pool) == 0) { 1663 mbx_activity = true; 1664 ixgbe_process_vf_ack(sc, vf); 1665 } 1666 1667 /* Do not overwrite a response produced by this mailbox pass. */ 1668 if (!mbx_activity && 1669 (vf->flags & IXGBE_VF_MDD_NOTIFY_PENDING) != 0) 1670 ixgbe_notify_vf_mdd_reset(sc, vf); 1671 1672 if (vf->flags & IXGBE_VF_MBX_CLEANUP) 1673 cleanup_pending = true; 1674 } 1675 sc->iov_mbx_cleanup_pending = cleanup_pending; 1676 } /* ixgbe_handle_mbx */ 1677 1678 /* 1679 * VFREQ, VFACK, a bare VFLR, and WQBR can remain latched without a usable 1680 * shared mailbox interrupt across a PF stop/restart or an MDD mask interval. 1681 * Sample their aggregate registers from the periodic admin pass so work does 1682 * not depend on another edge. Pending asynchronous MDD notifications use the 1683 * same pass to retry after the VF wins a mailbox collision. 1684 */ 1685 bool 1686 ixgbe_mbx_pending(struct ixgbe_softc *sc) 1687 { 1688 struct ixgbe_hw *hw; 1689 uint32_t events, vf_mbx[4], vf_mdd[2], vf_rst[2]; 1690 int i, index; 1691 1692 if (sc->num_vfs == 0) 1693 return (false); 1694 1695 bzero(vf_mbx, sizeof(vf_mbx)); 1696 bzero(vf_mdd, sizeof(vf_mdd)); 1697 bzero(vf_rst, sizeof(vf_rst)); 1698 for (i = 0; i < sc->num_vfs; i++) { 1699 if ((sc->vfs[i].flags & IXGBE_VF_MDD_NOTIFY_PENDING) != 0) 1700 return (true); 1701 index = IXGBE_PFMBICR_INDEX(i); 1702 vf_mbx[index] |= 1703 IXGBE_PFMBICR_VFREQ_VF1 << 1704 IXGBE_PFMBICR_SHIFT(i); 1705 vf_mbx[index] |= 1706 IXGBE_PFMBICR_VFACK_VF1 << 1707 IXGBE_PFMBICR_SHIFT(i); 1708 index = IXGBE_PFVFLRE_INDEX(i); 1709 vf_rst[index] |= 1U << IXGBE_PFVFLRE_SHIFT(i); 1710 } 1711 1712 hw = &sc->hw; 1713 for (index = 0; index < nitems(vf_mbx); index++) { 1714 if (vf_mbx[index] != 0 && 1715 (IXGBE_READ_REG(hw, IXGBE_PFMBICR(index)) & 1716 vf_mbx[index]) != 0) 1717 return (true); 1718 } 1719 for (index = 0; index < nitems(vf_rst); index++) { 1720 if (vf_rst[index] == 0) 1721 continue; 1722 switch (hw->mac.type) { 1723 case ixgbe_mac_82599EB: 1724 events = IXGBE_READ_REG(hw, IXGBE_PFVFLRE(index)); 1725 break; 1726 case ixgbe_mac_X540: 1727 case ixgbe_mac_X550: 1728 case ixgbe_mac_X550EM_x: 1729 case ixgbe_mac_X550EM_a: 1730 case ixgbe_mac_E610: 1731 events = IXGBE_READ_REG(hw, IXGBE_PFVFLREC(index)); 1732 break; 1733 default: 1734 return (false); 1735 } 1736 if ((events & vf_rst[index]) != 0) 1737 return (true); 1738 } 1739 ixgbe_mdd_event(hw, vf_mdd); 1740 /* A fenced VF retains WQBR until reset; do not reschedule for it. */ 1741 for (i = 0; i < sc->num_vfs; i++) { 1742 if ((sc->vfs[i].flags & IXGBE_VF_MDD_BLOCKED) != 0) 1743 vf_mdd[i / 32] &= ~(1U << (i % 32)); 1744 } 1745 if (sc->iov_pf_mdd_reset_pending) 1746 vf_mdd[sc->pool / 32] &= ~(1U << (sc->pool % 32)); 1747 if (vf_mdd[0] != 0 || vf_mdd[1] != 0) 1748 return (true); 1749 return (false); 1750 } 1751 1752 static const char * 1753 ixgbe_vf_api_version(uint16_t api_ver) 1754 { 1755 switch (api_ver) { 1756 case ixgbe_mbox_api_10: 1757 return ("1.0"); 1758 case ixgbe_mbox_api_11: 1759 return ("1.1"); 1760 case ixgbe_mbox_api_12: 1761 return ("1.2"); 1762 case ixgbe_mbox_api_13: 1763 return ("1.3"); 1764 case ixgbe_mbox_api_14: 1765 return ("1.4"); 1766 case ixgbe_mbox_api_15: 1767 return ("1.5"); 1768 case ixgbe_mbox_api_16: 1769 return ("1.6"); 1770 case ixgbe_mbox_api_20: 1771 return ("2.0"); 1772 default: 1773 return (NULL); 1774 } 1775 } 1776 1777 int 1778 ixgbe_if_vf_status(if_ctx_t ctx, struct if_vf_status **statusp) 1779 { 1780 struct ixgbe_softc *sc; 1781 struct ixgbe_vf *vf; 1782 struct if_vf_info *info; 1783 struct if_vf_status *status; 1784 const char *api_ver; 1785 int i; 1786 1787 sc = iflib_get_softc(ctx); 1788 if (!sc->iov_attached) 1789 return (EOPNOTSUPP); 1790 status = if_vf_status_alloc(sc->num_vfs); 1791 if (status == NULL) 1792 return (ENOMEM); 1793 for (i = 0; i < sc->num_vfs; i++) { 1794 vf = &sc->vfs[i]; 1795 info = &status->vfs[i]; 1796 info->fields = IFVF_F_CONFIGURED | IFVF_F_INITIALIZED | 1797 IFVF_F_VLAN_MODE | IFVF_F_VLAN_COUNT | 1798 IFVF_F_NUM_TX_QUEUES | IFVF_F_NUM_RX_QUEUES | 1799 IFVF_F_ALLOW_SET_MAC | 1800 IFVF_F_ALLOW_SET_VLAN | IFVF_F_MAC_ANTI_SPOOF | 1801 IFVF_F_ALLOW_PROMISC | IFVF_F_TRAFFIC_ALLOWED | 1802 IFVF_F_FAULT_BLOCKED | IFVF_F_QUARANTINED; 1803 info->index = i; 1804 info->configured = (vf->flags & IXGBE_VF_ACTIVE) != 0; 1805 info->initialized = 1806 (vf->flags & (IXGBE_VF_CTS | IXGBE_VF_INIT_DONE)) == 1807 (IXGBE_VF_CTS | IXGBE_VF_INIT_DONE); 1808 if (!ETHER_IS_ZERO(vf->ether_addr)) { 1809 memcpy(info->mac, vf->ether_addr, sizeof(info->mac)); 1810 info->fields |= IFVF_F_MAC; 1811 } 1812 if (vf->default_vlan == 0) 1813 info->vlan_mode = IFVF_VLAN_TRUNK; 1814 else { 1815 info->vlan_mode = IFVF_VLAN_ACCESS; 1816 info->vlan = vf->default_vlan; 1817 info->vlan_pcp = 0; 1818 info->vlan_proto = ETHERTYPE_VLAN; 1819 info->fields |= IFVF_F_VLAN | IFVF_F_VLAN_PCP | 1820 IFVF_F_VLAN_PROTO; 1821 } 1822 info->vlan_count = vf->num_vlans; 1823 info->tx_queue_count = ixgbe_vf_queues(sc->iov_mode); 1824 info->rx_queue_count = ixgbe_vf_queues(sc->iov_mode); 1825 info->allow_set_mac = (vf->flags & IXGBE_VF_CAP_MAC) != 0; 1826 info->allow_set_vlan = (vf->flags & IXGBE_VF_CAP_VLAN) != 0; 1827 info->mac_anti_spoof = 1828 (vf->flags & IXGBE_VF_ANTI_SPOOF) != 0; 1829 info->allow_promisc = 1830 (vf->flags & IXGBE_VF_ALLOW_PROMISC) != 0; 1831 info->traffic_allowed = info->configured && 1832 (vf->flags & IXGBE_VF_TRAFFIC_DISABLED) == 0; 1833 info->fault_blocked = 1834 (vf->flags & IXGBE_VF_TRAFFIC_DISABLED) != 0; 1835 info->quarantined = (vf->flags & IXGBE_VF_QUARANTINED) != 0; 1836 api_ver = ixgbe_vf_api_version(vf->api_ver); 1837 if (api_ver != NULL) { 1838 strlcpy(info->api_version, api_ver, 1839 sizeof(info->api_version)); 1840 info->fields |= IFVF_F_API_VERSION; 1841 } 1842 } 1843 *statusp = status; 1844 return (0); 1845 } 1846 1847 int 1848 ixgbe_iov_validate(struct ixgbe_softc *sc, u16 num_vfs) 1849 { 1850 int mode, pool, queue_count; 1851 1852 if (!(sc->feat_cap & IXGBE_FEATURE_SRIOV)) 1853 return (ENXIO); 1854 if (num_vfs == 0) 1855 return (EINVAL); 1856 if (sc->vfs != NULL || sc->vf_mac_filters != NULL || 1857 (sc->feat_en & IXGBE_FEATURE_SRIOV)) 1858 return (EBUSY); 1859 if (sc->feat_en & IXGBE_FEATURE_FDIR) { 1860 device_printf(sc->dev, 1861 "Flow Director is not supported with SR-IOV\n"); 1862 return (ENOTSUP); 1863 } 1864 if (sc->intr_type != IFLIB_INTR_MSIX) { 1865 device_printf(sc->dev, "SR-IOV requires MSI-X\n"); 1866 return (ENOTSUP); 1867 } 1868 1869 /* 1870 * We've got to reserve a VM's worth of queues for the PF, 1871 * thus we go into "64 VF mode" if 32+ VFs are requested. 1872 * With 64 VFs, you can only have two queues per VF. 1873 * With 32 VFs, you can have up to four queues per VF. 1874 */ 1875 if (num_vfs >= IXGBE_32_VM) 1876 mode = IXGBE_64_VM; 1877 else 1878 mode = IXGBE_32_VM; 1879 queue_count = ixgbe_vf_queues(mode); 1880 if (sc->num_rx_queues > queue_count || 1881 sc->num_tx_queues > queue_count) { 1882 device_printf(sc->dev, 1883 "SR-IOV mode supports %d PF queues, but %d RX and %d TX " 1884 "queues are allocated\n", queue_count, sc->num_rx_queues, 1885 sc->num_tx_queues); 1886 return (ENOSPC); 1887 } 1888 1889 /* Again, reserving 1 VM's worth of queues for the PF */ 1890 pool = mode - 1; 1891 if (num_vfs > pool || num_vfs >= IXGBE_64_VM) 1892 return (ENOSPC); 1893 return (0); 1894 } 1895 1896 int 1897 ixgbe_if_iov_init(if_ctx_t ctx, u16 num_vfs, const nvlist_t *config) 1898 { 1899 struct ixgbe_softc *sc; 1900 int i, num_filters, retval; 1901 1902 (void)config; 1903 sc = iflib_get_softc(ctx); 1904 retval = ixgbe_iov_validate(sc, num_vfs); 1905 if (retval != 0) 1906 return (retval); 1907 1908 if (num_vfs >= IXGBE_32_VM) 1909 sc->iov_mode = IXGBE_64_VM; 1910 else 1911 sc->iov_mode = IXGBE_32_VM; 1912 sc->pool = sc->iov_mode - 1; 1913 1914 sc->vfs = malloc(sizeof(*sc->vfs) * num_vfs, M_IXGBE_SRIOV, 1915 M_NOWAIT | M_ZERO); 1916 1917 if (sc->vfs == NULL) { 1918 retval = ENOMEM; 1919 goto err_init_iov; 1920 } 1921 for (i = 0; i < num_vfs; i++) 1922 sc->vfs[i].api_ver = IXGBE_API_VER_UNKNOWN; 1923 num_filters = sc->hw.mac.num_rar_entries - num_vfs - 1 - 1924 IXGBE_MAX_PF_MAC_FILTERS; 1925 if (num_filters > 0) { 1926 sc->vf_mac_filters = mallocarray(num_filters, 1927 sizeof(*sc->vf_mac_filters), M_IXGBE_SRIOV, 1928 M_NOWAIT | M_ZERO); 1929 if (sc->vf_mac_filters != NULL) { 1930 sc->num_vf_mac_filters = num_filters; 1931 for (i = 0; i < num_filters; i++) 1932 sc->vf_mac_filters[i].rar_index = 1933 IXGBE_MAX_PF_MAC_FILTERS + 1 + i; 1934 } else 1935 device_printf(sc->dev, 1936 "could not allocate VF secondary MAC filters; " 1937 "SET_MACVLAN will be unavailable\n"); 1938 } 1939 1940 sc->num_vfs = num_vfs; 1941 sc->iov_mbx_cleanup_pending = false; 1942 sc->iov_pf_mdd_reset_pending = false; 1943 sc->iov_recovery_time = 0; 1944 sc->iov_recovery_cursor = 0; 1945 sc->iov_quarantined_vfs = 0; 1946 ixgbe_init_mbx_params_pf(&sc->hw); 1947 1948 sc->feat_en |= IXGBE_FEATURE_SRIOV; 1949 1950 return (retval); 1951 1952 err_init_iov: 1953 free(sc->vf_mac_filters, M_IXGBE_SRIOV); 1954 sc->vf_mac_filters = NULL; 1955 sc->num_vf_mac_filters = 0; 1956 free(sc->vfs, M_IXGBE_SRIOV); 1957 sc->vfs = NULL; 1958 sc->num_vfs = 0; 1959 sc->pool = 0; 1960 sc->iov_mode = IXGBE_NO_VM; 1961 sc->iov_mbx_cleanup_pending = false; 1962 sc->iov_pf_mdd_reset_pending = false; 1963 sc->iov_quarantined_vfs = 0; 1964 1965 return (retval); 1966 } /* ixgbe_if_iov_init */ 1967 1968 void 1969 ixgbe_if_iov_uninit(if_ctx_t ctx) 1970 { 1971 struct ixgbe_hw *hw; 1972 struct ixgbe_softc *sc; 1973 uint32_t pf_reg, vf_reg; 1974 int error, i, iov_pos; 1975 u16 iov_ctl; 1976 1977 sc = iflib_get_softc(ctx); 1978 hw = &sc->hw; 1979 ixgbe_disable_mdd(hw); 1980 1981 /* Enable rx/tx for the PF and disable it for all VFs. */ 1982 pf_reg = IXGBE_VF_INDEX(sc->pool); 1983 IXGBE_WRITE_REG(hw, IXGBE_VFRE(pf_reg), IXGBE_VF_BIT(sc->pool)); 1984 IXGBE_WRITE_REG(hw, IXGBE_VFTE(pf_reg), IXGBE_VF_BIT(sc->pool)); 1985 1986 if (pf_reg == 0) 1987 vf_reg = 1; 1988 else 1989 vf_reg = 0; 1990 IXGBE_WRITE_REG(hw, IXGBE_VFRE(vf_reg), 0); 1991 IXGBE_WRITE_REG(hw, IXGBE_VFTE(vf_reg), 0); 1992 IXGBE_WRITE_FLUSH(hw); 1993 1994 /* 1995 * pci_iov(4) normally clears VF Enable after this callback returns, 1996 * but iflib's restart transaction reuses the PF queues first. Disable 1997 * the VFs here and allow outstanding transactions to drain before the 1998 * queue layout changes. 1999 */ 2000 error = pci_find_extcap(sc->dev, PCIZ_SRIOV, &iov_pos); 2001 if (error == 0) { 2002 iov_ctl = pci_read_config(sc->dev, 2003 iov_pos + PCIR_SRIOV_CTL, 2); 2004 iov_ctl &= ~(PCIM_SRIOV_VF_EN | PCIM_SRIOV_VF_MSE); 2005 pci_write_config(sc->dev, iov_pos + PCIR_SRIOV_CTL, 2006 iov_ctl, 2); 2007 pause("ixiov", MAX(1, howmany(hz, 10))); 2008 } else 2009 device_printf(sc->dev, 2010 "could not disable PCI SR-IOV before queue reuse: %d\n", 2011 error); 2012 2013 for (i = 0; i < sc->num_vfs; i++) { 2014 if (!(sc->vfs[i].flags & IXGBE_VF_ACTIVE)) 2015 continue; 2016 ixgbe_vf_set_rx_drop(sc, &sc->vfs[i], false); 2017 ixgbe_vf_clear_mac_filters(sc, &sc->vfs[i], true); 2018 sc->vfs[i].flags &= ~IXGBE_VF_ANTI_SPOOF; 2019 ixgbe_vf_set_anti_spoof(sc, &sc->vfs[i]); 2020 } 2021 if (hw->mac.ops.set_ethertype_anti_spoofing != NULL) { 2022 IXGBE_WRITE_REG(hw, IXGBE_ETQF(IXGBE_ETQF_FILTER_LLDP), 0); 2023 IXGBE_WRITE_REG(hw, IXGBE_ETQF(IXGBE_ETQF_FILTER_FC), 0); 2024 } 2025 2026 IXGBE_WRITE_REG(hw, IXGBE_VT_CTL, 0); 2027 2028 sc->num_vfs = 0; 2029 ixgbe_iov_rebuild_mta(sc); 2030 free(sc->vf_mac_filters, M_IXGBE_SRIOV); 2031 sc->vf_mac_filters = NULL; 2032 sc->num_vf_mac_filters = 0; 2033 free(sc->vfs, M_IXGBE_SRIOV); 2034 sc->vfs = NULL; 2035 sc->feat_en &= ~IXGBE_FEATURE_SRIOV; 2036 sc->iov_quarantined_vfs = 0; 2037 sc->pool = 0; 2038 sc->iov_mode = IXGBE_NO_VM; 2039 ixgbe_align_all_queue_indices(sc); 2040 sc->iov_vfta_valid = false; 2041 sc->iov_vlan_promisc = false; 2042 sc->iov_mbx_cleanup_pending = false; 2043 sc->iov_pf_mdd_reset_pending = false; 2044 (void)ixgbe_clear_vfta(hw); 2045 ixgbe_setup_vlan_hw_support(ctx); 2046 } /* ixgbe_if_iov_uninit */ 2047 2048 static s32 2049 ixgbe_init_vf(struct ixgbe_softc *sc, struct ixgbe_vf *vf) 2050 { 2051 struct ixgbe_hw *hw; 2052 uint32_t vf_index, pfmbimr; 2053 s32 error; 2054 2055 hw = &sc->hw; 2056 /* Preserve quarantine until the SR-IOV configuration is destroyed. */ 2057 vf->flags &= ~(IXGBE_VF_INIT_DONE | IXGBE_VF_DMA_ABORT_PENDING | 2058 IXGBE_VF_PCI_STATE_SAVED | IXGBE_VF_MDD_BLOCKED | 2059 IXGBE_VF_MDD_NOTIFY_PENDING); 2060 vf->pci_saved_command = 0; 2061 vf->recovery_tx_pending = 0; 2062 2063 if (!(vf->flags & IXGBE_VF_ACTIVE)) 2064 return (IXGBE_SUCCESS); 2065 if (vf->flags & IXGBE_VF_QUARANTINED) { 2066 vf->flags &= ~IXGBE_VF_CTS; 2067 return (IXGBE_SUCCESS); 2068 } 2069 2070 vf_index = IXGBE_VF_INDEX(vf->pool); 2071 pfmbimr = IXGBE_READ_REG(hw, IXGBE_PFMBIMR(vf_index)); 2072 pfmbimr |= IXGBE_VF_BIT(vf->pool); 2073 IXGBE_WRITE_REG(hw, IXGBE_PFMBIMR(vf_index), pfmbimr); 2074 2075 vf->xcast_mode = IXGBEVF_XCAST_MODE_NONE; 2076 vf->api_ver = IXGBE_API_VER_UNKNOWN; 2077 vf->num_mc_hashes = 0; 2078 bzero(vf->mc_hash, sizeof(vf->mc_hash)); 2079 ixgbe_vf_clear_mac_filters(sc, vf, false); 2080 error = ixgbe_vf_reset_vlan(sc, vf, false); 2081 if (error != IXGBE_SUCCESS) 2082 return (error); 2083 2084 if (ixgbe_validate_mac_addr(vf->ether_addr) == 0) { 2085 ixgbe_set_rar(&sc->hw, vf->rar_index, 2086 vf->ether_addr, vf->pool, true); 2087 } 2088 ixgbe_vf_set_anti_spoof(sc, vf); 2089 2090 vf->flags |= IXGBE_VF_INIT_DONE; 2091 return (IXGBE_SUCCESS); 2092 } /* ixgbe_init_vf */ 2093 2094 static void 2095 ixgbe_activate_vf(struct ixgbe_softc *sc, struct ixgbe_vf *vf) 2096 { 2097 if ((vf->flags & (IXGBE_VF_ACTIVE | IXGBE_VF_INIT_DONE)) != 2098 (IXGBE_VF_ACTIVE | IXGBE_VF_INIT_DONE) || 2099 (vf->flags & IXGBE_VF_TRAFFIC_DISABLED)) 2100 return; 2101 2102 ixgbe_vf_enable_transmit(sc, vf); 2103 ixgbe_vf_enable_receive(sc, vf); 2104 ixgbe_send_vf_msg(&sc->hw, vf, IXGBE_PF_CONTROL_MSG); 2105 } /* ixgbe_activate_vf */ 2106 2107 void 2108 ixgbe_initialize_iov(struct ixgbe_softc *sc) 2109 { 2110 struct ixgbe_hw *hw = &sc->hw; 2111 uint32_t mrqc, mtqc, vt_ctl, vf_reg, gcr_ext, gpie; 2112 int i; 2113 2114 if (sc->iov_mode == IXGBE_NO_VM) 2115 return; 2116 sc->iov_pf_mdd_reset_pending = false; 2117 2118 /* RMW appropriate registers based on IOV mode */ 2119 /* Read... */ 2120 mrqc = IXGBE_READ_REG(hw, IXGBE_MRQC); 2121 gcr_ext = IXGBE_READ_REG(hw, IXGBE_GCR_EXT); 2122 gpie = IXGBE_READ_REG(hw, IXGBE_GPIE); 2123 /* Modify... */ 2124 mrqc &= ~IXGBE_MRQC_MRQE_MASK; 2125 mtqc = IXGBE_MTQC_VT_ENA; /* No initial MTQC read needed */ 2126 gcr_ext |= IXGBE_GCR_EXT_MSIX_EN; 2127 gcr_ext &= ~IXGBE_GCR_EXT_VT_MODE_MASK; 2128 gpie &= ~IXGBE_GPIE_VTMODE_MASK; 2129 switch (sc->iov_mode) { 2130 case IXGBE_64_VM: 2131 mrqc |= IXGBE_MRQC_VMDQRSS64EN; 2132 mtqc |= IXGBE_MTQC_64VF; 2133 gcr_ext |= IXGBE_GCR_EXT_VT_MODE_64; 2134 gpie |= IXGBE_GPIE_VTMODE_64; 2135 break; 2136 case IXGBE_32_VM: 2137 mrqc |= IXGBE_MRQC_VMDQRSS32EN; 2138 mtqc |= IXGBE_MTQC_32VF; 2139 gcr_ext |= IXGBE_GCR_EXT_VT_MODE_32; 2140 gpie |= IXGBE_GPIE_VTMODE_32; 2141 break; 2142 default: 2143 panic("Unexpected SR-IOV mode %d", sc->iov_mode); 2144 } 2145 /* Write... */ 2146 IXGBE_WRITE_REG(hw, IXGBE_MRQC, mrqc); 2147 IXGBE_WRITE_REG(hw, IXGBE_MTQC, mtqc); 2148 IXGBE_WRITE_REG(hw, IXGBE_GCR_EXT, gcr_ext); 2149 IXGBE_WRITE_REG(hw, IXGBE_GPIE, gpie); 2150 2151 /* Enable rx/tx for the PF. */ 2152 vf_reg = IXGBE_VF_INDEX(sc->pool); 2153 IXGBE_WRITE_REG(hw, IXGBE_VFRE(vf_reg), IXGBE_VF_BIT(sc->pool)); 2154 IXGBE_WRITE_REG(hw, IXGBE_VFTE(vf_reg), IXGBE_VF_BIT(sc->pool)); 2155 2156 /* Allow VM-to-VM communication. */ 2157 IXGBE_WRITE_REG(hw, IXGBE_PFDTXGSWC, IXGBE_PFDTXGSWC_VT_LBEN); 2158 2159 vt_ctl = IXGBE_VT_CTL_VT_ENABLE | IXGBE_VT_CTL_REPLEN; 2160 vt_ctl |= (sc->pool << IXGBE_VT_CTL_POOL_SHIFT); 2161 IXGBE_WRITE_REG(hw, IXGBE_VT_CTL, vt_ctl); 2162 2163 for (i = 0; i < sc->num_vfs; i++) { 2164 if (ixgbe_init_vf(sc, &sc->vfs[i]) != IXGBE_SUCCESS) 2165 device_printf(sc->dev, 2166 "VF %d default VLAN restore failed\n", i); 2167 } 2168 } /* ixgbe_initialize_iov */ 2169 2170 void 2171 ixgbe_activate_vfs(struct ixgbe_softc *sc) 2172 { 2173 int i; 2174 2175 for (i = 0; i < sc->num_vfs; i++) 2176 ixgbe_activate_vf(sc, &sc->vfs[i]); 2177 } /* ixgbe_activate_vfs */ 2178 2179 2180 /* Recompute the maximum frame setting of the PF and all active VFs. */ 2181 void 2182 ixgbe_recalculate_max_frame(struct ixgbe_softc *sc) 2183 { 2184 struct ixgbe_vf *vf; 2185 2186 sc->max_frame_size = if_getmtu(iflib_get_ifp(sc->ctx)) + IXGBE_MTU_HDR; 2187 for (int i = 0; i < sc->num_vfs; i++) { 2188 vf = &sc->vfs[i]; 2189 if (vf->flags & IXGBE_VF_ACTIVE) 2190 ixgbe_update_max_frame(sc, vf->maximum_frame_size); 2191 } 2192 } /* ixgbe_recalculate_max_frame */ 2193 2194 int 2195 ixgbe_if_iov_vf_add(if_ctx_t ctx, u16 vfnum, const nvlist_t *config) 2196 { 2197 struct ixgbe_softc *sc; 2198 struct ixgbe_vf *vf; 2199 const void *mac; 2200 uint8_t mac_addr[ETHER_ADDR_LEN]; 2201 uint64_t configured_vlan; 2202 uint16_t vlan; 2203 s32 error; 2204 2205 sc = iflib_get_softc(ctx); 2206 2207 KASSERT(vfnum < sc->num_vfs, ("VF index %d is out of range %d", 2208 vfnum, sc->num_vfs)); 2209 2210 vf = &sc->vfs[vfnum]; 2211 if (vf->flags & IXGBE_VF_ACTIVE) 2212 return (EBUSY); 2213 bzero(vf, sizeof(*vf)); 2214 2215 configured_vlan = nvlist_get_number(config, "vlan"); 2216 if (configured_vlan > VF_VLAN_TRUNK) 2217 return (EINVAL); 2218 vlan = configured_vlan; 2219 if (vlan == 0) 2220 return (ENOTSUP); 2221 if (vlan == VF_VLAN_TRUNK) 2222 vlan = 0; 2223 2224 vf->pool = vfnum; 2225 2226 /* Allocate VF-primary RARs from the top, away from PF filters. */ 2227 vf->rar_index = sc->hw.mac.num_rar_entries - (vfnum + 1); 2228 vf->default_vlan = vlan; 2229 vf->maximum_frame_size = ETHER_MAX_LEN; 2230 ixgbe_update_max_frame(sc, vf->maximum_frame_size); 2231 if (nvlist_get_bool(config, "mac-anti-spoof")) 2232 vf->flags |= IXGBE_VF_ANTI_SPOOF; 2233 if (nvlist_get_bool(config, "allow-promisc")) 2234 vf->flags |= IXGBE_VF_ALLOW_PROMISC; 2235 2236 if (nvlist_exists_binary(config, "mac-addr")) { 2237 mac = nvlist_get_binary(config, "mac-addr", NULL); 2238 bcopy(mac, mac_addr, sizeof(mac_addr)); 2239 if (ixgbe_validate_mac_addr(mac_addr) != IXGBE_SUCCESS) 2240 return (EINVAL); 2241 if (ixgbe_rar_mac_in_use(sc, mac_addr, vf->rar_index)) 2242 return (EADDRINUSE); 2243 bcopy(mac_addr, vf->ether_addr, ETHER_ADDR_LEN); 2244 if (nvlist_get_bool(config, "allow-set-mac")) 2245 vf->flags |= IXGBE_VF_CAP_MAC; 2246 } else 2247 /* 2248 * If the administrator has not specified a MAC address then 2249 * we must allow the VF to choose one. 2250 */ 2251 vf->flags |= IXGBE_VF_CAP_MAC; 2252 if (vf->default_vlan == 0) 2253 vf->flags |= IXGBE_VF_CAP_VLAN; 2254 2255 vf->flags |= IXGBE_VF_ACTIVE; 2256 2257 error = ixgbe_init_vf(sc, vf); 2258 if (error != IXGBE_SUCCESS) { 2259 vf->flags &= ~IXGBE_VF_ACTIVE; 2260 vf->default_vlan = 0; 2261 ixgbe_vf_clear_vlans(sc, vf, true); 2262 return (ENOSPC); 2263 } 2264 ixgbe_activate_vf(sc, vf); 2265 2266 return (0); 2267 } /* ixgbe_if_iov_vf_add */ 2268 2269 #else 2270 2271 void 2272 ixgbe_handle_mbx(void *context) 2273 { 2274 UNREFERENCED_PARAMETER(context); 2275 } /* ixgbe_handle_mbx */ 2276 2277 bool 2278 ixgbe_mbx_pending(struct ixgbe_softc *sc) 2279 { 2280 UNREFERENCED_PARAMETER(sc); 2281 return (false); 2282 } 2283 2284 #endif 2285