1 /***************************************************************************** 2 3 Copyright (c) 2001-2017, Intel Corporation 4 All rights reserved. 5 6 Redistribution and use in source and binary forms, with or without 7 modification, are permitted provided that the following conditions are met: 8 9 1. Redistributions of source code must retain the above copyright notice, 10 this list of conditions and the following disclaimer. 11 12 2. Redistributions in binary form must reproduce the above copyright 13 notice, this list of conditions and the following disclaimer in the 14 documentation and/or other materials provided with the distribution. 15 16 3. Neither the name of the Intel Corporation nor the names of its 17 contributors may be used to endorse or promote products derived from 18 this software without specific prior written permission. 19 20 THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 21 AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 22 IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 23 ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE 24 LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 25 CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 26 SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 27 INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 28 CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 29 ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 30 POSSIBILITY OF SUCH DAMAGE. 31 32 *****************************************************************************/ 33 34 #include "opt_inet.h" 35 #include "opt_inet6.h" 36 #include "opt_rss.h" 37 38 #include "ixgbe.h" 39 #include "mdio_if.h" 40 #include "ixgbe_sriov.h" 41 #include "ifdi_if.h" 42 #include "if_ix_mdio_hw.h" 43 #include "if_ix_mdio.h" 44 45 #include <net/netmap.h> 46 #include <dev/mdio/mdio.h> 47 #include <dev/netmap/netmap_kern.h> 48 49 /************************************************************************ 50 * Driver version 51 ************************************************************************/ 52 static const char ixgbe_driver_version[] = "5.0.1-k"; 53 54 /* Bound one admin-task invocation while still coalescing new requests. */ 55 #define IXGBE_ADMIN_TASK_BUDGET 8 56 57 /************************************************************************ 58 * PCI Device ID Table 59 * 60 * Used by probe to select devices to load on 61 * Last field stores an index into ixgbe_strings 62 * Last entry must be all 0s 63 * 64 * { Vendor ID, Device ID, SubVendor ID, SubDevice ID, String Index } 65 ************************************************************************/ 66 static const pci_vendor_info_t ixgbe_vendor_info_array[] = 67 { 68 PVID(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82598AF_DUAL_PORT, 69 "Intel(R) 82598EB AF (Dual Fiber)"), 70 PVID(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82598AF_SINGLE_PORT, 71 "Intel(R) 82598EB AF (Fiber)"), 72 PVID(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82598EB_CX4, 73 "Intel(R) 82598EB AT (CX4)"), 74 PVID(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82598AT, 75 "Intel(R) 82598EB AT"), 76 PVID(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82598AT2, 77 "Intel(R) 82598EB AT2"), 78 PVID(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82598, "Intel(R) 82598"), 79 PVID(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82598_DA_DUAL_PORT, 80 "Intel(R) 82598EB AF DA (Dual Fiber)"), 81 PVID(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82598_CX4_DUAL_PORT, 82 "Intel(R) 82598EB AT (Dual CX4)"), 83 PVID(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82598EB_XF_LR, 84 "Intel(R) 82598EB AF (Dual Fiber LR)"), 85 PVID(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82598_SR_DUAL_PORT_EM, 86 "Intel(R) 82598EB AF (Dual Fiber SR)"), 87 PVID(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82598EB_SFP_LOM, 88 "Intel(R) 82598EB LOM"), 89 PVID(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82598_BX, 90 "Intel(R) 82598EB BX Backplane"), 91 PVID(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_KX4, 92 "Intel(R) X520 82599 (KX4)"), 93 PVID(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_KX4_MEZZ, 94 "Intel(R) X520 82599 (KX4 Mezzanine)"), 95 PVID(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_SFP, 96 "Intel(R) X520 82599ES (SFI/SFP+)"), 97 PVID(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_KR, 98 "Intel(R) X520 82599ES (KR Backplane)"), 99 PVID(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_SFP_EM, 100 "Intel(R) X520-P2 82599 (SFP+)"), 101 PVID(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_XAUI_LOM, 102 "Intel(R) X520 82599 (XAUI/BX4)"), 103 PVID(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_CX4, 104 "Intel(R) X520 82599 (Dual CX4)"), 105 PVID(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_T3_LOM, 106 "Intel(R) X520-T 82599 LOM"), 107 PVID(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_LS, 108 "Intel(R) X520 82599 LS"), 109 PVID(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_COMBO_BACKPLANE, 110 "Intel(R) X520 82599 (Combined Backplane)"), 111 PVID(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_BACKPLANE_FCOE, 112 "Intel(R) X520 82599 (Backplane w/FCoE)"), 113 PVID(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_SFP_SF2, 114 "Intel(R) X520 82599 (Dual SFP+)"), 115 PVID(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_SFP_FCOE, 116 "Intel(R) X520 82599 (Dual SFP+ w/FCoE)"), 117 PVID(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599EN_SFP, 118 "Intel(R) X520-1 82599EN (SFP+)"), 119 PVID(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_SFP_SF_QP, 120 "Intel(R) X520-4 82599 (Quad SFP+)"), 121 PVID(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_QSFP_SF_QP, 122 "Intel(R) X520-Q1 82599 (QSFP+)"), 123 PVID(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X540T, 124 "Intel(R) X540-AT2"), 125 PVID(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X540T1, "Intel(R) X540-T1"), 126 PVID(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550T, "Intel(R) X550-T2"), 127 PVID(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550T1, "Intel(R) X550-T1"), 128 PVID(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_X_KR, 129 "Intel(R) X552 (KR Backplane)"), 130 PVID(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_X_KX4, 131 "Intel(R) X552 (KX4 Backplane)"), 132 PVID(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_X_10G_T, 133 "Intel(R) X552/X557-AT (10GBASE-T)"), 134 PVID(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_X_1G_T, 135 "Intel(R) X552 (1000BASE-T)"), 136 PVID(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_X_SFP, 137 "Intel(R) X552 (SFP+)"), 138 PVID(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_X_XFI, 139 "Intel(R) X552 (XFI Backplane)"), 140 PVID(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_A_KR, 141 "Intel(R) X553 (KR Backplane)"), 142 PVID(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_A_KR_L, 143 "Intel(R) X553 L (KR Backplane)"), 144 PVID(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_A_SFP, 145 "Intel(R) X553 (SFP+)"), 146 PVID(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_A_SFP_N, 147 "Intel(R) X553 N (SFP+)"), 148 PVID(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_A_QSFP, 149 "Intel(R) X553 (QSFP+)"), 150 PVID(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_A_QSFP_N, 151 "Intel(R) X553 N (QSFP+)"), 152 PVID(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_A_SGMII, 153 "Intel(R) X553 (1GbE SGMII)"), 154 PVID(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_A_SGMII_L, 155 "Intel(R) X553 L (1GbE SGMII)"), 156 PVID(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_A_10G_T, 157 "Intel(R) X553/X557-AT (10GBASE-T)"), 158 PVID(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_A_1G_T, 159 "Intel(R) X553 (1GbE)"), 160 PVID(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_A_1G_T_L, 161 "Intel(R) X553 L (1GbE)"), 162 PVID(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X540_BYPASS, 163 "Intel(R) X540-T2 (Bypass)"), 164 PVID(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_BYPASS, 165 "Intel(R) X520 82599 (Bypass)"), 166 PVID(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_E610_BACKPLANE, 167 "Intel(R) E610 (Backplane)"), 168 PVID(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_E610_SFP, 169 "Intel(R) E610 (SFP)"), 170 PVID(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_E610_2_5G_T, 171 "Intel(R) E610 (2.5 GbE)"), 172 PVID(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_E610_10G_T, 173 "Intel(R) E610 (10 GbE)"), 174 PVID(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_E610_SGMII, 175 "Intel(R) E610 (SGMII)"), 176 /* required last entry */ 177 PVID_END 178 }; 179 180 static void *ixgbe_register(device_t); 181 static int ixgbe_if_attach_pre(if_ctx_t); 182 static int ixgbe_if_attach_post(if_ctx_t); 183 static int ixgbe_if_detach(if_ctx_t); 184 static int ixgbe_if_shutdown(if_ctx_t); 185 static int ixgbe_if_suspend(if_ctx_t); 186 static int ixgbe_if_resume(if_ctx_t); 187 #ifdef PCI_IOV 188 static int ixgbe_device_iov_init(device_t, uint16_t, const nvlist_t *); 189 #endif 190 191 static void ixgbe_if_stop(if_ctx_t); 192 void ixgbe_if_enable_intr(if_ctx_t); 193 static void ixgbe_if_disable_intr(if_ctx_t); 194 static void ixgbe_link_intr_enable(if_ctx_t); 195 static int ixgbe_if_rx_queue_intr_enable(if_ctx_t, uint16_t); 196 static void ixgbe_if_media_status(if_ctx_t, struct ifmediareq *); 197 static int ixgbe_if_media_change(if_ctx_t); 198 static int ixgbe_if_msix_intr_assign(if_ctx_t, int); 199 static int ixgbe_if_mtu_set(if_ctx_t, uint32_t); 200 static void ixgbe_if_crcstrip_set(if_ctx_t, int, int); 201 static void ixgbe_if_multi_set(if_ctx_t); 202 static int ixgbe_if_promisc_set(if_ctx_t, int); 203 static int ixgbe_if_tx_queues_alloc(if_ctx_t, caddr_t *, uint64_t *, int, 204 int); 205 static int ixgbe_if_rx_queues_alloc(if_ctx_t, caddr_t *, uint64_t *, int, 206 int); 207 static void ixgbe_if_queues_free(if_ctx_t); 208 static void ixgbe_if_timer(if_ctx_t, uint16_t); 209 static const char *ixgbe_link_speed_to_str(u32 link_speed); 210 static void ixgbe_if_update_admin_status(if_ctx_t); 211 static void ixgbe_if_vlan_register(if_ctx_t, u16); 212 static void ixgbe_if_vlan_unregister(if_ctx_t, u16); 213 static int ixgbe_if_i2c_req(if_ctx_t, struct ifi2creq *); 214 static bool ixgbe_if_needs_restart(if_ctx_t, enum iflib_restart_event); 215 static void ixgbe_if_led_func(if_ctx_t, int); 216 static void ixgbe_led_restore(struct ixgbe_softc *); 217 int ixgbe_intr(void *); 218 219 static int ixgbe_if_priv_ioctl(if_ctx_t ctx, u_long command, caddr_t data); 220 221 /************************************************************************ 222 * Function prototypes 223 ************************************************************************/ 224 static uint64_t ixgbe_if_get_counter(if_ctx_t, ift_counter); 225 226 static void ixgbe_enable_queue(struct ixgbe_softc *, u32); 227 static void ixgbe_disable_queue(struct ixgbe_softc *, u32); 228 static void ixgbe_add_device_sysctls(if_ctx_t); 229 static int ixgbe_allocate_pci_resources(if_ctx_t); 230 static int ixgbe_setup_low_power_mode(if_ctx_t, bool); 231 232 static void ixgbe_config_dmac(struct ixgbe_softc *); 233 static void ixgbe_configure_ivars(struct ixgbe_softc *); 234 static void ixgbe_set_ivar(struct ixgbe_softc *, u8, u8, s8); 235 static u8 *ixgbe_mc_array_itr(struct ixgbe_hw *, u8 **, u32 *); 236 static bool ixgbe_sfp_probe(if_ctx_t); 237 238 static void ixgbe_free_pci_resources(if_ctx_t); 239 240 static int ixgbe_msix_link(void *); 241 static int ixgbe_msix_que(void *); 242 static void ixgbe_initialize_rss_mapping(struct ixgbe_softc *); 243 static void ixgbe_initialize_receive_units(if_ctx_t); 244 static void ixgbe_initialize_transmit_units(if_ctx_t); 245 246 static int ixgbe_setup_interface(if_ctx_t); 247 static void ixgbe_init_device_features(struct ixgbe_softc *); 248 static void ixgbe_check_fan_failure(struct ixgbe_softc *, u32, bool); 249 static void ixgbe_sbuf_fw_version(struct ixgbe_hw *, struct sbuf *); 250 static void ixgbe_print_fw_version(if_ctx_t); 251 static void ixgbe_add_media_types(if_ctx_t); 252 static void ixgbe_update_stats_counters(struct ixgbe_softc *); 253 static void ixgbe_config_link(if_ctx_t); 254 static void ixgbe_get_slot_info(struct ixgbe_softc *); 255 static void ixgbe_fw_mode_timer(void *); 256 static void ixgbe_configure_wakeup(if_ctx_t); 257 static void ixgbe_configure_wakeup_mta(if_ctx_t); 258 static void ixgbe_prepare_wakeup(if_ctx_t, bool); 259 static void ixgbe_enable_rx_drop(struct ixgbe_softc *); 260 static void ixgbe_disable_rx_drop(struct ixgbe_softc *); 261 262 static void ixgbe_add_hw_stats(struct ixgbe_softc *); 263 static int ixgbe_set_flowcntl(struct ixgbe_softc *, int); 264 static int ixgbe_set_advertise(struct ixgbe_softc *, int); 265 static int ixgbe_get_default_advertise(struct ixgbe_softc *); 266 static void ixgbe_config_gpie(struct ixgbe_softc *); 267 static void ixgbe_config_delay_values(struct ixgbe_softc *); 268 269 static void ixgbe_add_debug_sysctls(struct ixgbe_softc *sc); 270 static void ixgbe_add_debug_dump_sysctls(struct ixgbe_softc *sc); 271 static int ixgbe_debug_dump_ioctl(struct ixgbe_softc *sc, struct ifdrv *ifd); 272 static u8 ixgbe_debug_dump_print_cluster(struct ixgbe_softc *sc, 273 struct sbuf *sbuf, u8 cluster_id); 274 static int ixgbe_nvm_access_ioctl(struct ixgbe_softc *sc, struct ifdrv *ifd); 275 276 /* Sysctl handlers */ 277 static int ixgbe_sysctl_flowcntl(SYSCTL_HANDLER_ARGS); 278 static int ixgbe_sysctl_advertise(SYSCTL_HANDLER_ARGS); 279 static int ixgbe_sysctl_interrupt_rate_handler(SYSCTL_HANDLER_ARGS); 280 static int ixgbe_sysctl_dmac(SYSCTL_HANDLER_ARGS); 281 static int ixgbe_sysctl_phy_temp(SYSCTL_HANDLER_ARGS); 282 static int ixgbe_sysctl_phy_overtemp_occurred(SYSCTL_HANDLER_ARGS); 283 static int ixgbe_sysctl_print_fw_version(SYSCTL_HANDLER_ARGS); 284 #ifdef IXGBE_DEBUG 285 static int ixgbe_sysctl_power_state(SYSCTL_HANDLER_ARGS); 286 static int ixgbe_sysctl_print_rss_config(SYSCTL_HANDLER_ARGS); 287 #endif 288 static int ixgbe_sysctl_rdh_handler(SYSCTL_HANDLER_ARGS); 289 static int ixgbe_sysctl_rdt_handler(SYSCTL_HANDLER_ARGS); 290 static int ixgbe_sysctl_tdt_handler(SYSCTL_HANDLER_ARGS); 291 static int ixgbe_sysctl_tdh_handler(SYSCTL_HANDLER_ARGS); 292 static int ixgbe_sysctl_eee_state(SYSCTL_HANDLER_ARGS); 293 static int ixgbe_sysctl_tso_tcp_flags_mask(SYSCTL_HANDLER_ARGS); 294 295 static int ixgbe_sysctl_debug_dump_set_clusters(SYSCTL_HANDLER_ARGS); 296 static int ixgbe_sysctl_dump_debug_dump(SYSCTL_HANDLER_ARGS); 297 298 /* Deferred interrupt tasklets */ 299 static void ixgbe_handle_msf(void *); 300 static bool ixgbe_handle_mod(void *); 301 static void ixgbe_handle_phy(void *); 302 static u32 ixgbe_handle_fw_event(void *); 303 304 static int ixgbe_enable_lse(struct ixgbe_softc *sc); 305 static int ixgbe_disable_lse(struct ixgbe_softc *sc); 306 307 /************************************************************************ 308 * FreeBSD Device Interface Entry Points 309 ************************************************************************/ 310 static device_method_t ix_methods[] = { 311 /* Device interface */ 312 DEVMETHOD(device_register, ixgbe_register), 313 DEVMETHOD(device_probe, iflib_device_probe), 314 DEVMETHOD(device_attach, iflib_device_attach), 315 DEVMETHOD(device_detach, iflib_device_detach), 316 DEVMETHOD(device_shutdown, iflib_device_shutdown), 317 DEVMETHOD(device_suspend, iflib_device_suspend), 318 DEVMETHOD(device_resume, iflib_device_resume), 319 #ifdef PCI_IOV 320 DEVMETHOD(pci_iov_init, ixgbe_device_iov_init), 321 DEVMETHOD(pci_iov_uninit, iflib_device_iov_uninit_restart), 322 DEVMETHOD(pci_iov_add_vf, iflib_device_iov_add_vf), 323 #endif /* PCI_IOV */ 324 DEVMETHOD(bus_add_child, device_add_child_ordered), 325 DEVMETHOD(mdio_readreg, ixgbe_mdio_readreg_c22), 326 DEVMETHOD(mdio_writereg, ixgbe_mdio_writereg_c22), 327 328 DEVMETHOD_END 329 }; 330 331 static driver_t ix_driver = { 332 "ix", ix_methods, sizeof(struct ixgbe_softc), 333 }; 334 335 DRIVER_MODULE(mdio, ix, mdio_driver, 0, 0); /* needs to happen before ix */ 336 DRIVER_MODULE_ORDERED(ix, pci, ix_driver, NULL, NULL, SI_ORDER_ANY); /* needs to be last */ 337 IFLIB_PNP_INFO(pci, ix_driver, ixgbe_vendor_info_array); 338 MODULE_DEPEND(ix, pci, 1, 1, 1); 339 MODULE_DEPEND(ix, ether, 1, 1, 1); 340 MODULE_DEPEND(ix, iflib, 1, 1, 1); 341 MODULE_DEPEND(ix, mdio, 1, 1, 1); 342 343 #ifdef PCI_IOV 344 static int 345 ixgbe_device_iov_init(device_t dev, uint16_t num_vfs, 346 const nvlist_t *params) 347 { 348 struct ixgbe_softc *sc; 349 if_ctx_t ctx; 350 int error; 351 352 ctx = device_get_softc(dev); 353 sc = iflib_get_softc(ctx); 354 error = ixgbe_iov_validate(sc, num_vfs); 355 if (error != 0) 356 return (error); 357 return (iflib_device_iov_init_restart(dev, num_vfs, params)); 358 } 359 #endif 360 361 static device_method_t ixgbe_if_methods[] = { 362 DEVMETHOD(ifdi_attach_pre, ixgbe_if_attach_pre), 363 DEVMETHOD(ifdi_attach_post, ixgbe_if_attach_post), 364 DEVMETHOD(ifdi_detach, ixgbe_if_detach), 365 DEVMETHOD(ifdi_shutdown, ixgbe_if_shutdown), 366 DEVMETHOD(ifdi_suspend, ixgbe_if_suspend), 367 DEVMETHOD(ifdi_resume, ixgbe_if_resume), 368 DEVMETHOD(ifdi_init, ixgbe_if_init), 369 DEVMETHOD(ifdi_stop, ixgbe_if_stop), 370 DEVMETHOD(ifdi_msix_intr_assign, ixgbe_if_msix_intr_assign), 371 DEVMETHOD(ifdi_intr_enable, ixgbe_if_enable_intr), 372 DEVMETHOD(ifdi_intr_disable, ixgbe_if_disable_intr), 373 DEVMETHOD(ifdi_link_intr_enable, ixgbe_link_intr_enable), 374 DEVMETHOD(ifdi_tx_queue_intr_enable, ixgbe_if_rx_queue_intr_enable), 375 DEVMETHOD(ifdi_rx_queue_intr_enable, ixgbe_if_rx_queue_intr_enable), 376 DEVMETHOD(ifdi_tx_queues_alloc, ixgbe_if_tx_queues_alloc), 377 DEVMETHOD(ifdi_rx_queues_alloc, ixgbe_if_rx_queues_alloc), 378 DEVMETHOD(ifdi_queues_free, ixgbe_if_queues_free), 379 DEVMETHOD(ifdi_update_admin_status, ixgbe_if_update_admin_status), 380 DEVMETHOD(ifdi_multi_set, ixgbe_if_multi_set), 381 DEVMETHOD(ifdi_mtu_set, ixgbe_if_mtu_set), 382 DEVMETHOD(ifdi_crcstrip_set, ixgbe_if_crcstrip_set), 383 DEVMETHOD(ifdi_media_status, ixgbe_if_media_status), 384 DEVMETHOD(ifdi_media_change, ixgbe_if_media_change), 385 DEVMETHOD(ifdi_promisc_set, ixgbe_if_promisc_set), 386 DEVMETHOD(ifdi_timer, ixgbe_if_timer), 387 DEVMETHOD(ifdi_vlan_register, ixgbe_if_vlan_register), 388 DEVMETHOD(ifdi_vlan_unregister, ixgbe_if_vlan_unregister), 389 DEVMETHOD(ifdi_get_counter, ixgbe_if_get_counter), 390 DEVMETHOD(ifdi_i2c_req, ixgbe_if_i2c_req), 391 DEVMETHOD(ifdi_needs_restart, ixgbe_if_needs_restart), 392 DEVMETHOD(ifdi_priv_ioctl, ixgbe_if_priv_ioctl), 393 DEVMETHOD(ifdi_led_func, ixgbe_if_led_func), 394 #ifdef PCI_IOV 395 DEVMETHOD(ifdi_iov_init, ixgbe_if_iov_init), 396 DEVMETHOD(ifdi_iov_uninit, ixgbe_if_iov_uninit), 397 DEVMETHOD(ifdi_iov_vf_add, ixgbe_if_iov_vf_add), 398 DEVMETHOD(ifdi_vf_status, ixgbe_if_vf_status), 399 #endif /* PCI_IOV */ 400 DEVMETHOD_END 401 }; 402 403 /* 404 * TUNEABLE PARAMETERS: 405 */ 406 407 static SYSCTL_NODE(_hw, OID_AUTO, ix, CTLFLAG_RD | CTLFLAG_MPSAFE, 0, 408 "IXGBE driver parameters"); 409 static driver_t ixgbe_if_driver = { 410 "ixgbe_if", ixgbe_if_methods, sizeof(struct ixgbe_softc) 411 }; 412 413 static int ixgbe_max_interrupt_rate = (4000000 / IXGBE_LOW_LATENCY); 414 SYSCTL_INT(_hw_ix, OID_AUTO, max_interrupt_rate, CTLFLAG_RDTUN, 415 &ixgbe_max_interrupt_rate, 0, "Maximum interrupts per second"); 416 417 /* Flow control setting, default to full */ 418 static int ixgbe_flow_control = ixgbe_fc_full; 419 SYSCTL_INT(_hw_ix, OID_AUTO, flow_control, CTLFLAG_RDTUN, 420 &ixgbe_flow_control, 0, "Default flow control used for all adapters"); 421 422 /* Advertise Speed, default to 0 (auto) */ 423 static int ixgbe_advertise_speed = 0; 424 SYSCTL_INT(_hw_ix, OID_AUTO, advertise_speed, CTLFLAG_RDTUN, 425 &ixgbe_advertise_speed, 0, "Default advertised speed for all adapters"); 426 427 /* 428 * Smart speed setting, default to on 429 * this only works as a compile option 430 * right now as its during attach, set 431 * this to 'ixgbe_smart_speed_off' to 432 * disable. 433 */ 434 static int ixgbe_smart_speed = ixgbe_smart_speed_on; 435 436 /* 437 * MSI-X should be the default for best performance, 438 * but this allows it to be forced off for testing. 439 */ 440 static int ixgbe_enable_msix = 1; 441 SYSCTL_INT(_hw_ix, OID_AUTO, enable_msix, CTLFLAG_RDTUN, &ixgbe_enable_msix, 442 0, 443 "Enable MSI-X interrupts"); 444 445 /* 446 * Defining this on will allow the use 447 * of unsupported SFP+ modules, note that 448 * doing so you are on your own :) 449 */ 450 static int allow_unsupported_sfp = false; 451 SYSCTL_INT(_hw_ix, OID_AUTO, unsupported_sfp, CTLFLAG_RDTUN, 452 &allow_unsupported_sfp, 0, 453 "Allow unsupported SFP modules...use at your own risk"); 454 455 /* 456 * Not sure if Flow Director is fully baked, 457 * so we'll default to turning it off. 458 */ 459 static int ixgbe_enable_fdir = 0; 460 SYSCTL_INT(_hw_ix, OID_AUTO, enable_fdir, CTLFLAG_RDTUN, &ixgbe_enable_fdir, 461 0, 462 "Enable Flow Director"); 463 464 /* Receive-Side Scaling */ 465 static int ixgbe_enable_rss = 1; 466 SYSCTL_INT(_hw_ix, OID_AUTO, enable_rss, CTLFLAG_RDTUN, &ixgbe_enable_rss, 467 0, 468 "Enable Receive-Side Scaling (RSS)"); 469 470 /* 471 * AIM: Adaptive Interrupt Moderation 472 * which means that the interrupt rate 473 * is varied over time based on the 474 * traffic for that interrupt vector 475 */ 476 static int ixgbe_enable_aim = false; 477 SYSCTL_INT(_hw_ix, OID_AUTO, enable_aim, CTLFLAG_RWTUN, &ixgbe_enable_aim, 478 0, 479 "Enable adaptive interrupt moderation"); 480 481 #if 0 482 /* Keep running tab on them for sanity check */ 483 static int ixgbe_total_ports; 484 #endif 485 486 MALLOC_DEFINE(M_IXGBE, "ix", "ix driver allocations"); 487 488 /* 489 * For Flow Director: this is the number of TX packets we sample 490 * for the filter pool, this means every 20th packet will be probed. 491 * 492 * This feature can be disabled by setting this to 0. 493 */ 494 static int atr_sample_rate = 20; 495 496 extern struct if_txrx ixgbe_txrx; 497 498 static struct if_shared_ctx ixgbe_sctx_init = { 499 .isc_magic = IFLIB_MAGIC, 500 .isc_q_align = PAGE_SIZE,/* max(DBA_ALIGN, PAGE_SIZE) */ 501 .isc_tx_maxsize = IXGBE_TSO_SIZE + sizeof(struct ether_vlan_header), 502 .isc_tx_maxsegsize = PAGE_SIZE, 503 .isc_tso_maxsize = IXGBE_TSO_SIZE + sizeof(struct ether_vlan_header), 504 .isc_tso_maxsegsize = PAGE_SIZE, 505 .isc_rx_maxsize = PAGE_SIZE*4, 506 .isc_rx_nsegments = 1, 507 .isc_rx_maxsegsize = PAGE_SIZE*4, 508 .isc_nfl = 1, 509 .isc_ntxqs = 1, 510 .isc_nrxqs = 1, 511 512 .isc_admin_intrcnt = 1, 513 .isc_vendor_info = ixgbe_vendor_info_array, 514 .isc_driver_version = ixgbe_driver_version, 515 .isc_driver = &ixgbe_if_driver, 516 .isc_flags = IFLIB_TSO_INIT_IP, 517 518 .isc_nrxd_min = {MIN_RXD}, 519 .isc_ntxd_min = {MIN_TXD}, 520 .isc_nrxd_max = {MAX_RXD}, 521 .isc_ntxd_max = {MAX_TXD}, 522 .isc_nrxd_default = {DEFAULT_RXD}, 523 .isc_ntxd_default = {DEFAULT_TXD}, 524 }; 525 526 /************************************************************************ 527 * ixgbe_if_tx_queues_alloc 528 ************************************************************************/ 529 static int 530 ixgbe_if_tx_queues_alloc(if_ctx_t ctx, caddr_t *vaddrs, uint64_t *paddrs, 531 int ntxqs, int ntxqsets) 532 { 533 struct ixgbe_softc *sc = iflib_get_softc(ctx); 534 if_softc_ctx_t scctx = sc->shared; 535 struct ix_tx_queue *que; 536 int i, j, error; 537 538 MPASS(sc->num_tx_queues > 0); 539 MPASS(sc->num_tx_queues == ntxqsets); 540 MPASS(ntxqs == 1); 541 542 /* Allocate queue structure memory */ 543 sc->tx_queues = 544 (struct ix_tx_queue *)malloc(sizeof(struct ix_tx_queue) * 545 ntxqsets, M_IXGBE, M_NOWAIT | M_ZERO); 546 if (!sc->tx_queues) { 547 device_printf(iflib_get_dev(ctx), 548 "Unable to allocate TX ring memory\n"); 549 return (ENOMEM); 550 } 551 552 for (i = 0, que = sc->tx_queues; i < ntxqsets; i++, que++) { 553 struct tx_ring *txr = &que->txr; 554 555 /* In case SR-IOV is enabled, align the index properly */ 556 txr->me = ixgbe_vf_que_index(sc->iov_mode, sc->pool, i); 557 558 txr->sc = que->sc = sc; 559 560 /* Allocate report status array */ 561 txr->tx_rsq = (qidx_t *)malloc(sizeof(qidx_t) * 562 scctx->isc_ntxd[0], M_IXGBE, M_NOWAIT | M_ZERO); 563 if (txr->tx_rsq == NULL) { 564 error = ENOMEM; 565 goto fail; 566 } 567 for (j = 0; j < scctx->isc_ntxd[0]; j++) 568 txr->tx_rsq[j] = QIDX_INVALID; 569 /* get virtual and physical address of the hardware queues */ 570 txr->tail = IXGBE_TDT(txr->me); 571 txr->tx_base = (union ixgbe_adv_tx_desc *)vaddrs[i]; 572 txr->tx_paddr = paddrs[i]; 573 574 txr->bytes = 0; 575 txr->total_packets = 0; 576 577 /* Set the rate at which we sample packets */ 578 if (sc->feat_en & IXGBE_FEATURE_FDIR) 579 txr->atr_sample = atr_sample_rate; 580 581 } 582 583 device_printf(iflib_get_dev(ctx), "allocated for %d queues\n", 584 sc->num_tx_queues); 585 586 return (0); 587 588 fail: 589 ixgbe_if_queues_free(ctx); 590 591 return (error); 592 } /* ixgbe_if_tx_queues_alloc */ 593 594 /************************************************************************ 595 * ixgbe_if_rx_queues_alloc 596 ************************************************************************/ 597 static int 598 ixgbe_if_rx_queues_alloc(if_ctx_t ctx, caddr_t *vaddrs, uint64_t *paddrs, 599 int nrxqs, int nrxqsets) 600 { 601 struct ixgbe_softc *sc = iflib_get_softc(ctx); 602 struct ix_rx_queue *que; 603 int i; 604 605 MPASS(sc->num_rx_queues > 0); 606 MPASS(sc->num_rx_queues == nrxqsets); 607 MPASS(nrxqs == 1); 608 609 /* Allocate queue structure memory */ 610 sc->rx_queues = 611 (struct ix_rx_queue *)malloc(sizeof(struct ix_rx_queue)*nrxqsets, 612 M_IXGBE, M_NOWAIT | M_ZERO); 613 if (!sc->rx_queues) { 614 device_printf(iflib_get_dev(ctx), 615 "Unable to allocate TX ring memory\n"); 616 return (ENOMEM); 617 } 618 619 for (i = 0, que = sc->rx_queues; i < nrxqsets; i++, que++) { 620 struct rx_ring *rxr = &que->rxr; 621 622 /* In case SR-IOV is enabled, align the index properly */ 623 rxr->me = ixgbe_vf_que_index(sc->iov_mode, sc->pool, i); 624 625 rxr->sc = que->sc = sc; 626 627 /* get the virtual and physical address of the hw queues */ 628 rxr->tail = IXGBE_RDT(rxr->me); 629 rxr->rx_base = (union ixgbe_adv_rx_desc *)vaddrs[i]; 630 rxr->rx_paddr = paddrs[i]; 631 rxr->bytes = 0; 632 rxr->que = que; 633 } 634 635 device_printf(iflib_get_dev(ctx), "allocated for %d rx queues\n", 636 sc->num_rx_queues); 637 638 return (0); 639 } /* ixgbe_if_rx_queues_alloc */ 640 641 /************************************************************************ 642 * ixgbe_if_queues_free 643 ************************************************************************/ 644 static void 645 ixgbe_if_queues_free(if_ctx_t ctx) 646 { 647 struct ixgbe_softc *sc = iflib_get_softc(ctx); 648 struct ix_tx_queue *tx_que = sc->tx_queues; 649 struct ix_rx_queue *rx_que = sc->rx_queues; 650 int i; 651 652 if (tx_que != NULL) { 653 for (i = 0; i < sc->num_tx_queues; i++, tx_que++) { 654 struct tx_ring *txr = &tx_que->txr; 655 if (txr->tx_rsq == NULL) 656 break; 657 658 free(txr->tx_rsq, M_IXGBE); 659 txr->tx_rsq = NULL; 660 } 661 662 free(sc->tx_queues, M_IXGBE); 663 sc->tx_queues = NULL; 664 } 665 if (rx_que != NULL) { 666 free(sc->rx_queues, M_IXGBE); 667 sc->rx_queues = NULL; 668 } 669 } /* ixgbe_if_queues_free */ 670 671 /************************************************************************ 672 * ixgbe_initialize_rss_mapping 673 ************************************************************************/ 674 static void 675 ixgbe_initialize_rss_mapping(struct ixgbe_softc *sc) 676 { 677 struct ixgbe_hw *hw = &sc->hw; 678 bool per_pool_rss; 679 u32 reta = 0, mrqc, rss_fields, rss_key[10]; 680 int i, index_mult, j, queue_id, reta_queues, table_size; 681 u32 rss_hash_config; 682 #ifdef PCI_IOV 683 u32 pfmrqc; 684 #endif 685 686 if (sc->feat_en & IXGBE_FEATURE_RSS) { 687 /* Fetch the configured RSS key */ 688 rss_getkey((uint8_t *)&rss_key); 689 } else { 690 /* set up random bits */ 691 arc4rand(&rss_key, sizeof(rss_key), 0); 692 } 693 694 /* Set multiplier for RETA setup and table size based on MAC */ 695 index_mult = 0x1; 696 per_pool_rss = false; 697 table_size = 128; 698 switch (sc->hw.mac.type) { 699 case ixgbe_mac_82598EB: 700 index_mult = 0x11; 701 break; 702 case ixgbe_mac_X550: 703 case ixgbe_mac_X550EM_x: 704 case ixgbe_mac_X550EM_a: 705 case ixgbe_mac_E610: 706 table_size = 512; 707 #ifdef PCI_IOV 708 if (sc->iov_mode != IXGBE_NO_VM) { 709 per_pool_rss = true; 710 table_size = 64; 711 } 712 #endif 713 break; 714 default: 715 break; 716 } 717 718 /* 719 * The global RETA is shared by the PF and VFs on 82599 and X540. 720 * X550-family devices instead use per-pool tables in multiple-RSS 721 * mode; initialize only the PF pool here because each VF owns and 722 * programs its own key and redirection table. 723 * On the shared tables, program all four queue indices while SR-IOV 724 * is active so a VF can use its full queue grant even when the PF uses 725 * fewer queues. PSRTYPE.RQPL limits the subset selected in each pool. 726 */ 727 reta_queues = sc->num_rx_queues; 728 #ifdef PCI_IOV 729 if (sc->iov_mode != IXGBE_NO_VM && !per_pool_rss) 730 reta_queues = MAX(reta_queues, 4); 731 #endif 732 733 /* Set up the redirection table */ 734 for (i = 0, j = 0; i < table_size; i++, j++) { 735 if (j == reta_queues) 736 j = 0; 737 738 if (sc->feat_en & IXGBE_FEATURE_RSS) { 739 /* 740 * Fetch the RSS bucket id for the given indirection 741 * entry. Cap it at the number of queue indices that must 742 * be represented in the shared table. 743 */ 744 queue_id = rss_get_indirection_to_bucket(i); 745 queue_id = queue_id % reta_queues; 746 } else 747 queue_id = (j * index_mult); 748 749 /* 750 * The low 8 bits are for hash value (n+0); 751 * The next 8 bits are for hash value (n+1), etc. 752 */ 753 reta = reta >> 8; 754 reta = reta | (((uint32_t)queue_id) << 24); 755 if ((i & 3) == 3) { 756 if (per_pool_rss) { 757 #ifdef PCI_IOV 758 IXGBE_WRITE_REG(hw, 759 IXGBE_PFVFRETA(i >> 2, sc->pool), reta); 760 #endif 761 } else if (i < 128) 762 IXGBE_WRITE_REG(hw, IXGBE_RETA(i >> 2), reta); 763 else 764 IXGBE_WRITE_REG(hw, 765 IXGBE_ERETA((i >> 2) - 32), reta); 766 reta = 0; 767 } 768 } 769 770 /* Now fill our hash function seeds */ 771 for (i = 0; i < 10; i++) { 772 if (per_pool_rss) { 773 #ifdef PCI_IOV 774 IXGBE_WRITE_REG(hw, IXGBE_PFVFRSSRK(i, sc->pool), 775 rss_key[i]); 776 #endif 777 } else 778 IXGBE_WRITE_REG(hw, IXGBE_RSSRK(i), rss_key[i]); 779 } 780 781 /* Perform hash on these packet types */ 782 if (sc->feat_en & IXGBE_FEATURE_RSS) 783 rss_hash_config = rss_gethashconfig(); 784 else { 785 /* 786 * Disable UDP - IP fragments aren't currently being handled 787 * and so we end up with a mix of 2-tuple and 4-tuple 788 * traffic. 789 */ 790 rss_hash_config = RSS_HASHTYPE_RSS_IPV4 | 791 RSS_HASHTYPE_RSS_TCP_IPV4 | 792 RSS_HASHTYPE_RSS_IPV6 | 793 RSS_HASHTYPE_RSS_TCP_IPV6 | 794 RSS_HASHTYPE_RSS_IPV6_EX | 795 RSS_HASHTYPE_RSS_TCP_IPV6_EX; 796 } 797 798 mrqc = ixgbe_get_mrqc(sc->iov_mode); 799 rss_fields = 0; 800 if (rss_hash_config & RSS_HASHTYPE_RSS_IPV4) 801 rss_fields |= IXGBE_MRQC_RSS_FIELD_IPV4; 802 if (rss_hash_config & RSS_HASHTYPE_RSS_TCP_IPV4) 803 rss_fields |= IXGBE_MRQC_RSS_FIELD_IPV4_TCP; 804 if (rss_hash_config & RSS_HASHTYPE_RSS_IPV6) 805 rss_fields |= IXGBE_MRQC_RSS_FIELD_IPV6; 806 if (rss_hash_config & RSS_HASHTYPE_RSS_TCP_IPV6) 807 rss_fields |= IXGBE_MRQC_RSS_FIELD_IPV6_TCP; 808 if (rss_hash_config & RSS_HASHTYPE_RSS_IPV6_EX) 809 rss_fields |= IXGBE_MRQC_RSS_FIELD_IPV6_EX; 810 if (rss_hash_config & RSS_HASHTYPE_RSS_TCP_IPV6_EX) 811 rss_fields |= IXGBE_MRQC_RSS_FIELD_IPV6_EX_TCP; 812 if (rss_hash_config & RSS_HASHTYPE_RSS_UDP_IPV4) 813 rss_fields |= IXGBE_MRQC_RSS_FIELD_IPV4_UDP; 814 if (rss_hash_config & RSS_HASHTYPE_RSS_UDP_IPV6) 815 rss_fields |= IXGBE_MRQC_RSS_FIELD_IPV6_UDP; 816 if (rss_hash_config & RSS_HASHTYPE_RSS_UDP_IPV6_EX) 817 rss_fields |= IXGBE_MRQC_RSS_FIELD_IPV6_EX_UDP; 818 if (hw->mac.type == ixgbe_mac_E610) { 819 /* E610 folds IPv6 extension headers into the base selectors. */ 820 if (rss_fields & IXGBE_MRQC_RSS_FIELD_IPV6_EX) 821 rss_fields |= IXGBE_MRQC_RSS_FIELD_IPV6; 822 if (rss_fields & IXGBE_MRQC_RSS_FIELD_IPV6_EX_TCP) 823 rss_fields |= IXGBE_MRQC_RSS_FIELD_IPV6_TCP; 824 if (rss_fields & IXGBE_MRQC_RSS_FIELD_IPV6_EX_UDP) 825 rss_fields |= IXGBE_MRQC_RSS_FIELD_IPV6_UDP; 826 rss_fields &= ~(IXGBE_MRQC_RSS_FIELD_IPV6_EX | 827 IXGBE_MRQC_RSS_FIELD_IPV6_EX_TCP | 828 IXGBE_MRQC_RSS_FIELD_IPV6_EX_UDP); 829 } 830 831 if (per_pool_rss) { 832 #ifdef PCI_IOV 833 mrqc |= IXGBE_MRQC_MULTIPLE_RSS; 834 IXGBE_WRITE_REG(hw, IXGBE_MRQC, mrqc); 835 836 pfmrqc = IXGBE_MRQC_RSSEN | rss_fields; 837 IXGBE_WRITE_REG(hw, IXGBE_PFVFMRQC(sc->pool), pfmrqc); 838 #endif 839 } else { 840 mrqc |= rss_fields; 841 IXGBE_WRITE_REG(hw, IXGBE_MRQC, mrqc); 842 } 843 } /* ixgbe_initialize_rss_mapping */ 844 845 /************************************************************************ 846 * ixgbe_initialize_receive_units - Setup receive registers and features. 847 ************************************************************************/ 848 #define BSIZEPKT_ROUNDUP ((1<<IXGBE_SRRCTL_BSIZEPKT_SHIFT)-1) 849 850 static void 851 ixgbe_initialize_receive_units(if_ctx_t ctx) 852 { 853 struct ixgbe_softc *sc = iflib_get_softc(ctx); 854 if_softc_ctx_t scctx = sc->shared; 855 struct ixgbe_hw *hw = &sc->hw; 856 if_t ifp = iflib_get_ifp(ctx); 857 struct ix_rx_queue *que; 858 int i, j; 859 u32 bufsz, fctrl, srrctl, rxcsum; 860 u32 hlreg; 861 862 /* 863 * Make sure receives are disabled while 864 * setting up the descriptor ring 865 */ 866 ixgbe_disable_rx(hw); 867 868 /* Enable broadcasts */ 869 fctrl = IXGBE_READ_REG(hw, IXGBE_FCTRL); 870 fctrl |= IXGBE_FCTRL_BAM; 871 if (sc->hw.mac.type == ixgbe_mac_82598EB) { 872 fctrl |= IXGBE_FCTRL_DPF; 873 fctrl |= IXGBE_FCTRL_PMCF; 874 } 875 IXGBE_WRITE_REG(hw, IXGBE_FCTRL, fctrl); 876 877 /* Set for Jumbo Frames? */ 878 hlreg = IXGBE_READ_REG(hw, IXGBE_HLREG0); 879 if (if_getmtu(ifp) > ETHERMTU) 880 hlreg |= IXGBE_HLREG0_JUMBOEN; 881 else 882 hlreg &= ~IXGBE_HLREG0_JUMBOEN; 883 IXGBE_WRITE_REG(hw, IXGBE_HLREG0, hlreg); 884 885 bufsz = (sc->rx_mbuf_sz + BSIZEPKT_ROUNDUP) >> 886 IXGBE_SRRCTL_BSIZEPKT_SHIFT; 887 888 /* Setup the Base and Length of the Rx Descriptor Ring */ 889 for (i = 0, que = sc->rx_queues; i < sc->num_rx_queues; i++, que++) { 890 struct rx_ring *rxr = &que->rxr; 891 u64 rdba = rxr->rx_paddr; 892 893 j = rxr->me; 894 895 /* Setup the Base and Length of the Rx Descriptor Ring */ 896 IXGBE_WRITE_REG(hw, IXGBE_RDBAL(j), 897 (rdba & 0x00000000ffffffffULL)); 898 IXGBE_WRITE_REG(hw, IXGBE_RDBAH(j), (rdba >> 32)); 899 IXGBE_WRITE_REG(hw, IXGBE_RDLEN(j), 900 scctx->isc_nrxd[0] * sizeof(union ixgbe_adv_rx_desc)); 901 902 /* Set up the SRRCTL register */ 903 srrctl = IXGBE_READ_REG(hw, IXGBE_SRRCTL(j)); 904 srrctl &= ~IXGBE_SRRCTL_BSIZEHDR_MASK; 905 srrctl &= ~IXGBE_SRRCTL_BSIZEPKT_MASK; 906 srrctl |= bufsz; 907 srrctl |= IXGBE_SRRCTL_DESCTYPE_ADV_ONEBUF; 908 909 /* 910 * Set DROP_EN iff we have no flow control and >1 queue. 911 * Note that srrctl was cleared shortly before during reset, 912 * so we do not need to clear the bit, but do it just in case 913 * this code is moved elsewhere. 914 */ 915 if (sc->num_rx_queues > 1 && 916 sc->hw.fc.requested_mode == ixgbe_fc_none) { 917 srrctl |= IXGBE_SRRCTL_DROP_EN; 918 } else { 919 srrctl &= ~IXGBE_SRRCTL_DROP_EN; 920 } 921 922 IXGBE_WRITE_REG(hw, IXGBE_SRRCTL(j), srrctl); 923 924 /* Setup the HW Rx Head and Tail Descriptor Pointers */ 925 IXGBE_WRITE_REG(hw, IXGBE_RDH(j), 0); 926 IXGBE_WRITE_REG(hw, IXGBE_RDT(j), 0); 927 928 /* Set the driver rx tail address */ 929 rxr->tail = IXGBE_RDT(rxr->me); 930 } 931 932 if (sc->hw.mac.type != ixgbe_mac_82598EB) { 933 u32 psrtype = IXGBE_PSRTYPE_TCPHDR | 934 IXGBE_PSRTYPE_UDPHDR | 935 IXGBE_PSRTYPE_IPV4HDR | 936 IXGBE_PSRTYPE_IPV6HDR; 937 938 /* 939 * In VMDq+RSS mode PSRTYPE is per pool, and RQPL controls 940 * how many receive queues RSS may select within that pool. 941 * The PF occupies the last pool rather than pool zero. 942 */ 943 #ifdef PCI_IOV 944 if (sc->iov_mode != IXGBE_NO_VM) { 945 if (sc->num_rx_queues > 3) 946 psrtype |= 2u << IXGBE_PSRTYPE_RQPL_SHIFT; 947 else if (sc->num_rx_queues > 1) 948 psrtype |= 1u << IXGBE_PSRTYPE_RQPL_SHIFT; 949 } 950 #endif 951 IXGBE_WRITE_REG(hw, IXGBE_PSRTYPE(sc->pool), psrtype); 952 } 953 954 rxcsum = IXGBE_READ_REG(hw, IXGBE_RXCSUM); 955 956 ixgbe_initialize_rss_mapping(sc); 957 958 if (sc->feat_en & IXGBE_FEATURE_RSS) { 959 /* RSS and RX IPP Checksum are mutually exclusive */ 960 rxcsum |= IXGBE_RXCSUM_PCSD; 961 } 962 963 if (if_getcapenable(ifp) & IFCAP_RXCSUM) 964 rxcsum |= IXGBE_RXCSUM_PCSD; 965 966 /* This is useful for calculating UDP/IP fragment checksums */ 967 if (!(rxcsum & IXGBE_RXCSUM_PCSD)) 968 rxcsum |= IXGBE_RXCSUM_IPPCSE; 969 970 IXGBE_WRITE_REG(hw, IXGBE_RXCSUM, rxcsum); 971 972 } /* ixgbe_initialize_receive_units */ 973 974 /************************************************************************ 975 * ixgbe_initialize_transmit_units - Enable transmit units. 976 ************************************************************************/ 977 static void 978 ixgbe_initialize_transmit_units(if_ctx_t ctx) 979 { 980 struct ixgbe_softc *sc = iflib_get_softc(ctx); 981 struct ixgbe_hw *hw = &sc->hw; 982 if_softc_ctx_t scctx = sc->shared; 983 struct ix_tx_queue *que; 984 int i; 985 986 /* Setup the Base and Length of the Tx Descriptor Ring */ 987 for (i = 0, que = sc->tx_queues; i < sc->num_tx_queues; 988 i++, que++) { 989 struct tx_ring *txr = &que->txr; 990 u64 tdba = txr->tx_paddr; 991 u32 txctrl = 0; 992 int j = txr->me; 993 994 IXGBE_WRITE_REG(hw, IXGBE_TDBAL(j), 995 (tdba & 0x00000000ffffffffULL)); 996 IXGBE_WRITE_REG(hw, IXGBE_TDBAH(j), (tdba >> 32)); 997 IXGBE_WRITE_REG(hw, IXGBE_TDLEN(j), 998 scctx->isc_ntxd[0] * sizeof(union ixgbe_adv_tx_desc)); 999 1000 /* Setup the HW Tx Head and Tail descriptor pointers */ 1001 IXGBE_WRITE_REG(hw, IXGBE_TDH(j), 0); 1002 IXGBE_WRITE_REG(hw, IXGBE_TDT(j), 0); 1003 1004 /* Cache the tail address */ 1005 txr->tail = IXGBE_TDT(txr->me); 1006 1007 txr->tx_rs_cidx = txr->tx_rs_pidx; 1008 txr->tx_cidx_processed = scctx->isc_ntxd[0] - 1; 1009 for (int k = 0; k < scctx->isc_ntxd[0]; k++) 1010 txr->tx_rsq[k] = QIDX_INVALID; 1011 1012 /* Disable Head Writeback */ 1013 /* 1014 * Note: for X550 series devices, these registers are actually 1015 * prefixed with TPH_ isntead of DCA_, but the addresses and 1016 * fields remain the same. 1017 */ 1018 switch (hw->mac.type) { 1019 case ixgbe_mac_82598EB: 1020 txctrl = IXGBE_READ_REG(hw, IXGBE_DCA_TXCTRL(j)); 1021 break; 1022 default: 1023 txctrl = 1024 IXGBE_READ_REG(hw, IXGBE_DCA_TXCTRL_82599(j)); 1025 break; 1026 } 1027 txctrl &= ~IXGBE_DCA_TXCTRL_DESC_WRO_EN; 1028 switch (hw->mac.type) { 1029 case ixgbe_mac_82598EB: 1030 IXGBE_WRITE_REG(hw, IXGBE_DCA_TXCTRL(j), txctrl); 1031 break; 1032 default: 1033 IXGBE_WRITE_REG(hw, IXGBE_DCA_TXCTRL_82599(j), 1034 txctrl); 1035 break; 1036 } 1037 1038 } 1039 1040 if (hw->mac.type != ixgbe_mac_82598EB) { 1041 u32 dmatxctl, rttdcs; 1042 1043 dmatxctl = IXGBE_READ_REG(hw, IXGBE_DMATXCTL); 1044 dmatxctl |= IXGBE_DMATXCTL_TE; 1045 IXGBE_WRITE_REG(hw, IXGBE_DMATXCTL, dmatxctl); 1046 /* Disable arbiter to set MTQC */ 1047 rttdcs = IXGBE_READ_REG(hw, IXGBE_RTTDCS); 1048 rttdcs |= IXGBE_RTTDCS_ARBDIS; 1049 IXGBE_WRITE_REG(hw, IXGBE_RTTDCS, rttdcs); 1050 IXGBE_WRITE_REG(hw, IXGBE_MTQC, 1051 ixgbe_get_mtqc(sc->iov_mode)); 1052 rttdcs &= ~IXGBE_RTTDCS_ARBDIS; 1053 IXGBE_WRITE_REG(hw, IXGBE_RTTDCS, rttdcs); 1054 } 1055 1056 } /* ixgbe_initialize_transmit_units */ 1057 1058 static int 1059 ixgbe_check_fw_api_version(struct ixgbe_softc *sc) 1060 { 1061 struct ixgbe_hw *hw = &sc->hw; 1062 if (hw->api_maj_ver > IXGBE_FW_API_VER_MAJOR) { 1063 device_printf(sc->dev, 1064 "The driver for the device stopped because the NVM " 1065 "image is newer than expected. You must install the " 1066 "most recent version of the network driver.\n"); 1067 return (EOPNOTSUPP); 1068 } else if (hw->api_maj_ver == IXGBE_FW_API_VER_MAJOR && 1069 hw->api_min_ver > (IXGBE_FW_API_VER_MINOR + 2)) { 1070 device_printf(sc->dev, 1071 "The driver for the device detected a newer version of " 1072 "the NVM image than expected. Please install the most " 1073 "recent version of the network driver.\n"); 1074 } else if (hw->api_maj_ver < IXGBE_FW_API_VER_MAJOR || 1075 hw->api_min_ver < IXGBE_FW_API_VER_MINOR - 2) { 1076 device_printf(sc->dev, 1077 "The driver for the device detected an older version " 1078 "of the NVM image than expected. " 1079 "Please update the NVM image.\n"); 1080 } 1081 return (0); 1082 } 1083 1084 /************************************************************************ 1085 * ixgbe_register 1086 ************************************************************************/ 1087 static void * 1088 ixgbe_register(device_t dev) 1089 { 1090 return (&ixgbe_sctx_init); 1091 } /* ixgbe_register */ 1092 1093 /************************************************************************ 1094 * ixgbe_if_attach_pre - Device initialization routine, part 1 1095 * 1096 * Called when the driver is being loaded. 1097 * Identifies the type of hardware, initializes the hardware, 1098 * and initializes iflib structures. 1099 * 1100 * return 0 on success, positive on failure 1101 ************************************************************************/ 1102 static int 1103 ixgbe_if_attach_pre(if_ctx_t ctx) 1104 { 1105 struct ixgbe_softc *sc; 1106 device_t dev; 1107 if_softc_ctx_t scctx; 1108 struct ixgbe_hw *hw; 1109 int error = 0; 1110 u32 ctrl_ext; 1111 size_t i; 1112 1113 INIT_DEBUGOUT("ixgbe_attach: begin"); 1114 1115 /* Allocate, clear, and link in our adapter structure */ 1116 dev = iflib_get_dev(ctx); 1117 sc = iflib_get_softc(ctx); 1118 sc->hw.back = sc; 1119 sc->ctx = ctx; 1120 sc->dev = dev; 1121 scctx = sc->shared = iflib_get_softc_ctx(ctx); 1122 sc->media = iflib_get_media(ctx); 1123 hw = &sc->hw; 1124 1125 /* Determine hardware revision */ 1126 hw->vendor_id = pci_get_vendor(dev); 1127 hw->device_id = pci_get_device(dev); 1128 hw->revision_id = pci_get_revid(dev); 1129 hw->subsystem_vendor_id = pci_get_subvendor(dev); 1130 hw->subsystem_device_id = pci_get_subdevice(dev); 1131 1132 /* Do base PCI setup - map BAR0 */ 1133 if (ixgbe_allocate_pci_resources(ctx)) { 1134 device_printf(dev, "Allocation of PCI resources failed\n"); 1135 return (ENXIO); 1136 } 1137 1138 /* let hardware know driver is loaded */ 1139 ctrl_ext = IXGBE_READ_REG(hw, IXGBE_CTRL_EXT); 1140 ctrl_ext |= IXGBE_CTRL_EXT_DRV_LOAD; 1141 IXGBE_WRITE_REG(hw, IXGBE_CTRL_EXT, ctrl_ext); 1142 1143 /* 1144 * Initialize the shared code 1145 */ 1146 if (ixgbe_init_shared_code(hw) != 0) { 1147 device_printf(dev, "Unable to initialize the shared code\n"); 1148 error = ENXIO; 1149 goto err_pci; 1150 } 1151 1152 if (hw->mac.type == ixgbe_mac_E610) 1153 ixgbe_init_aci(hw); 1154 1155 sc->do_debug_dump = false; 1156 1157 if (hw->mac.ops.fw_recovery_mode && 1158 hw->mac.ops.fw_recovery_mode(hw)) { 1159 device_printf(dev, 1160 "Firmware recovery mode detected. Limiting " 1161 "functionality.\nRefer to the Intel(R) Ethernet Adapters " 1162 "and Devices User Guide for details on firmware recovery " 1163 "mode."); 1164 error = ENOSYS; 1165 goto err_pci; 1166 } 1167 1168 /* 82598 Does not support SR-IOV, initialize everything else */ 1169 if (hw->mac.type >= ixgbe_mac_82599_vf) { 1170 for (i = 0; i < sc->num_vfs; i++) 1171 hw->mbx.ops[i].init_params(hw); 1172 } 1173 1174 hw->allow_unsupported_sfp = allow_unsupported_sfp; 1175 1176 if (hw->mac.type != ixgbe_mac_82598EB) 1177 hw->phy.smart_speed = ixgbe_smart_speed; 1178 1179 ixgbe_init_device_features(sc); 1180 1181 /* Verify adapter fan is still functional (if applicable) */ 1182 if (sc->feat_en & IXGBE_FEATURE_FAN_FAIL) { 1183 u32 esdp = IXGBE_READ_REG(hw, IXGBE_ESDP); 1184 ixgbe_check_fan_failure(sc, esdp, false); 1185 } 1186 1187 /* Ensure SW/FW semaphore is free */ 1188 ixgbe_init_swfw_semaphore(hw); 1189 1190 /* Enable EEE power saving */ 1191 if (sc->feat_en & IXGBE_FEATURE_EEE) 1192 hw->mac.ops.setup_eee(hw, true); 1193 1194 /* Set an initial default flow control value */ 1195 hw->fc.requested_mode = ixgbe_flow_control; 1196 1197 hw->phy.reset_if_overtemp = true; 1198 error = ixgbe_reset_hw(hw); 1199 hw->phy.reset_if_overtemp = false; 1200 if (error == IXGBE_ERR_SFP_NOT_PRESENT) { 1201 /* 1202 * No optics in this port, set up 1203 * so the timer routine will probe 1204 * for later insertion. 1205 */ 1206 sc->sfp_probe = true; 1207 error = 0; 1208 } else if (error == IXGBE_ERR_SFP_NOT_SUPPORTED) { 1209 device_printf(dev, "Unsupported SFP+ module detected!\n"); 1210 error = EIO; 1211 goto err_pci; 1212 } else if (error) { 1213 device_printf(dev, "Hardware initialization failed\n"); 1214 error = EIO; 1215 goto err_pci; 1216 } 1217 1218 /* Make sure we have a good EEPROM before we read from it */ 1219 if (ixgbe_validate_eeprom_checksum(&sc->hw, NULL) < 0) { 1220 device_printf(dev, "The EEPROM Checksum Is Not Valid\n"); 1221 error = EIO; 1222 goto err_pci; 1223 } 1224 1225 error = ixgbe_start_hw(hw); 1226 switch (error) { 1227 case IXGBE_ERR_EEPROM_VERSION: 1228 device_printf(dev, 1229 "This device is a pre-production adapter/LOM. Please be" 1230 " aware there may be issues associated with your" 1231 " hardware.\nIf you are experiencing problems please" 1232 " contact your Intel or hardware representative who" 1233 " provided you with this hardware.\n"); 1234 break; 1235 case IXGBE_ERR_SFP_NOT_SUPPORTED: 1236 device_printf(dev, "Unsupported SFP+ Module\n"); 1237 error = EIO; 1238 goto err_pci; 1239 case IXGBE_ERR_SFP_NOT_PRESENT: 1240 device_printf(dev, "No SFP+ Module found\n"); 1241 /* falls thru */ 1242 default: 1243 break; 1244 } 1245 1246 /* Check the FW API version and enable FW logging support for E610 */ 1247 if (hw->mac.type == ixgbe_mac_E610) { 1248 if (ixgbe_check_fw_api_version(sc)) { 1249 error = EIO; 1250 goto err_pci; 1251 } 1252 ixgbe_fwlog_set_support_ena(hw); 1253 } 1254 1255 /* Most of the iflib initialization... */ 1256 1257 iflib_set_mac(ctx, hw->mac.addr); 1258 switch (sc->hw.mac.type) { 1259 case ixgbe_mac_X550: 1260 case ixgbe_mac_X550EM_x: 1261 case ixgbe_mac_X550EM_a: 1262 scctx->isc_rss_table_size = 512; 1263 scctx->isc_ntxqsets_max = scctx->isc_nrxqsets_max = 64; 1264 break; 1265 default: 1266 scctx->isc_rss_table_size = 128; 1267 scctx->isc_ntxqsets_max = scctx->isc_nrxqsets_max = 16; 1268 } 1269 1270 /* Allow legacy interrupts */ 1271 ixgbe_txrx.ift_legacy_intr = ixgbe_intr; 1272 1273 scctx->isc_txqsizes[0] = 1274 roundup2(scctx->isc_ntxd[0] * sizeof(union ixgbe_adv_tx_desc) + 1275 sizeof(u32), DBA_ALIGN), 1276 scctx->isc_rxqsizes[0] = 1277 roundup2(scctx->isc_nrxd[0] * sizeof(union ixgbe_adv_rx_desc), 1278 DBA_ALIGN); 1279 1280 /* XXX */ 1281 scctx->isc_tx_csum_flags = CSUM_IP | CSUM_TCP | CSUM_UDP | CSUM_TSO | 1282 CSUM_IP6_TCP | CSUM_IP6_UDP | CSUM_IP6_TSO; 1283 if (sc->hw.mac.type == ixgbe_mac_82598EB) { 1284 scctx->isc_tx_nsegments = IXGBE_82598_SCATTER; 1285 } else { 1286 scctx->isc_tx_csum_flags |= CSUM_SCTP |CSUM_IP6_SCTP; 1287 scctx->isc_tx_nsegments = IXGBE_82599_SCATTER; 1288 } 1289 1290 scctx->isc_msix_bar = pci_msix_table_bar(dev); 1291 1292 scctx->isc_tx_tso_segments_max = scctx->isc_tx_nsegments; 1293 scctx->isc_tx_tso_size_max = IXGBE_TSO_SIZE; 1294 scctx->isc_tx_tso_segsize_max = PAGE_SIZE; 1295 1296 scctx->isc_txrx = &ixgbe_txrx; 1297 1298 scctx->isc_capabilities = scctx->isc_capenable = IXGBE_CAPS; 1299 ixgbe_configure_wakeup(ctx); 1300 1301 return (0); 1302 1303 err_pci: 1304 ctrl_ext = IXGBE_READ_REG(&sc->hw, IXGBE_CTRL_EXT); 1305 ctrl_ext &= ~IXGBE_CTRL_EXT_DRV_LOAD; 1306 IXGBE_WRITE_REG(&sc->hw, IXGBE_CTRL_EXT, ctrl_ext); 1307 ixgbe_free_pci_resources(ctx); 1308 1309 if (hw->mac.type == ixgbe_mac_E610) 1310 ixgbe_shutdown_aci(hw); 1311 1312 return (error); 1313 } /* ixgbe_if_attach_pre */ 1314 1315 /********************************************************************* 1316 * ixgbe_if_attach_post - Device initialization routine, part 2 1317 * 1318 * Called during driver load, but after interrupts and 1319 * resources have been allocated and configured. 1320 * Sets up some data structures not relevant to iflib. 1321 * 1322 * return 0 on success, positive on failure 1323 *********************************************************************/ 1324 static int 1325 ixgbe_if_attach_post(if_ctx_t ctx) 1326 { 1327 device_t dev; 1328 struct ixgbe_softc *sc; 1329 struct ixgbe_hw *hw; 1330 int error = 0; 1331 1332 dev = iflib_get_dev(ctx); 1333 sc = iflib_get_softc(ctx); 1334 hw = &sc->hw; 1335 ixgbe_init_iov_recovery(sc); 1336 1337 if (sc->intr_type == IFLIB_INTR_LEGACY && 1338 (sc->feat_cap & IXGBE_FEATURE_LEGACY_IRQ) == 0) { 1339 device_printf(dev, "Device does not support legacy interrupts"); 1340 error = ENXIO; 1341 goto err; 1342 } 1343 1344 /* Allocate multicast array memory. */ 1345 sc->mta = malloc(sizeof(*sc->mta) * MAX_NUM_MULTICAST_ADDRESSES, 1346 M_IXGBE, M_NOWAIT); 1347 if (sc->mta == NULL) { 1348 device_printf(dev, 1349 "Can not allocate multicast setup array\n"); 1350 error = ENOMEM; 1351 goto err; 1352 } 1353 1354 /* hw.ix defaults init */ 1355 ixgbe_set_advertise(sc, ixgbe_advertise_speed); 1356 1357 /* Enable the optics for 82599 SFP+ fiber */ 1358 ixgbe_enable_tx_laser(hw); 1359 1360 /* Enable power to the phy. */ 1361 ixgbe_set_phy_power(hw, true); 1362 1363 ixgbe_initialize_iov(sc); 1364 1365 error = ixgbe_setup_interface(ctx); 1366 if (error) { 1367 device_printf(dev, "Interface setup failed: %d\n", error); 1368 goto err; 1369 } 1370 1371 ixgbe_if_update_admin_status(ctx); 1372 1373 /* Initialize statistics */ 1374 ixgbe_update_stats_counters(sc); 1375 ixgbe_add_hw_stats(sc); 1376 1377 /* Check PCIE slot type/speed/width */ 1378 ixgbe_get_slot_info(sc); 1379 1380 /* 1381 * Do time init and sysctl init here, but 1382 * only on the first port of a bypass sc. 1383 */ 1384 ixgbe_bypass_init(sc); 1385 1386 /* Display NVM and Option ROM versions */ 1387 ixgbe_print_fw_version(ctx); 1388 1389 /* Set an initial dmac value */ 1390 sc->dmac = 0; 1391 /* Set initial advertised speeds (if applicable) */ 1392 sc->advertise = ixgbe_get_default_advertise(sc); 1393 1394 if (sc->feat_cap & IXGBE_FEATURE_SRIOV) 1395 ixgbe_define_iov_schemas(sc, &error); 1396 1397 /* Add sysctls */ 1398 ixgbe_add_device_sysctls(ctx); 1399 1400 /* Add MDIO bus if required / supported */ 1401 ixgbe_mdio_attach(sc); 1402 1403 /* Init recovery mode timer and state variable */ 1404 if (sc->feat_en & IXGBE_FEATURE_RECOVERY_MODE) { 1405 sc->recovery_mode = 0; 1406 1407 /* Set up the timer callout */ 1408 callout_init(&sc->fw_mode_timer, true); 1409 1410 /* Start the task */ 1411 callout_reset(&sc->fw_mode_timer, hz, ixgbe_fw_mode_timer, sc); 1412 } 1413 1414 return (0); 1415 err: 1416 return (error); 1417 } /* ixgbe_if_attach_post */ 1418 1419 /************************************************************************ 1420 * ixgbe_configure_wakeup 1421 * 1422 * Advertise the wake modes supported by this board and port. The NVM 1423 * APME setting selects the initial magic-packet policy. 1424 ************************************************************************/ 1425 static void 1426 ixgbe_configure_wakeup(if_ctx_t ctx) 1427 { 1428 struct ixgbe_softc *sc = iflib_get_softc(ctx); 1429 if_softc_ctx_t scctx = iflib_get_softc_ctx(ctx); 1430 struct ixgbe_hw *hw = &sc->hw; 1431 device_t dev = iflib_get_dev(ctx); 1432 u16 dev_caps = 0; 1433 u16 subdevice_id; 1434 u16 wol_cap; 1435 bool apme, supported; 1436 1437 supported = false; 1438 subdevice_id = hw->subsystem_device_id; 1439 if (hw->mac.ops.set_lan_id != NULL) 1440 hw->mac.ops.set_lan_id(hw); 1441 1442 /* X540 and newer advertise per-port WoL support in the NVM. */ 1443 if (hw->mac.type >= ixgbe_mac_X540) { 1444 if (ixgbe_get_device_caps(hw, &dev_caps) == IXGBE_SUCCESS) { 1445 wol_cap = dev_caps & IXGBE_DEVICE_CAPS_WOL_MASK; 1446 if (wol_cap == IXGBE_DEVICE_CAPS_WOL_PORT0_1 || 1447 (wol_cap == IXGBE_DEVICE_CAPS_WOL_PORT0 && 1448 hw->bus.func == 0)) 1449 supported = true; 1450 } 1451 } else if (hw->mac.type == ixgbe_mac_82599EB) { 1452 /* 82599 WoL support is board and, in some cases, port specific. */ 1453 switch (hw->device_id) { 1454 case IXGBE_DEV_ID_82599_SFP: 1455 switch (subdevice_id) { 1456 case IXGBE_SUBDEV_ID_82599_560FLR: 1457 case IXGBE_SUBDEV_ID_82599_LOM_SNAP6: 1458 case IXGBE_SUBDEV_ID_82599_SFP_WOL0: 1459 case IXGBE_SUBDEV_ID_82599_SFP_2OCP: 1460 supported = hw->bus.func == 0; 1461 break; 1462 case IXGBE_SUBDEV_ID_82599_SP_560FLR: 1463 case IXGBE_SUBDEV_ID_82599_SFP: 1464 case IXGBE_SUBDEV_ID_82599_RNDC: 1465 case IXGBE_SUBDEV_ID_82599_ECNA_DP: 1466 case IXGBE_SUBDEV_ID_82599_SFP_1OCP: 1467 case IXGBE_SUBDEV_ID_82599_SFP_LOM_OEM1: 1468 case IXGBE_SUBDEV_ID_82599_SFP_LOM_OEM2: 1469 supported = true; 1470 break; 1471 default: 1472 break; 1473 } 1474 break; 1475 case IXGBE_DEV_ID_82599EN_SFP: 1476 supported = 1477 subdevice_id == IXGBE_SUBDEV_ID_82599EN_SFP_OCP1; 1478 break; 1479 case IXGBE_DEV_ID_82599_COMBO_BACKPLANE: 1480 supported = 1481 subdevice_id != IXGBE_SUBDEV_ID_82599_KX4_KR_MEZZ; 1482 break; 1483 case IXGBE_DEV_ID_82599_KX4: 1484 supported = true; 1485 break; 1486 default: 1487 break; 1488 } 1489 } 1490 if (!pci_has_pme(dev, PCI_POWERSTATE_D3_HOT)) 1491 supported = false; 1492 apme = supported && 1493 (IXGBE_READ_REG(hw, IXGBE_GRC_BY_MAC(hw)) & IXGBE_GRC_APME) != 0; 1494 1495 scctx->isc_capabilities &= ~IFCAP_WOL; 1496 scctx->isc_capenable &= ~IFCAP_WOL; 1497 if (supported) { 1498 scctx->isc_capabilities |= IFCAP_WOL; 1499 if (apme) 1500 scctx->isc_capenable |= IFCAP_WOL_MAGIC; 1501 } 1502 1503 /* hw->wol_enabled describes the policy active in hardware, not support. */ 1504 hw->wol_enabled = false; 1505 sc->wol_filters = 0; 1506 } /* ixgbe_configure_wakeup */ 1507 1508 /************************************************************************ 1509 * ixgbe_setup_interface 1510 * 1511 * Setup networking device structure and register an interface. 1512 ************************************************************************/ 1513 static int 1514 ixgbe_setup_interface(if_ctx_t ctx) 1515 { 1516 if_t ifp = iflib_get_ifp(ctx); 1517 struct ixgbe_softc *sc = iflib_get_softc(ctx); 1518 1519 INIT_DEBUGOUT("ixgbe_setup_interface: begin"); 1520 1521 if_setbaudrate(ifp, IF_Gbps(10)); 1522 1523 sc->max_frame_size = if_getmtu(ifp) + ETHER_HDR_LEN + ETHER_CRC_LEN; 1524 1525 sc->phy_layer = ixgbe_get_supported_physical_layer(&sc->hw); 1526 1527 ixgbe_add_media_types(ctx); 1528 1529 /* Autoselect media by default */ 1530 ifmedia_set(sc->media, IFM_ETHER | IFM_AUTO); 1531 1532 return (0); 1533 } /* ixgbe_setup_interface */ 1534 1535 /************************************************************************ 1536 * ixgbe_if_get_counter 1537 ************************************************************************/ 1538 static uint64_t 1539 ixgbe_if_get_counter(if_ctx_t ctx, ift_counter cnt) 1540 { 1541 struct ixgbe_softc *sc = iflib_get_softc(ctx); 1542 if_t ifp = iflib_get_ifp(ctx); 1543 1544 switch (cnt) { 1545 case IFCOUNTER_IPACKETS: 1546 return (sc->ipackets); 1547 case IFCOUNTER_OPACKETS: 1548 return (sc->opackets); 1549 case IFCOUNTER_IBYTES: 1550 return (sc->ibytes); 1551 case IFCOUNTER_OBYTES: 1552 return (sc->obytes); 1553 case IFCOUNTER_IMCASTS: 1554 return (sc->imcasts); 1555 case IFCOUNTER_OMCASTS: 1556 return (sc->omcasts); 1557 case IFCOUNTER_COLLISIONS: 1558 return (0); 1559 case IFCOUNTER_IQDROPS: 1560 return (sc->iqdrops); 1561 case IFCOUNTER_IERRORS: 1562 return (sc->ierrors); 1563 default: 1564 return (if_get_counter_default(ifp, cnt)); 1565 } 1566 } /* ixgbe_if_get_counter */ 1567 1568 /************************************************************************ 1569 * ixgbe_if_i2c_req 1570 ************************************************************************/ 1571 static int 1572 ixgbe_if_i2c_req(if_ctx_t ctx, struct ifi2creq *req) 1573 { 1574 struct ixgbe_softc *sc = iflib_get_softc(ctx); 1575 struct ixgbe_hw *hw = &sc->hw; 1576 int i; 1577 1578 if (hw->phy.ops.read_i2c_byte == NULL) 1579 return (ENXIO); 1580 for (i = 0; i < req->len; i++) 1581 hw->phy.ops.read_i2c_byte(hw, req->offset + i, 1582 req->dev_addr, &req->data[i]); 1583 return (0); 1584 } /* ixgbe_if_i2c_req */ 1585 1586 /* ixgbe_if_needs_restart - Tell iflib when the driver needs to be 1587 * reinitialized 1588 * @ctx: iflib context 1589 * @event: event code to check 1590 * 1591 * Defaults to returning false for unknown events. 1592 * 1593 * @returns true if iflib needs to reinit the interface 1594 */ 1595 static bool 1596 ixgbe_if_needs_restart(if_ctx_t ctx __unused, enum iflib_restart_event event) 1597 { 1598 switch (event) { 1599 case IFLIB_RESTART_VLAN_CONFIG: 1600 default: 1601 return (false); 1602 } 1603 } 1604 1605 /************************************************************************ 1606 * ixgbe_if_priv_ioctl - Ioctl handler for driver 1607 * 1608 * Handler for custom driver specific ioctls 1609 * 1610 * return 0 on success, positive on failure 1611 ************************************************************************/ 1612 static int 1613 ixgbe_if_priv_ioctl(if_ctx_t ctx, u_long command, caddr_t data) 1614 { 1615 struct ixgbe_softc *sc = iflib_get_softc(ctx); 1616 struct ifdrv *ifd; 1617 device_t dev = sc->dev; 1618 1619 /* Make sure the command type is valid */ 1620 switch (command) { 1621 case SIOCSDRVSPEC: 1622 case SIOCGDRVSPEC: 1623 /* Accepted commands */ 1624 break; 1625 case SIOCGPRIVATE_0: 1626 /* 1627 * Although we do not support this ioctl command, it's expected 1628 * that iflib will forward it to the IFDI_PRIV_IOCTL handler. 1629 * Do not print a message in this case. 1630 */ 1631 return (ENOTSUP); 1632 default: 1633 /* 1634 * If we get a different command for this function, it's 1635 * definitely unexpected, so log a message indicating what 1636 * command we got for debugging purposes. 1637 */ 1638 device_printf(dev, 1639 "%s: unexpected ioctl command %08lx\n", 1640 __func__, command); 1641 return (EINVAL); 1642 } 1643 1644 ifd = (struct ifdrv *)data; 1645 1646 switch (ifd->ifd_cmd) { 1647 case IXGBE_NVM_ACCESS: 1648 IOCTL_DEBUGOUT("ioctl: NVM ACCESS"); 1649 return (ixgbe_nvm_access_ioctl(sc, ifd)); 1650 case IXGBE_DEBUG_DUMP: 1651 IOCTL_DEBUGOUT("ioctl: DEBUG DUMP"); 1652 return (ixgbe_debug_dump_ioctl(sc, ifd)); 1653 default: 1654 IOCTL_DEBUGOUT1( 1655 "ioctl: UNKNOWN SIOC(S|G)DRVSPEC (0x%X) command\n", 1656 (int)ifd->ifd_cmd); 1657 return (EINVAL); 1658 } 1659 1660 return (0); 1661 } 1662 1663 /************************************************************************ 1664 * ixgbe_nvm_access_ioctl 1665 * 1666 * Handles an NVM access ioctl request 1667 ************************************************************************/ 1668 static int 1669 ixgbe_nvm_access_ioctl(struct ixgbe_softc *sc, struct ifdrv *ifd) 1670 { 1671 struct ixgbe_nvm_access_data *data; 1672 struct ixgbe_nvm_access_cmd *cmd; 1673 struct ixgbe_hw *hw = &sc->hw; 1674 size_t ifd_len = ifd->ifd_len; 1675 size_t malloc_len; 1676 device_t dev = sc->dev; 1677 s32 status; 1678 u8 *nvm_buffer; 1679 int error = 0; 1680 1681 /* 1682 * ifioctl forwards SIOCxDRVSPEC to iflib without conducting 1683 * a privilege check. Subsequently, iflib passes the ioctl to the driver 1684 * without verifying privileges. To prevent non-privileged threads from 1685 * accessing this interface, perform a privilege check at this point. 1686 */ 1687 error = priv_check(curthread, PRIV_DRIVER); 1688 if (error) 1689 return (error); 1690 1691 if (ifd_len < sizeof(*cmd)) { 1692 device_printf(dev, 1693 "%s: ifdrv length is too small. Got %zu, " 1694 "but expected %zu\n", 1695 __func__, ifd_len, sizeof(*cmd)); 1696 return (EINVAL); 1697 } 1698 1699 if (ifd->ifd_data == NULL) { 1700 device_printf(dev, "%s: No ifd data buffer.\n", 1701 __func__); 1702 return (EINVAL); 1703 } 1704 1705 malloc_len = max(ifd_len, sizeof(*data) + sizeof(*cmd)); 1706 1707 nvm_buffer = (u8 *)malloc(malloc_len, M_IXGBE, M_ZERO | M_NOWAIT); 1708 if (!nvm_buffer) 1709 return (ENOMEM); 1710 1711 /* Copy the NVM access command and data in from user space */ 1712 error = copyin(ifd->ifd_data, nvm_buffer, ifd_len); 1713 if (error) { 1714 device_printf(dev, "%s: Failed to copy data in, error: %d\n", 1715 __func__, error); 1716 goto cleanup_free_nvm_buffer; 1717 } 1718 1719 /* 1720 * The NVM command structure is immediately followed by data which 1721 * varies in size based on the command. 1722 */ 1723 cmd = (struct ixgbe_nvm_access_cmd *)nvm_buffer; 1724 data = (struct ixgbe_nvm_access_data *) 1725 (nvm_buffer + sizeof(struct ixgbe_nvm_access_cmd)); 1726 1727 /* Handle the NVM access request */ 1728 status = ixgbe_handle_nvm_access(hw, cmd, data); 1729 if (status) { 1730 device_printf(dev, "%s: NVM access request failed, error %d\n", 1731 __func__, status); 1732 } 1733 1734 /* Copy the possibly modified contents of the handled request out */ 1735 error = copyout(nvm_buffer, ifd->ifd_data, ifd_len); 1736 if (error) { 1737 device_printf(dev, "%s: Copying response back to " 1738 "user space failed, error %d\n", 1739 __func__, error); 1740 goto cleanup_free_nvm_buffer; 1741 } 1742 1743 /* Convert private status to an error code for proper ioctl response */ 1744 switch (status) { 1745 case IXGBE_SUCCESS: 1746 error = 0; 1747 break; 1748 case IXGBE_ERR_OUT_OF_RANGE: 1749 error = ENOTTY; 1750 break; 1751 case IXGBE_ERR_PARAM: 1752 default: 1753 error = EINVAL; 1754 break; 1755 } 1756 1757 cleanup_free_nvm_buffer: 1758 free(nvm_buffer, M_IXGBE); 1759 return (error); 1760 } 1761 1762 /************************************************************************ 1763 * ixgbe_debug_dump_ioctl 1764 * 1765 * Makes debug dump of internal FW/HW data. 1766 ************************************************************************/ 1767 static int 1768 ixgbe_debug_dump_ioctl(struct ixgbe_softc *sc, struct ifdrv *ifd) 1769 { 1770 struct ixgbe_debug_dump_cmd *dd_cmd; 1771 struct ixgbe_hw *hw = &sc->hw; 1772 size_t ifd_len = ifd->ifd_len; 1773 device_t dev = sc->dev; 1774 s32 error = 0; 1775 1776 if (!(sc->feat_en & IXGBE_FEATURE_DBG_DUMP)) 1777 return (ENODEV); 1778 1779 /* Data returned from ACI command */ 1780 u16 ret_buf_size = 0; 1781 u16 ret_next_cluster = 0; 1782 u16 ret_next_table = 0; 1783 u32 ret_next_index = 0; 1784 1785 /* 1786 * ifioctl forwards SIOCxDRVSPEC to iflib without conducting 1787 * a privilege check. Subsequently, iflib passes the ioctl to the driver 1788 * without verifying privileges. To prevent non-privileged threads from 1789 * accessing this interface, perform a privilege check at this point. 1790 */ 1791 error = priv_check(curthread, PRIV_DRIVER); 1792 if (error) 1793 return (error); 1794 1795 if (ifd_len < sizeof(*dd_cmd)) { 1796 device_printf(dev, 1797 "%s: ifdrv length is too small. Got %zu, " 1798 "but expected %zu\n", 1799 __func__, ifd_len, sizeof(*dd_cmd)); 1800 return (EINVAL); 1801 } 1802 1803 if (ifd->ifd_data == NULL) { 1804 device_printf(dev, "%s: No ifd data buffer.\n", 1805 __func__); 1806 return (EINVAL); 1807 } 1808 1809 dd_cmd = (struct ixgbe_debug_dump_cmd *)malloc(ifd_len, M_IXGBE, 1810 M_NOWAIT | M_ZERO); 1811 if (!dd_cmd) { 1812 error = -ENOMEM; 1813 goto out; 1814 } 1815 /* copy data from userspace */ 1816 error = copyin(ifd->ifd_data, dd_cmd, ifd_len); 1817 if (error) { 1818 device_printf(dev, "%s: Failed to copy data in, error: %d\n", 1819 __func__, error); 1820 goto out; 1821 } 1822 1823 /* ACI command requires buf_size arg to be grater than 0 */ 1824 if (dd_cmd->data_size == 0) { 1825 device_printf(dev, "%s: data_size must be greater than 0\n", 1826 __func__); 1827 error = EINVAL; 1828 goto out; 1829 } 1830 1831 /* Zero the data buffer memory space */ 1832 memset(dd_cmd->data, 0, ifd_len - sizeof(*dd_cmd)); 1833 1834 error = ixgbe_aci_get_internal_data(hw, dd_cmd->cluster_id, 1835 dd_cmd->table_id, dd_cmd->offset, dd_cmd->data, dd_cmd->data_size, 1836 &ret_buf_size, &ret_next_cluster, &ret_next_table, &ret_next_index); 1837 if (error) { 1838 device_printf(dev, 1839 "%s: Failed to get internal FW/HW data, error: %d\n", 1840 __func__, error); 1841 goto out; 1842 } 1843 1844 dd_cmd->cluster_id = ret_next_cluster; 1845 dd_cmd->table_id = ret_next_table; 1846 dd_cmd->offset = ret_next_index; 1847 dd_cmd->data_size = ret_buf_size; 1848 1849 error = copyout(dd_cmd, ifd->ifd_data, ifd->ifd_len); 1850 if (error) { 1851 device_printf(dev, 1852 "%s: Failed to copy data out, error: %d\n", 1853 __func__, error); 1854 } 1855 1856 out: 1857 free(dd_cmd, M_IXGBE); 1858 1859 return (error); 1860 } 1861 1862 /************************************************************************ 1863 * ixgbe_add_media_types 1864 ************************************************************************/ 1865 static void 1866 ixgbe_add_media_types(if_ctx_t ctx) 1867 { 1868 struct ixgbe_softc *sc = iflib_get_softc(ctx); 1869 struct ixgbe_hw *hw = &sc->hw; 1870 device_t dev = iflib_get_dev(ctx); 1871 u64 layer; 1872 1873 layer = sc->phy_layer = ixgbe_get_supported_physical_layer(hw); 1874 1875 /* Media types with matching FreeBSD media defines */ 1876 if (layer & IXGBE_PHYSICAL_LAYER_10GBASE_T) 1877 ifmedia_add(sc->media, IFM_ETHER | IFM_10G_T, 0, NULL); 1878 if (layer & IXGBE_PHYSICAL_LAYER_5000BASE_T) 1879 ifmedia_add(sc->media, IFM_ETHER | IFM_5000_T, 0, NULL); 1880 if (layer & IXGBE_PHYSICAL_LAYER_2500BASE_T) 1881 ifmedia_add(sc->media, IFM_ETHER | IFM_2500_T, 0, NULL); 1882 if (layer & IXGBE_PHYSICAL_LAYER_1000BASE_T) 1883 ifmedia_add(sc->media, IFM_ETHER | IFM_1000_T, 0, NULL); 1884 if (layer & IXGBE_PHYSICAL_LAYER_100BASE_TX) 1885 ifmedia_add(sc->media, IFM_ETHER | IFM_100_TX, 0, NULL); 1886 if (layer & IXGBE_PHYSICAL_LAYER_10BASE_T) 1887 ifmedia_add(sc->media, IFM_ETHER | IFM_10_T, 0, NULL); 1888 1889 if (hw->mac.type == ixgbe_mac_X550) { 1890 ifmedia_add(sc->media, IFM_ETHER | IFM_2500_T, 0, NULL); 1891 ifmedia_add(sc->media, IFM_ETHER | IFM_5000_T, 0, NULL); 1892 } 1893 1894 if (layer & IXGBE_PHYSICAL_LAYER_SFP_PLUS_CU || 1895 layer & IXGBE_PHYSICAL_LAYER_SFP_ACTIVE_DA) { 1896 ifmedia_add(sc->media, IFM_ETHER | IFM_10G_TWINAX, 0, 1897 NULL); 1898 ifmedia_add(sc->media, IFM_ETHER | IFM_1000_KX, 0, NULL); 1899 } 1900 1901 if (layer & IXGBE_PHYSICAL_LAYER_10GBASE_LR) { 1902 ifmedia_add(sc->media, IFM_ETHER | IFM_10G_LR, 0, NULL); 1903 if (hw->phy.multispeed_fiber) 1904 ifmedia_add(sc->media, IFM_ETHER | IFM_1000_LX, 0, 1905 NULL); 1906 } 1907 if (layer & IXGBE_PHYSICAL_LAYER_10GBASE_BX) { 1908 device_printf(dev, "Media supported: 10Gbase-BX\n"); 1909 ifmedia_add(sc->media, IFM_ETHER | IFM_10G_BX, 0, NULL); 1910 } 1911 if (layer & IXGBE_PHYSICAL_LAYER_10GBASE_SR) { 1912 ifmedia_add(sc->media, IFM_ETHER | IFM_10G_SR, 0, NULL); 1913 if (hw->phy.multispeed_fiber) 1914 ifmedia_add(sc->media, IFM_ETHER | IFM_1000_SX, 0, 1915 NULL); 1916 } else if (layer & IXGBE_PHYSICAL_LAYER_1000BASE_SX) 1917 ifmedia_add(sc->media, IFM_ETHER | IFM_1000_SX, 0, NULL); 1918 if (layer & IXGBE_PHYSICAL_LAYER_10GBASE_CX4) 1919 ifmedia_add(sc->media, IFM_ETHER | IFM_10G_CX4, 0, NULL); 1920 1921 #ifdef IFM_ETH_XTYPE 1922 if (layer & IXGBE_PHYSICAL_LAYER_10GBASE_KR) 1923 ifmedia_add(sc->media, IFM_ETHER | IFM_10G_KR, 0, NULL); 1924 if (layer & IXGBE_PHYSICAL_LAYER_10GBASE_KX4) 1925 ifmedia_add( sc->media, IFM_ETHER | IFM_10G_KX4, 0, NULL); 1926 if (layer & IXGBE_PHYSICAL_LAYER_1000BASE_KX) 1927 ifmedia_add(sc->media, IFM_ETHER | IFM_1000_KX, 0, NULL); 1928 if (layer & IXGBE_PHYSICAL_LAYER_2500BASE_KX) 1929 ifmedia_add(sc->media, IFM_ETHER | IFM_2500_KX, 0, NULL); 1930 #else 1931 if (layer & IXGBE_PHYSICAL_LAYER_10GBASE_KR) { 1932 device_printf(dev, "Media supported: 10GbaseKR\n"); 1933 device_printf(dev, "10GbaseKR mapped to 10GbaseSR\n"); 1934 ifmedia_add(sc->media, IFM_ETHER | IFM_10G_SR, 0, NULL); 1935 } 1936 if (layer & IXGBE_PHYSICAL_LAYER_10GBASE_KX4) { 1937 device_printf(dev, "Media supported: 10GbaseKX4\n"); 1938 device_printf(dev, "10GbaseKX4 mapped to 10GbaseCX4\n"); 1939 ifmedia_add(sc->media, IFM_ETHER | IFM_10G_CX4, 0, NULL); 1940 } 1941 if (layer & IXGBE_PHYSICAL_LAYER_1000BASE_KX) { 1942 device_printf(dev, "Media supported: 1000baseKX\n"); 1943 device_printf(dev, "1000baseKX mapped to 1000baseCX\n"); 1944 ifmedia_add(sc->media, IFM_ETHER | IFM_1000_CX, 0, NULL); 1945 } 1946 if (layer & IXGBE_PHYSICAL_LAYER_2500BASE_KX) { 1947 device_printf(dev, "Media supported: 2500baseKX\n"); 1948 device_printf(dev, "2500baseKX mapped to 2500baseSX\n"); 1949 ifmedia_add(sc->media, IFM_ETHER | IFM_2500_SX, 0, NULL); 1950 } 1951 #endif 1952 if (layer & IXGBE_PHYSICAL_LAYER_1000BASE_BX) { 1953 device_printf(dev, "Media supported: 1000baseBX\n"); 1954 ifmedia_add(sc->media, IFM_ETHER | IFM_1000_BX, 0, NULL); 1955 } 1956 1957 if (hw->device_id == IXGBE_DEV_ID_82598AT) { 1958 ifmedia_add(sc->media, IFM_ETHER | IFM_1000_T | IFM_FDX, 1959 0, NULL); 1960 ifmedia_add(sc->media, IFM_ETHER | IFM_1000_T, 0, NULL); 1961 } 1962 1963 ifmedia_add(sc->media, IFM_ETHER | IFM_AUTO, 0, NULL); 1964 } /* ixgbe_add_media_types */ 1965 1966 /************************************************************************ 1967 * ixgbe_is_sfp 1968 ************************************************************************/ 1969 static inline bool 1970 ixgbe_is_sfp(struct ixgbe_hw *hw) 1971 { 1972 switch (hw->mac.type) { 1973 case ixgbe_mac_82598EB: 1974 if (hw->phy.type == ixgbe_phy_nl) 1975 return (true); 1976 return (false); 1977 case ixgbe_mac_82599EB: 1978 switch (hw->mac.ops.get_media_type(hw)) { 1979 case ixgbe_media_type_fiber: 1980 case ixgbe_media_type_fiber_qsfp: 1981 return (true); 1982 default: 1983 return (false); 1984 } 1985 case ixgbe_mac_X550EM_x: 1986 case ixgbe_mac_X550EM_a: 1987 case ixgbe_mac_E610: 1988 if (hw->mac.ops.get_media_type(hw) == ixgbe_media_type_fiber) 1989 return (true); 1990 return (false); 1991 default: 1992 return (false); 1993 } 1994 } /* ixgbe_is_sfp */ 1995 1996 /************************************************************************ 1997 * ixgbe_config_link 1998 ************************************************************************/ 1999 static void 2000 ixgbe_config_link(if_ctx_t ctx) 2001 { 2002 struct ixgbe_softc *sc = iflib_get_softc(ctx); 2003 struct ixgbe_hw *hw = &sc->hw; 2004 u32 autoneg, err = 0; 2005 bool sfp, negotiate; 2006 2007 sfp = ixgbe_is_sfp(hw); 2008 2009 if (sfp) { 2010 /* ixgbe_if_stop() disables it on every 82599 SFP port. */ 2011 ixgbe_enable_tx_laser(hw); 2012 atomic_set_32(&sc->task_requests, IXGBE_REQUEST_TASK_MOD); 2013 iflib_admin_intr_deferred(ctx); 2014 } else { 2015 if (hw->mac.ops.check_link) 2016 err = ixgbe_check_link(hw, &sc->link_speed, 2017 &sc->link_up, false); 2018 if (err) 2019 return; 2020 autoneg = hw->phy.autoneg_advertised; 2021 if ((!autoneg) && (hw->mac.ops.get_link_capabilities)) 2022 err = hw->mac.ops.get_link_capabilities(hw, &autoneg, 2023 &negotiate); 2024 if (err) 2025 return; 2026 2027 if (hw->mac.type == ixgbe_mac_X550 && 2028 hw->phy.autoneg_advertised == 0) { 2029 /* 2030 * 2.5G and 5G autonegotiation speeds on X550 2031 * are disabled by default due to reported 2032 * interoperability issues with some switches. 2033 * 2034 * The second condition checks if any operations 2035 * involving setting autonegotiation speeds have 2036 * been performed prior to this ixgbe_config_link() 2037 * call. 2038 * 2039 * If hw->phy.autoneg_advertised does not 2040 * equal 0, this means that the user might have 2041 * set autonegotiation speeds via the sysctl 2042 * before bringing the interface up. In this 2043 * case, we should not disable 2.5G and 5G 2044 * since that speeds might be selected by the 2045 * user. 2046 * 2047 * Otherwise (i.e. if hw->phy.autoneg_advertised 2048 * is set to 0), it is the first time we set 2049 * autonegotiation preferences and the default 2050 * set of speeds should exclude 2.5G and 5G. 2051 */ 2052 autoneg &= ~(IXGBE_LINK_SPEED_2_5GB_FULL | 2053 IXGBE_LINK_SPEED_5GB_FULL); 2054 } 2055 2056 if (hw->mac.type == ixgbe_mac_E610) { 2057 hw->phy.ops.init(hw); 2058 err = ixgbe_enable_lse(sc); 2059 if (err) 2060 device_printf(sc->dev, 2061 "Failed to enable Link Status Event, " 2062 "error: %d", err); 2063 } 2064 2065 if (hw->mac.ops.setup_link) 2066 err = hw->mac.ops.setup_link(hw, autoneg, 2067 sc->link_up); 2068 } 2069 } /* ixgbe_config_link */ 2070 2071 /************************************************************************ 2072 * ixgbe_update_stats_counters - Update board statistics counters. 2073 ************************************************************************/ 2074 static void 2075 ixgbe_update_stats_counters(struct ixgbe_softc *sc) 2076 { 2077 struct ixgbe_hw *hw = &sc->hw; 2078 struct ixgbe_hw_stats *stats = &sc->stats.pf; 2079 u32 missed_rx = 0, mpc, bprc, lxon, lxoff; 2080 u32 lxoffrxc; 2081 u64 total_missed_rx = 0, total; 2082 2083 stats->crcerrs += IXGBE_READ_REG(hw, IXGBE_CRCERRS); 2084 stats->illerrc += IXGBE_READ_REG(hw, IXGBE_ILLERRC); 2085 stats->errbc += IXGBE_READ_REG(hw, IXGBE_ERRBC); 2086 stats->mspdc += IXGBE_READ_REG(hw, IXGBE_MSPDC); 2087 for (int i = 0; i < nitems(stats->mpc); i++) { 2088 mpc = IXGBE_READ_REG(hw, IXGBE_MPC(i)); 2089 missed_rx += mpc; 2090 stats->mpc[i] += mpc; 2091 total_missed_rx += stats->mpc[i]; 2092 } 2093 stats->mpctotal = total_missed_rx; 2094 2095 for (int i = 0; i < 16; i++) { 2096 stats->qprc[i] += IXGBE_READ_REG(hw, IXGBE_QPRC(i)); 2097 stats->qptc[i] += IXGBE_READ_REG(hw, IXGBE_QPTC(i)); 2098 stats->qprdc[i] += IXGBE_READ_REG(hw, IXGBE_QPRDC(i)); 2099 } 2100 stats->mlfc += IXGBE_READ_REG(hw, IXGBE_MLFC); 2101 stats->mrfc += IXGBE_READ_REG(hw, IXGBE_MRFC); 2102 stats->rlec += IXGBE_READ_REG(hw, IXGBE_RLEC); 2103 2104 /* Hardware workaround, gprc counts missed packets */ 2105 stats->gprc += IXGBE_READ_REG(hw, IXGBE_GPRC); 2106 stats->gprc -= missed_rx; 2107 2108 if (hw->mac.type != ixgbe_mac_82598EB) { 2109 stats->gorc += IXGBE_READ_REG(hw, IXGBE_GORCL) + 2110 ((u64)IXGBE_READ_REG(hw, IXGBE_GORCH) << 32); 2111 stats->gotc += IXGBE_READ_REG(hw, IXGBE_GOTCL) + 2112 ((u64)IXGBE_READ_REG(hw, IXGBE_GOTCH) << 32); 2113 stats->tor += IXGBE_READ_REG(hw, IXGBE_TORL) + 2114 ((u64)IXGBE_READ_REG(hw, IXGBE_TORH) << 32); 2115 stats->lxonrxc += IXGBE_READ_REG(hw, IXGBE_LXONRXCNT); 2116 lxoffrxc = IXGBE_READ_REG(hw, IXGBE_LXOFFRXCNT); 2117 stats->lxoffrxc += lxoffrxc; 2118 } else { 2119 stats->lxonrxc += IXGBE_READ_REG(hw, IXGBE_LXONRXC); 2120 lxoffrxc = IXGBE_READ_REG(hw, IXGBE_LXOFFRXC); 2121 stats->lxoffrxc += lxoffrxc; 2122 /* 82598 only has a counter in the high register */ 2123 stats->gorc += IXGBE_READ_REG(hw, IXGBE_GORCH); 2124 stats->gotc += IXGBE_READ_REG(hw, IXGBE_GOTCH); 2125 stats->tor += IXGBE_READ_REG(hw, IXGBE_TORH); 2126 } 2127 2128 /* 2129 * For watchdog management we need to know if we have been paused 2130 * during the last interval, so capture that here. 2131 */ 2132 if (lxoffrxc) 2133 sc->shared->isc_pause_frames = 1; 2134 2135 /* 2136 * Workaround: mprc hardware is incorrectly counting 2137 * broadcasts, so for now we subtract those. 2138 */ 2139 bprc = IXGBE_READ_REG(hw, IXGBE_BPRC); 2140 stats->bprc += bprc; 2141 stats->mprc += IXGBE_READ_REG(hw, IXGBE_MPRC); 2142 if (hw->mac.type == ixgbe_mac_82598EB) 2143 stats->mprc -= bprc; 2144 2145 stats->prc64 += IXGBE_READ_REG(hw, IXGBE_PRC64); 2146 stats->prc127 += IXGBE_READ_REG(hw, IXGBE_PRC127); 2147 stats->prc255 += IXGBE_READ_REG(hw, IXGBE_PRC255); 2148 stats->prc511 += IXGBE_READ_REG(hw, IXGBE_PRC511); 2149 stats->prc1023 += IXGBE_READ_REG(hw, IXGBE_PRC1023); 2150 stats->prc1522 += IXGBE_READ_REG(hw, IXGBE_PRC1522); 2151 2152 lxon = IXGBE_READ_REG(hw, IXGBE_LXONTXC); 2153 stats->lxontxc += lxon; 2154 lxoff = IXGBE_READ_REG(hw, IXGBE_LXOFFTXC); 2155 stats->lxofftxc += lxoff; 2156 total = (u64)lxon + lxoff; 2157 2158 stats->gptc += IXGBE_READ_REG(hw, IXGBE_GPTC); 2159 stats->mptc += IXGBE_READ_REG(hw, IXGBE_MPTC); 2160 stats->ptc64 += IXGBE_READ_REG(hw, IXGBE_PTC64); 2161 stats->gptc -= total; 2162 stats->mptc -= total; 2163 stats->ptc64 -= total; 2164 stats->gotc -= total * ETHER_MIN_LEN; 2165 2166 stats->ruc += IXGBE_READ_REG(hw, IXGBE_RUC); 2167 stats->rfc += IXGBE_READ_REG(hw, IXGBE_RFC); 2168 stats->roc += IXGBE_READ_REG(hw, IXGBE_ROC); 2169 stats->rjc += IXGBE_READ_REG(hw, IXGBE_RJC); 2170 stats->mngprc += IXGBE_READ_REG(hw, IXGBE_MNGPRC); 2171 stats->mngpdc += IXGBE_READ_REG(hw, IXGBE_MNGPDC); 2172 stats->mngptc += IXGBE_READ_REG(hw, IXGBE_MNGPTC); 2173 stats->tpr += IXGBE_READ_REG(hw, IXGBE_TPR); 2174 stats->tpt += IXGBE_READ_REG(hw, IXGBE_TPT); 2175 stats->ptc127 += IXGBE_READ_REG(hw, IXGBE_PTC127); 2176 stats->ptc255 += IXGBE_READ_REG(hw, IXGBE_PTC255); 2177 stats->ptc511 += IXGBE_READ_REG(hw, IXGBE_PTC511); 2178 stats->ptc1023 += IXGBE_READ_REG(hw, IXGBE_PTC1023); 2179 stats->ptc1522 += IXGBE_READ_REG(hw, IXGBE_PTC1522); 2180 stats->bptc += IXGBE_READ_REG(hw, IXGBE_BPTC); 2181 stats->xec += IXGBE_READ_REG(hw, IXGBE_XEC); 2182 stats->fccrc += IXGBE_READ_REG(hw, IXGBE_FCCRC); 2183 stats->fclast += IXGBE_READ_REG(hw, IXGBE_FCLAST); 2184 /* Only read FCOE on 82599 */ 2185 if (hw->mac.type != ixgbe_mac_82598EB) { 2186 stats->fcoerpdc += IXGBE_READ_REG(hw, IXGBE_FCOERPDC); 2187 stats->fcoeprc += IXGBE_READ_REG(hw, IXGBE_FCOEPRC); 2188 stats->fcoeptc += IXGBE_READ_REG(hw, IXGBE_FCOEPTC); 2189 stats->fcoedwrc += IXGBE_READ_REG(hw, IXGBE_FCOEDWRC); 2190 stats->fcoedwtc += IXGBE_READ_REG(hw, IXGBE_FCOEDWTC); 2191 } 2192 2193 /* TLPIC and RLPIC are clear-on-read. */ 2194 if (sc->feat_cap & IXGBE_FEATURE_EEE) { 2195 stats->tlpic += IXGBE_READ_REG(hw, IXGBE_TLPIC); 2196 stats->rlpic += IXGBE_READ_REG(hw, IXGBE_RLPIC); 2197 } 2198 2199 /* Fill out the OS statistics structure */ 2200 IXGBE_SET_IPACKETS(sc, stats->gprc); 2201 IXGBE_SET_OPACKETS(sc, stats->gptc); 2202 IXGBE_SET_IBYTES(sc, stats->gorc); 2203 IXGBE_SET_OBYTES(sc, stats->gotc); 2204 IXGBE_SET_IMCASTS(sc, stats->mprc); 2205 IXGBE_SET_OMCASTS(sc, stats->mptc); 2206 IXGBE_SET_COLLISIONS(sc, 0); 2207 IXGBE_SET_IQDROPS(sc, total_missed_rx); 2208 2209 /* 2210 * Aggregate following types of errors as RX errors: 2211 * - CRC error count, 2212 * - illegal byte error count, 2213 * - missed packets count, 2214 * - length error count, 2215 * - undersized packets count, 2216 * - fragmented packets count, 2217 * - oversized packets count, 2218 * - jabber count. 2219 */ 2220 IXGBE_SET_IERRORS(sc, stats->crcerrs + stats->illerrc + 2221 stats->mpctotal + stats->rlec + stats->ruc + stats->rfc + 2222 stats->roc + stats->rjc); 2223 } /* ixgbe_update_stats_counters */ 2224 2225 /************************************************************************ 2226 * ixgbe_add_hw_stats 2227 * 2228 * Add sysctl variables, one per statistic, to the system. 2229 ************************************************************************/ 2230 static void 2231 ixgbe_add_hw_stats(struct ixgbe_softc *sc) 2232 { 2233 device_t dev = iflib_get_dev(sc->ctx); 2234 struct ix_rx_queue *rx_que; 2235 struct ix_tx_queue *tx_que; 2236 struct sysctl_ctx_list *ctx = device_get_sysctl_ctx(dev); 2237 struct sysctl_oid *tree = device_get_sysctl_tree(dev); 2238 struct sysctl_oid_list *child = SYSCTL_CHILDREN(tree); 2239 struct ixgbe_hw_stats *stats = &sc->stats.pf; 2240 struct sysctl_oid *stat_node, *queue_node; 2241 struct sysctl_oid_list *stat_list, *queue_list; 2242 int i; 2243 2244 #define QUEUE_NAME_LEN 32 2245 char namebuf[QUEUE_NAME_LEN]; 2246 2247 /* Driver Statistics */ 2248 SYSCTL_ADD_ULONG(ctx, child, OID_AUTO, "dropped", 2249 CTLFLAG_RD, &sc->dropped_pkts, "Driver dropped packets"); 2250 SYSCTL_ADD_ULONG(ctx, child, OID_AUTO, "link_irq", 2251 CTLFLAG_RD, &sc->link_irq, "Link MSI-X IRQ Handled"); 2252 2253 for (i = 0, tx_que = sc->tx_queues; i < sc->num_tx_queues; 2254 i++, tx_que++) { 2255 struct tx_ring *txr = &tx_que->txr; 2256 snprintf(namebuf, QUEUE_NAME_LEN, "queue%d", i); 2257 queue_node = SYSCTL_ADD_NODE(ctx, child, OID_AUTO, namebuf, 2258 CTLFLAG_RD | CTLFLAG_MPSAFE, NULL, "Queue Name"); 2259 queue_list = SYSCTL_CHILDREN(queue_node); 2260 2261 SYSCTL_ADD_PROC(ctx, queue_list, OID_AUTO, "txd_head", 2262 CTLTYPE_UINT | CTLFLAG_RD, txr, 0, 2263 ixgbe_sysctl_tdh_handler, "IU", 2264 "Transmit Descriptor Head"); 2265 SYSCTL_ADD_PROC(ctx, queue_list, OID_AUTO, "txd_tail", 2266 CTLTYPE_UINT | CTLFLAG_RD, txr, 0, 2267 ixgbe_sysctl_tdt_handler, "IU", 2268 "Transmit Descriptor Tail"); 2269 SYSCTL_ADD_UQUAD(ctx, queue_list, OID_AUTO, "tso_tx", 2270 CTLFLAG_RD, &txr->tso_tx, "TSO"); 2271 SYSCTL_ADD_UQUAD(ctx, queue_list, OID_AUTO, "tx_packets", 2272 CTLFLAG_RD, &txr->total_packets, 2273 "Queue Packets Transmitted"); 2274 } 2275 2276 for (i = 0, rx_que = sc->rx_queues; i < sc->num_rx_queues; 2277 i++, rx_que++) { 2278 struct rx_ring *rxr = &rx_que->rxr; 2279 snprintf(namebuf, QUEUE_NAME_LEN, "queue%d", i); 2280 queue_node = SYSCTL_ADD_NODE(ctx, child, OID_AUTO, namebuf, 2281 CTLFLAG_RD | CTLFLAG_MPSAFE, NULL, "Queue Name"); 2282 queue_list = SYSCTL_CHILDREN(queue_node); 2283 2284 SYSCTL_ADD_PROC(ctx, queue_list, OID_AUTO, "interrupt_rate", 2285 CTLTYPE_UINT | CTLFLAG_RW, 2286 &sc->rx_queues[i], 0, 2287 ixgbe_sysctl_interrupt_rate_handler, "IU", 2288 "Interrupt Rate"); 2289 SYSCTL_ADD_UQUAD(ctx, queue_list, OID_AUTO, "irqs", 2290 CTLFLAG_RD, &(sc->rx_queues[i].irqs), 2291 "irqs on this queue"); 2292 SYSCTL_ADD_PROC(ctx, queue_list, OID_AUTO, "rxd_head", 2293 CTLTYPE_UINT | CTLFLAG_RD, rxr, 0, 2294 ixgbe_sysctl_rdh_handler, "IU", 2295 "Receive Descriptor Head"); 2296 SYSCTL_ADD_PROC(ctx, queue_list, OID_AUTO, "rxd_tail", 2297 CTLTYPE_UINT | CTLFLAG_RD, rxr, 0, 2298 ixgbe_sysctl_rdt_handler, "IU", 2299 "Receive Descriptor Tail"); 2300 SYSCTL_ADD_UQUAD(ctx, queue_list, OID_AUTO, "rx_packets", 2301 CTLFLAG_RD, &rxr->rx_packets, "Queue Packets Received"); 2302 SYSCTL_ADD_UQUAD(ctx, queue_list, OID_AUTO, "rx_bytes", 2303 CTLFLAG_RD, &rxr->rx_bytes, "Queue Bytes Received"); 2304 SYSCTL_ADD_UQUAD(ctx, queue_list, OID_AUTO, "rx_copies", 2305 CTLFLAG_RD, &rxr->rx_copies, "Copied RX Frames"); 2306 SYSCTL_ADD_UQUAD(ctx, queue_list, OID_AUTO, "rx_discarded", 2307 CTLFLAG_RD, &rxr->rx_discarded, "Discarded RX packets"); 2308 } 2309 2310 /* MAC stats get their own sub node */ 2311 stat_node = SYSCTL_ADD_NODE(ctx, child, OID_AUTO, "mac_stats", 2312 CTLFLAG_RD | CTLFLAG_MPSAFE, NULL, "MAC Statistics"); 2313 stat_list = SYSCTL_CHILDREN(stat_node); 2314 2315 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "rx_errs", 2316 CTLFLAG_RD, &sc->ierrors, IXGBE_SYSCTL_DESC_RX_ERRS); 2317 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "crc_errs", 2318 CTLFLAG_RD, &stats->crcerrs, "CRC Errors"); 2319 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "ill_errs", 2320 CTLFLAG_RD, &stats->illerrc, "Illegal Byte Errors"); 2321 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "byte_errs", 2322 CTLFLAG_RD, &stats->errbc, "Byte Errors"); 2323 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "short_discards", 2324 CTLFLAG_RD, &stats->mspdc, "MAC Short Packets Discarded"); 2325 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "local_faults", 2326 CTLFLAG_RD, &stats->mlfc, "MAC Local Faults"); 2327 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "remote_faults", 2328 CTLFLAG_RD, &stats->mrfc, "MAC Remote Faults"); 2329 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "rec_len_errs", 2330 CTLFLAG_RD, &stats->rlec, "Receive Length Errors"); 2331 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "rx_missed_packets", 2332 CTLFLAG_RD, &stats->mpctotal, "RX Missed Packet Count"); 2333 2334 /* Flow Control stats */ 2335 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "xon_txd", 2336 CTLFLAG_RD, &stats->lxontxc, "Link XON Transmitted"); 2337 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "xon_recvd", 2338 CTLFLAG_RD, &stats->lxonrxc, "Link XON Received"); 2339 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "xoff_txd", 2340 CTLFLAG_RD, &stats->lxofftxc, "Link XOFF Transmitted"); 2341 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "xoff_recvd", 2342 CTLFLAG_RD, &stats->lxoffrxc, "Link XOFF Received"); 2343 2344 /* Packet Reception Stats */ 2345 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "total_octets_rcvd", 2346 CTLFLAG_RD, &stats->tor, "Total Octets Received"); 2347 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "good_octets_rcvd", 2348 CTLFLAG_RD, &stats->gorc, "Good Octets Received"); 2349 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "total_pkts_rcvd", 2350 CTLFLAG_RD, &stats->tpr, "Total Packets Received"); 2351 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "good_pkts_rcvd", 2352 CTLFLAG_RD, &stats->gprc, "Good Packets Received"); 2353 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "mcast_pkts_rcvd", 2354 CTLFLAG_RD, &stats->mprc, "Multicast Packets Received"); 2355 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "bcast_pkts_rcvd", 2356 CTLFLAG_RD, &stats->bprc, "Broadcast Packets Received"); 2357 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "rx_frames_64", 2358 CTLFLAG_RD, &stats->prc64, "64 byte frames received "); 2359 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "rx_frames_65_127", 2360 CTLFLAG_RD, &stats->prc127, "65-127 byte frames received"); 2361 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "rx_frames_128_255", 2362 CTLFLAG_RD, &stats->prc255, "128-255 byte frames received"); 2363 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "rx_frames_256_511", 2364 CTLFLAG_RD, &stats->prc511, "256-511 byte frames received"); 2365 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "rx_frames_512_1023", 2366 CTLFLAG_RD, &stats->prc1023, "512-1023 byte frames received"); 2367 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "rx_frames_1024_1522", 2368 CTLFLAG_RD, &stats->prc1522, "1023-1522 byte frames received"); 2369 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "recv_undersized", 2370 CTLFLAG_RD, &stats->ruc, "Receive Undersized"); 2371 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "recv_fragmented", 2372 CTLFLAG_RD, &stats->rfc, "Fragmented Packets Received "); 2373 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "recv_oversized", 2374 CTLFLAG_RD, &stats->roc, "Oversized Packets Received"); 2375 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "recv_jabberd", 2376 CTLFLAG_RD, &stats->rjc, "Received Jabber"); 2377 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "management_pkts_rcvd", 2378 CTLFLAG_RD, &stats->mngprc, "Management Packets Received"); 2379 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "management_pkts_drpd", 2380 CTLFLAG_RD, &stats->mngpdc, "Management Packets Dropped"); 2381 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "checksum_errs", 2382 CTLFLAG_RD, &stats->xec, "Checksum Errors"); 2383 2384 /* Packet Transmission Stats */ 2385 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "good_octets_txd", 2386 CTLFLAG_RD, &stats->gotc, "Good Octets Transmitted"); 2387 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "total_pkts_txd", 2388 CTLFLAG_RD, &stats->tpt, "Total Packets Transmitted"); 2389 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "good_pkts_txd", 2390 CTLFLAG_RD, &stats->gptc, "Good Packets Transmitted"); 2391 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "bcast_pkts_txd", 2392 CTLFLAG_RD, &stats->bptc, "Broadcast Packets Transmitted"); 2393 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "mcast_pkts_txd", 2394 CTLFLAG_RD, &stats->mptc, "Multicast Packets Transmitted"); 2395 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "management_pkts_txd", 2396 CTLFLAG_RD, &stats->mngptc, "Management Packets Transmitted"); 2397 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "tx_frames_64", 2398 CTLFLAG_RD, &stats->ptc64, "64 byte frames transmitted "); 2399 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "tx_frames_65_127", 2400 CTLFLAG_RD, &stats->ptc127, "65-127 byte frames transmitted"); 2401 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "tx_frames_128_255", 2402 CTLFLAG_RD, &stats->ptc255, "128-255 byte frames transmitted"); 2403 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "tx_frames_256_511", 2404 CTLFLAG_RD, &stats->ptc511, "256-511 byte frames transmitted"); 2405 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "tx_frames_512_1023", 2406 CTLFLAG_RD, &stats->ptc1023, "512-1023 byte frames transmitted"); 2407 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "tx_frames_1024_1522", 2408 CTLFLAG_RD, &stats->ptc1522, "1024-1522 byte frames transmitted"); 2409 } /* ixgbe_add_hw_stats */ 2410 2411 /************************************************************************ 2412 * ixgbe_sysctl_tdh_handler - Transmit Descriptor Head handler function 2413 * 2414 * Retrieves the TDH value from the hardware 2415 ************************************************************************/ 2416 static int 2417 ixgbe_sysctl_tdh_handler(SYSCTL_HANDLER_ARGS) 2418 { 2419 struct tx_ring *txr = ((struct tx_ring *)oidp->oid_arg1); 2420 int error; 2421 unsigned int val; 2422 2423 if (!txr) 2424 return (0); 2425 2426 2427 if (atomic_load_acq_int(&txr->sc->recovery_mode)) 2428 return (EPERM); 2429 2430 val = IXGBE_READ_REG(&txr->sc->hw, IXGBE_TDH(txr->me)); 2431 error = sysctl_handle_int(oidp, &val, 0, req); 2432 if (error || !req->newptr) 2433 return error; 2434 2435 return (0); 2436 } /* ixgbe_sysctl_tdh_handler */ 2437 2438 /************************************************************************ 2439 * ixgbe_sysctl_tdt_handler - Transmit Descriptor Tail handler function 2440 * 2441 * Retrieves the TDT value from the hardware 2442 ************************************************************************/ 2443 static int 2444 ixgbe_sysctl_tdt_handler(SYSCTL_HANDLER_ARGS) 2445 { 2446 struct tx_ring *txr = ((struct tx_ring *)oidp->oid_arg1); 2447 int error; 2448 unsigned int val; 2449 2450 if (!txr) 2451 return (0); 2452 2453 if (atomic_load_acq_int(&txr->sc->recovery_mode)) 2454 return (EPERM); 2455 2456 val = IXGBE_READ_REG(&txr->sc->hw, IXGBE_TDT(txr->me)); 2457 error = sysctl_handle_int(oidp, &val, 0, req); 2458 if (error || !req->newptr) 2459 return error; 2460 2461 return (0); 2462 } /* ixgbe_sysctl_tdt_handler */ 2463 2464 /************************************************************************ 2465 * ixgbe_sysctl_rdh_handler - Receive Descriptor Head handler function 2466 * 2467 * Retrieves the RDH value from the hardware 2468 ************************************************************************/ 2469 static int 2470 ixgbe_sysctl_rdh_handler(SYSCTL_HANDLER_ARGS) 2471 { 2472 struct rx_ring *rxr = ((struct rx_ring *)oidp->oid_arg1); 2473 int error; 2474 unsigned int val; 2475 2476 if (!rxr) 2477 return (0); 2478 2479 if (atomic_load_acq_int(&rxr->sc->recovery_mode)) 2480 return (EPERM); 2481 2482 val = IXGBE_READ_REG(&rxr->sc->hw, IXGBE_RDH(rxr->me)); 2483 error = sysctl_handle_int(oidp, &val, 0, req); 2484 if (error || !req->newptr) 2485 return error; 2486 2487 return (0); 2488 } /* ixgbe_sysctl_rdh_handler */ 2489 2490 /************************************************************************ 2491 * ixgbe_sysctl_rdt_handler - Receive Descriptor Tail handler function 2492 * 2493 * Retrieves the RDT value from the hardware 2494 ************************************************************************/ 2495 static int 2496 ixgbe_sysctl_rdt_handler(SYSCTL_HANDLER_ARGS) 2497 { 2498 struct rx_ring *rxr = ((struct rx_ring *)oidp->oid_arg1); 2499 int error; 2500 unsigned int val; 2501 2502 if (!rxr) 2503 return (0); 2504 2505 if (atomic_load_acq_int(&rxr->sc->recovery_mode)) 2506 return (EPERM); 2507 2508 val = IXGBE_READ_REG(&rxr->sc->hw, IXGBE_RDT(rxr->me)); 2509 error = sysctl_handle_int(oidp, &val, 0, req); 2510 if (error || !req->newptr) 2511 return error; 2512 2513 return (0); 2514 } /* ixgbe_sysctl_rdt_handler */ 2515 2516 /************************************************************************ 2517 * ixgbe_if_vlan_register 2518 * 2519 * Run via vlan config EVENT, it enables us to use the 2520 * HW Filter table since we can get the vlan id. This 2521 * just creates the entry in the soft version of the 2522 * VFTA, init will repopulate the real table. 2523 ************************************************************************/ 2524 static void 2525 ixgbe_if_vlan_register(if_ctx_t ctx, u16 vtag) 2526 { 2527 struct ixgbe_softc *sc = iflib_get_softc(ctx); 2528 bool present; 2529 u16 index; 2530 u32 mask; 2531 2532 index = (vtag >> 5) & 0x7F; 2533 mask = 1U << (vtag & 0x1F); 2534 present = (sc->shadow_vfta[index] & mask) != 0; 2535 sc->shadow_vfta[index] |= mask; 2536 if (!present) 2537 ++sc->num_vlans; 2538 #ifdef PCI_IOV 2539 if ((sc->feat_en & IXGBE_FEATURE_SRIOV) != 0 && 2540 sc->iov_vfta_valid && !sc->iov_vlan_promisc) 2541 (void)ixgbe_set_vfta(&sc->hw, vtag, sc->pool, true, true); 2542 #endif 2543 ixgbe_setup_vlan_hw_support(ctx); 2544 } /* ixgbe_if_vlan_register */ 2545 2546 /************************************************************************ 2547 * ixgbe_if_vlan_unregister 2548 * 2549 * Run via vlan unconfig EVENT, remove our entry in the soft vfta. 2550 ************************************************************************/ 2551 static void 2552 ixgbe_if_vlan_unregister(if_ctx_t ctx, u16 vtag) 2553 { 2554 struct ixgbe_softc *sc = iflib_get_softc(ctx); 2555 bool present; 2556 u16 index; 2557 u32 mask; 2558 2559 index = (vtag >> 5) & 0x7F; 2560 mask = 1U << (vtag & 0x1F); 2561 present = (sc->shadow_vfta[index] & mask) != 0; 2562 sc->shadow_vfta[index] &= ~mask; 2563 if (present) 2564 --sc->num_vlans; 2565 #ifdef PCI_IOV 2566 if ((sc->feat_en & IXGBE_FEATURE_SRIOV) != 0 && 2567 sc->iov_vfta_valid && !sc->iov_vlan_promisc) 2568 (void)ixgbe_set_vfta(&sc->hw, vtag, sc->pool, false, true); 2569 #endif 2570 ixgbe_setup_vlan_hw_support(ctx); 2571 } /* ixgbe_if_vlan_unregister */ 2572 2573 #ifdef PCI_IOV 2574 static bool 2575 ixgbe_iov_pf_owns_vlan(const struct ixgbe_softc *sc, u16 vlan) 2576 { 2577 2578 return ((sc->shadow_vfta[vlan >> 5] & 2579 (1U << (vlan & 0x1f))) != 0); 2580 } 2581 2582 /* 2583 * start_hw clears both VFTA and VLVF. Reconstruct the shared tables from 2584 * PF and VF desired state after every reset or filtering-mode transition. 2585 * Allocate VF entries first so PF-only VLANs cannot exhaust VLVF. 2586 */ 2587 static void 2588 ixgbe_iov_vlan_rebuild(struct ixgbe_softc *sc, bool promisc) 2589 { 2590 struct ixgbe_hw *hw; 2591 struct ixgbe_vf *vf; 2592 u32 vfta[IXGBE_VFTA_SIZE]; 2593 u32 bits, vlan, vlvf; 2594 int bit, failures, i, word; 2595 2596 hw = &sc->hw; 2597 bcopy(sc->shadow_vfta, vfta, sizeof(vfta)); 2598 (void)ixgbe_clear_vfta(hw); 2599 failures = 0; 2600 for (i = 0; i < sc->num_vfs; i++) { 2601 vf = &sc->vfs[i]; 2602 if ((vf->flags & IXGBE_VF_ACTIVE) == 0) 2603 continue; 2604 if (vf->default_vlan == 0 && 2605 ixgbe_set_vfta(hw, 0, vf->pool, true, false) != 2606 IXGBE_SUCCESS) 2607 failures++; 2608 for (word = 0; word < IXGBE_VFTA_SIZE; word++) { 2609 bits = vf->vlans[word]; 2610 while (bits != 0) { 2611 bit = ffs(bits) - 1; 2612 vlan = word * 32 + bit; 2613 if (ixgbe_set_vfta(hw, vlan, vf->pool, true, 2614 false) == IXGBE_SUCCESS) 2615 vfta[word] |= 1U << bit; 2616 else 2617 failures++; 2618 bits &= ~(1U << bit); 2619 } 2620 } 2621 } 2622 if (ixgbe_set_vfta(hw, 0, sc->pool, true, false) != IXGBE_SUCCESS) 2623 failures++; 2624 2625 /* Add the PF to shared entries, or every entry in promiscuous mode. */ 2626 for (i = 1; i < IXGBE_VLVF_ENTRIES; i++) { 2627 vlvf = IXGBE_READ_REG(hw, IXGBE_VLVF(i)); 2628 if ((vlvf & IXGBE_VLVF_VIEN) == 0) 2629 continue; 2630 vlan = vlvf & IXGBE_VLVF_VLANID_MASK; 2631 if (promisc || ixgbe_iov_pf_owns_vlan(sc, vlan)) 2632 (void)ixgbe_set_vfta(hw, vlan, sc->pool, true, true); 2633 vfta[vlan >> 5] |= 1U << (vlan & 0x1f); 2634 } 2635 if (promisc) 2636 for (i = 0; i < IXGBE_VFTA_SIZE; i++) 2637 vfta[i] = UINT32_MAX; 2638 for (i = 0; i < IXGBE_VFTA_SIZE; i++) 2639 IXGBE_WRITE_REG(hw, IXGBE_VFTA(i), vfta[i]); 2640 if (failures != 0) 2641 device_printf(sc->dev, 2642 "VLAN pool restore failed for %d memberships\n", failures); 2643 } 2644 2645 static void 2646 ixgbe_iov_vlan_sync(struct ixgbe_softc *sc, bool promisc) 2647 { 2648 2649 if (sc->iov_vfta_valid && sc->iov_vlan_promisc == promisc) 2650 return; 2651 ixgbe_iov_vlan_rebuild(sc, promisc); 2652 sc->iov_vlan_promisc = promisc; 2653 sc->iov_vfta_valid = true; 2654 } 2655 #endif 2656 2657 /************************************************************************ 2658 * ixgbe_setup_vlan_hw_support 2659 ************************************************************************/ 2660 void 2661 ixgbe_setup_vlan_hw_support(if_ctx_t ctx) 2662 { 2663 if_t ifp = iflib_get_ifp(ctx); 2664 struct ixgbe_softc *sc = iflib_get_softc(ctx); 2665 struct ixgbe_hw *hw = &sc->hw; 2666 struct rx_ring *rxr; 2667 bool strip; 2668 int i; 2669 u32 ctrl; 2670 2671 strip = sc->num_vlans != 0 && 2672 (if_getcapenable(ifp) & IFCAP_VLAN_HWTAGGING) != 0; 2673 for (i = 0; i < sc->num_rx_queues; i++) { 2674 rxr = &sc->rx_queues[i].rxr; 2675 /* On 82599 and newer VLAN stripping is per receive queue. */ 2676 if (hw->mac.type != ixgbe_mac_82598EB) { 2677 ctrl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(rxr->me)); 2678 if (strip) 2679 ctrl |= IXGBE_RXDCTL_VME; 2680 else 2681 ctrl &= ~IXGBE_RXDCTL_VME; 2682 IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(rxr->me), ctrl); 2683 } 2684 rxr->vtag_strip = strip; 2685 } 2686 2687 ctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL); 2688 if (hw->mac.type == ixgbe_mac_82598EB) { 2689 if (strip) 2690 ctrl |= IXGBE_VLNCTRL_VME; 2691 else 2692 ctrl &= ~IXGBE_VLNCTRL_VME; 2693 } 2694 2695 /* Always admit priority-tagged frames. */ 2696 sc->shadow_vfta[0] |= 1U; 2697 2698 #ifdef PCI_IOV 2699 if ((sc->feat_en & IXGBE_FEATURE_SRIOV) != 0) { 2700 /* 2701 * VFE must remain enabled to enforce per-pool VLAN ownership. 2702 */ 2703 ctrl &= ~IXGBE_VLNCTRL_CFIEN; 2704 ctrl |= IXGBE_VLNCTRL_VFE; 2705 IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, ctrl); 2706 ixgbe_iov_vlan_sync(sc, 2707 (if_getcapenable(ifp) & IFCAP_VLAN_HWFILTER) == 0); 2708 return; 2709 } 2710 #endif 2711 2712 if (!strip || 2713 (if_getcapenable(ifp) & IFCAP_VLAN_HWFILTER) == 0) { 2714 ctrl |= IXGBE_VLNCTRL_CFIEN; 2715 ctrl &= ~IXGBE_VLNCTRL_VFE; 2716 IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, ctrl); 2717 return; 2718 } 2719 2720 /* A soft reset clears VFTA, so restore the PF's desired bitmap. */ 2721 for (i = 0; i < IXGBE_VFTA_SIZE; i++) 2722 IXGBE_WRITE_REG(hw, IXGBE_VFTA(i), sc->shadow_vfta[i]); 2723 ctrl &= ~IXGBE_VLNCTRL_CFIEN; 2724 ctrl |= IXGBE_VLNCTRL_VFE; 2725 IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, ctrl); 2726 } /* ixgbe_setup_vlan_hw_support */ 2727 2728 /************************************************************************ 2729 * ixgbe_get_slot_info 2730 * 2731 * Get the width and transaction speed of 2732 * the slot this adapter is plugged into. 2733 ************************************************************************/ 2734 static void 2735 ixgbe_get_slot_info(struct ixgbe_softc *sc) 2736 { 2737 device_t dev = iflib_get_dev(sc->ctx); 2738 struct ixgbe_hw *hw = &sc->hw; 2739 int bus_info_valid = true; 2740 u32 offset; 2741 u16 link; 2742 2743 /* Some devices are behind an internal bridge */ 2744 switch (hw->device_id) { 2745 case IXGBE_DEV_ID_82599_SFP_SF_QP: 2746 case IXGBE_DEV_ID_82599_QSFP_SF_QP: 2747 goto get_parent_info; 2748 default: 2749 break; 2750 } 2751 2752 ixgbe_get_bus_info(hw); 2753 2754 /* 2755 * Some devices don't use PCI-E, but there is no need 2756 * to display "Unknown" for bus speed and width. 2757 */ 2758 switch (hw->mac.type) { 2759 case ixgbe_mac_X550EM_x: 2760 case ixgbe_mac_X550EM_a: 2761 return; 2762 default: 2763 goto display; 2764 } 2765 2766 get_parent_info: 2767 /* 2768 * For the Quad port adapter we need to parse back 2769 * up the PCI tree to find the speed of the expansion 2770 * slot into which this adapter is plugged. A bit more work. 2771 */ 2772 dev = device_get_parent(device_get_parent(dev)); 2773 #ifdef IXGBE_DEBUG 2774 device_printf(dev, "parent pcib = %x,%x,%x\n", pci_get_bus(dev), 2775 pci_get_slot(dev), pci_get_function(dev)); 2776 #endif 2777 dev = device_get_parent(device_get_parent(dev)); 2778 #ifdef IXGBE_DEBUG 2779 device_printf(dev, "slot pcib = %x,%x,%x\n", pci_get_bus(dev), 2780 pci_get_slot(dev), pci_get_function(dev)); 2781 #endif 2782 /* Now get the PCI Express Capabilities offset */ 2783 if (pci_find_cap(dev, PCIY_EXPRESS, &offset)) { 2784 /* 2785 * Hmm...can't get PCI-Express capabilities. 2786 * Falling back to default method. 2787 */ 2788 bus_info_valid = false; 2789 ixgbe_get_bus_info(hw); 2790 goto display; 2791 } 2792 /* ...and read the Link Status Register */ 2793 link = pci_read_config(dev, offset + PCIER_LINK_STA, 2); 2794 ixgbe_set_pci_config_data_generic(hw, link); 2795 2796 display: 2797 device_printf(dev, "PCI Express Bus: Speed %s Width %s\n", 2798 ((hw->bus.speed == ixgbe_bus_speed_16000) ? "16.0GT/s" : 2799 (hw->bus.speed == ixgbe_bus_speed_8000) ? "8.0GT/s" : 2800 (hw->bus.speed == ixgbe_bus_speed_5000) ? "5.0GT/s" : 2801 (hw->bus.speed == ixgbe_bus_speed_2500) ? "2.5GT/s" : 2802 "Unknown"), 2803 ((hw->bus.width == ixgbe_bus_width_pcie_x8) ? "x8" : 2804 (hw->bus.width == ixgbe_bus_width_pcie_x4) ? "x4" : 2805 (hw->bus.width == ixgbe_bus_width_pcie_x1) ? "x1" : 2806 "Unknown")); 2807 2808 if (bus_info_valid) { 2809 if ((hw->device_id != IXGBE_DEV_ID_82599_SFP_SF_QP) && 2810 ((hw->bus.width <= ixgbe_bus_width_pcie_x4) && 2811 (hw->bus.speed == ixgbe_bus_speed_2500))) { 2812 device_printf(dev, 2813 "PCI-Express bandwidth available for this card" 2814 " is not sufficient for optimal performance.\n"); 2815 device_printf(dev, 2816 "For optimal performance a x8 PCIE, or x4 PCIE" 2817 " Gen2 slot is required.\n"); 2818 } 2819 if ((hw->device_id == IXGBE_DEV_ID_82599_SFP_SF_QP) && 2820 ((hw->bus.width <= ixgbe_bus_width_pcie_x8) && 2821 (hw->bus.speed < ixgbe_bus_speed_8000))) { 2822 device_printf(dev, 2823 "PCI-Express bandwidth available for this card" 2824 " is not sufficient for optimal performance.\n"); 2825 device_printf(dev, 2826 "For optimal performance a x8 PCIE Gen3 slot is" 2827 " required.\n"); 2828 } 2829 } else 2830 device_printf(dev, 2831 "Unable to determine slot speed/width. The speed/width" 2832 " reported are that of the internal switch.\n"); 2833 2834 return; 2835 } /* ixgbe_get_slot_info */ 2836 2837 /************************************************************************ 2838 * ixgbe_if_msix_intr_assign 2839 * 2840 * Setup MSI-X Interrupt resources and handlers 2841 ************************************************************************/ 2842 static int 2843 ixgbe_if_msix_intr_assign(if_ctx_t ctx, int msix) 2844 { 2845 struct ixgbe_softc *sc = iflib_get_softc(ctx); 2846 struct ix_rx_queue *rx_que = sc->rx_queues; 2847 struct ix_tx_queue *tx_que; 2848 int error, rid, vector = 0; 2849 char buf[16]; 2850 2851 /* Admin Que is vector 0*/ 2852 rid = vector + 1; 2853 for (int i = 0; i < sc->num_rx_queues; i++, vector++, rx_que++) { 2854 rid = vector + 1; 2855 2856 snprintf(buf, sizeof(buf), "rxq%d", i); 2857 error = iflib_irq_alloc_generic(ctx, &rx_que->que_irq, rid, 2858 IFLIB_INTR_RXTX, ixgbe_msix_que, rx_que, rx_que->rxr.me, 2859 buf); 2860 2861 if (error) { 2862 device_printf(iflib_get_dev(ctx), 2863 "Failed to allocate que int %d err: %d", 2864 i,error); 2865 sc->num_rx_queues = i + 1; 2866 goto fail; 2867 } 2868 2869 rx_que->msix = vector; 2870 } 2871 for (int i = 0; i < sc->num_tx_queues; i++) { 2872 snprintf(buf, sizeof(buf), "txq%d", i); 2873 tx_que = &sc->tx_queues[i]; 2874 tx_que->msix = i % sc->num_rx_queues; 2875 iflib_softirq_alloc_generic(ctx, 2876 &sc->rx_queues[tx_que->msix].que_irq, 2877 IFLIB_INTR_TX, tx_que, tx_que->txr.me, buf); 2878 } 2879 rid = vector + 1; 2880 error = iflib_irq_alloc_generic(ctx, &sc->irq, rid, 2881 IFLIB_INTR_ADMIN, ixgbe_msix_link, sc, 0, "aq"); 2882 if (error) { 2883 device_printf(iflib_get_dev(ctx), 2884 "Failed to register admin handler"); 2885 return (error); 2886 } 2887 2888 sc->vector = vector; 2889 2890 return (0); 2891 fail: 2892 iflib_irq_free(ctx, &sc->irq); 2893 rx_que = sc->rx_queues; 2894 for (int i = 0; i < sc->num_rx_queues; i++, rx_que++) 2895 iflib_irq_free(ctx, &rx_que->que_irq); 2896 2897 return (error); 2898 } /* ixgbe_if_msix_intr_assign */ 2899 2900 static inline void 2901 ixgbe_perform_aim(struct ixgbe_softc *sc, struct ix_rx_queue *que) 2902 { 2903 uint32_t newitr = 0; 2904 struct rx_ring *rxr = &que->rxr; 2905 /* FIXME struct tx_ring *txr = ... ->txr; */ 2906 2907 /* 2908 * Do Adaptive Interrupt Moderation: 2909 * - Write out last calculated setting 2910 * - Calculate based on average size over 2911 * the last interval. 2912 */ 2913 if (que->eitr_setting) { 2914 IXGBE_WRITE_REG(&sc->hw, IXGBE_EITR(que->msix), 2915 que->eitr_setting); 2916 } 2917 2918 que->eitr_setting = 0; 2919 /* Idle, do nothing */ 2920 if (rxr->bytes == 0) { 2921 /* FIXME && txr->bytes == 0 */ 2922 return; 2923 } 2924 2925 if ((rxr->bytes) && (rxr->packets)) 2926 newitr = rxr->bytes / rxr->packets; 2927 /* FIXME for transmit accounting 2928 * if ((txr->bytes) && (txr->packets)) 2929 * newitr = txr->bytes/txr->packets; 2930 * if ((rxr->bytes) && (rxr->packets)) 2931 * newitr = max(newitr, (rxr->bytes / rxr->packets)); 2932 */ 2933 2934 newitr += 24; /* account for hardware frame, crc */ 2935 /* set an upper boundary */ 2936 newitr = min(newitr, 3000); 2937 2938 /* Be nice to the mid range */ 2939 if ((newitr > 300) && (newitr < 1200)) { 2940 newitr = (newitr / 3); 2941 } else { 2942 newitr = (newitr / 2); 2943 } 2944 2945 if (sc->hw.mac.type == ixgbe_mac_82598EB) { 2946 newitr |= newitr << 16; 2947 } else { 2948 newitr |= IXGBE_EITR_CNT_WDIS; 2949 } 2950 2951 /* save for next interrupt */ 2952 que->eitr_setting = newitr; 2953 2954 /* Reset state */ 2955 /* FIXME txr->bytes = 0; */ 2956 /* FIXME txr->packets = 0; */ 2957 rxr->bytes = 0; 2958 rxr->packets = 0; 2959 2960 return; 2961 } 2962 2963 /********************************************************************* 2964 * ixgbe_msix_que - MSI-X Queue Interrupt Service routine 2965 **********************************************************************/ 2966 static int 2967 ixgbe_msix_que(void *arg) 2968 { 2969 struct ix_rx_queue *que = arg; 2970 struct ixgbe_softc *sc = que->sc; 2971 if_t ifp = iflib_get_ifp(que->sc->ctx); 2972 2973 /* Protect against spurious interrupts */ 2974 if ((if_getdrvflags(ifp) & IFF_DRV_RUNNING) == 0) 2975 return (FILTER_HANDLED); 2976 2977 ixgbe_disable_queue(sc, que->msix); 2978 ++que->irqs; 2979 2980 /* Check for AIM */ 2981 if (sc->enable_aim) { 2982 ixgbe_perform_aim(sc, que); 2983 } 2984 2985 return (FILTER_SCHEDULE_THREAD); 2986 } /* ixgbe_msix_que */ 2987 2988 /************************************************************************ 2989 * ixgbe_media_status - Media Ioctl callback 2990 * 2991 * Called whenever the user queries the status of 2992 * the interface using ifconfig. 2993 ************************************************************************/ 2994 static void 2995 ixgbe_if_media_status(if_ctx_t ctx, struct ifmediareq * ifmr) 2996 { 2997 struct ixgbe_softc *sc = iflib_get_softc(ctx); 2998 struct ixgbe_hw *hw = &sc->hw; 2999 int layer; 3000 3001 INIT_DEBUGOUT("ixgbe_if_media_status: begin"); 3002 3003 ifmr->ifm_status = IFM_AVALID; 3004 ifmr->ifm_active = IFM_ETHER; 3005 3006 if (!sc->link_active) 3007 return; 3008 3009 ifmr->ifm_status |= IFM_ACTIVE; 3010 layer = sc->phy_layer; 3011 3012 if (layer & IXGBE_PHYSICAL_LAYERS_BASE_T_ALL) 3013 switch (sc->link_speed) { 3014 case IXGBE_LINK_SPEED_10GB_FULL: 3015 ifmr->ifm_active |= IFM_10G_T | IFM_FDX; 3016 break; 3017 case IXGBE_LINK_SPEED_5GB_FULL: 3018 ifmr->ifm_active |= IFM_5000_T | IFM_FDX; 3019 break; 3020 case IXGBE_LINK_SPEED_2_5GB_FULL: 3021 ifmr->ifm_active |= IFM_2500_T | IFM_FDX; 3022 break; 3023 case IXGBE_LINK_SPEED_1GB_FULL: 3024 ifmr->ifm_active |= IFM_1000_T | IFM_FDX; 3025 break; 3026 case IXGBE_LINK_SPEED_100_FULL: 3027 ifmr->ifm_active |= IFM_100_TX | IFM_FDX; 3028 break; 3029 case IXGBE_LINK_SPEED_10_FULL: 3030 ifmr->ifm_active |= IFM_10_T | IFM_FDX; 3031 break; 3032 } 3033 if (layer & IXGBE_PHYSICAL_LAYER_SFP_PLUS_CU || 3034 layer & IXGBE_PHYSICAL_LAYER_SFP_ACTIVE_DA) 3035 switch (sc->link_speed) { 3036 case IXGBE_LINK_SPEED_10GB_FULL: 3037 ifmr->ifm_active |= IFM_10G_TWINAX | IFM_FDX; 3038 break; 3039 case IXGBE_LINK_SPEED_1GB_FULL: 3040 ifmr->ifm_active |= IFM_1000_KX | IFM_FDX; 3041 break; 3042 } 3043 if (layer & IXGBE_PHYSICAL_LAYER_10GBASE_LR) 3044 switch (sc->link_speed) { 3045 case IXGBE_LINK_SPEED_10GB_FULL: 3046 ifmr->ifm_active |= IFM_10G_LR | IFM_FDX; 3047 break; 3048 case IXGBE_LINK_SPEED_1GB_FULL: 3049 ifmr->ifm_active |= IFM_1000_LX | IFM_FDX; 3050 break; 3051 } 3052 if (layer & IXGBE_PHYSICAL_LAYER_10GBASE_BX && 3053 sc->link_speed == IXGBE_LINK_SPEED_10GB_FULL) 3054 ifmr->ifm_active |= IFM_10G_BX | IFM_FDX; 3055 if (layer & IXGBE_PHYSICAL_LAYER_10GBASE_LRM) 3056 switch (sc->link_speed) { 3057 case IXGBE_LINK_SPEED_10GB_FULL: 3058 ifmr->ifm_active |= IFM_10G_LRM | IFM_FDX; 3059 break; 3060 case IXGBE_LINK_SPEED_1GB_FULL: 3061 ifmr->ifm_active |= IFM_1000_LX | IFM_FDX; 3062 break; 3063 } 3064 if (layer & IXGBE_PHYSICAL_LAYER_10GBASE_SR || 3065 layer & IXGBE_PHYSICAL_LAYER_1000BASE_SX) 3066 switch (sc->link_speed) { 3067 case IXGBE_LINK_SPEED_10GB_FULL: 3068 ifmr->ifm_active |= IFM_10G_SR | IFM_FDX; 3069 break; 3070 case IXGBE_LINK_SPEED_1GB_FULL: 3071 ifmr->ifm_active |= IFM_1000_SX | IFM_FDX; 3072 break; 3073 } 3074 if (layer & IXGBE_PHYSICAL_LAYER_10GBASE_CX4) 3075 switch (sc->link_speed) { 3076 case IXGBE_LINK_SPEED_10GB_FULL: 3077 ifmr->ifm_active |= IFM_10G_CX4 | IFM_FDX; 3078 break; 3079 } 3080 /* 3081 * XXX: These need to use the proper media types once 3082 * they're added. 3083 */ 3084 #ifndef IFM_ETH_XTYPE 3085 if (layer & IXGBE_PHYSICAL_LAYER_10GBASE_KR) 3086 switch (sc->link_speed) { 3087 case IXGBE_LINK_SPEED_10GB_FULL: 3088 ifmr->ifm_active |= IFM_10G_SR | IFM_FDX; 3089 break; 3090 case IXGBE_LINK_SPEED_2_5GB_FULL: 3091 ifmr->ifm_active |= IFM_2500_SX | IFM_FDX; 3092 break; 3093 case IXGBE_LINK_SPEED_1GB_FULL: 3094 ifmr->ifm_active |= IFM_1000_CX | IFM_FDX; 3095 break; 3096 } 3097 else if (layer & IXGBE_PHYSICAL_LAYER_10GBASE_KX4 || 3098 layer & IXGBE_PHYSICAL_LAYER_2500BASE_KX || 3099 layer & IXGBE_PHYSICAL_LAYER_1000BASE_KX) 3100 switch (sc->link_speed) { 3101 case IXGBE_LINK_SPEED_10GB_FULL: 3102 ifmr->ifm_active |= IFM_10G_CX4 | IFM_FDX; 3103 break; 3104 case IXGBE_LINK_SPEED_2_5GB_FULL: 3105 ifmr->ifm_active |= IFM_2500_SX | IFM_FDX; 3106 break; 3107 case IXGBE_LINK_SPEED_1GB_FULL: 3108 ifmr->ifm_active |= IFM_1000_CX | IFM_FDX; 3109 break; 3110 } 3111 #else 3112 if (layer & IXGBE_PHYSICAL_LAYER_10GBASE_KR) 3113 switch (sc->link_speed) { 3114 case IXGBE_LINK_SPEED_10GB_FULL: 3115 ifmr->ifm_active |= IFM_10G_KR | IFM_FDX; 3116 break; 3117 case IXGBE_LINK_SPEED_2_5GB_FULL: 3118 ifmr->ifm_active |= IFM_2500_KX | IFM_FDX; 3119 break; 3120 case IXGBE_LINK_SPEED_1GB_FULL: 3121 ifmr->ifm_active |= IFM_1000_KX | IFM_FDX; 3122 break; 3123 } 3124 else if (layer & IXGBE_PHYSICAL_LAYER_10GBASE_KX4 || 3125 layer & IXGBE_PHYSICAL_LAYER_2500BASE_KX || 3126 layer & IXGBE_PHYSICAL_LAYER_1000BASE_KX) 3127 switch (sc->link_speed) { 3128 case IXGBE_LINK_SPEED_10GB_FULL: 3129 ifmr->ifm_active |= IFM_10G_KX4 | IFM_FDX; 3130 break; 3131 case IXGBE_LINK_SPEED_2_5GB_FULL: 3132 ifmr->ifm_active |= IFM_2500_KX | IFM_FDX; 3133 break; 3134 case IXGBE_LINK_SPEED_1GB_FULL: 3135 ifmr->ifm_active |= IFM_1000_KX | IFM_FDX; 3136 break; 3137 } 3138 #endif 3139 3140 /* If nothing is recognized... */ 3141 if (IFM_SUBTYPE(ifmr->ifm_active) == 0) 3142 ifmr->ifm_active |= IFM_UNKNOWN; 3143 3144 /* Display current flow control setting used on link */ 3145 if (hw->fc.current_mode == ixgbe_fc_rx_pause || 3146 hw->fc.current_mode == ixgbe_fc_full) 3147 ifmr->ifm_active |= IFM_ETH_RXPAUSE; 3148 if (hw->fc.current_mode == ixgbe_fc_tx_pause || 3149 hw->fc.current_mode == ixgbe_fc_full) 3150 ifmr->ifm_active |= IFM_ETH_TXPAUSE; 3151 } /* ixgbe_media_status */ 3152 3153 /************************************************************************ 3154 * ixgbe_media_change - Media Ioctl callback 3155 * 3156 * Called when the user changes speed/duplex using 3157 * media/mediopt option with ifconfig. 3158 ************************************************************************/ 3159 static int 3160 ixgbe_if_media_change(if_ctx_t ctx) 3161 { 3162 struct ixgbe_softc *sc = iflib_get_softc(ctx); 3163 struct ifmedia *ifm = iflib_get_media(ctx); 3164 struct ixgbe_hw *hw = &sc->hw; 3165 ixgbe_link_speed speed = 0; 3166 3167 INIT_DEBUGOUT("ixgbe_if_media_change: begin"); 3168 3169 if (IFM_TYPE(ifm->ifm_media) != IFM_ETHER) 3170 return (EINVAL); 3171 3172 if (hw->phy.media_type == ixgbe_media_type_backplane) 3173 return (EPERM); 3174 3175 /* 3176 * We don't actually need to check against the supported 3177 * media types of the adapter; ifmedia will take care of 3178 * that for us. 3179 */ 3180 switch (IFM_SUBTYPE(ifm->ifm_media)) { 3181 case IFM_AUTO: 3182 case IFM_10G_T: 3183 speed |= IXGBE_LINK_SPEED_100_FULL; 3184 speed |= IXGBE_LINK_SPEED_1GB_FULL; 3185 speed |= IXGBE_LINK_SPEED_10GB_FULL; 3186 break; 3187 case IFM_10G_BX: 3188 speed |= IXGBE_LINK_SPEED_10GB_FULL; 3189 break; 3190 case IFM_10G_LRM: 3191 case IFM_10G_LR: 3192 #ifndef IFM_ETH_XTYPE 3193 case IFM_10G_SR: /* KR, too */ 3194 case IFM_10G_CX4: /* KX4 */ 3195 #else 3196 case IFM_10G_KR: 3197 case IFM_10G_KX4: 3198 #endif 3199 speed |= IXGBE_LINK_SPEED_1GB_FULL; 3200 speed |= IXGBE_LINK_SPEED_10GB_FULL; 3201 break; 3202 #ifndef IFM_ETH_XTYPE 3203 case IFM_1000_CX: /* KX */ 3204 #else 3205 case IFM_1000_KX: 3206 #endif 3207 case IFM_1000_LX: 3208 case IFM_1000_SX: 3209 case IFM_1000_BX: 3210 speed |= IXGBE_LINK_SPEED_1GB_FULL; 3211 break; 3212 case IFM_1000_T: 3213 speed |= IXGBE_LINK_SPEED_100_FULL; 3214 speed |= IXGBE_LINK_SPEED_1GB_FULL; 3215 break; 3216 case IFM_10G_TWINAX: 3217 speed |= IXGBE_LINK_SPEED_10GB_FULL; 3218 break; 3219 case IFM_5000_T: 3220 speed |= IXGBE_LINK_SPEED_5GB_FULL; 3221 break; 3222 case IFM_2500_T: 3223 speed |= IXGBE_LINK_SPEED_2_5GB_FULL; 3224 break; 3225 case IFM_100_TX: 3226 speed |= IXGBE_LINK_SPEED_100_FULL; 3227 break; 3228 case IFM_10_T: 3229 speed |= IXGBE_LINK_SPEED_10_FULL; 3230 break; 3231 default: 3232 goto invalid; 3233 } 3234 3235 hw->mac.autotry_restart = true; 3236 hw->mac.ops.setup_link(hw, speed, true); 3237 sc->advertise = 3238 ((speed & IXGBE_LINK_SPEED_10GB_FULL) ? 0x4 : 0) | 3239 ((speed & IXGBE_LINK_SPEED_5GB_FULL) ? 0x20 : 0) | 3240 ((speed & IXGBE_LINK_SPEED_2_5GB_FULL) ? 0x10 : 0) | 3241 ((speed & IXGBE_LINK_SPEED_1GB_FULL) ? 0x2 : 0) | 3242 ((speed & IXGBE_LINK_SPEED_100_FULL) ? 0x1 : 0) | 3243 ((speed & IXGBE_LINK_SPEED_10_FULL) ? 0x8 : 0); 3244 3245 return (0); 3246 3247 invalid: 3248 device_printf(iflib_get_dev(ctx), "Invalid media type!\n"); 3249 3250 return (EINVAL); 3251 } /* ixgbe_if_media_change */ 3252 3253 /************************************************************************ 3254 * ixgbe_set_promisc 3255 ************************************************************************/ 3256 static int 3257 ixgbe_if_promisc_set(if_ctx_t ctx, int flags) 3258 { 3259 struct ixgbe_softc *sc = iflib_get_softc(ctx); 3260 if_t ifp = iflib_get_ifp(ctx); 3261 u32 rctl; 3262 int mcnt = 0; 3263 3264 rctl = IXGBE_READ_REG(&sc->hw, IXGBE_FCTRL); 3265 rctl &= (~IXGBE_FCTRL_UPE); 3266 if (if_getflags(ifp) & IFF_ALLMULTI) 3267 mcnt = MAX_NUM_MULTICAST_ADDRESSES; 3268 else { 3269 mcnt = min(if_llmaddr_count(ifp), 3270 MAX_NUM_MULTICAST_ADDRESSES); 3271 } 3272 if (mcnt < MAX_NUM_MULTICAST_ADDRESSES) 3273 rctl &= (~IXGBE_FCTRL_MPE); 3274 IXGBE_WRITE_REG(&sc->hw, IXGBE_FCTRL, rctl); 3275 3276 if (if_getflags(ifp) & IFF_PROMISC) { 3277 rctl |= (IXGBE_FCTRL_UPE | IXGBE_FCTRL_MPE); 3278 IXGBE_WRITE_REG(&sc->hw, IXGBE_FCTRL, rctl); 3279 } else if (if_getflags(ifp) & IFF_ALLMULTI) { 3280 rctl |= IXGBE_FCTRL_MPE; 3281 rctl &= ~IXGBE_FCTRL_UPE; 3282 IXGBE_WRITE_REG(&sc->hw, IXGBE_FCTRL, rctl); 3283 } 3284 return (0); 3285 } /* ixgbe_if_promisc_set */ 3286 3287 /************************************************************************ 3288 * ixgbe_handle_ecc - Defer recovery from an ECC interrupt 3289 ************************************************************************/ 3290 static bool 3291 ixgbe_handle_ecc(struct ixgbe_softc *sc, u32 eicr) 3292 { 3293 struct ixgbe_hw *hw = &sc->hw; 3294 3295 if ((eicr & IXGBE_EICR_ECC) == 0) 3296 return (false); 3297 3298 IXGBE_WRITE_REG(hw, IXGBE_EIMC, IXGBE_EIMC_ECC); 3299 if (!atomic_cmpset_int(&sc->ecc_reset_pending, 0, 1)) 3300 return (false); 3301 3302 device_printf(sc->dev, "Received ECC Err, initiating reset\n"); 3303 return (true); 3304 } 3305 3306 /************************************************************************ 3307 * ixgbe_msix_link - Link status change ISR (MSI/MSI-X) 3308 ************************************************************************/ 3309 static int 3310 ixgbe_msix_link(void *arg) 3311 { 3312 struct ixgbe_softc *sc = arg; 3313 struct ixgbe_hw *hw = &sc->hw; 3314 u32 eicr, eicr_mask; 3315 s32 retval; 3316 3317 ++sc->link_irq; 3318 3319 /* Pause other interrupts */ 3320 IXGBE_WRITE_REG(hw, IXGBE_EIMC, IXGBE_EIMC_OTHER); 3321 3322 /* First get the cause */ 3323 eicr = IXGBE_READ_REG(hw, IXGBE_EICS); 3324 /* Be sure the queue bits are not cleared */ 3325 eicr &= ~IXGBE_EICR_RTX_QUEUE; 3326 /* Clear interrupt with write */ 3327 IXGBE_WRITE_REG(hw, IXGBE_EICR, eicr); 3328 3329 /* Link status change */ 3330 if (eicr & IXGBE_EICR_LSC) { 3331 IXGBE_WRITE_REG(hw, IXGBE_EIMC, IXGBE_EIMC_LSC); 3332 atomic_set_32(&sc->task_requests, IXGBE_REQUEST_TASK_LSC); 3333 } 3334 3335 if (eicr & IXGBE_EICR_FW_EVENT) { 3336 IXGBE_WRITE_REG(hw, IXGBE_EIMC, IXGBE_EICR_FW_EVENT); 3337 atomic_set_32(&sc->task_requests, IXGBE_REQUEST_TASK_FWEVENT); 3338 } 3339 3340 if (sc->hw.mac.type != ixgbe_mac_82598EB) { 3341 if ((sc->feat_en & IXGBE_FEATURE_FDIR) && 3342 (eicr & IXGBE_EICR_FLOW_DIR)) { 3343 /* This is probably overkill :) */ 3344 if (atomic_cmpset_int(&sc->fdir_reinit, 0, 1)) { 3345 /* Disable the interrupt */ 3346 IXGBE_WRITE_REG(hw, IXGBE_EIMC, 3347 IXGBE_EICR_FLOW_DIR); 3348 atomic_set_32(&sc->task_requests, 3349 IXGBE_REQUEST_TASK_FDIR); 3350 } 3351 } 3352 if (ixgbe_handle_ecc(sc, eicr)) 3353 atomic_set_32(&sc->task_requests, 3354 IXGBE_REQUEST_TASK_RESET); 3355 3356 /* Check for over temp condition */ 3357 if (sc->feat_en & IXGBE_FEATURE_TEMP_SENSOR) { 3358 switch (sc->hw.mac.type) { 3359 case ixgbe_mac_X550EM_a: 3360 if (!(eicr & IXGBE_EICR_GPI_SDP0_X550EM_a)) 3361 break; 3362 IXGBE_WRITE_REG(hw, IXGBE_EIMC, 3363 IXGBE_EICR_GPI_SDP0_X550EM_a); 3364 IXGBE_WRITE_REG(hw, IXGBE_EICR, 3365 IXGBE_EICR_GPI_SDP0_X550EM_a); 3366 retval = hw->phy.ops.check_overtemp(hw); 3367 if (retval != IXGBE_ERR_OVERTEMP) 3368 break; 3369 device_printf(iflib_get_dev(sc->ctx), 3370 "\nCRITICAL: OVER TEMP!!" 3371 " PHY IS SHUT DOWN!!\n"); 3372 device_printf(iflib_get_dev(sc->ctx), 3373 "System shutdown required!\n"); 3374 break; 3375 default: 3376 if (!(eicr & IXGBE_EICR_TS)) 3377 break; 3378 retval = hw->phy.ops.check_overtemp(hw); 3379 if (retval != IXGBE_ERR_OVERTEMP) 3380 break; 3381 device_printf(iflib_get_dev(sc->ctx), 3382 "\nCRITICAL: OVER TEMP!!" 3383 " PHY IS SHUT DOWN!!\n"); 3384 device_printf(iflib_get_dev(sc->ctx), 3385 "System shutdown required!\n"); 3386 IXGBE_WRITE_REG(hw, IXGBE_EICR, 3387 IXGBE_EICR_TS); 3388 break; 3389 } 3390 } 3391 3392 /* Check for VF message */ 3393 if ((sc->feat_en & IXGBE_FEATURE_SRIOV) && 3394 (eicr & IXGBE_EICR_MAILBOX)) { 3395 atomic_set_32(&sc->task_requests, IXGBE_REQUEST_TASK_MBX); 3396 } 3397 } 3398 3399 /* 3400 * On E610, the firmware handles PHY configuration, so 3401 * there is no need to perform any SFP-specific tasks. 3402 */ 3403 if (hw->mac.type != ixgbe_mac_E610 && ixgbe_is_sfp(hw)) { 3404 /* Pluggable optics-related interrupt */ 3405 if (hw->mac.type >= ixgbe_mac_X540) 3406 eicr_mask = IXGBE_EICR_GPI_SDP0_X540; 3407 else 3408 eicr_mask = IXGBE_EICR_GPI_SDP2_BY_MAC(hw); 3409 3410 if (eicr & eicr_mask) { 3411 IXGBE_WRITE_REG(hw, IXGBE_EICR, eicr_mask); 3412 atomic_set_32(&sc->task_requests, IXGBE_REQUEST_TASK_MOD); 3413 } 3414 3415 if ((hw->mac.type == ixgbe_mac_82599EB) && 3416 (eicr & IXGBE_EICR_GPI_SDP1_BY_MAC(hw))) { 3417 IXGBE_WRITE_REG(hw, IXGBE_EICR, 3418 IXGBE_EICR_GPI_SDP1_BY_MAC(hw)); 3419 atomic_set_32(&sc->task_requests, IXGBE_REQUEST_TASK_MSF); 3420 } 3421 } 3422 3423 /* Check for fan failure */ 3424 if (sc->feat_en & IXGBE_FEATURE_FAN_FAIL) { 3425 ixgbe_check_fan_failure(sc, eicr, true); 3426 IXGBE_WRITE_REG(hw, IXGBE_EICR, 3427 IXGBE_EICR_GPI_SDP1_BY_MAC(hw)); 3428 } 3429 3430 /* External PHY interrupt */ 3431 if ((hw->phy.type == ixgbe_phy_x550em_ext_t) && 3432 (eicr & IXGBE_EICR_GPI_SDP0_X540)) { 3433 IXGBE_WRITE_REG(hw, IXGBE_EICR, IXGBE_EICR_GPI_SDP0_X540); 3434 atomic_set_32(&sc->task_requests, IXGBE_REQUEST_TASK_PHY); 3435 } 3436 3437 return (atomic_load_acq_32(&sc->task_requests) != 0) ? 3438 FILTER_SCHEDULE_THREAD : FILTER_HANDLED; 3439 } /* ixgbe_msix_link */ 3440 3441 /************************************************************************ 3442 * ixgbe_sysctl_interrupt_rate_handler 3443 ************************************************************************/ 3444 static int 3445 ixgbe_sysctl_interrupt_rate_handler(SYSCTL_HANDLER_ARGS) 3446 { 3447 struct ix_rx_queue *que = ((struct ix_rx_queue *)oidp->oid_arg1); 3448 int error; 3449 unsigned int reg, usec, rate; 3450 3451 if (atomic_load_acq_int(&que->sc->recovery_mode)) 3452 return (EPERM); 3453 3454 reg = IXGBE_READ_REG(&que->sc->hw, IXGBE_EITR(que->msix)); 3455 usec = ((reg & 0x0FF8) >> 3); 3456 if (usec > 0) 3457 rate = 500000 / usec; 3458 else 3459 rate = 0; 3460 error = sysctl_handle_int(oidp, &rate, 0, req); 3461 if (error || !req->newptr) 3462 return error; 3463 reg &= ~0xfff; /* default, no limitation */ 3464 ixgbe_max_interrupt_rate = 0; 3465 if (rate > 0 && rate < 500000) { 3466 if (rate < 1000) 3467 rate = 1000; 3468 ixgbe_max_interrupt_rate = rate; 3469 reg |= ((4000000/rate) & 0xff8); 3470 } 3471 IXGBE_WRITE_REG(&que->sc->hw, IXGBE_EITR(que->msix), reg); 3472 3473 return (0); 3474 } /* ixgbe_sysctl_interrupt_rate_handler */ 3475 3476 /************************************************************************ 3477 * ixgbe_debug_dump_print_cluster 3478 ************************************************************************/ 3479 static u8 3480 ixgbe_debug_dump_print_cluster(struct ixgbe_softc *sc, struct sbuf *sbuf, 3481 u8 cluster_id) 3482 { 3483 u16 data_buf_size = IXGBE_ACI_MAX_BUFFER_SIZE; 3484 device_t dev = sc->dev; 3485 struct ixgbe_hw *hw = &sc->hw; 3486 const u8 reserved_buf[8] = {}; 3487 int max_aci_calls = 1000; 3488 int error, counter = 0; 3489 u8 *data_buf; 3490 3491 /* Input parameters / loop variables */ 3492 u16 table_id = 0; 3493 u32 offset = 0; 3494 3495 /* Data returned from ACI command */ 3496 u16 ret_buf_size = 0; 3497 u16 ret_next_cluster = 0; 3498 u16 ret_next_table = 0; 3499 u32 ret_next_index = 0; 3500 3501 data_buf = (u8 *)malloc(data_buf_size, M_IXGBE, M_NOWAIT | M_ZERO); 3502 if (!data_buf) 3503 return (0); 3504 3505 DEBUGOUT2("%s: dumping cluster id (relative) %d\n", 3506 __func__, cluster_id); 3507 3508 do { 3509 DEBUGOUT3("table_id 0x%04x offset 0x%08x buf_size %d\n", 3510 table_id, offset, data_buf_size); 3511 3512 error = ixgbe_aci_get_internal_data(hw, cluster_id, table_id, 3513 offset, data_buf, data_buf_size, &ret_buf_size, 3514 &ret_next_cluster, &ret_next_table, &ret_next_index); 3515 if (error) { 3516 device_printf(dev, 3517 "%s: Failed to get internal FW/HW data, error: %d, " 3518 "last aci status: %d\n", 3519 __func__, error, hw->aci.last_status); 3520 break; 3521 } 3522 3523 DEBUGOUT3("ret_table_id 0x%04x ret_offset 0x%08x " 3524 "ret_buf_size %d\n", 3525 ret_next_table, ret_next_index, ret_buf_size); 3526 3527 /* Print cluster id */ 3528 u32 print_cluster_id = (u32)cluster_id; 3529 sbuf_bcat(sbuf, &print_cluster_id, sizeof(print_cluster_id)); 3530 /* Print table id */ 3531 u32 print_table_id = (u32)table_id; 3532 sbuf_bcat(sbuf, &print_table_id, sizeof(print_table_id)); 3533 /* Print table length */ 3534 u32 print_table_length = (u32)ret_buf_size; 3535 sbuf_bcat(sbuf, &print_table_length, 3536 sizeof(print_table_length)); 3537 /* Print current offset */ 3538 u32 print_curr_offset = offset; 3539 sbuf_bcat(sbuf, &print_curr_offset, sizeof(print_curr_offset)); 3540 /* Print reserved bytes */ 3541 sbuf_bcat(sbuf, reserved_buf, sizeof(reserved_buf)); 3542 /* Print data */ 3543 sbuf_bcat(sbuf, data_buf, ret_buf_size); 3544 3545 /* Prepare for the next loop spin */ 3546 memset(data_buf, 0, data_buf_size); 3547 3548 bool last_index = (ret_next_index == 0xffffffff); 3549 bool last_table = ((ret_next_table == 0xff || 3550 ret_next_table == 0xffff) && 3551 last_index); 3552 3553 if (last_table) { 3554 /* End of the cluster */ 3555 DEBUGOUT1("End of the cluster ID %d\n", cluster_id); 3556 break; 3557 } else if (last_index) { 3558 /* End of the table */ 3559 table_id = ret_next_table; 3560 offset = 0; 3561 } else { 3562 /* More data left in the table */ 3563 offset = ret_next_index; 3564 } 3565 } while (++counter < max_aci_calls); 3566 3567 if (counter >= max_aci_calls) 3568 device_printf(dev, "Exceeded nr of ACI calls for cluster %d\n", 3569 cluster_id); 3570 3571 free(data_buf, M_IXGBE); 3572 3573 return (++cluster_id); 3574 } /* ixgbe_print_debug_dump_cluster */ 3575 3576 /************************************************************************ 3577 * ixgbe_sysctl_debug_dump_set_clusters 3578 * 3579 * Sets the cluster to dump from FW when Debug Dump requested. 3580 ************************************************************************/ 3581 static int 3582 ixgbe_sysctl_debug_dump_set_clusters(SYSCTL_HANDLER_ARGS) 3583 { 3584 struct ixgbe_softc *sc = (struct ixgbe_softc *)arg1; 3585 u32 clusters = sc->debug_dump_cluster_mask; 3586 device_t dev = sc->dev; 3587 int error; 3588 3589 error = sysctl_handle_32(oidp, &clusters, 0, req); 3590 if ((error) || !req->newptr) 3591 return (error); 3592 3593 if (clusters & ~(IXGBE_DBG_DUMP_VALID_CLUSTERS_MASK)) { 3594 device_printf(dev, 3595 "%s: Unrecognized parameter: %u\n", 3596 __func__, clusters); 3597 sc->debug_dump_cluster_mask = 3598 IXGBE_ACI_DBG_DUMP_CLUSTER_ID_INVALID; 3599 return (EINVAL); 3600 } 3601 3602 sc->debug_dump_cluster_mask = clusters; 3603 3604 return (0); 3605 } /* ixgbe_sysctl_debug_dump_set_clusters */ 3606 3607 /************************************************************************ 3608 * ixgbe_sysctl_dump_debug_dump 3609 ************************************************************************/ 3610 static int 3611 ixgbe_sysctl_dump_debug_dump(SYSCTL_HANDLER_ARGS) 3612 { 3613 struct ixgbe_softc *sc = (struct ixgbe_softc *)arg1; 3614 device_t dev = sc->dev; 3615 struct sbuf *sbuf; 3616 int error = 0; 3617 3618 UNREFERENCED_PARAMETER(arg2); 3619 3620 if (!sc->do_debug_dump) { 3621 if (req->oldptr == NULL && req->newptr == NULL) { 3622 error = SYSCTL_OUT(req, 0, 0); 3623 return (error); 3624 } 3625 3626 char input_buf[2] = ""; 3627 error = sysctl_handle_string(oidp, input_buf, 3628 sizeof(input_buf), req); 3629 if ((error) || (req->newptr == NULL)) 3630 return (error); 3631 3632 if (input_buf[0] == '1') { 3633 if (sc->debug_dump_cluster_mask == 3634 IXGBE_ACI_DBG_DUMP_CLUSTER_ID_INVALID) { 3635 device_printf(dev, 3636 "Debug Dump failed because an invalid " 3637 "cluster was specified.\n"); 3638 return (EINVAL); 3639 } 3640 3641 sc->do_debug_dump = true; 3642 return (0); 3643 } 3644 3645 return (EINVAL); 3646 } 3647 3648 /* Caller just wants the upper bound for size */ 3649 if (req->oldptr == NULL && req->newptr == NULL) { 3650 size_t est_output_len = IXGBE_DBG_DUMP_BASE_SIZE; 3651 if (sc->debug_dump_cluster_mask & 0x2) 3652 est_output_len += IXGBE_DBG_DUMP_BASE_SIZE; 3653 error = SYSCTL_OUT(req, 0, est_output_len); 3654 return (error); 3655 } 3656 3657 sbuf = sbuf_new_for_sysctl(NULL, NULL, 128, req); 3658 sbuf_clear_flags(sbuf, SBUF_INCLUDENUL); 3659 3660 DEBUGOUT("FW Debug Dump running...\n"); 3661 3662 if (sc->debug_dump_cluster_mask) { 3663 for (u8 id = 0; id <= IXGBE_ACI_DBG_DUMP_CLUSTER_ID_MAX; id++) { 3664 if (sc->debug_dump_cluster_mask & BIT(id)) { 3665 DEBUGOUT1("Dumping cluster ID %u...\n", id); 3666 ixgbe_debug_dump_print_cluster(sc, sbuf, id); 3667 } 3668 } 3669 } else { 3670 u8 next_cluster_id = 0; 3671 do { 3672 DEBUGOUT1("Dumping cluster ID %u...\n", 3673 next_cluster_id); 3674 next_cluster_id = ixgbe_debug_dump_print_cluster(sc, 3675 sbuf, next_cluster_id); 3676 } while (next_cluster_id != 0 && 3677 next_cluster_id <= IXGBE_ACI_DBG_DUMP_CLUSTER_ID_MAX); 3678 } 3679 3680 sbuf_finish(sbuf); 3681 sbuf_delete(sbuf); 3682 3683 sc->do_debug_dump = false; 3684 3685 return (error); 3686 } /* ixgbe_sysctl_dump_debug_dump */ 3687 3688 /************************************************************************ 3689 * ixgbe_add_debug_dump_sysctls 3690 ************************************************************************/ 3691 static void 3692 ixgbe_add_debug_dump_sysctls(struct ixgbe_softc *sc) 3693 { 3694 struct sysctl_oid_list *debug_list, *dump_list; 3695 struct sysctl_oid *dump_node; 3696 struct sysctl_ctx_list *ctx; 3697 device_t dev = sc->dev; 3698 3699 ctx = device_get_sysctl_ctx(dev); 3700 debug_list = SYSCTL_CHILDREN(sc->debug_sysctls); 3701 3702 dump_node = SYSCTL_ADD_NODE(ctx, debug_list, OID_AUTO, "dump", 3703 CTLFLAG_RD, NULL, "Internal FW/HW Dump"); 3704 dump_list = SYSCTL_CHILDREN(dump_node); 3705 3706 SYSCTL_ADD_PROC(ctx, dump_list, OID_AUTO, "clusters", 3707 CTLTYPE_U32 | CTLFLAG_RW, sc, 0, 3708 ixgbe_sysctl_debug_dump_set_clusters, "SU", 3709 IXGBE_SYSCTL_DESC_DEBUG_DUMP_SET_CLUSTER); 3710 3711 SYSCTL_ADD_PROC(ctx, dump_list, OID_AUTO, "dump", 3712 CTLTYPE_STRING | CTLFLAG_RW | CTLFLAG_MPSAFE, sc, 0, 3713 ixgbe_sysctl_dump_debug_dump, "", 3714 IXGBE_SYSCTL_DESC_DUMP_DEBUG_DUMP); 3715 } /* ixgbe_add_debug_dump_sysctls */ 3716 3717 static void 3718 ixgbe_add_debug_sysctls(struct ixgbe_softc *sc) 3719 { 3720 struct sysctl_oid_list *ctx_list; 3721 struct sysctl_ctx_list *ctx; 3722 device_t dev = sc->dev; 3723 3724 ctx = device_get_sysctl_ctx(dev); 3725 ctx_list = SYSCTL_CHILDREN(device_get_sysctl_tree(dev)); 3726 3727 sc->debug_sysctls = SYSCTL_ADD_NODE(ctx, ctx_list, OID_AUTO, "debug", 3728 CTLFLAG_RD, NULL, "Debug Sysctls"); 3729 3730 if (sc->feat_en & IXGBE_FEATURE_DBG_DUMP) 3731 ixgbe_add_debug_dump_sysctls(sc); 3732 3733 if (sc->feat_en & IXGBE_FEATURE_FW_LOGGING) 3734 ixgbe_add_fw_logging_tunables(sc, sc->debug_sysctls); 3735 } /* ixgbe_add_debug_sysctls */ 3736 3737 /************************************************************************ 3738 * ixgbe_add_device_sysctls 3739 ************************************************************************/ 3740 static void 3741 ixgbe_add_device_sysctls(if_ctx_t ctx) 3742 { 3743 struct ixgbe_softc *sc = iflib_get_softc(ctx); 3744 device_t dev = iflib_get_dev(ctx); 3745 struct ixgbe_hw *hw = &sc->hw; 3746 struct sysctl_oid_list *child; 3747 struct sysctl_ctx_list *ctx_list; 3748 3749 ctx_list = device_get_sysctl_ctx(dev); 3750 child = SYSCTL_CHILDREN(device_get_sysctl_tree(dev)); 3751 3752 /* Sysctls for all devices */ 3753 SYSCTL_ADD_PROC(ctx_list, child, OID_AUTO, "fc", 3754 CTLTYPE_INT | CTLFLAG_RW, 3755 sc, 0, ixgbe_sysctl_flowcntl, "I", 3756 IXGBE_SYSCTL_DESC_SET_FC); 3757 3758 SYSCTL_ADD_PROC(ctx_list, child, OID_AUTO, "advertise_speed", 3759 CTLTYPE_INT | CTLFLAG_RW, 3760 sc, 0, ixgbe_sysctl_advertise, "I", 3761 IXGBE_SYSCTL_DESC_ADV_SPEED); 3762 if (hw->mac.type == ixgbe_mac_82599EB || 3763 hw->mac.type == ixgbe_mac_X540) { 3764 SYSCTL_ADD_U64(ctx_list, child, OID_AUTO, 3765 "iov_dma_abort_events", CTLFLAG_RD, 3766 &sc->iov_dma_abort_events, 0, 3767 "VF invalid-DMA events"); 3768 SYSCTL_ADD_U64(ctx_list, child, OID_AUTO, 3769 "iov_dma_abort_flr_failures", CTLFLAG_RD, 3770 &sc->iov_dma_abort_flr_failures, 0, 3771 "Failed VF reset attempts after invalid-DMA events"); 3772 SYSCTL_ADD_U64(ctx_list, child, OID_AUTO, 3773 "iov_dma_abort_quarantines", CTLFLAG_RD, 3774 &sc->iov_dma_abort_quarantines, 0, 3775 "VFs quarantined after repeated invalid-DMA events"); 3776 SYSCTL_ADD_U64(ctx_list, child, OID_AUTO, 3777 "iov_quarantined_vfs", CTLFLAG_RD, 3778 &sc->iov_quarantined_vfs, 0, 3779 "Bitmap of quarantined VF pools"); 3780 } 3781 3782 sc->enable_aim = ixgbe_enable_aim; 3783 SYSCTL_ADD_INT(ctx_list, child, OID_AUTO, "enable_aim", CTLFLAG_RW, 3784 &sc->enable_aim, 0, "Interrupt Moderation"); 3785 3786 SYSCTL_ADD_PROC(ctx_list, child, OID_AUTO, "fw_version", 3787 CTLTYPE_STRING | CTLFLAG_RD, sc, 0, 3788 ixgbe_sysctl_print_fw_version, "A", "Prints FW/NVM Versions"); 3789 3790 SYSCTL_ADD_PROC(ctx_list, child, OID_AUTO, 3791 "tso_tcp_flags_mask_first_segment", 3792 CTLTYPE_UINT | CTLFLAG_RW | CTLFLAG_NEEDGIANT, 3793 sc, 0, ixgbe_sysctl_tso_tcp_flags_mask, "IU", 3794 "TSO TCP flags mask for first segment"); 3795 3796 SYSCTL_ADD_PROC(ctx_list, child, OID_AUTO, 3797 "tso_tcp_flags_mask_middle_segment", 3798 CTLTYPE_UINT | CTLFLAG_RW | CTLFLAG_NEEDGIANT, 3799 sc, 1, ixgbe_sysctl_tso_tcp_flags_mask, "IU", 3800 "TSO TCP flags mask for middle segment"); 3801 3802 SYSCTL_ADD_PROC(ctx_list, child, OID_AUTO, 3803 "tso_tcp_flags_mask_last_segment", 3804 CTLTYPE_UINT | CTLFLAG_RW | CTLFLAG_NEEDGIANT, 3805 sc, 2, ixgbe_sysctl_tso_tcp_flags_mask, "IU", 3806 "TSO TCP flags mask for last segment"); 3807 3808 #ifdef IXGBE_DEBUG 3809 /* testing sysctls (for all devices) */ 3810 SYSCTL_ADD_PROC(ctx_list, child, OID_AUTO, "power_state", 3811 CTLTYPE_INT | CTLFLAG_RW, 3812 sc, 0, ixgbe_sysctl_power_state, 3813 "I", "PCI Power State"); 3814 3815 SYSCTL_ADD_PROC(ctx_list, child, OID_AUTO, "print_rss_config", 3816 CTLTYPE_STRING | CTLFLAG_RD, sc, 0, 3817 ixgbe_sysctl_print_rss_config, "A", "Prints RSS Configuration"); 3818 #endif 3819 /* for X550 series devices */ 3820 if (hw->mac.type >= ixgbe_mac_X550) 3821 SYSCTL_ADD_PROC(ctx_list, child, OID_AUTO, "dmac", 3822 CTLTYPE_U16 | CTLFLAG_RW, 3823 sc, 0, ixgbe_sysctl_dmac, 3824 "I", "DMA Coalesce"); 3825 3826 /* for X552/X557-AT devices */ 3827 if (hw->device_id == IXGBE_DEV_ID_X550EM_X_10G_T) { 3828 struct sysctl_oid *phy_node; 3829 struct sysctl_oid_list *phy_list; 3830 3831 phy_node = SYSCTL_ADD_NODE(ctx_list, child, OID_AUTO, "phy", 3832 CTLFLAG_RD | CTLFLAG_MPSAFE, NULL, 3833 "External PHY sysctls"); 3834 phy_list = SYSCTL_CHILDREN(phy_node); 3835 3836 SYSCTL_ADD_PROC(ctx_list, phy_list, OID_AUTO, "temp", 3837 CTLTYPE_U16 | CTLFLAG_RD, 3838 sc, 0, ixgbe_sysctl_phy_temp, 3839 "I", "Current External PHY Temperature (Celsius)"); 3840 3841 SYSCTL_ADD_PROC(ctx_list, phy_list, OID_AUTO, 3842 "overtemp_occurred", 3843 CTLTYPE_U16 | CTLFLAG_RD, sc, 0, 3844 ixgbe_sysctl_phy_overtemp_occurred, "I", 3845 "External PHY High Temperature Event Occurred"); 3846 } 3847 3848 if (sc->feat_cap & IXGBE_FEATURE_EEE) { 3849 struct sysctl_oid *eee_node; 3850 struct sysctl_oid_list *eee_list; 3851 3852 SYSCTL_ADD_PROC(ctx_list, child, OID_AUTO, "eee_state", 3853 CTLTYPE_INT | CTLFLAG_RW, sc, 0, 3854 ixgbe_sysctl_eee_state, "I", "EEE Power Save State"); 3855 3856 eee_node = SYSCTL_ADD_NODE(ctx_list, child, OID_AUTO, "eee", 3857 CTLFLAG_RD | CTLFLAG_MPSAFE, NULL, 3858 "Energy Efficient Ethernet statistics"); 3859 eee_list = SYSCTL_CHILDREN(eee_node); 3860 SYSCTL_ADD_UQUAD(ctx_list, eee_list, OID_AUTO, "tx_lpi_count", 3861 CTLFLAG_RD, &sc->stats.pf.tlpic, "TX LPI event count"); 3862 SYSCTL_ADD_UQUAD(ctx_list, eee_list, OID_AUTO, "rx_lpi_count", 3863 CTLFLAG_RD, &sc->stats.pf.rlpic, "RX LPI event count"); 3864 } 3865 3866 ixgbe_add_debug_sysctls(sc); 3867 } /* ixgbe_add_device_sysctls */ 3868 3869 /************************************************************************ 3870 * ixgbe_allocate_pci_resources 3871 ************************************************************************/ 3872 static int 3873 ixgbe_allocate_pci_resources(if_ctx_t ctx) 3874 { 3875 struct ixgbe_softc *sc = iflib_get_softc(ctx); 3876 device_t dev = iflib_get_dev(ctx); 3877 int rid; 3878 3879 rid = PCIR_BAR(0); 3880 sc->pci_mem = bus_alloc_resource_any(dev, SYS_RES_MEMORY, &rid, 3881 RF_ACTIVE); 3882 3883 if (!(sc->pci_mem)) { 3884 device_printf(dev, 3885 "Unable to allocate bus resource: memory\n"); 3886 return (ENXIO); 3887 } 3888 3889 /* Save bus_space values for READ/WRITE_REG macros */ 3890 sc->osdep.mem_bus_space_tag = rman_get_bustag(sc->pci_mem); 3891 sc->osdep.mem_bus_space_handle = 3892 rman_get_bushandle(sc->pci_mem); 3893 /* Set hw values for shared code */ 3894 sc->hw.hw_addr = (u8 *)&sc->osdep.mem_bus_space_handle; 3895 3896 return (0); 3897 } /* ixgbe_allocate_pci_resources */ 3898 3899 /************************************************************************ 3900 * ixgbe_detach - Device removal routine 3901 * 3902 * Called when the driver is being removed. 3903 * Stops the adapter and deallocates all the resources 3904 * that were allocated for driver operation. 3905 * 3906 * return 0 on success, positive on failure 3907 ************************************************************************/ 3908 static int 3909 ixgbe_if_detach(if_ctx_t ctx) 3910 { 3911 struct ixgbe_softc *sc = iflib_get_softc(ctx); 3912 u32 ctrl_ext; 3913 3914 INIT_DEBUGOUT("ixgbe_detach: begin"); 3915 3916 sc->iov_recovery_stop = true; 3917 3918 ixgbe_setup_low_power_mode(ctx, false); 3919 3920 /* let hardware know driver is unloading */ 3921 ctrl_ext = IXGBE_READ_REG(&sc->hw, IXGBE_CTRL_EXT); 3922 ctrl_ext &= ~IXGBE_CTRL_EXT_DRV_LOAD; 3923 IXGBE_WRITE_REG(&sc->hw, IXGBE_CTRL_EXT, ctrl_ext); 3924 3925 callout_drain(&sc->fw_mode_timer); 3926 3927 if (sc->hw.mac.type == ixgbe_mac_E610) { 3928 ixgbe_disable_lse(sc); 3929 ixgbe_shutdown_aci(&sc->hw); 3930 } 3931 3932 ixgbe_free_pci_resources(ctx); 3933 3934 free(sc->mta, M_IXGBE); 3935 3936 return (0); 3937 } /* ixgbe_if_detach */ 3938 3939 static void 3940 ixgbe_prepare_wakeup(if_ctx_t ctx, bool arm_wake) 3941 { 3942 struct ixgbe_softc *sc = iflib_get_softc(ctx); 3943 struct ixgbe_hw *hw = &sc->hw; 3944 if_t ifp = iflib_get_ifp(ctx); 3945 int enabled; 3946 u32 wufc; 3947 3948 enabled = arm_wake ? 3949 if_getcapenable(ifp) & if_getcapabilities(ifp) & IFCAP_WOL : 0; 3950 wufc = 0; 3951 if ((enabled & IFCAP_WOL_MAGIC) != 0) 3952 wufc |= IXGBE_WUFC_MAG; 3953 if ((enabled & IFCAP_WOL_UCAST) != 0) 3954 wufc |= IXGBE_WUFC_EX; 3955 if ((enabled & IFCAP_WOL_MCAST) != 0) 3956 wufc |= IXGBE_WUFC_MC; 3957 sc->wol_filters = wufc; 3958 hw->wol_enabled = wufc != 0; 3959 3960 /* X550EM 10GBASE-T requires PHY reset suppression during the stop. */ 3961 if (hw->device_id == IXGBE_DEV_ID_X550EM_X_10G_T && 3962 hw->phy.ops.enter_lplu != NULL) 3963 hw->phy.reset_disable = true; 3964 } 3965 3966 static u_int 3967 ixgbe_wakeup_mta_apply(void *arg, struct sockaddr_dl *sdl, u_int idx __unused) 3968 { 3969 struct ixgbe_hw *hw = arg; 3970 3971 ixgbe_set_mta(hw, LLADDR(sdl)); 3972 return (1); 3973 } 3974 3975 /* Restore multicast hashes needed by directed and multicast-magic wake. */ 3976 static void 3977 ixgbe_configure_wakeup_mta(if_ctx_t ctx) 3978 { 3979 struct ixgbe_softc *sc = iflib_get_softc(ctx); 3980 struct ixgbe_hw *hw = &sc->hw; 3981 u_int i, mcnt; 3982 3983 bzero(hw->mac.mta_shadow, sizeof(hw->mac.mta_shadow)); 3984 hw->addr_ctrl.mta_in_use = 0; 3985 mcnt = if_foreach_llmaddr(iflib_get_ifp(ctx), 3986 ixgbe_wakeup_mta_apply, hw); 3987 hw->addr_ctrl.num_mc_addrs = mcnt; 3988 for (i = 0; i < hw->mac.mcft_size; i++) 3989 IXGBE_WRITE_REG_ARRAY(hw, IXGBE_MTA(0), i, 3990 hw->mac.mta_shadow[i]); 3991 IXGBE_WRITE_REG(hw, IXGBE_MCSTCTRL, 3992 (hw->addr_ctrl.mta_in_use != 0 ? IXGBE_MCSTCTRL_MFE : 0) | 3993 hw->mac.mc_filter_type); 3994 } 3995 3996 /************************************************************************ 3997 * ixgbe_setup_low_power_mode - LPLU/WoL preparation 3998 * 3999 * Prepare the adapter/port for LPLU and/or WoL 4000 ************************************************************************/ 4001 static int 4002 ixgbe_setup_low_power_mode(if_ctx_t ctx, bool arm_wake) 4003 { 4004 struct ixgbe_softc *sc = iflib_get_softc(ctx); 4005 struct ixgbe_hw *hw = &sc->hw; 4006 device_t dev = iflib_get_dev(ctx); 4007 u32 fctrl, grc, wufc; 4008 s32 error = 0; 4009 4010 /* Snapshot wake policy before the terminal stop clears hardware state. */ 4011 ixgbe_prepare_wakeup(ctx, arm_wake); 4012 wufc = sc->wol_filters; 4013 ixgbe_if_stop(ctx); 4014 4015 /* Limit power management flow to X550EM baseT */ 4016 if (hw->device_id == IXGBE_DEV_ID_X550EM_X_10G_T && 4017 hw->phy.ops.enter_lplu) { 4018 /* X550EM baseT adapters need a special LPLU flow. */ 4019 error = hw->phy.ops.enter_lplu(hw); 4020 if (error) 4021 device_printf(dev, "Error entering LPLU: %d\n", 4022 error); 4023 hw->phy.reset_disable = false; 4024 error = 0; 4025 } 4026 4027 /* Disable the 82599 link only when actually entering D3. */ 4028 if (hw->mac.type == ixgbe_mac_82599EB) 4029 ixgbe_stop_mac_link_on_d3_82599(hw); 4030 4031 /* 4032 * Make ifconfig's ACPI policy authoritative. All supported families, 4033 * including E610, implement the standard filters in WUFC; leaving the 4034 * NVM-selected APM path enabled would permit an unrequested magic wake. 4035 */ 4036 if (hw->mac.type != ixgbe_mac_82598EB) { 4037 grc = IXGBE_READ_REG(hw, IXGBE_GRC_BY_MAC(hw)); 4038 IXGBE_WRITE_REG(hw, IXGBE_GRC_BY_MAC(hw), 4039 grc & ~IXGBE_GRC_APME); 4040 } 4041 IXGBE_WRITE_REG(hw, IXGBE_WUFC, 0); 4042 IXGBE_WRITE_REG(hw, IXGBE_WUC, 0); 4043 IXGBE_WRITE_REG(hw, IXGBE_WUS, 0xffffffff); 4044 pci_clear_pme(dev); 4045 if (wufc != 0) { 4046 bcopy(if_getlladdr(iflib_get_ifp(ctx)), hw->mac.addr, 4047 IXGBE_ETH_LENGTH_OF_ADDRESS); 4048 error = ixgbe_set_rar(hw, 0, hw->mac.addr, sc->pool, 4049 IXGBE_RAH_AV); 4050 if (error != IXGBE_SUCCESS) { 4051 device_printf(dev, 4052 "Could not restore unicast wake address: %d\n", error); 4053 sc->wol_filters = 0; 4054 hw->wol_enabled = false; 4055 goto no_wake; 4056 } 4057 4058 /* 82599 SFP+ ports need the laser for an optical wake packet. */ 4059 ixgbe_enable_tx_laser(hw); 4060 4061 /* Rebuild address filtering erased by the terminal reset. */ 4062 ixgbe_configure_wakeup_mta(ctx); 4063 fctrl = IXGBE_READ_REG(hw, IXGBE_FCTRL); 4064 fctrl |= IXGBE_FCTRL_BAM | IXGBE_FCTRL_MPE; 4065 IXGBE_WRITE_REG(hw, IXGBE_FCTRL, fctrl); 4066 4067 IXGBE_WRITE_REG(hw, IXGBE_WUFC, wufc); 4068 IXGBE_WRITE_REG(hw, IXGBE_WUC, 4069 IXGBE_WUC_WKEN | IXGBE_WUC_PME_EN); 4070 pci_enable_pme(dev); 4071 return (0); 4072 } 4073 4074 no_wake: 4075 ixgbe_set_phy_power(hw, false); 4076 return (error == IXGBE_SUCCESS ? 0 : EIO); 4077 } /* ixgbe_setup_low_power_mode */ 4078 4079 /************************************************************************ 4080 * ixgbe_shutdown - Shutdown entry point 4081 ************************************************************************/ 4082 static int 4083 ixgbe_if_shutdown(if_ctx_t ctx) 4084 { 4085 int error = 0; 4086 4087 INIT_DEBUGOUT("ixgbe_shutdown: begin"); 4088 4089 error = ixgbe_setup_low_power_mode(ctx, true); 4090 if (error != 0) 4091 device_printf(iflib_get_dev(ctx), 4092 "Wake configuration failed during shutdown: %d\n", error); 4093 return (0); 4094 } /* ixgbe_if_shutdown */ 4095 4096 /************************************************************************ 4097 * ixgbe_suspend 4098 * 4099 * From D0 to D3 4100 ************************************************************************/ 4101 static int 4102 ixgbe_if_suspend(if_ctx_t ctx) 4103 { 4104 int error = 0; 4105 4106 INIT_DEBUGOUT("ixgbe_suspend: begin"); 4107 4108 error = ixgbe_setup_low_power_mode(ctx, true); 4109 4110 return (error); 4111 } /* ixgbe_if_suspend */ 4112 4113 /************************************************************************ 4114 * ixgbe_resume 4115 * 4116 * From D3 to D0 4117 ************************************************************************/ 4118 static int 4119 ixgbe_if_resume(if_ctx_t ctx) 4120 { 4121 struct ixgbe_softc *sc = iflib_get_softc(ctx); 4122 device_t dev = iflib_get_dev(ctx); 4123 if_t ifp = iflib_get_ifp(ctx); 4124 struct ixgbe_hw *hw = &sc->hw; 4125 u32 wus; 4126 4127 INIT_DEBUGOUT("ixgbe_resume: begin"); 4128 4129 /* Read & clear WUS register */ 4130 wus = IXGBE_READ_REG(hw, IXGBE_WUS); 4131 if (wus) 4132 device_printf(dev, "Woken up by (WUS): %#010x\n", 4133 wus); 4134 /* Remove every device wake source before clearing PCI PME. */ 4135 IXGBE_WRITE_REG(hw, IXGBE_WUFC, 0); 4136 if (hw->mac.type != ixgbe_mac_82598EB) 4137 IXGBE_WRITE_REG(hw, IXGBE_GRC_BY_MAC(hw), 4138 IXGBE_READ_REG(hw, IXGBE_GRC_BY_MAC(hw)) & 4139 ~IXGBE_GRC_APME); 4140 IXGBE_WRITE_REG(hw, IXGBE_WUC, 0); 4141 IXGBE_WRITE_REG(hw, IXGBE_WUS, 0xffffffff); 4142 pci_clear_pme(dev); 4143 hw->wol_enabled = false; 4144 sc->wol_filters = 0; 4145 4146 /* 4147 * Required after D3->D0 transition; 4148 * will re-advertise all previous advertised speeds 4149 */ 4150 if (if_getflags(ifp) & IFF_UP) 4151 ixgbe_if_init(ctx); 4152 4153 return (0); 4154 } /* ixgbe_if_resume */ 4155 4156 /************************************************************************ 4157 * ixgbe_if_mtu_set - Ioctl mtu entry point 4158 * 4159 * Return 0 on success, EINVAL on failure 4160 ************************************************************************/ 4161 static int 4162 ixgbe_if_mtu_set(if_ctx_t ctx, uint32_t mtu) 4163 { 4164 struct ixgbe_softc *sc = iflib_get_softc(ctx); 4165 int error = 0; 4166 4167 IOCTL_DEBUGOUT("ioctl: SIOCIFMTU (Set Interface MTU)"); 4168 4169 if (mtu > IXGBE_MAX_MTU) { 4170 error = EINVAL; 4171 } else { 4172 sc->max_frame_size = mtu + IXGBE_MTU_HDR; 4173 } 4174 4175 return error; 4176 } /* ixgbe_if_mtu_set */ 4177 4178 /************************************************************************ 4179 * ixgbe_if_crcstrip_set 4180 ************************************************************************/ 4181 static void 4182 ixgbe_if_crcstrip_set(if_ctx_t ctx, int onoff, int crcstrip) 4183 { 4184 struct ixgbe_softc *sc = iflib_get_softc(ctx); 4185 struct ixgbe_hw *hw = &sc->hw; 4186 /* crc stripping is set in two places: 4187 * IXGBE_HLREG0 (modified on init_locked and hw reset) 4188 * IXGBE_RDRXCTL (set by the original driver in 4189 * ixgbe_setup_hw_rsc() called in init_locked. 4190 * We disable the setting when netmap is compiled in). 4191 * We update the values here, but also in ixgbe.c because 4192 * init_locked sometimes is called outside our control. 4193 */ 4194 uint32_t hl, rxc; 4195 4196 hl = IXGBE_READ_REG(hw, IXGBE_HLREG0); 4197 rxc = IXGBE_READ_REG(hw, IXGBE_RDRXCTL); 4198 #ifdef NETMAP 4199 if (netmap_verbose) 4200 D("%s read HLREG 0x%x rxc 0x%x", 4201 onoff ? "enter" : "exit", hl, rxc); 4202 #endif 4203 /* hw requirements ... */ 4204 rxc &= ~IXGBE_RDRXCTL_RSCFRSTSIZE; 4205 rxc |= IXGBE_RDRXCTL_RSCACKC; 4206 if (onoff && !crcstrip) { 4207 /* keep the crc. Fast rx */ 4208 hl &= ~IXGBE_HLREG0_RXCRCSTRP; 4209 rxc &= ~IXGBE_RDRXCTL_CRCSTRIP; 4210 } else { 4211 /* reset default mode */ 4212 hl |= IXGBE_HLREG0_RXCRCSTRP; 4213 rxc |= IXGBE_RDRXCTL_CRCSTRIP; 4214 } 4215 #ifdef NETMAP 4216 if (netmap_verbose) 4217 D("%s write HLREG 0x%x rxc 0x%x", 4218 onoff ? "enter" : "exit", hl, rxc); 4219 #endif 4220 IXGBE_WRITE_REG(hw, IXGBE_HLREG0, hl); 4221 IXGBE_WRITE_REG(hw, IXGBE_RDRXCTL, rxc); 4222 } /* ixgbe_if_crcstrip_set */ 4223 4224 /********************************************************************* 4225 * ixgbe_if_init - Init entry point 4226 * 4227 * Used in two ways: It is used by the stack as an init 4228 * entry point in network interface structure. It is also 4229 * used by the driver as a hw/sw initialization routine to 4230 * get to a consistent state. 4231 * 4232 * Return 0 on success, positive on failure 4233 **********************************************************************/ 4234 void 4235 ixgbe_if_init(if_ctx_t ctx) 4236 { 4237 struct ixgbe_softc *sc = iflib_get_softc(ctx); 4238 if_t ifp = iflib_get_ifp(ctx); 4239 device_t dev = iflib_get_dev(ctx); 4240 struct ixgbe_hw *hw = &sc->hw; 4241 struct ix_rx_queue *rx_que; 4242 struct ix_tx_queue *tx_que; 4243 u32 txdctl, mhadd; 4244 u32 rxdctl, rxctrl; 4245 u32 ctrl_ext; 4246 4247 int i, j, err; 4248 4249 INIT_DEBUGOUT("ixgbe_if_init: begin"); 4250 if (atomic_load_acq_int(&sc->recovery_mode)) { 4251 iflib_init_failed(ctx); 4252 return; 4253 } 4254 /* Leave an overheated adapter stopped until an operator retries. */ 4255 if (sc->overtemp_shutdown_pending) { 4256 sc->overtemp_shutdown_pending = false; 4257 iflib_init_failed(ctx); 4258 return; 4259 } 4260 4261 /* Preserve the largest frame requested by the PF or an active VF. */ 4262 sc->max_frame_size = if_getmtu(ifp) + IXGBE_MTU_HDR; 4263 ixgbe_recalculate_max_frame(sc); 4264 4265 /* Queue indices may change with IOV mode */ 4266 ixgbe_align_all_queue_indices(sc); 4267 4268 /* reprogram the RAR[0] in case user changed it. */ 4269 ixgbe_set_rar(hw, 0, hw->mac.addr, sc->pool, IXGBE_RAH_AV); 4270 4271 /* Get the latest mac address, User can use a LAA */ 4272 bcopy(if_getlladdr(ifp), hw->mac.addr, IXGBE_ETH_LENGTH_OF_ADDRESS); 4273 ixgbe_set_rar(hw, 0, hw->mac.addr, sc->pool, 1); 4274 hw->addr_ctrl.rar_used_count = 1; 4275 4276 ixgbe_init_hw(hw); 4277 sc->iov_mta_valid = false; 4278 sc->iov_vfta_valid = false; 4279 4280 ixgbe_initialize_iov(sc); 4281 4282 ixgbe_initialize_transmit_units(ctx); 4283 4284 /* Setup Multicast table */ 4285 ixgbe_if_multi_set(ctx); 4286 4287 /* Determine the correct mbuf pool, based on frame size */ 4288 sc->rx_mbuf_sz = iflib_get_rx_mbuf_sz(ctx); 4289 4290 /* Configure RX settings */ 4291 ixgbe_initialize_receive_units(ctx); 4292 4293 /* 4294 * Initialize the deferred administrative request mask. 4295 */ 4296 atomic_store_rel_32(&sc->task_requests, 0); 4297 4298 /* Enable SDP & MSI-X interrupts based on adapter */ 4299 ixgbe_config_gpie(sc); 4300 4301 /* Set MTU size */ 4302 if (sc->max_frame_size > ETHER_MAX_LEN) { 4303 /* aka IXGBE_MAXFRS on 82599 and newer */ 4304 mhadd = IXGBE_READ_REG(hw, IXGBE_MHADD); 4305 mhadd &= ~IXGBE_MHADD_MFS_MASK; 4306 mhadd |= sc->max_frame_size << IXGBE_MHADD_MFS_SHIFT; 4307 IXGBE_WRITE_REG(hw, IXGBE_MHADD, mhadd); 4308 } 4309 4310 /* Now enable all the queues */ 4311 for (i = 0, tx_que = sc->tx_queues; i < sc->num_tx_queues; 4312 i++, tx_que++) { 4313 struct tx_ring *txr = &tx_que->txr; 4314 4315 txdctl = IXGBE_READ_REG(hw, IXGBE_TXDCTL(txr->me)); 4316 txdctl &= ~IXGBE_TXDCTL_THRESH_MASK; 4317 txdctl |= IXGBE_TXDCTL_ENABLE | IXGBE_TXDCTL_THRESH_DEFAULT; 4318 /* 4319 * When the internal queue falls below PTHRESH (32), 4320 * start prefetching as long as there are at least 4321 * HTHRESH (1) buffers ready. Leave WTHRESH at zero 4322 * so that writeback follows iflib's sparse RS bits. 4323 * Prefetching enables tx line rate even with 1 queue. 4324 */ 4325 IXGBE_WRITE_REG(hw, IXGBE_TXDCTL(txr->me), txdctl); 4326 } 4327 4328 for (i = 0, rx_que = sc->rx_queues; i < sc->num_rx_queues; 4329 i++, rx_que++) { 4330 struct rx_ring *rxr = &rx_que->rxr; 4331 4332 rxdctl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(rxr->me)); 4333 if (hw->mac.type == ixgbe_mac_82598EB) { 4334 /* 4335 * PTHRESH = 21 4336 * HTHRESH = 4 4337 * WTHRESH = 8 4338 */ 4339 rxdctl &= ~0x3FFFFF; 4340 rxdctl |= 0x080420; 4341 } 4342 rxdctl |= IXGBE_RXDCTL_ENABLE; 4343 IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(rxr->me), rxdctl); 4344 for (j = 0; j < 10; j++) { 4345 if (IXGBE_READ_REG(hw, IXGBE_RXDCTL(rxr->me)) & 4346 IXGBE_RXDCTL_ENABLE) 4347 break; 4348 else 4349 msec_delay(1); 4350 } 4351 wmb(); 4352 } 4353 4354 /* Enable Receive engine */ 4355 rxctrl = IXGBE_READ_REG(hw, IXGBE_RXCTRL); 4356 if (hw->mac.type == ixgbe_mac_82598EB) 4357 rxctrl |= IXGBE_RXCTRL_DMBYPS; 4358 rxctrl |= IXGBE_RXCTRL_RXEN; 4359 ixgbe_enable_rx_dma(hw, rxctrl); 4360 4361 /* Set up MSI/MSI-X routing */ 4362 if (ixgbe_enable_msix) { 4363 ixgbe_configure_ivars(sc); 4364 /* Set up auto-mask */ 4365 if (hw->mac.type == ixgbe_mac_82598EB) 4366 IXGBE_WRITE_REG(hw, IXGBE_EIAM, IXGBE_EICS_RTX_QUEUE); 4367 else { 4368 IXGBE_WRITE_REG(hw, IXGBE_EIAM_EX(0), 0xFFFFFFFF); 4369 IXGBE_WRITE_REG(hw, IXGBE_EIAM_EX(1), 0xFFFFFFFF); 4370 } 4371 } else { /* Simple settings for Legacy/MSI */ 4372 ixgbe_set_ivar(sc, 0, 0, 0); 4373 ixgbe_set_ivar(sc, 0, 0, 1); 4374 IXGBE_WRITE_REG(hw, IXGBE_EIAM, IXGBE_EICS_RTX_QUEUE); 4375 } 4376 4377 ixgbe_init_fdir(sc); 4378 4379 /* 4380 * Check on any SFP devices that 4381 * need to be kick-started 4382 */ 4383 if (hw->phy.type == ixgbe_phy_none) { 4384 err = hw->phy.ops.identify(hw); 4385 if (err == IXGBE_ERR_SFP_NOT_SUPPORTED) { 4386 device_printf(dev, 4387 "Unsupported SFP+ module type was detected.\n"); 4388 return; 4389 } 4390 } 4391 4392 /* Set moderation on the Link interrupt */ 4393 IXGBE_WRITE_REG(hw, IXGBE_EITR(sc->vector), IXGBE_LINK_ITR); 4394 4395 /* Enable power to the phy. */ 4396 ixgbe_set_phy_power(hw, true); 4397 4398 /* Config/Enable Link */ 4399 ixgbe_config_link(ctx); 4400 4401 /* Hardware Packet Buffer & Flow Control setup */ 4402 ixgbe_config_delay_values(sc); 4403 4404 /* Initialize the FC settings */ 4405 ixgbe_start_hw(hw); 4406 4407 /* Set up VLAN support and filter */ 4408 ixgbe_setup_vlan_hw_support(ctx); 4409 4410 /* Setup DMA Coalescing */ 4411 ixgbe_config_dmac(sc); 4412 4413 if (sc->feat_en & IXGBE_FEATURE_SRIOV) { 4414 ixgbe_enable_mdd(hw); 4415 ixgbe_activate_vfs(sc); 4416 } 4417 4418 /* And now turn on interrupts */ 4419 ixgbe_if_enable_intr(ctx); 4420 4421 /* Enable the use of the MBX by the VF's */ 4422 if (sc->feat_en & IXGBE_FEATURE_SRIOV) { 4423 ctrl_ext = IXGBE_READ_REG(hw, IXGBE_CTRL_EXT); 4424 ctrl_ext |= IXGBE_CTRL_EXT_PFRSTD; 4425 IXGBE_WRITE_REG(hw, IXGBE_CTRL_EXT, ctrl_ext); 4426 } 4427 4428 } /* ixgbe_init_locked */ 4429 4430 /************************************************************************ 4431 * ixgbe_set_ivar 4432 * 4433 * Setup the correct IVAR register for a particular MSI-X interrupt 4434 * (yes this is all very magic and confusing :) 4435 * - entry is the register array entry 4436 * - vector is the MSI-X vector for this queue 4437 * - type is RX/TX/MISC 4438 ************************************************************************/ 4439 static void 4440 ixgbe_set_ivar(struct ixgbe_softc *sc, u8 entry, u8 vector, s8 type) 4441 { 4442 struct ixgbe_hw *hw = &sc->hw; 4443 u32 ivar, index; 4444 4445 vector |= IXGBE_IVAR_ALLOC_VAL; 4446 4447 switch (hw->mac.type) { 4448 case ixgbe_mac_82598EB: 4449 if (type == -1) 4450 entry = IXGBE_IVAR_OTHER_CAUSES_INDEX; 4451 else 4452 entry += (type * 64); 4453 index = (entry >> 2) & 0x1F; 4454 ivar = IXGBE_READ_REG(hw, IXGBE_IVAR(index)); 4455 ivar &= ~(0xFF << (8 * (entry & 0x3))); 4456 ivar |= (vector << (8 * (entry & 0x3))); 4457 IXGBE_WRITE_REG(&sc->hw, IXGBE_IVAR(index), ivar); 4458 break; 4459 case ixgbe_mac_82599EB: 4460 case ixgbe_mac_X540: 4461 case ixgbe_mac_X550: 4462 case ixgbe_mac_X550EM_x: 4463 case ixgbe_mac_X550EM_a: 4464 case ixgbe_mac_E610: 4465 if (type == -1) { /* MISC IVAR */ 4466 index = (entry & 1) * 8; 4467 ivar = IXGBE_READ_REG(hw, IXGBE_IVAR_MISC); 4468 ivar &= ~(0xFF << index); 4469 ivar |= (vector << index); 4470 IXGBE_WRITE_REG(hw, IXGBE_IVAR_MISC, ivar); 4471 } else { /* RX/TX IVARS */ 4472 index = (16 * (entry & 1)) + (8 * type); 4473 ivar = IXGBE_READ_REG(hw, IXGBE_IVAR(entry >> 1)); 4474 ivar &= ~(0xFF << index); 4475 ivar |= (vector << index); 4476 IXGBE_WRITE_REG(hw, IXGBE_IVAR(entry >> 1), ivar); 4477 } 4478 default: 4479 break; 4480 } 4481 } /* ixgbe_set_ivar */ 4482 4483 /************************************************************************ 4484 * ixgbe_configure_ivars 4485 ************************************************************************/ 4486 static void 4487 ixgbe_configure_ivars(struct ixgbe_softc *sc) 4488 { 4489 struct ix_rx_queue *rx_que = sc->rx_queues; 4490 struct ix_tx_queue *tx_que = sc->tx_queues; 4491 u32 newitr; 4492 4493 if (ixgbe_max_interrupt_rate > 0) 4494 newitr = (4000000 / ixgbe_max_interrupt_rate) & 0x0FF8; 4495 else { 4496 /* 4497 * Disable DMA coalescing if interrupt moderation is 4498 * disabled. 4499 */ 4500 sc->dmac = 0; 4501 newitr = 0; 4502 } 4503 4504 for (int i = 0; i < sc->num_rx_queues; i++, rx_que++) { 4505 struct rx_ring *rxr = &rx_que->rxr; 4506 4507 /* First the RX queue entry */ 4508 ixgbe_set_ivar(sc, rxr->me, rx_que->msix, 0); 4509 4510 /* Set an Initial EITR value */ 4511 IXGBE_WRITE_REG(&sc->hw, IXGBE_EITR(rx_que->msix), newitr); 4512 } 4513 for (int i = 0; i < sc->num_tx_queues; i++, tx_que++) { 4514 struct tx_ring *txr = &tx_que->txr; 4515 4516 /* ... and the TX */ 4517 ixgbe_set_ivar(sc, txr->me, tx_que->msix, 1); 4518 } 4519 /* For the Link interrupt */ 4520 ixgbe_set_ivar(sc, 1, sc->vector, -1); 4521 } /* ixgbe_configure_ivars */ 4522 4523 /************************************************************************ 4524 * ixgbe_config_gpie 4525 ************************************************************************/ 4526 static void 4527 ixgbe_config_gpie(struct ixgbe_softc *sc) 4528 { 4529 struct ixgbe_hw *hw = &sc->hw; 4530 u32 gpie; 4531 4532 gpie = IXGBE_READ_REG(hw, IXGBE_GPIE); 4533 4534 if (sc->intr_type == IFLIB_INTR_MSIX) { 4535 /* Enable Enhanced MSI-X mode */ 4536 gpie |= IXGBE_GPIE_MSIX_MODE | 4537 IXGBE_GPIE_EIAME | 4538 IXGBE_GPIE_PBA_SUPPORT | 4539 IXGBE_GPIE_OCD; 4540 } 4541 4542 /* Fan Failure Interrupt */ 4543 if (sc->feat_en & IXGBE_FEATURE_FAN_FAIL) 4544 gpie |= IXGBE_SDP1_GPIEN; 4545 4546 /* Thermal Sensor Interrupt */ 4547 if (sc->feat_en & IXGBE_FEATURE_TEMP_SENSOR) 4548 gpie |= IXGBE_SDP0_GPIEN_X540; 4549 4550 /* Link detection */ 4551 switch (hw->mac.type) { 4552 case ixgbe_mac_82599EB: 4553 gpie |= IXGBE_SDP1_GPIEN | IXGBE_SDP2_GPIEN; 4554 break; 4555 case ixgbe_mac_X550EM_x: 4556 case ixgbe_mac_X550EM_a: 4557 gpie |= IXGBE_SDP0_GPIEN_X540; 4558 break; 4559 default: 4560 break; 4561 } 4562 4563 IXGBE_WRITE_REG(hw, IXGBE_GPIE, gpie); 4564 4565 } /* ixgbe_config_gpie */ 4566 4567 /************************************************************************ 4568 * ixgbe_config_delay_values 4569 * 4570 * Requires sc->max_frame_size to be set. 4571 ************************************************************************/ 4572 static void 4573 ixgbe_config_delay_values(struct ixgbe_softc *sc) 4574 { 4575 struct ixgbe_hw *hw = &sc->hw; 4576 u32 rxpb, frame, size, tmp; 4577 4578 frame = sc->max_frame_size; 4579 4580 /* Calculate High Water */ 4581 switch (hw->mac.type) { 4582 case ixgbe_mac_X540: 4583 case ixgbe_mac_X550: 4584 case ixgbe_mac_X550EM_x: 4585 case ixgbe_mac_X550EM_a: 4586 tmp = IXGBE_DV_X540(frame, frame); 4587 break; 4588 default: 4589 tmp = IXGBE_DV(frame, frame); 4590 break; 4591 } 4592 size = IXGBE_BT2KB(tmp); 4593 rxpb = IXGBE_READ_REG(hw, IXGBE_RXPBSIZE(0)) >> 10; 4594 hw->fc.high_water[0] = rxpb - size; 4595 4596 /* Now calculate Low Water */ 4597 switch (hw->mac.type) { 4598 case ixgbe_mac_X540: 4599 case ixgbe_mac_X550: 4600 case ixgbe_mac_X550EM_x: 4601 case ixgbe_mac_X550EM_a: 4602 tmp = IXGBE_LOW_DV_X540(frame); 4603 break; 4604 default: 4605 tmp = IXGBE_LOW_DV(frame); 4606 break; 4607 } 4608 hw->fc.low_water[0] = IXGBE_BT2KB(tmp); 4609 4610 hw->fc.pause_time = IXGBE_FC_PAUSE; 4611 hw->fc.send_xon = true; 4612 } /* ixgbe_config_delay_values */ 4613 4614 /************************************************************************ 4615 * ixgbe_set_multi - Multicast Update 4616 * 4617 * Called whenever multicast address list is updated. 4618 ************************************************************************/ 4619 static u_int 4620 ixgbe_mc_filter_apply(void *arg, struct sockaddr_dl *sdl, u_int idx) 4621 { 4622 struct ixgbe_softc *sc = arg; 4623 struct ixgbe_mc_addr *mta = sc->mta; 4624 4625 if (idx == MAX_NUM_MULTICAST_ADDRESSES) 4626 return (0); 4627 bcopy(LLADDR(sdl), mta[idx].addr, IXGBE_ETH_LENGTH_OF_ADDRESS); 4628 mta[idx].vmdq = sc->pool; 4629 4630 return (1); 4631 } /* ixgbe_mc_filter_apply */ 4632 4633 #ifdef PCI_IOV 4634 /* 4635 * The MTA is shared by the PF and every VF. Rebuild it from all owners 4636 * because an individual bit cannot be cleared safely when hashes collide. 4637 */ 4638 u_int 4639 ixgbe_iov_rebuild_mta(struct ixgbe_softc *sc) 4640 { 4641 struct ixgbe_hw *hw; 4642 struct ixgbe_mc_addr *mta; 4643 struct ixgbe_vf *vf; 4644 u32 old_mta[IXGBE_MAX_MTA]; 4645 u32 hash; 4646 u_int i, mcnt; 4647 int vf_index; 4648 4649 hw = &sc->hw; 4650 mta = sc->mta; 4651 bzero(mta, sizeof(*mta) * MAX_NUM_MULTICAST_ADDRESSES); 4652 mcnt = if_foreach_llmaddr(iflib_get_ifp(sc->ctx), 4653 ixgbe_mc_filter_apply, sc); 4654 4655 bcopy(hw->mac.mta_shadow, old_mta, sizeof(old_mta)); 4656 bzero(hw->mac.mta_shadow, sizeof(hw->mac.mta_shadow)); 4657 hw->addr_ctrl.num_mc_addrs = mcnt; 4658 hw->addr_ctrl.mta_in_use = 0; 4659 4660 for (i = 0; i < mcnt; i++) 4661 ixgbe_set_mta(hw, mta[i].addr); 4662 4663 for (vf_index = 0; vf_index < sc->num_vfs; vf_index++) { 4664 vf = &sc->vfs[vf_index]; 4665 if (!(vf->flags & IXGBE_VF_ACTIVE)) 4666 continue; 4667 4668 for (i = 0; i < vf->num_mc_hashes; i++) { 4669 hash = vf->mc_hash[i] & 0xfff; 4670 hw->mac.mta_shadow[(hash >> 5) & 4671 (hw->mac.mcft_size - 1)] |= 4672 1U << (hash & 0x1f); 4673 hw->addr_ctrl.mta_in_use++; 4674 } 4675 } 4676 4677 for (i = 0; i < hw->mac.mcft_size; i++) { 4678 if (sc->iov_mta_valid && 4679 old_mta[i] == hw->mac.mta_shadow[i]) 4680 continue; 4681 IXGBE_WRITE_REG_ARRAY(hw, IXGBE_MTA(0), i, 4682 hw->mac.mta_shadow[i]); 4683 } 4684 sc->iov_mta_valid = true; 4685 4686 IXGBE_WRITE_REG(hw, IXGBE_MCSTCTRL, 4687 (hw->addr_ctrl.mta_in_use != 0 ? IXGBE_MCSTCTRL_MFE : 0) | 4688 hw->mac.mc_filter_type); 4689 4690 return (mcnt); 4691 } 4692 #endif 4693 4694 static void 4695 ixgbe_if_multi_set(if_ctx_t ctx) 4696 { 4697 struct ixgbe_softc *sc = iflib_get_softc(ctx); 4698 struct ixgbe_mc_addr *mta; 4699 if_t ifp = iflib_get_ifp(ctx); 4700 u8 *update_ptr; 4701 u32 fctrl; 4702 u_int mcnt; 4703 4704 IOCTL_DEBUGOUT("ixgbe_if_multi_set: begin"); 4705 4706 #ifdef PCI_IOV 4707 if (sc->feat_en & IXGBE_FEATURE_SRIOV) { 4708 mcnt = ixgbe_iov_rebuild_mta(sc); 4709 } else 4710 #endif 4711 { 4712 mta = sc->mta; 4713 bzero(mta, sizeof(*mta) * MAX_NUM_MULTICAST_ADDRESSES); 4714 4715 mcnt = if_foreach_llmaddr(iflib_get_ifp(ctx), 4716 ixgbe_mc_filter_apply, sc); 4717 4718 if (mcnt < MAX_NUM_MULTICAST_ADDRESSES) { 4719 update_ptr = (u8 *)mta; 4720 ixgbe_update_mc_addr_list(&sc->hw, update_ptr, mcnt, 4721 ixgbe_mc_array_itr, true); 4722 } 4723 } 4724 4725 fctrl = IXGBE_READ_REG(&sc->hw, IXGBE_FCTRL); 4726 4727 if (if_getflags(ifp) & IFF_PROMISC) 4728 fctrl |= (IXGBE_FCTRL_UPE | IXGBE_FCTRL_MPE); 4729 else if (mcnt >= MAX_NUM_MULTICAST_ADDRESSES || 4730 if_getflags(ifp) & IFF_ALLMULTI) { 4731 fctrl |= IXGBE_FCTRL_MPE; 4732 fctrl &= ~IXGBE_FCTRL_UPE; 4733 } else 4734 fctrl &= ~(IXGBE_FCTRL_UPE | IXGBE_FCTRL_MPE); 4735 4736 IXGBE_WRITE_REG(&sc->hw, IXGBE_FCTRL, fctrl); 4737 } /* ixgbe_if_multi_set */ 4738 4739 /************************************************************************ 4740 * ixgbe_mc_array_itr 4741 * 4742 * An iterator function needed by the multicast shared code. 4743 * It feeds the shared code routine the addresses in the 4744 * array of ixgbe_set_multi() one by one. 4745 ************************************************************************/ 4746 static u8 * 4747 ixgbe_mc_array_itr(struct ixgbe_hw *hw, u8 **update_ptr, u32 *vmdq) 4748 { 4749 struct ixgbe_mc_addr *mta; 4750 4751 mta = (struct ixgbe_mc_addr *)*update_ptr; 4752 *vmdq = mta->vmdq; 4753 4754 *update_ptr = (u8*)(mta + 1); 4755 4756 return (mta->addr); 4757 } /* ixgbe_mc_array_itr */ 4758 4759 /************************************************************************ 4760 * ixgbe_local_timer - Timer routine 4761 * 4762 * Checks for link status, updates statistics, 4763 * and runs the watchdog check. 4764 ************************************************************************/ 4765 static void 4766 ixgbe_if_timer(if_ctx_t ctx, uint16_t qid) 4767 { 4768 struct ixgbe_softc *sc = iflib_get_softc(ctx); 4769 4770 if (qid != 0) 4771 return; 4772 4773 /* Check for pluggable optics */ 4774 if (sc->sfp_probe) 4775 if (!ixgbe_sfp_probe(ctx)) 4776 return; /* Nothing to do */ 4777 4778 ixgbe_check_link(&sc->hw, &sc->link_speed, &sc->link_up, 0); 4779 4780 /* Fire off the adminq task */ 4781 iflib_admin_intr_deferred(ctx); 4782 4783 } /* ixgbe_if_timer */ 4784 4785 /************************************************************************ 4786 * ixgbe_fw_mode_timer - FW mode timer routine 4787 ************************************************************************/ 4788 static void 4789 ixgbe_fw_mode_timer(void *arg) 4790 { 4791 struct ixgbe_softc *sc = arg; 4792 struct ixgbe_hw *hw = &sc->hw; 4793 4794 if (ixgbe_fw_recovery_mode(hw)) { 4795 if (atomic_cmpset_acq_int(&sc->recovery_mode, 0, 1)) { 4796 /* Firmware error detected, entering recovery mode */ 4797 device_printf(sc->dev, 4798 "Firmware recovery mode detected. Limiting" 4799 " functionality. Refer to the Intel(R) Ethernet" 4800 " Adapters and Devices User Guide for details on" 4801 " firmware recovery mode.\n"); 4802 4803 /* Stop and publish the failure from the iflib taskqueue. */ 4804 iflib_request_reset_if_up(sc->ctx); 4805 iflib_admin_intr_deferred(sc->ctx); 4806 } 4807 } else if (atomic_cmpset_acq_int(&sc->recovery_mode, 1, 0)) { 4808 /* Reinitialize an interface which was up when recovery began. */ 4809 iflib_request_reset_if_up(sc->ctx); 4810 iflib_admin_intr_deferred(sc->ctx); 4811 } 4812 4813 4814 callout_reset(&sc->fw_mode_timer, hz, 4815 ixgbe_fw_mode_timer, sc); 4816 } /* ixgbe_fw_mode_timer */ 4817 4818 /************************************************************************ 4819 * ixgbe_sfp_probe 4820 * 4821 * Determine if a port had optics inserted. 4822 ************************************************************************/ 4823 static bool 4824 ixgbe_sfp_probe(if_ctx_t ctx) 4825 { 4826 struct ixgbe_softc *sc = iflib_get_softc(ctx); 4827 struct ixgbe_hw *hw = &sc->hw; 4828 device_t dev = iflib_get_dev(ctx); 4829 bool result = false; 4830 4831 if ((hw->phy.type == ixgbe_phy_nl) && 4832 (hw->phy.sfp_type == ixgbe_sfp_type_not_present)) { 4833 s32 ret = hw->phy.ops.identify_sfp(hw); 4834 if (ret) 4835 goto out; 4836 ret = hw->phy.ops.reset(hw); 4837 sc->sfp_probe = false; 4838 if (ret == IXGBE_ERR_SFP_NOT_SUPPORTED) { 4839 device_printf(dev, 4840 "Unsupported SFP+ module detected!"); 4841 device_printf(dev, 4842 "Reload driver with supported module.\n"); 4843 goto out; 4844 } else 4845 device_printf(dev, "SFP+ module detected!\n"); 4846 /* We now have supported optics */ 4847 result = true; 4848 } 4849 out: 4850 4851 return (result); 4852 } /* ixgbe_sfp_probe */ 4853 4854 /************************************************************************ 4855 * ixgbe_handle_mod - Tasklet for SFP module interrupts 4856 ************************************************************************/ 4857 static bool 4858 ixgbe_handle_mod(void *context) 4859 { 4860 if_ctx_t ctx = context; 4861 struct ixgbe_softc *sc = iflib_get_softc(ctx); 4862 struct ixgbe_hw *hw = &sc->hw; 4863 device_t dev = iflib_get_dev(ctx); 4864 u32 err, cage_full = 0; 4865 4866 if (sc->hw.need_crosstalk_fix) { 4867 switch (hw->mac.type) { 4868 case ixgbe_mac_82599EB: 4869 cage_full = IXGBE_READ_REG(hw, IXGBE_ESDP) & 4870 IXGBE_ESDP_SDP2; 4871 break; 4872 case ixgbe_mac_X550EM_x: 4873 case ixgbe_mac_X550EM_a: 4874 cage_full = IXGBE_READ_REG(hw, IXGBE_ESDP) & 4875 IXGBE_ESDP_SDP0; 4876 break; 4877 default: 4878 break; 4879 } 4880 4881 if (!cage_full) 4882 goto handle_mod_out; 4883 } 4884 4885 err = hw->phy.ops.identify_sfp(hw); 4886 if (err == IXGBE_ERR_SFP_NOT_SUPPORTED) { 4887 device_printf(dev, 4888 "Unsupported SFP+ module type was detected.\n"); 4889 goto handle_mod_out; 4890 } 4891 4892 if (hw->mac.type == ixgbe_mac_82598EB) 4893 err = hw->phy.ops.reset(hw); 4894 else 4895 err = hw->mac.ops.setup_sfp(hw); 4896 4897 if (err == IXGBE_ERR_SFP_NOT_SUPPORTED) { 4898 device_printf(dev, 4899 "Setup failure - unsupported SFP+ module type.\n"); 4900 goto handle_mod_out; 4901 } 4902 return (true); 4903 4904 handle_mod_out: 4905 return (false); 4906 } /* ixgbe_handle_mod */ 4907 4908 4909 /************************************************************************ 4910 * ixgbe_handle_msf - Tasklet for MSF (multispeed fiber) interrupts 4911 ************************************************************************/ 4912 static void 4913 ixgbe_handle_msf(void *context) 4914 { 4915 if_ctx_t ctx = context; 4916 struct ixgbe_softc *sc = iflib_get_softc(ctx); 4917 struct ixgbe_hw *hw = &sc->hw; 4918 u32 autoneg; 4919 bool negotiate; 4920 4921 /* get_supported_phy_layer will call hw->phy.ops.identify_sfp() */ 4922 sc->phy_layer = ixgbe_get_supported_physical_layer(hw); 4923 4924 autoneg = hw->phy.autoneg_advertised; 4925 if ((!autoneg) && (hw->mac.ops.get_link_capabilities)) 4926 hw->mac.ops.get_link_capabilities(hw, &autoneg, &negotiate); 4927 if (hw->mac.ops.setup_link) 4928 hw->mac.ops.setup_link(hw, autoneg, true); 4929 4930 /* Adjust media types shown in ifconfig */ 4931 ifmedia_removeall(sc->media); 4932 ixgbe_add_media_types(sc->ctx); 4933 ifmedia_set(sc->media, IFM_ETHER | IFM_AUTO); 4934 } /* ixgbe_handle_msf */ 4935 4936 /************************************************************************ 4937 * ixgbe_handle_phy - Tasklet for external PHY interrupts 4938 ************************************************************************/ 4939 static void 4940 ixgbe_handle_phy(void *context) 4941 { 4942 if_ctx_t ctx = context; 4943 struct ixgbe_softc *sc = iflib_get_softc(ctx); 4944 struct ixgbe_hw *hw = &sc->hw; 4945 int error; 4946 4947 error = hw->phy.ops.handle_lasi(hw); 4948 if (error == IXGBE_ERR_OVERTEMP) 4949 device_printf(sc->dev, 4950 "CRITICAL: EXTERNAL PHY OVER TEMP!!" 4951 " PHY will downshift to lower power state!\n"); 4952 else if (error) 4953 device_printf(sc->dev, 4954 "Error handling LASI interrupt: %d\n", error); 4955 } /* ixgbe_handle_phy */ 4956 4957 /************************************************************************ 4958 * ixgbe_enable_lse - enable link status events 4959 * 4960 * Sets mask and enables link status events 4961 ************************************************************************/ 4962 s32 ixgbe_enable_lse(struct ixgbe_softc *sc) 4963 { 4964 s32 error; 4965 4966 u16 mask = ~((u16)(IXGBE_ACI_LINK_EVENT_UPDOWN | 4967 IXGBE_ACI_LINK_EVENT_MEDIA_NA | 4968 IXGBE_ACI_LINK_EVENT_MODULE_QUAL_FAIL | 4969 IXGBE_ACI_LINK_EVENT_PHY_FW_LOAD_FAIL)); 4970 4971 error = ixgbe_configure_lse(&sc->hw, TRUE, mask); 4972 if (error) 4973 return (error); 4974 4975 sc->lse_mask = mask; 4976 return (IXGBE_SUCCESS); 4977 } /* ixgbe_enable_lse */ 4978 4979 /************************************************************************ 4980 * ixgbe_disable_lse - disable link status events 4981 ************************************************************************/ 4982 s32 ixgbe_disable_lse(struct ixgbe_softc *sc) 4983 { 4984 s32 error; 4985 4986 error = ixgbe_configure_lse(&sc->hw, false, sc->lse_mask); 4987 if (error) 4988 return (error); 4989 4990 sc->lse_mask = 0; 4991 return (IXGBE_SUCCESS); 4992 } /* ixgbe_disable_lse */ 4993 4994 /************************************************************************ 4995 * ixgbe_handle_fw_event - Tasklet for MSI-X Link Status Event interrupts 4996 ************************************************************************/ 4997 static u32 4998 ixgbe_handle_fw_event(void *context) 4999 { 5000 if_ctx_t ctx = context; 5001 struct ixgbe_softc *sc = iflib_get_softc(ctx); 5002 struct ixgbe_hw *hw = &sc->hw; 5003 struct ixgbe_aci_event event; 5004 bool pending = false; 5005 s32 error; 5006 u32 requests = 0; 5007 5008 event.buf_len = IXGBE_ACI_MAX_BUFFER_SIZE; 5009 event.msg_buf = malloc(event.buf_len, M_IXGBE, M_ZERO | M_NOWAIT); 5010 if (!event.msg_buf) { 5011 device_printf(sc->dev, "Can not allocate buffer for " 5012 "event message\n"); 5013 return (0); 5014 } 5015 5016 do { 5017 error = ixgbe_aci_get_event(hw, &event, &pending); 5018 if (error) { 5019 device_printf(sc->dev, "Error getting event from " 5020 "FW:%d\n", error); 5021 break; 5022 } 5023 5024 switch (le16toh(event.desc.opcode)) { 5025 case ixgbe_aci_opc_get_link_status: 5026 requests |= IXGBE_REQUEST_TASK_LSC; 5027 break; 5028 5029 case ixgbe_aci_opc_fw_logs_event: 5030 ixgbe_fwlog_event_dump(&sc->hw, &event.desc, event.msg_buf); 5031 break; 5032 5033 case ixgbe_aci_opc_temp_tca_event: 5034 if (!sc->overtemp_shutdown_pending) { 5035 sc->overtemp_shutdown_pending = true; 5036 requests |= IXGBE_REQUEST_TASK_RESET; 5037 device_printf(sc->dev, 5038 "CRITICAL: OVER TEMP!! PHY IS SHUT DOWN!!\n"); 5039 device_printf(sc->dev, 5040 "System shutdown required!\n"); 5041 } 5042 break; 5043 5044 default: 5045 device_printf(sc->dev, 5046 "Unknown FW event captured, opcode=0x%04X\n", 5047 le16toh(event.desc.opcode)); 5048 break; 5049 } 5050 } while (pending); 5051 5052 free(event.msg_buf, M_IXGBE); 5053 return (requests); 5054 } /* ixgbe_handle_fw_event */ 5055 5056 /************************************************************************ 5057 * ixgbe_if_stop - Stop the hardware 5058 * 5059 * Disables all traffic on the adapter by issuing a 5060 * global reset on the MAC and deallocates TX/RX buffers. 5061 ************************************************************************/ 5062 static void 5063 ixgbe_if_stop(if_ctx_t ctx) 5064 { 5065 struct ixgbe_softc *sc = iflib_get_softc(ctx); 5066 struct ixgbe_hw *hw = &sc->hw; 5067 5068 INIT_DEBUGOUT("ixgbe_if_stop: begin\n"); 5069 5070 ixgbe_led_restore(sc); 5071 if (sc->feat_en & IXGBE_FEATURE_SRIOV) { 5072 ixgbe_disable_mdd(hw); 5073 ixgbe_quiesce_vfs(sc); 5074 } 5075 ixgbe_reset_hw(hw); 5076 atomic_store_rel_int(&sc->ecc_reset_pending, 0); 5077 hw->adapter_stopped = false; 5078 ixgbe_stop_adapter(hw); 5079 /* Turn off the laser - noop with no optics */ 5080 ixgbe_disable_tx_laser(hw); 5081 5082 /* Update the stack */ 5083 sc->link_up = false; 5084 if (sc->link_active) { 5085 if (bootverbose) 5086 device_printf(sc->dev, "Link is Down\n"); 5087 iflib_link_state_change(ctx, LINK_STATE_DOWN, 0); 5088 sc->link_active = false; 5089 } 5090 5091 /* reprogram the RAR[0] in case user changed it. */ 5092 ixgbe_set_rar(&sc->hw, 0, sc->hw.mac.addr, 0, IXGBE_RAH_AV); 5093 5094 return; 5095 } /* ixgbe_if_stop */ 5096 5097 /* 5098 * Identify the physical port while retaining the NVM-selected LED mode. 5099 * E610 exposes identification through firmware rather than LEDCTL. 5100 */ 5101 static void 5102 ixgbe_if_led_func(if_ctx_t ctx, int onoff) 5103 { 5104 struct ixgbe_softc *sc; 5105 struct ixgbe_hw *hw; 5106 5107 sc = iflib_get_softc(ctx); 5108 hw = &sc->hw; 5109 if (!onoff) { 5110 ixgbe_led_restore(sc); 5111 return; 5112 } 5113 if (sc->led_active) 5114 return; 5115 5116 if (hw->mac.type == ixgbe_mac_E610) { 5117 if (ixgbe_aci_set_port_id_led(hw, false) == IXGBE_SUCCESS) 5118 sc->led_active = true; 5119 return; 5120 } 5121 5122 sc->ledctl_default = IXGBE_READ_REG(hw, IXGBE_LEDCTL); 5123 if (ixgbe_led_on(hw, hw->mac.led_link_act) == IXGBE_SUCCESS) 5124 sc->led_active = true; 5125 } 5126 5127 static void 5128 ixgbe_led_restore(struct ixgbe_softc *sc) 5129 { 5130 struct ixgbe_hw *hw; 5131 5132 if (!sc->led_active) 5133 return; 5134 5135 hw = &sc->hw; 5136 if (hw->mac.type == ixgbe_mac_E610) { 5137 (void)ixgbe_aci_set_port_id_led(hw, true); 5138 } else { 5139 /* Clear any PHY manual override before restoring LEDCTL. */ 5140 (void)ixgbe_led_off(hw, hw->mac.led_link_act); 5141 IXGBE_WRITE_REG(hw, IXGBE_LEDCTL, sc->ledctl_default); 5142 IXGBE_WRITE_FLUSH(hw); 5143 } 5144 sc->led_active = false; 5145 } 5146 5147 /************************************************************************ 5148 * ixgbe_link_speed_to_str - Convert link speed to string 5149 * 5150 * Helper function to convert link speed constants to human-readable 5151 * string representations in conventional Gbps or Mbps. 5152 ************************************************************************/ 5153 static const char * 5154 ixgbe_link_speed_to_str(u32 link_speed) 5155 { 5156 switch (link_speed) { 5157 case IXGBE_LINK_SPEED_10GB_FULL: 5158 return "10 Gbps"; 5159 case IXGBE_LINK_SPEED_5GB_FULL: 5160 return "5 Gbps"; 5161 case IXGBE_LINK_SPEED_2_5GB_FULL: 5162 return "2.5 Gbps"; 5163 case IXGBE_LINK_SPEED_1GB_FULL: 5164 return "1 Gbps"; 5165 case IXGBE_LINK_SPEED_100_FULL: 5166 return "100 Mbps"; 5167 case IXGBE_LINK_SPEED_10_FULL: 5168 return "10 Mbps"; 5169 default: 5170 return "Unknown"; 5171 } 5172 } /* ixgbe_link_speed_to_str */ 5173 5174 /************************************************************************ 5175 * ixgbe_update_link_status - Update OS on link state 5176 * 5177 * Process deferred administrative requests and update the OS link state. 5178 ************************************************************************/ 5179 static void 5180 ixgbe_if_update_admin_status(if_ctx_t ctx) 5181 { 5182 struct ixgbe_softc *sc = iflib_get_softc(ctx); 5183 device_t dev = iflib_get_dev(ctx); 5184 u32 requests; 5185 u_int pass; 5186 bool check_link = false; 5187 5188 /* 5189 * The interrupt filter and other producers can run concurrently with 5190 * this task. Claim each batch atomically so a request posted while the 5191 * task is running remains pending for this or the next invocation. 5192 * 5193 * MOD and firmware events can produce dependent requests. Fold those 5194 * into the claimed batch so link state is sampled after any link setup. 5195 */ 5196 if ((if_getdrvflags(iflib_get_ifp(ctx)) & IFF_DRV_RUNNING) != 0 && 5197 (sc->iov_mbx_cleanup_pending || ixgbe_mbx_pending(sc))) 5198 atomic_set_32(&sc->task_requests, IXGBE_REQUEST_TASK_MBX); 5199 for (pass = 0; pass < IXGBE_ADMIN_TASK_BUDGET; pass++) { 5200 requests = atomic_readandclear_32(&sc->task_requests); 5201 if (requests == 0) 5202 break; 5203 if (requests & IXGBE_REQUEST_TASK_FWEVENT) 5204 requests |= ixgbe_handle_fw_event(ctx); 5205 if (requests & IXGBE_REQUEST_TASK_MOD) { 5206 if (ixgbe_handle_mod(ctx)) 5207 requests |= IXGBE_REQUEST_TASK_MSF; 5208 else 5209 requests &= ~IXGBE_REQUEST_TASK_MSF; 5210 } 5211 if (requests & IXGBE_REQUEST_TASK_MSF) 5212 ixgbe_handle_msf(ctx); 5213 /* A reset request can re-enable VF traffic; skip it while stopped. */ 5214 if ((requests & IXGBE_REQUEST_TASK_MBX) != 0 && 5215 (if_getdrvflags(iflib_get_ifp(ctx)) & IFF_DRV_RUNNING) != 0) 5216 ixgbe_handle_mbx(ctx); 5217 if (requests & IXGBE_REQUEST_TASK_FDIR) 5218 ixgbe_reinit_fdir(ctx); 5219 if (requests & IXGBE_REQUEST_TASK_PHY) 5220 ixgbe_handle_phy(ctx); 5221 if (requests & IXGBE_REQUEST_TASK_LSC) 5222 check_link = true; 5223 if (requests & IXGBE_REQUEST_TASK_RESET) { 5224 /* Re-enter the admin task so it observes IFC_DO_RESET. */ 5225 iflib_request_reset(ctx); 5226 iflib_admin_intr_deferred(ctx); 5227 } 5228 } 5229 5230 /* Do not let a continuous producer monopolize the admin taskqueue. */ 5231 if (atomic_load_acq_32(&sc->task_requests) != 0) 5232 iflib_admin_intr_deferred(ctx); 5233 5234 if (check_link) 5235 ixgbe_check_link(&sc->hw, &sc->link_speed, &sc->link_up, 5236 false); 5237 5238 if (sc->link_up) { 5239 if (sc->link_active == false) { 5240 if (bootverbose) 5241 device_printf(dev, 5242 "Link is up %s Full Duplex\n", 5243 ixgbe_link_speed_to_str(sc->link_speed)); 5244 sc->link_active = true; 5245 5246 /* If link speed is <= 1Gbps and EEE is enabled, 5247 * log info. 5248 */ 5249 if (sc->hw.mac.type == ixgbe_mac_E610 && 5250 (sc->feat_en & IXGBE_FEATURE_EEE) && 5251 sc->link_speed <= IXGBE_LINK_SPEED_1GB_FULL) { 5252 device_printf(sc->dev, 5253 "Energy Efficient Ethernet (EEE) feature " 5254 "is not supported on link speeds equal to " 5255 "or below 1Gbps. EEE is supported on " 5256 "speeds above 1Gbps.\n"); 5257 } 5258 5259 /* Update any Flow Control changes */ 5260 ixgbe_fc_enable(&sc->hw); 5261 /* Update DMA coalescing config */ 5262 ixgbe_config_dmac(sc); 5263 iflib_link_state_change(ctx, LINK_STATE_UP, 5264 ixgbe_link_speed_to_baudrate(sc->link_speed)); 5265 5266 if (sc->feat_en & IXGBE_FEATURE_SRIOV) 5267 ixgbe_ping_all_vfs(sc); 5268 } 5269 } else { /* Link down */ 5270 if (sc->link_active == true) { 5271 if (bootverbose) 5272 device_printf(dev, "Link is Down\n"); 5273 iflib_link_state_change(ctx, LINK_STATE_DOWN, 0); 5274 sc->link_active = false; 5275 if (sc->feat_en & IXGBE_FEATURE_SRIOV) 5276 ixgbe_ping_all_vfs(sc); 5277 } 5278 } 5279 5280 ixgbe_schedule_iov_recovery(sc); 5281 5282 ixgbe_update_stats_counters(sc); 5283 } /* ixgbe_if_update_admin_status */ 5284 5285 /************************************************************************ 5286 * ixgbe_config_dmac - Configure DMA Coalescing 5287 ************************************************************************/ 5288 static void 5289 ixgbe_config_dmac(struct ixgbe_softc *sc) 5290 { 5291 struct ixgbe_hw *hw = &sc->hw; 5292 struct ixgbe_dmac_config *dcfg = &hw->mac.dmac_config; 5293 5294 if (hw->mac.type < ixgbe_mac_X550 || !hw->mac.ops.dmac_config) 5295 return; 5296 5297 if (dcfg->watchdog_timer ^ sc->dmac || 5298 dcfg->link_speed ^ sc->link_speed) { 5299 dcfg->watchdog_timer = sc->dmac; 5300 dcfg->fcoe_en = false; 5301 dcfg->link_speed = sc->link_speed; 5302 dcfg->num_tcs = 1; 5303 5304 INIT_DEBUGOUT2("dmac settings: watchdog %d, link speed %d\n", 5305 dcfg->watchdog_timer, dcfg->link_speed); 5306 5307 hw->mac.ops.dmac_config(hw); 5308 } 5309 } /* ixgbe_config_dmac */ 5310 5311 /************************************************************************ 5312 * ixgbe_if_enable_intr 5313 ************************************************************************/ 5314 void 5315 ixgbe_if_enable_intr(if_ctx_t ctx) 5316 { 5317 struct ixgbe_softc *sc = iflib_get_softc(ctx); 5318 struct ixgbe_hw *hw = &sc->hw; 5319 struct ix_rx_queue *que = sc->rx_queues; 5320 u32 mask, fwsm; 5321 5322 mask = (IXGBE_EIMS_ENABLE_MASK & ~IXGBE_EIMS_RTX_QUEUE); 5323 5324 switch (sc->hw.mac.type) { 5325 case ixgbe_mac_82599EB: 5326 mask |= IXGBE_EIMS_ECC; 5327 /* Temperature sensor on some scs */ 5328 mask |= IXGBE_EIMS_GPI_SDP0; 5329 /* SFP+ (RX_LOS_N & MOD_ABS_N) */ 5330 mask |= IXGBE_EIMS_GPI_SDP1; 5331 mask |= IXGBE_EIMS_GPI_SDP2; 5332 break; 5333 case ixgbe_mac_X540: 5334 /* Detect if Thermal Sensor is enabled */ 5335 fwsm = IXGBE_READ_REG(hw, IXGBE_FWSM); 5336 if (fwsm & IXGBE_FWSM_TS_ENABLED) 5337 mask |= IXGBE_EIMS_TS; 5338 mask |= IXGBE_EIMS_ECC; 5339 break; 5340 case ixgbe_mac_X550: 5341 /* MAC thermal sensor is automatically enabled */ 5342 mask |= IXGBE_EIMS_TS; 5343 mask |= IXGBE_EIMS_ECC; 5344 break; 5345 case ixgbe_mac_X550EM_x: 5346 case ixgbe_mac_X550EM_a: 5347 /* Some devices use SDP0 for important information */ 5348 if (hw->device_id == IXGBE_DEV_ID_X550EM_X_SFP || 5349 hw->device_id == IXGBE_DEV_ID_X550EM_A_SFP || 5350 hw->device_id == IXGBE_DEV_ID_X550EM_A_SFP_N || 5351 hw->device_id == IXGBE_DEV_ID_X550EM_X_10G_T) 5352 mask |= IXGBE_EIMS_GPI_SDP0_BY_MAC(hw); 5353 if (hw->phy.type == ixgbe_phy_x550em_ext_t) 5354 mask |= IXGBE_EICR_GPI_SDP0_X540; 5355 mask |= IXGBE_EIMS_ECC; 5356 break; 5357 case ixgbe_mac_E610: 5358 mask |= IXGBE_EIMS_FW_EVENT; 5359 break; 5360 default: 5361 break; 5362 } 5363 5364 /* Enable Fan Failure detection */ 5365 if (sc->feat_en & IXGBE_FEATURE_FAN_FAIL) 5366 mask |= IXGBE_EIMS_GPI_SDP1; 5367 /* Enable SR-IOV */ 5368 if (sc->feat_en & IXGBE_FEATURE_SRIOV) 5369 mask |= IXGBE_EIMS_MAILBOX; 5370 /* Enable Flow Director */ 5371 if (sc->feat_en & IXGBE_FEATURE_FDIR) 5372 mask |= IXGBE_EIMS_FLOW_DIR; 5373 if (atomic_load_acq_int(&sc->ecc_reset_pending)) 5374 mask &= ~IXGBE_EIMS_ECC; 5375 5376 IXGBE_WRITE_REG(hw, IXGBE_EIMS, mask); 5377 5378 /* With MSI-X we use auto clear */ 5379 if (sc->intr_type == IFLIB_INTR_MSIX) { 5380 mask = IXGBE_EIMS_ENABLE_MASK; 5381 /* Don't autoclear Link */ 5382 mask &= ~IXGBE_EIMS_OTHER; 5383 mask &= ~IXGBE_EIMS_LSC; 5384 mask &= ~IXGBE_EIMS_FW_EVENT; 5385 if (sc->feat_cap & IXGBE_FEATURE_SRIOV) 5386 mask &= ~IXGBE_EIMS_MAILBOX; 5387 IXGBE_WRITE_REG(hw, IXGBE_EIAC, mask); 5388 } 5389 5390 /* 5391 * Now enable all queues, this is done separately to 5392 * allow for handling the extended (beyond 32) MSI-X 5393 * vectors that can be used by 82599 5394 */ 5395 for (int i = 0; i < sc->num_rx_queues; i++, que++) 5396 ixgbe_enable_queue(sc, que->msix); 5397 5398 IXGBE_WRITE_FLUSH(hw); 5399 5400 } /* ixgbe_if_enable_intr */ 5401 5402 /************************************************************************ 5403 * ixgbe_if_disable_intr 5404 ************************************************************************/ 5405 static void 5406 ixgbe_if_disable_intr(if_ctx_t ctx) 5407 { 5408 struct ixgbe_softc *sc = iflib_get_softc(ctx); 5409 5410 if (sc->intr_type == IFLIB_INTR_MSIX) 5411 IXGBE_WRITE_REG(&sc->hw, IXGBE_EIAC, 0); 5412 if (sc->hw.mac.type == ixgbe_mac_82598EB) { 5413 IXGBE_WRITE_REG(&sc->hw, IXGBE_EIMC, ~0); 5414 } else { 5415 IXGBE_WRITE_REG(&sc->hw, IXGBE_EIMC, 0xFFFF0000); 5416 IXGBE_WRITE_REG(&sc->hw, IXGBE_EIMC_EX(0), ~0); 5417 IXGBE_WRITE_REG(&sc->hw, IXGBE_EIMC_EX(1), ~0); 5418 } 5419 IXGBE_WRITE_FLUSH(&sc->hw); 5420 5421 } /* ixgbe_if_disable_intr */ 5422 5423 /************************************************************************ 5424 * ixgbe_link_intr_enable 5425 ************************************************************************/ 5426 static void 5427 ixgbe_link_intr_enable(if_ctx_t ctx) 5428 { 5429 struct ixgbe_hw *hw = 5430 &((struct ixgbe_softc *)iflib_get_softc(ctx))->hw; 5431 5432 /* Re-enable other interrupts */ 5433 IXGBE_WRITE_REG(hw, IXGBE_EIMS, IXGBE_EIMS_OTHER | IXGBE_EIMS_LSC); 5434 } /* ixgbe_link_intr_enable */ 5435 5436 /************************************************************************ 5437 * ixgbe_if_rx_queue_intr_enable 5438 ************************************************************************/ 5439 static int 5440 ixgbe_if_rx_queue_intr_enable(if_ctx_t ctx, uint16_t rxqid) 5441 { 5442 struct ixgbe_softc *sc = iflib_get_softc(ctx); 5443 struct ix_rx_queue *que = &sc->rx_queues[rxqid]; 5444 5445 ixgbe_enable_queue(sc, que->msix); 5446 5447 return (0); 5448 } /* ixgbe_if_rx_queue_intr_enable */ 5449 5450 /************************************************************************ 5451 * ixgbe_enable_queue 5452 ************************************************************************/ 5453 static void 5454 ixgbe_enable_queue(struct ixgbe_softc *sc, u32 vector) 5455 { 5456 struct ixgbe_hw *hw = &sc->hw; 5457 u64 queue = 1ULL << vector; 5458 u32 mask; 5459 5460 if (hw->mac.type == ixgbe_mac_82598EB) { 5461 mask = (IXGBE_EIMS_RTX_QUEUE & queue); 5462 IXGBE_WRITE_REG(hw, IXGBE_EIMS, mask); 5463 } else { 5464 mask = (queue & 0xFFFFFFFF); 5465 if (mask) 5466 IXGBE_WRITE_REG(hw, IXGBE_EIMS_EX(0), mask); 5467 mask = (queue >> 32); 5468 if (mask) 5469 IXGBE_WRITE_REG(hw, IXGBE_EIMS_EX(1), mask); 5470 } 5471 } /* ixgbe_enable_queue */ 5472 5473 /************************************************************************ 5474 * ixgbe_disable_queue 5475 ************************************************************************/ 5476 static void 5477 ixgbe_disable_queue(struct ixgbe_softc *sc, u32 vector) 5478 { 5479 struct ixgbe_hw *hw = &sc->hw; 5480 u64 queue = 1ULL << vector; 5481 u32 mask; 5482 5483 if (hw->mac.type == ixgbe_mac_82598EB) { 5484 mask = (IXGBE_EIMS_RTX_QUEUE & queue); 5485 IXGBE_WRITE_REG(hw, IXGBE_EIMC, mask); 5486 } else { 5487 mask = (queue & 0xFFFFFFFF); 5488 if (mask) 5489 IXGBE_WRITE_REG(hw, IXGBE_EIMC_EX(0), mask); 5490 mask = (queue >> 32); 5491 if (mask) 5492 IXGBE_WRITE_REG(hw, IXGBE_EIMC_EX(1), mask); 5493 } 5494 } /* ixgbe_disable_queue */ 5495 5496 /************************************************************************ 5497 * ixgbe_intr - Legacy Interrupt Service Routine 5498 ************************************************************************/ 5499 int 5500 ixgbe_intr(void *arg) 5501 { 5502 struct ixgbe_softc *sc = arg; 5503 struct ix_rx_queue *que = sc->rx_queues; 5504 struct ixgbe_hw *hw = &sc->hw; 5505 if_ctx_t ctx = sc->ctx; 5506 u32 eicr, eicr_mask, requests; 5507 5508 eicr = IXGBE_READ_REG(hw, IXGBE_EICR); 5509 requests = 0; 5510 5511 ++que->irqs; 5512 if (eicr == 0) { 5513 ixgbe_if_enable_intr(ctx); 5514 return (FILTER_HANDLED); 5515 } 5516 5517 /* Check for fan failure */ 5518 if ((sc->feat_en & IXGBE_FEATURE_FAN_FAIL) && 5519 (eicr & IXGBE_EICR_GPI_SDP1)) { 5520 device_printf(sc->dev, 5521 "\nCRITICAL: FAN FAILURE!! REPLACE IMMEDIATELY!!\n"); 5522 IXGBE_WRITE_REG(hw, IXGBE_EIMS, 5523 IXGBE_EICR_GPI_SDP1_BY_MAC(hw)); 5524 } 5525 5526 /* Link status change */ 5527 if (eicr & IXGBE_EICR_LSC) { 5528 IXGBE_WRITE_REG(hw, IXGBE_EIMC, IXGBE_EIMC_LSC); 5529 requests |= IXGBE_REQUEST_TASK_LSC; 5530 } 5531 5532 if (ixgbe_is_sfp(hw)) { 5533 /* Pluggable optics-related interrupt */ 5534 if (hw->mac.type >= ixgbe_mac_X540) 5535 eicr_mask = IXGBE_EICR_GPI_SDP0_X540; 5536 else 5537 eicr_mask = IXGBE_EICR_GPI_SDP2_BY_MAC(hw); 5538 5539 if (eicr & eicr_mask) { 5540 IXGBE_WRITE_REG(hw, IXGBE_EICR, eicr_mask); 5541 requests |= IXGBE_REQUEST_TASK_MOD; 5542 } 5543 5544 if ((hw->mac.type == ixgbe_mac_82599EB) && 5545 (eicr & IXGBE_EICR_GPI_SDP1_BY_MAC(hw))) { 5546 IXGBE_WRITE_REG(hw, IXGBE_EICR, 5547 IXGBE_EICR_GPI_SDP1_BY_MAC(hw)); 5548 requests |= IXGBE_REQUEST_TASK_MSF; 5549 } 5550 } 5551 5552 /* External PHY interrupt */ 5553 if ((hw->phy.type == ixgbe_phy_x550em_ext_t) && 5554 (eicr & IXGBE_EICR_GPI_SDP0_X540)) { 5555 requests |= IXGBE_REQUEST_TASK_PHY; 5556 } 5557 if (hw->mac.type != ixgbe_mac_82598EB && 5558 ixgbe_handle_ecc(sc, eicr)) 5559 requests |= IXGBE_REQUEST_TASK_RESET; 5560 if (requests != 0) { 5561 atomic_set_32(&sc->task_requests, requests); 5562 iflib_admin_intr_deferred(ctx); 5563 } 5564 5565 return (FILTER_SCHEDULE_THREAD); 5566 } /* ixgbe_intr */ 5567 5568 /************************************************************************ 5569 * ixgbe_free_pci_resources 5570 ************************************************************************/ 5571 static void 5572 ixgbe_free_pci_resources(if_ctx_t ctx) 5573 { 5574 struct ixgbe_softc *sc = iflib_get_softc(ctx); 5575 struct ix_rx_queue *que = sc->rx_queues; 5576 device_t dev = iflib_get_dev(ctx); 5577 5578 /* Release all MSI-X queue resources */ 5579 if (sc->intr_type == IFLIB_INTR_MSIX) 5580 iflib_irq_free(ctx, &sc->irq); 5581 5582 if (que != NULL) { 5583 for (int i = 0; i < sc->num_rx_queues; i++, que++) { 5584 iflib_irq_free(ctx, &que->que_irq); 5585 } 5586 } 5587 5588 if (sc->pci_mem != NULL) 5589 bus_release_resource(dev, SYS_RES_MEMORY, 5590 rman_get_rid(sc->pci_mem), sc->pci_mem); 5591 } /* ixgbe_free_pci_resources */ 5592 5593 /************************************************************************ 5594 * ixgbe_sysctl_flowcntl 5595 * 5596 * SYSCTL wrapper around setting Flow Control 5597 ************************************************************************/ 5598 static int 5599 ixgbe_sysctl_flowcntl(SYSCTL_HANDLER_ARGS) 5600 { 5601 struct ixgbe_softc *sc; 5602 struct sx *ctx_lock; 5603 int error, fc; 5604 5605 sc = (struct ixgbe_softc *)arg1; 5606 fc = sc->hw.fc.requested_mode; 5607 5608 error = sysctl_handle_int(oidp, &fc, 0, req); 5609 if ((error) || (req->newptr == NULL)) 5610 return (error); 5611 5612 /* Serialize the live register update with the administrative task. */ 5613 ctx_lock = iflib_ctx_lock_get(sc->ctx); 5614 sx_xlock(ctx_lock); 5615 if (fc == sc->hw.fc.requested_mode) 5616 error = 0; 5617 else 5618 error = ixgbe_set_flowcntl(sc, fc); 5619 sx_xunlock(ctx_lock); 5620 return (error); 5621 } /* ixgbe_sysctl_flowcntl */ 5622 5623 /************************************************************************ 5624 * ixgbe_set_flowcntl - Set flow control 5625 * 5626 * Flow control values: 5627 * 0 - off 5628 * 1 - rx pause 5629 * 2 - tx pause 5630 * 3 - full 5631 ************************************************************************/ 5632 static int 5633 ixgbe_set_flowcntl(struct ixgbe_softc *sc, int fc) 5634 { 5635 bool enable_drop, mdd_active; 5636 5637 switch (fc) { 5638 case ixgbe_fc_rx_pause: 5639 case ixgbe_fc_tx_pause: 5640 case ixgbe_fc_full: 5641 enable_drop = false; 5642 break; 5643 case ixgbe_fc_none: 5644 enable_drop = true; 5645 break; 5646 default: 5647 return (EINVAL); 5648 } 5649 5650 /* Updating SRRCTL on a live queue is itself an MDD violation. */ 5651 mdd_active = sc->num_rx_queues > 1 && 5652 (sc->feat_en & IXGBE_FEATURE_SRIOV) != 0 && 5653 (if_getdrvflags(iflib_get_ifp(sc->ctx)) & IFF_DRV_RUNNING) != 0; 5654 if (mdd_active) 5655 ixgbe_disable_mdd(&sc->hw); 5656 if (sc->num_rx_queues > 1) { 5657 if (enable_drop) 5658 ixgbe_enable_rx_drop(sc); 5659 else 5660 ixgbe_disable_rx_drop(sc); 5661 } 5662 if (mdd_active) { 5663 ixgbe_enable_mdd(&sc->hw); 5664 /* Service an event whose interrupt edge was lost while masked. */ 5665 if (ixgbe_mbx_pending(sc)) { 5666 atomic_set_32(&sc->task_requests, 5667 IXGBE_REQUEST_TASK_MBX); 5668 iflib_admin_intr_deferred(sc->ctx); 5669 } 5670 } 5671 5672 sc->hw.fc.requested_mode = fc; 5673 5674 /* Don't autoneg if forcing a value */ 5675 sc->hw.fc.disable_fc_autoneg = true; 5676 ixgbe_fc_enable(&sc->hw); 5677 5678 return (0); 5679 } /* ixgbe_set_flowcntl */ 5680 5681 /************************************************************************ 5682 * ixgbe_enable_rx_drop 5683 * 5684 * Enable the hardware to drop packets when the buffer is 5685 * full. This is useful with multiqueue, so that no single 5686 * queue being full stalls the entire RX engine. We only 5687 * enable this when Multiqueue is enabled AND Flow Control 5688 * is disabled. 5689 ************************************************************************/ 5690 static void 5691 ixgbe_enable_rx_drop(struct ixgbe_softc *sc) 5692 { 5693 struct ixgbe_hw *hw = &sc->hw; 5694 struct rx_ring *rxr; 5695 u32 srrctl; 5696 5697 for (int i = 0; i < sc->num_rx_queues; i++) { 5698 rxr = &sc->rx_queues[i].rxr; 5699 srrctl = IXGBE_READ_REG(hw, IXGBE_SRRCTL(rxr->me)); 5700 srrctl |= IXGBE_SRRCTL_DROP_EN; 5701 IXGBE_WRITE_REG(hw, IXGBE_SRRCTL(rxr->me), srrctl); 5702 } 5703 5704 } /* ixgbe_enable_rx_drop */ 5705 5706 /************************************************************************ 5707 * ixgbe_disable_rx_drop 5708 ************************************************************************/ 5709 static void 5710 ixgbe_disable_rx_drop(struct ixgbe_softc *sc) 5711 { 5712 struct ixgbe_hw *hw = &sc->hw; 5713 struct rx_ring *rxr; 5714 u32 srrctl; 5715 5716 for (int i = 0; i < sc->num_rx_queues; i++) { 5717 rxr = &sc->rx_queues[i].rxr; 5718 srrctl = IXGBE_READ_REG(hw, IXGBE_SRRCTL(rxr->me)); 5719 srrctl &= ~IXGBE_SRRCTL_DROP_EN; 5720 IXGBE_WRITE_REG(hw, IXGBE_SRRCTL(rxr->me), srrctl); 5721 } 5722 5723 } /* ixgbe_disable_rx_drop */ 5724 5725 /************************************************************************ 5726 * ixgbe_sysctl_advertise 5727 * 5728 * SYSCTL wrapper around setting advertised speed 5729 ************************************************************************/ 5730 static int 5731 ixgbe_sysctl_advertise(SYSCTL_HANDLER_ARGS) 5732 { 5733 struct ixgbe_softc *sc; 5734 int error, advertise; 5735 5736 sc = (struct ixgbe_softc *)arg1; 5737 if (atomic_load_acq_int(&sc->recovery_mode)) 5738 return (EPERM); 5739 5740 advertise = sc->advertise; 5741 5742 error = sysctl_handle_int(oidp, &advertise, 0, req); 5743 if ((error) || (req->newptr == NULL)) 5744 return (error); 5745 5746 return ixgbe_set_advertise(sc, advertise); 5747 } /* ixgbe_sysctl_advertise */ 5748 5749 /************************************************************************ 5750 * ixgbe_set_advertise - Control advertised link speed 5751 * 5752 * Flags: 5753 * 0x1 - advertise 100 Mb 5754 * 0x2 - advertise 1G 5755 * 0x4 - advertise 10G 5756 * 0x8 - advertise 10 Mb (yes, Mb) 5757 * 0x10 - advertise 2.5G (disabled by default) 5758 * 0x20 - advertise 5G (disabled by default) 5759 * 5760 ************************************************************************/ 5761 static int 5762 ixgbe_set_advertise(struct ixgbe_softc *sc, int advertise) 5763 { 5764 device_t dev = iflib_get_dev(sc->ctx); 5765 struct ixgbe_hw *hw; 5766 ixgbe_link_speed speed = 0; 5767 ixgbe_link_speed link_caps = 0; 5768 s32 err = IXGBE_NOT_IMPLEMENTED; 5769 bool negotiate = false; 5770 5771 /* Checks to validate new value */ 5772 if (sc->advertise == advertise) /* no change */ 5773 return (0); 5774 5775 hw = &sc->hw; 5776 5777 /* No speed changes for backplane media */ 5778 if (hw->phy.media_type == ixgbe_media_type_backplane) 5779 return (ENODEV); 5780 5781 if (!((hw->phy.media_type == ixgbe_media_type_copper) || 5782 (hw->phy.multispeed_fiber))) { 5783 device_printf(dev, 5784 "Advertised speed can only be set on copper or multispeed" 5785 " fiber media types.\n"); 5786 return (EINVAL); 5787 } 5788 5789 if (advertise < 0x1 || advertise > 0x3F) { 5790 device_printf(dev, 5791 "Invalid advertised speed; valid modes are 0x1 through" 5792 " 0x3F\n"); 5793 return (EINVAL); 5794 } 5795 5796 if (hw->mac.ops.get_link_capabilities) { 5797 err = hw->mac.ops.get_link_capabilities(hw, &link_caps, 5798 &negotiate); 5799 if (err != IXGBE_SUCCESS) { 5800 device_printf(dev, 5801 "Unable to determine supported advertise speeds" 5802 "\n"); 5803 return (ENODEV); 5804 } 5805 } 5806 5807 /* Set new value and report new advertised mode */ 5808 if (advertise & 0x1) { 5809 if (!(link_caps & IXGBE_LINK_SPEED_100_FULL)) { 5810 device_printf(dev, 5811 "Interface does not support 100Mb advertised" 5812 " speed\n"); 5813 return (EINVAL); 5814 } 5815 speed |= IXGBE_LINK_SPEED_100_FULL; 5816 } 5817 if (advertise & 0x2) { 5818 if (!(link_caps & IXGBE_LINK_SPEED_1GB_FULL)) { 5819 device_printf(dev, 5820 "Interface does not support 1Gb advertised speed" 5821 "\n"); 5822 return (EINVAL); 5823 } 5824 speed |= IXGBE_LINK_SPEED_1GB_FULL; 5825 } 5826 if (advertise & 0x4) { 5827 if (!(link_caps & IXGBE_LINK_SPEED_10GB_FULL)) { 5828 device_printf(dev, 5829 "Interface does not support 10Gb advertised speed" 5830 "\n"); 5831 return (EINVAL); 5832 } 5833 speed |= IXGBE_LINK_SPEED_10GB_FULL; 5834 } 5835 if (advertise & 0x8) { 5836 if (!(link_caps & IXGBE_LINK_SPEED_10_FULL)) { 5837 device_printf(dev, 5838 "Interface does not support 10Mb advertised speed" 5839 "\n"); 5840 return (EINVAL); 5841 } 5842 speed |= IXGBE_LINK_SPEED_10_FULL; 5843 } 5844 if (advertise & 0x10) { 5845 if (!(link_caps & IXGBE_LINK_SPEED_2_5GB_FULL)) { 5846 device_printf(dev, 5847 "Interface does not support 2.5G advertised speed" 5848 "\n"); 5849 return (EINVAL); 5850 } 5851 speed |= IXGBE_LINK_SPEED_2_5GB_FULL; 5852 } 5853 if (advertise & 0x20) { 5854 if (!(link_caps & IXGBE_LINK_SPEED_5GB_FULL)) { 5855 device_printf(dev, 5856 "Interface does not support 5G advertised speed" 5857 "\n"); 5858 return (EINVAL); 5859 } 5860 speed |= IXGBE_LINK_SPEED_5GB_FULL; 5861 } 5862 5863 hw->mac.autotry_restart = true; 5864 hw->mac.ops.setup_link(hw, speed, true); 5865 sc->advertise = advertise; 5866 5867 return (0); 5868 } /* ixgbe_set_advertise */ 5869 5870 /************************************************************************ 5871 * ixgbe_get_default_advertise - Get default advertised speed settings 5872 * 5873 * Formatted for sysctl usage. 5874 * Flags: 5875 * 0x1 - advertise 100 Mb 5876 * 0x2 - advertise 1G 5877 * 0x4 - advertise 10G 5878 * 0x8 - advertise 10 Mb (yes, Mb) 5879 * 0x10 - advertise 2.5G (disabled by default) 5880 * 0x20 - advertise 5G (disabled by default) 5881 ************************************************************************/ 5882 static int 5883 ixgbe_get_default_advertise(struct ixgbe_softc *sc) 5884 { 5885 struct ixgbe_hw *hw = &sc->hw; 5886 int speed; 5887 ixgbe_link_speed link_caps = 0; 5888 s32 err; 5889 bool negotiate = false; 5890 5891 /* 5892 * Advertised speed means nothing unless it's copper or 5893 * multi-speed fiber 5894 */ 5895 if (!(hw->phy.media_type == ixgbe_media_type_copper) && 5896 !(hw->phy.multispeed_fiber)) 5897 return (0); 5898 5899 err = hw->mac.ops.get_link_capabilities(hw, &link_caps, &negotiate); 5900 if (err != IXGBE_SUCCESS) 5901 return (0); 5902 5903 if (hw->mac.type == ixgbe_mac_X550) { 5904 /* 5905 * 2.5G and 5G autonegotiation speeds on X550 5906 * are disabled by default due to reported 5907 * interoperability issues with some switches. 5908 */ 5909 link_caps &= ~(IXGBE_LINK_SPEED_2_5GB_FULL | 5910 IXGBE_LINK_SPEED_5GB_FULL); 5911 } 5912 5913 speed = 5914 ((link_caps & IXGBE_LINK_SPEED_10GB_FULL) ? 0x4 : 0) | 5915 ((link_caps & IXGBE_LINK_SPEED_5GB_FULL) ? 0x20 : 0) | 5916 ((link_caps & IXGBE_LINK_SPEED_2_5GB_FULL) ? 0x10 : 0) | 5917 ((link_caps & IXGBE_LINK_SPEED_1GB_FULL) ? 0x2 : 0) | 5918 ((link_caps & IXGBE_LINK_SPEED_100_FULL) ? 0x1 : 0) | 5919 ((link_caps & IXGBE_LINK_SPEED_10_FULL) ? 0x8 : 0); 5920 5921 return speed; 5922 } /* ixgbe_get_default_advertise */ 5923 5924 /************************************************************************ 5925 * ixgbe_sysctl_dmac - Manage DMA Coalescing 5926 * 5927 * Control values: 5928 * 0/1 - off / on (use default value of 1000) 5929 * 5930 * Legal timer values are: 5931 * 50,100,250,500,1000,2000,5000,10000 5932 * 5933 * Turning off interrupt moderation will also turn this off. 5934 ************************************************************************/ 5935 static int 5936 ixgbe_sysctl_dmac(SYSCTL_HANDLER_ARGS) 5937 { 5938 struct ixgbe_softc *sc = (struct ixgbe_softc *)arg1; 5939 if_t ifp = iflib_get_ifp(sc->ctx); 5940 int error; 5941 u16 newval; 5942 5943 newval = sc->dmac; 5944 error = sysctl_handle_16(oidp, &newval, 0, req); 5945 if ((error) || (req->newptr == NULL)) 5946 return (error); 5947 5948 switch (newval) { 5949 case 0: 5950 /* Disabled */ 5951 sc->dmac = 0; 5952 break; 5953 case 1: 5954 /* Enable and use default */ 5955 sc->dmac = 1000; 5956 break; 5957 case 50: 5958 case 100: 5959 case 250: 5960 case 500: 5961 case 1000: 5962 case 2000: 5963 case 5000: 5964 case 10000: 5965 /* Legal values - allow */ 5966 sc->dmac = newval; 5967 break; 5968 default: 5969 /* Do nothing, illegal value */ 5970 return (EINVAL); 5971 } 5972 5973 /* Re-initialize hardware if it's already running */ 5974 if (if_getdrvflags(ifp) & IFF_DRV_RUNNING) 5975 if_init(ifp, ifp); 5976 5977 return (0); 5978 } /* ixgbe_sysctl_dmac */ 5979 5980 #ifdef IXGBE_DEBUG 5981 /************************************************************************ 5982 * ixgbe_sysctl_power_state 5983 * 5984 * Sysctl to test power states 5985 * Values: 5986 * 0 - set device to D0 5987 * 3 - set device to D3 5988 * (none) - get current device power state 5989 ************************************************************************/ 5990 static int 5991 ixgbe_sysctl_power_state(SYSCTL_HANDLER_ARGS) 5992 { 5993 struct ixgbe_softc *sc = (struct ixgbe_softc *)arg1; 5994 device_t dev = sc->dev; 5995 int curr_ps, new_ps, error = 0; 5996 5997 curr_ps = new_ps = pci_get_powerstate(dev); 5998 5999 error = sysctl_handle_int(oidp, &new_ps, 0, req); 6000 if ((error) || (req->newptr == NULL)) 6001 return (error); 6002 6003 if (new_ps == curr_ps) 6004 return (0); 6005 6006 if (new_ps == 3 && curr_ps == 0) 6007 error = DEVICE_SUSPEND(dev); 6008 else if (new_ps == 0 && curr_ps == 3) 6009 error = DEVICE_RESUME(dev); 6010 else 6011 return (EINVAL); 6012 6013 device_printf(dev, "New state: %d\n", pci_get_powerstate(dev)); 6014 6015 return (error); 6016 } /* ixgbe_sysctl_power_state */ 6017 #endif 6018 6019 #ifdef IXGBE_DEBUG 6020 /************************************************************************ 6021 * ixgbe_sysctl_print_rss_config 6022 ************************************************************************/ 6023 static int 6024 ixgbe_sysctl_print_rss_config(SYSCTL_HANDLER_ARGS) 6025 { 6026 struct ixgbe_softc *sc = (struct ixgbe_softc *)arg1; 6027 struct ixgbe_hw *hw = &sc->hw; 6028 device_t dev = sc->dev; 6029 struct sbuf *buf; 6030 int error = 0, reta_size; 6031 u32 reg; 6032 6033 if (atomic_load_acq_int(&sc->recovery_mode)) 6034 return (EPERM); 6035 6036 buf = sbuf_new_for_sysctl(NULL, NULL, 128, req); 6037 if (!buf) { 6038 device_printf(dev, "Could not allocate sbuf for output.\n"); 6039 return (ENOMEM); 6040 } 6041 6042 // TODO: use sbufs to make a string to print out 6043 /* Set multiplier for RETA setup and table size based on MAC */ 6044 switch (sc->hw.mac.type) { 6045 case ixgbe_mac_X550: 6046 case ixgbe_mac_X550EM_x: 6047 case ixgbe_mac_X550EM_a: 6048 reta_size = 128; 6049 break; 6050 default: 6051 reta_size = 32; 6052 break; 6053 } 6054 6055 /* Print out the redirection table */ 6056 sbuf_cat(buf, "\n"); 6057 for (int i = 0; i < reta_size; i++) { 6058 if (i < 32) { 6059 reg = IXGBE_READ_REG(hw, IXGBE_RETA(i)); 6060 sbuf_printf(buf, "RETA(%2d): 0x%08x\n", i, reg); 6061 } else { 6062 reg = IXGBE_READ_REG(hw, IXGBE_ERETA(i - 32)); 6063 sbuf_printf(buf, "ERETA(%2d): 0x%08x\n", i - 32, reg); 6064 } 6065 } 6066 6067 // TODO: print more config 6068 6069 error = sbuf_finish(buf); 6070 if (error) 6071 device_printf(dev, "Error finishing sbuf: %d\n", error); 6072 6073 sbuf_delete(buf); 6074 6075 return (0); 6076 } /* ixgbe_sysctl_print_rss_config */ 6077 #endif /* IXGBE_DEBUG */ 6078 6079 /************************************************************************ 6080 * ixgbe_sysctl_phy_temp - Retrieve temperature of PHY 6081 * 6082 * For X552/X557-AT devices using an external PHY 6083 ************************************************************************/ 6084 static int 6085 ixgbe_sysctl_phy_temp(SYSCTL_HANDLER_ARGS) 6086 { 6087 struct ixgbe_softc *sc = (struct ixgbe_softc *)arg1; 6088 struct ixgbe_hw *hw = &sc->hw; 6089 u16 reg; 6090 6091 if (atomic_load_acq_int(&sc->recovery_mode)) 6092 return (EPERM); 6093 6094 if (hw->device_id != IXGBE_DEV_ID_X550EM_X_10G_T) { 6095 device_printf(iflib_get_dev(sc->ctx), 6096 "Device has no supported external thermal sensor.\n"); 6097 return (ENODEV); 6098 } 6099 6100 if (hw->phy.ops.read_reg(hw, IXGBE_PHY_CURRENT_TEMP, 6101 IXGBE_MDIO_VENDOR_SPECIFIC_1_DEV_TYPE, ®)) { 6102 device_printf(iflib_get_dev(sc->ctx), 6103 "Error reading from PHY's current temperature register" 6104 "\n"); 6105 return (EAGAIN); 6106 } 6107 6108 /* Shift temp for output */ 6109 reg = reg >> 8; 6110 6111 return (sysctl_handle_16(oidp, NULL, reg, req)); 6112 } /* ixgbe_sysctl_phy_temp */ 6113 6114 /************************************************************************ 6115 * ixgbe_sysctl_phy_overtemp_occurred 6116 * 6117 * Reports (directly from the PHY) whether the current PHY 6118 * temperature is over the overtemp threshold. 6119 ************************************************************************/ 6120 static int 6121 ixgbe_sysctl_phy_overtemp_occurred(SYSCTL_HANDLER_ARGS) 6122 { 6123 struct ixgbe_softc *sc = (struct ixgbe_softc *)arg1; 6124 struct ixgbe_hw *hw = &sc->hw; 6125 u16 reg; 6126 6127 if (atomic_load_acq_int(&sc->recovery_mode)) 6128 return (EPERM); 6129 6130 if (hw->device_id != IXGBE_DEV_ID_X550EM_X_10G_T) { 6131 device_printf(iflib_get_dev(sc->ctx), 6132 "Device has no supported external thermal sensor.\n"); 6133 return (ENODEV); 6134 } 6135 6136 if (hw->phy.ops.read_reg(hw, IXGBE_PHY_OVERTEMP_STATUS, 6137 IXGBE_MDIO_VENDOR_SPECIFIC_1_DEV_TYPE, ®)) { 6138 device_printf(iflib_get_dev(sc->ctx), 6139 "Error reading from PHY's temperature status register\n"); 6140 return (EAGAIN); 6141 } 6142 6143 /* Get occurrence bit */ 6144 reg = !!(reg & 0x4000); 6145 6146 return (sysctl_handle_16(oidp, 0, reg, req)); 6147 } /* ixgbe_sysctl_phy_overtemp_occurred */ 6148 6149 /************************************************************************ 6150 * ixgbe_sysctl_eee_state 6151 * 6152 * Sysctl to set EEE power saving feature 6153 * Values: 6154 * 0 - disable EEE 6155 * 1 - enable EEE 6156 * (none) - get current device EEE state 6157 ************************************************************************/ 6158 static int 6159 ixgbe_sysctl_eee_state(SYSCTL_HANDLER_ARGS) 6160 { 6161 struct ixgbe_softc *sc = (struct ixgbe_softc *)arg1; 6162 device_t dev = sc->dev; 6163 if_t ifp = iflib_get_ifp(sc->ctx); 6164 int curr_eee, new_eee, error = 0; 6165 s32 retval; 6166 6167 if (atomic_load_acq_int(&sc->recovery_mode)) 6168 return (EPERM); 6169 6170 curr_eee = new_eee = !!(sc->feat_en & IXGBE_FEATURE_EEE); 6171 6172 error = sysctl_handle_int(oidp, &new_eee, 0, req); 6173 if ((error) || (req->newptr == NULL)) 6174 return (error); 6175 6176 /* Nothing to do */ 6177 if (new_eee == curr_eee) 6178 return (0); 6179 6180 /* Not supported */ 6181 if (!(sc->feat_cap & IXGBE_FEATURE_EEE)) 6182 return (EINVAL); 6183 6184 /* Bounds checking */ 6185 if ((new_eee < 0) || (new_eee > 1)) 6186 return (EINVAL); 6187 6188 /* If link speed is <= 1Gbps and EEE is being enabled, log info */ 6189 if (sc->hw.mac.type == ixgbe_mac_E610 && 6190 new_eee && 6191 sc->link_speed <= IXGBE_LINK_SPEED_1GB_FULL) { 6192 device_printf(dev, 6193 "Energy Efficient Ethernet (EEE) feature is not " 6194 "supported on link speeds equal to or below 1Gbps. " 6195 "EEE is supported on speeds above 1Gbps.\n"); 6196 return (EINVAL); 6197 } 6198 6199 retval = ixgbe_setup_eee(&sc->hw, new_eee); 6200 if (retval) { 6201 device_printf(dev, "Error in EEE setup: 0x%08X\n", retval); 6202 return (EINVAL); 6203 } 6204 6205 /* Restart auto-neg */ 6206 if_init(ifp, ifp); 6207 6208 device_printf(dev, "New EEE state: %d\n", new_eee); 6209 6210 /* Cache new value */ 6211 if (new_eee) 6212 sc->feat_en |= IXGBE_FEATURE_EEE; 6213 else 6214 sc->feat_en &= ~IXGBE_FEATURE_EEE; 6215 6216 return (error); 6217 } /* ixgbe_sysctl_eee_state */ 6218 6219 static int 6220 ixgbe_sysctl_tso_tcp_flags_mask(SYSCTL_HANDLER_ARGS) 6221 { 6222 struct ixgbe_softc *sc; 6223 u32 reg, val, shift; 6224 int error, mask; 6225 6226 sc = oidp->oid_arg1; 6227 switch (oidp->oid_arg2) { 6228 case 0: 6229 reg = IXGBE_DTXTCPFLGL; 6230 shift = 0; 6231 break; 6232 case 1: 6233 reg = IXGBE_DTXTCPFLGL; 6234 shift = 16; 6235 break; 6236 case 2: 6237 reg = IXGBE_DTXTCPFLGH; 6238 shift = 0; 6239 break; 6240 default: 6241 return (EINVAL); 6242 break; 6243 } 6244 val = IXGBE_READ_REG(&sc->hw, reg); 6245 mask = (val >> shift) & 0xfff; 6246 error = sysctl_handle_int(oidp, &mask, 0, req); 6247 if (error != 0 || req->newptr == NULL) 6248 return (error); 6249 if (mask < 0 || mask > 0xfff) 6250 return (EINVAL); 6251 val = (val & ~(0xfff << shift)) | (mask << shift); 6252 IXGBE_WRITE_REG(&sc->hw, reg, val); 6253 return (0); 6254 } 6255 6256 /************************************************************************ 6257 * ixgbe_init_device_features 6258 ************************************************************************/ 6259 static void 6260 ixgbe_init_device_features(struct ixgbe_softc *sc) 6261 { 6262 s32 error; 6263 6264 sc->feat_cap = IXGBE_FEATURE_NETMAP | 6265 IXGBE_FEATURE_RSS | 6266 IXGBE_FEATURE_MSI | 6267 IXGBE_FEATURE_MSIX | 6268 IXGBE_FEATURE_LEGACY_IRQ; 6269 6270 /* Set capabilities first... */ 6271 switch (sc->hw.mac.type) { 6272 case ixgbe_mac_82598EB: 6273 if (sc->hw.device_id == IXGBE_DEV_ID_82598AT) 6274 sc->feat_cap |= IXGBE_FEATURE_FAN_FAIL; 6275 break; 6276 case ixgbe_mac_X540: 6277 sc->feat_cap |= IXGBE_FEATURE_SRIOV; 6278 sc->feat_cap |= IXGBE_FEATURE_FDIR; 6279 if ((sc->hw.device_id == IXGBE_DEV_ID_X540_BYPASS) && 6280 (sc->hw.bus.func == 0)) 6281 sc->feat_cap |= IXGBE_FEATURE_BYPASS; 6282 break; 6283 case ixgbe_mac_X550: 6284 sc->feat_cap |= IXGBE_FEATURE_RECOVERY_MODE; 6285 sc->feat_cap |= IXGBE_FEATURE_TEMP_SENSOR; 6286 sc->feat_cap |= IXGBE_FEATURE_SRIOV; 6287 sc->feat_cap |= IXGBE_FEATURE_FDIR; 6288 break; 6289 case ixgbe_mac_X550EM_x: 6290 sc->feat_cap |= IXGBE_FEATURE_RECOVERY_MODE; 6291 sc->feat_cap |= IXGBE_FEATURE_SRIOV; 6292 sc->feat_cap |= IXGBE_FEATURE_FDIR; 6293 if (sc->hw.device_id == IXGBE_DEV_ID_X550EM_X_KR) 6294 sc->feat_cap |= IXGBE_FEATURE_EEE; 6295 break; 6296 case ixgbe_mac_X550EM_a: 6297 sc->feat_cap |= IXGBE_FEATURE_RECOVERY_MODE; 6298 sc->feat_cap |= IXGBE_FEATURE_SRIOV; 6299 sc->feat_cap |= IXGBE_FEATURE_FDIR; 6300 sc->feat_cap &= ~IXGBE_FEATURE_LEGACY_IRQ; 6301 if ((sc->hw.device_id == IXGBE_DEV_ID_X550EM_A_1G_T) || 6302 (sc->hw.device_id == IXGBE_DEV_ID_X550EM_A_1G_T_L)) { 6303 sc->feat_cap |= IXGBE_FEATURE_TEMP_SENSOR; 6304 sc->feat_cap |= IXGBE_FEATURE_EEE; 6305 } 6306 break; 6307 case ixgbe_mac_82599EB: 6308 sc->feat_cap |= IXGBE_FEATURE_SRIOV; 6309 sc->feat_cap |= IXGBE_FEATURE_FDIR; 6310 if ((sc->hw.device_id == IXGBE_DEV_ID_82599_BYPASS) && 6311 (sc->hw.bus.func == 0)) 6312 sc->feat_cap |= IXGBE_FEATURE_BYPASS; 6313 if (sc->hw.device_id == IXGBE_DEV_ID_82599_QSFP_SF_QP) 6314 sc->feat_cap &= ~IXGBE_FEATURE_LEGACY_IRQ; 6315 break; 6316 case ixgbe_mac_E610: 6317 sc->feat_cap |= IXGBE_FEATURE_RECOVERY_MODE; 6318 sc->feat_cap |= IXGBE_FEATURE_SRIOV; 6319 sc->feat_cap |= IXGBE_FEATURE_DBG_DUMP; 6320 sc->feat_cap |= IXGBE_FEATURE_FW_LOGGING; 6321 error = ixgbe_get_caps(&sc->hw); 6322 if (error == 0 && sc->hw.func_caps.common_cap.eee_support != 0) 6323 sc->feat_cap |= IXGBE_FEATURE_EEE; 6324 break; 6325 default: 6326 break; 6327 } 6328 6329 /* Enabled by default... */ 6330 /* Fan failure detection */ 6331 if (sc->feat_cap & IXGBE_FEATURE_FAN_FAIL) 6332 sc->feat_en |= IXGBE_FEATURE_FAN_FAIL; 6333 /* Netmap */ 6334 if (sc->feat_cap & IXGBE_FEATURE_NETMAP) 6335 sc->feat_en |= IXGBE_FEATURE_NETMAP; 6336 /* EEE */ 6337 if (sc->feat_cap & IXGBE_FEATURE_EEE) 6338 sc->feat_en |= IXGBE_FEATURE_EEE; 6339 /* Thermal Sensor */ 6340 if (sc->feat_cap & IXGBE_FEATURE_TEMP_SENSOR) 6341 sc->feat_en |= IXGBE_FEATURE_TEMP_SENSOR; 6342 /* Recovery mode */ 6343 if (sc->feat_cap & IXGBE_FEATURE_RECOVERY_MODE) 6344 sc->feat_en |= IXGBE_FEATURE_RECOVERY_MODE; 6345 /* FW Debug Dump */ 6346 if (sc->feat_cap & IXGBE_FEATURE_DBG_DUMP) 6347 sc->feat_en |= IXGBE_FEATURE_DBG_DUMP; 6348 /* FW Logging */ 6349 if (sc->feat_cap & IXGBE_FEATURE_FW_LOGGING) 6350 sc->feat_en |= IXGBE_FEATURE_FW_LOGGING; 6351 6352 /* Enabled via global sysctl... */ 6353 /* Flow Director */ 6354 if (ixgbe_enable_fdir) { 6355 if (sc->feat_cap & IXGBE_FEATURE_FDIR) 6356 sc->feat_en |= IXGBE_FEATURE_FDIR; 6357 else 6358 device_printf(sc->dev, 6359 "Device does not support Flow Director." 6360 " Leaving disabled."); 6361 } 6362 /* 6363 * Message Signal Interrupts - Extended (MSI-X) 6364 * Normal MSI is only enabled if MSI-X calls fail. 6365 */ 6366 if (!ixgbe_enable_msix) 6367 sc->feat_cap &= ~IXGBE_FEATURE_MSIX; 6368 /* Receive-Side Scaling (RSS) */ 6369 if ((sc->feat_cap & IXGBE_FEATURE_RSS) && ixgbe_enable_rss) 6370 sc->feat_en |= IXGBE_FEATURE_RSS; 6371 6372 /* Disable features with unmet dependencies... */ 6373 /* No MSI-X */ 6374 if (!(sc->feat_cap & IXGBE_FEATURE_MSIX)) { 6375 sc->feat_cap &= ~IXGBE_FEATURE_RSS; 6376 sc->feat_cap &= ~IXGBE_FEATURE_SRIOV; 6377 sc->feat_en &= ~IXGBE_FEATURE_RSS; 6378 sc->feat_en &= ~IXGBE_FEATURE_SRIOV; 6379 } 6380 } /* ixgbe_init_device_features */ 6381 6382 /************************************************************************ 6383 * ixgbe_check_fan_failure 6384 ************************************************************************/ 6385 static void 6386 ixgbe_check_fan_failure(struct ixgbe_softc *sc, u32 reg, bool in_interrupt) 6387 { 6388 u32 mask; 6389 6390 mask = (in_interrupt) ? IXGBE_EICR_GPI_SDP1_BY_MAC(&sc->hw) : 6391 IXGBE_ESDP_SDP1; 6392 6393 if (reg & mask) 6394 device_printf(sc->dev, 6395 "\nCRITICAL: FAN FAILURE!! REPLACE IMMEDIATELY!!\n"); 6396 } /* ixgbe_check_fan_failure */ 6397 6398 /************************************************************************ 6399 * ixgbe_sbuf_fw_version 6400 ************************************************************************/ 6401 static void 6402 ixgbe_sbuf_fw_version(struct ixgbe_hw *hw, struct sbuf *buf) 6403 { 6404 struct ixgbe_nvm_version nvm_ver = {0}; 6405 const char *space = ""; 6406 6407 ixgbe_get_nvm_version(hw, &nvm_ver); /* NVM version */ 6408 ixgbe_get_oem_prod_version(hw, &nvm_ver); /* OEM's NVM version */ 6409 ixgbe_get_etk_id(hw, &nvm_ver); /* eTrack a build ID in Intel's SCM */ 6410 ixgbe_get_orom_version(hw, &nvm_ver); /* Option ROM */ 6411 6412 /* FW version */ 6413 if ((nvm_ver.phy_fw_maj == 0x0 && 6414 nvm_ver.phy_fw_min == 0x0 && 6415 nvm_ver.phy_fw_id == 0x0) || 6416 (nvm_ver.phy_fw_maj == 0xF && 6417 nvm_ver.phy_fw_min == 0xFF && 6418 nvm_ver.phy_fw_id == 0xF)) { 6419 /* If major, minor and id numbers are set to 0, 6420 * reading FW version is unsupported. If major number 6421 * is set to 0xF, minor is set to 0xFF and id is set 6422 * to 0xF, this means that number read is invalid. */ 6423 } else 6424 sbuf_printf(buf, "fw %d.%d.%d ", 6425 nvm_ver.phy_fw_maj, nvm_ver.phy_fw_min, 6426 nvm_ver.phy_fw_id); 6427 6428 /* NVM version */ 6429 if ((nvm_ver.nvm_major == 0x0 && 6430 nvm_ver.nvm_minor == 0x0 && 6431 nvm_ver.nvm_id == 0x0) || 6432 (nvm_ver.nvm_major == 0xF && 6433 nvm_ver.nvm_minor == 0xFF && 6434 nvm_ver.nvm_id == 0xF)) { 6435 /* If major, minor and id numbers are set to 0, 6436 * reading NVM version is unsupported. If major number 6437 * is set to 0xF, minor is set to 0xFF and id is set 6438 * to 0xF, this means that number read is invalid. */ 6439 } else 6440 sbuf_printf(buf, "nvm %x.%02x.%x ", 6441 nvm_ver.nvm_major, nvm_ver.nvm_minor, nvm_ver.nvm_id); 6442 6443 if (nvm_ver.oem_valid) { 6444 sbuf_printf(buf, "NVM OEM V%d.%d R%d", nvm_ver.oem_major, 6445 nvm_ver.oem_minor, nvm_ver.oem_release); 6446 space = " "; 6447 } 6448 6449 if (nvm_ver.or_valid) { 6450 sbuf_printf(buf, "%sOption ROM V%d-b%d-p%d", 6451 space, nvm_ver.or_major, nvm_ver.or_build, 6452 nvm_ver.or_patch); 6453 space = " "; 6454 } 6455 6456 if (nvm_ver.etk_id != ((NVM_VER_INVALID << NVM_ETK_SHIFT) | 6457 NVM_VER_INVALID | 0xFFFFFFFF)) { 6458 sbuf_printf(buf, "%seTrack 0x%08x", space, nvm_ver.etk_id); 6459 } 6460 } /* ixgbe_sbuf_fw_version */ 6461 6462 /************************************************************************ 6463 * ixgbe_print_fw_version 6464 ************************************************************************/ 6465 static void 6466 ixgbe_print_fw_version(if_ctx_t ctx) 6467 { 6468 struct ixgbe_softc *sc = iflib_get_softc(ctx); 6469 struct ixgbe_hw *hw = &sc->hw; 6470 device_t dev = sc->dev; 6471 struct sbuf *buf; 6472 int error = 0; 6473 6474 buf = sbuf_new_auto(); 6475 if (!buf) { 6476 device_printf(dev, "Could not allocate sbuf for output.\n"); 6477 return; 6478 } 6479 6480 ixgbe_sbuf_fw_version(hw, buf); 6481 6482 error = sbuf_finish(buf); 6483 if (error) 6484 device_printf(dev, "Error finishing sbuf: %d\n", error); 6485 else if (sbuf_len(buf)) 6486 device_printf(dev, "%s\n", sbuf_data(buf)); 6487 6488 sbuf_delete(buf); 6489 } /* ixgbe_print_fw_version */ 6490 6491 /************************************************************************ 6492 * ixgbe_sysctl_print_fw_version 6493 ************************************************************************/ 6494 static int 6495 ixgbe_sysctl_print_fw_version(SYSCTL_HANDLER_ARGS) 6496 { 6497 struct ixgbe_softc *sc = (struct ixgbe_softc *)arg1; 6498 struct ixgbe_hw *hw = &sc->hw; 6499 device_t dev = sc->dev; 6500 struct sbuf *buf; 6501 int error = 0; 6502 6503 buf = sbuf_new_for_sysctl(NULL, NULL, 128, req); 6504 if (!buf) { 6505 device_printf(dev, "Could not allocate sbuf for output.\n"); 6506 return (ENOMEM); 6507 } 6508 6509 ixgbe_sbuf_fw_version(hw, buf); 6510 6511 error = sbuf_finish(buf); 6512 if (error) 6513 device_printf(dev, "Error finishing sbuf: %d\n", error); 6514 6515 sbuf_delete(buf); 6516 6517 return (0); 6518 } /* ixgbe_sysctl_print_fw_version */ 6519