1 /****************************************************************************** 2 3 Copyright (c) 2001-2017, Intel Corporation 4 All rights reserved. 5 6 Redistribution and use in source and binary forms, with or without 7 modification, are permitted provided that the following conditions are met: 8 9 1. Redistributions of source code must retain the above copyright notice, 10 this list of conditions and the following disclaimer. 11 12 2. Redistributions in binary form must reproduce the above copyright 13 notice, this list of conditions and the following disclaimer in the 14 documentation and/or other materials provided with the distribution. 15 16 3. Neither the name of the Intel Corporation nor the names of its 17 contributors may be used to endorse or promote products derived from 18 this software without specific prior written permission. 19 20 THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 21 AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 22 IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 23 ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE 24 LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 25 CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 26 SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 27 INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 28 CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 29 ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 30 POSSIBILITY OF SUCH DAMAGE. 31 32 ******************************************************************************/ 33 /*$FreeBSD$*/ 34 35 #include "opt_inet.h" 36 #include "opt_inet6.h" 37 #include "opt_rss.h" 38 39 #include "ixgbe.h" 40 #include "ixgbe_sriov.h" 41 #include "ifdi_if.h" 42 43 #include <net/netmap.h> 44 #include <dev/netmap/netmap_kern.h> 45 46 /************************************************************************ 47 * Driver version 48 ************************************************************************/ 49 char ixgbe_driver_version[] = "4.0.1-k"; 50 51 /************************************************************************ 52 * PCI Device ID Table 53 * 54 * Used by probe to select devices to load on 55 * Last field stores an index into ixgbe_strings 56 * Last entry must be all 0s 57 * 58 * { Vendor ID, Device ID, SubVendor ID, SubDevice ID, String Index } 59 ************************************************************************/ 60 static pci_vendor_info_t ixgbe_vendor_info_array[] = 61 { 62 PVID(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82598AF_DUAL_PORT, "Intel(R) 82598EB AF (Dual Fiber)"), 63 PVID(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82598AF_SINGLE_PORT, "Intel(R) 82598EB AF (Fiber)"), 64 PVID(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82598EB_CX4, "Intel(R) 82598EB AT (CX4)"), 65 PVID(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82598AT, "Intel(R) 82598EB AT"), 66 PVID(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82598AT2, "Intel(R) 82598EB AT2"), 67 PVID(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82598, "Intel(R) 82598"), 68 PVID(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82598_DA_DUAL_PORT, "Intel(R) 82598EB AF DA (Dual Fiber)"), 69 PVID(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82598_CX4_DUAL_PORT, "Intel(R) 82598EB AT (Dual CX4)"), 70 PVID(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82598EB_XF_LR, "Intel(R) 82598EB AF (Dual Fiber LR)"), 71 PVID(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82598_SR_DUAL_PORT_EM, "Intel(R) 82598EB AF (Dual Fiber SR)"), 72 PVID(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82598EB_SFP_LOM, "Intel(R) 82598EB LOM"), 73 PVID(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_KX4, "Intel(R) X520 82599 (KX4)"), 74 PVID(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_KX4_MEZZ, "Intel(R) X520 82599 (KX4 Mezzanine)"), 75 PVID(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_SFP, "Intel(R) X520 82599ES (SFI/SFP+)"), 76 PVID(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_XAUI_LOM, "Intel(R) X520 82599 (XAUI/BX4)"), 77 PVID(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_CX4, "Intel(R) X520 82599 (Dual CX4)"), 78 PVID(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_T3_LOM, "Intel(R) X520-T 82599 LOM"), 79 PVID(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_COMBO_BACKPLANE, "Intel(R) X520 82599 (Combined Backplane)"), 80 PVID(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_BACKPLANE_FCOE, "Intel(R) X520 82599 (Backplane w/FCoE)"), 81 PVID(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_SFP_SF2, "Intel(R) X520 82599 (Dual SFP+)"), 82 PVID(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_SFP_FCOE, "Intel(R) X520 82599 (Dual SFP+ w/FCoE)"), 83 PVID(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599EN_SFP, "Intel(R) X520-1 82599EN (SFP+)"), 84 PVID(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_SFP_SF_QP, "Intel(R) X520-4 82599 (Quad SFP+)"), 85 PVID(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_QSFP_SF_QP, "Intel(R) X520-Q1 82599 (QSFP+)"), 86 PVID(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X540T, "Intel(R) X540-AT2"), 87 PVID(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X540T1, "Intel(R) X540-T1"), 88 PVID(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550T, "Intel(R) X550-T2"), 89 PVID(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550T1, "Intel(R) X550-T1"), 90 PVID(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_X_KR, "Intel(R) X552 (KR Backplane)"), 91 PVID(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_X_KX4, "Intel(R) X552 (KX4 Backplane)"), 92 PVID(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_X_10G_T, "Intel(R) X552/X557-AT (10GBASE-T)"), 93 PVID(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_X_1G_T, "Intel(R) X552 (1000BASE-T)"), 94 PVID(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_X_SFP, "Intel(R) X552 (SFP+)"), 95 PVID(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_A_KR, "Intel(R) X553 (KR Backplane)"), 96 PVID(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_A_KR_L, "Intel(R) X553 L (KR Backplane)"), 97 PVID(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_A_SFP, "Intel(R) X553 (SFP+)"), 98 PVID(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_A_SFP_N, "Intel(R) X553 N (SFP+)"), 99 PVID(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_A_SGMII, "Intel(R) X553 (1GbE SGMII)"), 100 PVID(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_A_SGMII_L, "Intel(R) X553 L (1GbE SGMII)"), 101 PVID(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_A_10G_T, "Intel(R) X553/X557-AT (10GBASE-T)"), 102 PVID(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_A_1G_T, "Intel(R) X553 (1GbE)"), 103 PVID(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_A_1G_T_L, "Intel(R) X553 L (1GbE)"), 104 PVID(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X540_BYPASS, "Intel(R) X540-T2 (Bypass)"), 105 PVID(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_BYPASS, "Intel(R) X520 82599 (Bypass)"), 106 /* required last entry */ 107 PVID_END 108 }; 109 110 static void *ixgbe_register(device_t); 111 static int ixgbe_if_attach_pre(if_ctx_t); 112 static int ixgbe_if_attach_post(if_ctx_t); 113 static int ixgbe_if_detach(if_ctx_t); 114 static int ixgbe_if_shutdown(if_ctx_t); 115 static int ixgbe_if_suspend(if_ctx_t); 116 static int ixgbe_if_resume(if_ctx_t); 117 118 static void ixgbe_if_stop(if_ctx_t); 119 void ixgbe_if_enable_intr(if_ctx_t); 120 static void ixgbe_if_disable_intr(if_ctx_t); 121 static void ixgbe_link_intr_enable(if_ctx_t); 122 static int ixgbe_if_rx_queue_intr_enable(if_ctx_t, uint16_t); 123 static void ixgbe_if_media_status(if_ctx_t, struct ifmediareq *); 124 static int ixgbe_if_media_change(if_ctx_t); 125 static int ixgbe_if_msix_intr_assign(if_ctx_t, int); 126 static int ixgbe_if_mtu_set(if_ctx_t, uint32_t); 127 static void ixgbe_if_crcstrip_set(if_ctx_t, int, int); 128 static void ixgbe_if_multi_set(if_ctx_t); 129 static int ixgbe_if_promisc_set(if_ctx_t, int); 130 static int ixgbe_if_tx_queues_alloc(if_ctx_t, caddr_t *, uint64_t *, int, int); 131 static int ixgbe_if_rx_queues_alloc(if_ctx_t, caddr_t *, uint64_t *, int, int); 132 static void ixgbe_if_queues_free(if_ctx_t); 133 static void ixgbe_if_timer(if_ctx_t, uint16_t); 134 static void ixgbe_if_update_admin_status(if_ctx_t); 135 static void ixgbe_if_vlan_register(if_ctx_t, u16); 136 static void ixgbe_if_vlan_unregister(if_ctx_t, u16); 137 static int ixgbe_if_i2c_req(if_ctx_t, struct ifi2creq *); 138 static bool ixgbe_if_needs_restart(if_ctx_t, enum iflib_restart_event); 139 int ixgbe_intr(void *); 140 141 /************************************************************************ 142 * Function prototypes 143 ************************************************************************/ 144 static uint64_t ixgbe_if_get_counter(if_ctx_t, ift_counter); 145 146 static void ixgbe_enable_queue(struct ixgbe_softc *, u32); 147 static void ixgbe_disable_queue(struct ixgbe_softc *, u32); 148 static void ixgbe_add_device_sysctls(if_ctx_t); 149 static int ixgbe_allocate_pci_resources(if_ctx_t); 150 static int ixgbe_setup_low_power_mode(if_ctx_t); 151 152 static void ixgbe_config_dmac(struct ixgbe_softc *); 153 static void ixgbe_configure_ivars(struct ixgbe_softc *); 154 static void ixgbe_set_ivar(struct ixgbe_softc *, u8, u8, s8); 155 static u8 *ixgbe_mc_array_itr(struct ixgbe_hw *, u8 **, u32 *); 156 static bool ixgbe_sfp_probe(if_ctx_t); 157 158 static void ixgbe_free_pci_resources(if_ctx_t); 159 160 static int ixgbe_msix_link(void *); 161 static int ixgbe_msix_que(void *); 162 static void ixgbe_initialize_rss_mapping(struct ixgbe_softc *); 163 static void ixgbe_initialize_receive_units(if_ctx_t); 164 static void ixgbe_initialize_transmit_units(if_ctx_t); 165 166 static int ixgbe_setup_interface(if_ctx_t); 167 static void ixgbe_init_device_features(struct ixgbe_softc *); 168 static void ixgbe_check_fan_failure(struct ixgbe_softc *, u32, bool); 169 static void ixgbe_sbuf_fw_version(struct ixgbe_hw *, struct sbuf *); 170 static void ixgbe_print_fw_version(if_ctx_t); 171 static void ixgbe_add_media_types(if_ctx_t); 172 static void ixgbe_update_stats_counters(struct ixgbe_softc *); 173 static void ixgbe_config_link(if_ctx_t); 174 static void ixgbe_get_slot_info(struct ixgbe_softc *); 175 static void ixgbe_check_wol_support(struct ixgbe_softc *); 176 static void ixgbe_enable_rx_drop(struct ixgbe_softc *); 177 static void ixgbe_disable_rx_drop(struct ixgbe_softc *); 178 179 static void ixgbe_add_hw_stats(struct ixgbe_softc *); 180 static int ixgbe_set_flowcntl(struct ixgbe_softc *, int); 181 static int ixgbe_set_advertise(struct ixgbe_softc *, int); 182 static int ixgbe_get_default_advertise(struct ixgbe_softc *); 183 static void ixgbe_setup_vlan_hw_support(if_ctx_t); 184 static void ixgbe_config_gpie(struct ixgbe_softc *); 185 static void ixgbe_config_delay_values(struct ixgbe_softc *); 186 187 /* Sysctl handlers */ 188 static int ixgbe_sysctl_flowcntl(SYSCTL_HANDLER_ARGS); 189 static int ixgbe_sysctl_advertise(SYSCTL_HANDLER_ARGS); 190 static int ixgbe_sysctl_interrupt_rate_handler(SYSCTL_HANDLER_ARGS); 191 static int ixgbe_sysctl_dmac(SYSCTL_HANDLER_ARGS); 192 static int ixgbe_sysctl_phy_temp(SYSCTL_HANDLER_ARGS); 193 static int ixgbe_sysctl_phy_overtemp_occurred(SYSCTL_HANDLER_ARGS); 194 static int ixgbe_sysctl_print_fw_version(SYSCTL_HANDLER_ARGS); 195 #ifdef IXGBE_DEBUG 196 static int ixgbe_sysctl_power_state(SYSCTL_HANDLER_ARGS); 197 static int ixgbe_sysctl_print_rss_config(SYSCTL_HANDLER_ARGS); 198 #endif 199 static int ixgbe_sysctl_rdh_handler(SYSCTL_HANDLER_ARGS); 200 static int ixgbe_sysctl_rdt_handler(SYSCTL_HANDLER_ARGS); 201 static int ixgbe_sysctl_tdt_handler(SYSCTL_HANDLER_ARGS); 202 static int ixgbe_sysctl_tdh_handler(SYSCTL_HANDLER_ARGS); 203 static int ixgbe_sysctl_eee_state(SYSCTL_HANDLER_ARGS); 204 static int ixgbe_sysctl_wol_enable(SYSCTL_HANDLER_ARGS); 205 static int ixgbe_sysctl_wufc(SYSCTL_HANDLER_ARGS); 206 207 /* Deferred interrupt tasklets */ 208 static void ixgbe_handle_msf(void *); 209 static void ixgbe_handle_mod(void *); 210 static void ixgbe_handle_phy(void *); 211 212 /************************************************************************ 213 * FreeBSD Device Interface Entry Points 214 ************************************************************************/ 215 static device_method_t ix_methods[] = { 216 /* Device interface */ 217 DEVMETHOD(device_register, ixgbe_register), 218 DEVMETHOD(device_probe, iflib_device_probe), 219 DEVMETHOD(device_attach, iflib_device_attach), 220 DEVMETHOD(device_detach, iflib_device_detach), 221 DEVMETHOD(device_shutdown, iflib_device_shutdown), 222 DEVMETHOD(device_suspend, iflib_device_suspend), 223 DEVMETHOD(device_resume, iflib_device_resume), 224 #ifdef PCI_IOV 225 DEVMETHOD(pci_iov_init, iflib_device_iov_init), 226 DEVMETHOD(pci_iov_uninit, iflib_device_iov_uninit), 227 DEVMETHOD(pci_iov_add_vf, iflib_device_iov_add_vf), 228 #endif /* PCI_IOV */ 229 DEVMETHOD_END 230 }; 231 232 static driver_t ix_driver = { 233 "ix", ix_methods, sizeof(struct ixgbe_softc), 234 }; 235 236 DRIVER_MODULE(ix, pci, ix_driver, 0, 0); 237 IFLIB_PNP_INFO(pci, ix_driver, ixgbe_vendor_info_array); 238 MODULE_DEPEND(ix, pci, 1, 1, 1); 239 MODULE_DEPEND(ix, ether, 1, 1, 1); 240 MODULE_DEPEND(ix, iflib, 1, 1, 1); 241 242 static device_method_t ixgbe_if_methods[] = { 243 DEVMETHOD(ifdi_attach_pre, ixgbe_if_attach_pre), 244 DEVMETHOD(ifdi_attach_post, ixgbe_if_attach_post), 245 DEVMETHOD(ifdi_detach, ixgbe_if_detach), 246 DEVMETHOD(ifdi_shutdown, ixgbe_if_shutdown), 247 DEVMETHOD(ifdi_suspend, ixgbe_if_suspend), 248 DEVMETHOD(ifdi_resume, ixgbe_if_resume), 249 DEVMETHOD(ifdi_init, ixgbe_if_init), 250 DEVMETHOD(ifdi_stop, ixgbe_if_stop), 251 DEVMETHOD(ifdi_msix_intr_assign, ixgbe_if_msix_intr_assign), 252 DEVMETHOD(ifdi_intr_enable, ixgbe_if_enable_intr), 253 DEVMETHOD(ifdi_intr_disable, ixgbe_if_disable_intr), 254 DEVMETHOD(ifdi_link_intr_enable, ixgbe_link_intr_enable), 255 DEVMETHOD(ifdi_tx_queue_intr_enable, ixgbe_if_rx_queue_intr_enable), 256 DEVMETHOD(ifdi_rx_queue_intr_enable, ixgbe_if_rx_queue_intr_enable), 257 DEVMETHOD(ifdi_tx_queues_alloc, ixgbe_if_tx_queues_alloc), 258 DEVMETHOD(ifdi_rx_queues_alloc, ixgbe_if_rx_queues_alloc), 259 DEVMETHOD(ifdi_queues_free, ixgbe_if_queues_free), 260 DEVMETHOD(ifdi_update_admin_status, ixgbe_if_update_admin_status), 261 DEVMETHOD(ifdi_multi_set, ixgbe_if_multi_set), 262 DEVMETHOD(ifdi_mtu_set, ixgbe_if_mtu_set), 263 DEVMETHOD(ifdi_crcstrip_set, ixgbe_if_crcstrip_set), 264 DEVMETHOD(ifdi_media_status, ixgbe_if_media_status), 265 DEVMETHOD(ifdi_media_change, ixgbe_if_media_change), 266 DEVMETHOD(ifdi_promisc_set, ixgbe_if_promisc_set), 267 DEVMETHOD(ifdi_timer, ixgbe_if_timer), 268 DEVMETHOD(ifdi_vlan_register, ixgbe_if_vlan_register), 269 DEVMETHOD(ifdi_vlan_unregister, ixgbe_if_vlan_unregister), 270 DEVMETHOD(ifdi_get_counter, ixgbe_if_get_counter), 271 DEVMETHOD(ifdi_i2c_req, ixgbe_if_i2c_req), 272 DEVMETHOD(ifdi_needs_restart, ixgbe_if_needs_restart), 273 #ifdef PCI_IOV 274 DEVMETHOD(ifdi_iov_init, ixgbe_if_iov_init), 275 DEVMETHOD(ifdi_iov_uninit, ixgbe_if_iov_uninit), 276 DEVMETHOD(ifdi_iov_vf_add, ixgbe_if_iov_vf_add), 277 #endif /* PCI_IOV */ 278 DEVMETHOD_END 279 }; 280 281 /* 282 * TUNEABLE PARAMETERS: 283 */ 284 285 static SYSCTL_NODE(_hw, OID_AUTO, ix, CTLFLAG_RD | CTLFLAG_MPSAFE, 0, 286 "IXGBE driver parameters"); 287 static driver_t ixgbe_if_driver = { 288 "ixgbe_if", ixgbe_if_methods, sizeof(struct ixgbe_softc) 289 }; 290 291 static int ixgbe_max_interrupt_rate = (4000000 / IXGBE_LOW_LATENCY); 292 SYSCTL_INT(_hw_ix, OID_AUTO, max_interrupt_rate, CTLFLAG_RDTUN, 293 &ixgbe_max_interrupt_rate, 0, "Maximum interrupts per second"); 294 295 /* Flow control setting, default to full */ 296 static int ixgbe_flow_control = ixgbe_fc_full; 297 SYSCTL_INT(_hw_ix, OID_AUTO, flow_control, CTLFLAG_RDTUN, 298 &ixgbe_flow_control, 0, "Default flow control used for all adapters"); 299 300 /* Advertise Speed, default to 0 (auto) */ 301 static int ixgbe_advertise_speed = 0; 302 SYSCTL_INT(_hw_ix, OID_AUTO, advertise_speed, CTLFLAG_RDTUN, 303 &ixgbe_advertise_speed, 0, "Default advertised speed for all adapters"); 304 305 /* 306 * Smart speed setting, default to on 307 * this only works as a compile option 308 * right now as its during attach, set 309 * this to 'ixgbe_smart_speed_off' to 310 * disable. 311 */ 312 static int ixgbe_smart_speed = ixgbe_smart_speed_on; 313 314 /* 315 * MSI-X should be the default for best performance, 316 * but this allows it to be forced off for testing. 317 */ 318 static int ixgbe_enable_msix = 1; 319 SYSCTL_INT(_hw_ix, OID_AUTO, enable_msix, CTLFLAG_RDTUN, &ixgbe_enable_msix, 0, 320 "Enable MSI-X interrupts"); 321 322 /* 323 * Defining this on will allow the use 324 * of unsupported SFP+ modules, note that 325 * doing so you are on your own :) 326 */ 327 static int allow_unsupported_sfp = false; 328 SYSCTL_INT(_hw_ix, OID_AUTO, unsupported_sfp, CTLFLAG_RDTUN, 329 &allow_unsupported_sfp, 0, 330 "Allow unsupported SFP modules...use at your own risk"); 331 332 /* 333 * Not sure if Flow Director is fully baked, 334 * so we'll default to turning it off. 335 */ 336 static int ixgbe_enable_fdir = 0; 337 SYSCTL_INT(_hw_ix, OID_AUTO, enable_fdir, CTLFLAG_RDTUN, &ixgbe_enable_fdir, 0, 338 "Enable Flow Director"); 339 340 /* Receive-Side Scaling */ 341 static int ixgbe_enable_rss = 1; 342 SYSCTL_INT(_hw_ix, OID_AUTO, enable_rss, CTLFLAG_RDTUN, &ixgbe_enable_rss, 0, 343 "Enable Receive-Side Scaling (RSS)"); 344 345 /* 346 * AIM: Adaptive Interrupt Moderation 347 * which means that the interrupt rate 348 * is varied over time based on the 349 * traffic for that interrupt vector 350 */ 351 static int ixgbe_enable_aim = false; 352 SYSCTL_INT(_hw_ix, OID_AUTO, enable_aim, CTLFLAG_RWTUN, &ixgbe_enable_aim, 0, 353 "Enable adaptive interrupt moderation"); 354 355 #if 0 356 /* Keep running tab on them for sanity check */ 357 static int ixgbe_total_ports; 358 #endif 359 360 MALLOC_DEFINE(M_IXGBE, "ix", "ix driver allocations"); 361 362 /* 363 * For Flow Director: this is the number of TX packets we sample 364 * for the filter pool, this means every 20th packet will be probed. 365 * 366 * This feature can be disabled by setting this to 0. 367 */ 368 static int atr_sample_rate = 20; 369 370 extern struct if_txrx ixgbe_txrx; 371 372 static struct if_shared_ctx ixgbe_sctx_init = { 373 .isc_magic = IFLIB_MAGIC, 374 .isc_q_align = PAGE_SIZE,/* max(DBA_ALIGN, PAGE_SIZE) */ 375 .isc_tx_maxsize = IXGBE_TSO_SIZE + sizeof(struct ether_vlan_header), 376 .isc_tx_maxsegsize = PAGE_SIZE, 377 .isc_tso_maxsize = IXGBE_TSO_SIZE + sizeof(struct ether_vlan_header), 378 .isc_tso_maxsegsize = PAGE_SIZE, 379 .isc_rx_maxsize = PAGE_SIZE*4, 380 .isc_rx_nsegments = 1, 381 .isc_rx_maxsegsize = PAGE_SIZE*4, 382 .isc_nfl = 1, 383 .isc_ntxqs = 1, 384 .isc_nrxqs = 1, 385 386 .isc_admin_intrcnt = 1, 387 .isc_vendor_info = ixgbe_vendor_info_array, 388 .isc_driver_version = ixgbe_driver_version, 389 .isc_driver = &ixgbe_if_driver, 390 .isc_flags = IFLIB_TSO_INIT_IP, 391 392 .isc_nrxd_min = {MIN_RXD}, 393 .isc_ntxd_min = {MIN_TXD}, 394 .isc_nrxd_max = {MAX_RXD}, 395 .isc_ntxd_max = {MAX_TXD}, 396 .isc_nrxd_default = {DEFAULT_RXD}, 397 .isc_ntxd_default = {DEFAULT_TXD}, 398 }; 399 400 /************************************************************************ 401 * ixgbe_if_tx_queues_alloc 402 ************************************************************************/ 403 static int 404 ixgbe_if_tx_queues_alloc(if_ctx_t ctx, caddr_t *vaddrs, uint64_t *paddrs, 405 int ntxqs, int ntxqsets) 406 { 407 struct ixgbe_softc *sc = iflib_get_softc(ctx); 408 if_softc_ctx_t scctx = sc->shared; 409 struct ix_tx_queue *que; 410 int i, j, error; 411 412 MPASS(sc->num_tx_queues > 0); 413 MPASS(sc->num_tx_queues == ntxqsets); 414 MPASS(ntxqs == 1); 415 416 /* Allocate queue structure memory */ 417 sc->tx_queues = 418 (struct ix_tx_queue *)malloc(sizeof(struct ix_tx_queue) * ntxqsets, 419 M_IXGBE, M_NOWAIT | M_ZERO); 420 if (!sc->tx_queues) { 421 device_printf(iflib_get_dev(ctx), 422 "Unable to allocate TX ring memory\n"); 423 return (ENOMEM); 424 } 425 426 for (i = 0, que = sc->tx_queues; i < ntxqsets; i++, que++) { 427 struct tx_ring *txr = &que->txr; 428 429 /* In case SR-IOV is enabled, align the index properly */ 430 txr->me = ixgbe_vf_que_index(sc->iov_mode, sc->pool, 431 i); 432 433 txr->sc = que->sc = sc; 434 435 /* Allocate report status array */ 436 txr->tx_rsq = (qidx_t *)malloc(sizeof(qidx_t) * scctx->isc_ntxd[0], M_IXGBE, M_NOWAIT | M_ZERO); 437 if (txr->tx_rsq == NULL) { 438 error = ENOMEM; 439 goto fail; 440 } 441 for (j = 0; j < scctx->isc_ntxd[0]; j++) 442 txr->tx_rsq[j] = QIDX_INVALID; 443 /* get the virtual and physical address of the hardware queues */ 444 txr->tail = IXGBE_TDT(txr->me); 445 txr->tx_base = (union ixgbe_adv_tx_desc *)vaddrs[i]; 446 txr->tx_paddr = paddrs[i]; 447 448 txr->bytes = 0; 449 txr->total_packets = 0; 450 451 /* Set the rate at which we sample packets */ 452 if (sc->feat_en & IXGBE_FEATURE_FDIR) 453 txr->atr_sample = atr_sample_rate; 454 455 } 456 457 device_printf(iflib_get_dev(ctx), "allocated for %d queues\n", 458 sc->num_tx_queues); 459 460 return (0); 461 462 fail: 463 ixgbe_if_queues_free(ctx); 464 465 return (error); 466 } /* ixgbe_if_tx_queues_alloc */ 467 468 /************************************************************************ 469 * ixgbe_if_rx_queues_alloc 470 ************************************************************************/ 471 static int 472 ixgbe_if_rx_queues_alloc(if_ctx_t ctx, caddr_t *vaddrs, uint64_t *paddrs, 473 int nrxqs, int nrxqsets) 474 { 475 struct ixgbe_softc *sc = iflib_get_softc(ctx); 476 struct ix_rx_queue *que; 477 int i; 478 479 MPASS(sc->num_rx_queues > 0); 480 MPASS(sc->num_rx_queues == nrxqsets); 481 MPASS(nrxqs == 1); 482 483 /* Allocate queue structure memory */ 484 sc->rx_queues = 485 (struct ix_rx_queue *)malloc(sizeof(struct ix_rx_queue)*nrxqsets, 486 M_IXGBE, M_NOWAIT | M_ZERO); 487 if (!sc->rx_queues) { 488 device_printf(iflib_get_dev(ctx), 489 "Unable to allocate TX ring memory\n"); 490 return (ENOMEM); 491 } 492 493 for (i = 0, que = sc->rx_queues; i < nrxqsets; i++, que++) { 494 struct rx_ring *rxr = &que->rxr; 495 496 /* In case SR-IOV is enabled, align the index properly */ 497 rxr->me = ixgbe_vf_que_index(sc->iov_mode, sc->pool, 498 i); 499 500 rxr->sc = que->sc = sc; 501 502 /* get the virtual and physical address of the hw queues */ 503 rxr->tail = IXGBE_RDT(rxr->me); 504 rxr->rx_base = (union ixgbe_adv_rx_desc *)vaddrs[i]; 505 rxr->rx_paddr = paddrs[i]; 506 rxr->bytes = 0; 507 rxr->que = que; 508 } 509 510 device_printf(iflib_get_dev(ctx), "allocated for %d rx queues\n", 511 sc->num_rx_queues); 512 513 return (0); 514 } /* ixgbe_if_rx_queues_alloc */ 515 516 /************************************************************************ 517 * ixgbe_if_queues_free 518 ************************************************************************/ 519 static void 520 ixgbe_if_queues_free(if_ctx_t ctx) 521 { 522 struct ixgbe_softc *sc = iflib_get_softc(ctx); 523 struct ix_tx_queue *tx_que = sc->tx_queues; 524 struct ix_rx_queue *rx_que = sc->rx_queues; 525 int i; 526 527 if (tx_que != NULL) { 528 for (i = 0; i < sc->num_tx_queues; i++, tx_que++) { 529 struct tx_ring *txr = &tx_que->txr; 530 if (txr->tx_rsq == NULL) 531 break; 532 533 free(txr->tx_rsq, M_IXGBE); 534 txr->tx_rsq = NULL; 535 } 536 537 free(sc->tx_queues, M_IXGBE); 538 sc->tx_queues = NULL; 539 } 540 if (rx_que != NULL) { 541 free(sc->rx_queues, M_IXGBE); 542 sc->rx_queues = NULL; 543 } 544 } /* ixgbe_if_queues_free */ 545 546 /************************************************************************ 547 * ixgbe_initialize_rss_mapping 548 ************************************************************************/ 549 static void 550 ixgbe_initialize_rss_mapping(struct ixgbe_softc *sc) 551 { 552 struct ixgbe_hw *hw = &sc->hw; 553 u32 reta = 0, mrqc, rss_key[10]; 554 int queue_id, table_size, index_mult; 555 int i, j; 556 u32 rss_hash_config; 557 558 if (sc->feat_en & IXGBE_FEATURE_RSS) { 559 /* Fetch the configured RSS key */ 560 rss_getkey((uint8_t *)&rss_key); 561 } else { 562 /* set up random bits */ 563 arc4rand(&rss_key, sizeof(rss_key), 0); 564 } 565 566 /* Set multiplier for RETA setup and table size based on MAC */ 567 index_mult = 0x1; 568 table_size = 128; 569 switch (sc->hw.mac.type) { 570 case ixgbe_mac_82598EB: 571 index_mult = 0x11; 572 break; 573 case ixgbe_mac_X550: 574 case ixgbe_mac_X550EM_x: 575 case ixgbe_mac_X550EM_a: 576 table_size = 512; 577 break; 578 default: 579 break; 580 } 581 582 /* Set up the redirection table */ 583 for (i = 0, j = 0; i < table_size; i++, j++) { 584 if (j == sc->num_rx_queues) 585 j = 0; 586 587 if (sc->feat_en & IXGBE_FEATURE_RSS) { 588 /* 589 * Fetch the RSS bucket id for the given indirection 590 * entry. Cap it at the number of configured buckets 591 * (which is num_rx_queues.) 592 */ 593 queue_id = rss_get_indirection_to_bucket(i); 594 queue_id = queue_id % sc->num_rx_queues; 595 } else 596 queue_id = (j * index_mult); 597 598 /* 599 * The low 8 bits are for hash value (n+0); 600 * The next 8 bits are for hash value (n+1), etc. 601 */ 602 reta = reta >> 8; 603 reta = reta | (((uint32_t)queue_id) << 24); 604 if ((i & 3) == 3) { 605 if (i < 128) 606 IXGBE_WRITE_REG(hw, IXGBE_RETA(i >> 2), reta); 607 else 608 IXGBE_WRITE_REG(hw, IXGBE_ERETA((i >> 2) - 32), 609 reta); 610 reta = 0; 611 } 612 } 613 614 /* Now fill our hash function seeds */ 615 for (i = 0; i < 10; i++) 616 IXGBE_WRITE_REG(hw, IXGBE_RSSRK(i), rss_key[i]); 617 618 /* Perform hash on these packet types */ 619 if (sc->feat_en & IXGBE_FEATURE_RSS) 620 rss_hash_config = rss_gethashconfig(); 621 else { 622 /* 623 * Disable UDP - IP fragments aren't currently being handled 624 * and so we end up with a mix of 2-tuple and 4-tuple 625 * traffic. 626 */ 627 rss_hash_config = RSS_HASHTYPE_RSS_IPV4 628 | RSS_HASHTYPE_RSS_TCP_IPV4 629 | RSS_HASHTYPE_RSS_IPV6 630 | RSS_HASHTYPE_RSS_TCP_IPV6 631 | RSS_HASHTYPE_RSS_IPV6_EX 632 | RSS_HASHTYPE_RSS_TCP_IPV6_EX; 633 } 634 635 mrqc = IXGBE_MRQC_RSSEN; 636 if (rss_hash_config & RSS_HASHTYPE_RSS_IPV4) 637 mrqc |= IXGBE_MRQC_RSS_FIELD_IPV4; 638 if (rss_hash_config & RSS_HASHTYPE_RSS_TCP_IPV4) 639 mrqc |= IXGBE_MRQC_RSS_FIELD_IPV4_TCP; 640 if (rss_hash_config & RSS_HASHTYPE_RSS_IPV6) 641 mrqc |= IXGBE_MRQC_RSS_FIELD_IPV6; 642 if (rss_hash_config & RSS_HASHTYPE_RSS_TCP_IPV6) 643 mrqc |= IXGBE_MRQC_RSS_FIELD_IPV6_TCP; 644 if (rss_hash_config & RSS_HASHTYPE_RSS_IPV6_EX) 645 mrqc |= IXGBE_MRQC_RSS_FIELD_IPV6_EX; 646 if (rss_hash_config & RSS_HASHTYPE_RSS_TCP_IPV6_EX) 647 mrqc |= IXGBE_MRQC_RSS_FIELD_IPV6_EX_TCP; 648 if (rss_hash_config & RSS_HASHTYPE_RSS_UDP_IPV4) 649 mrqc |= IXGBE_MRQC_RSS_FIELD_IPV4_UDP; 650 if (rss_hash_config & RSS_HASHTYPE_RSS_UDP_IPV6) 651 mrqc |= IXGBE_MRQC_RSS_FIELD_IPV6_UDP; 652 if (rss_hash_config & RSS_HASHTYPE_RSS_UDP_IPV6_EX) 653 mrqc |= IXGBE_MRQC_RSS_FIELD_IPV6_EX_UDP; 654 mrqc |= ixgbe_get_mrqc(sc->iov_mode); 655 IXGBE_WRITE_REG(hw, IXGBE_MRQC, mrqc); 656 } /* ixgbe_initialize_rss_mapping */ 657 658 /************************************************************************ 659 * ixgbe_initialize_receive_units - Setup receive registers and features. 660 ************************************************************************/ 661 #define BSIZEPKT_ROUNDUP ((1<<IXGBE_SRRCTL_BSIZEPKT_SHIFT)-1) 662 663 static void 664 ixgbe_initialize_receive_units(if_ctx_t ctx) 665 { 666 struct ixgbe_softc *sc = iflib_get_softc(ctx); 667 if_softc_ctx_t scctx = sc->shared; 668 struct ixgbe_hw *hw = &sc->hw; 669 if_t ifp = iflib_get_ifp(ctx); 670 struct ix_rx_queue *que; 671 int i, j; 672 u32 bufsz, fctrl, srrctl, rxcsum; 673 u32 hlreg; 674 675 /* 676 * Make sure receives are disabled while 677 * setting up the descriptor ring 678 */ 679 ixgbe_disable_rx(hw); 680 681 /* Enable broadcasts */ 682 fctrl = IXGBE_READ_REG(hw, IXGBE_FCTRL); 683 fctrl |= IXGBE_FCTRL_BAM; 684 if (sc->hw.mac.type == ixgbe_mac_82598EB) { 685 fctrl |= IXGBE_FCTRL_DPF; 686 fctrl |= IXGBE_FCTRL_PMCF; 687 } 688 IXGBE_WRITE_REG(hw, IXGBE_FCTRL, fctrl); 689 690 /* Set for Jumbo Frames? */ 691 hlreg = IXGBE_READ_REG(hw, IXGBE_HLREG0); 692 if (if_getmtu(ifp) > ETHERMTU) 693 hlreg |= IXGBE_HLREG0_JUMBOEN; 694 else 695 hlreg &= ~IXGBE_HLREG0_JUMBOEN; 696 IXGBE_WRITE_REG(hw, IXGBE_HLREG0, hlreg); 697 698 bufsz = (sc->rx_mbuf_sz + BSIZEPKT_ROUNDUP) >> 699 IXGBE_SRRCTL_BSIZEPKT_SHIFT; 700 701 /* Setup the Base and Length of the Rx Descriptor Ring */ 702 for (i = 0, que = sc->rx_queues; i < sc->num_rx_queues; i++, que++) { 703 struct rx_ring *rxr = &que->rxr; 704 u64 rdba = rxr->rx_paddr; 705 706 j = rxr->me; 707 708 /* Setup the Base and Length of the Rx Descriptor Ring */ 709 IXGBE_WRITE_REG(hw, IXGBE_RDBAL(j), 710 (rdba & 0x00000000ffffffffULL)); 711 IXGBE_WRITE_REG(hw, IXGBE_RDBAH(j), (rdba >> 32)); 712 IXGBE_WRITE_REG(hw, IXGBE_RDLEN(j), 713 scctx->isc_nrxd[0] * sizeof(union ixgbe_adv_rx_desc)); 714 715 /* Set up the SRRCTL register */ 716 srrctl = IXGBE_READ_REG(hw, IXGBE_SRRCTL(j)); 717 srrctl &= ~IXGBE_SRRCTL_BSIZEHDR_MASK; 718 srrctl &= ~IXGBE_SRRCTL_BSIZEPKT_MASK; 719 srrctl |= bufsz; 720 srrctl |= IXGBE_SRRCTL_DESCTYPE_ADV_ONEBUF; 721 722 /* 723 * Set DROP_EN iff we have no flow control and >1 queue. 724 * Note that srrctl was cleared shortly before during reset, 725 * so we do not need to clear the bit, but do it just in case 726 * this code is moved elsewhere. 727 */ 728 if (sc->num_rx_queues > 1 && 729 sc->hw.fc.requested_mode == ixgbe_fc_none) { 730 srrctl |= IXGBE_SRRCTL_DROP_EN; 731 } else { 732 srrctl &= ~IXGBE_SRRCTL_DROP_EN; 733 } 734 735 IXGBE_WRITE_REG(hw, IXGBE_SRRCTL(j), srrctl); 736 737 /* Setup the HW Rx Head and Tail Descriptor Pointers */ 738 IXGBE_WRITE_REG(hw, IXGBE_RDH(j), 0); 739 IXGBE_WRITE_REG(hw, IXGBE_RDT(j), 0); 740 741 /* Set the driver rx tail address */ 742 rxr->tail = IXGBE_RDT(rxr->me); 743 } 744 745 if (sc->hw.mac.type != ixgbe_mac_82598EB) { 746 u32 psrtype = IXGBE_PSRTYPE_TCPHDR 747 | IXGBE_PSRTYPE_UDPHDR 748 | IXGBE_PSRTYPE_IPV4HDR 749 | IXGBE_PSRTYPE_IPV6HDR; 750 IXGBE_WRITE_REG(hw, IXGBE_PSRTYPE(0), psrtype); 751 } 752 753 rxcsum = IXGBE_READ_REG(hw, IXGBE_RXCSUM); 754 755 ixgbe_initialize_rss_mapping(sc); 756 757 if (sc->feat_en & IXGBE_FEATURE_RSS) { 758 /* RSS and RX IPP Checksum are mutually exclusive */ 759 rxcsum |= IXGBE_RXCSUM_PCSD; 760 } 761 762 if (if_getcapenable(ifp) & IFCAP_RXCSUM) 763 rxcsum |= IXGBE_RXCSUM_PCSD; 764 765 /* This is useful for calculating UDP/IP fragment checksums */ 766 if (!(rxcsum & IXGBE_RXCSUM_PCSD)) 767 rxcsum |= IXGBE_RXCSUM_IPPCSE; 768 769 IXGBE_WRITE_REG(hw, IXGBE_RXCSUM, rxcsum); 770 771 } /* ixgbe_initialize_receive_units */ 772 773 /************************************************************************ 774 * ixgbe_initialize_transmit_units - Enable transmit units. 775 ************************************************************************/ 776 static void 777 ixgbe_initialize_transmit_units(if_ctx_t ctx) 778 { 779 struct ixgbe_softc *sc = iflib_get_softc(ctx); 780 struct ixgbe_hw *hw = &sc->hw; 781 if_softc_ctx_t scctx = sc->shared; 782 struct ix_tx_queue *que; 783 int i; 784 785 /* Setup the Base and Length of the Tx Descriptor Ring */ 786 for (i = 0, que = sc->tx_queues; i < sc->num_tx_queues; 787 i++, que++) { 788 struct tx_ring *txr = &que->txr; 789 u64 tdba = txr->tx_paddr; 790 u32 txctrl = 0; 791 int j = txr->me; 792 793 IXGBE_WRITE_REG(hw, IXGBE_TDBAL(j), 794 (tdba & 0x00000000ffffffffULL)); 795 IXGBE_WRITE_REG(hw, IXGBE_TDBAH(j), (tdba >> 32)); 796 IXGBE_WRITE_REG(hw, IXGBE_TDLEN(j), 797 scctx->isc_ntxd[0] * sizeof(union ixgbe_adv_tx_desc)); 798 799 /* Setup the HW Tx Head and Tail descriptor pointers */ 800 IXGBE_WRITE_REG(hw, IXGBE_TDH(j), 0); 801 IXGBE_WRITE_REG(hw, IXGBE_TDT(j), 0); 802 803 /* Cache the tail address */ 804 txr->tail = IXGBE_TDT(txr->me); 805 806 txr->tx_rs_cidx = txr->tx_rs_pidx; 807 txr->tx_cidx_processed = scctx->isc_ntxd[0] - 1; 808 for (int k = 0; k < scctx->isc_ntxd[0]; k++) 809 txr->tx_rsq[k] = QIDX_INVALID; 810 811 /* Disable Head Writeback */ 812 /* 813 * Note: for X550 series devices, these registers are actually 814 * prefixed with TPH_ isntead of DCA_, but the addresses and 815 * fields remain the same. 816 */ 817 switch (hw->mac.type) { 818 case ixgbe_mac_82598EB: 819 txctrl = IXGBE_READ_REG(hw, IXGBE_DCA_TXCTRL(j)); 820 break; 821 default: 822 txctrl = IXGBE_READ_REG(hw, IXGBE_DCA_TXCTRL_82599(j)); 823 break; 824 } 825 txctrl &= ~IXGBE_DCA_TXCTRL_DESC_WRO_EN; 826 switch (hw->mac.type) { 827 case ixgbe_mac_82598EB: 828 IXGBE_WRITE_REG(hw, IXGBE_DCA_TXCTRL(j), txctrl); 829 break; 830 default: 831 IXGBE_WRITE_REG(hw, IXGBE_DCA_TXCTRL_82599(j), txctrl); 832 break; 833 } 834 835 } 836 837 if (hw->mac.type != ixgbe_mac_82598EB) { 838 u32 dmatxctl, rttdcs; 839 840 dmatxctl = IXGBE_READ_REG(hw, IXGBE_DMATXCTL); 841 dmatxctl |= IXGBE_DMATXCTL_TE; 842 IXGBE_WRITE_REG(hw, IXGBE_DMATXCTL, dmatxctl); 843 /* Disable arbiter to set MTQC */ 844 rttdcs = IXGBE_READ_REG(hw, IXGBE_RTTDCS); 845 rttdcs |= IXGBE_RTTDCS_ARBDIS; 846 IXGBE_WRITE_REG(hw, IXGBE_RTTDCS, rttdcs); 847 IXGBE_WRITE_REG(hw, IXGBE_MTQC, 848 ixgbe_get_mtqc(sc->iov_mode)); 849 rttdcs &= ~IXGBE_RTTDCS_ARBDIS; 850 IXGBE_WRITE_REG(hw, IXGBE_RTTDCS, rttdcs); 851 } 852 853 } /* ixgbe_initialize_transmit_units */ 854 855 /************************************************************************ 856 * ixgbe_register 857 ************************************************************************/ 858 static void * 859 ixgbe_register(device_t dev) 860 { 861 return (&ixgbe_sctx_init); 862 } /* ixgbe_register */ 863 864 /************************************************************************ 865 * ixgbe_if_attach_pre - Device initialization routine, part 1 866 * 867 * Called when the driver is being loaded. 868 * Identifies the type of hardware, initializes the hardware, 869 * and initializes iflib structures. 870 * 871 * return 0 on success, positive on failure 872 ************************************************************************/ 873 static int 874 ixgbe_if_attach_pre(if_ctx_t ctx) 875 { 876 struct ixgbe_softc *sc; 877 device_t dev; 878 if_softc_ctx_t scctx; 879 struct ixgbe_hw *hw; 880 int error = 0; 881 u32 ctrl_ext; 882 883 INIT_DEBUGOUT("ixgbe_attach: begin"); 884 885 /* Allocate, clear, and link in our adapter structure */ 886 dev = iflib_get_dev(ctx); 887 sc = iflib_get_softc(ctx); 888 sc->hw.back = sc; 889 sc->ctx = ctx; 890 sc->dev = dev; 891 scctx = sc->shared = iflib_get_softc_ctx(ctx); 892 sc->media = iflib_get_media(ctx); 893 hw = &sc->hw; 894 895 /* Determine hardware revision */ 896 hw->vendor_id = pci_get_vendor(dev); 897 hw->device_id = pci_get_device(dev); 898 hw->revision_id = pci_get_revid(dev); 899 hw->subsystem_vendor_id = pci_get_subvendor(dev); 900 hw->subsystem_device_id = pci_get_subdevice(dev); 901 902 /* Do base PCI setup - map BAR0 */ 903 if (ixgbe_allocate_pci_resources(ctx)) { 904 device_printf(dev, "Allocation of PCI resources failed\n"); 905 return (ENXIO); 906 } 907 908 /* let hardware know driver is loaded */ 909 ctrl_ext = IXGBE_READ_REG(hw, IXGBE_CTRL_EXT); 910 ctrl_ext |= IXGBE_CTRL_EXT_DRV_LOAD; 911 IXGBE_WRITE_REG(hw, IXGBE_CTRL_EXT, ctrl_ext); 912 913 /* 914 * Initialize the shared code 915 */ 916 if (ixgbe_init_shared_code(hw) != 0) { 917 device_printf(dev, "Unable to initialize the shared code\n"); 918 error = ENXIO; 919 goto err_pci; 920 } 921 922 if (hw->mac.ops.fw_recovery_mode && hw->mac.ops.fw_recovery_mode(hw)) { 923 device_printf(dev, "Firmware recovery mode detected. Limiting " 924 "functionality.\nRefer to the Intel(R) Ethernet Adapters " 925 "and Devices User Guide for details on firmware recovery " 926 "mode."); 927 error = ENOSYS; 928 goto err_pci; 929 } 930 931 if (hw->mbx.ops.init_params) 932 hw->mbx.ops.init_params(hw); 933 934 hw->allow_unsupported_sfp = allow_unsupported_sfp; 935 936 if (hw->mac.type != ixgbe_mac_82598EB) 937 hw->phy.smart_speed = ixgbe_smart_speed; 938 939 ixgbe_init_device_features(sc); 940 941 /* Enable WoL (if supported) */ 942 ixgbe_check_wol_support(sc); 943 944 /* Verify adapter fan is still functional (if applicable) */ 945 if (sc->feat_en & IXGBE_FEATURE_FAN_FAIL) { 946 u32 esdp = IXGBE_READ_REG(hw, IXGBE_ESDP); 947 ixgbe_check_fan_failure(sc, esdp, false); 948 } 949 950 /* Ensure SW/FW semaphore is free */ 951 ixgbe_init_swfw_semaphore(hw); 952 953 /* Set an initial default flow control value */ 954 hw->fc.requested_mode = ixgbe_flow_control; 955 956 hw->phy.reset_if_overtemp = true; 957 error = ixgbe_reset_hw(hw); 958 hw->phy.reset_if_overtemp = false; 959 if (error == IXGBE_ERR_SFP_NOT_PRESENT) { 960 /* 961 * No optics in this port, set up 962 * so the timer routine will probe 963 * for later insertion. 964 */ 965 sc->sfp_probe = true; 966 error = 0; 967 } else if (error == IXGBE_ERR_SFP_NOT_SUPPORTED) { 968 device_printf(dev, "Unsupported SFP+ module detected!\n"); 969 error = EIO; 970 goto err_pci; 971 } else if (error) { 972 device_printf(dev, "Hardware initialization failed\n"); 973 error = EIO; 974 goto err_pci; 975 } 976 977 /* Make sure we have a good EEPROM before we read from it */ 978 if (ixgbe_validate_eeprom_checksum(&sc->hw, NULL) < 0) { 979 device_printf(dev, "The EEPROM Checksum Is Not Valid\n"); 980 error = EIO; 981 goto err_pci; 982 } 983 984 error = ixgbe_start_hw(hw); 985 switch (error) { 986 case IXGBE_ERR_EEPROM_VERSION: 987 device_printf(dev, "This device is a pre-production adapter/LOM. Please be aware there may be issues associated with your hardware.\nIf you are experiencing problems please contact your Intel or hardware representative who provided you with this hardware.\n"); 988 break; 989 case IXGBE_ERR_SFP_NOT_SUPPORTED: 990 device_printf(dev, "Unsupported SFP+ Module\n"); 991 error = EIO; 992 goto err_pci; 993 case IXGBE_ERR_SFP_NOT_PRESENT: 994 device_printf(dev, "No SFP+ Module found\n"); 995 /* falls thru */ 996 default: 997 break; 998 } 999 1000 /* Most of the iflib initialization... */ 1001 1002 iflib_set_mac(ctx, hw->mac.addr); 1003 switch (sc->hw.mac.type) { 1004 case ixgbe_mac_X550: 1005 case ixgbe_mac_X550EM_x: 1006 case ixgbe_mac_X550EM_a: 1007 scctx->isc_rss_table_size = 512; 1008 scctx->isc_ntxqsets_max = scctx->isc_nrxqsets_max = 64; 1009 break; 1010 default: 1011 scctx->isc_rss_table_size = 128; 1012 scctx->isc_ntxqsets_max = scctx->isc_nrxqsets_max = 16; 1013 } 1014 1015 /* Allow legacy interrupts */ 1016 ixgbe_txrx.ift_legacy_intr = ixgbe_intr; 1017 1018 scctx->isc_txqsizes[0] = 1019 roundup2(scctx->isc_ntxd[0] * sizeof(union ixgbe_adv_tx_desc) + 1020 sizeof(u32), DBA_ALIGN), 1021 scctx->isc_rxqsizes[0] = 1022 roundup2(scctx->isc_nrxd[0] * sizeof(union ixgbe_adv_rx_desc), 1023 DBA_ALIGN); 1024 1025 /* XXX */ 1026 scctx->isc_tx_csum_flags = CSUM_IP | CSUM_TCP | CSUM_UDP | CSUM_TSO | 1027 CSUM_IP6_TCP | CSUM_IP6_UDP | CSUM_IP6_TSO; 1028 if (sc->hw.mac.type == ixgbe_mac_82598EB) { 1029 scctx->isc_tx_nsegments = IXGBE_82598_SCATTER; 1030 } else { 1031 scctx->isc_tx_csum_flags |= CSUM_SCTP |CSUM_IP6_SCTP; 1032 scctx->isc_tx_nsegments = IXGBE_82599_SCATTER; 1033 } 1034 1035 scctx->isc_msix_bar = pci_msix_table_bar(dev); 1036 1037 scctx->isc_tx_tso_segments_max = scctx->isc_tx_nsegments; 1038 scctx->isc_tx_tso_size_max = IXGBE_TSO_SIZE; 1039 scctx->isc_tx_tso_segsize_max = PAGE_SIZE; 1040 1041 scctx->isc_txrx = &ixgbe_txrx; 1042 1043 scctx->isc_capabilities = scctx->isc_capenable = IXGBE_CAPS; 1044 1045 return (0); 1046 1047 err_pci: 1048 ctrl_ext = IXGBE_READ_REG(&sc->hw, IXGBE_CTRL_EXT); 1049 ctrl_ext &= ~IXGBE_CTRL_EXT_DRV_LOAD; 1050 IXGBE_WRITE_REG(&sc->hw, IXGBE_CTRL_EXT, ctrl_ext); 1051 ixgbe_free_pci_resources(ctx); 1052 1053 return (error); 1054 } /* ixgbe_if_attach_pre */ 1055 1056 /********************************************************************* 1057 * ixgbe_if_attach_post - Device initialization routine, part 2 1058 * 1059 * Called during driver load, but after interrupts and 1060 * resources have been allocated and configured. 1061 * Sets up some data structures not relevant to iflib. 1062 * 1063 * return 0 on success, positive on failure 1064 *********************************************************************/ 1065 static int 1066 ixgbe_if_attach_post(if_ctx_t ctx) 1067 { 1068 device_t dev; 1069 struct ixgbe_softc *sc; 1070 struct ixgbe_hw *hw; 1071 int error = 0; 1072 1073 dev = iflib_get_dev(ctx); 1074 sc = iflib_get_softc(ctx); 1075 hw = &sc->hw; 1076 1077 1078 if (sc->intr_type == IFLIB_INTR_LEGACY && 1079 (sc->feat_cap & IXGBE_FEATURE_LEGACY_IRQ) == 0) { 1080 device_printf(dev, "Device does not support legacy interrupts"); 1081 error = ENXIO; 1082 goto err; 1083 } 1084 1085 /* Allocate multicast array memory. */ 1086 sc->mta = malloc(sizeof(*sc->mta) * 1087 MAX_NUM_MULTICAST_ADDRESSES, M_IXGBE, M_NOWAIT); 1088 if (sc->mta == NULL) { 1089 device_printf(dev, "Can not allocate multicast setup array\n"); 1090 error = ENOMEM; 1091 goto err; 1092 } 1093 1094 /* hw.ix defaults init */ 1095 ixgbe_set_advertise(sc, ixgbe_advertise_speed); 1096 1097 /* Enable the optics for 82599 SFP+ fiber */ 1098 ixgbe_enable_tx_laser(hw); 1099 1100 /* Enable power to the phy. */ 1101 ixgbe_set_phy_power(hw, true); 1102 1103 ixgbe_initialize_iov(sc); 1104 1105 error = ixgbe_setup_interface(ctx); 1106 if (error) { 1107 device_printf(dev, "Interface setup failed: %d\n", error); 1108 goto err; 1109 } 1110 1111 ixgbe_if_update_admin_status(ctx); 1112 1113 /* Initialize statistics */ 1114 ixgbe_update_stats_counters(sc); 1115 ixgbe_add_hw_stats(sc); 1116 1117 /* Check PCIE slot type/speed/width */ 1118 ixgbe_get_slot_info(sc); 1119 1120 /* 1121 * Do time init and sysctl init here, but 1122 * only on the first port of a bypass sc. 1123 */ 1124 ixgbe_bypass_init(sc); 1125 1126 /* Display NVM and Option ROM versions */ 1127 ixgbe_print_fw_version(ctx); 1128 1129 /* Set an initial dmac value */ 1130 sc->dmac = 0; 1131 /* Set initial advertised speeds (if applicable) */ 1132 sc->advertise = ixgbe_get_default_advertise(sc); 1133 1134 if (sc->feat_cap & IXGBE_FEATURE_SRIOV) 1135 ixgbe_define_iov_schemas(dev, &error); 1136 1137 /* Add sysctls */ 1138 ixgbe_add_device_sysctls(ctx); 1139 1140 return (0); 1141 err: 1142 return (error); 1143 } /* ixgbe_if_attach_post */ 1144 1145 /************************************************************************ 1146 * ixgbe_check_wol_support 1147 * 1148 * Checks whether the adapter's ports are capable of 1149 * Wake On LAN by reading the adapter's NVM. 1150 * 1151 * Sets each port's hw->wol_enabled value depending 1152 * on the value read here. 1153 ************************************************************************/ 1154 static void 1155 ixgbe_check_wol_support(struct ixgbe_softc *sc) 1156 { 1157 struct ixgbe_hw *hw = &sc->hw; 1158 u16 dev_caps = 0; 1159 1160 /* Find out WoL support for port */ 1161 sc->wol_support = hw->wol_enabled = 0; 1162 ixgbe_get_device_caps(hw, &dev_caps); 1163 if ((dev_caps & IXGBE_DEVICE_CAPS_WOL_PORT0_1) || 1164 ((dev_caps & IXGBE_DEVICE_CAPS_WOL_PORT0) && 1165 hw->bus.func == 0)) 1166 sc->wol_support = hw->wol_enabled = 1; 1167 1168 /* Save initial wake up filter configuration */ 1169 sc->wufc = IXGBE_READ_REG(hw, IXGBE_WUFC); 1170 1171 return; 1172 } /* ixgbe_check_wol_support */ 1173 1174 /************************************************************************ 1175 * ixgbe_setup_interface 1176 * 1177 * Setup networking device structure and register an interface. 1178 ************************************************************************/ 1179 static int 1180 ixgbe_setup_interface(if_ctx_t ctx) 1181 { 1182 if_t ifp = iflib_get_ifp(ctx); 1183 struct ixgbe_softc *sc = iflib_get_softc(ctx); 1184 1185 INIT_DEBUGOUT("ixgbe_setup_interface: begin"); 1186 1187 if_setbaudrate(ifp, IF_Gbps(10)); 1188 1189 sc->max_frame_size = if_getmtu(ifp) + ETHER_HDR_LEN + ETHER_CRC_LEN; 1190 1191 sc->phy_layer = ixgbe_get_supported_physical_layer(&sc->hw); 1192 1193 ixgbe_add_media_types(ctx); 1194 1195 /* Autoselect media by default */ 1196 ifmedia_set(sc->media, IFM_ETHER | IFM_AUTO); 1197 1198 return (0); 1199 } /* ixgbe_setup_interface */ 1200 1201 /************************************************************************ 1202 * ixgbe_if_get_counter 1203 ************************************************************************/ 1204 static uint64_t 1205 ixgbe_if_get_counter(if_ctx_t ctx, ift_counter cnt) 1206 { 1207 struct ixgbe_softc *sc = iflib_get_softc(ctx); 1208 if_t ifp = iflib_get_ifp(ctx); 1209 1210 switch (cnt) { 1211 case IFCOUNTER_IPACKETS: 1212 return (sc->ipackets); 1213 case IFCOUNTER_OPACKETS: 1214 return (sc->opackets); 1215 case IFCOUNTER_IBYTES: 1216 return (sc->ibytes); 1217 case IFCOUNTER_OBYTES: 1218 return (sc->obytes); 1219 case IFCOUNTER_IMCASTS: 1220 return (sc->imcasts); 1221 case IFCOUNTER_OMCASTS: 1222 return (sc->omcasts); 1223 case IFCOUNTER_COLLISIONS: 1224 return (0); 1225 case IFCOUNTER_IQDROPS: 1226 return (sc->iqdrops); 1227 case IFCOUNTER_OQDROPS: 1228 return (0); 1229 case IFCOUNTER_IERRORS: 1230 return (sc->ierrors); 1231 default: 1232 return (if_get_counter_default(ifp, cnt)); 1233 } 1234 } /* ixgbe_if_get_counter */ 1235 1236 /************************************************************************ 1237 * ixgbe_if_i2c_req 1238 ************************************************************************/ 1239 static int 1240 ixgbe_if_i2c_req(if_ctx_t ctx, struct ifi2creq *req) 1241 { 1242 struct ixgbe_softc *sc = iflib_get_softc(ctx); 1243 struct ixgbe_hw *hw = &sc->hw; 1244 int i; 1245 1246 1247 if (hw->phy.ops.read_i2c_byte == NULL) 1248 return (ENXIO); 1249 for (i = 0; i < req->len; i++) 1250 hw->phy.ops.read_i2c_byte(hw, req->offset + i, 1251 req->dev_addr, &req->data[i]); 1252 return (0); 1253 } /* ixgbe_if_i2c_req */ 1254 1255 /* ixgbe_if_needs_restart - Tell iflib when the driver needs to be reinitialized 1256 * @ctx: iflib context 1257 * @event: event code to check 1258 * 1259 * Defaults to returning true for unknown events. 1260 * 1261 * @returns true if iflib needs to reinit the interface 1262 */ 1263 static bool 1264 ixgbe_if_needs_restart(if_ctx_t ctx __unused, enum iflib_restart_event event) 1265 { 1266 switch (event) { 1267 case IFLIB_RESTART_VLAN_CONFIG: 1268 return (false); 1269 default: 1270 return (true); 1271 } 1272 } 1273 1274 /************************************************************************ 1275 * ixgbe_add_media_types 1276 ************************************************************************/ 1277 static void 1278 ixgbe_add_media_types(if_ctx_t ctx) 1279 { 1280 struct ixgbe_softc *sc = iflib_get_softc(ctx); 1281 struct ixgbe_hw *hw = &sc->hw; 1282 device_t dev = iflib_get_dev(ctx); 1283 u64 layer; 1284 1285 layer = sc->phy_layer = ixgbe_get_supported_physical_layer(hw); 1286 1287 /* Media types with matching FreeBSD media defines */ 1288 if (layer & IXGBE_PHYSICAL_LAYER_10GBASE_T) 1289 ifmedia_add(sc->media, IFM_ETHER | IFM_10G_T, 0, NULL); 1290 if (layer & IXGBE_PHYSICAL_LAYER_1000BASE_T) 1291 ifmedia_add(sc->media, IFM_ETHER | IFM_1000_T, 0, NULL); 1292 if (layer & IXGBE_PHYSICAL_LAYER_100BASE_TX) 1293 ifmedia_add(sc->media, IFM_ETHER | IFM_100_TX, 0, NULL); 1294 if (layer & IXGBE_PHYSICAL_LAYER_10BASE_T) 1295 ifmedia_add(sc->media, IFM_ETHER | IFM_10_T, 0, NULL); 1296 1297 if (hw->mac.type == ixgbe_mac_X550) { 1298 ifmedia_add(sc->media, IFM_ETHER | IFM_2500_T, 0, NULL); 1299 ifmedia_add(sc->media, IFM_ETHER | IFM_5000_T, 0, NULL); 1300 } 1301 1302 if (layer & IXGBE_PHYSICAL_LAYER_SFP_PLUS_CU || 1303 layer & IXGBE_PHYSICAL_LAYER_SFP_ACTIVE_DA) 1304 ifmedia_add(sc->media, IFM_ETHER | IFM_10G_TWINAX, 0, 1305 NULL); 1306 1307 if (layer & IXGBE_PHYSICAL_LAYER_10GBASE_LR) { 1308 ifmedia_add(sc->media, IFM_ETHER | IFM_10G_LR, 0, NULL); 1309 if (hw->phy.multispeed_fiber) 1310 ifmedia_add(sc->media, IFM_ETHER | IFM_1000_LX, 0, 1311 NULL); 1312 } 1313 if (layer & IXGBE_PHYSICAL_LAYER_10GBASE_SR) { 1314 ifmedia_add(sc->media, IFM_ETHER | IFM_10G_SR, 0, NULL); 1315 if (hw->phy.multispeed_fiber) 1316 ifmedia_add(sc->media, IFM_ETHER | IFM_1000_SX, 0, 1317 NULL); 1318 } else if (layer & IXGBE_PHYSICAL_LAYER_1000BASE_SX) 1319 ifmedia_add(sc->media, IFM_ETHER | IFM_1000_SX, 0, NULL); 1320 if (layer & IXGBE_PHYSICAL_LAYER_10GBASE_CX4) 1321 ifmedia_add(sc->media, IFM_ETHER | IFM_10G_CX4, 0, NULL); 1322 1323 #ifdef IFM_ETH_XTYPE 1324 if (layer & IXGBE_PHYSICAL_LAYER_10GBASE_KR) 1325 ifmedia_add(sc->media, IFM_ETHER | IFM_10G_KR, 0, NULL); 1326 if (layer & IXGBE_PHYSICAL_LAYER_10GBASE_KX4) 1327 ifmedia_add( sc->media, IFM_ETHER | IFM_10G_KX4, 0, NULL); 1328 if (layer & IXGBE_PHYSICAL_LAYER_1000BASE_KX) 1329 ifmedia_add(sc->media, IFM_ETHER | IFM_1000_KX, 0, NULL); 1330 if (layer & IXGBE_PHYSICAL_LAYER_2500BASE_KX) 1331 ifmedia_add(sc->media, IFM_ETHER | IFM_2500_KX, 0, NULL); 1332 #else 1333 if (layer & IXGBE_PHYSICAL_LAYER_10GBASE_KR) { 1334 device_printf(dev, "Media supported: 10GbaseKR\n"); 1335 device_printf(dev, "10GbaseKR mapped to 10GbaseSR\n"); 1336 ifmedia_add(sc->media, IFM_ETHER | IFM_10G_SR, 0, NULL); 1337 } 1338 if (layer & IXGBE_PHYSICAL_LAYER_10GBASE_KX4) { 1339 device_printf(dev, "Media supported: 10GbaseKX4\n"); 1340 device_printf(dev, "10GbaseKX4 mapped to 10GbaseCX4\n"); 1341 ifmedia_add(sc->media, IFM_ETHER | IFM_10G_CX4, 0, NULL); 1342 } 1343 if (layer & IXGBE_PHYSICAL_LAYER_1000BASE_KX) { 1344 device_printf(dev, "Media supported: 1000baseKX\n"); 1345 device_printf(dev, "1000baseKX mapped to 1000baseCX\n"); 1346 ifmedia_add(sc->media, IFM_ETHER | IFM_1000_CX, 0, NULL); 1347 } 1348 if (layer & IXGBE_PHYSICAL_LAYER_2500BASE_KX) { 1349 device_printf(dev, "Media supported: 2500baseKX\n"); 1350 device_printf(dev, "2500baseKX mapped to 2500baseSX\n"); 1351 ifmedia_add(sc->media, IFM_ETHER | IFM_2500_SX, 0, NULL); 1352 } 1353 #endif 1354 if (layer & IXGBE_PHYSICAL_LAYER_1000BASE_BX) 1355 device_printf(dev, "Media supported: 1000baseBX\n"); 1356 1357 if (hw->device_id == IXGBE_DEV_ID_82598AT) { 1358 ifmedia_add(sc->media, IFM_ETHER | IFM_1000_T | IFM_FDX, 1359 0, NULL); 1360 ifmedia_add(sc->media, IFM_ETHER | IFM_1000_T, 0, NULL); 1361 } 1362 1363 ifmedia_add(sc->media, IFM_ETHER | IFM_AUTO, 0, NULL); 1364 } /* ixgbe_add_media_types */ 1365 1366 /************************************************************************ 1367 * ixgbe_is_sfp 1368 ************************************************************************/ 1369 static inline bool 1370 ixgbe_is_sfp(struct ixgbe_hw *hw) 1371 { 1372 switch (hw->mac.type) { 1373 case ixgbe_mac_82598EB: 1374 if (hw->phy.type == ixgbe_phy_nl) 1375 return (true); 1376 return (false); 1377 case ixgbe_mac_82599EB: 1378 switch (hw->mac.ops.get_media_type(hw)) { 1379 case ixgbe_media_type_fiber: 1380 case ixgbe_media_type_fiber_qsfp: 1381 return (true); 1382 default: 1383 return (false); 1384 } 1385 case ixgbe_mac_X550EM_x: 1386 case ixgbe_mac_X550EM_a: 1387 if (hw->mac.ops.get_media_type(hw) == ixgbe_media_type_fiber) 1388 return (true); 1389 return (false); 1390 default: 1391 return (false); 1392 } 1393 } /* ixgbe_is_sfp */ 1394 1395 /************************************************************************ 1396 * ixgbe_config_link 1397 ************************************************************************/ 1398 static void 1399 ixgbe_config_link(if_ctx_t ctx) 1400 { 1401 struct ixgbe_softc *sc = iflib_get_softc(ctx); 1402 struct ixgbe_hw *hw = &sc->hw; 1403 u32 autoneg, err = 0; 1404 bool sfp, negotiate; 1405 1406 sfp = ixgbe_is_sfp(hw); 1407 1408 if (sfp) { 1409 sc->task_requests |= IXGBE_REQUEST_TASK_MOD; 1410 iflib_admin_intr_deferred(ctx); 1411 } else { 1412 if (hw->mac.ops.check_link) 1413 err = ixgbe_check_link(hw, &sc->link_speed, 1414 &sc->link_up, false); 1415 if (err) 1416 return; 1417 autoneg = hw->phy.autoneg_advertised; 1418 if ((!autoneg) && (hw->mac.ops.get_link_capabilities)) 1419 err = hw->mac.ops.get_link_capabilities(hw, &autoneg, 1420 &negotiate); 1421 if (err) 1422 return; 1423 1424 if (hw->mac.type == ixgbe_mac_X550 && 1425 hw->phy.autoneg_advertised == 0) { 1426 /* 1427 * 2.5G and 5G autonegotiation speeds on X550 1428 * are disabled by default due to reported 1429 * interoperability issues with some switches. 1430 * 1431 * The second condition checks if any operations 1432 * involving setting autonegotiation speeds have 1433 * been performed prior to this ixgbe_config_link() 1434 * call. 1435 * 1436 * If hw->phy.autoneg_advertised does not 1437 * equal 0, this means that the user might have 1438 * set autonegotiation speeds via the sysctl 1439 * before bringing the interface up. In this 1440 * case, we should not disable 2.5G and 5G 1441 * since that speeds might be selected by the 1442 * user. 1443 * 1444 * Otherwise (i.e. if hw->phy.autoneg_advertised 1445 * is set to 0), it is the first time we set 1446 * autonegotiation preferences and the default 1447 * set of speeds should exclude 2.5G and 5G. 1448 */ 1449 autoneg &= ~(IXGBE_LINK_SPEED_2_5GB_FULL | 1450 IXGBE_LINK_SPEED_5GB_FULL); 1451 } 1452 1453 if (hw->mac.ops.setup_link) 1454 err = hw->mac.ops.setup_link(hw, autoneg, 1455 sc->link_up); 1456 } 1457 } /* ixgbe_config_link */ 1458 1459 /************************************************************************ 1460 * ixgbe_update_stats_counters - Update board statistics counters. 1461 ************************************************************************/ 1462 static void 1463 ixgbe_update_stats_counters(struct ixgbe_softc *sc) 1464 { 1465 struct ixgbe_hw *hw = &sc->hw; 1466 struct ixgbe_hw_stats *stats = &sc->stats.pf; 1467 u32 missed_rx = 0, bprc, lxon, lxoff, total; 1468 u32 lxoffrxc; 1469 u64 total_missed_rx = 0; 1470 1471 stats->crcerrs += IXGBE_READ_REG(hw, IXGBE_CRCERRS); 1472 stats->illerrc += IXGBE_READ_REG(hw, IXGBE_ILLERRC); 1473 stats->errbc += IXGBE_READ_REG(hw, IXGBE_ERRBC); 1474 stats->mspdc += IXGBE_READ_REG(hw, IXGBE_MSPDC); 1475 stats->mpc[0] += IXGBE_READ_REG(hw, IXGBE_MPC(0)); 1476 1477 for (int i = 0; i < 16; i++) { 1478 stats->qprc[i] += IXGBE_READ_REG(hw, IXGBE_QPRC(i)); 1479 stats->qptc[i] += IXGBE_READ_REG(hw, IXGBE_QPTC(i)); 1480 stats->qprdc[i] += IXGBE_READ_REG(hw, IXGBE_QPRDC(i)); 1481 } 1482 stats->mlfc += IXGBE_READ_REG(hw, IXGBE_MLFC); 1483 stats->mrfc += IXGBE_READ_REG(hw, IXGBE_MRFC); 1484 stats->rlec += IXGBE_READ_REG(hw, IXGBE_RLEC); 1485 1486 /* Hardware workaround, gprc counts missed packets */ 1487 stats->gprc += IXGBE_READ_REG(hw, IXGBE_GPRC); 1488 stats->gprc -= missed_rx; 1489 1490 if (hw->mac.type != ixgbe_mac_82598EB) { 1491 stats->gorc += IXGBE_READ_REG(hw, IXGBE_GORCL) + 1492 ((u64)IXGBE_READ_REG(hw, IXGBE_GORCH) << 32); 1493 stats->gotc += IXGBE_READ_REG(hw, IXGBE_GOTCL) + 1494 ((u64)IXGBE_READ_REG(hw, IXGBE_GOTCH) << 32); 1495 stats->tor += IXGBE_READ_REG(hw, IXGBE_TORL) + 1496 ((u64)IXGBE_READ_REG(hw, IXGBE_TORH) << 32); 1497 stats->lxonrxc += IXGBE_READ_REG(hw, IXGBE_LXONRXCNT); 1498 lxoffrxc = IXGBE_READ_REG(hw, IXGBE_LXOFFRXCNT); 1499 stats->lxoffrxc += lxoffrxc; 1500 } else { 1501 stats->lxonrxc += IXGBE_READ_REG(hw, IXGBE_LXONRXC); 1502 lxoffrxc = IXGBE_READ_REG(hw, IXGBE_LXOFFRXC); 1503 stats->lxoffrxc += lxoffrxc; 1504 /* 82598 only has a counter in the high register */ 1505 stats->gorc += IXGBE_READ_REG(hw, IXGBE_GORCH); 1506 stats->gotc += IXGBE_READ_REG(hw, IXGBE_GOTCH); 1507 stats->tor += IXGBE_READ_REG(hw, IXGBE_TORH); 1508 } 1509 1510 /* 1511 * For watchdog management we need to know if we have been paused 1512 * during the last interval, so capture that here. 1513 */ 1514 if (lxoffrxc) 1515 sc->shared->isc_pause_frames = 1; 1516 1517 /* 1518 * Workaround: mprc hardware is incorrectly counting 1519 * broadcasts, so for now we subtract those. 1520 */ 1521 bprc = IXGBE_READ_REG(hw, IXGBE_BPRC); 1522 stats->bprc += bprc; 1523 stats->mprc += IXGBE_READ_REG(hw, IXGBE_MPRC); 1524 if (hw->mac.type == ixgbe_mac_82598EB) 1525 stats->mprc -= bprc; 1526 1527 stats->prc64 += IXGBE_READ_REG(hw, IXGBE_PRC64); 1528 stats->prc127 += IXGBE_READ_REG(hw, IXGBE_PRC127); 1529 stats->prc255 += IXGBE_READ_REG(hw, IXGBE_PRC255); 1530 stats->prc511 += IXGBE_READ_REG(hw, IXGBE_PRC511); 1531 stats->prc1023 += IXGBE_READ_REG(hw, IXGBE_PRC1023); 1532 stats->prc1522 += IXGBE_READ_REG(hw, IXGBE_PRC1522); 1533 1534 lxon = IXGBE_READ_REG(hw, IXGBE_LXONTXC); 1535 stats->lxontxc += lxon; 1536 lxoff = IXGBE_READ_REG(hw, IXGBE_LXOFFTXC); 1537 stats->lxofftxc += lxoff; 1538 total = lxon + lxoff; 1539 1540 stats->gptc += IXGBE_READ_REG(hw, IXGBE_GPTC); 1541 stats->mptc += IXGBE_READ_REG(hw, IXGBE_MPTC); 1542 stats->ptc64 += IXGBE_READ_REG(hw, IXGBE_PTC64); 1543 stats->gptc -= total; 1544 stats->mptc -= total; 1545 stats->ptc64 -= total; 1546 stats->gotc -= total * ETHER_MIN_LEN; 1547 1548 stats->ruc += IXGBE_READ_REG(hw, IXGBE_RUC); 1549 stats->rfc += IXGBE_READ_REG(hw, IXGBE_RFC); 1550 stats->roc += IXGBE_READ_REG(hw, IXGBE_ROC); 1551 stats->rjc += IXGBE_READ_REG(hw, IXGBE_RJC); 1552 stats->mngprc += IXGBE_READ_REG(hw, IXGBE_MNGPRC); 1553 stats->mngpdc += IXGBE_READ_REG(hw, IXGBE_MNGPDC); 1554 stats->mngptc += IXGBE_READ_REG(hw, IXGBE_MNGPTC); 1555 stats->tpr += IXGBE_READ_REG(hw, IXGBE_TPR); 1556 stats->tpt += IXGBE_READ_REG(hw, IXGBE_TPT); 1557 stats->ptc127 += IXGBE_READ_REG(hw, IXGBE_PTC127); 1558 stats->ptc255 += IXGBE_READ_REG(hw, IXGBE_PTC255); 1559 stats->ptc511 += IXGBE_READ_REG(hw, IXGBE_PTC511); 1560 stats->ptc1023 += IXGBE_READ_REG(hw, IXGBE_PTC1023); 1561 stats->ptc1522 += IXGBE_READ_REG(hw, IXGBE_PTC1522); 1562 stats->bptc += IXGBE_READ_REG(hw, IXGBE_BPTC); 1563 stats->xec += IXGBE_READ_REG(hw, IXGBE_XEC); 1564 stats->fccrc += IXGBE_READ_REG(hw, IXGBE_FCCRC); 1565 stats->fclast += IXGBE_READ_REG(hw, IXGBE_FCLAST); 1566 /* Only read FCOE on 82599 */ 1567 if (hw->mac.type != ixgbe_mac_82598EB) { 1568 stats->fcoerpdc += IXGBE_READ_REG(hw, IXGBE_FCOERPDC); 1569 stats->fcoeprc += IXGBE_READ_REG(hw, IXGBE_FCOEPRC); 1570 stats->fcoeptc += IXGBE_READ_REG(hw, IXGBE_FCOEPTC); 1571 stats->fcoedwrc += IXGBE_READ_REG(hw, IXGBE_FCOEDWRC); 1572 stats->fcoedwtc += IXGBE_READ_REG(hw, IXGBE_FCOEDWTC); 1573 } 1574 1575 /* Fill out the OS statistics structure */ 1576 IXGBE_SET_IPACKETS(sc, stats->gprc); 1577 IXGBE_SET_OPACKETS(sc, stats->gptc); 1578 IXGBE_SET_IBYTES(sc, stats->gorc); 1579 IXGBE_SET_OBYTES(sc, stats->gotc); 1580 IXGBE_SET_IMCASTS(sc, stats->mprc); 1581 IXGBE_SET_OMCASTS(sc, stats->mptc); 1582 IXGBE_SET_COLLISIONS(sc, 0); 1583 IXGBE_SET_IQDROPS(sc, total_missed_rx); 1584 1585 /* 1586 * Aggregate following types of errors as RX errors: 1587 * - CRC error count, 1588 * - illegal byte error count, 1589 * - missed packets count, 1590 * - length error count, 1591 * - undersized packets count, 1592 * - fragmented packets count, 1593 * - oversized packets count, 1594 * - jabber count. 1595 */ 1596 IXGBE_SET_IERRORS(sc, stats->crcerrs + stats->illerrc + 1597 stats->mpc[0] + stats->rlec + stats->ruc + stats->rfc + stats->roc + 1598 stats->rjc); 1599 } /* ixgbe_update_stats_counters */ 1600 1601 /************************************************************************ 1602 * ixgbe_add_hw_stats 1603 * 1604 * Add sysctl variables, one per statistic, to the system. 1605 ************************************************************************/ 1606 static void 1607 ixgbe_add_hw_stats(struct ixgbe_softc *sc) 1608 { 1609 device_t dev = iflib_get_dev(sc->ctx); 1610 struct ix_rx_queue *rx_que; 1611 struct ix_tx_queue *tx_que; 1612 struct sysctl_ctx_list *ctx = device_get_sysctl_ctx(dev); 1613 struct sysctl_oid *tree = device_get_sysctl_tree(dev); 1614 struct sysctl_oid_list *child = SYSCTL_CHILDREN(tree); 1615 struct ixgbe_hw_stats *stats = &sc->stats.pf; 1616 struct sysctl_oid *stat_node, *queue_node; 1617 struct sysctl_oid_list *stat_list, *queue_list; 1618 int i; 1619 1620 #define QUEUE_NAME_LEN 32 1621 char namebuf[QUEUE_NAME_LEN]; 1622 1623 /* Driver Statistics */ 1624 SYSCTL_ADD_ULONG(ctx, child, OID_AUTO, "dropped", 1625 CTLFLAG_RD, &sc->dropped_pkts, "Driver dropped packets"); 1626 SYSCTL_ADD_ULONG(ctx, child, OID_AUTO, "watchdog_events", 1627 CTLFLAG_RD, &sc->watchdog_events, "Watchdog timeouts"); 1628 SYSCTL_ADD_ULONG(ctx, child, OID_AUTO, "link_irq", 1629 CTLFLAG_RD, &sc->link_irq, "Link MSI-X IRQ Handled"); 1630 1631 for (i = 0, tx_que = sc->tx_queues; i < sc->num_tx_queues; i++, tx_que++) { 1632 struct tx_ring *txr = &tx_que->txr; 1633 snprintf(namebuf, QUEUE_NAME_LEN, "queue%d", i); 1634 queue_node = SYSCTL_ADD_NODE(ctx, child, OID_AUTO, namebuf, 1635 CTLFLAG_RD | CTLFLAG_MPSAFE, NULL, "Queue Name"); 1636 queue_list = SYSCTL_CHILDREN(queue_node); 1637 1638 SYSCTL_ADD_PROC(ctx, queue_list, OID_AUTO, "txd_head", 1639 CTLTYPE_UINT | CTLFLAG_RD | CTLFLAG_NEEDGIANT, txr, 0, 1640 ixgbe_sysctl_tdh_handler, "IU", "Transmit Descriptor Head"); 1641 SYSCTL_ADD_PROC(ctx, queue_list, OID_AUTO, "txd_tail", 1642 CTLTYPE_UINT | CTLFLAG_RD | CTLFLAG_NEEDGIANT, txr, 0, 1643 ixgbe_sysctl_tdt_handler, "IU", "Transmit Descriptor Tail"); 1644 SYSCTL_ADD_UQUAD(ctx, queue_list, OID_AUTO, "tso_tx", 1645 CTLFLAG_RD, &txr->tso_tx, "TSO"); 1646 SYSCTL_ADD_UQUAD(ctx, queue_list, OID_AUTO, "tx_packets", 1647 CTLFLAG_RD, &txr->total_packets, 1648 "Queue Packets Transmitted"); 1649 } 1650 1651 for (i = 0, rx_que = sc->rx_queues; i < sc->num_rx_queues; i++, rx_que++) { 1652 struct rx_ring *rxr = &rx_que->rxr; 1653 snprintf(namebuf, QUEUE_NAME_LEN, "queue%d", i); 1654 queue_node = SYSCTL_ADD_NODE(ctx, child, OID_AUTO, namebuf, 1655 CTLFLAG_RD | CTLFLAG_MPSAFE, NULL, "Queue Name"); 1656 queue_list = SYSCTL_CHILDREN(queue_node); 1657 1658 SYSCTL_ADD_PROC(ctx, queue_list, OID_AUTO, "interrupt_rate", 1659 CTLTYPE_UINT | CTLFLAG_RW | CTLFLAG_NEEDGIANT, 1660 &sc->rx_queues[i], 0, 1661 ixgbe_sysctl_interrupt_rate_handler, "IU", 1662 "Interrupt Rate"); 1663 SYSCTL_ADD_UQUAD(ctx, queue_list, OID_AUTO, "irqs", 1664 CTLFLAG_RD, &(sc->rx_queues[i].irqs), 1665 "irqs on this queue"); 1666 SYSCTL_ADD_PROC(ctx, queue_list, OID_AUTO, "rxd_head", 1667 CTLTYPE_UINT | CTLFLAG_RD | CTLFLAG_NEEDGIANT, rxr, 0, 1668 ixgbe_sysctl_rdh_handler, "IU", "Receive Descriptor Head"); 1669 SYSCTL_ADD_PROC(ctx, queue_list, OID_AUTO, "rxd_tail", 1670 CTLTYPE_UINT | CTLFLAG_RD | CTLFLAG_NEEDGIANT, rxr, 0, 1671 ixgbe_sysctl_rdt_handler, "IU", "Receive Descriptor Tail"); 1672 SYSCTL_ADD_UQUAD(ctx, queue_list, OID_AUTO, "rx_packets", 1673 CTLFLAG_RD, &rxr->rx_packets, "Queue Packets Received"); 1674 SYSCTL_ADD_UQUAD(ctx, queue_list, OID_AUTO, "rx_bytes", 1675 CTLFLAG_RD, &rxr->rx_bytes, "Queue Bytes Received"); 1676 SYSCTL_ADD_UQUAD(ctx, queue_list, OID_AUTO, "rx_copies", 1677 CTLFLAG_RD, &rxr->rx_copies, "Copied RX Frames"); 1678 SYSCTL_ADD_UQUAD(ctx, queue_list, OID_AUTO, "rx_discarded", 1679 CTLFLAG_RD, &rxr->rx_discarded, "Discarded RX packets"); 1680 } 1681 1682 /* MAC stats get their own sub node */ 1683 1684 stat_node = SYSCTL_ADD_NODE(ctx, child, OID_AUTO, "mac_stats", 1685 CTLFLAG_RD | CTLFLAG_MPSAFE, NULL, "MAC Statistics"); 1686 stat_list = SYSCTL_CHILDREN(stat_node); 1687 1688 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "rx_errs", 1689 CTLFLAG_RD, &sc->ierrors, IXGBE_SYSCTL_DESC_RX_ERRS); 1690 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "crc_errs", 1691 CTLFLAG_RD, &stats->crcerrs, "CRC Errors"); 1692 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "ill_errs", 1693 CTLFLAG_RD, &stats->illerrc, "Illegal Byte Errors"); 1694 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "byte_errs", 1695 CTLFLAG_RD, &stats->errbc, "Byte Errors"); 1696 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "short_discards", 1697 CTLFLAG_RD, &stats->mspdc, "MAC Short Packets Discarded"); 1698 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "local_faults", 1699 CTLFLAG_RD, &stats->mlfc, "MAC Local Faults"); 1700 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "remote_faults", 1701 CTLFLAG_RD, &stats->mrfc, "MAC Remote Faults"); 1702 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "rec_len_errs", 1703 CTLFLAG_RD, &stats->rlec, "Receive Length Errors"); 1704 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "rx_missed_packets", 1705 CTLFLAG_RD, &stats->mpc[0], "RX Missed Packet Count"); 1706 1707 /* Flow Control stats */ 1708 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "xon_txd", 1709 CTLFLAG_RD, &stats->lxontxc, "Link XON Transmitted"); 1710 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "xon_recvd", 1711 CTLFLAG_RD, &stats->lxonrxc, "Link XON Received"); 1712 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "xoff_txd", 1713 CTLFLAG_RD, &stats->lxofftxc, "Link XOFF Transmitted"); 1714 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "xoff_recvd", 1715 CTLFLAG_RD, &stats->lxoffrxc, "Link XOFF Received"); 1716 1717 /* Packet Reception Stats */ 1718 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "total_octets_rcvd", 1719 CTLFLAG_RD, &stats->tor, "Total Octets Received"); 1720 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "good_octets_rcvd", 1721 CTLFLAG_RD, &stats->gorc, "Good Octets Received"); 1722 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "total_pkts_rcvd", 1723 CTLFLAG_RD, &stats->tpr, "Total Packets Received"); 1724 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "good_pkts_rcvd", 1725 CTLFLAG_RD, &stats->gprc, "Good Packets Received"); 1726 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "mcast_pkts_rcvd", 1727 CTLFLAG_RD, &stats->mprc, "Multicast Packets Received"); 1728 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "bcast_pkts_rcvd", 1729 CTLFLAG_RD, &stats->bprc, "Broadcast Packets Received"); 1730 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "rx_frames_64", 1731 CTLFLAG_RD, &stats->prc64, "64 byte frames received "); 1732 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "rx_frames_65_127", 1733 CTLFLAG_RD, &stats->prc127, "65-127 byte frames received"); 1734 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "rx_frames_128_255", 1735 CTLFLAG_RD, &stats->prc255, "128-255 byte frames received"); 1736 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "rx_frames_256_511", 1737 CTLFLAG_RD, &stats->prc511, "256-511 byte frames received"); 1738 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "rx_frames_512_1023", 1739 CTLFLAG_RD, &stats->prc1023, "512-1023 byte frames received"); 1740 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "rx_frames_1024_1522", 1741 CTLFLAG_RD, &stats->prc1522, "1023-1522 byte frames received"); 1742 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "recv_undersized", 1743 CTLFLAG_RD, &stats->ruc, "Receive Undersized"); 1744 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "recv_fragmented", 1745 CTLFLAG_RD, &stats->rfc, "Fragmented Packets Received "); 1746 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "recv_oversized", 1747 CTLFLAG_RD, &stats->roc, "Oversized Packets Received"); 1748 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "recv_jabberd", 1749 CTLFLAG_RD, &stats->rjc, "Received Jabber"); 1750 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "management_pkts_rcvd", 1751 CTLFLAG_RD, &stats->mngprc, "Management Packets Received"); 1752 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "management_pkts_drpd", 1753 CTLFLAG_RD, &stats->mngptc, "Management Packets Dropped"); 1754 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "checksum_errs", 1755 CTLFLAG_RD, &stats->xec, "Checksum Errors"); 1756 1757 /* Packet Transmission Stats */ 1758 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "good_octets_txd", 1759 CTLFLAG_RD, &stats->gotc, "Good Octets Transmitted"); 1760 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "total_pkts_txd", 1761 CTLFLAG_RD, &stats->tpt, "Total Packets Transmitted"); 1762 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "good_pkts_txd", 1763 CTLFLAG_RD, &stats->gptc, "Good Packets Transmitted"); 1764 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "bcast_pkts_txd", 1765 CTLFLAG_RD, &stats->bptc, "Broadcast Packets Transmitted"); 1766 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "mcast_pkts_txd", 1767 CTLFLAG_RD, &stats->mptc, "Multicast Packets Transmitted"); 1768 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "management_pkts_txd", 1769 CTLFLAG_RD, &stats->mngptc, "Management Packets Transmitted"); 1770 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "tx_frames_64", 1771 CTLFLAG_RD, &stats->ptc64, "64 byte frames transmitted "); 1772 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "tx_frames_65_127", 1773 CTLFLAG_RD, &stats->ptc127, "65-127 byte frames transmitted"); 1774 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "tx_frames_128_255", 1775 CTLFLAG_RD, &stats->ptc255, "128-255 byte frames transmitted"); 1776 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "tx_frames_256_511", 1777 CTLFLAG_RD, &stats->ptc511, "256-511 byte frames transmitted"); 1778 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "tx_frames_512_1023", 1779 CTLFLAG_RD, &stats->ptc1023, "512-1023 byte frames transmitted"); 1780 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "tx_frames_1024_1522", 1781 CTLFLAG_RD, &stats->ptc1522, "1024-1522 byte frames transmitted"); 1782 } /* ixgbe_add_hw_stats */ 1783 1784 /************************************************************************ 1785 * ixgbe_sysctl_tdh_handler - Transmit Descriptor Head handler function 1786 * 1787 * Retrieves the TDH value from the hardware 1788 ************************************************************************/ 1789 static int 1790 ixgbe_sysctl_tdh_handler(SYSCTL_HANDLER_ARGS) 1791 { 1792 struct tx_ring *txr = ((struct tx_ring *)oidp->oid_arg1); 1793 int error; 1794 unsigned int val; 1795 1796 if (!txr) 1797 return (0); 1798 1799 val = IXGBE_READ_REG(&txr->sc->hw, IXGBE_TDH(txr->me)); 1800 error = sysctl_handle_int(oidp, &val, 0, req); 1801 if (error || !req->newptr) 1802 return error; 1803 1804 return (0); 1805 } /* ixgbe_sysctl_tdh_handler */ 1806 1807 /************************************************************************ 1808 * ixgbe_sysctl_tdt_handler - Transmit Descriptor Tail handler function 1809 * 1810 * Retrieves the TDT value from the hardware 1811 ************************************************************************/ 1812 static int 1813 ixgbe_sysctl_tdt_handler(SYSCTL_HANDLER_ARGS) 1814 { 1815 struct tx_ring *txr = ((struct tx_ring *)oidp->oid_arg1); 1816 int error; 1817 unsigned int val; 1818 1819 if (!txr) 1820 return (0); 1821 1822 val = IXGBE_READ_REG(&txr->sc->hw, IXGBE_TDT(txr->me)); 1823 error = sysctl_handle_int(oidp, &val, 0, req); 1824 if (error || !req->newptr) 1825 return error; 1826 1827 return (0); 1828 } /* ixgbe_sysctl_tdt_handler */ 1829 1830 /************************************************************************ 1831 * ixgbe_sysctl_rdh_handler - Receive Descriptor Head handler function 1832 * 1833 * Retrieves the RDH value from the hardware 1834 ************************************************************************/ 1835 static int 1836 ixgbe_sysctl_rdh_handler(SYSCTL_HANDLER_ARGS) 1837 { 1838 struct rx_ring *rxr = ((struct rx_ring *)oidp->oid_arg1); 1839 int error; 1840 unsigned int val; 1841 1842 if (!rxr) 1843 return (0); 1844 1845 val = IXGBE_READ_REG(&rxr->sc->hw, IXGBE_RDH(rxr->me)); 1846 error = sysctl_handle_int(oidp, &val, 0, req); 1847 if (error || !req->newptr) 1848 return error; 1849 1850 return (0); 1851 } /* ixgbe_sysctl_rdh_handler */ 1852 1853 /************************************************************************ 1854 * ixgbe_sysctl_rdt_handler - Receive Descriptor Tail handler function 1855 * 1856 * Retrieves the RDT value from the hardware 1857 ************************************************************************/ 1858 static int 1859 ixgbe_sysctl_rdt_handler(SYSCTL_HANDLER_ARGS) 1860 { 1861 struct rx_ring *rxr = ((struct rx_ring *)oidp->oid_arg1); 1862 int error; 1863 unsigned int val; 1864 1865 if (!rxr) 1866 return (0); 1867 1868 val = IXGBE_READ_REG(&rxr->sc->hw, IXGBE_RDT(rxr->me)); 1869 error = sysctl_handle_int(oidp, &val, 0, req); 1870 if (error || !req->newptr) 1871 return error; 1872 1873 return (0); 1874 } /* ixgbe_sysctl_rdt_handler */ 1875 1876 /************************************************************************ 1877 * ixgbe_if_vlan_register 1878 * 1879 * Run via vlan config EVENT, it enables us to use the 1880 * HW Filter table since we can get the vlan id. This 1881 * just creates the entry in the soft version of the 1882 * VFTA, init will repopulate the real table. 1883 ************************************************************************/ 1884 static void 1885 ixgbe_if_vlan_register(if_ctx_t ctx, u16 vtag) 1886 { 1887 struct ixgbe_softc *sc = iflib_get_softc(ctx); 1888 u16 index, bit; 1889 1890 index = (vtag >> 5) & 0x7F; 1891 bit = vtag & 0x1F; 1892 sc->shadow_vfta[index] |= (1 << bit); 1893 ++sc->num_vlans; 1894 ixgbe_setup_vlan_hw_support(ctx); 1895 } /* ixgbe_if_vlan_register */ 1896 1897 /************************************************************************ 1898 * ixgbe_if_vlan_unregister 1899 * 1900 * Run via vlan unconfig EVENT, remove our entry in the soft vfta. 1901 ************************************************************************/ 1902 static void 1903 ixgbe_if_vlan_unregister(if_ctx_t ctx, u16 vtag) 1904 { 1905 struct ixgbe_softc *sc = iflib_get_softc(ctx); 1906 u16 index, bit; 1907 1908 index = (vtag >> 5) & 0x7F; 1909 bit = vtag & 0x1F; 1910 sc->shadow_vfta[index] &= ~(1 << bit); 1911 --sc->num_vlans; 1912 /* Re-init to load the changes */ 1913 ixgbe_setup_vlan_hw_support(ctx); 1914 } /* ixgbe_if_vlan_unregister */ 1915 1916 /************************************************************************ 1917 * ixgbe_setup_vlan_hw_support 1918 ************************************************************************/ 1919 static void 1920 ixgbe_setup_vlan_hw_support(if_ctx_t ctx) 1921 { 1922 if_t ifp = iflib_get_ifp(ctx); 1923 struct ixgbe_softc *sc = iflib_get_softc(ctx); 1924 struct ixgbe_hw *hw = &sc->hw; 1925 struct rx_ring *rxr; 1926 int i; 1927 u32 ctrl; 1928 1929 1930 /* 1931 * We get here thru init_locked, meaning 1932 * a soft reset, this has already cleared 1933 * the VFTA and other state, so if there 1934 * have been no vlan's registered do nothing. 1935 */ 1936 if (sc->num_vlans == 0 || (if_getcapenable(ifp) & IFCAP_VLAN_HWTAGGING) == 0) { 1937 /* Clear the vlan hw flag */ 1938 for (i = 0; i < sc->num_rx_queues; i++) { 1939 rxr = &sc->rx_queues[i].rxr; 1940 /* On 82599 the VLAN enable is per/queue in RXDCTL */ 1941 if (hw->mac.type != ixgbe_mac_82598EB) { 1942 ctrl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(rxr->me)); 1943 ctrl &= ~IXGBE_RXDCTL_VME; 1944 IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(rxr->me), ctrl); 1945 } 1946 rxr->vtag_strip = false; 1947 } 1948 ctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL); 1949 /* Enable the Filter Table if enabled */ 1950 ctrl |= IXGBE_VLNCTRL_CFIEN; 1951 ctrl &= ~IXGBE_VLNCTRL_VFE; 1952 if (hw->mac.type == ixgbe_mac_82598EB) 1953 ctrl &= ~IXGBE_VLNCTRL_VME; 1954 IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, ctrl); 1955 return; 1956 } 1957 1958 /* Setup the queues for vlans */ 1959 if (if_getcapenable(ifp) & IFCAP_VLAN_HWTAGGING) { 1960 for (i = 0; i < sc->num_rx_queues; i++) { 1961 rxr = &sc->rx_queues[i].rxr; 1962 /* On 82599 the VLAN enable is per/queue in RXDCTL */ 1963 if (hw->mac.type != ixgbe_mac_82598EB) { 1964 ctrl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(rxr->me)); 1965 ctrl |= IXGBE_RXDCTL_VME; 1966 IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(rxr->me), ctrl); 1967 } 1968 rxr->vtag_strip = true; 1969 } 1970 } 1971 1972 if ((if_getcapenable(ifp) & IFCAP_VLAN_HWFILTER) == 0) 1973 return; 1974 /* 1975 * A soft reset zero's out the VFTA, so 1976 * we need to repopulate it now. 1977 */ 1978 for (i = 0; i < IXGBE_VFTA_SIZE; i++) 1979 if (sc->shadow_vfta[i] != 0) 1980 IXGBE_WRITE_REG(hw, IXGBE_VFTA(i), 1981 sc->shadow_vfta[i]); 1982 1983 ctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL); 1984 /* Enable the Filter Table if enabled */ 1985 if (if_getcapenable(ifp) & IFCAP_VLAN_HWFILTER) { 1986 ctrl &= ~IXGBE_VLNCTRL_CFIEN; 1987 ctrl |= IXGBE_VLNCTRL_VFE; 1988 } 1989 if (hw->mac.type == ixgbe_mac_82598EB) 1990 ctrl |= IXGBE_VLNCTRL_VME; 1991 IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, ctrl); 1992 } /* ixgbe_setup_vlan_hw_support */ 1993 1994 /************************************************************************ 1995 * ixgbe_get_slot_info 1996 * 1997 * Get the width and transaction speed of 1998 * the slot this adapter is plugged into. 1999 ************************************************************************/ 2000 static void 2001 ixgbe_get_slot_info(struct ixgbe_softc *sc) 2002 { 2003 device_t dev = iflib_get_dev(sc->ctx); 2004 struct ixgbe_hw *hw = &sc->hw; 2005 int bus_info_valid = true; 2006 u32 offset; 2007 u16 link; 2008 2009 /* Some devices are behind an internal bridge */ 2010 switch (hw->device_id) { 2011 case IXGBE_DEV_ID_82599_SFP_SF_QP: 2012 case IXGBE_DEV_ID_82599_QSFP_SF_QP: 2013 goto get_parent_info; 2014 default: 2015 break; 2016 } 2017 2018 ixgbe_get_bus_info(hw); 2019 2020 /* 2021 * Some devices don't use PCI-E, but there is no need 2022 * to display "Unknown" for bus speed and width. 2023 */ 2024 switch (hw->mac.type) { 2025 case ixgbe_mac_X550EM_x: 2026 case ixgbe_mac_X550EM_a: 2027 return; 2028 default: 2029 goto display; 2030 } 2031 2032 get_parent_info: 2033 /* 2034 * For the Quad port adapter we need to parse back 2035 * up the PCI tree to find the speed of the expansion 2036 * slot into which this adapter is plugged. A bit more work. 2037 */ 2038 dev = device_get_parent(device_get_parent(dev)); 2039 #ifdef IXGBE_DEBUG 2040 device_printf(dev, "parent pcib = %x,%x,%x\n", pci_get_bus(dev), 2041 pci_get_slot(dev), pci_get_function(dev)); 2042 #endif 2043 dev = device_get_parent(device_get_parent(dev)); 2044 #ifdef IXGBE_DEBUG 2045 device_printf(dev, "slot pcib = %x,%x,%x\n", pci_get_bus(dev), 2046 pci_get_slot(dev), pci_get_function(dev)); 2047 #endif 2048 /* Now get the PCI Express Capabilities offset */ 2049 if (pci_find_cap(dev, PCIY_EXPRESS, &offset)) { 2050 /* 2051 * Hmm...can't get PCI-Express capabilities. 2052 * Falling back to default method. 2053 */ 2054 bus_info_valid = false; 2055 ixgbe_get_bus_info(hw); 2056 goto display; 2057 } 2058 /* ...and read the Link Status Register */ 2059 link = pci_read_config(dev, offset + PCIER_LINK_STA, 2); 2060 ixgbe_set_pci_config_data_generic(hw, link); 2061 2062 display: 2063 device_printf(dev, "PCI Express Bus: Speed %s %s\n", 2064 ((hw->bus.speed == ixgbe_bus_speed_8000) ? "8.0GT/s" : 2065 (hw->bus.speed == ixgbe_bus_speed_5000) ? "5.0GT/s" : 2066 (hw->bus.speed == ixgbe_bus_speed_2500) ? "2.5GT/s" : 2067 "Unknown"), 2068 ((hw->bus.width == ixgbe_bus_width_pcie_x8) ? "Width x8" : 2069 (hw->bus.width == ixgbe_bus_width_pcie_x4) ? "Width x4" : 2070 (hw->bus.width == ixgbe_bus_width_pcie_x1) ? "Width x1" : 2071 "Unknown")); 2072 2073 if (bus_info_valid) { 2074 if ((hw->device_id != IXGBE_DEV_ID_82599_SFP_SF_QP) && 2075 ((hw->bus.width <= ixgbe_bus_width_pcie_x4) && 2076 (hw->bus.speed == ixgbe_bus_speed_2500))) { 2077 device_printf(dev, "PCI-Express bandwidth available for this card\n is not sufficient for optimal performance.\n"); 2078 device_printf(dev, "For optimal performance a x8 PCIE, or x4 PCIE Gen2 slot is required.\n"); 2079 } 2080 if ((hw->device_id == IXGBE_DEV_ID_82599_SFP_SF_QP) && 2081 ((hw->bus.width <= ixgbe_bus_width_pcie_x8) && 2082 (hw->bus.speed < ixgbe_bus_speed_8000))) { 2083 device_printf(dev, "PCI-Express bandwidth available for this card\n is not sufficient for optimal performance.\n"); 2084 device_printf(dev, "For optimal performance a x8 PCIE Gen3 slot is required.\n"); 2085 } 2086 } else 2087 device_printf(dev, "Unable to determine slot speed/width. The speed/width reported are that of the internal switch.\n"); 2088 2089 return; 2090 } /* ixgbe_get_slot_info */ 2091 2092 /************************************************************************ 2093 * ixgbe_if_msix_intr_assign 2094 * 2095 * Setup MSI-X Interrupt resources and handlers 2096 ************************************************************************/ 2097 static int 2098 ixgbe_if_msix_intr_assign(if_ctx_t ctx, int msix) 2099 { 2100 struct ixgbe_softc *sc = iflib_get_softc(ctx); 2101 struct ix_rx_queue *rx_que = sc->rx_queues; 2102 struct ix_tx_queue *tx_que; 2103 int error, rid, vector = 0; 2104 char buf[16]; 2105 2106 /* Admin Que is vector 0*/ 2107 rid = vector + 1; 2108 for (int i = 0; i < sc->num_rx_queues; i++, vector++, rx_que++) { 2109 rid = vector + 1; 2110 2111 snprintf(buf, sizeof(buf), "rxq%d", i); 2112 error = iflib_irq_alloc_generic(ctx, &rx_que->que_irq, rid, 2113 IFLIB_INTR_RXTX, ixgbe_msix_que, rx_que, rx_que->rxr.me, buf); 2114 2115 if (error) { 2116 device_printf(iflib_get_dev(ctx), 2117 "Failed to allocate que int %d err: %d", i, error); 2118 sc->num_rx_queues = i + 1; 2119 goto fail; 2120 } 2121 2122 rx_que->msix = vector; 2123 } 2124 for (int i = 0; i < sc->num_tx_queues; i++) { 2125 snprintf(buf, sizeof(buf), "txq%d", i); 2126 tx_que = &sc->tx_queues[i]; 2127 tx_que->msix = i % sc->num_rx_queues; 2128 iflib_softirq_alloc_generic(ctx, 2129 &sc->rx_queues[tx_que->msix].que_irq, 2130 IFLIB_INTR_TX, tx_que, tx_que->txr.me, buf); 2131 } 2132 rid = vector + 1; 2133 error = iflib_irq_alloc_generic(ctx, &sc->irq, rid, 2134 IFLIB_INTR_ADMIN, ixgbe_msix_link, sc, 0, "aq"); 2135 if (error) { 2136 device_printf(iflib_get_dev(ctx), 2137 "Failed to register admin handler"); 2138 return (error); 2139 } 2140 2141 sc->vector = vector; 2142 2143 return (0); 2144 fail: 2145 iflib_irq_free(ctx, &sc->irq); 2146 rx_que = sc->rx_queues; 2147 for (int i = 0; i < sc->num_rx_queues; i++, rx_que++) 2148 iflib_irq_free(ctx, &rx_que->que_irq); 2149 2150 return (error); 2151 } /* ixgbe_if_msix_intr_assign */ 2152 2153 static inline void 2154 ixgbe_perform_aim(struct ixgbe_softc *sc, struct ix_rx_queue *que) 2155 { 2156 uint32_t newitr = 0; 2157 struct rx_ring *rxr = &que->rxr; 2158 2159 /* 2160 * Do Adaptive Interrupt Moderation: 2161 * - Write out last calculated setting 2162 * - Calculate based on average size over 2163 * the last interval. 2164 */ 2165 if (que->eitr_setting) { 2166 IXGBE_WRITE_REG(&sc->hw, IXGBE_EITR(que->msix), 2167 que->eitr_setting); 2168 } 2169 2170 que->eitr_setting = 0; 2171 /* Idle, do nothing */ 2172 if (rxr->bytes == 0) { 2173 return; 2174 } 2175 2176 if ((rxr->bytes) && (rxr->packets)) { 2177 newitr = (rxr->bytes / rxr->packets); 2178 } 2179 2180 newitr += 24; /* account for hardware frame, crc */ 2181 /* set an upper boundary */ 2182 newitr = min(newitr, 3000); 2183 2184 /* Be nice to the mid range */ 2185 if ((newitr > 300) && (newitr < 1200)) { 2186 newitr = (newitr / 3); 2187 } else { 2188 newitr = (newitr / 2); 2189 } 2190 2191 if (sc->hw.mac.type == ixgbe_mac_82598EB) { 2192 newitr |= newitr << 16; 2193 } else { 2194 newitr |= IXGBE_EITR_CNT_WDIS; 2195 } 2196 2197 /* save for next interrupt */ 2198 que->eitr_setting = newitr; 2199 2200 /* Reset state */ 2201 rxr->bytes = 0; 2202 rxr->packets = 0; 2203 2204 return; 2205 } 2206 2207 /********************************************************************* 2208 * ixgbe_msix_que - MSI-X Queue Interrupt Service routine 2209 **********************************************************************/ 2210 static int 2211 ixgbe_msix_que(void *arg) 2212 { 2213 struct ix_rx_queue *que = arg; 2214 struct ixgbe_softc *sc = que->sc; 2215 if_t ifp = iflib_get_ifp(que->sc->ctx); 2216 2217 /* Protect against spurious interrupts */ 2218 if ((if_getdrvflags(ifp) & IFF_DRV_RUNNING) == 0) 2219 return (FILTER_HANDLED); 2220 2221 ixgbe_disable_queue(sc, que->msix); 2222 ++que->irqs; 2223 2224 /* Check for AIM */ 2225 if (sc->enable_aim) { 2226 ixgbe_perform_aim(sc, que); 2227 } 2228 2229 return (FILTER_SCHEDULE_THREAD); 2230 } /* ixgbe_msix_que */ 2231 2232 /************************************************************************ 2233 * ixgbe_media_status - Media Ioctl callback 2234 * 2235 * Called whenever the user queries the status of 2236 * the interface using ifconfig. 2237 ************************************************************************/ 2238 static void 2239 ixgbe_if_media_status(if_ctx_t ctx, struct ifmediareq * ifmr) 2240 { 2241 struct ixgbe_softc *sc = iflib_get_softc(ctx); 2242 struct ixgbe_hw *hw = &sc->hw; 2243 int layer; 2244 2245 INIT_DEBUGOUT("ixgbe_if_media_status: begin"); 2246 2247 ifmr->ifm_status = IFM_AVALID; 2248 ifmr->ifm_active = IFM_ETHER; 2249 2250 if (!sc->link_active) 2251 return; 2252 2253 ifmr->ifm_status |= IFM_ACTIVE; 2254 layer = sc->phy_layer; 2255 2256 if (layer & IXGBE_PHYSICAL_LAYER_10GBASE_T || 2257 layer & IXGBE_PHYSICAL_LAYER_1000BASE_T || 2258 layer & IXGBE_PHYSICAL_LAYER_100BASE_TX || 2259 layer & IXGBE_PHYSICAL_LAYER_10BASE_T) 2260 switch (sc->link_speed) { 2261 case IXGBE_LINK_SPEED_10GB_FULL: 2262 ifmr->ifm_active |= IFM_10G_T | IFM_FDX; 2263 break; 2264 case IXGBE_LINK_SPEED_1GB_FULL: 2265 ifmr->ifm_active |= IFM_1000_T | IFM_FDX; 2266 break; 2267 case IXGBE_LINK_SPEED_100_FULL: 2268 ifmr->ifm_active |= IFM_100_TX | IFM_FDX; 2269 break; 2270 case IXGBE_LINK_SPEED_10_FULL: 2271 ifmr->ifm_active |= IFM_10_T | IFM_FDX; 2272 break; 2273 } 2274 if (hw->mac.type == ixgbe_mac_X550) 2275 switch (sc->link_speed) { 2276 case IXGBE_LINK_SPEED_5GB_FULL: 2277 ifmr->ifm_active |= IFM_5000_T | IFM_FDX; 2278 break; 2279 case IXGBE_LINK_SPEED_2_5GB_FULL: 2280 ifmr->ifm_active |= IFM_2500_T | IFM_FDX; 2281 break; 2282 } 2283 if (layer & IXGBE_PHYSICAL_LAYER_SFP_PLUS_CU || 2284 layer & IXGBE_PHYSICAL_LAYER_SFP_ACTIVE_DA) 2285 switch (sc->link_speed) { 2286 case IXGBE_LINK_SPEED_10GB_FULL: 2287 ifmr->ifm_active |= IFM_10G_TWINAX | IFM_FDX; 2288 break; 2289 } 2290 if (layer & IXGBE_PHYSICAL_LAYER_10GBASE_LR) 2291 switch (sc->link_speed) { 2292 case IXGBE_LINK_SPEED_10GB_FULL: 2293 ifmr->ifm_active |= IFM_10G_LR | IFM_FDX; 2294 break; 2295 case IXGBE_LINK_SPEED_1GB_FULL: 2296 ifmr->ifm_active |= IFM_1000_LX | IFM_FDX; 2297 break; 2298 } 2299 if (layer & IXGBE_PHYSICAL_LAYER_10GBASE_LRM) 2300 switch (sc->link_speed) { 2301 case IXGBE_LINK_SPEED_10GB_FULL: 2302 ifmr->ifm_active |= IFM_10G_LRM | IFM_FDX; 2303 break; 2304 case IXGBE_LINK_SPEED_1GB_FULL: 2305 ifmr->ifm_active |= IFM_1000_LX | IFM_FDX; 2306 break; 2307 } 2308 if (layer & IXGBE_PHYSICAL_LAYER_10GBASE_SR || 2309 layer & IXGBE_PHYSICAL_LAYER_1000BASE_SX) 2310 switch (sc->link_speed) { 2311 case IXGBE_LINK_SPEED_10GB_FULL: 2312 ifmr->ifm_active |= IFM_10G_SR | IFM_FDX; 2313 break; 2314 case IXGBE_LINK_SPEED_1GB_FULL: 2315 ifmr->ifm_active |= IFM_1000_SX | IFM_FDX; 2316 break; 2317 } 2318 if (layer & IXGBE_PHYSICAL_LAYER_10GBASE_CX4) 2319 switch (sc->link_speed) { 2320 case IXGBE_LINK_SPEED_10GB_FULL: 2321 ifmr->ifm_active |= IFM_10G_CX4 | IFM_FDX; 2322 break; 2323 } 2324 /* 2325 * XXX: These need to use the proper media types once 2326 * they're added. 2327 */ 2328 #ifndef IFM_ETH_XTYPE 2329 if (layer & IXGBE_PHYSICAL_LAYER_10GBASE_KR) 2330 switch (sc->link_speed) { 2331 case IXGBE_LINK_SPEED_10GB_FULL: 2332 ifmr->ifm_active |= IFM_10G_SR | IFM_FDX; 2333 break; 2334 case IXGBE_LINK_SPEED_2_5GB_FULL: 2335 ifmr->ifm_active |= IFM_2500_SX | IFM_FDX; 2336 break; 2337 case IXGBE_LINK_SPEED_1GB_FULL: 2338 ifmr->ifm_active |= IFM_1000_CX | IFM_FDX; 2339 break; 2340 } 2341 else if (layer & IXGBE_PHYSICAL_LAYER_10GBASE_KX4 || 2342 layer & IXGBE_PHYSICAL_LAYER_2500BASE_KX || 2343 layer & IXGBE_PHYSICAL_LAYER_1000BASE_KX) 2344 switch (sc->link_speed) { 2345 case IXGBE_LINK_SPEED_10GB_FULL: 2346 ifmr->ifm_active |= IFM_10G_CX4 | IFM_FDX; 2347 break; 2348 case IXGBE_LINK_SPEED_2_5GB_FULL: 2349 ifmr->ifm_active |= IFM_2500_SX | IFM_FDX; 2350 break; 2351 case IXGBE_LINK_SPEED_1GB_FULL: 2352 ifmr->ifm_active |= IFM_1000_CX | IFM_FDX; 2353 break; 2354 } 2355 #else 2356 if (layer & IXGBE_PHYSICAL_LAYER_10GBASE_KR) 2357 switch (sc->link_speed) { 2358 case IXGBE_LINK_SPEED_10GB_FULL: 2359 ifmr->ifm_active |= IFM_10G_KR | IFM_FDX; 2360 break; 2361 case IXGBE_LINK_SPEED_2_5GB_FULL: 2362 ifmr->ifm_active |= IFM_2500_KX | IFM_FDX; 2363 break; 2364 case IXGBE_LINK_SPEED_1GB_FULL: 2365 ifmr->ifm_active |= IFM_1000_KX | IFM_FDX; 2366 break; 2367 } 2368 else if (layer & IXGBE_PHYSICAL_LAYER_10GBASE_KX4 || 2369 layer & IXGBE_PHYSICAL_LAYER_2500BASE_KX || 2370 layer & IXGBE_PHYSICAL_LAYER_1000BASE_KX) 2371 switch (sc->link_speed) { 2372 case IXGBE_LINK_SPEED_10GB_FULL: 2373 ifmr->ifm_active |= IFM_10G_KX4 | IFM_FDX; 2374 break; 2375 case IXGBE_LINK_SPEED_2_5GB_FULL: 2376 ifmr->ifm_active |= IFM_2500_KX | IFM_FDX; 2377 break; 2378 case IXGBE_LINK_SPEED_1GB_FULL: 2379 ifmr->ifm_active |= IFM_1000_KX | IFM_FDX; 2380 break; 2381 } 2382 #endif 2383 2384 /* If nothing is recognized... */ 2385 if (IFM_SUBTYPE(ifmr->ifm_active) == 0) 2386 ifmr->ifm_active |= IFM_UNKNOWN; 2387 2388 /* Display current flow control setting used on link */ 2389 if (hw->fc.current_mode == ixgbe_fc_rx_pause || 2390 hw->fc.current_mode == ixgbe_fc_full) 2391 ifmr->ifm_active |= IFM_ETH_RXPAUSE; 2392 if (hw->fc.current_mode == ixgbe_fc_tx_pause || 2393 hw->fc.current_mode == ixgbe_fc_full) 2394 ifmr->ifm_active |= IFM_ETH_TXPAUSE; 2395 } /* ixgbe_media_status */ 2396 2397 /************************************************************************ 2398 * ixgbe_media_change - Media Ioctl callback 2399 * 2400 * Called when the user changes speed/duplex using 2401 * media/mediopt option with ifconfig. 2402 ************************************************************************/ 2403 static int 2404 ixgbe_if_media_change(if_ctx_t ctx) 2405 { 2406 struct ixgbe_softc *sc = iflib_get_softc(ctx); 2407 struct ifmedia *ifm = iflib_get_media(ctx); 2408 struct ixgbe_hw *hw = &sc->hw; 2409 ixgbe_link_speed speed = 0; 2410 2411 INIT_DEBUGOUT("ixgbe_if_media_change: begin"); 2412 2413 if (IFM_TYPE(ifm->ifm_media) != IFM_ETHER) 2414 return (EINVAL); 2415 2416 if (hw->phy.media_type == ixgbe_media_type_backplane) 2417 return (EPERM); 2418 2419 /* 2420 * We don't actually need to check against the supported 2421 * media types of the adapter; ifmedia will take care of 2422 * that for us. 2423 */ 2424 switch (IFM_SUBTYPE(ifm->ifm_media)) { 2425 case IFM_AUTO: 2426 case IFM_10G_T: 2427 speed |= IXGBE_LINK_SPEED_100_FULL; 2428 speed |= IXGBE_LINK_SPEED_1GB_FULL; 2429 speed |= IXGBE_LINK_SPEED_10GB_FULL; 2430 break; 2431 case IFM_10G_LRM: 2432 case IFM_10G_LR: 2433 #ifndef IFM_ETH_XTYPE 2434 case IFM_10G_SR: /* KR, too */ 2435 case IFM_10G_CX4: /* KX4 */ 2436 #else 2437 case IFM_10G_KR: 2438 case IFM_10G_KX4: 2439 #endif 2440 speed |= IXGBE_LINK_SPEED_1GB_FULL; 2441 speed |= IXGBE_LINK_SPEED_10GB_FULL; 2442 break; 2443 #ifndef IFM_ETH_XTYPE 2444 case IFM_1000_CX: /* KX */ 2445 #else 2446 case IFM_1000_KX: 2447 #endif 2448 case IFM_1000_LX: 2449 case IFM_1000_SX: 2450 speed |= IXGBE_LINK_SPEED_1GB_FULL; 2451 break; 2452 case IFM_1000_T: 2453 speed |= IXGBE_LINK_SPEED_100_FULL; 2454 speed |= IXGBE_LINK_SPEED_1GB_FULL; 2455 break; 2456 case IFM_10G_TWINAX: 2457 speed |= IXGBE_LINK_SPEED_10GB_FULL; 2458 break; 2459 case IFM_5000_T: 2460 speed |= IXGBE_LINK_SPEED_5GB_FULL; 2461 break; 2462 case IFM_2500_T: 2463 speed |= IXGBE_LINK_SPEED_2_5GB_FULL; 2464 break; 2465 case IFM_100_TX: 2466 speed |= IXGBE_LINK_SPEED_100_FULL; 2467 break; 2468 case IFM_10_T: 2469 speed |= IXGBE_LINK_SPEED_10_FULL; 2470 break; 2471 default: 2472 goto invalid; 2473 } 2474 2475 hw->mac.autotry_restart = true; 2476 hw->mac.ops.setup_link(hw, speed, true); 2477 sc->advertise = 2478 ((speed & IXGBE_LINK_SPEED_10GB_FULL) ? 0x4 : 0) | 2479 ((speed & IXGBE_LINK_SPEED_5GB_FULL) ? 0x20 : 0) | 2480 ((speed & IXGBE_LINK_SPEED_2_5GB_FULL) ? 0x10 : 0) | 2481 ((speed & IXGBE_LINK_SPEED_1GB_FULL) ? 0x2 : 0) | 2482 ((speed & IXGBE_LINK_SPEED_100_FULL) ? 0x1 : 0) | 2483 ((speed & IXGBE_LINK_SPEED_10_FULL) ? 0x8 : 0); 2484 2485 return (0); 2486 2487 invalid: 2488 device_printf(iflib_get_dev(ctx), "Invalid media type!\n"); 2489 2490 return (EINVAL); 2491 } /* ixgbe_if_media_change */ 2492 2493 /************************************************************************ 2494 * ixgbe_set_promisc 2495 ************************************************************************/ 2496 static int 2497 ixgbe_if_promisc_set(if_ctx_t ctx, int flags) 2498 { 2499 struct ixgbe_softc *sc = iflib_get_softc(ctx); 2500 if_t ifp = iflib_get_ifp(ctx); 2501 u32 rctl; 2502 int mcnt = 0; 2503 2504 rctl = IXGBE_READ_REG(&sc->hw, IXGBE_FCTRL); 2505 rctl &= (~IXGBE_FCTRL_UPE); 2506 if (if_getflags(ifp) & IFF_ALLMULTI) 2507 mcnt = MAX_NUM_MULTICAST_ADDRESSES; 2508 else { 2509 mcnt = min(if_llmaddr_count(ifp), MAX_NUM_MULTICAST_ADDRESSES); 2510 } 2511 if (mcnt < MAX_NUM_MULTICAST_ADDRESSES) 2512 rctl &= (~IXGBE_FCTRL_MPE); 2513 IXGBE_WRITE_REG(&sc->hw, IXGBE_FCTRL, rctl); 2514 2515 if (if_getflags(ifp) & IFF_PROMISC) { 2516 rctl |= (IXGBE_FCTRL_UPE | IXGBE_FCTRL_MPE); 2517 IXGBE_WRITE_REG(&sc->hw, IXGBE_FCTRL, rctl); 2518 } else if (if_getflags(ifp) & IFF_ALLMULTI) { 2519 rctl |= IXGBE_FCTRL_MPE; 2520 rctl &= ~IXGBE_FCTRL_UPE; 2521 IXGBE_WRITE_REG(&sc->hw, IXGBE_FCTRL, rctl); 2522 } 2523 return (0); 2524 } /* ixgbe_if_promisc_set */ 2525 2526 /************************************************************************ 2527 * ixgbe_msix_link - Link status change ISR (MSI/MSI-X) 2528 ************************************************************************/ 2529 static int 2530 ixgbe_msix_link(void *arg) 2531 { 2532 struct ixgbe_softc *sc = arg; 2533 struct ixgbe_hw *hw = &sc->hw; 2534 u32 eicr, eicr_mask; 2535 s32 retval; 2536 2537 ++sc->link_irq; 2538 2539 /* Pause other interrupts */ 2540 IXGBE_WRITE_REG(hw, IXGBE_EIMC, IXGBE_EIMC_OTHER); 2541 2542 /* First get the cause */ 2543 eicr = IXGBE_READ_REG(hw, IXGBE_EICS); 2544 /* Be sure the queue bits are not cleared */ 2545 eicr &= ~IXGBE_EICR_RTX_QUEUE; 2546 /* Clear interrupt with write */ 2547 IXGBE_WRITE_REG(hw, IXGBE_EICR, eicr); 2548 2549 /* Link status change */ 2550 if (eicr & IXGBE_EICR_LSC) { 2551 IXGBE_WRITE_REG(hw, IXGBE_EIMC, IXGBE_EIMC_LSC); 2552 sc->task_requests |= IXGBE_REQUEST_TASK_LSC; 2553 } 2554 2555 if (sc->hw.mac.type != ixgbe_mac_82598EB) { 2556 if ((sc->feat_en & IXGBE_FEATURE_FDIR) && 2557 (eicr & IXGBE_EICR_FLOW_DIR)) { 2558 /* This is probably overkill :) */ 2559 if (!atomic_cmpset_int(&sc->fdir_reinit, 0, 1)) 2560 return (FILTER_HANDLED); 2561 /* Disable the interrupt */ 2562 IXGBE_WRITE_REG(hw, IXGBE_EIMC, IXGBE_EICR_FLOW_DIR); 2563 sc->task_requests |= IXGBE_REQUEST_TASK_FDIR; 2564 } else 2565 if (eicr & IXGBE_EICR_ECC) { 2566 device_printf(iflib_get_dev(sc->ctx), 2567 "Received ECC Err, initiating reset\n"); 2568 hw->mac.flags |= ~IXGBE_FLAGS_DOUBLE_RESET_REQUIRED; 2569 ixgbe_reset_hw(hw); 2570 IXGBE_WRITE_REG(hw, IXGBE_EICR, IXGBE_EICR_ECC); 2571 } 2572 2573 /* Check for over temp condition */ 2574 if (sc->feat_en & IXGBE_FEATURE_TEMP_SENSOR) { 2575 switch (sc->hw.mac.type) { 2576 case ixgbe_mac_X550EM_a: 2577 if (!(eicr & IXGBE_EICR_GPI_SDP0_X550EM_a)) 2578 break; 2579 IXGBE_WRITE_REG(hw, IXGBE_EIMC, 2580 IXGBE_EICR_GPI_SDP0_X550EM_a); 2581 IXGBE_WRITE_REG(hw, IXGBE_EICR, 2582 IXGBE_EICR_GPI_SDP0_X550EM_a); 2583 retval = hw->phy.ops.check_overtemp(hw); 2584 if (retval != IXGBE_ERR_OVERTEMP) 2585 break; 2586 device_printf(iflib_get_dev(sc->ctx), 2587 "\nCRITICAL: OVER TEMP!! PHY IS SHUT DOWN!!\n"); 2588 device_printf(iflib_get_dev(sc->ctx), 2589 "System shutdown required!\n"); 2590 break; 2591 default: 2592 if (!(eicr & IXGBE_EICR_TS)) 2593 break; 2594 retval = hw->phy.ops.check_overtemp(hw); 2595 if (retval != IXGBE_ERR_OVERTEMP) 2596 break; 2597 device_printf(iflib_get_dev(sc->ctx), 2598 "\nCRITICAL: OVER TEMP!! PHY IS SHUT DOWN!!\n"); 2599 device_printf(iflib_get_dev(sc->ctx), 2600 "System shutdown required!\n"); 2601 IXGBE_WRITE_REG(hw, IXGBE_EICR, IXGBE_EICR_TS); 2602 break; 2603 } 2604 } 2605 2606 /* Check for VF message */ 2607 if ((sc->feat_en & IXGBE_FEATURE_SRIOV) && 2608 (eicr & IXGBE_EICR_MAILBOX)) 2609 sc->task_requests |= IXGBE_REQUEST_TASK_MBX; 2610 } 2611 2612 if (ixgbe_is_sfp(hw)) { 2613 /* Pluggable optics-related interrupt */ 2614 if (hw->mac.type >= ixgbe_mac_X540) 2615 eicr_mask = IXGBE_EICR_GPI_SDP0_X540; 2616 else 2617 eicr_mask = IXGBE_EICR_GPI_SDP2_BY_MAC(hw); 2618 2619 if (eicr & eicr_mask) { 2620 IXGBE_WRITE_REG(hw, IXGBE_EICR, eicr_mask); 2621 sc->task_requests |= IXGBE_REQUEST_TASK_MOD; 2622 } 2623 2624 if ((hw->mac.type == ixgbe_mac_82599EB) && 2625 (eicr & IXGBE_EICR_GPI_SDP1_BY_MAC(hw))) { 2626 IXGBE_WRITE_REG(hw, IXGBE_EICR, 2627 IXGBE_EICR_GPI_SDP1_BY_MAC(hw)); 2628 sc->task_requests |= IXGBE_REQUEST_TASK_MSF; 2629 } 2630 } 2631 2632 /* Check for fan failure */ 2633 if (sc->feat_en & IXGBE_FEATURE_FAN_FAIL) { 2634 ixgbe_check_fan_failure(sc, eicr, true); 2635 IXGBE_WRITE_REG(hw, IXGBE_EICR, IXGBE_EICR_GPI_SDP1_BY_MAC(hw)); 2636 } 2637 2638 /* External PHY interrupt */ 2639 if ((hw->phy.type == ixgbe_phy_x550em_ext_t) && 2640 (eicr & IXGBE_EICR_GPI_SDP0_X540)) { 2641 IXGBE_WRITE_REG(hw, IXGBE_EICR, IXGBE_EICR_GPI_SDP0_X540); 2642 sc->task_requests |= IXGBE_REQUEST_TASK_PHY; 2643 } 2644 2645 return (sc->task_requests != 0) ? FILTER_SCHEDULE_THREAD : FILTER_HANDLED; 2646 } /* ixgbe_msix_link */ 2647 2648 /************************************************************************ 2649 * ixgbe_sysctl_interrupt_rate_handler 2650 ************************************************************************/ 2651 static int 2652 ixgbe_sysctl_interrupt_rate_handler(SYSCTL_HANDLER_ARGS) 2653 { 2654 struct ix_rx_queue *que = ((struct ix_rx_queue *)oidp->oid_arg1); 2655 int error; 2656 unsigned int reg, usec, rate; 2657 2658 reg = IXGBE_READ_REG(&que->sc->hw, IXGBE_EITR(que->msix)); 2659 usec = ((reg & 0x0FF8) >> 3); 2660 if (usec > 0) 2661 rate = 500000 / usec; 2662 else 2663 rate = 0; 2664 error = sysctl_handle_int(oidp, &rate, 0, req); 2665 if (error || !req->newptr) 2666 return error; 2667 reg &= ~0xfff; /* default, no limitation */ 2668 ixgbe_max_interrupt_rate = 0; 2669 if (rate > 0 && rate < 500000) { 2670 if (rate < 1000) 2671 rate = 1000; 2672 ixgbe_max_interrupt_rate = rate; 2673 reg |= ((4000000/rate) & 0xff8); 2674 } 2675 IXGBE_WRITE_REG(&que->sc->hw, IXGBE_EITR(que->msix), reg); 2676 2677 return (0); 2678 } /* ixgbe_sysctl_interrupt_rate_handler */ 2679 2680 /************************************************************************ 2681 * ixgbe_add_device_sysctls 2682 ************************************************************************/ 2683 static void 2684 ixgbe_add_device_sysctls(if_ctx_t ctx) 2685 { 2686 struct ixgbe_softc *sc = iflib_get_softc(ctx); 2687 device_t dev = iflib_get_dev(ctx); 2688 struct ixgbe_hw *hw = &sc->hw; 2689 struct sysctl_oid_list *child; 2690 struct sysctl_ctx_list *ctx_list; 2691 2692 ctx_list = device_get_sysctl_ctx(dev); 2693 child = SYSCTL_CHILDREN(device_get_sysctl_tree(dev)); 2694 2695 /* Sysctls for all devices */ 2696 SYSCTL_ADD_PROC(ctx_list, child, OID_AUTO, "fc", 2697 CTLTYPE_INT | CTLFLAG_RW | CTLFLAG_NEEDGIANT, 2698 sc, 0, ixgbe_sysctl_flowcntl, "I", 2699 IXGBE_SYSCTL_DESC_SET_FC); 2700 2701 SYSCTL_ADD_PROC(ctx_list, child, OID_AUTO, "advertise_speed", 2702 CTLTYPE_INT | CTLFLAG_RW | CTLFLAG_NEEDGIANT, 2703 sc, 0, ixgbe_sysctl_advertise, "I", 2704 IXGBE_SYSCTL_DESC_ADV_SPEED); 2705 2706 sc->enable_aim = ixgbe_enable_aim; 2707 SYSCTL_ADD_INT(ctx_list, child, OID_AUTO, "enable_aim", CTLFLAG_RW, 2708 &sc->enable_aim, 0, "Interrupt Moderation"); 2709 2710 SYSCTL_ADD_PROC(ctx_list, child, OID_AUTO, "fw_version", 2711 CTLTYPE_STRING | CTLFLAG_RD | CTLFLAG_NEEDGIANT, sc, 0, 2712 ixgbe_sysctl_print_fw_version, "A", "Prints FW/NVM Versions"); 2713 2714 #ifdef IXGBE_DEBUG 2715 /* testing sysctls (for all devices) */ 2716 SYSCTL_ADD_PROC(ctx_list, child, OID_AUTO, "power_state", 2717 CTLTYPE_INT | CTLFLAG_RW | CTLFLAG_NEEDGIANT, 2718 sc, 0, ixgbe_sysctl_power_state, 2719 "I", "PCI Power State"); 2720 2721 SYSCTL_ADD_PROC(ctx_list, child, OID_AUTO, "print_rss_config", 2722 CTLTYPE_STRING | CTLFLAG_RD | CTLFLAG_NEEDGIANT, sc, 0, 2723 ixgbe_sysctl_print_rss_config, "A", "Prints RSS Configuration"); 2724 #endif 2725 /* for X550 series devices */ 2726 if (hw->mac.type >= ixgbe_mac_X550) 2727 SYSCTL_ADD_PROC(ctx_list, child, OID_AUTO, "dmac", 2728 CTLTYPE_U16 | CTLFLAG_RW | CTLFLAG_NEEDGIANT, 2729 sc, 0, ixgbe_sysctl_dmac, 2730 "I", "DMA Coalesce"); 2731 2732 /* for WoL-capable devices */ 2733 if (hw->device_id == IXGBE_DEV_ID_X550EM_X_10G_T) { 2734 SYSCTL_ADD_PROC(ctx_list, child, OID_AUTO, "wol_enable", 2735 CTLTYPE_INT | CTLFLAG_RW | CTLFLAG_NEEDGIANT, sc, 0, 2736 ixgbe_sysctl_wol_enable, "I", "Enable/Disable Wake on LAN"); 2737 2738 SYSCTL_ADD_PROC(ctx_list, child, OID_AUTO, "wufc", 2739 CTLTYPE_U32 | CTLFLAG_RW | CTLFLAG_NEEDGIANT, 2740 sc, 0, ixgbe_sysctl_wufc, 2741 "I", "Enable/Disable Wake Up Filters"); 2742 } 2743 2744 /* for X552/X557-AT devices */ 2745 if (hw->device_id == IXGBE_DEV_ID_X550EM_X_10G_T) { 2746 struct sysctl_oid *phy_node; 2747 struct sysctl_oid_list *phy_list; 2748 2749 phy_node = SYSCTL_ADD_NODE(ctx_list, child, OID_AUTO, "phy", 2750 CTLFLAG_RD | CTLFLAG_MPSAFE, NULL, "External PHY sysctls"); 2751 phy_list = SYSCTL_CHILDREN(phy_node); 2752 2753 SYSCTL_ADD_PROC(ctx_list, phy_list, OID_AUTO, "temp", 2754 CTLTYPE_U16 | CTLFLAG_RD | CTLFLAG_NEEDGIANT, 2755 sc, 0, ixgbe_sysctl_phy_temp, 2756 "I", "Current External PHY Temperature (Celsius)"); 2757 2758 SYSCTL_ADD_PROC(ctx_list, phy_list, OID_AUTO, 2759 "overtemp_occurred", 2760 CTLTYPE_U16 | CTLFLAG_RD | CTLFLAG_NEEDGIANT, sc, 0, 2761 ixgbe_sysctl_phy_overtemp_occurred, "I", 2762 "External PHY High Temperature Event Occurred"); 2763 } 2764 2765 if (sc->feat_cap & IXGBE_FEATURE_EEE) { 2766 SYSCTL_ADD_PROC(ctx_list, child, OID_AUTO, "eee_state", 2767 CTLTYPE_INT | CTLFLAG_RW | CTLFLAG_NEEDGIANT, sc, 0, 2768 ixgbe_sysctl_eee_state, "I", "EEE Power Save State"); 2769 } 2770 } /* ixgbe_add_device_sysctls */ 2771 2772 /************************************************************************ 2773 * ixgbe_allocate_pci_resources 2774 ************************************************************************/ 2775 static int 2776 ixgbe_allocate_pci_resources(if_ctx_t ctx) 2777 { 2778 struct ixgbe_softc *sc = iflib_get_softc(ctx); 2779 device_t dev = iflib_get_dev(ctx); 2780 int rid; 2781 2782 rid = PCIR_BAR(0); 2783 sc->pci_mem = bus_alloc_resource_any(dev, SYS_RES_MEMORY, &rid, 2784 RF_ACTIVE); 2785 2786 if (!(sc->pci_mem)) { 2787 device_printf(dev, "Unable to allocate bus resource: memory\n"); 2788 return (ENXIO); 2789 } 2790 2791 /* Save bus_space values for READ/WRITE_REG macros */ 2792 sc->osdep.mem_bus_space_tag = rman_get_bustag(sc->pci_mem); 2793 sc->osdep.mem_bus_space_handle = 2794 rman_get_bushandle(sc->pci_mem); 2795 /* Set hw values for shared code */ 2796 sc->hw.hw_addr = (u8 *)&sc->osdep.mem_bus_space_handle; 2797 2798 return (0); 2799 } /* ixgbe_allocate_pci_resources */ 2800 2801 /************************************************************************ 2802 * ixgbe_detach - Device removal routine 2803 * 2804 * Called when the driver is being removed. 2805 * Stops the adapter and deallocates all the resources 2806 * that were allocated for driver operation. 2807 * 2808 * return 0 on success, positive on failure 2809 ************************************************************************/ 2810 static int 2811 ixgbe_if_detach(if_ctx_t ctx) 2812 { 2813 struct ixgbe_softc *sc = iflib_get_softc(ctx); 2814 device_t dev = iflib_get_dev(ctx); 2815 u32 ctrl_ext; 2816 2817 INIT_DEBUGOUT("ixgbe_detach: begin"); 2818 2819 if (ixgbe_pci_iov_detach(dev) != 0) { 2820 device_printf(dev, "SR-IOV in use; detach first.\n"); 2821 return (EBUSY); 2822 } 2823 2824 ixgbe_setup_low_power_mode(ctx); 2825 2826 /* let hardware know driver is unloading */ 2827 ctrl_ext = IXGBE_READ_REG(&sc->hw, IXGBE_CTRL_EXT); 2828 ctrl_ext &= ~IXGBE_CTRL_EXT_DRV_LOAD; 2829 IXGBE_WRITE_REG(&sc->hw, IXGBE_CTRL_EXT, ctrl_ext); 2830 2831 ixgbe_free_pci_resources(ctx); 2832 free(sc->mta, M_IXGBE); 2833 2834 return (0); 2835 } /* ixgbe_if_detach */ 2836 2837 /************************************************************************ 2838 * ixgbe_setup_low_power_mode - LPLU/WoL preparation 2839 * 2840 * Prepare the adapter/port for LPLU and/or WoL 2841 ************************************************************************/ 2842 static int 2843 ixgbe_setup_low_power_mode(if_ctx_t ctx) 2844 { 2845 struct ixgbe_softc *sc = iflib_get_softc(ctx); 2846 struct ixgbe_hw *hw = &sc->hw; 2847 device_t dev = iflib_get_dev(ctx); 2848 s32 error = 0; 2849 2850 if (!hw->wol_enabled) 2851 ixgbe_set_phy_power(hw, false); 2852 2853 /* Limit power management flow to X550EM baseT */ 2854 if (hw->device_id == IXGBE_DEV_ID_X550EM_X_10G_T && 2855 hw->phy.ops.enter_lplu) { 2856 /* Turn off support for APM wakeup. (Using ACPI instead) */ 2857 IXGBE_WRITE_REG(hw, IXGBE_GRC, 2858 IXGBE_READ_REG(hw, IXGBE_GRC) & ~(u32)2); 2859 2860 /* 2861 * Clear Wake Up Status register to prevent any previous wakeup 2862 * events from waking us up immediately after we suspend. 2863 */ 2864 IXGBE_WRITE_REG(hw, IXGBE_WUS, 0xffffffff); 2865 2866 /* 2867 * Program the Wakeup Filter Control register with user filter 2868 * settings 2869 */ 2870 IXGBE_WRITE_REG(hw, IXGBE_WUFC, sc->wufc); 2871 2872 /* Enable wakeups and power management in Wakeup Control */ 2873 IXGBE_WRITE_REG(hw, IXGBE_WUC, 2874 IXGBE_WUC_WKEN | IXGBE_WUC_PME_EN); 2875 2876 /* X550EM baseT adapters need a special LPLU flow */ 2877 hw->phy.reset_disable = true; 2878 ixgbe_if_stop(ctx); 2879 error = hw->phy.ops.enter_lplu(hw); 2880 if (error) 2881 device_printf(dev, "Error entering LPLU: %d\n", error); 2882 hw->phy.reset_disable = false; 2883 } else { 2884 /* Just stop for other adapters */ 2885 ixgbe_if_stop(ctx); 2886 } 2887 2888 return error; 2889 } /* ixgbe_setup_low_power_mode */ 2890 2891 /************************************************************************ 2892 * ixgbe_shutdown - Shutdown entry point 2893 ************************************************************************/ 2894 static int 2895 ixgbe_if_shutdown(if_ctx_t ctx) 2896 { 2897 int error = 0; 2898 2899 INIT_DEBUGOUT("ixgbe_shutdown: begin"); 2900 2901 error = ixgbe_setup_low_power_mode(ctx); 2902 2903 return (error); 2904 } /* ixgbe_if_shutdown */ 2905 2906 /************************************************************************ 2907 * ixgbe_suspend 2908 * 2909 * From D0 to D3 2910 ************************************************************************/ 2911 static int 2912 ixgbe_if_suspend(if_ctx_t ctx) 2913 { 2914 int error = 0; 2915 2916 INIT_DEBUGOUT("ixgbe_suspend: begin"); 2917 2918 error = ixgbe_setup_low_power_mode(ctx); 2919 2920 return (error); 2921 } /* ixgbe_if_suspend */ 2922 2923 /************************************************************************ 2924 * ixgbe_resume 2925 * 2926 * From D3 to D0 2927 ************************************************************************/ 2928 static int 2929 ixgbe_if_resume(if_ctx_t ctx) 2930 { 2931 struct ixgbe_softc *sc = iflib_get_softc(ctx); 2932 device_t dev = iflib_get_dev(ctx); 2933 if_t ifp = iflib_get_ifp(ctx); 2934 struct ixgbe_hw *hw = &sc->hw; 2935 u32 wus; 2936 2937 INIT_DEBUGOUT("ixgbe_resume: begin"); 2938 2939 /* Read & clear WUS register */ 2940 wus = IXGBE_READ_REG(hw, IXGBE_WUS); 2941 if (wus) 2942 device_printf(dev, "Woken up by (WUS): %#010x\n", 2943 IXGBE_READ_REG(hw, IXGBE_WUS)); 2944 IXGBE_WRITE_REG(hw, IXGBE_WUS, 0xffffffff); 2945 /* And clear WUFC until next low-power transition */ 2946 IXGBE_WRITE_REG(hw, IXGBE_WUFC, 0); 2947 2948 /* 2949 * Required after D3->D0 transition; 2950 * will re-advertise all previous advertised speeds 2951 */ 2952 if (if_getflags(ifp) & IFF_UP) 2953 ixgbe_if_init(ctx); 2954 2955 return (0); 2956 } /* ixgbe_if_resume */ 2957 2958 /************************************************************************ 2959 * ixgbe_if_mtu_set - Ioctl mtu entry point 2960 * 2961 * Return 0 on success, EINVAL on failure 2962 ************************************************************************/ 2963 static int 2964 ixgbe_if_mtu_set(if_ctx_t ctx, uint32_t mtu) 2965 { 2966 struct ixgbe_softc *sc = iflib_get_softc(ctx); 2967 int error = 0; 2968 2969 IOCTL_DEBUGOUT("ioctl: SIOCIFMTU (Set Interface MTU)"); 2970 2971 if (mtu > IXGBE_MAX_MTU) { 2972 error = EINVAL; 2973 } else { 2974 sc->max_frame_size = mtu + IXGBE_MTU_HDR; 2975 } 2976 2977 return error; 2978 } /* ixgbe_if_mtu_set */ 2979 2980 /************************************************************************ 2981 * ixgbe_if_crcstrip_set 2982 ************************************************************************/ 2983 static void 2984 ixgbe_if_crcstrip_set(if_ctx_t ctx, int onoff, int crcstrip) 2985 { 2986 struct ixgbe_softc *sc = iflib_get_softc(ctx); 2987 struct ixgbe_hw *hw = &sc->hw; 2988 /* crc stripping is set in two places: 2989 * IXGBE_HLREG0 (modified on init_locked and hw reset) 2990 * IXGBE_RDRXCTL (set by the original driver in 2991 * ixgbe_setup_hw_rsc() called in init_locked. 2992 * We disable the setting when netmap is compiled in). 2993 * We update the values here, but also in ixgbe.c because 2994 * init_locked sometimes is called outside our control. 2995 */ 2996 uint32_t hl, rxc; 2997 2998 hl = IXGBE_READ_REG(hw, IXGBE_HLREG0); 2999 rxc = IXGBE_READ_REG(hw, IXGBE_RDRXCTL); 3000 #ifdef NETMAP 3001 if (netmap_verbose) 3002 D("%s read HLREG 0x%x rxc 0x%x", 3003 onoff ? "enter" : "exit", hl, rxc); 3004 #endif 3005 /* hw requirements ... */ 3006 rxc &= ~IXGBE_RDRXCTL_RSCFRSTSIZE; 3007 rxc |= IXGBE_RDRXCTL_RSCACKC; 3008 if (onoff && !crcstrip) { 3009 /* keep the crc. Fast rx */ 3010 hl &= ~IXGBE_HLREG0_RXCRCSTRP; 3011 rxc &= ~IXGBE_RDRXCTL_CRCSTRIP; 3012 } else { 3013 /* reset default mode */ 3014 hl |= IXGBE_HLREG0_RXCRCSTRP; 3015 rxc |= IXGBE_RDRXCTL_CRCSTRIP; 3016 } 3017 #ifdef NETMAP 3018 if (netmap_verbose) 3019 D("%s write HLREG 0x%x rxc 0x%x", 3020 onoff ? "enter" : "exit", hl, rxc); 3021 #endif 3022 IXGBE_WRITE_REG(hw, IXGBE_HLREG0, hl); 3023 IXGBE_WRITE_REG(hw, IXGBE_RDRXCTL, rxc); 3024 } /* ixgbe_if_crcstrip_set */ 3025 3026 /********************************************************************* 3027 * ixgbe_if_init - Init entry point 3028 * 3029 * Used in two ways: It is used by the stack as an init 3030 * entry point in network interface structure. It is also 3031 * used by the driver as a hw/sw initialization routine to 3032 * get to a consistent state. 3033 * 3034 * Return 0 on success, positive on failure 3035 **********************************************************************/ 3036 void 3037 ixgbe_if_init(if_ctx_t ctx) 3038 { 3039 struct ixgbe_softc *sc = iflib_get_softc(ctx); 3040 if_t ifp = iflib_get_ifp(ctx); 3041 device_t dev = iflib_get_dev(ctx); 3042 struct ixgbe_hw *hw = &sc->hw; 3043 struct ix_rx_queue *rx_que; 3044 struct ix_tx_queue *tx_que; 3045 u32 txdctl, mhadd; 3046 u32 rxdctl, rxctrl; 3047 u32 ctrl_ext; 3048 3049 int i, j, err; 3050 3051 INIT_DEBUGOUT("ixgbe_if_init: begin"); 3052 3053 /* Queue indices may change with IOV mode */ 3054 ixgbe_align_all_queue_indices(sc); 3055 3056 /* reprogram the RAR[0] in case user changed it. */ 3057 ixgbe_set_rar(hw, 0, hw->mac.addr, sc->pool, IXGBE_RAH_AV); 3058 3059 /* Get the latest mac address, User can use a LAA */ 3060 bcopy(if_getlladdr(ifp), hw->mac.addr, IXGBE_ETH_LENGTH_OF_ADDRESS); 3061 ixgbe_set_rar(hw, 0, hw->mac.addr, sc->pool, 1); 3062 hw->addr_ctrl.rar_used_count = 1; 3063 3064 ixgbe_init_hw(hw); 3065 3066 ixgbe_initialize_iov(sc); 3067 3068 ixgbe_initialize_transmit_units(ctx); 3069 3070 /* Setup Multicast table */ 3071 ixgbe_if_multi_set(ctx); 3072 3073 /* Determine the correct mbuf pool, based on frame size */ 3074 sc->rx_mbuf_sz = iflib_get_rx_mbuf_sz(ctx); 3075 3076 /* Configure RX settings */ 3077 ixgbe_initialize_receive_units(ctx); 3078 3079 /* 3080 * Initialize variable holding task enqueue requests 3081 * from MSI-X interrupts 3082 */ 3083 sc->task_requests = 0; 3084 3085 /* Enable SDP & MSI-X interrupts based on adapter */ 3086 ixgbe_config_gpie(sc); 3087 3088 /* Set MTU size */ 3089 if (if_getmtu(ifp) > ETHERMTU) { 3090 /* aka IXGBE_MAXFRS on 82599 and newer */ 3091 mhadd = IXGBE_READ_REG(hw, IXGBE_MHADD); 3092 mhadd &= ~IXGBE_MHADD_MFS_MASK; 3093 mhadd |= sc->max_frame_size << IXGBE_MHADD_MFS_SHIFT; 3094 IXGBE_WRITE_REG(hw, IXGBE_MHADD, mhadd); 3095 } 3096 3097 /* Now enable all the queues */ 3098 for (i = 0, tx_que = sc->tx_queues; i < sc->num_tx_queues; i++, tx_que++) { 3099 struct tx_ring *txr = &tx_que->txr; 3100 3101 txdctl = IXGBE_READ_REG(hw, IXGBE_TXDCTL(txr->me)); 3102 txdctl |= IXGBE_TXDCTL_ENABLE; 3103 /* Set WTHRESH to 8, burst writeback */ 3104 txdctl |= (8 << 16); 3105 /* 3106 * When the internal queue falls below PTHRESH (32), 3107 * start prefetching as long as there are at least 3108 * HTHRESH (1) buffers ready. The values are taken 3109 * from the Intel linux driver 3.8.21. 3110 * Prefetching enables tx line rate even with 1 queue. 3111 */ 3112 txdctl |= (32 << 0) | (1 << 8); 3113 IXGBE_WRITE_REG(hw, IXGBE_TXDCTL(txr->me), txdctl); 3114 } 3115 3116 for (i = 0, rx_que = sc->rx_queues; i < sc->num_rx_queues; i++, rx_que++) { 3117 struct rx_ring *rxr = &rx_que->rxr; 3118 3119 rxdctl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(rxr->me)); 3120 if (hw->mac.type == ixgbe_mac_82598EB) { 3121 /* 3122 * PTHRESH = 21 3123 * HTHRESH = 4 3124 * WTHRESH = 8 3125 */ 3126 rxdctl &= ~0x3FFFFF; 3127 rxdctl |= 0x080420; 3128 } 3129 rxdctl |= IXGBE_RXDCTL_ENABLE; 3130 IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(rxr->me), rxdctl); 3131 for (j = 0; j < 10; j++) { 3132 if (IXGBE_READ_REG(hw, IXGBE_RXDCTL(rxr->me)) & 3133 IXGBE_RXDCTL_ENABLE) 3134 break; 3135 else 3136 msec_delay(1); 3137 } 3138 wmb(); 3139 } 3140 3141 /* Enable Receive engine */ 3142 rxctrl = IXGBE_READ_REG(hw, IXGBE_RXCTRL); 3143 if (hw->mac.type == ixgbe_mac_82598EB) 3144 rxctrl |= IXGBE_RXCTRL_DMBYPS; 3145 rxctrl |= IXGBE_RXCTRL_RXEN; 3146 ixgbe_enable_rx_dma(hw, rxctrl); 3147 3148 /* Set up MSI/MSI-X routing */ 3149 if (ixgbe_enable_msix) { 3150 ixgbe_configure_ivars(sc); 3151 /* Set up auto-mask */ 3152 if (hw->mac.type == ixgbe_mac_82598EB) 3153 IXGBE_WRITE_REG(hw, IXGBE_EIAM, IXGBE_EICS_RTX_QUEUE); 3154 else { 3155 IXGBE_WRITE_REG(hw, IXGBE_EIAM_EX(0), 0xFFFFFFFF); 3156 IXGBE_WRITE_REG(hw, IXGBE_EIAM_EX(1), 0xFFFFFFFF); 3157 } 3158 } else { /* Simple settings for Legacy/MSI */ 3159 ixgbe_set_ivar(sc, 0, 0, 0); 3160 ixgbe_set_ivar(sc, 0, 0, 1); 3161 IXGBE_WRITE_REG(hw, IXGBE_EIAM, IXGBE_EICS_RTX_QUEUE); 3162 } 3163 3164 ixgbe_init_fdir(sc); 3165 3166 /* 3167 * Check on any SFP devices that 3168 * need to be kick-started 3169 */ 3170 if (hw->phy.type == ixgbe_phy_none) { 3171 err = hw->phy.ops.identify(hw); 3172 if (err == IXGBE_ERR_SFP_NOT_SUPPORTED) { 3173 device_printf(dev, 3174 "Unsupported SFP+ module type was detected.\n"); 3175 return; 3176 } 3177 } 3178 3179 /* Set moderation on the Link interrupt */ 3180 IXGBE_WRITE_REG(hw, IXGBE_EITR(sc->vector), IXGBE_LINK_ITR); 3181 3182 /* Enable power to the phy. */ 3183 ixgbe_set_phy_power(hw, true); 3184 3185 /* Config/Enable Link */ 3186 ixgbe_config_link(ctx); 3187 3188 /* Hardware Packet Buffer & Flow Control setup */ 3189 ixgbe_config_delay_values(sc); 3190 3191 /* Initialize the FC settings */ 3192 ixgbe_start_hw(hw); 3193 3194 /* Set up VLAN support and filter */ 3195 ixgbe_setup_vlan_hw_support(ctx); 3196 3197 /* Setup DMA Coalescing */ 3198 ixgbe_config_dmac(sc); 3199 3200 /* And now turn on interrupts */ 3201 ixgbe_if_enable_intr(ctx); 3202 3203 /* Enable the use of the MBX by the VF's */ 3204 if (sc->feat_en & IXGBE_FEATURE_SRIOV) { 3205 ctrl_ext = IXGBE_READ_REG(hw, IXGBE_CTRL_EXT); 3206 ctrl_ext |= IXGBE_CTRL_EXT_PFRSTD; 3207 IXGBE_WRITE_REG(hw, IXGBE_CTRL_EXT, ctrl_ext); 3208 } 3209 3210 } /* ixgbe_init_locked */ 3211 3212 /************************************************************************ 3213 * ixgbe_set_ivar 3214 * 3215 * Setup the correct IVAR register for a particular MSI-X interrupt 3216 * (yes this is all very magic and confusing :) 3217 * - entry is the register array entry 3218 * - vector is the MSI-X vector for this queue 3219 * - type is RX/TX/MISC 3220 ************************************************************************/ 3221 static void 3222 ixgbe_set_ivar(struct ixgbe_softc *sc, u8 entry, u8 vector, s8 type) 3223 { 3224 struct ixgbe_hw *hw = &sc->hw; 3225 u32 ivar, index; 3226 3227 vector |= IXGBE_IVAR_ALLOC_VAL; 3228 3229 switch (hw->mac.type) { 3230 case ixgbe_mac_82598EB: 3231 if (type == -1) 3232 entry = IXGBE_IVAR_OTHER_CAUSES_INDEX; 3233 else 3234 entry += (type * 64); 3235 index = (entry >> 2) & 0x1F; 3236 ivar = IXGBE_READ_REG(hw, IXGBE_IVAR(index)); 3237 ivar &= ~(0xFF << (8 * (entry & 0x3))); 3238 ivar |= (vector << (8 * (entry & 0x3))); 3239 IXGBE_WRITE_REG(&sc->hw, IXGBE_IVAR(index), ivar); 3240 break; 3241 case ixgbe_mac_82599EB: 3242 case ixgbe_mac_X540: 3243 case ixgbe_mac_X550: 3244 case ixgbe_mac_X550EM_x: 3245 case ixgbe_mac_X550EM_a: 3246 if (type == -1) { /* MISC IVAR */ 3247 index = (entry & 1) * 8; 3248 ivar = IXGBE_READ_REG(hw, IXGBE_IVAR_MISC); 3249 ivar &= ~(0xFF << index); 3250 ivar |= (vector << index); 3251 IXGBE_WRITE_REG(hw, IXGBE_IVAR_MISC, ivar); 3252 } else { /* RX/TX IVARS */ 3253 index = (16 * (entry & 1)) + (8 * type); 3254 ivar = IXGBE_READ_REG(hw, IXGBE_IVAR(entry >> 1)); 3255 ivar &= ~(0xFF << index); 3256 ivar |= (vector << index); 3257 IXGBE_WRITE_REG(hw, IXGBE_IVAR(entry >> 1), ivar); 3258 } 3259 default: 3260 break; 3261 } 3262 } /* ixgbe_set_ivar */ 3263 3264 /************************************************************************ 3265 * ixgbe_configure_ivars 3266 ************************************************************************/ 3267 static void 3268 ixgbe_configure_ivars(struct ixgbe_softc *sc) 3269 { 3270 struct ix_rx_queue *rx_que = sc->rx_queues; 3271 struct ix_tx_queue *tx_que = sc->tx_queues; 3272 u32 newitr; 3273 3274 if (ixgbe_max_interrupt_rate > 0) 3275 newitr = (4000000 / ixgbe_max_interrupt_rate) & 0x0FF8; 3276 else { 3277 /* 3278 * Disable DMA coalescing if interrupt moderation is 3279 * disabled. 3280 */ 3281 sc->dmac = 0; 3282 newitr = 0; 3283 } 3284 3285 for (int i = 0; i < sc->num_rx_queues; i++, rx_que++) { 3286 struct rx_ring *rxr = &rx_que->rxr; 3287 3288 /* First the RX queue entry */ 3289 ixgbe_set_ivar(sc, rxr->me, rx_que->msix, 0); 3290 3291 /* Set an Initial EITR value */ 3292 IXGBE_WRITE_REG(&sc->hw, IXGBE_EITR(rx_que->msix), newitr); 3293 } 3294 for (int i = 0; i < sc->num_tx_queues; i++, tx_que++) { 3295 struct tx_ring *txr = &tx_que->txr; 3296 3297 /* ... and the TX */ 3298 ixgbe_set_ivar(sc, txr->me, tx_que->msix, 1); 3299 } 3300 /* For the Link interrupt */ 3301 ixgbe_set_ivar(sc, 1, sc->vector, -1); 3302 } /* ixgbe_configure_ivars */ 3303 3304 /************************************************************************ 3305 * ixgbe_config_gpie 3306 ************************************************************************/ 3307 static void 3308 ixgbe_config_gpie(struct ixgbe_softc *sc) 3309 { 3310 struct ixgbe_hw *hw = &sc->hw; 3311 u32 gpie; 3312 3313 gpie = IXGBE_READ_REG(hw, IXGBE_GPIE); 3314 3315 if (sc->intr_type == IFLIB_INTR_MSIX) { 3316 /* Enable Enhanced MSI-X mode */ 3317 gpie |= IXGBE_GPIE_MSIX_MODE 3318 | IXGBE_GPIE_EIAME 3319 | IXGBE_GPIE_PBA_SUPPORT 3320 | IXGBE_GPIE_OCD; 3321 } 3322 3323 /* Fan Failure Interrupt */ 3324 if (sc->feat_en & IXGBE_FEATURE_FAN_FAIL) 3325 gpie |= IXGBE_SDP1_GPIEN; 3326 3327 /* Thermal Sensor Interrupt */ 3328 if (sc->feat_en & IXGBE_FEATURE_TEMP_SENSOR) 3329 gpie |= IXGBE_SDP0_GPIEN_X540; 3330 3331 /* Link detection */ 3332 switch (hw->mac.type) { 3333 case ixgbe_mac_82599EB: 3334 gpie |= IXGBE_SDP1_GPIEN | IXGBE_SDP2_GPIEN; 3335 break; 3336 case ixgbe_mac_X550EM_x: 3337 case ixgbe_mac_X550EM_a: 3338 gpie |= IXGBE_SDP0_GPIEN_X540; 3339 break; 3340 default: 3341 break; 3342 } 3343 3344 IXGBE_WRITE_REG(hw, IXGBE_GPIE, gpie); 3345 3346 } /* ixgbe_config_gpie */ 3347 3348 /************************************************************************ 3349 * ixgbe_config_delay_values 3350 * 3351 * Requires sc->max_frame_size to be set. 3352 ************************************************************************/ 3353 static void 3354 ixgbe_config_delay_values(struct ixgbe_softc *sc) 3355 { 3356 struct ixgbe_hw *hw = &sc->hw; 3357 u32 rxpb, frame, size, tmp; 3358 3359 frame = sc->max_frame_size; 3360 3361 /* Calculate High Water */ 3362 switch (hw->mac.type) { 3363 case ixgbe_mac_X540: 3364 case ixgbe_mac_X550: 3365 case ixgbe_mac_X550EM_x: 3366 case ixgbe_mac_X550EM_a: 3367 tmp = IXGBE_DV_X540(frame, frame); 3368 break; 3369 default: 3370 tmp = IXGBE_DV(frame, frame); 3371 break; 3372 } 3373 size = IXGBE_BT2KB(tmp); 3374 rxpb = IXGBE_READ_REG(hw, IXGBE_RXPBSIZE(0)) >> 10; 3375 hw->fc.high_water[0] = rxpb - size; 3376 3377 /* Now calculate Low Water */ 3378 switch (hw->mac.type) { 3379 case ixgbe_mac_X540: 3380 case ixgbe_mac_X550: 3381 case ixgbe_mac_X550EM_x: 3382 case ixgbe_mac_X550EM_a: 3383 tmp = IXGBE_LOW_DV_X540(frame); 3384 break; 3385 default: 3386 tmp = IXGBE_LOW_DV(frame); 3387 break; 3388 } 3389 hw->fc.low_water[0] = IXGBE_BT2KB(tmp); 3390 3391 hw->fc.pause_time = IXGBE_FC_PAUSE; 3392 hw->fc.send_xon = true; 3393 } /* ixgbe_config_delay_values */ 3394 3395 /************************************************************************ 3396 * ixgbe_set_multi - Multicast Update 3397 * 3398 * Called whenever multicast address list is updated. 3399 ************************************************************************/ 3400 static u_int 3401 ixgbe_mc_filter_apply(void *arg, struct sockaddr_dl *sdl, u_int idx) 3402 { 3403 struct ixgbe_softc *sc = arg; 3404 struct ixgbe_mc_addr *mta = sc->mta; 3405 3406 if (idx == MAX_NUM_MULTICAST_ADDRESSES) 3407 return (0); 3408 bcopy(LLADDR(sdl), mta[idx].addr, IXGBE_ETH_LENGTH_OF_ADDRESS); 3409 mta[idx].vmdq = sc->pool; 3410 3411 return (1); 3412 } /* ixgbe_mc_filter_apply */ 3413 3414 static void 3415 ixgbe_if_multi_set(if_ctx_t ctx) 3416 { 3417 struct ixgbe_softc *sc = iflib_get_softc(ctx); 3418 struct ixgbe_mc_addr *mta; 3419 if_t ifp = iflib_get_ifp(ctx); 3420 u8 *update_ptr; 3421 u32 fctrl; 3422 u_int mcnt; 3423 3424 IOCTL_DEBUGOUT("ixgbe_if_multi_set: begin"); 3425 3426 mta = sc->mta; 3427 bzero(mta, sizeof(*mta) * MAX_NUM_MULTICAST_ADDRESSES); 3428 3429 mcnt = if_foreach_llmaddr(iflib_get_ifp(ctx), ixgbe_mc_filter_apply, sc); 3430 3431 if (mcnt < MAX_NUM_MULTICAST_ADDRESSES) { 3432 update_ptr = (u8 *)mta; 3433 ixgbe_update_mc_addr_list(&sc->hw, update_ptr, mcnt, 3434 ixgbe_mc_array_itr, true); 3435 } 3436 3437 fctrl = IXGBE_READ_REG(&sc->hw, IXGBE_FCTRL); 3438 3439 if (if_getflags(ifp) & IFF_PROMISC) 3440 fctrl |= (IXGBE_FCTRL_UPE | IXGBE_FCTRL_MPE); 3441 else if (mcnt >= MAX_NUM_MULTICAST_ADDRESSES || 3442 if_getflags(ifp) & IFF_ALLMULTI) { 3443 fctrl |= IXGBE_FCTRL_MPE; 3444 fctrl &= ~IXGBE_FCTRL_UPE; 3445 } else 3446 fctrl &= ~(IXGBE_FCTRL_UPE | IXGBE_FCTRL_MPE); 3447 3448 IXGBE_WRITE_REG(&sc->hw, IXGBE_FCTRL, fctrl); 3449 } /* ixgbe_if_multi_set */ 3450 3451 /************************************************************************ 3452 * ixgbe_mc_array_itr 3453 * 3454 * An iterator function needed by the multicast shared code. 3455 * It feeds the shared code routine the addresses in the 3456 * array of ixgbe_set_multi() one by one. 3457 ************************************************************************/ 3458 static u8 * 3459 ixgbe_mc_array_itr(struct ixgbe_hw *hw, u8 **update_ptr, u32 *vmdq) 3460 { 3461 struct ixgbe_mc_addr *mta; 3462 3463 mta = (struct ixgbe_mc_addr *)*update_ptr; 3464 *vmdq = mta->vmdq; 3465 3466 *update_ptr = (u8*)(mta + 1); 3467 3468 return (mta->addr); 3469 } /* ixgbe_mc_array_itr */ 3470 3471 /************************************************************************ 3472 * ixgbe_local_timer - Timer routine 3473 * 3474 * Checks for link status, updates statistics, 3475 * and runs the watchdog check. 3476 ************************************************************************/ 3477 static void 3478 ixgbe_if_timer(if_ctx_t ctx, uint16_t qid) 3479 { 3480 struct ixgbe_softc *sc = iflib_get_softc(ctx); 3481 3482 if (qid != 0) 3483 return; 3484 3485 /* Check for pluggable optics */ 3486 if (sc->sfp_probe) 3487 if (!ixgbe_sfp_probe(ctx)) 3488 return; /* Nothing to do */ 3489 3490 ixgbe_check_link(&sc->hw, &sc->link_speed, &sc->link_up, 0); 3491 3492 /* Fire off the adminq task */ 3493 iflib_admin_intr_deferred(ctx); 3494 3495 } /* ixgbe_if_timer */ 3496 3497 /************************************************************************ 3498 * ixgbe_sfp_probe 3499 * 3500 * Determine if a port had optics inserted. 3501 ************************************************************************/ 3502 static bool 3503 ixgbe_sfp_probe(if_ctx_t ctx) 3504 { 3505 struct ixgbe_softc *sc = iflib_get_softc(ctx); 3506 struct ixgbe_hw *hw = &sc->hw; 3507 device_t dev = iflib_get_dev(ctx); 3508 bool result = false; 3509 3510 if ((hw->phy.type == ixgbe_phy_nl) && 3511 (hw->phy.sfp_type == ixgbe_sfp_type_not_present)) { 3512 s32 ret = hw->phy.ops.identify_sfp(hw); 3513 if (ret) 3514 goto out; 3515 ret = hw->phy.ops.reset(hw); 3516 sc->sfp_probe = false; 3517 if (ret == IXGBE_ERR_SFP_NOT_SUPPORTED) { 3518 device_printf(dev, "Unsupported SFP+ module detected!"); 3519 device_printf(dev, 3520 "Reload driver with supported module.\n"); 3521 goto out; 3522 } else 3523 device_printf(dev, "SFP+ module detected!\n"); 3524 /* We now have supported optics */ 3525 result = true; 3526 } 3527 out: 3528 3529 return (result); 3530 } /* ixgbe_sfp_probe */ 3531 3532 /************************************************************************ 3533 * ixgbe_handle_mod - Tasklet for SFP module interrupts 3534 ************************************************************************/ 3535 static void 3536 ixgbe_handle_mod(void *context) 3537 { 3538 if_ctx_t ctx = context; 3539 struct ixgbe_softc *sc = iflib_get_softc(ctx); 3540 struct ixgbe_hw *hw = &sc->hw; 3541 device_t dev = iflib_get_dev(ctx); 3542 u32 err, cage_full = 0; 3543 3544 if (sc->hw.need_crosstalk_fix) { 3545 switch (hw->mac.type) { 3546 case ixgbe_mac_82599EB: 3547 cage_full = IXGBE_READ_REG(hw, IXGBE_ESDP) & 3548 IXGBE_ESDP_SDP2; 3549 break; 3550 case ixgbe_mac_X550EM_x: 3551 case ixgbe_mac_X550EM_a: 3552 cage_full = IXGBE_READ_REG(hw, IXGBE_ESDP) & 3553 IXGBE_ESDP_SDP0; 3554 break; 3555 default: 3556 break; 3557 } 3558 3559 if (!cage_full) 3560 goto handle_mod_out; 3561 } 3562 3563 err = hw->phy.ops.identify_sfp(hw); 3564 if (err == IXGBE_ERR_SFP_NOT_SUPPORTED) { 3565 device_printf(dev, 3566 "Unsupported SFP+ module type was detected.\n"); 3567 goto handle_mod_out; 3568 } 3569 3570 if (hw->mac.type == ixgbe_mac_82598EB) 3571 err = hw->phy.ops.reset(hw); 3572 else 3573 err = hw->mac.ops.setup_sfp(hw); 3574 3575 if (err == IXGBE_ERR_SFP_NOT_SUPPORTED) { 3576 device_printf(dev, 3577 "Setup failure - unsupported SFP+ module type.\n"); 3578 goto handle_mod_out; 3579 } 3580 sc->task_requests |= IXGBE_REQUEST_TASK_MSF; 3581 return; 3582 3583 handle_mod_out: 3584 sc->task_requests &= ~(IXGBE_REQUEST_TASK_MSF); 3585 } /* ixgbe_handle_mod */ 3586 3587 3588 /************************************************************************ 3589 * ixgbe_handle_msf - Tasklet for MSF (multispeed fiber) interrupts 3590 ************************************************************************/ 3591 static void 3592 ixgbe_handle_msf(void *context) 3593 { 3594 if_ctx_t ctx = context; 3595 struct ixgbe_softc *sc = iflib_get_softc(ctx); 3596 struct ixgbe_hw *hw = &sc->hw; 3597 u32 autoneg; 3598 bool negotiate; 3599 3600 /* get_supported_phy_layer will call hw->phy.ops.identify_sfp() */ 3601 sc->phy_layer = ixgbe_get_supported_physical_layer(hw); 3602 3603 autoneg = hw->phy.autoneg_advertised; 3604 if ((!autoneg) && (hw->mac.ops.get_link_capabilities)) 3605 hw->mac.ops.get_link_capabilities(hw, &autoneg, &negotiate); 3606 if (hw->mac.ops.setup_link) 3607 hw->mac.ops.setup_link(hw, autoneg, true); 3608 3609 /* Adjust media types shown in ifconfig */ 3610 ifmedia_removeall(sc->media); 3611 ixgbe_add_media_types(sc->ctx); 3612 ifmedia_set(sc->media, IFM_ETHER | IFM_AUTO); 3613 } /* ixgbe_handle_msf */ 3614 3615 /************************************************************************ 3616 * ixgbe_handle_phy - Tasklet for external PHY interrupts 3617 ************************************************************************/ 3618 static void 3619 ixgbe_handle_phy(void *context) 3620 { 3621 if_ctx_t ctx = context; 3622 struct ixgbe_softc *sc = iflib_get_softc(ctx); 3623 struct ixgbe_hw *hw = &sc->hw; 3624 int error; 3625 3626 error = hw->phy.ops.handle_lasi(hw); 3627 if (error == IXGBE_ERR_OVERTEMP) 3628 device_printf(sc->dev, "CRITICAL: EXTERNAL PHY OVER TEMP!! PHY will downshift to lower power state!\n"); 3629 else if (error) 3630 device_printf(sc->dev, 3631 "Error handling LASI interrupt: %d\n", error); 3632 } /* ixgbe_handle_phy */ 3633 3634 /************************************************************************ 3635 * ixgbe_if_stop - Stop the hardware 3636 * 3637 * Disables all traffic on the adapter by issuing a 3638 * global reset on the MAC and deallocates TX/RX buffers. 3639 ************************************************************************/ 3640 static void 3641 ixgbe_if_stop(if_ctx_t ctx) 3642 { 3643 struct ixgbe_softc *sc = iflib_get_softc(ctx); 3644 struct ixgbe_hw *hw = &sc->hw; 3645 3646 INIT_DEBUGOUT("ixgbe_if_stop: begin\n"); 3647 3648 ixgbe_reset_hw(hw); 3649 hw->adapter_stopped = false; 3650 ixgbe_stop_adapter(hw); 3651 if (hw->mac.type == ixgbe_mac_82599EB) 3652 ixgbe_stop_mac_link_on_d3_82599(hw); 3653 /* Turn off the laser - noop with no optics */ 3654 ixgbe_disable_tx_laser(hw); 3655 3656 /* Update the stack */ 3657 sc->link_up = false; 3658 ixgbe_if_update_admin_status(ctx); 3659 3660 /* reprogram the RAR[0] in case user changed it. */ 3661 ixgbe_set_rar(&sc->hw, 0, sc->hw.mac.addr, 0, IXGBE_RAH_AV); 3662 3663 return; 3664 } /* ixgbe_if_stop */ 3665 3666 /************************************************************************ 3667 * ixgbe_update_link_status - Update OS on link state 3668 * 3669 * Note: Only updates the OS on the cached link state. 3670 * The real check of the hardware only happens with 3671 * a link interrupt. 3672 ************************************************************************/ 3673 static void 3674 ixgbe_if_update_admin_status(if_ctx_t ctx) 3675 { 3676 struct ixgbe_softc *sc = iflib_get_softc(ctx); 3677 device_t dev = iflib_get_dev(ctx); 3678 3679 if (sc->link_up) { 3680 if (sc->link_active == false) { 3681 if (bootverbose) 3682 device_printf(dev, "Link is up %d Gbps %s \n", 3683 ((sc->link_speed == 128) ? 10 : 1), 3684 "Full Duplex"); 3685 sc->link_active = true; 3686 /* Update any Flow Control changes */ 3687 ixgbe_fc_enable(&sc->hw); 3688 /* Update DMA coalescing config */ 3689 ixgbe_config_dmac(sc); 3690 iflib_link_state_change(ctx, LINK_STATE_UP, 3691 ixgbe_link_speed_to_baudrate(sc->link_speed)); 3692 3693 if (sc->feat_en & IXGBE_FEATURE_SRIOV) 3694 ixgbe_ping_all_vfs(sc); 3695 } 3696 } else { /* Link down */ 3697 if (sc->link_active == true) { 3698 if (bootverbose) 3699 device_printf(dev, "Link is Down\n"); 3700 iflib_link_state_change(ctx, LINK_STATE_DOWN, 0); 3701 sc->link_active = false; 3702 if (sc->feat_en & IXGBE_FEATURE_SRIOV) 3703 ixgbe_ping_all_vfs(sc); 3704 } 3705 } 3706 3707 /* Handle task requests from msix_link() */ 3708 if (sc->task_requests & IXGBE_REQUEST_TASK_MOD) 3709 ixgbe_handle_mod(ctx); 3710 if (sc->task_requests & IXGBE_REQUEST_TASK_MSF) 3711 ixgbe_handle_msf(ctx); 3712 if (sc->task_requests & IXGBE_REQUEST_TASK_MBX) 3713 ixgbe_handle_mbx(ctx); 3714 if (sc->task_requests & IXGBE_REQUEST_TASK_FDIR) 3715 ixgbe_reinit_fdir(ctx); 3716 if (sc->task_requests & IXGBE_REQUEST_TASK_PHY) 3717 ixgbe_handle_phy(ctx); 3718 sc->task_requests = 0; 3719 3720 ixgbe_update_stats_counters(sc); 3721 } /* ixgbe_if_update_admin_status */ 3722 3723 /************************************************************************ 3724 * ixgbe_config_dmac - Configure DMA Coalescing 3725 ************************************************************************/ 3726 static void 3727 ixgbe_config_dmac(struct ixgbe_softc *sc) 3728 { 3729 struct ixgbe_hw *hw = &sc->hw; 3730 struct ixgbe_dmac_config *dcfg = &hw->mac.dmac_config; 3731 3732 if (hw->mac.type < ixgbe_mac_X550 || !hw->mac.ops.dmac_config) 3733 return; 3734 3735 if (dcfg->watchdog_timer ^ sc->dmac || 3736 dcfg->link_speed ^ sc->link_speed) { 3737 dcfg->watchdog_timer = sc->dmac; 3738 dcfg->fcoe_en = false; 3739 dcfg->link_speed = sc->link_speed; 3740 dcfg->num_tcs = 1; 3741 3742 INIT_DEBUGOUT2("dmac settings: watchdog %d, link speed %d\n", 3743 dcfg->watchdog_timer, dcfg->link_speed); 3744 3745 hw->mac.ops.dmac_config(hw); 3746 } 3747 } /* ixgbe_config_dmac */ 3748 3749 /************************************************************************ 3750 * ixgbe_if_enable_intr 3751 ************************************************************************/ 3752 void 3753 ixgbe_if_enable_intr(if_ctx_t ctx) 3754 { 3755 struct ixgbe_softc *sc = iflib_get_softc(ctx); 3756 struct ixgbe_hw *hw = &sc->hw; 3757 struct ix_rx_queue *que = sc->rx_queues; 3758 u32 mask, fwsm; 3759 3760 mask = (IXGBE_EIMS_ENABLE_MASK & ~IXGBE_EIMS_RTX_QUEUE); 3761 3762 switch (sc->hw.mac.type) { 3763 case ixgbe_mac_82599EB: 3764 mask |= IXGBE_EIMS_ECC; 3765 /* Temperature sensor on some scs */ 3766 mask |= IXGBE_EIMS_GPI_SDP0; 3767 /* SFP+ (RX_LOS_N & MOD_ABS_N) */ 3768 mask |= IXGBE_EIMS_GPI_SDP1; 3769 mask |= IXGBE_EIMS_GPI_SDP2; 3770 break; 3771 case ixgbe_mac_X540: 3772 /* Detect if Thermal Sensor is enabled */ 3773 fwsm = IXGBE_READ_REG(hw, IXGBE_FWSM); 3774 if (fwsm & IXGBE_FWSM_TS_ENABLED) 3775 mask |= IXGBE_EIMS_TS; 3776 mask |= IXGBE_EIMS_ECC; 3777 break; 3778 case ixgbe_mac_X550: 3779 /* MAC thermal sensor is automatically enabled */ 3780 mask |= IXGBE_EIMS_TS; 3781 mask |= IXGBE_EIMS_ECC; 3782 break; 3783 case ixgbe_mac_X550EM_x: 3784 case ixgbe_mac_X550EM_a: 3785 /* Some devices use SDP0 for important information */ 3786 if (hw->device_id == IXGBE_DEV_ID_X550EM_X_SFP || 3787 hw->device_id == IXGBE_DEV_ID_X550EM_A_SFP || 3788 hw->device_id == IXGBE_DEV_ID_X550EM_A_SFP_N || 3789 hw->device_id == IXGBE_DEV_ID_X550EM_X_10G_T) 3790 mask |= IXGBE_EIMS_GPI_SDP0_BY_MAC(hw); 3791 if (hw->phy.type == ixgbe_phy_x550em_ext_t) 3792 mask |= IXGBE_EICR_GPI_SDP0_X540; 3793 mask |= IXGBE_EIMS_ECC; 3794 break; 3795 default: 3796 break; 3797 } 3798 3799 /* Enable Fan Failure detection */ 3800 if (sc->feat_en & IXGBE_FEATURE_FAN_FAIL) 3801 mask |= IXGBE_EIMS_GPI_SDP1; 3802 /* Enable SR-IOV */ 3803 if (sc->feat_en & IXGBE_FEATURE_SRIOV) 3804 mask |= IXGBE_EIMS_MAILBOX; 3805 /* Enable Flow Director */ 3806 if (sc->feat_en & IXGBE_FEATURE_FDIR) 3807 mask |= IXGBE_EIMS_FLOW_DIR; 3808 3809 IXGBE_WRITE_REG(hw, IXGBE_EIMS, mask); 3810 3811 /* With MSI-X we use auto clear */ 3812 if (sc->intr_type == IFLIB_INTR_MSIX) { 3813 mask = IXGBE_EIMS_ENABLE_MASK; 3814 /* Don't autoclear Link */ 3815 mask &= ~IXGBE_EIMS_OTHER; 3816 mask &= ~IXGBE_EIMS_LSC; 3817 if (sc->feat_cap & IXGBE_FEATURE_SRIOV) 3818 mask &= ~IXGBE_EIMS_MAILBOX; 3819 IXGBE_WRITE_REG(hw, IXGBE_EIAC, mask); 3820 } 3821 3822 /* 3823 * Now enable all queues, this is done separately to 3824 * allow for handling the extended (beyond 32) MSI-X 3825 * vectors that can be used by 82599 3826 */ 3827 for (int i = 0; i < sc->num_rx_queues; i++, que++) 3828 ixgbe_enable_queue(sc, que->msix); 3829 3830 IXGBE_WRITE_FLUSH(hw); 3831 3832 } /* ixgbe_if_enable_intr */ 3833 3834 /************************************************************************ 3835 * ixgbe_disable_intr 3836 ************************************************************************/ 3837 static void 3838 ixgbe_if_disable_intr(if_ctx_t ctx) 3839 { 3840 struct ixgbe_softc *sc = iflib_get_softc(ctx); 3841 3842 if (sc->intr_type == IFLIB_INTR_MSIX) 3843 IXGBE_WRITE_REG(&sc->hw, IXGBE_EIAC, 0); 3844 if (sc->hw.mac.type == ixgbe_mac_82598EB) { 3845 IXGBE_WRITE_REG(&sc->hw, IXGBE_EIMC, ~0); 3846 } else { 3847 IXGBE_WRITE_REG(&sc->hw, IXGBE_EIMC, 0xFFFF0000); 3848 IXGBE_WRITE_REG(&sc->hw, IXGBE_EIMC_EX(0), ~0); 3849 IXGBE_WRITE_REG(&sc->hw, IXGBE_EIMC_EX(1), ~0); 3850 } 3851 IXGBE_WRITE_FLUSH(&sc->hw); 3852 3853 } /* ixgbe_if_disable_intr */ 3854 3855 /************************************************************************ 3856 * ixgbe_link_intr_enable 3857 ************************************************************************/ 3858 static void 3859 ixgbe_link_intr_enable(if_ctx_t ctx) 3860 { 3861 struct ixgbe_hw *hw = &((struct ixgbe_softc *)iflib_get_softc(ctx))->hw; 3862 3863 /* Re-enable other interrupts */ 3864 IXGBE_WRITE_REG(hw, IXGBE_EIMS, IXGBE_EIMS_OTHER | IXGBE_EIMS_LSC); 3865 } /* ixgbe_link_intr_enable */ 3866 3867 /************************************************************************ 3868 * ixgbe_if_rx_queue_intr_enable 3869 ************************************************************************/ 3870 static int 3871 ixgbe_if_rx_queue_intr_enable(if_ctx_t ctx, uint16_t rxqid) 3872 { 3873 struct ixgbe_softc *sc = iflib_get_softc(ctx); 3874 struct ix_rx_queue *que = &sc->rx_queues[rxqid]; 3875 3876 ixgbe_enable_queue(sc, que->msix); 3877 3878 return (0); 3879 } /* ixgbe_if_rx_queue_intr_enable */ 3880 3881 /************************************************************************ 3882 * ixgbe_enable_queue 3883 ************************************************************************/ 3884 static void 3885 ixgbe_enable_queue(struct ixgbe_softc *sc, u32 vector) 3886 { 3887 struct ixgbe_hw *hw = &sc->hw; 3888 u64 queue = 1ULL << vector; 3889 u32 mask; 3890 3891 if (hw->mac.type == ixgbe_mac_82598EB) { 3892 mask = (IXGBE_EIMS_RTX_QUEUE & queue); 3893 IXGBE_WRITE_REG(hw, IXGBE_EIMS, mask); 3894 } else { 3895 mask = (queue & 0xFFFFFFFF); 3896 if (mask) 3897 IXGBE_WRITE_REG(hw, IXGBE_EIMS_EX(0), mask); 3898 mask = (queue >> 32); 3899 if (mask) 3900 IXGBE_WRITE_REG(hw, IXGBE_EIMS_EX(1), mask); 3901 } 3902 } /* ixgbe_enable_queue */ 3903 3904 /************************************************************************ 3905 * ixgbe_disable_queue 3906 ************************************************************************/ 3907 static void 3908 ixgbe_disable_queue(struct ixgbe_softc *sc, u32 vector) 3909 { 3910 struct ixgbe_hw *hw = &sc->hw; 3911 u64 queue = 1ULL << vector; 3912 u32 mask; 3913 3914 if (hw->mac.type == ixgbe_mac_82598EB) { 3915 mask = (IXGBE_EIMS_RTX_QUEUE & queue); 3916 IXGBE_WRITE_REG(hw, IXGBE_EIMC, mask); 3917 } else { 3918 mask = (queue & 0xFFFFFFFF); 3919 if (mask) 3920 IXGBE_WRITE_REG(hw, IXGBE_EIMC_EX(0), mask); 3921 mask = (queue >> 32); 3922 if (mask) 3923 IXGBE_WRITE_REG(hw, IXGBE_EIMC_EX(1), mask); 3924 } 3925 } /* ixgbe_disable_queue */ 3926 3927 /************************************************************************ 3928 * ixgbe_intr - Legacy Interrupt Service Routine 3929 ************************************************************************/ 3930 int 3931 ixgbe_intr(void *arg) 3932 { 3933 struct ixgbe_softc *sc = arg; 3934 struct ix_rx_queue *que = sc->rx_queues; 3935 struct ixgbe_hw *hw = &sc->hw; 3936 if_ctx_t ctx = sc->ctx; 3937 u32 eicr, eicr_mask; 3938 3939 eicr = IXGBE_READ_REG(hw, IXGBE_EICR); 3940 3941 ++que->irqs; 3942 if (eicr == 0) { 3943 ixgbe_if_enable_intr(ctx); 3944 return (FILTER_HANDLED); 3945 } 3946 3947 /* Check for fan failure */ 3948 if ((hw->device_id == IXGBE_DEV_ID_82598AT) && 3949 (eicr & IXGBE_EICR_GPI_SDP1)) { 3950 device_printf(sc->dev, 3951 "\nCRITICAL: FAN FAILURE!! REPLACE IMMEDIATELY!!\n"); 3952 IXGBE_WRITE_REG(hw, IXGBE_EIMS, IXGBE_EICR_GPI_SDP1_BY_MAC(hw)); 3953 } 3954 3955 /* Link status change */ 3956 if (eicr & IXGBE_EICR_LSC) { 3957 IXGBE_WRITE_REG(hw, IXGBE_EIMC, IXGBE_EIMC_LSC); 3958 iflib_admin_intr_deferred(ctx); 3959 } 3960 3961 if (ixgbe_is_sfp(hw)) { 3962 /* Pluggable optics-related interrupt */ 3963 if (hw->mac.type >= ixgbe_mac_X540) 3964 eicr_mask = IXGBE_EICR_GPI_SDP0_X540; 3965 else 3966 eicr_mask = IXGBE_EICR_GPI_SDP2_BY_MAC(hw); 3967 3968 if (eicr & eicr_mask) { 3969 IXGBE_WRITE_REG(hw, IXGBE_EICR, eicr_mask); 3970 sc->task_requests |= IXGBE_REQUEST_TASK_MOD; 3971 } 3972 3973 if ((hw->mac.type == ixgbe_mac_82599EB) && 3974 (eicr & IXGBE_EICR_GPI_SDP1_BY_MAC(hw))) { 3975 IXGBE_WRITE_REG(hw, IXGBE_EICR, 3976 IXGBE_EICR_GPI_SDP1_BY_MAC(hw)); 3977 sc->task_requests |= IXGBE_REQUEST_TASK_MSF; 3978 } 3979 } 3980 3981 /* External PHY interrupt */ 3982 if ((hw->phy.type == ixgbe_phy_x550em_ext_t) && 3983 (eicr & IXGBE_EICR_GPI_SDP0_X540)) 3984 sc->task_requests |= IXGBE_REQUEST_TASK_PHY; 3985 3986 return (FILTER_SCHEDULE_THREAD); 3987 } /* ixgbe_intr */ 3988 3989 /************************************************************************ 3990 * ixgbe_free_pci_resources 3991 ************************************************************************/ 3992 static void 3993 ixgbe_free_pci_resources(if_ctx_t ctx) 3994 { 3995 struct ixgbe_softc *sc = iflib_get_softc(ctx); 3996 struct ix_rx_queue *que = sc->rx_queues; 3997 device_t dev = iflib_get_dev(ctx); 3998 3999 /* Release all MSI-X queue resources */ 4000 if (sc->intr_type == IFLIB_INTR_MSIX) 4001 iflib_irq_free(ctx, &sc->irq); 4002 4003 if (que != NULL) { 4004 for (int i = 0; i < sc->num_rx_queues; i++, que++) { 4005 iflib_irq_free(ctx, &que->que_irq); 4006 } 4007 } 4008 4009 if (sc->pci_mem != NULL) 4010 bus_release_resource(dev, SYS_RES_MEMORY, 4011 rman_get_rid(sc->pci_mem), sc->pci_mem); 4012 } /* ixgbe_free_pci_resources */ 4013 4014 /************************************************************************ 4015 * ixgbe_sysctl_flowcntl 4016 * 4017 * SYSCTL wrapper around setting Flow Control 4018 ************************************************************************/ 4019 static int 4020 ixgbe_sysctl_flowcntl(SYSCTL_HANDLER_ARGS) 4021 { 4022 struct ixgbe_softc *sc; 4023 int error, fc; 4024 4025 sc = (struct ixgbe_softc *)arg1; 4026 fc = sc->hw.fc.current_mode; 4027 4028 error = sysctl_handle_int(oidp, &fc, 0, req); 4029 if ((error) || (req->newptr == NULL)) 4030 return (error); 4031 4032 /* Don't bother if it's not changed */ 4033 if (fc == sc->hw.fc.current_mode) 4034 return (0); 4035 4036 return ixgbe_set_flowcntl(sc, fc); 4037 } /* ixgbe_sysctl_flowcntl */ 4038 4039 /************************************************************************ 4040 * ixgbe_set_flowcntl - Set flow control 4041 * 4042 * Flow control values: 4043 * 0 - off 4044 * 1 - rx pause 4045 * 2 - tx pause 4046 * 3 - full 4047 ************************************************************************/ 4048 static int 4049 ixgbe_set_flowcntl(struct ixgbe_softc *sc, int fc) 4050 { 4051 switch (fc) { 4052 case ixgbe_fc_rx_pause: 4053 case ixgbe_fc_tx_pause: 4054 case ixgbe_fc_full: 4055 sc->hw.fc.requested_mode = fc; 4056 if (sc->num_rx_queues > 1) 4057 ixgbe_disable_rx_drop(sc); 4058 break; 4059 case ixgbe_fc_none: 4060 sc->hw.fc.requested_mode = ixgbe_fc_none; 4061 if (sc->num_rx_queues > 1) 4062 ixgbe_enable_rx_drop(sc); 4063 break; 4064 default: 4065 return (EINVAL); 4066 } 4067 4068 /* Don't autoneg if forcing a value */ 4069 sc->hw.fc.disable_fc_autoneg = true; 4070 ixgbe_fc_enable(&sc->hw); 4071 4072 return (0); 4073 } /* ixgbe_set_flowcntl */ 4074 4075 /************************************************************************ 4076 * ixgbe_enable_rx_drop 4077 * 4078 * Enable the hardware to drop packets when the buffer is 4079 * full. This is useful with multiqueue, so that no single 4080 * queue being full stalls the entire RX engine. We only 4081 * enable this when Multiqueue is enabled AND Flow Control 4082 * is disabled. 4083 ************************************************************************/ 4084 static void 4085 ixgbe_enable_rx_drop(struct ixgbe_softc *sc) 4086 { 4087 struct ixgbe_hw *hw = &sc->hw; 4088 struct rx_ring *rxr; 4089 u32 srrctl; 4090 4091 for (int i = 0; i < sc->num_rx_queues; i++) { 4092 rxr = &sc->rx_queues[i].rxr; 4093 srrctl = IXGBE_READ_REG(hw, IXGBE_SRRCTL(rxr->me)); 4094 srrctl |= IXGBE_SRRCTL_DROP_EN; 4095 IXGBE_WRITE_REG(hw, IXGBE_SRRCTL(rxr->me), srrctl); 4096 } 4097 4098 /* enable drop for each vf */ 4099 for (int i = 0; i < sc->num_vfs; i++) { 4100 IXGBE_WRITE_REG(hw, IXGBE_QDE, 4101 (IXGBE_QDE_WRITE | (i << IXGBE_QDE_IDX_SHIFT) | 4102 IXGBE_QDE_ENABLE)); 4103 } 4104 } /* ixgbe_enable_rx_drop */ 4105 4106 /************************************************************************ 4107 * ixgbe_disable_rx_drop 4108 ************************************************************************/ 4109 static void 4110 ixgbe_disable_rx_drop(struct ixgbe_softc *sc) 4111 { 4112 struct ixgbe_hw *hw = &sc->hw; 4113 struct rx_ring *rxr; 4114 u32 srrctl; 4115 4116 for (int i = 0; i < sc->num_rx_queues; i++) { 4117 rxr = &sc->rx_queues[i].rxr; 4118 srrctl = IXGBE_READ_REG(hw, IXGBE_SRRCTL(rxr->me)); 4119 srrctl &= ~IXGBE_SRRCTL_DROP_EN; 4120 IXGBE_WRITE_REG(hw, IXGBE_SRRCTL(rxr->me), srrctl); 4121 } 4122 4123 /* disable drop for each vf */ 4124 for (int i = 0; i < sc->num_vfs; i++) { 4125 IXGBE_WRITE_REG(hw, IXGBE_QDE, 4126 (IXGBE_QDE_WRITE | (i << IXGBE_QDE_IDX_SHIFT))); 4127 } 4128 } /* ixgbe_disable_rx_drop */ 4129 4130 /************************************************************************ 4131 * ixgbe_sysctl_advertise 4132 * 4133 * SYSCTL wrapper around setting advertised speed 4134 ************************************************************************/ 4135 static int 4136 ixgbe_sysctl_advertise(SYSCTL_HANDLER_ARGS) 4137 { 4138 struct ixgbe_softc *sc; 4139 int error, advertise; 4140 4141 sc = (struct ixgbe_softc *)arg1; 4142 advertise = sc->advertise; 4143 4144 error = sysctl_handle_int(oidp, &advertise, 0, req); 4145 if ((error) || (req->newptr == NULL)) 4146 return (error); 4147 4148 return ixgbe_set_advertise(sc, advertise); 4149 } /* ixgbe_sysctl_advertise */ 4150 4151 /************************************************************************ 4152 * ixgbe_set_advertise - Control advertised link speed 4153 * 4154 * Flags: 4155 * 0x1 - advertise 100 Mb 4156 * 0x2 - advertise 1G 4157 * 0x4 - advertise 10G 4158 * 0x8 - advertise 10 Mb (yes, Mb) 4159 * 0x10 - advertise 2.5G (disabled by default) 4160 * 0x20 - advertise 5G (disabled by default) 4161 * 4162 ************************************************************************/ 4163 static int 4164 ixgbe_set_advertise(struct ixgbe_softc *sc, int advertise) 4165 { 4166 device_t dev = iflib_get_dev(sc->ctx); 4167 struct ixgbe_hw *hw; 4168 ixgbe_link_speed speed = 0; 4169 ixgbe_link_speed link_caps = 0; 4170 s32 err = IXGBE_NOT_IMPLEMENTED; 4171 bool negotiate = false; 4172 4173 /* Checks to validate new value */ 4174 if (sc->advertise == advertise) /* no change */ 4175 return (0); 4176 4177 hw = &sc->hw; 4178 4179 /* No speed changes for backplane media */ 4180 if (hw->phy.media_type == ixgbe_media_type_backplane) 4181 return (ENODEV); 4182 4183 if (!((hw->phy.media_type == ixgbe_media_type_copper) || 4184 (hw->phy.multispeed_fiber))) { 4185 device_printf(dev, "Advertised speed can only be set on copper or multispeed fiber media types.\n"); 4186 return (EINVAL); 4187 } 4188 4189 if (advertise < 0x1 || advertise > 0x3F) { 4190 device_printf(dev, "Invalid advertised speed; valid modes are 0x1 through 0x3F\n"); 4191 return (EINVAL); 4192 } 4193 4194 if (hw->mac.ops.get_link_capabilities) { 4195 err = hw->mac.ops.get_link_capabilities(hw, &link_caps, 4196 &negotiate); 4197 if (err != IXGBE_SUCCESS) { 4198 device_printf(dev, "Unable to determine supported advertise speeds\n"); 4199 return (ENODEV); 4200 } 4201 } 4202 4203 /* Set new value and report new advertised mode */ 4204 if (advertise & 0x1) { 4205 if (!(link_caps & IXGBE_LINK_SPEED_100_FULL)) { 4206 device_printf(dev, "Interface does not support 100Mb advertised speed\n"); 4207 return (EINVAL); 4208 } 4209 speed |= IXGBE_LINK_SPEED_100_FULL; 4210 } 4211 if (advertise & 0x2) { 4212 if (!(link_caps & IXGBE_LINK_SPEED_1GB_FULL)) { 4213 device_printf(dev, "Interface does not support 1Gb advertised speed\n"); 4214 return (EINVAL); 4215 } 4216 speed |= IXGBE_LINK_SPEED_1GB_FULL; 4217 } 4218 if (advertise & 0x4) { 4219 if (!(link_caps & IXGBE_LINK_SPEED_10GB_FULL)) { 4220 device_printf(dev, "Interface does not support 10Gb advertised speed\n"); 4221 return (EINVAL); 4222 } 4223 speed |= IXGBE_LINK_SPEED_10GB_FULL; 4224 } 4225 if (advertise & 0x8) { 4226 if (!(link_caps & IXGBE_LINK_SPEED_10_FULL)) { 4227 device_printf(dev, "Interface does not support 10Mb advertised speed\n"); 4228 return (EINVAL); 4229 } 4230 speed |= IXGBE_LINK_SPEED_10_FULL; 4231 } 4232 if (advertise & 0x10) { 4233 if (!(link_caps & IXGBE_LINK_SPEED_2_5GB_FULL)) { 4234 device_printf(dev, "Interface does not support 2.5G advertised speed\n"); 4235 return (EINVAL); 4236 } 4237 speed |= IXGBE_LINK_SPEED_2_5GB_FULL; 4238 } 4239 if (advertise & 0x20) { 4240 if (!(link_caps & IXGBE_LINK_SPEED_5GB_FULL)) { 4241 device_printf(dev, "Interface does not support 5G advertised speed\n"); 4242 return (EINVAL); 4243 } 4244 speed |= IXGBE_LINK_SPEED_5GB_FULL; 4245 } 4246 4247 hw->mac.autotry_restart = true; 4248 hw->mac.ops.setup_link(hw, speed, true); 4249 sc->advertise = advertise; 4250 4251 return (0); 4252 } /* ixgbe_set_advertise */ 4253 4254 /************************************************************************ 4255 * ixgbe_get_default_advertise - Get default advertised speed settings 4256 * 4257 * Formatted for sysctl usage. 4258 * Flags: 4259 * 0x1 - advertise 100 Mb 4260 * 0x2 - advertise 1G 4261 * 0x4 - advertise 10G 4262 * 0x8 - advertise 10 Mb (yes, Mb) 4263 * 0x10 - advertise 2.5G (disabled by default) 4264 * 0x20 - advertise 5G (disabled by default) 4265 ************************************************************************/ 4266 static int 4267 ixgbe_get_default_advertise(struct ixgbe_softc *sc) 4268 { 4269 struct ixgbe_hw *hw = &sc->hw; 4270 int speed; 4271 ixgbe_link_speed link_caps = 0; 4272 s32 err; 4273 bool negotiate = false; 4274 4275 /* 4276 * Advertised speed means nothing unless it's copper or 4277 * multi-speed fiber 4278 */ 4279 if (!(hw->phy.media_type == ixgbe_media_type_copper) && 4280 !(hw->phy.multispeed_fiber)) 4281 return (0); 4282 4283 err = hw->mac.ops.get_link_capabilities(hw, &link_caps, &negotiate); 4284 if (err != IXGBE_SUCCESS) 4285 return (0); 4286 4287 if (hw->mac.type == ixgbe_mac_X550) { 4288 /* 4289 * 2.5G and 5G autonegotiation speeds on X550 4290 * are disabled by default due to reported 4291 * interoperability issues with some switches. 4292 */ 4293 link_caps &= ~(IXGBE_LINK_SPEED_2_5GB_FULL | 4294 IXGBE_LINK_SPEED_5GB_FULL); 4295 } 4296 4297 speed = 4298 ((link_caps & IXGBE_LINK_SPEED_10GB_FULL) ? 0x4 : 0) | 4299 ((link_caps & IXGBE_LINK_SPEED_5GB_FULL) ? 0x20 : 0) | 4300 ((link_caps & IXGBE_LINK_SPEED_2_5GB_FULL) ? 0x10 : 0) | 4301 ((link_caps & IXGBE_LINK_SPEED_1GB_FULL) ? 0x2 : 0) | 4302 ((link_caps & IXGBE_LINK_SPEED_100_FULL) ? 0x1 : 0) | 4303 ((link_caps & IXGBE_LINK_SPEED_10_FULL) ? 0x8 : 0); 4304 4305 return speed; 4306 } /* ixgbe_get_default_advertise */ 4307 4308 /************************************************************************ 4309 * ixgbe_sysctl_dmac - Manage DMA Coalescing 4310 * 4311 * Control values: 4312 * 0/1 - off / on (use default value of 1000) 4313 * 4314 * Legal timer values are: 4315 * 50,100,250,500,1000,2000,5000,10000 4316 * 4317 * Turning off interrupt moderation will also turn this off. 4318 ************************************************************************/ 4319 static int 4320 ixgbe_sysctl_dmac(SYSCTL_HANDLER_ARGS) 4321 { 4322 struct ixgbe_softc *sc = (struct ixgbe_softc *)arg1; 4323 if_t ifp = iflib_get_ifp(sc->ctx); 4324 int error; 4325 u16 newval; 4326 4327 newval = sc->dmac; 4328 error = sysctl_handle_16(oidp, &newval, 0, req); 4329 if ((error) || (req->newptr == NULL)) 4330 return (error); 4331 4332 switch (newval) { 4333 case 0: 4334 /* Disabled */ 4335 sc->dmac = 0; 4336 break; 4337 case 1: 4338 /* Enable and use default */ 4339 sc->dmac = 1000; 4340 break; 4341 case 50: 4342 case 100: 4343 case 250: 4344 case 500: 4345 case 1000: 4346 case 2000: 4347 case 5000: 4348 case 10000: 4349 /* Legal values - allow */ 4350 sc->dmac = newval; 4351 break; 4352 default: 4353 /* Do nothing, illegal value */ 4354 return (EINVAL); 4355 } 4356 4357 /* Re-initialize hardware if it's already running */ 4358 if (if_getdrvflags(ifp) & IFF_DRV_RUNNING) 4359 if_init(ifp, ifp); 4360 4361 return (0); 4362 } /* ixgbe_sysctl_dmac */ 4363 4364 #ifdef IXGBE_DEBUG 4365 /************************************************************************ 4366 * ixgbe_sysctl_power_state 4367 * 4368 * Sysctl to test power states 4369 * Values: 4370 * 0 - set device to D0 4371 * 3 - set device to D3 4372 * (none) - get current device power state 4373 ************************************************************************/ 4374 static int 4375 ixgbe_sysctl_power_state(SYSCTL_HANDLER_ARGS) 4376 { 4377 struct ixgbe_softc *sc = (struct ixgbe_softc *)arg1; 4378 device_t dev = sc->dev; 4379 int curr_ps, new_ps, error = 0; 4380 4381 curr_ps = new_ps = pci_get_powerstate(dev); 4382 4383 error = sysctl_handle_int(oidp, &new_ps, 0, req); 4384 if ((error) || (req->newptr == NULL)) 4385 return (error); 4386 4387 if (new_ps == curr_ps) 4388 return (0); 4389 4390 if (new_ps == 3 && curr_ps == 0) 4391 error = DEVICE_SUSPEND(dev); 4392 else if (new_ps == 0 && curr_ps == 3) 4393 error = DEVICE_RESUME(dev); 4394 else 4395 return (EINVAL); 4396 4397 device_printf(dev, "New state: %d\n", pci_get_powerstate(dev)); 4398 4399 return (error); 4400 } /* ixgbe_sysctl_power_state */ 4401 #endif 4402 4403 /************************************************************************ 4404 * ixgbe_sysctl_wol_enable 4405 * 4406 * Sysctl to enable/disable the WoL capability, 4407 * if supported by the adapter. 4408 * 4409 * Values: 4410 * 0 - disabled 4411 * 1 - enabled 4412 ************************************************************************/ 4413 static int 4414 ixgbe_sysctl_wol_enable(SYSCTL_HANDLER_ARGS) 4415 { 4416 struct ixgbe_softc *sc = (struct ixgbe_softc *)arg1; 4417 struct ixgbe_hw *hw = &sc->hw; 4418 int new_wol_enabled; 4419 int error = 0; 4420 4421 new_wol_enabled = hw->wol_enabled; 4422 error = sysctl_handle_int(oidp, &new_wol_enabled, 0, req); 4423 if ((error) || (req->newptr == NULL)) 4424 return (error); 4425 new_wol_enabled = !!(new_wol_enabled); 4426 if (new_wol_enabled == hw->wol_enabled) 4427 return (0); 4428 4429 if (new_wol_enabled > 0 && !sc->wol_support) 4430 return (ENODEV); 4431 else 4432 hw->wol_enabled = new_wol_enabled; 4433 4434 return (0); 4435 } /* ixgbe_sysctl_wol_enable */ 4436 4437 /************************************************************************ 4438 * ixgbe_sysctl_wufc - Wake Up Filter Control 4439 * 4440 * Sysctl to enable/disable the types of packets that the 4441 * adapter will wake up on upon receipt. 4442 * Flags: 4443 * 0x1 - Link Status Change 4444 * 0x2 - Magic Packet 4445 * 0x4 - Direct Exact 4446 * 0x8 - Directed Multicast 4447 * 0x10 - Broadcast 4448 * 0x20 - ARP/IPv4 Request Packet 4449 * 0x40 - Direct IPv4 Packet 4450 * 0x80 - Direct IPv6 Packet 4451 * 4452 * Settings not listed above will cause the sysctl to return an error. 4453 ************************************************************************/ 4454 static int 4455 ixgbe_sysctl_wufc(SYSCTL_HANDLER_ARGS) 4456 { 4457 struct ixgbe_softc *sc = (struct ixgbe_softc *)arg1; 4458 int error = 0; 4459 u32 new_wufc; 4460 4461 new_wufc = sc->wufc; 4462 4463 error = sysctl_handle_32(oidp, &new_wufc, 0, req); 4464 if ((error) || (req->newptr == NULL)) 4465 return (error); 4466 if (new_wufc == sc->wufc) 4467 return (0); 4468 4469 if (new_wufc & 0xffffff00) 4470 return (EINVAL); 4471 4472 new_wufc &= 0xff; 4473 new_wufc |= (0xffffff & sc->wufc); 4474 sc->wufc = new_wufc; 4475 4476 return (0); 4477 } /* ixgbe_sysctl_wufc */ 4478 4479 #ifdef IXGBE_DEBUG 4480 /************************************************************************ 4481 * ixgbe_sysctl_print_rss_config 4482 ************************************************************************/ 4483 static int 4484 ixgbe_sysctl_print_rss_config(SYSCTL_HANDLER_ARGS) 4485 { 4486 struct ixgbe_softc *sc = (struct ixgbe_softc *)arg1; 4487 struct ixgbe_hw *hw = &sc->hw; 4488 device_t dev = sc->dev; 4489 struct sbuf *buf; 4490 int error = 0, reta_size; 4491 u32 reg; 4492 4493 buf = sbuf_new_for_sysctl(NULL, NULL, 128, req); 4494 if (!buf) { 4495 device_printf(dev, "Could not allocate sbuf for output.\n"); 4496 return (ENOMEM); 4497 } 4498 4499 // TODO: use sbufs to make a string to print out 4500 /* Set multiplier for RETA setup and table size based on MAC */ 4501 switch (sc->hw.mac.type) { 4502 case ixgbe_mac_X550: 4503 case ixgbe_mac_X550EM_x: 4504 case ixgbe_mac_X550EM_a: 4505 reta_size = 128; 4506 break; 4507 default: 4508 reta_size = 32; 4509 break; 4510 } 4511 4512 /* Print out the redirection table */ 4513 sbuf_cat(buf, "\n"); 4514 for (int i = 0; i < reta_size; i++) { 4515 if (i < 32) { 4516 reg = IXGBE_READ_REG(hw, IXGBE_RETA(i)); 4517 sbuf_printf(buf, "RETA(%2d): 0x%08x\n", i, reg); 4518 } else { 4519 reg = IXGBE_READ_REG(hw, IXGBE_ERETA(i - 32)); 4520 sbuf_printf(buf, "ERETA(%2d): 0x%08x\n", i - 32, reg); 4521 } 4522 } 4523 4524 // TODO: print more config 4525 4526 error = sbuf_finish(buf); 4527 if (error) 4528 device_printf(dev, "Error finishing sbuf: %d\n", error); 4529 4530 sbuf_delete(buf); 4531 4532 return (0); 4533 } /* ixgbe_sysctl_print_rss_config */ 4534 #endif /* IXGBE_DEBUG */ 4535 4536 /************************************************************************ 4537 * ixgbe_sysctl_phy_temp - Retrieve temperature of PHY 4538 * 4539 * For X552/X557-AT devices using an external PHY 4540 ************************************************************************/ 4541 static int 4542 ixgbe_sysctl_phy_temp(SYSCTL_HANDLER_ARGS) 4543 { 4544 struct ixgbe_softc *sc = (struct ixgbe_softc *)arg1; 4545 struct ixgbe_hw *hw = &sc->hw; 4546 u16 reg; 4547 4548 if (hw->device_id != IXGBE_DEV_ID_X550EM_X_10G_T) { 4549 device_printf(iflib_get_dev(sc->ctx), 4550 "Device has no supported external thermal sensor.\n"); 4551 return (ENODEV); 4552 } 4553 4554 if (hw->phy.ops.read_reg(hw, IXGBE_PHY_CURRENT_TEMP, 4555 IXGBE_MDIO_VENDOR_SPECIFIC_1_DEV_TYPE, ®)) { 4556 device_printf(iflib_get_dev(sc->ctx), 4557 "Error reading from PHY's current temperature register\n"); 4558 return (EAGAIN); 4559 } 4560 4561 /* Shift temp for output */ 4562 reg = reg >> 8; 4563 4564 return (sysctl_handle_16(oidp, NULL, reg, req)); 4565 } /* ixgbe_sysctl_phy_temp */ 4566 4567 /************************************************************************ 4568 * ixgbe_sysctl_phy_overtemp_occurred 4569 * 4570 * Reports (directly from the PHY) whether the current PHY 4571 * temperature is over the overtemp threshold. 4572 ************************************************************************/ 4573 static int 4574 ixgbe_sysctl_phy_overtemp_occurred(SYSCTL_HANDLER_ARGS) 4575 { 4576 struct ixgbe_softc *sc = (struct ixgbe_softc *)arg1; 4577 struct ixgbe_hw *hw = &sc->hw; 4578 u16 reg; 4579 4580 if (hw->device_id != IXGBE_DEV_ID_X550EM_X_10G_T) { 4581 device_printf(iflib_get_dev(sc->ctx), 4582 "Device has no supported external thermal sensor.\n"); 4583 return (ENODEV); 4584 } 4585 4586 if (hw->phy.ops.read_reg(hw, IXGBE_PHY_OVERTEMP_STATUS, 4587 IXGBE_MDIO_VENDOR_SPECIFIC_1_DEV_TYPE, ®)) { 4588 device_printf(iflib_get_dev(sc->ctx), 4589 "Error reading from PHY's temperature status register\n"); 4590 return (EAGAIN); 4591 } 4592 4593 /* Get occurrence bit */ 4594 reg = !!(reg & 0x4000); 4595 4596 return (sysctl_handle_16(oidp, 0, reg, req)); 4597 } /* ixgbe_sysctl_phy_overtemp_occurred */ 4598 4599 /************************************************************************ 4600 * ixgbe_sysctl_eee_state 4601 * 4602 * Sysctl to set EEE power saving feature 4603 * Values: 4604 * 0 - disable EEE 4605 * 1 - enable EEE 4606 * (none) - get current device EEE state 4607 ************************************************************************/ 4608 static int 4609 ixgbe_sysctl_eee_state(SYSCTL_HANDLER_ARGS) 4610 { 4611 struct ixgbe_softc *sc = (struct ixgbe_softc *)arg1; 4612 device_t dev = sc->dev; 4613 if_t ifp = iflib_get_ifp(sc->ctx); 4614 int curr_eee, new_eee, error = 0; 4615 s32 retval; 4616 4617 curr_eee = new_eee = !!(sc->feat_en & IXGBE_FEATURE_EEE); 4618 4619 error = sysctl_handle_int(oidp, &new_eee, 0, req); 4620 if ((error) || (req->newptr == NULL)) 4621 return (error); 4622 4623 /* Nothing to do */ 4624 if (new_eee == curr_eee) 4625 return (0); 4626 4627 /* Not supported */ 4628 if (!(sc->feat_cap & IXGBE_FEATURE_EEE)) 4629 return (EINVAL); 4630 4631 /* Bounds checking */ 4632 if ((new_eee < 0) || (new_eee > 1)) 4633 return (EINVAL); 4634 4635 retval = ixgbe_setup_eee(&sc->hw, new_eee); 4636 if (retval) { 4637 device_printf(dev, "Error in EEE setup: 0x%08X\n", retval); 4638 return (EINVAL); 4639 } 4640 4641 /* Restart auto-neg */ 4642 if_init(ifp, ifp); 4643 4644 device_printf(dev, "New EEE state: %d\n", new_eee); 4645 4646 /* Cache new value */ 4647 if (new_eee) 4648 sc->feat_en |= IXGBE_FEATURE_EEE; 4649 else 4650 sc->feat_en &= ~IXGBE_FEATURE_EEE; 4651 4652 return (error); 4653 } /* ixgbe_sysctl_eee_state */ 4654 4655 /************************************************************************ 4656 * ixgbe_init_device_features 4657 ************************************************************************/ 4658 static void 4659 ixgbe_init_device_features(struct ixgbe_softc *sc) 4660 { 4661 sc->feat_cap = IXGBE_FEATURE_NETMAP 4662 | IXGBE_FEATURE_RSS 4663 | IXGBE_FEATURE_MSI 4664 | IXGBE_FEATURE_MSIX 4665 | IXGBE_FEATURE_LEGACY_IRQ; 4666 4667 /* Set capabilities first... */ 4668 switch (sc->hw.mac.type) { 4669 case ixgbe_mac_82598EB: 4670 if (sc->hw.device_id == IXGBE_DEV_ID_82598AT) 4671 sc->feat_cap |= IXGBE_FEATURE_FAN_FAIL; 4672 break; 4673 case ixgbe_mac_X540: 4674 sc->feat_cap |= IXGBE_FEATURE_SRIOV; 4675 sc->feat_cap |= IXGBE_FEATURE_FDIR; 4676 if ((sc->hw.device_id == IXGBE_DEV_ID_X540_BYPASS) && 4677 (sc->hw.bus.func == 0)) 4678 sc->feat_cap |= IXGBE_FEATURE_BYPASS; 4679 break; 4680 case ixgbe_mac_X550: 4681 sc->feat_cap |= IXGBE_FEATURE_TEMP_SENSOR; 4682 sc->feat_cap |= IXGBE_FEATURE_SRIOV; 4683 sc->feat_cap |= IXGBE_FEATURE_FDIR; 4684 break; 4685 case ixgbe_mac_X550EM_x: 4686 sc->feat_cap |= IXGBE_FEATURE_SRIOV; 4687 sc->feat_cap |= IXGBE_FEATURE_FDIR; 4688 break; 4689 case ixgbe_mac_X550EM_a: 4690 sc->feat_cap |= IXGBE_FEATURE_SRIOV; 4691 sc->feat_cap |= IXGBE_FEATURE_FDIR; 4692 sc->feat_cap &= ~IXGBE_FEATURE_LEGACY_IRQ; 4693 if ((sc->hw.device_id == IXGBE_DEV_ID_X550EM_A_1G_T) || 4694 (sc->hw.device_id == IXGBE_DEV_ID_X550EM_A_1G_T_L)) { 4695 sc->feat_cap |= IXGBE_FEATURE_TEMP_SENSOR; 4696 sc->feat_cap |= IXGBE_FEATURE_EEE; 4697 } 4698 break; 4699 case ixgbe_mac_82599EB: 4700 sc->feat_cap |= IXGBE_FEATURE_SRIOV; 4701 sc->feat_cap |= IXGBE_FEATURE_FDIR; 4702 if ((sc->hw.device_id == IXGBE_DEV_ID_82599_BYPASS) && 4703 (sc->hw.bus.func == 0)) 4704 sc->feat_cap |= IXGBE_FEATURE_BYPASS; 4705 if (sc->hw.device_id == IXGBE_DEV_ID_82599_QSFP_SF_QP) 4706 sc->feat_cap &= ~IXGBE_FEATURE_LEGACY_IRQ; 4707 break; 4708 default: 4709 break; 4710 } 4711 4712 /* Enabled by default... */ 4713 /* Fan failure detection */ 4714 if (sc->feat_cap & IXGBE_FEATURE_FAN_FAIL) 4715 sc->feat_en |= IXGBE_FEATURE_FAN_FAIL; 4716 /* Netmap */ 4717 if (sc->feat_cap & IXGBE_FEATURE_NETMAP) 4718 sc->feat_en |= IXGBE_FEATURE_NETMAP; 4719 /* EEE */ 4720 if (sc->feat_cap & IXGBE_FEATURE_EEE) 4721 sc->feat_en |= IXGBE_FEATURE_EEE; 4722 /* Thermal Sensor */ 4723 if (sc->feat_cap & IXGBE_FEATURE_TEMP_SENSOR) 4724 sc->feat_en |= IXGBE_FEATURE_TEMP_SENSOR; 4725 4726 /* Enabled via global sysctl... */ 4727 /* Flow Director */ 4728 if (ixgbe_enable_fdir) { 4729 if (sc->feat_cap & IXGBE_FEATURE_FDIR) 4730 sc->feat_en |= IXGBE_FEATURE_FDIR; 4731 else 4732 device_printf(sc->dev, "Device does not support Flow Director. Leaving disabled."); 4733 } 4734 /* 4735 * Message Signal Interrupts - Extended (MSI-X) 4736 * Normal MSI is only enabled if MSI-X calls fail. 4737 */ 4738 if (!ixgbe_enable_msix) 4739 sc->feat_cap &= ~IXGBE_FEATURE_MSIX; 4740 /* Receive-Side Scaling (RSS) */ 4741 if ((sc->feat_cap & IXGBE_FEATURE_RSS) && ixgbe_enable_rss) 4742 sc->feat_en |= IXGBE_FEATURE_RSS; 4743 4744 /* Disable features with unmet dependencies... */ 4745 /* No MSI-X */ 4746 if (!(sc->feat_cap & IXGBE_FEATURE_MSIX)) { 4747 sc->feat_cap &= ~IXGBE_FEATURE_RSS; 4748 sc->feat_cap &= ~IXGBE_FEATURE_SRIOV; 4749 sc->feat_en &= ~IXGBE_FEATURE_RSS; 4750 sc->feat_en &= ~IXGBE_FEATURE_SRIOV; 4751 } 4752 } /* ixgbe_init_device_features */ 4753 4754 /************************************************************************ 4755 * ixgbe_check_fan_failure 4756 ************************************************************************/ 4757 static void 4758 ixgbe_check_fan_failure(struct ixgbe_softc *sc, u32 reg, bool in_interrupt) 4759 { 4760 u32 mask; 4761 4762 mask = (in_interrupt) ? IXGBE_EICR_GPI_SDP1_BY_MAC(&sc->hw) : 4763 IXGBE_ESDP_SDP1; 4764 4765 if (reg & mask) 4766 device_printf(sc->dev, "\nCRITICAL: FAN FAILURE!! REPLACE IMMEDIATELY!!\n"); 4767 } /* ixgbe_check_fan_failure */ 4768 4769 /************************************************************************ 4770 * ixgbe_sbuf_fw_version 4771 ************************************************************************/ 4772 static void 4773 ixgbe_sbuf_fw_version(struct ixgbe_hw *hw, struct sbuf *buf) 4774 { 4775 struct ixgbe_nvm_version nvm_ver = {0}; 4776 uint16_t phyfw = 0; 4777 int status; 4778 const char *space = ""; 4779 4780 ixgbe_get_oem_prod_version(hw, &nvm_ver); /* OEM's NVM version */ 4781 ixgbe_get_orom_version(hw, &nvm_ver); /* Option ROM */ 4782 ixgbe_get_etk_id(hw, &nvm_ver); /* eTrack identifies a build in Intel's SCM */ 4783 status = ixgbe_get_phy_firmware_version(hw, &phyfw); 4784 4785 if (nvm_ver.oem_valid) { 4786 sbuf_printf(buf, "NVM OEM V%d.%d R%d", nvm_ver.oem_major, 4787 nvm_ver.oem_minor, nvm_ver.oem_release); 4788 space = " "; 4789 } 4790 4791 if (nvm_ver.or_valid) { 4792 sbuf_printf(buf, "%sOption ROM V%d-b%d-p%d", 4793 space, nvm_ver.or_major, nvm_ver.or_build, nvm_ver.or_patch); 4794 space = " "; 4795 } 4796 4797 if (nvm_ver.etk_id != ((NVM_VER_INVALID << NVM_ETK_SHIFT) | 4798 NVM_VER_INVALID)) { 4799 sbuf_printf(buf, "%seTrack 0x%08x", space, nvm_ver.etk_id); 4800 space = " "; 4801 } 4802 4803 if (phyfw != 0 && status == IXGBE_SUCCESS) 4804 sbuf_printf(buf, "%sPHY FW V%d", space, phyfw); 4805 } /* ixgbe_sbuf_fw_version */ 4806 4807 /************************************************************************ 4808 * ixgbe_print_fw_version 4809 ************************************************************************/ 4810 static void 4811 ixgbe_print_fw_version(if_ctx_t ctx) 4812 { 4813 struct ixgbe_softc *sc = iflib_get_softc(ctx); 4814 struct ixgbe_hw *hw = &sc->hw; 4815 device_t dev = sc->dev; 4816 struct sbuf *buf; 4817 int error = 0; 4818 4819 buf = sbuf_new_auto(); 4820 if (!buf) { 4821 device_printf(dev, "Could not allocate sbuf for output.\n"); 4822 return; 4823 } 4824 4825 ixgbe_sbuf_fw_version(hw, buf); 4826 4827 error = sbuf_finish(buf); 4828 if (error) 4829 device_printf(dev, "Error finishing sbuf: %d\n", error); 4830 else if (sbuf_len(buf)) 4831 device_printf(dev, "%s\n", sbuf_data(buf)); 4832 4833 sbuf_delete(buf); 4834 } /* ixgbe_print_fw_version */ 4835 4836 /************************************************************************ 4837 * ixgbe_sysctl_print_fw_version 4838 ************************************************************************/ 4839 static int 4840 ixgbe_sysctl_print_fw_version(SYSCTL_HANDLER_ARGS) 4841 { 4842 struct ixgbe_softc *sc = (struct ixgbe_softc *)arg1; 4843 struct ixgbe_hw *hw = &sc->hw; 4844 device_t dev = sc->dev; 4845 struct sbuf *buf; 4846 int error = 0; 4847 4848 buf = sbuf_new_for_sysctl(NULL, NULL, 128, req); 4849 if (!buf) { 4850 device_printf(dev, "Could not allocate sbuf for output.\n"); 4851 return (ENOMEM); 4852 } 4853 4854 ixgbe_sbuf_fw_version(hw, buf); 4855 4856 error = sbuf_finish(buf); 4857 if (error) 4858 device_printf(dev, "Error finishing sbuf: %d\n", error); 4859 4860 sbuf_delete(buf); 4861 4862 return (0); 4863 } /* ixgbe_sysctl_print_fw_version */ 4864