1 /****************************************************************************** 2 3 Copyright (c) 2001-2017, Intel Corporation 4 All rights reserved. 5 6 Redistribution and use in source and binary forms, with or without 7 modification, are permitted provided that the following conditions are met: 8 9 1. Redistributions of source code must retain the above copyright notice, 10 this list of conditions and the following disclaimer. 11 12 2. Redistributions in binary form must reproduce the above copyright 13 notice, this list of conditions and the following disclaimer in the 14 documentation and/or other materials provided with the distribution. 15 16 3. Neither the name of the Intel Corporation nor the names of its 17 contributors may be used to endorse or promote products derived from 18 this software without specific prior written permission. 19 20 THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 21 AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 22 IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 23 ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE 24 LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 25 CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 26 SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 27 INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 28 CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 29 ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 30 POSSIBILITY OF SUCH DAMAGE. 31 32 ******************************************************************************/ 33 34 #include "opt_inet.h" 35 #include "opt_inet6.h" 36 #include "opt_rss.h" 37 38 #include "ixgbe.h" 39 #include "ixgbe_sriov.h" 40 #include "ifdi_if.h" 41 42 #include <net/netmap.h> 43 #include <dev/netmap/netmap_kern.h> 44 45 /************************************************************************ 46 * Driver version 47 ************************************************************************/ 48 static const char ixgbe_driver_version[] = "4.0.1-k"; 49 50 /************************************************************************ 51 * PCI Device ID Table 52 * 53 * Used by probe to select devices to load on 54 * Last field stores an index into ixgbe_strings 55 * Last entry must be all 0s 56 * 57 * { Vendor ID, Device ID, SubVendor ID, SubDevice ID, String Index } 58 ************************************************************************/ 59 static const pci_vendor_info_t ixgbe_vendor_info_array[] = 60 { 61 PVID(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82598AF_DUAL_PORT, "Intel(R) 82598EB AF (Dual Fiber)"), 62 PVID(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82598AF_SINGLE_PORT, "Intel(R) 82598EB AF (Fiber)"), 63 PVID(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82598EB_CX4, "Intel(R) 82598EB AT (CX4)"), 64 PVID(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82598AT, "Intel(R) 82598EB AT"), 65 PVID(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82598AT2, "Intel(R) 82598EB AT2"), 66 PVID(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82598, "Intel(R) 82598"), 67 PVID(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82598_DA_DUAL_PORT, "Intel(R) 82598EB AF DA (Dual Fiber)"), 68 PVID(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82598_CX4_DUAL_PORT, "Intel(R) 82598EB AT (Dual CX4)"), 69 PVID(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82598EB_XF_LR, "Intel(R) 82598EB AF (Dual Fiber LR)"), 70 PVID(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82598_SR_DUAL_PORT_EM, "Intel(R) 82598EB AF (Dual Fiber SR)"), 71 PVID(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82598EB_SFP_LOM, "Intel(R) 82598EB LOM"), 72 PVID(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_KX4, "Intel(R) X520 82599 (KX4)"), 73 PVID(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_KX4_MEZZ, "Intel(R) X520 82599 (KX4 Mezzanine)"), 74 PVID(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_SFP, "Intel(R) X520 82599ES (SFI/SFP+)"), 75 PVID(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_XAUI_LOM, "Intel(R) X520 82599 (XAUI/BX4)"), 76 PVID(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_CX4, "Intel(R) X520 82599 (Dual CX4)"), 77 PVID(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_T3_LOM, "Intel(R) X520-T 82599 LOM"), 78 PVID(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_LS, "Intel(R) X520 82599 LS"), 79 PVID(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_COMBO_BACKPLANE, "Intel(R) X520 82599 (Combined Backplane)"), 80 PVID(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_BACKPLANE_FCOE, "Intel(R) X520 82599 (Backplane w/FCoE)"), 81 PVID(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_SFP_SF2, "Intel(R) X520 82599 (Dual SFP+)"), 82 PVID(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_SFP_FCOE, "Intel(R) X520 82599 (Dual SFP+ w/FCoE)"), 83 PVID(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599EN_SFP, "Intel(R) X520-1 82599EN (SFP+)"), 84 PVID(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_SFP_SF_QP, "Intel(R) X520-4 82599 (Quad SFP+)"), 85 PVID(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_QSFP_SF_QP, "Intel(R) X520-Q1 82599 (QSFP+)"), 86 PVID(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X540T, "Intel(R) X540-AT2"), 87 PVID(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X540T1, "Intel(R) X540-T1"), 88 PVID(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550T, "Intel(R) X550-T2"), 89 PVID(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550T1, "Intel(R) X550-T1"), 90 PVID(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_X_KR, "Intel(R) X552 (KR Backplane)"), 91 PVID(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_X_KX4, "Intel(R) X552 (KX4 Backplane)"), 92 PVID(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_X_10G_T, "Intel(R) X552/X557-AT (10GBASE-T)"), 93 PVID(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_X_1G_T, "Intel(R) X552 (1000BASE-T)"), 94 PVID(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_X_SFP, "Intel(R) X552 (SFP+)"), 95 PVID(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_A_KR, "Intel(R) X553 (KR Backplane)"), 96 PVID(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_A_KR_L, "Intel(R) X553 L (KR Backplane)"), 97 PVID(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_A_SFP, "Intel(R) X553 (SFP+)"), 98 PVID(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_A_SFP_N, "Intel(R) X553 N (SFP+)"), 99 PVID(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_A_SGMII, "Intel(R) X553 (1GbE SGMII)"), 100 PVID(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_A_SGMII_L, "Intel(R) X553 L (1GbE SGMII)"), 101 PVID(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_A_10G_T, "Intel(R) X553/X557-AT (10GBASE-T)"), 102 PVID(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_A_1G_T, "Intel(R) X553 (1GbE)"), 103 PVID(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_A_1G_T_L, "Intel(R) X553 L (1GbE)"), 104 PVID(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X540_BYPASS, "Intel(R) X540-T2 (Bypass)"), 105 PVID(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_BYPASS, "Intel(R) X520 82599 (Bypass)"), 106 /* required last entry */ 107 PVID_END 108 }; 109 110 static void *ixgbe_register(device_t); 111 static int ixgbe_if_attach_pre(if_ctx_t); 112 static int ixgbe_if_attach_post(if_ctx_t); 113 static int ixgbe_if_detach(if_ctx_t); 114 static int ixgbe_if_shutdown(if_ctx_t); 115 static int ixgbe_if_suspend(if_ctx_t); 116 static int ixgbe_if_resume(if_ctx_t); 117 118 static void ixgbe_if_stop(if_ctx_t); 119 void ixgbe_if_enable_intr(if_ctx_t); 120 static void ixgbe_if_disable_intr(if_ctx_t); 121 static void ixgbe_link_intr_enable(if_ctx_t); 122 static int ixgbe_if_rx_queue_intr_enable(if_ctx_t, uint16_t); 123 static void ixgbe_if_media_status(if_ctx_t, struct ifmediareq *); 124 static int ixgbe_if_media_change(if_ctx_t); 125 static int ixgbe_if_msix_intr_assign(if_ctx_t, int); 126 static int ixgbe_if_mtu_set(if_ctx_t, uint32_t); 127 static void ixgbe_if_crcstrip_set(if_ctx_t, int, int); 128 static void ixgbe_if_multi_set(if_ctx_t); 129 static int ixgbe_if_promisc_set(if_ctx_t, int); 130 static int ixgbe_if_tx_queues_alloc(if_ctx_t, caddr_t *, uint64_t *, int, int); 131 static int ixgbe_if_rx_queues_alloc(if_ctx_t, caddr_t *, uint64_t *, int, int); 132 static void ixgbe_if_queues_free(if_ctx_t); 133 static void ixgbe_if_timer(if_ctx_t, uint16_t); 134 static void ixgbe_if_update_admin_status(if_ctx_t); 135 static void ixgbe_if_vlan_register(if_ctx_t, u16); 136 static void ixgbe_if_vlan_unregister(if_ctx_t, u16); 137 static int ixgbe_if_i2c_req(if_ctx_t, struct ifi2creq *); 138 static bool ixgbe_if_needs_restart(if_ctx_t, enum iflib_restart_event); 139 int ixgbe_intr(void *); 140 141 /************************************************************************ 142 * Function prototypes 143 ************************************************************************/ 144 static uint64_t ixgbe_if_get_counter(if_ctx_t, ift_counter); 145 146 static void ixgbe_enable_queue(struct ixgbe_softc *, u32); 147 static void ixgbe_disable_queue(struct ixgbe_softc *, u32); 148 static void ixgbe_add_device_sysctls(if_ctx_t); 149 static int ixgbe_allocate_pci_resources(if_ctx_t); 150 static int ixgbe_setup_low_power_mode(if_ctx_t); 151 152 static void ixgbe_config_dmac(struct ixgbe_softc *); 153 static void ixgbe_configure_ivars(struct ixgbe_softc *); 154 static void ixgbe_set_ivar(struct ixgbe_softc *, u8, u8, s8); 155 static u8 *ixgbe_mc_array_itr(struct ixgbe_hw *, u8 **, u32 *); 156 static bool ixgbe_sfp_probe(if_ctx_t); 157 158 static void ixgbe_free_pci_resources(if_ctx_t); 159 160 static int ixgbe_msix_link(void *); 161 static int ixgbe_msix_que(void *); 162 static void ixgbe_initialize_rss_mapping(struct ixgbe_softc *); 163 static void ixgbe_initialize_receive_units(if_ctx_t); 164 static void ixgbe_initialize_transmit_units(if_ctx_t); 165 166 static int ixgbe_setup_interface(if_ctx_t); 167 static void ixgbe_init_device_features(struct ixgbe_softc *); 168 static void ixgbe_check_fan_failure(struct ixgbe_softc *, u32, bool); 169 static void ixgbe_sbuf_fw_version(struct ixgbe_hw *, struct sbuf *); 170 static void ixgbe_print_fw_version(if_ctx_t); 171 static void ixgbe_add_media_types(if_ctx_t); 172 static void ixgbe_update_stats_counters(struct ixgbe_softc *); 173 static void ixgbe_config_link(if_ctx_t); 174 static void ixgbe_get_slot_info(struct ixgbe_softc *); 175 static void ixgbe_check_wol_support(struct ixgbe_softc *); 176 static void ixgbe_enable_rx_drop(struct ixgbe_softc *); 177 static void ixgbe_disable_rx_drop(struct ixgbe_softc *); 178 179 static void ixgbe_add_hw_stats(struct ixgbe_softc *); 180 static int ixgbe_set_flowcntl(struct ixgbe_softc *, int); 181 static int ixgbe_set_advertise(struct ixgbe_softc *, int); 182 static int ixgbe_get_default_advertise(struct ixgbe_softc *); 183 static void ixgbe_setup_vlan_hw_support(if_ctx_t); 184 static void ixgbe_config_gpie(struct ixgbe_softc *); 185 static void ixgbe_config_delay_values(struct ixgbe_softc *); 186 187 /* Sysctl handlers */ 188 static int ixgbe_sysctl_flowcntl(SYSCTL_HANDLER_ARGS); 189 static int ixgbe_sysctl_advertise(SYSCTL_HANDLER_ARGS); 190 static int ixgbe_sysctl_interrupt_rate_handler(SYSCTL_HANDLER_ARGS); 191 static int ixgbe_sysctl_dmac(SYSCTL_HANDLER_ARGS); 192 static int ixgbe_sysctl_phy_temp(SYSCTL_HANDLER_ARGS); 193 static int ixgbe_sysctl_phy_overtemp_occurred(SYSCTL_HANDLER_ARGS); 194 static int ixgbe_sysctl_print_fw_version(SYSCTL_HANDLER_ARGS); 195 #ifdef IXGBE_DEBUG 196 static int ixgbe_sysctl_power_state(SYSCTL_HANDLER_ARGS); 197 static int ixgbe_sysctl_print_rss_config(SYSCTL_HANDLER_ARGS); 198 #endif 199 static int ixgbe_sysctl_rdh_handler(SYSCTL_HANDLER_ARGS); 200 static int ixgbe_sysctl_rdt_handler(SYSCTL_HANDLER_ARGS); 201 static int ixgbe_sysctl_tdt_handler(SYSCTL_HANDLER_ARGS); 202 static int ixgbe_sysctl_tdh_handler(SYSCTL_HANDLER_ARGS); 203 static int ixgbe_sysctl_eee_state(SYSCTL_HANDLER_ARGS); 204 static int ixgbe_sysctl_wol_enable(SYSCTL_HANDLER_ARGS); 205 static int ixgbe_sysctl_wufc(SYSCTL_HANDLER_ARGS); 206 207 /* Deferred interrupt tasklets */ 208 static void ixgbe_handle_msf(void *); 209 static void ixgbe_handle_mod(void *); 210 static void ixgbe_handle_phy(void *); 211 212 /************************************************************************ 213 * FreeBSD Device Interface Entry Points 214 ************************************************************************/ 215 static device_method_t ix_methods[] = { 216 /* Device interface */ 217 DEVMETHOD(device_register, ixgbe_register), 218 DEVMETHOD(device_probe, iflib_device_probe), 219 DEVMETHOD(device_attach, iflib_device_attach), 220 DEVMETHOD(device_detach, iflib_device_detach), 221 DEVMETHOD(device_shutdown, iflib_device_shutdown), 222 DEVMETHOD(device_suspend, iflib_device_suspend), 223 DEVMETHOD(device_resume, iflib_device_resume), 224 #ifdef PCI_IOV 225 DEVMETHOD(pci_iov_init, iflib_device_iov_init), 226 DEVMETHOD(pci_iov_uninit, iflib_device_iov_uninit), 227 DEVMETHOD(pci_iov_add_vf, iflib_device_iov_add_vf), 228 #endif /* PCI_IOV */ 229 DEVMETHOD_END 230 }; 231 232 static driver_t ix_driver = { 233 "ix", ix_methods, sizeof(struct ixgbe_softc), 234 }; 235 236 DRIVER_MODULE(ix, pci, ix_driver, 0, 0); 237 IFLIB_PNP_INFO(pci, ix_driver, ixgbe_vendor_info_array); 238 MODULE_DEPEND(ix, pci, 1, 1, 1); 239 MODULE_DEPEND(ix, ether, 1, 1, 1); 240 MODULE_DEPEND(ix, iflib, 1, 1, 1); 241 242 static device_method_t ixgbe_if_methods[] = { 243 DEVMETHOD(ifdi_attach_pre, ixgbe_if_attach_pre), 244 DEVMETHOD(ifdi_attach_post, ixgbe_if_attach_post), 245 DEVMETHOD(ifdi_detach, ixgbe_if_detach), 246 DEVMETHOD(ifdi_shutdown, ixgbe_if_shutdown), 247 DEVMETHOD(ifdi_suspend, ixgbe_if_suspend), 248 DEVMETHOD(ifdi_resume, ixgbe_if_resume), 249 DEVMETHOD(ifdi_init, ixgbe_if_init), 250 DEVMETHOD(ifdi_stop, ixgbe_if_stop), 251 DEVMETHOD(ifdi_msix_intr_assign, ixgbe_if_msix_intr_assign), 252 DEVMETHOD(ifdi_intr_enable, ixgbe_if_enable_intr), 253 DEVMETHOD(ifdi_intr_disable, ixgbe_if_disable_intr), 254 DEVMETHOD(ifdi_link_intr_enable, ixgbe_link_intr_enable), 255 DEVMETHOD(ifdi_tx_queue_intr_enable, ixgbe_if_rx_queue_intr_enable), 256 DEVMETHOD(ifdi_rx_queue_intr_enable, ixgbe_if_rx_queue_intr_enable), 257 DEVMETHOD(ifdi_tx_queues_alloc, ixgbe_if_tx_queues_alloc), 258 DEVMETHOD(ifdi_rx_queues_alloc, ixgbe_if_rx_queues_alloc), 259 DEVMETHOD(ifdi_queues_free, ixgbe_if_queues_free), 260 DEVMETHOD(ifdi_update_admin_status, ixgbe_if_update_admin_status), 261 DEVMETHOD(ifdi_multi_set, ixgbe_if_multi_set), 262 DEVMETHOD(ifdi_mtu_set, ixgbe_if_mtu_set), 263 DEVMETHOD(ifdi_crcstrip_set, ixgbe_if_crcstrip_set), 264 DEVMETHOD(ifdi_media_status, ixgbe_if_media_status), 265 DEVMETHOD(ifdi_media_change, ixgbe_if_media_change), 266 DEVMETHOD(ifdi_promisc_set, ixgbe_if_promisc_set), 267 DEVMETHOD(ifdi_timer, ixgbe_if_timer), 268 DEVMETHOD(ifdi_vlan_register, ixgbe_if_vlan_register), 269 DEVMETHOD(ifdi_vlan_unregister, ixgbe_if_vlan_unregister), 270 DEVMETHOD(ifdi_get_counter, ixgbe_if_get_counter), 271 DEVMETHOD(ifdi_i2c_req, ixgbe_if_i2c_req), 272 DEVMETHOD(ifdi_needs_restart, ixgbe_if_needs_restart), 273 #ifdef PCI_IOV 274 DEVMETHOD(ifdi_iov_init, ixgbe_if_iov_init), 275 DEVMETHOD(ifdi_iov_uninit, ixgbe_if_iov_uninit), 276 DEVMETHOD(ifdi_iov_vf_add, ixgbe_if_iov_vf_add), 277 #endif /* PCI_IOV */ 278 DEVMETHOD_END 279 }; 280 281 /* 282 * TUNEABLE PARAMETERS: 283 */ 284 285 static SYSCTL_NODE(_hw, OID_AUTO, ix, CTLFLAG_RD | CTLFLAG_MPSAFE, 0, 286 "IXGBE driver parameters"); 287 static driver_t ixgbe_if_driver = { 288 "ixgbe_if", ixgbe_if_methods, sizeof(struct ixgbe_softc) 289 }; 290 291 static int ixgbe_max_interrupt_rate = (4000000 / IXGBE_LOW_LATENCY); 292 SYSCTL_INT(_hw_ix, OID_AUTO, max_interrupt_rate, CTLFLAG_RDTUN, 293 &ixgbe_max_interrupt_rate, 0, "Maximum interrupts per second"); 294 295 /* Flow control setting, default to full */ 296 static int ixgbe_flow_control = ixgbe_fc_full; 297 SYSCTL_INT(_hw_ix, OID_AUTO, flow_control, CTLFLAG_RDTUN, 298 &ixgbe_flow_control, 0, "Default flow control used for all adapters"); 299 300 /* Advertise Speed, default to 0 (auto) */ 301 static int ixgbe_advertise_speed = 0; 302 SYSCTL_INT(_hw_ix, OID_AUTO, advertise_speed, CTLFLAG_RDTUN, 303 &ixgbe_advertise_speed, 0, "Default advertised speed for all adapters"); 304 305 /* 306 * Smart speed setting, default to on 307 * this only works as a compile option 308 * right now as its during attach, set 309 * this to 'ixgbe_smart_speed_off' to 310 * disable. 311 */ 312 static int ixgbe_smart_speed = ixgbe_smart_speed_on; 313 314 /* 315 * MSI-X should be the default for best performance, 316 * but this allows it to be forced off for testing. 317 */ 318 static int ixgbe_enable_msix = 1; 319 SYSCTL_INT(_hw_ix, OID_AUTO, enable_msix, CTLFLAG_RDTUN, &ixgbe_enable_msix, 0, 320 "Enable MSI-X interrupts"); 321 322 /* 323 * Defining this on will allow the use 324 * of unsupported SFP+ modules, note that 325 * doing so you are on your own :) 326 */ 327 static int allow_unsupported_sfp = false; 328 SYSCTL_INT(_hw_ix, OID_AUTO, unsupported_sfp, CTLFLAG_RDTUN, 329 &allow_unsupported_sfp, 0, 330 "Allow unsupported SFP modules...use at your own risk"); 331 332 /* 333 * Not sure if Flow Director is fully baked, 334 * so we'll default to turning it off. 335 */ 336 static int ixgbe_enable_fdir = 0; 337 SYSCTL_INT(_hw_ix, OID_AUTO, enable_fdir, CTLFLAG_RDTUN, &ixgbe_enable_fdir, 0, 338 "Enable Flow Director"); 339 340 /* Receive-Side Scaling */ 341 static int ixgbe_enable_rss = 1; 342 SYSCTL_INT(_hw_ix, OID_AUTO, enable_rss, CTLFLAG_RDTUN, &ixgbe_enable_rss, 0, 343 "Enable Receive-Side Scaling (RSS)"); 344 345 /* 346 * AIM: Adaptive Interrupt Moderation 347 * which means that the interrupt rate 348 * is varied over time based on the 349 * traffic for that interrupt vector 350 */ 351 static int ixgbe_enable_aim = false; 352 SYSCTL_INT(_hw_ix, OID_AUTO, enable_aim, CTLFLAG_RWTUN, &ixgbe_enable_aim, 0, 353 "Enable adaptive interrupt moderation"); 354 355 #if 0 356 /* Keep running tab on them for sanity check */ 357 static int ixgbe_total_ports; 358 #endif 359 360 MALLOC_DEFINE(M_IXGBE, "ix", "ix driver allocations"); 361 362 /* 363 * For Flow Director: this is the number of TX packets we sample 364 * for the filter pool, this means every 20th packet will be probed. 365 * 366 * This feature can be disabled by setting this to 0. 367 */ 368 static int atr_sample_rate = 20; 369 370 extern struct if_txrx ixgbe_txrx; 371 372 static struct if_shared_ctx ixgbe_sctx_init = { 373 .isc_magic = IFLIB_MAGIC, 374 .isc_q_align = PAGE_SIZE,/* max(DBA_ALIGN, PAGE_SIZE) */ 375 .isc_tx_maxsize = IXGBE_TSO_SIZE + sizeof(struct ether_vlan_header), 376 .isc_tx_maxsegsize = PAGE_SIZE, 377 .isc_tso_maxsize = IXGBE_TSO_SIZE + sizeof(struct ether_vlan_header), 378 .isc_tso_maxsegsize = PAGE_SIZE, 379 .isc_rx_maxsize = PAGE_SIZE*4, 380 .isc_rx_nsegments = 1, 381 .isc_rx_maxsegsize = PAGE_SIZE*4, 382 .isc_nfl = 1, 383 .isc_ntxqs = 1, 384 .isc_nrxqs = 1, 385 386 .isc_admin_intrcnt = 1, 387 .isc_vendor_info = ixgbe_vendor_info_array, 388 .isc_driver_version = ixgbe_driver_version, 389 .isc_driver = &ixgbe_if_driver, 390 .isc_flags = IFLIB_TSO_INIT_IP, 391 392 .isc_nrxd_min = {MIN_RXD}, 393 .isc_ntxd_min = {MIN_TXD}, 394 .isc_nrxd_max = {MAX_RXD}, 395 .isc_ntxd_max = {MAX_TXD}, 396 .isc_nrxd_default = {DEFAULT_RXD}, 397 .isc_ntxd_default = {DEFAULT_TXD}, 398 }; 399 400 /************************************************************************ 401 * ixgbe_if_tx_queues_alloc 402 ************************************************************************/ 403 static int 404 ixgbe_if_tx_queues_alloc(if_ctx_t ctx, caddr_t *vaddrs, uint64_t *paddrs, 405 int ntxqs, int ntxqsets) 406 { 407 struct ixgbe_softc *sc = iflib_get_softc(ctx); 408 if_softc_ctx_t scctx = sc->shared; 409 struct ix_tx_queue *que; 410 int i, j, error; 411 412 MPASS(sc->num_tx_queues > 0); 413 MPASS(sc->num_tx_queues == ntxqsets); 414 MPASS(ntxqs == 1); 415 416 /* Allocate queue structure memory */ 417 sc->tx_queues = 418 (struct ix_tx_queue *)malloc(sizeof(struct ix_tx_queue) * ntxqsets, 419 M_IXGBE, M_NOWAIT | M_ZERO); 420 if (!sc->tx_queues) { 421 device_printf(iflib_get_dev(ctx), 422 "Unable to allocate TX ring memory\n"); 423 return (ENOMEM); 424 } 425 426 for (i = 0, que = sc->tx_queues; i < ntxqsets; i++, que++) { 427 struct tx_ring *txr = &que->txr; 428 429 /* In case SR-IOV is enabled, align the index properly */ 430 txr->me = ixgbe_vf_que_index(sc->iov_mode, sc->pool, 431 i); 432 433 txr->sc = que->sc = sc; 434 435 /* Allocate report status array */ 436 txr->tx_rsq = (qidx_t *)malloc(sizeof(qidx_t) * scctx->isc_ntxd[0], M_IXGBE, M_NOWAIT | M_ZERO); 437 if (txr->tx_rsq == NULL) { 438 error = ENOMEM; 439 goto fail; 440 } 441 for (j = 0; j < scctx->isc_ntxd[0]; j++) 442 txr->tx_rsq[j] = QIDX_INVALID; 443 /* get the virtual and physical address of the hardware queues */ 444 txr->tail = IXGBE_TDT(txr->me); 445 txr->tx_base = (union ixgbe_adv_tx_desc *)vaddrs[i]; 446 txr->tx_paddr = paddrs[i]; 447 448 txr->bytes = 0; 449 txr->total_packets = 0; 450 451 /* Set the rate at which we sample packets */ 452 if (sc->feat_en & IXGBE_FEATURE_FDIR) 453 txr->atr_sample = atr_sample_rate; 454 455 } 456 457 device_printf(iflib_get_dev(ctx), "allocated for %d queues\n", 458 sc->num_tx_queues); 459 460 return (0); 461 462 fail: 463 ixgbe_if_queues_free(ctx); 464 465 return (error); 466 } /* ixgbe_if_tx_queues_alloc */ 467 468 /************************************************************************ 469 * ixgbe_if_rx_queues_alloc 470 ************************************************************************/ 471 static int 472 ixgbe_if_rx_queues_alloc(if_ctx_t ctx, caddr_t *vaddrs, uint64_t *paddrs, 473 int nrxqs, int nrxqsets) 474 { 475 struct ixgbe_softc *sc = iflib_get_softc(ctx); 476 struct ix_rx_queue *que; 477 int i; 478 479 MPASS(sc->num_rx_queues > 0); 480 MPASS(sc->num_rx_queues == nrxqsets); 481 MPASS(nrxqs == 1); 482 483 /* Allocate queue structure memory */ 484 sc->rx_queues = 485 (struct ix_rx_queue *)malloc(sizeof(struct ix_rx_queue)*nrxqsets, 486 M_IXGBE, M_NOWAIT | M_ZERO); 487 if (!sc->rx_queues) { 488 device_printf(iflib_get_dev(ctx), 489 "Unable to allocate TX ring memory\n"); 490 return (ENOMEM); 491 } 492 493 for (i = 0, que = sc->rx_queues; i < nrxqsets; i++, que++) { 494 struct rx_ring *rxr = &que->rxr; 495 496 /* In case SR-IOV is enabled, align the index properly */ 497 rxr->me = ixgbe_vf_que_index(sc->iov_mode, sc->pool, 498 i); 499 500 rxr->sc = que->sc = sc; 501 502 /* get the virtual and physical address of the hw queues */ 503 rxr->tail = IXGBE_RDT(rxr->me); 504 rxr->rx_base = (union ixgbe_adv_rx_desc *)vaddrs[i]; 505 rxr->rx_paddr = paddrs[i]; 506 rxr->bytes = 0; 507 rxr->que = que; 508 } 509 510 device_printf(iflib_get_dev(ctx), "allocated for %d rx queues\n", 511 sc->num_rx_queues); 512 513 return (0); 514 } /* ixgbe_if_rx_queues_alloc */ 515 516 /************************************************************************ 517 * ixgbe_if_queues_free 518 ************************************************************************/ 519 static void 520 ixgbe_if_queues_free(if_ctx_t ctx) 521 { 522 struct ixgbe_softc *sc = iflib_get_softc(ctx); 523 struct ix_tx_queue *tx_que = sc->tx_queues; 524 struct ix_rx_queue *rx_que = sc->rx_queues; 525 int i; 526 527 if (tx_que != NULL) { 528 for (i = 0; i < sc->num_tx_queues; i++, tx_que++) { 529 struct tx_ring *txr = &tx_que->txr; 530 if (txr->tx_rsq == NULL) 531 break; 532 533 free(txr->tx_rsq, M_IXGBE); 534 txr->tx_rsq = NULL; 535 } 536 537 free(sc->tx_queues, M_IXGBE); 538 sc->tx_queues = NULL; 539 } 540 if (rx_que != NULL) { 541 free(sc->rx_queues, M_IXGBE); 542 sc->rx_queues = NULL; 543 } 544 } /* ixgbe_if_queues_free */ 545 546 /************************************************************************ 547 * ixgbe_initialize_rss_mapping 548 ************************************************************************/ 549 static void 550 ixgbe_initialize_rss_mapping(struct ixgbe_softc *sc) 551 { 552 struct ixgbe_hw *hw = &sc->hw; 553 u32 reta = 0, mrqc, rss_key[10]; 554 int queue_id, table_size, index_mult; 555 int i, j; 556 u32 rss_hash_config; 557 558 if (sc->feat_en & IXGBE_FEATURE_RSS) { 559 /* Fetch the configured RSS key */ 560 rss_getkey((uint8_t *)&rss_key); 561 } else { 562 /* set up random bits */ 563 arc4rand(&rss_key, sizeof(rss_key), 0); 564 } 565 566 /* Set multiplier for RETA setup and table size based on MAC */ 567 index_mult = 0x1; 568 table_size = 128; 569 switch (sc->hw.mac.type) { 570 case ixgbe_mac_82598EB: 571 index_mult = 0x11; 572 break; 573 case ixgbe_mac_X550: 574 case ixgbe_mac_X550EM_x: 575 case ixgbe_mac_X550EM_a: 576 table_size = 512; 577 break; 578 default: 579 break; 580 } 581 582 /* Set up the redirection table */ 583 for (i = 0, j = 0; i < table_size; i++, j++) { 584 if (j == sc->num_rx_queues) 585 j = 0; 586 587 if (sc->feat_en & IXGBE_FEATURE_RSS) { 588 /* 589 * Fetch the RSS bucket id for the given indirection 590 * entry. Cap it at the number of configured buckets 591 * (which is num_rx_queues.) 592 */ 593 queue_id = rss_get_indirection_to_bucket(i); 594 queue_id = queue_id % sc->num_rx_queues; 595 } else 596 queue_id = (j * index_mult); 597 598 /* 599 * The low 8 bits are for hash value (n+0); 600 * The next 8 bits are for hash value (n+1), etc. 601 */ 602 reta = reta >> 8; 603 reta = reta | (((uint32_t)queue_id) << 24); 604 if ((i & 3) == 3) { 605 if (i < 128) 606 IXGBE_WRITE_REG(hw, IXGBE_RETA(i >> 2), reta); 607 else 608 IXGBE_WRITE_REG(hw, IXGBE_ERETA((i >> 2) - 32), 609 reta); 610 reta = 0; 611 } 612 } 613 614 /* Now fill our hash function seeds */ 615 for (i = 0; i < 10; i++) 616 IXGBE_WRITE_REG(hw, IXGBE_RSSRK(i), rss_key[i]); 617 618 /* Perform hash on these packet types */ 619 if (sc->feat_en & IXGBE_FEATURE_RSS) 620 rss_hash_config = rss_gethashconfig(); 621 else { 622 /* 623 * Disable UDP - IP fragments aren't currently being handled 624 * and so we end up with a mix of 2-tuple and 4-tuple 625 * traffic. 626 */ 627 rss_hash_config = RSS_HASHTYPE_RSS_IPV4 628 | RSS_HASHTYPE_RSS_TCP_IPV4 629 | RSS_HASHTYPE_RSS_IPV6 630 | RSS_HASHTYPE_RSS_TCP_IPV6 631 | RSS_HASHTYPE_RSS_IPV6_EX 632 | RSS_HASHTYPE_RSS_TCP_IPV6_EX; 633 } 634 635 mrqc = IXGBE_MRQC_RSSEN; 636 if (rss_hash_config & RSS_HASHTYPE_RSS_IPV4) 637 mrqc |= IXGBE_MRQC_RSS_FIELD_IPV4; 638 if (rss_hash_config & RSS_HASHTYPE_RSS_TCP_IPV4) 639 mrqc |= IXGBE_MRQC_RSS_FIELD_IPV4_TCP; 640 if (rss_hash_config & RSS_HASHTYPE_RSS_IPV6) 641 mrqc |= IXGBE_MRQC_RSS_FIELD_IPV6; 642 if (rss_hash_config & RSS_HASHTYPE_RSS_TCP_IPV6) 643 mrqc |= IXGBE_MRQC_RSS_FIELD_IPV6_TCP; 644 if (rss_hash_config & RSS_HASHTYPE_RSS_IPV6_EX) 645 mrqc |= IXGBE_MRQC_RSS_FIELD_IPV6_EX; 646 if (rss_hash_config & RSS_HASHTYPE_RSS_TCP_IPV6_EX) 647 mrqc |= IXGBE_MRQC_RSS_FIELD_IPV6_EX_TCP; 648 if (rss_hash_config & RSS_HASHTYPE_RSS_UDP_IPV4) 649 mrqc |= IXGBE_MRQC_RSS_FIELD_IPV4_UDP; 650 if (rss_hash_config & RSS_HASHTYPE_RSS_UDP_IPV6) 651 mrqc |= IXGBE_MRQC_RSS_FIELD_IPV6_UDP; 652 if (rss_hash_config & RSS_HASHTYPE_RSS_UDP_IPV6_EX) 653 mrqc |= IXGBE_MRQC_RSS_FIELD_IPV6_EX_UDP; 654 mrqc |= ixgbe_get_mrqc(sc->iov_mode); 655 IXGBE_WRITE_REG(hw, IXGBE_MRQC, mrqc); 656 } /* ixgbe_initialize_rss_mapping */ 657 658 /************************************************************************ 659 * ixgbe_initialize_receive_units - Setup receive registers and features. 660 ************************************************************************/ 661 #define BSIZEPKT_ROUNDUP ((1<<IXGBE_SRRCTL_BSIZEPKT_SHIFT)-1) 662 663 static void 664 ixgbe_initialize_receive_units(if_ctx_t ctx) 665 { 666 struct ixgbe_softc *sc = iflib_get_softc(ctx); 667 if_softc_ctx_t scctx = sc->shared; 668 struct ixgbe_hw *hw = &sc->hw; 669 if_t ifp = iflib_get_ifp(ctx); 670 struct ix_rx_queue *que; 671 int i, j; 672 u32 bufsz, fctrl, srrctl, rxcsum; 673 u32 hlreg; 674 675 /* 676 * Make sure receives are disabled while 677 * setting up the descriptor ring 678 */ 679 ixgbe_disable_rx(hw); 680 681 /* Enable broadcasts */ 682 fctrl = IXGBE_READ_REG(hw, IXGBE_FCTRL); 683 fctrl |= IXGBE_FCTRL_BAM; 684 if (sc->hw.mac.type == ixgbe_mac_82598EB) { 685 fctrl |= IXGBE_FCTRL_DPF; 686 fctrl |= IXGBE_FCTRL_PMCF; 687 } 688 IXGBE_WRITE_REG(hw, IXGBE_FCTRL, fctrl); 689 690 /* Set for Jumbo Frames? */ 691 hlreg = IXGBE_READ_REG(hw, IXGBE_HLREG0); 692 if (if_getmtu(ifp) > ETHERMTU) 693 hlreg |= IXGBE_HLREG0_JUMBOEN; 694 else 695 hlreg &= ~IXGBE_HLREG0_JUMBOEN; 696 IXGBE_WRITE_REG(hw, IXGBE_HLREG0, hlreg); 697 698 bufsz = (sc->rx_mbuf_sz + BSIZEPKT_ROUNDUP) >> 699 IXGBE_SRRCTL_BSIZEPKT_SHIFT; 700 701 /* Setup the Base and Length of the Rx Descriptor Ring */ 702 for (i = 0, que = sc->rx_queues; i < sc->num_rx_queues; i++, que++) { 703 struct rx_ring *rxr = &que->rxr; 704 u64 rdba = rxr->rx_paddr; 705 706 j = rxr->me; 707 708 /* Setup the Base and Length of the Rx Descriptor Ring */ 709 IXGBE_WRITE_REG(hw, IXGBE_RDBAL(j), 710 (rdba & 0x00000000ffffffffULL)); 711 IXGBE_WRITE_REG(hw, IXGBE_RDBAH(j), (rdba >> 32)); 712 IXGBE_WRITE_REG(hw, IXGBE_RDLEN(j), 713 scctx->isc_nrxd[0] * sizeof(union ixgbe_adv_rx_desc)); 714 715 /* Set up the SRRCTL register */ 716 srrctl = IXGBE_READ_REG(hw, IXGBE_SRRCTL(j)); 717 srrctl &= ~IXGBE_SRRCTL_BSIZEHDR_MASK; 718 srrctl &= ~IXGBE_SRRCTL_BSIZEPKT_MASK; 719 srrctl |= bufsz; 720 srrctl |= IXGBE_SRRCTL_DESCTYPE_ADV_ONEBUF; 721 722 /* 723 * Set DROP_EN iff we have no flow control and >1 queue. 724 * Note that srrctl was cleared shortly before during reset, 725 * so we do not need to clear the bit, but do it just in case 726 * this code is moved elsewhere. 727 */ 728 if (sc->num_rx_queues > 1 && 729 sc->hw.fc.requested_mode == ixgbe_fc_none) { 730 srrctl |= IXGBE_SRRCTL_DROP_EN; 731 } else { 732 srrctl &= ~IXGBE_SRRCTL_DROP_EN; 733 } 734 735 IXGBE_WRITE_REG(hw, IXGBE_SRRCTL(j), srrctl); 736 737 /* Setup the HW Rx Head and Tail Descriptor Pointers */ 738 IXGBE_WRITE_REG(hw, IXGBE_RDH(j), 0); 739 IXGBE_WRITE_REG(hw, IXGBE_RDT(j), 0); 740 741 /* Set the driver rx tail address */ 742 rxr->tail = IXGBE_RDT(rxr->me); 743 } 744 745 if (sc->hw.mac.type != ixgbe_mac_82598EB) { 746 u32 psrtype = IXGBE_PSRTYPE_TCPHDR 747 | IXGBE_PSRTYPE_UDPHDR 748 | IXGBE_PSRTYPE_IPV4HDR 749 | IXGBE_PSRTYPE_IPV6HDR; 750 IXGBE_WRITE_REG(hw, IXGBE_PSRTYPE(0), psrtype); 751 } 752 753 rxcsum = IXGBE_READ_REG(hw, IXGBE_RXCSUM); 754 755 ixgbe_initialize_rss_mapping(sc); 756 757 if (sc->feat_en & IXGBE_FEATURE_RSS) { 758 /* RSS and RX IPP Checksum are mutually exclusive */ 759 rxcsum |= IXGBE_RXCSUM_PCSD; 760 } 761 762 if (if_getcapenable(ifp) & IFCAP_RXCSUM) 763 rxcsum |= IXGBE_RXCSUM_PCSD; 764 765 /* This is useful for calculating UDP/IP fragment checksums */ 766 if (!(rxcsum & IXGBE_RXCSUM_PCSD)) 767 rxcsum |= IXGBE_RXCSUM_IPPCSE; 768 769 IXGBE_WRITE_REG(hw, IXGBE_RXCSUM, rxcsum); 770 771 } /* ixgbe_initialize_receive_units */ 772 773 /************************************************************************ 774 * ixgbe_initialize_transmit_units - Enable transmit units. 775 ************************************************************************/ 776 static void 777 ixgbe_initialize_transmit_units(if_ctx_t ctx) 778 { 779 struct ixgbe_softc *sc = iflib_get_softc(ctx); 780 struct ixgbe_hw *hw = &sc->hw; 781 if_softc_ctx_t scctx = sc->shared; 782 struct ix_tx_queue *que; 783 int i; 784 785 /* Setup the Base and Length of the Tx Descriptor Ring */ 786 for (i = 0, que = sc->tx_queues; i < sc->num_tx_queues; 787 i++, que++) { 788 struct tx_ring *txr = &que->txr; 789 u64 tdba = txr->tx_paddr; 790 u32 txctrl = 0; 791 int j = txr->me; 792 793 IXGBE_WRITE_REG(hw, IXGBE_TDBAL(j), 794 (tdba & 0x00000000ffffffffULL)); 795 IXGBE_WRITE_REG(hw, IXGBE_TDBAH(j), (tdba >> 32)); 796 IXGBE_WRITE_REG(hw, IXGBE_TDLEN(j), 797 scctx->isc_ntxd[0] * sizeof(union ixgbe_adv_tx_desc)); 798 799 /* Setup the HW Tx Head and Tail descriptor pointers */ 800 IXGBE_WRITE_REG(hw, IXGBE_TDH(j), 0); 801 IXGBE_WRITE_REG(hw, IXGBE_TDT(j), 0); 802 803 /* Cache the tail address */ 804 txr->tail = IXGBE_TDT(txr->me); 805 806 txr->tx_rs_cidx = txr->tx_rs_pidx; 807 txr->tx_cidx_processed = scctx->isc_ntxd[0] - 1; 808 for (int k = 0; k < scctx->isc_ntxd[0]; k++) 809 txr->tx_rsq[k] = QIDX_INVALID; 810 811 /* Disable Head Writeback */ 812 /* 813 * Note: for X550 series devices, these registers are actually 814 * prefixed with TPH_ isntead of DCA_, but the addresses and 815 * fields remain the same. 816 */ 817 switch (hw->mac.type) { 818 case ixgbe_mac_82598EB: 819 txctrl = IXGBE_READ_REG(hw, IXGBE_DCA_TXCTRL(j)); 820 break; 821 default: 822 txctrl = IXGBE_READ_REG(hw, IXGBE_DCA_TXCTRL_82599(j)); 823 break; 824 } 825 txctrl &= ~IXGBE_DCA_TXCTRL_DESC_WRO_EN; 826 switch (hw->mac.type) { 827 case ixgbe_mac_82598EB: 828 IXGBE_WRITE_REG(hw, IXGBE_DCA_TXCTRL(j), txctrl); 829 break; 830 default: 831 IXGBE_WRITE_REG(hw, IXGBE_DCA_TXCTRL_82599(j), txctrl); 832 break; 833 } 834 835 } 836 837 if (hw->mac.type != ixgbe_mac_82598EB) { 838 u32 dmatxctl, rttdcs; 839 840 dmatxctl = IXGBE_READ_REG(hw, IXGBE_DMATXCTL); 841 dmatxctl |= IXGBE_DMATXCTL_TE; 842 IXGBE_WRITE_REG(hw, IXGBE_DMATXCTL, dmatxctl); 843 /* Disable arbiter to set MTQC */ 844 rttdcs = IXGBE_READ_REG(hw, IXGBE_RTTDCS); 845 rttdcs |= IXGBE_RTTDCS_ARBDIS; 846 IXGBE_WRITE_REG(hw, IXGBE_RTTDCS, rttdcs); 847 IXGBE_WRITE_REG(hw, IXGBE_MTQC, 848 ixgbe_get_mtqc(sc->iov_mode)); 849 rttdcs &= ~IXGBE_RTTDCS_ARBDIS; 850 IXGBE_WRITE_REG(hw, IXGBE_RTTDCS, rttdcs); 851 } 852 853 } /* ixgbe_initialize_transmit_units */ 854 855 /************************************************************************ 856 * ixgbe_register 857 ************************************************************************/ 858 static void * 859 ixgbe_register(device_t dev) 860 { 861 return (&ixgbe_sctx_init); 862 } /* ixgbe_register */ 863 864 /************************************************************************ 865 * ixgbe_if_attach_pre - Device initialization routine, part 1 866 * 867 * Called when the driver is being loaded. 868 * Identifies the type of hardware, initializes the hardware, 869 * and initializes iflib structures. 870 * 871 * return 0 on success, positive on failure 872 ************************************************************************/ 873 static int 874 ixgbe_if_attach_pre(if_ctx_t ctx) 875 { 876 struct ixgbe_softc *sc; 877 device_t dev; 878 if_softc_ctx_t scctx; 879 struct ixgbe_hw *hw; 880 int error = 0; 881 u32 ctrl_ext; 882 size_t i; 883 884 INIT_DEBUGOUT("ixgbe_attach: begin"); 885 886 /* Allocate, clear, and link in our adapter structure */ 887 dev = iflib_get_dev(ctx); 888 sc = iflib_get_softc(ctx); 889 sc->hw.back = sc; 890 sc->ctx = ctx; 891 sc->dev = dev; 892 scctx = sc->shared = iflib_get_softc_ctx(ctx); 893 sc->media = iflib_get_media(ctx); 894 hw = &sc->hw; 895 896 /* Determine hardware revision */ 897 hw->vendor_id = pci_get_vendor(dev); 898 hw->device_id = pci_get_device(dev); 899 hw->revision_id = pci_get_revid(dev); 900 hw->subsystem_vendor_id = pci_get_subvendor(dev); 901 hw->subsystem_device_id = pci_get_subdevice(dev); 902 903 /* Do base PCI setup - map BAR0 */ 904 if (ixgbe_allocate_pci_resources(ctx)) { 905 device_printf(dev, "Allocation of PCI resources failed\n"); 906 return (ENXIO); 907 } 908 909 /* let hardware know driver is loaded */ 910 ctrl_ext = IXGBE_READ_REG(hw, IXGBE_CTRL_EXT); 911 ctrl_ext |= IXGBE_CTRL_EXT_DRV_LOAD; 912 IXGBE_WRITE_REG(hw, IXGBE_CTRL_EXT, ctrl_ext); 913 914 /* 915 * Initialize the shared code 916 */ 917 if (ixgbe_init_shared_code(hw) != 0) { 918 device_printf(dev, "Unable to initialize the shared code\n"); 919 error = ENXIO; 920 goto err_pci; 921 } 922 923 if (hw->mac.ops.fw_recovery_mode && hw->mac.ops.fw_recovery_mode(hw)) { 924 device_printf(dev, "Firmware recovery mode detected. Limiting " 925 "functionality.\nRefer to the Intel(R) Ethernet Adapters " 926 "and Devices User Guide for details on firmware recovery " 927 "mode."); 928 error = ENOSYS; 929 goto err_pci; 930 } 931 932 if (hw->mbx.ops[0].init_params) { 933 for (i = 0; i < sc->num_vfs; i++) 934 hw->mbx.ops[i].init_params(hw); 935 } 936 937 hw->allow_unsupported_sfp = allow_unsupported_sfp; 938 939 if (hw->mac.type != ixgbe_mac_82598EB) 940 hw->phy.smart_speed = ixgbe_smart_speed; 941 942 ixgbe_init_device_features(sc); 943 944 /* Enable WoL (if supported) */ 945 ixgbe_check_wol_support(sc); 946 947 /* Verify adapter fan is still functional (if applicable) */ 948 if (sc->feat_en & IXGBE_FEATURE_FAN_FAIL) { 949 u32 esdp = IXGBE_READ_REG(hw, IXGBE_ESDP); 950 ixgbe_check_fan_failure(sc, esdp, false); 951 } 952 953 /* Ensure SW/FW semaphore is free */ 954 ixgbe_init_swfw_semaphore(hw); 955 956 /* Set an initial default flow control value */ 957 hw->fc.requested_mode = ixgbe_flow_control; 958 959 hw->phy.reset_if_overtemp = true; 960 error = ixgbe_reset_hw(hw); 961 hw->phy.reset_if_overtemp = false; 962 if (error == IXGBE_ERR_SFP_NOT_PRESENT) { 963 /* 964 * No optics in this port, set up 965 * so the timer routine will probe 966 * for later insertion. 967 */ 968 sc->sfp_probe = true; 969 error = 0; 970 } else if (error == IXGBE_ERR_SFP_NOT_SUPPORTED) { 971 device_printf(dev, "Unsupported SFP+ module detected!\n"); 972 error = EIO; 973 goto err_pci; 974 } else if (error) { 975 device_printf(dev, "Hardware initialization failed\n"); 976 error = EIO; 977 goto err_pci; 978 } 979 980 /* Make sure we have a good EEPROM before we read from it */ 981 if (ixgbe_validate_eeprom_checksum(&sc->hw, NULL) < 0) { 982 device_printf(dev, "The EEPROM Checksum Is Not Valid\n"); 983 error = EIO; 984 goto err_pci; 985 } 986 987 error = ixgbe_start_hw(hw); 988 switch (error) { 989 case IXGBE_ERR_EEPROM_VERSION: 990 device_printf(dev, "This device is a pre-production adapter/LOM. Please be aware there may be issues associated with your hardware.\nIf you are experiencing problems please contact your Intel or hardware representative who provided you with this hardware.\n"); 991 break; 992 case IXGBE_ERR_SFP_NOT_SUPPORTED: 993 device_printf(dev, "Unsupported SFP+ Module\n"); 994 error = EIO; 995 goto err_pci; 996 case IXGBE_ERR_SFP_NOT_PRESENT: 997 device_printf(dev, "No SFP+ Module found\n"); 998 /* falls thru */ 999 default: 1000 break; 1001 } 1002 1003 /* Most of the iflib initialization... */ 1004 1005 iflib_set_mac(ctx, hw->mac.addr); 1006 switch (sc->hw.mac.type) { 1007 case ixgbe_mac_X550: 1008 case ixgbe_mac_X550EM_x: 1009 case ixgbe_mac_X550EM_a: 1010 scctx->isc_rss_table_size = 512; 1011 scctx->isc_ntxqsets_max = scctx->isc_nrxqsets_max = 64; 1012 break; 1013 default: 1014 scctx->isc_rss_table_size = 128; 1015 scctx->isc_ntxqsets_max = scctx->isc_nrxqsets_max = 16; 1016 } 1017 1018 /* Allow legacy interrupts */ 1019 ixgbe_txrx.ift_legacy_intr = ixgbe_intr; 1020 1021 scctx->isc_txqsizes[0] = 1022 roundup2(scctx->isc_ntxd[0] * sizeof(union ixgbe_adv_tx_desc) + 1023 sizeof(u32), DBA_ALIGN), 1024 scctx->isc_rxqsizes[0] = 1025 roundup2(scctx->isc_nrxd[0] * sizeof(union ixgbe_adv_rx_desc), 1026 DBA_ALIGN); 1027 1028 /* XXX */ 1029 scctx->isc_tx_csum_flags = CSUM_IP | CSUM_TCP | CSUM_UDP | CSUM_TSO | 1030 CSUM_IP6_TCP | CSUM_IP6_UDP | CSUM_IP6_TSO; 1031 if (sc->hw.mac.type == ixgbe_mac_82598EB) { 1032 scctx->isc_tx_nsegments = IXGBE_82598_SCATTER; 1033 } else { 1034 scctx->isc_tx_csum_flags |= CSUM_SCTP |CSUM_IP6_SCTP; 1035 scctx->isc_tx_nsegments = IXGBE_82599_SCATTER; 1036 } 1037 1038 scctx->isc_msix_bar = pci_msix_table_bar(dev); 1039 1040 scctx->isc_tx_tso_segments_max = scctx->isc_tx_nsegments; 1041 scctx->isc_tx_tso_size_max = IXGBE_TSO_SIZE; 1042 scctx->isc_tx_tso_segsize_max = PAGE_SIZE; 1043 1044 scctx->isc_txrx = &ixgbe_txrx; 1045 1046 scctx->isc_capabilities = scctx->isc_capenable = IXGBE_CAPS; 1047 1048 return (0); 1049 1050 err_pci: 1051 ctrl_ext = IXGBE_READ_REG(&sc->hw, IXGBE_CTRL_EXT); 1052 ctrl_ext &= ~IXGBE_CTRL_EXT_DRV_LOAD; 1053 IXGBE_WRITE_REG(&sc->hw, IXGBE_CTRL_EXT, ctrl_ext); 1054 ixgbe_free_pci_resources(ctx); 1055 1056 return (error); 1057 } /* ixgbe_if_attach_pre */ 1058 1059 /********************************************************************* 1060 * ixgbe_if_attach_post - Device initialization routine, part 2 1061 * 1062 * Called during driver load, but after interrupts and 1063 * resources have been allocated and configured. 1064 * Sets up some data structures not relevant to iflib. 1065 * 1066 * return 0 on success, positive on failure 1067 *********************************************************************/ 1068 static int 1069 ixgbe_if_attach_post(if_ctx_t ctx) 1070 { 1071 device_t dev; 1072 struct ixgbe_softc *sc; 1073 struct ixgbe_hw *hw; 1074 int error = 0; 1075 1076 dev = iflib_get_dev(ctx); 1077 sc = iflib_get_softc(ctx); 1078 hw = &sc->hw; 1079 1080 1081 if (sc->intr_type == IFLIB_INTR_LEGACY && 1082 (sc->feat_cap & IXGBE_FEATURE_LEGACY_IRQ) == 0) { 1083 device_printf(dev, "Device does not support legacy interrupts"); 1084 error = ENXIO; 1085 goto err; 1086 } 1087 1088 /* Allocate multicast array memory. */ 1089 sc->mta = malloc(sizeof(*sc->mta) * 1090 MAX_NUM_MULTICAST_ADDRESSES, M_IXGBE, M_NOWAIT); 1091 if (sc->mta == NULL) { 1092 device_printf(dev, "Can not allocate multicast setup array\n"); 1093 error = ENOMEM; 1094 goto err; 1095 } 1096 1097 /* hw.ix defaults init */ 1098 ixgbe_set_advertise(sc, ixgbe_advertise_speed); 1099 1100 /* Enable the optics for 82599 SFP+ fiber */ 1101 ixgbe_enable_tx_laser(hw); 1102 1103 /* Enable power to the phy. */ 1104 ixgbe_set_phy_power(hw, true); 1105 1106 ixgbe_initialize_iov(sc); 1107 1108 error = ixgbe_setup_interface(ctx); 1109 if (error) { 1110 device_printf(dev, "Interface setup failed: %d\n", error); 1111 goto err; 1112 } 1113 1114 ixgbe_if_update_admin_status(ctx); 1115 1116 /* Initialize statistics */ 1117 ixgbe_update_stats_counters(sc); 1118 ixgbe_add_hw_stats(sc); 1119 1120 /* Check PCIE slot type/speed/width */ 1121 ixgbe_get_slot_info(sc); 1122 1123 /* 1124 * Do time init and sysctl init here, but 1125 * only on the first port of a bypass sc. 1126 */ 1127 ixgbe_bypass_init(sc); 1128 1129 /* Display NVM and Option ROM versions */ 1130 ixgbe_print_fw_version(ctx); 1131 1132 /* Set an initial dmac value */ 1133 sc->dmac = 0; 1134 /* Set initial advertised speeds (if applicable) */ 1135 sc->advertise = ixgbe_get_default_advertise(sc); 1136 1137 if (sc->feat_cap & IXGBE_FEATURE_SRIOV) 1138 ixgbe_define_iov_schemas(dev, &error); 1139 1140 /* Add sysctls */ 1141 ixgbe_add_device_sysctls(ctx); 1142 1143 return (0); 1144 err: 1145 return (error); 1146 } /* ixgbe_if_attach_post */ 1147 1148 /************************************************************************ 1149 * ixgbe_check_wol_support 1150 * 1151 * Checks whether the adapter's ports are capable of 1152 * Wake On LAN by reading the adapter's NVM. 1153 * 1154 * Sets each port's hw->wol_enabled value depending 1155 * on the value read here. 1156 ************************************************************************/ 1157 static void 1158 ixgbe_check_wol_support(struct ixgbe_softc *sc) 1159 { 1160 struct ixgbe_hw *hw = &sc->hw; 1161 u16 dev_caps = 0; 1162 1163 /* Find out WoL support for port */ 1164 sc->wol_support = hw->wol_enabled = 0; 1165 ixgbe_get_device_caps(hw, &dev_caps); 1166 if ((dev_caps & IXGBE_DEVICE_CAPS_WOL_PORT0_1) || 1167 ((dev_caps & IXGBE_DEVICE_CAPS_WOL_PORT0) && 1168 hw->bus.func == 0)) 1169 sc->wol_support = hw->wol_enabled = 1; 1170 1171 /* Save initial wake up filter configuration */ 1172 sc->wufc = IXGBE_READ_REG(hw, IXGBE_WUFC); 1173 1174 return; 1175 } /* ixgbe_check_wol_support */ 1176 1177 /************************************************************************ 1178 * ixgbe_setup_interface 1179 * 1180 * Setup networking device structure and register an interface. 1181 ************************************************************************/ 1182 static int 1183 ixgbe_setup_interface(if_ctx_t ctx) 1184 { 1185 if_t ifp = iflib_get_ifp(ctx); 1186 struct ixgbe_softc *sc = iflib_get_softc(ctx); 1187 1188 INIT_DEBUGOUT("ixgbe_setup_interface: begin"); 1189 1190 if_setbaudrate(ifp, IF_Gbps(10)); 1191 1192 sc->max_frame_size = if_getmtu(ifp) + ETHER_HDR_LEN + ETHER_CRC_LEN; 1193 1194 sc->phy_layer = ixgbe_get_supported_physical_layer(&sc->hw); 1195 1196 ixgbe_add_media_types(ctx); 1197 1198 /* Autoselect media by default */ 1199 ifmedia_set(sc->media, IFM_ETHER | IFM_AUTO); 1200 1201 return (0); 1202 } /* ixgbe_setup_interface */ 1203 1204 /************************************************************************ 1205 * ixgbe_if_get_counter 1206 ************************************************************************/ 1207 static uint64_t 1208 ixgbe_if_get_counter(if_ctx_t ctx, ift_counter cnt) 1209 { 1210 struct ixgbe_softc *sc = iflib_get_softc(ctx); 1211 if_t ifp = iflib_get_ifp(ctx); 1212 1213 switch (cnt) { 1214 case IFCOUNTER_IPACKETS: 1215 return (sc->ipackets); 1216 case IFCOUNTER_OPACKETS: 1217 return (sc->opackets); 1218 case IFCOUNTER_IBYTES: 1219 return (sc->ibytes); 1220 case IFCOUNTER_OBYTES: 1221 return (sc->obytes); 1222 case IFCOUNTER_IMCASTS: 1223 return (sc->imcasts); 1224 case IFCOUNTER_OMCASTS: 1225 return (sc->omcasts); 1226 case IFCOUNTER_COLLISIONS: 1227 return (0); 1228 case IFCOUNTER_IQDROPS: 1229 return (sc->iqdrops); 1230 case IFCOUNTER_OQDROPS: 1231 return (0); 1232 case IFCOUNTER_IERRORS: 1233 return (sc->ierrors); 1234 default: 1235 return (if_get_counter_default(ifp, cnt)); 1236 } 1237 } /* ixgbe_if_get_counter */ 1238 1239 /************************************************************************ 1240 * ixgbe_if_i2c_req 1241 ************************************************************************/ 1242 static int 1243 ixgbe_if_i2c_req(if_ctx_t ctx, struct ifi2creq *req) 1244 { 1245 struct ixgbe_softc *sc = iflib_get_softc(ctx); 1246 struct ixgbe_hw *hw = &sc->hw; 1247 int i; 1248 1249 1250 if (hw->phy.ops.read_i2c_byte == NULL) 1251 return (ENXIO); 1252 for (i = 0; i < req->len; i++) 1253 hw->phy.ops.read_i2c_byte(hw, req->offset + i, 1254 req->dev_addr, &req->data[i]); 1255 return (0); 1256 } /* ixgbe_if_i2c_req */ 1257 1258 /* ixgbe_if_needs_restart - Tell iflib when the driver needs to be reinitialized 1259 * @ctx: iflib context 1260 * @event: event code to check 1261 * 1262 * Defaults to returning false for unknown events. 1263 * 1264 * @returns true if iflib needs to reinit the interface 1265 */ 1266 static bool 1267 ixgbe_if_needs_restart(if_ctx_t ctx __unused, enum iflib_restart_event event) 1268 { 1269 switch (event) { 1270 case IFLIB_RESTART_VLAN_CONFIG: 1271 default: 1272 return (false); 1273 } 1274 } 1275 1276 /************************************************************************ 1277 * ixgbe_add_media_types 1278 ************************************************************************/ 1279 static void 1280 ixgbe_add_media_types(if_ctx_t ctx) 1281 { 1282 struct ixgbe_softc *sc = iflib_get_softc(ctx); 1283 struct ixgbe_hw *hw = &sc->hw; 1284 device_t dev = iflib_get_dev(ctx); 1285 u64 layer; 1286 1287 layer = sc->phy_layer = ixgbe_get_supported_physical_layer(hw); 1288 1289 /* Media types with matching FreeBSD media defines */ 1290 if (layer & IXGBE_PHYSICAL_LAYER_10GBASE_T) 1291 ifmedia_add(sc->media, IFM_ETHER | IFM_10G_T, 0, NULL); 1292 if (layer & IXGBE_PHYSICAL_LAYER_1000BASE_T) 1293 ifmedia_add(sc->media, IFM_ETHER | IFM_1000_T, 0, NULL); 1294 if (layer & IXGBE_PHYSICAL_LAYER_100BASE_TX) 1295 ifmedia_add(sc->media, IFM_ETHER | IFM_100_TX, 0, NULL); 1296 if (layer & IXGBE_PHYSICAL_LAYER_10BASE_T) 1297 ifmedia_add(sc->media, IFM_ETHER | IFM_10_T, 0, NULL); 1298 1299 if (hw->mac.type == ixgbe_mac_X550) { 1300 ifmedia_add(sc->media, IFM_ETHER | IFM_2500_T, 0, NULL); 1301 ifmedia_add(sc->media, IFM_ETHER | IFM_5000_T, 0, NULL); 1302 } 1303 1304 if (layer & IXGBE_PHYSICAL_LAYER_SFP_PLUS_CU || 1305 layer & IXGBE_PHYSICAL_LAYER_SFP_ACTIVE_DA) 1306 ifmedia_add(sc->media, IFM_ETHER | IFM_10G_TWINAX, 0, 1307 NULL); 1308 1309 if (layer & IXGBE_PHYSICAL_LAYER_10GBASE_LR) { 1310 ifmedia_add(sc->media, IFM_ETHER | IFM_10G_LR, 0, NULL); 1311 if (hw->phy.multispeed_fiber) 1312 ifmedia_add(sc->media, IFM_ETHER | IFM_1000_LX, 0, 1313 NULL); 1314 } 1315 if (layer & IXGBE_PHYSICAL_LAYER_10GBASE_SR) { 1316 ifmedia_add(sc->media, IFM_ETHER | IFM_10G_SR, 0, NULL); 1317 if (hw->phy.multispeed_fiber) 1318 ifmedia_add(sc->media, IFM_ETHER | IFM_1000_SX, 0, 1319 NULL); 1320 } else if (layer & IXGBE_PHYSICAL_LAYER_1000BASE_SX) 1321 ifmedia_add(sc->media, IFM_ETHER | IFM_1000_SX, 0, NULL); 1322 if (layer & IXGBE_PHYSICAL_LAYER_10GBASE_CX4) 1323 ifmedia_add(sc->media, IFM_ETHER | IFM_10G_CX4, 0, NULL); 1324 1325 #ifdef IFM_ETH_XTYPE 1326 if (layer & IXGBE_PHYSICAL_LAYER_10GBASE_KR) 1327 ifmedia_add(sc->media, IFM_ETHER | IFM_10G_KR, 0, NULL); 1328 if (layer & IXGBE_PHYSICAL_LAYER_10GBASE_KX4) 1329 ifmedia_add( sc->media, IFM_ETHER | IFM_10G_KX4, 0, NULL); 1330 if (layer & IXGBE_PHYSICAL_LAYER_1000BASE_KX) 1331 ifmedia_add(sc->media, IFM_ETHER | IFM_1000_KX, 0, NULL); 1332 if (layer & IXGBE_PHYSICAL_LAYER_2500BASE_KX) 1333 ifmedia_add(sc->media, IFM_ETHER | IFM_2500_KX, 0, NULL); 1334 #else 1335 if (layer & IXGBE_PHYSICAL_LAYER_10GBASE_KR) { 1336 device_printf(dev, "Media supported: 10GbaseKR\n"); 1337 device_printf(dev, "10GbaseKR mapped to 10GbaseSR\n"); 1338 ifmedia_add(sc->media, IFM_ETHER | IFM_10G_SR, 0, NULL); 1339 } 1340 if (layer & IXGBE_PHYSICAL_LAYER_10GBASE_KX4) { 1341 device_printf(dev, "Media supported: 10GbaseKX4\n"); 1342 device_printf(dev, "10GbaseKX4 mapped to 10GbaseCX4\n"); 1343 ifmedia_add(sc->media, IFM_ETHER | IFM_10G_CX4, 0, NULL); 1344 } 1345 if (layer & IXGBE_PHYSICAL_LAYER_1000BASE_KX) { 1346 device_printf(dev, "Media supported: 1000baseKX\n"); 1347 device_printf(dev, "1000baseKX mapped to 1000baseCX\n"); 1348 ifmedia_add(sc->media, IFM_ETHER | IFM_1000_CX, 0, NULL); 1349 } 1350 if (layer & IXGBE_PHYSICAL_LAYER_2500BASE_KX) { 1351 device_printf(dev, "Media supported: 2500baseKX\n"); 1352 device_printf(dev, "2500baseKX mapped to 2500baseSX\n"); 1353 ifmedia_add(sc->media, IFM_ETHER | IFM_2500_SX, 0, NULL); 1354 } 1355 #endif 1356 if (layer & IXGBE_PHYSICAL_LAYER_1000BASE_BX) 1357 device_printf(dev, "Media supported: 1000baseBX\n"); 1358 1359 if (hw->device_id == IXGBE_DEV_ID_82598AT) { 1360 ifmedia_add(sc->media, IFM_ETHER | IFM_1000_T | IFM_FDX, 1361 0, NULL); 1362 ifmedia_add(sc->media, IFM_ETHER | IFM_1000_T, 0, NULL); 1363 } 1364 1365 ifmedia_add(sc->media, IFM_ETHER | IFM_AUTO, 0, NULL); 1366 } /* ixgbe_add_media_types */ 1367 1368 /************************************************************************ 1369 * ixgbe_is_sfp 1370 ************************************************************************/ 1371 static inline bool 1372 ixgbe_is_sfp(struct ixgbe_hw *hw) 1373 { 1374 switch (hw->mac.type) { 1375 case ixgbe_mac_82598EB: 1376 if (hw->phy.type == ixgbe_phy_nl) 1377 return (true); 1378 return (false); 1379 case ixgbe_mac_82599EB: 1380 switch (hw->mac.ops.get_media_type(hw)) { 1381 case ixgbe_media_type_fiber: 1382 case ixgbe_media_type_fiber_qsfp: 1383 return (true); 1384 default: 1385 return (false); 1386 } 1387 case ixgbe_mac_X550EM_x: 1388 case ixgbe_mac_X550EM_a: 1389 if (hw->mac.ops.get_media_type(hw) == ixgbe_media_type_fiber) 1390 return (true); 1391 return (false); 1392 default: 1393 return (false); 1394 } 1395 } /* ixgbe_is_sfp */ 1396 1397 /************************************************************************ 1398 * ixgbe_config_link 1399 ************************************************************************/ 1400 static void 1401 ixgbe_config_link(if_ctx_t ctx) 1402 { 1403 struct ixgbe_softc *sc = iflib_get_softc(ctx); 1404 struct ixgbe_hw *hw = &sc->hw; 1405 u32 autoneg, err = 0; 1406 bool sfp, negotiate; 1407 1408 sfp = ixgbe_is_sfp(hw); 1409 1410 if (sfp) { 1411 sc->task_requests |= IXGBE_REQUEST_TASK_MOD; 1412 iflib_admin_intr_deferred(ctx); 1413 } else { 1414 if (hw->mac.ops.check_link) 1415 err = ixgbe_check_link(hw, &sc->link_speed, 1416 &sc->link_up, false); 1417 if (err) 1418 return; 1419 autoneg = hw->phy.autoneg_advertised; 1420 if ((!autoneg) && (hw->mac.ops.get_link_capabilities)) 1421 err = hw->mac.ops.get_link_capabilities(hw, &autoneg, 1422 &negotiate); 1423 if (err) 1424 return; 1425 1426 if (hw->mac.type == ixgbe_mac_X550 && 1427 hw->phy.autoneg_advertised == 0) { 1428 /* 1429 * 2.5G and 5G autonegotiation speeds on X550 1430 * are disabled by default due to reported 1431 * interoperability issues with some switches. 1432 * 1433 * The second condition checks if any operations 1434 * involving setting autonegotiation speeds have 1435 * been performed prior to this ixgbe_config_link() 1436 * call. 1437 * 1438 * If hw->phy.autoneg_advertised does not 1439 * equal 0, this means that the user might have 1440 * set autonegotiation speeds via the sysctl 1441 * before bringing the interface up. In this 1442 * case, we should not disable 2.5G and 5G 1443 * since that speeds might be selected by the 1444 * user. 1445 * 1446 * Otherwise (i.e. if hw->phy.autoneg_advertised 1447 * is set to 0), it is the first time we set 1448 * autonegotiation preferences and the default 1449 * set of speeds should exclude 2.5G and 5G. 1450 */ 1451 autoneg &= ~(IXGBE_LINK_SPEED_2_5GB_FULL | 1452 IXGBE_LINK_SPEED_5GB_FULL); 1453 } 1454 1455 if (hw->mac.ops.setup_link) 1456 err = hw->mac.ops.setup_link(hw, autoneg, 1457 sc->link_up); 1458 } 1459 } /* ixgbe_config_link */ 1460 1461 /************************************************************************ 1462 * ixgbe_update_stats_counters - Update board statistics counters. 1463 ************************************************************************/ 1464 static void 1465 ixgbe_update_stats_counters(struct ixgbe_softc *sc) 1466 { 1467 struct ixgbe_hw *hw = &sc->hw; 1468 struct ixgbe_hw_stats *stats = &sc->stats.pf; 1469 u32 missed_rx = 0, bprc, lxon, lxoff, total; 1470 u32 lxoffrxc; 1471 u64 total_missed_rx = 0; 1472 1473 stats->crcerrs += IXGBE_READ_REG(hw, IXGBE_CRCERRS); 1474 stats->illerrc += IXGBE_READ_REG(hw, IXGBE_ILLERRC); 1475 stats->errbc += IXGBE_READ_REG(hw, IXGBE_ERRBC); 1476 stats->mspdc += IXGBE_READ_REG(hw, IXGBE_MSPDC); 1477 stats->mpc[0] += IXGBE_READ_REG(hw, IXGBE_MPC(0)); 1478 1479 for (int i = 0; i < 16; i++) { 1480 stats->qprc[i] += IXGBE_READ_REG(hw, IXGBE_QPRC(i)); 1481 stats->qptc[i] += IXGBE_READ_REG(hw, IXGBE_QPTC(i)); 1482 stats->qprdc[i] += IXGBE_READ_REG(hw, IXGBE_QPRDC(i)); 1483 } 1484 stats->mlfc += IXGBE_READ_REG(hw, IXGBE_MLFC); 1485 stats->mrfc += IXGBE_READ_REG(hw, IXGBE_MRFC); 1486 stats->rlec += IXGBE_READ_REG(hw, IXGBE_RLEC); 1487 1488 /* Hardware workaround, gprc counts missed packets */ 1489 stats->gprc += IXGBE_READ_REG(hw, IXGBE_GPRC); 1490 stats->gprc -= missed_rx; 1491 1492 if (hw->mac.type != ixgbe_mac_82598EB) { 1493 stats->gorc += IXGBE_READ_REG(hw, IXGBE_GORCL) + 1494 ((u64)IXGBE_READ_REG(hw, IXGBE_GORCH) << 32); 1495 stats->gotc += IXGBE_READ_REG(hw, IXGBE_GOTCL) + 1496 ((u64)IXGBE_READ_REG(hw, IXGBE_GOTCH) << 32); 1497 stats->tor += IXGBE_READ_REG(hw, IXGBE_TORL) + 1498 ((u64)IXGBE_READ_REG(hw, IXGBE_TORH) << 32); 1499 stats->lxonrxc += IXGBE_READ_REG(hw, IXGBE_LXONRXCNT); 1500 lxoffrxc = IXGBE_READ_REG(hw, IXGBE_LXOFFRXCNT); 1501 stats->lxoffrxc += lxoffrxc; 1502 } else { 1503 stats->lxonrxc += IXGBE_READ_REG(hw, IXGBE_LXONRXC); 1504 lxoffrxc = IXGBE_READ_REG(hw, IXGBE_LXOFFRXC); 1505 stats->lxoffrxc += lxoffrxc; 1506 /* 82598 only has a counter in the high register */ 1507 stats->gorc += IXGBE_READ_REG(hw, IXGBE_GORCH); 1508 stats->gotc += IXGBE_READ_REG(hw, IXGBE_GOTCH); 1509 stats->tor += IXGBE_READ_REG(hw, IXGBE_TORH); 1510 } 1511 1512 /* 1513 * For watchdog management we need to know if we have been paused 1514 * during the last interval, so capture that here. 1515 */ 1516 if (lxoffrxc) 1517 sc->shared->isc_pause_frames = 1; 1518 1519 /* 1520 * Workaround: mprc hardware is incorrectly counting 1521 * broadcasts, so for now we subtract those. 1522 */ 1523 bprc = IXGBE_READ_REG(hw, IXGBE_BPRC); 1524 stats->bprc += bprc; 1525 stats->mprc += IXGBE_READ_REG(hw, IXGBE_MPRC); 1526 if (hw->mac.type == ixgbe_mac_82598EB) 1527 stats->mprc -= bprc; 1528 1529 stats->prc64 += IXGBE_READ_REG(hw, IXGBE_PRC64); 1530 stats->prc127 += IXGBE_READ_REG(hw, IXGBE_PRC127); 1531 stats->prc255 += IXGBE_READ_REG(hw, IXGBE_PRC255); 1532 stats->prc511 += IXGBE_READ_REG(hw, IXGBE_PRC511); 1533 stats->prc1023 += IXGBE_READ_REG(hw, IXGBE_PRC1023); 1534 stats->prc1522 += IXGBE_READ_REG(hw, IXGBE_PRC1522); 1535 1536 lxon = IXGBE_READ_REG(hw, IXGBE_LXONTXC); 1537 stats->lxontxc += lxon; 1538 lxoff = IXGBE_READ_REG(hw, IXGBE_LXOFFTXC); 1539 stats->lxofftxc += lxoff; 1540 total = lxon + lxoff; 1541 1542 stats->gptc += IXGBE_READ_REG(hw, IXGBE_GPTC); 1543 stats->mptc += IXGBE_READ_REG(hw, IXGBE_MPTC); 1544 stats->ptc64 += IXGBE_READ_REG(hw, IXGBE_PTC64); 1545 stats->gptc -= total; 1546 stats->mptc -= total; 1547 stats->ptc64 -= total; 1548 stats->gotc -= total * ETHER_MIN_LEN; 1549 1550 stats->ruc += IXGBE_READ_REG(hw, IXGBE_RUC); 1551 stats->rfc += IXGBE_READ_REG(hw, IXGBE_RFC); 1552 stats->roc += IXGBE_READ_REG(hw, IXGBE_ROC); 1553 stats->rjc += IXGBE_READ_REG(hw, IXGBE_RJC); 1554 stats->mngprc += IXGBE_READ_REG(hw, IXGBE_MNGPRC); 1555 stats->mngpdc += IXGBE_READ_REG(hw, IXGBE_MNGPDC); 1556 stats->mngptc += IXGBE_READ_REG(hw, IXGBE_MNGPTC); 1557 stats->tpr += IXGBE_READ_REG(hw, IXGBE_TPR); 1558 stats->tpt += IXGBE_READ_REG(hw, IXGBE_TPT); 1559 stats->ptc127 += IXGBE_READ_REG(hw, IXGBE_PTC127); 1560 stats->ptc255 += IXGBE_READ_REG(hw, IXGBE_PTC255); 1561 stats->ptc511 += IXGBE_READ_REG(hw, IXGBE_PTC511); 1562 stats->ptc1023 += IXGBE_READ_REG(hw, IXGBE_PTC1023); 1563 stats->ptc1522 += IXGBE_READ_REG(hw, IXGBE_PTC1522); 1564 stats->bptc += IXGBE_READ_REG(hw, IXGBE_BPTC); 1565 stats->xec += IXGBE_READ_REG(hw, IXGBE_XEC); 1566 stats->fccrc += IXGBE_READ_REG(hw, IXGBE_FCCRC); 1567 stats->fclast += IXGBE_READ_REG(hw, IXGBE_FCLAST); 1568 /* Only read FCOE on 82599 */ 1569 if (hw->mac.type != ixgbe_mac_82598EB) { 1570 stats->fcoerpdc += IXGBE_READ_REG(hw, IXGBE_FCOERPDC); 1571 stats->fcoeprc += IXGBE_READ_REG(hw, IXGBE_FCOEPRC); 1572 stats->fcoeptc += IXGBE_READ_REG(hw, IXGBE_FCOEPTC); 1573 stats->fcoedwrc += IXGBE_READ_REG(hw, IXGBE_FCOEDWRC); 1574 stats->fcoedwtc += IXGBE_READ_REG(hw, IXGBE_FCOEDWTC); 1575 } 1576 1577 /* Fill out the OS statistics structure */ 1578 IXGBE_SET_IPACKETS(sc, stats->gprc); 1579 IXGBE_SET_OPACKETS(sc, stats->gptc); 1580 IXGBE_SET_IBYTES(sc, stats->gorc); 1581 IXGBE_SET_OBYTES(sc, stats->gotc); 1582 IXGBE_SET_IMCASTS(sc, stats->mprc); 1583 IXGBE_SET_OMCASTS(sc, stats->mptc); 1584 IXGBE_SET_COLLISIONS(sc, 0); 1585 IXGBE_SET_IQDROPS(sc, total_missed_rx); 1586 1587 /* 1588 * Aggregate following types of errors as RX errors: 1589 * - CRC error count, 1590 * - illegal byte error count, 1591 * - missed packets count, 1592 * - length error count, 1593 * - undersized packets count, 1594 * - fragmented packets count, 1595 * - oversized packets count, 1596 * - jabber count. 1597 */ 1598 IXGBE_SET_IERRORS(sc, stats->crcerrs + stats->illerrc + 1599 stats->mpc[0] + stats->rlec + stats->ruc + stats->rfc + stats->roc + 1600 stats->rjc); 1601 } /* ixgbe_update_stats_counters */ 1602 1603 /************************************************************************ 1604 * ixgbe_add_hw_stats 1605 * 1606 * Add sysctl variables, one per statistic, to the system. 1607 ************************************************************************/ 1608 static void 1609 ixgbe_add_hw_stats(struct ixgbe_softc *sc) 1610 { 1611 device_t dev = iflib_get_dev(sc->ctx); 1612 struct ix_rx_queue *rx_que; 1613 struct ix_tx_queue *tx_que; 1614 struct sysctl_ctx_list *ctx = device_get_sysctl_ctx(dev); 1615 struct sysctl_oid *tree = device_get_sysctl_tree(dev); 1616 struct sysctl_oid_list *child = SYSCTL_CHILDREN(tree); 1617 struct ixgbe_hw_stats *stats = &sc->stats.pf; 1618 struct sysctl_oid *stat_node, *queue_node; 1619 struct sysctl_oid_list *stat_list, *queue_list; 1620 int i; 1621 1622 #define QUEUE_NAME_LEN 32 1623 char namebuf[QUEUE_NAME_LEN]; 1624 1625 /* Driver Statistics */ 1626 SYSCTL_ADD_ULONG(ctx, child, OID_AUTO, "dropped", 1627 CTLFLAG_RD, &sc->dropped_pkts, "Driver dropped packets"); 1628 SYSCTL_ADD_ULONG(ctx, child, OID_AUTO, "watchdog_events", 1629 CTLFLAG_RD, &sc->watchdog_events, "Watchdog timeouts"); 1630 SYSCTL_ADD_ULONG(ctx, child, OID_AUTO, "link_irq", 1631 CTLFLAG_RD, &sc->link_irq, "Link MSI-X IRQ Handled"); 1632 1633 for (i = 0, tx_que = sc->tx_queues; i < sc->num_tx_queues; i++, tx_que++) { 1634 struct tx_ring *txr = &tx_que->txr; 1635 snprintf(namebuf, QUEUE_NAME_LEN, "queue%d", i); 1636 queue_node = SYSCTL_ADD_NODE(ctx, child, OID_AUTO, namebuf, 1637 CTLFLAG_RD | CTLFLAG_MPSAFE, NULL, "Queue Name"); 1638 queue_list = SYSCTL_CHILDREN(queue_node); 1639 1640 SYSCTL_ADD_PROC(ctx, queue_list, OID_AUTO, "txd_head", 1641 CTLTYPE_UINT | CTLFLAG_RD | CTLFLAG_NEEDGIANT, txr, 0, 1642 ixgbe_sysctl_tdh_handler, "IU", "Transmit Descriptor Head"); 1643 SYSCTL_ADD_PROC(ctx, queue_list, OID_AUTO, "txd_tail", 1644 CTLTYPE_UINT | CTLFLAG_RD | CTLFLAG_NEEDGIANT, txr, 0, 1645 ixgbe_sysctl_tdt_handler, "IU", "Transmit Descriptor Tail"); 1646 SYSCTL_ADD_UQUAD(ctx, queue_list, OID_AUTO, "tso_tx", 1647 CTLFLAG_RD, &txr->tso_tx, "TSO"); 1648 SYSCTL_ADD_UQUAD(ctx, queue_list, OID_AUTO, "tx_packets", 1649 CTLFLAG_RD, &txr->total_packets, 1650 "Queue Packets Transmitted"); 1651 } 1652 1653 for (i = 0, rx_que = sc->rx_queues; i < sc->num_rx_queues; i++, rx_que++) { 1654 struct rx_ring *rxr = &rx_que->rxr; 1655 snprintf(namebuf, QUEUE_NAME_LEN, "queue%d", i); 1656 queue_node = SYSCTL_ADD_NODE(ctx, child, OID_AUTO, namebuf, 1657 CTLFLAG_RD | CTLFLAG_MPSAFE, NULL, "Queue Name"); 1658 queue_list = SYSCTL_CHILDREN(queue_node); 1659 1660 SYSCTL_ADD_PROC(ctx, queue_list, OID_AUTO, "interrupt_rate", 1661 CTLTYPE_UINT | CTLFLAG_RW | CTLFLAG_NEEDGIANT, 1662 &sc->rx_queues[i], 0, 1663 ixgbe_sysctl_interrupt_rate_handler, "IU", 1664 "Interrupt Rate"); 1665 SYSCTL_ADD_UQUAD(ctx, queue_list, OID_AUTO, "irqs", 1666 CTLFLAG_RD, &(sc->rx_queues[i].irqs), 1667 "irqs on this queue"); 1668 SYSCTL_ADD_PROC(ctx, queue_list, OID_AUTO, "rxd_head", 1669 CTLTYPE_UINT | CTLFLAG_RD | CTLFLAG_NEEDGIANT, rxr, 0, 1670 ixgbe_sysctl_rdh_handler, "IU", "Receive Descriptor Head"); 1671 SYSCTL_ADD_PROC(ctx, queue_list, OID_AUTO, "rxd_tail", 1672 CTLTYPE_UINT | CTLFLAG_RD | CTLFLAG_NEEDGIANT, rxr, 0, 1673 ixgbe_sysctl_rdt_handler, "IU", "Receive Descriptor Tail"); 1674 SYSCTL_ADD_UQUAD(ctx, queue_list, OID_AUTO, "rx_packets", 1675 CTLFLAG_RD, &rxr->rx_packets, "Queue Packets Received"); 1676 SYSCTL_ADD_UQUAD(ctx, queue_list, OID_AUTO, "rx_bytes", 1677 CTLFLAG_RD, &rxr->rx_bytes, "Queue Bytes Received"); 1678 SYSCTL_ADD_UQUAD(ctx, queue_list, OID_AUTO, "rx_copies", 1679 CTLFLAG_RD, &rxr->rx_copies, "Copied RX Frames"); 1680 SYSCTL_ADD_UQUAD(ctx, queue_list, OID_AUTO, "rx_discarded", 1681 CTLFLAG_RD, &rxr->rx_discarded, "Discarded RX packets"); 1682 } 1683 1684 /* MAC stats get their own sub node */ 1685 1686 stat_node = SYSCTL_ADD_NODE(ctx, child, OID_AUTO, "mac_stats", 1687 CTLFLAG_RD | CTLFLAG_MPSAFE, NULL, "MAC Statistics"); 1688 stat_list = SYSCTL_CHILDREN(stat_node); 1689 1690 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "rx_errs", 1691 CTLFLAG_RD, &sc->ierrors, IXGBE_SYSCTL_DESC_RX_ERRS); 1692 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "crc_errs", 1693 CTLFLAG_RD, &stats->crcerrs, "CRC Errors"); 1694 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "ill_errs", 1695 CTLFLAG_RD, &stats->illerrc, "Illegal Byte Errors"); 1696 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "byte_errs", 1697 CTLFLAG_RD, &stats->errbc, "Byte Errors"); 1698 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "short_discards", 1699 CTLFLAG_RD, &stats->mspdc, "MAC Short Packets Discarded"); 1700 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "local_faults", 1701 CTLFLAG_RD, &stats->mlfc, "MAC Local Faults"); 1702 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "remote_faults", 1703 CTLFLAG_RD, &stats->mrfc, "MAC Remote Faults"); 1704 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "rec_len_errs", 1705 CTLFLAG_RD, &stats->rlec, "Receive Length Errors"); 1706 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "rx_missed_packets", 1707 CTLFLAG_RD, &stats->mpc[0], "RX Missed Packet Count"); 1708 1709 /* Flow Control stats */ 1710 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "xon_txd", 1711 CTLFLAG_RD, &stats->lxontxc, "Link XON Transmitted"); 1712 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "xon_recvd", 1713 CTLFLAG_RD, &stats->lxonrxc, "Link XON Received"); 1714 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "xoff_txd", 1715 CTLFLAG_RD, &stats->lxofftxc, "Link XOFF Transmitted"); 1716 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "xoff_recvd", 1717 CTLFLAG_RD, &stats->lxoffrxc, "Link XOFF Received"); 1718 1719 /* Packet Reception Stats */ 1720 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "total_octets_rcvd", 1721 CTLFLAG_RD, &stats->tor, "Total Octets Received"); 1722 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "good_octets_rcvd", 1723 CTLFLAG_RD, &stats->gorc, "Good Octets Received"); 1724 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "total_pkts_rcvd", 1725 CTLFLAG_RD, &stats->tpr, "Total Packets Received"); 1726 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "good_pkts_rcvd", 1727 CTLFLAG_RD, &stats->gprc, "Good Packets Received"); 1728 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "mcast_pkts_rcvd", 1729 CTLFLAG_RD, &stats->mprc, "Multicast Packets Received"); 1730 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "bcast_pkts_rcvd", 1731 CTLFLAG_RD, &stats->bprc, "Broadcast Packets Received"); 1732 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "rx_frames_64", 1733 CTLFLAG_RD, &stats->prc64, "64 byte frames received "); 1734 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "rx_frames_65_127", 1735 CTLFLAG_RD, &stats->prc127, "65-127 byte frames received"); 1736 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "rx_frames_128_255", 1737 CTLFLAG_RD, &stats->prc255, "128-255 byte frames received"); 1738 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "rx_frames_256_511", 1739 CTLFLAG_RD, &stats->prc511, "256-511 byte frames received"); 1740 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "rx_frames_512_1023", 1741 CTLFLAG_RD, &stats->prc1023, "512-1023 byte frames received"); 1742 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "rx_frames_1024_1522", 1743 CTLFLAG_RD, &stats->prc1522, "1023-1522 byte frames received"); 1744 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "recv_undersized", 1745 CTLFLAG_RD, &stats->ruc, "Receive Undersized"); 1746 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "recv_fragmented", 1747 CTLFLAG_RD, &stats->rfc, "Fragmented Packets Received "); 1748 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "recv_oversized", 1749 CTLFLAG_RD, &stats->roc, "Oversized Packets Received"); 1750 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "recv_jabberd", 1751 CTLFLAG_RD, &stats->rjc, "Received Jabber"); 1752 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "management_pkts_rcvd", 1753 CTLFLAG_RD, &stats->mngprc, "Management Packets Received"); 1754 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "management_pkts_drpd", 1755 CTLFLAG_RD, &stats->mngptc, "Management Packets Dropped"); 1756 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "checksum_errs", 1757 CTLFLAG_RD, &stats->xec, "Checksum Errors"); 1758 1759 /* Packet Transmission Stats */ 1760 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "good_octets_txd", 1761 CTLFLAG_RD, &stats->gotc, "Good Octets Transmitted"); 1762 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "total_pkts_txd", 1763 CTLFLAG_RD, &stats->tpt, "Total Packets Transmitted"); 1764 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "good_pkts_txd", 1765 CTLFLAG_RD, &stats->gptc, "Good Packets Transmitted"); 1766 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "bcast_pkts_txd", 1767 CTLFLAG_RD, &stats->bptc, "Broadcast Packets Transmitted"); 1768 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "mcast_pkts_txd", 1769 CTLFLAG_RD, &stats->mptc, "Multicast Packets Transmitted"); 1770 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "management_pkts_txd", 1771 CTLFLAG_RD, &stats->mngptc, "Management Packets Transmitted"); 1772 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "tx_frames_64", 1773 CTLFLAG_RD, &stats->ptc64, "64 byte frames transmitted "); 1774 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "tx_frames_65_127", 1775 CTLFLAG_RD, &stats->ptc127, "65-127 byte frames transmitted"); 1776 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "tx_frames_128_255", 1777 CTLFLAG_RD, &stats->ptc255, "128-255 byte frames transmitted"); 1778 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "tx_frames_256_511", 1779 CTLFLAG_RD, &stats->ptc511, "256-511 byte frames transmitted"); 1780 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "tx_frames_512_1023", 1781 CTLFLAG_RD, &stats->ptc1023, "512-1023 byte frames transmitted"); 1782 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "tx_frames_1024_1522", 1783 CTLFLAG_RD, &stats->ptc1522, "1024-1522 byte frames transmitted"); 1784 } /* ixgbe_add_hw_stats */ 1785 1786 /************************************************************************ 1787 * ixgbe_sysctl_tdh_handler - Transmit Descriptor Head handler function 1788 * 1789 * Retrieves the TDH value from the hardware 1790 ************************************************************************/ 1791 static int 1792 ixgbe_sysctl_tdh_handler(SYSCTL_HANDLER_ARGS) 1793 { 1794 struct tx_ring *txr = ((struct tx_ring *)oidp->oid_arg1); 1795 int error; 1796 unsigned int val; 1797 1798 if (!txr) 1799 return (0); 1800 1801 val = IXGBE_READ_REG(&txr->sc->hw, IXGBE_TDH(txr->me)); 1802 error = sysctl_handle_int(oidp, &val, 0, req); 1803 if (error || !req->newptr) 1804 return error; 1805 1806 return (0); 1807 } /* ixgbe_sysctl_tdh_handler */ 1808 1809 /************************************************************************ 1810 * ixgbe_sysctl_tdt_handler - Transmit Descriptor Tail handler function 1811 * 1812 * Retrieves the TDT value from the hardware 1813 ************************************************************************/ 1814 static int 1815 ixgbe_sysctl_tdt_handler(SYSCTL_HANDLER_ARGS) 1816 { 1817 struct tx_ring *txr = ((struct tx_ring *)oidp->oid_arg1); 1818 int error; 1819 unsigned int val; 1820 1821 if (!txr) 1822 return (0); 1823 1824 val = IXGBE_READ_REG(&txr->sc->hw, IXGBE_TDT(txr->me)); 1825 error = sysctl_handle_int(oidp, &val, 0, req); 1826 if (error || !req->newptr) 1827 return error; 1828 1829 return (0); 1830 } /* ixgbe_sysctl_tdt_handler */ 1831 1832 /************************************************************************ 1833 * ixgbe_sysctl_rdh_handler - Receive Descriptor Head handler function 1834 * 1835 * Retrieves the RDH value from the hardware 1836 ************************************************************************/ 1837 static int 1838 ixgbe_sysctl_rdh_handler(SYSCTL_HANDLER_ARGS) 1839 { 1840 struct rx_ring *rxr = ((struct rx_ring *)oidp->oid_arg1); 1841 int error; 1842 unsigned int val; 1843 1844 if (!rxr) 1845 return (0); 1846 1847 val = IXGBE_READ_REG(&rxr->sc->hw, IXGBE_RDH(rxr->me)); 1848 error = sysctl_handle_int(oidp, &val, 0, req); 1849 if (error || !req->newptr) 1850 return error; 1851 1852 return (0); 1853 } /* ixgbe_sysctl_rdh_handler */ 1854 1855 /************************************************************************ 1856 * ixgbe_sysctl_rdt_handler - Receive Descriptor Tail handler function 1857 * 1858 * Retrieves the RDT value from the hardware 1859 ************************************************************************/ 1860 static int 1861 ixgbe_sysctl_rdt_handler(SYSCTL_HANDLER_ARGS) 1862 { 1863 struct rx_ring *rxr = ((struct rx_ring *)oidp->oid_arg1); 1864 int error; 1865 unsigned int val; 1866 1867 if (!rxr) 1868 return (0); 1869 1870 val = IXGBE_READ_REG(&rxr->sc->hw, IXGBE_RDT(rxr->me)); 1871 error = sysctl_handle_int(oidp, &val, 0, req); 1872 if (error || !req->newptr) 1873 return error; 1874 1875 return (0); 1876 } /* ixgbe_sysctl_rdt_handler */ 1877 1878 /************************************************************************ 1879 * ixgbe_if_vlan_register 1880 * 1881 * Run via vlan config EVENT, it enables us to use the 1882 * HW Filter table since we can get the vlan id. This 1883 * just creates the entry in the soft version of the 1884 * VFTA, init will repopulate the real table. 1885 ************************************************************************/ 1886 static void 1887 ixgbe_if_vlan_register(if_ctx_t ctx, u16 vtag) 1888 { 1889 struct ixgbe_softc *sc = iflib_get_softc(ctx); 1890 u16 index, bit; 1891 1892 index = (vtag >> 5) & 0x7F; 1893 bit = vtag & 0x1F; 1894 sc->shadow_vfta[index] |= (1 << bit); 1895 ++sc->num_vlans; 1896 ixgbe_setup_vlan_hw_support(ctx); 1897 } /* ixgbe_if_vlan_register */ 1898 1899 /************************************************************************ 1900 * ixgbe_if_vlan_unregister 1901 * 1902 * Run via vlan unconfig EVENT, remove our entry in the soft vfta. 1903 ************************************************************************/ 1904 static void 1905 ixgbe_if_vlan_unregister(if_ctx_t ctx, u16 vtag) 1906 { 1907 struct ixgbe_softc *sc = iflib_get_softc(ctx); 1908 u16 index, bit; 1909 1910 index = (vtag >> 5) & 0x7F; 1911 bit = vtag & 0x1F; 1912 sc->shadow_vfta[index] &= ~(1 << bit); 1913 --sc->num_vlans; 1914 /* Re-init to load the changes */ 1915 ixgbe_setup_vlan_hw_support(ctx); 1916 } /* ixgbe_if_vlan_unregister */ 1917 1918 /************************************************************************ 1919 * ixgbe_setup_vlan_hw_support 1920 ************************************************************************/ 1921 static void 1922 ixgbe_setup_vlan_hw_support(if_ctx_t ctx) 1923 { 1924 if_t ifp = iflib_get_ifp(ctx); 1925 struct ixgbe_softc *sc = iflib_get_softc(ctx); 1926 struct ixgbe_hw *hw = &sc->hw; 1927 struct rx_ring *rxr; 1928 int i; 1929 u32 ctrl; 1930 1931 1932 /* 1933 * We get here thru init_locked, meaning 1934 * a soft reset, this has already cleared 1935 * the VFTA and other state, so if there 1936 * have been no vlan's registered do nothing. 1937 */ 1938 if (sc->num_vlans == 0 || (if_getcapenable(ifp) & IFCAP_VLAN_HWTAGGING) == 0) { 1939 /* Clear the vlan hw flag */ 1940 for (i = 0; i < sc->num_rx_queues; i++) { 1941 rxr = &sc->rx_queues[i].rxr; 1942 /* On 82599 the VLAN enable is per/queue in RXDCTL */ 1943 if (hw->mac.type != ixgbe_mac_82598EB) { 1944 ctrl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(rxr->me)); 1945 ctrl &= ~IXGBE_RXDCTL_VME; 1946 IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(rxr->me), ctrl); 1947 } 1948 rxr->vtag_strip = false; 1949 } 1950 ctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL); 1951 /* Enable the Filter Table if enabled */ 1952 ctrl |= IXGBE_VLNCTRL_CFIEN; 1953 ctrl &= ~IXGBE_VLNCTRL_VFE; 1954 if (hw->mac.type == ixgbe_mac_82598EB) 1955 ctrl &= ~IXGBE_VLNCTRL_VME; 1956 IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, ctrl); 1957 return; 1958 } 1959 1960 /* Setup the queues for vlans */ 1961 if (if_getcapenable(ifp) & IFCAP_VLAN_HWTAGGING) { 1962 for (i = 0; i < sc->num_rx_queues; i++) { 1963 rxr = &sc->rx_queues[i].rxr; 1964 /* On 82599 the VLAN enable is per/queue in RXDCTL */ 1965 if (hw->mac.type != ixgbe_mac_82598EB) { 1966 ctrl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(rxr->me)); 1967 ctrl |= IXGBE_RXDCTL_VME; 1968 IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(rxr->me), ctrl); 1969 } 1970 rxr->vtag_strip = true; 1971 } 1972 } 1973 1974 if ((if_getcapenable(ifp) & IFCAP_VLAN_HWFILTER) == 0) 1975 return; 1976 /* 1977 * A soft reset zero's out the VFTA, so 1978 * we need to repopulate it now. 1979 */ 1980 for (i = 0; i < IXGBE_VFTA_SIZE; i++) 1981 if (sc->shadow_vfta[i] != 0) 1982 IXGBE_WRITE_REG(hw, IXGBE_VFTA(i), 1983 sc->shadow_vfta[i]); 1984 1985 ctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL); 1986 /* Enable the Filter Table if enabled */ 1987 if (if_getcapenable(ifp) & IFCAP_VLAN_HWFILTER) { 1988 ctrl &= ~IXGBE_VLNCTRL_CFIEN; 1989 ctrl |= IXGBE_VLNCTRL_VFE; 1990 } 1991 if (hw->mac.type == ixgbe_mac_82598EB) 1992 ctrl |= IXGBE_VLNCTRL_VME; 1993 IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, ctrl); 1994 } /* ixgbe_setup_vlan_hw_support */ 1995 1996 /************************************************************************ 1997 * ixgbe_get_slot_info 1998 * 1999 * Get the width and transaction speed of 2000 * the slot this adapter is plugged into. 2001 ************************************************************************/ 2002 static void 2003 ixgbe_get_slot_info(struct ixgbe_softc *sc) 2004 { 2005 device_t dev = iflib_get_dev(sc->ctx); 2006 struct ixgbe_hw *hw = &sc->hw; 2007 int bus_info_valid = true; 2008 u32 offset; 2009 u16 link; 2010 2011 /* Some devices are behind an internal bridge */ 2012 switch (hw->device_id) { 2013 case IXGBE_DEV_ID_82599_SFP_SF_QP: 2014 case IXGBE_DEV_ID_82599_QSFP_SF_QP: 2015 goto get_parent_info; 2016 default: 2017 break; 2018 } 2019 2020 ixgbe_get_bus_info(hw); 2021 2022 /* 2023 * Some devices don't use PCI-E, but there is no need 2024 * to display "Unknown" for bus speed and width. 2025 */ 2026 switch (hw->mac.type) { 2027 case ixgbe_mac_X550EM_x: 2028 case ixgbe_mac_X550EM_a: 2029 return; 2030 default: 2031 goto display; 2032 } 2033 2034 get_parent_info: 2035 /* 2036 * For the Quad port adapter we need to parse back 2037 * up the PCI tree to find the speed of the expansion 2038 * slot into which this adapter is plugged. A bit more work. 2039 */ 2040 dev = device_get_parent(device_get_parent(dev)); 2041 #ifdef IXGBE_DEBUG 2042 device_printf(dev, "parent pcib = %x,%x,%x\n", pci_get_bus(dev), 2043 pci_get_slot(dev), pci_get_function(dev)); 2044 #endif 2045 dev = device_get_parent(device_get_parent(dev)); 2046 #ifdef IXGBE_DEBUG 2047 device_printf(dev, "slot pcib = %x,%x,%x\n", pci_get_bus(dev), 2048 pci_get_slot(dev), pci_get_function(dev)); 2049 #endif 2050 /* Now get the PCI Express Capabilities offset */ 2051 if (pci_find_cap(dev, PCIY_EXPRESS, &offset)) { 2052 /* 2053 * Hmm...can't get PCI-Express capabilities. 2054 * Falling back to default method. 2055 */ 2056 bus_info_valid = false; 2057 ixgbe_get_bus_info(hw); 2058 goto display; 2059 } 2060 /* ...and read the Link Status Register */ 2061 link = pci_read_config(dev, offset + PCIER_LINK_STA, 2); 2062 ixgbe_set_pci_config_data_generic(hw, link); 2063 2064 display: 2065 device_printf(dev, "PCI Express Bus: Speed %s %s\n", 2066 ((hw->bus.speed == ixgbe_bus_speed_8000) ? "8.0GT/s" : 2067 (hw->bus.speed == ixgbe_bus_speed_5000) ? "5.0GT/s" : 2068 (hw->bus.speed == ixgbe_bus_speed_2500) ? "2.5GT/s" : 2069 "Unknown"), 2070 ((hw->bus.width == ixgbe_bus_width_pcie_x8) ? "Width x8" : 2071 (hw->bus.width == ixgbe_bus_width_pcie_x4) ? "Width x4" : 2072 (hw->bus.width == ixgbe_bus_width_pcie_x1) ? "Width x1" : 2073 "Unknown")); 2074 2075 if (bus_info_valid) { 2076 if ((hw->device_id != IXGBE_DEV_ID_82599_SFP_SF_QP) && 2077 ((hw->bus.width <= ixgbe_bus_width_pcie_x4) && 2078 (hw->bus.speed == ixgbe_bus_speed_2500))) { 2079 device_printf(dev, "PCI-Express bandwidth available for this card\n is not sufficient for optimal performance.\n"); 2080 device_printf(dev, "For optimal performance a x8 PCIE, or x4 PCIE Gen2 slot is required.\n"); 2081 } 2082 if ((hw->device_id == IXGBE_DEV_ID_82599_SFP_SF_QP) && 2083 ((hw->bus.width <= ixgbe_bus_width_pcie_x8) && 2084 (hw->bus.speed < ixgbe_bus_speed_8000))) { 2085 device_printf(dev, "PCI-Express bandwidth available for this card\n is not sufficient for optimal performance.\n"); 2086 device_printf(dev, "For optimal performance a x8 PCIE Gen3 slot is required.\n"); 2087 } 2088 } else 2089 device_printf(dev, "Unable to determine slot speed/width. The speed/width reported are that of the internal switch.\n"); 2090 2091 return; 2092 } /* ixgbe_get_slot_info */ 2093 2094 /************************************************************************ 2095 * ixgbe_if_msix_intr_assign 2096 * 2097 * Setup MSI-X Interrupt resources and handlers 2098 ************************************************************************/ 2099 static int 2100 ixgbe_if_msix_intr_assign(if_ctx_t ctx, int msix) 2101 { 2102 struct ixgbe_softc *sc = iflib_get_softc(ctx); 2103 struct ix_rx_queue *rx_que = sc->rx_queues; 2104 struct ix_tx_queue *tx_que; 2105 int error, rid, vector = 0; 2106 char buf[16]; 2107 2108 /* Admin Que is vector 0*/ 2109 rid = vector + 1; 2110 for (int i = 0; i < sc->num_rx_queues; i++, vector++, rx_que++) { 2111 rid = vector + 1; 2112 2113 snprintf(buf, sizeof(buf), "rxq%d", i); 2114 error = iflib_irq_alloc_generic(ctx, &rx_que->que_irq, rid, 2115 IFLIB_INTR_RXTX, ixgbe_msix_que, rx_que, rx_que->rxr.me, buf); 2116 2117 if (error) { 2118 device_printf(iflib_get_dev(ctx), 2119 "Failed to allocate que int %d err: %d", i, error); 2120 sc->num_rx_queues = i + 1; 2121 goto fail; 2122 } 2123 2124 rx_que->msix = vector; 2125 } 2126 for (int i = 0; i < sc->num_tx_queues; i++) { 2127 snprintf(buf, sizeof(buf), "txq%d", i); 2128 tx_que = &sc->tx_queues[i]; 2129 tx_que->msix = i % sc->num_rx_queues; 2130 iflib_softirq_alloc_generic(ctx, 2131 &sc->rx_queues[tx_que->msix].que_irq, 2132 IFLIB_INTR_TX, tx_que, tx_que->txr.me, buf); 2133 } 2134 rid = vector + 1; 2135 error = iflib_irq_alloc_generic(ctx, &sc->irq, rid, 2136 IFLIB_INTR_ADMIN, ixgbe_msix_link, sc, 0, "aq"); 2137 if (error) { 2138 device_printf(iflib_get_dev(ctx), 2139 "Failed to register admin handler"); 2140 return (error); 2141 } 2142 2143 sc->vector = vector; 2144 2145 return (0); 2146 fail: 2147 iflib_irq_free(ctx, &sc->irq); 2148 rx_que = sc->rx_queues; 2149 for (int i = 0; i < sc->num_rx_queues; i++, rx_que++) 2150 iflib_irq_free(ctx, &rx_que->que_irq); 2151 2152 return (error); 2153 } /* ixgbe_if_msix_intr_assign */ 2154 2155 static inline void 2156 ixgbe_perform_aim(struct ixgbe_softc *sc, struct ix_rx_queue *que) 2157 { 2158 uint32_t newitr = 0; 2159 struct rx_ring *rxr = &que->rxr; 2160 2161 /* 2162 * Do Adaptive Interrupt Moderation: 2163 * - Write out last calculated setting 2164 * - Calculate based on average size over 2165 * the last interval. 2166 */ 2167 if (que->eitr_setting) { 2168 IXGBE_WRITE_REG(&sc->hw, IXGBE_EITR(que->msix), 2169 que->eitr_setting); 2170 } 2171 2172 que->eitr_setting = 0; 2173 /* Idle, do nothing */ 2174 if (rxr->bytes == 0) { 2175 return; 2176 } 2177 2178 if ((rxr->bytes) && (rxr->packets)) { 2179 newitr = (rxr->bytes / rxr->packets); 2180 } 2181 2182 newitr += 24; /* account for hardware frame, crc */ 2183 /* set an upper boundary */ 2184 newitr = min(newitr, 3000); 2185 2186 /* Be nice to the mid range */ 2187 if ((newitr > 300) && (newitr < 1200)) { 2188 newitr = (newitr / 3); 2189 } else { 2190 newitr = (newitr / 2); 2191 } 2192 2193 if (sc->hw.mac.type == ixgbe_mac_82598EB) { 2194 newitr |= newitr << 16; 2195 } else { 2196 newitr |= IXGBE_EITR_CNT_WDIS; 2197 } 2198 2199 /* save for next interrupt */ 2200 que->eitr_setting = newitr; 2201 2202 /* Reset state */ 2203 rxr->bytes = 0; 2204 rxr->packets = 0; 2205 2206 return; 2207 } 2208 2209 /********************************************************************* 2210 * ixgbe_msix_que - MSI-X Queue Interrupt Service routine 2211 **********************************************************************/ 2212 static int 2213 ixgbe_msix_que(void *arg) 2214 { 2215 struct ix_rx_queue *que = arg; 2216 struct ixgbe_softc *sc = que->sc; 2217 if_t ifp = iflib_get_ifp(que->sc->ctx); 2218 2219 /* Protect against spurious interrupts */ 2220 if ((if_getdrvflags(ifp) & IFF_DRV_RUNNING) == 0) 2221 return (FILTER_HANDLED); 2222 2223 ixgbe_disable_queue(sc, que->msix); 2224 ++que->irqs; 2225 2226 /* Check for AIM */ 2227 if (sc->enable_aim) { 2228 ixgbe_perform_aim(sc, que); 2229 } 2230 2231 return (FILTER_SCHEDULE_THREAD); 2232 } /* ixgbe_msix_que */ 2233 2234 /************************************************************************ 2235 * ixgbe_media_status - Media Ioctl callback 2236 * 2237 * Called whenever the user queries the status of 2238 * the interface using ifconfig. 2239 ************************************************************************/ 2240 static void 2241 ixgbe_if_media_status(if_ctx_t ctx, struct ifmediareq * ifmr) 2242 { 2243 struct ixgbe_softc *sc = iflib_get_softc(ctx); 2244 struct ixgbe_hw *hw = &sc->hw; 2245 int layer; 2246 2247 INIT_DEBUGOUT("ixgbe_if_media_status: begin"); 2248 2249 ifmr->ifm_status = IFM_AVALID; 2250 ifmr->ifm_active = IFM_ETHER; 2251 2252 if (!sc->link_active) 2253 return; 2254 2255 ifmr->ifm_status |= IFM_ACTIVE; 2256 layer = sc->phy_layer; 2257 2258 if (layer & IXGBE_PHYSICAL_LAYER_10GBASE_T || 2259 layer & IXGBE_PHYSICAL_LAYER_1000BASE_T || 2260 layer & IXGBE_PHYSICAL_LAYER_100BASE_TX || 2261 layer & IXGBE_PHYSICAL_LAYER_10BASE_T) 2262 switch (sc->link_speed) { 2263 case IXGBE_LINK_SPEED_10GB_FULL: 2264 ifmr->ifm_active |= IFM_10G_T | IFM_FDX; 2265 break; 2266 case IXGBE_LINK_SPEED_1GB_FULL: 2267 ifmr->ifm_active |= IFM_1000_T | IFM_FDX; 2268 break; 2269 case IXGBE_LINK_SPEED_100_FULL: 2270 ifmr->ifm_active |= IFM_100_TX | IFM_FDX; 2271 break; 2272 case IXGBE_LINK_SPEED_10_FULL: 2273 ifmr->ifm_active |= IFM_10_T | IFM_FDX; 2274 break; 2275 } 2276 if (hw->mac.type == ixgbe_mac_X550) 2277 switch (sc->link_speed) { 2278 case IXGBE_LINK_SPEED_5GB_FULL: 2279 ifmr->ifm_active |= IFM_5000_T | IFM_FDX; 2280 break; 2281 case IXGBE_LINK_SPEED_2_5GB_FULL: 2282 ifmr->ifm_active |= IFM_2500_T | IFM_FDX; 2283 break; 2284 } 2285 if (layer & IXGBE_PHYSICAL_LAYER_SFP_PLUS_CU || 2286 layer & IXGBE_PHYSICAL_LAYER_SFP_ACTIVE_DA) 2287 switch (sc->link_speed) { 2288 case IXGBE_LINK_SPEED_10GB_FULL: 2289 ifmr->ifm_active |= IFM_10G_TWINAX | IFM_FDX; 2290 break; 2291 } 2292 if (layer & IXGBE_PHYSICAL_LAYER_10GBASE_LR) 2293 switch (sc->link_speed) { 2294 case IXGBE_LINK_SPEED_10GB_FULL: 2295 ifmr->ifm_active |= IFM_10G_LR | IFM_FDX; 2296 break; 2297 case IXGBE_LINK_SPEED_1GB_FULL: 2298 ifmr->ifm_active |= IFM_1000_LX | IFM_FDX; 2299 break; 2300 } 2301 if (layer & IXGBE_PHYSICAL_LAYER_10GBASE_LRM) 2302 switch (sc->link_speed) { 2303 case IXGBE_LINK_SPEED_10GB_FULL: 2304 ifmr->ifm_active |= IFM_10G_LRM | IFM_FDX; 2305 break; 2306 case IXGBE_LINK_SPEED_1GB_FULL: 2307 ifmr->ifm_active |= IFM_1000_LX | IFM_FDX; 2308 break; 2309 } 2310 if (layer & IXGBE_PHYSICAL_LAYER_10GBASE_SR || 2311 layer & IXGBE_PHYSICAL_LAYER_1000BASE_SX) 2312 switch (sc->link_speed) { 2313 case IXGBE_LINK_SPEED_10GB_FULL: 2314 ifmr->ifm_active |= IFM_10G_SR | IFM_FDX; 2315 break; 2316 case IXGBE_LINK_SPEED_1GB_FULL: 2317 ifmr->ifm_active |= IFM_1000_SX | IFM_FDX; 2318 break; 2319 } 2320 if (layer & IXGBE_PHYSICAL_LAYER_10GBASE_CX4) 2321 switch (sc->link_speed) { 2322 case IXGBE_LINK_SPEED_10GB_FULL: 2323 ifmr->ifm_active |= IFM_10G_CX4 | IFM_FDX; 2324 break; 2325 } 2326 /* 2327 * XXX: These need to use the proper media types once 2328 * they're added. 2329 */ 2330 #ifndef IFM_ETH_XTYPE 2331 if (layer & IXGBE_PHYSICAL_LAYER_10GBASE_KR) 2332 switch (sc->link_speed) { 2333 case IXGBE_LINK_SPEED_10GB_FULL: 2334 ifmr->ifm_active |= IFM_10G_SR | IFM_FDX; 2335 break; 2336 case IXGBE_LINK_SPEED_2_5GB_FULL: 2337 ifmr->ifm_active |= IFM_2500_SX | IFM_FDX; 2338 break; 2339 case IXGBE_LINK_SPEED_1GB_FULL: 2340 ifmr->ifm_active |= IFM_1000_CX | IFM_FDX; 2341 break; 2342 } 2343 else if (layer & IXGBE_PHYSICAL_LAYER_10GBASE_KX4 || 2344 layer & IXGBE_PHYSICAL_LAYER_2500BASE_KX || 2345 layer & IXGBE_PHYSICAL_LAYER_1000BASE_KX) 2346 switch (sc->link_speed) { 2347 case IXGBE_LINK_SPEED_10GB_FULL: 2348 ifmr->ifm_active |= IFM_10G_CX4 | IFM_FDX; 2349 break; 2350 case IXGBE_LINK_SPEED_2_5GB_FULL: 2351 ifmr->ifm_active |= IFM_2500_SX | IFM_FDX; 2352 break; 2353 case IXGBE_LINK_SPEED_1GB_FULL: 2354 ifmr->ifm_active |= IFM_1000_CX | IFM_FDX; 2355 break; 2356 } 2357 #else 2358 if (layer & IXGBE_PHYSICAL_LAYER_10GBASE_KR) 2359 switch (sc->link_speed) { 2360 case IXGBE_LINK_SPEED_10GB_FULL: 2361 ifmr->ifm_active |= IFM_10G_KR | IFM_FDX; 2362 break; 2363 case IXGBE_LINK_SPEED_2_5GB_FULL: 2364 ifmr->ifm_active |= IFM_2500_KX | IFM_FDX; 2365 break; 2366 case IXGBE_LINK_SPEED_1GB_FULL: 2367 ifmr->ifm_active |= IFM_1000_KX | IFM_FDX; 2368 break; 2369 } 2370 else if (layer & IXGBE_PHYSICAL_LAYER_10GBASE_KX4 || 2371 layer & IXGBE_PHYSICAL_LAYER_2500BASE_KX || 2372 layer & IXGBE_PHYSICAL_LAYER_1000BASE_KX) 2373 switch (sc->link_speed) { 2374 case IXGBE_LINK_SPEED_10GB_FULL: 2375 ifmr->ifm_active |= IFM_10G_KX4 | IFM_FDX; 2376 break; 2377 case IXGBE_LINK_SPEED_2_5GB_FULL: 2378 ifmr->ifm_active |= IFM_2500_KX | IFM_FDX; 2379 break; 2380 case IXGBE_LINK_SPEED_1GB_FULL: 2381 ifmr->ifm_active |= IFM_1000_KX | IFM_FDX; 2382 break; 2383 } 2384 #endif 2385 2386 /* If nothing is recognized... */ 2387 if (IFM_SUBTYPE(ifmr->ifm_active) == 0) 2388 ifmr->ifm_active |= IFM_UNKNOWN; 2389 2390 /* Display current flow control setting used on link */ 2391 if (hw->fc.current_mode == ixgbe_fc_rx_pause || 2392 hw->fc.current_mode == ixgbe_fc_full) 2393 ifmr->ifm_active |= IFM_ETH_RXPAUSE; 2394 if (hw->fc.current_mode == ixgbe_fc_tx_pause || 2395 hw->fc.current_mode == ixgbe_fc_full) 2396 ifmr->ifm_active |= IFM_ETH_TXPAUSE; 2397 } /* ixgbe_media_status */ 2398 2399 /************************************************************************ 2400 * ixgbe_media_change - Media Ioctl callback 2401 * 2402 * Called when the user changes speed/duplex using 2403 * media/mediopt option with ifconfig. 2404 ************************************************************************/ 2405 static int 2406 ixgbe_if_media_change(if_ctx_t ctx) 2407 { 2408 struct ixgbe_softc *sc = iflib_get_softc(ctx); 2409 struct ifmedia *ifm = iflib_get_media(ctx); 2410 struct ixgbe_hw *hw = &sc->hw; 2411 ixgbe_link_speed speed = 0; 2412 2413 INIT_DEBUGOUT("ixgbe_if_media_change: begin"); 2414 2415 if (IFM_TYPE(ifm->ifm_media) != IFM_ETHER) 2416 return (EINVAL); 2417 2418 if (hw->phy.media_type == ixgbe_media_type_backplane) 2419 return (EPERM); 2420 2421 /* 2422 * We don't actually need to check against the supported 2423 * media types of the adapter; ifmedia will take care of 2424 * that for us. 2425 */ 2426 switch (IFM_SUBTYPE(ifm->ifm_media)) { 2427 case IFM_AUTO: 2428 case IFM_10G_T: 2429 speed |= IXGBE_LINK_SPEED_100_FULL; 2430 speed |= IXGBE_LINK_SPEED_1GB_FULL; 2431 speed |= IXGBE_LINK_SPEED_10GB_FULL; 2432 break; 2433 case IFM_10G_LRM: 2434 case IFM_10G_LR: 2435 #ifndef IFM_ETH_XTYPE 2436 case IFM_10G_SR: /* KR, too */ 2437 case IFM_10G_CX4: /* KX4 */ 2438 #else 2439 case IFM_10G_KR: 2440 case IFM_10G_KX4: 2441 #endif 2442 speed |= IXGBE_LINK_SPEED_1GB_FULL; 2443 speed |= IXGBE_LINK_SPEED_10GB_FULL; 2444 break; 2445 #ifndef IFM_ETH_XTYPE 2446 case IFM_1000_CX: /* KX */ 2447 #else 2448 case IFM_1000_KX: 2449 #endif 2450 case IFM_1000_LX: 2451 case IFM_1000_SX: 2452 speed |= IXGBE_LINK_SPEED_1GB_FULL; 2453 break; 2454 case IFM_1000_T: 2455 speed |= IXGBE_LINK_SPEED_100_FULL; 2456 speed |= IXGBE_LINK_SPEED_1GB_FULL; 2457 break; 2458 case IFM_10G_TWINAX: 2459 speed |= IXGBE_LINK_SPEED_10GB_FULL; 2460 break; 2461 case IFM_5000_T: 2462 speed |= IXGBE_LINK_SPEED_5GB_FULL; 2463 break; 2464 case IFM_2500_T: 2465 speed |= IXGBE_LINK_SPEED_2_5GB_FULL; 2466 break; 2467 case IFM_100_TX: 2468 speed |= IXGBE_LINK_SPEED_100_FULL; 2469 break; 2470 case IFM_10_T: 2471 speed |= IXGBE_LINK_SPEED_10_FULL; 2472 break; 2473 default: 2474 goto invalid; 2475 } 2476 2477 hw->mac.autotry_restart = true; 2478 hw->mac.ops.setup_link(hw, speed, true); 2479 sc->advertise = 2480 ((speed & IXGBE_LINK_SPEED_10GB_FULL) ? 0x4 : 0) | 2481 ((speed & IXGBE_LINK_SPEED_5GB_FULL) ? 0x20 : 0) | 2482 ((speed & IXGBE_LINK_SPEED_2_5GB_FULL) ? 0x10 : 0) | 2483 ((speed & IXGBE_LINK_SPEED_1GB_FULL) ? 0x2 : 0) | 2484 ((speed & IXGBE_LINK_SPEED_100_FULL) ? 0x1 : 0) | 2485 ((speed & IXGBE_LINK_SPEED_10_FULL) ? 0x8 : 0); 2486 2487 return (0); 2488 2489 invalid: 2490 device_printf(iflib_get_dev(ctx), "Invalid media type!\n"); 2491 2492 return (EINVAL); 2493 } /* ixgbe_if_media_change */ 2494 2495 /************************************************************************ 2496 * ixgbe_set_promisc 2497 ************************************************************************/ 2498 static int 2499 ixgbe_if_promisc_set(if_ctx_t ctx, int flags) 2500 { 2501 struct ixgbe_softc *sc = iflib_get_softc(ctx); 2502 if_t ifp = iflib_get_ifp(ctx); 2503 u32 rctl; 2504 int mcnt = 0; 2505 2506 rctl = IXGBE_READ_REG(&sc->hw, IXGBE_FCTRL); 2507 rctl &= (~IXGBE_FCTRL_UPE); 2508 if (if_getflags(ifp) & IFF_ALLMULTI) 2509 mcnt = MAX_NUM_MULTICAST_ADDRESSES; 2510 else { 2511 mcnt = min(if_llmaddr_count(ifp), MAX_NUM_MULTICAST_ADDRESSES); 2512 } 2513 if (mcnt < MAX_NUM_MULTICAST_ADDRESSES) 2514 rctl &= (~IXGBE_FCTRL_MPE); 2515 IXGBE_WRITE_REG(&sc->hw, IXGBE_FCTRL, rctl); 2516 2517 if (if_getflags(ifp) & IFF_PROMISC) { 2518 rctl |= (IXGBE_FCTRL_UPE | IXGBE_FCTRL_MPE); 2519 IXGBE_WRITE_REG(&sc->hw, IXGBE_FCTRL, rctl); 2520 } else if (if_getflags(ifp) & IFF_ALLMULTI) { 2521 rctl |= IXGBE_FCTRL_MPE; 2522 rctl &= ~IXGBE_FCTRL_UPE; 2523 IXGBE_WRITE_REG(&sc->hw, IXGBE_FCTRL, rctl); 2524 } 2525 return (0); 2526 } /* ixgbe_if_promisc_set */ 2527 2528 /************************************************************************ 2529 * ixgbe_msix_link - Link status change ISR (MSI/MSI-X) 2530 ************************************************************************/ 2531 static int 2532 ixgbe_msix_link(void *arg) 2533 { 2534 struct ixgbe_softc *sc = arg; 2535 struct ixgbe_hw *hw = &sc->hw; 2536 u32 eicr, eicr_mask; 2537 s32 retval; 2538 2539 ++sc->link_irq; 2540 2541 /* Pause other interrupts */ 2542 IXGBE_WRITE_REG(hw, IXGBE_EIMC, IXGBE_EIMC_OTHER); 2543 2544 /* First get the cause */ 2545 eicr = IXGBE_READ_REG(hw, IXGBE_EICS); 2546 /* Be sure the queue bits are not cleared */ 2547 eicr &= ~IXGBE_EICR_RTX_QUEUE; 2548 /* Clear interrupt with write */ 2549 IXGBE_WRITE_REG(hw, IXGBE_EICR, eicr); 2550 2551 /* Link status change */ 2552 if (eicr & IXGBE_EICR_LSC) { 2553 IXGBE_WRITE_REG(hw, IXGBE_EIMC, IXGBE_EIMC_LSC); 2554 sc->task_requests |= IXGBE_REQUEST_TASK_LSC; 2555 } 2556 2557 if (sc->hw.mac.type != ixgbe_mac_82598EB) { 2558 if ((sc->feat_en & IXGBE_FEATURE_FDIR) && 2559 (eicr & IXGBE_EICR_FLOW_DIR)) { 2560 /* This is probably overkill :) */ 2561 if (!atomic_cmpset_int(&sc->fdir_reinit, 0, 1)) 2562 return (FILTER_HANDLED); 2563 /* Disable the interrupt */ 2564 IXGBE_WRITE_REG(hw, IXGBE_EIMC, IXGBE_EICR_FLOW_DIR); 2565 sc->task_requests |= IXGBE_REQUEST_TASK_FDIR; 2566 } else 2567 if (eicr & IXGBE_EICR_ECC) { 2568 device_printf(iflib_get_dev(sc->ctx), 2569 "Received ECC Err, initiating reset\n"); 2570 hw->mac.flags |= ~IXGBE_FLAGS_DOUBLE_RESET_REQUIRED; 2571 ixgbe_reset_hw(hw); 2572 IXGBE_WRITE_REG(hw, IXGBE_EICR, IXGBE_EICR_ECC); 2573 } 2574 2575 /* Check for over temp condition */ 2576 if (sc->feat_en & IXGBE_FEATURE_TEMP_SENSOR) { 2577 switch (sc->hw.mac.type) { 2578 case ixgbe_mac_X550EM_a: 2579 if (!(eicr & IXGBE_EICR_GPI_SDP0_X550EM_a)) 2580 break; 2581 IXGBE_WRITE_REG(hw, IXGBE_EIMC, 2582 IXGBE_EICR_GPI_SDP0_X550EM_a); 2583 IXGBE_WRITE_REG(hw, IXGBE_EICR, 2584 IXGBE_EICR_GPI_SDP0_X550EM_a); 2585 retval = hw->phy.ops.check_overtemp(hw); 2586 if (retval != IXGBE_ERR_OVERTEMP) 2587 break; 2588 device_printf(iflib_get_dev(sc->ctx), 2589 "\nCRITICAL: OVER TEMP!! PHY IS SHUT DOWN!!\n"); 2590 device_printf(iflib_get_dev(sc->ctx), 2591 "System shutdown required!\n"); 2592 break; 2593 default: 2594 if (!(eicr & IXGBE_EICR_TS)) 2595 break; 2596 retval = hw->phy.ops.check_overtemp(hw); 2597 if (retval != IXGBE_ERR_OVERTEMP) 2598 break; 2599 device_printf(iflib_get_dev(sc->ctx), 2600 "\nCRITICAL: OVER TEMP!! PHY IS SHUT DOWN!!\n"); 2601 device_printf(iflib_get_dev(sc->ctx), 2602 "System shutdown required!\n"); 2603 IXGBE_WRITE_REG(hw, IXGBE_EICR, IXGBE_EICR_TS); 2604 break; 2605 } 2606 } 2607 2608 /* Check for VF message */ 2609 if ((sc->feat_en & IXGBE_FEATURE_SRIOV) && 2610 (eicr & IXGBE_EICR_MAILBOX)) 2611 sc->task_requests |= IXGBE_REQUEST_TASK_MBX; 2612 } 2613 2614 if (ixgbe_is_sfp(hw)) { 2615 /* Pluggable optics-related interrupt */ 2616 if (hw->mac.type >= ixgbe_mac_X540) 2617 eicr_mask = IXGBE_EICR_GPI_SDP0_X540; 2618 else 2619 eicr_mask = IXGBE_EICR_GPI_SDP2_BY_MAC(hw); 2620 2621 if (eicr & eicr_mask) { 2622 IXGBE_WRITE_REG(hw, IXGBE_EICR, eicr_mask); 2623 sc->task_requests |= IXGBE_REQUEST_TASK_MOD; 2624 } 2625 2626 if ((hw->mac.type == ixgbe_mac_82599EB) && 2627 (eicr & IXGBE_EICR_GPI_SDP1_BY_MAC(hw))) { 2628 IXGBE_WRITE_REG(hw, IXGBE_EICR, 2629 IXGBE_EICR_GPI_SDP1_BY_MAC(hw)); 2630 sc->task_requests |= IXGBE_REQUEST_TASK_MSF; 2631 } 2632 } 2633 2634 /* Check for fan failure */ 2635 if (sc->feat_en & IXGBE_FEATURE_FAN_FAIL) { 2636 ixgbe_check_fan_failure(sc, eicr, true); 2637 IXGBE_WRITE_REG(hw, IXGBE_EICR, IXGBE_EICR_GPI_SDP1_BY_MAC(hw)); 2638 } 2639 2640 /* External PHY interrupt */ 2641 if ((hw->phy.type == ixgbe_phy_x550em_ext_t) && 2642 (eicr & IXGBE_EICR_GPI_SDP0_X540)) { 2643 IXGBE_WRITE_REG(hw, IXGBE_EICR, IXGBE_EICR_GPI_SDP0_X540); 2644 sc->task_requests |= IXGBE_REQUEST_TASK_PHY; 2645 } 2646 2647 return (sc->task_requests != 0) ? FILTER_SCHEDULE_THREAD : FILTER_HANDLED; 2648 } /* ixgbe_msix_link */ 2649 2650 /************************************************************************ 2651 * ixgbe_sysctl_interrupt_rate_handler 2652 ************************************************************************/ 2653 static int 2654 ixgbe_sysctl_interrupt_rate_handler(SYSCTL_HANDLER_ARGS) 2655 { 2656 struct ix_rx_queue *que = ((struct ix_rx_queue *)oidp->oid_arg1); 2657 int error; 2658 unsigned int reg, usec, rate; 2659 2660 reg = IXGBE_READ_REG(&que->sc->hw, IXGBE_EITR(que->msix)); 2661 usec = ((reg & 0x0FF8) >> 3); 2662 if (usec > 0) 2663 rate = 500000 / usec; 2664 else 2665 rate = 0; 2666 error = sysctl_handle_int(oidp, &rate, 0, req); 2667 if (error || !req->newptr) 2668 return error; 2669 reg &= ~0xfff; /* default, no limitation */ 2670 ixgbe_max_interrupt_rate = 0; 2671 if (rate > 0 && rate < 500000) { 2672 if (rate < 1000) 2673 rate = 1000; 2674 ixgbe_max_interrupt_rate = rate; 2675 reg |= ((4000000/rate) & 0xff8); 2676 } 2677 IXGBE_WRITE_REG(&que->sc->hw, IXGBE_EITR(que->msix), reg); 2678 2679 return (0); 2680 } /* ixgbe_sysctl_interrupt_rate_handler */ 2681 2682 /************************************************************************ 2683 * ixgbe_add_device_sysctls 2684 ************************************************************************/ 2685 static void 2686 ixgbe_add_device_sysctls(if_ctx_t ctx) 2687 { 2688 struct ixgbe_softc *sc = iflib_get_softc(ctx); 2689 device_t dev = iflib_get_dev(ctx); 2690 struct ixgbe_hw *hw = &sc->hw; 2691 struct sysctl_oid_list *child; 2692 struct sysctl_ctx_list *ctx_list; 2693 2694 ctx_list = device_get_sysctl_ctx(dev); 2695 child = SYSCTL_CHILDREN(device_get_sysctl_tree(dev)); 2696 2697 /* Sysctls for all devices */ 2698 SYSCTL_ADD_PROC(ctx_list, child, OID_AUTO, "fc", 2699 CTLTYPE_INT | CTLFLAG_RW | CTLFLAG_NEEDGIANT, 2700 sc, 0, ixgbe_sysctl_flowcntl, "I", 2701 IXGBE_SYSCTL_DESC_SET_FC); 2702 2703 SYSCTL_ADD_PROC(ctx_list, child, OID_AUTO, "advertise_speed", 2704 CTLTYPE_INT | CTLFLAG_RW | CTLFLAG_NEEDGIANT, 2705 sc, 0, ixgbe_sysctl_advertise, "I", 2706 IXGBE_SYSCTL_DESC_ADV_SPEED); 2707 2708 sc->enable_aim = ixgbe_enable_aim; 2709 SYSCTL_ADD_INT(ctx_list, child, OID_AUTO, "enable_aim", CTLFLAG_RW, 2710 &sc->enable_aim, 0, "Interrupt Moderation"); 2711 2712 SYSCTL_ADD_PROC(ctx_list, child, OID_AUTO, "fw_version", 2713 CTLTYPE_STRING | CTLFLAG_RD | CTLFLAG_NEEDGIANT, sc, 0, 2714 ixgbe_sysctl_print_fw_version, "A", "Prints FW/NVM Versions"); 2715 2716 #ifdef IXGBE_DEBUG 2717 /* testing sysctls (for all devices) */ 2718 SYSCTL_ADD_PROC(ctx_list, child, OID_AUTO, "power_state", 2719 CTLTYPE_INT | CTLFLAG_RW | CTLFLAG_NEEDGIANT, 2720 sc, 0, ixgbe_sysctl_power_state, 2721 "I", "PCI Power State"); 2722 2723 SYSCTL_ADD_PROC(ctx_list, child, OID_AUTO, "print_rss_config", 2724 CTLTYPE_STRING | CTLFLAG_RD | CTLFLAG_NEEDGIANT, sc, 0, 2725 ixgbe_sysctl_print_rss_config, "A", "Prints RSS Configuration"); 2726 #endif 2727 /* for X550 series devices */ 2728 if (hw->mac.type >= ixgbe_mac_X550) 2729 SYSCTL_ADD_PROC(ctx_list, child, OID_AUTO, "dmac", 2730 CTLTYPE_U16 | CTLFLAG_RW | CTLFLAG_NEEDGIANT, 2731 sc, 0, ixgbe_sysctl_dmac, 2732 "I", "DMA Coalesce"); 2733 2734 /* for WoL-capable devices */ 2735 if (hw->device_id == IXGBE_DEV_ID_X550EM_X_10G_T) { 2736 SYSCTL_ADD_PROC(ctx_list, child, OID_AUTO, "wol_enable", 2737 CTLTYPE_INT | CTLFLAG_RW | CTLFLAG_NEEDGIANT, sc, 0, 2738 ixgbe_sysctl_wol_enable, "I", "Enable/Disable Wake on LAN"); 2739 2740 SYSCTL_ADD_PROC(ctx_list, child, OID_AUTO, "wufc", 2741 CTLTYPE_U32 | CTLFLAG_RW | CTLFLAG_NEEDGIANT, 2742 sc, 0, ixgbe_sysctl_wufc, 2743 "I", "Enable/Disable Wake Up Filters"); 2744 } 2745 2746 /* for X552/X557-AT devices */ 2747 if (hw->device_id == IXGBE_DEV_ID_X550EM_X_10G_T) { 2748 struct sysctl_oid *phy_node; 2749 struct sysctl_oid_list *phy_list; 2750 2751 phy_node = SYSCTL_ADD_NODE(ctx_list, child, OID_AUTO, "phy", 2752 CTLFLAG_RD | CTLFLAG_MPSAFE, NULL, "External PHY sysctls"); 2753 phy_list = SYSCTL_CHILDREN(phy_node); 2754 2755 SYSCTL_ADD_PROC(ctx_list, phy_list, OID_AUTO, "temp", 2756 CTLTYPE_U16 | CTLFLAG_RD | CTLFLAG_NEEDGIANT, 2757 sc, 0, ixgbe_sysctl_phy_temp, 2758 "I", "Current External PHY Temperature (Celsius)"); 2759 2760 SYSCTL_ADD_PROC(ctx_list, phy_list, OID_AUTO, 2761 "overtemp_occurred", 2762 CTLTYPE_U16 | CTLFLAG_RD | CTLFLAG_NEEDGIANT, sc, 0, 2763 ixgbe_sysctl_phy_overtemp_occurred, "I", 2764 "External PHY High Temperature Event Occurred"); 2765 } 2766 2767 if (sc->feat_cap & IXGBE_FEATURE_EEE) { 2768 SYSCTL_ADD_PROC(ctx_list, child, OID_AUTO, "eee_state", 2769 CTLTYPE_INT | CTLFLAG_RW | CTLFLAG_NEEDGIANT, sc, 0, 2770 ixgbe_sysctl_eee_state, "I", "EEE Power Save State"); 2771 } 2772 } /* ixgbe_add_device_sysctls */ 2773 2774 /************************************************************************ 2775 * ixgbe_allocate_pci_resources 2776 ************************************************************************/ 2777 static int 2778 ixgbe_allocate_pci_resources(if_ctx_t ctx) 2779 { 2780 struct ixgbe_softc *sc = iflib_get_softc(ctx); 2781 device_t dev = iflib_get_dev(ctx); 2782 int rid; 2783 2784 rid = PCIR_BAR(0); 2785 sc->pci_mem = bus_alloc_resource_any(dev, SYS_RES_MEMORY, &rid, 2786 RF_ACTIVE); 2787 2788 if (!(sc->pci_mem)) { 2789 device_printf(dev, "Unable to allocate bus resource: memory\n"); 2790 return (ENXIO); 2791 } 2792 2793 /* Save bus_space values for READ/WRITE_REG macros */ 2794 sc->osdep.mem_bus_space_tag = rman_get_bustag(sc->pci_mem); 2795 sc->osdep.mem_bus_space_handle = 2796 rman_get_bushandle(sc->pci_mem); 2797 /* Set hw values for shared code */ 2798 sc->hw.hw_addr = (u8 *)&sc->osdep.mem_bus_space_handle; 2799 2800 return (0); 2801 } /* ixgbe_allocate_pci_resources */ 2802 2803 /************************************************************************ 2804 * ixgbe_detach - Device removal routine 2805 * 2806 * Called when the driver is being removed. 2807 * Stops the adapter and deallocates all the resources 2808 * that were allocated for driver operation. 2809 * 2810 * return 0 on success, positive on failure 2811 ************************************************************************/ 2812 static int 2813 ixgbe_if_detach(if_ctx_t ctx) 2814 { 2815 struct ixgbe_softc *sc = iflib_get_softc(ctx); 2816 device_t dev = iflib_get_dev(ctx); 2817 u32 ctrl_ext; 2818 2819 INIT_DEBUGOUT("ixgbe_detach: begin"); 2820 2821 if (ixgbe_pci_iov_detach(dev) != 0) { 2822 device_printf(dev, "SR-IOV in use; detach first.\n"); 2823 return (EBUSY); 2824 } 2825 2826 ixgbe_setup_low_power_mode(ctx); 2827 2828 /* let hardware know driver is unloading */ 2829 ctrl_ext = IXGBE_READ_REG(&sc->hw, IXGBE_CTRL_EXT); 2830 ctrl_ext &= ~IXGBE_CTRL_EXT_DRV_LOAD; 2831 IXGBE_WRITE_REG(&sc->hw, IXGBE_CTRL_EXT, ctrl_ext); 2832 2833 ixgbe_free_pci_resources(ctx); 2834 free(sc->mta, M_IXGBE); 2835 2836 return (0); 2837 } /* ixgbe_if_detach */ 2838 2839 /************************************************************************ 2840 * ixgbe_setup_low_power_mode - LPLU/WoL preparation 2841 * 2842 * Prepare the adapter/port for LPLU and/or WoL 2843 ************************************************************************/ 2844 static int 2845 ixgbe_setup_low_power_mode(if_ctx_t ctx) 2846 { 2847 struct ixgbe_softc *sc = iflib_get_softc(ctx); 2848 struct ixgbe_hw *hw = &sc->hw; 2849 device_t dev = iflib_get_dev(ctx); 2850 s32 error = 0; 2851 2852 if (!hw->wol_enabled) 2853 ixgbe_set_phy_power(hw, false); 2854 2855 /* Limit power management flow to X550EM baseT */ 2856 if (hw->device_id == IXGBE_DEV_ID_X550EM_X_10G_T && 2857 hw->phy.ops.enter_lplu) { 2858 /* Turn off support for APM wakeup. (Using ACPI instead) */ 2859 IXGBE_WRITE_REG(hw, IXGBE_GRC_BY_MAC(hw), 2860 IXGBE_READ_REG(hw, IXGBE_GRC_BY_MAC(hw)) & ~(u32)2); 2861 2862 /* 2863 * Clear Wake Up Status register to prevent any previous wakeup 2864 * events from waking us up immediately after we suspend. 2865 */ 2866 IXGBE_WRITE_REG(hw, IXGBE_WUS, 0xffffffff); 2867 2868 /* 2869 * Program the Wakeup Filter Control register with user filter 2870 * settings 2871 */ 2872 IXGBE_WRITE_REG(hw, IXGBE_WUFC, sc->wufc); 2873 2874 /* Enable wakeups and power management in Wakeup Control */ 2875 IXGBE_WRITE_REG(hw, IXGBE_WUC, 2876 IXGBE_WUC_WKEN | IXGBE_WUC_PME_EN); 2877 2878 /* X550EM baseT adapters need a special LPLU flow */ 2879 hw->phy.reset_disable = true; 2880 ixgbe_if_stop(ctx); 2881 error = hw->phy.ops.enter_lplu(hw); 2882 if (error) 2883 device_printf(dev, "Error entering LPLU: %d\n", error); 2884 hw->phy.reset_disable = false; 2885 } else { 2886 /* Just stop for other adapters */ 2887 ixgbe_if_stop(ctx); 2888 } 2889 2890 return error; 2891 } /* ixgbe_setup_low_power_mode */ 2892 2893 /************************************************************************ 2894 * ixgbe_shutdown - Shutdown entry point 2895 ************************************************************************/ 2896 static int 2897 ixgbe_if_shutdown(if_ctx_t ctx) 2898 { 2899 int error = 0; 2900 2901 INIT_DEBUGOUT("ixgbe_shutdown: begin"); 2902 2903 error = ixgbe_setup_low_power_mode(ctx); 2904 2905 return (error); 2906 } /* ixgbe_if_shutdown */ 2907 2908 /************************************************************************ 2909 * ixgbe_suspend 2910 * 2911 * From D0 to D3 2912 ************************************************************************/ 2913 static int 2914 ixgbe_if_suspend(if_ctx_t ctx) 2915 { 2916 int error = 0; 2917 2918 INIT_DEBUGOUT("ixgbe_suspend: begin"); 2919 2920 error = ixgbe_setup_low_power_mode(ctx); 2921 2922 return (error); 2923 } /* ixgbe_if_suspend */ 2924 2925 /************************************************************************ 2926 * ixgbe_resume 2927 * 2928 * From D3 to D0 2929 ************************************************************************/ 2930 static int 2931 ixgbe_if_resume(if_ctx_t ctx) 2932 { 2933 struct ixgbe_softc *sc = iflib_get_softc(ctx); 2934 device_t dev = iflib_get_dev(ctx); 2935 if_t ifp = iflib_get_ifp(ctx); 2936 struct ixgbe_hw *hw = &sc->hw; 2937 u32 wus; 2938 2939 INIT_DEBUGOUT("ixgbe_resume: begin"); 2940 2941 /* Read & clear WUS register */ 2942 wus = IXGBE_READ_REG(hw, IXGBE_WUS); 2943 if (wus) 2944 device_printf(dev, "Woken up by (WUS): %#010x\n", 2945 IXGBE_READ_REG(hw, IXGBE_WUS)); 2946 IXGBE_WRITE_REG(hw, IXGBE_WUS, 0xffffffff); 2947 /* And clear WUFC until next low-power transition */ 2948 IXGBE_WRITE_REG(hw, IXGBE_WUFC, 0); 2949 2950 /* 2951 * Required after D3->D0 transition; 2952 * will re-advertise all previous advertised speeds 2953 */ 2954 if (if_getflags(ifp) & IFF_UP) 2955 ixgbe_if_init(ctx); 2956 2957 return (0); 2958 } /* ixgbe_if_resume */ 2959 2960 /************************************************************************ 2961 * ixgbe_if_mtu_set - Ioctl mtu entry point 2962 * 2963 * Return 0 on success, EINVAL on failure 2964 ************************************************************************/ 2965 static int 2966 ixgbe_if_mtu_set(if_ctx_t ctx, uint32_t mtu) 2967 { 2968 struct ixgbe_softc *sc = iflib_get_softc(ctx); 2969 int error = 0; 2970 2971 IOCTL_DEBUGOUT("ioctl: SIOCIFMTU (Set Interface MTU)"); 2972 2973 if (mtu > IXGBE_MAX_MTU) { 2974 error = EINVAL; 2975 } else { 2976 sc->max_frame_size = mtu + IXGBE_MTU_HDR; 2977 } 2978 2979 return error; 2980 } /* ixgbe_if_mtu_set */ 2981 2982 /************************************************************************ 2983 * ixgbe_if_crcstrip_set 2984 ************************************************************************/ 2985 static void 2986 ixgbe_if_crcstrip_set(if_ctx_t ctx, int onoff, int crcstrip) 2987 { 2988 struct ixgbe_softc *sc = iflib_get_softc(ctx); 2989 struct ixgbe_hw *hw = &sc->hw; 2990 /* crc stripping is set in two places: 2991 * IXGBE_HLREG0 (modified on init_locked and hw reset) 2992 * IXGBE_RDRXCTL (set by the original driver in 2993 * ixgbe_setup_hw_rsc() called in init_locked. 2994 * We disable the setting when netmap is compiled in). 2995 * We update the values here, but also in ixgbe.c because 2996 * init_locked sometimes is called outside our control. 2997 */ 2998 uint32_t hl, rxc; 2999 3000 hl = IXGBE_READ_REG(hw, IXGBE_HLREG0); 3001 rxc = IXGBE_READ_REG(hw, IXGBE_RDRXCTL); 3002 #ifdef NETMAP 3003 if (netmap_verbose) 3004 D("%s read HLREG 0x%x rxc 0x%x", 3005 onoff ? "enter" : "exit", hl, rxc); 3006 #endif 3007 /* hw requirements ... */ 3008 rxc &= ~IXGBE_RDRXCTL_RSCFRSTSIZE; 3009 rxc |= IXGBE_RDRXCTL_RSCACKC; 3010 if (onoff && !crcstrip) { 3011 /* keep the crc. Fast rx */ 3012 hl &= ~IXGBE_HLREG0_RXCRCSTRP; 3013 rxc &= ~IXGBE_RDRXCTL_CRCSTRIP; 3014 } else { 3015 /* reset default mode */ 3016 hl |= IXGBE_HLREG0_RXCRCSTRP; 3017 rxc |= IXGBE_RDRXCTL_CRCSTRIP; 3018 } 3019 #ifdef NETMAP 3020 if (netmap_verbose) 3021 D("%s write HLREG 0x%x rxc 0x%x", 3022 onoff ? "enter" : "exit", hl, rxc); 3023 #endif 3024 IXGBE_WRITE_REG(hw, IXGBE_HLREG0, hl); 3025 IXGBE_WRITE_REG(hw, IXGBE_RDRXCTL, rxc); 3026 } /* ixgbe_if_crcstrip_set */ 3027 3028 /********************************************************************* 3029 * ixgbe_if_init - Init entry point 3030 * 3031 * Used in two ways: It is used by the stack as an init 3032 * entry point in network interface structure. It is also 3033 * used by the driver as a hw/sw initialization routine to 3034 * get to a consistent state. 3035 * 3036 * Return 0 on success, positive on failure 3037 **********************************************************************/ 3038 void 3039 ixgbe_if_init(if_ctx_t ctx) 3040 { 3041 struct ixgbe_softc *sc = iflib_get_softc(ctx); 3042 if_t ifp = iflib_get_ifp(ctx); 3043 device_t dev = iflib_get_dev(ctx); 3044 struct ixgbe_hw *hw = &sc->hw; 3045 struct ix_rx_queue *rx_que; 3046 struct ix_tx_queue *tx_que; 3047 u32 txdctl, mhadd; 3048 u32 rxdctl, rxctrl; 3049 u32 ctrl_ext; 3050 3051 int i, j, err; 3052 3053 INIT_DEBUGOUT("ixgbe_if_init: begin"); 3054 3055 /* Queue indices may change with IOV mode */ 3056 ixgbe_align_all_queue_indices(sc); 3057 3058 /* reprogram the RAR[0] in case user changed it. */ 3059 ixgbe_set_rar(hw, 0, hw->mac.addr, sc->pool, IXGBE_RAH_AV); 3060 3061 /* Get the latest mac address, User can use a LAA */ 3062 bcopy(if_getlladdr(ifp), hw->mac.addr, IXGBE_ETH_LENGTH_OF_ADDRESS); 3063 ixgbe_set_rar(hw, 0, hw->mac.addr, sc->pool, 1); 3064 hw->addr_ctrl.rar_used_count = 1; 3065 3066 ixgbe_init_hw(hw); 3067 3068 ixgbe_initialize_iov(sc); 3069 3070 ixgbe_initialize_transmit_units(ctx); 3071 3072 /* Setup Multicast table */ 3073 ixgbe_if_multi_set(ctx); 3074 3075 /* Determine the correct mbuf pool, based on frame size */ 3076 sc->rx_mbuf_sz = iflib_get_rx_mbuf_sz(ctx); 3077 3078 /* Configure RX settings */ 3079 ixgbe_initialize_receive_units(ctx); 3080 3081 /* 3082 * Initialize variable holding task enqueue requests 3083 * from MSI-X interrupts 3084 */ 3085 sc->task_requests = 0; 3086 3087 /* Enable SDP & MSI-X interrupts based on adapter */ 3088 ixgbe_config_gpie(sc); 3089 3090 /* Set MTU size */ 3091 if (if_getmtu(ifp) > ETHERMTU) { 3092 /* aka IXGBE_MAXFRS on 82599 and newer */ 3093 mhadd = IXGBE_READ_REG(hw, IXGBE_MHADD); 3094 mhadd &= ~IXGBE_MHADD_MFS_MASK; 3095 mhadd |= sc->max_frame_size << IXGBE_MHADD_MFS_SHIFT; 3096 IXGBE_WRITE_REG(hw, IXGBE_MHADD, mhadd); 3097 } 3098 3099 /* Now enable all the queues */ 3100 for (i = 0, tx_que = sc->tx_queues; i < sc->num_tx_queues; i++, tx_que++) { 3101 struct tx_ring *txr = &tx_que->txr; 3102 3103 txdctl = IXGBE_READ_REG(hw, IXGBE_TXDCTL(txr->me)); 3104 txdctl |= IXGBE_TXDCTL_ENABLE; 3105 /* Set WTHRESH to 8, burst writeback */ 3106 txdctl |= (8 << 16); 3107 /* 3108 * When the internal queue falls below PTHRESH (32), 3109 * start prefetching as long as there are at least 3110 * HTHRESH (1) buffers ready. The values are taken 3111 * from the Intel linux driver 3.8.21. 3112 * Prefetching enables tx line rate even with 1 queue. 3113 */ 3114 txdctl |= (32 << 0) | (1 << 8); 3115 IXGBE_WRITE_REG(hw, IXGBE_TXDCTL(txr->me), txdctl); 3116 } 3117 3118 for (i = 0, rx_que = sc->rx_queues; i < sc->num_rx_queues; i++, rx_que++) { 3119 struct rx_ring *rxr = &rx_que->rxr; 3120 3121 rxdctl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(rxr->me)); 3122 if (hw->mac.type == ixgbe_mac_82598EB) { 3123 /* 3124 * PTHRESH = 21 3125 * HTHRESH = 4 3126 * WTHRESH = 8 3127 */ 3128 rxdctl &= ~0x3FFFFF; 3129 rxdctl |= 0x080420; 3130 } 3131 rxdctl |= IXGBE_RXDCTL_ENABLE; 3132 IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(rxr->me), rxdctl); 3133 for (j = 0; j < 10; j++) { 3134 if (IXGBE_READ_REG(hw, IXGBE_RXDCTL(rxr->me)) & 3135 IXGBE_RXDCTL_ENABLE) 3136 break; 3137 else 3138 msec_delay(1); 3139 } 3140 wmb(); 3141 } 3142 3143 /* Enable Receive engine */ 3144 rxctrl = IXGBE_READ_REG(hw, IXGBE_RXCTRL); 3145 if (hw->mac.type == ixgbe_mac_82598EB) 3146 rxctrl |= IXGBE_RXCTRL_DMBYPS; 3147 rxctrl |= IXGBE_RXCTRL_RXEN; 3148 ixgbe_enable_rx_dma(hw, rxctrl); 3149 3150 /* Set up MSI/MSI-X routing */ 3151 if (ixgbe_enable_msix) { 3152 ixgbe_configure_ivars(sc); 3153 /* Set up auto-mask */ 3154 if (hw->mac.type == ixgbe_mac_82598EB) 3155 IXGBE_WRITE_REG(hw, IXGBE_EIAM, IXGBE_EICS_RTX_QUEUE); 3156 else { 3157 IXGBE_WRITE_REG(hw, IXGBE_EIAM_EX(0), 0xFFFFFFFF); 3158 IXGBE_WRITE_REG(hw, IXGBE_EIAM_EX(1), 0xFFFFFFFF); 3159 } 3160 } else { /* Simple settings for Legacy/MSI */ 3161 ixgbe_set_ivar(sc, 0, 0, 0); 3162 ixgbe_set_ivar(sc, 0, 0, 1); 3163 IXGBE_WRITE_REG(hw, IXGBE_EIAM, IXGBE_EICS_RTX_QUEUE); 3164 } 3165 3166 ixgbe_init_fdir(sc); 3167 3168 /* 3169 * Check on any SFP devices that 3170 * need to be kick-started 3171 */ 3172 if (hw->phy.type == ixgbe_phy_none) { 3173 err = hw->phy.ops.identify(hw); 3174 if (err == IXGBE_ERR_SFP_NOT_SUPPORTED) { 3175 device_printf(dev, 3176 "Unsupported SFP+ module type was detected.\n"); 3177 return; 3178 } 3179 } 3180 3181 /* Set moderation on the Link interrupt */ 3182 IXGBE_WRITE_REG(hw, IXGBE_EITR(sc->vector), IXGBE_LINK_ITR); 3183 3184 /* Enable power to the phy. */ 3185 ixgbe_set_phy_power(hw, true); 3186 3187 /* Config/Enable Link */ 3188 ixgbe_config_link(ctx); 3189 3190 /* Hardware Packet Buffer & Flow Control setup */ 3191 ixgbe_config_delay_values(sc); 3192 3193 /* Initialize the FC settings */ 3194 ixgbe_start_hw(hw); 3195 3196 /* Set up VLAN support and filter */ 3197 ixgbe_setup_vlan_hw_support(ctx); 3198 3199 /* Setup DMA Coalescing */ 3200 ixgbe_config_dmac(sc); 3201 3202 /* And now turn on interrupts */ 3203 ixgbe_if_enable_intr(ctx); 3204 3205 /* Enable the use of the MBX by the VF's */ 3206 if (sc->feat_en & IXGBE_FEATURE_SRIOV) { 3207 ctrl_ext = IXGBE_READ_REG(hw, IXGBE_CTRL_EXT); 3208 ctrl_ext |= IXGBE_CTRL_EXT_PFRSTD; 3209 IXGBE_WRITE_REG(hw, IXGBE_CTRL_EXT, ctrl_ext); 3210 } 3211 3212 } /* ixgbe_init_locked */ 3213 3214 /************************************************************************ 3215 * ixgbe_set_ivar 3216 * 3217 * Setup the correct IVAR register for a particular MSI-X interrupt 3218 * (yes this is all very magic and confusing :) 3219 * - entry is the register array entry 3220 * - vector is the MSI-X vector for this queue 3221 * - type is RX/TX/MISC 3222 ************************************************************************/ 3223 static void 3224 ixgbe_set_ivar(struct ixgbe_softc *sc, u8 entry, u8 vector, s8 type) 3225 { 3226 struct ixgbe_hw *hw = &sc->hw; 3227 u32 ivar, index; 3228 3229 vector |= IXGBE_IVAR_ALLOC_VAL; 3230 3231 switch (hw->mac.type) { 3232 case ixgbe_mac_82598EB: 3233 if (type == -1) 3234 entry = IXGBE_IVAR_OTHER_CAUSES_INDEX; 3235 else 3236 entry += (type * 64); 3237 index = (entry >> 2) & 0x1F; 3238 ivar = IXGBE_READ_REG(hw, IXGBE_IVAR(index)); 3239 ivar &= ~(0xFF << (8 * (entry & 0x3))); 3240 ivar |= (vector << (8 * (entry & 0x3))); 3241 IXGBE_WRITE_REG(&sc->hw, IXGBE_IVAR(index), ivar); 3242 break; 3243 case ixgbe_mac_82599EB: 3244 case ixgbe_mac_X540: 3245 case ixgbe_mac_X550: 3246 case ixgbe_mac_X550EM_x: 3247 case ixgbe_mac_X550EM_a: 3248 if (type == -1) { /* MISC IVAR */ 3249 index = (entry & 1) * 8; 3250 ivar = IXGBE_READ_REG(hw, IXGBE_IVAR_MISC); 3251 ivar &= ~(0xFF << index); 3252 ivar |= (vector << index); 3253 IXGBE_WRITE_REG(hw, IXGBE_IVAR_MISC, ivar); 3254 } else { /* RX/TX IVARS */ 3255 index = (16 * (entry & 1)) + (8 * type); 3256 ivar = IXGBE_READ_REG(hw, IXGBE_IVAR(entry >> 1)); 3257 ivar &= ~(0xFF << index); 3258 ivar |= (vector << index); 3259 IXGBE_WRITE_REG(hw, IXGBE_IVAR(entry >> 1), ivar); 3260 } 3261 default: 3262 break; 3263 } 3264 } /* ixgbe_set_ivar */ 3265 3266 /************************************************************************ 3267 * ixgbe_configure_ivars 3268 ************************************************************************/ 3269 static void 3270 ixgbe_configure_ivars(struct ixgbe_softc *sc) 3271 { 3272 struct ix_rx_queue *rx_que = sc->rx_queues; 3273 struct ix_tx_queue *tx_que = sc->tx_queues; 3274 u32 newitr; 3275 3276 if (ixgbe_max_interrupt_rate > 0) 3277 newitr = (4000000 / ixgbe_max_interrupt_rate) & 0x0FF8; 3278 else { 3279 /* 3280 * Disable DMA coalescing if interrupt moderation is 3281 * disabled. 3282 */ 3283 sc->dmac = 0; 3284 newitr = 0; 3285 } 3286 3287 for (int i = 0; i < sc->num_rx_queues; i++, rx_que++) { 3288 struct rx_ring *rxr = &rx_que->rxr; 3289 3290 /* First the RX queue entry */ 3291 ixgbe_set_ivar(sc, rxr->me, rx_que->msix, 0); 3292 3293 /* Set an Initial EITR value */ 3294 IXGBE_WRITE_REG(&sc->hw, IXGBE_EITR(rx_que->msix), newitr); 3295 } 3296 for (int i = 0; i < sc->num_tx_queues; i++, tx_que++) { 3297 struct tx_ring *txr = &tx_que->txr; 3298 3299 /* ... and the TX */ 3300 ixgbe_set_ivar(sc, txr->me, tx_que->msix, 1); 3301 } 3302 /* For the Link interrupt */ 3303 ixgbe_set_ivar(sc, 1, sc->vector, -1); 3304 } /* ixgbe_configure_ivars */ 3305 3306 /************************************************************************ 3307 * ixgbe_config_gpie 3308 ************************************************************************/ 3309 static void 3310 ixgbe_config_gpie(struct ixgbe_softc *sc) 3311 { 3312 struct ixgbe_hw *hw = &sc->hw; 3313 u32 gpie; 3314 3315 gpie = IXGBE_READ_REG(hw, IXGBE_GPIE); 3316 3317 if (sc->intr_type == IFLIB_INTR_MSIX) { 3318 /* Enable Enhanced MSI-X mode */ 3319 gpie |= IXGBE_GPIE_MSIX_MODE 3320 | IXGBE_GPIE_EIAME 3321 | IXGBE_GPIE_PBA_SUPPORT 3322 | IXGBE_GPIE_OCD; 3323 } 3324 3325 /* Fan Failure Interrupt */ 3326 if (sc->feat_en & IXGBE_FEATURE_FAN_FAIL) 3327 gpie |= IXGBE_SDP1_GPIEN; 3328 3329 /* Thermal Sensor Interrupt */ 3330 if (sc->feat_en & IXGBE_FEATURE_TEMP_SENSOR) 3331 gpie |= IXGBE_SDP0_GPIEN_X540; 3332 3333 /* Link detection */ 3334 switch (hw->mac.type) { 3335 case ixgbe_mac_82599EB: 3336 gpie |= IXGBE_SDP1_GPIEN | IXGBE_SDP2_GPIEN; 3337 break; 3338 case ixgbe_mac_X550EM_x: 3339 case ixgbe_mac_X550EM_a: 3340 gpie |= IXGBE_SDP0_GPIEN_X540; 3341 break; 3342 default: 3343 break; 3344 } 3345 3346 IXGBE_WRITE_REG(hw, IXGBE_GPIE, gpie); 3347 3348 } /* ixgbe_config_gpie */ 3349 3350 /************************************************************************ 3351 * ixgbe_config_delay_values 3352 * 3353 * Requires sc->max_frame_size to be set. 3354 ************************************************************************/ 3355 static void 3356 ixgbe_config_delay_values(struct ixgbe_softc *sc) 3357 { 3358 struct ixgbe_hw *hw = &sc->hw; 3359 u32 rxpb, frame, size, tmp; 3360 3361 frame = sc->max_frame_size; 3362 3363 /* Calculate High Water */ 3364 switch (hw->mac.type) { 3365 case ixgbe_mac_X540: 3366 case ixgbe_mac_X550: 3367 case ixgbe_mac_X550EM_x: 3368 case ixgbe_mac_X550EM_a: 3369 tmp = IXGBE_DV_X540(frame, frame); 3370 break; 3371 default: 3372 tmp = IXGBE_DV(frame, frame); 3373 break; 3374 } 3375 size = IXGBE_BT2KB(tmp); 3376 rxpb = IXGBE_READ_REG(hw, IXGBE_RXPBSIZE(0)) >> 10; 3377 hw->fc.high_water[0] = rxpb - size; 3378 3379 /* Now calculate Low Water */ 3380 switch (hw->mac.type) { 3381 case ixgbe_mac_X540: 3382 case ixgbe_mac_X550: 3383 case ixgbe_mac_X550EM_x: 3384 case ixgbe_mac_X550EM_a: 3385 tmp = IXGBE_LOW_DV_X540(frame); 3386 break; 3387 default: 3388 tmp = IXGBE_LOW_DV(frame); 3389 break; 3390 } 3391 hw->fc.low_water[0] = IXGBE_BT2KB(tmp); 3392 3393 hw->fc.pause_time = IXGBE_FC_PAUSE; 3394 hw->fc.send_xon = true; 3395 } /* ixgbe_config_delay_values */ 3396 3397 /************************************************************************ 3398 * ixgbe_set_multi - Multicast Update 3399 * 3400 * Called whenever multicast address list is updated. 3401 ************************************************************************/ 3402 static u_int 3403 ixgbe_mc_filter_apply(void *arg, struct sockaddr_dl *sdl, u_int idx) 3404 { 3405 struct ixgbe_softc *sc = arg; 3406 struct ixgbe_mc_addr *mta = sc->mta; 3407 3408 if (idx == MAX_NUM_MULTICAST_ADDRESSES) 3409 return (0); 3410 bcopy(LLADDR(sdl), mta[idx].addr, IXGBE_ETH_LENGTH_OF_ADDRESS); 3411 mta[idx].vmdq = sc->pool; 3412 3413 return (1); 3414 } /* ixgbe_mc_filter_apply */ 3415 3416 static void 3417 ixgbe_if_multi_set(if_ctx_t ctx) 3418 { 3419 struct ixgbe_softc *sc = iflib_get_softc(ctx); 3420 struct ixgbe_mc_addr *mta; 3421 if_t ifp = iflib_get_ifp(ctx); 3422 u8 *update_ptr; 3423 u32 fctrl; 3424 u_int mcnt; 3425 3426 IOCTL_DEBUGOUT("ixgbe_if_multi_set: begin"); 3427 3428 mta = sc->mta; 3429 bzero(mta, sizeof(*mta) * MAX_NUM_MULTICAST_ADDRESSES); 3430 3431 mcnt = if_foreach_llmaddr(iflib_get_ifp(ctx), ixgbe_mc_filter_apply, sc); 3432 3433 if (mcnt < MAX_NUM_MULTICAST_ADDRESSES) { 3434 update_ptr = (u8 *)mta; 3435 ixgbe_update_mc_addr_list(&sc->hw, update_ptr, mcnt, 3436 ixgbe_mc_array_itr, true); 3437 } 3438 3439 fctrl = IXGBE_READ_REG(&sc->hw, IXGBE_FCTRL); 3440 3441 if (if_getflags(ifp) & IFF_PROMISC) 3442 fctrl |= (IXGBE_FCTRL_UPE | IXGBE_FCTRL_MPE); 3443 else if (mcnt >= MAX_NUM_MULTICAST_ADDRESSES || 3444 if_getflags(ifp) & IFF_ALLMULTI) { 3445 fctrl |= IXGBE_FCTRL_MPE; 3446 fctrl &= ~IXGBE_FCTRL_UPE; 3447 } else 3448 fctrl &= ~(IXGBE_FCTRL_UPE | IXGBE_FCTRL_MPE); 3449 3450 IXGBE_WRITE_REG(&sc->hw, IXGBE_FCTRL, fctrl); 3451 } /* ixgbe_if_multi_set */ 3452 3453 /************************************************************************ 3454 * ixgbe_mc_array_itr 3455 * 3456 * An iterator function needed by the multicast shared code. 3457 * It feeds the shared code routine the addresses in the 3458 * array of ixgbe_set_multi() one by one. 3459 ************************************************************************/ 3460 static u8 * 3461 ixgbe_mc_array_itr(struct ixgbe_hw *hw, u8 **update_ptr, u32 *vmdq) 3462 { 3463 struct ixgbe_mc_addr *mta; 3464 3465 mta = (struct ixgbe_mc_addr *)*update_ptr; 3466 *vmdq = mta->vmdq; 3467 3468 *update_ptr = (u8*)(mta + 1); 3469 3470 return (mta->addr); 3471 } /* ixgbe_mc_array_itr */ 3472 3473 /************************************************************************ 3474 * ixgbe_local_timer - Timer routine 3475 * 3476 * Checks for link status, updates statistics, 3477 * and runs the watchdog check. 3478 ************************************************************************/ 3479 static void 3480 ixgbe_if_timer(if_ctx_t ctx, uint16_t qid) 3481 { 3482 struct ixgbe_softc *sc = iflib_get_softc(ctx); 3483 3484 if (qid != 0) 3485 return; 3486 3487 /* Check for pluggable optics */ 3488 if (sc->sfp_probe) 3489 if (!ixgbe_sfp_probe(ctx)) 3490 return; /* Nothing to do */ 3491 3492 ixgbe_check_link(&sc->hw, &sc->link_speed, &sc->link_up, 0); 3493 3494 /* Fire off the adminq task */ 3495 iflib_admin_intr_deferred(ctx); 3496 3497 } /* ixgbe_if_timer */ 3498 3499 /************************************************************************ 3500 * ixgbe_sfp_probe 3501 * 3502 * Determine if a port had optics inserted. 3503 ************************************************************************/ 3504 static bool 3505 ixgbe_sfp_probe(if_ctx_t ctx) 3506 { 3507 struct ixgbe_softc *sc = iflib_get_softc(ctx); 3508 struct ixgbe_hw *hw = &sc->hw; 3509 device_t dev = iflib_get_dev(ctx); 3510 bool result = false; 3511 3512 if ((hw->phy.type == ixgbe_phy_nl) && 3513 (hw->phy.sfp_type == ixgbe_sfp_type_not_present)) { 3514 s32 ret = hw->phy.ops.identify_sfp(hw); 3515 if (ret) 3516 goto out; 3517 ret = hw->phy.ops.reset(hw); 3518 sc->sfp_probe = false; 3519 if (ret == IXGBE_ERR_SFP_NOT_SUPPORTED) { 3520 device_printf(dev, "Unsupported SFP+ module detected!"); 3521 device_printf(dev, 3522 "Reload driver with supported module.\n"); 3523 goto out; 3524 } else 3525 device_printf(dev, "SFP+ module detected!\n"); 3526 /* We now have supported optics */ 3527 result = true; 3528 } 3529 out: 3530 3531 return (result); 3532 } /* ixgbe_sfp_probe */ 3533 3534 /************************************************************************ 3535 * ixgbe_handle_mod - Tasklet for SFP module interrupts 3536 ************************************************************************/ 3537 static void 3538 ixgbe_handle_mod(void *context) 3539 { 3540 if_ctx_t ctx = context; 3541 struct ixgbe_softc *sc = iflib_get_softc(ctx); 3542 struct ixgbe_hw *hw = &sc->hw; 3543 device_t dev = iflib_get_dev(ctx); 3544 u32 err, cage_full = 0; 3545 3546 if (sc->hw.need_crosstalk_fix) { 3547 switch (hw->mac.type) { 3548 case ixgbe_mac_82599EB: 3549 cage_full = IXGBE_READ_REG(hw, IXGBE_ESDP) & 3550 IXGBE_ESDP_SDP2; 3551 break; 3552 case ixgbe_mac_X550EM_x: 3553 case ixgbe_mac_X550EM_a: 3554 cage_full = IXGBE_READ_REG(hw, IXGBE_ESDP) & 3555 IXGBE_ESDP_SDP0; 3556 break; 3557 default: 3558 break; 3559 } 3560 3561 if (!cage_full) 3562 goto handle_mod_out; 3563 } 3564 3565 err = hw->phy.ops.identify_sfp(hw); 3566 if (err == IXGBE_ERR_SFP_NOT_SUPPORTED) { 3567 device_printf(dev, 3568 "Unsupported SFP+ module type was detected.\n"); 3569 goto handle_mod_out; 3570 } 3571 3572 if (hw->mac.type == ixgbe_mac_82598EB) 3573 err = hw->phy.ops.reset(hw); 3574 else 3575 err = hw->mac.ops.setup_sfp(hw); 3576 3577 if (err == IXGBE_ERR_SFP_NOT_SUPPORTED) { 3578 device_printf(dev, 3579 "Setup failure - unsupported SFP+ module type.\n"); 3580 goto handle_mod_out; 3581 } 3582 sc->task_requests |= IXGBE_REQUEST_TASK_MSF; 3583 return; 3584 3585 handle_mod_out: 3586 sc->task_requests &= ~(IXGBE_REQUEST_TASK_MSF); 3587 } /* ixgbe_handle_mod */ 3588 3589 3590 /************************************************************************ 3591 * ixgbe_handle_msf - Tasklet for MSF (multispeed fiber) interrupts 3592 ************************************************************************/ 3593 static void 3594 ixgbe_handle_msf(void *context) 3595 { 3596 if_ctx_t ctx = context; 3597 struct ixgbe_softc *sc = iflib_get_softc(ctx); 3598 struct ixgbe_hw *hw = &sc->hw; 3599 u32 autoneg; 3600 bool negotiate; 3601 3602 /* get_supported_phy_layer will call hw->phy.ops.identify_sfp() */ 3603 sc->phy_layer = ixgbe_get_supported_physical_layer(hw); 3604 3605 autoneg = hw->phy.autoneg_advertised; 3606 if ((!autoneg) && (hw->mac.ops.get_link_capabilities)) 3607 hw->mac.ops.get_link_capabilities(hw, &autoneg, &negotiate); 3608 if (hw->mac.ops.setup_link) 3609 hw->mac.ops.setup_link(hw, autoneg, true); 3610 3611 /* Adjust media types shown in ifconfig */ 3612 ifmedia_removeall(sc->media); 3613 ixgbe_add_media_types(sc->ctx); 3614 ifmedia_set(sc->media, IFM_ETHER | IFM_AUTO); 3615 } /* ixgbe_handle_msf */ 3616 3617 /************************************************************************ 3618 * ixgbe_handle_phy - Tasklet for external PHY interrupts 3619 ************************************************************************/ 3620 static void 3621 ixgbe_handle_phy(void *context) 3622 { 3623 if_ctx_t ctx = context; 3624 struct ixgbe_softc *sc = iflib_get_softc(ctx); 3625 struct ixgbe_hw *hw = &sc->hw; 3626 int error; 3627 3628 error = hw->phy.ops.handle_lasi(hw); 3629 if (error == IXGBE_ERR_OVERTEMP) 3630 device_printf(sc->dev, "CRITICAL: EXTERNAL PHY OVER TEMP!! PHY will downshift to lower power state!\n"); 3631 else if (error) 3632 device_printf(sc->dev, 3633 "Error handling LASI interrupt: %d\n", error); 3634 } /* ixgbe_handle_phy */ 3635 3636 /************************************************************************ 3637 * ixgbe_if_stop - Stop the hardware 3638 * 3639 * Disables all traffic on the adapter by issuing a 3640 * global reset on the MAC and deallocates TX/RX buffers. 3641 ************************************************************************/ 3642 static void 3643 ixgbe_if_stop(if_ctx_t ctx) 3644 { 3645 struct ixgbe_softc *sc = iflib_get_softc(ctx); 3646 struct ixgbe_hw *hw = &sc->hw; 3647 3648 INIT_DEBUGOUT("ixgbe_if_stop: begin\n"); 3649 3650 ixgbe_reset_hw(hw); 3651 hw->adapter_stopped = false; 3652 ixgbe_stop_adapter(hw); 3653 if (hw->mac.type == ixgbe_mac_82599EB) 3654 ixgbe_stop_mac_link_on_d3_82599(hw); 3655 /* Turn off the laser - noop with no optics */ 3656 ixgbe_disable_tx_laser(hw); 3657 3658 /* Update the stack */ 3659 sc->link_up = false; 3660 ixgbe_if_update_admin_status(ctx); 3661 3662 /* reprogram the RAR[0] in case user changed it. */ 3663 ixgbe_set_rar(&sc->hw, 0, sc->hw.mac.addr, 0, IXGBE_RAH_AV); 3664 3665 return; 3666 } /* ixgbe_if_stop */ 3667 3668 /************************************************************************ 3669 * ixgbe_update_link_status - Update OS on link state 3670 * 3671 * Note: Only updates the OS on the cached link state. 3672 * The real check of the hardware only happens with 3673 * a link interrupt. 3674 ************************************************************************/ 3675 static void 3676 ixgbe_if_update_admin_status(if_ctx_t ctx) 3677 { 3678 struct ixgbe_softc *sc = iflib_get_softc(ctx); 3679 device_t dev = iflib_get_dev(ctx); 3680 3681 if (sc->link_up) { 3682 if (sc->link_active == false) { 3683 if (bootverbose) 3684 device_printf(dev, "Link is up %d Gbps %s \n", 3685 ((sc->link_speed == 128) ? 10 : 1), 3686 "Full Duplex"); 3687 sc->link_active = true; 3688 /* Update any Flow Control changes */ 3689 ixgbe_fc_enable(&sc->hw); 3690 /* Update DMA coalescing config */ 3691 ixgbe_config_dmac(sc); 3692 iflib_link_state_change(ctx, LINK_STATE_UP, 3693 ixgbe_link_speed_to_baudrate(sc->link_speed)); 3694 3695 if (sc->feat_en & IXGBE_FEATURE_SRIOV) 3696 ixgbe_ping_all_vfs(sc); 3697 } 3698 } else { /* Link down */ 3699 if (sc->link_active == true) { 3700 if (bootverbose) 3701 device_printf(dev, "Link is Down\n"); 3702 iflib_link_state_change(ctx, LINK_STATE_DOWN, 0); 3703 sc->link_active = false; 3704 if (sc->feat_en & IXGBE_FEATURE_SRIOV) 3705 ixgbe_ping_all_vfs(sc); 3706 } 3707 } 3708 3709 /* Handle task requests from msix_link() */ 3710 if (sc->task_requests & IXGBE_REQUEST_TASK_MOD) 3711 ixgbe_handle_mod(ctx); 3712 if (sc->task_requests & IXGBE_REQUEST_TASK_MSF) 3713 ixgbe_handle_msf(ctx); 3714 if (sc->task_requests & IXGBE_REQUEST_TASK_MBX) 3715 ixgbe_handle_mbx(ctx); 3716 if (sc->task_requests & IXGBE_REQUEST_TASK_FDIR) 3717 ixgbe_reinit_fdir(ctx); 3718 if (sc->task_requests & IXGBE_REQUEST_TASK_PHY) 3719 ixgbe_handle_phy(ctx); 3720 sc->task_requests = 0; 3721 3722 ixgbe_update_stats_counters(sc); 3723 } /* ixgbe_if_update_admin_status */ 3724 3725 /************************************************************************ 3726 * ixgbe_config_dmac - Configure DMA Coalescing 3727 ************************************************************************/ 3728 static void 3729 ixgbe_config_dmac(struct ixgbe_softc *sc) 3730 { 3731 struct ixgbe_hw *hw = &sc->hw; 3732 struct ixgbe_dmac_config *dcfg = &hw->mac.dmac_config; 3733 3734 if (hw->mac.type < ixgbe_mac_X550 || !hw->mac.ops.dmac_config) 3735 return; 3736 3737 if (dcfg->watchdog_timer ^ sc->dmac || 3738 dcfg->link_speed ^ sc->link_speed) { 3739 dcfg->watchdog_timer = sc->dmac; 3740 dcfg->fcoe_en = false; 3741 dcfg->link_speed = sc->link_speed; 3742 dcfg->num_tcs = 1; 3743 3744 INIT_DEBUGOUT2("dmac settings: watchdog %d, link speed %d\n", 3745 dcfg->watchdog_timer, dcfg->link_speed); 3746 3747 hw->mac.ops.dmac_config(hw); 3748 } 3749 } /* ixgbe_config_dmac */ 3750 3751 /************************************************************************ 3752 * ixgbe_if_enable_intr 3753 ************************************************************************/ 3754 void 3755 ixgbe_if_enable_intr(if_ctx_t ctx) 3756 { 3757 struct ixgbe_softc *sc = iflib_get_softc(ctx); 3758 struct ixgbe_hw *hw = &sc->hw; 3759 struct ix_rx_queue *que = sc->rx_queues; 3760 u32 mask, fwsm; 3761 3762 mask = (IXGBE_EIMS_ENABLE_MASK & ~IXGBE_EIMS_RTX_QUEUE); 3763 3764 switch (sc->hw.mac.type) { 3765 case ixgbe_mac_82599EB: 3766 mask |= IXGBE_EIMS_ECC; 3767 /* Temperature sensor on some scs */ 3768 mask |= IXGBE_EIMS_GPI_SDP0; 3769 /* SFP+ (RX_LOS_N & MOD_ABS_N) */ 3770 mask |= IXGBE_EIMS_GPI_SDP1; 3771 mask |= IXGBE_EIMS_GPI_SDP2; 3772 break; 3773 case ixgbe_mac_X540: 3774 /* Detect if Thermal Sensor is enabled */ 3775 fwsm = IXGBE_READ_REG(hw, IXGBE_FWSM); 3776 if (fwsm & IXGBE_FWSM_TS_ENABLED) 3777 mask |= IXGBE_EIMS_TS; 3778 mask |= IXGBE_EIMS_ECC; 3779 break; 3780 case ixgbe_mac_X550: 3781 /* MAC thermal sensor is automatically enabled */ 3782 mask |= IXGBE_EIMS_TS; 3783 mask |= IXGBE_EIMS_ECC; 3784 break; 3785 case ixgbe_mac_X550EM_x: 3786 case ixgbe_mac_X550EM_a: 3787 /* Some devices use SDP0 for important information */ 3788 if (hw->device_id == IXGBE_DEV_ID_X550EM_X_SFP || 3789 hw->device_id == IXGBE_DEV_ID_X550EM_A_SFP || 3790 hw->device_id == IXGBE_DEV_ID_X550EM_A_SFP_N || 3791 hw->device_id == IXGBE_DEV_ID_X550EM_X_10G_T) 3792 mask |= IXGBE_EIMS_GPI_SDP0_BY_MAC(hw); 3793 if (hw->phy.type == ixgbe_phy_x550em_ext_t) 3794 mask |= IXGBE_EICR_GPI_SDP0_X540; 3795 mask |= IXGBE_EIMS_ECC; 3796 break; 3797 default: 3798 break; 3799 } 3800 3801 /* Enable Fan Failure detection */ 3802 if (sc->feat_en & IXGBE_FEATURE_FAN_FAIL) 3803 mask |= IXGBE_EIMS_GPI_SDP1; 3804 /* Enable SR-IOV */ 3805 if (sc->feat_en & IXGBE_FEATURE_SRIOV) 3806 mask |= IXGBE_EIMS_MAILBOX; 3807 /* Enable Flow Director */ 3808 if (sc->feat_en & IXGBE_FEATURE_FDIR) 3809 mask |= IXGBE_EIMS_FLOW_DIR; 3810 3811 IXGBE_WRITE_REG(hw, IXGBE_EIMS, mask); 3812 3813 /* With MSI-X we use auto clear */ 3814 if (sc->intr_type == IFLIB_INTR_MSIX) { 3815 mask = IXGBE_EIMS_ENABLE_MASK; 3816 /* Don't autoclear Link */ 3817 mask &= ~IXGBE_EIMS_OTHER; 3818 mask &= ~IXGBE_EIMS_LSC; 3819 if (sc->feat_cap & IXGBE_FEATURE_SRIOV) 3820 mask &= ~IXGBE_EIMS_MAILBOX; 3821 IXGBE_WRITE_REG(hw, IXGBE_EIAC, mask); 3822 } 3823 3824 /* 3825 * Now enable all queues, this is done separately to 3826 * allow for handling the extended (beyond 32) MSI-X 3827 * vectors that can be used by 82599 3828 */ 3829 for (int i = 0; i < sc->num_rx_queues; i++, que++) 3830 ixgbe_enable_queue(sc, que->msix); 3831 3832 IXGBE_WRITE_FLUSH(hw); 3833 3834 } /* ixgbe_if_enable_intr */ 3835 3836 /************************************************************************ 3837 * ixgbe_disable_intr 3838 ************************************************************************/ 3839 static void 3840 ixgbe_if_disable_intr(if_ctx_t ctx) 3841 { 3842 struct ixgbe_softc *sc = iflib_get_softc(ctx); 3843 3844 if (sc->intr_type == IFLIB_INTR_MSIX) 3845 IXGBE_WRITE_REG(&sc->hw, IXGBE_EIAC, 0); 3846 if (sc->hw.mac.type == ixgbe_mac_82598EB) { 3847 IXGBE_WRITE_REG(&sc->hw, IXGBE_EIMC, ~0); 3848 } else { 3849 IXGBE_WRITE_REG(&sc->hw, IXGBE_EIMC, 0xFFFF0000); 3850 IXGBE_WRITE_REG(&sc->hw, IXGBE_EIMC_EX(0), ~0); 3851 IXGBE_WRITE_REG(&sc->hw, IXGBE_EIMC_EX(1), ~0); 3852 } 3853 IXGBE_WRITE_FLUSH(&sc->hw); 3854 3855 } /* ixgbe_if_disable_intr */ 3856 3857 /************************************************************************ 3858 * ixgbe_link_intr_enable 3859 ************************************************************************/ 3860 static void 3861 ixgbe_link_intr_enable(if_ctx_t ctx) 3862 { 3863 struct ixgbe_hw *hw = &((struct ixgbe_softc *)iflib_get_softc(ctx))->hw; 3864 3865 /* Re-enable other interrupts */ 3866 IXGBE_WRITE_REG(hw, IXGBE_EIMS, IXGBE_EIMS_OTHER | IXGBE_EIMS_LSC); 3867 } /* ixgbe_link_intr_enable */ 3868 3869 /************************************************************************ 3870 * ixgbe_if_rx_queue_intr_enable 3871 ************************************************************************/ 3872 static int 3873 ixgbe_if_rx_queue_intr_enable(if_ctx_t ctx, uint16_t rxqid) 3874 { 3875 struct ixgbe_softc *sc = iflib_get_softc(ctx); 3876 struct ix_rx_queue *que = &sc->rx_queues[rxqid]; 3877 3878 ixgbe_enable_queue(sc, que->msix); 3879 3880 return (0); 3881 } /* ixgbe_if_rx_queue_intr_enable */ 3882 3883 /************************************************************************ 3884 * ixgbe_enable_queue 3885 ************************************************************************/ 3886 static void 3887 ixgbe_enable_queue(struct ixgbe_softc *sc, u32 vector) 3888 { 3889 struct ixgbe_hw *hw = &sc->hw; 3890 u64 queue = 1ULL << vector; 3891 u32 mask; 3892 3893 if (hw->mac.type == ixgbe_mac_82598EB) { 3894 mask = (IXGBE_EIMS_RTX_QUEUE & queue); 3895 IXGBE_WRITE_REG(hw, IXGBE_EIMS, mask); 3896 } else { 3897 mask = (queue & 0xFFFFFFFF); 3898 if (mask) 3899 IXGBE_WRITE_REG(hw, IXGBE_EIMS_EX(0), mask); 3900 mask = (queue >> 32); 3901 if (mask) 3902 IXGBE_WRITE_REG(hw, IXGBE_EIMS_EX(1), mask); 3903 } 3904 } /* ixgbe_enable_queue */ 3905 3906 /************************************************************************ 3907 * ixgbe_disable_queue 3908 ************************************************************************/ 3909 static void 3910 ixgbe_disable_queue(struct ixgbe_softc *sc, u32 vector) 3911 { 3912 struct ixgbe_hw *hw = &sc->hw; 3913 u64 queue = 1ULL << vector; 3914 u32 mask; 3915 3916 if (hw->mac.type == ixgbe_mac_82598EB) { 3917 mask = (IXGBE_EIMS_RTX_QUEUE & queue); 3918 IXGBE_WRITE_REG(hw, IXGBE_EIMC, mask); 3919 } else { 3920 mask = (queue & 0xFFFFFFFF); 3921 if (mask) 3922 IXGBE_WRITE_REG(hw, IXGBE_EIMC_EX(0), mask); 3923 mask = (queue >> 32); 3924 if (mask) 3925 IXGBE_WRITE_REG(hw, IXGBE_EIMC_EX(1), mask); 3926 } 3927 } /* ixgbe_disable_queue */ 3928 3929 /************************************************************************ 3930 * ixgbe_intr - Legacy Interrupt Service Routine 3931 ************************************************************************/ 3932 int 3933 ixgbe_intr(void *arg) 3934 { 3935 struct ixgbe_softc *sc = arg; 3936 struct ix_rx_queue *que = sc->rx_queues; 3937 struct ixgbe_hw *hw = &sc->hw; 3938 if_ctx_t ctx = sc->ctx; 3939 u32 eicr, eicr_mask; 3940 3941 eicr = IXGBE_READ_REG(hw, IXGBE_EICR); 3942 3943 ++que->irqs; 3944 if (eicr == 0) { 3945 ixgbe_if_enable_intr(ctx); 3946 return (FILTER_HANDLED); 3947 } 3948 3949 /* Check for fan failure */ 3950 if ((hw->device_id == IXGBE_DEV_ID_82598AT) && 3951 (eicr & IXGBE_EICR_GPI_SDP1)) { 3952 device_printf(sc->dev, 3953 "\nCRITICAL: FAN FAILURE!! REPLACE IMMEDIATELY!!\n"); 3954 IXGBE_WRITE_REG(hw, IXGBE_EIMS, IXGBE_EICR_GPI_SDP1_BY_MAC(hw)); 3955 } 3956 3957 /* Link status change */ 3958 if (eicr & IXGBE_EICR_LSC) { 3959 IXGBE_WRITE_REG(hw, IXGBE_EIMC, IXGBE_EIMC_LSC); 3960 iflib_admin_intr_deferred(ctx); 3961 } 3962 3963 if (ixgbe_is_sfp(hw)) { 3964 /* Pluggable optics-related interrupt */ 3965 if (hw->mac.type >= ixgbe_mac_X540) 3966 eicr_mask = IXGBE_EICR_GPI_SDP0_X540; 3967 else 3968 eicr_mask = IXGBE_EICR_GPI_SDP2_BY_MAC(hw); 3969 3970 if (eicr & eicr_mask) { 3971 IXGBE_WRITE_REG(hw, IXGBE_EICR, eicr_mask); 3972 sc->task_requests |= IXGBE_REQUEST_TASK_MOD; 3973 } 3974 3975 if ((hw->mac.type == ixgbe_mac_82599EB) && 3976 (eicr & IXGBE_EICR_GPI_SDP1_BY_MAC(hw))) { 3977 IXGBE_WRITE_REG(hw, IXGBE_EICR, 3978 IXGBE_EICR_GPI_SDP1_BY_MAC(hw)); 3979 sc->task_requests |= IXGBE_REQUEST_TASK_MSF; 3980 } 3981 } 3982 3983 /* External PHY interrupt */ 3984 if ((hw->phy.type == ixgbe_phy_x550em_ext_t) && 3985 (eicr & IXGBE_EICR_GPI_SDP0_X540)) 3986 sc->task_requests |= IXGBE_REQUEST_TASK_PHY; 3987 3988 return (FILTER_SCHEDULE_THREAD); 3989 } /* ixgbe_intr */ 3990 3991 /************************************************************************ 3992 * ixgbe_free_pci_resources 3993 ************************************************************************/ 3994 static void 3995 ixgbe_free_pci_resources(if_ctx_t ctx) 3996 { 3997 struct ixgbe_softc *sc = iflib_get_softc(ctx); 3998 struct ix_rx_queue *que = sc->rx_queues; 3999 device_t dev = iflib_get_dev(ctx); 4000 4001 /* Release all MSI-X queue resources */ 4002 if (sc->intr_type == IFLIB_INTR_MSIX) 4003 iflib_irq_free(ctx, &sc->irq); 4004 4005 if (que != NULL) { 4006 for (int i = 0; i < sc->num_rx_queues; i++, que++) { 4007 iflib_irq_free(ctx, &que->que_irq); 4008 } 4009 } 4010 4011 if (sc->pci_mem != NULL) 4012 bus_release_resource(dev, SYS_RES_MEMORY, 4013 rman_get_rid(sc->pci_mem), sc->pci_mem); 4014 } /* ixgbe_free_pci_resources */ 4015 4016 /************************************************************************ 4017 * ixgbe_sysctl_flowcntl 4018 * 4019 * SYSCTL wrapper around setting Flow Control 4020 ************************************************************************/ 4021 static int 4022 ixgbe_sysctl_flowcntl(SYSCTL_HANDLER_ARGS) 4023 { 4024 struct ixgbe_softc *sc; 4025 int error, fc; 4026 4027 sc = (struct ixgbe_softc *)arg1; 4028 fc = sc->hw.fc.current_mode; 4029 4030 error = sysctl_handle_int(oidp, &fc, 0, req); 4031 if ((error) || (req->newptr == NULL)) 4032 return (error); 4033 4034 /* Don't bother if it's not changed */ 4035 if (fc == sc->hw.fc.current_mode) 4036 return (0); 4037 4038 return ixgbe_set_flowcntl(sc, fc); 4039 } /* ixgbe_sysctl_flowcntl */ 4040 4041 /************************************************************************ 4042 * ixgbe_set_flowcntl - Set flow control 4043 * 4044 * Flow control values: 4045 * 0 - off 4046 * 1 - rx pause 4047 * 2 - tx pause 4048 * 3 - full 4049 ************************************************************************/ 4050 static int 4051 ixgbe_set_flowcntl(struct ixgbe_softc *sc, int fc) 4052 { 4053 switch (fc) { 4054 case ixgbe_fc_rx_pause: 4055 case ixgbe_fc_tx_pause: 4056 case ixgbe_fc_full: 4057 sc->hw.fc.requested_mode = fc; 4058 if (sc->num_rx_queues > 1) 4059 ixgbe_disable_rx_drop(sc); 4060 break; 4061 case ixgbe_fc_none: 4062 sc->hw.fc.requested_mode = ixgbe_fc_none; 4063 if (sc->num_rx_queues > 1) 4064 ixgbe_enable_rx_drop(sc); 4065 break; 4066 default: 4067 return (EINVAL); 4068 } 4069 4070 /* Don't autoneg if forcing a value */ 4071 sc->hw.fc.disable_fc_autoneg = true; 4072 ixgbe_fc_enable(&sc->hw); 4073 4074 return (0); 4075 } /* ixgbe_set_flowcntl */ 4076 4077 /************************************************************************ 4078 * ixgbe_enable_rx_drop 4079 * 4080 * Enable the hardware to drop packets when the buffer is 4081 * full. This is useful with multiqueue, so that no single 4082 * queue being full stalls the entire RX engine. We only 4083 * enable this when Multiqueue is enabled AND Flow Control 4084 * is disabled. 4085 ************************************************************************/ 4086 static void 4087 ixgbe_enable_rx_drop(struct ixgbe_softc *sc) 4088 { 4089 struct ixgbe_hw *hw = &sc->hw; 4090 struct rx_ring *rxr; 4091 u32 srrctl; 4092 4093 for (int i = 0; i < sc->num_rx_queues; i++) { 4094 rxr = &sc->rx_queues[i].rxr; 4095 srrctl = IXGBE_READ_REG(hw, IXGBE_SRRCTL(rxr->me)); 4096 srrctl |= IXGBE_SRRCTL_DROP_EN; 4097 IXGBE_WRITE_REG(hw, IXGBE_SRRCTL(rxr->me), srrctl); 4098 } 4099 4100 /* enable drop for each vf */ 4101 for (int i = 0; i < sc->num_vfs; i++) { 4102 IXGBE_WRITE_REG(hw, IXGBE_QDE, 4103 (IXGBE_QDE_WRITE | (i << IXGBE_QDE_IDX_SHIFT) | 4104 IXGBE_QDE_ENABLE)); 4105 } 4106 } /* ixgbe_enable_rx_drop */ 4107 4108 /************************************************************************ 4109 * ixgbe_disable_rx_drop 4110 ************************************************************************/ 4111 static void 4112 ixgbe_disable_rx_drop(struct ixgbe_softc *sc) 4113 { 4114 struct ixgbe_hw *hw = &sc->hw; 4115 struct rx_ring *rxr; 4116 u32 srrctl; 4117 4118 for (int i = 0; i < sc->num_rx_queues; i++) { 4119 rxr = &sc->rx_queues[i].rxr; 4120 srrctl = IXGBE_READ_REG(hw, IXGBE_SRRCTL(rxr->me)); 4121 srrctl &= ~IXGBE_SRRCTL_DROP_EN; 4122 IXGBE_WRITE_REG(hw, IXGBE_SRRCTL(rxr->me), srrctl); 4123 } 4124 4125 /* disable drop for each vf */ 4126 for (int i = 0; i < sc->num_vfs; i++) { 4127 IXGBE_WRITE_REG(hw, IXGBE_QDE, 4128 (IXGBE_QDE_WRITE | (i << IXGBE_QDE_IDX_SHIFT))); 4129 } 4130 } /* ixgbe_disable_rx_drop */ 4131 4132 /************************************************************************ 4133 * ixgbe_sysctl_advertise 4134 * 4135 * SYSCTL wrapper around setting advertised speed 4136 ************************************************************************/ 4137 static int 4138 ixgbe_sysctl_advertise(SYSCTL_HANDLER_ARGS) 4139 { 4140 struct ixgbe_softc *sc; 4141 int error, advertise; 4142 4143 sc = (struct ixgbe_softc *)arg1; 4144 advertise = sc->advertise; 4145 4146 error = sysctl_handle_int(oidp, &advertise, 0, req); 4147 if ((error) || (req->newptr == NULL)) 4148 return (error); 4149 4150 return ixgbe_set_advertise(sc, advertise); 4151 } /* ixgbe_sysctl_advertise */ 4152 4153 /************************************************************************ 4154 * ixgbe_set_advertise - Control advertised link speed 4155 * 4156 * Flags: 4157 * 0x1 - advertise 100 Mb 4158 * 0x2 - advertise 1G 4159 * 0x4 - advertise 10G 4160 * 0x8 - advertise 10 Mb (yes, Mb) 4161 * 0x10 - advertise 2.5G (disabled by default) 4162 * 0x20 - advertise 5G (disabled by default) 4163 * 4164 ************************************************************************/ 4165 static int 4166 ixgbe_set_advertise(struct ixgbe_softc *sc, int advertise) 4167 { 4168 device_t dev = iflib_get_dev(sc->ctx); 4169 struct ixgbe_hw *hw; 4170 ixgbe_link_speed speed = 0; 4171 ixgbe_link_speed link_caps = 0; 4172 s32 err = IXGBE_NOT_IMPLEMENTED; 4173 bool negotiate = false; 4174 4175 /* Checks to validate new value */ 4176 if (sc->advertise == advertise) /* no change */ 4177 return (0); 4178 4179 hw = &sc->hw; 4180 4181 /* No speed changes for backplane media */ 4182 if (hw->phy.media_type == ixgbe_media_type_backplane) 4183 return (ENODEV); 4184 4185 if (!((hw->phy.media_type == ixgbe_media_type_copper) || 4186 (hw->phy.multispeed_fiber))) { 4187 device_printf(dev, "Advertised speed can only be set on copper or multispeed fiber media types.\n"); 4188 return (EINVAL); 4189 } 4190 4191 if (advertise < 0x1 || advertise > 0x3F) { 4192 device_printf(dev, "Invalid advertised speed; valid modes are 0x1 through 0x3F\n"); 4193 return (EINVAL); 4194 } 4195 4196 if (hw->mac.ops.get_link_capabilities) { 4197 err = hw->mac.ops.get_link_capabilities(hw, &link_caps, 4198 &negotiate); 4199 if (err != IXGBE_SUCCESS) { 4200 device_printf(dev, "Unable to determine supported advertise speeds\n"); 4201 return (ENODEV); 4202 } 4203 } 4204 4205 /* Set new value and report new advertised mode */ 4206 if (advertise & 0x1) { 4207 if (!(link_caps & IXGBE_LINK_SPEED_100_FULL)) { 4208 device_printf(dev, "Interface does not support 100Mb advertised speed\n"); 4209 return (EINVAL); 4210 } 4211 speed |= IXGBE_LINK_SPEED_100_FULL; 4212 } 4213 if (advertise & 0x2) { 4214 if (!(link_caps & IXGBE_LINK_SPEED_1GB_FULL)) { 4215 device_printf(dev, "Interface does not support 1Gb advertised speed\n"); 4216 return (EINVAL); 4217 } 4218 speed |= IXGBE_LINK_SPEED_1GB_FULL; 4219 } 4220 if (advertise & 0x4) { 4221 if (!(link_caps & IXGBE_LINK_SPEED_10GB_FULL)) { 4222 device_printf(dev, "Interface does not support 10Gb advertised speed\n"); 4223 return (EINVAL); 4224 } 4225 speed |= IXGBE_LINK_SPEED_10GB_FULL; 4226 } 4227 if (advertise & 0x8) { 4228 if (!(link_caps & IXGBE_LINK_SPEED_10_FULL)) { 4229 device_printf(dev, "Interface does not support 10Mb advertised speed\n"); 4230 return (EINVAL); 4231 } 4232 speed |= IXGBE_LINK_SPEED_10_FULL; 4233 } 4234 if (advertise & 0x10) { 4235 if (!(link_caps & IXGBE_LINK_SPEED_2_5GB_FULL)) { 4236 device_printf(dev, "Interface does not support 2.5G advertised speed\n"); 4237 return (EINVAL); 4238 } 4239 speed |= IXGBE_LINK_SPEED_2_5GB_FULL; 4240 } 4241 if (advertise & 0x20) { 4242 if (!(link_caps & IXGBE_LINK_SPEED_5GB_FULL)) { 4243 device_printf(dev, "Interface does not support 5G advertised speed\n"); 4244 return (EINVAL); 4245 } 4246 speed |= IXGBE_LINK_SPEED_5GB_FULL; 4247 } 4248 4249 hw->mac.autotry_restart = true; 4250 hw->mac.ops.setup_link(hw, speed, true); 4251 sc->advertise = advertise; 4252 4253 return (0); 4254 } /* ixgbe_set_advertise */ 4255 4256 /************************************************************************ 4257 * ixgbe_get_default_advertise - Get default advertised speed settings 4258 * 4259 * Formatted for sysctl usage. 4260 * Flags: 4261 * 0x1 - advertise 100 Mb 4262 * 0x2 - advertise 1G 4263 * 0x4 - advertise 10G 4264 * 0x8 - advertise 10 Mb (yes, Mb) 4265 * 0x10 - advertise 2.5G (disabled by default) 4266 * 0x20 - advertise 5G (disabled by default) 4267 ************************************************************************/ 4268 static int 4269 ixgbe_get_default_advertise(struct ixgbe_softc *sc) 4270 { 4271 struct ixgbe_hw *hw = &sc->hw; 4272 int speed; 4273 ixgbe_link_speed link_caps = 0; 4274 s32 err; 4275 bool negotiate = false; 4276 4277 /* 4278 * Advertised speed means nothing unless it's copper or 4279 * multi-speed fiber 4280 */ 4281 if (!(hw->phy.media_type == ixgbe_media_type_copper) && 4282 !(hw->phy.multispeed_fiber)) 4283 return (0); 4284 4285 err = hw->mac.ops.get_link_capabilities(hw, &link_caps, &negotiate); 4286 if (err != IXGBE_SUCCESS) 4287 return (0); 4288 4289 if (hw->mac.type == ixgbe_mac_X550) { 4290 /* 4291 * 2.5G and 5G autonegotiation speeds on X550 4292 * are disabled by default due to reported 4293 * interoperability issues with some switches. 4294 */ 4295 link_caps &= ~(IXGBE_LINK_SPEED_2_5GB_FULL | 4296 IXGBE_LINK_SPEED_5GB_FULL); 4297 } 4298 4299 speed = 4300 ((link_caps & IXGBE_LINK_SPEED_10GB_FULL) ? 0x4 : 0) | 4301 ((link_caps & IXGBE_LINK_SPEED_5GB_FULL) ? 0x20 : 0) | 4302 ((link_caps & IXGBE_LINK_SPEED_2_5GB_FULL) ? 0x10 : 0) | 4303 ((link_caps & IXGBE_LINK_SPEED_1GB_FULL) ? 0x2 : 0) | 4304 ((link_caps & IXGBE_LINK_SPEED_100_FULL) ? 0x1 : 0) | 4305 ((link_caps & IXGBE_LINK_SPEED_10_FULL) ? 0x8 : 0); 4306 4307 return speed; 4308 } /* ixgbe_get_default_advertise */ 4309 4310 /************************************************************************ 4311 * ixgbe_sysctl_dmac - Manage DMA Coalescing 4312 * 4313 * Control values: 4314 * 0/1 - off / on (use default value of 1000) 4315 * 4316 * Legal timer values are: 4317 * 50,100,250,500,1000,2000,5000,10000 4318 * 4319 * Turning off interrupt moderation will also turn this off. 4320 ************************************************************************/ 4321 static int 4322 ixgbe_sysctl_dmac(SYSCTL_HANDLER_ARGS) 4323 { 4324 struct ixgbe_softc *sc = (struct ixgbe_softc *)arg1; 4325 if_t ifp = iflib_get_ifp(sc->ctx); 4326 int error; 4327 u16 newval; 4328 4329 newval = sc->dmac; 4330 error = sysctl_handle_16(oidp, &newval, 0, req); 4331 if ((error) || (req->newptr == NULL)) 4332 return (error); 4333 4334 switch (newval) { 4335 case 0: 4336 /* Disabled */ 4337 sc->dmac = 0; 4338 break; 4339 case 1: 4340 /* Enable and use default */ 4341 sc->dmac = 1000; 4342 break; 4343 case 50: 4344 case 100: 4345 case 250: 4346 case 500: 4347 case 1000: 4348 case 2000: 4349 case 5000: 4350 case 10000: 4351 /* Legal values - allow */ 4352 sc->dmac = newval; 4353 break; 4354 default: 4355 /* Do nothing, illegal value */ 4356 return (EINVAL); 4357 } 4358 4359 /* Re-initialize hardware if it's already running */ 4360 if (if_getdrvflags(ifp) & IFF_DRV_RUNNING) 4361 if_init(ifp, ifp); 4362 4363 return (0); 4364 } /* ixgbe_sysctl_dmac */ 4365 4366 #ifdef IXGBE_DEBUG 4367 /************************************************************************ 4368 * ixgbe_sysctl_power_state 4369 * 4370 * Sysctl to test power states 4371 * Values: 4372 * 0 - set device to D0 4373 * 3 - set device to D3 4374 * (none) - get current device power state 4375 ************************************************************************/ 4376 static int 4377 ixgbe_sysctl_power_state(SYSCTL_HANDLER_ARGS) 4378 { 4379 struct ixgbe_softc *sc = (struct ixgbe_softc *)arg1; 4380 device_t dev = sc->dev; 4381 int curr_ps, new_ps, error = 0; 4382 4383 curr_ps = new_ps = pci_get_powerstate(dev); 4384 4385 error = sysctl_handle_int(oidp, &new_ps, 0, req); 4386 if ((error) || (req->newptr == NULL)) 4387 return (error); 4388 4389 if (new_ps == curr_ps) 4390 return (0); 4391 4392 if (new_ps == 3 && curr_ps == 0) 4393 error = DEVICE_SUSPEND(dev); 4394 else if (new_ps == 0 && curr_ps == 3) 4395 error = DEVICE_RESUME(dev); 4396 else 4397 return (EINVAL); 4398 4399 device_printf(dev, "New state: %d\n", pci_get_powerstate(dev)); 4400 4401 return (error); 4402 } /* ixgbe_sysctl_power_state */ 4403 #endif 4404 4405 /************************************************************************ 4406 * ixgbe_sysctl_wol_enable 4407 * 4408 * Sysctl to enable/disable the WoL capability, 4409 * if supported by the adapter. 4410 * 4411 * Values: 4412 * 0 - disabled 4413 * 1 - enabled 4414 ************************************************************************/ 4415 static int 4416 ixgbe_sysctl_wol_enable(SYSCTL_HANDLER_ARGS) 4417 { 4418 struct ixgbe_softc *sc = (struct ixgbe_softc *)arg1; 4419 struct ixgbe_hw *hw = &sc->hw; 4420 int new_wol_enabled; 4421 int error = 0; 4422 4423 new_wol_enabled = hw->wol_enabled; 4424 error = sysctl_handle_int(oidp, &new_wol_enabled, 0, req); 4425 if ((error) || (req->newptr == NULL)) 4426 return (error); 4427 new_wol_enabled = !!(new_wol_enabled); 4428 if (new_wol_enabled == hw->wol_enabled) 4429 return (0); 4430 4431 if (new_wol_enabled > 0 && !sc->wol_support) 4432 return (ENODEV); 4433 else 4434 hw->wol_enabled = new_wol_enabled; 4435 4436 return (0); 4437 } /* ixgbe_sysctl_wol_enable */ 4438 4439 /************************************************************************ 4440 * ixgbe_sysctl_wufc - Wake Up Filter Control 4441 * 4442 * Sysctl to enable/disable the types of packets that the 4443 * adapter will wake up on upon receipt. 4444 * Flags: 4445 * 0x1 - Link Status Change 4446 * 0x2 - Magic Packet 4447 * 0x4 - Direct Exact 4448 * 0x8 - Directed Multicast 4449 * 0x10 - Broadcast 4450 * 0x20 - ARP/IPv4 Request Packet 4451 * 0x40 - Direct IPv4 Packet 4452 * 0x80 - Direct IPv6 Packet 4453 * 4454 * Settings not listed above will cause the sysctl to return an error. 4455 ************************************************************************/ 4456 static int 4457 ixgbe_sysctl_wufc(SYSCTL_HANDLER_ARGS) 4458 { 4459 struct ixgbe_softc *sc = (struct ixgbe_softc *)arg1; 4460 int error = 0; 4461 u32 new_wufc; 4462 4463 new_wufc = sc->wufc; 4464 4465 error = sysctl_handle_32(oidp, &new_wufc, 0, req); 4466 if ((error) || (req->newptr == NULL)) 4467 return (error); 4468 if (new_wufc == sc->wufc) 4469 return (0); 4470 4471 if (new_wufc & 0xffffff00) 4472 return (EINVAL); 4473 4474 new_wufc &= 0xff; 4475 new_wufc |= (0xffffff & sc->wufc); 4476 sc->wufc = new_wufc; 4477 4478 return (0); 4479 } /* ixgbe_sysctl_wufc */ 4480 4481 #ifdef IXGBE_DEBUG 4482 /************************************************************************ 4483 * ixgbe_sysctl_print_rss_config 4484 ************************************************************************/ 4485 static int 4486 ixgbe_sysctl_print_rss_config(SYSCTL_HANDLER_ARGS) 4487 { 4488 struct ixgbe_softc *sc = (struct ixgbe_softc *)arg1; 4489 struct ixgbe_hw *hw = &sc->hw; 4490 device_t dev = sc->dev; 4491 struct sbuf *buf; 4492 int error = 0, reta_size; 4493 u32 reg; 4494 4495 buf = sbuf_new_for_sysctl(NULL, NULL, 128, req); 4496 if (!buf) { 4497 device_printf(dev, "Could not allocate sbuf for output.\n"); 4498 return (ENOMEM); 4499 } 4500 4501 // TODO: use sbufs to make a string to print out 4502 /* Set multiplier for RETA setup and table size based on MAC */ 4503 switch (sc->hw.mac.type) { 4504 case ixgbe_mac_X550: 4505 case ixgbe_mac_X550EM_x: 4506 case ixgbe_mac_X550EM_a: 4507 reta_size = 128; 4508 break; 4509 default: 4510 reta_size = 32; 4511 break; 4512 } 4513 4514 /* Print out the redirection table */ 4515 sbuf_cat(buf, "\n"); 4516 for (int i = 0; i < reta_size; i++) { 4517 if (i < 32) { 4518 reg = IXGBE_READ_REG(hw, IXGBE_RETA(i)); 4519 sbuf_printf(buf, "RETA(%2d): 0x%08x\n", i, reg); 4520 } else { 4521 reg = IXGBE_READ_REG(hw, IXGBE_ERETA(i - 32)); 4522 sbuf_printf(buf, "ERETA(%2d): 0x%08x\n", i - 32, reg); 4523 } 4524 } 4525 4526 // TODO: print more config 4527 4528 error = sbuf_finish(buf); 4529 if (error) 4530 device_printf(dev, "Error finishing sbuf: %d\n", error); 4531 4532 sbuf_delete(buf); 4533 4534 return (0); 4535 } /* ixgbe_sysctl_print_rss_config */ 4536 #endif /* IXGBE_DEBUG */ 4537 4538 /************************************************************************ 4539 * ixgbe_sysctl_phy_temp - Retrieve temperature of PHY 4540 * 4541 * For X552/X557-AT devices using an external PHY 4542 ************************************************************************/ 4543 static int 4544 ixgbe_sysctl_phy_temp(SYSCTL_HANDLER_ARGS) 4545 { 4546 struct ixgbe_softc *sc = (struct ixgbe_softc *)arg1; 4547 struct ixgbe_hw *hw = &sc->hw; 4548 u16 reg; 4549 4550 if (hw->device_id != IXGBE_DEV_ID_X550EM_X_10G_T) { 4551 device_printf(iflib_get_dev(sc->ctx), 4552 "Device has no supported external thermal sensor.\n"); 4553 return (ENODEV); 4554 } 4555 4556 if (hw->phy.ops.read_reg(hw, IXGBE_PHY_CURRENT_TEMP, 4557 IXGBE_MDIO_VENDOR_SPECIFIC_1_DEV_TYPE, ®)) { 4558 device_printf(iflib_get_dev(sc->ctx), 4559 "Error reading from PHY's current temperature register\n"); 4560 return (EAGAIN); 4561 } 4562 4563 /* Shift temp for output */ 4564 reg = reg >> 8; 4565 4566 return (sysctl_handle_16(oidp, NULL, reg, req)); 4567 } /* ixgbe_sysctl_phy_temp */ 4568 4569 /************************************************************************ 4570 * ixgbe_sysctl_phy_overtemp_occurred 4571 * 4572 * Reports (directly from the PHY) whether the current PHY 4573 * temperature is over the overtemp threshold. 4574 ************************************************************************/ 4575 static int 4576 ixgbe_sysctl_phy_overtemp_occurred(SYSCTL_HANDLER_ARGS) 4577 { 4578 struct ixgbe_softc *sc = (struct ixgbe_softc *)arg1; 4579 struct ixgbe_hw *hw = &sc->hw; 4580 u16 reg; 4581 4582 if (hw->device_id != IXGBE_DEV_ID_X550EM_X_10G_T) { 4583 device_printf(iflib_get_dev(sc->ctx), 4584 "Device has no supported external thermal sensor.\n"); 4585 return (ENODEV); 4586 } 4587 4588 if (hw->phy.ops.read_reg(hw, IXGBE_PHY_OVERTEMP_STATUS, 4589 IXGBE_MDIO_VENDOR_SPECIFIC_1_DEV_TYPE, ®)) { 4590 device_printf(iflib_get_dev(sc->ctx), 4591 "Error reading from PHY's temperature status register\n"); 4592 return (EAGAIN); 4593 } 4594 4595 /* Get occurrence bit */ 4596 reg = !!(reg & 0x4000); 4597 4598 return (sysctl_handle_16(oidp, 0, reg, req)); 4599 } /* ixgbe_sysctl_phy_overtemp_occurred */ 4600 4601 /************************************************************************ 4602 * ixgbe_sysctl_eee_state 4603 * 4604 * Sysctl to set EEE power saving feature 4605 * Values: 4606 * 0 - disable EEE 4607 * 1 - enable EEE 4608 * (none) - get current device EEE state 4609 ************************************************************************/ 4610 static int 4611 ixgbe_sysctl_eee_state(SYSCTL_HANDLER_ARGS) 4612 { 4613 struct ixgbe_softc *sc = (struct ixgbe_softc *)arg1; 4614 device_t dev = sc->dev; 4615 if_t ifp = iflib_get_ifp(sc->ctx); 4616 int curr_eee, new_eee, error = 0; 4617 s32 retval; 4618 4619 curr_eee = new_eee = !!(sc->feat_en & IXGBE_FEATURE_EEE); 4620 4621 error = sysctl_handle_int(oidp, &new_eee, 0, req); 4622 if ((error) || (req->newptr == NULL)) 4623 return (error); 4624 4625 /* Nothing to do */ 4626 if (new_eee == curr_eee) 4627 return (0); 4628 4629 /* Not supported */ 4630 if (!(sc->feat_cap & IXGBE_FEATURE_EEE)) 4631 return (EINVAL); 4632 4633 /* Bounds checking */ 4634 if ((new_eee < 0) || (new_eee > 1)) 4635 return (EINVAL); 4636 4637 retval = ixgbe_setup_eee(&sc->hw, new_eee); 4638 if (retval) { 4639 device_printf(dev, "Error in EEE setup: 0x%08X\n", retval); 4640 return (EINVAL); 4641 } 4642 4643 /* Restart auto-neg */ 4644 if_init(ifp, ifp); 4645 4646 device_printf(dev, "New EEE state: %d\n", new_eee); 4647 4648 /* Cache new value */ 4649 if (new_eee) 4650 sc->feat_en |= IXGBE_FEATURE_EEE; 4651 else 4652 sc->feat_en &= ~IXGBE_FEATURE_EEE; 4653 4654 return (error); 4655 } /* ixgbe_sysctl_eee_state */ 4656 4657 /************************************************************************ 4658 * ixgbe_init_device_features 4659 ************************************************************************/ 4660 static void 4661 ixgbe_init_device_features(struct ixgbe_softc *sc) 4662 { 4663 sc->feat_cap = IXGBE_FEATURE_NETMAP 4664 | IXGBE_FEATURE_RSS 4665 | IXGBE_FEATURE_MSI 4666 | IXGBE_FEATURE_MSIX 4667 | IXGBE_FEATURE_LEGACY_IRQ; 4668 4669 /* Set capabilities first... */ 4670 switch (sc->hw.mac.type) { 4671 case ixgbe_mac_82598EB: 4672 if (sc->hw.device_id == IXGBE_DEV_ID_82598AT) 4673 sc->feat_cap |= IXGBE_FEATURE_FAN_FAIL; 4674 break; 4675 case ixgbe_mac_X540: 4676 sc->feat_cap |= IXGBE_FEATURE_SRIOV; 4677 sc->feat_cap |= IXGBE_FEATURE_FDIR; 4678 if ((sc->hw.device_id == IXGBE_DEV_ID_X540_BYPASS) && 4679 (sc->hw.bus.func == 0)) 4680 sc->feat_cap |= IXGBE_FEATURE_BYPASS; 4681 break; 4682 case ixgbe_mac_X550: 4683 sc->feat_cap |= IXGBE_FEATURE_TEMP_SENSOR; 4684 sc->feat_cap |= IXGBE_FEATURE_SRIOV; 4685 sc->feat_cap |= IXGBE_FEATURE_FDIR; 4686 break; 4687 case ixgbe_mac_X550EM_x: 4688 sc->feat_cap |= IXGBE_FEATURE_SRIOV; 4689 sc->feat_cap |= IXGBE_FEATURE_FDIR; 4690 break; 4691 case ixgbe_mac_X550EM_a: 4692 sc->feat_cap |= IXGBE_FEATURE_SRIOV; 4693 sc->feat_cap |= IXGBE_FEATURE_FDIR; 4694 sc->feat_cap &= ~IXGBE_FEATURE_LEGACY_IRQ; 4695 if ((sc->hw.device_id == IXGBE_DEV_ID_X550EM_A_1G_T) || 4696 (sc->hw.device_id == IXGBE_DEV_ID_X550EM_A_1G_T_L)) { 4697 sc->feat_cap |= IXGBE_FEATURE_TEMP_SENSOR; 4698 sc->feat_cap |= IXGBE_FEATURE_EEE; 4699 } 4700 break; 4701 case ixgbe_mac_82599EB: 4702 sc->feat_cap |= IXGBE_FEATURE_SRIOV; 4703 sc->feat_cap |= IXGBE_FEATURE_FDIR; 4704 if ((sc->hw.device_id == IXGBE_DEV_ID_82599_BYPASS) && 4705 (sc->hw.bus.func == 0)) 4706 sc->feat_cap |= IXGBE_FEATURE_BYPASS; 4707 if (sc->hw.device_id == IXGBE_DEV_ID_82599_QSFP_SF_QP) 4708 sc->feat_cap &= ~IXGBE_FEATURE_LEGACY_IRQ; 4709 break; 4710 default: 4711 break; 4712 } 4713 4714 /* Enabled by default... */ 4715 /* Fan failure detection */ 4716 if (sc->feat_cap & IXGBE_FEATURE_FAN_FAIL) 4717 sc->feat_en |= IXGBE_FEATURE_FAN_FAIL; 4718 /* Netmap */ 4719 if (sc->feat_cap & IXGBE_FEATURE_NETMAP) 4720 sc->feat_en |= IXGBE_FEATURE_NETMAP; 4721 /* EEE */ 4722 if (sc->feat_cap & IXGBE_FEATURE_EEE) 4723 sc->feat_en |= IXGBE_FEATURE_EEE; 4724 /* Thermal Sensor */ 4725 if (sc->feat_cap & IXGBE_FEATURE_TEMP_SENSOR) 4726 sc->feat_en |= IXGBE_FEATURE_TEMP_SENSOR; 4727 4728 /* Enabled via global sysctl... */ 4729 /* Flow Director */ 4730 if (ixgbe_enable_fdir) { 4731 if (sc->feat_cap & IXGBE_FEATURE_FDIR) 4732 sc->feat_en |= IXGBE_FEATURE_FDIR; 4733 else 4734 device_printf(sc->dev, "Device does not support Flow Director. Leaving disabled."); 4735 } 4736 /* 4737 * Message Signal Interrupts - Extended (MSI-X) 4738 * Normal MSI is only enabled if MSI-X calls fail. 4739 */ 4740 if (!ixgbe_enable_msix) 4741 sc->feat_cap &= ~IXGBE_FEATURE_MSIX; 4742 /* Receive-Side Scaling (RSS) */ 4743 if ((sc->feat_cap & IXGBE_FEATURE_RSS) && ixgbe_enable_rss) 4744 sc->feat_en |= IXGBE_FEATURE_RSS; 4745 4746 /* Disable features with unmet dependencies... */ 4747 /* No MSI-X */ 4748 if (!(sc->feat_cap & IXGBE_FEATURE_MSIX)) { 4749 sc->feat_cap &= ~IXGBE_FEATURE_RSS; 4750 sc->feat_cap &= ~IXGBE_FEATURE_SRIOV; 4751 sc->feat_en &= ~IXGBE_FEATURE_RSS; 4752 sc->feat_en &= ~IXGBE_FEATURE_SRIOV; 4753 } 4754 } /* ixgbe_init_device_features */ 4755 4756 /************************************************************************ 4757 * ixgbe_check_fan_failure 4758 ************************************************************************/ 4759 static void 4760 ixgbe_check_fan_failure(struct ixgbe_softc *sc, u32 reg, bool in_interrupt) 4761 { 4762 u32 mask; 4763 4764 mask = (in_interrupt) ? IXGBE_EICR_GPI_SDP1_BY_MAC(&sc->hw) : 4765 IXGBE_ESDP_SDP1; 4766 4767 if (reg & mask) 4768 device_printf(sc->dev, "\nCRITICAL: FAN FAILURE!! REPLACE IMMEDIATELY!!\n"); 4769 } /* ixgbe_check_fan_failure */ 4770 4771 /************************************************************************ 4772 * ixgbe_sbuf_fw_version 4773 ************************************************************************/ 4774 static void 4775 ixgbe_sbuf_fw_version(struct ixgbe_hw *hw, struct sbuf *buf) 4776 { 4777 struct ixgbe_nvm_version nvm_ver = {0}; 4778 uint16_t phyfw = 0; 4779 int status; 4780 const char *space = ""; 4781 4782 ixgbe_get_oem_prod_version(hw, &nvm_ver); /* OEM's NVM version */ 4783 ixgbe_get_orom_version(hw, &nvm_ver); /* Option ROM */ 4784 ixgbe_get_etk_id(hw, &nvm_ver); /* eTrack identifies a build in Intel's SCM */ 4785 status = ixgbe_get_phy_firmware_version(hw, &phyfw); 4786 4787 if (nvm_ver.oem_valid) { 4788 sbuf_printf(buf, "NVM OEM V%d.%d R%d", nvm_ver.oem_major, 4789 nvm_ver.oem_minor, nvm_ver.oem_release); 4790 space = " "; 4791 } 4792 4793 if (nvm_ver.or_valid) { 4794 sbuf_printf(buf, "%sOption ROM V%d-b%d-p%d", 4795 space, nvm_ver.or_major, nvm_ver.or_build, nvm_ver.or_patch); 4796 space = " "; 4797 } 4798 4799 if (nvm_ver.etk_id != ((NVM_VER_INVALID << NVM_ETK_SHIFT) | 4800 NVM_VER_INVALID)) { 4801 sbuf_printf(buf, "%seTrack 0x%08x", space, nvm_ver.etk_id); 4802 space = " "; 4803 } 4804 4805 if (phyfw != 0 && status == IXGBE_SUCCESS) 4806 sbuf_printf(buf, "%sPHY FW V%d", space, phyfw); 4807 } /* ixgbe_sbuf_fw_version */ 4808 4809 /************************************************************************ 4810 * ixgbe_print_fw_version 4811 ************************************************************************/ 4812 static void 4813 ixgbe_print_fw_version(if_ctx_t ctx) 4814 { 4815 struct ixgbe_softc *sc = iflib_get_softc(ctx); 4816 struct ixgbe_hw *hw = &sc->hw; 4817 device_t dev = sc->dev; 4818 struct sbuf *buf; 4819 int error = 0; 4820 4821 buf = sbuf_new_auto(); 4822 if (!buf) { 4823 device_printf(dev, "Could not allocate sbuf for output.\n"); 4824 return; 4825 } 4826 4827 ixgbe_sbuf_fw_version(hw, buf); 4828 4829 error = sbuf_finish(buf); 4830 if (error) 4831 device_printf(dev, "Error finishing sbuf: %d\n", error); 4832 else if (sbuf_len(buf)) 4833 device_printf(dev, "%s\n", sbuf_data(buf)); 4834 4835 sbuf_delete(buf); 4836 } /* ixgbe_print_fw_version */ 4837 4838 /************************************************************************ 4839 * ixgbe_sysctl_print_fw_version 4840 ************************************************************************/ 4841 static int 4842 ixgbe_sysctl_print_fw_version(SYSCTL_HANDLER_ARGS) 4843 { 4844 struct ixgbe_softc *sc = (struct ixgbe_softc *)arg1; 4845 struct ixgbe_hw *hw = &sc->hw; 4846 device_t dev = sc->dev; 4847 struct sbuf *buf; 4848 int error = 0; 4849 4850 buf = sbuf_new_for_sysctl(NULL, NULL, 128, req); 4851 if (!buf) { 4852 device_printf(dev, "Could not allocate sbuf for output.\n"); 4853 return (ENOMEM); 4854 } 4855 4856 ixgbe_sbuf_fw_version(hw, buf); 4857 4858 error = sbuf_finish(buf); 4859 if (error) 4860 device_printf(dev, "Error finishing sbuf: %d\n", error); 4861 4862 sbuf_delete(buf); 4863 4864 return (0); 4865 } /* ixgbe_sysctl_print_fw_version */ 4866