1 /****************************************************************************** 2 3 Copyright (c) 2001-2017, Intel Corporation 4 All rights reserved. 5 6 Redistribution and use in source and binary forms, with or without 7 modification, are permitted provided that the following conditions are met: 8 9 1. Redistributions of source code must retain the above copyright notice, 10 this list of conditions and the following disclaimer. 11 12 2. Redistributions in binary form must reproduce the above copyright 13 notice, this list of conditions and the following disclaimer in the 14 documentation and/or other materials provided with the distribution. 15 16 3. Neither the name of the Intel Corporation nor the names of its 17 contributors may be used to endorse or promote products derived from 18 this software without specific prior written permission. 19 20 THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 21 AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 22 IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 23 ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE 24 LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 25 CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 26 SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 27 INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 28 CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 29 ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 30 POSSIBILITY OF SUCH DAMAGE. 31 32 ******************************************************************************/ 33 /*$FreeBSD$*/ 34 35 #include "opt_inet.h" 36 #include "opt_inet6.h" 37 #include "opt_rss.h" 38 39 #include "ixgbe.h" 40 #include "ixgbe_sriov.h" 41 #include "ifdi_if.h" 42 43 #include <net/netmap.h> 44 #include <dev/netmap/netmap_kern.h> 45 46 /************************************************************************ 47 * Driver version 48 ************************************************************************/ 49 char ixgbe_driver_version[] = "4.0.1-k"; 50 51 /************************************************************************ 52 * PCI Device ID Table 53 * 54 * Used by probe to select devices to load on 55 * Last field stores an index into ixgbe_strings 56 * Last entry must be all 0s 57 * 58 * { Vendor ID, Device ID, SubVendor ID, SubDevice ID, String Index } 59 ************************************************************************/ 60 static pci_vendor_info_t ixgbe_vendor_info_array[] = 61 { 62 PVID(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82598AF_DUAL_PORT, "Intel(R) 82598EB AF (Dual Fiber)"), 63 PVID(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82598AF_SINGLE_PORT, "Intel(R) 82598EB AF (Fiber)"), 64 PVID(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82598EB_CX4, "Intel(R) 82598EB AT (CX4)"), 65 PVID(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82598AT, "Intel(R) 82598EB AT"), 66 PVID(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82598AT2, "Intel(R) 82598EB AT2"), 67 PVID(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82598, "Intel(R) 82598"), 68 PVID(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82598_DA_DUAL_PORT, "Intel(R) 82598EB AF DA (Dual Fiber)"), 69 PVID(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82598_CX4_DUAL_PORT, "Intel(R) 82598EB AT (Dual CX4)"), 70 PVID(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82598EB_XF_LR, "Intel(R) 82598EB AF (Dual Fiber LR)"), 71 PVID(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82598_SR_DUAL_PORT_EM, "Intel(R) 82598EB AF (Dual Fiber SR)"), 72 PVID(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82598EB_SFP_LOM, "Intel(R) 82598EB LOM"), 73 PVID(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_KX4, "Intel(R) X520 82599 (KX4)"), 74 PVID(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_KX4_MEZZ, "Intel(R) X520 82599 (KX4 Mezzanine)"), 75 PVID(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_SFP, "Intel(R) X520 82599ES (SFI/SFP+)"), 76 PVID(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_XAUI_LOM, "Intel(R) X520 82599 (XAUI/BX4)"), 77 PVID(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_CX4, "Intel(R) X520 82599 (Dual CX4)"), 78 PVID(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_T3_LOM, "Intel(R) X520-T 82599 LOM"), 79 PVID(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_COMBO_BACKPLANE, "Intel(R) X520 82599 (Combined Backplane)"), 80 PVID(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_BACKPLANE_FCOE, "Intel(R) X520 82599 (Backplane w/FCoE)"), 81 PVID(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_SFP_SF2, "Intel(R) X520 82599 (Dual SFP+)"), 82 PVID(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_SFP_FCOE, "Intel(R) X520 82599 (Dual SFP+ w/FCoE)"), 83 PVID(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599EN_SFP, "Intel(R) X520-1 82599EN (SFP+)"), 84 PVID(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_SFP_SF_QP, "Intel(R) X520-4 82599 (Quad SFP+)"), 85 PVID(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_QSFP_SF_QP, "Intel(R) X520-Q1 82599 (QSFP+)"), 86 PVID(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X540T, "Intel(R) X540-AT2"), 87 PVID(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X540T1, "Intel(R) X540-T1"), 88 PVID(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550T, "Intel(R) X550-T2"), 89 PVID(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550T1, "Intel(R) X550-T1"), 90 PVID(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_X_KR, "Intel(R) X552 (KR Backplane)"), 91 PVID(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_X_KX4, "Intel(R) X552 (KX4 Backplane)"), 92 PVID(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_X_10G_T, "Intel(R) X552/X557-AT (10GBASE-T)"), 93 PVID(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_X_1G_T, "Intel(R) X552 (1000BASE-T)"), 94 PVID(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_X_SFP, "Intel(R) X552 (SFP+)"), 95 PVID(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_A_KR, "Intel(R) X553 (KR Backplane)"), 96 PVID(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_A_KR_L, "Intel(R) X553 L (KR Backplane)"), 97 PVID(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_A_SFP, "Intel(R) X553 (SFP+)"), 98 PVID(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_A_SFP_N, "Intel(R) X553 N (SFP+)"), 99 PVID(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_A_SGMII, "Intel(R) X553 (1GbE SGMII)"), 100 PVID(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_A_SGMII_L, "Intel(R) X553 L (1GbE SGMII)"), 101 PVID(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_A_10G_T, "Intel(R) X553/X557-AT (10GBASE-T)"), 102 PVID(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_A_1G_T, "Intel(R) X553 (1GbE)"), 103 PVID(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_A_1G_T_L, "Intel(R) X553 L (1GbE)"), 104 PVID(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X540_BYPASS, "Intel(R) X540-T2 (Bypass)"), 105 PVID(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_BYPASS, "Intel(R) X520 82599 (Bypass)"), 106 /* required last entry */ 107 PVID_END 108 }; 109 110 static void *ixgbe_register(device_t); 111 static int ixgbe_if_attach_pre(if_ctx_t); 112 static int ixgbe_if_attach_post(if_ctx_t); 113 static int ixgbe_if_detach(if_ctx_t); 114 static int ixgbe_if_shutdown(if_ctx_t); 115 static int ixgbe_if_suspend(if_ctx_t); 116 static int ixgbe_if_resume(if_ctx_t); 117 118 static void ixgbe_if_stop(if_ctx_t); 119 void ixgbe_if_enable_intr(if_ctx_t); 120 static void ixgbe_if_disable_intr(if_ctx_t); 121 static void ixgbe_link_intr_enable(if_ctx_t); 122 static int ixgbe_if_rx_queue_intr_enable(if_ctx_t, uint16_t); 123 static void ixgbe_if_media_status(if_ctx_t, struct ifmediareq *); 124 static int ixgbe_if_media_change(if_ctx_t); 125 static int ixgbe_if_msix_intr_assign(if_ctx_t, int); 126 static int ixgbe_if_mtu_set(if_ctx_t, uint32_t); 127 static void ixgbe_if_crcstrip_set(if_ctx_t, int, int); 128 static void ixgbe_if_multi_set(if_ctx_t); 129 static int ixgbe_if_promisc_set(if_ctx_t, int); 130 static int ixgbe_if_tx_queues_alloc(if_ctx_t, caddr_t *, uint64_t *, int, int); 131 static int ixgbe_if_rx_queues_alloc(if_ctx_t, caddr_t *, uint64_t *, int, int); 132 static void ixgbe_if_queues_free(if_ctx_t); 133 static void ixgbe_if_timer(if_ctx_t, uint16_t); 134 static void ixgbe_if_update_admin_status(if_ctx_t); 135 static void ixgbe_if_vlan_register(if_ctx_t, u16); 136 static void ixgbe_if_vlan_unregister(if_ctx_t, u16); 137 static int ixgbe_if_i2c_req(if_ctx_t, struct ifi2creq *); 138 static bool ixgbe_if_needs_restart(if_ctx_t, enum iflib_restart_event); 139 int ixgbe_intr(void *); 140 141 /************************************************************************ 142 * Function prototypes 143 ************************************************************************/ 144 static uint64_t ixgbe_if_get_counter(if_ctx_t, ift_counter); 145 146 static void ixgbe_enable_queue(struct ixgbe_softc *, u32); 147 static void ixgbe_disable_queue(struct ixgbe_softc *, u32); 148 static void ixgbe_add_device_sysctls(if_ctx_t); 149 static int ixgbe_allocate_pci_resources(if_ctx_t); 150 static int ixgbe_setup_low_power_mode(if_ctx_t); 151 152 static void ixgbe_config_dmac(struct ixgbe_softc *); 153 static void ixgbe_configure_ivars(struct ixgbe_softc *); 154 static void ixgbe_set_ivar(struct ixgbe_softc *, u8, u8, s8); 155 static u8 *ixgbe_mc_array_itr(struct ixgbe_hw *, u8 **, u32 *); 156 static bool ixgbe_sfp_probe(if_ctx_t); 157 158 static void ixgbe_free_pci_resources(if_ctx_t); 159 160 static int ixgbe_msix_link(void *); 161 static int ixgbe_msix_que(void *); 162 static void ixgbe_initialize_rss_mapping(struct ixgbe_softc *); 163 static void ixgbe_initialize_receive_units(if_ctx_t); 164 static void ixgbe_initialize_transmit_units(if_ctx_t); 165 166 static int ixgbe_setup_interface(if_ctx_t); 167 static void ixgbe_init_device_features(struct ixgbe_softc *); 168 static void ixgbe_check_fan_failure(struct ixgbe_softc *, u32, bool); 169 static void ixgbe_sbuf_fw_version(struct ixgbe_hw *, struct sbuf *); 170 static void ixgbe_print_fw_version(if_ctx_t); 171 static void ixgbe_add_media_types(if_ctx_t); 172 static void ixgbe_update_stats_counters(struct ixgbe_softc *); 173 static void ixgbe_config_link(if_ctx_t); 174 static void ixgbe_get_slot_info(struct ixgbe_softc *); 175 static void ixgbe_check_wol_support(struct ixgbe_softc *); 176 static void ixgbe_enable_rx_drop(struct ixgbe_softc *); 177 static void ixgbe_disable_rx_drop(struct ixgbe_softc *); 178 179 static void ixgbe_add_hw_stats(struct ixgbe_softc *); 180 static int ixgbe_set_flowcntl(struct ixgbe_softc *, int); 181 static int ixgbe_set_advertise(struct ixgbe_softc *, int); 182 static int ixgbe_get_default_advertise(struct ixgbe_softc *); 183 static void ixgbe_setup_vlan_hw_support(if_ctx_t); 184 static void ixgbe_config_gpie(struct ixgbe_softc *); 185 static void ixgbe_config_delay_values(struct ixgbe_softc *); 186 187 /* Sysctl handlers */ 188 static int ixgbe_sysctl_flowcntl(SYSCTL_HANDLER_ARGS); 189 static int ixgbe_sysctl_advertise(SYSCTL_HANDLER_ARGS); 190 static int ixgbe_sysctl_interrupt_rate_handler(SYSCTL_HANDLER_ARGS); 191 static int ixgbe_sysctl_dmac(SYSCTL_HANDLER_ARGS); 192 static int ixgbe_sysctl_phy_temp(SYSCTL_HANDLER_ARGS); 193 static int ixgbe_sysctl_phy_overtemp_occurred(SYSCTL_HANDLER_ARGS); 194 static int ixgbe_sysctl_print_fw_version(SYSCTL_HANDLER_ARGS); 195 #ifdef IXGBE_DEBUG 196 static int ixgbe_sysctl_power_state(SYSCTL_HANDLER_ARGS); 197 static int ixgbe_sysctl_print_rss_config(SYSCTL_HANDLER_ARGS); 198 #endif 199 static int ixgbe_sysctl_rdh_handler(SYSCTL_HANDLER_ARGS); 200 static int ixgbe_sysctl_rdt_handler(SYSCTL_HANDLER_ARGS); 201 static int ixgbe_sysctl_tdt_handler(SYSCTL_HANDLER_ARGS); 202 static int ixgbe_sysctl_tdh_handler(SYSCTL_HANDLER_ARGS); 203 static int ixgbe_sysctl_eee_state(SYSCTL_HANDLER_ARGS); 204 static int ixgbe_sysctl_wol_enable(SYSCTL_HANDLER_ARGS); 205 static int ixgbe_sysctl_wufc(SYSCTL_HANDLER_ARGS); 206 207 /* Deferred interrupt tasklets */ 208 static void ixgbe_handle_msf(void *); 209 static void ixgbe_handle_mod(void *); 210 static void ixgbe_handle_phy(void *); 211 212 /************************************************************************ 213 * FreeBSD Device Interface Entry Points 214 ************************************************************************/ 215 static device_method_t ix_methods[] = { 216 /* Device interface */ 217 DEVMETHOD(device_register, ixgbe_register), 218 DEVMETHOD(device_probe, iflib_device_probe), 219 DEVMETHOD(device_attach, iflib_device_attach), 220 DEVMETHOD(device_detach, iflib_device_detach), 221 DEVMETHOD(device_shutdown, iflib_device_shutdown), 222 DEVMETHOD(device_suspend, iflib_device_suspend), 223 DEVMETHOD(device_resume, iflib_device_resume), 224 #ifdef PCI_IOV 225 DEVMETHOD(pci_iov_init, iflib_device_iov_init), 226 DEVMETHOD(pci_iov_uninit, iflib_device_iov_uninit), 227 DEVMETHOD(pci_iov_add_vf, iflib_device_iov_add_vf), 228 #endif /* PCI_IOV */ 229 DEVMETHOD_END 230 }; 231 232 static driver_t ix_driver = { 233 "ix", ix_methods, sizeof(struct ixgbe_softc), 234 }; 235 236 DRIVER_MODULE(ix, pci, ix_driver, 0, 0); 237 IFLIB_PNP_INFO(pci, ix_driver, ixgbe_vendor_info_array); 238 MODULE_DEPEND(ix, pci, 1, 1, 1); 239 MODULE_DEPEND(ix, ether, 1, 1, 1); 240 MODULE_DEPEND(ix, iflib, 1, 1, 1); 241 242 static device_method_t ixgbe_if_methods[] = { 243 DEVMETHOD(ifdi_attach_pre, ixgbe_if_attach_pre), 244 DEVMETHOD(ifdi_attach_post, ixgbe_if_attach_post), 245 DEVMETHOD(ifdi_detach, ixgbe_if_detach), 246 DEVMETHOD(ifdi_shutdown, ixgbe_if_shutdown), 247 DEVMETHOD(ifdi_suspend, ixgbe_if_suspend), 248 DEVMETHOD(ifdi_resume, ixgbe_if_resume), 249 DEVMETHOD(ifdi_init, ixgbe_if_init), 250 DEVMETHOD(ifdi_stop, ixgbe_if_stop), 251 DEVMETHOD(ifdi_msix_intr_assign, ixgbe_if_msix_intr_assign), 252 DEVMETHOD(ifdi_intr_enable, ixgbe_if_enable_intr), 253 DEVMETHOD(ifdi_intr_disable, ixgbe_if_disable_intr), 254 DEVMETHOD(ifdi_link_intr_enable, ixgbe_link_intr_enable), 255 DEVMETHOD(ifdi_tx_queue_intr_enable, ixgbe_if_rx_queue_intr_enable), 256 DEVMETHOD(ifdi_rx_queue_intr_enable, ixgbe_if_rx_queue_intr_enable), 257 DEVMETHOD(ifdi_tx_queues_alloc, ixgbe_if_tx_queues_alloc), 258 DEVMETHOD(ifdi_rx_queues_alloc, ixgbe_if_rx_queues_alloc), 259 DEVMETHOD(ifdi_queues_free, ixgbe_if_queues_free), 260 DEVMETHOD(ifdi_update_admin_status, ixgbe_if_update_admin_status), 261 DEVMETHOD(ifdi_multi_set, ixgbe_if_multi_set), 262 DEVMETHOD(ifdi_mtu_set, ixgbe_if_mtu_set), 263 DEVMETHOD(ifdi_crcstrip_set, ixgbe_if_crcstrip_set), 264 DEVMETHOD(ifdi_media_status, ixgbe_if_media_status), 265 DEVMETHOD(ifdi_media_change, ixgbe_if_media_change), 266 DEVMETHOD(ifdi_promisc_set, ixgbe_if_promisc_set), 267 DEVMETHOD(ifdi_timer, ixgbe_if_timer), 268 DEVMETHOD(ifdi_vlan_register, ixgbe_if_vlan_register), 269 DEVMETHOD(ifdi_vlan_unregister, ixgbe_if_vlan_unregister), 270 DEVMETHOD(ifdi_get_counter, ixgbe_if_get_counter), 271 DEVMETHOD(ifdi_i2c_req, ixgbe_if_i2c_req), 272 DEVMETHOD(ifdi_needs_restart, ixgbe_if_needs_restart), 273 #ifdef PCI_IOV 274 DEVMETHOD(ifdi_iov_init, ixgbe_if_iov_init), 275 DEVMETHOD(ifdi_iov_uninit, ixgbe_if_iov_uninit), 276 DEVMETHOD(ifdi_iov_vf_add, ixgbe_if_iov_vf_add), 277 #endif /* PCI_IOV */ 278 DEVMETHOD_END 279 }; 280 281 /* 282 * TUNEABLE PARAMETERS: 283 */ 284 285 static SYSCTL_NODE(_hw, OID_AUTO, ix, CTLFLAG_RD | CTLFLAG_MPSAFE, 0, 286 "IXGBE driver parameters"); 287 static driver_t ixgbe_if_driver = { 288 "ixgbe_if", ixgbe_if_methods, sizeof(struct ixgbe_softc) 289 }; 290 291 static int ixgbe_max_interrupt_rate = (4000000 / IXGBE_LOW_LATENCY); 292 SYSCTL_INT(_hw_ix, OID_AUTO, max_interrupt_rate, CTLFLAG_RDTUN, 293 &ixgbe_max_interrupt_rate, 0, "Maximum interrupts per second"); 294 295 /* Flow control setting, default to full */ 296 static int ixgbe_flow_control = ixgbe_fc_full; 297 SYSCTL_INT(_hw_ix, OID_AUTO, flow_control, CTLFLAG_RDTUN, 298 &ixgbe_flow_control, 0, "Default flow control used for all adapters"); 299 300 /* Advertise Speed, default to 0 (auto) */ 301 static int ixgbe_advertise_speed = 0; 302 SYSCTL_INT(_hw_ix, OID_AUTO, advertise_speed, CTLFLAG_RDTUN, 303 &ixgbe_advertise_speed, 0, "Default advertised speed for all adapters"); 304 305 /* 306 * Smart speed setting, default to on 307 * this only works as a compile option 308 * right now as its during attach, set 309 * this to 'ixgbe_smart_speed_off' to 310 * disable. 311 */ 312 static int ixgbe_smart_speed = ixgbe_smart_speed_on; 313 314 /* 315 * MSI-X should be the default for best performance, 316 * but this allows it to be forced off for testing. 317 */ 318 static int ixgbe_enable_msix = 1; 319 SYSCTL_INT(_hw_ix, OID_AUTO, enable_msix, CTLFLAG_RDTUN, &ixgbe_enable_msix, 0, 320 "Enable MSI-X interrupts"); 321 322 /* 323 * Defining this on will allow the use 324 * of unsupported SFP+ modules, note that 325 * doing so you are on your own :) 326 */ 327 static int allow_unsupported_sfp = false; 328 SYSCTL_INT(_hw_ix, OID_AUTO, unsupported_sfp, CTLFLAG_RDTUN, 329 &allow_unsupported_sfp, 0, 330 "Allow unsupported SFP modules...use at your own risk"); 331 332 /* 333 * Not sure if Flow Director is fully baked, 334 * so we'll default to turning it off. 335 */ 336 static int ixgbe_enable_fdir = 0; 337 SYSCTL_INT(_hw_ix, OID_AUTO, enable_fdir, CTLFLAG_RDTUN, &ixgbe_enable_fdir, 0, 338 "Enable Flow Director"); 339 340 /* Receive-Side Scaling */ 341 static int ixgbe_enable_rss = 1; 342 SYSCTL_INT(_hw_ix, OID_AUTO, enable_rss, CTLFLAG_RDTUN, &ixgbe_enable_rss, 0, 343 "Enable Receive-Side Scaling (RSS)"); 344 345 /* 346 * AIM: Adaptive Interrupt Moderation 347 * which means that the interrupt rate 348 * is varied over time based on the 349 * traffic for that interrupt vector 350 */ 351 static int ixgbe_enable_aim = false; 352 SYSCTL_INT(_hw_ix, OID_AUTO, enable_aim, CTLFLAG_RWTUN, &ixgbe_enable_aim, 0, 353 "Enable adaptive interrupt moderation"); 354 355 #if 0 356 /* Keep running tab on them for sanity check */ 357 static int ixgbe_total_ports; 358 #endif 359 360 MALLOC_DEFINE(M_IXGBE, "ix", "ix driver allocations"); 361 362 /* 363 * For Flow Director: this is the number of TX packets we sample 364 * for the filter pool, this means every 20th packet will be probed. 365 * 366 * This feature can be disabled by setting this to 0. 367 */ 368 static int atr_sample_rate = 20; 369 370 extern struct if_txrx ixgbe_txrx; 371 372 static struct if_shared_ctx ixgbe_sctx_init = { 373 .isc_magic = IFLIB_MAGIC, 374 .isc_q_align = PAGE_SIZE,/* max(DBA_ALIGN, PAGE_SIZE) */ 375 .isc_tx_maxsize = IXGBE_TSO_SIZE + sizeof(struct ether_vlan_header), 376 .isc_tx_maxsegsize = PAGE_SIZE, 377 .isc_tso_maxsize = IXGBE_TSO_SIZE + sizeof(struct ether_vlan_header), 378 .isc_tso_maxsegsize = PAGE_SIZE, 379 .isc_rx_maxsize = PAGE_SIZE*4, 380 .isc_rx_nsegments = 1, 381 .isc_rx_maxsegsize = PAGE_SIZE*4, 382 .isc_nfl = 1, 383 .isc_ntxqs = 1, 384 .isc_nrxqs = 1, 385 386 .isc_admin_intrcnt = 1, 387 .isc_vendor_info = ixgbe_vendor_info_array, 388 .isc_driver_version = ixgbe_driver_version, 389 .isc_driver = &ixgbe_if_driver, 390 .isc_flags = IFLIB_TSO_INIT_IP, 391 392 .isc_nrxd_min = {MIN_RXD}, 393 .isc_ntxd_min = {MIN_TXD}, 394 .isc_nrxd_max = {MAX_RXD}, 395 .isc_ntxd_max = {MAX_TXD}, 396 .isc_nrxd_default = {DEFAULT_RXD}, 397 .isc_ntxd_default = {DEFAULT_TXD}, 398 }; 399 400 /************************************************************************ 401 * ixgbe_if_tx_queues_alloc 402 ************************************************************************/ 403 static int 404 ixgbe_if_tx_queues_alloc(if_ctx_t ctx, caddr_t *vaddrs, uint64_t *paddrs, 405 int ntxqs, int ntxqsets) 406 { 407 struct ixgbe_softc *sc = iflib_get_softc(ctx); 408 if_softc_ctx_t scctx = sc->shared; 409 struct ix_tx_queue *que; 410 int i, j, error; 411 412 MPASS(sc->num_tx_queues > 0); 413 MPASS(sc->num_tx_queues == ntxqsets); 414 MPASS(ntxqs == 1); 415 416 /* Allocate queue structure memory */ 417 sc->tx_queues = 418 (struct ix_tx_queue *)malloc(sizeof(struct ix_tx_queue) * ntxqsets, 419 M_IXGBE, M_NOWAIT | M_ZERO); 420 if (!sc->tx_queues) { 421 device_printf(iflib_get_dev(ctx), 422 "Unable to allocate TX ring memory\n"); 423 return (ENOMEM); 424 } 425 426 for (i = 0, que = sc->tx_queues; i < ntxqsets; i++, que++) { 427 struct tx_ring *txr = &que->txr; 428 429 /* In case SR-IOV is enabled, align the index properly */ 430 txr->me = ixgbe_vf_que_index(sc->iov_mode, sc->pool, 431 i); 432 433 txr->sc = que->sc = sc; 434 435 /* Allocate report status array */ 436 txr->tx_rsq = (qidx_t *)malloc(sizeof(qidx_t) * scctx->isc_ntxd[0], M_IXGBE, M_NOWAIT | M_ZERO); 437 if (txr->tx_rsq == NULL) { 438 error = ENOMEM; 439 goto fail; 440 } 441 for (j = 0; j < scctx->isc_ntxd[0]; j++) 442 txr->tx_rsq[j] = QIDX_INVALID; 443 /* get the virtual and physical address of the hardware queues */ 444 txr->tail = IXGBE_TDT(txr->me); 445 txr->tx_base = (union ixgbe_adv_tx_desc *)vaddrs[i]; 446 txr->tx_paddr = paddrs[i]; 447 448 txr->bytes = 0; 449 txr->total_packets = 0; 450 451 /* Set the rate at which we sample packets */ 452 if (sc->feat_en & IXGBE_FEATURE_FDIR) 453 txr->atr_sample = atr_sample_rate; 454 455 } 456 457 device_printf(iflib_get_dev(ctx), "allocated for %d queues\n", 458 sc->num_tx_queues); 459 460 return (0); 461 462 fail: 463 ixgbe_if_queues_free(ctx); 464 465 return (error); 466 } /* ixgbe_if_tx_queues_alloc */ 467 468 /************************************************************************ 469 * ixgbe_if_rx_queues_alloc 470 ************************************************************************/ 471 static int 472 ixgbe_if_rx_queues_alloc(if_ctx_t ctx, caddr_t *vaddrs, uint64_t *paddrs, 473 int nrxqs, int nrxqsets) 474 { 475 struct ixgbe_softc *sc = iflib_get_softc(ctx); 476 struct ix_rx_queue *que; 477 int i; 478 479 MPASS(sc->num_rx_queues > 0); 480 MPASS(sc->num_rx_queues == nrxqsets); 481 MPASS(nrxqs == 1); 482 483 /* Allocate queue structure memory */ 484 sc->rx_queues = 485 (struct ix_rx_queue *)malloc(sizeof(struct ix_rx_queue)*nrxqsets, 486 M_IXGBE, M_NOWAIT | M_ZERO); 487 if (!sc->rx_queues) { 488 device_printf(iflib_get_dev(ctx), 489 "Unable to allocate TX ring memory\n"); 490 return (ENOMEM); 491 } 492 493 for (i = 0, que = sc->rx_queues; i < nrxqsets; i++, que++) { 494 struct rx_ring *rxr = &que->rxr; 495 496 /* In case SR-IOV is enabled, align the index properly */ 497 rxr->me = ixgbe_vf_que_index(sc->iov_mode, sc->pool, 498 i); 499 500 rxr->sc = que->sc = sc; 501 502 /* get the virtual and physical address of the hw queues */ 503 rxr->tail = IXGBE_RDT(rxr->me); 504 rxr->rx_base = (union ixgbe_adv_rx_desc *)vaddrs[i]; 505 rxr->rx_paddr = paddrs[i]; 506 rxr->bytes = 0; 507 rxr->que = que; 508 } 509 510 device_printf(iflib_get_dev(ctx), "allocated for %d rx queues\n", 511 sc->num_rx_queues); 512 513 return (0); 514 } /* ixgbe_if_rx_queues_alloc */ 515 516 /************************************************************************ 517 * ixgbe_if_queues_free 518 ************************************************************************/ 519 static void 520 ixgbe_if_queues_free(if_ctx_t ctx) 521 { 522 struct ixgbe_softc *sc = iflib_get_softc(ctx); 523 struct ix_tx_queue *tx_que = sc->tx_queues; 524 struct ix_rx_queue *rx_que = sc->rx_queues; 525 int i; 526 527 if (tx_que != NULL) { 528 for (i = 0; i < sc->num_tx_queues; i++, tx_que++) { 529 struct tx_ring *txr = &tx_que->txr; 530 if (txr->tx_rsq == NULL) 531 break; 532 533 free(txr->tx_rsq, M_IXGBE); 534 txr->tx_rsq = NULL; 535 } 536 537 free(sc->tx_queues, M_IXGBE); 538 sc->tx_queues = NULL; 539 } 540 if (rx_que != NULL) { 541 free(sc->rx_queues, M_IXGBE); 542 sc->rx_queues = NULL; 543 } 544 } /* ixgbe_if_queues_free */ 545 546 /************************************************************************ 547 * ixgbe_initialize_rss_mapping 548 ************************************************************************/ 549 static void 550 ixgbe_initialize_rss_mapping(struct ixgbe_softc *sc) 551 { 552 struct ixgbe_hw *hw = &sc->hw; 553 u32 reta = 0, mrqc, rss_key[10]; 554 int queue_id, table_size, index_mult; 555 int i, j; 556 u32 rss_hash_config; 557 558 if (sc->feat_en & IXGBE_FEATURE_RSS) { 559 /* Fetch the configured RSS key */ 560 rss_getkey((uint8_t *)&rss_key); 561 } else { 562 /* set up random bits */ 563 arc4rand(&rss_key, sizeof(rss_key), 0); 564 } 565 566 /* Set multiplier for RETA setup and table size based on MAC */ 567 index_mult = 0x1; 568 table_size = 128; 569 switch (sc->hw.mac.type) { 570 case ixgbe_mac_82598EB: 571 index_mult = 0x11; 572 break; 573 case ixgbe_mac_X550: 574 case ixgbe_mac_X550EM_x: 575 case ixgbe_mac_X550EM_a: 576 table_size = 512; 577 break; 578 default: 579 break; 580 } 581 582 /* Set up the redirection table */ 583 for (i = 0, j = 0; i < table_size; i++, j++) { 584 if (j == sc->num_rx_queues) 585 j = 0; 586 587 if (sc->feat_en & IXGBE_FEATURE_RSS) { 588 /* 589 * Fetch the RSS bucket id for the given indirection 590 * entry. Cap it at the number of configured buckets 591 * (which is num_rx_queues.) 592 */ 593 queue_id = rss_get_indirection_to_bucket(i); 594 queue_id = queue_id % sc->num_rx_queues; 595 } else 596 queue_id = (j * index_mult); 597 598 /* 599 * The low 8 bits are for hash value (n+0); 600 * The next 8 bits are for hash value (n+1), etc. 601 */ 602 reta = reta >> 8; 603 reta = reta | (((uint32_t)queue_id) << 24); 604 if ((i & 3) == 3) { 605 if (i < 128) 606 IXGBE_WRITE_REG(hw, IXGBE_RETA(i >> 2), reta); 607 else 608 IXGBE_WRITE_REG(hw, IXGBE_ERETA((i >> 2) - 32), 609 reta); 610 reta = 0; 611 } 612 } 613 614 /* Now fill our hash function seeds */ 615 for (i = 0; i < 10; i++) 616 IXGBE_WRITE_REG(hw, IXGBE_RSSRK(i), rss_key[i]); 617 618 /* Perform hash on these packet types */ 619 if (sc->feat_en & IXGBE_FEATURE_RSS) 620 rss_hash_config = rss_gethashconfig(); 621 else { 622 /* 623 * Disable UDP - IP fragments aren't currently being handled 624 * and so we end up with a mix of 2-tuple and 4-tuple 625 * traffic. 626 */ 627 rss_hash_config = RSS_HASHTYPE_RSS_IPV4 628 | RSS_HASHTYPE_RSS_TCP_IPV4 629 | RSS_HASHTYPE_RSS_IPV6 630 | RSS_HASHTYPE_RSS_TCP_IPV6 631 | RSS_HASHTYPE_RSS_IPV6_EX 632 | RSS_HASHTYPE_RSS_TCP_IPV6_EX; 633 } 634 635 mrqc = IXGBE_MRQC_RSSEN; 636 if (rss_hash_config & RSS_HASHTYPE_RSS_IPV4) 637 mrqc |= IXGBE_MRQC_RSS_FIELD_IPV4; 638 if (rss_hash_config & RSS_HASHTYPE_RSS_TCP_IPV4) 639 mrqc |= IXGBE_MRQC_RSS_FIELD_IPV4_TCP; 640 if (rss_hash_config & RSS_HASHTYPE_RSS_IPV6) 641 mrqc |= IXGBE_MRQC_RSS_FIELD_IPV6; 642 if (rss_hash_config & RSS_HASHTYPE_RSS_TCP_IPV6) 643 mrqc |= IXGBE_MRQC_RSS_FIELD_IPV6_TCP; 644 if (rss_hash_config & RSS_HASHTYPE_RSS_IPV6_EX) 645 mrqc |= IXGBE_MRQC_RSS_FIELD_IPV6_EX; 646 if (rss_hash_config & RSS_HASHTYPE_RSS_TCP_IPV6_EX) 647 mrqc |= IXGBE_MRQC_RSS_FIELD_IPV6_EX_TCP; 648 if (rss_hash_config & RSS_HASHTYPE_RSS_UDP_IPV4) 649 mrqc |= IXGBE_MRQC_RSS_FIELD_IPV4_UDP; 650 if (rss_hash_config & RSS_HASHTYPE_RSS_UDP_IPV6) 651 mrqc |= IXGBE_MRQC_RSS_FIELD_IPV6_UDP; 652 if (rss_hash_config & RSS_HASHTYPE_RSS_UDP_IPV6_EX) 653 mrqc |= IXGBE_MRQC_RSS_FIELD_IPV6_EX_UDP; 654 mrqc |= ixgbe_get_mrqc(sc->iov_mode); 655 IXGBE_WRITE_REG(hw, IXGBE_MRQC, mrqc); 656 } /* ixgbe_initialize_rss_mapping */ 657 658 /************************************************************************ 659 * ixgbe_initialize_receive_units - Setup receive registers and features. 660 ************************************************************************/ 661 #define BSIZEPKT_ROUNDUP ((1<<IXGBE_SRRCTL_BSIZEPKT_SHIFT)-1) 662 663 static void 664 ixgbe_initialize_receive_units(if_ctx_t ctx) 665 { 666 struct ixgbe_softc *sc = iflib_get_softc(ctx); 667 if_softc_ctx_t scctx = sc->shared; 668 struct ixgbe_hw *hw = &sc->hw; 669 if_t ifp = iflib_get_ifp(ctx); 670 struct ix_rx_queue *que; 671 int i, j; 672 u32 bufsz, fctrl, srrctl, rxcsum; 673 u32 hlreg; 674 675 /* 676 * Make sure receives are disabled while 677 * setting up the descriptor ring 678 */ 679 ixgbe_disable_rx(hw); 680 681 /* Enable broadcasts */ 682 fctrl = IXGBE_READ_REG(hw, IXGBE_FCTRL); 683 fctrl |= IXGBE_FCTRL_BAM; 684 if (sc->hw.mac.type == ixgbe_mac_82598EB) { 685 fctrl |= IXGBE_FCTRL_DPF; 686 fctrl |= IXGBE_FCTRL_PMCF; 687 } 688 IXGBE_WRITE_REG(hw, IXGBE_FCTRL, fctrl); 689 690 /* Set for Jumbo Frames? */ 691 hlreg = IXGBE_READ_REG(hw, IXGBE_HLREG0); 692 if (if_getmtu(ifp) > ETHERMTU) 693 hlreg |= IXGBE_HLREG0_JUMBOEN; 694 else 695 hlreg &= ~IXGBE_HLREG0_JUMBOEN; 696 IXGBE_WRITE_REG(hw, IXGBE_HLREG0, hlreg); 697 698 bufsz = (sc->rx_mbuf_sz + BSIZEPKT_ROUNDUP) >> 699 IXGBE_SRRCTL_BSIZEPKT_SHIFT; 700 701 /* Setup the Base and Length of the Rx Descriptor Ring */ 702 for (i = 0, que = sc->rx_queues; i < sc->num_rx_queues; i++, que++) { 703 struct rx_ring *rxr = &que->rxr; 704 u64 rdba = rxr->rx_paddr; 705 706 j = rxr->me; 707 708 /* Setup the Base and Length of the Rx Descriptor Ring */ 709 IXGBE_WRITE_REG(hw, IXGBE_RDBAL(j), 710 (rdba & 0x00000000ffffffffULL)); 711 IXGBE_WRITE_REG(hw, IXGBE_RDBAH(j), (rdba >> 32)); 712 IXGBE_WRITE_REG(hw, IXGBE_RDLEN(j), 713 scctx->isc_nrxd[0] * sizeof(union ixgbe_adv_rx_desc)); 714 715 /* Set up the SRRCTL register */ 716 srrctl = IXGBE_READ_REG(hw, IXGBE_SRRCTL(j)); 717 srrctl &= ~IXGBE_SRRCTL_BSIZEHDR_MASK; 718 srrctl &= ~IXGBE_SRRCTL_BSIZEPKT_MASK; 719 srrctl |= bufsz; 720 srrctl |= IXGBE_SRRCTL_DESCTYPE_ADV_ONEBUF; 721 722 /* 723 * Set DROP_EN iff we have no flow control and >1 queue. 724 * Note that srrctl was cleared shortly before during reset, 725 * so we do not need to clear the bit, but do it just in case 726 * this code is moved elsewhere. 727 */ 728 if (sc->num_rx_queues > 1 && 729 sc->hw.fc.requested_mode == ixgbe_fc_none) { 730 srrctl |= IXGBE_SRRCTL_DROP_EN; 731 } else { 732 srrctl &= ~IXGBE_SRRCTL_DROP_EN; 733 } 734 735 IXGBE_WRITE_REG(hw, IXGBE_SRRCTL(j), srrctl); 736 737 /* Setup the HW Rx Head and Tail Descriptor Pointers */ 738 IXGBE_WRITE_REG(hw, IXGBE_RDH(j), 0); 739 IXGBE_WRITE_REG(hw, IXGBE_RDT(j), 0); 740 741 /* Set the driver rx tail address */ 742 rxr->tail = IXGBE_RDT(rxr->me); 743 } 744 745 if (sc->hw.mac.type != ixgbe_mac_82598EB) { 746 u32 psrtype = IXGBE_PSRTYPE_TCPHDR 747 | IXGBE_PSRTYPE_UDPHDR 748 | IXGBE_PSRTYPE_IPV4HDR 749 | IXGBE_PSRTYPE_IPV6HDR; 750 IXGBE_WRITE_REG(hw, IXGBE_PSRTYPE(0), psrtype); 751 } 752 753 rxcsum = IXGBE_READ_REG(hw, IXGBE_RXCSUM); 754 755 ixgbe_initialize_rss_mapping(sc); 756 757 if (sc->num_rx_queues > 1) { 758 /* RSS and RX IPP Checksum are mutually exclusive */ 759 rxcsum |= IXGBE_RXCSUM_PCSD; 760 } 761 762 if (if_getcapenable(ifp) & IFCAP_RXCSUM) 763 rxcsum |= IXGBE_RXCSUM_PCSD; 764 765 /* This is useful for calculating UDP/IP fragment checksums */ 766 if (!(rxcsum & IXGBE_RXCSUM_PCSD)) 767 rxcsum |= IXGBE_RXCSUM_IPPCSE; 768 769 IXGBE_WRITE_REG(hw, IXGBE_RXCSUM, rxcsum); 770 771 } /* ixgbe_initialize_receive_units */ 772 773 /************************************************************************ 774 * ixgbe_initialize_transmit_units - Enable transmit units. 775 ************************************************************************/ 776 static void 777 ixgbe_initialize_transmit_units(if_ctx_t ctx) 778 { 779 struct ixgbe_softc *sc = iflib_get_softc(ctx); 780 struct ixgbe_hw *hw = &sc->hw; 781 if_softc_ctx_t scctx = sc->shared; 782 struct ix_tx_queue *que; 783 int i; 784 785 /* Setup the Base and Length of the Tx Descriptor Ring */ 786 for (i = 0, que = sc->tx_queues; i < sc->num_tx_queues; 787 i++, que++) { 788 struct tx_ring *txr = &que->txr; 789 u64 tdba = txr->tx_paddr; 790 u32 txctrl = 0; 791 int j = txr->me; 792 793 IXGBE_WRITE_REG(hw, IXGBE_TDBAL(j), 794 (tdba & 0x00000000ffffffffULL)); 795 IXGBE_WRITE_REG(hw, IXGBE_TDBAH(j), (tdba >> 32)); 796 IXGBE_WRITE_REG(hw, IXGBE_TDLEN(j), 797 scctx->isc_ntxd[0] * sizeof(union ixgbe_adv_tx_desc)); 798 799 /* Setup the HW Tx Head and Tail descriptor pointers */ 800 IXGBE_WRITE_REG(hw, IXGBE_TDH(j), 0); 801 IXGBE_WRITE_REG(hw, IXGBE_TDT(j), 0); 802 803 /* Cache the tail address */ 804 txr->tail = IXGBE_TDT(txr->me); 805 806 txr->tx_rs_cidx = txr->tx_rs_pidx; 807 txr->tx_cidx_processed = scctx->isc_ntxd[0] - 1; 808 for (int k = 0; k < scctx->isc_ntxd[0]; k++) 809 txr->tx_rsq[k] = QIDX_INVALID; 810 811 /* Disable Head Writeback */ 812 /* 813 * Note: for X550 series devices, these registers are actually 814 * prefixed with TPH_ isntead of DCA_, but the addresses and 815 * fields remain the same. 816 */ 817 switch (hw->mac.type) { 818 case ixgbe_mac_82598EB: 819 txctrl = IXGBE_READ_REG(hw, IXGBE_DCA_TXCTRL(j)); 820 break; 821 default: 822 txctrl = IXGBE_READ_REG(hw, IXGBE_DCA_TXCTRL_82599(j)); 823 break; 824 } 825 txctrl &= ~IXGBE_DCA_TXCTRL_DESC_WRO_EN; 826 switch (hw->mac.type) { 827 case ixgbe_mac_82598EB: 828 IXGBE_WRITE_REG(hw, IXGBE_DCA_TXCTRL(j), txctrl); 829 break; 830 default: 831 IXGBE_WRITE_REG(hw, IXGBE_DCA_TXCTRL_82599(j), txctrl); 832 break; 833 } 834 835 } 836 837 if (hw->mac.type != ixgbe_mac_82598EB) { 838 u32 dmatxctl, rttdcs; 839 840 dmatxctl = IXGBE_READ_REG(hw, IXGBE_DMATXCTL); 841 dmatxctl |= IXGBE_DMATXCTL_TE; 842 IXGBE_WRITE_REG(hw, IXGBE_DMATXCTL, dmatxctl); 843 /* Disable arbiter to set MTQC */ 844 rttdcs = IXGBE_READ_REG(hw, IXGBE_RTTDCS); 845 rttdcs |= IXGBE_RTTDCS_ARBDIS; 846 IXGBE_WRITE_REG(hw, IXGBE_RTTDCS, rttdcs); 847 IXGBE_WRITE_REG(hw, IXGBE_MTQC, 848 ixgbe_get_mtqc(sc->iov_mode)); 849 rttdcs &= ~IXGBE_RTTDCS_ARBDIS; 850 IXGBE_WRITE_REG(hw, IXGBE_RTTDCS, rttdcs); 851 } 852 853 } /* ixgbe_initialize_transmit_units */ 854 855 /************************************************************************ 856 * ixgbe_register 857 ************************************************************************/ 858 static void * 859 ixgbe_register(device_t dev) 860 { 861 return (&ixgbe_sctx_init); 862 } /* ixgbe_register */ 863 864 /************************************************************************ 865 * ixgbe_if_attach_pre - Device initialization routine, part 1 866 * 867 * Called when the driver is being loaded. 868 * Identifies the type of hardware, initializes the hardware, 869 * and initializes iflib structures. 870 * 871 * return 0 on success, positive on failure 872 ************************************************************************/ 873 static int 874 ixgbe_if_attach_pre(if_ctx_t ctx) 875 { 876 struct ixgbe_softc *sc; 877 device_t dev; 878 if_softc_ctx_t scctx; 879 struct ixgbe_hw *hw; 880 int error = 0; 881 u32 ctrl_ext; 882 883 INIT_DEBUGOUT("ixgbe_attach: begin"); 884 885 /* Allocate, clear, and link in our adapter structure */ 886 dev = iflib_get_dev(ctx); 887 sc = iflib_get_softc(ctx); 888 sc->hw.back = sc; 889 sc->ctx = ctx; 890 sc->dev = dev; 891 scctx = sc->shared = iflib_get_softc_ctx(ctx); 892 sc->media = iflib_get_media(ctx); 893 hw = &sc->hw; 894 895 /* Determine hardware revision */ 896 hw->vendor_id = pci_get_vendor(dev); 897 hw->device_id = pci_get_device(dev); 898 hw->revision_id = pci_get_revid(dev); 899 hw->subsystem_vendor_id = pci_get_subvendor(dev); 900 hw->subsystem_device_id = pci_get_subdevice(dev); 901 902 /* Do base PCI setup - map BAR0 */ 903 if (ixgbe_allocate_pci_resources(ctx)) { 904 device_printf(dev, "Allocation of PCI resources failed\n"); 905 return (ENXIO); 906 } 907 908 /* let hardware know driver is loaded */ 909 ctrl_ext = IXGBE_READ_REG(hw, IXGBE_CTRL_EXT); 910 ctrl_ext |= IXGBE_CTRL_EXT_DRV_LOAD; 911 IXGBE_WRITE_REG(hw, IXGBE_CTRL_EXT, ctrl_ext); 912 913 /* 914 * Initialize the shared code 915 */ 916 if (ixgbe_init_shared_code(hw) != 0) { 917 device_printf(dev, "Unable to initialize the shared code\n"); 918 error = ENXIO; 919 goto err_pci; 920 } 921 922 if (hw->mbx.ops.init_params) 923 hw->mbx.ops.init_params(hw); 924 925 hw->allow_unsupported_sfp = allow_unsupported_sfp; 926 927 if (hw->mac.type != ixgbe_mac_82598EB) 928 hw->phy.smart_speed = ixgbe_smart_speed; 929 930 ixgbe_init_device_features(sc); 931 932 /* Enable WoL (if supported) */ 933 ixgbe_check_wol_support(sc); 934 935 /* Verify adapter fan is still functional (if applicable) */ 936 if (sc->feat_en & IXGBE_FEATURE_FAN_FAIL) { 937 u32 esdp = IXGBE_READ_REG(hw, IXGBE_ESDP); 938 ixgbe_check_fan_failure(sc, esdp, false); 939 } 940 941 /* Ensure SW/FW semaphore is free */ 942 ixgbe_init_swfw_semaphore(hw); 943 944 /* Set an initial default flow control value */ 945 hw->fc.requested_mode = ixgbe_flow_control; 946 947 hw->phy.reset_if_overtemp = true; 948 error = ixgbe_reset_hw(hw); 949 hw->phy.reset_if_overtemp = false; 950 if (error == IXGBE_ERR_SFP_NOT_PRESENT) { 951 /* 952 * No optics in this port, set up 953 * so the timer routine will probe 954 * for later insertion. 955 */ 956 sc->sfp_probe = true; 957 error = 0; 958 } else if (error == IXGBE_ERR_SFP_NOT_SUPPORTED) { 959 device_printf(dev, "Unsupported SFP+ module detected!\n"); 960 error = EIO; 961 goto err_pci; 962 } else if (error) { 963 device_printf(dev, "Hardware initialization failed\n"); 964 error = EIO; 965 goto err_pci; 966 } 967 968 /* Make sure we have a good EEPROM before we read from it */ 969 if (ixgbe_validate_eeprom_checksum(&sc->hw, NULL) < 0) { 970 device_printf(dev, "The EEPROM Checksum Is Not Valid\n"); 971 error = EIO; 972 goto err_pci; 973 } 974 975 error = ixgbe_start_hw(hw); 976 switch (error) { 977 case IXGBE_ERR_EEPROM_VERSION: 978 device_printf(dev, "This device is a pre-production adapter/LOM. Please be aware there may be issues associated with your hardware.\nIf you are experiencing problems please contact your Intel or hardware representative who provided you with this hardware.\n"); 979 break; 980 case IXGBE_ERR_SFP_NOT_SUPPORTED: 981 device_printf(dev, "Unsupported SFP+ Module\n"); 982 error = EIO; 983 goto err_pci; 984 case IXGBE_ERR_SFP_NOT_PRESENT: 985 device_printf(dev, "No SFP+ Module found\n"); 986 /* falls thru */ 987 default: 988 break; 989 } 990 991 /* Most of the iflib initialization... */ 992 993 iflib_set_mac(ctx, hw->mac.addr); 994 switch (sc->hw.mac.type) { 995 case ixgbe_mac_X550: 996 case ixgbe_mac_X550EM_x: 997 case ixgbe_mac_X550EM_a: 998 scctx->isc_rss_table_size = 512; 999 scctx->isc_ntxqsets_max = scctx->isc_nrxqsets_max = 64; 1000 break; 1001 default: 1002 scctx->isc_rss_table_size = 128; 1003 scctx->isc_ntxqsets_max = scctx->isc_nrxqsets_max = 16; 1004 } 1005 1006 /* Allow legacy interrupts */ 1007 ixgbe_txrx.ift_legacy_intr = ixgbe_intr; 1008 1009 scctx->isc_txqsizes[0] = 1010 roundup2(scctx->isc_ntxd[0] * sizeof(union ixgbe_adv_tx_desc) + 1011 sizeof(u32), DBA_ALIGN), 1012 scctx->isc_rxqsizes[0] = 1013 roundup2(scctx->isc_nrxd[0] * sizeof(union ixgbe_adv_rx_desc), 1014 DBA_ALIGN); 1015 1016 /* XXX */ 1017 scctx->isc_tx_csum_flags = CSUM_IP | CSUM_TCP | CSUM_UDP | CSUM_TSO | 1018 CSUM_IP6_TCP | CSUM_IP6_UDP | CSUM_IP6_TSO; 1019 if (sc->hw.mac.type == ixgbe_mac_82598EB) { 1020 scctx->isc_tx_nsegments = IXGBE_82598_SCATTER; 1021 } else { 1022 scctx->isc_tx_csum_flags |= CSUM_SCTP |CSUM_IP6_SCTP; 1023 scctx->isc_tx_nsegments = IXGBE_82599_SCATTER; 1024 } 1025 1026 scctx->isc_msix_bar = pci_msix_table_bar(dev); 1027 1028 scctx->isc_tx_tso_segments_max = scctx->isc_tx_nsegments; 1029 scctx->isc_tx_tso_size_max = IXGBE_TSO_SIZE; 1030 scctx->isc_tx_tso_segsize_max = PAGE_SIZE; 1031 1032 scctx->isc_txrx = &ixgbe_txrx; 1033 1034 scctx->isc_capabilities = scctx->isc_capenable = IXGBE_CAPS; 1035 1036 return (0); 1037 1038 err_pci: 1039 ctrl_ext = IXGBE_READ_REG(&sc->hw, IXGBE_CTRL_EXT); 1040 ctrl_ext &= ~IXGBE_CTRL_EXT_DRV_LOAD; 1041 IXGBE_WRITE_REG(&sc->hw, IXGBE_CTRL_EXT, ctrl_ext); 1042 ixgbe_free_pci_resources(ctx); 1043 1044 return (error); 1045 } /* ixgbe_if_attach_pre */ 1046 1047 /********************************************************************* 1048 * ixgbe_if_attach_post - Device initialization routine, part 2 1049 * 1050 * Called during driver load, but after interrupts and 1051 * resources have been allocated and configured. 1052 * Sets up some data structures not relevant to iflib. 1053 * 1054 * return 0 on success, positive on failure 1055 *********************************************************************/ 1056 static int 1057 ixgbe_if_attach_post(if_ctx_t ctx) 1058 { 1059 device_t dev; 1060 struct ixgbe_softc *sc; 1061 struct ixgbe_hw *hw; 1062 int error = 0; 1063 1064 dev = iflib_get_dev(ctx); 1065 sc = iflib_get_softc(ctx); 1066 hw = &sc->hw; 1067 1068 1069 if (sc->intr_type == IFLIB_INTR_LEGACY && 1070 (sc->feat_cap & IXGBE_FEATURE_LEGACY_IRQ) == 0) { 1071 device_printf(dev, "Device does not support legacy interrupts"); 1072 error = ENXIO; 1073 goto err; 1074 } 1075 1076 /* Allocate multicast array memory. */ 1077 sc->mta = malloc(sizeof(*sc->mta) * 1078 MAX_NUM_MULTICAST_ADDRESSES, M_IXGBE, M_NOWAIT); 1079 if (sc->mta == NULL) { 1080 device_printf(dev, "Can not allocate multicast setup array\n"); 1081 error = ENOMEM; 1082 goto err; 1083 } 1084 1085 /* hw.ix defaults init */ 1086 ixgbe_set_advertise(sc, ixgbe_advertise_speed); 1087 1088 /* Enable the optics for 82599 SFP+ fiber */ 1089 ixgbe_enable_tx_laser(hw); 1090 1091 /* Enable power to the phy. */ 1092 ixgbe_set_phy_power(hw, true); 1093 1094 ixgbe_initialize_iov(sc); 1095 1096 error = ixgbe_setup_interface(ctx); 1097 if (error) { 1098 device_printf(dev, "Interface setup failed: %d\n", error); 1099 goto err; 1100 } 1101 1102 ixgbe_if_update_admin_status(ctx); 1103 1104 /* Initialize statistics */ 1105 ixgbe_update_stats_counters(sc); 1106 ixgbe_add_hw_stats(sc); 1107 1108 /* Check PCIE slot type/speed/width */ 1109 ixgbe_get_slot_info(sc); 1110 1111 /* 1112 * Do time init and sysctl init here, but 1113 * only on the first port of a bypass sc. 1114 */ 1115 ixgbe_bypass_init(sc); 1116 1117 /* Display NVM and Option ROM versions */ 1118 ixgbe_print_fw_version(ctx); 1119 1120 /* Set an initial dmac value */ 1121 sc->dmac = 0; 1122 /* Set initial advertised speeds (if applicable) */ 1123 sc->advertise = ixgbe_get_default_advertise(sc); 1124 1125 if (sc->feat_cap & IXGBE_FEATURE_SRIOV) 1126 ixgbe_define_iov_schemas(dev, &error); 1127 1128 /* Add sysctls */ 1129 ixgbe_add_device_sysctls(ctx); 1130 1131 return (0); 1132 err: 1133 return (error); 1134 } /* ixgbe_if_attach_post */ 1135 1136 /************************************************************************ 1137 * ixgbe_check_wol_support 1138 * 1139 * Checks whether the adapter's ports are capable of 1140 * Wake On LAN by reading the adapter's NVM. 1141 * 1142 * Sets each port's hw->wol_enabled value depending 1143 * on the value read here. 1144 ************************************************************************/ 1145 static void 1146 ixgbe_check_wol_support(struct ixgbe_softc *sc) 1147 { 1148 struct ixgbe_hw *hw = &sc->hw; 1149 u16 dev_caps = 0; 1150 1151 /* Find out WoL support for port */ 1152 sc->wol_support = hw->wol_enabled = 0; 1153 ixgbe_get_device_caps(hw, &dev_caps); 1154 if ((dev_caps & IXGBE_DEVICE_CAPS_WOL_PORT0_1) || 1155 ((dev_caps & IXGBE_DEVICE_CAPS_WOL_PORT0) && 1156 hw->bus.func == 0)) 1157 sc->wol_support = hw->wol_enabled = 1; 1158 1159 /* Save initial wake up filter configuration */ 1160 sc->wufc = IXGBE_READ_REG(hw, IXGBE_WUFC); 1161 1162 return; 1163 } /* ixgbe_check_wol_support */ 1164 1165 /************************************************************************ 1166 * ixgbe_setup_interface 1167 * 1168 * Setup networking device structure and register an interface. 1169 ************************************************************************/ 1170 static int 1171 ixgbe_setup_interface(if_ctx_t ctx) 1172 { 1173 if_t ifp = iflib_get_ifp(ctx); 1174 struct ixgbe_softc *sc = iflib_get_softc(ctx); 1175 1176 INIT_DEBUGOUT("ixgbe_setup_interface: begin"); 1177 1178 if_setbaudrate(ifp, IF_Gbps(10)); 1179 1180 sc->max_frame_size = if_getmtu(ifp) + ETHER_HDR_LEN + ETHER_CRC_LEN; 1181 1182 sc->phy_layer = ixgbe_get_supported_physical_layer(&sc->hw); 1183 1184 ixgbe_add_media_types(ctx); 1185 1186 /* Autoselect media by default */ 1187 ifmedia_set(sc->media, IFM_ETHER | IFM_AUTO); 1188 1189 return (0); 1190 } /* ixgbe_setup_interface */ 1191 1192 /************************************************************************ 1193 * ixgbe_if_get_counter 1194 ************************************************************************/ 1195 static uint64_t 1196 ixgbe_if_get_counter(if_ctx_t ctx, ift_counter cnt) 1197 { 1198 struct ixgbe_softc *sc = iflib_get_softc(ctx); 1199 if_t ifp = iflib_get_ifp(ctx); 1200 1201 switch (cnt) { 1202 case IFCOUNTER_IPACKETS: 1203 return (sc->ipackets); 1204 case IFCOUNTER_OPACKETS: 1205 return (sc->opackets); 1206 case IFCOUNTER_IBYTES: 1207 return (sc->ibytes); 1208 case IFCOUNTER_OBYTES: 1209 return (sc->obytes); 1210 case IFCOUNTER_IMCASTS: 1211 return (sc->imcasts); 1212 case IFCOUNTER_OMCASTS: 1213 return (sc->omcasts); 1214 case IFCOUNTER_COLLISIONS: 1215 return (0); 1216 case IFCOUNTER_IQDROPS: 1217 return (sc->iqdrops); 1218 case IFCOUNTER_OQDROPS: 1219 return (0); 1220 case IFCOUNTER_IERRORS: 1221 return (sc->ierrors); 1222 default: 1223 return (if_get_counter_default(ifp, cnt)); 1224 } 1225 } /* ixgbe_if_get_counter */ 1226 1227 /************************************************************************ 1228 * ixgbe_if_i2c_req 1229 ************************************************************************/ 1230 static int 1231 ixgbe_if_i2c_req(if_ctx_t ctx, struct ifi2creq *req) 1232 { 1233 struct ixgbe_softc *sc = iflib_get_softc(ctx); 1234 struct ixgbe_hw *hw = &sc->hw; 1235 int i; 1236 1237 1238 if (hw->phy.ops.read_i2c_byte == NULL) 1239 return (ENXIO); 1240 for (i = 0; i < req->len; i++) 1241 hw->phy.ops.read_i2c_byte(hw, req->offset + i, 1242 req->dev_addr, &req->data[i]); 1243 return (0); 1244 } /* ixgbe_if_i2c_req */ 1245 1246 /* ixgbe_if_needs_restart - Tell iflib when the driver needs to be reinitialized 1247 * @ctx: iflib context 1248 * @event: event code to check 1249 * 1250 * Defaults to returning true for unknown events. 1251 * 1252 * @returns true if iflib needs to reinit the interface 1253 */ 1254 static bool 1255 ixgbe_if_needs_restart(if_ctx_t ctx __unused, enum iflib_restart_event event) 1256 { 1257 switch (event) { 1258 case IFLIB_RESTART_VLAN_CONFIG: 1259 return (false); 1260 default: 1261 return (true); 1262 } 1263 } 1264 1265 /************************************************************************ 1266 * ixgbe_add_media_types 1267 ************************************************************************/ 1268 static void 1269 ixgbe_add_media_types(if_ctx_t ctx) 1270 { 1271 struct ixgbe_softc *sc = iflib_get_softc(ctx); 1272 struct ixgbe_hw *hw = &sc->hw; 1273 device_t dev = iflib_get_dev(ctx); 1274 u64 layer; 1275 1276 layer = sc->phy_layer = ixgbe_get_supported_physical_layer(hw); 1277 1278 /* Media types with matching FreeBSD media defines */ 1279 if (layer & IXGBE_PHYSICAL_LAYER_10GBASE_T) 1280 ifmedia_add(sc->media, IFM_ETHER | IFM_10G_T, 0, NULL); 1281 if (layer & IXGBE_PHYSICAL_LAYER_1000BASE_T) 1282 ifmedia_add(sc->media, IFM_ETHER | IFM_1000_T, 0, NULL); 1283 if (layer & IXGBE_PHYSICAL_LAYER_100BASE_TX) 1284 ifmedia_add(sc->media, IFM_ETHER | IFM_100_TX, 0, NULL); 1285 if (layer & IXGBE_PHYSICAL_LAYER_10BASE_T) 1286 ifmedia_add(sc->media, IFM_ETHER | IFM_10_T, 0, NULL); 1287 1288 if (hw->mac.type == ixgbe_mac_X550) { 1289 ifmedia_add(sc->media, IFM_ETHER | IFM_2500_T, 0, NULL); 1290 ifmedia_add(sc->media, IFM_ETHER | IFM_5000_T, 0, NULL); 1291 } 1292 1293 if (layer & IXGBE_PHYSICAL_LAYER_SFP_PLUS_CU || 1294 layer & IXGBE_PHYSICAL_LAYER_SFP_ACTIVE_DA) 1295 ifmedia_add(sc->media, IFM_ETHER | IFM_10G_TWINAX, 0, 1296 NULL); 1297 1298 if (layer & IXGBE_PHYSICAL_LAYER_10GBASE_LR) { 1299 ifmedia_add(sc->media, IFM_ETHER | IFM_10G_LR, 0, NULL); 1300 if (hw->phy.multispeed_fiber) 1301 ifmedia_add(sc->media, IFM_ETHER | IFM_1000_LX, 0, 1302 NULL); 1303 } 1304 if (layer & IXGBE_PHYSICAL_LAYER_10GBASE_SR) { 1305 ifmedia_add(sc->media, IFM_ETHER | IFM_10G_SR, 0, NULL); 1306 if (hw->phy.multispeed_fiber) 1307 ifmedia_add(sc->media, IFM_ETHER | IFM_1000_SX, 0, 1308 NULL); 1309 } else if (layer & IXGBE_PHYSICAL_LAYER_1000BASE_SX) 1310 ifmedia_add(sc->media, IFM_ETHER | IFM_1000_SX, 0, NULL); 1311 if (layer & IXGBE_PHYSICAL_LAYER_10GBASE_CX4) 1312 ifmedia_add(sc->media, IFM_ETHER | IFM_10G_CX4, 0, NULL); 1313 1314 #ifdef IFM_ETH_XTYPE 1315 if (layer & IXGBE_PHYSICAL_LAYER_10GBASE_KR) 1316 ifmedia_add(sc->media, IFM_ETHER | IFM_10G_KR, 0, NULL); 1317 if (layer & IXGBE_PHYSICAL_LAYER_10GBASE_KX4) 1318 ifmedia_add( sc->media, IFM_ETHER | IFM_10G_KX4, 0, NULL); 1319 if (layer & IXGBE_PHYSICAL_LAYER_1000BASE_KX) 1320 ifmedia_add(sc->media, IFM_ETHER | IFM_1000_KX, 0, NULL); 1321 if (layer & IXGBE_PHYSICAL_LAYER_2500BASE_KX) 1322 ifmedia_add(sc->media, IFM_ETHER | IFM_2500_KX, 0, NULL); 1323 #else 1324 if (layer & IXGBE_PHYSICAL_LAYER_10GBASE_KR) { 1325 device_printf(dev, "Media supported: 10GbaseKR\n"); 1326 device_printf(dev, "10GbaseKR mapped to 10GbaseSR\n"); 1327 ifmedia_add(sc->media, IFM_ETHER | IFM_10G_SR, 0, NULL); 1328 } 1329 if (layer & IXGBE_PHYSICAL_LAYER_10GBASE_KX4) { 1330 device_printf(dev, "Media supported: 10GbaseKX4\n"); 1331 device_printf(dev, "10GbaseKX4 mapped to 10GbaseCX4\n"); 1332 ifmedia_add(sc->media, IFM_ETHER | IFM_10G_CX4, 0, NULL); 1333 } 1334 if (layer & IXGBE_PHYSICAL_LAYER_1000BASE_KX) { 1335 device_printf(dev, "Media supported: 1000baseKX\n"); 1336 device_printf(dev, "1000baseKX mapped to 1000baseCX\n"); 1337 ifmedia_add(sc->media, IFM_ETHER | IFM_1000_CX, 0, NULL); 1338 } 1339 if (layer & IXGBE_PHYSICAL_LAYER_2500BASE_KX) { 1340 device_printf(dev, "Media supported: 2500baseKX\n"); 1341 device_printf(dev, "2500baseKX mapped to 2500baseSX\n"); 1342 ifmedia_add(sc->media, IFM_ETHER | IFM_2500_SX, 0, NULL); 1343 } 1344 #endif 1345 if (layer & IXGBE_PHYSICAL_LAYER_1000BASE_BX) 1346 device_printf(dev, "Media supported: 1000baseBX\n"); 1347 1348 if (hw->device_id == IXGBE_DEV_ID_82598AT) { 1349 ifmedia_add(sc->media, IFM_ETHER | IFM_1000_T | IFM_FDX, 1350 0, NULL); 1351 ifmedia_add(sc->media, IFM_ETHER | IFM_1000_T, 0, NULL); 1352 } 1353 1354 ifmedia_add(sc->media, IFM_ETHER | IFM_AUTO, 0, NULL); 1355 } /* ixgbe_add_media_types */ 1356 1357 /************************************************************************ 1358 * ixgbe_is_sfp 1359 ************************************************************************/ 1360 static inline bool 1361 ixgbe_is_sfp(struct ixgbe_hw *hw) 1362 { 1363 switch (hw->mac.type) { 1364 case ixgbe_mac_82598EB: 1365 if (hw->phy.type == ixgbe_phy_nl) 1366 return (true); 1367 return (false); 1368 case ixgbe_mac_82599EB: 1369 switch (hw->mac.ops.get_media_type(hw)) { 1370 case ixgbe_media_type_fiber: 1371 case ixgbe_media_type_fiber_qsfp: 1372 return (true); 1373 default: 1374 return (false); 1375 } 1376 case ixgbe_mac_X550EM_x: 1377 case ixgbe_mac_X550EM_a: 1378 if (hw->mac.ops.get_media_type(hw) == ixgbe_media_type_fiber) 1379 return (true); 1380 return (false); 1381 default: 1382 return (false); 1383 } 1384 } /* ixgbe_is_sfp */ 1385 1386 /************************************************************************ 1387 * ixgbe_config_link 1388 ************************************************************************/ 1389 static void 1390 ixgbe_config_link(if_ctx_t ctx) 1391 { 1392 struct ixgbe_softc *sc = iflib_get_softc(ctx); 1393 struct ixgbe_hw *hw = &sc->hw; 1394 u32 autoneg, err = 0; 1395 bool sfp, negotiate; 1396 1397 sfp = ixgbe_is_sfp(hw); 1398 1399 if (sfp) { 1400 sc->task_requests |= IXGBE_REQUEST_TASK_MOD; 1401 iflib_admin_intr_deferred(ctx); 1402 } else { 1403 if (hw->mac.ops.check_link) 1404 err = ixgbe_check_link(hw, &sc->link_speed, 1405 &sc->link_up, false); 1406 if (err) 1407 return; 1408 autoneg = hw->phy.autoneg_advertised; 1409 if ((!autoneg) && (hw->mac.ops.get_link_capabilities)) 1410 err = hw->mac.ops.get_link_capabilities(hw, &autoneg, 1411 &negotiate); 1412 if (err) 1413 return; 1414 1415 if (hw->mac.type == ixgbe_mac_X550 && 1416 hw->phy.autoneg_advertised == 0) { 1417 /* 1418 * 2.5G and 5G autonegotiation speeds on X550 1419 * are disabled by default due to reported 1420 * interoperability issues with some switches. 1421 * 1422 * The second condition checks if any operations 1423 * involving setting autonegotiation speeds have 1424 * been performed prior to this ixgbe_config_link() 1425 * call. 1426 * 1427 * If hw->phy.autoneg_advertised does not 1428 * equal 0, this means that the user might have 1429 * set autonegotiation speeds via the sysctl 1430 * before bringing the interface up. In this 1431 * case, we should not disable 2.5G and 5G 1432 * since that speeds might be selected by the 1433 * user. 1434 * 1435 * Otherwise (i.e. if hw->phy.autoneg_advertised 1436 * is set to 0), it is the first time we set 1437 * autonegotiation preferences and the default 1438 * set of speeds should exclude 2.5G and 5G. 1439 */ 1440 autoneg &= ~(IXGBE_LINK_SPEED_2_5GB_FULL | 1441 IXGBE_LINK_SPEED_5GB_FULL); 1442 } 1443 1444 if (hw->mac.ops.setup_link) 1445 err = hw->mac.ops.setup_link(hw, autoneg, 1446 sc->link_up); 1447 } 1448 } /* ixgbe_config_link */ 1449 1450 /************************************************************************ 1451 * ixgbe_update_stats_counters - Update board statistics counters. 1452 ************************************************************************/ 1453 static void 1454 ixgbe_update_stats_counters(struct ixgbe_softc *sc) 1455 { 1456 struct ixgbe_hw *hw = &sc->hw; 1457 struct ixgbe_hw_stats *stats = &sc->stats.pf; 1458 u32 missed_rx = 0, bprc, lxon, lxoff, total; 1459 u32 lxoffrxc; 1460 u64 total_missed_rx = 0; 1461 1462 stats->crcerrs += IXGBE_READ_REG(hw, IXGBE_CRCERRS); 1463 stats->illerrc += IXGBE_READ_REG(hw, IXGBE_ILLERRC); 1464 stats->errbc += IXGBE_READ_REG(hw, IXGBE_ERRBC); 1465 stats->mspdc += IXGBE_READ_REG(hw, IXGBE_MSPDC); 1466 stats->mpc[0] += IXGBE_READ_REG(hw, IXGBE_MPC(0)); 1467 1468 for (int i = 0; i < 16; i++) { 1469 stats->qprc[i] += IXGBE_READ_REG(hw, IXGBE_QPRC(i)); 1470 stats->qptc[i] += IXGBE_READ_REG(hw, IXGBE_QPTC(i)); 1471 stats->qprdc[i] += IXGBE_READ_REG(hw, IXGBE_QPRDC(i)); 1472 } 1473 stats->mlfc += IXGBE_READ_REG(hw, IXGBE_MLFC); 1474 stats->mrfc += IXGBE_READ_REG(hw, IXGBE_MRFC); 1475 stats->rlec += IXGBE_READ_REG(hw, IXGBE_RLEC); 1476 1477 /* Hardware workaround, gprc counts missed packets */ 1478 stats->gprc += IXGBE_READ_REG(hw, IXGBE_GPRC); 1479 stats->gprc -= missed_rx; 1480 1481 if (hw->mac.type != ixgbe_mac_82598EB) { 1482 stats->gorc += IXGBE_READ_REG(hw, IXGBE_GORCL) + 1483 ((u64)IXGBE_READ_REG(hw, IXGBE_GORCH) << 32); 1484 stats->gotc += IXGBE_READ_REG(hw, IXGBE_GOTCL) + 1485 ((u64)IXGBE_READ_REG(hw, IXGBE_GOTCH) << 32); 1486 stats->tor += IXGBE_READ_REG(hw, IXGBE_TORL) + 1487 ((u64)IXGBE_READ_REG(hw, IXGBE_TORH) << 32); 1488 stats->lxonrxc += IXGBE_READ_REG(hw, IXGBE_LXONRXCNT); 1489 lxoffrxc = IXGBE_READ_REG(hw, IXGBE_LXOFFRXCNT); 1490 stats->lxoffrxc += lxoffrxc; 1491 } else { 1492 stats->lxonrxc += IXGBE_READ_REG(hw, IXGBE_LXONRXC); 1493 lxoffrxc = IXGBE_READ_REG(hw, IXGBE_LXOFFRXC); 1494 stats->lxoffrxc += lxoffrxc; 1495 /* 82598 only has a counter in the high register */ 1496 stats->gorc += IXGBE_READ_REG(hw, IXGBE_GORCH); 1497 stats->gotc += IXGBE_READ_REG(hw, IXGBE_GOTCH); 1498 stats->tor += IXGBE_READ_REG(hw, IXGBE_TORH); 1499 } 1500 1501 /* 1502 * For watchdog management we need to know if we have been paused 1503 * during the last interval, so capture that here. 1504 */ 1505 if (lxoffrxc) 1506 sc->shared->isc_pause_frames = 1; 1507 1508 /* 1509 * Workaround: mprc hardware is incorrectly counting 1510 * broadcasts, so for now we subtract those. 1511 */ 1512 bprc = IXGBE_READ_REG(hw, IXGBE_BPRC); 1513 stats->bprc += bprc; 1514 stats->mprc += IXGBE_READ_REG(hw, IXGBE_MPRC); 1515 if (hw->mac.type == ixgbe_mac_82598EB) 1516 stats->mprc -= bprc; 1517 1518 stats->prc64 += IXGBE_READ_REG(hw, IXGBE_PRC64); 1519 stats->prc127 += IXGBE_READ_REG(hw, IXGBE_PRC127); 1520 stats->prc255 += IXGBE_READ_REG(hw, IXGBE_PRC255); 1521 stats->prc511 += IXGBE_READ_REG(hw, IXGBE_PRC511); 1522 stats->prc1023 += IXGBE_READ_REG(hw, IXGBE_PRC1023); 1523 stats->prc1522 += IXGBE_READ_REG(hw, IXGBE_PRC1522); 1524 1525 lxon = IXGBE_READ_REG(hw, IXGBE_LXONTXC); 1526 stats->lxontxc += lxon; 1527 lxoff = IXGBE_READ_REG(hw, IXGBE_LXOFFTXC); 1528 stats->lxofftxc += lxoff; 1529 total = lxon + lxoff; 1530 1531 stats->gptc += IXGBE_READ_REG(hw, IXGBE_GPTC); 1532 stats->mptc += IXGBE_READ_REG(hw, IXGBE_MPTC); 1533 stats->ptc64 += IXGBE_READ_REG(hw, IXGBE_PTC64); 1534 stats->gptc -= total; 1535 stats->mptc -= total; 1536 stats->ptc64 -= total; 1537 stats->gotc -= total * ETHER_MIN_LEN; 1538 1539 stats->ruc += IXGBE_READ_REG(hw, IXGBE_RUC); 1540 stats->rfc += IXGBE_READ_REG(hw, IXGBE_RFC); 1541 stats->roc += IXGBE_READ_REG(hw, IXGBE_ROC); 1542 stats->rjc += IXGBE_READ_REG(hw, IXGBE_RJC); 1543 stats->mngprc += IXGBE_READ_REG(hw, IXGBE_MNGPRC); 1544 stats->mngpdc += IXGBE_READ_REG(hw, IXGBE_MNGPDC); 1545 stats->mngptc += IXGBE_READ_REG(hw, IXGBE_MNGPTC); 1546 stats->tpr += IXGBE_READ_REG(hw, IXGBE_TPR); 1547 stats->tpt += IXGBE_READ_REG(hw, IXGBE_TPT); 1548 stats->ptc127 += IXGBE_READ_REG(hw, IXGBE_PTC127); 1549 stats->ptc255 += IXGBE_READ_REG(hw, IXGBE_PTC255); 1550 stats->ptc511 += IXGBE_READ_REG(hw, IXGBE_PTC511); 1551 stats->ptc1023 += IXGBE_READ_REG(hw, IXGBE_PTC1023); 1552 stats->ptc1522 += IXGBE_READ_REG(hw, IXGBE_PTC1522); 1553 stats->bptc += IXGBE_READ_REG(hw, IXGBE_BPTC); 1554 stats->xec += IXGBE_READ_REG(hw, IXGBE_XEC); 1555 stats->fccrc += IXGBE_READ_REG(hw, IXGBE_FCCRC); 1556 stats->fclast += IXGBE_READ_REG(hw, IXGBE_FCLAST); 1557 /* Only read FCOE on 82599 */ 1558 if (hw->mac.type != ixgbe_mac_82598EB) { 1559 stats->fcoerpdc += IXGBE_READ_REG(hw, IXGBE_FCOERPDC); 1560 stats->fcoeprc += IXGBE_READ_REG(hw, IXGBE_FCOEPRC); 1561 stats->fcoeptc += IXGBE_READ_REG(hw, IXGBE_FCOEPTC); 1562 stats->fcoedwrc += IXGBE_READ_REG(hw, IXGBE_FCOEDWRC); 1563 stats->fcoedwtc += IXGBE_READ_REG(hw, IXGBE_FCOEDWTC); 1564 } 1565 1566 /* Fill out the OS statistics structure */ 1567 IXGBE_SET_IPACKETS(sc, stats->gprc); 1568 IXGBE_SET_OPACKETS(sc, stats->gptc); 1569 IXGBE_SET_IBYTES(sc, stats->gorc); 1570 IXGBE_SET_OBYTES(sc, stats->gotc); 1571 IXGBE_SET_IMCASTS(sc, stats->mprc); 1572 IXGBE_SET_OMCASTS(sc, stats->mptc); 1573 IXGBE_SET_COLLISIONS(sc, 0); 1574 IXGBE_SET_IQDROPS(sc, total_missed_rx); 1575 1576 /* 1577 * Aggregate following types of errors as RX errors: 1578 * - CRC error count, 1579 * - illegal byte error count, 1580 * - missed packets count, 1581 * - length error count, 1582 * - undersized packets count, 1583 * - fragmented packets count, 1584 * - oversized packets count, 1585 * - jabber count. 1586 */ 1587 IXGBE_SET_IERRORS(sc, stats->crcerrs + stats->illerrc + 1588 stats->mpc[0] + stats->rlec + stats->ruc + stats->rfc + stats->roc + 1589 stats->rjc); 1590 } /* ixgbe_update_stats_counters */ 1591 1592 /************************************************************************ 1593 * ixgbe_add_hw_stats 1594 * 1595 * Add sysctl variables, one per statistic, to the system. 1596 ************************************************************************/ 1597 static void 1598 ixgbe_add_hw_stats(struct ixgbe_softc *sc) 1599 { 1600 device_t dev = iflib_get_dev(sc->ctx); 1601 struct ix_rx_queue *rx_que; 1602 struct ix_tx_queue *tx_que; 1603 struct sysctl_ctx_list *ctx = device_get_sysctl_ctx(dev); 1604 struct sysctl_oid *tree = device_get_sysctl_tree(dev); 1605 struct sysctl_oid_list *child = SYSCTL_CHILDREN(tree); 1606 struct ixgbe_hw_stats *stats = &sc->stats.pf; 1607 struct sysctl_oid *stat_node, *queue_node; 1608 struct sysctl_oid_list *stat_list, *queue_list; 1609 int i; 1610 1611 #define QUEUE_NAME_LEN 32 1612 char namebuf[QUEUE_NAME_LEN]; 1613 1614 /* Driver Statistics */ 1615 SYSCTL_ADD_ULONG(ctx, child, OID_AUTO, "dropped", 1616 CTLFLAG_RD, &sc->dropped_pkts, "Driver dropped packets"); 1617 SYSCTL_ADD_ULONG(ctx, child, OID_AUTO, "watchdog_events", 1618 CTLFLAG_RD, &sc->watchdog_events, "Watchdog timeouts"); 1619 SYSCTL_ADD_ULONG(ctx, child, OID_AUTO, "link_irq", 1620 CTLFLAG_RD, &sc->link_irq, "Link MSI-X IRQ Handled"); 1621 1622 for (i = 0, tx_que = sc->tx_queues; i < sc->num_tx_queues; i++, tx_que++) { 1623 struct tx_ring *txr = &tx_que->txr; 1624 snprintf(namebuf, QUEUE_NAME_LEN, "queue%d", i); 1625 queue_node = SYSCTL_ADD_NODE(ctx, child, OID_AUTO, namebuf, 1626 CTLFLAG_RD | CTLFLAG_MPSAFE, NULL, "Queue Name"); 1627 queue_list = SYSCTL_CHILDREN(queue_node); 1628 1629 SYSCTL_ADD_PROC(ctx, queue_list, OID_AUTO, "txd_head", 1630 CTLTYPE_UINT | CTLFLAG_RD | CTLFLAG_NEEDGIANT, txr, 0, 1631 ixgbe_sysctl_tdh_handler, "IU", "Transmit Descriptor Head"); 1632 SYSCTL_ADD_PROC(ctx, queue_list, OID_AUTO, "txd_tail", 1633 CTLTYPE_UINT | CTLFLAG_RD | CTLFLAG_NEEDGIANT, txr, 0, 1634 ixgbe_sysctl_tdt_handler, "IU", "Transmit Descriptor Tail"); 1635 SYSCTL_ADD_UQUAD(ctx, queue_list, OID_AUTO, "tso_tx", 1636 CTLFLAG_RD, &txr->tso_tx, "TSO"); 1637 SYSCTL_ADD_UQUAD(ctx, queue_list, OID_AUTO, "tx_packets", 1638 CTLFLAG_RD, &txr->total_packets, 1639 "Queue Packets Transmitted"); 1640 } 1641 1642 for (i = 0, rx_que = sc->rx_queues; i < sc->num_rx_queues; i++, rx_que++) { 1643 struct rx_ring *rxr = &rx_que->rxr; 1644 snprintf(namebuf, QUEUE_NAME_LEN, "queue%d", i); 1645 queue_node = SYSCTL_ADD_NODE(ctx, child, OID_AUTO, namebuf, 1646 CTLFLAG_RD | CTLFLAG_MPSAFE, NULL, "Queue Name"); 1647 queue_list = SYSCTL_CHILDREN(queue_node); 1648 1649 SYSCTL_ADD_PROC(ctx, queue_list, OID_AUTO, "interrupt_rate", 1650 CTLTYPE_UINT | CTLFLAG_RW | CTLFLAG_NEEDGIANT, 1651 &sc->rx_queues[i], 0, 1652 ixgbe_sysctl_interrupt_rate_handler, "IU", 1653 "Interrupt Rate"); 1654 SYSCTL_ADD_UQUAD(ctx, queue_list, OID_AUTO, "irqs", 1655 CTLFLAG_RD, &(sc->rx_queues[i].irqs), 1656 "irqs on this queue"); 1657 SYSCTL_ADD_PROC(ctx, queue_list, OID_AUTO, "rxd_head", 1658 CTLTYPE_UINT | CTLFLAG_RD | CTLFLAG_NEEDGIANT, rxr, 0, 1659 ixgbe_sysctl_rdh_handler, "IU", "Receive Descriptor Head"); 1660 SYSCTL_ADD_PROC(ctx, queue_list, OID_AUTO, "rxd_tail", 1661 CTLTYPE_UINT | CTLFLAG_RD | CTLFLAG_NEEDGIANT, rxr, 0, 1662 ixgbe_sysctl_rdt_handler, "IU", "Receive Descriptor Tail"); 1663 SYSCTL_ADD_UQUAD(ctx, queue_list, OID_AUTO, "rx_packets", 1664 CTLFLAG_RD, &rxr->rx_packets, "Queue Packets Received"); 1665 SYSCTL_ADD_UQUAD(ctx, queue_list, OID_AUTO, "rx_bytes", 1666 CTLFLAG_RD, &rxr->rx_bytes, "Queue Bytes Received"); 1667 SYSCTL_ADD_UQUAD(ctx, queue_list, OID_AUTO, "rx_copies", 1668 CTLFLAG_RD, &rxr->rx_copies, "Copied RX Frames"); 1669 SYSCTL_ADD_UQUAD(ctx, queue_list, OID_AUTO, "rx_discarded", 1670 CTLFLAG_RD, &rxr->rx_discarded, "Discarded RX packets"); 1671 } 1672 1673 /* MAC stats get their own sub node */ 1674 1675 stat_node = SYSCTL_ADD_NODE(ctx, child, OID_AUTO, "mac_stats", 1676 CTLFLAG_RD | CTLFLAG_MPSAFE, NULL, "MAC Statistics"); 1677 stat_list = SYSCTL_CHILDREN(stat_node); 1678 1679 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "rx_errs", 1680 CTLFLAG_RD, &sc->ierrors, IXGBE_SYSCTL_DESC_RX_ERRS); 1681 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "crc_errs", 1682 CTLFLAG_RD, &stats->crcerrs, "CRC Errors"); 1683 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "ill_errs", 1684 CTLFLAG_RD, &stats->illerrc, "Illegal Byte Errors"); 1685 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "byte_errs", 1686 CTLFLAG_RD, &stats->errbc, "Byte Errors"); 1687 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "short_discards", 1688 CTLFLAG_RD, &stats->mspdc, "MAC Short Packets Discarded"); 1689 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "local_faults", 1690 CTLFLAG_RD, &stats->mlfc, "MAC Local Faults"); 1691 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "remote_faults", 1692 CTLFLAG_RD, &stats->mrfc, "MAC Remote Faults"); 1693 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "rec_len_errs", 1694 CTLFLAG_RD, &stats->rlec, "Receive Length Errors"); 1695 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "rx_missed_packets", 1696 CTLFLAG_RD, &stats->mpc[0], "RX Missed Packet Count"); 1697 1698 /* Flow Control stats */ 1699 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "xon_txd", 1700 CTLFLAG_RD, &stats->lxontxc, "Link XON Transmitted"); 1701 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "xon_recvd", 1702 CTLFLAG_RD, &stats->lxonrxc, "Link XON Received"); 1703 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "xoff_txd", 1704 CTLFLAG_RD, &stats->lxofftxc, "Link XOFF Transmitted"); 1705 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "xoff_recvd", 1706 CTLFLAG_RD, &stats->lxoffrxc, "Link XOFF Received"); 1707 1708 /* Packet Reception Stats */ 1709 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "total_octets_rcvd", 1710 CTLFLAG_RD, &stats->tor, "Total Octets Received"); 1711 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "good_octets_rcvd", 1712 CTLFLAG_RD, &stats->gorc, "Good Octets Received"); 1713 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "total_pkts_rcvd", 1714 CTLFLAG_RD, &stats->tpr, "Total Packets Received"); 1715 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "good_pkts_rcvd", 1716 CTLFLAG_RD, &stats->gprc, "Good Packets Received"); 1717 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "mcast_pkts_rcvd", 1718 CTLFLAG_RD, &stats->mprc, "Multicast Packets Received"); 1719 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "bcast_pkts_rcvd", 1720 CTLFLAG_RD, &stats->bprc, "Broadcast Packets Received"); 1721 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "rx_frames_64", 1722 CTLFLAG_RD, &stats->prc64, "64 byte frames received "); 1723 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "rx_frames_65_127", 1724 CTLFLAG_RD, &stats->prc127, "65-127 byte frames received"); 1725 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "rx_frames_128_255", 1726 CTLFLAG_RD, &stats->prc255, "128-255 byte frames received"); 1727 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "rx_frames_256_511", 1728 CTLFLAG_RD, &stats->prc511, "256-511 byte frames received"); 1729 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "rx_frames_512_1023", 1730 CTLFLAG_RD, &stats->prc1023, "512-1023 byte frames received"); 1731 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "rx_frames_1024_1522", 1732 CTLFLAG_RD, &stats->prc1522, "1023-1522 byte frames received"); 1733 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "recv_undersized", 1734 CTLFLAG_RD, &stats->ruc, "Receive Undersized"); 1735 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "recv_fragmented", 1736 CTLFLAG_RD, &stats->rfc, "Fragmented Packets Received "); 1737 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "recv_oversized", 1738 CTLFLAG_RD, &stats->roc, "Oversized Packets Received"); 1739 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "recv_jabberd", 1740 CTLFLAG_RD, &stats->rjc, "Received Jabber"); 1741 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "management_pkts_rcvd", 1742 CTLFLAG_RD, &stats->mngprc, "Management Packets Received"); 1743 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "management_pkts_drpd", 1744 CTLFLAG_RD, &stats->mngptc, "Management Packets Dropped"); 1745 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "checksum_errs", 1746 CTLFLAG_RD, &stats->xec, "Checksum Errors"); 1747 1748 /* Packet Transmission Stats */ 1749 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "good_octets_txd", 1750 CTLFLAG_RD, &stats->gotc, "Good Octets Transmitted"); 1751 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "total_pkts_txd", 1752 CTLFLAG_RD, &stats->tpt, "Total Packets Transmitted"); 1753 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "good_pkts_txd", 1754 CTLFLAG_RD, &stats->gptc, "Good Packets Transmitted"); 1755 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "bcast_pkts_txd", 1756 CTLFLAG_RD, &stats->bptc, "Broadcast Packets Transmitted"); 1757 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "mcast_pkts_txd", 1758 CTLFLAG_RD, &stats->mptc, "Multicast Packets Transmitted"); 1759 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "management_pkts_txd", 1760 CTLFLAG_RD, &stats->mngptc, "Management Packets Transmitted"); 1761 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "tx_frames_64", 1762 CTLFLAG_RD, &stats->ptc64, "64 byte frames transmitted "); 1763 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "tx_frames_65_127", 1764 CTLFLAG_RD, &stats->ptc127, "65-127 byte frames transmitted"); 1765 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "tx_frames_128_255", 1766 CTLFLAG_RD, &stats->ptc255, "128-255 byte frames transmitted"); 1767 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "tx_frames_256_511", 1768 CTLFLAG_RD, &stats->ptc511, "256-511 byte frames transmitted"); 1769 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "tx_frames_512_1023", 1770 CTLFLAG_RD, &stats->ptc1023, "512-1023 byte frames transmitted"); 1771 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "tx_frames_1024_1522", 1772 CTLFLAG_RD, &stats->ptc1522, "1024-1522 byte frames transmitted"); 1773 } /* ixgbe_add_hw_stats */ 1774 1775 /************************************************************************ 1776 * ixgbe_sysctl_tdh_handler - Transmit Descriptor Head handler function 1777 * 1778 * Retrieves the TDH value from the hardware 1779 ************************************************************************/ 1780 static int 1781 ixgbe_sysctl_tdh_handler(SYSCTL_HANDLER_ARGS) 1782 { 1783 struct tx_ring *txr = ((struct tx_ring *)oidp->oid_arg1); 1784 int error; 1785 unsigned int val; 1786 1787 if (!txr) 1788 return (0); 1789 1790 val = IXGBE_READ_REG(&txr->sc->hw, IXGBE_TDH(txr->me)); 1791 error = sysctl_handle_int(oidp, &val, 0, req); 1792 if (error || !req->newptr) 1793 return error; 1794 1795 return (0); 1796 } /* ixgbe_sysctl_tdh_handler */ 1797 1798 /************************************************************************ 1799 * ixgbe_sysctl_tdt_handler - Transmit Descriptor Tail handler function 1800 * 1801 * Retrieves the TDT value from the hardware 1802 ************************************************************************/ 1803 static int 1804 ixgbe_sysctl_tdt_handler(SYSCTL_HANDLER_ARGS) 1805 { 1806 struct tx_ring *txr = ((struct tx_ring *)oidp->oid_arg1); 1807 int error; 1808 unsigned int val; 1809 1810 if (!txr) 1811 return (0); 1812 1813 val = IXGBE_READ_REG(&txr->sc->hw, IXGBE_TDT(txr->me)); 1814 error = sysctl_handle_int(oidp, &val, 0, req); 1815 if (error || !req->newptr) 1816 return error; 1817 1818 return (0); 1819 } /* ixgbe_sysctl_tdt_handler */ 1820 1821 /************************************************************************ 1822 * ixgbe_sysctl_rdh_handler - Receive Descriptor Head handler function 1823 * 1824 * Retrieves the RDH value from the hardware 1825 ************************************************************************/ 1826 static int 1827 ixgbe_sysctl_rdh_handler(SYSCTL_HANDLER_ARGS) 1828 { 1829 struct rx_ring *rxr = ((struct rx_ring *)oidp->oid_arg1); 1830 int error; 1831 unsigned int val; 1832 1833 if (!rxr) 1834 return (0); 1835 1836 val = IXGBE_READ_REG(&rxr->sc->hw, IXGBE_RDH(rxr->me)); 1837 error = sysctl_handle_int(oidp, &val, 0, req); 1838 if (error || !req->newptr) 1839 return error; 1840 1841 return (0); 1842 } /* ixgbe_sysctl_rdh_handler */ 1843 1844 /************************************************************************ 1845 * ixgbe_sysctl_rdt_handler - Receive Descriptor Tail handler function 1846 * 1847 * Retrieves the RDT value from the hardware 1848 ************************************************************************/ 1849 static int 1850 ixgbe_sysctl_rdt_handler(SYSCTL_HANDLER_ARGS) 1851 { 1852 struct rx_ring *rxr = ((struct rx_ring *)oidp->oid_arg1); 1853 int error; 1854 unsigned int val; 1855 1856 if (!rxr) 1857 return (0); 1858 1859 val = IXGBE_READ_REG(&rxr->sc->hw, IXGBE_RDT(rxr->me)); 1860 error = sysctl_handle_int(oidp, &val, 0, req); 1861 if (error || !req->newptr) 1862 return error; 1863 1864 return (0); 1865 } /* ixgbe_sysctl_rdt_handler */ 1866 1867 /************************************************************************ 1868 * ixgbe_if_vlan_register 1869 * 1870 * Run via vlan config EVENT, it enables us to use the 1871 * HW Filter table since we can get the vlan id. This 1872 * just creates the entry in the soft version of the 1873 * VFTA, init will repopulate the real table. 1874 ************************************************************************/ 1875 static void 1876 ixgbe_if_vlan_register(if_ctx_t ctx, u16 vtag) 1877 { 1878 struct ixgbe_softc *sc = iflib_get_softc(ctx); 1879 u16 index, bit; 1880 1881 index = (vtag >> 5) & 0x7F; 1882 bit = vtag & 0x1F; 1883 sc->shadow_vfta[index] |= (1 << bit); 1884 ++sc->num_vlans; 1885 ixgbe_setup_vlan_hw_support(ctx); 1886 } /* ixgbe_if_vlan_register */ 1887 1888 /************************************************************************ 1889 * ixgbe_if_vlan_unregister 1890 * 1891 * Run via vlan unconfig EVENT, remove our entry in the soft vfta. 1892 ************************************************************************/ 1893 static void 1894 ixgbe_if_vlan_unregister(if_ctx_t ctx, u16 vtag) 1895 { 1896 struct ixgbe_softc *sc = iflib_get_softc(ctx); 1897 u16 index, bit; 1898 1899 index = (vtag >> 5) & 0x7F; 1900 bit = vtag & 0x1F; 1901 sc->shadow_vfta[index] &= ~(1 << bit); 1902 --sc->num_vlans; 1903 /* Re-init to load the changes */ 1904 ixgbe_setup_vlan_hw_support(ctx); 1905 } /* ixgbe_if_vlan_unregister */ 1906 1907 /************************************************************************ 1908 * ixgbe_setup_vlan_hw_support 1909 ************************************************************************/ 1910 static void 1911 ixgbe_setup_vlan_hw_support(if_ctx_t ctx) 1912 { 1913 if_t ifp = iflib_get_ifp(ctx); 1914 struct ixgbe_softc *sc = iflib_get_softc(ctx); 1915 struct ixgbe_hw *hw = &sc->hw; 1916 struct rx_ring *rxr; 1917 int i; 1918 u32 ctrl; 1919 1920 1921 /* 1922 * We get here thru init_locked, meaning 1923 * a soft reset, this has already cleared 1924 * the VFTA and other state, so if there 1925 * have been no vlan's registered do nothing. 1926 */ 1927 if (sc->num_vlans == 0 || (if_getcapenable(ifp) & IFCAP_VLAN_HWTAGGING) == 0) { 1928 /* Clear the vlan hw flag */ 1929 for (i = 0; i < sc->num_rx_queues; i++) { 1930 rxr = &sc->rx_queues[i].rxr; 1931 /* On 82599 the VLAN enable is per/queue in RXDCTL */ 1932 if (hw->mac.type != ixgbe_mac_82598EB) { 1933 ctrl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(rxr->me)); 1934 ctrl &= ~IXGBE_RXDCTL_VME; 1935 IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(rxr->me), ctrl); 1936 } 1937 rxr->vtag_strip = false; 1938 } 1939 ctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL); 1940 /* Enable the Filter Table if enabled */ 1941 ctrl |= IXGBE_VLNCTRL_CFIEN; 1942 ctrl &= ~IXGBE_VLNCTRL_VFE; 1943 if (hw->mac.type == ixgbe_mac_82598EB) 1944 ctrl &= ~IXGBE_VLNCTRL_VME; 1945 IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, ctrl); 1946 return; 1947 } 1948 1949 /* Setup the queues for vlans */ 1950 if (if_getcapenable(ifp) & IFCAP_VLAN_HWTAGGING) { 1951 for (i = 0; i < sc->num_rx_queues; i++) { 1952 rxr = &sc->rx_queues[i].rxr; 1953 /* On 82599 the VLAN enable is per/queue in RXDCTL */ 1954 if (hw->mac.type != ixgbe_mac_82598EB) { 1955 ctrl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(rxr->me)); 1956 ctrl |= IXGBE_RXDCTL_VME; 1957 IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(rxr->me), ctrl); 1958 } 1959 rxr->vtag_strip = true; 1960 } 1961 } 1962 1963 if ((if_getcapenable(ifp) & IFCAP_VLAN_HWFILTER) == 0) 1964 return; 1965 /* 1966 * A soft reset zero's out the VFTA, so 1967 * we need to repopulate it now. 1968 */ 1969 for (i = 0; i < IXGBE_VFTA_SIZE; i++) 1970 if (sc->shadow_vfta[i] != 0) 1971 IXGBE_WRITE_REG(hw, IXGBE_VFTA(i), 1972 sc->shadow_vfta[i]); 1973 1974 ctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL); 1975 /* Enable the Filter Table if enabled */ 1976 if (if_getcapenable(ifp) & IFCAP_VLAN_HWFILTER) { 1977 ctrl &= ~IXGBE_VLNCTRL_CFIEN; 1978 ctrl |= IXGBE_VLNCTRL_VFE; 1979 } 1980 if (hw->mac.type == ixgbe_mac_82598EB) 1981 ctrl |= IXGBE_VLNCTRL_VME; 1982 IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, ctrl); 1983 } /* ixgbe_setup_vlan_hw_support */ 1984 1985 /************************************************************************ 1986 * ixgbe_get_slot_info 1987 * 1988 * Get the width and transaction speed of 1989 * the slot this adapter is plugged into. 1990 ************************************************************************/ 1991 static void 1992 ixgbe_get_slot_info(struct ixgbe_softc *sc) 1993 { 1994 device_t dev = iflib_get_dev(sc->ctx); 1995 struct ixgbe_hw *hw = &sc->hw; 1996 int bus_info_valid = true; 1997 u32 offset; 1998 u16 link; 1999 2000 /* Some devices are behind an internal bridge */ 2001 switch (hw->device_id) { 2002 case IXGBE_DEV_ID_82599_SFP_SF_QP: 2003 case IXGBE_DEV_ID_82599_QSFP_SF_QP: 2004 goto get_parent_info; 2005 default: 2006 break; 2007 } 2008 2009 ixgbe_get_bus_info(hw); 2010 2011 /* 2012 * Some devices don't use PCI-E, but there is no need 2013 * to display "Unknown" for bus speed and width. 2014 */ 2015 switch (hw->mac.type) { 2016 case ixgbe_mac_X550EM_x: 2017 case ixgbe_mac_X550EM_a: 2018 return; 2019 default: 2020 goto display; 2021 } 2022 2023 get_parent_info: 2024 /* 2025 * For the Quad port adapter we need to parse back 2026 * up the PCI tree to find the speed of the expansion 2027 * slot into which this adapter is plugged. A bit more work. 2028 */ 2029 dev = device_get_parent(device_get_parent(dev)); 2030 #ifdef IXGBE_DEBUG 2031 device_printf(dev, "parent pcib = %x,%x,%x\n", pci_get_bus(dev), 2032 pci_get_slot(dev), pci_get_function(dev)); 2033 #endif 2034 dev = device_get_parent(device_get_parent(dev)); 2035 #ifdef IXGBE_DEBUG 2036 device_printf(dev, "slot pcib = %x,%x,%x\n", pci_get_bus(dev), 2037 pci_get_slot(dev), pci_get_function(dev)); 2038 #endif 2039 /* Now get the PCI Express Capabilities offset */ 2040 if (pci_find_cap(dev, PCIY_EXPRESS, &offset)) { 2041 /* 2042 * Hmm...can't get PCI-Express capabilities. 2043 * Falling back to default method. 2044 */ 2045 bus_info_valid = false; 2046 ixgbe_get_bus_info(hw); 2047 goto display; 2048 } 2049 /* ...and read the Link Status Register */ 2050 link = pci_read_config(dev, offset + PCIER_LINK_STA, 2); 2051 ixgbe_set_pci_config_data_generic(hw, link); 2052 2053 display: 2054 device_printf(dev, "PCI Express Bus: Speed %s %s\n", 2055 ((hw->bus.speed == ixgbe_bus_speed_8000) ? "8.0GT/s" : 2056 (hw->bus.speed == ixgbe_bus_speed_5000) ? "5.0GT/s" : 2057 (hw->bus.speed == ixgbe_bus_speed_2500) ? "2.5GT/s" : 2058 "Unknown"), 2059 ((hw->bus.width == ixgbe_bus_width_pcie_x8) ? "Width x8" : 2060 (hw->bus.width == ixgbe_bus_width_pcie_x4) ? "Width x4" : 2061 (hw->bus.width == ixgbe_bus_width_pcie_x1) ? "Width x1" : 2062 "Unknown")); 2063 2064 if (bus_info_valid) { 2065 if ((hw->device_id != IXGBE_DEV_ID_82599_SFP_SF_QP) && 2066 ((hw->bus.width <= ixgbe_bus_width_pcie_x4) && 2067 (hw->bus.speed == ixgbe_bus_speed_2500))) { 2068 device_printf(dev, "PCI-Express bandwidth available for this card\n is not sufficient for optimal performance.\n"); 2069 device_printf(dev, "For optimal performance a x8 PCIE, or x4 PCIE Gen2 slot is required.\n"); 2070 } 2071 if ((hw->device_id == IXGBE_DEV_ID_82599_SFP_SF_QP) && 2072 ((hw->bus.width <= ixgbe_bus_width_pcie_x8) && 2073 (hw->bus.speed < ixgbe_bus_speed_8000))) { 2074 device_printf(dev, "PCI-Express bandwidth available for this card\n is not sufficient for optimal performance.\n"); 2075 device_printf(dev, "For optimal performance a x8 PCIE Gen3 slot is required.\n"); 2076 } 2077 } else 2078 device_printf(dev, "Unable to determine slot speed/width. The speed/width reported are that of the internal switch.\n"); 2079 2080 return; 2081 } /* ixgbe_get_slot_info */ 2082 2083 /************************************************************************ 2084 * ixgbe_if_msix_intr_assign 2085 * 2086 * Setup MSI-X Interrupt resources and handlers 2087 ************************************************************************/ 2088 static int 2089 ixgbe_if_msix_intr_assign(if_ctx_t ctx, int msix) 2090 { 2091 struct ixgbe_softc *sc = iflib_get_softc(ctx); 2092 struct ix_rx_queue *rx_que = sc->rx_queues; 2093 struct ix_tx_queue *tx_que; 2094 int error, rid, vector = 0; 2095 char buf[16]; 2096 2097 /* Admin Que is vector 0*/ 2098 rid = vector + 1; 2099 for (int i = 0; i < sc->num_rx_queues; i++, vector++, rx_que++) { 2100 rid = vector + 1; 2101 2102 snprintf(buf, sizeof(buf), "rxq%d", i); 2103 error = iflib_irq_alloc_generic(ctx, &rx_que->que_irq, rid, 2104 IFLIB_INTR_RXTX, ixgbe_msix_que, rx_que, rx_que->rxr.me, buf); 2105 2106 if (error) { 2107 device_printf(iflib_get_dev(ctx), 2108 "Failed to allocate que int %d err: %d", i, error); 2109 sc->num_rx_queues = i + 1; 2110 goto fail; 2111 } 2112 2113 rx_que->msix = vector; 2114 } 2115 for (int i = 0; i < sc->num_tx_queues; i++) { 2116 snprintf(buf, sizeof(buf), "txq%d", i); 2117 tx_que = &sc->tx_queues[i]; 2118 tx_que->msix = i % sc->num_rx_queues; 2119 iflib_softirq_alloc_generic(ctx, 2120 &sc->rx_queues[tx_que->msix].que_irq, 2121 IFLIB_INTR_TX, tx_que, tx_que->txr.me, buf); 2122 } 2123 rid = vector + 1; 2124 error = iflib_irq_alloc_generic(ctx, &sc->irq, rid, 2125 IFLIB_INTR_ADMIN, ixgbe_msix_link, sc, 0, "aq"); 2126 if (error) { 2127 device_printf(iflib_get_dev(ctx), 2128 "Failed to register admin handler"); 2129 return (error); 2130 } 2131 2132 sc->vector = vector; 2133 2134 return (0); 2135 fail: 2136 iflib_irq_free(ctx, &sc->irq); 2137 rx_que = sc->rx_queues; 2138 for (int i = 0; i < sc->num_rx_queues; i++, rx_que++) 2139 iflib_irq_free(ctx, &rx_que->que_irq); 2140 2141 return (error); 2142 } /* ixgbe_if_msix_intr_assign */ 2143 2144 static inline void 2145 ixgbe_perform_aim(struct ixgbe_softc *sc, struct ix_rx_queue *que) 2146 { 2147 uint32_t newitr = 0; 2148 struct rx_ring *rxr = &que->rxr; 2149 2150 /* 2151 * Do Adaptive Interrupt Moderation: 2152 * - Write out last calculated setting 2153 * - Calculate based on average size over 2154 * the last interval. 2155 */ 2156 if (que->eitr_setting) { 2157 IXGBE_WRITE_REG(&sc->hw, IXGBE_EITR(que->msix), 2158 que->eitr_setting); 2159 } 2160 2161 que->eitr_setting = 0; 2162 /* Idle, do nothing */ 2163 if (rxr->bytes == 0) { 2164 return; 2165 } 2166 2167 if ((rxr->bytes) && (rxr->packets)) { 2168 newitr = (rxr->bytes / rxr->packets); 2169 } 2170 2171 newitr += 24; /* account for hardware frame, crc */ 2172 /* set an upper boundary */ 2173 newitr = min(newitr, 3000); 2174 2175 /* Be nice to the mid range */ 2176 if ((newitr > 300) && (newitr < 1200)) { 2177 newitr = (newitr / 3); 2178 } else { 2179 newitr = (newitr / 2); 2180 } 2181 2182 if (sc->hw.mac.type == ixgbe_mac_82598EB) { 2183 newitr |= newitr << 16; 2184 } else { 2185 newitr |= IXGBE_EITR_CNT_WDIS; 2186 } 2187 2188 /* save for next interrupt */ 2189 que->eitr_setting = newitr; 2190 2191 /* Reset state */ 2192 rxr->bytes = 0; 2193 rxr->packets = 0; 2194 2195 return; 2196 } 2197 2198 /********************************************************************* 2199 * ixgbe_msix_que - MSI-X Queue Interrupt Service routine 2200 **********************************************************************/ 2201 static int 2202 ixgbe_msix_que(void *arg) 2203 { 2204 struct ix_rx_queue *que = arg; 2205 struct ixgbe_softc *sc = que->sc; 2206 if_t ifp = iflib_get_ifp(que->sc->ctx); 2207 2208 /* Protect against spurious interrupts */ 2209 if ((if_getdrvflags(ifp) & IFF_DRV_RUNNING) == 0) 2210 return (FILTER_HANDLED); 2211 2212 ixgbe_disable_queue(sc, que->msix); 2213 ++que->irqs; 2214 2215 /* Check for AIM */ 2216 if (sc->enable_aim) { 2217 ixgbe_perform_aim(sc, que); 2218 } 2219 2220 return (FILTER_SCHEDULE_THREAD); 2221 } /* ixgbe_msix_que */ 2222 2223 /************************************************************************ 2224 * ixgbe_media_status - Media Ioctl callback 2225 * 2226 * Called whenever the user queries the status of 2227 * the interface using ifconfig. 2228 ************************************************************************/ 2229 static void 2230 ixgbe_if_media_status(if_ctx_t ctx, struct ifmediareq * ifmr) 2231 { 2232 struct ixgbe_softc *sc = iflib_get_softc(ctx); 2233 struct ixgbe_hw *hw = &sc->hw; 2234 int layer; 2235 2236 INIT_DEBUGOUT("ixgbe_if_media_status: begin"); 2237 2238 ifmr->ifm_status = IFM_AVALID; 2239 ifmr->ifm_active = IFM_ETHER; 2240 2241 if (!sc->link_active) 2242 return; 2243 2244 ifmr->ifm_status |= IFM_ACTIVE; 2245 layer = sc->phy_layer; 2246 2247 if (layer & IXGBE_PHYSICAL_LAYER_10GBASE_T || 2248 layer & IXGBE_PHYSICAL_LAYER_1000BASE_T || 2249 layer & IXGBE_PHYSICAL_LAYER_100BASE_TX || 2250 layer & IXGBE_PHYSICAL_LAYER_10BASE_T) 2251 switch (sc->link_speed) { 2252 case IXGBE_LINK_SPEED_10GB_FULL: 2253 ifmr->ifm_active |= IFM_10G_T | IFM_FDX; 2254 break; 2255 case IXGBE_LINK_SPEED_1GB_FULL: 2256 ifmr->ifm_active |= IFM_1000_T | IFM_FDX; 2257 break; 2258 case IXGBE_LINK_SPEED_100_FULL: 2259 ifmr->ifm_active |= IFM_100_TX | IFM_FDX; 2260 break; 2261 case IXGBE_LINK_SPEED_10_FULL: 2262 ifmr->ifm_active |= IFM_10_T | IFM_FDX; 2263 break; 2264 } 2265 if (hw->mac.type == ixgbe_mac_X550) 2266 switch (sc->link_speed) { 2267 case IXGBE_LINK_SPEED_5GB_FULL: 2268 ifmr->ifm_active |= IFM_5000_T | IFM_FDX; 2269 break; 2270 case IXGBE_LINK_SPEED_2_5GB_FULL: 2271 ifmr->ifm_active |= IFM_2500_T | IFM_FDX; 2272 break; 2273 } 2274 if (layer & IXGBE_PHYSICAL_LAYER_SFP_PLUS_CU || 2275 layer & IXGBE_PHYSICAL_LAYER_SFP_ACTIVE_DA) 2276 switch (sc->link_speed) { 2277 case IXGBE_LINK_SPEED_10GB_FULL: 2278 ifmr->ifm_active |= IFM_10G_TWINAX | IFM_FDX; 2279 break; 2280 } 2281 if (layer & IXGBE_PHYSICAL_LAYER_10GBASE_LR) 2282 switch (sc->link_speed) { 2283 case IXGBE_LINK_SPEED_10GB_FULL: 2284 ifmr->ifm_active |= IFM_10G_LR | IFM_FDX; 2285 break; 2286 case IXGBE_LINK_SPEED_1GB_FULL: 2287 ifmr->ifm_active |= IFM_1000_LX | IFM_FDX; 2288 break; 2289 } 2290 if (layer & IXGBE_PHYSICAL_LAYER_10GBASE_LRM) 2291 switch (sc->link_speed) { 2292 case IXGBE_LINK_SPEED_10GB_FULL: 2293 ifmr->ifm_active |= IFM_10G_LRM | IFM_FDX; 2294 break; 2295 case IXGBE_LINK_SPEED_1GB_FULL: 2296 ifmr->ifm_active |= IFM_1000_LX | IFM_FDX; 2297 break; 2298 } 2299 if (layer & IXGBE_PHYSICAL_LAYER_10GBASE_SR || 2300 layer & IXGBE_PHYSICAL_LAYER_1000BASE_SX) 2301 switch (sc->link_speed) { 2302 case IXGBE_LINK_SPEED_10GB_FULL: 2303 ifmr->ifm_active |= IFM_10G_SR | IFM_FDX; 2304 break; 2305 case IXGBE_LINK_SPEED_1GB_FULL: 2306 ifmr->ifm_active |= IFM_1000_SX | IFM_FDX; 2307 break; 2308 } 2309 if (layer & IXGBE_PHYSICAL_LAYER_10GBASE_CX4) 2310 switch (sc->link_speed) { 2311 case IXGBE_LINK_SPEED_10GB_FULL: 2312 ifmr->ifm_active |= IFM_10G_CX4 | IFM_FDX; 2313 break; 2314 } 2315 /* 2316 * XXX: These need to use the proper media types once 2317 * they're added. 2318 */ 2319 #ifndef IFM_ETH_XTYPE 2320 if (layer & IXGBE_PHYSICAL_LAYER_10GBASE_KR) 2321 switch (sc->link_speed) { 2322 case IXGBE_LINK_SPEED_10GB_FULL: 2323 ifmr->ifm_active |= IFM_10G_SR | IFM_FDX; 2324 break; 2325 case IXGBE_LINK_SPEED_2_5GB_FULL: 2326 ifmr->ifm_active |= IFM_2500_SX | IFM_FDX; 2327 break; 2328 case IXGBE_LINK_SPEED_1GB_FULL: 2329 ifmr->ifm_active |= IFM_1000_CX | IFM_FDX; 2330 break; 2331 } 2332 else if (layer & IXGBE_PHYSICAL_LAYER_10GBASE_KX4 || 2333 layer & IXGBE_PHYSICAL_LAYER_2500BASE_KX || 2334 layer & IXGBE_PHYSICAL_LAYER_1000BASE_KX) 2335 switch (sc->link_speed) { 2336 case IXGBE_LINK_SPEED_10GB_FULL: 2337 ifmr->ifm_active |= IFM_10G_CX4 | IFM_FDX; 2338 break; 2339 case IXGBE_LINK_SPEED_2_5GB_FULL: 2340 ifmr->ifm_active |= IFM_2500_SX | IFM_FDX; 2341 break; 2342 case IXGBE_LINK_SPEED_1GB_FULL: 2343 ifmr->ifm_active |= IFM_1000_CX | IFM_FDX; 2344 break; 2345 } 2346 #else 2347 if (layer & IXGBE_PHYSICAL_LAYER_10GBASE_KR) 2348 switch (sc->link_speed) { 2349 case IXGBE_LINK_SPEED_10GB_FULL: 2350 ifmr->ifm_active |= IFM_10G_KR | IFM_FDX; 2351 break; 2352 case IXGBE_LINK_SPEED_2_5GB_FULL: 2353 ifmr->ifm_active |= IFM_2500_KX | IFM_FDX; 2354 break; 2355 case IXGBE_LINK_SPEED_1GB_FULL: 2356 ifmr->ifm_active |= IFM_1000_KX | IFM_FDX; 2357 break; 2358 } 2359 else if (layer & IXGBE_PHYSICAL_LAYER_10GBASE_KX4 || 2360 layer & IXGBE_PHYSICAL_LAYER_2500BASE_KX || 2361 layer & IXGBE_PHYSICAL_LAYER_1000BASE_KX) 2362 switch (sc->link_speed) { 2363 case IXGBE_LINK_SPEED_10GB_FULL: 2364 ifmr->ifm_active |= IFM_10G_KX4 | IFM_FDX; 2365 break; 2366 case IXGBE_LINK_SPEED_2_5GB_FULL: 2367 ifmr->ifm_active |= IFM_2500_KX | IFM_FDX; 2368 break; 2369 case IXGBE_LINK_SPEED_1GB_FULL: 2370 ifmr->ifm_active |= IFM_1000_KX | IFM_FDX; 2371 break; 2372 } 2373 #endif 2374 2375 /* If nothing is recognized... */ 2376 if (IFM_SUBTYPE(ifmr->ifm_active) == 0) 2377 ifmr->ifm_active |= IFM_UNKNOWN; 2378 2379 /* Display current flow control setting used on link */ 2380 if (hw->fc.current_mode == ixgbe_fc_rx_pause || 2381 hw->fc.current_mode == ixgbe_fc_full) 2382 ifmr->ifm_active |= IFM_ETH_RXPAUSE; 2383 if (hw->fc.current_mode == ixgbe_fc_tx_pause || 2384 hw->fc.current_mode == ixgbe_fc_full) 2385 ifmr->ifm_active |= IFM_ETH_TXPAUSE; 2386 } /* ixgbe_media_status */ 2387 2388 /************************************************************************ 2389 * ixgbe_media_change - Media Ioctl callback 2390 * 2391 * Called when the user changes speed/duplex using 2392 * media/mediopt option with ifconfig. 2393 ************************************************************************/ 2394 static int 2395 ixgbe_if_media_change(if_ctx_t ctx) 2396 { 2397 struct ixgbe_softc *sc = iflib_get_softc(ctx); 2398 struct ifmedia *ifm = iflib_get_media(ctx); 2399 struct ixgbe_hw *hw = &sc->hw; 2400 ixgbe_link_speed speed = 0; 2401 2402 INIT_DEBUGOUT("ixgbe_if_media_change: begin"); 2403 2404 if (IFM_TYPE(ifm->ifm_media) != IFM_ETHER) 2405 return (EINVAL); 2406 2407 if (hw->phy.media_type == ixgbe_media_type_backplane) 2408 return (EPERM); 2409 2410 /* 2411 * We don't actually need to check against the supported 2412 * media types of the adapter; ifmedia will take care of 2413 * that for us. 2414 */ 2415 switch (IFM_SUBTYPE(ifm->ifm_media)) { 2416 case IFM_AUTO: 2417 case IFM_10G_T: 2418 speed |= IXGBE_LINK_SPEED_100_FULL; 2419 speed |= IXGBE_LINK_SPEED_1GB_FULL; 2420 speed |= IXGBE_LINK_SPEED_10GB_FULL; 2421 break; 2422 case IFM_10G_LRM: 2423 case IFM_10G_LR: 2424 #ifndef IFM_ETH_XTYPE 2425 case IFM_10G_SR: /* KR, too */ 2426 case IFM_10G_CX4: /* KX4 */ 2427 #else 2428 case IFM_10G_KR: 2429 case IFM_10G_KX4: 2430 #endif 2431 speed |= IXGBE_LINK_SPEED_1GB_FULL; 2432 speed |= IXGBE_LINK_SPEED_10GB_FULL; 2433 break; 2434 #ifndef IFM_ETH_XTYPE 2435 case IFM_1000_CX: /* KX */ 2436 #else 2437 case IFM_1000_KX: 2438 #endif 2439 case IFM_1000_LX: 2440 case IFM_1000_SX: 2441 speed |= IXGBE_LINK_SPEED_1GB_FULL; 2442 break; 2443 case IFM_1000_T: 2444 speed |= IXGBE_LINK_SPEED_100_FULL; 2445 speed |= IXGBE_LINK_SPEED_1GB_FULL; 2446 break; 2447 case IFM_10G_TWINAX: 2448 speed |= IXGBE_LINK_SPEED_10GB_FULL; 2449 break; 2450 case IFM_5000_T: 2451 speed |= IXGBE_LINK_SPEED_5GB_FULL; 2452 break; 2453 case IFM_2500_T: 2454 speed |= IXGBE_LINK_SPEED_2_5GB_FULL; 2455 break; 2456 case IFM_100_TX: 2457 speed |= IXGBE_LINK_SPEED_100_FULL; 2458 break; 2459 case IFM_10_T: 2460 speed |= IXGBE_LINK_SPEED_10_FULL; 2461 break; 2462 default: 2463 goto invalid; 2464 } 2465 2466 hw->mac.autotry_restart = true; 2467 hw->mac.ops.setup_link(hw, speed, true); 2468 sc->advertise = 2469 ((speed & IXGBE_LINK_SPEED_10GB_FULL) ? 0x4 : 0) | 2470 ((speed & IXGBE_LINK_SPEED_5GB_FULL) ? 0x20 : 0) | 2471 ((speed & IXGBE_LINK_SPEED_2_5GB_FULL) ? 0x10 : 0) | 2472 ((speed & IXGBE_LINK_SPEED_1GB_FULL) ? 0x2 : 0) | 2473 ((speed & IXGBE_LINK_SPEED_100_FULL) ? 0x1 : 0) | 2474 ((speed & IXGBE_LINK_SPEED_10_FULL) ? 0x8 : 0); 2475 2476 return (0); 2477 2478 invalid: 2479 device_printf(iflib_get_dev(ctx), "Invalid media type!\n"); 2480 2481 return (EINVAL); 2482 } /* ixgbe_if_media_change */ 2483 2484 /************************************************************************ 2485 * ixgbe_set_promisc 2486 ************************************************************************/ 2487 static int 2488 ixgbe_if_promisc_set(if_ctx_t ctx, int flags) 2489 { 2490 struct ixgbe_softc *sc = iflib_get_softc(ctx); 2491 if_t ifp = iflib_get_ifp(ctx); 2492 u32 rctl; 2493 int mcnt = 0; 2494 2495 rctl = IXGBE_READ_REG(&sc->hw, IXGBE_FCTRL); 2496 rctl &= (~IXGBE_FCTRL_UPE); 2497 if (if_getflags(ifp) & IFF_ALLMULTI) 2498 mcnt = MAX_NUM_MULTICAST_ADDRESSES; 2499 else { 2500 mcnt = min(if_llmaddr_count(ifp), MAX_NUM_MULTICAST_ADDRESSES); 2501 } 2502 if (mcnt < MAX_NUM_MULTICAST_ADDRESSES) 2503 rctl &= (~IXGBE_FCTRL_MPE); 2504 IXGBE_WRITE_REG(&sc->hw, IXGBE_FCTRL, rctl); 2505 2506 if (if_getflags(ifp) & IFF_PROMISC) { 2507 rctl |= (IXGBE_FCTRL_UPE | IXGBE_FCTRL_MPE); 2508 IXGBE_WRITE_REG(&sc->hw, IXGBE_FCTRL, rctl); 2509 } else if (if_getflags(ifp) & IFF_ALLMULTI) { 2510 rctl |= IXGBE_FCTRL_MPE; 2511 rctl &= ~IXGBE_FCTRL_UPE; 2512 IXGBE_WRITE_REG(&sc->hw, IXGBE_FCTRL, rctl); 2513 } 2514 return (0); 2515 } /* ixgbe_if_promisc_set */ 2516 2517 /************************************************************************ 2518 * ixgbe_msix_link - Link status change ISR (MSI/MSI-X) 2519 ************************************************************************/ 2520 static int 2521 ixgbe_msix_link(void *arg) 2522 { 2523 struct ixgbe_softc *sc = arg; 2524 struct ixgbe_hw *hw = &sc->hw; 2525 u32 eicr, eicr_mask; 2526 s32 retval; 2527 2528 ++sc->link_irq; 2529 2530 /* Pause other interrupts */ 2531 IXGBE_WRITE_REG(hw, IXGBE_EIMC, IXGBE_EIMC_OTHER); 2532 2533 /* First get the cause */ 2534 eicr = IXGBE_READ_REG(hw, IXGBE_EICS); 2535 /* Be sure the queue bits are not cleared */ 2536 eicr &= ~IXGBE_EICR_RTX_QUEUE; 2537 /* Clear interrupt with write */ 2538 IXGBE_WRITE_REG(hw, IXGBE_EICR, eicr); 2539 2540 /* Link status change */ 2541 if (eicr & IXGBE_EICR_LSC) { 2542 IXGBE_WRITE_REG(hw, IXGBE_EIMC, IXGBE_EIMC_LSC); 2543 sc->task_requests |= IXGBE_REQUEST_TASK_LSC; 2544 } 2545 2546 if (sc->hw.mac.type != ixgbe_mac_82598EB) { 2547 if ((sc->feat_en & IXGBE_FEATURE_FDIR) && 2548 (eicr & IXGBE_EICR_FLOW_DIR)) { 2549 /* This is probably overkill :) */ 2550 if (!atomic_cmpset_int(&sc->fdir_reinit, 0, 1)) 2551 return (FILTER_HANDLED); 2552 /* Disable the interrupt */ 2553 IXGBE_WRITE_REG(hw, IXGBE_EIMC, IXGBE_EICR_FLOW_DIR); 2554 sc->task_requests |= IXGBE_REQUEST_TASK_FDIR; 2555 } else 2556 if (eicr & IXGBE_EICR_ECC) { 2557 device_printf(iflib_get_dev(sc->ctx), 2558 "Received ECC Err, initiating reset\n"); 2559 hw->mac.flags |= ~IXGBE_FLAGS_DOUBLE_RESET_REQUIRED; 2560 ixgbe_reset_hw(hw); 2561 IXGBE_WRITE_REG(hw, IXGBE_EICR, IXGBE_EICR_ECC); 2562 } 2563 2564 /* Check for over temp condition */ 2565 if (sc->feat_en & IXGBE_FEATURE_TEMP_SENSOR) { 2566 switch (sc->hw.mac.type) { 2567 case ixgbe_mac_X550EM_a: 2568 if (!(eicr & IXGBE_EICR_GPI_SDP0_X550EM_a)) 2569 break; 2570 IXGBE_WRITE_REG(hw, IXGBE_EIMC, 2571 IXGBE_EICR_GPI_SDP0_X550EM_a); 2572 IXGBE_WRITE_REG(hw, IXGBE_EICR, 2573 IXGBE_EICR_GPI_SDP0_X550EM_a); 2574 retval = hw->phy.ops.check_overtemp(hw); 2575 if (retval != IXGBE_ERR_OVERTEMP) 2576 break; 2577 device_printf(iflib_get_dev(sc->ctx), 2578 "\nCRITICAL: OVER TEMP!! PHY IS SHUT DOWN!!\n"); 2579 device_printf(iflib_get_dev(sc->ctx), 2580 "System shutdown required!\n"); 2581 break; 2582 default: 2583 if (!(eicr & IXGBE_EICR_TS)) 2584 break; 2585 retval = hw->phy.ops.check_overtemp(hw); 2586 if (retval != IXGBE_ERR_OVERTEMP) 2587 break; 2588 device_printf(iflib_get_dev(sc->ctx), 2589 "\nCRITICAL: OVER TEMP!! PHY IS SHUT DOWN!!\n"); 2590 device_printf(iflib_get_dev(sc->ctx), 2591 "System shutdown required!\n"); 2592 IXGBE_WRITE_REG(hw, IXGBE_EICR, IXGBE_EICR_TS); 2593 break; 2594 } 2595 } 2596 2597 /* Check for VF message */ 2598 if ((sc->feat_en & IXGBE_FEATURE_SRIOV) && 2599 (eicr & IXGBE_EICR_MAILBOX)) 2600 sc->task_requests |= IXGBE_REQUEST_TASK_MBX; 2601 } 2602 2603 if (ixgbe_is_sfp(hw)) { 2604 /* Pluggable optics-related interrupt */ 2605 if (hw->mac.type >= ixgbe_mac_X540) 2606 eicr_mask = IXGBE_EICR_GPI_SDP0_X540; 2607 else 2608 eicr_mask = IXGBE_EICR_GPI_SDP2_BY_MAC(hw); 2609 2610 if (eicr & eicr_mask) { 2611 IXGBE_WRITE_REG(hw, IXGBE_EICR, eicr_mask); 2612 sc->task_requests |= IXGBE_REQUEST_TASK_MOD; 2613 } 2614 2615 if ((hw->mac.type == ixgbe_mac_82599EB) && 2616 (eicr & IXGBE_EICR_GPI_SDP1_BY_MAC(hw))) { 2617 IXGBE_WRITE_REG(hw, IXGBE_EICR, 2618 IXGBE_EICR_GPI_SDP1_BY_MAC(hw)); 2619 sc->task_requests |= IXGBE_REQUEST_TASK_MSF; 2620 } 2621 } 2622 2623 /* Check for fan failure */ 2624 if (sc->feat_en & IXGBE_FEATURE_FAN_FAIL) { 2625 ixgbe_check_fan_failure(sc, eicr, true); 2626 IXGBE_WRITE_REG(hw, IXGBE_EICR, IXGBE_EICR_GPI_SDP1_BY_MAC(hw)); 2627 } 2628 2629 /* External PHY interrupt */ 2630 if ((hw->phy.type == ixgbe_phy_x550em_ext_t) && 2631 (eicr & IXGBE_EICR_GPI_SDP0_X540)) { 2632 IXGBE_WRITE_REG(hw, IXGBE_EICR, IXGBE_EICR_GPI_SDP0_X540); 2633 sc->task_requests |= IXGBE_REQUEST_TASK_PHY; 2634 } 2635 2636 return (sc->task_requests != 0) ? FILTER_SCHEDULE_THREAD : FILTER_HANDLED; 2637 } /* ixgbe_msix_link */ 2638 2639 /************************************************************************ 2640 * ixgbe_sysctl_interrupt_rate_handler 2641 ************************************************************************/ 2642 static int 2643 ixgbe_sysctl_interrupt_rate_handler(SYSCTL_HANDLER_ARGS) 2644 { 2645 struct ix_rx_queue *que = ((struct ix_rx_queue *)oidp->oid_arg1); 2646 int error; 2647 unsigned int reg, usec, rate; 2648 2649 reg = IXGBE_READ_REG(&que->sc->hw, IXGBE_EITR(que->msix)); 2650 usec = ((reg & 0x0FF8) >> 3); 2651 if (usec > 0) 2652 rate = 500000 / usec; 2653 else 2654 rate = 0; 2655 error = sysctl_handle_int(oidp, &rate, 0, req); 2656 if (error || !req->newptr) 2657 return error; 2658 reg &= ~0xfff; /* default, no limitation */ 2659 ixgbe_max_interrupt_rate = 0; 2660 if (rate > 0 && rate < 500000) { 2661 if (rate < 1000) 2662 rate = 1000; 2663 ixgbe_max_interrupt_rate = rate; 2664 reg |= ((4000000/rate) & 0xff8); 2665 } 2666 IXGBE_WRITE_REG(&que->sc->hw, IXGBE_EITR(que->msix), reg); 2667 2668 return (0); 2669 } /* ixgbe_sysctl_interrupt_rate_handler */ 2670 2671 /************************************************************************ 2672 * ixgbe_add_device_sysctls 2673 ************************************************************************/ 2674 static void 2675 ixgbe_add_device_sysctls(if_ctx_t ctx) 2676 { 2677 struct ixgbe_softc *sc = iflib_get_softc(ctx); 2678 device_t dev = iflib_get_dev(ctx); 2679 struct ixgbe_hw *hw = &sc->hw; 2680 struct sysctl_oid_list *child; 2681 struct sysctl_ctx_list *ctx_list; 2682 2683 ctx_list = device_get_sysctl_ctx(dev); 2684 child = SYSCTL_CHILDREN(device_get_sysctl_tree(dev)); 2685 2686 /* Sysctls for all devices */ 2687 SYSCTL_ADD_PROC(ctx_list, child, OID_AUTO, "fc", 2688 CTLTYPE_INT | CTLFLAG_RW | CTLFLAG_NEEDGIANT, 2689 sc, 0, ixgbe_sysctl_flowcntl, "I", 2690 IXGBE_SYSCTL_DESC_SET_FC); 2691 2692 SYSCTL_ADD_PROC(ctx_list, child, OID_AUTO, "advertise_speed", 2693 CTLTYPE_INT | CTLFLAG_RW | CTLFLAG_NEEDGIANT, 2694 sc, 0, ixgbe_sysctl_advertise, "I", 2695 IXGBE_SYSCTL_DESC_ADV_SPEED); 2696 2697 sc->enable_aim = ixgbe_enable_aim; 2698 SYSCTL_ADD_INT(ctx_list, child, OID_AUTO, "enable_aim", CTLFLAG_RW, 2699 &sc->enable_aim, 0, "Interrupt Moderation"); 2700 2701 SYSCTL_ADD_PROC(ctx_list, child, OID_AUTO, "fw_version", 2702 CTLTYPE_STRING | CTLFLAG_RD | CTLFLAG_NEEDGIANT, sc, 0, 2703 ixgbe_sysctl_print_fw_version, "A", "Prints FW/NVM Versions"); 2704 2705 #ifdef IXGBE_DEBUG 2706 /* testing sysctls (for all devices) */ 2707 SYSCTL_ADD_PROC(ctx_list, child, OID_AUTO, "power_state", 2708 CTLTYPE_INT | CTLFLAG_RW | CTLFLAG_NEEDGIANT, 2709 sc, 0, ixgbe_sysctl_power_state, 2710 "I", "PCI Power State"); 2711 2712 SYSCTL_ADD_PROC(ctx_list, child, OID_AUTO, "print_rss_config", 2713 CTLTYPE_STRING | CTLFLAG_RD | CTLFLAG_NEEDGIANT, sc, 0, 2714 ixgbe_sysctl_print_rss_config, "A", "Prints RSS Configuration"); 2715 #endif 2716 /* for X550 series devices */ 2717 if (hw->mac.type >= ixgbe_mac_X550) 2718 SYSCTL_ADD_PROC(ctx_list, child, OID_AUTO, "dmac", 2719 CTLTYPE_U16 | CTLFLAG_RW | CTLFLAG_NEEDGIANT, 2720 sc, 0, ixgbe_sysctl_dmac, 2721 "I", "DMA Coalesce"); 2722 2723 /* for WoL-capable devices */ 2724 if (hw->device_id == IXGBE_DEV_ID_X550EM_X_10G_T) { 2725 SYSCTL_ADD_PROC(ctx_list, child, OID_AUTO, "wol_enable", 2726 CTLTYPE_INT | CTLFLAG_RW | CTLFLAG_NEEDGIANT, sc, 0, 2727 ixgbe_sysctl_wol_enable, "I", "Enable/Disable Wake on LAN"); 2728 2729 SYSCTL_ADD_PROC(ctx_list, child, OID_AUTO, "wufc", 2730 CTLTYPE_U32 | CTLFLAG_RW | CTLFLAG_NEEDGIANT, 2731 sc, 0, ixgbe_sysctl_wufc, 2732 "I", "Enable/Disable Wake Up Filters"); 2733 } 2734 2735 /* for X552/X557-AT devices */ 2736 if (hw->device_id == IXGBE_DEV_ID_X550EM_X_10G_T) { 2737 struct sysctl_oid *phy_node; 2738 struct sysctl_oid_list *phy_list; 2739 2740 phy_node = SYSCTL_ADD_NODE(ctx_list, child, OID_AUTO, "phy", 2741 CTLFLAG_RD | CTLFLAG_MPSAFE, NULL, "External PHY sysctls"); 2742 phy_list = SYSCTL_CHILDREN(phy_node); 2743 2744 SYSCTL_ADD_PROC(ctx_list, phy_list, OID_AUTO, "temp", 2745 CTLTYPE_U16 | CTLFLAG_RD | CTLFLAG_NEEDGIANT, 2746 sc, 0, ixgbe_sysctl_phy_temp, 2747 "I", "Current External PHY Temperature (Celsius)"); 2748 2749 SYSCTL_ADD_PROC(ctx_list, phy_list, OID_AUTO, 2750 "overtemp_occurred", 2751 CTLTYPE_U16 | CTLFLAG_RD | CTLFLAG_NEEDGIANT, sc, 0, 2752 ixgbe_sysctl_phy_overtemp_occurred, "I", 2753 "External PHY High Temperature Event Occurred"); 2754 } 2755 2756 if (sc->feat_cap & IXGBE_FEATURE_EEE) { 2757 SYSCTL_ADD_PROC(ctx_list, child, OID_AUTO, "eee_state", 2758 CTLTYPE_INT | CTLFLAG_RW | CTLFLAG_NEEDGIANT, sc, 0, 2759 ixgbe_sysctl_eee_state, "I", "EEE Power Save State"); 2760 } 2761 } /* ixgbe_add_device_sysctls */ 2762 2763 /************************************************************************ 2764 * ixgbe_allocate_pci_resources 2765 ************************************************************************/ 2766 static int 2767 ixgbe_allocate_pci_resources(if_ctx_t ctx) 2768 { 2769 struct ixgbe_softc *sc = iflib_get_softc(ctx); 2770 device_t dev = iflib_get_dev(ctx); 2771 int rid; 2772 2773 rid = PCIR_BAR(0); 2774 sc->pci_mem = bus_alloc_resource_any(dev, SYS_RES_MEMORY, &rid, 2775 RF_ACTIVE); 2776 2777 if (!(sc->pci_mem)) { 2778 device_printf(dev, "Unable to allocate bus resource: memory\n"); 2779 return (ENXIO); 2780 } 2781 2782 /* Save bus_space values for READ/WRITE_REG macros */ 2783 sc->osdep.mem_bus_space_tag = rman_get_bustag(sc->pci_mem); 2784 sc->osdep.mem_bus_space_handle = 2785 rman_get_bushandle(sc->pci_mem); 2786 /* Set hw values for shared code */ 2787 sc->hw.hw_addr = (u8 *)&sc->osdep.mem_bus_space_handle; 2788 2789 return (0); 2790 } /* ixgbe_allocate_pci_resources */ 2791 2792 /************************************************************************ 2793 * ixgbe_detach - Device removal routine 2794 * 2795 * Called when the driver is being removed. 2796 * Stops the adapter and deallocates all the resources 2797 * that were allocated for driver operation. 2798 * 2799 * return 0 on success, positive on failure 2800 ************************************************************************/ 2801 static int 2802 ixgbe_if_detach(if_ctx_t ctx) 2803 { 2804 struct ixgbe_softc *sc = iflib_get_softc(ctx); 2805 device_t dev = iflib_get_dev(ctx); 2806 u32 ctrl_ext; 2807 2808 INIT_DEBUGOUT("ixgbe_detach: begin"); 2809 2810 if (ixgbe_pci_iov_detach(dev) != 0) { 2811 device_printf(dev, "SR-IOV in use; detach first.\n"); 2812 return (EBUSY); 2813 } 2814 2815 ixgbe_setup_low_power_mode(ctx); 2816 2817 /* let hardware know driver is unloading */ 2818 ctrl_ext = IXGBE_READ_REG(&sc->hw, IXGBE_CTRL_EXT); 2819 ctrl_ext &= ~IXGBE_CTRL_EXT_DRV_LOAD; 2820 IXGBE_WRITE_REG(&sc->hw, IXGBE_CTRL_EXT, ctrl_ext); 2821 2822 ixgbe_free_pci_resources(ctx); 2823 free(sc->mta, M_IXGBE); 2824 2825 return (0); 2826 } /* ixgbe_if_detach */ 2827 2828 /************************************************************************ 2829 * ixgbe_setup_low_power_mode - LPLU/WoL preparation 2830 * 2831 * Prepare the adapter/port for LPLU and/or WoL 2832 ************************************************************************/ 2833 static int 2834 ixgbe_setup_low_power_mode(if_ctx_t ctx) 2835 { 2836 struct ixgbe_softc *sc = iflib_get_softc(ctx); 2837 struct ixgbe_hw *hw = &sc->hw; 2838 device_t dev = iflib_get_dev(ctx); 2839 s32 error = 0; 2840 2841 if (!hw->wol_enabled) 2842 ixgbe_set_phy_power(hw, false); 2843 2844 /* Limit power management flow to X550EM baseT */ 2845 if (hw->device_id == IXGBE_DEV_ID_X550EM_X_10G_T && 2846 hw->phy.ops.enter_lplu) { 2847 /* Turn off support for APM wakeup. (Using ACPI instead) */ 2848 IXGBE_WRITE_REG(hw, IXGBE_GRC, 2849 IXGBE_READ_REG(hw, IXGBE_GRC) & ~(u32)2); 2850 2851 /* 2852 * Clear Wake Up Status register to prevent any previous wakeup 2853 * events from waking us up immediately after we suspend. 2854 */ 2855 IXGBE_WRITE_REG(hw, IXGBE_WUS, 0xffffffff); 2856 2857 /* 2858 * Program the Wakeup Filter Control register with user filter 2859 * settings 2860 */ 2861 IXGBE_WRITE_REG(hw, IXGBE_WUFC, sc->wufc); 2862 2863 /* Enable wakeups and power management in Wakeup Control */ 2864 IXGBE_WRITE_REG(hw, IXGBE_WUC, 2865 IXGBE_WUC_WKEN | IXGBE_WUC_PME_EN); 2866 2867 /* X550EM baseT adapters need a special LPLU flow */ 2868 hw->phy.reset_disable = true; 2869 ixgbe_if_stop(ctx); 2870 error = hw->phy.ops.enter_lplu(hw); 2871 if (error) 2872 device_printf(dev, "Error entering LPLU: %d\n", error); 2873 hw->phy.reset_disable = false; 2874 } else { 2875 /* Just stop for other adapters */ 2876 ixgbe_if_stop(ctx); 2877 } 2878 2879 return error; 2880 } /* ixgbe_setup_low_power_mode */ 2881 2882 /************************************************************************ 2883 * ixgbe_shutdown - Shutdown entry point 2884 ************************************************************************/ 2885 static int 2886 ixgbe_if_shutdown(if_ctx_t ctx) 2887 { 2888 int error = 0; 2889 2890 INIT_DEBUGOUT("ixgbe_shutdown: begin"); 2891 2892 error = ixgbe_setup_low_power_mode(ctx); 2893 2894 return (error); 2895 } /* ixgbe_if_shutdown */ 2896 2897 /************************************************************************ 2898 * ixgbe_suspend 2899 * 2900 * From D0 to D3 2901 ************************************************************************/ 2902 static int 2903 ixgbe_if_suspend(if_ctx_t ctx) 2904 { 2905 int error = 0; 2906 2907 INIT_DEBUGOUT("ixgbe_suspend: begin"); 2908 2909 error = ixgbe_setup_low_power_mode(ctx); 2910 2911 return (error); 2912 } /* ixgbe_if_suspend */ 2913 2914 /************************************************************************ 2915 * ixgbe_resume 2916 * 2917 * From D3 to D0 2918 ************************************************************************/ 2919 static int 2920 ixgbe_if_resume(if_ctx_t ctx) 2921 { 2922 struct ixgbe_softc *sc = iflib_get_softc(ctx); 2923 device_t dev = iflib_get_dev(ctx); 2924 if_t ifp = iflib_get_ifp(ctx); 2925 struct ixgbe_hw *hw = &sc->hw; 2926 u32 wus; 2927 2928 INIT_DEBUGOUT("ixgbe_resume: begin"); 2929 2930 /* Read & clear WUS register */ 2931 wus = IXGBE_READ_REG(hw, IXGBE_WUS); 2932 if (wus) 2933 device_printf(dev, "Woken up by (WUS): %#010x\n", 2934 IXGBE_READ_REG(hw, IXGBE_WUS)); 2935 IXGBE_WRITE_REG(hw, IXGBE_WUS, 0xffffffff); 2936 /* And clear WUFC until next low-power transition */ 2937 IXGBE_WRITE_REG(hw, IXGBE_WUFC, 0); 2938 2939 /* 2940 * Required after D3->D0 transition; 2941 * will re-advertise all previous advertised speeds 2942 */ 2943 if (if_getflags(ifp) & IFF_UP) 2944 ixgbe_if_init(ctx); 2945 2946 return (0); 2947 } /* ixgbe_if_resume */ 2948 2949 /************************************************************************ 2950 * ixgbe_if_mtu_set - Ioctl mtu entry point 2951 * 2952 * Return 0 on success, EINVAL on failure 2953 ************************************************************************/ 2954 static int 2955 ixgbe_if_mtu_set(if_ctx_t ctx, uint32_t mtu) 2956 { 2957 struct ixgbe_softc *sc = iflib_get_softc(ctx); 2958 int error = 0; 2959 2960 IOCTL_DEBUGOUT("ioctl: SIOCIFMTU (Set Interface MTU)"); 2961 2962 if (mtu > IXGBE_MAX_MTU) { 2963 error = EINVAL; 2964 } else { 2965 sc->max_frame_size = mtu + IXGBE_MTU_HDR; 2966 } 2967 2968 return error; 2969 } /* ixgbe_if_mtu_set */ 2970 2971 /************************************************************************ 2972 * ixgbe_if_crcstrip_set 2973 ************************************************************************/ 2974 static void 2975 ixgbe_if_crcstrip_set(if_ctx_t ctx, int onoff, int crcstrip) 2976 { 2977 struct ixgbe_softc *sc = iflib_get_softc(ctx); 2978 struct ixgbe_hw *hw = &sc->hw; 2979 /* crc stripping is set in two places: 2980 * IXGBE_HLREG0 (modified on init_locked and hw reset) 2981 * IXGBE_RDRXCTL (set by the original driver in 2982 * ixgbe_setup_hw_rsc() called in init_locked. 2983 * We disable the setting when netmap is compiled in). 2984 * We update the values here, but also in ixgbe.c because 2985 * init_locked sometimes is called outside our control. 2986 */ 2987 uint32_t hl, rxc; 2988 2989 hl = IXGBE_READ_REG(hw, IXGBE_HLREG0); 2990 rxc = IXGBE_READ_REG(hw, IXGBE_RDRXCTL); 2991 #ifdef NETMAP 2992 if (netmap_verbose) 2993 D("%s read HLREG 0x%x rxc 0x%x", 2994 onoff ? "enter" : "exit", hl, rxc); 2995 #endif 2996 /* hw requirements ... */ 2997 rxc &= ~IXGBE_RDRXCTL_RSCFRSTSIZE; 2998 rxc |= IXGBE_RDRXCTL_RSCACKC; 2999 if (onoff && !crcstrip) { 3000 /* keep the crc. Fast rx */ 3001 hl &= ~IXGBE_HLREG0_RXCRCSTRP; 3002 rxc &= ~IXGBE_RDRXCTL_CRCSTRIP; 3003 } else { 3004 /* reset default mode */ 3005 hl |= IXGBE_HLREG0_RXCRCSTRP; 3006 rxc |= IXGBE_RDRXCTL_CRCSTRIP; 3007 } 3008 #ifdef NETMAP 3009 if (netmap_verbose) 3010 D("%s write HLREG 0x%x rxc 0x%x", 3011 onoff ? "enter" : "exit", hl, rxc); 3012 #endif 3013 IXGBE_WRITE_REG(hw, IXGBE_HLREG0, hl); 3014 IXGBE_WRITE_REG(hw, IXGBE_RDRXCTL, rxc); 3015 } /* ixgbe_if_crcstrip_set */ 3016 3017 /********************************************************************* 3018 * ixgbe_if_init - Init entry point 3019 * 3020 * Used in two ways: It is used by the stack as an init 3021 * entry point in network interface structure. It is also 3022 * used by the driver as a hw/sw initialization routine to 3023 * get to a consistent state. 3024 * 3025 * Return 0 on success, positive on failure 3026 **********************************************************************/ 3027 void 3028 ixgbe_if_init(if_ctx_t ctx) 3029 { 3030 struct ixgbe_softc *sc = iflib_get_softc(ctx); 3031 if_t ifp = iflib_get_ifp(ctx); 3032 device_t dev = iflib_get_dev(ctx); 3033 struct ixgbe_hw *hw = &sc->hw; 3034 struct ix_rx_queue *rx_que; 3035 struct ix_tx_queue *tx_que; 3036 u32 txdctl, mhadd; 3037 u32 rxdctl, rxctrl; 3038 u32 ctrl_ext; 3039 3040 int i, j, err; 3041 3042 INIT_DEBUGOUT("ixgbe_if_init: begin"); 3043 3044 /* Queue indices may change with IOV mode */ 3045 ixgbe_align_all_queue_indices(sc); 3046 3047 /* reprogram the RAR[0] in case user changed it. */ 3048 ixgbe_set_rar(hw, 0, hw->mac.addr, sc->pool, IXGBE_RAH_AV); 3049 3050 /* Get the latest mac address, User can use a LAA */ 3051 bcopy(if_getlladdr(ifp), hw->mac.addr, IXGBE_ETH_LENGTH_OF_ADDRESS); 3052 ixgbe_set_rar(hw, 0, hw->mac.addr, sc->pool, 1); 3053 hw->addr_ctrl.rar_used_count = 1; 3054 3055 ixgbe_init_hw(hw); 3056 3057 ixgbe_initialize_iov(sc); 3058 3059 ixgbe_initialize_transmit_units(ctx); 3060 3061 /* Setup Multicast table */ 3062 ixgbe_if_multi_set(ctx); 3063 3064 /* Determine the correct mbuf pool, based on frame size */ 3065 sc->rx_mbuf_sz = iflib_get_rx_mbuf_sz(ctx); 3066 3067 /* Configure RX settings */ 3068 ixgbe_initialize_receive_units(ctx); 3069 3070 /* 3071 * Initialize variable holding task enqueue requests 3072 * from MSI-X interrupts 3073 */ 3074 sc->task_requests = 0; 3075 3076 /* Enable SDP & MSI-X interrupts based on adapter */ 3077 ixgbe_config_gpie(sc); 3078 3079 /* Set MTU size */ 3080 if (if_getmtu(ifp) > ETHERMTU) { 3081 /* aka IXGBE_MAXFRS on 82599 and newer */ 3082 mhadd = IXGBE_READ_REG(hw, IXGBE_MHADD); 3083 mhadd &= ~IXGBE_MHADD_MFS_MASK; 3084 mhadd |= sc->max_frame_size << IXGBE_MHADD_MFS_SHIFT; 3085 IXGBE_WRITE_REG(hw, IXGBE_MHADD, mhadd); 3086 } 3087 3088 /* Now enable all the queues */ 3089 for (i = 0, tx_que = sc->tx_queues; i < sc->num_tx_queues; i++, tx_que++) { 3090 struct tx_ring *txr = &tx_que->txr; 3091 3092 txdctl = IXGBE_READ_REG(hw, IXGBE_TXDCTL(txr->me)); 3093 txdctl |= IXGBE_TXDCTL_ENABLE; 3094 /* Set WTHRESH to 8, burst writeback */ 3095 txdctl |= (8 << 16); 3096 /* 3097 * When the internal queue falls below PTHRESH (32), 3098 * start prefetching as long as there are at least 3099 * HTHRESH (1) buffers ready. The values are taken 3100 * from the Intel linux driver 3.8.21. 3101 * Prefetching enables tx line rate even with 1 queue. 3102 */ 3103 txdctl |= (32 << 0) | (1 << 8); 3104 IXGBE_WRITE_REG(hw, IXGBE_TXDCTL(txr->me), txdctl); 3105 } 3106 3107 for (i = 0, rx_que = sc->rx_queues; i < sc->num_rx_queues; i++, rx_que++) { 3108 struct rx_ring *rxr = &rx_que->rxr; 3109 3110 rxdctl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(rxr->me)); 3111 if (hw->mac.type == ixgbe_mac_82598EB) { 3112 /* 3113 * PTHRESH = 21 3114 * HTHRESH = 4 3115 * WTHRESH = 8 3116 */ 3117 rxdctl &= ~0x3FFFFF; 3118 rxdctl |= 0x080420; 3119 } 3120 rxdctl |= IXGBE_RXDCTL_ENABLE; 3121 IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(rxr->me), rxdctl); 3122 for (j = 0; j < 10; j++) { 3123 if (IXGBE_READ_REG(hw, IXGBE_RXDCTL(rxr->me)) & 3124 IXGBE_RXDCTL_ENABLE) 3125 break; 3126 else 3127 msec_delay(1); 3128 } 3129 wmb(); 3130 } 3131 3132 /* Enable Receive engine */ 3133 rxctrl = IXGBE_READ_REG(hw, IXGBE_RXCTRL); 3134 if (hw->mac.type == ixgbe_mac_82598EB) 3135 rxctrl |= IXGBE_RXCTRL_DMBYPS; 3136 rxctrl |= IXGBE_RXCTRL_RXEN; 3137 ixgbe_enable_rx_dma(hw, rxctrl); 3138 3139 /* Set up MSI/MSI-X routing */ 3140 if (ixgbe_enable_msix) { 3141 ixgbe_configure_ivars(sc); 3142 /* Set up auto-mask */ 3143 if (hw->mac.type == ixgbe_mac_82598EB) 3144 IXGBE_WRITE_REG(hw, IXGBE_EIAM, IXGBE_EICS_RTX_QUEUE); 3145 else { 3146 IXGBE_WRITE_REG(hw, IXGBE_EIAM_EX(0), 0xFFFFFFFF); 3147 IXGBE_WRITE_REG(hw, IXGBE_EIAM_EX(1), 0xFFFFFFFF); 3148 } 3149 } else { /* Simple settings for Legacy/MSI */ 3150 ixgbe_set_ivar(sc, 0, 0, 0); 3151 ixgbe_set_ivar(sc, 0, 0, 1); 3152 IXGBE_WRITE_REG(hw, IXGBE_EIAM, IXGBE_EICS_RTX_QUEUE); 3153 } 3154 3155 ixgbe_init_fdir(sc); 3156 3157 /* 3158 * Check on any SFP devices that 3159 * need to be kick-started 3160 */ 3161 if (hw->phy.type == ixgbe_phy_none) { 3162 err = hw->phy.ops.identify(hw); 3163 if (err == IXGBE_ERR_SFP_NOT_SUPPORTED) { 3164 device_printf(dev, 3165 "Unsupported SFP+ module type was detected.\n"); 3166 return; 3167 } 3168 } 3169 3170 /* Set moderation on the Link interrupt */ 3171 IXGBE_WRITE_REG(hw, IXGBE_EITR(sc->vector), IXGBE_LINK_ITR); 3172 3173 /* Enable power to the phy. */ 3174 ixgbe_set_phy_power(hw, true); 3175 3176 /* Config/Enable Link */ 3177 ixgbe_config_link(ctx); 3178 3179 /* Hardware Packet Buffer & Flow Control setup */ 3180 ixgbe_config_delay_values(sc); 3181 3182 /* Initialize the FC settings */ 3183 ixgbe_start_hw(hw); 3184 3185 /* Set up VLAN support and filter */ 3186 ixgbe_setup_vlan_hw_support(ctx); 3187 3188 /* Setup DMA Coalescing */ 3189 ixgbe_config_dmac(sc); 3190 3191 /* And now turn on interrupts */ 3192 ixgbe_if_enable_intr(ctx); 3193 3194 /* Enable the use of the MBX by the VF's */ 3195 if (sc->feat_en & IXGBE_FEATURE_SRIOV) { 3196 ctrl_ext = IXGBE_READ_REG(hw, IXGBE_CTRL_EXT); 3197 ctrl_ext |= IXGBE_CTRL_EXT_PFRSTD; 3198 IXGBE_WRITE_REG(hw, IXGBE_CTRL_EXT, ctrl_ext); 3199 } 3200 3201 } /* ixgbe_init_locked */ 3202 3203 /************************************************************************ 3204 * ixgbe_set_ivar 3205 * 3206 * Setup the correct IVAR register for a particular MSI-X interrupt 3207 * (yes this is all very magic and confusing :) 3208 * - entry is the register array entry 3209 * - vector is the MSI-X vector for this queue 3210 * - type is RX/TX/MISC 3211 ************************************************************************/ 3212 static void 3213 ixgbe_set_ivar(struct ixgbe_softc *sc, u8 entry, u8 vector, s8 type) 3214 { 3215 struct ixgbe_hw *hw = &sc->hw; 3216 u32 ivar, index; 3217 3218 vector |= IXGBE_IVAR_ALLOC_VAL; 3219 3220 switch (hw->mac.type) { 3221 case ixgbe_mac_82598EB: 3222 if (type == -1) 3223 entry = IXGBE_IVAR_OTHER_CAUSES_INDEX; 3224 else 3225 entry += (type * 64); 3226 index = (entry >> 2) & 0x1F; 3227 ivar = IXGBE_READ_REG(hw, IXGBE_IVAR(index)); 3228 ivar &= ~(0xFF << (8 * (entry & 0x3))); 3229 ivar |= (vector << (8 * (entry & 0x3))); 3230 IXGBE_WRITE_REG(&sc->hw, IXGBE_IVAR(index), ivar); 3231 break; 3232 case ixgbe_mac_82599EB: 3233 case ixgbe_mac_X540: 3234 case ixgbe_mac_X550: 3235 case ixgbe_mac_X550EM_x: 3236 case ixgbe_mac_X550EM_a: 3237 if (type == -1) { /* MISC IVAR */ 3238 index = (entry & 1) * 8; 3239 ivar = IXGBE_READ_REG(hw, IXGBE_IVAR_MISC); 3240 ivar &= ~(0xFF << index); 3241 ivar |= (vector << index); 3242 IXGBE_WRITE_REG(hw, IXGBE_IVAR_MISC, ivar); 3243 } else { /* RX/TX IVARS */ 3244 index = (16 * (entry & 1)) + (8 * type); 3245 ivar = IXGBE_READ_REG(hw, IXGBE_IVAR(entry >> 1)); 3246 ivar &= ~(0xFF << index); 3247 ivar |= (vector << index); 3248 IXGBE_WRITE_REG(hw, IXGBE_IVAR(entry >> 1), ivar); 3249 } 3250 default: 3251 break; 3252 } 3253 } /* ixgbe_set_ivar */ 3254 3255 /************************************************************************ 3256 * ixgbe_configure_ivars 3257 ************************************************************************/ 3258 static void 3259 ixgbe_configure_ivars(struct ixgbe_softc *sc) 3260 { 3261 struct ix_rx_queue *rx_que = sc->rx_queues; 3262 struct ix_tx_queue *tx_que = sc->tx_queues; 3263 u32 newitr; 3264 3265 if (ixgbe_max_interrupt_rate > 0) 3266 newitr = (4000000 / ixgbe_max_interrupt_rate) & 0x0FF8; 3267 else { 3268 /* 3269 * Disable DMA coalescing if interrupt moderation is 3270 * disabled. 3271 */ 3272 sc->dmac = 0; 3273 newitr = 0; 3274 } 3275 3276 for (int i = 0; i < sc->num_rx_queues; i++, rx_que++) { 3277 struct rx_ring *rxr = &rx_que->rxr; 3278 3279 /* First the RX queue entry */ 3280 ixgbe_set_ivar(sc, rxr->me, rx_que->msix, 0); 3281 3282 /* Set an Initial EITR value */ 3283 IXGBE_WRITE_REG(&sc->hw, IXGBE_EITR(rx_que->msix), newitr); 3284 } 3285 for (int i = 0; i < sc->num_tx_queues; i++, tx_que++) { 3286 struct tx_ring *txr = &tx_que->txr; 3287 3288 /* ... and the TX */ 3289 ixgbe_set_ivar(sc, txr->me, tx_que->msix, 1); 3290 } 3291 /* For the Link interrupt */ 3292 ixgbe_set_ivar(sc, 1, sc->vector, -1); 3293 } /* ixgbe_configure_ivars */ 3294 3295 /************************************************************************ 3296 * ixgbe_config_gpie 3297 ************************************************************************/ 3298 static void 3299 ixgbe_config_gpie(struct ixgbe_softc *sc) 3300 { 3301 struct ixgbe_hw *hw = &sc->hw; 3302 u32 gpie; 3303 3304 gpie = IXGBE_READ_REG(hw, IXGBE_GPIE); 3305 3306 if (sc->intr_type == IFLIB_INTR_MSIX) { 3307 /* Enable Enhanced MSI-X mode */ 3308 gpie |= IXGBE_GPIE_MSIX_MODE 3309 | IXGBE_GPIE_EIAME 3310 | IXGBE_GPIE_PBA_SUPPORT 3311 | IXGBE_GPIE_OCD; 3312 } 3313 3314 /* Fan Failure Interrupt */ 3315 if (sc->feat_en & IXGBE_FEATURE_FAN_FAIL) 3316 gpie |= IXGBE_SDP1_GPIEN; 3317 3318 /* Thermal Sensor Interrupt */ 3319 if (sc->feat_en & IXGBE_FEATURE_TEMP_SENSOR) 3320 gpie |= IXGBE_SDP0_GPIEN_X540; 3321 3322 /* Link detection */ 3323 switch (hw->mac.type) { 3324 case ixgbe_mac_82599EB: 3325 gpie |= IXGBE_SDP1_GPIEN | IXGBE_SDP2_GPIEN; 3326 break; 3327 case ixgbe_mac_X550EM_x: 3328 case ixgbe_mac_X550EM_a: 3329 gpie |= IXGBE_SDP0_GPIEN_X540; 3330 break; 3331 default: 3332 break; 3333 } 3334 3335 IXGBE_WRITE_REG(hw, IXGBE_GPIE, gpie); 3336 3337 } /* ixgbe_config_gpie */ 3338 3339 /************************************************************************ 3340 * ixgbe_config_delay_values 3341 * 3342 * Requires sc->max_frame_size to be set. 3343 ************************************************************************/ 3344 static void 3345 ixgbe_config_delay_values(struct ixgbe_softc *sc) 3346 { 3347 struct ixgbe_hw *hw = &sc->hw; 3348 u32 rxpb, frame, size, tmp; 3349 3350 frame = sc->max_frame_size; 3351 3352 /* Calculate High Water */ 3353 switch (hw->mac.type) { 3354 case ixgbe_mac_X540: 3355 case ixgbe_mac_X550: 3356 case ixgbe_mac_X550EM_x: 3357 case ixgbe_mac_X550EM_a: 3358 tmp = IXGBE_DV_X540(frame, frame); 3359 break; 3360 default: 3361 tmp = IXGBE_DV(frame, frame); 3362 break; 3363 } 3364 size = IXGBE_BT2KB(tmp); 3365 rxpb = IXGBE_READ_REG(hw, IXGBE_RXPBSIZE(0)) >> 10; 3366 hw->fc.high_water[0] = rxpb - size; 3367 3368 /* Now calculate Low Water */ 3369 switch (hw->mac.type) { 3370 case ixgbe_mac_X540: 3371 case ixgbe_mac_X550: 3372 case ixgbe_mac_X550EM_x: 3373 case ixgbe_mac_X550EM_a: 3374 tmp = IXGBE_LOW_DV_X540(frame); 3375 break; 3376 default: 3377 tmp = IXGBE_LOW_DV(frame); 3378 break; 3379 } 3380 hw->fc.low_water[0] = IXGBE_BT2KB(tmp); 3381 3382 hw->fc.pause_time = IXGBE_FC_PAUSE; 3383 hw->fc.send_xon = true; 3384 } /* ixgbe_config_delay_values */ 3385 3386 /************************************************************************ 3387 * ixgbe_set_multi - Multicast Update 3388 * 3389 * Called whenever multicast address list is updated. 3390 ************************************************************************/ 3391 static u_int 3392 ixgbe_mc_filter_apply(void *arg, struct sockaddr_dl *sdl, u_int idx) 3393 { 3394 struct ixgbe_softc *sc = arg; 3395 struct ixgbe_mc_addr *mta = sc->mta; 3396 3397 if (idx == MAX_NUM_MULTICAST_ADDRESSES) 3398 return (0); 3399 bcopy(LLADDR(sdl), mta[idx].addr, IXGBE_ETH_LENGTH_OF_ADDRESS); 3400 mta[idx].vmdq = sc->pool; 3401 3402 return (1); 3403 } /* ixgbe_mc_filter_apply */ 3404 3405 static void 3406 ixgbe_if_multi_set(if_ctx_t ctx) 3407 { 3408 struct ixgbe_softc *sc = iflib_get_softc(ctx); 3409 struct ixgbe_mc_addr *mta; 3410 if_t ifp = iflib_get_ifp(ctx); 3411 u8 *update_ptr; 3412 u32 fctrl; 3413 u_int mcnt; 3414 3415 IOCTL_DEBUGOUT("ixgbe_if_multi_set: begin"); 3416 3417 mta = sc->mta; 3418 bzero(mta, sizeof(*mta) * MAX_NUM_MULTICAST_ADDRESSES); 3419 3420 mcnt = if_foreach_llmaddr(iflib_get_ifp(ctx), ixgbe_mc_filter_apply, sc); 3421 3422 if (mcnt < MAX_NUM_MULTICAST_ADDRESSES) { 3423 update_ptr = (u8 *)mta; 3424 ixgbe_update_mc_addr_list(&sc->hw, update_ptr, mcnt, 3425 ixgbe_mc_array_itr, true); 3426 } 3427 3428 fctrl = IXGBE_READ_REG(&sc->hw, IXGBE_FCTRL); 3429 3430 if (if_getflags(ifp) & IFF_PROMISC) 3431 fctrl |= (IXGBE_FCTRL_UPE | IXGBE_FCTRL_MPE); 3432 else if (mcnt >= MAX_NUM_MULTICAST_ADDRESSES || 3433 if_getflags(ifp) & IFF_ALLMULTI) { 3434 fctrl |= IXGBE_FCTRL_MPE; 3435 fctrl &= ~IXGBE_FCTRL_UPE; 3436 } else 3437 fctrl &= ~(IXGBE_FCTRL_UPE | IXGBE_FCTRL_MPE); 3438 3439 IXGBE_WRITE_REG(&sc->hw, IXGBE_FCTRL, fctrl); 3440 } /* ixgbe_if_multi_set */ 3441 3442 /************************************************************************ 3443 * ixgbe_mc_array_itr 3444 * 3445 * An iterator function needed by the multicast shared code. 3446 * It feeds the shared code routine the addresses in the 3447 * array of ixgbe_set_multi() one by one. 3448 ************************************************************************/ 3449 static u8 * 3450 ixgbe_mc_array_itr(struct ixgbe_hw *hw, u8 **update_ptr, u32 *vmdq) 3451 { 3452 struct ixgbe_mc_addr *mta; 3453 3454 mta = (struct ixgbe_mc_addr *)*update_ptr; 3455 *vmdq = mta->vmdq; 3456 3457 *update_ptr = (u8*)(mta + 1); 3458 3459 return (mta->addr); 3460 } /* ixgbe_mc_array_itr */ 3461 3462 /************************************************************************ 3463 * ixgbe_local_timer - Timer routine 3464 * 3465 * Checks for link status, updates statistics, 3466 * and runs the watchdog check. 3467 ************************************************************************/ 3468 static void 3469 ixgbe_if_timer(if_ctx_t ctx, uint16_t qid) 3470 { 3471 struct ixgbe_softc *sc = iflib_get_softc(ctx); 3472 3473 if (qid != 0) 3474 return; 3475 3476 /* Check for pluggable optics */ 3477 if (sc->sfp_probe) 3478 if (!ixgbe_sfp_probe(ctx)) 3479 return; /* Nothing to do */ 3480 3481 ixgbe_check_link(&sc->hw, &sc->link_speed, &sc->link_up, 0); 3482 3483 /* Fire off the adminq task */ 3484 iflib_admin_intr_deferred(ctx); 3485 3486 } /* ixgbe_if_timer */ 3487 3488 /************************************************************************ 3489 * ixgbe_sfp_probe 3490 * 3491 * Determine if a port had optics inserted. 3492 ************************************************************************/ 3493 static bool 3494 ixgbe_sfp_probe(if_ctx_t ctx) 3495 { 3496 struct ixgbe_softc *sc = iflib_get_softc(ctx); 3497 struct ixgbe_hw *hw = &sc->hw; 3498 device_t dev = iflib_get_dev(ctx); 3499 bool result = false; 3500 3501 if ((hw->phy.type == ixgbe_phy_nl) && 3502 (hw->phy.sfp_type == ixgbe_sfp_type_not_present)) { 3503 s32 ret = hw->phy.ops.identify_sfp(hw); 3504 if (ret) 3505 goto out; 3506 ret = hw->phy.ops.reset(hw); 3507 sc->sfp_probe = false; 3508 if (ret == IXGBE_ERR_SFP_NOT_SUPPORTED) { 3509 device_printf(dev, "Unsupported SFP+ module detected!"); 3510 device_printf(dev, 3511 "Reload driver with supported module.\n"); 3512 goto out; 3513 } else 3514 device_printf(dev, "SFP+ module detected!\n"); 3515 /* We now have supported optics */ 3516 result = true; 3517 } 3518 out: 3519 3520 return (result); 3521 } /* ixgbe_sfp_probe */ 3522 3523 /************************************************************************ 3524 * ixgbe_handle_mod - Tasklet for SFP module interrupts 3525 ************************************************************************/ 3526 static void 3527 ixgbe_handle_mod(void *context) 3528 { 3529 if_ctx_t ctx = context; 3530 struct ixgbe_softc *sc = iflib_get_softc(ctx); 3531 struct ixgbe_hw *hw = &sc->hw; 3532 device_t dev = iflib_get_dev(ctx); 3533 u32 err, cage_full = 0; 3534 3535 if (sc->hw.need_crosstalk_fix) { 3536 switch (hw->mac.type) { 3537 case ixgbe_mac_82599EB: 3538 cage_full = IXGBE_READ_REG(hw, IXGBE_ESDP) & 3539 IXGBE_ESDP_SDP2; 3540 break; 3541 case ixgbe_mac_X550EM_x: 3542 case ixgbe_mac_X550EM_a: 3543 cage_full = IXGBE_READ_REG(hw, IXGBE_ESDP) & 3544 IXGBE_ESDP_SDP0; 3545 break; 3546 default: 3547 break; 3548 } 3549 3550 if (!cage_full) 3551 goto handle_mod_out; 3552 } 3553 3554 err = hw->phy.ops.identify_sfp(hw); 3555 if (err == IXGBE_ERR_SFP_NOT_SUPPORTED) { 3556 device_printf(dev, 3557 "Unsupported SFP+ module type was detected.\n"); 3558 goto handle_mod_out; 3559 } 3560 3561 if (hw->mac.type == ixgbe_mac_82598EB) 3562 err = hw->phy.ops.reset(hw); 3563 else 3564 err = hw->mac.ops.setup_sfp(hw); 3565 3566 if (err == IXGBE_ERR_SFP_NOT_SUPPORTED) { 3567 device_printf(dev, 3568 "Setup failure - unsupported SFP+ module type.\n"); 3569 goto handle_mod_out; 3570 } 3571 sc->task_requests |= IXGBE_REQUEST_TASK_MSF; 3572 return; 3573 3574 handle_mod_out: 3575 sc->task_requests &= ~(IXGBE_REQUEST_TASK_MSF); 3576 } /* ixgbe_handle_mod */ 3577 3578 3579 /************************************************************************ 3580 * ixgbe_handle_msf - Tasklet for MSF (multispeed fiber) interrupts 3581 ************************************************************************/ 3582 static void 3583 ixgbe_handle_msf(void *context) 3584 { 3585 if_ctx_t ctx = context; 3586 struct ixgbe_softc *sc = iflib_get_softc(ctx); 3587 struct ixgbe_hw *hw = &sc->hw; 3588 u32 autoneg; 3589 bool negotiate; 3590 3591 /* get_supported_phy_layer will call hw->phy.ops.identify_sfp() */ 3592 sc->phy_layer = ixgbe_get_supported_physical_layer(hw); 3593 3594 autoneg = hw->phy.autoneg_advertised; 3595 if ((!autoneg) && (hw->mac.ops.get_link_capabilities)) 3596 hw->mac.ops.get_link_capabilities(hw, &autoneg, &negotiate); 3597 if (hw->mac.ops.setup_link) 3598 hw->mac.ops.setup_link(hw, autoneg, true); 3599 3600 /* Adjust media types shown in ifconfig */ 3601 ifmedia_removeall(sc->media); 3602 ixgbe_add_media_types(sc->ctx); 3603 ifmedia_set(sc->media, IFM_ETHER | IFM_AUTO); 3604 } /* ixgbe_handle_msf */ 3605 3606 /************************************************************************ 3607 * ixgbe_handle_phy - Tasklet for external PHY interrupts 3608 ************************************************************************/ 3609 static void 3610 ixgbe_handle_phy(void *context) 3611 { 3612 if_ctx_t ctx = context; 3613 struct ixgbe_softc *sc = iflib_get_softc(ctx); 3614 struct ixgbe_hw *hw = &sc->hw; 3615 int error; 3616 3617 error = hw->phy.ops.handle_lasi(hw); 3618 if (error == IXGBE_ERR_OVERTEMP) 3619 device_printf(sc->dev, "CRITICAL: EXTERNAL PHY OVER TEMP!! PHY will downshift to lower power state!\n"); 3620 else if (error) 3621 device_printf(sc->dev, 3622 "Error handling LASI interrupt: %d\n", error); 3623 } /* ixgbe_handle_phy */ 3624 3625 /************************************************************************ 3626 * ixgbe_if_stop - Stop the hardware 3627 * 3628 * Disables all traffic on the adapter by issuing a 3629 * global reset on the MAC and deallocates TX/RX buffers. 3630 ************************************************************************/ 3631 static void 3632 ixgbe_if_stop(if_ctx_t ctx) 3633 { 3634 struct ixgbe_softc *sc = iflib_get_softc(ctx); 3635 struct ixgbe_hw *hw = &sc->hw; 3636 3637 INIT_DEBUGOUT("ixgbe_if_stop: begin\n"); 3638 3639 ixgbe_reset_hw(hw); 3640 hw->adapter_stopped = false; 3641 ixgbe_stop_adapter(hw); 3642 if (hw->mac.type == ixgbe_mac_82599EB) 3643 ixgbe_stop_mac_link_on_d3_82599(hw); 3644 /* Turn off the laser - noop with no optics */ 3645 ixgbe_disable_tx_laser(hw); 3646 3647 /* Update the stack */ 3648 sc->link_up = false; 3649 ixgbe_if_update_admin_status(ctx); 3650 3651 /* reprogram the RAR[0] in case user changed it. */ 3652 ixgbe_set_rar(&sc->hw, 0, sc->hw.mac.addr, 0, IXGBE_RAH_AV); 3653 3654 return; 3655 } /* ixgbe_if_stop */ 3656 3657 /************************************************************************ 3658 * ixgbe_update_link_status - Update OS on link state 3659 * 3660 * Note: Only updates the OS on the cached link state. 3661 * The real check of the hardware only happens with 3662 * a link interrupt. 3663 ************************************************************************/ 3664 static void 3665 ixgbe_if_update_admin_status(if_ctx_t ctx) 3666 { 3667 struct ixgbe_softc *sc = iflib_get_softc(ctx); 3668 device_t dev = iflib_get_dev(ctx); 3669 3670 if (sc->link_up) { 3671 if (sc->link_active == false) { 3672 if (bootverbose) 3673 device_printf(dev, "Link is up %d Gbps %s \n", 3674 ((sc->link_speed == 128) ? 10 : 1), 3675 "Full Duplex"); 3676 sc->link_active = true; 3677 /* Update any Flow Control changes */ 3678 ixgbe_fc_enable(&sc->hw); 3679 /* Update DMA coalescing config */ 3680 ixgbe_config_dmac(sc); 3681 /* should actually be negotiated value */ 3682 iflib_link_state_change(ctx, LINK_STATE_UP, IF_Gbps(10)); 3683 3684 if (sc->feat_en & IXGBE_FEATURE_SRIOV) 3685 ixgbe_ping_all_vfs(sc); 3686 } 3687 } else { /* Link down */ 3688 if (sc->link_active == true) { 3689 if (bootverbose) 3690 device_printf(dev, "Link is Down\n"); 3691 iflib_link_state_change(ctx, LINK_STATE_DOWN, 0); 3692 sc->link_active = false; 3693 if (sc->feat_en & IXGBE_FEATURE_SRIOV) 3694 ixgbe_ping_all_vfs(sc); 3695 } 3696 } 3697 3698 /* Handle task requests from msix_link() */ 3699 if (sc->task_requests & IXGBE_REQUEST_TASK_MOD) 3700 ixgbe_handle_mod(ctx); 3701 if (sc->task_requests & IXGBE_REQUEST_TASK_MSF) 3702 ixgbe_handle_msf(ctx); 3703 if (sc->task_requests & IXGBE_REQUEST_TASK_MBX) 3704 ixgbe_handle_mbx(ctx); 3705 if (sc->task_requests & IXGBE_REQUEST_TASK_FDIR) 3706 ixgbe_reinit_fdir(ctx); 3707 if (sc->task_requests & IXGBE_REQUEST_TASK_PHY) 3708 ixgbe_handle_phy(ctx); 3709 sc->task_requests = 0; 3710 3711 ixgbe_update_stats_counters(sc); 3712 } /* ixgbe_if_update_admin_status */ 3713 3714 /************************************************************************ 3715 * ixgbe_config_dmac - Configure DMA Coalescing 3716 ************************************************************************/ 3717 static void 3718 ixgbe_config_dmac(struct ixgbe_softc *sc) 3719 { 3720 struct ixgbe_hw *hw = &sc->hw; 3721 struct ixgbe_dmac_config *dcfg = &hw->mac.dmac_config; 3722 3723 if (hw->mac.type < ixgbe_mac_X550 || !hw->mac.ops.dmac_config) 3724 return; 3725 3726 if (dcfg->watchdog_timer ^ sc->dmac || 3727 dcfg->link_speed ^ sc->link_speed) { 3728 dcfg->watchdog_timer = sc->dmac; 3729 dcfg->fcoe_en = false; 3730 dcfg->link_speed = sc->link_speed; 3731 dcfg->num_tcs = 1; 3732 3733 INIT_DEBUGOUT2("dmac settings: watchdog %d, link speed %d\n", 3734 dcfg->watchdog_timer, dcfg->link_speed); 3735 3736 hw->mac.ops.dmac_config(hw); 3737 } 3738 } /* ixgbe_config_dmac */ 3739 3740 /************************************************************************ 3741 * ixgbe_if_enable_intr 3742 ************************************************************************/ 3743 void 3744 ixgbe_if_enable_intr(if_ctx_t ctx) 3745 { 3746 struct ixgbe_softc *sc = iflib_get_softc(ctx); 3747 struct ixgbe_hw *hw = &sc->hw; 3748 struct ix_rx_queue *que = sc->rx_queues; 3749 u32 mask, fwsm; 3750 3751 mask = (IXGBE_EIMS_ENABLE_MASK & ~IXGBE_EIMS_RTX_QUEUE); 3752 3753 switch (sc->hw.mac.type) { 3754 case ixgbe_mac_82599EB: 3755 mask |= IXGBE_EIMS_ECC; 3756 /* Temperature sensor on some scs */ 3757 mask |= IXGBE_EIMS_GPI_SDP0; 3758 /* SFP+ (RX_LOS_N & MOD_ABS_N) */ 3759 mask |= IXGBE_EIMS_GPI_SDP1; 3760 mask |= IXGBE_EIMS_GPI_SDP2; 3761 break; 3762 case ixgbe_mac_X540: 3763 /* Detect if Thermal Sensor is enabled */ 3764 fwsm = IXGBE_READ_REG(hw, IXGBE_FWSM); 3765 if (fwsm & IXGBE_FWSM_TS_ENABLED) 3766 mask |= IXGBE_EIMS_TS; 3767 mask |= IXGBE_EIMS_ECC; 3768 break; 3769 case ixgbe_mac_X550: 3770 /* MAC thermal sensor is automatically enabled */ 3771 mask |= IXGBE_EIMS_TS; 3772 mask |= IXGBE_EIMS_ECC; 3773 break; 3774 case ixgbe_mac_X550EM_x: 3775 case ixgbe_mac_X550EM_a: 3776 /* Some devices use SDP0 for important information */ 3777 if (hw->device_id == IXGBE_DEV_ID_X550EM_X_SFP || 3778 hw->device_id == IXGBE_DEV_ID_X550EM_A_SFP || 3779 hw->device_id == IXGBE_DEV_ID_X550EM_A_SFP_N || 3780 hw->device_id == IXGBE_DEV_ID_X550EM_X_10G_T) 3781 mask |= IXGBE_EIMS_GPI_SDP0_BY_MAC(hw); 3782 if (hw->phy.type == ixgbe_phy_x550em_ext_t) 3783 mask |= IXGBE_EICR_GPI_SDP0_X540; 3784 mask |= IXGBE_EIMS_ECC; 3785 break; 3786 default: 3787 break; 3788 } 3789 3790 /* Enable Fan Failure detection */ 3791 if (sc->feat_en & IXGBE_FEATURE_FAN_FAIL) 3792 mask |= IXGBE_EIMS_GPI_SDP1; 3793 /* Enable SR-IOV */ 3794 if (sc->feat_en & IXGBE_FEATURE_SRIOV) 3795 mask |= IXGBE_EIMS_MAILBOX; 3796 /* Enable Flow Director */ 3797 if (sc->feat_en & IXGBE_FEATURE_FDIR) 3798 mask |= IXGBE_EIMS_FLOW_DIR; 3799 3800 IXGBE_WRITE_REG(hw, IXGBE_EIMS, mask); 3801 3802 /* With MSI-X we use auto clear */ 3803 if (sc->intr_type == IFLIB_INTR_MSIX) { 3804 mask = IXGBE_EIMS_ENABLE_MASK; 3805 /* Don't autoclear Link */ 3806 mask &= ~IXGBE_EIMS_OTHER; 3807 mask &= ~IXGBE_EIMS_LSC; 3808 if (sc->feat_cap & IXGBE_FEATURE_SRIOV) 3809 mask &= ~IXGBE_EIMS_MAILBOX; 3810 IXGBE_WRITE_REG(hw, IXGBE_EIAC, mask); 3811 } 3812 3813 /* 3814 * Now enable all queues, this is done separately to 3815 * allow for handling the extended (beyond 32) MSI-X 3816 * vectors that can be used by 82599 3817 */ 3818 for (int i = 0; i < sc->num_rx_queues; i++, que++) 3819 ixgbe_enable_queue(sc, que->msix); 3820 3821 IXGBE_WRITE_FLUSH(hw); 3822 3823 } /* ixgbe_if_enable_intr */ 3824 3825 /************************************************************************ 3826 * ixgbe_disable_intr 3827 ************************************************************************/ 3828 static void 3829 ixgbe_if_disable_intr(if_ctx_t ctx) 3830 { 3831 struct ixgbe_softc *sc = iflib_get_softc(ctx); 3832 3833 if (sc->intr_type == IFLIB_INTR_MSIX) 3834 IXGBE_WRITE_REG(&sc->hw, IXGBE_EIAC, 0); 3835 if (sc->hw.mac.type == ixgbe_mac_82598EB) { 3836 IXGBE_WRITE_REG(&sc->hw, IXGBE_EIMC, ~0); 3837 } else { 3838 IXGBE_WRITE_REG(&sc->hw, IXGBE_EIMC, 0xFFFF0000); 3839 IXGBE_WRITE_REG(&sc->hw, IXGBE_EIMC_EX(0), ~0); 3840 IXGBE_WRITE_REG(&sc->hw, IXGBE_EIMC_EX(1), ~0); 3841 } 3842 IXGBE_WRITE_FLUSH(&sc->hw); 3843 3844 } /* ixgbe_if_disable_intr */ 3845 3846 /************************************************************************ 3847 * ixgbe_link_intr_enable 3848 ************************************************************************/ 3849 static void 3850 ixgbe_link_intr_enable(if_ctx_t ctx) 3851 { 3852 struct ixgbe_hw *hw = &((struct ixgbe_softc *)iflib_get_softc(ctx))->hw; 3853 3854 /* Re-enable other interrupts */ 3855 IXGBE_WRITE_REG(hw, IXGBE_EIMS, IXGBE_EIMS_OTHER | IXGBE_EIMS_LSC); 3856 } /* ixgbe_link_intr_enable */ 3857 3858 /************************************************************************ 3859 * ixgbe_if_rx_queue_intr_enable 3860 ************************************************************************/ 3861 static int 3862 ixgbe_if_rx_queue_intr_enable(if_ctx_t ctx, uint16_t rxqid) 3863 { 3864 struct ixgbe_softc *sc = iflib_get_softc(ctx); 3865 struct ix_rx_queue *que = &sc->rx_queues[rxqid]; 3866 3867 ixgbe_enable_queue(sc, que->msix); 3868 3869 return (0); 3870 } /* ixgbe_if_rx_queue_intr_enable */ 3871 3872 /************************************************************************ 3873 * ixgbe_enable_queue 3874 ************************************************************************/ 3875 static void 3876 ixgbe_enable_queue(struct ixgbe_softc *sc, u32 vector) 3877 { 3878 struct ixgbe_hw *hw = &sc->hw; 3879 u64 queue = 1ULL << vector; 3880 u32 mask; 3881 3882 if (hw->mac.type == ixgbe_mac_82598EB) { 3883 mask = (IXGBE_EIMS_RTX_QUEUE & queue); 3884 IXGBE_WRITE_REG(hw, IXGBE_EIMS, mask); 3885 } else { 3886 mask = (queue & 0xFFFFFFFF); 3887 if (mask) 3888 IXGBE_WRITE_REG(hw, IXGBE_EIMS_EX(0), mask); 3889 mask = (queue >> 32); 3890 if (mask) 3891 IXGBE_WRITE_REG(hw, IXGBE_EIMS_EX(1), mask); 3892 } 3893 } /* ixgbe_enable_queue */ 3894 3895 /************************************************************************ 3896 * ixgbe_disable_queue 3897 ************************************************************************/ 3898 static void 3899 ixgbe_disable_queue(struct ixgbe_softc *sc, u32 vector) 3900 { 3901 struct ixgbe_hw *hw = &sc->hw; 3902 u64 queue = 1ULL << vector; 3903 u32 mask; 3904 3905 if (hw->mac.type == ixgbe_mac_82598EB) { 3906 mask = (IXGBE_EIMS_RTX_QUEUE & queue); 3907 IXGBE_WRITE_REG(hw, IXGBE_EIMC, mask); 3908 } else { 3909 mask = (queue & 0xFFFFFFFF); 3910 if (mask) 3911 IXGBE_WRITE_REG(hw, IXGBE_EIMC_EX(0), mask); 3912 mask = (queue >> 32); 3913 if (mask) 3914 IXGBE_WRITE_REG(hw, IXGBE_EIMC_EX(1), mask); 3915 } 3916 } /* ixgbe_disable_queue */ 3917 3918 /************************************************************************ 3919 * ixgbe_intr - Legacy Interrupt Service Routine 3920 ************************************************************************/ 3921 int 3922 ixgbe_intr(void *arg) 3923 { 3924 struct ixgbe_softc *sc = arg; 3925 struct ix_rx_queue *que = sc->rx_queues; 3926 struct ixgbe_hw *hw = &sc->hw; 3927 if_ctx_t ctx = sc->ctx; 3928 u32 eicr, eicr_mask; 3929 3930 eicr = IXGBE_READ_REG(hw, IXGBE_EICR); 3931 3932 ++que->irqs; 3933 if (eicr == 0) { 3934 ixgbe_if_enable_intr(ctx); 3935 return (FILTER_HANDLED); 3936 } 3937 3938 /* Check for fan failure */ 3939 if ((hw->device_id == IXGBE_DEV_ID_82598AT) && 3940 (eicr & IXGBE_EICR_GPI_SDP1)) { 3941 device_printf(sc->dev, 3942 "\nCRITICAL: FAN FAILURE!! REPLACE IMMEDIATELY!!\n"); 3943 IXGBE_WRITE_REG(hw, IXGBE_EIMS, IXGBE_EICR_GPI_SDP1_BY_MAC(hw)); 3944 } 3945 3946 /* Link status change */ 3947 if (eicr & IXGBE_EICR_LSC) { 3948 IXGBE_WRITE_REG(hw, IXGBE_EIMC, IXGBE_EIMC_LSC); 3949 iflib_admin_intr_deferred(ctx); 3950 } 3951 3952 if (ixgbe_is_sfp(hw)) { 3953 /* Pluggable optics-related interrupt */ 3954 if (hw->mac.type >= ixgbe_mac_X540) 3955 eicr_mask = IXGBE_EICR_GPI_SDP0_X540; 3956 else 3957 eicr_mask = IXGBE_EICR_GPI_SDP2_BY_MAC(hw); 3958 3959 if (eicr & eicr_mask) { 3960 IXGBE_WRITE_REG(hw, IXGBE_EICR, eicr_mask); 3961 sc->task_requests |= IXGBE_REQUEST_TASK_MOD; 3962 } 3963 3964 if ((hw->mac.type == ixgbe_mac_82599EB) && 3965 (eicr & IXGBE_EICR_GPI_SDP1_BY_MAC(hw))) { 3966 IXGBE_WRITE_REG(hw, IXGBE_EICR, 3967 IXGBE_EICR_GPI_SDP1_BY_MAC(hw)); 3968 sc->task_requests |= IXGBE_REQUEST_TASK_MSF; 3969 } 3970 } 3971 3972 /* External PHY interrupt */ 3973 if ((hw->phy.type == ixgbe_phy_x550em_ext_t) && 3974 (eicr & IXGBE_EICR_GPI_SDP0_X540)) 3975 sc->task_requests |= IXGBE_REQUEST_TASK_PHY; 3976 3977 return (FILTER_SCHEDULE_THREAD); 3978 } /* ixgbe_intr */ 3979 3980 /************************************************************************ 3981 * ixgbe_free_pci_resources 3982 ************************************************************************/ 3983 static void 3984 ixgbe_free_pci_resources(if_ctx_t ctx) 3985 { 3986 struct ixgbe_softc *sc = iflib_get_softc(ctx); 3987 struct ix_rx_queue *que = sc->rx_queues; 3988 device_t dev = iflib_get_dev(ctx); 3989 3990 /* Release all MSI-X queue resources */ 3991 if (sc->intr_type == IFLIB_INTR_MSIX) 3992 iflib_irq_free(ctx, &sc->irq); 3993 3994 if (que != NULL) { 3995 for (int i = 0; i < sc->num_rx_queues; i++, que++) { 3996 iflib_irq_free(ctx, &que->que_irq); 3997 } 3998 } 3999 4000 if (sc->pci_mem != NULL) 4001 bus_release_resource(dev, SYS_RES_MEMORY, 4002 rman_get_rid(sc->pci_mem), sc->pci_mem); 4003 } /* ixgbe_free_pci_resources */ 4004 4005 /************************************************************************ 4006 * ixgbe_sysctl_flowcntl 4007 * 4008 * SYSCTL wrapper around setting Flow Control 4009 ************************************************************************/ 4010 static int 4011 ixgbe_sysctl_flowcntl(SYSCTL_HANDLER_ARGS) 4012 { 4013 struct ixgbe_softc *sc; 4014 int error, fc; 4015 4016 sc = (struct ixgbe_softc *)arg1; 4017 fc = sc->hw.fc.current_mode; 4018 4019 error = sysctl_handle_int(oidp, &fc, 0, req); 4020 if ((error) || (req->newptr == NULL)) 4021 return (error); 4022 4023 /* Don't bother if it's not changed */ 4024 if (fc == sc->hw.fc.current_mode) 4025 return (0); 4026 4027 return ixgbe_set_flowcntl(sc, fc); 4028 } /* ixgbe_sysctl_flowcntl */ 4029 4030 /************************************************************************ 4031 * ixgbe_set_flowcntl - Set flow control 4032 * 4033 * Flow control values: 4034 * 0 - off 4035 * 1 - rx pause 4036 * 2 - tx pause 4037 * 3 - full 4038 ************************************************************************/ 4039 static int 4040 ixgbe_set_flowcntl(struct ixgbe_softc *sc, int fc) 4041 { 4042 switch (fc) { 4043 case ixgbe_fc_rx_pause: 4044 case ixgbe_fc_tx_pause: 4045 case ixgbe_fc_full: 4046 sc->hw.fc.requested_mode = fc; 4047 if (sc->num_rx_queues > 1) 4048 ixgbe_disable_rx_drop(sc); 4049 break; 4050 case ixgbe_fc_none: 4051 sc->hw.fc.requested_mode = ixgbe_fc_none; 4052 if (sc->num_rx_queues > 1) 4053 ixgbe_enable_rx_drop(sc); 4054 break; 4055 default: 4056 return (EINVAL); 4057 } 4058 4059 /* Don't autoneg if forcing a value */ 4060 sc->hw.fc.disable_fc_autoneg = true; 4061 ixgbe_fc_enable(&sc->hw); 4062 4063 return (0); 4064 } /* ixgbe_set_flowcntl */ 4065 4066 /************************************************************************ 4067 * ixgbe_enable_rx_drop 4068 * 4069 * Enable the hardware to drop packets when the buffer is 4070 * full. This is useful with multiqueue, so that no single 4071 * queue being full stalls the entire RX engine. We only 4072 * enable this when Multiqueue is enabled AND Flow Control 4073 * is disabled. 4074 ************************************************************************/ 4075 static void 4076 ixgbe_enable_rx_drop(struct ixgbe_softc *sc) 4077 { 4078 struct ixgbe_hw *hw = &sc->hw; 4079 struct rx_ring *rxr; 4080 u32 srrctl; 4081 4082 for (int i = 0; i < sc->num_rx_queues; i++) { 4083 rxr = &sc->rx_queues[i].rxr; 4084 srrctl = IXGBE_READ_REG(hw, IXGBE_SRRCTL(rxr->me)); 4085 srrctl |= IXGBE_SRRCTL_DROP_EN; 4086 IXGBE_WRITE_REG(hw, IXGBE_SRRCTL(rxr->me), srrctl); 4087 } 4088 4089 /* enable drop for each vf */ 4090 for (int i = 0; i < sc->num_vfs; i++) { 4091 IXGBE_WRITE_REG(hw, IXGBE_QDE, 4092 (IXGBE_QDE_WRITE | (i << IXGBE_QDE_IDX_SHIFT) | 4093 IXGBE_QDE_ENABLE)); 4094 } 4095 } /* ixgbe_enable_rx_drop */ 4096 4097 /************************************************************************ 4098 * ixgbe_disable_rx_drop 4099 ************************************************************************/ 4100 static void 4101 ixgbe_disable_rx_drop(struct ixgbe_softc *sc) 4102 { 4103 struct ixgbe_hw *hw = &sc->hw; 4104 struct rx_ring *rxr; 4105 u32 srrctl; 4106 4107 for (int i = 0; i < sc->num_rx_queues; i++) { 4108 rxr = &sc->rx_queues[i].rxr; 4109 srrctl = IXGBE_READ_REG(hw, IXGBE_SRRCTL(rxr->me)); 4110 srrctl &= ~IXGBE_SRRCTL_DROP_EN; 4111 IXGBE_WRITE_REG(hw, IXGBE_SRRCTL(rxr->me), srrctl); 4112 } 4113 4114 /* disable drop for each vf */ 4115 for (int i = 0; i < sc->num_vfs; i++) { 4116 IXGBE_WRITE_REG(hw, IXGBE_QDE, 4117 (IXGBE_QDE_WRITE | (i << IXGBE_QDE_IDX_SHIFT))); 4118 } 4119 } /* ixgbe_disable_rx_drop */ 4120 4121 /************************************************************************ 4122 * ixgbe_sysctl_advertise 4123 * 4124 * SYSCTL wrapper around setting advertised speed 4125 ************************************************************************/ 4126 static int 4127 ixgbe_sysctl_advertise(SYSCTL_HANDLER_ARGS) 4128 { 4129 struct ixgbe_softc *sc; 4130 int error, advertise; 4131 4132 sc = (struct ixgbe_softc *)arg1; 4133 advertise = sc->advertise; 4134 4135 error = sysctl_handle_int(oidp, &advertise, 0, req); 4136 if ((error) || (req->newptr == NULL)) 4137 return (error); 4138 4139 return ixgbe_set_advertise(sc, advertise); 4140 } /* ixgbe_sysctl_advertise */ 4141 4142 /************************************************************************ 4143 * ixgbe_set_advertise - Control advertised link speed 4144 * 4145 * Flags: 4146 * 0x1 - advertise 100 Mb 4147 * 0x2 - advertise 1G 4148 * 0x4 - advertise 10G 4149 * 0x8 - advertise 10 Mb (yes, Mb) 4150 * 0x10 - advertise 2.5G (disabled by default) 4151 * 0x20 - advertise 5G (disabled by default) 4152 * 4153 ************************************************************************/ 4154 static int 4155 ixgbe_set_advertise(struct ixgbe_softc *sc, int advertise) 4156 { 4157 device_t dev = iflib_get_dev(sc->ctx); 4158 struct ixgbe_hw *hw; 4159 ixgbe_link_speed speed = 0; 4160 ixgbe_link_speed link_caps = 0; 4161 s32 err = IXGBE_NOT_IMPLEMENTED; 4162 bool negotiate = false; 4163 4164 /* Checks to validate new value */ 4165 if (sc->advertise == advertise) /* no change */ 4166 return (0); 4167 4168 hw = &sc->hw; 4169 4170 /* No speed changes for backplane media */ 4171 if (hw->phy.media_type == ixgbe_media_type_backplane) 4172 return (ENODEV); 4173 4174 if (!((hw->phy.media_type == ixgbe_media_type_copper) || 4175 (hw->phy.multispeed_fiber))) { 4176 device_printf(dev, "Advertised speed can only be set on copper or multispeed fiber media types.\n"); 4177 return (EINVAL); 4178 } 4179 4180 if (advertise < 0x1 || advertise > 0x3F) { 4181 device_printf(dev, "Invalid advertised speed; valid modes are 0x1 through 0x3F\n"); 4182 return (EINVAL); 4183 } 4184 4185 if (hw->mac.ops.get_link_capabilities) { 4186 err = hw->mac.ops.get_link_capabilities(hw, &link_caps, 4187 &negotiate); 4188 if (err != IXGBE_SUCCESS) { 4189 device_printf(dev, "Unable to determine supported advertise speeds\n"); 4190 return (ENODEV); 4191 } 4192 } 4193 4194 /* Set new value and report new advertised mode */ 4195 if (advertise & 0x1) { 4196 if (!(link_caps & IXGBE_LINK_SPEED_100_FULL)) { 4197 device_printf(dev, "Interface does not support 100Mb advertised speed\n"); 4198 return (EINVAL); 4199 } 4200 speed |= IXGBE_LINK_SPEED_100_FULL; 4201 } 4202 if (advertise & 0x2) { 4203 if (!(link_caps & IXGBE_LINK_SPEED_1GB_FULL)) { 4204 device_printf(dev, "Interface does not support 1Gb advertised speed\n"); 4205 return (EINVAL); 4206 } 4207 speed |= IXGBE_LINK_SPEED_1GB_FULL; 4208 } 4209 if (advertise & 0x4) { 4210 if (!(link_caps & IXGBE_LINK_SPEED_10GB_FULL)) { 4211 device_printf(dev, "Interface does not support 10Gb advertised speed\n"); 4212 return (EINVAL); 4213 } 4214 speed |= IXGBE_LINK_SPEED_10GB_FULL; 4215 } 4216 if (advertise & 0x8) { 4217 if (!(link_caps & IXGBE_LINK_SPEED_10_FULL)) { 4218 device_printf(dev, "Interface does not support 10Mb advertised speed\n"); 4219 return (EINVAL); 4220 } 4221 speed |= IXGBE_LINK_SPEED_10_FULL; 4222 } 4223 if (advertise & 0x10) { 4224 if (!(link_caps & IXGBE_LINK_SPEED_2_5GB_FULL)) { 4225 device_printf(dev, "Interface does not support 2.5G advertised speed\n"); 4226 return (EINVAL); 4227 } 4228 speed |= IXGBE_LINK_SPEED_2_5GB_FULL; 4229 } 4230 if (advertise & 0x20) { 4231 if (!(link_caps & IXGBE_LINK_SPEED_5GB_FULL)) { 4232 device_printf(dev, "Interface does not support 5G advertised speed\n"); 4233 return (EINVAL); 4234 } 4235 speed |= IXGBE_LINK_SPEED_5GB_FULL; 4236 } 4237 4238 hw->mac.autotry_restart = true; 4239 hw->mac.ops.setup_link(hw, speed, true); 4240 sc->advertise = advertise; 4241 4242 return (0); 4243 } /* ixgbe_set_advertise */ 4244 4245 /************************************************************************ 4246 * ixgbe_get_default_advertise - Get default advertised speed settings 4247 * 4248 * Formatted for sysctl usage. 4249 * Flags: 4250 * 0x1 - advertise 100 Mb 4251 * 0x2 - advertise 1G 4252 * 0x4 - advertise 10G 4253 * 0x8 - advertise 10 Mb (yes, Mb) 4254 * 0x10 - advertise 2.5G (disabled by default) 4255 * 0x20 - advertise 5G (disabled by default) 4256 ************************************************************************/ 4257 static int 4258 ixgbe_get_default_advertise(struct ixgbe_softc *sc) 4259 { 4260 struct ixgbe_hw *hw = &sc->hw; 4261 int speed; 4262 ixgbe_link_speed link_caps = 0; 4263 s32 err; 4264 bool negotiate = false; 4265 4266 /* 4267 * Advertised speed means nothing unless it's copper or 4268 * multi-speed fiber 4269 */ 4270 if (!(hw->phy.media_type == ixgbe_media_type_copper) && 4271 !(hw->phy.multispeed_fiber)) 4272 return (0); 4273 4274 err = hw->mac.ops.get_link_capabilities(hw, &link_caps, &negotiate); 4275 if (err != IXGBE_SUCCESS) 4276 return (0); 4277 4278 if (hw->mac.type == ixgbe_mac_X550) { 4279 /* 4280 * 2.5G and 5G autonegotiation speeds on X550 4281 * are disabled by default due to reported 4282 * interoperability issues with some switches. 4283 */ 4284 link_caps &= ~(IXGBE_LINK_SPEED_2_5GB_FULL | 4285 IXGBE_LINK_SPEED_5GB_FULL); 4286 } 4287 4288 speed = 4289 ((link_caps & IXGBE_LINK_SPEED_10GB_FULL) ? 0x4 : 0) | 4290 ((link_caps & IXGBE_LINK_SPEED_5GB_FULL) ? 0x20 : 0) | 4291 ((link_caps & IXGBE_LINK_SPEED_2_5GB_FULL) ? 0x10 : 0) | 4292 ((link_caps & IXGBE_LINK_SPEED_1GB_FULL) ? 0x2 : 0) | 4293 ((link_caps & IXGBE_LINK_SPEED_100_FULL) ? 0x1 : 0) | 4294 ((link_caps & IXGBE_LINK_SPEED_10_FULL) ? 0x8 : 0); 4295 4296 return speed; 4297 } /* ixgbe_get_default_advertise */ 4298 4299 /************************************************************************ 4300 * ixgbe_sysctl_dmac - Manage DMA Coalescing 4301 * 4302 * Control values: 4303 * 0/1 - off / on (use default value of 1000) 4304 * 4305 * Legal timer values are: 4306 * 50,100,250,500,1000,2000,5000,10000 4307 * 4308 * Turning off interrupt moderation will also turn this off. 4309 ************************************************************************/ 4310 static int 4311 ixgbe_sysctl_dmac(SYSCTL_HANDLER_ARGS) 4312 { 4313 struct ixgbe_softc *sc = (struct ixgbe_softc *)arg1; 4314 if_t ifp = iflib_get_ifp(sc->ctx); 4315 int error; 4316 u16 newval; 4317 4318 newval = sc->dmac; 4319 error = sysctl_handle_16(oidp, &newval, 0, req); 4320 if ((error) || (req->newptr == NULL)) 4321 return (error); 4322 4323 switch (newval) { 4324 case 0: 4325 /* Disabled */ 4326 sc->dmac = 0; 4327 break; 4328 case 1: 4329 /* Enable and use default */ 4330 sc->dmac = 1000; 4331 break; 4332 case 50: 4333 case 100: 4334 case 250: 4335 case 500: 4336 case 1000: 4337 case 2000: 4338 case 5000: 4339 case 10000: 4340 /* Legal values - allow */ 4341 sc->dmac = newval; 4342 break; 4343 default: 4344 /* Do nothing, illegal value */ 4345 return (EINVAL); 4346 } 4347 4348 /* Re-initialize hardware if it's already running */ 4349 if (if_getdrvflags(ifp) & IFF_DRV_RUNNING) 4350 if_init(ifp, ifp); 4351 4352 return (0); 4353 } /* ixgbe_sysctl_dmac */ 4354 4355 #ifdef IXGBE_DEBUG 4356 /************************************************************************ 4357 * ixgbe_sysctl_power_state 4358 * 4359 * Sysctl to test power states 4360 * Values: 4361 * 0 - set device to D0 4362 * 3 - set device to D3 4363 * (none) - get current device power state 4364 ************************************************************************/ 4365 static int 4366 ixgbe_sysctl_power_state(SYSCTL_HANDLER_ARGS) 4367 { 4368 struct ixgbe_softc *sc = (struct ixgbe_softc *)arg1; 4369 device_t dev = sc->dev; 4370 int curr_ps, new_ps, error = 0; 4371 4372 curr_ps = new_ps = pci_get_powerstate(dev); 4373 4374 error = sysctl_handle_int(oidp, &new_ps, 0, req); 4375 if ((error) || (req->newptr == NULL)) 4376 return (error); 4377 4378 if (new_ps == curr_ps) 4379 return (0); 4380 4381 if (new_ps == 3 && curr_ps == 0) 4382 error = DEVICE_SUSPEND(dev); 4383 else if (new_ps == 0 && curr_ps == 3) 4384 error = DEVICE_RESUME(dev); 4385 else 4386 return (EINVAL); 4387 4388 device_printf(dev, "New state: %d\n", pci_get_powerstate(dev)); 4389 4390 return (error); 4391 } /* ixgbe_sysctl_power_state */ 4392 #endif 4393 4394 /************************************************************************ 4395 * ixgbe_sysctl_wol_enable 4396 * 4397 * Sysctl to enable/disable the WoL capability, 4398 * if supported by the adapter. 4399 * 4400 * Values: 4401 * 0 - disabled 4402 * 1 - enabled 4403 ************************************************************************/ 4404 static int 4405 ixgbe_sysctl_wol_enable(SYSCTL_HANDLER_ARGS) 4406 { 4407 struct ixgbe_softc *sc = (struct ixgbe_softc *)arg1; 4408 struct ixgbe_hw *hw = &sc->hw; 4409 int new_wol_enabled; 4410 int error = 0; 4411 4412 new_wol_enabled = hw->wol_enabled; 4413 error = sysctl_handle_int(oidp, &new_wol_enabled, 0, req); 4414 if ((error) || (req->newptr == NULL)) 4415 return (error); 4416 new_wol_enabled = !!(new_wol_enabled); 4417 if (new_wol_enabled == hw->wol_enabled) 4418 return (0); 4419 4420 if (new_wol_enabled > 0 && !sc->wol_support) 4421 return (ENODEV); 4422 else 4423 hw->wol_enabled = new_wol_enabled; 4424 4425 return (0); 4426 } /* ixgbe_sysctl_wol_enable */ 4427 4428 /************************************************************************ 4429 * ixgbe_sysctl_wufc - Wake Up Filter Control 4430 * 4431 * Sysctl to enable/disable the types of packets that the 4432 * adapter will wake up on upon receipt. 4433 * Flags: 4434 * 0x1 - Link Status Change 4435 * 0x2 - Magic Packet 4436 * 0x4 - Direct Exact 4437 * 0x8 - Directed Multicast 4438 * 0x10 - Broadcast 4439 * 0x20 - ARP/IPv4 Request Packet 4440 * 0x40 - Direct IPv4 Packet 4441 * 0x80 - Direct IPv6 Packet 4442 * 4443 * Settings not listed above will cause the sysctl to return an error. 4444 ************************************************************************/ 4445 static int 4446 ixgbe_sysctl_wufc(SYSCTL_HANDLER_ARGS) 4447 { 4448 struct ixgbe_softc *sc = (struct ixgbe_softc *)arg1; 4449 int error = 0; 4450 u32 new_wufc; 4451 4452 new_wufc = sc->wufc; 4453 4454 error = sysctl_handle_32(oidp, &new_wufc, 0, req); 4455 if ((error) || (req->newptr == NULL)) 4456 return (error); 4457 if (new_wufc == sc->wufc) 4458 return (0); 4459 4460 if (new_wufc & 0xffffff00) 4461 return (EINVAL); 4462 4463 new_wufc &= 0xff; 4464 new_wufc |= (0xffffff & sc->wufc); 4465 sc->wufc = new_wufc; 4466 4467 return (0); 4468 } /* ixgbe_sysctl_wufc */ 4469 4470 #ifdef IXGBE_DEBUG 4471 /************************************************************************ 4472 * ixgbe_sysctl_print_rss_config 4473 ************************************************************************/ 4474 static int 4475 ixgbe_sysctl_print_rss_config(SYSCTL_HANDLER_ARGS) 4476 { 4477 struct ixgbe_softc *sc = (struct ixgbe_softc *)arg1; 4478 struct ixgbe_hw *hw = &sc->hw; 4479 device_t dev = sc->dev; 4480 struct sbuf *buf; 4481 int error = 0, reta_size; 4482 u32 reg; 4483 4484 buf = sbuf_new_for_sysctl(NULL, NULL, 128, req); 4485 if (!buf) { 4486 device_printf(dev, "Could not allocate sbuf for output.\n"); 4487 return (ENOMEM); 4488 } 4489 4490 // TODO: use sbufs to make a string to print out 4491 /* Set multiplier for RETA setup and table size based on MAC */ 4492 switch (sc->hw.mac.type) { 4493 case ixgbe_mac_X550: 4494 case ixgbe_mac_X550EM_x: 4495 case ixgbe_mac_X550EM_a: 4496 reta_size = 128; 4497 break; 4498 default: 4499 reta_size = 32; 4500 break; 4501 } 4502 4503 /* Print out the redirection table */ 4504 sbuf_cat(buf, "\n"); 4505 for (int i = 0; i < reta_size; i++) { 4506 if (i < 32) { 4507 reg = IXGBE_READ_REG(hw, IXGBE_RETA(i)); 4508 sbuf_printf(buf, "RETA(%2d): 0x%08x\n", i, reg); 4509 } else { 4510 reg = IXGBE_READ_REG(hw, IXGBE_ERETA(i - 32)); 4511 sbuf_printf(buf, "ERETA(%2d): 0x%08x\n", i - 32, reg); 4512 } 4513 } 4514 4515 // TODO: print more config 4516 4517 error = sbuf_finish(buf); 4518 if (error) 4519 device_printf(dev, "Error finishing sbuf: %d\n", error); 4520 4521 sbuf_delete(buf); 4522 4523 return (0); 4524 } /* ixgbe_sysctl_print_rss_config */ 4525 #endif /* IXGBE_DEBUG */ 4526 4527 /************************************************************************ 4528 * ixgbe_sysctl_phy_temp - Retrieve temperature of PHY 4529 * 4530 * For X552/X557-AT devices using an external PHY 4531 ************************************************************************/ 4532 static int 4533 ixgbe_sysctl_phy_temp(SYSCTL_HANDLER_ARGS) 4534 { 4535 struct ixgbe_softc *sc = (struct ixgbe_softc *)arg1; 4536 struct ixgbe_hw *hw = &sc->hw; 4537 u16 reg; 4538 4539 if (hw->device_id != IXGBE_DEV_ID_X550EM_X_10G_T) { 4540 device_printf(iflib_get_dev(sc->ctx), 4541 "Device has no supported external thermal sensor.\n"); 4542 return (ENODEV); 4543 } 4544 4545 if (hw->phy.ops.read_reg(hw, IXGBE_PHY_CURRENT_TEMP, 4546 IXGBE_MDIO_VENDOR_SPECIFIC_1_DEV_TYPE, ®)) { 4547 device_printf(iflib_get_dev(sc->ctx), 4548 "Error reading from PHY's current temperature register\n"); 4549 return (EAGAIN); 4550 } 4551 4552 /* Shift temp for output */ 4553 reg = reg >> 8; 4554 4555 return (sysctl_handle_16(oidp, NULL, reg, req)); 4556 } /* ixgbe_sysctl_phy_temp */ 4557 4558 /************************************************************************ 4559 * ixgbe_sysctl_phy_overtemp_occurred 4560 * 4561 * Reports (directly from the PHY) whether the current PHY 4562 * temperature is over the overtemp threshold. 4563 ************************************************************************/ 4564 static int 4565 ixgbe_sysctl_phy_overtemp_occurred(SYSCTL_HANDLER_ARGS) 4566 { 4567 struct ixgbe_softc *sc = (struct ixgbe_softc *)arg1; 4568 struct ixgbe_hw *hw = &sc->hw; 4569 u16 reg; 4570 4571 if (hw->device_id != IXGBE_DEV_ID_X550EM_X_10G_T) { 4572 device_printf(iflib_get_dev(sc->ctx), 4573 "Device has no supported external thermal sensor.\n"); 4574 return (ENODEV); 4575 } 4576 4577 if (hw->phy.ops.read_reg(hw, IXGBE_PHY_OVERTEMP_STATUS, 4578 IXGBE_MDIO_VENDOR_SPECIFIC_1_DEV_TYPE, ®)) { 4579 device_printf(iflib_get_dev(sc->ctx), 4580 "Error reading from PHY's temperature status register\n"); 4581 return (EAGAIN); 4582 } 4583 4584 /* Get occurrence bit */ 4585 reg = !!(reg & 0x4000); 4586 4587 return (sysctl_handle_16(oidp, 0, reg, req)); 4588 } /* ixgbe_sysctl_phy_overtemp_occurred */ 4589 4590 /************************************************************************ 4591 * ixgbe_sysctl_eee_state 4592 * 4593 * Sysctl to set EEE power saving feature 4594 * Values: 4595 * 0 - disable EEE 4596 * 1 - enable EEE 4597 * (none) - get current device EEE state 4598 ************************************************************************/ 4599 static int 4600 ixgbe_sysctl_eee_state(SYSCTL_HANDLER_ARGS) 4601 { 4602 struct ixgbe_softc *sc = (struct ixgbe_softc *)arg1; 4603 device_t dev = sc->dev; 4604 if_t ifp = iflib_get_ifp(sc->ctx); 4605 int curr_eee, new_eee, error = 0; 4606 s32 retval; 4607 4608 curr_eee = new_eee = !!(sc->feat_en & IXGBE_FEATURE_EEE); 4609 4610 error = sysctl_handle_int(oidp, &new_eee, 0, req); 4611 if ((error) || (req->newptr == NULL)) 4612 return (error); 4613 4614 /* Nothing to do */ 4615 if (new_eee == curr_eee) 4616 return (0); 4617 4618 /* Not supported */ 4619 if (!(sc->feat_cap & IXGBE_FEATURE_EEE)) 4620 return (EINVAL); 4621 4622 /* Bounds checking */ 4623 if ((new_eee < 0) || (new_eee > 1)) 4624 return (EINVAL); 4625 4626 retval = ixgbe_setup_eee(&sc->hw, new_eee); 4627 if (retval) { 4628 device_printf(dev, "Error in EEE setup: 0x%08X\n", retval); 4629 return (EINVAL); 4630 } 4631 4632 /* Restart auto-neg */ 4633 if_init(ifp, ifp); 4634 4635 device_printf(dev, "New EEE state: %d\n", new_eee); 4636 4637 /* Cache new value */ 4638 if (new_eee) 4639 sc->feat_en |= IXGBE_FEATURE_EEE; 4640 else 4641 sc->feat_en &= ~IXGBE_FEATURE_EEE; 4642 4643 return (error); 4644 } /* ixgbe_sysctl_eee_state */ 4645 4646 /************************************************************************ 4647 * ixgbe_init_device_features 4648 ************************************************************************/ 4649 static void 4650 ixgbe_init_device_features(struct ixgbe_softc *sc) 4651 { 4652 sc->feat_cap = IXGBE_FEATURE_NETMAP 4653 | IXGBE_FEATURE_RSS 4654 | IXGBE_FEATURE_MSI 4655 | IXGBE_FEATURE_MSIX 4656 | IXGBE_FEATURE_LEGACY_IRQ; 4657 4658 /* Set capabilities first... */ 4659 switch (sc->hw.mac.type) { 4660 case ixgbe_mac_82598EB: 4661 if (sc->hw.device_id == IXGBE_DEV_ID_82598AT) 4662 sc->feat_cap |= IXGBE_FEATURE_FAN_FAIL; 4663 break; 4664 case ixgbe_mac_X540: 4665 sc->feat_cap |= IXGBE_FEATURE_SRIOV; 4666 sc->feat_cap |= IXGBE_FEATURE_FDIR; 4667 if ((sc->hw.device_id == IXGBE_DEV_ID_X540_BYPASS) && 4668 (sc->hw.bus.func == 0)) 4669 sc->feat_cap |= IXGBE_FEATURE_BYPASS; 4670 break; 4671 case ixgbe_mac_X550: 4672 sc->feat_cap |= IXGBE_FEATURE_TEMP_SENSOR; 4673 sc->feat_cap |= IXGBE_FEATURE_SRIOV; 4674 sc->feat_cap |= IXGBE_FEATURE_FDIR; 4675 break; 4676 case ixgbe_mac_X550EM_x: 4677 sc->feat_cap |= IXGBE_FEATURE_SRIOV; 4678 sc->feat_cap |= IXGBE_FEATURE_FDIR; 4679 break; 4680 case ixgbe_mac_X550EM_a: 4681 sc->feat_cap |= IXGBE_FEATURE_SRIOV; 4682 sc->feat_cap |= IXGBE_FEATURE_FDIR; 4683 sc->feat_cap &= ~IXGBE_FEATURE_LEGACY_IRQ; 4684 if ((sc->hw.device_id == IXGBE_DEV_ID_X550EM_A_1G_T) || 4685 (sc->hw.device_id == IXGBE_DEV_ID_X550EM_A_1G_T_L)) { 4686 sc->feat_cap |= IXGBE_FEATURE_TEMP_SENSOR; 4687 sc->feat_cap |= IXGBE_FEATURE_EEE; 4688 } 4689 break; 4690 case ixgbe_mac_82599EB: 4691 sc->feat_cap |= IXGBE_FEATURE_SRIOV; 4692 sc->feat_cap |= IXGBE_FEATURE_FDIR; 4693 if ((sc->hw.device_id == IXGBE_DEV_ID_82599_BYPASS) && 4694 (sc->hw.bus.func == 0)) 4695 sc->feat_cap |= IXGBE_FEATURE_BYPASS; 4696 if (sc->hw.device_id == IXGBE_DEV_ID_82599_QSFP_SF_QP) 4697 sc->feat_cap &= ~IXGBE_FEATURE_LEGACY_IRQ; 4698 break; 4699 default: 4700 break; 4701 } 4702 4703 /* Enabled by default... */ 4704 /* Fan failure detection */ 4705 if (sc->feat_cap & IXGBE_FEATURE_FAN_FAIL) 4706 sc->feat_en |= IXGBE_FEATURE_FAN_FAIL; 4707 /* Netmap */ 4708 if (sc->feat_cap & IXGBE_FEATURE_NETMAP) 4709 sc->feat_en |= IXGBE_FEATURE_NETMAP; 4710 /* EEE */ 4711 if (sc->feat_cap & IXGBE_FEATURE_EEE) 4712 sc->feat_en |= IXGBE_FEATURE_EEE; 4713 /* Thermal Sensor */ 4714 if (sc->feat_cap & IXGBE_FEATURE_TEMP_SENSOR) 4715 sc->feat_en |= IXGBE_FEATURE_TEMP_SENSOR; 4716 4717 /* Enabled via global sysctl... */ 4718 /* Flow Director */ 4719 if (ixgbe_enable_fdir) { 4720 if (sc->feat_cap & IXGBE_FEATURE_FDIR) 4721 sc->feat_en |= IXGBE_FEATURE_FDIR; 4722 else 4723 device_printf(sc->dev, "Device does not support Flow Director. Leaving disabled."); 4724 } 4725 /* 4726 * Message Signal Interrupts - Extended (MSI-X) 4727 * Normal MSI is only enabled if MSI-X calls fail. 4728 */ 4729 if (!ixgbe_enable_msix) 4730 sc->feat_cap &= ~IXGBE_FEATURE_MSIX; 4731 /* Receive-Side Scaling (RSS) */ 4732 if ((sc->feat_cap & IXGBE_FEATURE_RSS) && ixgbe_enable_rss) 4733 sc->feat_en |= IXGBE_FEATURE_RSS; 4734 4735 /* Disable features with unmet dependencies... */ 4736 /* No MSI-X */ 4737 if (!(sc->feat_cap & IXGBE_FEATURE_MSIX)) { 4738 sc->feat_cap &= ~IXGBE_FEATURE_RSS; 4739 sc->feat_cap &= ~IXGBE_FEATURE_SRIOV; 4740 sc->feat_en &= ~IXGBE_FEATURE_RSS; 4741 sc->feat_en &= ~IXGBE_FEATURE_SRIOV; 4742 } 4743 } /* ixgbe_init_device_features */ 4744 4745 /************************************************************************ 4746 * ixgbe_check_fan_failure 4747 ************************************************************************/ 4748 static void 4749 ixgbe_check_fan_failure(struct ixgbe_softc *sc, u32 reg, bool in_interrupt) 4750 { 4751 u32 mask; 4752 4753 mask = (in_interrupt) ? IXGBE_EICR_GPI_SDP1_BY_MAC(&sc->hw) : 4754 IXGBE_ESDP_SDP1; 4755 4756 if (reg & mask) 4757 device_printf(sc->dev, "\nCRITICAL: FAN FAILURE!! REPLACE IMMEDIATELY!!\n"); 4758 } /* ixgbe_check_fan_failure */ 4759 4760 /************************************************************************ 4761 * ixgbe_sbuf_fw_version 4762 ************************************************************************/ 4763 static void 4764 ixgbe_sbuf_fw_version(struct ixgbe_hw *hw, struct sbuf *buf) 4765 { 4766 struct ixgbe_nvm_version nvm_ver = {0}; 4767 uint16_t phyfw = 0; 4768 int status; 4769 const char *space = ""; 4770 4771 ixgbe_get_oem_prod_version(hw, &nvm_ver); /* OEM's NVM version */ 4772 ixgbe_get_orom_version(hw, &nvm_ver); /* Option ROM */ 4773 ixgbe_get_etk_id(hw, &nvm_ver); /* eTrack identifies a build in Intel's SCM */ 4774 status = ixgbe_get_phy_firmware_version(hw, &phyfw); 4775 4776 if (nvm_ver.oem_valid) { 4777 sbuf_printf(buf, "NVM OEM V%d.%d R%d", nvm_ver.oem_major, 4778 nvm_ver.oem_minor, nvm_ver.oem_release); 4779 space = " "; 4780 } 4781 4782 if (nvm_ver.or_valid) { 4783 sbuf_printf(buf, "%sOption ROM V%d-b%d-p%d", 4784 space, nvm_ver.or_major, nvm_ver.or_build, nvm_ver.or_patch); 4785 space = " "; 4786 } 4787 4788 if (nvm_ver.etk_id != ((NVM_VER_INVALID << NVM_ETK_SHIFT) | 4789 NVM_VER_INVALID)) { 4790 sbuf_printf(buf, "%seTrack 0x%08x", space, nvm_ver.etk_id); 4791 space = " "; 4792 } 4793 4794 if (phyfw != 0 && status == IXGBE_SUCCESS) 4795 sbuf_printf(buf, "%sPHY FW V%d", space, phyfw); 4796 } /* ixgbe_sbuf_fw_version */ 4797 4798 /************************************************************************ 4799 * ixgbe_print_fw_version 4800 ************************************************************************/ 4801 static void 4802 ixgbe_print_fw_version(if_ctx_t ctx) 4803 { 4804 struct ixgbe_softc *sc = iflib_get_softc(ctx); 4805 struct ixgbe_hw *hw = &sc->hw; 4806 device_t dev = sc->dev; 4807 struct sbuf *buf; 4808 int error = 0; 4809 4810 buf = sbuf_new_auto(); 4811 if (!buf) { 4812 device_printf(dev, "Could not allocate sbuf for output.\n"); 4813 return; 4814 } 4815 4816 ixgbe_sbuf_fw_version(hw, buf); 4817 4818 error = sbuf_finish(buf); 4819 if (error) 4820 device_printf(dev, "Error finishing sbuf: %d\n", error); 4821 else if (sbuf_len(buf)) 4822 device_printf(dev, "%s\n", sbuf_data(buf)); 4823 4824 sbuf_delete(buf); 4825 } /* ixgbe_print_fw_version */ 4826 4827 /************************************************************************ 4828 * ixgbe_sysctl_print_fw_version 4829 ************************************************************************/ 4830 static int 4831 ixgbe_sysctl_print_fw_version(SYSCTL_HANDLER_ARGS) 4832 { 4833 struct ixgbe_softc *sc = (struct ixgbe_softc *)arg1; 4834 struct ixgbe_hw *hw = &sc->hw; 4835 device_t dev = sc->dev; 4836 struct sbuf *buf; 4837 int error = 0; 4838 4839 buf = sbuf_new_for_sysctl(NULL, NULL, 128, req); 4840 if (!buf) { 4841 device_printf(dev, "Could not allocate sbuf for output.\n"); 4842 return (ENOMEM); 4843 } 4844 4845 ixgbe_sbuf_fw_version(hw, buf); 4846 4847 error = sbuf_finish(buf); 4848 if (error) 4849 device_printf(dev, "Error finishing sbuf: %d\n", error); 4850 4851 sbuf_delete(buf); 4852 4853 return (0); 4854 } /* ixgbe_sysctl_print_fw_version */ 4855