1 /* $FreeBSD$ */ 2 /* $OpenBSD: if_iwnreg.h,v 1.40 2010/05/05 19:41:57 damien Exp $ */ 3 4 /*- 5 * Copyright (c) 2007, 2008 6 * Damien Bergamini <damien.bergamini@free.fr> 7 * 8 * Permission to use, copy, modify, and distribute this software for any 9 * purpose with or without fee is hereby granted, provided that the above 10 * copyright notice and this permission notice appear in all copies. 11 * 12 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 13 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 14 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR 15 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 16 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN 17 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF 18 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 19 */ 20 21 #define IWN_TX_RING_COUNT 256 22 #define IWN_TX_RING_LOMARK 192 23 #define IWN_TX_RING_HIMARK 224 24 #define IWN_RX_RING_COUNT_LOG 6 25 #define IWN_RX_RING_COUNT (1 << IWN_RX_RING_COUNT_LOG) 26 27 #define IWN4965_NTXQUEUES 16 28 #define IWN5000_NTXQUEUES 20 29 30 #define IWN4965_FIRSTAGGQUEUE 7 31 #define IWN5000_FIRSTAGGQUEUE 10 32 33 #define IWN4965_NDMACHNLS 7 34 #define IWN5000_NDMACHNLS 8 35 36 #define IWN_SRVC_DMACHNL 9 37 38 #define IWN_ICT_SIZE 4096 39 #define IWN_ICT_COUNT (IWN_ICT_SIZE / sizeof (uint32_t)) 40 41 /* Maximum number of DMA segments for TX. */ 42 #define IWN_MAX_SCATTER 20 43 44 /* RX buffers must be large enough to hold a full 4K A-MPDU. */ 45 #define IWN_RBUF_SIZE (4 * 1024) 46 47 #if defined(__LP64__) 48 /* HW supports 36-bit DMA addresses. */ 49 #define IWN_LOADDR(paddr) ((uint32_t)(paddr)) 50 #define IWN_HIADDR(paddr) (((paddr) >> 32) & 0xf) 51 #else 52 #define IWN_LOADDR(paddr) (paddr) 53 #define IWN_HIADDR(paddr) (0) 54 #endif 55 56 /* 57 * Control and status registers. 58 */ 59 #define IWN_HW_IF_CONFIG 0x000 60 #define IWN_INT_COALESCING 0x004 61 #define IWN_INT_PERIODIC 0x005 /* use IWN_WRITE_1 */ 62 #define IWN_INT 0x008 63 #define IWN_INT_MASK 0x00c 64 #define IWN_FH_INT 0x010 65 #define IWN_RESET 0x020 66 #define IWN_GP_CNTRL 0x024 67 #define IWN_HW_REV 0x028 68 #define IWN_EEPROM 0x02c 69 #define IWN_EEPROM_GP 0x030 70 #define IWN_OTP_GP 0x034 71 #define IWN_GIO 0x03c 72 #define IWN_GP_DRIVER 0x050 73 #define IWN_UCODE_GP1_CLR 0x05c 74 #define IWN_LED 0x094 75 #define IWN_DRAM_INT_TBL 0x0a0 76 #define IWN_SHADOW_REG_CTRL 0x0a8 77 #define IWN_GIO_CHICKEN 0x100 78 #define IWN_ANA_PLL 0x20c 79 #define IWN_HW_REV_WA 0x22c 80 #define IWN_DBG_HPET_MEM 0x240 81 #define IWN_DBG_LINK_PWR_MGMT 0x250 82 #define IWN_MEM_RADDR 0x40c 83 #define IWN_MEM_WADDR 0x410 84 #define IWN_MEM_WDATA 0x418 85 #define IWN_MEM_RDATA 0x41c 86 #define IWN_PRPH_WADDR 0x444 87 #define IWN_PRPH_RADDR 0x448 88 #define IWN_PRPH_WDATA 0x44c 89 #define IWN_PRPH_RDATA 0x450 90 #define IWN_HBUS_TARG_WRPTR 0x460 91 92 /* 93 * Flow-Handler registers. 94 */ 95 #define IWN_FH_TFBD_CTRL0(qid) (0x1900 + (qid) * 8) 96 #define IWN_FH_TFBD_CTRL1(qid) (0x1904 + (qid) * 8) 97 #define IWN_FH_KW_ADDR 0x197c 98 #define IWN_FH_SRAM_ADDR(qid) (0x19a4 + (qid) * 4) 99 #define IWN_FH_CBBC_QUEUE(qid) (0x19d0 + (qid) * 4) 100 #define IWN_FH_STATUS_WPTR 0x1bc0 101 #define IWN_FH_RX_BASE 0x1bc4 102 #define IWN_FH_RX_WPTR 0x1bc8 103 #define IWN_FH_RX_CONFIG 0x1c00 104 #define IWN_FH_RX_STATUS 0x1c44 105 #define IWN_FH_TX_CONFIG(qid) (0x1d00 + (qid) * 32) 106 #define IWN_FH_TXBUF_STATUS(qid) (0x1d08 + (qid) * 32) 107 #define IWN_FH_TX_CHICKEN 0x1e98 108 #define IWN_FH_TX_STATUS 0x1eb0 109 110 /* 111 * TX scheduler registers. 112 */ 113 #define IWN_SCHED_BASE 0xa02c00 114 #define IWN_SCHED_SRAM_ADDR (IWN_SCHED_BASE + 0x000) 115 #define IWN5000_SCHED_DRAM_ADDR (IWN_SCHED_BASE + 0x008) 116 #define IWN4965_SCHED_DRAM_ADDR (IWN_SCHED_BASE + 0x010) 117 #define IWN5000_SCHED_TXFACT (IWN_SCHED_BASE + 0x010) 118 #define IWN4965_SCHED_TXFACT (IWN_SCHED_BASE + 0x01c) 119 #define IWN4965_SCHED_QUEUE_RDPTR(qid) (IWN_SCHED_BASE + 0x064 + (qid) * 4) 120 #define IWN5000_SCHED_QUEUE_RDPTR(qid) (IWN_SCHED_BASE + 0x068 + (qid) * 4) 121 #define IWN4965_SCHED_QCHAIN_SEL (IWN_SCHED_BASE + 0x0d0) 122 #define IWN4965_SCHED_INTR_MASK (IWN_SCHED_BASE + 0x0e4) 123 #define IWN5000_SCHED_QCHAIN_SEL (IWN_SCHED_BASE + 0x0e8) 124 #define IWN4965_SCHED_QUEUE_STATUS(qid) (IWN_SCHED_BASE + 0x104 + (qid) * 4) 125 #define IWN5000_SCHED_INTR_MASK (IWN_SCHED_BASE + 0x108) 126 #define IWN5000_SCHED_QUEUE_STATUS(qid) (IWN_SCHED_BASE + 0x10c + (qid) * 4) 127 #define IWN5000_SCHED_AGGR_SEL (IWN_SCHED_BASE + 0x248) 128 129 /* 130 * Offsets in TX scheduler's SRAM. 131 */ 132 #define IWN4965_SCHED_CTX_OFF 0x380 133 #define IWN4965_SCHED_CTX_LEN 416 134 #define IWN4965_SCHED_QUEUE_OFFSET(qid) (0x380 + (qid) * 8) 135 #define IWN4965_SCHED_TRANS_TBL(qid) (0x500 + (qid) * 2) 136 #define IWN5000_SCHED_CTX_OFF 0x600 137 #define IWN5000_SCHED_CTX_LEN 520 138 #define IWN5000_SCHED_QUEUE_OFFSET(qid) (0x600 + (qid) * 8) 139 #define IWN5000_SCHED_TRANS_TBL(qid) (0x7e0 + (qid) * 2) 140 141 /* 142 * NIC internal memory offsets. 143 */ 144 #define IWN_APMG_CLK_CTRL 0x3000 145 #define IWN_APMG_CLK_EN 0x3004 146 #define IWN_APMG_CLK_DIS 0x3008 147 #define IWN_APMG_PS 0x300c 148 #define IWN_APMG_DIGITAL_SVR 0x3058 149 #define IWN_APMG_ANALOG_SVR 0x306c 150 #define IWN_APMG_PCI_STT 0x3010 151 #define IWN_BSM_WR_CTRL 0x3400 152 #define IWN_BSM_WR_MEM_SRC 0x3404 153 #define IWN_BSM_WR_MEM_DST 0x3408 154 #define IWN_BSM_WR_DWCOUNT 0x340c 155 #define IWN_BSM_DRAM_TEXT_ADDR 0x3490 156 #define IWN_BSM_DRAM_TEXT_SIZE 0x3494 157 #define IWN_BSM_DRAM_DATA_ADDR 0x3498 158 #define IWN_BSM_DRAM_DATA_SIZE 0x349c 159 #define IWN_BSM_SRAM_BASE 0x3800 160 161 /* Possible flags for register IWN_HW_IF_CONFIG. */ 162 #define IWN_HW_IF_CONFIG_4965_R (1 << 4) 163 #define IWN_HW_IF_CONFIG_MAC_SI (1 << 8) 164 #define IWN_HW_IF_CONFIG_RADIO_SI (1 << 9) 165 #define IWN_HW_IF_CONFIG_EEPROM_LOCKED (1 << 21) 166 #define IWN_HW_IF_CONFIG_NIC_READY (1 << 22) 167 #define IWN_HW_IF_CONFIG_HAP_WAKE_L1A (1 << 23) 168 #define IWN_HW_IF_CONFIG_PREPARE_DONE (1 << 25) 169 #define IWN_HW_IF_CONFIG_PREPARE (1 << 27) 170 171 /* Possible values for register IWN_INT_PERIODIC. */ 172 #define IWN_INT_PERIODIC_DIS 0x00 173 #define IWN_INT_PERIODIC_ENA 0xff 174 175 /* Possible flags for registers IWN_PRPH_RADDR/IWN_PRPH_WADDR. */ 176 #define IWN_PRPH_DWORD ((sizeof (uint32_t) - 1) << 24) 177 178 /* Possible values for IWN_BSM_WR_MEM_DST. */ 179 #define IWN_FW_TEXT_BASE 0x00000000 180 #define IWN_FW_DATA_BASE 0x00800000 181 182 /* Possible flags for register IWN_RESET. */ 183 #define IWN_RESET_NEVO (1 << 0) 184 #define IWN_RESET_SW (1 << 7) 185 #define IWN_RESET_MASTER_DISABLED (1 << 8) 186 #define IWN_RESET_STOP_MASTER (1 << 9) 187 #define IWN_RESET_LINK_PWR_MGMT_DIS (1 << 31) 188 189 /* Possible flags for register IWN_GP_CNTRL. */ 190 #define IWN_GP_CNTRL_MAC_ACCESS_ENA (1 << 0) 191 #define IWN_GP_CNTRL_MAC_CLOCK_READY (1 << 0) 192 #define IWN_GP_CNTRL_INIT_DONE (1 << 2) 193 #define IWN_GP_CNTRL_MAC_ACCESS_REQ (1 << 3) 194 #define IWN_GP_CNTRL_SLEEP (1 << 4) 195 #define IWN_GP_CNTRL_RFKILL (1 << 27) 196 197 /* Possible flags for register IWN_HW_REV. */ 198 #define IWN_HW_REV_TYPE_SHIFT 4 199 #define IWN_HW_REV_TYPE_MASK 0x000000f0 200 #define IWN_HW_REV_TYPE_4965 0 201 #define IWN_HW_REV_TYPE_5300 2 202 #define IWN_HW_REV_TYPE_5350 3 203 #define IWN_HW_REV_TYPE_5150 4 204 #define IWN_HW_REV_TYPE_5100 5 205 #define IWN_HW_REV_TYPE_1000 6 206 #define IWN_HW_REV_TYPE_6000 7 207 #define IWN_HW_REV_TYPE_6050 8 208 #define IWN_HW_REV_TYPE_6005 11 209 210 /* Possible flags for register IWN_GIO_CHICKEN. */ 211 #define IWN_GIO_CHICKEN_L1A_NO_L0S_RX (1 << 23) 212 #define IWN_GIO_CHICKEN_DIS_L0S_TIMER (1 << 29) 213 214 /* Possible flags for register IWN_GIO. */ 215 #define IWN_GIO_L0S_ENA (1 << 1) 216 217 /* Possible flags for register IWN_GP_DRIVER. */ 218 #define IWN_GP_DRIVER_RADIO_3X3_HYB (0 << 0) 219 #define IWN_GP_DRIVER_RADIO_2X2_HYB (1 << 0) 220 #define IWN_GP_DRIVER_RADIO_2X2_IPA (2 << 0) 221 #define IWN_GP_DRIVER_CALIB_VER6 (1 << 2) 222 #define IWN_GP_DRIVER_6050_1X2 (1 << 3) 223 224 /* Possible flags for register IWN_UCODE_GP1_CLR. */ 225 #define IWN_UCODE_GP1_RFKILL (1 << 1) 226 #define IWN_UCODE_GP1_CMD_BLOCKED (1 << 2) 227 #define IWN_UCODE_GP1_CTEMP_STOP_RF (1 << 3) 228 229 /* Possible flags/values for register IWN_LED. */ 230 #define IWN_LED_BSM_CTRL (1 << 5) 231 #define IWN_LED_OFF 0x00000038 232 #define IWN_LED_ON 0x00000078 233 234 /* Possible flags for register IWN_DRAM_INT_TBL. */ 235 #define IWN_DRAM_INT_TBL_WRAP_CHECK (1 << 27) 236 #define IWN_DRAM_INT_TBL_ENABLE (1 << 31) 237 238 /* Possible values for register IWN_ANA_PLL. */ 239 #define IWN_ANA_PLL_INIT 0x00880300 240 241 /* Possible flags for register IWN_FH_RX_STATUS. */ 242 #define IWN_FH_RX_STATUS_IDLE (1 << 24) 243 244 /* Possible flags for register IWN_BSM_WR_CTRL. */ 245 #define IWN_BSM_WR_CTRL_START_EN (1 << 30) 246 #define IWN_BSM_WR_CTRL_START (1 << 31) 247 248 /* Possible flags for register IWN_INT. */ 249 #define IWN_INT_ALIVE (1 << 0) 250 #define IWN_INT_WAKEUP (1 << 1) 251 #define IWN_INT_SW_RX (1 << 3) 252 #define IWN_INT_CT_REACHED (1 << 6) 253 #define IWN_INT_RF_TOGGLED (1 << 7) 254 #define IWN_INT_SW_ERR (1 << 25) 255 #define IWN_INT_SCHED (1 << 26) 256 #define IWN_INT_FH_TX (1 << 27) 257 #define IWN_INT_RX_PERIODIC (1 << 28) 258 #define IWN_INT_HW_ERR (1 << 29) 259 #define IWN_INT_FH_RX (1 << 31) 260 261 /* Shortcut. */ 262 #define IWN_INT_MASK_DEF \ 263 (IWN_INT_SW_ERR | IWN_INT_HW_ERR | IWN_INT_FH_TX | \ 264 IWN_INT_FH_RX | IWN_INT_ALIVE | IWN_INT_WAKEUP | \ 265 IWN_INT_SW_RX | IWN_INT_CT_REACHED | IWN_INT_RF_TOGGLED) 266 267 /* Possible flags for register IWN_FH_INT. */ 268 #define IWN_FH_INT_TX_CHNL(x) (1 << (x)) 269 #define IWN_FH_INT_RX_CHNL(x) (1 << ((x) + 16)) 270 #define IWN_FH_INT_HI_PRIOR (1 << 30) 271 /* Shortcuts for the above. */ 272 #define IWN_FH_INT_TX \ 273 (IWN_FH_INT_TX_CHNL(0) | IWN_FH_INT_TX_CHNL(1)) 274 #define IWN_FH_INT_RX \ 275 (IWN_FH_INT_RX_CHNL(0) | IWN_FH_INT_RX_CHNL(1) | IWN_FH_INT_HI_PRIOR) 276 277 /* Possible flags/values for register IWN_FH_TX_CONFIG. */ 278 #define IWN_FH_TX_CONFIG_DMA_PAUSE 0 279 #define IWN_FH_TX_CONFIG_DMA_ENA (1 << 31) 280 #define IWN_FH_TX_CONFIG_CIRQ_HOST_ENDTFD (1 << 20) 281 282 /* Possible flags/values for register IWN_FH_TXBUF_STATUS. */ 283 #define IWN_FH_TXBUF_STATUS_TBNUM(x) ((x) << 20) 284 #define IWN_FH_TXBUF_STATUS_TBIDX(x) ((x) << 12) 285 #define IWN_FH_TXBUF_STATUS_TFBD_VALID 3 286 287 /* Possible flags for register IWN_FH_TX_CHICKEN. */ 288 #define IWN_FH_TX_CHICKEN_SCHED_RETRY (1 << 1) 289 290 /* Possible flags for register IWN_FH_TX_STATUS. */ 291 #define IWN_FH_TX_STATUS_IDLE(chnl) (1 << ((chnl) + 16)) 292 293 /* Possible flags for register IWN_FH_RX_CONFIG. */ 294 #define IWN_FH_RX_CONFIG_ENA (1 << 31) 295 #define IWN_FH_RX_CONFIG_NRBD(x) ((x) << 20) 296 #define IWN_FH_RX_CONFIG_RB_SIZE_8K (1 << 16) 297 #define IWN_FH_RX_CONFIG_SINGLE_FRAME (1 << 15) 298 #define IWN_FH_RX_CONFIG_IRQ_DST_HOST (1 << 12) 299 #define IWN_FH_RX_CONFIG_RB_TIMEOUT(x) ((x) << 4) 300 #define IWN_FH_RX_CONFIG_IGN_RXF_EMPTY (1 << 2) 301 302 /* Possible flags for register IWN_FH_TX_CONFIG. */ 303 #define IWN_FH_TX_CONFIG_DMA_ENA (1 << 31) 304 #define IWN_FH_TX_CONFIG_DMA_CREDIT_ENA (1 << 3) 305 306 /* Possible flags for register IWN_EEPROM. */ 307 #define IWN_EEPROM_READ_VALID (1 << 0) 308 #define IWN_EEPROM_CMD (1 << 1) 309 310 /* Possible flags for register IWN_EEPROM_GP. */ 311 #define IWN_EEPROM_GP_IF_OWNER 0x00000180 312 313 /* Possible flags for register IWN_OTP_GP. */ 314 #define IWN_OTP_GP_DEV_SEL_OTP (1 << 16) 315 #define IWN_OTP_GP_RELATIVE_ACCESS (1 << 17) 316 #define IWN_OTP_GP_ECC_CORR_STTS (1 << 20) 317 #define IWN_OTP_GP_ECC_UNCORR_STTS (1 << 21) 318 319 /* Possible flags for register IWN_SCHED_QUEUE_STATUS. */ 320 #define IWN4965_TXQ_STATUS_ACTIVE 0x0007fc01 321 #define IWN4965_TXQ_STATUS_INACTIVE 0x0007fc00 322 #define IWN4965_TXQ_STATUS_AGGR_ENA (1 << 5 | 1 << 8) 323 #define IWN4965_TXQ_STATUS_CHGACT (1 << 10) 324 #define IWN5000_TXQ_STATUS_ACTIVE 0x00ff0018 325 #define IWN5000_TXQ_STATUS_INACTIVE 0x00ff0010 326 #define IWN5000_TXQ_STATUS_CHGACT (1 << 19) 327 328 /* Possible flags for registers IWN_APMG_CLK_*. */ 329 #define IWN_APMG_CLK_CTRL_DMA_CLK_RQT (1 << 9) 330 #define IWN_APMG_CLK_CTRL_BSM_CLK_RQT (1 << 11) 331 332 /* Possible flags for register IWN_APMG_PS. */ 333 #define IWN_APMG_PS_EARLY_PWROFF_DIS (1 << 22) 334 #define IWN_APMG_PS_PWR_SRC(x) ((x) << 24) 335 #define IWN_APMG_PS_PWR_SRC_VMAIN 0 336 #define IWN_APMG_PS_PWR_SRC_VAUX 2 337 #define IWN_APMG_PS_PWR_SRC_MASK IWN_APMG_PS_PWR_SRC(3) 338 #define IWN_APMG_PS_RESET_REQ (1 << 26) 339 340 /* Possible flags for register IWN_APMG_DIGITAL_SVR. */ 341 #define IWN_APMG_DIGITAL_SVR_VOLTAGE(x) (((x) & 0xf) << 5) 342 #define IWN_APMG_DIGITAL_SVR_VOLTAGE_MASK \ 343 IWN_APMG_DIGITAL_SVR_VOLTAGE(0xf) 344 #define IWN_APMG_DIGITAL_SVR_VOLTAGE_1_32 \ 345 IWN_APMG_DIGITAL_SVR_VOLTAGE(3) 346 347 /* Possible flags for IWN_APMG_PCI_STT. */ 348 #define IWN_APMG_PCI_STT_L1A_DIS (1 << 11) 349 350 /* Possible flags for register IWN_BSM_DRAM_TEXT_SIZE. */ 351 #define IWN_FW_UPDATED (1 << 31) 352 353 #define IWN_SCHED_WINSZ 64 354 #define IWN_SCHED_LIMIT 64 355 #define IWN4965_SCHED_COUNT 512 356 #define IWN5000_SCHED_COUNT (IWN_TX_RING_COUNT + IWN_SCHED_WINSZ) 357 #define IWN4965_SCHEDSZ (IWN4965_NTXQUEUES * IWN4965_SCHED_COUNT * 2) 358 #define IWN5000_SCHEDSZ (IWN5000_NTXQUEUES * IWN5000_SCHED_COUNT * 2) 359 360 struct iwn_tx_desc { 361 uint8_t reserved1[3]; 362 uint8_t nsegs; 363 struct { 364 uint32_t addr; 365 uint16_t len; 366 } __packed segs[IWN_MAX_SCATTER]; 367 /* Pad to 128 bytes. */ 368 uint32_t reserved2; 369 } __packed; 370 371 struct iwn_rx_status { 372 uint16_t closed_count; 373 uint16_t closed_rx_count; 374 uint16_t finished_count; 375 uint16_t finished_rx_count; 376 uint32_t reserved[2]; 377 } __packed; 378 379 struct iwn_rx_desc { 380 uint32_t len; 381 uint8_t type; 382 #define IWN_UC_READY 1 383 #define IWN_ADD_NODE_DONE 24 384 #define IWN_TX_DONE 28 385 #define IWN5000_CALIBRATION_RESULT 102 386 #define IWN5000_CALIBRATION_DONE 103 387 #define IWN_START_SCAN 130 388 #define IWN_STOP_SCAN 132 389 #define IWN_RX_STATISTICS 156 390 #define IWN_BEACON_STATISTICS 157 391 #define IWN_STATE_CHANGED 161 392 #define IWN_BEACON_MISSED 162 393 #define IWN_RX_PHY 192 394 #define IWN_MPDU_RX_DONE 193 395 #define IWN_RX_DONE 195 396 #define IWN_RX_COMPRESSED_BA 197 397 398 uint8_t flags; 399 uint8_t idx; 400 uint8_t qid; 401 } __packed; 402 403 /* Possible RX status flags. */ 404 #define IWN_RX_NO_CRC_ERR (1 << 0) 405 #define IWN_RX_NO_OVFL_ERR (1 << 1) 406 /* Shortcut for the above. */ 407 #define IWN_RX_NOERROR (IWN_RX_NO_CRC_ERR | IWN_RX_NO_OVFL_ERR) 408 #define IWN_RX_MPDU_MIC_OK (1 << 6) 409 #define IWN_RX_CIPHER_MASK (7 << 8) 410 #define IWN_RX_CIPHER_CCMP (2 << 8) 411 #define IWN_RX_MPDU_DEC (1 << 11) 412 #define IWN_RX_DECRYPT_MASK (3 << 11) 413 #define IWN_RX_DECRYPT_OK (3 << 11) 414 415 struct iwn_tx_cmd { 416 uint8_t code; 417 #define IWN_CMD_RXON 16 418 #define IWN_CMD_RXON_ASSOC 17 419 #define IWN_CMD_EDCA_PARAMS 19 420 #define IWN_CMD_TIMING 20 421 #define IWN_CMD_ADD_NODE 24 422 #define IWN_CMD_TX_DATA 28 423 #define IWN_CMD_LINK_QUALITY 78 424 #define IWN_CMD_SET_LED 72 425 #define IWN5000_CMD_WIMAX_COEX 90 426 #define IWN5000_CMD_CALIB_CONFIG 101 427 #define IWN5000_CMD_CALIB_RESULT 102 428 #define IWN5000_CMD_CALIB_COMPLETE 103 429 #define IWN_CMD_SET_POWER_MODE 119 430 #define IWN_CMD_SCAN 128 431 #define IWN_CMD_SCAN_RESULTS 131 432 #define IWN_CMD_TXPOWER_DBM 149 433 #define IWN_CMD_TXPOWER 151 434 #define IWN5000_CMD_TX_ANT_CONFIG 152 435 #define IWN_CMD_BT_COEX 155 436 #define IWN_CMD_GET_STATISTICS 156 437 #define IWN_CMD_SET_CRITICAL_TEMP 164 438 #define IWN_CMD_SET_SENSITIVITY 168 439 #define IWN_CMD_PHY_CALIB 176 440 #define IWN_CMD_BT_COEX_PRIOTABLE 204 441 #define IWN_CMD_BT_COEX_PROT 205 442 443 uint8_t flags; 444 uint8_t idx; 445 uint8_t qid; 446 uint8_t data[136]; 447 } __packed; 448 449 /* Antenna flags, used in various commands. */ 450 #define IWN_ANT_A (1 << 0) 451 #define IWN_ANT_B (1 << 1) 452 #define IWN_ANT_C (1 << 2) 453 /* Shortcuts. */ 454 #define IWN_ANT_AB (IWN_ANT_A | IWN_ANT_B) 455 #define IWN_ANT_BC (IWN_ANT_B | IWN_ANT_C) 456 #define IWN_ANT_ABC (IWN_ANT_A | IWN_ANT_B | IWN_ANT_C) 457 458 /* Structure for command IWN_CMD_RXON. */ 459 struct iwn_rxon { 460 uint8_t myaddr[IEEE80211_ADDR_LEN]; 461 uint16_t reserved1; 462 uint8_t bssid[IEEE80211_ADDR_LEN]; 463 uint16_t reserved2; 464 uint8_t wlap[IEEE80211_ADDR_LEN]; 465 uint16_t reserved3; 466 uint8_t mode; 467 #define IWN_MODE_HOSTAP 1 468 #define IWN_MODE_STA 3 469 #define IWN_MODE_IBSS 4 470 #define IWN_MODE_MONITOR 6 471 472 uint8_t air; 473 uint16_t rxchain; 474 #define IWN_RXCHAIN_DRIVER_FORCE (1 << 0) 475 #define IWN_RXCHAIN_VALID(x) (((x) & IWN_ANT_ABC) << 1) 476 #define IWN_RXCHAIN_FORCE_SEL(x) (((x) & IWN_ANT_ABC) << 4) 477 #define IWN_RXCHAIN_FORCE_MIMO_SEL(x) (((x) & IWN_ANT_ABC) << 7) 478 #define IWN_RXCHAIN_IDLE_COUNT(x) ((x) << 10) 479 #define IWN_RXCHAIN_MIMO_COUNT(x) ((x) << 12) 480 #define IWN_RXCHAIN_MIMO_FORCE (1 << 14) 481 482 uint8_t ofdm_mask; 483 uint8_t cck_mask; 484 uint16_t associd; 485 uint32_t flags; 486 #define IWN_RXON_24GHZ (1 << 0) 487 #define IWN_RXON_CCK (1 << 1) 488 #define IWN_RXON_AUTO (1 << 2) 489 #define IWN_RXON_SHSLOT (1 << 4) 490 #define IWN_RXON_SHPREAMBLE (1 << 5) 491 #define IWN_RXON_NODIVERSITY (1 << 7) 492 #define IWN_RXON_ANTENNA_A (1 << 8) 493 #define IWN_RXON_ANTENNA_B (1 << 9) 494 #define IWN_RXON_TSF (1 << 15) 495 #define IWN_RXON_HT_HT40MINUS (1 << 22) 496 #define IWN_RXON_HT_PROTMODE(x) (x << 23) 497 #define IWN_RXON_HT_MODEPURE40 (1 << 25) 498 #define IWN_RXON_HT_MODEMIXED (2 << 25) 499 #define IWN_RXON_CTS_TO_SELF (1 << 30) 500 501 uint32_t filter; 502 #define IWN_FILTER_PROMISC (1 << 0) 503 #define IWN_FILTER_CTL (1 << 1) 504 #define IWN_FILTER_MULTICAST (1 << 2) 505 #define IWN_FILTER_NODECRYPT (1 << 3) 506 #define IWN_FILTER_BSS (1 << 5) 507 #define IWN_FILTER_BEACON (1 << 6) 508 509 uint8_t chan; 510 uint8_t reserved4; 511 uint8_t ht_single_mask; 512 uint8_t ht_dual_mask; 513 /* The following fields are for >=5000 Series only. */ 514 uint8_t ht_triple_mask; 515 uint8_t reserved5; 516 uint16_t acquisition; 517 uint16_t reserved6; 518 } __packed; 519 520 #define IWN4965_RXONSZ (sizeof (struct iwn_rxon) - 6) 521 #define IWN5000_RXONSZ (sizeof (struct iwn_rxon)) 522 523 /* Structure for command IWN_CMD_ASSOCIATE. */ 524 struct iwn_assoc { 525 uint32_t flags; 526 uint32_t filter; 527 uint8_t ofdm_mask; 528 uint8_t cck_mask; 529 uint16_t reserved; 530 } __packed; 531 532 /* Structure for command IWN_CMD_EDCA_PARAMS. */ 533 struct iwn_edca_params { 534 uint32_t flags; 535 #define IWN_EDCA_UPDATE (1 << 0) 536 #define IWN_EDCA_TXOP (1 << 4) 537 538 struct { 539 uint16_t cwmin; 540 uint16_t cwmax; 541 uint8_t aifsn; 542 uint8_t reserved; 543 uint16_t txoplimit; 544 } __packed ac[WME_NUM_AC]; 545 } __packed; 546 547 /* Structure for command IWN_CMD_TIMING. */ 548 struct iwn_cmd_timing { 549 uint64_t tstamp; 550 uint16_t bintval; 551 uint16_t atim; 552 uint32_t binitval; 553 uint16_t lintval; 554 uint16_t reserved; 555 } __packed; 556 557 /* Structure for command IWN_CMD_ADD_NODE. */ 558 struct iwn_node_info { 559 uint8_t control; 560 #define IWN_NODE_UPDATE (1 << 0) 561 562 uint8_t reserved1[3]; 563 564 uint8_t macaddr[IEEE80211_ADDR_LEN]; 565 uint16_t reserved2; 566 uint8_t id; 567 #define IWN_ID_BSS 0 568 #define IWN5000_ID_BROADCAST 15 569 #define IWN4965_ID_BROADCAST 31 570 571 uint8_t flags; 572 #define IWN_FLAG_SET_KEY (1 << 0) 573 #define IWN_FLAG_SET_DISABLE_TID (1 << 1) 574 #define IWN_FLAG_SET_TXRATE (1 << 2) 575 #define IWN_FLAG_SET_ADDBA (1 << 3) 576 #define IWN_FLAG_SET_DELBA (1 << 4) 577 578 uint16_t reserved3; 579 uint16_t kflags; 580 #define IWN_KFLAG_CCMP (1 << 1) 581 #define IWN_KFLAG_MAP (1 << 3) 582 #define IWN_KFLAG_KID(kid) ((kid) << 8) 583 #define IWN_KFLAG_INVALID (1 << 11) 584 #define IWN_KFLAG_GROUP (1 << 14) 585 586 uint8_t tsc2; /* TKIP TSC2 */ 587 uint8_t reserved4; 588 uint16_t ttak[5]; 589 uint8_t kid; 590 uint8_t reserved5; 591 uint8_t key[16]; 592 /* The following 3 fields are for 5000 Series only. */ 593 uint64_t tsc; 594 uint8_t rxmic[8]; 595 uint8_t txmic[8]; 596 597 uint32_t htflags; 598 #define IWN_SMPS_MIMO_PROT (1 << 17) 599 #define IWN_AMDPU_SIZE_FACTOR(x) ((x) << 19) 600 #define IWN_NODE_HT40 (1 << 21) 601 #define IWN_SMPS_MIMO_DIS (1 << 22) 602 #define IWN_AMDPU_DENSITY(x) ((x) << 23) 603 604 uint32_t mask; 605 uint16_t disable_tid; 606 uint16_t reserved6; 607 uint8_t addba_tid; 608 uint8_t delba_tid; 609 uint16_t addba_ssn; 610 uint32_t reserved7; 611 } __packed; 612 613 struct iwn4965_node_info { 614 uint8_t control; 615 uint8_t reserved1[3]; 616 uint8_t macaddr[IEEE80211_ADDR_LEN]; 617 uint16_t reserved2; 618 uint8_t id; 619 uint8_t flags; 620 uint16_t reserved3; 621 uint16_t kflags; 622 uint8_t tsc2; /* TKIP TSC2 */ 623 uint8_t reserved4; 624 uint16_t ttak[5]; 625 uint8_t kid; 626 uint8_t reserved5; 627 uint8_t key[16]; 628 uint32_t htflags; 629 uint32_t mask; 630 uint16_t disable_tid; 631 uint16_t reserved6; 632 uint8_t addba_tid; 633 uint8_t delba_tid; 634 uint16_t addba_ssn; 635 uint32_t reserved7; 636 } __packed; 637 638 #define IWN_RFLAG_MCS (1 << 8) 639 #define IWN_RFLAG_CCK (1 << 9) 640 #define IWN_RFLAG_GREENFIELD (1 << 10) 641 #define IWN_RFLAG_HT40 (1 << 11) 642 #define IWN_RFLAG_DUPLICATE (1 << 12) 643 #define IWN_RFLAG_SGI (1 << 13) 644 #define IWN_RFLAG_ANT(x) ((x) << 14) 645 646 /* Structure for command IWN_CMD_TX_DATA. */ 647 struct iwn_cmd_data { 648 uint16_t len; 649 uint16_t lnext; 650 uint32_t flags; 651 #define IWN_TX_NEED_PROTECTION (1 << 0) /* 5000 only */ 652 #define IWN_TX_NEED_RTS (1 << 1) 653 #define IWN_TX_NEED_CTS (1 << 2) 654 #define IWN_TX_NEED_ACK (1 << 3) 655 #define IWN_TX_LINKQ (1 << 4) 656 #define IWN_TX_IMM_BA (1 << 6) 657 #define IWN_TX_FULL_TXOP (1 << 7) 658 #define IWN_TX_BT_DISABLE (1 << 12) /* bluetooth coexistence */ 659 #define IWN_TX_AUTO_SEQ (1 << 13) 660 #define IWN_TX_MORE_FRAG (1 << 14) 661 #define IWN_TX_INSERT_TSTAMP (1 << 16) 662 #define IWN_TX_NEED_PADDING (1 << 20) 663 664 uint32_t scratch; 665 uint32_t rate; 666 667 uint8_t id; 668 uint8_t security; 669 #define IWN_CIPHER_WEP40 1 670 #define IWN_CIPHER_CCMP 2 671 #define IWN_CIPHER_TKIP 3 672 #define IWN_CIPHER_WEP104 9 673 674 uint8_t linkq; 675 uint8_t reserved2; 676 uint8_t key[16]; 677 uint16_t fnext; 678 uint16_t reserved3; 679 uint32_t lifetime; 680 #define IWN_LIFETIME_INFINITE 0xffffffff 681 682 uint32_t loaddr; 683 uint8_t hiaddr; 684 uint8_t rts_ntries; 685 uint8_t data_ntries; 686 uint8_t tid; 687 uint16_t timeout; 688 uint16_t txop; 689 } __packed; 690 691 /* Structure for command IWN_CMD_LINK_QUALITY. */ 692 #define IWN_MAX_TX_RETRIES 16 693 struct iwn_cmd_link_quality { 694 uint8_t id; 695 uint8_t reserved1; 696 uint16_t ctl; 697 uint8_t flags; 698 uint8_t mimo; 699 uint8_t antmsk_1stream; 700 uint8_t antmsk_2stream; 701 uint8_t ridx[WME_NUM_AC]; 702 uint16_t ampdu_limit; 703 uint8_t ampdu_threshold; 704 uint8_t ampdu_max; 705 uint32_t reserved2; 706 uint32_t retry[IWN_MAX_TX_RETRIES]; 707 uint32_t reserved3; 708 } __packed; 709 710 /* Structure for command IWN_CMD_SET_LED. */ 711 struct iwn_cmd_led { 712 uint32_t unit; /* multiplier (in usecs) */ 713 uint8_t which; 714 #define IWN_LED_ACTIVITY 1 715 #define IWN_LED_LINK 2 716 717 uint8_t off; 718 uint8_t on; 719 uint8_t reserved; 720 } __packed; 721 722 /* Structure for command IWN5000_CMD_WIMAX_COEX. */ 723 struct iwn5000_wimax_coex { 724 uint32_t flags; 725 #define IWN_WIMAX_COEX_STA_TABLE_VALID (1 << 0) 726 #define IWN_WIMAX_COEX_UNASSOC_WA_UNMASK (1 << 2) 727 #define IWN_WIMAX_COEX_ASSOC_WA_UNMASK (1 << 3) 728 #define IWN_WIMAX_COEX_ENABLE (1 << 7) 729 730 struct iwn5000_wimax_event { 731 uint8_t request; 732 uint8_t window; 733 uint8_t reserved; 734 uint8_t flags; 735 } __packed events[16]; 736 } __packed; 737 738 /* Structures for command IWN5000_CMD_CALIB_CONFIG. */ 739 struct iwn5000_calib_elem { 740 uint32_t enable; 741 uint32_t start; 742 uint32_t send; 743 uint32_t apply; 744 uint32_t reserved; 745 } __packed; 746 747 struct iwn5000_calib_status { 748 struct iwn5000_calib_elem once; 749 struct iwn5000_calib_elem perd; 750 uint32_t flags; 751 } __packed; 752 753 struct iwn5000_calib_config { 754 struct iwn5000_calib_status ucode; 755 struct iwn5000_calib_status driver; 756 uint32_t reserved; 757 } __packed; 758 759 /* Structure for command IWN_CMD_SET_POWER_MODE. */ 760 struct iwn_pmgt_cmd { 761 uint16_t flags; 762 #define IWN_PS_ALLOW_SLEEP (1 << 0) 763 #define IWN_PS_NOTIFY (1 << 1) 764 #define IWN_PS_SLEEP_OVER_DTIM (1 << 2) 765 #define IWN_PS_PCI_PMGT (1 << 3) 766 #define IWN_PS_FAST_PD (1 << 4) 767 768 uint8_t keepalive; 769 uint8_t debug; 770 uint32_t rxtimeout; 771 uint32_t txtimeout; 772 uint32_t intval[5]; 773 uint32_t beacons; 774 } __packed; 775 776 /* Structures for command IWN_CMD_SCAN. */ 777 struct iwn_scan_essid { 778 uint8_t id; 779 uint8_t len; 780 uint8_t data[IEEE80211_NWID_LEN]; 781 } __packed; 782 783 struct iwn_scan_hdr { 784 uint16_t len; 785 uint8_t reserved1; 786 uint8_t nchan; 787 uint16_t quiet_time; 788 uint16_t quiet_threshold; 789 uint16_t crc_threshold; 790 uint16_t rxchain; 791 uint32_t max_svc; /* background scans */ 792 uint32_t pause_svc; /* background scans */ 793 uint32_t flags; 794 uint32_t filter; 795 796 /* Followed by a struct iwn_cmd_data. */ 797 /* Followed by an array of 20 structs iwn_scan_essid. */ 798 /* Followed by probe request body. */ 799 /* Followed by an array of ``nchan'' structs iwn_scan_chan. */ 800 } __packed; 801 802 struct iwn_scan_chan { 803 uint32_t flags; 804 #define IWN_CHAN_ACTIVE (1 << 0) 805 #define IWN_CHAN_NPBREQS(x) (((1 << (x)) - 1) << 1) 806 807 uint16_t chan; 808 uint8_t rf_gain; 809 uint8_t dsp_gain; 810 uint16_t active; /* msecs */ 811 uint16_t passive; /* msecs */ 812 } __packed; 813 814 /* Maximum size of a scan command. */ 815 #define IWN_SCAN_MAXSZ (MCLBYTES - 4) 816 817 /* Structure for command IWN_CMD_TXPOWER (4965AGN only.) */ 818 #define IWN_RIDX_MAX 32 819 struct iwn4965_cmd_txpower { 820 uint8_t band; 821 uint8_t reserved1; 822 uint8_t chan; 823 uint8_t reserved2; 824 struct { 825 uint8_t rf_gain[2]; 826 uint8_t dsp_gain[2]; 827 } __packed power[IWN_RIDX_MAX + 1]; 828 } __packed; 829 830 /* Structure for command IWN_CMD_TXPOWER_DBM (5000 Series only.) */ 831 struct iwn5000_cmd_txpower { 832 int8_t global_limit; /* in half-dBm */ 833 #define IWN5000_TXPOWER_AUTO 0x7f 834 #define IWN5000_TXPOWER_MAX_DBM 16 835 836 uint8_t flags; 837 #define IWN5000_TXPOWER_NO_CLOSED (1 << 6) 838 839 int8_t srv_limit; /* in half-dBm */ 840 uint8_t reserved; 841 } __packed; 842 843 /* Structures for command IWN_CMD_BLUETOOTH. */ 844 struct iwn_bluetooth { 845 uint8_t flags; 846 #define IWN_BT_COEX_CHAN_ANN (1 << 0) 847 #define IWN_BT_COEX_BT_PRIO (1 << 1) 848 #define IWN_BT_COEX_2_WIRE (1 << 2) 849 850 uint8_t lead_time; 851 #define IWN_BT_LEAD_TIME_DEF 30 852 853 uint8_t max_kill; 854 #define IWN_BT_MAX_KILL_DEF 5 855 856 uint8_t reserved; 857 uint32_t kill_ack; 858 uint32_t kill_cts; 859 } __packed; 860 861 struct iwn6000_btcoex_config { 862 uint8_t flags; 863 uint8_t lead_time; 864 uint8_t max_kill; 865 uint8_t bt3_t7_timer; 866 uint32_t kill_ack; 867 uint32_t kill_cts; 868 uint8_t sample_time; 869 uint8_t bt3_t2_timer; 870 uint16_t bt4_reaction; 871 uint32_t lookup_table[12]; 872 uint16_t bt4_decision; 873 uint16_t valid; 874 uint8_t prio_boost; 875 uint8_t tx_prio_boost; 876 uint16_t rx_prio_boost; 877 } __packed; 878 879 struct iwn_btcoex_priotable { 880 uint8_t calib_init1; 881 uint8_t calib_init2; 882 uint8_t calib_periodic_low1; 883 uint8_t calib_periodic_low2; 884 uint8_t calib_periodic_high1; 885 uint8_t calib_periodic_high2; 886 uint8_t dtim; 887 uint8_t scan52; 888 uint8_t scan24; 889 uint8_t reserved[7]; 890 } __packed; 891 892 struct iwn_btcoex_prot { 893 uint8_t open; 894 uint8_t type; 895 uint8_t reserved[2]; 896 } __packed; 897 898 /* Structure for command IWN_CMD_SET_CRITICAL_TEMP. */ 899 struct iwn_critical_temp { 900 uint32_t reserved; 901 uint32_t tempM; 902 uint32_t tempR; 903 /* degK <-> degC conversion macros. */ 904 #define IWN_CTOK(c) ((c) + 273) 905 #define IWN_KTOC(k) ((k) - 273) 906 #define IWN_CTOMUK(c) (((c) * 1000000) + 273150000) 907 } __packed; 908 909 /* Structures for command IWN_CMD_SET_SENSITIVITY. */ 910 struct iwn_sensitivity_cmd { 911 uint16_t which; 912 #define IWN_SENSITIVITY_DEFAULTTBL 0 913 #define IWN_SENSITIVITY_WORKTBL 1 914 915 uint16_t energy_cck; 916 uint16_t energy_ofdm; 917 uint16_t corr_ofdm_x1; 918 uint16_t corr_ofdm_mrc_x1; 919 uint16_t corr_cck_mrc_x4; 920 uint16_t corr_ofdm_x4; 921 uint16_t corr_ofdm_mrc_x4; 922 uint16_t corr_barker; 923 uint16_t corr_barker_mrc; 924 uint16_t corr_cck_x4; 925 uint16_t energy_ofdm_th; 926 } __packed; 927 928 struct iwn_enhanced_sensitivity_cmd { 929 uint16_t which; 930 uint16_t energy_cck; 931 uint16_t energy_ofdm; 932 uint16_t corr_ofdm_x1; 933 uint16_t corr_ofdm_mrc_x1; 934 uint16_t corr_cck_mrc_x4; 935 uint16_t corr_ofdm_x4; 936 uint16_t corr_ofdm_mrc_x4; 937 uint16_t corr_barker; 938 uint16_t corr_barker_mrc; 939 uint16_t corr_cck_x4; 940 uint16_t energy_ofdm_th; 941 /* "Enhanced" part. */ 942 uint16_t ina_det_ofdm; 943 uint16_t ina_det_cck; 944 uint16_t corr_11_9_en; 945 uint16_t ofdm_det_slope_mrc; 946 uint16_t ofdm_det_icept_mrc; 947 uint16_t ofdm_det_slope; 948 uint16_t ofdm_det_icept; 949 uint16_t cck_det_slope_mrc; 950 uint16_t cck_det_icept_mrc; 951 uint16_t cck_det_slope; 952 uint16_t cck_det_icept; 953 uint16_t reserved; 954 } __packed; 955 956 /* Structures for command IWN_CMD_PHY_CALIB. */ 957 struct iwn_phy_calib { 958 uint8_t code; 959 #define IWN4965_PHY_CALIB_DIFF_GAIN 7 960 #define IWN5000_PHY_CALIB_DC 8 961 #define IWN5000_PHY_CALIB_LO 9 962 #define IWN5000_PHY_CALIB_TX_IQ 11 963 #define IWN5000_PHY_CALIB_CRYSTAL 15 964 #define IWN5000_PHY_CALIB_BASE_BAND 16 965 #define IWN5000_PHY_CALIB_TX_IQ_PERIODIC 17 966 #define IWN5000_PHY_CALIB_TEMP_OFFSET 18 967 968 #define IWN5000_PHY_CALIB_RESET_NOISE_GAIN 18 969 #define IWN5000_PHY_CALIB_NOISE_GAIN 19 970 971 uint8_t group; 972 uint8_t ngroups; 973 uint8_t isvalid; 974 } __packed; 975 976 struct iwn5000_phy_calib_crystal { 977 uint8_t code; 978 uint8_t group; 979 uint8_t ngroups; 980 uint8_t isvalid; 981 982 uint8_t cap_pin[2]; 983 uint8_t reserved[2]; 984 } __packed; 985 986 struct iwn5000_phy_calib_temp_offset { 987 uint8_t code; 988 uint8_t group; 989 uint8_t ngroups; 990 uint8_t isvalid; 991 int16_t offset; 992 #define IWN_DEFAULT_TEMP_OFFSET 2700 993 994 uint16_t reserved; 995 } __packed; 996 997 struct iwn_phy_calib_gain { 998 uint8_t code; 999 uint8_t group; 1000 uint8_t ngroups; 1001 uint8_t isvalid; 1002 1003 int8_t gain[3]; 1004 uint8_t reserved; 1005 } __packed; 1006 1007 /* Structure for command IWN_CMD_SPECTRUM_MEASUREMENT. */ 1008 struct iwn_spectrum_cmd { 1009 uint16_t len; 1010 uint8_t token; 1011 uint8_t id; 1012 uint8_t origin; 1013 uint8_t periodic; 1014 uint16_t timeout; 1015 uint32_t start; 1016 uint32_t reserved1; 1017 uint32_t flags; 1018 uint32_t filter; 1019 uint16_t nchan; 1020 uint16_t reserved2; 1021 struct { 1022 uint32_t duration; 1023 uint8_t chan; 1024 uint8_t type; 1025 #define IWN_MEASUREMENT_BASIC (1 << 0) 1026 #define IWN_MEASUREMENT_CCA (1 << 1) 1027 #define IWN_MEASUREMENT_RPI_HISTOGRAM (1 << 2) 1028 #define IWN_MEASUREMENT_NOISE_HISTOGRAM (1 << 3) 1029 #define IWN_MEASUREMENT_FRAME (1 << 4) 1030 #define IWN_MEASUREMENT_IDLE (1 << 7) 1031 1032 uint16_t reserved; 1033 } __packed chan[10]; 1034 } __packed; 1035 1036 /* Structure for IWN_UC_READY notification. */ 1037 #define IWN_NATTEN_GROUPS 5 1038 struct iwn_ucode_info { 1039 uint8_t minor; 1040 uint8_t major; 1041 uint16_t reserved1; 1042 uint8_t revision[8]; 1043 uint8_t type; 1044 uint8_t subtype; 1045 #define IWN_UCODE_RUNTIME 0 1046 #define IWN_UCODE_INIT 9 1047 1048 uint16_t reserved2; 1049 uint32_t logptr; 1050 uint32_t errptr; 1051 uint32_t tstamp; 1052 uint32_t valid; 1053 1054 /* The following fields are for UCODE_INIT only. */ 1055 int32_t volt; 1056 struct { 1057 int32_t chan20MHz; 1058 int32_t chan40MHz; 1059 } __packed temp[4]; 1060 int32_t atten[IWN_NATTEN_GROUPS][2]; 1061 } __packed; 1062 1063 /* Structures for IWN_TX_DONE notification. */ 1064 #define IWN_TX_SUCCESS 0x00 1065 #define IWN_TX_FAIL 0x80 /* all failures have 0x80 set */ 1066 #define IWN_TX_FAIL_SHORT_LIMIT 0x82 /* too many RTS retries */ 1067 #define IWN_TX_FAIL_LONG_LIMIT 0x83 /* too many retries */ 1068 #define IWN_TX_FAIL_FIFO_UNDERRRUN 0x84 /* tx fifo not kept running */ 1069 #define IWN_TX_FAIL_DEST_IN_PS 0x88 /* sta found in power save */ 1070 #define IWN_TX_FAIL_TX_LOCKED 0x90 /* waiting to see traffic */ 1071 1072 struct iwn4965_tx_stat { 1073 uint8_t nframes; 1074 uint8_t btkillcnt; 1075 uint8_t rtsfailcnt; 1076 uint8_t ackfailcnt; 1077 uint32_t rate; 1078 uint16_t duration; 1079 uint16_t reserved; 1080 uint32_t power[2]; 1081 uint32_t status; 1082 } __packed; 1083 1084 struct iwn5000_tx_stat { 1085 uint8_t nframes; 1086 uint8_t btkillcnt; 1087 uint8_t rtsfailcnt; 1088 uint8_t ackfailcnt; 1089 uint32_t rate; 1090 uint16_t duration; 1091 uint16_t reserved; 1092 uint32_t power[2]; 1093 uint32_t info; 1094 uint16_t seq; 1095 uint16_t len; 1096 uint8_t tlc; 1097 uint8_t ratid; 1098 uint8_t fc[2]; 1099 uint16_t status; 1100 uint16_t sequence; 1101 } __packed; 1102 1103 /* Structure for IWN_BEACON_MISSED notification. */ 1104 struct iwn_beacon_missed { 1105 uint32_t consecutive; 1106 uint32_t total; 1107 uint32_t expected; 1108 uint32_t received; 1109 } __packed; 1110 1111 /* Structure for IWN_MPDU_RX_DONE notification. */ 1112 struct iwn_rx_mpdu { 1113 uint16_t len; 1114 uint16_t reserved; 1115 } __packed; 1116 1117 /* Structures for IWN_RX_DONE and IWN_MPDU_RX_DONE notifications. */ 1118 struct iwn4965_rx_phystat { 1119 uint16_t antenna; 1120 uint16_t agc; 1121 uint8_t rssi[6]; 1122 } __packed; 1123 1124 struct iwn5000_rx_phystat { 1125 uint32_t reserved1; 1126 uint32_t agc; 1127 uint16_t rssi[3]; 1128 } __packed; 1129 1130 struct iwn_rx_stat { 1131 uint8_t phy_len; 1132 uint8_t cfg_phy_len; 1133 #define IWN_STAT_MAXLEN 20 1134 1135 uint8_t id; 1136 uint8_t reserved1; 1137 uint64_t tstamp; 1138 uint32_t beacon; 1139 uint16_t flags; 1140 #define IWN_STAT_FLAG_SHPREAMBLE (1 << 2) 1141 1142 uint16_t chan; 1143 uint8_t phybuf[32]; 1144 uint32_t rate; 1145 uint16_t len; 1146 uint16_t reserve3; 1147 } __packed; 1148 1149 #define IWN_RSSI_TO_DBM 44 1150 1151 /* Structure for IWN_RX_COMPRESSED_BA notification. */ 1152 struct iwn_compressed_ba { 1153 uint8_t macaddr[IEEE80211_ADDR_LEN]; 1154 uint16_t reserved; 1155 uint8_t id; 1156 uint8_t tid; 1157 uint16_t seq; 1158 uint64_t bitmap; 1159 uint16_t qid; 1160 uint16_t ssn; 1161 } __packed; 1162 1163 /* Structure for IWN_START_SCAN notification. */ 1164 struct iwn_start_scan { 1165 uint64_t tstamp; 1166 uint32_t tbeacon; 1167 uint8_t chan; 1168 uint8_t band; 1169 uint16_t reserved; 1170 uint32_t status; 1171 } __packed; 1172 1173 /* Structure for IWN_STOP_SCAN notification. */ 1174 struct iwn_stop_scan { 1175 uint8_t nchan; 1176 uint8_t status; 1177 uint8_t reserved; 1178 uint8_t chan; 1179 uint64_t tsf; 1180 } __packed; 1181 1182 /* Structure for IWN_SPECTRUM_MEASUREMENT notification. */ 1183 struct iwn_spectrum_notif { 1184 uint8_t id; 1185 uint8_t token; 1186 uint8_t idx; 1187 uint8_t state; 1188 #define IWN_MEASUREMENT_START 0 1189 #define IWN_MEASUREMENT_STOP 1 1190 1191 uint32_t start; 1192 uint8_t band; 1193 uint8_t chan; 1194 uint8_t type; 1195 uint8_t reserved1; 1196 uint32_t cca_ofdm; 1197 uint32_t cca_cck; 1198 uint32_t cca_time; 1199 uint8_t basic; 1200 uint8_t reserved2[3]; 1201 uint32_t ofdm[8]; 1202 uint32_t cck[8]; 1203 uint32_t stop; 1204 uint32_t status; 1205 #define IWN_MEASUREMENT_OK 0 1206 #define IWN_MEASUREMENT_CONCURRENT 1 1207 #define IWN_MEASUREMENT_CSA_CONFLICT 2 1208 #define IWN_MEASUREMENT_TGH_CONFLICT 3 1209 #define IWN_MEASUREMENT_STOPPED 6 1210 #define IWN_MEASUREMENT_TIMEOUT 7 1211 #define IWN_MEASUREMENT_FAILED 8 1212 } __packed; 1213 1214 /* Structures for IWN_{RX,BEACON}_STATISTICS notification. */ 1215 struct iwn_rx_phy_stats { 1216 uint32_t ina; 1217 uint32_t fina; 1218 uint32_t bad_plcp; 1219 uint32_t bad_crc32; 1220 uint32_t overrun; 1221 uint32_t eoverrun; 1222 uint32_t good_crc32; 1223 uint32_t fa; 1224 uint32_t bad_fina_sync; 1225 uint32_t sfd_timeout; 1226 uint32_t fina_timeout; 1227 uint32_t no_rts_ack; 1228 uint32_t rxe_limit; 1229 uint32_t ack; 1230 uint32_t cts; 1231 uint32_t ba_resp; 1232 uint32_t dsp_kill; 1233 uint32_t bad_mh; 1234 uint32_t rssi_sum; 1235 uint32_t reserved; 1236 } __packed; 1237 1238 struct iwn_rx_general_stats { 1239 uint32_t bad_cts; 1240 uint32_t bad_ack; 1241 uint32_t not_bss; 1242 uint32_t filtered; 1243 uint32_t bad_chan; 1244 uint32_t beacons; 1245 uint32_t missed_beacons; 1246 uint32_t adc_saturated; /* time in 0.8us */ 1247 uint32_t ina_searched; /* time in 0.8us */ 1248 uint32_t noise[3]; 1249 uint32_t flags; 1250 uint32_t load; 1251 uint32_t fa; 1252 uint32_t rssi[3]; 1253 uint32_t energy[3]; 1254 } __packed; 1255 1256 struct iwn_rx_ht_phy_stats { 1257 uint32_t bad_plcp; 1258 uint32_t overrun; 1259 uint32_t eoverrun; 1260 uint32_t good_crc32; 1261 uint32_t bad_crc32; 1262 uint32_t bad_mh; 1263 uint32_t good_ampdu_crc32; 1264 uint32_t ampdu; 1265 uint32_t fragment; 1266 uint32_t reserved; 1267 } __packed; 1268 1269 struct iwn_rx_stats { 1270 struct iwn_rx_phy_stats ofdm; 1271 struct iwn_rx_phy_stats cck; 1272 struct iwn_rx_general_stats general; 1273 struct iwn_rx_ht_phy_stats ht; 1274 } __packed; 1275 1276 struct iwn_tx_stats { 1277 uint32_t preamble; 1278 uint32_t rx_detected; 1279 uint32_t bt_defer; 1280 uint32_t bt_kill; 1281 uint32_t short_len; 1282 uint32_t cts_timeout; 1283 uint32_t ack_timeout; 1284 uint32_t exp_ack; 1285 uint32_t ack; 1286 uint32_t msdu; 1287 uint32_t busrt_err1; 1288 uint32_t burst_err2; 1289 uint32_t cts_collision; 1290 uint32_t ack_collision; 1291 uint32_t ba_timeout; 1292 uint32_t ba_resched; 1293 uint32_t query_ampdu; 1294 uint32_t query; 1295 uint32_t query_ampdu_frag; 1296 uint32_t query_mismatch; 1297 uint32_t not_ready; 1298 uint32_t underrun; 1299 uint32_t bt_ht_kill; 1300 uint32_t rx_ba_resp; 1301 uint32_t reserved[2]; 1302 } __packed; 1303 1304 struct iwn_general_stats { 1305 uint32_t temp; 1306 uint32_t temp_m; 1307 uint32_t burst_check; 1308 uint32_t burst; 1309 uint32_t reserved1[4]; 1310 uint32_t sleep; 1311 uint32_t slot_out; 1312 uint32_t slot_idle; 1313 uint32_t ttl_tstamp; 1314 uint32_t tx_ant_a; 1315 uint32_t tx_ant_b; 1316 uint32_t exec; 1317 uint32_t probe; 1318 uint32_t reserved2[2]; 1319 uint32_t rx_enabled; 1320 uint32_t reserved3[3]; 1321 } __packed; 1322 1323 struct iwn_stats { 1324 uint32_t flags; 1325 struct iwn_rx_stats rx; 1326 struct iwn_tx_stats tx; 1327 struct iwn_general_stats general; 1328 } __packed; 1329 1330 1331 /* Firmware error dump. */ 1332 struct iwn_fw_dump { 1333 uint32_t valid; 1334 uint32_t id; 1335 uint32_t pc; 1336 uint32_t branch_link[2]; 1337 uint32_t interrupt_link[2]; 1338 uint32_t error_data[2]; 1339 uint32_t src_line; 1340 uint32_t tsf; 1341 uint32_t time[2]; 1342 } __packed; 1343 1344 /* TLV firmware header. */ 1345 struct iwn_fw_tlv_hdr { 1346 uint32_t zero; /* Always 0, to differentiate from legacy. */ 1347 uint32_t signature; 1348 #define IWN_FW_SIGNATURE 0x0a4c5749 /* "IWL\n" */ 1349 1350 uint8_t descr[64]; 1351 uint32_t rev; 1352 #define IWN_FW_API(x) (((x) >> 8) & 0xff) 1353 1354 uint32_t build; 1355 uint64_t altmask; 1356 } __packed; 1357 1358 /* TLV header. */ 1359 struct iwn_fw_tlv { 1360 uint16_t type; 1361 #define IWN_FW_TLV_MAIN_TEXT 1 1362 #define IWN_FW_TLV_MAIN_DATA 2 1363 #define IWN_FW_TLV_INIT_TEXT 3 1364 #define IWN_FW_TLV_INIT_DATA 4 1365 #define IWN_FW_TLV_BOOT_TEXT 5 1366 #define IWN_FW_TLV_PBREQ_MAXLEN 6 1367 #define IWN_FW_TLV_ENH_SENS 14 1368 #define IWN_FW_TLV_PHY_CALIB 15 1369 1370 uint16_t alt; 1371 uint32_t len; 1372 } __packed; 1373 1374 #define IWN4965_FW_TEXT_MAXSZ ( 96 * 1024) 1375 #define IWN4965_FW_DATA_MAXSZ ( 40 * 1024) 1376 #define IWN5000_FW_TEXT_MAXSZ (256 * 1024) 1377 #define IWN5000_FW_DATA_MAXSZ ( 80 * 1024) 1378 #define IWN_FW_BOOT_TEXT_MAXSZ 1024 1379 #define IWN4965_FWSZ (IWN4965_FW_TEXT_MAXSZ + IWN4965_FW_DATA_MAXSZ) 1380 #define IWN5000_FWSZ IWN5000_FW_TEXT_MAXSZ 1381 1382 /* 1383 * Offsets into EEPROM. 1384 */ 1385 #define IWN_EEPROM_MAC 0x015 1386 #define IWN_EEPROM_SKU_CAP 0x045 1387 #define IWN_EEPROM_RFCFG 0x048 1388 #define IWN4965_EEPROM_DOMAIN 0x060 1389 #define IWN4965_EEPROM_BAND1 0x063 1390 #define IWN5000_EEPROM_REG 0x066 1391 #define IWN5000_EEPROM_CAL 0x067 1392 #define IWN4965_EEPROM_BAND2 0x072 1393 #define IWN4965_EEPROM_BAND3 0x080 1394 #define IWN4965_EEPROM_BAND4 0x08d 1395 #define IWN4965_EEPROM_BAND5 0x099 1396 #define IWN4965_EEPROM_BAND6 0x0a0 1397 #define IWN4965_EEPROM_BAND7 0x0a8 1398 #define IWN4965_EEPROM_MAXPOW 0x0e8 1399 #define IWN4965_EEPROM_VOLTAGE 0x0e9 1400 #define IWN4965_EEPROM_BANDS 0x0ea 1401 /* Indirect offsets. */ 1402 #define IWN5000_EEPROM_DOMAIN 0x001 1403 #define IWN5000_EEPROM_BAND1 0x004 1404 #define IWN5000_EEPROM_BAND2 0x013 1405 #define IWN5000_EEPROM_BAND3 0x021 1406 #define IWN5000_EEPROM_BAND4 0x02e 1407 #define IWN5000_EEPROM_BAND5 0x03a 1408 #define IWN5000_EEPROM_BAND6 0x041 1409 #define IWN6000_EEPROM_BAND6 0x040 1410 #define IWN5000_EEPROM_BAND7 0x049 1411 #define IWN6000_EEPROM_ENHINFO 0x054 1412 #define IWN5000_EEPROM_CRYSTAL 0x128 1413 #define IWN5000_EEPROM_TEMP 0x12a 1414 #define IWN5000_EEPROM_VOLT 0x12b 1415 1416 /* Possible flags for IWN_EEPROM_SKU_CAP. */ 1417 #define IWN_EEPROM_SKU_CAP_11N (1 << 6) 1418 #define IWN_EEPROM_SKU_CAP_AMT (1 << 7) 1419 #define IWN_EEPROM_SKU_CAP_IPAN (1 << 8) 1420 1421 /* Possible flags for IWN_EEPROM_RFCFG. */ 1422 #define IWN_RFCFG_TYPE(x) (((x) >> 0) & 0x3) 1423 #define IWN_RFCFG_STEP(x) (((x) >> 2) & 0x3) 1424 #define IWN_RFCFG_DASH(x) (((x) >> 4) & 0x3) 1425 #define IWN_RFCFG_TXANTMSK(x) (((x) >> 8) & 0xf) 1426 #define IWN_RFCFG_RXANTMSK(x) (((x) >> 12) & 0xf) 1427 1428 struct iwn_eeprom_chan { 1429 uint8_t flags; 1430 #define IWN_EEPROM_CHAN_VALID (1 << 0) 1431 #define IWN_EEPROM_CHAN_IBSS (1 << 1) 1432 #define IWN_EEPROM_CHAN_ACTIVE (1 << 3) 1433 #define IWN_EEPROM_CHAN_RADAR (1 << 4) 1434 1435 int8_t maxpwr; 1436 } __packed; 1437 1438 struct iwn_eeprom_enhinfo { 1439 uint8_t flags; 1440 #define IWN_ENHINFO_VALID 0x01 1441 #define IWN_ENHINFO_5GHZ 0x02 1442 #define IWN_ENHINFO_OFDM 0x04 1443 #define IWN_ENHINFO_HT40 0x08 1444 #define IWN_ENHINFO_HTAP 0x10 1445 #define IWN_ENHINFO_RES1 0x20 1446 #define IWN_ENHINFO_RES2 0x40 1447 #define IWN_ENHINFO_COMMON 0x80 1448 1449 uint8_t chan; 1450 int8_t chain[3]; /* max power in half-dBm */ 1451 uint8_t reserved; 1452 int8_t mimo2; /* max power in half-dBm */ 1453 int8_t mimo3; /* max power in half-dBm */ 1454 } __packed; 1455 1456 struct iwn5000_eeprom_calib_hdr { 1457 uint8_t version; 1458 uint8_t pa_type; 1459 uint16_t volt; 1460 } __packed; 1461 1462 #define IWN_NSAMPLES 3 1463 struct iwn4965_eeprom_chan_samples { 1464 uint8_t num; 1465 struct { 1466 uint8_t temp; 1467 uint8_t gain; 1468 uint8_t power; 1469 int8_t pa_det; 1470 } samples[2][IWN_NSAMPLES]; 1471 } __packed; 1472 1473 #define IWN_NBANDS 8 1474 struct iwn4965_eeprom_band { 1475 uint8_t lo; /* low channel number */ 1476 uint8_t hi; /* high channel number */ 1477 struct iwn4965_eeprom_chan_samples chans[2]; 1478 } __packed; 1479 1480 /* 1481 * Offsets of channels descriptions in EEPROM. 1482 */ 1483 static const uint32_t iwn4965_regulatory_bands[IWN_NBANDS] = { 1484 IWN4965_EEPROM_BAND1, 1485 IWN4965_EEPROM_BAND2, 1486 IWN4965_EEPROM_BAND3, 1487 IWN4965_EEPROM_BAND4, 1488 IWN4965_EEPROM_BAND5, 1489 IWN4965_EEPROM_BAND6, 1490 IWN4965_EEPROM_BAND7 1491 }; 1492 1493 static const uint32_t iwn5000_regulatory_bands[IWN_NBANDS] = { 1494 IWN5000_EEPROM_BAND1, 1495 IWN5000_EEPROM_BAND2, 1496 IWN5000_EEPROM_BAND3, 1497 IWN5000_EEPROM_BAND4, 1498 IWN5000_EEPROM_BAND5, 1499 IWN5000_EEPROM_BAND6, 1500 IWN5000_EEPROM_BAND7 1501 }; 1502 1503 static const uint32_t iwn6000_regulatory_bands[IWN_NBANDS] = { 1504 IWN5000_EEPROM_BAND1, 1505 IWN5000_EEPROM_BAND2, 1506 IWN5000_EEPROM_BAND3, 1507 IWN5000_EEPROM_BAND4, 1508 IWN5000_EEPROM_BAND5, 1509 IWN6000_EEPROM_BAND6, 1510 IWN5000_EEPROM_BAND7 1511 }; 1512 1513 #define IWN_CHAN_BANDS_COUNT 7 1514 #define IWN_MAX_CHAN_PER_BAND 14 1515 static const struct iwn_chan_band { 1516 uint8_t nchan; 1517 uint8_t chan[IWN_MAX_CHAN_PER_BAND]; 1518 } iwn_bands[] = { 1519 /* 20MHz channels, 2GHz band. */ 1520 { 14, { 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14 } }, 1521 /* 20MHz channels, 5GHz band. */ 1522 { 13, { 183, 184, 185, 187, 188, 189, 192, 196, 7, 8, 11, 12, 16 } }, 1523 { 12, { 34, 36, 38, 40, 42, 44, 46, 48, 52, 56, 60, 64 } }, 1524 { 11, { 100, 104, 108, 112, 116, 120, 124, 128, 132, 136, 140 } }, 1525 { 6, { 145, 149, 153, 157, 161, 165 } }, 1526 /* 40MHz channels (primary channels), 2GHz band. */ 1527 { 7, { 1, 2, 3, 4, 5, 6, 7 } }, 1528 /* 40MHz channels (primary channels), 5GHz band. */ 1529 { 11, { 36, 44, 52, 60, 100, 108, 116, 124, 132, 149, 157 } } 1530 }; 1531 1532 #define IWN1000_OTP_NBLOCKS 3 1533 #define IWN6000_OTP_NBLOCKS 4 1534 #define IWN6050_OTP_NBLOCKS 7 1535 1536 /* HW rate indices. */ 1537 #define IWN_RIDX_CCK1 0 1538 #define IWN_RIDX_OFDM6 4 1539 1540 #define IWN4965_MAX_PWR_INDEX 107 1541 1542 /* 1543 * RF Tx gain values from highest to lowest power (values obtained from 1544 * the reference driver.) 1545 */ 1546 static const uint8_t iwn4965_rf_gain_2ghz[IWN4965_MAX_PWR_INDEX + 1] = { 1547 0x3f, 0x3f, 0x3f, 0x3e, 0x3e, 0x3e, 0x3d, 0x3d, 0x3d, 0x3c, 0x3c, 1548 0x3c, 0x3b, 0x3b, 0x3b, 0x3a, 0x3a, 0x3a, 0x39, 0x39, 0x39, 0x38, 1549 0x38, 0x38, 0x37, 0x37, 0x37, 0x36, 0x36, 0x36, 0x35, 0x35, 0x35, 1550 0x34, 0x34, 0x34, 0x33, 0x33, 0x33, 0x32, 0x32, 0x32, 0x31, 0x31, 1551 0x31, 0x30, 0x30, 0x30, 0x06, 0x06, 0x06, 0x05, 0x05, 0x05, 0x04, 1552 0x04, 0x04, 0x03, 0x03, 0x03, 0x02, 0x02, 0x02, 0x01, 0x01, 0x01, 1553 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 1554 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 1555 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 1556 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 1557 }; 1558 1559 static const uint8_t iwn4965_rf_gain_5ghz[IWN4965_MAX_PWR_INDEX + 1] = { 1560 0x3f, 0x3f, 0x3f, 0x3f, 0x3f, 0x3e, 0x3e, 0x3e, 0x3d, 0x3d, 0x3d, 1561 0x3c, 0x3c, 0x3c, 0x3b, 0x3b, 0x3b, 0x3a, 0x3a, 0x3a, 0x39, 0x39, 1562 0x39, 0x38, 0x38, 0x38, 0x37, 0x37, 0x37, 0x36, 0x36, 0x36, 0x35, 1563 0x35, 0x35, 0x34, 0x34, 0x34, 0x33, 0x33, 0x33, 0x32, 0x32, 0x32, 1564 0x31, 0x31, 0x31, 0x30, 0x30, 0x30, 0x25, 0x25, 0x25, 0x24, 0x24, 1565 0x24, 0x23, 0x23, 0x23, 0x22, 0x18, 0x18, 0x17, 0x17, 0x17, 0x16, 1566 0x16, 0x16, 0x15, 0x15, 0x15, 0x14, 0x14, 0x14, 0x13, 0x13, 0x13, 1567 0x12, 0x08, 0x08, 0x07, 0x07, 0x07, 0x06, 0x06, 0x06, 0x05, 0x05, 1568 0x05, 0x04, 0x04, 0x04, 0x03, 0x03, 0x03, 0x02, 0x02, 0x02, 0x01, 1569 0x01, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 1570 }; 1571 1572 /* 1573 * DSP pre-DAC gain values from highest to lowest power (values obtained 1574 * from the reference driver.) 1575 */ 1576 static const uint8_t iwn4965_dsp_gain_2ghz[IWN4965_MAX_PWR_INDEX + 1] = { 1577 0x6e, 0x68, 0x62, 0x6e, 0x68, 0x62, 0x6e, 0x68, 0x62, 0x6e, 0x68, 1578 0x62, 0x6e, 0x68, 0x62, 0x6e, 0x68, 0x62, 0x6e, 0x68, 0x62, 0x6e, 1579 0x68, 0x62, 0x6e, 0x68, 0x62, 0x6e, 0x68, 0x62, 0x6e, 0x68, 0x62, 1580 0x6e, 0x68, 0x62, 0x6e, 0x68, 0x62, 0x6e, 0x68, 0x62, 0x6e, 0x68, 1581 0x62, 0x6e, 0x68, 0x62, 0x6e, 0x68, 0x62, 0x6e, 0x68, 0x62, 0x6e, 1582 0x68, 0x62, 0x6e, 0x68, 0x62, 0x6e, 0x68, 0x62, 0x6e, 0x68, 0x62, 1583 0x6e, 0x68, 0x62, 0x61, 0x60, 0x5f, 0x5e, 0x5d, 0x5c, 0x5b, 0x5a, 1584 0x59, 0x58, 0x57, 0x56, 0x55, 0x54, 0x53, 0x52, 0x51, 0x50, 0x4f, 1585 0x4e, 0x4d, 0x4c, 0x4b, 0x4a, 0x49, 0x48, 0x47, 0x46, 0x45, 0x44, 1586 0x43, 0x42, 0x41, 0x40, 0x3f, 0x3e, 0x3d, 0x3c, 0x3b 1587 }; 1588 1589 static const uint8_t iwn4965_dsp_gain_5ghz[IWN4965_MAX_PWR_INDEX + 1] = { 1590 0x7b, 0x75, 0x6e, 0x68, 0x62, 0x6e, 0x68, 0x62, 0x6e, 0x68, 0x62, 1591 0x6e, 0x68, 0x62, 0x6e, 0x68, 0x62, 0x6e, 0x68, 0x62, 0x6e, 0x68, 1592 0x62, 0x6e, 0x68, 0x62, 0x6e, 0x68, 0x62, 0x6e, 0x68, 0x62, 0x6e, 1593 0x68, 0x62, 0x6e, 0x68, 0x62, 0x6e, 0x68, 0x62, 0x6e, 0x68, 0x62, 1594 0x6e, 0x68, 0x62, 0x6e, 0x68, 0x62, 0x6e, 0x68, 0x62, 0x6e, 0x68, 1595 0x62, 0x6e, 0x68, 0x62, 0x6e, 0x68, 0x62, 0x6e, 0x68, 0x62, 0x6e, 1596 0x68, 0x62, 0x6e, 0x68, 0x62, 0x6e, 0x68, 0x62, 0x6e, 0x68, 0x62, 1597 0x6e, 0x68, 0x62, 0x6e, 0x68, 0x62, 0x6e, 0x68, 0x62, 0x6e, 0x68, 1598 0x62, 0x6e, 0x68, 0x62, 0x6e, 0x68, 0x62, 0x6e, 0x68, 0x62, 0x6e, 1599 0x68, 0x62, 0x6e, 0x68, 0x62, 0x5d, 0x58, 0x53, 0x4e 1600 }; 1601 1602 /* 1603 * Power saving settings (values obtained from the reference driver.) 1604 */ 1605 #define IWN_NDTIMRANGES 3 1606 #define IWN_NPOWERLEVELS 6 1607 static const struct iwn_pmgt { 1608 uint32_t rxtimeout; 1609 uint32_t txtimeout; 1610 uint32_t intval[5]; 1611 int skip_dtim; 1612 } iwn_pmgt[IWN_NDTIMRANGES][IWN_NPOWERLEVELS] = { 1613 /* DTIM <= 2 */ 1614 { 1615 { 0, 0, { 0, 0, 0, 0, 0 }, 0 }, /* CAM */ 1616 { 200, 500, { 1, 2, 2, 2, -1 }, 0 }, /* PS level 1 */ 1617 { 200, 300, { 1, 2, 2, 2, -1 }, 0 }, /* PS level 2 */ 1618 { 50, 100, { 2, 2, 2, 2, -1 }, 0 }, /* PS level 3 */ 1619 { 50, 25, { 2, 2, 4, 4, -1 }, 1 }, /* PS level 4 */ 1620 { 25, 25, { 2, 2, 4, 6, -1 }, 2 } /* PS level 5 */ 1621 }, 1622 /* 3 <= DTIM <= 10 */ 1623 { 1624 { 0, 0, { 0, 0, 0, 0, 0 }, 0 }, /* CAM */ 1625 { 200, 500, { 1, 2, 3, 4, 4 }, 0 }, /* PS level 1 */ 1626 { 200, 300, { 1, 2, 3, 4, 7 }, 0 }, /* PS level 2 */ 1627 { 50, 100, { 2, 4, 6, 7, 9 }, 0 }, /* PS level 3 */ 1628 { 50, 25, { 2, 4, 6, 9, 10 }, 1 }, /* PS level 4 */ 1629 { 25, 25, { 2, 4, 7, 10, 10 }, 2 } /* PS level 5 */ 1630 }, 1631 /* DTIM >= 11 */ 1632 { 1633 { 0, 0, { 0, 0, 0, 0, 0 }, 0 }, /* CAM */ 1634 { 200, 500, { 1, 2, 3, 4, -1 }, 0 }, /* PS level 1 */ 1635 { 200, 300, { 2, 4, 6, 7, -1 }, 0 }, /* PS level 2 */ 1636 { 50, 100, { 2, 7, 9, 9, -1 }, 0 }, /* PS level 3 */ 1637 { 50, 25, { 2, 7, 9, 9, -1 }, 0 }, /* PS level 4 */ 1638 { 25, 25, { 4, 7, 10, 10, -1 }, 0 } /* PS level 5 */ 1639 } 1640 }; 1641 1642 struct iwn_sensitivity_limits { 1643 uint32_t min_ofdm_x1; 1644 uint32_t max_ofdm_x1; 1645 uint32_t min_ofdm_mrc_x1; 1646 uint32_t max_ofdm_mrc_x1; 1647 uint32_t min_ofdm_x4; 1648 uint32_t max_ofdm_x4; 1649 uint32_t min_ofdm_mrc_x4; 1650 uint32_t max_ofdm_mrc_x4; 1651 uint32_t min_cck_x4; 1652 uint32_t max_cck_x4; 1653 uint32_t min_cck_mrc_x4; 1654 uint32_t max_cck_mrc_x4; 1655 uint32_t min_energy_cck; 1656 uint32_t energy_cck; 1657 uint32_t energy_ofdm; 1658 }; 1659 1660 /* 1661 * RX sensitivity limits (values obtained from the reference driver.) 1662 */ 1663 static const struct iwn_sensitivity_limits iwn4965_sensitivity_limits = { 1664 105, 140, 1665 220, 270, 1666 85, 120, 1667 170, 210, 1668 125, 200, 1669 200, 400, 1670 97, 1671 100, 1672 100 1673 }; 1674 1675 static const struct iwn_sensitivity_limits iwn5000_sensitivity_limits = { 1676 120, 120, /* min = max for performance bug in DSP. */ 1677 240, 240, /* min = max for performance bug in DSP. */ 1678 90, 120, 1679 170, 210, 1680 125, 200, 1681 170, 400, 1682 95, 1683 95, 1684 95 1685 }; 1686 1687 static const struct iwn_sensitivity_limits iwn5150_sensitivity_limits = { 1688 105, 105, /* min = max for performance bug in DSP. */ 1689 220, 220, /* min = max for performance bug in DSP. */ 1690 90, 120, 1691 170, 210, 1692 125, 200, 1693 170, 400, 1694 95, 1695 95, 1696 95 1697 }; 1698 1699 static const struct iwn_sensitivity_limits iwn1000_sensitivity_limits = { 1700 120, 155, 1701 240, 290, 1702 90, 120, 1703 170, 210, 1704 125, 200, 1705 170, 400, 1706 95, 1707 95, 1708 95 1709 }; 1710 1711 static const struct iwn_sensitivity_limits iwn6000_sensitivity_limits = { 1712 105, 110, 1713 192, 232, 1714 80, 145, 1715 128, 232, 1716 125, 175, 1717 160, 310, 1718 97, 1719 97, 1720 100 1721 }; 1722 1723 /* Map TID to TX scheduler's FIFO. */ 1724 static const uint8_t iwn_tid2fifo[] = { 1725 1, 0, 0, 1, 2, 2, 3, 3, 7, 7, 7, 7, 7, 7, 7, 7, 3 1726 }; 1727 1728 /* WiFi/WiMAX coexist event priority table for 6050. */ 1729 static const struct iwn5000_wimax_event iwn6050_wimax_events[] = { 1730 { 0x04, 0x03, 0x00, 0x00 }, 1731 { 0x04, 0x03, 0x00, 0x03 }, 1732 { 0x04, 0x03, 0x00, 0x03 }, 1733 { 0x04, 0x03, 0x00, 0x03 }, 1734 { 0x04, 0x03, 0x00, 0x00 }, 1735 { 0x04, 0x03, 0x00, 0x07 }, 1736 { 0x04, 0x03, 0x00, 0x00 }, 1737 { 0x04, 0x03, 0x00, 0x03 }, 1738 { 0x04, 0x03, 0x00, 0x03 }, 1739 { 0x04, 0x03, 0x00, 0x00 }, 1740 { 0x06, 0x03, 0x00, 0x07 }, 1741 { 0x04, 0x03, 0x00, 0x00 }, 1742 { 0x06, 0x06, 0x00, 0x03 }, 1743 { 0x04, 0x03, 0x00, 0x07 }, 1744 { 0x04, 0x03, 0x00, 0x00 }, 1745 { 0x04, 0x03, 0x00, 0x00 } 1746 }; 1747 1748 /* Firmware errors. */ 1749 static const char * const iwn_fw_errmsg[] = { 1750 "OK", 1751 "FAIL", 1752 "BAD_PARAM", 1753 "BAD_CHECKSUM", 1754 "NMI_INTERRUPT_WDG", 1755 "SYSASSERT", 1756 "FATAL_ERROR", 1757 "BAD_COMMAND", 1758 "HW_ERROR_TUNE_LOCK", 1759 "HW_ERROR_TEMPERATURE", 1760 "ILLEGAL_CHAN_FREQ", 1761 "VCC_NOT_STABLE", 1762 "FH_ERROR", 1763 "NMI_INTERRUPT_HOST", 1764 "NMI_INTERRUPT_ACTION_PT", 1765 "NMI_INTERRUPT_UNKNOWN", 1766 "UCODE_VERSION_MISMATCH", 1767 "HW_ERROR_ABS_LOCK", 1768 "HW_ERROR_CAL_LOCK_FAIL", 1769 "NMI_INTERRUPT_INST_ACTION_PT", 1770 "NMI_INTERRUPT_DATA_ACTION_PT", 1771 "NMI_TRM_HW_ER", 1772 "NMI_INTERRUPT_TRM", 1773 "NMI_INTERRUPT_BREAKPOINT" 1774 "DEBUG_0", 1775 "DEBUG_1", 1776 "DEBUG_2", 1777 "DEBUG_3", 1778 "ADVANCED_SYSASSERT" 1779 }; 1780 1781 /* Find least significant bit that is set. */ 1782 #define IWN_LSB(x) ((((x) - 1) & (x)) ^ (x)) 1783 1784 #define IWN_READ(sc, reg) \ 1785 bus_space_read_4((sc)->sc_st, (sc)->sc_sh, (reg)) 1786 1787 #define IWN_WRITE(sc, reg, val) \ 1788 bus_space_write_4((sc)->sc_st, (sc)->sc_sh, (reg), (val)) 1789 1790 #define IWN_WRITE_1(sc, reg, val) \ 1791 bus_space_write_1((sc)->sc_st, (sc)->sc_sh, (reg), (val)) 1792 1793 #define IWN_SETBITS(sc, reg, mask) \ 1794 IWN_WRITE(sc, reg, IWN_READ(sc, reg) | (mask)) 1795 1796 #define IWN_CLRBITS(sc, reg, mask) \ 1797 IWN_WRITE(sc, reg, IWN_READ(sc, reg) & ~(mask)) 1798 1799 #define IWN_BARRIER_WRITE(sc) \ 1800 bus_space_barrier((sc)->sc_st, (sc)->sc_sh, 0, (sc)->sc_sz, \ 1801 BUS_SPACE_BARRIER_WRITE) 1802 1803 #define IWN_BARRIER_READ_WRITE(sc) \ 1804 bus_space_barrier((sc)->sc_st, (sc)->sc_sh, 0, (sc)->sc_sz, \ 1805 BUS_SPACE_BARRIER_READ | BUS_SPACE_BARRIER_WRITE) 1806