1 /* $FreeBSD$ */ 2 /* $OpenBSD: if_iwnreg.h,v 1.26 2009/05/29 08:25:45 damien Exp $ */ 3 4 /*- 5 * Copyright (c) 2007, 2008 6 * Damien Bergamini <damien.bergamini@free.fr> 7 * 8 * Permission to use, copy, modify, and distribute this software for any 9 * purpose with or without fee is hereby granted, provided that the above 10 * copyright notice and this permission notice appear in all copies. 11 * 12 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 13 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 14 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR 15 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 16 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN 17 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF 18 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 19 */ 20 21 #define EDCA_NUM_AC 4 22 23 #define IWN_TX_RING_COUNT 256 24 #define IWN_TX_RING_LOMARK 192 25 #define IWN_TX_RING_HIMARK 224 26 #define IWN_RX_RING_COUNT_LOG 6 27 #define IWN_RX_RING_COUNT (1 << IWN_RX_RING_COUNT_LOG) 28 29 #define IWN4965_NTXQUEUES 16 30 #define IWN5000_NTXQUEUES 20 31 32 #define IWN4965_NDMACHNLS 7 33 #define IWN5000_NDMACHNLS 8 34 35 #define IWN_SRVC_DMACHNL 9 36 37 /* Maximum number of DMA segments for TX. */ 38 #define IWN_MAX_SCATTER 20 39 40 /* RX buffers must be large enough to hold a full 4K A-MPDU. */ 41 #define IWN_RBUF_SIZE (4 * 1024) 42 43 #if defined(__LP64__) 44 /* HW supports 36-bit DMA addresses. */ 45 #define IWN_LOADDR(paddr) ((uint32_t)(paddr)) 46 #define IWN_HIADDR(paddr) (((paddr) >> 32) & 0xf) 47 #else 48 #define IWN_LOADDR(paddr) (paddr) 49 #define IWN_HIADDR(paddr) (0) 50 #endif 51 52 /* Base Address Register. */ 53 #define IWN_PCI_BAR0 PCI_MAPREG_START 54 55 /* 56 * Control and status registers. 57 */ 58 #define IWN_HW_IF_CONFIG 0x000 59 #define IWN_INT_COALESCING 0x004 60 #define IWN_INT 0x008 61 #define IWN_MASK 0x00c 62 #define IWN_FH_INT 0x010 63 #define IWN_RESET 0x020 64 #define IWN_GP_CNTRL 0x024 65 #define IWN_HW_REV 0x028 66 #define IWN_EEPROM 0x02c 67 #define IWN_EEPROM_GP 0x030 68 #define IWN_OTP_GP 0x034 69 #define IWN_GIO 0x03c 70 #define IWN_UCODE_GP1_CLR 0x05c 71 #define IWN_LED 0x094 72 #define IWN_GIO_CHICKEN 0x100 73 #define IWN_ANA_PLL 0x20c 74 #define IWN_DBG_HPET_MEM 0x240 75 #define IWN_MEM_RADDR 0x40c 76 #define IWN_MEM_WADDR 0x410 77 #define IWN_MEM_WDATA 0x418 78 #define IWN_MEM_RDATA 0x41c 79 #define IWN_PRPH_WADDR 0x444 80 #define IWN_PRPH_RADDR 0x448 81 #define IWN_PRPH_WDATA 0x44c 82 #define IWN_PRPH_RDATA 0x450 83 #define IWN_HBUS_TARG_WRPTR 0x460 84 85 /* 86 * Flow-Handler registers. 87 */ 88 #define IWN_FH_TFBD_CTRL0(qid) (0x1900 + (qid) * 8) 89 #define IWN_FH_TFBD_CTRL1(qid) (0x1904 + (qid) * 8) 90 #define IWN_FH_KW_ADDR 0x197c 91 #define IWN_FH_SRAM_ADDR(qid) (0x19a4 + (qid) * 4) 92 #define IWN_FH_CBBC_QUEUE(qid) (0x19d0 + (qid) * 4) 93 #define IWN_FH_STATUS_WPTR 0x1bc0 94 #define IWN_FH_RX_BASE 0x1bc4 95 #define IWN_FH_RX_WPTR 0x1bc8 96 #define IWN_FH_RX_CONFIG 0x1c00 97 #define IWN_FH_RX_STATUS 0x1c44 98 #define IWN_FH_TX_CONFIG(qid) (0x1d00 + (qid) * 32) 99 #define IWN_FH_TXBUF_STATUS(qid) (0x1d08 + (qid) * 32) 100 #define IWN_FH_TX_CHICKEN 0x1e98 101 #define IWN_FH_TX_STATUS 0x1eb0 102 103 /* 104 * TX scheduler registers. 105 */ 106 #define IWN_SCHED_BASE 0xa02c00 107 #define IWN_SCHED_SRAM_ADDR (IWN_SCHED_BASE + 0x000) 108 #define IWN5000_SCHED_DRAM_ADDR (IWN_SCHED_BASE + 0x008) 109 #define IWN4965_SCHED_DRAM_ADDR (IWN_SCHED_BASE + 0x010) 110 #define IWN5000_SCHED_TXFACT (IWN_SCHED_BASE + 0x010) 111 #define IWN4965_SCHED_TXFACT (IWN_SCHED_BASE + 0x01c) 112 #define IWN4965_SCHED_QUEUE_RDPTR(qid) (IWN_SCHED_BASE + 0x064 + (qid) * 4) 113 #define IWN5000_SCHED_QUEUE_RDPTR(qid) (IWN_SCHED_BASE + 0x068 + (qid) * 4) 114 #define IWN4965_SCHED_QCHAIN_SEL (IWN_SCHED_BASE + 0x0d0) 115 #define IWN4965_SCHED_INTR_MASK (IWN_SCHED_BASE + 0x0e4) 116 #define IWN5000_SCHED_QCHAIN_SEL (IWN_SCHED_BASE + 0x0e8) 117 #define IWN4965_SCHED_QUEUE_STATUS(qid) (IWN_SCHED_BASE + 0x104 + (qid) * 4) 118 #define IWN5000_SCHED_INTR_MASK (IWN_SCHED_BASE + 0x108) 119 #define IWN5000_SCHED_QUEUE_STATUS(qid) (IWN_SCHED_BASE + 0x10c + (qid) * 4) 120 #define IWN5000_SCHED_AGGR_SEL (IWN_SCHED_BASE + 0x248) 121 122 /* 123 * Offsets in TX scheduler's SRAM. 124 */ 125 #define IWN4965_SCHED_CTX_OFF 0x380 126 #define IWN4965_SCHED_CTX_LEN 416 127 #define IWN4965_SCHED_QUEUE_OFFSET(qid) (0x380 + (qid) * 8) 128 #define IWN4965_SCHED_TRANS_TBL(qid) (0x500 + (qid) * 2) 129 #define IWN5000_SCHED_CTX_OFF 0x600 130 #define IWN5000_SCHED_CTX_LEN 520 131 #define IWN5000_SCHED_QUEUE_OFFSET(qid) (0x600 + (qid) * 8) 132 #define IWN5000_SCHED_TRANS_TBL(qid) (0x7e0 + (qid) * 2) 133 134 /* 135 * NIC internal memory offsets. 136 */ 137 #define IWN_CLOCK_CTL 0x3000 138 #define IWN_APMG_CLK_CTRL 0x3004 139 #define IWN_APMG_CLK_DIS 0x3008 140 #define IWN_APMG_PS 0x300c 141 #define IWN_APMG_PCI_STT 0x3010 142 #define IWN_BSM_WR_CTRL 0x3400 143 #define IWN_BSM_WR_MEM_SRC 0x3404 144 #define IWN_BSM_WR_MEM_DST 0x3408 145 #define IWN_BSM_WR_DWCOUNT 0x340c 146 #define IWN_BSM_DRAM_TEXT_ADDR 0x3490 147 #define IWN_BSM_DRAM_TEXT_SIZE 0x3494 148 #define IWN_BSM_DRAM_DATA_ADDR 0x3498 149 #define IWN_BSM_DRAM_DATA_SIZE 0x349c 150 #define IWN_BSM_SRAM_BASE 0x3800 151 152 /* Possible values for IWN_APMG_CLK_DIS. */ 153 #define IWN_APMG_CLK_DMA_RQT (1 << 9) 154 155 /* Possible flags for register IWN_HW_IF_CONFIG. */ 156 #define IWN_HW_IF_CONFIG_4965_R (1 << 4) 157 #define IWN_HW_IF_CONFIG_MAC_SI (1 << 8) 158 #define IWN_HW_IF_CONFIG_RADIO_SI (1 << 9) 159 #define IWN_HW_IF_CONFIG_EEPROM_LOCKED (1 << 21) 160 #define IWN_HW_IF_CONFIG_NIC_READY (1 << 22) 161 #define IWN_HW_IF_CONFIG_HAP_WAKE_L1A (1 << 23) 162 #define IWN_HW_IF_CONFIG_PREPARE_DONE (1 << 25) 163 #define IWN_HW_IF_CONFIG_PREPARE (1 << 27) 164 165 /* Possible flags for registers IWN_PRPH_RADDR/IWN_PRPH_WADDR. */ 166 #define IWN_PRPH_DWORD ((sizeof (uint32_t) - 1) << 24) 167 168 /* Possible values for IWN_BSM_WR_MEM_DST. */ 169 #define IWN_FW_TEXT_BASE 0x00000000 170 #define IWN_FW_DATA_BASE 0x00800000 171 172 /* Possible flags for register IWN_RESET. */ 173 #define IWN_RESET_NEVO (1 << 0) 174 #define IWN_RESET_SW (1 << 7) 175 #define IWN_RESET_MASTER_DISABLED (1 << 8) 176 #define IWN_RESET_STOP_MASTER (1 << 9) 177 178 /* Possible flags for register IWN_GP_CNTRL. */ 179 #define IWN_GP_CNTRL_MAC_ACCESS_ENA (1 << 0) 180 #define IWN_GP_CNTRL_MAC_CLOCK_READY (1 << 0) 181 #define IWN_GP_CNTRL_INIT_DONE (1 << 2) 182 #define IWN_GP_CNTRL_MAC_ACCESS_REQ (1 << 3) 183 #define IWN_GP_CNTRL_SLEEP (1 << 4) 184 #define IWN_GP_CNTRL_RFKILL (1 << 27) 185 186 /* Possible flags for register IWN_HW_REV. */ 187 #define IWN_HW_REV_TYPE_SHIFT 4 188 #define IWN_HW_REV_TYPE_MASK 0x000000f0 189 #define IWN_HW_REV_TYPE_4965 0 190 #define IWN_HW_REV_TYPE_5300 2 191 #define IWN_HW_REV_TYPE_5350 3 192 #define IWN_HW_REV_TYPE_5150 4 193 #define IWN_HW_REV_TYPE_5100 5 194 #define IWN_HW_REV_TYPE_1000 6 195 #define IWN_HW_REV_TYPE_6000 7 196 #define IWN_HW_REV_TYPE_6050 8 197 198 /* Possible flags for register IWN_GIO_CHICKEN. */ 199 #define IWN_GIO_CHICKEN_L1A_NO_L0S_RX (1 << 23) 200 #define IWN_GIO_CHICKEN_DIS_L0S_TIMER (1 << 29) 201 202 /* Possible flags for register IWN_GIO. */ 203 #define IWN_GIO_L0S_ENA (1 << 1) 204 205 /* Possible flags for register IWN_UCODE_GP1_CLR. */ 206 #define IWN_UCODE_GP1_RFKILL (1 << 1) 207 #define IWN_UCODE_GP1_CMD_BLOCKED (1 << 2) 208 #define IWN_UCODE_GP1_CTEMP_STOP_RF (1 << 3) 209 210 /* Possible flags/values for register IWN_LED. */ 211 #define IWN_LED_BSM_CTRL (1 << 5) 212 #define IWN_LED_OFF 0x00000038 213 #define IWN_LED_ON 0x00000078 214 215 /* Possible values for register IWN_ANA_PLL. */ 216 #define IWN_ANA_PLL_INIT 0x00880300 217 218 /* Possible flags for register IWN_FH_RX_STATUS. */ 219 #define IWN_FH_RX_STATUS_IDLE (1 << 24) 220 221 /* Possible flags for register IWN_BSM_WR_CTRL. */ 222 #define IWN_BSM_WR_CTRL_START_EN (1 << 30) 223 #define IWN_BSM_WR_CTRL_START (1 << 31) 224 225 /* Possible flags for register IWN_INT. */ 226 #define IWN_INT_ALIVE (1 << 0) 227 #define IWN_INT_WAKEUP (1 << 1) 228 #define IWN_INT_SW_RX (1 << 3) 229 #define IWN_INT_CT_REACHED (1 << 6) 230 #define IWN_INT_RF_TOGGLED (1 << 7) 231 #define IWN_INT_SW_ERR (1 << 25) 232 #define IWN_INT_FH_TX (1 << 27) 233 #define IWN_INT_HW_ERR (1 << 29) 234 #define IWN_INT_FH_RX (1 << 31) 235 236 /* Shortcut. */ 237 #define IWN_INT_MASK \ 238 (IWN_INT_SW_ERR | IWN_INT_HW_ERR | IWN_INT_FH_TX | \ 239 IWN_INT_FH_RX | IWN_INT_ALIVE | IWN_INT_WAKEUP | \ 240 IWN_INT_SW_RX | IWN_INT_CT_REACHED | IWN_INT_RF_TOGGLED) 241 242 /* Possible flags for register IWN_FH_INT. */ 243 #define IWN_FH_INT_TX_CHNL(x) (1 << (x)) 244 #define IWN_FH_INT_RX_CHNL(x) (1 << ((x) + 16)) 245 #define IWN_FH_INT_HI_PRIOR (1 << 30) 246 /* Shortcuts for the above. */ 247 #define IWN_FH_INT_TX \ 248 (IWN_FH_INT_TX_CHNL(0) | IWN_FH_INT_TX_CHNL(1)) 249 #define IWN_FH_INT_RX \ 250 (IWN_FH_INT_RX_CHNL(0) | IWN_FH_INT_RX_CHNL(1) | IWN_FH_INT_HI_PRIOR) 251 252 /* Possible flags/values for register IWN_FH_TX_CONFIG. */ 253 #define IWN_FH_TX_CONFIG_DMA_PAUSE 0 254 #define IWN_FH_TX_CONFIG_DMA_ENA (1 << 31) 255 #define IWN_FH_TX_CONFIG_CIRQ_HOST_ENDTFD (1 << 20) 256 257 /* Possible flags/values for register IWN_FH_TXBUF_STATUS. */ 258 #define IWN_FH_TXBUF_STATUS_TBNUM(x) ((x) << 20) 259 #define IWN_FH_TXBUF_STATUS_TBIDX(x) ((x) << 12) 260 #define IWN_FH_TXBUF_STATUS_TFBD_VALID 3 261 262 /* Possible flags for register IWN_FH_TX_CHICKEN. */ 263 #define IWN_FH_TX_CHICKEN_SCHED_RETRY (1 << 1) 264 265 /* Possible flags for register IWN_FH_TX_STATUS. */ 266 #define IWN_FH_TX_STATUS_IDLE(chnl) \ 267 (1 << ((chnl) + 24) | 1 << ((chnl) + 16)) 268 269 /* Possible flags for register IWN_FH_RX_CONFIG. */ 270 #define IWN_FH_RX_CONFIG_ENA (1 << 31) 271 #define IWN_FH_RX_CONFIG_NRBD(x) ((x) << 20) 272 #define IWN_FH_RX_CONFIG_RB_SIZE_8K (1 << 16) 273 #define IWN_FH_RX_CONFIG_SINGLE_FRAME (1 << 15) 274 #define IWN_FH_RX_CONFIG_IRQ_DST_HOST (1 << 12) 275 #define IWN_FH_RX_CONFIG_RB_TIMEOUT(x) ((x) << 4) 276 #define IWN_FH_RX_CONFIG_IGN_RXF_EMPTY (1 << 2) 277 278 /* Possible flags for register IWN_FH_TX_CONFIG. */ 279 #define IWN_FH_TX_CONFIG_DMA_ENA (1 << 31) 280 #define IWN_FH_TX_CONFIG_DMA_CREDIT_ENA (1 << 3) 281 282 /* Possible flags for register IWN_EEPROM. */ 283 #define IWN_EEPROM_READ_VALID (1 << 0) 284 #define IWN_EEPROM_CMD (1 << 1) 285 286 /* Possible flags for register IWN_EEPROM_GP. */ 287 #define IWN_EEPROM_GP_IF_OWNER 0x00000180 288 289 /* Possible flags for register IWN_OTP_GP. */ 290 #define IWN_OTP_GP_DEV_SEL_OTP (1 << 16) 291 #define IWN_OTP_GP_RELATIVE_ACCESS (1 << 17) 292 #define IWN_OTP_GP_ECC_CORR_STTS (1 << 20) 293 #define IWN_OTP_GP_ECC_UNCORR_STTS (1 << 21) 294 295 /* Possible flags for register IWN_SCHED_QUEUE_STATUS. */ 296 #define IWN4965_TXQ_STATUS_ACTIVE 0x0007fc01 297 #define IWN4965_TXQ_STATUS_INACTIVE 0x0007fc00 298 #define IWN4965_TXQ_STATUS_AGGR_ENA (1 << 5 | 1 << 8) 299 #define IWN4965_TXQ_STATUS_CHGACT (1 << 10) 300 #define IWN5000_TXQ_STATUS_ACTIVE 0x00ff0018 301 #define IWN5000_TXQ_STATUS_INACTIVE 0x00ff0010 302 #define IWN5000_TXQ_STATUS_CHGACT (1 << 19) 303 304 /* Possible flags for register IWN_APMG_CLK_CTRL. */ 305 #define IWN_APMG_CLK_CTRL_DMA_CLK_RQT (1 << 9) 306 #define IWN_APMG_CLK_CTRL_BSM_CLK_RQT (1 << 11) 307 308 /* Possible flags for register IWN_APMG_PS. */ 309 #define IWN_APMG_PS_EARLY_PWROFF_DIS (1 << 22) 310 #define IWN_APMG_PS_PWR_SRC(x) ((x) << 24) 311 #define IWN_APMG_PS_PWR_SRC_VMAIN 0 312 #define IWN_APMG_PS_PWR_SRC_VAUX 2 313 #define IWN_APMG_PS_PWR_SRC_MASK IWN_APMG_PS_PWR_SRC(3) 314 #define IWN_APMG_PS_RESET_REQ (1 << 26) 315 316 /* Possible flags for IWN_APMG_PCI_STT. */ 317 #define IWN_APMG_PCI_STT_L1A_DIS (1 << 11) 318 319 /* Possible flags for register IWN_BSM_DRAM_TEXT_SIZE. */ 320 #define IWN_FW_UPDATED (1 << 31) 321 322 #define IWN_SCHED_WINSZ 64 323 #define IWN_SCHED_LIMIT 64 324 #define IWN4965_SCHED_COUNT 512 325 #define IWN5000_SCHED_COUNT (IWN_TX_RING_COUNT + IWN_SCHED_WINSZ) 326 #define IWN4965_SCHEDSZ (IWN4965_NTXQUEUES * IWN4965_SCHED_COUNT * 2) 327 #define IWN5000_SCHEDSZ (IWN5000_NTXQUEUES * IWN5000_SCHED_COUNT * 2) 328 329 struct iwn_tx_desc { 330 uint8_t reserved1[3]; 331 uint8_t nsegs; 332 struct { 333 uint32_t addr; 334 uint16_t len; 335 } __packed segs[IWN_MAX_SCATTER]; 336 /* Pad to 128 bytes. */ 337 uint32_t reserved2; 338 } __packed; 339 340 struct iwn_rx_status { 341 uint16_t closed_count; 342 uint16_t closed_rx_count; 343 uint16_t finished_count; 344 uint16_t finished_rx_count; 345 uint32_t reserved[2]; 346 } __packed; 347 348 struct iwn_rx_desc { 349 uint32_t len; 350 uint8_t type; 351 #define IWN_UC_READY 1 352 #define IWN_ADD_NODE_DONE 24 353 #define IWN_TX_DONE 28 354 #define IWN5000_CALIBRATION_RESULT 102 355 #define IWN5000_CALIBRATION_DONE 103 356 #define IWN_START_SCAN 130 357 #define IWN_STOP_SCAN 132 358 #define IWN_RX_STATISTICS 156 359 #define IWN_BEACON_STATISTICS 157 360 #define IWN_STATE_CHANGED 161 361 #define IWN_BEACON_MISSED 162 362 #define IWN_RX_PHY 192 363 #define IWN_MPDU_RX_DONE 193 364 #define IWN_RX_DONE 195 365 366 uint8_t flags; 367 uint8_t idx; 368 uint8_t qid; 369 } __packed; 370 371 /* Possible RX status flags. */ 372 #define IWN_RX_NO_CRC_ERR (1 << 0) 373 #define IWN_RX_NO_OVFL_ERR (1 << 1) 374 /* Shortcut for the above. */ 375 #define IWN_RX_NOERROR (IWN_RX_NO_CRC_ERR | IWN_RX_NO_OVFL_ERR) 376 #define IWN_RX_MPDU_MIC_OK (1 << 6) 377 #define IWN_RX_CIPHER_MASK (7 << 8) 378 #define IWN_RX_CIPHER_CCMP (2 << 8) 379 #define IWN_RX_MPDU_DEC (1 << 11) 380 #define IWN_RX_DECRYPT_MASK (3 << 11) 381 #define IWN_RX_DECRYPT_OK (3 << 11) 382 383 struct iwn_tx_cmd { 384 uint8_t code; 385 #define IWN_CMD_CONFIGURE 16 386 #define IWN_CMD_ASSOCIATE 17 387 #define IWN_CMD_EDCA_PARAMS 19 388 #define IWN_CMD_TIMING 20 389 #define IWN_CMD_ADD_NODE 24 390 #define IWN_CMD_TX_DATA 28 391 #define IWN_CMD_LINK_QUALITY 78 392 #define IWN_CMD_SET_LED 72 393 #define IWN5000_CMD_WIMAX_COEX 90 394 #define IWN5000_CMD_CALIB_CONFIG 101 395 #define IWN_CMD_SET_POWER_MODE 119 396 #define IWN_CMD_SCAN 128 397 #define IWN_CMD_TXPOWER 151 398 #define IWN_CMD_TXPOWER_DBM 152 399 #define IWN_CMD_BT_COEX 155 400 #define IWN_CMD_GET_STATISTICS 156 401 #define IWN_CMD_SET_CRITICAL_TEMP 164 402 #define IWN_CMD_SET_SENSITIVITY 168 403 #define IWN_CMD_PHY_CALIB 176 404 405 uint8_t flags; 406 uint8_t idx; 407 uint8_t qid; 408 uint8_t data[136]; 409 } __packed; 410 411 /* Antenna flags, used in various commands. */ 412 #define IWN_ANT_A (1 << 0) 413 #define IWN_ANT_B (1 << 1) 414 #define IWN_ANT_C (1 << 2) 415 /* Shortcut. */ 416 #define IWN_ANT_ABC (IWN_ANT_A | IWN_ANT_B | IWN_ANT_C) 417 418 /* Structure for command IWN_CMD_CONFIGURE. */ 419 struct iwn_rxon { 420 uint8_t myaddr[IEEE80211_ADDR_LEN]; 421 uint16_t reserved1; 422 uint8_t bssid[IEEE80211_ADDR_LEN]; 423 uint16_t reserved2; 424 uint8_t wlap[IEEE80211_ADDR_LEN]; 425 uint16_t reserved3; 426 uint8_t mode; 427 #define IWN_MODE_HOSTAP 1 428 #define IWN_MODE_STA 3 429 #define IWN_MODE_IBSS 4 430 #define IWN_MODE_MONITOR 6 431 432 uint8_t air; 433 uint16_t rxchain; 434 #define IWN_RXCHAIN_FORCE (1 << 0) 435 #define IWN_RXCHAIN_VALID(x) ((x) << 1) 436 #define IWN_RXCHAIN_SEL(x) ((x) << 4) 437 #define IWN_RXCHAIN_MIMO(x) ((x) << 7) 438 #define IWN_RXCHAIN_IDLE_COUNT(x) ((x) << 10) 439 #define IWN_RXCHAIN_MIMO_COUNT(x) ((x) << 12) 440 #define IWN_RXCHAIN_MIMO_FORCE (1 << 14) 441 442 uint8_t ofdm_mask; 443 uint8_t cck_mask; 444 uint16_t associd; 445 uint32_t flags; 446 #define IWN_RXON_24GHZ 0x00000001 /* band */ 447 #define IWN_RXON_CCK 0x00000002 /* modulation */ 448 #define IWN_RXON_AUTO 0x00000004 /* 2.4-only auto-detect */ 449 #define IWN_RXON_HTPROT 0x00000008 /* xmit with HT protection */ 450 #define IWN_RXON_SHSLOT 0x00000010 /* short slot time */ 451 #define IWN_RXON_SHPREAMBLE 0x00000020 /* short premable */ 452 #define IWN_RXON_NODIVERSITY 0x00000080 /* disable antenna diversity */ 453 #define IWN_RXON_ANTENNA_A 0x00000100 454 #define IWN_RXON_ANTENNA_B 0x00000200 455 #define IWN_RXON_RADAR 0x00001000 /* enable radar detect */ 456 #define IWN_RXON_NARROW 0x00002000 /* MKK narrow band select */ 457 #define IWN_RXON_TSF 0x00008000 458 #define IWN_RXON_HT 0x06400000 459 #define IWN_RXON_HT20 0x02000000 460 #define IWN_RXON_HT40U 0x04000000 461 #define IWN_RXON_HT40D 0x04400000 462 #define IWN_RXON_CTS_TO_SELF 0x40000000 463 464 uint32_t filter; 465 #define IWN_FILTER_PROMISC (1 << 0) 466 #define IWN_FILTER_CTL (1 << 1) 467 #define IWN_FILTER_MULTICAST (1 << 2) 468 #define IWN_FILTER_NODECRYPT (1 << 3) 469 #define IWN_FILTER_BSS (1 << 5) 470 #define IWN_FILTER_BEACON (1 << 6) 471 472 uint8_t chan; 473 uint8_t reserved4; 474 uint8_t ht_single_mask; 475 uint8_t ht_dual_mask; 476 /* The following fields are for 5000 Series only. */ 477 uint8_t ht_triple_mask; 478 uint8_t reserved5; 479 uint16_t acquisition; 480 uint16_t reserved6; 481 } __packed; 482 483 #define IWN4965_RXONSZ (sizeof (struct iwn_rxon) - 6) 484 #define IWN5000_RXONSZ (sizeof (struct iwn_rxon)) 485 486 /* Structure for command IWN_CMD_ASSOCIATE. */ 487 struct iwn_assoc { 488 uint32_t flags; 489 uint32_t filter; 490 uint8_t ofdm_mask; 491 uint8_t cck_mask; 492 uint16_t reserved; 493 } __packed; 494 495 /* Structure for command IWN_CMD_EDCA_PARAMS. */ 496 struct iwn_edca_params { 497 uint32_t flags; 498 #define IWN_EDCA_UPDATE (1 << 0) 499 #define IWN_EDCA_TXOP (1 << 4) 500 501 struct { 502 uint16_t cwmin; 503 uint16_t cwmax; 504 uint8_t aifsn; 505 uint8_t reserved; 506 uint16_t txoplimit; 507 } __packed ac[EDCA_NUM_AC]; 508 } __packed; 509 510 /* Structure for command IWN_CMD_TIMING. */ 511 struct iwn_cmd_timing { 512 uint64_t tstamp; 513 uint16_t bintval; 514 uint16_t atim; 515 uint32_t binitval; 516 uint16_t lintval; 517 uint16_t reserved; 518 } __packed; 519 520 /* Structure for command IWN_CMD_ADD_NODE. */ 521 struct iwn_node_info { 522 uint8_t control; 523 #define IWN_NODE_UPDATE (1 << 0) 524 525 uint8_t reserved1[3]; 526 527 uint8_t macaddr[IEEE80211_ADDR_LEN]; 528 uint16_t reserved2; 529 uint8_t id; 530 #define IWN_ID_BSS 0 531 #define IWN5000_ID_BROADCAST 15 532 #define IWN4965_ID_BROADCAST 31 533 534 uint8_t flags; 535 #define IWN_FLAG_SET_KEY (1 << 0) 536 #define IWN_FLAG_SET_DISABLE_TID (1 << 1) 537 #define IWN_FLAG_SET_TXRATE (1 << 2) 538 #define IWN_FLAG_SET_ADDBA (1 << 3) 539 #define IWN_FLAG_SET_DELBA (1 << 4) 540 541 uint16_t reserved3; 542 uint16_t kflags; 543 #define IWN_KFLAG_CCMP (1 << 1) 544 #define IWN_KFLAG_MAP (1 << 3) 545 #define IWN_KFLAG_KID(kid) ((kid) << 8) 546 #define IWN_KFLAG_INVALID (1 << 11) 547 #define IWN_KFLAG_GROUP (1 << 14) 548 549 uint8_t tsc2; /* TKIP TSC2 */ 550 uint8_t reserved4; 551 uint16_t ttak[5]; 552 uint8_t kid; 553 uint8_t reserved5; 554 uint8_t key[16]; 555 /* The following 3 fields are for 5000 Series only. */ 556 uint64_t tsc; 557 uint8_t rxmic[8]; 558 uint8_t txmic[8]; 559 560 uint32_t htflags; 561 #define IWN_AMDPU_SIZE_FACTOR(x) ((x) << 19) 562 #define IWN_AMDPU_DENSITY(x) ((x) << 23) 563 564 uint32_t mask; 565 uint16_t disable_tid; 566 uint16_t reserved6; 567 uint8_t addba_tid; 568 uint8_t delba_tid; 569 uint16_t addba_ssn; 570 uint32_t reserved7; 571 } __packed; 572 573 struct iwn4965_node_info { 574 uint8_t control; 575 uint8_t reserved1[3]; 576 uint8_t macaddr[IEEE80211_ADDR_LEN]; 577 uint16_t reserved2; 578 uint8_t id; 579 uint8_t flags; 580 uint16_t reserved3; 581 uint16_t kflags; 582 uint8_t tsc2; /* TKIP TSC2 */ 583 uint8_t reserved4; 584 uint16_t ttak[5]; 585 uint8_t kid; 586 uint8_t reserved5; 587 uint8_t key[16]; 588 uint32_t htflags; 589 uint32_t mask; 590 uint16_t disable_tid; 591 uint16_t reserved6; 592 uint8_t addba_tid; 593 uint8_t delba_tid; 594 uint16_t addba_ssn; 595 uint32_t reserved7; 596 } __packed; 597 598 #define IWN_RFLAG_HT (1 << 0) /* use HT modulation */ 599 #define IWN_RFLAG_CCK (1 << 1) /* use CCK modulation */ 600 #define IWN_RFLAG_HT40 (1 << 3) /* use dual-stream */ 601 #define IWN_RFLAG_SGI (1 << 5) /* use short GI */ 602 #define IWN_RFLAG_ANT_A (1 << 6) /* start on antenna port A */ 603 #define IWN_RFLAG_ANT_B (1 << 7) /* start on antenna port B */ 604 #define IWN_RFLAG_ANT(x) ((x) << 6) 605 606 /* Structure for command IWN_CMD_TX_DATA. */ 607 struct iwn_cmd_data { 608 uint16_t len; 609 uint16_t lnext; 610 uint32_t flags; 611 #define IWN_TX_NEED_PROTECTION (1 << 0) /* 5000 only */ 612 #define IWN_TX_NEED_RTS (1 << 1) 613 #define IWN_TX_NEED_CTS (1 << 2) 614 #define IWN_TX_NEED_ACK (1 << 3) 615 #define IWN_TX_LINKQ (1 << 4) 616 #define IWN_TX_IMM_BA (1 << 6) 617 #define IWN_TX_FULL_TXOP (1 << 7) 618 #define IWN_TX_BT_DISABLE (1 << 12) /* bluetooth coexistence */ 619 #define IWN_TX_AUTO_SEQ (1 << 13) 620 #define IWN_TX_MORE_FRAG (1 << 14) 621 #define IWN_TX_INSERT_TSTAMP (1 << 16) 622 #define IWN_TX_NEED_PADDING (1 << 20) 623 624 uint32_t scratch; 625 uint8_t plcp; 626 uint8_t rflags; 627 uint16_t xrflags; 628 629 uint8_t id; 630 uint8_t security; 631 #define IWN_CIPHER_WEP40 1 632 #define IWN_CIPHER_CCMP 2 633 #define IWN_CIPHER_TKIP 3 634 #define IWN_CIPHER_WEP104 9 635 636 uint8_t linkq; 637 uint8_t reserved2; 638 uint8_t key[16]; 639 uint16_t fnext; 640 uint16_t reserved3; 641 uint32_t lifetime; 642 #define IWN_LIFETIME_INFINITE 0xffffffff 643 644 uint32_t loaddr; 645 uint8_t hiaddr; 646 uint8_t rts_ntries; 647 uint8_t data_ntries; 648 uint8_t tid; 649 uint16_t timeout; 650 uint16_t txop; 651 } __packed; 652 653 /* Structure for command IWN_CMD_LINK_QUALITY. */ 654 #define IWN_MAX_TX_RETRIES 16 655 struct iwn_cmd_link_quality { 656 uint8_t id; 657 uint8_t reserved1; 658 uint16_t ctl; 659 uint8_t flags; 660 uint8_t mimo; 661 uint8_t antmsk_1stream; 662 uint8_t antmsk_2stream; 663 uint8_t ridx[EDCA_NUM_AC]; 664 uint16_t ampdu_limit; 665 uint8_t ampdu_threshold; 666 uint8_t ampdu_max; 667 uint32_t reserved2; 668 struct { 669 uint8_t plcp; 670 uint8_t rflags; 671 uint16_t xrflags; 672 } __packed retry[IWN_MAX_TX_RETRIES]; 673 uint32_t reserved3; 674 } __packed; 675 676 /* Structure for command IWN_CMD_SET_LED. */ 677 struct iwn_cmd_led { 678 uint32_t unit; /* multiplier (in usecs) */ 679 uint8_t which; 680 #define IWN_LED_ACTIVITY 1 681 #define IWN_LED_LINK 2 682 683 uint8_t off; 684 uint8_t on; 685 uint8_t reserved; 686 } __packed; 687 688 /* Structure for command IWN5000_CMD_WIMAX_COEX. */ 689 struct iwn5000_wimax_coex { 690 uint32_t flags; 691 struct { 692 uint8_t request; 693 uint8_t window; 694 uint8_t reserved; 695 uint8_t flags; 696 } __packed events[16]; 697 } __packed; 698 699 /* Structures for command IWN5000_CMD_CALIB_CONFIG. */ 700 struct iwn5000_calib_elem { 701 uint32_t enable; 702 uint32_t start; 703 uint32_t send; 704 uint32_t apply; 705 uint32_t reserved; 706 } __packed; 707 708 struct iwn5000_calib_status { 709 struct iwn5000_calib_elem once; 710 struct iwn5000_calib_elem perd; 711 uint32_t flags; 712 } __packed; 713 714 struct iwn5000_calib_config { 715 struct iwn5000_calib_status ucode; 716 struct iwn5000_calib_status driver; 717 uint32_t reserved; 718 } __packed; 719 720 /* Structure for command IWN_CMD_SET_POWER_MODE. */ 721 struct iwn_pmgt_cmd { 722 uint16_t flags; 723 #define IWN_PS_ALLOW_SLEEP (1 << 0) 724 #define IWN_PS_NOTIFY (1 << 1) 725 #define IWN_PS_SLEEP_OVER_DTIM (1 << 2) 726 #define IWN_PS_PCI_PMGT (1 << 3) 727 #define IWN_PS_FAST_PD (1 << 4) 728 729 uint8_t keepalive; 730 uint8_t debug; 731 uint32_t rxtimeout; 732 uint32_t txtimeout; 733 uint32_t intval[5]; 734 uint32_t beacons; 735 } __packed; 736 737 /* Structures for command IWN_CMD_SCAN. */ 738 struct iwn_scan_essid { 739 uint8_t id; 740 uint8_t len; 741 uint8_t data[IEEE80211_NWID_LEN]; 742 } __packed; 743 744 struct iwn_scan_hdr { 745 uint16_t len; 746 uint8_t reserved1; 747 uint8_t nchan; 748 uint16_t quiet_time; 749 uint16_t quiet_threshold; 750 uint16_t crc_threshold; 751 uint16_t rxchain; 752 uint32_t max_svc; /* background scans */ 753 uint32_t pause_svc; /* background scans */ 754 uint32_t flags; 755 uint32_t filter; 756 757 /* Followed by a struct iwn_cmd_data. */ 758 /* Followed by an array of 20 structs iwn_scan_essid. */ 759 /* Followed by probe request body. */ 760 /* Followed by an array of ``nchan'' structs iwn_scan_chan. */ 761 } __packed; 762 763 struct iwn_scan_chan { 764 uint32_t flags; 765 #define IWN_CHAN_ACTIVE (1 << 0) 766 #define IWN_CHAN_NPBREQS(x) (((1 << (x)) - 1) << 1) 767 768 uint16_t chan; 769 uint8_t rf_gain; 770 uint8_t dsp_gain; 771 uint16_t active; /* msecs */ 772 uint16_t passive; /* msecs */ 773 } __packed; 774 775 /* Maximum size of a scan command. */ 776 #define IWN_SCAN_MAXSZ (MCLBYTES - 4) 777 778 /* Structure for command IWN_CMD_TXPOWER (4965AGN only.) */ 779 #define IWN_RIDX_MAX 32 780 struct iwn4965_cmd_txpower { 781 uint8_t band; 782 uint8_t reserved1; 783 uint8_t chan; 784 uint8_t reserved2; 785 struct { 786 uint8_t rf_gain[2]; 787 uint8_t dsp_gain[2]; 788 } __packed power[IWN_RIDX_MAX + 1]; 789 } __packed; 790 791 /* Structure for command IWN_CMD_TXPOWER_DBM (5000 Series only.) */ 792 struct iwn5000_cmd_txpower { 793 int8_t global_limit; /* in half-dBm */ 794 #define IWN5000_TXPOWER_AUTO 0x7f 795 #define IWN5000_TXPOWER_MAX_DBM 16 796 797 uint8_t flags; 798 #define IWN5000_TXPOWER_NO_CLOSED (1 << 6) 799 800 int8_t srv_limit; /* in half-dBm */ 801 uint8_t reserved; 802 } __packed; 803 804 /* Structure for command IWN_CMD_BLUETOOTH. */ 805 struct iwn_bluetooth { 806 uint8_t flags; 807 uint8_t lead; 808 uint8_t kill; 809 uint8_t reserved; 810 uint32_t ack; 811 uint32_t cts; 812 } __packed; 813 814 /* Structure for command IWN_CMD_SET_CRITICAL_TEMP. */ 815 struct iwn_critical_temp { 816 uint32_t reserved; 817 uint32_t tempM; 818 uint32_t tempR; 819 /* degK <-> degC conversion macros. */ 820 #define IWN_CTOK(c) ((c) + 273) 821 #define IWN_KTOC(k) ((k) - 273) 822 #define IWN_CTOMUK(c) (((c) * 1000000) + 273150000) 823 } __packed; 824 825 /* Structure for command IWN_CMD_SET_SENSITIVITY. */ 826 struct iwn_sensitivity_cmd { 827 uint16_t which; 828 #define IWN_SENSITIVITY_DEFAULTTBL 0 829 #define IWN_SENSITIVITY_WORKTBL 1 830 831 uint16_t energy_cck; 832 uint16_t energy_ofdm; 833 uint16_t corr_ofdm_x1; 834 uint16_t corr_ofdm_mrc_x1; 835 uint16_t corr_cck_mrc_x4; 836 uint16_t corr_ofdm_x4; 837 uint16_t corr_ofdm_mrc_x4; 838 uint16_t corr_barker; 839 uint16_t corr_barker_mrc; 840 uint16_t corr_cck_x4; 841 uint16_t energy_ofdm_th; 842 } __packed; 843 844 /* Structures for command IWN_CMD_PHY_CALIB. */ 845 struct iwn_phy_calib { 846 uint8_t code; 847 #define IWN4965_PHY_CALIB_DIFF_GAIN 7 848 #define IWN5000_PHY_CALIB_DC 8 849 #define IWN5000_PHY_CALIB_LO 9 850 #define IWN5000_PHY_CALIB_TX_IQ 11 851 #define IWN5000_PHY_CALIB_CRYSTAL 15 852 #define IWN5000_PHY_CALIB_BASE_BAND 16 853 #define IWN5000_PHY_CALIB_TX_IQ_PERD 17 854 #define IWN5000_PHY_CALIB_RESET_NOISE_GAIN 18 855 #define IWN5000_PHY_CALIB_NOISE_GAIN 19 856 857 uint8_t group; 858 uint8_t ngroups; 859 uint8_t isvalid; 860 } __packed; 861 862 struct iwn5000_phy_calib_crystal { 863 uint8_t code; 864 uint8_t group; 865 uint8_t ngroups; 866 uint8_t isvalid; 867 868 uint8_t cap_pin[2]; 869 uint8_t reserved[2]; 870 } __packed; 871 872 struct iwn_phy_calib_gain { 873 uint8_t code; 874 uint8_t group; 875 uint8_t ngroups; 876 uint8_t isvalid; 877 878 int8_t gain[3]; 879 uint8_t reserved; 880 } __packed; 881 882 /* Structure for command IWN_CMD_SPECTRUM_MEASUREMENT. */ 883 struct iwn_spectrum_cmd { 884 uint16_t len; 885 uint8_t token; 886 uint8_t id; 887 uint8_t origin; 888 uint8_t periodic; 889 uint16_t timeout; 890 uint32_t start; 891 uint32_t reserved1; 892 uint32_t flags; 893 uint32_t filter; 894 uint16_t nchan; 895 uint16_t reserved2; 896 struct { 897 uint32_t duration; 898 uint8_t chan; 899 uint8_t type; 900 #define IWN_MEASUREMENT_BASIC (1 << 0) 901 #define IWN_MEASUREMENT_CCA (1 << 1) 902 #define IWN_MEASUREMENT_RPI_HISTOGRAM (1 << 2) 903 #define IWN_MEASUREMENT_NOISE_HISTOGRAM (1 << 3) 904 #define IWN_MEASUREMENT_FRAME (1 << 4) 905 #define IWN_MEASUREMENT_IDLE (1 << 7) 906 907 uint16_t reserved; 908 } __packed chan[10]; 909 } __packed; 910 911 /* Structure for IWN_UC_READY notification. */ 912 #define IWN_NATTEN_GROUPS 5 913 struct iwn_ucode_info { 914 uint8_t minor; 915 uint8_t major; 916 uint16_t reserved1; 917 uint8_t revision[8]; 918 uint8_t type; 919 uint8_t subtype; 920 #define IWN_UCODE_RUNTIME 0 921 #define IWN_UCODE_INIT 9 922 923 uint16_t reserved2; 924 uint32_t logptr; 925 uint32_t errptr; 926 uint32_t tstamp; 927 uint32_t valid; 928 929 /* The following fields are for UCODE_INIT only. */ 930 int32_t volt; 931 struct { 932 int32_t chan20MHz; 933 int32_t chan40MHz; 934 } __packed temp[4]; 935 int32_t atten[IWN_NATTEN_GROUPS][2]; 936 } __packed; 937 938 /* Structures for IWN_TX_DONE notification. */ 939 #define IWN_TX_SUCCESS 0x00 940 #define IWN_TX_FAIL 0x80 /* all failures have 0x80 set */ 941 #define IWN_TX_FAIL_SHORT_LIMIT 0x82 /* too many RTS retries */ 942 #define IWN_TX_FAIL_LONG_LIMIT 0x83 /* too many retries */ 943 #define IWN_TX_FAIL_FIFO_UNDERRRUN 0x84 /* tx fifo not kept running */ 944 #define IWN_TX_FAIL_DEST_IN_PS 0x88 /* sta found in power save */ 945 #define IWN_TX_FAIL_TX_LOCKED 0x90 /* waiting to see traffic */ 946 947 struct iwn4965_tx_stat { 948 uint8_t nframes; 949 uint8_t killcnt; 950 uint8_t rtscnt; 951 uint8_t retrycnt; 952 uint8_t rate; 953 uint8_t rflags; 954 uint16_t xrflags; 955 uint16_t duration; 956 uint16_t reserved; 957 uint32_t power[2]; 958 uint32_t status; 959 } __packed; 960 961 struct iwn5000_tx_stat { 962 uint8_t nframes; 963 uint8_t killcnt; 964 uint8_t rtscnt; 965 uint8_t retrycnt; 966 uint8_t rate; 967 uint8_t rflags; 968 uint16_t xrflags; 969 uint16_t duration; 970 uint16_t reserved; 971 uint32_t power[2]; 972 uint32_t info; 973 uint16_t seq; 974 uint16_t len; 975 uint32_t tlc; 976 uint16_t status; 977 uint16_t sequence; 978 } __packed; 979 980 /* Structure for IWN_BEACON_MISSED notification. */ 981 struct iwn_beacon_missed { 982 uint32_t consecutive; 983 uint32_t total; 984 uint32_t expected; 985 uint32_t received; 986 } __packed; 987 988 /* Structure for IWN_MPDU_RX_DONE notification. */ 989 struct iwn_rx_mpdu { 990 uint16_t len; 991 uint16_t reserved; 992 } __packed; 993 994 /* Structures for IWN_RX_DONE and IWN_MPDU_RX_DONE notifications. */ 995 struct iwn4965_rx_phystat { 996 uint16_t antenna; 997 uint16_t agc; 998 uint8_t rssi[6]; 999 } __packed; 1000 1001 struct iwn5000_rx_phystat { 1002 uint32_t reserved1; 1003 uint32_t agc; 1004 uint16_t rssi[3]; 1005 } __packed; 1006 1007 struct iwn_rx_stat { 1008 uint8_t phy_len; 1009 uint8_t cfg_phy_len; 1010 #define IWN_STAT_MAXLEN 20 1011 1012 uint8_t id; 1013 uint8_t reserved1; 1014 uint64_t tstamp; 1015 uint32_t beacon; 1016 uint16_t flags; 1017 #define IWN_STAT_FLAG_SHPREAMBLE (1 << 2) 1018 1019 uint16_t chan; 1020 uint8_t phybuf[32]; 1021 uint8_t rate; 1022 uint8_t rflags; 1023 uint16_t xrflags; 1024 uint16_t len; 1025 uint16_t reserve3; 1026 } __packed; 1027 1028 #define IWN_RSSI_TO_DBM 44 1029 1030 /* Structure for IWN_START_SCAN notification. */ 1031 struct iwn_start_scan { 1032 uint64_t tstamp; 1033 uint32_t tbeacon; 1034 uint8_t chan; 1035 uint8_t band; 1036 uint16_t reserved; 1037 uint32_t status; 1038 } __packed; 1039 1040 /* Structure for IWN_STOP_SCAN notification. */ 1041 struct iwn_stop_scan { 1042 uint8_t nchan; 1043 uint8_t status; 1044 uint8_t reserved; 1045 uint8_t chan; 1046 uint64_t tsf; 1047 } __packed; 1048 1049 /* Structure for IWN_SPECTRUM_MEASUREMENT notification. */ 1050 struct iwn_spectrum_notif { 1051 uint8_t id; 1052 uint8_t token; 1053 uint8_t idx; 1054 uint8_t state; 1055 #define IWN_MEASUREMENT_START 0 1056 #define IWN_MEASUREMENT_STOP 1 1057 1058 uint32_t start; 1059 uint8_t band; 1060 uint8_t chan; 1061 uint8_t type; 1062 uint8_t reserved1; 1063 uint32_t cca_ofdm; 1064 uint32_t cca_cck; 1065 uint32_t cca_time; 1066 uint8_t basic; 1067 uint8_t reserved2[3]; 1068 uint32_t ofdm[8]; 1069 uint32_t cck[8]; 1070 uint32_t stop; 1071 uint32_t status; 1072 #define IWN_MEASUREMENT_OK 0 1073 #define IWN_MEASUREMENT_CONCURRENT 1 1074 #define IWN_MEASUREMENT_CSA_CONFLICT 2 1075 #define IWN_MEASUREMENT_TGH_CONFLICT 3 1076 #define IWN_MEASUREMENT_STOPPED 6 1077 #define IWN_MEASUREMENT_TIMEOUT 7 1078 #define IWN_MEASUREMENT_FAILED 8 1079 } __packed; 1080 1081 /* Structure for IWN_{RX,BEACON}_STATISTICS notification. */ 1082 struct iwn_rx_phy_stats { 1083 uint32_t ina; 1084 uint32_t fina; 1085 uint32_t bad_plcp; 1086 uint32_t bad_crc32; 1087 uint32_t overrun; 1088 uint32_t eoverrun; 1089 uint32_t good_crc32; 1090 uint32_t fa; 1091 uint32_t bad_fina_sync; 1092 uint32_t sfd_timeout; 1093 uint32_t fina_timeout; 1094 uint32_t no_rts_ack; 1095 uint32_t rxe_limit; 1096 uint32_t ack; 1097 uint32_t cts; 1098 uint32_t ba_resp; 1099 uint32_t dsp_kill; 1100 uint32_t bad_mh; 1101 uint32_t rssi_sum; 1102 uint32_t reserved; 1103 } __packed; 1104 1105 struct iwn_rx_general_stats { 1106 uint32_t bad_cts; 1107 uint32_t bad_ack; 1108 uint32_t not_bss; 1109 uint32_t filtered; 1110 uint32_t bad_chan; 1111 uint32_t beacons; 1112 uint32_t missed_beacons; 1113 uint32_t adc_saturated; /* time in 0.8us */ 1114 uint32_t ina_searched; /* time in 0.8us */ 1115 uint32_t noise[3]; 1116 uint32_t flags; 1117 uint32_t load; 1118 uint32_t fa; 1119 uint32_t rssi[3]; 1120 uint32_t energy[3]; 1121 } __packed; 1122 1123 struct iwn_rx_ht_phy_stats { 1124 uint32_t bad_plcp; 1125 uint32_t overrun; 1126 uint32_t eoverrun; 1127 uint32_t good_crc32; 1128 uint32_t bad_crc32; 1129 uint32_t bad_mh; 1130 uint32_t good_ampdu_crc32; 1131 uint32_t ampdu; 1132 uint32_t fragment; 1133 uint32_t reserved; 1134 } __packed; 1135 1136 struct iwn_rx_stats { 1137 struct iwn_rx_phy_stats ofdm; 1138 struct iwn_rx_phy_stats cck; 1139 struct iwn_rx_general_stats general; 1140 struct iwn_rx_ht_phy_stats ht; 1141 } __packed; 1142 1143 struct iwn_tx_stats { 1144 uint32_t preamble; 1145 uint32_t rx_detected; 1146 uint32_t bt_defer; 1147 uint32_t bt_kill; 1148 uint32_t short_len; 1149 uint32_t cts_timeout; 1150 uint32_t ack_timeout; 1151 uint32_t exp_ack; 1152 uint32_t ack; 1153 uint32_t msdu; 1154 uint32_t busrt_err1; 1155 uint32_t burst_err2; 1156 uint32_t cts_collision; 1157 uint32_t ack_collision; 1158 uint32_t ba_timeout; 1159 uint32_t ba_resched; 1160 uint32_t query_ampdu; 1161 uint32_t query; 1162 uint32_t query_ampdu_frag; 1163 uint32_t query_mismatch; 1164 uint32_t not_ready; 1165 uint32_t underrun; 1166 uint32_t bt_ht_kill; 1167 uint32_t rx_ba_resp; 1168 uint32_t reserved[2]; 1169 } __packed; 1170 1171 struct iwn_general_stats { 1172 uint32_t temp; 1173 uint32_t temp_m; 1174 uint32_t burst_check; 1175 uint32_t burst; 1176 uint32_t reserved1[4]; 1177 uint32_t sleep; 1178 uint32_t slot_out; 1179 uint32_t slot_idle; 1180 uint32_t ttl_tstamp; 1181 uint32_t tx_ant_a; 1182 uint32_t tx_ant_b; 1183 uint32_t exec; 1184 uint32_t probe; 1185 uint32_t reserved2[2]; 1186 uint32_t rx_enabled; 1187 uint32_t reserved3[3]; 1188 } __packed; 1189 1190 struct iwn_stats { 1191 uint32_t flags; 1192 struct iwn_rx_stats rx; 1193 struct iwn_tx_stats tx; 1194 struct iwn_general_stats general; 1195 } __packed; 1196 1197 1198 /* Firmware error dump. */ 1199 struct iwn_fw_dump { 1200 uint32_t valid; 1201 uint32_t id; 1202 uint32_t pc; 1203 uint32_t branch_link[2]; 1204 uint32_t interrupt_link[2]; 1205 uint32_t error_data[2]; 1206 uint32_t src_line; 1207 uint32_t tsf; 1208 uint32_t time[2]; 1209 } __packed; 1210 1211 /* Firmware image file header. */ 1212 struct iwn_firmware_hdr { 1213 uint32_t version; 1214 uint32_t main_textsz; 1215 uint32_t main_datasz; 1216 uint32_t init_textsz; 1217 uint32_t init_datasz; 1218 uint32_t boot_textsz; 1219 } __packed; 1220 1221 #define IWN4965_FW_TEXT_MAXSZ ( 96 * 1024) 1222 #define IWN4965_FW_DATA_MAXSZ ( 40 * 1024) 1223 #define IWN5000_FW_TEXT_MAXSZ (256 * 1024) 1224 #define IWN5000_FW_DATA_MAXSZ ( 80 * 1024) 1225 #define IWN_FW_BOOT_TEXT_MAXSZ 1024 1226 #define IWN4965_FWSZ (IWN4965_FW_TEXT_MAXSZ + IWN4965_FW_DATA_MAXSZ) 1227 #define IWN5000_FWSZ IWN5000_FW_TEXT_MAXSZ 1228 1229 /* 1230 * Offsets into EEPROM. 1231 */ 1232 #define IWN_EEPROM_MAC 0x015 1233 #define IWN_EEPROM_RFCFG 0x048 1234 #define IWN4965_EEPROM_DOMAIN 0x060 1235 #define IWN4965_EEPROM_BAND1 0x063 1236 #define IWN5000_EEPROM_REG 0x066 1237 #define IWN5000_EEPROM_CAL 0x067 1238 #define IWN4965_EEPROM_BAND2 0x072 1239 #define IWN4965_EEPROM_BAND3 0x080 1240 #define IWN4965_EEPROM_BAND4 0x08d 1241 #define IWN4965_EEPROM_BAND5 0x099 1242 #define IWN4965_EEPROM_BAND6 0x0a0 1243 #define IWN4965_EEPROM_BAND7 0x0a8 1244 #define IWN4965_EEPROM_MAXPOW 0x0e8 1245 #define IWN4965_EEPROM_VOLTAGE 0x0e9 1246 #define IWN4965_EEPROM_BANDS 0x0ea 1247 /* Indirect offsets. */ 1248 #define IWN5000_EEPROM_DOMAIN 0x001 1249 #define IWN5000_EEPROM_BAND1 0x004 1250 #define IWN5000_EEPROM_BAND2 0x013 1251 #define IWN5000_EEPROM_BAND3 0x021 1252 #define IWN5000_EEPROM_BAND4 0x02e 1253 #define IWN5000_EEPROM_BAND5 0x03a 1254 #define IWN5000_EEPROM_BAND6 0x041 1255 #define IWN5000_EEPROM_BAND7 0x049 1256 #define IWN5000_EEPROM_CRYSTAL 0x128 1257 #define IWN5000_EEPROM_TEMP 0x12a 1258 #define IWN5000_EEPROM_VOLT 0x12b 1259 1260 /* Possible flags for IWN_EEPROM_RFCFG. */ 1261 #define IWN_RFCFG_TYPE(x) (((x) >> 0) & 0x3) 1262 #define IWN_RFCFG_STEP(x) (((x) >> 2) & 0x3) 1263 #define IWN_RFCFG_DASH(x) (((x) >> 4) & 0x3) 1264 #define IWN_RFCFG_TXANTMSK(x) (((x) >> 8) & 0xf) 1265 #define IWN_RFCFG_RXANTMSK(x) (((x) >> 12) & 0xf) 1266 1267 struct iwn_eeprom_chan { 1268 uint8_t flags; 1269 #define IWN_EEPROM_CHAN_VALID (1 << 0) 1270 #define IWN_EEPROM_CHAN_IBSS (1 << 1) 1271 #define IWN_EEPROM_CHAN_ACTIVE (1 << 3) 1272 #define IWN_EEPROM_CHAN_RADAR (1 << 4) 1273 #define IWN_EEPROM_CHAN_WIDE (1 << 5) /* HT40 */ 1274 #define IWN_EEPROM_CHAN_NARROW (1 << 6) /* HT20 */ 1275 1276 int8_t maxpwr; 1277 } __packed; 1278 1279 #define IWN_NSAMPLES 3 1280 struct iwn4965_eeprom_chan_samples { 1281 uint8_t num; 1282 struct { 1283 uint8_t temp; 1284 uint8_t gain; 1285 uint8_t power; 1286 int8_t pa_det; 1287 } samples[2][IWN_NSAMPLES]; 1288 } __packed; 1289 1290 #define IWN_NBANDS 8 1291 struct iwn4965_eeprom_band { 1292 uint8_t lo; /* low channel number */ 1293 uint8_t hi; /* high channel number */ 1294 struct iwn4965_eeprom_chan_samples chans[2]; 1295 } __packed; 1296 1297 /* 1298 * Offsets of channels descriptions in EEPROM. 1299 */ 1300 static const uint32_t iwn4965_regulatory_bands[IWN_NBANDS] = { 1301 IWN4965_EEPROM_BAND1, 1302 IWN4965_EEPROM_BAND2, 1303 IWN4965_EEPROM_BAND3, 1304 IWN4965_EEPROM_BAND4, 1305 IWN4965_EEPROM_BAND5, 1306 IWN4965_EEPROM_BAND6, 1307 IWN4965_EEPROM_BAND7 1308 }; 1309 1310 static const uint32_t iwn5000_regulatory_bands[IWN_NBANDS] = { 1311 IWN5000_EEPROM_BAND1, 1312 IWN5000_EEPROM_BAND2, 1313 IWN5000_EEPROM_BAND3, 1314 IWN5000_EEPROM_BAND4, 1315 IWN5000_EEPROM_BAND5, 1316 IWN5000_EEPROM_BAND6, 1317 IWN5000_EEPROM_BAND7 1318 }; 1319 1320 #define IWN_CHAN_BANDS_COUNT 7 1321 #define IWN_MAX_CHAN_PER_BAND 14 1322 static const struct iwn_chan_band { 1323 uint8_t nchan; 1324 uint8_t chan[IWN_MAX_CHAN_PER_BAND]; 1325 } iwn_bands[] = { 1326 /* 20MHz channels, 2GHz band. */ 1327 { 14, { 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14 } }, 1328 /* 20MHz channels, 5GHz band. */ 1329 { 13, { 183, 184, 185, 187, 188, 189, 192, 196, 7, 8, 11, 12, 16 } }, 1330 { 12, { 34, 36, 38, 40, 42, 44, 46, 48, 52, 56, 60, 64 } }, 1331 { 11, { 100, 104, 108, 112, 116, 120, 124, 128, 132, 136, 140 } }, 1332 { 6, { 145, 149, 153, 157, 161, 165 } }, 1333 /* 40MHz channels (primary channels), 2GHz band. */ 1334 { 7, { 1, 2, 3, 4, 5, 6, 7 } }, 1335 /* 40MHz channels (primary channels), 5GHz band. */ 1336 { 11, { 36, 44, 52, 60, 100, 108, 116, 124, 132, 149, 157 } } 1337 }; 1338 1339 #define IWN_RIDX_MCS 0x08 /* or'd to indicate MCS */ 1340 1341 /* HW rate indices. */ 1342 #define IWN_RIDX_CCK1 0 1343 #define IWN_RIDX_CCK11 3 1344 #define IWN_RIDX_OFDM6 4 1345 #define IWN_RIDX_OFDM54 11 1346 1347 static const struct iwn_rate { 1348 uint8_t rate; 1349 uint8_t plcp; 1350 uint8_t flags; 1351 } iwn_rates[IWN_RIDX_MAX + 1] = { 1352 { 2, 10, IWN_RFLAG_CCK }, 1353 { 4, 20, IWN_RFLAG_CCK }, 1354 { 11, 55, IWN_RFLAG_CCK }, 1355 { 22, 110, IWN_RFLAG_CCK }, 1356 { 12, 0xd, 0 }, 1357 { 18, 0xf, 0 }, 1358 { 24, 0x5, 0 }, 1359 { 36, 0x7, 0 }, 1360 { 48, 0x9, 0 }, 1361 { 72, 0xb, 0 }, 1362 { 96, 0x1, 0 }, 1363 { 108, 0x3, 0 }, 1364 { 120, 0x3, 0 } 1365 }; 1366 1367 #define IWN4965_MAX_PWR_INDEX 107 1368 1369 /* 1370 * RF Tx gain values from highest to lowest power (values obtained from 1371 * the reference driver.) 1372 */ 1373 static const uint8_t iwn4965_rf_gain_2ghz[IWN4965_MAX_PWR_INDEX + 1] = { 1374 0x3f, 0x3f, 0x3f, 0x3e, 0x3e, 0x3e, 0x3d, 0x3d, 0x3d, 0x3c, 0x3c, 1375 0x3c, 0x3b, 0x3b, 0x3b, 0x3a, 0x3a, 0x3a, 0x39, 0x39, 0x39, 0x38, 1376 0x38, 0x38, 0x37, 0x37, 0x37, 0x36, 0x36, 0x36, 0x35, 0x35, 0x35, 1377 0x34, 0x34, 0x34, 0x33, 0x33, 0x33, 0x32, 0x32, 0x32, 0x31, 0x31, 1378 0x31, 0x30, 0x30, 0x30, 0x06, 0x06, 0x06, 0x05, 0x05, 0x05, 0x04, 1379 0x04, 0x04, 0x03, 0x03, 0x03, 0x02, 0x02, 0x02, 0x01, 0x01, 0x01, 1380 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 1381 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 1382 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 1383 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 1384 }; 1385 1386 static const uint8_t iwn4965_rf_gain_5ghz[IWN4965_MAX_PWR_INDEX + 1] = { 1387 0x3f, 0x3f, 0x3f, 0x3f, 0x3f, 0x3e, 0x3e, 0x3e, 0x3d, 0x3d, 0x3d, 1388 0x3c, 0x3c, 0x3c, 0x3b, 0x3b, 0x3b, 0x3a, 0x3a, 0x3a, 0x39, 0x39, 1389 0x39, 0x38, 0x38, 0x38, 0x37, 0x37, 0x37, 0x36, 0x36, 0x36, 0x35, 1390 0x35, 0x35, 0x34, 0x34, 0x34, 0x33, 0x33, 0x33, 0x32, 0x32, 0x32, 1391 0x31, 0x31, 0x31, 0x30, 0x30, 0x30, 0x25, 0x25, 0x25, 0x24, 0x24, 1392 0x24, 0x23, 0x23, 0x23, 0x22, 0x18, 0x18, 0x17, 0x17, 0x17, 0x16, 1393 0x16, 0x16, 0x15, 0x15, 0x15, 0x14, 0x14, 0x14, 0x13, 0x13, 0x13, 1394 0x12, 0x08, 0x08, 0x07, 0x07, 0x07, 0x06, 0x06, 0x06, 0x05, 0x05, 1395 0x05, 0x04, 0x04, 0x04, 0x03, 0x03, 0x03, 0x02, 0x02, 0x02, 0x01, 1396 0x01, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 1397 }; 1398 1399 /* 1400 * DSP pre-DAC gain values from highest to lowest power (values obtained 1401 * from the reference driver.) 1402 */ 1403 static const uint8_t iwn4965_dsp_gain_2ghz[IWN4965_MAX_PWR_INDEX + 1] = { 1404 0x6e, 0x68, 0x62, 0x6e, 0x68, 0x62, 0x6e, 0x68, 0x62, 0x6e, 0x68, 1405 0x62, 0x6e, 0x68, 0x62, 0x6e, 0x68, 0x62, 0x6e, 0x68, 0x62, 0x6e, 1406 0x68, 0x62, 0x6e, 0x68, 0x62, 0x6e, 0x68, 0x62, 0x6e, 0x68, 0x62, 1407 0x6e, 0x68, 0x62, 0x6e, 0x68, 0x62, 0x6e, 0x68, 0x62, 0x6e, 0x68, 1408 0x62, 0x6e, 0x68, 0x62, 0x6e, 0x68, 0x62, 0x6e, 0x68, 0x62, 0x6e, 1409 0x68, 0x62, 0x6e, 0x68, 0x62, 0x6e, 0x68, 0x62, 0x6e, 0x68, 0x62, 1410 0x6e, 0x68, 0x62, 0x61, 0x60, 0x5f, 0x5e, 0x5d, 0x5c, 0x5b, 0x5a, 1411 0x59, 0x58, 0x57, 0x56, 0x55, 0x54, 0x53, 0x52, 0x51, 0x50, 0x4f, 1412 0x4e, 0x4d, 0x4c, 0x4b, 0x4a, 0x49, 0x48, 0x47, 0x46, 0x45, 0x44, 1413 0x43, 0x42, 0x41, 0x40, 0x3f, 0x3e, 0x3d, 0x3c, 0x3b 1414 }; 1415 1416 static const uint8_t iwn4965_dsp_gain_5ghz[IWN4965_MAX_PWR_INDEX + 1] = { 1417 0x7b, 0x75, 0x6e, 0x68, 0x62, 0x6e, 0x68, 0x62, 0x6e, 0x68, 0x62, 1418 0x6e, 0x68, 0x62, 0x6e, 0x68, 0x62, 0x6e, 0x68, 0x62, 0x6e, 0x68, 1419 0x62, 0x6e, 0x68, 0x62, 0x6e, 0x68, 0x62, 0x6e, 0x68, 0x62, 0x6e, 1420 0x68, 0x62, 0x6e, 0x68, 0x62, 0x6e, 0x68, 0x62, 0x6e, 0x68, 0x62, 1421 0x6e, 0x68, 0x62, 0x6e, 0x68, 0x62, 0x6e, 0x68, 0x62, 0x6e, 0x68, 1422 0x62, 0x6e, 0x68, 0x62, 0x6e, 0x68, 0x62, 0x6e, 0x68, 0x62, 0x6e, 1423 0x68, 0x62, 0x6e, 0x68, 0x62, 0x6e, 0x68, 0x62, 0x6e, 0x68, 0x62, 1424 0x6e, 0x68, 0x62, 0x6e, 0x68, 0x62, 0x6e, 0x68, 0x62, 0x6e, 0x68, 1425 0x62, 0x6e, 0x68, 0x62, 0x6e, 0x68, 0x62, 0x6e, 0x68, 0x62, 0x6e, 1426 0x68, 0x62, 0x6e, 0x68, 0x62, 0x5d, 0x58, 0x53, 0x4e 1427 }; 1428 1429 /* 1430 * Power saving settings (values obtained from the reference driver.) 1431 */ 1432 #define IWN_NDTIMRANGES 3 1433 #define IWN_NPOWERLEVELS 6 1434 static const struct iwn_pmgt { 1435 uint32_t rxtimeout; 1436 uint32_t txtimeout; 1437 uint32_t intval[5]; 1438 int skip_dtim; 1439 } iwn_pmgt[IWN_NDTIMRANGES][IWN_NPOWERLEVELS] = { 1440 /* DTIM <= 2 */ 1441 { 1442 { 0, 0, { 0, 0, 0, 0, 0 }, 0 }, /* CAM */ 1443 { 200, 500, { 1, 2, 2, 2, -1 }, 0 }, /* PS level 1 */ 1444 { 200, 300, { 1, 2, 2, 2, -1 }, 0 }, /* PS level 2 */ 1445 { 50, 100, { 2, 2, 2, 2, -1 }, 0 }, /* PS level 3 */ 1446 { 50, 25, { 2, 2, 4, 4, -1 }, 1 }, /* PS level 4 */ 1447 { 25, 25, { 2, 2, 4, 6, -1 }, 2 } /* PS level 5 */ 1448 }, 1449 /* 3 <= DTIM <= 10 */ 1450 { 1451 { 0, 0, { 0, 0, 0, 0, 0 }, 0 }, /* CAM */ 1452 { 200, 500, { 1, 2, 3, 4, 4 }, 0 }, /* PS level 1 */ 1453 { 200, 300, { 1, 2, 3, 4, 7 }, 0 }, /* PS level 2 */ 1454 { 50, 100, { 2, 4, 6, 7, 9 }, 0 }, /* PS level 3 */ 1455 { 50, 25, { 2, 4, 6, 9, 10 }, 1 }, /* PS level 4 */ 1456 { 25, 25, { 2, 4, 7, 10, 10 }, 2 } /* PS level 5 */ 1457 }, 1458 /* DTIM >= 11 */ 1459 { 1460 { 0, 0, { 0, 0, 0, 0, 0 }, 0 }, /* CAM */ 1461 { 200, 500, { 1, 2, 3, 4, -1 }, 0 }, /* PS level 1 */ 1462 { 200, 300, { 2, 4, 6, 7, -1 }, 0 }, /* PS level 2 */ 1463 { 50, 100, { 2, 7, 9, 9, -1 }, 0 }, /* PS level 3 */ 1464 { 50, 25, { 2, 7, 9, 9, -1 }, 0 }, /* PS level 4 */ 1465 { 25, 25, { 4, 7, 10, 10, -1 }, 0 } /* PS level 5 */ 1466 } 1467 }; 1468 1469 struct iwn_sensitivity_limits { 1470 uint32_t min_ofdm_x1; 1471 uint32_t max_ofdm_x1; 1472 uint32_t min_ofdm_mrc_x1; 1473 uint32_t max_ofdm_mrc_x1; 1474 uint32_t min_ofdm_x4; 1475 uint32_t max_ofdm_x4; 1476 uint32_t min_ofdm_mrc_x4; 1477 uint32_t max_ofdm_mrc_x4; 1478 uint32_t min_cck_x4; 1479 uint32_t max_cck_x4; 1480 uint32_t min_cck_mrc_x4; 1481 uint32_t max_cck_mrc_x4; 1482 uint32_t min_energy_cck; 1483 uint32_t energy_cck; 1484 uint32_t energy_ofdm; 1485 }; 1486 1487 /* 1488 * RX sensitivity limits (values obtained from the reference driver.) 1489 */ 1490 static const struct iwn_sensitivity_limits iwn4965_sensitivity_limits = { 1491 105, 140, 1492 170, 210, 1493 85, 120, 1494 170, 210, 1495 125, 200, 1496 200, 400, 1497 97, 1498 100, 1499 100 1500 }; 1501 1502 static const struct iwn_sensitivity_limits iwn5000_sensitivity_limits = { 1503 120, 155, 1504 240, 290, 1505 90, 120, 1506 170, 210, 1507 125, 200, 1508 170, 400, 1509 95, 1510 95, 1511 95 1512 }; 1513 1514 /* Map TID to TX scheduler's FIFO. */ 1515 static const uint8_t iwn_tid2fifo[] = { 1516 1, 0, 0, 1, 2, 2, 3, 3, 7, 7, 7, 7, 7, 7, 7, 7, 3 1517 }; 1518 1519 /* Firmware errors. */ 1520 static const char * const iwn_fw_errmsg[] = { 1521 "OK", 1522 "FAIL", 1523 "BAD_PARAM", 1524 "BAD_CHECKSUM", 1525 "NMI_INTERRUPT_WDG", 1526 "SYSASSERT", 1527 "FATAL_ERROR", 1528 "BAD_COMMAND", 1529 "HW_ERROR_TUNE_LOCK", 1530 "HW_ERROR_TEMPERATURE", 1531 "ILLEGAL_CHAN_FREQ", 1532 "VCC_NOT_STABLE", 1533 "FH_ERROR", 1534 "NMI_INTERRUPT_HOST", 1535 "NMI_INTERRUPT_ACTION_PT", 1536 "NMI_INTERRUPT_UNKNOWN", 1537 "UCODE_VERSION_MISMATCH", 1538 "HW_ERROR_ABS_LOCK", 1539 "HW_ERROR_CAL_LOCK_FAIL", 1540 "NMI_INTERRUPT_INST_ACTION_PT", 1541 "NMI_INTERRUPT_DATA_ACTION_PT", 1542 "NMI_TRM_HW_ER", 1543 "NMI_INTERRUPT_TRM", 1544 "NMI_INTERRUPT_BREAKPOINT" 1545 "DEBUG_0", 1546 "DEBUG_1", 1547 "DEBUG_2", 1548 "DEBUG_3", 1549 "UNKNOWN" 1550 }; 1551 1552 /* Find least significant bit that is set. */ 1553 #define IWN_LSB(x) ((((x) - 1) & (x)) ^ (x)) 1554 1555 #define IWN_READ(sc, reg) \ 1556 bus_space_read_4((sc)->sc_st, (sc)->sc_sh, (reg)) 1557 1558 #define IWN_WRITE(sc, reg, val) \ 1559 bus_space_write_4((sc)->sc_st, (sc)->sc_sh, (reg), (val)) 1560 1561 #define IWN_SETBITS(sc, reg, mask) \ 1562 IWN_WRITE(sc, reg, IWN_READ(sc, reg) | (mask)) 1563 1564 #define IWN_CLRBITS(sc, reg, mask) \ 1565 IWN_WRITE(sc, reg, IWN_READ(sc, reg) & ~(mask)) 1566