1 /* $FreeBSD$ */ 2 /* $OpenBSD: if_iwnreg.h,v 1.40 2010/05/05 19:41:57 damien Exp $ */ 3 4 /*- 5 * Copyright (c) 2007, 2008 6 * Damien Bergamini <damien.bergamini@free.fr> 7 * 8 * Permission to use, copy, modify, and distribute this software for any 9 * purpose with or without fee is hereby granted, provided that the above 10 * copyright notice and this permission notice appear in all copies. 11 * 12 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 13 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 14 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR 15 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 16 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN 17 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF 18 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 19 */ 20 #ifndef __IF_IWNREG_H__ 21 #define __IF_IWNREG_H__ 22 23 #define IWN_CT_KILL_THRESHOLD 114 /* in Celsius */ 24 #define IWN_CT_KILL_EXIT_THRESHOLD 95 /* in Celsius */ 25 26 #define IWN_TX_RING_COUNT 256 27 #define IWN_TX_RING_LOMARK 192 28 #define IWN_TX_RING_HIMARK 224 29 #define IWN_RX_RING_COUNT_LOG 6 30 #define IWN_RX_RING_COUNT (1 << IWN_RX_RING_COUNT_LOG) 31 32 #define IWN4965_NTXQUEUES 16 33 #define IWN5000_NTXQUEUES 20 34 35 #define IWN4965_FIRSTAGGQUEUE 7 36 #define IWN5000_FIRSTAGGQUEUE 10 37 38 #define IWN4965_NDMACHNLS 7 39 #define IWN5000_NDMACHNLS 8 40 41 #define IWN_SRVC_DMACHNL 9 42 43 #define IWN_ICT_SIZE 4096 44 #define IWN_ICT_COUNT (IWN_ICT_SIZE / sizeof (uint32_t)) 45 46 /* For cards with PAN command, default is IWN_CMD_QUEUE_NUM */ 47 #define IWN_CMD_QUEUE_NUM 4 48 #define IWN_PAN_CMD_QUEUE 9 49 50 /* Maximum number of DMA segments for TX. */ 51 #define IWN_MAX_SCATTER 20 52 53 /* RX buffers must be large enough to hold a full 4K A-MPDU. */ 54 #define IWN_RBUF_SIZE (4 * 1024) 55 56 #if defined(__LP64__) 57 /* HW supports 36-bit DMA addresses. */ 58 #define IWN_LOADDR(paddr) ((uint32_t)(paddr)) 59 #define IWN_HIADDR(paddr) (((paddr) >> 32) & 0xf) 60 #else 61 #define IWN_LOADDR(paddr) (paddr) 62 #define IWN_HIADDR(paddr) (0) 63 #endif 64 65 /* 66 * Control and status registers. 67 */ 68 #define IWN_HW_IF_CONFIG 0x000 69 #define IWN_INT_COALESCING 0x004 70 #define IWN_INT_PERIODIC 0x005 /* use IWN_WRITE_1 */ 71 #define IWN_INT 0x008 72 #define IWN_INT_MASK 0x00c 73 #define IWN_FH_INT 0x010 74 #define IWN_GPIO_IN 0x018 /* read external chip pins */ 75 #define IWN_RESET 0x020 76 #define IWN_GP_CNTRL 0x024 77 #define IWN_HW_REV 0x028 78 #define IWN_EEPROM 0x02c 79 #define IWN_EEPROM_GP 0x030 80 #define IWN_OTP_GP 0x034 81 #define IWN_GIO 0x03c 82 #define IWN_GP_UCODE 0x048 83 #define IWN_GP_DRIVER 0x050 84 #define IWN_UCODE_GP1 0x054 85 #define IWN_UCODE_GP1_SET 0x058 86 #define IWN_UCODE_GP1_CLR 0x05c 87 #define IWN_UCODE_GP2 0x060 88 #define IWN_LED 0x094 89 #define IWN_DRAM_INT_TBL 0x0a0 90 #define IWN_SHADOW_REG_CTRL 0x0a8 91 #define IWN_GIO_CHICKEN 0x100 92 #define IWN_ANA_PLL 0x20c 93 #define IWN_HW_REV_WA 0x22c 94 #define IWN_DBG_HPET_MEM 0x240 95 #define IWN_DBG_LINK_PWR_MGMT 0x250 96 /* Need nic_lock for use above */ 97 #define IWN_MEM_RADDR 0x40c 98 #define IWN_MEM_WADDR 0x410 99 #define IWN_MEM_WDATA 0x418 100 #define IWN_MEM_RDATA 0x41c 101 #define IWN_TARG_MBX_C 0x430 102 #define IWN_PRPH_WADDR 0x444 103 #define IWN_PRPH_RADDR 0x448 104 #define IWN_PRPH_WDATA 0x44c 105 #define IWN_PRPH_RDATA 0x450 106 #define IWN_HBUS_TARG_WRPTR 0x460 107 108 /* 109 * Flow-Handler registers. 110 */ 111 #define IWN_FH_TFBD_CTRL0(qid) (0x1900 + (qid) * 8) 112 #define IWN_FH_TFBD_CTRL1(qid) (0x1904 + (qid) * 8) 113 #define IWN_FH_KW_ADDR 0x197c 114 #define IWN_FH_SRAM_ADDR(qid) (0x19a4 + (qid) * 4) 115 #define IWN_FH_CBBC_QUEUE(qid) (0x19d0 + (qid) * 4) 116 #define IWN_FH_STATUS_WPTR 0x1bc0 117 #define IWN_FH_RX_BASE 0x1bc4 118 #define IWN_FH_RX_WPTR 0x1bc8 119 #define IWN_FH_RX_CONFIG 0x1c00 120 #define IWN_FH_RX_STATUS 0x1c44 121 #define IWN_FH_TX_CONFIG(qid) (0x1d00 + (qid) * 32) 122 #define IWN_FH_TXBUF_STATUS(qid) (0x1d08 + (qid) * 32) 123 #define IWN_FH_TX_CHICKEN 0x1e98 124 #define IWN_FH_TX_STATUS 0x1eb0 125 126 /* 127 * TX scheduler registers. 128 */ 129 #define IWN_SCHED_BASE 0xa02c00 130 #define IWN_SCHED_SRAM_ADDR (IWN_SCHED_BASE + 0x000) 131 #define IWN5000_SCHED_DRAM_ADDR (IWN_SCHED_BASE + 0x008) 132 #define IWN4965_SCHED_DRAM_ADDR (IWN_SCHED_BASE + 0x010) 133 #define IWN5000_SCHED_TXFACT (IWN_SCHED_BASE + 0x010) 134 #define IWN4965_SCHED_TXFACT (IWN_SCHED_BASE + 0x01c) 135 #define IWN4965_SCHED_QUEUE_RDPTR(qid) (IWN_SCHED_BASE + 0x064 + (qid) * 4) 136 #define IWN5000_SCHED_QUEUE_RDPTR(qid) (IWN_SCHED_BASE + 0x068 + (qid) * 4) 137 #define IWN4965_SCHED_QCHAIN_SEL (IWN_SCHED_BASE + 0x0d0) 138 #define IWN4965_SCHED_INTR_MASK (IWN_SCHED_BASE + 0x0e4) 139 #define IWN5000_SCHED_QCHAIN_SEL (IWN_SCHED_BASE + 0x0e8) 140 #define IWN4965_SCHED_QUEUE_STATUS(qid) (IWN_SCHED_BASE + 0x104 + (qid) * 4) 141 #define IWN5000_SCHED_INTR_MASK (IWN_SCHED_BASE + 0x108) 142 #define IWN5000_SCHED_QUEUE_STATUS(qid) (IWN_SCHED_BASE + 0x10c + (qid) * 4) 143 #define IWN5000_SCHED_AGGR_SEL (IWN_SCHED_BASE + 0x248) 144 145 /* 146 * Offsets in TX scheduler's SRAM. 147 */ 148 #define IWN4965_SCHED_CTX_OFF 0x380 149 #define IWN4965_SCHED_CTX_LEN 416 150 #define IWN4965_SCHED_QUEUE_OFFSET(qid) (0x380 + (qid) * 8) 151 #define IWN4965_SCHED_TRANS_TBL(qid) (0x500 + (qid) * 2) 152 #define IWN5000_SCHED_CTX_OFF 0x600 153 #define IWN5000_SCHED_CTX_LEN 520 154 #define IWN5000_SCHED_QUEUE_OFFSET(qid) (0x600 + (qid) * 8) 155 #define IWN5000_SCHED_TRANS_TBL(qid) (0x7e0 + (qid) * 2) 156 157 /* 158 * NIC internal memory offsets. 159 */ 160 #define IWN_APMG_CLK_CTRL 0x3000 161 #define IWN_APMG_CLK_EN 0x3004 162 #define IWN_APMG_CLK_DIS 0x3008 163 #define IWN_APMG_PS 0x300c 164 #define IWN_APMG_DIGITAL_SVR 0x3058 165 #define IWN_APMG_ANALOG_SVR 0x306c 166 #define IWN_APMG_PCI_STT 0x3010 167 #define IWN_BSM_WR_CTRL 0x3400 168 #define IWN_BSM_WR_MEM_SRC 0x3404 169 #define IWN_BSM_WR_MEM_DST 0x3408 170 #define IWN_BSM_WR_DWCOUNT 0x340c 171 #define IWN_BSM_DRAM_TEXT_ADDR 0x3490 172 #define IWN_BSM_DRAM_TEXT_SIZE 0x3494 173 #define IWN_BSM_DRAM_DATA_ADDR 0x3498 174 #define IWN_BSM_DRAM_DATA_SIZE 0x349c 175 #define IWN_BSM_SRAM_BASE 0x3800 176 177 /* Possible flags for register IWN_HW_IF_CONFIG. */ 178 #define IWN_HW_IF_CONFIG_4965_R (1 << 4) 179 #define IWN_HW_IF_CONFIG_MAC_SI (1 << 8) 180 #define IWN_HW_IF_CONFIG_RADIO_SI (1 << 9) 181 #define IWN_HW_IF_CONFIG_EEPROM_LOCKED (1 << 21) 182 #define IWN_HW_IF_CONFIG_NIC_READY (1 << 22) 183 #define IWN_HW_IF_CONFIG_HAP_WAKE_L1A (1 << 23) 184 #define IWN_HW_IF_CONFIG_PREPARE_DONE (1 << 25) 185 #define IWN_HW_IF_CONFIG_PREPARE (1 << 27) 186 187 /* Possible values for register IWN_INT_PERIODIC. */ 188 #define IWN_INT_PERIODIC_DIS 0x00 189 #define IWN_INT_PERIODIC_ENA 0xff 190 191 /* Possible flags for registers IWN_PRPH_RADDR/IWN_PRPH_WADDR. */ 192 #define IWN_PRPH_DWORD ((sizeof (uint32_t) - 1) << 24) 193 194 /* Possible values for IWN_BSM_WR_MEM_DST. */ 195 #define IWN_FW_TEXT_BASE 0x00000000 196 #define IWN_FW_DATA_BASE 0x00800000 197 198 /* Possible flags for register IWN_RESET. */ 199 #define IWN_RESET_NEVO (1 << 0) 200 #define IWN_RESET_SW (1 << 7) 201 #define IWN_RESET_MASTER_DISABLED (1 << 8) 202 #define IWN_RESET_STOP_MASTER (1 << 9) 203 #define IWN_RESET_LINK_PWR_MGMT_DIS (1U << 31) 204 205 /* Possible flags for register IWN_GP_CNTRL. */ 206 #define IWN_GP_CNTRL_MAC_ACCESS_ENA (1 << 0) 207 #define IWN_GP_CNTRL_MAC_CLOCK_READY (1 << 0) 208 #define IWN_GP_CNTRL_INIT_DONE (1 << 2) 209 #define IWN_GP_CNTRL_MAC_ACCESS_REQ (1 << 3) 210 #define IWN_GP_CNTRL_SLEEP (1 << 4) 211 #define IWN_GP_CNTRL_RFKILL (1 << 27) 212 213 /* Possible flags for register IWN_GIO_CHICKEN. */ 214 #define IWN_GIO_CHICKEN_L1A_NO_L0S_RX (1 << 23) 215 #define IWN_GIO_CHICKEN_DIS_L0S_TIMER (1 << 29) 216 217 /* Possible flags for register IWN_GIO. */ 218 #define IWN_GIO_L0S_ENA (1 << 1) 219 220 /* Possible flags for register IWN_GP_DRIVER. */ 221 #define IWN_GP_DRIVER_RADIO_3X3_HYB (0 << 0) 222 #define IWN_GP_DRIVER_RADIO_2X2_HYB (1 << 0) 223 #define IWN_GP_DRIVER_RADIO_2X2_IPA (2 << 0) 224 #define IWN_GP_DRIVER_CALIB_VER6 (1 << 2) 225 #define IWN_GP_DRIVER_6050_1X2 (1 << 3) 226 #define IWN_GP_DRIVER_REG_BIT_RADIO_IQ_INVERT (1 << 7) 227 #define IWN_GP_DRIVER_NONE 0 228 229 /* Possible flags for register IWN_UCODE_GP1_CLR. */ 230 #define IWN_UCODE_GP1_RFKILL (1 << 1) 231 #define IWN_UCODE_GP1_CMD_BLOCKED (1 << 2) 232 #define IWN_UCODE_GP1_CTEMP_STOP_RF (1 << 3) 233 #define IWN_UCODE_GP1_CFG_COMPLETE (1 << 5) 234 235 /* Possible flags/values for register IWN_LED. */ 236 #define IWN_LED_BSM_CTRL (1 << 5) 237 #define IWN_LED_OFF 0x00000038 238 #define IWN_LED_ON 0x00000078 239 240 #define IWN_MAX_BLINK_TBL 10 241 #define IWN_LED_STATIC_ON 0 242 #define IWN_LED_STATIC_OFF 1 243 #define IWN_LED_SLOW_BLINK 2 244 #define IWN_LED_INT_BLINK 3 245 #define IWN_LED_UNIT 0x1388 /* 5 ms */ 246 247 static const struct { 248 uint16_t tpt; /* Mb/s */ 249 uint8_t on_time; 250 uint8_t off_time; 251 } blink_tbl[] = 252 { 253 {300, 5, 5}, 254 {200, 8, 8}, 255 {100, 11, 11}, 256 {70, 13, 13}, 257 {50, 15, 15}, 258 {20, 17, 17}, 259 {10, 19, 19}, 260 {5, 22, 22}, 261 {1, 26, 26}, 262 {0, 33, 33}, 263 /* SOLID_ON */ 264 }; 265 266 /* Possible flags for register IWN_DRAM_INT_TBL. */ 267 #define IWN_DRAM_INT_TBL_WRAP_CHECK (1 << 27) 268 #define IWN_DRAM_INT_TBL_ENABLE (1U << 31) 269 270 /* Possible values for register IWN_ANA_PLL. */ 271 #define IWN_ANA_PLL_INIT 0x00880300 272 273 /* Possible flags for register IWN_FH_RX_STATUS. */ 274 #define IWN_FH_RX_STATUS_IDLE (1 << 24) 275 276 /* Possible flags for register IWN_BSM_WR_CTRL. */ 277 #define IWN_BSM_WR_CTRL_START_EN (1 << 30) 278 #define IWN_BSM_WR_CTRL_START (1U << 31) 279 280 /* Possible flags for register IWN_INT. */ 281 #define IWN_INT_ALIVE (1 << 0) 282 #define IWN_INT_WAKEUP (1 << 1) 283 #define IWN_INT_SW_RX (1 << 3) 284 #define IWN_INT_CT_REACHED (1 << 6) 285 #define IWN_INT_RF_TOGGLED (1 << 7) 286 #define IWN_INT_SW_ERR (1 << 25) 287 #define IWN_INT_SCHED (1 << 26) 288 #define IWN_INT_FH_TX (1 << 27) 289 #define IWN_INT_RX_PERIODIC (1 << 28) 290 #define IWN_INT_HW_ERR (1 << 29) 291 #define IWN_INT_FH_RX (1U << 31) 292 293 /* Shortcut. */ 294 #define IWN_INT_MASK_DEF \ 295 (IWN_INT_SW_ERR | IWN_INT_HW_ERR | IWN_INT_FH_TX | \ 296 IWN_INT_FH_RX | IWN_INT_ALIVE | IWN_INT_WAKEUP | \ 297 IWN_INT_SW_RX | IWN_INT_CT_REACHED | IWN_INT_RF_TOGGLED) 298 299 /* Possible flags for register IWN_FH_INT. */ 300 #define IWN_FH_INT_TX_CHNL(x) (1 << (x)) 301 #define IWN_FH_INT_RX_CHNL(x) (1 << ((x) + 16)) 302 #define IWN_FH_INT_HI_PRIOR (1 << 30) 303 /* Shortcuts for the above. */ 304 #define IWN_FH_INT_TX \ 305 (IWN_FH_INT_TX_CHNL(0) | IWN_FH_INT_TX_CHNL(1)) 306 #define IWN_FH_INT_RX \ 307 (IWN_FH_INT_RX_CHNL(0) | IWN_FH_INT_RX_CHNL(1) | IWN_FH_INT_HI_PRIOR) 308 309 /* Possible flags/values for register IWN_FH_TX_CONFIG. */ 310 #define IWN_FH_TX_CONFIG_DMA_PAUSE 0 311 #define IWN_FH_TX_CONFIG_DMA_ENA (1U << 31) 312 #define IWN_FH_TX_CONFIG_CIRQ_HOST_ENDTFD (1 << 20) 313 314 /* Possible flags/values for register IWN_FH_TXBUF_STATUS. */ 315 #define IWN_FH_TXBUF_STATUS_TBNUM(x) ((x) << 20) 316 #define IWN_FH_TXBUF_STATUS_TBIDX(x) ((x) << 12) 317 #define IWN_FH_TXBUF_STATUS_TFBD_VALID 3 318 319 /* Possible flags for register IWN_FH_TX_CHICKEN. */ 320 #define IWN_FH_TX_CHICKEN_SCHED_RETRY (1 << 1) 321 322 /* Possible flags for register IWN_FH_TX_STATUS. */ 323 #define IWN_FH_TX_STATUS_IDLE(chnl) (1 << ((chnl) + 16)) 324 325 /* Possible flags for register IWN_FH_RX_CONFIG. */ 326 #define IWN_FH_RX_CONFIG_ENA (1U << 31) 327 #define IWN_FH_RX_CONFIG_NRBD(x) ((x) << 20) 328 #define IWN_FH_RX_CONFIG_RB_SIZE_8K (1 << 16) 329 #define IWN_FH_RX_CONFIG_SINGLE_FRAME (1 << 15) 330 #define IWN_FH_RX_CONFIG_IRQ_DST_HOST (1 << 12) 331 #define IWN_FH_RX_CONFIG_RB_TIMEOUT(x) ((x) << 4) 332 #define IWN_FH_RX_CONFIG_IGN_RXF_EMPTY (1 << 2) 333 334 /* Possible flags for register IWN_FH_TX_CONFIG. */ 335 #define IWN_FH_TX_CONFIG_DMA_ENA (1U << 31) 336 #define IWN_FH_TX_CONFIG_DMA_CREDIT_ENA (1 << 3) 337 338 /* Possible flags for register IWN_EEPROM. */ 339 #define IWN_EEPROM_READ_VALID (1 << 0) 340 #define IWN_EEPROM_CMD (1 << 1) 341 342 /* Possible flags for register IWN_EEPROM_GP. */ 343 #define IWN_EEPROM_GP_IF_OWNER 0x00000180 344 345 /* Possible flags for register IWN_OTP_GP. */ 346 #define IWN_OTP_GP_DEV_SEL_OTP (1 << 16) 347 #define IWN_OTP_GP_RELATIVE_ACCESS (1 << 17) 348 #define IWN_OTP_GP_ECC_CORR_STTS (1 << 20) 349 #define IWN_OTP_GP_ECC_UNCORR_STTS (1 << 21) 350 351 /* Possible flags for register IWN_SCHED_QUEUE_STATUS. */ 352 #define IWN4965_TXQ_STATUS_ACTIVE 0x0007fc01 353 #define IWN4965_TXQ_STATUS_INACTIVE 0x0007fc00 354 #define IWN4965_TXQ_STATUS_AGGR_ENA (1 << 5 | 1 << 8) 355 #define IWN4965_TXQ_STATUS_CHGACT (1 << 10) 356 #define IWN5000_TXQ_STATUS_ACTIVE 0x00ff0018 357 #define IWN5000_TXQ_STATUS_INACTIVE 0x00ff0010 358 #define IWN5000_TXQ_STATUS_CHGACT (1 << 19) 359 360 /* Possible flags for registers IWN_APMG_CLK_*. */ 361 #define IWN_APMG_CLK_CTRL_DMA_CLK_RQT (1 << 9) 362 #define IWN_APMG_CLK_CTRL_BSM_CLK_RQT (1 << 11) 363 364 /* Possible flags for register IWN_APMG_PS. */ 365 #define IWN_APMG_PS_EARLY_PWROFF_DIS (1 << 22) 366 #define IWN_APMG_PS_PWR_SRC(x) ((x) << 24) 367 #define IWN_APMG_PS_PWR_SRC_VMAIN 0 368 #define IWN_APMG_PS_PWR_SRC_VAUX 2 369 #define IWN_APMG_PS_PWR_SRC_MASK IWN_APMG_PS_PWR_SRC(3) 370 #define IWN_APMG_PS_RESET_REQ (1 << 26) 371 372 /* Possible flags for register IWN_APMG_DIGITAL_SVR. */ 373 #define IWN_APMG_DIGITAL_SVR_VOLTAGE(x) (((x) & 0xf) << 5) 374 #define IWN_APMG_DIGITAL_SVR_VOLTAGE_MASK \ 375 IWN_APMG_DIGITAL_SVR_VOLTAGE(0xf) 376 #define IWN_APMG_DIGITAL_SVR_VOLTAGE_1_32 \ 377 IWN_APMG_DIGITAL_SVR_VOLTAGE(3) 378 379 /* Possible flags for IWN_APMG_PCI_STT. */ 380 #define IWN_APMG_PCI_STT_L1A_DIS (1 << 11) 381 382 /* Possible flags for register IWN_BSM_DRAM_TEXT_SIZE. */ 383 #define IWN_FW_UPDATED (1U << 31) 384 385 #define IWN_SCHED_WINSZ 64 386 #define IWN_SCHED_LIMIT 64 387 #define IWN4965_SCHED_COUNT 512 388 #define IWN5000_SCHED_COUNT (IWN_TX_RING_COUNT + IWN_SCHED_WINSZ) 389 #define IWN4965_SCHEDSZ (IWN4965_NTXQUEUES * IWN4965_SCHED_COUNT * 2) 390 #define IWN5000_SCHEDSZ (IWN5000_NTXQUEUES * IWN5000_SCHED_COUNT * 2) 391 392 struct iwn_tx_desc { 393 uint8_t reserved1[3]; 394 uint8_t nsegs; 395 struct { 396 uint32_t addr; 397 uint16_t len; 398 } __packed segs[IWN_MAX_SCATTER]; 399 /* Pad to 128 bytes. */ 400 uint32_t reserved2; 401 } __packed; 402 403 struct iwn_rx_status { 404 uint16_t closed_count; 405 uint16_t closed_rx_count; 406 uint16_t finished_count; 407 uint16_t finished_rx_count; 408 uint32_t reserved[2]; 409 } __packed; 410 411 struct iwn_rx_desc { 412 /* 413 * The first 4 bytes of the RX frame header contain both the RX frame 414 * size and some flags. 415 * Bit fields: 416 * 31: flag flush RB request 417 * 30: flag ignore TC (terminal counter) request 418 * 29: flag fast IRQ request 419 * 28-14: Reserved 420 * 13-00: RX frame size 421 */ 422 uint32_t len; 423 uint8_t type; 424 #define IWN_UC_READY 1 425 #define IWN_ADD_NODE_DONE 24 426 #define IWN_TX_DONE 28 427 #define IWN_REPLY_LED_CMD 72 428 #define IWN5000_CALIBRATION_RESULT 102 429 #define IWN5000_CALIBRATION_DONE 103 430 #define IWN_START_SCAN 130 431 #define IWN_NOTIF_SCAN_RESULT 131 432 #define IWN_STOP_SCAN 132 433 #define IWN_RX_STATISTICS 156 434 #define IWN_BEACON_STATISTICS 157 435 #define IWN_STATE_CHANGED 161 436 #define IWN_BEACON_MISSED 162 437 #define IWN_RX_PHY 192 438 #define IWN_MPDU_RX_DONE 193 439 #define IWN_RX_DONE 195 440 #define IWN_RX_COMPRESSED_BA 197 441 442 uint8_t flags; /* 0:5 reserved, 6 abort, 7 internal */ 443 uint8_t idx; /* position within TX queue */ 444 uint8_t qid; 445 /* 0:4 TX queue id - 5:6 reserved - 7 unsolicited RX 446 * or uCode-originated notification 447 */ 448 } __packed; 449 450 #define IWN_RX_DESC_QID_MSK 0x1F 451 #define IWN_UNSOLICITED_RX_NOTIF 0x80 452 453 /* CARD_STATE_NOTIFICATION */ 454 #define IWN_STATE_CHANGE_HW_CARD_DISABLED 0x01 455 #define IWN_STATE_CHANGE_SW_CARD_DISABLED 0x02 456 #define IWN_STATE_CHANGE_CT_CARD_DISABLED 0x04 457 #define IWN_STATE_CHANGE_RXON_CARD_DISABLED 0x10 458 459 /* Possible RX status flags. */ 460 #define IWN_RX_NO_CRC_ERR (1 << 0) 461 #define IWN_RX_NO_OVFL_ERR (1 << 1) 462 /* Shortcut for the above. */ 463 #define IWN_RX_NOERROR (IWN_RX_NO_CRC_ERR | IWN_RX_NO_OVFL_ERR) 464 #define IWN_RX_MPDU_MIC_OK (1 << 6) 465 #define IWN_RX_CIPHER_MASK (7 << 8) 466 #define IWN_RX_CIPHER_CCMP (2 << 8) 467 #define IWN_RX_MPDU_DEC (1 << 11) 468 #define IWN_RX_DECRYPT_MASK (3 << 11) 469 #define IWN_RX_DECRYPT_OK (3 << 11) 470 471 struct iwn_tx_cmd { 472 uint8_t code; 473 #define IWN_CMD_RXON 16 474 #define IWN_CMD_RXON_ASSOC 17 475 #define IWN_CMD_EDCA_PARAMS 19 476 #define IWN_CMD_TIMING 20 477 #define IWN_CMD_ADD_NODE 24 478 #define IWN_CMD_TX_DATA 28 479 #define IWN_CMD_LINK_QUALITY 78 480 #define IWN_CMD_SET_LED 72 481 #define IWN5000_CMD_WIMAX_COEX 90 482 #define IWN_TEMP_NOTIFICATION 98 483 #define IWN5000_CMD_CALIB_CONFIG 101 484 #define IWN5000_CMD_CALIB_RESULT 102 485 #define IWN5000_CMD_CALIB_COMPLETE 103 486 #define IWN_CMD_SET_POWER_MODE 119 487 #define IWN_CMD_SCAN 128 488 #define IWN_CMD_SCAN_RESULTS 131 489 #define IWN_CMD_TXPOWER_DBM 149 490 #define IWN_CMD_TXPOWER 151 491 #define IWN5000_CMD_TX_ANT_CONFIG 152 492 #define IWN_CMD_TXPOWER_DBM_V1 152 493 #define IWN_CMD_BT_COEX 155 494 #define IWN_CMD_GET_STATISTICS 156 495 #define IWN_CMD_SET_CRITICAL_TEMP 164 496 #define IWN_CMD_SET_SENSITIVITY 168 497 #define IWN_CMD_PHY_CALIB 176 498 #define IWN_CMD_BT_COEX_PRIOTABLE 204 499 #define IWN_CMD_BT_COEX_PROT 205 500 #define IWN_CMD_BT_COEX_NOTIF 206 501 /* PAN commands */ 502 #define IWN_CMD_WIPAN_PARAMS 0xb2 503 #define IWN_CMD_WIPAN_RXON 0xb3 504 #define IWN_CMD_WIPAN_RXON_TIMING 0xb4 505 #define IWN_CMD_WIPAN_RXON_ASSOC 0xb6 506 #define IWN_CMD_WIPAN_QOS_PARAM 0xb7 507 #define IWN_CMD_WIPAN_WEPKEY 0xb8 508 #define IWN_CMD_WIPAN_P2P_CHANNEL_SWITCH 0xb9 509 #define IWN_CMD_WIPAN_NOA_NOTIFICATION 0xbc 510 #define IWN_CMD_WIPAN_DEACTIVATION_COMPLETE 0xbd 511 512 uint8_t flags; 513 uint8_t idx; 514 uint8_t qid; 515 uint8_t data[136]; 516 } __packed; 517 518 /* 519 * Structure for IWN_CMD_GET_STATISTICS = (0x9c) 156 520 * all devices identical. 521 * 522 * This command triggers an immediate response containing uCode statistics. 523 * The response is in the same format as IWN_BEACON_STATISTICS (0x9d) 157. 524 * 525 * If the CLEAR_STATS configuration flag is set, uCode will clear its 526 * internal copy of the statistics (counters) after issuing the response. 527 * This flag does not affect IWN_BEACON_STATISTICS after beacons (see below). 528 * 529 * If the DISABLE_NOTIF configuration flag is set, uCode will not issue 530 * IWN_BEACON_STATISTICS after received beacons. This flag 531 * does not affect the response to the IWN_CMD_GET_STATISTICS 0x9c itself. 532 */ 533 struct iwn_statistics_cmd { 534 uint32_t configuration_flags; 535 #define IWN_STATS_CONF_CLEAR_STATS htole32(0x1) 536 #define IWN_STATS_CONF_DISABLE_NOTIF htole32(0x2) 537 } __packed; 538 539 /* Antenna flags, used in various commands. */ 540 #define IWN_ANT_A (1 << 0) 541 #define IWN_ANT_B (1 << 1) 542 #define IWN_ANT_C (1 << 2) 543 /* Shortcuts. */ 544 #define IWN_ANT_AB (IWN_ANT_A | IWN_ANT_B) 545 #define IWN_ANT_BC (IWN_ANT_B | IWN_ANT_C) 546 #define IWN_ANT_AC (IWN_ANT_A | IWN_ANT_C) 547 #define IWN_ANT_ABC (IWN_ANT_A | IWN_ANT_B | IWN_ANT_C) 548 549 /* Structure for command IWN_CMD_RXON. */ 550 struct iwn_rxon { 551 uint8_t myaddr[IEEE80211_ADDR_LEN]; 552 uint16_t reserved1; 553 uint8_t bssid[IEEE80211_ADDR_LEN]; 554 uint16_t reserved2; 555 uint8_t wlap[IEEE80211_ADDR_LEN]; 556 uint16_t reserved3; 557 uint8_t mode; 558 #define IWN_MODE_HOSTAP 1 559 #define IWN_MODE_STA 3 560 #define IWN_MODE_IBSS 4 561 #define IWN_MODE_MONITOR 6 562 #define IWN_MODE_2STA 8 563 #define IWN_MODE_P2P 9 564 565 uint8_t air; 566 uint16_t rxchain; 567 #define IWN_RXCHAIN_DRIVER_FORCE (1 << 0) 568 #define IWN_RXCHAIN_VALID(x) (((x) & IWN_ANT_ABC) << 1) 569 #define IWN_RXCHAIN_FORCE_SEL(x) (((x) & IWN_ANT_ABC) << 4) 570 #define IWN_RXCHAIN_FORCE_MIMO_SEL(x) (((x) & IWN_ANT_ABC) << 7) 571 #define IWN_RXCHAIN_IDLE_COUNT(x) ((x) << 10) 572 #define IWN_RXCHAIN_MIMO_COUNT(x) ((x) << 12) 573 #define IWN_RXCHAIN_MIMO_FORCE (1 << 14) 574 575 uint8_t ofdm_mask; 576 uint8_t cck_mask; 577 uint16_t associd; 578 uint32_t flags; 579 #define IWN_RXON_24GHZ (1 << 0) 580 #define IWN_RXON_CCK (1 << 1) 581 #define IWN_RXON_AUTO (1 << 2) 582 #define IWN_RXON_SHSLOT (1 << 4) 583 #define IWN_RXON_SHPREAMBLE (1 << 5) 584 #define IWN_RXON_NODIVERSITY (1 << 7) 585 #define IWN_RXON_ANTENNA_A (1 << 8) 586 #define IWN_RXON_ANTENNA_B (1 << 9) 587 #define IWN_RXON_TSF (1 << 15) 588 #define IWN_RXON_HT_HT40MINUS (1 << 22) 589 #define IWN_RXON_HT_PROTMODE(x) (x << 23) 590 #define IWN_RXON_HT_MODEPURE40 (1 << 25) 591 #define IWN_RXON_HT_MODEMIXED (2 << 25) 592 #define IWN_RXON_CTS_TO_SELF (1 << 30) 593 594 uint32_t filter; 595 #define IWN_FILTER_PROMISC (1 << 0) 596 #define IWN_FILTER_CTL (1 << 1) 597 #define IWN_FILTER_MULTICAST (1 << 2) 598 #define IWN_FILTER_NODECRYPT (1 << 3) 599 #define IWN_FILTER_BSS (1 << 5) 600 #define IWN_FILTER_BEACON (1 << 6) 601 602 uint8_t chan; 603 uint8_t reserved4; 604 uint8_t ht_single_mask; 605 uint8_t ht_dual_mask; 606 /* The following fields are for >=5000 Series only. */ 607 uint8_t ht_triple_mask; 608 uint8_t reserved5; 609 uint16_t acquisition; 610 uint16_t reserved6; 611 } __packed; 612 613 #define IWN4965_RXONSZ (sizeof (struct iwn_rxon) - 6) 614 #define IWN5000_RXONSZ (sizeof (struct iwn_rxon)) 615 616 /* Structure for command IWN_CMD_ASSOCIATE. */ 617 struct iwn_assoc { 618 uint32_t flags; 619 uint32_t filter; 620 uint8_t ofdm_mask; 621 uint8_t cck_mask; 622 uint16_t reserved; 623 } __packed; 624 625 /* Structure for command IWN_CMD_EDCA_PARAMS. */ 626 struct iwn_edca_params { 627 uint32_t flags; 628 #define IWN_EDCA_UPDATE (1 << 0) 629 #define IWN_EDCA_TXOP (1 << 4) 630 631 struct { 632 uint16_t cwmin; 633 uint16_t cwmax; 634 uint8_t aifsn; 635 uint8_t reserved; 636 uint16_t txoplimit; 637 } __packed ac[WME_NUM_AC]; 638 } __packed; 639 640 /* Structure for command IWN_CMD_TIMING. */ 641 struct iwn_cmd_timing { 642 uint64_t tstamp; 643 uint16_t bintval; 644 uint16_t atim; 645 uint32_t binitval; 646 uint16_t lintval; 647 uint8_t dtim_period; 648 uint8_t delta_cp_bss_tbtts; 649 } __packed; 650 651 /* Structure for command IWN_CMD_ADD_NODE. */ 652 struct iwn_node_info { 653 uint8_t control; 654 #define IWN_NODE_UPDATE (1 << 0) 655 656 uint8_t reserved1[3]; 657 658 uint8_t macaddr[IEEE80211_ADDR_LEN]; 659 uint16_t reserved2; 660 uint8_t id; 661 #define IWN_ID_BSS 0 662 #define IWN_STA_ID 1 663 664 #define IWN_PAN_ID_BCAST 14 665 #define IWN5000_ID_BROADCAST 15 666 #define IWN4965_ID_BROADCAST 31 667 668 uint8_t flags; 669 #define IWN_FLAG_SET_KEY (1 << 0) 670 #define IWN_FLAG_SET_DISABLE_TID (1 << 1) 671 #define IWN_FLAG_SET_TXRATE (1 << 2) 672 #define IWN_FLAG_SET_ADDBA (1 << 3) 673 #define IWN_FLAG_SET_DELBA (1 << 4) 674 675 uint16_t reserved3; 676 uint16_t kflags; 677 #define IWN_KFLAG_CCMP (1 << 1) 678 #define IWN_KFLAG_MAP (1 << 3) 679 #define IWN_KFLAG_KID(kid) ((kid) << 8) 680 #define IWN_KFLAG_INVALID (1 << 11) 681 #define IWN_KFLAG_GROUP (1 << 14) 682 683 uint8_t tsc2; /* TKIP TSC2 */ 684 uint8_t reserved4; 685 uint16_t ttak[5]; 686 uint8_t kid; 687 uint8_t reserved5; 688 uint8_t key[16]; 689 /* The following 3 fields are for 5000 Series only. */ 690 uint64_t tsc; 691 uint8_t rxmic[8]; 692 uint8_t txmic[8]; 693 694 uint32_t htflags; 695 #define IWN_SMPS_MIMO_PROT (1 << 17) 696 #define IWN_AMDPU_SIZE_FACTOR(x) ((x) << 19) 697 #define IWN_NODE_HT40 (1 << 21) 698 #define IWN_SMPS_MIMO_DIS (1 << 22) 699 #define IWN_AMDPU_DENSITY(x) ((x) << 23) 700 701 uint32_t mask; 702 uint16_t disable_tid; 703 uint16_t reserved6; 704 uint8_t addba_tid; 705 uint8_t delba_tid; 706 uint16_t addba_ssn; 707 uint32_t reserved7; 708 } __packed; 709 710 struct iwn4965_node_info { 711 uint8_t control; 712 uint8_t reserved1[3]; 713 uint8_t macaddr[IEEE80211_ADDR_LEN]; 714 uint16_t reserved2; 715 uint8_t id; 716 uint8_t flags; 717 uint16_t reserved3; 718 uint16_t kflags; 719 uint8_t tsc2; /* TKIP TSC2 */ 720 uint8_t reserved4; 721 uint16_t ttak[5]; 722 uint8_t kid; 723 uint8_t reserved5; 724 uint8_t key[16]; 725 uint32_t htflags; 726 uint32_t mask; 727 uint16_t disable_tid; 728 uint16_t reserved6; 729 uint8_t addba_tid; 730 uint8_t delba_tid; 731 uint16_t addba_ssn; 732 uint32_t reserved7; 733 } __packed; 734 735 #define IWN_RFLAG_MCS (1 << 8) 736 #define IWN_RFLAG_CCK (1 << 9) 737 #define IWN_RFLAG_GREENFIELD (1 << 10) 738 #define IWN_RFLAG_HT40 (1 << 11) 739 #define IWN_RFLAG_DUPLICATE (1 << 12) 740 #define IWN_RFLAG_SGI (1 << 13) 741 #define IWN_RFLAG_ANT(x) ((x) << 14) 742 743 /* Structure for command IWN_CMD_TX_DATA. */ 744 struct iwn_cmd_data { 745 uint16_t len; 746 uint16_t lnext; 747 uint32_t flags; 748 #define IWN_TX_NEED_PROTECTION (1 << 0) /* 5000 only */ 749 #define IWN_TX_NEED_RTS (1 << 1) 750 #define IWN_TX_NEED_CTS (1 << 2) 751 #define IWN_TX_NEED_ACK (1 << 3) 752 #define IWN_TX_LINKQ (1 << 4) 753 #define IWN_TX_IMM_BA (1 << 6) 754 #define IWN_TX_FULL_TXOP (1 << 7) 755 #define IWN_TX_BT_DISABLE (1 << 12) /* bluetooth coexistence */ 756 #define IWN_TX_AUTO_SEQ (1 << 13) 757 #define IWN_TX_MORE_FRAG (1 << 14) 758 #define IWN_TX_INSERT_TSTAMP (1 << 16) 759 #define IWN_TX_NEED_PADDING (1 << 20) 760 761 uint32_t scratch; 762 uint32_t rate; 763 764 uint8_t id; 765 uint8_t security; 766 #define IWN_CIPHER_WEP40 1 767 #define IWN_CIPHER_CCMP 2 768 #define IWN_CIPHER_TKIP 3 769 #define IWN_CIPHER_WEP104 9 770 771 uint8_t linkq; 772 uint8_t reserved2; 773 uint8_t key[16]; 774 uint16_t fnext; 775 uint16_t reserved3; 776 uint32_t lifetime; 777 #define IWN_LIFETIME_INFINITE 0xffffffff 778 779 uint32_t loaddr; 780 uint8_t hiaddr; 781 uint8_t rts_ntries; 782 uint8_t data_ntries; 783 uint8_t tid; 784 uint16_t timeout; 785 uint16_t txop; 786 } __packed; 787 788 /* Structure for command IWN_CMD_LINK_QUALITY. */ 789 #define IWN_MAX_TX_RETRIES 16 790 struct iwn_cmd_link_quality { 791 uint8_t id; 792 uint8_t reserved1; 793 uint16_t ctl; 794 uint8_t flags; 795 uint8_t mimo; 796 uint8_t antmsk_1stream; 797 uint8_t antmsk_2stream; 798 uint8_t ridx[WME_NUM_AC]; 799 uint16_t ampdu_limit; 800 uint8_t ampdu_threshold; 801 uint8_t ampdu_max; 802 uint32_t reserved2; 803 uint32_t retry[IWN_MAX_TX_RETRIES]; 804 uint32_t reserved3; 805 } __packed; 806 807 /* Structure for command IWN_CMD_SET_LED. */ 808 struct iwn_cmd_led { 809 uint32_t unit; /* multiplier (in usecs) */ 810 uint8_t which; 811 #define IWN_LED_ACTIVITY 1 812 #define IWN_LED_LINK 2 813 814 uint8_t off; 815 uint8_t on; 816 uint8_t reserved; 817 } __packed; 818 819 /* Structure for command IWN5000_CMD_WIMAX_COEX. */ 820 struct iwn5000_wimax_coex { 821 uint32_t flags; 822 #define IWN_WIMAX_COEX_STA_TABLE_VALID (1 << 0) 823 #define IWN_WIMAX_COEX_UNASSOC_WA_UNMASK (1 << 2) 824 #define IWN_WIMAX_COEX_ASSOC_WA_UNMASK (1 << 3) 825 #define IWN_WIMAX_COEX_ENABLE (1 << 7) 826 827 struct iwn5000_wimax_event { 828 uint8_t request; 829 uint8_t window; 830 uint8_t reserved; 831 uint8_t flags; 832 } __packed events[16]; 833 } __packed; 834 835 /* Structures for command IWN5000_CMD_CALIB_CONFIG. */ 836 struct iwn5000_calib_elem { 837 uint32_t enable; 838 uint32_t start; 839 #define IWN5000_CALIB_DC (1 << 1) 840 841 uint32_t send; 842 uint32_t apply; 843 uint32_t reserved; 844 } __packed; 845 846 struct iwn5000_calib_status { 847 struct iwn5000_calib_elem once; 848 struct iwn5000_calib_elem perd; 849 uint32_t flags; 850 } __packed; 851 852 struct iwn5000_calib_config { 853 struct iwn5000_calib_status ucode; 854 struct iwn5000_calib_status driver; 855 uint32_t reserved; 856 } __packed; 857 858 /* Structure for command IWN_CMD_SET_POWER_MODE. */ 859 struct iwn_pmgt_cmd { 860 uint16_t flags; 861 #define IWN_PS_ALLOW_SLEEP (1 << 0) 862 #define IWN_PS_NOTIFY (1 << 1) 863 #define IWN_PS_SLEEP_OVER_DTIM (1 << 2) 864 #define IWN_PS_PCI_PMGT (1 << 3) 865 #define IWN_PS_FAST_PD (1 << 4) 866 #define IWN_PS_BEACON_FILTERING (1 << 5) 867 #define IWN_PS_SHADOW_REG (1 << 6) 868 #define IWN_PS_CT_KILL (1 << 7) 869 #define IWN_PS_BT_SCD (1 << 8) 870 #define IWN_PS_ADVANCED_PM (1 << 9) 871 872 uint8_t keepalive; 873 uint8_t debug; 874 uint32_t rxtimeout; 875 uint32_t txtimeout; 876 uint32_t intval[5]; 877 uint32_t beacons; 878 } __packed; 879 880 /* Structures for command IWN_CMD_SCAN. */ 881 struct iwn_scan_essid { 882 uint8_t id; 883 uint8_t len; 884 uint8_t data[IEEE80211_NWID_LEN]; 885 } __packed; 886 887 struct iwn_scan_hdr { 888 uint16_t len; 889 uint8_t scan_flags; 890 uint8_t nchan; 891 uint16_t quiet_time; 892 uint16_t quiet_threshold; 893 uint16_t crc_threshold; 894 uint16_t rxchain; 895 uint32_t max_svc; /* background scans */ 896 uint32_t pause_svc; /* background scans */ 897 uint32_t flags; 898 uint32_t filter; 899 900 /* Followed by a struct iwn_cmd_data. */ 901 /* Followed by an array of 20 structs iwn_scan_essid. */ 902 /* Followed by probe request body. */ 903 /* Followed by an array of ``nchan'' structs iwn_scan_chan. */ 904 } __packed; 905 906 struct iwn_scan_chan { 907 uint32_t flags; 908 #define IWN_CHAN_PASSIVE (0 << 0) 909 #define IWN_CHAN_ACTIVE (1 << 0) 910 #define IWN_CHAN_NPBREQS(x) (((1 << (x)) - 1) << 1) 911 912 uint16_t chan; 913 uint8_t rf_gain; 914 uint8_t dsp_gain; 915 uint16_t active; /* msecs */ 916 uint16_t passive; /* msecs */ 917 } __packed; 918 919 #define IWN_SCAN_CRC_TH_DISABLED 0 920 #define IWN_SCAN_CRC_TH_DEFAULT htole16(1) 921 #define IWN_SCAN_CRC_TH_NEVER htole16(0xffff) 922 923 /* Maximum size of a scan command. */ 924 #define IWN_SCAN_MAXSZ (MCLBYTES - 4) 925 926 /* 927 * For active scan, listen ACTIVE_DWELL_TIME (msec) on each channel after 928 * sending probe req. This should be set long enough to hear probe responses 929 * from more than one AP. 930 */ 931 #define IWN_ACTIVE_DWELL_TIME_2GHZ (30) /* all times in msec */ 932 #define IWN_ACTIVE_DWELL_TIME_5GHZ (20) 933 #define IWN_ACTIVE_DWELL_FACTOR_2GHZ (3) 934 #define IWN_ACTIVE_DWELL_FACTOR_5GHZ (2) 935 936 /* 937 * For passive scan, listen PASSIVE_DWELL_TIME (msec) on each channel. 938 * Must be set longer than active dwell time. 939 * For the most reliable scan, set > AP beacon interval (typically 100msec). 940 */ 941 #define IWN_PASSIVE_DWELL_TIME_2GHZ (20) /* all times in msec */ 942 #define IWN_PASSIVE_DWELL_TIME_5GHZ (10) 943 #define IWN_PASSIVE_DWELL_BASE (100) 944 #define IWN_CHANNEL_TUNE_TIME (5) 945 946 #define IWN_SCAN_CHAN_TIMEOUT 2 947 #define IWN_MAX_SCAN_CHANNEL 50 948 949 /* 950 * If active scanning is requested but a certain channel is 951 * marked passive, we can do active scanning if we detect 952 * transmissions. 953 * 954 * There is an issue with some firmware versions that triggers 955 * a sysassert on a "good CRC threshold" of zero (== disabled), 956 * on a radar channel even though this means that we should NOT 957 * send probes. 958 * 959 * The "good CRC threshold" is the number of frames that we 960 * need to receive during our dwell time on a channel before 961 * sending out probes -- setting this to a huge value will 962 * mean we never reach it, but at the same time work around 963 * the aforementioned issue. Thus use IWL_GOOD_CRC_TH_NEVER 964 * here instead of IWL_GOOD_CRC_TH_DISABLED. 965 * 966 * This was fixed in later versions along with some other 967 * scan changes, and the threshold behaves as a flag in those 968 * versions. 969 */ 970 #define IWN_GOOD_CRC_TH_DISABLED 0 971 #define IWN_GOOD_CRC_TH_DEFAULT htole16(1) 972 #define IWN_GOOD_CRC_TH_NEVER htole16(0xffff) 973 974 /* Structure for command IWN_CMD_TXPOWER (4965AGN only.) */ 975 #define IWN_RIDX_MAX 32 976 struct iwn4965_cmd_txpower { 977 uint8_t band; 978 uint8_t reserved1; 979 uint8_t chan; 980 uint8_t reserved2; 981 struct { 982 uint8_t rf_gain[2]; 983 uint8_t dsp_gain[2]; 984 } __packed power[IWN_RIDX_MAX + 1]; 985 } __packed; 986 987 /* Structure for command IWN_CMD_TXPOWER_DBM (5000 Series only.) */ 988 struct iwn5000_cmd_txpower { 989 int8_t global_limit; /* in half-dBm */ 990 #define IWN5000_TXPOWER_AUTO 0x7f 991 #define IWN5000_TXPOWER_MAX_DBM 16 992 993 uint8_t flags; 994 #define IWN5000_TXPOWER_NO_CLOSED (1 << 6) 995 996 int8_t srv_limit; /* in half-dBm */ 997 uint8_t reserved; 998 } __packed; 999 1000 /* Structures for command IWN_CMD_BLUETOOTH. */ 1001 struct iwn_bluetooth { 1002 uint8_t flags; 1003 #define IWN_BT_COEX_CHAN_ANN (1 << 0) 1004 #define IWN_BT_COEX_BT_PRIO (1 << 1) 1005 #define IWN_BT_COEX_2_WIRE (1 << 2) 1006 1007 uint8_t lead_time; 1008 #define IWN_BT_LEAD_TIME_DEF 30 1009 1010 uint8_t max_kill; 1011 #define IWN_BT_MAX_KILL_DEF 5 1012 1013 uint8_t reserved; 1014 uint32_t kill_ack; 1015 uint32_t kill_cts; 1016 } __packed; 1017 1018 struct iwn6000_btcoex_config { 1019 uint8_t flags; 1020 #define IWN_BT_FLAG_COEX6000_CHAN_INHIBITION 1 1021 #define IWN_BT_FLAG_COEX6000_MODE_MASK ((1 << 3) | (1 << 4) | (1 << 5 )) 1022 #define IWN_BT_FLAG_COEX6000_MODE_SHIFT 3 1023 #define IWN_BT_FLAG_COEX6000_MODE_DISABLED 0 1024 #define IWN_BT_FLAG_COEX6000_MODE_LEGACY_2W 1 1025 #define IWN_BT_FLAG_COEX6000_MODE_3W 2 1026 #define IWN_BT_FLAG_COEX6000_MODE_4W 3 1027 1028 #define IWN_BT_FLAG_UCODE_DEFAULT (1 << 6) 1029 #define IWN_BT_FLAG_SYNC_2_BT_DISABLE (1 << 7) 1030 uint8_t lead_time; 1031 uint8_t max_kill; 1032 uint8_t bt3_t7_timer; 1033 uint32_t kill_ack; 1034 uint32_t kill_cts; 1035 uint8_t sample_time; 1036 uint8_t bt3_t2_timer; 1037 uint16_t bt4_reaction; 1038 uint32_t lookup_table[12]; 1039 uint16_t bt4_decision; 1040 uint16_t valid; 1041 uint8_t prio_boost; 1042 uint8_t tx_prio_boost; 1043 uint16_t rx_prio_boost; 1044 } __packed; 1045 1046 /* Structure for enhanced command IWN_CMD_BLUETOOTH for 2000 Series. */ 1047 struct iwn2000_btcoex_config { 1048 uint8_t flags; /* Cf Flags in iwn6000_btcoex_config */ 1049 uint8_t lead_time; 1050 uint8_t max_kill; 1051 uint8_t bt3_t7_timer; 1052 uint32_t kill_ack; 1053 uint32_t kill_cts; 1054 uint8_t sample_time; 1055 uint8_t bt3_t2_timer; 1056 uint16_t bt4_reaction; 1057 uint32_t lookup_table[12]; 1058 uint16_t bt4_decision; 1059 uint16_t valid; 1060 1061 uint32_t prio_boost; /* size change prior to iwn6000_btcoex_config */ 1062 uint8_t reserved; /* added prior to iwn6000_btcoex_config */ 1063 1064 uint8_t tx_prio_boost; 1065 uint16_t rx_prio_boost; 1066 } __packed; 1067 1068 struct iwn_btcoex_priotable { 1069 uint8_t calib_init1; 1070 uint8_t calib_init2; 1071 uint8_t calib_periodic_low1; 1072 uint8_t calib_periodic_low2; 1073 uint8_t calib_periodic_high1; 1074 uint8_t calib_periodic_high2; 1075 uint8_t dtim; 1076 uint8_t scan52; 1077 uint8_t scan24; 1078 uint8_t reserved[7]; 1079 } __packed; 1080 1081 struct iwn_btcoex_prot { 1082 uint8_t open; 1083 uint8_t type; 1084 uint8_t reserved[2]; 1085 } __packed; 1086 1087 /* Structure for command IWN_CMD_SET_CRITICAL_TEMP. */ 1088 struct iwn_critical_temp { 1089 uint32_t reserved; 1090 uint32_t tempM; 1091 uint32_t tempR; 1092 /* degK <-> degC conversion macros. */ 1093 #define IWN_CTOK(c) ((c) + 273) 1094 #define IWN_KTOC(k) ((k) - 273) 1095 #define IWN_CTOMUK(c) (((c) * 1000000) + 273150000) 1096 } __packed; 1097 1098 /* Structures for command IWN_CMD_SET_SENSITIVITY. */ 1099 struct iwn_sensitivity_cmd { 1100 uint16_t which; 1101 #define IWN_SENSITIVITY_DEFAULTTBL 0 1102 #define IWN_SENSITIVITY_WORKTBL 1 1103 1104 uint16_t energy_cck; 1105 uint16_t energy_ofdm; 1106 uint16_t corr_ofdm_x1; 1107 uint16_t corr_ofdm_mrc_x1; 1108 uint16_t corr_cck_mrc_x4; 1109 uint16_t corr_ofdm_x4; 1110 uint16_t corr_ofdm_mrc_x4; 1111 uint16_t corr_barker; 1112 uint16_t corr_barker_mrc; 1113 uint16_t corr_cck_x4; 1114 uint16_t energy_ofdm_th; 1115 } __packed; 1116 1117 struct iwn_enhanced_sensitivity_cmd { 1118 uint16_t which; 1119 uint16_t energy_cck; 1120 uint16_t energy_ofdm; 1121 uint16_t corr_ofdm_x1; 1122 uint16_t corr_ofdm_mrc_x1; 1123 uint16_t corr_cck_mrc_x4; 1124 uint16_t corr_ofdm_x4; 1125 uint16_t corr_ofdm_mrc_x4; 1126 uint16_t corr_barker; 1127 uint16_t corr_barker_mrc; 1128 uint16_t corr_cck_x4; 1129 uint16_t energy_ofdm_th; 1130 /* "Enhanced" part. */ 1131 uint16_t ina_det_ofdm; 1132 uint16_t ina_det_cck; 1133 uint16_t corr_11_9_en; 1134 uint16_t ofdm_det_slope_mrc; 1135 uint16_t ofdm_det_icept_mrc; 1136 uint16_t ofdm_det_slope; 1137 uint16_t ofdm_det_icept; 1138 uint16_t cck_det_slope_mrc; 1139 uint16_t cck_det_icept_mrc; 1140 uint16_t cck_det_slope; 1141 uint16_t cck_det_icept; 1142 uint16_t reserved; 1143 } __packed; 1144 1145 /* 1146 * Define maximal number of calib result send to runtime firmware 1147 * PS: TEMP_OFFSET count for 2 (std and v2) 1148 */ 1149 #define IWN5000_PHY_CALIB_MAX_RESULT 8 1150 1151 /* Structures for command IWN_CMD_PHY_CALIB. */ 1152 struct iwn_phy_calib { 1153 uint8_t code; 1154 #define IWN4965_PHY_CALIB_DIFF_GAIN 7 1155 #define IWN5000_PHY_CALIB_DC 8 1156 #define IWN5000_PHY_CALIB_LO 9 1157 #define IWN5000_PHY_CALIB_TX_IQ 11 1158 #define IWN5000_PHY_CALIB_CRYSTAL 15 1159 #define IWN5000_PHY_CALIB_BASE_BAND 16 1160 #define IWN5000_PHY_CALIB_TX_IQ_PERIODIC 17 1161 #define IWN5000_PHY_CALIB_TEMP_OFFSET 18 1162 1163 #define IWN5000_PHY_CALIB_RESET_NOISE_GAIN 18 1164 #define IWN5000_PHY_CALIB_NOISE_GAIN 19 1165 1166 uint8_t group; 1167 uint8_t ngroups; 1168 uint8_t isvalid; 1169 } __packed; 1170 1171 struct iwn5000_phy_calib_crystal { 1172 uint8_t code; 1173 uint8_t group; 1174 uint8_t ngroups; 1175 uint8_t isvalid; 1176 1177 uint8_t cap_pin[2]; 1178 uint8_t reserved[2]; 1179 } __packed; 1180 1181 struct iwn5000_phy_calib_temp_offset { 1182 uint8_t code; 1183 uint8_t group; 1184 uint8_t ngroups; 1185 uint8_t isvalid; 1186 int16_t offset; 1187 #define IWN_DEFAULT_TEMP_OFFSET 2700 1188 1189 uint16_t reserved; 1190 } __packed; 1191 1192 struct iwn5000_phy_calib_temp_offsetv2 { 1193 uint8_t code; 1194 uint8_t group; 1195 uint8_t ngroups; 1196 uint8_t isvalid; 1197 int16_t offset_high; 1198 int16_t offset_low; 1199 int16_t burnt_voltage_ref; 1200 int16_t reserved; 1201 } __packed; 1202 1203 struct iwn_phy_calib_gain { 1204 uint8_t code; 1205 uint8_t group; 1206 uint8_t ngroups; 1207 uint8_t isvalid; 1208 1209 int8_t gain[3]; 1210 uint8_t reserved; 1211 } __packed; 1212 1213 /* Structure for command IWN_CMD_SPECTRUM_MEASUREMENT. */ 1214 struct iwn_spectrum_cmd { 1215 uint16_t len; 1216 uint8_t token; 1217 uint8_t id; 1218 uint8_t origin; 1219 uint8_t periodic; 1220 uint16_t timeout; 1221 uint32_t start; 1222 uint32_t reserved1; 1223 uint32_t flags; 1224 uint32_t filter; 1225 uint16_t nchan; 1226 uint16_t reserved2; 1227 struct { 1228 uint32_t duration; 1229 uint8_t chan; 1230 uint8_t type; 1231 #define IWN_MEASUREMENT_BASIC (1 << 0) 1232 #define IWN_MEASUREMENT_CCA (1 << 1) 1233 #define IWN_MEASUREMENT_RPI_HISTOGRAM (1 << 2) 1234 #define IWN_MEASUREMENT_NOISE_HISTOGRAM (1 << 3) 1235 #define IWN_MEASUREMENT_FRAME (1 << 4) 1236 #define IWN_MEASUREMENT_IDLE (1 << 7) 1237 1238 uint16_t reserved; 1239 } __packed chan[10]; 1240 } __packed; 1241 1242 /* Structure for IWN_UC_READY notification. */ 1243 #define IWN_NATTEN_GROUPS 5 1244 struct iwn_ucode_info { 1245 uint8_t minor; 1246 uint8_t major; 1247 uint16_t reserved1; 1248 uint8_t revision[8]; 1249 uint8_t type; 1250 uint8_t subtype; 1251 #define IWN_UCODE_RUNTIME 0 1252 #define IWN_UCODE_INIT 9 1253 1254 uint16_t reserved2; 1255 uint32_t logptr; 1256 uint32_t errptr; 1257 uint32_t tstamp; 1258 uint32_t valid; 1259 1260 /* The following fields are for UCODE_INIT only. */ 1261 int32_t volt; 1262 struct { 1263 int32_t chan20MHz; 1264 int32_t chan40MHz; 1265 } __packed temp[4]; 1266 int32_t atten[IWN_NATTEN_GROUPS][2]; 1267 } __packed; 1268 1269 /* Structures for IWN_TX_DONE notification. */ 1270 1271 /* 1272 * TX command response is sent after *agn* transmission attempts. 1273 * 1274 * both postpone and abort status are expected behavior from uCode. there is 1275 * no special operation required from driver; except for RFKILL_FLUSH, 1276 * which required tx flush host command to flush all the tx frames in queues 1277 */ 1278 #define IWN_TX_STATUS_MSK 0x000000ff 1279 #define IWN_TX_STATUS_DELAY_MSK 0x00000040 1280 #define IWN_TX_STATUS_ABORT_MSK 0x00000080 1281 #define IWN_TX_PACKET_MODE_MSK 0x0000ff00 1282 #define IWN_TX_FIFO_NUMBER_MSK 0x00070000 1283 #define IWN_TX_RESERVED 0x00780000 1284 #define IWN_TX_POWER_PA_DETECT_MSK 0x7f800000 1285 #define IWN_TX_ABORT_REQUIRED_MSK 0x80000000 1286 1287 /* Success status */ 1288 #define IWN_TX_STATUS_SUCCESS 0x01 1289 #define IWN_TX_STATUS_DIRECT_DONE 0x02 1290 1291 /* postpone TX */ 1292 #define IWN_TX_STATUS_POSTPONE_DELAY 0x40 1293 #define IWN_TX_STATUS_POSTPONE_FEW_BYTES 0x41 1294 #define IWN_TX_STATUS_POSTPONE_BT_PRIO 0x42 1295 #define IWN_TX_STATUS_POSTPONE_QUIET_PERIOD 0x43 1296 #define IWN_TX_STATUS_POSTPONE_CALC_TTAK 0x44 1297 1298 /* Failures */ 1299 #define IWN_TX_FAIL 0x80 /* all failures have 0x80 set */ 1300 #define IWN_TX_STATUS_FAIL_INTERNAL_CROSSED_RETRY 0x81 1301 #define IWN_TX_FAIL_SHORT_LIMIT 0x82 /* too many RTS retries */ 1302 #define IWN_TX_FAIL_LONG_LIMIT 0x83 /* too many retries */ 1303 #define IWN_TX_FAIL_FIFO_UNDERRRUN 0x84 /* tx fifo not kept running */ 1304 #define IWN_TX_STATUS_FAIL_DRAIN_FLOW 0x85 1305 #define IWN_TX_STATUS_FAIL_RFKILL_FLUSH 0x86 1306 #define IWN_TX_STATUS_FAIL_LIFE_EXPIRE 0x87 1307 #define IWN_TX_FAIL_DEST_IN_PS 0x88 /* sta found in power save */ 1308 #define IWN_TX_STATUS_FAIL_HOST_ABORTED 0x89 1309 #define IWN_TX_STATUS_FAIL_BT_RETRY 0x8a 1310 #define IWN_TX_FAIL_STA_INVALID 0x8b /* XXX STA invalid (???) */ 1311 #define IWN_TX_STATUS_FAIL_FRAG_DROPPED 0x8c 1312 #define IWN_TX_STATUS_FAIL_TID_DISABLE 0x8d 1313 #define IWN_TX_STATUS_FAIL_FIFO_FLUSHED 0x8e 1314 #define IWN_TX_STATUS_FAIL_INSUFFICIENT_CF_POLL 0x8f 1315 #define IWN_TX_FAIL_TX_LOCKED 0x90 /* waiting to see traffic */ 1316 #define IWN_TX_STATUS_FAIL_NO_BEACON_ON_RADAR 0x91 1317 1318 /* 1319 * TX command response for A-MPDU packet responses. 1320 * 1321 * The status response is different to the non A-MPDU responses. 1322 * In addition, the sequence number is treated as the sequence 1323 * number of the TX command, NOT the 802.11 sequence number! 1324 */ 1325 #define IWN_AGG_TX_STATE_TRANSMITTED 0x00 1326 #define IWN_AGG_TX_STATE_UNDERRUN_MSK 0x01 1327 #define IWN_AGG_TX_STATE_FEW_BYTES_MSK 0x04 1328 #define IWN_AGG_TX_STATE_ABORT_MSK 0x08 1329 1330 #define IWN_AGG_TX_STATE_LAST_SENT_TTL_MSK 0x10 1331 #define IWN_AGG_TX_STATE_LAST_SENT_TRY_CNT_MSK 0x20 1332 1333 #define IWN_AGG_TX_STATE_SCD_QUERY_MSK 0x80 1334 1335 #define IWN_AGG_TX_STATE_TEST_BAD_CRC32_MSK 0x100 1336 1337 #define IWN_AGG_TX_STATE_RESPONSE_MSK 0x1ff 1338 #define IWN_AGG_TX_STATE_DUMP_TX_MSK 0x200 1339 #define IWN_AGG_TX_STATE_DELAY_TX_MSK 0x400 1340 1341 #define IWN_AGG_TX_STATUS_MSK 0x00000fff 1342 #define IWN_AGG_TX_TRY_MSK 0x0000f000 1343 1344 #define IWN_AGG_TX_STATE_LAST_SENT_MSK \ 1345 (IWN_AGG_TX_STATE_LAST_SENT_TTL_MSK | \ 1346 IWN_AGG_TX_STATE_LAST_SENT_TRY_CNT_MSK) 1347 1348 /* # tx attempts for first frame in aggregation */ 1349 #define IWN_AGG_TX_STATE_TRY_CNT_POS 12 1350 #define IWN_AGG_TX_STATE_TRY_CNT_MSK 0xf000 1351 1352 /* Command ID and sequence number of Tx command for this frame */ 1353 #define IWN_AGG_TX_STATE_SEQ_NUM_POS 16 1354 #define IWN_AGG_TX_STATE_SEQ_NUM_MSK 0xffff0000 1355 1356 struct iwn4965_tx_stat { 1357 uint8_t nframes; 1358 uint8_t btkillcnt; 1359 uint8_t rtsfailcnt; 1360 uint8_t ackfailcnt; 1361 uint32_t rate; 1362 uint16_t duration; 1363 uint16_t reserved; 1364 uint32_t power[2]; 1365 uint32_t status; 1366 } __packed; 1367 1368 struct iwn5000_tx_stat { 1369 uint8_t nframes; /* 1 no aggregation, >1 aggregation */ 1370 uint8_t btkillcnt; 1371 uint8_t rtsfailcnt; 1372 uint8_t ackfailcnt; 1373 uint32_t rate; 1374 uint16_t duration; 1375 uint16_t reserved; 1376 uint32_t power[2]; 1377 uint32_t info; 1378 uint16_t seq; 1379 uint16_t len; 1380 uint8_t tlc; 1381 uint8_t ratid; /* tid (0:3), sta_id (4:7) */ 1382 uint8_t fc[2]; 1383 uint16_t status; 1384 uint16_t sequence; 1385 } __packed; 1386 1387 /* Structure for IWN_BEACON_MISSED notification. */ 1388 struct iwn_beacon_missed { 1389 uint32_t consecutive; 1390 uint32_t total; 1391 uint32_t expected; 1392 uint32_t received; 1393 } __packed; 1394 1395 /* Structure for IWN_MPDU_RX_DONE notification. */ 1396 struct iwn_rx_mpdu { 1397 uint16_t len; 1398 uint16_t reserved; 1399 } __packed; 1400 1401 /* Structures for IWN_RX_DONE and IWN_MPDU_RX_DONE notifications. */ 1402 struct iwn4965_rx_phystat { 1403 uint16_t antenna; 1404 uint16_t agc; 1405 uint8_t rssi[6]; 1406 } __packed; 1407 1408 struct iwn5000_rx_phystat { 1409 uint32_t reserved1; 1410 uint32_t agc; 1411 uint16_t rssi[3]; 1412 } __packed; 1413 1414 struct iwn_rx_stat { 1415 uint8_t phy_len; 1416 uint8_t cfg_phy_len; 1417 #define IWN_STAT_MAXLEN 20 1418 1419 uint8_t id; 1420 uint8_t reserved1; 1421 uint64_t tstamp; 1422 uint32_t beacon; 1423 uint16_t flags; 1424 #define IWN_STAT_FLAG_SHPREAMBLE (1 << 2) 1425 1426 uint16_t chan; 1427 uint8_t phybuf[32]; 1428 uint32_t rate; 1429 /* 1430 * rate bit fields 1431 * 1432 * High-throughput (HT) rate format for bits 7:0 (bit 8 must be "1"): 1433 * 2-0: 0) 6 Mbps 1434 * 1) 12 Mbps 1435 * 2) 18 Mbps 1436 * 3) 24 Mbps 1437 * 4) 36 Mbps 1438 * 5) 48 Mbps 1439 * 6) 54 Mbps 1440 * 7) 60 Mbps 1441 * 1442 * 4-3: 0) Single stream (SISO) 1443 * 1) Dual stream (MIMO) 1444 * 2) Triple stream (MIMO) 1445 * 1446 * 5: Value of 0x20 in bits 7:0 indicates 6 Mbps HT40 duplicate data 1447 * 1448 * Legacy OFDM rate format for bits 7:0 (bit 8 must be "0", bit 9 "0"): 1449 * 3-0: 0xD) 6 Mbps 1450 * 0xF) 9 Mbps 1451 * 0x5) 12 Mbps 1452 * 0x7) 18 Mbps 1453 * 0x9) 24 Mbps 1454 * 0xB) 36 Mbps 1455 * 0x1) 48 Mbps 1456 * 0x3) 54 Mbps 1457 * 1458 * Legacy CCK rate format for bits 7:0 (bit 8 must be "0", bit 9 "1"): 1459 * 6-0: 10) 1 Mbps 1460 * 20) 2 Mbps 1461 * 55) 5.5 Mbps 1462 * 110) 11 Mbps 1463 * 1464 */ 1465 uint16_t len; 1466 uint16_t reserve3; 1467 } __packed; 1468 1469 #define IWN_RSSI_TO_DBM 44 1470 1471 /* Structure for IWN_RX_COMPRESSED_BA notification. */ 1472 struct iwn_compressed_ba { 1473 uint8_t macaddr[IEEE80211_ADDR_LEN]; 1474 uint16_t reserved; 1475 uint8_t id; 1476 uint8_t tid; 1477 uint16_t seq; 1478 uint64_t bitmap; 1479 uint16_t qid; 1480 uint16_t ssn; 1481 /* extra fields starting with iwn5000 */ 1482 #if 0 1483 uint8_t txed; /* number of frames sent */ 1484 uint8_t txed_2_done; /* number of frames acked */ 1485 uint16_t reserved1; 1486 #endif 1487 } __packed; 1488 1489 /* Structure for IWN_START_SCAN notification. */ 1490 struct iwn_start_scan { 1491 uint64_t tstamp; 1492 uint32_t tbeacon; 1493 uint8_t chan; 1494 uint8_t band; 1495 uint16_t reserved; 1496 uint32_t status; 1497 } __packed; 1498 1499 /* Structure for IWN_STOP_SCAN notification. */ 1500 struct iwn_stop_scan { 1501 uint8_t nchan; 1502 uint8_t status; 1503 uint8_t reserved; 1504 uint8_t chan; 1505 uint64_t tsf; 1506 } __packed; 1507 1508 /* Structure for IWN_SPECTRUM_MEASUREMENT notification. */ 1509 struct iwn_spectrum_notif { 1510 uint8_t id; 1511 uint8_t token; 1512 uint8_t idx; 1513 uint8_t state; 1514 #define IWN_MEASUREMENT_START 0 1515 #define IWN_MEASUREMENT_STOP 1 1516 1517 uint32_t start; 1518 uint8_t band; 1519 uint8_t chan; 1520 uint8_t type; 1521 uint8_t reserved1; 1522 uint32_t cca_ofdm; 1523 uint32_t cca_cck; 1524 uint32_t cca_time; 1525 uint8_t basic; 1526 uint8_t reserved2[3]; 1527 uint32_t ofdm[8]; 1528 uint32_t cck[8]; 1529 uint32_t stop; 1530 uint32_t status; 1531 #define IWN_MEASUREMENT_OK 0 1532 #define IWN_MEASUREMENT_CONCURRENT 1 1533 #define IWN_MEASUREMENT_CSA_CONFLICT 2 1534 #define IWN_MEASUREMENT_TGH_CONFLICT 3 1535 #define IWN_MEASUREMENT_STOPPED 6 1536 #define IWN_MEASUREMENT_TIMEOUT 7 1537 #define IWN_MEASUREMENT_FAILED 8 1538 } __packed; 1539 1540 /* Structures for IWN_{RX,BEACON}_STATISTICS notification. */ 1541 struct iwn_rx_phy_stats { 1542 uint32_t ina; 1543 uint32_t fina; 1544 uint32_t bad_plcp; 1545 uint32_t bad_crc32; 1546 uint32_t overrun; 1547 uint32_t eoverrun; 1548 uint32_t good_crc32; 1549 uint32_t fa; 1550 uint32_t bad_fina_sync; 1551 uint32_t sfd_timeout; 1552 uint32_t fina_timeout; 1553 uint32_t no_rts_ack; 1554 uint32_t rxe_limit; 1555 uint32_t ack; 1556 uint32_t cts; 1557 uint32_t ba_resp; 1558 uint32_t dsp_kill; 1559 uint32_t bad_mh; 1560 uint32_t rssi_sum; 1561 uint32_t reserved; 1562 } __packed; 1563 1564 struct iwn_rx_general_stats { 1565 uint32_t bad_cts; 1566 uint32_t bad_ack; 1567 uint32_t not_bss; 1568 uint32_t filtered; 1569 uint32_t bad_chan; 1570 uint32_t beacons; 1571 uint32_t missed_beacons; 1572 uint32_t adc_saturated; /* time in 0.8us */ 1573 uint32_t ina_searched; /* time in 0.8us */ 1574 uint32_t noise[3]; 1575 uint32_t flags; 1576 uint32_t load; 1577 uint32_t fa; 1578 uint32_t rssi[3]; 1579 uint32_t energy[3]; 1580 } __packed; 1581 1582 struct iwn_rx_ht_phy_stats { 1583 uint32_t bad_plcp; 1584 uint32_t overrun; 1585 uint32_t eoverrun; 1586 uint32_t good_crc32; 1587 uint32_t bad_crc32; 1588 uint32_t bad_mh; 1589 uint32_t good_ampdu_crc32; 1590 uint32_t ampdu; 1591 uint32_t fragment; 1592 uint32_t unsupport_mcs; 1593 } __packed; 1594 1595 struct iwn_rx_stats { 1596 struct iwn_rx_phy_stats ofdm; 1597 struct iwn_rx_phy_stats cck; 1598 struct iwn_rx_general_stats general; 1599 struct iwn_rx_ht_phy_stats ht; 1600 } __packed; 1601 1602 struct iwn_rx_general_stats_bt { 1603 struct iwn_rx_general_stats common; 1604 /* additional stats for bt */ 1605 uint32_t num_bt_kills; 1606 uint32_t reserved[2]; 1607 } __packed; 1608 1609 struct iwn_rx_stats_bt { 1610 struct iwn_rx_phy_stats ofdm; 1611 struct iwn_rx_phy_stats cck; 1612 struct iwn_rx_general_stats_bt general_bt; 1613 struct iwn_rx_ht_phy_stats ht; 1614 } __packed; 1615 1616 struct iwn_tx_stats { 1617 uint32_t preamble; 1618 uint32_t rx_detected; 1619 uint32_t bt_defer; 1620 uint32_t bt_kill; 1621 uint32_t short_len; 1622 uint32_t cts_timeout; 1623 uint32_t ack_timeout; 1624 uint32_t exp_ack; 1625 uint32_t ack; 1626 uint32_t msdu; 1627 uint32_t burst_err1; 1628 uint32_t burst_err2; 1629 uint32_t cts_collision; 1630 uint32_t ack_collision; 1631 uint32_t ba_timeout; 1632 uint32_t ba_resched; 1633 uint32_t query_ampdu; 1634 uint32_t query; 1635 uint32_t query_ampdu_frag; 1636 uint32_t query_mismatch; 1637 uint32_t not_ready; 1638 uint32_t underrun; 1639 uint32_t bt_ht_kill; 1640 uint32_t rx_ba_resp; 1641 /* 1642 * 6000 series only - LSB=ant A, ant B, ant C, MSB=reserved 1643 * TX power on chain in 1/2 dBm. 1644 */ 1645 uint32_t tx_power; 1646 uint32_t reserved[1]; 1647 } __packed; 1648 1649 struct iwn_general_stats { 1650 uint32_t temp; /* radio temperature */ 1651 uint32_t temp_m; /* radio voltage */ 1652 uint32_t burst_check; 1653 uint32_t burst; 1654 uint32_t wait_for_silence_timeout_cnt; 1655 uint32_t reserved1[3]; 1656 uint32_t sleep; 1657 uint32_t slot_out; 1658 uint32_t slot_idle; 1659 uint32_t ttl_tstamp; 1660 uint32_t tx_ant_a; 1661 uint32_t tx_ant_b; 1662 uint32_t exec; 1663 uint32_t probe; 1664 uint32_t reserved2[2]; 1665 uint32_t rx_enabled; 1666 /* 1667 * This is the number of times we have to re-tune 1668 * in order to get out of bad PHY status. 1669 */ 1670 uint32_t num_of_sos_states; 1671 } __packed; 1672 1673 struct iwn_stats { 1674 uint32_t flags; 1675 struct iwn_rx_stats rx; 1676 struct iwn_tx_stats tx; 1677 struct iwn_general_stats general; 1678 uint32_t reserved1[2]; 1679 } __packed; 1680 1681 struct iwn_bt_activity_stats { 1682 /* Tx statistics */ 1683 uint32_t hi_priority_tx_req_cnt; 1684 uint32_t hi_priority_tx_denied_cnt; 1685 uint32_t lo_priority_tx_req_cnt; 1686 uint32_t lo_priority_tx_denied_cnt; 1687 /* Rx statistics */ 1688 uint32_t hi_priority_rx_req_cnt; 1689 uint32_t hi_priority_rx_denied_cnt; 1690 uint32_t lo_priority_rx_req_cnt; 1691 uint32_t lo_priority_rx_denied_cnt; 1692 } __packed; 1693 1694 struct iwn_stats_bt { 1695 uint32_t flags; 1696 struct iwn_rx_stats_bt rx_bt; 1697 struct iwn_tx_stats tx; 1698 struct iwn_general_stats general; 1699 struct iwn_bt_activity_stats activity; 1700 uint32_t reserved1[2]; 1701 }; 1702 1703 /* Firmware error dump. */ 1704 struct iwn_fw_dump { 1705 uint32_t valid; 1706 uint32_t id; 1707 uint32_t pc; 1708 uint32_t branch_link[2]; 1709 uint32_t interrupt_link[2]; 1710 uint32_t error_data[2]; 1711 uint32_t src_line; 1712 uint32_t tsf; 1713 uint32_t time[2]; 1714 } __packed; 1715 1716 /* TLV firmware header. */ 1717 struct iwn_fw_tlv_hdr { 1718 uint32_t zero; /* Always 0, to differentiate from legacy. */ 1719 uint32_t signature; 1720 #define IWN_FW_SIGNATURE 0x0a4c5749 /* "IWL\n" */ 1721 1722 uint8_t descr[64]; 1723 uint32_t rev; 1724 #define IWN_FW_API(x) (((x) >> 8) & 0xff) 1725 1726 uint32_t build; 1727 uint64_t altmask; 1728 } __packed; 1729 1730 /* TLV header. */ 1731 struct iwn_fw_tlv { 1732 uint16_t type; 1733 #define IWN_FW_TLV_MAIN_TEXT 1 1734 #define IWN_FW_TLV_MAIN_DATA 2 1735 #define IWN_FW_TLV_INIT_TEXT 3 1736 #define IWN_FW_TLV_INIT_DATA 4 1737 #define IWN_FW_TLV_BOOT_TEXT 5 1738 #define IWN_FW_TLV_PBREQ_MAXLEN 6 1739 #define IWN_FW_TLV_PAN 7 1740 #define IWN_FW_TLV_RUNT_EVTLOG_PTR 8 1741 #define IWN_FW_TLV_RUNT_EVTLOG_SIZE 9 1742 #define IWN_FW_TLV_RUNT_ERRLOG_PTR 10 1743 #define IWN_FW_TLV_INIT_EVTLOG_PTR 11 1744 #define IWN_FW_TLV_INIT_EVTLOG_SIZE 12 1745 #define IWN_FW_TLV_INIT_ERRLOG_PTR 13 1746 #define IWN_FW_TLV_ENH_SENS 14 1747 #define IWN_FW_TLV_PHY_CALIB 15 1748 #define IWN_FW_TLV_WOWLAN_INST 16 1749 #define IWN_FW_TLV_WOWLAN_DATA 17 1750 #define IWN_FW_TLV_FLAGS 18 1751 1752 uint16_t alt; 1753 uint32_t len; 1754 } __packed; 1755 1756 #define IWN4965_FW_TEXT_MAXSZ ( 96 * 1024) 1757 #define IWN4965_FW_DATA_MAXSZ ( 40 * 1024) 1758 #define IWN5000_FW_TEXT_MAXSZ (256 * 1024) 1759 #define IWN5000_FW_DATA_MAXSZ ( 80 * 1024) 1760 #define IWN_FW_BOOT_TEXT_MAXSZ 1024 1761 #define IWN4965_FWSZ (IWN4965_FW_TEXT_MAXSZ + IWN4965_FW_DATA_MAXSZ) 1762 #define IWN5000_FWSZ IWN5000_FW_TEXT_MAXSZ 1763 1764 /* 1765 * Microcode flags TLV (18.) 1766 */ 1767 1768 /** 1769 * enum iwn_ucode_tlv_flag - ucode API flags 1770 * @IWN_UCODE_TLV_FLAGS_PAN: This is PAN capable microcode; this previously 1771 * was a separate TLV but moved here to save space. 1772 * @IWN_UCODE_TLV_FLAGS_NEWSCAN: new uCode scan behaviour on hidden SSID, 1773 * treats good CRC threshold as a boolean 1774 * @IWN_UCODE_TLV_FLAGS_MFP: This uCode image supports MFP (802.11w). 1775 * @IWN_UCODE_TLV_FLAGS_P2P: This uCode image supports P2P. 1776 * @IWN_UCODE_TLV_FLAGS_DW_BC_TABLE: The SCD byte count table is in DWORDS 1777 * @IWN_UCODE_TLV_FLAGS_UAPSD: This uCode image supports uAPSD 1778 * @IWN_UCODE_TLV_FLAGS_SHORT_BL: 16 entries of black list instead of 64 in scan 1779 * offload profile config command. 1780 * @IWN_UCODE_TLV_FLAGS_RX_ENERGY_API: supports rx signal strength api 1781 * @IWN_UCODE_TLV_FLAGS_TIME_EVENT_API_V2: using the new time event API. 1782 * @IWN_UCODE_TLV_FLAGS_D3_6_IPV6_ADDRS: D3 image supports up to six 1783 * (rather than two) IPv6 addresses 1784 * @IWN_UCODE_TLV_FLAGS_BF_UPDATED: new beacon filtering API 1785 * @IWN_UCODE_TLV_FLAGS_NO_BASIC_SSID: not sending a probe with the SSID element 1786 * from the probe request template. 1787 * @IWN_UCODE_TLV_FLAGS_D3_CONTINUITY_API: modified D3 API to allow keeping 1788 * connection when going back to D0 1789 * @IWN_UCODE_TLV_FLAGS_NEW_NSOFFL_SMALL: new NS offload (small version) 1790 * @IWN_UCODE_TLV_FLAGS_NEW_NSOFFL_LARGE: new NS offload (large version) 1791 * @IWN_UCODE_TLV_FLAGS_SCHED_SCAN: this uCode image supports scheduled scan. 1792 * @IWN_UCODE_TLV_FLAGS_STA_KEY_CMD: new ADD_STA and ADD_STA_KEY command API 1793 * @IWN_UCODE_TLV_FLAGS_DEVICE_PS_CMD: support device wide power command 1794 * containing CAM (Continuous Active Mode) indication. 1795 */ 1796 enum iwn_ucode_tlv_flag { 1797 IWN_UCODE_TLV_FLAGS_PAN = (1 << 0), 1798 IWN_UCODE_TLV_FLAGS_NEWSCAN = (1 << 1), 1799 IWN_UCODE_TLV_FLAGS_MFP = (1 << 2), 1800 IWN_UCODE_TLV_FLAGS_P2P = (1 << 3), 1801 IWN_UCODE_TLV_FLAGS_DW_BC_TABLE = (1 << 4), 1802 IWN_UCODE_TLV_FLAGS_NEWBT_COEX = (1 << 5), 1803 IWN_UCODE_TLV_FLAGS_UAPSD = (1 << 6), 1804 IWN_UCODE_TLV_FLAGS_SHORT_BL = (1 << 7), 1805 IWN_UCODE_TLV_FLAGS_RX_ENERGY_API = (1 << 8), 1806 IWN_UCODE_TLV_FLAGS_TIME_EVENT_API_V2 = (1 << 9), 1807 IWN_UCODE_TLV_FLAGS_D3_6_IPV6_ADDRS = (1 << 10), 1808 IWN_UCODE_TLV_FLAGS_BF_UPDATED = (1 << 11), 1809 IWN_UCODE_TLV_FLAGS_NO_BASIC_SSID = (1 << 12), 1810 IWN_UCODE_TLV_FLAGS_D3_CONTINUITY_API = (1 << 14), 1811 IWN_UCODE_TLV_FLAGS_NEW_NSOFFL_SMALL = (1 << 15), 1812 IWN_UCODE_TLV_FLAGS_NEW_NSOFFL_LARGE = (1 << 16), 1813 IWN_UCODE_TLV_FLAGS_SCHED_SCAN = (1 << 17), 1814 IWN_UCODE_TLV_FLAGS_STA_KEY_CMD = (1 << 19), 1815 IWN_UCODE_TLV_FLAGS_DEVICE_PS_CMD = (1 << 20), 1816 }; 1817 1818 /* 1819 * Offsets into EEPROM. 1820 */ 1821 #define IWN_EEPROM_MAC 0x015 1822 #define IWN_EEPROM_SKU_CAP 0x045 1823 #define IWN_EEPROM_RFCFG 0x048 1824 #define IWN4965_EEPROM_DOMAIN 0x060 1825 #define IWN4965_EEPROM_BAND1 0x063 1826 #define IWN5000_EEPROM_REG 0x066 1827 #define IWN5000_EEPROM_CAL 0x067 1828 #define IWN4965_EEPROM_BAND2 0x072 1829 #define IWN4965_EEPROM_BAND3 0x080 1830 #define IWN4965_EEPROM_BAND4 0x08d 1831 #define IWN4965_EEPROM_BAND5 0x099 1832 #define IWN4965_EEPROM_BAND6 0x0a0 1833 #define IWN4965_EEPROM_BAND7 0x0a8 1834 #define IWN4965_EEPROM_MAXPOW 0x0e8 1835 #define IWN4965_EEPROM_VOLTAGE 0x0e9 1836 #define IWN4965_EEPROM_BANDS 0x0ea 1837 /* Indirect offsets. */ 1838 #define IWN5000_EEPROM_NO_HT40 0x000 1839 #define IWN5000_EEPROM_DOMAIN 0x001 1840 #define IWN5000_EEPROM_BAND1 0x004 1841 #define IWN5000_EEPROM_BAND2 0x013 1842 #define IWN5000_EEPROM_BAND3 0x021 1843 #define IWN5000_EEPROM_BAND4 0x02e 1844 #define IWN5000_EEPROM_BAND5 0x03a 1845 #define IWN5000_EEPROM_BAND6 0x041 1846 #define IWN6000_EEPROM_BAND6 0x040 1847 #define IWN5000_EEPROM_BAND7 0x049 1848 #define IWN6000_EEPROM_ENHINFO 0x054 1849 #define IWN5000_EEPROM_CRYSTAL 0x128 1850 #define IWN5000_EEPROM_TEMP 0x12a 1851 #define IWN5000_EEPROM_VOLT 0x12b 1852 1853 /* Possible flags for IWN_EEPROM_SKU_CAP. */ 1854 #define IWN_EEPROM_SKU_CAP_11N (1 << 6) 1855 #define IWN_EEPROM_SKU_CAP_AMT (1 << 7) 1856 #define IWN_EEPROM_SKU_CAP_IPAN (1 << 8) 1857 1858 /* Possible flags for IWN_EEPROM_RFCFG. */ 1859 #define IWN_RFCFG_TYPE(x) (((x) >> 0) & 0x3) 1860 #define IWN_RFCFG_STEP(x) (((x) >> 2) & 0x3) 1861 #define IWN_RFCFG_DASH(x) (((x) >> 4) & 0x3) 1862 #define IWN_RFCFG_TXANTMSK(x) (((x) >> 8) & 0xf) 1863 #define IWN_RFCFG_RXANTMSK(x) (((x) >> 12) & 0xf) 1864 1865 struct iwn_eeprom_chan { 1866 uint8_t flags; 1867 #define IWN_EEPROM_CHAN_VALID (1 << 0) 1868 #define IWN_EEPROM_CHAN_IBSS (1 << 1) 1869 #define IWN_EEPROM_CHAN_ACTIVE (1 << 3) 1870 #define IWN_EEPROM_CHAN_RADAR (1 << 4) 1871 1872 int8_t maxpwr; 1873 } __packed; 1874 1875 struct iwn_eeprom_enhinfo { 1876 uint8_t flags; 1877 #define IWN_ENHINFO_VALID 0x01 1878 #define IWN_ENHINFO_5GHZ 0x02 1879 #define IWN_ENHINFO_OFDM 0x04 1880 #define IWN_ENHINFO_HT40 0x08 1881 #define IWN_ENHINFO_HTAP 0x10 1882 #define IWN_ENHINFO_RES1 0x20 1883 #define IWN_ENHINFO_RES2 0x40 1884 #define IWN_ENHINFO_COMMON 0x80 1885 1886 uint8_t chan; 1887 int8_t chain[3]; /* max power in half-dBm */ 1888 uint8_t reserved; 1889 int8_t mimo2; /* max power in half-dBm */ 1890 int8_t mimo3; /* max power in half-dBm */ 1891 } __packed; 1892 1893 struct iwn5000_eeprom_calib_hdr { 1894 uint8_t version; 1895 uint8_t pa_type; 1896 uint16_t volt; 1897 } __packed; 1898 1899 #define IWN_NSAMPLES 3 1900 struct iwn4965_eeprom_chan_samples { 1901 uint8_t num; 1902 struct { 1903 uint8_t temp; 1904 uint8_t gain; 1905 uint8_t power; 1906 int8_t pa_det; 1907 } samples[2][IWN_NSAMPLES]; 1908 } __packed; 1909 1910 #define IWN_NBANDS 8 1911 struct iwn4965_eeprom_band { 1912 uint8_t lo; /* low channel number */ 1913 uint8_t hi; /* high channel number */ 1914 struct iwn4965_eeprom_chan_samples chans[2]; 1915 } __packed; 1916 1917 /* 1918 * Offsets of channels descriptions in EEPROM. 1919 */ 1920 static const uint32_t iwn4965_regulatory_bands[IWN_NBANDS] = { 1921 IWN4965_EEPROM_BAND1, 1922 IWN4965_EEPROM_BAND2, 1923 IWN4965_EEPROM_BAND3, 1924 IWN4965_EEPROM_BAND4, 1925 IWN4965_EEPROM_BAND5, 1926 IWN4965_EEPROM_BAND6, 1927 IWN4965_EEPROM_BAND7 1928 }; 1929 1930 static const uint32_t iwn5000_regulatory_bands[IWN_NBANDS] = { 1931 IWN5000_EEPROM_BAND1, 1932 IWN5000_EEPROM_BAND2, 1933 IWN5000_EEPROM_BAND3, 1934 IWN5000_EEPROM_BAND4, 1935 IWN5000_EEPROM_BAND5, 1936 IWN5000_EEPROM_BAND6, 1937 IWN5000_EEPROM_BAND7 1938 }; 1939 1940 static const uint32_t iwn6000_regulatory_bands[IWN_NBANDS] = { 1941 IWN5000_EEPROM_BAND1, 1942 IWN5000_EEPROM_BAND2, 1943 IWN5000_EEPROM_BAND3, 1944 IWN5000_EEPROM_BAND4, 1945 IWN5000_EEPROM_BAND5, 1946 IWN6000_EEPROM_BAND6, 1947 IWN5000_EEPROM_BAND7 1948 }; 1949 1950 static const uint32_t iwn1000_regulatory_bands[IWN_NBANDS] = { 1951 IWN5000_EEPROM_BAND1, 1952 IWN5000_EEPROM_BAND2, 1953 IWN5000_EEPROM_BAND3, 1954 IWN5000_EEPROM_BAND4, 1955 IWN5000_EEPROM_BAND5, 1956 IWN5000_EEPROM_BAND6, 1957 IWN5000_EEPROM_NO_HT40, 1958 }; 1959 1960 static const uint32_t iwn2030_regulatory_bands[IWN_NBANDS] = { 1961 IWN5000_EEPROM_BAND1, 1962 IWN5000_EEPROM_BAND2, 1963 IWN5000_EEPROM_BAND3, 1964 IWN5000_EEPROM_BAND4, 1965 IWN5000_EEPROM_BAND5, 1966 IWN6000_EEPROM_BAND6, 1967 IWN5000_EEPROM_BAND7 1968 }; 1969 1970 #define IWN_CHAN_BANDS_COUNT 7 1971 #define IWN_MAX_CHAN_PER_BAND 14 1972 static const struct iwn_chan_band { 1973 uint8_t nchan; 1974 uint8_t chan[IWN_MAX_CHAN_PER_BAND]; 1975 } iwn_bands[] = { 1976 /* 20MHz channels, 2GHz band. */ 1977 { 14, { 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14 } }, 1978 /* 20MHz channels, 5GHz band. */ 1979 { 13, { 183, 184, 185, 187, 188, 189, 192, 196, 7, 8, 11, 12, 16 } }, 1980 { 12, { 34, 36, 38, 40, 42, 44, 46, 48, 52, 56, 60, 64 } }, 1981 { 11, { 100, 104, 108, 112, 116, 120, 124, 128, 132, 136, 140 } }, 1982 { 6, { 145, 149, 153, 157, 161, 165 } }, 1983 /* 40MHz channels (primary channels), 2GHz band. */ 1984 { 7, { 1, 2, 3, 4, 5, 6, 7 } }, 1985 /* 40MHz channels (primary channels), 5GHz band. */ 1986 { 11, { 36, 44, 52, 60, 100, 108, 116, 124, 132, 149, 157 } } 1987 }; 1988 1989 static const uint8_t iwn_bss_ac_to_queue[] = { 1990 2, 3, 1, 0, 1991 }; 1992 1993 static const uint8_t iwn_pan_ac_to_queue[] = { 1994 5, 4, 6, 7, 1995 }; 1996 #define IWN1000_OTP_NBLOCKS 3 1997 #define IWN6000_OTP_NBLOCKS 4 1998 #define IWN6050_OTP_NBLOCKS 7 1999 2000 /* HW rate indices. */ 2001 #define IWN_RIDX_CCK1 0 2002 #define IWN_RIDX_OFDM6 4 2003 2004 #define IWN4965_MAX_PWR_INDEX 107 2005 #define IWN_POWERSAVE_LVL_NONE 0 2006 #define IWN_POWERSAVE_LVL_VOIP_COMPATIBLE 1 2007 #define IWN_POWERSAVE_LVL_MAX 5 2008 2009 #define IWN_POWERSAVE_LVL_DEFAULT IWN_POWERSAVE_LVL_NONE 2010 2011 /* DTIM value to pass in for IWN_POWERSAVE_LVL_VOIP_COMPATIBLE */ 2012 #define IWN_POWERSAVE_DTIM_VOIP_COMPATIBLE 2 2013 2014 /* 2015 * RF Tx gain values from highest to lowest power (values obtained from 2016 * the reference driver.) 2017 */ 2018 static const uint8_t iwn4965_rf_gain_2ghz[IWN4965_MAX_PWR_INDEX + 1] = { 2019 0x3f, 0x3f, 0x3f, 0x3e, 0x3e, 0x3e, 0x3d, 0x3d, 0x3d, 0x3c, 0x3c, 2020 0x3c, 0x3b, 0x3b, 0x3b, 0x3a, 0x3a, 0x3a, 0x39, 0x39, 0x39, 0x38, 2021 0x38, 0x38, 0x37, 0x37, 0x37, 0x36, 0x36, 0x36, 0x35, 0x35, 0x35, 2022 0x34, 0x34, 0x34, 0x33, 0x33, 0x33, 0x32, 0x32, 0x32, 0x31, 0x31, 2023 0x31, 0x30, 0x30, 0x30, 0x06, 0x06, 0x06, 0x05, 0x05, 0x05, 0x04, 2024 0x04, 0x04, 0x03, 0x03, 0x03, 0x02, 0x02, 0x02, 0x01, 0x01, 0x01, 2025 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 2026 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 2027 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 2028 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 2029 }; 2030 2031 static const uint8_t iwn4965_rf_gain_5ghz[IWN4965_MAX_PWR_INDEX + 1] = { 2032 0x3f, 0x3f, 0x3f, 0x3f, 0x3f, 0x3e, 0x3e, 0x3e, 0x3d, 0x3d, 0x3d, 2033 0x3c, 0x3c, 0x3c, 0x3b, 0x3b, 0x3b, 0x3a, 0x3a, 0x3a, 0x39, 0x39, 2034 0x39, 0x38, 0x38, 0x38, 0x37, 0x37, 0x37, 0x36, 0x36, 0x36, 0x35, 2035 0x35, 0x35, 0x34, 0x34, 0x34, 0x33, 0x33, 0x33, 0x32, 0x32, 0x32, 2036 0x31, 0x31, 0x31, 0x30, 0x30, 0x30, 0x25, 0x25, 0x25, 0x24, 0x24, 2037 0x24, 0x23, 0x23, 0x23, 0x22, 0x18, 0x18, 0x17, 0x17, 0x17, 0x16, 2038 0x16, 0x16, 0x15, 0x15, 0x15, 0x14, 0x14, 0x14, 0x13, 0x13, 0x13, 2039 0x12, 0x08, 0x08, 0x07, 0x07, 0x07, 0x06, 0x06, 0x06, 0x05, 0x05, 2040 0x05, 0x04, 0x04, 0x04, 0x03, 0x03, 0x03, 0x02, 0x02, 0x02, 0x01, 2041 0x01, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 2042 }; 2043 2044 /* 2045 * DSP pre-DAC gain values from highest to lowest power (values obtained 2046 * from the reference driver.) 2047 */ 2048 static const uint8_t iwn4965_dsp_gain_2ghz[IWN4965_MAX_PWR_INDEX + 1] = { 2049 0x6e, 0x68, 0x62, 0x6e, 0x68, 0x62, 0x6e, 0x68, 0x62, 0x6e, 0x68, 2050 0x62, 0x6e, 0x68, 0x62, 0x6e, 0x68, 0x62, 0x6e, 0x68, 0x62, 0x6e, 2051 0x68, 0x62, 0x6e, 0x68, 0x62, 0x6e, 0x68, 0x62, 0x6e, 0x68, 0x62, 2052 0x6e, 0x68, 0x62, 0x6e, 0x68, 0x62, 0x6e, 0x68, 0x62, 0x6e, 0x68, 2053 0x62, 0x6e, 0x68, 0x62, 0x6e, 0x68, 0x62, 0x6e, 0x68, 0x62, 0x6e, 2054 0x68, 0x62, 0x6e, 0x68, 0x62, 0x6e, 0x68, 0x62, 0x6e, 0x68, 0x62, 2055 0x6e, 0x68, 0x62, 0x61, 0x60, 0x5f, 0x5e, 0x5d, 0x5c, 0x5b, 0x5a, 2056 0x59, 0x58, 0x57, 0x56, 0x55, 0x54, 0x53, 0x52, 0x51, 0x50, 0x4f, 2057 0x4e, 0x4d, 0x4c, 0x4b, 0x4a, 0x49, 0x48, 0x47, 0x46, 0x45, 0x44, 2058 0x43, 0x42, 0x41, 0x40, 0x3f, 0x3e, 0x3d, 0x3c, 0x3b 2059 }; 2060 2061 static const uint8_t iwn4965_dsp_gain_5ghz[IWN4965_MAX_PWR_INDEX + 1] = { 2062 0x7b, 0x75, 0x6e, 0x68, 0x62, 0x6e, 0x68, 0x62, 0x6e, 0x68, 0x62, 2063 0x6e, 0x68, 0x62, 0x6e, 0x68, 0x62, 0x6e, 0x68, 0x62, 0x6e, 0x68, 2064 0x62, 0x6e, 0x68, 0x62, 0x6e, 0x68, 0x62, 0x6e, 0x68, 0x62, 0x6e, 2065 0x68, 0x62, 0x6e, 0x68, 0x62, 0x6e, 0x68, 0x62, 0x6e, 0x68, 0x62, 2066 0x6e, 0x68, 0x62, 0x6e, 0x68, 0x62, 0x6e, 0x68, 0x62, 0x6e, 0x68, 2067 0x62, 0x6e, 0x68, 0x62, 0x6e, 0x68, 0x62, 0x6e, 0x68, 0x62, 0x6e, 2068 0x68, 0x62, 0x6e, 0x68, 0x62, 0x6e, 0x68, 0x62, 0x6e, 0x68, 0x62, 2069 0x6e, 0x68, 0x62, 0x6e, 0x68, 0x62, 0x6e, 0x68, 0x62, 0x6e, 0x68, 2070 0x62, 0x6e, 0x68, 0x62, 0x6e, 0x68, 0x62, 0x6e, 0x68, 0x62, 0x6e, 2071 0x68, 0x62, 0x6e, 0x68, 0x62, 0x5d, 0x58, 0x53, 0x4e 2072 }; 2073 2074 /* 2075 * Power saving settings (values obtained from the reference driver.) 2076 */ 2077 #define IWN_NDTIMRANGES 3 2078 #define IWN_NPOWERLEVELS 6 2079 static const struct iwn_pmgt { 2080 uint32_t rxtimeout; 2081 uint32_t txtimeout; 2082 uint32_t intval[5]; 2083 int skip_dtim; 2084 } iwn_pmgt[IWN_NDTIMRANGES][IWN_NPOWERLEVELS] = { 2085 /* DTIM <= 2 */ 2086 { 2087 { 0, 0, { 0, 0, 0, 0, 0 }, 0 }, /* CAM */ 2088 { 200, 500, { 1, 2, 2, 2, -1 }, 0 }, /* PS level 1 */ 2089 { 200, 300, { 1, 2, 2, 2, -1 }, 0 }, /* PS level 2 */ 2090 { 50, 100, { 2, 2, 2, 2, -1 }, 0 }, /* PS level 3 */ 2091 { 50, 25, { 2, 2, 4, 4, -1 }, 1 }, /* PS level 4 */ 2092 { 25, 25, { 2, 2, 4, 6, -1 }, 2 } /* PS level 5 */ 2093 }, 2094 /* 3 <= DTIM <= 10 */ 2095 { 2096 { 0, 0, { 0, 0, 0, 0, 0 }, 0 }, /* CAM */ 2097 { 200, 500, { 1, 2, 3, 4, 4 }, 0 }, /* PS level 1 */ 2098 { 200, 300, { 1, 2, 3, 4, 7 }, 0 }, /* PS level 2 */ 2099 { 50, 100, { 2, 4, 6, 7, 9 }, 0 }, /* PS level 3 */ 2100 { 50, 25, { 2, 4, 6, 9, 10 }, 1 }, /* PS level 4 */ 2101 { 25, 25, { 2, 4, 7, 10, 10 }, 2 } /* PS level 5 */ 2102 }, 2103 /* DTIM >= 11 */ 2104 { 2105 { 0, 0, { 0, 0, 0, 0, 0 }, 0 }, /* CAM */ 2106 { 200, 500, { 1, 2, 3, 4, -1 }, 0 }, /* PS level 1 */ 2107 { 200, 300, { 2, 4, 6, 7, -1 }, 0 }, /* PS level 2 */ 2108 { 50, 100, { 2, 7, 9, 9, -1 }, 0 }, /* PS level 3 */ 2109 { 50, 25, { 2, 7, 9, 9, -1 }, 0 }, /* PS level 4 */ 2110 { 25, 25, { 4, 7, 10, 10, -1 }, 0 } /* PS level 5 */ 2111 } 2112 }; 2113 2114 struct iwn_sensitivity_limits { 2115 uint32_t min_ofdm_x1; 2116 uint32_t max_ofdm_x1; 2117 uint32_t min_ofdm_mrc_x1; 2118 uint32_t max_ofdm_mrc_x1; 2119 uint32_t min_ofdm_x4; 2120 uint32_t max_ofdm_x4; 2121 uint32_t min_ofdm_mrc_x4; 2122 uint32_t max_ofdm_mrc_x4; 2123 uint32_t min_cck_x4; 2124 uint32_t max_cck_x4; 2125 uint32_t min_cck_mrc_x4; 2126 uint32_t max_cck_mrc_x4; 2127 uint32_t min_energy_cck; 2128 uint32_t energy_cck; 2129 uint32_t energy_ofdm; 2130 uint32_t barker_mrc; 2131 }; 2132 2133 /* 2134 * RX sensitivity limits (values obtained from the reference driver.) 2135 */ 2136 static const struct iwn_sensitivity_limits iwn4965_sensitivity_limits = { 2137 105, 140, 2138 220, 270, 2139 85, 120, 2140 170, 210, 2141 125, 200, 2142 200, 400, 2143 97, 2144 100, 2145 100, 2146 390 2147 }; 2148 2149 static const struct iwn_sensitivity_limits iwn5000_sensitivity_limits = { 2150 120, 120, /* min = max for performance bug in DSP. */ 2151 240, 240, /* min = max for performance bug in DSP. */ 2152 90, 120, 2153 170, 210, 2154 125, 200, 2155 170, 400, 2156 95, 2157 95, 2158 95, 2159 390 2160 }; 2161 2162 static const struct iwn_sensitivity_limits iwn5150_sensitivity_limits = { 2163 105, 105, /* min = max for performance bug in DSP. */ 2164 220, 220, /* min = max for performance bug in DSP. */ 2165 90, 120, 2166 170, 210, 2167 125, 200, 2168 170, 400, 2169 95, 2170 95, 2171 95, 2172 390, 2173 }; 2174 2175 static const struct iwn_sensitivity_limits iwn1000_sensitivity_limits = { 2176 120, 155, 2177 240, 290, 2178 90, 120, 2179 170, 210, 2180 125, 200, 2181 170, 400, 2182 95, 2183 95, 2184 95, 2185 390, 2186 }; 2187 2188 static const struct iwn_sensitivity_limits iwn6000_sensitivity_limits = { 2189 105, 110, 2190 192, 232, 2191 80, 145, 2192 128, 232, 2193 125, 175, 2194 160, 310, 2195 97, 2196 97, 2197 100, 2198 390 2199 }; 2200 2201 static const struct iwn_sensitivity_limits iwn6235_sensitivity_limits = { 2202 105, 110, 2203 192, 232, 2204 80, 145, 2205 128, 232, 2206 125, 175, 2207 160, 310, 2208 100, 2209 110, 2210 110, 2211 336 2212 }; 2213 2214 2215 /* Get value from linux kernel 3.2.+ in Drivers/net/wireless/iwlwifi/iwl-2000.c*/ 2216 static const struct iwn_sensitivity_limits iwn2030_sensitivity_limits = { 2217 105,110, 2218 128,232, 2219 80,145, 2220 128,232, 2221 125,175, 2222 160,310, 2223 97, 2224 97, 2225 110 2226 }; 2227 2228 /* Map TID to TX scheduler's FIFO. */ 2229 static const uint8_t iwn_tid2fifo[] = { 2230 1, 0, 0, 1, 2, 2, 3, 3, 7, 7, 7, 7, 7, 7, 7, 7, 3 2231 }; 2232 2233 /* WiFi/WiMAX coexist event priority table for 6050. */ 2234 static const struct iwn5000_wimax_event iwn6050_wimax_events[] = { 2235 { 0x04, 0x03, 0x00, 0x00 }, 2236 { 0x04, 0x03, 0x00, 0x03 }, 2237 { 0x04, 0x03, 0x00, 0x03 }, 2238 { 0x04, 0x03, 0x00, 0x03 }, 2239 { 0x04, 0x03, 0x00, 0x00 }, 2240 { 0x04, 0x03, 0x00, 0x07 }, 2241 { 0x04, 0x03, 0x00, 0x00 }, 2242 { 0x04, 0x03, 0x00, 0x03 }, 2243 { 0x04, 0x03, 0x00, 0x03 }, 2244 { 0x04, 0x03, 0x00, 0x00 }, 2245 { 0x06, 0x03, 0x00, 0x07 }, 2246 { 0x04, 0x03, 0x00, 0x00 }, 2247 { 0x06, 0x06, 0x00, 0x03 }, 2248 { 0x04, 0x03, 0x00, 0x07 }, 2249 { 0x04, 0x03, 0x00, 0x00 }, 2250 { 0x04, 0x03, 0x00, 0x00 } 2251 }; 2252 2253 /* Firmware errors. */ 2254 static const char * const iwn_fw_errmsg[] = { 2255 "OK", 2256 "FAIL", 2257 "BAD_PARAM", 2258 "BAD_CHECKSUM", 2259 "NMI_INTERRUPT_WDG", 2260 "SYSASSERT", 2261 "FATAL_ERROR", 2262 "BAD_COMMAND", 2263 "HW_ERROR_TUNE_LOCK", 2264 "HW_ERROR_TEMPERATURE", 2265 "ILLEGAL_CHAN_FREQ", 2266 "VCC_NOT_STABLE", 2267 "FH_ERROR", 2268 "NMI_INTERRUPT_HOST", 2269 "NMI_INTERRUPT_ACTION_PT", 2270 "NMI_INTERRUPT_UNKNOWN", 2271 "UCODE_VERSION_MISMATCH", 2272 "HW_ERROR_ABS_LOCK", 2273 "HW_ERROR_CAL_LOCK_FAIL", 2274 "NMI_INTERRUPT_INST_ACTION_PT", 2275 "NMI_INTERRUPT_DATA_ACTION_PT", 2276 "NMI_TRM_HW_ER", 2277 "NMI_INTERRUPT_TRM", 2278 "NMI_INTERRUPT_BREAKPOINT", 2279 "DEBUG_0", 2280 "DEBUG_1", 2281 "DEBUG_2", 2282 "DEBUG_3", 2283 "ADVANCED_SYSASSERT" 2284 }; 2285 2286 /* Find least significant bit that is set. */ 2287 #define IWN_LSB(x) ((((x) - 1) & (x)) ^ (x)) 2288 2289 #define IWN_READ(sc, reg) \ 2290 bus_space_read_4((sc)->sc_st, (sc)->sc_sh, (reg)) 2291 2292 #define IWN_WRITE(sc, reg, val) \ 2293 bus_space_write_4((sc)->sc_st, (sc)->sc_sh, (reg), (val)) 2294 2295 #define IWN_WRITE_1(sc, reg, val) \ 2296 bus_space_write_1((sc)->sc_st, (sc)->sc_sh, (reg), (val)) 2297 2298 #define IWN_SETBITS(sc, reg, mask) \ 2299 IWN_WRITE(sc, reg, IWN_READ(sc, reg) | (mask)) 2300 2301 #define IWN_CLRBITS(sc, reg, mask) \ 2302 IWN_WRITE(sc, reg, IWN_READ(sc, reg) & ~(mask)) 2303 2304 #define IWN_BARRIER_WRITE(sc) \ 2305 bus_space_barrier((sc)->sc_st, (sc)->sc_sh, 0, (sc)->sc_sz, \ 2306 BUS_SPACE_BARRIER_WRITE) 2307 2308 #define IWN_BARRIER_READ_WRITE(sc) \ 2309 bus_space_barrier((sc)->sc_st, (sc)->sc_sh, 0, (sc)->sc_sz, \ 2310 BUS_SPACE_BARRIER_READ | BUS_SPACE_BARRIER_WRITE) 2311 2312 #endif /* __IF_IWNREG_H__ */ 2313