1 /* $FreeBSD$ */ 2 /* $OpenBSD: if_iwnreg.h,v 1.34 2009/11/08 11:54:48 damien Exp $ */ 3 4 /*- 5 * Copyright (c) 2007, 2008 6 * Damien Bergamini <damien.bergamini@free.fr> 7 * 8 * Permission to use, copy, modify, and distribute this software for any 9 * purpose with or without fee is hereby granted, provided that the above 10 * copyright notice and this permission notice appear in all copies. 11 * 12 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 13 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 14 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR 15 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 16 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN 17 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF 18 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 19 */ 20 21 #define IWN_TX_RING_COUNT 256 22 #define IWN_TX_RING_LOMARK 192 23 #define IWN_TX_RING_HIMARK 224 24 #define IWN_RX_RING_COUNT_LOG 6 25 #define IWN_RX_RING_COUNT (1 << IWN_RX_RING_COUNT_LOG) 26 27 #define IWN4965_NTXQUEUES 16 28 #define IWN5000_NTXQUEUES 20 29 30 #define IWN4965_NDMACHNLS 7 31 #define IWN5000_NDMACHNLS 8 32 33 #define IWN_SRVC_DMACHNL 9 34 35 #define IWN_ICT_SIZE 4096 36 #define IWN_ICT_COUNT (IWN_ICT_SIZE / sizeof (uint32_t)) 37 38 /* Maximum number of DMA segments for TX. */ 39 #define IWN_MAX_SCATTER 20 40 41 /* RX buffers must be large enough to hold a full 4K A-MPDU. */ 42 #define IWN_RBUF_SIZE (4 * 1024) 43 44 #if defined(__LP64__) 45 /* HW supports 36-bit DMA addresses. */ 46 #define IWN_LOADDR(paddr) ((uint32_t)(paddr)) 47 #define IWN_HIADDR(paddr) (((paddr) >> 32) & 0xf) 48 #else 49 #define IWN_LOADDR(paddr) (paddr) 50 #define IWN_HIADDR(paddr) (0) 51 #endif 52 53 /* Base Address Register. */ 54 #define IWN_PCI_BAR0 PCI_MAPREG_START 55 56 /* 57 * Control and status registers. 58 */ 59 #define IWN_HW_IF_CONFIG 0x000 60 #define IWN_INT_COALESCING 0x004 61 #define IWN_INT_PERIODIC 0x005 /* use IWN_WRITE_1 */ 62 #define IWN_INT 0x008 63 #define IWN_INT_MASK 0x00c 64 #define IWN_FH_INT 0x010 65 #define IWN_RESET 0x020 66 #define IWN_GP_CNTRL 0x024 67 #define IWN_HW_REV 0x028 68 #define IWN_EEPROM 0x02c 69 #define IWN_EEPROM_GP 0x030 70 #define IWN_OTP_GP 0x034 71 #define IWN_GIO 0x03c 72 #define IWN_GP_DRIVER 0x050 73 #define IWN_UCODE_GP1_CLR 0x05c 74 #define IWN_LED 0x094 75 #define IWN_DRAM_INT_TBL 0x0a0 76 #define IWN_GIO_CHICKEN 0x100 77 #define IWN_ANA_PLL 0x20c 78 #define IWN_HW_REV_WA 0x22c 79 #define IWN_DBG_HPET_MEM 0x240 80 #define IWN_DBG_LINK_PWR_MGMT 0x250 81 #define IWN_MEM_RADDR 0x40c 82 #define IWN_MEM_WADDR 0x410 83 #define IWN_MEM_WDATA 0x418 84 #define IWN_MEM_RDATA 0x41c 85 #define IWN_PRPH_WADDR 0x444 86 #define IWN_PRPH_RADDR 0x448 87 #define IWN_PRPH_WDATA 0x44c 88 #define IWN_PRPH_RDATA 0x450 89 #define IWN_HBUS_TARG_WRPTR 0x460 90 91 /* 92 * Flow-Handler registers. 93 */ 94 #define IWN_FH_TFBD_CTRL0(qid) (0x1900 + (qid) * 8) 95 #define IWN_FH_TFBD_CTRL1(qid) (0x1904 + (qid) * 8) 96 #define IWN_FH_KW_ADDR 0x197c 97 #define IWN_FH_SRAM_ADDR(qid) (0x19a4 + (qid) * 4) 98 #define IWN_FH_CBBC_QUEUE(qid) (0x19d0 + (qid) * 4) 99 #define IWN_FH_STATUS_WPTR 0x1bc0 100 #define IWN_FH_RX_BASE 0x1bc4 101 #define IWN_FH_RX_WPTR 0x1bc8 102 #define IWN_FH_RX_CONFIG 0x1c00 103 #define IWN_FH_RX_STATUS 0x1c44 104 #define IWN_FH_TX_CONFIG(qid) (0x1d00 + (qid) * 32) 105 #define IWN_FH_TXBUF_STATUS(qid) (0x1d08 + (qid) * 32) 106 #define IWN_FH_TX_CHICKEN 0x1e98 107 #define IWN_FH_TX_STATUS 0x1eb0 108 109 /* 110 * TX scheduler registers. 111 */ 112 #define IWN_SCHED_BASE 0xa02c00 113 #define IWN_SCHED_SRAM_ADDR (IWN_SCHED_BASE + 0x000) 114 #define IWN5000_SCHED_DRAM_ADDR (IWN_SCHED_BASE + 0x008) 115 #define IWN4965_SCHED_DRAM_ADDR (IWN_SCHED_BASE + 0x010) 116 #define IWN5000_SCHED_TXFACT (IWN_SCHED_BASE + 0x010) 117 #define IWN4965_SCHED_TXFACT (IWN_SCHED_BASE + 0x01c) 118 #define IWN4965_SCHED_QUEUE_RDPTR(qid) (IWN_SCHED_BASE + 0x064 + (qid) * 4) 119 #define IWN5000_SCHED_QUEUE_RDPTR(qid) (IWN_SCHED_BASE + 0x068 + (qid) * 4) 120 #define IWN4965_SCHED_QCHAIN_SEL (IWN_SCHED_BASE + 0x0d0) 121 #define IWN4965_SCHED_INTR_MASK (IWN_SCHED_BASE + 0x0e4) 122 #define IWN5000_SCHED_QCHAIN_SEL (IWN_SCHED_BASE + 0x0e8) 123 #define IWN4965_SCHED_QUEUE_STATUS(qid) (IWN_SCHED_BASE + 0x104 + (qid) * 4) 124 #define IWN5000_SCHED_INTR_MASK (IWN_SCHED_BASE + 0x108) 125 #define IWN5000_SCHED_QUEUE_STATUS(qid) (IWN_SCHED_BASE + 0x10c + (qid) * 4) 126 #define IWN5000_SCHED_AGGR_SEL (IWN_SCHED_BASE + 0x248) 127 128 /* 129 * Offsets in TX scheduler's SRAM. 130 */ 131 #define IWN4965_SCHED_CTX_OFF 0x380 132 #define IWN4965_SCHED_CTX_LEN 416 133 #define IWN4965_SCHED_QUEUE_OFFSET(qid) (0x380 + (qid) * 8) 134 #define IWN4965_SCHED_TRANS_TBL(qid) (0x500 + (qid) * 2) 135 #define IWN5000_SCHED_CTX_OFF 0x600 136 #define IWN5000_SCHED_CTX_LEN 520 137 #define IWN5000_SCHED_QUEUE_OFFSET(qid) (0x600 + (qid) * 8) 138 #define IWN5000_SCHED_TRANS_TBL(qid) (0x7e0 + (qid) * 2) 139 140 /* 141 * NIC internal memory offsets. 142 */ 143 #define IWN_APMG_CLK_CTRL 0x3000 144 #define IWN_APMG_CLK_EN 0x3004 145 #define IWN_APMG_CLK_DIS 0x3008 146 #define IWN_APMG_PS 0x300c 147 #define IWN_APMG_DIGITAL_SVR 0x3058 148 #define IWN_APMG_ANALOG_SVR 0x306c 149 #define IWN_APMG_PCI_STT 0x3010 150 #define IWN_BSM_WR_CTRL 0x3400 151 #define IWN_BSM_WR_MEM_SRC 0x3404 152 #define IWN_BSM_WR_MEM_DST 0x3408 153 #define IWN_BSM_WR_DWCOUNT 0x340c 154 #define IWN_BSM_DRAM_TEXT_ADDR 0x3490 155 #define IWN_BSM_DRAM_TEXT_SIZE 0x3494 156 #define IWN_BSM_DRAM_DATA_ADDR 0x3498 157 #define IWN_BSM_DRAM_DATA_SIZE 0x349c 158 #define IWN_BSM_SRAM_BASE 0x3800 159 160 /* Possible flags for register IWN_HW_IF_CONFIG. */ 161 #define IWN_HW_IF_CONFIG_4965_R (1 << 4) 162 #define IWN_HW_IF_CONFIG_MAC_SI (1 << 8) 163 #define IWN_HW_IF_CONFIG_RADIO_SI (1 << 9) 164 #define IWN_HW_IF_CONFIG_EEPROM_LOCKED (1 << 21) 165 #define IWN_HW_IF_CONFIG_NIC_READY (1 << 22) 166 #define IWN_HW_IF_CONFIG_HAP_WAKE_L1A (1 << 23) 167 #define IWN_HW_IF_CONFIG_PREPARE_DONE (1 << 25) 168 #define IWN_HW_IF_CONFIG_PREPARE (1 << 27) 169 170 /* Possible values for register IWN_INT_PERIODIC. */ 171 #define IWN_INT_PERIODIC_DIS 0x00 172 #define IWN_INT_PERIODIC_ENA 0xff 173 174 /* Possible flags for registers IWN_PRPH_RADDR/IWN_PRPH_WADDR. */ 175 #define IWN_PRPH_DWORD ((sizeof (uint32_t) - 1) << 24) 176 177 /* Possible values for IWN_BSM_WR_MEM_DST. */ 178 #define IWN_FW_TEXT_BASE 0x00000000 179 #define IWN_FW_DATA_BASE 0x00800000 180 181 /* Possible flags for register IWN_RESET. */ 182 #define IWN_RESET_NEVO (1 << 0) 183 #define IWN_RESET_SW (1 << 7) 184 #define IWN_RESET_MASTER_DISABLED (1 << 8) 185 #define IWN_RESET_STOP_MASTER (1 << 9) 186 #define IWN_RESET_LINK_PWR_MGMT_DIS (1 << 31) 187 188 /* Possible flags for register IWN_GP_CNTRL. */ 189 #define IWN_GP_CNTRL_MAC_ACCESS_ENA (1 << 0) 190 #define IWN_GP_CNTRL_MAC_CLOCK_READY (1 << 0) 191 #define IWN_GP_CNTRL_INIT_DONE (1 << 2) 192 #define IWN_GP_CNTRL_MAC_ACCESS_REQ (1 << 3) 193 #define IWN_GP_CNTRL_SLEEP (1 << 4) 194 #define IWN_GP_CNTRL_RFKILL (1 << 27) 195 196 /* Possible flags for register IWN_HW_REV. */ 197 #define IWN_HW_REV_TYPE_SHIFT 4 198 #define IWN_HW_REV_TYPE_MASK 0x000000f0 199 #define IWN_HW_REV_TYPE_4965 0 200 #define IWN_HW_REV_TYPE_5300 2 201 #define IWN_HW_REV_TYPE_5350 3 202 #define IWN_HW_REV_TYPE_5150 4 203 #define IWN_HW_REV_TYPE_5100 5 204 #define IWN_HW_REV_TYPE_1000 6 205 #define IWN_HW_REV_TYPE_6000 7 206 #define IWN_HW_REV_TYPE_6050 8 207 208 /* Possible flags for register IWN_GIO_CHICKEN. */ 209 #define IWN_GIO_CHICKEN_L1A_NO_L0S_RX (1 << 23) 210 #define IWN_GIO_CHICKEN_DIS_L0S_TIMER (1 << 29) 211 212 /* Possible flags for register IWN_GIO. */ 213 #define IWN_GIO_L0S_ENA (1 << 1) 214 215 /* Possible flags for register IWN_GP_DRIVER. */ 216 #define IWN_GP_DRIVER_RADIO_3X3_HYB (0 << 0) 217 #define IWN_GP_DRIVER_RADIO_2X2_HYB (1 << 0) 218 #define IWN_GP_DRIVER_RADIO_2X2_IPA (2 << 0) 219 220 /* Possible flags for register IWN_UCODE_GP1_CLR. */ 221 #define IWN_UCODE_GP1_RFKILL (1 << 1) 222 #define IWN_UCODE_GP1_CMD_BLOCKED (1 << 2) 223 #define IWN_UCODE_GP1_CTEMP_STOP_RF (1 << 3) 224 225 /* Possible flags/values for register IWN_LED. */ 226 #define IWN_LED_BSM_CTRL (1 << 5) 227 #define IWN_LED_OFF 0x00000038 228 #define IWN_LED_ON 0x00000078 229 230 /* Possible flags for register IWN_DRAM_INT_TBL. */ 231 #define IWN_DRAM_INT_TBL_WRAP_CHECK (1 << 27) 232 #define IWN_DRAM_INT_TBL_ENABLE (1 << 31) 233 234 /* Possible values for register IWN_ANA_PLL. */ 235 #define IWN_ANA_PLL_INIT 0x00880300 236 237 /* Possible flags for register IWN_FH_RX_STATUS. */ 238 #define IWN_FH_RX_STATUS_IDLE (1 << 24) 239 240 /* Possible flags for register IWN_BSM_WR_CTRL. */ 241 #define IWN_BSM_WR_CTRL_START_EN (1 << 30) 242 #define IWN_BSM_WR_CTRL_START (1 << 31) 243 244 /* Possible flags for register IWN_INT. */ 245 #define IWN_INT_ALIVE (1 << 0) 246 #define IWN_INT_WAKEUP (1 << 1) 247 #define IWN_INT_SW_RX (1 << 3) 248 #define IWN_INT_CT_REACHED (1 << 6) 249 #define IWN_INT_RF_TOGGLED (1 << 7) 250 #define IWN_INT_SW_ERR (1 << 25) 251 #define IWN_INT_SCHED (1 << 26) 252 #define IWN_INT_FH_TX (1 << 27) 253 #define IWN_INT_RX_PERIODIC (1 << 28) 254 #define IWN_INT_HW_ERR (1 << 29) 255 #define IWN_INT_FH_RX (1 << 31) 256 257 /* Shortcut. */ 258 #define IWN_INT_MASK_DEF \ 259 (IWN_INT_SW_ERR | IWN_INT_HW_ERR | IWN_INT_FH_TX | \ 260 IWN_INT_FH_RX | IWN_INT_ALIVE | IWN_INT_WAKEUP | \ 261 IWN_INT_SW_RX | IWN_INT_CT_REACHED | IWN_INT_RF_TOGGLED) 262 263 /* Possible flags for register IWN_FH_INT. */ 264 #define IWN_FH_INT_TX_CHNL(x) (1 << (x)) 265 #define IWN_FH_INT_RX_CHNL(x) (1 << ((x) + 16)) 266 #define IWN_FH_INT_HI_PRIOR (1 << 30) 267 /* Shortcuts for the above. */ 268 #define IWN_FH_INT_TX \ 269 (IWN_FH_INT_TX_CHNL(0) | IWN_FH_INT_TX_CHNL(1)) 270 #define IWN_FH_INT_RX \ 271 (IWN_FH_INT_RX_CHNL(0) | IWN_FH_INT_RX_CHNL(1) | IWN_FH_INT_HI_PRIOR) 272 273 /* Possible flags/values for register IWN_FH_TX_CONFIG. */ 274 #define IWN_FH_TX_CONFIG_DMA_PAUSE 0 275 #define IWN_FH_TX_CONFIG_DMA_ENA (1 << 31) 276 #define IWN_FH_TX_CONFIG_CIRQ_HOST_ENDTFD (1 << 20) 277 278 /* Possible flags/values for register IWN_FH_TXBUF_STATUS. */ 279 #define IWN_FH_TXBUF_STATUS_TBNUM(x) ((x) << 20) 280 #define IWN_FH_TXBUF_STATUS_TBIDX(x) ((x) << 12) 281 #define IWN_FH_TXBUF_STATUS_TFBD_VALID 3 282 283 /* Possible flags for register IWN_FH_TX_CHICKEN. */ 284 #define IWN_FH_TX_CHICKEN_SCHED_RETRY (1 << 1) 285 286 /* Possible flags for register IWN_FH_TX_STATUS. */ 287 #define IWN_FH_TX_STATUS_IDLE(chnl) \ 288 (1 << ((chnl) + 24) | 1 << ((chnl) + 16)) 289 290 /* Possible flags for register IWN_FH_RX_CONFIG. */ 291 #define IWN_FH_RX_CONFIG_ENA (1 << 31) 292 #define IWN_FH_RX_CONFIG_NRBD(x) ((x) << 20) 293 #define IWN_FH_RX_CONFIG_RB_SIZE_8K (1 << 16) 294 #define IWN_FH_RX_CONFIG_SINGLE_FRAME (1 << 15) 295 #define IWN_FH_RX_CONFIG_IRQ_DST_HOST (1 << 12) 296 #define IWN_FH_RX_CONFIG_RB_TIMEOUT(x) ((x) << 4) 297 #define IWN_FH_RX_CONFIG_IGN_RXF_EMPTY (1 << 2) 298 299 /* Possible flags for register IWN_FH_TX_CONFIG. */ 300 #define IWN_FH_TX_CONFIG_DMA_ENA (1 << 31) 301 #define IWN_FH_TX_CONFIG_DMA_CREDIT_ENA (1 << 3) 302 303 /* Possible flags for register IWN_EEPROM. */ 304 #define IWN_EEPROM_READ_VALID (1 << 0) 305 #define IWN_EEPROM_CMD (1 << 1) 306 307 /* Possible flags for register IWN_EEPROM_GP. */ 308 #define IWN_EEPROM_GP_IF_OWNER 0x00000180 309 310 /* Possible flags for register IWN_OTP_GP. */ 311 #define IWN_OTP_GP_DEV_SEL_OTP (1 << 16) 312 #define IWN_OTP_GP_RELATIVE_ACCESS (1 << 17) 313 #define IWN_OTP_GP_ECC_CORR_STTS (1 << 20) 314 #define IWN_OTP_GP_ECC_UNCORR_STTS (1 << 21) 315 316 /* Possible flags for register IWN_SCHED_QUEUE_STATUS. */ 317 #define IWN4965_TXQ_STATUS_ACTIVE 0x0007fc01 318 #define IWN4965_TXQ_STATUS_INACTIVE 0x0007fc00 319 #define IWN4965_TXQ_STATUS_AGGR_ENA (1 << 5 | 1 << 8) 320 #define IWN4965_TXQ_STATUS_CHGACT (1 << 10) 321 #define IWN5000_TXQ_STATUS_ACTIVE 0x00ff0018 322 #define IWN5000_TXQ_STATUS_INACTIVE 0x00ff0010 323 #define IWN5000_TXQ_STATUS_CHGACT (1 << 19) 324 325 /* Possible flags for registers IWN_APMG_CLK_*. */ 326 #define IWN_APMG_CLK_CTRL_DMA_CLK_RQT (1 << 9) 327 #define IWN_APMG_CLK_CTRL_BSM_CLK_RQT (1 << 11) 328 329 /* Possible flags for register IWN_APMG_PS. */ 330 #define IWN_APMG_PS_EARLY_PWROFF_DIS (1 << 22) 331 #define IWN_APMG_PS_PWR_SRC(x) ((x) << 24) 332 #define IWN_APMG_PS_PWR_SRC_VMAIN 0 333 #define IWN_APMG_PS_PWR_SRC_VAUX 2 334 #define IWN_APMG_PS_PWR_SRC_MASK IWN_APMG_PS_PWR_SRC(3) 335 #define IWN_APMG_PS_RESET_REQ (1 << 26) 336 337 /* Possible flags for register IWN_APMG_DIGITAL_SVR. */ 338 #define IWN_APMG_DIGITAL_SVR_VOLTAGE(x) (((x) & 0xf) << 5) 339 #define IWN_APMG_DIGITAL_SVR_VOLTAGE_MASK \ 340 IWN_APMG_DIGITAL_SVR_VOLTAGE(0xf) 341 #define IWN_APMG_DIGITAL_SVR_VOLTAGE_1_32 \ 342 IWN_APMG_DIGITAL_SVR_VOLTAGE(3) 343 344 /* Possible flags for IWN_APMG_PCI_STT. */ 345 #define IWN_APMG_PCI_STT_L1A_DIS (1 << 11) 346 347 /* Possible flags for register IWN_BSM_DRAM_TEXT_SIZE. */ 348 #define IWN_FW_UPDATED (1 << 31) 349 350 #define IWN_SCHED_WINSZ 64 351 #define IWN_SCHED_LIMIT 64 352 #define IWN4965_SCHED_COUNT 512 353 #define IWN5000_SCHED_COUNT (IWN_TX_RING_COUNT + IWN_SCHED_WINSZ) 354 #define IWN4965_SCHEDSZ (IWN4965_NTXQUEUES * IWN4965_SCHED_COUNT * 2) 355 #define IWN5000_SCHEDSZ (IWN5000_NTXQUEUES * IWN5000_SCHED_COUNT * 2) 356 357 struct iwn_tx_desc { 358 uint8_t reserved1[3]; 359 uint8_t nsegs; 360 struct { 361 uint32_t addr; 362 uint16_t len; 363 } __packed segs[IWN_MAX_SCATTER]; 364 /* Pad to 128 bytes. */ 365 uint32_t reserved2; 366 } __packed; 367 368 struct iwn_rx_status { 369 uint16_t closed_count; 370 uint16_t closed_rx_count; 371 uint16_t finished_count; 372 uint16_t finished_rx_count; 373 uint32_t reserved[2]; 374 } __packed; 375 376 struct iwn_rx_desc { 377 uint32_t len; 378 uint8_t type; 379 #define IWN_UC_READY 1 380 #define IWN_ADD_NODE_DONE 24 381 #define IWN_TX_DONE 28 382 #define IWN5000_CALIBRATION_RESULT 102 383 #define IWN5000_CALIBRATION_DONE 103 384 #define IWN_START_SCAN 130 385 #define IWN_STOP_SCAN 132 386 #define IWN_RX_STATISTICS 156 387 #define IWN_BEACON_STATISTICS 157 388 #define IWN_STATE_CHANGED 161 389 #define IWN_BEACON_MISSED 162 390 #define IWN_RX_PHY 192 391 #define IWN_MPDU_RX_DONE 193 392 #define IWN_RX_DONE 195 393 #define IWN_RX_COMPRESSED_BA 197 394 395 uint8_t flags; 396 uint8_t idx; 397 uint8_t qid; 398 } __packed; 399 400 /* Possible RX status flags. */ 401 #define IWN_RX_NO_CRC_ERR (1 << 0) 402 #define IWN_RX_NO_OVFL_ERR (1 << 1) 403 /* Shortcut for the above. */ 404 #define IWN_RX_NOERROR (IWN_RX_NO_CRC_ERR | IWN_RX_NO_OVFL_ERR) 405 #define IWN_RX_MPDU_MIC_OK (1 << 6) 406 #define IWN_RX_CIPHER_MASK (7 << 8) 407 #define IWN_RX_CIPHER_CCMP (2 << 8) 408 #define IWN_RX_MPDU_DEC (1 << 11) 409 #define IWN_RX_DECRYPT_MASK (3 << 11) 410 #define IWN_RX_DECRYPT_OK (3 << 11) 411 412 struct iwn_tx_cmd { 413 uint8_t code; 414 #define IWN_CMD_RXON 16 415 #define IWN_CMD_RXON_ASSOC 17 416 #define IWN_CMD_EDCA_PARAMS 19 417 #define IWN_CMD_TIMING 20 418 #define IWN_CMD_ADD_NODE 24 419 #define IWN_CMD_TX_DATA 28 420 #define IWN_CMD_LINK_QUALITY 78 421 #define IWN_CMD_SET_LED 72 422 #define IWN5000_CMD_WIMAX_COEX 90 423 #define IWN5000_CMD_CALIB_CONFIG 101 424 #define IWN_CMD_SET_POWER_MODE 119 425 #define IWN_CMD_SCAN 128 426 #define IWN_CMD_TXPOWER_DBM 149 427 #define IWN_CMD_TXPOWER 151 428 #define IWN5000_CMD_TX_ANT_CONFIG 152 429 #define IWN_CMD_BT_COEX 155 430 #define IWN_CMD_GET_STATISTICS 156 431 #define IWN_CMD_SET_CRITICAL_TEMP 164 432 #define IWN_CMD_SET_SENSITIVITY 168 433 #define IWN_CMD_PHY_CALIB 176 434 435 uint8_t flags; 436 uint8_t idx; 437 uint8_t qid; 438 uint8_t data[136]; 439 } __packed; 440 441 /* Antenna flags, used in various commands. */ 442 #define IWN_ANT_A (1 << 0) 443 #define IWN_ANT_B (1 << 1) 444 #define IWN_ANT_C (1 << 2) 445 /* Shortcuts. */ 446 #define IWN_ANT_AB (IWN_ANT_A | IWN_ANT_B) 447 #define IWN_ANT_BC (IWN_ANT_B | IWN_ANT_C) 448 #define IWN_ANT_ABC (IWN_ANT_A | IWN_ANT_B | IWN_ANT_C) 449 450 /* Structure for command IWN_CMD_RXON. */ 451 struct iwn_rxon { 452 uint8_t myaddr[IEEE80211_ADDR_LEN]; 453 uint16_t reserved1; 454 uint8_t bssid[IEEE80211_ADDR_LEN]; 455 uint16_t reserved2; 456 uint8_t wlap[IEEE80211_ADDR_LEN]; 457 uint16_t reserved3; 458 uint8_t mode; 459 #define IWN_MODE_HOSTAP 1 460 #define IWN_MODE_STA 3 461 #define IWN_MODE_IBSS 4 462 #define IWN_MODE_MONITOR 6 463 464 uint8_t air; 465 uint16_t rxchain; 466 #define IWN_RXCHAIN_DRIVER_FORCE (1 << 0) 467 #define IWN_RXCHAIN_VALID(x) (((x) & IWN_ANT_ABC) << 1) 468 #define IWN_RXCHAIN_FORCE_SEL(x) (((x) & IWN_ANT_ABC) << 4) 469 #define IWN_RXCHAIN_FORCE_MIMO_SEL(x) (((x) & IWN_ANT_ABC) << 7) 470 #define IWN_RXCHAIN_IDLE_COUNT(x) ((x) << 10) 471 #define IWN_RXCHAIN_MIMO_COUNT(x) ((x) << 12) 472 #define IWN_RXCHAIN_MIMO_FORCE (1 << 14) 473 474 uint8_t ofdm_mask; 475 uint8_t cck_mask; 476 uint16_t associd; 477 uint32_t flags; 478 #define IWN_RXON_24GHZ (1 << 0) 479 #define IWN_RXON_CCK (1 << 1) 480 #define IWN_RXON_AUTO (1 << 2) 481 #define IWN_RXON_SHSLOT (1 << 4) 482 #define IWN_RXON_SHPREAMBLE (1 << 5) 483 #define IWN_RXON_NODIVERSITY (1 << 7) 484 #define IWN_RXON_ANTENNA_A (1 << 8) 485 #define IWN_RXON_ANTENNA_B (1 << 9) 486 #define IWN_RXON_TSF (1 << 15) 487 #define IWN_RXON_CTS_TO_SELF (1 << 30) 488 489 uint32_t filter; 490 #define IWN_FILTER_PROMISC (1 << 0) 491 #define IWN_FILTER_CTL (1 << 1) 492 #define IWN_FILTER_MULTICAST (1 << 2) 493 #define IWN_FILTER_NODECRYPT (1 << 3) 494 #define IWN_FILTER_BSS (1 << 5) 495 #define IWN_FILTER_BEACON (1 << 6) 496 497 uint8_t chan; 498 uint8_t reserved4; 499 uint8_t ht_single_mask; 500 uint8_t ht_dual_mask; 501 /* The following fields are for >=5000 Series only. */ 502 uint8_t ht_triple_mask; 503 uint8_t reserved5; 504 uint16_t acquisition; 505 uint16_t reserved6; 506 } __packed; 507 508 #define IWN4965_RXONSZ (sizeof (struct iwn_rxon) - 6) 509 #define IWN5000_RXONSZ (sizeof (struct iwn_rxon)) 510 511 /* Structure for command IWN_CMD_ASSOCIATE. */ 512 struct iwn_assoc { 513 uint32_t flags; 514 uint32_t filter; 515 uint8_t ofdm_mask; 516 uint8_t cck_mask; 517 uint16_t reserved; 518 } __packed; 519 520 /* Structure for command IWN_CMD_EDCA_PARAMS. */ 521 struct iwn_edca_params { 522 uint32_t flags; 523 #define IWN_EDCA_UPDATE (1 << 0) 524 #define IWN_EDCA_TXOP (1 << 4) 525 526 struct { 527 uint16_t cwmin; 528 uint16_t cwmax; 529 uint8_t aifsn; 530 uint8_t reserved; 531 uint16_t txoplimit; 532 } __packed ac[WME_NUM_AC]; 533 } __packed; 534 535 /* Structure for command IWN_CMD_TIMING. */ 536 struct iwn_cmd_timing { 537 uint64_t tstamp; 538 uint16_t bintval; 539 uint16_t atim; 540 uint32_t binitval; 541 uint16_t lintval; 542 uint16_t reserved; 543 } __packed; 544 545 /* Structure for command IWN_CMD_ADD_NODE. */ 546 struct iwn_node_info { 547 uint8_t control; 548 #define IWN_NODE_UPDATE (1 << 0) 549 550 uint8_t reserved1[3]; 551 552 uint8_t macaddr[IEEE80211_ADDR_LEN]; 553 uint16_t reserved2; 554 uint8_t id; 555 #define IWN_ID_BSS 0 556 #define IWN5000_ID_BROADCAST 15 557 #define IWN4965_ID_BROADCAST 31 558 559 uint8_t flags; 560 #define IWN_FLAG_SET_KEY (1 << 0) 561 #define IWN_FLAG_SET_DISABLE_TID (1 << 1) 562 #define IWN_FLAG_SET_TXRATE (1 << 2) 563 #define IWN_FLAG_SET_ADDBA (1 << 3) 564 #define IWN_FLAG_SET_DELBA (1 << 4) 565 566 uint16_t reserved3; 567 uint16_t kflags; 568 #define IWN_KFLAG_CCMP (1 << 1) 569 #define IWN_KFLAG_MAP (1 << 3) 570 #define IWN_KFLAG_KID(kid) ((kid) << 8) 571 #define IWN_KFLAG_INVALID (1 << 11) 572 #define IWN_KFLAG_GROUP (1 << 14) 573 574 uint8_t tsc2; /* TKIP TSC2 */ 575 uint8_t reserved4; 576 uint16_t ttak[5]; 577 uint8_t kid; 578 uint8_t reserved5; 579 uint8_t key[16]; 580 /* The following 3 fields are for 5000 Series only. */ 581 uint64_t tsc; 582 uint8_t rxmic[8]; 583 uint8_t txmic[8]; 584 585 uint32_t htflags; 586 #define IWN_AMDPU_SIZE_FACTOR(x) ((x) << 19) 587 #define IWN_AMDPU_DENSITY(x) ((x) << 23) 588 589 uint32_t mask; 590 uint16_t disable_tid; 591 uint16_t reserved6; 592 uint8_t addba_tid; 593 uint8_t delba_tid; 594 uint16_t addba_ssn; 595 uint32_t reserved7; 596 } __packed; 597 598 struct iwn4965_node_info { 599 uint8_t control; 600 uint8_t reserved1[3]; 601 uint8_t macaddr[IEEE80211_ADDR_LEN]; 602 uint16_t reserved2; 603 uint8_t id; 604 uint8_t flags; 605 uint16_t reserved3; 606 uint16_t kflags; 607 uint8_t tsc2; /* TKIP TSC2 */ 608 uint8_t reserved4; 609 uint16_t ttak[5]; 610 uint8_t kid; 611 uint8_t reserved5; 612 uint8_t key[16]; 613 uint32_t htflags; 614 uint32_t mask; 615 uint16_t disable_tid; 616 uint16_t reserved6; 617 uint8_t addba_tid; 618 uint8_t delba_tid; 619 uint16_t addba_ssn; 620 uint32_t reserved7; 621 } __packed; 622 623 #define IWN_RFLAG_CCK (1 << 1) 624 #define IWN_RFLAG_ANT(x) ((x) << 6) 625 626 /* Structure for command IWN_CMD_TX_DATA. */ 627 struct iwn_cmd_data { 628 uint16_t len; 629 uint16_t lnext; 630 uint32_t flags; 631 #define IWN_TX_NEED_PROTECTION (1 << 0) /* 5000 only */ 632 #define IWN_TX_NEED_RTS (1 << 1) 633 #define IWN_TX_NEED_CTS (1 << 2) 634 #define IWN_TX_NEED_ACK (1 << 3) 635 #define IWN_TX_LINKQ (1 << 4) 636 #define IWN_TX_IMM_BA (1 << 6) 637 #define IWN_TX_FULL_TXOP (1 << 7) 638 #define IWN_TX_BT_DISABLE (1 << 12) /* bluetooth coexistence */ 639 #define IWN_TX_AUTO_SEQ (1 << 13) 640 #define IWN_TX_MORE_FRAG (1 << 14) 641 #define IWN_TX_INSERT_TSTAMP (1 << 16) 642 #define IWN_TX_NEED_PADDING (1 << 20) 643 644 uint32_t scratch; 645 uint8_t plcp; 646 uint8_t rflags; 647 uint16_t xrflags; 648 649 uint8_t id; 650 uint8_t security; 651 #define IWN_CIPHER_WEP40 1 652 #define IWN_CIPHER_CCMP 2 653 #define IWN_CIPHER_TKIP 3 654 #define IWN_CIPHER_WEP104 9 655 656 uint8_t linkq; 657 uint8_t reserved2; 658 uint8_t key[16]; 659 uint16_t fnext; 660 uint16_t reserved3; 661 uint32_t lifetime; 662 #define IWN_LIFETIME_INFINITE 0xffffffff 663 664 uint32_t loaddr; 665 uint8_t hiaddr; 666 uint8_t rts_ntries; 667 uint8_t data_ntries; 668 uint8_t tid; 669 uint16_t timeout; 670 uint16_t txop; 671 } __packed; 672 673 /* Structure for command IWN_CMD_LINK_QUALITY. */ 674 #define IWN_MAX_TX_RETRIES 16 675 struct iwn_cmd_link_quality { 676 uint8_t id; 677 uint8_t reserved1; 678 uint16_t ctl; 679 uint8_t flags; 680 uint8_t mimo; 681 uint8_t antmsk_1stream; 682 uint8_t antmsk_2stream; 683 uint8_t ridx[WME_NUM_AC]; 684 uint16_t ampdu_limit; 685 uint8_t ampdu_threshold; 686 uint8_t ampdu_max; 687 uint32_t reserved2; 688 struct { 689 uint8_t plcp; 690 uint8_t rflags; 691 uint16_t xrflags; 692 } __packed retry[IWN_MAX_TX_RETRIES]; 693 uint32_t reserved3; 694 } __packed; 695 696 /* Structure for command IWN_CMD_SET_LED. */ 697 struct iwn_cmd_led { 698 uint32_t unit; /* multiplier (in usecs) */ 699 uint8_t which; 700 #define IWN_LED_ACTIVITY 1 701 #define IWN_LED_LINK 2 702 703 uint8_t off; 704 uint8_t on; 705 uint8_t reserved; 706 } __packed; 707 708 /* Structure for command IWN5000_CMD_WIMAX_COEX. */ 709 struct iwn5000_wimax_coex { 710 uint32_t flags; 711 #define IWN_WIMAX_COEX_STA_TABLE_VALID (1 << 0) 712 #define IWN_WIMAX_COEX_UNASSOC_WA_UNMASK (1 << 2) 713 #define IWN_WIMAX_COEX_ASSOC_WA_UNMASK (1 << 3) 714 #define IWN_WIMAX_COEX_ENABLE (1 << 7) 715 716 struct iwn5000_wimax_event { 717 uint8_t request; 718 uint8_t window; 719 uint8_t reserved; 720 uint8_t flags; 721 } __packed events[16]; 722 } __packed; 723 724 /* Structures for command IWN5000_CMD_CALIB_CONFIG. */ 725 struct iwn5000_calib_elem { 726 uint32_t enable; 727 uint32_t start; 728 uint32_t send; 729 uint32_t apply; 730 uint32_t reserved; 731 } __packed; 732 733 struct iwn5000_calib_status { 734 struct iwn5000_calib_elem once; 735 struct iwn5000_calib_elem perd; 736 uint32_t flags; 737 } __packed; 738 739 struct iwn5000_calib_config { 740 struct iwn5000_calib_status ucode; 741 struct iwn5000_calib_status driver; 742 uint32_t reserved; 743 } __packed; 744 745 /* Structure for command IWN_CMD_SET_POWER_MODE. */ 746 struct iwn_pmgt_cmd { 747 uint16_t flags; 748 #define IWN_PS_ALLOW_SLEEP (1 << 0) 749 #define IWN_PS_NOTIFY (1 << 1) 750 #define IWN_PS_SLEEP_OVER_DTIM (1 << 2) 751 #define IWN_PS_PCI_PMGT (1 << 3) 752 #define IWN_PS_FAST_PD (1 << 4) 753 754 uint8_t keepalive; 755 uint8_t debug; 756 uint32_t rxtimeout; 757 uint32_t txtimeout; 758 uint32_t intval[5]; 759 uint32_t beacons; 760 } __packed; 761 762 /* Structures for command IWN_CMD_SCAN. */ 763 struct iwn_scan_essid { 764 uint8_t id; 765 uint8_t len; 766 uint8_t data[IEEE80211_NWID_LEN]; 767 } __packed; 768 769 struct iwn_scan_hdr { 770 uint16_t len; 771 uint8_t reserved1; 772 uint8_t nchan; 773 uint16_t quiet_time; 774 uint16_t quiet_threshold; 775 uint16_t crc_threshold; 776 uint16_t rxchain; 777 uint32_t max_svc; /* background scans */ 778 uint32_t pause_svc; /* background scans */ 779 uint32_t flags; 780 uint32_t filter; 781 782 /* Followed by a struct iwn_cmd_data. */ 783 /* Followed by an array of 20 structs iwn_scan_essid. */ 784 /* Followed by probe request body. */ 785 /* Followed by an array of ``nchan'' structs iwn_scan_chan. */ 786 } __packed; 787 788 struct iwn_scan_chan { 789 uint32_t flags; 790 #define IWN_CHAN_ACTIVE (1 << 0) 791 #define IWN_CHAN_NPBREQS(x) (((1 << (x)) - 1) << 1) 792 793 uint16_t chan; 794 uint8_t rf_gain; 795 uint8_t dsp_gain; 796 uint16_t active; /* msecs */ 797 uint16_t passive; /* msecs */ 798 } __packed; 799 800 /* Maximum size of a scan command. */ 801 #define IWN_SCAN_MAXSZ (MCLBYTES - 4) 802 803 /* Structure for command IWN_CMD_TXPOWER (4965AGN only.) */ 804 #define IWN_RIDX_MAX 32 805 struct iwn4965_cmd_txpower { 806 uint8_t band; 807 uint8_t reserved1; 808 uint8_t chan; 809 uint8_t reserved2; 810 struct { 811 uint8_t rf_gain[2]; 812 uint8_t dsp_gain[2]; 813 } __packed power[IWN_RIDX_MAX + 1]; 814 } __packed; 815 816 /* Structure for command IWN_CMD_TXPOWER_DBM (5000 Series only.) */ 817 struct iwn5000_cmd_txpower { 818 int8_t global_limit; /* in half-dBm */ 819 #define IWN5000_TXPOWER_AUTO 0x7f 820 #define IWN5000_TXPOWER_MAX_DBM 16 821 822 uint8_t flags; 823 #define IWN5000_TXPOWER_NO_CLOSED (1 << 6) 824 825 int8_t srv_limit; /* in half-dBm */ 826 uint8_t reserved; 827 } __packed; 828 829 /* Structure for command IWN_CMD_BLUETOOTH. */ 830 struct iwn_bluetooth { 831 uint8_t flags; 832 #define IWN_BT_COEX_DISABLE 0 833 #define IWN_BT_COEX_MODE_2WIRE 1 834 #define IWN_BT_COEX_MODE_3WIRE 2 835 #define IWN_BT_COEX_MODE_4WIRE 3 836 837 uint8_t lead_time; 838 #define IWN_BT_LEAD_TIME_DEF 30 839 840 uint8_t max_kill; 841 #define IWN_BT_MAX_KILL_DEF 5 842 843 uint8_t reserved; 844 uint32_t kill_ack; 845 uint32_t kill_cts; 846 } __packed; 847 848 /* Structure for command IWN_CMD_SET_CRITICAL_TEMP. */ 849 struct iwn_critical_temp { 850 uint32_t reserved; 851 uint32_t tempM; 852 uint32_t tempR; 853 /* degK <-> degC conversion macros. */ 854 #define IWN_CTOK(c) ((c) + 273) 855 #define IWN_KTOC(k) ((k) - 273) 856 #define IWN_CTOMUK(c) (((c) * 1000000) + 273150000) 857 } __packed; 858 859 /* Structure for command IWN_CMD_SET_SENSITIVITY. */ 860 struct iwn_sensitivity_cmd { 861 uint16_t which; 862 #define IWN_SENSITIVITY_DEFAULTTBL 0 863 #define IWN_SENSITIVITY_WORKTBL 1 864 865 uint16_t energy_cck; 866 uint16_t energy_ofdm; 867 uint16_t corr_ofdm_x1; 868 uint16_t corr_ofdm_mrc_x1; 869 uint16_t corr_cck_mrc_x4; 870 uint16_t corr_ofdm_x4; 871 uint16_t corr_ofdm_mrc_x4; 872 uint16_t corr_barker; 873 uint16_t corr_barker_mrc; 874 uint16_t corr_cck_x4; 875 uint16_t energy_ofdm_th; 876 } __packed; 877 878 /* Structures for command IWN_CMD_PHY_CALIB. */ 879 struct iwn_phy_calib { 880 uint8_t code; 881 #define IWN4965_PHY_CALIB_DIFF_GAIN 7 882 #define IWN5000_PHY_CALIB_DC 8 883 #define IWN5000_PHY_CALIB_LO 9 884 #define IWN5000_PHY_CALIB_TX_IQ 11 885 #define IWN5000_PHY_CALIB_CRYSTAL 15 886 #define IWN5000_PHY_CALIB_BASE_BAND 16 887 #define IWN5000_PHY_CALIB_TX_IQ_PERIODIC 17 888 #define IWN5000_PHY_CALIB_RESET_NOISE_GAIN 18 889 #define IWN5000_PHY_CALIB_NOISE_GAIN 19 890 891 uint8_t group; 892 uint8_t ngroups; 893 uint8_t isvalid; 894 } __packed; 895 896 struct iwn5000_phy_calib_crystal { 897 uint8_t code; 898 uint8_t group; 899 uint8_t ngroups; 900 uint8_t isvalid; 901 902 uint8_t cap_pin[2]; 903 uint8_t reserved[2]; 904 } __packed; 905 906 struct iwn_phy_calib_gain { 907 uint8_t code; 908 uint8_t group; 909 uint8_t ngroups; 910 uint8_t isvalid; 911 912 int8_t gain[3]; 913 uint8_t reserved; 914 } __packed; 915 916 /* Structure for command IWN_CMD_SPECTRUM_MEASUREMENT. */ 917 struct iwn_spectrum_cmd { 918 uint16_t len; 919 uint8_t token; 920 uint8_t id; 921 uint8_t origin; 922 uint8_t periodic; 923 uint16_t timeout; 924 uint32_t start; 925 uint32_t reserved1; 926 uint32_t flags; 927 uint32_t filter; 928 uint16_t nchan; 929 uint16_t reserved2; 930 struct { 931 uint32_t duration; 932 uint8_t chan; 933 uint8_t type; 934 #define IWN_MEASUREMENT_BASIC (1 << 0) 935 #define IWN_MEASUREMENT_CCA (1 << 1) 936 #define IWN_MEASUREMENT_RPI_HISTOGRAM (1 << 2) 937 #define IWN_MEASUREMENT_NOISE_HISTOGRAM (1 << 3) 938 #define IWN_MEASUREMENT_FRAME (1 << 4) 939 #define IWN_MEASUREMENT_IDLE (1 << 7) 940 941 uint16_t reserved; 942 } __packed chan[10]; 943 } __packed; 944 945 /* Structure for IWN_UC_READY notification. */ 946 #define IWN_NATTEN_GROUPS 5 947 struct iwn_ucode_info { 948 uint8_t minor; 949 uint8_t major; 950 uint16_t reserved1; 951 uint8_t revision[8]; 952 uint8_t type; 953 uint8_t subtype; 954 #define IWN_UCODE_RUNTIME 0 955 #define IWN_UCODE_INIT 9 956 957 uint16_t reserved2; 958 uint32_t logptr; 959 uint32_t errptr; 960 uint32_t tstamp; 961 uint32_t valid; 962 963 /* The following fields are for UCODE_INIT only. */ 964 int32_t volt; 965 struct { 966 int32_t chan20MHz; 967 int32_t chan40MHz; 968 } __packed temp[4]; 969 int32_t atten[IWN_NATTEN_GROUPS][2]; 970 } __packed; 971 972 /* Structures for IWN_TX_DONE notification. */ 973 #define IWN_TX_SUCCESS 0x00 974 #define IWN_TX_FAIL 0x80 /* all failures have 0x80 set */ 975 #define IWN_TX_FAIL_SHORT_LIMIT 0x82 /* too many RTS retries */ 976 #define IWN_TX_FAIL_LONG_LIMIT 0x83 /* too many retries */ 977 #define IWN_TX_FAIL_FIFO_UNDERRRUN 0x84 /* tx fifo not kept running */ 978 #define IWN_TX_FAIL_DEST_IN_PS 0x88 /* sta found in power save */ 979 #define IWN_TX_FAIL_TX_LOCKED 0x90 /* waiting to see traffic */ 980 981 struct iwn4965_tx_stat { 982 uint8_t nframes; 983 uint8_t btkillcnt; 984 uint8_t rtsfailcnt; 985 uint8_t ackfailcnt; 986 uint8_t rate; 987 uint8_t rflags; 988 uint16_t xrflags; 989 uint16_t duration; 990 uint16_t reserved; 991 uint32_t power[2]; 992 uint32_t status; 993 } __packed; 994 995 struct iwn5000_tx_stat { 996 uint8_t nframes; 997 uint8_t btkillcnt; 998 uint8_t rtsfailcnt; 999 uint8_t ackfailcnt; 1000 uint8_t rate; 1001 uint8_t rflags; 1002 uint16_t xrflags; 1003 uint16_t duration; 1004 uint16_t reserved; 1005 uint32_t power[2]; 1006 uint32_t info; 1007 uint16_t seq; 1008 uint16_t len; 1009 uint8_t tlc; 1010 uint8_t ratid; 1011 uint8_t fc[2]; 1012 uint16_t status; 1013 uint16_t sequence; 1014 } __packed; 1015 1016 /* Structure for IWN_BEACON_MISSED notification. */ 1017 struct iwn_beacon_missed { 1018 uint32_t consecutive; 1019 uint32_t total; 1020 uint32_t expected; 1021 uint32_t received; 1022 } __packed; 1023 1024 /* Structure for IWN_MPDU_RX_DONE notification. */ 1025 struct iwn_rx_mpdu { 1026 uint16_t len; 1027 uint16_t reserved; 1028 } __packed; 1029 1030 /* Structures for IWN_RX_DONE and IWN_MPDU_RX_DONE notifications. */ 1031 struct iwn4965_rx_phystat { 1032 uint16_t antenna; 1033 uint16_t agc; 1034 uint8_t rssi[6]; 1035 } __packed; 1036 1037 struct iwn5000_rx_phystat { 1038 uint32_t reserved1; 1039 uint32_t agc; 1040 uint16_t rssi[3]; 1041 } __packed; 1042 1043 struct iwn_rx_stat { 1044 uint8_t phy_len; 1045 uint8_t cfg_phy_len; 1046 #define IWN_STAT_MAXLEN 20 1047 1048 uint8_t id; 1049 uint8_t reserved1; 1050 uint64_t tstamp; 1051 uint32_t beacon; 1052 uint16_t flags; 1053 #define IWN_STAT_FLAG_SHPREAMBLE (1 << 2) 1054 1055 uint16_t chan; 1056 uint8_t phybuf[32]; 1057 uint8_t rate; 1058 uint8_t rflags; 1059 uint16_t xrflags; 1060 uint16_t len; 1061 uint16_t reserve3; 1062 } __packed; 1063 1064 #define IWN_RSSI_TO_DBM 44 1065 1066 /* Structure for IWN_RX_COMPRESSED_BA notification. */ 1067 struct iwn_compressed_ba { 1068 uint8_t macaddr[IEEE80211_ADDR_LEN]; 1069 uint16_t reserved; 1070 uint8_t id; 1071 uint8_t tid; 1072 uint16_t seq; 1073 uint64_t bitmap; 1074 uint16_t qid; 1075 uint16_t ssn; 1076 } __packed; 1077 1078 /* Structure for IWN_START_SCAN notification. */ 1079 struct iwn_start_scan { 1080 uint64_t tstamp; 1081 uint32_t tbeacon; 1082 uint8_t chan; 1083 uint8_t band; 1084 uint16_t reserved; 1085 uint32_t status; 1086 } __packed; 1087 1088 /* Structure for IWN_STOP_SCAN notification. */ 1089 struct iwn_stop_scan { 1090 uint8_t nchan; 1091 uint8_t status; 1092 uint8_t reserved; 1093 uint8_t chan; 1094 uint64_t tsf; 1095 } __packed; 1096 1097 /* Structure for IWN_SPECTRUM_MEASUREMENT notification. */ 1098 struct iwn_spectrum_notif { 1099 uint8_t id; 1100 uint8_t token; 1101 uint8_t idx; 1102 uint8_t state; 1103 #define IWN_MEASUREMENT_START 0 1104 #define IWN_MEASUREMENT_STOP 1 1105 1106 uint32_t start; 1107 uint8_t band; 1108 uint8_t chan; 1109 uint8_t type; 1110 uint8_t reserved1; 1111 uint32_t cca_ofdm; 1112 uint32_t cca_cck; 1113 uint32_t cca_time; 1114 uint8_t basic; 1115 uint8_t reserved2[3]; 1116 uint32_t ofdm[8]; 1117 uint32_t cck[8]; 1118 uint32_t stop; 1119 uint32_t status; 1120 #define IWN_MEASUREMENT_OK 0 1121 #define IWN_MEASUREMENT_CONCURRENT 1 1122 #define IWN_MEASUREMENT_CSA_CONFLICT 2 1123 #define IWN_MEASUREMENT_TGH_CONFLICT 3 1124 #define IWN_MEASUREMENT_STOPPED 6 1125 #define IWN_MEASUREMENT_TIMEOUT 7 1126 #define IWN_MEASUREMENT_FAILED 8 1127 } __packed; 1128 1129 /* Structures for IWN_{RX,BEACON}_STATISTICS notification. */ 1130 struct iwn_rx_phy_stats { 1131 uint32_t ina; 1132 uint32_t fina; 1133 uint32_t bad_plcp; 1134 uint32_t bad_crc32; 1135 uint32_t overrun; 1136 uint32_t eoverrun; 1137 uint32_t good_crc32; 1138 uint32_t fa; 1139 uint32_t bad_fina_sync; 1140 uint32_t sfd_timeout; 1141 uint32_t fina_timeout; 1142 uint32_t no_rts_ack; 1143 uint32_t rxe_limit; 1144 uint32_t ack; 1145 uint32_t cts; 1146 uint32_t ba_resp; 1147 uint32_t dsp_kill; 1148 uint32_t bad_mh; 1149 uint32_t rssi_sum; 1150 uint32_t reserved; 1151 } __packed; 1152 1153 struct iwn_rx_general_stats { 1154 uint32_t bad_cts; 1155 uint32_t bad_ack; 1156 uint32_t not_bss; 1157 uint32_t filtered; 1158 uint32_t bad_chan; 1159 uint32_t beacons; 1160 uint32_t missed_beacons; 1161 uint32_t adc_saturated; /* time in 0.8us */ 1162 uint32_t ina_searched; /* time in 0.8us */ 1163 uint32_t noise[3]; 1164 uint32_t flags; 1165 uint32_t load; 1166 uint32_t fa; 1167 uint32_t rssi[3]; 1168 uint32_t energy[3]; 1169 } __packed; 1170 1171 struct iwn_rx_ht_phy_stats { 1172 uint32_t bad_plcp; 1173 uint32_t overrun; 1174 uint32_t eoverrun; 1175 uint32_t good_crc32; 1176 uint32_t bad_crc32; 1177 uint32_t bad_mh; 1178 uint32_t good_ampdu_crc32; 1179 uint32_t ampdu; 1180 uint32_t fragment; 1181 uint32_t reserved; 1182 } __packed; 1183 1184 struct iwn_rx_stats { 1185 struct iwn_rx_phy_stats ofdm; 1186 struct iwn_rx_phy_stats cck; 1187 struct iwn_rx_general_stats general; 1188 struct iwn_rx_ht_phy_stats ht; 1189 } __packed; 1190 1191 struct iwn_tx_stats { 1192 uint32_t preamble; 1193 uint32_t rx_detected; 1194 uint32_t bt_defer; 1195 uint32_t bt_kill; 1196 uint32_t short_len; 1197 uint32_t cts_timeout; 1198 uint32_t ack_timeout; 1199 uint32_t exp_ack; 1200 uint32_t ack; 1201 uint32_t msdu; 1202 uint32_t busrt_err1; 1203 uint32_t burst_err2; 1204 uint32_t cts_collision; 1205 uint32_t ack_collision; 1206 uint32_t ba_timeout; 1207 uint32_t ba_resched; 1208 uint32_t query_ampdu; 1209 uint32_t query; 1210 uint32_t query_ampdu_frag; 1211 uint32_t query_mismatch; 1212 uint32_t not_ready; 1213 uint32_t underrun; 1214 uint32_t bt_ht_kill; 1215 uint32_t rx_ba_resp; 1216 uint32_t reserved[2]; 1217 } __packed; 1218 1219 struct iwn_general_stats { 1220 uint32_t temp; 1221 uint32_t temp_m; 1222 uint32_t burst_check; 1223 uint32_t burst; 1224 uint32_t reserved1[4]; 1225 uint32_t sleep; 1226 uint32_t slot_out; 1227 uint32_t slot_idle; 1228 uint32_t ttl_tstamp; 1229 uint32_t tx_ant_a; 1230 uint32_t tx_ant_b; 1231 uint32_t exec; 1232 uint32_t probe; 1233 uint32_t reserved2[2]; 1234 uint32_t rx_enabled; 1235 uint32_t reserved3[3]; 1236 } __packed; 1237 1238 struct iwn_stats { 1239 uint32_t flags; 1240 struct iwn_rx_stats rx; 1241 struct iwn_tx_stats tx; 1242 struct iwn_general_stats general; 1243 } __packed; 1244 1245 1246 /* Firmware error dump. */ 1247 struct iwn_fw_dump { 1248 uint32_t valid; 1249 uint32_t id; 1250 uint32_t pc; 1251 uint32_t branch_link[2]; 1252 uint32_t interrupt_link[2]; 1253 uint32_t error_data[2]; 1254 uint32_t src_line; 1255 uint32_t tsf; 1256 uint32_t time[2]; 1257 } __packed; 1258 1259 #define IWN4965_FW_TEXT_MAXSZ ( 96 * 1024) 1260 #define IWN4965_FW_DATA_MAXSZ ( 40 * 1024) 1261 #define IWN5000_FW_TEXT_MAXSZ (256 * 1024) 1262 #define IWN5000_FW_DATA_MAXSZ ( 80 * 1024) 1263 #define IWN_FW_BOOT_TEXT_MAXSZ 1024 1264 #define IWN4965_FWSZ (IWN4965_FW_TEXT_MAXSZ + IWN4965_FW_DATA_MAXSZ) 1265 #define IWN5000_FWSZ IWN5000_FW_TEXT_MAXSZ 1266 1267 #define IWN_FW_API(x) (((x) >> 8) & 0xff) 1268 1269 /* 1270 * Offsets into EEPROM. 1271 */ 1272 #define IWN_EEPROM_MAC 0x015 1273 #define IWN_EEPROM_RFCFG 0x048 1274 #define IWN4965_EEPROM_DOMAIN 0x060 1275 #define IWN4965_EEPROM_BAND1 0x063 1276 #define IWN5000_EEPROM_REG 0x066 1277 #define IWN5000_EEPROM_CAL 0x067 1278 #define IWN4965_EEPROM_BAND2 0x072 1279 #define IWN4965_EEPROM_BAND3 0x080 1280 #define IWN4965_EEPROM_BAND4 0x08d 1281 #define IWN4965_EEPROM_BAND5 0x099 1282 #define IWN4965_EEPROM_BAND6 0x0a0 1283 #define IWN4965_EEPROM_BAND7 0x0a8 1284 #define IWN4965_EEPROM_MAXPOW 0x0e8 1285 #define IWN4965_EEPROM_VOLTAGE 0x0e9 1286 #define IWN4965_EEPROM_BANDS 0x0ea 1287 /* Indirect offsets. */ 1288 #define IWN5000_EEPROM_DOMAIN 0x001 1289 #define IWN5000_EEPROM_BAND1 0x004 1290 #define IWN5000_EEPROM_BAND2 0x013 1291 #define IWN5000_EEPROM_BAND3 0x021 1292 #define IWN5000_EEPROM_BAND4 0x02e 1293 #define IWN5000_EEPROM_BAND5 0x03a 1294 #define IWN5000_EEPROM_BAND6 0x041 1295 #define IWN5000_EEPROM_BAND7 0x049 1296 #define IWN6000_EEPROM_ENHINFO 0x054 1297 #define IWN5000_EEPROM_CRYSTAL 0x128 1298 #define IWN5000_EEPROM_TEMP 0x12a 1299 #define IWN5000_EEPROM_VOLT 0x12b 1300 1301 /* Possible flags for IWN_EEPROM_RFCFG. */ 1302 #define IWN_RFCFG_TYPE(x) (((x) >> 0) & 0x3) 1303 #define IWN_RFCFG_STEP(x) (((x) >> 2) & 0x3) 1304 #define IWN_RFCFG_DASH(x) (((x) >> 4) & 0x3) 1305 #define IWN_RFCFG_TXANTMSK(x) (((x) >> 8) & 0xf) 1306 #define IWN_RFCFG_RXANTMSK(x) (((x) >> 12) & 0xf) 1307 1308 struct iwn_eeprom_chan { 1309 uint8_t flags; 1310 #define IWN_EEPROM_CHAN_VALID (1 << 0) 1311 #define IWN_EEPROM_CHAN_IBSS (1 << 1) 1312 #define IWN_EEPROM_CHAN_ACTIVE (1 << 3) 1313 #define IWN_EEPROM_CHAN_RADAR (1 << 4) 1314 1315 int8_t maxpwr; 1316 } __packed; 1317 1318 struct iwn_eeprom_enhinfo { 1319 uint16_t chan; 1320 int8_t chain[3]; /* max power in half-dBm */ 1321 uint8_t reserved; 1322 int8_t mimo2; /* max power in half-dBm */ 1323 int8_t mimo3; /* max power in half-dBm */ 1324 } __packed; 1325 1326 #define IWN_NSAMPLES 3 1327 struct iwn4965_eeprom_chan_samples { 1328 uint8_t num; 1329 struct { 1330 uint8_t temp; 1331 uint8_t gain; 1332 uint8_t power; 1333 int8_t pa_det; 1334 } samples[2][IWN_NSAMPLES]; 1335 } __packed; 1336 1337 #define IWN_NBANDS 8 1338 struct iwn4965_eeprom_band { 1339 uint8_t lo; /* low channel number */ 1340 uint8_t hi; /* high channel number */ 1341 struct iwn4965_eeprom_chan_samples chans[2]; 1342 } __packed; 1343 1344 /* 1345 * Offsets of channels descriptions in EEPROM. 1346 */ 1347 static const uint32_t iwn4965_regulatory_bands[IWN_NBANDS] = { 1348 IWN4965_EEPROM_BAND1, 1349 IWN4965_EEPROM_BAND2, 1350 IWN4965_EEPROM_BAND3, 1351 IWN4965_EEPROM_BAND4, 1352 IWN4965_EEPROM_BAND5, 1353 IWN4965_EEPROM_BAND6, 1354 IWN4965_EEPROM_BAND7 1355 }; 1356 1357 static const uint32_t iwn5000_regulatory_bands[IWN_NBANDS] = { 1358 IWN5000_EEPROM_BAND1, 1359 IWN5000_EEPROM_BAND2, 1360 IWN5000_EEPROM_BAND3, 1361 IWN5000_EEPROM_BAND4, 1362 IWN5000_EEPROM_BAND5, 1363 IWN5000_EEPROM_BAND6, 1364 IWN5000_EEPROM_BAND7 1365 }; 1366 1367 #define IWN_CHAN_BANDS_COUNT 7 1368 #define IWN_MAX_CHAN_PER_BAND 14 1369 static const struct iwn_chan_band { 1370 uint8_t nchan; 1371 uint8_t chan[IWN_MAX_CHAN_PER_BAND]; 1372 } iwn_bands[] = { 1373 /* 20MHz channels, 2GHz band. */ 1374 { 14, { 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14 } }, 1375 /* 20MHz channels, 5GHz band. */ 1376 { 13, { 183, 184, 185, 187, 188, 189, 192, 196, 7, 8, 11, 12, 16 } }, 1377 { 12, { 34, 36, 38, 40, 42, 44, 46, 48, 52, 56, 60, 64 } }, 1378 { 11, { 100, 104, 108, 112, 116, 120, 124, 128, 132, 136, 140 } }, 1379 { 6, { 145, 149, 153, 157, 161, 165 } }, 1380 /* 40MHz channels (primary channels), 2GHz band. */ 1381 { 7, { 1, 2, 3, 4, 5, 6, 7 } }, 1382 /* 40MHz channels (primary channels), 5GHz band. */ 1383 { 11, { 36, 44, 52, 60, 100, 108, 116, 124, 132, 149, 157 } } 1384 }; 1385 1386 #define IWN1000_OTP_NBLOCKS 3 1387 #define IWN6000_OTP_NBLOCKS 4 1388 #define IWN6050_OTP_NBLOCKS 7 1389 1390 /* HW rate indices. */ 1391 #define IWN_RIDX_CCK1 0 1392 #define IWN_RIDX_CCK11 3 1393 #define IWN_RIDX_OFDM6 4 1394 #define IWN_RIDX_OFDM54 11 1395 1396 static const struct iwn_rate { 1397 uint8_t rate; 1398 uint8_t plcp; 1399 uint8_t flags; 1400 } iwn_rates[IWN_RIDX_MAX + 1] = { 1401 { 2, 10, IWN_RFLAG_CCK }, 1402 { 4, 20, IWN_RFLAG_CCK }, 1403 { 11, 55, IWN_RFLAG_CCK }, 1404 { 22, 110, IWN_RFLAG_CCK }, 1405 { 12, 0xd, 0 }, 1406 { 18, 0xf, 0 }, 1407 { 24, 0x5, 0 }, 1408 { 36, 0x7, 0 }, 1409 { 48, 0x9, 0 }, 1410 { 72, 0xb, 0 }, 1411 { 96, 0x1, 0 }, 1412 { 108, 0x3, 0 }, 1413 { 120, 0x3, 0 } 1414 }; 1415 1416 #define IWN4965_MAX_PWR_INDEX 107 1417 1418 /* 1419 * RF Tx gain values from highest to lowest power (values obtained from 1420 * the reference driver.) 1421 */ 1422 static const uint8_t iwn4965_rf_gain_2ghz[IWN4965_MAX_PWR_INDEX + 1] = { 1423 0x3f, 0x3f, 0x3f, 0x3e, 0x3e, 0x3e, 0x3d, 0x3d, 0x3d, 0x3c, 0x3c, 1424 0x3c, 0x3b, 0x3b, 0x3b, 0x3a, 0x3a, 0x3a, 0x39, 0x39, 0x39, 0x38, 1425 0x38, 0x38, 0x37, 0x37, 0x37, 0x36, 0x36, 0x36, 0x35, 0x35, 0x35, 1426 0x34, 0x34, 0x34, 0x33, 0x33, 0x33, 0x32, 0x32, 0x32, 0x31, 0x31, 1427 0x31, 0x30, 0x30, 0x30, 0x06, 0x06, 0x06, 0x05, 0x05, 0x05, 0x04, 1428 0x04, 0x04, 0x03, 0x03, 0x03, 0x02, 0x02, 0x02, 0x01, 0x01, 0x01, 1429 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 1430 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 1431 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 1432 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 1433 }; 1434 1435 static const uint8_t iwn4965_rf_gain_5ghz[IWN4965_MAX_PWR_INDEX + 1] = { 1436 0x3f, 0x3f, 0x3f, 0x3f, 0x3f, 0x3e, 0x3e, 0x3e, 0x3d, 0x3d, 0x3d, 1437 0x3c, 0x3c, 0x3c, 0x3b, 0x3b, 0x3b, 0x3a, 0x3a, 0x3a, 0x39, 0x39, 1438 0x39, 0x38, 0x38, 0x38, 0x37, 0x37, 0x37, 0x36, 0x36, 0x36, 0x35, 1439 0x35, 0x35, 0x34, 0x34, 0x34, 0x33, 0x33, 0x33, 0x32, 0x32, 0x32, 1440 0x31, 0x31, 0x31, 0x30, 0x30, 0x30, 0x25, 0x25, 0x25, 0x24, 0x24, 1441 0x24, 0x23, 0x23, 0x23, 0x22, 0x18, 0x18, 0x17, 0x17, 0x17, 0x16, 1442 0x16, 0x16, 0x15, 0x15, 0x15, 0x14, 0x14, 0x14, 0x13, 0x13, 0x13, 1443 0x12, 0x08, 0x08, 0x07, 0x07, 0x07, 0x06, 0x06, 0x06, 0x05, 0x05, 1444 0x05, 0x04, 0x04, 0x04, 0x03, 0x03, 0x03, 0x02, 0x02, 0x02, 0x01, 1445 0x01, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 1446 }; 1447 1448 /* 1449 * DSP pre-DAC gain values from highest to lowest power (values obtained 1450 * from the reference driver.) 1451 */ 1452 static const uint8_t iwn4965_dsp_gain_2ghz[IWN4965_MAX_PWR_INDEX + 1] = { 1453 0x6e, 0x68, 0x62, 0x6e, 0x68, 0x62, 0x6e, 0x68, 0x62, 0x6e, 0x68, 1454 0x62, 0x6e, 0x68, 0x62, 0x6e, 0x68, 0x62, 0x6e, 0x68, 0x62, 0x6e, 1455 0x68, 0x62, 0x6e, 0x68, 0x62, 0x6e, 0x68, 0x62, 0x6e, 0x68, 0x62, 1456 0x6e, 0x68, 0x62, 0x6e, 0x68, 0x62, 0x6e, 0x68, 0x62, 0x6e, 0x68, 1457 0x62, 0x6e, 0x68, 0x62, 0x6e, 0x68, 0x62, 0x6e, 0x68, 0x62, 0x6e, 1458 0x68, 0x62, 0x6e, 0x68, 0x62, 0x6e, 0x68, 0x62, 0x6e, 0x68, 0x62, 1459 0x6e, 0x68, 0x62, 0x61, 0x60, 0x5f, 0x5e, 0x5d, 0x5c, 0x5b, 0x5a, 1460 0x59, 0x58, 0x57, 0x56, 0x55, 0x54, 0x53, 0x52, 0x51, 0x50, 0x4f, 1461 0x4e, 0x4d, 0x4c, 0x4b, 0x4a, 0x49, 0x48, 0x47, 0x46, 0x45, 0x44, 1462 0x43, 0x42, 0x41, 0x40, 0x3f, 0x3e, 0x3d, 0x3c, 0x3b 1463 }; 1464 1465 static const uint8_t iwn4965_dsp_gain_5ghz[IWN4965_MAX_PWR_INDEX + 1] = { 1466 0x7b, 0x75, 0x6e, 0x68, 0x62, 0x6e, 0x68, 0x62, 0x6e, 0x68, 0x62, 1467 0x6e, 0x68, 0x62, 0x6e, 0x68, 0x62, 0x6e, 0x68, 0x62, 0x6e, 0x68, 1468 0x62, 0x6e, 0x68, 0x62, 0x6e, 0x68, 0x62, 0x6e, 0x68, 0x62, 0x6e, 1469 0x68, 0x62, 0x6e, 0x68, 0x62, 0x6e, 0x68, 0x62, 0x6e, 0x68, 0x62, 1470 0x6e, 0x68, 0x62, 0x6e, 0x68, 0x62, 0x6e, 0x68, 0x62, 0x6e, 0x68, 1471 0x62, 0x6e, 0x68, 0x62, 0x6e, 0x68, 0x62, 0x6e, 0x68, 0x62, 0x6e, 1472 0x68, 0x62, 0x6e, 0x68, 0x62, 0x6e, 0x68, 0x62, 0x6e, 0x68, 0x62, 1473 0x6e, 0x68, 0x62, 0x6e, 0x68, 0x62, 0x6e, 0x68, 0x62, 0x6e, 0x68, 1474 0x62, 0x6e, 0x68, 0x62, 0x6e, 0x68, 0x62, 0x6e, 0x68, 0x62, 0x6e, 1475 0x68, 0x62, 0x6e, 0x68, 0x62, 0x5d, 0x58, 0x53, 0x4e 1476 }; 1477 1478 /* 1479 * Power saving settings (values obtained from the reference driver.) 1480 */ 1481 #define IWN_NDTIMRANGES 3 1482 #define IWN_NPOWERLEVELS 6 1483 static const struct iwn_pmgt { 1484 uint32_t rxtimeout; 1485 uint32_t txtimeout; 1486 uint32_t intval[5]; 1487 int skip_dtim; 1488 } iwn_pmgt[IWN_NDTIMRANGES][IWN_NPOWERLEVELS] = { 1489 /* DTIM <= 2 */ 1490 { 1491 { 0, 0, { 0, 0, 0, 0, 0 }, 0 }, /* CAM */ 1492 { 200, 500, { 1, 2, 2, 2, -1 }, 0 }, /* PS level 1 */ 1493 { 200, 300, { 1, 2, 2, 2, -1 }, 0 }, /* PS level 2 */ 1494 { 50, 100, { 2, 2, 2, 2, -1 }, 0 }, /* PS level 3 */ 1495 { 50, 25, { 2, 2, 4, 4, -1 }, 1 }, /* PS level 4 */ 1496 { 25, 25, { 2, 2, 4, 6, -1 }, 2 } /* PS level 5 */ 1497 }, 1498 /* 3 <= DTIM <= 10 */ 1499 { 1500 { 0, 0, { 0, 0, 0, 0, 0 }, 0 }, /* CAM */ 1501 { 200, 500, { 1, 2, 3, 4, 4 }, 0 }, /* PS level 1 */ 1502 { 200, 300, { 1, 2, 3, 4, 7 }, 0 }, /* PS level 2 */ 1503 { 50, 100, { 2, 4, 6, 7, 9 }, 0 }, /* PS level 3 */ 1504 { 50, 25, { 2, 4, 6, 9, 10 }, 1 }, /* PS level 4 */ 1505 { 25, 25, { 2, 4, 7, 10, 10 }, 2 } /* PS level 5 */ 1506 }, 1507 /* DTIM >= 11 */ 1508 { 1509 { 0, 0, { 0, 0, 0, 0, 0 }, 0 }, /* CAM */ 1510 { 200, 500, { 1, 2, 3, 4, -1 }, 0 }, /* PS level 1 */ 1511 { 200, 300, { 2, 4, 6, 7, -1 }, 0 }, /* PS level 2 */ 1512 { 50, 100, { 2, 7, 9, 9, -1 }, 0 }, /* PS level 3 */ 1513 { 50, 25, { 2, 7, 9, 9, -1 }, 0 }, /* PS level 4 */ 1514 { 25, 25, { 4, 7, 10, 10, -1 }, 0 } /* PS level 5 */ 1515 } 1516 }; 1517 1518 struct iwn_sensitivity_limits { 1519 uint32_t min_ofdm_x1; 1520 uint32_t max_ofdm_x1; 1521 uint32_t min_ofdm_mrc_x1; 1522 uint32_t max_ofdm_mrc_x1; 1523 uint32_t min_ofdm_x4; 1524 uint32_t max_ofdm_x4; 1525 uint32_t min_ofdm_mrc_x4; 1526 uint32_t max_ofdm_mrc_x4; 1527 uint32_t min_cck_x4; 1528 uint32_t max_cck_x4; 1529 uint32_t min_cck_mrc_x4; 1530 uint32_t max_cck_mrc_x4; 1531 uint32_t min_energy_cck; 1532 uint32_t energy_cck; 1533 uint32_t energy_ofdm; 1534 }; 1535 1536 /* 1537 * RX sensitivity limits (values obtained from the reference driver.) 1538 */ 1539 static const struct iwn_sensitivity_limits iwn4965_sensitivity_limits = { 1540 105, 140, 1541 220, 270, 1542 85, 120, 1543 170, 210, 1544 125, 200, 1545 200, 400, 1546 97, 1547 100, 1548 100 1549 }; 1550 1551 static const struct iwn_sensitivity_limits iwn5000_sensitivity_limits = { 1552 120, 155, 1553 240, 290, 1554 90, 120, 1555 170, 210, 1556 125, 200, 1557 170, 400, 1558 95, 1559 95, 1560 95 1561 }; 1562 1563 static const struct iwn_sensitivity_limits iwn5150_sensitivity_limits = { 1564 105, 105, /* min = max for performance bug in DSP. */ 1565 220, 220, /* min = max for performance bug in DSP. */ 1566 90, 120, 1567 170, 210, 1568 125, 200, 1569 170, 400, 1570 95, 1571 95, 1572 95 1573 }; 1574 1575 static const struct iwn_sensitivity_limits iwn6000_sensitivity_limits = { 1576 105, 145, 1577 192, 232, 1578 80, 145, 1579 128, 232, 1580 125, 175, 1581 160, 310, 1582 97, 1583 97, 1584 100 1585 }; 1586 1587 /* Map TID to TX scheduler's FIFO. */ 1588 static const uint8_t iwn_tid2fifo[] = { 1589 1, 0, 0, 1, 2, 2, 3, 3, 7, 7, 7, 7, 7, 7, 7, 7, 3 1590 }; 1591 1592 /* WiFi/WiMAX coexist event priority table for 6050. */ 1593 static const struct iwn5000_wimax_event iwn6050_wimax_events[] = { 1594 { 0x04, 0x03, 0x00, 0x00 }, 1595 { 0x04, 0x03, 0x00, 0x03 }, 1596 { 0x04, 0x03, 0x00, 0x03 }, 1597 { 0x04, 0x03, 0x00, 0x03 }, 1598 { 0x04, 0x03, 0x00, 0x00 }, 1599 { 0x04, 0x03, 0x00, 0x07 }, 1600 { 0x04, 0x03, 0x00, 0x00 }, 1601 { 0x04, 0x03, 0x00, 0x03 }, 1602 { 0x04, 0x03, 0x00, 0x03 }, 1603 { 0x04, 0x03, 0x00, 0x00 }, 1604 { 0x06, 0x03, 0x00, 0x07 }, 1605 { 0x04, 0x03, 0x00, 0x00 }, 1606 { 0x06, 0x06, 0x00, 0x03 }, 1607 { 0x04, 0x03, 0x00, 0x07 }, 1608 { 0x04, 0x03, 0x00, 0x00 }, 1609 { 0x04, 0x03, 0x00, 0x00 } 1610 }; 1611 1612 /* Firmware errors. */ 1613 static const char * const iwn_fw_errmsg[] = { 1614 "OK", 1615 "FAIL", 1616 "BAD_PARAM", 1617 "BAD_CHECKSUM", 1618 "NMI_INTERRUPT_WDG", 1619 "SYSASSERT", 1620 "FATAL_ERROR", 1621 "BAD_COMMAND", 1622 "HW_ERROR_TUNE_LOCK", 1623 "HW_ERROR_TEMPERATURE", 1624 "ILLEGAL_CHAN_FREQ", 1625 "VCC_NOT_STABLE", 1626 "FH_ERROR", 1627 "NMI_INTERRUPT_HOST", 1628 "NMI_INTERRUPT_ACTION_PT", 1629 "NMI_INTERRUPT_UNKNOWN", 1630 "UCODE_VERSION_MISMATCH", 1631 "HW_ERROR_ABS_LOCK", 1632 "HW_ERROR_CAL_LOCK_FAIL", 1633 "NMI_INTERRUPT_INST_ACTION_PT", 1634 "NMI_INTERRUPT_DATA_ACTION_PT", 1635 "NMI_TRM_HW_ER", 1636 "NMI_INTERRUPT_TRM", 1637 "NMI_INTERRUPT_BREAKPOINT" 1638 "DEBUG_0", 1639 "DEBUG_1", 1640 "DEBUG_2", 1641 "DEBUG_3", 1642 "UNKNOWN" 1643 }; 1644 1645 /* Find least significant bit that is set. */ 1646 #define IWN_LSB(x) ((((x) - 1) & (x)) ^ (x)) 1647 1648 #define IWN_READ(sc, reg) \ 1649 bus_space_read_4((sc)->sc_st, (sc)->sc_sh, (reg)) 1650 1651 #define IWN_WRITE(sc, reg, val) \ 1652 bus_space_write_4((sc)->sc_st, (sc)->sc_sh, (reg), (val)) 1653 1654 #define IWN_WRITE_1(sc, reg, val) \ 1655 bus_space_write_1((sc)->sc_st, (sc)->sc_sh, (reg), (val)) 1656 1657 #define IWN_SETBITS(sc, reg, mask) \ 1658 IWN_WRITE(sc, reg, IWN_READ(sc, reg) | (mask)) 1659 1660 #define IWN_CLRBITS(sc, reg, mask) \ 1661 IWN_WRITE(sc, reg, IWN_READ(sc, reg) & ~(mask)) 1662 1663 #define IWN_BARRIER_WRITE(sc) \ 1664 bus_space_barrier((sc)->sc_st, (sc)->sc_sh, 0, (sc)->sc_sz, \ 1665 BUS_SPACE_BARRIER_WRITE) 1666 1667 #define IWN_BARRIER_READ_WRITE(sc) \ 1668 bus_space_barrier((sc)->sc_st, (sc)->sc_sh, 0, (sc)->sc_sz, \ 1669 BUS_SPACE_BARRIER_READ | BUS_SPACE_BARRIER_WRITE) 1670