1 /*- 2 * Copyright (c) 2007-2009 Damien Bergamini <damien.bergamini@free.fr> 3 * Copyright (c) 2008 Benjamin Close <benjsc@FreeBSD.org> 4 * Copyright (c) 2008 Sam Leffler, Errno Consulting 5 * Copyright (c) 2011 Intel Corporation 6 * Copyright (c) 2013 Cedric GROSS <c.gross@kreiz-it.fr> 7 * Copyright (c) 2013 Adrian Chadd <adrian@FreeBSD.org> 8 * 9 * Permission to use, copy, modify, and distribute this software for any 10 * purpose with or without fee is hereby granted, provided that the above 11 * copyright notice and this permission notice appear in all copies. 12 * 13 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 14 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 15 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR 16 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 17 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN 18 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF 19 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 20 */ 21 22 /* 23 * Driver for Intel WiFi Link 4965 and 1000/5000/6000 Series 802.11 network 24 * adapters. 25 */ 26 27 #include <sys/cdefs.h> 28 __FBSDID("$FreeBSD$"); 29 30 #include "opt_wlan.h" 31 #include "opt_iwn.h" 32 33 #include <sys/param.h> 34 #include <sys/sockio.h> 35 #include <sys/sysctl.h> 36 #include <sys/mbuf.h> 37 #include <sys/kernel.h> 38 #include <sys/socket.h> 39 #include <sys/systm.h> 40 #include <sys/malloc.h> 41 #include <sys/bus.h> 42 #include <sys/conf.h> 43 #include <sys/rman.h> 44 #include <sys/endian.h> 45 #include <sys/firmware.h> 46 #include <sys/limits.h> 47 #include <sys/module.h> 48 #include <sys/priv.h> 49 #include <sys/queue.h> 50 #include <sys/taskqueue.h> 51 52 #include <machine/bus.h> 53 #include <machine/resource.h> 54 #include <machine/clock.h> 55 56 #include <dev/pci/pcireg.h> 57 #include <dev/pci/pcivar.h> 58 59 #include <net/if.h> 60 #include <net/if_var.h> 61 #include <net/if_dl.h> 62 #include <net/if_media.h> 63 64 #include <netinet/in.h> 65 #include <netinet/if_ether.h> 66 67 #include <net80211/ieee80211_var.h> 68 #include <net80211/ieee80211_radiotap.h> 69 #include <net80211/ieee80211_regdomain.h> 70 #include <net80211/ieee80211_ratectl.h> 71 72 #include <dev/iwn/if_iwnreg.h> 73 #include <dev/iwn/if_iwnvar.h> 74 #include <dev/iwn/if_iwn_devid.h> 75 #include <dev/iwn/if_iwn_chip_cfg.h> 76 #include <dev/iwn/if_iwn_debug.h> 77 #include <dev/iwn/if_iwn_ioctl.h> 78 79 struct iwn_ident { 80 uint16_t vendor; 81 uint16_t device; 82 const char *name; 83 }; 84 85 static const struct iwn_ident iwn_ident_table[] = { 86 { 0x8086, IWN_DID_6x05_1, "Intel Centrino Advanced-N 6205" }, 87 { 0x8086, IWN_DID_1000_1, "Intel Centrino Wireless-N 1000" }, 88 { 0x8086, IWN_DID_1000_2, "Intel Centrino Wireless-N 1000" }, 89 { 0x8086, IWN_DID_6x05_2, "Intel Centrino Advanced-N 6205" }, 90 { 0x8086, IWN_DID_6050_1, "Intel Centrino Advanced-N + WiMAX 6250" }, 91 { 0x8086, IWN_DID_6050_2, "Intel Centrino Advanced-N + WiMAX 6250" }, 92 { 0x8086, IWN_DID_x030_1, "Intel Centrino Wireless-N 1030" }, 93 { 0x8086, IWN_DID_x030_2, "Intel Centrino Wireless-N 1030" }, 94 { 0x8086, IWN_DID_x030_3, "Intel Centrino Advanced-N 6230" }, 95 { 0x8086, IWN_DID_x030_4, "Intel Centrino Advanced-N 6230" }, 96 { 0x8086, IWN_DID_6150_1, "Intel Centrino Wireless-N + WiMAX 6150" }, 97 { 0x8086, IWN_DID_6150_2, "Intel Centrino Wireless-N + WiMAX 6150" }, 98 { 0x8086, IWN_DID_2x00_1, "Intel(R) Centrino(R) Wireless-N 2200 BGN" }, 99 { 0x8086, IWN_DID_2x00_2, "Intel(R) Centrino(R) Wireless-N 2200 BGN" }, 100 /* XXX 2200D is IWN_SDID_2x00_4; there's no way to express this here! */ 101 { 0x8086, IWN_DID_2x30_1, "Intel Centrino Wireless-N 2230" }, 102 { 0x8086, IWN_DID_2x30_2, "Intel Centrino Wireless-N 2230" }, 103 { 0x8086, IWN_DID_130_1, "Intel Centrino Wireless-N 130" }, 104 { 0x8086, IWN_DID_130_2, "Intel Centrino Wireless-N 130" }, 105 { 0x8086, IWN_DID_100_1, "Intel Centrino Wireless-N 100" }, 106 { 0x8086, IWN_DID_100_2, "Intel Centrino Wireless-N 100" }, 107 { 0x8086, IWN_DID_105_1, "Intel Centrino Wireless-N 105" }, 108 { 0x8086, IWN_DID_105_2, "Intel Centrino Wireless-N 105" }, 109 { 0x8086, IWN_DID_135_1, "Intel Centrino Wireless-N 135" }, 110 { 0x8086, IWN_DID_135_2, "Intel Centrino Wireless-N 135" }, 111 { 0x8086, IWN_DID_4965_1, "Intel Wireless WiFi Link 4965" }, 112 { 0x8086, IWN_DID_6x00_1, "Intel Centrino Ultimate-N 6300" }, 113 { 0x8086, IWN_DID_6x00_2, "Intel Centrino Advanced-N 6200" }, 114 { 0x8086, IWN_DID_4965_2, "Intel Wireless WiFi Link 4965" }, 115 { 0x8086, IWN_DID_4965_3, "Intel Wireless WiFi Link 4965" }, 116 { 0x8086, IWN_DID_5x00_1, "Intel WiFi Link 5100" }, 117 { 0x8086, IWN_DID_4965_4, "Intel Wireless WiFi Link 4965" }, 118 { 0x8086, IWN_DID_5x00_3, "Intel Ultimate N WiFi Link 5300" }, 119 { 0x8086, IWN_DID_5x00_4, "Intel Ultimate N WiFi Link 5300" }, 120 { 0x8086, IWN_DID_5x00_2, "Intel WiFi Link 5100" }, 121 { 0x8086, IWN_DID_6x00_3, "Intel Centrino Ultimate-N 6300" }, 122 { 0x8086, IWN_DID_6x00_4, "Intel Centrino Advanced-N 6200" }, 123 { 0x8086, IWN_DID_5x50_1, "Intel WiMAX/WiFi Link 5350" }, 124 { 0x8086, IWN_DID_5x50_2, "Intel WiMAX/WiFi Link 5350" }, 125 { 0x8086, IWN_DID_5x50_3, "Intel WiMAX/WiFi Link 5150" }, 126 { 0x8086, IWN_DID_5x50_4, "Intel WiMAX/WiFi Link 5150" }, 127 { 0x8086, IWN_DID_6035_1, "Intel Centrino Advanced 6235" }, 128 { 0x8086, IWN_DID_6035_2, "Intel Centrino Advanced 6235" }, 129 { 0, 0, NULL } 130 }; 131 132 static int iwn_probe(device_t); 133 static int iwn_attach(device_t); 134 static void iwn4965_attach(struct iwn_softc *, uint16_t); 135 static void iwn5000_attach(struct iwn_softc *, uint16_t); 136 static int iwn_config_specific(struct iwn_softc *, uint16_t); 137 static void iwn_radiotap_attach(struct iwn_softc *); 138 static void iwn_sysctlattach(struct iwn_softc *); 139 static struct ieee80211vap *iwn_vap_create(struct ieee80211com *, 140 const char [IFNAMSIZ], int, enum ieee80211_opmode, int, 141 const uint8_t [IEEE80211_ADDR_LEN], 142 const uint8_t [IEEE80211_ADDR_LEN]); 143 static void iwn_vap_delete(struct ieee80211vap *); 144 static int iwn_detach(device_t); 145 static int iwn_shutdown(device_t); 146 static int iwn_suspend(device_t); 147 static int iwn_resume(device_t); 148 static int iwn_nic_lock(struct iwn_softc *); 149 static int iwn_eeprom_lock(struct iwn_softc *); 150 static int iwn_init_otprom(struct iwn_softc *); 151 static int iwn_read_prom_data(struct iwn_softc *, uint32_t, void *, int); 152 static void iwn_dma_map_addr(void *, bus_dma_segment_t *, int, int); 153 static int iwn_dma_contig_alloc(struct iwn_softc *, struct iwn_dma_info *, 154 void **, bus_size_t, bus_size_t); 155 static void iwn_dma_contig_free(struct iwn_dma_info *); 156 static int iwn_alloc_sched(struct iwn_softc *); 157 static void iwn_free_sched(struct iwn_softc *); 158 static int iwn_alloc_kw(struct iwn_softc *); 159 static void iwn_free_kw(struct iwn_softc *); 160 static int iwn_alloc_ict(struct iwn_softc *); 161 static void iwn_free_ict(struct iwn_softc *); 162 static int iwn_alloc_fwmem(struct iwn_softc *); 163 static void iwn_free_fwmem(struct iwn_softc *); 164 static int iwn_alloc_rx_ring(struct iwn_softc *, struct iwn_rx_ring *); 165 static void iwn_reset_rx_ring(struct iwn_softc *, struct iwn_rx_ring *); 166 static void iwn_free_rx_ring(struct iwn_softc *, struct iwn_rx_ring *); 167 static int iwn_alloc_tx_ring(struct iwn_softc *, struct iwn_tx_ring *, 168 int); 169 static void iwn_reset_tx_ring(struct iwn_softc *, struct iwn_tx_ring *); 170 static void iwn_free_tx_ring(struct iwn_softc *, struct iwn_tx_ring *); 171 static void iwn_check_tx_ring(struct iwn_softc *, int); 172 static void iwn5000_ict_reset(struct iwn_softc *); 173 static int iwn_read_eeprom(struct iwn_softc *, 174 uint8_t macaddr[IEEE80211_ADDR_LEN]); 175 static void iwn4965_read_eeprom(struct iwn_softc *); 176 #ifdef IWN_DEBUG 177 static void iwn4965_print_power_group(struct iwn_softc *, int); 178 #endif 179 static void iwn5000_read_eeprom(struct iwn_softc *); 180 static uint32_t iwn_eeprom_channel_flags(struct iwn_eeprom_chan *); 181 static void iwn_read_eeprom_band(struct iwn_softc *, int, int, int *, 182 struct ieee80211_channel[]); 183 static void iwn_read_eeprom_ht40(struct iwn_softc *, int, int, int *, 184 struct ieee80211_channel[]); 185 static void iwn_read_eeprom_channels(struct iwn_softc *, int, uint32_t); 186 static struct iwn_eeprom_chan *iwn_find_eeprom_channel(struct iwn_softc *, 187 struct ieee80211_channel *); 188 static void iwn_getradiocaps(struct ieee80211com *, int, int *, 189 struct ieee80211_channel[]); 190 static int iwn_setregdomain(struct ieee80211com *, 191 struct ieee80211_regdomain *, int, 192 struct ieee80211_channel[]); 193 static void iwn_read_eeprom_enhinfo(struct iwn_softc *); 194 static struct ieee80211_node *iwn_node_alloc(struct ieee80211vap *, 195 const uint8_t mac[IEEE80211_ADDR_LEN]); 196 static void iwn_newassoc(struct ieee80211_node *, int); 197 static int iwn_media_change(struct ifnet *); 198 static int iwn_newstate(struct ieee80211vap *, enum ieee80211_state, int); 199 static void iwn_calib_timeout(void *); 200 static void iwn_rx_phy(struct iwn_softc *, struct iwn_rx_desc *); 201 static void iwn_rx_done(struct iwn_softc *, struct iwn_rx_desc *, 202 struct iwn_rx_data *); 203 static void iwn_agg_tx_complete(struct iwn_softc *, struct iwn_tx_ring *, 204 int, int, int); 205 static void iwn_rx_compressed_ba(struct iwn_softc *, struct iwn_rx_desc *); 206 static void iwn5000_rx_calib_results(struct iwn_softc *, 207 struct iwn_rx_desc *); 208 static void iwn_rx_statistics(struct iwn_softc *, struct iwn_rx_desc *); 209 static void iwn4965_tx_done(struct iwn_softc *, struct iwn_rx_desc *, 210 struct iwn_rx_data *); 211 static void iwn5000_tx_done(struct iwn_softc *, struct iwn_rx_desc *, 212 struct iwn_rx_data *); 213 static void iwn_adj_ampdu_ptr(struct iwn_softc *, struct iwn_tx_ring *); 214 static void iwn_tx_done(struct iwn_softc *, struct iwn_rx_desc *, int, int, 215 uint8_t); 216 static int iwn_ampdu_check_bitmap(uint64_t, int, int); 217 static int iwn_ampdu_index_check(struct iwn_softc *, struct iwn_tx_ring *, 218 uint64_t, int, int); 219 static void iwn_ampdu_tx_done(struct iwn_softc *, int, int, int, void *); 220 static void iwn_cmd_done(struct iwn_softc *, struct iwn_rx_desc *); 221 static void iwn_notif_intr(struct iwn_softc *); 222 static void iwn_wakeup_intr(struct iwn_softc *); 223 static void iwn_rftoggle_task(void *, int); 224 static void iwn_fatal_intr(struct iwn_softc *); 225 static void iwn_intr(void *); 226 static void iwn4965_update_sched(struct iwn_softc *, int, int, uint8_t, 227 uint16_t); 228 static void iwn5000_update_sched(struct iwn_softc *, int, int, uint8_t, 229 uint16_t); 230 #ifdef notyet 231 static void iwn5000_reset_sched(struct iwn_softc *, int, int); 232 #endif 233 static int iwn_tx_data(struct iwn_softc *, struct mbuf *, 234 struct ieee80211_node *); 235 static int iwn_tx_data_raw(struct iwn_softc *, struct mbuf *, 236 struct ieee80211_node *, 237 const struct ieee80211_bpf_params *params); 238 static int iwn_tx_cmd(struct iwn_softc *, struct mbuf *, 239 struct ieee80211_node *, struct iwn_tx_ring *); 240 static void iwn_xmit_task(void *arg0, int pending); 241 static int iwn_raw_xmit(struct ieee80211_node *, struct mbuf *, 242 const struct ieee80211_bpf_params *); 243 static int iwn_transmit(struct ieee80211com *, struct mbuf *); 244 static void iwn_scan_timeout(void *); 245 static void iwn_watchdog(void *); 246 static int iwn_ioctl(struct ieee80211com *, u_long , void *); 247 static void iwn_parent(struct ieee80211com *); 248 static int iwn_cmd(struct iwn_softc *, int, const void *, int, int); 249 static int iwn4965_add_node(struct iwn_softc *, struct iwn_node_info *, 250 int); 251 static int iwn5000_add_node(struct iwn_softc *, struct iwn_node_info *, 252 int); 253 static int iwn_set_link_quality(struct iwn_softc *, 254 struct ieee80211_node *); 255 static int iwn_add_broadcast_node(struct iwn_softc *, int); 256 static int iwn_updateedca(struct ieee80211com *); 257 static void iwn_set_promisc(struct iwn_softc *); 258 static void iwn_update_promisc(struct ieee80211com *); 259 static void iwn_update_mcast(struct ieee80211com *); 260 static void iwn_set_led(struct iwn_softc *, uint8_t, uint8_t, uint8_t); 261 static int iwn_set_critical_temp(struct iwn_softc *); 262 static int iwn_set_timing(struct iwn_softc *, struct ieee80211_node *); 263 static void iwn4965_power_calibration(struct iwn_softc *, int); 264 static int iwn4965_set_txpower(struct iwn_softc *, int); 265 static int iwn5000_set_txpower(struct iwn_softc *, int); 266 static int iwn4965_get_rssi(struct iwn_softc *, struct iwn_rx_stat *); 267 static int iwn5000_get_rssi(struct iwn_softc *, struct iwn_rx_stat *); 268 static int iwn_get_noise(const struct iwn_rx_general_stats *); 269 static int iwn4965_get_temperature(struct iwn_softc *); 270 static int iwn5000_get_temperature(struct iwn_softc *); 271 static int iwn_init_sensitivity(struct iwn_softc *); 272 static void iwn_collect_noise(struct iwn_softc *, 273 const struct iwn_rx_general_stats *); 274 static int iwn4965_init_gains(struct iwn_softc *); 275 static int iwn5000_init_gains(struct iwn_softc *); 276 static int iwn4965_set_gains(struct iwn_softc *); 277 static int iwn5000_set_gains(struct iwn_softc *); 278 static void iwn_tune_sensitivity(struct iwn_softc *, 279 const struct iwn_rx_stats *); 280 static void iwn_save_stats_counters(struct iwn_softc *, 281 const struct iwn_stats *); 282 static int iwn_send_sensitivity(struct iwn_softc *); 283 static void iwn_check_rx_recovery(struct iwn_softc *, struct iwn_stats *); 284 static int iwn_set_pslevel(struct iwn_softc *, int, int, int); 285 static int iwn_send_btcoex(struct iwn_softc *); 286 static int iwn_send_advanced_btcoex(struct iwn_softc *); 287 static int iwn5000_runtime_calib(struct iwn_softc *); 288 static int iwn_check_bss_filter(struct iwn_softc *); 289 static int iwn4965_rxon_assoc(struct iwn_softc *, int); 290 static int iwn5000_rxon_assoc(struct iwn_softc *, int); 291 static int iwn_send_rxon(struct iwn_softc *, int, int); 292 static int iwn_config(struct iwn_softc *); 293 static int iwn_scan(struct iwn_softc *, struct ieee80211vap *, 294 struct ieee80211_scan_state *, struct ieee80211_channel *); 295 static int iwn_auth(struct iwn_softc *, struct ieee80211vap *vap); 296 static int iwn_run(struct iwn_softc *, struct ieee80211vap *vap); 297 static int iwn_ampdu_rx_start(struct ieee80211_node *, 298 struct ieee80211_rx_ampdu *, int, int, int); 299 static void iwn_ampdu_rx_stop(struct ieee80211_node *, 300 struct ieee80211_rx_ampdu *); 301 static int iwn_addba_request(struct ieee80211_node *, 302 struct ieee80211_tx_ampdu *, int, int, int); 303 static int iwn_addba_response(struct ieee80211_node *, 304 struct ieee80211_tx_ampdu *, int, int, int); 305 static int iwn_ampdu_tx_start(struct ieee80211com *, 306 struct ieee80211_node *, uint8_t); 307 static void iwn_ampdu_tx_stop(struct ieee80211_node *, 308 struct ieee80211_tx_ampdu *); 309 static void iwn4965_ampdu_tx_start(struct iwn_softc *, 310 struct ieee80211_node *, int, uint8_t, uint16_t); 311 static void iwn4965_ampdu_tx_stop(struct iwn_softc *, int, 312 uint8_t, uint16_t); 313 static void iwn5000_ampdu_tx_start(struct iwn_softc *, 314 struct ieee80211_node *, int, uint8_t, uint16_t); 315 static void iwn5000_ampdu_tx_stop(struct iwn_softc *, int, 316 uint8_t, uint16_t); 317 static int iwn5000_query_calibration(struct iwn_softc *); 318 static int iwn5000_send_calibration(struct iwn_softc *); 319 static int iwn5000_send_wimax_coex(struct iwn_softc *); 320 static int iwn5000_crystal_calib(struct iwn_softc *); 321 static int iwn5000_temp_offset_calib(struct iwn_softc *); 322 static int iwn5000_temp_offset_calibv2(struct iwn_softc *); 323 static int iwn4965_post_alive(struct iwn_softc *); 324 static int iwn5000_post_alive(struct iwn_softc *); 325 static int iwn4965_load_bootcode(struct iwn_softc *, const uint8_t *, 326 int); 327 static int iwn4965_load_firmware(struct iwn_softc *); 328 static int iwn5000_load_firmware_section(struct iwn_softc *, uint32_t, 329 const uint8_t *, int); 330 static int iwn5000_load_firmware(struct iwn_softc *); 331 static int iwn_read_firmware_leg(struct iwn_softc *, 332 struct iwn_fw_info *); 333 static int iwn_read_firmware_tlv(struct iwn_softc *, 334 struct iwn_fw_info *, uint16_t); 335 static int iwn_read_firmware(struct iwn_softc *); 336 static void iwn_unload_firmware(struct iwn_softc *); 337 static int iwn_clock_wait(struct iwn_softc *); 338 static int iwn_apm_init(struct iwn_softc *); 339 static void iwn_apm_stop_master(struct iwn_softc *); 340 static void iwn_apm_stop(struct iwn_softc *); 341 static int iwn4965_nic_config(struct iwn_softc *); 342 static int iwn5000_nic_config(struct iwn_softc *); 343 static int iwn_hw_prepare(struct iwn_softc *); 344 static int iwn_hw_init(struct iwn_softc *); 345 static void iwn_hw_stop(struct iwn_softc *); 346 static void iwn_panicked(void *, int); 347 static int iwn_init_locked(struct iwn_softc *); 348 static int iwn_init(struct iwn_softc *); 349 static void iwn_stop_locked(struct iwn_softc *); 350 static void iwn_stop(struct iwn_softc *); 351 static void iwn_scan_start(struct ieee80211com *); 352 static void iwn_scan_end(struct ieee80211com *); 353 static void iwn_set_channel(struct ieee80211com *); 354 static void iwn_scan_curchan(struct ieee80211_scan_state *, unsigned long); 355 static void iwn_scan_mindwell(struct ieee80211_scan_state *); 356 #ifdef IWN_DEBUG 357 static char *iwn_get_csr_string(int); 358 static void iwn_debug_register(struct iwn_softc *); 359 #endif 360 361 static device_method_t iwn_methods[] = { 362 /* Device interface */ 363 DEVMETHOD(device_probe, iwn_probe), 364 DEVMETHOD(device_attach, iwn_attach), 365 DEVMETHOD(device_detach, iwn_detach), 366 DEVMETHOD(device_shutdown, iwn_shutdown), 367 DEVMETHOD(device_suspend, iwn_suspend), 368 DEVMETHOD(device_resume, iwn_resume), 369 370 DEVMETHOD_END 371 }; 372 373 static driver_t iwn_driver = { 374 "iwn", 375 iwn_methods, 376 sizeof(struct iwn_softc) 377 }; 378 static devclass_t iwn_devclass; 379 380 DRIVER_MODULE(iwn, pci, iwn_driver, iwn_devclass, NULL, NULL); 381 MODULE_PNP_INFO("U16:vendor;U16:device;D:#", pci, iwn, iwn_ident_table, 382 nitems(iwn_ident_table) - 1); 383 MODULE_VERSION(iwn, 1); 384 385 MODULE_DEPEND(iwn, firmware, 1, 1, 1); 386 MODULE_DEPEND(iwn, pci, 1, 1, 1); 387 MODULE_DEPEND(iwn, wlan, 1, 1, 1); 388 389 static d_ioctl_t iwn_cdev_ioctl; 390 static d_open_t iwn_cdev_open; 391 static d_close_t iwn_cdev_close; 392 393 static struct cdevsw iwn_cdevsw = { 394 .d_version = D_VERSION, 395 .d_flags = 0, 396 .d_open = iwn_cdev_open, 397 .d_close = iwn_cdev_close, 398 .d_ioctl = iwn_cdev_ioctl, 399 .d_name = "iwn", 400 }; 401 402 static int 403 iwn_probe(device_t dev) 404 { 405 const struct iwn_ident *ident; 406 407 for (ident = iwn_ident_table; ident->name != NULL; ident++) { 408 if (pci_get_vendor(dev) == ident->vendor && 409 pci_get_device(dev) == ident->device) { 410 device_set_desc(dev, ident->name); 411 return (BUS_PROBE_DEFAULT); 412 } 413 } 414 return ENXIO; 415 } 416 417 static int 418 iwn_is_3stream_device(struct iwn_softc *sc) 419 { 420 /* XXX for now only 5300, until the 5350 can be tested */ 421 if (sc->hw_type == IWN_HW_REV_TYPE_5300) 422 return (1); 423 return (0); 424 } 425 426 static int 427 iwn_attach(device_t dev) 428 { 429 struct iwn_softc *sc = device_get_softc(dev); 430 struct ieee80211com *ic; 431 int i, error, rid; 432 433 sc->sc_dev = dev; 434 435 #ifdef IWN_DEBUG 436 error = resource_int_value(device_get_name(sc->sc_dev), 437 device_get_unit(sc->sc_dev), "debug", &(sc->sc_debug)); 438 if (error != 0) 439 sc->sc_debug = 0; 440 #else 441 sc->sc_debug = 0; 442 #endif 443 444 DPRINTF(sc, IWN_DEBUG_TRACE, "->%s: begin\n",__func__); 445 446 /* 447 * Get the offset of the PCI Express Capability Structure in PCI 448 * Configuration Space. 449 */ 450 error = pci_find_cap(dev, PCIY_EXPRESS, &sc->sc_cap_off); 451 if (error != 0) { 452 device_printf(dev, "PCIe capability structure not found!\n"); 453 return error; 454 } 455 456 /* Clear device-specific "PCI retry timeout" register (41h). */ 457 pci_write_config(dev, 0x41, 0, 1); 458 459 /* Enable bus-mastering. */ 460 pci_enable_busmaster(dev); 461 462 rid = PCIR_BAR(0); 463 sc->mem = bus_alloc_resource_any(dev, SYS_RES_MEMORY, &rid, 464 RF_ACTIVE); 465 if (sc->mem == NULL) { 466 device_printf(dev, "can't map mem space\n"); 467 error = ENOMEM; 468 return error; 469 } 470 sc->sc_st = rman_get_bustag(sc->mem); 471 sc->sc_sh = rman_get_bushandle(sc->mem); 472 473 i = 1; 474 rid = 0; 475 if (pci_alloc_msi(dev, &i) == 0) 476 rid = 1; 477 /* Install interrupt handler. */ 478 sc->irq = bus_alloc_resource_any(dev, SYS_RES_IRQ, &rid, RF_ACTIVE | 479 (rid != 0 ? 0 : RF_SHAREABLE)); 480 if (sc->irq == NULL) { 481 device_printf(dev, "can't map interrupt\n"); 482 error = ENOMEM; 483 goto fail; 484 } 485 486 IWN_LOCK_INIT(sc); 487 488 /* Read hardware revision and attach. */ 489 sc->hw_type = (IWN_READ(sc, IWN_HW_REV) >> IWN_HW_REV_TYPE_SHIFT) 490 & IWN_HW_REV_TYPE_MASK; 491 sc->subdevice_id = pci_get_subdevice(dev); 492 493 /* 494 * 4965 versus 5000 and later have different methods. 495 * Let's set those up first. 496 */ 497 if (sc->hw_type == IWN_HW_REV_TYPE_4965) 498 iwn4965_attach(sc, pci_get_device(dev)); 499 else 500 iwn5000_attach(sc, pci_get_device(dev)); 501 502 /* 503 * Next, let's setup the various parameters of each NIC. 504 */ 505 error = iwn_config_specific(sc, pci_get_device(dev)); 506 if (error != 0) { 507 device_printf(dev, "could not attach device, error %d\n", 508 error); 509 goto fail; 510 } 511 512 if ((error = iwn_hw_prepare(sc)) != 0) { 513 device_printf(dev, "hardware not ready, error %d\n", error); 514 goto fail; 515 } 516 517 /* Allocate DMA memory for firmware transfers. */ 518 if ((error = iwn_alloc_fwmem(sc)) != 0) { 519 device_printf(dev, 520 "could not allocate memory for firmware, error %d\n", 521 error); 522 goto fail; 523 } 524 525 /* Allocate "Keep Warm" page. */ 526 if ((error = iwn_alloc_kw(sc)) != 0) { 527 device_printf(dev, 528 "could not allocate keep warm page, error %d\n", error); 529 goto fail; 530 } 531 532 /* Allocate ICT table for 5000 Series. */ 533 if (sc->hw_type != IWN_HW_REV_TYPE_4965 && 534 (error = iwn_alloc_ict(sc)) != 0) { 535 device_printf(dev, "could not allocate ICT table, error %d\n", 536 error); 537 goto fail; 538 } 539 540 /* Allocate TX scheduler "rings". */ 541 if ((error = iwn_alloc_sched(sc)) != 0) { 542 device_printf(dev, 543 "could not allocate TX scheduler rings, error %d\n", error); 544 goto fail; 545 } 546 547 /* Allocate TX rings (16 on 4965AGN, 20 on >=5000). */ 548 for (i = 0; i < sc->ntxqs; i++) { 549 if ((error = iwn_alloc_tx_ring(sc, &sc->txq[i], i)) != 0) { 550 device_printf(dev, 551 "could not allocate TX ring %d, error %d\n", i, 552 error); 553 goto fail; 554 } 555 } 556 557 /* Allocate RX ring. */ 558 if ((error = iwn_alloc_rx_ring(sc, &sc->rxq)) != 0) { 559 device_printf(dev, "could not allocate RX ring, error %d\n", 560 error); 561 goto fail; 562 } 563 564 /* Clear pending interrupts. */ 565 IWN_WRITE(sc, IWN_INT, 0xffffffff); 566 567 ic = &sc->sc_ic; 568 ic->ic_softc = sc; 569 ic->ic_name = device_get_nameunit(dev); 570 ic->ic_phytype = IEEE80211_T_OFDM; /* not only, but not used */ 571 ic->ic_opmode = IEEE80211_M_STA; /* default to BSS mode */ 572 573 /* Set device capabilities. */ 574 ic->ic_caps = 575 IEEE80211_C_STA /* station mode supported */ 576 | IEEE80211_C_MONITOR /* monitor mode supported */ 577 #if 0 578 | IEEE80211_C_BGSCAN /* background scanning */ 579 #endif 580 | IEEE80211_C_TXPMGT /* tx power management */ 581 | IEEE80211_C_SHSLOT /* short slot time supported */ 582 | IEEE80211_C_WPA 583 | IEEE80211_C_SHPREAMBLE /* short preamble supported */ 584 #if 0 585 | IEEE80211_C_IBSS /* ibss/adhoc mode */ 586 #endif 587 | IEEE80211_C_WME /* WME */ 588 | IEEE80211_C_PMGT /* Station-side power mgmt */ 589 ; 590 591 /* Read MAC address, channels, etc from EEPROM. */ 592 if ((error = iwn_read_eeprom(sc, ic->ic_macaddr)) != 0) { 593 device_printf(dev, "could not read EEPROM, error %d\n", 594 error); 595 goto fail; 596 } 597 598 /* Count the number of available chains. */ 599 sc->ntxchains = 600 ((sc->txchainmask >> 2) & 1) + 601 ((sc->txchainmask >> 1) & 1) + 602 ((sc->txchainmask >> 0) & 1); 603 sc->nrxchains = 604 ((sc->rxchainmask >> 2) & 1) + 605 ((sc->rxchainmask >> 1) & 1) + 606 ((sc->rxchainmask >> 0) & 1); 607 if (bootverbose) { 608 device_printf(dev, "MIMO %dT%dR, %.4s, address %6D\n", 609 sc->ntxchains, sc->nrxchains, sc->eeprom_domain, 610 ic->ic_macaddr, ":"); 611 } 612 613 if (sc->sc_flags & IWN_FLAG_HAS_11N) { 614 ic->ic_rxstream = sc->nrxchains; 615 ic->ic_txstream = sc->ntxchains; 616 617 /* 618 * Some of the 3 antenna devices (ie, the 4965) only supports 619 * 2x2 operation. So correct the number of streams if 620 * it's not a 3-stream device. 621 */ 622 if (! iwn_is_3stream_device(sc)) { 623 if (ic->ic_rxstream > 2) 624 ic->ic_rxstream = 2; 625 if (ic->ic_txstream > 2) 626 ic->ic_txstream = 2; 627 } 628 629 ic->ic_htcaps = 630 IEEE80211_HTCAP_SMPS_OFF /* SMPS mode disabled */ 631 | IEEE80211_HTCAP_SHORTGI20 /* short GI in 20MHz */ 632 | IEEE80211_HTCAP_CHWIDTH40 /* 40MHz channel width*/ 633 | IEEE80211_HTCAP_SHORTGI40 /* short GI in 40MHz */ 634 #ifdef notyet 635 | IEEE80211_HTCAP_GREENFIELD 636 #if IWN_RBUF_SIZE == 8192 637 | IEEE80211_HTCAP_MAXAMSDU_7935 /* max A-MSDU length */ 638 #else 639 | IEEE80211_HTCAP_MAXAMSDU_3839 /* max A-MSDU length */ 640 #endif 641 #endif 642 /* s/w capabilities */ 643 | IEEE80211_HTC_HT /* HT operation */ 644 | IEEE80211_HTC_AMPDU /* tx A-MPDU */ 645 #ifdef notyet 646 | IEEE80211_HTC_AMSDU /* tx A-MSDU */ 647 #endif 648 ; 649 } 650 651 ieee80211_ifattach(ic); 652 ic->ic_vap_create = iwn_vap_create; 653 ic->ic_ioctl = iwn_ioctl; 654 ic->ic_parent = iwn_parent; 655 ic->ic_vap_delete = iwn_vap_delete; 656 ic->ic_transmit = iwn_transmit; 657 ic->ic_raw_xmit = iwn_raw_xmit; 658 ic->ic_node_alloc = iwn_node_alloc; 659 sc->sc_ampdu_rx_start = ic->ic_ampdu_rx_start; 660 ic->ic_ampdu_rx_start = iwn_ampdu_rx_start; 661 sc->sc_ampdu_rx_stop = ic->ic_ampdu_rx_stop; 662 ic->ic_ampdu_rx_stop = iwn_ampdu_rx_stop; 663 sc->sc_addba_request = ic->ic_addba_request; 664 ic->ic_addba_request = iwn_addba_request; 665 sc->sc_addba_response = ic->ic_addba_response; 666 ic->ic_addba_response = iwn_addba_response; 667 sc->sc_addba_stop = ic->ic_addba_stop; 668 ic->ic_addba_stop = iwn_ampdu_tx_stop; 669 ic->ic_newassoc = iwn_newassoc; 670 ic->ic_wme.wme_update = iwn_updateedca; 671 ic->ic_update_promisc = iwn_update_promisc; 672 ic->ic_update_mcast = iwn_update_mcast; 673 ic->ic_scan_start = iwn_scan_start; 674 ic->ic_scan_end = iwn_scan_end; 675 ic->ic_set_channel = iwn_set_channel; 676 ic->ic_scan_curchan = iwn_scan_curchan; 677 ic->ic_scan_mindwell = iwn_scan_mindwell; 678 ic->ic_getradiocaps = iwn_getradiocaps; 679 ic->ic_setregdomain = iwn_setregdomain; 680 681 iwn_radiotap_attach(sc); 682 683 callout_init_mtx(&sc->calib_to, &sc->sc_mtx, 0); 684 callout_init_mtx(&sc->scan_timeout, &sc->sc_mtx, 0); 685 callout_init_mtx(&sc->watchdog_to, &sc->sc_mtx, 0); 686 TASK_INIT(&sc->sc_rftoggle_task, 0, iwn_rftoggle_task, sc); 687 TASK_INIT(&sc->sc_panic_task, 0, iwn_panicked, sc); 688 TASK_INIT(&sc->sc_xmit_task, 0, iwn_xmit_task, sc); 689 690 mbufq_init(&sc->sc_xmit_queue, 1024); 691 692 sc->sc_tq = taskqueue_create("iwn_taskq", M_WAITOK, 693 taskqueue_thread_enqueue, &sc->sc_tq); 694 error = taskqueue_start_threads(&sc->sc_tq, 1, 0, "iwn_taskq"); 695 if (error != 0) { 696 device_printf(dev, "can't start threads, error %d\n", error); 697 goto fail; 698 } 699 700 iwn_sysctlattach(sc); 701 702 /* 703 * Hook our interrupt after all initialization is complete. 704 */ 705 error = bus_setup_intr(dev, sc->irq, INTR_TYPE_NET | INTR_MPSAFE, 706 NULL, iwn_intr, sc, &sc->sc_ih); 707 if (error != 0) { 708 device_printf(dev, "can't establish interrupt, error %d\n", 709 error); 710 goto fail; 711 } 712 713 #if 0 714 device_printf(sc->sc_dev, "%s: rx_stats=%d, rx_stats_bt=%d\n", 715 __func__, 716 sizeof(struct iwn_stats), 717 sizeof(struct iwn_stats_bt)); 718 #endif 719 720 if (bootverbose) 721 ieee80211_announce(ic); 722 DPRINTF(sc, IWN_DEBUG_TRACE, "->%s: end\n",__func__); 723 724 /* Add debug ioctl right at the end */ 725 sc->sc_cdev = make_dev(&iwn_cdevsw, device_get_unit(dev), 726 UID_ROOT, GID_WHEEL, 0600, "%s", device_get_nameunit(dev)); 727 if (sc->sc_cdev == NULL) { 728 device_printf(dev, "failed to create debug character device\n"); 729 } else { 730 sc->sc_cdev->si_drv1 = sc; 731 } 732 return 0; 733 fail: 734 iwn_detach(dev); 735 DPRINTF(sc, IWN_DEBUG_TRACE, "->%s: end in error\n",__func__); 736 return error; 737 } 738 739 /* 740 * Define specific configuration based on device id and subdevice id 741 * pid : PCI device id 742 */ 743 static int 744 iwn_config_specific(struct iwn_softc *sc, uint16_t pid) 745 { 746 747 switch (pid) { 748 /* 4965 series */ 749 case IWN_DID_4965_1: 750 case IWN_DID_4965_2: 751 case IWN_DID_4965_3: 752 case IWN_DID_4965_4: 753 sc->base_params = &iwn4965_base_params; 754 sc->limits = &iwn4965_sensitivity_limits; 755 sc->fwname = "iwn4965fw"; 756 /* Override chains masks, ROM is known to be broken. */ 757 sc->txchainmask = IWN_ANT_AB; 758 sc->rxchainmask = IWN_ANT_ABC; 759 /* Enable normal btcoex */ 760 sc->sc_flags |= IWN_FLAG_BTCOEX; 761 break; 762 /* 1000 Series */ 763 case IWN_DID_1000_1: 764 case IWN_DID_1000_2: 765 switch(sc->subdevice_id) { 766 case IWN_SDID_1000_1: 767 case IWN_SDID_1000_2: 768 case IWN_SDID_1000_3: 769 case IWN_SDID_1000_4: 770 case IWN_SDID_1000_5: 771 case IWN_SDID_1000_6: 772 case IWN_SDID_1000_7: 773 case IWN_SDID_1000_8: 774 case IWN_SDID_1000_9: 775 case IWN_SDID_1000_10: 776 case IWN_SDID_1000_11: 777 case IWN_SDID_1000_12: 778 sc->limits = &iwn1000_sensitivity_limits; 779 sc->base_params = &iwn1000_base_params; 780 sc->fwname = "iwn1000fw"; 781 break; 782 default: 783 device_printf(sc->sc_dev, "adapter type id : 0x%04x sub id :" 784 "0x%04x rev %d not supported (subdevice)\n", pid, 785 sc->subdevice_id,sc->hw_type); 786 return ENOTSUP; 787 } 788 break; 789 /* 6x00 Series */ 790 case IWN_DID_6x00_2: 791 case IWN_DID_6x00_4: 792 case IWN_DID_6x00_1: 793 case IWN_DID_6x00_3: 794 sc->fwname = "iwn6000fw"; 795 sc->limits = &iwn6000_sensitivity_limits; 796 switch(sc->subdevice_id) { 797 case IWN_SDID_6x00_1: 798 case IWN_SDID_6x00_2: 799 case IWN_SDID_6x00_8: 800 //iwl6000_3agn_cfg 801 sc->base_params = &iwn_6000_base_params; 802 break; 803 case IWN_SDID_6x00_3: 804 case IWN_SDID_6x00_6: 805 case IWN_SDID_6x00_9: 806 ////iwl6000i_2agn 807 case IWN_SDID_6x00_4: 808 case IWN_SDID_6x00_7: 809 case IWN_SDID_6x00_10: 810 //iwl6000i_2abg_cfg 811 case IWN_SDID_6x00_5: 812 //iwl6000i_2bg_cfg 813 sc->base_params = &iwn_6000i_base_params; 814 sc->sc_flags |= IWN_FLAG_INTERNAL_PA; 815 sc->txchainmask = IWN_ANT_BC; 816 sc->rxchainmask = IWN_ANT_BC; 817 break; 818 default: 819 device_printf(sc->sc_dev, "adapter type id : 0x%04x sub id :" 820 "0x%04x rev %d not supported (subdevice)\n", pid, 821 sc->subdevice_id,sc->hw_type); 822 return ENOTSUP; 823 } 824 break; 825 /* 6x05 Series */ 826 case IWN_DID_6x05_1: 827 case IWN_DID_6x05_2: 828 switch(sc->subdevice_id) { 829 case IWN_SDID_6x05_1: 830 case IWN_SDID_6x05_4: 831 case IWN_SDID_6x05_6: 832 //iwl6005_2agn_cfg 833 case IWN_SDID_6x05_2: 834 case IWN_SDID_6x05_5: 835 case IWN_SDID_6x05_7: 836 //iwl6005_2abg_cfg 837 case IWN_SDID_6x05_3: 838 //iwl6005_2bg_cfg 839 case IWN_SDID_6x05_8: 840 case IWN_SDID_6x05_9: 841 //iwl6005_2agn_sff_cfg 842 case IWN_SDID_6x05_10: 843 //iwl6005_2agn_d_cfg 844 case IWN_SDID_6x05_11: 845 //iwl6005_2agn_mow1_cfg 846 case IWN_SDID_6x05_12: 847 //iwl6005_2agn_mow2_cfg 848 sc->fwname = "iwn6000g2afw"; 849 sc->limits = &iwn6000_sensitivity_limits; 850 sc->base_params = &iwn_6000g2_base_params; 851 break; 852 default: 853 device_printf(sc->sc_dev, "adapter type id : 0x%04x sub id :" 854 "0x%04x rev %d not supported (subdevice)\n", pid, 855 sc->subdevice_id,sc->hw_type); 856 return ENOTSUP; 857 } 858 break; 859 /* 6x35 Series */ 860 case IWN_DID_6035_1: 861 case IWN_DID_6035_2: 862 switch(sc->subdevice_id) { 863 case IWN_SDID_6035_1: 864 case IWN_SDID_6035_2: 865 case IWN_SDID_6035_3: 866 case IWN_SDID_6035_4: 867 case IWN_SDID_6035_5: 868 sc->fwname = "iwn6000g2bfw"; 869 sc->limits = &iwn6235_sensitivity_limits; 870 sc->base_params = &iwn_6235_base_params; 871 break; 872 default: 873 device_printf(sc->sc_dev, "adapter type id : 0x%04x sub id :" 874 "0x%04x rev %d not supported (subdevice)\n", pid, 875 sc->subdevice_id,sc->hw_type); 876 return ENOTSUP; 877 } 878 break; 879 /* 6x50 WiFi/WiMax Series */ 880 case IWN_DID_6050_1: 881 case IWN_DID_6050_2: 882 switch(sc->subdevice_id) { 883 case IWN_SDID_6050_1: 884 case IWN_SDID_6050_3: 885 case IWN_SDID_6050_5: 886 //iwl6050_2agn_cfg 887 case IWN_SDID_6050_2: 888 case IWN_SDID_6050_4: 889 case IWN_SDID_6050_6: 890 //iwl6050_2abg_cfg 891 sc->fwname = "iwn6050fw"; 892 sc->txchainmask = IWN_ANT_AB; 893 sc->rxchainmask = IWN_ANT_AB; 894 sc->limits = &iwn6000_sensitivity_limits; 895 sc->base_params = &iwn_6050_base_params; 896 break; 897 default: 898 device_printf(sc->sc_dev, "adapter type id : 0x%04x sub id :" 899 "0x%04x rev %d not supported (subdevice)\n", pid, 900 sc->subdevice_id,sc->hw_type); 901 return ENOTSUP; 902 } 903 break; 904 /* 6150 WiFi/WiMax Series */ 905 case IWN_DID_6150_1: 906 case IWN_DID_6150_2: 907 switch(sc->subdevice_id) { 908 case IWN_SDID_6150_1: 909 case IWN_SDID_6150_3: 910 case IWN_SDID_6150_5: 911 // iwl6150_bgn_cfg 912 case IWN_SDID_6150_2: 913 case IWN_SDID_6150_4: 914 case IWN_SDID_6150_6: 915 //iwl6150_bg_cfg 916 sc->fwname = "iwn6050fw"; 917 sc->limits = &iwn6000_sensitivity_limits; 918 sc->base_params = &iwn_6150_base_params; 919 break; 920 default: 921 device_printf(sc->sc_dev, "adapter type id : 0x%04x sub id :" 922 "0x%04x rev %d not supported (subdevice)\n", pid, 923 sc->subdevice_id,sc->hw_type); 924 return ENOTSUP; 925 } 926 break; 927 /* 6030 Series and 1030 Series */ 928 case IWN_DID_x030_1: 929 case IWN_DID_x030_2: 930 case IWN_DID_x030_3: 931 case IWN_DID_x030_4: 932 switch(sc->subdevice_id) { 933 case IWN_SDID_x030_1: 934 case IWN_SDID_x030_3: 935 case IWN_SDID_x030_5: 936 // iwl1030_bgn_cfg 937 case IWN_SDID_x030_2: 938 case IWN_SDID_x030_4: 939 case IWN_SDID_x030_6: 940 //iwl1030_bg_cfg 941 case IWN_SDID_x030_7: 942 case IWN_SDID_x030_10: 943 case IWN_SDID_x030_14: 944 //iwl6030_2agn_cfg 945 case IWN_SDID_x030_8: 946 case IWN_SDID_x030_11: 947 case IWN_SDID_x030_15: 948 // iwl6030_2bgn_cfg 949 case IWN_SDID_x030_9: 950 case IWN_SDID_x030_12: 951 case IWN_SDID_x030_16: 952 // iwl6030_2abg_cfg 953 case IWN_SDID_x030_13: 954 //iwl6030_2bg_cfg 955 sc->fwname = "iwn6000g2bfw"; 956 sc->limits = &iwn6000_sensitivity_limits; 957 sc->base_params = &iwn_6000g2b_base_params; 958 break; 959 default: 960 device_printf(sc->sc_dev, "adapter type id : 0x%04x sub id :" 961 "0x%04x rev %d not supported (subdevice)\n", pid, 962 sc->subdevice_id,sc->hw_type); 963 return ENOTSUP; 964 } 965 break; 966 /* 130 Series WiFi */ 967 /* XXX: This series will need adjustment for rate. 968 * see rx_with_siso_diversity in linux kernel 969 */ 970 case IWN_DID_130_1: 971 case IWN_DID_130_2: 972 switch(sc->subdevice_id) { 973 case IWN_SDID_130_1: 974 case IWN_SDID_130_3: 975 case IWN_SDID_130_5: 976 //iwl130_bgn_cfg 977 case IWN_SDID_130_2: 978 case IWN_SDID_130_4: 979 case IWN_SDID_130_6: 980 //iwl130_bg_cfg 981 sc->fwname = "iwn6000g2bfw"; 982 sc->limits = &iwn6000_sensitivity_limits; 983 sc->base_params = &iwn_6000g2b_base_params; 984 break; 985 default: 986 device_printf(sc->sc_dev, "adapter type id : 0x%04x sub id :" 987 "0x%04x rev %d not supported (subdevice)\n", pid, 988 sc->subdevice_id,sc->hw_type); 989 return ENOTSUP; 990 } 991 break; 992 /* 100 Series WiFi */ 993 case IWN_DID_100_1: 994 case IWN_DID_100_2: 995 switch(sc->subdevice_id) { 996 case IWN_SDID_100_1: 997 case IWN_SDID_100_2: 998 case IWN_SDID_100_3: 999 case IWN_SDID_100_4: 1000 case IWN_SDID_100_5: 1001 case IWN_SDID_100_6: 1002 sc->limits = &iwn1000_sensitivity_limits; 1003 sc->base_params = &iwn1000_base_params; 1004 sc->fwname = "iwn100fw"; 1005 break; 1006 default: 1007 device_printf(sc->sc_dev, "adapter type id : 0x%04x sub id :" 1008 "0x%04x rev %d not supported (subdevice)\n", pid, 1009 sc->subdevice_id,sc->hw_type); 1010 return ENOTSUP; 1011 } 1012 break; 1013 1014 /* 105 Series */ 1015 /* XXX: This series will need adjustment for rate. 1016 * see rx_with_siso_diversity in linux kernel 1017 */ 1018 case IWN_DID_105_1: 1019 case IWN_DID_105_2: 1020 switch(sc->subdevice_id) { 1021 case IWN_SDID_105_1: 1022 case IWN_SDID_105_2: 1023 case IWN_SDID_105_3: 1024 //iwl105_bgn_cfg 1025 case IWN_SDID_105_4: 1026 //iwl105_bgn_d_cfg 1027 sc->limits = &iwn2030_sensitivity_limits; 1028 sc->base_params = &iwn2000_base_params; 1029 sc->fwname = "iwn105fw"; 1030 break; 1031 default: 1032 device_printf(sc->sc_dev, "adapter type id : 0x%04x sub id :" 1033 "0x%04x rev %d not supported (subdevice)\n", pid, 1034 sc->subdevice_id,sc->hw_type); 1035 return ENOTSUP; 1036 } 1037 break; 1038 1039 /* 135 Series */ 1040 /* XXX: This series will need adjustment for rate. 1041 * see rx_with_siso_diversity in linux kernel 1042 */ 1043 case IWN_DID_135_1: 1044 case IWN_DID_135_2: 1045 switch(sc->subdevice_id) { 1046 case IWN_SDID_135_1: 1047 case IWN_SDID_135_2: 1048 case IWN_SDID_135_3: 1049 sc->limits = &iwn2030_sensitivity_limits; 1050 sc->base_params = &iwn2030_base_params; 1051 sc->fwname = "iwn135fw"; 1052 break; 1053 default: 1054 device_printf(sc->sc_dev, "adapter type id : 0x%04x sub id :" 1055 "0x%04x rev %d not supported (subdevice)\n", pid, 1056 sc->subdevice_id,sc->hw_type); 1057 return ENOTSUP; 1058 } 1059 break; 1060 1061 /* 2x00 Series */ 1062 case IWN_DID_2x00_1: 1063 case IWN_DID_2x00_2: 1064 switch(sc->subdevice_id) { 1065 case IWN_SDID_2x00_1: 1066 case IWN_SDID_2x00_2: 1067 case IWN_SDID_2x00_3: 1068 //iwl2000_2bgn_cfg 1069 case IWN_SDID_2x00_4: 1070 //iwl2000_2bgn_d_cfg 1071 sc->limits = &iwn2030_sensitivity_limits; 1072 sc->base_params = &iwn2000_base_params; 1073 sc->fwname = "iwn2000fw"; 1074 break; 1075 default: 1076 device_printf(sc->sc_dev, "adapter type id : 0x%04x sub id :" 1077 "0x%04x rev %d not supported (subdevice) \n", 1078 pid, sc->subdevice_id, sc->hw_type); 1079 return ENOTSUP; 1080 } 1081 break; 1082 /* 2x30 Series */ 1083 case IWN_DID_2x30_1: 1084 case IWN_DID_2x30_2: 1085 switch(sc->subdevice_id) { 1086 case IWN_SDID_2x30_1: 1087 case IWN_SDID_2x30_3: 1088 case IWN_SDID_2x30_5: 1089 //iwl100_bgn_cfg 1090 case IWN_SDID_2x30_2: 1091 case IWN_SDID_2x30_4: 1092 case IWN_SDID_2x30_6: 1093 //iwl100_bg_cfg 1094 sc->limits = &iwn2030_sensitivity_limits; 1095 sc->base_params = &iwn2030_base_params; 1096 sc->fwname = "iwn2030fw"; 1097 break; 1098 default: 1099 device_printf(sc->sc_dev, "adapter type id : 0x%04x sub id :" 1100 "0x%04x rev %d not supported (subdevice)\n", pid, 1101 sc->subdevice_id,sc->hw_type); 1102 return ENOTSUP; 1103 } 1104 break; 1105 /* 5x00 Series */ 1106 case IWN_DID_5x00_1: 1107 case IWN_DID_5x00_2: 1108 case IWN_DID_5x00_3: 1109 case IWN_DID_5x00_4: 1110 sc->limits = &iwn5000_sensitivity_limits; 1111 sc->base_params = &iwn5000_base_params; 1112 sc->fwname = "iwn5000fw"; 1113 switch(sc->subdevice_id) { 1114 case IWN_SDID_5x00_1: 1115 case IWN_SDID_5x00_2: 1116 case IWN_SDID_5x00_3: 1117 case IWN_SDID_5x00_4: 1118 case IWN_SDID_5x00_9: 1119 case IWN_SDID_5x00_10: 1120 case IWN_SDID_5x00_11: 1121 case IWN_SDID_5x00_12: 1122 case IWN_SDID_5x00_17: 1123 case IWN_SDID_5x00_18: 1124 case IWN_SDID_5x00_19: 1125 case IWN_SDID_5x00_20: 1126 //iwl5100_agn_cfg 1127 sc->txchainmask = IWN_ANT_B; 1128 sc->rxchainmask = IWN_ANT_AB; 1129 break; 1130 case IWN_SDID_5x00_5: 1131 case IWN_SDID_5x00_6: 1132 case IWN_SDID_5x00_13: 1133 case IWN_SDID_5x00_14: 1134 case IWN_SDID_5x00_21: 1135 case IWN_SDID_5x00_22: 1136 //iwl5100_bgn_cfg 1137 sc->txchainmask = IWN_ANT_B; 1138 sc->rxchainmask = IWN_ANT_AB; 1139 break; 1140 case IWN_SDID_5x00_7: 1141 case IWN_SDID_5x00_8: 1142 case IWN_SDID_5x00_15: 1143 case IWN_SDID_5x00_16: 1144 case IWN_SDID_5x00_23: 1145 case IWN_SDID_5x00_24: 1146 //iwl5100_abg_cfg 1147 sc->txchainmask = IWN_ANT_B; 1148 sc->rxchainmask = IWN_ANT_AB; 1149 break; 1150 case IWN_SDID_5x00_25: 1151 case IWN_SDID_5x00_26: 1152 case IWN_SDID_5x00_27: 1153 case IWN_SDID_5x00_28: 1154 case IWN_SDID_5x00_29: 1155 case IWN_SDID_5x00_30: 1156 case IWN_SDID_5x00_31: 1157 case IWN_SDID_5x00_32: 1158 case IWN_SDID_5x00_33: 1159 case IWN_SDID_5x00_34: 1160 case IWN_SDID_5x00_35: 1161 case IWN_SDID_5x00_36: 1162 //iwl5300_agn_cfg 1163 sc->txchainmask = IWN_ANT_ABC; 1164 sc->rxchainmask = IWN_ANT_ABC; 1165 break; 1166 default: 1167 device_printf(sc->sc_dev, "adapter type id : 0x%04x sub id :" 1168 "0x%04x rev %d not supported (subdevice)\n", pid, 1169 sc->subdevice_id,sc->hw_type); 1170 return ENOTSUP; 1171 } 1172 break; 1173 /* 5x50 Series */ 1174 case IWN_DID_5x50_1: 1175 case IWN_DID_5x50_2: 1176 case IWN_DID_5x50_3: 1177 case IWN_DID_5x50_4: 1178 sc->limits = &iwn5000_sensitivity_limits; 1179 sc->base_params = &iwn5000_base_params; 1180 sc->fwname = "iwn5000fw"; 1181 switch(sc->subdevice_id) { 1182 case IWN_SDID_5x50_1: 1183 case IWN_SDID_5x50_2: 1184 case IWN_SDID_5x50_3: 1185 //iwl5350_agn_cfg 1186 sc->limits = &iwn5000_sensitivity_limits; 1187 sc->base_params = &iwn5000_base_params; 1188 sc->fwname = "iwn5000fw"; 1189 break; 1190 case IWN_SDID_5x50_4: 1191 case IWN_SDID_5x50_5: 1192 case IWN_SDID_5x50_8: 1193 case IWN_SDID_5x50_9: 1194 case IWN_SDID_5x50_10: 1195 case IWN_SDID_5x50_11: 1196 //iwl5150_agn_cfg 1197 case IWN_SDID_5x50_6: 1198 case IWN_SDID_5x50_7: 1199 case IWN_SDID_5x50_12: 1200 case IWN_SDID_5x50_13: 1201 //iwl5150_abg_cfg 1202 sc->limits = &iwn5000_sensitivity_limits; 1203 sc->fwname = "iwn5150fw"; 1204 sc->base_params = &iwn_5x50_base_params; 1205 break; 1206 default: 1207 device_printf(sc->sc_dev, "adapter type id : 0x%04x sub id :" 1208 "0x%04x rev %d not supported (subdevice)\n", pid, 1209 sc->subdevice_id,sc->hw_type); 1210 return ENOTSUP; 1211 } 1212 break; 1213 default: 1214 device_printf(sc->sc_dev, "adapter type id : 0x%04x sub id : 0x%04x" 1215 "rev 0x%08x not supported (device)\n", pid, sc->subdevice_id, 1216 sc->hw_type); 1217 return ENOTSUP; 1218 } 1219 return 0; 1220 } 1221 1222 static void 1223 iwn4965_attach(struct iwn_softc *sc, uint16_t pid) 1224 { 1225 struct iwn_ops *ops = &sc->ops; 1226 1227 DPRINTF(sc, IWN_DEBUG_TRACE, "->%s begin\n", __func__); 1228 1229 ops->load_firmware = iwn4965_load_firmware; 1230 ops->read_eeprom = iwn4965_read_eeprom; 1231 ops->post_alive = iwn4965_post_alive; 1232 ops->nic_config = iwn4965_nic_config; 1233 ops->update_sched = iwn4965_update_sched; 1234 ops->get_temperature = iwn4965_get_temperature; 1235 ops->get_rssi = iwn4965_get_rssi; 1236 ops->set_txpower = iwn4965_set_txpower; 1237 ops->init_gains = iwn4965_init_gains; 1238 ops->set_gains = iwn4965_set_gains; 1239 ops->rxon_assoc = iwn4965_rxon_assoc; 1240 ops->add_node = iwn4965_add_node; 1241 ops->tx_done = iwn4965_tx_done; 1242 ops->ampdu_tx_start = iwn4965_ampdu_tx_start; 1243 ops->ampdu_tx_stop = iwn4965_ampdu_tx_stop; 1244 sc->ntxqs = IWN4965_NTXQUEUES; 1245 sc->firstaggqueue = IWN4965_FIRSTAGGQUEUE; 1246 sc->ndmachnls = IWN4965_NDMACHNLS; 1247 sc->broadcast_id = IWN4965_ID_BROADCAST; 1248 sc->rxonsz = IWN4965_RXONSZ; 1249 sc->schedsz = IWN4965_SCHEDSZ; 1250 sc->fw_text_maxsz = IWN4965_FW_TEXT_MAXSZ; 1251 sc->fw_data_maxsz = IWN4965_FW_DATA_MAXSZ; 1252 sc->fwsz = IWN4965_FWSZ; 1253 sc->sched_txfact_addr = IWN4965_SCHED_TXFACT; 1254 sc->limits = &iwn4965_sensitivity_limits; 1255 sc->fwname = "iwn4965fw"; 1256 /* Override chains masks, ROM is known to be broken. */ 1257 sc->txchainmask = IWN_ANT_AB; 1258 sc->rxchainmask = IWN_ANT_ABC; 1259 /* Enable normal btcoex */ 1260 sc->sc_flags |= IWN_FLAG_BTCOEX; 1261 1262 DPRINTF(sc, IWN_DEBUG_TRACE, "%s: end\n",__func__); 1263 } 1264 1265 static void 1266 iwn5000_attach(struct iwn_softc *sc, uint16_t pid) 1267 { 1268 struct iwn_ops *ops = &sc->ops; 1269 1270 DPRINTF(sc, IWN_DEBUG_TRACE, "->%s begin\n", __func__); 1271 1272 ops->load_firmware = iwn5000_load_firmware; 1273 ops->read_eeprom = iwn5000_read_eeprom; 1274 ops->post_alive = iwn5000_post_alive; 1275 ops->nic_config = iwn5000_nic_config; 1276 ops->update_sched = iwn5000_update_sched; 1277 ops->get_temperature = iwn5000_get_temperature; 1278 ops->get_rssi = iwn5000_get_rssi; 1279 ops->set_txpower = iwn5000_set_txpower; 1280 ops->init_gains = iwn5000_init_gains; 1281 ops->set_gains = iwn5000_set_gains; 1282 ops->rxon_assoc = iwn5000_rxon_assoc; 1283 ops->add_node = iwn5000_add_node; 1284 ops->tx_done = iwn5000_tx_done; 1285 ops->ampdu_tx_start = iwn5000_ampdu_tx_start; 1286 ops->ampdu_tx_stop = iwn5000_ampdu_tx_stop; 1287 sc->ntxqs = IWN5000_NTXQUEUES; 1288 sc->firstaggqueue = IWN5000_FIRSTAGGQUEUE; 1289 sc->ndmachnls = IWN5000_NDMACHNLS; 1290 sc->broadcast_id = IWN5000_ID_BROADCAST; 1291 sc->rxonsz = IWN5000_RXONSZ; 1292 sc->schedsz = IWN5000_SCHEDSZ; 1293 sc->fw_text_maxsz = IWN5000_FW_TEXT_MAXSZ; 1294 sc->fw_data_maxsz = IWN5000_FW_DATA_MAXSZ; 1295 sc->fwsz = IWN5000_FWSZ; 1296 sc->sched_txfact_addr = IWN5000_SCHED_TXFACT; 1297 sc->reset_noise_gain = IWN5000_PHY_CALIB_RESET_NOISE_GAIN; 1298 sc->noise_gain = IWN5000_PHY_CALIB_NOISE_GAIN; 1299 1300 DPRINTF(sc, IWN_DEBUG_TRACE, "%s: end\n",__func__); 1301 } 1302 1303 /* 1304 * Attach the interface to 802.11 radiotap. 1305 */ 1306 static void 1307 iwn_radiotap_attach(struct iwn_softc *sc) 1308 { 1309 1310 DPRINTF(sc, IWN_DEBUG_TRACE, "->%s begin\n", __func__); 1311 ieee80211_radiotap_attach(&sc->sc_ic, 1312 &sc->sc_txtap.wt_ihdr, sizeof(sc->sc_txtap), 1313 IWN_TX_RADIOTAP_PRESENT, 1314 &sc->sc_rxtap.wr_ihdr, sizeof(sc->sc_rxtap), 1315 IWN_RX_RADIOTAP_PRESENT); 1316 DPRINTF(sc, IWN_DEBUG_TRACE, "->%s end\n", __func__); 1317 } 1318 1319 static void 1320 iwn_sysctlattach(struct iwn_softc *sc) 1321 { 1322 #ifdef IWN_DEBUG 1323 struct sysctl_ctx_list *ctx = device_get_sysctl_ctx(sc->sc_dev); 1324 struct sysctl_oid *tree = device_get_sysctl_tree(sc->sc_dev); 1325 1326 SYSCTL_ADD_INT(ctx, SYSCTL_CHILDREN(tree), OID_AUTO, 1327 "debug", CTLFLAG_RW, &sc->sc_debug, sc->sc_debug, 1328 "control debugging printfs"); 1329 #endif 1330 } 1331 1332 static struct ieee80211vap * 1333 iwn_vap_create(struct ieee80211com *ic, const char name[IFNAMSIZ], int unit, 1334 enum ieee80211_opmode opmode, int flags, 1335 const uint8_t bssid[IEEE80211_ADDR_LEN], 1336 const uint8_t mac[IEEE80211_ADDR_LEN]) 1337 { 1338 struct iwn_softc *sc = ic->ic_softc; 1339 struct iwn_vap *ivp; 1340 struct ieee80211vap *vap; 1341 1342 if (!TAILQ_EMPTY(&ic->ic_vaps)) /* only one at a time */ 1343 return NULL; 1344 1345 ivp = malloc(sizeof(struct iwn_vap), M_80211_VAP, M_WAITOK | M_ZERO); 1346 vap = &ivp->iv_vap; 1347 ieee80211_vap_setup(ic, vap, name, unit, opmode, flags, bssid); 1348 ivp->ctx = IWN_RXON_BSS_CTX; 1349 vap->iv_bmissthreshold = 10; /* override default */ 1350 /* Override with driver methods. */ 1351 ivp->iv_newstate = vap->iv_newstate; 1352 vap->iv_newstate = iwn_newstate; 1353 sc->ivap[IWN_RXON_BSS_CTX] = vap; 1354 1355 ieee80211_ratectl_init(vap); 1356 /* Complete setup. */ 1357 ieee80211_vap_attach(vap, iwn_media_change, ieee80211_media_status, 1358 mac); 1359 ic->ic_opmode = opmode; 1360 return vap; 1361 } 1362 1363 static void 1364 iwn_vap_delete(struct ieee80211vap *vap) 1365 { 1366 struct iwn_vap *ivp = IWN_VAP(vap); 1367 1368 ieee80211_ratectl_deinit(vap); 1369 ieee80211_vap_detach(vap); 1370 free(ivp, M_80211_VAP); 1371 } 1372 1373 static void 1374 iwn_xmit_queue_drain(struct iwn_softc *sc) 1375 { 1376 struct mbuf *m; 1377 struct ieee80211_node *ni; 1378 1379 IWN_LOCK_ASSERT(sc); 1380 while ((m = mbufq_dequeue(&sc->sc_xmit_queue)) != NULL) { 1381 ni = (struct ieee80211_node *)m->m_pkthdr.rcvif; 1382 ieee80211_free_node(ni); 1383 m_freem(m); 1384 } 1385 } 1386 1387 static int 1388 iwn_xmit_queue_enqueue(struct iwn_softc *sc, struct mbuf *m) 1389 { 1390 1391 IWN_LOCK_ASSERT(sc); 1392 return (mbufq_enqueue(&sc->sc_xmit_queue, m)); 1393 } 1394 1395 static int 1396 iwn_detach(device_t dev) 1397 { 1398 struct iwn_softc *sc = device_get_softc(dev); 1399 int qid; 1400 1401 DPRINTF(sc, IWN_DEBUG_TRACE, "->%s begin\n", __func__); 1402 1403 if (sc->sc_ic.ic_softc != NULL) { 1404 /* Free the mbuf queue and node references */ 1405 IWN_LOCK(sc); 1406 iwn_xmit_queue_drain(sc); 1407 IWN_UNLOCK(sc); 1408 1409 iwn_stop(sc); 1410 1411 taskqueue_drain_all(sc->sc_tq); 1412 taskqueue_free(sc->sc_tq); 1413 1414 callout_drain(&sc->watchdog_to); 1415 callout_drain(&sc->scan_timeout); 1416 callout_drain(&sc->calib_to); 1417 ieee80211_ifdetach(&sc->sc_ic); 1418 } 1419 1420 /* Uninstall interrupt handler. */ 1421 if (sc->irq != NULL) { 1422 bus_teardown_intr(dev, sc->irq, sc->sc_ih); 1423 bus_release_resource(dev, SYS_RES_IRQ, rman_get_rid(sc->irq), 1424 sc->irq); 1425 pci_release_msi(dev); 1426 } 1427 1428 /* Free DMA resources. */ 1429 iwn_free_rx_ring(sc, &sc->rxq); 1430 for (qid = 0; qid < sc->ntxqs; qid++) 1431 iwn_free_tx_ring(sc, &sc->txq[qid]); 1432 iwn_free_sched(sc); 1433 iwn_free_kw(sc); 1434 if (sc->ict != NULL) 1435 iwn_free_ict(sc); 1436 iwn_free_fwmem(sc); 1437 1438 if (sc->mem != NULL) 1439 bus_release_resource(dev, SYS_RES_MEMORY, 1440 rman_get_rid(sc->mem), sc->mem); 1441 1442 if (sc->sc_cdev) { 1443 destroy_dev(sc->sc_cdev); 1444 sc->sc_cdev = NULL; 1445 } 1446 1447 DPRINTF(sc, IWN_DEBUG_TRACE, "->%s: end\n", __func__); 1448 IWN_LOCK_DESTROY(sc); 1449 return 0; 1450 } 1451 1452 static int 1453 iwn_shutdown(device_t dev) 1454 { 1455 struct iwn_softc *sc = device_get_softc(dev); 1456 1457 iwn_stop(sc); 1458 return 0; 1459 } 1460 1461 static int 1462 iwn_suspend(device_t dev) 1463 { 1464 struct iwn_softc *sc = device_get_softc(dev); 1465 1466 ieee80211_suspend_all(&sc->sc_ic); 1467 return 0; 1468 } 1469 1470 static int 1471 iwn_resume(device_t dev) 1472 { 1473 struct iwn_softc *sc = device_get_softc(dev); 1474 1475 /* Clear device-specific "PCI retry timeout" register (41h). */ 1476 pci_write_config(dev, 0x41, 0, 1); 1477 1478 ieee80211_resume_all(&sc->sc_ic); 1479 return 0; 1480 } 1481 1482 static int 1483 iwn_nic_lock(struct iwn_softc *sc) 1484 { 1485 int ntries; 1486 1487 /* Request exclusive access to NIC. */ 1488 IWN_SETBITS(sc, IWN_GP_CNTRL, IWN_GP_CNTRL_MAC_ACCESS_REQ); 1489 1490 /* Spin until we actually get the lock. */ 1491 for (ntries = 0; ntries < 1000; ntries++) { 1492 if ((IWN_READ(sc, IWN_GP_CNTRL) & 1493 (IWN_GP_CNTRL_MAC_ACCESS_ENA | IWN_GP_CNTRL_SLEEP)) == 1494 IWN_GP_CNTRL_MAC_ACCESS_ENA) 1495 return 0; 1496 DELAY(10); 1497 } 1498 return ETIMEDOUT; 1499 } 1500 1501 static __inline void 1502 iwn_nic_unlock(struct iwn_softc *sc) 1503 { 1504 IWN_CLRBITS(sc, IWN_GP_CNTRL, IWN_GP_CNTRL_MAC_ACCESS_REQ); 1505 } 1506 1507 static __inline uint32_t 1508 iwn_prph_read(struct iwn_softc *sc, uint32_t addr) 1509 { 1510 IWN_WRITE(sc, IWN_PRPH_RADDR, IWN_PRPH_DWORD | addr); 1511 IWN_BARRIER_READ_WRITE(sc); 1512 return IWN_READ(sc, IWN_PRPH_RDATA); 1513 } 1514 1515 static __inline void 1516 iwn_prph_write(struct iwn_softc *sc, uint32_t addr, uint32_t data) 1517 { 1518 IWN_WRITE(sc, IWN_PRPH_WADDR, IWN_PRPH_DWORD | addr); 1519 IWN_BARRIER_WRITE(sc); 1520 IWN_WRITE(sc, IWN_PRPH_WDATA, data); 1521 } 1522 1523 static __inline void 1524 iwn_prph_setbits(struct iwn_softc *sc, uint32_t addr, uint32_t mask) 1525 { 1526 iwn_prph_write(sc, addr, iwn_prph_read(sc, addr) | mask); 1527 } 1528 1529 static __inline void 1530 iwn_prph_clrbits(struct iwn_softc *sc, uint32_t addr, uint32_t mask) 1531 { 1532 iwn_prph_write(sc, addr, iwn_prph_read(sc, addr) & ~mask); 1533 } 1534 1535 static __inline void 1536 iwn_prph_write_region_4(struct iwn_softc *sc, uint32_t addr, 1537 const uint32_t *data, int count) 1538 { 1539 for (; count > 0; count--, data++, addr += 4) 1540 iwn_prph_write(sc, addr, *data); 1541 } 1542 1543 static __inline uint32_t 1544 iwn_mem_read(struct iwn_softc *sc, uint32_t addr) 1545 { 1546 IWN_WRITE(sc, IWN_MEM_RADDR, addr); 1547 IWN_BARRIER_READ_WRITE(sc); 1548 return IWN_READ(sc, IWN_MEM_RDATA); 1549 } 1550 1551 static __inline void 1552 iwn_mem_write(struct iwn_softc *sc, uint32_t addr, uint32_t data) 1553 { 1554 IWN_WRITE(sc, IWN_MEM_WADDR, addr); 1555 IWN_BARRIER_WRITE(sc); 1556 IWN_WRITE(sc, IWN_MEM_WDATA, data); 1557 } 1558 1559 static __inline void 1560 iwn_mem_write_2(struct iwn_softc *sc, uint32_t addr, uint16_t data) 1561 { 1562 uint32_t tmp; 1563 1564 tmp = iwn_mem_read(sc, addr & ~3); 1565 if (addr & 3) 1566 tmp = (tmp & 0x0000ffff) | data << 16; 1567 else 1568 tmp = (tmp & 0xffff0000) | data; 1569 iwn_mem_write(sc, addr & ~3, tmp); 1570 } 1571 1572 static __inline void 1573 iwn_mem_read_region_4(struct iwn_softc *sc, uint32_t addr, uint32_t *data, 1574 int count) 1575 { 1576 for (; count > 0; count--, addr += 4) 1577 *data++ = iwn_mem_read(sc, addr); 1578 } 1579 1580 static __inline void 1581 iwn_mem_set_region_4(struct iwn_softc *sc, uint32_t addr, uint32_t val, 1582 int count) 1583 { 1584 for (; count > 0; count--, addr += 4) 1585 iwn_mem_write(sc, addr, val); 1586 } 1587 1588 static int 1589 iwn_eeprom_lock(struct iwn_softc *sc) 1590 { 1591 int i, ntries; 1592 1593 for (i = 0; i < 100; i++) { 1594 /* Request exclusive access to EEPROM. */ 1595 IWN_SETBITS(sc, IWN_HW_IF_CONFIG, 1596 IWN_HW_IF_CONFIG_EEPROM_LOCKED); 1597 1598 /* Spin until we actually get the lock. */ 1599 for (ntries = 0; ntries < 100; ntries++) { 1600 if (IWN_READ(sc, IWN_HW_IF_CONFIG) & 1601 IWN_HW_IF_CONFIG_EEPROM_LOCKED) 1602 return 0; 1603 DELAY(10); 1604 } 1605 } 1606 DPRINTF(sc, IWN_DEBUG_TRACE, "->%s end timeout\n", __func__); 1607 return ETIMEDOUT; 1608 } 1609 1610 static __inline void 1611 iwn_eeprom_unlock(struct iwn_softc *sc) 1612 { 1613 IWN_CLRBITS(sc, IWN_HW_IF_CONFIG, IWN_HW_IF_CONFIG_EEPROM_LOCKED); 1614 } 1615 1616 /* 1617 * Initialize access by host to One Time Programmable ROM. 1618 * NB: This kind of ROM can be found on 1000 or 6000 Series only. 1619 */ 1620 static int 1621 iwn_init_otprom(struct iwn_softc *sc) 1622 { 1623 uint16_t prev, base, next; 1624 int count, error; 1625 1626 DPRINTF(sc, IWN_DEBUG_TRACE, "->%s begin\n", __func__); 1627 1628 /* Wait for clock stabilization before accessing prph. */ 1629 if ((error = iwn_clock_wait(sc)) != 0) 1630 return error; 1631 1632 if ((error = iwn_nic_lock(sc)) != 0) 1633 return error; 1634 iwn_prph_setbits(sc, IWN_APMG_PS, IWN_APMG_PS_RESET_REQ); 1635 DELAY(5); 1636 iwn_prph_clrbits(sc, IWN_APMG_PS, IWN_APMG_PS_RESET_REQ); 1637 iwn_nic_unlock(sc); 1638 1639 /* Set auto clock gate disable bit for HW with OTP shadow RAM. */ 1640 if (sc->base_params->shadow_ram_support) { 1641 IWN_SETBITS(sc, IWN_DBG_LINK_PWR_MGMT, 1642 IWN_RESET_LINK_PWR_MGMT_DIS); 1643 } 1644 IWN_CLRBITS(sc, IWN_EEPROM_GP, IWN_EEPROM_GP_IF_OWNER); 1645 /* Clear ECC status. */ 1646 IWN_SETBITS(sc, IWN_OTP_GP, 1647 IWN_OTP_GP_ECC_CORR_STTS | IWN_OTP_GP_ECC_UNCORR_STTS); 1648 1649 /* 1650 * Find the block before last block (contains the EEPROM image) 1651 * for HW without OTP shadow RAM. 1652 */ 1653 if (! sc->base_params->shadow_ram_support) { 1654 /* Switch to absolute addressing mode. */ 1655 IWN_CLRBITS(sc, IWN_OTP_GP, IWN_OTP_GP_RELATIVE_ACCESS); 1656 base = prev = 0; 1657 for (count = 0; count < sc->base_params->max_ll_items; 1658 count++) { 1659 error = iwn_read_prom_data(sc, base, &next, 2); 1660 if (error != 0) 1661 return error; 1662 if (next == 0) /* End of linked-list. */ 1663 break; 1664 prev = base; 1665 base = le16toh(next); 1666 } 1667 if (count == 0 || count == sc->base_params->max_ll_items) 1668 return EIO; 1669 /* Skip "next" word. */ 1670 sc->prom_base = prev + 1; 1671 } 1672 1673 DPRINTF(sc, IWN_DEBUG_TRACE, "->%s end\n", __func__); 1674 1675 return 0; 1676 } 1677 1678 static int 1679 iwn_read_prom_data(struct iwn_softc *sc, uint32_t addr, void *data, int count) 1680 { 1681 uint8_t *out = data; 1682 uint32_t val, tmp; 1683 int ntries; 1684 1685 DPRINTF(sc, IWN_DEBUG_TRACE, "->%s begin\n", __func__); 1686 1687 addr += sc->prom_base; 1688 for (; count > 0; count -= 2, addr++) { 1689 IWN_WRITE(sc, IWN_EEPROM, addr << 2); 1690 for (ntries = 0; ntries < 10; ntries++) { 1691 val = IWN_READ(sc, IWN_EEPROM); 1692 if (val & IWN_EEPROM_READ_VALID) 1693 break; 1694 DELAY(5); 1695 } 1696 if (ntries == 10) { 1697 device_printf(sc->sc_dev, 1698 "timeout reading ROM at 0x%x\n", addr); 1699 return ETIMEDOUT; 1700 } 1701 if (sc->sc_flags & IWN_FLAG_HAS_OTPROM) { 1702 /* OTPROM, check for ECC errors. */ 1703 tmp = IWN_READ(sc, IWN_OTP_GP); 1704 if (tmp & IWN_OTP_GP_ECC_UNCORR_STTS) { 1705 device_printf(sc->sc_dev, 1706 "OTPROM ECC error at 0x%x\n", addr); 1707 return EIO; 1708 } 1709 if (tmp & IWN_OTP_GP_ECC_CORR_STTS) { 1710 /* Correctable ECC error, clear bit. */ 1711 IWN_SETBITS(sc, IWN_OTP_GP, 1712 IWN_OTP_GP_ECC_CORR_STTS); 1713 } 1714 } 1715 *out++ = val >> 16; 1716 if (count > 1) 1717 *out++ = val >> 24; 1718 } 1719 1720 DPRINTF(sc, IWN_DEBUG_TRACE, "->%s end\n", __func__); 1721 1722 return 0; 1723 } 1724 1725 static void 1726 iwn_dma_map_addr(void *arg, bus_dma_segment_t *segs, int nsegs, int error) 1727 { 1728 if (error != 0) 1729 return; 1730 KASSERT(nsegs == 1, ("too many DMA segments, %d should be 1", nsegs)); 1731 *(bus_addr_t *)arg = segs[0].ds_addr; 1732 } 1733 1734 static int 1735 iwn_dma_contig_alloc(struct iwn_softc *sc, struct iwn_dma_info *dma, 1736 void **kvap, bus_size_t size, bus_size_t alignment) 1737 { 1738 int error; 1739 1740 dma->tag = NULL; 1741 dma->size = size; 1742 1743 error = bus_dma_tag_create(bus_get_dma_tag(sc->sc_dev), alignment, 1744 0, BUS_SPACE_MAXADDR_32BIT, BUS_SPACE_MAXADDR, NULL, NULL, size, 1745 1, size, 0, NULL, NULL, &dma->tag); 1746 if (error != 0) 1747 goto fail; 1748 1749 error = bus_dmamem_alloc(dma->tag, (void **)&dma->vaddr, 1750 BUS_DMA_NOWAIT | BUS_DMA_ZERO | BUS_DMA_COHERENT, &dma->map); 1751 if (error != 0) 1752 goto fail; 1753 1754 error = bus_dmamap_load(dma->tag, dma->map, dma->vaddr, size, 1755 iwn_dma_map_addr, &dma->paddr, BUS_DMA_NOWAIT); 1756 if (error != 0) 1757 goto fail; 1758 1759 bus_dmamap_sync(dma->tag, dma->map, BUS_DMASYNC_PREWRITE); 1760 1761 if (kvap != NULL) 1762 *kvap = dma->vaddr; 1763 1764 return 0; 1765 1766 fail: iwn_dma_contig_free(dma); 1767 return error; 1768 } 1769 1770 static void 1771 iwn_dma_contig_free(struct iwn_dma_info *dma) 1772 { 1773 if (dma->vaddr != NULL) { 1774 bus_dmamap_sync(dma->tag, dma->map, 1775 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); 1776 bus_dmamap_unload(dma->tag, dma->map); 1777 bus_dmamem_free(dma->tag, dma->vaddr, dma->map); 1778 dma->vaddr = NULL; 1779 } 1780 if (dma->tag != NULL) { 1781 bus_dma_tag_destroy(dma->tag); 1782 dma->tag = NULL; 1783 } 1784 } 1785 1786 static int 1787 iwn_alloc_sched(struct iwn_softc *sc) 1788 { 1789 /* TX scheduler rings must be aligned on a 1KB boundary. */ 1790 return iwn_dma_contig_alloc(sc, &sc->sched_dma, (void **)&sc->sched, 1791 sc->schedsz, 1024); 1792 } 1793 1794 static void 1795 iwn_free_sched(struct iwn_softc *sc) 1796 { 1797 iwn_dma_contig_free(&sc->sched_dma); 1798 } 1799 1800 static int 1801 iwn_alloc_kw(struct iwn_softc *sc) 1802 { 1803 /* "Keep Warm" page must be aligned on a 4KB boundary. */ 1804 return iwn_dma_contig_alloc(sc, &sc->kw_dma, NULL, 4096, 4096); 1805 } 1806 1807 static void 1808 iwn_free_kw(struct iwn_softc *sc) 1809 { 1810 iwn_dma_contig_free(&sc->kw_dma); 1811 } 1812 1813 static int 1814 iwn_alloc_ict(struct iwn_softc *sc) 1815 { 1816 /* ICT table must be aligned on a 4KB boundary. */ 1817 return iwn_dma_contig_alloc(sc, &sc->ict_dma, (void **)&sc->ict, 1818 IWN_ICT_SIZE, 4096); 1819 } 1820 1821 static void 1822 iwn_free_ict(struct iwn_softc *sc) 1823 { 1824 iwn_dma_contig_free(&sc->ict_dma); 1825 } 1826 1827 static int 1828 iwn_alloc_fwmem(struct iwn_softc *sc) 1829 { 1830 /* Must be aligned on a 16-byte boundary. */ 1831 return iwn_dma_contig_alloc(sc, &sc->fw_dma, NULL, sc->fwsz, 16); 1832 } 1833 1834 static void 1835 iwn_free_fwmem(struct iwn_softc *sc) 1836 { 1837 iwn_dma_contig_free(&sc->fw_dma); 1838 } 1839 1840 static int 1841 iwn_alloc_rx_ring(struct iwn_softc *sc, struct iwn_rx_ring *ring) 1842 { 1843 bus_size_t size; 1844 int i, error; 1845 1846 ring->cur = 0; 1847 1848 DPRINTF(sc, IWN_DEBUG_TRACE, "->%s begin\n", __func__); 1849 1850 /* Allocate RX descriptors (256-byte aligned). */ 1851 size = IWN_RX_RING_COUNT * sizeof (uint32_t); 1852 error = iwn_dma_contig_alloc(sc, &ring->desc_dma, (void **)&ring->desc, 1853 size, 256); 1854 if (error != 0) { 1855 device_printf(sc->sc_dev, 1856 "%s: could not allocate RX ring DMA memory, error %d\n", 1857 __func__, error); 1858 goto fail; 1859 } 1860 1861 /* Allocate RX status area (16-byte aligned). */ 1862 error = iwn_dma_contig_alloc(sc, &ring->stat_dma, (void **)&ring->stat, 1863 sizeof (struct iwn_rx_status), 16); 1864 if (error != 0) { 1865 device_printf(sc->sc_dev, 1866 "%s: could not allocate RX status DMA memory, error %d\n", 1867 __func__, error); 1868 goto fail; 1869 } 1870 1871 /* Create RX buffer DMA tag. */ 1872 error = bus_dma_tag_create(bus_get_dma_tag(sc->sc_dev), 1, 0, 1873 BUS_SPACE_MAXADDR_32BIT, BUS_SPACE_MAXADDR, NULL, NULL, 1874 IWN_RBUF_SIZE, 1, IWN_RBUF_SIZE, 0, NULL, NULL, &ring->data_dmat); 1875 if (error != 0) { 1876 device_printf(sc->sc_dev, 1877 "%s: could not create RX buf DMA tag, error %d\n", 1878 __func__, error); 1879 goto fail; 1880 } 1881 1882 /* 1883 * Allocate and map RX buffers. 1884 */ 1885 for (i = 0; i < IWN_RX_RING_COUNT; i++) { 1886 struct iwn_rx_data *data = &ring->data[i]; 1887 bus_addr_t paddr; 1888 1889 error = bus_dmamap_create(ring->data_dmat, 0, &data->map); 1890 if (error != 0) { 1891 device_printf(sc->sc_dev, 1892 "%s: could not create RX buf DMA map, error %d\n", 1893 __func__, error); 1894 goto fail; 1895 } 1896 1897 data->m = m_getjcl(M_NOWAIT, MT_DATA, M_PKTHDR, 1898 IWN_RBUF_SIZE); 1899 if (data->m == NULL) { 1900 device_printf(sc->sc_dev, 1901 "%s: could not allocate RX mbuf\n", __func__); 1902 error = ENOBUFS; 1903 goto fail; 1904 } 1905 1906 error = bus_dmamap_load(ring->data_dmat, data->map, 1907 mtod(data->m, void *), IWN_RBUF_SIZE, iwn_dma_map_addr, 1908 &paddr, BUS_DMA_NOWAIT); 1909 if (error != 0 && error != EFBIG) { 1910 device_printf(sc->sc_dev, 1911 "%s: can't map mbuf, error %d\n", __func__, 1912 error); 1913 goto fail; 1914 } 1915 1916 bus_dmamap_sync(ring->data_dmat, data->map, 1917 BUS_DMASYNC_PREREAD); 1918 1919 /* Set physical address of RX buffer (256-byte aligned). */ 1920 ring->desc[i] = htole32(paddr >> 8); 1921 } 1922 1923 bus_dmamap_sync(ring->desc_dma.tag, ring->desc_dma.map, 1924 BUS_DMASYNC_PREWRITE); 1925 1926 DPRINTF(sc, IWN_DEBUG_TRACE, "->%s: end\n",__func__); 1927 1928 return 0; 1929 1930 fail: iwn_free_rx_ring(sc, ring); 1931 1932 DPRINTF(sc, IWN_DEBUG_TRACE, "->%s: end in error\n",__func__); 1933 1934 return error; 1935 } 1936 1937 static void 1938 iwn_reset_rx_ring(struct iwn_softc *sc, struct iwn_rx_ring *ring) 1939 { 1940 int ntries; 1941 1942 DPRINTF(sc, IWN_DEBUG_TRACE, "->Doing %s\n", __func__); 1943 1944 if (iwn_nic_lock(sc) == 0) { 1945 IWN_WRITE(sc, IWN_FH_RX_CONFIG, 0); 1946 for (ntries = 0; ntries < 1000; ntries++) { 1947 if (IWN_READ(sc, IWN_FH_RX_STATUS) & 1948 IWN_FH_RX_STATUS_IDLE) 1949 break; 1950 DELAY(10); 1951 } 1952 iwn_nic_unlock(sc); 1953 } 1954 ring->cur = 0; 1955 sc->last_rx_valid = 0; 1956 } 1957 1958 static void 1959 iwn_free_rx_ring(struct iwn_softc *sc, struct iwn_rx_ring *ring) 1960 { 1961 int i; 1962 1963 DPRINTF(sc, IWN_DEBUG_TRACE, "->Doing %s \n", __func__); 1964 1965 iwn_dma_contig_free(&ring->desc_dma); 1966 iwn_dma_contig_free(&ring->stat_dma); 1967 1968 for (i = 0; i < IWN_RX_RING_COUNT; i++) { 1969 struct iwn_rx_data *data = &ring->data[i]; 1970 1971 if (data->m != NULL) { 1972 bus_dmamap_sync(ring->data_dmat, data->map, 1973 BUS_DMASYNC_POSTREAD); 1974 bus_dmamap_unload(ring->data_dmat, data->map); 1975 m_freem(data->m); 1976 data->m = NULL; 1977 } 1978 if (data->map != NULL) 1979 bus_dmamap_destroy(ring->data_dmat, data->map); 1980 } 1981 if (ring->data_dmat != NULL) { 1982 bus_dma_tag_destroy(ring->data_dmat); 1983 ring->data_dmat = NULL; 1984 } 1985 } 1986 1987 static int 1988 iwn_alloc_tx_ring(struct iwn_softc *sc, struct iwn_tx_ring *ring, int qid) 1989 { 1990 bus_addr_t paddr; 1991 bus_size_t size; 1992 int i, error; 1993 1994 ring->qid = qid; 1995 ring->queued = 0; 1996 ring->cur = 0; 1997 1998 DPRINTF(sc, IWN_DEBUG_TRACE, "->%s begin\n", __func__); 1999 2000 /* Allocate TX descriptors (256-byte aligned). */ 2001 size = IWN_TX_RING_COUNT * sizeof (struct iwn_tx_desc); 2002 error = iwn_dma_contig_alloc(sc, &ring->desc_dma, (void **)&ring->desc, 2003 size, 256); 2004 if (error != 0) { 2005 device_printf(sc->sc_dev, 2006 "%s: could not allocate TX ring DMA memory, error %d\n", 2007 __func__, error); 2008 goto fail; 2009 } 2010 2011 size = IWN_TX_RING_COUNT * sizeof (struct iwn_tx_cmd); 2012 error = iwn_dma_contig_alloc(sc, &ring->cmd_dma, (void **)&ring->cmd, 2013 size, 4); 2014 if (error != 0) { 2015 device_printf(sc->sc_dev, 2016 "%s: could not allocate TX cmd DMA memory, error %d\n", 2017 __func__, error); 2018 goto fail; 2019 } 2020 2021 error = bus_dma_tag_create(bus_get_dma_tag(sc->sc_dev), 1, 0, 2022 BUS_SPACE_MAXADDR_32BIT, BUS_SPACE_MAXADDR, NULL, NULL, MCLBYTES, 2023 IWN_MAX_SCATTER - 1, MCLBYTES, 0, NULL, NULL, &ring->data_dmat); 2024 if (error != 0) { 2025 device_printf(sc->sc_dev, 2026 "%s: could not create TX buf DMA tag, error %d\n", 2027 __func__, error); 2028 goto fail; 2029 } 2030 2031 paddr = ring->cmd_dma.paddr; 2032 for (i = 0; i < IWN_TX_RING_COUNT; i++) { 2033 struct iwn_tx_data *data = &ring->data[i]; 2034 2035 data->cmd_paddr = paddr; 2036 data->scratch_paddr = paddr + 12; 2037 paddr += sizeof (struct iwn_tx_cmd); 2038 2039 error = bus_dmamap_create(ring->data_dmat, 0, &data->map); 2040 if (error != 0) { 2041 device_printf(sc->sc_dev, 2042 "%s: could not create TX buf DMA map, error %d\n", 2043 __func__, error); 2044 goto fail; 2045 } 2046 } 2047 2048 DPRINTF(sc, IWN_DEBUG_TRACE, "->%s end\n", __func__); 2049 2050 return 0; 2051 2052 fail: iwn_free_tx_ring(sc, ring); 2053 DPRINTF(sc, IWN_DEBUG_TRACE, "->%s end in error\n", __func__); 2054 return error; 2055 } 2056 2057 static void 2058 iwn_reset_tx_ring(struct iwn_softc *sc, struct iwn_tx_ring *ring) 2059 { 2060 int i; 2061 2062 DPRINTF(sc, IWN_DEBUG_TRACE, "->doing %s \n", __func__); 2063 2064 for (i = 0; i < IWN_TX_RING_COUNT; i++) { 2065 struct iwn_tx_data *data = &ring->data[i]; 2066 2067 if (data->m != NULL) { 2068 bus_dmamap_sync(ring->data_dmat, data->map, 2069 BUS_DMASYNC_POSTWRITE); 2070 bus_dmamap_unload(ring->data_dmat, data->map); 2071 m_freem(data->m); 2072 data->m = NULL; 2073 } 2074 if (data->ni != NULL) { 2075 ieee80211_free_node(data->ni); 2076 data->ni = NULL; 2077 } 2078 data->remapped = 0; 2079 data->long_retries = 0; 2080 } 2081 /* Clear TX descriptors. */ 2082 memset(ring->desc, 0, ring->desc_dma.size); 2083 bus_dmamap_sync(ring->desc_dma.tag, ring->desc_dma.map, 2084 BUS_DMASYNC_PREWRITE); 2085 sc->qfullmsk &= ~(1 << ring->qid); 2086 ring->queued = 0; 2087 ring->cur = 0; 2088 } 2089 2090 static void 2091 iwn_free_tx_ring(struct iwn_softc *sc, struct iwn_tx_ring *ring) 2092 { 2093 int i; 2094 2095 DPRINTF(sc, IWN_DEBUG_TRACE, "->Doing %s \n", __func__); 2096 2097 iwn_dma_contig_free(&ring->desc_dma); 2098 iwn_dma_contig_free(&ring->cmd_dma); 2099 2100 for (i = 0; i < IWN_TX_RING_COUNT; i++) { 2101 struct iwn_tx_data *data = &ring->data[i]; 2102 2103 if (data->m != NULL) { 2104 bus_dmamap_sync(ring->data_dmat, data->map, 2105 BUS_DMASYNC_POSTWRITE); 2106 bus_dmamap_unload(ring->data_dmat, data->map); 2107 m_freem(data->m); 2108 } 2109 if (data->map != NULL) 2110 bus_dmamap_destroy(ring->data_dmat, data->map); 2111 } 2112 if (ring->data_dmat != NULL) { 2113 bus_dma_tag_destroy(ring->data_dmat); 2114 ring->data_dmat = NULL; 2115 } 2116 } 2117 2118 static void 2119 iwn_check_tx_ring(struct iwn_softc *sc, int qid) 2120 { 2121 struct iwn_tx_ring *ring = &sc->txq[qid]; 2122 2123 KASSERT(ring->queued >= 0, ("%s: ring->queued (%d) for queue %d < 0!", 2124 __func__, ring->queued, qid)); 2125 2126 if (qid >= sc->firstaggqueue) { 2127 struct iwn_ops *ops = &sc->ops; 2128 struct ieee80211_tx_ampdu *tap = sc->qid2tap[qid]; 2129 2130 if (ring->queued == 0 && !IEEE80211_AMPDU_RUNNING(tap)) { 2131 uint16_t ssn = tap->txa_start & 0xfff; 2132 uint8_t tid = tap->txa_tid; 2133 int *res = tap->txa_private; 2134 2135 iwn_nic_lock(sc); 2136 ops->ampdu_tx_stop(sc, qid, tid, ssn); 2137 iwn_nic_unlock(sc); 2138 2139 sc->qid2tap[qid] = NULL; 2140 free(res, M_DEVBUF); 2141 } 2142 } 2143 2144 if (ring->queued < IWN_TX_RING_LOMARK) { 2145 sc->qfullmsk &= ~(1 << qid); 2146 2147 if (ring->queued == 0) 2148 sc->sc_tx_timer = 0; 2149 else 2150 sc->sc_tx_timer = 5; 2151 } 2152 } 2153 2154 static void 2155 iwn5000_ict_reset(struct iwn_softc *sc) 2156 { 2157 /* Disable interrupts. */ 2158 IWN_WRITE(sc, IWN_INT_MASK, 0); 2159 2160 /* Reset ICT table. */ 2161 memset(sc->ict, 0, IWN_ICT_SIZE); 2162 sc->ict_cur = 0; 2163 2164 bus_dmamap_sync(sc->ict_dma.tag, sc->ict_dma.map, 2165 BUS_DMASYNC_PREWRITE); 2166 2167 /* Set physical address of ICT table (4KB aligned). */ 2168 DPRINTF(sc, IWN_DEBUG_RESET, "%s: enabling ICT\n", __func__); 2169 IWN_WRITE(sc, IWN_DRAM_INT_TBL, IWN_DRAM_INT_TBL_ENABLE | 2170 IWN_DRAM_INT_TBL_WRAP_CHECK | sc->ict_dma.paddr >> 12); 2171 2172 /* Enable periodic RX interrupt. */ 2173 sc->int_mask |= IWN_INT_RX_PERIODIC; 2174 /* Switch to ICT interrupt mode in driver. */ 2175 sc->sc_flags |= IWN_FLAG_USE_ICT; 2176 2177 /* Re-enable interrupts. */ 2178 IWN_WRITE(sc, IWN_INT, 0xffffffff); 2179 IWN_WRITE(sc, IWN_INT_MASK, sc->int_mask); 2180 } 2181 2182 static int 2183 iwn_read_eeprom(struct iwn_softc *sc, uint8_t macaddr[IEEE80211_ADDR_LEN]) 2184 { 2185 struct iwn_ops *ops = &sc->ops; 2186 uint16_t val; 2187 int error; 2188 2189 DPRINTF(sc, IWN_DEBUG_TRACE, "->%s begin\n", __func__); 2190 2191 /* Check whether adapter has an EEPROM or an OTPROM. */ 2192 if (sc->hw_type >= IWN_HW_REV_TYPE_1000 && 2193 (IWN_READ(sc, IWN_OTP_GP) & IWN_OTP_GP_DEV_SEL_OTP)) 2194 sc->sc_flags |= IWN_FLAG_HAS_OTPROM; 2195 DPRINTF(sc, IWN_DEBUG_RESET, "%s found\n", 2196 (sc->sc_flags & IWN_FLAG_HAS_OTPROM) ? "OTPROM" : "EEPROM"); 2197 2198 /* Adapter has to be powered on for EEPROM access to work. */ 2199 if ((error = iwn_apm_init(sc)) != 0) { 2200 device_printf(sc->sc_dev, 2201 "%s: could not power ON adapter, error %d\n", __func__, 2202 error); 2203 return error; 2204 } 2205 2206 if ((IWN_READ(sc, IWN_EEPROM_GP) & 0x7) == 0) { 2207 device_printf(sc->sc_dev, "%s: bad ROM signature\n", __func__); 2208 return EIO; 2209 } 2210 if ((error = iwn_eeprom_lock(sc)) != 0) { 2211 device_printf(sc->sc_dev, "%s: could not lock ROM, error %d\n", 2212 __func__, error); 2213 return error; 2214 } 2215 if (sc->sc_flags & IWN_FLAG_HAS_OTPROM) { 2216 if ((error = iwn_init_otprom(sc)) != 0) { 2217 device_printf(sc->sc_dev, 2218 "%s: could not initialize OTPROM, error %d\n", 2219 __func__, error); 2220 return error; 2221 } 2222 } 2223 2224 iwn_read_prom_data(sc, IWN_EEPROM_SKU_CAP, &val, 2); 2225 DPRINTF(sc, IWN_DEBUG_RESET, "SKU capabilities=0x%04x\n", le16toh(val)); 2226 /* Check if HT support is bonded out. */ 2227 if (val & htole16(IWN_EEPROM_SKU_CAP_11N)) 2228 sc->sc_flags |= IWN_FLAG_HAS_11N; 2229 2230 iwn_read_prom_data(sc, IWN_EEPROM_RFCFG, &val, 2); 2231 sc->rfcfg = le16toh(val); 2232 DPRINTF(sc, IWN_DEBUG_RESET, "radio config=0x%04x\n", sc->rfcfg); 2233 /* Read Tx/Rx chains from ROM unless it's known to be broken. */ 2234 if (sc->txchainmask == 0) 2235 sc->txchainmask = IWN_RFCFG_TXANTMSK(sc->rfcfg); 2236 if (sc->rxchainmask == 0) 2237 sc->rxchainmask = IWN_RFCFG_RXANTMSK(sc->rfcfg); 2238 2239 /* Read MAC address. */ 2240 iwn_read_prom_data(sc, IWN_EEPROM_MAC, macaddr, 6); 2241 2242 /* Read adapter-specific information from EEPROM. */ 2243 ops->read_eeprom(sc); 2244 2245 iwn_apm_stop(sc); /* Power OFF adapter. */ 2246 2247 iwn_eeprom_unlock(sc); 2248 2249 DPRINTF(sc, IWN_DEBUG_TRACE, "->%s end\n", __func__); 2250 2251 return 0; 2252 } 2253 2254 static void 2255 iwn4965_read_eeprom(struct iwn_softc *sc) 2256 { 2257 uint32_t addr; 2258 uint16_t val; 2259 int i; 2260 2261 DPRINTF(sc, IWN_DEBUG_TRACE, "->%s begin\n", __func__); 2262 2263 /* Read regulatory domain (4 ASCII characters). */ 2264 iwn_read_prom_data(sc, IWN4965_EEPROM_DOMAIN, sc->eeprom_domain, 4); 2265 2266 /* Read the list of authorized channels (20MHz & 40MHz). */ 2267 for (i = 0; i < IWN_NBANDS - 1; i++) { 2268 addr = iwn4965_regulatory_bands[i]; 2269 iwn_read_eeprom_channels(sc, i, addr); 2270 } 2271 2272 /* Read maximum allowed TX power for 2GHz and 5GHz bands. */ 2273 iwn_read_prom_data(sc, IWN4965_EEPROM_MAXPOW, &val, 2); 2274 sc->maxpwr2GHz = val & 0xff; 2275 sc->maxpwr5GHz = val >> 8; 2276 /* Check that EEPROM values are within valid range. */ 2277 if (sc->maxpwr5GHz < 20 || sc->maxpwr5GHz > 50) 2278 sc->maxpwr5GHz = 38; 2279 if (sc->maxpwr2GHz < 20 || sc->maxpwr2GHz > 50) 2280 sc->maxpwr2GHz = 38; 2281 DPRINTF(sc, IWN_DEBUG_RESET, "maxpwr 2GHz=%d 5GHz=%d\n", 2282 sc->maxpwr2GHz, sc->maxpwr5GHz); 2283 2284 /* Read samples for each TX power group. */ 2285 iwn_read_prom_data(sc, IWN4965_EEPROM_BANDS, sc->bands, 2286 sizeof sc->bands); 2287 2288 /* Read voltage at which samples were taken. */ 2289 iwn_read_prom_data(sc, IWN4965_EEPROM_VOLTAGE, &val, 2); 2290 sc->eeprom_voltage = (int16_t)le16toh(val); 2291 DPRINTF(sc, IWN_DEBUG_RESET, "voltage=%d (in 0.3V)\n", 2292 sc->eeprom_voltage); 2293 2294 #ifdef IWN_DEBUG 2295 /* Print samples. */ 2296 if (sc->sc_debug & IWN_DEBUG_ANY) { 2297 for (i = 0; i < IWN_NBANDS - 1; i++) 2298 iwn4965_print_power_group(sc, i); 2299 } 2300 #endif 2301 2302 DPRINTF(sc, IWN_DEBUG_TRACE, "->%s end\n", __func__); 2303 } 2304 2305 #ifdef IWN_DEBUG 2306 static void 2307 iwn4965_print_power_group(struct iwn_softc *sc, int i) 2308 { 2309 struct iwn4965_eeprom_band *band = &sc->bands[i]; 2310 struct iwn4965_eeprom_chan_samples *chans = band->chans; 2311 int j, c; 2312 2313 printf("===band %d===\n", i); 2314 printf("chan lo=%d, chan hi=%d\n", band->lo, band->hi); 2315 printf("chan1 num=%d\n", chans[0].num); 2316 for (c = 0; c < 2; c++) { 2317 for (j = 0; j < IWN_NSAMPLES; j++) { 2318 printf("chain %d, sample %d: temp=%d gain=%d " 2319 "power=%d pa_det=%d\n", c, j, 2320 chans[0].samples[c][j].temp, 2321 chans[0].samples[c][j].gain, 2322 chans[0].samples[c][j].power, 2323 chans[0].samples[c][j].pa_det); 2324 } 2325 } 2326 printf("chan2 num=%d\n", chans[1].num); 2327 for (c = 0; c < 2; c++) { 2328 for (j = 0; j < IWN_NSAMPLES; j++) { 2329 printf("chain %d, sample %d: temp=%d gain=%d " 2330 "power=%d pa_det=%d\n", c, j, 2331 chans[1].samples[c][j].temp, 2332 chans[1].samples[c][j].gain, 2333 chans[1].samples[c][j].power, 2334 chans[1].samples[c][j].pa_det); 2335 } 2336 } 2337 } 2338 #endif 2339 2340 static void 2341 iwn5000_read_eeprom(struct iwn_softc *sc) 2342 { 2343 struct iwn5000_eeprom_calib_hdr hdr; 2344 int32_t volt; 2345 uint32_t base, addr; 2346 uint16_t val; 2347 int i; 2348 2349 DPRINTF(sc, IWN_DEBUG_TRACE, "->%s begin\n", __func__); 2350 2351 /* Read regulatory domain (4 ASCII characters). */ 2352 iwn_read_prom_data(sc, IWN5000_EEPROM_REG, &val, 2); 2353 base = le16toh(val); 2354 iwn_read_prom_data(sc, base + IWN5000_EEPROM_DOMAIN, 2355 sc->eeprom_domain, 4); 2356 2357 /* Read the list of authorized channels (20MHz & 40MHz). */ 2358 for (i = 0; i < IWN_NBANDS - 1; i++) { 2359 addr = base + sc->base_params->regulatory_bands[i]; 2360 iwn_read_eeprom_channels(sc, i, addr); 2361 } 2362 2363 /* Read enhanced TX power information for 6000 Series. */ 2364 if (sc->base_params->enhanced_TX_power) 2365 iwn_read_eeprom_enhinfo(sc); 2366 2367 iwn_read_prom_data(sc, IWN5000_EEPROM_CAL, &val, 2); 2368 base = le16toh(val); 2369 iwn_read_prom_data(sc, base, &hdr, sizeof hdr); 2370 DPRINTF(sc, IWN_DEBUG_CALIBRATE, 2371 "%s: calib version=%u pa type=%u voltage=%u\n", __func__, 2372 hdr.version, hdr.pa_type, le16toh(hdr.volt)); 2373 sc->calib_ver = hdr.version; 2374 2375 if (sc->base_params->calib_need & IWN_FLG_NEED_PHY_CALIB_TEMP_OFFSETv2) { 2376 sc->eeprom_voltage = le16toh(hdr.volt); 2377 iwn_read_prom_data(sc, base + IWN5000_EEPROM_TEMP, &val, 2); 2378 sc->eeprom_temp_high=le16toh(val); 2379 iwn_read_prom_data(sc, base + IWN5000_EEPROM_VOLT, &val, 2); 2380 sc->eeprom_temp = le16toh(val); 2381 } 2382 2383 if (sc->hw_type == IWN_HW_REV_TYPE_5150) { 2384 /* Compute temperature offset. */ 2385 iwn_read_prom_data(sc, base + IWN5000_EEPROM_TEMP, &val, 2); 2386 sc->eeprom_temp = le16toh(val); 2387 iwn_read_prom_data(sc, base + IWN5000_EEPROM_VOLT, &val, 2); 2388 volt = le16toh(val); 2389 sc->temp_off = sc->eeprom_temp - (volt / -5); 2390 DPRINTF(sc, IWN_DEBUG_CALIBRATE, "temp=%d volt=%d offset=%dK\n", 2391 sc->eeprom_temp, volt, sc->temp_off); 2392 } else { 2393 /* Read crystal calibration. */ 2394 iwn_read_prom_data(sc, base + IWN5000_EEPROM_CRYSTAL, 2395 &sc->eeprom_crystal, sizeof (uint32_t)); 2396 DPRINTF(sc, IWN_DEBUG_CALIBRATE, "crystal calibration 0x%08x\n", 2397 le32toh(sc->eeprom_crystal)); 2398 } 2399 2400 DPRINTF(sc, IWN_DEBUG_TRACE, "->%s end\n", __func__); 2401 2402 } 2403 2404 /* 2405 * Translate EEPROM flags to net80211. 2406 */ 2407 static uint32_t 2408 iwn_eeprom_channel_flags(struct iwn_eeprom_chan *channel) 2409 { 2410 uint32_t nflags; 2411 2412 nflags = 0; 2413 if ((channel->flags & IWN_EEPROM_CHAN_ACTIVE) == 0) 2414 nflags |= IEEE80211_CHAN_PASSIVE; 2415 if ((channel->flags & IWN_EEPROM_CHAN_IBSS) == 0) 2416 nflags |= IEEE80211_CHAN_NOADHOC; 2417 if (channel->flags & IWN_EEPROM_CHAN_RADAR) { 2418 nflags |= IEEE80211_CHAN_DFS; 2419 /* XXX apparently IBSS may still be marked */ 2420 nflags |= IEEE80211_CHAN_NOADHOC; 2421 } 2422 2423 return nflags; 2424 } 2425 2426 static void 2427 iwn_read_eeprom_band(struct iwn_softc *sc, int n, int maxchans, int *nchans, 2428 struct ieee80211_channel chans[]) 2429 { 2430 struct iwn_eeprom_chan *channels = sc->eeprom_channels[n]; 2431 const struct iwn_chan_band *band = &iwn_bands[n]; 2432 uint8_t bands[IEEE80211_MODE_BYTES]; 2433 uint8_t chan; 2434 int i, error, nflags; 2435 2436 DPRINTF(sc, IWN_DEBUG_TRACE, "->%s begin\n", __func__); 2437 2438 memset(bands, 0, sizeof(bands)); 2439 if (n == 0) { 2440 setbit(bands, IEEE80211_MODE_11B); 2441 setbit(bands, IEEE80211_MODE_11G); 2442 if (sc->sc_flags & IWN_FLAG_HAS_11N) 2443 setbit(bands, IEEE80211_MODE_11NG); 2444 } else { 2445 setbit(bands, IEEE80211_MODE_11A); 2446 if (sc->sc_flags & IWN_FLAG_HAS_11N) 2447 setbit(bands, IEEE80211_MODE_11NA); 2448 } 2449 2450 for (i = 0; i < band->nchan; i++) { 2451 if (!(channels[i].flags & IWN_EEPROM_CHAN_VALID)) { 2452 DPRINTF(sc, IWN_DEBUG_RESET, 2453 "skip chan %d flags 0x%x maxpwr %d\n", 2454 band->chan[i], channels[i].flags, 2455 channels[i].maxpwr); 2456 continue; 2457 } 2458 2459 chan = band->chan[i]; 2460 nflags = iwn_eeprom_channel_flags(&channels[i]); 2461 error = ieee80211_add_channel(chans, maxchans, nchans, 2462 chan, 0, channels[i].maxpwr, nflags, bands); 2463 if (error != 0) 2464 break; 2465 2466 /* Save maximum allowed TX power for this channel. */ 2467 /* XXX wrong */ 2468 sc->maxpwr[chan] = channels[i].maxpwr; 2469 2470 DPRINTF(sc, IWN_DEBUG_RESET, 2471 "add chan %d flags 0x%x maxpwr %d\n", chan, 2472 channels[i].flags, channels[i].maxpwr); 2473 } 2474 2475 DPRINTF(sc, IWN_DEBUG_TRACE, "->%s end\n", __func__); 2476 2477 } 2478 2479 static void 2480 iwn_read_eeprom_ht40(struct iwn_softc *sc, int n, int maxchans, int *nchans, 2481 struct ieee80211_channel chans[]) 2482 { 2483 struct iwn_eeprom_chan *channels = sc->eeprom_channels[n]; 2484 const struct iwn_chan_band *band = &iwn_bands[n]; 2485 uint8_t chan; 2486 int i, error, nflags; 2487 2488 DPRINTF(sc, IWN_DEBUG_TRACE, "->%s start\n", __func__); 2489 2490 if (!(sc->sc_flags & IWN_FLAG_HAS_11N)) { 2491 DPRINTF(sc, IWN_DEBUG_TRACE, "->%s end no 11n\n", __func__); 2492 return; 2493 } 2494 2495 for (i = 0; i < band->nchan; i++) { 2496 if (!(channels[i].flags & IWN_EEPROM_CHAN_VALID)) { 2497 DPRINTF(sc, IWN_DEBUG_RESET, 2498 "skip chan %d flags 0x%x maxpwr %d\n", 2499 band->chan[i], channels[i].flags, 2500 channels[i].maxpwr); 2501 continue; 2502 } 2503 2504 chan = band->chan[i]; 2505 nflags = iwn_eeprom_channel_flags(&channels[i]); 2506 nflags |= (n == 5 ? IEEE80211_CHAN_G : IEEE80211_CHAN_A); 2507 error = ieee80211_add_channel_ht40(chans, maxchans, nchans, 2508 chan, channels[i].maxpwr, nflags); 2509 switch (error) { 2510 case EINVAL: 2511 device_printf(sc->sc_dev, 2512 "%s: no entry for channel %d\n", __func__, chan); 2513 continue; 2514 case ENOENT: 2515 DPRINTF(sc, IWN_DEBUG_RESET, 2516 "%s: skip chan %d, extension channel not found\n", 2517 __func__, chan); 2518 continue; 2519 case ENOBUFS: 2520 device_printf(sc->sc_dev, 2521 "%s: channel table is full!\n", __func__); 2522 break; 2523 case 0: 2524 DPRINTF(sc, IWN_DEBUG_RESET, 2525 "add ht40 chan %d flags 0x%x maxpwr %d\n", 2526 chan, channels[i].flags, channels[i].maxpwr); 2527 /* FALLTHROUGH */ 2528 default: 2529 break; 2530 } 2531 } 2532 2533 DPRINTF(sc, IWN_DEBUG_TRACE, "->%s end\n", __func__); 2534 2535 } 2536 2537 static void 2538 iwn_read_eeprom_channels(struct iwn_softc *sc, int n, uint32_t addr) 2539 { 2540 struct ieee80211com *ic = &sc->sc_ic; 2541 2542 iwn_read_prom_data(sc, addr, &sc->eeprom_channels[n], 2543 iwn_bands[n].nchan * sizeof (struct iwn_eeprom_chan)); 2544 2545 if (n < 5) { 2546 iwn_read_eeprom_band(sc, n, IEEE80211_CHAN_MAX, &ic->ic_nchans, 2547 ic->ic_channels); 2548 } else { 2549 iwn_read_eeprom_ht40(sc, n, IEEE80211_CHAN_MAX, &ic->ic_nchans, 2550 ic->ic_channels); 2551 } 2552 ieee80211_sort_channels(ic->ic_channels, ic->ic_nchans); 2553 } 2554 2555 static struct iwn_eeprom_chan * 2556 iwn_find_eeprom_channel(struct iwn_softc *sc, struct ieee80211_channel *c) 2557 { 2558 int band, chan, i, j; 2559 2560 if (IEEE80211_IS_CHAN_HT40(c)) { 2561 band = IEEE80211_IS_CHAN_5GHZ(c) ? 6 : 5; 2562 if (IEEE80211_IS_CHAN_HT40D(c)) 2563 chan = c->ic_extieee; 2564 else 2565 chan = c->ic_ieee; 2566 for (i = 0; i < iwn_bands[band].nchan; i++) { 2567 if (iwn_bands[band].chan[i] == chan) 2568 return &sc->eeprom_channels[band][i]; 2569 } 2570 } else { 2571 for (j = 0; j < 5; j++) { 2572 for (i = 0; i < iwn_bands[j].nchan; i++) { 2573 if (iwn_bands[j].chan[i] == c->ic_ieee && 2574 ((j == 0) ^ IEEE80211_IS_CHAN_A(c)) == 1) 2575 return &sc->eeprom_channels[j][i]; 2576 } 2577 } 2578 } 2579 return NULL; 2580 } 2581 2582 static void 2583 iwn_getradiocaps(struct ieee80211com *ic, 2584 int maxchans, int *nchans, struct ieee80211_channel chans[]) 2585 { 2586 struct iwn_softc *sc = ic->ic_softc; 2587 int i; 2588 2589 /* Parse the list of authorized channels. */ 2590 for (i = 0; i < 5 && *nchans < maxchans; i++) 2591 iwn_read_eeprom_band(sc, i, maxchans, nchans, chans); 2592 for (i = 5; i < IWN_NBANDS - 1 && *nchans < maxchans; i++) 2593 iwn_read_eeprom_ht40(sc, i, maxchans, nchans, chans); 2594 } 2595 2596 /* 2597 * Enforce flags read from EEPROM. 2598 */ 2599 static int 2600 iwn_setregdomain(struct ieee80211com *ic, struct ieee80211_regdomain *rd, 2601 int nchan, struct ieee80211_channel chans[]) 2602 { 2603 struct iwn_softc *sc = ic->ic_softc; 2604 int i; 2605 2606 for (i = 0; i < nchan; i++) { 2607 struct ieee80211_channel *c = &chans[i]; 2608 struct iwn_eeprom_chan *channel; 2609 2610 channel = iwn_find_eeprom_channel(sc, c); 2611 if (channel == NULL) { 2612 ic_printf(ic, "%s: invalid channel %u freq %u/0x%x\n", 2613 __func__, c->ic_ieee, c->ic_freq, c->ic_flags); 2614 return EINVAL; 2615 } 2616 c->ic_flags |= iwn_eeprom_channel_flags(channel); 2617 } 2618 2619 return 0; 2620 } 2621 2622 static void 2623 iwn_read_eeprom_enhinfo(struct iwn_softc *sc) 2624 { 2625 struct iwn_eeprom_enhinfo enhinfo[35]; 2626 struct ieee80211com *ic = &sc->sc_ic; 2627 struct ieee80211_channel *c; 2628 uint16_t val, base; 2629 int8_t maxpwr; 2630 uint8_t flags; 2631 int i, j; 2632 2633 DPRINTF(sc, IWN_DEBUG_TRACE, "->%s begin\n", __func__); 2634 2635 iwn_read_prom_data(sc, IWN5000_EEPROM_REG, &val, 2); 2636 base = le16toh(val); 2637 iwn_read_prom_data(sc, base + IWN6000_EEPROM_ENHINFO, 2638 enhinfo, sizeof enhinfo); 2639 2640 for (i = 0; i < nitems(enhinfo); i++) { 2641 flags = enhinfo[i].flags; 2642 if (!(flags & IWN_ENHINFO_VALID)) 2643 continue; /* Skip invalid entries. */ 2644 2645 maxpwr = 0; 2646 if (sc->txchainmask & IWN_ANT_A) 2647 maxpwr = MAX(maxpwr, enhinfo[i].chain[0]); 2648 if (sc->txchainmask & IWN_ANT_B) 2649 maxpwr = MAX(maxpwr, enhinfo[i].chain[1]); 2650 if (sc->txchainmask & IWN_ANT_C) 2651 maxpwr = MAX(maxpwr, enhinfo[i].chain[2]); 2652 if (sc->ntxchains == 2) 2653 maxpwr = MAX(maxpwr, enhinfo[i].mimo2); 2654 else if (sc->ntxchains == 3) 2655 maxpwr = MAX(maxpwr, enhinfo[i].mimo3); 2656 2657 for (j = 0; j < ic->ic_nchans; j++) { 2658 c = &ic->ic_channels[j]; 2659 if ((flags & IWN_ENHINFO_5GHZ)) { 2660 if (!IEEE80211_IS_CHAN_A(c)) 2661 continue; 2662 } else if ((flags & IWN_ENHINFO_OFDM)) { 2663 if (!IEEE80211_IS_CHAN_G(c)) 2664 continue; 2665 } else if (!IEEE80211_IS_CHAN_B(c)) 2666 continue; 2667 if ((flags & IWN_ENHINFO_HT40)) { 2668 if (!IEEE80211_IS_CHAN_HT40(c)) 2669 continue; 2670 } else { 2671 if (IEEE80211_IS_CHAN_HT40(c)) 2672 continue; 2673 } 2674 if (enhinfo[i].chan != 0 && 2675 enhinfo[i].chan != c->ic_ieee) 2676 continue; 2677 2678 DPRINTF(sc, IWN_DEBUG_RESET, 2679 "channel %d(%x), maxpwr %d\n", c->ic_ieee, 2680 c->ic_flags, maxpwr / 2); 2681 c->ic_maxregpower = maxpwr / 2; 2682 c->ic_maxpower = maxpwr; 2683 } 2684 } 2685 2686 DPRINTF(sc, IWN_DEBUG_TRACE, "->%s end\n", __func__); 2687 2688 } 2689 2690 static struct ieee80211_node * 2691 iwn_node_alloc(struct ieee80211vap *vap, const uint8_t mac[IEEE80211_ADDR_LEN]) 2692 { 2693 struct iwn_node *wn; 2694 2695 wn = malloc(sizeof (struct iwn_node), M_80211_NODE, M_NOWAIT | M_ZERO); 2696 if (wn == NULL) 2697 return (NULL); 2698 2699 wn->id = IWN_ID_UNDEFINED; 2700 2701 return (&wn->ni); 2702 } 2703 2704 static __inline int 2705 rate2plcp(int rate) 2706 { 2707 switch (rate & 0xff) { 2708 case 12: return 0xd; 2709 case 18: return 0xf; 2710 case 24: return 0x5; 2711 case 36: return 0x7; 2712 case 48: return 0x9; 2713 case 72: return 0xb; 2714 case 96: return 0x1; 2715 case 108: return 0x3; 2716 case 2: return 10; 2717 case 4: return 20; 2718 case 11: return 55; 2719 case 22: return 110; 2720 } 2721 return 0; 2722 } 2723 2724 static __inline uint8_t 2725 plcp2rate(const uint8_t rate_plcp) 2726 { 2727 switch (rate_plcp) { 2728 case 0xd: return 12; 2729 case 0xf: return 18; 2730 case 0x5: return 24; 2731 case 0x7: return 36; 2732 case 0x9: return 48; 2733 case 0xb: return 72; 2734 case 0x1: return 96; 2735 case 0x3: return 108; 2736 case 10: return 2; 2737 case 20: return 4; 2738 case 55: return 11; 2739 case 110: return 22; 2740 default: return 0; 2741 } 2742 } 2743 2744 static int 2745 iwn_get_1stream_tx_antmask(struct iwn_softc *sc) 2746 { 2747 2748 return IWN_LSB(sc->txchainmask); 2749 } 2750 2751 static int 2752 iwn_get_2stream_tx_antmask(struct iwn_softc *sc) 2753 { 2754 int tx; 2755 2756 /* 2757 * The '2 stream' setup is a bit .. odd. 2758 * 2759 * For NICs that support only 1 antenna, default to IWN_ANT_AB or 2760 * the firmware panics (eg Intel 5100.) 2761 * 2762 * For NICs that support two antennas, we use ANT_AB. 2763 * 2764 * For NICs that support three antennas, we use the two that 2765 * wasn't the default one. 2766 * 2767 * XXX TODO: if bluetooth (full concurrent) is enabled, restrict 2768 * this to only one antenna. 2769 */ 2770 2771 /* Default - transmit on the other antennas */ 2772 tx = (sc->txchainmask & ~IWN_LSB(sc->txchainmask)); 2773 2774 /* Now, if it's zero, set it to IWN_ANT_AB, so to not panic firmware */ 2775 if (tx == 0) 2776 tx = IWN_ANT_AB; 2777 2778 /* 2779 * If the NIC is a two-stream TX NIC, configure the TX mask to 2780 * the default chainmask 2781 */ 2782 else if (sc->ntxchains == 2) 2783 tx = sc->txchainmask; 2784 2785 return (tx); 2786 } 2787 2788 2789 2790 /* 2791 * Calculate the required PLCP value from the given rate, 2792 * to the given node. 2793 * 2794 * This will take the node configuration (eg 11n, rate table 2795 * setup, etc) into consideration. 2796 */ 2797 static uint32_t 2798 iwn_rate_to_plcp(struct iwn_softc *sc, struct ieee80211_node *ni, 2799 uint8_t rate) 2800 { 2801 struct ieee80211com *ic = ni->ni_ic; 2802 uint32_t plcp = 0; 2803 int ridx; 2804 2805 /* 2806 * If it's an MCS rate, let's set the plcp correctly 2807 * and set the relevant flags based on the node config. 2808 */ 2809 if (rate & IEEE80211_RATE_MCS) { 2810 /* 2811 * Set the initial PLCP value to be between 0->31 for 2812 * MCS 0 -> MCS 31, then set the "I'm an MCS rate!" 2813 * flag. 2814 */ 2815 plcp = IEEE80211_RV(rate) | IWN_RFLAG_MCS; 2816 2817 /* 2818 * XXX the following should only occur if both 2819 * the local configuration _and_ the remote node 2820 * advertise these capabilities. Thus this code 2821 * may need fixing! 2822 */ 2823 2824 /* 2825 * Set the channel width and guard interval. 2826 */ 2827 if (IEEE80211_IS_CHAN_HT40(ni->ni_chan)) { 2828 plcp |= IWN_RFLAG_HT40; 2829 if (ni->ni_htcap & IEEE80211_HTCAP_SHORTGI40) 2830 plcp |= IWN_RFLAG_SGI; 2831 } else if (ni->ni_htcap & IEEE80211_HTCAP_SHORTGI20) { 2832 plcp |= IWN_RFLAG_SGI; 2833 } 2834 2835 /* 2836 * Ensure the selected rate matches the link quality 2837 * table entries being used. 2838 */ 2839 if (rate > 0x8f) 2840 plcp |= IWN_RFLAG_ANT(sc->txchainmask); 2841 else if (rate > 0x87) 2842 plcp |= IWN_RFLAG_ANT(iwn_get_2stream_tx_antmask(sc)); 2843 else 2844 plcp |= IWN_RFLAG_ANT(iwn_get_1stream_tx_antmask(sc)); 2845 } else { 2846 /* 2847 * Set the initial PLCP - fine for both 2848 * OFDM and CCK rates. 2849 */ 2850 plcp = rate2plcp(rate); 2851 2852 /* Set CCK flag if it's CCK */ 2853 2854 /* XXX It would be nice to have a method 2855 * to map the ridx -> phy table entry 2856 * so we could just query that, rather than 2857 * this hack to check against IWN_RIDX_OFDM6. 2858 */ 2859 ridx = ieee80211_legacy_rate_lookup(ic->ic_rt, 2860 rate & IEEE80211_RATE_VAL); 2861 if (ridx < IWN_RIDX_OFDM6 && 2862 IEEE80211_IS_CHAN_2GHZ(ni->ni_chan)) 2863 plcp |= IWN_RFLAG_CCK; 2864 2865 /* Set antenna configuration */ 2866 /* XXX TODO: is this the right antenna to use for legacy? */ 2867 plcp |= IWN_RFLAG_ANT(iwn_get_1stream_tx_antmask(sc)); 2868 } 2869 2870 DPRINTF(sc, IWN_DEBUG_TXRATE, "%s: rate=0x%02x, plcp=0x%08x\n", 2871 __func__, 2872 rate, 2873 plcp); 2874 2875 return (htole32(plcp)); 2876 } 2877 2878 static void 2879 iwn_newassoc(struct ieee80211_node *ni, int isnew) 2880 { 2881 /* Doesn't do anything at the moment */ 2882 } 2883 2884 static int 2885 iwn_media_change(struct ifnet *ifp) 2886 { 2887 int error; 2888 2889 error = ieee80211_media_change(ifp); 2890 /* NB: only the fixed rate can change and that doesn't need a reset */ 2891 return (error == ENETRESET ? 0 : error); 2892 } 2893 2894 static int 2895 iwn_newstate(struct ieee80211vap *vap, enum ieee80211_state nstate, int arg) 2896 { 2897 struct iwn_vap *ivp = IWN_VAP(vap); 2898 struct ieee80211com *ic = vap->iv_ic; 2899 struct iwn_softc *sc = ic->ic_softc; 2900 int error = 0; 2901 2902 DPRINTF(sc, IWN_DEBUG_TRACE, "->%s begin\n", __func__); 2903 2904 DPRINTF(sc, IWN_DEBUG_STATE, "%s: %s -> %s\n", __func__, 2905 ieee80211_state_name[vap->iv_state], ieee80211_state_name[nstate]); 2906 2907 IEEE80211_UNLOCK(ic); 2908 IWN_LOCK(sc); 2909 callout_stop(&sc->calib_to); 2910 2911 sc->rxon = &sc->rx_on[IWN_RXON_BSS_CTX]; 2912 2913 switch (nstate) { 2914 case IEEE80211_S_ASSOC: 2915 if (vap->iv_state != IEEE80211_S_RUN) 2916 break; 2917 /* FALLTHROUGH */ 2918 case IEEE80211_S_AUTH: 2919 if (vap->iv_state == IEEE80211_S_AUTH) 2920 break; 2921 2922 /* 2923 * !AUTH -> AUTH transition requires state reset to handle 2924 * reassociations correctly. 2925 */ 2926 sc->rxon->associd = 0; 2927 sc->rxon->filter &= ~htole32(IWN_FILTER_BSS); 2928 sc->calib.state = IWN_CALIB_STATE_INIT; 2929 2930 /* Wait until we hear a beacon before we transmit */ 2931 if (IEEE80211_IS_CHAN_PASSIVE(ic->ic_curchan)) 2932 sc->sc_beacon_wait = 1; 2933 2934 if ((error = iwn_auth(sc, vap)) != 0) { 2935 device_printf(sc->sc_dev, 2936 "%s: could not move to auth state\n", __func__); 2937 } 2938 break; 2939 2940 case IEEE80211_S_RUN: 2941 /* 2942 * RUN -> RUN transition; Just restart the timers. 2943 */ 2944 if (vap->iv_state == IEEE80211_S_RUN) { 2945 sc->calib_cnt = 0; 2946 break; 2947 } 2948 2949 /* Wait until we hear a beacon before we transmit */ 2950 if (IEEE80211_IS_CHAN_PASSIVE(ic->ic_curchan)) 2951 sc->sc_beacon_wait = 1; 2952 2953 /* 2954 * !RUN -> RUN requires setting the association id 2955 * which is done with a firmware cmd. We also defer 2956 * starting the timers until that work is done. 2957 */ 2958 if ((error = iwn_run(sc, vap)) != 0) { 2959 device_printf(sc->sc_dev, 2960 "%s: could not move to run state\n", __func__); 2961 } 2962 break; 2963 2964 case IEEE80211_S_INIT: 2965 sc->calib.state = IWN_CALIB_STATE_INIT; 2966 /* 2967 * Purge the xmit queue so we don't have old frames 2968 * during a new association attempt. 2969 */ 2970 sc->sc_beacon_wait = 0; 2971 iwn_xmit_queue_drain(sc); 2972 break; 2973 2974 default: 2975 break; 2976 } 2977 IWN_UNLOCK(sc); 2978 IEEE80211_LOCK(ic); 2979 if (error != 0){ 2980 DPRINTF(sc, IWN_DEBUG_TRACE, "->%s end in error\n", __func__); 2981 return error; 2982 } 2983 2984 DPRINTF(sc, IWN_DEBUG_TRACE, "->%s: end\n",__func__); 2985 2986 return ivp->iv_newstate(vap, nstate, arg); 2987 } 2988 2989 static void 2990 iwn_calib_timeout(void *arg) 2991 { 2992 struct iwn_softc *sc = arg; 2993 2994 IWN_LOCK_ASSERT(sc); 2995 2996 /* Force automatic TX power calibration every 60 secs. */ 2997 if (++sc->calib_cnt >= 120) { 2998 uint32_t flags = 0; 2999 3000 DPRINTF(sc, IWN_DEBUG_CALIBRATE, "%s\n", 3001 "sending request for statistics"); 3002 (void)iwn_cmd(sc, IWN_CMD_GET_STATISTICS, &flags, 3003 sizeof flags, 1); 3004 sc->calib_cnt = 0; 3005 } 3006 callout_reset(&sc->calib_to, msecs_to_ticks(500), iwn_calib_timeout, 3007 sc); 3008 } 3009 3010 /* 3011 * Process an RX_PHY firmware notification. This is usually immediately 3012 * followed by an MPDU_RX_DONE notification. 3013 */ 3014 static void 3015 iwn_rx_phy(struct iwn_softc *sc, struct iwn_rx_desc *desc) 3016 { 3017 struct iwn_rx_stat *stat = (struct iwn_rx_stat *)(desc + 1); 3018 3019 DPRINTF(sc, IWN_DEBUG_CALIBRATE, "%s: received PHY stats\n", __func__); 3020 3021 /* Save RX statistics, they will be used on MPDU_RX_DONE. */ 3022 memcpy(&sc->last_rx_stat, stat, sizeof (*stat)); 3023 sc->last_rx_valid = 1; 3024 } 3025 3026 /* 3027 * Process an RX_DONE (4965AGN only) or MPDU_RX_DONE firmware notification. 3028 * Each MPDU_RX_DONE notification must be preceded by an RX_PHY one. 3029 */ 3030 static void 3031 iwn_rx_done(struct iwn_softc *sc, struct iwn_rx_desc *desc, 3032 struct iwn_rx_data *data) 3033 { 3034 struct epoch_tracker et; 3035 struct iwn_ops *ops = &sc->ops; 3036 struct ieee80211com *ic = &sc->sc_ic; 3037 struct iwn_rx_ring *ring = &sc->rxq; 3038 struct ieee80211_frame_min *wh; 3039 struct ieee80211_node *ni; 3040 struct mbuf *m, *m1; 3041 struct iwn_rx_stat *stat; 3042 caddr_t head; 3043 bus_addr_t paddr; 3044 uint32_t flags; 3045 int error, len, rssi, nf; 3046 3047 DPRINTF(sc, IWN_DEBUG_TRACE, "->%s begin\n", __func__); 3048 3049 if (desc->type == IWN_MPDU_RX_DONE) { 3050 /* Check for prior RX_PHY notification. */ 3051 if (!sc->last_rx_valid) { 3052 DPRINTF(sc, IWN_DEBUG_ANY, 3053 "%s: missing RX_PHY\n", __func__); 3054 return; 3055 } 3056 stat = &sc->last_rx_stat; 3057 } else 3058 stat = (struct iwn_rx_stat *)(desc + 1); 3059 3060 if (stat->cfg_phy_len > IWN_STAT_MAXLEN) { 3061 device_printf(sc->sc_dev, 3062 "%s: invalid RX statistic header, len %d\n", __func__, 3063 stat->cfg_phy_len); 3064 return; 3065 } 3066 if (desc->type == IWN_MPDU_RX_DONE) { 3067 struct iwn_rx_mpdu *mpdu = (struct iwn_rx_mpdu *)(desc + 1); 3068 head = (caddr_t)(mpdu + 1); 3069 len = le16toh(mpdu->len); 3070 } else { 3071 head = (caddr_t)(stat + 1) + stat->cfg_phy_len; 3072 len = le16toh(stat->len); 3073 } 3074 3075 flags = le32toh(*(uint32_t *)(head + len)); 3076 3077 /* Discard frames with a bad FCS early. */ 3078 if ((flags & IWN_RX_NOERROR) != IWN_RX_NOERROR) { 3079 DPRINTF(sc, IWN_DEBUG_RECV, "%s: RX flags error %x\n", 3080 __func__, flags); 3081 counter_u64_add(ic->ic_ierrors, 1); 3082 return; 3083 } 3084 /* Discard frames that are too short. */ 3085 if (len < sizeof (struct ieee80211_frame_ack)) { 3086 DPRINTF(sc, IWN_DEBUG_RECV, "%s: frame too short: %d\n", 3087 __func__, len); 3088 counter_u64_add(ic->ic_ierrors, 1); 3089 return; 3090 } 3091 3092 m1 = m_getjcl(M_NOWAIT, MT_DATA, M_PKTHDR, IWN_RBUF_SIZE); 3093 if (m1 == NULL) { 3094 DPRINTF(sc, IWN_DEBUG_ANY, "%s: no mbuf to restock ring\n", 3095 __func__); 3096 counter_u64_add(ic->ic_ierrors, 1); 3097 return; 3098 } 3099 bus_dmamap_unload(ring->data_dmat, data->map); 3100 3101 error = bus_dmamap_load(ring->data_dmat, data->map, mtod(m1, void *), 3102 IWN_RBUF_SIZE, iwn_dma_map_addr, &paddr, BUS_DMA_NOWAIT); 3103 if (error != 0 && error != EFBIG) { 3104 device_printf(sc->sc_dev, 3105 "%s: bus_dmamap_load failed, error %d\n", __func__, error); 3106 m_freem(m1); 3107 3108 /* Try to reload the old mbuf. */ 3109 error = bus_dmamap_load(ring->data_dmat, data->map, 3110 mtod(data->m, void *), IWN_RBUF_SIZE, iwn_dma_map_addr, 3111 &paddr, BUS_DMA_NOWAIT); 3112 if (error != 0 && error != EFBIG) { 3113 panic("%s: could not load old RX mbuf", __func__); 3114 } 3115 bus_dmamap_sync(ring->data_dmat, data->map, 3116 BUS_DMASYNC_PREREAD); 3117 /* Physical address may have changed. */ 3118 ring->desc[ring->cur] = htole32(paddr >> 8); 3119 bus_dmamap_sync(ring->desc_dma.tag, ring->desc_dma.map, 3120 BUS_DMASYNC_PREWRITE); 3121 counter_u64_add(ic->ic_ierrors, 1); 3122 return; 3123 } 3124 3125 bus_dmamap_sync(ring->data_dmat, data->map, 3126 BUS_DMASYNC_PREREAD); 3127 3128 m = data->m; 3129 data->m = m1; 3130 /* Update RX descriptor. */ 3131 ring->desc[ring->cur] = htole32(paddr >> 8); 3132 bus_dmamap_sync(ring->desc_dma.tag, ring->desc_dma.map, 3133 BUS_DMASYNC_PREWRITE); 3134 3135 /* Finalize mbuf. */ 3136 m->m_data = head; 3137 m->m_pkthdr.len = m->m_len = len; 3138 3139 /* Grab a reference to the source node. */ 3140 wh = mtod(m, struct ieee80211_frame_min *); 3141 if (len >= sizeof(struct ieee80211_frame_min)) 3142 ni = ieee80211_find_rxnode(ic, wh); 3143 else 3144 ni = NULL; 3145 nf = (ni != NULL && ni->ni_vap->iv_state == IEEE80211_S_RUN && 3146 (ic->ic_flags & IEEE80211_F_SCAN) == 0) ? sc->noise : -95; 3147 3148 rssi = ops->get_rssi(sc, stat); 3149 3150 if (ieee80211_radiotap_active(ic)) { 3151 struct iwn_rx_radiotap_header *tap = &sc->sc_rxtap; 3152 uint32_t rate = le32toh(stat->rate); 3153 3154 tap->wr_flags = 0; 3155 if (stat->flags & htole16(IWN_STAT_FLAG_SHPREAMBLE)) 3156 tap->wr_flags |= IEEE80211_RADIOTAP_F_SHORTPRE; 3157 tap->wr_dbm_antsignal = (int8_t)rssi; 3158 tap->wr_dbm_antnoise = (int8_t)nf; 3159 tap->wr_tsft = stat->tstamp; 3160 if (rate & IWN_RFLAG_MCS) { 3161 tap->wr_rate = rate & IWN_RFLAG_RATE_MCS; 3162 tap->wr_rate |= IEEE80211_RATE_MCS; 3163 } else 3164 tap->wr_rate = plcp2rate(rate & IWN_RFLAG_RATE); 3165 } 3166 3167 /* 3168 * If it's a beacon and we're waiting, then do the 3169 * wakeup. This should unblock raw_xmit/start. 3170 */ 3171 if (sc->sc_beacon_wait) { 3172 uint8_t type, subtype; 3173 /* NB: Re-assign wh */ 3174 wh = mtod(m, struct ieee80211_frame_min *); 3175 type = wh->i_fc[0] & IEEE80211_FC0_TYPE_MASK; 3176 subtype = wh->i_fc[0] & IEEE80211_FC0_SUBTYPE_MASK; 3177 /* 3178 * This assumes at this point we've received our own 3179 * beacon. 3180 */ 3181 DPRINTF(sc, IWN_DEBUG_TRACE, 3182 "%s: beacon_wait, type=%d, subtype=%d\n", 3183 __func__, type, subtype); 3184 if (type == IEEE80211_FC0_TYPE_MGT && 3185 subtype == IEEE80211_FC0_SUBTYPE_BEACON) { 3186 DPRINTF(sc, IWN_DEBUG_TRACE | IWN_DEBUG_XMIT, 3187 "%s: waking things up\n", __func__); 3188 /* queue taskqueue to transmit! */ 3189 taskqueue_enqueue(sc->sc_tq, &sc->sc_xmit_task); 3190 } 3191 } 3192 3193 IWN_UNLOCK(sc); 3194 NET_EPOCH_ENTER(et); 3195 3196 /* Send the frame to the 802.11 layer. */ 3197 if (ni != NULL) { 3198 if (ni->ni_flags & IEEE80211_NODE_HT) 3199 m->m_flags |= M_AMPDU; 3200 (void)ieee80211_input(ni, m, rssi - nf, nf); 3201 /* Node is no longer needed. */ 3202 ieee80211_free_node(ni); 3203 } else 3204 (void)ieee80211_input_all(ic, m, rssi - nf, nf); 3205 3206 NET_EPOCH_EXIT(et); 3207 IWN_LOCK(sc); 3208 3209 DPRINTF(sc, IWN_DEBUG_TRACE, "->%s: end\n",__func__); 3210 3211 } 3212 3213 static void 3214 iwn_agg_tx_complete(struct iwn_softc *sc, struct iwn_tx_ring *ring, int tid, 3215 int idx, int success) 3216 { 3217 struct ieee80211_ratectl_tx_status *txs = &sc->sc_txs; 3218 struct iwn_tx_data *data = &ring->data[idx]; 3219 struct iwn_node *wn; 3220 struct mbuf *m; 3221 struct ieee80211_node *ni; 3222 3223 KASSERT(data->ni != NULL, ("idx %d: no node", idx)); 3224 KASSERT(data->m != NULL, ("idx %d: no mbuf", idx)); 3225 3226 /* Unmap and free mbuf. */ 3227 bus_dmamap_sync(ring->data_dmat, data->map, 3228 BUS_DMASYNC_POSTWRITE); 3229 bus_dmamap_unload(ring->data_dmat, data->map); 3230 m = data->m, data->m = NULL; 3231 ni = data->ni, data->ni = NULL; 3232 wn = (void *)ni; 3233 3234 #if 0 3235 /* XXX causes significant performance degradation. */ 3236 txs->flags = IEEE80211_RATECTL_STATUS_SHORT_RETRY | 3237 IEEE80211_RATECTL_STATUS_LONG_RETRY; 3238 txs->long_retries = data->long_retries - 1; 3239 #else 3240 txs->flags = IEEE80211_RATECTL_STATUS_SHORT_RETRY; 3241 #endif 3242 txs->short_retries = wn->agg[tid].short_retries; 3243 if (success) 3244 txs->status = IEEE80211_RATECTL_TX_SUCCESS; 3245 else 3246 txs->status = IEEE80211_RATECTL_TX_FAIL_UNSPECIFIED; 3247 3248 wn->agg[tid].short_retries = 0; 3249 data->long_retries = 0; 3250 3251 DPRINTF(sc, IWN_DEBUG_AMPDU, "%s: freeing m %p ni %p idx %d qid %d\n", 3252 __func__, m, ni, idx, ring->qid); 3253 ieee80211_ratectl_tx_complete(ni, txs); 3254 ieee80211_tx_complete(ni, m, !success); 3255 } 3256 3257 /* Process an incoming Compressed BlockAck. */ 3258 static void 3259 iwn_rx_compressed_ba(struct iwn_softc *sc, struct iwn_rx_desc *desc) 3260 { 3261 struct iwn_tx_ring *ring; 3262 struct iwn_tx_data *data; 3263 struct iwn_node *wn; 3264 struct iwn_compressed_ba *ba = (struct iwn_compressed_ba *)(desc + 1); 3265 struct ieee80211_tx_ampdu *tap; 3266 uint64_t bitmap; 3267 uint8_t tid; 3268 int i, qid, shift; 3269 int tx_ok = 0; 3270 3271 DPRINTF(sc, IWN_DEBUG_TRACE, "->%s begin\n", __func__); 3272 3273 qid = le16toh(ba->qid); 3274 tap = sc->qid2tap[qid]; 3275 ring = &sc->txq[qid]; 3276 tid = tap->txa_tid; 3277 wn = (void *)tap->txa_ni; 3278 3279 DPRINTF(sc, IWN_DEBUG_AMPDU, "%s: qid %d tid %d seq %04X ssn %04X\n" 3280 "bitmap: ba %016jX wn %016jX, start %d\n", 3281 __func__, qid, tid, le16toh(ba->seq), le16toh(ba->ssn), 3282 (uintmax_t)le64toh(ba->bitmap), (uintmax_t)wn->agg[tid].bitmap, 3283 wn->agg[tid].startidx); 3284 3285 if (wn->agg[tid].bitmap == 0) 3286 return; 3287 3288 shift = wn->agg[tid].startidx - ((le16toh(ba->seq) >> 4) & 0xff); 3289 if (shift <= -64) 3290 shift += 0x100; 3291 3292 /* 3293 * Walk the bitmap and calculate how many successful attempts 3294 * are made. 3295 * 3296 * Yes, the rate control code doesn't know these are A-MPDU 3297 * subframes; due to that long_retries stats are not used here. 3298 */ 3299 bitmap = le64toh(ba->bitmap); 3300 if (shift >= 0) 3301 bitmap >>= shift; 3302 else 3303 bitmap <<= -shift; 3304 bitmap &= wn->agg[tid].bitmap; 3305 wn->agg[tid].bitmap = 0; 3306 3307 for (i = wn->agg[tid].startidx; 3308 bitmap; 3309 bitmap >>= 1, i = (i + 1) % IWN_TX_RING_COUNT) { 3310 if ((bitmap & 1) == 0) 3311 continue; 3312 3313 data = &ring->data[i]; 3314 if (__predict_false(data->m == NULL)) { 3315 /* 3316 * There is no frame; skip this entry. 3317 * 3318 * NB: it is "ok" to have both 3319 * 'tx done' + 'compressed BA' replies for frame 3320 * with STATE_SCD_QUERY status. 3321 */ 3322 DPRINTF(sc, IWN_DEBUG_AMPDU, 3323 "%s: ring %d: no entry %d\n", __func__, qid, i); 3324 continue; 3325 } 3326 3327 tx_ok++; 3328 iwn_agg_tx_complete(sc, ring, tid, i, 1); 3329 } 3330 3331 ring->queued -= tx_ok; 3332 iwn_check_tx_ring(sc, qid); 3333 3334 DPRINTF(sc, IWN_DEBUG_TRACE | IWN_DEBUG_AMPDU, 3335 "->%s: end; %d ok\n",__func__, tx_ok); 3336 } 3337 3338 /* 3339 * Process a CALIBRATION_RESULT notification sent by the initialization 3340 * firmware on response to a CMD_CALIB_CONFIG command (5000 only). 3341 */ 3342 static void 3343 iwn5000_rx_calib_results(struct iwn_softc *sc, struct iwn_rx_desc *desc) 3344 { 3345 struct iwn_phy_calib *calib = (struct iwn_phy_calib *)(desc + 1); 3346 int len, idx = -1; 3347 3348 DPRINTF(sc, IWN_DEBUG_TRACE, "->%s begin\n", __func__); 3349 3350 /* Runtime firmware should not send such a notification. */ 3351 if (sc->sc_flags & IWN_FLAG_CALIB_DONE){ 3352 DPRINTF(sc, IWN_DEBUG_TRACE, 3353 "->%s received after calib done\n", __func__); 3354 return; 3355 } 3356 len = (le32toh(desc->len) & 0x3fff) - 4; 3357 3358 switch (calib->code) { 3359 case IWN5000_PHY_CALIB_DC: 3360 if (sc->base_params->calib_need & IWN_FLG_NEED_PHY_CALIB_DC) 3361 idx = 0; 3362 break; 3363 case IWN5000_PHY_CALIB_LO: 3364 if (sc->base_params->calib_need & IWN_FLG_NEED_PHY_CALIB_LO) 3365 idx = 1; 3366 break; 3367 case IWN5000_PHY_CALIB_TX_IQ: 3368 if (sc->base_params->calib_need & IWN_FLG_NEED_PHY_CALIB_TX_IQ) 3369 idx = 2; 3370 break; 3371 case IWN5000_PHY_CALIB_TX_IQ_PERIODIC: 3372 if (sc->base_params->calib_need & IWN_FLG_NEED_PHY_CALIB_TX_IQ_PERIODIC) 3373 idx = 3; 3374 break; 3375 case IWN5000_PHY_CALIB_BASE_BAND: 3376 if (sc->base_params->calib_need & IWN_FLG_NEED_PHY_CALIB_BASE_BAND) 3377 idx = 4; 3378 break; 3379 } 3380 if (idx == -1) /* Ignore other results. */ 3381 return; 3382 3383 /* Save calibration result. */ 3384 if (sc->calibcmd[idx].buf != NULL) 3385 free(sc->calibcmd[idx].buf, M_DEVBUF); 3386 sc->calibcmd[idx].buf = malloc(len, M_DEVBUF, M_NOWAIT); 3387 if (sc->calibcmd[idx].buf == NULL) { 3388 DPRINTF(sc, IWN_DEBUG_CALIBRATE, 3389 "not enough memory for calibration result %d\n", 3390 calib->code); 3391 return; 3392 } 3393 DPRINTF(sc, IWN_DEBUG_CALIBRATE, 3394 "saving calibration result idx=%d, code=%d len=%d\n", idx, calib->code, len); 3395 sc->calibcmd[idx].len = len; 3396 memcpy(sc->calibcmd[idx].buf, calib, len); 3397 } 3398 3399 static void 3400 iwn_stats_update(struct iwn_softc *sc, struct iwn_calib_state *calib, 3401 struct iwn_stats *stats, int len) 3402 { 3403 struct iwn_stats_bt *stats_bt; 3404 struct iwn_stats *lstats; 3405 3406 /* 3407 * First - check whether the length is the bluetooth or normal. 3408 * 3409 * If it's normal - just copy it and bump out. 3410 * Otherwise we have to convert things. 3411 */ 3412 3413 if (len == sizeof(struct iwn_stats) + 4) { 3414 memcpy(&sc->last_stat, stats, sizeof(struct iwn_stats)); 3415 sc->last_stat_valid = 1; 3416 return; 3417 } 3418 3419 /* 3420 * If it's not the bluetooth size - log, then just copy. 3421 */ 3422 if (len != sizeof(struct iwn_stats_bt) + 4) { 3423 DPRINTF(sc, IWN_DEBUG_STATS, 3424 "%s: size of rx statistics (%d) not an expected size!\n", 3425 __func__, 3426 len); 3427 memcpy(&sc->last_stat, stats, sizeof(struct iwn_stats)); 3428 sc->last_stat_valid = 1; 3429 return; 3430 } 3431 3432 /* 3433 * Ok. Time to copy. 3434 */ 3435 stats_bt = (struct iwn_stats_bt *) stats; 3436 lstats = &sc->last_stat; 3437 3438 /* flags */ 3439 lstats->flags = stats_bt->flags; 3440 /* rx_bt */ 3441 memcpy(&lstats->rx.ofdm, &stats_bt->rx_bt.ofdm, 3442 sizeof(struct iwn_rx_phy_stats)); 3443 memcpy(&lstats->rx.cck, &stats_bt->rx_bt.cck, 3444 sizeof(struct iwn_rx_phy_stats)); 3445 memcpy(&lstats->rx.general, &stats_bt->rx_bt.general_bt.common, 3446 sizeof(struct iwn_rx_general_stats)); 3447 memcpy(&lstats->rx.ht, &stats_bt->rx_bt.ht, 3448 sizeof(struct iwn_rx_ht_phy_stats)); 3449 /* tx */ 3450 memcpy(&lstats->tx, &stats_bt->tx, 3451 sizeof(struct iwn_tx_stats)); 3452 /* general */ 3453 memcpy(&lstats->general, &stats_bt->general, 3454 sizeof(struct iwn_general_stats)); 3455 3456 /* XXX TODO: Squirrel away the extra bluetooth stats somewhere */ 3457 sc->last_stat_valid = 1; 3458 } 3459 3460 /* 3461 * Process an RX_STATISTICS or BEACON_STATISTICS firmware notification. 3462 * The latter is sent by the firmware after each received beacon. 3463 */ 3464 static void 3465 iwn_rx_statistics(struct iwn_softc *sc, struct iwn_rx_desc *desc) 3466 { 3467 struct iwn_ops *ops = &sc->ops; 3468 struct ieee80211com *ic = &sc->sc_ic; 3469 struct ieee80211vap *vap = TAILQ_FIRST(&ic->ic_vaps); 3470 struct iwn_calib_state *calib = &sc->calib; 3471 struct iwn_stats *stats = (struct iwn_stats *)(desc + 1); 3472 struct iwn_stats *lstats; 3473 int temp; 3474 3475 DPRINTF(sc, IWN_DEBUG_TRACE, "->%s begin\n", __func__); 3476 3477 /* Ignore statistics received during a scan. */ 3478 if (vap->iv_state != IEEE80211_S_RUN || 3479 (ic->ic_flags & IEEE80211_F_SCAN)){ 3480 DPRINTF(sc, IWN_DEBUG_TRACE, "->%s received during calib\n", 3481 __func__); 3482 return; 3483 } 3484 3485 DPRINTF(sc, IWN_DEBUG_CALIBRATE | IWN_DEBUG_STATS, 3486 "%s: received statistics, cmd %d, len %d\n", 3487 __func__, desc->type, le16toh(desc->len)); 3488 sc->calib_cnt = 0; /* Reset TX power calibration timeout. */ 3489 3490 /* 3491 * Collect/track general statistics for reporting. 3492 * 3493 * This takes care of ensuring that the bluetooth sized message 3494 * will be correctly converted to the legacy sized message. 3495 */ 3496 iwn_stats_update(sc, calib, stats, le16toh(desc->len)); 3497 3498 /* 3499 * And now, let's take a reference of it to use! 3500 */ 3501 lstats = &sc->last_stat; 3502 3503 /* Test if temperature has changed. */ 3504 if (lstats->general.temp != sc->rawtemp) { 3505 /* Convert "raw" temperature to degC. */ 3506 sc->rawtemp = stats->general.temp; 3507 temp = ops->get_temperature(sc); 3508 DPRINTF(sc, IWN_DEBUG_CALIBRATE, "%s: temperature %d\n", 3509 __func__, temp); 3510 3511 /* Update TX power if need be (4965AGN only). */ 3512 if (sc->hw_type == IWN_HW_REV_TYPE_4965) 3513 iwn4965_power_calibration(sc, temp); 3514 } 3515 3516 if (desc->type != IWN_BEACON_STATISTICS) 3517 return; /* Reply to a statistics request. */ 3518 3519 sc->noise = iwn_get_noise(&lstats->rx.general); 3520 DPRINTF(sc, IWN_DEBUG_CALIBRATE, "%s: noise %d\n", __func__, sc->noise); 3521 3522 /* Test that RSSI and noise are present in stats report. */ 3523 if (le32toh(lstats->rx.general.flags) != 1) { 3524 DPRINTF(sc, IWN_DEBUG_ANY, "%s\n", 3525 "received statistics without RSSI"); 3526 return; 3527 } 3528 3529 if (calib->state == IWN_CALIB_STATE_ASSOC) 3530 iwn_collect_noise(sc, &lstats->rx.general); 3531 else if (calib->state == IWN_CALIB_STATE_RUN) { 3532 iwn_tune_sensitivity(sc, &lstats->rx); 3533 /* 3534 * XXX TODO: Only run the RX recovery if we're associated! 3535 */ 3536 iwn_check_rx_recovery(sc, lstats); 3537 iwn_save_stats_counters(sc, lstats); 3538 } 3539 3540 DPRINTF(sc, IWN_DEBUG_TRACE, "->%s: end\n",__func__); 3541 } 3542 3543 /* 3544 * Save the relevant statistic counters for the next calibration 3545 * pass. 3546 */ 3547 static void 3548 iwn_save_stats_counters(struct iwn_softc *sc, const struct iwn_stats *rs) 3549 { 3550 struct iwn_calib_state *calib = &sc->calib; 3551 3552 /* Save counters values for next call. */ 3553 calib->bad_plcp_cck = le32toh(rs->rx.cck.bad_plcp); 3554 calib->fa_cck = le32toh(rs->rx.cck.fa); 3555 calib->bad_plcp_ht = le32toh(rs->rx.ht.bad_plcp); 3556 calib->bad_plcp_ofdm = le32toh(rs->rx.ofdm.bad_plcp); 3557 calib->fa_ofdm = le32toh(rs->rx.ofdm.fa); 3558 3559 /* Last time we received these tick values */ 3560 sc->last_calib_ticks = ticks; 3561 } 3562 3563 /* 3564 * Process a TX_DONE firmware notification. Unfortunately, the 4965AGN 3565 * and 5000 adapters have different incompatible TX status formats. 3566 */ 3567 static void 3568 iwn4965_tx_done(struct iwn_softc *sc, struct iwn_rx_desc *desc, 3569 struct iwn_rx_data *data) 3570 { 3571 struct iwn4965_tx_stat *stat = (struct iwn4965_tx_stat *)(desc + 1); 3572 int qid = desc->qid & IWN_RX_DESC_QID_MSK; 3573 3574 DPRINTF(sc, IWN_DEBUG_XMIT, "%s: " 3575 "qid %d idx %d RTS retries %d ACK retries %d nkill %d rate %x duration %d status %x\n", 3576 __func__, desc->qid, desc->idx, 3577 stat->rtsfailcnt, 3578 stat->ackfailcnt, 3579 stat->btkillcnt, 3580 stat->rate, le16toh(stat->duration), 3581 le32toh(stat->status)); 3582 3583 if (qid >= sc->firstaggqueue && stat->nframes != 1) { 3584 iwn_ampdu_tx_done(sc, qid, stat->nframes, stat->rtsfailcnt, 3585 &stat->status); 3586 } else { 3587 iwn_tx_done(sc, desc, stat->rtsfailcnt, stat->ackfailcnt, 3588 le32toh(stat->status) & 0xff); 3589 } 3590 } 3591 3592 static void 3593 iwn5000_tx_done(struct iwn_softc *sc, struct iwn_rx_desc *desc, 3594 struct iwn_rx_data *data) 3595 { 3596 struct iwn5000_tx_stat *stat = (struct iwn5000_tx_stat *)(desc + 1); 3597 int qid = desc->qid & IWN_RX_DESC_QID_MSK; 3598 3599 DPRINTF(sc, IWN_DEBUG_XMIT, "%s: " 3600 "qid %d idx %d RTS retries %d ACK retries %d nkill %d rate %x duration %d status %x\n", 3601 __func__, desc->qid, desc->idx, 3602 stat->rtsfailcnt, 3603 stat->ackfailcnt, 3604 stat->btkillcnt, 3605 stat->rate, le16toh(stat->duration), 3606 le32toh(stat->status)); 3607 3608 #ifdef notyet 3609 /* Reset TX scheduler slot. */ 3610 iwn5000_reset_sched(sc, qid, desc->idx); 3611 #endif 3612 3613 if (qid >= sc->firstaggqueue && stat->nframes != 1) { 3614 iwn_ampdu_tx_done(sc, qid, stat->nframes, stat->rtsfailcnt, 3615 &stat->status); 3616 } else { 3617 iwn_tx_done(sc, desc, stat->rtsfailcnt, stat->ackfailcnt, 3618 le16toh(stat->status) & 0xff); 3619 } 3620 } 3621 3622 static void 3623 iwn_adj_ampdu_ptr(struct iwn_softc *sc, struct iwn_tx_ring *ring) 3624 { 3625 int i; 3626 3627 for (i = ring->read; i != ring->cur; i = (i + 1) % IWN_TX_RING_COUNT) { 3628 struct iwn_tx_data *data = &ring->data[i]; 3629 3630 if (data->m != NULL) 3631 break; 3632 3633 data->remapped = 0; 3634 } 3635 3636 ring->read = i; 3637 } 3638 3639 /* 3640 * Adapter-independent backend for TX_DONE firmware notifications. 3641 */ 3642 static void 3643 iwn_tx_done(struct iwn_softc *sc, struct iwn_rx_desc *desc, int rtsfailcnt, 3644 int ackfailcnt, uint8_t status) 3645 { 3646 struct ieee80211_ratectl_tx_status *txs = &sc->sc_txs; 3647 struct iwn_tx_ring *ring = &sc->txq[desc->qid & IWN_RX_DESC_QID_MSK]; 3648 struct iwn_tx_data *data = &ring->data[desc->idx]; 3649 struct mbuf *m; 3650 struct ieee80211_node *ni; 3651 3652 if (__predict_false(data->m == NULL && 3653 ring->qid >= sc->firstaggqueue)) { 3654 /* 3655 * There is no frame; skip this entry. 3656 */ 3657 DPRINTF(sc, IWN_DEBUG_AMPDU, "%s: ring %d: no entry %d\n", 3658 __func__, ring->qid, desc->idx); 3659 return; 3660 } 3661 3662 KASSERT(data->ni != NULL, ("no node")); 3663 KASSERT(data->m != NULL, ("no mbuf")); 3664 3665 DPRINTF(sc, IWN_DEBUG_TRACE, "->%s begin\n", __func__); 3666 3667 /* Unmap and free mbuf. */ 3668 bus_dmamap_sync(ring->data_dmat, data->map, BUS_DMASYNC_POSTWRITE); 3669 bus_dmamap_unload(ring->data_dmat, data->map); 3670 m = data->m, data->m = NULL; 3671 ni = data->ni, data->ni = NULL; 3672 3673 data->long_retries = 0; 3674 3675 if (ring->qid >= sc->firstaggqueue) 3676 iwn_adj_ampdu_ptr(sc, ring); 3677 3678 /* 3679 * XXX f/w may hang (device timeout) when desc->idx - ring->read == 64 3680 * (aggregation queues only). 3681 */ 3682 3683 ring->queued--; 3684 iwn_check_tx_ring(sc, ring->qid); 3685 3686 /* 3687 * Update rate control statistics for the node. 3688 */ 3689 txs->flags = IEEE80211_RATECTL_STATUS_SHORT_RETRY | 3690 IEEE80211_RATECTL_STATUS_LONG_RETRY; 3691 txs->short_retries = rtsfailcnt; 3692 txs->long_retries = ackfailcnt; 3693 if (!(status & IWN_TX_FAIL)) 3694 txs->status = IEEE80211_RATECTL_TX_SUCCESS; 3695 else { 3696 switch (status) { 3697 case IWN_TX_FAIL_SHORT_LIMIT: 3698 txs->status = IEEE80211_RATECTL_TX_FAIL_SHORT; 3699 break; 3700 case IWN_TX_FAIL_LONG_LIMIT: 3701 txs->status = IEEE80211_RATECTL_TX_FAIL_LONG; 3702 break; 3703 case IWN_TX_STATUS_FAIL_LIFE_EXPIRE: 3704 txs->status = IEEE80211_RATECTL_TX_FAIL_EXPIRED; 3705 break; 3706 default: 3707 txs->status = IEEE80211_RATECTL_TX_FAIL_UNSPECIFIED; 3708 break; 3709 } 3710 } 3711 ieee80211_ratectl_tx_complete(ni, txs); 3712 3713 /* 3714 * Channels marked for "radar" require traffic to be received 3715 * to unlock before we can transmit. Until traffic is seen 3716 * any attempt to transmit is returned immediately with status 3717 * set to IWN_TX_FAIL_TX_LOCKED. Unfortunately this can easily 3718 * happen on first authenticate after scanning. To workaround 3719 * this we ignore a failure of this sort in AUTH state so the 3720 * 802.11 layer will fall back to using a timeout to wait for 3721 * the AUTH reply. This allows the firmware time to see 3722 * traffic so a subsequent retry of AUTH succeeds. It's 3723 * unclear why the firmware does not maintain state for 3724 * channels recently visited as this would allow immediate 3725 * use of the channel after a scan (where we see traffic). 3726 */ 3727 if (status == IWN_TX_FAIL_TX_LOCKED && 3728 ni->ni_vap->iv_state == IEEE80211_S_AUTH) 3729 ieee80211_tx_complete(ni, m, 0); 3730 else 3731 ieee80211_tx_complete(ni, m, 3732 (status & IWN_TX_FAIL) != 0); 3733 3734 DPRINTF(sc, IWN_DEBUG_TRACE, "->%s: end\n",__func__); 3735 } 3736 3737 /* 3738 * Process a "command done" firmware notification. This is where we wakeup 3739 * processes waiting for a synchronous command completion. 3740 */ 3741 static void 3742 iwn_cmd_done(struct iwn_softc *sc, struct iwn_rx_desc *desc) 3743 { 3744 struct iwn_tx_ring *ring; 3745 struct iwn_tx_data *data; 3746 int cmd_queue_num; 3747 3748 if (sc->sc_flags & IWN_FLAG_PAN_SUPPORT) 3749 cmd_queue_num = IWN_PAN_CMD_QUEUE; 3750 else 3751 cmd_queue_num = IWN_CMD_QUEUE_NUM; 3752 3753 if ((desc->qid & IWN_RX_DESC_QID_MSK) != cmd_queue_num) 3754 return; /* Not a command ack. */ 3755 3756 ring = &sc->txq[cmd_queue_num]; 3757 data = &ring->data[desc->idx]; 3758 3759 /* If the command was mapped in an mbuf, free it. */ 3760 if (data->m != NULL) { 3761 bus_dmamap_sync(ring->data_dmat, data->map, 3762 BUS_DMASYNC_POSTWRITE); 3763 bus_dmamap_unload(ring->data_dmat, data->map); 3764 m_freem(data->m); 3765 data->m = NULL; 3766 } 3767 wakeup(&ring->desc[desc->idx]); 3768 } 3769 3770 static int 3771 iwn_ampdu_check_bitmap(uint64_t bitmap, int start, int idx) 3772 { 3773 int bit, shift; 3774 3775 bit = idx - start; 3776 shift = 0; 3777 if (bit >= 64) { 3778 shift = 0x100 - bit; 3779 bit = 0; 3780 } else if (bit <= -64) 3781 bit = 0x100 + bit; 3782 else if (bit < 0) { 3783 shift = -bit; 3784 bit = 0; 3785 } 3786 3787 if (bit - shift >= 64) 3788 return (0); 3789 3790 return ((bitmap & (1ULL << (bit - shift))) != 0); 3791 } 3792 3793 /* 3794 * Firmware bug workaround: in case if 'retries' counter 3795 * overflows 'seqno' field will be incremented: 3796 * status|sequence|status|sequence|status|sequence 3797 * 0000 0A48 0001 0A49 0000 0A6A 3798 * 1000 0A48 1000 0A49 1000 0A6A 3799 * 2000 0A48 2000 0A49 2000 0A6A 3800 * ... 3801 * E000 0A48 E000 0A49 E000 0A6A 3802 * F000 0A48 F000 0A49 F000 0A6A 3803 * 0000 0A49 0000 0A49 0000 0A6B 3804 * 1000 0A49 1000 0A49 1000 0A6B 3805 * ... 3806 * D000 0A49 D000 0A49 D000 0A6B 3807 * E000 0A49 E001 0A49 E000 0A6B 3808 * F000 0A49 F001 0A49 F000 0A6B 3809 * 0000 0A4A 0000 0A4B 0000 0A6A 3810 * 1000 0A4A 1000 0A4B 1000 0A6A 3811 * ... 3812 * 3813 * Odd 'seqno' numbers are incremened by 2 every 2 overflows. 3814 * For even 'seqno' % 4 != 0 overflow is cyclic (0 -> +1 -> 0). 3815 * Not checked with nretries >= 64. 3816 * 3817 */ 3818 static int 3819 iwn_ampdu_index_check(struct iwn_softc *sc, struct iwn_tx_ring *ring, 3820 uint64_t bitmap, int start, int idx) 3821 { 3822 struct ieee80211com *ic = &sc->sc_ic; 3823 struct iwn_tx_data *data; 3824 int diff, min_retries, max_retries, new_idx, loop_end; 3825 3826 new_idx = idx - IWN_LONG_RETRY_LIMIT_LOG; 3827 if (new_idx < 0) 3828 new_idx += IWN_TX_RING_COUNT; 3829 3830 /* 3831 * Corner case: check if retry count is not too big; 3832 * reset device otherwise. 3833 */ 3834 if (!iwn_ampdu_check_bitmap(bitmap, start, new_idx)) { 3835 data = &ring->data[new_idx]; 3836 if (data->long_retries > IWN_LONG_RETRY_LIMIT) { 3837 device_printf(sc->sc_dev, 3838 "%s: retry count (%d) for idx %d/%d overflow, " 3839 "resetting...\n", __func__, data->long_retries, 3840 ring->qid, new_idx); 3841 ieee80211_restart_all(ic); 3842 return (-1); 3843 } 3844 } 3845 3846 /* Correct index if needed. */ 3847 loop_end = idx; 3848 do { 3849 data = &ring->data[new_idx]; 3850 diff = idx - new_idx; 3851 if (diff < 0) 3852 diff += IWN_TX_RING_COUNT; 3853 3854 min_retries = IWN_LONG_RETRY_FW_OVERFLOW * diff; 3855 if ((new_idx % 2) == 0) 3856 max_retries = IWN_LONG_RETRY_FW_OVERFLOW * (diff + 1); 3857 else 3858 max_retries = IWN_LONG_RETRY_FW_OVERFLOW * (diff + 2); 3859 3860 if (!iwn_ampdu_check_bitmap(bitmap, start, new_idx) && 3861 ((data->long_retries >= min_retries && 3862 data->long_retries < max_retries) || 3863 (diff == 1 && 3864 (new_idx & 0x03) == 0x02 && 3865 data->long_retries >= IWN_LONG_RETRY_FW_OVERFLOW))) { 3866 DPRINTF(sc, IWN_DEBUG_AMPDU, 3867 "%s: correcting index %d -> %d in queue %d" 3868 " (retries %d)\n", __func__, idx, new_idx, 3869 ring->qid, data->long_retries); 3870 return (new_idx); 3871 } 3872 3873 new_idx = (new_idx + 1) % IWN_TX_RING_COUNT; 3874 } while (new_idx != loop_end); 3875 3876 return (idx); 3877 } 3878 3879 static void 3880 iwn_ampdu_tx_done(struct iwn_softc *sc, int qid, int nframes, int rtsfailcnt, 3881 void *stat) 3882 { 3883 struct iwn_tx_ring *ring = &sc->txq[qid]; 3884 struct ieee80211_tx_ampdu *tap = sc->qid2tap[qid]; 3885 struct iwn_node *wn = (void *)tap->txa_ni; 3886 struct iwn_tx_data *data; 3887 uint64_t bitmap = 0; 3888 uint16_t *aggstatus = stat; 3889 uint8_t tid = tap->txa_tid; 3890 int bit, i, idx, shift, start, tx_err; 3891 3892 DPRINTF(sc, IWN_DEBUG_TRACE, "->%s begin\n", __func__); 3893 3894 start = le16toh(*(aggstatus + nframes * 2)) & 0xff; 3895 3896 for (i = 0; i < nframes; i++) { 3897 uint16_t status = le16toh(aggstatus[i * 2]); 3898 3899 if (status & IWN_AGG_TX_STATE_IGNORE_MASK) 3900 continue; 3901 3902 idx = le16toh(aggstatus[i * 2 + 1]) & 0xff; 3903 data = &ring->data[idx]; 3904 if (data->remapped) { 3905 idx = iwn_ampdu_index_check(sc, ring, bitmap, start, idx); 3906 if (idx == -1) { 3907 /* skip error (device will be restarted anyway). */ 3908 continue; 3909 } 3910 3911 /* Index may have changed. */ 3912 data = &ring->data[idx]; 3913 } 3914 3915 /* 3916 * XXX Sometimes (rarely) some frames are excluded from events. 3917 * XXX Due to that long_retries counter may be wrong. 3918 */ 3919 data->long_retries &= ~0x0f; 3920 data->long_retries += IWN_AGG_TX_TRY_COUNT(status) + 1; 3921 3922 if (data->long_retries >= IWN_LONG_RETRY_FW_OVERFLOW) { 3923 int diff, wrong_idx; 3924 3925 diff = data->long_retries / IWN_LONG_RETRY_FW_OVERFLOW; 3926 wrong_idx = (idx + diff) % IWN_TX_RING_COUNT; 3927 3928 /* 3929 * Mark the entry so the above code will check it 3930 * next time. 3931 */ 3932 ring->data[wrong_idx].remapped = 1; 3933 } 3934 3935 if (status & IWN_AGG_TX_STATE_UNDERRUN_MSK) { 3936 /* 3937 * NB: count retries but postpone - it was not 3938 * transmitted. 3939 */ 3940 continue; 3941 } 3942 3943 bit = idx - start; 3944 shift = 0; 3945 if (bit >= 64) { 3946 shift = 0x100 - bit; 3947 bit = 0; 3948 } else if (bit <= -64) 3949 bit = 0x100 + bit; 3950 else if (bit < 0) { 3951 shift = -bit; 3952 bit = 0; 3953 } 3954 bitmap = bitmap << shift; 3955 bitmap |= 1ULL << bit; 3956 } 3957 wn->agg[tid].startidx = start; 3958 wn->agg[tid].bitmap = bitmap; 3959 wn->agg[tid].short_retries = rtsfailcnt; 3960 3961 DPRINTF(sc, IWN_DEBUG_AMPDU, "%s: nframes %d start %d bitmap %016jX\n", 3962 __func__, nframes, start, (uintmax_t)bitmap); 3963 3964 i = ring->read; 3965 3966 for (tx_err = 0; 3967 i != wn->agg[tid].startidx; 3968 i = (i + 1) % IWN_TX_RING_COUNT) { 3969 data = &ring->data[i]; 3970 data->remapped = 0; 3971 if (data->m == NULL) 3972 continue; 3973 3974 tx_err++; 3975 iwn_agg_tx_complete(sc, ring, tid, i, 0); 3976 } 3977 3978 ring->read = wn->agg[tid].startidx; 3979 ring->queued -= tx_err; 3980 3981 iwn_check_tx_ring(sc, qid); 3982 3983 DPRINTF(sc, IWN_DEBUG_TRACE, "->%s: end\n",__func__); 3984 } 3985 3986 /* 3987 * Process an INT_FH_RX or INT_SW_RX interrupt. 3988 */ 3989 static void 3990 iwn_notif_intr(struct iwn_softc *sc) 3991 { 3992 struct iwn_ops *ops = &sc->ops; 3993 struct ieee80211com *ic = &sc->sc_ic; 3994 struct ieee80211vap *vap = TAILQ_FIRST(&ic->ic_vaps); 3995 uint16_t hw; 3996 int is_stopped; 3997 3998 bus_dmamap_sync(sc->rxq.stat_dma.tag, sc->rxq.stat_dma.map, 3999 BUS_DMASYNC_POSTREAD); 4000 4001 hw = le16toh(sc->rxq.stat->closed_count) & 0xfff; 4002 while (sc->rxq.cur != hw) { 4003 struct iwn_rx_data *data = &sc->rxq.data[sc->rxq.cur]; 4004 struct iwn_rx_desc *desc; 4005 4006 bus_dmamap_sync(sc->rxq.data_dmat, data->map, 4007 BUS_DMASYNC_POSTREAD); 4008 desc = mtod(data->m, struct iwn_rx_desc *); 4009 4010 DPRINTF(sc, IWN_DEBUG_RECV, 4011 "%s: cur=%d; qid %x idx %d flags %x type %d(%s) len %d\n", 4012 __func__, sc->rxq.cur, desc->qid & IWN_RX_DESC_QID_MSK, 4013 desc->idx, desc->flags, desc->type, 4014 iwn_intr_str(desc->type), le16toh(desc->len)); 4015 4016 if (!(desc->qid & IWN_UNSOLICITED_RX_NOTIF)) /* Reply to a command. */ 4017 iwn_cmd_done(sc, desc); 4018 4019 switch (desc->type) { 4020 case IWN_RX_PHY: 4021 iwn_rx_phy(sc, desc); 4022 break; 4023 4024 case IWN_RX_DONE: /* 4965AGN only. */ 4025 case IWN_MPDU_RX_DONE: 4026 /* An 802.11 frame has been received. */ 4027 iwn_rx_done(sc, desc, data); 4028 4029 is_stopped = (sc->sc_flags & IWN_FLAG_RUNNING) == 0; 4030 if (__predict_false(is_stopped)) 4031 return; 4032 4033 break; 4034 4035 case IWN_RX_COMPRESSED_BA: 4036 /* A Compressed BlockAck has been received. */ 4037 iwn_rx_compressed_ba(sc, desc); 4038 break; 4039 4040 case IWN_TX_DONE: 4041 /* An 802.11 frame has been transmitted. */ 4042 ops->tx_done(sc, desc, data); 4043 break; 4044 4045 case IWN_RX_STATISTICS: 4046 case IWN_BEACON_STATISTICS: 4047 iwn_rx_statistics(sc, desc); 4048 break; 4049 4050 case IWN_BEACON_MISSED: 4051 { 4052 struct iwn_beacon_missed *miss = 4053 (struct iwn_beacon_missed *)(desc + 1); 4054 int misses; 4055 4056 misses = le32toh(miss->consecutive); 4057 4058 DPRINTF(sc, IWN_DEBUG_STATE, 4059 "%s: beacons missed %d/%d\n", __func__, 4060 misses, le32toh(miss->total)); 4061 /* 4062 * If more than 5 consecutive beacons are missed, 4063 * reinitialize the sensitivity state machine. 4064 */ 4065 if (vap->iv_state == IEEE80211_S_RUN && 4066 (ic->ic_flags & IEEE80211_F_SCAN) == 0) { 4067 if (misses > 5) 4068 (void)iwn_init_sensitivity(sc); 4069 if (misses >= vap->iv_bmissthreshold) { 4070 IWN_UNLOCK(sc); 4071 ieee80211_beacon_miss(ic); 4072 IWN_LOCK(sc); 4073 4074 is_stopped = (sc->sc_flags & 4075 IWN_FLAG_RUNNING) == 0; 4076 if (__predict_false(is_stopped)) 4077 return; 4078 } 4079 } 4080 break; 4081 } 4082 case IWN_UC_READY: 4083 { 4084 struct iwn_ucode_info *uc = 4085 (struct iwn_ucode_info *)(desc + 1); 4086 4087 /* The microcontroller is ready. */ 4088 DPRINTF(sc, IWN_DEBUG_RESET, 4089 "microcode alive notification version=%d.%d " 4090 "subtype=%x alive=%x\n", uc->major, uc->minor, 4091 uc->subtype, le32toh(uc->valid)); 4092 4093 if (le32toh(uc->valid) != 1) { 4094 device_printf(sc->sc_dev, 4095 "microcontroller initialization failed"); 4096 break; 4097 } 4098 if (uc->subtype == IWN_UCODE_INIT) { 4099 /* Save microcontroller report. */ 4100 memcpy(&sc->ucode_info, uc, sizeof (*uc)); 4101 } 4102 /* Save the address of the error log in SRAM. */ 4103 sc->errptr = le32toh(uc->errptr); 4104 break; 4105 } 4106 #ifdef IWN_DEBUG 4107 case IWN_STATE_CHANGED: 4108 { 4109 /* 4110 * State change allows hardware switch change to be 4111 * noted. However, we handle this in iwn_intr as we 4112 * get both the enable/disble intr. 4113 */ 4114 uint32_t *status = (uint32_t *)(desc + 1); 4115 DPRINTF(sc, IWN_DEBUG_INTR | IWN_DEBUG_STATE, 4116 "state changed to %x\n", 4117 le32toh(*status)); 4118 break; 4119 } 4120 case IWN_START_SCAN: 4121 { 4122 struct iwn_start_scan *scan = 4123 (struct iwn_start_scan *)(desc + 1); 4124 DPRINTF(sc, IWN_DEBUG_ANY, 4125 "%s: scanning channel %d status %x\n", 4126 __func__, scan->chan, le32toh(scan->status)); 4127 break; 4128 } 4129 #endif 4130 case IWN_STOP_SCAN: 4131 { 4132 #ifdef IWN_DEBUG 4133 struct iwn_stop_scan *scan = 4134 (struct iwn_stop_scan *)(desc + 1); 4135 DPRINTF(sc, IWN_DEBUG_STATE | IWN_DEBUG_SCAN, 4136 "scan finished nchan=%d status=%d chan=%d\n", 4137 scan->nchan, scan->status, scan->chan); 4138 #endif 4139 sc->sc_is_scanning = 0; 4140 callout_stop(&sc->scan_timeout); 4141 IWN_UNLOCK(sc); 4142 ieee80211_scan_next(vap); 4143 IWN_LOCK(sc); 4144 4145 is_stopped = (sc->sc_flags & IWN_FLAG_RUNNING) == 0; 4146 if (__predict_false(is_stopped)) 4147 return; 4148 4149 break; 4150 } 4151 case IWN5000_CALIBRATION_RESULT: 4152 iwn5000_rx_calib_results(sc, desc); 4153 break; 4154 4155 case IWN5000_CALIBRATION_DONE: 4156 sc->sc_flags |= IWN_FLAG_CALIB_DONE; 4157 wakeup(sc); 4158 break; 4159 } 4160 4161 sc->rxq.cur = (sc->rxq.cur + 1) % IWN_RX_RING_COUNT; 4162 } 4163 4164 /* Tell the firmware what we have processed. */ 4165 hw = (hw == 0) ? IWN_RX_RING_COUNT - 1 : hw - 1; 4166 IWN_WRITE(sc, IWN_FH_RX_WPTR, hw & ~7); 4167 } 4168 4169 /* 4170 * Process an INT_WAKEUP interrupt raised when the microcontroller wakes up 4171 * from power-down sleep mode. 4172 */ 4173 static void 4174 iwn_wakeup_intr(struct iwn_softc *sc) 4175 { 4176 int qid; 4177 4178 DPRINTF(sc, IWN_DEBUG_RESET, "%s: ucode wakeup from power-down sleep\n", 4179 __func__); 4180 4181 /* Wakeup RX and TX rings. */ 4182 IWN_WRITE(sc, IWN_FH_RX_WPTR, sc->rxq.cur & ~7); 4183 for (qid = 0; qid < sc->ntxqs; qid++) { 4184 struct iwn_tx_ring *ring = &sc->txq[qid]; 4185 IWN_WRITE(sc, IWN_HBUS_TARG_WRPTR, qid << 8 | ring->cur); 4186 } 4187 } 4188 4189 static void 4190 iwn_rftoggle_task(void *arg, int npending) 4191 { 4192 struct iwn_softc *sc = arg; 4193 struct ieee80211com *ic = &sc->sc_ic; 4194 uint32_t tmp; 4195 4196 IWN_LOCK(sc); 4197 tmp = IWN_READ(sc, IWN_GP_CNTRL); 4198 IWN_UNLOCK(sc); 4199 4200 device_printf(sc->sc_dev, "RF switch: radio %s\n", 4201 (tmp & IWN_GP_CNTRL_RFKILL) ? "enabled" : "disabled"); 4202 if (!(tmp & IWN_GP_CNTRL_RFKILL)) { 4203 ieee80211_suspend_all(ic); 4204 4205 /* Enable interrupts to get RF toggle notification. */ 4206 IWN_LOCK(sc); 4207 IWN_WRITE(sc, IWN_INT, 0xffffffff); 4208 IWN_WRITE(sc, IWN_INT_MASK, sc->int_mask); 4209 IWN_UNLOCK(sc); 4210 } else 4211 ieee80211_resume_all(ic); 4212 } 4213 4214 /* 4215 * Dump the error log of the firmware when a firmware panic occurs. Although 4216 * we can't debug the firmware because it is neither open source nor free, it 4217 * can help us to identify certain classes of problems. 4218 */ 4219 static void 4220 iwn_fatal_intr(struct iwn_softc *sc) 4221 { 4222 struct iwn_fw_dump dump; 4223 int i; 4224 4225 IWN_LOCK_ASSERT(sc); 4226 4227 /* Force a complete recalibration on next init. */ 4228 sc->sc_flags &= ~IWN_FLAG_CALIB_DONE; 4229 4230 /* Check that the error log address is valid. */ 4231 if (sc->errptr < IWN_FW_DATA_BASE || 4232 sc->errptr + sizeof (dump) > 4233 IWN_FW_DATA_BASE + sc->fw_data_maxsz) { 4234 printf("%s: bad firmware error log address 0x%08x\n", __func__, 4235 sc->errptr); 4236 return; 4237 } 4238 if (iwn_nic_lock(sc) != 0) { 4239 printf("%s: could not read firmware error log\n", __func__); 4240 return; 4241 } 4242 /* Read firmware error log from SRAM. */ 4243 iwn_mem_read_region_4(sc, sc->errptr, (uint32_t *)&dump, 4244 sizeof (dump) / sizeof (uint32_t)); 4245 iwn_nic_unlock(sc); 4246 4247 if (dump.valid == 0) { 4248 printf("%s: firmware error log is empty\n", __func__); 4249 return; 4250 } 4251 printf("firmware error log:\n"); 4252 printf(" error type = \"%s\" (0x%08X)\n", 4253 (dump.id < nitems(iwn_fw_errmsg)) ? 4254 iwn_fw_errmsg[dump.id] : "UNKNOWN", 4255 dump.id); 4256 printf(" program counter = 0x%08X\n", dump.pc); 4257 printf(" source line = 0x%08X\n", dump.src_line); 4258 printf(" error data = 0x%08X%08X\n", 4259 dump.error_data[0], dump.error_data[1]); 4260 printf(" branch link = 0x%08X%08X\n", 4261 dump.branch_link[0], dump.branch_link[1]); 4262 printf(" interrupt link = 0x%08X%08X\n", 4263 dump.interrupt_link[0], dump.interrupt_link[1]); 4264 printf(" time = %u\n", dump.time[0]); 4265 4266 /* Dump driver status (TX and RX rings) while we're here. */ 4267 printf("driver status:\n"); 4268 for (i = 0; i < sc->ntxqs; i++) { 4269 struct iwn_tx_ring *ring = &sc->txq[i]; 4270 printf(" tx ring %2d: qid=%-2d cur=%-3d queued=%-3d\n", 4271 i, ring->qid, ring->cur, ring->queued); 4272 } 4273 printf(" rx ring: cur=%d\n", sc->rxq.cur); 4274 } 4275 4276 static void 4277 iwn_intr(void *arg) 4278 { 4279 struct iwn_softc *sc = arg; 4280 uint32_t r1, r2, tmp; 4281 4282 IWN_LOCK(sc); 4283 4284 /* Disable interrupts. */ 4285 IWN_WRITE(sc, IWN_INT_MASK, 0); 4286 4287 /* Read interrupts from ICT (fast) or from registers (slow). */ 4288 if (sc->sc_flags & IWN_FLAG_USE_ICT) { 4289 bus_dmamap_sync(sc->ict_dma.tag, sc->ict_dma.map, 4290 BUS_DMASYNC_POSTREAD); 4291 tmp = 0; 4292 while (sc->ict[sc->ict_cur] != 0) { 4293 tmp |= sc->ict[sc->ict_cur]; 4294 sc->ict[sc->ict_cur] = 0; /* Acknowledge. */ 4295 sc->ict_cur = (sc->ict_cur + 1) % IWN_ICT_COUNT; 4296 } 4297 tmp = le32toh(tmp); 4298 if (tmp == 0xffffffff) /* Shouldn't happen. */ 4299 tmp = 0; 4300 else if (tmp & 0xc0000) /* Workaround a HW bug. */ 4301 tmp |= 0x8000; 4302 r1 = (tmp & 0xff00) << 16 | (tmp & 0xff); 4303 r2 = 0; /* Unused. */ 4304 } else { 4305 r1 = IWN_READ(sc, IWN_INT); 4306 if (r1 == 0xffffffff || (r1 & 0xfffffff0) == 0xa5a5a5a0) { 4307 IWN_UNLOCK(sc); 4308 return; /* Hardware gone! */ 4309 } 4310 r2 = IWN_READ(sc, IWN_FH_INT); 4311 } 4312 4313 DPRINTF(sc, IWN_DEBUG_INTR, "interrupt reg1=0x%08x reg2=0x%08x\n" 4314 , r1, r2); 4315 4316 if (r1 == 0 && r2 == 0) 4317 goto done; /* Interrupt not for us. */ 4318 4319 /* Acknowledge interrupts. */ 4320 IWN_WRITE(sc, IWN_INT, r1); 4321 if (!(sc->sc_flags & IWN_FLAG_USE_ICT)) 4322 IWN_WRITE(sc, IWN_FH_INT, r2); 4323 4324 if (r1 & IWN_INT_RF_TOGGLED) { 4325 taskqueue_enqueue(sc->sc_tq, &sc->sc_rftoggle_task); 4326 goto done; 4327 } 4328 if (r1 & IWN_INT_CT_REACHED) { 4329 device_printf(sc->sc_dev, "%s: critical temperature reached!\n", 4330 __func__); 4331 } 4332 if (r1 & (IWN_INT_SW_ERR | IWN_INT_HW_ERR)) { 4333 device_printf(sc->sc_dev, "%s: fatal firmware error\n", 4334 __func__); 4335 #ifdef IWN_DEBUG 4336 iwn_debug_register(sc); 4337 #endif 4338 /* Dump firmware error log and stop. */ 4339 iwn_fatal_intr(sc); 4340 4341 taskqueue_enqueue(sc->sc_tq, &sc->sc_panic_task); 4342 goto done; 4343 } 4344 if ((r1 & (IWN_INT_FH_RX | IWN_INT_SW_RX | IWN_INT_RX_PERIODIC)) || 4345 (r2 & IWN_FH_INT_RX)) { 4346 if (sc->sc_flags & IWN_FLAG_USE_ICT) { 4347 if (r1 & (IWN_INT_FH_RX | IWN_INT_SW_RX)) 4348 IWN_WRITE(sc, IWN_FH_INT, IWN_FH_INT_RX); 4349 IWN_WRITE_1(sc, IWN_INT_PERIODIC, 4350 IWN_INT_PERIODIC_DIS); 4351 iwn_notif_intr(sc); 4352 if (r1 & (IWN_INT_FH_RX | IWN_INT_SW_RX)) { 4353 IWN_WRITE_1(sc, IWN_INT_PERIODIC, 4354 IWN_INT_PERIODIC_ENA); 4355 } 4356 } else 4357 iwn_notif_intr(sc); 4358 } 4359 4360 if ((r1 & IWN_INT_FH_TX) || (r2 & IWN_FH_INT_TX)) { 4361 if (sc->sc_flags & IWN_FLAG_USE_ICT) 4362 IWN_WRITE(sc, IWN_FH_INT, IWN_FH_INT_TX); 4363 wakeup(sc); /* FH DMA transfer completed. */ 4364 } 4365 4366 if (r1 & IWN_INT_ALIVE) 4367 wakeup(sc); /* Firmware is alive. */ 4368 4369 if (r1 & IWN_INT_WAKEUP) 4370 iwn_wakeup_intr(sc); 4371 4372 done: 4373 /* Re-enable interrupts. */ 4374 if (sc->sc_flags & IWN_FLAG_RUNNING) 4375 IWN_WRITE(sc, IWN_INT_MASK, sc->int_mask); 4376 4377 IWN_UNLOCK(sc); 4378 } 4379 4380 /* 4381 * Update TX scheduler ring when transmitting an 802.11 frame (4965AGN and 4382 * 5000 adapters use a slightly different format). 4383 */ 4384 static void 4385 iwn4965_update_sched(struct iwn_softc *sc, int qid, int idx, uint8_t id, 4386 uint16_t len) 4387 { 4388 uint16_t *w = &sc->sched[qid * IWN4965_SCHED_COUNT + idx]; 4389 4390 DPRINTF(sc, IWN_DEBUG_TRACE, "->Doing %s\n", __func__); 4391 4392 *w = htole16(len + 8); 4393 bus_dmamap_sync(sc->sched_dma.tag, sc->sched_dma.map, 4394 BUS_DMASYNC_PREWRITE); 4395 if (idx < IWN_SCHED_WINSZ) { 4396 *(w + IWN_TX_RING_COUNT) = *w; 4397 bus_dmamap_sync(sc->sched_dma.tag, sc->sched_dma.map, 4398 BUS_DMASYNC_PREWRITE); 4399 } 4400 } 4401 4402 static void 4403 iwn5000_update_sched(struct iwn_softc *sc, int qid, int idx, uint8_t id, 4404 uint16_t len) 4405 { 4406 uint16_t *w = &sc->sched[qid * IWN5000_SCHED_COUNT + idx]; 4407 4408 DPRINTF(sc, IWN_DEBUG_TRACE, "->Doing %s\n", __func__); 4409 4410 *w = htole16(id << 12 | (len + 8)); 4411 bus_dmamap_sync(sc->sched_dma.tag, sc->sched_dma.map, 4412 BUS_DMASYNC_PREWRITE); 4413 if (idx < IWN_SCHED_WINSZ) { 4414 *(w + IWN_TX_RING_COUNT) = *w; 4415 bus_dmamap_sync(sc->sched_dma.tag, sc->sched_dma.map, 4416 BUS_DMASYNC_PREWRITE); 4417 } 4418 } 4419 4420 #ifdef notyet 4421 static void 4422 iwn5000_reset_sched(struct iwn_softc *sc, int qid, int idx) 4423 { 4424 uint16_t *w = &sc->sched[qid * IWN5000_SCHED_COUNT + idx]; 4425 4426 DPRINTF(sc, IWN_DEBUG_TRACE, "->Doing %s\n", __func__); 4427 4428 *w = (*w & htole16(0xf000)) | htole16(1); 4429 bus_dmamap_sync(sc->sched_dma.tag, sc->sched_dma.map, 4430 BUS_DMASYNC_PREWRITE); 4431 if (idx < IWN_SCHED_WINSZ) { 4432 *(w + IWN_TX_RING_COUNT) = *w; 4433 bus_dmamap_sync(sc->sched_dma.tag, sc->sched_dma.map, 4434 BUS_DMASYNC_PREWRITE); 4435 } 4436 } 4437 #endif 4438 4439 /* 4440 * Check whether OFDM 11g protection will be enabled for the given rate. 4441 * 4442 * The original driver code only enabled protection for OFDM rates. 4443 * It didn't check to see whether it was operating in 11a or 11bg mode. 4444 */ 4445 static int 4446 iwn_check_rate_needs_protection(struct iwn_softc *sc, 4447 struct ieee80211vap *vap, uint8_t rate) 4448 { 4449 struct ieee80211com *ic = vap->iv_ic; 4450 4451 /* 4452 * Not in 2GHz mode? Then there's no need to enable OFDM 4453 * 11bg protection. 4454 */ 4455 if (! IEEE80211_IS_CHAN_2GHZ(ic->ic_curchan)) { 4456 return (0); 4457 } 4458 4459 /* 4460 * 11bg protection not enabled? Then don't use it. 4461 */ 4462 if ((ic->ic_flags & IEEE80211_F_USEPROT) == 0) 4463 return (0); 4464 4465 /* 4466 * If it's an 11n rate - no protection. 4467 * We'll do it via a specific 11n check. 4468 */ 4469 if (rate & IEEE80211_RATE_MCS) { 4470 return (0); 4471 } 4472 4473 /* 4474 * Do a rate table lookup. If the PHY is CCK, 4475 * don't do protection. 4476 */ 4477 if (ieee80211_rate2phytype(ic->ic_rt, rate) == IEEE80211_T_CCK) 4478 return (0); 4479 4480 /* 4481 * Yup, enable protection. 4482 */ 4483 return (1); 4484 } 4485 4486 /* 4487 * return a value between 0 and IWN_MAX_TX_RETRIES-1 as an index into 4488 * the link quality table that reflects this particular entry. 4489 */ 4490 static int 4491 iwn_tx_rate_to_linkq_offset(struct iwn_softc *sc, struct ieee80211_node *ni, 4492 uint8_t rate) 4493 { 4494 struct ieee80211_rateset *rs; 4495 int is_11n; 4496 int nr; 4497 int i; 4498 uint8_t cmp_rate; 4499 4500 /* 4501 * Figure out if we're using 11n or not here. 4502 */ 4503 if (IEEE80211_IS_CHAN_HT(ni->ni_chan) && ni->ni_htrates.rs_nrates > 0) 4504 is_11n = 1; 4505 else 4506 is_11n = 0; 4507 4508 /* 4509 * Use the correct rate table. 4510 */ 4511 if (is_11n) { 4512 rs = (struct ieee80211_rateset *) &ni->ni_htrates; 4513 nr = ni->ni_htrates.rs_nrates; 4514 } else { 4515 rs = &ni->ni_rates; 4516 nr = rs->rs_nrates; 4517 } 4518 4519 /* 4520 * Find the relevant link quality entry in the table. 4521 */ 4522 for (i = 0; i < nr && i < IWN_MAX_TX_RETRIES - 1 ; i++) { 4523 /* 4524 * The link quality table index starts at 0 == highest 4525 * rate, so we walk the rate table backwards. 4526 */ 4527 cmp_rate = rs->rs_rates[(nr - 1) - i]; 4528 if (rate & IEEE80211_RATE_MCS) 4529 cmp_rate |= IEEE80211_RATE_MCS; 4530 4531 #if 0 4532 DPRINTF(sc, IWN_DEBUG_XMIT, "%s: idx %d: nr=%d, rate=0x%02x, rateentry=0x%02x\n", 4533 __func__, 4534 i, 4535 nr, 4536 rate, 4537 cmp_rate); 4538 #endif 4539 4540 if (cmp_rate == rate) 4541 return (i); 4542 } 4543 4544 /* Failed? Start at the end */ 4545 return (IWN_MAX_TX_RETRIES - 1); 4546 } 4547 4548 static int 4549 iwn_tx_data(struct iwn_softc *sc, struct mbuf *m, struct ieee80211_node *ni) 4550 { 4551 const struct ieee80211_txparam *tp = ni->ni_txparms; 4552 struct ieee80211vap *vap = ni->ni_vap; 4553 struct ieee80211com *ic = ni->ni_ic; 4554 struct iwn_node *wn = (void *)ni; 4555 struct iwn_tx_ring *ring; 4556 struct iwn_tx_cmd *cmd; 4557 struct iwn_cmd_data *tx; 4558 struct ieee80211_frame *wh; 4559 struct ieee80211_key *k = NULL; 4560 uint32_t flags; 4561 uint16_t qos; 4562 uint8_t tid, type; 4563 int ac, totlen, rate; 4564 4565 DPRINTF(sc, IWN_DEBUG_TRACE, "->%s begin\n", __func__); 4566 4567 IWN_LOCK_ASSERT(sc); 4568 4569 wh = mtod(m, struct ieee80211_frame *); 4570 type = wh->i_fc[0] & IEEE80211_FC0_TYPE_MASK; 4571 4572 /* Select EDCA Access Category and TX ring for this frame. */ 4573 if (IEEE80211_QOS_HAS_SEQ(wh)) { 4574 qos = ((const struct ieee80211_qosframe *)wh)->i_qos[0]; 4575 tid = qos & IEEE80211_QOS_TID; 4576 } else { 4577 qos = 0; 4578 tid = 0; 4579 } 4580 4581 /* Choose a TX rate index. */ 4582 if (type == IEEE80211_FC0_TYPE_MGT || 4583 type == IEEE80211_FC0_TYPE_CTL || 4584 (m->m_flags & M_EAPOL) != 0) 4585 rate = tp->mgmtrate; 4586 else if (IEEE80211_IS_MULTICAST(wh->i_addr1)) 4587 rate = tp->mcastrate; 4588 else if (tp->ucastrate != IEEE80211_FIXED_RATE_NONE) 4589 rate = tp->ucastrate; 4590 else { 4591 /* XXX pass pktlen */ 4592 (void) ieee80211_ratectl_rate(ni, NULL, 0); 4593 rate = ni->ni_txrate; 4594 } 4595 4596 /* 4597 * XXX TODO: Group addressed frames aren't aggregated and must 4598 * go to the normal non-aggregation queue, and have a NONQOS TID 4599 * assigned from net80211. 4600 */ 4601 4602 ac = M_WME_GETAC(m); 4603 if (m->m_flags & M_AMPDU_MPDU) { 4604 struct ieee80211_tx_ampdu *tap = &ni->ni_tx_ampdu[ac]; 4605 4606 if (!IEEE80211_AMPDU_RUNNING(tap)) 4607 return (EINVAL); 4608 4609 ac = *(int *)tap->txa_private; 4610 } 4611 4612 /* Encrypt the frame if need be. */ 4613 if (wh->i_fc[1] & IEEE80211_FC1_PROTECTED) { 4614 /* Retrieve key for TX. */ 4615 k = ieee80211_crypto_encap(ni, m); 4616 if (k == NULL) { 4617 return ENOBUFS; 4618 } 4619 /* 802.11 header may have moved. */ 4620 wh = mtod(m, struct ieee80211_frame *); 4621 } 4622 totlen = m->m_pkthdr.len; 4623 4624 if (ieee80211_radiotap_active_vap(vap)) { 4625 struct iwn_tx_radiotap_header *tap = &sc->sc_txtap; 4626 4627 tap->wt_flags = 0; 4628 tap->wt_rate = rate; 4629 if (k != NULL) 4630 tap->wt_flags |= IEEE80211_RADIOTAP_F_WEP; 4631 4632 ieee80211_radiotap_tx(vap, m); 4633 } 4634 4635 flags = 0; 4636 if (!IEEE80211_IS_MULTICAST(wh->i_addr1)) { 4637 /* Unicast frame, check if an ACK is expected. */ 4638 if (!qos || (qos & IEEE80211_QOS_ACKPOLICY) != 4639 IEEE80211_QOS_ACKPOLICY_NOACK) 4640 flags |= IWN_TX_NEED_ACK; 4641 } 4642 if ((wh->i_fc[0] & 4643 (IEEE80211_FC0_TYPE_MASK | IEEE80211_FC0_SUBTYPE_MASK)) == 4644 (IEEE80211_FC0_TYPE_CTL | IEEE80211_FC0_SUBTYPE_BAR)) 4645 flags |= IWN_TX_IMM_BA; /* Cannot happen yet. */ 4646 4647 if (wh->i_fc[1] & IEEE80211_FC1_MORE_FRAG) 4648 flags |= IWN_TX_MORE_FRAG; /* Cannot happen yet. */ 4649 4650 /* Check if frame must be protected using RTS/CTS or CTS-to-self. */ 4651 if (!IEEE80211_IS_MULTICAST(wh->i_addr1)) { 4652 /* NB: Group frames are sent using CCK in 802.11b/g. */ 4653 if (totlen + IEEE80211_CRC_LEN > vap->iv_rtsthreshold) { 4654 flags |= IWN_TX_NEED_RTS; 4655 } else if (iwn_check_rate_needs_protection(sc, vap, rate)) { 4656 if (ic->ic_protmode == IEEE80211_PROT_CTSONLY) 4657 flags |= IWN_TX_NEED_CTS; 4658 else if (ic->ic_protmode == IEEE80211_PROT_RTSCTS) 4659 flags |= IWN_TX_NEED_RTS; 4660 } else if ((rate & IEEE80211_RATE_MCS) && 4661 (ic->ic_htprotmode == IEEE80211_PROT_RTSCTS)) { 4662 flags |= IWN_TX_NEED_RTS; 4663 } 4664 4665 /* XXX HT protection? */ 4666 4667 if (flags & (IWN_TX_NEED_RTS | IWN_TX_NEED_CTS)) { 4668 if (sc->hw_type != IWN_HW_REV_TYPE_4965) { 4669 /* 5000 autoselects RTS/CTS or CTS-to-self. */ 4670 flags &= ~(IWN_TX_NEED_RTS | IWN_TX_NEED_CTS); 4671 flags |= IWN_TX_NEED_PROTECTION; 4672 } else 4673 flags |= IWN_TX_FULL_TXOP; 4674 } 4675 } 4676 4677 ring = &sc->txq[ac]; 4678 if (m->m_flags & M_AMPDU_MPDU) { 4679 uint16_t seqno = ni->ni_txseqs[tid]; 4680 4681 if (ring->queued > IWN_TX_RING_COUNT / 2 && 4682 (ring->cur + 1) % IWN_TX_RING_COUNT == ring->read) { 4683 DPRINTF(sc, IWN_DEBUG_AMPDU, "%s: no more space " 4684 "(queued %d) left in %d queue!\n", 4685 __func__, ring->queued, ac); 4686 return (ENOBUFS); 4687 } 4688 4689 /* 4690 * Queue this frame to the hardware ring that we've 4691 * negotiated AMPDU TX on. 4692 * 4693 * Note that the sequence number must match the TX slot 4694 * being used! 4695 */ 4696 if ((seqno % 256) != ring->cur) { 4697 device_printf(sc->sc_dev, 4698 "%s: m=%p: seqno (%d) (%d) != ring index (%d) !\n", 4699 __func__, 4700 m, 4701 seqno, 4702 seqno % 256, 4703 ring->cur); 4704 4705 /* XXX until D9195 will not be committed */ 4706 ni->ni_txseqs[tid] &= ~0xff; 4707 ni->ni_txseqs[tid] += ring->cur; 4708 seqno = ni->ni_txseqs[tid]; 4709 } 4710 4711 *(uint16_t *)wh->i_seq = 4712 htole16(seqno << IEEE80211_SEQ_SEQ_SHIFT); 4713 ni->ni_txseqs[tid]++; 4714 } 4715 4716 /* Prepare TX firmware command. */ 4717 cmd = &ring->cmd[ring->cur]; 4718 tx = (struct iwn_cmd_data *)cmd->data; 4719 4720 /* NB: No need to clear tx, all fields are reinitialized here. */ 4721 tx->scratch = 0; /* clear "scratch" area */ 4722 4723 if (IEEE80211_IS_MULTICAST(wh->i_addr1) || 4724 type != IEEE80211_FC0_TYPE_DATA) 4725 tx->id = sc->broadcast_id; 4726 else 4727 tx->id = wn->id; 4728 4729 if (type == IEEE80211_FC0_TYPE_MGT) { 4730 uint8_t subtype = wh->i_fc[0] & IEEE80211_FC0_SUBTYPE_MASK; 4731 4732 /* Tell HW to set timestamp in probe responses. */ 4733 if (subtype == IEEE80211_FC0_SUBTYPE_PROBE_RESP) 4734 flags |= IWN_TX_INSERT_TSTAMP; 4735 if (subtype == IEEE80211_FC0_SUBTYPE_ASSOC_REQ || 4736 subtype == IEEE80211_FC0_SUBTYPE_REASSOC_REQ) 4737 tx->timeout = htole16(3); 4738 else 4739 tx->timeout = htole16(2); 4740 } else 4741 tx->timeout = htole16(0); 4742 4743 if (tx->id == sc->broadcast_id) { 4744 /* Group or management frame. */ 4745 tx->linkq = 0; 4746 } else { 4747 tx->linkq = iwn_tx_rate_to_linkq_offset(sc, ni, rate); 4748 flags |= IWN_TX_LINKQ; /* enable MRR */ 4749 } 4750 4751 tx->tid = tid; 4752 tx->rts_ntries = 60; 4753 tx->data_ntries = 15; 4754 tx->lifetime = htole32(IWN_LIFETIME_INFINITE); 4755 tx->rate = iwn_rate_to_plcp(sc, ni, rate); 4756 tx->security = 0; 4757 tx->flags = htole32(flags); 4758 4759 return (iwn_tx_cmd(sc, m, ni, ring)); 4760 } 4761 4762 static int 4763 iwn_tx_data_raw(struct iwn_softc *sc, struct mbuf *m, 4764 struct ieee80211_node *ni, const struct ieee80211_bpf_params *params) 4765 { 4766 struct ieee80211vap *vap = ni->ni_vap; 4767 struct iwn_tx_cmd *cmd; 4768 struct iwn_cmd_data *tx; 4769 struct ieee80211_frame *wh; 4770 struct iwn_tx_ring *ring; 4771 uint32_t flags; 4772 int ac, rate; 4773 uint8_t type; 4774 4775 DPRINTF(sc, IWN_DEBUG_TRACE, "->%s begin\n", __func__); 4776 4777 IWN_LOCK_ASSERT(sc); 4778 4779 wh = mtod(m, struct ieee80211_frame *); 4780 type = wh->i_fc[0] & IEEE80211_FC0_TYPE_MASK; 4781 4782 ac = params->ibp_pri & 3; 4783 4784 /* Choose a TX rate. */ 4785 rate = params->ibp_rate0; 4786 4787 flags = 0; 4788 if ((params->ibp_flags & IEEE80211_BPF_NOACK) == 0) 4789 flags |= IWN_TX_NEED_ACK; 4790 if (params->ibp_flags & IEEE80211_BPF_RTS) { 4791 if (sc->hw_type != IWN_HW_REV_TYPE_4965) { 4792 /* 5000 autoselects RTS/CTS or CTS-to-self. */ 4793 flags &= ~IWN_TX_NEED_RTS; 4794 flags |= IWN_TX_NEED_PROTECTION; 4795 } else 4796 flags |= IWN_TX_NEED_RTS | IWN_TX_FULL_TXOP; 4797 } 4798 if (params->ibp_flags & IEEE80211_BPF_CTS) { 4799 if (sc->hw_type != IWN_HW_REV_TYPE_4965) { 4800 /* 5000 autoselects RTS/CTS or CTS-to-self. */ 4801 flags &= ~IWN_TX_NEED_CTS; 4802 flags |= IWN_TX_NEED_PROTECTION; 4803 } else 4804 flags |= IWN_TX_NEED_CTS | IWN_TX_FULL_TXOP; 4805 } 4806 4807 if (ieee80211_radiotap_active_vap(vap)) { 4808 struct iwn_tx_radiotap_header *tap = &sc->sc_txtap; 4809 4810 tap->wt_flags = 0; 4811 tap->wt_rate = rate; 4812 4813 ieee80211_radiotap_tx(vap, m); 4814 } 4815 4816 ring = &sc->txq[ac]; 4817 cmd = &ring->cmd[ring->cur]; 4818 4819 tx = (struct iwn_cmd_data *)cmd->data; 4820 /* NB: No need to clear tx, all fields are reinitialized here. */ 4821 tx->scratch = 0; /* clear "scratch" area */ 4822 4823 if (type == IEEE80211_FC0_TYPE_MGT) { 4824 uint8_t subtype = wh->i_fc[0] & IEEE80211_FC0_SUBTYPE_MASK; 4825 4826 /* Tell HW to set timestamp in probe responses. */ 4827 if (subtype == IEEE80211_FC0_SUBTYPE_PROBE_RESP) 4828 flags |= IWN_TX_INSERT_TSTAMP; 4829 4830 if (subtype == IEEE80211_FC0_SUBTYPE_ASSOC_REQ || 4831 subtype == IEEE80211_FC0_SUBTYPE_REASSOC_REQ) 4832 tx->timeout = htole16(3); 4833 else 4834 tx->timeout = htole16(2); 4835 } else 4836 tx->timeout = htole16(0); 4837 4838 tx->tid = 0; 4839 tx->id = sc->broadcast_id; 4840 tx->rts_ntries = params->ibp_try1; 4841 tx->data_ntries = params->ibp_try0; 4842 tx->lifetime = htole32(IWN_LIFETIME_INFINITE); 4843 tx->rate = iwn_rate_to_plcp(sc, ni, rate); 4844 tx->security = 0; 4845 tx->flags = htole32(flags); 4846 4847 /* Group or management frame. */ 4848 tx->linkq = 0; 4849 4850 return (iwn_tx_cmd(sc, m, ni, ring)); 4851 } 4852 4853 static int 4854 iwn_tx_cmd(struct iwn_softc *sc, struct mbuf *m, struct ieee80211_node *ni, 4855 struct iwn_tx_ring *ring) 4856 { 4857 struct iwn_ops *ops = &sc->ops; 4858 struct iwn_tx_cmd *cmd; 4859 struct iwn_cmd_data *tx; 4860 struct ieee80211_frame *wh; 4861 struct iwn_tx_desc *desc; 4862 struct iwn_tx_data *data; 4863 bus_dma_segment_t *seg, segs[IWN_MAX_SCATTER]; 4864 struct mbuf *m1; 4865 u_int hdrlen; 4866 int totlen, error, pad, nsegs = 0, i; 4867 4868 wh = mtod(m, struct ieee80211_frame *); 4869 hdrlen = ieee80211_anyhdrsize(wh); 4870 totlen = m->m_pkthdr.len; 4871 4872 desc = &ring->desc[ring->cur]; 4873 data = &ring->data[ring->cur]; 4874 4875 if (__predict_false(data->m != NULL || data->ni != NULL)) { 4876 device_printf(sc->sc_dev, "%s: ni (%p) or m (%p) for idx %d " 4877 "in queue %d is not NULL!\n", __func__, data->ni, data->m, 4878 ring->cur, ring->qid); 4879 return EIO; 4880 } 4881 4882 /* Prepare TX firmware command. */ 4883 cmd = &ring->cmd[ring->cur]; 4884 cmd->code = IWN_CMD_TX_DATA; 4885 cmd->flags = 0; 4886 cmd->qid = ring->qid; 4887 cmd->idx = ring->cur; 4888 4889 tx = (struct iwn_cmd_data *)cmd->data; 4890 tx->len = htole16(totlen); 4891 4892 /* Set physical address of "scratch area". */ 4893 tx->loaddr = htole32(IWN_LOADDR(data->scratch_paddr)); 4894 tx->hiaddr = IWN_HIADDR(data->scratch_paddr); 4895 if (hdrlen & 3) { 4896 /* First segment length must be a multiple of 4. */ 4897 tx->flags |= htole32(IWN_TX_NEED_PADDING); 4898 pad = 4 - (hdrlen & 3); 4899 } else 4900 pad = 0; 4901 4902 /* Copy 802.11 header in TX command. */ 4903 memcpy((uint8_t *)(tx + 1), wh, hdrlen); 4904 4905 /* Trim 802.11 header. */ 4906 m_adj(m, hdrlen); 4907 4908 error = bus_dmamap_load_mbuf_sg(ring->data_dmat, data->map, m, segs, 4909 &nsegs, BUS_DMA_NOWAIT); 4910 if (error != 0) { 4911 if (error != EFBIG) { 4912 device_printf(sc->sc_dev, 4913 "%s: can't map mbuf (error %d)\n", __func__, error); 4914 return error; 4915 } 4916 /* Too many DMA segments, linearize mbuf. */ 4917 m1 = m_collapse(m, M_NOWAIT, IWN_MAX_SCATTER - 1); 4918 if (m1 == NULL) { 4919 device_printf(sc->sc_dev, 4920 "%s: could not defrag mbuf\n", __func__); 4921 return ENOBUFS; 4922 } 4923 m = m1; 4924 4925 error = bus_dmamap_load_mbuf_sg(ring->data_dmat, data->map, m, 4926 segs, &nsegs, BUS_DMA_NOWAIT); 4927 if (error != 0) { 4928 /* XXX fix this */ 4929 /* 4930 * NB: Do not return error; 4931 * original mbuf does not exist anymore. 4932 */ 4933 device_printf(sc->sc_dev, 4934 "%s: can't map mbuf (error %d)\n", 4935 __func__, error); 4936 if_inc_counter(ni->ni_vap->iv_ifp, 4937 IFCOUNTER_OERRORS, 1); 4938 ieee80211_free_node(ni); 4939 m_freem(m); 4940 return 0; 4941 } 4942 } 4943 4944 data->m = m; 4945 data->ni = ni; 4946 4947 DPRINTF(sc, IWN_DEBUG_XMIT, "%s: qid %d idx %d len %d nsegs %d " 4948 "plcp %d\n", 4949 __func__, ring->qid, ring->cur, totlen, nsegs, tx->rate); 4950 4951 /* Fill TX descriptor. */ 4952 desc->nsegs = 1; 4953 if (m->m_len != 0) 4954 desc->nsegs += nsegs; 4955 /* First DMA segment is used by the TX command. */ 4956 desc->segs[0].addr = htole32(IWN_LOADDR(data->cmd_paddr)); 4957 desc->segs[0].len = htole16(IWN_HIADDR(data->cmd_paddr) | 4958 (4 + sizeof (*tx) + hdrlen + pad) << 4); 4959 /* Other DMA segments are for data payload. */ 4960 seg = &segs[0]; 4961 for (i = 1; i <= nsegs; i++) { 4962 desc->segs[i].addr = htole32(IWN_LOADDR(seg->ds_addr)); 4963 desc->segs[i].len = htole16(IWN_HIADDR(seg->ds_addr) | 4964 seg->ds_len << 4); 4965 seg++; 4966 } 4967 4968 bus_dmamap_sync(ring->data_dmat, data->map, BUS_DMASYNC_PREWRITE); 4969 bus_dmamap_sync(ring->cmd_dma.tag, ring->cmd_dma.map, 4970 BUS_DMASYNC_PREWRITE); 4971 bus_dmamap_sync(ring->desc_dma.tag, ring->desc_dma.map, 4972 BUS_DMASYNC_PREWRITE); 4973 4974 /* Update TX scheduler. */ 4975 if (ring->qid >= sc->firstaggqueue) 4976 ops->update_sched(sc, ring->qid, ring->cur, tx->id, totlen); 4977 4978 /* Kick TX ring. */ 4979 ring->cur = (ring->cur + 1) % IWN_TX_RING_COUNT; 4980 IWN_WRITE(sc, IWN_HBUS_TARG_WRPTR, ring->qid << 8 | ring->cur); 4981 4982 /* Mark TX ring as full if we reach a certain threshold. */ 4983 if (++ring->queued > IWN_TX_RING_HIMARK) 4984 sc->qfullmsk |= 1 << ring->qid; 4985 4986 DPRINTF(sc, IWN_DEBUG_TRACE, "->%s: end\n",__func__); 4987 4988 return 0; 4989 } 4990 4991 static void 4992 iwn_xmit_task(void *arg0, int pending) 4993 { 4994 struct iwn_softc *sc = arg0; 4995 struct ieee80211_node *ni; 4996 struct mbuf *m; 4997 int error; 4998 struct ieee80211_bpf_params p; 4999 int have_p; 5000 5001 DPRINTF(sc, IWN_DEBUG_XMIT, "%s: called\n", __func__); 5002 5003 IWN_LOCK(sc); 5004 /* 5005 * Dequeue frames, attempt to transmit, 5006 * then disable beaconwait when we're done. 5007 */ 5008 while ((m = mbufq_dequeue(&sc->sc_xmit_queue)) != NULL) { 5009 have_p = 0; 5010 ni = (struct ieee80211_node *)m->m_pkthdr.rcvif; 5011 5012 /* Get xmit params if appropriate */ 5013 if (ieee80211_get_xmit_params(m, &p) == 0) 5014 have_p = 1; 5015 5016 DPRINTF(sc, IWN_DEBUG_XMIT, "%s: m=%p, have_p=%d\n", 5017 __func__, m, have_p); 5018 5019 /* If we have xmit params, use them */ 5020 if (have_p) 5021 error = iwn_tx_data_raw(sc, m, ni, &p); 5022 else 5023 error = iwn_tx_data(sc, m, ni); 5024 5025 if (error != 0) { 5026 if_inc_counter(ni->ni_vap->iv_ifp, 5027 IFCOUNTER_OERRORS, 1); 5028 ieee80211_free_node(ni); 5029 m_freem(m); 5030 } 5031 } 5032 5033 sc->sc_beacon_wait = 0; 5034 IWN_UNLOCK(sc); 5035 } 5036 5037 /* 5038 * raw frame xmit - free node/reference if failed. 5039 */ 5040 static int 5041 iwn_raw_xmit(struct ieee80211_node *ni, struct mbuf *m, 5042 const struct ieee80211_bpf_params *params) 5043 { 5044 struct ieee80211com *ic = ni->ni_ic; 5045 struct iwn_softc *sc = ic->ic_softc; 5046 int error = 0; 5047 5048 DPRINTF(sc, IWN_DEBUG_XMIT | IWN_DEBUG_TRACE, "->%s begin\n", __func__); 5049 5050 IWN_LOCK(sc); 5051 if ((sc->sc_flags & IWN_FLAG_RUNNING) == 0) { 5052 m_freem(m); 5053 IWN_UNLOCK(sc); 5054 return (ENETDOWN); 5055 } 5056 5057 /* queue frame if we have to */ 5058 if (sc->sc_beacon_wait) { 5059 if (iwn_xmit_queue_enqueue(sc, m) != 0) { 5060 m_freem(m); 5061 IWN_UNLOCK(sc); 5062 return (ENOBUFS); 5063 } 5064 /* Queued, so just return OK */ 5065 IWN_UNLOCK(sc); 5066 return (0); 5067 } 5068 5069 if (params == NULL) { 5070 /* 5071 * Legacy path; interpret frame contents to decide 5072 * precisely how to send the frame. 5073 */ 5074 error = iwn_tx_data(sc, m, ni); 5075 } else { 5076 /* 5077 * Caller supplied explicit parameters to use in 5078 * sending the frame. 5079 */ 5080 error = iwn_tx_data_raw(sc, m, ni, params); 5081 } 5082 if (error == 0) 5083 sc->sc_tx_timer = 5; 5084 else 5085 m_freem(m); 5086 5087 IWN_UNLOCK(sc); 5088 5089 DPRINTF(sc, IWN_DEBUG_TRACE | IWN_DEBUG_XMIT, "->%s: end\n",__func__); 5090 5091 return (error); 5092 } 5093 5094 /* 5095 * transmit - don't free mbuf if failed; don't free node ref if failed. 5096 */ 5097 static int 5098 iwn_transmit(struct ieee80211com *ic, struct mbuf *m) 5099 { 5100 struct iwn_softc *sc = ic->ic_softc; 5101 struct ieee80211_node *ni; 5102 int error; 5103 5104 ni = (struct ieee80211_node *)m->m_pkthdr.rcvif; 5105 5106 IWN_LOCK(sc); 5107 if ((sc->sc_flags & IWN_FLAG_RUNNING) == 0 || sc->sc_beacon_wait) { 5108 IWN_UNLOCK(sc); 5109 return (ENXIO); 5110 } 5111 5112 if (sc->qfullmsk) { 5113 IWN_UNLOCK(sc); 5114 return (ENOBUFS); 5115 } 5116 5117 error = iwn_tx_data(sc, m, ni); 5118 if (!error) 5119 sc->sc_tx_timer = 5; 5120 IWN_UNLOCK(sc); 5121 return (error); 5122 } 5123 5124 static void 5125 iwn_scan_timeout(void *arg) 5126 { 5127 struct iwn_softc *sc = arg; 5128 struct ieee80211com *ic = &sc->sc_ic; 5129 5130 ic_printf(ic, "scan timeout\n"); 5131 ieee80211_restart_all(ic); 5132 } 5133 5134 static void 5135 iwn_watchdog(void *arg) 5136 { 5137 struct iwn_softc *sc = arg; 5138 struct ieee80211com *ic = &sc->sc_ic; 5139 5140 IWN_LOCK_ASSERT(sc); 5141 5142 KASSERT(sc->sc_flags & IWN_FLAG_RUNNING, ("not running")); 5143 5144 DPRINTF(sc, IWN_DEBUG_TRACE, "->Doing %s\n", __func__); 5145 5146 if (sc->sc_tx_timer > 0) { 5147 if (--sc->sc_tx_timer == 0) { 5148 ic_printf(ic, "device timeout\n"); 5149 ieee80211_restart_all(ic); 5150 return; 5151 } 5152 } 5153 callout_reset(&sc->watchdog_to, hz, iwn_watchdog, sc); 5154 } 5155 5156 static int 5157 iwn_cdev_open(struct cdev *dev, int flags, int type, struct thread *td) 5158 { 5159 5160 return (0); 5161 } 5162 5163 static int 5164 iwn_cdev_close(struct cdev *dev, int flags, int type, struct thread *td) 5165 { 5166 5167 return (0); 5168 } 5169 5170 static int 5171 iwn_cdev_ioctl(struct cdev *dev, unsigned long cmd, caddr_t data, int fflag, 5172 struct thread *td) 5173 { 5174 int rc; 5175 struct iwn_softc *sc = dev->si_drv1; 5176 struct iwn_ioctl_data *d; 5177 5178 rc = priv_check(td, PRIV_DRIVER); 5179 if (rc != 0) 5180 return (0); 5181 5182 switch (cmd) { 5183 case SIOCGIWNSTATS: 5184 d = (struct iwn_ioctl_data *) data; 5185 IWN_LOCK(sc); 5186 /* XXX validate permissions/memory/etc? */ 5187 rc = copyout(&sc->last_stat, d->dst_addr, sizeof(struct iwn_stats)); 5188 IWN_UNLOCK(sc); 5189 break; 5190 case SIOCZIWNSTATS: 5191 IWN_LOCK(sc); 5192 memset(&sc->last_stat, 0, sizeof(struct iwn_stats)); 5193 IWN_UNLOCK(sc); 5194 break; 5195 default: 5196 rc = EINVAL; 5197 break; 5198 } 5199 return (rc); 5200 } 5201 5202 static int 5203 iwn_ioctl(struct ieee80211com *ic, u_long cmd, void *data) 5204 { 5205 5206 return (ENOTTY); 5207 } 5208 5209 static void 5210 iwn_parent(struct ieee80211com *ic) 5211 { 5212 struct iwn_softc *sc = ic->ic_softc; 5213 struct ieee80211vap *vap; 5214 int error; 5215 5216 if (ic->ic_nrunning > 0) { 5217 error = iwn_init(sc); 5218 5219 switch (error) { 5220 case 0: 5221 ieee80211_start_all(ic); 5222 break; 5223 case 1: 5224 /* radio is disabled via RFkill switch */ 5225 taskqueue_enqueue(sc->sc_tq, &sc->sc_rftoggle_task); 5226 break; 5227 default: 5228 vap = TAILQ_FIRST(&ic->ic_vaps); 5229 if (vap != NULL) 5230 ieee80211_stop(vap); 5231 break; 5232 } 5233 } else 5234 iwn_stop(sc); 5235 } 5236 5237 /* 5238 * Send a command to the firmware. 5239 */ 5240 static int 5241 iwn_cmd(struct iwn_softc *sc, int code, const void *buf, int size, int async) 5242 { 5243 struct iwn_tx_ring *ring; 5244 struct iwn_tx_desc *desc; 5245 struct iwn_tx_data *data; 5246 struct iwn_tx_cmd *cmd; 5247 struct mbuf *m; 5248 bus_addr_t paddr; 5249 int totlen, error; 5250 int cmd_queue_num; 5251 5252 DPRINTF(sc, IWN_DEBUG_TRACE, "->%s begin\n", __func__); 5253 5254 if (async == 0) 5255 IWN_LOCK_ASSERT(sc); 5256 5257 if (sc->sc_flags & IWN_FLAG_PAN_SUPPORT) 5258 cmd_queue_num = IWN_PAN_CMD_QUEUE; 5259 else 5260 cmd_queue_num = IWN_CMD_QUEUE_NUM; 5261 5262 ring = &sc->txq[cmd_queue_num]; 5263 desc = &ring->desc[ring->cur]; 5264 data = &ring->data[ring->cur]; 5265 totlen = 4 + size; 5266 5267 if (size > sizeof cmd->data) { 5268 /* Command is too large to fit in a descriptor. */ 5269 if (totlen > MCLBYTES) 5270 return EINVAL; 5271 m = m_getjcl(M_NOWAIT, MT_DATA, M_PKTHDR, MJUMPAGESIZE); 5272 if (m == NULL) 5273 return ENOMEM; 5274 cmd = mtod(m, struct iwn_tx_cmd *); 5275 error = bus_dmamap_load(ring->data_dmat, data->map, cmd, 5276 totlen, iwn_dma_map_addr, &paddr, BUS_DMA_NOWAIT); 5277 if (error != 0) { 5278 m_freem(m); 5279 return error; 5280 } 5281 data->m = m; 5282 } else { 5283 cmd = &ring->cmd[ring->cur]; 5284 paddr = data->cmd_paddr; 5285 } 5286 5287 cmd->code = code; 5288 cmd->flags = 0; 5289 cmd->qid = ring->qid; 5290 cmd->idx = ring->cur; 5291 memcpy(cmd->data, buf, size); 5292 5293 desc->nsegs = 1; 5294 desc->segs[0].addr = htole32(IWN_LOADDR(paddr)); 5295 desc->segs[0].len = htole16(IWN_HIADDR(paddr) | totlen << 4); 5296 5297 DPRINTF(sc, IWN_DEBUG_CMD, "%s: %s (0x%x) flags %d qid %d idx %d\n", 5298 __func__, iwn_intr_str(cmd->code), cmd->code, 5299 cmd->flags, cmd->qid, cmd->idx); 5300 5301 if (size > sizeof cmd->data) { 5302 bus_dmamap_sync(ring->data_dmat, data->map, 5303 BUS_DMASYNC_PREWRITE); 5304 } else { 5305 bus_dmamap_sync(ring->cmd_dma.tag, ring->cmd_dma.map, 5306 BUS_DMASYNC_PREWRITE); 5307 } 5308 bus_dmamap_sync(ring->desc_dma.tag, ring->desc_dma.map, 5309 BUS_DMASYNC_PREWRITE); 5310 5311 /* Kick command ring. */ 5312 ring->cur = (ring->cur + 1) % IWN_TX_RING_COUNT; 5313 IWN_WRITE(sc, IWN_HBUS_TARG_WRPTR, ring->qid << 8 | ring->cur); 5314 5315 DPRINTF(sc, IWN_DEBUG_TRACE, "->%s: end\n",__func__); 5316 5317 return async ? 0 : msleep(desc, &sc->sc_mtx, PCATCH, "iwncmd", hz); 5318 } 5319 5320 static int 5321 iwn4965_add_node(struct iwn_softc *sc, struct iwn_node_info *node, int async) 5322 { 5323 struct iwn4965_node_info hnode; 5324 caddr_t src, dst; 5325 5326 DPRINTF(sc, IWN_DEBUG_TRACE, "->Doing %s\n", __func__); 5327 5328 /* 5329 * We use the node structure for 5000 Series internally (it is 5330 * a superset of the one for 4965AGN). We thus copy the common 5331 * fields before sending the command. 5332 */ 5333 src = (caddr_t)node; 5334 dst = (caddr_t)&hnode; 5335 memcpy(dst, src, 48); 5336 /* Skip TSC, RX MIC and TX MIC fields from ``src''. */ 5337 memcpy(dst + 48, src + 72, 20); 5338 return iwn_cmd(sc, IWN_CMD_ADD_NODE, &hnode, sizeof hnode, async); 5339 } 5340 5341 static int 5342 iwn5000_add_node(struct iwn_softc *sc, struct iwn_node_info *node, int async) 5343 { 5344 5345 DPRINTF(sc, IWN_DEBUG_TRACE, "->Doing %s\n", __func__); 5346 5347 /* Direct mapping. */ 5348 return iwn_cmd(sc, IWN_CMD_ADD_NODE, node, sizeof (*node), async); 5349 } 5350 5351 static int 5352 iwn_set_link_quality(struct iwn_softc *sc, struct ieee80211_node *ni) 5353 { 5354 struct iwn_node *wn = (void *)ni; 5355 struct ieee80211_rateset *rs; 5356 struct iwn_cmd_link_quality linkq; 5357 int i, rate, txrate; 5358 int is_11n; 5359 5360 DPRINTF(sc, IWN_DEBUG_TRACE, "->%s begin\n", __func__); 5361 5362 memset(&linkq, 0, sizeof linkq); 5363 linkq.id = wn->id; 5364 linkq.antmsk_1stream = iwn_get_1stream_tx_antmask(sc); 5365 linkq.antmsk_2stream = iwn_get_2stream_tx_antmask(sc); 5366 5367 linkq.ampdu_max = 32; /* XXX negotiated? */ 5368 linkq.ampdu_threshold = 3; 5369 linkq.ampdu_limit = htole16(4000); /* 4ms */ 5370 5371 DPRINTF(sc, IWN_DEBUG_XMIT, 5372 "%s: 1stream antenna=0x%02x, 2stream antenna=0x%02x, ntxstreams=%d\n", 5373 __func__, 5374 linkq.antmsk_1stream, 5375 linkq.antmsk_2stream, 5376 sc->ntxchains); 5377 5378 /* 5379 * Are we using 11n rates? Ensure the channel is 5380 * 11n _and_ we have some 11n rates, or don't 5381 * try. 5382 */ 5383 if (IEEE80211_IS_CHAN_HT(ni->ni_chan) && ni->ni_htrates.rs_nrates > 0) { 5384 rs = (struct ieee80211_rateset *) &ni->ni_htrates; 5385 is_11n = 1; 5386 } else { 5387 rs = &ni->ni_rates; 5388 is_11n = 0; 5389 } 5390 5391 /* Start at highest available bit-rate. */ 5392 /* 5393 * XXX this is all very dirty! 5394 */ 5395 if (is_11n) 5396 txrate = ni->ni_htrates.rs_nrates - 1; 5397 else 5398 txrate = rs->rs_nrates - 1; 5399 for (i = 0; i < IWN_MAX_TX_RETRIES; i++) { 5400 uint32_t plcp; 5401 5402 /* 5403 * XXX TODO: ensure the last two slots are the two lowest 5404 * rate entries, just for now. 5405 */ 5406 if (i == 14 || i == 15) 5407 txrate = 0; 5408 5409 if (is_11n) 5410 rate = IEEE80211_RATE_MCS | rs->rs_rates[txrate]; 5411 else 5412 rate = IEEE80211_RV(rs->rs_rates[txrate]); 5413 5414 /* Do rate -> PLCP config mapping */ 5415 plcp = iwn_rate_to_plcp(sc, ni, rate); 5416 linkq.retry[i] = plcp; 5417 DPRINTF(sc, IWN_DEBUG_XMIT, 5418 "%s: i=%d, txrate=%d, rate=0x%02x, plcp=0x%08x\n", 5419 __func__, 5420 i, 5421 txrate, 5422 rate, 5423 le32toh(plcp)); 5424 5425 /* 5426 * The mimo field is an index into the table which 5427 * indicates the first index where it and subsequent entries 5428 * will not be using MIMO. 5429 * 5430 * Since we're filling linkq from 0..15 and we're filling 5431 * from the highest MCS rates to the lowest rates, if we 5432 * _are_ doing a dual-stream rate, set mimo to idx+1 (ie, 5433 * the next entry.) That way if the next entry is a non-MIMO 5434 * entry, we're already pointing at it. 5435 */ 5436 if ((le32toh(plcp) & IWN_RFLAG_MCS) && 5437 IEEE80211_RV(le32toh(plcp)) > 7) 5438 linkq.mimo = i + 1; 5439 5440 /* Next retry at immediate lower bit-rate. */ 5441 if (txrate > 0) 5442 txrate--; 5443 } 5444 /* 5445 * If we reached the end of the list and indeed we hit 5446 * all MIMO rates (eg 5300 doing MCS23-15) then yes, 5447 * set mimo to 15. Setting it to 16 panics the firmware. 5448 */ 5449 if (linkq.mimo > 15) 5450 linkq.mimo = 15; 5451 5452 DPRINTF(sc, IWN_DEBUG_XMIT, "%s: mimo = %d\n", __func__, linkq.mimo); 5453 5454 DPRINTF(sc, IWN_DEBUG_TRACE, "->%s: end\n",__func__); 5455 5456 return iwn_cmd(sc, IWN_CMD_LINK_QUALITY, &linkq, sizeof linkq, 1); 5457 } 5458 5459 /* 5460 * Broadcast node is used to send group-addressed and management frames. 5461 */ 5462 static int 5463 iwn_add_broadcast_node(struct iwn_softc *sc, int async) 5464 { 5465 struct iwn_ops *ops = &sc->ops; 5466 struct ieee80211com *ic = &sc->sc_ic; 5467 struct iwn_node_info node; 5468 struct iwn_cmd_link_quality linkq; 5469 uint8_t txant; 5470 int i, error; 5471 5472 DPRINTF(sc, IWN_DEBUG_TRACE, "->%s begin\n", __func__); 5473 5474 sc->rxon = &sc->rx_on[IWN_RXON_BSS_CTX]; 5475 5476 memset(&node, 0, sizeof node); 5477 IEEE80211_ADDR_COPY(node.macaddr, ieee80211broadcastaddr); 5478 node.id = sc->broadcast_id; 5479 DPRINTF(sc, IWN_DEBUG_RESET, "%s: adding broadcast node\n", __func__); 5480 if ((error = ops->add_node(sc, &node, async)) != 0) 5481 return error; 5482 5483 /* Use the first valid TX antenna. */ 5484 txant = IWN_LSB(sc->txchainmask); 5485 5486 memset(&linkq, 0, sizeof linkq); 5487 linkq.id = sc->broadcast_id; 5488 linkq.antmsk_1stream = iwn_get_1stream_tx_antmask(sc); 5489 linkq.antmsk_2stream = iwn_get_2stream_tx_antmask(sc); 5490 linkq.ampdu_max = 64; 5491 linkq.ampdu_threshold = 3; 5492 linkq.ampdu_limit = htole16(4000); /* 4ms */ 5493 5494 /* Use lowest mandatory bit-rate. */ 5495 /* XXX rate table lookup? */ 5496 if (IEEE80211_IS_CHAN_5GHZ(ic->ic_curchan)) 5497 linkq.retry[0] = htole32(0xd); 5498 else 5499 linkq.retry[0] = htole32(10 | IWN_RFLAG_CCK); 5500 linkq.retry[0] |= htole32(IWN_RFLAG_ANT(txant)); 5501 /* Use same bit-rate for all TX retries. */ 5502 for (i = 1; i < IWN_MAX_TX_RETRIES; i++) { 5503 linkq.retry[i] = linkq.retry[0]; 5504 } 5505 5506 DPRINTF(sc, IWN_DEBUG_TRACE, "->%s: end\n",__func__); 5507 5508 return iwn_cmd(sc, IWN_CMD_LINK_QUALITY, &linkq, sizeof linkq, async); 5509 } 5510 5511 static int 5512 iwn_updateedca(struct ieee80211com *ic) 5513 { 5514 #define IWN_EXP2(x) ((1 << (x)) - 1) /* CWmin = 2^ECWmin - 1 */ 5515 struct iwn_softc *sc = ic->ic_softc; 5516 struct iwn_edca_params cmd; 5517 struct chanAccParams chp; 5518 int aci; 5519 5520 DPRINTF(sc, IWN_DEBUG_TRACE, "->%s begin\n", __func__); 5521 5522 ieee80211_wme_ic_getparams(ic, &chp); 5523 5524 memset(&cmd, 0, sizeof cmd); 5525 cmd.flags = htole32(IWN_EDCA_UPDATE); 5526 5527 IEEE80211_LOCK(ic); 5528 for (aci = 0; aci < WME_NUM_AC; aci++) { 5529 const struct wmeParams *ac = &chp.cap_wmeParams[aci]; 5530 cmd.ac[aci].aifsn = ac->wmep_aifsn; 5531 cmd.ac[aci].cwmin = htole16(IWN_EXP2(ac->wmep_logcwmin)); 5532 cmd.ac[aci].cwmax = htole16(IWN_EXP2(ac->wmep_logcwmax)); 5533 cmd.ac[aci].txoplimit = 5534 htole16(IEEE80211_TXOP_TO_US(ac->wmep_txopLimit)); 5535 } 5536 IEEE80211_UNLOCK(ic); 5537 5538 IWN_LOCK(sc); 5539 (void)iwn_cmd(sc, IWN_CMD_EDCA_PARAMS, &cmd, sizeof cmd, 1); 5540 IWN_UNLOCK(sc); 5541 5542 DPRINTF(sc, IWN_DEBUG_TRACE, "->%s: end\n",__func__); 5543 5544 return 0; 5545 #undef IWN_EXP2 5546 } 5547 5548 static void 5549 iwn_set_promisc(struct iwn_softc *sc) 5550 { 5551 struct ieee80211com *ic = &sc->sc_ic; 5552 uint32_t promisc_filter; 5553 5554 promisc_filter = IWN_FILTER_CTL | IWN_FILTER_PROMISC; 5555 if (ic->ic_promisc > 0 || ic->ic_opmode == IEEE80211_M_MONITOR) 5556 sc->rxon->filter |= htole32(promisc_filter); 5557 else 5558 sc->rxon->filter &= ~htole32(promisc_filter); 5559 } 5560 5561 static void 5562 iwn_update_promisc(struct ieee80211com *ic) 5563 { 5564 struct iwn_softc *sc = ic->ic_softc; 5565 int error; 5566 5567 if (ic->ic_opmode == IEEE80211_M_MONITOR) 5568 return; /* nothing to do */ 5569 5570 IWN_LOCK(sc); 5571 if (!(sc->sc_flags & IWN_FLAG_RUNNING)) { 5572 IWN_UNLOCK(sc); 5573 return; 5574 } 5575 5576 iwn_set_promisc(sc); 5577 if ((error = iwn_send_rxon(sc, 1, 1)) != 0) { 5578 device_printf(sc->sc_dev, 5579 "%s: could not send RXON, error %d\n", 5580 __func__, error); 5581 } 5582 IWN_UNLOCK(sc); 5583 } 5584 5585 static void 5586 iwn_update_mcast(struct ieee80211com *ic) 5587 { 5588 /* Ignore */ 5589 } 5590 5591 static void 5592 iwn_set_led(struct iwn_softc *sc, uint8_t which, uint8_t off, uint8_t on) 5593 { 5594 struct iwn_cmd_led led; 5595 5596 DPRINTF(sc, IWN_DEBUG_TRACE, "->Doing %s\n", __func__); 5597 5598 #if 0 5599 /* XXX don't set LEDs during scan? */ 5600 if (sc->sc_is_scanning) 5601 return; 5602 #endif 5603 5604 /* Clear microcode LED ownership. */ 5605 IWN_CLRBITS(sc, IWN_LED, IWN_LED_BSM_CTRL); 5606 5607 led.which = which; 5608 led.unit = htole32(10000); /* on/off in unit of 100ms */ 5609 led.off = off; 5610 led.on = on; 5611 (void)iwn_cmd(sc, IWN_CMD_SET_LED, &led, sizeof led, 1); 5612 } 5613 5614 /* 5615 * Set the critical temperature at which the firmware will stop the radio 5616 * and notify us. 5617 */ 5618 static int 5619 iwn_set_critical_temp(struct iwn_softc *sc) 5620 { 5621 struct iwn_critical_temp crit; 5622 int32_t temp; 5623 5624 DPRINTF(sc, IWN_DEBUG_TRACE, "->Doing %s\n", __func__); 5625 5626 IWN_WRITE(sc, IWN_UCODE_GP1_CLR, IWN_UCODE_GP1_CTEMP_STOP_RF); 5627 5628 if (sc->hw_type == IWN_HW_REV_TYPE_5150) 5629 temp = (IWN_CTOK(110) - sc->temp_off) * -5; 5630 else if (sc->hw_type == IWN_HW_REV_TYPE_4965) 5631 temp = IWN_CTOK(110); 5632 else 5633 temp = 110; 5634 memset(&crit, 0, sizeof crit); 5635 crit.tempR = htole32(temp); 5636 DPRINTF(sc, IWN_DEBUG_RESET, "setting critical temp to %d\n", temp); 5637 return iwn_cmd(sc, IWN_CMD_SET_CRITICAL_TEMP, &crit, sizeof crit, 0); 5638 } 5639 5640 static int 5641 iwn_set_timing(struct iwn_softc *sc, struct ieee80211_node *ni) 5642 { 5643 struct iwn_cmd_timing cmd; 5644 uint64_t val, mod; 5645 5646 DPRINTF(sc, IWN_DEBUG_TRACE, "->Doing %s\n", __func__); 5647 5648 memset(&cmd, 0, sizeof cmd); 5649 memcpy(&cmd.tstamp, ni->ni_tstamp.data, sizeof (uint64_t)); 5650 cmd.bintval = htole16(ni->ni_intval); 5651 cmd.lintval = htole16(10); 5652 5653 /* Compute remaining time until next beacon. */ 5654 val = (uint64_t)ni->ni_intval * IEEE80211_DUR_TU; 5655 mod = le64toh(cmd.tstamp) % val; 5656 cmd.binitval = htole32((uint32_t)(val - mod)); 5657 5658 DPRINTF(sc, IWN_DEBUG_RESET, "timing bintval=%u tstamp=%ju, init=%u\n", 5659 ni->ni_intval, le64toh(cmd.tstamp), (uint32_t)(val - mod)); 5660 5661 return iwn_cmd(sc, IWN_CMD_TIMING, &cmd, sizeof cmd, 1); 5662 } 5663 5664 static void 5665 iwn4965_power_calibration(struct iwn_softc *sc, int temp) 5666 { 5667 5668 DPRINTF(sc, IWN_DEBUG_TRACE, "->Doing %s\n", __func__); 5669 5670 /* Adjust TX power if need be (delta >= 3 degC). */ 5671 DPRINTF(sc, IWN_DEBUG_CALIBRATE, "%s: temperature %d->%d\n", 5672 __func__, sc->temp, temp); 5673 if (abs(temp - sc->temp) >= 3) { 5674 /* Record temperature of last calibration. */ 5675 sc->temp = temp; 5676 (void)iwn4965_set_txpower(sc, 1); 5677 } 5678 } 5679 5680 /* 5681 * Set TX power for current channel (each rate has its own power settings). 5682 * This function takes into account the regulatory information from EEPROM, 5683 * the current temperature and the current voltage. 5684 */ 5685 static int 5686 iwn4965_set_txpower(struct iwn_softc *sc, int async) 5687 { 5688 /* Fixed-point arithmetic division using a n-bit fractional part. */ 5689 #define fdivround(a, b, n) \ 5690 ((((1 << n) * (a)) / (b) + (1 << n) / 2) / (1 << n)) 5691 /* Linear interpolation. */ 5692 #define interpolate(x, x1, y1, x2, y2, n) \ 5693 ((y1) + fdivround(((int)(x) - (x1)) * ((y2) - (y1)), (x2) - (x1), n)) 5694 5695 static const int tdiv[IWN_NATTEN_GROUPS] = { 9, 8, 8, 8, 6 }; 5696 struct iwn_ucode_info *uc = &sc->ucode_info; 5697 struct iwn4965_cmd_txpower cmd; 5698 struct iwn4965_eeprom_chan_samples *chans; 5699 const uint8_t *rf_gain, *dsp_gain; 5700 int32_t vdiff, tdiff; 5701 int i, is_chan_5ghz, c, grp, maxpwr; 5702 uint8_t chan; 5703 5704 sc->rxon = &sc->rx_on[IWN_RXON_BSS_CTX]; 5705 /* Retrieve current channel from last RXON. */ 5706 chan = sc->rxon->chan; 5707 is_chan_5ghz = (sc->rxon->flags & htole32(IWN_RXON_24GHZ)) == 0; 5708 DPRINTF(sc, IWN_DEBUG_RESET, "setting TX power for channel %d\n", 5709 chan); 5710 5711 memset(&cmd, 0, sizeof cmd); 5712 cmd.band = is_chan_5ghz ? 0 : 1; 5713 cmd.chan = chan; 5714 5715 if (is_chan_5ghz) { 5716 maxpwr = sc->maxpwr5GHz; 5717 rf_gain = iwn4965_rf_gain_5ghz; 5718 dsp_gain = iwn4965_dsp_gain_5ghz; 5719 } else { 5720 maxpwr = sc->maxpwr2GHz; 5721 rf_gain = iwn4965_rf_gain_2ghz; 5722 dsp_gain = iwn4965_dsp_gain_2ghz; 5723 } 5724 5725 /* Compute voltage compensation. */ 5726 vdiff = ((int32_t)le32toh(uc->volt) - sc->eeprom_voltage) / 7; 5727 if (vdiff > 0) 5728 vdiff *= 2; 5729 if (abs(vdiff) > 2) 5730 vdiff = 0; 5731 DPRINTF(sc, IWN_DEBUG_CALIBRATE | IWN_DEBUG_TXPOW, 5732 "%s: voltage compensation=%d (UCODE=%d, EEPROM=%d)\n", 5733 __func__, vdiff, le32toh(uc->volt), sc->eeprom_voltage); 5734 5735 /* Get channel attenuation group. */ 5736 if (chan <= 20) /* 1-20 */ 5737 grp = 4; 5738 else if (chan <= 43) /* 34-43 */ 5739 grp = 0; 5740 else if (chan <= 70) /* 44-70 */ 5741 grp = 1; 5742 else if (chan <= 124) /* 71-124 */ 5743 grp = 2; 5744 else /* 125-200 */ 5745 grp = 3; 5746 DPRINTF(sc, IWN_DEBUG_CALIBRATE | IWN_DEBUG_TXPOW, 5747 "%s: chan %d, attenuation group=%d\n", __func__, chan, grp); 5748 5749 /* Get channel sub-band. */ 5750 for (i = 0; i < IWN_NBANDS; i++) 5751 if (sc->bands[i].lo != 0 && 5752 sc->bands[i].lo <= chan && chan <= sc->bands[i].hi) 5753 break; 5754 if (i == IWN_NBANDS) /* Can't happen in real-life. */ 5755 return EINVAL; 5756 chans = sc->bands[i].chans; 5757 DPRINTF(sc, IWN_DEBUG_CALIBRATE | IWN_DEBUG_TXPOW, 5758 "%s: chan %d sub-band=%d\n", __func__, chan, i); 5759 5760 for (c = 0; c < 2; c++) { 5761 uint8_t power, gain, temp; 5762 int maxchpwr, pwr, ridx, idx; 5763 5764 power = interpolate(chan, 5765 chans[0].num, chans[0].samples[c][1].power, 5766 chans[1].num, chans[1].samples[c][1].power, 1); 5767 gain = interpolate(chan, 5768 chans[0].num, chans[0].samples[c][1].gain, 5769 chans[1].num, chans[1].samples[c][1].gain, 1); 5770 temp = interpolate(chan, 5771 chans[0].num, chans[0].samples[c][1].temp, 5772 chans[1].num, chans[1].samples[c][1].temp, 1); 5773 DPRINTF(sc, IWN_DEBUG_CALIBRATE | IWN_DEBUG_TXPOW, 5774 "%s: Tx chain %d: power=%d gain=%d temp=%d\n", 5775 __func__, c, power, gain, temp); 5776 5777 /* Compute temperature compensation. */ 5778 tdiff = ((sc->temp - temp) * 2) / tdiv[grp]; 5779 DPRINTF(sc, IWN_DEBUG_CALIBRATE | IWN_DEBUG_TXPOW, 5780 "%s: temperature compensation=%d (current=%d, EEPROM=%d)\n", 5781 __func__, tdiff, sc->temp, temp); 5782 5783 for (ridx = 0; ridx <= IWN_RIDX_MAX; ridx++) { 5784 /* Convert dBm to half-dBm. */ 5785 maxchpwr = sc->maxpwr[chan] * 2; 5786 if ((ridx / 8) & 1) 5787 maxchpwr -= 6; /* MIMO 2T: -3dB */ 5788 5789 pwr = maxpwr; 5790 5791 /* Adjust TX power based on rate. */ 5792 if ((ridx % 8) == 5) 5793 pwr -= 15; /* OFDM48: -7.5dB */ 5794 else if ((ridx % 8) == 6) 5795 pwr -= 17; /* OFDM54: -8.5dB */ 5796 else if ((ridx % 8) == 7) 5797 pwr -= 20; /* OFDM60: -10dB */ 5798 else 5799 pwr -= 10; /* Others: -5dB */ 5800 5801 /* Do not exceed channel max TX power. */ 5802 if (pwr > maxchpwr) 5803 pwr = maxchpwr; 5804 5805 idx = gain - (pwr - power) - tdiff - vdiff; 5806 if ((ridx / 8) & 1) /* MIMO */ 5807 idx += (int32_t)le32toh(uc->atten[grp][c]); 5808 5809 if (cmd.band == 0) 5810 idx += 9; /* 5GHz */ 5811 if (ridx == IWN_RIDX_MAX) 5812 idx += 5; /* CCK */ 5813 5814 /* Make sure idx stays in a valid range. */ 5815 if (idx < 0) 5816 idx = 0; 5817 else if (idx > IWN4965_MAX_PWR_INDEX) 5818 idx = IWN4965_MAX_PWR_INDEX; 5819 5820 DPRINTF(sc, IWN_DEBUG_CALIBRATE | IWN_DEBUG_TXPOW, 5821 "%s: Tx chain %d, rate idx %d: power=%d\n", 5822 __func__, c, ridx, idx); 5823 cmd.power[ridx].rf_gain[c] = rf_gain[idx]; 5824 cmd.power[ridx].dsp_gain[c] = dsp_gain[idx]; 5825 } 5826 } 5827 5828 DPRINTF(sc, IWN_DEBUG_CALIBRATE | IWN_DEBUG_TXPOW, 5829 "%s: set tx power for chan %d\n", __func__, chan); 5830 return iwn_cmd(sc, IWN_CMD_TXPOWER, &cmd, sizeof cmd, async); 5831 5832 #undef interpolate 5833 #undef fdivround 5834 } 5835 5836 static int 5837 iwn5000_set_txpower(struct iwn_softc *sc, int async) 5838 { 5839 struct iwn5000_cmd_txpower cmd; 5840 int cmdid; 5841 5842 DPRINTF(sc, IWN_DEBUG_TRACE, "->Doing %s\n", __func__); 5843 5844 /* 5845 * TX power calibration is handled automatically by the firmware 5846 * for 5000 Series. 5847 */ 5848 memset(&cmd, 0, sizeof cmd); 5849 cmd.global_limit = 2 * IWN5000_TXPOWER_MAX_DBM; /* 16 dBm */ 5850 cmd.flags = IWN5000_TXPOWER_NO_CLOSED; 5851 cmd.srv_limit = IWN5000_TXPOWER_AUTO; 5852 DPRINTF(sc, IWN_DEBUG_CALIBRATE | IWN_DEBUG_XMIT, 5853 "%s: setting TX power; rev=%d\n", 5854 __func__, 5855 IWN_UCODE_API(sc->ucode_rev)); 5856 if (IWN_UCODE_API(sc->ucode_rev) == 1) 5857 cmdid = IWN_CMD_TXPOWER_DBM_V1; 5858 else 5859 cmdid = IWN_CMD_TXPOWER_DBM; 5860 return iwn_cmd(sc, cmdid, &cmd, sizeof cmd, async); 5861 } 5862 5863 /* 5864 * Retrieve the maximum RSSI (in dBm) among receivers. 5865 */ 5866 static int 5867 iwn4965_get_rssi(struct iwn_softc *sc, struct iwn_rx_stat *stat) 5868 { 5869 struct iwn4965_rx_phystat *phy = (void *)stat->phybuf; 5870 uint8_t mask, agc; 5871 int rssi; 5872 5873 DPRINTF(sc, IWN_DEBUG_TRACE, "->Doing %s\n", __func__); 5874 5875 mask = (le16toh(phy->antenna) >> 4) & IWN_ANT_ABC; 5876 agc = (le16toh(phy->agc) >> 7) & 0x7f; 5877 5878 rssi = 0; 5879 if (mask & IWN_ANT_A) 5880 rssi = MAX(rssi, phy->rssi[0]); 5881 if (mask & IWN_ANT_B) 5882 rssi = MAX(rssi, phy->rssi[2]); 5883 if (mask & IWN_ANT_C) 5884 rssi = MAX(rssi, phy->rssi[4]); 5885 5886 DPRINTF(sc, IWN_DEBUG_RECV, 5887 "%s: agc %d mask 0x%x rssi %d %d %d result %d\n", __func__, agc, 5888 mask, phy->rssi[0], phy->rssi[2], phy->rssi[4], 5889 rssi - agc - IWN_RSSI_TO_DBM); 5890 return rssi - agc - IWN_RSSI_TO_DBM; 5891 } 5892 5893 static int 5894 iwn5000_get_rssi(struct iwn_softc *sc, struct iwn_rx_stat *stat) 5895 { 5896 struct iwn5000_rx_phystat *phy = (void *)stat->phybuf; 5897 uint8_t agc; 5898 int rssi; 5899 5900 DPRINTF(sc, IWN_DEBUG_TRACE, "->Doing %s\n", __func__); 5901 5902 agc = (le32toh(phy->agc) >> 9) & 0x7f; 5903 5904 rssi = MAX(le16toh(phy->rssi[0]) & 0xff, 5905 le16toh(phy->rssi[1]) & 0xff); 5906 rssi = MAX(le16toh(phy->rssi[2]) & 0xff, rssi); 5907 5908 DPRINTF(sc, IWN_DEBUG_RECV, 5909 "%s: agc %d rssi %d %d %d result %d\n", __func__, agc, 5910 phy->rssi[0], phy->rssi[1], phy->rssi[2], 5911 rssi - agc - IWN_RSSI_TO_DBM); 5912 return rssi - agc - IWN_RSSI_TO_DBM; 5913 } 5914 5915 /* 5916 * Retrieve the average noise (in dBm) among receivers. 5917 */ 5918 static int 5919 iwn_get_noise(const struct iwn_rx_general_stats *stats) 5920 { 5921 int i, total, nbant, noise; 5922 5923 total = nbant = 0; 5924 for (i = 0; i < 3; i++) { 5925 if ((noise = le32toh(stats->noise[i]) & 0xff) == 0) 5926 continue; 5927 total += noise; 5928 nbant++; 5929 } 5930 /* There should be at least one antenna but check anyway. */ 5931 return (nbant == 0) ? -127 : (total / nbant) - 107; 5932 } 5933 5934 /* 5935 * Compute temperature (in degC) from last received statistics. 5936 */ 5937 static int 5938 iwn4965_get_temperature(struct iwn_softc *sc) 5939 { 5940 struct iwn_ucode_info *uc = &sc->ucode_info; 5941 int32_t r1, r2, r3, r4, temp; 5942 5943 DPRINTF(sc, IWN_DEBUG_TRACE, "->Doing %s\n", __func__); 5944 5945 r1 = le32toh(uc->temp[0].chan20MHz); 5946 r2 = le32toh(uc->temp[1].chan20MHz); 5947 r3 = le32toh(uc->temp[2].chan20MHz); 5948 r4 = le32toh(sc->rawtemp); 5949 5950 if (r1 == r3) /* Prevents division by 0 (should not happen). */ 5951 return 0; 5952 5953 /* Sign-extend 23-bit R4 value to 32-bit. */ 5954 r4 = ((r4 & 0xffffff) ^ 0x800000) - 0x800000; 5955 /* Compute temperature in Kelvin. */ 5956 temp = (259 * (r4 - r2)) / (r3 - r1); 5957 temp = (temp * 97) / 100 + 8; 5958 5959 DPRINTF(sc, IWN_DEBUG_ANY, "temperature %dK/%dC\n", temp, 5960 IWN_KTOC(temp)); 5961 return IWN_KTOC(temp); 5962 } 5963 5964 static int 5965 iwn5000_get_temperature(struct iwn_softc *sc) 5966 { 5967 int32_t temp; 5968 5969 DPRINTF(sc, IWN_DEBUG_TRACE, "->Doing %s\n", __func__); 5970 5971 /* 5972 * Temperature is not used by the driver for 5000 Series because 5973 * TX power calibration is handled by firmware. 5974 */ 5975 temp = le32toh(sc->rawtemp); 5976 if (sc->hw_type == IWN_HW_REV_TYPE_5150) { 5977 temp = (temp / -5) + sc->temp_off; 5978 temp = IWN_KTOC(temp); 5979 } 5980 return temp; 5981 } 5982 5983 /* 5984 * Initialize sensitivity calibration state machine. 5985 */ 5986 static int 5987 iwn_init_sensitivity(struct iwn_softc *sc) 5988 { 5989 struct iwn_ops *ops = &sc->ops; 5990 struct iwn_calib_state *calib = &sc->calib; 5991 uint32_t flags; 5992 int error; 5993 5994 DPRINTF(sc, IWN_DEBUG_TRACE, "->Doing %s\n", __func__); 5995 5996 /* Reset calibration state machine. */ 5997 memset(calib, 0, sizeof (*calib)); 5998 calib->state = IWN_CALIB_STATE_INIT; 5999 calib->cck_state = IWN_CCK_STATE_HIFA; 6000 /* Set initial correlation values. */ 6001 calib->ofdm_x1 = sc->limits->min_ofdm_x1; 6002 calib->ofdm_mrc_x1 = sc->limits->min_ofdm_mrc_x1; 6003 calib->ofdm_x4 = sc->limits->min_ofdm_x4; 6004 calib->ofdm_mrc_x4 = sc->limits->min_ofdm_mrc_x4; 6005 calib->cck_x4 = 125; 6006 calib->cck_mrc_x4 = sc->limits->min_cck_mrc_x4; 6007 calib->energy_cck = sc->limits->energy_cck; 6008 6009 /* Write initial sensitivity. */ 6010 if ((error = iwn_send_sensitivity(sc)) != 0) 6011 return error; 6012 6013 /* Write initial gains. */ 6014 if ((error = ops->init_gains(sc)) != 0) 6015 return error; 6016 6017 /* Request statistics at each beacon interval. */ 6018 flags = 0; 6019 DPRINTF(sc, IWN_DEBUG_CALIBRATE, "%s: sending request for statistics\n", 6020 __func__); 6021 return iwn_cmd(sc, IWN_CMD_GET_STATISTICS, &flags, sizeof flags, 1); 6022 } 6023 6024 /* 6025 * Collect noise and RSSI statistics for the first 20 beacons received 6026 * after association and use them to determine connected antennas and 6027 * to set differential gains. 6028 */ 6029 static void 6030 iwn_collect_noise(struct iwn_softc *sc, 6031 const struct iwn_rx_general_stats *stats) 6032 { 6033 struct iwn_ops *ops = &sc->ops; 6034 struct iwn_calib_state *calib = &sc->calib; 6035 struct ieee80211com *ic = &sc->sc_ic; 6036 uint32_t val; 6037 int i; 6038 6039 DPRINTF(sc, IWN_DEBUG_TRACE, "->%s begin\n", __func__); 6040 6041 /* Accumulate RSSI and noise for all 3 antennas. */ 6042 for (i = 0; i < 3; i++) { 6043 calib->rssi[i] += le32toh(stats->rssi[i]) & 0xff; 6044 calib->noise[i] += le32toh(stats->noise[i]) & 0xff; 6045 } 6046 /* NB: We update differential gains only once after 20 beacons. */ 6047 if (++calib->nbeacons < 20) 6048 return; 6049 6050 /* Determine highest average RSSI. */ 6051 val = MAX(calib->rssi[0], calib->rssi[1]); 6052 val = MAX(calib->rssi[2], val); 6053 6054 /* Determine which antennas are connected. */ 6055 sc->chainmask = sc->rxchainmask; 6056 for (i = 0; i < 3; i++) 6057 if (val - calib->rssi[i] > 15 * 20) 6058 sc->chainmask &= ~(1 << i); 6059 DPRINTF(sc, IWN_DEBUG_CALIBRATE | IWN_DEBUG_XMIT, 6060 "%s: RX chains mask: theoretical=0x%x, actual=0x%x\n", 6061 __func__, sc->rxchainmask, sc->chainmask); 6062 6063 /* If none of the TX antennas are connected, keep at least one. */ 6064 if ((sc->chainmask & sc->txchainmask) == 0) 6065 sc->chainmask |= IWN_LSB(sc->txchainmask); 6066 6067 (void)ops->set_gains(sc); 6068 calib->state = IWN_CALIB_STATE_RUN; 6069 6070 #ifdef notyet 6071 /* XXX Disable RX chains with no antennas connected. */ 6072 sc->rxon->rxchain = htole16(IWN_RXCHAIN_SEL(sc->chainmask)); 6073 if (sc->sc_is_scanning) 6074 device_printf(sc->sc_dev, 6075 "%s: is_scanning set, before RXON\n", 6076 __func__); 6077 (void)iwn_cmd(sc, IWN_CMD_RXON, sc->rxon, sc->rxonsz, 1); 6078 #endif 6079 6080 /* Enable power-saving mode if requested by user. */ 6081 if (ic->ic_flags & IEEE80211_F_PMGTON) 6082 (void)iwn_set_pslevel(sc, 0, 3, 1); 6083 6084 DPRINTF(sc, IWN_DEBUG_TRACE, "->%s: end\n",__func__); 6085 6086 } 6087 6088 static int 6089 iwn4965_init_gains(struct iwn_softc *sc) 6090 { 6091 struct iwn_phy_calib_gain cmd; 6092 6093 DPRINTF(sc, IWN_DEBUG_TRACE, "->Doing %s\n", __func__); 6094 6095 memset(&cmd, 0, sizeof cmd); 6096 cmd.code = IWN4965_PHY_CALIB_DIFF_GAIN; 6097 /* Differential gains initially set to 0 for all 3 antennas. */ 6098 DPRINTF(sc, IWN_DEBUG_CALIBRATE, 6099 "%s: setting initial differential gains\n", __func__); 6100 return iwn_cmd(sc, IWN_CMD_PHY_CALIB, &cmd, sizeof cmd, 1); 6101 } 6102 6103 static int 6104 iwn5000_init_gains(struct iwn_softc *sc) 6105 { 6106 struct iwn_phy_calib cmd; 6107 6108 DPRINTF(sc, IWN_DEBUG_TRACE, "->Doing %s\n", __func__); 6109 6110 memset(&cmd, 0, sizeof cmd); 6111 cmd.code = sc->reset_noise_gain; 6112 cmd.ngroups = 1; 6113 cmd.isvalid = 1; 6114 DPRINTF(sc, IWN_DEBUG_CALIBRATE, 6115 "%s: setting initial differential gains\n", __func__); 6116 return iwn_cmd(sc, IWN_CMD_PHY_CALIB, &cmd, sizeof cmd, 1); 6117 } 6118 6119 static int 6120 iwn4965_set_gains(struct iwn_softc *sc) 6121 { 6122 struct iwn_calib_state *calib = &sc->calib; 6123 struct iwn_phy_calib_gain cmd; 6124 int i, delta, noise; 6125 6126 DPRINTF(sc, IWN_DEBUG_TRACE, "->Doing %s\n", __func__); 6127 6128 /* Get minimal noise among connected antennas. */ 6129 noise = INT_MAX; /* NB: There's at least one antenna. */ 6130 for (i = 0; i < 3; i++) 6131 if (sc->chainmask & (1 << i)) 6132 noise = MIN(calib->noise[i], noise); 6133 6134 memset(&cmd, 0, sizeof cmd); 6135 cmd.code = IWN4965_PHY_CALIB_DIFF_GAIN; 6136 /* Set differential gains for connected antennas. */ 6137 for (i = 0; i < 3; i++) { 6138 if (sc->chainmask & (1 << i)) { 6139 /* Compute attenuation (in unit of 1.5dB). */ 6140 delta = (noise - (int32_t)calib->noise[i]) / 30; 6141 /* NB: delta <= 0 */ 6142 /* Limit to [-4.5dB,0]. */ 6143 cmd.gain[i] = MIN(abs(delta), 3); 6144 if (delta < 0) 6145 cmd.gain[i] |= 1 << 2; /* sign bit */ 6146 } 6147 } 6148 DPRINTF(sc, IWN_DEBUG_CALIBRATE, 6149 "setting differential gains Ant A/B/C: %x/%x/%x (%x)\n", 6150 cmd.gain[0], cmd.gain[1], cmd.gain[2], sc->chainmask); 6151 return iwn_cmd(sc, IWN_CMD_PHY_CALIB, &cmd, sizeof cmd, 1); 6152 } 6153 6154 static int 6155 iwn5000_set_gains(struct iwn_softc *sc) 6156 { 6157 struct iwn_calib_state *calib = &sc->calib; 6158 struct iwn_phy_calib_gain cmd; 6159 int i, ant, div, delta; 6160 6161 DPRINTF(sc, IWN_DEBUG_TRACE, "->Doing %s\n", __func__); 6162 6163 /* We collected 20 beacons and !=6050 need a 1.5 factor. */ 6164 div = (sc->hw_type == IWN_HW_REV_TYPE_6050) ? 20 : 30; 6165 6166 memset(&cmd, 0, sizeof cmd); 6167 cmd.code = sc->noise_gain; 6168 cmd.ngroups = 1; 6169 cmd.isvalid = 1; 6170 /* Get first available RX antenna as referential. */ 6171 ant = IWN_LSB(sc->rxchainmask); 6172 /* Set differential gains for other antennas. */ 6173 for (i = ant + 1; i < 3; i++) { 6174 if (sc->chainmask & (1 << i)) { 6175 /* The delta is relative to antenna "ant". */ 6176 delta = ((int32_t)calib->noise[ant] - 6177 (int32_t)calib->noise[i]) / div; 6178 /* Limit to [-4.5dB,+4.5dB]. */ 6179 cmd.gain[i - 1] = MIN(abs(delta), 3); 6180 if (delta < 0) 6181 cmd.gain[i - 1] |= 1 << 2; /* sign bit */ 6182 } 6183 } 6184 DPRINTF(sc, IWN_DEBUG_CALIBRATE | IWN_DEBUG_XMIT, 6185 "setting differential gains Ant B/C: %x/%x (%x)\n", 6186 cmd.gain[0], cmd.gain[1], sc->chainmask); 6187 return iwn_cmd(sc, IWN_CMD_PHY_CALIB, &cmd, sizeof cmd, 1); 6188 } 6189 6190 /* 6191 * Tune RF RX sensitivity based on the number of false alarms detected 6192 * during the last beacon period. 6193 */ 6194 static void 6195 iwn_tune_sensitivity(struct iwn_softc *sc, const struct iwn_rx_stats *stats) 6196 { 6197 #define inc(val, inc, max) \ 6198 if ((val) < (max)) { \ 6199 if ((val) < (max) - (inc)) \ 6200 (val) += (inc); \ 6201 else \ 6202 (val) = (max); \ 6203 needs_update = 1; \ 6204 } 6205 #define dec(val, dec, min) \ 6206 if ((val) > (min)) { \ 6207 if ((val) > (min) + (dec)) \ 6208 (val) -= (dec); \ 6209 else \ 6210 (val) = (min); \ 6211 needs_update = 1; \ 6212 } 6213 6214 const struct iwn_sensitivity_limits *limits = sc->limits; 6215 struct iwn_calib_state *calib = &sc->calib; 6216 uint32_t val, rxena, fa; 6217 uint32_t energy[3], energy_min; 6218 uint8_t noise[3], noise_ref; 6219 int i, needs_update = 0; 6220 6221 DPRINTF(sc, IWN_DEBUG_TRACE, "->%s begin\n", __func__); 6222 6223 /* Check that we've been enabled long enough. */ 6224 if ((rxena = le32toh(stats->general.load)) == 0){ 6225 DPRINTF(sc, IWN_DEBUG_TRACE, "->%s end not so long\n", __func__); 6226 return; 6227 } 6228 6229 /* Compute number of false alarms since last call for OFDM. */ 6230 fa = le32toh(stats->ofdm.bad_plcp) - calib->bad_plcp_ofdm; 6231 fa += le32toh(stats->ofdm.fa) - calib->fa_ofdm; 6232 fa *= 200 * IEEE80211_DUR_TU; /* 200TU */ 6233 6234 if (fa > 50 * rxena) { 6235 /* High false alarm count, decrease sensitivity. */ 6236 DPRINTF(sc, IWN_DEBUG_CALIBRATE, 6237 "%s: OFDM high false alarm count: %u\n", __func__, fa); 6238 inc(calib->ofdm_x1, 1, limits->max_ofdm_x1); 6239 inc(calib->ofdm_mrc_x1, 1, limits->max_ofdm_mrc_x1); 6240 inc(calib->ofdm_x4, 1, limits->max_ofdm_x4); 6241 inc(calib->ofdm_mrc_x4, 1, limits->max_ofdm_mrc_x4); 6242 6243 } else if (fa < 5 * rxena) { 6244 /* Low false alarm count, increase sensitivity. */ 6245 DPRINTF(sc, IWN_DEBUG_CALIBRATE, 6246 "%s: OFDM low false alarm count: %u\n", __func__, fa); 6247 dec(calib->ofdm_x1, 1, limits->min_ofdm_x1); 6248 dec(calib->ofdm_mrc_x1, 1, limits->min_ofdm_mrc_x1); 6249 dec(calib->ofdm_x4, 1, limits->min_ofdm_x4); 6250 dec(calib->ofdm_mrc_x4, 1, limits->min_ofdm_mrc_x4); 6251 } 6252 6253 /* Compute maximum noise among 3 receivers. */ 6254 for (i = 0; i < 3; i++) 6255 noise[i] = (le32toh(stats->general.noise[i]) >> 8) & 0xff; 6256 val = MAX(noise[0], noise[1]); 6257 val = MAX(noise[2], val); 6258 /* Insert it into our samples table. */ 6259 calib->noise_samples[calib->cur_noise_sample] = val; 6260 calib->cur_noise_sample = (calib->cur_noise_sample + 1) % 20; 6261 6262 /* Compute maximum noise among last 20 samples. */ 6263 noise_ref = calib->noise_samples[0]; 6264 for (i = 1; i < 20; i++) 6265 noise_ref = MAX(noise_ref, calib->noise_samples[i]); 6266 6267 /* Compute maximum energy among 3 receivers. */ 6268 for (i = 0; i < 3; i++) 6269 energy[i] = le32toh(stats->general.energy[i]); 6270 val = MIN(energy[0], energy[1]); 6271 val = MIN(energy[2], val); 6272 /* Insert it into our samples table. */ 6273 calib->energy_samples[calib->cur_energy_sample] = val; 6274 calib->cur_energy_sample = (calib->cur_energy_sample + 1) % 10; 6275 6276 /* Compute minimum energy among last 10 samples. */ 6277 energy_min = calib->energy_samples[0]; 6278 for (i = 1; i < 10; i++) 6279 energy_min = MAX(energy_min, calib->energy_samples[i]); 6280 energy_min += 6; 6281 6282 /* Compute number of false alarms since last call for CCK. */ 6283 fa = le32toh(stats->cck.bad_plcp) - calib->bad_plcp_cck; 6284 fa += le32toh(stats->cck.fa) - calib->fa_cck; 6285 fa *= 200 * IEEE80211_DUR_TU; /* 200TU */ 6286 6287 if (fa > 50 * rxena) { 6288 /* High false alarm count, decrease sensitivity. */ 6289 DPRINTF(sc, IWN_DEBUG_CALIBRATE, 6290 "%s: CCK high false alarm count: %u\n", __func__, fa); 6291 calib->cck_state = IWN_CCK_STATE_HIFA; 6292 calib->low_fa = 0; 6293 6294 if (calib->cck_x4 > 160) { 6295 calib->noise_ref = noise_ref; 6296 if (calib->energy_cck > 2) 6297 dec(calib->energy_cck, 2, energy_min); 6298 } 6299 if (calib->cck_x4 < 160) { 6300 calib->cck_x4 = 161; 6301 needs_update = 1; 6302 } else 6303 inc(calib->cck_x4, 3, limits->max_cck_x4); 6304 6305 inc(calib->cck_mrc_x4, 3, limits->max_cck_mrc_x4); 6306 6307 } else if (fa < 5 * rxena) { 6308 /* Low false alarm count, increase sensitivity. */ 6309 DPRINTF(sc, IWN_DEBUG_CALIBRATE, 6310 "%s: CCK low false alarm count: %u\n", __func__, fa); 6311 calib->cck_state = IWN_CCK_STATE_LOFA; 6312 calib->low_fa++; 6313 6314 if (calib->cck_state != IWN_CCK_STATE_INIT && 6315 (((int32_t)calib->noise_ref - (int32_t)noise_ref) > 2 || 6316 calib->low_fa > 100)) { 6317 inc(calib->energy_cck, 2, limits->min_energy_cck); 6318 dec(calib->cck_x4, 3, limits->min_cck_x4); 6319 dec(calib->cck_mrc_x4, 3, limits->min_cck_mrc_x4); 6320 } 6321 } else { 6322 /* Not worth to increase or decrease sensitivity. */ 6323 DPRINTF(sc, IWN_DEBUG_CALIBRATE, 6324 "%s: CCK normal false alarm count: %u\n", __func__, fa); 6325 calib->low_fa = 0; 6326 calib->noise_ref = noise_ref; 6327 6328 if (calib->cck_state == IWN_CCK_STATE_HIFA) { 6329 /* Previous interval had many false alarms. */ 6330 dec(calib->energy_cck, 8, energy_min); 6331 } 6332 calib->cck_state = IWN_CCK_STATE_INIT; 6333 } 6334 6335 if (needs_update) 6336 (void)iwn_send_sensitivity(sc); 6337 6338 DPRINTF(sc, IWN_DEBUG_TRACE, "->%s: end\n",__func__); 6339 6340 #undef dec 6341 #undef inc 6342 } 6343 6344 static int 6345 iwn_send_sensitivity(struct iwn_softc *sc) 6346 { 6347 struct iwn_calib_state *calib = &sc->calib; 6348 struct iwn_enhanced_sensitivity_cmd cmd; 6349 int len; 6350 6351 memset(&cmd, 0, sizeof cmd); 6352 len = sizeof (struct iwn_sensitivity_cmd); 6353 cmd.which = IWN_SENSITIVITY_WORKTBL; 6354 /* OFDM modulation. */ 6355 cmd.corr_ofdm_x1 = htole16(calib->ofdm_x1); 6356 cmd.corr_ofdm_mrc_x1 = htole16(calib->ofdm_mrc_x1); 6357 cmd.corr_ofdm_x4 = htole16(calib->ofdm_x4); 6358 cmd.corr_ofdm_mrc_x4 = htole16(calib->ofdm_mrc_x4); 6359 cmd.energy_ofdm = htole16(sc->limits->energy_ofdm); 6360 cmd.energy_ofdm_th = htole16(62); 6361 /* CCK modulation. */ 6362 cmd.corr_cck_x4 = htole16(calib->cck_x4); 6363 cmd.corr_cck_mrc_x4 = htole16(calib->cck_mrc_x4); 6364 cmd.energy_cck = htole16(calib->energy_cck); 6365 /* Barker modulation: use default values. */ 6366 cmd.corr_barker = htole16(190); 6367 cmd.corr_barker_mrc = htole16(sc->limits->barker_mrc); 6368 6369 DPRINTF(sc, IWN_DEBUG_CALIBRATE, 6370 "%s: set sensitivity %d/%d/%d/%d/%d/%d/%d\n", __func__, 6371 calib->ofdm_x1, calib->ofdm_mrc_x1, calib->ofdm_x4, 6372 calib->ofdm_mrc_x4, calib->cck_x4, 6373 calib->cck_mrc_x4, calib->energy_cck); 6374 6375 if (!(sc->sc_flags & IWN_FLAG_ENH_SENS)) 6376 goto send; 6377 /* Enhanced sensitivity settings. */ 6378 len = sizeof (struct iwn_enhanced_sensitivity_cmd); 6379 cmd.ofdm_det_slope_mrc = htole16(668); 6380 cmd.ofdm_det_icept_mrc = htole16(4); 6381 cmd.ofdm_det_slope = htole16(486); 6382 cmd.ofdm_det_icept = htole16(37); 6383 cmd.cck_det_slope_mrc = htole16(853); 6384 cmd.cck_det_icept_mrc = htole16(4); 6385 cmd.cck_det_slope = htole16(476); 6386 cmd.cck_det_icept = htole16(99); 6387 send: 6388 return iwn_cmd(sc, IWN_CMD_SET_SENSITIVITY, &cmd, len, 1); 6389 } 6390 6391 /* 6392 * Look at the increase of PLCP errors over time; if it exceeds 6393 * a programmed threshold then trigger an RF retune. 6394 */ 6395 static void 6396 iwn_check_rx_recovery(struct iwn_softc *sc, struct iwn_stats *rs) 6397 { 6398 int32_t delta_ofdm, delta_ht, delta_cck; 6399 struct iwn_calib_state *calib = &sc->calib; 6400 int delta_ticks, cur_ticks; 6401 int delta_msec; 6402 int thresh; 6403 6404 /* 6405 * Calculate the difference between the current and 6406 * previous statistics. 6407 */ 6408 delta_cck = le32toh(rs->rx.cck.bad_plcp) - calib->bad_plcp_cck; 6409 delta_ofdm = le32toh(rs->rx.ofdm.bad_plcp) - calib->bad_plcp_ofdm; 6410 delta_ht = le32toh(rs->rx.ht.bad_plcp) - calib->bad_plcp_ht; 6411 6412 /* 6413 * Calculate the delta in time between successive statistics 6414 * messages. Yes, it can roll over; so we make sure that 6415 * this doesn't happen. 6416 * 6417 * XXX go figure out what to do about rollover 6418 * XXX go figure out what to do if ticks rolls over to -ve instead! 6419 * XXX go stab signed integer overflow undefined-ness in the face. 6420 */ 6421 cur_ticks = ticks; 6422 delta_ticks = cur_ticks - sc->last_calib_ticks; 6423 6424 /* 6425 * If any are negative, then the firmware likely reset; so just 6426 * bail. We'll pick this up next time. 6427 */ 6428 if (delta_cck < 0 || delta_ofdm < 0 || delta_ht < 0 || delta_ticks < 0) 6429 return; 6430 6431 /* 6432 * delta_ticks is in ticks; we need to convert it up to milliseconds 6433 * so we can do some useful math with it. 6434 */ 6435 delta_msec = ticks_to_msecs(delta_ticks); 6436 6437 /* 6438 * Calculate what our threshold is given the current delta_msec. 6439 */ 6440 thresh = sc->base_params->plcp_err_threshold * delta_msec; 6441 6442 DPRINTF(sc, IWN_DEBUG_STATE, 6443 "%s: time delta: %d; cck=%d, ofdm=%d, ht=%d, total=%d, thresh=%d\n", 6444 __func__, 6445 delta_msec, 6446 delta_cck, 6447 delta_ofdm, 6448 delta_ht, 6449 (delta_msec + delta_cck + delta_ofdm + delta_ht), 6450 thresh); 6451 6452 /* 6453 * If we need a retune, then schedule a single channel scan 6454 * to a channel that isn't the currently active one! 6455 * 6456 * The math from linux iwlwifi: 6457 * 6458 * if ((delta * 100 / msecs) > threshold) 6459 */ 6460 if (thresh > 0 && (delta_cck + delta_ofdm + delta_ht) * 100 > thresh) { 6461 DPRINTF(sc, IWN_DEBUG_ANY, 6462 "%s: PLCP error threshold raw (%d) comparison (%d) " 6463 "over limit (%d); retune!\n", 6464 __func__, 6465 (delta_cck + delta_ofdm + delta_ht), 6466 (delta_cck + delta_ofdm + delta_ht) * 100, 6467 thresh); 6468 } 6469 } 6470 6471 /* 6472 * Set STA mode power saving level (between 0 and 5). 6473 * Level 0 is CAM (Continuously Aware Mode), 5 is for maximum power saving. 6474 */ 6475 static int 6476 iwn_set_pslevel(struct iwn_softc *sc, int dtim, int level, int async) 6477 { 6478 struct iwn_pmgt_cmd cmd; 6479 const struct iwn_pmgt *pmgt; 6480 uint32_t max, skip_dtim; 6481 uint32_t reg; 6482 int i; 6483 6484 DPRINTF(sc, IWN_DEBUG_PWRSAVE, 6485 "%s: dtim=%d, level=%d, async=%d\n", 6486 __func__, 6487 dtim, 6488 level, 6489 async); 6490 6491 /* Select which PS parameters to use. */ 6492 if (dtim <= 2) 6493 pmgt = &iwn_pmgt[0][level]; 6494 else if (dtim <= 10) 6495 pmgt = &iwn_pmgt[1][level]; 6496 else 6497 pmgt = &iwn_pmgt[2][level]; 6498 6499 memset(&cmd, 0, sizeof cmd); 6500 if (level != 0) /* not CAM */ 6501 cmd.flags |= htole16(IWN_PS_ALLOW_SLEEP); 6502 if (level == 5) 6503 cmd.flags |= htole16(IWN_PS_FAST_PD); 6504 /* Retrieve PCIe Active State Power Management (ASPM). */ 6505 reg = pci_read_config(sc->sc_dev, sc->sc_cap_off + PCIER_LINK_CTL, 4); 6506 if (!(reg & PCIEM_LINK_CTL_ASPMC_L0S)) /* L0s Entry disabled. */ 6507 cmd.flags |= htole16(IWN_PS_PCI_PMGT); 6508 cmd.rxtimeout = htole32(pmgt->rxtimeout * 1024); 6509 cmd.txtimeout = htole32(pmgt->txtimeout * 1024); 6510 6511 if (dtim == 0) { 6512 dtim = 1; 6513 skip_dtim = 0; 6514 } else 6515 skip_dtim = pmgt->skip_dtim; 6516 if (skip_dtim != 0) { 6517 cmd.flags |= htole16(IWN_PS_SLEEP_OVER_DTIM); 6518 max = pmgt->intval[4]; 6519 if (max == (uint32_t)-1) 6520 max = dtim * (skip_dtim + 1); 6521 else if (max > dtim) 6522 max = rounddown(max, dtim); 6523 } else 6524 max = dtim; 6525 for (i = 0; i < 5; i++) 6526 cmd.intval[i] = htole32(MIN(max, pmgt->intval[i])); 6527 6528 DPRINTF(sc, IWN_DEBUG_RESET, "setting power saving level to %d\n", 6529 level); 6530 return iwn_cmd(sc, IWN_CMD_SET_POWER_MODE, &cmd, sizeof cmd, async); 6531 } 6532 6533 static int 6534 iwn_send_btcoex(struct iwn_softc *sc) 6535 { 6536 struct iwn_bluetooth cmd; 6537 6538 memset(&cmd, 0, sizeof cmd); 6539 cmd.flags = IWN_BT_COEX_CHAN_ANN | IWN_BT_COEX_BT_PRIO; 6540 cmd.lead_time = IWN_BT_LEAD_TIME_DEF; 6541 cmd.max_kill = IWN_BT_MAX_KILL_DEF; 6542 DPRINTF(sc, IWN_DEBUG_RESET, "%s: configuring bluetooth coexistence\n", 6543 __func__); 6544 return iwn_cmd(sc, IWN_CMD_BT_COEX, &cmd, sizeof(cmd), 0); 6545 } 6546 6547 static int 6548 iwn_send_advanced_btcoex(struct iwn_softc *sc) 6549 { 6550 static const uint32_t btcoex_3wire[12] = { 6551 0xaaaaaaaa, 0xaaaaaaaa, 0xaeaaaaaa, 0xaaaaaaaa, 6552 0xcc00ff28, 0x0000aaaa, 0xcc00aaaa, 0x0000aaaa, 6553 0xc0004000, 0x00004000, 0xf0005000, 0xf0005000, 6554 }; 6555 struct iwn6000_btcoex_config btconfig; 6556 struct iwn2000_btcoex_config btconfig2k; 6557 struct iwn_btcoex_priotable btprio; 6558 struct iwn_btcoex_prot btprot; 6559 int error, i; 6560 uint8_t flags; 6561 6562 memset(&btconfig, 0, sizeof btconfig); 6563 memset(&btconfig2k, 0, sizeof btconfig2k); 6564 6565 flags = IWN_BT_FLAG_COEX6000_MODE_3W << 6566 IWN_BT_FLAG_COEX6000_MODE_SHIFT; // Done as is in linux kernel 3.2 6567 6568 if (sc->base_params->bt_sco_disable) 6569 flags &= ~IWN_BT_FLAG_SYNC_2_BT_DISABLE; 6570 else 6571 flags |= IWN_BT_FLAG_SYNC_2_BT_DISABLE; 6572 6573 flags |= IWN_BT_FLAG_COEX6000_CHAN_INHIBITION; 6574 6575 /* Default flags result is 145 as old value */ 6576 6577 /* 6578 * Flags value has to be review. Values must change if we 6579 * which to disable it 6580 */ 6581 if (sc->base_params->bt_session_2) { 6582 btconfig2k.flags = flags; 6583 btconfig2k.max_kill = 5; 6584 btconfig2k.bt3_t7_timer = 1; 6585 btconfig2k.kill_ack = htole32(0xffff0000); 6586 btconfig2k.kill_cts = htole32(0xffff0000); 6587 btconfig2k.sample_time = 2; 6588 btconfig2k.bt3_t2_timer = 0xc; 6589 6590 for (i = 0; i < 12; i++) 6591 btconfig2k.lookup_table[i] = htole32(btcoex_3wire[i]); 6592 btconfig2k.valid = htole16(0xff); 6593 btconfig2k.prio_boost = htole32(0xf0); 6594 DPRINTF(sc, IWN_DEBUG_RESET, 6595 "%s: configuring advanced bluetooth coexistence" 6596 " session 2, flags : 0x%x\n", 6597 __func__, 6598 flags); 6599 error = iwn_cmd(sc, IWN_CMD_BT_COEX, &btconfig2k, 6600 sizeof(btconfig2k), 1); 6601 } else { 6602 btconfig.flags = flags; 6603 btconfig.max_kill = 5; 6604 btconfig.bt3_t7_timer = 1; 6605 btconfig.kill_ack = htole32(0xffff0000); 6606 btconfig.kill_cts = htole32(0xffff0000); 6607 btconfig.sample_time = 2; 6608 btconfig.bt3_t2_timer = 0xc; 6609 6610 for (i = 0; i < 12; i++) 6611 btconfig.lookup_table[i] = htole32(btcoex_3wire[i]); 6612 btconfig.valid = htole16(0xff); 6613 btconfig.prio_boost = 0xf0; 6614 DPRINTF(sc, IWN_DEBUG_RESET, 6615 "%s: configuring advanced bluetooth coexistence," 6616 " flags : 0x%x\n", 6617 __func__, 6618 flags); 6619 error = iwn_cmd(sc, IWN_CMD_BT_COEX, &btconfig, 6620 sizeof(btconfig), 1); 6621 } 6622 6623 if (error != 0) 6624 return error; 6625 6626 memset(&btprio, 0, sizeof btprio); 6627 btprio.calib_init1 = 0x6; 6628 btprio.calib_init2 = 0x7; 6629 btprio.calib_periodic_low1 = 0x2; 6630 btprio.calib_periodic_low2 = 0x3; 6631 btprio.calib_periodic_high1 = 0x4; 6632 btprio.calib_periodic_high2 = 0x5; 6633 btprio.dtim = 0x6; 6634 btprio.scan52 = 0x8; 6635 btprio.scan24 = 0xa; 6636 error = iwn_cmd(sc, IWN_CMD_BT_COEX_PRIOTABLE, &btprio, sizeof(btprio), 6637 1); 6638 if (error != 0) 6639 return error; 6640 6641 /* Force BT state machine change. */ 6642 memset(&btprot, 0, sizeof btprot); 6643 btprot.open = 1; 6644 btprot.type = 1; 6645 error = iwn_cmd(sc, IWN_CMD_BT_COEX_PROT, &btprot, sizeof(btprot), 1); 6646 if (error != 0) 6647 return error; 6648 btprot.open = 0; 6649 return iwn_cmd(sc, IWN_CMD_BT_COEX_PROT, &btprot, sizeof(btprot), 1); 6650 } 6651 6652 static int 6653 iwn5000_runtime_calib(struct iwn_softc *sc) 6654 { 6655 struct iwn5000_calib_config cmd; 6656 6657 memset(&cmd, 0, sizeof cmd); 6658 cmd.ucode.once.enable = 0xffffffff; 6659 cmd.ucode.once.start = IWN5000_CALIB_DC; 6660 DPRINTF(sc, IWN_DEBUG_CALIBRATE, 6661 "%s: configuring runtime calibration\n", __func__); 6662 return iwn_cmd(sc, IWN5000_CMD_CALIB_CONFIG, &cmd, sizeof(cmd), 0); 6663 } 6664 6665 static uint32_t 6666 iwn_get_rxon_ht_flags(struct iwn_softc *sc, struct ieee80211_channel *c) 6667 { 6668 struct ieee80211com *ic = &sc->sc_ic; 6669 uint32_t htflags = 0; 6670 6671 if (! IEEE80211_IS_CHAN_HT(c)) 6672 return (0); 6673 6674 htflags |= IWN_RXON_HT_PROTMODE(ic->ic_curhtprotmode); 6675 6676 if (IEEE80211_IS_CHAN_HT40(c)) { 6677 switch (ic->ic_curhtprotmode) { 6678 case IEEE80211_HTINFO_OPMODE_HT20PR: 6679 htflags |= IWN_RXON_HT_MODEPURE40; 6680 break; 6681 default: 6682 htflags |= IWN_RXON_HT_MODEMIXED; 6683 break; 6684 } 6685 } 6686 if (IEEE80211_IS_CHAN_HT40D(c)) 6687 htflags |= IWN_RXON_HT_HT40MINUS; 6688 6689 return (htflags); 6690 } 6691 6692 static int 6693 iwn_check_bss_filter(struct iwn_softc *sc) 6694 { 6695 return ((sc->rxon->filter & htole32(IWN_FILTER_BSS)) != 0); 6696 } 6697 6698 static int 6699 iwn4965_rxon_assoc(struct iwn_softc *sc, int async) 6700 { 6701 struct iwn4965_rxon_assoc cmd; 6702 struct iwn_rxon *rxon = sc->rxon; 6703 6704 cmd.flags = rxon->flags; 6705 cmd.filter = rxon->filter; 6706 cmd.ofdm_mask = rxon->ofdm_mask; 6707 cmd.cck_mask = rxon->cck_mask; 6708 cmd.ht_single_mask = rxon->ht_single_mask; 6709 cmd.ht_dual_mask = rxon->ht_dual_mask; 6710 cmd.rxchain = rxon->rxchain; 6711 cmd.reserved = 0; 6712 6713 return (iwn_cmd(sc, IWN_CMD_RXON_ASSOC, &cmd, sizeof(cmd), async)); 6714 } 6715 6716 static int 6717 iwn5000_rxon_assoc(struct iwn_softc *sc, int async) 6718 { 6719 struct iwn5000_rxon_assoc cmd; 6720 struct iwn_rxon *rxon = sc->rxon; 6721 6722 cmd.flags = rxon->flags; 6723 cmd.filter = rxon->filter; 6724 cmd.ofdm_mask = rxon->ofdm_mask; 6725 cmd.cck_mask = rxon->cck_mask; 6726 cmd.reserved1 = 0; 6727 cmd.ht_single_mask = rxon->ht_single_mask; 6728 cmd.ht_dual_mask = rxon->ht_dual_mask; 6729 cmd.ht_triple_mask = rxon->ht_triple_mask; 6730 cmd.reserved2 = 0; 6731 cmd.rxchain = rxon->rxchain; 6732 cmd.acquisition = rxon->acquisition; 6733 cmd.reserved3 = 0; 6734 6735 return (iwn_cmd(sc, IWN_CMD_RXON_ASSOC, &cmd, sizeof(cmd), async)); 6736 } 6737 6738 static int 6739 iwn_send_rxon(struct iwn_softc *sc, int assoc, int async) 6740 { 6741 struct iwn_ops *ops = &sc->ops; 6742 int error; 6743 6744 IWN_LOCK_ASSERT(sc); 6745 6746 if (assoc && iwn_check_bss_filter(sc) != 0) { 6747 error = ops->rxon_assoc(sc, async); 6748 if (error != 0) { 6749 device_printf(sc->sc_dev, 6750 "%s: RXON_ASSOC command failed, error %d\n", 6751 __func__, error); 6752 return (error); 6753 } 6754 } else { 6755 if (sc->sc_is_scanning) 6756 device_printf(sc->sc_dev, 6757 "%s: is_scanning set, before RXON\n", 6758 __func__); 6759 6760 error = iwn_cmd(sc, IWN_CMD_RXON, sc->rxon, sc->rxonsz, async); 6761 if (error != 0) { 6762 device_printf(sc->sc_dev, 6763 "%s: RXON command failed, error %d\n", 6764 __func__, error); 6765 return (error); 6766 } 6767 6768 /* 6769 * Reconfiguring RXON clears the firmware nodes table so 6770 * we must add the broadcast node again. 6771 */ 6772 if (iwn_check_bss_filter(sc) == 0 && 6773 (error = iwn_add_broadcast_node(sc, async)) != 0) { 6774 device_printf(sc->sc_dev, 6775 "%s: could not add broadcast node, error %d\n", 6776 __func__, error); 6777 return (error); 6778 } 6779 } 6780 6781 /* Configuration has changed, set TX power accordingly. */ 6782 if ((error = ops->set_txpower(sc, async)) != 0) { 6783 device_printf(sc->sc_dev, 6784 "%s: could not set TX power, error %d\n", 6785 __func__, error); 6786 return (error); 6787 } 6788 6789 return (0); 6790 } 6791 6792 static int 6793 iwn_config(struct iwn_softc *sc) 6794 { 6795 struct ieee80211com *ic = &sc->sc_ic; 6796 struct ieee80211vap *vap = TAILQ_FIRST(&ic->ic_vaps); 6797 const uint8_t *macaddr; 6798 uint32_t txmask; 6799 uint16_t rxchain; 6800 int error; 6801 6802 DPRINTF(sc, IWN_DEBUG_TRACE, "->%s begin\n", __func__); 6803 6804 if ((sc->base_params->calib_need & IWN_FLG_NEED_PHY_CALIB_TEMP_OFFSET) 6805 && (sc->base_params->calib_need & IWN_FLG_NEED_PHY_CALIB_TEMP_OFFSETv2)) { 6806 device_printf(sc->sc_dev,"%s: temp_offset and temp_offsetv2 are" 6807 " exclusive each together. Review NIC config file. Conf" 6808 " : 0x%08x Flags : 0x%08x \n", __func__, 6809 sc->base_params->calib_need, 6810 (IWN_FLG_NEED_PHY_CALIB_TEMP_OFFSET | 6811 IWN_FLG_NEED_PHY_CALIB_TEMP_OFFSETv2)); 6812 return (EINVAL); 6813 } 6814 6815 /* Compute temperature calib if needed. Will be send by send calib */ 6816 if (sc->base_params->calib_need & IWN_FLG_NEED_PHY_CALIB_TEMP_OFFSET) { 6817 error = iwn5000_temp_offset_calib(sc); 6818 if (error != 0) { 6819 device_printf(sc->sc_dev, 6820 "%s: could not set temperature offset\n", __func__); 6821 return (error); 6822 } 6823 } else if (sc->base_params->calib_need & IWN_FLG_NEED_PHY_CALIB_TEMP_OFFSETv2) { 6824 error = iwn5000_temp_offset_calibv2(sc); 6825 if (error != 0) { 6826 device_printf(sc->sc_dev, 6827 "%s: could not compute temperature offset v2\n", 6828 __func__); 6829 return (error); 6830 } 6831 } 6832 6833 if (sc->hw_type == IWN_HW_REV_TYPE_6050) { 6834 /* Configure runtime DC calibration. */ 6835 error = iwn5000_runtime_calib(sc); 6836 if (error != 0) { 6837 device_printf(sc->sc_dev, 6838 "%s: could not configure runtime calibration\n", 6839 __func__); 6840 return error; 6841 } 6842 } 6843 6844 /* Configure valid TX chains for >=5000 Series. */ 6845 if (sc->hw_type != IWN_HW_REV_TYPE_4965 && 6846 IWN_UCODE_API(sc->ucode_rev) > 1) { 6847 txmask = htole32(sc->txchainmask); 6848 DPRINTF(sc, IWN_DEBUG_RESET | IWN_DEBUG_XMIT, 6849 "%s: configuring valid TX chains 0x%x\n", __func__, txmask); 6850 error = iwn_cmd(sc, IWN5000_CMD_TX_ANT_CONFIG, &txmask, 6851 sizeof txmask, 0); 6852 if (error != 0) { 6853 device_printf(sc->sc_dev, 6854 "%s: could not configure valid TX chains, " 6855 "error %d\n", __func__, error); 6856 return error; 6857 } 6858 } 6859 6860 /* Configure bluetooth coexistence. */ 6861 error = 0; 6862 6863 /* Configure bluetooth coexistence if needed. */ 6864 if (sc->base_params->bt_mode == IWN_BT_ADVANCED) 6865 error = iwn_send_advanced_btcoex(sc); 6866 if (sc->base_params->bt_mode == IWN_BT_SIMPLE) 6867 error = iwn_send_btcoex(sc); 6868 6869 if (error != 0) { 6870 device_printf(sc->sc_dev, 6871 "%s: could not configure bluetooth coexistence, error %d\n", 6872 __func__, error); 6873 return error; 6874 } 6875 6876 /* Set mode, channel, RX filter and enable RX. */ 6877 sc->rxon = &sc->rx_on[IWN_RXON_BSS_CTX]; 6878 memset(sc->rxon, 0, sizeof (struct iwn_rxon)); 6879 macaddr = vap ? vap->iv_myaddr : ic->ic_macaddr; 6880 IEEE80211_ADDR_COPY(sc->rxon->myaddr, macaddr); 6881 IEEE80211_ADDR_COPY(sc->rxon->wlap, macaddr); 6882 sc->rxon->chan = ieee80211_chan2ieee(ic, ic->ic_curchan); 6883 sc->rxon->flags = htole32(IWN_RXON_TSF | IWN_RXON_CTS_TO_SELF); 6884 if (IEEE80211_IS_CHAN_2GHZ(ic->ic_curchan)) 6885 sc->rxon->flags |= htole32(IWN_RXON_AUTO | IWN_RXON_24GHZ); 6886 6887 sc->rxon->filter = htole32(IWN_FILTER_MULTICAST); 6888 switch (ic->ic_opmode) { 6889 case IEEE80211_M_STA: 6890 sc->rxon->mode = IWN_MODE_STA; 6891 break; 6892 case IEEE80211_M_MONITOR: 6893 sc->rxon->mode = IWN_MODE_MONITOR; 6894 break; 6895 default: 6896 /* Should not get there. */ 6897 break; 6898 } 6899 iwn_set_promisc(sc); 6900 sc->rxon->cck_mask = 0x0f; /* not yet negotiated */ 6901 sc->rxon->ofdm_mask = 0xff; /* not yet negotiated */ 6902 sc->rxon->ht_single_mask = 0xff; 6903 sc->rxon->ht_dual_mask = 0xff; 6904 sc->rxon->ht_triple_mask = 0xff; 6905 /* 6906 * In active association mode, ensure that 6907 * all the receive chains are enabled. 6908 * 6909 * Since we're not yet doing SMPS, don't allow the 6910 * number of idle RX chains to be less than the active 6911 * number. 6912 */ 6913 rxchain = 6914 IWN_RXCHAIN_VALID(sc->rxchainmask) | 6915 IWN_RXCHAIN_MIMO_COUNT(sc->nrxchains) | 6916 IWN_RXCHAIN_IDLE_COUNT(sc->nrxchains); 6917 sc->rxon->rxchain = htole16(rxchain); 6918 DPRINTF(sc, IWN_DEBUG_RESET | IWN_DEBUG_XMIT, 6919 "%s: rxchainmask=0x%x, nrxchains=%d\n", 6920 __func__, 6921 sc->rxchainmask, 6922 sc->nrxchains); 6923 6924 sc->rxon->flags |= htole32(iwn_get_rxon_ht_flags(sc, ic->ic_curchan)); 6925 6926 DPRINTF(sc, IWN_DEBUG_RESET, 6927 "%s: setting configuration; flags=0x%08x\n", 6928 __func__, le32toh(sc->rxon->flags)); 6929 if ((error = iwn_send_rxon(sc, 0, 0)) != 0) { 6930 device_printf(sc->sc_dev, "%s: could not send RXON\n", 6931 __func__); 6932 return error; 6933 } 6934 6935 if ((error = iwn_set_critical_temp(sc)) != 0) { 6936 device_printf(sc->sc_dev, 6937 "%s: could not set critical temperature\n", __func__); 6938 return error; 6939 } 6940 6941 /* Set power saving level to CAM during initialization. */ 6942 if ((error = iwn_set_pslevel(sc, 0, 0, 0)) != 0) { 6943 device_printf(sc->sc_dev, 6944 "%s: could not set power saving level\n", __func__); 6945 return error; 6946 } 6947 6948 DPRINTF(sc, IWN_DEBUG_TRACE, "->%s: end\n",__func__); 6949 6950 return 0; 6951 } 6952 6953 static uint16_t 6954 iwn_get_active_dwell_time(struct iwn_softc *sc, 6955 struct ieee80211_channel *c, uint8_t n_probes) 6956 { 6957 /* No channel? Default to 2GHz settings */ 6958 if (c == NULL || IEEE80211_IS_CHAN_2GHZ(c)) { 6959 return (IWN_ACTIVE_DWELL_TIME_2GHZ + 6960 IWN_ACTIVE_DWELL_FACTOR_2GHZ * (n_probes + 1)); 6961 } 6962 6963 /* 5GHz dwell time */ 6964 return (IWN_ACTIVE_DWELL_TIME_5GHZ + 6965 IWN_ACTIVE_DWELL_FACTOR_5GHZ * (n_probes + 1)); 6966 } 6967 6968 /* 6969 * Limit the total dwell time to 85% of the beacon interval. 6970 * 6971 * Returns the dwell time in milliseconds. 6972 */ 6973 static uint16_t 6974 iwn_limit_dwell(struct iwn_softc *sc, uint16_t dwell_time) 6975 { 6976 struct ieee80211com *ic = &sc->sc_ic; 6977 struct ieee80211vap *vap = NULL; 6978 int bintval = 0; 6979 6980 /* bintval is in TU (1.024mS) */ 6981 if (! TAILQ_EMPTY(&ic->ic_vaps)) { 6982 vap = TAILQ_FIRST(&ic->ic_vaps); 6983 bintval = vap->iv_bss->ni_intval; 6984 } 6985 6986 /* 6987 * If it's non-zero, we should calculate the minimum of 6988 * it and the DWELL_BASE. 6989 * 6990 * XXX Yes, the math should take into account that bintval 6991 * is 1.024mS, not 1mS.. 6992 */ 6993 if (bintval > 0) { 6994 DPRINTF(sc, IWN_DEBUG_SCAN, 6995 "%s: bintval=%d\n", 6996 __func__, 6997 bintval); 6998 return (MIN(IWN_PASSIVE_DWELL_BASE, ((bintval * 85) / 100))); 6999 } 7000 7001 /* No association context? Default */ 7002 return (IWN_PASSIVE_DWELL_BASE); 7003 } 7004 7005 static uint16_t 7006 iwn_get_passive_dwell_time(struct iwn_softc *sc, struct ieee80211_channel *c) 7007 { 7008 uint16_t passive; 7009 7010 if (c == NULL || IEEE80211_IS_CHAN_2GHZ(c)) { 7011 passive = IWN_PASSIVE_DWELL_BASE + IWN_PASSIVE_DWELL_TIME_2GHZ; 7012 } else { 7013 passive = IWN_PASSIVE_DWELL_BASE + IWN_PASSIVE_DWELL_TIME_5GHZ; 7014 } 7015 7016 /* Clamp to the beacon interval if we're associated */ 7017 return (iwn_limit_dwell(sc, passive)); 7018 } 7019 7020 static int 7021 iwn_scan(struct iwn_softc *sc, struct ieee80211vap *vap, 7022 struct ieee80211_scan_state *ss, struct ieee80211_channel *c) 7023 { 7024 struct ieee80211com *ic = &sc->sc_ic; 7025 struct ieee80211_node *ni = vap->iv_bss; 7026 struct iwn_scan_hdr *hdr; 7027 struct iwn_cmd_data *tx; 7028 struct iwn_scan_essid *essid; 7029 struct iwn_scan_chan *chan; 7030 struct ieee80211_frame *wh; 7031 struct ieee80211_rateset *rs; 7032 uint8_t *buf, *frm; 7033 uint16_t rxchain; 7034 uint8_t txant; 7035 int buflen, error; 7036 int is_active; 7037 uint16_t dwell_active, dwell_passive; 7038 uint32_t extra, scan_service_time; 7039 7040 DPRINTF(sc, IWN_DEBUG_TRACE, "->%s begin\n", __func__); 7041 7042 /* 7043 * We are absolutely not allowed to send a scan command when another 7044 * scan command is pending. 7045 */ 7046 if (sc->sc_is_scanning) { 7047 device_printf(sc->sc_dev, "%s: called whilst scanning!\n", 7048 __func__); 7049 return (EAGAIN); 7050 } 7051 7052 /* Assign the scan channel */ 7053 c = ic->ic_curchan; 7054 7055 sc->rxon = &sc->rx_on[IWN_RXON_BSS_CTX]; 7056 buf = malloc(IWN_SCAN_MAXSZ, M_DEVBUF, M_NOWAIT | M_ZERO); 7057 if (buf == NULL) { 7058 device_printf(sc->sc_dev, 7059 "%s: could not allocate buffer for scan command\n", 7060 __func__); 7061 return ENOMEM; 7062 } 7063 hdr = (struct iwn_scan_hdr *)buf; 7064 /* 7065 * Move to the next channel if no frames are received within 10ms 7066 * after sending the probe request. 7067 */ 7068 hdr->quiet_time = htole16(10); /* timeout in milliseconds */ 7069 hdr->quiet_threshold = htole16(1); /* min # of packets */ 7070 /* 7071 * Max needs to be greater than active and passive and quiet! 7072 * It's also in microseconds! 7073 */ 7074 hdr->max_svc = htole32(250 * 1024); 7075 7076 /* 7077 * Reset scan: interval=100 7078 * Normal scan: interval=becaon interval 7079 * suspend_time: 100 (TU) 7080 * 7081 */ 7082 extra = (100 /* suspend_time */ / 100 /* beacon interval */) << 22; 7083 //scan_service_time = extra | ((100 /* susp */ % 100 /* int */) * 1024); 7084 scan_service_time = (4 << 22) | (100 * 1024); /* Hardcode for now! */ 7085 hdr->pause_svc = htole32(scan_service_time); 7086 7087 /* Select antennas for scanning. */ 7088 rxchain = 7089 IWN_RXCHAIN_VALID(sc->rxchainmask) | 7090 IWN_RXCHAIN_FORCE_MIMO_SEL(sc->rxchainmask) | 7091 IWN_RXCHAIN_DRIVER_FORCE; 7092 if (IEEE80211_IS_CHAN_A(c) && 7093 sc->hw_type == IWN_HW_REV_TYPE_4965) { 7094 /* Ant A must be avoided in 5GHz because of an HW bug. */ 7095 rxchain |= IWN_RXCHAIN_FORCE_SEL(IWN_ANT_B); 7096 } else /* Use all available RX antennas. */ 7097 rxchain |= IWN_RXCHAIN_FORCE_SEL(sc->rxchainmask); 7098 hdr->rxchain = htole16(rxchain); 7099 hdr->filter = htole32(IWN_FILTER_MULTICAST | IWN_FILTER_BEACON); 7100 7101 tx = (struct iwn_cmd_data *)(hdr + 1); 7102 tx->flags = htole32(IWN_TX_AUTO_SEQ); 7103 tx->id = sc->broadcast_id; 7104 tx->lifetime = htole32(IWN_LIFETIME_INFINITE); 7105 7106 if (IEEE80211_IS_CHAN_5GHZ(c)) { 7107 /* Send probe requests at 6Mbps. */ 7108 tx->rate = htole32(0xd); 7109 rs = &ic->ic_sup_rates[IEEE80211_MODE_11A]; 7110 } else { 7111 hdr->flags = htole32(IWN_RXON_24GHZ | IWN_RXON_AUTO); 7112 if (sc->hw_type == IWN_HW_REV_TYPE_4965 && 7113 sc->rxon->associd && sc->rxon->chan > 14) 7114 tx->rate = htole32(0xd); 7115 else { 7116 /* Send probe requests at 1Mbps. */ 7117 tx->rate = htole32(10 | IWN_RFLAG_CCK); 7118 } 7119 rs = &ic->ic_sup_rates[IEEE80211_MODE_11G]; 7120 } 7121 /* Use the first valid TX antenna. */ 7122 txant = IWN_LSB(sc->txchainmask); 7123 tx->rate |= htole32(IWN_RFLAG_ANT(txant)); 7124 7125 /* 7126 * Only do active scanning if we're announcing a probe request 7127 * for a given SSID (or more, if we ever add it to the driver.) 7128 */ 7129 is_active = 0; 7130 7131 /* 7132 * If we're scanning for a specific SSID, add it to the command. 7133 * 7134 * XXX maybe look at adding support for scanning multiple SSIDs? 7135 */ 7136 essid = (struct iwn_scan_essid *)(tx + 1); 7137 if (ss != NULL) { 7138 if (ss->ss_ssid[0].len != 0) { 7139 essid[0].id = IEEE80211_ELEMID_SSID; 7140 essid[0].len = ss->ss_ssid[0].len; 7141 memcpy(essid[0].data, ss->ss_ssid[0].ssid, ss->ss_ssid[0].len); 7142 } 7143 7144 DPRINTF(sc, IWN_DEBUG_SCAN, "%s: ssid_len=%d, ssid=%*s\n", 7145 __func__, 7146 ss->ss_ssid[0].len, 7147 ss->ss_ssid[0].len, 7148 ss->ss_ssid[0].ssid); 7149 7150 if (ss->ss_nssid > 0) 7151 is_active = 1; 7152 } 7153 7154 /* 7155 * Build a probe request frame. Most of the following code is a 7156 * copy & paste of what is done in net80211. 7157 */ 7158 wh = (struct ieee80211_frame *)(essid + 20); 7159 wh->i_fc[0] = IEEE80211_FC0_VERSION_0 | IEEE80211_FC0_TYPE_MGT | 7160 IEEE80211_FC0_SUBTYPE_PROBE_REQ; 7161 wh->i_fc[1] = IEEE80211_FC1_DIR_NODS; 7162 IEEE80211_ADDR_COPY(wh->i_addr1, vap->iv_ifp->if_broadcastaddr); 7163 IEEE80211_ADDR_COPY(wh->i_addr2, IF_LLADDR(vap->iv_ifp)); 7164 IEEE80211_ADDR_COPY(wh->i_addr3, vap->iv_ifp->if_broadcastaddr); 7165 *(uint16_t *)&wh->i_dur[0] = 0; /* filled by HW */ 7166 *(uint16_t *)&wh->i_seq[0] = 0; /* filled by HW */ 7167 7168 frm = (uint8_t *)(wh + 1); 7169 frm = ieee80211_add_ssid(frm, NULL, 0); 7170 frm = ieee80211_add_rates(frm, rs); 7171 if (rs->rs_nrates > IEEE80211_RATE_SIZE) 7172 frm = ieee80211_add_xrates(frm, rs); 7173 if (ic->ic_htcaps & IEEE80211_HTC_HT) 7174 frm = ieee80211_add_htcap(frm, ni); 7175 7176 /* Set length of probe request. */ 7177 tx->len = htole16(frm - (uint8_t *)wh); 7178 7179 /* 7180 * If active scanning is requested but a certain channel is 7181 * marked passive, we can do active scanning if we detect 7182 * transmissions. 7183 * 7184 * There is an issue with some firmware versions that triggers 7185 * a sysassert on a "good CRC threshold" of zero (== disabled), 7186 * on a radar channel even though this means that we should NOT 7187 * send probes. 7188 * 7189 * The "good CRC threshold" is the number of frames that we 7190 * need to receive during our dwell time on a channel before 7191 * sending out probes -- setting this to a huge value will 7192 * mean we never reach it, but at the same time work around 7193 * the aforementioned issue. Thus use IWL_GOOD_CRC_TH_NEVER 7194 * here instead of IWL_GOOD_CRC_TH_DISABLED. 7195 * 7196 * This was fixed in later versions along with some other 7197 * scan changes, and the threshold behaves as a flag in those 7198 * versions. 7199 */ 7200 7201 /* 7202 * If we're doing active scanning, set the crc_threshold 7203 * to a suitable value. This is different to active veruss 7204 * passive scanning depending upon the channel flags; the 7205 * firmware will obey that particular check for us. 7206 */ 7207 if (sc->tlv_feature_flags & IWN_UCODE_TLV_FLAGS_NEWSCAN) 7208 hdr->crc_threshold = is_active ? 7209 IWN_GOOD_CRC_TH_DEFAULT : IWN_GOOD_CRC_TH_DISABLED; 7210 else 7211 hdr->crc_threshold = is_active ? 7212 IWN_GOOD_CRC_TH_DEFAULT : IWN_GOOD_CRC_TH_NEVER; 7213 7214 chan = (struct iwn_scan_chan *)frm; 7215 chan->chan = htole16(ieee80211_chan2ieee(ic, c)); 7216 chan->flags = 0; 7217 if (ss->ss_nssid > 0) 7218 chan->flags |= htole32(IWN_CHAN_NPBREQS(1)); 7219 chan->dsp_gain = 0x6e; 7220 7221 /* 7222 * Set the passive/active flag depending upon the channel mode. 7223 * XXX TODO: take the is_active flag into account as well? 7224 */ 7225 if (c->ic_flags & IEEE80211_CHAN_PASSIVE) 7226 chan->flags |= htole32(IWN_CHAN_PASSIVE); 7227 else 7228 chan->flags |= htole32(IWN_CHAN_ACTIVE); 7229 7230 /* 7231 * Calculate the active/passive dwell times. 7232 */ 7233 7234 dwell_active = iwn_get_active_dwell_time(sc, c, ss->ss_nssid); 7235 dwell_passive = iwn_get_passive_dwell_time(sc, c); 7236 7237 /* Make sure they're valid */ 7238 if (dwell_passive <= dwell_active) 7239 dwell_passive = dwell_active + 1; 7240 7241 chan->active = htole16(dwell_active); 7242 chan->passive = htole16(dwell_passive); 7243 7244 if (IEEE80211_IS_CHAN_5GHZ(c)) 7245 chan->rf_gain = 0x3b; 7246 else 7247 chan->rf_gain = 0x28; 7248 7249 DPRINTF(sc, IWN_DEBUG_STATE, 7250 "%s: chan %u flags 0x%x rf_gain 0x%x " 7251 "dsp_gain 0x%x active %d passive %d scan_svc_time %d crc 0x%x " 7252 "isactive=%d numssid=%d\n", __func__, 7253 chan->chan, chan->flags, chan->rf_gain, chan->dsp_gain, 7254 dwell_active, dwell_passive, scan_service_time, 7255 hdr->crc_threshold, is_active, ss->ss_nssid); 7256 7257 hdr->nchan++; 7258 chan++; 7259 buflen = (uint8_t *)chan - buf; 7260 hdr->len = htole16(buflen); 7261 7262 if (sc->sc_is_scanning) { 7263 device_printf(sc->sc_dev, 7264 "%s: called with is_scanning set!\n", 7265 __func__); 7266 } 7267 sc->sc_is_scanning = 1; 7268 7269 DPRINTF(sc, IWN_DEBUG_STATE, "sending scan command nchan=%d\n", 7270 hdr->nchan); 7271 error = iwn_cmd(sc, IWN_CMD_SCAN, buf, buflen, 1); 7272 free(buf, M_DEVBUF); 7273 if (error == 0) 7274 callout_reset(&sc->scan_timeout, 5*hz, iwn_scan_timeout, sc); 7275 7276 DPRINTF(sc, IWN_DEBUG_TRACE, "->%s: end\n",__func__); 7277 7278 return error; 7279 } 7280 7281 static int 7282 iwn_auth(struct iwn_softc *sc, struct ieee80211vap *vap) 7283 { 7284 struct ieee80211com *ic = &sc->sc_ic; 7285 struct ieee80211_node *ni = vap->iv_bss; 7286 int error; 7287 7288 DPRINTF(sc, IWN_DEBUG_TRACE, "->%s begin\n", __func__); 7289 7290 sc->rxon = &sc->rx_on[IWN_RXON_BSS_CTX]; 7291 /* Update adapter configuration. */ 7292 IEEE80211_ADDR_COPY(sc->rxon->bssid, ni->ni_bssid); 7293 sc->rxon->chan = ieee80211_chan2ieee(ic, ni->ni_chan); 7294 sc->rxon->flags = htole32(IWN_RXON_TSF | IWN_RXON_CTS_TO_SELF); 7295 if (IEEE80211_IS_CHAN_2GHZ(ni->ni_chan)) 7296 sc->rxon->flags |= htole32(IWN_RXON_AUTO | IWN_RXON_24GHZ); 7297 if (ic->ic_flags & IEEE80211_F_SHSLOT) 7298 sc->rxon->flags |= htole32(IWN_RXON_SHSLOT); 7299 if (ic->ic_flags & IEEE80211_F_SHPREAMBLE) 7300 sc->rxon->flags |= htole32(IWN_RXON_SHPREAMBLE); 7301 if (IEEE80211_IS_CHAN_A(ni->ni_chan)) { 7302 sc->rxon->cck_mask = 0; 7303 sc->rxon->ofdm_mask = 0x15; 7304 } else if (IEEE80211_IS_CHAN_B(ni->ni_chan)) { 7305 sc->rxon->cck_mask = 0x03; 7306 sc->rxon->ofdm_mask = 0; 7307 } else { 7308 /* Assume 802.11b/g. */ 7309 sc->rxon->cck_mask = 0x03; 7310 sc->rxon->ofdm_mask = 0x15; 7311 } 7312 7313 /* try HT */ 7314 sc->rxon->flags |= htole32(iwn_get_rxon_ht_flags(sc, ic->ic_curchan)); 7315 7316 DPRINTF(sc, IWN_DEBUG_STATE, "rxon chan %d flags %x cck %x ofdm %x\n", 7317 sc->rxon->chan, sc->rxon->flags, sc->rxon->cck_mask, 7318 sc->rxon->ofdm_mask); 7319 7320 if ((error = iwn_send_rxon(sc, 0, 1)) != 0) { 7321 device_printf(sc->sc_dev, "%s: could not send RXON\n", 7322 __func__); 7323 return (error); 7324 } 7325 7326 DPRINTF(sc, IWN_DEBUG_TRACE, "->%s: end\n",__func__); 7327 7328 return (0); 7329 } 7330 7331 static int 7332 iwn_run(struct iwn_softc *sc, struct ieee80211vap *vap) 7333 { 7334 struct iwn_ops *ops = &sc->ops; 7335 struct ieee80211com *ic = &sc->sc_ic; 7336 struct ieee80211_node *ni = vap->iv_bss; 7337 struct iwn_node_info node; 7338 int error; 7339 7340 DPRINTF(sc, IWN_DEBUG_TRACE, "->%s begin\n", __func__); 7341 7342 sc->rxon = &sc->rx_on[IWN_RXON_BSS_CTX]; 7343 if (ic->ic_opmode == IEEE80211_M_MONITOR) { 7344 /* Link LED blinks while monitoring. */ 7345 iwn_set_led(sc, IWN_LED_LINK, 5, 5); 7346 return 0; 7347 } 7348 if ((error = iwn_set_timing(sc, ni)) != 0) { 7349 device_printf(sc->sc_dev, 7350 "%s: could not set timing, error %d\n", __func__, error); 7351 return error; 7352 } 7353 7354 /* Update adapter configuration. */ 7355 IEEE80211_ADDR_COPY(sc->rxon->bssid, ni->ni_bssid); 7356 sc->rxon->associd = htole16(IEEE80211_AID(ni->ni_associd)); 7357 sc->rxon->chan = ieee80211_chan2ieee(ic, ni->ni_chan); 7358 sc->rxon->flags = htole32(IWN_RXON_TSF | IWN_RXON_CTS_TO_SELF); 7359 if (IEEE80211_IS_CHAN_2GHZ(ni->ni_chan)) 7360 sc->rxon->flags |= htole32(IWN_RXON_AUTO | IWN_RXON_24GHZ); 7361 if (ic->ic_flags & IEEE80211_F_SHSLOT) 7362 sc->rxon->flags |= htole32(IWN_RXON_SHSLOT); 7363 if (ic->ic_flags & IEEE80211_F_SHPREAMBLE) 7364 sc->rxon->flags |= htole32(IWN_RXON_SHPREAMBLE); 7365 if (IEEE80211_IS_CHAN_A(ni->ni_chan)) { 7366 sc->rxon->cck_mask = 0; 7367 sc->rxon->ofdm_mask = 0x15; 7368 } else if (IEEE80211_IS_CHAN_B(ni->ni_chan)) { 7369 sc->rxon->cck_mask = 0x03; 7370 sc->rxon->ofdm_mask = 0; 7371 } else { 7372 /* Assume 802.11b/g. */ 7373 sc->rxon->cck_mask = 0x0f; 7374 sc->rxon->ofdm_mask = 0x15; 7375 } 7376 /* try HT */ 7377 sc->rxon->flags |= htole32(iwn_get_rxon_ht_flags(sc, ni->ni_chan)); 7378 sc->rxon->filter |= htole32(IWN_FILTER_BSS); 7379 DPRINTF(sc, IWN_DEBUG_STATE, "rxon chan %d flags %x, curhtprotmode=%d\n", 7380 sc->rxon->chan, le32toh(sc->rxon->flags), ic->ic_curhtprotmode); 7381 7382 if ((error = iwn_send_rxon(sc, 0, 1)) != 0) { 7383 device_printf(sc->sc_dev, "%s: could not send RXON\n", 7384 __func__); 7385 return error; 7386 } 7387 7388 /* Fake a join to initialize the TX rate. */ 7389 ((struct iwn_node *)ni)->id = IWN_ID_BSS; 7390 iwn_newassoc(ni, 1); 7391 7392 /* Add BSS node. */ 7393 memset(&node, 0, sizeof node); 7394 IEEE80211_ADDR_COPY(node.macaddr, ni->ni_macaddr); 7395 node.id = IWN_ID_BSS; 7396 if (IEEE80211_IS_CHAN_HT(ni->ni_chan)) { 7397 switch (ni->ni_htcap & IEEE80211_HTCAP_SMPS) { 7398 case IEEE80211_HTCAP_SMPS_ENA: 7399 node.htflags |= htole32(IWN_SMPS_MIMO_DIS); 7400 break; 7401 case IEEE80211_HTCAP_SMPS_DYNAMIC: 7402 node.htflags |= htole32(IWN_SMPS_MIMO_PROT); 7403 break; 7404 } 7405 node.htflags |= htole32(IWN_AMDPU_SIZE_FACTOR(3) | 7406 IWN_AMDPU_DENSITY(5)); /* 4us */ 7407 if (IEEE80211_IS_CHAN_HT40(ni->ni_chan)) 7408 node.htflags |= htole32(IWN_NODE_HT40); 7409 } 7410 DPRINTF(sc, IWN_DEBUG_STATE, "%s: adding BSS node\n", __func__); 7411 error = ops->add_node(sc, &node, 1); 7412 if (error != 0) { 7413 device_printf(sc->sc_dev, 7414 "%s: could not add BSS node, error %d\n", __func__, error); 7415 return error; 7416 } 7417 DPRINTF(sc, IWN_DEBUG_STATE, "%s: setting link quality for node %d\n", 7418 __func__, node.id); 7419 if ((error = iwn_set_link_quality(sc, ni)) != 0) { 7420 device_printf(sc->sc_dev, 7421 "%s: could not setup link quality for node %d, error %d\n", 7422 __func__, node.id, error); 7423 return error; 7424 } 7425 7426 if ((error = iwn_init_sensitivity(sc)) != 0) { 7427 device_printf(sc->sc_dev, 7428 "%s: could not set sensitivity, error %d\n", __func__, 7429 error); 7430 return error; 7431 } 7432 /* Start periodic calibration timer. */ 7433 sc->calib.state = IWN_CALIB_STATE_ASSOC; 7434 sc->calib_cnt = 0; 7435 callout_reset(&sc->calib_to, msecs_to_ticks(500), iwn_calib_timeout, 7436 sc); 7437 7438 /* Link LED always on while associated. */ 7439 iwn_set_led(sc, IWN_LED_LINK, 0, 1); 7440 7441 DPRINTF(sc, IWN_DEBUG_TRACE, "->%s: end\n",__func__); 7442 7443 return 0; 7444 } 7445 7446 /* 7447 * This function is called by upper layer when an ADDBA request is received 7448 * from another STA and before the ADDBA response is sent. 7449 */ 7450 static int 7451 iwn_ampdu_rx_start(struct ieee80211_node *ni, struct ieee80211_rx_ampdu *rap, 7452 int baparamset, int batimeout, int baseqctl) 7453 { 7454 #define MS(_v, _f) (((_v) & _f) >> _f##_S) 7455 struct iwn_softc *sc = ni->ni_ic->ic_softc; 7456 struct iwn_ops *ops = &sc->ops; 7457 struct iwn_node *wn = (void *)ni; 7458 struct iwn_node_info node; 7459 uint16_t ssn; 7460 uint8_t tid; 7461 int error; 7462 7463 DPRINTF(sc, IWN_DEBUG_TRACE, "->Doing %s\n", __func__); 7464 7465 tid = MS(le16toh(baparamset), IEEE80211_BAPS_TID); 7466 ssn = MS(le16toh(baseqctl), IEEE80211_BASEQ_START); 7467 7468 if (wn->id == IWN_ID_UNDEFINED) 7469 return (ENOENT); 7470 7471 memset(&node, 0, sizeof node); 7472 node.id = wn->id; 7473 node.control = IWN_NODE_UPDATE; 7474 node.flags = IWN_FLAG_SET_ADDBA; 7475 node.addba_tid = tid; 7476 node.addba_ssn = htole16(ssn); 7477 DPRINTF(sc, IWN_DEBUG_RECV, "ADDBA RA=%d TID=%d SSN=%d\n", 7478 wn->id, tid, ssn); 7479 error = ops->add_node(sc, &node, 1); 7480 if (error != 0) 7481 return error; 7482 return sc->sc_ampdu_rx_start(ni, rap, baparamset, batimeout, baseqctl); 7483 #undef MS 7484 } 7485 7486 /* 7487 * This function is called by upper layer on teardown of an HT-immediate 7488 * Block Ack agreement (eg. uppon receipt of a DELBA frame). 7489 */ 7490 static void 7491 iwn_ampdu_rx_stop(struct ieee80211_node *ni, struct ieee80211_rx_ampdu *rap) 7492 { 7493 struct ieee80211com *ic = ni->ni_ic; 7494 struct iwn_softc *sc = ic->ic_softc; 7495 struct iwn_ops *ops = &sc->ops; 7496 struct iwn_node *wn = (void *)ni; 7497 struct iwn_node_info node; 7498 uint8_t tid; 7499 7500 DPRINTF(sc, IWN_DEBUG_TRACE, "->Doing %s\n", __func__); 7501 7502 if (wn->id == IWN_ID_UNDEFINED) 7503 goto end; 7504 7505 /* XXX: tid as an argument */ 7506 for (tid = 0; tid < WME_NUM_TID; tid++) { 7507 if (&ni->ni_rx_ampdu[tid] == rap) 7508 break; 7509 } 7510 7511 memset(&node, 0, sizeof node); 7512 node.id = wn->id; 7513 node.control = IWN_NODE_UPDATE; 7514 node.flags = IWN_FLAG_SET_DELBA; 7515 node.delba_tid = tid; 7516 DPRINTF(sc, IWN_DEBUG_RECV, "DELBA RA=%d TID=%d\n", wn->id, tid); 7517 (void)ops->add_node(sc, &node, 1); 7518 end: 7519 sc->sc_ampdu_rx_stop(ni, rap); 7520 } 7521 7522 static int 7523 iwn_addba_request(struct ieee80211_node *ni, struct ieee80211_tx_ampdu *tap, 7524 int dialogtoken, int baparamset, int batimeout) 7525 { 7526 struct iwn_softc *sc = ni->ni_ic->ic_softc; 7527 int qid; 7528 7529 DPRINTF(sc, IWN_DEBUG_TRACE, "->Doing %s\n", __func__); 7530 7531 for (qid = sc->firstaggqueue; qid < sc->ntxqs; qid++) { 7532 if (sc->qid2tap[qid] == NULL) 7533 break; 7534 } 7535 if (qid == sc->ntxqs) { 7536 DPRINTF(sc, IWN_DEBUG_XMIT, "%s: not free aggregation queue\n", 7537 __func__); 7538 return 0; 7539 } 7540 tap->txa_private = malloc(sizeof(int), M_DEVBUF, M_NOWAIT); 7541 if (tap->txa_private == NULL) { 7542 device_printf(sc->sc_dev, 7543 "%s: failed to alloc TX aggregation structure\n", __func__); 7544 return 0; 7545 } 7546 sc->qid2tap[qid] = tap; 7547 *(int *)tap->txa_private = qid; 7548 return sc->sc_addba_request(ni, tap, dialogtoken, baparamset, 7549 batimeout); 7550 } 7551 7552 static int 7553 iwn_addba_response(struct ieee80211_node *ni, struct ieee80211_tx_ampdu *tap, 7554 int code, int baparamset, int batimeout) 7555 { 7556 struct iwn_softc *sc = ni->ni_ic->ic_softc; 7557 int qid = *(int *)tap->txa_private; 7558 uint8_t tid = tap->txa_tid; 7559 int ret; 7560 7561 DPRINTF(sc, IWN_DEBUG_TRACE, "->Doing %s\n", __func__); 7562 7563 if (code == IEEE80211_STATUS_SUCCESS) { 7564 ni->ni_txseqs[tid] = tap->txa_start & 0xfff; 7565 ret = iwn_ampdu_tx_start(ni->ni_ic, ni, tid); 7566 if (ret != 1) 7567 return ret; 7568 } else { 7569 sc->qid2tap[qid] = NULL; 7570 free(tap->txa_private, M_DEVBUF); 7571 tap->txa_private = NULL; 7572 } 7573 return sc->sc_addba_response(ni, tap, code, baparamset, batimeout); 7574 } 7575 7576 /* 7577 * This function is called by upper layer when an ADDBA response is received 7578 * from another STA. 7579 */ 7580 static int 7581 iwn_ampdu_tx_start(struct ieee80211com *ic, struct ieee80211_node *ni, 7582 uint8_t tid) 7583 { 7584 struct ieee80211_tx_ampdu *tap = &ni->ni_tx_ampdu[tid]; 7585 struct iwn_softc *sc = ni->ni_ic->ic_softc; 7586 struct iwn_ops *ops = &sc->ops; 7587 struct iwn_node *wn = (void *)ni; 7588 struct iwn_node_info node; 7589 int error, qid; 7590 7591 DPRINTF(sc, IWN_DEBUG_TRACE, "->Doing %s\n", __func__); 7592 7593 if (wn->id == IWN_ID_UNDEFINED) 7594 return (0); 7595 7596 /* Enable TX for the specified RA/TID. */ 7597 wn->disable_tid &= ~(1 << tid); 7598 memset(&node, 0, sizeof node); 7599 node.id = wn->id; 7600 node.control = IWN_NODE_UPDATE; 7601 node.flags = IWN_FLAG_SET_DISABLE_TID; 7602 node.disable_tid = htole16(wn->disable_tid); 7603 error = ops->add_node(sc, &node, 1); 7604 if (error != 0) 7605 return 0; 7606 7607 if ((error = iwn_nic_lock(sc)) != 0) 7608 return 0; 7609 qid = *(int *)tap->txa_private; 7610 DPRINTF(sc, IWN_DEBUG_XMIT, "%s: ra=%d tid=%d ssn=%d qid=%d\n", 7611 __func__, wn->id, tid, tap->txa_start, qid); 7612 ops->ampdu_tx_start(sc, ni, qid, tid, tap->txa_start & 0xfff); 7613 iwn_nic_unlock(sc); 7614 7615 iwn_set_link_quality(sc, ni); 7616 return 1; 7617 } 7618 7619 static void 7620 iwn_ampdu_tx_stop(struct ieee80211_node *ni, struct ieee80211_tx_ampdu *tap) 7621 { 7622 struct iwn_softc *sc = ni->ni_ic->ic_softc; 7623 struct iwn_ops *ops = &sc->ops; 7624 uint8_t tid = tap->txa_tid; 7625 int qid; 7626 7627 DPRINTF(sc, IWN_DEBUG_TRACE, "->Doing %s\n", __func__); 7628 7629 sc->sc_addba_stop(ni, tap); 7630 7631 if (tap->txa_private == NULL) 7632 return; 7633 7634 qid = *(int *)tap->txa_private; 7635 if (sc->txq[qid].queued != 0) 7636 return; 7637 if (iwn_nic_lock(sc) != 0) 7638 return; 7639 ops->ampdu_tx_stop(sc, qid, tid, tap->txa_start & 0xfff); 7640 iwn_nic_unlock(sc); 7641 sc->qid2tap[qid] = NULL; 7642 free(tap->txa_private, M_DEVBUF); 7643 tap->txa_private = NULL; 7644 } 7645 7646 static void 7647 iwn4965_ampdu_tx_start(struct iwn_softc *sc, struct ieee80211_node *ni, 7648 int qid, uint8_t tid, uint16_t ssn) 7649 { 7650 struct iwn_node *wn = (void *)ni; 7651 7652 DPRINTF(sc, IWN_DEBUG_TRACE, "->Doing %s\n", __func__); 7653 7654 /* Stop TX scheduler while we're changing its configuration. */ 7655 iwn_prph_write(sc, IWN4965_SCHED_QUEUE_STATUS(qid), 7656 IWN4965_TXQ_STATUS_CHGACT); 7657 7658 /* Assign RA/TID translation to the queue. */ 7659 iwn_mem_write_2(sc, sc->sched_base + IWN4965_SCHED_TRANS_TBL(qid), 7660 wn->id << 4 | tid); 7661 7662 /* Enable chain-building mode for the queue. */ 7663 iwn_prph_setbits(sc, IWN4965_SCHED_QCHAIN_SEL, 1 << qid); 7664 7665 /* Set starting sequence number from the ADDBA request. */ 7666 sc->txq[qid].cur = sc->txq[qid].read = (ssn & 0xff); 7667 IWN_WRITE(sc, IWN_HBUS_TARG_WRPTR, qid << 8 | (ssn & 0xff)); 7668 iwn_prph_write(sc, IWN4965_SCHED_QUEUE_RDPTR(qid), ssn); 7669 7670 /* Set scheduler window size. */ 7671 iwn_mem_write(sc, sc->sched_base + IWN4965_SCHED_QUEUE_OFFSET(qid), 7672 IWN_SCHED_WINSZ); 7673 /* Set scheduler frame limit. */ 7674 iwn_mem_write(sc, sc->sched_base + IWN4965_SCHED_QUEUE_OFFSET(qid) + 4, 7675 IWN_SCHED_LIMIT << 16); 7676 7677 /* Enable interrupts for the queue. */ 7678 iwn_prph_setbits(sc, IWN4965_SCHED_INTR_MASK, 1 << qid); 7679 7680 /* Mark the queue as active. */ 7681 iwn_prph_write(sc, IWN4965_SCHED_QUEUE_STATUS(qid), 7682 IWN4965_TXQ_STATUS_ACTIVE | IWN4965_TXQ_STATUS_AGGR_ENA | 7683 iwn_tid2fifo[tid] << 1); 7684 } 7685 7686 static void 7687 iwn4965_ampdu_tx_stop(struct iwn_softc *sc, int qid, uint8_t tid, uint16_t ssn) 7688 { 7689 DPRINTF(sc, IWN_DEBUG_TRACE, "->Doing %s\n", __func__); 7690 7691 /* Stop TX scheduler while we're changing its configuration. */ 7692 iwn_prph_write(sc, IWN4965_SCHED_QUEUE_STATUS(qid), 7693 IWN4965_TXQ_STATUS_CHGACT); 7694 7695 /* Set starting sequence number from the ADDBA request. */ 7696 IWN_WRITE(sc, IWN_HBUS_TARG_WRPTR, qid << 8 | (ssn & 0xff)); 7697 iwn_prph_write(sc, IWN4965_SCHED_QUEUE_RDPTR(qid), ssn); 7698 7699 /* Disable interrupts for the queue. */ 7700 iwn_prph_clrbits(sc, IWN4965_SCHED_INTR_MASK, 1 << qid); 7701 7702 /* Mark the queue as inactive. */ 7703 iwn_prph_write(sc, IWN4965_SCHED_QUEUE_STATUS(qid), 7704 IWN4965_TXQ_STATUS_INACTIVE | iwn_tid2fifo[tid] << 1); 7705 } 7706 7707 static void 7708 iwn5000_ampdu_tx_start(struct iwn_softc *sc, struct ieee80211_node *ni, 7709 int qid, uint8_t tid, uint16_t ssn) 7710 { 7711 DPRINTF(sc, IWN_DEBUG_TRACE, "->Doing %s\n", __func__); 7712 7713 struct iwn_node *wn = (void *)ni; 7714 7715 /* Stop TX scheduler while we're changing its configuration. */ 7716 iwn_prph_write(sc, IWN5000_SCHED_QUEUE_STATUS(qid), 7717 IWN5000_TXQ_STATUS_CHGACT); 7718 7719 /* Assign RA/TID translation to the queue. */ 7720 iwn_mem_write_2(sc, sc->sched_base + IWN5000_SCHED_TRANS_TBL(qid), 7721 wn->id << 4 | tid); 7722 7723 /* Enable chain-building mode for the queue. */ 7724 iwn_prph_setbits(sc, IWN5000_SCHED_QCHAIN_SEL, 1 << qid); 7725 7726 /* Enable aggregation for the queue. */ 7727 iwn_prph_setbits(sc, IWN5000_SCHED_AGGR_SEL, 1 << qid); 7728 7729 /* Set starting sequence number from the ADDBA request. */ 7730 sc->txq[qid].cur = sc->txq[qid].read = (ssn & 0xff); 7731 IWN_WRITE(sc, IWN_HBUS_TARG_WRPTR, qid << 8 | (ssn & 0xff)); 7732 iwn_prph_write(sc, IWN5000_SCHED_QUEUE_RDPTR(qid), ssn); 7733 7734 /* Set scheduler window size and frame limit. */ 7735 iwn_mem_write(sc, sc->sched_base + IWN5000_SCHED_QUEUE_OFFSET(qid) + 4, 7736 IWN_SCHED_LIMIT << 16 | IWN_SCHED_WINSZ); 7737 7738 /* Enable interrupts for the queue. */ 7739 iwn_prph_setbits(sc, IWN5000_SCHED_INTR_MASK, 1 << qid); 7740 7741 /* Mark the queue as active. */ 7742 iwn_prph_write(sc, IWN5000_SCHED_QUEUE_STATUS(qid), 7743 IWN5000_TXQ_STATUS_ACTIVE | iwn_tid2fifo[tid]); 7744 } 7745 7746 static void 7747 iwn5000_ampdu_tx_stop(struct iwn_softc *sc, int qid, uint8_t tid, uint16_t ssn) 7748 { 7749 DPRINTF(sc, IWN_DEBUG_TRACE, "->Doing %s\n", __func__); 7750 7751 /* Stop TX scheduler while we're changing its configuration. */ 7752 iwn_prph_write(sc, IWN5000_SCHED_QUEUE_STATUS(qid), 7753 IWN5000_TXQ_STATUS_CHGACT); 7754 7755 /* Disable aggregation for the queue. */ 7756 iwn_prph_clrbits(sc, IWN5000_SCHED_AGGR_SEL, 1 << qid); 7757 7758 /* Set starting sequence number from the ADDBA request. */ 7759 IWN_WRITE(sc, IWN_HBUS_TARG_WRPTR, qid << 8 | (ssn & 0xff)); 7760 iwn_prph_write(sc, IWN5000_SCHED_QUEUE_RDPTR(qid), ssn); 7761 7762 /* Disable interrupts for the queue. */ 7763 iwn_prph_clrbits(sc, IWN5000_SCHED_INTR_MASK, 1 << qid); 7764 7765 /* Mark the queue as inactive. */ 7766 iwn_prph_write(sc, IWN5000_SCHED_QUEUE_STATUS(qid), 7767 IWN5000_TXQ_STATUS_INACTIVE | iwn_tid2fifo[tid]); 7768 } 7769 7770 /* 7771 * Query calibration tables from the initialization firmware. We do this 7772 * only once at first boot. Called from a process context. 7773 */ 7774 static int 7775 iwn5000_query_calibration(struct iwn_softc *sc) 7776 { 7777 struct iwn5000_calib_config cmd; 7778 int error; 7779 7780 memset(&cmd, 0, sizeof cmd); 7781 cmd.ucode.once.enable = htole32(0xffffffff); 7782 cmd.ucode.once.start = htole32(0xffffffff); 7783 cmd.ucode.once.send = htole32(0xffffffff); 7784 cmd.ucode.flags = htole32(0xffffffff); 7785 DPRINTF(sc, IWN_DEBUG_CALIBRATE, "%s: sending calibration query\n", 7786 __func__); 7787 error = iwn_cmd(sc, IWN5000_CMD_CALIB_CONFIG, &cmd, sizeof cmd, 0); 7788 if (error != 0) 7789 return error; 7790 7791 /* Wait at most two seconds for calibration to complete. */ 7792 if (!(sc->sc_flags & IWN_FLAG_CALIB_DONE)) 7793 error = msleep(sc, &sc->sc_mtx, PCATCH, "iwncal", 2 * hz); 7794 return error; 7795 } 7796 7797 /* 7798 * Send calibration results to the runtime firmware. These results were 7799 * obtained on first boot from the initialization firmware. 7800 */ 7801 static int 7802 iwn5000_send_calibration(struct iwn_softc *sc) 7803 { 7804 int idx, error; 7805 7806 for (idx = 0; idx < IWN5000_PHY_CALIB_MAX_RESULT; idx++) { 7807 if (!(sc->base_params->calib_need & (1<<idx))) { 7808 DPRINTF(sc, IWN_DEBUG_CALIBRATE, 7809 "No need of calib %d\n", 7810 idx); 7811 continue; /* no need for this calib */ 7812 } 7813 if (sc->calibcmd[idx].buf == NULL) { 7814 DPRINTF(sc, IWN_DEBUG_CALIBRATE, 7815 "Need calib idx : %d but no available data\n", 7816 idx); 7817 continue; 7818 } 7819 7820 DPRINTF(sc, IWN_DEBUG_CALIBRATE, 7821 "send calibration result idx=%d len=%d\n", idx, 7822 sc->calibcmd[idx].len); 7823 error = iwn_cmd(sc, IWN_CMD_PHY_CALIB, sc->calibcmd[idx].buf, 7824 sc->calibcmd[idx].len, 0); 7825 if (error != 0) { 7826 device_printf(sc->sc_dev, 7827 "%s: could not send calibration result, error %d\n", 7828 __func__, error); 7829 return error; 7830 } 7831 } 7832 return 0; 7833 } 7834 7835 static int 7836 iwn5000_send_wimax_coex(struct iwn_softc *sc) 7837 { 7838 struct iwn5000_wimax_coex wimax; 7839 7840 #if 0 7841 if (sc->hw_type == IWN_HW_REV_TYPE_6050) { 7842 /* Enable WiMAX coexistence for combo adapters. */ 7843 wimax.flags = 7844 IWN_WIMAX_COEX_ASSOC_WA_UNMASK | 7845 IWN_WIMAX_COEX_UNASSOC_WA_UNMASK | 7846 IWN_WIMAX_COEX_STA_TABLE_VALID | 7847 IWN_WIMAX_COEX_ENABLE; 7848 memcpy(wimax.events, iwn6050_wimax_events, 7849 sizeof iwn6050_wimax_events); 7850 } else 7851 #endif 7852 { 7853 /* Disable WiMAX coexistence. */ 7854 wimax.flags = 0; 7855 memset(wimax.events, 0, sizeof wimax.events); 7856 } 7857 DPRINTF(sc, IWN_DEBUG_RESET, "%s: Configuring WiMAX coexistence\n", 7858 __func__); 7859 return iwn_cmd(sc, IWN5000_CMD_WIMAX_COEX, &wimax, sizeof wimax, 0); 7860 } 7861 7862 static int 7863 iwn5000_crystal_calib(struct iwn_softc *sc) 7864 { 7865 struct iwn5000_phy_calib_crystal cmd; 7866 7867 memset(&cmd, 0, sizeof cmd); 7868 cmd.code = IWN5000_PHY_CALIB_CRYSTAL; 7869 cmd.ngroups = 1; 7870 cmd.isvalid = 1; 7871 cmd.cap_pin[0] = le32toh(sc->eeprom_crystal) & 0xff; 7872 cmd.cap_pin[1] = (le32toh(sc->eeprom_crystal) >> 16) & 0xff; 7873 DPRINTF(sc, IWN_DEBUG_CALIBRATE, "sending crystal calibration %d, %d\n", 7874 cmd.cap_pin[0], cmd.cap_pin[1]); 7875 return iwn_cmd(sc, IWN_CMD_PHY_CALIB, &cmd, sizeof cmd, 0); 7876 } 7877 7878 static int 7879 iwn5000_temp_offset_calib(struct iwn_softc *sc) 7880 { 7881 struct iwn5000_phy_calib_temp_offset cmd; 7882 7883 memset(&cmd, 0, sizeof cmd); 7884 cmd.code = IWN5000_PHY_CALIB_TEMP_OFFSET; 7885 cmd.ngroups = 1; 7886 cmd.isvalid = 1; 7887 if (sc->eeprom_temp != 0) 7888 cmd.offset = htole16(sc->eeprom_temp); 7889 else 7890 cmd.offset = htole16(IWN_DEFAULT_TEMP_OFFSET); 7891 DPRINTF(sc, IWN_DEBUG_CALIBRATE, "setting radio sensor offset to %d\n", 7892 le16toh(cmd.offset)); 7893 return iwn_cmd(sc, IWN_CMD_PHY_CALIB, &cmd, sizeof cmd, 0); 7894 } 7895 7896 static int 7897 iwn5000_temp_offset_calibv2(struct iwn_softc *sc) 7898 { 7899 struct iwn5000_phy_calib_temp_offsetv2 cmd; 7900 7901 memset(&cmd, 0, sizeof cmd); 7902 cmd.code = IWN5000_PHY_CALIB_TEMP_OFFSET; 7903 cmd.ngroups = 1; 7904 cmd.isvalid = 1; 7905 if (sc->eeprom_temp != 0) { 7906 cmd.offset_low = htole16(sc->eeprom_temp); 7907 cmd.offset_high = htole16(sc->eeprom_temp_high); 7908 } else { 7909 cmd.offset_low = htole16(IWN_DEFAULT_TEMP_OFFSET); 7910 cmd.offset_high = htole16(IWN_DEFAULT_TEMP_OFFSET); 7911 } 7912 cmd.burnt_voltage_ref = htole16(sc->eeprom_voltage); 7913 7914 DPRINTF(sc, IWN_DEBUG_CALIBRATE, 7915 "setting radio sensor low offset to %d, high offset to %d, voltage to %d\n", 7916 le16toh(cmd.offset_low), 7917 le16toh(cmd.offset_high), 7918 le16toh(cmd.burnt_voltage_ref)); 7919 7920 return iwn_cmd(sc, IWN_CMD_PHY_CALIB, &cmd, sizeof cmd, 0); 7921 } 7922 7923 /* 7924 * This function is called after the runtime firmware notifies us of its 7925 * readiness (called in a process context). 7926 */ 7927 static int 7928 iwn4965_post_alive(struct iwn_softc *sc) 7929 { 7930 int error, qid; 7931 7932 if ((error = iwn_nic_lock(sc)) != 0) 7933 return error; 7934 7935 DPRINTF(sc, IWN_DEBUG_TRACE, "->Doing %s\n", __func__); 7936 7937 /* Clear TX scheduler state in SRAM. */ 7938 sc->sched_base = iwn_prph_read(sc, IWN_SCHED_SRAM_ADDR); 7939 iwn_mem_set_region_4(sc, sc->sched_base + IWN4965_SCHED_CTX_OFF, 0, 7940 IWN4965_SCHED_CTX_LEN / sizeof (uint32_t)); 7941 7942 /* Set physical address of TX scheduler rings (1KB aligned). */ 7943 iwn_prph_write(sc, IWN4965_SCHED_DRAM_ADDR, sc->sched_dma.paddr >> 10); 7944 7945 IWN_SETBITS(sc, IWN_FH_TX_CHICKEN, IWN_FH_TX_CHICKEN_SCHED_RETRY); 7946 7947 /* Disable chain mode for all our 16 queues. */ 7948 iwn_prph_write(sc, IWN4965_SCHED_QCHAIN_SEL, 0); 7949 7950 for (qid = 0; qid < IWN4965_NTXQUEUES; qid++) { 7951 iwn_prph_write(sc, IWN4965_SCHED_QUEUE_RDPTR(qid), 0); 7952 IWN_WRITE(sc, IWN_HBUS_TARG_WRPTR, qid << 8 | 0); 7953 7954 /* Set scheduler window size. */ 7955 iwn_mem_write(sc, sc->sched_base + 7956 IWN4965_SCHED_QUEUE_OFFSET(qid), IWN_SCHED_WINSZ); 7957 /* Set scheduler frame limit. */ 7958 iwn_mem_write(sc, sc->sched_base + 7959 IWN4965_SCHED_QUEUE_OFFSET(qid) + 4, 7960 IWN_SCHED_LIMIT << 16); 7961 } 7962 7963 /* Enable interrupts for all our 16 queues. */ 7964 iwn_prph_write(sc, IWN4965_SCHED_INTR_MASK, 0xffff); 7965 /* Identify TX FIFO rings (0-7). */ 7966 iwn_prph_write(sc, IWN4965_SCHED_TXFACT, 0xff); 7967 7968 /* Mark TX rings (4 EDCA + cmd + 2 HCCA) as active. */ 7969 for (qid = 0; qid < 7; qid++) { 7970 static uint8_t qid2fifo[] = { 3, 2, 1, 0, 4, 5, 6 }; 7971 iwn_prph_write(sc, IWN4965_SCHED_QUEUE_STATUS(qid), 7972 IWN4965_TXQ_STATUS_ACTIVE | qid2fifo[qid] << 1); 7973 } 7974 iwn_nic_unlock(sc); 7975 return 0; 7976 } 7977 7978 /* 7979 * This function is called after the initialization or runtime firmware 7980 * notifies us of its readiness (called in a process context). 7981 */ 7982 static int 7983 iwn5000_post_alive(struct iwn_softc *sc) 7984 { 7985 int error, qid; 7986 7987 DPRINTF(sc, IWN_DEBUG_TRACE, "->%s begin\n", __func__); 7988 7989 /* Switch to using ICT interrupt mode. */ 7990 iwn5000_ict_reset(sc); 7991 7992 if ((error = iwn_nic_lock(sc)) != 0){ 7993 DPRINTF(sc, IWN_DEBUG_TRACE, "->%s end in error\n", __func__); 7994 return error; 7995 } 7996 7997 /* Clear TX scheduler state in SRAM. */ 7998 sc->sched_base = iwn_prph_read(sc, IWN_SCHED_SRAM_ADDR); 7999 iwn_mem_set_region_4(sc, sc->sched_base + IWN5000_SCHED_CTX_OFF, 0, 8000 IWN5000_SCHED_CTX_LEN / sizeof (uint32_t)); 8001 8002 /* Set physical address of TX scheduler rings (1KB aligned). */ 8003 iwn_prph_write(sc, IWN5000_SCHED_DRAM_ADDR, sc->sched_dma.paddr >> 10); 8004 8005 IWN_SETBITS(sc, IWN_FH_TX_CHICKEN, IWN_FH_TX_CHICKEN_SCHED_RETRY); 8006 8007 /* Enable chain mode for all queues, except command queue. */ 8008 if (sc->sc_flags & IWN_FLAG_PAN_SUPPORT) 8009 iwn_prph_write(sc, IWN5000_SCHED_QCHAIN_SEL, 0xfffdf); 8010 else 8011 iwn_prph_write(sc, IWN5000_SCHED_QCHAIN_SEL, 0xfffef); 8012 iwn_prph_write(sc, IWN5000_SCHED_AGGR_SEL, 0); 8013 8014 for (qid = 0; qid < IWN5000_NTXQUEUES; qid++) { 8015 iwn_prph_write(sc, IWN5000_SCHED_QUEUE_RDPTR(qid), 0); 8016 IWN_WRITE(sc, IWN_HBUS_TARG_WRPTR, qid << 8 | 0); 8017 8018 iwn_mem_write(sc, sc->sched_base + 8019 IWN5000_SCHED_QUEUE_OFFSET(qid), 0); 8020 /* Set scheduler window size and frame limit. */ 8021 iwn_mem_write(sc, sc->sched_base + 8022 IWN5000_SCHED_QUEUE_OFFSET(qid) + 4, 8023 IWN_SCHED_LIMIT << 16 | IWN_SCHED_WINSZ); 8024 } 8025 8026 /* Enable interrupts for all our 20 queues. */ 8027 iwn_prph_write(sc, IWN5000_SCHED_INTR_MASK, 0xfffff); 8028 /* Identify TX FIFO rings (0-7). */ 8029 iwn_prph_write(sc, IWN5000_SCHED_TXFACT, 0xff); 8030 8031 /* Mark TX rings (4 EDCA + cmd + 2 HCCA) as active. */ 8032 if (sc->sc_flags & IWN_FLAG_PAN_SUPPORT) { 8033 /* Mark TX rings as active. */ 8034 for (qid = 0; qid < 11; qid++) { 8035 static uint8_t qid2fifo[] = { 3, 2, 1, 0, 0, 4, 2, 5, 4, 7, 5 }; 8036 iwn_prph_write(sc, IWN5000_SCHED_QUEUE_STATUS(qid), 8037 IWN5000_TXQ_STATUS_ACTIVE | qid2fifo[qid]); 8038 } 8039 } else { 8040 /* Mark TX rings (4 EDCA + cmd + 2 HCCA) as active. */ 8041 for (qid = 0; qid < 7; qid++) { 8042 static uint8_t qid2fifo[] = { 3, 2, 1, 0, 7, 5, 6 }; 8043 iwn_prph_write(sc, IWN5000_SCHED_QUEUE_STATUS(qid), 8044 IWN5000_TXQ_STATUS_ACTIVE | qid2fifo[qid]); 8045 } 8046 } 8047 iwn_nic_unlock(sc); 8048 8049 /* Configure WiMAX coexistence for combo adapters. */ 8050 error = iwn5000_send_wimax_coex(sc); 8051 if (error != 0) { 8052 device_printf(sc->sc_dev, 8053 "%s: could not configure WiMAX coexistence, error %d\n", 8054 __func__, error); 8055 return error; 8056 } 8057 if (sc->hw_type != IWN_HW_REV_TYPE_5150) { 8058 /* Perform crystal calibration. */ 8059 error = iwn5000_crystal_calib(sc); 8060 if (error != 0) { 8061 device_printf(sc->sc_dev, 8062 "%s: crystal calibration failed, error %d\n", 8063 __func__, error); 8064 return error; 8065 } 8066 } 8067 if (!(sc->sc_flags & IWN_FLAG_CALIB_DONE)) { 8068 /* Query calibration from the initialization firmware. */ 8069 if ((error = iwn5000_query_calibration(sc)) != 0) { 8070 device_printf(sc->sc_dev, 8071 "%s: could not query calibration, error %d\n", 8072 __func__, error); 8073 return error; 8074 } 8075 /* 8076 * We have the calibration results now, reboot with the 8077 * runtime firmware (call ourselves recursively!) 8078 */ 8079 iwn_hw_stop(sc); 8080 error = iwn_hw_init(sc); 8081 } else { 8082 /* Send calibration results to runtime firmware. */ 8083 error = iwn5000_send_calibration(sc); 8084 } 8085 8086 DPRINTF(sc, IWN_DEBUG_TRACE, "->%s: end\n",__func__); 8087 8088 return error; 8089 } 8090 8091 /* 8092 * The firmware boot code is small and is intended to be copied directly into 8093 * the NIC internal memory (no DMA transfer). 8094 */ 8095 static int 8096 iwn4965_load_bootcode(struct iwn_softc *sc, const uint8_t *ucode, int size) 8097 { 8098 int error, ntries; 8099 8100 size /= sizeof (uint32_t); 8101 8102 if ((error = iwn_nic_lock(sc)) != 0) 8103 return error; 8104 8105 /* Copy microcode image into NIC memory. */ 8106 iwn_prph_write_region_4(sc, IWN_BSM_SRAM_BASE, 8107 (const uint32_t *)ucode, size); 8108 8109 iwn_prph_write(sc, IWN_BSM_WR_MEM_SRC, 0); 8110 iwn_prph_write(sc, IWN_BSM_WR_MEM_DST, IWN_FW_TEXT_BASE); 8111 iwn_prph_write(sc, IWN_BSM_WR_DWCOUNT, size); 8112 8113 /* Start boot load now. */ 8114 iwn_prph_write(sc, IWN_BSM_WR_CTRL, IWN_BSM_WR_CTRL_START); 8115 8116 /* Wait for transfer to complete. */ 8117 for (ntries = 0; ntries < 1000; ntries++) { 8118 if (!(iwn_prph_read(sc, IWN_BSM_WR_CTRL) & 8119 IWN_BSM_WR_CTRL_START)) 8120 break; 8121 DELAY(10); 8122 } 8123 if (ntries == 1000) { 8124 device_printf(sc->sc_dev, "%s: could not load boot firmware\n", 8125 __func__); 8126 iwn_nic_unlock(sc); 8127 return ETIMEDOUT; 8128 } 8129 8130 /* Enable boot after power up. */ 8131 iwn_prph_write(sc, IWN_BSM_WR_CTRL, IWN_BSM_WR_CTRL_START_EN); 8132 8133 iwn_nic_unlock(sc); 8134 return 0; 8135 } 8136 8137 static int 8138 iwn4965_load_firmware(struct iwn_softc *sc) 8139 { 8140 struct iwn_fw_info *fw = &sc->fw; 8141 struct iwn_dma_info *dma = &sc->fw_dma; 8142 int error; 8143 8144 /* Copy initialization sections into pre-allocated DMA-safe memory. */ 8145 memcpy(dma->vaddr, fw->init.data, fw->init.datasz); 8146 bus_dmamap_sync(dma->tag, dma->map, BUS_DMASYNC_PREWRITE); 8147 memcpy(dma->vaddr + IWN4965_FW_DATA_MAXSZ, 8148 fw->init.text, fw->init.textsz); 8149 bus_dmamap_sync(dma->tag, dma->map, BUS_DMASYNC_PREWRITE); 8150 8151 /* Tell adapter where to find initialization sections. */ 8152 if ((error = iwn_nic_lock(sc)) != 0) 8153 return error; 8154 iwn_prph_write(sc, IWN_BSM_DRAM_DATA_ADDR, dma->paddr >> 4); 8155 iwn_prph_write(sc, IWN_BSM_DRAM_DATA_SIZE, fw->init.datasz); 8156 iwn_prph_write(sc, IWN_BSM_DRAM_TEXT_ADDR, 8157 (dma->paddr + IWN4965_FW_DATA_MAXSZ) >> 4); 8158 iwn_prph_write(sc, IWN_BSM_DRAM_TEXT_SIZE, fw->init.textsz); 8159 iwn_nic_unlock(sc); 8160 8161 /* Load firmware boot code. */ 8162 error = iwn4965_load_bootcode(sc, fw->boot.text, fw->boot.textsz); 8163 if (error != 0) { 8164 device_printf(sc->sc_dev, "%s: could not load boot firmware\n", 8165 __func__); 8166 return error; 8167 } 8168 /* Now press "execute". */ 8169 IWN_WRITE(sc, IWN_RESET, 0); 8170 8171 /* Wait at most one second for first alive notification. */ 8172 if ((error = msleep(sc, &sc->sc_mtx, PCATCH, "iwninit", hz)) != 0) { 8173 device_printf(sc->sc_dev, 8174 "%s: timeout waiting for adapter to initialize, error %d\n", 8175 __func__, error); 8176 return error; 8177 } 8178 8179 /* Retrieve current temperature for initial TX power calibration. */ 8180 sc->rawtemp = sc->ucode_info.temp[3].chan20MHz; 8181 sc->temp = iwn4965_get_temperature(sc); 8182 8183 /* Copy runtime sections into pre-allocated DMA-safe memory. */ 8184 memcpy(dma->vaddr, fw->main.data, fw->main.datasz); 8185 bus_dmamap_sync(dma->tag, dma->map, BUS_DMASYNC_PREWRITE); 8186 memcpy(dma->vaddr + IWN4965_FW_DATA_MAXSZ, 8187 fw->main.text, fw->main.textsz); 8188 bus_dmamap_sync(dma->tag, dma->map, BUS_DMASYNC_PREWRITE); 8189 8190 /* Tell adapter where to find runtime sections. */ 8191 if ((error = iwn_nic_lock(sc)) != 0) 8192 return error; 8193 iwn_prph_write(sc, IWN_BSM_DRAM_DATA_ADDR, dma->paddr >> 4); 8194 iwn_prph_write(sc, IWN_BSM_DRAM_DATA_SIZE, fw->main.datasz); 8195 iwn_prph_write(sc, IWN_BSM_DRAM_TEXT_ADDR, 8196 (dma->paddr + IWN4965_FW_DATA_MAXSZ) >> 4); 8197 iwn_prph_write(sc, IWN_BSM_DRAM_TEXT_SIZE, 8198 IWN_FW_UPDATED | fw->main.textsz); 8199 iwn_nic_unlock(sc); 8200 8201 return 0; 8202 } 8203 8204 static int 8205 iwn5000_load_firmware_section(struct iwn_softc *sc, uint32_t dst, 8206 const uint8_t *section, int size) 8207 { 8208 struct iwn_dma_info *dma = &sc->fw_dma; 8209 int error; 8210 8211 DPRINTF(sc, IWN_DEBUG_TRACE, "->Doing %s\n", __func__); 8212 8213 /* Copy firmware section into pre-allocated DMA-safe memory. */ 8214 memcpy(dma->vaddr, section, size); 8215 bus_dmamap_sync(dma->tag, dma->map, BUS_DMASYNC_PREWRITE); 8216 8217 if ((error = iwn_nic_lock(sc)) != 0) 8218 return error; 8219 8220 IWN_WRITE(sc, IWN_FH_TX_CONFIG(IWN_SRVC_DMACHNL), 8221 IWN_FH_TX_CONFIG_DMA_PAUSE); 8222 8223 IWN_WRITE(sc, IWN_FH_SRAM_ADDR(IWN_SRVC_DMACHNL), dst); 8224 IWN_WRITE(sc, IWN_FH_TFBD_CTRL0(IWN_SRVC_DMACHNL), 8225 IWN_LOADDR(dma->paddr)); 8226 IWN_WRITE(sc, IWN_FH_TFBD_CTRL1(IWN_SRVC_DMACHNL), 8227 IWN_HIADDR(dma->paddr) << 28 | size); 8228 IWN_WRITE(sc, IWN_FH_TXBUF_STATUS(IWN_SRVC_DMACHNL), 8229 IWN_FH_TXBUF_STATUS_TBNUM(1) | 8230 IWN_FH_TXBUF_STATUS_TBIDX(1) | 8231 IWN_FH_TXBUF_STATUS_TFBD_VALID); 8232 8233 /* Kick Flow Handler to start DMA transfer. */ 8234 IWN_WRITE(sc, IWN_FH_TX_CONFIG(IWN_SRVC_DMACHNL), 8235 IWN_FH_TX_CONFIG_DMA_ENA | IWN_FH_TX_CONFIG_CIRQ_HOST_ENDTFD); 8236 8237 iwn_nic_unlock(sc); 8238 8239 /* Wait at most five seconds for FH DMA transfer to complete. */ 8240 return msleep(sc, &sc->sc_mtx, PCATCH, "iwninit", 5 * hz); 8241 } 8242 8243 static int 8244 iwn5000_load_firmware(struct iwn_softc *sc) 8245 { 8246 struct iwn_fw_part *fw; 8247 int error; 8248 8249 DPRINTF(sc, IWN_DEBUG_TRACE, "->Doing %s\n", __func__); 8250 8251 /* Load the initialization firmware on first boot only. */ 8252 fw = (sc->sc_flags & IWN_FLAG_CALIB_DONE) ? 8253 &sc->fw.main : &sc->fw.init; 8254 8255 error = iwn5000_load_firmware_section(sc, IWN_FW_TEXT_BASE, 8256 fw->text, fw->textsz); 8257 if (error != 0) { 8258 device_printf(sc->sc_dev, 8259 "%s: could not load firmware %s section, error %d\n", 8260 __func__, ".text", error); 8261 return error; 8262 } 8263 error = iwn5000_load_firmware_section(sc, IWN_FW_DATA_BASE, 8264 fw->data, fw->datasz); 8265 if (error != 0) { 8266 device_printf(sc->sc_dev, 8267 "%s: could not load firmware %s section, error %d\n", 8268 __func__, ".data", error); 8269 return error; 8270 } 8271 8272 /* Now press "execute". */ 8273 IWN_WRITE(sc, IWN_RESET, 0); 8274 return 0; 8275 } 8276 8277 /* 8278 * Extract text and data sections from a legacy firmware image. 8279 */ 8280 static int 8281 iwn_read_firmware_leg(struct iwn_softc *sc, struct iwn_fw_info *fw) 8282 { 8283 const uint32_t *ptr; 8284 size_t hdrlen = 24; 8285 uint32_t rev; 8286 8287 ptr = (const uint32_t *)fw->data; 8288 rev = le32toh(*ptr++); 8289 8290 sc->ucode_rev = rev; 8291 8292 /* Check firmware API version. */ 8293 if (IWN_FW_API(rev) <= 1) { 8294 device_printf(sc->sc_dev, 8295 "%s: bad firmware, need API version >=2\n", __func__); 8296 return EINVAL; 8297 } 8298 if (IWN_FW_API(rev) >= 3) { 8299 /* Skip build number (version 2 header). */ 8300 hdrlen += 4; 8301 ptr++; 8302 } 8303 if (fw->size < hdrlen) { 8304 device_printf(sc->sc_dev, "%s: firmware too short: %zu bytes\n", 8305 __func__, fw->size); 8306 return EINVAL; 8307 } 8308 fw->main.textsz = le32toh(*ptr++); 8309 fw->main.datasz = le32toh(*ptr++); 8310 fw->init.textsz = le32toh(*ptr++); 8311 fw->init.datasz = le32toh(*ptr++); 8312 fw->boot.textsz = le32toh(*ptr++); 8313 8314 /* Check that all firmware sections fit. */ 8315 if (fw->size < hdrlen + fw->main.textsz + fw->main.datasz + 8316 fw->init.textsz + fw->init.datasz + fw->boot.textsz) { 8317 device_printf(sc->sc_dev, "%s: firmware too short: %zu bytes\n", 8318 __func__, fw->size); 8319 return EINVAL; 8320 } 8321 8322 /* Get pointers to firmware sections. */ 8323 fw->main.text = (const uint8_t *)ptr; 8324 fw->main.data = fw->main.text + fw->main.textsz; 8325 fw->init.text = fw->main.data + fw->main.datasz; 8326 fw->init.data = fw->init.text + fw->init.textsz; 8327 fw->boot.text = fw->init.data + fw->init.datasz; 8328 return 0; 8329 } 8330 8331 /* 8332 * Extract text and data sections from a TLV firmware image. 8333 */ 8334 static int 8335 iwn_read_firmware_tlv(struct iwn_softc *sc, struct iwn_fw_info *fw, 8336 uint16_t alt) 8337 { 8338 const struct iwn_fw_tlv_hdr *hdr; 8339 const struct iwn_fw_tlv *tlv; 8340 const uint8_t *ptr, *end; 8341 uint64_t altmask; 8342 uint32_t len, tmp; 8343 8344 if (fw->size < sizeof (*hdr)) { 8345 device_printf(sc->sc_dev, "%s: firmware too short: %zu bytes\n", 8346 __func__, fw->size); 8347 return EINVAL; 8348 } 8349 hdr = (const struct iwn_fw_tlv_hdr *)fw->data; 8350 if (hdr->signature != htole32(IWN_FW_SIGNATURE)) { 8351 device_printf(sc->sc_dev, "%s: bad firmware signature 0x%08x\n", 8352 __func__, le32toh(hdr->signature)); 8353 return EINVAL; 8354 } 8355 DPRINTF(sc, IWN_DEBUG_RESET, "FW: \"%.64s\", build 0x%x\n", hdr->descr, 8356 le32toh(hdr->build)); 8357 sc->ucode_rev = le32toh(hdr->rev); 8358 8359 /* 8360 * Select the closest supported alternative that is less than 8361 * or equal to the specified one. 8362 */ 8363 altmask = le64toh(hdr->altmask); 8364 while (alt > 0 && !(altmask & (1ULL << alt))) 8365 alt--; /* Downgrade. */ 8366 DPRINTF(sc, IWN_DEBUG_RESET, "using alternative %d\n", alt); 8367 8368 ptr = (const uint8_t *)(hdr + 1); 8369 end = (const uint8_t *)(fw->data + fw->size); 8370 8371 /* Parse type-length-value fields. */ 8372 while (ptr + sizeof (*tlv) <= end) { 8373 tlv = (const struct iwn_fw_tlv *)ptr; 8374 len = le32toh(tlv->len); 8375 8376 ptr += sizeof (*tlv); 8377 if (ptr + len > end) { 8378 device_printf(sc->sc_dev, 8379 "%s: firmware too short: %zu bytes\n", __func__, 8380 fw->size); 8381 return EINVAL; 8382 } 8383 /* Skip other alternatives. */ 8384 if (tlv->alt != 0 && tlv->alt != htole16(alt)) 8385 goto next; 8386 8387 switch (le16toh(tlv->type)) { 8388 case IWN_FW_TLV_MAIN_TEXT: 8389 fw->main.text = ptr; 8390 fw->main.textsz = len; 8391 break; 8392 case IWN_FW_TLV_MAIN_DATA: 8393 fw->main.data = ptr; 8394 fw->main.datasz = len; 8395 break; 8396 case IWN_FW_TLV_INIT_TEXT: 8397 fw->init.text = ptr; 8398 fw->init.textsz = len; 8399 break; 8400 case IWN_FW_TLV_INIT_DATA: 8401 fw->init.data = ptr; 8402 fw->init.datasz = len; 8403 break; 8404 case IWN_FW_TLV_BOOT_TEXT: 8405 fw->boot.text = ptr; 8406 fw->boot.textsz = len; 8407 break; 8408 case IWN_FW_TLV_ENH_SENS: 8409 if (!len) 8410 sc->sc_flags |= IWN_FLAG_ENH_SENS; 8411 break; 8412 case IWN_FW_TLV_PHY_CALIB: 8413 tmp = le32toh(*ptr); 8414 if (tmp < 253) { 8415 sc->reset_noise_gain = tmp; 8416 sc->noise_gain = tmp + 1; 8417 } 8418 break; 8419 case IWN_FW_TLV_PAN: 8420 sc->sc_flags |= IWN_FLAG_PAN_SUPPORT; 8421 DPRINTF(sc, IWN_DEBUG_RESET, 8422 "PAN Support found: %d\n", 1); 8423 break; 8424 case IWN_FW_TLV_FLAGS: 8425 if (len < sizeof(uint32_t)) 8426 break; 8427 if (len % sizeof(uint32_t)) 8428 break; 8429 sc->tlv_feature_flags = le32toh(*ptr); 8430 DPRINTF(sc, IWN_DEBUG_RESET, 8431 "%s: feature: 0x%08x\n", 8432 __func__, 8433 sc->tlv_feature_flags); 8434 break; 8435 case IWN_FW_TLV_PBREQ_MAXLEN: 8436 case IWN_FW_TLV_RUNT_EVTLOG_PTR: 8437 case IWN_FW_TLV_RUNT_EVTLOG_SIZE: 8438 case IWN_FW_TLV_RUNT_ERRLOG_PTR: 8439 case IWN_FW_TLV_INIT_EVTLOG_PTR: 8440 case IWN_FW_TLV_INIT_EVTLOG_SIZE: 8441 case IWN_FW_TLV_INIT_ERRLOG_PTR: 8442 case IWN_FW_TLV_WOWLAN_INST: 8443 case IWN_FW_TLV_WOWLAN_DATA: 8444 DPRINTF(sc, IWN_DEBUG_RESET, 8445 "TLV type %d recognized but not handled\n", 8446 le16toh(tlv->type)); 8447 break; 8448 default: 8449 DPRINTF(sc, IWN_DEBUG_RESET, 8450 "TLV type %d not handled\n", le16toh(tlv->type)); 8451 break; 8452 } 8453 next: /* TLV fields are 32-bit aligned. */ 8454 ptr += (len + 3) & ~3; 8455 } 8456 return 0; 8457 } 8458 8459 static int 8460 iwn_read_firmware(struct iwn_softc *sc) 8461 { 8462 struct iwn_fw_info *fw = &sc->fw; 8463 int error; 8464 8465 DPRINTF(sc, IWN_DEBUG_TRACE, "->Doing %s\n", __func__); 8466 8467 IWN_UNLOCK(sc); 8468 8469 memset(fw, 0, sizeof (*fw)); 8470 8471 /* Read firmware image from filesystem. */ 8472 sc->fw_fp = firmware_get(sc->fwname); 8473 if (sc->fw_fp == NULL) { 8474 device_printf(sc->sc_dev, "%s: could not read firmware %s\n", 8475 __func__, sc->fwname); 8476 IWN_LOCK(sc); 8477 return EINVAL; 8478 } 8479 IWN_LOCK(sc); 8480 8481 fw->size = sc->fw_fp->datasize; 8482 fw->data = (const uint8_t *)sc->fw_fp->data; 8483 if (fw->size < sizeof (uint32_t)) { 8484 device_printf(sc->sc_dev, "%s: firmware too short: %zu bytes\n", 8485 __func__, fw->size); 8486 error = EINVAL; 8487 goto fail; 8488 } 8489 8490 /* Retrieve text and data sections. */ 8491 if (*(const uint32_t *)fw->data != 0) /* Legacy image. */ 8492 error = iwn_read_firmware_leg(sc, fw); 8493 else 8494 error = iwn_read_firmware_tlv(sc, fw, 1); 8495 if (error != 0) { 8496 device_printf(sc->sc_dev, 8497 "%s: could not read firmware sections, error %d\n", 8498 __func__, error); 8499 goto fail; 8500 } 8501 8502 device_printf(sc->sc_dev, "%s: ucode rev=0x%08x\n", __func__, sc->ucode_rev); 8503 8504 /* Make sure text and data sections fit in hardware memory. */ 8505 if (fw->main.textsz > sc->fw_text_maxsz || 8506 fw->main.datasz > sc->fw_data_maxsz || 8507 fw->init.textsz > sc->fw_text_maxsz || 8508 fw->init.datasz > sc->fw_data_maxsz || 8509 fw->boot.textsz > IWN_FW_BOOT_TEXT_MAXSZ || 8510 (fw->boot.textsz & 3) != 0) { 8511 device_printf(sc->sc_dev, "%s: firmware sections too large\n", 8512 __func__); 8513 error = EINVAL; 8514 goto fail; 8515 } 8516 8517 /* We can proceed with loading the firmware. */ 8518 return 0; 8519 8520 fail: iwn_unload_firmware(sc); 8521 return error; 8522 } 8523 8524 static void 8525 iwn_unload_firmware(struct iwn_softc *sc) 8526 { 8527 firmware_put(sc->fw_fp, FIRMWARE_UNLOAD); 8528 sc->fw_fp = NULL; 8529 } 8530 8531 static int 8532 iwn_clock_wait(struct iwn_softc *sc) 8533 { 8534 int ntries; 8535 8536 /* Set "initialization complete" bit. */ 8537 IWN_SETBITS(sc, IWN_GP_CNTRL, IWN_GP_CNTRL_INIT_DONE); 8538 8539 /* Wait for clock stabilization. */ 8540 for (ntries = 0; ntries < 2500; ntries++) { 8541 if (IWN_READ(sc, IWN_GP_CNTRL) & IWN_GP_CNTRL_MAC_CLOCK_READY) 8542 return 0; 8543 DELAY(10); 8544 } 8545 device_printf(sc->sc_dev, 8546 "%s: timeout waiting for clock stabilization\n", __func__); 8547 return ETIMEDOUT; 8548 } 8549 8550 static int 8551 iwn_apm_init(struct iwn_softc *sc) 8552 { 8553 uint32_t reg; 8554 int error; 8555 8556 DPRINTF(sc, IWN_DEBUG_TRACE, "->Doing %s\n", __func__); 8557 8558 /* Disable L0s exit timer (NMI bug workaround). */ 8559 IWN_SETBITS(sc, IWN_GIO_CHICKEN, IWN_GIO_CHICKEN_DIS_L0S_TIMER); 8560 /* Don't wait for ICH L0s (ICH bug workaround). */ 8561 IWN_SETBITS(sc, IWN_GIO_CHICKEN, IWN_GIO_CHICKEN_L1A_NO_L0S_RX); 8562 8563 /* Set FH wait threshold to max (HW bug under stress workaround). */ 8564 IWN_SETBITS(sc, IWN_DBG_HPET_MEM, 0xffff0000); 8565 8566 /* Enable HAP INTA to move adapter from L1a to L0s. */ 8567 IWN_SETBITS(sc, IWN_HW_IF_CONFIG, IWN_HW_IF_CONFIG_HAP_WAKE_L1A); 8568 8569 /* Retrieve PCIe Active State Power Management (ASPM). */ 8570 reg = pci_read_config(sc->sc_dev, sc->sc_cap_off + PCIER_LINK_CTL, 4); 8571 /* Workaround for HW instability in PCIe L0->L0s->L1 transition. */ 8572 if (reg & PCIEM_LINK_CTL_ASPMC_L1) /* L1 Entry enabled. */ 8573 IWN_SETBITS(sc, IWN_GIO, IWN_GIO_L0S_ENA); 8574 else 8575 IWN_CLRBITS(sc, IWN_GIO, IWN_GIO_L0S_ENA); 8576 8577 if (sc->base_params->pll_cfg_val) 8578 IWN_SETBITS(sc, IWN_ANA_PLL, sc->base_params->pll_cfg_val); 8579 8580 /* Wait for clock stabilization before accessing prph. */ 8581 if ((error = iwn_clock_wait(sc)) != 0) 8582 return error; 8583 8584 if ((error = iwn_nic_lock(sc)) != 0) 8585 return error; 8586 if (sc->hw_type == IWN_HW_REV_TYPE_4965) { 8587 /* Enable DMA and BSM (Bootstrap State Machine). */ 8588 iwn_prph_write(sc, IWN_APMG_CLK_EN, 8589 IWN_APMG_CLK_CTRL_DMA_CLK_RQT | 8590 IWN_APMG_CLK_CTRL_BSM_CLK_RQT); 8591 } else { 8592 /* Enable DMA. */ 8593 iwn_prph_write(sc, IWN_APMG_CLK_EN, 8594 IWN_APMG_CLK_CTRL_DMA_CLK_RQT); 8595 } 8596 DELAY(20); 8597 /* Disable L1-Active. */ 8598 iwn_prph_setbits(sc, IWN_APMG_PCI_STT, IWN_APMG_PCI_STT_L1A_DIS); 8599 iwn_nic_unlock(sc); 8600 8601 return 0; 8602 } 8603 8604 static void 8605 iwn_apm_stop_master(struct iwn_softc *sc) 8606 { 8607 int ntries; 8608 8609 /* Stop busmaster DMA activity. */ 8610 IWN_SETBITS(sc, IWN_RESET, IWN_RESET_STOP_MASTER); 8611 for (ntries = 0; ntries < 100; ntries++) { 8612 if (IWN_READ(sc, IWN_RESET) & IWN_RESET_MASTER_DISABLED) 8613 return; 8614 DELAY(10); 8615 } 8616 device_printf(sc->sc_dev, "%s: timeout waiting for master\n", __func__); 8617 } 8618 8619 static void 8620 iwn_apm_stop(struct iwn_softc *sc) 8621 { 8622 iwn_apm_stop_master(sc); 8623 8624 /* Reset the entire device. */ 8625 IWN_SETBITS(sc, IWN_RESET, IWN_RESET_SW); 8626 DELAY(10); 8627 /* Clear "initialization complete" bit. */ 8628 IWN_CLRBITS(sc, IWN_GP_CNTRL, IWN_GP_CNTRL_INIT_DONE); 8629 } 8630 8631 static int 8632 iwn4965_nic_config(struct iwn_softc *sc) 8633 { 8634 DPRINTF(sc, IWN_DEBUG_TRACE, "->Doing %s\n", __func__); 8635 8636 if (IWN_RFCFG_TYPE(sc->rfcfg) == 1) { 8637 /* 8638 * I don't believe this to be correct but this is what the 8639 * vendor driver is doing. Probably the bits should not be 8640 * shifted in IWN_RFCFG_*. 8641 */ 8642 IWN_SETBITS(sc, IWN_HW_IF_CONFIG, 8643 IWN_RFCFG_TYPE(sc->rfcfg) | 8644 IWN_RFCFG_STEP(sc->rfcfg) | 8645 IWN_RFCFG_DASH(sc->rfcfg)); 8646 } 8647 IWN_SETBITS(sc, IWN_HW_IF_CONFIG, 8648 IWN_HW_IF_CONFIG_RADIO_SI | IWN_HW_IF_CONFIG_MAC_SI); 8649 return 0; 8650 } 8651 8652 static int 8653 iwn5000_nic_config(struct iwn_softc *sc) 8654 { 8655 uint32_t tmp; 8656 int error; 8657 8658 DPRINTF(sc, IWN_DEBUG_TRACE, "->Doing %s\n", __func__); 8659 8660 if (IWN_RFCFG_TYPE(sc->rfcfg) < 3) { 8661 IWN_SETBITS(sc, IWN_HW_IF_CONFIG, 8662 IWN_RFCFG_TYPE(sc->rfcfg) | 8663 IWN_RFCFG_STEP(sc->rfcfg) | 8664 IWN_RFCFG_DASH(sc->rfcfg)); 8665 } 8666 IWN_SETBITS(sc, IWN_HW_IF_CONFIG, 8667 IWN_HW_IF_CONFIG_RADIO_SI | IWN_HW_IF_CONFIG_MAC_SI); 8668 8669 if ((error = iwn_nic_lock(sc)) != 0) 8670 return error; 8671 iwn_prph_setbits(sc, IWN_APMG_PS, IWN_APMG_PS_EARLY_PWROFF_DIS); 8672 8673 if (sc->hw_type == IWN_HW_REV_TYPE_1000) { 8674 /* 8675 * Select first Switching Voltage Regulator (1.32V) to 8676 * solve a stability issue related to noisy DC2DC line 8677 * in the silicon of 1000 Series. 8678 */ 8679 tmp = iwn_prph_read(sc, IWN_APMG_DIGITAL_SVR); 8680 tmp &= ~IWN_APMG_DIGITAL_SVR_VOLTAGE_MASK; 8681 tmp |= IWN_APMG_DIGITAL_SVR_VOLTAGE_1_32; 8682 iwn_prph_write(sc, IWN_APMG_DIGITAL_SVR, tmp); 8683 } 8684 iwn_nic_unlock(sc); 8685 8686 if (sc->sc_flags & IWN_FLAG_INTERNAL_PA) { 8687 /* Use internal power amplifier only. */ 8688 IWN_WRITE(sc, IWN_GP_DRIVER, IWN_GP_DRIVER_RADIO_2X2_IPA); 8689 } 8690 if (sc->base_params->additional_nic_config && sc->calib_ver >= 6) { 8691 /* Indicate that ROM calibration version is >=6. */ 8692 IWN_SETBITS(sc, IWN_GP_DRIVER, IWN_GP_DRIVER_CALIB_VER6); 8693 } 8694 if (sc->base_params->additional_gp_drv_bit) 8695 IWN_SETBITS(sc, IWN_GP_DRIVER, 8696 sc->base_params->additional_gp_drv_bit); 8697 return 0; 8698 } 8699 8700 /* 8701 * Take NIC ownership over Intel Active Management Technology (AMT). 8702 */ 8703 static int 8704 iwn_hw_prepare(struct iwn_softc *sc) 8705 { 8706 int ntries; 8707 8708 DPRINTF(sc, IWN_DEBUG_TRACE, "->Doing %s\n", __func__); 8709 8710 /* Check if hardware is ready. */ 8711 IWN_SETBITS(sc, IWN_HW_IF_CONFIG, IWN_HW_IF_CONFIG_NIC_READY); 8712 for (ntries = 0; ntries < 5; ntries++) { 8713 if (IWN_READ(sc, IWN_HW_IF_CONFIG) & 8714 IWN_HW_IF_CONFIG_NIC_READY) 8715 return 0; 8716 DELAY(10); 8717 } 8718 8719 /* Hardware not ready, force into ready state. */ 8720 IWN_SETBITS(sc, IWN_HW_IF_CONFIG, IWN_HW_IF_CONFIG_PREPARE); 8721 for (ntries = 0; ntries < 15000; ntries++) { 8722 if (!(IWN_READ(sc, IWN_HW_IF_CONFIG) & 8723 IWN_HW_IF_CONFIG_PREPARE_DONE)) 8724 break; 8725 DELAY(10); 8726 } 8727 if (ntries == 15000) 8728 return ETIMEDOUT; 8729 8730 /* Hardware should be ready now. */ 8731 IWN_SETBITS(sc, IWN_HW_IF_CONFIG, IWN_HW_IF_CONFIG_NIC_READY); 8732 for (ntries = 0; ntries < 5; ntries++) { 8733 if (IWN_READ(sc, IWN_HW_IF_CONFIG) & 8734 IWN_HW_IF_CONFIG_NIC_READY) 8735 return 0; 8736 DELAY(10); 8737 } 8738 return ETIMEDOUT; 8739 } 8740 8741 static int 8742 iwn_hw_init(struct iwn_softc *sc) 8743 { 8744 struct iwn_ops *ops = &sc->ops; 8745 int error, chnl, qid; 8746 8747 DPRINTF(sc, IWN_DEBUG_TRACE, "->%s begin\n", __func__); 8748 8749 /* Clear pending interrupts. */ 8750 IWN_WRITE(sc, IWN_INT, 0xffffffff); 8751 8752 if ((error = iwn_apm_init(sc)) != 0) { 8753 device_printf(sc->sc_dev, 8754 "%s: could not power ON adapter, error %d\n", __func__, 8755 error); 8756 return error; 8757 } 8758 8759 /* Select VMAIN power source. */ 8760 if ((error = iwn_nic_lock(sc)) != 0) 8761 return error; 8762 iwn_prph_clrbits(sc, IWN_APMG_PS, IWN_APMG_PS_PWR_SRC_MASK); 8763 iwn_nic_unlock(sc); 8764 8765 /* Perform adapter-specific initialization. */ 8766 if ((error = ops->nic_config(sc)) != 0) 8767 return error; 8768 8769 /* Initialize RX ring. */ 8770 if ((error = iwn_nic_lock(sc)) != 0) 8771 return error; 8772 IWN_WRITE(sc, IWN_FH_RX_CONFIG, 0); 8773 IWN_WRITE(sc, IWN_FH_RX_WPTR, 0); 8774 /* Set physical address of RX ring (256-byte aligned). */ 8775 IWN_WRITE(sc, IWN_FH_RX_BASE, sc->rxq.desc_dma.paddr >> 8); 8776 /* Set physical address of RX status (16-byte aligned). */ 8777 IWN_WRITE(sc, IWN_FH_STATUS_WPTR, sc->rxq.stat_dma.paddr >> 4); 8778 /* Enable RX. */ 8779 IWN_WRITE(sc, IWN_FH_RX_CONFIG, 8780 IWN_FH_RX_CONFIG_ENA | 8781 IWN_FH_RX_CONFIG_IGN_RXF_EMPTY | /* HW bug workaround */ 8782 IWN_FH_RX_CONFIG_IRQ_DST_HOST | 8783 IWN_FH_RX_CONFIG_SINGLE_FRAME | 8784 IWN_FH_RX_CONFIG_RB_TIMEOUT(0) | 8785 IWN_FH_RX_CONFIG_NRBD(IWN_RX_RING_COUNT_LOG)); 8786 iwn_nic_unlock(sc); 8787 IWN_WRITE(sc, IWN_FH_RX_WPTR, (IWN_RX_RING_COUNT - 1) & ~7); 8788 8789 if ((error = iwn_nic_lock(sc)) != 0) 8790 return error; 8791 8792 /* Initialize TX scheduler. */ 8793 iwn_prph_write(sc, sc->sched_txfact_addr, 0); 8794 8795 /* Set physical address of "keep warm" page (16-byte aligned). */ 8796 IWN_WRITE(sc, IWN_FH_KW_ADDR, sc->kw_dma.paddr >> 4); 8797 8798 /* Initialize TX rings. */ 8799 for (qid = 0; qid < sc->ntxqs; qid++) { 8800 struct iwn_tx_ring *txq = &sc->txq[qid]; 8801 8802 /* Set physical address of TX ring (256-byte aligned). */ 8803 IWN_WRITE(sc, IWN_FH_CBBC_QUEUE(qid), 8804 txq->desc_dma.paddr >> 8); 8805 } 8806 iwn_nic_unlock(sc); 8807 8808 /* Enable DMA channels. */ 8809 for (chnl = 0; chnl < sc->ndmachnls; chnl++) { 8810 IWN_WRITE(sc, IWN_FH_TX_CONFIG(chnl), 8811 IWN_FH_TX_CONFIG_DMA_ENA | 8812 IWN_FH_TX_CONFIG_DMA_CREDIT_ENA); 8813 } 8814 8815 /* Clear "radio off" and "commands blocked" bits. */ 8816 IWN_WRITE(sc, IWN_UCODE_GP1_CLR, IWN_UCODE_GP1_RFKILL); 8817 IWN_WRITE(sc, IWN_UCODE_GP1_CLR, IWN_UCODE_GP1_CMD_BLOCKED); 8818 8819 /* Clear pending interrupts. */ 8820 IWN_WRITE(sc, IWN_INT, 0xffffffff); 8821 /* Enable interrupt coalescing. */ 8822 IWN_WRITE(sc, IWN_INT_COALESCING, 512 / 8); 8823 /* Enable interrupts. */ 8824 IWN_WRITE(sc, IWN_INT_MASK, sc->int_mask); 8825 8826 /* _Really_ make sure "radio off" bit is cleared! */ 8827 IWN_WRITE(sc, IWN_UCODE_GP1_CLR, IWN_UCODE_GP1_RFKILL); 8828 IWN_WRITE(sc, IWN_UCODE_GP1_CLR, IWN_UCODE_GP1_RFKILL); 8829 8830 /* Enable shadow registers. */ 8831 if (sc->base_params->shadow_reg_enable) 8832 IWN_SETBITS(sc, IWN_SHADOW_REG_CTRL, 0x800fffff); 8833 8834 if ((error = ops->load_firmware(sc)) != 0) { 8835 device_printf(sc->sc_dev, 8836 "%s: could not load firmware, error %d\n", __func__, 8837 error); 8838 return error; 8839 } 8840 /* Wait at most one second for firmware alive notification. */ 8841 if ((error = msleep(sc, &sc->sc_mtx, PCATCH, "iwninit", hz)) != 0) { 8842 device_printf(sc->sc_dev, 8843 "%s: timeout waiting for adapter to initialize, error %d\n", 8844 __func__, error); 8845 return error; 8846 } 8847 /* Do post-firmware initialization. */ 8848 8849 DPRINTF(sc, IWN_DEBUG_TRACE, "->%s: end\n",__func__); 8850 8851 return ops->post_alive(sc); 8852 } 8853 8854 static void 8855 iwn_hw_stop(struct iwn_softc *sc) 8856 { 8857 int chnl, qid, ntries; 8858 8859 DPRINTF(sc, IWN_DEBUG_TRACE, "->Doing %s\n", __func__); 8860 8861 IWN_WRITE(sc, IWN_RESET, IWN_RESET_NEVO); 8862 8863 /* Disable interrupts. */ 8864 IWN_WRITE(sc, IWN_INT_MASK, 0); 8865 IWN_WRITE(sc, IWN_INT, 0xffffffff); 8866 IWN_WRITE(sc, IWN_FH_INT, 0xffffffff); 8867 sc->sc_flags &= ~IWN_FLAG_USE_ICT; 8868 8869 /* Make sure we no longer hold the NIC lock. */ 8870 iwn_nic_unlock(sc); 8871 8872 /* Stop TX scheduler. */ 8873 iwn_prph_write(sc, sc->sched_txfact_addr, 0); 8874 8875 /* Stop all DMA channels. */ 8876 if (iwn_nic_lock(sc) == 0) { 8877 for (chnl = 0; chnl < sc->ndmachnls; chnl++) { 8878 IWN_WRITE(sc, IWN_FH_TX_CONFIG(chnl), 0); 8879 for (ntries = 0; ntries < 200; ntries++) { 8880 if (IWN_READ(sc, IWN_FH_TX_STATUS) & 8881 IWN_FH_TX_STATUS_IDLE(chnl)) 8882 break; 8883 DELAY(10); 8884 } 8885 } 8886 iwn_nic_unlock(sc); 8887 } 8888 8889 /* Stop RX ring. */ 8890 iwn_reset_rx_ring(sc, &sc->rxq); 8891 8892 /* Reset all TX rings. */ 8893 for (qid = 0; qid < sc->ntxqs; qid++) 8894 iwn_reset_tx_ring(sc, &sc->txq[qid]); 8895 8896 if (iwn_nic_lock(sc) == 0) { 8897 iwn_prph_write(sc, IWN_APMG_CLK_DIS, 8898 IWN_APMG_CLK_CTRL_DMA_CLK_RQT); 8899 iwn_nic_unlock(sc); 8900 } 8901 DELAY(5); 8902 /* Power OFF adapter. */ 8903 iwn_apm_stop(sc); 8904 } 8905 8906 static void 8907 iwn_panicked(void *arg0, int pending) 8908 { 8909 struct iwn_softc *sc = arg0; 8910 struct ieee80211com *ic = &sc->sc_ic; 8911 struct ieee80211vap *vap = TAILQ_FIRST(&ic->ic_vaps); 8912 #if 0 8913 int error; 8914 #endif 8915 8916 if (vap == NULL) { 8917 printf("%s: null vap\n", __func__); 8918 return; 8919 } 8920 8921 device_printf(sc->sc_dev, "%s: controller panicked, iv_state = %d; " 8922 "restarting\n", __func__, vap->iv_state); 8923 8924 /* 8925 * This is not enough work. We need to also reinitialise 8926 * the correct transmit state for aggregation enabled queues, 8927 * which has a very specific requirement of 8928 * ring index = 802.11 seqno % 256. If we don't do this (which 8929 * we definitely don't!) then the firmware will just panic again. 8930 */ 8931 #if 1 8932 ieee80211_restart_all(ic); 8933 #else 8934 IWN_LOCK(sc); 8935 8936 iwn_stop_locked(sc); 8937 if ((error = iwn_init_locked(sc)) != 0) { 8938 device_printf(sc->sc_dev, 8939 "%s: could not init hardware\n", __func__); 8940 goto unlock; 8941 } 8942 if (vap->iv_state >= IEEE80211_S_AUTH && 8943 (error = iwn_auth(sc, vap)) != 0) { 8944 device_printf(sc->sc_dev, 8945 "%s: could not move to auth state\n", __func__); 8946 } 8947 if (vap->iv_state >= IEEE80211_S_RUN && 8948 (error = iwn_run(sc, vap)) != 0) { 8949 device_printf(sc->sc_dev, 8950 "%s: could not move to run state\n", __func__); 8951 } 8952 8953 unlock: 8954 IWN_UNLOCK(sc); 8955 #endif 8956 } 8957 8958 static int 8959 iwn_init_locked(struct iwn_softc *sc) 8960 { 8961 int error; 8962 8963 DPRINTF(sc, IWN_DEBUG_TRACE, "->%s begin\n", __func__); 8964 8965 IWN_LOCK_ASSERT(sc); 8966 8967 if (sc->sc_flags & IWN_FLAG_RUNNING) 8968 goto end; 8969 8970 sc->sc_flags |= IWN_FLAG_RUNNING; 8971 8972 if ((error = iwn_hw_prepare(sc)) != 0) { 8973 device_printf(sc->sc_dev, "%s: hardware not ready, error %d\n", 8974 __func__, error); 8975 goto fail; 8976 } 8977 8978 /* Initialize interrupt mask to default value. */ 8979 sc->int_mask = IWN_INT_MASK_DEF; 8980 sc->sc_flags &= ~IWN_FLAG_USE_ICT; 8981 8982 /* Check that the radio is not disabled by hardware switch. */ 8983 if (!(IWN_READ(sc, IWN_GP_CNTRL) & IWN_GP_CNTRL_RFKILL)) { 8984 iwn_stop_locked(sc); 8985 DPRINTF(sc, IWN_DEBUG_TRACE, "->%s: end\n",__func__); 8986 8987 return (1); 8988 } 8989 8990 /* Read firmware images from the filesystem. */ 8991 if ((error = iwn_read_firmware(sc)) != 0) { 8992 device_printf(sc->sc_dev, 8993 "%s: could not read firmware, error %d\n", __func__, 8994 error); 8995 goto fail; 8996 } 8997 8998 /* Initialize hardware and upload firmware. */ 8999 error = iwn_hw_init(sc); 9000 iwn_unload_firmware(sc); 9001 if (error != 0) { 9002 device_printf(sc->sc_dev, 9003 "%s: could not initialize hardware, error %d\n", __func__, 9004 error); 9005 goto fail; 9006 } 9007 9008 /* Configure adapter now that it is ready. */ 9009 if ((error = iwn_config(sc)) != 0) { 9010 device_printf(sc->sc_dev, 9011 "%s: could not configure device, error %d\n", __func__, 9012 error); 9013 goto fail; 9014 } 9015 9016 callout_reset(&sc->watchdog_to, hz, iwn_watchdog, sc); 9017 9018 end: 9019 DPRINTF(sc, IWN_DEBUG_TRACE, "->%s: end\n",__func__); 9020 9021 return (0); 9022 9023 fail: 9024 iwn_stop_locked(sc); 9025 9026 DPRINTF(sc, IWN_DEBUG_TRACE, "->%s: end in error\n",__func__); 9027 9028 return (-1); 9029 } 9030 9031 static int 9032 iwn_init(struct iwn_softc *sc) 9033 { 9034 int error; 9035 9036 IWN_LOCK(sc); 9037 error = iwn_init_locked(sc); 9038 IWN_UNLOCK(sc); 9039 9040 return (error); 9041 } 9042 9043 static void 9044 iwn_stop_locked(struct iwn_softc *sc) 9045 { 9046 9047 IWN_LOCK_ASSERT(sc); 9048 9049 if (!(sc->sc_flags & IWN_FLAG_RUNNING)) 9050 return; 9051 9052 sc->sc_is_scanning = 0; 9053 sc->sc_tx_timer = 0; 9054 callout_stop(&sc->watchdog_to); 9055 callout_stop(&sc->scan_timeout); 9056 callout_stop(&sc->calib_to); 9057 sc->sc_flags &= ~IWN_FLAG_RUNNING; 9058 9059 /* Power OFF hardware. */ 9060 iwn_hw_stop(sc); 9061 } 9062 9063 static void 9064 iwn_stop(struct iwn_softc *sc) 9065 { 9066 IWN_LOCK(sc); 9067 iwn_stop_locked(sc); 9068 IWN_UNLOCK(sc); 9069 } 9070 9071 /* 9072 * Callback from net80211 to start a scan. 9073 */ 9074 static void 9075 iwn_scan_start(struct ieee80211com *ic) 9076 { 9077 struct iwn_softc *sc = ic->ic_softc; 9078 9079 IWN_LOCK(sc); 9080 /* make the link LED blink while we're scanning */ 9081 iwn_set_led(sc, IWN_LED_LINK, 20, 2); 9082 IWN_UNLOCK(sc); 9083 } 9084 9085 /* 9086 * Callback from net80211 to terminate a scan. 9087 */ 9088 static void 9089 iwn_scan_end(struct ieee80211com *ic) 9090 { 9091 struct iwn_softc *sc = ic->ic_softc; 9092 struct ieee80211vap *vap = TAILQ_FIRST(&ic->ic_vaps); 9093 9094 IWN_LOCK(sc); 9095 if (vap->iv_state == IEEE80211_S_RUN) { 9096 /* Set link LED to ON status if we are associated */ 9097 iwn_set_led(sc, IWN_LED_LINK, 0, 1); 9098 } 9099 IWN_UNLOCK(sc); 9100 } 9101 9102 /* 9103 * Callback from net80211 to force a channel change. 9104 */ 9105 static void 9106 iwn_set_channel(struct ieee80211com *ic) 9107 { 9108 struct iwn_softc *sc = ic->ic_softc; 9109 int error; 9110 9111 DPRINTF(sc, IWN_DEBUG_TRACE, "->Doing %s\n", __func__); 9112 9113 IWN_LOCK(sc); 9114 /* 9115 * Only need to set the channel in Monitor mode. AP scanning and auth 9116 * are already taken care of by their respective firmware commands. 9117 */ 9118 if (ic->ic_opmode == IEEE80211_M_MONITOR) { 9119 error = iwn_config(sc); 9120 if (error != 0) 9121 device_printf(sc->sc_dev, 9122 "%s: error %d settting channel\n", __func__, error); 9123 } 9124 IWN_UNLOCK(sc); 9125 } 9126 9127 /* 9128 * Callback from net80211 to start scanning of the current channel. 9129 */ 9130 static void 9131 iwn_scan_curchan(struct ieee80211_scan_state *ss, unsigned long maxdwell) 9132 { 9133 struct ieee80211vap *vap = ss->ss_vap; 9134 struct ieee80211com *ic = vap->iv_ic; 9135 struct iwn_softc *sc = ic->ic_softc; 9136 int error; 9137 9138 IWN_LOCK(sc); 9139 error = iwn_scan(sc, vap, ss, ic->ic_curchan); 9140 IWN_UNLOCK(sc); 9141 if (error != 0) 9142 ieee80211_cancel_scan(vap); 9143 } 9144 9145 /* 9146 * Callback from net80211 to handle the minimum dwell time being met. 9147 * The intent is to terminate the scan but we just let the firmware 9148 * notify us when it's finished as we have no safe way to abort it. 9149 */ 9150 static void 9151 iwn_scan_mindwell(struct ieee80211_scan_state *ss) 9152 { 9153 /* NB: don't try to abort scan; wait for firmware to finish */ 9154 } 9155 #ifdef IWN_DEBUG 9156 #define IWN_DESC(x) case x: return #x 9157 9158 /* 9159 * Translate CSR code to string 9160 */ 9161 static char *iwn_get_csr_string(int csr) 9162 { 9163 switch (csr) { 9164 IWN_DESC(IWN_HW_IF_CONFIG); 9165 IWN_DESC(IWN_INT_COALESCING); 9166 IWN_DESC(IWN_INT); 9167 IWN_DESC(IWN_INT_MASK); 9168 IWN_DESC(IWN_FH_INT); 9169 IWN_DESC(IWN_GPIO_IN); 9170 IWN_DESC(IWN_RESET); 9171 IWN_DESC(IWN_GP_CNTRL); 9172 IWN_DESC(IWN_HW_REV); 9173 IWN_DESC(IWN_EEPROM); 9174 IWN_DESC(IWN_EEPROM_GP); 9175 IWN_DESC(IWN_OTP_GP); 9176 IWN_DESC(IWN_GIO); 9177 IWN_DESC(IWN_GP_UCODE); 9178 IWN_DESC(IWN_GP_DRIVER); 9179 IWN_DESC(IWN_UCODE_GP1); 9180 IWN_DESC(IWN_UCODE_GP2); 9181 IWN_DESC(IWN_LED); 9182 IWN_DESC(IWN_DRAM_INT_TBL); 9183 IWN_DESC(IWN_GIO_CHICKEN); 9184 IWN_DESC(IWN_ANA_PLL); 9185 IWN_DESC(IWN_HW_REV_WA); 9186 IWN_DESC(IWN_DBG_HPET_MEM); 9187 default: 9188 return "UNKNOWN CSR"; 9189 } 9190 } 9191 9192 /* 9193 * This function print firmware register 9194 */ 9195 static void 9196 iwn_debug_register(struct iwn_softc *sc) 9197 { 9198 int i; 9199 static const uint32_t csr_tbl[] = { 9200 IWN_HW_IF_CONFIG, 9201 IWN_INT_COALESCING, 9202 IWN_INT, 9203 IWN_INT_MASK, 9204 IWN_FH_INT, 9205 IWN_GPIO_IN, 9206 IWN_RESET, 9207 IWN_GP_CNTRL, 9208 IWN_HW_REV, 9209 IWN_EEPROM, 9210 IWN_EEPROM_GP, 9211 IWN_OTP_GP, 9212 IWN_GIO, 9213 IWN_GP_UCODE, 9214 IWN_GP_DRIVER, 9215 IWN_UCODE_GP1, 9216 IWN_UCODE_GP2, 9217 IWN_LED, 9218 IWN_DRAM_INT_TBL, 9219 IWN_GIO_CHICKEN, 9220 IWN_ANA_PLL, 9221 IWN_HW_REV_WA, 9222 IWN_DBG_HPET_MEM, 9223 }; 9224 DPRINTF(sc, IWN_DEBUG_REGISTER, 9225 "CSR values: (2nd byte of IWN_INT_COALESCING is IWN_INT_PERIODIC)%s", 9226 "\n"); 9227 for (i = 0; i < nitems(csr_tbl); i++){ 9228 DPRINTF(sc, IWN_DEBUG_REGISTER," %10s: 0x%08x ", 9229 iwn_get_csr_string(csr_tbl[i]), IWN_READ(sc, csr_tbl[i])); 9230 if ((i+1) % 3 == 0) 9231 DPRINTF(sc, IWN_DEBUG_REGISTER,"%s","\n"); 9232 } 9233 DPRINTF(sc, IWN_DEBUG_REGISTER,"%s","\n"); 9234 } 9235 #endif 9236 9237 9238