1 /*- 2 * Copyright (c) 2007-2009 Damien Bergamini <damien.bergamini@free.fr> 3 * Copyright (c) 2008 Benjamin Close <benjsc@FreeBSD.org> 4 * Copyright (c) 2008 Sam Leffler, Errno Consulting 5 * Copyright (c) 2011 Intel Corporation 6 * Copyright (c) 2013 Cedric GROSS <c.gross@kreiz-it.fr> 7 * Copyright (c) 2013 Adrian Chadd <adrian@FreeBSD.org> 8 * 9 * Permission to use, copy, modify, and distribute this software for any 10 * purpose with or without fee is hereby granted, provided that the above 11 * copyright notice and this permission notice appear in all copies. 12 * 13 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 14 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 15 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR 16 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 17 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN 18 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF 19 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 20 */ 21 22 /* 23 * Driver for Intel WiFi Link 4965 and 1000/5000/6000 Series 802.11 network 24 * adapters. 25 */ 26 27 #include <sys/cdefs.h> 28 #include "opt_wlan.h" 29 #include "opt_iwn.h" 30 31 #include <sys/param.h> 32 #include <sys/sockio.h> 33 #include <sys/sysctl.h> 34 #include <sys/mbuf.h> 35 #include <sys/kernel.h> 36 #include <sys/socket.h> 37 #include <sys/systm.h> 38 #include <sys/malloc.h> 39 #include <sys/bus.h> 40 #include <sys/conf.h> 41 #include <sys/rman.h> 42 #include <sys/endian.h> 43 #include <sys/firmware.h> 44 #include <sys/limits.h> 45 #include <sys/module.h> 46 #include <sys/priv.h> 47 #include <sys/queue.h> 48 #include <sys/taskqueue.h> 49 50 #include <machine/bus.h> 51 #include <machine/resource.h> 52 #include <machine/clock.h> 53 54 #include <dev/pci/pcireg.h> 55 #include <dev/pci/pcivar.h> 56 57 #include <net/if.h> 58 #include <net/if_var.h> 59 #include <net/if_dl.h> 60 #include <net/if_media.h> 61 62 #include <netinet/in.h> 63 #include <netinet/if_ether.h> 64 65 #include <net80211/ieee80211_var.h> 66 #include <net80211/ieee80211_radiotap.h> 67 #include <net80211/ieee80211_regdomain.h> 68 #include <net80211/ieee80211_ratectl.h> 69 70 #include <dev/iwn/if_iwnreg.h> 71 #include <dev/iwn/if_iwnvar.h> 72 #include <dev/iwn/if_iwn_devid.h> 73 #include <dev/iwn/if_iwn_chip_cfg.h> 74 #include <dev/iwn/if_iwn_debug.h> 75 #include <dev/iwn/if_iwn_ioctl.h> 76 77 struct iwn_ident { 78 uint16_t vendor; 79 uint16_t device; 80 const char *name; 81 }; 82 83 static const struct iwn_ident iwn_ident_table[] = { 84 { 0x8086, IWN_DID_6x05_1, "Intel Centrino Advanced-N 6205" }, 85 { 0x8086, IWN_DID_1000_1, "Intel Centrino Wireless-N 1000" }, 86 { 0x8086, IWN_DID_1000_2, "Intel Centrino Wireless-N 1000" }, 87 { 0x8086, IWN_DID_6x05_2, "Intel Centrino Advanced-N 6205" }, 88 { 0x8086, IWN_DID_6050_1, "Intel Centrino Advanced-N + WiMAX 6250" }, 89 { 0x8086, IWN_DID_6050_2, "Intel Centrino Advanced-N + WiMAX 6250" }, 90 { 0x8086, IWN_DID_x030_1, "Intel Centrino Wireless-N 1030" }, 91 { 0x8086, IWN_DID_x030_2, "Intel Centrino Wireless-N 1030" }, 92 { 0x8086, IWN_DID_x030_3, "Intel Centrino Advanced-N 6230" }, 93 { 0x8086, IWN_DID_x030_4, "Intel Centrino Advanced-N 6230" }, 94 { 0x8086, IWN_DID_6150_1, "Intel Centrino Wireless-N + WiMAX 6150" }, 95 { 0x8086, IWN_DID_6150_2, "Intel Centrino Wireless-N + WiMAX 6150" }, 96 { 0x8086, IWN_DID_2x00_1, "Intel(R) Centrino(R) Wireless-N 2200 BGN" }, 97 { 0x8086, IWN_DID_2x00_2, "Intel(R) Centrino(R) Wireless-N 2200 BGN" }, 98 /* XXX 2200D is IWN_SDID_2x00_4; there's no way to express this here! */ 99 { 0x8086, IWN_DID_2x30_1, "Intel Centrino Wireless-N 2230" }, 100 { 0x8086, IWN_DID_2x30_2, "Intel Centrino Wireless-N 2230" }, 101 { 0x8086, IWN_DID_130_1, "Intel Centrino Wireless-N 130" }, 102 { 0x8086, IWN_DID_130_2, "Intel Centrino Wireless-N 130" }, 103 { 0x8086, IWN_DID_100_1, "Intel Centrino Wireless-N 100" }, 104 { 0x8086, IWN_DID_100_2, "Intel Centrino Wireless-N 100" }, 105 { 0x8086, IWN_DID_105_1, "Intel Centrino Wireless-N 105" }, 106 { 0x8086, IWN_DID_105_2, "Intel Centrino Wireless-N 105" }, 107 { 0x8086, IWN_DID_135_1, "Intel Centrino Wireless-N 135" }, 108 { 0x8086, IWN_DID_135_2, "Intel Centrino Wireless-N 135" }, 109 { 0x8086, IWN_DID_4965_1, "Intel Wireless WiFi Link 4965" }, 110 { 0x8086, IWN_DID_6x00_1, "Intel Centrino Ultimate-N 6300" }, 111 { 0x8086, IWN_DID_6x00_2, "Intel Centrino Advanced-N 6200" }, 112 { 0x8086, IWN_DID_4965_2, "Intel Wireless WiFi Link 4965" }, 113 { 0x8086, IWN_DID_4965_3, "Intel Wireless WiFi Link 4965" }, 114 { 0x8086, IWN_DID_5x00_1, "Intel WiFi Link 5100" }, 115 { 0x8086, IWN_DID_4965_4, "Intel Wireless WiFi Link 4965" }, 116 { 0x8086, IWN_DID_5x00_3, "Intel Ultimate N WiFi Link 5300" }, 117 { 0x8086, IWN_DID_5x00_4, "Intel Ultimate N WiFi Link 5300" }, 118 { 0x8086, IWN_DID_5x00_2, "Intel WiFi Link 5100" }, 119 { 0x8086, IWN_DID_6x00_3, "Intel Centrino Ultimate-N 6300" }, 120 { 0x8086, IWN_DID_6x00_4, "Intel Centrino Advanced-N 6200" }, 121 { 0x8086, IWN_DID_5x50_1, "Intel WiMAX/WiFi Link 5350" }, 122 { 0x8086, IWN_DID_5x50_2, "Intel WiMAX/WiFi Link 5350" }, 123 { 0x8086, IWN_DID_5x50_3, "Intel WiMAX/WiFi Link 5150" }, 124 { 0x8086, IWN_DID_5x50_4, "Intel WiMAX/WiFi Link 5150" }, 125 { 0x8086, IWN_DID_6035_1, "Intel Centrino Advanced 6235" }, 126 { 0x8086, IWN_DID_6035_2, "Intel Centrino Advanced 6235" }, 127 { 0, 0, NULL } 128 }; 129 130 static int iwn_probe(device_t); 131 static int iwn_attach(device_t); 132 static void iwn4965_attach(struct iwn_softc *, uint16_t); 133 static void iwn5000_attach(struct iwn_softc *, uint16_t); 134 static int iwn_config_specific(struct iwn_softc *, uint16_t); 135 static void iwn_radiotap_attach(struct iwn_softc *); 136 static void iwn_sysctlattach(struct iwn_softc *); 137 static struct ieee80211vap *iwn_vap_create(struct ieee80211com *, 138 const char [IFNAMSIZ], int, enum ieee80211_opmode, int, 139 const uint8_t [IEEE80211_ADDR_LEN], 140 const uint8_t [IEEE80211_ADDR_LEN]); 141 static void iwn_vap_delete(struct ieee80211vap *); 142 static int iwn_detach(device_t); 143 static int iwn_shutdown(device_t); 144 static int iwn_suspend(device_t); 145 static int iwn_resume(device_t); 146 static int iwn_nic_lock(struct iwn_softc *); 147 static int iwn_eeprom_lock(struct iwn_softc *); 148 static int iwn_init_otprom(struct iwn_softc *); 149 static int iwn_read_prom_data(struct iwn_softc *, uint32_t, void *, int); 150 static void iwn_dma_map_addr(void *, bus_dma_segment_t *, int, int); 151 static int iwn_dma_contig_alloc(struct iwn_softc *, struct iwn_dma_info *, 152 void **, bus_size_t, bus_size_t); 153 static void iwn_dma_contig_free(struct iwn_dma_info *); 154 static int iwn_alloc_sched(struct iwn_softc *); 155 static void iwn_free_sched(struct iwn_softc *); 156 static int iwn_alloc_kw(struct iwn_softc *); 157 static void iwn_free_kw(struct iwn_softc *); 158 static int iwn_alloc_ict(struct iwn_softc *); 159 static void iwn_free_ict(struct iwn_softc *); 160 static int iwn_alloc_fwmem(struct iwn_softc *); 161 static void iwn_free_fwmem(struct iwn_softc *); 162 static int iwn_alloc_rx_ring(struct iwn_softc *, struct iwn_rx_ring *); 163 static void iwn_reset_rx_ring(struct iwn_softc *, struct iwn_rx_ring *); 164 static void iwn_free_rx_ring(struct iwn_softc *, struct iwn_rx_ring *); 165 static int iwn_alloc_tx_ring(struct iwn_softc *, struct iwn_tx_ring *, 166 int); 167 static void iwn_reset_tx_ring(struct iwn_softc *, struct iwn_tx_ring *); 168 static void iwn_free_tx_ring(struct iwn_softc *, struct iwn_tx_ring *); 169 static void iwn_check_tx_ring(struct iwn_softc *, int); 170 static void iwn5000_ict_reset(struct iwn_softc *); 171 static int iwn_read_eeprom(struct iwn_softc *, 172 uint8_t macaddr[IEEE80211_ADDR_LEN]); 173 static void iwn4965_read_eeprom(struct iwn_softc *); 174 #ifdef IWN_DEBUG 175 static void iwn4965_print_power_group(struct iwn_softc *, int); 176 #endif 177 static void iwn5000_read_eeprom(struct iwn_softc *); 178 static uint32_t iwn_eeprom_channel_flags(struct iwn_eeprom_chan *); 179 static void iwn_read_eeprom_band(struct iwn_softc *, int, int, int *, 180 struct ieee80211_channel[]); 181 static void iwn_read_eeprom_ht40(struct iwn_softc *, int, int, int *, 182 struct ieee80211_channel[]); 183 static void iwn_read_eeprom_channels(struct iwn_softc *, int, uint32_t); 184 static struct iwn_eeprom_chan *iwn_find_eeprom_channel(struct iwn_softc *, 185 struct ieee80211_channel *); 186 static void iwn_getradiocaps(struct ieee80211com *, int, int *, 187 struct ieee80211_channel[]); 188 static int iwn_setregdomain(struct ieee80211com *, 189 struct ieee80211_regdomain *, int, 190 struct ieee80211_channel[]); 191 static void iwn_read_eeprom_enhinfo(struct iwn_softc *); 192 static struct ieee80211_node *iwn_node_alloc(struct ieee80211vap *, 193 const uint8_t mac[IEEE80211_ADDR_LEN]); 194 static void iwn_newassoc(struct ieee80211_node *, int); 195 static int iwn_newstate(struct ieee80211vap *, enum ieee80211_state, int); 196 static void iwn_calib_timeout(void *); 197 static void iwn_rx_phy(struct iwn_softc *, struct iwn_rx_desc *); 198 static void iwn_rx_done(struct iwn_softc *, struct iwn_rx_desc *, 199 struct iwn_rx_data *); 200 static void iwn_agg_tx_complete(struct iwn_softc *, struct iwn_tx_ring *, 201 int, int, int); 202 static void iwn_rx_compressed_ba(struct iwn_softc *, struct iwn_rx_desc *); 203 static void iwn5000_rx_calib_results(struct iwn_softc *, 204 struct iwn_rx_desc *); 205 static void iwn_rx_statistics(struct iwn_softc *, struct iwn_rx_desc *); 206 static void iwn4965_tx_done(struct iwn_softc *, struct iwn_rx_desc *, 207 struct iwn_rx_data *); 208 static void iwn5000_tx_done(struct iwn_softc *, struct iwn_rx_desc *, 209 struct iwn_rx_data *); 210 static void iwn_adj_ampdu_ptr(struct iwn_softc *, struct iwn_tx_ring *); 211 static void iwn_tx_done(struct iwn_softc *, struct iwn_rx_desc *, int, int, 212 uint8_t); 213 static int iwn_ampdu_check_bitmap(uint64_t, int, int); 214 static int iwn_ampdu_index_check(struct iwn_softc *, struct iwn_tx_ring *, 215 uint64_t, int, int); 216 static void iwn_ampdu_tx_done(struct iwn_softc *, int, int, int, void *); 217 static void iwn_cmd_done(struct iwn_softc *, struct iwn_rx_desc *); 218 static void iwn_notif_intr(struct iwn_softc *); 219 static void iwn_wakeup_intr(struct iwn_softc *); 220 static void iwn_rftoggle_task(void *, int); 221 static void iwn_fatal_intr(struct iwn_softc *); 222 static void iwn_intr(void *); 223 static void iwn4965_update_sched(struct iwn_softc *, int, int, uint8_t, 224 uint16_t); 225 static void iwn5000_update_sched(struct iwn_softc *, int, int, uint8_t, 226 uint16_t); 227 #ifdef notyet 228 static void iwn5000_reset_sched(struct iwn_softc *, int, int); 229 #endif 230 static int iwn_tx_data(struct iwn_softc *, struct mbuf *, 231 struct ieee80211_node *); 232 static int iwn_tx_data_raw(struct iwn_softc *, struct mbuf *, 233 struct ieee80211_node *, 234 const struct ieee80211_bpf_params *params); 235 static int iwn_tx_cmd(struct iwn_softc *, struct mbuf *, 236 struct ieee80211_node *, struct iwn_tx_ring *); 237 static void iwn_xmit_task(void *arg0, int pending); 238 static int iwn_raw_xmit(struct ieee80211_node *, struct mbuf *, 239 const struct ieee80211_bpf_params *); 240 static int iwn_transmit(struct ieee80211com *, struct mbuf *); 241 static void iwn_scan_timeout(void *); 242 static void iwn_watchdog(void *); 243 static int iwn_ioctl(struct ieee80211com *, u_long , void *); 244 static void iwn_parent(struct ieee80211com *); 245 static int iwn_cmd(struct iwn_softc *, int, const void *, int, int); 246 static int iwn4965_add_node(struct iwn_softc *, struct iwn_node_info *, 247 int); 248 static int iwn5000_add_node(struct iwn_softc *, struct iwn_node_info *, 249 int); 250 static int iwn_set_link_quality(struct iwn_softc *, 251 struct ieee80211_node *); 252 static int iwn_add_broadcast_node(struct iwn_softc *, int); 253 static int iwn_updateedca(struct ieee80211com *); 254 static void iwn_set_promisc(struct iwn_softc *); 255 static void iwn_update_promisc(struct ieee80211com *); 256 static void iwn_update_mcast(struct ieee80211com *); 257 static void iwn_set_led(struct iwn_softc *, uint8_t, uint8_t, uint8_t); 258 static int iwn_set_critical_temp(struct iwn_softc *); 259 static int iwn_set_timing(struct iwn_softc *, struct ieee80211_node *); 260 static void iwn4965_power_calibration(struct iwn_softc *, int); 261 static int iwn4965_set_txpower(struct iwn_softc *, int); 262 static int iwn5000_set_txpower(struct iwn_softc *, int); 263 static int iwn4965_get_rssi(struct iwn_softc *, struct iwn_rx_stat *); 264 static int iwn5000_get_rssi(struct iwn_softc *, struct iwn_rx_stat *); 265 static int iwn_get_noise(const struct iwn_rx_general_stats *); 266 static int iwn4965_get_temperature(struct iwn_softc *); 267 static int iwn5000_get_temperature(struct iwn_softc *); 268 static int iwn_init_sensitivity(struct iwn_softc *); 269 static void iwn_collect_noise(struct iwn_softc *, 270 const struct iwn_rx_general_stats *); 271 static int iwn4965_init_gains(struct iwn_softc *); 272 static int iwn5000_init_gains(struct iwn_softc *); 273 static int iwn4965_set_gains(struct iwn_softc *); 274 static int iwn5000_set_gains(struct iwn_softc *); 275 static void iwn_tune_sensitivity(struct iwn_softc *, 276 const struct iwn_rx_stats *); 277 static void iwn_save_stats_counters(struct iwn_softc *, 278 const struct iwn_stats *); 279 static int iwn_send_sensitivity(struct iwn_softc *); 280 static void iwn_check_rx_recovery(struct iwn_softc *, struct iwn_stats *); 281 static int iwn_set_pslevel(struct iwn_softc *, int, int, int); 282 static int iwn_send_btcoex(struct iwn_softc *); 283 static int iwn_send_advanced_btcoex(struct iwn_softc *); 284 static int iwn5000_runtime_calib(struct iwn_softc *); 285 static int iwn_check_bss_filter(struct iwn_softc *); 286 static int iwn4965_rxon_assoc(struct iwn_softc *, int); 287 static int iwn5000_rxon_assoc(struct iwn_softc *, int); 288 static int iwn_send_rxon(struct iwn_softc *, int, int); 289 static int iwn_config(struct iwn_softc *); 290 static int iwn_scan(struct iwn_softc *, struct ieee80211vap *, 291 struct ieee80211_scan_state *, struct ieee80211_channel *); 292 static int iwn_auth(struct iwn_softc *, struct ieee80211vap *vap); 293 static int iwn_run(struct iwn_softc *, struct ieee80211vap *vap); 294 static int iwn_ampdu_rx_start(struct ieee80211_node *, 295 struct ieee80211_rx_ampdu *, int, int, int); 296 static void iwn_ampdu_rx_stop(struct ieee80211_node *, 297 struct ieee80211_rx_ampdu *); 298 static int iwn_addba_request(struct ieee80211_node *, 299 struct ieee80211_tx_ampdu *, int, int, int); 300 static int iwn_addba_response(struct ieee80211_node *, 301 struct ieee80211_tx_ampdu *, int, int, int); 302 static int iwn_ampdu_tx_start(struct ieee80211com *, 303 struct ieee80211_node *, uint8_t); 304 static void iwn_ampdu_tx_stop(struct ieee80211_node *, 305 struct ieee80211_tx_ampdu *); 306 static void iwn4965_ampdu_tx_start(struct iwn_softc *, 307 struct ieee80211_node *, int, uint8_t, uint16_t); 308 static void iwn4965_ampdu_tx_stop(struct iwn_softc *, int, 309 uint8_t, uint16_t); 310 static void iwn5000_ampdu_tx_start(struct iwn_softc *, 311 struct ieee80211_node *, int, uint8_t, uint16_t); 312 static void iwn5000_ampdu_tx_stop(struct iwn_softc *, int, 313 uint8_t, uint16_t); 314 static int iwn5000_query_calibration(struct iwn_softc *); 315 static int iwn5000_send_calibration(struct iwn_softc *); 316 static int iwn5000_send_wimax_coex(struct iwn_softc *); 317 static int iwn5000_crystal_calib(struct iwn_softc *); 318 static int iwn5000_temp_offset_calib(struct iwn_softc *); 319 static int iwn5000_temp_offset_calibv2(struct iwn_softc *); 320 static int iwn4965_post_alive(struct iwn_softc *); 321 static int iwn5000_post_alive(struct iwn_softc *); 322 static int iwn4965_load_bootcode(struct iwn_softc *, const uint8_t *, 323 int); 324 static int iwn4965_load_firmware(struct iwn_softc *); 325 static int iwn5000_load_firmware_section(struct iwn_softc *, uint32_t, 326 const uint8_t *, int); 327 static int iwn5000_load_firmware(struct iwn_softc *); 328 static int iwn_read_firmware_leg(struct iwn_softc *, 329 struct iwn_fw_info *); 330 static int iwn_read_firmware_tlv(struct iwn_softc *, 331 struct iwn_fw_info *, uint16_t); 332 static int iwn_read_firmware(struct iwn_softc *); 333 static void iwn_unload_firmware(struct iwn_softc *); 334 static int iwn_clock_wait(struct iwn_softc *); 335 static int iwn_apm_init(struct iwn_softc *); 336 static void iwn_apm_stop_master(struct iwn_softc *); 337 static void iwn_apm_stop(struct iwn_softc *); 338 static int iwn4965_nic_config(struct iwn_softc *); 339 static int iwn5000_nic_config(struct iwn_softc *); 340 static int iwn_hw_prepare(struct iwn_softc *); 341 static int iwn_hw_init(struct iwn_softc *); 342 static void iwn_hw_stop(struct iwn_softc *); 343 static void iwn_panicked(void *, int); 344 static int iwn_init_locked(struct iwn_softc *); 345 static int iwn_init(struct iwn_softc *); 346 static void iwn_stop_locked(struct iwn_softc *); 347 static void iwn_stop(struct iwn_softc *); 348 static void iwn_scan_start(struct ieee80211com *); 349 static void iwn_scan_end(struct ieee80211com *); 350 static void iwn_set_channel(struct ieee80211com *); 351 static void iwn_scan_curchan(struct ieee80211_scan_state *, unsigned long); 352 static void iwn_scan_mindwell(struct ieee80211_scan_state *); 353 #ifdef IWN_DEBUG 354 static char *iwn_get_csr_string(int); 355 static void iwn_debug_register(struct iwn_softc *); 356 #endif 357 358 static device_method_t iwn_methods[] = { 359 /* Device interface */ 360 DEVMETHOD(device_probe, iwn_probe), 361 DEVMETHOD(device_attach, iwn_attach), 362 DEVMETHOD(device_detach, iwn_detach), 363 DEVMETHOD(device_shutdown, iwn_shutdown), 364 DEVMETHOD(device_suspend, iwn_suspend), 365 DEVMETHOD(device_resume, iwn_resume), 366 367 DEVMETHOD_END 368 }; 369 370 static driver_t iwn_driver = { 371 "iwn", 372 iwn_methods, 373 sizeof(struct iwn_softc) 374 }; 375 376 DRIVER_MODULE(iwn, pci, iwn_driver, NULL, NULL); 377 MODULE_PNP_INFO("U16:vendor;U16:device;D:#", pci, iwn, iwn_ident_table, 378 nitems(iwn_ident_table) - 1); 379 MODULE_VERSION(iwn, 1); 380 381 MODULE_DEPEND(iwn, firmware, 1, 1, 1); 382 MODULE_DEPEND(iwn, pci, 1, 1, 1); 383 MODULE_DEPEND(iwn, wlan, 1, 1, 1); 384 385 static d_ioctl_t iwn_cdev_ioctl; 386 static d_open_t iwn_cdev_open; 387 static d_close_t iwn_cdev_close; 388 389 static struct cdevsw iwn_cdevsw = { 390 .d_version = D_VERSION, 391 .d_flags = 0, 392 .d_open = iwn_cdev_open, 393 .d_close = iwn_cdev_close, 394 .d_ioctl = iwn_cdev_ioctl, 395 .d_name = "iwn", 396 }; 397 398 static int 399 iwn_probe(device_t dev) 400 { 401 const struct iwn_ident *ident; 402 403 for (ident = iwn_ident_table; ident->name != NULL; ident++) { 404 if (pci_get_vendor(dev) == ident->vendor && 405 pci_get_device(dev) == ident->device) { 406 device_set_desc(dev, ident->name); 407 return (BUS_PROBE_DEFAULT); 408 } 409 } 410 return ENXIO; 411 } 412 413 static int 414 iwn_is_3stream_device(struct iwn_softc *sc) 415 { 416 /* XXX for now only 5300, until the 5350 can be tested */ 417 if (sc->hw_type == IWN_HW_REV_TYPE_5300) 418 return (1); 419 return (0); 420 } 421 422 static int 423 iwn_attach(device_t dev) 424 { 425 struct iwn_softc *sc = device_get_softc(dev); 426 struct ieee80211com *ic; 427 int i, error, rid; 428 429 sc->sc_dev = dev; 430 431 #ifdef IWN_DEBUG 432 error = resource_int_value(device_get_name(sc->sc_dev), 433 device_get_unit(sc->sc_dev), "debug", &(sc->sc_debug)); 434 if (error != 0) 435 sc->sc_debug = 0; 436 #else 437 sc->sc_debug = 0; 438 #endif 439 440 DPRINTF(sc, IWN_DEBUG_TRACE, "->%s: begin\n",__func__); 441 442 /* 443 * Get the offset of the PCI Express Capability Structure in PCI 444 * Configuration Space. 445 */ 446 error = pci_find_cap(dev, PCIY_EXPRESS, &sc->sc_cap_off); 447 if (error != 0) { 448 device_printf(dev, "PCIe capability structure not found!\n"); 449 return error; 450 } 451 452 /* Clear device-specific "PCI retry timeout" register (41h). */ 453 pci_write_config(dev, 0x41, 0, 1); 454 455 /* Enable bus-mastering. */ 456 pci_enable_busmaster(dev); 457 458 rid = PCIR_BAR(0); 459 sc->mem = bus_alloc_resource_any(dev, SYS_RES_MEMORY, &rid, 460 RF_ACTIVE); 461 if (sc->mem == NULL) { 462 device_printf(dev, "can't map mem space\n"); 463 error = ENOMEM; 464 return error; 465 } 466 sc->sc_st = rman_get_bustag(sc->mem); 467 sc->sc_sh = rman_get_bushandle(sc->mem); 468 469 i = 1; 470 rid = 0; 471 if (pci_alloc_msi(dev, &i) == 0) 472 rid = 1; 473 /* Install interrupt handler. */ 474 sc->irq = bus_alloc_resource_any(dev, SYS_RES_IRQ, &rid, RF_ACTIVE | 475 (rid != 0 ? 0 : RF_SHAREABLE)); 476 if (sc->irq == NULL) { 477 device_printf(dev, "can't map interrupt\n"); 478 error = ENOMEM; 479 goto fail; 480 } 481 482 IWN_LOCK_INIT(sc); 483 484 /* Read hardware revision and attach. */ 485 sc->hw_type = (IWN_READ(sc, IWN_HW_REV) >> IWN_HW_REV_TYPE_SHIFT) 486 & IWN_HW_REV_TYPE_MASK; 487 sc->subdevice_id = pci_get_subdevice(dev); 488 489 /* 490 * 4965 versus 5000 and later have different methods. 491 * Let's set those up first. 492 */ 493 if (sc->hw_type == IWN_HW_REV_TYPE_4965) 494 iwn4965_attach(sc, pci_get_device(dev)); 495 else 496 iwn5000_attach(sc, pci_get_device(dev)); 497 498 /* 499 * Next, let's setup the various parameters of each NIC. 500 */ 501 error = iwn_config_specific(sc, pci_get_device(dev)); 502 if (error != 0) { 503 device_printf(dev, "could not attach device, error %d\n", 504 error); 505 goto fail; 506 } 507 508 if ((error = iwn_hw_prepare(sc)) != 0) { 509 device_printf(dev, "hardware not ready, error %d\n", error); 510 goto fail; 511 } 512 513 /* Allocate DMA memory for firmware transfers. */ 514 if ((error = iwn_alloc_fwmem(sc)) != 0) { 515 device_printf(dev, 516 "could not allocate memory for firmware, error %d\n", 517 error); 518 goto fail; 519 } 520 521 /* Allocate "Keep Warm" page. */ 522 if ((error = iwn_alloc_kw(sc)) != 0) { 523 device_printf(dev, 524 "could not allocate keep warm page, error %d\n", error); 525 goto fail; 526 } 527 528 /* Allocate ICT table for 5000 Series. */ 529 if (sc->hw_type != IWN_HW_REV_TYPE_4965 && 530 (error = iwn_alloc_ict(sc)) != 0) { 531 device_printf(dev, "could not allocate ICT table, error %d\n", 532 error); 533 goto fail; 534 } 535 536 /* Allocate TX scheduler "rings". */ 537 if ((error = iwn_alloc_sched(sc)) != 0) { 538 device_printf(dev, 539 "could not allocate TX scheduler rings, error %d\n", error); 540 goto fail; 541 } 542 543 /* Allocate TX rings (16 on 4965AGN, 20 on >=5000). */ 544 for (i = 0; i < sc->ntxqs; i++) { 545 if ((error = iwn_alloc_tx_ring(sc, &sc->txq[i], i)) != 0) { 546 device_printf(dev, 547 "could not allocate TX ring %d, error %d\n", i, 548 error); 549 goto fail; 550 } 551 } 552 553 /* Allocate RX ring. */ 554 if ((error = iwn_alloc_rx_ring(sc, &sc->rxq)) != 0) { 555 device_printf(dev, "could not allocate RX ring, error %d\n", 556 error); 557 goto fail; 558 } 559 560 /* Clear pending interrupts. */ 561 IWN_WRITE(sc, IWN_INT, 0xffffffff); 562 563 ic = &sc->sc_ic; 564 ic->ic_softc = sc; 565 ic->ic_name = device_get_nameunit(dev); 566 ic->ic_phytype = IEEE80211_T_OFDM; /* not only, but not used */ 567 ic->ic_opmode = IEEE80211_M_STA; /* default to BSS mode */ 568 569 /* Set device capabilities. */ 570 ic->ic_caps = 571 IEEE80211_C_STA /* station mode supported */ 572 | IEEE80211_C_MONITOR /* monitor mode supported */ 573 #if 0 574 | IEEE80211_C_BGSCAN /* background scanning */ 575 #endif 576 | IEEE80211_C_TXPMGT /* tx power management */ 577 | IEEE80211_C_SHSLOT /* short slot time supported */ 578 | IEEE80211_C_WPA 579 | IEEE80211_C_SHPREAMBLE /* short preamble supported */ 580 #if 0 581 | IEEE80211_C_IBSS /* ibss/adhoc mode */ 582 #endif 583 | IEEE80211_C_WME /* WME */ 584 | IEEE80211_C_PMGT /* Station-side power mgmt */ 585 ; 586 587 /* Read MAC address, channels, etc from EEPROM. */ 588 if ((error = iwn_read_eeprom(sc, ic->ic_macaddr)) != 0) { 589 device_printf(dev, "could not read EEPROM, error %d\n", 590 error); 591 goto fail; 592 } 593 594 /* Count the number of available chains. */ 595 sc->ntxchains = 596 ((sc->txchainmask >> 2) & 1) + 597 ((sc->txchainmask >> 1) & 1) + 598 ((sc->txchainmask >> 0) & 1); 599 sc->nrxchains = 600 ((sc->rxchainmask >> 2) & 1) + 601 ((sc->rxchainmask >> 1) & 1) + 602 ((sc->rxchainmask >> 0) & 1); 603 if (bootverbose) { 604 device_printf(dev, "MIMO %dT%dR, %.4s, address %6D\n", 605 sc->ntxchains, sc->nrxchains, sc->eeprom_domain, 606 ic->ic_macaddr, ":"); 607 } 608 609 if (sc->sc_flags & IWN_FLAG_HAS_11N) { 610 ic->ic_rxstream = sc->nrxchains; 611 ic->ic_txstream = sc->ntxchains; 612 613 /* 614 * Some of the 3 antenna devices (ie, the 4965) only supports 615 * 2x2 operation. So correct the number of streams if 616 * it's not a 3-stream device. 617 */ 618 if (! iwn_is_3stream_device(sc)) { 619 if (ic->ic_rxstream > 2) 620 ic->ic_rxstream = 2; 621 if (ic->ic_txstream > 2) 622 ic->ic_txstream = 2; 623 } 624 625 ic->ic_htcaps = 626 IEEE80211_HTCAP_SMPS_OFF /* SMPS mode disabled */ 627 | IEEE80211_HTCAP_SHORTGI20 /* short GI in 20MHz */ 628 | IEEE80211_HTCAP_CHWIDTH40 /* 40MHz channel width*/ 629 | IEEE80211_HTCAP_SHORTGI40 /* short GI in 40MHz */ 630 #ifdef notyet 631 | IEEE80211_HTCAP_GREENFIELD 632 #if IWN_RBUF_SIZE == 8192 633 | IEEE80211_HTCAP_MAXAMSDU_7935 /* max A-MSDU length */ 634 #else 635 | IEEE80211_HTCAP_MAXAMSDU_3839 /* max A-MSDU length */ 636 #endif 637 #endif 638 /* s/w capabilities */ 639 | IEEE80211_HTC_HT /* HT operation */ 640 | IEEE80211_HTC_AMPDU /* tx A-MPDU */ 641 #ifdef notyet 642 | IEEE80211_HTC_AMSDU /* tx A-MSDU */ 643 #endif 644 ; 645 } 646 647 ieee80211_ifattach(ic); 648 ic->ic_vap_create = iwn_vap_create; 649 ic->ic_ioctl = iwn_ioctl; 650 ic->ic_parent = iwn_parent; 651 ic->ic_vap_delete = iwn_vap_delete; 652 ic->ic_transmit = iwn_transmit; 653 ic->ic_raw_xmit = iwn_raw_xmit; 654 ic->ic_node_alloc = iwn_node_alloc; 655 sc->sc_ampdu_rx_start = ic->ic_ampdu_rx_start; 656 ic->ic_ampdu_rx_start = iwn_ampdu_rx_start; 657 sc->sc_ampdu_rx_stop = ic->ic_ampdu_rx_stop; 658 ic->ic_ampdu_rx_stop = iwn_ampdu_rx_stop; 659 sc->sc_addba_request = ic->ic_addba_request; 660 ic->ic_addba_request = iwn_addba_request; 661 sc->sc_addba_response = ic->ic_addba_response; 662 ic->ic_addba_response = iwn_addba_response; 663 sc->sc_addba_stop = ic->ic_addba_stop; 664 ic->ic_addba_stop = iwn_ampdu_tx_stop; 665 ic->ic_newassoc = iwn_newassoc; 666 ic->ic_wme.wme_update = iwn_updateedca; 667 ic->ic_update_promisc = iwn_update_promisc; 668 ic->ic_update_mcast = iwn_update_mcast; 669 ic->ic_scan_start = iwn_scan_start; 670 ic->ic_scan_end = iwn_scan_end; 671 ic->ic_set_channel = iwn_set_channel; 672 ic->ic_scan_curchan = iwn_scan_curchan; 673 ic->ic_scan_mindwell = iwn_scan_mindwell; 674 ic->ic_getradiocaps = iwn_getradiocaps; 675 ic->ic_setregdomain = iwn_setregdomain; 676 677 iwn_radiotap_attach(sc); 678 679 callout_init_mtx(&sc->calib_to, &sc->sc_mtx, 0); 680 callout_init_mtx(&sc->scan_timeout, &sc->sc_mtx, 0); 681 callout_init_mtx(&sc->watchdog_to, &sc->sc_mtx, 0); 682 TASK_INIT(&sc->sc_rftoggle_task, 0, iwn_rftoggle_task, sc); 683 TASK_INIT(&sc->sc_panic_task, 0, iwn_panicked, sc); 684 TASK_INIT(&sc->sc_xmit_task, 0, iwn_xmit_task, sc); 685 686 mbufq_init(&sc->sc_xmit_queue, 1024); 687 688 sc->sc_tq = taskqueue_create("iwn_taskq", M_WAITOK, 689 taskqueue_thread_enqueue, &sc->sc_tq); 690 error = taskqueue_start_threads(&sc->sc_tq, 1, 0, "iwn_taskq"); 691 if (error != 0) { 692 device_printf(dev, "can't start threads, error %d\n", error); 693 goto fail; 694 } 695 696 iwn_sysctlattach(sc); 697 698 /* 699 * Hook our interrupt after all initialization is complete. 700 */ 701 error = bus_setup_intr(dev, sc->irq, INTR_TYPE_NET | INTR_MPSAFE, 702 NULL, iwn_intr, sc, &sc->sc_ih); 703 if (error != 0) { 704 device_printf(dev, "can't establish interrupt, error %d\n", 705 error); 706 goto fail; 707 } 708 709 #if 0 710 device_printf(sc->sc_dev, "%s: rx_stats=%d, rx_stats_bt=%d\n", 711 __func__, 712 sizeof(struct iwn_stats), 713 sizeof(struct iwn_stats_bt)); 714 #endif 715 716 if (bootverbose) 717 ieee80211_announce(ic); 718 DPRINTF(sc, IWN_DEBUG_TRACE, "->%s: end\n",__func__); 719 720 /* Add debug ioctl right at the end */ 721 sc->sc_cdev = make_dev(&iwn_cdevsw, device_get_unit(dev), 722 UID_ROOT, GID_WHEEL, 0600, "%s", device_get_nameunit(dev)); 723 if (sc->sc_cdev == NULL) { 724 device_printf(dev, "failed to create debug character device\n"); 725 } else { 726 sc->sc_cdev->si_drv1 = sc; 727 } 728 return 0; 729 fail: 730 iwn_detach(dev); 731 DPRINTF(sc, IWN_DEBUG_TRACE, "->%s: end in error\n",__func__); 732 return error; 733 } 734 735 /* 736 * Define specific configuration based on device id and subdevice id 737 * pid : PCI device id 738 */ 739 static int 740 iwn_config_specific(struct iwn_softc *sc, uint16_t pid) 741 { 742 743 switch (pid) { 744 /* 4965 series */ 745 case IWN_DID_4965_1: 746 case IWN_DID_4965_2: 747 case IWN_DID_4965_3: 748 case IWN_DID_4965_4: 749 sc->base_params = &iwn4965_base_params; 750 sc->limits = &iwn4965_sensitivity_limits; 751 sc->fwname = "iwn4965fw"; 752 /* Override chains masks, ROM is known to be broken. */ 753 sc->txchainmask = IWN_ANT_AB; 754 sc->rxchainmask = IWN_ANT_ABC; 755 /* Enable normal btcoex */ 756 sc->sc_flags |= IWN_FLAG_BTCOEX; 757 break; 758 /* 1000 Series */ 759 case IWN_DID_1000_1: 760 case IWN_DID_1000_2: 761 switch(sc->subdevice_id) { 762 case IWN_SDID_1000_1: 763 case IWN_SDID_1000_2: 764 case IWN_SDID_1000_3: 765 case IWN_SDID_1000_4: 766 case IWN_SDID_1000_5: 767 case IWN_SDID_1000_6: 768 case IWN_SDID_1000_7: 769 case IWN_SDID_1000_8: 770 case IWN_SDID_1000_9: 771 case IWN_SDID_1000_10: 772 case IWN_SDID_1000_11: 773 case IWN_SDID_1000_12: 774 sc->limits = &iwn1000_sensitivity_limits; 775 sc->base_params = &iwn1000_base_params; 776 sc->fwname = "iwn1000fw"; 777 break; 778 default: 779 device_printf(sc->sc_dev, "adapter type id : 0x%04x sub id :" 780 "0x%04x rev %d not supported (subdevice)\n", pid, 781 sc->subdevice_id,sc->hw_type); 782 return ENOTSUP; 783 } 784 break; 785 /* 6x00 Series */ 786 case IWN_DID_6x00_2: 787 case IWN_DID_6x00_4: 788 case IWN_DID_6x00_1: 789 case IWN_DID_6x00_3: 790 sc->fwname = "iwn6000fw"; 791 sc->limits = &iwn6000_sensitivity_limits; 792 switch(sc->subdevice_id) { 793 case IWN_SDID_6x00_1: 794 case IWN_SDID_6x00_2: 795 case IWN_SDID_6x00_8: 796 //iwl6000_3agn_cfg 797 sc->base_params = &iwn_6000_base_params; 798 break; 799 case IWN_SDID_6x00_3: 800 case IWN_SDID_6x00_6: 801 case IWN_SDID_6x00_9: 802 ////iwl6000i_2agn 803 case IWN_SDID_6x00_4: 804 case IWN_SDID_6x00_7: 805 case IWN_SDID_6x00_10: 806 //iwl6000i_2abg_cfg 807 case IWN_SDID_6x00_5: 808 //iwl6000i_2bg_cfg 809 sc->base_params = &iwn_6000i_base_params; 810 sc->sc_flags |= IWN_FLAG_INTERNAL_PA; 811 sc->txchainmask = IWN_ANT_BC; 812 sc->rxchainmask = IWN_ANT_BC; 813 break; 814 default: 815 device_printf(sc->sc_dev, "adapter type id : 0x%04x sub id :" 816 "0x%04x rev %d not supported (subdevice)\n", pid, 817 sc->subdevice_id,sc->hw_type); 818 return ENOTSUP; 819 } 820 break; 821 /* 6x05 Series */ 822 case IWN_DID_6x05_1: 823 case IWN_DID_6x05_2: 824 switch(sc->subdevice_id) { 825 case IWN_SDID_6x05_1: 826 case IWN_SDID_6x05_4: 827 case IWN_SDID_6x05_6: 828 //iwl6005_2agn_cfg 829 case IWN_SDID_6x05_2: 830 case IWN_SDID_6x05_5: 831 case IWN_SDID_6x05_7: 832 //iwl6005_2abg_cfg 833 case IWN_SDID_6x05_3: 834 //iwl6005_2bg_cfg 835 case IWN_SDID_6x05_8: 836 case IWN_SDID_6x05_9: 837 //iwl6005_2agn_sff_cfg 838 case IWN_SDID_6x05_10: 839 //iwl6005_2agn_d_cfg 840 case IWN_SDID_6x05_11: 841 //iwl6005_2agn_mow1_cfg 842 case IWN_SDID_6x05_12: 843 //iwl6005_2agn_mow2_cfg 844 sc->fwname = "iwn6000g2afw"; 845 sc->limits = &iwn6000_sensitivity_limits; 846 sc->base_params = &iwn_6000g2_base_params; 847 break; 848 default: 849 device_printf(sc->sc_dev, "adapter type id : 0x%04x sub id :" 850 "0x%04x rev %d not supported (subdevice)\n", pid, 851 sc->subdevice_id,sc->hw_type); 852 return ENOTSUP; 853 } 854 break; 855 /* 6x35 Series */ 856 case IWN_DID_6035_1: 857 case IWN_DID_6035_2: 858 switch(sc->subdevice_id) { 859 case IWN_SDID_6035_1: 860 case IWN_SDID_6035_2: 861 case IWN_SDID_6035_3: 862 case IWN_SDID_6035_4: 863 case IWN_SDID_6035_5: 864 sc->fwname = "iwn6000g2bfw"; 865 sc->limits = &iwn6235_sensitivity_limits; 866 sc->base_params = &iwn_6235_base_params; 867 break; 868 default: 869 device_printf(sc->sc_dev, "adapter type id : 0x%04x sub id :" 870 "0x%04x rev %d not supported (subdevice)\n", pid, 871 sc->subdevice_id,sc->hw_type); 872 return ENOTSUP; 873 } 874 break; 875 /* 6x50 WiFi/WiMax Series */ 876 case IWN_DID_6050_1: 877 case IWN_DID_6050_2: 878 switch(sc->subdevice_id) { 879 case IWN_SDID_6050_1: 880 case IWN_SDID_6050_3: 881 case IWN_SDID_6050_5: 882 //iwl6050_2agn_cfg 883 case IWN_SDID_6050_2: 884 case IWN_SDID_6050_4: 885 case IWN_SDID_6050_6: 886 //iwl6050_2abg_cfg 887 sc->fwname = "iwn6050fw"; 888 sc->txchainmask = IWN_ANT_AB; 889 sc->rxchainmask = IWN_ANT_AB; 890 sc->limits = &iwn6000_sensitivity_limits; 891 sc->base_params = &iwn_6050_base_params; 892 break; 893 default: 894 device_printf(sc->sc_dev, "adapter type id : 0x%04x sub id :" 895 "0x%04x rev %d not supported (subdevice)\n", pid, 896 sc->subdevice_id,sc->hw_type); 897 return ENOTSUP; 898 } 899 break; 900 /* 6150 WiFi/WiMax Series */ 901 case IWN_DID_6150_1: 902 case IWN_DID_6150_2: 903 switch(sc->subdevice_id) { 904 case IWN_SDID_6150_1: 905 case IWN_SDID_6150_3: 906 case IWN_SDID_6150_5: 907 // iwl6150_bgn_cfg 908 case IWN_SDID_6150_2: 909 case IWN_SDID_6150_4: 910 case IWN_SDID_6150_6: 911 //iwl6150_bg_cfg 912 sc->fwname = "iwn6050fw"; 913 sc->limits = &iwn6000_sensitivity_limits; 914 sc->base_params = &iwn_6150_base_params; 915 break; 916 default: 917 device_printf(sc->sc_dev, "adapter type id : 0x%04x sub id :" 918 "0x%04x rev %d not supported (subdevice)\n", pid, 919 sc->subdevice_id,sc->hw_type); 920 return ENOTSUP; 921 } 922 break; 923 /* 6030 Series and 1030 Series */ 924 case IWN_DID_x030_1: 925 case IWN_DID_x030_2: 926 case IWN_DID_x030_3: 927 case IWN_DID_x030_4: 928 switch(sc->subdevice_id) { 929 case IWN_SDID_x030_1: 930 case IWN_SDID_x030_3: 931 case IWN_SDID_x030_5: 932 // iwl1030_bgn_cfg 933 case IWN_SDID_x030_2: 934 case IWN_SDID_x030_4: 935 case IWN_SDID_x030_6: 936 //iwl1030_bg_cfg 937 case IWN_SDID_x030_7: 938 case IWN_SDID_x030_10: 939 case IWN_SDID_x030_14: 940 //iwl6030_2agn_cfg 941 case IWN_SDID_x030_8: 942 case IWN_SDID_x030_11: 943 case IWN_SDID_x030_15: 944 // iwl6030_2bgn_cfg 945 case IWN_SDID_x030_9: 946 case IWN_SDID_x030_12: 947 case IWN_SDID_x030_16: 948 // iwl6030_2abg_cfg 949 case IWN_SDID_x030_13: 950 //iwl6030_2bg_cfg 951 sc->fwname = "iwn6000g2bfw"; 952 sc->limits = &iwn6000_sensitivity_limits; 953 sc->base_params = &iwn_6000g2b_base_params; 954 break; 955 default: 956 device_printf(sc->sc_dev, "adapter type id : 0x%04x sub id :" 957 "0x%04x rev %d not supported (subdevice)\n", pid, 958 sc->subdevice_id,sc->hw_type); 959 return ENOTSUP; 960 } 961 break; 962 /* 130 Series WiFi */ 963 /* XXX: This series will need adjustment for rate. 964 * see rx_with_siso_diversity in linux kernel 965 */ 966 case IWN_DID_130_1: 967 case IWN_DID_130_2: 968 switch(sc->subdevice_id) { 969 case IWN_SDID_130_1: 970 case IWN_SDID_130_3: 971 case IWN_SDID_130_5: 972 //iwl130_bgn_cfg 973 case IWN_SDID_130_2: 974 case IWN_SDID_130_4: 975 case IWN_SDID_130_6: 976 //iwl130_bg_cfg 977 sc->fwname = "iwn6000g2bfw"; 978 sc->limits = &iwn6000_sensitivity_limits; 979 sc->base_params = &iwn_6000g2b_base_params; 980 break; 981 default: 982 device_printf(sc->sc_dev, "adapter type id : 0x%04x sub id :" 983 "0x%04x rev %d not supported (subdevice)\n", pid, 984 sc->subdevice_id,sc->hw_type); 985 return ENOTSUP; 986 } 987 break; 988 /* 100 Series WiFi */ 989 case IWN_DID_100_1: 990 case IWN_DID_100_2: 991 switch(sc->subdevice_id) { 992 case IWN_SDID_100_1: 993 case IWN_SDID_100_2: 994 case IWN_SDID_100_3: 995 case IWN_SDID_100_4: 996 case IWN_SDID_100_5: 997 case IWN_SDID_100_6: 998 sc->limits = &iwn1000_sensitivity_limits; 999 sc->base_params = &iwn1000_base_params; 1000 sc->fwname = "iwn100fw"; 1001 break; 1002 default: 1003 device_printf(sc->sc_dev, "adapter type id : 0x%04x sub id :" 1004 "0x%04x rev %d not supported (subdevice)\n", pid, 1005 sc->subdevice_id,sc->hw_type); 1006 return ENOTSUP; 1007 } 1008 break; 1009 1010 /* 105 Series */ 1011 /* XXX: This series will need adjustment for rate. 1012 * see rx_with_siso_diversity in linux kernel 1013 */ 1014 case IWN_DID_105_1: 1015 case IWN_DID_105_2: 1016 switch(sc->subdevice_id) { 1017 case IWN_SDID_105_1: 1018 case IWN_SDID_105_2: 1019 case IWN_SDID_105_3: 1020 //iwl105_bgn_cfg 1021 case IWN_SDID_105_4: 1022 //iwl105_bgn_d_cfg 1023 sc->limits = &iwn2030_sensitivity_limits; 1024 sc->base_params = &iwn2000_base_params; 1025 sc->fwname = "iwn105fw"; 1026 break; 1027 default: 1028 device_printf(sc->sc_dev, "adapter type id : 0x%04x sub id :" 1029 "0x%04x rev %d not supported (subdevice)\n", pid, 1030 sc->subdevice_id,sc->hw_type); 1031 return ENOTSUP; 1032 } 1033 break; 1034 1035 /* 135 Series */ 1036 /* XXX: This series will need adjustment for rate. 1037 * see rx_with_siso_diversity in linux kernel 1038 */ 1039 case IWN_DID_135_1: 1040 case IWN_DID_135_2: 1041 switch(sc->subdevice_id) { 1042 case IWN_SDID_135_1: 1043 case IWN_SDID_135_2: 1044 case IWN_SDID_135_3: 1045 sc->limits = &iwn2030_sensitivity_limits; 1046 sc->base_params = &iwn2030_base_params; 1047 sc->fwname = "iwn135fw"; 1048 break; 1049 default: 1050 device_printf(sc->sc_dev, "adapter type id : 0x%04x sub id :" 1051 "0x%04x rev %d not supported (subdevice)\n", pid, 1052 sc->subdevice_id,sc->hw_type); 1053 return ENOTSUP; 1054 } 1055 break; 1056 1057 /* 2x00 Series */ 1058 case IWN_DID_2x00_1: 1059 case IWN_DID_2x00_2: 1060 switch(sc->subdevice_id) { 1061 case IWN_SDID_2x00_1: 1062 case IWN_SDID_2x00_2: 1063 case IWN_SDID_2x00_3: 1064 //iwl2000_2bgn_cfg 1065 case IWN_SDID_2x00_4: 1066 //iwl2000_2bgn_d_cfg 1067 sc->limits = &iwn2030_sensitivity_limits; 1068 sc->base_params = &iwn2000_base_params; 1069 sc->fwname = "iwn2000fw"; 1070 break; 1071 default: 1072 device_printf(sc->sc_dev, "adapter type id : 0x%04x sub id :" 1073 "0x%04x rev %d not supported (subdevice) \n", 1074 pid, sc->subdevice_id, sc->hw_type); 1075 return ENOTSUP; 1076 } 1077 break; 1078 /* 2x30 Series */ 1079 case IWN_DID_2x30_1: 1080 case IWN_DID_2x30_2: 1081 switch(sc->subdevice_id) { 1082 case IWN_SDID_2x30_1: 1083 case IWN_SDID_2x30_3: 1084 case IWN_SDID_2x30_5: 1085 //iwl100_bgn_cfg 1086 case IWN_SDID_2x30_2: 1087 case IWN_SDID_2x30_4: 1088 case IWN_SDID_2x30_6: 1089 //iwl100_bg_cfg 1090 sc->limits = &iwn2030_sensitivity_limits; 1091 sc->base_params = &iwn2030_base_params; 1092 sc->fwname = "iwn2030fw"; 1093 break; 1094 default: 1095 device_printf(sc->sc_dev, "adapter type id : 0x%04x sub id :" 1096 "0x%04x rev %d not supported (subdevice)\n", pid, 1097 sc->subdevice_id,sc->hw_type); 1098 return ENOTSUP; 1099 } 1100 break; 1101 /* 5x00 Series */ 1102 case IWN_DID_5x00_1: 1103 case IWN_DID_5x00_2: 1104 case IWN_DID_5x00_3: 1105 case IWN_DID_5x00_4: 1106 sc->limits = &iwn5000_sensitivity_limits; 1107 sc->base_params = &iwn5000_base_params; 1108 sc->fwname = "iwn5000fw"; 1109 switch(sc->subdevice_id) { 1110 case IWN_SDID_5x00_1: 1111 case IWN_SDID_5x00_2: 1112 case IWN_SDID_5x00_3: 1113 case IWN_SDID_5x00_4: 1114 case IWN_SDID_5x00_9: 1115 case IWN_SDID_5x00_10: 1116 case IWN_SDID_5x00_11: 1117 case IWN_SDID_5x00_12: 1118 case IWN_SDID_5x00_17: 1119 case IWN_SDID_5x00_18: 1120 case IWN_SDID_5x00_19: 1121 case IWN_SDID_5x00_20: 1122 //iwl5100_agn_cfg 1123 sc->txchainmask = IWN_ANT_B; 1124 sc->rxchainmask = IWN_ANT_AB; 1125 break; 1126 case IWN_SDID_5x00_5: 1127 case IWN_SDID_5x00_6: 1128 case IWN_SDID_5x00_13: 1129 case IWN_SDID_5x00_14: 1130 case IWN_SDID_5x00_21: 1131 case IWN_SDID_5x00_22: 1132 //iwl5100_bgn_cfg 1133 sc->txchainmask = IWN_ANT_B; 1134 sc->rxchainmask = IWN_ANT_AB; 1135 break; 1136 case IWN_SDID_5x00_7: 1137 case IWN_SDID_5x00_8: 1138 case IWN_SDID_5x00_15: 1139 case IWN_SDID_5x00_16: 1140 case IWN_SDID_5x00_23: 1141 case IWN_SDID_5x00_24: 1142 //iwl5100_abg_cfg 1143 sc->txchainmask = IWN_ANT_B; 1144 sc->rxchainmask = IWN_ANT_AB; 1145 break; 1146 case IWN_SDID_5x00_25: 1147 case IWN_SDID_5x00_26: 1148 case IWN_SDID_5x00_27: 1149 case IWN_SDID_5x00_28: 1150 case IWN_SDID_5x00_29: 1151 case IWN_SDID_5x00_30: 1152 case IWN_SDID_5x00_31: 1153 case IWN_SDID_5x00_32: 1154 case IWN_SDID_5x00_33: 1155 case IWN_SDID_5x00_34: 1156 case IWN_SDID_5x00_35: 1157 case IWN_SDID_5x00_36: 1158 //iwl5300_agn_cfg 1159 sc->txchainmask = IWN_ANT_ABC; 1160 sc->rxchainmask = IWN_ANT_ABC; 1161 break; 1162 default: 1163 device_printf(sc->sc_dev, "adapter type id : 0x%04x sub id :" 1164 "0x%04x rev %d not supported (subdevice)\n", pid, 1165 sc->subdevice_id,sc->hw_type); 1166 return ENOTSUP; 1167 } 1168 break; 1169 /* 5x50 Series */ 1170 case IWN_DID_5x50_1: 1171 case IWN_DID_5x50_2: 1172 case IWN_DID_5x50_3: 1173 case IWN_DID_5x50_4: 1174 sc->limits = &iwn5000_sensitivity_limits; 1175 sc->base_params = &iwn5000_base_params; 1176 sc->fwname = "iwn5000fw"; 1177 switch(sc->subdevice_id) { 1178 case IWN_SDID_5x50_1: 1179 case IWN_SDID_5x50_2: 1180 case IWN_SDID_5x50_3: 1181 //iwl5350_agn_cfg 1182 sc->limits = &iwn5000_sensitivity_limits; 1183 sc->base_params = &iwn5000_base_params; 1184 sc->fwname = "iwn5000fw"; 1185 break; 1186 case IWN_SDID_5x50_4: 1187 case IWN_SDID_5x50_5: 1188 case IWN_SDID_5x50_8: 1189 case IWN_SDID_5x50_9: 1190 case IWN_SDID_5x50_10: 1191 case IWN_SDID_5x50_11: 1192 //iwl5150_agn_cfg 1193 case IWN_SDID_5x50_6: 1194 case IWN_SDID_5x50_7: 1195 case IWN_SDID_5x50_12: 1196 case IWN_SDID_5x50_13: 1197 //iwl5150_abg_cfg 1198 sc->limits = &iwn5000_sensitivity_limits; 1199 sc->fwname = "iwn5150fw"; 1200 sc->base_params = &iwn_5x50_base_params; 1201 break; 1202 default: 1203 device_printf(sc->sc_dev, "adapter type id : 0x%04x sub id :" 1204 "0x%04x rev %d not supported (subdevice)\n", pid, 1205 sc->subdevice_id,sc->hw_type); 1206 return ENOTSUP; 1207 } 1208 break; 1209 default: 1210 device_printf(sc->sc_dev, "adapter type id : 0x%04x sub id : 0x%04x" 1211 "rev 0x%08x not supported (device)\n", pid, sc->subdevice_id, 1212 sc->hw_type); 1213 return ENOTSUP; 1214 } 1215 return 0; 1216 } 1217 1218 static void 1219 iwn4965_attach(struct iwn_softc *sc, uint16_t pid) 1220 { 1221 struct iwn_ops *ops = &sc->ops; 1222 1223 DPRINTF(sc, IWN_DEBUG_TRACE, "->%s begin\n", __func__); 1224 1225 ops->load_firmware = iwn4965_load_firmware; 1226 ops->read_eeprom = iwn4965_read_eeprom; 1227 ops->post_alive = iwn4965_post_alive; 1228 ops->nic_config = iwn4965_nic_config; 1229 ops->update_sched = iwn4965_update_sched; 1230 ops->get_temperature = iwn4965_get_temperature; 1231 ops->get_rssi = iwn4965_get_rssi; 1232 ops->set_txpower = iwn4965_set_txpower; 1233 ops->init_gains = iwn4965_init_gains; 1234 ops->set_gains = iwn4965_set_gains; 1235 ops->rxon_assoc = iwn4965_rxon_assoc; 1236 ops->add_node = iwn4965_add_node; 1237 ops->tx_done = iwn4965_tx_done; 1238 ops->ampdu_tx_start = iwn4965_ampdu_tx_start; 1239 ops->ampdu_tx_stop = iwn4965_ampdu_tx_stop; 1240 sc->ntxqs = IWN4965_NTXQUEUES; 1241 sc->firstaggqueue = IWN4965_FIRSTAGGQUEUE; 1242 sc->ndmachnls = IWN4965_NDMACHNLS; 1243 sc->broadcast_id = IWN4965_ID_BROADCAST; 1244 sc->rxonsz = IWN4965_RXONSZ; 1245 sc->schedsz = IWN4965_SCHEDSZ; 1246 sc->fw_text_maxsz = IWN4965_FW_TEXT_MAXSZ; 1247 sc->fw_data_maxsz = IWN4965_FW_DATA_MAXSZ; 1248 sc->fwsz = IWN4965_FWSZ; 1249 sc->sched_txfact_addr = IWN4965_SCHED_TXFACT; 1250 sc->limits = &iwn4965_sensitivity_limits; 1251 sc->fwname = "iwn4965fw"; 1252 /* Override chains masks, ROM is known to be broken. */ 1253 sc->txchainmask = IWN_ANT_AB; 1254 sc->rxchainmask = IWN_ANT_ABC; 1255 /* Enable normal btcoex */ 1256 sc->sc_flags |= IWN_FLAG_BTCOEX; 1257 1258 DPRINTF(sc, IWN_DEBUG_TRACE, "%s: end\n",__func__); 1259 } 1260 1261 static void 1262 iwn5000_attach(struct iwn_softc *sc, uint16_t pid) 1263 { 1264 struct iwn_ops *ops = &sc->ops; 1265 1266 DPRINTF(sc, IWN_DEBUG_TRACE, "->%s begin\n", __func__); 1267 1268 ops->load_firmware = iwn5000_load_firmware; 1269 ops->read_eeprom = iwn5000_read_eeprom; 1270 ops->post_alive = iwn5000_post_alive; 1271 ops->nic_config = iwn5000_nic_config; 1272 ops->update_sched = iwn5000_update_sched; 1273 ops->get_temperature = iwn5000_get_temperature; 1274 ops->get_rssi = iwn5000_get_rssi; 1275 ops->set_txpower = iwn5000_set_txpower; 1276 ops->init_gains = iwn5000_init_gains; 1277 ops->set_gains = iwn5000_set_gains; 1278 ops->rxon_assoc = iwn5000_rxon_assoc; 1279 ops->add_node = iwn5000_add_node; 1280 ops->tx_done = iwn5000_tx_done; 1281 ops->ampdu_tx_start = iwn5000_ampdu_tx_start; 1282 ops->ampdu_tx_stop = iwn5000_ampdu_tx_stop; 1283 sc->ntxqs = IWN5000_NTXQUEUES; 1284 sc->firstaggqueue = IWN5000_FIRSTAGGQUEUE; 1285 sc->ndmachnls = IWN5000_NDMACHNLS; 1286 sc->broadcast_id = IWN5000_ID_BROADCAST; 1287 sc->rxonsz = IWN5000_RXONSZ; 1288 sc->schedsz = IWN5000_SCHEDSZ; 1289 sc->fw_text_maxsz = IWN5000_FW_TEXT_MAXSZ; 1290 sc->fw_data_maxsz = IWN5000_FW_DATA_MAXSZ; 1291 sc->fwsz = IWN5000_FWSZ; 1292 sc->sched_txfact_addr = IWN5000_SCHED_TXFACT; 1293 sc->reset_noise_gain = IWN5000_PHY_CALIB_RESET_NOISE_GAIN; 1294 sc->noise_gain = IWN5000_PHY_CALIB_NOISE_GAIN; 1295 1296 DPRINTF(sc, IWN_DEBUG_TRACE, "%s: end\n",__func__); 1297 } 1298 1299 /* 1300 * Attach the interface to 802.11 radiotap. 1301 */ 1302 static void 1303 iwn_radiotap_attach(struct iwn_softc *sc) 1304 { 1305 1306 DPRINTF(sc, IWN_DEBUG_TRACE, "->%s begin\n", __func__); 1307 ieee80211_radiotap_attach(&sc->sc_ic, 1308 &sc->sc_txtap.wt_ihdr, sizeof(sc->sc_txtap), 1309 IWN_TX_RADIOTAP_PRESENT, 1310 &sc->sc_rxtap.wr_ihdr, sizeof(sc->sc_rxtap), 1311 IWN_RX_RADIOTAP_PRESENT); 1312 DPRINTF(sc, IWN_DEBUG_TRACE, "->%s end\n", __func__); 1313 } 1314 1315 static void 1316 iwn_sysctlattach(struct iwn_softc *sc) 1317 { 1318 #ifdef IWN_DEBUG 1319 struct sysctl_ctx_list *ctx = device_get_sysctl_ctx(sc->sc_dev); 1320 struct sysctl_oid *tree = device_get_sysctl_tree(sc->sc_dev); 1321 1322 SYSCTL_ADD_INT(ctx, SYSCTL_CHILDREN(tree), OID_AUTO, 1323 "debug", CTLFLAG_RW, &sc->sc_debug, sc->sc_debug, 1324 "control debugging printfs"); 1325 #endif 1326 } 1327 1328 static struct ieee80211vap * 1329 iwn_vap_create(struct ieee80211com *ic, const char name[IFNAMSIZ], int unit, 1330 enum ieee80211_opmode opmode, int flags, 1331 const uint8_t bssid[IEEE80211_ADDR_LEN], 1332 const uint8_t mac[IEEE80211_ADDR_LEN]) 1333 { 1334 struct iwn_softc *sc = ic->ic_softc; 1335 struct iwn_vap *ivp; 1336 struct ieee80211vap *vap; 1337 1338 if (!TAILQ_EMPTY(&ic->ic_vaps)) /* only one at a time */ 1339 return NULL; 1340 1341 ivp = malloc(sizeof(struct iwn_vap), M_80211_VAP, M_WAITOK | M_ZERO); 1342 vap = &ivp->iv_vap; 1343 ieee80211_vap_setup(ic, vap, name, unit, opmode, flags, bssid); 1344 ivp->ctx = IWN_RXON_BSS_CTX; 1345 vap->iv_bmissthreshold = 10; /* override default */ 1346 /* Override with driver methods. */ 1347 ivp->iv_newstate = vap->iv_newstate; 1348 vap->iv_newstate = iwn_newstate; 1349 sc->ivap[IWN_RXON_BSS_CTX] = vap; 1350 vap->iv_ampdu_rxmax = IEEE80211_HTCAP_MAXRXAMPDU_64K; 1351 vap->iv_ampdu_density = IEEE80211_HTCAP_MPDUDENSITY_4; /* 4uS */ 1352 1353 ieee80211_ratectl_init(vap); 1354 /* Complete setup. */ 1355 ieee80211_vap_attach(vap, ieee80211_media_change, 1356 ieee80211_media_status, mac); 1357 ic->ic_opmode = opmode; 1358 return vap; 1359 } 1360 1361 static void 1362 iwn_vap_delete(struct ieee80211vap *vap) 1363 { 1364 struct iwn_vap *ivp = IWN_VAP(vap); 1365 1366 ieee80211_ratectl_deinit(vap); 1367 ieee80211_vap_detach(vap); 1368 free(ivp, M_80211_VAP); 1369 } 1370 1371 static void 1372 iwn_xmit_queue_drain(struct iwn_softc *sc) 1373 { 1374 struct mbuf *m; 1375 struct ieee80211_node *ni; 1376 1377 IWN_LOCK_ASSERT(sc); 1378 while ((m = mbufq_dequeue(&sc->sc_xmit_queue)) != NULL) { 1379 ni = (struct ieee80211_node *)m->m_pkthdr.rcvif; 1380 ieee80211_free_node(ni); 1381 m_freem(m); 1382 } 1383 } 1384 1385 static int 1386 iwn_xmit_queue_enqueue(struct iwn_softc *sc, struct mbuf *m) 1387 { 1388 1389 IWN_LOCK_ASSERT(sc); 1390 return (mbufq_enqueue(&sc->sc_xmit_queue, m)); 1391 } 1392 1393 static int 1394 iwn_detach(device_t dev) 1395 { 1396 struct iwn_softc *sc = device_get_softc(dev); 1397 int qid; 1398 1399 DPRINTF(sc, IWN_DEBUG_TRACE, "->%s begin\n", __func__); 1400 1401 if (sc->sc_ic.ic_softc != NULL) { 1402 /* Free the mbuf queue and node references */ 1403 IWN_LOCK(sc); 1404 iwn_xmit_queue_drain(sc); 1405 IWN_UNLOCK(sc); 1406 1407 iwn_stop(sc); 1408 1409 taskqueue_drain_all(sc->sc_tq); 1410 taskqueue_free(sc->sc_tq); 1411 1412 callout_drain(&sc->watchdog_to); 1413 callout_drain(&sc->scan_timeout); 1414 callout_drain(&sc->calib_to); 1415 ieee80211_ifdetach(&sc->sc_ic); 1416 } 1417 1418 /* Uninstall interrupt handler. */ 1419 if (sc->irq != NULL) { 1420 bus_teardown_intr(dev, sc->irq, sc->sc_ih); 1421 bus_release_resource(dev, SYS_RES_IRQ, rman_get_rid(sc->irq), 1422 sc->irq); 1423 pci_release_msi(dev); 1424 } 1425 1426 /* Free DMA resources. */ 1427 iwn_free_rx_ring(sc, &sc->rxq); 1428 for (qid = 0; qid < sc->ntxqs; qid++) 1429 iwn_free_tx_ring(sc, &sc->txq[qid]); 1430 iwn_free_sched(sc); 1431 iwn_free_kw(sc); 1432 if (sc->ict != NULL) 1433 iwn_free_ict(sc); 1434 iwn_free_fwmem(sc); 1435 1436 if (sc->mem != NULL) 1437 bus_release_resource(dev, SYS_RES_MEMORY, 1438 rman_get_rid(sc->mem), sc->mem); 1439 1440 if (sc->sc_cdev) { 1441 destroy_dev(sc->sc_cdev); 1442 sc->sc_cdev = NULL; 1443 } 1444 1445 DPRINTF(sc, IWN_DEBUG_TRACE, "->%s: end\n", __func__); 1446 IWN_LOCK_DESTROY(sc); 1447 return 0; 1448 } 1449 1450 static int 1451 iwn_shutdown(device_t dev) 1452 { 1453 struct iwn_softc *sc = device_get_softc(dev); 1454 1455 iwn_stop(sc); 1456 return 0; 1457 } 1458 1459 static int 1460 iwn_suspend(device_t dev) 1461 { 1462 struct iwn_softc *sc = device_get_softc(dev); 1463 1464 ieee80211_suspend_all(&sc->sc_ic); 1465 return 0; 1466 } 1467 1468 static int 1469 iwn_resume(device_t dev) 1470 { 1471 struct iwn_softc *sc = device_get_softc(dev); 1472 1473 /* Clear device-specific "PCI retry timeout" register (41h). */ 1474 pci_write_config(dev, 0x41, 0, 1); 1475 1476 ieee80211_resume_all(&sc->sc_ic); 1477 return 0; 1478 } 1479 1480 static int 1481 iwn_nic_lock(struct iwn_softc *sc) 1482 { 1483 int ntries; 1484 1485 /* Request exclusive access to NIC. */ 1486 IWN_SETBITS(sc, IWN_GP_CNTRL, IWN_GP_CNTRL_MAC_ACCESS_REQ); 1487 1488 /* Spin until we actually get the lock. */ 1489 for (ntries = 0; ntries < 1000; ntries++) { 1490 if ((IWN_READ(sc, IWN_GP_CNTRL) & 1491 (IWN_GP_CNTRL_MAC_ACCESS_ENA | IWN_GP_CNTRL_SLEEP)) == 1492 IWN_GP_CNTRL_MAC_ACCESS_ENA) 1493 return 0; 1494 DELAY(10); 1495 } 1496 return ETIMEDOUT; 1497 } 1498 1499 static __inline void 1500 iwn_nic_unlock(struct iwn_softc *sc) 1501 { 1502 IWN_CLRBITS(sc, IWN_GP_CNTRL, IWN_GP_CNTRL_MAC_ACCESS_REQ); 1503 } 1504 1505 static __inline uint32_t 1506 iwn_prph_read(struct iwn_softc *sc, uint32_t addr) 1507 { 1508 IWN_WRITE(sc, IWN_PRPH_RADDR, IWN_PRPH_DWORD | addr); 1509 IWN_BARRIER_READ_WRITE(sc); 1510 return IWN_READ(sc, IWN_PRPH_RDATA); 1511 } 1512 1513 static __inline void 1514 iwn_prph_write(struct iwn_softc *sc, uint32_t addr, uint32_t data) 1515 { 1516 IWN_WRITE(sc, IWN_PRPH_WADDR, IWN_PRPH_DWORD | addr); 1517 IWN_BARRIER_WRITE(sc); 1518 IWN_WRITE(sc, IWN_PRPH_WDATA, data); 1519 } 1520 1521 static __inline void 1522 iwn_prph_setbits(struct iwn_softc *sc, uint32_t addr, uint32_t mask) 1523 { 1524 iwn_prph_write(sc, addr, iwn_prph_read(sc, addr) | mask); 1525 } 1526 1527 static __inline void 1528 iwn_prph_clrbits(struct iwn_softc *sc, uint32_t addr, uint32_t mask) 1529 { 1530 iwn_prph_write(sc, addr, iwn_prph_read(sc, addr) & ~mask); 1531 } 1532 1533 static __inline void 1534 iwn_prph_write_region_4(struct iwn_softc *sc, uint32_t addr, 1535 const uint32_t *data, int count) 1536 { 1537 for (; count > 0; count--, data++, addr += 4) 1538 iwn_prph_write(sc, addr, *data); 1539 } 1540 1541 static __inline uint32_t 1542 iwn_mem_read(struct iwn_softc *sc, uint32_t addr) 1543 { 1544 IWN_WRITE(sc, IWN_MEM_RADDR, addr); 1545 IWN_BARRIER_READ_WRITE(sc); 1546 return IWN_READ(sc, IWN_MEM_RDATA); 1547 } 1548 1549 static __inline void 1550 iwn_mem_write(struct iwn_softc *sc, uint32_t addr, uint32_t data) 1551 { 1552 IWN_WRITE(sc, IWN_MEM_WADDR, addr); 1553 IWN_BARRIER_WRITE(sc); 1554 IWN_WRITE(sc, IWN_MEM_WDATA, data); 1555 } 1556 1557 static __inline void 1558 iwn_mem_write_2(struct iwn_softc *sc, uint32_t addr, uint16_t data) 1559 { 1560 uint32_t tmp; 1561 1562 tmp = iwn_mem_read(sc, addr & ~3); 1563 if (addr & 3) 1564 tmp = (tmp & 0x0000ffff) | data << 16; 1565 else 1566 tmp = (tmp & 0xffff0000) | data; 1567 iwn_mem_write(sc, addr & ~3, tmp); 1568 } 1569 1570 static __inline void 1571 iwn_mem_read_region_4(struct iwn_softc *sc, uint32_t addr, uint32_t *data, 1572 int count) 1573 { 1574 for (; count > 0; count--, addr += 4) 1575 *data++ = iwn_mem_read(sc, addr); 1576 } 1577 1578 static __inline void 1579 iwn_mem_set_region_4(struct iwn_softc *sc, uint32_t addr, uint32_t val, 1580 int count) 1581 { 1582 for (; count > 0; count--, addr += 4) 1583 iwn_mem_write(sc, addr, val); 1584 } 1585 1586 static int 1587 iwn_eeprom_lock(struct iwn_softc *sc) 1588 { 1589 int i, ntries; 1590 1591 for (i = 0; i < 100; i++) { 1592 /* Request exclusive access to EEPROM. */ 1593 IWN_SETBITS(sc, IWN_HW_IF_CONFIG, 1594 IWN_HW_IF_CONFIG_EEPROM_LOCKED); 1595 1596 /* Spin until we actually get the lock. */ 1597 for (ntries = 0; ntries < 100; ntries++) { 1598 if (IWN_READ(sc, IWN_HW_IF_CONFIG) & 1599 IWN_HW_IF_CONFIG_EEPROM_LOCKED) 1600 return 0; 1601 DELAY(10); 1602 } 1603 } 1604 DPRINTF(sc, IWN_DEBUG_TRACE, "->%s end timeout\n", __func__); 1605 return ETIMEDOUT; 1606 } 1607 1608 static __inline void 1609 iwn_eeprom_unlock(struct iwn_softc *sc) 1610 { 1611 IWN_CLRBITS(sc, IWN_HW_IF_CONFIG, IWN_HW_IF_CONFIG_EEPROM_LOCKED); 1612 } 1613 1614 /* 1615 * Initialize access by host to One Time Programmable ROM. 1616 * NB: This kind of ROM can be found on 1000 or 6000 Series only. 1617 */ 1618 static int 1619 iwn_init_otprom(struct iwn_softc *sc) 1620 { 1621 uint16_t prev, base, next; 1622 int count, error; 1623 1624 DPRINTF(sc, IWN_DEBUG_TRACE, "->%s begin\n", __func__); 1625 1626 /* Wait for clock stabilization before accessing prph. */ 1627 if ((error = iwn_clock_wait(sc)) != 0) 1628 return error; 1629 1630 if ((error = iwn_nic_lock(sc)) != 0) 1631 return error; 1632 iwn_prph_setbits(sc, IWN_APMG_PS, IWN_APMG_PS_RESET_REQ); 1633 DELAY(5); 1634 iwn_prph_clrbits(sc, IWN_APMG_PS, IWN_APMG_PS_RESET_REQ); 1635 iwn_nic_unlock(sc); 1636 1637 /* Set auto clock gate disable bit for HW with OTP shadow RAM. */ 1638 if (sc->base_params->shadow_ram_support) { 1639 IWN_SETBITS(sc, IWN_DBG_LINK_PWR_MGMT, 1640 IWN_RESET_LINK_PWR_MGMT_DIS); 1641 } 1642 IWN_CLRBITS(sc, IWN_EEPROM_GP, IWN_EEPROM_GP_IF_OWNER); 1643 /* Clear ECC status. */ 1644 IWN_SETBITS(sc, IWN_OTP_GP, 1645 IWN_OTP_GP_ECC_CORR_STTS | IWN_OTP_GP_ECC_UNCORR_STTS); 1646 1647 /* 1648 * Find the block before last block (contains the EEPROM image) 1649 * for HW without OTP shadow RAM. 1650 */ 1651 if (! sc->base_params->shadow_ram_support) { 1652 /* Switch to absolute addressing mode. */ 1653 IWN_CLRBITS(sc, IWN_OTP_GP, IWN_OTP_GP_RELATIVE_ACCESS); 1654 base = prev = 0; 1655 for (count = 0; count < sc->base_params->max_ll_items; 1656 count++) { 1657 error = iwn_read_prom_data(sc, base, &next, 2); 1658 if (error != 0) 1659 return error; 1660 if (next == 0) /* End of linked-list. */ 1661 break; 1662 prev = base; 1663 base = le16toh(next); 1664 } 1665 if (count == 0 || count == sc->base_params->max_ll_items) 1666 return EIO; 1667 /* Skip "next" word. */ 1668 sc->prom_base = prev + 1; 1669 } 1670 1671 DPRINTF(sc, IWN_DEBUG_TRACE, "->%s end\n", __func__); 1672 1673 return 0; 1674 } 1675 1676 static int 1677 iwn_read_prom_data(struct iwn_softc *sc, uint32_t addr, void *data, int count) 1678 { 1679 uint8_t *out = data; 1680 uint32_t val, tmp; 1681 int ntries; 1682 1683 DPRINTF(sc, IWN_DEBUG_TRACE, "->%s begin\n", __func__); 1684 1685 addr += sc->prom_base; 1686 for (; count > 0; count -= 2, addr++) { 1687 IWN_WRITE(sc, IWN_EEPROM, addr << 2); 1688 for (ntries = 0; ntries < 20; ntries++) { 1689 val = IWN_READ(sc, IWN_EEPROM); 1690 if (val & IWN_EEPROM_READ_VALID) 1691 break; 1692 DELAY(5); 1693 } 1694 if (ntries == 20) { 1695 device_printf(sc->sc_dev, 1696 "timeout reading ROM at 0x%x\n", addr); 1697 return ETIMEDOUT; 1698 } 1699 if (sc->sc_flags & IWN_FLAG_HAS_OTPROM) { 1700 /* OTPROM, check for ECC errors. */ 1701 tmp = IWN_READ(sc, IWN_OTP_GP); 1702 if (tmp & IWN_OTP_GP_ECC_UNCORR_STTS) { 1703 device_printf(sc->sc_dev, 1704 "OTPROM ECC error at 0x%x\n", addr); 1705 return EIO; 1706 } 1707 if (tmp & IWN_OTP_GP_ECC_CORR_STTS) { 1708 /* Correctable ECC error, clear bit. */ 1709 IWN_SETBITS(sc, IWN_OTP_GP, 1710 IWN_OTP_GP_ECC_CORR_STTS); 1711 } 1712 } 1713 *out++ = val >> 16; 1714 if (count > 1) 1715 *out++ = val >> 24; 1716 } 1717 1718 DPRINTF(sc, IWN_DEBUG_TRACE, "->%s end\n", __func__); 1719 1720 return 0; 1721 } 1722 1723 static void 1724 iwn_dma_map_addr(void *arg, bus_dma_segment_t *segs, int nsegs, int error) 1725 { 1726 if (error != 0) 1727 return; 1728 KASSERT(nsegs == 1, ("too many DMA segments, %d should be 1", nsegs)); 1729 *(bus_addr_t *)arg = segs[0].ds_addr; 1730 } 1731 1732 static int 1733 iwn_dma_contig_alloc(struct iwn_softc *sc, struct iwn_dma_info *dma, 1734 void **kvap, bus_size_t size, bus_size_t alignment) 1735 { 1736 int error; 1737 1738 dma->tag = NULL; 1739 dma->size = size; 1740 1741 error = bus_dma_tag_create(bus_get_dma_tag(sc->sc_dev), alignment, 1742 0, BUS_SPACE_MAXADDR_32BIT, BUS_SPACE_MAXADDR, NULL, NULL, size, 1743 1, size, 0, NULL, NULL, &dma->tag); 1744 if (error != 0) 1745 goto fail; 1746 1747 error = bus_dmamem_alloc(dma->tag, (void **)&dma->vaddr, 1748 BUS_DMA_NOWAIT | BUS_DMA_ZERO | BUS_DMA_COHERENT, &dma->map); 1749 if (error != 0) 1750 goto fail; 1751 1752 error = bus_dmamap_load(dma->tag, dma->map, dma->vaddr, size, 1753 iwn_dma_map_addr, &dma->paddr, BUS_DMA_NOWAIT); 1754 if (error != 0) 1755 goto fail; 1756 1757 bus_dmamap_sync(dma->tag, dma->map, BUS_DMASYNC_PREWRITE); 1758 1759 if (kvap != NULL) 1760 *kvap = dma->vaddr; 1761 1762 return 0; 1763 1764 fail: iwn_dma_contig_free(dma); 1765 return error; 1766 } 1767 1768 static void 1769 iwn_dma_contig_free(struct iwn_dma_info *dma) 1770 { 1771 if (dma->vaddr != NULL) { 1772 bus_dmamap_sync(dma->tag, dma->map, 1773 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); 1774 bus_dmamap_unload(dma->tag, dma->map); 1775 bus_dmamem_free(dma->tag, dma->vaddr, dma->map); 1776 dma->vaddr = NULL; 1777 } 1778 if (dma->tag != NULL) { 1779 bus_dma_tag_destroy(dma->tag); 1780 dma->tag = NULL; 1781 } 1782 } 1783 1784 static int 1785 iwn_alloc_sched(struct iwn_softc *sc) 1786 { 1787 /* TX scheduler rings must be aligned on a 1KB boundary. */ 1788 return iwn_dma_contig_alloc(sc, &sc->sched_dma, (void **)&sc->sched, 1789 sc->schedsz, 1024); 1790 } 1791 1792 static void 1793 iwn_free_sched(struct iwn_softc *sc) 1794 { 1795 iwn_dma_contig_free(&sc->sched_dma); 1796 } 1797 1798 static int 1799 iwn_alloc_kw(struct iwn_softc *sc) 1800 { 1801 /* "Keep Warm" page must be aligned on a 4KB boundary. */ 1802 return iwn_dma_contig_alloc(sc, &sc->kw_dma, NULL, 4096, 4096); 1803 } 1804 1805 static void 1806 iwn_free_kw(struct iwn_softc *sc) 1807 { 1808 iwn_dma_contig_free(&sc->kw_dma); 1809 } 1810 1811 static int 1812 iwn_alloc_ict(struct iwn_softc *sc) 1813 { 1814 /* ICT table must be aligned on a 4KB boundary. */ 1815 return iwn_dma_contig_alloc(sc, &sc->ict_dma, (void **)&sc->ict, 1816 IWN_ICT_SIZE, 4096); 1817 } 1818 1819 static void 1820 iwn_free_ict(struct iwn_softc *sc) 1821 { 1822 iwn_dma_contig_free(&sc->ict_dma); 1823 } 1824 1825 static int 1826 iwn_alloc_fwmem(struct iwn_softc *sc) 1827 { 1828 /* Must be aligned on a 16-byte boundary. */ 1829 return iwn_dma_contig_alloc(sc, &sc->fw_dma, NULL, sc->fwsz, 16); 1830 } 1831 1832 static void 1833 iwn_free_fwmem(struct iwn_softc *sc) 1834 { 1835 iwn_dma_contig_free(&sc->fw_dma); 1836 } 1837 1838 static int 1839 iwn_alloc_rx_ring(struct iwn_softc *sc, struct iwn_rx_ring *ring) 1840 { 1841 bus_size_t size; 1842 int i, error; 1843 1844 ring->cur = 0; 1845 1846 DPRINTF(sc, IWN_DEBUG_TRACE, "->%s begin\n", __func__); 1847 1848 /* Allocate RX descriptors (256-byte aligned). */ 1849 size = IWN_RX_RING_COUNT * sizeof (uint32_t); 1850 error = iwn_dma_contig_alloc(sc, &ring->desc_dma, (void **)&ring->desc, 1851 size, 256); 1852 if (error != 0) { 1853 device_printf(sc->sc_dev, 1854 "%s: could not allocate RX ring DMA memory, error %d\n", 1855 __func__, error); 1856 goto fail; 1857 } 1858 1859 /* Allocate RX status area (16-byte aligned). */ 1860 error = iwn_dma_contig_alloc(sc, &ring->stat_dma, (void **)&ring->stat, 1861 sizeof (struct iwn_rx_status), 16); 1862 if (error != 0) { 1863 device_printf(sc->sc_dev, 1864 "%s: could not allocate RX status DMA memory, error %d\n", 1865 __func__, error); 1866 goto fail; 1867 } 1868 1869 /* Create RX buffer DMA tag. */ 1870 error = bus_dma_tag_create(bus_get_dma_tag(sc->sc_dev), 1, 0, 1871 BUS_SPACE_MAXADDR_32BIT, BUS_SPACE_MAXADDR, NULL, NULL, 1872 IWN_RBUF_SIZE, 1, IWN_RBUF_SIZE, 0, NULL, NULL, &ring->data_dmat); 1873 if (error != 0) { 1874 device_printf(sc->sc_dev, 1875 "%s: could not create RX buf DMA tag, error %d\n", 1876 __func__, error); 1877 goto fail; 1878 } 1879 1880 /* 1881 * Allocate and map RX buffers. 1882 */ 1883 for (i = 0; i < IWN_RX_RING_COUNT; i++) { 1884 struct iwn_rx_data *data = &ring->data[i]; 1885 bus_addr_t paddr; 1886 1887 error = bus_dmamap_create(ring->data_dmat, 0, &data->map); 1888 if (error != 0) { 1889 device_printf(sc->sc_dev, 1890 "%s: could not create RX buf DMA map, error %d\n", 1891 __func__, error); 1892 goto fail; 1893 } 1894 1895 data->m = m_getjcl(M_NOWAIT, MT_DATA, M_PKTHDR, 1896 IWN_RBUF_SIZE); 1897 if (data->m == NULL) { 1898 device_printf(sc->sc_dev, 1899 "%s: could not allocate RX mbuf\n", __func__); 1900 error = ENOBUFS; 1901 goto fail; 1902 } 1903 1904 error = bus_dmamap_load(ring->data_dmat, data->map, 1905 mtod(data->m, void *), IWN_RBUF_SIZE, iwn_dma_map_addr, 1906 &paddr, BUS_DMA_NOWAIT); 1907 if (error != 0 && error != EFBIG) { 1908 device_printf(sc->sc_dev, 1909 "%s: can't map mbuf, error %d\n", __func__, 1910 error); 1911 goto fail; 1912 } 1913 1914 bus_dmamap_sync(ring->data_dmat, data->map, 1915 BUS_DMASYNC_PREREAD); 1916 1917 /* Set physical address of RX buffer (256-byte aligned). */ 1918 ring->desc[i] = htole32(paddr >> 8); 1919 } 1920 1921 bus_dmamap_sync(ring->desc_dma.tag, ring->desc_dma.map, 1922 BUS_DMASYNC_PREWRITE); 1923 1924 DPRINTF(sc, IWN_DEBUG_TRACE, "->%s: end\n",__func__); 1925 1926 return 0; 1927 1928 fail: iwn_free_rx_ring(sc, ring); 1929 1930 DPRINTF(sc, IWN_DEBUG_TRACE, "->%s: end in error\n",__func__); 1931 1932 return error; 1933 } 1934 1935 static void 1936 iwn_reset_rx_ring(struct iwn_softc *sc, struct iwn_rx_ring *ring) 1937 { 1938 int ntries; 1939 1940 DPRINTF(sc, IWN_DEBUG_TRACE, "->Doing %s\n", __func__); 1941 1942 if (iwn_nic_lock(sc) == 0) { 1943 IWN_WRITE(sc, IWN_FH_RX_CONFIG, 0); 1944 for (ntries = 0; ntries < 1000; ntries++) { 1945 if (IWN_READ(sc, IWN_FH_RX_STATUS) & 1946 IWN_FH_RX_STATUS_IDLE) 1947 break; 1948 DELAY(10); 1949 } 1950 iwn_nic_unlock(sc); 1951 } 1952 ring->cur = 0; 1953 sc->last_rx_valid = 0; 1954 } 1955 1956 static void 1957 iwn_free_rx_ring(struct iwn_softc *sc, struct iwn_rx_ring *ring) 1958 { 1959 int i; 1960 1961 DPRINTF(sc, IWN_DEBUG_TRACE, "->Doing %s \n", __func__); 1962 1963 iwn_dma_contig_free(&ring->desc_dma); 1964 iwn_dma_contig_free(&ring->stat_dma); 1965 1966 for (i = 0; i < IWN_RX_RING_COUNT; i++) { 1967 struct iwn_rx_data *data = &ring->data[i]; 1968 1969 if (data->m != NULL) { 1970 bus_dmamap_sync(ring->data_dmat, data->map, 1971 BUS_DMASYNC_POSTREAD); 1972 bus_dmamap_unload(ring->data_dmat, data->map); 1973 m_freem(data->m); 1974 data->m = NULL; 1975 } 1976 if (data->map != NULL) 1977 bus_dmamap_destroy(ring->data_dmat, data->map); 1978 } 1979 if (ring->data_dmat != NULL) { 1980 bus_dma_tag_destroy(ring->data_dmat); 1981 ring->data_dmat = NULL; 1982 } 1983 } 1984 1985 static int 1986 iwn_alloc_tx_ring(struct iwn_softc *sc, struct iwn_tx_ring *ring, int qid) 1987 { 1988 bus_addr_t paddr; 1989 bus_size_t size; 1990 int i, error; 1991 1992 ring->qid = qid; 1993 ring->queued = 0; 1994 ring->cur = 0; 1995 1996 DPRINTF(sc, IWN_DEBUG_TRACE, "->%s begin\n", __func__); 1997 1998 /* Allocate TX descriptors (256-byte aligned). */ 1999 size = IWN_TX_RING_COUNT * sizeof (struct iwn_tx_desc); 2000 error = iwn_dma_contig_alloc(sc, &ring->desc_dma, (void **)&ring->desc, 2001 size, 256); 2002 if (error != 0) { 2003 device_printf(sc->sc_dev, 2004 "%s: could not allocate TX ring DMA memory, error %d\n", 2005 __func__, error); 2006 goto fail; 2007 } 2008 2009 size = IWN_TX_RING_COUNT * sizeof (struct iwn_tx_cmd); 2010 error = iwn_dma_contig_alloc(sc, &ring->cmd_dma, (void **)&ring->cmd, 2011 size, 4); 2012 if (error != 0) { 2013 device_printf(sc->sc_dev, 2014 "%s: could not allocate TX cmd DMA memory, error %d\n", 2015 __func__, error); 2016 goto fail; 2017 } 2018 2019 error = bus_dma_tag_create(bus_get_dma_tag(sc->sc_dev), 1, 0, 2020 BUS_SPACE_MAXADDR_32BIT, BUS_SPACE_MAXADDR, NULL, NULL, MCLBYTES, 2021 IWN_MAX_SCATTER - 1, MCLBYTES, 0, NULL, NULL, &ring->data_dmat); 2022 if (error != 0) { 2023 device_printf(sc->sc_dev, 2024 "%s: could not create TX buf DMA tag, error %d\n", 2025 __func__, error); 2026 goto fail; 2027 } 2028 2029 paddr = ring->cmd_dma.paddr; 2030 for (i = 0; i < IWN_TX_RING_COUNT; i++) { 2031 struct iwn_tx_data *data = &ring->data[i]; 2032 2033 data->cmd_paddr = paddr; 2034 data->scratch_paddr = paddr + 12; 2035 paddr += sizeof (struct iwn_tx_cmd); 2036 2037 error = bus_dmamap_create(ring->data_dmat, 0, &data->map); 2038 if (error != 0) { 2039 device_printf(sc->sc_dev, 2040 "%s: could not create TX buf DMA map, error %d\n", 2041 __func__, error); 2042 goto fail; 2043 } 2044 } 2045 2046 DPRINTF(sc, IWN_DEBUG_TRACE, "->%s end\n", __func__); 2047 2048 return 0; 2049 2050 fail: iwn_free_tx_ring(sc, ring); 2051 DPRINTF(sc, IWN_DEBUG_TRACE, "->%s end in error\n", __func__); 2052 return error; 2053 } 2054 2055 static void 2056 iwn_reset_tx_ring(struct iwn_softc *sc, struct iwn_tx_ring *ring) 2057 { 2058 int i; 2059 2060 DPRINTF(sc, IWN_DEBUG_TRACE, "->doing %s \n", __func__); 2061 2062 for (i = 0; i < IWN_TX_RING_COUNT; i++) { 2063 struct iwn_tx_data *data = &ring->data[i]; 2064 2065 if (data->m != NULL) { 2066 bus_dmamap_sync(ring->data_dmat, data->map, 2067 BUS_DMASYNC_POSTWRITE); 2068 bus_dmamap_unload(ring->data_dmat, data->map); 2069 m_freem(data->m); 2070 data->m = NULL; 2071 } 2072 if (data->ni != NULL) { 2073 ieee80211_free_node(data->ni); 2074 data->ni = NULL; 2075 } 2076 data->remapped = 0; 2077 data->long_retries = 0; 2078 } 2079 /* Clear TX descriptors. */ 2080 memset(ring->desc, 0, ring->desc_dma.size); 2081 bus_dmamap_sync(ring->desc_dma.tag, ring->desc_dma.map, 2082 BUS_DMASYNC_PREWRITE); 2083 sc->qfullmsk &= ~(1 << ring->qid); 2084 ring->queued = 0; 2085 ring->cur = 0; 2086 } 2087 2088 static void 2089 iwn_free_tx_ring(struct iwn_softc *sc, struct iwn_tx_ring *ring) 2090 { 2091 int i; 2092 2093 DPRINTF(sc, IWN_DEBUG_TRACE, "->Doing %s \n", __func__); 2094 2095 iwn_dma_contig_free(&ring->desc_dma); 2096 iwn_dma_contig_free(&ring->cmd_dma); 2097 2098 for (i = 0; i < IWN_TX_RING_COUNT; i++) { 2099 struct iwn_tx_data *data = &ring->data[i]; 2100 2101 if (data->m != NULL) { 2102 bus_dmamap_sync(ring->data_dmat, data->map, 2103 BUS_DMASYNC_POSTWRITE); 2104 bus_dmamap_unload(ring->data_dmat, data->map); 2105 m_freem(data->m); 2106 } 2107 if (data->map != NULL) 2108 bus_dmamap_destroy(ring->data_dmat, data->map); 2109 } 2110 if (ring->data_dmat != NULL) { 2111 bus_dma_tag_destroy(ring->data_dmat); 2112 ring->data_dmat = NULL; 2113 } 2114 } 2115 2116 static void 2117 iwn_check_tx_ring(struct iwn_softc *sc, int qid) 2118 { 2119 struct iwn_tx_ring *ring = &sc->txq[qid]; 2120 2121 KASSERT(ring->queued >= 0, ("%s: ring->queued (%d) for queue %d < 0!", 2122 __func__, ring->queued, qid)); 2123 2124 if (qid >= sc->firstaggqueue) { 2125 struct iwn_ops *ops = &sc->ops; 2126 struct ieee80211_tx_ampdu *tap = sc->qid2tap[qid]; 2127 2128 if (ring->queued == 0 && !IEEE80211_AMPDU_RUNNING(tap)) { 2129 uint16_t ssn = tap->txa_start & 0xfff; 2130 uint8_t tid = tap->txa_tid; 2131 int *res = tap->txa_private; 2132 2133 iwn_nic_lock(sc); 2134 ops->ampdu_tx_stop(sc, qid, tid, ssn); 2135 iwn_nic_unlock(sc); 2136 2137 sc->qid2tap[qid] = NULL; 2138 free(res, M_DEVBUF); 2139 } 2140 } 2141 2142 if (ring->queued < IWN_TX_RING_LOMARK) { 2143 sc->qfullmsk &= ~(1 << qid); 2144 2145 if (ring->queued == 0) 2146 sc->sc_tx_timer = 0; 2147 else 2148 sc->sc_tx_timer = 5; 2149 } 2150 } 2151 2152 static void 2153 iwn5000_ict_reset(struct iwn_softc *sc) 2154 { 2155 /* Disable interrupts. */ 2156 IWN_WRITE(sc, IWN_INT_MASK, 0); 2157 2158 /* Reset ICT table. */ 2159 memset(sc->ict, 0, IWN_ICT_SIZE); 2160 sc->ict_cur = 0; 2161 2162 bus_dmamap_sync(sc->ict_dma.tag, sc->ict_dma.map, 2163 BUS_DMASYNC_PREWRITE); 2164 2165 /* Set physical address of ICT table (4KB aligned). */ 2166 DPRINTF(sc, IWN_DEBUG_RESET, "%s: enabling ICT\n", __func__); 2167 IWN_WRITE(sc, IWN_DRAM_INT_TBL, IWN_DRAM_INT_TBL_ENABLE | 2168 IWN_DRAM_INT_TBL_WRAP_CHECK | sc->ict_dma.paddr >> 12); 2169 2170 /* Enable periodic RX interrupt. */ 2171 sc->int_mask |= IWN_INT_RX_PERIODIC; 2172 /* Switch to ICT interrupt mode in driver. */ 2173 sc->sc_flags |= IWN_FLAG_USE_ICT; 2174 2175 /* Re-enable interrupts. */ 2176 IWN_WRITE(sc, IWN_INT, 0xffffffff); 2177 IWN_WRITE(sc, IWN_INT_MASK, sc->int_mask); 2178 } 2179 2180 static int 2181 iwn_read_eeprom(struct iwn_softc *sc, uint8_t macaddr[IEEE80211_ADDR_LEN]) 2182 { 2183 struct iwn_ops *ops = &sc->ops; 2184 uint16_t val; 2185 int error; 2186 2187 DPRINTF(sc, IWN_DEBUG_TRACE, "->%s begin\n", __func__); 2188 2189 /* Check whether adapter has an EEPROM or an OTPROM. */ 2190 if (sc->hw_type >= IWN_HW_REV_TYPE_1000 && 2191 (IWN_READ(sc, IWN_OTP_GP) & IWN_OTP_GP_DEV_SEL_OTP)) 2192 sc->sc_flags |= IWN_FLAG_HAS_OTPROM; 2193 DPRINTF(sc, IWN_DEBUG_RESET, "%s found\n", 2194 (sc->sc_flags & IWN_FLAG_HAS_OTPROM) ? "OTPROM" : "EEPROM"); 2195 2196 /* Adapter has to be powered on for EEPROM access to work. */ 2197 if ((error = iwn_apm_init(sc)) != 0) { 2198 device_printf(sc->sc_dev, 2199 "%s: could not power ON adapter, error %d\n", __func__, 2200 error); 2201 return error; 2202 } 2203 2204 if ((IWN_READ(sc, IWN_EEPROM_GP) & 0x7) == 0) { 2205 device_printf(sc->sc_dev, "%s: bad ROM signature\n", __func__); 2206 return EIO; 2207 } 2208 if ((error = iwn_eeprom_lock(sc)) != 0) { 2209 device_printf(sc->sc_dev, "%s: could not lock ROM, error %d\n", 2210 __func__, error); 2211 return error; 2212 } 2213 if (sc->sc_flags & IWN_FLAG_HAS_OTPROM) { 2214 if ((error = iwn_init_otprom(sc)) != 0) { 2215 device_printf(sc->sc_dev, 2216 "%s: could not initialize OTPROM, error %d\n", 2217 __func__, error); 2218 return error; 2219 } 2220 } 2221 2222 iwn_read_prom_data(sc, IWN_EEPROM_SKU_CAP, &val, 2); 2223 DPRINTF(sc, IWN_DEBUG_RESET, "SKU capabilities=0x%04x\n", le16toh(val)); 2224 /* Check if HT support is bonded out. */ 2225 if (val & htole16(IWN_EEPROM_SKU_CAP_11N)) 2226 sc->sc_flags |= IWN_FLAG_HAS_11N; 2227 2228 iwn_read_prom_data(sc, IWN_EEPROM_RFCFG, &val, 2); 2229 sc->rfcfg = le16toh(val); 2230 DPRINTF(sc, IWN_DEBUG_RESET, "radio config=0x%04x\n", sc->rfcfg); 2231 /* Read Tx/Rx chains from ROM unless it's known to be broken. */ 2232 if (sc->txchainmask == 0) 2233 sc->txchainmask = IWN_RFCFG_TXANTMSK(sc->rfcfg); 2234 if (sc->rxchainmask == 0) 2235 sc->rxchainmask = IWN_RFCFG_RXANTMSK(sc->rfcfg); 2236 2237 /* Read MAC address. */ 2238 iwn_read_prom_data(sc, IWN_EEPROM_MAC, macaddr, 6); 2239 2240 /* Read adapter-specific information from EEPROM. */ 2241 ops->read_eeprom(sc); 2242 2243 iwn_apm_stop(sc); /* Power OFF adapter. */ 2244 2245 iwn_eeprom_unlock(sc); 2246 2247 DPRINTF(sc, IWN_DEBUG_TRACE, "->%s end\n", __func__); 2248 2249 return 0; 2250 } 2251 2252 static void 2253 iwn4965_read_eeprom(struct iwn_softc *sc) 2254 { 2255 uint32_t addr; 2256 uint16_t val; 2257 int i; 2258 2259 DPRINTF(sc, IWN_DEBUG_TRACE, "->%s begin\n", __func__); 2260 2261 /* Read regulatory domain (4 ASCII characters). */ 2262 iwn_read_prom_data(sc, IWN4965_EEPROM_DOMAIN, sc->eeprom_domain, 4); 2263 2264 /* Read the list of authorized channels (20MHz & 40MHz). */ 2265 for (i = 0; i < IWN_NBANDS - 1; i++) { 2266 addr = iwn4965_regulatory_bands[i]; 2267 iwn_read_eeprom_channels(sc, i, addr); 2268 } 2269 2270 /* Read maximum allowed TX power for 2GHz and 5GHz bands. */ 2271 iwn_read_prom_data(sc, IWN4965_EEPROM_MAXPOW, &val, 2); 2272 sc->maxpwr2GHz = val & 0xff; 2273 sc->maxpwr5GHz = val >> 8; 2274 /* Check that EEPROM values are within valid range. */ 2275 if (sc->maxpwr5GHz < 20 || sc->maxpwr5GHz > 50) 2276 sc->maxpwr5GHz = 38; 2277 if (sc->maxpwr2GHz < 20 || sc->maxpwr2GHz > 50) 2278 sc->maxpwr2GHz = 38; 2279 DPRINTF(sc, IWN_DEBUG_RESET, "maxpwr 2GHz=%d 5GHz=%d\n", 2280 sc->maxpwr2GHz, sc->maxpwr5GHz); 2281 2282 /* Read samples for each TX power group. */ 2283 iwn_read_prom_data(sc, IWN4965_EEPROM_BANDS, sc->bands, 2284 sizeof sc->bands); 2285 2286 /* Read voltage at which samples were taken. */ 2287 iwn_read_prom_data(sc, IWN4965_EEPROM_VOLTAGE, &val, 2); 2288 sc->eeprom_voltage = (int16_t)le16toh(val); 2289 DPRINTF(sc, IWN_DEBUG_RESET, "voltage=%d (in 0.3V)\n", 2290 sc->eeprom_voltage); 2291 2292 #ifdef IWN_DEBUG 2293 /* Print samples. */ 2294 if (sc->sc_debug & IWN_DEBUG_ANY) { 2295 for (i = 0; i < IWN_NBANDS - 1; i++) 2296 iwn4965_print_power_group(sc, i); 2297 } 2298 #endif 2299 2300 DPRINTF(sc, IWN_DEBUG_TRACE, "->%s end\n", __func__); 2301 } 2302 2303 #ifdef IWN_DEBUG 2304 static void 2305 iwn4965_print_power_group(struct iwn_softc *sc, int i) 2306 { 2307 struct iwn4965_eeprom_band *band = &sc->bands[i]; 2308 struct iwn4965_eeprom_chan_samples *chans = band->chans; 2309 int j, c; 2310 2311 printf("===band %d===\n", i); 2312 printf("chan lo=%d, chan hi=%d\n", band->lo, band->hi); 2313 printf("chan1 num=%d\n", chans[0].num); 2314 for (c = 0; c < 2; c++) { 2315 for (j = 0; j < IWN_NSAMPLES; j++) { 2316 printf("chain %d, sample %d: temp=%d gain=%d " 2317 "power=%d pa_det=%d\n", c, j, 2318 chans[0].samples[c][j].temp, 2319 chans[0].samples[c][j].gain, 2320 chans[0].samples[c][j].power, 2321 chans[0].samples[c][j].pa_det); 2322 } 2323 } 2324 printf("chan2 num=%d\n", chans[1].num); 2325 for (c = 0; c < 2; c++) { 2326 for (j = 0; j < IWN_NSAMPLES; j++) { 2327 printf("chain %d, sample %d: temp=%d gain=%d " 2328 "power=%d pa_det=%d\n", c, j, 2329 chans[1].samples[c][j].temp, 2330 chans[1].samples[c][j].gain, 2331 chans[1].samples[c][j].power, 2332 chans[1].samples[c][j].pa_det); 2333 } 2334 } 2335 } 2336 #endif 2337 2338 static void 2339 iwn5000_read_eeprom(struct iwn_softc *sc) 2340 { 2341 struct iwn5000_eeprom_calib_hdr hdr; 2342 int32_t volt; 2343 uint32_t base, addr; 2344 uint16_t val; 2345 int i; 2346 2347 DPRINTF(sc, IWN_DEBUG_TRACE, "->%s begin\n", __func__); 2348 2349 /* Read regulatory domain (4 ASCII characters). */ 2350 iwn_read_prom_data(sc, IWN5000_EEPROM_REG, &val, 2); 2351 base = le16toh(val); 2352 iwn_read_prom_data(sc, base + IWN5000_EEPROM_DOMAIN, 2353 sc->eeprom_domain, 4); 2354 2355 /* Read the list of authorized channels (20MHz & 40MHz). */ 2356 for (i = 0; i < IWN_NBANDS - 1; i++) { 2357 addr = base + sc->base_params->regulatory_bands[i]; 2358 iwn_read_eeprom_channels(sc, i, addr); 2359 } 2360 2361 /* Read enhanced TX power information for 6000 Series. */ 2362 if (sc->base_params->enhanced_TX_power) 2363 iwn_read_eeprom_enhinfo(sc); 2364 2365 iwn_read_prom_data(sc, IWN5000_EEPROM_CAL, &val, 2); 2366 base = le16toh(val); 2367 iwn_read_prom_data(sc, base, &hdr, sizeof hdr); 2368 DPRINTF(sc, IWN_DEBUG_CALIBRATE, 2369 "%s: calib version=%u pa type=%u voltage=%u\n", __func__, 2370 hdr.version, hdr.pa_type, le16toh(hdr.volt)); 2371 sc->calib_ver = hdr.version; 2372 2373 if (sc->base_params->calib_need & IWN_FLG_NEED_PHY_CALIB_TEMP_OFFSETv2) { 2374 sc->eeprom_voltage = le16toh(hdr.volt); 2375 iwn_read_prom_data(sc, base + IWN5000_EEPROM_TEMP, &val, 2); 2376 sc->eeprom_temp_high=le16toh(val); 2377 iwn_read_prom_data(sc, base + IWN5000_EEPROM_VOLT, &val, 2); 2378 sc->eeprom_temp = le16toh(val); 2379 } 2380 2381 if (sc->hw_type == IWN_HW_REV_TYPE_5150) { 2382 /* Compute temperature offset. */ 2383 iwn_read_prom_data(sc, base + IWN5000_EEPROM_TEMP, &val, 2); 2384 sc->eeprom_temp = le16toh(val); 2385 iwn_read_prom_data(sc, base + IWN5000_EEPROM_VOLT, &val, 2); 2386 volt = le16toh(val); 2387 sc->temp_off = sc->eeprom_temp - (volt / -5); 2388 DPRINTF(sc, IWN_DEBUG_CALIBRATE, "temp=%d volt=%d offset=%dK\n", 2389 sc->eeprom_temp, volt, sc->temp_off); 2390 } else { 2391 /* Read crystal calibration. */ 2392 iwn_read_prom_data(sc, base + IWN5000_EEPROM_CRYSTAL, 2393 &sc->eeprom_crystal, sizeof (uint32_t)); 2394 DPRINTF(sc, IWN_DEBUG_CALIBRATE, "crystal calibration 0x%08x\n", 2395 le32toh(sc->eeprom_crystal)); 2396 } 2397 2398 DPRINTF(sc, IWN_DEBUG_TRACE, "->%s end\n", __func__); 2399 2400 } 2401 2402 /* 2403 * Translate EEPROM flags to net80211. 2404 */ 2405 static uint32_t 2406 iwn_eeprom_channel_flags(struct iwn_eeprom_chan *channel) 2407 { 2408 uint32_t nflags; 2409 2410 nflags = 0; 2411 if ((channel->flags & IWN_EEPROM_CHAN_ACTIVE) == 0) 2412 nflags |= IEEE80211_CHAN_PASSIVE; 2413 if ((channel->flags & IWN_EEPROM_CHAN_IBSS) == 0) 2414 nflags |= IEEE80211_CHAN_NOADHOC; 2415 if (channel->flags & IWN_EEPROM_CHAN_RADAR) { 2416 nflags |= IEEE80211_CHAN_DFS; 2417 /* XXX apparently IBSS may still be marked */ 2418 nflags |= IEEE80211_CHAN_NOADHOC; 2419 } 2420 2421 return nflags; 2422 } 2423 2424 static void 2425 iwn_read_eeprom_band(struct iwn_softc *sc, int n, int maxchans, int *nchans, 2426 struct ieee80211_channel chans[]) 2427 { 2428 struct iwn_eeprom_chan *channels = sc->eeprom_channels[n]; 2429 const struct iwn_chan_band *band = &iwn_bands[n]; 2430 uint8_t bands[IEEE80211_MODE_BYTES]; 2431 uint8_t chan; 2432 int i, error, nflags; 2433 2434 DPRINTF(sc, IWN_DEBUG_TRACE, "->%s begin\n", __func__); 2435 2436 memset(bands, 0, sizeof(bands)); 2437 if (n == 0) { 2438 setbit(bands, IEEE80211_MODE_11B); 2439 setbit(bands, IEEE80211_MODE_11G); 2440 if (sc->sc_flags & IWN_FLAG_HAS_11N) 2441 setbit(bands, IEEE80211_MODE_11NG); 2442 } else { 2443 setbit(bands, IEEE80211_MODE_11A); 2444 if (sc->sc_flags & IWN_FLAG_HAS_11N) 2445 setbit(bands, IEEE80211_MODE_11NA); 2446 } 2447 2448 for (i = 0; i < band->nchan; i++) { 2449 if (!(channels[i].flags & IWN_EEPROM_CHAN_VALID)) { 2450 DPRINTF(sc, IWN_DEBUG_RESET, 2451 "skip chan %d flags 0x%x maxpwr %d\n", 2452 band->chan[i], channels[i].flags, 2453 channels[i].maxpwr); 2454 continue; 2455 } 2456 2457 chan = band->chan[i]; 2458 nflags = iwn_eeprom_channel_flags(&channels[i]); 2459 error = ieee80211_add_channel(chans, maxchans, nchans, 2460 chan, 0, channels[i].maxpwr, nflags, bands); 2461 if (error != 0) 2462 break; 2463 2464 /* Save maximum allowed TX power for this channel. */ 2465 /* XXX wrong */ 2466 sc->maxpwr[chan] = channels[i].maxpwr; 2467 2468 DPRINTF(sc, IWN_DEBUG_RESET, 2469 "add chan %d flags 0x%x maxpwr %d\n", chan, 2470 channels[i].flags, channels[i].maxpwr); 2471 } 2472 2473 DPRINTF(sc, IWN_DEBUG_TRACE, "->%s end\n", __func__); 2474 2475 } 2476 2477 static void 2478 iwn_read_eeprom_ht40(struct iwn_softc *sc, int n, int maxchans, int *nchans, 2479 struct ieee80211_channel chans[]) 2480 { 2481 struct iwn_eeprom_chan *channels = sc->eeprom_channels[n]; 2482 const struct iwn_chan_band *band = &iwn_bands[n]; 2483 uint8_t chan; 2484 int i, error, nflags; 2485 2486 DPRINTF(sc, IWN_DEBUG_TRACE, "->%s start\n", __func__); 2487 2488 if (!(sc->sc_flags & IWN_FLAG_HAS_11N)) { 2489 DPRINTF(sc, IWN_DEBUG_TRACE, "->%s end no 11n\n", __func__); 2490 return; 2491 } 2492 2493 for (i = 0; i < band->nchan; i++) { 2494 if (!(channels[i].flags & IWN_EEPROM_CHAN_VALID)) { 2495 DPRINTF(sc, IWN_DEBUG_RESET, 2496 "skip chan %d flags 0x%x maxpwr %d\n", 2497 band->chan[i], channels[i].flags, 2498 channels[i].maxpwr); 2499 continue; 2500 } 2501 2502 chan = band->chan[i]; 2503 nflags = iwn_eeprom_channel_flags(&channels[i]); 2504 nflags |= (n == 5 ? IEEE80211_CHAN_G : IEEE80211_CHAN_A); 2505 error = ieee80211_add_channel_ht40(chans, maxchans, nchans, 2506 chan, channels[i].maxpwr, nflags); 2507 switch (error) { 2508 case EINVAL: 2509 device_printf(sc->sc_dev, 2510 "%s: no entry for channel %d\n", __func__, chan); 2511 continue; 2512 case ENOENT: 2513 DPRINTF(sc, IWN_DEBUG_RESET, 2514 "%s: skip chan %d, extension channel not found\n", 2515 __func__, chan); 2516 continue; 2517 case ENOBUFS: 2518 device_printf(sc->sc_dev, 2519 "%s: channel table is full!\n", __func__); 2520 break; 2521 case 0: 2522 DPRINTF(sc, IWN_DEBUG_RESET, 2523 "add ht40 chan %d flags 0x%x maxpwr %d\n", 2524 chan, channels[i].flags, channels[i].maxpwr); 2525 /* FALLTHROUGH */ 2526 default: 2527 break; 2528 } 2529 } 2530 2531 DPRINTF(sc, IWN_DEBUG_TRACE, "->%s end\n", __func__); 2532 2533 } 2534 2535 static void 2536 iwn_read_eeprom_channels(struct iwn_softc *sc, int n, uint32_t addr) 2537 { 2538 struct ieee80211com *ic = &sc->sc_ic; 2539 2540 iwn_read_prom_data(sc, addr, &sc->eeprom_channels[n], 2541 iwn_bands[n].nchan * sizeof (struct iwn_eeprom_chan)); 2542 2543 if (n < 5) { 2544 iwn_read_eeprom_band(sc, n, IEEE80211_CHAN_MAX, &ic->ic_nchans, 2545 ic->ic_channels); 2546 } else { 2547 iwn_read_eeprom_ht40(sc, n, IEEE80211_CHAN_MAX, &ic->ic_nchans, 2548 ic->ic_channels); 2549 } 2550 ieee80211_sort_channels(ic->ic_channels, ic->ic_nchans); 2551 } 2552 2553 static struct iwn_eeprom_chan * 2554 iwn_find_eeprom_channel(struct iwn_softc *sc, struct ieee80211_channel *c) 2555 { 2556 int band, chan, i, j; 2557 2558 if (IEEE80211_IS_CHAN_HT40(c)) { 2559 band = IEEE80211_IS_CHAN_5GHZ(c) ? 6 : 5; 2560 if (IEEE80211_IS_CHAN_HT40D(c)) 2561 chan = c->ic_extieee; 2562 else 2563 chan = c->ic_ieee; 2564 for (i = 0; i < iwn_bands[band].nchan; i++) { 2565 if (iwn_bands[band].chan[i] == chan) 2566 return &sc->eeprom_channels[band][i]; 2567 } 2568 } else { 2569 for (j = 0; j < 5; j++) { 2570 for (i = 0; i < iwn_bands[j].nchan; i++) { 2571 if (iwn_bands[j].chan[i] == c->ic_ieee && 2572 ((j == 0) ^ IEEE80211_IS_CHAN_A(c)) == 1) 2573 return &sc->eeprom_channels[j][i]; 2574 } 2575 } 2576 } 2577 return NULL; 2578 } 2579 2580 static void 2581 iwn_getradiocaps(struct ieee80211com *ic, 2582 int maxchans, int *nchans, struct ieee80211_channel chans[]) 2583 { 2584 struct iwn_softc *sc = ic->ic_softc; 2585 int i; 2586 2587 /* Parse the list of authorized channels. */ 2588 for (i = 0; i < 5 && *nchans < maxchans; i++) 2589 iwn_read_eeprom_band(sc, i, maxchans, nchans, chans); 2590 for (i = 5; i < IWN_NBANDS - 1 && *nchans < maxchans; i++) 2591 iwn_read_eeprom_ht40(sc, i, maxchans, nchans, chans); 2592 } 2593 2594 /* 2595 * Enforce flags read from EEPROM. 2596 */ 2597 static int 2598 iwn_setregdomain(struct ieee80211com *ic, struct ieee80211_regdomain *rd, 2599 int nchan, struct ieee80211_channel chans[]) 2600 { 2601 struct iwn_softc *sc = ic->ic_softc; 2602 int i; 2603 2604 for (i = 0; i < nchan; i++) { 2605 struct ieee80211_channel *c = &chans[i]; 2606 struct iwn_eeprom_chan *channel; 2607 2608 channel = iwn_find_eeprom_channel(sc, c); 2609 if (channel == NULL) { 2610 ic_printf(ic, "%s: invalid channel %u freq %u/0x%x\n", 2611 __func__, c->ic_ieee, c->ic_freq, c->ic_flags); 2612 return EINVAL; 2613 } 2614 c->ic_flags |= iwn_eeprom_channel_flags(channel); 2615 } 2616 2617 return 0; 2618 } 2619 2620 static void 2621 iwn_read_eeprom_enhinfo(struct iwn_softc *sc) 2622 { 2623 struct iwn_eeprom_enhinfo enhinfo[35]; 2624 struct ieee80211com *ic = &sc->sc_ic; 2625 struct ieee80211_channel *c; 2626 uint16_t val, base; 2627 int8_t maxpwr; 2628 uint8_t flags; 2629 int i, j; 2630 2631 DPRINTF(sc, IWN_DEBUG_TRACE, "->%s begin\n", __func__); 2632 2633 iwn_read_prom_data(sc, IWN5000_EEPROM_REG, &val, 2); 2634 base = le16toh(val); 2635 iwn_read_prom_data(sc, base + IWN6000_EEPROM_ENHINFO, 2636 enhinfo, sizeof enhinfo); 2637 2638 for (i = 0; i < nitems(enhinfo); i++) { 2639 flags = enhinfo[i].flags; 2640 if (!(flags & IWN_ENHINFO_VALID)) 2641 continue; /* Skip invalid entries. */ 2642 2643 maxpwr = 0; 2644 if (sc->txchainmask & IWN_ANT_A) 2645 maxpwr = MAX(maxpwr, enhinfo[i].chain[0]); 2646 if (sc->txchainmask & IWN_ANT_B) 2647 maxpwr = MAX(maxpwr, enhinfo[i].chain[1]); 2648 if (sc->txchainmask & IWN_ANT_C) 2649 maxpwr = MAX(maxpwr, enhinfo[i].chain[2]); 2650 if (sc->ntxchains == 2) 2651 maxpwr = MAX(maxpwr, enhinfo[i].mimo2); 2652 else if (sc->ntxchains == 3) 2653 maxpwr = MAX(maxpwr, enhinfo[i].mimo3); 2654 2655 for (j = 0; j < ic->ic_nchans; j++) { 2656 c = &ic->ic_channels[j]; 2657 if ((flags & IWN_ENHINFO_5GHZ)) { 2658 if (!IEEE80211_IS_CHAN_A(c)) 2659 continue; 2660 } else if ((flags & IWN_ENHINFO_OFDM)) { 2661 if (!IEEE80211_IS_CHAN_G(c)) 2662 continue; 2663 } else if (!IEEE80211_IS_CHAN_B(c)) 2664 continue; 2665 if ((flags & IWN_ENHINFO_HT40)) { 2666 if (!IEEE80211_IS_CHAN_HT40(c)) 2667 continue; 2668 } else { 2669 if (IEEE80211_IS_CHAN_HT40(c)) 2670 continue; 2671 } 2672 if (enhinfo[i].chan != 0 && 2673 enhinfo[i].chan != c->ic_ieee) 2674 continue; 2675 2676 DPRINTF(sc, IWN_DEBUG_RESET, 2677 "channel %d(%x), maxpwr %d\n", c->ic_ieee, 2678 c->ic_flags, maxpwr / 2); 2679 c->ic_maxregpower = maxpwr / 2; 2680 c->ic_maxpower = maxpwr; 2681 } 2682 } 2683 2684 DPRINTF(sc, IWN_DEBUG_TRACE, "->%s end\n", __func__); 2685 2686 } 2687 2688 static struct ieee80211_node * 2689 iwn_node_alloc(struct ieee80211vap *vap, const uint8_t mac[IEEE80211_ADDR_LEN]) 2690 { 2691 struct iwn_node *wn; 2692 2693 wn = malloc(sizeof (struct iwn_node), M_80211_NODE, M_NOWAIT | M_ZERO); 2694 if (wn == NULL) 2695 return (NULL); 2696 2697 wn->id = IWN_ID_UNDEFINED; 2698 2699 return (&wn->ni); 2700 } 2701 2702 static __inline int 2703 rate2plcp(int rate) 2704 { 2705 switch (rate & 0xff) { 2706 case 12: return 0xd; 2707 case 18: return 0xf; 2708 case 24: return 0x5; 2709 case 36: return 0x7; 2710 case 48: return 0x9; 2711 case 72: return 0xb; 2712 case 96: return 0x1; 2713 case 108: return 0x3; 2714 case 2: return 10; 2715 case 4: return 20; 2716 case 11: return 55; 2717 case 22: return 110; 2718 } 2719 return 0; 2720 } 2721 2722 static __inline uint8_t 2723 plcp2rate(const uint8_t rate_plcp) 2724 { 2725 switch (rate_plcp) { 2726 case 0xd: return 12; 2727 case 0xf: return 18; 2728 case 0x5: return 24; 2729 case 0x7: return 36; 2730 case 0x9: return 48; 2731 case 0xb: return 72; 2732 case 0x1: return 96; 2733 case 0x3: return 108; 2734 case 10: return 2; 2735 case 20: return 4; 2736 case 55: return 11; 2737 case 110: return 22; 2738 default: return 0; 2739 } 2740 } 2741 2742 static int 2743 iwn_get_1stream_tx_antmask(struct iwn_softc *sc) 2744 { 2745 2746 return IWN_LSB(sc->txchainmask); 2747 } 2748 2749 static int 2750 iwn_get_2stream_tx_antmask(struct iwn_softc *sc) 2751 { 2752 int tx; 2753 2754 /* 2755 * The '2 stream' setup is a bit .. odd. 2756 * 2757 * For NICs that support only 1 antenna, default to IWN_ANT_AB or 2758 * the firmware panics (eg Intel 5100.) 2759 * 2760 * For NICs that support two antennas, we use ANT_AB. 2761 * 2762 * For NICs that support three antennas, we use the two that 2763 * wasn't the default one. 2764 * 2765 * XXX TODO: if bluetooth (full concurrent) is enabled, restrict 2766 * this to only one antenna. 2767 */ 2768 2769 /* Default - transmit on the other antennas */ 2770 tx = (sc->txchainmask & ~IWN_LSB(sc->txchainmask)); 2771 2772 /* Now, if it's zero, set it to IWN_ANT_AB, so to not panic firmware */ 2773 if (tx == 0) 2774 tx = IWN_ANT_AB; 2775 2776 /* 2777 * If the NIC is a two-stream TX NIC, configure the TX mask to 2778 * the default chainmask 2779 */ 2780 else if (sc->ntxchains == 2) 2781 tx = sc->txchainmask; 2782 2783 return (tx); 2784 } 2785 2786 2787 2788 /* 2789 * Calculate the required PLCP value from the given rate, 2790 * to the given node. 2791 * 2792 * This will take the node configuration (eg 11n, rate table 2793 * setup, etc) into consideration. 2794 */ 2795 static uint32_t 2796 iwn_rate_to_plcp(struct iwn_softc *sc, struct ieee80211_node *ni, 2797 uint8_t rate) 2798 { 2799 struct ieee80211com *ic = ni->ni_ic; 2800 uint32_t plcp = 0; 2801 int ridx; 2802 2803 /* 2804 * If it's an MCS rate, let's set the plcp correctly 2805 * and set the relevant flags based on the node config. 2806 */ 2807 if (rate & IEEE80211_RATE_MCS) { 2808 /* 2809 * Set the initial PLCP value to be between 0->31 for 2810 * MCS 0 -> MCS 31, then set the "I'm an MCS rate!" 2811 * flag. 2812 */ 2813 plcp = IEEE80211_RV(rate) | IWN_RFLAG_MCS; 2814 2815 /* 2816 * XXX the following should only occur if both 2817 * the local configuration _and_ the remote node 2818 * advertise these capabilities. Thus this code 2819 * may need fixing! 2820 */ 2821 2822 /* 2823 * Set the channel width and guard interval. 2824 */ 2825 if (IEEE80211_IS_CHAN_HT40(ni->ni_chan)) { 2826 plcp |= IWN_RFLAG_HT40; 2827 if (ni->ni_htcap & IEEE80211_HTCAP_SHORTGI40) 2828 plcp |= IWN_RFLAG_SGI; 2829 } else if (ni->ni_htcap & IEEE80211_HTCAP_SHORTGI20) { 2830 plcp |= IWN_RFLAG_SGI; 2831 } 2832 2833 /* 2834 * Ensure the selected rate matches the link quality 2835 * table entries being used. 2836 */ 2837 if (rate > 0x8f) 2838 plcp |= IWN_RFLAG_ANT(sc->txchainmask); 2839 else if (rate > 0x87) 2840 plcp |= IWN_RFLAG_ANT(iwn_get_2stream_tx_antmask(sc)); 2841 else 2842 plcp |= IWN_RFLAG_ANT(iwn_get_1stream_tx_antmask(sc)); 2843 } else { 2844 /* 2845 * Set the initial PLCP - fine for both 2846 * OFDM and CCK rates. 2847 */ 2848 plcp = rate2plcp(rate); 2849 2850 /* Set CCK flag if it's CCK */ 2851 2852 /* XXX It would be nice to have a method 2853 * to map the ridx -> phy table entry 2854 * so we could just query that, rather than 2855 * this hack to check against IWN_RIDX_OFDM6. 2856 */ 2857 ridx = ieee80211_legacy_rate_lookup(ic->ic_rt, 2858 rate & IEEE80211_RATE_VAL); 2859 if (ridx < IWN_RIDX_OFDM6 && 2860 IEEE80211_IS_CHAN_2GHZ(ni->ni_chan)) 2861 plcp |= IWN_RFLAG_CCK; 2862 2863 /* Set antenna configuration */ 2864 /* XXX TODO: is this the right antenna to use for legacy? */ 2865 plcp |= IWN_RFLAG_ANT(iwn_get_1stream_tx_antmask(sc)); 2866 } 2867 2868 DPRINTF(sc, IWN_DEBUG_TXRATE, "%s: rate=0x%02x, plcp=0x%08x\n", 2869 __func__, 2870 rate, 2871 plcp); 2872 2873 return (htole32(plcp)); 2874 } 2875 2876 static void 2877 iwn_newassoc(struct ieee80211_node *ni, int isnew) 2878 { 2879 /* Doesn't do anything at the moment */ 2880 } 2881 2882 static int 2883 iwn_newstate(struct ieee80211vap *vap, enum ieee80211_state nstate, int arg) 2884 { 2885 struct iwn_vap *ivp = IWN_VAP(vap); 2886 struct ieee80211com *ic = vap->iv_ic; 2887 struct iwn_softc *sc = ic->ic_softc; 2888 int error = 0; 2889 2890 DPRINTF(sc, IWN_DEBUG_TRACE, "->%s begin\n", __func__); 2891 2892 DPRINTF(sc, IWN_DEBUG_STATE, "%s: %s -> %s\n", __func__, 2893 ieee80211_state_name[vap->iv_state], ieee80211_state_name[nstate]); 2894 2895 IEEE80211_UNLOCK(ic); 2896 IWN_LOCK(sc); 2897 callout_stop(&sc->calib_to); 2898 2899 sc->rxon = &sc->rx_on[IWN_RXON_BSS_CTX]; 2900 2901 switch (nstate) { 2902 case IEEE80211_S_ASSOC: 2903 if (vap->iv_state != IEEE80211_S_RUN) 2904 break; 2905 /* FALLTHROUGH */ 2906 case IEEE80211_S_AUTH: 2907 if (vap->iv_state == IEEE80211_S_AUTH) 2908 break; 2909 2910 /* 2911 * !AUTH -> AUTH transition requires state reset to handle 2912 * reassociations correctly. 2913 */ 2914 sc->rxon->associd = 0; 2915 sc->rxon->filter &= ~htole32(IWN_FILTER_BSS); 2916 sc->calib.state = IWN_CALIB_STATE_INIT; 2917 2918 /* Wait until we hear a beacon before we transmit */ 2919 if (IEEE80211_IS_CHAN_PASSIVE(ic->ic_curchan)) 2920 sc->sc_beacon_wait = 1; 2921 2922 if ((error = iwn_auth(sc, vap)) != 0) { 2923 device_printf(sc->sc_dev, 2924 "%s: could not move to auth state\n", __func__); 2925 } 2926 break; 2927 2928 case IEEE80211_S_RUN: 2929 /* 2930 * RUN -> RUN transition; Just restart the timers. 2931 */ 2932 if (vap->iv_state == IEEE80211_S_RUN) { 2933 sc->calib_cnt = 0; 2934 break; 2935 } 2936 2937 /* Wait until we hear a beacon before we transmit */ 2938 if (IEEE80211_IS_CHAN_PASSIVE(ic->ic_curchan)) 2939 sc->sc_beacon_wait = 1; 2940 2941 /* 2942 * !RUN -> RUN requires setting the association id 2943 * which is done with a firmware cmd. We also defer 2944 * starting the timers until that work is done. 2945 */ 2946 if ((error = iwn_run(sc, vap)) != 0) { 2947 device_printf(sc->sc_dev, 2948 "%s: could not move to run state\n", __func__); 2949 } 2950 break; 2951 2952 case IEEE80211_S_INIT: 2953 sc->calib.state = IWN_CALIB_STATE_INIT; 2954 /* 2955 * Purge the xmit queue so we don't have old frames 2956 * during a new association attempt. 2957 */ 2958 sc->sc_beacon_wait = 0; 2959 iwn_xmit_queue_drain(sc); 2960 break; 2961 2962 default: 2963 break; 2964 } 2965 IWN_UNLOCK(sc); 2966 IEEE80211_LOCK(ic); 2967 if (error != 0){ 2968 DPRINTF(sc, IWN_DEBUG_TRACE, "->%s end in error\n", __func__); 2969 return error; 2970 } 2971 2972 DPRINTF(sc, IWN_DEBUG_TRACE, "->%s: end\n",__func__); 2973 2974 return ivp->iv_newstate(vap, nstate, arg); 2975 } 2976 2977 static void 2978 iwn_calib_timeout(void *arg) 2979 { 2980 struct iwn_softc *sc = arg; 2981 2982 IWN_LOCK_ASSERT(sc); 2983 2984 /* Force automatic TX power calibration every 60 secs. */ 2985 if (++sc->calib_cnt >= 120) { 2986 uint32_t flags = 0; 2987 2988 DPRINTF(sc, IWN_DEBUG_CALIBRATE, "%s\n", 2989 "sending request for statistics"); 2990 (void)iwn_cmd(sc, IWN_CMD_GET_STATISTICS, &flags, 2991 sizeof flags, 1); 2992 sc->calib_cnt = 0; 2993 } 2994 callout_reset(&sc->calib_to, msecs_to_ticks(500), iwn_calib_timeout, 2995 sc); 2996 } 2997 2998 /* 2999 * Process an RX_PHY firmware notification. This is usually immediately 3000 * followed by an MPDU_RX_DONE notification. 3001 */ 3002 static void 3003 iwn_rx_phy(struct iwn_softc *sc, struct iwn_rx_desc *desc) 3004 { 3005 struct iwn_rx_stat *stat = (struct iwn_rx_stat *)(desc + 1); 3006 3007 DPRINTF(sc, IWN_DEBUG_CALIBRATE, "%s: received PHY stats\n", __func__); 3008 3009 /* Save RX statistics, they will be used on MPDU_RX_DONE. */ 3010 memcpy(&sc->last_rx_stat, stat, sizeof (*stat)); 3011 sc->last_rx_valid = 1; 3012 } 3013 3014 /* 3015 * Process an RX_DONE (4965AGN only) or MPDU_RX_DONE firmware notification. 3016 * Each MPDU_RX_DONE notification must be preceded by an RX_PHY one. 3017 */ 3018 static void 3019 iwn_rx_done(struct iwn_softc *sc, struct iwn_rx_desc *desc, 3020 struct iwn_rx_data *data) 3021 { 3022 struct epoch_tracker et; 3023 struct iwn_ops *ops = &sc->ops; 3024 struct ieee80211com *ic = &sc->sc_ic; 3025 struct iwn_rx_ring *ring = &sc->rxq; 3026 struct ieee80211_frame_min *wh; 3027 struct ieee80211_node *ni; 3028 struct mbuf *m, *m1; 3029 struct iwn_rx_stat *stat; 3030 caddr_t head; 3031 bus_addr_t paddr; 3032 uint32_t flags; 3033 int error, len, rssi, nf; 3034 3035 DPRINTF(sc, IWN_DEBUG_TRACE, "->%s begin\n", __func__); 3036 3037 if (desc->type == IWN_MPDU_RX_DONE) { 3038 /* Check for prior RX_PHY notification. */ 3039 if (!sc->last_rx_valid) { 3040 DPRINTF(sc, IWN_DEBUG_ANY, 3041 "%s: missing RX_PHY\n", __func__); 3042 return; 3043 } 3044 stat = &sc->last_rx_stat; 3045 } else 3046 stat = (struct iwn_rx_stat *)(desc + 1); 3047 3048 if (stat->cfg_phy_len > IWN_STAT_MAXLEN) { 3049 device_printf(sc->sc_dev, 3050 "%s: invalid RX statistic header, len %d\n", __func__, 3051 stat->cfg_phy_len); 3052 return; 3053 } 3054 if (desc->type == IWN_MPDU_RX_DONE) { 3055 struct iwn_rx_mpdu *mpdu = (struct iwn_rx_mpdu *)(desc + 1); 3056 head = (caddr_t)(mpdu + 1); 3057 len = le16toh(mpdu->len); 3058 } else { 3059 head = (caddr_t)(stat + 1) + stat->cfg_phy_len; 3060 len = le16toh(stat->len); 3061 } 3062 3063 flags = le32toh(*(uint32_t *)(head + len)); 3064 3065 /* Discard frames with a bad FCS early. */ 3066 if ((flags & IWN_RX_NOERROR) != IWN_RX_NOERROR) { 3067 DPRINTF(sc, IWN_DEBUG_RECV, "%s: RX flags error %x\n", 3068 __func__, flags); 3069 counter_u64_add(ic->ic_ierrors, 1); 3070 return; 3071 } 3072 /* Discard frames that are too short. */ 3073 if (len < sizeof (struct ieee80211_frame_ack)) { 3074 DPRINTF(sc, IWN_DEBUG_RECV, "%s: frame too short: %d\n", 3075 __func__, len); 3076 counter_u64_add(ic->ic_ierrors, 1); 3077 return; 3078 } 3079 3080 m1 = m_getjcl(M_NOWAIT, MT_DATA, M_PKTHDR, IWN_RBUF_SIZE); 3081 if (m1 == NULL) { 3082 DPRINTF(sc, IWN_DEBUG_ANY, "%s: no mbuf to restock ring\n", 3083 __func__); 3084 counter_u64_add(ic->ic_ierrors, 1); 3085 return; 3086 } 3087 bus_dmamap_unload(ring->data_dmat, data->map); 3088 3089 error = bus_dmamap_load(ring->data_dmat, data->map, mtod(m1, void *), 3090 IWN_RBUF_SIZE, iwn_dma_map_addr, &paddr, BUS_DMA_NOWAIT); 3091 if (error != 0 && error != EFBIG) { 3092 device_printf(sc->sc_dev, 3093 "%s: bus_dmamap_load failed, error %d\n", __func__, error); 3094 m_freem(m1); 3095 3096 /* Try to reload the old mbuf. */ 3097 error = bus_dmamap_load(ring->data_dmat, data->map, 3098 mtod(data->m, void *), IWN_RBUF_SIZE, iwn_dma_map_addr, 3099 &paddr, BUS_DMA_NOWAIT); 3100 if (error != 0 && error != EFBIG) { 3101 panic("%s: could not load old RX mbuf", __func__); 3102 } 3103 bus_dmamap_sync(ring->data_dmat, data->map, 3104 BUS_DMASYNC_PREREAD); 3105 /* Physical address may have changed. */ 3106 ring->desc[ring->cur] = htole32(paddr >> 8); 3107 bus_dmamap_sync(ring->desc_dma.tag, ring->desc_dma.map, 3108 BUS_DMASYNC_PREWRITE); 3109 counter_u64_add(ic->ic_ierrors, 1); 3110 return; 3111 } 3112 3113 bus_dmamap_sync(ring->data_dmat, data->map, 3114 BUS_DMASYNC_PREREAD); 3115 3116 m = data->m; 3117 data->m = m1; 3118 /* Update RX descriptor. */ 3119 ring->desc[ring->cur] = htole32(paddr >> 8); 3120 bus_dmamap_sync(ring->desc_dma.tag, ring->desc_dma.map, 3121 BUS_DMASYNC_PREWRITE); 3122 3123 /* Finalize mbuf. */ 3124 m->m_data = head; 3125 m->m_pkthdr.len = m->m_len = len; 3126 3127 /* Grab a reference to the source node. */ 3128 wh = mtod(m, struct ieee80211_frame_min *); 3129 if (len >= sizeof(struct ieee80211_frame_min)) 3130 ni = ieee80211_find_rxnode(ic, wh); 3131 else 3132 ni = NULL; 3133 nf = (ni != NULL && ni->ni_vap->iv_state == IEEE80211_S_RUN && 3134 (ic->ic_flags & IEEE80211_F_SCAN) == 0) ? sc->noise : -95; 3135 3136 rssi = ops->get_rssi(sc, stat); 3137 3138 if (ieee80211_radiotap_active(ic)) { 3139 struct iwn_rx_radiotap_header *tap = &sc->sc_rxtap; 3140 uint32_t rate = le32toh(stat->rate); 3141 3142 tap->wr_flags = 0; 3143 if (stat->flags & htole16(IWN_STAT_FLAG_SHPREAMBLE)) 3144 tap->wr_flags |= IEEE80211_RADIOTAP_F_SHORTPRE; 3145 tap->wr_dbm_antsignal = (int8_t)rssi; 3146 tap->wr_dbm_antnoise = (int8_t)nf; 3147 tap->wr_tsft = stat->tstamp; 3148 if (rate & IWN_RFLAG_MCS) { 3149 tap->wr_rate = rate & IWN_RFLAG_RATE_MCS; 3150 tap->wr_rate |= IEEE80211_RATE_MCS; 3151 } else 3152 tap->wr_rate = plcp2rate(rate & IWN_RFLAG_RATE); 3153 } 3154 3155 /* 3156 * If it's a beacon and we're waiting, then do the 3157 * wakeup. This should unblock raw_xmit/start. 3158 */ 3159 if (sc->sc_beacon_wait) { 3160 uint8_t type, subtype; 3161 /* NB: Re-assign wh */ 3162 wh = mtod(m, struct ieee80211_frame_min *); 3163 type = wh->i_fc[0] & IEEE80211_FC0_TYPE_MASK; 3164 subtype = wh->i_fc[0] & IEEE80211_FC0_SUBTYPE_MASK; 3165 /* 3166 * This assumes at this point we've received our own 3167 * beacon. 3168 */ 3169 DPRINTF(sc, IWN_DEBUG_TRACE, 3170 "%s: beacon_wait, type=%d, subtype=%d\n", 3171 __func__, type, subtype); 3172 if (type == IEEE80211_FC0_TYPE_MGT && 3173 subtype == IEEE80211_FC0_SUBTYPE_BEACON) { 3174 DPRINTF(sc, IWN_DEBUG_TRACE | IWN_DEBUG_XMIT, 3175 "%s: waking things up\n", __func__); 3176 /* queue taskqueue to transmit! */ 3177 taskqueue_enqueue(sc->sc_tq, &sc->sc_xmit_task); 3178 } 3179 } 3180 3181 IWN_UNLOCK(sc); 3182 NET_EPOCH_ENTER(et); 3183 3184 /* Send the frame to the 802.11 layer. */ 3185 if (ni != NULL) { 3186 if (ni->ni_flags & IEEE80211_NODE_HT) 3187 m->m_flags |= M_AMPDU; 3188 (void)ieee80211_input(ni, m, rssi - nf, nf); 3189 /* Node is no longer needed. */ 3190 ieee80211_free_node(ni); 3191 } else 3192 (void)ieee80211_input_all(ic, m, rssi - nf, nf); 3193 3194 NET_EPOCH_EXIT(et); 3195 IWN_LOCK(sc); 3196 3197 DPRINTF(sc, IWN_DEBUG_TRACE, "->%s: end\n",__func__); 3198 3199 } 3200 3201 static void 3202 iwn_agg_tx_complete(struct iwn_softc *sc, struct iwn_tx_ring *ring, int tid, 3203 int idx, int success) 3204 { 3205 struct ieee80211_ratectl_tx_status *txs = &sc->sc_txs; 3206 struct iwn_tx_data *data = &ring->data[idx]; 3207 struct iwn_node *wn; 3208 struct mbuf *m; 3209 struct ieee80211_node *ni; 3210 3211 KASSERT(data->ni != NULL, ("idx %d: no node", idx)); 3212 KASSERT(data->m != NULL, ("idx %d: no mbuf", idx)); 3213 3214 /* Unmap and free mbuf. */ 3215 bus_dmamap_sync(ring->data_dmat, data->map, 3216 BUS_DMASYNC_POSTWRITE); 3217 bus_dmamap_unload(ring->data_dmat, data->map); 3218 m = data->m, data->m = NULL; 3219 ni = data->ni, data->ni = NULL; 3220 wn = (void *)ni; 3221 3222 #if 0 3223 /* XXX causes significant performance degradation. */ 3224 txs->flags = IEEE80211_RATECTL_STATUS_SHORT_RETRY | 3225 IEEE80211_RATECTL_STATUS_LONG_RETRY; 3226 txs->long_retries = data->long_retries - 1; 3227 #else 3228 txs->flags = IEEE80211_RATECTL_STATUS_SHORT_RETRY; 3229 #endif 3230 txs->short_retries = wn->agg[tid].short_retries; 3231 if (success) 3232 txs->status = IEEE80211_RATECTL_TX_SUCCESS; 3233 else 3234 txs->status = IEEE80211_RATECTL_TX_FAIL_UNSPECIFIED; 3235 3236 wn->agg[tid].short_retries = 0; 3237 data->long_retries = 0; 3238 3239 DPRINTF(sc, IWN_DEBUG_AMPDU, "%s: freeing m %p ni %p idx %d qid %d\n", 3240 __func__, m, ni, idx, ring->qid); 3241 ieee80211_ratectl_tx_complete(ni, txs); 3242 ieee80211_tx_complete(ni, m, !success); 3243 } 3244 3245 /* Process an incoming Compressed BlockAck. */ 3246 static void 3247 iwn_rx_compressed_ba(struct iwn_softc *sc, struct iwn_rx_desc *desc) 3248 { 3249 struct iwn_tx_ring *ring; 3250 struct iwn_tx_data *data; 3251 struct iwn_node *wn; 3252 struct iwn_compressed_ba *ba = (struct iwn_compressed_ba *)(desc + 1); 3253 struct ieee80211_tx_ampdu *tap; 3254 uint64_t bitmap; 3255 uint8_t tid; 3256 int i, qid, shift; 3257 int tx_ok = 0; 3258 3259 DPRINTF(sc, IWN_DEBUG_TRACE, "->%s begin\n", __func__); 3260 3261 qid = le16toh(ba->qid); 3262 tap = sc->qid2tap[qid]; 3263 ring = &sc->txq[qid]; 3264 tid = tap->txa_tid; 3265 wn = (void *)tap->txa_ni; 3266 3267 DPRINTF(sc, IWN_DEBUG_AMPDU, "%s: qid %d tid %d seq %04X ssn %04X\n" 3268 "bitmap: ba %016jX wn %016jX, start %d\n", 3269 __func__, qid, tid, le16toh(ba->seq), le16toh(ba->ssn), 3270 (uintmax_t)le64toh(ba->bitmap), (uintmax_t)wn->agg[tid].bitmap, 3271 wn->agg[tid].startidx); 3272 3273 if (wn->agg[tid].bitmap == 0) 3274 return; 3275 3276 shift = wn->agg[tid].startidx - ((le16toh(ba->seq) >> 4) & 0xff); 3277 if (shift <= -64) 3278 shift += 0x100; 3279 3280 /* 3281 * Walk the bitmap and calculate how many successful attempts 3282 * are made. 3283 * 3284 * Yes, the rate control code doesn't know these are A-MPDU 3285 * subframes; due to that long_retries stats are not used here. 3286 */ 3287 bitmap = le64toh(ba->bitmap); 3288 if (shift >= 0) 3289 bitmap >>= shift; 3290 else 3291 bitmap <<= -shift; 3292 bitmap &= wn->agg[tid].bitmap; 3293 wn->agg[tid].bitmap = 0; 3294 3295 for (i = wn->agg[tid].startidx; 3296 bitmap; 3297 bitmap >>= 1, i = (i + 1) % IWN_TX_RING_COUNT) { 3298 if ((bitmap & 1) == 0) 3299 continue; 3300 3301 data = &ring->data[i]; 3302 if (__predict_false(data->m == NULL)) { 3303 /* 3304 * There is no frame; skip this entry. 3305 * 3306 * NB: it is "ok" to have both 3307 * 'tx done' + 'compressed BA' replies for frame 3308 * with STATE_SCD_QUERY status. 3309 */ 3310 DPRINTF(sc, IWN_DEBUG_AMPDU, 3311 "%s: ring %d: no entry %d\n", __func__, qid, i); 3312 continue; 3313 } 3314 3315 tx_ok++; 3316 iwn_agg_tx_complete(sc, ring, tid, i, 1); 3317 } 3318 3319 ring->queued -= tx_ok; 3320 iwn_check_tx_ring(sc, qid); 3321 3322 DPRINTF(sc, IWN_DEBUG_TRACE | IWN_DEBUG_AMPDU, 3323 "->%s: end; %d ok\n",__func__, tx_ok); 3324 } 3325 3326 /* 3327 * Process a CALIBRATION_RESULT notification sent by the initialization 3328 * firmware on response to a CMD_CALIB_CONFIG command (5000 only). 3329 */ 3330 static void 3331 iwn5000_rx_calib_results(struct iwn_softc *sc, struct iwn_rx_desc *desc) 3332 { 3333 struct iwn_phy_calib *calib = (struct iwn_phy_calib *)(desc + 1); 3334 int len, idx = -1; 3335 3336 DPRINTF(sc, IWN_DEBUG_TRACE, "->%s begin\n", __func__); 3337 3338 /* Runtime firmware should not send such a notification. */ 3339 if (sc->sc_flags & IWN_FLAG_CALIB_DONE){ 3340 DPRINTF(sc, IWN_DEBUG_TRACE, 3341 "->%s received after calib done\n", __func__); 3342 return; 3343 } 3344 len = (le32toh(desc->len) & 0x3fff) - 4; 3345 3346 switch (calib->code) { 3347 case IWN5000_PHY_CALIB_DC: 3348 if (sc->base_params->calib_need & IWN_FLG_NEED_PHY_CALIB_DC) 3349 idx = 0; 3350 break; 3351 case IWN5000_PHY_CALIB_LO: 3352 if (sc->base_params->calib_need & IWN_FLG_NEED_PHY_CALIB_LO) 3353 idx = 1; 3354 break; 3355 case IWN5000_PHY_CALIB_TX_IQ: 3356 if (sc->base_params->calib_need & IWN_FLG_NEED_PHY_CALIB_TX_IQ) 3357 idx = 2; 3358 break; 3359 case IWN5000_PHY_CALIB_TX_IQ_PERIODIC: 3360 if (sc->base_params->calib_need & IWN_FLG_NEED_PHY_CALIB_TX_IQ_PERIODIC) 3361 idx = 3; 3362 break; 3363 case IWN5000_PHY_CALIB_BASE_BAND: 3364 if (sc->base_params->calib_need & IWN_FLG_NEED_PHY_CALIB_BASE_BAND) 3365 idx = 4; 3366 break; 3367 } 3368 if (idx == -1) /* Ignore other results. */ 3369 return; 3370 3371 /* Save calibration result. */ 3372 if (sc->calibcmd[idx].buf != NULL) 3373 free(sc->calibcmd[idx].buf, M_DEVBUF); 3374 sc->calibcmd[idx].buf = malloc(len, M_DEVBUF, M_NOWAIT); 3375 if (sc->calibcmd[idx].buf == NULL) { 3376 DPRINTF(sc, IWN_DEBUG_CALIBRATE, 3377 "not enough memory for calibration result %d\n", 3378 calib->code); 3379 return; 3380 } 3381 DPRINTF(sc, IWN_DEBUG_CALIBRATE, 3382 "saving calibration result idx=%d, code=%d len=%d\n", idx, calib->code, len); 3383 sc->calibcmd[idx].len = len; 3384 memcpy(sc->calibcmd[idx].buf, calib, len); 3385 } 3386 3387 static void 3388 iwn_stats_update(struct iwn_softc *sc, struct iwn_calib_state *calib, 3389 struct iwn_stats *stats, int len) 3390 { 3391 struct iwn_stats_bt *stats_bt; 3392 struct iwn_stats *lstats; 3393 3394 /* 3395 * First - check whether the length is the bluetooth or normal. 3396 * 3397 * If it's normal - just copy it and bump out. 3398 * Otherwise we have to convert things. 3399 */ 3400 3401 if (len == sizeof(struct iwn_stats) + 4) { 3402 memcpy(&sc->last_stat, stats, sizeof(struct iwn_stats)); 3403 sc->last_stat_valid = 1; 3404 return; 3405 } 3406 3407 /* 3408 * If it's not the bluetooth size - log, then just copy. 3409 */ 3410 if (len != sizeof(struct iwn_stats_bt) + 4) { 3411 DPRINTF(sc, IWN_DEBUG_STATS, 3412 "%s: size of rx statistics (%d) not an expected size!\n", 3413 __func__, 3414 len); 3415 memcpy(&sc->last_stat, stats, sizeof(struct iwn_stats)); 3416 sc->last_stat_valid = 1; 3417 return; 3418 } 3419 3420 /* 3421 * Ok. Time to copy. 3422 */ 3423 stats_bt = (struct iwn_stats_bt *) stats; 3424 lstats = &sc->last_stat; 3425 3426 /* flags */ 3427 lstats->flags = stats_bt->flags; 3428 /* rx_bt */ 3429 memcpy(&lstats->rx.ofdm, &stats_bt->rx_bt.ofdm, 3430 sizeof(struct iwn_rx_phy_stats)); 3431 memcpy(&lstats->rx.cck, &stats_bt->rx_bt.cck, 3432 sizeof(struct iwn_rx_phy_stats)); 3433 memcpy(&lstats->rx.general, &stats_bt->rx_bt.general_bt.common, 3434 sizeof(struct iwn_rx_general_stats)); 3435 memcpy(&lstats->rx.ht, &stats_bt->rx_bt.ht, 3436 sizeof(struct iwn_rx_ht_phy_stats)); 3437 /* tx */ 3438 memcpy(&lstats->tx, &stats_bt->tx, 3439 sizeof(struct iwn_tx_stats)); 3440 /* general */ 3441 memcpy(&lstats->general, &stats_bt->general, 3442 sizeof(struct iwn_general_stats)); 3443 3444 /* XXX TODO: Squirrel away the extra bluetooth stats somewhere */ 3445 sc->last_stat_valid = 1; 3446 } 3447 3448 /* 3449 * Process an RX_STATISTICS or BEACON_STATISTICS firmware notification. 3450 * The latter is sent by the firmware after each received beacon. 3451 */ 3452 static void 3453 iwn_rx_statistics(struct iwn_softc *sc, struct iwn_rx_desc *desc) 3454 { 3455 struct iwn_ops *ops = &sc->ops; 3456 struct ieee80211com *ic = &sc->sc_ic; 3457 struct ieee80211vap *vap = TAILQ_FIRST(&ic->ic_vaps); 3458 struct iwn_calib_state *calib = &sc->calib; 3459 struct iwn_stats *stats = (struct iwn_stats *)(desc + 1); 3460 struct iwn_stats *lstats; 3461 int temp; 3462 3463 DPRINTF(sc, IWN_DEBUG_TRACE, "->%s begin\n", __func__); 3464 3465 /* Ignore statistics received during a scan. */ 3466 if (vap->iv_state != IEEE80211_S_RUN || 3467 (ic->ic_flags & IEEE80211_F_SCAN)){ 3468 DPRINTF(sc, IWN_DEBUG_TRACE, "->%s received during calib\n", 3469 __func__); 3470 return; 3471 } 3472 3473 DPRINTF(sc, IWN_DEBUG_CALIBRATE | IWN_DEBUG_STATS, 3474 "%s: received statistics, cmd %d, len %d\n", 3475 __func__, desc->type, le16toh(desc->len)); 3476 sc->calib_cnt = 0; /* Reset TX power calibration timeout. */ 3477 3478 /* 3479 * Collect/track general statistics for reporting. 3480 * 3481 * This takes care of ensuring that the bluetooth sized message 3482 * will be correctly converted to the legacy sized message. 3483 */ 3484 iwn_stats_update(sc, calib, stats, le16toh(desc->len)); 3485 3486 /* 3487 * And now, let's take a reference of it to use! 3488 */ 3489 lstats = &sc->last_stat; 3490 3491 /* Test if temperature has changed. */ 3492 if (lstats->general.temp != sc->rawtemp) { 3493 /* Convert "raw" temperature to degC. */ 3494 sc->rawtemp = stats->general.temp; 3495 temp = ops->get_temperature(sc); 3496 DPRINTF(sc, IWN_DEBUG_CALIBRATE, "%s: temperature %d\n", 3497 __func__, temp); 3498 3499 /* Update TX power if need be (4965AGN only). */ 3500 if (sc->hw_type == IWN_HW_REV_TYPE_4965) 3501 iwn4965_power_calibration(sc, temp); 3502 } 3503 3504 if (desc->type != IWN_BEACON_STATISTICS) 3505 return; /* Reply to a statistics request. */ 3506 3507 sc->noise = iwn_get_noise(&lstats->rx.general); 3508 DPRINTF(sc, IWN_DEBUG_CALIBRATE, "%s: noise %d\n", __func__, sc->noise); 3509 3510 /* Test that RSSI and noise are present in stats report. */ 3511 if (le32toh(lstats->rx.general.flags) != 1) { 3512 DPRINTF(sc, IWN_DEBUG_ANY, "%s\n", 3513 "received statistics without RSSI"); 3514 return; 3515 } 3516 3517 if (calib->state == IWN_CALIB_STATE_ASSOC) 3518 iwn_collect_noise(sc, &lstats->rx.general); 3519 else if (calib->state == IWN_CALIB_STATE_RUN) { 3520 iwn_tune_sensitivity(sc, &lstats->rx); 3521 /* 3522 * XXX TODO: Only run the RX recovery if we're associated! 3523 */ 3524 iwn_check_rx_recovery(sc, lstats); 3525 iwn_save_stats_counters(sc, lstats); 3526 } 3527 3528 DPRINTF(sc, IWN_DEBUG_TRACE, "->%s: end\n",__func__); 3529 } 3530 3531 /* 3532 * Save the relevant statistic counters for the next calibration 3533 * pass. 3534 */ 3535 static void 3536 iwn_save_stats_counters(struct iwn_softc *sc, const struct iwn_stats *rs) 3537 { 3538 struct iwn_calib_state *calib = &sc->calib; 3539 3540 /* Save counters values for next call. */ 3541 calib->bad_plcp_cck = le32toh(rs->rx.cck.bad_plcp); 3542 calib->fa_cck = le32toh(rs->rx.cck.fa); 3543 calib->bad_plcp_ht = le32toh(rs->rx.ht.bad_plcp); 3544 calib->bad_plcp_ofdm = le32toh(rs->rx.ofdm.bad_plcp); 3545 calib->fa_ofdm = le32toh(rs->rx.ofdm.fa); 3546 3547 /* Last time we received these tick values */ 3548 sc->last_calib_ticks = ticks; 3549 } 3550 3551 /* 3552 * Process a TX_DONE firmware notification. Unfortunately, the 4965AGN 3553 * and 5000 adapters have different incompatible TX status formats. 3554 */ 3555 static void 3556 iwn4965_tx_done(struct iwn_softc *sc, struct iwn_rx_desc *desc, 3557 struct iwn_rx_data *data) 3558 { 3559 struct iwn4965_tx_stat *stat = (struct iwn4965_tx_stat *)(desc + 1); 3560 int qid = desc->qid & IWN_RX_DESC_QID_MSK; 3561 3562 DPRINTF(sc, IWN_DEBUG_XMIT, "%s: " 3563 "qid %d idx %d RTS retries %d ACK retries %d nkill %d rate %x duration %d status %x\n", 3564 __func__, desc->qid, desc->idx, 3565 stat->rtsfailcnt, 3566 stat->ackfailcnt, 3567 stat->btkillcnt, 3568 stat->rate, le16toh(stat->duration), 3569 le32toh(stat->status)); 3570 3571 if (qid >= sc->firstaggqueue && stat->nframes != 1) { 3572 iwn_ampdu_tx_done(sc, qid, stat->nframes, stat->rtsfailcnt, 3573 &stat->status); 3574 } else { 3575 iwn_tx_done(sc, desc, stat->rtsfailcnt, stat->ackfailcnt, 3576 le32toh(stat->status) & 0xff); 3577 } 3578 } 3579 3580 static void 3581 iwn5000_tx_done(struct iwn_softc *sc, struct iwn_rx_desc *desc, 3582 struct iwn_rx_data *data) 3583 { 3584 struct iwn5000_tx_stat *stat = (struct iwn5000_tx_stat *)(desc + 1); 3585 int qid = desc->qid & IWN_RX_DESC_QID_MSK; 3586 3587 DPRINTF(sc, IWN_DEBUG_XMIT, "%s: " 3588 "qid %d idx %d RTS retries %d ACK retries %d nkill %d rate %x duration %d status %x\n", 3589 __func__, desc->qid, desc->idx, 3590 stat->rtsfailcnt, 3591 stat->ackfailcnt, 3592 stat->btkillcnt, 3593 stat->rate, le16toh(stat->duration), 3594 le32toh(stat->status)); 3595 3596 #ifdef notyet 3597 /* Reset TX scheduler slot. */ 3598 iwn5000_reset_sched(sc, qid, desc->idx); 3599 #endif 3600 3601 if (qid >= sc->firstaggqueue && stat->nframes != 1) { 3602 iwn_ampdu_tx_done(sc, qid, stat->nframes, stat->rtsfailcnt, 3603 &stat->status); 3604 } else { 3605 iwn_tx_done(sc, desc, stat->rtsfailcnt, stat->ackfailcnt, 3606 le16toh(stat->status) & 0xff); 3607 } 3608 } 3609 3610 static void 3611 iwn_adj_ampdu_ptr(struct iwn_softc *sc, struct iwn_tx_ring *ring) 3612 { 3613 int i; 3614 3615 for (i = ring->read; i != ring->cur; i = (i + 1) % IWN_TX_RING_COUNT) { 3616 struct iwn_tx_data *data = &ring->data[i]; 3617 3618 if (data->m != NULL) 3619 break; 3620 3621 data->remapped = 0; 3622 } 3623 3624 ring->read = i; 3625 } 3626 3627 /* 3628 * Adapter-independent backend for TX_DONE firmware notifications. 3629 */ 3630 static void 3631 iwn_tx_done(struct iwn_softc *sc, struct iwn_rx_desc *desc, int rtsfailcnt, 3632 int ackfailcnt, uint8_t status) 3633 { 3634 struct ieee80211_ratectl_tx_status *txs = &sc->sc_txs; 3635 struct iwn_tx_ring *ring = &sc->txq[desc->qid & IWN_RX_DESC_QID_MSK]; 3636 struct iwn_tx_data *data = &ring->data[desc->idx]; 3637 struct mbuf *m; 3638 struct ieee80211_node *ni; 3639 3640 if (__predict_false(data->m == NULL && 3641 ring->qid >= sc->firstaggqueue)) { 3642 /* 3643 * There is no frame; skip this entry. 3644 */ 3645 DPRINTF(sc, IWN_DEBUG_AMPDU, "%s: ring %d: no entry %d\n", 3646 __func__, ring->qid, desc->idx); 3647 return; 3648 } 3649 3650 KASSERT(data->ni != NULL, ("no node")); 3651 KASSERT(data->m != NULL, ("no mbuf")); 3652 3653 DPRINTF(sc, IWN_DEBUG_TRACE, "->%s begin\n", __func__); 3654 3655 /* Unmap and free mbuf. */ 3656 bus_dmamap_sync(ring->data_dmat, data->map, BUS_DMASYNC_POSTWRITE); 3657 bus_dmamap_unload(ring->data_dmat, data->map); 3658 m = data->m, data->m = NULL; 3659 ni = data->ni, data->ni = NULL; 3660 3661 data->long_retries = 0; 3662 3663 if (ring->qid >= sc->firstaggqueue) 3664 iwn_adj_ampdu_ptr(sc, ring); 3665 3666 /* 3667 * XXX f/w may hang (device timeout) when desc->idx - ring->read == 64 3668 * (aggregation queues only). 3669 */ 3670 3671 ring->queued--; 3672 iwn_check_tx_ring(sc, ring->qid); 3673 3674 /* 3675 * Update rate control statistics for the node. 3676 */ 3677 txs->flags = IEEE80211_RATECTL_STATUS_SHORT_RETRY | 3678 IEEE80211_RATECTL_STATUS_LONG_RETRY; 3679 txs->short_retries = rtsfailcnt; 3680 txs->long_retries = ackfailcnt; 3681 if (!(status & IWN_TX_FAIL)) 3682 txs->status = IEEE80211_RATECTL_TX_SUCCESS; 3683 else { 3684 switch (status) { 3685 case IWN_TX_FAIL_SHORT_LIMIT: 3686 txs->status = IEEE80211_RATECTL_TX_FAIL_SHORT; 3687 break; 3688 case IWN_TX_FAIL_LONG_LIMIT: 3689 txs->status = IEEE80211_RATECTL_TX_FAIL_LONG; 3690 break; 3691 case IWN_TX_STATUS_FAIL_LIFE_EXPIRE: 3692 txs->status = IEEE80211_RATECTL_TX_FAIL_EXPIRED; 3693 break; 3694 default: 3695 txs->status = IEEE80211_RATECTL_TX_FAIL_UNSPECIFIED; 3696 break; 3697 } 3698 } 3699 ieee80211_ratectl_tx_complete(ni, txs); 3700 3701 /* 3702 * Channels marked for "radar" require traffic to be received 3703 * to unlock before we can transmit. Until traffic is seen 3704 * any attempt to transmit is returned immediately with status 3705 * set to IWN_TX_FAIL_TX_LOCKED. Unfortunately this can easily 3706 * happen on first authenticate after scanning. To workaround 3707 * this we ignore a failure of this sort in AUTH state so the 3708 * 802.11 layer will fall back to using a timeout to wait for 3709 * the AUTH reply. This allows the firmware time to see 3710 * traffic so a subsequent retry of AUTH succeeds. It's 3711 * unclear why the firmware does not maintain state for 3712 * channels recently visited as this would allow immediate 3713 * use of the channel after a scan (where we see traffic). 3714 */ 3715 if (status == IWN_TX_FAIL_TX_LOCKED && 3716 ni->ni_vap->iv_state == IEEE80211_S_AUTH) 3717 ieee80211_tx_complete(ni, m, 0); 3718 else 3719 ieee80211_tx_complete(ni, m, 3720 (status & IWN_TX_FAIL) != 0); 3721 3722 DPRINTF(sc, IWN_DEBUG_TRACE, "->%s: end\n",__func__); 3723 } 3724 3725 /* 3726 * Process a "command done" firmware notification. This is where we wakeup 3727 * processes waiting for a synchronous command completion. 3728 */ 3729 static void 3730 iwn_cmd_done(struct iwn_softc *sc, struct iwn_rx_desc *desc) 3731 { 3732 struct iwn_tx_ring *ring; 3733 struct iwn_tx_data *data; 3734 int cmd_queue_num; 3735 3736 if (sc->sc_flags & IWN_FLAG_PAN_SUPPORT) 3737 cmd_queue_num = IWN_PAN_CMD_QUEUE; 3738 else 3739 cmd_queue_num = IWN_CMD_QUEUE_NUM; 3740 3741 if ((desc->qid & IWN_RX_DESC_QID_MSK) != cmd_queue_num) 3742 return; /* Not a command ack. */ 3743 3744 ring = &sc->txq[cmd_queue_num]; 3745 data = &ring->data[desc->idx]; 3746 3747 /* If the command was mapped in an mbuf, free it. */ 3748 if (data->m != NULL) { 3749 bus_dmamap_sync(ring->data_dmat, data->map, 3750 BUS_DMASYNC_POSTWRITE); 3751 bus_dmamap_unload(ring->data_dmat, data->map); 3752 m_freem(data->m); 3753 data->m = NULL; 3754 } 3755 wakeup(&ring->desc[desc->idx]); 3756 } 3757 3758 static int 3759 iwn_ampdu_check_bitmap(uint64_t bitmap, int start, int idx) 3760 { 3761 int bit, shift; 3762 3763 bit = idx - start; 3764 shift = 0; 3765 if (bit >= 64) { 3766 shift = 0x100 - bit; 3767 bit = 0; 3768 } else if (bit <= -64) 3769 bit = 0x100 + bit; 3770 else if (bit < 0) { 3771 shift = -bit; 3772 bit = 0; 3773 } 3774 3775 if (bit - shift >= 64) 3776 return (0); 3777 3778 return ((bitmap & (1ULL << (bit - shift))) != 0); 3779 } 3780 3781 /* 3782 * Firmware bug workaround: in case if 'retries' counter 3783 * overflows 'seqno' field will be incremented: 3784 * status|sequence|status|sequence|status|sequence 3785 * 0000 0A48 0001 0A49 0000 0A6A 3786 * 1000 0A48 1000 0A49 1000 0A6A 3787 * 2000 0A48 2000 0A49 2000 0A6A 3788 * ... 3789 * E000 0A48 E000 0A49 E000 0A6A 3790 * F000 0A48 F000 0A49 F000 0A6A 3791 * 0000 0A49 0000 0A49 0000 0A6B 3792 * 1000 0A49 1000 0A49 1000 0A6B 3793 * ... 3794 * D000 0A49 D000 0A49 D000 0A6B 3795 * E000 0A49 E001 0A49 E000 0A6B 3796 * F000 0A49 F001 0A49 F000 0A6B 3797 * 0000 0A4A 0000 0A4B 0000 0A6A 3798 * 1000 0A4A 1000 0A4B 1000 0A6A 3799 * ... 3800 * 3801 * Odd 'seqno' numbers are incremened by 2 every 2 overflows. 3802 * For even 'seqno' % 4 != 0 overflow is cyclic (0 -> +1 -> 0). 3803 * Not checked with nretries >= 64. 3804 * 3805 */ 3806 static int 3807 iwn_ampdu_index_check(struct iwn_softc *sc, struct iwn_tx_ring *ring, 3808 uint64_t bitmap, int start, int idx) 3809 { 3810 struct ieee80211com *ic = &sc->sc_ic; 3811 struct iwn_tx_data *data; 3812 int diff, min_retries, max_retries, new_idx, loop_end; 3813 3814 new_idx = idx - IWN_LONG_RETRY_LIMIT_LOG; 3815 if (new_idx < 0) 3816 new_idx += IWN_TX_RING_COUNT; 3817 3818 /* 3819 * Corner case: check if retry count is not too big; 3820 * reset device otherwise. 3821 */ 3822 if (!iwn_ampdu_check_bitmap(bitmap, start, new_idx)) { 3823 data = &ring->data[new_idx]; 3824 if (data->long_retries > IWN_LONG_RETRY_LIMIT) { 3825 device_printf(sc->sc_dev, 3826 "%s: retry count (%d) for idx %d/%d overflow, " 3827 "resetting...\n", __func__, data->long_retries, 3828 ring->qid, new_idx); 3829 ieee80211_restart_all(ic); 3830 return (-1); 3831 } 3832 } 3833 3834 /* Correct index if needed. */ 3835 loop_end = idx; 3836 do { 3837 data = &ring->data[new_idx]; 3838 diff = idx - new_idx; 3839 if (diff < 0) 3840 diff += IWN_TX_RING_COUNT; 3841 3842 min_retries = IWN_LONG_RETRY_FW_OVERFLOW * diff; 3843 if ((new_idx % 2) == 0) 3844 max_retries = IWN_LONG_RETRY_FW_OVERFLOW * (diff + 1); 3845 else 3846 max_retries = IWN_LONG_RETRY_FW_OVERFLOW * (diff + 2); 3847 3848 if (!iwn_ampdu_check_bitmap(bitmap, start, new_idx) && 3849 ((data->long_retries >= min_retries && 3850 data->long_retries < max_retries) || 3851 (diff == 1 && 3852 (new_idx & 0x03) == 0x02 && 3853 data->long_retries >= IWN_LONG_RETRY_FW_OVERFLOW))) { 3854 DPRINTF(sc, IWN_DEBUG_AMPDU, 3855 "%s: correcting index %d -> %d in queue %d" 3856 " (retries %d)\n", __func__, idx, new_idx, 3857 ring->qid, data->long_retries); 3858 return (new_idx); 3859 } 3860 3861 new_idx = (new_idx + 1) % IWN_TX_RING_COUNT; 3862 } while (new_idx != loop_end); 3863 3864 return (idx); 3865 } 3866 3867 static void 3868 iwn_ampdu_tx_done(struct iwn_softc *sc, int qid, int nframes, int rtsfailcnt, 3869 void *stat) 3870 { 3871 struct iwn_tx_ring *ring = &sc->txq[qid]; 3872 struct ieee80211_tx_ampdu *tap = sc->qid2tap[qid]; 3873 struct iwn_node *wn = (void *)tap->txa_ni; 3874 struct iwn_tx_data *data; 3875 uint64_t bitmap = 0; 3876 uint16_t *aggstatus = stat; 3877 uint8_t tid = tap->txa_tid; 3878 int bit, i, idx, shift, start, tx_err; 3879 3880 DPRINTF(sc, IWN_DEBUG_TRACE, "->%s begin\n", __func__); 3881 3882 start = le16toh(*(aggstatus + nframes * 2)) & 0xff; 3883 3884 for (i = 0; i < nframes; i++) { 3885 uint16_t status = le16toh(aggstatus[i * 2]); 3886 3887 if (status & IWN_AGG_TX_STATE_IGNORE_MASK) 3888 continue; 3889 3890 idx = le16toh(aggstatus[i * 2 + 1]) & 0xff; 3891 data = &ring->data[idx]; 3892 if (data->remapped) { 3893 idx = iwn_ampdu_index_check(sc, ring, bitmap, start, idx); 3894 if (idx == -1) { 3895 /* skip error (device will be restarted anyway). */ 3896 continue; 3897 } 3898 3899 /* Index may have changed. */ 3900 data = &ring->data[idx]; 3901 } 3902 3903 /* 3904 * XXX Sometimes (rarely) some frames are excluded from events. 3905 * XXX Due to that long_retries counter may be wrong. 3906 */ 3907 data->long_retries &= ~0x0f; 3908 data->long_retries += IWN_AGG_TX_TRY_COUNT(status) + 1; 3909 3910 if (data->long_retries >= IWN_LONG_RETRY_FW_OVERFLOW) { 3911 int diff, wrong_idx; 3912 3913 diff = data->long_retries / IWN_LONG_RETRY_FW_OVERFLOW; 3914 wrong_idx = (idx + diff) % IWN_TX_RING_COUNT; 3915 3916 /* 3917 * Mark the entry so the above code will check it 3918 * next time. 3919 */ 3920 ring->data[wrong_idx].remapped = 1; 3921 } 3922 3923 if (status & IWN_AGG_TX_STATE_UNDERRUN_MSK) { 3924 /* 3925 * NB: count retries but postpone - it was not 3926 * transmitted. 3927 */ 3928 continue; 3929 } 3930 3931 bit = idx - start; 3932 shift = 0; 3933 if (bit >= 64) { 3934 shift = 0x100 - bit; 3935 bit = 0; 3936 } else if (bit <= -64) 3937 bit = 0x100 + bit; 3938 else if (bit < 0) { 3939 shift = -bit; 3940 bit = 0; 3941 } 3942 bitmap = bitmap << shift; 3943 bitmap |= 1ULL << bit; 3944 } 3945 wn->agg[tid].startidx = start; 3946 wn->agg[tid].bitmap = bitmap; 3947 wn->agg[tid].short_retries = rtsfailcnt; 3948 3949 DPRINTF(sc, IWN_DEBUG_AMPDU, "%s: nframes %d start %d bitmap %016jX\n", 3950 __func__, nframes, start, (uintmax_t)bitmap); 3951 3952 i = ring->read; 3953 3954 for (tx_err = 0; 3955 i != wn->agg[tid].startidx; 3956 i = (i + 1) % IWN_TX_RING_COUNT) { 3957 data = &ring->data[i]; 3958 data->remapped = 0; 3959 if (data->m == NULL) 3960 continue; 3961 3962 tx_err++; 3963 iwn_agg_tx_complete(sc, ring, tid, i, 0); 3964 } 3965 3966 ring->read = wn->agg[tid].startidx; 3967 ring->queued -= tx_err; 3968 3969 iwn_check_tx_ring(sc, qid); 3970 3971 DPRINTF(sc, IWN_DEBUG_TRACE, "->%s: end\n",__func__); 3972 } 3973 3974 /* 3975 * Process an INT_FH_RX or INT_SW_RX interrupt. 3976 */ 3977 static void 3978 iwn_notif_intr(struct iwn_softc *sc) 3979 { 3980 struct iwn_ops *ops = &sc->ops; 3981 struct ieee80211com *ic = &sc->sc_ic; 3982 struct ieee80211vap *vap = TAILQ_FIRST(&ic->ic_vaps); 3983 uint16_t hw; 3984 int is_stopped; 3985 3986 bus_dmamap_sync(sc->rxq.stat_dma.tag, sc->rxq.stat_dma.map, 3987 BUS_DMASYNC_POSTREAD); 3988 3989 hw = le16toh(sc->rxq.stat->closed_count) & 0xfff; 3990 while (sc->rxq.cur != hw) { 3991 struct iwn_rx_data *data = &sc->rxq.data[sc->rxq.cur]; 3992 struct iwn_rx_desc *desc; 3993 3994 bus_dmamap_sync(sc->rxq.data_dmat, data->map, 3995 BUS_DMASYNC_POSTREAD); 3996 desc = mtod(data->m, struct iwn_rx_desc *); 3997 3998 DPRINTF(sc, IWN_DEBUG_RECV, 3999 "%s: cur=%d; qid %x idx %d flags %x type %d(%s) len %d\n", 4000 __func__, sc->rxq.cur, desc->qid & IWN_RX_DESC_QID_MSK, 4001 desc->idx, desc->flags, desc->type, 4002 iwn_intr_str(desc->type), le16toh(desc->len)); 4003 4004 if (!(desc->qid & IWN_UNSOLICITED_RX_NOTIF)) /* Reply to a command. */ 4005 iwn_cmd_done(sc, desc); 4006 4007 switch (desc->type) { 4008 case IWN_RX_PHY: 4009 iwn_rx_phy(sc, desc); 4010 break; 4011 4012 case IWN_RX_DONE: /* 4965AGN only. */ 4013 case IWN_MPDU_RX_DONE: 4014 /* An 802.11 frame has been received. */ 4015 iwn_rx_done(sc, desc, data); 4016 4017 is_stopped = (sc->sc_flags & IWN_FLAG_RUNNING) == 0; 4018 if (__predict_false(is_stopped)) 4019 return; 4020 4021 break; 4022 4023 case IWN_RX_COMPRESSED_BA: 4024 /* A Compressed BlockAck has been received. */ 4025 iwn_rx_compressed_ba(sc, desc); 4026 break; 4027 4028 case IWN_TX_DONE: 4029 /* An 802.11 frame has been transmitted. */ 4030 ops->tx_done(sc, desc, data); 4031 break; 4032 4033 case IWN_RX_STATISTICS: 4034 case IWN_BEACON_STATISTICS: 4035 iwn_rx_statistics(sc, desc); 4036 break; 4037 4038 case IWN_BEACON_MISSED: 4039 { 4040 struct iwn_beacon_missed *miss = 4041 (struct iwn_beacon_missed *)(desc + 1); 4042 int misses; 4043 4044 misses = le32toh(miss->consecutive); 4045 4046 DPRINTF(sc, IWN_DEBUG_STATE, 4047 "%s: beacons missed %d/%d\n", __func__, 4048 misses, le32toh(miss->total)); 4049 /* 4050 * If more than 5 consecutive beacons are missed, 4051 * reinitialize the sensitivity state machine. 4052 */ 4053 if (vap->iv_state == IEEE80211_S_RUN && 4054 (ic->ic_flags & IEEE80211_F_SCAN) == 0) { 4055 if (misses > 5) 4056 (void)iwn_init_sensitivity(sc); 4057 if (misses >= vap->iv_bmissthreshold) { 4058 IWN_UNLOCK(sc); 4059 ieee80211_beacon_miss(ic); 4060 IWN_LOCK(sc); 4061 4062 is_stopped = (sc->sc_flags & 4063 IWN_FLAG_RUNNING) == 0; 4064 if (__predict_false(is_stopped)) 4065 return; 4066 } 4067 } 4068 break; 4069 } 4070 case IWN_UC_READY: 4071 { 4072 struct iwn_ucode_info *uc = 4073 (struct iwn_ucode_info *)(desc + 1); 4074 4075 /* The microcontroller is ready. */ 4076 DPRINTF(sc, IWN_DEBUG_RESET, 4077 "microcode alive notification version=%d.%d " 4078 "subtype=%x alive=%x\n", uc->major, uc->minor, 4079 uc->subtype, le32toh(uc->valid)); 4080 4081 if (le32toh(uc->valid) != 1) { 4082 device_printf(sc->sc_dev, 4083 "microcontroller initialization failed"); 4084 break; 4085 } 4086 if (uc->subtype == IWN_UCODE_INIT) { 4087 /* Save microcontroller report. */ 4088 memcpy(&sc->ucode_info, uc, sizeof (*uc)); 4089 } 4090 /* Save the address of the error log in SRAM. */ 4091 sc->errptr = le32toh(uc->errptr); 4092 break; 4093 } 4094 #ifdef IWN_DEBUG 4095 case IWN_STATE_CHANGED: 4096 { 4097 /* 4098 * State change allows hardware switch change to be 4099 * noted. However, we handle this in iwn_intr as we 4100 * get both the enable/disble intr. 4101 */ 4102 uint32_t *status = (uint32_t *)(desc + 1); 4103 DPRINTF(sc, IWN_DEBUG_INTR | IWN_DEBUG_STATE, 4104 "state changed to %x\n", 4105 le32toh(*status)); 4106 break; 4107 } 4108 case IWN_START_SCAN: 4109 { 4110 struct iwn_start_scan *scan = 4111 (struct iwn_start_scan *)(desc + 1); 4112 DPRINTF(sc, IWN_DEBUG_ANY, 4113 "%s: scanning channel %d status %x\n", 4114 __func__, scan->chan, le32toh(scan->status)); 4115 break; 4116 } 4117 #endif 4118 case IWN_STOP_SCAN: 4119 { 4120 #ifdef IWN_DEBUG 4121 struct iwn_stop_scan *scan = 4122 (struct iwn_stop_scan *)(desc + 1); 4123 DPRINTF(sc, IWN_DEBUG_STATE | IWN_DEBUG_SCAN, 4124 "scan finished nchan=%d status=%d chan=%d\n", 4125 scan->nchan, scan->status, scan->chan); 4126 #endif 4127 sc->sc_is_scanning = 0; 4128 callout_stop(&sc->scan_timeout); 4129 IWN_UNLOCK(sc); 4130 ieee80211_scan_next(vap); 4131 IWN_LOCK(sc); 4132 4133 is_stopped = (sc->sc_flags & IWN_FLAG_RUNNING) == 0; 4134 if (__predict_false(is_stopped)) 4135 return; 4136 4137 break; 4138 } 4139 case IWN5000_CALIBRATION_RESULT: 4140 iwn5000_rx_calib_results(sc, desc); 4141 break; 4142 4143 case IWN5000_CALIBRATION_DONE: 4144 sc->sc_flags |= IWN_FLAG_CALIB_DONE; 4145 wakeup(sc); 4146 break; 4147 } 4148 4149 sc->rxq.cur = (sc->rxq.cur + 1) % IWN_RX_RING_COUNT; 4150 } 4151 4152 /* Tell the firmware what we have processed. */ 4153 hw = (hw == 0) ? IWN_RX_RING_COUNT - 1 : hw - 1; 4154 IWN_WRITE(sc, IWN_FH_RX_WPTR, hw & ~7); 4155 } 4156 4157 /* 4158 * Process an INT_WAKEUP interrupt raised when the microcontroller wakes up 4159 * from power-down sleep mode. 4160 */ 4161 static void 4162 iwn_wakeup_intr(struct iwn_softc *sc) 4163 { 4164 int qid; 4165 4166 DPRINTF(sc, IWN_DEBUG_RESET, "%s: ucode wakeup from power-down sleep\n", 4167 __func__); 4168 4169 /* Wakeup RX and TX rings. */ 4170 IWN_WRITE(sc, IWN_FH_RX_WPTR, sc->rxq.cur & ~7); 4171 for (qid = 0; qid < sc->ntxqs; qid++) { 4172 struct iwn_tx_ring *ring = &sc->txq[qid]; 4173 IWN_WRITE(sc, IWN_HBUS_TARG_WRPTR, qid << 8 | ring->cur); 4174 } 4175 } 4176 4177 static void 4178 iwn_rftoggle_task(void *arg, int npending) 4179 { 4180 struct iwn_softc *sc = arg; 4181 struct ieee80211com *ic = &sc->sc_ic; 4182 uint32_t tmp; 4183 4184 IWN_LOCK(sc); 4185 tmp = IWN_READ(sc, IWN_GP_CNTRL); 4186 IWN_UNLOCK(sc); 4187 4188 device_printf(sc->sc_dev, "RF switch: radio %s\n", 4189 (tmp & IWN_GP_CNTRL_RFKILL) ? "enabled" : "disabled"); 4190 if (!(tmp & IWN_GP_CNTRL_RFKILL)) { 4191 ieee80211_suspend_all(ic); 4192 4193 /* Enable interrupts to get RF toggle notification. */ 4194 IWN_LOCK(sc); 4195 IWN_WRITE(sc, IWN_INT, 0xffffffff); 4196 IWN_WRITE(sc, IWN_INT_MASK, sc->int_mask); 4197 IWN_UNLOCK(sc); 4198 } else 4199 ieee80211_resume_all(ic); 4200 } 4201 4202 /* 4203 * Dump the error log of the firmware when a firmware panic occurs. Although 4204 * we can't debug the firmware because it is neither open source nor free, it 4205 * can help us to identify certain classes of problems. 4206 */ 4207 static void 4208 iwn_fatal_intr(struct iwn_softc *sc) 4209 { 4210 struct iwn_fw_dump dump; 4211 int i; 4212 4213 IWN_LOCK_ASSERT(sc); 4214 4215 /* Force a complete recalibration on next init. */ 4216 sc->sc_flags &= ~IWN_FLAG_CALIB_DONE; 4217 4218 /* Check that the error log address is valid. */ 4219 if (sc->errptr < IWN_FW_DATA_BASE || 4220 sc->errptr + sizeof (dump) > 4221 IWN_FW_DATA_BASE + sc->fw_data_maxsz) { 4222 printf("%s: bad firmware error log address 0x%08x\n", __func__, 4223 sc->errptr); 4224 return; 4225 } 4226 if (iwn_nic_lock(sc) != 0) { 4227 printf("%s: could not read firmware error log\n", __func__); 4228 return; 4229 } 4230 /* Read firmware error log from SRAM. */ 4231 iwn_mem_read_region_4(sc, sc->errptr, (uint32_t *)&dump, 4232 sizeof (dump) / sizeof (uint32_t)); 4233 iwn_nic_unlock(sc); 4234 4235 if (dump.valid == 0) { 4236 printf("%s: firmware error log is empty\n", __func__); 4237 return; 4238 } 4239 printf("firmware error log:\n"); 4240 printf(" error type = \"%s\" (0x%08X)\n", 4241 (dump.id < nitems(iwn_fw_errmsg)) ? 4242 iwn_fw_errmsg[dump.id] : "UNKNOWN", 4243 dump.id); 4244 printf(" program counter = 0x%08X\n", dump.pc); 4245 printf(" source line = 0x%08X\n", dump.src_line); 4246 printf(" error data = 0x%08X%08X\n", 4247 dump.error_data[0], dump.error_data[1]); 4248 printf(" branch link = 0x%08X%08X\n", 4249 dump.branch_link[0], dump.branch_link[1]); 4250 printf(" interrupt link = 0x%08X%08X\n", 4251 dump.interrupt_link[0], dump.interrupt_link[1]); 4252 printf(" time = %u\n", dump.time[0]); 4253 4254 /* Dump driver status (TX and RX rings) while we're here. */ 4255 printf("driver status:\n"); 4256 for (i = 0; i < sc->ntxqs; i++) { 4257 struct iwn_tx_ring *ring = &sc->txq[i]; 4258 printf(" tx ring %2d: qid=%-2d cur=%-3d queued=%-3d\n", 4259 i, ring->qid, ring->cur, ring->queued); 4260 } 4261 printf(" rx ring: cur=%d\n", sc->rxq.cur); 4262 } 4263 4264 static void 4265 iwn_intr(void *arg) 4266 { 4267 struct iwn_softc *sc = arg; 4268 uint32_t r1, r2, tmp; 4269 4270 IWN_LOCK(sc); 4271 4272 /* Disable interrupts. */ 4273 IWN_WRITE(sc, IWN_INT_MASK, 0); 4274 4275 /* Read interrupts from ICT (fast) or from registers (slow). */ 4276 if (sc->sc_flags & IWN_FLAG_USE_ICT) { 4277 bus_dmamap_sync(sc->ict_dma.tag, sc->ict_dma.map, 4278 BUS_DMASYNC_POSTREAD); 4279 tmp = 0; 4280 while (sc->ict[sc->ict_cur] != 0) { 4281 tmp |= sc->ict[sc->ict_cur]; 4282 sc->ict[sc->ict_cur] = 0; /* Acknowledge. */ 4283 sc->ict_cur = (sc->ict_cur + 1) % IWN_ICT_COUNT; 4284 } 4285 tmp = le32toh(tmp); 4286 if (tmp == 0xffffffff) /* Shouldn't happen. */ 4287 tmp = 0; 4288 else if (tmp & 0xc0000) /* Workaround a HW bug. */ 4289 tmp |= 0x8000; 4290 r1 = (tmp & 0xff00) << 16 | (tmp & 0xff); 4291 r2 = 0; /* Unused. */ 4292 } else { 4293 r1 = IWN_READ(sc, IWN_INT); 4294 if (r1 == 0xffffffff || (r1 & 0xfffffff0) == 0xa5a5a5a0) { 4295 IWN_UNLOCK(sc); 4296 return; /* Hardware gone! */ 4297 } 4298 r2 = IWN_READ(sc, IWN_FH_INT); 4299 } 4300 4301 DPRINTF(sc, IWN_DEBUG_INTR, "interrupt reg1=0x%08x reg2=0x%08x\n" 4302 , r1, r2); 4303 4304 if (r1 == 0 && r2 == 0) 4305 goto done; /* Interrupt not for us. */ 4306 4307 /* Acknowledge interrupts. */ 4308 IWN_WRITE(sc, IWN_INT, r1); 4309 if (!(sc->sc_flags & IWN_FLAG_USE_ICT)) 4310 IWN_WRITE(sc, IWN_FH_INT, r2); 4311 4312 if (r1 & IWN_INT_RF_TOGGLED) { 4313 taskqueue_enqueue(sc->sc_tq, &sc->sc_rftoggle_task); 4314 goto done; 4315 } 4316 if (r1 & IWN_INT_CT_REACHED) { 4317 device_printf(sc->sc_dev, "%s: critical temperature reached!\n", 4318 __func__); 4319 } 4320 if (r1 & (IWN_INT_SW_ERR | IWN_INT_HW_ERR)) { 4321 device_printf(sc->sc_dev, "%s: fatal firmware error\n", 4322 __func__); 4323 #ifdef IWN_DEBUG 4324 iwn_debug_register(sc); 4325 #endif 4326 /* Dump firmware error log and stop. */ 4327 iwn_fatal_intr(sc); 4328 4329 taskqueue_enqueue(sc->sc_tq, &sc->sc_panic_task); 4330 goto done; 4331 } 4332 if ((r1 & (IWN_INT_FH_RX | IWN_INT_SW_RX | IWN_INT_RX_PERIODIC)) || 4333 (r2 & IWN_FH_INT_RX)) { 4334 if (sc->sc_flags & IWN_FLAG_USE_ICT) { 4335 if (r1 & (IWN_INT_FH_RX | IWN_INT_SW_RX)) 4336 IWN_WRITE(sc, IWN_FH_INT, IWN_FH_INT_RX); 4337 IWN_WRITE_1(sc, IWN_INT_PERIODIC, 4338 IWN_INT_PERIODIC_DIS); 4339 iwn_notif_intr(sc); 4340 if (r1 & (IWN_INT_FH_RX | IWN_INT_SW_RX)) { 4341 IWN_WRITE_1(sc, IWN_INT_PERIODIC, 4342 IWN_INT_PERIODIC_ENA); 4343 } 4344 } else 4345 iwn_notif_intr(sc); 4346 } 4347 4348 if ((r1 & IWN_INT_FH_TX) || (r2 & IWN_FH_INT_TX)) { 4349 if (sc->sc_flags & IWN_FLAG_USE_ICT) 4350 IWN_WRITE(sc, IWN_FH_INT, IWN_FH_INT_TX); 4351 wakeup(sc); /* FH DMA transfer completed. */ 4352 } 4353 4354 if (r1 & IWN_INT_ALIVE) 4355 wakeup(sc); /* Firmware is alive. */ 4356 4357 if (r1 & IWN_INT_WAKEUP) 4358 iwn_wakeup_intr(sc); 4359 4360 done: 4361 /* Re-enable interrupts. */ 4362 if (sc->sc_flags & IWN_FLAG_RUNNING) 4363 IWN_WRITE(sc, IWN_INT_MASK, sc->int_mask); 4364 4365 IWN_UNLOCK(sc); 4366 } 4367 4368 /* 4369 * Update TX scheduler ring when transmitting an 802.11 frame (4965AGN and 4370 * 5000 adapters use a slightly different format). 4371 */ 4372 static void 4373 iwn4965_update_sched(struct iwn_softc *sc, int qid, int idx, uint8_t id, 4374 uint16_t len) 4375 { 4376 uint16_t *w = &sc->sched[qid * IWN4965_SCHED_COUNT + idx]; 4377 4378 DPRINTF(sc, IWN_DEBUG_TRACE, "->Doing %s\n", __func__); 4379 4380 *w = htole16(len + 8); 4381 bus_dmamap_sync(sc->sched_dma.tag, sc->sched_dma.map, 4382 BUS_DMASYNC_PREWRITE); 4383 if (idx < IWN_SCHED_WINSZ) { 4384 *(w + IWN_TX_RING_COUNT) = *w; 4385 bus_dmamap_sync(sc->sched_dma.tag, sc->sched_dma.map, 4386 BUS_DMASYNC_PREWRITE); 4387 } 4388 } 4389 4390 static void 4391 iwn5000_update_sched(struct iwn_softc *sc, int qid, int idx, uint8_t id, 4392 uint16_t len) 4393 { 4394 uint16_t *w = &sc->sched[qid * IWN5000_SCHED_COUNT + idx]; 4395 4396 DPRINTF(sc, IWN_DEBUG_TRACE, "->Doing %s\n", __func__); 4397 4398 *w = htole16(id << 12 | (len + 8)); 4399 bus_dmamap_sync(sc->sched_dma.tag, sc->sched_dma.map, 4400 BUS_DMASYNC_PREWRITE); 4401 if (idx < IWN_SCHED_WINSZ) { 4402 *(w + IWN_TX_RING_COUNT) = *w; 4403 bus_dmamap_sync(sc->sched_dma.tag, sc->sched_dma.map, 4404 BUS_DMASYNC_PREWRITE); 4405 } 4406 } 4407 4408 #ifdef notyet 4409 static void 4410 iwn5000_reset_sched(struct iwn_softc *sc, int qid, int idx) 4411 { 4412 uint16_t *w = &sc->sched[qid * IWN5000_SCHED_COUNT + idx]; 4413 4414 DPRINTF(sc, IWN_DEBUG_TRACE, "->Doing %s\n", __func__); 4415 4416 *w = (*w & htole16(0xf000)) | htole16(1); 4417 bus_dmamap_sync(sc->sched_dma.tag, sc->sched_dma.map, 4418 BUS_DMASYNC_PREWRITE); 4419 if (idx < IWN_SCHED_WINSZ) { 4420 *(w + IWN_TX_RING_COUNT) = *w; 4421 bus_dmamap_sync(sc->sched_dma.tag, sc->sched_dma.map, 4422 BUS_DMASYNC_PREWRITE); 4423 } 4424 } 4425 #endif 4426 4427 /* 4428 * Check whether OFDM 11g protection will be enabled for the given rate. 4429 * 4430 * The original driver code only enabled protection for OFDM rates. 4431 * It didn't check to see whether it was operating in 11a or 11bg mode. 4432 */ 4433 static int 4434 iwn_check_rate_needs_protection(struct iwn_softc *sc, 4435 struct ieee80211vap *vap, uint8_t rate) 4436 { 4437 struct ieee80211com *ic = vap->iv_ic; 4438 4439 /* 4440 * Not in 2GHz mode? Then there's no need to enable OFDM 4441 * 11bg protection. 4442 */ 4443 if (! IEEE80211_IS_CHAN_2GHZ(ic->ic_curchan)) { 4444 return (0); 4445 } 4446 4447 /* 4448 * 11bg protection not enabled? Then don't use it. 4449 */ 4450 if ((vap->iv_flags & IEEE80211_F_USEPROT) == 0) 4451 return (0); 4452 4453 /* 4454 * If it's an 11n rate - no protection. 4455 * We'll do it via a specific 11n check. 4456 */ 4457 if (rate & IEEE80211_RATE_MCS) { 4458 return (0); 4459 } 4460 4461 /* 4462 * Do a rate table lookup. If the PHY is CCK, 4463 * don't do protection. 4464 */ 4465 if (ieee80211_rate2phytype(ic->ic_rt, rate) == IEEE80211_T_CCK) 4466 return (0); 4467 4468 /* 4469 * Yup, enable protection. 4470 */ 4471 return (1); 4472 } 4473 4474 /* 4475 * return a value between 0 and IWN_MAX_TX_RETRIES-1 as an index into 4476 * the link quality table that reflects this particular entry. 4477 */ 4478 static int 4479 iwn_tx_rate_to_linkq_offset(struct iwn_softc *sc, struct ieee80211_node *ni, 4480 uint8_t rate) 4481 { 4482 struct ieee80211_rateset *rs; 4483 int is_11n; 4484 int nr; 4485 int i; 4486 uint8_t cmp_rate; 4487 4488 /* 4489 * Figure out if we're using 11n or not here. 4490 */ 4491 if (IEEE80211_IS_CHAN_HT(ni->ni_chan) && ni->ni_htrates.rs_nrates > 0) 4492 is_11n = 1; 4493 else 4494 is_11n = 0; 4495 4496 /* 4497 * Use the correct rate table. 4498 */ 4499 if (is_11n) { 4500 rs = (struct ieee80211_rateset *) &ni->ni_htrates; 4501 nr = ni->ni_htrates.rs_nrates; 4502 } else { 4503 rs = &ni->ni_rates; 4504 nr = rs->rs_nrates; 4505 } 4506 4507 /* 4508 * Find the relevant link quality entry in the table. 4509 */ 4510 for (i = 0; i < nr && i < IWN_MAX_TX_RETRIES - 1 ; i++) { 4511 /* 4512 * The link quality table index starts at 0 == highest 4513 * rate, so we walk the rate table backwards. 4514 */ 4515 cmp_rate = rs->rs_rates[(nr - 1) - i]; 4516 if (rate & IEEE80211_RATE_MCS) 4517 cmp_rate |= IEEE80211_RATE_MCS; 4518 4519 #if 0 4520 DPRINTF(sc, IWN_DEBUG_XMIT, "%s: idx %d: nr=%d, rate=0x%02x, rateentry=0x%02x\n", 4521 __func__, 4522 i, 4523 nr, 4524 rate, 4525 cmp_rate); 4526 #endif 4527 4528 if (cmp_rate == rate) 4529 return (i); 4530 } 4531 4532 /* Failed? Start at the end */ 4533 return (IWN_MAX_TX_RETRIES - 1); 4534 } 4535 4536 static int 4537 iwn_tx_data(struct iwn_softc *sc, struct mbuf *m, struct ieee80211_node *ni) 4538 { 4539 const struct ieee80211_txparam *tp = ni->ni_txparms; 4540 struct ieee80211vap *vap = ni->ni_vap; 4541 struct ieee80211com *ic = ni->ni_ic; 4542 struct iwn_node *wn = (void *)ni; 4543 struct iwn_tx_ring *ring; 4544 struct iwn_tx_cmd *cmd; 4545 struct iwn_cmd_data *tx; 4546 struct ieee80211_frame *wh; 4547 struct ieee80211_key *k = NULL; 4548 uint32_t flags; 4549 uint16_t qos; 4550 uint8_t tid, type; 4551 int ac, totlen, rate; 4552 4553 DPRINTF(sc, IWN_DEBUG_TRACE, "->%s begin\n", __func__); 4554 4555 IWN_LOCK_ASSERT(sc); 4556 4557 wh = mtod(m, struct ieee80211_frame *); 4558 type = wh->i_fc[0] & IEEE80211_FC0_TYPE_MASK; 4559 4560 /* Select EDCA Access Category and TX ring for this frame. */ 4561 if (IEEE80211_QOS_HAS_SEQ(wh)) { 4562 qos = ((const struct ieee80211_qosframe *)wh)->i_qos[0]; 4563 tid = qos & IEEE80211_QOS_TID; 4564 } else { 4565 qos = 0; 4566 tid = 0; 4567 } 4568 4569 /* Choose a TX rate index. */ 4570 if (type == IEEE80211_FC0_TYPE_MGT || 4571 type == IEEE80211_FC0_TYPE_CTL || 4572 (m->m_flags & M_EAPOL) != 0) 4573 rate = tp->mgmtrate; 4574 else if (IEEE80211_IS_MULTICAST(wh->i_addr1)) 4575 rate = tp->mcastrate; 4576 else if (tp->ucastrate != IEEE80211_FIXED_RATE_NONE) 4577 rate = tp->ucastrate; 4578 else { 4579 /* XXX pass pktlen */ 4580 (void) ieee80211_ratectl_rate(ni, NULL, 0); 4581 rate = ni->ni_txrate; 4582 } 4583 4584 /* 4585 * XXX TODO: Group addressed frames aren't aggregated and must 4586 * go to the normal non-aggregation queue, and have a NONQOS TID 4587 * assigned from net80211. 4588 */ 4589 4590 ac = M_WME_GETAC(m); 4591 if (m->m_flags & M_AMPDU_MPDU) { 4592 struct ieee80211_tx_ampdu *tap = &ni->ni_tx_ampdu[ac]; 4593 4594 if (!IEEE80211_AMPDU_RUNNING(tap)) 4595 return (EINVAL); 4596 4597 ac = *(int *)tap->txa_private; 4598 } 4599 4600 /* Encrypt the frame if need be. */ 4601 if (wh->i_fc[1] & IEEE80211_FC1_PROTECTED) { 4602 /* Retrieve key for TX. */ 4603 k = ieee80211_crypto_encap(ni, m); 4604 if (k == NULL) { 4605 return ENOBUFS; 4606 } 4607 /* 802.11 header may have moved. */ 4608 wh = mtod(m, struct ieee80211_frame *); 4609 } 4610 totlen = m->m_pkthdr.len; 4611 4612 if (ieee80211_radiotap_active_vap(vap)) { 4613 struct iwn_tx_radiotap_header *tap = &sc->sc_txtap; 4614 4615 tap->wt_flags = 0; 4616 tap->wt_rate = rate; 4617 if (k != NULL) 4618 tap->wt_flags |= IEEE80211_RADIOTAP_F_WEP; 4619 4620 ieee80211_radiotap_tx(vap, m); 4621 } 4622 4623 flags = 0; 4624 if (!IEEE80211_IS_MULTICAST(wh->i_addr1)) { 4625 /* Unicast frame, check if an ACK is expected. */ 4626 if (!qos || (qos & IEEE80211_QOS_ACKPOLICY) != 4627 IEEE80211_QOS_ACKPOLICY_NOACK) 4628 flags |= IWN_TX_NEED_ACK; 4629 } 4630 if ((wh->i_fc[0] & 4631 (IEEE80211_FC0_TYPE_MASK | IEEE80211_FC0_SUBTYPE_MASK)) == 4632 (IEEE80211_FC0_TYPE_CTL | IEEE80211_FC0_SUBTYPE_BAR)) 4633 flags |= IWN_TX_IMM_BA; /* Cannot happen yet. */ 4634 4635 if (wh->i_fc[1] & IEEE80211_FC1_MORE_FRAG) 4636 flags |= IWN_TX_MORE_FRAG; /* Cannot happen yet. */ 4637 4638 /* Check if frame must be protected using RTS/CTS or CTS-to-self. */ 4639 if (!IEEE80211_IS_MULTICAST(wh->i_addr1)) { 4640 /* NB: Group frames are sent using CCK in 802.11b/g. */ 4641 if (totlen + IEEE80211_CRC_LEN > vap->iv_rtsthreshold) { 4642 flags |= IWN_TX_NEED_RTS; 4643 } else if (iwn_check_rate_needs_protection(sc, vap, rate)) { 4644 if (ic->ic_protmode == IEEE80211_PROT_CTSONLY) 4645 flags |= IWN_TX_NEED_CTS; 4646 else if (ic->ic_protmode == IEEE80211_PROT_RTSCTS) 4647 flags |= IWN_TX_NEED_RTS; 4648 } else if ((rate & IEEE80211_RATE_MCS) && 4649 (ic->ic_htprotmode == IEEE80211_PROT_RTSCTS)) { 4650 flags |= IWN_TX_NEED_RTS; 4651 } 4652 4653 /* XXX HT protection? */ 4654 4655 if (flags & (IWN_TX_NEED_RTS | IWN_TX_NEED_CTS)) { 4656 if (sc->hw_type != IWN_HW_REV_TYPE_4965) { 4657 /* 5000 autoselects RTS/CTS or CTS-to-self. */ 4658 flags &= ~(IWN_TX_NEED_RTS | IWN_TX_NEED_CTS); 4659 flags |= IWN_TX_NEED_PROTECTION; 4660 } else 4661 flags |= IWN_TX_FULL_TXOP; 4662 } 4663 } 4664 4665 ring = &sc->txq[ac]; 4666 if (m->m_flags & M_AMPDU_MPDU) { 4667 uint16_t seqno = ni->ni_txseqs[tid]; 4668 4669 if (ring->queued > IWN_TX_RING_COUNT / 2 && 4670 (ring->cur + 1) % IWN_TX_RING_COUNT == ring->read) { 4671 DPRINTF(sc, IWN_DEBUG_AMPDU, "%s: no more space " 4672 "(queued %d) left in %d queue!\n", 4673 __func__, ring->queued, ac); 4674 return (ENOBUFS); 4675 } 4676 4677 /* 4678 * Queue this frame to the hardware ring that we've 4679 * negotiated AMPDU TX on. 4680 * 4681 * Note that the sequence number must match the TX slot 4682 * being used! 4683 */ 4684 if ((seqno % 256) != ring->cur) { 4685 device_printf(sc->sc_dev, 4686 "%s: m=%p: seqno (%d) (%d) != ring index (%d) !\n", 4687 __func__, 4688 m, 4689 seqno, 4690 seqno % 256, 4691 ring->cur); 4692 4693 /* XXX until D9195 will not be committed */ 4694 ni->ni_txseqs[tid] &= ~0xff; 4695 ni->ni_txseqs[tid] += ring->cur; 4696 seqno = ni->ni_txseqs[tid]; 4697 } 4698 4699 *(uint16_t *)wh->i_seq = 4700 htole16(seqno << IEEE80211_SEQ_SEQ_SHIFT); 4701 ni->ni_txseqs[tid]++; 4702 } 4703 4704 /* Prepare TX firmware command. */ 4705 cmd = &ring->cmd[ring->cur]; 4706 tx = (struct iwn_cmd_data *)cmd->data; 4707 4708 /* NB: No need to clear tx, all fields are reinitialized here. */ 4709 tx->scratch = 0; /* clear "scratch" area */ 4710 4711 if (IEEE80211_IS_MULTICAST(wh->i_addr1) || 4712 type != IEEE80211_FC0_TYPE_DATA) 4713 tx->id = sc->broadcast_id; 4714 else 4715 tx->id = wn->id; 4716 4717 if (type == IEEE80211_FC0_TYPE_MGT) { 4718 uint8_t subtype = wh->i_fc[0] & IEEE80211_FC0_SUBTYPE_MASK; 4719 4720 /* Tell HW to set timestamp in probe responses. */ 4721 if (subtype == IEEE80211_FC0_SUBTYPE_PROBE_RESP) 4722 flags |= IWN_TX_INSERT_TSTAMP; 4723 if (subtype == IEEE80211_FC0_SUBTYPE_ASSOC_REQ || 4724 subtype == IEEE80211_FC0_SUBTYPE_REASSOC_REQ) 4725 tx->timeout = htole16(3); 4726 else 4727 tx->timeout = htole16(2); 4728 } else 4729 tx->timeout = htole16(0); 4730 4731 if (tx->id == sc->broadcast_id) { 4732 /* Group or management frame. */ 4733 tx->linkq = 0; 4734 } else { 4735 tx->linkq = iwn_tx_rate_to_linkq_offset(sc, ni, rate); 4736 flags |= IWN_TX_LINKQ; /* enable MRR */ 4737 } 4738 4739 tx->tid = tid; 4740 tx->rts_ntries = 60; 4741 tx->data_ntries = 15; 4742 tx->lifetime = htole32(IWN_LIFETIME_INFINITE); 4743 tx->rate = iwn_rate_to_plcp(sc, ni, rate); 4744 tx->security = 0; 4745 tx->flags = htole32(flags); 4746 4747 return (iwn_tx_cmd(sc, m, ni, ring)); 4748 } 4749 4750 static int 4751 iwn_tx_data_raw(struct iwn_softc *sc, struct mbuf *m, 4752 struct ieee80211_node *ni, const struct ieee80211_bpf_params *params) 4753 { 4754 struct ieee80211vap *vap = ni->ni_vap; 4755 struct iwn_tx_cmd *cmd; 4756 struct iwn_cmd_data *tx; 4757 struct ieee80211_frame *wh; 4758 struct iwn_tx_ring *ring; 4759 uint32_t flags; 4760 int ac, rate; 4761 uint8_t type; 4762 4763 DPRINTF(sc, IWN_DEBUG_TRACE, "->%s begin\n", __func__); 4764 4765 IWN_LOCK_ASSERT(sc); 4766 4767 wh = mtod(m, struct ieee80211_frame *); 4768 type = wh->i_fc[0] & IEEE80211_FC0_TYPE_MASK; 4769 4770 ac = params->ibp_pri & 3; 4771 4772 /* Choose a TX rate. */ 4773 rate = params->ibp_rate0; 4774 4775 flags = 0; 4776 if ((params->ibp_flags & IEEE80211_BPF_NOACK) == 0) 4777 flags |= IWN_TX_NEED_ACK; 4778 if (params->ibp_flags & IEEE80211_BPF_RTS) { 4779 if (sc->hw_type != IWN_HW_REV_TYPE_4965) { 4780 /* 5000 autoselects RTS/CTS or CTS-to-self. */ 4781 flags &= ~IWN_TX_NEED_RTS; 4782 flags |= IWN_TX_NEED_PROTECTION; 4783 } else 4784 flags |= IWN_TX_NEED_RTS | IWN_TX_FULL_TXOP; 4785 } 4786 if (params->ibp_flags & IEEE80211_BPF_CTS) { 4787 if (sc->hw_type != IWN_HW_REV_TYPE_4965) { 4788 /* 5000 autoselects RTS/CTS or CTS-to-self. */ 4789 flags &= ~IWN_TX_NEED_CTS; 4790 flags |= IWN_TX_NEED_PROTECTION; 4791 } else 4792 flags |= IWN_TX_NEED_CTS | IWN_TX_FULL_TXOP; 4793 } 4794 4795 if (ieee80211_radiotap_active_vap(vap)) { 4796 struct iwn_tx_radiotap_header *tap = &sc->sc_txtap; 4797 4798 tap->wt_flags = 0; 4799 tap->wt_rate = rate; 4800 4801 ieee80211_radiotap_tx(vap, m); 4802 } 4803 4804 ring = &sc->txq[ac]; 4805 cmd = &ring->cmd[ring->cur]; 4806 4807 tx = (struct iwn_cmd_data *)cmd->data; 4808 /* NB: No need to clear tx, all fields are reinitialized here. */ 4809 tx->scratch = 0; /* clear "scratch" area */ 4810 4811 if (type == IEEE80211_FC0_TYPE_MGT) { 4812 uint8_t subtype = wh->i_fc[0] & IEEE80211_FC0_SUBTYPE_MASK; 4813 4814 /* Tell HW to set timestamp in probe responses. */ 4815 if (subtype == IEEE80211_FC0_SUBTYPE_PROBE_RESP) 4816 flags |= IWN_TX_INSERT_TSTAMP; 4817 4818 if (subtype == IEEE80211_FC0_SUBTYPE_ASSOC_REQ || 4819 subtype == IEEE80211_FC0_SUBTYPE_REASSOC_REQ) 4820 tx->timeout = htole16(3); 4821 else 4822 tx->timeout = htole16(2); 4823 } else 4824 tx->timeout = htole16(0); 4825 4826 tx->tid = 0; 4827 tx->id = sc->broadcast_id; 4828 tx->rts_ntries = params->ibp_try1; 4829 tx->data_ntries = params->ibp_try0; 4830 tx->lifetime = htole32(IWN_LIFETIME_INFINITE); 4831 tx->rate = iwn_rate_to_plcp(sc, ni, rate); 4832 tx->security = 0; 4833 tx->flags = htole32(flags); 4834 4835 /* Group or management frame. */ 4836 tx->linkq = 0; 4837 4838 return (iwn_tx_cmd(sc, m, ni, ring)); 4839 } 4840 4841 static int 4842 iwn_tx_cmd(struct iwn_softc *sc, struct mbuf *m, struct ieee80211_node *ni, 4843 struct iwn_tx_ring *ring) 4844 { 4845 struct iwn_ops *ops = &sc->ops; 4846 struct iwn_tx_cmd *cmd; 4847 struct iwn_cmd_data *tx; 4848 struct ieee80211_frame *wh; 4849 struct iwn_tx_desc *desc; 4850 struct iwn_tx_data *data; 4851 bus_dma_segment_t *seg, segs[IWN_MAX_SCATTER]; 4852 struct mbuf *m1; 4853 u_int hdrlen; 4854 int totlen, error, pad, nsegs = 0, i; 4855 4856 wh = mtod(m, struct ieee80211_frame *); 4857 hdrlen = ieee80211_anyhdrsize(wh); 4858 totlen = m->m_pkthdr.len; 4859 4860 desc = &ring->desc[ring->cur]; 4861 data = &ring->data[ring->cur]; 4862 4863 if (__predict_false(data->m != NULL || data->ni != NULL)) { 4864 device_printf(sc->sc_dev, "%s: ni (%p) or m (%p) for idx %d " 4865 "in queue %d is not NULL!\n", __func__, data->ni, data->m, 4866 ring->cur, ring->qid); 4867 return EIO; 4868 } 4869 4870 /* Prepare TX firmware command. */ 4871 cmd = &ring->cmd[ring->cur]; 4872 cmd->code = IWN_CMD_TX_DATA; 4873 cmd->flags = 0; 4874 cmd->qid = ring->qid; 4875 cmd->idx = ring->cur; 4876 4877 tx = (struct iwn_cmd_data *)cmd->data; 4878 tx->len = htole16(totlen); 4879 4880 /* Set physical address of "scratch area". */ 4881 tx->loaddr = htole32(IWN_LOADDR(data->scratch_paddr)); 4882 tx->hiaddr = IWN_HIADDR(data->scratch_paddr); 4883 if (hdrlen & 3) { 4884 /* First segment length must be a multiple of 4. */ 4885 tx->flags |= htole32(IWN_TX_NEED_PADDING); 4886 pad = 4 - (hdrlen & 3); 4887 } else 4888 pad = 0; 4889 4890 /* Copy 802.11 header in TX command. */ 4891 memcpy((uint8_t *)(tx + 1), wh, hdrlen); 4892 4893 /* Trim 802.11 header. */ 4894 m_adj(m, hdrlen); 4895 4896 error = bus_dmamap_load_mbuf_sg(ring->data_dmat, data->map, m, segs, 4897 &nsegs, BUS_DMA_NOWAIT); 4898 if (error != 0) { 4899 if (error != EFBIG) { 4900 device_printf(sc->sc_dev, 4901 "%s: can't map mbuf (error %d)\n", __func__, error); 4902 return error; 4903 } 4904 /* Too many DMA segments, linearize mbuf. */ 4905 m1 = m_collapse(m, M_NOWAIT, IWN_MAX_SCATTER - 1); 4906 if (m1 == NULL) { 4907 device_printf(sc->sc_dev, 4908 "%s: could not defrag mbuf\n", __func__); 4909 return ENOBUFS; 4910 } 4911 m = m1; 4912 4913 error = bus_dmamap_load_mbuf_sg(ring->data_dmat, data->map, m, 4914 segs, &nsegs, BUS_DMA_NOWAIT); 4915 if (error != 0) { 4916 /* XXX fix this */ 4917 /* 4918 * NB: Do not return error; 4919 * original mbuf does not exist anymore. 4920 */ 4921 device_printf(sc->sc_dev, 4922 "%s: can't map mbuf (error %d)\n", 4923 __func__, error); 4924 if_inc_counter(ni->ni_vap->iv_ifp, 4925 IFCOUNTER_OERRORS, 1); 4926 ieee80211_free_node(ni); 4927 m_freem(m); 4928 return 0; 4929 } 4930 } 4931 4932 data->m = m; 4933 data->ni = ni; 4934 4935 DPRINTF(sc, IWN_DEBUG_XMIT, "%s: qid %d idx %d len %d nsegs %d " 4936 "plcp 0x%x\n", 4937 __func__, ring->qid, ring->cur, totlen, nsegs, tx->rate); 4938 4939 /* Fill TX descriptor. */ 4940 desc->nsegs = 1; 4941 if (m->m_len != 0) 4942 desc->nsegs += nsegs; 4943 /* First DMA segment is used by the TX command. */ 4944 desc->segs[0].addr = htole32(IWN_LOADDR(data->cmd_paddr)); 4945 desc->segs[0].len = htole16(IWN_HIADDR(data->cmd_paddr) | 4946 (4 + sizeof (*tx) + hdrlen + pad) << 4); 4947 /* Other DMA segments are for data payload. */ 4948 seg = &segs[0]; 4949 for (i = 1; i <= nsegs; i++) { 4950 desc->segs[i].addr = htole32(IWN_LOADDR(seg->ds_addr)); 4951 desc->segs[i].len = htole16(IWN_HIADDR(seg->ds_addr) | 4952 seg->ds_len << 4); 4953 seg++; 4954 } 4955 4956 bus_dmamap_sync(ring->data_dmat, data->map, BUS_DMASYNC_PREWRITE); 4957 bus_dmamap_sync(ring->cmd_dma.tag, ring->cmd_dma.map, 4958 BUS_DMASYNC_PREWRITE); 4959 bus_dmamap_sync(ring->desc_dma.tag, ring->desc_dma.map, 4960 BUS_DMASYNC_PREWRITE); 4961 4962 /* Update TX scheduler. */ 4963 if (ring->qid >= sc->firstaggqueue) 4964 ops->update_sched(sc, ring->qid, ring->cur, tx->id, totlen); 4965 4966 /* Kick TX ring. */ 4967 ring->cur = (ring->cur + 1) % IWN_TX_RING_COUNT; 4968 IWN_WRITE(sc, IWN_HBUS_TARG_WRPTR, ring->qid << 8 | ring->cur); 4969 4970 /* Mark TX ring as full if we reach a certain threshold. */ 4971 if (++ring->queued > IWN_TX_RING_HIMARK) 4972 sc->qfullmsk |= 1 << ring->qid; 4973 4974 DPRINTF(sc, IWN_DEBUG_TRACE, "->%s: end\n",__func__); 4975 4976 return 0; 4977 } 4978 4979 static void 4980 iwn_xmit_task(void *arg0, int pending) 4981 { 4982 struct iwn_softc *sc = arg0; 4983 struct ieee80211_node *ni; 4984 struct mbuf *m; 4985 int error; 4986 struct ieee80211_bpf_params p; 4987 int have_p; 4988 4989 DPRINTF(sc, IWN_DEBUG_XMIT, "%s: called\n", __func__); 4990 4991 IWN_LOCK(sc); 4992 /* 4993 * Dequeue frames, attempt to transmit, 4994 * then disable beaconwait when we're done. 4995 */ 4996 while ((m = mbufq_dequeue(&sc->sc_xmit_queue)) != NULL) { 4997 have_p = 0; 4998 ni = (struct ieee80211_node *)m->m_pkthdr.rcvif; 4999 5000 /* Get xmit params if appropriate */ 5001 if (ieee80211_get_xmit_params(m, &p) == 0) 5002 have_p = 1; 5003 5004 DPRINTF(sc, IWN_DEBUG_XMIT, "%s: m=%p, have_p=%d\n", 5005 __func__, m, have_p); 5006 5007 /* If we have xmit params, use them */ 5008 if (have_p) 5009 error = iwn_tx_data_raw(sc, m, ni, &p); 5010 else 5011 error = iwn_tx_data(sc, m, ni); 5012 5013 if (error != 0) { 5014 if_inc_counter(ni->ni_vap->iv_ifp, 5015 IFCOUNTER_OERRORS, 1); 5016 ieee80211_free_node(ni); 5017 m_freem(m); 5018 } 5019 } 5020 5021 sc->sc_beacon_wait = 0; 5022 IWN_UNLOCK(sc); 5023 } 5024 5025 /* 5026 * raw frame xmit - free node/reference if failed. 5027 */ 5028 static int 5029 iwn_raw_xmit(struct ieee80211_node *ni, struct mbuf *m, 5030 const struct ieee80211_bpf_params *params) 5031 { 5032 struct ieee80211com *ic = ni->ni_ic; 5033 struct iwn_softc *sc = ic->ic_softc; 5034 int error = 0; 5035 5036 DPRINTF(sc, IWN_DEBUG_XMIT | IWN_DEBUG_TRACE, "->%s begin\n", __func__); 5037 5038 IWN_LOCK(sc); 5039 if ((sc->sc_flags & IWN_FLAG_RUNNING) == 0) { 5040 m_freem(m); 5041 IWN_UNLOCK(sc); 5042 return (ENETDOWN); 5043 } 5044 5045 /* queue frame if we have to */ 5046 if (sc->sc_beacon_wait) { 5047 if (iwn_xmit_queue_enqueue(sc, m) != 0) { 5048 m_freem(m); 5049 IWN_UNLOCK(sc); 5050 return (ENOBUFS); 5051 } 5052 /* Queued, so just return OK */ 5053 IWN_UNLOCK(sc); 5054 return (0); 5055 } 5056 5057 if (params == NULL) { 5058 /* 5059 * Legacy path; interpret frame contents to decide 5060 * precisely how to send the frame. 5061 */ 5062 error = iwn_tx_data(sc, m, ni); 5063 } else { 5064 /* 5065 * Caller supplied explicit parameters to use in 5066 * sending the frame. 5067 */ 5068 error = iwn_tx_data_raw(sc, m, ni, params); 5069 } 5070 if (error == 0) 5071 sc->sc_tx_timer = 5; 5072 else 5073 m_freem(m); 5074 5075 IWN_UNLOCK(sc); 5076 5077 DPRINTF(sc, IWN_DEBUG_TRACE | IWN_DEBUG_XMIT, "->%s: end\n",__func__); 5078 5079 return (error); 5080 } 5081 5082 /* 5083 * transmit - don't free mbuf if failed; don't free node ref if failed. 5084 */ 5085 static int 5086 iwn_transmit(struct ieee80211com *ic, struct mbuf *m) 5087 { 5088 struct iwn_softc *sc = ic->ic_softc; 5089 struct ieee80211_node *ni; 5090 int error; 5091 5092 ni = (struct ieee80211_node *)m->m_pkthdr.rcvif; 5093 5094 IWN_LOCK(sc); 5095 if ((sc->sc_flags & IWN_FLAG_RUNNING) == 0 || sc->sc_beacon_wait) { 5096 IWN_UNLOCK(sc); 5097 return (ENXIO); 5098 } 5099 5100 if (sc->qfullmsk) { 5101 IWN_UNLOCK(sc); 5102 return (ENOBUFS); 5103 } 5104 5105 error = iwn_tx_data(sc, m, ni); 5106 if (!error) 5107 sc->sc_tx_timer = 5; 5108 IWN_UNLOCK(sc); 5109 return (error); 5110 } 5111 5112 static void 5113 iwn_scan_timeout(void *arg) 5114 { 5115 struct iwn_softc *sc = arg; 5116 struct ieee80211com *ic = &sc->sc_ic; 5117 5118 ic_printf(ic, "scan timeout\n"); 5119 ieee80211_restart_all(ic); 5120 } 5121 5122 static void 5123 iwn_watchdog(void *arg) 5124 { 5125 struct iwn_softc *sc = arg; 5126 struct ieee80211com *ic = &sc->sc_ic; 5127 5128 IWN_LOCK_ASSERT(sc); 5129 5130 KASSERT(sc->sc_flags & IWN_FLAG_RUNNING, ("not running")); 5131 5132 DPRINTF(sc, IWN_DEBUG_TRACE, "->Doing %s\n", __func__); 5133 5134 if (sc->sc_tx_timer > 0) { 5135 if (--sc->sc_tx_timer == 0) { 5136 ic_printf(ic, "device timeout\n"); 5137 ieee80211_restart_all(ic); 5138 return; 5139 } 5140 } 5141 callout_reset(&sc->watchdog_to, hz, iwn_watchdog, sc); 5142 } 5143 5144 static int 5145 iwn_cdev_open(struct cdev *dev, int flags, int type, struct thread *td) 5146 { 5147 5148 return (0); 5149 } 5150 5151 static int 5152 iwn_cdev_close(struct cdev *dev, int flags, int type, struct thread *td) 5153 { 5154 5155 return (0); 5156 } 5157 5158 static int 5159 iwn_cdev_ioctl(struct cdev *dev, unsigned long cmd, caddr_t data, int fflag, 5160 struct thread *td) 5161 { 5162 int rc; 5163 struct iwn_softc *sc = dev->si_drv1; 5164 struct iwn_ioctl_data *d; 5165 5166 rc = priv_check(td, PRIV_DRIVER); 5167 if (rc != 0) 5168 return (0); 5169 5170 switch (cmd) { 5171 case SIOCGIWNSTATS: 5172 d = (struct iwn_ioctl_data *) data; 5173 IWN_LOCK(sc); 5174 /* XXX validate permissions/memory/etc? */ 5175 rc = copyout(&sc->last_stat, d->dst_addr, sizeof(struct iwn_stats)); 5176 IWN_UNLOCK(sc); 5177 break; 5178 case SIOCZIWNSTATS: 5179 IWN_LOCK(sc); 5180 memset(&sc->last_stat, 0, sizeof(struct iwn_stats)); 5181 IWN_UNLOCK(sc); 5182 break; 5183 default: 5184 rc = EINVAL; 5185 break; 5186 } 5187 return (rc); 5188 } 5189 5190 static int 5191 iwn_ioctl(struct ieee80211com *ic, u_long cmd, void *data) 5192 { 5193 5194 return (ENOTTY); 5195 } 5196 5197 static void 5198 iwn_parent(struct ieee80211com *ic) 5199 { 5200 struct iwn_softc *sc = ic->ic_softc; 5201 struct ieee80211vap *vap; 5202 int error; 5203 5204 if (ic->ic_nrunning > 0) { 5205 error = iwn_init(sc); 5206 5207 switch (error) { 5208 case 0: 5209 ieee80211_start_all(ic); 5210 break; 5211 case 1: 5212 /* radio is disabled via RFkill switch */ 5213 taskqueue_enqueue(sc->sc_tq, &sc->sc_rftoggle_task); 5214 break; 5215 default: 5216 vap = TAILQ_FIRST(&ic->ic_vaps); 5217 if (vap != NULL) 5218 ieee80211_stop(vap); 5219 break; 5220 } 5221 } else 5222 iwn_stop(sc); 5223 } 5224 5225 /* 5226 * Send a command to the firmware. 5227 */ 5228 static int 5229 iwn_cmd(struct iwn_softc *sc, int code, const void *buf, int size, int async) 5230 { 5231 struct iwn_tx_ring *ring; 5232 struct iwn_tx_desc *desc; 5233 struct iwn_tx_data *data; 5234 struct iwn_tx_cmd *cmd; 5235 struct mbuf *m; 5236 bus_addr_t paddr; 5237 int totlen, error; 5238 int cmd_queue_num; 5239 5240 DPRINTF(sc, IWN_DEBUG_TRACE, "->%s begin\n", __func__); 5241 5242 if (async == 0) 5243 IWN_LOCK_ASSERT(sc); 5244 5245 if (sc->sc_flags & IWN_FLAG_PAN_SUPPORT) 5246 cmd_queue_num = IWN_PAN_CMD_QUEUE; 5247 else 5248 cmd_queue_num = IWN_CMD_QUEUE_NUM; 5249 5250 ring = &sc->txq[cmd_queue_num]; 5251 desc = &ring->desc[ring->cur]; 5252 data = &ring->data[ring->cur]; 5253 totlen = 4 + size; 5254 5255 if (size > sizeof cmd->data) { 5256 /* Command is too large to fit in a descriptor. */ 5257 if (totlen > MCLBYTES) 5258 return EINVAL; 5259 m = m_getjcl(M_NOWAIT, MT_DATA, M_PKTHDR, MJUMPAGESIZE); 5260 if (m == NULL) 5261 return ENOMEM; 5262 cmd = mtod(m, struct iwn_tx_cmd *); 5263 error = bus_dmamap_load(ring->data_dmat, data->map, cmd, 5264 totlen, iwn_dma_map_addr, &paddr, BUS_DMA_NOWAIT); 5265 if (error != 0) { 5266 m_freem(m); 5267 return error; 5268 } 5269 data->m = m; 5270 } else { 5271 cmd = &ring->cmd[ring->cur]; 5272 paddr = data->cmd_paddr; 5273 } 5274 5275 cmd->code = code; 5276 cmd->flags = 0; 5277 cmd->qid = ring->qid; 5278 cmd->idx = ring->cur; 5279 memcpy(cmd->data, buf, size); 5280 5281 desc->nsegs = 1; 5282 desc->segs[0].addr = htole32(IWN_LOADDR(paddr)); 5283 desc->segs[0].len = htole16(IWN_HIADDR(paddr) | totlen << 4); 5284 5285 DPRINTF(sc, IWN_DEBUG_CMD, "%s: %s (0x%x) flags %d qid %d idx %d\n", 5286 __func__, iwn_intr_str(cmd->code), cmd->code, 5287 cmd->flags, cmd->qid, cmd->idx); 5288 5289 if (size > sizeof cmd->data) { 5290 bus_dmamap_sync(ring->data_dmat, data->map, 5291 BUS_DMASYNC_PREWRITE); 5292 } else { 5293 bus_dmamap_sync(ring->cmd_dma.tag, ring->cmd_dma.map, 5294 BUS_DMASYNC_PREWRITE); 5295 } 5296 bus_dmamap_sync(ring->desc_dma.tag, ring->desc_dma.map, 5297 BUS_DMASYNC_PREWRITE); 5298 5299 /* Kick command ring. */ 5300 ring->cur = (ring->cur + 1) % IWN_TX_RING_COUNT; 5301 IWN_WRITE(sc, IWN_HBUS_TARG_WRPTR, ring->qid << 8 | ring->cur); 5302 5303 DPRINTF(sc, IWN_DEBUG_TRACE, "->%s: end\n",__func__); 5304 5305 return async ? 0 : msleep(desc, &sc->sc_mtx, PCATCH, "iwncmd", hz); 5306 } 5307 5308 static int 5309 iwn4965_add_node(struct iwn_softc *sc, struct iwn_node_info *node, int async) 5310 { 5311 struct iwn4965_node_info hnode; 5312 caddr_t src, dst; 5313 5314 DPRINTF(sc, IWN_DEBUG_TRACE, "->Doing %s\n", __func__); 5315 5316 /* 5317 * We use the node structure for 5000 Series internally (it is 5318 * a superset of the one for 4965AGN). We thus copy the common 5319 * fields before sending the command. 5320 */ 5321 src = (caddr_t)node; 5322 dst = (caddr_t)&hnode; 5323 memcpy(dst, src, 48); 5324 /* Skip TSC, RX MIC and TX MIC fields from ``src''. */ 5325 memcpy(dst + 48, src + 72, 20); 5326 return iwn_cmd(sc, IWN_CMD_ADD_NODE, &hnode, sizeof hnode, async); 5327 } 5328 5329 static int 5330 iwn5000_add_node(struct iwn_softc *sc, struct iwn_node_info *node, int async) 5331 { 5332 5333 DPRINTF(sc, IWN_DEBUG_TRACE, "->Doing %s\n", __func__); 5334 5335 /* Direct mapping. */ 5336 return iwn_cmd(sc, IWN_CMD_ADD_NODE, node, sizeof (*node), async); 5337 } 5338 5339 static int 5340 iwn_set_link_quality(struct iwn_softc *sc, struct ieee80211_node *ni) 5341 { 5342 struct iwn_node *wn = (void *)ni; 5343 struct ieee80211_rateset *rs; 5344 struct iwn_cmd_link_quality linkq; 5345 int i, rate, txrate; 5346 int is_11n; 5347 5348 DPRINTF(sc, IWN_DEBUG_TRACE, "->%s begin\n", __func__); 5349 5350 memset(&linkq, 0, sizeof linkq); 5351 linkq.id = wn->id; 5352 linkq.antmsk_1stream = iwn_get_1stream_tx_antmask(sc); 5353 linkq.antmsk_2stream = iwn_get_2stream_tx_antmask(sc); 5354 5355 linkq.ampdu_max = 32; /* XXX negotiated? */ 5356 linkq.ampdu_threshold = 3; 5357 linkq.ampdu_limit = htole16(4000); /* 4ms */ 5358 5359 DPRINTF(sc, IWN_DEBUG_XMIT, 5360 "%s: 1stream antenna=0x%02x, 2stream antenna=0x%02x, ntxstreams=%d\n", 5361 __func__, 5362 linkq.antmsk_1stream, 5363 linkq.antmsk_2stream, 5364 sc->ntxchains); 5365 5366 /* 5367 * Are we using 11n rates? Ensure the channel is 5368 * 11n _and_ we have some 11n rates, or don't 5369 * try. 5370 */ 5371 if (IEEE80211_IS_CHAN_HT(ni->ni_chan) && ni->ni_htrates.rs_nrates > 0) { 5372 rs = (struct ieee80211_rateset *) &ni->ni_htrates; 5373 is_11n = 1; 5374 } else { 5375 rs = &ni->ni_rates; 5376 is_11n = 0; 5377 } 5378 5379 /* Start at highest available bit-rate. */ 5380 /* 5381 * XXX this is all very dirty! 5382 */ 5383 if (is_11n) 5384 txrate = ni->ni_htrates.rs_nrates - 1; 5385 else 5386 txrate = rs->rs_nrates - 1; 5387 for (i = 0; i < IWN_MAX_TX_RETRIES; i++) { 5388 uint32_t plcp; 5389 5390 /* 5391 * XXX TODO: ensure the last two slots are the two lowest 5392 * rate entries, just for now. 5393 */ 5394 if (i == 14 || i == 15) 5395 txrate = 0; 5396 5397 if (is_11n) 5398 rate = IEEE80211_RATE_MCS | rs->rs_rates[txrate]; 5399 else 5400 rate = IEEE80211_RV(rs->rs_rates[txrate]); 5401 5402 /* Do rate -> PLCP config mapping */ 5403 plcp = iwn_rate_to_plcp(sc, ni, rate); 5404 linkq.retry[i] = plcp; 5405 DPRINTF(sc, IWN_DEBUG_XMIT, 5406 "%s: i=%d, txrate=%d, rate=0x%02x, plcp=0x%08x\n", 5407 __func__, 5408 i, 5409 txrate, 5410 rate, 5411 le32toh(plcp)); 5412 5413 /* 5414 * The mimo field is an index into the table which 5415 * indicates the first index where it and subsequent entries 5416 * will not be using MIMO. 5417 * 5418 * Since we're filling linkq from 0..15 and we're filling 5419 * from the highest MCS rates to the lowest rates, if we 5420 * _are_ doing a dual-stream rate, set mimo to idx+1 (ie, 5421 * the next entry.) That way if the next entry is a non-MIMO 5422 * entry, we're already pointing at it. 5423 */ 5424 if ((le32toh(plcp) & IWN_RFLAG_MCS) && 5425 IEEE80211_RV(le32toh(plcp)) > 7) 5426 linkq.mimo = i + 1; 5427 5428 /* Next retry at immediate lower bit-rate. */ 5429 if (txrate > 0) 5430 txrate--; 5431 } 5432 /* 5433 * If we reached the end of the list and indeed we hit 5434 * all MIMO rates (eg 5300 doing MCS23-15) then yes, 5435 * set mimo to 15. Setting it to 16 panics the firmware. 5436 */ 5437 if (linkq.mimo > 15) 5438 linkq.mimo = 15; 5439 5440 DPRINTF(sc, IWN_DEBUG_XMIT, "%s: mimo = %d\n", __func__, linkq.mimo); 5441 5442 DPRINTF(sc, IWN_DEBUG_TRACE, "->%s: end\n",__func__); 5443 5444 return iwn_cmd(sc, IWN_CMD_LINK_QUALITY, &linkq, sizeof linkq, 1); 5445 } 5446 5447 /* 5448 * Broadcast node is used to send group-addressed and management frames. 5449 */ 5450 static int 5451 iwn_add_broadcast_node(struct iwn_softc *sc, int async) 5452 { 5453 struct iwn_ops *ops = &sc->ops; 5454 struct ieee80211com *ic = &sc->sc_ic; 5455 struct iwn_node_info node; 5456 struct iwn_cmd_link_quality linkq; 5457 uint8_t txant; 5458 int i, error; 5459 5460 DPRINTF(sc, IWN_DEBUG_TRACE, "->%s begin\n", __func__); 5461 5462 sc->rxon = &sc->rx_on[IWN_RXON_BSS_CTX]; 5463 5464 memset(&node, 0, sizeof node); 5465 IEEE80211_ADDR_COPY(node.macaddr, ieee80211broadcastaddr); 5466 node.id = sc->broadcast_id; 5467 DPRINTF(sc, IWN_DEBUG_RESET, "%s: adding broadcast node\n", __func__); 5468 if ((error = ops->add_node(sc, &node, async)) != 0) 5469 return error; 5470 5471 /* Use the first valid TX antenna. */ 5472 txant = IWN_LSB(sc->txchainmask); 5473 5474 memset(&linkq, 0, sizeof linkq); 5475 linkq.id = sc->broadcast_id; 5476 linkq.antmsk_1stream = iwn_get_1stream_tx_antmask(sc); 5477 linkq.antmsk_2stream = iwn_get_2stream_tx_antmask(sc); 5478 linkq.ampdu_max = 64; 5479 linkq.ampdu_threshold = 3; 5480 linkq.ampdu_limit = htole16(4000); /* 4ms */ 5481 5482 /* Use lowest mandatory bit-rate. */ 5483 /* XXX rate table lookup? */ 5484 if (IEEE80211_IS_CHAN_5GHZ(ic->ic_curchan)) 5485 linkq.retry[0] = htole32(0xd); 5486 else 5487 linkq.retry[0] = htole32(10 | IWN_RFLAG_CCK); 5488 linkq.retry[0] |= htole32(IWN_RFLAG_ANT(txant)); 5489 /* Use same bit-rate for all TX retries. */ 5490 for (i = 1; i < IWN_MAX_TX_RETRIES; i++) { 5491 linkq.retry[i] = linkq.retry[0]; 5492 } 5493 5494 DPRINTF(sc, IWN_DEBUG_TRACE, "->%s: end\n",__func__); 5495 5496 return iwn_cmd(sc, IWN_CMD_LINK_QUALITY, &linkq, sizeof linkq, async); 5497 } 5498 5499 static int 5500 iwn_updateedca(struct ieee80211com *ic) 5501 { 5502 #define IWN_EXP2(x) ((1 << (x)) - 1) /* CWmin = 2^ECWmin - 1 */ 5503 struct iwn_softc *sc = ic->ic_softc; 5504 struct iwn_edca_params cmd; 5505 struct chanAccParams chp; 5506 int aci; 5507 5508 DPRINTF(sc, IWN_DEBUG_TRACE, "->%s begin\n", __func__); 5509 5510 ieee80211_wme_ic_getparams(ic, &chp); 5511 5512 memset(&cmd, 0, sizeof cmd); 5513 cmd.flags = htole32(IWN_EDCA_UPDATE); 5514 5515 IEEE80211_LOCK(ic); 5516 for (aci = 0; aci < WME_NUM_AC; aci++) { 5517 const struct wmeParams *ac = &chp.cap_wmeParams[aci]; 5518 cmd.ac[aci].aifsn = ac->wmep_aifsn; 5519 cmd.ac[aci].cwmin = htole16(IWN_EXP2(ac->wmep_logcwmin)); 5520 cmd.ac[aci].cwmax = htole16(IWN_EXP2(ac->wmep_logcwmax)); 5521 cmd.ac[aci].txoplimit = 5522 htole16(IEEE80211_TXOP_TO_US(ac->wmep_txopLimit)); 5523 } 5524 IEEE80211_UNLOCK(ic); 5525 5526 IWN_LOCK(sc); 5527 (void)iwn_cmd(sc, IWN_CMD_EDCA_PARAMS, &cmd, sizeof cmd, 1); 5528 IWN_UNLOCK(sc); 5529 5530 DPRINTF(sc, IWN_DEBUG_TRACE, "->%s: end\n",__func__); 5531 5532 return 0; 5533 #undef IWN_EXP2 5534 } 5535 5536 static void 5537 iwn_set_promisc(struct iwn_softc *sc) 5538 { 5539 struct ieee80211com *ic = &sc->sc_ic; 5540 uint32_t promisc_filter; 5541 5542 promisc_filter = IWN_FILTER_CTL | IWN_FILTER_PROMISC; 5543 if (ic->ic_promisc > 0 || ic->ic_opmode == IEEE80211_M_MONITOR) 5544 sc->rxon->filter |= htole32(promisc_filter); 5545 else 5546 sc->rxon->filter &= ~htole32(promisc_filter); 5547 } 5548 5549 static void 5550 iwn_update_promisc(struct ieee80211com *ic) 5551 { 5552 struct iwn_softc *sc = ic->ic_softc; 5553 int error; 5554 5555 if (ic->ic_opmode == IEEE80211_M_MONITOR) 5556 return; /* nothing to do */ 5557 5558 IWN_LOCK(sc); 5559 if (!(sc->sc_flags & IWN_FLAG_RUNNING)) { 5560 IWN_UNLOCK(sc); 5561 return; 5562 } 5563 5564 iwn_set_promisc(sc); 5565 if ((error = iwn_send_rxon(sc, 1, 1)) != 0) { 5566 device_printf(sc->sc_dev, 5567 "%s: could not send RXON, error %d\n", 5568 __func__, error); 5569 } 5570 IWN_UNLOCK(sc); 5571 } 5572 5573 static void 5574 iwn_update_mcast(struct ieee80211com *ic) 5575 { 5576 /* Ignore */ 5577 } 5578 5579 static void 5580 iwn_set_led(struct iwn_softc *sc, uint8_t which, uint8_t off, uint8_t on) 5581 { 5582 struct iwn_cmd_led led; 5583 5584 DPRINTF(sc, IWN_DEBUG_TRACE, "->Doing %s\n", __func__); 5585 5586 #if 0 5587 /* XXX don't set LEDs during scan? */ 5588 if (sc->sc_is_scanning) 5589 return; 5590 #endif 5591 5592 /* Clear microcode LED ownership. */ 5593 IWN_CLRBITS(sc, IWN_LED, IWN_LED_BSM_CTRL); 5594 5595 led.which = which; 5596 led.unit = htole32(10000); /* on/off in unit of 100ms */ 5597 led.off = off; 5598 led.on = on; 5599 (void)iwn_cmd(sc, IWN_CMD_SET_LED, &led, sizeof led, 1); 5600 } 5601 5602 /* 5603 * Set the critical temperature at which the firmware will stop the radio 5604 * and notify us. 5605 */ 5606 static int 5607 iwn_set_critical_temp(struct iwn_softc *sc) 5608 { 5609 struct iwn_critical_temp crit; 5610 int32_t temp; 5611 5612 DPRINTF(sc, IWN_DEBUG_TRACE, "->Doing %s\n", __func__); 5613 5614 IWN_WRITE(sc, IWN_UCODE_GP1_CLR, IWN_UCODE_GP1_CTEMP_STOP_RF); 5615 5616 if (sc->hw_type == IWN_HW_REV_TYPE_5150) 5617 temp = (IWN_CTOK(110) - sc->temp_off) * -5; 5618 else if (sc->hw_type == IWN_HW_REV_TYPE_4965) 5619 temp = IWN_CTOK(110); 5620 else 5621 temp = 110; 5622 memset(&crit, 0, sizeof crit); 5623 crit.tempR = htole32(temp); 5624 DPRINTF(sc, IWN_DEBUG_RESET, "setting critical temp to %d\n", temp); 5625 return iwn_cmd(sc, IWN_CMD_SET_CRITICAL_TEMP, &crit, sizeof crit, 0); 5626 } 5627 5628 static int 5629 iwn_set_timing(struct iwn_softc *sc, struct ieee80211_node *ni) 5630 { 5631 struct iwn_cmd_timing cmd; 5632 uint64_t val, mod; 5633 5634 DPRINTF(sc, IWN_DEBUG_TRACE, "->Doing %s\n", __func__); 5635 5636 memset(&cmd, 0, sizeof cmd); 5637 memcpy(&cmd.tstamp, ni->ni_tstamp.data, sizeof (uint64_t)); 5638 cmd.bintval = htole16(ni->ni_intval); 5639 cmd.lintval = htole16(10); 5640 5641 /* Compute remaining time until next beacon. */ 5642 val = (uint64_t)ni->ni_intval * IEEE80211_DUR_TU; 5643 mod = le64toh(cmd.tstamp) % val; 5644 cmd.binitval = htole32((uint32_t)(val - mod)); 5645 5646 DPRINTF(sc, IWN_DEBUG_RESET, "timing bintval=%u tstamp=%ju, init=%u\n", 5647 ni->ni_intval, le64toh(cmd.tstamp), (uint32_t)(val - mod)); 5648 5649 return iwn_cmd(sc, IWN_CMD_TIMING, &cmd, sizeof cmd, 1); 5650 } 5651 5652 static void 5653 iwn4965_power_calibration(struct iwn_softc *sc, int temp) 5654 { 5655 5656 DPRINTF(sc, IWN_DEBUG_TRACE, "->Doing %s\n", __func__); 5657 5658 /* Adjust TX power if need be (delta >= 3 degC). */ 5659 DPRINTF(sc, IWN_DEBUG_CALIBRATE, "%s: temperature %d->%d\n", 5660 __func__, sc->temp, temp); 5661 if (abs(temp - sc->temp) >= 3) { 5662 /* Record temperature of last calibration. */ 5663 sc->temp = temp; 5664 (void)iwn4965_set_txpower(sc, 1); 5665 } 5666 } 5667 5668 /* 5669 * Set TX power for current channel (each rate has its own power settings). 5670 * This function takes into account the regulatory information from EEPROM, 5671 * the current temperature and the current voltage. 5672 */ 5673 static int 5674 iwn4965_set_txpower(struct iwn_softc *sc, int async) 5675 { 5676 /* Fixed-point arithmetic division using a n-bit fractional part. */ 5677 #define fdivround(a, b, n) \ 5678 ((((1 << n) * (a)) / (b) + (1 << n) / 2) / (1 << n)) 5679 /* Linear interpolation. */ 5680 #define interpolate(x, x1, y1, x2, y2, n) \ 5681 ((y1) + fdivround(((int)(x) - (x1)) * ((y2) - (y1)), (x2) - (x1), n)) 5682 5683 static const int tdiv[IWN_NATTEN_GROUPS] = { 9, 8, 8, 8, 6 }; 5684 struct iwn_ucode_info *uc = &sc->ucode_info; 5685 struct iwn4965_cmd_txpower cmd; 5686 struct iwn4965_eeprom_chan_samples *chans; 5687 const uint8_t *rf_gain, *dsp_gain; 5688 int32_t vdiff, tdiff; 5689 int i, is_chan_5ghz, c, grp, maxpwr; 5690 uint8_t chan; 5691 5692 sc->rxon = &sc->rx_on[IWN_RXON_BSS_CTX]; 5693 /* Retrieve current channel from last RXON. */ 5694 chan = sc->rxon->chan; 5695 is_chan_5ghz = (sc->rxon->flags & htole32(IWN_RXON_24GHZ)) == 0; 5696 DPRINTF(sc, IWN_DEBUG_RESET, "setting TX power for channel %d\n", 5697 chan); 5698 5699 memset(&cmd, 0, sizeof cmd); 5700 cmd.band = is_chan_5ghz ? 0 : 1; 5701 cmd.chan = chan; 5702 5703 if (is_chan_5ghz) { 5704 maxpwr = sc->maxpwr5GHz; 5705 rf_gain = iwn4965_rf_gain_5ghz; 5706 dsp_gain = iwn4965_dsp_gain_5ghz; 5707 } else { 5708 maxpwr = sc->maxpwr2GHz; 5709 rf_gain = iwn4965_rf_gain_2ghz; 5710 dsp_gain = iwn4965_dsp_gain_2ghz; 5711 } 5712 5713 /* Compute voltage compensation. */ 5714 vdiff = ((int32_t)le32toh(uc->volt) - sc->eeprom_voltage) / 7; 5715 if (vdiff > 0) 5716 vdiff *= 2; 5717 if (abs(vdiff) > 2) 5718 vdiff = 0; 5719 DPRINTF(sc, IWN_DEBUG_CALIBRATE | IWN_DEBUG_TXPOW, 5720 "%s: voltage compensation=%d (UCODE=%d, EEPROM=%d)\n", 5721 __func__, vdiff, le32toh(uc->volt), sc->eeprom_voltage); 5722 5723 /* Get channel attenuation group. */ 5724 if (chan <= 20) /* 1-20 */ 5725 grp = 4; 5726 else if (chan <= 43) /* 34-43 */ 5727 grp = 0; 5728 else if (chan <= 70) /* 44-70 */ 5729 grp = 1; 5730 else if (chan <= 124) /* 71-124 */ 5731 grp = 2; 5732 else /* 125-200 */ 5733 grp = 3; 5734 DPRINTF(sc, IWN_DEBUG_CALIBRATE | IWN_DEBUG_TXPOW, 5735 "%s: chan %d, attenuation group=%d\n", __func__, chan, grp); 5736 5737 /* Get channel sub-band. */ 5738 for (i = 0; i < IWN_NBANDS; i++) 5739 if (sc->bands[i].lo != 0 && 5740 sc->bands[i].lo <= chan && chan <= sc->bands[i].hi) 5741 break; 5742 if (i == IWN_NBANDS) /* Can't happen in real-life. */ 5743 return EINVAL; 5744 chans = sc->bands[i].chans; 5745 DPRINTF(sc, IWN_DEBUG_CALIBRATE | IWN_DEBUG_TXPOW, 5746 "%s: chan %d sub-band=%d\n", __func__, chan, i); 5747 5748 for (c = 0; c < 2; c++) { 5749 uint8_t power, gain, temp; 5750 int maxchpwr, pwr, ridx, idx; 5751 5752 power = interpolate(chan, 5753 chans[0].num, chans[0].samples[c][1].power, 5754 chans[1].num, chans[1].samples[c][1].power, 1); 5755 gain = interpolate(chan, 5756 chans[0].num, chans[0].samples[c][1].gain, 5757 chans[1].num, chans[1].samples[c][1].gain, 1); 5758 temp = interpolate(chan, 5759 chans[0].num, chans[0].samples[c][1].temp, 5760 chans[1].num, chans[1].samples[c][1].temp, 1); 5761 DPRINTF(sc, IWN_DEBUG_CALIBRATE | IWN_DEBUG_TXPOW, 5762 "%s: Tx chain %d: power=%d gain=%d temp=%d\n", 5763 __func__, c, power, gain, temp); 5764 5765 /* Compute temperature compensation. */ 5766 tdiff = ((sc->temp - temp) * 2) / tdiv[grp]; 5767 DPRINTF(sc, IWN_DEBUG_CALIBRATE | IWN_DEBUG_TXPOW, 5768 "%s: temperature compensation=%d (current=%d, EEPROM=%d)\n", 5769 __func__, tdiff, sc->temp, temp); 5770 5771 for (ridx = 0; ridx <= IWN_RIDX_MAX; ridx++) { 5772 /* Convert dBm to half-dBm. */ 5773 maxchpwr = sc->maxpwr[chan] * 2; 5774 if ((ridx / 8) & 1) 5775 maxchpwr -= 6; /* MIMO 2T: -3dB */ 5776 5777 pwr = maxpwr; 5778 5779 /* Adjust TX power based on rate. */ 5780 if ((ridx % 8) == 5) 5781 pwr -= 15; /* OFDM48: -7.5dB */ 5782 else if ((ridx % 8) == 6) 5783 pwr -= 17; /* OFDM54: -8.5dB */ 5784 else if ((ridx % 8) == 7) 5785 pwr -= 20; /* OFDM60: -10dB */ 5786 else 5787 pwr -= 10; /* Others: -5dB */ 5788 5789 /* Do not exceed channel max TX power. */ 5790 if (pwr > maxchpwr) 5791 pwr = maxchpwr; 5792 5793 idx = gain - (pwr - power) - tdiff - vdiff; 5794 if ((ridx / 8) & 1) /* MIMO */ 5795 idx += (int32_t)le32toh(uc->atten[grp][c]); 5796 5797 if (cmd.band == 0) 5798 idx += 9; /* 5GHz */ 5799 if (ridx == IWN_RIDX_MAX) 5800 idx += 5; /* CCK */ 5801 5802 /* Make sure idx stays in a valid range. */ 5803 if (idx < 0) 5804 idx = 0; 5805 else if (idx > IWN4965_MAX_PWR_INDEX) 5806 idx = IWN4965_MAX_PWR_INDEX; 5807 5808 DPRINTF(sc, IWN_DEBUG_CALIBRATE | IWN_DEBUG_TXPOW, 5809 "%s: Tx chain %d, rate idx %d: power=%d\n", 5810 __func__, c, ridx, idx); 5811 cmd.power[ridx].rf_gain[c] = rf_gain[idx]; 5812 cmd.power[ridx].dsp_gain[c] = dsp_gain[idx]; 5813 } 5814 } 5815 5816 DPRINTF(sc, IWN_DEBUG_CALIBRATE | IWN_DEBUG_TXPOW, 5817 "%s: set tx power for chan %d\n", __func__, chan); 5818 return iwn_cmd(sc, IWN_CMD_TXPOWER, &cmd, sizeof cmd, async); 5819 5820 #undef interpolate 5821 #undef fdivround 5822 } 5823 5824 static int 5825 iwn5000_set_txpower(struct iwn_softc *sc, int async) 5826 { 5827 struct iwn5000_cmd_txpower cmd; 5828 int cmdid; 5829 5830 DPRINTF(sc, IWN_DEBUG_TRACE, "->Doing %s\n", __func__); 5831 5832 /* 5833 * TX power calibration is handled automatically by the firmware 5834 * for 5000 Series. 5835 */ 5836 memset(&cmd, 0, sizeof cmd); 5837 cmd.global_limit = 2 * IWN5000_TXPOWER_MAX_DBM; /* 16 dBm */ 5838 cmd.flags = IWN5000_TXPOWER_NO_CLOSED; 5839 cmd.srv_limit = IWN5000_TXPOWER_AUTO; 5840 DPRINTF(sc, IWN_DEBUG_CALIBRATE | IWN_DEBUG_XMIT, 5841 "%s: setting TX power; rev=%d\n", 5842 __func__, 5843 IWN_UCODE_API(sc->ucode_rev)); 5844 if (IWN_UCODE_API(sc->ucode_rev) == 1) 5845 cmdid = IWN_CMD_TXPOWER_DBM_V1; 5846 else 5847 cmdid = IWN_CMD_TXPOWER_DBM; 5848 return iwn_cmd(sc, cmdid, &cmd, sizeof cmd, async); 5849 } 5850 5851 /* 5852 * Retrieve the maximum RSSI (in dBm) among receivers. 5853 */ 5854 static int 5855 iwn4965_get_rssi(struct iwn_softc *sc, struct iwn_rx_stat *stat) 5856 { 5857 struct iwn4965_rx_phystat *phy = (void *)stat->phybuf; 5858 uint8_t mask, agc; 5859 int rssi; 5860 5861 DPRINTF(sc, IWN_DEBUG_TRACE, "->Doing %s\n", __func__); 5862 5863 mask = (le16toh(phy->antenna) >> 4) & IWN_ANT_ABC; 5864 agc = (le16toh(phy->agc) >> 7) & 0x7f; 5865 5866 rssi = 0; 5867 if (mask & IWN_ANT_A) 5868 rssi = MAX(rssi, phy->rssi[0]); 5869 if (mask & IWN_ANT_B) 5870 rssi = MAX(rssi, phy->rssi[2]); 5871 if (mask & IWN_ANT_C) 5872 rssi = MAX(rssi, phy->rssi[4]); 5873 5874 DPRINTF(sc, IWN_DEBUG_RECV, 5875 "%s: agc %d mask 0x%x rssi %d %d %d result %d\n", __func__, agc, 5876 mask, phy->rssi[0], phy->rssi[2], phy->rssi[4], 5877 rssi - agc - IWN_RSSI_TO_DBM); 5878 return rssi - agc - IWN_RSSI_TO_DBM; 5879 } 5880 5881 static int 5882 iwn5000_get_rssi(struct iwn_softc *sc, struct iwn_rx_stat *stat) 5883 { 5884 struct iwn5000_rx_phystat *phy = (void *)stat->phybuf; 5885 uint8_t agc; 5886 int rssi; 5887 5888 DPRINTF(sc, IWN_DEBUG_TRACE, "->Doing %s\n", __func__); 5889 5890 agc = (le32toh(phy->agc) >> 9) & 0x7f; 5891 5892 rssi = MAX(le16toh(phy->rssi[0]) & 0xff, 5893 le16toh(phy->rssi[1]) & 0xff); 5894 rssi = MAX(le16toh(phy->rssi[2]) & 0xff, rssi); 5895 5896 DPRINTF(sc, IWN_DEBUG_RECV, 5897 "%s: agc %d rssi %d %d %d result %d\n", __func__, agc, 5898 phy->rssi[0], phy->rssi[1], phy->rssi[2], 5899 rssi - agc - IWN_RSSI_TO_DBM); 5900 return rssi - agc - IWN_RSSI_TO_DBM; 5901 } 5902 5903 /* 5904 * Retrieve the average noise (in dBm) among receivers. 5905 */ 5906 static int 5907 iwn_get_noise(const struct iwn_rx_general_stats *stats) 5908 { 5909 int i, total, nbant, noise; 5910 5911 total = nbant = 0; 5912 for (i = 0; i < 3; i++) { 5913 if ((noise = le32toh(stats->noise[i]) & 0xff) == 0) 5914 continue; 5915 total += noise; 5916 nbant++; 5917 } 5918 /* There should be at least one antenna but check anyway. */ 5919 return (nbant == 0) ? -127 : (total / nbant) - 107; 5920 } 5921 5922 /* 5923 * Compute temperature (in degC) from last received statistics. 5924 */ 5925 static int 5926 iwn4965_get_temperature(struct iwn_softc *sc) 5927 { 5928 struct iwn_ucode_info *uc = &sc->ucode_info; 5929 int32_t r1, r2, r3, r4, temp; 5930 5931 DPRINTF(sc, IWN_DEBUG_TRACE, "->Doing %s\n", __func__); 5932 5933 r1 = le32toh(uc->temp[0].chan20MHz); 5934 r2 = le32toh(uc->temp[1].chan20MHz); 5935 r3 = le32toh(uc->temp[2].chan20MHz); 5936 r4 = le32toh(sc->rawtemp); 5937 5938 if (r1 == r3) /* Prevents division by 0 (should not happen). */ 5939 return 0; 5940 5941 /* Sign-extend 23-bit R4 value to 32-bit. */ 5942 r4 = ((r4 & 0xffffff) ^ 0x800000) - 0x800000; 5943 /* Compute temperature in Kelvin. */ 5944 temp = (259 * (r4 - r2)) / (r3 - r1); 5945 temp = (temp * 97) / 100 + 8; 5946 5947 DPRINTF(sc, IWN_DEBUG_ANY, "temperature %dK/%dC\n", temp, 5948 IWN_KTOC(temp)); 5949 return IWN_KTOC(temp); 5950 } 5951 5952 static int 5953 iwn5000_get_temperature(struct iwn_softc *sc) 5954 { 5955 int32_t temp; 5956 5957 DPRINTF(sc, IWN_DEBUG_TRACE, "->Doing %s\n", __func__); 5958 5959 /* 5960 * Temperature is not used by the driver for 5000 Series because 5961 * TX power calibration is handled by firmware. 5962 */ 5963 temp = le32toh(sc->rawtemp); 5964 if (sc->hw_type == IWN_HW_REV_TYPE_5150) { 5965 temp = (temp / -5) + sc->temp_off; 5966 temp = IWN_KTOC(temp); 5967 } 5968 return temp; 5969 } 5970 5971 /* 5972 * Initialize sensitivity calibration state machine. 5973 */ 5974 static int 5975 iwn_init_sensitivity(struct iwn_softc *sc) 5976 { 5977 struct iwn_ops *ops = &sc->ops; 5978 struct iwn_calib_state *calib = &sc->calib; 5979 uint32_t flags; 5980 int error; 5981 5982 DPRINTF(sc, IWN_DEBUG_TRACE, "->Doing %s\n", __func__); 5983 5984 /* Reset calibration state machine. */ 5985 memset(calib, 0, sizeof (*calib)); 5986 calib->state = IWN_CALIB_STATE_INIT; 5987 calib->cck_state = IWN_CCK_STATE_HIFA; 5988 /* Set initial correlation values. */ 5989 calib->ofdm_x1 = sc->limits->min_ofdm_x1; 5990 calib->ofdm_mrc_x1 = sc->limits->min_ofdm_mrc_x1; 5991 calib->ofdm_x4 = sc->limits->min_ofdm_x4; 5992 calib->ofdm_mrc_x4 = sc->limits->min_ofdm_mrc_x4; 5993 calib->cck_x4 = 125; 5994 calib->cck_mrc_x4 = sc->limits->min_cck_mrc_x4; 5995 calib->energy_cck = sc->limits->energy_cck; 5996 5997 /* Write initial sensitivity. */ 5998 if ((error = iwn_send_sensitivity(sc)) != 0) 5999 return error; 6000 6001 /* Write initial gains. */ 6002 if ((error = ops->init_gains(sc)) != 0) 6003 return error; 6004 6005 /* Request statistics at each beacon interval. */ 6006 flags = 0; 6007 DPRINTF(sc, IWN_DEBUG_CALIBRATE, "%s: sending request for statistics\n", 6008 __func__); 6009 return iwn_cmd(sc, IWN_CMD_GET_STATISTICS, &flags, sizeof flags, 1); 6010 } 6011 6012 /* 6013 * Collect noise and RSSI statistics for the first 20 beacons received 6014 * after association and use them to determine connected antennas and 6015 * to set differential gains. 6016 */ 6017 static void 6018 iwn_collect_noise(struct iwn_softc *sc, 6019 const struct iwn_rx_general_stats *stats) 6020 { 6021 struct iwn_ops *ops = &sc->ops; 6022 struct iwn_calib_state *calib = &sc->calib; 6023 struct ieee80211com *ic = &sc->sc_ic; 6024 uint32_t val; 6025 int i; 6026 6027 DPRINTF(sc, IWN_DEBUG_TRACE, "->%s begin\n", __func__); 6028 6029 /* Accumulate RSSI and noise for all 3 antennas. */ 6030 for (i = 0; i < 3; i++) { 6031 calib->rssi[i] += le32toh(stats->rssi[i]) & 0xff; 6032 calib->noise[i] += le32toh(stats->noise[i]) & 0xff; 6033 } 6034 /* NB: We update differential gains only once after 20 beacons. */ 6035 if (++calib->nbeacons < 20) 6036 return; 6037 6038 /* Determine highest average RSSI. */ 6039 val = MAX(calib->rssi[0], calib->rssi[1]); 6040 val = MAX(calib->rssi[2], val); 6041 6042 /* Determine which antennas are connected. */ 6043 sc->chainmask = sc->rxchainmask; 6044 for (i = 0; i < 3; i++) 6045 if (val - calib->rssi[i] > 15 * 20) 6046 sc->chainmask &= ~(1 << i); 6047 DPRINTF(sc, IWN_DEBUG_CALIBRATE | IWN_DEBUG_XMIT, 6048 "%s: RX chains mask: theoretical=0x%x, actual=0x%x\n", 6049 __func__, sc->rxchainmask, sc->chainmask); 6050 6051 /* If none of the TX antennas are connected, keep at least one. */ 6052 if ((sc->chainmask & sc->txchainmask) == 0) 6053 sc->chainmask |= IWN_LSB(sc->txchainmask); 6054 6055 (void)ops->set_gains(sc); 6056 calib->state = IWN_CALIB_STATE_RUN; 6057 6058 #ifdef notyet 6059 /* XXX Disable RX chains with no antennas connected. */ 6060 sc->rxon->rxchain = htole16(IWN_RXCHAIN_SEL(sc->chainmask)); 6061 if (sc->sc_is_scanning) 6062 device_printf(sc->sc_dev, 6063 "%s: is_scanning set, before RXON\n", 6064 __func__); 6065 (void)iwn_cmd(sc, IWN_CMD_RXON, sc->rxon, sc->rxonsz, 1); 6066 #endif 6067 6068 /* Enable power-saving mode if requested by user. */ 6069 if (ic->ic_flags & IEEE80211_F_PMGTON) 6070 (void)iwn_set_pslevel(sc, 0, 3, 1); 6071 6072 DPRINTF(sc, IWN_DEBUG_TRACE, "->%s: end\n",__func__); 6073 6074 } 6075 6076 static int 6077 iwn4965_init_gains(struct iwn_softc *sc) 6078 { 6079 struct iwn_phy_calib_gain cmd; 6080 6081 DPRINTF(sc, IWN_DEBUG_TRACE, "->Doing %s\n", __func__); 6082 6083 memset(&cmd, 0, sizeof cmd); 6084 cmd.code = IWN4965_PHY_CALIB_DIFF_GAIN; 6085 /* Differential gains initially set to 0 for all 3 antennas. */ 6086 DPRINTF(sc, IWN_DEBUG_CALIBRATE, 6087 "%s: setting initial differential gains\n", __func__); 6088 return iwn_cmd(sc, IWN_CMD_PHY_CALIB, &cmd, sizeof cmd, 1); 6089 } 6090 6091 static int 6092 iwn5000_init_gains(struct iwn_softc *sc) 6093 { 6094 struct iwn_phy_calib cmd; 6095 6096 DPRINTF(sc, IWN_DEBUG_TRACE, "->Doing %s\n", __func__); 6097 6098 memset(&cmd, 0, sizeof cmd); 6099 cmd.code = sc->reset_noise_gain; 6100 cmd.ngroups = 1; 6101 cmd.isvalid = 1; 6102 DPRINTF(sc, IWN_DEBUG_CALIBRATE, 6103 "%s: setting initial differential gains\n", __func__); 6104 return iwn_cmd(sc, IWN_CMD_PHY_CALIB, &cmd, sizeof cmd, 1); 6105 } 6106 6107 static int 6108 iwn4965_set_gains(struct iwn_softc *sc) 6109 { 6110 struct iwn_calib_state *calib = &sc->calib; 6111 struct iwn_phy_calib_gain cmd; 6112 int i, delta, noise; 6113 6114 DPRINTF(sc, IWN_DEBUG_TRACE, "->Doing %s\n", __func__); 6115 6116 /* Get minimal noise among connected antennas. */ 6117 noise = INT_MAX; /* NB: There's at least one antenna. */ 6118 for (i = 0; i < 3; i++) 6119 if (sc->chainmask & (1 << i)) 6120 noise = MIN(calib->noise[i], noise); 6121 6122 memset(&cmd, 0, sizeof cmd); 6123 cmd.code = IWN4965_PHY_CALIB_DIFF_GAIN; 6124 /* Set differential gains for connected antennas. */ 6125 for (i = 0; i < 3; i++) { 6126 if (sc->chainmask & (1 << i)) { 6127 /* Compute attenuation (in unit of 1.5dB). */ 6128 delta = (noise - (int32_t)calib->noise[i]) / 30; 6129 /* NB: delta <= 0 */ 6130 /* Limit to [-4.5dB,0]. */ 6131 cmd.gain[i] = MIN(abs(delta), 3); 6132 if (delta < 0) 6133 cmd.gain[i] |= 1 << 2; /* sign bit */ 6134 } 6135 } 6136 DPRINTF(sc, IWN_DEBUG_CALIBRATE, 6137 "setting differential gains Ant A/B/C: %x/%x/%x (%x)\n", 6138 cmd.gain[0], cmd.gain[1], cmd.gain[2], sc->chainmask); 6139 return iwn_cmd(sc, IWN_CMD_PHY_CALIB, &cmd, sizeof cmd, 1); 6140 } 6141 6142 static int 6143 iwn5000_set_gains(struct iwn_softc *sc) 6144 { 6145 struct iwn_calib_state *calib = &sc->calib; 6146 struct iwn_phy_calib_gain cmd; 6147 int i, ant, div, delta; 6148 6149 DPRINTF(sc, IWN_DEBUG_TRACE, "->Doing %s\n", __func__); 6150 6151 /* We collected 20 beacons and !=6050 need a 1.5 factor. */ 6152 div = (sc->hw_type == IWN_HW_REV_TYPE_6050) ? 20 : 30; 6153 6154 memset(&cmd, 0, sizeof cmd); 6155 cmd.code = sc->noise_gain; 6156 cmd.ngroups = 1; 6157 cmd.isvalid = 1; 6158 /* Get first available RX antenna as referential. */ 6159 ant = IWN_LSB(sc->rxchainmask); 6160 /* Set differential gains for other antennas. */ 6161 for (i = ant + 1; i < 3; i++) { 6162 if (sc->chainmask & (1 << i)) { 6163 /* The delta is relative to antenna "ant". */ 6164 delta = ((int32_t)calib->noise[ant] - 6165 (int32_t)calib->noise[i]) / div; 6166 /* Limit to [-4.5dB,+4.5dB]. */ 6167 cmd.gain[i - 1] = MIN(abs(delta), 3); 6168 if (delta < 0) 6169 cmd.gain[i - 1] |= 1 << 2; /* sign bit */ 6170 } 6171 } 6172 DPRINTF(sc, IWN_DEBUG_CALIBRATE | IWN_DEBUG_XMIT, 6173 "setting differential gains Ant B/C: %x/%x (%x)\n", 6174 cmd.gain[0], cmd.gain[1], sc->chainmask); 6175 return iwn_cmd(sc, IWN_CMD_PHY_CALIB, &cmd, sizeof cmd, 1); 6176 } 6177 6178 /* 6179 * Tune RF RX sensitivity based on the number of false alarms detected 6180 * during the last beacon period. 6181 */ 6182 static void 6183 iwn_tune_sensitivity(struct iwn_softc *sc, const struct iwn_rx_stats *stats) 6184 { 6185 #define inc(val, inc, max) \ 6186 if ((val) < (max)) { \ 6187 if ((val) < (max) - (inc)) \ 6188 (val) += (inc); \ 6189 else \ 6190 (val) = (max); \ 6191 needs_update = 1; \ 6192 } 6193 #define dec(val, dec, min) \ 6194 if ((val) > (min)) { \ 6195 if ((val) > (min) + (dec)) \ 6196 (val) -= (dec); \ 6197 else \ 6198 (val) = (min); \ 6199 needs_update = 1; \ 6200 } 6201 6202 const struct iwn_sensitivity_limits *limits = sc->limits; 6203 struct iwn_calib_state *calib = &sc->calib; 6204 uint32_t val, rxena, fa; 6205 uint32_t energy[3], energy_min; 6206 uint8_t noise[3], noise_ref; 6207 int i, needs_update = 0; 6208 6209 DPRINTF(sc, IWN_DEBUG_TRACE, "->%s begin\n", __func__); 6210 6211 /* Check that we've been enabled long enough. */ 6212 if ((rxena = le32toh(stats->general.load)) == 0){ 6213 DPRINTF(sc, IWN_DEBUG_TRACE, "->%s end not so long\n", __func__); 6214 return; 6215 } 6216 6217 /* Compute number of false alarms since last call for OFDM. */ 6218 fa = le32toh(stats->ofdm.bad_plcp) - calib->bad_plcp_ofdm; 6219 fa += le32toh(stats->ofdm.fa) - calib->fa_ofdm; 6220 fa *= 200 * IEEE80211_DUR_TU; /* 200TU */ 6221 6222 if (fa > 50 * rxena) { 6223 /* High false alarm count, decrease sensitivity. */ 6224 DPRINTF(sc, IWN_DEBUG_CALIBRATE, 6225 "%s: OFDM high false alarm count: %u\n", __func__, fa); 6226 inc(calib->ofdm_x1, 1, limits->max_ofdm_x1); 6227 inc(calib->ofdm_mrc_x1, 1, limits->max_ofdm_mrc_x1); 6228 inc(calib->ofdm_x4, 1, limits->max_ofdm_x4); 6229 inc(calib->ofdm_mrc_x4, 1, limits->max_ofdm_mrc_x4); 6230 6231 } else if (fa < 5 * rxena) { 6232 /* Low false alarm count, increase sensitivity. */ 6233 DPRINTF(sc, IWN_DEBUG_CALIBRATE, 6234 "%s: OFDM low false alarm count: %u\n", __func__, fa); 6235 dec(calib->ofdm_x1, 1, limits->min_ofdm_x1); 6236 dec(calib->ofdm_mrc_x1, 1, limits->min_ofdm_mrc_x1); 6237 dec(calib->ofdm_x4, 1, limits->min_ofdm_x4); 6238 dec(calib->ofdm_mrc_x4, 1, limits->min_ofdm_mrc_x4); 6239 } 6240 6241 /* Compute maximum noise among 3 receivers. */ 6242 for (i = 0; i < 3; i++) 6243 noise[i] = (le32toh(stats->general.noise[i]) >> 8) & 0xff; 6244 val = MAX(noise[0], noise[1]); 6245 val = MAX(noise[2], val); 6246 /* Insert it into our samples table. */ 6247 calib->noise_samples[calib->cur_noise_sample] = val; 6248 calib->cur_noise_sample = (calib->cur_noise_sample + 1) % 20; 6249 6250 /* Compute maximum noise among last 20 samples. */ 6251 noise_ref = calib->noise_samples[0]; 6252 for (i = 1; i < 20; i++) 6253 noise_ref = MAX(noise_ref, calib->noise_samples[i]); 6254 6255 /* Compute maximum energy among 3 receivers. */ 6256 for (i = 0; i < 3; i++) 6257 energy[i] = le32toh(stats->general.energy[i]); 6258 val = MIN(energy[0], energy[1]); 6259 val = MIN(energy[2], val); 6260 /* Insert it into our samples table. */ 6261 calib->energy_samples[calib->cur_energy_sample] = val; 6262 calib->cur_energy_sample = (calib->cur_energy_sample + 1) % 10; 6263 6264 /* Compute minimum energy among last 10 samples. */ 6265 energy_min = calib->energy_samples[0]; 6266 for (i = 1; i < 10; i++) 6267 energy_min = MAX(energy_min, calib->energy_samples[i]); 6268 energy_min += 6; 6269 6270 /* Compute number of false alarms since last call for CCK. */ 6271 fa = le32toh(stats->cck.bad_plcp) - calib->bad_plcp_cck; 6272 fa += le32toh(stats->cck.fa) - calib->fa_cck; 6273 fa *= 200 * IEEE80211_DUR_TU; /* 200TU */ 6274 6275 if (fa > 50 * rxena) { 6276 /* High false alarm count, decrease sensitivity. */ 6277 DPRINTF(sc, IWN_DEBUG_CALIBRATE, 6278 "%s: CCK high false alarm count: %u\n", __func__, fa); 6279 calib->cck_state = IWN_CCK_STATE_HIFA; 6280 calib->low_fa = 0; 6281 6282 if (calib->cck_x4 > 160) { 6283 calib->noise_ref = noise_ref; 6284 if (calib->energy_cck > 2) 6285 dec(calib->energy_cck, 2, energy_min); 6286 } 6287 if (calib->cck_x4 < 160) { 6288 calib->cck_x4 = 161; 6289 needs_update = 1; 6290 } else 6291 inc(calib->cck_x4, 3, limits->max_cck_x4); 6292 6293 inc(calib->cck_mrc_x4, 3, limits->max_cck_mrc_x4); 6294 6295 } else if (fa < 5 * rxena) { 6296 /* Low false alarm count, increase sensitivity. */ 6297 DPRINTF(sc, IWN_DEBUG_CALIBRATE, 6298 "%s: CCK low false alarm count: %u\n", __func__, fa); 6299 calib->cck_state = IWN_CCK_STATE_LOFA; 6300 calib->low_fa++; 6301 6302 if (calib->cck_state != IWN_CCK_STATE_INIT && 6303 (((int32_t)calib->noise_ref - (int32_t)noise_ref) > 2 || 6304 calib->low_fa > 100)) { 6305 inc(calib->energy_cck, 2, limits->min_energy_cck); 6306 dec(calib->cck_x4, 3, limits->min_cck_x4); 6307 dec(calib->cck_mrc_x4, 3, limits->min_cck_mrc_x4); 6308 } 6309 } else { 6310 /* Not worth to increase or decrease sensitivity. */ 6311 DPRINTF(sc, IWN_DEBUG_CALIBRATE, 6312 "%s: CCK normal false alarm count: %u\n", __func__, fa); 6313 calib->low_fa = 0; 6314 calib->noise_ref = noise_ref; 6315 6316 if (calib->cck_state == IWN_CCK_STATE_HIFA) { 6317 /* Previous interval had many false alarms. */ 6318 dec(calib->energy_cck, 8, energy_min); 6319 } 6320 calib->cck_state = IWN_CCK_STATE_INIT; 6321 } 6322 6323 if (needs_update) 6324 (void)iwn_send_sensitivity(sc); 6325 6326 DPRINTF(sc, IWN_DEBUG_TRACE, "->%s: end\n",__func__); 6327 6328 #undef dec 6329 #undef inc 6330 } 6331 6332 static int 6333 iwn_send_sensitivity(struct iwn_softc *sc) 6334 { 6335 struct iwn_calib_state *calib = &sc->calib; 6336 struct iwn_enhanced_sensitivity_cmd cmd; 6337 int len; 6338 6339 memset(&cmd, 0, sizeof cmd); 6340 len = sizeof (struct iwn_sensitivity_cmd); 6341 cmd.which = IWN_SENSITIVITY_WORKTBL; 6342 /* OFDM modulation. */ 6343 cmd.corr_ofdm_x1 = htole16(calib->ofdm_x1); 6344 cmd.corr_ofdm_mrc_x1 = htole16(calib->ofdm_mrc_x1); 6345 cmd.corr_ofdm_x4 = htole16(calib->ofdm_x4); 6346 cmd.corr_ofdm_mrc_x4 = htole16(calib->ofdm_mrc_x4); 6347 cmd.energy_ofdm = htole16(sc->limits->energy_ofdm); 6348 cmd.energy_ofdm_th = htole16(62); 6349 /* CCK modulation. */ 6350 cmd.corr_cck_x4 = htole16(calib->cck_x4); 6351 cmd.corr_cck_mrc_x4 = htole16(calib->cck_mrc_x4); 6352 cmd.energy_cck = htole16(calib->energy_cck); 6353 /* Barker modulation: use default values. */ 6354 cmd.corr_barker = htole16(190); 6355 cmd.corr_barker_mrc = htole16(sc->limits->barker_mrc); 6356 6357 DPRINTF(sc, IWN_DEBUG_CALIBRATE, 6358 "%s: set sensitivity %d/%d/%d/%d/%d/%d/%d\n", __func__, 6359 calib->ofdm_x1, calib->ofdm_mrc_x1, calib->ofdm_x4, 6360 calib->ofdm_mrc_x4, calib->cck_x4, 6361 calib->cck_mrc_x4, calib->energy_cck); 6362 6363 if (!(sc->sc_flags & IWN_FLAG_ENH_SENS)) 6364 goto send; 6365 /* Enhanced sensitivity settings. */ 6366 len = sizeof (struct iwn_enhanced_sensitivity_cmd); 6367 cmd.ofdm_det_slope_mrc = htole16(668); 6368 cmd.ofdm_det_icept_mrc = htole16(4); 6369 cmd.ofdm_det_slope = htole16(486); 6370 cmd.ofdm_det_icept = htole16(37); 6371 cmd.cck_det_slope_mrc = htole16(853); 6372 cmd.cck_det_icept_mrc = htole16(4); 6373 cmd.cck_det_slope = htole16(476); 6374 cmd.cck_det_icept = htole16(99); 6375 send: 6376 return iwn_cmd(sc, IWN_CMD_SET_SENSITIVITY, &cmd, len, 1); 6377 } 6378 6379 /* 6380 * Look at the increase of PLCP errors over time; if it exceeds 6381 * a programmed threshold then trigger an RF retune. 6382 */ 6383 static void 6384 iwn_check_rx_recovery(struct iwn_softc *sc, struct iwn_stats *rs) 6385 { 6386 int32_t delta_ofdm, delta_ht, delta_cck; 6387 struct iwn_calib_state *calib = &sc->calib; 6388 int delta_ticks, cur_ticks; 6389 int delta_msec; 6390 int thresh; 6391 6392 /* 6393 * Calculate the difference between the current and 6394 * previous statistics. 6395 */ 6396 delta_cck = le32toh(rs->rx.cck.bad_plcp) - calib->bad_plcp_cck; 6397 delta_ofdm = le32toh(rs->rx.ofdm.bad_plcp) - calib->bad_plcp_ofdm; 6398 delta_ht = le32toh(rs->rx.ht.bad_plcp) - calib->bad_plcp_ht; 6399 6400 /* 6401 * Calculate the delta in time between successive statistics 6402 * messages. Yes, it can roll over; so we make sure that 6403 * this doesn't happen. 6404 * 6405 * XXX go figure out what to do about rollover 6406 * XXX go figure out what to do if ticks rolls over to -ve instead! 6407 * XXX go stab signed integer overflow undefined-ness in the face. 6408 */ 6409 cur_ticks = ticks; 6410 delta_ticks = cur_ticks - sc->last_calib_ticks; 6411 6412 /* 6413 * If any are negative, then the firmware likely reset; so just 6414 * bail. We'll pick this up next time. 6415 */ 6416 if (delta_cck < 0 || delta_ofdm < 0 || delta_ht < 0 || delta_ticks < 0) 6417 return; 6418 6419 /* 6420 * delta_ticks is in ticks; we need to convert it up to milliseconds 6421 * so we can do some useful math with it. 6422 */ 6423 delta_msec = ticks_to_msecs(delta_ticks); 6424 6425 /* 6426 * Calculate what our threshold is given the current delta_msec. 6427 */ 6428 thresh = sc->base_params->plcp_err_threshold * delta_msec; 6429 6430 DPRINTF(sc, IWN_DEBUG_STATE, 6431 "%s: time delta: %d; cck=%d, ofdm=%d, ht=%d, total=%d, thresh=%d\n", 6432 __func__, 6433 delta_msec, 6434 delta_cck, 6435 delta_ofdm, 6436 delta_ht, 6437 (delta_msec + delta_cck + delta_ofdm + delta_ht), 6438 thresh); 6439 6440 /* 6441 * If we need a retune, then schedule a single channel scan 6442 * to a channel that isn't the currently active one! 6443 * 6444 * The math from linux iwlwifi: 6445 * 6446 * if ((delta * 100 / msecs) > threshold) 6447 */ 6448 if (thresh > 0 && (delta_cck + delta_ofdm + delta_ht) * 100 > thresh) { 6449 DPRINTF(sc, IWN_DEBUG_ANY, 6450 "%s: PLCP error threshold raw (%d) comparison (%d) " 6451 "over limit (%d); retune!\n", 6452 __func__, 6453 (delta_cck + delta_ofdm + delta_ht), 6454 (delta_cck + delta_ofdm + delta_ht) * 100, 6455 thresh); 6456 } 6457 } 6458 6459 /* 6460 * Set STA mode power saving level (between 0 and 5). 6461 * Level 0 is CAM (Continuously Aware Mode), 5 is for maximum power saving. 6462 */ 6463 static int 6464 iwn_set_pslevel(struct iwn_softc *sc, int dtim, int level, int async) 6465 { 6466 struct iwn_pmgt_cmd cmd; 6467 const struct iwn_pmgt *pmgt; 6468 uint32_t max, skip_dtim; 6469 uint32_t reg; 6470 int i; 6471 6472 DPRINTF(sc, IWN_DEBUG_PWRSAVE, 6473 "%s: dtim=%d, level=%d, async=%d\n", 6474 __func__, 6475 dtim, 6476 level, 6477 async); 6478 6479 /* Select which PS parameters to use. */ 6480 if (dtim <= 2) 6481 pmgt = &iwn_pmgt[0][level]; 6482 else if (dtim <= 10) 6483 pmgt = &iwn_pmgt[1][level]; 6484 else 6485 pmgt = &iwn_pmgt[2][level]; 6486 6487 memset(&cmd, 0, sizeof cmd); 6488 if (level != 0) /* not CAM */ 6489 cmd.flags |= htole16(IWN_PS_ALLOW_SLEEP); 6490 if (level == 5) 6491 cmd.flags |= htole16(IWN_PS_FAST_PD); 6492 /* Retrieve PCIe Active State Power Management (ASPM). */ 6493 reg = pci_read_config(sc->sc_dev, sc->sc_cap_off + PCIER_LINK_CTL, 4); 6494 if (!(reg & PCIEM_LINK_CTL_ASPMC_L0S)) /* L0s Entry disabled. */ 6495 cmd.flags |= htole16(IWN_PS_PCI_PMGT); 6496 cmd.rxtimeout = htole32(pmgt->rxtimeout * 1024); 6497 cmd.txtimeout = htole32(pmgt->txtimeout * 1024); 6498 6499 if (dtim == 0) { 6500 dtim = 1; 6501 skip_dtim = 0; 6502 } else 6503 skip_dtim = pmgt->skip_dtim; 6504 if (skip_dtim != 0) { 6505 cmd.flags |= htole16(IWN_PS_SLEEP_OVER_DTIM); 6506 max = pmgt->intval[4]; 6507 if (max == (uint32_t)-1) 6508 max = dtim * (skip_dtim + 1); 6509 else if (max > dtim) 6510 max = rounddown(max, dtim); 6511 } else 6512 max = dtim; 6513 for (i = 0; i < 5; i++) 6514 cmd.intval[i] = htole32(MIN(max, pmgt->intval[i])); 6515 6516 DPRINTF(sc, IWN_DEBUG_RESET, "setting power saving level to %d\n", 6517 level); 6518 return iwn_cmd(sc, IWN_CMD_SET_POWER_MODE, &cmd, sizeof cmd, async); 6519 } 6520 6521 static int 6522 iwn_send_btcoex(struct iwn_softc *sc) 6523 { 6524 struct iwn_bluetooth cmd; 6525 6526 memset(&cmd, 0, sizeof cmd); 6527 cmd.flags = IWN_BT_COEX_CHAN_ANN | IWN_BT_COEX_BT_PRIO; 6528 cmd.lead_time = IWN_BT_LEAD_TIME_DEF; 6529 cmd.max_kill = IWN_BT_MAX_KILL_DEF; 6530 DPRINTF(sc, IWN_DEBUG_RESET, "%s: configuring bluetooth coexistence\n", 6531 __func__); 6532 return iwn_cmd(sc, IWN_CMD_BT_COEX, &cmd, sizeof(cmd), 0); 6533 } 6534 6535 static int 6536 iwn_send_advanced_btcoex(struct iwn_softc *sc) 6537 { 6538 static const uint32_t btcoex_3wire[12] = { 6539 0xaaaaaaaa, 0xaaaaaaaa, 0xaeaaaaaa, 0xaaaaaaaa, 6540 0xcc00ff28, 0x0000aaaa, 0xcc00aaaa, 0x0000aaaa, 6541 0xc0004000, 0x00004000, 0xf0005000, 0xf0005000, 6542 }; 6543 struct iwn6000_btcoex_config btconfig; 6544 struct iwn2000_btcoex_config btconfig2k; 6545 struct iwn_btcoex_priotable btprio; 6546 struct iwn_btcoex_prot btprot; 6547 int error, i; 6548 uint8_t flags; 6549 6550 memset(&btconfig, 0, sizeof btconfig); 6551 memset(&btconfig2k, 0, sizeof btconfig2k); 6552 6553 flags = IWN_BT_FLAG_COEX6000_MODE_3W << 6554 IWN_BT_FLAG_COEX6000_MODE_SHIFT; // Done as is in linux kernel 3.2 6555 6556 if (sc->base_params->bt_sco_disable) 6557 flags &= ~IWN_BT_FLAG_SYNC_2_BT_DISABLE; 6558 else 6559 flags |= IWN_BT_FLAG_SYNC_2_BT_DISABLE; 6560 6561 flags |= IWN_BT_FLAG_COEX6000_CHAN_INHIBITION; 6562 6563 /* Default flags result is 145 as old value */ 6564 6565 /* 6566 * Flags value has to be review. Values must change if we 6567 * which to disable it 6568 */ 6569 if (sc->base_params->bt_session_2) { 6570 btconfig2k.flags = flags; 6571 btconfig2k.max_kill = 5; 6572 btconfig2k.bt3_t7_timer = 1; 6573 btconfig2k.kill_ack = htole32(0xffff0000); 6574 btconfig2k.kill_cts = htole32(0xffff0000); 6575 btconfig2k.sample_time = 2; 6576 btconfig2k.bt3_t2_timer = 0xc; 6577 6578 for (i = 0; i < 12; i++) 6579 btconfig2k.lookup_table[i] = htole32(btcoex_3wire[i]); 6580 btconfig2k.valid = htole16(0xff); 6581 btconfig2k.prio_boost = htole32(0xf0); 6582 DPRINTF(sc, IWN_DEBUG_RESET, 6583 "%s: configuring advanced bluetooth coexistence" 6584 " session 2, flags : 0x%x\n", 6585 __func__, 6586 flags); 6587 error = iwn_cmd(sc, IWN_CMD_BT_COEX, &btconfig2k, 6588 sizeof(btconfig2k), 1); 6589 } else { 6590 btconfig.flags = flags; 6591 btconfig.max_kill = 5; 6592 btconfig.bt3_t7_timer = 1; 6593 btconfig.kill_ack = htole32(0xffff0000); 6594 btconfig.kill_cts = htole32(0xffff0000); 6595 btconfig.sample_time = 2; 6596 btconfig.bt3_t2_timer = 0xc; 6597 6598 for (i = 0; i < 12; i++) 6599 btconfig.lookup_table[i] = htole32(btcoex_3wire[i]); 6600 btconfig.valid = htole16(0xff); 6601 btconfig.prio_boost = 0xf0; 6602 DPRINTF(sc, IWN_DEBUG_RESET, 6603 "%s: configuring advanced bluetooth coexistence," 6604 " flags : 0x%x\n", 6605 __func__, 6606 flags); 6607 error = iwn_cmd(sc, IWN_CMD_BT_COEX, &btconfig, 6608 sizeof(btconfig), 1); 6609 } 6610 6611 if (error != 0) 6612 return error; 6613 6614 memset(&btprio, 0, sizeof btprio); 6615 btprio.calib_init1 = 0x6; 6616 btprio.calib_init2 = 0x7; 6617 btprio.calib_periodic_low1 = 0x2; 6618 btprio.calib_periodic_low2 = 0x3; 6619 btprio.calib_periodic_high1 = 0x4; 6620 btprio.calib_periodic_high2 = 0x5; 6621 btprio.dtim = 0x6; 6622 btprio.scan52 = 0x8; 6623 btprio.scan24 = 0xa; 6624 error = iwn_cmd(sc, IWN_CMD_BT_COEX_PRIOTABLE, &btprio, sizeof(btprio), 6625 1); 6626 if (error != 0) 6627 return error; 6628 6629 /* Force BT state machine change. */ 6630 memset(&btprot, 0, sizeof btprot); 6631 btprot.open = 1; 6632 btprot.type = 1; 6633 error = iwn_cmd(sc, IWN_CMD_BT_COEX_PROT, &btprot, sizeof(btprot), 1); 6634 if (error != 0) 6635 return error; 6636 btprot.open = 0; 6637 return iwn_cmd(sc, IWN_CMD_BT_COEX_PROT, &btprot, sizeof(btprot), 1); 6638 } 6639 6640 static int 6641 iwn5000_runtime_calib(struct iwn_softc *sc) 6642 { 6643 struct iwn5000_calib_config cmd; 6644 6645 memset(&cmd, 0, sizeof cmd); 6646 cmd.ucode.once.enable = 0xffffffff; 6647 cmd.ucode.once.start = IWN5000_CALIB_DC; 6648 DPRINTF(sc, IWN_DEBUG_CALIBRATE, 6649 "%s: configuring runtime calibration\n", __func__); 6650 return iwn_cmd(sc, IWN5000_CMD_CALIB_CONFIG, &cmd, sizeof(cmd), 0); 6651 } 6652 6653 static uint32_t 6654 iwn_get_rxon_ht_flags(struct iwn_softc *sc, struct ieee80211vap *vap, 6655 struct ieee80211_channel *c) 6656 { 6657 uint32_t htflags = 0; 6658 6659 if (! IEEE80211_IS_CHAN_HT(c)) 6660 return (0); 6661 6662 htflags |= IWN_RXON_HT_PROTMODE(vap->iv_curhtprotmode); 6663 6664 if (IEEE80211_IS_CHAN_HT40(c)) { 6665 switch (vap->iv_curhtprotmode) { 6666 case IEEE80211_HTINFO_OPMODE_HT20PR: 6667 htflags |= IWN_RXON_HT_MODEPURE40; 6668 break; 6669 default: 6670 htflags |= IWN_RXON_HT_MODEMIXED; 6671 break; 6672 } 6673 } 6674 if (IEEE80211_IS_CHAN_HT40D(c)) 6675 htflags |= IWN_RXON_HT_HT40MINUS; 6676 6677 return (htflags); 6678 } 6679 6680 static int 6681 iwn_check_bss_filter(struct iwn_softc *sc) 6682 { 6683 return ((sc->rxon->filter & htole32(IWN_FILTER_BSS)) != 0); 6684 } 6685 6686 static int 6687 iwn4965_rxon_assoc(struct iwn_softc *sc, int async) 6688 { 6689 struct iwn4965_rxon_assoc cmd; 6690 struct iwn_rxon *rxon = sc->rxon; 6691 6692 cmd.flags = rxon->flags; 6693 cmd.filter = rxon->filter; 6694 cmd.ofdm_mask = rxon->ofdm_mask; 6695 cmd.cck_mask = rxon->cck_mask; 6696 cmd.ht_single_mask = rxon->ht_single_mask; 6697 cmd.ht_dual_mask = rxon->ht_dual_mask; 6698 cmd.rxchain = rxon->rxchain; 6699 cmd.reserved = 0; 6700 6701 return (iwn_cmd(sc, IWN_CMD_RXON_ASSOC, &cmd, sizeof(cmd), async)); 6702 } 6703 6704 static int 6705 iwn5000_rxon_assoc(struct iwn_softc *sc, int async) 6706 { 6707 struct iwn5000_rxon_assoc cmd; 6708 struct iwn_rxon *rxon = sc->rxon; 6709 6710 cmd.flags = rxon->flags; 6711 cmd.filter = rxon->filter; 6712 cmd.ofdm_mask = rxon->ofdm_mask; 6713 cmd.cck_mask = rxon->cck_mask; 6714 cmd.reserved1 = 0; 6715 cmd.ht_single_mask = rxon->ht_single_mask; 6716 cmd.ht_dual_mask = rxon->ht_dual_mask; 6717 cmd.ht_triple_mask = rxon->ht_triple_mask; 6718 cmd.reserved2 = 0; 6719 cmd.rxchain = rxon->rxchain; 6720 cmd.acquisition = rxon->acquisition; 6721 cmd.reserved3 = 0; 6722 6723 return (iwn_cmd(sc, IWN_CMD_RXON_ASSOC, &cmd, sizeof(cmd), async)); 6724 } 6725 6726 static int 6727 iwn_send_rxon(struct iwn_softc *sc, int assoc, int async) 6728 { 6729 struct iwn_ops *ops = &sc->ops; 6730 int error; 6731 6732 IWN_LOCK_ASSERT(sc); 6733 6734 if (assoc && iwn_check_bss_filter(sc) != 0) { 6735 error = ops->rxon_assoc(sc, async); 6736 if (error != 0) { 6737 device_printf(sc->sc_dev, 6738 "%s: RXON_ASSOC command failed, error %d\n", 6739 __func__, error); 6740 return (error); 6741 } 6742 } else { 6743 if (sc->sc_is_scanning) 6744 device_printf(sc->sc_dev, 6745 "%s: is_scanning set, before RXON\n", 6746 __func__); 6747 6748 error = iwn_cmd(sc, IWN_CMD_RXON, sc->rxon, sc->rxonsz, async); 6749 if (error != 0) { 6750 device_printf(sc->sc_dev, 6751 "%s: RXON command failed, error %d\n", 6752 __func__, error); 6753 return (error); 6754 } 6755 6756 /* 6757 * Reconfiguring RXON clears the firmware nodes table so 6758 * we must add the broadcast node again. 6759 */ 6760 if (iwn_check_bss_filter(sc) == 0 && 6761 (error = iwn_add_broadcast_node(sc, async)) != 0) { 6762 device_printf(sc->sc_dev, 6763 "%s: could not add broadcast node, error %d\n", 6764 __func__, error); 6765 return (error); 6766 } 6767 } 6768 6769 /* Configuration has changed, set TX power accordingly. */ 6770 if ((error = ops->set_txpower(sc, async)) != 0) { 6771 device_printf(sc->sc_dev, 6772 "%s: could not set TX power, error %d\n", 6773 __func__, error); 6774 return (error); 6775 } 6776 6777 return (0); 6778 } 6779 6780 static int 6781 iwn_config(struct iwn_softc *sc) 6782 { 6783 struct ieee80211com *ic = &sc->sc_ic; 6784 struct ieee80211vap *vap = TAILQ_FIRST(&ic->ic_vaps); 6785 const uint8_t *macaddr; 6786 uint32_t txmask; 6787 uint16_t rxchain; 6788 int error; 6789 6790 DPRINTF(sc, IWN_DEBUG_TRACE, "->%s begin\n", __func__); 6791 6792 if ((sc->base_params->calib_need & IWN_FLG_NEED_PHY_CALIB_TEMP_OFFSET) 6793 && (sc->base_params->calib_need & IWN_FLG_NEED_PHY_CALIB_TEMP_OFFSETv2)) { 6794 device_printf(sc->sc_dev,"%s: temp_offset and temp_offsetv2 are" 6795 " exclusive each together. Review NIC config file. Conf" 6796 " : 0x%08x Flags : 0x%08x \n", __func__, 6797 sc->base_params->calib_need, 6798 (IWN_FLG_NEED_PHY_CALIB_TEMP_OFFSET | 6799 IWN_FLG_NEED_PHY_CALIB_TEMP_OFFSETv2)); 6800 return (EINVAL); 6801 } 6802 6803 /* Compute temperature calib if needed. Will be send by send calib */ 6804 if (sc->base_params->calib_need & IWN_FLG_NEED_PHY_CALIB_TEMP_OFFSET) { 6805 error = iwn5000_temp_offset_calib(sc); 6806 if (error != 0) { 6807 device_printf(sc->sc_dev, 6808 "%s: could not set temperature offset\n", __func__); 6809 return (error); 6810 } 6811 } else if (sc->base_params->calib_need & IWN_FLG_NEED_PHY_CALIB_TEMP_OFFSETv2) { 6812 error = iwn5000_temp_offset_calibv2(sc); 6813 if (error != 0) { 6814 device_printf(sc->sc_dev, 6815 "%s: could not compute temperature offset v2\n", 6816 __func__); 6817 return (error); 6818 } 6819 } 6820 6821 if (sc->hw_type == IWN_HW_REV_TYPE_6050) { 6822 /* Configure runtime DC calibration. */ 6823 error = iwn5000_runtime_calib(sc); 6824 if (error != 0) { 6825 device_printf(sc->sc_dev, 6826 "%s: could not configure runtime calibration\n", 6827 __func__); 6828 return error; 6829 } 6830 } 6831 6832 /* Configure valid TX chains for >=5000 Series. */ 6833 if (sc->hw_type != IWN_HW_REV_TYPE_4965 && 6834 IWN_UCODE_API(sc->ucode_rev) > 1) { 6835 txmask = htole32(sc->txchainmask); 6836 DPRINTF(sc, IWN_DEBUG_RESET | IWN_DEBUG_XMIT, 6837 "%s: configuring valid TX chains 0x%x\n", __func__, txmask); 6838 error = iwn_cmd(sc, IWN5000_CMD_TX_ANT_CONFIG, &txmask, 6839 sizeof txmask, 0); 6840 if (error != 0) { 6841 device_printf(sc->sc_dev, 6842 "%s: could not configure valid TX chains, " 6843 "error %d\n", __func__, error); 6844 return error; 6845 } 6846 } 6847 6848 /* Configure bluetooth coexistence. */ 6849 error = 0; 6850 6851 /* Configure bluetooth coexistence if needed. */ 6852 if (sc->base_params->bt_mode == IWN_BT_ADVANCED) 6853 error = iwn_send_advanced_btcoex(sc); 6854 if (sc->base_params->bt_mode == IWN_BT_SIMPLE) 6855 error = iwn_send_btcoex(sc); 6856 6857 if (error != 0) { 6858 device_printf(sc->sc_dev, 6859 "%s: could not configure bluetooth coexistence, error %d\n", 6860 __func__, error); 6861 return error; 6862 } 6863 6864 /* Set mode, channel, RX filter and enable RX. */ 6865 sc->rxon = &sc->rx_on[IWN_RXON_BSS_CTX]; 6866 memset(sc->rxon, 0, sizeof (struct iwn_rxon)); 6867 macaddr = vap ? vap->iv_myaddr : ic->ic_macaddr; 6868 IEEE80211_ADDR_COPY(sc->rxon->myaddr, macaddr); 6869 IEEE80211_ADDR_COPY(sc->rxon->wlap, macaddr); 6870 sc->rxon->chan = ieee80211_chan2ieee(ic, ic->ic_curchan); 6871 sc->rxon->flags = htole32(IWN_RXON_TSF | IWN_RXON_CTS_TO_SELF); 6872 if (IEEE80211_IS_CHAN_2GHZ(ic->ic_curchan)) 6873 sc->rxon->flags |= htole32(IWN_RXON_AUTO | IWN_RXON_24GHZ); 6874 6875 sc->rxon->filter = htole32(IWN_FILTER_MULTICAST); 6876 switch (ic->ic_opmode) { 6877 case IEEE80211_M_STA: 6878 sc->rxon->mode = IWN_MODE_STA; 6879 break; 6880 case IEEE80211_M_MONITOR: 6881 sc->rxon->mode = IWN_MODE_MONITOR; 6882 break; 6883 default: 6884 /* Should not get there. */ 6885 break; 6886 } 6887 iwn_set_promisc(sc); 6888 sc->rxon->cck_mask = 0x0f; /* not yet negotiated */ 6889 sc->rxon->ofdm_mask = 0xff; /* not yet negotiated */ 6890 sc->rxon->ht_single_mask = 0xff; 6891 sc->rxon->ht_dual_mask = 0xff; 6892 sc->rxon->ht_triple_mask = 0xff; 6893 /* 6894 * In active association mode, ensure that 6895 * all the receive chains are enabled. 6896 * 6897 * Since we're not yet doing SMPS, don't allow the 6898 * number of idle RX chains to be less than the active 6899 * number. 6900 */ 6901 rxchain = 6902 IWN_RXCHAIN_VALID(sc->rxchainmask) | 6903 IWN_RXCHAIN_MIMO_COUNT(sc->nrxchains) | 6904 IWN_RXCHAIN_IDLE_COUNT(sc->nrxchains); 6905 sc->rxon->rxchain = htole16(rxchain); 6906 DPRINTF(sc, IWN_DEBUG_RESET | IWN_DEBUG_XMIT, 6907 "%s: rxchainmask=0x%x, nrxchains=%d\n", 6908 __func__, 6909 sc->rxchainmask, 6910 sc->nrxchains); 6911 6912 sc->rxon->flags |= htole32(iwn_get_rxon_ht_flags(sc, vap, ic->ic_curchan)); 6913 6914 DPRINTF(sc, IWN_DEBUG_RESET, 6915 "%s: setting configuration; flags=0x%08x\n", 6916 __func__, le32toh(sc->rxon->flags)); 6917 if ((error = iwn_send_rxon(sc, 0, 0)) != 0) { 6918 device_printf(sc->sc_dev, "%s: could not send RXON\n", 6919 __func__); 6920 return error; 6921 } 6922 6923 if ((error = iwn_set_critical_temp(sc)) != 0) { 6924 device_printf(sc->sc_dev, 6925 "%s: could not set critical temperature\n", __func__); 6926 return error; 6927 } 6928 6929 /* Set power saving level to CAM during initialization. */ 6930 if ((error = iwn_set_pslevel(sc, 0, 0, 0)) != 0) { 6931 device_printf(sc->sc_dev, 6932 "%s: could not set power saving level\n", __func__); 6933 return error; 6934 } 6935 6936 DPRINTF(sc, IWN_DEBUG_TRACE, "->%s: end\n",__func__); 6937 6938 return 0; 6939 } 6940 6941 static uint16_t 6942 iwn_get_active_dwell_time(struct iwn_softc *sc, 6943 struct ieee80211_channel *c, uint8_t n_probes) 6944 { 6945 /* No channel? Default to 2GHz settings */ 6946 if (c == NULL || IEEE80211_IS_CHAN_2GHZ(c)) { 6947 return (IWN_ACTIVE_DWELL_TIME_2GHZ + 6948 IWN_ACTIVE_DWELL_FACTOR_2GHZ * (n_probes + 1)); 6949 } 6950 6951 /* 5GHz dwell time */ 6952 return (IWN_ACTIVE_DWELL_TIME_5GHZ + 6953 IWN_ACTIVE_DWELL_FACTOR_5GHZ * (n_probes + 1)); 6954 } 6955 6956 /* 6957 * Limit the total dwell time to 85% of the beacon interval. 6958 * 6959 * Returns the dwell time in milliseconds. 6960 */ 6961 static uint16_t 6962 iwn_limit_dwell(struct iwn_softc *sc, uint16_t dwell_time) 6963 { 6964 struct ieee80211com *ic = &sc->sc_ic; 6965 struct ieee80211vap *vap = NULL; 6966 int bintval = 0; 6967 6968 /* bintval is in TU (1.024mS) */ 6969 if (! TAILQ_EMPTY(&ic->ic_vaps)) { 6970 vap = TAILQ_FIRST(&ic->ic_vaps); 6971 bintval = vap->iv_bss->ni_intval; 6972 } 6973 6974 /* 6975 * If it's non-zero, we should calculate the minimum of 6976 * it and the DWELL_BASE. 6977 * 6978 * XXX Yes, the math should take into account that bintval 6979 * is 1.024mS, not 1mS.. 6980 */ 6981 if (bintval > 0) { 6982 DPRINTF(sc, IWN_DEBUG_SCAN, 6983 "%s: bintval=%d\n", 6984 __func__, 6985 bintval); 6986 return (MIN(IWN_PASSIVE_DWELL_BASE, ((bintval * 85) / 100))); 6987 } 6988 6989 /* No association context? Default */ 6990 return (IWN_PASSIVE_DWELL_BASE); 6991 } 6992 6993 static uint16_t 6994 iwn_get_passive_dwell_time(struct iwn_softc *sc, struct ieee80211_channel *c) 6995 { 6996 uint16_t passive; 6997 6998 if (c == NULL || IEEE80211_IS_CHAN_2GHZ(c)) { 6999 passive = IWN_PASSIVE_DWELL_BASE + IWN_PASSIVE_DWELL_TIME_2GHZ; 7000 } else { 7001 passive = IWN_PASSIVE_DWELL_BASE + IWN_PASSIVE_DWELL_TIME_5GHZ; 7002 } 7003 7004 /* Clamp to the beacon interval if we're associated */ 7005 return (iwn_limit_dwell(sc, passive)); 7006 } 7007 7008 static int 7009 iwn_scan(struct iwn_softc *sc, struct ieee80211vap *vap, 7010 struct ieee80211_scan_state *ss, struct ieee80211_channel *c) 7011 { 7012 struct ieee80211com *ic = &sc->sc_ic; 7013 struct ieee80211_node *ni = vap->iv_bss; 7014 struct iwn_scan_hdr *hdr; 7015 struct iwn_cmd_data *tx; 7016 struct iwn_scan_essid *essid; 7017 struct iwn_scan_chan *chan; 7018 struct ieee80211_frame *wh; 7019 struct ieee80211_rateset *rs; 7020 uint8_t *buf, *frm; 7021 uint16_t rxchain; 7022 uint8_t txant; 7023 int buflen, error; 7024 int is_active; 7025 uint16_t dwell_active, dwell_passive; 7026 uint32_t scan_service_time; 7027 7028 DPRINTF(sc, IWN_DEBUG_TRACE, "->%s begin\n", __func__); 7029 7030 /* 7031 * We are absolutely not allowed to send a scan command when another 7032 * scan command is pending. 7033 */ 7034 if (sc->sc_is_scanning) { 7035 device_printf(sc->sc_dev, "%s: called whilst scanning!\n", 7036 __func__); 7037 return (EAGAIN); 7038 } 7039 7040 /* Assign the scan channel */ 7041 c = ic->ic_curchan; 7042 7043 sc->rxon = &sc->rx_on[IWN_RXON_BSS_CTX]; 7044 buf = malloc(IWN_SCAN_MAXSZ, M_DEVBUF, M_NOWAIT | M_ZERO); 7045 if (buf == NULL) { 7046 device_printf(sc->sc_dev, 7047 "%s: could not allocate buffer for scan command\n", 7048 __func__); 7049 return ENOMEM; 7050 } 7051 hdr = (struct iwn_scan_hdr *)buf; 7052 /* 7053 * Move to the next channel if no frames are received within 10ms 7054 * after sending the probe request. 7055 */ 7056 hdr->quiet_time = htole16(10); /* timeout in milliseconds */ 7057 hdr->quiet_threshold = htole16(1); /* min # of packets */ 7058 /* 7059 * Max needs to be greater than active and passive and quiet! 7060 * It's also in microseconds! 7061 */ 7062 hdr->max_svc = htole32(250 * 1024); 7063 7064 /* 7065 * Reset scan: interval=100 7066 * Normal scan: interval=becaon interval 7067 * suspend_time: 100 (TU) 7068 * 7069 */ 7070 #if 0 7071 extra = (100 /* suspend_time */ / 100 /* beacon interval */) << 22; 7072 scan_service_time = extra | ((100 /* susp */ % 100 /* int */) * 1024); 7073 #else 7074 scan_service_time = (4 << 22) | (100 * 1024); /* Hardcode for now! */ 7075 #endif 7076 hdr->pause_svc = htole32(scan_service_time); 7077 7078 /* Select antennas for scanning. */ 7079 rxchain = 7080 IWN_RXCHAIN_VALID(sc->rxchainmask) | 7081 IWN_RXCHAIN_FORCE_MIMO_SEL(sc->rxchainmask) | 7082 IWN_RXCHAIN_DRIVER_FORCE; 7083 if (IEEE80211_IS_CHAN_A(c) && 7084 sc->hw_type == IWN_HW_REV_TYPE_4965) { 7085 /* Ant A must be avoided in 5GHz because of an HW bug. */ 7086 rxchain |= IWN_RXCHAIN_FORCE_SEL(IWN_ANT_B); 7087 } else /* Use all available RX antennas. */ 7088 rxchain |= IWN_RXCHAIN_FORCE_SEL(sc->rxchainmask); 7089 hdr->rxchain = htole16(rxchain); 7090 hdr->filter = htole32(IWN_FILTER_MULTICAST | IWN_FILTER_BEACON); 7091 7092 tx = (struct iwn_cmd_data *)(hdr + 1); 7093 tx->flags = htole32(IWN_TX_AUTO_SEQ); 7094 tx->id = sc->broadcast_id; 7095 tx->lifetime = htole32(IWN_LIFETIME_INFINITE); 7096 7097 if (IEEE80211_IS_CHAN_5GHZ(c)) { 7098 /* Send probe requests at 6Mbps. */ 7099 tx->rate = htole32(0xd); 7100 rs = &ic->ic_sup_rates[IEEE80211_MODE_11A]; 7101 } else { 7102 hdr->flags = htole32(IWN_RXON_24GHZ | IWN_RXON_AUTO); 7103 if (sc->hw_type == IWN_HW_REV_TYPE_4965 && 7104 sc->rxon->associd && sc->rxon->chan > 14) 7105 tx->rate = htole32(0xd); 7106 else { 7107 /* Send probe requests at 1Mbps. */ 7108 tx->rate = htole32(10 | IWN_RFLAG_CCK); 7109 } 7110 rs = &ic->ic_sup_rates[IEEE80211_MODE_11G]; 7111 } 7112 /* Use the first valid TX antenna. */ 7113 txant = IWN_LSB(sc->txchainmask); 7114 tx->rate |= htole32(IWN_RFLAG_ANT(txant)); 7115 7116 /* 7117 * Only do active scanning if we're announcing a probe request 7118 * for a given SSID (or more, if we ever add it to the driver.) 7119 */ 7120 is_active = 0; 7121 7122 /* 7123 * If we're scanning for a specific SSID, add it to the command. 7124 * 7125 * XXX maybe look at adding support for scanning multiple SSIDs? 7126 */ 7127 essid = (struct iwn_scan_essid *)(tx + 1); 7128 if (ss != NULL) { 7129 if (ss->ss_ssid[0].len != 0) { 7130 essid[0].id = IEEE80211_ELEMID_SSID; 7131 essid[0].len = ss->ss_ssid[0].len; 7132 memcpy(essid[0].data, ss->ss_ssid[0].ssid, ss->ss_ssid[0].len); 7133 } 7134 7135 DPRINTF(sc, IWN_DEBUG_SCAN, "%s: ssid_len=%d, ssid=%*s\n", 7136 __func__, 7137 ss->ss_ssid[0].len, 7138 ss->ss_ssid[0].len, 7139 ss->ss_ssid[0].ssid); 7140 7141 if (ss->ss_nssid > 0) 7142 is_active = 1; 7143 } 7144 7145 /* 7146 * Build a probe request frame. Most of the following code is a 7147 * copy & paste of what is done in net80211. 7148 */ 7149 wh = (struct ieee80211_frame *)(essid + 20); 7150 wh->i_fc[0] = IEEE80211_FC0_VERSION_0 | IEEE80211_FC0_TYPE_MGT | 7151 IEEE80211_FC0_SUBTYPE_PROBE_REQ; 7152 wh->i_fc[1] = IEEE80211_FC1_DIR_NODS; 7153 IEEE80211_ADDR_COPY(wh->i_addr1, if_getbroadcastaddr(vap->iv_ifp)); 7154 IEEE80211_ADDR_COPY(wh->i_addr2, if_getlladdr(vap->iv_ifp)); 7155 IEEE80211_ADDR_COPY(wh->i_addr3, if_getbroadcastaddr(vap->iv_ifp)); 7156 *(uint16_t *)&wh->i_dur[0] = 0; /* filled by HW */ 7157 *(uint16_t *)&wh->i_seq[0] = 0; /* filled by HW */ 7158 7159 frm = (uint8_t *)(wh + 1); 7160 frm = ieee80211_add_ssid(frm, NULL, 0); 7161 frm = ieee80211_add_rates(frm, rs); 7162 if (rs->rs_nrates > IEEE80211_RATE_SIZE) 7163 frm = ieee80211_add_xrates(frm, rs); 7164 if (ic->ic_htcaps & IEEE80211_HTC_HT) 7165 frm = ieee80211_add_htcap(frm, ni); 7166 7167 /* Set length of probe request. */ 7168 tx->len = htole16(frm - (uint8_t *)wh); 7169 7170 /* 7171 * If active scanning is requested but a certain channel is 7172 * marked passive, we can do active scanning if we detect 7173 * transmissions. 7174 * 7175 * There is an issue with some firmware versions that triggers 7176 * a sysassert on a "good CRC threshold" of zero (== disabled), 7177 * on a radar channel even though this means that we should NOT 7178 * send probes. 7179 * 7180 * The "good CRC threshold" is the number of frames that we 7181 * need to receive during our dwell time on a channel before 7182 * sending out probes -- setting this to a huge value will 7183 * mean we never reach it, but at the same time work around 7184 * the aforementioned issue. Thus use IWL_GOOD_CRC_TH_NEVER 7185 * here instead of IWL_GOOD_CRC_TH_DISABLED. 7186 * 7187 * This was fixed in later versions along with some other 7188 * scan changes, and the threshold behaves as a flag in those 7189 * versions. 7190 */ 7191 7192 /* 7193 * If we're doing active scanning, set the crc_threshold 7194 * to a suitable value. This is different to active veruss 7195 * passive scanning depending upon the channel flags; the 7196 * firmware will obey that particular check for us. 7197 */ 7198 if (sc->tlv_feature_flags & IWN_UCODE_TLV_FLAGS_NEWSCAN) 7199 hdr->crc_threshold = is_active ? 7200 IWN_GOOD_CRC_TH_DEFAULT : IWN_GOOD_CRC_TH_DISABLED; 7201 else 7202 hdr->crc_threshold = is_active ? 7203 IWN_GOOD_CRC_TH_DEFAULT : IWN_GOOD_CRC_TH_NEVER; 7204 7205 chan = (struct iwn_scan_chan *)frm; 7206 chan->chan = htole16(ieee80211_chan2ieee(ic, c)); 7207 chan->flags = 0; 7208 if (ss->ss_nssid > 0) 7209 chan->flags |= htole32(IWN_CHAN_NPBREQS(1)); 7210 chan->dsp_gain = 0x6e; 7211 7212 /* 7213 * Set the passive/active flag depending upon the channel mode. 7214 * XXX TODO: take the is_active flag into account as well? 7215 */ 7216 if (c->ic_flags & IEEE80211_CHAN_PASSIVE) 7217 chan->flags |= htole32(IWN_CHAN_PASSIVE); 7218 else 7219 chan->flags |= htole32(IWN_CHAN_ACTIVE); 7220 7221 /* 7222 * Calculate the active/passive dwell times. 7223 */ 7224 7225 dwell_active = iwn_get_active_dwell_time(sc, c, ss->ss_nssid); 7226 dwell_passive = iwn_get_passive_dwell_time(sc, c); 7227 7228 /* Make sure they're valid */ 7229 if (dwell_passive <= dwell_active) 7230 dwell_passive = dwell_active + 1; 7231 7232 chan->active = htole16(dwell_active); 7233 chan->passive = htole16(dwell_passive); 7234 7235 if (IEEE80211_IS_CHAN_5GHZ(c)) 7236 chan->rf_gain = 0x3b; 7237 else 7238 chan->rf_gain = 0x28; 7239 7240 DPRINTF(sc, IWN_DEBUG_STATE, 7241 "%s: chan %u flags 0x%x rf_gain 0x%x " 7242 "dsp_gain 0x%x active %d passive %d scan_svc_time %d crc 0x%x " 7243 "isactive=%d numssid=%d\n", __func__, 7244 chan->chan, chan->flags, chan->rf_gain, chan->dsp_gain, 7245 dwell_active, dwell_passive, scan_service_time, 7246 hdr->crc_threshold, is_active, ss->ss_nssid); 7247 7248 hdr->nchan++; 7249 chan++; 7250 buflen = (uint8_t *)chan - buf; 7251 hdr->len = htole16(buflen); 7252 7253 if (sc->sc_is_scanning) { 7254 device_printf(sc->sc_dev, 7255 "%s: called with is_scanning set!\n", 7256 __func__); 7257 } 7258 sc->sc_is_scanning = 1; 7259 7260 DPRINTF(sc, IWN_DEBUG_STATE, "sending scan command nchan=%d\n", 7261 hdr->nchan); 7262 error = iwn_cmd(sc, IWN_CMD_SCAN, buf, buflen, 1); 7263 free(buf, M_DEVBUF); 7264 if (error == 0) 7265 callout_reset(&sc->scan_timeout, 5*hz, iwn_scan_timeout, sc); 7266 7267 DPRINTF(sc, IWN_DEBUG_TRACE, "->%s: end\n",__func__); 7268 7269 return error; 7270 } 7271 7272 static int 7273 iwn_auth(struct iwn_softc *sc, struct ieee80211vap *vap) 7274 { 7275 struct ieee80211com *ic = &sc->sc_ic; 7276 struct ieee80211_node *ni = vap->iv_bss; 7277 int error; 7278 7279 DPRINTF(sc, IWN_DEBUG_TRACE, "->%s begin\n", __func__); 7280 7281 sc->rxon = &sc->rx_on[IWN_RXON_BSS_CTX]; 7282 /* Update adapter configuration. */ 7283 IEEE80211_ADDR_COPY(sc->rxon->bssid, ni->ni_bssid); 7284 sc->rxon->chan = ieee80211_chan2ieee(ic, ni->ni_chan); 7285 sc->rxon->flags = htole32(IWN_RXON_TSF | IWN_RXON_CTS_TO_SELF); 7286 if (IEEE80211_IS_CHAN_2GHZ(ni->ni_chan)) 7287 sc->rxon->flags |= htole32(IWN_RXON_AUTO | IWN_RXON_24GHZ); 7288 7289 /* 7290 * We always set short slot on 5GHz channels. 7291 * We optionally set it for 2.4GHz channels. 7292 */ 7293 if (IEEE80211_IS_CHAN_5GHZ(ni->ni_chan)) 7294 sc->rxon->flags |= htole32(IWN_RXON_SHSLOT); 7295 else if (vap->iv_flags & IEEE80211_F_SHSLOT) 7296 sc->rxon->flags |= htole32(IWN_RXON_SHSLOT); 7297 7298 if (vap->iv_flags & IEEE80211_F_SHPREAMBLE) 7299 sc->rxon->flags |= htole32(IWN_RXON_SHPREAMBLE); 7300 if (IEEE80211_IS_CHAN_A(ni->ni_chan)) { 7301 sc->rxon->cck_mask = 0; 7302 sc->rxon->ofdm_mask = 0x15; 7303 } else if (IEEE80211_IS_CHAN_B(ni->ni_chan)) { 7304 sc->rxon->cck_mask = 0x03; 7305 sc->rxon->ofdm_mask = 0; 7306 } else { 7307 /* Assume 802.11b/g. */ 7308 sc->rxon->cck_mask = 0x03; 7309 sc->rxon->ofdm_mask = 0x15; 7310 } 7311 7312 /* try HT */ 7313 sc->rxon->flags |= htole32(iwn_get_rxon_ht_flags(sc, vap, ic->ic_curchan)); 7314 7315 DPRINTF(sc, IWN_DEBUG_STATE, "rxon chan %d flags %x cck %x ofdm %x\n", 7316 sc->rxon->chan, sc->rxon->flags, sc->rxon->cck_mask, 7317 sc->rxon->ofdm_mask); 7318 7319 if ((error = iwn_send_rxon(sc, 0, 1)) != 0) { 7320 device_printf(sc->sc_dev, "%s: could not send RXON\n", 7321 __func__); 7322 return (error); 7323 } 7324 7325 DPRINTF(sc, IWN_DEBUG_TRACE, "->%s: end\n",__func__); 7326 7327 return (0); 7328 } 7329 7330 static int 7331 iwn_run(struct iwn_softc *sc, struct ieee80211vap *vap) 7332 { 7333 struct iwn_ops *ops = &sc->ops; 7334 struct ieee80211com *ic = &sc->sc_ic; 7335 struct ieee80211_node *ni = vap->iv_bss; 7336 struct iwn_node_info node; 7337 int error; 7338 7339 DPRINTF(sc, IWN_DEBUG_TRACE, "->%s begin\n", __func__); 7340 7341 sc->rxon = &sc->rx_on[IWN_RXON_BSS_CTX]; 7342 if (ic->ic_opmode == IEEE80211_M_MONITOR) { 7343 /* Link LED blinks while monitoring. */ 7344 iwn_set_led(sc, IWN_LED_LINK, 5, 5); 7345 return 0; 7346 } 7347 if ((error = iwn_set_timing(sc, ni)) != 0) { 7348 device_printf(sc->sc_dev, 7349 "%s: could not set timing, error %d\n", __func__, error); 7350 return error; 7351 } 7352 7353 /* Update adapter configuration. */ 7354 IEEE80211_ADDR_COPY(sc->rxon->bssid, ni->ni_bssid); 7355 sc->rxon->associd = htole16(IEEE80211_AID(ni->ni_associd)); 7356 sc->rxon->chan = ieee80211_chan2ieee(ic, ni->ni_chan); 7357 sc->rxon->flags = htole32(IWN_RXON_TSF | IWN_RXON_CTS_TO_SELF); 7358 if (IEEE80211_IS_CHAN_2GHZ(ni->ni_chan)) 7359 sc->rxon->flags |= htole32(IWN_RXON_AUTO | IWN_RXON_24GHZ); 7360 7361 /* As previously - short slot only on 5GHz */ 7362 if (IEEE80211_IS_CHAN_5GHZ(ni->ni_chan)) 7363 sc->rxon->flags |= htole32(IWN_RXON_SHSLOT); 7364 else if (vap->iv_flags & IEEE80211_F_SHSLOT) 7365 sc->rxon->flags |= htole32(IWN_RXON_SHSLOT); 7366 7367 if (vap->iv_flags & IEEE80211_F_SHPREAMBLE) 7368 sc->rxon->flags |= htole32(IWN_RXON_SHPREAMBLE); 7369 if (IEEE80211_IS_CHAN_A(ni->ni_chan)) { 7370 sc->rxon->cck_mask = 0; 7371 sc->rxon->ofdm_mask = 0x15; 7372 } else if (IEEE80211_IS_CHAN_B(ni->ni_chan)) { 7373 sc->rxon->cck_mask = 0x03; 7374 sc->rxon->ofdm_mask = 0; 7375 } else { 7376 /* Assume 802.11b/g. */ 7377 sc->rxon->cck_mask = 0x0f; 7378 sc->rxon->ofdm_mask = 0x15; 7379 } 7380 /* try HT */ 7381 sc->rxon->flags |= htole32(iwn_get_rxon_ht_flags(sc, vap, ni->ni_chan)); 7382 sc->rxon->filter |= htole32(IWN_FILTER_BSS); 7383 DPRINTF(sc, IWN_DEBUG_STATE, "rxon chan %d flags %x, curhtprotmode=%d\n", 7384 sc->rxon->chan, le32toh(sc->rxon->flags), vap->iv_curhtprotmode); 7385 7386 if ((error = iwn_send_rxon(sc, 0, 1)) != 0) { 7387 device_printf(sc->sc_dev, "%s: could not send RXON\n", 7388 __func__); 7389 return error; 7390 } 7391 7392 /* Fake a join to initialize the TX rate. */ 7393 ((struct iwn_node *)ni)->id = IWN_ID_BSS; 7394 iwn_newassoc(ni, 1); 7395 7396 /* Add BSS node. */ 7397 memset(&node, 0, sizeof node); 7398 IEEE80211_ADDR_COPY(node.macaddr, ni->ni_macaddr); 7399 node.id = IWN_ID_BSS; 7400 if (IEEE80211_IS_CHAN_HT(ni->ni_chan)) { 7401 switch (ni->ni_htcap & IEEE80211_HTCAP_SMPS) { 7402 case IEEE80211_HTCAP_SMPS_ENA: 7403 node.htflags |= htole32(IWN_SMPS_MIMO_DIS); 7404 break; 7405 case IEEE80211_HTCAP_SMPS_DYNAMIC: 7406 node.htflags |= htole32(IWN_SMPS_MIMO_PROT); 7407 break; 7408 } 7409 node.htflags |= htole32(IWN_AMDPU_SIZE_FACTOR(3) | 7410 IWN_AMDPU_DENSITY(5)); /* 4us */ 7411 if (IEEE80211_IS_CHAN_HT40(ni->ni_chan)) 7412 node.htflags |= htole32(IWN_NODE_HT40); 7413 } 7414 DPRINTF(sc, IWN_DEBUG_STATE, "%s: adding BSS node\n", __func__); 7415 error = ops->add_node(sc, &node, 1); 7416 if (error != 0) { 7417 device_printf(sc->sc_dev, 7418 "%s: could not add BSS node, error %d\n", __func__, error); 7419 return error; 7420 } 7421 DPRINTF(sc, IWN_DEBUG_STATE, "%s: setting link quality for node %d\n", 7422 __func__, node.id); 7423 if ((error = iwn_set_link_quality(sc, ni)) != 0) { 7424 device_printf(sc->sc_dev, 7425 "%s: could not setup link quality for node %d, error %d\n", 7426 __func__, node.id, error); 7427 return error; 7428 } 7429 7430 if ((error = iwn_init_sensitivity(sc)) != 0) { 7431 device_printf(sc->sc_dev, 7432 "%s: could not set sensitivity, error %d\n", __func__, 7433 error); 7434 return error; 7435 } 7436 /* Start periodic calibration timer. */ 7437 sc->calib.state = IWN_CALIB_STATE_ASSOC; 7438 sc->calib_cnt = 0; 7439 callout_reset(&sc->calib_to, msecs_to_ticks(500), iwn_calib_timeout, 7440 sc); 7441 7442 /* Link LED always on while associated. */ 7443 iwn_set_led(sc, IWN_LED_LINK, 0, 1); 7444 7445 DPRINTF(sc, IWN_DEBUG_TRACE, "->%s: end\n",__func__); 7446 7447 return 0; 7448 } 7449 7450 /* 7451 * This function is called by upper layer when an ADDBA request is received 7452 * from another STA and before the ADDBA response is sent. 7453 */ 7454 static int 7455 iwn_ampdu_rx_start(struct ieee80211_node *ni, struct ieee80211_rx_ampdu *rap, 7456 int baparamset, int batimeout, int baseqctl) 7457 { 7458 struct iwn_softc *sc = ni->ni_ic->ic_softc; 7459 struct iwn_ops *ops = &sc->ops; 7460 struct iwn_node *wn = (void *)ni; 7461 struct iwn_node_info node; 7462 uint16_t ssn; 7463 uint8_t tid; 7464 int error; 7465 7466 DPRINTF(sc, IWN_DEBUG_TRACE, "->Doing %s\n", __func__); 7467 7468 tid = _IEEE80211_MASKSHIFT(le16toh(baparamset), IEEE80211_BAPS_TID); 7469 ssn = _IEEE80211_MASKSHIFT(le16toh(baseqctl), IEEE80211_BASEQ_START); 7470 7471 if (wn->id == IWN_ID_UNDEFINED) 7472 return (ENOENT); 7473 7474 memset(&node, 0, sizeof node); 7475 node.id = wn->id; 7476 node.control = IWN_NODE_UPDATE; 7477 node.flags = IWN_FLAG_SET_ADDBA; 7478 node.addba_tid = tid; 7479 node.addba_ssn = htole16(ssn); 7480 DPRINTF(sc, IWN_DEBUG_RECV, "ADDBA RA=%d TID=%d SSN=%d\n", 7481 wn->id, tid, ssn); 7482 error = ops->add_node(sc, &node, 1); 7483 if (error != 0) 7484 return error; 7485 return sc->sc_ampdu_rx_start(ni, rap, baparamset, batimeout, baseqctl); 7486 } 7487 7488 /* 7489 * This function is called by upper layer on teardown of an HT-immediate 7490 * Block Ack agreement (eg. uppon receipt of a DELBA frame). 7491 */ 7492 static void 7493 iwn_ampdu_rx_stop(struct ieee80211_node *ni, struct ieee80211_rx_ampdu *rap) 7494 { 7495 struct ieee80211com *ic = ni->ni_ic; 7496 struct iwn_softc *sc = ic->ic_softc; 7497 struct iwn_ops *ops = &sc->ops; 7498 struct iwn_node *wn = (void *)ni; 7499 struct iwn_node_info node; 7500 uint8_t tid; 7501 7502 DPRINTF(sc, IWN_DEBUG_TRACE, "->Doing %s\n", __func__); 7503 7504 if (wn->id == IWN_ID_UNDEFINED) 7505 goto end; 7506 7507 /* XXX: tid as an argument */ 7508 for (tid = 0; tid < WME_NUM_TID; tid++) { 7509 if (&ni->ni_rx_ampdu[tid] == rap) 7510 break; 7511 } 7512 7513 memset(&node, 0, sizeof node); 7514 node.id = wn->id; 7515 node.control = IWN_NODE_UPDATE; 7516 node.flags = IWN_FLAG_SET_DELBA; 7517 node.delba_tid = tid; 7518 DPRINTF(sc, IWN_DEBUG_RECV, "DELBA RA=%d TID=%d\n", wn->id, tid); 7519 (void)ops->add_node(sc, &node, 1); 7520 end: 7521 sc->sc_ampdu_rx_stop(ni, rap); 7522 } 7523 7524 static int 7525 iwn_addba_request(struct ieee80211_node *ni, struct ieee80211_tx_ampdu *tap, 7526 int dialogtoken, int baparamset, int batimeout) 7527 { 7528 struct iwn_softc *sc = ni->ni_ic->ic_softc; 7529 int qid; 7530 7531 DPRINTF(sc, IWN_DEBUG_TRACE, "->Doing %s\n", __func__); 7532 7533 for (qid = sc->firstaggqueue; qid < sc->ntxqs; qid++) { 7534 if (sc->qid2tap[qid] == NULL) 7535 break; 7536 } 7537 if (qid == sc->ntxqs) { 7538 DPRINTF(sc, IWN_DEBUG_XMIT, "%s: not free aggregation queue\n", 7539 __func__); 7540 return 0; 7541 } 7542 tap->txa_private = malloc(sizeof(int), M_DEVBUF, M_NOWAIT); 7543 if (tap->txa_private == NULL) { 7544 device_printf(sc->sc_dev, 7545 "%s: failed to alloc TX aggregation structure\n", __func__); 7546 return 0; 7547 } 7548 sc->qid2tap[qid] = tap; 7549 *(int *)tap->txa_private = qid; 7550 return sc->sc_addba_request(ni, tap, dialogtoken, baparamset, 7551 batimeout); 7552 } 7553 7554 static int 7555 iwn_addba_response(struct ieee80211_node *ni, struct ieee80211_tx_ampdu *tap, 7556 int code, int baparamset, int batimeout) 7557 { 7558 struct iwn_softc *sc = ni->ni_ic->ic_softc; 7559 int qid = *(int *)tap->txa_private; 7560 uint8_t tid = tap->txa_tid; 7561 int ret; 7562 7563 DPRINTF(sc, IWN_DEBUG_TRACE, "->Doing %s\n", __func__); 7564 7565 if (code == IEEE80211_STATUS_SUCCESS) { 7566 ni->ni_txseqs[tid] = tap->txa_start & 0xfff; 7567 ret = iwn_ampdu_tx_start(ni->ni_ic, ni, tid); 7568 if (ret != 1) 7569 return ret; 7570 } else { 7571 sc->qid2tap[qid] = NULL; 7572 free(tap->txa_private, M_DEVBUF); 7573 tap->txa_private = NULL; 7574 } 7575 return sc->sc_addba_response(ni, tap, code, baparamset, batimeout); 7576 } 7577 7578 /* 7579 * This function is called by upper layer when an ADDBA response is received 7580 * from another STA. 7581 */ 7582 static int 7583 iwn_ampdu_tx_start(struct ieee80211com *ic, struct ieee80211_node *ni, 7584 uint8_t tid) 7585 { 7586 struct ieee80211_tx_ampdu *tap = &ni->ni_tx_ampdu[tid]; 7587 struct iwn_softc *sc = ni->ni_ic->ic_softc; 7588 struct iwn_ops *ops = &sc->ops; 7589 struct iwn_node *wn = (void *)ni; 7590 struct iwn_node_info node; 7591 int error, qid; 7592 7593 DPRINTF(sc, IWN_DEBUG_TRACE, "->Doing %s\n", __func__); 7594 7595 if (wn->id == IWN_ID_UNDEFINED) 7596 return (0); 7597 7598 /* Enable TX for the specified RA/TID. */ 7599 wn->disable_tid &= ~(1 << tid); 7600 memset(&node, 0, sizeof node); 7601 node.id = wn->id; 7602 node.control = IWN_NODE_UPDATE; 7603 node.flags = IWN_FLAG_SET_DISABLE_TID; 7604 node.disable_tid = htole16(wn->disable_tid); 7605 error = ops->add_node(sc, &node, 1); 7606 if (error != 0) 7607 return 0; 7608 7609 if ((error = iwn_nic_lock(sc)) != 0) 7610 return 0; 7611 qid = *(int *)tap->txa_private; 7612 DPRINTF(sc, IWN_DEBUG_XMIT, "%s: ra=%d tid=%d ssn=%d qid=%d\n", 7613 __func__, wn->id, tid, tap->txa_start, qid); 7614 ops->ampdu_tx_start(sc, ni, qid, tid, tap->txa_start & 0xfff); 7615 iwn_nic_unlock(sc); 7616 7617 iwn_set_link_quality(sc, ni); 7618 return 1; 7619 } 7620 7621 static void 7622 iwn_ampdu_tx_stop(struct ieee80211_node *ni, struct ieee80211_tx_ampdu *tap) 7623 { 7624 struct iwn_softc *sc = ni->ni_ic->ic_softc; 7625 struct iwn_ops *ops = &sc->ops; 7626 uint8_t tid = tap->txa_tid; 7627 int qid; 7628 7629 DPRINTF(sc, IWN_DEBUG_TRACE, "->Doing %s\n", __func__); 7630 7631 sc->sc_addba_stop(ni, tap); 7632 7633 if (tap->txa_private == NULL) 7634 return; 7635 7636 qid = *(int *)tap->txa_private; 7637 if (sc->txq[qid].queued != 0) 7638 return; 7639 if (iwn_nic_lock(sc) != 0) 7640 return; 7641 ops->ampdu_tx_stop(sc, qid, tid, tap->txa_start & 0xfff); 7642 iwn_nic_unlock(sc); 7643 sc->qid2tap[qid] = NULL; 7644 free(tap->txa_private, M_DEVBUF); 7645 tap->txa_private = NULL; 7646 } 7647 7648 static void 7649 iwn4965_ampdu_tx_start(struct iwn_softc *sc, struct ieee80211_node *ni, 7650 int qid, uint8_t tid, uint16_t ssn) 7651 { 7652 struct iwn_node *wn = (void *)ni; 7653 7654 DPRINTF(sc, IWN_DEBUG_TRACE, "->Doing %s\n", __func__); 7655 7656 /* Stop TX scheduler while we're changing its configuration. */ 7657 iwn_prph_write(sc, IWN4965_SCHED_QUEUE_STATUS(qid), 7658 IWN4965_TXQ_STATUS_CHGACT); 7659 7660 /* Assign RA/TID translation to the queue. */ 7661 iwn_mem_write_2(sc, sc->sched_base + IWN4965_SCHED_TRANS_TBL(qid), 7662 wn->id << 4 | tid); 7663 7664 /* Enable chain-building mode for the queue. */ 7665 iwn_prph_setbits(sc, IWN4965_SCHED_QCHAIN_SEL, 1 << qid); 7666 7667 /* Set starting sequence number from the ADDBA request. */ 7668 sc->txq[qid].cur = sc->txq[qid].read = (ssn & 0xff); 7669 IWN_WRITE(sc, IWN_HBUS_TARG_WRPTR, qid << 8 | (ssn & 0xff)); 7670 iwn_prph_write(sc, IWN4965_SCHED_QUEUE_RDPTR(qid), ssn); 7671 7672 /* Set scheduler window size. */ 7673 iwn_mem_write(sc, sc->sched_base + IWN4965_SCHED_QUEUE_OFFSET(qid), 7674 IWN_SCHED_WINSZ); 7675 /* Set scheduler frame limit. */ 7676 iwn_mem_write(sc, sc->sched_base + IWN4965_SCHED_QUEUE_OFFSET(qid) + 4, 7677 IWN_SCHED_LIMIT << 16); 7678 7679 /* Enable interrupts for the queue. */ 7680 iwn_prph_setbits(sc, IWN4965_SCHED_INTR_MASK, 1 << qid); 7681 7682 /* Mark the queue as active. */ 7683 iwn_prph_write(sc, IWN4965_SCHED_QUEUE_STATUS(qid), 7684 IWN4965_TXQ_STATUS_ACTIVE | IWN4965_TXQ_STATUS_AGGR_ENA | 7685 iwn_tid2fifo[tid] << 1); 7686 } 7687 7688 static void 7689 iwn4965_ampdu_tx_stop(struct iwn_softc *sc, int qid, uint8_t tid, uint16_t ssn) 7690 { 7691 DPRINTF(sc, IWN_DEBUG_TRACE, "->Doing %s\n", __func__); 7692 7693 /* Stop TX scheduler while we're changing its configuration. */ 7694 iwn_prph_write(sc, IWN4965_SCHED_QUEUE_STATUS(qid), 7695 IWN4965_TXQ_STATUS_CHGACT); 7696 7697 /* Set starting sequence number from the ADDBA request. */ 7698 IWN_WRITE(sc, IWN_HBUS_TARG_WRPTR, qid << 8 | (ssn & 0xff)); 7699 iwn_prph_write(sc, IWN4965_SCHED_QUEUE_RDPTR(qid), ssn); 7700 7701 /* Disable interrupts for the queue. */ 7702 iwn_prph_clrbits(sc, IWN4965_SCHED_INTR_MASK, 1 << qid); 7703 7704 /* Mark the queue as inactive. */ 7705 iwn_prph_write(sc, IWN4965_SCHED_QUEUE_STATUS(qid), 7706 IWN4965_TXQ_STATUS_INACTIVE | iwn_tid2fifo[tid] << 1); 7707 } 7708 7709 static void 7710 iwn5000_ampdu_tx_start(struct iwn_softc *sc, struct ieee80211_node *ni, 7711 int qid, uint8_t tid, uint16_t ssn) 7712 { 7713 DPRINTF(sc, IWN_DEBUG_TRACE, "->Doing %s\n", __func__); 7714 7715 struct iwn_node *wn = (void *)ni; 7716 7717 /* Stop TX scheduler while we're changing its configuration. */ 7718 iwn_prph_write(sc, IWN5000_SCHED_QUEUE_STATUS(qid), 7719 IWN5000_TXQ_STATUS_CHGACT); 7720 7721 /* Assign RA/TID translation to the queue. */ 7722 iwn_mem_write_2(sc, sc->sched_base + IWN5000_SCHED_TRANS_TBL(qid), 7723 wn->id << 4 | tid); 7724 7725 /* Enable chain-building mode for the queue. */ 7726 iwn_prph_setbits(sc, IWN5000_SCHED_QCHAIN_SEL, 1 << qid); 7727 7728 /* Enable aggregation for the queue. */ 7729 iwn_prph_setbits(sc, IWN5000_SCHED_AGGR_SEL, 1 << qid); 7730 7731 /* Set starting sequence number from the ADDBA request. */ 7732 sc->txq[qid].cur = sc->txq[qid].read = (ssn & 0xff); 7733 IWN_WRITE(sc, IWN_HBUS_TARG_WRPTR, qid << 8 | (ssn & 0xff)); 7734 iwn_prph_write(sc, IWN5000_SCHED_QUEUE_RDPTR(qid), ssn); 7735 7736 /* Set scheduler window size and frame limit. */ 7737 iwn_mem_write(sc, sc->sched_base + IWN5000_SCHED_QUEUE_OFFSET(qid) + 4, 7738 IWN_SCHED_LIMIT << 16 | IWN_SCHED_WINSZ); 7739 7740 /* Enable interrupts for the queue. */ 7741 iwn_prph_setbits(sc, IWN5000_SCHED_INTR_MASK, 1 << qid); 7742 7743 /* Mark the queue as active. */ 7744 iwn_prph_write(sc, IWN5000_SCHED_QUEUE_STATUS(qid), 7745 IWN5000_TXQ_STATUS_ACTIVE | iwn_tid2fifo[tid]); 7746 } 7747 7748 static void 7749 iwn5000_ampdu_tx_stop(struct iwn_softc *sc, int qid, uint8_t tid, uint16_t ssn) 7750 { 7751 DPRINTF(sc, IWN_DEBUG_TRACE, "->Doing %s\n", __func__); 7752 7753 /* Stop TX scheduler while we're changing its configuration. */ 7754 iwn_prph_write(sc, IWN5000_SCHED_QUEUE_STATUS(qid), 7755 IWN5000_TXQ_STATUS_CHGACT); 7756 7757 /* Disable aggregation for the queue. */ 7758 iwn_prph_clrbits(sc, IWN5000_SCHED_AGGR_SEL, 1 << qid); 7759 7760 /* Set starting sequence number from the ADDBA request. */ 7761 IWN_WRITE(sc, IWN_HBUS_TARG_WRPTR, qid << 8 | (ssn & 0xff)); 7762 iwn_prph_write(sc, IWN5000_SCHED_QUEUE_RDPTR(qid), ssn); 7763 7764 /* Disable interrupts for the queue. */ 7765 iwn_prph_clrbits(sc, IWN5000_SCHED_INTR_MASK, 1 << qid); 7766 7767 /* Mark the queue as inactive. */ 7768 iwn_prph_write(sc, IWN5000_SCHED_QUEUE_STATUS(qid), 7769 IWN5000_TXQ_STATUS_INACTIVE | iwn_tid2fifo[tid]); 7770 } 7771 7772 /* 7773 * Query calibration tables from the initialization firmware. We do this 7774 * only once at first boot. Called from a process context. 7775 */ 7776 static int 7777 iwn5000_query_calibration(struct iwn_softc *sc) 7778 { 7779 struct iwn5000_calib_config cmd; 7780 int error; 7781 7782 memset(&cmd, 0, sizeof cmd); 7783 cmd.ucode.once.enable = htole32(0xffffffff); 7784 cmd.ucode.once.start = htole32(0xffffffff); 7785 cmd.ucode.once.send = htole32(0xffffffff); 7786 cmd.ucode.flags = htole32(0xffffffff); 7787 DPRINTF(sc, IWN_DEBUG_CALIBRATE, "%s: sending calibration query\n", 7788 __func__); 7789 error = iwn_cmd(sc, IWN5000_CMD_CALIB_CONFIG, &cmd, sizeof cmd, 0); 7790 if (error != 0) 7791 return error; 7792 7793 /* Wait at most two seconds for calibration to complete. */ 7794 if (!(sc->sc_flags & IWN_FLAG_CALIB_DONE)) 7795 error = msleep(sc, &sc->sc_mtx, PCATCH, "iwncal", 2 * hz); 7796 return error; 7797 } 7798 7799 /* 7800 * Send calibration results to the runtime firmware. These results were 7801 * obtained on first boot from the initialization firmware. 7802 */ 7803 static int 7804 iwn5000_send_calibration(struct iwn_softc *sc) 7805 { 7806 int idx, error; 7807 7808 for (idx = 0; idx < IWN5000_PHY_CALIB_MAX_RESULT; idx++) { 7809 if (!(sc->base_params->calib_need & (1<<idx))) { 7810 DPRINTF(sc, IWN_DEBUG_CALIBRATE, 7811 "No need of calib %d\n", 7812 idx); 7813 continue; /* no need for this calib */ 7814 } 7815 if (sc->calibcmd[idx].buf == NULL) { 7816 DPRINTF(sc, IWN_DEBUG_CALIBRATE, 7817 "Need calib idx : %d but no available data\n", 7818 idx); 7819 continue; 7820 } 7821 7822 DPRINTF(sc, IWN_DEBUG_CALIBRATE, 7823 "send calibration result idx=%d len=%d\n", idx, 7824 sc->calibcmd[idx].len); 7825 error = iwn_cmd(sc, IWN_CMD_PHY_CALIB, sc->calibcmd[idx].buf, 7826 sc->calibcmd[idx].len, 0); 7827 if (error != 0) { 7828 device_printf(sc->sc_dev, 7829 "%s: could not send calibration result, error %d\n", 7830 __func__, error); 7831 return error; 7832 } 7833 } 7834 return 0; 7835 } 7836 7837 static int 7838 iwn5000_send_wimax_coex(struct iwn_softc *sc) 7839 { 7840 struct iwn5000_wimax_coex wimax; 7841 7842 #if 0 7843 if (sc->hw_type == IWN_HW_REV_TYPE_6050) { 7844 /* Enable WiMAX coexistence for combo adapters. */ 7845 wimax.flags = 7846 IWN_WIMAX_COEX_ASSOC_WA_UNMASK | 7847 IWN_WIMAX_COEX_UNASSOC_WA_UNMASK | 7848 IWN_WIMAX_COEX_STA_TABLE_VALID | 7849 IWN_WIMAX_COEX_ENABLE; 7850 memcpy(wimax.events, iwn6050_wimax_events, 7851 sizeof iwn6050_wimax_events); 7852 } else 7853 #endif 7854 { 7855 /* Disable WiMAX coexistence. */ 7856 wimax.flags = 0; 7857 memset(wimax.events, 0, sizeof wimax.events); 7858 } 7859 DPRINTF(sc, IWN_DEBUG_RESET, "%s: Configuring WiMAX coexistence\n", 7860 __func__); 7861 return iwn_cmd(sc, IWN5000_CMD_WIMAX_COEX, &wimax, sizeof wimax, 0); 7862 } 7863 7864 static int 7865 iwn5000_crystal_calib(struct iwn_softc *sc) 7866 { 7867 struct iwn5000_phy_calib_crystal cmd; 7868 7869 memset(&cmd, 0, sizeof cmd); 7870 cmd.code = IWN5000_PHY_CALIB_CRYSTAL; 7871 cmd.ngroups = 1; 7872 cmd.isvalid = 1; 7873 cmd.cap_pin[0] = le32toh(sc->eeprom_crystal) & 0xff; 7874 cmd.cap_pin[1] = (le32toh(sc->eeprom_crystal) >> 16) & 0xff; 7875 DPRINTF(sc, IWN_DEBUG_CALIBRATE, "sending crystal calibration %d, %d\n", 7876 cmd.cap_pin[0], cmd.cap_pin[1]); 7877 return iwn_cmd(sc, IWN_CMD_PHY_CALIB, &cmd, sizeof cmd, 0); 7878 } 7879 7880 static int 7881 iwn5000_temp_offset_calib(struct iwn_softc *sc) 7882 { 7883 struct iwn5000_phy_calib_temp_offset cmd; 7884 7885 memset(&cmd, 0, sizeof cmd); 7886 cmd.code = IWN5000_PHY_CALIB_TEMP_OFFSET; 7887 cmd.ngroups = 1; 7888 cmd.isvalid = 1; 7889 if (sc->eeprom_temp != 0) 7890 cmd.offset = htole16(sc->eeprom_temp); 7891 else 7892 cmd.offset = htole16(IWN_DEFAULT_TEMP_OFFSET); 7893 DPRINTF(sc, IWN_DEBUG_CALIBRATE, "setting radio sensor offset to %d\n", 7894 le16toh(cmd.offset)); 7895 return iwn_cmd(sc, IWN_CMD_PHY_CALIB, &cmd, sizeof cmd, 0); 7896 } 7897 7898 static int 7899 iwn5000_temp_offset_calibv2(struct iwn_softc *sc) 7900 { 7901 struct iwn5000_phy_calib_temp_offsetv2 cmd; 7902 7903 memset(&cmd, 0, sizeof cmd); 7904 cmd.code = IWN5000_PHY_CALIB_TEMP_OFFSET; 7905 cmd.ngroups = 1; 7906 cmd.isvalid = 1; 7907 if (sc->eeprom_temp != 0) { 7908 cmd.offset_low = htole16(sc->eeprom_temp); 7909 cmd.offset_high = htole16(sc->eeprom_temp_high); 7910 } else { 7911 cmd.offset_low = htole16(IWN_DEFAULT_TEMP_OFFSET); 7912 cmd.offset_high = htole16(IWN_DEFAULT_TEMP_OFFSET); 7913 } 7914 cmd.burnt_voltage_ref = htole16(sc->eeprom_voltage); 7915 7916 DPRINTF(sc, IWN_DEBUG_CALIBRATE, 7917 "setting radio sensor low offset to %d, high offset to %d, voltage to %d\n", 7918 le16toh(cmd.offset_low), 7919 le16toh(cmd.offset_high), 7920 le16toh(cmd.burnt_voltage_ref)); 7921 7922 return iwn_cmd(sc, IWN_CMD_PHY_CALIB, &cmd, sizeof cmd, 0); 7923 } 7924 7925 /* 7926 * This function is called after the runtime firmware notifies us of its 7927 * readiness (called in a process context). 7928 */ 7929 static int 7930 iwn4965_post_alive(struct iwn_softc *sc) 7931 { 7932 int error, qid; 7933 7934 if ((error = iwn_nic_lock(sc)) != 0) 7935 return error; 7936 7937 DPRINTF(sc, IWN_DEBUG_TRACE, "->Doing %s\n", __func__); 7938 7939 /* Clear TX scheduler state in SRAM. */ 7940 sc->sched_base = iwn_prph_read(sc, IWN_SCHED_SRAM_ADDR); 7941 iwn_mem_set_region_4(sc, sc->sched_base + IWN4965_SCHED_CTX_OFF, 0, 7942 IWN4965_SCHED_CTX_LEN / sizeof (uint32_t)); 7943 7944 /* Set physical address of TX scheduler rings (1KB aligned). */ 7945 iwn_prph_write(sc, IWN4965_SCHED_DRAM_ADDR, sc->sched_dma.paddr >> 10); 7946 7947 IWN_SETBITS(sc, IWN_FH_TX_CHICKEN, IWN_FH_TX_CHICKEN_SCHED_RETRY); 7948 7949 /* Disable chain mode for all our 16 queues. */ 7950 iwn_prph_write(sc, IWN4965_SCHED_QCHAIN_SEL, 0); 7951 7952 for (qid = 0; qid < IWN4965_NTXQUEUES; qid++) { 7953 iwn_prph_write(sc, IWN4965_SCHED_QUEUE_RDPTR(qid), 0); 7954 IWN_WRITE(sc, IWN_HBUS_TARG_WRPTR, qid << 8 | 0); 7955 7956 /* Set scheduler window size. */ 7957 iwn_mem_write(sc, sc->sched_base + 7958 IWN4965_SCHED_QUEUE_OFFSET(qid), IWN_SCHED_WINSZ); 7959 /* Set scheduler frame limit. */ 7960 iwn_mem_write(sc, sc->sched_base + 7961 IWN4965_SCHED_QUEUE_OFFSET(qid) + 4, 7962 IWN_SCHED_LIMIT << 16); 7963 } 7964 7965 /* Enable interrupts for all our 16 queues. */ 7966 iwn_prph_write(sc, IWN4965_SCHED_INTR_MASK, 0xffff); 7967 /* Identify TX FIFO rings (0-7). */ 7968 iwn_prph_write(sc, IWN4965_SCHED_TXFACT, 0xff); 7969 7970 /* Mark TX rings (4 EDCA + cmd + 2 HCCA) as active. */ 7971 for (qid = 0; qid < 7; qid++) { 7972 static uint8_t qid2fifo[] = { 3, 2, 1, 0, 4, 5, 6 }; 7973 iwn_prph_write(sc, IWN4965_SCHED_QUEUE_STATUS(qid), 7974 IWN4965_TXQ_STATUS_ACTIVE | qid2fifo[qid] << 1); 7975 } 7976 iwn_nic_unlock(sc); 7977 return 0; 7978 } 7979 7980 /* 7981 * This function is called after the initialization or runtime firmware 7982 * notifies us of its readiness (called in a process context). 7983 */ 7984 static int 7985 iwn5000_post_alive(struct iwn_softc *sc) 7986 { 7987 int error, qid; 7988 7989 DPRINTF(sc, IWN_DEBUG_TRACE, "->%s begin\n", __func__); 7990 7991 /* Switch to using ICT interrupt mode. */ 7992 iwn5000_ict_reset(sc); 7993 7994 if ((error = iwn_nic_lock(sc)) != 0){ 7995 DPRINTF(sc, IWN_DEBUG_TRACE, "->%s end in error\n", __func__); 7996 return error; 7997 } 7998 7999 /* Clear TX scheduler state in SRAM. */ 8000 sc->sched_base = iwn_prph_read(sc, IWN_SCHED_SRAM_ADDR); 8001 iwn_mem_set_region_4(sc, sc->sched_base + IWN5000_SCHED_CTX_OFF, 0, 8002 IWN5000_SCHED_CTX_LEN / sizeof (uint32_t)); 8003 8004 /* Set physical address of TX scheduler rings (1KB aligned). */ 8005 iwn_prph_write(sc, IWN5000_SCHED_DRAM_ADDR, sc->sched_dma.paddr >> 10); 8006 8007 IWN_SETBITS(sc, IWN_FH_TX_CHICKEN, IWN_FH_TX_CHICKEN_SCHED_RETRY); 8008 8009 /* Enable chain mode for all queues, except command queue. */ 8010 if (sc->sc_flags & IWN_FLAG_PAN_SUPPORT) 8011 iwn_prph_write(sc, IWN5000_SCHED_QCHAIN_SEL, 0xfffdf); 8012 else 8013 iwn_prph_write(sc, IWN5000_SCHED_QCHAIN_SEL, 0xfffef); 8014 iwn_prph_write(sc, IWN5000_SCHED_AGGR_SEL, 0); 8015 8016 for (qid = 0; qid < IWN5000_NTXQUEUES; qid++) { 8017 iwn_prph_write(sc, IWN5000_SCHED_QUEUE_RDPTR(qid), 0); 8018 IWN_WRITE(sc, IWN_HBUS_TARG_WRPTR, qid << 8 | 0); 8019 8020 iwn_mem_write(sc, sc->sched_base + 8021 IWN5000_SCHED_QUEUE_OFFSET(qid), 0); 8022 /* Set scheduler window size and frame limit. */ 8023 iwn_mem_write(sc, sc->sched_base + 8024 IWN5000_SCHED_QUEUE_OFFSET(qid) + 4, 8025 IWN_SCHED_LIMIT << 16 | IWN_SCHED_WINSZ); 8026 } 8027 8028 /* Enable interrupts for all our 20 queues. */ 8029 iwn_prph_write(sc, IWN5000_SCHED_INTR_MASK, 0xfffff); 8030 /* Identify TX FIFO rings (0-7). */ 8031 iwn_prph_write(sc, IWN5000_SCHED_TXFACT, 0xff); 8032 8033 /* Mark TX rings (4 EDCA + cmd + 2 HCCA) as active. */ 8034 if (sc->sc_flags & IWN_FLAG_PAN_SUPPORT) { 8035 /* Mark TX rings as active. */ 8036 for (qid = 0; qid < 11; qid++) { 8037 static uint8_t qid2fifo[] = { 3, 2, 1, 0, 0, 4, 2, 5, 4, 7, 5 }; 8038 iwn_prph_write(sc, IWN5000_SCHED_QUEUE_STATUS(qid), 8039 IWN5000_TXQ_STATUS_ACTIVE | qid2fifo[qid]); 8040 } 8041 } else { 8042 /* Mark TX rings (4 EDCA + cmd + 2 HCCA) as active. */ 8043 for (qid = 0; qid < 7; qid++) { 8044 static uint8_t qid2fifo[] = { 3, 2, 1, 0, 7, 5, 6 }; 8045 iwn_prph_write(sc, IWN5000_SCHED_QUEUE_STATUS(qid), 8046 IWN5000_TXQ_STATUS_ACTIVE | qid2fifo[qid]); 8047 } 8048 } 8049 iwn_nic_unlock(sc); 8050 8051 /* Configure WiMAX coexistence for combo adapters. */ 8052 error = iwn5000_send_wimax_coex(sc); 8053 if (error != 0) { 8054 device_printf(sc->sc_dev, 8055 "%s: could not configure WiMAX coexistence, error %d\n", 8056 __func__, error); 8057 return error; 8058 } 8059 if (sc->hw_type != IWN_HW_REV_TYPE_5150) { 8060 /* Perform crystal calibration. */ 8061 error = iwn5000_crystal_calib(sc); 8062 if (error != 0) { 8063 device_printf(sc->sc_dev, 8064 "%s: crystal calibration failed, error %d\n", 8065 __func__, error); 8066 return error; 8067 } 8068 } 8069 if (!(sc->sc_flags & IWN_FLAG_CALIB_DONE)) { 8070 /* Query calibration from the initialization firmware. */ 8071 if ((error = iwn5000_query_calibration(sc)) != 0) { 8072 device_printf(sc->sc_dev, 8073 "%s: could not query calibration, error %d\n", 8074 __func__, error); 8075 return error; 8076 } 8077 /* 8078 * We have the calibration results now, reboot with the 8079 * runtime firmware (call ourselves recursively!) 8080 */ 8081 iwn_hw_stop(sc); 8082 error = iwn_hw_init(sc); 8083 } else { 8084 /* Send calibration results to runtime firmware. */ 8085 error = iwn5000_send_calibration(sc); 8086 } 8087 8088 DPRINTF(sc, IWN_DEBUG_TRACE, "->%s: end\n",__func__); 8089 8090 return error; 8091 } 8092 8093 /* 8094 * The firmware boot code is small and is intended to be copied directly into 8095 * the NIC internal memory (no DMA transfer). 8096 */ 8097 static int 8098 iwn4965_load_bootcode(struct iwn_softc *sc, const uint8_t *ucode, int size) 8099 { 8100 int error, ntries; 8101 8102 size /= sizeof (uint32_t); 8103 8104 if ((error = iwn_nic_lock(sc)) != 0) 8105 return error; 8106 8107 /* Copy microcode image into NIC memory. */ 8108 iwn_prph_write_region_4(sc, IWN_BSM_SRAM_BASE, 8109 (const uint32_t *)ucode, size); 8110 8111 iwn_prph_write(sc, IWN_BSM_WR_MEM_SRC, 0); 8112 iwn_prph_write(sc, IWN_BSM_WR_MEM_DST, IWN_FW_TEXT_BASE); 8113 iwn_prph_write(sc, IWN_BSM_WR_DWCOUNT, size); 8114 8115 /* Start boot load now. */ 8116 iwn_prph_write(sc, IWN_BSM_WR_CTRL, IWN_BSM_WR_CTRL_START); 8117 8118 /* Wait for transfer to complete. */ 8119 for (ntries = 0; ntries < 1000; ntries++) { 8120 if (!(iwn_prph_read(sc, IWN_BSM_WR_CTRL) & 8121 IWN_BSM_WR_CTRL_START)) 8122 break; 8123 DELAY(10); 8124 } 8125 if (ntries == 1000) { 8126 device_printf(sc->sc_dev, "%s: could not load boot firmware\n", 8127 __func__); 8128 iwn_nic_unlock(sc); 8129 return ETIMEDOUT; 8130 } 8131 8132 /* Enable boot after power up. */ 8133 iwn_prph_write(sc, IWN_BSM_WR_CTRL, IWN_BSM_WR_CTRL_START_EN); 8134 8135 iwn_nic_unlock(sc); 8136 return 0; 8137 } 8138 8139 static int 8140 iwn4965_load_firmware(struct iwn_softc *sc) 8141 { 8142 struct iwn_fw_info *fw = &sc->fw; 8143 struct iwn_dma_info *dma = &sc->fw_dma; 8144 int error; 8145 8146 /* Copy initialization sections into pre-allocated DMA-safe memory. */ 8147 memcpy(dma->vaddr, fw->init.data, fw->init.datasz); 8148 bus_dmamap_sync(dma->tag, dma->map, BUS_DMASYNC_PREWRITE); 8149 memcpy(dma->vaddr + IWN4965_FW_DATA_MAXSZ, 8150 fw->init.text, fw->init.textsz); 8151 bus_dmamap_sync(dma->tag, dma->map, BUS_DMASYNC_PREWRITE); 8152 8153 /* Tell adapter where to find initialization sections. */ 8154 if ((error = iwn_nic_lock(sc)) != 0) 8155 return error; 8156 iwn_prph_write(sc, IWN_BSM_DRAM_DATA_ADDR, dma->paddr >> 4); 8157 iwn_prph_write(sc, IWN_BSM_DRAM_DATA_SIZE, fw->init.datasz); 8158 iwn_prph_write(sc, IWN_BSM_DRAM_TEXT_ADDR, 8159 (dma->paddr + IWN4965_FW_DATA_MAXSZ) >> 4); 8160 iwn_prph_write(sc, IWN_BSM_DRAM_TEXT_SIZE, fw->init.textsz); 8161 iwn_nic_unlock(sc); 8162 8163 /* Load firmware boot code. */ 8164 error = iwn4965_load_bootcode(sc, fw->boot.text, fw->boot.textsz); 8165 if (error != 0) { 8166 device_printf(sc->sc_dev, "%s: could not load boot firmware\n", 8167 __func__); 8168 return error; 8169 } 8170 /* Now press "execute". */ 8171 IWN_WRITE(sc, IWN_RESET, 0); 8172 8173 /* Wait at most one second for first alive notification. */ 8174 if ((error = msleep(sc, &sc->sc_mtx, PCATCH, "iwninit", hz)) != 0) { 8175 device_printf(sc->sc_dev, 8176 "%s: timeout waiting for adapter to initialize, error %d\n", 8177 __func__, error); 8178 return error; 8179 } 8180 8181 /* Retrieve current temperature for initial TX power calibration. */ 8182 sc->rawtemp = sc->ucode_info.temp[3].chan20MHz; 8183 sc->temp = iwn4965_get_temperature(sc); 8184 8185 /* Copy runtime sections into pre-allocated DMA-safe memory. */ 8186 memcpy(dma->vaddr, fw->main.data, fw->main.datasz); 8187 bus_dmamap_sync(dma->tag, dma->map, BUS_DMASYNC_PREWRITE); 8188 memcpy(dma->vaddr + IWN4965_FW_DATA_MAXSZ, 8189 fw->main.text, fw->main.textsz); 8190 bus_dmamap_sync(dma->tag, dma->map, BUS_DMASYNC_PREWRITE); 8191 8192 /* Tell adapter where to find runtime sections. */ 8193 if ((error = iwn_nic_lock(sc)) != 0) 8194 return error; 8195 iwn_prph_write(sc, IWN_BSM_DRAM_DATA_ADDR, dma->paddr >> 4); 8196 iwn_prph_write(sc, IWN_BSM_DRAM_DATA_SIZE, fw->main.datasz); 8197 iwn_prph_write(sc, IWN_BSM_DRAM_TEXT_ADDR, 8198 (dma->paddr + IWN4965_FW_DATA_MAXSZ) >> 4); 8199 iwn_prph_write(sc, IWN_BSM_DRAM_TEXT_SIZE, 8200 IWN_FW_UPDATED | fw->main.textsz); 8201 iwn_nic_unlock(sc); 8202 8203 return 0; 8204 } 8205 8206 static int 8207 iwn5000_load_firmware_section(struct iwn_softc *sc, uint32_t dst, 8208 const uint8_t *section, int size) 8209 { 8210 struct iwn_dma_info *dma = &sc->fw_dma; 8211 int error; 8212 8213 DPRINTF(sc, IWN_DEBUG_TRACE, "->Doing %s\n", __func__); 8214 8215 /* Copy firmware section into pre-allocated DMA-safe memory. */ 8216 memcpy(dma->vaddr, section, size); 8217 bus_dmamap_sync(dma->tag, dma->map, BUS_DMASYNC_PREWRITE); 8218 8219 if ((error = iwn_nic_lock(sc)) != 0) 8220 return error; 8221 8222 IWN_WRITE(sc, IWN_FH_TX_CONFIG(IWN_SRVC_DMACHNL), 8223 IWN_FH_TX_CONFIG_DMA_PAUSE); 8224 8225 IWN_WRITE(sc, IWN_FH_SRAM_ADDR(IWN_SRVC_DMACHNL), dst); 8226 IWN_WRITE(sc, IWN_FH_TFBD_CTRL0(IWN_SRVC_DMACHNL), 8227 IWN_LOADDR(dma->paddr)); 8228 IWN_WRITE(sc, IWN_FH_TFBD_CTRL1(IWN_SRVC_DMACHNL), 8229 IWN_HIADDR(dma->paddr) << 28 | size); 8230 IWN_WRITE(sc, IWN_FH_TXBUF_STATUS(IWN_SRVC_DMACHNL), 8231 IWN_FH_TXBUF_STATUS_TBNUM(1) | 8232 IWN_FH_TXBUF_STATUS_TBIDX(1) | 8233 IWN_FH_TXBUF_STATUS_TFBD_VALID); 8234 8235 /* Kick Flow Handler to start DMA transfer. */ 8236 IWN_WRITE(sc, IWN_FH_TX_CONFIG(IWN_SRVC_DMACHNL), 8237 IWN_FH_TX_CONFIG_DMA_ENA | IWN_FH_TX_CONFIG_CIRQ_HOST_ENDTFD); 8238 8239 iwn_nic_unlock(sc); 8240 8241 /* Wait at most five seconds for FH DMA transfer to complete. */ 8242 return msleep(sc, &sc->sc_mtx, PCATCH, "iwninit", 5 * hz); 8243 } 8244 8245 static int 8246 iwn5000_load_firmware(struct iwn_softc *sc) 8247 { 8248 struct iwn_fw_part *fw; 8249 int error; 8250 8251 DPRINTF(sc, IWN_DEBUG_TRACE, "->Doing %s\n", __func__); 8252 8253 /* Load the initialization firmware on first boot only. */ 8254 fw = (sc->sc_flags & IWN_FLAG_CALIB_DONE) ? 8255 &sc->fw.main : &sc->fw.init; 8256 8257 error = iwn5000_load_firmware_section(sc, IWN_FW_TEXT_BASE, 8258 fw->text, fw->textsz); 8259 if (error != 0) { 8260 device_printf(sc->sc_dev, 8261 "%s: could not load firmware %s section, error %d\n", 8262 __func__, ".text", error); 8263 return error; 8264 } 8265 error = iwn5000_load_firmware_section(sc, IWN_FW_DATA_BASE, 8266 fw->data, fw->datasz); 8267 if (error != 0) { 8268 device_printf(sc->sc_dev, 8269 "%s: could not load firmware %s section, error %d\n", 8270 __func__, ".data", error); 8271 return error; 8272 } 8273 8274 /* Now press "execute". */ 8275 IWN_WRITE(sc, IWN_RESET, 0); 8276 return 0; 8277 } 8278 8279 /* 8280 * Extract text and data sections from a legacy firmware image. 8281 */ 8282 static int 8283 iwn_read_firmware_leg(struct iwn_softc *sc, struct iwn_fw_info *fw) 8284 { 8285 const uint32_t *ptr; 8286 size_t hdrlen = 24; 8287 uint32_t rev; 8288 8289 ptr = (const uint32_t *)fw->data; 8290 rev = le32toh(*ptr++); 8291 8292 sc->ucode_rev = rev; 8293 8294 /* Check firmware API version. */ 8295 if (IWN_FW_API(rev) <= 1) { 8296 device_printf(sc->sc_dev, 8297 "%s: bad firmware, need API version >=2\n", __func__); 8298 return EINVAL; 8299 } 8300 if (IWN_FW_API(rev) >= 3) { 8301 /* Skip build number (version 2 header). */ 8302 hdrlen += 4; 8303 ptr++; 8304 } 8305 if (fw->size < hdrlen) { 8306 device_printf(sc->sc_dev, "%s: firmware too short: %zu bytes\n", 8307 __func__, fw->size); 8308 return EINVAL; 8309 } 8310 fw->main.textsz = le32toh(*ptr++); 8311 fw->main.datasz = le32toh(*ptr++); 8312 fw->init.textsz = le32toh(*ptr++); 8313 fw->init.datasz = le32toh(*ptr++); 8314 fw->boot.textsz = le32toh(*ptr++); 8315 8316 /* Check that all firmware sections fit. */ 8317 if (fw->size < hdrlen + fw->main.textsz + fw->main.datasz + 8318 fw->init.textsz + fw->init.datasz + fw->boot.textsz) { 8319 device_printf(sc->sc_dev, "%s: firmware too short: %zu bytes\n", 8320 __func__, fw->size); 8321 return EINVAL; 8322 } 8323 8324 /* Get pointers to firmware sections. */ 8325 fw->main.text = (const uint8_t *)ptr; 8326 fw->main.data = fw->main.text + fw->main.textsz; 8327 fw->init.text = fw->main.data + fw->main.datasz; 8328 fw->init.data = fw->init.text + fw->init.textsz; 8329 fw->boot.text = fw->init.data + fw->init.datasz; 8330 return 0; 8331 } 8332 8333 /* 8334 * Extract text and data sections from a TLV firmware image. 8335 */ 8336 static int 8337 iwn_read_firmware_tlv(struct iwn_softc *sc, struct iwn_fw_info *fw, 8338 uint16_t alt) 8339 { 8340 const struct iwn_fw_tlv_hdr *hdr; 8341 const struct iwn_fw_tlv *tlv; 8342 const uint8_t *ptr, *end; 8343 uint64_t altmask; 8344 uint32_t len, tmp; 8345 8346 if (fw->size < sizeof (*hdr)) { 8347 device_printf(sc->sc_dev, "%s: firmware too short: %zu bytes\n", 8348 __func__, fw->size); 8349 return EINVAL; 8350 } 8351 hdr = (const struct iwn_fw_tlv_hdr *)fw->data; 8352 if (hdr->signature != htole32(IWN_FW_SIGNATURE)) { 8353 device_printf(sc->sc_dev, "%s: bad firmware signature 0x%08x\n", 8354 __func__, le32toh(hdr->signature)); 8355 return EINVAL; 8356 } 8357 DPRINTF(sc, IWN_DEBUG_RESET, "FW: \"%.64s\", build 0x%x\n", hdr->descr, 8358 le32toh(hdr->build)); 8359 sc->ucode_rev = le32toh(hdr->rev); 8360 8361 /* 8362 * Select the closest supported alternative that is less than 8363 * or equal to the specified one. 8364 */ 8365 altmask = le64toh(hdr->altmask); 8366 while (alt > 0 && !(altmask & (1ULL << alt))) 8367 alt--; /* Downgrade. */ 8368 DPRINTF(sc, IWN_DEBUG_RESET, "using alternative %d\n", alt); 8369 8370 ptr = (const uint8_t *)(hdr + 1); 8371 end = (const uint8_t *)(fw->data + fw->size); 8372 8373 /* Parse type-length-value fields. */ 8374 while (ptr + sizeof (*tlv) <= end) { 8375 tlv = (const struct iwn_fw_tlv *)ptr; 8376 len = le32toh(tlv->len); 8377 8378 ptr += sizeof (*tlv); 8379 if (ptr + len > end) { 8380 device_printf(sc->sc_dev, 8381 "%s: firmware too short: %zu bytes\n", __func__, 8382 fw->size); 8383 return EINVAL; 8384 } 8385 /* Skip other alternatives. */ 8386 if (tlv->alt != 0 && tlv->alt != htole16(alt)) 8387 goto next; 8388 8389 switch (le16toh(tlv->type)) { 8390 case IWN_FW_TLV_MAIN_TEXT: 8391 fw->main.text = ptr; 8392 fw->main.textsz = len; 8393 break; 8394 case IWN_FW_TLV_MAIN_DATA: 8395 fw->main.data = ptr; 8396 fw->main.datasz = len; 8397 break; 8398 case IWN_FW_TLV_INIT_TEXT: 8399 fw->init.text = ptr; 8400 fw->init.textsz = len; 8401 break; 8402 case IWN_FW_TLV_INIT_DATA: 8403 fw->init.data = ptr; 8404 fw->init.datasz = len; 8405 break; 8406 case IWN_FW_TLV_BOOT_TEXT: 8407 fw->boot.text = ptr; 8408 fw->boot.textsz = len; 8409 break; 8410 case IWN_FW_TLV_ENH_SENS: 8411 if (!len) 8412 sc->sc_flags |= IWN_FLAG_ENH_SENS; 8413 break; 8414 case IWN_FW_TLV_PHY_CALIB: 8415 tmp = le32toh(*ptr); 8416 if (tmp < 253) { 8417 sc->reset_noise_gain = tmp; 8418 sc->noise_gain = tmp + 1; 8419 } 8420 break; 8421 case IWN_FW_TLV_PAN: 8422 sc->sc_flags |= IWN_FLAG_PAN_SUPPORT; 8423 DPRINTF(sc, IWN_DEBUG_RESET, 8424 "PAN Support found: %d\n", 1); 8425 break; 8426 case IWN_FW_TLV_FLAGS: 8427 if (len < sizeof(uint32_t)) 8428 break; 8429 if (len % sizeof(uint32_t)) 8430 break; 8431 sc->tlv_feature_flags = le32toh(*ptr); 8432 DPRINTF(sc, IWN_DEBUG_RESET, 8433 "%s: feature: 0x%08x\n", 8434 __func__, 8435 sc->tlv_feature_flags); 8436 break; 8437 case IWN_FW_TLV_PBREQ_MAXLEN: 8438 case IWN_FW_TLV_RUNT_EVTLOG_PTR: 8439 case IWN_FW_TLV_RUNT_EVTLOG_SIZE: 8440 case IWN_FW_TLV_RUNT_ERRLOG_PTR: 8441 case IWN_FW_TLV_INIT_EVTLOG_PTR: 8442 case IWN_FW_TLV_INIT_EVTLOG_SIZE: 8443 case IWN_FW_TLV_INIT_ERRLOG_PTR: 8444 case IWN_FW_TLV_WOWLAN_INST: 8445 case IWN_FW_TLV_WOWLAN_DATA: 8446 DPRINTF(sc, IWN_DEBUG_RESET, 8447 "TLV type %d recognized but not handled\n", 8448 le16toh(tlv->type)); 8449 break; 8450 default: 8451 DPRINTF(sc, IWN_DEBUG_RESET, 8452 "TLV type %d not handled\n", le16toh(tlv->type)); 8453 break; 8454 } 8455 next: /* TLV fields are 32-bit aligned. */ 8456 ptr += (len + 3) & ~3; 8457 } 8458 return 0; 8459 } 8460 8461 static int 8462 iwn_read_firmware(struct iwn_softc *sc) 8463 { 8464 struct iwn_fw_info *fw = &sc->fw; 8465 int error; 8466 8467 DPRINTF(sc, IWN_DEBUG_TRACE, "->Doing %s\n", __func__); 8468 8469 IWN_UNLOCK(sc); 8470 8471 memset(fw, 0, sizeof (*fw)); 8472 8473 /* Read firmware image from filesystem. */ 8474 sc->fw_fp = firmware_get(sc->fwname); 8475 if (sc->fw_fp == NULL) { 8476 device_printf(sc->sc_dev, "%s: could not read firmware %s\n", 8477 __func__, sc->fwname); 8478 IWN_LOCK(sc); 8479 return EINVAL; 8480 } 8481 IWN_LOCK(sc); 8482 8483 fw->size = sc->fw_fp->datasize; 8484 fw->data = (const uint8_t *)sc->fw_fp->data; 8485 if (fw->size < sizeof (uint32_t)) { 8486 device_printf(sc->sc_dev, "%s: firmware too short: %zu bytes\n", 8487 __func__, fw->size); 8488 error = EINVAL; 8489 goto fail; 8490 } 8491 8492 /* Retrieve text and data sections. */ 8493 if (*(const uint32_t *)fw->data != 0) /* Legacy image. */ 8494 error = iwn_read_firmware_leg(sc, fw); 8495 else 8496 error = iwn_read_firmware_tlv(sc, fw, 1); 8497 if (error != 0) { 8498 device_printf(sc->sc_dev, 8499 "%s: could not read firmware sections, error %d\n", 8500 __func__, error); 8501 goto fail; 8502 } 8503 8504 device_printf(sc->sc_dev, "%s: ucode rev=0x%08x\n", __func__, sc->ucode_rev); 8505 8506 /* Make sure text and data sections fit in hardware memory. */ 8507 if (fw->main.textsz > sc->fw_text_maxsz || 8508 fw->main.datasz > sc->fw_data_maxsz || 8509 fw->init.textsz > sc->fw_text_maxsz || 8510 fw->init.datasz > sc->fw_data_maxsz || 8511 fw->boot.textsz > IWN_FW_BOOT_TEXT_MAXSZ || 8512 (fw->boot.textsz & 3) != 0) { 8513 device_printf(sc->sc_dev, "%s: firmware sections too large\n", 8514 __func__); 8515 error = EINVAL; 8516 goto fail; 8517 } 8518 8519 /* We can proceed with loading the firmware. */ 8520 return 0; 8521 8522 fail: iwn_unload_firmware(sc); 8523 return error; 8524 } 8525 8526 static void 8527 iwn_unload_firmware(struct iwn_softc *sc) 8528 { 8529 firmware_put(sc->fw_fp, FIRMWARE_UNLOAD); 8530 sc->fw_fp = NULL; 8531 } 8532 8533 static int 8534 iwn_clock_wait(struct iwn_softc *sc) 8535 { 8536 int ntries; 8537 8538 /* Set "initialization complete" bit. */ 8539 IWN_SETBITS(sc, IWN_GP_CNTRL, IWN_GP_CNTRL_INIT_DONE); 8540 8541 /* Wait for clock stabilization. */ 8542 for (ntries = 0; ntries < 2500; ntries++) { 8543 if (IWN_READ(sc, IWN_GP_CNTRL) & IWN_GP_CNTRL_MAC_CLOCK_READY) 8544 return 0; 8545 DELAY(10); 8546 } 8547 device_printf(sc->sc_dev, 8548 "%s: timeout waiting for clock stabilization\n", __func__); 8549 return ETIMEDOUT; 8550 } 8551 8552 static int 8553 iwn_apm_init(struct iwn_softc *sc) 8554 { 8555 uint32_t reg; 8556 int error; 8557 8558 DPRINTF(sc, IWN_DEBUG_TRACE, "->Doing %s\n", __func__); 8559 8560 /* Disable L0s exit timer (NMI bug workaround). */ 8561 IWN_SETBITS(sc, IWN_GIO_CHICKEN, IWN_GIO_CHICKEN_DIS_L0S_TIMER); 8562 /* Don't wait for ICH L0s (ICH bug workaround). */ 8563 IWN_SETBITS(sc, IWN_GIO_CHICKEN, IWN_GIO_CHICKEN_L1A_NO_L0S_RX); 8564 8565 /* Set FH wait threshold to max (HW bug under stress workaround). */ 8566 IWN_SETBITS(sc, IWN_DBG_HPET_MEM, 0xffff0000); 8567 8568 /* Enable HAP INTA to move adapter from L1a to L0s. */ 8569 IWN_SETBITS(sc, IWN_HW_IF_CONFIG, IWN_HW_IF_CONFIG_HAP_WAKE_L1A); 8570 8571 /* Retrieve PCIe Active State Power Management (ASPM). */ 8572 reg = pci_read_config(sc->sc_dev, sc->sc_cap_off + PCIER_LINK_CTL, 4); 8573 /* Workaround for HW instability in PCIe L0->L0s->L1 transition. */ 8574 if (reg & PCIEM_LINK_CTL_ASPMC_L1) /* L1 Entry enabled. */ 8575 IWN_SETBITS(sc, IWN_GIO, IWN_GIO_L0S_ENA); 8576 else 8577 IWN_CLRBITS(sc, IWN_GIO, IWN_GIO_L0S_ENA); 8578 8579 if (sc->base_params->pll_cfg_val) 8580 IWN_SETBITS(sc, IWN_ANA_PLL, sc->base_params->pll_cfg_val); 8581 8582 /* Wait for clock stabilization before accessing prph. */ 8583 if ((error = iwn_clock_wait(sc)) != 0) 8584 return error; 8585 8586 if ((error = iwn_nic_lock(sc)) != 0) 8587 return error; 8588 if (sc->hw_type == IWN_HW_REV_TYPE_4965) { 8589 /* Enable DMA and BSM (Bootstrap State Machine). */ 8590 iwn_prph_write(sc, IWN_APMG_CLK_EN, 8591 IWN_APMG_CLK_CTRL_DMA_CLK_RQT | 8592 IWN_APMG_CLK_CTRL_BSM_CLK_RQT); 8593 } else { 8594 /* Enable DMA. */ 8595 iwn_prph_write(sc, IWN_APMG_CLK_EN, 8596 IWN_APMG_CLK_CTRL_DMA_CLK_RQT); 8597 } 8598 DELAY(20); 8599 /* Disable L1-Active. */ 8600 iwn_prph_setbits(sc, IWN_APMG_PCI_STT, IWN_APMG_PCI_STT_L1A_DIS); 8601 iwn_nic_unlock(sc); 8602 8603 return 0; 8604 } 8605 8606 static void 8607 iwn_apm_stop_master(struct iwn_softc *sc) 8608 { 8609 int ntries; 8610 8611 /* Stop busmaster DMA activity. */ 8612 IWN_SETBITS(sc, IWN_RESET, IWN_RESET_STOP_MASTER); 8613 for (ntries = 0; ntries < 100; ntries++) { 8614 if (IWN_READ(sc, IWN_RESET) & IWN_RESET_MASTER_DISABLED) 8615 return; 8616 DELAY(10); 8617 } 8618 device_printf(sc->sc_dev, "%s: timeout waiting for master\n", __func__); 8619 } 8620 8621 static void 8622 iwn_apm_stop(struct iwn_softc *sc) 8623 { 8624 iwn_apm_stop_master(sc); 8625 8626 /* Reset the entire device. */ 8627 IWN_SETBITS(sc, IWN_RESET, IWN_RESET_SW); 8628 DELAY(10); 8629 /* Clear "initialization complete" bit. */ 8630 IWN_CLRBITS(sc, IWN_GP_CNTRL, IWN_GP_CNTRL_INIT_DONE); 8631 } 8632 8633 static int 8634 iwn4965_nic_config(struct iwn_softc *sc) 8635 { 8636 DPRINTF(sc, IWN_DEBUG_TRACE, "->Doing %s\n", __func__); 8637 8638 if (IWN_RFCFG_TYPE(sc->rfcfg) == 1) { 8639 /* 8640 * I don't believe this to be correct but this is what the 8641 * vendor driver is doing. Probably the bits should not be 8642 * shifted in IWN_RFCFG_*. 8643 */ 8644 IWN_SETBITS(sc, IWN_HW_IF_CONFIG, 8645 IWN_RFCFG_TYPE(sc->rfcfg) | 8646 IWN_RFCFG_STEP(sc->rfcfg) | 8647 IWN_RFCFG_DASH(sc->rfcfg)); 8648 } 8649 IWN_SETBITS(sc, IWN_HW_IF_CONFIG, 8650 IWN_HW_IF_CONFIG_RADIO_SI | IWN_HW_IF_CONFIG_MAC_SI); 8651 return 0; 8652 } 8653 8654 static int 8655 iwn5000_nic_config(struct iwn_softc *sc) 8656 { 8657 uint32_t tmp; 8658 int error; 8659 8660 DPRINTF(sc, IWN_DEBUG_TRACE, "->Doing %s\n", __func__); 8661 8662 if (IWN_RFCFG_TYPE(sc->rfcfg) < 3) { 8663 IWN_SETBITS(sc, IWN_HW_IF_CONFIG, 8664 IWN_RFCFG_TYPE(sc->rfcfg) | 8665 IWN_RFCFG_STEP(sc->rfcfg) | 8666 IWN_RFCFG_DASH(sc->rfcfg)); 8667 } 8668 IWN_SETBITS(sc, IWN_HW_IF_CONFIG, 8669 IWN_HW_IF_CONFIG_RADIO_SI | IWN_HW_IF_CONFIG_MAC_SI); 8670 8671 if ((error = iwn_nic_lock(sc)) != 0) 8672 return error; 8673 iwn_prph_setbits(sc, IWN_APMG_PS, IWN_APMG_PS_EARLY_PWROFF_DIS); 8674 8675 if (sc->hw_type == IWN_HW_REV_TYPE_1000) { 8676 /* 8677 * Select first Switching Voltage Regulator (1.32V) to 8678 * solve a stability issue related to noisy DC2DC line 8679 * in the silicon of 1000 Series. 8680 */ 8681 tmp = iwn_prph_read(sc, IWN_APMG_DIGITAL_SVR); 8682 tmp &= ~IWN_APMG_DIGITAL_SVR_VOLTAGE_MASK; 8683 tmp |= IWN_APMG_DIGITAL_SVR_VOLTAGE_1_32; 8684 iwn_prph_write(sc, IWN_APMG_DIGITAL_SVR, tmp); 8685 } 8686 iwn_nic_unlock(sc); 8687 8688 if (sc->sc_flags & IWN_FLAG_INTERNAL_PA) { 8689 /* Use internal power amplifier only. */ 8690 IWN_WRITE(sc, IWN_GP_DRIVER, IWN_GP_DRIVER_RADIO_2X2_IPA); 8691 } 8692 if (sc->base_params->additional_nic_config && sc->calib_ver >= 6) { 8693 /* Indicate that ROM calibration version is >=6. */ 8694 IWN_SETBITS(sc, IWN_GP_DRIVER, IWN_GP_DRIVER_CALIB_VER6); 8695 } 8696 if (sc->base_params->additional_gp_drv_bit) 8697 IWN_SETBITS(sc, IWN_GP_DRIVER, 8698 sc->base_params->additional_gp_drv_bit); 8699 return 0; 8700 } 8701 8702 /* 8703 * Take NIC ownership over Intel Active Management Technology (AMT). 8704 */ 8705 static int 8706 iwn_hw_prepare(struct iwn_softc *sc) 8707 { 8708 int ntries; 8709 8710 DPRINTF(sc, IWN_DEBUG_TRACE, "->Doing %s\n", __func__); 8711 8712 /* Check if hardware is ready. */ 8713 IWN_SETBITS(sc, IWN_HW_IF_CONFIG, IWN_HW_IF_CONFIG_NIC_READY); 8714 for (ntries = 0; ntries < 5; ntries++) { 8715 if (IWN_READ(sc, IWN_HW_IF_CONFIG) & 8716 IWN_HW_IF_CONFIG_NIC_READY) 8717 return 0; 8718 DELAY(10); 8719 } 8720 8721 /* Hardware not ready, force into ready state. */ 8722 IWN_SETBITS(sc, IWN_HW_IF_CONFIG, IWN_HW_IF_CONFIG_PREPARE); 8723 for (ntries = 0; ntries < 15000; ntries++) { 8724 if (!(IWN_READ(sc, IWN_HW_IF_CONFIG) & 8725 IWN_HW_IF_CONFIG_PREPARE_DONE)) 8726 break; 8727 DELAY(10); 8728 } 8729 if (ntries == 15000) 8730 return ETIMEDOUT; 8731 8732 /* Hardware should be ready now. */ 8733 IWN_SETBITS(sc, IWN_HW_IF_CONFIG, IWN_HW_IF_CONFIG_NIC_READY); 8734 for (ntries = 0; ntries < 5; ntries++) { 8735 if (IWN_READ(sc, IWN_HW_IF_CONFIG) & 8736 IWN_HW_IF_CONFIG_NIC_READY) 8737 return 0; 8738 DELAY(10); 8739 } 8740 return ETIMEDOUT; 8741 } 8742 8743 static int 8744 iwn_hw_init(struct iwn_softc *sc) 8745 { 8746 struct iwn_ops *ops = &sc->ops; 8747 int error, chnl, qid; 8748 8749 DPRINTF(sc, IWN_DEBUG_TRACE, "->%s begin\n", __func__); 8750 8751 /* Clear pending interrupts. */ 8752 IWN_WRITE(sc, IWN_INT, 0xffffffff); 8753 8754 if ((error = iwn_apm_init(sc)) != 0) { 8755 device_printf(sc->sc_dev, 8756 "%s: could not power ON adapter, error %d\n", __func__, 8757 error); 8758 return error; 8759 } 8760 8761 /* Select VMAIN power source. */ 8762 if ((error = iwn_nic_lock(sc)) != 0) 8763 return error; 8764 iwn_prph_clrbits(sc, IWN_APMG_PS, IWN_APMG_PS_PWR_SRC_MASK); 8765 iwn_nic_unlock(sc); 8766 8767 /* Perform adapter-specific initialization. */ 8768 if ((error = ops->nic_config(sc)) != 0) 8769 return error; 8770 8771 /* Initialize RX ring. */ 8772 if ((error = iwn_nic_lock(sc)) != 0) 8773 return error; 8774 IWN_WRITE(sc, IWN_FH_RX_CONFIG, 0); 8775 IWN_WRITE(sc, IWN_FH_RX_WPTR, 0); 8776 /* Set physical address of RX ring (256-byte aligned). */ 8777 IWN_WRITE(sc, IWN_FH_RX_BASE, sc->rxq.desc_dma.paddr >> 8); 8778 /* Set physical address of RX status (16-byte aligned). */ 8779 IWN_WRITE(sc, IWN_FH_STATUS_WPTR, sc->rxq.stat_dma.paddr >> 4); 8780 /* Enable RX. */ 8781 IWN_WRITE(sc, IWN_FH_RX_CONFIG, 8782 IWN_FH_RX_CONFIG_ENA | 8783 IWN_FH_RX_CONFIG_IGN_RXF_EMPTY | /* HW bug workaround */ 8784 IWN_FH_RX_CONFIG_IRQ_DST_HOST | 8785 IWN_FH_RX_CONFIG_SINGLE_FRAME | 8786 IWN_FH_RX_CONFIG_RB_TIMEOUT(0) | 8787 IWN_FH_RX_CONFIG_NRBD(IWN_RX_RING_COUNT_LOG)); 8788 iwn_nic_unlock(sc); 8789 IWN_WRITE(sc, IWN_FH_RX_WPTR, (IWN_RX_RING_COUNT - 1) & ~7); 8790 8791 if ((error = iwn_nic_lock(sc)) != 0) 8792 return error; 8793 8794 /* Initialize TX scheduler. */ 8795 iwn_prph_write(sc, sc->sched_txfact_addr, 0); 8796 8797 /* Set physical address of "keep warm" page (16-byte aligned). */ 8798 IWN_WRITE(sc, IWN_FH_KW_ADDR, sc->kw_dma.paddr >> 4); 8799 8800 /* Initialize TX rings. */ 8801 for (qid = 0; qid < sc->ntxqs; qid++) { 8802 struct iwn_tx_ring *txq = &sc->txq[qid]; 8803 8804 /* Set physical address of TX ring (256-byte aligned). */ 8805 IWN_WRITE(sc, IWN_FH_CBBC_QUEUE(qid), 8806 txq->desc_dma.paddr >> 8); 8807 } 8808 iwn_nic_unlock(sc); 8809 8810 /* Enable DMA channels. */ 8811 for (chnl = 0; chnl < sc->ndmachnls; chnl++) { 8812 IWN_WRITE(sc, IWN_FH_TX_CONFIG(chnl), 8813 IWN_FH_TX_CONFIG_DMA_ENA | 8814 IWN_FH_TX_CONFIG_DMA_CREDIT_ENA); 8815 } 8816 8817 /* Clear "radio off" and "commands blocked" bits. */ 8818 IWN_WRITE(sc, IWN_UCODE_GP1_CLR, IWN_UCODE_GP1_RFKILL); 8819 IWN_WRITE(sc, IWN_UCODE_GP1_CLR, IWN_UCODE_GP1_CMD_BLOCKED); 8820 8821 /* Clear pending interrupts. */ 8822 IWN_WRITE(sc, IWN_INT, 0xffffffff); 8823 /* Enable interrupt coalescing. */ 8824 IWN_WRITE(sc, IWN_INT_COALESCING, 512 / 8); 8825 /* Enable interrupts. */ 8826 IWN_WRITE(sc, IWN_INT_MASK, sc->int_mask); 8827 8828 /* _Really_ make sure "radio off" bit is cleared! */ 8829 IWN_WRITE(sc, IWN_UCODE_GP1_CLR, IWN_UCODE_GP1_RFKILL); 8830 IWN_WRITE(sc, IWN_UCODE_GP1_CLR, IWN_UCODE_GP1_RFKILL); 8831 8832 /* Enable shadow registers. */ 8833 if (sc->base_params->shadow_reg_enable) 8834 IWN_SETBITS(sc, IWN_SHADOW_REG_CTRL, 0x800fffff); 8835 8836 if ((error = ops->load_firmware(sc)) != 0) { 8837 device_printf(sc->sc_dev, 8838 "%s: could not load firmware, error %d\n", __func__, 8839 error); 8840 return error; 8841 } 8842 /* Wait at most one second for firmware alive notification. */ 8843 if ((error = msleep(sc, &sc->sc_mtx, PCATCH, "iwninit", hz)) != 0) { 8844 device_printf(sc->sc_dev, 8845 "%s: timeout waiting for adapter to initialize, error %d\n", 8846 __func__, error); 8847 return error; 8848 } 8849 /* Do post-firmware initialization. */ 8850 8851 DPRINTF(sc, IWN_DEBUG_TRACE, "->%s: end\n",__func__); 8852 8853 return ops->post_alive(sc); 8854 } 8855 8856 static void 8857 iwn_hw_stop(struct iwn_softc *sc) 8858 { 8859 int chnl, qid, ntries; 8860 8861 DPRINTF(sc, IWN_DEBUG_TRACE, "->Doing %s\n", __func__); 8862 8863 IWN_WRITE(sc, IWN_RESET, IWN_RESET_NEVO); 8864 8865 /* Disable interrupts. */ 8866 IWN_WRITE(sc, IWN_INT_MASK, 0); 8867 IWN_WRITE(sc, IWN_INT, 0xffffffff); 8868 IWN_WRITE(sc, IWN_FH_INT, 0xffffffff); 8869 sc->sc_flags &= ~IWN_FLAG_USE_ICT; 8870 8871 /* Make sure we no longer hold the NIC lock. */ 8872 iwn_nic_unlock(sc); 8873 8874 /* Stop TX scheduler. */ 8875 iwn_prph_write(sc, sc->sched_txfact_addr, 0); 8876 8877 /* Stop all DMA channels. */ 8878 if (iwn_nic_lock(sc) == 0) { 8879 for (chnl = 0; chnl < sc->ndmachnls; chnl++) { 8880 IWN_WRITE(sc, IWN_FH_TX_CONFIG(chnl), 0); 8881 for (ntries = 0; ntries < 200; ntries++) { 8882 if (IWN_READ(sc, IWN_FH_TX_STATUS) & 8883 IWN_FH_TX_STATUS_IDLE(chnl)) 8884 break; 8885 DELAY(10); 8886 } 8887 } 8888 iwn_nic_unlock(sc); 8889 } 8890 8891 /* Stop RX ring. */ 8892 iwn_reset_rx_ring(sc, &sc->rxq); 8893 8894 /* Reset all TX rings. */ 8895 for (qid = 0; qid < sc->ntxqs; qid++) 8896 iwn_reset_tx_ring(sc, &sc->txq[qid]); 8897 8898 if (iwn_nic_lock(sc) == 0) { 8899 iwn_prph_write(sc, IWN_APMG_CLK_DIS, 8900 IWN_APMG_CLK_CTRL_DMA_CLK_RQT); 8901 iwn_nic_unlock(sc); 8902 } 8903 DELAY(5); 8904 /* Power OFF adapter. */ 8905 iwn_apm_stop(sc); 8906 } 8907 8908 static void 8909 iwn_panicked(void *arg0, int pending) 8910 { 8911 struct iwn_softc *sc = arg0; 8912 struct ieee80211com *ic = &sc->sc_ic; 8913 struct ieee80211vap *vap = TAILQ_FIRST(&ic->ic_vaps); 8914 #if 0 8915 int error; 8916 #endif 8917 8918 if (vap == NULL) { 8919 printf("%s: null vap\n", __func__); 8920 return; 8921 } 8922 8923 device_printf(sc->sc_dev, "%s: controller panicked, iv_state = %d; " 8924 "restarting\n", __func__, vap->iv_state); 8925 8926 /* 8927 * This is not enough work. We need to also reinitialise 8928 * the correct transmit state for aggregation enabled queues, 8929 * which has a very specific requirement of 8930 * ring index = 802.11 seqno % 256. If we don't do this (which 8931 * we definitely don't!) then the firmware will just panic again. 8932 */ 8933 #if 1 8934 ieee80211_restart_all(ic); 8935 #else 8936 IWN_LOCK(sc); 8937 8938 iwn_stop_locked(sc); 8939 if ((error = iwn_init_locked(sc)) != 0) { 8940 device_printf(sc->sc_dev, 8941 "%s: could not init hardware\n", __func__); 8942 goto unlock; 8943 } 8944 if (vap->iv_state >= IEEE80211_S_AUTH && 8945 (error = iwn_auth(sc, vap)) != 0) { 8946 device_printf(sc->sc_dev, 8947 "%s: could not move to auth state\n", __func__); 8948 } 8949 if (vap->iv_state >= IEEE80211_S_RUN && 8950 (error = iwn_run(sc, vap)) != 0) { 8951 device_printf(sc->sc_dev, 8952 "%s: could not move to run state\n", __func__); 8953 } 8954 8955 unlock: 8956 IWN_UNLOCK(sc); 8957 #endif 8958 } 8959 8960 static int 8961 iwn_init_locked(struct iwn_softc *sc) 8962 { 8963 int error; 8964 8965 DPRINTF(sc, IWN_DEBUG_TRACE, "->%s begin\n", __func__); 8966 8967 IWN_LOCK_ASSERT(sc); 8968 8969 if (sc->sc_flags & IWN_FLAG_RUNNING) 8970 goto end; 8971 8972 sc->sc_flags |= IWN_FLAG_RUNNING; 8973 8974 if ((error = iwn_hw_prepare(sc)) != 0) { 8975 device_printf(sc->sc_dev, "%s: hardware not ready, error %d\n", 8976 __func__, error); 8977 goto fail; 8978 } 8979 8980 /* Initialize interrupt mask to default value. */ 8981 sc->int_mask = IWN_INT_MASK_DEF; 8982 sc->sc_flags &= ~IWN_FLAG_USE_ICT; 8983 8984 /* Check that the radio is not disabled by hardware switch. */ 8985 if (!(IWN_READ(sc, IWN_GP_CNTRL) & IWN_GP_CNTRL_RFKILL)) { 8986 iwn_stop_locked(sc); 8987 DPRINTF(sc, IWN_DEBUG_TRACE, "->%s: end\n",__func__); 8988 8989 return (1); 8990 } 8991 8992 /* Read firmware images from the filesystem. */ 8993 if ((error = iwn_read_firmware(sc)) != 0) { 8994 device_printf(sc->sc_dev, 8995 "%s: could not read firmware, error %d\n", __func__, 8996 error); 8997 goto fail; 8998 } 8999 9000 /* Initialize hardware and upload firmware. */ 9001 error = iwn_hw_init(sc); 9002 iwn_unload_firmware(sc); 9003 if (error != 0) { 9004 device_printf(sc->sc_dev, 9005 "%s: could not initialize hardware, error %d\n", __func__, 9006 error); 9007 goto fail; 9008 } 9009 9010 /* Configure adapter now that it is ready. */ 9011 if ((error = iwn_config(sc)) != 0) { 9012 device_printf(sc->sc_dev, 9013 "%s: could not configure device, error %d\n", __func__, 9014 error); 9015 goto fail; 9016 } 9017 9018 callout_reset(&sc->watchdog_to, hz, iwn_watchdog, sc); 9019 9020 end: 9021 DPRINTF(sc, IWN_DEBUG_TRACE, "->%s: end\n",__func__); 9022 9023 return (0); 9024 9025 fail: 9026 iwn_stop_locked(sc); 9027 9028 DPRINTF(sc, IWN_DEBUG_TRACE, "->%s: end in error\n",__func__); 9029 9030 return (-1); 9031 } 9032 9033 static int 9034 iwn_init(struct iwn_softc *sc) 9035 { 9036 int error; 9037 9038 IWN_LOCK(sc); 9039 error = iwn_init_locked(sc); 9040 IWN_UNLOCK(sc); 9041 9042 return (error); 9043 } 9044 9045 static void 9046 iwn_stop_locked(struct iwn_softc *sc) 9047 { 9048 9049 IWN_LOCK_ASSERT(sc); 9050 9051 if (!(sc->sc_flags & IWN_FLAG_RUNNING)) 9052 return; 9053 9054 sc->sc_is_scanning = 0; 9055 sc->sc_tx_timer = 0; 9056 callout_stop(&sc->watchdog_to); 9057 callout_stop(&sc->scan_timeout); 9058 callout_stop(&sc->calib_to); 9059 sc->sc_flags &= ~IWN_FLAG_RUNNING; 9060 9061 /* Power OFF hardware. */ 9062 iwn_hw_stop(sc); 9063 } 9064 9065 static void 9066 iwn_stop(struct iwn_softc *sc) 9067 { 9068 IWN_LOCK(sc); 9069 iwn_stop_locked(sc); 9070 IWN_UNLOCK(sc); 9071 } 9072 9073 /* 9074 * Callback from net80211 to start a scan. 9075 */ 9076 static void 9077 iwn_scan_start(struct ieee80211com *ic) 9078 { 9079 struct iwn_softc *sc = ic->ic_softc; 9080 9081 IWN_LOCK(sc); 9082 /* make the link LED blink while we're scanning */ 9083 iwn_set_led(sc, IWN_LED_LINK, 20, 2); 9084 IWN_UNLOCK(sc); 9085 } 9086 9087 /* 9088 * Callback from net80211 to terminate a scan. 9089 */ 9090 static void 9091 iwn_scan_end(struct ieee80211com *ic) 9092 { 9093 struct iwn_softc *sc = ic->ic_softc; 9094 struct ieee80211vap *vap = TAILQ_FIRST(&ic->ic_vaps); 9095 9096 IWN_LOCK(sc); 9097 if (vap->iv_state == IEEE80211_S_RUN) { 9098 /* Set link LED to ON status if we are associated */ 9099 iwn_set_led(sc, IWN_LED_LINK, 0, 1); 9100 } 9101 IWN_UNLOCK(sc); 9102 } 9103 9104 /* 9105 * Callback from net80211 to force a channel change. 9106 */ 9107 static void 9108 iwn_set_channel(struct ieee80211com *ic) 9109 { 9110 struct iwn_softc *sc = ic->ic_softc; 9111 int error; 9112 9113 DPRINTF(sc, IWN_DEBUG_TRACE, "->Doing %s\n", __func__); 9114 9115 IWN_LOCK(sc); 9116 /* 9117 * Only need to set the channel in Monitor mode. AP scanning and auth 9118 * are already taken care of by their respective firmware commands. 9119 */ 9120 if (ic->ic_opmode == IEEE80211_M_MONITOR) { 9121 error = iwn_config(sc); 9122 if (error != 0) 9123 device_printf(sc->sc_dev, 9124 "%s: error %d setting channel\n", __func__, error); 9125 } 9126 IWN_UNLOCK(sc); 9127 } 9128 9129 /* 9130 * Callback from net80211 to start scanning of the current channel. 9131 */ 9132 static void 9133 iwn_scan_curchan(struct ieee80211_scan_state *ss, unsigned long maxdwell) 9134 { 9135 struct ieee80211vap *vap = ss->ss_vap; 9136 struct ieee80211com *ic = vap->iv_ic; 9137 struct iwn_softc *sc = ic->ic_softc; 9138 int error; 9139 9140 IWN_LOCK(sc); 9141 error = iwn_scan(sc, vap, ss, ic->ic_curchan); 9142 IWN_UNLOCK(sc); 9143 if (error != 0) 9144 ieee80211_cancel_scan(vap); 9145 } 9146 9147 /* 9148 * Callback from net80211 to handle the minimum dwell time being met. 9149 * The intent is to terminate the scan but we just let the firmware 9150 * notify us when it's finished as we have no safe way to abort it. 9151 */ 9152 static void 9153 iwn_scan_mindwell(struct ieee80211_scan_state *ss) 9154 { 9155 /* NB: don't try to abort scan; wait for firmware to finish */ 9156 } 9157 #ifdef IWN_DEBUG 9158 #define IWN_DESC(x) case x: return #x 9159 9160 /* 9161 * Translate CSR code to string 9162 */ 9163 static char *iwn_get_csr_string(int csr) 9164 { 9165 switch (csr) { 9166 IWN_DESC(IWN_HW_IF_CONFIG); 9167 IWN_DESC(IWN_INT_COALESCING); 9168 IWN_DESC(IWN_INT); 9169 IWN_DESC(IWN_INT_MASK); 9170 IWN_DESC(IWN_FH_INT); 9171 IWN_DESC(IWN_GPIO_IN); 9172 IWN_DESC(IWN_RESET); 9173 IWN_DESC(IWN_GP_CNTRL); 9174 IWN_DESC(IWN_HW_REV); 9175 IWN_DESC(IWN_EEPROM); 9176 IWN_DESC(IWN_EEPROM_GP); 9177 IWN_DESC(IWN_OTP_GP); 9178 IWN_DESC(IWN_GIO); 9179 IWN_DESC(IWN_GP_UCODE); 9180 IWN_DESC(IWN_GP_DRIVER); 9181 IWN_DESC(IWN_UCODE_GP1); 9182 IWN_DESC(IWN_UCODE_GP2); 9183 IWN_DESC(IWN_LED); 9184 IWN_DESC(IWN_DRAM_INT_TBL); 9185 IWN_DESC(IWN_GIO_CHICKEN); 9186 IWN_DESC(IWN_ANA_PLL); 9187 IWN_DESC(IWN_HW_REV_WA); 9188 IWN_DESC(IWN_DBG_HPET_MEM); 9189 default: 9190 return "UNKNOWN CSR"; 9191 } 9192 } 9193 9194 /* 9195 * This function print firmware register 9196 */ 9197 static void 9198 iwn_debug_register(struct iwn_softc *sc) 9199 { 9200 int i; 9201 static const uint32_t csr_tbl[] = { 9202 IWN_HW_IF_CONFIG, 9203 IWN_INT_COALESCING, 9204 IWN_INT, 9205 IWN_INT_MASK, 9206 IWN_FH_INT, 9207 IWN_GPIO_IN, 9208 IWN_RESET, 9209 IWN_GP_CNTRL, 9210 IWN_HW_REV, 9211 IWN_EEPROM, 9212 IWN_EEPROM_GP, 9213 IWN_OTP_GP, 9214 IWN_GIO, 9215 IWN_GP_UCODE, 9216 IWN_GP_DRIVER, 9217 IWN_UCODE_GP1, 9218 IWN_UCODE_GP2, 9219 IWN_LED, 9220 IWN_DRAM_INT_TBL, 9221 IWN_GIO_CHICKEN, 9222 IWN_ANA_PLL, 9223 IWN_HW_REV_WA, 9224 IWN_DBG_HPET_MEM, 9225 }; 9226 DPRINTF(sc, IWN_DEBUG_REGISTER, 9227 "CSR values: (2nd byte of IWN_INT_COALESCING is IWN_INT_PERIODIC)%s", 9228 "\n"); 9229 for (i = 0; i < nitems(csr_tbl); i++){ 9230 DPRINTF(sc, IWN_DEBUG_REGISTER," %10s: 0x%08x ", 9231 iwn_get_csr_string(csr_tbl[i]), IWN_READ(sc, csr_tbl[i])); 9232 if ((i+1) % 3 == 0) 9233 DPRINTF(sc, IWN_DEBUG_REGISTER,"%s","\n"); 9234 } 9235 DPRINTF(sc, IWN_DEBUG_REGISTER,"%s","\n"); 9236 } 9237 #endif 9238 9239 9240