1 /*- 2 * Copyright (c) 2007-2009 Damien Bergamini <damien.bergamini@free.fr> 3 * Copyright (c) 2008 Benjamin Close <benjsc@FreeBSD.org> 4 * Copyright (c) 2008 Sam Leffler, Errno Consulting 5 * Copyright (c) 2011 Intel Corporation 6 * Copyright (c) 2013 Cedric GROSS <c.gross@kreiz-it.fr> 7 * Copyright (c) 2013 Adrian Chadd <adrian@FreeBSD.org> 8 * 9 * Permission to use, copy, modify, and distribute this software for any 10 * purpose with or without fee is hereby granted, provided that the above 11 * copyright notice and this permission notice appear in all copies. 12 * 13 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 14 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 15 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR 16 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 17 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN 18 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF 19 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 20 */ 21 22 /* 23 * Driver for Intel WiFi Link 4965 and 1000/5000/6000 Series 802.11 network 24 * adapters. 25 */ 26 27 #include <sys/cdefs.h> 28 __FBSDID("$FreeBSD$"); 29 30 #include "opt_wlan.h" 31 #include "opt_iwn.h" 32 33 #include <sys/param.h> 34 #include <sys/sockio.h> 35 #include <sys/sysctl.h> 36 #include <sys/mbuf.h> 37 #include <sys/kernel.h> 38 #include <sys/socket.h> 39 #include <sys/systm.h> 40 #include <sys/malloc.h> 41 #include <sys/bus.h> 42 #include <sys/conf.h> 43 #include <sys/rman.h> 44 #include <sys/endian.h> 45 #include <sys/firmware.h> 46 #include <sys/limits.h> 47 #include <sys/module.h> 48 #include <sys/priv.h> 49 #include <sys/queue.h> 50 #include <sys/taskqueue.h> 51 52 #include <machine/bus.h> 53 #include <machine/resource.h> 54 #include <machine/clock.h> 55 56 #include <dev/pci/pcireg.h> 57 #include <dev/pci/pcivar.h> 58 59 #include <net/if.h> 60 #include <net/if_var.h> 61 #include <net/if_dl.h> 62 #include <net/if_media.h> 63 64 #include <netinet/in.h> 65 #include <netinet/if_ether.h> 66 67 #include <net80211/ieee80211_var.h> 68 #include <net80211/ieee80211_radiotap.h> 69 #include <net80211/ieee80211_regdomain.h> 70 #include <net80211/ieee80211_ratectl.h> 71 72 #include <dev/iwn/if_iwnreg.h> 73 #include <dev/iwn/if_iwnvar.h> 74 #include <dev/iwn/if_iwn_devid.h> 75 #include <dev/iwn/if_iwn_chip_cfg.h> 76 #include <dev/iwn/if_iwn_debug.h> 77 #include <dev/iwn/if_iwn_ioctl.h> 78 79 struct iwn_ident { 80 uint16_t vendor; 81 uint16_t device; 82 const char *name; 83 }; 84 85 static const struct iwn_ident iwn_ident_table[] = { 86 { 0x8086, IWN_DID_6x05_1, "Intel Centrino Advanced-N 6205" }, 87 { 0x8086, IWN_DID_1000_1, "Intel Centrino Wireless-N 1000" }, 88 { 0x8086, IWN_DID_1000_2, "Intel Centrino Wireless-N 1000" }, 89 { 0x8086, IWN_DID_6x05_2, "Intel Centrino Advanced-N 6205" }, 90 { 0x8086, IWN_DID_6050_1, "Intel Centrino Advanced-N + WiMAX 6250" }, 91 { 0x8086, IWN_DID_6050_2, "Intel Centrino Advanced-N + WiMAX 6250" }, 92 { 0x8086, IWN_DID_x030_1, "Intel Centrino Wireless-N 1030" }, 93 { 0x8086, IWN_DID_x030_2, "Intel Centrino Wireless-N 1030" }, 94 { 0x8086, IWN_DID_x030_3, "Intel Centrino Advanced-N 6230" }, 95 { 0x8086, IWN_DID_x030_4, "Intel Centrino Advanced-N 6230" }, 96 { 0x8086, IWN_DID_6150_1, "Intel Centrino Wireless-N + WiMAX 6150" }, 97 { 0x8086, IWN_DID_6150_2, "Intel Centrino Wireless-N + WiMAX 6150" }, 98 { 0x8086, IWN_DID_2x00_1, "Intel(R) Centrino(R) Wireless-N 2200 BGN" }, 99 { 0x8086, IWN_DID_2x00_2, "Intel(R) Centrino(R) Wireless-N 2200 BGN" }, 100 /* XXX 2200D is IWN_SDID_2x00_4; there's no way to express this here! */ 101 { 0x8086, IWN_DID_2x30_1, "Intel Centrino Wireless-N 2230" }, 102 { 0x8086, IWN_DID_2x30_2, "Intel Centrino Wireless-N 2230" }, 103 { 0x8086, IWN_DID_130_1, "Intel Centrino Wireless-N 130" }, 104 { 0x8086, IWN_DID_130_2, "Intel Centrino Wireless-N 130" }, 105 { 0x8086, IWN_DID_100_1, "Intel Centrino Wireless-N 100" }, 106 { 0x8086, IWN_DID_100_2, "Intel Centrino Wireless-N 100" }, 107 { 0x8086, IWN_DID_105_1, "Intel Centrino Wireless-N 105" }, 108 { 0x8086, IWN_DID_105_2, "Intel Centrino Wireless-N 105" }, 109 { 0x8086, IWN_DID_135_1, "Intel Centrino Wireless-N 135" }, 110 { 0x8086, IWN_DID_135_2, "Intel Centrino Wireless-N 135" }, 111 { 0x8086, IWN_DID_4965_1, "Intel Wireless WiFi Link 4965" }, 112 { 0x8086, IWN_DID_6x00_1, "Intel Centrino Ultimate-N 6300" }, 113 { 0x8086, IWN_DID_6x00_2, "Intel Centrino Advanced-N 6200" }, 114 { 0x8086, IWN_DID_4965_2, "Intel Wireless WiFi Link 4965" }, 115 { 0x8086, IWN_DID_4965_3, "Intel Wireless WiFi Link 4965" }, 116 { 0x8086, IWN_DID_5x00_1, "Intel WiFi Link 5100" }, 117 { 0x8086, IWN_DID_4965_4, "Intel Wireless WiFi Link 4965" }, 118 { 0x8086, IWN_DID_5x00_3, "Intel Ultimate N WiFi Link 5300" }, 119 { 0x8086, IWN_DID_5x00_4, "Intel Ultimate N WiFi Link 5300" }, 120 { 0x8086, IWN_DID_5x00_2, "Intel WiFi Link 5100" }, 121 { 0x8086, IWN_DID_6x00_3, "Intel Centrino Ultimate-N 6300" }, 122 { 0x8086, IWN_DID_6x00_4, "Intel Centrino Advanced-N 6200" }, 123 { 0x8086, IWN_DID_5x50_1, "Intel WiMAX/WiFi Link 5350" }, 124 { 0x8086, IWN_DID_5x50_2, "Intel WiMAX/WiFi Link 5350" }, 125 { 0x8086, IWN_DID_5x50_3, "Intel WiMAX/WiFi Link 5150" }, 126 { 0x8086, IWN_DID_5x50_4, "Intel WiMAX/WiFi Link 5150" }, 127 { 0x8086, IWN_DID_6035_1, "Intel Centrino Advanced 6235" }, 128 { 0x8086, IWN_DID_6035_2, "Intel Centrino Advanced 6235" }, 129 { 0, 0, NULL } 130 }; 131 132 static int iwn_probe(device_t); 133 static int iwn_attach(device_t); 134 static int iwn4965_attach(struct iwn_softc *, uint16_t); 135 static int iwn5000_attach(struct iwn_softc *, uint16_t); 136 static int iwn_config_specific(struct iwn_softc *, uint16_t); 137 static void iwn_radiotap_attach(struct iwn_softc *); 138 static void iwn_sysctlattach(struct iwn_softc *); 139 static struct ieee80211vap *iwn_vap_create(struct ieee80211com *, 140 const char [IFNAMSIZ], int, enum ieee80211_opmode, int, 141 const uint8_t [IEEE80211_ADDR_LEN], 142 const uint8_t [IEEE80211_ADDR_LEN]); 143 static void iwn_vap_delete(struct ieee80211vap *); 144 static int iwn_detach(device_t); 145 static int iwn_shutdown(device_t); 146 static int iwn_suspend(device_t); 147 static int iwn_resume(device_t); 148 static int iwn_nic_lock(struct iwn_softc *); 149 static int iwn_eeprom_lock(struct iwn_softc *); 150 static int iwn_init_otprom(struct iwn_softc *); 151 static int iwn_read_prom_data(struct iwn_softc *, uint32_t, void *, int); 152 static void iwn_dma_map_addr(void *, bus_dma_segment_t *, int, int); 153 static int iwn_dma_contig_alloc(struct iwn_softc *, struct iwn_dma_info *, 154 void **, bus_size_t, bus_size_t); 155 static void iwn_dma_contig_free(struct iwn_dma_info *); 156 static int iwn_alloc_sched(struct iwn_softc *); 157 static void iwn_free_sched(struct iwn_softc *); 158 static int iwn_alloc_kw(struct iwn_softc *); 159 static void iwn_free_kw(struct iwn_softc *); 160 static int iwn_alloc_ict(struct iwn_softc *); 161 static void iwn_free_ict(struct iwn_softc *); 162 static int iwn_alloc_fwmem(struct iwn_softc *); 163 static void iwn_free_fwmem(struct iwn_softc *); 164 static int iwn_alloc_rx_ring(struct iwn_softc *, struct iwn_rx_ring *); 165 static void iwn_reset_rx_ring(struct iwn_softc *, struct iwn_rx_ring *); 166 static void iwn_free_rx_ring(struct iwn_softc *, struct iwn_rx_ring *); 167 static int iwn_alloc_tx_ring(struct iwn_softc *, struct iwn_tx_ring *, 168 int); 169 static void iwn_reset_tx_ring(struct iwn_softc *, struct iwn_tx_ring *); 170 static void iwn_free_tx_ring(struct iwn_softc *, struct iwn_tx_ring *); 171 static void iwn5000_ict_reset(struct iwn_softc *); 172 static int iwn_read_eeprom(struct iwn_softc *, 173 uint8_t macaddr[IEEE80211_ADDR_LEN]); 174 static void iwn4965_read_eeprom(struct iwn_softc *); 175 #ifdef IWN_DEBUG 176 static void iwn4965_print_power_group(struct iwn_softc *, int); 177 #endif 178 static void iwn5000_read_eeprom(struct iwn_softc *); 179 static uint32_t iwn_eeprom_channel_flags(struct iwn_eeprom_chan *); 180 static void iwn_read_eeprom_band(struct iwn_softc *, int, int, int *, 181 struct ieee80211_channel[]); 182 static void iwn_read_eeprom_ht40(struct iwn_softc *, int, int, int *, 183 struct ieee80211_channel[]); 184 static void iwn_read_eeprom_channels(struct iwn_softc *, int, uint32_t); 185 static struct iwn_eeprom_chan *iwn_find_eeprom_channel(struct iwn_softc *, 186 struct ieee80211_channel *); 187 static void iwn_getradiocaps(struct ieee80211com *, int, int *, 188 struct ieee80211_channel[]); 189 static int iwn_setregdomain(struct ieee80211com *, 190 struct ieee80211_regdomain *, int, 191 struct ieee80211_channel[]); 192 static void iwn_read_eeprom_enhinfo(struct iwn_softc *); 193 static struct ieee80211_node *iwn_node_alloc(struct ieee80211vap *, 194 const uint8_t mac[IEEE80211_ADDR_LEN]); 195 static void iwn_newassoc(struct ieee80211_node *, int); 196 static int iwn_media_change(struct ifnet *); 197 static int iwn_newstate(struct ieee80211vap *, enum ieee80211_state, int); 198 static void iwn_calib_timeout(void *); 199 static void iwn_rx_phy(struct iwn_softc *, struct iwn_rx_desc *, 200 struct iwn_rx_data *); 201 static void iwn_rx_done(struct iwn_softc *, struct iwn_rx_desc *, 202 struct iwn_rx_data *); 203 static void iwn_rx_compressed_ba(struct iwn_softc *, struct iwn_rx_desc *, 204 struct iwn_rx_data *); 205 static void iwn5000_rx_calib_results(struct iwn_softc *, 206 struct iwn_rx_desc *, struct iwn_rx_data *); 207 static void iwn_rx_statistics(struct iwn_softc *, struct iwn_rx_desc *, 208 struct iwn_rx_data *); 209 static void iwn4965_tx_done(struct iwn_softc *, struct iwn_rx_desc *, 210 struct iwn_rx_data *); 211 static void iwn5000_tx_done(struct iwn_softc *, struct iwn_rx_desc *, 212 struct iwn_rx_data *); 213 static void iwn_tx_done(struct iwn_softc *, struct iwn_rx_desc *, int, int, 214 uint8_t); 215 static void iwn_ampdu_tx_done(struct iwn_softc *, int, int, int, int, int, 216 void *); 217 static void iwn_cmd_done(struct iwn_softc *, struct iwn_rx_desc *); 218 static void iwn_notif_intr(struct iwn_softc *); 219 static void iwn_wakeup_intr(struct iwn_softc *); 220 static void iwn_rftoggle_task(void *, int); 221 static void iwn_fatal_intr(struct iwn_softc *); 222 static void iwn_intr(void *); 223 static void iwn4965_update_sched(struct iwn_softc *, int, int, uint8_t, 224 uint16_t); 225 static void iwn5000_update_sched(struct iwn_softc *, int, int, uint8_t, 226 uint16_t); 227 #ifdef notyet 228 static void iwn5000_reset_sched(struct iwn_softc *, int, int); 229 #endif 230 static int iwn_tx_data(struct iwn_softc *, struct mbuf *, 231 struct ieee80211_node *); 232 static int iwn_tx_data_raw(struct iwn_softc *, struct mbuf *, 233 struct ieee80211_node *, 234 const struct ieee80211_bpf_params *params); 235 static void iwn_xmit_task(void *arg0, int pending); 236 static int iwn_raw_xmit(struct ieee80211_node *, struct mbuf *, 237 const struct ieee80211_bpf_params *); 238 static int iwn_transmit(struct ieee80211com *, struct mbuf *); 239 static void iwn_scan_timeout(void *); 240 static void iwn_watchdog(void *); 241 static int iwn_ioctl(struct ieee80211com *, u_long , void *); 242 static void iwn_parent(struct ieee80211com *); 243 static int iwn_cmd(struct iwn_softc *, int, const void *, int, int); 244 static int iwn4965_add_node(struct iwn_softc *, struct iwn_node_info *, 245 int); 246 static int iwn5000_add_node(struct iwn_softc *, struct iwn_node_info *, 247 int); 248 static int iwn_set_link_quality(struct iwn_softc *, 249 struct ieee80211_node *); 250 static int iwn_add_broadcast_node(struct iwn_softc *, int); 251 static int iwn_updateedca(struct ieee80211com *); 252 static void iwn_update_mcast(struct ieee80211com *); 253 static void iwn_set_led(struct iwn_softc *, uint8_t, uint8_t, uint8_t); 254 static int iwn_set_critical_temp(struct iwn_softc *); 255 static int iwn_set_timing(struct iwn_softc *, struct ieee80211_node *); 256 static void iwn4965_power_calibration(struct iwn_softc *, int); 257 static int iwn4965_set_txpower(struct iwn_softc *, int); 258 static int iwn5000_set_txpower(struct iwn_softc *, int); 259 static int iwn4965_get_rssi(struct iwn_softc *, struct iwn_rx_stat *); 260 static int iwn5000_get_rssi(struct iwn_softc *, struct iwn_rx_stat *); 261 static int iwn_get_noise(const struct iwn_rx_general_stats *); 262 static int iwn4965_get_temperature(struct iwn_softc *); 263 static int iwn5000_get_temperature(struct iwn_softc *); 264 static int iwn_init_sensitivity(struct iwn_softc *); 265 static void iwn_collect_noise(struct iwn_softc *, 266 const struct iwn_rx_general_stats *); 267 static int iwn4965_init_gains(struct iwn_softc *); 268 static int iwn5000_init_gains(struct iwn_softc *); 269 static int iwn4965_set_gains(struct iwn_softc *); 270 static int iwn5000_set_gains(struct iwn_softc *); 271 static void iwn_tune_sensitivity(struct iwn_softc *, 272 const struct iwn_rx_stats *); 273 static void iwn_save_stats_counters(struct iwn_softc *, 274 const struct iwn_stats *); 275 static int iwn_send_sensitivity(struct iwn_softc *); 276 static void iwn_check_rx_recovery(struct iwn_softc *, struct iwn_stats *); 277 static int iwn_set_pslevel(struct iwn_softc *, int, int, int); 278 static int iwn_send_btcoex(struct iwn_softc *); 279 static int iwn_send_advanced_btcoex(struct iwn_softc *); 280 static int iwn5000_runtime_calib(struct iwn_softc *); 281 static int iwn_config(struct iwn_softc *); 282 static int iwn_scan(struct iwn_softc *, struct ieee80211vap *, 283 struct ieee80211_scan_state *, struct ieee80211_channel *); 284 static int iwn_auth(struct iwn_softc *, struct ieee80211vap *vap); 285 static int iwn_run(struct iwn_softc *, struct ieee80211vap *vap); 286 static int iwn_ampdu_rx_start(struct ieee80211_node *, 287 struct ieee80211_rx_ampdu *, int, int, int); 288 static void iwn_ampdu_rx_stop(struct ieee80211_node *, 289 struct ieee80211_rx_ampdu *); 290 static int iwn_addba_request(struct ieee80211_node *, 291 struct ieee80211_tx_ampdu *, int, int, int); 292 static int iwn_addba_response(struct ieee80211_node *, 293 struct ieee80211_tx_ampdu *, int, int, int); 294 static int iwn_ampdu_tx_start(struct ieee80211com *, 295 struct ieee80211_node *, uint8_t); 296 static void iwn_ampdu_tx_stop(struct ieee80211_node *, 297 struct ieee80211_tx_ampdu *); 298 static void iwn4965_ampdu_tx_start(struct iwn_softc *, 299 struct ieee80211_node *, int, uint8_t, uint16_t); 300 static void iwn4965_ampdu_tx_stop(struct iwn_softc *, int, 301 uint8_t, uint16_t); 302 static void iwn5000_ampdu_tx_start(struct iwn_softc *, 303 struct ieee80211_node *, int, uint8_t, uint16_t); 304 static void iwn5000_ampdu_tx_stop(struct iwn_softc *, int, 305 uint8_t, uint16_t); 306 static int iwn5000_query_calibration(struct iwn_softc *); 307 static int iwn5000_send_calibration(struct iwn_softc *); 308 static int iwn5000_send_wimax_coex(struct iwn_softc *); 309 static int iwn5000_crystal_calib(struct iwn_softc *); 310 static int iwn5000_temp_offset_calib(struct iwn_softc *); 311 static int iwn5000_temp_offset_calibv2(struct iwn_softc *); 312 static int iwn4965_post_alive(struct iwn_softc *); 313 static int iwn5000_post_alive(struct iwn_softc *); 314 static int iwn4965_load_bootcode(struct iwn_softc *, const uint8_t *, 315 int); 316 static int iwn4965_load_firmware(struct iwn_softc *); 317 static int iwn5000_load_firmware_section(struct iwn_softc *, uint32_t, 318 const uint8_t *, int); 319 static int iwn5000_load_firmware(struct iwn_softc *); 320 static int iwn_read_firmware_leg(struct iwn_softc *, 321 struct iwn_fw_info *); 322 static int iwn_read_firmware_tlv(struct iwn_softc *, 323 struct iwn_fw_info *, uint16_t); 324 static int iwn_read_firmware(struct iwn_softc *); 325 static void iwn_unload_firmware(struct iwn_softc *); 326 static int iwn_clock_wait(struct iwn_softc *); 327 static int iwn_apm_init(struct iwn_softc *); 328 static void iwn_apm_stop_master(struct iwn_softc *); 329 static void iwn_apm_stop(struct iwn_softc *); 330 static int iwn4965_nic_config(struct iwn_softc *); 331 static int iwn5000_nic_config(struct iwn_softc *); 332 static int iwn_hw_prepare(struct iwn_softc *); 333 static int iwn_hw_init(struct iwn_softc *); 334 static void iwn_hw_stop(struct iwn_softc *); 335 static void iwn_panicked(void *, int); 336 static int iwn_init_locked(struct iwn_softc *); 337 static int iwn_init(struct iwn_softc *); 338 static void iwn_stop_locked(struct iwn_softc *); 339 static void iwn_stop(struct iwn_softc *); 340 static void iwn_scan_start(struct ieee80211com *); 341 static void iwn_scan_end(struct ieee80211com *); 342 static void iwn_set_channel(struct ieee80211com *); 343 static void iwn_scan_curchan(struct ieee80211_scan_state *, unsigned long); 344 static void iwn_scan_mindwell(struct ieee80211_scan_state *); 345 #ifdef IWN_DEBUG 346 static char *iwn_get_csr_string(int); 347 static void iwn_debug_register(struct iwn_softc *); 348 #endif 349 350 static device_method_t iwn_methods[] = { 351 /* Device interface */ 352 DEVMETHOD(device_probe, iwn_probe), 353 DEVMETHOD(device_attach, iwn_attach), 354 DEVMETHOD(device_detach, iwn_detach), 355 DEVMETHOD(device_shutdown, iwn_shutdown), 356 DEVMETHOD(device_suspend, iwn_suspend), 357 DEVMETHOD(device_resume, iwn_resume), 358 359 DEVMETHOD_END 360 }; 361 362 static driver_t iwn_driver = { 363 "iwn", 364 iwn_methods, 365 sizeof(struct iwn_softc) 366 }; 367 static devclass_t iwn_devclass; 368 369 DRIVER_MODULE(iwn, pci, iwn_driver, iwn_devclass, NULL, NULL); 370 371 MODULE_VERSION(iwn, 1); 372 373 MODULE_DEPEND(iwn, firmware, 1, 1, 1); 374 MODULE_DEPEND(iwn, pci, 1, 1, 1); 375 MODULE_DEPEND(iwn, wlan, 1, 1, 1); 376 377 static d_ioctl_t iwn_cdev_ioctl; 378 static d_open_t iwn_cdev_open; 379 static d_close_t iwn_cdev_close; 380 381 static struct cdevsw iwn_cdevsw = { 382 .d_version = D_VERSION, 383 .d_flags = 0, 384 .d_open = iwn_cdev_open, 385 .d_close = iwn_cdev_close, 386 .d_ioctl = iwn_cdev_ioctl, 387 .d_name = "iwn", 388 }; 389 390 static int 391 iwn_probe(device_t dev) 392 { 393 const struct iwn_ident *ident; 394 395 for (ident = iwn_ident_table; ident->name != NULL; ident++) { 396 if (pci_get_vendor(dev) == ident->vendor && 397 pci_get_device(dev) == ident->device) { 398 device_set_desc(dev, ident->name); 399 return (BUS_PROBE_DEFAULT); 400 } 401 } 402 return ENXIO; 403 } 404 405 static int 406 iwn_is_3stream_device(struct iwn_softc *sc) 407 { 408 /* XXX for now only 5300, until the 5350 can be tested */ 409 if (sc->hw_type == IWN_HW_REV_TYPE_5300) 410 return (1); 411 return (0); 412 } 413 414 static int 415 iwn_attach(device_t dev) 416 { 417 struct iwn_softc *sc = device_get_softc(dev); 418 struct ieee80211com *ic; 419 int i, error, rid; 420 421 sc->sc_dev = dev; 422 423 #ifdef IWN_DEBUG 424 error = resource_int_value(device_get_name(sc->sc_dev), 425 device_get_unit(sc->sc_dev), "debug", &(sc->sc_debug)); 426 if (error != 0) 427 sc->sc_debug = 0; 428 #else 429 sc->sc_debug = 0; 430 #endif 431 432 DPRINTF(sc, IWN_DEBUG_TRACE, "->%s: begin\n",__func__); 433 434 /* 435 * Get the offset of the PCI Express Capability Structure in PCI 436 * Configuration Space. 437 */ 438 error = pci_find_cap(dev, PCIY_EXPRESS, &sc->sc_cap_off); 439 if (error != 0) { 440 device_printf(dev, "PCIe capability structure not found!\n"); 441 return error; 442 } 443 444 /* Clear device-specific "PCI retry timeout" register (41h). */ 445 pci_write_config(dev, 0x41, 0, 1); 446 447 /* Enable bus-mastering. */ 448 pci_enable_busmaster(dev); 449 450 rid = PCIR_BAR(0); 451 sc->mem = bus_alloc_resource_any(dev, SYS_RES_MEMORY, &rid, 452 RF_ACTIVE); 453 if (sc->mem == NULL) { 454 device_printf(dev, "can't map mem space\n"); 455 error = ENOMEM; 456 return error; 457 } 458 sc->sc_st = rman_get_bustag(sc->mem); 459 sc->sc_sh = rman_get_bushandle(sc->mem); 460 461 i = 1; 462 rid = 0; 463 if (pci_alloc_msi(dev, &i) == 0) 464 rid = 1; 465 /* Install interrupt handler. */ 466 sc->irq = bus_alloc_resource_any(dev, SYS_RES_IRQ, &rid, RF_ACTIVE | 467 (rid != 0 ? 0 : RF_SHAREABLE)); 468 if (sc->irq == NULL) { 469 device_printf(dev, "can't map interrupt\n"); 470 error = ENOMEM; 471 goto fail; 472 } 473 474 IWN_LOCK_INIT(sc); 475 476 /* Read hardware revision and attach. */ 477 sc->hw_type = (IWN_READ(sc, IWN_HW_REV) >> IWN_HW_REV_TYPE_SHIFT) 478 & IWN_HW_REV_TYPE_MASK; 479 sc->subdevice_id = pci_get_subdevice(dev); 480 481 /* 482 * 4965 versus 5000 and later have different methods. 483 * Let's set those up first. 484 */ 485 if (sc->hw_type == IWN_HW_REV_TYPE_4965) 486 error = iwn4965_attach(sc, pci_get_device(dev)); 487 else 488 error = iwn5000_attach(sc, pci_get_device(dev)); 489 if (error != 0) { 490 device_printf(dev, "could not attach device, error %d\n", 491 error); 492 goto fail; 493 } 494 495 /* 496 * Next, let's setup the various parameters of each NIC. 497 */ 498 error = iwn_config_specific(sc, pci_get_device(dev)); 499 if (error != 0) { 500 device_printf(dev, "could not attach device, error %d\n", 501 error); 502 goto fail; 503 } 504 505 if ((error = iwn_hw_prepare(sc)) != 0) { 506 device_printf(dev, "hardware not ready, error %d\n", error); 507 goto fail; 508 } 509 510 /* Allocate DMA memory for firmware transfers. */ 511 if ((error = iwn_alloc_fwmem(sc)) != 0) { 512 device_printf(dev, 513 "could not allocate memory for firmware, error %d\n", 514 error); 515 goto fail; 516 } 517 518 /* Allocate "Keep Warm" page. */ 519 if ((error = iwn_alloc_kw(sc)) != 0) { 520 device_printf(dev, 521 "could not allocate keep warm page, error %d\n", error); 522 goto fail; 523 } 524 525 /* Allocate ICT table for 5000 Series. */ 526 if (sc->hw_type != IWN_HW_REV_TYPE_4965 && 527 (error = iwn_alloc_ict(sc)) != 0) { 528 device_printf(dev, "could not allocate ICT table, error %d\n", 529 error); 530 goto fail; 531 } 532 533 /* Allocate TX scheduler "rings". */ 534 if ((error = iwn_alloc_sched(sc)) != 0) { 535 device_printf(dev, 536 "could not allocate TX scheduler rings, error %d\n", error); 537 goto fail; 538 } 539 540 /* Allocate TX rings (16 on 4965AGN, 20 on >=5000). */ 541 for (i = 0; i < sc->ntxqs; i++) { 542 if ((error = iwn_alloc_tx_ring(sc, &sc->txq[i], i)) != 0) { 543 device_printf(dev, 544 "could not allocate TX ring %d, error %d\n", i, 545 error); 546 goto fail; 547 } 548 } 549 550 /* Allocate RX ring. */ 551 if ((error = iwn_alloc_rx_ring(sc, &sc->rxq)) != 0) { 552 device_printf(dev, "could not allocate RX ring, error %d\n", 553 error); 554 goto fail; 555 } 556 557 /* Clear pending interrupts. */ 558 IWN_WRITE(sc, IWN_INT, 0xffffffff); 559 560 ic = &sc->sc_ic; 561 ic->ic_softc = sc; 562 ic->ic_name = device_get_nameunit(dev); 563 ic->ic_phytype = IEEE80211_T_OFDM; /* not only, but not used */ 564 ic->ic_opmode = IEEE80211_M_STA; /* default to BSS mode */ 565 566 /* Set device capabilities. */ 567 ic->ic_caps = 568 IEEE80211_C_STA /* station mode supported */ 569 | IEEE80211_C_MONITOR /* monitor mode supported */ 570 #if 0 571 | IEEE80211_C_BGSCAN /* background scanning */ 572 #endif 573 | IEEE80211_C_TXPMGT /* tx power management */ 574 | IEEE80211_C_SHSLOT /* short slot time supported */ 575 | IEEE80211_C_WPA 576 | IEEE80211_C_SHPREAMBLE /* short preamble supported */ 577 #if 0 578 | IEEE80211_C_IBSS /* ibss/adhoc mode */ 579 #endif 580 | IEEE80211_C_WME /* WME */ 581 | IEEE80211_C_PMGT /* Station-side power mgmt */ 582 ; 583 584 /* Read MAC address, channels, etc from EEPROM. */ 585 if ((error = iwn_read_eeprom(sc, ic->ic_macaddr)) != 0) { 586 device_printf(dev, "could not read EEPROM, error %d\n", 587 error); 588 goto fail; 589 } 590 591 /* Count the number of available chains. */ 592 sc->ntxchains = 593 ((sc->txchainmask >> 2) & 1) + 594 ((sc->txchainmask >> 1) & 1) + 595 ((sc->txchainmask >> 0) & 1); 596 sc->nrxchains = 597 ((sc->rxchainmask >> 2) & 1) + 598 ((sc->rxchainmask >> 1) & 1) + 599 ((sc->rxchainmask >> 0) & 1); 600 if (bootverbose) { 601 device_printf(dev, "MIMO %dT%dR, %.4s, address %6D\n", 602 sc->ntxchains, sc->nrxchains, sc->eeprom_domain, 603 ic->ic_macaddr, ":"); 604 } 605 606 if (sc->sc_flags & IWN_FLAG_HAS_11N) { 607 ic->ic_rxstream = sc->nrxchains; 608 ic->ic_txstream = sc->ntxchains; 609 610 /* 611 * Some of the 3 antenna devices (ie, the 4965) only supports 612 * 2x2 operation. So correct the number of streams if 613 * it's not a 3-stream device. 614 */ 615 if (! iwn_is_3stream_device(sc)) { 616 if (ic->ic_rxstream > 2) 617 ic->ic_rxstream = 2; 618 if (ic->ic_txstream > 2) 619 ic->ic_txstream = 2; 620 } 621 622 ic->ic_htcaps = 623 IEEE80211_HTCAP_SMPS_OFF /* SMPS mode disabled */ 624 | IEEE80211_HTCAP_SHORTGI20 /* short GI in 20MHz */ 625 | IEEE80211_HTCAP_CHWIDTH40 /* 40MHz channel width*/ 626 | IEEE80211_HTCAP_SHORTGI40 /* short GI in 40MHz */ 627 #ifdef notyet 628 | IEEE80211_HTCAP_GREENFIELD 629 #if IWN_RBUF_SIZE == 8192 630 | IEEE80211_HTCAP_MAXAMSDU_7935 /* max A-MSDU length */ 631 #else 632 | IEEE80211_HTCAP_MAXAMSDU_3839 /* max A-MSDU length */ 633 #endif 634 #endif 635 /* s/w capabilities */ 636 | IEEE80211_HTC_HT /* HT operation */ 637 | IEEE80211_HTC_AMPDU /* tx A-MPDU */ 638 #ifdef notyet 639 | IEEE80211_HTC_AMSDU /* tx A-MSDU */ 640 #endif 641 ; 642 } 643 644 ieee80211_ifattach(ic); 645 ic->ic_vap_create = iwn_vap_create; 646 ic->ic_ioctl = iwn_ioctl; 647 ic->ic_parent = iwn_parent; 648 ic->ic_vap_delete = iwn_vap_delete; 649 ic->ic_transmit = iwn_transmit; 650 ic->ic_raw_xmit = iwn_raw_xmit; 651 ic->ic_node_alloc = iwn_node_alloc; 652 sc->sc_ampdu_rx_start = ic->ic_ampdu_rx_start; 653 ic->ic_ampdu_rx_start = iwn_ampdu_rx_start; 654 sc->sc_ampdu_rx_stop = ic->ic_ampdu_rx_stop; 655 ic->ic_ampdu_rx_stop = iwn_ampdu_rx_stop; 656 sc->sc_addba_request = ic->ic_addba_request; 657 ic->ic_addba_request = iwn_addba_request; 658 sc->sc_addba_response = ic->ic_addba_response; 659 ic->ic_addba_response = iwn_addba_response; 660 sc->sc_addba_stop = ic->ic_addba_stop; 661 ic->ic_addba_stop = iwn_ampdu_tx_stop; 662 ic->ic_newassoc = iwn_newassoc; 663 ic->ic_wme.wme_update = iwn_updateedca; 664 ic->ic_update_mcast = iwn_update_mcast; 665 ic->ic_scan_start = iwn_scan_start; 666 ic->ic_scan_end = iwn_scan_end; 667 ic->ic_set_channel = iwn_set_channel; 668 ic->ic_scan_curchan = iwn_scan_curchan; 669 ic->ic_scan_mindwell = iwn_scan_mindwell; 670 ic->ic_getradiocaps = iwn_getradiocaps; 671 ic->ic_setregdomain = iwn_setregdomain; 672 673 iwn_radiotap_attach(sc); 674 675 callout_init_mtx(&sc->calib_to, &sc->sc_mtx, 0); 676 callout_init_mtx(&sc->scan_timeout, &sc->sc_mtx, 0); 677 callout_init_mtx(&sc->watchdog_to, &sc->sc_mtx, 0); 678 TASK_INIT(&sc->sc_rftoggle_task, 0, iwn_rftoggle_task, sc); 679 TASK_INIT(&sc->sc_panic_task, 0, iwn_panicked, sc); 680 TASK_INIT(&sc->sc_xmit_task, 0, iwn_xmit_task, sc); 681 682 mbufq_init(&sc->sc_xmit_queue, 1024); 683 684 sc->sc_tq = taskqueue_create("iwn_taskq", M_WAITOK, 685 taskqueue_thread_enqueue, &sc->sc_tq); 686 error = taskqueue_start_threads(&sc->sc_tq, 1, 0, "iwn_taskq"); 687 if (error != 0) { 688 device_printf(dev, "can't start threads, error %d\n", error); 689 goto fail; 690 } 691 692 iwn_sysctlattach(sc); 693 694 /* 695 * Hook our interrupt after all initialization is complete. 696 */ 697 error = bus_setup_intr(dev, sc->irq, INTR_TYPE_NET | INTR_MPSAFE, 698 NULL, iwn_intr, sc, &sc->sc_ih); 699 if (error != 0) { 700 device_printf(dev, "can't establish interrupt, error %d\n", 701 error); 702 goto fail; 703 } 704 705 #if 0 706 device_printf(sc->sc_dev, "%s: rx_stats=%d, rx_stats_bt=%d\n", 707 __func__, 708 sizeof(struct iwn_stats), 709 sizeof(struct iwn_stats_bt)); 710 #endif 711 712 if (bootverbose) 713 ieee80211_announce(ic); 714 DPRINTF(sc, IWN_DEBUG_TRACE, "->%s: end\n",__func__); 715 716 /* Add debug ioctl right at the end */ 717 sc->sc_cdev = make_dev(&iwn_cdevsw, device_get_unit(dev), 718 UID_ROOT, GID_WHEEL, 0600, "%s", device_get_nameunit(dev)); 719 if (sc->sc_cdev == NULL) { 720 device_printf(dev, "failed to create debug character device\n"); 721 } else { 722 sc->sc_cdev->si_drv1 = sc; 723 } 724 return 0; 725 fail: 726 iwn_detach(dev); 727 DPRINTF(sc, IWN_DEBUG_TRACE, "->%s: end in error\n",__func__); 728 return error; 729 } 730 731 /* 732 * Define specific configuration based on device id and subdevice id 733 * pid : PCI device id 734 */ 735 static int 736 iwn_config_specific(struct iwn_softc *sc, uint16_t pid) 737 { 738 739 switch (pid) { 740 /* 4965 series */ 741 case IWN_DID_4965_1: 742 case IWN_DID_4965_2: 743 case IWN_DID_4965_3: 744 case IWN_DID_4965_4: 745 sc->base_params = &iwn4965_base_params; 746 sc->limits = &iwn4965_sensitivity_limits; 747 sc->fwname = "iwn4965fw"; 748 /* Override chains masks, ROM is known to be broken. */ 749 sc->txchainmask = IWN_ANT_AB; 750 sc->rxchainmask = IWN_ANT_ABC; 751 /* Enable normal btcoex */ 752 sc->sc_flags |= IWN_FLAG_BTCOEX; 753 break; 754 /* 1000 Series */ 755 case IWN_DID_1000_1: 756 case IWN_DID_1000_2: 757 switch(sc->subdevice_id) { 758 case IWN_SDID_1000_1: 759 case IWN_SDID_1000_2: 760 case IWN_SDID_1000_3: 761 case IWN_SDID_1000_4: 762 case IWN_SDID_1000_5: 763 case IWN_SDID_1000_6: 764 case IWN_SDID_1000_7: 765 case IWN_SDID_1000_8: 766 case IWN_SDID_1000_9: 767 case IWN_SDID_1000_10: 768 case IWN_SDID_1000_11: 769 case IWN_SDID_1000_12: 770 sc->limits = &iwn1000_sensitivity_limits; 771 sc->base_params = &iwn1000_base_params; 772 sc->fwname = "iwn1000fw"; 773 break; 774 default: 775 device_printf(sc->sc_dev, "adapter type id : 0x%04x sub id :" 776 "0x%04x rev %d not supported (subdevice)\n", pid, 777 sc->subdevice_id,sc->hw_type); 778 return ENOTSUP; 779 } 780 break; 781 /* 6x00 Series */ 782 case IWN_DID_6x00_2: 783 case IWN_DID_6x00_4: 784 case IWN_DID_6x00_1: 785 case IWN_DID_6x00_3: 786 sc->fwname = "iwn6000fw"; 787 sc->limits = &iwn6000_sensitivity_limits; 788 switch(sc->subdevice_id) { 789 case IWN_SDID_6x00_1: 790 case IWN_SDID_6x00_2: 791 case IWN_SDID_6x00_8: 792 //iwl6000_3agn_cfg 793 sc->base_params = &iwn_6000_base_params; 794 break; 795 case IWN_SDID_6x00_3: 796 case IWN_SDID_6x00_6: 797 case IWN_SDID_6x00_9: 798 ////iwl6000i_2agn 799 case IWN_SDID_6x00_4: 800 case IWN_SDID_6x00_7: 801 case IWN_SDID_6x00_10: 802 //iwl6000i_2abg_cfg 803 case IWN_SDID_6x00_5: 804 //iwl6000i_2bg_cfg 805 sc->base_params = &iwn_6000i_base_params; 806 sc->sc_flags |= IWN_FLAG_INTERNAL_PA; 807 sc->txchainmask = IWN_ANT_BC; 808 sc->rxchainmask = IWN_ANT_BC; 809 break; 810 default: 811 device_printf(sc->sc_dev, "adapter type id : 0x%04x sub id :" 812 "0x%04x rev %d not supported (subdevice)\n", pid, 813 sc->subdevice_id,sc->hw_type); 814 return ENOTSUP; 815 } 816 break; 817 /* 6x05 Series */ 818 case IWN_DID_6x05_1: 819 case IWN_DID_6x05_2: 820 switch(sc->subdevice_id) { 821 case IWN_SDID_6x05_1: 822 case IWN_SDID_6x05_4: 823 case IWN_SDID_6x05_6: 824 //iwl6005_2agn_cfg 825 case IWN_SDID_6x05_2: 826 case IWN_SDID_6x05_5: 827 case IWN_SDID_6x05_7: 828 //iwl6005_2abg_cfg 829 case IWN_SDID_6x05_3: 830 //iwl6005_2bg_cfg 831 case IWN_SDID_6x05_8: 832 case IWN_SDID_6x05_9: 833 //iwl6005_2agn_sff_cfg 834 case IWN_SDID_6x05_10: 835 //iwl6005_2agn_d_cfg 836 case IWN_SDID_6x05_11: 837 //iwl6005_2agn_mow1_cfg 838 case IWN_SDID_6x05_12: 839 //iwl6005_2agn_mow2_cfg 840 sc->fwname = "iwn6000g2afw"; 841 sc->limits = &iwn6000_sensitivity_limits; 842 sc->base_params = &iwn_6000g2_base_params; 843 break; 844 default: 845 device_printf(sc->sc_dev, "adapter type id : 0x%04x sub id :" 846 "0x%04x rev %d not supported (subdevice)\n", pid, 847 sc->subdevice_id,sc->hw_type); 848 return ENOTSUP; 849 } 850 break; 851 /* 6x35 Series */ 852 case IWN_DID_6035_1: 853 case IWN_DID_6035_2: 854 switch(sc->subdevice_id) { 855 case IWN_SDID_6035_1: 856 case IWN_SDID_6035_2: 857 case IWN_SDID_6035_3: 858 case IWN_SDID_6035_4: 859 sc->fwname = "iwn6000g2bfw"; 860 sc->limits = &iwn6235_sensitivity_limits; 861 sc->base_params = &iwn_6235_base_params; 862 break; 863 default: 864 device_printf(sc->sc_dev, "adapter type id : 0x%04x sub id :" 865 "0x%04x rev %d not supported (subdevice)\n", pid, 866 sc->subdevice_id,sc->hw_type); 867 return ENOTSUP; 868 } 869 break; 870 /* 6x50 WiFi/WiMax Series */ 871 case IWN_DID_6050_1: 872 case IWN_DID_6050_2: 873 switch(sc->subdevice_id) { 874 case IWN_SDID_6050_1: 875 case IWN_SDID_6050_3: 876 case IWN_SDID_6050_5: 877 //iwl6050_2agn_cfg 878 case IWN_SDID_6050_2: 879 case IWN_SDID_6050_4: 880 case IWN_SDID_6050_6: 881 //iwl6050_2abg_cfg 882 sc->fwname = "iwn6050fw"; 883 sc->txchainmask = IWN_ANT_AB; 884 sc->rxchainmask = IWN_ANT_AB; 885 sc->limits = &iwn6000_sensitivity_limits; 886 sc->base_params = &iwn_6050_base_params; 887 break; 888 default: 889 device_printf(sc->sc_dev, "adapter type id : 0x%04x sub id :" 890 "0x%04x rev %d not supported (subdevice)\n", pid, 891 sc->subdevice_id,sc->hw_type); 892 return ENOTSUP; 893 } 894 break; 895 /* 6150 WiFi/WiMax Series */ 896 case IWN_DID_6150_1: 897 case IWN_DID_6150_2: 898 switch(sc->subdevice_id) { 899 case IWN_SDID_6150_1: 900 case IWN_SDID_6150_3: 901 case IWN_SDID_6150_5: 902 // iwl6150_bgn_cfg 903 case IWN_SDID_6150_2: 904 case IWN_SDID_6150_4: 905 case IWN_SDID_6150_6: 906 //iwl6150_bg_cfg 907 sc->fwname = "iwn6050fw"; 908 sc->limits = &iwn6000_sensitivity_limits; 909 sc->base_params = &iwn_6150_base_params; 910 break; 911 default: 912 device_printf(sc->sc_dev, "adapter type id : 0x%04x sub id :" 913 "0x%04x rev %d not supported (subdevice)\n", pid, 914 sc->subdevice_id,sc->hw_type); 915 return ENOTSUP; 916 } 917 break; 918 /* 6030 Series and 1030 Series */ 919 case IWN_DID_x030_1: 920 case IWN_DID_x030_2: 921 case IWN_DID_x030_3: 922 case IWN_DID_x030_4: 923 switch(sc->subdevice_id) { 924 case IWN_SDID_x030_1: 925 case IWN_SDID_x030_3: 926 case IWN_SDID_x030_5: 927 // iwl1030_bgn_cfg 928 case IWN_SDID_x030_2: 929 case IWN_SDID_x030_4: 930 case IWN_SDID_x030_6: 931 //iwl1030_bg_cfg 932 case IWN_SDID_x030_7: 933 case IWN_SDID_x030_10: 934 case IWN_SDID_x030_14: 935 //iwl6030_2agn_cfg 936 case IWN_SDID_x030_8: 937 case IWN_SDID_x030_11: 938 case IWN_SDID_x030_15: 939 // iwl6030_2bgn_cfg 940 case IWN_SDID_x030_9: 941 case IWN_SDID_x030_12: 942 case IWN_SDID_x030_16: 943 // iwl6030_2abg_cfg 944 case IWN_SDID_x030_13: 945 //iwl6030_2bg_cfg 946 sc->fwname = "iwn6000g2bfw"; 947 sc->limits = &iwn6000_sensitivity_limits; 948 sc->base_params = &iwn_6000g2b_base_params; 949 break; 950 default: 951 device_printf(sc->sc_dev, "adapter type id : 0x%04x sub id :" 952 "0x%04x rev %d not supported (subdevice)\n", pid, 953 sc->subdevice_id,sc->hw_type); 954 return ENOTSUP; 955 } 956 break; 957 /* 130 Series WiFi */ 958 /* XXX: This series will need adjustment for rate. 959 * see rx_with_siso_diversity in linux kernel 960 */ 961 case IWN_DID_130_1: 962 case IWN_DID_130_2: 963 switch(sc->subdevice_id) { 964 case IWN_SDID_130_1: 965 case IWN_SDID_130_3: 966 case IWN_SDID_130_5: 967 //iwl130_bgn_cfg 968 case IWN_SDID_130_2: 969 case IWN_SDID_130_4: 970 case IWN_SDID_130_6: 971 //iwl130_bg_cfg 972 sc->fwname = "iwn6000g2bfw"; 973 sc->limits = &iwn6000_sensitivity_limits; 974 sc->base_params = &iwn_6000g2b_base_params; 975 break; 976 default: 977 device_printf(sc->sc_dev, "adapter type id : 0x%04x sub id :" 978 "0x%04x rev %d not supported (subdevice)\n", pid, 979 sc->subdevice_id,sc->hw_type); 980 return ENOTSUP; 981 } 982 break; 983 /* 100 Series WiFi */ 984 case IWN_DID_100_1: 985 case IWN_DID_100_2: 986 switch(sc->subdevice_id) { 987 case IWN_SDID_100_1: 988 case IWN_SDID_100_2: 989 case IWN_SDID_100_3: 990 case IWN_SDID_100_4: 991 case IWN_SDID_100_5: 992 case IWN_SDID_100_6: 993 sc->limits = &iwn1000_sensitivity_limits; 994 sc->base_params = &iwn1000_base_params; 995 sc->fwname = "iwn100fw"; 996 break; 997 default: 998 device_printf(sc->sc_dev, "adapter type id : 0x%04x sub id :" 999 "0x%04x rev %d not supported (subdevice)\n", pid, 1000 sc->subdevice_id,sc->hw_type); 1001 return ENOTSUP; 1002 } 1003 break; 1004 1005 /* 105 Series */ 1006 /* XXX: This series will need adjustment for rate. 1007 * see rx_with_siso_diversity in linux kernel 1008 */ 1009 case IWN_DID_105_1: 1010 case IWN_DID_105_2: 1011 switch(sc->subdevice_id) { 1012 case IWN_SDID_105_1: 1013 case IWN_SDID_105_2: 1014 case IWN_SDID_105_3: 1015 //iwl105_bgn_cfg 1016 case IWN_SDID_105_4: 1017 //iwl105_bgn_d_cfg 1018 sc->limits = &iwn2030_sensitivity_limits; 1019 sc->base_params = &iwn2000_base_params; 1020 sc->fwname = "iwn105fw"; 1021 break; 1022 default: 1023 device_printf(sc->sc_dev, "adapter type id : 0x%04x sub id :" 1024 "0x%04x rev %d not supported (subdevice)\n", pid, 1025 sc->subdevice_id,sc->hw_type); 1026 return ENOTSUP; 1027 } 1028 break; 1029 1030 /* 135 Series */ 1031 /* XXX: This series will need adjustment for rate. 1032 * see rx_with_siso_diversity in linux kernel 1033 */ 1034 case IWN_DID_135_1: 1035 case IWN_DID_135_2: 1036 switch(sc->subdevice_id) { 1037 case IWN_SDID_135_1: 1038 case IWN_SDID_135_2: 1039 case IWN_SDID_135_3: 1040 sc->limits = &iwn2030_sensitivity_limits; 1041 sc->base_params = &iwn2030_base_params; 1042 sc->fwname = "iwn135fw"; 1043 break; 1044 default: 1045 device_printf(sc->sc_dev, "adapter type id : 0x%04x sub id :" 1046 "0x%04x rev %d not supported (subdevice)\n", pid, 1047 sc->subdevice_id,sc->hw_type); 1048 return ENOTSUP; 1049 } 1050 break; 1051 1052 /* 2x00 Series */ 1053 case IWN_DID_2x00_1: 1054 case IWN_DID_2x00_2: 1055 switch(sc->subdevice_id) { 1056 case IWN_SDID_2x00_1: 1057 case IWN_SDID_2x00_2: 1058 case IWN_SDID_2x00_3: 1059 //iwl2000_2bgn_cfg 1060 case IWN_SDID_2x00_4: 1061 //iwl2000_2bgn_d_cfg 1062 sc->limits = &iwn2030_sensitivity_limits; 1063 sc->base_params = &iwn2000_base_params; 1064 sc->fwname = "iwn2000fw"; 1065 break; 1066 default: 1067 device_printf(sc->sc_dev, "adapter type id : 0x%04x sub id :" 1068 "0x%04x rev %d not supported (subdevice) \n", 1069 pid, sc->subdevice_id, sc->hw_type); 1070 return ENOTSUP; 1071 } 1072 break; 1073 /* 2x30 Series */ 1074 case IWN_DID_2x30_1: 1075 case IWN_DID_2x30_2: 1076 switch(sc->subdevice_id) { 1077 case IWN_SDID_2x30_1: 1078 case IWN_SDID_2x30_3: 1079 case IWN_SDID_2x30_5: 1080 //iwl100_bgn_cfg 1081 case IWN_SDID_2x30_2: 1082 case IWN_SDID_2x30_4: 1083 case IWN_SDID_2x30_6: 1084 //iwl100_bg_cfg 1085 sc->limits = &iwn2030_sensitivity_limits; 1086 sc->base_params = &iwn2030_base_params; 1087 sc->fwname = "iwn2030fw"; 1088 break; 1089 default: 1090 device_printf(sc->sc_dev, "adapter type id : 0x%04x sub id :" 1091 "0x%04x rev %d not supported (subdevice)\n", pid, 1092 sc->subdevice_id,sc->hw_type); 1093 return ENOTSUP; 1094 } 1095 break; 1096 /* 5x00 Series */ 1097 case IWN_DID_5x00_1: 1098 case IWN_DID_5x00_2: 1099 case IWN_DID_5x00_3: 1100 case IWN_DID_5x00_4: 1101 sc->limits = &iwn5000_sensitivity_limits; 1102 sc->base_params = &iwn5000_base_params; 1103 sc->fwname = "iwn5000fw"; 1104 switch(sc->subdevice_id) { 1105 case IWN_SDID_5x00_1: 1106 case IWN_SDID_5x00_2: 1107 case IWN_SDID_5x00_3: 1108 case IWN_SDID_5x00_4: 1109 case IWN_SDID_5x00_9: 1110 case IWN_SDID_5x00_10: 1111 case IWN_SDID_5x00_11: 1112 case IWN_SDID_5x00_12: 1113 case IWN_SDID_5x00_17: 1114 case IWN_SDID_5x00_18: 1115 case IWN_SDID_5x00_19: 1116 case IWN_SDID_5x00_20: 1117 //iwl5100_agn_cfg 1118 sc->txchainmask = IWN_ANT_B; 1119 sc->rxchainmask = IWN_ANT_AB; 1120 break; 1121 case IWN_SDID_5x00_5: 1122 case IWN_SDID_5x00_6: 1123 case IWN_SDID_5x00_13: 1124 case IWN_SDID_5x00_14: 1125 case IWN_SDID_5x00_21: 1126 case IWN_SDID_5x00_22: 1127 //iwl5100_bgn_cfg 1128 sc->txchainmask = IWN_ANT_B; 1129 sc->rxchainmask = IWN_ANT_AB; 1130 break; 1131 case IWN_SDID_5x00_7: 1132 case IWN_SDID_5x00_8: 1133 case IWN_SDID_5x00_15: 1134 case IWN_SDID_5x00_16: 1135 case IWN_SDID_5x00_23: 1136 case IWN_SDID_5x00_24: 1137 //iwl5100_abg_cfg 1138 sc->txchainmask = IWN_ANT_B; 1139 sc->rxchainmask = IWN_ANT_AB; 1140 break; 1141 case IWN_SDID_5x00_25: 1142 case IWN_SDID_5x00_26: 1143 case IWN_SDID_5x00_27: 1144 case IWN_SDID_5x00_28: 1145 case IWN_SDID_5x00_29: 1146 case IWN_SDID_5x00_30: 1147 case IWN_SDID_5x00_31: 1148 case IWN_SDID_5x00_32: 1149 case IWN_SDID_5x00_33: 1150 case IWN_SDID_5x00_34: 1151 case IWN_SDID_5x00_35: 1152 case IWN_SDID_5x00_36: 1153 //iwl5300_agn_cfg 1154 sc->txchainmask = IWN_ANT_ABC; 1155 sc->rxchainmask = IWN_ANT_ABC; 1156 break; 1157 default: 1158 device_printf(sc->sc_dev, "adapter type id : 0x%04x sub id :" 1159 "0x%04x rev %d not supported (subdevice)\n", pid, 1160 sc->subdevice_id,sc->hw_type); 1161 return ENOTSUP; 1162 } 1163 break; 1164 /* 5x50 Series */ 1165 case IWN_DID_5x50_1: 1166 case IWN_DID_5x50_2: 1167 case IWN_DID_5x50_3: 1168 case IWN_DID_5x50_4: 1169 sc->limits = &iwn5000_sensitivity_limits; 1170 sc->base_params = &iwn5000_base_params; 1171 sc->fwname = "iwn5000fw"; 1172 switch(sc->subdevice_id) { 1173 case IWN_SDID_5x50_1: 1174 case IWN_SDID_5x50_2: 1175 case IWN_SDID_5x50_3: 1176 //iwl5350_agn_cfg 1177 sc->limits = &iwn5000_sensitivity_limits; 1178 sc->base_params = &iwn5000_base_params; 1179 sc->fwname = "iwn5000fw"; 1180 break; 1181 case IWN_SDID_5x50_4: 1182 case IWN_SDID_5x50_5: 1183 case IWN_SDID_5x50_8: 1184 case IWN_SDID_5x50_9: 1185 case IWN_SDID_5x50_10: 1186 case IWN_SDID_5x50_11: 1187 //iwl5150_agn_cfg 1188 case IWN_SDID_5x50_6: 1189 case IWN_SDID_5x50_7: 1190 case IWN_SDID_5x50_12: 1191 case IWN_SDID_5x50_13: 1192 //iwl5150_abg_cfg 1193 sc->limits = &iwn5000_sensitivity_limits; 1194 sc->fwname = "iwn5150fw"; 1195 sc->base_params = &iwn_5x50_base_params; 1196 break; 1197 default: 1198 device_printf(sc->sc_dev, "adapter type id : 0x%04x sub id :" 1199 "0x%04x rev %d not supported (subdevice)\n", pid, 1200 sc->subdevice_id,sc->hw_type); 1201 return ENOTSUP; 1202 } 1203 break; 1204 default: 1205 device_printf(sc->sc_dev, "adapter type id : 0x%04x sub id : 0x%04x" 1206 "rev 0x%08x not supported (device)\n", pid, sc->subdevice_id, 1207 sc->hw_type); 1208 return ENOTSUP; 1209 } 1210 return 0; 1211 } 1212 1213 static int 1214 iwn4965_attach(struct iwn_softc *sc, uint16_t pid) 1215 { 1216 struct iwn_ops *ops = &sc->ops; 1217 1218 DPRINTF(sc, IWN_DEBUG_TRACE, "->%s begin\n", __func__); 1219 ops->load_firmware = iwn4965_load_firmware; 1220 ops->read_eeprom = iwn4965_read_eeprom; 1221 ops->post_alive = iwn4965_post_alive; 1222 ops->nic_config = iwn4965_nic_config; 1223 ops->update_sched = iwn4965_update_sched; 1224 ops->get_temperature = iwn4965_get_temperature; 1225 ops->get_rssi = iwn4965_get_rssi; 1226 ops->set_txpower = iwn4965_set_txpower; 1227 ops->init_gains = iwn4965_init_gains; 1228 ops->set_gains = iwn4965_set_gains; 1229 ops->add_node = iwn4965_add_node; 1230 ops->tx_done = iwn4965_tx_done; 1231 ops->ampdu_tx_start = iwn4965_ampdu_tx_start; 1232 ops->ampdu_tx_stop = iwn4965_ampdu_tx_stop; 1233 sc->ntxqs = IWN4965_NTXQUEUES; 1234 sc->firstaggqueue = IWN4965_FIRSTAGGQUEUE; 1235 sc->ndmachnls = IWN4965_NDMACHNLS; 1236 sc->broadcast_id = IWN4965_ID_BROADCAST; 1237 sc->rxonsz = IWN4965_RXONSZ; 1238 sc->schedsz = IWN4965_SCHEDSZ; 1239 sc->fw_text_maxsz = IWN4965_FW_TEXT_MAXSZ; 1240 sc->fw_data_maxsz = IWN4965_FW_DATA_MAXSZ; 1241 sc->fwsz = IWN4965_FWSZ; 1242 sc->sched_txfact_addr = IWN4965_SCHED_TXFACT; 1243 sc->limits = &iwn4965_sensitivity_limits; 1244 sc->fwname = "iwn4965fw"; 1245 /* Override chains masks, ROM is known to be broken. */ 1246 sc->txchainmask = IWN_ANT_AB; 1247 sc->rxchainmask = IWN_ANT_ABC; 1248 /* Enable normal btcoex */ 1249 sc->sc_flags |= IWN_FLAG_BTCOEX; 1250 1251 DPRINTF(sc, IWN_DEBUG_TRACE, "%s: end\n",__func__); 1252 1253 return 0; 1254 } 1255 1256 static int 1257 iwn5000_attach(struct iwn_softc *sc, uint16_t pid) 1258 { 1259 struct iwn_ops *ops = &sc->ops; 1260 1261 DPRINTF(sc, IWN_DEBUG_TRACE, "->%s begin\n", __func__); 1262 1263 ops->load_firmware = iwn5000_load_firmware; 1264 ops->read_eeprom = iwn5000_read_eeprom; 1265 ops->post_alive = iwn5000_post_alive; 1266 ops->nic_config = iwn5000_nic_config; 1267 ops->update_sched = iwn5000_update_sched; 1268 ops->get_temperature = iwn5000_get_temperature; 1269 ops->get_rssi = iwn5000_get_rssi; 1270 ops->set_txpower = iwn5000_set_txpower; 1271 ops->init_gains = iwn5000_init_gains; 1272 ops->set_gains = iwn5000_set_gains; 1273 ops->add_node = iwn5000_add_node; 1274 ops->tx_done = iwn5000_tx_done; 1275 ops->ampdu_tx_start = iwn5000_ampdu_tx_start; 1276 ops->ampdu_tx_stop = iwn5000_ampdu_tx_stop; 1277 sc->ntxqs = IWN5000_NTXQUEUES; 1278 sc->firstaggqueue = IWN5000_FIRSTAGGQUEUE; 1279 sc->ndmachnls = IWN5000_NDMACHNLS; 1280 sc->broadcast_id = IWN5000_ID_BROADCAST; 1281 sc->rxonsz = IWN5000_RXONSZ; 1282 sc->schedsz = IWN5000_SCHEDSZ; 1283 sc->fw_text_maxsz = IWN5000_FW_TEXT_MAXSZ; 1284 sc->fw_data_maxsz = IWN5000_FW_DATA_MAXSZ; 1285 sc->fwsz = IWN5000_FWSZ; 1286 sc->sched_txfact_addr = IWN5000_SCHED_TXFACT; 1287 sc->reset_noise_gain = IWN5000_PHY_CALIB_RESET_NOISE_GAIN; 1288 sc->noise_gain = IWN5000_PHY_CALIB_NOISE_GAIN; 1289 1290 return 0; 1291 } 1292 1293 /* 1294 * Attach the interface to 802.11 radiotap. 1295 */ 1296 static void 1297 iwn_radiotap_attach(struct iwn_softc *sc) 1298 { 1299 1300 DPRINTF(sc, IWN_DEBUG_TRACE, "->%s begin\n", __func__); 1301 ieee80211_radiotap_attach(&sc->sc_ic, 1302 &sc->sc_txtap.wt_ihdr, sizeof(sc->sc_txtap), 1303 IWN_TX_RADIOTAP_PRESENT, 1304 &sc->sc_rxtap.wr_ihdr, sizeof(sc->sc_rxtap), 1305 IWN_RX_RADIOTAP_PRESENT); 1306 DPRINTF(sc, IWN_DEBUG_TRACE, "->%s end\n", __func__); 1307 } 1308 1309 static void 1310 iwn_sysctlattach(struct iwn_softc *sc) 1311 { 1312 #ifdef IWN_DEBUG 1313 struct sysctl_ctx_list *ctx = device_get_sysctl_ctx(sc->sc_dev); 1314 struct sysctl_oid *tree = device_get_sysctl_tree(sc->sc_dev); 1315 1316 SYSCTL_ADD_INT(ctx, SYSCTL_CHILDREN(tree), OID_AUTO, 1317 "debug", CTLFLAG_RW, &sc->sc_debug, sc->sc_debug, 1318 "control debugging printfs"); 1319 #endif 1320 } 1321 1322 static struct ieee80211vap * 1323 iwn_vap_create(struct ieee80211com *ic, const char name[IFNAMSIZ], int unit, 1324 enum ieee80211_opmode opmode, int flags, 1325 const uint8_t bssid[IEEE80211_ADDR_LEN], 1326 const uint8_t mac[IEEE80211_ADDR_LEN]) 1327 { 1328 struct iwn_softc *sc = ic->ic_softc; 1329 struct iwn_vap *ivp; 1330 struct ieee80211vap *vap; 1331 1332 if (!TAILQ_EMPTY(&ic->ic_vaps)) /* only one at a time */ 1333 return NULL; 1334 1335 ivp = malloc(sizeof(struct iwn_vap), M_80211_VAP, M_WAITOK | M_ZERO); 1336 vap = &ivp->iv_vap; 1337 ieee80211_vap_setup(ic, vap, name, unit, opmode, flags, bssid); 1338 ivp->ctx = IWN_RXON_BSS_CTX; 1339 vap->iv_bmissthreshold = 10; /* override default */ 1340 /* Override with driver methods. */ 1341 ivp->iv_newstate = vap->iv_newstate; 1342 vap->iv_newstate = iwn_newstate; 1343 sc->ivap[IWN_RXON_BSS_CTX] = vap; 1344 1345 ieee80211_ratectl_init(vap); 1346 /* Complete setup. */ 1347 ieee80211_vap_attach(vap, iwn_media_change, ieee80211_media_status, 1348 mac); 1349 ic->ic_opmode = opmode; 1350 return vap; 1351 } 1352 1353 static void 1354 iwn_vap_delete(struct ieee80211vap *vap) 1355 { 1356 struct iwn_vap *ivp = IWN_VAP(vap); 1357 1358 ieee80211_ratectl_deinit(vap); 1359 ieee80211_vap_detach(vap); 1360 free(ivp, M_80211_VAP); 1361 } 1362 1363 static void 1364 iwn_xmit_queue_drain(struct iwn_softc *sc) 1365 { 1366 struct mbuf *m; 1367 struct ieee80211_node *ni; 1368 1369 IWN_LOCK_ASSERT(sc); 1370 while ((m = mbufq_dequeue(&sc->sc_xmit_queue)) != NULL) { 1371 ni = (struct ieee80211_node *)m->m_pkthdr.rcvif; 1372 ieee80211_free_node(ni); 1373 m_freem(m); 1374 } 1375 } 1376 1377 static int 1378 iwn_xmit_queue_enqueue(struct iwn_softc *sc, struct mbuf *m) 1379 { 1380 1381 IWN_LOCK_ASSERT(sc); 1382 return (mbufq_enqueue(&sc->sc_xmit_queue, m)); 1383 } 1384 1385 static int 1386 iwn_detach(device_t dev) 1387 { 1388 struct iwn_softc *sc = device_get_softc(dev); 1389 int qid; 1390 1391 DPRINTF(sc, IWN_DEBUG_TRACE, "->%s begin\n", __func__); 1392 1393 if (sc->sc_ic.ic_softc != NULL) { 1394 /* Free the mbuf queue and node references */ 1395 IWN_LOCK(sc); 1396 iwn_xmit_queue_drain(sc); 1397 IWN_UNLOCK(sc); 1398 1399 iwn_stop(sc); 1400 1401 taskqueue_drain_all(sc->sc_tq); 1402 taskqueue_free(sc->sc_tq); 1403 1404 callout_drain(&sc->watchdog_to); 1405 callout_drain(&sc->scan_timeout); 1406 callout_drain(&sc->calib_to); 1407 ieee80211_ifdetach(&sc->sc_ic); 1408 } 1409 1410 /* Uninstall interrupt handler. */ 1411 if (sc->irq != NULL) { 1412 bus_teardown_intr(dev, sc->irq, sc->sc_ih); 1413 bus_release_resource(dev, SYS_RES_IRQ, rman_get_rid(sc->irq), 1414 sc->irq); 1415 pci_release_msi(dev); 1416 } 1417 1418 /* Free DMA resources. */ 1419 iwn_free_rx_ring(sc, &sc->rxq); 1420 for (qid = 0; qid < sc->ntxqs; qid++) 1421 iwn_free_tx_ring(sc, &sc->txq[qid]); 1422 iwn_free_sched(sc); 1423 iwn_free_kw(sc); 1424 if (sc->ict != NULL) 1425 iwn_free_ict(sc); 1426 iwn_free_fwmem(sc); 1427 1428 if (sc->mem != NULL) 1429 bus_release_resource(dev, SYS_RES_MEMORY, 1430 rman_get_rid(sc->mem), sc->mem); 1431 1432 if (sc->sc_cdev) { 1433 destroy_dev(sc->sc_cdev); 1434 sc->sc_cdev = NULL; 1435 } 1436 1437 DPRINTF(sc, IWN_DEBUG_TRACE, "->%s: end\n", __func__); 1438 IWN_LOCK_DESTROY(sc); 1439 return 0; 1440 } 1441 1442 static int 1443 iwn_shutdown(device_t dev) 1444 { 1445 struct iwn_softc *sc = device_get_softc(dev); 1446 1447 iwn_stop(sc); 1448 return 0; 1449 } 1450 1451 static int 1452 iwn_suspend(device_t dev) 1453 { 1454 struct iwn_softc *sc = device_get_softc(dev); 1455 1456 ieee80211_suspend_all(&sc->sc_ic); 1457 return 0; 1458 } 1459 1460 static int 1461 iwn_resume(device_t dev) 1462 { 1463 struct iwn_softc *sc = device_get_softc(dev); 1464 1465 /* Clear device-specific "PCI retry timeout" register (41h). */ 1466 pci_write_config(dev, 0x41, 0, 1); 1467 1468 ieee80211_resume_all(&sc->sc_ic); 1469 return 0; 1470 } 1471 1472 static int 1473 iwn_nic_lock(struct iwn_softc *sc) 1474 { 1475 int ntries; 1476 1477 /* Request exclusive access to NIC. */ 1478 IWN_SETBITS(sc, IWN_GP_CNTRL, IWN_GP_CNTRL_MAC_ACCESS_REQ); 1479 1480 /* Spin until we actually get the lock. */ 1481 for (ntries = 0; ntries < 1000; ntries++) { 1482 if ((IWN_READ(sc, IWN_GP_CNTRL) & 1483 (IWN_GP_CNTRL_MAC_ACCESS_ENA | IWN_GP_CNTRL_SLEEP)) == 1484 IWN_GP_CNTRL_MAC_ACCESS_ENA) 1485 return 0; 1486 DELAY(10); 1487 } 1488 return ETIMEDOUT; 1489 } 1490 1491 static __inline void 1492 iwn_nic_unlock(struct iwn_softc *sc) 1493 { 1494 IWN_CLRBITS(sc, IWN_GP_CNTRL, IWN_GP_CNTRL_MAC_ACCESS_REQ); 1495 } 1496 1497 static __inline uint32_t 1498 iwn_prph_read(struct iwn_softc *sc, uint32_t addr) 1499 { 1500 IWN_WRITE(sc, IWN_PRPH_RADDR, IWN_PRPH_DWORD | addr); 1501 IWN_BARRIER_READ_WRITE(sc); 1502 return IWN_READ(sc, IWN_PRPH_RDATA); 1503 } 1504 1505 static __inline void 1506 iwn_prph_write(struct iwn_softc *sc, uint32_t addr, uint32_t data) 1507 { 1508 IWN_WRITE(sc, IWN_PRPH_WADDR, IWN_PRPH_DWORD | addr); 1509 IWN_BARRIER_WRITE(sc); 1510 IWN_WRITE(sc, IWN_PRPH_WDATA, data); 1511 } 1512 1513 static __inline void 1514 iwn_prph_setbits(struct iwn_softc *sc, uint32_t addr, uint32_t mask) 1515 { 1516 iwn_prph_write(sc, addr, iwn_prph_read(sc, addr) | mask); 1517 } 1518 1519 static __inline void 1520 iwn_prph_clrbits(struct iwn_softc *sc, uint32_t addr, uint32_t mask) 1521 { 1522 iwn_prph_write(sc, addr, iwn_prph_read(sc, addr) & ~mask); 1523 } 1524 1525 static __inline void 1526 iwn_prph_write_region_4(struct iwn_softc *sc, uint32_t addr, 1527 const uint32_t *data, int count) 1528 { 1529 for (; count > 0; count--, data++, addr += 4) 1530 iwn_prph_write(sc, addr, *data); 1531 } 1532 1533 static __inline uint32_t 1534 iwn_mem_read(struct iwn_softc *sc, uint32_t addr) 1535 { 1536 IWN_WRITE(sc, IWN_MEM_RADDR, addr); 1537 IWN_BARRIER_READ_WRITE(sc); 1538 return IWN_READ(sc, IWN_MEM_RDATA); 1539 } 1540 1541 static __inline void 1542 iwn_mem_write(struct iwn_softc *sc, uint32_t addr, uint32_t data) 1543 { 1544 IWN_WRITE(sc, IWN_MEM_WADDR, addr); 1545 IWN_BARRIER_WRITE(sc); 1546 IWN_WRITE(sc, IWN_MEM_WDATA, data); 1547 } 1548 1549 static __inline void 1550 iwn_mem_write_2(struct iwn_softc *sc, uint32_t addr, uint16_t data) 1551 { 1552 uint32_t tmp; 1553 1554 tmp = iwn_mem_read(sc, addr & ~3); 1555 if (addr & 3) 1556 tmp = (tmp & 0x0000ffff) | data << 16; 1557 else 1558 tmp = (tmp & 0xffff0000) | data; 1559 iwn_mem_write(sc, addr & ~3, tmp); 1560 } 1561 1562 static __inline void 1563 iwn_mem_read_region_4(struct iwn_softc *sc, uint32_t addr, uint32_t *data, 1564 int count) 1565 { 1566 for (; count > 0; count--, addr += 4) 1567 *data++ = iwn_mem_read(sc, addr); 1568 } 1569 1570 static __inline void 1571 iwn_mem_set_region_4(struct iwn_softc *sc, uint32_t addr, uint32_t val, 1572 int count) 1573 { 1574 for (; count > 0; count--, addr += 4) 1575 iwn_mem_write(sc, addr, val); 1576 } 1577 1578 static int 1579 iwn_eeprom_lock(struct iwn_softc *sc) 1580 { 1581 int i, ntries; 1582 1583 for (i = 0; i < 100; i++) { 1584 /* Request exclusive access to EEPROM. */ 1585 IWN_SETBITS(sc, IWN_HW_IF_CONFIG, 1586 IWN_HW_IF_CONFIG_EEPROM_LOCKED); 1587 1588 /* Spin until we actually get the lock. */ 1589 for (ntries = 0; ntries < 100; ntries++) { 1590 if (IWN_READ(sc, IWN_HW_IF_CONFIG) & 1591 IWN_HW_IF_CONFIG_EEPROM_LOCKED) 1592 return 0; 1593 DELAY(10); 1594 } 1595 } 1596 DPRINTF(sc, IWN_DEBUG_TRACE, "->%s end timeout\n", __func__); 1597 return ETIMEDOUT; 1598 } 1599 1600 static __inline void 1601 iwn_eeprom_unlock(struct iwn_softc *sc) 1602 { 1603 IWN_CLRBITS(sc, IWN_HW_IF_CONFIG, IWN_HW_IF_CONFIG_EEPROM_LOCKED); 1604 } 1605 1606 /* 1607 * Initialize access by host to One Time Programmable ROM. 1608 * NB: This kind of ROM can be found on 1000 or 6000 Series only. 1609 */ 1610 static int 1611 iwn_init_otprom(struct iwn_softc *sc) 1612 { 1613 uint16_t prev, base, next; 1614 int count, error; 1615 1616 DPRINTF(sc, IWN_DEBUG_TRACE, "->%s begin\n", __func__); 1617 1618 /* Wait for clock stabilization before accessing prph. */ 1619 if ((error = iwn_clock_wait(sc)) != 0) 1620 return error; 1621 1622 if ((error = iwn_nic_lock(sc)) != 0) 1623 return error; 1624 iwn_prph_setbits(sc, IWN_APMG_PS, IWN_APMG_PS_RESET_REQ); 1625 DELAY(5); 1626 iwn_prph_clrbits(sc, IWN_APMG_PS, IWN_APMG_PS_RESET_REQ); 1627 iwn_nic_unlock(sc); 1628 1629 /* Set auto clock gate disable bit for HW with OTP shadow RAM. */ 1630 if (sc->base_params->shadow_ram_support) { 1631 IWN_SETBITS(sc, IWN_DBG_LINK_PWR_MGMT, 1632 IWN_RESET_LINK_PWR_MGMT_DIS); 1633 } 1634 IWN_CLRBITS(sc, IWN_EEPROM_GP, IWN_EEPROM_GP_IF_OWNER); 1635 /* Clear ECC status. */ 1636 IWN_SETBITS(sc, IWN_OTP_GP, 1637 IWN_OTP_GP_ECC_CORR_STTS | IWN_OTP_GP_ECC_UNCORR_STTS); 1638 1639 /* 1640 * Find the block before last block (contains the EEPROM image) 1641 * for HW without OTP shadow RAM. 1642 */ 1643 if (! sc->base_params->shadow_ram_support) { 1644 /* Switch to absolute addressing mode. */ 1645 IWN_CLRBITS(sc, IWN_OTP_GP, IWN_OTP_GP_RELATIVE_ACCESS); 1646 base = prev = 0; 1647 for (count = 0; count < sc->base_params->max_ll_items; 1648 count++) { 1649 error = iwn_read_prom_data(sc, base, &next, 2); 1650 if (error != 0) 1651 return error; 1652 if (next == 0) /* End of linked-list. */ 1653 break; 1654 prev = base; 1655 base = le16toh(next); 1656 } 1657 if (count == 0 || count == sc->base_params->max_ll_items) 1658 return EIO; 1659 /* Skip "next" word. */ 1660 sc->prom_base = prev + 1; 1661 } 1662 1663 DPRINTF(sc, IWN_DEBUG_TRACE, "->%s end\n", __func__); 1664 1665 return 0; 1666 } 1667 1668 static int 1669 iwn_read_prom_data(struct iwn_softc *sc, uint32_t addr, void *data, int count) 1670 { 1671 uint8_t *out = data; 1672 uint32_t val, tmp; 1673 int ntries; 1674 1675 DPRINTF(sc, IWN_DEBUG_TRACE, "->%s begin\n", __func__); 1676 1677 addr += sc->prom_base; 1678 for (; count > 0; count -= 2, addr++) { 1679 IWN_WRITE(sc, IWN_EEPROM, addr << 2); 1680 for (ntries = 0; ntries < 10; ntries++) { 1681 val = IWN_READ(sc, IWN_EEPROM); 1682 if (val & IWN_EEPROM_READ_VALID) 1683 break; 1684 DELAY(5); 1685 } 1686 if (ntries == 10) { 1687 device_printf(sc->sc_dev, 1688 "timeout reading ROM at 0x%x\n", addr); 1689 return ETIMEDOUT; 1690 } 1691 if (sc->sc_flags & IWN_FLAG_HAS_OTPROM) { 1692 /* OTPROM, check for ECC errors. */ 1693 tmp = IWN_READ(sc, IWN_OTP_GP); 1694 if (tmp & IWN_OTP_GP_ECC_UNCORR_STTS) { 1695 device_printf(sc->sc_dev, 1696 "OTPROM ECC error at 0x%x\n", addr); 1697 return EIO; 1698 } 1699 if (tmp & IWN_OTP_GP_ECC_CORR_STTS) { 1700 /* Correctable ECC error, clear bit. */ 1701 IWN_SETBITS(sc, IWN_OTP_GP, 1702 IWN_OTP_GP_ECC_CORR_STTS); 1703 } 1704 } 1705 *out++ = val >> 16; 1706 if (count > 1) 1707 *out++ = val >> 24; 1708 } 1709 1710 DPRINTF(sc, IWN_DEBUG_TRACE, "->%s end\n", __func__); 1711 1712 return 0; 1713 } 1714 1715 static void 1716 iwn_dma_map_addr(void *arg, bus_dma_segment_t *segs, int nsegs, int error) 1717 { 1718 if (error != 0) 1719 return; 1720 KASSERT(nsegs == 1, ("too many DMA segments, %d should be 1", nsegs)); 1721 *(bus_addr_t *)arg = segs[0].ds_addr; 1722 } 1723 1724 static int 1725 iwn_dma_contig_alloc(struct iwn_softc *sc, struct iwn_dma_info *dma, 1726 void **kvap, bus_size_t size, bus_size_t alignment) 1727 { 1728 int error; 1729 1730 dma->tag = NULL; 1731 dma->size = size; 1732 1733 error = bus_dma_tag_create(bus_get_dma_tag(sc->sc_dev), alignment, 1734 0, BUS_SPACE_MAXADDR_32BIT, BUS_SPACE_MAXADDR, NULL, NULL, size, 1735 1, size, 0, NULL, NULL, &dma->tag); 1736 if (error != 0) 1737 goto fail; 1738 1739 error = bus_dmamem_alloc(dma->tag, (void **)&dma->vaddr, 1740 BUS_DMA_NOWAIT | BUS_DMA_ZERO | BUS_DMA_COHERENT, &dma->map); 1741 if (error != 0) 1742 goto fail; 1743 1744 error = bus_dmamap_load(dma->tag, dma->map, dma->vaddr, size, 1745 iwn_dma_map_addr, &dma->paddr, BUS_DMA_NOWAIT); 1746 if (error != 0) 1747 goto fail; 1748 1749 bus_dmamap_sync(dma->tag, dma->map, BUS_DMASYNC_PREWRITE); 1750 1751 if (kvap != NULL) 1752 *kvap = dma->vaddr; 1753 1754 return 0; 1755 1756 fail: iwn_dma_contig_free(dma); 1757 return error; 1758 } 1759 1760 static void 1761 iwn_dma_contig_free(struct iwn_dma_info *dma) 1762 { 1763 if (dma->vaddr != NULL) { 1764 bus_dmamap_sync(dma->tag, dma->map, 1765 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); 1766 bus_dmamap_unload(dma->tag, dma->map); 1767 bus_dmamem_free(dma->tag, dma->vaddr, dma->map); 1768 dma->vaddr = NULL; 1769 } 1770 if (dma->tag != NULL) { 1771 bus_dma_tag_destroy(dma->tag); 1772 dma->tag = NULL; 1773 } 1774 } 1775 1776 static int 1777 iwn_alloc_sched(struct iwn_softc *sc) 1778 { 1779 /* TX scheduler rings must be aligned on a 1KB boundary. */ 1780 return iwn_dma_contig_alloc(sc, &sc->sched_dma, (void **)&sc->sched, 1781 sc->schedsz, 1024); 1782 } 1783 1784 static void 1785 iwn_free_sched(struct iwn_softc *sc) 1786 { 1787 iwn_dma_contig_free(&sc->sched_dma); 1788 } 1789 1790 static int 1791 iwn_alloc_kw(struct iwn_softc *sc) 1792 { 1793 /* "Keep Warm" page must be aligned on a 4KB boundary. */ 1794 return iwn_dma_contig_alloc(sc, &sc->kw_dma, NULL, 4096, 4096); 1795 } 1796 1797 static void 1798 iwn_free_kw(struct iwn_softc *sc) 1799 { 1800 iwn_dma_contig_free(&sc->kw_dma); 1801 } 1802 1803 static int 1804 iwn_alloc_ict(struct iwn_softc *sc) 1805 { 1806 /* ICT table must be aligned on a 4KB boundary. */ 1807 return iwn_dma_contig_alloc(sc, &sc->ict_dma, (void **)&sc->ict, 1808 IWN_ICT_SIZE, 4096); 1809 } 1810 1811 static void 1812 iwn_free_ict(struct iwn_softc *sc) 1813 { 1814 iwn_dma_contig_free(&sc->ict_dma); 1815 } 1816 1817 static int 1818 iwn_alloc_fwmem(struct iwn_softc *sc) 1819 { 1820 /* Must be aligned on a 16-byte boundary. */ 1821 return iwn_dma_contig_alloc(sc, &sc->fw_dma, NULL, sc->fwsz, 16); 1822 } 1823 1824 static void 1825 iwn_free_fwmem(struct iwn_softc *sc) 1826 { 1827 iwn_dma_contig_free(&sc->fw_dma); 1828 } 1829 1830 static int 1831 iwn_alloc_rx_ring(struct iwn_softc *sc, struct iwn_rx_ring *ring) 1832 { 1833 bus_size_t size; 1834 int i, error; 1835 1836 ring->cur = 0; 1837 1838 DPRINTF(sc, IWN_DEBUG_TRACE, "->%s begin\n", __func__); 1839 1840 /* Allocate RX descriptors (256-byte aligned). */ 1841 size = IWN_RX_RING_COUNT * sizeof (uint32_t); 1842 error = iwn_dma_contig_alloc(sc, &ring->desc_dma, (void **)&ring->desc, 1843 size, 256); 1844 if (error != 0) { 1845 device_printf(sc->sc_dev, 1846 "%s: could not allocate RX ring DMA memory, error %d\n", 1847 __func__, error); 1848 goto fail; 1849 } 1850 1851 /* Allocate RX status area (16-byte aligned). */ 1852 error = iwn_dma_contig_alloc(sc, &ring->stat_dma, (void **)&ring->stat, 1853 sizeof (struct iwn_rx_status), 16); 1854 if (error != 0) { 1855 device_printf(sc->sc_dev, 1856 "%s: could not allocate RX status DMA memory, error %d\n", 1857 __func__, error); 1858 goto fail; 1859 } 1860 1861 /* Create RX buffer DMA tag. */ 1862 error = bus_dma_tag_create(bus_get_dma_tag(sc->sc_dev), 1, 0, 1863 BUS_SPACE_MAXADDR_32BIT, BUS_SPACE_MAXADDR, NULL, NULL, 1864 IWN_RBUF_SIZE, 1, IWN_RBUF_SIZE, 0, NULL, NULL, &ring->data_dmat); 1865 if (error != 0) { 1866 device_printf(sc->sc_dev, 1867 "%s: could not create RX buf DMA tag, error %d\n", 1868 __func__, error); 1869 goto fail; 1870 } 1871 1872 /* 1873 * Allocate and map RX buffers. 1874 */ 1875 for (i = 0; i < IWN_RX_RING_COUNT; i++) { 1876 struct iwn_rx_data *data = &ring->data[i]; 1877 bus_addr_t paddr; 1878 1879 error = bus_dmamap_create(ring->data_dmat, 0, &data->map); 1880 if (error != 0) { 1881 device_printf(sc->sc_dev, 1882 "%s: could not create RX buf DMA map, error %d\n", 1883 __func__, error); 1884 goto fail; 1885 } 1886 1887 data->m = m_getjcl(M_NOWAIT, MT_DATA, M_PKTHDR, 1888 IWN_RBUF_SIZE); 1889 if (data->m == NULL) { 1890 device_printf(sc->sc_dev, 1891 "%s: could not allocate RX mbuf\n", __func__); 1892 error = ENOBUFS; 1893 goto fail; 1894 } 1895 1896 error = bus_dmamap_load(ring->data_dmat, data->map, 1897 mtod(data->m, void *), IWN_RBUF_SIZE, iwn_dma_map_addr, 1898 &paddr, BUS_DMA_NOWAIT); 1899 if (error != 0 && error != EFBIG) { 1900 device_printf(sc->sc_dev, 1901 "%s: can't map mbuf, error %d\n", __func__, 1902 error); 1903 goto fail; 1904 } 1905 1906 bus_dmamap_sync(ring->data_dmat, data->map, 1907 BUS_DMASYNC_PREREAD); 1908 1909 /* Set physical address of RX buffer (256-byte aligned). */ 1910 ring->desc[i] = htole32(paddr >> 8); 1911 } 1912 1913 bus_dmamap_sync(ring->desc_dma.tag, ring->desc_dma.map, 1914 BUS_DMASYNC_PREWRITE); 1915 1916 DPRINTF(sc, IWN_DEBUG_TRACE, "->%s: end\n",__func__); 1917 1918 return 0; 1919 1920 fail: iwn_free_rx_ring(sc, ring); 1921 1922 DPRINTF(sc, IWN_DEBUG_TRACE, "->%s: end in error\n",__func__); 1923 1924 return error; 1925 } 1926 1927 static void 1928 iwn_reset_rx_ring(struct iwn_softc *sc, struct iwn_rx_ring *ring) 1929 { 1930 int ntries; 1931 1932 DPRINTF(sc, IWN_DEBUG_TRACE, "->Doing %s\n", __func__); 1933 1934 if (iwn_nic_lock(sc) == 0) { 1935 IWN_WRITE(sc, IWN_FH_RX_CONFIG, 0); 1936 for (ntries = 0; ntries < 1000; ntries++) { 1937 if (IWN_READ(sc, IWN_FH_RX_STATUS) & 1938 IWN_FH_RX_STATUS_IDLE) 1939 break; 1940 DELAY(10); 1941 } 1942 iwn_nic_unlock(sc); 1943 } 1944 ring->cur = 0; 1945 sc->last_rx_valid = 0; 1946 } 1947 1948 static void 1949 iwn_free_rx_ring(struct iwn_softc *sc, struct iwn_rx_ring *ring) 1950 { 1951 int i; 1952 1953 DPRINTF(sc, IWN_DEBUG_TRACE, "->Doing %s \n", __func__); 1954 1955 iwn_dma_contig_free(&ring->desc_dma); 1956 iwn_dma_contig_free(&ring->stat_dma); 1957 1958 for (i = 0; i < IWN_RX_RING_COUNT; i++) { 1959 struct iwn_rx_data *data = &ring->data[i]; 1960 1961 if (data->m != NULL) { 1962 bus_dmamap_sync(ring->data_dmat, data->map, 1963 BUS_DMASYNC_POSTREAD); 1964 bus_dmamap_unload(ring->data_dmat, data->map); 1965 m_freem(data->m); 1966 data->m = NULL; 1967 } 1968 if (data->map != NULL) 1969 bus_dmamap_destroy(ring->data_dmat, data->map); 1970 } 1971 if (ring->data_dmat != NULL) { 1972 bus_dma_tag_destroy(ring->data_dmat); 1973 ring->data_dmat = NULL; 1974 } 1975 } 1976 1977 static int 1978 iwn_alloc_tx_ring(struct iwn_softc *sc, struct iwn_tx_ring *ring, int qid) 1979 { 1980 bus_addr_t paddr; 1981 bus_size_t size; 1982 int i, error; 1983 1984 ring->qid = qid; 1985 ring->queued = 0; 1986 ring->cur = 0; 1987 1988 DPRINTF(sc, IWN_DEBUG_TRACE, "->%s begin\n", __func__); 1989 1990 /* Allocate TX descriptors (256-byte aligned). */ 1991 size = IWN_TX_RING_COUNT * sizeof (struct iwn_tx_desc); 1992 error = iwn_dma_contig_alloc(sc, &ring->desc_dma, (void **)&ring->desc, 1993 size, 256); 1994 if (error != 0) { 1995 device_printf(sc->sc_dev, 1996 "%s: could not allocate TX ring DMA memory, error %d\n", 1997 __func__, error); 1998 goto fail; 1999 } 2000 2001 size = IWN_TX_RING_COUNT * sizeof (struct iwn_tx_cmd); 2002 error = iwn_dma_contig_alloc(sc, &ring->cmd_dma, (void **)&ring->cmd, 2003 size, 4); 2004 if (error != 0) { 2005 device_printf(sc->sc_dev, 2006 "%s: could not allocate TX cmd DMA memory, error %d\n", 2007 __func__, error); 2008 goto fail; 2009 } 2010 2011 error = bus_dma_tag_create(bus_get_dma_tag(sc->sc_dev), 1, 0, 2012 BUS_SPACE_MAXADDR_32BIT, BUS_SPACE_MAXADDR, NULL, NULL, MCLBYTES, 2013 IWN_MAX_SCATTER - 1, MCLBYTES, 0, NULL, NULL, &ring->data_dmat); 2014 if (error != 0) { 2015 device_printf(sc->sc_dev, 2016 "%s: could not create TX buf DMA tag, error %d\n", 2017 __func__, error); 2018 goto fail; 2019 } 2020 2021 paddr = ring->cmd_dma.paddr; 2022 for (i = 0; i < IWN_TX_RING_COUNT; i++) { 2023 struct iwn_tx_data *data = &ring->data[i]; 2024 2025 data->cmd_paddr = paddr; 2026 data->scratch_paddr = paddr + 12; 2027 paddr += sizeof (struct iwn_tx_cmd); 2028 2029 error = bus_dmamap_create(ring->data_dmat, 0, &data->map); 2030 if (error != 0) { 2031 device_printf(sc->sc_dev, 2032 "%s: could not create TX buf DMA map, error %d\n", 2033 __func__, error); 2034 goto fail; 2035 } 2036 } 2037 2038 DPRINTF(sc, IWN_DEBUG_TRACE, "->%s end\n", __func__); 2039 2040 return 0; 2041 2042 fail: iwn_free_tx_ring(sc, ring); 2043 DPRINTF(sc, IWN_DEBUG_TRACE, "->%s end in error\n", __func__); 2044 return error; 2045 } 2046 2047 static void 2048 iwn_reset_tx_ring(struct iwn_softc *sc, struct iwn_tx_ring *ring) 2049 { 2050 int i; 2051 2052 DPRINTF(sc, IWN_DEBUG_TRACE, "->doing %s \n", __func__); 2053 2054 for (i = 0; i < IWN_TX_RING_COUNT; i++) { 2055 struct iwn_tx_data *data = &ring->data[i]; 2056 2057 if (data->m != NULL) { 2058 bus_dmamap_sync(ring->data_dmat, data->map, 2059 BUS_DMASYNC_POSTWRITE); 2060 bus_dmamap_unload(ring->data_dmat, data->map); 2061 m_freem(data->m); 2062 data->m = NULL; 2063 } 2064 if (data->ni != NULL) { 2065 ieee80211_free_node(data->ni); 2066 data->ni = NULL; 2067 } 2068 } 2069 /* Clear TX descriptors. */ 2070 memset(ring->desc, 0, ring->desc_dma.size); 2071 bus_dmamap_sync(ring->desc_dma.tag, ring->desc_dma.map, 2072 BUS_DMASYNC_PREWRITE); 2073 sc->qfullmsk &= ~(1 << ring->qid); 2074 ring->queued = 0; 2075 ring->cur = 0; 2076 } 2077 2078 static void 2079 iwn_free_tx_ring(struct iwn_softc *sc, struct iwn_tx_ring *ring) 2080 { 2081 int i; 2082 2083 DPRINTF(sc, IWN_DEBUG_TRACE, "->Doing %s \n", __func__); 2084 2085 iwn_dma_contig_free(&ring->desc_dma); 2086 iwn_dma_contig_free(&ring->cmd_dma); 2087 2088 for (i = 0; i < IWN_TX_RING_COUNT; i++) { 2089 struct iwn_tx_data *data = &ring->data[i]; 2090 2091 if (data->m != NULL) { 2092 bus_dmamap_sync(ring->data_dmat, data->map, 2093 BUS_DMASYNC_POSTWRITE); 2094 bus_dmamap_unload(ring->data_dmat, data->map); 2095 m_freem(data->m); 2096 } 2097 if (data->map != NULL) 2098 bus_dmamap_destroy(ring->data_dmat, data->map); 2099 } 2100 if (ring->data_dmat != NULL) { 2101 bus_dma_tag_destroy(ring->data_dmat); 2102 ring->data_dmat = NULL; 2103 } 2104 } 2105 2106 static void 2107 iwn5000_ict_reset(struct iwn_softc *sc) 2108 { 2109 /* Disable interrupts. */ 2110 IWN_WRITE(sc, IWN_INT_MASK, 0); 2111 2112 /* Reset ICT table. */ 2113 memset(sc->ict, 0, IWN_ICT_SIZE); 2114 sc->ict_cur = 0; 2115 2116 bus_dmamap_sync(sc->ict_dma.tag, sc->ict_dma.map, 2117 BUS_DMASYNC_PREWRITE); 2118 2119 /* Set physical address of ICT table (4KB aligned). */ 2120 DPRINTF(sc, IWN_DEBUG_RESET, "%s: enabling ICT\n", __func__); 2121 IWN_WRITE(sc, IWN_DRAM_INT_TBL, IWN_DRAM_INT_TBL_ENABLE | 2122 IWN_DRAM_INT_TBL_WRAP_CHECK | sc->ict_dma.paddr >> 12); 2123 2124 /* Enable periodic RX interrupt. */ 2125 sc->int_mask |= IWN_INT_RX_PERIODIC; 2126 /* Switch to ICT interrupt mode in driver. */ 2127 sc->sc_flags |= IWN_FLAG_USE_ICT; 2128 2129 /* Re-enable interrupts. */ 2130 IWN_WRITE(sc, IWN_INT, 0xffffffff); 2131 IWN_WRITE(sc, IWN_INT_MASK, sc->int_mask); 2132 } 2133 2134 static int 2135 iwn_read_eeprom(struct iwn_softc *sc, uint8_t macaddr[IEEE80211_ADDR_LEN]) 2136 { 2137 struct iwn_ops *ops = &sc->ops; 2138 uint16_t val; 2139 int error; 2140 2141 DPRINTF(sc, IWN_DEBUG_TRACE, "->%s begin\n", __func__); 2142 2143 /* Check whether adapter has an EEPROM or an OTPROM. */ 2144 if (sc->hw_type >= IWN_HW_REV_TYPE_1000 && 2145 (IWN_READ(sc, IWN_OTP_GP) & IWN_OTP_GP_DEV_SEL_OTP)) 2146 sc->sc_flags |= IWN_FLAG_HAS_OTPROM; 2147 DPRINTF(sc, IWN_DEBUG_RESET, "%s found\n", 2148 (sc->sc_flags & IWN_FLAG_HAS_OTPROM) ? "OTPROM" : "EEPROM"); 2149 2150 /* Adapter has to be powered on for EEPROM access to work. */ 2151 if ((error = iwn_apm_init(sc)) != 0) { 2152 device_printf(sc->sc_dev, 2153 "%s: could not power ON adapter, error %d\n", __func__, 2154 error); 2155 return error; 2156 } 2157 2158 if ((IWN_READ(sc, IWN_EEPROM_GP) & 0x7) == 0) { 2159 device_printf(sc->sc_dev, "%s: bad ROM signature\n", __func__); 2160 return EIO; 2161 } 2162 if ((error = iwn_eeprom_lock(sc)) != 0) { 2163 device_printf(sc->sc_dev, "%s: could not lock ROM, error %d\n", 2164 __func__, error); 2165 return error; 2166 } 2167 if (sc->sc_flags & IWN_FLAG_HAS_OTPROM) { 2168 if ((error = iwn_init_otprom(sc)) != 0) { 2169 device_printf(sc->sc_dev, 2170 "%s: could not initialize OTPROM, error %d\n", 2171 __func__, error); 2172 return error; 2173 } 2174 } 2175 2176 iwn_read_prom_data(sc, IWN_EEPROM_SKU_CAP, &val, 2); 2177 DPRINTF(sc, IWN_DEBUG_RESET, "SKU capabilities=0x%04x\n", le16toh(val)); 2178 /* Check if HT support is bonded out. */ 2179 if (val & htole16(IWN_EEPROM_SKU_CAP_11N)) 2180 sc->sc_flags |= IWN_FLAG_HAS_11N; 2181 2182 iwn_read_prom_data(sc, IWN_EEPROM_RFCFG, &val, 2); 2183 sc->rfcfg = le16toh(val); 2184 DPRINTF(sc, IWN_DEBUG_RESET, "radio config=0x%04x\n", sc->rfcfg); 2185 /* Read Tx/Rx chains from ROM unless it's known to be broken. */ 2186 if (sc->txchainmask == 0) 2187 sc->txchainmask = IWN_RFCFG_TXANTMSK(sc->rfcfg); 2188 if (sc->rxchainmask == 0) 2189 sc->rxchainmask = IWN_RFCFG_RXANTMSK(sc->rfcfg); 2190 2191 /* Read MAC address. */ 2192 iwn_read_prom_data(sc, IWN_EEPROM_MAC, macaddr, 6); 2193 2194 /* Read adapter-specific information from EEPROM. */ 2195 ops->read_eeprom(sc); 2196 2197 iwn_apm_stop(sc); /* Power OFF adapter. */ 2198 2199 iwn_eeprom_unlock(sc); 2200 2201 DPRINTF(sc, IWN_DEBUG_TRACE, "->%s end\n", __func__); 2202 2203 return 0; 2204 } 2205 2206 static void 2207 iwn4965_read_eeprom(struct iwn_softc *sc) 2208 { 2209 uint32_t addr; 2210 uint16_t val; 2211 int i; 2212 2213 DPRINTF(sc, IWN_DEBUG_TRACE, "->%s begin\n", __func__); 2214 2215 /* Read regulatory domain (4 ASCII characters). */ 2216 iwn_read_prom_data(sc, IWN4965_EEPROM_DOMAIN, sc->eeprom_domain, 4); 2217 2218 /* Read the list of authorized channels (20MHz & 40MHz). */ 2219 for (i = 0; i < IWN_NBANDS - 1; i++) { 2220 addr = iwn4965_regulatory_bands[i]; 2221 iwn_read_eeprom_channels(sc, i, addr); 2222 } 2223 2224 /* Read maximum allowed TX power for 2GHz and 5GHz bands. */ 2225 iwn_read_prom_data(sc, IWN4965_EEPROM_MAXPOW, &val, 2); 2226 sc->maxpwr2GHz = val & 0xff; 2227 sc->maxpwr5GHz = val >> 8; 2228 /* Check that EEPROM values are within valid range. */ 2229 if (sc->maxpwr5GHz < 20 || sc->maxpwr5GHz > 50) 2230 sc->maxpwr5GHz = 38; 2231 if (sc->maxpwr2GHz < 20 || sc->maxpwr2GHz > 50) 2232 sc->maxpwr2GHz = 38; 2233 DPRINTF(sc, IWN_DEBUG_RESET, "maxpwr 2GHz=%d 5GHz=%d\n", 2234 sc->maxpwr2GHz, sc->maxpwr5GHz); 2235 2236 /* Read samples for each TX power group. */ 2237 iwn_read_prom_data(sc, IWN4965_EEPROM_BANDS, sc->bands, 2238 sizeof sc->bands); 2239 2240 /* Read voltage at which samples were taken. */ 2241 iwn_read_prom_data(sc, IWN4965_EEPROM_VOLTAGE, &val, 2); 2242 sc->eeprom_voltage = (int16_t)le16toh(val); 2243 DPRINTF(sc, IWN_DEBUG_RESET, "voltage=%d (in 0.3V)\n", 2244 sc->eeprom_voltage); 2245 2246 #ifdef IWN_DEBUG 2247 /* Print samples. */ 2248 if (sc->sc_debug & IWN_DEBUG_ANY) { 2249 for (i = 0; i < IWN_NBANDS - 1; i++) 2250 iwn4965_print_power_group(sc, i); 2251 } 2252 #endif 2253 2254 DPRINTF(sc, IWN_DEBUG_TRACE, "->%s end\n", __func__); 2255 } 2256 2257 #ifdef IWN_DEBUG 2258 static void 2259 iwn4965_print_power_group(struct iwn_softc *sc, int i) 2260 { 2261 struct iwn4965_eeprom_band *band = &sc->bands[i]; 2262 struct iwn4965_eeprom_chan_samples *chans = band->chans; 2263 int j, c; 2264 2265 printf("===band %d===\n", i); 2266 printf("chan lo=%d, chan hi=%d\n", band->lo, band->hi); 2267 printf("chan1 num=%d\n", chans[0].num); 2268 for (c = 0; c < 2; c++) { 2269 for (j = 0; j < IWN_NSAMPLES; j++) { 2270 printf("chain %d, sample %d: temp=%d gain=%d " 2271 "power=%d pa_det=%d\n", c, j, 2272 chans[0].samples[c][j].temp, 2273 chans[0].samples[c][j].gain, 2274 chans[0].samples[c][j].power, 2275 chans[0].samples[c][j].pa_det); 2276 } 2277 } 2278 printf("chan2 num=%d\n", chans[1].num); 2279 for (c = 0; c < 2; c++) { 2280 for (j = 0; j < IWN_NSAMPLES; j++) { 2281 printf("chain %d, sample %d: temp=%d gain=%d " 2282 "power=%d pa_det=%d\n", c, j, 2283 chans[1].samples[c][j].temp, 2284 chans[1].samples[c][j].gain, 2285 chans[1].samples[c][j].power, 2286 chans[1].samples[c][j].pa_det); 2287 } 2288 } 2289 } 2290 #endif 2291 2292 static void 2293 iwn5000_read_eeprom(struct iwn_softc *sc) 2294 { 2295 struct iwn5000_eeprom_calib_hdr hdr; 2296 int32_t volt; 2297 uint32_t base, addr; 2298 uint16_t val; 2299 int i; 2300 2301 DPRINTF(sc, IWN_DEBUG_TRACE, "->%s begin\n", __func__); 2302 2303 /* Read regulatory domain (4 ASCII characters). */ 2304 iwn_read_prom_data(sc, IWN5000_EEPROM_REG, &val, 2); 2305 base = le16toh(val); 2306 iwn_read_prom_data(sc, base + IWN5000_EEPROM_DOMAIN, 2307 sc->eeprom_domain, 4); 2308 2309 /* Read the list of authorized channels (20MHz & 40MHz). */ 2310 for (i = 0; i < IWN_NBANDS - 1; i++) { 2311 addr = base + sc->base_params->regulatory_bands[i]; 2312 iwn_read_eeprom_channels(sc, i, addr); 2313 } 2314 2315 /* Read enhanced TX power information for 6000 Series. */ 2316 if (sc->base_params->enhanced_TX_power) 2317 iwn_read_eeprom_enhinfo(sc); 2318 2319 iwn_read_prom_data(sc, IWN5000_EEPROM_CAL, &val, 2); 2320 base = le16toh(val); 2321 iwn_read_prom_data(sc, base, &hdr, sizeof hdr); 2322 DPRINTF(sc, IWN_DEBUG_CALIBRATE, 2323 "%s: calib version=%u pa type=%u voltage=%u\n", __func__, 2324 hdr.version, hdr.pa_type, le16toh(hdr.volt)); 2325 sc->calib_ver = hdr.version; 2326 2327 if (sc->base_params->calib_need & IWN_FLG_NEED_PHY_CALIB_TEMP_OFFSETv2) { 2328 sc->eeprom_voltage = le16toh(hdr.volt); 2329 iwn_read_prom_data(sc, base + IWN5000_EEPROM_TEMP, &val, 2); 2330 sc->eeprom_temp_high=le16toh(val); 2331 iwn_read_prom_data(sc, base + IWN5000_EEPROM_VOLT, &val, 2); 2332 sc->eeprom_temp = le16toh(val); 2333 } 2334 2335 if (sc->hw_type == IWN_HW_REV_TYPE_5150) { 2336 /* Compute temperature offset. */ 2337 iwn_read_prom_data(sc, base + IWN5000_EEPROM_TEMP, &val, 2); 2338 sc->eeprom_temp = le16toh(val); 2339 iwn_read_prom_data(sc, base + IWN5000_EEPROM_VOLT, &val, 2); 2340 volt = le16toh(val); 2341 sc->temp_off = sc->eeprom_temp - (volt / -5); 2342 DPRINTF(sc, IWN_DEBUG_CALIBRATE, "temp=%d volt=%d offset=%dK\n", 2343 sc->eeprom_temp, volt, sc->temp_off); 2344 } else { 2345 /* Read crystal calibration. */ 2346 iwn_read_prom_data(sc, base + IWN5000_EEPROM_CRYSTAL, 2347 &sc->eeprom_crystal, sizeof (uint32_t)); 2348 DPRINTF(sc, IWN_DEBUG_CALIBRATE, "crystal calibration 0x%08x\n", 2349 le32toh(sc->eeprom_crystal)); 2350 } 2351 2352 DPRINTF(sc, IWN_DEBUG_TRACE, "->%s end\n", __func__); 2353 2354 } 2355 2356 /* 2357 * Translate EEPROM flags to net80211. 2358 */ 2359 static uint32_t 2360 iwn_eeprom_channel_flags(struct iwn_eeprom_chan *channel) 2361 { 2362 uint32_t nflags; 2363 2364 nflags = 0; 2365 if ((channel->flags & IWN_EEPROM_CHAN_ACTIVE) == 0) 2366 nflags |= IEEE80211_CHAN_PASSIVE; 2367 if ((channel->flags & IWN_EEPROM_CHAN_IBSS) == 0) 2368 nflags |= IEEE80211_CHAN_NOADHOC; 2369 if (channel->flags & IWN_EEPROM_CHAN_RADAR) { 2370 nflags |= IEEE80211_CHAN_DFS; 2371 /* XXX apparently IBSS may still be marked */ 2372 nflags |= IEEE80211_CHAN_NOADHOC; 2373 } 2374 2375 return nflags; 2376 } 2377 2378 static void 2379 iwn_read_eeprom_band(struct iwn_softc *sc, int n, int maxchans, int *nchans, 2380 struct ieee80211_channel chans[]) 2381 { 2382 struct iwn_eeprom_chan *channels = sc->eeprom_channels[n]; 2383 const struct iwn_chan_band *band = &iwn_bands[n]; 2384 uint8_t bands[IEEE80211_MODE_BYTES]; 2385 uint8_t chan; 2386 int i, error, nflags; 2387 2388 DPRINTF(sc, IWN_DEBUG_TRACE, "->%s begin\n", __func__); 2389 2390 memset(bands, 0, sizeof(bands)); 2391 if (n == 0) { 2392 setbit(bands, IEEE80211_MODE_11B); 2393 setbit(bands, IEEE80211_MODE_11G); 2394 if (sc->sc_flags & IWN_FLAG_HAS_11N) 2395 setbit(bands, IEEE80211_MODE_11NG); 2396 } else { 2397 setbit(bands, IEEE80211_MODE_11A); 2398 if (sc->sc_flags & IWN_FLAG_HAS_11N) 2399 setbit(bands, IEEE80211_MODE_11NA); 2400 } 2401 2402 for (i = 0; i < band->nchan; i++) { 2403 if (!(channels[i].flags & IWN_EEPROM_CHAN_VALID)) { 2404 DPRINTF(sc, IWN_DEBUG_RESET, 2405 "skip chan %d flags 0x%x maxpwr %d\n", 2406 band->chan[i], channels[i].flags, 2407 channels[i].maxpwr); 2408 continue; 2409 } 2410 2411 chan = band->chan[i]; 2412 nflags = iwn_eeprom_channel_flags(&channels[i]); 2413 error = ieee80211_add_channel(chans, maxchans, nchans, 2414 chan, 0, channels[i].maxpwr, nflags, bands); 2415 if (error != 0) 2416 break; 2417 2418 /* Save maximum allowed TX power for this channel. */ 2419 /* XXX wrong */ 2420 sc->maxpwr[chan] = channels[i].maxpwr; 2421 2422 DPRINTF(sc, IWN_DEBUG_RESET, 2423 "add chan %d flags 0x%x maxpwr %d\n", chan, 2424 channels[i].flags, channels[i].maxpwr); 2425 } 2426 2427 DPRINTF(sc, IWN_DEBUG_TRACE, "->%s end\n", __func__); 2428 2429 } 2430 2431 static void 2432 iwn_read_eeprom_ht40(struct iwn_softc *sc, int n, int maxchans, int *nchans, 2433 struct ieee80211_channel chans[]) 2434 { 2435 struct iwn_eeprom_chan *channels = sc->eeprom_channels[n]; 2436 const struct iwn_chan_band *band = &iwn_bands[n]; 2437 uint8_t chan; 2438 int i, error, nflags; 2439 2440 DPRINTF(sc, IWN_DEBUG_TRACE, "->%s start\n", __func__); 2441 2442 if (!(sc->sc_flags & IWN_FLAG_HAS_11N)) { 2443 DPRINTF(sc, IWN_DEBUG_TRACE, "->%s end no 11n\n", __func__); 2444 return; 2445 } 2446 2447 for (i = 0; i < band->nchan; i++) { 2448 if (!(channels[i].flags & IWN_EEPROM_CHAN_VALID)) { 2449 DPRINTF(sc, IWN_DEBUG_RESET, 2450 "skip chan %d flags 0x%x maxpwr %d\n", 2451 band->chan[i], channels[i].flags, 2452 channels[i].maxpwr); 2453 continue; 2454 } 2455 2456 chan = band->chan[i]; 2457 nflags = iwn_eeprom_channel_flags(&channels[i]); 2458 nflags |= (n == 5 ? IEEE80211_CHAN_G : IEEE80211_CHAN_A); 2459 error = ieee80211_add_channel_ht40(chans, maxchans, nchans, 2460 chan, channels[i].maxpwr, nflags); 2461 switch (error) { 2462 case EINVAL: 2463 device_printf(sc->sc_dev, 2464 "%s: no entry for channel %d\n", __func__, chan); 2465 continue; 2466 case ENOENT: 2467 DPRINTF(sc, IWN_DEBUG_RESET, 2468 "%s: skip chan %d, extension channel not found\n", 2469 __func__, chan); 2470 continue; 2471 case ENOBUFS: 2472 device_printf(sc->sc_dev, 2473 "%s: channel table is full!\n", __func__); 2474 break; 2475 case 0: 2476 DPRINTF(sc, IWN_DEBUG_RESET, 2477 "add ht40 chan %d flags 0x%x maxpwr %d\n", 2478 chan, channels[i].flags, channels[i].maxpwr); 2479 /* FALLTHROUGH */ 2480 default: 2481 break; 2482 } 2483 } 2484 2485 DPRINTF(sc, IWN_DEBUG_TRACE, "->%s end\n", __func__); 2486 2487 } 2488 2489 static void 2490 iwn_read_eeprom_channels(struct iwn_softc *sc, int n, uint32_t addr) 2491 { 2492 struct ieee80211com *ic = &sc->sc_ic; 2493 2494 iwn_read_prom_data(sc, addr, &sc->eeprom_channels[n], 2495 iwn_bands[n].nchan * sizeof (struct iwn_eeprom_chan)); 2496 2497 if (n < 5) { 2498 iwn_read_eeprom_band(sc, n, IEEE80211_CHAN_MAX, &ic->ic_nchans, 2499 ic->ic_channels); 2500 } else { 2501 iwn_read_eeprom_ht40(sc, n, IEEE80211_CHAN_MAX, &ic->ic_nchans, 2502 ic->ic_channels); 2503 } 2504 ieee80211_sort_channels(ic->ic_channels, ic->ic_nchans); 2505 } 2506 2507 static struct iwn_eeprom_chan * 2508 iwn_find_eeprom_channel(struct iwn_softc *sc, struct ieee80211_channel *c) 2509 { 2510 int band, chan, i, j; 2511 2512 if (IEEE80211_IS_CHAN_HT40(c)) { 2513 band = IEEE80211_IS_CHAN_5GHZ(c) ? 6 : 5; 2514 if (IEEE80211_IS_CHAN_HT40D(c)) 2515 chan = c->ic_extieee; 2516 else 2517 chan = c->ic_ieee; 2518 for (i = 0; i < iwn_bands[band].nchan; i++) { 2519 if (iwn_bands[band].chan[i] == chan) 2520 return &sc->eeprom_channels[band][i]; 2521 } 2522 } else { 2523 for (j = 0; j < 5; j++) { 2524 for (i = 0; i < iwn_bands[j].nchan; i++) { 2525 if (iwn_bands[j].chan[i] == c->ic_ieee && 2526 ((j == 0) ^ IEEE80211_IS_CHAN_A(c)) == 1) 2527 return &sc->eeprom_channels[j][i]; 2528 } 2529 } 2530 } 2531 return NULL; 2532 } 2533 2534 static void 2535 iwn_getradiocaps(struct ieee80211com *ic, 2536 int maxchans, int *nchans, struct ieee80211_channel chans[]) 2537 { 2538 struct iwn_softc *sc = ic->ic_softc; 2539 int i; 2540 2541 /* Parse the list of authorized channels. */ 2542 for (i = 0; i < 5 && *nchans < maxchans; i++) 2543 iwn_read_eeprom_band(sc, i, maxchans, nchans, chans); 2544 for (i = 5; i < IWN_NBANDS - 1 && *nchans < maxchans; i++) 2545 iwn_read_eeprom_ht40(sc, i, maxchans, nchans, chans); 2546 } 2547 2548 /* 2549 * Enforce flags read from EEPROM. 2550 */ 2551 static int 2552 iwn_setregdomain(struct ieee80211com *ic, struct ieee80211_regdomain *rd, 2553 int nchan, struct ieee80211_channel chans[]) 2554 { 2555 struct iwn_softc *sc = ic->ic_softc; 2556 int i; 2557 2558 for (i = 0; i < nchan; i++) { 2559 struct ieee80211_channel *c = &chans[i]; 2560 struct iwn_eeprom_chan *channel; 2561 2562 channel = iwn_find_eeprom_channel(sc, c); 2563 if (channel == NULL) { 2564 ic_printf(ic, "%s: invalid channel %u freq %u/0x%x\n", 2565 __func__, c->ic_ieee, c->ic_freq, c->ic_flags); 2566 return EINVAL; 2567 } 2568 c->ic_flags |= iwn_eeprom_channel_flags(channel); 2569 } 2570 2571 return 0; 2572 } 2573 2574 static void 2575 iwn_read_eeprom_enhinfo(struct iwn_softc *sc) 2576 { 2577 struct iwn_eeprom_enhinfo enhinfo[35]; 2578 struct ieee80211com *ic = &sc->sc_ic; 2579 struct ieee80211_channel *c; 2580 uint16_t val, base; 2581 int8_t maxpwr; 2582 uint8_t flags; 2583 int i, j; 2584 2585 DPRINTF(sc, IWN_DEBUG_TRACE, "->%s begin\n", __func__); 2586 2587 iwn_read_prom_data(sc, IWN5000_EEPROM_REG, &val, 2); 2588 base = le16toh(val); 2589 iwn_read_prom_data(sc, base + IWN6000_EEPROM_ENHINFO, 2590 enhinfo, sizeof enhinfo); 2591 2592 for (i = 0; i < nitems(enhinfo); i++) { 2593 flags = enhinfo[i].flags; 2594 if (!(flags & IWN_ENHINFO_VALID)) 2595 continue; /* Skip invalid entries. */ 2596 2597 maxpwr = 0; 2598 if (sc->txchainmask & IWN_ANT_A) 2599 maxpwr = MAX(maxpwr, enhinfo[i].chain[0]); 2600 if (sc->txchainmask & IWN_ANT_B) 2601 maxpwr = MAX(maxpwr, enhinfo[i].chain[1]); 2602 if (sc->txchainmask & IWN_ANT_C) 2603 maxpwr = MAX(maxpwr, enhinfo[i].chain[2]); 2604 if (sc->ntxchains == 2) 2605 maxpwr = MAX(maxpwr, enhinfo[i].mimo2); 2606 else if (sc->ntxchains == 3) 2607 maxpwr = MAX(maxpwr, enhinfo[i].mimo3); 2608 2609 for (j = 0; j < ic->ic_nchans; j++) { 2610 c = &ic->ic_channels[j]; 2611 if ((flags & IWN_ENHINFO_5GHZ)) { 2612 if (!IEEE80211_IS_CHAN_A(c)) 2613 continue; 2614 } else if ((flags & IWN_ENHINFO_OFDM)) { 2615 if (!IEEE80211_IS_CHAN_G(c)) 2616 continue; 2617 } else if (!IEEE80211_IS_CHAN_B(c)) 2618 continue; 2619 if ((flags & IWN_ENHINFO_HT40)) { 2620 if (!IEEE80211_IS_CHAN_HT40(c)) 2621 continue; 2622 } else { 2623 if (IEEE80211_IS_CHAN_HT40(c)) 2624 continue; 2625 } 2626 if (enhinfo[i].chan != 0 && 2627 enhinfo[i].chan != c->ic_ieee) 2628 continue; 2629 2630 DPRINTF(sc, IWN_DEBUG_RESET, 2631 "channel %d(%x), maxpwr %d\n", c->ic_ieee, 2632 c->ic_flags, maxpwr / 2); 2633 c->ic_maxregpower = maxpwr / 2; 2634 c->ic_maxpower = maxpwr; 2635 } 2636 } 2637 2638 DPRINTF(sc, IWN_DEBUG_TRACE, "->%s end\n", __func__); 2639 2640 } 2641 2642 static struct ieee80211_node * 2643 iwn_node_alloc(struct ieee80211vap *vap, const uint8_t mac[IEEE80211_ADDR_LEN]) 2644 { 2645 return malloc(sizeof (struct iwn_node), M_80211_NODE,M_NOWAIT | M_ZERO); 2646 } 2647 2648 static __inline int 2649 rate2plcp(int rate) 2650 { 2651 switch (rate & 0xff) { 2652 case 12: return 0xd; 2653 case 18: return 0xf; 2654 case 24: return 0x5; 2655 case 36: return 0x7; 2656 case 48: return 0x9; 2657 case 72: return 0xb; 2658 case 96: return 0x1; 2659 case 108: return 0x3; 2660 case 2: return 10; 2661 case 4: return 20; 2662 case 11: return 55; 2663 case 22: return 110; 2664 } 2665 return 0; 2666 } 2667 2668 static __inline uint8_t 2669 plcp2rate(const uint8_t rate_plcp) 2670 { 2671 switch (rate_plcp) { 2672 case 0xd: return 12; 2673 case 0xf: return 18; 2674 case 0x5: return 24; 2675 case 0x7: return 36; 2676 case 0x9: return 48; 2677 case 0xb: return 72; 2678 case 0x1: return 96; 2679 case 0x3: return 108; 2680 case 10: return 2; 2681 case 20: return 4; 2682 case 55: return 11; 2683 case 110: return 22; 2684 default: return 0; 2685 } 2686 } 2687 2688 static int 2689 iwn_get_1stream_tx_antmask(struct iwn_softc *sc) 2690 { 2691 2692 return IWN_LSB(sc->txchainmask); 2693 } 2694 2695 static int 2696 iwn_get_2stream_tx_antmask(struct iwn_softc *sc) 2697 { 2698 int tx; 2699 2700 /* 2701 * The '2 stream' setup is a bit .. odd. 2702 * 2703 * For NICs that support only 1 antenna, default to IWN_ANT_AB or 2704 * the firmware panics (eg Intel 5100.) 2705 * 2706 * For NICs that support two antennas, we use ANT_AB. 2707 * 2708 * For NICs that support three antennas, we use the two that 2709 * wasn't the default one. 2710 * 2711 * XXX TODO: if bluetooth (full concurrent) is enabled, restrict 2712 * this to only one antenna. 2713 */ 2714 2715 /* Default - transmit on the other antennas */ 2716 tx = (sc->txchainmask & ~IWN_LSB(sc->txchainmask)); 2717 2718 /* Now, if it's zero, set it to IWN_ANT_AB, so to not panic firmware */ 2719 if (tx == 0) 2720 tx = IWN_ANT_AB; 2721 2722 /* 2723 * If the NIC is a two-stream TX NIC, configure the TX mask to 2724 * the default chainmask 2725 */ 2726 else if (sc->ntxchains == 2) 2727 tx = sc->txchainmask; 2728 2729 return (tx); 2730 } 2731 2732 2733 2734 /* 2735 * Calculate the required PLCP value from the given rate, 2736 * to the given node. 2737 * 2738 * This will take the node configuration (eg 11n, rate table 2739 * setup, etc) into consideration. 2740 */ 2741 static uint32_t 2742 iwn_rate_to_plcp(struct iwn_softc *sc, struct ieee80211_node *ni, 2743 uint8_t rate) 2744 { 2745 struct ieee80211com *ic = ni->ni_ic; 2746 uint32_t plcp = 0; 2747 int ridx; 2748 2749 /* 2750 * If it's an MCS rate, let's set the plcp correctly 2751 * and set the relevant flags based on the node config. 2752 */ 2753 if (rate & IEEE80211_RATE_MCS) { 2754 /* 2755 * Set the initial PLCP value to be between 0->31 for 2756 * MCS 0 -> MCS 31, then set the "I'm an MCS rate!" 2757 * flag. 2758 */ 2759 plcp = IEEE80211_RV(rate) | IWN_RFLAG_MCS; 2760 2761 /* 2762 * XXX the following should only occur if both 2763 * the local configuration _and_ the remote node 2764 * advertise these capabilities. Thus this code 2765 * may need fixing! 2766 */ 2767 2768 /* 2769 * Set the channel width and guard interval. 2770 */ 2771 if (IEEE80211_IS_CHAN_HT40(ni->ni_chan)) { 2772 plcp |= IWN_RFLAG_HT40; 2773 if (ni->ni_htcap & IEEE80211_HTCAP_SHORTGI40) 2774 plcp |= IWN_RFLAG_SGI; 2775 } else if (ni->ni_htcap & IEEE80211_HTCAP_SHORTGI20) { 2776 plcp |= IWN_RFLAG_SGI; 2777 } 2778 2779 /* 2780 * Ensure the selected rate matches the link quality 2781 * table entries being used. 2782 */ 2783 if (rate > 0x8f) 2784 plcp |= IWN_RFLAG_ANT(sc->txchainmask); 2785 else if (rate > 0x87) 2786 plcp |= IWN_RFLAG_ANT(iwn_get_2stream_tx_antmask(sc)); 2787 else 2788 plcp |= IWN_RFLAG_ANT(iwn_get_1stream_tx_antmask(sc)); 2789 } else { 2790 /* 2791 * Set the initial PLCP - fine for both 2792 * OFDM and CCK rates. 2793 */ 2794 plcp = rate2plcp(rate); 2795 2796 /* Set CCK flag if it's CCK */ 2797 2798 /* XXX It would be nice to have a method 2799 * to map the ridx -> phy table entry 2800 * so we could just query that, rather than 2801 * this hack to check against IWN_RIDX_OFDM6. 2802 */ 2803 ridx = ieee80211_legacy_rate_lookup(ic->ic_rt, 2804 rate & IEEE80211_RATE_VAL); 2805 if (ridx < IWN_RIDX_OFDM6 && 2806 IEEE80211_IS_CHAN_2GHZ(ni->ni_chan)) 2807 plcp |= IWN_RFLAG_CCK; 2808 2809 /* Set antenna configuration */ 2810 /* XXX TODO: is this the right antenna to use for legacy? */ 2811 plcp |= IWN_RFLAG_ANT(iwn_get_1stream_tx_antmask(sc)); 2812 } 2813 2814 DPRINTF(sc, IWN_DEBUG_TXRATE, "%s: rate=0x%02x, plcp=0x%08x\n", 2815 __func__, 2816 rate, 2817 plcp); 2818 2819 return (htole32(plcp)); 2820 } 2821 2822 static void 2823 iwn_newassoc(struct ieee80211_node *ni, int isnew) 2824 { 2825 /* Doesn't do anything at the moment */ 2826 } 2827 2828 static int 2829 iwn_media_change(struct ifnet *ifp) 2830 { 2831 int error; 2832 2833 error = ieee80211_media_change(ifp); 2834 /* NB: only the fixed rate can change and that doesn't need a reset */ 2835 return (error == ENETRESET ? 0 : error); 2836 } 2837 2838 static int 2839 iwn_newstate(struct ieee80211vap *vap, enum ieee80211_state nstate, int arg) 2840 { 2841 struct iwn_vap *ivp = IWN_VAP(vap); 2842 struct ieee80211com *ic = vap->iv_ic; 2843 struct iwn_softc *sc = ic->ic_softc; 2844 int error = 0; 2845 2846 DPRINTF(sc, IWN_DEBUG_TRACE, "->%s begin\n", __func__); 2847 2848 DPRINTF(sc, IWN_DEBUG_STATE, "%s: %s -> %s\n", __func__, 2849 ieee80211_state_name[vap->iv_state], ieee80211_state_name[nstate]); 2850 2851 IEEE80211_UNLOCK(ic); 2852 IWN_LOCK(sc); 2853 callout_stop(&sc->calib_to); 2854 2855 sc->rxon = &sc->rx_on[IWN_RXON_BSS_CTX]; 2856 2857 switch (nstate) { 2858 case IEEE80211_S_ASSOC: 2859 if (vap->iv_state != IEEE80211_S_RUN) 2860 break; 2861 /* FALLTHROUGH */ 2862 case IEEE80211_S_AUTH: 2863 if (vap->iv_state == IEEE80211_S_AUTH) 2864 break; 2865 2866 /* 2867 * !AUTH -> AUTH transition requires state reset to handle 2868 * reassociations correctly. 2869 */ 2870 sc->rxon->associd = 0; 2871 sc->rxon->filter &= ~htole32(IWN_FILTER_BSS); 2872 sc->calib.state = IWN_CALIB_STATE_INIT; 2873 2874 /* Wait until we hear a beacon before we transmit */ 2875 if (IEEE80211_IS_CHAN_PASSIVE(ic->ic_curchan)) 2876 sc->sc_beacon_wait = 1; 2877 2878 if ((error = iwn_auth(sc, vap)) != 0) { 2879 device_printf(sc->sc_dev, 2880 "%s: could not move to auth state\n", __func__); 2881 } 2882 break; 2883 2884 case IEEE80211_S_RUN: 2885 /* 2886 * RUN -> RUN transition; Just restart the timers. 2887 */ 2888 if (vap->iv_state == IEEE80211_S_RUN) { 2889 sc->calib_cnt = 0; 2890 break; 2891 } 2892 2893 /* Wait until we hear a beacon before we transmit */ 2894 if (IEEE80211_IS_CHAN_PASSIVE(ic->ic_curchan)) 2895 sc->sc_beacon_wait = 1; 2896 2897 /* 2898 * !RUN -> RUN requires setting the association id 2899 * which is done with a firmware cmd. We also defer 2900 * starting the timers until that work is done. 2901 */ 2902 if ((error = iwn_run(sc, vap)) != 0) { 2903 device_printf(sc->sc_dev, 2904 "%s: could not move to run state\n", __func__); 2905 } 2906 break; 2907 2908 case IEEE80211_S_INIT: 2909 sc->calib.state = IWN_CALIB_STATE_INIT; 2910 /* 2911 * Purge the xmit queue so we don't have old frames 2912 * during a new association attempt. 2913 */ 2914 sc->sc_beacon_wait = 0; 2915 iwn_xmit_queue_drain(sc); 2916 break; 2917 2918 default: 2919 break; 2920 } 2921 IWN_UNLOCK(sc); 2922 IEEE80211_LOCK(ic); 2923 if (error != 0){ 2924 DPRINTF(sc, IWN_DEBUG_TRACE, "->%s end in error\n", __func__); 2925 return error; 2926 } 2927 2928 DPRINTF(sc, IWN_DEBUG_TRACE, "->%s: end\n",__func__); 2929 2930 return ivp->iv_newstate(vap, nstate, arg); 2931 } 2932 2933 static void 2934 iwn_calib_timeout(void *arg) 2935 { 2936 struct iwn_softc *sc = arg; 2937 2938 IWN_LOCK_ASSERT(sc); 2939 2940 /* Force automatic TX power calibration every 60 secs. */ 2941 if (++sc->calib_cnt >= 120) { 2942 uint32_t flags = 0; 2943 2944 DPRINTF(sc, IWN_DEBUG_CALIBRATE, "%s\n", 2945 "sending request for statistics"); 2946 (void)iwn_cmd(sc, IWN_CMD_GET_STATISTICS, &flags, 2947 sizeof flags, 1); 2948 sc->calib_cnt = 0; 2949 } 2950 callout_reset(&sc->calib_to, msecs_to_ticks(500), iwn_calib_timeout, 2951 sc); 2952 } 2953 2954 /* 2955 * Process an RX_PHY firmware notification. This is usually immediately 2956 * followed by an MPDU_RX_DONE notification. 2957 */ 2958 static void 2959 iwn_rx_phy(struct iwn_softc *sc, struct iwn_rx_desc *desc, 2960 struct iwn_rx_data *data) 2961 { 2962 struct iwn_rx_stat *stat = (struct iwn_rx_stat *)(desc + 1); 2963 2964 DPRINTF(sc, IWN_DEBUG_CALIBRATE, "%s: received PHY stats\n", __func__); 2965 bus_dmamap_sync(sc->rxq.data_dmat, data->map, BUS_DMASYNC_POSTREAD); 2966 2967 /* Save RX statistics, they will be used on MPDU_RX_DONE. */ 2968 memcpy(&sc->last_rx_stat, stat, sizeof (*stat)); 2969 sc->last_rx_valid = 1; 2970 } 2971 2972 /* 2973 * Process an RX_DONE (4965AGN only) or MPDU_RX_DONE firmware notification. 2974 * Each MPDU_RX_DONE notification must be preceded by an RX_PHY one. 2975 */ 2976 static void 2977 iwn_rx_done(struct iwn_softc *sc, struct iwn_rx_desc *desc, 2978 struct iwn_rx_data *data) 2979 { 2980 struct iwn_ops *ops = &sc->ops; 2981 struct ieee80211com *ic = &sc->sc_ic; 2982 struct iwn_rx_ring *ring = &sc->rxq; 2983 struct ieee80211_frame *wh; 2984 struct ieee80211_node *ni; 2985 struct mbuf *m, *m1; 2986 struct iwn_rx_stat *stat; 2987 caddr_t head; 2988 bus_addr_t paddr; 2989 uint32_t flags; 2990 int error, len, rssi, nf; 2991 2992 DPRINTF(sc, IWN_DEBUG_TRACE, "->%s begin\n", __func__); 2993 2994 if (desc->type == IWN_MPDU_RX_DONE) { 2995 /* Check for prior RX_PHY notification. */ 2996 if (!sc->last_rx_valid) { 2997 DPRINTF(sc, IWN_DEBUG_ANY, 2998 "%s: missing RX_PHY\n", __func__); 2999 return; 3000 } 3001 stat = &sc->last_rx_stat; 3002 } else 3003 stat = (struct iwn_rx_stat *)(desc + 1); 3004 3005 bus_dmamap_sync(ring->data_dmat, data->map, BUS_DMASYNC_POSTREAD); 3006 3007 if (stat->cfg_phy_len > IWN_STAT_MAXLEN) { 3008 device_printf(sc->sc_dev, 3009 "%s: invalid RX statistic header, len %d\n", __func__, 3010 stat->cfg_phy_len); 3011 return; 3012 } 3013 if (desc->type == IWN_MPDU_RX_DONE) { 3014 struct iwn_rx_mpdu *mpdu = (struct iwn_rx_mpdu *)(desc + 1); 3015 head = (caddr_t)(mpdu + 1); 3016 len = le16toh(mpdu->len); 3017 } else { 3018 head = (caddr_t)(stat + 1) + stat->cfg_phy_len; 3019 len = le16toh(stat->len); 3020 } 3021 3022 flags = le32toh(*(uint32_t *)(head + len)); 3023 3024 /* Discard frames with a bad FCS early. */ 3025 if ((flags & IWN_RX_NOERROR) != IWN_RX_NOERROR) { 3026 DPRINTF(sc, IWN_DEBUG_RECV, "%s: RX flags error %x\n", 3027 __func__, flags); 3028 counter_u64_add(ic->ic_ierrors, 1); 3029 return; 3030 } 3031 /* Discard frames that are too short. */ 3032 if (len < sizeof (struct ieee80211_frame_ack)) { 3033 DPRINTF(sc, IWN_DEBUG_RECV, "%s: frame too short: %d\n", 3034 __func__, len); 3035 counter_u64_add(ic->ic_ierrors, 1); 3036 return; 3037 } 3038 3039 m1 = m_getjcl(M_NOWAIT, MT_DATA, M_PKTHDR, IWN_RBUF_SIZE); 3040 if (m1 == NULL) { 3041 DPRINTF(sc, IWN_DEBUG_ANY, "%s: no mbuf to restock ring\n", 3042 __func__); 3043 counter_u64_add(ic->ic_ierrors, 1); 3044 return; 3045 } 3046 bus_dmamap_unload(ring->data_dmat, data->map); 3047 3048 error = bus_dmamap_load(ring->data_dmat, data->map, mtod(m1, void *), 3049 IWN_RBUF_SIZE, iwn_dma_map_addr, &paddr, BUS_DMA_NOWAIT); 3050 if (error != 0 && error != EFBIG) { 3051 device_printf(sc->sc_dev, 3052 "%s: bus_dmamap_load failed, error %d\n", __func__, error); 3053 m_freem(m1); 3054 3055 /* Try to reload the old mbuf. */ 3056 error = bus_dmamap_load(ring->data_dmat, data->map, 3057 mtod(data->m, void *), IWN_RBUF_SIZE, iwn_dma_map_addr, 3058 &paddr, BUS_DMA_NOWAIT); 3059 if (error != 0 && error != EFBIG) { 3060 panic("%s: could not load old RX mbuf", __func__); 3061 } 3062 bus_dmamap_sync(ring->data_dmat, data->map, 3063 BUS_DMASYNC_PREREAD); 3064 /* Physical address may have changed. */ 3065 ring->desc[ring->cur] = htole32(paddr >> 8); 3066 bus_dmamap_sync(ring->desc_dma.tag, ring->desc_dma.map, 3067 BUS_DMASYNC_PREWRITE); 3068 counter_u64_add(ic->ic_ierrors, 1); 3069 return; 3070 } 3071 3072 bus_dmamap_sync(ring->data_dmat, data->map, 3073 BUS_DMASYNC_PREREAD); 3074 3075 m = data->m; 3076 data->m = m1; 3077 /* Update RX descriptor. */ 3078 ring->desc[ring->cur] = htole32(paddr >> 8); 3079 bus_dmamap_sync(ring->desc_dma.tag, ring->desc_dma.map, 3080 BUS_DMASYNC_PREWRITE); 3081 3082 /* Finalize mbuf. */ 3083 m->m_data = head; 3084 m->m_pkthdr.len = m->m_len = len; 3085 3086 /* Grab a reference to the source node. */ 3087 wh = mtod(m, struct ieee80211_frame *); 3088 if (len >= sizeof(struct ieee80211_frame_min)) 3089 ni = ieee80211_find_rxnode(ic, (struct ieee80211_frame_min *)wh); 3090 else 3091 ni = NULL; 3092 nf = (ni != NULL && ni->ni_vap->iv_state == IEEE80211_S_RUN && 3093 (ic->ic_flags & IEEE80211_F_SCAN) == 0) ? sc->noise : -95; 3094 3095 rssi = ops->get_rssi(sc, stat); 3096 3097 if (ieee80211_radiotap_active(ic)) { 3098 struct iwn_rx_radiotap_header *tap = &sc->sc_rxtap; 3099 uint32_t rate = le32toh(stat->rate); 3100 3101 tap->wr_flags = 0; 3102 if (stat->flags & htole16(IWN_STAT_FLAG_SHPREAMBLE)) 3103 tap->wr_flags |= IEEE80211_RADIOTAP_F_SHORTPRE; 3104 tap->wr_dbm_antsignal = (int8_t)rssi; 3105 tap->wr_dbm_antnoise = (int8_t)nf; 3106 tap->wr_tsft = stat->tstamp; 3107 if (rate & IWN_RFLAG_MCS) { 3108 tap->wr_rate = rate & IWN_RFLAG_RATE_MCS; 3109 tap->wr_rate |= IEEE80211_RATE_MCS; 3110 } else 3111 tap->wr_rate = plcp2rate(rate & IWN_RFLAG_RATE); 3112 } 3113 3114 /* 3115 * If it's a beacon and we're waiting, then do the 3116 * wakeup. This should unblock raw_xmit/start. 3117 */ 3118 if (sc->sc_beacon_wait) { 3119 uint8_t type, subtype; 3120 /* NB: Re-assign wh */ 3121 wh = mtod(m, struct ieee80211_frame *); 3122 type = wh->i_fc[0] & IEEE80211_FC0_TYPE_MASK; 3123 subtype = wh->i_fc[0] & IEEE80211_FC0_SUBTYPE_MASK; 3124 /* 3125 * This assumes at this point we've received our own 3126 * beacon. 3127 */ 3128 DPRINTF(sc, IWN_DEBUG_TRACE, 3129 "%s: beacon_wait, type=%d, subtype=%d\n", 3130 __func__, type, subtype); 3131 if (type == IEEE80211_FC0_TYPE_MGT && 3132 subtype == IEEE80211_FC0_SUBTYPE_BEACON) { 3133 DPRINTF(sc, IWN_DEBUG_TRACE | IWN_DEBUG_XMIT, 3134 "%s: waking things up\n", __func__); 3135 /* queue taskqueue to transmit! */ 3136 taskqueue_enqueue(sc->sc_tq, &sc->sc_xmit_task); 3137 } 3138 } 3139 3140 IWN_UNLOCK(sc); 3141 3142 /* Send the frame to the 802.11 layer. */ 3143 if (ni != NULL) { 3144 if (ni->ni_flags & IEEE80211_NODE_HT) 3145 m->m_flags |= M_AMPDU; 3146 (void)ieee80211_input(ni, m, rssi - nf, nf); 3147 /* Node is no longer needed. */ 3148 ieee80211_free_node(ni); 3149 } else 3150 (void)ieee80211_input_all(ic, m, rssi - nf, nf); 3151 3152 IWN_LOCK(sc); 3153 3154 DPRINTF(sc, IWN_DEBUG_TRACE, "->%s: end\n",__func__); 3155 3156 } 3157 3158 /* Process an incoming Compressed BlockAck. */ 3159 static void 3160 iwn_rx_compressed_ba(struct iwn_softc *sc, struct iwn_rx_desc *desc, 3161 struct iwn_rx_data *data) 3162 { 3163 struct ieee80211_ratectl_tx_status *txs = &sc->sc_txs; 3164 struct iwn_ops *ops = &sc->ops; 3165 struct iwn_node *wn; 3166 struct ieee80211_node *ni; 3167 struct iwn_compressed_ba *ba = (struct iwn_compressed_ba *)(desc + 1); 3168 struct iwn_tx_ring *txq; 3169 struct iwn_tx_data *txdata; 3170 struct ieee80211_tx_ampdu *tap; 3171 struct mbuf *m; 3172 uint64_t bitmap; 3173 uint16_t ssn; 3174 uint8_t tid; 3175 int i, lastidx, qid, *res, shift; 3176 int tx_ok = 0, tx_err = 0; 3177 3178 DPRINTF(sc, IWN_DEBUG_TRACE | IWN_DEBUG_XMIT, "->%s begin\n", __func__); 3179 3180 bus_dmamap_sync(sc->rxq.data_dmat, data->map, BUS_DMASYNC_POSTREAD); 3181 3182 qid = le16toh(ba->qid); 3183 txq = &sc->txq[ba->qid]; 3184 tap = sc->qid2tap[ba->qid]; 3185 tid = tap->txa_tid; 3186 wn = (void *)tap->txa_ni; 3187 3188 res = NULL; 3189 ssn = 0; 3190 if (!IEEE80211_AMPDU_RUNNING(tap)) { 3191 res = tap->txa_private; 3192 ssn = tap->txa_start & 0xfff; 3193 } 3194 3195 for (lastidx = le16toh(ba->ssn) & 0xff; txq->read != lastidx;) { 3196 txdata = &txq->data[txq->read]; 3197 3198 /* Unmap and free mbuf. */ 3199 bus_dmamap_sync(txq->data_dmat, txdata->map, 3200 BUS_DMASYNC_POSTWRITE); 3201 bus_dmamap_unload(txq->data_dmat, txdata->map); 3202 m = txdata->m, txdata->m = NULL; 3203 ni = txdata->ni, txdata->ni = NULL; 3204 3205 KASSERT(ni != NULL, ("no node")); 3206 KASSERT(m != NULL, ("no mbuf")); 3207 3208 DPRINTF(sc, IWN_DEBUG_XMIT, "%s: freeing m=%p\n", __func__, m); 3209 ieee80211_tx_complete(ni, m, 1); 3210 3211 txq->queued--; 3212 txq->read = (txq->read + 1) % IWN_TX_RING_COUNT; 3213 } 3214 3215 if (txq->queued == 0 && res != NULL) { 3216 iwn_nic_lock(sc); 3217 ops->ampdu_tx_stop(sc, qid, tid, ssn); 3218 iwn_nic_unlock(sc); 3219 sc->qid2tap[qid] = NULL; 3220 free(res, M_DEVBUF); 3221 return; 3222 } 3223 3224 if (wn->agg[tid].bitmap == 0) 3225 return; 3226 3227 shift = wn->agg[tid].startidx - ((le16toh(ba->seq) >> 4) & 0xff); 3228 if (shift < 0) 3229 shift += 0x100; 3230 3231 if (wn->agg[tid].nframes > (64 - shift)) 3232 return; 3233 3234 /* 3235 * Walk the bitmap and calculate how many successful and failed 3236 * attempts are made. 3237 * 3238 * Yes, the rate control code doesn't know these are A-MPDU 3239 * subframes and that it's okay to fail some of these. 3240 */ 3241 ni = tap->txa_ni; 3242 bitmap = (le64toh(ba->bitmap) >> shift) & wn->agg[tid].bitmap; 3243 for (i = 0; bitmap; i++) { 3244 txs->flags = 0; /* XXX TODO */ 3245 if ((bitmap & 1) == 0) { 3246 tx_err ++; 3247 txs->status = IEEE80211_RATECTL_TX_FAIL_UNSPECIFIED; 3248 } else { 3249 tx_ok ++; 3250 txs->status = IEEE80211_RATECTL_TX_SUCCESS; 3251 } 3252 ieee80211_ratectl_tx_complete(ni, txs); 3253 bitmap >>= 1; 3254 } 3255 3256 DPRINTF(sc, IWN_DEBUG_TRACE | IWN_DEBUG_XMIT, 3257 "->%s: end; %d ok; %d err\n",__func__, tx_ok, tx_err); 3258 3259 } 3260 3261 /* 3262 * Process a CALIBRATION_RESULT notification sent by the initialization 3263 * firmware on response to a CMD_CALIB_CONFIG command (5000 only). 3264 */ 3265 static void 3266 iwn5000_rx_calib_results(struct iwn_softc *sc, struct iwn_rx_desc *desc, 3267 struct iwn_rx_data *data) 3268 { 3269 struct iwn_phy_calib *calib = (struct iwn_phy_calib *)(desc + 1); 3270 int len, idx = -1; 3271 3272 DPRINTF(sc, IWN_DEBUG_TRACE, "->%s begin\n", __func__); 3273 3274 /* Runtime firmware should not send such a notification. */ 3275 if (sc->sc_flags & IWN_FLAG_CALIB_DONE){ 3276 DPRINTF(sc, IWN_DEBUG_TRACE, "->%s received after clib done\n", 3277 __func__); 3278 return; 3279 } 3280 len = (le32toh(desc->len) & 0x3fff) - 4; 3281 bus_dmamap_sync(sc->rxq.data_dmat, data->map, BUS_DMASYNC_POSTREAD); 3282 3283 switch (calib->code) { 3284 case IWN5000_PHY_CALIB_DC: 3285 if (sc->base_params->calib_need & IWN_FLG_NEED_PHY_CALIB_DC) 3286 idx = 0; 3287 break; 3288 case IWN5000_PHY_CALIB_LO: 3289 if (sc->base_params->calib_need & IWN_FLG_NEED_PHY_CALIB_LO) 3290 idx = 1; 3291 break; 3292 case IWN5000_PHY_CALIB_TX_IQ: 3293 if (sc->base_params->calib_need & IWN_FLG_NEED_PHY_CALIB_TX_IQ) 3294 idx = 2; 3295 break; 3296 case IWN5000_PHY_CALIB_TX_IQ_PERIODIC: 3297 if (sc->base_params->calib_need & IWN_FLG_NEED_PHY_CALIB_TX_IQ_PERIODIC) 3298 idx = 3; 3299 break; 3300 case IWN5000_PHY_CALIB_BASE_BAND: 3301 if (sc->base_params->calib_need & IWN_FLG_NEED_PHY_CALIB_BASE_BAND) 3302 idx = 4; 3303 break; 3304 } 3305 if (idx == -1) /* Ignore other results. */ 3306 return; 3307 3308 /* Save calibration result. */ 3309 if (sc->calibcmd[idx].buf != NULL) 3310 free(sc->calibcmd[idx].buf, M_DEVBUF); 3311 sc->calibcmd[idx].buf = malloc(len, M_DEVBUF, M_NOWAIT); 3312 if (sc->calibcmd[idx].buf == NULL) { 3313 DPRINTF(sc, IWN_DEBUG_CALIBRATE, 3314 "not enough memory for calibration result %d\n", 3315 calib->code); 3316 return; 3317 } 3318 DPRINTF(sc, IWN_DEBUG_CALIBRATE, 3319 "saving calibration result idx=%d, code=%d len=%d\n", idx, calib->code, len); 3320 sc->calibcmd[idx].len = len; 3321 memcpy(sc->calibcmd[idx].buf, calib, len); 3322 } 3323 3324 static void 3325 iwn_stats_update(struct iwn_softc *sc, struct iwn_calib_state *calib, 3326 struct iwn_stats *stats, int len) 3327 { 3328 struct iwn_stats_bt *stats_bt; 3329 struct iwn_stats *lstats; 3330 3331 /* 3332 * First - check whether the length is the bluetooth or normal. 3333 * 3334 * If it's normal - just copy it and bump out. 3335 * Otherwise we have to convert things. 3336 */ 3337 3338 if (len == sizeof(struct iwn_stats) + 4) { 3339 memcpy(&sc->last_stat, stats, sizeof(struct iwn_stats)); 3340 sc->last_stat_valid = 1; 3341 return; 3342 } 3343 3344 /* 3345 * If it's not the bluetooth size - log, then just copy. 3346 */ 3347 if (len != sizeof(struct iwn_stats_bt) + 4) { 3348 DPRINTF(sc, IWN_DEBUG_STATS, 3349 "%s: size of rx statistics (%d) not an expected size!\n", 3350 __func__, 3351 len); 3352 memcpy(&sc->last_stat, stats, sizeof(struct iwn_stats)); 3353 sc->last_stat_valid = 1; 3354 return; 3355 } 3356 3357 /* 3358 * Ok. Time to copy. 3359 */ 3360 stats_bt = (struct iwn_stats_bt *) stats; 3361 lstats = &sc->last_stat; 3362 3363 /* flags */ 3364 lstats->flags = stats_bt->flags; 3365 /* rx_bt */ 3366 memcpy(&lstats->rx.ofdm, &stats_bt->rx_bt.ofdm, 3367 sizeof(struct iwn_rx_phy_stats)); 3368 memcpy(&lstats->rx.cck, &stats_bt->rx_bt.cck, 3369 sizeof(struct iwn_rx_phy_stats)); 3370 memcpy(&lstats->rx.general, &stats_bt->rx_bt.general_bt.common, 3371 sizeof(struct iwn_rx_general_stats)); 3372 memcpy(&lstats->rx.ht, &stats_bt->rx_bt.ht, 3373 sizeof(struct iwn_rx_ht_phy_stats)); 3374 /* tx */ 3375 memcpy(&lstats->tx, &stats_bt->tx, 3376 sizeof(struct iwn_tx_stats)); 3377 /* general */ 3378 memcpy(&lstats->general, &stats_bt->general, 3379 sizeof(struct iwn_general_stats)); 3380 3381 /* XXX TODO: Squirrel away the extra bluetooth stats somewhere */ 3382 sc->last_stat_valid = 1; 3383 } 3384 3385 /* 3386 * Process an RX_STATISTICS or BEACON_STATISTICS firmware notification. 3387 * The latter is sent by the firmware after each received beacon. 3388 */ 3389 static void 3390 iwn_rx_statistics(struct iwn_softc *sc, struct iwn_rx_desc *desc, 3391 struct iwn_rx_data *data) 3392 { 3393 struct iwn_ops *ops = &sc->ops; 3394 struct ieee80211com *ic = &sc->sc_ic; 3395 struct ieee80211vap *vap = TAILQ_FIRST(&ic->ic_vaps); 3396 struct iwn_calib_state *calib = &sc->calib; 3397 struct iwn_stats *stats = (struct iwn_stats *)(desc + 1); 3398 struct iwn_stats *lstats; 3399 int temp; 3400 3401 DPRINTF(sc, IWN_DEBUG_TRACE, "->%s begin\n", __func__); 3402 3403 /* Ignore statistics received during a scan. */ 3404 if (vap->iv_state != IEEE80211_S_RUN || 3405 (ic->ic_flags & IEEE80211_F_SCAN)){ 3406 DPRINTF(sc, IWN_DEBUG_TRACE, "->%s received during calib\n", 3407 __func__); 3408 return; 3409 } 3410 3411 bus_dmamap_sync(sc->rxq.data_dmat, data->map, BUS_DMASYNC_POSTREAD); 3412 3413 DPRINTF(sc, IWN_DEBUG_CALIBRATE | IWN_DEBUG_STATS, 3414 "%s: received statistics, cmd %d, len %d\n", 3415 __func__, desc->type, le16toh(desc->len)); 3416 sc->calib_cnt = 0; /* Reset TX power calibration timeout. */ 3417 3418 /* 3419 * Collect/track general statistics for reporting. 3420 * 3421 * This takes care of ensuring that the bluetooth sized message 3422 * will be correctly converted to the legacy sized message. 3423 */ 3424 iwn_stats_update(sc, calib, stats, le16toh(desc->len)); 3425 3426 /* 3427 * And now, let's take a reference of it to use! 3428 */ 3429 lstats = &sc->last_stat; 3430 3431 /* Test if temperature has changed. */ 3432 if (lstats->general.temp != sc->rawtemp) { 3433 /* Convert "raw" temperature to degC. */ 3434 sc->rawtemp = stats->general.temp; 3435 temp = ops->get_temperature(sc); 3436 DPRINTF(sc, IWN_DEBUG_CALIBRATE, "%s: temperature %d\n", 3437 __func__, temp); 3438 3439 /* Update TX power if need be (4965AGN only). */ 3440 if (sc->hw_type == IWN_HW_REV_TYPE_4965) 3441 iwn4965_power_calibration(sc, temp); 3442 } 3443 3444 if (desc->type != IWN_BEACON_STATISTICS) 3445 return; /* Reply to a statistics request. */ 3446 3447 sc->noise = iwn_get_noise(&lstats->rx.general); 3448 DPRINTF(sc, IWN_DEBUG_CALIBRATE, "%s: noise %d\n", __func__, sc->noise); 3449 3450 /* Test that RSSI and noise are present in stats report. */ 3451 if (le32toh(lstats->rx.general.flags) != 1) { 3452 DPRINTF(sc, IWN_DEBUG_ANY, "%s\n", 3453 "received statistics without RSSI"); 3454 return; 3455 } 3456 3457 if (calib->state == IWN_CALIB_STATE_ASSOC) 3458 iwn_collect_noise(sc, &lstats->rx.general); 3459 else if (calib->state == IWN_CALIB_STATE_RUN) { 3460 iwn_tune_sensitivity(sc, &lstats->rx); 3461 /* 3462 * XXX TODO: Only run the RX recovery if we're associated! 3463 */ 3464 iwn_check_rx_recovery(sc, lstats); 3465 iwn_save_stats_counters(sc, lstats); 3466 } 3467 3468 DPRINTF(sc, IWN_DEBUG_TRACE, "->%s: end\n",__func__); 3469 } 3470 3471 /* 3472 * Save the relevant statistic counters for the next calibration 3473 * pass. 3474 */ 3475 static void 3476 iwn_save_stats_counters(struct iwn_softc *sc, const struct iwn_stats *rs) 3477 { 3478 struct iwn_calib_state *calib = &sc->calib; 3479 3480 /* Save counters values for next call. */ 3481 calib->bad_plcp_cck = le32toh(rs->rx.cck.bad_plcp); 3482 calib->fa_cck = le32toh(rs->rx.cck.fa); 3483 calib->bad_plcp_ht = le32toh(rs->rx.ht.bad_plcp); 3484 calib->bad_plcp_ofdm = le32toh(rs->rx.ofdm.bad_plcp); 3485 calib->fa_ofdm = le32toh(rs->rx.ofdm.fa); 3486 3487 /* Last time we received these tick values */ 3488 sc->last_calib_ticks = ticks; 3489 } 3490 3491 /* 3492 * Process a TX_DONE firmware notification. Unfortunately, the 4965AGN 3493 * and 5000 adapters have different incompatible TX status formats. 3494 */ 3495 static void 3496 iwn4965_tx_done(struct iwn_softc *sc, struct iwn_rx_desc *desc, 3497 struct iwn_rx_data *data) 3498 { 3499 struct iwn4965_tx_stat *stat = (struct iwn4965_tx_stat *)(desc + 1); 3500 struct iwn_tx_ring *ring; 3501 int qid; 3502 3503 qid = desc->qid & 0xf; 3504 ring = &sc->txq[qid]; 3505 3506 DPRINTF(sc, IWN_DEBUG_XMIT, "%s: " 3507 "qid %d idx %d RTS retries %d ACK retries %d nkill %d rate %x duration %d status %x\n", 3508 __func__, desc->qid, desc->idx, 3509 stat->rtsfailcnt, 3510 stat->ackfailcnt, 3511 stat->btkillcnt, 3512 stat->rate, le16toh(stat->duration), 3513 le32toh(stat->status)); 3514 3515 bus_dmamap_sync(ring->data_dmat, data->map, BUS_DMASYNC_POSTREAD); 3516 if (qid >= sc->firstaggqueue) { 3517 iwn_ampdu_tx_done(sc, qid, desc->idx, stat->nframes, 3518 stat->rtsfailcnt, stat->ackfailcnt, &stat->status); 3519 } else { 3520 iwn_tx_done(sc, desc, stat->rtsfailcnt, stat->ackfailcnt, 3521 le32toh(stat->status) & 0xff); 3522 } 3523 } 3524 3525 static void 3526 iwn5000_tx_done(struct iwn_softc *sc, struct iwn_rx_desc *desc, 3527 struct iwn_rx_data *data) 3528 { 3529 struct iwn5000_tx_stat *stat = (struct iwn5000_tx_stat *)(desc + 1); 3530 struct iwn_tx_ring *ring; 3531 int qid; 3532 3533 qid = desc->qid & 0xf; 3534 ring = &sc->txq[qid]; 3535 3536 DPRINTF(sc, IWN_DEBUG_XMIT, "%s: " 3537 "qid %d idx %d RTS retries %d ACK retries %d nkill %d rate %x duration %d status %x\n", 3538 __func__, desc->qid, desc->idx, 3539 stat->rtsfailcnt, 3540 stat->ackfailcnt, 3541 stat->btkillcnt, 3542 stat->rate, le16toh(stat->duration), 3543 le32toh(stat->status)); 3544 3545 #ifdef notyet 3546 /* Reset TX scheduler slot. */ 3547 iwn5000_reset_sched(sc, desc->qid & 0xf, desc->idx); 3548 #endif 3549 3550 bus_dmamap_sync(ring->data_dmat, data->map, BUS_DMASYNC_POSTREAD); 3551 if (qid >= sc->firstaggqueue) { 3552 iwn_ampdu_tx_done(sc, qid, desc->idx, stat->nframes, 3553 stat->rtsfailcnt, stat->ackfailcnt, &stat->status); 3554 } else { 3555 iwn_tx_done(sc, desc, stat->rtsfailcnt, stat->ackfailcnt, 3556 le16toh(stat->status) & 0xff); 3557 } 3558 } 3559 3560 /* 3561 * Adapter-independent backend for TX_DONE firmware notifications. 3562 */ 3563 static void 3564 iwn_tx_done(struct iwn_softc *sc, struct iwn_rx_desc *desc, int rtsfailcnt, 3565 int ackfailcnt, uint8_t status) 3566 { 3567 struct ieee80211_ratectl_tx_status *txs = &sc->sc_txs; 3568 struct iwn_tx_ring *ring = &sc->txq[desc->qid & 0xf]; 3569 struct iwn_tx_data *data = &ring->data[desc->idx]; 3570 struct mbuf *m; 3571 struct ieee80211_node *ni; 3572 3573 KASSERT(data->ni != NULL, ("no node")); 3574 3575 DPRINTF(sc, IWN_DEBUG_TRACE, "->%s begin\n", __func__); 3576 3577 /* Unmap and free mbuf. */ 3578 bus_dmamap_sync(ring->data_dmat, data->map, BUS_DMASYNC_POSTWRITE); 3579 bus_dmamap_unload(ring->data_dmat, data->map); 3580 m = data->m, data->m = NULL; 3581 ni = data->ni, data->ni = NULL; 3582 3583 /* 3584 * Update rate control statistics for the node. 3585 */ 3586 txs->flags = IEEE80211_RATECTL_STATUS_SHORT_RETRY | 3587 IEEE80211_RATECTL_STATUS_LONG_RETRY; 3588 txs->short_retries = rtsfailcnt; 3589 txs->long_retries = ackfailcnt; 3590 if (!(status & IWN_TX_FAIL)) 3591 txs->status = IEEE80211_RATECTL_TX_SUCCESS; 3592 else { 3593 switch (status) { 3594 case IWN_TX_FAIL_SHORT_LIMIT: 3595 txs->status = IEEE80211_RATECTL_TX_FAIL_SHORT; 3596 break; 3597 case IWN_TX_FAIL_LONG_LIMIT: 3598 txs->status = IEEE80211_RATECTL_TX_FAIL_LONG; 3599 break; 3600 case IWN_TX_STATUS_FAIL_LIFE_EXPIRE: 3601 txs->status = IEEE80211_RATECTL_TX_FAIL_EXPIRED; 3602 break; 3603 default: 3604 txs->status = IEEE80211_RATECTL_TX_FAIL_UNSPECIFIED; 3605 break; 3606 } 3607 } 3608 ieee80211_ratectl_tx_complete(ni, txs); 3609 3610 /* 3611 * Channels marked for "radar" require traffic to be received 3612 * to unlock before we can transmit. Until traffic is seen 3613 * any attempt to transmit is returned immediately with status 3614 * set to IWN_TX_FAIL_TX_LOCKED. Unfortunately this can easily 3615 * happen on first authenticate after scanning. To workaround 3616 * this we ignore a failure of this sort in AUTH state so the 3617 * 802.11 layer will fall back to using a timeout to wait for 3618 * the AUTH reply. This allows the firmware time to see 3619 * traffic so a subsequent retry of AUTH succeeds. It's 3620 * unclear why the firmware does not maintain state for 3621 * channels recently visited as this would allow immediate 3622 * use of the channel after a scan (where we see traffic). 3623 */ 3624 if (status == IWN_TX_FAIL_TX_LOCKED && 3625 ni->ni_vap->iv_state == IEEE80211_S_AUTH) 3626 ieee80211_tx_complete(ni, m, 0); 3627 else 3628 ieee80211_tx_complete(ni, m, 3629 (status & IWN_TX_FAIL) != 0); 3630 3631 sc->sc_tx_timer = 0; 3632 if (--ring->queued < IWN_TX_RING_LOMARK) 3633 sc->qfullmsk &= ~(1 << ring->qid); 3634 3635 DPRINTF(sc, IWN_DEBUG_TRACE, "->%s: end\n",__func__); 3636 } 3637 3638 /* 3639 * Process a "command done" firmware notification. This is where we wakeup 3640 * processes waiting for a synchronous command completion. 3641 */ 3642 static void 3643 iwn_cmd_done(struct iwn_softc *sc, struct iwn_rx_desc *desc) 3644 { 3645 struct iwn_tx_ring *ring; 3646 struct iwn_tx_data *data; 3647 int cmd_queue_num; 3648 3649 if (sc->sc_flags & IWN_FLAG_PAN_SUPPORT) 3650 cmd_queue_num = IWN_PAN_CMD_QUEUE; 3651 else 3652 cmd_queue_num = IWN_CMD_QUEUE_NUM; 3653 3654 if ((desc->qid & IWN_RX_DESC_QID_MSK) != cmd_queue_num) 3655 return; /* Not a command ack. */ 3656 3657 ring = &sc->txq[cmd_queue_num]; 3658 data = &ring->data[desc->idx]; 3659 3660 /* If the command was mapped in an mbuf, free it. */ 3661 if (data->m != NULL) { 3662 bus_dmamap_sync(ring->data_dmat, data->map, 3663 BUS_DMASYNC_POSTWRITE); 3664 bus_dmamap_unload(ring->data_dmat, data->map); 3665 m_freem(data->m); 3666 data->m = NULL; 3667 } 3668 wakeup(&ring->desc[desc->idx]); 3669 } 3670 3671 static void 3672 iwn_ampdu_tx_done(struct iwn_softc *sc, int qid, int idx, int nframes, 3673 int rtsfailcnt, int ackfailcnt, void *stat) 3674 { 3675 struct iwn_ops *ops = &sc->ops; 3676 struct iwn_tx_ring *ring = &sc->txq[qid]; 3677 struct ieee80211_ratectl_tx_status *txs = &sc->sc_txs; 3678 struct iwn_tx_data *data; 3679 struct mbuf *m; 3680 struct iwn_node *wn; 3681 struct ieee80211_node *ni; 3682 struct ieee80211_tx_ampdu *tap; 3683 uint64_t bitmap; 3684 uint32_t *status = stat; 3685 uint16_t *aggstatus = stat; 3686 uint16_t ssn; 3687 uint8_t tid; 3688 int bit, i, lastidx, *res, seqno, shift, start; 3689 3690 /* XXX TODO: status is le16 field! Grr */ 3691 3692 DPRINTF(sc, IWN_DEBUG_TRACE, "->%s begin\n", __func__); 3693 DPRINTF(sc, IWN_DEBUG_XMIT, "%s: nframes=%d, status=0x%08x\n", 3694 __func__, 3695 nframes, 3696 *status); 3697 3698 tap = sc->qid2tap[qid]; 3699 tid = tap->txa_tid; 3700 wn = (void *)tap->txa_ni; 3701 ni = tap->txa_ni; 3702 3703 /* 3704 * XXX TODO: ACK and RTS failures would be nice here! 3705 */ 3706 3707 /* 3708 * A-MPDU single frame status - if we failed to transmit it 3709 * in A-MPDU, then it may be a permanent failure. 3710 * 3711 * XXX TODO: check what the Linux iwlwifi driver does here; 3712 * there's some permanent and temporary failures that may be 3713 * handled differently. 3714 */ 3715 if (nframes == 1) { 3716 txs->flags = IEEE80211_RATECTL_STATUS_SHORT_RETRY | 3717 IEEE80211_RATECTL_STATUS_LONG_RETRY; 3718 txs->short_retries = rtsfailcnt; 3719 txs->long_retries = ackfailcnt; 3720 if ((*status & 0xff) != 1 && (*status & 0xff) != 2) { 3721 #ifdef NOT_YET 3722 printf("ieee80211_send_bar()\n"); 3723 #endif 3724 /* 3725 * If we completely fail a transmit, make sure a 3726 * notification is pushed up to the rate control 3727 * layer. 3728 */ 3729 /* XXX */ 3730 txs->status = IEEE80211_RATECTL_TX_FAIL_UNSPECIFIED; 3731 } else { 3732 /* 3733 * If nframes=1, then we won't be getting a BA for 3734 * this frame. Ensure that we correctly update the 3735 * rate control code with how many retries were 3736 * needed to send it. 3737 */ 3738 txs->status = IEEE80211_RATECTL_TX_SUCCESS; 3739 } 3740 ieee80211_ratectl_tx_complete(ni, txs); 3741 } 3742 3743 bitmap = 0; 3744 start = idx; 3745 for (i = 0; i < nframes; i++) { 3746 if (le16toh(aggstatus[i * 2]) & 0xc) 3747 continue; 3748 3749 idx = le16toh(aggstatus[2*i + 1]) & 0xff; 3750 bit = idx - start; 3751 shift = 0; 3752 if (bit >= 64) { 3753 shift = 0x100 - idx + start; 3754 bit = 0; 3755 start = idx; 3756 } else if (bit <= -64) 3757 bit = 0x100 - start + idx; 3758 else if (bit < 0) { 3759 shift = start - idx; 3760 start = idx; 3761 bit = 0; 3762 } 3763 bitmap = bitmap << shift; 3764 bitmap |= 1ULL << bit; 3765 } 3766 tap = sc->qid2tap[qid]; 3767 tid = tap->txa_tid; 3768 wn = (void *)tap->txa_ni; 3769 wn->agg[tid].bitmap = bitmap; 3770 wn->agg[tid].startidx = start; 3771 wn->agg[tid].nframes = nframes; 3772 3773 res = NULL; 3774 ssn = 0; 3775 if (!IEEE80211_AMPDU_RUNNING(tap)) { 3776 res = tap->txa_private; 3777 ssn = tap->txa_start & 0xfff; 3778 } 3779 3780 /* This is going nframes DWORDS into the descriptor? */ 3781 seqno = le32toh(*(status + nframes)) & 0xfff; 3782 for (lastidx = (seqno & 0xff); ring->read != lastidx;) { 3783 data = &ring->data[ring->read]; 3784 3785 /* Unmap and free mbuf. */ 3786 bus_dmamap_sync(ring->data_dmat, data->map, 3787 BUS_DMASYNC_POSTWRITE); 3788 bus_dmamap_unload(ring->data_dmat, data->map); 3789 m = data->m, data->m = NULL; 3790 ni = data->ni, data->ni = NULL; 3791 3792 KASSERT(ni != NULL, ("no node")); 3793 KASSERT(m != NULL, ("no mbuf")); 3794 DPRINTF(sc, IWN_DEBUG_XMIT, "%s: freeing m=%p\n", __func__, m); 3795 ieee80211_tx_complete(ni, m, 1); 3796 3797 ring->queued--; 3798 ring->read = (ring->read + 1) % IWN_TX_RING_COUNT; 3799 } 3800 3801 if (ring->queued == 0 && res != NULL) { 3802 iwn_nic_lock(sc); 3803 ops->ampdu_tx_stop(sc, qid, tid, ssn); 3804 iwn_nic_unlock(sc); 3805 sc->qid2tap[qid] = NULL; 3806 free(res, M_DEVBUF); 3807 return; 3808 } 3809 3810 sc->sc_tx_timer = 0; 3811 if (ring->queued < IWN_TX_RING_LOMARK) 3812 sc->qfullmsk &= ~(1 << ring->qid); 3813 3814 DPRINTF(sc, IWN_DEBUG_TRACE, "->%s: end\n",__func__); 3815 } 3816 3817 /* 3818 * Process an INT_FH_RX or INT_SW_RX interrupt. 3819 */ 3820 static void 3821 iwn_notif_intr(struct iwn_softc *sc) 3822 { 3823 struct iwn_ops *ops = &sc->ops; 3824 struct ieee80211com *ic = &sc->sc_ic; 3825 struct ieee80211vap *vap = TAILQ_FIRST(&ic->ic_vaps); 3826 uint16_t hw; 3827 3828 bus_dmamap_sync(sc->rxq.stat_dma.tag, sc->rxq.stat_dma.map, 3829 BUS_DMASYNC_POSTREAD); 3830 3831 hw = le16toh(sc->rxq.stat->closed_count) & 0xfff; 3832 while (sc->rxq.cur != hw) { 3833 struct iwn_rx_data *data = &sc->rxq.data[sc->rxq.cur]; 3834 struct iwn_rx_desc *desc; 3835 3836 bus_dmamap_sync(sc->rxq.data_dmat, data->map, 3837 BUS_DMASYNC_POSTREAD); 3838 desc = mtod(data->m, struct iwn_rx_desc *); 3839 3840 DPRINTF(sc, IWN_DEBUG_RECV, 3841 "%s: cur=%d; qid %x idx %d flags %x type %d(%s) len %d\n", 3842 __func__, sc->rxq.cur, desc->qid & 0xf, desc->idx, desc->flags, 3843 desc->type, iwn_intr_str(desc->type), 3844 le16toh(desc->len)); 3845 3846 if (!(desc->qid & IWN_UNSOLICITED_RX_NOTIF)) /* Reply to a command. */ 3847 iwn_cmd_done(sc, desc); 3848 3849 switch (desc->type) { 3850 case IWN_RX_PHY: 3851 iwn_rx_phy(sc, desc, data); 3852 break; 3853 3854 case IWN_RX_DONE: /* 4965AGN only. */ 3855 case IWN_MPDU_RX_DONE: 3856 /* An 802.11 frame has been received. */ 3857 iwn_rx_done(sc, desc, data); 3858 break; 3859 3860 case IWN_RX_COMPRESSED_BA: 3861 /* A Compressed BlockAck has been received. */ 3862 iwn_rx_compressed_ba(sc, desc, data); 3863 break; 3864 3865 case IWN_TX_DONE: 3866 /* An 802.11 frame has been transmitted. */ 3867 ops->tx_done(sc, desc, data); 3868 break; 3869 3870 case IWN_RX_STATISTICS: 3871 case IWN_BEACON_STATISTICS: 3872 iwn_rx_statistics(sc, desc, data); 3873 break; 3874 3875 case IWN_BEACON_MISSED: 3876 { 3877 struct iwn_beacon_missed *miss = 3878 (struct iwn_beacon_missed *)(desc + 1); 3879 int misses; 3880 3881 bus_dmamap_sync(sc->rxq.data_dmat, data->map, 3882 BUS_DMASYNC_POSTREAD); 3883 misses = le32toh(miss->consecutive); 3884 3885 DPRINTF(sc, IWN_DEBUG_STATE, 3886 "%s: beacons missed %d/%d\n", __func__, 3887 misses, le32toh(miss->total)); 3888 /* 3889 * If more than 5 consecutive beacons are missed, 3890 * reinitialize the sensitivity state machine. 3891 */ 3892 if (vap->iv_state == IEEE80211_S_RUN && 3893 (ic->ic_flags & IEEE80211_F_SCAN) == 0) { 3894 if (misses > 5) 3895 (void)iwn_init_sensitivity(sc); 3896 if (misses >= vap->iv_bmissthreshold) { 3897 IWN_UNLOCK(sc); 3898 ieee80211_beacon_miss(ic); 3899 IWN_LOCK(sc); 3900 } 3901 } 3902 break; 3903 } 3904 case IWN_UC_READY: 3905 { 3906 struct iwn_ucode_info *uc = 3907 (struct iwn_ucode_info *)(desc + 1); 3908 3909 /* The microcontroller is ready. */ 3910 bus_dmamap_sync(sc->rxq.data_dmat, data->map, 3911 BUS_DMASYNC_POSTREAD); 3912 DPRINTF(sc, IWN_DEBUG_RESET, 3913 "microcode alive notification version=%d.%d " 3914 "subtype=%x alive=%x\n", uc->major, uc->minor, 3915 uc->subtype, le32toh(uc->valid)); 3916 3917 if (le32toh(uc->valid) != 1) { 3918 device_printf(sc->sc_dev, 3919 "microcontroller initialization failed"); 3920 break; 3921 } 3922 if (uc->subtype == IWN_UCODE_INIT) { 3923 /* Save microcontroller report. */ 3924 memcpy(&sc->ucode_info, uc, sizeof (*uc)); 3925 } 3926 /* Save the address of the error log in SRAM. */ 3927 sc->errptr = le32toh(uc->errptr); 3928 break; 3929 } 3930 case IWN_STATE_CHANGED: 3931 { 3932 /* 3933 * State change allows hardware switch change to be 3934 * noted. However, we handle this in iwn_intr as we 3935 * get both the enable/disble intr. 3936 */ 3937 bus_dmamap_sync(sc->rxq.data_dmat, data->map, 3938 BUS_DMASYNC_POSTREAD); 3939 #ifdef IWN_DEBUG 3940 uint32_t *status = (uint32_t *)(desc + 1); 3941 DPRINTF(sc, IWN_DEBUG_INTR | IWN_DEBUG_STATE, 3942 "state changed to %x\n", 3943 le32toh(*status)); 3944 #endif 3945 break; 3946 } 3947 case IWN_START_SCAN: 3948 { 3949 bus_dmamap_sync(sc->rxq.data_dmat, data->map, 3950 BUS_DMASYNC_POSTREAD); 3951 #ifdef IWN_DEBUG 3952 struct iwn_start_scan *scan = 3953 (struct iwn_start_scan *)(desc + 1); 3954 DPRINTF(sc, IWN_DEBUG_ANY, 3955 "%s: scanning channel %d status %x\n", 3956 __func__, scan->chan, le32toh(scan->status)); 3957 #endif 3958 break; 3959 } 3960 case IWN_STOP_SCAN: 3961 { 3962 bus_dmamap_sync(sc->rxq.data_dmat, data->map, 3963 BUS_DMASYNC_POSTREAD); 3964 #ifdef IWN_DEBUG 3965 struct iwn_stop_scan *scan = 3966 (struct iwn_stop_scan *)(desc + 1); 3967 DPRINTF(sc, IWN_DEBUG_STATE | IWN_DEBUG_SCAN, 3968 "scan finished nchan=%d status=%d chan=%d\n", 3969 scan->nchan, scan->status, scan->chan); 3970 #endif 3971 sc->sc_is_scanning = 0; 3972 callout_stop(&sc->scan_timeout); 3973 IWN_UNLOCK(sc); 3974 ieee80211_scan_next(vap); 3975 IWN_LOCK(sc); 3976 break; 3977 } 3978 case IWN5000_CALIBRATION_RESULT: 3979 iwn5000_rx_calib_results(sc, desc, data); 3980 break; 3981 3982 case IWN5000_CALIBRATION_DONE: 3983 sc->sc_flags |= IWN_FLAG_CALIB_DONE; 3984 wakeup(sc); 3985 break; 3986 } 3987 3988 sc->rxq.cur = (sc->rxq.cur + 1) % IWN_RX_RING_COUNT; 3989 } 3990 3991 /* Tell the firmware what we have processed. */ 3992 hw = (hw == 0) ? IWN_RX_RING_COUNT - 1 : hw - 1; 3993 IWN_WRITE(sc, IWN_FH_RX_WPTR, hw & ~7); 3994 } 3995 3996 /* 3997 * Process an INT_WAKEUP interrupt raised when the microcontroller wakes up 3998 * from power-down sleep mode. 3999 */ 4000 static void 4001 iwn_wakeup_intr(struct iwn_softc *sc) 4002 { 4003 int qid; 4004 4005 DPRINTF(sc, IWN_DEBUG_RESET, "%s: ucode wakeup from power-down sleep\n", 4006 __func__); 4007 4008 /* Wakeup RX and TX rings. */ 4009 IWN_WRITE(sc, IWN_FH_RX_WPTR, sc->rxq.cur & ~7); 4010 for (qid = 0; qid < sc->ntxqs; qid++) { 4011 struct iwn_tx_ring *ring = &sc->txq[qid]; 4012 IWN_WRITE(sc, IWN_HBUS_TARG_WRPTR, qid << 8 | ring->cur); 4013 } 4014 } 4015 4016 static void 4017 iwn_rftoggle_task(void *arg, int npending) 4018 { 4019 struct iwn_softc *sc = arg; 4020 struct ieee80211com *ic = &sc->sc_ic; 4021 uint32_t tmp; 4022 4023 IWN_LOCK(sc); 4024 tmp = IWN_READ(sc, IWN_GP_CNTRL); 4025 IWN_UNLOCK(sc); 4026 4027 device_printf(sc->sc_dev, "RF switch: radio %s\n", 4028 (tmp & IWN_GP_CNTRL_RFKILL) ? "enabled" : "disabled"); 4029 if (!(tmp & IWN_GP_CNTRL_RFKILL)) { 4030 ieee80211_suspend_all(ic); 4031 4032 /* Enable interrupts to get RF toggle notification. */ 4033 IWN_LOCK(sc); 4034 IWN_WRITE(sc, IWN_INT, 0xffffffff); 4035 IWN_WRITE(sc, IWN_INT_MASK, sc->int_mask); 4036 IWN_UNLOCK(sc); 4037 } else 4038 ieee80211_resume_all(ic); 4039 } 4040 4041 /* 4042 * Dump the error log of the firmware when a firmware panic occurs. Although 4043 * we can't debug the firmware because it is neither open source nor free, it 4044 * can help us to identify certain classes of problems. 4045 */ 4046 static void 4047 iwn_fatal_intr(struct iwn_softc *sc) 4048 { 4049 struct iwn_fw_dump dump; 4050 int i; 4051 4052 IWN_LOCK_ASSERT(sc); 4053 4054 /* Force a complete recalibration on next init. */ 4055 sc->sc_flags &= ~IWN_FLAG_CALIB_DONE; 4056 4057 /* Check that the error log address is valid. */ 4058 if (sc->errptr < IWN_FW_DATA_BASE || 4059 sc->errptr + sizeof (dump) > 4060 IWN_FW_DATA_BASE + sc->fw_data_maxsz) { 4061 printf("%s: bad firmware error log address 0x%08x\n", __func__, 4062 sc->errptr); 4063 return; 4064 } 4065 if (iwn_nic_lock(sc) != 0) { 4066 printf("%s: could not read firmware error log\n", __func__); 4067 return; 4068 } 4069 /* Read firmware error log from SRAM. */ 4070 iwn_mem_read_region_4(sc, sc->errptr, (uint32_t *)&dump, 4071 sizeof (dump) / sizeof (uint32_t)); 4072 iwn_nic_unlock(sc); 4073 4074 if (dump.valid == 0) { 4075 printf("%s: firmware error log is empty\n", __func__); 4076 return; 4077 } 4078 printf("firmware error log:\n"); 4079 printf(" error type = \"%s\" (0x%08X)\n", 4080 (dump.id < nitems(iwn_fw_errmsg)) ? 4081 iwn_fw_errmsg[dump.id] : "UNKNOWN", 4082 dump.id); 4083 printf(" program counter = 0x%08X\n", dump.pc); 4084 printf(" source line = 0x%08X\n", dump.src_line); 4085 printf(" error data = 0x%08X%08X\n", 4086 dump.error_data[0], dump.error_data[1]); 4087 printf(" branch link = 0x%08X%08X\n", 4088 dump.branch_link[0], dump.branch_link[1]); 4089 printf(" interrupt link = 0x%08X%08X\n", 4090 dump.interrupt_link[0], dump.interrupt_link[1]); 4091 printf(" time = %u\n", dump.time[0]); 4092 4093 /* Dump driver status (TX and RX rings) while we're here. */ 4094 printf("driver status:\n"); 4095 for (i = 0; i < sc->ntxqs; i++) { 4096 struct iwn_tx_ring *ring = &sc->txq[i]; 4097 printf(" tx ring %2d: qid=%-2d cur=%-3d queued=%-3d\n", 4098 i, ring->qid, ring->cur, ring->queued); 4099 } 4100 printf(" rx ring: cur=%d\n", sc->rxq.cur); 4101 } 4102 4103 static void 4104 iwn_intr(void *arg) 4105 { 4106 struct iwn_softc *sc = arg; 4107 uint32_t r1, r2, tmp; 4108 4109 IWN_LOCK(sc); 4110 4111 /* Disable interrupts. */ 4112 IWN_WRITE(sc, IWN_INT_MASK, 0); 4113 4114 /* Read interrupts from ICT (fast) or from registers (slow). */ 4115 if (sc->sc_flags & IWN_FLAG_USE_ICT) { 4116 bus_dmamap_sync(sc->ict_dma.tag, sc->ict_dma.map, 4117 BUS_DMASYNC_POSTREAD); 4118 tmp = 0; 4119 while (sc->ict[sc->ict_cur] != 0) { 4120 tmp |= sc->ict[sc->ict_cur]; 4121 sc->ict[sc->ict_cur] = 0; /* Acknowledge. */ 4122 sc->ict_cur = (sc->ict_cur + 1) % IWN_ICT_COUNT; 4123 } 4124 tmp = le32toh(tmp); 4125 if (tmp == 0xffffffff) /* Shouldn't happen. */ 4126 tmp = 0; 4127 else if (tmp & 0xc0000) /* Workaround a HW bug. */ 4128 tmp |= 0x8000; 4129 r1 = (tmp & 0xff00) << 16 | (tmp & 0xff); 4130 r2 = 0; /* Unused. */ 4131 } else { 4132 r1 = IWN_READ(sc, IWN_INT); 4133 if (r1 == 0xffffffff || (r1 & 0xfffffff0) == 0xa5a5a5a0) { 4134 IWN_UNLOCK(sc); 4135 return; /* Hardware gone! */ 4136 } 4137 r2 = IWN_READ(sc, IWN_FH_INT); 4138 } 4139 4140 DPRINTF(sc, IWN_DEBUG_INTR, "interrupt reg1=0x%08x reg2=0x%08x\n" 4141 , r1, r2); 4142 4143 if (r1 == 0 && r2 == 0) 4144 goto done; /* Interrupt not for us. */ 4145 4146 /* Acknowledge interrupts. */ 4147 IWN_WRITE(sc, IWN_INT, r1); 4148 if (!(sc->sc_flags & IWN_FLAG_USE_ICT)) 4149 IWN_WRITE(sc, IWN_FH_INT, r2); 4150 4151 if (r1 & IWN_INT_RF_TOGGLED) { 4152 taskqueue_enqueue(sc->sc_tq, &sc->sc_rftoggle_task); 4153 goto done; 4154 } 4155 if (r1 & IWN_INT_CT_REACHED) { 4156 device_printf(sc->sc_dev, "%s: critical temperature reached!\n", 4157 __func__); 4158 } 4159 if (r1 & (IWN_INT_SW_ERR | IWN_INT_HW_ERR)) { 4160 device_printf(sc->sc_dev, "%s: fatal firmware error\n", 4161 __func__); 4162 #ifdef IWN_DEBUG 4163 iwn_debug_register(sc); 4164 #endif 4165 /* Dump firmware error log and stop. */ 4166 iwn_fatal_intr(sc); 4167 4168 taskqueue_enqueue(sc->sc_tq, &sc->sc_panic_task); 4169 goto done; 4170 } 4171 if ((r1 & (IWN_INT_FH_RX | IWN_INT_SW_RX | IWN_INT_RX_PERIODIC)) || 4172 (r2 & IWN_FH_INT_RX)) { 4173 if (sc->sc_flags & IWN_FLAG_USE_ICT) { 4174 if (r1 & (IWN_INT_FH_RX | IWN_INT_SW_RX)) 4175 IWN_WRITE(sc, IWN_FH_INT, IWN_FH_INT_RX); 4176 IWN_WRITE_1(sc, IWN_INT_PERIODIC, 4177 IWN_INT_PERIODIC_DIS); 4178 iwn_notif_intr(sc); 4179 if (r1 & (IWN_INT_FH_RX | IWN_INT_SW_RX)) { 4180 IWN_WRITE_1(sc, IWN_INT_PERIODIC, 4181 IWN_INT_PERIODIC_ENA); 4182 } 4183 } else 4184 iwn_notif_intr(sc); 4185 } 4186 4187 if ((r1 & IWN_INT_FH_TX) || (r2 & IWN_FH_INT_TX)) { 4188 if (sc->sc_flags & IWN_FLAG_USE_ICT) 4189 IWN_WRITE(sc, IWN_FH_INT, IWN_FH_INT_TX); 4190 wakeup(sc); /* FH DMA transfer completed. */ 4191 } 4192 4193 if (r1 & IWN_INT_ALIVE) 4194 wakeup(sc); /* Firmware is alive. */ 4195 4196 if (r1 & IWN_INT_WAKEUP) 4197 iwn_wakeup_intr(sc); 4198 4199 done: 4200 /* Re-enable interrupts. */ 4201 if (sc->sc_flags & IWN_FLAG_RUNNING) 4202 IWN_WRITE(sc, IWN_INT_MASK, sc->int_mask); 4203 4204 IWN_UNLOCK(sc); 4205 } 4206 4207 /* 4208 * Update TX scheduler ring when transmitting an 802.11 frame (4965AGN and 4209 * 5000 adapters use a slightly different format). 4210 */ 4211 static void 4212 iwn4965_update_sched(struct iwn_softc *sc, int qid, int idx, uint8_t id, 4213 uint16_t len) 4214 { 4215 uint16_t *w = &sc->sched[qid * IWN4965_SCHED_COUNT + idx]; 4216 4217 DPRINTF(sc, IWN_DEBUG_TRACE, "->Doing %s\n", __func__); 4218 4219 *w = htole16(len + 8); 4220 bus_dmamap_sync(sc->sched_dma.tag, sc->sched_dma.map, 4221 BUS_DMASYNC_PREWRITE); 4222 if (idx < IWN_SCHED_WINSZ) { 4223 *(w + IWN_TX_RING_COUNT) = *w; 4224 bus_dmamap_sync(sc->sched_dma.tag, sc->sched_dma.map, 4225 BUS_DMASYNC_PREWRITE); 4226 } 4227 } 4228 4229 static void 4230 iwn5000_update_sched(struct iwn_softc *sc, int qid, int idx, uint8_t id, 4231 uint16_t len) 4232 { 4233 uint16_t *w = &sc->sched[qid * IWN5000_SCHED_COUNT + idx]; 4234 4235 DPRINTF(sc, IWN_DEBUG_TRACE, "->Doing %s\n", __func__); 4236 4237 *w = htole16(id << 12 | (len + 8)); 4238 bus_dmamap_sync(sc->sched_dma.tag, sc->sched_dma.map, 4239 BUS_DMASYNC_PREWRITE); 4240 if (idx < IWN_SCHED_WINSZ) { 4241 *(w + IWN_TX_RING_COUNT) = *w; 4242 bus_dmamap_sync(sc->sched_dma.tag, sc->sched_dma.map, 4243 BUS_DMASYNC_PREWRITE); 4244 } 4245 } 4246 4247 #ifdef notyet 4248 static void 4249 iwn5000_reset_sched(struct iwn_softc *sc, int qid, int idx) 4250 { 4251 uint16_t *w = &sc->sched[qid * IWN5000_SCHED_COUNT + idx]; 4252 4253 DPRINTF(sc, IWN_DEBUG_TRACE, "->Doing %s\n", __func__); 4254 4255 *w = (*w & htole16(0xf000)) | htole16(1); 4256 bus_dmamap_sync(sc->sched_dma.tag, sc->sched_dma.map, 4257 BUS_DMASYNC_PREWRITE); 4258 if (idx < IWN_SCHED_WINSZ) { 4259 *(w + IWN_TX_RING_COUNT) = *w; 4260 bus_dmamap_sync(sc->sched_dma.tag, sc->sched_dma.map, 4261 BUS_DMASYNC_PREWRITE); 4262 } 4263 } 4264 #endif 4265 4266 /* 4267 * Check whether OFDM 11g protection will be enabled for the given rate. 4268 * 4269 * The original driver code only enabled protection for OFDM rates. 4270 * It didn't check to see whether it was operating in 11a or 11bg mode. 4271 */ 4272 static int 4273 iwn_check_rate_needs_protection(struct iwn_softc *sc, 4274 struct ieee80211vap *vap, uint8_t rate) 4275 { 4276 struct ieee80211com *ic = vap->iv_ic; 4277 4278 /* 4279 * Not in 2GHz mode? Then there's no need to enable OFDM 4280 * 11bg protection. 4281 */ 4282 if (! IEEE80211_IS_CHAN_2GHZ(ic->ic_curchan)) { 4283 return (0); 4284 } 4285 4286 /* 4287 * 11bg protection not enabled? Then don't use it. 4288 */ 4289 if ((ic->ic_flags & IEEE80211_F_USEPROT) == 0) 4290 return (0); 4291 4292 /* 4293 * If it's an 11n rate - no protection. 4294 * We'll do it via a specific 11n check. 4295 */ 4296 if (rate & IEEE80211_RATE_MCS) { 4297 return (0); 4298 } 4299 4300 /* 4301 * Do a rate table lookup. If the PHY is CCK, 4302 * don't do protection. 4303 */ 4304 if (ieee80211_rate2phytype(ic->ic_rt, rate) == IEEE80211_T_CCK) 4305 return (0); 4306 4307 /* 4308 * Yup, enable protection. 4309 */ 4310 return (1); 4311 } 4312 4313 /* 4314 * return a value between 0 and IWN_MAX_TX_RETRIES-1 as an index into 4315 * the link quality table that reflects this particular entry. 4316 */ 4317 static int 4318 iwn_tx_rate_to_linkq_offset(struct iwn_softc *sc, struct ieee80211_node *ni, 4319 uint8_t rate) 4320 { 4321 struct ieee80211_rateset *rs; 4322 int is_11n; 4323 int nr; 4324 int i; 4325 uint8_t cmp_rate; 4326 4327 /* 4328 * Figure out if we're using 11n or not here. 4329 */ 4330 if (IEEE80211_IS_CHAN_HT(ni->ni_chan) && ni->ni_htrates.rs_nrates > 0) 4331 is_11n = 1; 4332 else 4333 is_11n = 0; 4334 4335 /* 4336 * Use the correct rate table. 4337 */ 4338 if (is_11n) { 4339 rs = (struct ieee80211_rateset *) &ni->ni_htrates; 4340 nr = ni->ni_htrates.rs_nrates; 4341 } else { 4342 rs = &ni->ni_rates; 4343 nr = rs->rs_nrates; 4344 } 4345 4346 /* 4347 * Find the relevant link quality entry in the table. 4348 */ 4349 for (i = 0; i < nr && i < IWN_MAX_TX_RETRIES - 1 ; i++) { 4350 /* 4351 * The link quality table index starts at 0 == highest 4352 * rate, so we walk the rate table backwards. 4353 */ 4354 cmp_rate = rs->rs_rates[(nr - 1) - i]; 4355 if (rate & IEEE80211_RATE_MCS) 4356 cmp_rate |= IEEE80211_RATE_MCS; 4357 4358 #if 0 4359 DPRINTF(sc, IWN_DEBUG_XMIT, "%s: idx %d: nr=%d, rate=0x%02x, rateentry=0x%02x\n", 4360 __func__, 4361 i, 4362 nr, 4363 rate, 4364 cmp_rate); 4365 #endif 4366 4367 if (cmp_rate == rate) 4368 return (i); 4369 } 4370 4371 /* Failed? Start at the end */ 4372 return (IWN_MAX_TX_RETRIES - 1); 4373 } 4374 4375 static int 4376 iwn_tx_data(struct iwn_softc *sc, struct mbuf *m, struct ieee80211_node *ni) 4377 { 4378 struct iwn_ops *ops = &sc->ops; 4379 const struct ieee80211_txparam *tp = ni->ni_txparms; 4380 struct ieee80211vap *vap = ni->ni_vap; 4381 struct ieee80211com *ic = ni->ni_ic; 4382 struct iwn_node *wn = (void *)ni; 4383 struct iwn_tx_ring *ring; 4384 struct iwn_tx_desc *desc; 4385 struct iwn_tx_data *data; 4386 struct iwn_tx_cmd *cmd; 4387 struct iwn_cmd_data *tx; 4388 struct ieee80211_frame *wh; 4389 struct ieee80211_key *k = NULL; 4390 struct mbuf *m1; 4391 uint32_t flags; 4392 uint16_t qos; 4393 u_int hdrlen; 4394 bus_dma_segment_t *seg, segs[IWN_MAX_SCATTER]; 4395 uint8_t tid, type; 4396 int ac, i, totlen, error, pad, nsegs = 0, rate; 4397 4398 DPRINTF(sc, IWN_DEBUG_TRACE, "->%s begin\n", __func__); 4399 4400 IWN_LOCK_ASSERT(sc); 4401 4402 wh = mtod(m, struct ieee80211_frame *); 4403 hdrlen = ieee80211_anyhdrsize(wh); 4404 type = wh->i_fc[0] & IEEE80211_FC0_TYPE_MASK; 4405 4406 /* Select EDCA Access Category and TX ring for this frame. */ 4407 if (IEEE80211_QOS_HAS_SEQ(wh)) { 4408 qos = ((const struct ieee80211_qosframe *)wh)->i_qos[0]; 4409 tid = qos & IEEE80211_QOS_TID; 4410 } else { 4411 qos = 0; 4412 tid = 0; 4413 } 4414 ac = M_WME_GETAC(m); 4415 4416 /* 4417 * XXX TODO: Group addressed frames aren't aggregated and must 4418 * go to the normal non-aggregation queue, and have a NONQOS TID 4419 * assigned from net80211. 4420 */ 4421 4422 if (m->m_flags & M_AMPDU_MPDU) { 4423 uint16_t seqno; 4424 struct ieee80211_tx_ampdu *tap = &ni->ni_tx_ampdu[ac]; 4425 4426 if (!IEEE80211_AMPDU_RUNNING(tap)) { 4427 return EINVAL; 4428 } 4429 4430 /* 4431 * Queue this frame to the hardware ring that we've 4432 * negotiated AMPDU TX on. 4433 * 4434 * Note that the sequence number must match the TX slot 4435 * being used! 4436 */ 4437 ac = *(int *)tap->txa_private; 4438 seqno = ni->ni_txseqs[tid]; 4439 *(uint16_t *)wh->i_seq = 4440 htole16(seqno << IEEE80211_SEQ_SEQ_SHIFT); 4441 ring = &sc->txq[ac]; 4442 if ((seqno % 256) != ring->cur) { 4443 device_printf(sc->sc_dev, 4444 "%s: m=%p: seqno (%d) (%d) != ring index (%d) !\n", 4445 __func__, 4446 m, 4447 seqno, 4448 seqno % 256, 4449 ring->cur); 4450 } 4451 ni->ni_txseqs[tid]++; 4452 } 4453 ring = &sc->txq[ac]; 4454 desc = &ring->desc[ring->cur]; 4455 data = &ring->data[ring->cur]; 4456 4457 /* Choose a TX rate index. */ 4458 if (type == IEEE80211_FC0_TYPE_MGT || 4459 type == IEEE80211_FC0_TYPE_CTL || 4460 (m->m_flags & M_EAPOL) != 0) 4461 rate = tp->mgmtrate; 4462 else if (IEEE80211_IS_MULTICAST(wh->i_addr1)) 4463 rate = tp->mcastrate; 4464 else if (tp->ucastrate != IEEE80211_FIXED_RATE_NONE) 4465 rate = tp->ucastrate; 4466 else { 4467 /* XXX pass pktlen */ 4468 (void) ieee80211_ratectl_rate(ni, NULL, 0); 4469 rate = ni->ni_txrate; 4470 } 4471 4472 /* Encrypt the frame if need be. */ 4473 if (wh->i_fc[1] & IEEE80211_FC1_PROTECTED) { 4474 /* Retrieve key for TX. */ 4475 k = ieee80211_crypto_encap(ni, m); 4476 if (k == NULL) { 4477 return ENOBUFS; 4478 } 4479 /* 802.11 header may have moved. */ 4480 wh = mtod(m, struct ieee80211_frame *); 4481 } 4482 totlen = m->m_pkthdr.len; 4483 4484 if (ieee80211_radiotap_active_vap(vap)) { 4485 struct iwn_tx_radiotap_header *tap = &sc->sc_txtap; 4486 4487 tap->wt_flags = 0; 4488 tap->wt_rate = rate; 4489 if (k != NULL) 4490 tap->wt_flags |= IEEE80211_RADIOTAP_F_WEP; 4491 4492 ieee80211_radiotap_tx(vap, m); 4493 } 4494 4495 /* Prepare TX firmware command. */ 4496 cmd = &ring->cmd[ring->cur]; 4497 cmd->code = IWN_CMD_TX_DATA; 4498 cmd->flags = 0; 4499 cmd->qid = ring->qid; 4500 cmd->idx = ring->cur; 4501 4502 tx = (struct iwn_cmd_data *)cmd->data; 4503 /* NB: No need to clear tx, all fields are reinitialized here. */ 4504 tx->scratch = 0; /* clear "scratch" area */ 4505 4506 flags = 0; 4507 if (!IEEE80211_IS_MULTICAST(wh->i_addr1)) { 4508 /* Unicast frame, check if an ACK is expected. */ 4509 if (!qos || (qos & IEEE80211_QOS_ACKPOLICY) != 4510 IEEE80211_QOS_ACKPOLICY_NOACK) 4511 flags |= IWN_TX_NEED_ACK; 4512 } 4513 if ((wh->i_fc[0] & 4514 (IEEE80211_FC0_TYPE_MASK | IEEE80211_FC0_SUBTYPE_MASK)) == 4515 (IEEE80211_FC0_TYPE_CTL | IEEE80211_FC0_SUBTYPE_BAR)) 4516 flags |= IWN_TX_IMM_BA; /* Cannot happen yet. */ 4517 4518 if (wh->i_fc[1] & IEEE80211_FC1_MORE_FRAG) 4519 flags |= IWN_TX_MORE_FRAG; /* Cannot happen yet. */ 4520 4521 /* Check if frame must be protected using RTS/CTS or CTS-to-self. */ 4522 if (!IEEE80211_IS_MULTICAST(wh->i_addr1)) { 4523 /* NB: Group frames are sent using CCK in 802.11b/g. */ 4524 if (totlen + IEEE80211_CRC_LEN > vap->iv_rtsthreshold) { 4525 flags |= IWN_TX_NEED_RTS; 4526 } else if (iwn_check_rate_needs_protection(sc, vap, rate)) { 4527 if (ic->ic_protmode == IEEE80211_PROT_CTSONLY) 4528 flags |= IWN_TX_NEED_CTS; 4529 else if (ic->ic_protmode == IEEE80211_PROT_RTSCTS) 4530 flags |= IWN_TX_NEED_RTS; 4531 } else if ((rate & IEEE80211_RATE_MCS) && 4532 (ic->ic_htprotmode == IEEE80211_PROT_RTSCTS)) { 4533 flags |= IWN_TX_NEED_RTS; 4534 } 4535 4536 /* XXX HT protection? */ 4537 4538 if (flags & (IWN_TX_NEED_RTS | IWN_TX_NEED_CTS)) { 4539 if (sc->hw_type != IWN_HW_REV_TYPE_4965) { 4540 /* 5000 autoselects RTS/CTS or CTS-to-self. */ 4541 flags &= ~(IWN_TX_NEED_RTS | IWN_TX_NEED_CTS); 4542 flags |= IWN_TX_NEED_PROTECTION; 4543 } else 4544 flags |= IWN_TX_FULL_TXOP; 4545 } 4546 } 4547 4548 if (IEEE80211_IS_MULTICAST(wh->i_addr1) || 4549 type != IEEE80211_FC0_TYPE_DATA) 4550 tx->id = sc->broadcast_id; 4551 else 4552 tx->id = wn->id; 4553 4554 if (type == IEEE80211_FC0_TYPE_MGT) { 4555 uint8_t subtype = wh->i_fc[0] & IEEE80211_FC0_SUBTYPE_MASK; 4556 4557 /* Tell HW to set timestamp in probe responses. */ 4558 if (subtype == IEEE80211_FC0_SUBTYPE_PROBE_RESP) 4559 flags |= IWN_TX_INSERT_TSTAMP; 4560 if (subtype == IEEE80211_FC0_SUBTYPE_ASSOC_REQ || 4561 subtype == IEEE80211_FC0_SUBTYPE_REASSOC_REQ) 4562 tx->timeout = htole16(3); 4563 else 4564 tx->timeout = htole16(2); 4565 } else 4566 tx->timeout = htole16(0); 4567 4568 if (hdrlen & 3) { 4569 /* First segment length must be a multiple of 4. */ 4570 flags |= IWN_TX_NEED_PADDING; 4571 pad = 4 - (hdrlen & 3); 4572 } else 4573 pad = 0; 4574 4575 tx->len = htole16(totlen); 4576 tx->tid = tid; 4577 tx->rts_ntries = 60; 4578 tx->data_ntries = 15; 4579 tx->lifetime = htole32(IWN_LIFETIME_INFINITE); 4580 tx->rate = iwn_rate_to_plcp(sc, ni, rate); 4581 if (tx->id == sc->broadcast_id) { 4582 /* Group or management frame. */ 4583 tx->linkq = 0; 4584 } else { 4585 tx->linkq = iwn_tx_rate_to_linkq_offset(sc, ni, rate); 4586 flags |= IWN_TX_LINKQ; /* enable MRR */ 4587 } 4588 4589 /* Set physical address of "scratch area". */ 4590 tx->loaddr = htole32(IWN_LOADDR(data->scratch_paddr)); 4591 tx->hiaddr = IWN_HIADDR(data->scratch_paddr); 4592 4593 /* Copy 802.11 header in TX command. */ 4594 memcpy((uint8_t *)(tx + 1), wh, hdrlen); 4595 4596 /* Trim 802.11 header. */ 4597 m_adj(m, hdrlen); 4598 tx->security = 0; 4599 tx->flags = htole32(flags); 4600 4601 error = bus_dmamap_load_mbuf_sg(ring->data_dmat, data->map, m, segs, 4602 &nsegs, BUS_DMA_NOWAIT); 4603 if (error != 0) { 4604 if (error != EFBIG) { 4605 device_printf(sc->sc_dev, 4606 "%s: can't map mbuf (error %d)\n", __func__, error); 4607 return error; 4608 } 4609 /* Too many DMA segments, linearize mbuf. */ 4610 m1 = m_collapse(m, M_NOWAIT, IWN_MAX_SCATTER - 1); 4611 if (m1 == NULL) { 4612 device_printf(sc->sc_dev, 4613 "%s: could not defrag mbuf\n", __func__); 4614 return ENOBUFS; 4615 } 4616 m = m1; 4617 4618 error = bus_dmamap_load_mbuf_sg(ring->data_dmat, data->map, m, 4619 segs, &nsegs, BUS_DMA_NOWAIT); 4620 if (error != 0) { 4621 device_printf(sc->sc_dev, 4622 "%s: can't map mbuf (error %d)\n", __func__, error); 4623 return error; 4624 } 4625 } 4626 4627 data->m = m; 4628 data->ni = ni; 4629 4630 DPRINTF(sc, IWN_DEBUG_XMIT, 4631 "%s: qid %d idx %d len %d nsegs %d flags 0x%08x rate 0x%04x plcp 0x%08x\n", 4632 __func__, 4633 ring->qid, 4634 ring->cur, 4635 m->m_pkthdr.len, 4636 nsegs, 4637 flags, 4638 rate, 4639 tx->rate); 4640 4641 /* Fill TX descriptor. */ 4642 desc->nsegs = 1; 4643 if (m->m_len != 0) 4644 desc->nsegs += nsegs; 4645 /* First DMA segment is used by the TX command. */ 4646 desc->segs[0].addr = htole32(IWN_LOADDR(data->cmd_paddr)); 4647 desc->segs[0].len = htole16(IWN_HIADDR(data->cmd_paddr) | 4648 (4 + sizeof (*tx) + hdrlen + pad) << 4); 4649 /* Other DMA segments are for data payload. */ 4650 seg = &segs[0]; 4651 for (i = 1; i <= nsegs; i++) { 4652 desc->segs[i].addr = htole32(IWN_LOADDR(seg->ds_addr)); 4653 desc->segs[i].len = htole16(IWN_HIADDR(seg->ds_addr) | 4654 seg->ds_len << 4); 4655 seg++; 4656 } 4657 4658 bus_dmamap_sync(ring->data_dmat, data->map, BUS_DMASYNC_PREWRITE); 4659 bus_dmamap_sync(ring->cmd_dma.tag, ring->cmd_dma.map, 4660 BUS_DMASYNC_PREWRITE); 4661 bus_dmamap_sync(ring->desc_dma.tag, ring->desc_dma.map, 4662 BUS_DMASYNC_PREWRITE); 4663 4664 /* Update TX scheduler. */ 4665 if (ring->qid >= sc->firstaggqueue) 4666 ops->update_sched(sc, ring->qid, ring->cur, tx->id, totlen); 4667 4668 /* Kick TX ring. */ 4669 ring->cur = (ring->cur + 1) % IWN_TX_RING_COUNT; 4670 IWN_WRITE(sc, IWN_HBUS_TARG_WRPTR, ring->qid << 8 | ring->cur); 4671 4672 /* Mark TX ring as full if we reach a certain threshold. */ 4673 if (++ring->queued > IWN_TX_RING_HIMARK) 4674 sc->qfullmsk |= 1 << ring->qid; 4675 4676 DPRINTF(sc, IWN_DEBUG_TRACE, "->%s: end\n",__func__); 4677 4678 return 0; 4679 } 4680 4681 static int 4682 iwn_tx_data_raw(struct iwn_softc *sc, struct mbuf *m, 4683 struct ieee80211_node *ni, const struct ieee80211_bpf_params *params) 4684 { 4685 struct iwn_ops *ops = &sc->ops; 4686 struct ieee80211vap *vap = ni->ni_vap; 4687 struct iwn_tx_cmd *cmd; 4688 struct iwn_cmd_data *tx; 4689 struct ieee80211_frame *wh; 4690 struct iwn_tx_ring *ring; 4691 struct iwn_tx_desc *desc; 4692 struct iwn_tx_data *data; 4693 struct mbuf *m1; 4694 bus_dma_segment_t *seg, segs[IWN_MAX_SCATTER]; 4695 uint32_t flags; 4696 u_int hdrlen; 4697 int ac, totlen, error, pad, nsegs = 0, i, rate; 4698 uint8_t type; 4699 4700 DPRINTF(sc, IWN_DEBUG_TRACE, "->%s begin\n", __func__); 4701 4702 IWN_LOCK_ASSERT(sc); 4703 4704 wh = mtod(m, struct ieee80211_frame *); 4705 hdrlen = ieee80211_anyhdrsize(wh); 4706 type = wh->i_fc[0] & IEEE80211_FC0_TYPE_MASK; 4707 4708 ac = params->ibp_pri & 3; 4709 4710 ring = &sc->txq[ac]; 4711 desc = &ring->desc[ring->cur]; 4712 data = &ring->data[ring->cur]; 4713 4714 /* Choose a TX rate. */ 4715 rate = params->ibp_rate0; 4716 totlen = m->m_pkthdr.len; 4717 4718 /* Prepare TX firmware command. */ 4719 cmd = &ring->cmd[ring->cur]; 4720 cmd->code = IWN_CMD_TX_DATA; 4721 cmd->flags = 0; 4722 cmd->qid = ring->qid; 4723 cmd->idx = ring->cur; 4724 4725 tx = (struct iwn_cmd_data *)cmd->data; 4726 /* NB: No need to clear tx, all fields are reinitialized here. */ 4727 tx->scratch = 0; /* clear "scratch" area */ 4728 4729 flags = 0; 4730 if ((params->ibp_flags & IEEE80211_BPF_NOACK) == 0) 4731 flags |= IWN_TX_NEED_ACK; 4732 if (params->ibp_flags & IEEE80211_BPF_RTS) { 4733 if (sc->hw_type != IWN_HW_REV_TYPE_4965) { 4734 /* 5000 autoselects RTS/CTS or CTS-to-self. */ 4735 flags &= ~IWN_TX_NEED_RTS; 4736 flags |= IWN_TX_NEED_PROTECTION; 4737 } else 4738 flags |= IWN_TX_NEED_RTS | IWN_TX_FULL_TXOP; 4739 } 4740 if (params->ibp_flags & IEEE80211_BPF_CTS) { 4741 if (sc->hw_type != IWN_HW_REV_TYPE_4965) { 4742 /* 5000 autoselects RTS/CTS or CTS-to-self. */ 4743 flags &= ~IWN_TX_NEED_CTS; 4744 flags |= IWN_TX_NEED_PROTECTION; 4745 } else 4746 flags |= IWN_TX_NEED_CTS | IWN_TX_FULL_TXOP; 4747 } 4748 if (type == IEEE80211_FC0_TYPE_MGT) { 4749 uint8_t subtype = wh->i_fc[0] & IEEE80211_FC0_SUBTYPE_MASK; 4750 4751 /* Tell HW to set timestamp in probe responses. */ 4752 if (subtype == IEEE80211_FC0_SUBTYPE_PROBE_RESP) 4753 flags |= IWN_TX_INSERT_TSTAMP; 4754 4755 if (subtype == IEEE80211_FC0_SUBTYPE_ASSOC_REQ || 4756 subtype == IEEE80211_FC0_SUBTYPE_REASSOC_REQ) 4757 tx->timeout = htole16(3); 4758 else 4759 tx->timeout = htole16(2); 4760 } else 4761 tx->timeout = htole16(0); 4762 4763 if (hdrlen & 3) { 4764 /* First segment length must be a multiple of 4. */ 4765 flags |= IWN_TX_NEED_PADDING; 4766 pad = 4 - (hdrlen & 3); 4767 } else 4768 pad = 0; 4769 4770 if (ieee80211_radiotap_active_vap(vap)) { 4771 struct iwn_tx_radiotap_header *tap = &sc->sc_txtap; 4772 4773 tap->wt_flags = 0; 4774 tap->wt_rate = rate; 4775 4776 ieee80211_radiotap_tx(vap, m); 4777 } 4778 4779 tx->len = htole16(totlen); 4780 tx->tid = 0; 4781 tx->id = sc->broadcast_id; 4782 tx->rts_ntries = params->ibp_try1; 4783 tx->data_ntries = params->ibp_try0; 4784 tx->lifetime = htole32(IWN_LIFETIME_INFINITE); 4785 tx->rate = iwn_rate_to_plcp(sc, ni, rate); 4786 4787 /* Group or management frame. */ 4788 tx->linkq = 0; 4789 4790 /* Set physical address of "scratch area". */ 4791 tx->loaddr = htole32(IWN_LOADDR(data->scratch_paddr)); 4792 tx->hiaddr = IWN_HIADDR(data->scratch_paddr); 4793 4794 /* Copy 802.11 header in TX command. */ 4795 memcpy((uint8_t *)(tx + 1), wh, hdrlen); 4796 4797 /* Trim 802.11 header. */ 4798 m_adj(m, hdrlen); 4799 tx->security = 0; 4800 tx->flags = htole32(flags); 4801 4802 error = bus_dmamap_load_mbuf_sg(ring->data_dmat, data->map, m, segs, 4803 &nsegs, BUS_DMA_NOWAIT); 4804 if (error != 0) { 4805 if (error != EFBIG) { 4806 device_printf(sc->sc_dev, 4807 "%s: can't map mbuf (error %d)\n", __func__, error); 4808 return error; 4809 } 4810 /* Too many DMA segments, linearize mbuf. */ 4811 m1 = m_collapse(m, M_NOWAIT, IWN_MAX_SCATTER - 1); 4812 if (m1 == NULL) { 4813 device_printf(sc->sc_dev, 4814 "%s: could not defrag mbuf\n", __func__); 4815 return ENOBUFS; 4816 } 4817 m = m1; 4818 4819 error = bus_dmamap_load_mbuf_sg(ring->data_dmat, data->map, m, 4820 segs, &nsegs, BUS_DMA_NOWAIT); 4821 if (error != 0) { 4822 device_printf(sc->sc_dev, 4823 "%s: can't map mbuf (error %d)\n", __func__, error); 4824 return error; 4825 } 4826 } 4827 4828 data->m = m; 4829 data->ni = ni; 4830 4831 DPRINTF(sc, IWN_DEBUG_XMIT, "%s: qid %d idx %d len %d nsegs %d\n", 4832 __func__, ring->qid, ring->cur, m->m_pkthdr.len, nsegs); 4833 4834 /* Fill TX descriptor. */ 4835 desc->nsegs = 1; 4836 if (m->m_len != 0) 4837 desc->nsegs += nsegs; 4838 /* First DMA segment is used by the TX command. */ 4839 desc->segs[0].addr = htole32(IWN_LOADDR(data->cmd_paddr)); 4840 desc->segs[0].len = htole16(IWN_HIADDR(data->cmd_paddr) | 4841 (4 + sizeof (*tx) + hdrlen + pad) << 4); 4842 /* Other DMA segments are for data payload. */ 4843 seg = &segs[0]; 4844 for (i = 1; i <= nsegs; i++) { 4845 desc->segs[i].addr = htole32(IWN_LOADDR(seg->ds_addr)); 4846 desc->segs[i].len = htole16(IWN_HIADDR(seg->ds_addr) | 4847 seg->ds_len << 4); 4848 seg++; 4849 } 4850 4851 bus_dmamap_sync(ring->data_dmat, data->map, BUS_DMASYNC_PREWRITE); 4852 bus_dmamap_sync(ring->cmd_dma.tag, ring->cmd_dma.map, 4853 BUS_DMASYNC_PREWRITE); 4854 bus_dmamap_sync(ring->desc_dma.tag, ring->desc_dma.map, 4855 BUS_DMASYNC_PREWRITE); 4856 4857 /* Update TX scheduler. */ 4858 if (ring->qid >= sc->firstaggqueue) 4859 ops->update_sched(sc, ring->qid, ring->cur, tx->id, totlen); 4860 4861 /* Kick TX ring. */ 4862 ring->cur = (ring->cur + 1) % IWN_TX_RING_COUNT; 4863 IWN_WRITE(sc, IWN_HBUS_TARG_WRPTR, ring->qid << 8 | ring->cur); 4864 4865 /* Mark TX ring as full if we reach a certain threshold. */ 4866 if (++ring->queued > IWN_TX_RING_HIMARK) 4867 sc->qfullmsk |= 1 << ring->qid; 4868 4869 DPRINTF(sc, IWN_DEBUG_TRACE, "->%s: end\n",__func__); 4870 4871 return 0; 4872 } 4873 4874 static void 4875 iwn_xmit_task(void *arg0, int pending) 4876 { 4877 struct iwn_softc *sc = arg0; 4878 struct ieee80211_node *ni; 4879 struct mbuf *m; 4880 int error; 4881 struct ieee80211_bpf_params p; 4882 int have_p; 4883 4884 DPRINTF(sc, IWN_DEBUG_XMIT, "%s: called\n", __func__); 4885 4886 IWN_LOCK(sc); 4887 /* 4888 * Dequeue frames, attempt to transmit, 4889 * then disable beaconwait when we're done. 4890 */ 4891 while ((m = mbufq_dequeue(&sc->sc_xmit_queue)) != NULL) { 4892 have_p = 0; 4893 ni = (struct ieee80211_node *)m->m_pkthdr.rcvif; 4894 4895 /* Get xmit params if appropriate */ 4896 if (ieee80211_get_xmit_params(m, &p) == 0) 4897 have_p = 1; 4898 4899 DPRINTF(sc, IWN_DEBUG_XMIT, "%s: m=%p, have_p=%d\n", 4900 __func__, m, have_p); 4901 4902 /* If we have xmit params, use them */ 4903 if (have_p) 4904 error = iwn_tx_data_raw(sc, m, ni, &p); 4905 else 4906 error = iwn_tx_data(sc, m, ni); 4907 4908 if (error != 0) { 4909 if_inc_counter(ni->ni_vap->iv_ifp, 4910 IFCOUNTER_OERRORS, 1); 4911 ieee80211_free_node(ni); 4912 m_freem(m); 4913 } 4914 } 4915 4916 sc->sc_beacon_wait = 0; 4917 IWN_UNLOCK(sc); 4918 } 4919 4920 /* 4921 * raw frame xmit - free node/reference if failed. 4922 */ 4923 static int 4924 iwn_raw_xmit(struct ieee80211_node *ni, struct mbuf *m, 4925 const struct ieee80211_bpf_params *params) 4926 { 4927 struct ieee80211com *ic = ni->ni_ic; 4928 struct iwn_softc *sc = ic->ic_softc; 4929 int error = 0; 4930 4931 DPRINTF(sc, IWN_DEBUG_XMIT | IWN_DEBUG_TRACE, "->%s begin\n", __func__); 4932 4933 IWN_LOCK(sc); 4934 if ((sc->sc_flags & IWN_FLAG_RUNNING) == 0) { 4935 m_freem(m); 4936 IWN_UNLOCK(sc); 4937 return (ENETDOWN); 4938 } 4939 4940 /* queue frame if we have to */ 4941 if (sc->sc_beacon_wait) { 4942 if (iwn_xmit_queue_enqueue(sc, m) != 0) { 4943 m_freem(m); 4944 IWN_UNLOCK(sc); 4945 return (ENOBUFS); 4946 } 4947 /* Queued, so just return OK */ 4948 IWN_UNLOCK(sc); 4949 return (0); 4950 } 4951 4952 if (params == NULL) { 4953 /* 4954 * Legacy path; interpret frame contents to decide 4955 * precisely how to send the frame. 4956 */ 4957 error = iwn_tx_data(sc, m, ni); 4958 } else { 4959 /* 4960 * Caller supplied explicit parameters to use in 4961 * sending the frame. 4962 */ 4963 error = iwn_tx_data_raw(sc, m, ni, params); 4964 } 4965 if (error == 0) 4966 sc->sc_tx_timer = 5; 4967 else 4968 m_freem(m); 4969 4970 IWN_UNLOCK(sc); 4971 4972 DPRINTF(sc, IWN_DEBUG_TRACE | IWN_DEBUG_XMIT, "->%s: end\n",__func__); 4973 4974 return (error); 4975 } 4976 4977 /* 4978 * transmit - don't free mbuf if failed; don't free node ref if failed. 4979 */ 4980 static int 4981 iwn_transmit(struct ieee80211com *ic, struct mbuf *m) 4982 { 4983 struct iwn_softc *sc = ic->ic_softc; 4984 struct ieee80211_node *ni; 4985 int error; 4986 4987 ni = (struct ieee80211_node *)m->m_pkthdr.rcvif; 4988 4989 IWN_LOCK(sc); 4990 if ((sc->sc_flags & IWN_FLAG_RUNNING) == 0 || sc->sc_beacon_wait) { 4991 IWN_UNLOCK(sc); 4992 return (ENXIO); 4993 } 4994 4995 if (sc->qfullmsk) { 4996 IWN_UNLOCK(sc); 4997 return (ENOBUFS); 4998 } 4999 5000 error = iwn_tx_data(sc, m, ni); 5001 if (!error) 5002 sc->sc_tx_timer = 5; 5003 IWN_UNLOCK(sc); 5004 return (error); 5005 } 5006 5007 static void 5008 iwn_scan_timeout(void *arg) 5009 { 5010 struct iwn_softc *sc = arg; 5011 struct ieee80211com *ic = &sc->sc_ic; 5012 5013 ic_printf(ic, "scan timeout\n"); 5014 ieee80211_restart_all(ic); 5015 } 5016 5017 static void 5018 iwn_watchdog(void *arg) 5019 { 5020 struct iwn_softc *sc = arg; 5021 struct ieee80211com *ic = &sc->sc_ic; 5022 5023 IWN_LOCK_ASSERT(sc); 5024 5025 KASSERT(sc->sc_flags & IWN_FLAG_RUNNING, ("not running")); 5026 5027 DPRINTF(sc, IWN_DEBUG_TRACE, "->Doing %s\n", __func__); 5028 5029 if (sc->sc_tx_timer > 0) { 5030 if (--sc->sc_tx_timer == 0) { 5031 ic_printf(ic, "device timeout\n"); 5032 ieee80211_restart_all(ic); 5033 return; 5034 } 5035 } 5036 callout_reset(&sc->watchdog_to, hz, iwn_watchdog, sc); 5037 } 5038 5039 static int 5040 iwn_cdev_open(struct cdev *dev, int flags, int type, struct thread *td) 5041 { 5042 5043 return (0); 5044 } 5045 5046 static int 5047 iwn_cdev_close(struct cdev *dev, int flags, int type, struct thread *td) 5048 { 5049 5050 return (0); 5051 } 5052 5053 static int 5054 iwn_cdev_ioctl(struct cdev *dev, unsigned long cmd, caddr_t data, int fflag, 5055 struct thread *td) 5056 { 5057 int rc; 5058 struct iwn_softc *sc = dev->si_drv1; 5059 struct iwn_ioctl_data *d; 5060 5061 rc = priv_check(td, PRIV_DRIVER); 5062 if (rc != 0) 5063 return (0); 5064 5065 switch (cmd) { 5066 case SIOCGIWNSTATS: 5067 d = (struct iwn_ioctl_data *) data; 5068 IWN_LOCK(sc); 5069 /* XXX validate permissions/memory/etc? */ 5070 rc = copyout(&sc->last_stat, d->dst_addr, sizeof(struct iwn_stats)); 5071 IWN_UNLOCK(sc); 5072 break; 5073 case SIOCZIWNSTATS: 5074 IWN_LOCK(sc); 5075 memset(&sc->last_stat, 0, sizeof(struct iwn_stats)); 5076 IWN_UNLOCK(sc); 5077 break; 5078 default: 5079 rc = EINVAL; 5080 break; 5081 } 5082 return (rc); 5083 } 5084 5085 static int 5086 iwn_ioctl(struct ieee80211com *ic, u_long cmd, void *data) 5087 { 5088 5089 return (ENOTTY); 5090 } 5091 5092 static void 5093 iwn_parent(struct ieee80211com *ic) 5094 { 5095 struct iwn_softc *sc = ic->ic_softc; 5096 struct ieee80211vap *vap; 5097 int error; 5098 5099 if (ic->ic_nrunning > 0) { 5100 error = iwn_init(sc); 5101 5102 switch (error) { 5103 case 0: 5104 ieee80211_start_all(ic); 5105 break; 5106 case EAGAIN: 5107 /* radio is disabled via RFkill switch */ 5108 taskqueue_enqueue(sc->sc_tq, &sc->sc_rftoggle_task); 5109 break; 5110 default: 5111 vap = TAILQ_FIRST(&ic->ic_vaps); 5112 if (vap != NULL) 5113 ieee80211_stop(vap); 5114 break; 5115 } 5116 } else 5117 iwn_stop(sc); 5118 } 5119 5120 /* 5121 * Send a command to the firmware. 5122 */ 5123 static int 5124 iwn_cmd(struct iwn_softc *sc, int code, const void *buf, int size, int async) 5125 { 5126 struct iwn_tx_ring *ring; 5127 struct iwn_tx_desc *desc; 5128 struct iwn_tx_data *data; 5129 struct iwn_tx_cmd *cmd; 5130 struct mbuf *m; 5131 bus_addr_t paddr; 5132 int totlen, error; 5133 int cmd_queue_num; 5134 5135 DPRINTF(sc, IWN_DEBUG_TRACE, "->%s begin\n", __func__); 5136 5137 if (async == 0) 5138 IWN_LOCK_ASSERT(sc); 5139 5140 if (sc->sc_flags & IWN_FLAG_PAN_SUPPORT) 5141 cmd_queue_num = IWN_PAN_CMD_QUEUE; 5142 else 5143 cmd_queue_num = IWN_CMD_QUEUE_NUM; 5144 5145 ring = &sc->txq[cmd_queue_num]; 5146 desc = &ring->desc[ring->cur]; 5147 data = &ring->data[ring->cur]; 5148 totlen = 4 + size; 5149 5150 if (size > sizeof cmd->data) { 5151 /* Command is too large to fit in a descriptor. */ 5152 if (totlen > MCLBYTES) 5153 return EINVAL; 5154 m = m_getjcl(M_NOWAIT, MT_DATA, M_PKTHDR, MJUMPAGESIZE); 5155 if (m == NULL) 5156 return ENOMEM; 5157 cmd = mtod(m, struct iwn_tx_cmd *); 5158 error = bus_dmamap_load(ring->data_dmat, data->map, cmd, 5159 totlen, iwn_dma_map_addr, &paddr, BUS_DMA_NOWAIT); 5160 if (error != 0) { 5161 m_freem(m); 5162 return error; 5163 } 5164 data->m = m; 5165 } else { 5166 cmd = &ring->cmd[ring->cur]; 5167 paddr = data->cmd_paddr; 5168 } 5169 5170 cmd->code = code; 5171 cmd->flags = 0; 5172 cmd->qid = ring->qid; 5173 cmd->idx = ring->cur; 5174 memcpy(cmd->data, buf, size); 5175 5176 desc->nsegs = 1; 5177 desc->segs[0].addr = htole32(IWN_LOADDR(paddr)); 5178 desc->segs[0].len = htole16(IWN_HIADDR(paddr) | totlen << 4); 5179 5180 DPRINTF(sc, IWN_DEBUG_CMD, "%s: %s (0x%x) flags %d qid %d idx %d\n", 5181 __func__, iwn_intr_str(cmd->code), cmd->code, 5182 cmd->flags, cmd->qid, cmd->idx); 5183 5184 if (size > sizeof cmd->data) { 5185 bus_dmamap_sync(ring->data_dmat, data->map, 5186 BUS_DMASYNC_PREWRITE); 5187 } else { 5188 bus_dmamap_sync(ring->cmd_dma.tag, ring->cmd_dma.map, 5189 BUS_DMASYNC_PREWRITE); 5190 } 5191 bus_dmamap_sync(ring->desc_dma.tag, ring->desc_dma.map, 5192 BUS_DMASYNC_PREWRITE); 5193 5194 /* Kick command ring. */ 5195 ring->cur = (ring->cur + 1) % IWN_TX_RING_COUNT; 5196 IWN_WRITE(sc, IWN_HBUS_TARG_WRPTR, ring->qid << 8 | ring->cur); 5197 5198 DPRINTF(sc, IWN_DEBUG_TRACE, "->%s: end\n",__func__); 5199 5200 return async ? 0 : msleep(desc, &sc->sc_mtx, PCATCH, "iwncmd", hz); 5201 } 5202 5203 static int 5204 iwn4965_add_node(struct iwn_softc *sc, struct iwn_node_info *node, int async) 5205 { 5206 struct iwn4965_node_info hnode; 5207 caddr_t src, dst; 5208 5209 DPRINTF(sc, IWN_DEBUG_TRACE, "->Doing %s\n", __func__); 5210 5211 /* 5212 * We use the node structure for 5000 Series internally (it is 5213 * a superset of the one for 4965AGN). We thus copy the common 5214 * fields before sending the command. 5215 */ 5216 src = (caddr_t)node; 5217 dst = (caddr_t)&hnode; 5218 memcpy(dst, src, 48); 5219 /* Skip TSC, RX MIC and TX MIC fields from ``src''. */ 5220 memcpy(dst + 48, src + 72, 20); 5221 return iwn_cmd(sc, IWN_CMD_ADD_NODE, &hnode, sizeof hnode, async); 5222 } 5223 5224 static int 5225 iwn5000_add_node(struct iwn_softc *sc, struct iwn_node_info *node, int async) 5226 { 5227 5228 DPRINTF(sc, IWN_DEBUG_TRACE, "->Doing %s\n", __func__); 5229 5230 /* Direct mapping. */ 5231 return iwn_cmd(sc, IWN_CMD_ADD_NODE, node, sizeof (*node), async); 5232 } 5233 5234 static int 5235 iwn_set_link_quality(struct iwn_softc *sc, struct ieee80211_node *ni) 5236 { 5237 struct iwn_node *wn = (void *)ni; 5238 struct ieee80211_rateset *rs; 5239 struct iwn_cmd_link_quality linkq; 5240 int i, rate, txrate; 5241 int is_11n; 5242 5243 DPRINTF(sc, IWN_DEBUG_TRACE, "->%s begin\n", __func__); 5244 5245 memset(&linkq, 0, sizeof linkq); 5246 linkq.id = wn->id; 5247 linkq.antmsk_1stream = iwn_get_1stream_tx_antmask(sc); 5248 linkq.antmsk_2stream = iwn_get_2stream_tx_antmask(sc); 5249 5250 linkq.ampdu_max = 32; /* XXX negotiated? */ 5251 linkq.ampdu_threshold = 3; 5252 linkq.ampdu_limit = htole16(4000); /* 4ms */ 5253 5254 DPRINTF(sc, IWN_DEBUG_XMIT, 5255 "%s: 1stream antenna=0x%02x, 2stream antenna=0x%02x, ntxstreams=%d\n", 5256 __func__, 5257 linkq.antmsk_1stream, 5258 linkq.antmsk_2stream, 5259 sc->ntxchains); 5260 5261 /* 5262 * Are we using 11n rates? Ensure the channel is 5263 * 11n _and_ we have some 11n rates, or don't 5264 * try. 5265 */ 5266 if (IEEE80211_IS_CHAN_HT(ni->ni_chan) && ni->ni_htrates.rs_nrates > 0) { 5267 rs = (struct ieee80211_rateset *) &ni->ni_htrates; 5268 is_11n = 1; 5269 } else { 5270 rs = &ni->ni_rates; 5271 is_11n = 0; 5272 } 5273 5274 /* Start at highest available bit-rate. */ 5275 /* 5276 * XXX this is all very dirty! 5277 */ 5278 if (is_11n) 5279 txrate = ni->ni_htrates.rs_nrates - 1; 5280 else 5281 txrate = rs->rs_nrates - 1; 5282 for (i = 0; i < IWN_MAX_TX_RETRIES; i++) { 5283 uint32_t plcp; 5284 5285 /* 5286 * XXX TODO: ensure the last two slots are the two lowest 5287 * rate entries, just for now. 5288 */ 5289 if (i == 14 || i == 15) 5290 txrate = 0; 5291 5292 if (is_11n) 5293 rate = IEEE80211_RATE_MCS | rs->rs_rates[txrate]; 5294 else 5295 rate = IEEE80211_RV(rs->rs_rates[txrate]); 5296 5297 /* Do rate -> PLCP config mapping */ 5298 plcp = iwn_rate_to_plcp(sc, ni, rate); 5299 linkq.retry[i] = plcp; 5300 DPRINTF(sc, IWN_DEBUG_XMIT, 5301 "%s: i=%d, txrate=%d, rate=0x%02x, plcp=0x%08x\n", 5302 __func__, 5303 i, 5304 txrate, 5305 rate, 5306 le32toh(plcp)); 5307 5308 /* 5309 * The mimo field is an index into the table which 5310 * indicates the first index where it and subsequent entries 5311 * will not be using MIMO. 5312 * 5313 * Since we're filling linkq from 0..15 and we're filling 5314 * from the highest MCS rates to the lowest rates, if we 5315 * _are_ doing a dual-stream rate, set mimo to idx+1 (ie, 5316 * the next entry.) That way if the next entry is a non-MIMO 5317 * entry, we're already pointing at it. 5318 */ 5319 if ((le32toh(plcp) & IWN_RFLAG_MCS) && 5320 IEEE80211_RV(le32toh(plcp)) > 7) 5321 linkq.mimo = i + 1; 5322 5323 /* Next retry at immediate lower bit-rate. */ 5324 if (txrate > 0) 5325 txrate--; 5326 } 5327 /* 5328 * If we reached the end of the list and indeed we hit 5329 * all MIMO rates (eg 5300 doing MCS23-15) then yes, 5330 * set mimo to 15. Setting it to 16 panics the firmware. 5331 */ 5332 if (linkq.mimo > 15) 5333 linkq.mimo = 15; 5334 5335 DPRINTF(sc, IWN_DEBUG_XMIT, "%s: mimo = %d\n", __func__, linkq.mimo); 5336 5337 DPRINTF(sc, IWN_DEBUG_TRACE, "->%s: end\n",__func__); 5338 5339 return iwn_cmd(sc, IWN_CMD_LINK_QUALITY, &linkq, sizeof linkq, 1); 5340 } 5341 5342 /* 5343 * Broadcast node is used to send group-addressed and management frames. 5344 */ 5345 static int 5346 iwn_add_broadcast_node(struct iwn_softc *sc, int async) 5347 { 5348 struct iwn_ops *ops = &sc->ops; 5349 struct ieee80211com *ic = &sc->sc_ic; 5350 struct iwn_node_info node; 5351 struct iwn_cmd_link_quality linkq; 5352 uint8_t txant; 5353 int i, error; 5354 5355 DPRINTF(sc, IWN_DEBUG_TRACE, "->%s begin\n", __func__); 5356 5357 sc->rxon = &sc->rx_on[IWN_RXON_BSS_CTX]; 5358 5359 memset(&node, 0, sizeof node); 5360 IEEE80211_ADDR_COPY(node.macaddr, ieee80211broadcastaddr); 5361 node.id = sc->broadcast_id; 5362 DPRINTF(sc, IWN_DEBUG_RESET, "%s: adding broadcast node\n", __func__); 5363 if ((error = ops->add_node(sc, &node, async)) != 0) 5364 return error; 5365 5366 /* Use the first valid TX antenna. */ 5367 txant = IWN_LSB(sc->txchainmask); 5368 5369 memset(&linkq, 0, sizeof linkq); 5370 linkq.id = sc->broadcast_id; 5371 linkq.antmsk_1stream = iwn_get_1stream_tx_antmask(sc); 5372 linkq.antmsk_2stream = iwn_get_2stream_tx_antmask(sc); 5373 linkq.ampdu_max = 64; 5374 linkq.ampdu_threshold = 3; 5375 linkq.ampdu_limit = htole16(4000); /* 4ms */ 5376 5377 /* Use lowest mandatory bit-rate. */ 5378 /* XXX rate table lookup? */ 5379 if (IEEE80211_IS_CHAN_5GHZ(ic->ic_curchan)) 5380 linkq.retry[0] = htole32(0xd); 5381 else 5382 linkq.retry[0] = htole32(10 | IWN_RFLAG_CCK); 5383 linkq.retry[0] |= htole32(IWN_RFLAG_ANT(txant)); 5384 /* Use same bit-rate for all TX retries. */ 5385 for (i = 1; i < IWN_MAX_TX_RETRIES; i++) { 5386 linkq.retry[i] = linkq.retry[0]; 5387 } 5388 5389 DPRINTF(sc, IWN_DEBUG_TRACE, "->%s: end\n",__func__); 5390 5391 return iwn_cmd(sc, IWN_CMD_LINK_QUALITY, &linkq, sizeof linkq, async); 5392 } 5393 5394 static int 5395 iwn_updateedca(struct ieee80211com *ic) 5396 { 5397 #define IWN_EXP2(x) ((1 << (x)) - 1) /* CWmin = 2^ECWmin - 1 */ 5398 struct iwn_softc *sc = ic->ic_softc; 5399 struct iwn_edca_params cmd; 5400 int aci; 5401 5402 DPRINTF(sc, IWN_DEBUG_TRACE, "->%s begin\n", __func__); 5403 5404 memset(&cmd, 0, sizeof cmd); 5405 cmd.flags = htole32(IWN_EDCA_UPDATE); 5406 5407 IEEE80211_LOCK(ic); 5408 for (aci = 0; aci < WME_NUM_AC; aci++) { 5409 const struct wmeParams *ac = 5410 &ic->ic_wme.wme_chanParams.cap_wmeParams[aci]; 5411 cmd.ac[aci].aifsn = ac->wmep_aifsn; 5412 cmd.ac[aci].cwmin = htole16(IWN_EXP2(ac->wmep_logcwmin)); 5413 cmd.ac[aci].cwmax = htole16(IWN_EXP2(ac->wmep_logcwmax)); 5414 cmd.ac[aci].txoplimit = 5415 htole16(IEEE80211_TXOP_TO_US(ac->wmep_txopLimit)); 5416 } 5417 IEEE80211_UNLOCK(ic); 5418 5419 IWN_LOCK(sc); 5420 (void)iwn_cmd(sc, IWN_CMD_EDCA_PARAMS, &cmd, sizeof cmd, 1); 5421 IWN_UNLOCK(sc); 5422 5423 DPRINTF(sc, IWN_DEBUG_TRACE, "->%s: end\n",__func__); 5424 5425 return 0; 5426 #undef IWN_EXP2 5427 } 5428 5429 static void 5430 iwn_update_mcast(struct ieee80211com *ic) 5431 { 5432 /* Ignore */ 5433 } 5434 5435 static void 5436 iwn_set_led(struct iwn_softc *sc, uint8_t which, uint8_t off, uint8_t on) 5437 { 5438 struct iwn_cmd_led led; 5439 5440 DPRINTF(sc, IWN_DEBUG_TRACE, "->Doing %s\n", __func__); 5441 5442 #if 0 5443 /* XXX don't set LEDs during scan? */ 5444 if (sc->sc_is_scanning) 5445 return; 5446 #endif 5447 5448 /* Clear microcode LED ownership. */ 5449 IWN_CLRBITS(sc, IWN_LED, IWN_LED_BSM_CTRL); 5450 5451 led.which = which; 5452 led.unit = htole32(10000); /* on/off in unit of 100ms */ 5453 led.off = off; 5454 led.on = on; 5455 (void)iwn_cmd(sc, IWN_CMD_SET_LED, &led, sizeof led, 1); 5456 } 5457 5458 /* 5459 * Set the critical temperature at which the firmware will stop the radio 5460 * and notify us. 5461 */ 5462 static int 5463 iwn_set_critical_temp(struct iwn_softc *sc) 5464 { 5465 struct iwn_critical_temp crit; 5466 int32_t temp; 5467 5468 DPRINTF(sc, IWN_DEBUG_TRACE, "->Doing %s\n", __func__); 5469 5470 IWN_WRITE(sc, IWN_UCODE_GP1_CLR, IWN_UCODE_GP1_CTEMP_STOP_RF); 5471 5472 if (sc->hw_type == IWN_HW_REV_TYPE_5150) 5473 temp = (IWN_CTOK(110) - sc->temp_off) * -5; 5474 else if (sc->hw_type == IWN_HW_REV_TYPE_4965) 5475 temp = IWN_CTOK(110); 5476 else 5477 temp = 110; 5478 memset(&crit, 0, sizeof crit); 5479 crit.tempR = htole32(temp); 5480 DPRINTF(sc, IWN_DEBUG_RESET, "setting critical temp to %d\n", temp); 5481 return iwn_cmd(sc, IWN_CMD_SET_CRITICAL_TEMP, &crit, sizeof crit, 0); 5482 } 5483 5484 static int 5485 iwn_set_timing(struct iwn_softc *sc, struct ieee80211_node *ni) 5486 { 5487 struct iwn_cmd_timing cmd; 5488 uint64_t val, mod; 5489 5490 DPRINTF(sc, IWN_DEBUG_TRACE, "->Doing %s\n", __func__); 5491 5492 memset(&cmd, 0, sizeof cmd); 5493 memcpy(&cmd.tstamp, ni->ni_tstamp.data, sizeof (uint64_t)); 5494 cmd.bintval = htole16(ni->ni_intval); 5495 cmd.lintval = htole16(10); 5496 5497 /* Compute remaining time until next beacon. */ 5498 val = (uint64_t)ni->ni_intval * IEEE80211_DUR_TU; 5499 mod = le64toh(cmd.tstamp) % val; 5500 cmd.binitval = htole32((uint32_t)(val - mod)); 5501 5502 DPRINTF(sc, IWN_DEBUG_RESET, "timing bintval=%u tstamp=%ju, init=%u\n", 5503 ni->ni_intval, le64toh(cmd.tstamp), (uint32_t)(val - mod)); 5504 5505 return iwn_cmd(sc, IWN_CMD_TIMING, &cmd, sizeof cmd, 1); 5506 } 5507 5508 static void 5509 iwn4965_power_calibration(struct iwn_softc *sc, int temp) 5510 { 5511 5512 DPRINTF(sc, IWN_DEBUG_TRACE, "->Doing %s\n", __func__); 5513 5514 /* Adjust TX power if need be (delta >= 3 degC). */ 5515 DPRINTF(sc, IWN_DEBUG_CALIBRATE, "%s: temperature %d->%d\n", 5516 __func__, sc->temp, temp); 5517 if (abs(temp - sc->temp) >= 3) { 5518 /* Record temperature of last calibration. */ 5519 sc->temp = temp; 5520 (void)iwn4965_set_txpower(sc, 1); 5521 } 5522 } 5523 5524 /* 5525 * Set TX power for current channel (each rate has its own power settings). 5526 * This function takes into account the regulatory information from EEPROM, 5527 * the current temperature and the current voltage. 5528 */ 5529 static int 5530 iwn4965_set_txpower(struct iwn_softc *sc, int async) 5531 { 5532 /* Fixed-point arithmetic division using a n-bit fractional part. */ 5533 #define fdivround(a, b, n) \ 5534 ((((1 << n) * (a)) / (b) + (1 << n) / 2) / (1 << n)) 5535 /* Linear interpolation. */ 5536 #define interpolate(x, x1, y1, x2, y2, n) \ 5537 ((y1) + fdivround(((int)(x) - (x1)) * ((y2) - (y1)), (x2) - (x1), n)) 5538 5539 static const int tdiv[IWN_NATTEN_GROUPS] = { 9, 8, 8, 8, 6 }; 5540 struct iwn_ucode_info *uc = &sc->ucode_info; 5541 struct iwn4965_cmd_txpower cmd; 5542 struct iwn4965_eeprom_chan_samples *chans; 5543 const uint8_t *rf_gain, *dsp_gain; 5544 int32_t vdiff, tdiff; 5545 int i, is_chan_5ghz, c, grp, maxpwr; 5546 uint8_t chan; 5547 5548 sc->rxon = &sc->rx_on[IWN_RXON_BSS_CTX]; 5549 /* Retrieve current channel from last RXON. */ 5550 chan = sc->rxon->chan; 5551 is_chan_5ghz = (sc->rxon->flags & htole32(IWN_RXON_24GHZ)) == 0; 5552 DPRINTF(sc, IWN_DEBUG_RESET, "setting TX power for channel %d\n", 5553 chan); 5554 5555 memset(&cmd, 0, sizeof cmd); 5556 cmd.band = is_chan_5ghz ? 0 : 1; 5557 cmd.chan = chan; 5558 5559 if (is_chan_5ghz) { 5560 maxpwr = sc->maxpwr5GHz; 5561 rf_gain = iwn4965_rf_gain_5ghz; 5562 dsp_gain = iwn4965_dsp_gain_5ghz; 5563 } else { 5564 maxpwr = sc->maxpwr2GHz; 5565 rf_gain = iwn4965_rf_gain_2ghz; 5566 dsp_gain = iwn4965_dsp_gain_2ghz; 5567 } 5568 5569 /* Compute voltage compensation. */ 5570 vdiff = ((int32_t)le32toh(uc->volt) - sc->eeprom_voltage) / 7; 5571 if (vdiff > 0) 5572 vdiff *= 2; 5573 if (abs(vdiff) > 2) 5574 vdiff = 0; 5575 DPRINTF(sc, IWN_DEBUG_CALIBRATE | IWN_DEBUG_TXPOW, 5576 "%s: voltage compensation=%d (UCODE=%d, EEPROM=%d)\n", 5577 __func__, vdiff, le32toh(uc->volt), sc->eeprom_voltage); 5578 5579 /* Get channel attenuation group. */ 5580 if (chan <= 20) /* 1-20 */ 5581 grp = 4; 5582 else if (chan <= 43) /* 34-43 */ 5583 grp = 0; 5584 else if (chan <= 70) /* 44-70 */ 5585 grp = 1; 5586 else if (chan <= 124) /* 71-124 */ 5587 grp = 2; 5588 else /* 125-200 */ 5589 grp = 3; 5590 DPRINTF(sc, IWN_DEBUG_CALIBRATE | IWN_DEBUG_TXPOW, 5591 "%s: chan %d, attenuation group=%d\n", __func__, chan, grp); 5592 5593 /* Get channel sub-band. */ 5594 for (i = 0; i < IWN_NBANDS; i++) 5595 if (sc->bands[i].lo != 0 && 5596 sc->bands[i].lo <= chan && chan <= sc->bands[i].hi) 5597 break; 5598 if (i == IWN_NBANDS) /* Can't happen in real-life. */ 5599 return EINVAL; 5600 chans = sc->bands[i].chans; 5601 DPRINTF(sc, IWN_DEBUG_CALIBRATE | IWN_DEBUG_TXPOW, 5602 "%s: chan %d sub-band=%d\n", __func__, chan, i); 5603 5604 for (c = 0; c < 2; c++) { 5605 uint8_t power, gain, temp; 5606 int maxchpwr, pwr, ridx, idx; 5607 5608 power = interpolate(chan, 5609 chans[0].num, chans[0].samples[c][1].power, 5610 chans[1].num, chans[1].samples[c][1].power, 1); 5611 gain = interpolate(chan, 5612 chans[0].num, chans[0].samples[c][1].gain, 5613 chans[1].num, chans[1].samples[c][1].gain, 1); 5614 temp = interpolate(chan, 5615 chans[0].num, chans[0].samples[c][1].temp, 5616 chans[1].num, chans[1].samples[c][1].temp, 1); 5617 DPRINTF(sc, IWN_DEBUG_CALIBRATE | IWN_DEBUG_TXPOW, 5618 "%s: Tx chain %d: power=%d gain=%d temp=%d\n", 5619 __func__, c, power, gain, temp); 5620 5621 /* Compute temperature compensation. */ 5622 tdiff = ((sc->temp - temp) * 2) / tdiv[grp]; 5623 DPRINTF(sc, IWN_DEBUG_CALIBRATE | IWN_DEBUG_TXPOW, 5624 "%s: temperature compensation=%d (current=%d, EEPROM=%d)\n", 5625 __func__, tdiff, sc->temp, temp); 5626 5627 for (ridx = 0; ridx <= IWN_RIDX_MAX; ridx++) { 5628 /* Convert dBm to half-dBm. */ 5629 maxchpwr = sc->maxpwr[chan] * 2; 5630 if ((ridx / 8) & 1) 5631 maxchpwr -= 6; /* MIMO 2T: -3dB */ 5632 5633 pwr = maxpwr; 5634 5635 /* Adjust TX power based on rate. */ 5636 if ((ridx % 8) == 5) 5637 pwr -= 15; /* OFDM48: -7.5dB */ 5638 else if ((ridx % 8) == 6) 5639 pwr -= 17; /* OFDM54: -8.5dB */ 5640 else if ((ridx % 8) == 7) 5641 pwr -= 20; /* OFDM60: -10dB */ 5642 else 5643 pwr -= 10; /* Others: -5dB */ 5644 5645 /* Do not exceed channel max TX power. */ 5646 if (pwr > maxchpwr) 5647 pwr = maxchpwr; 5648 5649 idx = gain - (pwr - power) - tdiff - vdiff; 5650 if ((ridx / 8) & 1) /* MIMO */ 5651 idx += (int32_t)le32toh(uc->atten[grp][c]); 5652 5653 if (cmd.band == 0) 5654 idx += 9; /* 5GHz */ 5655 if (ridx == IWN_RIDX_MAX) 5656 idx += 5; /* CCK */ 5657 5658 /* Make sure idx stays in a valid range. */ 5659 if (idx < 0) 5660 idx = 0; 5661 else if (idx > IWN4965_MAX_PWR_INDEX) 5662 idx = IWN4965_MAX_PWR_INDEX; 5663 5664 DPRINTF(sc, IWN_DEBUG_CALIBRATE | IWN_DEBUG_TXPOW, 5665 "%s: Tx chain %d, rate idx %d: power=%d\n", 5666 __func__, c, ridx, idx); 5667 cmd.power[ridx].rf_gain[c] = rf_gain[idx]; 5668 cmd.power[ridx].dsp_gain[c] = dsp_gain[idx]; 5669 } 5670 } 5671 5672 DPRINTF(sc, IWN_DEBUG_CALIBRATE | IWN_DEBUG_TXPOW, 5673 "%s: set tx power for chan %d\n", __func__, chan); 5674 return iwn_cmd(sc, IWN_CMD_TXPOWER, &cmd, sizeof cmd, async); 5675 5676 #undef interpolate 5677 #undef fdivround 5678 } 5679 5680 static int 5681 iwn5000_set_txpower(struct iwn_softc *sc, int async) 5682 { 5683 struct iwn5000_cmd_txpower cmd; 5684 int cmdid; 5685 5686 DPRINTF(sc, IWN_DEBUG_TRACE, "->Doing %s\n", __func__); 5687 5688 /* 5689 * TX power calibration is handled automatically by the firmware 5690 * for 5000 Series. 5691 */ 5692 memset(&cmd, 0, sizeof cmd); 5693 cmd.global_limit = 2 * IWN5000_TXPOWER_MAX_DBM; /* 16 dBm */ 5694 cmd.flags = IWN5000_TXPOWER_NO_CLOSED; 5695 cmd.srv_limit = IWN5000_TXPOWER_AUTO; 5696 DPRINTF(sc, IWN_DEBUG_CALIBRATE | IWN_DEBUG_XMIT, 5697 "%s: setting TX power; rev=%d\n", 5698 __func__, 5699 IWN_UCODE_API(sc->ucode_rev)); 5700 if (IWN_UCODE_API(sc->ucode_rev) == 1) 5701 cmdid = IWN_CMD_TXPOWER_DBM_V1; 5702 else 5703 cmdid = IWN_CMD_TXPOWER_DBM; 5704 return iwn_cmd(sc, cmdid, &cmd, sizeof cmd, async); 5705 } 5706 5707 /* 5708 * Retrieve the maximum RSSI (in dBm) among receivers. 5709 */ 5710 static int 5711 iwn4965_get_rssi(struct iwn_softc *sc, struct iwn_rx_stat *stat) 5712 { 5713 struct iwn4965_rx_phystat *phy = (void *)stat->phybuf; 5714 uint8_t mask, agc; 5715 int rssi; 5716 5717 DPRINTF(sc, IWN_DEBUG_TRACE, "->Doing %s\n", __func__); 5718 5719 mask = (le16toh(phy->antenna) >> 4) & IWN_ANT_ABC; 5720 agc = (le16toh(phy->agc) >> 7) & 0x7f; 5721 5722 rssi = 0; 5723 if (mask & IWN_ANT_A) 5724 rssi = MAX(rssi, phy->rssi[0]); 5725 if (mask & IWN_ANT_B) 5726 rssi = MAX(rssi, phy->rssi[2]); 5727 if (mask & IWN_ANT_C) 5728 rssi = MAX(rssi, phy->rssi[4]); 5729 5730 DPRINTF(sc, IWN_DEBUG_RECV, 5731 "%s: agc %d mask 0x%x rssi %d %d %d result %d\n", __func__, agc, 5732 mask, phy->rssi[0], phy->rssi[2], phy->rssi[4], 5733 rssi - agc - IWN_RSSI_TO_DBM); 5734 return rssi - agc - IWN_RSSI_TO_DBM; 5735 } 5736 5737 static int 5738 iwn5000_get_rssi(struct iwn_softc *sc, struct iwn_rx_stat *stat) 5739 { 5740 struct iwn5000_rx_phystat *phy = (void *)stat->phybuf; 5741 uint8_t agc; 5742 int rssi; 5743 5744 DPRINTF(sc, IWN_DEBUG_TRACE, "->Doing %s\n", __func__); 5745 5746 agc = (le32toh(phy->agc) >> 9) & 0x7f; 5747 5748 rssi = MAX(le16toh(phy->rssi[0]) & 0xff, 5749 le16toh(phy->rssi[1]) & 0xff); 5750 rssi = MAX(le16toh(phy->rssi[2]) & 0xff, rssi); 5751 5752 DPRINTF(sc, IWN_DEBUG_RECV, 5753 "%s: agc %d rssi %d %d %d result %d\n", __func__, agc, 5754 phy->rssi[0], phy->rssi[1], phy->rssi[2], 5755 rssi - agc - IWN_RSSI_TO_DBM); 5756 return rssi - agc - IWN_RSSI_TO_DBM; 5757 } 5758 5759 /* 5760 * Retrieve the average noise (in dBm) among receivers. 5761 */ 5762 static int 5763 iwn_get_noise(const struct iwn_rx_general_stats *stats) 5764 { 5765 int i, total, nbant, noise; 5766 5767 total = nbant = 0; 5768 for (i = 0; i < 3; i++) { 5769 if ((noise = le32toh(stats->noise[i]) & 0xff) == 0) 5770 continue; 5771 total += noise; 5772 nbant++; 5773 } 5774 /* There should be at least one antenna but check anyway. */ 5775 return (nbant == 0) ? -127 : (total / nbant) - 107; 5776 } 5777 5778 /* 5779 * Compute temperature (in degC) from last received statistics. 5780 */ 5781 static int 5782 iwn4965_get_temperature(struct iwn_softc *sc) 5783 { 5784 struct iwn_ucode_info *uc = &sc->ucode_info; 5785 int32_t r1, r2, r3, r4, temp; 5786 5787 DPRINTF(sc, IWN_DEBUG_TRACE, "->Doing %s\n", __func__); 5788 5789 r1 = le32toh(uc->temp[0].chan20MHz); 5790 r2 = le32toh(uc->temp[1].chan20MHz); 5791 r3 = le32toh(uc->temp[2].chan20MHz); 5792 r4 = le32toh(sc->rawtemp); 5793 5794 if (r1 == r3) /* Prevents division by 0 (should not happen). */ 5795 return 0; 5796 5797 /* Sign-extend 23-bit R4 value to 32-bit. */ 5798 r4 = ((r4 & 0xffffff) ^ 0x800000) - 0x800000; 5799 /* Compute temperature in Kelvin. */ 5800 temp = (259 * (r4 - r2)) / (r3 - r1); 5801 temp = (temp * 97) / 100 + 8; 5802 5803 DPRINTF(sc, IWN_DEBUG_ANY, "temperature %dK/%dC\n", temp, 5804 IWN_KTOC(temp)); 5805 return IWN_KTOC(temp); 5806 } 5807 5808 static int 5809 iwn5000_get_temperature(struct iwn_softc *sc) 5810 { 5811 int32_t temp; 5812 5813 DPRINTF(sc, IWN_DEBUG_TRACE, "->Doing %s\n", __func__); 5814 5815 /* 5816 * Temperature is not used by the driver for 5000 Series because 5817 * TX power calibration is handled by firmware. 5818 */ 5819 temp = le32toh(sc->rawtemp); 5820 if (sc->hw_type == IWN_HW_REV_TYPE_5150) { 5821 temp = (temp / -5) + sc->temp_off; 5822 temp = IWN_KTOC(temp); 5823 } 5824 return temp; 5825 } 5826 5827 /* 5828 * Initialize sensitivity calibration state machine. 5829 */ 5830 static int 5831 iwn_init_sensitivity(struct iwn_softc *sc) 5832 { 5833 struct iwn_ops *ops = &sc->ops; 5834 struct iwn_calib_state *calib = &sc->calib; 5835 uint32_t flags; 5836 int error; 5837 5838 DPRINTF(sc, IWN_DEBUG_TRACE, "->Doing %s\n", __func__); 5839 5840 /* Reset calibration state machine. */ 5841 memset(calib, 0, sizeof (*calib)); 5842 calib->state = IWN_CALIB_STATE_INIT; 5843 calib->cck_state = IWN_CCK_STATE_HIFA; 5844 /* Set initial correlation values. */ 5845 calib->ofdm_x1 = sc->limits->min_ofdm_x1; 5846 calib->ofdm_mrc_x1 = sc->limits->min_ofdm_mrc_x1; 5847 calib->ofdm_x4 = sc->limits->min_ofdm_x4; 5848 calib->ofdm_mrc_x4 = sc->limits->min_ofdm_mrc_x4; 5849 calib->cck_x4 = 125; 5850 calib->cck_mrc_x4 = sc->limits->min_cck_mrc_x4; 5851 calib->energy_cck = sc->limits->energy_cck; 5852 5853 /* Write initial sensitivity. */ 5854 if ((error = iwn_send_sensitivity(sc)) != 0) 5855 return error; 5856 5857 /* Write initial gains. */ 5858 if ((error = ops->init_gains(sc)) != 0) 5859 return error; 5860 5861 /* Request statistics at each beacon interval. */ 5862 flags = 0; 5863 DPRINTF(sc, IWN_DEBUG_CALIBRATE, "%s: sending request for statistics\n", 5864 __func__); 5865 return iwn_cmd(sc, IWN_CMD_GET_STATISTICS, &flags, sizeof flags, 1); 5866 } 5867 5868 /* 5869 * Collect noise and RSSI statistics for the first 20 beacons received 5870 * after association and use them to determine connected antennas and 5871 * to set differential gains. 5872 */ 5873 static void 5874 iwn_collect_noise(struct iwn_softc *sc, 5875 const struct iwn_rx_general_stats *stats) 5876 { 5877 struct iwn_ops *ops = &sc->ops; 5878 struct iwn_calib_state *calib = &sc->calib; 5879 struct ieee80211com *ic = &sc->sc_ic; 5880 uint32_t val; 5881 int i; 5882 5883 DPRINTF(sc, IWN_DEBUG_TRACE, "->%s begin\n", __func__); 5884 5885 /* Accumulate RSSI and noise for all 3 antennas. */ 5886 for (i = 0; i < 3; i++) { 5887 calib->rssi[i] += le32toh(stats->rssi[i]) & 0xff; 5888 calib->noise[i] += le32toh(stats->noise[i]) & 0xff; 5889 } 5890 /* NB: We update differential gains only once after 20 beacons. */ 5891 if (++calib->nbeacons < 20) 5892 return; 5893 5894 /* Determine highest average RSSI. */ 5895 val = MAX(calib->rssi[0], calib->rssi[1]); 5896 val = MAX(calib->rssi[2], val); 5897 5898 /* Determine which antennas are connected. */ 5899 sc->chainmask = sc->rxchainmask; 5900 for (i = 0; i < 3; i++) 5901 if (val - calib->rssi[i] > 15 * 20) 5902 sc->chainmask &= ~(1 << i); 5903 DPRINTF(sc, IWN_DEBUG_CALIBRATE | IWN_DEBUG_XMIT, 5904 "%s: RX chains mask: theoretical=0x%x, actual=0x%x\n", 5905 __func__, sc->rxchainmask, sc->chainmask); 5906 5907 /* If none of the TX antennas are connected, keep at least one. */ 5908 if ((sc->chainmask & sc->txchainmask) == 0) 5909 sc->chainmask |= IWN_LSB(sc->txchainmask); 5910 5911 (void)ops->set_gains(sc); 5912 calib->state = IWN_CALIB_STATE_RUN; 5913 5914 #ifdef notyet 5915 /* XXX Disable RX chains with no antennas connected. */ 5916 sc->rxon->rxchain = htole16(IWN_RXCHAIN_SEL(sc->chainmask)); 5917 if (sc->sc_is_scanning) 5918 device_printf(sc->sc_dev, 5919 "%s: is_scanning set, before RXON\n", 5920 __func__); 5921 (void)iwn_cmd(sc, IWN_CMD_RXON, sc->rxon, sc->rxonsz, 1); 5922 #endif 5923 5924 /* Enable power-saving mode if requested by user. */ 5925 if (ic->ic_flags & IEEE80211_F_PMGTON) 5926 (void)iwn_set_pslevel(sc, 0, 3, 1); 5927 5928 DPRINTF(sc, IWN_DEBUG_TRACE, "->%s: end\n",__func__); 5929 5930 } 5931 5932 static int 5933 iwn4965_init_gains(struct iwn_softc *sc) 5934 { 5935 struct iwn_phy_calib_gain cmd; 5936 5937 DPRINTF(sc, IWN_DEBUG_TRACE, "->Doing %s\n", __func__); 5938 5939 memset(&cmd, 0, sizeof cmd); 5940 cmd.code = IWN4965_PHY_CALIB_DIFF_GAIN; 5941 /* Differential gains initially set to 0 for all 3 antennas. */ 5942 DPRINTF(sc, IWN_DEBUG_CALIBRATE, 5943 "%s: setting initial differential gains\n", __func__); 5944 return iwn_cmd(sc, IWN_CMD_PHY_CALIB, &cmd, sizeof cmd, 1); 5945 } 5946 5947 static int 5948 iwn5000_init_gains(struct iwn_softc *sc) 5949 { 5950 struct iwn_phy_calib cmd; 5951 5952 DPRINTF(sc, IWN_DEBUG_TRACE, "->Doing %s\n", __func__); 5953 5954 memset(&cmd, 0, sizeof cmd); 5955 cmd.code = sc->reset_noise_gain; 5956 cmd.ngroups = 1; 5957 cmd.isvalid = 1; 5958 DPRINTF(sc, IWN_DEBUG_CALIBRATE, 5959 "%s: setting initial differential gains\n", __func__); 5960 return iwn_cmd(sc, IWN_CMD_PHY_CALIB, &cmd, sizeof cmd, 1); 5961 } 5962 5963 static int 5964 iwn4965_set_gains(struct iwn_softc *sc) 5965 { 5966 struct iwn_calib_state *calib = &sc->calib; 5967 struct iwn_phy_calib_gain cmd; 5968 int i, delta, noise; 5969 5970 DPRINTF(sc, IWN_DEBUG_TRACE, "->Doing %s\n", __func__); 5971 5972 /* Get minimal noise among connected antennas. */ 5973 noise = INT_MAX; /* NB: There's at least one antenna. */ 5974 for (i = 0; i < 3; i++) 5975 if (sc->chainmask & (1 << i)) 5976 noise = MIN(calib->noise[i], noise); 5977 5978 memset(&cmd, 0, sizeof cmd); 5979 cmd.code = IWN4965_PHY_CALIB_DIFF_GAIN; 5980 /* Set differential gains for connected antennas. */ 5981 for (i = 0; i < 3; i++) { 5982 if (sc->chainmask & (1 << i)) { 5983 /* Compute attenuation (in unit of 1.5dB). */ 5984 delta = (noise - (int32_t)calib->noise[i]) / 30; 5985 /* NB: delta <= 0 */ 5986 /* Limit to [-4.5dB,0]. */ 5987 cmd.gain[i] = MIN(abs(delta), 3); 5988 if (delta < 0) 5989 cmd.gain[i] |= 1 << 2; /* sign bit */ 5990 } 5991 } 5992 DPRINTF(sc, IWN_DEBUG_CALIBRATE, 5993 "setting differential gains Ant A/B/C: %x/%x/%x (%x)\n", 5994 cmd.gain[0], cmd.gain[1], cmd.gain[2], sc->chainmask); 5995 return iwn_cmd(sc, IWN_CMD_PHY_CALIB, &cmd, sizeof cmd, 1); 5996 } 5997 5998 static int 5999 iwn5000_set_gains(struct iwn_softc *sc) 6000 { 6001 struct iwn_calib_state *calib = &sc->calib; 6002 struct iwn_phy_calib_gain cmd; 6003 int i, ant, div, delta; 6004 6005 DPRINTF(sc, IWN_DEBUG_TRACE, "->Doing %s\n", __func__); 6006 6007 /* We collected 20 beacons and !=6050 need a 1.5 factor. */ 6008 div = (sc->hw_type == IWN_HW_REV_TYPE_6050) ? 20 : 30; 6009 6010 memset(&cmd, 0, sizeof cmd); 6011 cmd.code = sc->noise_gain; 6012 cmd.ngroups = 1; 6013 cmd.isvalid = 1; 6014 /* Get first available RX antenna as referential. */ 6015 ant = IWN_LSB(sc->rxchainmask); 6016 /* Set differential gains for other antennas. */ 6017 for (i = ant + 1; i < 3; i++) { 6018 if (sc->chainmask & (1 << i)) { 6019 /* The delta is relative to antenna "ant". */ 6020 delta = ((int32_t)calib->noise[ant] - 6021 (int32_t)calib->noise[i]) / div; 6022 /* Limit to [-4.5dB,+4.5dB]. */ 6023 cmd.gain[i - 1] = MIN(abs(delta), 3); 6024 if (delta < 0) 6025 cmd.gain[i - 1] |= 1 << 2; /* sign bit */ 6026 } 6027 } 6028 DPRINTF(sc, IWN_DEBUG_CALIBRATE | IWN_DEBUG_XMIT, 6029 "setting differential gains Ant B/C: %x/%x (%x)\n", 6030 cmd.gain[0], cmd.gain[1], sc->chainmask); 6031 return iwn_cmd(sc, IWN_CMD_PHY_CALIB, &cmd, sizeof cmd, 1); 6032 } 6033 6034 /* 6035 * Tune RF RX sensitivity based on the number of false alarms detected 6036 * during the last beacon period. 6037 */ 6038 static void 6039 iwn_tune_sensitivity(struct iwn_softc *sc, const struct iwn_rx_stats *stats) 6040 { 6041 #define inc(val, inc, max) \ 6042 if ((val) < (max)) { \ 6043 if ((val) < (max) - (inc)) \ 6044 (val) += (inc); \ 6045 else \ 6046 (val) = (max); \ 6047 needs_update = 1; \ 6048 } 6049 #define dec(val, dec, min) \ 6050 if ((val) > (min)) { \ 6051 if ((val) > (min) + (dec)) \ 6052 (val) -= (dec); \ 6053 else \ 6054 (val) = (min); \ 6055 needs_update = 1; \ 6056 } 6057 6058 const struct iwn_sensitivity_limits *limits = sc->limits; 6059 struct iwn_calib_state *calib = &sc->calib; 6060 uint32_t val, rxena, fa; 6061 uint32_t energy[3], energy_min; 6062 uint8_t noise[3], noise_ref; 6063 int i, needs_update = 0; 6064 6065 DPRINTF(sc, IWN_DEBUG_TRACE, "->%s begin\n", __func__); 6066 6067 /* Check that we've been enabled long enough. */ 6068 if ((rxena = le32toh(stats->general.load)) == 0){ 6069 DPRINTF(sc, IWN_DEBUG_TRACE, "->%s end not so long\n", __func__); 6070 return; 6071 } 6072 6073 /* Compute number of false alarms since last call for OFDM. */ 6074 fa = le32toh(stats->ofdm.bad_plcp) - calib->bad_plcp_ofdm; 6075 fa += le32toh(stats->ofdm.fa) - calib->fa_ofdm; 6076 fa *= 200 * IEEE80211_DUR_TU; /* 200TU */ 6077 6078 if (fa > 50 * rxena) { 6079 /* High false alarm count, decrease sensitivity. */ 6080 DPRINTF(sc, IWN_DEBUG_CALIBRATE, 6081 "%s: OFDM high false alarm count: %u\n", __func__, fa); 6082 inc(calib->ofdm_x1, 1, limits->max_ofdm_x1); 6083 inc(calib->ofdm_mrc_x1, 1, limits->max_ofdm_mrc_x1); 6084 inc(calib->ofdm_x4, 1, limits->max_ofdm_x4); 6085 inc(calib->ofdm_mrc_x4, 1, limits->max_ofdm_mrc_x4); 6086 6087 } else if (fa < 5 * rxena) { 6088 /* Low false alarm count, increase sensitivity. */ 6089 DPRINTF(sc, IWN_DEBUG_CALIBRATE, 6090 "%s: OFDM low false alarm count: %u\n", __func__, fa); 6091 dec(calib->ofdm_x1, 1, limits->min_ofdm_x1); 6092 dec(calib->ofdm_mrc_x1, 1, limits->min_ofdm_mrc_x1); 6093 dec(calib->ofdm_x4, 1, limits->min_ofdm_x4); 6094 dec(calib->ofdm_mrc_x4, 1, limits->min_ofdm_mrc_x4); 6095 } 6096 6097 /* Compute maximum noise among 3 receivers. */ 6098 for (i = 0; i < 3; i++) 6099 noise[i] = (le32toh(stats->general.noise[i]) >> 8) & 0xff; 6100 val = MAX(noise[0], noise[1]); 6101 val = MAX(noise[2], val); 6102 /* Insert it into our samples table. */ 6103 calib->noise_samples[calib->cur_noise_sample] = val; 6104 calib->cur_noise_sample = (calib->cur_noise_sample + 1) % 20; 6105 6106 /* Compute maximum noise among last 20 samples. */ 6107 noise_ref = calib->noise_samples[0]; 6108 for (i = 1; i < 20; i++) 6109 noise_ref = MAX(noise_ref, calib->noise_samples[i]); 6110 6111 /* Compute maximum energy among 3 receivers. */ 6112 for (i = 0; i < 3; i++) 6113 energy[i] = le32toh(stats->general.energy[i]); 6114 val = MIN(energy[0], energy[1]); 6115 val = MIN(energy[2], val); 6116 /* Insert it into our samples table. */ 6117 calib->energy_samples[calib->cur_energy_sample] = val; 6118 calib->cur_energy_sample = (calib->cur_energy_sample + 1) % 10; 6119 6120 /* Compute minimum energy among last 10 samples. */ 6121 energy_min = calib->energy_samples[0]; 6122 for (i = 1; i < 10; i++) 6123 energy_min = MAX(energy_min, calib->energy_samples[i]); 6124 energy_min += 6; 6125 6126 /* Compute number of false alarms since last call for CCK. */ 6127 fa = le32toh(stats->cck.bad_plcp) - calib->bad_plcp_cck; 6128 fa += le32toh(stats->cck.fa) - calib->fa_cck; 6129 fa *= 200 * IEEE80211_DUR_TU; /* 200TU */ 6130 6131 if (fa > 50 * rxena) { 6132 /* High false alarm count, decrease sensitivity. */ 6133 DPRINTF(sc, IWN_DEBUG_CALIBRATE, 6134 "%s: CCK high false alarm count: %u\n", __func__, fa); 6135 calib->cck_state = IWN_CCK_STATE_HIFA; 6136 calib->low_fa = 0; 6137 6138 if (calib->cck_x4 > 160) { 6139 calib->noise_ref = noise_ref; 6140 if (calib->energy_cck > 2) 6141 dec(calib->energy_cck, 2, energy_min); 6142 } 6143 if (calib->cck_x4 < 160) { 6144 calib->cck_x4 = 161; 6145 needs_update = 1; 6146 } else 6147 inc(calib->cck_x4, 3, limits->max_cck_x4); 6148 6149 inc(calib->cck_mrc_x4, 3, limits->max_cck_mrc_x4); 6150 6151 } else if (fa < 5 * rxena) { 6152 /* Low false alarm count, increase sensitivity. */ 6153 DPRINTF(sc, IWN_DEBUG_CALIBRATE, 6154 "%s: CCK low false alarm count: %u\n", __func__, fa); 6155 calib->cck_state = IWN_CCK_STATE_LOFA; 6156 calib->low_fa++; 6157 6158 if (calib->cck_state != IWN_CCK_STATE_INIT && 6159 (((int32_t)calib->noise_ref - (int32_t)noise_ref) > 2 || 6160 calib->low_fa > 100)) { 6161 inc(calib->energy_cck, 2, limits->min_energy_cck); 6162 dec(calib->cck_x4, 3, limits->min_cck_x4); 6163 dec(calib->cck_mrc_x4, 3, limits->min_cck_mrc_x4); 6164 } 6165 } else { 6166 /* Not worth to increase or decrease sensitivity. */ 6167 DPRINTF(sc, IWN_DEBUG_CALIBRATE, 6168 "%s: CCK normal false alarm count: %u\n", __func__, fa); 6169 calib->low_fa = 0; 6170 calib->noise_ref = noise_ref; 6171 6172 if (calib->cck_state == IWN_CCK_STATE_HIFA) { 6173 /* Previous interval had many false alarms. */ 6174 dec(calib->energy_cck, 8, energy_min); 6175 } 6176 calib->cck_state = IWN_CCK_STATE_INIT; 6177 } 6178 6179 if (needs_update) 6180 (void)iwn_send_sensitivity(sc); 6181 6182 DPRINTF(sc, IWN_DEBUG_TRACE, "->%s: end\n",__func__); 6183 6184 #undef dec 6185 #undef inc 6186 } 6187 6188 static int 6189 iwn_send_sensitivity(struct iwn_softc *sc) 6190 { 6191 struct iwn_calib_state *calib = &sc->calib; 6192 struct iwn_enhanced_sensitivity_cmd cmd; 6193 int len; 6194 6195 memset(&cmd, 0, sizeof cmd); 6196 len = sizeof (struct iwn_sensitivity_cmd); 6197 cmd.which = IWN_SENSITIVITY_WORKTBL; 6198 /* OFDM modulation. */ 6199 cmd.corr_ofdm_x1 = htole16(calib->ofdm_x1); 6200 cmd.corr_ofdm_mrc_x1 = htole16(calib->ofdm_mrc_x1); 6201 cmd.corr_ofdm_x4 = htole16(calib->ofdm_x4); 6202 cmd.corr_ofdm_mrc_x4 = htole16(calib->ofdm_mrc_x4); 6203 cmd.energy_ofdm = htole16(sc->limits->energy_ofdm); 6204 cmd.energy_ofdm_th = htole16(62); 6205 /* CCK modulation. */ 6206 cmd.corr_cck_x4 = htole16(calib->cck_x4); 6207 cmd.corr_cck_mrc_x4 = htole16(calib->cck_mrc_x4); 6208 cmd.energy_cck = htole16(calib->energy_cck); 6209 /* Barker modulation: use default values. */ 6210 cmd.corr_barker = htole16(190); 6211 cmd.corr_barker_mrc = htole16(sc->limits->barker_mrc); 6212 6213 DPRINTF(sc, IWN_DEBUG_CALIBRATE, 6214 "%s: set sensitivity %d/%d/%d/%d/%d/%d/%d\n", __func__, 6215 calib->ofdm_x1, calib->ofdm_mrc_x1, calib->ofdm_x4, 6216 calib->ofdm_mrc_x4, calib->cck_x4, 6217 calib->cck_mrc_x4, calib->energy_cck); 6218 6219 if (!(sc->sc_flags & IWN_FLAG_ENH_SENS)) 6220 goto send; 6221 /* Enhanced sensitivity settings. */ 6222 len = sizeof (struct iwn_enhanced_sensitivity_cmd); 6223 cmd.ofdm_det_slope_mrc = htole16(668); 6224 cmd.ofdm_det_icept_mrc = htole16(4); 6225 cmd.ofdm_det_slope = htole16(486); 6226 cmd.ofdm_det_icept = htole16(37); 6227 cmd.cck_det_slope_mrc = htole16(853); 6228 cmd.cck_det_icept_mrc = htole16(4); 6229 cmd.cck_det_slope = htole16(476); 6230 cmd.cck_det_icept = htole16(99); 6231 send: 6232 return iwn_cmd(sc, IWN_CMD_SET_SENSITIVITY, &cmd, len, 1); 6233 } 6234 6235 /* 6236 * Look at the increase of PLCP errors over time; if it exceeds 6237 * a programmed threshold then trigger an RF retune. 6238 */ 6239 static void 6240 iwn_check_rx_recovery(struct iwn_softc *sc, struct iwn_stats *rs) 6241 { 6242 int32_t delta_ofdm, delta_ht, delta_cck; 6243 struct iwn_calib_state *calib = &sc->calib; 6244 int delta_ticks, cur_ticks; 6245 int delta_msec; 6246 int thresh; 6247 6248 /* 6249 * Calculate the difference between the current and 6250 * previous statistics. 6251 */ 6252 delta_cck = le32toh(rs->rx.cck.bad_plcp) - calib->bad_plcp_cck; 6253 delta_ofdm = le32toh(rs->rx.ofdm.bad_plcp) - calib->bad_plcp_ofdm; 6254 delta_ht = le32toh(rs->rx.ht.bad_plcp) - calib->bad_plcp_ht; 6255 6256 /* 6257 * Calculate the delta in time between successive statistics 6258 * messages. Yes, it can roll over; so we make sure that 6259 * this doesn't happen. 6260 * 6261 * XXX go figure out what to do about rollover 6262 * XXX go figure out what to do if ticks rolls over to -ve instead! 6263 * XXX go stab signed integer overflow undefined-ness in the face. 6264 */ 6265 cur_ticks = ticks; 6266 delta_ticks = cur_ticks - sc->last_calib_ticks; 6267 6268 /* 6269 * If any are negative, then the firmware likely reset; so just 6270 * bail. We'll pick this up next time. 6271 */ 6272 if (delta_cck < 0 || delta_ofdm < 0 || delta_ht < 0 || delta_ticks < 0) 6273 return; 6274 6275 /* 6276 * delta_ticks is in ticks; we need to convert it up to milliseconds 6277 * so we can do some useful math with it. 6278 */ 6279 delta_msec = ticks_to_msecs(delta_ticks); 6280 6281 /* 6282 * Calculate what our threshold is given the current delta_msec. 6283 */ 6284 thresh = sc->base_params->plcp_err_threshold * delta_msec; 6285 6286 DPRINTF(sc, IWN_DEBUG_STATE, 6287 "%s: time delta: %d; cck=%d, ofdm=%d, ht=%d, total=%d, thresh=%d\n", 6288 __func__, 6289 delta_msec, 6290 delta_cck, 6291 delta_ofdm, 6292 delta_ht, 6293 (delta_msec + delta_cck + delta_ofdm + delta_ht), 6294 thresh); 6295 6296 /* 6297 * If we need a retune, then schedule a single channel scan 6298 * to a channel that isn't the currently active one! 6299 * 6300 * The math from linux iwlwifi: 6301 * 6302 * if ((delta * 100 / msecs) > threshold) 6303 */ 6304 if (thresh > 0 && (delta_cck + delta_ofdm + delta_ht) * 100 > thresh) { 6305 DPRINTF(sc, IWN_DEBUG_ANY, 6306 "%s: PLCP error threshold raw (%d) comparison (%d) " 6307 "over limit (%d); retune!\n", 6308 __func__, 6309 (delta_cck + delta_ofdm + delta_ht), 6310 (delta_cck + delta_ofdm + delta_ht) * 100, 6311 thresh); 6312 } 6313 } 6314 6315 /* 6316 * Set STA mode power saving level (between 0 and 5). 6317 * Level 0 is CAM (Continuously Aware Mode), 5 is for maximum power saving. 6318 */ 6319 static int 6320 iwn_set_pslevel(struct iwn_softc *sc, int dtim, int level, int async) 6321 { 6322 struct iwn_pmgt_cmd cmd; 6323 const struct iwn_pmgt *pmgt; 6324 uint32_t max, skip_dtim; 6325 uint32_t reg; 6326 int i; 6327 6328 DPRINTF(sc, IWN_DEBUG_PWRSAVE, 6329 "%s: dtim=%d, level=%d, async=%d\n", 6330 __func__, 6331 dtim, 6332 level, 6333 async); 6334 6335 /* Select which PS parameters to use. */ 6336 if (dtim <= 2) 6337 pmgt = &iwn_pmgt[0][level]; 6338 else if (dtim <= 10) 6339 pmgt = &iwn_pmgt[1][level]; 6340 else 6341 pmgt = &iwn_pmgt[2][level]; 6342 6343 memset(&cmd, 0, sizeof cmd); 6344 if (level != 0) /* not CAM */ 6345 cmd.flags |= htole16(IWN_PS_ALLOW_SLEEP); 6346 if (level == 5) 6347 cmd.flags |= htole16(IWN_PS_FAST_PD); 6348 /* Retrieve PCIe Active State Power Management (ASPM). */ 6349 reg = pci_read_config(sc->sc_dev, sc->sc_cap_off + PCIER_LINK_CTL, 4); 6350 if (!(reg & PCIEM_LINK_CTL_ASPMC_L0S)) /* L0s Entry disabled. */ 6351 cmd.flags |= htole16(IWN_PS_PCI_PMGT); 6352 cmd.rxtimeout = htole32(pmgt->rxtimeout * 1024); 6353 cmd.txtimeout = htole32(pmgt->txtimeout * 1024); 6354 6355 if (dtim == 0) { 6356 dtim = 1; 6357 skip_dtim = 0; 6358 } else 6359 skip_dtim = pmgt->skip_dtim; 6360 if (skip_dtim != 0) { 6361 cmd.flags |= htole16(IWN_PS_SLEEP_OVER_DTIM); 6362 max = pmgt->intval[4]; 6363 if (max == (uint32_t)-1) 6364 max = dtim * (skip_dtim + 1); 6365 else if (max > dtim) 6366 max = rounddown(max, dtim); 6367 } else 6368 max = dtim; 6369 for (i = 0; i < 5; i++) 6370 cmd.intval[i] = htole32(MIN(max, pmgt->intval[i])); 6371 6372 DPRINTF(sc, IWN_DEBUG_RESET, "setting power saving level to %d\n", 6373 level); 6374 return iwn_cmd(sc, IWN_CMD_SET_POWER_MODE, &cmd, sizeof cmd, async); 6375 } 6376 6377 static int 6378 iwn_send_btcoex(struct iwn_softc *sc) 6379 { 6380 struct iwn_bluetooth cmd; 6381 6382 memset(&cmd, 0, sizeof cmd); 6383 cmd.flags = IWN_BT_COEX_CHAN_ANN | IWN_BT_COEX_BT_PRIO; 6384 cmd.lead_time = IWN_BT_LEAD_TIME_DEF; 6385 cmd.max_kill = IWN_BT_MAX_KILL_DEF; 6386 DPRINTF(sc, IWN_DEBUG_RESET, "%s: configuring bluetooth coexistence\n", 6387 __func__); 6388 return iwn_cmd(sc, IWN_CMD_BT_COEX, &cmd, sizeof(cmd), 0); 6389 } 6390 6391 static int 6392 iwn_send_advanced_btcoex(struct iwn_softc *sc) 6393 { 6394 static const uint32_t btcoex_3wire[12] = { 6395 0xaaaaaaaa, 0xaaaaaaaa, 0xaeaaaaaa, 0xaaaaaaaa, 6396 0xcc00ff28, 0x0000aaaa, 0xcc00aaaa, 0x0000aaaa, 6397 0xc0004000, 0x00004000, 0xf0005000, 0xf0005000, 6398 }; 6399 struct iwn6000_btcoex_config btconfig; 6400 struct iwn2000_btcoex_config btconfig2k; 6401 struct iwn_btcoex_priotable btprio; 6402 struct iwn_btcoex_prot btprot; 6403 int error, i; 6404 uint8_t flags; 6405 6406 memset(&btconfig, 0, sizeof btconfig); 6407 memset(&btconfig2k, 0, sizeof btconfig2k); 6408 6409 flags = IWN_BT_FLAG_COEX6000_MODE_3W << 6410 IWN_BT_FLAG_COEX6000_MODE_SHIFT; // Done as is in linux kernel 3.2 6411 6412 if (sc->base_params->bt_sco_disable) 6413 flags &= ~IWN_BT_FLAG_SYNC_2_BT_DISABLE; 6414 else 6415 flags |= IWN_BT_FLAG_SYNC_2_BT_DISABLE; 6416 6417 flags |= IWN_BT_FLAG_COEX6000_CHAN_INHIBITION; 6418 6419 /* Default flags result is 145 as old value */ 6420 6421 /* 6422 * Flags value has to be review. Values must change if we 6423 * which to disable it 6424 */ 6425 if (sc->base_params->bt_session_2) { 6426 btconfig2k.flags = flags; 6427 btconfig2k.max_kill = 5; 6428 btconfig2k.bt3_t7_timer = 1; 6429 btconfig2k.kill_ack = htole32(0xffff0000); 6430 btconfig2k.kill_cts = htole32(0xffff0000); 6431 btconfig2k.sample_time = 2; 6432 btconfig2k.bt3_t2_timer = 0xc; 6433 6434 for (i = 0; i < 12; i++) 6435 btconfig2k.lookup_table[i] = htole32(btcoex_3wire[i]); 6436 btconfig2k.valid = htole16(0xff); 6437 btconfig2k.prio_boost = htole32(0xf0); 6438 DPRINTF(sc, IWN_DEBUG_RESET, 6439 "%s: configuring advanced bluetooth coexistence" 6440 " session 2, flags : 0x%x\n", 6441 __func__, 6442 flags); 6443 error = iwn_cmd(sc, IWN_CMD_BT_COEX, &btconfig2k, 6444 sizeof(btconfig2k), 1); 6445 } else { 6446 btconfig.flags = flags; 6447 btconfig.max_kill = 5; 6448 btconfig.bt3_t7_timer = 1; 6449 btconfig.kill_ack = htole32(0xffff0000); 6450 btconfig.kill_cts = htole32(0xffff0000); 6451 btconfig.sample_time = 2; 6452 btconfig.bt3_t2_timer = 0xc; 6453 6454 for (i = 0; i < 12; i++) 6455 btconfig.lookup_table[i] = htole32(btcoex_3wire[i]); 6456 btconfig.valid = htole16(0xff); 6457 btconfig.prio_boost = 0xf0; 6458 DPRINTF(sc, IWN_DEBUG_RESET, 6459 "%s: configuring advanced bluetooth coexistence," 6460 " flags : 0x%x\n", 6461 __func__, 6462 flags); 6463 error = iwn_cmd(sc, IWN_CMD_BT_COEX, &btconfig, 6464 sizeof(btconfig), 1); 6465 } 6466 6467 if (error != 0) 6468 return error; 6469 6470 memset(&btprio, 0, sizeof btprio); 6471 btprio.calib_init1 = 0x6; 6472 btprio.calib_init2 = 0x7; 6473 btprio.calib_periodic_low1 = 0x2; 6474 btprio.calib_periodic_low2 = 0x3; 6475 btprio.calib_periodic_high1 = 0x4; 6476 btprio.calib_periodic_high2 = 0x5; 6477 btprio.dtim = 0x6; 6478 btprio.scan52 = 0x8; 6479 btprio.scan24 = 0xa; 6480 error = iwn_cmd(sc, IWN_CMD_BT_COEX_PRIOTABLE, &btprio, sizeof(btprio), 6481 1); 6482 if (error != 0) 6483 return error; 6484 6485 /* Force BT state machine change. */ 6486 memset(&btprot, 0, sizeof btprot); 6487 btprot.open = 1; 6488 btprot.type = 1; 6489 error = iwn_cmd(sc, IWN_CMD_BT_COEX_PROT, &btprot, sizeof(btprot), 1); 6490 if (error != 0) 6491 return error; 6492 btprot.open = 0; 6493 return iwn_cmd(sc, IWN_CMD_BT_COEX_PROT, &btprot, sizeof(btprot), 1); 6494 } 6495 6496 static int 6497 iwn5000_runtime_calib(struct iwn_softc *sc) 6498 { 6499 struct iwn5000_calib_config cmd; 6500 6501 memset(&cmd, 0, sizeof cmd); 6502 cmd.ucode.once.enable = 0xffffffff; 6503 cmd.ucode.once.start = IWN5000_CALIB_DC; 6504 DPRINTF(sc, IWN_DEBUG_CALIBRATE, 6505 "%s: configuring runtime calibration\n", __func__); 6506 return iwn_cmd(sc, IWN5000_CMD_CALIB_CONFIG, &cmd, sizeof(cmd), 0); 6507 } 6508 6509 static uint32_t 6510 iwn_get_rxon_ht_flags(struct iwn_softc *sc, struct ieee80211_channel *c) 6511 { 6512 struct ieee80211com *ic = &sc->sc_ic; 6513 uint32_t htflags = 0; 6514 6515 if (! IEEE80211_IS_CHAN_HT(c)) 6516 return (0); 6517 6518 htflags |= IWN_RXON_HT_PROTMODE(ic->ic_curhtprotmode); 6519 6520 if (IEEE80211_IS_CHAN_HT40(c)) { 6521 switch (ic->ic_curhtprotmode) { 6522 case IEEE80211_HTINFO_OPMODE_HT20PR: 6523 htflags |= IWN_RXON_HT_MODEPURE40; 6524 break; 6525 default: 6526 htflags |= IWN_RXON_HT_MODEMIXED; 6527 break; 6528 } 6529 } 6530 if (IEEE80211_IS_CHAN_HT40D(c)) 6531 htflags |= IWN_RXON_HT_HT40MINUS; 6532 6533 return (htflags); 6534 } 6535 6536 static int 6537 iwn_config(struct iwn_softc *sc) 6538 { 6539 struct iwn_ops *ops = &sc->ops; 6540 struct ieee80211com *ic = &sc->sc_ic; 6541 struct ieee80211vap *vap = TAILQ_FIRST(&ic->ic_vaps); 6542 const uint8_t *macaddr; 6543 uint32_t txmask; 6544 uint16_t rxchain; 6545 int error; 6546 6547 DPRINTF(sc, IWN_DEBUG_TRACE, "->%s begin\n", __func__); 6548 6549 if ((sc->base_params->calib_need & IWN_FLG_NEED_PHY_CALIB_TEMP_OFFSET) 6550 && (sc->base_params->calib_need & IWN_FLG_NEED_PHY_CALIB_TEMP_OFFSETv2)) { 6551 device_printf(sc->sc_dev,"%s: temp_offset and temp_offsetv2 are" 6552 " exclusive each together. Review NIC config file. Conf" 6553 " : 0x%08x Flags : 0x%08x \n", __func__, 6554 sc->base_params->calib_need, 6555 (IWN_FLG_NEED_PHY_CALIB_TEMP_OFFSET | 6556 IWN_FLG_NEED_PHY_CALIB_TEMP_OFFSETv2)); 6557 return (EINVAL); 6558 } 6559 6560 /* Compute temperature calib if needed. Will be send by send calib */ 6561 if (sc->base_params->calib_need & IWN_FLG_NEED_PHY_CALIB_TEMP_OFFSET) { 6562 error = iwn5000_temp_offset_calib(sc); 6563 if (error != 0) { 6564 device_printf(sc->sc_dev, 6565 "%s: could not set temperature offset\n", __func__); 6566 return (error); 6567 } 6568 } else if (sc->base_params->calib_need & IWN_FLG_NEED_PHY_CALIB_TEMP_OFFSETv2) { 6569 error = iwn5000_temp_offset_calibv2(sc); 6570 if (error != 0) { 6571 device_printf(sc->sc_dev, 6572 "%s: could not compute temperature offset v2\n", 6573 __func__); 6574 return (error); 6575 } 6576 } 6577 6578 if (sc->hw_type == IWN_HW_REV_TYPE_6050) { 6579 /* Configure runtime DC calibration. */ 6580 error = iwn5000_runtime_calib(sc); 6581 if (error != 0) { 6582 device_printf(sc->sc_dev, 6583 "%s: could not configure runtime calibration\n", 6584 __func__); 6585 return error; 6586 } 6587 } 6588 6589 /* Configure valid TX chains for >=5000 Series. */ 6590 if (sc->hw_type != IWN_HW_REV_TYPE_4965 && 6591 IWN_UCODE_API(sc->ucode_rev) > 1) { 6592 txmask = htole32(sc->txchainmask); 6593 DPRINTF(sc, IWN_DEBUG_RESET | IWN_DEBUG_XMIT, 6594 "%s: configuring valid TX chains 0x%x\n", __func__, txmask); 6595 error = iwn_cmd(sc, IWN5000_CMD_TX_ANT_CONFIG, &txmask, 6596 sizeof txmask, 0); 6597 if (error != 0) { 6598 device_printf(sc->sc_dev, 6599 "%s: could not configure valid TX chains, " 6600 "error %d\n", __func__, error); 6601 return error; 6602 } 6603 } 6604 6605 /* Configure bluetooth coexistence. */ 6606 error = 0; 6607 6608 /* Configure bluetooth coexistence if needed. */ 6609 if (sc->base_params->bt_mode == IWN_BT_ADVANCED) 6610 error = iwn_send_advanced_btcoex(sc); 6611 if (sc->base_params->bt_mode == IWN_BT_SIMPLE) 6612 error = iwn_send_btcoex(sc); 6613 6614 if (error != 0) { 6615 device_printf(sc->sc_dev, 6616 "%s: could not configure bluetooth coexistence, error %d\n", 6617 __func__, error); 6618 return error; 6619 } 6620 6621 /* Set mode, channel, RX filter and enable RX. */ 6622 sc->rxon = &sc->rx_on[IWN_RXON_BSS_CTX]; 6623 memset(sc->rxon, 0, sizeof (struct iwn_rxon)); 6624 macaddr = vap ? vap->iv_myaddr : ic->ic_macaddr; 6625 IEEE80211_ADDR_COPY(sc->rxon->myaddr, macaddr); 6626 IEEE80211_ADDR_COPY(sc->rxon->wlap, macaddr); 6627 sc->rxon->chan = ieee80211_chan2ieee(ic, ic->ic_curchan); 6628 sc->rxon->flags = htole32(IWN_RXON_TSF | IWN_RXON_CTS_TO_SELF); 6629 if (IEEE80211_IS_CHAN_2GHZ(ic->ic_curchan)) 6630 sc->rxon->flags |= htole32(IWN_RXON_AUTO | IWN_RXON_24GHZ); 6631 switch (ic->ic_opmode) { 6632 case IEEE80211_M_STA: 6633 sc->rxon->mode = IWN_MODE_STA; 6634 sc->rxon->filter = htole32(IWN_FILTER_MULTICAST); 6635 break; 6636 case IEEE80211_M_MONITOR: 6637 sc->rxon->mode = IWN_MODE_MONITOR; 6638 sc->rxon->filter = htole32(IWN_FILTER_MULTICAST | 6639 IWN_FILTER_CTL | IWN_FILTER_PROMISC); 6640 break; 6641 default: 6642 /* Should not get there. */ 6643 break; 6644 } 6645 sc->rxon->cck_mask = 0x0f; /* not yet negotiated */ 6646 sc->rxon->ofdm_mask = 0xff; /* not yet negotiated */ 6647 sc->rxon->ht_single_mask = 0xff; 6648 sc->rxon->ht_dual_mask = 0xff; 6649 sc->rxon->ht_triple_mask = 0xff; 6650 /* 6651 * In active association mode, ensure that 6652 * all the receive chains are enabled. 6653 * 6654 * Since we're not yet doing SMPS, don't allow the 6655 * number of idle RX chains to be less than the active 6656 * number. 6657 */ 6658 rxchain = 6659 IWN_RXCHAIN_VALID(sc->rxchainmask) | 6660 IWN_RXCHAIN_MIMO_COUNT(sc->nrxchains) | 6661 IWN_RXCHAIN_IDLE_COUNT(sc->nrxchains); 6662 sc->rxon->rxchain = htole16(rxchain); 6663 DPRINTF(sc, IWN_DEBUG_RESET | IWN_DEBUG_XMIT, 6664 "%s: rxchainmask=0x%x, nrxchains=%d\n", 6665 __func__, 6666 sc->rxchainmask, 6667 sc->nrxchains); 6668 6669 sc->rxon->flags |= htole32(iwn_get_rxon_ht_flags(sc, ic->ic_curchan)); 6670 6671 DPRINTF(sc, IWN_DEBUG_RESET, 6672 "%s: setting configuration; flags=0x%08x\n", 6673 __func__, le32toh(sc->rxon->flags)); 6674 if (sc->sc_is_scanning) 6675 device_printf(sc->sc_dev, 6676 "%s: is_scanning set, before RXON\n", 6677 __func__); 6678 error = iwn_cmd(sc, IWN_CMD_RXON, sc->rxon, sc->rxonsz, 0); 6679 if (error != 0) { 6680 device_printf(sc->sc_dev, "%s: RXON command failed\n", 6681 __func__); 6682 return error; 6683 } 6684 6685 if ((error = iwn_add_broadcast_node(sc, 0)) != 0) { 6686 device_printf(sc->sc_dev, "%s: could not add broadcast node\n", 6687 __func__); 6688 return error; 6689 } 6690 6691 /* Configuration has changed, set TX power accordingly. */ 6692 if ((error = ops->set_txpower(sc, 0)) != 0) { 6693 device_printf(sc->sc_dev, "%s: could not set TX power\n", 6694 __func__); 6695 return error; 6696 } 6697 6698 if ((error = iwn_set_critical_temp(sc)) != 0) { 6699 device_printf(sc->sc_dev, 6700 "%s: could not set critical temperature\n", __func__); 6701 return error; 6702 } 6703 6704 /* Set power saving level to CAM during initialization. */ 6705 if ((error = iwn_set_pslevel(sc, 0, 0, 0)) != 0) { 6706 device_printf(sc->sc_dev, 6707 "%s: could not set power saving level\n", __func__); 6708 return error; 6709 } 6710 6711 DPRINTF(sc, IWN_DEBUG_TRACE, "->%s: end\n",__func__); 6712 6713 return 0; 6714 } 6715 6716 static uint16_t 6717 iwn_get_active_dwell_time(struct iwn_softc *sc, 6718 struct ieee80211_channel *c, uint8_t n_probes) 6719 { 6720 /* No channel? Default to 2GHz settings */ 6721 if (c == NULL || IEEE80211_IS_CHAN_2GHZ(c)) { 6722 return (IWN_ACTIVE_DWELL_TIME_2GHZ + 6723 IWN_ACTIVE_DWELL_FACTOR_2GHZ * (n_probes + 1)); 6724 } 6725 6726 /* 5GHz dwell time */ 6727 return (IWN_ACTIVE_DWELL_TIME_5GHZ + 6728 IWN_ACTIVE_DWELL_FACTOR_5GHZ * (n_probes + 1)); 6729 } 6730 6731 /* 6732 * Limit the total dwell time to 85% of the beacon interval. 6733 * 6734 * Returns the dwell time in milliseconds. 6735 */ 6736 static uint16_t 6737 iwn_limit_dwell(struct iwn_softc *sc, uint16_t dwell_time) 6738 { 6739 struct ieee80211com *ic = &sc->sc_ic; 6740 struct ieee80211vap *vap = NULL; 6741 int bintval = 0; 6742 6743 /* bintval is in TU (1.024mS) */ 6744 if (! TAILQ_EMPTY(&ic->ic_vaps)) { 6745 vap = TAILQ_FIRST(&ic->ic_vaps); 6746 bintval = vap->iv_bss->ni_intval; 6747 } 6748 6749 /* 6750 * If it's non-zero, we should calculate the minimum of 6751 * it and the DWELL_BASE. 6752 * 6753 * XXX Yes, the math should take into account that bintval 6754 * is 1.024mS, not 1mS.. 6755 */ 6756 if (bintval > 0) { 6757 DPRINTF(sc, IWN_DEBUG_SCAN, 6758 "%s: bintval=%d\n", 6759 __func__, 6760 bintval); 6761 return (MIN(IWN_PASSIVE_DWELL_BASE, ((bintval * 85) / 100))); 6762 } 6763 6764 /* No association context? Default */ 6765 return (IWN_PASSIVE_DWELL_BASE); 6766 } 6767 6768 static uint16_t 6769 iwn_get_passive_dwell_time(struct iwn_softc *sc, struct ieee80211_channel *c) 6770 { 6771 uint16_t passive; 6772 6773 if (c == NULL || IEEE80211_IS_CHAN_2GHZ(c)) { 6774 passive = IWN_PASSIVE_DWELL_BASE + IWN_PASSIVE_DWELL_TIME_2GHZ; 6775 } else { 6776 passive = IWN_PASSIVE_DWELL_BASE + IWN_PASSIVE_DWELL_TIME_5GHZ; 6777 } 6778 6779 /* Clamp to the beacon interval if we're associated */ 6780 return (iwn_limit_dwell(sc, passive)); 6781 } 6782 6783 static int 6784 iwn_scan(struct iwn_softc *sc, struct ieee80211vap *vap, 6785 struct ieee80211_scan_state *ss, struct ieee80211_channel *c) 6786 { 6787 struct ieee80211com *ic = &sc->sc_ic; 6788 struct ieee80211_node *ni = vap->iv_bss; 6789 struct iwn_scan_hdr *hdr; 6790 struct iwn_cmd_data *tx; 6791 struct iwn_scan_essid *essid; 6792 struct iwn_scan_chan *chan; 6793 struct ieee80211_frame *wh; 6794 struct ieee80211_rateset *rs; 6795 uint8_t *buf, *frm; 6796 uint16_t rxchain; 6797 uint8_t txant; 6798 int buflen, error; 6799 int is_active; 6800 uint16_t dwell_active, dwell_passive; 6801 uint32_t extra, scan_service_time; 6802 6803 DPRINTF(sc, IWN_DEBUG_TRACE, "->%s begin\n", __func__); 6804 6805 /* 6806 * We are absolutely not allowed to send a scan command when another 6807 * scan command is pending. 6808 */ 6809 if (sc->sc_is_scanning) { 6810 device_printf(sc->sc_dev, "%s: called whilst scanning!\n", 6811 __func__); 6812 return (EAGAIN); 6813 } 6814 6815 /* Assign the scan channel */ 6816 c = ic->ic_curchan; 6817 6818 sc->rxon = &sc->rx_on[IWN_RXON_BSS_CTX]; 6819 buf = malloc(IWN_SCAN_MAXSZ, M_DEVBUF, M_NOWAIT | M_ZERO); 6820 if (buf == NULL) { 6821 device_printf(sc->sc_dev, 6822 "%s: could not allocate buffer for scan command\n", 6823 __func__); 6824 return ENOMEM; 6825 } 6826 hdr = (struct iwn_scan_hdr *)buf; 6827 /* 6828 * Move to the next channel if no frames are received within 10ms 6829 * after sending the probe request. 6830 */ 6831 hdr->quiet_time = htole16(10); /* timeout in milliseconds */ 6832 hdr->quiet_threshold = htole16(1); /* min # of packets */ 6833 /* 6834 * Max needs to be greater than active and passive and quiet! 6835 * It's also in microseconds! 6836 */ 6837 hdr->max_svc = htole32(250 * 1024); 6838 6839 /* 6840 * Reset scan: interval=100 6841 * Normal scan: interval=becaon interval 6842 * suspend_time: 100 (TU) 6843 * 6844 */ 6845 extra = (100 /* suspend_time */ / 100 /* beacon interval */) << 22; 6846 //scan_service_time = extra | ((100 /* susp */ % 100 /* int */) * 1024); 6847 scan_service_time = (4 << 22) | (100 * 1024); /* Hardcode for now! */ 6848 hdr->pause_svc = htole32(scan_service_time); 6849 6850 /* Select antennas for scanning. */ 6851 rxchain = 6852 IWN_RXCHAIN_VALID(sc->rxchainmask) | 6853 IWN_RXCHAIN_FORCE_MIMO_SEL(sc->rxchainmask) | 6854 IWN_RXCHAIN_DRIVER_FORCE; 6855 if (IEEE80211_IS_CHAN_A(c) && 6856 sc->hw_type == IWN_HW_REV_TYPE_4965) { 6857 /* Ant A must be avoided in 5GHz because of an HW bug. */ 6858 rxchain |= IWN_RXCHAIN_FORCE_SEL(IWN_ANT_B); 6859 } else /* Use all available RX antennas. */ 6860 rxchain |= IWN_RXCHAIN_FORCE_SEL(sc->rxchainmask); 6861 hdr->rxchain = htole16(rxchain); 6862 hdr->filter = htole32(IWN_FILTER_MULTICAST | IWN_FILTER_BEACON); 6863 6864 tx = (struct iwn_cmd_data *)(hdr + 1); 6865 tx->flags = htole32(IWN_TX_AUTO_SEQ); 6866 tx->id = sc->broadcast_id; 6867 tx->lifetime = htole32(IWN_LIFETIME_INFINITE); 6868 6869 if (IEEE80211_IS_CHAN_5GHZ(c)) { 6870 /* Send probe requests at 6Mbps. */ 6871 tx->rate = htole32(0xd); 6872 rs = &ic->ic_sup_rates[IEEE80211_MODE_11A]; 6873 } else { 6874 hdr->flags = htole32(IWN_RXON_24GHZ | IWN_RXON_AUTO); 6875 if (sc->hw_type == IWN_HW_REV_TYPE_4965 && 6876 sc->rxon->associd && sc->rxon->chan > 14) 6877 tx->rate = htole32(0xd); 6878 else { 6879 /* Send probe requests at 1Mbps. */ 6880 tx->rate = htole32(10 | IWN_RFLAG_CCK); 6881 } 6882 rs = &ic->ic_sup_rates[IEEE80211_MODE_11G]; 6883 } 6884 /* Use the first valid TX antenna. */ 6885 txant = IWN_LSB(sc->txchainmask); 6886 tx->rate |= htole32(IWN_RFLAG_ANT(txant)); 6887 6888 /* 6889 * Only do active scanning if we're announcing a probe request 6890 * for a given SSID (or more, if we ever add it to the driver.) 6891 */ 6892 is_active = 0; 6893 6894 /* 6895 * If we're scanning for a specific SSID, add it to the command. 6896 * 6897 * XXX maybe look at adding support for scanning multiple SSIDs? 6898 */ 6899 essid = (struct iwn_scan_essid *)(tx + 1); 6900 if (ss != NULL) { 6901 if (ss->ss_ssid[0].len != 0) { 6902 essid[0].id = IEEE80211_ELEMID_SSID; 6903 essid[0].len = ss->ss_ssid[0].len; 6904 memcpy(essid[0].data, ss->ss_ssid[0].ssid, ss->ss_ssid[0].len); 6905 } 6906 6907 DPRINTF(sc, IWN_DEBUG_SCAN, "%s: ssid_len=%d, ssid=%*s\n", 6908 __func__, 6909 ss->ss_ssid[0].len, 6910 ss->ss_ssid[0].len, 6911 ss->ss_ssid[0].ssid); 6912 6913 if (ss->ss_nssid > 0) 6914 is_active = 1; 6915 } 6916 6917 /* 6918 * Build a probe request frame. Most of the following code is a 6919 * copy & paste of what is done in net80211. 6920 */ 6921 wh = (struct ieee80211_frame *)(essid + 20); 6922 wh->i_fc[0] = IEEE80211_FC0_VERSION_0 | IEEE80211_FC0_TYPE_MGT | 6923 IEEE80211_FC0_SUBTYPE_PROBE_REQ; 6924 wh->i_fc[1] = IEEE80211_FC1_DIR_NODS; 6925 IEEE80211_ADDR_COPY(wh->i_addr1, vap->iv_ifp->if_broadcastaddr); 6926 IEEE80211_ADDR_COPY(wh->i_addr2, IF_LLADDR(vap->iv_ifp)); 6927 IEEE80211_ADDR_COPY(wh->i_addr3, vap->iv_ifp->if_broadcastaddr); 6928 *(uint16_t *)&wh->i_dur[0] = 0; /* filled by HW */ 6929 *(uint16_t *)&wh->i_seq[0] = 0; /* filled by HW */ 6930 6931 frm = (uint8_t *)(wh + 1); 6932 frm = ieee80211_add_ssid(frm, NULL, 0); 6933 frm = ieee80211_add_rates(frm, rs); 6934 if (rs->rs_nrates > IEEE80211_RATE_SIZE) 6935 frm = ieee80211_add_xrates(frm, rs); 6936 if (ic->ic_htcaps & IEEE80211_HTC_HT) 6937 frm = ieee80211_add_htcap(frm, ni); 6938 6939 /* Set length of probe request. */ 6940 tx->len = htole16(frm - (uint8_t *)wh); 6941 6942 /* 6943 * If active scanning is requested but a certain channel is 6944 * marked passive, we can do active scanning if we detect 6945 * transmissions. 6946 * 6947 * There is an issue with some firmware versions that triggers 6948 * a sysassert on a "good CRC threshold" of zero (== disabled), 6949 * on a radar channel even though this means that we should NOT 6950 * send probes. 6951 * 6952 * The "good CRC threshold" is the number of frames that we 6953 * need to receive during our dwell time on a channel before 6954 * sending out probes -- setting this to a huge value will 6955 * mean we never reach it, but at the same time work around 6956 * the aforementioned issue. Thus use IWL_GOOD_CRC_TH_NEVER 6957 * here instead of IWL_GOOD_CRC_TH_DISABLED. 6958 * 6959 * This was fixed in later versions along with some other 6960 * scan changes, and the threshold behaves as a flag in those 6961 * versions. 6962 */ 6963 6964 /* 6965 * If we're doing active scanning, set the crc_threshold 6966 * to a suitable value. This is different to active veruss 6967 * passive scanning depending upon the channel flags; the 6968 * firmware will obey that particular check for us. 6969 */ 6970 if (sc->tlv_feature_flags & IWN_UCODE_TLV_FLAGS_NEWSCAN) 6971 hdr->crc_threshold = is_active ? 6972 IWN_GOOD_CRC_TH_DEFAULT : IWN_GOOD_CRC_TH_DISABLED; 6973 else 6974 hdr->crc_threshold = is_active ? 6975 IWN_GOOD_CRC_TH_DEFAULT : IWN_GOOD_CRC_TH_NEVER; 6976 6977 chan = (struct iwn_scan_chan *)frm; 6978 chan->chan = htole16(ieee80211_chan2ieee(ic, c)); 6979 chan->flags = 0; 6980 if (ss->ss_nssid > 0) 6981 chan->flags |= htole32(IWN_CHAN_NPBREQS(1)); 6982 chan->dsp_gain = 0x6e; 6983 6984 /* 6985 * Set the passive/active flag depending upon the channel mode. 6986 * XXX TODO: take the is_active flag into account as well? 6987 */ 6988 if (c->ic_flags & IEEE80211_CHAN_PASSIVE) 6989 chan->flags |= htole32(IWN_CHAN_PASSIVE); 6990 else 6991 chan->flags |= htole32(IWN_CHAN_ACTIVE); 6992 6993 /* 6994 * Calculate the active/passive dwell times. 6995 */ 6996 6997 dwell_active = iwn_get_active_dwell_time(sc, c, ss->ss_nssid); 6998 dwell_passive = iwn_get_passive_dwell_time(sc, c); 6999 7000 /* Make sure they're valid */ 7001 if (dwell_passive <= dwell_active) 7002 dwell_passive = dwell_active + 1; 7003 7004 chan->active = htole16(dwell_active); 7005 chan->passive = htole16(dwell_passive); 7006 7007 if (IEEE80211_IS_CHAN_5GHZ(c)) 7008 chan->rf_gain = 0x3b; 7009 else 7010 chan->rf_gain = 0x28; 7011 7012 DPRINTF(sc, IWN_DEBUG_STATE, 7013 "%s: chan %u flags 0x%x rf_gain 0x%x " 7014 "dsp_gain 0x%x active %d passive %d scan_svc_time %d crc 0x%x " 7015 "isactive=%d numssid=%d\n", __func__, 7016 chan->chan, chan->flags, chan->rf_gain, chan->dsp_gain, 7017 dwell_active, dwell_passive, scan_service_time, 7018 hdr->crc_threshold, is_active, ss->ss_nssid); 7019 7020 hdr->nchan++; 7021 chan++; 7022 buflen = (uint8_t *)chan - buf; 7023 hdr->len = htole16(buflen); 7024 7025 if (sc->sc_is_scanning) { 7026 device_printf(sc->sc_dev, 7027 "%s: called with is_scanning set!\n", 7028 __func__); 7029 } 7030 sc->sc_is_scanning = 1; 7031 7032 DPRINTF(sc, IWN_DEBUG_STATE, "sending scan command nchan=%d\n", 7033 hdr->nchan); 7034 error = iwn_cmd(sc, IWN_CMD_SCAN, buf, buflen, 1); 7035 free(buf, M_DEVBUF); 7036 if (error == 0) 7037 callout_reset(&sc->scan_timeout, 5*hz, iwn_scan_timeout, sc); 7038 7039 DPRINTF(sc, IWN_DEBUG_TRACE, "->%s: end\n",__func__); 7040 7041 return error; 7042 } 7043 7044 static int 7045 iwn_auth(struct iwn_softc *sc, struct ieee80211vap *vap) 7046 { 7047 struct iwn_ops *ops = &sc->ops; 7048 struct ieee80211com *ic = &sc->sc_ic; 7049 struct ieee80211_node *ni = vap->iv_bss; 7050 int error; 7051 7052 DPRINTF(sc, IWN_DEBUG_TRACE, "->%s begin\n", __func__); 7053 7054 sc->rxon = &sc->rx_on[IWN_RXON_BSS_CTX]; 7055 /* Update adapter configuration. */ 7056 IEEE80211_ADDR_COPY(sc->rxon->bssid, ni->ni_bssid); 7057 sc->rxon->chan = ieee80211_chan2ieee(ic, ni->ni_chan); 7058 sc->rxon->flags = htole32(IWN_RXON_TSF | IWN_RXON_CTS_TO_SELF); 7059 if (IEEE80211_IS_CHAN_2GHZ(ni->ni_chan)) 7060 sc->rxon->flags |= htole32(IWN_RXON_AUTO | IWN_RXON_24GHZ); 7061 if (ic->ic_flags & IEEE80211_F_SHSLOT) 7062 sc->rxon->flags |= htole32(IWN_RXON_SHSLOT); 7063 if (ic->ic_flags & IEEE80211_F_SHPREAMBLE) 7064 sc->rxon->flags |= htole32(IWN_RXON_SHPREAMBLE); 7065 if (IEEE80211_IS_CHAN_A(ni->ni_chan)) { 7066 sc->rxon->cck_mask = 0; 7067 sc->rxon->ofdm_mask = 0x15; 7068 } else if (IEEE80211_IS_CHAN_B(ni->ni_chan)) { 7069 sc->rxon->cck_mask = 0x03; 7070 sc->rxon->ofdm_mask = 0; 7071 } else { 7072 /* Assume 802.11b/g. */ 7073 sc->rxon->cck_mask = 0x03; 7074 sc->rxon->ofdm_mask = 0x15; 7075 } 7076 7077 /* try HT */ 7078 sc->rxon->flags |= htole32(iwn_get_rxon_ht_flags(sc, ic->ic_curchan)); 7079 7080 DPRINTF(sc, IWN_DEBUG_STATE, "rxon chan %d flags %x cck %x ofdm %x\n", 7081 sc->rxon->chan, sc->rxon->flags, sc->rxon->cck_mask, 7082 sc->rxon->ofdm_mask); 7083 if (sc->sc_is_scanning) 7084 device_printf(sc->sc_dev, 7085 "%s: is_scanning set, before RXON\n", 7086 __func__); 7087 error = iwn_cmd(sc, IWN_CMD_RXON, sc->rxon, sc->rxonsz, 1); 7088 if (error != 0) { 7089 device_printf(sc->sc_dev, "%s: RXON command failed, error %d\n", 7090 __func__, error); 7091 return error; 7092 } 7093 7094 /* Configuration has changed, set TX power accordingly. */ 7095 if ((error = ops->set_txpower(sc, 1)) != 0) { 7096 device_printf(sc->sc_dev, 7097 "%s: could not set TX power, error %d\n", __func__, error); 7098 return error; 7099 } 7100 /* 7101 * Reconfiguring RXON clears the firmware nodes table so we must 7102 * add the broadcast node again. 7103 */ 7104 if ((error = iwn_add_broadcast_node(sc, 1)) != 0) { 7105 device_printf(sc->sc_dev, 7106 "%s: could not add broadcast node, error %d\n", __func__, 7107 error); 7108 return error; 7109 } 7110 7111 DPRINTF(sc, IWN_DEBUG_TRACE, "->%s: end\n",__func__); 7112 7113 return 0; 7114 } 7115 7116 static int 7117 iwn_run(struct iwn_softc *sc, struct ieee80211vap *vap) 7118 { 7119 struct iwn_ops *ops = &sc->ops; 7120 struct ieee80211com *ic = &sc->sc_ic; 7121 struct ieee80211_node *ni = vap->iv_bss; 7122 struct iwn_node_info node; 7123 int error; 7124 7125 DPRINTF(sc, IWN_DEBUG_TRACE, "->%s begin\n", __func__); 7126 7127 sc->rxon = &sc->rx_on[IWN_RXON_BSS_CTX]; 7128 if (ic->ic_opmode == IEEE80211_M_MONITOR) { 7129 /* Link LED blinks while monitoring. */ 7130 iwn_set_led(sc, IWN_LED_LINK, 5, 5); 7131 return 0; 7132 } 7133 if ((error = iwn_set_timing(sc, ni)) != 0) { 7134 device_printf(sc->sc_dev, 7135 "%s: could not set timing, error %d\n", __func__, error); 7136 return error; 7137 } 7138 7139 /* Update adapter configuration. */ 7140 IEEE80211_ADDR_COPY(sc->rxon->bssid, ni->ni_bssid); 7141 sc->rxon->associd = htole16(IEEE80211_AID(ni->ni_associd)); 7142 sc->rxon->chan = ieee80211_chan2ieee(ic, ni->ni_chan); 7143 sc->rxon->flags = htole32(IWN_RXON_TSF | IWN_RXON_CTS_TO_SELF); 7144 if (IEEE80211_IS_CHAN_2GHZ(ni->ni_chan)) 7145 sc->rxon->flags |= htole32(IWN_RXON_AUTO | IWN_RXON_24GHZ); 7146 if (ic->ic_flags & IEEE80211_F_SHSLOT) 7147 sc->rxon->flags |= htole32(IWN_RXON_SHSLOT); 7148 if (ic->ic_flags & IEEE80211_F_SHPREAMBLE) 7149 sc->rxon->flags |= htole32(IWN_RXON_SHPREAMBLE); 7150 if (IEEE80211_IS_CHAN_A(ni->ni_chan)) { 7151 sc->rxon->cck_mask = 0; 7152 sc->rxon->ofdm_mask = 0x15; 7153 } else if (IEEE80211_IS_CHAN_B(ni->ni_chan)) { 7154 sc->rxon->cck_mask = 0x03; 7155 sc->rxon->ofdm_mask = 0; 7156 } else { 7157 /* Assume 802.11b/g. */ 7158 sc->rxon->cck_mask = 0x0f; 7159 sc->rxon->ofdm_mask = 0x15; 7160 } 7161 /* try HT */ 7162 sc->rxon->flags |= htole32(iwn_get_rxon_ht_flags(sc, ni->ni_chan)); 7163 sc->rxon->filter |= htole32(IWN_FILTER_BSS); 7164 DPRINTF(sc, IWN_DEBUG_STATE, "rxon chan %d flags %x, curhtprotmode=%d\n", 7165 sc->rxon->chan, le32toh(sc->rxon->flags), ic->ic_curhtprotmode); 7166 if (sc->sc_is_scanning) 7167 device_printf(sc->sc_dev, 7168 "%s: is_scanning set, before RXON\n", 7169 __func__); 7170 error = iwn_cmd(sc, IWN_CMD_RXON, sc->rxon, sc->rxonsz, 1); 7171 if (error != 0) { 7172 device_printf(sc->sc_dev, 7173 "%s: could not update configuration, error %d\n", __func__, 7174 error); 7175 return error; 7176 } 7177 7178 /* Configuration has changed, set TX power accordingly. */ 7179 if ((error = ops->set_txpower(sc, 1)) != 0) { 7180 device_printf(sc->sc_dev, 7181 "%s: could not set TX power, error %d\n", __func__, error); 7182 return error; 7183 } 7184 7185 /* Fake a join to initialize the TX rate. */ 7186 ((struct iwn_node *)ni)->id = IWN_ID_BSS; 7187 iwn_newassoc(ni, 1); 7188 7189 /* Add BSS node. */ 7190 memset(&node, 0, sizeof node); 7191 IEEE80211_ADDR_COPY(node.macaddr, ni->ni_macaddr); 7192 node.id = IWN_ID_BSS; 7193 if (IEEE80211_IS_CHAN_HT(ni->ni_chan)) { 7194 switch (ni->ni_htcap & IEEE80211_HTCAP_SMPS) { 7195 case IEEE80211_HTCAP_SMPS_ENA: 7196 node.htflags |= htole32(IWN_SMPS_MIMO_DIS); 7197 break; 7198 case IEEE80211_HTCAP_SMPS_DYNAMIC: 7199 node.htflags |= htole32(IWN_SMPS_MIMO_PROT); 7200 break; 7201 } 7202 node.htflags |= htole32(IWN_AMDPU_SIZE_FACTOR(3) | 7203 IWN_AMDPU_DENSITY(5)); /* 4us */ 7204 if (IEEE80211_IS_CHAN_HT40(ni->ni_chan)) 7205 node.htflags |= htole32(IWN_NODE_HT40); 7206 } 7207 DPRINTF(sc, IWN_DEBUG_STATE, "%s: adding BSS node\n", __func__); 7208 error = ops->add_node(sc, &node, 1); 7209 if (error != 0) { 7210 device_printf(sc->sc_dev, 7211 "%s: could not add BSS node, error %d\n", __func__, error); 7212 return error; 7213 } 7214 DPRINTF(sc, IWN_DEBUG_STATE, "%s: setting link quality for node %d\n", 7215 __func__, node.id); 7216 if ((error = iwn_set_link_quality(sc, ni)) != 0) { 7217 device_printf(sc->sc_dev, 7218 "%s: could not setup link quality for node %d, error %d\n", 7219 __func__, node.id, error); 7220 return error; 7221 } 7222 7223 if ((error = iwn_init_sensitivity(sc)) != 0) { 7224 device_printf(sc->sc_dev, 7225 "%s: could not set sensitivity, error %d\n", __func__, 7226 error); 7227 return error; 7228 } 7229 /* Start periodic calibration timer. */ 7230 sc->calib.state = IWN_CALIB_STATE_ASSOC; 7231 sc->calib_cnt = 0; 7232 callout_reset(&sc->calib_to, msecs_to_ticks(500), iwn_calib_timeout, 7233 sc); 7234 7235 /* Link LED always on while associated. */ 7236 iwn_set_led(sc, IWN_LED_LINK, 0, 1); 7237 7238 DPRINTF(sc, IWN_DEBUG_TRACE, "->%s: end\n",__func__); 7239 7240 return 0; 7241 } 7242 7243 /* 7244 * This function is called by upper layer when an ADDBA request is received 7245 * from another STA and before the ADDBA response is sent. 7246 */ 7247 static int 7248 iwn_ampdu_rx_start(struct ieee80211_node *ni, struct ieee80211_rx_ampdu *rap, 7249 int baparamset, int batimeout, int baseqctl) 7250 { 7251 #define MS(_v, _f) (((_v) & _f) >> _f##_S) 7252 struct iwn_softc *sc = ni->ni_ic->ic_softc; 7253 struct iwn_ops *ops = &sc->ops; 7254 struct iwn_node *wn = (void *)ni; 7255 struct iwn_node_info node; 7256 uint16_t ssn; 7257 uint8_t tid; 7258 int error; 7259 7260 DPRINTF(sc, IWN_DEBUG_TRACE, "->Doing %s\n", __func__); 7261 7262 tid = MS(le16toh(baparamset), IEEE80211_BAPS_TID); 7263 ssn = MS(le16toh(baseqctl), IEEE80211_BASEQ_START); 7264 7265 memset(&node, 0, sizeof node); 7266 node.id = wn->id; 7267 node.control = IWN_NODE_UPDATE; 7268 node.flags = IWN_FLAG_SET_ADDBA; 7269 node.addba_tid = tid; 7270 node.addba_ssn = htole16(ssn); 7271 DPRINTF(sc, IWN_DEBUG_RECV, "ADDBA RA=%d TID=%d SSN=%d\n", 7272 wn->id, tid, ssn); 7273 error = ops->add_node(sc, &node, 1); 7274 if (error != 0) 7275 return error; 7276 return sc->sc_ampdu_rx_start(ni, rap, baparamset, batimeout, baseqctl); 7277 #undef MS 7278 } 7279 7280 /* 7281 * This function is called by upper layer on teardown of an HT-immediate 7282 * Block Ack agreement (eg. uppon receipt of a DELBA frame). 7283 */ 7284 static void 7285 iwn_ampdu_rx_stop(struct ieee80211_node *ni, struct ieee80211_rx_ampdu *rap) 7286 { 7287 struct ieee80211com *ic = ni->ni_ic; 7288 struct iwn_softc *sc = ic->ic_softc; 7289 struct iwn_ops *ops = &sc->ops; 7290 struct iwn_node *wn = (void *)ni; 7291 struct iwn_node_info node; 7292 uint8_t tid; 7293 7294 DPRINTF(sc, IWN_DEBUG_TRACE, "->Doing %s\n", __func__); 7295 7296 /* XXX: tid as an argument */ 7297 for (tid = 0; tid < WME_NUM_TID; tid++) { 7298 if (&ni->ni_rx_ampdu[tid] == rap) 7299 break; 7300 } 7301 7302 memset(&node, 0, sizeof node); 7303 node.id = wn->id; 7304 node.control = IWN_NODE_UPDATE; 7305 node.flags = IWN_FLAG_SET_DELBA; 7306 node.delba_tid = tid; 7307 DPRINTF(sc, IWN_DEBUG_RECV, "DELBA RA=%d TID=%d\n", wn->id, tid); 7308 (void)ops->add_node(sc, &node, 1); 7309 sc->sc_ampdu_rx_stop(ni, rap); 7310 } 7311 7312 static int 7313 iwn_addba_request(struct ieee80211_node *ni, struct ieee80211_tx_ampdu *tap, 7314 int dialogtoken, int baparamset, int batimeout) 7315 { 7316 struct iwn_softc *sc = ni->ni_ic->ic_softc; 7317 int qid; 7318 7319 DPRINTF(sc, IWN_DEBUG_TRACE, "->Doing %s\n", __func__); 7320 7321 for (qid = sc->firstaggqueue; qid < sc->ntxqs; qid++) { 7322 if (sc->qid2tap[qid] == NULL) 7323 break; 7324 } 7325 if (qid == sc->ntxqs) { 7326 DPRINTF(sc, IWN_DEBUG_XMIT, "%s: not free aggregation queue\n", 7327 __func__); 7328 return 0; 7329 } 7330 tap->txa_private = malloc(sizeof(int), M_DEVBUF, M_NOWAIT); 7331 if (tap->txa_private == NULL) { 7332 device_printf(sc->sc_dev, 7333 "%s: failed to alloc TX aggregation structure\n", __func__); 7334 return 0; 7335 } 7336 sc->qid2tap[qid] = tap; 7337 *(int *)tap->txa_private = qid; 7338 return sc->sc_addba_request(ni, tap, dialogtoken, baparamset, 7339 batimeout); 7340 } 7341 7342 static int 7343 iwn_addba_response(struct ieee80211_node *ni, struct ieee80211_tx_ampdu *tap, 7344 int code, int baparamset, int batimeout) 7345 { 7346 struct iwn_softc *sc = ni->ni_ic->ic_softc; 7347 int qid = *(int *)tap->txa_private; 7348 uint8_t tid = tap->txa_tid; 7349 int ret; 7350 7351 DPRINTF(sc, IWN_DEBUG_TRACE, "->Doing %s\n", __func__); 7352 7353 if (code == IEEE80211_STATUS_SUCCESS) { 7354 ni->ni_txseqs[tid] = tap->txa_start & 0xfff; 7355 ret = iwn_ampdu_tx_start(ni->ni_ic, ni, tid); 7356 if (ret != 1) 7357 return ret; 7358 } else { 7359 sc->qid2tap[qid] = NULL; 7360 free(tap->txa_private, M_DEVBUF); 7361 tap->txa_private = NULL; 7362 } 7363 return sc->sc_addba_response(ni, tap, code, baparamset, batimeout); 7364 } 7365 7366 /* 7367 * This function is called by upper layer when an ADDBA response is received 7368 * from another STA. 7369 */ 7370 static int 7371 iwn_ampdu_tx_start(struct ieee80211com *ic, struct ieee80211_node *ni, 7372 uint8_t tid) 7373 { 7374 struct ieee80211_tx_ampdu *tap = &ni->ni_tx_ampdu[tid]; 7375 struct iwn_softc *sc = ni->ni_ic->ic_softc; 7376 struct iwn_ops *ops = &sc->ops; 7377 struct iwn_node *wn = (void *)ni; 7378 struct iwn_node_info node; 7379 int error, qid; 7380 7381 DPRINTF(sc, IWN_DEBUG_TRACE, "->Doing %s\n", __func__); 7382 7383 /* Enable TX for the specified RA/TID. */ 7384 wn->disable_tid &= ~(1 << tid); 7385 memset(&node, 0, sizeof node); 7386 node.id = wn->id; 7387 node.control = IWN_NODE_UPDATE; 7388 node.flags = IWN_FLAG_SET_DISABLE_TID; 7389 node.disable_tid = htole16(wn->disable_tid); 7390 error = ops->add_node(sc, &node, 1); 7391 if (error != 0) 7392 return 0; 7393 7394 if ((error = iwn_nic_lock(sc)) != 0) 7395 return 0; 7396 qid = *(int *)tap->txa_private; 7397 DPRINTF(sc, IWN_DEBUG_XMIT, "%s: ra=%d tid=%d ssn=%d qid=%d\n", 7398 __func__, wn->id, tid, tap->txa_start, qid); 7399 ops->ampdu_tx_start(sc, ni, qid, tid, tap->txa_start & 0xfff); 7400 iwn_nic_unlock(sc); 7401 7402 iwn_set_link_quality(sc, ni); 7403 return 1; 7404 } 7405 7406 static void 7407 iwn_ampdu_tx_stop(struct ieee80211_node *ni, struct ieee80211_tx_ampdu *tap) 7408 { 7409 struct iwn_softc *sc = ni->ni_ic->ic_softc; 7410 struct iwn_ops *ops = &sc->ops; 7411 uint8_t tid = tap->txa_tid; 7412 int qid; 7413 7414 DPRINTF(sc, IWN_DEBUG_TRACE, "->Doing %s\n", __func__); 7415 7416 sc->sc_addba_stop(ni, tap); 7417 7418 if (tap->txa_private == NULL) 7419 return; 7420 7421 qid = *(int *)tap->txa_private; 7422 if (sc->txq[qid].queued != 0) 7423 return; 7424 if (iwn_nic_lock(sc) != 0) 7425 return; 7426 ops->ampdu_tx_stop(sc, qid, tid, tap->txa_start & 0xfff); 7427 iwn_nic_unlock(sc); 7428 sc->qid2tap[qid] = NULL; 7429 free(tap->txa_private, M_DEVBUF); 7430 tap->txa_private = NULL; 7431 } 7432 7433 static void 7434 iwn4965_ampdu_tx_start(struct iwn_softc *sc, struct ieee80211_node *ni, 7435 int qid, uint8_t tid, uint16_t ssn) 7436 { 7437 struct iwn_node *wn = (void *)ni; 7438 7439 DPRINTF(sc, IWN_DEBUG_TRACE, "->Doing %s\n", __func__); 7440 7441 /* Stop TX scheduler while we're changing its configuration. */ 7442 iwn_prph_write(sc, IWN4965_SCHED_QUEUE_STATUS(qid), 7443 IWN4965_TXQ_STATUS_CHGACT); 7444 7445 /* Assign RA/TID translation to the queue. */ 7446 iwn_mem_write_2(sc, sc->sched_base + IWN4965_SCHED_TRANS_TBL(qid), 7447 wn->id << 4 | tid); 7448 7449 /* Enable chain-building mode for the queue. */ 7450 iwn_prph_setbits(sc, IWN4965_SCHED_QCHAIN_SEL, 1 << qid); 7451 7452 /* Set starting sequence number from the ADDBA request. */ 7453 sc->txq[qid].cur = sc->txq[qid].read = (ssn & 0xff); 7454 IWN_WRITE(sc, IWN_HBUS_TARG_WRPTR, qid << 8 | (ssn & 0xff)); 7455 iwn_prph_write(sc, IWN4965_SCHED_QUEUE_RDPTR(qid), ssn); 7456 7457 /* Set scheduler window size. */ 7458 iwn_mem_write(sc, sc->sched_base + IWN4965_SCHED_QUEUE_OFFSET(qid), 7459 IWN_SCHED_WINSZ); 7460 /* Set scheduler frame limit. */ 7461 iwn_mem_write(sc, sc->sched_base + IWN4965_SCHED_QUEUE_OFFSET(qid) + 4, 7462 IWN_SCHED_LIMIT << 16); 7463 7464 /* Enable interrupts for the queue. */ 7465 iwn_prph_setbits(sc, IWN4965_SCHED_INTR_MASK, 1 << qid); 7466 7467 /* Mark the queue as active. */ 7468 iwn_prph_write(sc, IWN4965_SCHED_QUEUE_STATUS(qid), 7469 IWN4965_TXQ_STATUS_ACTIVE | IWN4965_TXQ_STATUS_AGGR_ENA | 7470 iwn_tid2fifo[tid] << 1); 7471 } 7472 7473 static void 7474 iwn4965_ampdu_tx_stop(struct iwn_softc *sc, int qid, uint8_t tid, uint16_t ssn) 7475 { 7476 DPRINTF(sc, IWN_DEBUG_TRACE, "->Doing %s\n", __func__); 7477 7478 /* Stop TX scheduler while we're changing its configuration. */ 7479 iwn_prph_write(sc, IWN4965_SCHED_QUEUE_STATUS(qid), 7480 IWN4965_TXQ_STATUS_CHGACT); 7481 7482 /* Set starting sequence number from the ADDBA request. */ 7483 IWN_WRITE(sc, IWN_HBUS_TARG_WRPTR, qid << 8 | (ssn & 0xff)); 7484 iwn_prph_write(sc, IWN4965_SCHED_QUEUE_RDPTR(qid), ssn); 7485 7486 /* Disable interrupts for the queue. */ 7487 iwn_prph_clrbits(sc, IWN4965_SCHED_INTR_MASK, 1 << qid); 7488 7489 /* Mark the queue as inactive. */ 7490 iwn_prph_write(sc, IWN4965_SCHED_QUEUE_STATUS(qid), 7491 IWN4965_TXQ_STATUS_INACTIVE | iwn_tid2fifo[tid] << 1); 7492 } 7493 7494 static void 7495 iwn5000_ampdu_tx_start(struct iwn_softc *sc, struct ieee80211_node *ni, 7496 int qid, uint8_t tid, uint16_t ssn) 7497 { 7498 DPRINTF(sc, IWN_DEBUG_TRACE, "->Doing %s\n", __func__); 7499 7500 struct iwn_node *wn = (void *)ni; 7501 7502 /* Stop TX scheduler while we're changing its configuration. */ 7503 iwn_prph_write(sc, IWN5000_SCHED_QUEUE_STATUS(qid), 7504 IWN5000_TXQ_STATUS_CHGACT); 7505 7506 /* Assign RA/TID translation to the queue. */ 7507 iwn_mem_write_2(sc, sc->sched_base + IWN5000_SCHED_TRANS_TBL(qid), 7508 wn->id << 4 | tid); 7509 7510 /* Enable chain-building mode for the queue. */ 7511 iwn_prph_setbits(sc, IWN5000_SCHED_QCHAIN_SEL, 1 << qid); 7512 7513 /* Enable aggregation for the queue. */ 7514 iwn_prph_setbits(sc, IWN5000_SCHED_AGGR_SEL, 1 << qid); 7515 7516 /* Set starting sequence number from the ADDBA request. */ 7517 sc->txq[qid].cur = sc->txq[qid].read = (ssn & 0xff); 7518 IWN_WRITE(sc, IWN_HBUS_TARG_WRPTR, qid << 8 | (ssn & 0xff)); 7519 iwn_prph_write(sc, IWN5000_SCHED_QUEUE_RDPTR(qid), ssn); 7520 7521 /* Set scheduler window size and frame limit. */ 7522 iwn_mem_write(sc, sc->sched_base + IWN5000_SCHED_QUEUE_OFFSET(qid) + 4, 7523 IWN_SCHED_LIMIT << 16 | IWN_SCHED_WINSZ); 7524 7525 /* Enable interrupts for the queue. */ 7526 iwn_prph_setbits(sc, IWN5000_SCHED_INTR_MASK, 1 << qid); 7527 7528 /* Mark the queue as active. */ 7529 iwn_prph_write(sc, IWN5000_SCHED_QUEUE_STATUS(qid), 7530 IWN5000_TXQ_STATUS_ACTIVE | iwn_tid2fifo[tid]); 7531 } 7532 7533 static void 7534 iwn5000_ampdu_tx_stop(struct iwn_softc *sc, int qid, uint8_t tid, uint16_t ssn) 7535 { 7536 DPRINTF(sc, IWN_DEBUG_TRACE, "->Doing %s\n", __func__); 7537 7538 /* Stop TX scheduler while we're changing its configuration. */ 7539 iwn_prph_write(sc, IWN5000_SCHED_QUEUE_STATUS(qid), 7540 IWN5000_TXQ_STATUS_CHGACT); 7541 7542 /* Disable aggregation for the queue. */ 7543 iwn_prph_clrbits(sc, IWN5000_SCHED_AGGR_SEL, 1 << qid); 7544 7545 /* Set starting sequence number from the ADDBA request. */ 7546 IWN_WRITE(sc, IWN_HBUS_TARG_WRPTR, qid << 8 | (ssn & 0xff)); 7547 iwn_prph_write(sc, IWN5000_SCHED_QUEUE_RDPTR(qid), ssn); 7548 7549 /* Disable interrupts for the queue. */ 7550 iwn_prph_clrbits(sc, IWN5000_SCHED_INTR_MASK, 1 << qid); 7551 7552 /* Mark the queue as inactive. */ 7553 iwn_prph_write(sc, IWN5000_SCHED_QUEUE_STATUS(qid), 7554 IWN5000_TXQ_STATUS_INACTIVE | iwn_tid2fifo[tid]); 7555 } 7556 7557 /* 7558 * Query calibration tables from the initialization firmware. We do this 7559 * only once at first boot. Called from a process context. 7560 */ 7561 static int 7562 iwn5000_query_calibration(struct iwn_softc *sc) 7563 { 7564 struct iwn5000_calib_config cmd; 7565 int error; 7566 7567 memset(&cmd, 0, sizeof cmd); 7568 cmd.ucode.once.enable = htole32(0xffffffff); 7569 cmd.ucode.once.start = htole32(0xffffffff); 7570 cmd.ucode.once.send = htole32(0xffffffff); 7571 cmd.ucode.flags = htole32(0xffffffff); 7572 DPRINTF(sc, IWN_DEBUG_CALIBRATE, "%s: sending calibration query\n", 7573 __func__); 7574 error = iwn_cmd(sc, IWN5000_CMD_CALIB_CONFIG, &cmd, sizeof cmd, 0); 7575 if (error != 0) 7576 return error; 7577 7578 /* Wait at most two seconds for calibration to complete. */ 7579 if (!(sc->sc_flags & IWN_FLAG_CALIB_DONE)) 7580 error = msleep(sc, &sc->sc_mtx, PCATCH, "iwncal", 2 * hz); 7581 return error; 7582 } 7583 7584 /* 7585 * Send calibration results to the runtime firmware. These results were 7586 * obtained on first boot from the initialization firmware. 7587 */ 7588 static int 7589 iwn5000_send_calibration(struct iwn_softc *sc) 7590 { 7591 int idx, error; 7592 7593 for (idx = 0; idx < IWN5000_PHY_CALIB_MAX_RESULT; idx++) { 7594 if (!(sc->base_params->calib_need & (1<<idx))) { 7595 DPRINTF(sc, IWN_DEBUG_CALIBRATE, 7596 "No need of calib %d\n", 7597 idx); 7598 continue; /* no need for this calib */ 7599 } 7600 if (sc->calibcmd[idx].buf == NULL) { 7601 DPRINTF(sc, IWN_DEBUG_CALIBRATE, 7602 "Need calib idx : %d but no available data\n", 7603 idx); 7604 continue; 7605 } 7606 7607 DPRINTF(sc, IWN_DEBUG_CALIBRATE, 7608 "send calibration result idx=%d len=%d\n", idx, 7609 sc->calibcmd[idx].len); 7610 error = iwn_cmd(sc, IWN_CMD_PHY_CALIB, sc->calibcmd[idx].buf, 7611 sc->calibcmd[idx].len, 0); 7612 if (error != 0) { 7613 device_printf(sc->sc_dev, 7614 "%s: could not send calibration result, error %d\n", 7615 __func__, error); 7616 return error; 7617 } 7618 } 7619 return 0; 7620 } 7621 7622 static int 7623 iwn5000_send_wimax_coex(struct iwn_softc *sc) 7624 { 7625 struct iwn5000_wimax_coex wimax; 7626 7627 #if 0 7628 if (sc->hw_type == IWN_HW_REV_TYPE_6050) { 7629 /* Enable WiMAX coexistence for combo adapters. */ 7630 wimax.flags = 7631 IWN_WIMAX_COEX_ASSOC_WA_UNMASK | 7632 IWN_WIMAX_COEX_UNASSOC_WA_UNMASK | 7633 IWN_WIMAX_COEX_STA_TABLE_VALID | 7634 IWN_WIMAX_COEX_ENABLE; 7635 memcpy(wimax.events, iwn6050_wimax_events, 7636 sizeof iwn6050_wimax_events); 7637 } else 7638 #endif 7639 { 7640 /* Disable WiMAX coexistence. */ 7641 wimax.flags = 0; 7642 memset(wimax.events, 0, sizeof wimax.events); 7643 } 7644 DPRINTF(sc, IWN_DEBUG_RESET, "%s: Configuring WiMAX coexistence\n", 7645 __func__); 7646 return iwn_cmd(sc, IWN5000_CMD_WIMAX_COEX, &wimax, sizeof wimax, 0); 7647 } 7648 7649 static int 7650 iwn5000_crystal_calib(struct iwn_softc *sc) 7651 { 7652 struct iwn5000_phy_calib_crystal cmd; 7653 7654 memset(&cmd, 0, sizeof cmd); 7655 cmd.code = IWN5000_PHY_CALIB_CRYSTAL; 7656 cmd.ngroups = 1; 7657 cmd.isvalid = 1; 7658 cmd.cap_pin[0] = le32toh(sc->eeprom_crystal) & 0xff; 7659 cmd.cap_pin[1] = (le32toh(sc->eeprom_crystal) >> 16) & 0xff; 7660 DPRINTF(sc, IWN_DEBUG_CALIBRATE, "sending crystal calibration %d, %d\n", 7661 cmd.cap_pin[0], cmd.cap_pin[1]); 7662 return iwn_cmd(sc, IWN_CMD_PHY_CALIB, &cmd, sizeof cmd, 0); 7663 } 7664 7665 static int 7666 iwn5000_temp_offset_calib(struct iwn_softc *sc) 7667 { 7668 struct iwn5000_phy_calib_temp_offset cmd; 7669 7670 memset(&cmd, 0, sizeof cmd); 7671 cmd.code = IWN5000_PHY_CALIB_TEMP_OFFSET; 7672 cmd.ngroups = 1; 7673 cmd.isvalid = 1; 7674 if (sc->eeprom_temp != 0) 7675 cmd.offset = htole16(sc->eeprom_temp); 7676 else 7677 cmd.offset = htole16(IWN_DEFAULT_TEMP_OFFSET); 7678 DPRINTF(sc, IWN_DEBUG_CALIBRATE, "setting radio sensor offset to %d\n", 7679 le16toh(cmd.offset)); 7680 return iwn_cmd(sc, IWN_CMD_PHY_CALIB, &cmd, sizeof cmd, 0); 7681 } 7682 7683 static int 7684 iwn5000_temp_offset_calibv2(struct iwn_softc *sc) 7685 { 7686 struct iwn5000_phy_calib_temp_offsetv2 cmd; 7687 7688 memset(&cmd, 0, sizeof cmd); 7689 cmd.code = IWN5000_PHY_CALIB_TEMP_OFFSET; 7690 cmd.ngroups = 1; 7691 cmd.isvalid = 1; 7692 if (sc->eeprom_temp != 0) { 7693 cmd.offset_low = htole16(sc->eeprom_temp); 7694 cmd.offset_high = htole16(sc->eeprom_temp_high); 7695 } else { 7696 cmd.offset_low = htole16(IWN_DEFAULT_TEMP_OFFSET); 7697 cmd.offset_high = htole16(IWN_DEFAULT_TEMP_OFFSET); 7698 } 7699 cmd.burnt_voltage_ref = htole16(sc->eeprom_voltage); 7700 7701 DPRINTF(sc, IWN_DEBUG_CALIBRATE, 7702 "setting radio sensor low offset to %d, high offset to %d, voltage to %d\n", 7703 le16toh(cmd.offset_low), 7704 le16toh(cmd.offset_high), 7705 le16toh(cmd.burnt_voltage_ref)); 7706 7707 return iwn_cmd(sc, IWN_CMD_PHY_CALIB, &cmd, sizeof cmd, 0); 7708 } 7709 7710 /* 7711 * This function is called after the runtime firmware notifies us of its 7712 * readiness (called in a process context). 7713 */ 7714 static int 7715 iwn4965_post_alive(struct iwn_softc *sc) 7716 { 7717 int error, qid; 7718 7719 if ((error = iwn_nic_lock(sc)) != 0) 7720 return error; 7721 7722 DPRINTF(sc, IWN_DEBUG_TRACE, "->Doing %s\n", __func__); 7723 7724 /* Clear TX scheduler state in SRAM. */ 7725 sc->sched_base = iwn_prph_read(sc, IWN_SCHED_SRAM_ADDR); 7726 iwn_mem_set_region_4(sc, sc->sched_base + IWN4965_SCHED_CTX_OFF, 0, 7727 IWN4965_SCHED_CTX_LEN / sizeof (uint32_t)); 7728 7729 /* Set physical address of TX scheduler rings (1KB aligned). */ 7730 iwn_prph_write(sc, IWN4965_SCHED_DRAM_ADDR, sc->sched_dma.paddr >> 10); 7731 7732 IWN_SETBITS(sc, IWN_FH_TX_CHICKEN, IWN_FH_TX_CHICKEN_SCHED_RETRY); 7733 7734 /* Disable chain mode for all our 16 queues. */ 7735 iwn_prph_write(sc, IWN4965_SCHED_QCHAIN_SEL, 0); 7736 7737 for (qid = 0; qid < IWN4965_NTXQUEUES; qid++) { 7738 iwn_prph_write(sc, IWN4965_SCHED_QUEUE_RDPTR(qid), 0); 7739 IWN_WRITE(sc, IWN_HBUS_TARG_WRPTR, qid << 8 | 0); 7740 7741 /* Set scheduler window size. */ 7742 iwn_mem_write(sc, sc->sched_base + 7743 IWN4965_SCHED_QUEUE_OFFSET(qid), IWN_SCHED_WINSZ); 7744 /* Set scheduler frame limit. */ 7745 iwn_mem_write(sc, sc->sched_base + 7746 IWN4965_SCHED_QUEUE_OFFSET(qid) + 4, 7747 IWN_SCHED_LIMIT << 16); 7748 } 7749 7750 /* Enable interrupts for all our 16 queues. */ 7751 iwn_prph_write(sc, IWN4965_SCHED_INTR_MASK, 0xffff); 7752 /* Identify TX FIFO rings (0-7). */ 7753 iwn_prph_write(sc, IWN4965_SCHED_TXFACT, 0xff); 7754 7755 /* Mark TX rings (4 EDCA + cmd + 2 HCCA) as active. */ 7756 for (qid = 0; qid < 7; qid++) { 7757 static uint8_t qid2fifo[] = { 3, 2, 1, 0, 4, 5, 6 }; 7758 iwn_prph_write(sc, IWN4965_SCHED_QUEUE_STATUS(qid), 7759 IWN4965_TXQ_STATUS_ACTIVE | qid2fifo[qid] << 1); 7760 } 7761 iwn_nic_unlock(sc); 7762 return 0; 7763 } 7764 7765 /* 7766 * This function is called after the initialization or runtime firmware 7767 * notifies us of its readiness (called in a process context). 7768 */ 7769 static int 7770 iwn5000_post_alive(struct iwn_softc *sc) 7771 { 7772 int error, qid; 7773 7774 DPRINTF(sc, IWN_DEBUG_TRACE, "->%s begin\n", __func__); 7775 7776 /* Switch to using ICT interrupt mode. */ 7777 iwn5000_ict_reset(sc); 7778 7779 if ((error = iwn_nic_lock(sc)) != 0){ 7780 DPRINTF(sc, IWN_DEBUG_TRACE, "->%s end in error\n", __func__); 7781 return error; 7782 } 7783 7784 /* Clear TX scheduler state in SRAM. */ 7785 sc->sched_base = iwn_prph_read(sc, IWN_SCHED_SRAM_ADDR); 7786 iwn_mem_set_region_4(sc, sc->sched_base + IWN5000_SCHED_CTX_OFF, 0, 7787 IWN5000_SCHED_CTX_LEN / sizeof (uint32_t)); 7788 7789 /* Set physical address of TX scheduler rings (1KB aligned). */ 7790 iwn_prph_write(sc, IWN5000_SCHED_DRAM_ADDR, sc->sched_dma.paddr >> 10); 7791 7792 IWN_SETBITS(sc, IWN_FH_TX_CHICKEN, IWN_FH_TX_CHICKEN_SCHED_RETRY); 7793 7794 /* Enable chain mode for all queues, except command queue. */ 7795 if (sc->sc_flags & IWN_FLAG_PAN_SUPPORT) 7796 iwn_prph_write(sc, IWN5000_SCHED_QCHAIN_SEL, 0xfffdf); 7797 else 7798 iwn_prph_write(sc, IWN5000_SCHED_QCHAIN_SEL, 0xfffef); 7799 iwn_prph_write(sc, IWN5000_SCHED_AGGR_SEL, 0); 7800 7801 for (qid = 0; qid < IWN5000_NTXQUEUES; qid++) { 7802 iwn_prph_write(sc, IWN5000_SCHED_QUEUE_RDPTR(qid), 0); 7803 IWN_WRITE(sc, IWN_HBUS_TARG_WRPTR, qid << 8 | 0); 7804 7805 iwn_mem_write(sc, sc->sched_base + 7806 IWN5000_SCHED_QUEUE_OFFSET(qid), 0); 7807 /* Set scheduler window size and frame limit. */ 7808 iwn_mem_write(sc, sc->sched_base + 7809 IWN5000_SCHED_QUEUE_OFFSET(qid) + 4, 7810 IWN_SCHED_LIMIT << 16 | IWN_SCHED_WINSZ); 7811 } 7812 7813 /* Enable interrupts for all our 20 queues. */ 7814 iwn_prph_write(sc, IWN5000_SCHED_INTR_MASK, 0xfffff); 7815 /* Identify TX FIFO rings (0-7). */ 7816 iwn_prph_write(sc, IWN5000_SCHED_TXFACT, 0xff); 7817 7818 /* Mark TX rings (4 EDCA + cmd + 2 HCCA) as active. */ 7819 if (sc->sc_flags & IWN_FLAG_PAN_SUPPORT) { 7820 /* Mark TX rings as active. */ 7821 for (qid = 0; qid < 11; qid++) { 7822 static uint8_t qid2fifo[] = { 3, 2, 1, 0, 0, 4, 2, 5, 4, 7, 5 }; 7823 iwn_prph_write(sc, IWN5000_SCHED_QUEUE_STATUS(qid), 7824 IWN5000_TXQ_STATUS_ACTIVE | qid2fifo[qid]); 7825 } 7826 } else { 7827 /* Mark TX rings (4 EDCA + cmd + 2 HCCA) as active. */ 7828 for (qid = 0; qid < 7; qid++) { 7829 static uint8_t qid2fifo[] = { 3, 2, 1, 0, 7, 5, 6 }; 7830 iwn_prph_write(sc, IWN5000_SCHED_QUEUE_STATUS(qid), 7831 IWN5000_TXQ_STATUS_ACTIVE | qid2fifo[qid]); 7832 } 7833 } 7834 iwn_nic_unlock(sc); 7835 7836 /* Configure WiMAX coexistence for combo adapters. */ 7837 error = iwn5000_send_wimax_coex(sc); 7838 if (error != 0) { 7839 device_printf(sc->sc_dev, 7840 "%s: could not configure WiMAX coexistence, error %d\n", 7841 __func__, error); 7842 return error; 7843 } 7844 if (sc->hw_type != IWN_HW_REV_TYPE_5150) { 7845 /* Perform crystal calibration. */ 7846 error = iwn5000_crystal_calib(sc); 7847 if (error != 0) { 7848 device_printf(sc->sc_dev, 7849 "%s: crystal calibration failed, error %d\n", 7850 __func__, error); 7851 return error; 7852 } 7853 } 7854 if (!(sc->sc_flags & IWN_FLAG_CALIB_DONE)) { 7855 /* Query calibration from the initialization firmware. */ 7856 if ((error = iwn5000_query_calibration(sc)) != 0) { 7857 device_printf(sc->sc_dev, 7858 "%s: could not query calibration, error %d\n", 7859 __func__, error); 7860 return error; 7861 } 7862 /* 7863 * We have the calibration results now, reboot with the 7864 * runtime firmware (call ourselves recursively!) 7865 */ 7866 iwn_hw_stop(sc); 7867 error = iwn_hw_init(sc); 7868 } else { 7869 /* Send calibration results to runtime firmware. */ 7870 error = iwn5000_send_calibration(sc); 7871 } 7872 7873 DPRINTF(sc, IWN_DEBUG_TRACE, "->%s: end\n",__func__); 7874 7875 return error; 7876 } 7877 7878 /* 7879 * The firmware boot code is small and is intended to be copied directly into 7880 * the NIC internal memory (no DMA transfer). 7881 */ 7882 static int 7883 iwn4965_load_bootcode(struct iwn_softc *sc, const uint8_t *ucode, int size) 7884 { 7885 int error, ntries; 7886 7887 size /= sizeof (uint32_t); 7888 7889 if ((error = iwn_nic_lock(sc)) != 0) 7890 return error; 7891 7892 /* Copy microcode image into NIC memory. */ 7893 iwn_prph_write_region_4(sc, IWN_BSM_SRAM_BASE, 7894 (const uint32_t *)ucode, size); 7895 7896 iwn_prph_write(sc, IWN_BSM_WR_MEM_SRC, 0); 7897 iwn_prph_write(sc, IWN_BSM_WR_MEM_DST, IWN_FW_TEXT_BASE); 7898 iwn_prph_write(sc, IWN_BSM_WR_DWCOUNT, size); 7899 7900 /* Start boot load now. */ 7901 iwn_prph_write(sc, IWN_BSM_WR_CTRL, IWN_BSM_WR_CTRL_START); 7902 7903 /* Wait for transfer to complete. */ 7904 for (ntries = 0; ntries < 1000; ntries++) { 7905 if (!(iwn_prph_read(sc, IWN_BSM_WR_CTRL) & 7906 IWN_BSM_WR_CTRL_START)) 7907 break; 7908 DELAY(10); 7909 } 7910 if (ntries == 1000) { 7911 device_printf(sc->sc_dev, "%s: could not load boot firmware\n", 7912 __func__); 7913 iwn_nic_unlock(sc); 7914 return ETIMEDOUT; 7915 } 7916 7917 /* Enable boot after power up. */ 7918 iwn_prph_write(sc, IWN_BSM_WR_CTRL, IWN_BSM_WR_CTRL_START_EN); 7919 7920 iwn_nic_unlock(sc); 7921 return 0; 7922 } 7923 7924 static int 7925 iwn4965_load_firmware(struct iwn_softc *sc) 7926 { 7927 struct iwn_fw_info *fw = &sc->fw; 7928 struct iwn_dma_info *dma = &sc->fw_dma; 7929 int error; 7930 7931 /* Copy initialization sections into pre-allocated DMA-safe memory. */ 7932 memcpy(dma->vaddr, fw->init.data, fw->init.datasz); 7933 bus_dmamap_sync(dma->tag, dma->map, BUS_DMASYNC_PREWRITE); 7934 memcpy(dma->vaddr + IWN4965_FW_DATA_MAXSZ, 7935 fw->init.text, fw->init.textsz); 7936 bus_dmamap_sync(dma->tag, dma->map, BUS_DMASYNC_PREWRITE); 7937 7938 /* Tell adapter where to find initialization sections. */ 7939 if ((error = iwn_nic_lock(sc)) != 0) 7940 return error; 7941 iwn_prph_write(sc, IWN_BSM_DRAM_DATA_ADDR, dma->paddr >> 4); 7942 iwn_prph_write(sc, IWN_BSM_DRAM_DATA_SIZE, fw->init.datasz); 7943 iwn_prph_write(sc, IWN_BSM_DRAM_TEXT_ADDR, 7944 (dma->paddr + IWN4965_FW_DATA_MAXSZ) >> 4); 7945 iwn_prph_write(sc, IWN_BSM_DRAM_TEXT_SIZE, fw->init.textsz); 7946 iwn_nic_unlock(sc); 7947 7948 /* Load firmware boot code. */ 7949 error = iwn4965_load_bootcode(sc, fw->boot.text, fw->boot.textsz); 7950 if (error != 0) { 7951 device_printf(sc->sc_dev, "%s: could not load boot firmware\n", 7952 __func__); 7953 return error; 7954 } 7955 /* Now press "execute". */ 7956 IWN_WRITE(sc, IWN_RESET, 0); 7957 7958 /* Wait at most one second for first alive notification. */ 7959 if ((error = msleep(sc, &sc->sc_mtx, PCATCH, "iwninit", hz)) != 0) { 7960 device_printf(sc->sc_dev, 7961 "%s: timeout waiting for adapter to initialize, error %d\n", 7962 __func__, error); 7963 return error; 7964 } 7965 7966 /* Retrieve current temperature for initial TX power calibration. */ 7967 sc->rawtemp = sc->ucode_info.temp[3].chan20MHz; 7968 sc->temp = iwn4965_get_temperature(sc); 7969 7970 /* Copy runtime sections into pre-allocated DMA-safe memory. */ 7971 memcpy(dma->vaddr, fw->main.data, fw->main.datasz); 7972 bus_dmamap_sync(dma->tag, dma->map, BUS_DMASYNC_PREWRITE); 7973 memcpy(dma->vaddr + IWN4965_FW_DATA_MAXSZ, 7974 fw->main.text, fw->main.textsz); 7975 bus_dmamap_sync(dma->tag, dma->map, BUS_DMASYNC_PREWRITE); 7976 7977 /* Tell adapter where to find runtime sections. */ 7978 if ((error = iwn_nic_lock(sc)) != 0) 7979 return error; 7980 iwn_prph_write(sc, IWN_BSM_DRAM_DATA_ADDR, dma->paddr >> 4); 7981 iwn_prph_write(sc, IWN_BSM_DRAM_DATA_SIZE, fw->main.datasz); 7982 iwn_prph_write(sc, IWN_BSM_DRAM_TEXT_ADDR, 7983 (dma->paddr + IWN4965_FW_DATA_MAXSZ) >> 4); 7984 iwn_prph_write(sc, IWN_BSM_DRAM_TEXT_SIZE, 7985 IWN_FW_UPDATED | fw->main.textsz); 7986 iwn_nic_unlock(sc); 7987 7988 return 0; 7989 } 7990 7991 static int 7992 iwn5000_load_firmware_section(struct iwn_softc *sc, uint32_t dst, 7993 const uint8_t *section, int size) 7994 { 7995 struct iwn_dma_info *dma = &sc->fw_dma; 7996 int error; 7997 7998 DPRINTF(sc, IWN_DEBUG_TRACE, "->Doing %s\n", __func__); 7999 8000 /* Copy firmware section into pre-allocated DMA-safe memory. */ 8001 memcpy(dma->vaddr, section, size); 8002 bus_dmamap_sync(dma->tag, dma->map, BUS_DMASYNC_PREWRITE); 8003 8004 if ((error = iwn_nic_lock(sc)) != 0) 8005 return error; 8006 8007 IWN_WRITE(sc, IWN_FH_TX_CONFIG(IWN_SRVC_DMACHNL), 8008 IWN_FH_TX_CONFIG_DMA_PAUSE); 8009 8010 IWN_WRITE(sc, IWN_FH_SRAM_ADDR(IWN_SRVC_DMACHNL), dst); 8011 IWN_WRITE(sc, IWN_FH_TFBD_CTRL0(IWN_SRVC_DMACHNL), 8012 IWN_LOADDR(dma->paddr)); 8013 IWN_WRITE(sc, IWN_FH_TFBD_CTRL1(IWN_SRVC_DMACHNL), 8014 IWN_HIADDR(dma->paddr) << 28 | size); 8015 IWN_WRITE(sc, IWN_FH_TXBUF_STATUS(IWN_SRVC_DMACHNL), 8016 IWN_FH_TXBUF_STATUS_TBNUM(1) | 8017 IWN_FH_TXBUF_STATUS_TBIDX(1) | 8018 IWN_FH_TXBUF_STATUS_TFBD_VALID); 8019 8020 /* Kick Flow Handler to start DMA transfer. */ 8021 IWN_WRITE(sc, IWN_FH_TX_CONFIG(IWN_SRVC_DMACHNL), 8022 IWN_FH_TX_CONFIG_DMA_ENA | IWN_FH_TX_CONFIG_CIRQ_HOST_ENDTFD); 8023 8024 iwn_nic_unlock(sc); 8025 8026 /* Wait at most five seconds for FH DMA transfer to complete. */ 8027 return msleep(sc, &sc->sc_mtx, PCATCH, "iwninit", 5 * hz); 8028 } 8029 8030 static int 8031 iwn5000_load_firmware(struct iwn_softc *sc) 8032 { 8033 struct iwn_fw_part *fw; 8034 int error; 8035 8036 DPRINTF(sc, IWN_DEBUG_TRACE, "->Doing %s\n", __func__); 8037 8038 /* Load the initialization firmware on first boot only. */ 8039 fw = (sc->sc_flags & IWN_FLAG_CALIB_DONE) ? 8040 &sc->fw.main : &sc->fw.init; 8041 8042 error = iwn5000_load_firmware_section(sc, IWN_FW_TEXT_BASE, 8043 fw->text, fw->textsz); 8044 if (error != 0) { 8045 device_printf(sc->sc_dev, 8046 "%s: could not load firmware %s section, error %d\n", 8047 __func__, ".text", error); 8048 return error; 8049 } 8050 error = iwn5000_load_firmware_section(sc, IWN_FW_DATA_BASE, 8051 fw->data, fw->datasz); 8052 if (error != 0) { 8053 device_printf(sc->sc_dev, 8054 "%s: could not load firmware %s section, error %d\n", 8055 __func__, ".data", error); 8056 return error; 8057 } 8058 8059 /* Now press "execute". */ 8060 IWN_WRITE(sc, IWN_RESET, 0); 8061 return 0; 8062 } 8063 8064 /* 8065 * Extract text and data sections from a legacy firmware image. 8066 */ 8067 static int 8068 iwn_read_firmware_leg(struct iwn_softc *sc, struct iwn_fw_info *fw) 8069 { 8070 const uint32_t *ptr; 8071 size_t hdrlen = 24; 8072 uint32_t rev; 8073 8074 ptr = (const uint32_t *)fw->data; 8075 rev = le32toh(*ptr++); 8076 8077 sc->ucode_rev = rev; 8078 8079 /* Check firmware API version. */ 8080 if (IWN_FW_API(rev) <= 1) { 8081 device_printf(sc->sc_dev, 8082 "%s: bad firmware, need API version >=2\n", __func__); 8083 return EINVAL; 8084 } 8085 if (IWN_FW_API(rev) >= 3) { 8086 /* Skip build number (version 2 header). */ 8087 hdrlen += 4; 8088 ptr++; 8089 } 8090 if (fw->size < hdrlen) { 8091 device_printf(sc->sc_dev, "%s: firmware too short: %zu bytes\n", 8092 __func__, fw->size); 8093 return EINVAL; 8094 } 8095 fw->main.textsz = le32toh(*ptr++); 8096 fw->main.datasz = le32toh(*ptr++); 8097 fw->init.textsz = le32toh(*ptr++); 8098 fw->init.datasz = le32toh(*ptr++); 8099 fw->boot.textsz = le32toh(*ptr++); 8100 8101 /* Check that all firmware sections fit. */ 8102 if (fw->size < hdrlen + fw->main.textsz + fw->main.datasz + 8103 fw->init.textsz + fw->init.datasz + fw->boot.textsz) { 8104 device_printf(sc->sc_dev, "%s: firmware too short: %zu bytes\n", 8105 __func__, fw->size); 8106 return EINVAL; 8107 } 8108 8109 /* Get pointers to firmware sections. */ 8110 fw->main.text = (const uint8_t *)ptr; 8111 fw->main.data = fw->main.text + fw->main.textsz; 8112 fw->init.text = fw->main.data + fw->main.datasz; 8113 fw->init.data = fw->init.text + fw->init.textsz; 8114 fw->boot.text = fw->init.data + fw->init.datasz; 8115 return 0; 8116 } 8117 8118 /* 8119 * Extract text and data sections from a TLV firmware image. 8120 */ 8121 static int 8122 iwn_read_firmware_tlv(struct iwn_softc *sc, struct iwn_fw_info *fw, 8123 uint16_t alt) 8124 { 8125 const struct iwn_fw_tlv_hdr *hdr; 8126 const struct iwn_fw_tlv *tlv; 8127 const uint8_t *ptr, *end; 8128 uint64_t altmask; 8129 uint32_t len, tmp; 8130 8131 if (fw->size < sizeof (*hdr)) { 8132 device_printf(sc->sc_dev, "%s: firmware too short: %zu bytes\n", 8133 __func__, fw->size); 8134 return EINVAL; 8135 } 8136 hdr = (const struct iwn_fw_tlv_hdr *)fw->data; 8137 if (hdr->signature != htole32(IWN_FW_SIGNATURE)) { 8138 device_printf(sc->sc_dev, "%s: bad firmware signature 0x%08x\n", 8139 __func__, le32toh(hdr->signature)); 8140 return EINVAL; 8141 } 8142 DPRINTF(sc, IWN_DEBUG_RESET, "FW: \"%.64s\", build 0x%x\n", hdr->descr, 8143 le32toh(hdr->build)); 8144 sc->ucode_rev = le32toh(hdr->rev); 8145 8146 /* 8147 * Select the closest supported alternative that is less than 8148 * or equal to the specified one. 8149 */ 8150 altmask = le64toh(hdr->altmask); 8151 while (alt > 0 && !(altmask & (1ULL << alt))) 8152 alt--; /* Downgrade. */ 8153 DPRINTF(sc, IWN_DEBUG_RESET, "using alternative %d\n", alt); 8154 8155 ptr = (const uint8_t *)(hdr + 1); 8156 end = (const uint8_t *)(fw->data + fw->size); 8157 8158 /* Parse type-length-value fields. */ 8159 while (ptr + sizeof (*tlv) <= end) { 8160 tlv = (const struct iwn_fw_tlv *)ptr; 8161 len = le32toh(tlv->len); 8162 8163 ptr += sizeof (*tlv); 8164 if (ptr + len > end) { 8165 device_printf(sc->sc_dev, 8166 "%s: firmware too short: %zu bytes\n", __func__, 8167 fw->size); 8168 return EINVAL; 8169 } 8170 /* Skip other alternatives. */ 8171 if (tlv->alt != 0 && tlv->alt != htole16(alt)) 8172 goto next; 8173 8174 switch (le16toh(tlv->type)) { 8175 case IWN_FW_TLV_MAIN_TEXT: 8176 fw->main.text = ptr; 8177 fw->main.textsz = len; 8178 break; 8179 case IWN_FW_TLV_MAIN_DATA: 8180 fw->main.data = ptr; 8181 fw->main.datasz = len; 8182 break; 8183 case IWN_FW_TLV_INIT_TEXT: 8184 fw->init.text = ptr; 8185 fw->init.textsz = len; 8186 break; 8187 case IWN_FW_TLV_INIT_DATA: 8188 fw->init.data = ptr; 8189 fw->init.datasz = len; 8190 break; 8191 case IWN_FW_TLV_BOOT_TEXT: 8192 fw->boot.text = ptr; 8193 fw->boot.textsz = len; 8194 break; 8195 case IWN_FW_TLV_ENH_SENS: 8196 if (!len) 8197 sc->sc_flags |= IWN_FLAG_ENH_SENS; 8198 break; 8199 case IWN_FW_TLV_PHY_CALIB: 8200 tmp = le32toh(*ptr); 8201 if (tmp < 253) { 8202 sc->reset_noise_gain = tmp; 8203 sc->noise_gain = tmp + 1; 8204 } 8205 break; 8206 case IWN_FW_TLV_PAN: 8207 sc->sc_flags |= IWN_FLAG_PAN_SUPPORT; 8208 DPRINTF(sc, IWN_DEBUG_RESET, 8209 "PAN Support found: %d\n", 1); 8210 break; 8211 case IWN_FW_TLV_FLAGS: 8212 if (len < sizeof(uint32_t)) 8213 break; 8214 if (len % sizeof(uint32_t)) 8215 break; 8216 sc->tlv_feature_flags = le32toh(*ptr); 8217 DPRINTF(sc, IWN_DEBUG_RESET, 8218 "%s: feature: 0x%08x\n", 8219 __func__, 8220 sc->tlv_feature_flags); 8221 break; 8222 case IWN_FW_TLV_PBREQ_MAXLEN: 8223 case IWN_FW_TLV_RUNT_EVTLOG_PTR: 8224 case IWN_FW_TLV_RUNT_EVTLOG_SIZE: 8225 case IWN_FW_TLV_RUNT_ERRLOG_PTR: 8226 case IWN_FW_TLV_INIT_EVTLOG_PTR: 8227 case IWN_FW_TLV_INIT_EVTLOG_SIZE: 8228 case IWN_FW_TLV_INIT_ERRLOG_PTR: 8229 case IWN_FW_TLV_WOWLAN_INST: 8230 case IWN_FW_TLV_WOWLAN_DATA: 8231 DPRINTF(sc, IWN_DEBUG_RESET, 8232 "TLV type %d recognized but not handled\n", 8233 le16toh(tlv->type)); 8234 break; 8235 default: 8236 DPRINTF(sc, IWN_DEBUG_RESET, 8237 "TLV type %d not handled\n", le16toh(tlv->type)); 8238 break; 8239 } 8240 next: /* TLV fields are 32-bit aligned. */ 8241 ptr += (len + 3) & ~3; 8242 } 8243 return 0; 8244 } 8245 8246 static int 8247 iwn_read_firmware(struct iwn_softc *sc) 8248 { 8249 struct iwn_fw_info *fw = &sc->fw; 8250 int error; 8251 8252 DPRINTF(sc, IWN_DEBUG_TRACE, "->Doing %s\n", __func__); 8253 8254 IWN_UNLOCK(sc); 8255 8256 memset(fw, 0, sizeof (*fw)); 8257 8258 /* Read firmware image from filesystem. */ 8259 sc->fw_fp = firmware_get(sc->fwname); 8260 if (sc->fw_fp == NULL) { 8261 device_printf(sc->sc_dev, "%s: could not read firmware %s\n", 8262 __func__, sc->fwname); 8263 IWN_LOCK(sc); 8264 return EINVAL; 8265 } 8266 IWN_LOCK(sc); 8267 8268 fw->size = sc->fw_fp->datasize; 8269 fw->data = (const uint8_t *)sc->fw_fp->data; 8270 if (fw->size < sizeof (uint32_t)) { 8271 device_printf(sc->sc_dev, "%s: firmware too short: %zu bytes\n", 8272 __func__, fw->size); 8273 error = EINVAL; 8274 goto fail; 8275 } 8276 8277 /* Retrieve text and data sections. */ 8278 if (*(const uint32_t *)fw->data != 0) /* Legacy image. */ 8279 error = iwn_read_firmware_leg(sc, fw); 8280 else 8281 error = iwn_read_firmware_tlv(sc, fw, 1); 8282 if (error != 0) { 8283 device_printf(sc->sc_dev, 8284 "%s: could not read firmware sections, error %d\n", 8285 __func__, error); 8286 goto fail; 8287 } 8288 8289 device_printf(sc->sc_dev, "%s: ucode rev=0x%08x\n", __func__, sc->ucode_rev); 8290 8291 /* Make sure text and data sections fit in hardware memory. */ 8292 if (fw->main.textsz > sc->fw_text_maxsz || 8293 fw->main.datasz > sc->fw_data_maxsz || 8294 fw->init.textsz > sc->fw_text_maxsz || 8295 fw->init.datasz > sc->fw_data_maxsz || 8296 fw->boot.textsz > IWN_FW_BOOT_TEXT_MAXSZ || 8297 (fw->boot.textsz & 3) != 0) { 8298 device_printf(sc->sc_dev, "%s: firmware sections too large\n", 8299 __func__); 8300 error = EINVAL; 8301 goto fail; 8302 } 8303 8304 /* We can proceed with loading the firmware. */ 8305 return 0; 8306 8307 fail: iwn_unload_firmware(sc); 8308 return error; 8309 } 8310 8311 static void 8312 iwn_unload_firmware(struct iwn_softc *sc) 8313 { 8314 firmware_put(sc->fw_fp, FIRMWARE_UNLOAD); 8315 sc->fw_fp = NULL; 8316 } 8317 8318 static int 8319 iwn_clock_wait(struct iwn_softc *sc) 8320 { 8321 int ntries; 8322 8323 /* Set "initialization complete" bit. */ 8324 IWN_SETBITS(sc, IWN_GP_CNTRL, IWN_GP_CNTRL_INIT_DONE); 8325 8326 /* Wait for clock stabilization. */ 8327 for (ntries = 0; ntries < 2500; ntries++) { 8328 if (IWN_READ(sc, IWN_GP_CNTRL) & IWN_GP_CNTRL_MAC_CLOCK_READY) 8329 return 0; 8330 DELAY(10); 8331 } 8332 device_printf(sc->sc_dev, 8333 "%s: timeout waiting for clock stabilization\n", __func__); 8334 return ETIMEDOUT; 8335 } 8336 8337 static int 8338 iwn_apm_init(struct iwn_softc *sc) 8339 { 8340 uint32_t reg; 8341 int error; 8342 8343 DPRINTF(sc, IWN_DEBUG_TRACE, "->Doing %s\n", __func__); 8344 8345 /* Disable L0s exit timer (NMI bug workaround). */ 8346 IWN_SETBITS(sc, IWN_GIO_CHICKEN, IWN_GIO_CHICKEN_DIS_L0S_TIMER); 8347 /* Don't wait for ICH L0s (ICH bug workaround). */ 8348 IWN_SETBITS(sc, IWN_GIO_CHICKEN, IWN_GIO_CHICKEN_L1A_NO_L0S_RX); 8349 8350 /* Set FH wait threshold to max (HW bug under stress workaround). */ 8351 IWN_SETBITS(sc, IWN_DBG_HPET_MEM, 0xffff0000); 8352 8353 /* Enable HAP INTA to move adapter from L1a to L0s. */ 8354 IWN_SETBITS(sc, IWN_HW_IF_CONFIG, IWN_HW_IF_CONFIG_HAP_WAKE_L1A); 8355 8356 /* Retrieve PCIe Active State Power Management (ASPM). */ 8357 reg = pci_read_config(sc->sc_dev, sc->sc_cap_off + PCIER_LINK_CTL, 4); 8358 /* Workaround for HW instability in PCIe L0->L0s->L1 transition. */ 8359 if (reg & PCIEM_LINK_CTL_ASPMC_L1) /* L1 Entry enabled. */ 8360 IWN_SETBITS(sc, IWN_GIO, IWN_GIO_L0S_ENA); 8361 else 8362 IWN_CLRBITS(sc, IWN_GIO, IWN_GIO_L0S_ENA); 8363 8364 if (sc->base_params->pll_cfg_val) 8365 IWN_SETBITS(sc, IWN_ANA_PLL, sc->base_params->pll_cfg_val); 8366 8367 /* Wait for clock stabilization before accessing prph. */ 8368 if ((error = iwn_clock_wait(sc)) != 0) 8369 return error; 8370 8371 if ((error = iwn_nic_lock(sc)) != 0) 8372 return error; 8373 if (sc->hw_type == IWN_HW_REV_TYPE_4965) { 8374 /* Enable DMA and BSM (Bootstrap State Machine). */ 8375 iwn_prph_write(sc, IWN_APMG_CLK_EN, 8376 IWN_APMG_CLK_CTRL_DMA_CLK_RQT | 8377 IWN_APMG_CLK_CTRL_BSM_CLK_RQT); 8378 } else { 8379 /* Enable DMA. */ 8380 iwn_prph_write(sc, IWN_APMG_CLK_EN, 8381 IWN_APMG_CLK_CTRL_DMA_CLK_RQT); 8382 } 8383 DELAY(20); 8384 /* Disable L1-Active. */ 8385 iwn_prph_setbits(sc, IWN_APMG_PCI_STT, IWN_APMG_PCI_STT_L1A_DIS); 8386 iwn_nic_unlock(sc); 8387 8388 return 0; 8389 } 8390 8391 static void 8392 iwn_apm_stop_master(struct iwn_softc *sc) 8393 { 8394 int ntries; 8395 8396 /* Stop busmaster DMA activity. */ 8397 IWN_SETBITS(sc, IWN_RESET, IWN_RESET_STOP_MASTER); 8398 for (ntries = 0; ntries < 100; ntries++) { 8399 if (IWN_READ(sc, IWN_RESET) & IWN_RESET_MASTER_DISABLED) 8400 return; 8401 DELAY(10); 8402 } 8403 device_printf(sc->sc_dev, "%s: timeout waiting for master\n", __func__); 8404 } 8405 8406 static void 8407 iwn_apm_stop(struct iwn_softc *sc) 8408 { 8409 iwn_apm_stop_master(sc); 8410 8411 /* Reset the entire device. */ 8412 IWN_SETBITS(sc, IWN_RESET, IWN_RESET_SW); 8413 DELAY(10); 8414 /* Clear "initialization complete" bit. */ 8415 IWN_CLRBITS(sc, IWN_GP_CNTRL, IWN_GP_CNTRL_INIT_DONE); 8416 } 8417 8418 static int 8419 iwn4965_nic_config(struct iwn_softc *sc) 8420 { 8421 DPRINTF(sc, IWN_DEBUG_TRACE, "->Doing %s\n", __func__); 8422 8423 if (IWN_RFCFG_TYPE(sc->rfcfg) == 1) { 8424 /* 8425 * I don't believe this to be correct but this is what the 8426 * vendor driver is doing. Probably the bits should not be 8427 * shifted in IWN_RFCFG_*. 8428 */ 8429 IWN_SETBITS(sc, IWN_HW_IF_CONFIG, 8430 IWN_RFCFG_TYPE(sc->rfcfg) | 8431 IWN_RFCFG_STEP(sc->rfcfg) | 8432 IWN_RFCFG_DASH(sc->rfcfg)); 8433 } 8434 IWN_SETBITS(sc, IWN_HW_IF_CONFIG, 8435 IWN_HW_IF_CONFIG_RADIO_SI | IWN_HW_IF_CONFIG_MAC_SI); 8436 return 0; 8437 } 8438 8439 static int 8440 iwn5000_nic_config(struct iwn_softc *sc) 8441 { 8442 uint32_t tmp; 8443 int error; 8444 8445 DPRINTF(sc, IWN_DEBUG_TRACE, "->Doing %s\n", __func__); 8446 8447 if (IWN_RFCFG_TYPE(sc->rfcfg) < 3) { 8448 IWN_SETBITS(sc, IWN_HW_IF_CONFIG, 8449 IWN_RFCFG_TYPE(sc->rfcfg) | 8450 IWN_RFCFG_STEP(sc->rfcfg) | 8451 IWN_RFCFG_DASH(sc->rfcfg)); 8452 } 8453 IWN_SETBITS(sc, IWN_HW_IF_CONFIG, 8454 IWN_HW_IF_CONFIG_RADIO_SI | IWN_HW_IF_CONFIG_MAC_SI); 8455 8456 if ((error = iwn_nic_lock(sc)) != 0) 8457 return error; 8458 iwn_prph_setbits(sc, IWN_APMG_PS, IWN_APMG_PS_EARLY_PWROFF_DIS); 8459 8460 if (sc->hw_type == IWN_HW_REV_TYPE_1000) { 8461 /* 8462 * Select first Switching Voltage Regulator (1.32V) to 8463 * solve a stability issue related to noisy DC2DC line 8464 * in the silicon of 1000 Series. 8465 */ 8466 tmp = iwn_prph_read(sc, IWN_APMG_DIGITAL_SVR); 8467 tmp &= ~IWN_APMG_DIGITAL_SVR_VOLTAGE_MASK; 8468 tmp |= IWN_APMG_DIGITAL_SVR_VOLTAGE_1_32; 8469 iwn_prph_write(sc, IWN_APMG_DIGITAL_SVR, tmp); 8470 } 8471 iwn_nic_unlock(sc); 8472 8473 if (sc->sc_flags & IWN_FLAG_INTERNAL_PA) { 8474 /* Use internal power amplifier only. */ 8475 IWN_WRITE(sc, IWN_GP_DRIVER, IWN_GP_DRIVER_RADIO_2X2_IPA); 8476 } 8477 if (sc->base_params->additional_nic_config && sc->calib_ver >= 6) { 8478 /* Indicate that ROM calibration version is >=6. */ 8479 IWN_SETBITS(sc, IWN_GP_DRIVER, IWN_GP_DRIVER_CALIB_VER6); 8480 } 8481 if (sc->base_params->additional_gp_drv_bit) 8482 IWN_SETBITS(sc, IWN_GP_DRIVER, 8483 sc->base_params->additional_gp_drv_bit); 8484 return 0; 8485 } 8486 8487 /* 8488 * Take NIC ownership over Intel Active Management Technology (AMT). 8489 */ 8490 static int 8491 iwn_hw_prepare(struct iwn_softc *sc) 8492 { 8493 int ntries; 8494 8495 DPRINTF(sc, IWN_DEBUG_TRACE, "->Doing %s\n", __func__); 8496 8497 /* Check if hardware is ready. */ 8498 IWN_SETBITS(sc, IWN_HW_IF_CONFIG, IWN_HW_IF_CONFIG_NIC_READY); 8499 for (ntries = 0; ntries < 5; ntries++) { 8500 if (IWN_READ(sc, IWN_HW_IF_CONFIG) & 8501 IWN_HW_IF_CONFIG_NIC_READY) 8502 return 0; 8503 DELAY(10); 8504 } 8505 8506 /* Hardware not ready, force into ready state. */ 8507 IWN_SETBITS(sc, IWN_HW_IF_CONFIG, IWN_HW_IF_CONFIG_PREPARE); 8508 for (ntries = 0; ntries < 15000; ntries++) { 8509 if (!(IWN_READ(sc, IWN_HW_IF_CONFIG) & 8510 IWN_HW_IF_CONFIG_PREPARE_DONE)) 8511 break; 8512 DELAY(10); 8513 } 8514 if (ntries == 15000) 8515 return ETIMEDOUT; 8516 8517 /* Hardware should be ready now. */ 8518 IWN_SETBITS(sc, IWN_HW_IF_CONFIG, IWN_HW_IF_CONFIG_NIC_READY); 8519 for (ntries = 0; ntries < 5; ntries++) { 8520 if (IWN_READ(sc, IWN_HW_IF_CONFIG) & 8521 IWN_HW_IF_CONFIG_NIC_READY) 8522 return 0; 8523 DELAY(10); 8524 } 8525 return ETIMEDOUT; 8526 } 8527 8528 static int 8529 iwn_hw_init(struct iwn_softc *sc) 8530 { 8531 struct iwn_ops *ops = &sc->ops; 8532 int error, chnl, qid; 8533 8534 DPRINTF(sc, IWN_DEBUG_TRACE, "->%s begin\n", __func__); 8535 8536 /* Clear pending interrupts. */ 8537 IWN_WRITE(sc, IWN_INT, 0xffffffff); 8538 8539 if ((error = iwn_apm_init(sc)) != 0) { 8540 device_printf(sc->sc_dev, 8541 "%s: could not power ON adapter, error %d\n", __func__, 8542 error); 8543 return error; 8544 } 8545 8546 /* Select VMAIN power source. */ 8547 if ((error = iwn_nic_lock(sc)) != 0) 8548 return error; 8549 iwn_prph_clrbits(sc, IWN_APMG_PS, IWN_APMG_PS_PWR_SRC_MASK); 8550 iwn_nic_unlock(sc); 8551 8552 /* Perform adapter-specific initialization. */ 8553 if ((error = ops->nic_config(sc)) != 0) 8554 return error; 8555 8556 /* Initialize RX ring. */ 8557 if ((error = iwn_nic_lock(sc)) != 0) 8558 return error; 8559 IWN_WRITE(sc, IWN_FH_RX_CONFIG, 0); 8560 IWN_WRITE(sc, IWN_FH_RX_WPTR, 0); 8561 /* Set physical address of RX ring (256-byte aligned). */ 8562 IWN_WRITE(sc, IWN_FH_RX_BASE, sc->rxq.desc_dma.paddr >> 8); 8563 /* Set physical address of RX status (16-byte aligned). */ 8564 IWN_WRITE(sc, IWN_FH_STATUS_WPTR, sc->rxq.stat_dma.paddr >> 4); 8565 /* Enable RX. */ 8566 IWN_WRITE(sc, IWN_FH_RX_CONFIG, 8567 IWN_FH_RX_CONFIG_ENA | 8568 IWN_FH_RX_CONFIG_IGN_RXF_EMPTY | /* HW bug workaround */ 8569 IWN_FH_RX_CONFIG_IRQ_DST_HOST | 8570 IWN_FH_RX_CONFIG_SINGLE_FRAME | 8571 IWN_FH_RX_CONFIG_RB_TIMEOUT(0) | 8572 IWN_FH_RX_CONFIG_NRBD(IWN_RX_RING_COUNT_LOG)); 8573 iwn_nic_unlock(sc); 8574 IWN_WRITE(sc, IWN_FH_RX_WPTR, (IWN_RX_RING_COUNT - 1) & ~7); 8575 8576 if ((error = iwn_nic_lock(sc)) != 0) 8577 return error; 8578 8579 /* Initialize TX scheduler. */ 8580 iwn_prph_write(sc, sc->sched_txfact_addr, 0); 8581 8582 /* Set physical address of "keep warm" page (16-byte aligned). */ 8583 IWN_WRITE(sc, IWN_FH_KW_ADDR, sc->kw_dma.paddr >> 4); 8584 8585 /* Initialize TX rings. */ 8586 for (qid = 0; qid < sc->ntxqs; qid++) { 8587 struct iwn_tx_ring *txq = &sc->txq[qid]; 8588 8589 /* Set physical address of TX ring (256-byte aligned). */ 8590 IWN_WRITE(sc, IWN_FH_CBBC_QUEUE(qid), 8591 txq->desc_dma.paddr >> 8); 8592 } 8593 iwn_nic_unlock(sc); 8594 8595 /* Enable DMA channels. */ 8596 for (chnl = 0; chnl < sc->ndmachnls; chnl++) { 8597 IWN_WRITE(sc, IWN_FH_TX_CONFIG(chnl), 8598 IWN_FH_TX_CONFIG_DMA_ENA | 8599 IWN_FH_TX_CONFIG_DMA_CREDIT_ENA); 8600 } 8601 8602 /* Clear "radio off" and "commands blocked" bits. */ 8603 IWN_WRITE(sc, IWN_UCODE_GP1_CLR, IWN_UCODE_GP1_RFKILL); 8604 IWN_WRITE(sc, IWN_UCODE_GP1_CLR, IWN_UCODE_GP1_CMD_BLOCKED); 8605 8606 /* Clear pending interrupts. */ 8607 IWN_WRITE(sc, IWN_INT, 0xffffffff); 8608 /* Enable interrupt coalescing. */ 8609 IWN_WRITE(sc, IWN_INT_COALESCING, 512 / 8); 8610 /* Enable interrupts. */ 8611 IWN_WRITE(sc, IWN_INT_MASK, sc->int_mask); 8612 8613 /* _Really_ make sure "radio off" bit is cleared! */ 8614 IWN_WRITE(sc, IWN_UCODE_GP1_CLR, IWN_UCODE_GP1_RFKILL); 8615 IWN_WRITE(sc, IWN_UCODE_GP1_CLR, IWN_UCODE_GP1_RFKILL); 8616 8617 /* Enable shadow registers. */ 8618 if (sc->base_params->shadow_reg_enable) 8619 IWN_SETBITS(sc, IWN_SHADOW_REG_CTRL, 0x800fffff); 8620 8621 if ((error = ops->load_firmware(sc)) != 0) { 8622 device_printf(sc->sc_dev, 8623 "%s: could not load firmware, error %d\n", __func__, 8624 error); 8625 return error; 8626 } 8627 /* Wait at most one second for firmware alive notification. */ 8628 if ((error = msleep(sc, &sc->sc_mtx, PCATCH, "iwninit", hz)) != 0) { 8629 device_printf(sc->sc_dev, 8630 "%s: timeout waiting for adapter to initialize, error %d\n", 8631 __func__, error); 8632 return error; 8633 } 8634 /* Do post-firmware initialization. */ 8635 8636 DPRINTF(sc, IWN_DEBUG_TRACE, "->%s: end\n",__func__); 8637 8638 return ops->post_alive(sc); 8639 } 8640 8641 static void 8642 iwn_hw_stop(struct iwn_softc *sc) 8643 { 8644 int chnl, qid, ntries; 8645 8646 DPRINTF(sc, IWN_DEBUG_TRACE, "->Doing %s\n", __func__); 8647 8648 IWN_WRITE(sc, IWN_RESET, IWN_RESET_NEVO); 8649 8650 /* Disable interrupts. */ 8651 IWN_WRITE(sc, IWN_INT_MASK, 0); 8652 IWN_WRITE(sc, IWN_INT, 0xffffffff); 8653 IWN_WRITE(sc, IWN_FH_INT, 0xffffffff); 8654 sc->sc_flags &= ~IWN_FLAG_USE_ICT; 8655 8656 /* Make sure we no longer hold the NIC lock. */ 8657 iwn_nic_unlock(sc); 8658 8659 /* Stop TX scheduler. */ 8660 iwn_prph_write(sc, sc->sched_txfact_addr, 0); 8661 8662 /* Stop all DMA channels. */ 8663 if (iwn_nic_lock(sc) == 0) { 8664 for (chnl = 0; chnl < sc->ndmachnls; chnl++) { 8665 IWN_WRITE(sc, IWN_FH_TX_CONFIG(chnl), 0); 8666 for (ntries = 0; ntries < 200; ntries++) { 8667 if (IWN_READ(sc, IWN_FH_TX_STATUS) & 8668 IWN_FH_TX_STATUS_IDLE(chnl)) 8669 break; 8670 DELAY(10); 8671 } 8672 } 8673 iwn_nic_unlock(sc); 8674 } 8675 8676 /* Stop RX ring. */ 8677 iwn_reset_rx_ring(sc, &sc->rxq); 8678 8679 /* Reset all TX rings. */ 8680 for (qid = 0; qid < sc->ntxqs; qid++) 8681 iwn_reset_tx_ring(sc, &sc->txq[qid]); 8682 8683 if (iwn_nic_lock(sc) == 0) { 8684 iwn_prph_write(sc, IWN_APMG_CLK_DIS, 8685 IWN_APMG_CLK_CTRL_DMA_CLK_RQT); 8686 iwn_nic_unlock(sc); 8687 } 8688 DELAY(5); 8689 /* Power OFF adapter. */ 8690 iwn_apm_stop(sc); 8691 } 8692 8693 static void 8694 iwn_panicked(void *arg0, int pending) 8695 { 8696 struct iwn_softc *sc = arg0; 8697 struct ieee80211com *ic = &sc->sc_ic; 8698 struct ieee80211vap *vap = TAILQ_FIRST(&ic->ic_vaps); 8699 #if 0 8700 int error; 8701 #endif 8702 8703 if (vap == NULL) { 8704 printf("%s: null vap\n", __func__); 8705 return; 8706 } 8707 8708 device_printf(sc->sc_dev, "%s: controller panicked, iv_state = %d; " 8709 "restarting\n", __func__, vap->iv_state); 8710 8711 /* 8712 * This is not enough work. We need to also reinitialise 8713 * the correct transmit state for aggregation enabled queues, 8714 * which has a very specific requirement of 8715 * ring index = 802.11 seqno % 256. If we don't do this (which 8716 * we definitely don't!) then the firmware will just panic again. 8717 */ 8718 #if 1 8719 ieee80211_restart_all(ic); 8720 #else 8721 IWN_LOCK(sc); 8722 8723 iwn_stop_locked(sc); 8724 if ((error = iwn_init_locked(sc)) != 0) { 8725 device_printf(sc->sc_dev, 8726 "%s: could not init hardware\n", __func__); 8727 goto unlock; 8728 } 8729 if (vap->iv_state >= IEEE80211_S_AUTH && 8730 (error = iwn_auth(sc, vap)) != 0) { 8731 device_printf(sc->sc_dev, 8732 "%s: could not move to auth state\n", __func__); 8733 } 8734 if (vap->iv_state >= IEEE80211_S_RUN && 8735 (error = iwn_run(sc, vap)) != 0) { 8736 device_printf(sc->sc_dev, 8737 "%s: could not move to run state\n", __func__); 8738 } 8739 8740 unlock: 8741 IWN_UNLOCK(sc); 8742 #endif 8743 } 8744 8745 static int 8746 iwn_init_locked(struct iwn_softc *sc) 8747 { 8748 int error; 8749 8750 DPRINTF(sc, IWN_DEBUG_TRACE, "->%s begin\n", __func__); 8751 8752 IWN_LOCK_ASSERT(sc); 8753 8754 if (sc->sc_flags & IWN_FLAG_RUNNING) 8755 goto end; 8756 8757 sc->sc_flags |= IWN_FLAG_RUNNING; 8758 8759 if ((error = iwn_hw_prepare(sc)) != 0) { 8760 device_printf(sc->sc_dev, "%s: hardware not ready, error %d\n", 8761 __func__, error); 8762 goto fail; 8763 } 8764 8765 /* Initialize interrupt mask to default value. */ 8766 sc->int_mask = IWN_INT_MASK_DEF; 8767 sc->sc_flags &= ~IWN_FLAG_USE_ICT; 8768 8769 /* Check that the radio is not disabled by hardware switch. */ 8770 if (!(IWN_READ(sc, IWN_GP_CNTRL) & IWN_GP_CNTRL_RFKILL)) { 8771 error = EAGAIN; 8772 goto fail; 8773 } 8774 8775 /* Read firmware images from the filesystem. */ 8776 if ((error = iwn_read_firmware(sc)) != 0) { 8777 device_printf(sc->sc_dev, 8778 "%s: could not read firmware, error %d\n", __func__, 8779 error); 8780 goto fail; 8781 } 8782 8783 /* Initialize hardware and upload firmware. */ 8784 error = iwn_hw_init(sc); 8785 iwn_unload_firmware(sc); 8786 if (error != 0) { 8787 device_printf(sc->sc_dev, 8788 "%s: could not initialize hardware, error %d\n", __func__, 8789 error); 8790 goto fail; 8791 } 8792 8793 /* Configure adapter now that it is ready. */ 8794 if ((error = iwn_config(sc)) != 0) { 8795 device_printf(sc->sc_dev, 8796 "%s: could not configure device, error %d\n", __func__, 8797 error); 8798 goto fail; 8799 } 8800 8801 callout_reset(&sc->watchdog_to, hz, iwn_watchdog, sc); 8802 8803 end: 8804 DPRINTF(sc, IWN_DEBUG_TRACE, "->%s: end\n",__func__); 8805 8806 return (0); 8807 8808 fail: 8809 iwn_stop_locked(sc); 8810 8811 DPRINTF(sc, IWN_DEBUG_TRACE, "->%s: end in error\n",__func__); 8812 8813 return (error); 8814 } 8815 8816 static int 8817 iwn_init(struct iwn_softc *sc) 8818 { 8819 int error; 8820 8821 IWN_LOCK(sc); 8822 error = iwn_init_locked(sc); 8823 IWN_UNLOCK(sc); 8824 8825 return (error); 8826 } 8827 8828 static void 8829 iwn_stop_locked(struct iwn_softc *sc) 8830 { 8831 8832 IWN_LOCK_ASSERT(sc); 8833 8834 if (!(sc->sc_flags & IWN_FLAG_RUNNING)) 8835 return; 8836 8837 sc->sc_is_scanning = 0; 8838 sc->sc_tx_timer = 0; 8839 callout_stop(&sc->watchdog_to); 8840 callout_stop(&sc->scan_timeout); 8841 callout_stop(&sc->calib_to); 8842 sc->sc_flags &= ~IWN_FLAG_RUNNING; 8843 8844 /* Power OFF hardware. */ 8845 iwn_hw_stop(sc); 8846 } 8847 8848 static void 8849 iwn_stop(struct iwn_softc *sc) 8850 { 8851 IWN_LOCK(sc); 8852 iwn_stop_locked(sc); 8853 IWN_UNLOCK(sc); 8854 } 8855 8856 /* 8857 * Callback from net80211 to start a scan. 8858 */ 8859 static void 8860 iwn_scan_start(struct ieee80211com *ic) 8861 { 8862 struct iwn_softc *sc = ic->ic_softc; 8863 8864 IWN_LOCK(sc); 8865 /* make the link LED blink while we're scanning */ 8866 iwn_set_led(sc, IWN_LED_LINK, 20, 2); 8867 IWN_UNLOCK(sc); 8868 } 8869 8870 /* 8871 * Callback from net80211 to terminate a scan. 8872 */ 8873 static void 8874 iwn_scan_end(struct ieee80211com *ic) 8875 { 8876 struct iwn_softc *sc = ic->ic_softc; 8877 struct ieee80211vap *vap = TAILQ_FIRST(&ic->ic_vaps); 8878 8879 IWN_LOCK(sc); 8880 if (vap->iv_state == IEEE80211_S_RUN) { 8881 /* Set link LED to ON status if we are associated */ 8882 iwn_set_led(sc, IWN_LED_LINK, 0, 1); 8883 } 8884 IWN_UNLOCK(sc); 8885 } 8886 8887 /* 8888 * Callback from net80211 to force a channel change. 8889 */ 8890 static void 8891 iwn_set_channel(struct ieee80211com *ic) 8892 { 8893 const struct ieee80211_channel *c = ic->ic_curchan; 8894 struct iwn_softc *sc = ic->ic_softc; 8895 int error; 8896 8897 DPRINTF(sc, IWN_DEBUG_TRACE, "->Doing %s\n", __func__); 8898 8899 IWN_LOCK(sc); 8900 sc->sc_rxtap.wr_chan_freq = htole16(c->ic_freq); 8901 sc->sc_rxtap.wr_chan_flags = htole16(c->ic_flags); 8902 sc->sc_txtap.wt_chan_freq = htole16(c->ic_freq); 8903 sc->sc_txtap.wt_chan_flags = htole16(c->ic_flags); 8904 8905 /* 8906 * Only need to set the channel in Monitor mode. AP scanning and auth 8907 * are already taken care of by their respective firmware commands. 8908 */ 8909 if (ic->ic_opmode == IEEE80211_M_MONITOR) { 8910 error = iwn_config(sc); 8911 if (error != 0) 8912 device_printf(sc->sc_dev, 8913 "%s: error %d settting channel\n", __func__, error); 8914 } 8915 IWN_UNLOCK(sc); 8916 } 8917 8918 /* 8919 * Callback from net80211 to start scanning of the current channel. 8920 */ 8921 static void 8922 iwn_scan_curchan(struct ieee80211_scan_state *ss, unsigned long maxdwell) 8923 { 8924 struct ieee80211vap *vap = ss->ss_vap; 8925 struct ieee80211com *ic = vap->iv_ic; 8926 struct iwn_softc *sc = ic->ic_softc; 8927 int error; 8928 8929 IWN_LOCK(sc); 8930 error = iwn_scan(sc, vap, ss, ic->ic_curchan); 8931 IWN_UNLOCK(sc); 8932 if (error != 0) 8933 ieee80211_cancel_scan(vap); 8934 } 8935 8936 /* 8937 * Callback from net80211 to handle the minimum dwell time being met. 8938 * The intent is to terminate the scan but we just let the firmware 8939 * notify us when it's finished as we have no safe way to abort it. 8940 */ 8941 static void 8942 iwn_scan_mindwell(struct ieee80211_scan_state *ss) 8943 { 8944 /* NB: don't try to abort scan; wait for firmware to finish */ 8945 } 8946 #ifdef IWN_DEBUG 8947 #define IWN_DESC(x) case x: return #x 8948 8949 /* 8950 * Translate CSR code to string 8951 */ 8952 static char *iwn_get_csr_string(int csr) 8953 { 8954 switch (csr) { 8955 IWN_DESC(IWN_HW_IF_CONFIG); 8956 IWN_DESC(IWN_INT_COALESCING); 8957 IWN_DESC(IWN_INT); 8958 IWN_DESC(IWN_INT_MASK); 8959 IWN_DESC(IWN_FH_INT); 8960 IWN_DESC(IWN_GPIO_IN); 8961 IWN_DESC(IWN_RESET); 8962 IWN_DESC(IWN_GP_CNTRL); 8963 IWN_DESC(IWN_HW_REV); 8964 IWN_DESC(IWN_EEPROM); 8965 IWN_DESC(IWN_EEPROM_GP); 8966 IWN_DESC(IWN_OTP_GP); 8967 IWN_DESC(IWN_GIO); 8968 IWN_DESC(IWN_GP_UCODE); 8969 IWN_DESC(IWN_GP_DRIVER); 8970 IWN_DESC(IWN_UCODE_GP1); 8971 IWN_DESC(IWN_UCODE_GP2); 8972 IWN_DESC(IWN_LED); 8973 IWN_DESC(IWN_DRAM_INT_TBL); 8974 IWN_DESC(IWN_GIO_CHICKEN); 8975 IWN_DESC(IWN_ANA_PLL); 8976 IWN_DESC(IWN_HW_REV_WA); 8977 IWN_DESC(IWN_DBG_HPET_MEM); 8978 default: 8979 return "UNKNOWN CSR"; 8980 } 8981 } 8982 8983 /* 8984 * This function print firmware register 8985 */ 8986 static void 8987 iwn_debug_register(struct iwn_softc *sc) 8988 { 8989 int i; 8990 static const uint32_t csr_tbl[] = { 8991 IWN_HW_IF_CONFIG, 8992 IWN_INT_COALESCING, 8993 IWN_INT, 8994 IWN_INT_MASK, 8995 IWN_FH_INT, 8996 IWN_GPIO_IN, 8997 IWN_RESET, 8998 IWN_GP_CNTRL, 8999 IWN_HW_REV, 9000 IWN_EEPROM, 9001 IWN_EEPROM_GP, 9002 IWN_OTP_GP, 9003 IWN_GIO, 9004 IWN_GP_UCODE, 9005 IWN_GP_DRIVER, 9006 IWN_UCODE_GP1, 9007 IWN_UCODE_GP2, 9008 IWN_LED, 9009 IWN_DRAM_INT_TBL, 9010 IWN_GIO_CHICKEN, 9011 IWN_ANA_PLL, 9012 IWN_HW_REV_WA, 9013 IWN_DBG_HPET_MEM, 9014 }; 9015 DPRINTF(sc, IWN_DEBUG_REGISTER, 9016 "CSR values: (2nd byte of IWN_INT_COALESCING is IWN_INT_PERIODIC)%s", 9017 "\n"); 9018 for (i = 0; i < nitems(csr_tbl); i++){ 9019 DPRINTF(sc, IWN_DEBUG_REGISTER," %10s: 0x%08x ", 9020 iwn_get_csr_string(csr_tbl[i]), IWN_READ(sc, csr_tbl[i])); 9021 if ((i+1) % 3 == 0) 9022 DPRINTF(sc, IWN_DEBUG_REGISTER,"%s","\n"); 9023 } 9024 DPRINTF(sc, IWN_DEBUG_REGISTER,"%s","\n"); 9025 } 9026 #endif 9027 9028 9029