1 /*- 2 * Copyright (c) 2007-2009 3 * Damien Bergamini <damien.bergamini@free.fr> 4 * Copyright (c) 2008 5 * Benjamin Close <benjsc@FreeBSD.org> 6 * Copyright (c) 2008 Sam Leffler, Errno Consulting 7 * 8 * Permission to use, copy, modify, and distribute this software for any 9 * purpose with or without fee is hereby granted, provided that the above 10 * copyright notice and this permission notice appear in all copies. 11 * 12 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 13 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 14 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR 15 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 16 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN 17 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF 18 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 19 */ 20 21 /* 22 * Driver for Intel WiFi Link 4965 and 1000/5000/6000 Series 802.11 network 23 * adapters. 24 */ 25 26 #include <sys/cdefs.h> 27 __FBSDID("$FreeBSD$"); 28 29 #include <sys/param.h> 30 #include <sys/sockio.h> 31 #include <sys/sysctl.h> 32 #include <sys/mbuf.h> 33 #include <sys/kernel.h> 34 #include <sys/socket.h> 35 #include <sys/systm.h> 36 #include <sys/malloc.h> 37 #include <sys/bus.h> 38 #include <sys/rman.h> 39 #include <sys/endian.h> 40 #include <sys/firmware.h> 41 #include <sys/limits.h> 42 #include <sys/module.h> 43 #include <sys/queue.h> 44 #include <sys/taskqueue.h> 45 46 #include <machine/bus.h> 47 #include <machine/resource.h> 48 #include <machine/clock.h> 49 50 #include <dev/pci/pcireg.h> 51 #include <dev/pci/pcivar.h> 52 53 #include <net/bpf.h> 54 #include <net/if.h> 55 #include <net/if_arp.h> 56 #include <net/ethernet.h> 57 #include <net/if_dl.h> 58 #include <net/if_media.h> 59 #include <net/if_types.h> 60 61 #include <netinet/in.h> 62 #include <netinet/in_systm.h> 63 #include <netinet/in_var.h> 64 #include <netinet/if_ether.h> 65 #include <netinet/ip.h> 66 67 #include <net80211/ieee80211_var.h> 68 #include <net80211/ieee80211_radiotap.h> 69 #include <net80211/ieee80211_regdomain.h> 70 #include <net80211/ieee80211_ratectl.h> 71 72 #include <dev/iwn/if_iwnreg.h> 73 #include <dev/iwn/if_iwnvar.h> 74 75 struct iwn_ident { 76 uint16_t vendor; 77 uint16_t device; 78 const char *name; 79 }; 80 81 static const struct iwn_ident iwn_ident_table [] = { 82 { 0x8086, 0x4229, "Intel(R) PRO/Wireless 4965BGN" }, 83 { 0x8086, 0x422D, "Intel(R) PRO/Wireless 4965BGN" }, 84 { 0x8086, 0x4230, "Intel(R) PRO/Wireless 4965BGN" }, 85 { 0x8086, 0x4233, "Intel(R) PRO/Wireless 4965BGN" }, 86 { 0x8086, 0x4232, "Intel(R) PRO/Wireless 5100" }, 87 { 0x8086, 0x4237, "Intel(R) PRO/Wireless 5100" }, 88 { 0x8086, 0x423C, "Intel(R) PRO/Wireless 5150" }, 89 { 0x8086, 0x423D, "Intel(R) PRO/Wireless 5150" }, 90 { 0x8086, 0x4235, "Intel(R) PRO/Wireless 5300" }, 91 { 0x8086, 0x4236, "Intel(R) PRO/Wireless 5300" }, 92 { 0x8086, 0x423A, "Intel(R) PRO/Wireless 5350" }, 93 { 0x8086, 0x423B, "Intel(R) PRO/Wireless 5350" }, 94 { 0x8086, 0x0083, "Intel(R) PRO/Wireless 1000" }, 95 { 0x8086, 0x0084, "Intel(R) PRO/Wireless 1000" }, 96 { 0x8086, 0x008D, "Intel(R) PRO/Wireless 6000" }, 97 { 0x8086, 0x008E, "Intel(R) PRO/Wireless 6000" }, 98 { 0x8086, 0x4238, "Intel(R) PRO/Wireless 6000" }, 99 { 0x8086, 0x4239, "Intel(R) PRO/Wireless 6000" }, 100 { 0x8086, 0x422B, "Intel(R) PRO/Wireless 6000" }, 101 { 0x8086, 0x422C, "Intel(R) PRO/Wireless 6000" }, 102 { 0x8086, 0x0087, "Intel(R) PRO/Wireless 6250" }, 103 { 0x8086, 0x0089, "Intel(R) PRO/Wireless 6250" }, 104 { 0x8086, 0x0082, "Intel(R) PRO/Wireless 6205a" }, 105 { 0x8086, 0x0085, "Intel(R) PRO/Wireless 6205a" }, 106 #ifdef notyet 107 { 0x8086, 0x008a, "Intel(R) PRO/Wireless 6205b" }, 108 { 0x8086, 0x008b, "Intel(R) PRO/Wireless 6205b" }, 109 { 0x8086, 0x008f, "Intel(R) PRO/Wireless 6205b" }, 110 { 0x8086, 0x0090, "Intel(R) PRO/Wireless 6205b" }, 111 { 0x8086, 0x0091, "Intel(R) PRO/Wireless 6205b" }, 112 #endif 113 { 0, 0, NULL } 114 }; 115 116 static int iwn_probe(device_t); 117 static int iwn_attach(device_t); 118 static int iwn4965_attach(struct iwn_softc *, uint16_t); 119 static int iwn5000_attach(struct iwn_softc *, uint16_t); 120 static void iwn_radiotap_attach(struct iwn_softc *); 121 static void iwn_sysctlattach(struct iwn_softc *); 122 static struct ieee80211vap *iwn_vap_create(struct ieee80211com *, 123 const char name[IFNAMSIZ], int unit, int opmode, 124 int flags, const uint8_t bssid[IEEE80211_ADDR_LEN], 125 const uint8_t mac[IEEE80211_ADDR_LEN]); 126 static void iwn_vap_delete(struct ieee80211vap *); 127 static int iwn_detach(device_t); 128 static int iwn_shutdown(device_t); 129 static int iwn_suspend(device_t); 130 static int iwn_resume(device_t); 131 static int iwn_nic_lock(struct iwn_softc *); 132 static int iwn_eeprom_lock(struct iwn_softc *); 133 static int iwn_init_otprom(struct iwn_softc *); 134 static int iwn_read_prom_data(struct iwn_softc *, uint32_t, void *, int); 135 static void iwn_dma_map_addr(void *, bus_dma_segment_t *, int, int); 136 static int iwn_dma_contig_alloc(struct iwn_softc *, struct iwn_dma_info *, 137 void **, bus_size_t, bus_size_t); 138 static void iwn_dma_contig_free(struct iwn_dma_info *); 139 static int iwn_alloc_sched(struct iwn_softc *); 140 static void iwn_free_sched(struct iwn_softc *); 141 static int iwn_alloc_kw(struct iwn_softc *); 142 static void iwn_free_kw(struct iwn_softc *); 143 static int iwn_alloc_ict(struct iwn_softc *); 144 static void iwn_free_ict(struct iwn_softc *); 145 static int iwn_alloc_fwmem(struct iwn_softc *); 146 static void iwn_free_fwmem(struct iwn_softc *); 147 static int iwn_alloc_rx_ring(struct iwn_softc *, struct iwn_rx_ring *); 148 static void iwn_reset_rx_ring(struct iwn_softc *, struct iwn_rx_ring *); 149 static void iwn_free_rx_ring(struct iwn_softc *, struct iwn_rx_ring *); 150 static int iwn_alloc_tx_ring(struct iwn_softc *, struct iwn_tx_ring *, 151 int); 152 static void iwn_reset_tx_ring(struct iwn_softc *, struct iwn_tx_ring *); 153 static void iwn_free_tx_ring(struct iwn_softc *, struct iwn_tx_ring *); 154 static void iwn5000_ict_reset(struct iwn_softc *); 155 static int iwn_read_eeprom(struct iwn_softc *, 156 uint8_t macaddr[IEEE80211_ADDR_LEN]); 157 static void iwn4965_read_eeprom(struct iwn_softc *); 158 static void iwn4965_print_power_group(struct iwn_softc *, int); 159 static void iwn5000_read_eeprom(struct iwn_softc *); 160 static uint32_t iwn_eeprom_channel_flags(struct iwn_eeprom_chan *); 161 static void iwn_read_eeprom_band(struct iwn_softc *, int); 162 #if 0 /* HT */ 163 static void iwn_read_eeprom_ht40(struct iwn_softc *, int); 164 #endif 165 static void iwn_read_eeprom_channels(struct iwn_softc *, int, uint32_t); 166 static struct iwn_eeprom_chan *iwn_find_eeprom_channel(struct iwn_softc *, 167 struct ieee80211_channel *); 168 static int iwn_setregdomain(struct ieee80211com *, 169 struct ieee80211_regdomain *, int, 170 struct ieee80211_channel[]); 171 static void iwn_read_eeprom_enhinfo(struct iwn_softc *); 172 static struct ieee80211_node *iwn_node_alloc(struct ieee80211vap *, 173 const uint8_t mac[IEEE80211_ADDR_LEN]); 174 static void iwn_newassoc(struct ieee80211_node *, int); 175 static int iwn_media_change(struct ifnet *); 176 static int iwn_newstate(struct ieee80211vap *, enum ieee80211_state, int); 177 static void iwn_calib_timeout(void *); 178 static void iwn_rx_phy(struct iwn_softc *, struct iwn_rx_desc *, 179 struct iwn_rx_data *); 180 static void iwn_rx_done(struct iwn_softc *, struct iwn_rx_desc *, 181 struct iwn_rx_data *); 182 #if 0 /* HT */ 183 static void iwn_rx_compressed_ba(struct iwn_softc *, struct iwn_rx_desc *, 184 struct iwn_rx_data *); 185 #endif 186 static void iwn5000_rx_calib_results(struct iwn_softc *, 187 struct iwn_rx_desc *, struct iwn_rx_data *); 188 static void iwn_rx_statistics(struct iwn_softc *, struct iwn_rx_desc *, 189 struct iwn_rx_data *); 190 static void iwn4965_tx_done(struct iwn_softc *, struct iwn_rx_desc *, 191 struct iwn_rx_data *); 192 static void iwn5000_tx_done(struct iwn_softc *, struct iwn_rx_desc *, 193 struct iwn_rx_data *); 194 static void iwn_tx_done(struct iwn_softc *, struct iwn_rx_desc *, int, 195 uint8_t); 196 static void iwn_cmd_done(struct iwn_softc *, struct iwn_rx_desc *); 197 static void iwn_notif_intr(struct iwn_softc *); 198 static void iwn_wakeup_intr(struct iwn_softc *); 199 static void iwn_rftoggle_intr(struct iwn_softc *); 200 static void iwn_fatal_intr(struct iwn_softc *); 201 static void iwn_intr(void *); 202 static void iwn4965_update_sched(struct iwn_softc *, int, int, uint8_t, 203 uint16_t); 204 static void iwn5000_update_sched(struct iwn_softc *, int, int, uint8_t, 205 uint16_t); 206 #ifdef notyet 207 static void iwn5000_reset_sched(struct iwn_softc *, int, int); 208 #endif 209 static uint8_t iwn_plcp_signal(int); 210 static int iwn_tx_data(struct iwn_softc *, struct mbuf *, 211 struct ieee80211_node *); 212 static int iwn_tx_data_raw(struct iwn_softc *, struct mbuf *, 213 struct ieee80211_node *, 214 const struct ieee80211_bpf_params *params); 215 static int iwn_raw_xmit(struct ieee80211_node *, struct mbuf *, 216 const struct ieee80211_bpf_params *); 217 static void iwn_start(struct ifnet *); 218 static void iwn_start_locked(struct ifnet *); 219 static void iwn_watchdog(void *); 220 static int iwn_ioctl(struct ifnet *, u_long, caddr_t); 221 static int iwn_cmd(struct iwn_softc *, int, const void *, int, int); 222 static int iwn4965_add_node(struct iwn_softc *, struct iwn_node_info *, 223 int); 224 static int iwn5000_add_node(struct iwn_softc *, struct iwn_node_info *, 225 int); 226 static int iwn_set_link_quality(struct iwn_softc *, 227 struct ieee80211_node *); 228 static int iwn_add_broadcast_node(struct iwn_softc *, int); 229 static int iwn_updateedca(struct ieee80211com *); 230 static void iwn_update_mcast(struct ifnet *); 231 static void iwn_set_led(struct iwn_softc *, uint8_t, uint8_t, uint8_t); 232 static int iwn_set_critical_temp(struct iwn_softc *); 233 static int iwn_set_timing(struct iwn_softc *, struct ieee80211_node *); 234 static void iwn4965_power_calibration(struct iwn_softc *, int); 235 static int iwn4965_set_txpower(struct iwn_softc *, 236 struct ieee80211_channel *, int); 237 static int iwn5000_set_txpower(struct iwn_softc *, 238 struct ieee80211_channel *, int); 239 static int iwn4965_get_rssi(struct iwn_softc *, struct iwn_rx_stat *); 240 static int iwn5000_get_rssi(struct iwn_softc *, struct iwn_rx_stat *); 241 static int iwn_get_noise(const struct iwn_rx_general_stats *); 242 static int iwn4965_get_temperature(struct iwn_softc *); 243 static int iwn5000_get_temperature(struct iwn_softc *); 244 static int iwn_init_sensitivity(struct iwn_softc *); 245 static void iwn_collect_noise(struct iwn_softc *, 246 const struct iwn_rx_general_stats *); 247 static int iwn4965_init_gains(struct iwn_softc *); 248 static int iwn5000_init_gains(struct iwn_softc *); 249 static int iwn4965_set_gains(struct iwn_softc *); 250 static int iwn5000_set_gains(struct iwn_softc *); 251 static void iwn_tune_sensitivity(struct iwn_softc *, 252 const struct iwn_rx_stats *); 253 static int iwn_send_sensitivity(struct iwn_softc *); 254 static int iwn_set_pslevel(struct iwn_softc *, int, int, int); 255 static int iwn_send_btcoex(struct iwn_softc *); 256 static int iwn_send_advanced_btcoex(struct iwn_softc *); 257 static int iwn_config(struct iwn_softc *); 258 static uint8_t *ieee80211_add_ssid(uint8_t *, const uint8_t *, u_int); 259 static int iwn_scan(struct iwn_softc *); 260 static int iwn_auth(struct iwn_softc *, struct ieee80211vap *vap); 261 static int iwn_run(struct iwn_softc *, struct ieee80211vap *vap); 262 #if 0 /* HT */ 263 static int iwn_ampdu_rx_start(struct ieee80211com *, 264 struct ieee80211_node *, uint8_t); 265 static void iwn_ampdu_rx_stop(struct ieee80211com *, 266 struct ieee80211_node *, uint8_t); 267 static int iwn_ampdu_tx_start(struct ieee80211com *, 268 struct ieee80211_node *, uint8_t); 269 static void iwn_ampdu_tx_stop(struct ieee80211com *, 270 struct ieee80211_node *, uint8_t); 271 static void iwn4965_ampdu_tx_start(struct iwn_softc *, 272 struct ieee80211_node *, uint8_t, uint16_t); 273 static void iwn4965_ampdu_tx_stop(struct iwn_softc *, 274 uint8_t, uint16_t); 275 static void iwn5000_ampdu_tx_start(struct iwn_softc *, 276 struct ieee80211_node *, uint8_t, uint16_t); 277 static void iwn5000_ampdu_tx_stop(struct iwn_softc *, 278 uint8_t, uint16_t); 279 #endif 280 static int iwn5000_query_calibration(struct iwn_softc *); 281 static int iwn5000_send_calibration(struct iwn_softc *); 282 static int iwn5000_send_wimax_coex(struct iwn_softc *); 283 static int iwn5000_crystal_calib(struct iwn_softc *); 284 static int iwn5000_temp_offset_calib(struct iwn_softc *); 285 static int iwn4965_post_alive(struct iwn_softc *); 286 static int iwn5000_post_alive(struct iwn_softc *); 287 static int iwn4965_load_bootcode(struct iwn_softc *, const uint8_t *, 288 int); 289 static int iwn4965_load_firmware(struct iwn_softc *); 290 static int iwn5000_load_firmware_section(struct iwn_softc *, uint32_t, 291 const uint8_t *, int); 292 static int iwn5000_load_firmware(struct iwn_softc *); 293 static int iwn_read_firmware_leg(struct iwn_softc *, 294 struct iwn_fw_info *); 295 static int iwn_read_firmware_tlv(struct iwn_softc *, 296 struct iwn_fw_info *, uint16_t); 297 static int iwn_read_firmware(struct iwn_softc *); 298 static int iwn_clock_wait(struct iwn_softc *); 299 static int iwn_apm_init(struct iwn_softc *); 300 static void iwn_apm_stop_master(struct iwn_softc *); 301 static void iwn_apm_stop(struct iwn_softc *); 302 static int iwn4965_nic_config(struct iwn_softc *); 303 static int iwn5000_nic_config(struct iwn_softc *); 304 static int iwn_hw_prepare(struct iwn_softc *); 305 static int iwn_hw_init(struct iwn_softc *); 306 static void iwn_hw_stop(struct iwn_softc *); 307 static void iwn_radio_on(void *, int); 308 static void iwn_radio_off(void *, int); 309 static void iwn_init_locked(struct iwn_softc *); 310 static void iwn_init(void *); 311 static void iwn_stop_locked(struct iwn_softc *); 312 static void iwn_stop(struct iwn_softc *); 313 static void iwn_scan_start(struct ieee80211com *); 314 static void iwn_scan_end(struct ieee80211com *); 315 static void iwn_set_channel(struct ieee80211com *); 316 static void iwn_scan_curchan(struct ieee80211_scan_state *, unsigned long); 317 static void iwn_scan_mindwell(struct ieee80211_scan_state *); 318 static void iwn_hw_reset(void *, int); 319 320 #define IWN_DEBUG 321 #ifdef IWN_DEBUG 322 enum { 323 IWN_DEBUG_XMIT = 0x00000001, /* basic xmit operation */ 324 IWN_DEBUG_RECV = 0x00000002, /* basic recv operation */ 325 IWN_DEBUG_STATE = 0x00000004, /* 802.11 state transitions */ 326 IWN_DEBUG_TXPOW = 0x00000008, /* tx power processing */ 327 IWN_DEBUG_RESET = 0x00000010, /* reset processing */ 328 IWN_DEBUG_OPS = 0x00000020, /* iwn_ops processing */ 329 IWN_DEBUG_BEACON = 0x00000040, /* beacon handling */ 330 IWN_DEBUG_WATCHDOG = 0x00000080, /* watchdog timeout */ 331 IWN_DEBUG_INTR = 0x00000100, /* ISR */ 332 IWN_DEBUG_CALIBRATE = 0x00000200, /* periodic calibration */ 333 IWN_DEBUG_NODE = 0x00000400, /* node management */ 334 IWN_DEBUG_LED = 0x00000800, /* led management */ 335 IWN_DEBUG_CMD = 0x00001000, /* cmd submission */ 336 IWN_DEBUG_FATAL = 0x80000000, /* fatal errors */ 337 IWN_DEBUG_ANY = 0xffffffff 338 }; 339 340 #define DPRINTF(sc, m, fmt, ...) do { \ 341 if (sc->sc_debug & (m)) \ 342 printf(fmt, __VA_ARGS__); \ 343 } while (0) 344 345 static const char * 346 iwn_intr_str(uint8_t cmd) 347 { 348 switch (cmd) { 349 /* Notifications */ 350 case IWN_UC_READY: return "UC_READY"; 351 case IWN_ADD_NODE_DONE: return "ADD_NODE_DONE"; 352 case IWN_TX_DONE: return "TX_DONE"; 353 case IWN_START_SCAN: return "START_SCAN"; 354 case IWN_STOP_SCAN: return "STOP_SCAN"; 355 case IWN_RX_STATISTICS: return "RX_STATS"; 356 case IWN_BEACON_STATISTICS: return "BEACON_STATS"; 357 case IWN_STATE_CHANGED: return "STATE_CHANGED"; 358 case IWN_BEACON_MISSED: return "BEACON_MISSED"; 359 case IWN_RX_PHY: return "RX_PHY"; 360 case IWN_MPDU_RX_DONE: return "MPDU_RX_DONE"; 361 case IWN_RX_DONE: return "RX_DONE"; 362 363 /* Command Notifications */ 364 case IWN_CMD_RXON: return "IWN_CMD_RXON"; 365 case IWN_CMD_RXON_ASSOC: return "IWN_CMD_RXON_ASSOC"; 366 case IWN_CMD_EDCA_PARAMS: return "IWN_CMD_EDCA_PARAMS"; 367 case IWN_CMD_TIMING: return "IWN_CMD_TIMING"; 368 case IWN_CMD_LINK_QUALITY: return "IWN_CMD_LINK_QUALITY"; 369 case IWN_CMD_SET_LED: return "IWN_CMD_SET_LED"; 370 case IWN5000_CMD_WIMAX_COEX: return "IWN5000_CMD_WIMAX_COEX"; 371 case IWN5000_CMD_CALIB_CONFIG: return "IWN5000_CMD_CALIB_CONFIG"; 372 case IWN5000_CMD_CALIB_RESULT: return "IWN5000_CMD_CALIB_RESULT"; 373 case IWN5000_CMD_CALIB_COMPLETE: return "IWN5000_CMD_CALIB_COMPLETE"; 374 case IWN_CMD_SET_POWER_MODE: return "IWN_CMD_SET_POWER_MODE"; 375 case IWN_CMD_SCAN: return "IWN_CMD_SCAN"; 376 case IWN_CMD_SCAN_RESULTS: return "IWN_CMD_SCAN_RESULTS"; 377 case IWN_CMD_TXPOWER: return "IWN_CMD_TXPOWER"; 378 case IWN_CMD_TXPOWER_DBM: return "IWN_CMD_TXPOWER_DBM"; 379 case IWN5000_CMD_TX_ANT_CONFIG: return "IWN5000_CMD_TX_ANT_CONFIG"; 380 case IWN_CMD_BT_COEX: return "IWN_CMD_BT_COEX"; 381 case IWN_CMD_SET_CRITICAL_TEMP: return "IWN_CMD_SET_CRITICAL_TEMP"; 382 case IWN_CMD_SET_SENSITIVITY: return "IWN_CMD_SET_SENSITIVITY"; 383 case IWN_CMD_PHY_CALIB: return "IWN_CMD_PHY_CALIB"; 384 } 385 return "UNKNOWN INTR NOTIF/CMD"; 386 } 387 #else 388 #define DPRINTF(sc, m, fmt, ...) do { (void) sc; } while (0) 389 #endif 390 391 static device_method_t iwn_methods[] = { 392 /* Device interface */ 393 DEVMETHOD(device_probe, iwn_probe), 394 DEVMETHOD(device_attach, iwn_attach), 395 DEVMETHOD(device_detach, iwn_detach), 396 DEVMETHOD(device_shutdown, iwn_shutdown), 397 DEVMETHOD(device_suspend, iwn_suspend), 398 DEVMETHOD(device_resume, iwn_resume), 399 { 0, 0 } 400 }; 401 402 static driver_t iwn_driver = { 403 "iwn", 404 iwn_methods, 405 sizeof(struct iwn_softc) 406 }; 407 static devclass_t iwn_devclass; 408 409 DRIVER_MODULE(iwn, pci, iwn_driver, iwn_devclass, 0, 0); 410 411 MODULE_DEPEND(iwn, firmware, 1, 1, 1); 412 MODULE_DEPEND(iwn, pci, 1, 1, 1); 413 MODULE_DEPEND(iwn, wlan, 1, 1, 1); 414 415 static int 416 iwn_probe(device_t dev) 417 { 418 const struct iwn_ident *ident; 419 420 for (ident = iwn_ident_table; ident->name != NULL; ident++) { 421 if (pci_get_vendor(dev) == ident->vendor && 422 pci_get_device(dev) == ident->device) { 423 device_set_desc(dev, ident->name); 424 return 0; 425 } 426 } 427 return ENXIO; 428 } 429 430 static int 431 iwn_attach(device_t dev) 432 { 433 struct iwn_softc *sc = (struct iwn_softc *)device_get_softc(dev); 434 struct ieee80211com *ic; 435 struct ifnet *ifp; 436 uint32_t reg; 437 int i, error, result; 438 uint8_t macaddr[IEEE80211_ADDR_LEN]; 439 440 sc->sc_dev = dev; 441 442 /* 443 * Get the offset of the PCI Express Capability Structure in PCI 444 * Configuration Space. 445 */ 446 error = pci_find_cap(dev, PCIY_EXPRESS, &sc->sc_cap_off); 447 if (error != 0) { 448 device_printf(dev, "PCIe capability structure not found!\n"); 449 return error; 450 } 451 452 /* Clear device-specific "PCI retry timeout" register (41h). */ 453 pci_write_config(dev, 0x41, 0, 1); 454 455 /* Hardware bug workaround. */ 456 reg = pci_read_config(dev, PCIR_COMMAND, 1); 457 if (reg & PCIM_CMD_INTxDIS) { 458 DPRINTF(sc, IWN_DEBUG_RESET, "%s: PCIe INTx Disable set\n", 459 __func__); 460 reg &= ~PCIM_CMD_INTxDIS; 461 pci_write_config(dev, PCIR_COMMAND, reg, 1); 462 } 463 464 /* Enable bus-mastering. */ 465 pci_enable_busmaster(dev); 466 467 sc->mem_rid = PCIR_BAR(0); 468 sc->mem = bus_alloc_resource_any(dev, SYS_RES_MEMORY, &sc->mem_rid, 469 RF_ACTIVE); 470 if (sc->mem == NULL) { 471 device_printf(dev, "can't map mem space\n"); 472 error = ENOMEM; 473 return error; 474 } 475 sc->sc_st = rman_get_bustag(sc->mem); 476 sc->sc_sh = rman_get_bushandle(sc->mem); 477 478 sc->irq_rid = 0; 479 if ((result = pci_msi_count(dev)) == 1 && 480 pci_alloc_msi(dev, &result) == 0) 481 sc->irq_rid = 1; 482 /* Install interrupt handler. */ 483 sc->irq = bus_alloc_resource_any(dev, SYS_RES_IRQ, &sc->irq_rid, 484 RF_ACTIVE | RF_SHAREABLE); 485 if (sc->irq == NULL) { 486 device_printf(dev, "can't map interrupt\n"); 487 error = ENOMEM; 488 goto fail; 489 } 490 491 IWN_LOCK_INIT(sc); 492 493 /* Read hardware revision and attach. */ 494 sc->hw_type = (IWN_READ(sc, IWN_HW_REV) >> 4) & 0xf; 495 if (sc->hw_type == IWN_HW_REV_TYPE_4965) 496 error = iwn4965_attach(sc, pci_get_device(dev)); 497 else 498 error = iwn5000_attach(sc, pci_get_device(dev)); 499 if (error != 0) { 500 device_printf(dev, "could not attach device, error %d\n", 501 error); 502 goto fail; 503 } 504 505 if ((error = iwn_hw_prepare(sc)) != 0) { 506 device_printf(dev, "hardware not ready, error %d\n", error); 507 goto fail; 508 } 509 510 /* Allocate DMA memory for firmware transfers. */ 511 if ((error = iwn_alloc_fwmem(sc)) != 0) { 512 device_printf(dev, 513 "could not allocate memory for firmware, error %d\n", 514 error); 515 goto fail; 516 } 517 518 /* Allocate "Keep Warm" page. */ 519 if ((error = iwn_alloc_kw(sc)) != 0) { 520 device_printf(dev, 521 "could not allocate keep warm page, error %d\n", error); 522 goto fail; 523 } 524 525 /* Allocate ICT table for 5000 Series. */ 526 if (sc->hw_type != IWN_HW_REV_TYPE_4965 && 527 (error = iwn_alloc_ict(sc)) != 0) { 528 device_printf(dev, "could not allocate ICT table, error %d\n", 529 error); 530 goto fail; 531 } 532 533 /* Allocate TX scheduler "rings". */ 534 if ((error = iwn_alloc_sched(sc)) != 0) { 535 device_printf(dev, 536 "could not allocate TX scheduler rings, error %d\n", error); 537 goto fail; 538 } 539 540 /* Allocate TX rings (16 on 4965AGN, 20 on >=5000). */ 541 for (i = 0; i < sc->ntxqs; i++) { 542 if ((error = iwn_alloc_tx_ring(sc, &sc->txq[i], i)) != 0) { 543 device_printf(dev, 544 "could not allocate TX ring %d, error %d\n", i, 545 error); 546 goto fail; 547 } 548 } 549 550 /* Allocate RX ring. */ 551 if ((error = iwn_alloc_rx_ring(sc, &sc->rxq)) != 0) { 552 device_printf(dev, "could not allocate RX ring, error %d\n", 553 error); 554 goto fail; 555 } 556 557 /* Clear pending interrupts. */ 558 IWN_WRITE(sc, IWN_INT, 0xffffffff); 559 560 /* Count the number of available chains. */ 561 sc->ntxchains = 562 ((sc->txchainmask >> 2) & 1) + 563 ((sc->txchainmask >> 1) & 1) + 564 ((sc->txchainmask >> 0) & 1); 565 sc->nrxchains = 566 ((sc->rxchainmask >> 2) & 1) + 567 ((sc->rxchainmask >> 1) & 1) + 568 ((sc->rxchainmask >> 0) & 1); 569 if (bootverbose) { 570 device_printf(dev, "MIMO %dT%dR, %.4s, address %6D\n", 571 sc->ntxchains, sc->nrxchains, sc->eeprom_domain, 572 macaddr, ":"); 573 } 574 575 ifp = sc->sc_ifp = if_alloc(IFT_IEEE80211); 576 if (ifp == NULL) { 577 device_printf(dev, "can not allocate ifnet structure\n"); 578 goto fail; 579 } 580 581 ic = ifp->if_l2com; 582 ic->ic_ifp = ifp; 583 ic->ic_phytype = IEEE80211_T_OFDM; /* not only, but not used */ 584 ic->ic_opmode = IEEE80211_M_STA; /* default to BSS mode */ 585 586 /* Set device capabilities. */ 587 ic->ic_caps = 588 IEEE80211_C_STA /* station mode supported */ 589 | IEEE80211_C_MONITOR /* monitor mode supported */ 590 | IEEE80211_C_TXPMGT /* tx power management */ 591 | IEEE80211_C_SHSLOT /* short slot time supported */ 592 | IEEE80211_C_WPA 593 | IEEE80211_C_SHPREAMBLE /* short preamble supported */ 594 | IEEE80211_C_BGSCAN /* background scanning */ 595 #if 0 596 | IEEE80211_C_IBSS /* ibss/adhoc mode */ 597 #endif 598 | IEEE80211_C_WME /* WME */ 599 ; 600 #if 0 /* HT */ 601 /* XXX disable until HT channel setup works */ 602 ic->ic_htcaps = 603 IEEE80211_HTCAP_SMPS_ENA /* SM PS mode enabled */ 604 | IEEE80211_HTCAP_CHWIDTH40 /* 40MHz channel width */ 605 | IEEE80211_HTCAP_SHORTGI20 /* short GI in 20MHz */ 606 | IEEE80211_HTCAP_SHORTGI40 /* short GI in 40MHz */ 607 | IEEE80211_HTCAP_RXSTBC_2STREAM/* 1-2 spatial streams */ 608 | IEEE80211_HTCAP_MAXAMSDU_3839 /* max A-MSDU length */ 609 /* s/w capabilities */ 610 | IEEE80211_HTC_HT /* HT operation */ 611 | IEEE80211_HTC_AMPDU /* tx A-MPDU */ 612 | IEEE80211_HTC_AMSDU /* tx A-MSDU */ 613 ; 614 615 /* Set HT capabilities. */ 616 ic->ic_htcaps = 617 #if IWN_RBUF_SIZE == 8192 618 IEEE80211_HTCAP_AMSDU7935 | 619 #endif 620 IEEE80211_HTCAP_CBW20_40 | 621 IEEE80211_HTCAP_SGI20 | 622 IEEE80211_HTCAP_SGI40; 623 if (sc->hw_type != IWN_HW_REV_TYPE_4965) 624 ic->ic_htcaps |= IEEE80211_HTCAP_GF; 625 if (sc->hw_type == IWN_HW_REV_TYPE_6050) 626 ic->ic_htcaps |= IEEE80211_HTCAP_SMPS_DYN; 627 else 628 ic->ic_htcaps |= IEEE80211_HTCAP_SMPS_DIS; 629 #endif 630 631 /* Read MAC address, channels, etc from EEPROM. */ 632 if ((error = iwn_read_eeprom(sc, macaddr)) != 0) { 633 device_printf(dev, "could not read EEPROM, error %d\n", 634 error); 635 goto fail; 636 } 637 638 #if 0 /* HT */ 639 /* Set supported HT rates. */ 640 ic->ic_sup_mcs[0] = 0xff; 641 if (sc->nrxchains > 1) 642 ic->ic_sup_mcs[1] = 0xff; 643 if (sc->nrxchains > 2) 644 ic->ic_sup_mcs[2] = 0xff; 645 #endif 646 647 if_initname(ifp, device_get_name(dev), device_get_unit(dev)); 648 ifp->if_softc = sc; 649 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 650 ifp->if_init = iwn_init; 651 ifp->if_ioctl = iwn_ioctl; 652 ifp->if_start = iwn_start; 653 IFQ_SET_MAXLEN(&ifp->if_snd, ifqmaxlen); 654 ifp->if_snd.ifq_drv_maxlen = ifqmaxlen; 655 IFQ_SET_READY(&ifp->if_snd); 656 657 ieee80211_ifattach(ic, macaddr); 658 ic->ic_vap_create = iwn_vap_create; 659 ic->ic_vap_delete = iwn_vap_delete; 660 ic->ic_raw_xmit = iwn_raw_xmit; 661 ic->ic_node_alloc = iwn_node_alloc; 662 #if 0 /* HT */ 663 ic->ic_ampdu_rx_start = iwn_ampdu_rx_start; 664 ic->ic_ampdu_rx_stop = iwn_ampdu_rx_stop; 665 ic->ic_ampdu_tx_start = iwn_ampdu_tx_start; 666 ic->ic_ampdu_tx_stop = iwn_ampdu_tx_stop; 667 #endif 668 ic->ic_newassoc = iwn_newassoc; 669 ic->ic_wme.wme_update = iwn_updateedca; 670 ic->ic_update_mcast = iwn_update_mcast; 671 ic->ic_scan_start = iwn_scan_start; 672 ic->ic_scan_end = iwn_scan_end; 673 ic->ic_set_channel = iwn_set_channel; 674 ic->ic_scan_curchan = iwn_scan_curchan; 675 ic->ic_scan_mindwell = iwn_scan_mindwell; 676 ic->ic_setregdomain = iwn_setregdomain; 677 678 iwn_radiotap_attach(sc); 679 680 callout_init_mtx(&sc->calib_to, &sc->sc_mtx, 0); 681 callout_init_mtx(&sc->watchdog_to, &sc->sc_mtx, 0); 682 TASK_INIT(&sc->sc_reinit_task, 0, iwn_hw_reset, sc); 683 TASK_INIT(&sc->sc_radioon_task, 0, iwn_radio_on, sc); 684 TASK_INIT(&sc->sc_radiooff_task, 0, iwn_radio_off, sc); 685 686 iwn_sysctlattach(sc); 687 688 /* 689 * Hook our interrupt after all initialization is complete. 690 */ 691 error = bus_setup_intr(dev, sc->irq, INTR_TYPE_NET | INTR_MPSAFE, 692 NULL, iwn_intr, sc, &sc->sc_ih); 693 if (error != 0) { 694 device_printf(dev, "can't establish interrupt, error %d\n", 695 error); 696 goto fail; 697 } 698 699 if (bootverbose) 700 ieee80211_announce(ic); 701 return 0; 702 fail: 703 iwn_detach(dev); 704 return error; 705 } 706 707 static int 708 iwn4965_attach(struct iwn_softc *sc, uint16_t pid) 709 { 710 struct iwn_ops *ops = &sc->ops; 711 712 ops->load_firmware = iwn4965_load_firmware; 713 ops->read_eeprom = iwn4965_read_eeprom; 714 ops->post_alive = iwn4965_post_alive; 715 ops->nic_config = iwn4965_nic_config; 716 ops->update_sched = iwn4965_update_sched; 717 ops->get_temperature = iwn4965_get_temperature; 718 ops->get_rssi = iwn4965_get_rssi; 719 ops->set_txpower = iwn4965_set_txpower; 720 ops->init_gains = iwn4965_init_gains; 721 ops->set_gains = iwn4965_set_gains; 722 ops->add_node = iwn4965_add_node; 723 ops->tx_done = iwn4965_tx_done; 724 #if 0 /* HT */ 725 ops->ampdu_tx_start = iwn4965_ampdu_tx_start; 726 ops->ampdu_tx_stop = iwn4965_ampdu_tx_stop; 727 #endif 728 sc->ntxqs = IWN4965_NTXQUEUES; 729 sc->ndmachnls = IWN4965_NDMACHNLS; 730 sc->broadcast_id = IWN4965_ID_BROADCAST; 731 sc->rxonsz = IWN4965_RXONSZ; 732 sc->schedsz = IWN4965_SCHEDSZ; 733 sc->fw_text_maxsz = IWN4965_FW_TEXT_MAXSZ; 734 sc->fw_data_maxsz = IWN4965_FW_DATA_MAXSZ; 735 sc->fwsz = IWN4965_FWSZ; 736 sc->sched_txfact_addr = IWN4965_SCHED_TXFACT; 737 sc->limits = &iwn4965_sensitivity_limits; 738 sc->fwname = "iwn4965fw"; 739 /* Override chains masks, ROM is known to be broken. */ 740 sc->txchainmask = IWN_ANT_AB; 741 sc->rxchainmask = IWN_ANT_ABC; 742 743 return 0; 744 } 745 746 static int 747 iwn5000_attach(struct iwn_softc *sc, uint16_t pid) 748 { 749 struct iwn_ops *ops = &sc->ops; 750 751 ops->load_firmware = iwn5000_load_firmware; 752 ops->read_eeprom = iwn5000_read_eeprom; 753 ops->post_alive = iwn5000_post_alive; 754 ops->nic_config = iwn5000_nic_config; 755 ops->update_sched = iwn5000_update_sched; 756 ops->get_temperature = iwn5000_get_temperature; 757 ops->get_rssi = iwn5000_get_rssi; 758 ops->set_txpower = iwn5000_set_txpower; 759 ops->init_gains = iwn5000_init_gains; 760 ops->set_gains = iwn5000_set_gains; 761 ops->add_node = iwn5000_add_node; 762 ops->tx_done = iwn5000_tx_done; 763 #if 0 /* HT */ 764 ops->ampdu_tx_start = iwn5000_ampdu_tx_start; 765 ops->ampdu_tx_stop = iwn5000_ampdu_tx_stop; 766 #endif 767 sc->ntxqs = IWN5000_NTXQUEUES; 768 sc->ndmachnls = IWN5000_NDMACHNLS; 769 sc->broadcast_id = IWN5000_ID_BROADCAST; 770 sc->rxonsz = IWN5000_RXONSZ; 771 sc->schedsz = IWN5000_SCHEDSZ; 772 sc->fw_text_maxsz = IWN5000_FW_TEXT_MAXSZ; 773 sc->fw_data_maxsz = IWN5000_FW_DATA_MAXSZ; 774 sc->fwsz = IWN5000_FWSZ; 775 sc->sched_txfact_addr = IWN5000_SCHED_TXFACT; 776 sc->reset_noise_gain = IWN5000_PHY_CALIB_RESET_NOISE_GAIN; 777 sc->noise_gain = IWN5000_PHY_CALIB_NOISE_GAIN; 778 779 switch (sc->hw_type) { 780 case IWN_HW_REV_TYPE_5100: 781 sc->limits = &iwn5000_sensitivity_limits; 782 sc->fwname = "iwn5000fw"; 783 /* Override chains masks, ROM is known to be broken. */ 784 sc->txchainmask = IWN_ANT_B; 785 sc->rxchainmask = IWN_ANT_AB; 786 break; 787 case IWN_HW_REV_TYPE_5150: 788 sc->limits = &iwn5150_sensitivity_limits; 789 sc->fwname = "iwn5150fw"; 790 break; 791 case IWN_HW_REV_TYPE_5300: 792 case IWN_HW_REV_TYPE_5350: 793 sc->limits = &iwn5000_sensitivity_limits; 794 sc->fwname = "iwn5000fw"; 795 break; 796 case IWN_HW_REV_TYPE_1000: 797 sc->limits = &iwn1000_sensitivity_limits; 798 sc->fwname = "iwn1000fw"; 799 break; 800 case IWN_HW_REV_TYPE_6000: 801 sc->limits = &iwn6000_sensitivity_limits; 802 sc->fwname = "iwn6000fw"; 803 if (pid == 0x422c || pid == 0x4239) { 804 sc->sc_flags |= IWN_FLAG_INTERNAL_PA; 805 /* Override chains masks, ROM is known to be broken. */ 806 sc->txchainmask = IWN_ANT_BC; 807 sc->rxchainmask = IWN_ANT_BC; 808 } 809 break; 810 case IWN_HW_REV_TYPE_6050: 811 sc->limits = &iwn6000_sensitivity_limits; 812 sc->fwname = "iwn6050fw"; 813 /* Override chains masks, ROM is known to be broken. */ 814 sc->txchainmask = IWN_ANT_AB; 815 sc->rxchainmask = IWN_ANT_AB; 816 break; 817 case IWN_HW_REV_TYPE_6005: 818 sc->limits = &iwn6000_sensitivity_limits; 819 sc->fwname = "iwn6005fw"; 820 if (pid != 0x0082 && pid != 0x0085) 821 sc->sc_flags |= IWN_FLAG_ADV_BTCOEX; 822 break; 823 default: 824 device_printf(sc->sc_dev, "adapter type %d not supported\n", 825 sc->hw_type); 826 return ENOTSUP; 827 } 828 return 0; 829 } 830 831 /* 832 * Attach the interface to 802.11 radiotap. 833 */ 834 static void 835 iwn_radiotap_attach(struct iwn_softc *sc) 836 { 837 struct ifnet *ifp = sc->sc_ifp; 838 struct ieee80211com *ic = ifp->if_l2com; 839 840 ieee80211_radiotap_attach(ic, 841 &sc->sc_txtap.wt_ihdr, sizeof(sc->sc_txtap), 842 IWN_TX_RADIOTAP_PRESENT, 843 &sc->sc_rxtap.wr_ihdr, sizeof(sc->sc_rxtap), 844 IWN_RX_RADIOTAP_PRESENT); 845 } 846 847 static void 848 iwn_sysctlattach(struct iwn_softc *sc) 849 { 850 struct sysctl_ctx_list *ctx = device_get_sysctl_ctx(sc->sc_dev); 851 struct sysctl_oid *tree = device_get_sysctl_tree(sc->sc_dev); 852 853 #ifdef IWN_DEBUG 854 sc->sc_debug = 0; 855 SYSCTL_ADD_INT(ctx, SYSCTL_CHILDREN(tree), OID_AUTO, 856 "debug", CTLFLAG_RW, &sc->sc_debug, 0, "control debugging printfs"); 857 #endif 858 } 859 860 static struct ieee80211vap * 861 iwn_vap_create(struct ieee80211com *ic, 862 const char name[IFNAMSIZ], int unit, int opmode, int flags, 863 const uint8_t bssid[IEEE80211_ADDR_LEN], 864 const uint8_t mac[IEEE80211_ADDR_LEN]) 865 { 866 struct iwn_vap *ivp; 867 struct ieee80211vap *vap; 868 869 if (!TAILQ_EMPTY(&ic->ic_vaps)) /* only one at a time */ 870 return NULL; 871 ivp = (struct iwn_vap *) malloc(sizeof(struct iwn_vap), 872 M_80211_VAP, M_NOWAIT | M_ZERO); 873 if (ivp == NULL) 874 return NULL; 875 vap = &ivp->iv_vap; 876 ieee80211_vap_setup(ic, vap, name, unit, opmode, flags, bssid, mac); 877 vap->iv_bmissthreshold = 10; /* override default */ 878 /* Override with driver methods. */ 879 ivp->iv_newstate = vap->iv_newstate; 880 vap->iv_newstate = iwn_newstate; 881 882 ieee80211_ratectl_init(vap); 883 /* Complete setup. */ 884 ieee80211_vap_attach(vap, iwn_media_change, ieee80211_media_status); 885 ic->ic_opmode = opmode; 886 return vap; 887 } 888 889 static void 890 iwn_vap_delete(struct ieee80211vap *vap) 891 { 892 struct iwn_vap *ivp = IWN_VAP(vap); 893 894 ieee80211_ratectl_deinit(vap); 895 ieee80211_vap_detach(vap); 896 free(ivp, M_80211_VAP); 897 } 898 899 static int 900 iwn_detach(device_t dev) 901 { 902 struct iwn_softc *sc = device_get_softc(dev); 903 struct ifnet *ifp = sc->sc_ifp; 904 struct ieee80211com *ic; 905 int qid; 906 907 if (ifp != NULL) { 908 ic = ifp->if_l2com; 909 910 ieee80211_draintask(ic, &sc->sc_reinit_task); 911 ieee80211_draintask(ic, &sc->sc_radioon_task); 912 ieee80211_draintask(ic, &sc->sc_radiooff_task); 913 914 iwn_stop(sc); 915 callout_drain(&sc->watchdog_to); 916 callout_drain(&sc->calib_to); 917 ieee80211_ifdetach(ic); 918 } 919 920 /* Uninstall interrupt handler. */ 921 if (sc->irq != NULL) { 922 bus_teardown_intr(dev, sc->irq, sc->sc_ih); 923 bus_release_resource(dev, SYS_RES_IRQ, sc->irq_rid, sc->irq); 924 if (sc->irq_rid == 1) 925 pci_release_msi(dev); 926 } 927 928 /* Free DMA resources. */ 929 iwn_free_rx_ring(sc, &sc->rxq); 930 for (qid = 0; qid < sc->ntxqs; qid++) 931 iwn_free_tx_ring(sc, &sc->txq[qid]); 932 iwn_free_sched(sc); 933 iwn_free_kw(sc); 934 if (sc->ict != NULL) 935 iwn_free_ict(sc); 936 iwn_free_fwmem(sc); 937 938 if (sc->mem != NULL) 939 bus_release_resource(dev, SYS_RES_MEMORY, sc->mem_rid, sc->mem); 940 941 if (ifp != NULL) 942 if_free(ifp); 943 944 IWN_LOCK_DESTROY(sc); 945 return 0; 946 } 947 948 static int 949 iwn_shutdown(device_t dev) 950 { 951 struct iwn_softc *sc = device_get_softc(dev); 952 953 iwn_stop(sc); 954 return 0; 955 } 956 957 static int 958 iwn_suspend(device_t dev) 959 { 960 struct iwn_softc *sc = device_get_softc(dev); 961 struct ifnet *ifp = sc->sc_ifp; 962 struct ieee80211com *ic = ifp->if_l2com; 963 struct ieee80211vap *vap = TAILQ_FIRST(&ic->ic_vaps); 964 965 iwn_stop(sc); 966 if (vap != NULL) 967 ieee80211_stop(vap); 968 return 0; 969 } 970 971 static int 972 iwn_resume(device_t dev) 973 { 974 struct iwn_softc *sc = device_get_softc(dev); 975 struct ifnet *ifp = sc->sc_ifp; 976 struct ieee80211com *ic = ifp->if_l2com; 977 struct ieee80211vap *vap = TAILQ_FIRST(&ic->ic_vaps); 978 979 /* Clear device-specific "PCI retry timeout" register (41h). */ 980 pci_write_config(dev, 0x41, 0, 1); 981 982 if (ifp->if_flags & IFF_UP) { 983 iwn_init(sc); 984 if (vap != NULL) 985 ieee80211_init(vap); 986 if (ifp->if_drv_flags & IFF_DRV_RUNNING) 987 iwn_start(ifp); 988 } 989 return 0; 990 } 991 992 static int 993 iwn_nic_lock(struct iwn_softc *sc) 994 { 995 int ntries; 996 997 /* Request exclusive access to NIC. */ 998 IWN_SETBITS(sc, IWN_GP_CNTRL, IWN_GP_CNTRL_MAC_ACCESS_REQ); 999 1000 /* Spin until we actually get the lock. */ 1001 for (ntries = 0; ntries < 1000; ntries++) { 1002 if ((IWN_READ(sc, IWN_GP_CNTRL) & 1003 (IWN_GP_CNTRL_MAC_ACCESS_ENA | IWN_GP_CNTRL_SLEEP)) == 1004 IWN_GP_CNTRL_MAC_ACCESS_ENA) 1005 return 0; 1006 DELAY(10); 1007 } 1008 return ETIMEDOUT; 1009 } 1010 1011 static __inline void 1012 iwn_nic_unlock(struct iwn_softc *sc) 1013 { 1014 IWN_CLRBITS(sc, IWN_GP_CNTRL, IWN_GP_CNTRL_MAC_ACCESS_REQ); 1015 } 1016 1017 static __inline uint32_t 1018 iwn_prph_read(struct iwn_softc *sc, uint32_t addr) 1019 { 1020 IWN_WRITE(sc, IWN_PRPH_RADDR, IWN_PRPH_DWORD | addr); 1021 IWN_BARRIER_READ_WRITE(sc); 1022 return IWN_READ(sc, IWN_PRPH_RDATA); 1023 } 1024 1025 static __inline void 1026 iwn_prph_write(struct iwn_softc *sc, uint32_t addr, uint32_t data) 1027 { 1028 IWN_WRITE(sc, IWN_PRPH_WADDR, IWN_PRPH_DWORD | addr); 1029 IWN_BARRIER_WRITE(sc); 1030 IWN_WRITE(sc, IWN_PRPH_WDATA, data); 1031 } 1032 1033 static __inline void 1034 iwn_prph_setbits(struct iwn_softc *sc, uint32_t addr, uint32_t mask) 1035 { 1036 iwn_prph_write(sc, addr, iwn_prph_read(sc, addr) | mask); 1037 } 1038 1039 static __inline void 1040 iwn_prph_clrbits(struct iwn_softc *sc, uint32_t addr, uint32_t mask) 1041 { 1042 iwn_prph_write(sc, addr, iwn_prph_read(sc, addr) & ~mask); 1043 } 1044 1045 static __inline void 1046 iwn_prph_write_region_4(struct iwn_softc *sc, uint32_t addr, 1047 const uint32_t *data, int count) 1048 { 1049 for (; count > 0; count--, data++, addr += 4) 1050 iwn_prph_write(sc, addr, *data); 1051 } 1052 1053 static __inline uint32_t 1054 iwn_mem_read(struct iwn_softc *sc, uint32_t addr) 1055 { 1056 IWN_WRITE(sc, IWN_MEM_RADDR, addr); 1057 IWN_BARRIER_READ_WRITE(sc); 1058 return IWN_READ(sc, IWN_MEM_RDATA); 1059 } 1060 1061 static __inline void 1062 iwn_mem_write(struct iwn_softc *sc, uint32_t addr, uint32_t data) 1063 { 1064 IWN_WRITE(sc, IWN_MEM_WADDR, addr); 1065 IWN_BARRIER_WRITE(sc); 1066 IWN_WRITE(sc, IWN_MEM_WDATA, data); 1067 } 1068 1069 static __inline void 1070 iwn_mem_write_2(struct iwn_softc *sc, uint32_t addr, uint16_t data) 1071 { 1072 uint32_t tmp; 1073 1074 tmp = iwn_mem_read(sc, addr & ~3); 1075 if (addr & 3) 1076 tmp = (tmp & 0x0000ffff) | data << 16; 1077 else 1078 tmp = (tmp & 0xffff0000) | data; 1079 iwn_mem_write(sc, addr & ~3, tmp); 1080 } 1081 1082 static __inline void 1083 iwn_mem_read_region_4(struct iwn_softc *sc, uint32_t addr, uint32_t *data, 1084 int count) 1085 { 1086 for (; count > 0; count--, addr += 4) 1087 *data++ = iwn_mem_read(sc, addr); 1088 } 1089 1090 static __inline void 1091 iwn_mem_set_region_4(struct iwn_softc *sc, uint32_t addr, uint32_t val, 1092 int count) 1093 { 1094 for (; count > 0; count--, addr += 4) 1095 iwn_mem_write(sc, addr, val); 1096 } 1097 1098 static int 1099 iwn_eeprom_lock(struct iwn_softc *sc) 1100 { 1101 int i, ntries; 1102 1103 for (i = 0; i < 100; i++) { 1104 /* Request exclusive access to EEPROM. */ 1105 IWN_SETBITS(sc, IWN_HW_IF_CONFIG, 1106 IWN_HW_IF_CONFIG_EEPROM_LOCKED); 1107 1108 /* Spin until we actually get the lock. */ 1109 for (ntries = 0; ntries < 100; ntries++) { 1110 if (IWN_READ(sc, IWN_HW_IF_CONFIG) & 1111 IWN_HW_IF_CONFIG_EEPROM_LOCKED) 1112 return 0; 1113 DELAY(10); 1114 } 1115 } 1116 return ETIMEDOUT; 1117 } 1118 1119 static __inline void 1120 iwn_eeprom_unlock(struct iwn_softc *sc) 1121 { 1122 IWN_CLRBITS(sc, IWN_HW_IF_CONFIG, IWN_HW_IF_CONFIG_EEPROM_LOCKED); 1123 } 1124 1125 /* 1126 * Initialize access by host to One Time Programmable ROM. 1127 * NB: This kind of ROM can be found on 1000 or 6000 Series only. 1128 */ 1129 static int 1130 iwn_init_otprom(struct iwn_softc *sc) 1131 { 1132 uint16_t prev, base, next; 1133 int count, error; 1134 1135 /* Wait for clock stabilization before accessing prph. */ 1136 if ((error = iwn_clock_wait(sc)) != 0) 1137 return error; 1138 1139 if ((error = iwn_nic_lock(sc)) != 0) 1140 return error; 1141 iwn_prph_setbits(sc, IWN_APMG_PS, IWN_APMG_PS_RESET_REQ); 1142 DELAY(5); 1143 iwn_prph_clrbits(sc, IWN_APMG_PS, IWN_APMG_PS_RESET_REQ); 1144 iwn_nic_unlock(sc); 1145 1146 /* Set auto clock gate disable bit for HW with OTP shadow RAM. */ 1147 if (sc->hw_type != IWN_HW_REV_TYPE_1000) { 1148 IWN_SETBITS(sc, IWN_DBG_LINK_PWR_MGMT, 1149 IWN_RESET_LINK_PWR_MGMT_DIS); 1150 } 1151 IWN_CLRBITS(sc, IWN_EEPROM_GP, IWN_EEPROM_GP_IF_OWNER); 1152 /* Clear ECC status. */ 1153 IWN_SETBITS(sc, IWN_OTP_GP, 1154 IWN_OTP_GP_ECC_CORR_STTS | IWN_OTP_GP_ECC_UNCORR_STTS); 1155 1156 /* 1157 * Find the block before last block (contains the EEPROM image) 1158 * for HW without OTP shadow RAM. 1159 */ 1160 if (sc->hw_type == IWN_HW_REV_TYPE_1000) { 1161 /* Switch to absolute addressing mode. */ 1162 IWN_CLRBITS(sc, IWN_OTP_GP, IWN_OTP_GP_RELATIVE_ACCESS); 1163 base = prev = 0; 1164 for (count = 0; count < IWN1000_OTP_NBLOCKS; count++) { 1165 error = iwn_read_prom_data(sc, base, &next, 2); 1166 if (error != 0) 1167 return error; 1168 if (next == 0) /* End of linked-list. */ 1169 break; 1170 prev = base; 1171 base = le16toh(next); 1172 } 1173 if (count == 0 || count == IWN1000_OTP_NBLOCKS) 1174 return EIO; 1175 /* Skip "next" word. */ 1176 sc->prom_base = prev + 1; 1177 } 1178 return 0; 1179 } 1180 1181 static int 1182 iwn_read_prom_data(struct iwn_softc *sc, uint32_t addr, void *data, int count) 1183 { 1184 uint8_t *out = data; 1185 uint32_t val, tmp; 1186 int ntries; 1187 1188 addr += sc->prom_base; 1189 for (; count > 0; count -= 2, addr++) { 1190 IWN_WRITE(sc, IWN_EEPROM, addr << 2); 1191 for (ntries = 0; ntries < 10; ntries++) { 1192 val = IWN_READ(sc, IWN_EEPROM); 1193 if (val & IWN_EEPROM_READ_VALID) 1194 break; 1195 DELAY(5); 1196 } 1197 if (ntries == 10) { 1198 device_printf(sc->sc_dev, 1199 "timeout reading ROM at 0x%x\n", addr); 1200 return ETIMEDOUT; 1201 } 1202 if (sc->sc_flags & IWN_FLAG_HAS_OTPROM) { 1203 /* OTPROM, check for ECC errors. */ 1204 tmp = IWN_READ(sc, IWN_OTP_GP); 1205 if (tmp & IWN_OTP_GP_ECC_UNCORR_STTS) { 1206 device_printf(sc->sc_dev, 1207 "OTPROM ECC error at 0x%x\n", addr); 1208 return EIO; 1209 } 1210 if (tmp & IWN_OTP_GP_ECC_CORR_STTS) { 1211 /* Correctable ECC error, clear bit. */ 1212 IWN_SETBITS(sc, IWN_OTP_GP, 1213 IWN_OTP_GP_ECC_CORR_STTS); 1214 } 1215 } 1216 *out++ = val >> 16; 1217 if (count > 1) 1218 *out++ = val >> 24; 1219 } 1220 return 0; 1221 } 1222 1223 static void 1224 iwn_dma_map_addr(void *arg, bus_dma_segment_t *segs, int nsegs, int error) 1225 { 1226 if (error != 0) 1227 return; 1228 KASSERT(nsegs == 1, ("too many DMA segments, %d should be 1", nsegs)); 1229 *(bus_addr_t *)arg = segs[0].ds_addr; 1230 } 1231 1232 static int 1233 iwn_dma_contig_alloc(struct iwn_softc *sc, struct iwn_dma_info *dma, 1234 void **kvap, bus_size_t size, bus_size_t alignment) 1235 { 1236 int error; 1237 1238 dma->tag = NULL; 1239 dma->size = size; 1240 1241 error = bus_dma_tag_create(bus_get_dma_tag(sc->sc_dev), alignment, 1242 0, BUS_SPACE_MAXADDR_32BIT, BUS_SPACE_MAXADDR, NULL, NULL, size, 1243 1, size, BUS_DMA_NOWAIT, NULL, NULL, &dma->tag); 1244 if (error != 0) 1245 goto fail; 1246 1247 error = bus_dmamem_alloc(dma->tag, (void **)&dma->vaddr, 1248 BUS_DMA_NOWAIT | BUS_DMA_ZERO | BUS_DMA_COHERENT, &dma->map); 1249 if (error != 0) 1250 goto fail; 1251 1252 error = bus_dmamap_load(dma->tag, dma->map, dma->vaddr, size, 1253 iwn_dma_map_addr, &dma->paddr, BUS_DMA_NOWAIT); 1254 if (error != 0) 1255 goto fail; 1256 1257 bus_dmamap_sync(dma->tag, dma->map, BUS_DMASYNC_PREWRITE); 1258 1259 if (kvap != NULL) 1260 *kvap = dma->vaddr; 1261 1262 return 0; 1263 1264 fail: iwn_dma_contig_free(dma); 1265 return error; 1266 } 1267 1268 static void 1269 iwn_dma_contig_free(struct iwn_dma_info *dma) 1270 { 1271 if (dma->map != NULL) { 1272 if (dma->vaddr != NULL) { 1273 bus_dmamap_sync(dma->tag, dma->map, 1274 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); 1275 bus_dmamap_unload(dma->tag, dma->map); 1276 bus_dmamem_free(dma->tag, &dma->vaddr, dma->map); 1277 dma->vaddr = NULL; 1278 } 1279 bus_dmamap_destroy(dma->tag, dma->map); 1280 dma->map = NULL; 1281 } 1282 if (dma->tag != NULL) { 1283 bus_dma_tag_destroy(dma->tag); 1284 dma->tag = NULL; 1285 } 1286 } 1287 1288 static int 1289 iwn_alloc_sched(struct iwn_softc *sc) 1290 { 1291 /* TX scheduler rings must be aligned on a 1KB boundary. */ 1292 return iwn_dma_contig_alloc(sc, &sc->sched_dma, (void **)&sc->sched, 1293 sc->schedsz, 1024); 1294 } 1295 1296 static void 1297 iwn_free_sched(struct iwn_softc *sc) 1298 { 1299 iwn_dma_contig_free(&sc->sched_dma); 1300 } 1301 1302 static int 1303 iwn_alloc_kw(struct iwn_softc *sc) 1304 { 1305 /* "Keep Warm" page must be aligned on a 4KB boundary. */ 1306 return iwn_dma_contig_alloc(sc, &sc->kw_dma, NULL, 4096, 4096); 1307 } 1308 1309 static void 1310 iwn_free_kw(struct iwn_softc *sc) 1311 { 1312 iwn_dma_contig_free(&sc->kw_dma); 1313 } 1314 1315 static int 1316 iwn_alloc_ict(struct iwn_softc *sc) 1317 { 1318 /* ICT table must be aligned on a 4KB boundary. */ 1319 return iwn_dma_contig_alloc(sc, &sc->ict_dma, (void **)&sc->ict, 1320 IWN_ICT_SIZE, 4096); 1321 } 1322 1323 static void 1324 iwn_free_ict(struct iwn_softc *sc) 1325 { 1326 iwn_dma_contig_free(&sc->ict_dma); 1327 } 1328 1329 static int 1330 iwn_alloc_fwmem(struct iwn_softc *sc) 1331 { 1332 /* Must be aligned on a 16-byte boundary. */ 1333 return iwn_dma_contig_alloc(sc, &sc->fw_dma, NULL, sc->fwsz, 16); 1334 } 1335 1336 static void 1337 iwn_free_fwmem(struct iwn_softc *sc) 1338 { 1339 iwn_dma_contig_free(&sc->fw_dma); 1340 } 1341 1342 static int 1343 iwn_alloc_rx_ring(struct iwn_softc *sc, struct iwn_rx_ring *ring) 1344 { 1345 bus_size_t size; 1346 int i, error; 1347 1348 ring->cur = 0; 1349 1350 /* Allocate RX descriptors (256-byte aligned). */ 1351 size = IWN_RX_RING_COUNT * sizeof (uint32_t); 1352 error = iwn_dma_contig_alloc(sc, &ring->desc_dma, (void **)&ring->desc, 1353 size, 256); 1354 if (error != 0) { 1355 device_printf(sc->sc_dev, 1356 "%s: could not allocate RX ring DMA memory, error %d\n", 1357 __func__, error); 1358 goto fail; 1359 } 1360 1361 /* Allocate RX status area (16-byte aligned). */ 1362 error = iwn_dma_contig_alloc(sc, &ring->stat_dma, (void **)&ring->stat, 1363 sizeof (struct iwn_rx_status), 16); 1364 if (error != 0) { 1365 device_printf(sc->sc_dev, 1366 "%s: could not allocate RX status DMA memory, error %d\n", 1367 __func__, error); 1368 goto fail; 1369 } 1370 1371 /* Create RX buffer DMA tag. */ 1372 error = bus_dma_tag_create(bus_get_dma_tag(sc->sc_dev), 1, 0, 1373 BUS_SPACE_MAXADDR_32BIT, BUS_SPACE_MAXADDR, NULL, NULL, 1374 IWN_RBUF_SIZE, 1, IWN_RBUF_SIZE, BUS_DMA_NOWAIT, NULL, NULL, 1375 &ring->data_dmat); 1376 if (error != 0) { 1377 device_printf(sc->sc_dev, 1378 "%s: could not create RX buf DMA tag, error %d\n", 1379 __func__, error); 1380 goto fail; 1381 } 1382 1383 /* 1384 * Allocate and map RX buffers. 1385 */ 1386 for (i = 0; i < IWN_RX_RING_COUNT; i++) { 1387 struct iwn_rx_data *data = &ring->data[i]; 1388 bus_addr_t paddr; 1389 1390 error = bus_dmamap_create(ring->data_dmat, 0, &data->map); 1391 if (error != 0) { 1392 device_printf(sc->sc_dev, 1393 "%s: could not create RX buf DMA map, error %d\n", 1394 __func__, error); 1395 goto fail; 1396 } 1397 1398 data->m = m_getjcl(M_DONTWAIT, MT_DATA, M_PKTHDR, 1399 IWN_RBUF_SIZE); 1400 if (data->m == NULL) { 1401 device_printf(sc->sc_dev, 1402 "%s: could not allocate RX mbuf\n", __func__); 1403 error = ENOBUFS; 1404 goto fail; 1405 } 1406 1407 error = bus_dmamap_load(ring->data_dmat, data->map, 1408 mtod(data->m, void *), IWN_RBUF_SIZE, iwn_dma_map_addr, 1409 &paddr, BUS_DMA_NOWAIT); 1410 if (error != 0 && error != EFBIG) { 1411 device_printf(sc->sc_dev, 1412 "%s: can't not map mbuf, error %d\n", __func__, 1413 error); 1414 goto fail; 1415 } 1416 1417 /* Set physical address of RX buffer (256-byte aligned). */ 1418 ring->desc[i] = htole32(paddr >> 8); 1419 } 1420 1421 bus_dmamap_sync(ring->desc_dma.tag, ring->desc_dma.map, 1422 BUS_DMASYNC_PREWRITE); 1423 1424 return 0; 1425 1426 fail: iwn_free_rx_ring(sc, ring); 1427 return error; 1428 } 1429 1430 static void 1431 iwn_reset_rx_ring(struct iwn_softc *sc, struct iwn_rx_ring *ring) 1432 { 1433 int ntries; 1434 1435 if (iwn_nic_lock(sc) == 0) { 1436 IWN_WRITE(sc, IWN_FH_RX_CONFIG, 0); 1437 for (ntries = 0; ntries < 1000; ntries++) { 1438 if (IWN_READ(sc, IWN_FH_RX_STATUS) & 1439 IWN_FH_RX_STATUS_IDLE) 1440 break; 1441 DELAY(10); 1442 } 1443 iwn_nic_unlock(sc); 1444 } 1445 ring->cur = 0; 1446 sc->last_rx_valid = 0; 1447 } 1448 1449 static void 1450 iwn_free_rx_ring(struct iwn_softc *sc, struct iwn_rx_ring *ring) 1451 { 1452 int i; 1453 1454 iwn_dma_contig_free(&ring->desc_dma); 1455 iwn_dma_contig_free(&ring->stat_dma); 1456 1457 for (i = 0; i < IWN_RX_RING_COUNT; i++) { 1458 struct iwn_rx_data *data = &ring->data[i]; 1459 1460 if (data->m != NULL) { 1461 bus_dmamap_sync(ring->data_dmat, data->map, 1462 BUS_DMASYNC_POSTREAD); 1463 bus_dmamap_unload(ring->data_dmat, data->map); 1464 m_freem(data->m); 1465 data->m = NULL; 1466 } 1467 if (data->map != NULL) 1468 bus_dmamap_destroy(ring->data_dmat, data->map); 1469 } 1470 if (ring->data_dmat != NULL) { 1471 bus_dma_tag_destroy(ring->data_dmat); 1472 ring->data_dmat = NULL; 1473 } 1474 } 1475 1476 static int 1477 iwn_alloc_tx_ring(struct iwn_softc *sc, struct iwn_tx_ring *ring, int qid) 1478 { 1479 bus_addr_t paddr; 1480 bus_size_t size; 1481 int i, error; 1482 1483 ring->qid = qid; 1484 ring->queued = 0; 1485 ring->cur = 0; 1486 1487 /* Allocate TX descriptors (256-byte aligned). */ 1488 size = IWN_TX_RING_COUNT * sizeof (struct iwn_tx_desc); 1489 error = iwn_dma_contig_alloc(sc, &ring->desc_dma, (void **)&ring->desc, 1490 size, 256); 1491 if (error != 0) { 1492 device_printf(sc->sc_dev, 1493 "%s: could not allocate TX ring DMA memory, error %d\n", 1494 __func__, error); 1495 goto fail; 1496 } 1497 /* 1498 * We only use rings 0 through 4 (4 EDCA + cmd) so there is no need 1499 * to allocate commands space for other rings. 1500 * XXX Do we really need to allocate descriptors for other rings? 1501 */ 1502 if (qid > 4) 1503 return 0; 1504 1505 size = IWN_TX_RING_COUNT * sizeof (struct iwn_tx_cmd); 1506 error = iwn_dma_contig_alloc(sc, &ring->cmd_dma, (void **)&ring->cmd, 1507 size, 4); 1508 if (error != 0) { 1509 device_printf(sc->sc_dev, 1510 "%s: could not allocate TX cmd DMA memory, error %d\n", 1511 __func__, error); 1512 goto fail; 1513 } 1514 1515 error = bus_dma_tag_create(bus_get_dma_tag(sc->sc_dev), 1, 0, 1516 BUS_SPACE_MAXADDR_32BIT, BUS_SPACE_MAXADDR, NULL, NULL, MCLBYTES, 1517 IWN_MAX_SCATTER - 1, MCLBYTES, BUS_DMA_NOWAIT, NULL, NULL, 1518 &ring->data_dmat); 1519 if (error != 0) { 1520 device_printf(sc->sc_dev, 1521 "%s: could not create TX buf DMA tag, error %d\n", 1522 __func__, error); 1523 goto fail; 1524 } 1525 1526 paddr = ring->cmd_dma.paddr; 1527 for (i = 0; i < IWN_TX_RING_COUNT; i++) { 1528 struct iwn_tx_data *data = &ring->data[i]; 1529 1530 data->cmd_paddr = paddr; 1531 data->scratch_paddr = paddr + 12; 1532 paddr += sizeof (struct iwn_tx_cmd); 1533 1534 error = bus_dmamap_create(ring->data_dmat, 0, &data->map); 1535 if (error != 0) { 1536 device_printf(sc->sc_dev, 1537 "%s: could not create TX buf DMA map, error %d\n", 1538 __func__, error); 1539 goto fail; 1540 } 1541 } 1542 return 0; 1543 1544 fail: iwn_free_tx_ring(sc, ring); 1545 return error; 1546 } 1547 1548 static void 1549 iwn_reset_tx_ring(struct iwn_softc *sc, struct iwn_tx_ring *ring) 1550 { 1551 int i; 1552 1553 for (i = 0; i < IWN_TX_RING_COUNT; i++) { 1554 struct iwn_tx_data *data = &ring->data[i]; 1555 1556 if (data->m != NULL) { 1557 bus_dmamap_sync(ring->data_dmat, data->map, 1558 BUS_DMASYNC_POSTWRITE); 1559 bus_dmamap_unload(ring->data_dmat, data->map); 1560 m_freem(data->m); 1561 data->m = NULL; 1562 } 1563 } 1564 /* Clear TX descriptors. */ 1565 memset(ring->desc, 0, ring->desc_dma.size); 1566 bus_dmamap_sync(ring->desc_dma.tag, ring->desc_dma.map, 1567 BUS_DMASYNC_PREWRITE); 1568 sc->qfullmsk &= ~(1 << ring->qid); 1569 ring->queued = 0; 1570 ring->cur = 0; 1571 } 1572 1573 static void 1574 iwn_free_tx_ring(struct iwn_softc *sc, struct iwn_tx_ring *ring) 1575 { 1576 int i; 1577 1578 iwn_dma_contig_free(&ring->desc_dma); 1579 iwn_dma_contig_free(&ring->cmd_dma); 1580 1581 for (i = 0; i < IWN_TX_RING_COUNT; i++) { 1582 struct iwn_tx_data *data = &ring->data[i]; 1583 1584 if (data->m != NULL) { 1585 bus_dmamap_sync(ring->data_dmat, data->map, 1586 BUS_DMASYNC_POSTWRITE); 1587 bus_dmamap_unload(ring->data_dmat, data->map); 1588 m_freem(data->m); 1589 } 1590 if (data->map != NULL) 1591 bus_dmamap_destroy(ring->data_dmat, data->map); 1592 } 1593 if (ring->data_dmat != NULL) { 1594 bus_dma_tag_destroy(ring->data_dmat); 1595 ring->data_dmat = NULL; 1596 } 1597 } 1598 1599 static void 1600 iwn5000_ict_reset(struct iwn_softc *sc) 1601 { 1602 /* Disable interrupts. */ 1603 IWN_WRITE(sc, IWN_INT_MASK, 0); 1604 1605 /* Reset ICT table. */ 1606 memset(sc->ict, 0, IWN_ICT_SIZE); 1607 sc->ict_cur = 0; 1608 1609 /* Set physical address of ICT table (4KB aligned). */ 1610 DPRINTF(sc, IWN_DEBUG_RESET, "%s: enabling ICT\n", __func__); 1611 IWN_WRITE(sc, IWN_DRAM_INT_TBL, IWN_DRAM_INT_TBL_ENABLE | 1612 IWN_DRAM_INT_TBL_WRAP_CHECK | sc->ict_dma.paddr >> 12); 1613 1614 /* Enable periodic RX interrupt. */ 1615 sc->int_mask |= IWN_INT_RX_PERIODIC; 1616 /* Switch to ICT interrupt mode in driver. */ 1617 sc->sc_flags |= IWN_FLAG_USE_ICT; 1618 1619 /* Re-enable interrupts. */ 1620 IWN_WRITE(sc, IWN_INT, 0xffffffff); 1621 IWN_WRITE(sc, IWN_INT_MASK, sc->int_mask); 1622 } 1623 1624 static int 1625 iwn_read_eeprom(struct iwn_softc *sc, uint8_t macaddr[IEEE80211_ADDR_LEN]) 1626 { 1627 struct iwn_ops *ops = &sc->ops; 1628 uint16_t val; 1629 int error; 1630 1631 /* Check whether adapter has an EEPROM or an OTPROM. */ 1632 if (sc->hw_type >= IWN_HW_REV_TYPE_1000 && 1633 (IWN_READ(sc, IWN_OTP_GP) & IWN_OTP_GP_DEV_SEL_OTP)) 1634 sc->sc_flags |= IWN_FLAG_HAS_OTPROM; 1635 DPRINTF(sc, IWN_DEBUG_RESET, "%s found\n", 1636 (sc->sc_flags & IWN_FLAG_HAS_OTPROM) ? "OTPROM" : "EEPROM"); 1637 1638 /* Adapter has to be powered on for EEPROM access to work. */ 1639 if ((error = iwn_apm_init(sc)) != 0) { 1640 device_printf(sc->sc_dev, 1641 "%s: could not power ON adapter, error %d\n", __func__, 1642 error); 1643 return error; 1644 } 1645 1646 if ((IWN_READ(sc, IWN_EEPROM_GP) & 0x7) == 0) { 1647 device_printf(sc->sc_dev, "%s: bad ROM signature\n", __func__); 1648 return EIO; 1649 } 1650 if ((error = iwn_eeprom_lock(sc)) != 0) { 1651 device_printf(sc->sc_dev, "%s: could not lock ROM, error %d\n", 1652 __func__, error); 1653 return error; 1654 } 1655 if (sc->sc_flags & IWN_FLAG_HAS_OTPROM) { 1656 if ((error = iwn_init_otprom(sc)) != 0) { 1657 device_printf(sc->sc_dev, 1658 "%s: could not initialize OTPROM, error %d\n", 1659 __func__, error); 1660 return error; 1661 } 1662 } 1663 1664 iwn_read_prom_data(sc, IWN_EEPROM_SKU_CAP, &val, 2); 1665 DPRINTF(sc, IWN_DEBUG_RESET, "SKU capabilities=0x%04x\n", le16toh(val)); 1666 /* Check if HT support is bonded out. */ 1667 if (val & htole16(IWN_EEPROM_SKU_CAP_11N)) 1668 sc->sc_flags |= IWN_FLAG_HAS_11N; 1669 1670 iwn_read_prom_data(sc, IWN_EEPROM_RFCFG, &val, 2); 1671 sc->rfcfg = le16toh(val); 1672 DPRINTF(sc, IWN_DEBUG_RESET, "radio config=0x%04x\n", sc->rfcfg); 1673 /* Read Tx/Rx chains from ROM unless it's known to be broken. */ 1674 if (sc->txchainmask == 0) 1675 sc->txchainmask = IWN_RFCFG_TXANTMSK(sc->rfcfg); 1676 if (sc->rxchainmask == 0) 1677 sc->rxchainmask = IWN_RFCFG_RXANTMSK(sc->rfcfg); 1678 1679 /* Read MAC address. */ 1680 iwn_read_prom_data(sc, IWN_EEPROM_MAC, macaddr, 6); 1681 1682 /* Read adapter-specific information from EEPROM. */ 1683 ops->read_eeprom(sc); 1684 1685 iwn_apm_stop(sc); /* Power OFF adapter. */ 1686 1687 iwn_eeprom_unlock(sc); 1688 return 0; 1689 } 1690 1691 static void 1692 iwn4965_read_eeprom(struct iwn_softc *sc) 1693 { 1694 uint32_t addr; 1695 uint16_t val; 1696 int i; 1697 1698 /* Read regulatory domain (4 ASCII characters). */ 1699 iwn_read_prom_data(sc, IWN4965_EEPROM_DOMAIN, sc->eeprom_domain, 4); 1700 1701 /* Read the list of authorized channels (20MHz ones only). */ 1702 for (i = 0; i < 5; i++) { 1703 addr = iwn4965_regulatory_bands[i]; 1704 iwn_read_eeprom_channels(sc, i, addr); 1705 } 1706 1707 /* Read maximum allowed TX power for 2GHz and 5GHz bands. */ 1708 iwn_read_prom_data(sc, IWN4965_EEPROM_MAXPOW, &val, 2); 1709 sc->maxpwr2GHz = val & 0xff; 1710 sc->maxpwr5GHz = val >> 8; 1711 /* Check that EEPROM values are within valid range. */ 1712 if (sc->maxpwr5GHz < 20 || sc->maxpwr5GHz > 50) 1713 sc->maxpwr5GHz = 38; 1714 if (sc->maxpwr2GHz < 20 || sc->maxpwr2GHz > 50) 1715 sc->maxpwr2GHz = 38; 1716 DPRINTF(sc, IWN_DEBUG_RESET, "maxpwr 2GHz=%d 5GHz=%d\n", 1717 sc->maxpwr2GHz, sc->maxpwr5GHz); 1718 1719 /* Read samples for each TX power group. */ 1720 iwn_read_prom_data(sc, IWN4965_EEPROM_BANDS, sc->bands, 1721 sizeof sc->bands); 1722 1723 /* Read voltage at which samples were taken. */ 1724 iwn_read_prom_data(sc, IWN4965_EEPROM_VOLTAGE, &val, 2); 1725 sc->eeprom_voltage = (int16_t)le16toh(val); 1726 DPRINTF(sc, IWN_DEBUG_RESET, "voltage=%d (in 0.3V)\n", 1727 sc->eeprom_voltage); 1728 1729 #ifdef IWN_DEBUG 1730 /* Print samples. */ 1731 if (sc->sc_debug & IWN_DEBUG_ANY) { 1732 for (i = 0; i < IWN_NBANDS; i++) 1733 iwn4965_print_power_group(sc, i); 1734 } 1735 #endif 1736 } 1737 1738 #ifdef IWN_DEBUG 1739 static void 1740 iwn4965_print_power_group(struct iwn_softc *sc, int i) 1741 { 1742 struct iwn4965_eeprom_band *band = &sc->bands[i]; 1743 struct iwn4965_eeprom_chan_samples *chans = band->chans; 1744 int j, c; 1745 1746 printf("===band %d===\n", i); 1747 printf("chan lo=%d, chan hi=%d\n", band->lo, band->hi); 1748 printf("chan1 num=%d\n", chans[0].num); 1749 for (c = 0; c < 2; c++) { 1750 for (j = 0; j < IWN_NSAMPLES; j++) { 1751 printf("chain %d, sample %d: temp=%d gain=%d " 1752 "power=%d pa_det=%d\n", c, j, 1753 chans[0].samples[c][j].temp, 1754 chans[0].samples[c][j].gain, 1755 chans[0].samples[c][j].power, 1756 chans[0].samples[c][j].pa_det); 1757 } 1758 } 1759 printf("chan2 num=%d\n", chans[1].num); 1760 for (c = 0; c < 2; c++) { 1761 for (j = 0; j < IWN_NSAMPLES; j++) { 1762 printf("chain %d, sample %d: temp=%d gain=%d " 1763 "power=%d pa_det=%d\n", c, j, 1764 chans[1].samples[c][j].temp, 1765 chans[1].samples[c][j].gain, 1766 chans[1].samples[c][j].power, 1767 chans[1].samples[c][j].pa_det); 1768 } 1769 } 1770 } 1771 #endif 1772 1773 static void 1774 iwn5000_read_eeprom(struct iwn_softc *sc) 1775 { 1776 struct iwn5000_eeprom_calib_hdr hdr; 1777 int32_t volt; 1778 uint32_t base, addr; 1779 uint16_t val; 1780 int i; 1781 1782 /* Read regulatory domain (4 ASCII characters). */ 1783 iwn_read_prom_data(sc, IWN5000_EEPROM_REG, &val, 2); 1784 base = le16toh(val); 1785 iwn_read_prom_data(sc, base + IWN5000_EEPROM_DOMAIN, 1786 sc->eeprom_domain, 4); 1787 1788 /* Read the list of authorized channels (20MHz ones only). */ 1789 for (i = 0; i < 5; i++) { 1790 addr = base + iwn5000_regulatory_bands[i]; 1791 iwn_read_eeprom_channels(sc, i, addr); 1792 } 1793 1794 /* Read enhanced TX power information for 6000 Series. */ 1795 if (sc->hw_type >= IWN_HW_REV_TYPE_6000) 1796 iwn_read_eeprom_enhinfo(sc); 1797 1798 iwn_read_prom_data(sc, IWN5000_EEPROM_CAL, &val, 2); 1799 base = le16toh(val); 1800 iwn_read_prom_data(sc, base, &hdr, sizeof hdr); 1801 DPRINTF(sc, IWN_DEBUG_CALIBRATE, 1802 "%s: calib version=%u pa type=%u voltage=%u\n", __func__, 1803 hdr.version, hdr.pa_type, le16toh(hdr.volt)); 1804 sc->calib_ver = hdr.version; 1805 1806 if (sc->hw_type == IWN_HW_REV_TYPE_5150) { 1807 /* Compute temperature offset. */ 1808 iwn_read_prom_data(sc, base + IWN5000_EEPROM_TEMP, &val, 2); 1809 sc->eeprom_temp = le16toh(val); 1810 iwn_read_prom_data(sc, base + IWN5000_EEPROM_VOLT, &val, 2); 1811 volt = le16toh(val); 1812 sc->temp_off = sc->eeprom_temp - (volt / -5); 1813 DPRINTF(sc, IWN_DEBUG_CALIBRATE, "temp=%d volt=%d offset=%dK\n", 1814 sc->eeprom_temp, volt, sc->temp_off); 1815 } else { 1816 /* Read crystal calibration. */ 1817 iwn_read_prom_data(sc, base + IWN5000_EEPROM_CRYSTAL, 1818 &sc->eeprom_crystal, sizeof (uint32_t)); 1819 DPRINTF(sc, IWN_DEBUG_CALIBRATE, "crystal calibration 0x%08x\n", 1820 le32toh(sc->eeprom_crystal)); 1821 } 1822 } 1823 1824 /* 1825 * Translate EEPROM flags to net80211. 1826 */ 1827 static uint32_t 1828 iwn_eeprom_channel_flags(struct iwn_eeprom_chan *channel) 1829 { 1830 uint32_t nflags; 1831 1832 nflags = 0; 1833 if ((channel->flags & IWN_EEPROM_CHAN_ACTIVE) == 0) 1834 nflags |= IEEE80211_CHAN_PASSIVE; 1835 if ((channel->flags & IWN_EEPROM_CHAN_IBSS) == 0) 1836 nflags |= IEEE80211_CHAN_NOADHOC; 1837 if (channel->flags & IWN_EEPROM_CHAN_RADAR) { 1838 nflags |= IEEE80211_CHAN_DFS; 1839 /* XXX apparently IBSS may still be marked */ 1840 nflags |= IEEE80211_CHAN_NOADHOC; 1841 } 1842 1843 return nflags; 1844 } 1845 1846 static void 1847 iwn_read_eeprom_band(struct iwn_softc *sc, int n) 1848 { 1849 struct ifnet *ifp = sc->sc_ifp; 1850 struct ieee80211com *ic = ifp->if_l2com; 1851 struct iwn_eeprom_chan *channels = sc->eeprom_channels[n]; 1852 const struct iwn_chan_band *band = &iwn_bands[n]; 1853 struct ieee80211_channel *c; 1854 uint8_t chan; 1855 int i, nflags; 1856 1857 for (i = 0; i < band->nchan; i++) { 1858 if (!(channels[i].flags & IWN_EEPROM_CHAN_VALID)) { 1859 DPRINTF(sc, IWN_DEBUG_RESET, 1860 "skip chan %d flags 0x%x maxpwr %d\n", 1861 band->chan[i], channels[i].flags, 1862 channels[i].maxpwr); 1863 continue; 1864 } 1865 chan = band->chan[i]; 1866 nflags = iwn_eeprom_channel_flags(&channels[i]); 1867 1868 c = &ic->ic_channels[ic->ic_nchans++]; 1869 c->ic_ieee = chan; 1870 c->ic_maxregpower = channels[i].maxpwr; 1871 c->ic_maxpower = 2*c->ic_maxregpower; 1872 1873 if (n == 0) { /* 2GHz band */ 1874 c->ic_freq = ieee80211_ieee2mhz(chan, IEEE80211_CHAN_G); 1875 /* G =>'s B is supported */ 1876 c->ic_flags = IEEE80211_CHAN_B | nflags; 1877 c = &ic->ic_channels[ic->ic_nchans++]; 1878 c[0] = c[-1]; 1879 c->ic_flags = IEEE80211_CHAN_G | nflags; 1880 } else { /* 5GHz band */ 1881 c->ic_freq = ieee80211_ieee2mhz(chan, IEEE80211_CHAN_A); 1882 c->ic_flags = IEEE80211_CHAN_A | nflags; 1883 } 1884 1885 /* Save maximum allowed TX power for this channel. */ 1886 sc->maxpwr[chan] = channels[i].maxpwr; 1887 1888 DPRINTF(sc, IWN_DEBUG_RESET, 1889 "add chan %d flags 0x%x maxpwr %d\n", chan, 1890 channels[i].flags, channels[i].maxpwr); 1891 1892 #if 0 /* HT */ 1893 /* XXX no constraints on using HT20 */ 1894 /* add HT20, HT40 added separately */ 1895 c = &ic->ic_channels[ic->ic_nchans++]; 1896 c[0] = c[-1]; 1897 c->ic_flags |= IEEE80211_CHAN_HT20; 1898 /* XXX NARROW =>'s 1/2 and 1/4 width? */ 1899 #endif 1900 } 1901 } 1902 1903 #if 0 /* HT */ 1904 static void 1905 iwn_read_eeprom_ht40(struct iwn_softc *sc, int n) 1906 { 1907 struct ifnet *ifp = sc->sc_ifp; 1908 struct ieee80211com *ic = ifp->if_l2com; 1909 struct iwn_eeprom_chan *channels = sc->eeprom_channels[n]; 1910 const struct iwn_chan_band *band = &iwn_bands[n]; 1911 struct ieee80211_channel *c, *cent, *extc; 1912 int i; 1913 1914 for (i = 0; i < band->nchan; i++) { 1915 if (!(channels[i].flags & IWN_EEPROM_CHAN_VALID) || 1916 !(channels[i].flags & IWN_EEPROM_CHAN_WIDE)) { 1917 DPRINTF(sc, IWN_DEBUG_RESET, 1918 "skip chan %d flags 0x%x maxpwr %d\n", 1919 band->chan[i], channels[i].flags, 1920 channels[i].maxpwr); 1921 continue; 1922 } 1923 /* 1924 * Each entry defines an HT40 channel pair; find the 1925 * center channel, then the extension channel above. 1926 */ 1927 cent = ieee80211_find_channel_byieee(ic, band->chan[i], 1928 band->flags & ~IEEE80211_CHAN_HT); 1929 if (cent == NULL) { /* XXX shouldn't happen */ 1930 device_printf(sc->sc_dev, 1931 "%s: no entry for channel %d\n", 1932 __func__, band->chan[i]); 1933 continue; 1934 } 1935 extc = ieee80211_find_channel(ic, cent->ic_freq+20, 1936 band->flags & ~IEEE80211_CHAN_HT); 1937 if (extc == NULL) { 1938 DPRINTF(sc, IWN_DEBUG_RESET, 1939 "skip chan %d, extension channel not found\n", 1940 band->chan[i]); 1941 continue; 1942 } 1943 1944 DPRINTF(sc, IWN_DEBUG_RESET, 1945 "add ht40 chan %d flags 0x%x maxpwr %d\n", 1946 band->chan[i], channels[i].flags, channels[i].maxpwr); 1947 1948 c = &ic->ic_channels[ic->ic_nchans++]; 1949 c[0] = cent[0]; 1950 c->ic_extieee = extc->ic_ieee; 1951 c->ic_flags &= ~IEEE80211_CHAN_HT; 1952 c->ic_flags |= IEEE80211_CHAN_HT40U; 1953 c = &ic->ic_channels[ic->ic_nchans++]; 1954 c[0] = extc[0]; 1955 c->ic_extieee = cent->ic_ieee; 1956 c->ic_flags &= ~IEEE80211_CHAN_HT; 1957 c->ic_flags |= IEEE80211_CHAN_HT40D; 1958 } 1959 } 1960 #endif 1961 1962 static void 1963 iwn_read_eeprom_channels(struct iwn_softc *sc, int n, uint32_t addr) 1964 { 1965 struct ifnet *ifp = sc->sc_ifp; 1966 struct ieee80211com *ic = ifp->if_l2com; 1967 1968 iwn_read_prom_data(sc, addr, &sc->eeprom_channels[n], 1969 iwn_bands[n].nchan * sizeof (struct iwn_eeprom_chan)); 1970 1971 if (n < 5) 1972 iwn_read_eeprom_band(sc, n); 1973 #if 0 /* HT */ 1974 else 1975 iwn_read_eeprom_ht40(sc, n); 1976 #endif 1977 ieee80211_sort_channels(ic->ic_channels, ic->ic_nchans); 1978 } 1979 1980 static struct iwn_eeprom_chan * 1981 iwn_find_eeprom_channel(struct iwn_softc *sc, struct ieee80211_channel *c) 1982 { 1983 int i, j; 1984 1985 for (j = 0; j < 7; j++) { 1986 for (i = 0; i < iwn_bands[j].nchan; i++) { 1987 if (iwn_bands[j].chan[i] == c->ic_ieee) 1988 return &sc->eeprom_channels[j][i]; 1989 } 1990 } 1991 1992 return NULL; 1993 } 1994 1995 /* 1996 * Enforce flags read from EEPROM. 1997 */ 1998 static int 1999 iwn_setregdomain(struct ieee80211com *ic, struct ieee80211_regdomain *rd, 2000 int nchan, struct ieee80211_channel chans[]) 2001 { 2002 struct iwn_softc *sc = ic->ic_ifp->if_softc; 2003 int i; 2004 2005 for (i = 0; i < nchan; i++) { 2006 struct ieee80211_channel *c = &chans[i]; 2007 struct iwn_eeprom_chan *channel; 2008 2009 channel = iwn_find_eeprom_channel(sc, c); 2010 if (channel == NULL) { 2011 if_printf(ic->ic_ifp, 2012 "%s: invalid channel %u freq %u/0x%x\n", 2013 __func__, c->ic_ieee, c->ic_freq, c->ic_flags); 2014 return EINVAL; 2015 } 2016 c->ic_flags |= iwn_eeprom_channel_flags(channel); 2017 } 2018 2019 return 0; 2020 } 2021 2022 #define nitems(_a) (sizeof((_a)) / sizeof((_a)[0])) 2023 2024 static void 2025 iwn_read_eeprom_enhinfo(struct iwn_softc *sc) 2026 { 2027 struct iwn_eeprom_enhinfo enhinfo[35]; 2028 uint16_t val, base; 2029 int8_t maxpwr; 2030 int i; 2031 2032 iwn_read_prom_data(sc, IWN5000_EEPROM_REG, &val, 2); 2033 base = le16toh(val); 2034 iwn_read_prom_data(sc, base + IWN6000_EEPROM_ENHINFO, 2035 enhinfo, sizeof enhinfo); 2036 2037 memset(sc->enh_maxpwr, 0, sizeof sc->enh_maxpwr); 2038 for (i = 0; i < nitems(enhinfo); i++) { 2039 if (enhinfo[i].chan == 0 || enhinfo[i].reserved != 0) 2040 continue; /* Skip invalid entries. */ 2041 2042 maxpwr = 0; 2043 if (sc->txchainmask & IWN_ANT_A) 2044 maxpwr = MAX(maxpwr, enhinfo[i].chain[0]); 2045 if (sc->txchainmask & IWN_ANT_B) 2046 maxpwr = MAX(maxpwr, enhinfo[i].chain[1]); 2047 if (sc->txchainmask & IWN_ANT_C) 2048 maxpwr = MAX(maxpwr, enhinfo[i].chain[2]); 2049 if (sc->ntxchains == 2) 2050 maxpwr = MAX(maxpwr, enhinfo[i].mimo2); 2051 else if (sc->ntxchains == 3) 2052 maxpwr = MAX(maxpwr, enhinfo[i].mimo3); 2053 maxpwr /= 2; /* Convert half-dBm to dBm. */ 2054 2055 DPRINTF(sc, IWN_DEBUG_RESET, "enhinfo %d, maxpwr=%d\n", i, 2056 maxpwr); 2057 sc->enh_maxpwr[i] = maxpwr; 2058 } 2059 } 2060 2061 static struct ieee80211_node * 2062 iwn_node_alloc(struct ieee80211vap *vap, const uint8_t mac[IEEE80211_ADDR_LEN]) 2063 { 2064 return malloc(sizeof (struct iwn_node), M_80211_NODE,M_NOWAIT | M_ZERO); 2065 } 2066 2067 static void 2068 iwn_newassoc(struct ieee80211_node *ni, int isnew) 2069 { 2070 struct iwn_node *wn = (void *)ni; 2071 int ridx, i; 2072 2073 for (i = 0; i < ni->ni_rates.rs_nrates; i++) { 2074 ridx = iwn_plcp_signal(ni->ni_rates.rs_rates[i]); 2075 wn->ridx[i] = ridx; 2076 } 2077 } 2078 2079 static int 2080 iwn_media_change(struct ifnet *ifp) 2081 { 2082 int error; 2083 2084 error = ieee80211_media_change(ifp); 2085 /* NB: only the fixed rate can change and that doesn't need a reset */ 2086 return (error == ENETRESET ? 0 : error); 2087 } 2088 2089 static int 2090 iwn_newstate(struct ieee80211vap *vap, enum ieee80211_state nstate, int arg) 2091 { 2092 struct iwn_vap *ivp = IWN_VAP(vap); 2093 struct ieee80211com *ic = vap->iv_ic; 2094 struct iwn_softc *sc = ic->ic_ifp->if_softc; 2095 int error = 0; 2096 2097 DPRINTF(sc, IWN_DEBUG_STATE, "%s: %s -> %s\n", __func__, 2098 ieee80211_state_name[vap->iv_state], ieee80211_state_name[nstate]); 2099 2100 IEEE80211_UNLOCK(ic); 2101 IWN_LOCK(sc); 2102 callout_stop(&sc->calib_to); 2103 2104 switch (nstate) { 2105 case IEEE80211_S_ASSOC: 2106 if (vap->iv_state != IEEE80211_S_RUN) 2107 break; 2108 /* FALLTHROUGH */ 2109 case IEEE80211_S_AUTH: 2110 if (vap->iv_state == IEEE80211_S_AUTH) 2111 break; 2112 2113 /* 2114 * !AUTH -> AUTH transition requires state reset to handle 2115 * reassociations correctly. 2116 */ 2117 sc->rxon.associd = 0; 2118 sc->rxon.filter &= ~htole32(IWN_FILTER_BSS); 2119 sc->calib.state = IWN_CALIB_STATE_INIT; 2120 2121 if ((error = iwn_auth(sc, vap)) != 0) { 2122 device_printf(sc->sc_dev, 2123 "%s: could not move to auth state\n", __func__); 2124 } 2125 break; 2126 2127 case IEEE80211_S_RUN: 2128 /* 2129 * RUN -> RUN transition; Just restart the timers. 2130 */ 2131 if (vap->iv_state == IEEE80211_S_RUN) { 2132 sc->calib_cnt = 0; 2133 break; 2134 } 2135 2136 /* 2137 * !RUN -> RUN requires setting the association id 2138 * which is done with a firmware cmd. We also defer 2139 * starting the timers until that work is done. 2140 */ 2141 if ((error = iwn_run(sc, vap)) != 0) { 2142 device_printf(sc->sc_dev, 2143 "%s: could not move to run state\n", __func__); 2144 } 2145 break; 2146 2147 case IEEE80211_S_INIT: 2148 sc->calib.state = IWN_CALIB_STATE_INIT; 2149 break; 2150 2151 default: 2152 break; 2153 } 2154 IWN_UNLOCK(sc); 2155 IEEE80211_LOCK(ic); 2156 if (error != 0) 2157 return error; 2158 return ivp->iv_newstate(vap, nstate, arg); 2159 } 2160 2161 static void 2162 iwn_calib_timeout(void *arg) 2163 { 2164 struct iwn_softc *sc = arg; 2165 2166 IWN_LOCK_ASSERT(sc); 2167 2168 /* Force automatic TX power calibration every 60 secs. */ 2169 if (++sc->calib_cnt >= 120) { 2170 uint32_t flags = 0; 2171 2172 DPRINTF(sc, IWN_DEBUG_CALIBRATE, "%s\n", 2173 "sending request for statistics"); 2174 (void)iwn_cmd(sc, IWN_CMD_GET_STATISTICS, &flags, 2175 sizeof flags, 1); 2176 sc->calib_cnt = 0; 2177 } 2178 callout_reset(&sc->calib_to, msecs_to_ticks(500), iwn_calib_timeout, 2179 sc); 2180 } 2181 2182 /* 2183 * Process an RX_PHY firmware notification. This is usually immediately 2184 * followed by an MPDU_RX_DONE notification. 2185 */ 2186 static void 2187 iwn_rx_phy(struct iwn_softc *sc, struct iwn_rx_desc *desc, 2188 struct iwn_rx_data *data) 2189 { 2190 struct iwn_rx_stat *stat = (struct iwn_rx_stat *)(desc + 1); 2191 2192 DPRINTF(sc, IWN_DEBUG_CALIBRATE, "%s: received PHY stats\n", __func__); 2193 bus_dmamap_sync(sc->rxq.data_dmat, data->map, BUS_DMASYNC_POSTREAD); 2194 2195 /* Save RX statistics, they will be used on MPDU_RX_DONE. */ 2196 memcpy(&sc->last_rx_stat, stat, sizeof (*stat)); 2197 sc->last_rx_valid = 1; 2198 } 2199 2200 /* 2201 * Process an RX_DONE (4965AGN only) or MPDU_RX_DONE firmware notification. 2202 * Each MPDU_RX_DONE notification must be preceded by an RX_PHY one. 2203 */ 2204 static void 2205 iwn_rx_done(struct iwn_softc *sc, struct iwn_rx_desc *desc, 2206 struct iwn_rx_data *data) 2207 { 2208 struct iwn_ops *ops = &sc->ops; 2209 struct ifnet *ifp = sc->sc_ifp; 2210 struct ieee80211com *ic = ifp->if_l2com; 2211 struct iwn_rx_ring *ring = &sc->rxq; 2212 struct ieee80211_frame *wh; 2213 struct ieee80211_node *ni; 2214 struct mbuf *m, *m1; 2215 struct iwn_rx_stat *stat; 2216 caddr_t head; 2217 bus_addr_t paddr; 2218 uint32_t flags; 2219 int error, len, rssi, nf; 2220 2221 if (desc->type == IWN_MPDU_RX_DONE) { 2222 /* Check for prior RX_PHY notification. */ 2223 if (!sc->last_rx_valid) { 2224 DPRINTF(sc, IWN_DEBUG_ANY, 2225 "%s: missing RX_PHY\n", __func__); 2226 return; 2227 } 2228 sc->last_rx_valid = 0; 2229 stat = &sc->last_rx_stat; 2230 } else 2231 stat = (struct iwn_rx_stat *)(desc + 1); 2232 2233 bus_dmamap_sync(ring->data_dmat, data->map, BUS_DMASYNC_POSTREAD); 2234 2235 if (stat->cfg_phy_len > IWN_STAT_MAXLEN) { 2236 device_printf(sc->sc_dev, 2237 "%s: invalid RX statistic header, len %d\n", __func__, 2238 stat->cfg_phy_len); 2239 return; 2240 } 2241 if (desc->type == IWN_MPDU_RX_DONE) { 2242 struct iwn_rx_mpdu *mpdu = (struct iwn_rx_mpdu *)(desc + 1); 2243 head = (caddr_t)(mpdu + 1); 2244 len = le16toh(mpdu->len); 2245 } else { 2246 head = (caddr_t)(stat + 1) + stat->cfg_phy_len; 2247 len = le16toh(stat->len); 2248 } 2249 2250 flags = le32toh(*(uint32_t *)(head + len)); 2251 2252 /* Discard frames with a bad FCS early. */ 2253 if ((flags & IWN_RX_NOERROR) != IWN_RX_NOERROR) { 2254 DPRINTF(sc, IWN_DEBUG_RECV, "%s: RX flags error %x\n", 2255 __func__, flags); 2256 ifp->if_ierrors++; 2257 return; 2258 } 2259 /* Discard frames that are too short. */ 2260 if (len < sizeof (*wh)) { 2261 DPRINTF(sc, IWN_DEBUG_RECV, "%s: frame too short: %d\n", 2262 __func__, len); 2263 ifp->if_ierrors++; 2264 return; 2265 } 2266 2267 m1 = m_getjcl(M_DONTWAIT, MT_DATA, M_PKTHDR, IWN_RBUF_SIZE); 2268 if (m1 == NULL) { 2269 DPRINTF(sc, IWN_DEBUG_ANY, "%s: no mbuf to restock ring\n", 2270 __func__); 2271 ifp->if_ierrors++; 2272 return; 2273 } 2274 bus_dmamap_unload(ring->data_dmat, data->map); 2275 2276 error = bus_dmamap_load(ring->data_dmat, data->map, mtod(m1, void *), 2277 IWN_RBUF_SIZE, iwn_dma_map_addr, &paddr, BUS_DMA_NOWAIT); 2278 if (error != 0 && error != EFBIG) { 2279 device_printf(sc->sc_dev, 2280 "%s: bus_dmamap_load failed, error %d\n", __func__, error); 2281 m_freem(m1); 2282 2283 /* Try to reload the old mbuf. */ 2284 error = bus_dmamap_load(ring->data_dmat, data->map, 2285 mtod(data->m, void *), IWN_RBUF_SIZE, iwn_dma_map_addr, 2286 &paddr, BUS_DMA_NOWAIT); 2287 if (error != 0 && error != EFBIG) { 2288 panic("%s: could not load old RX mbuf", __func__); 2289 } 2290 /* Physical address may have changed. */ 2291 ring->desc[ring->cur] = htole32(paddr >> 8); 2292 bus_dmamap_sync(ring->data_dmat, ring->desc_dma.map, 2293 BUS_DMASYNC_PREWRITE); 2294 ifp->if_ierrors++; 2295 return; 2296 } 2297 2298 m = data->m; 2299 data->m = m1; 2300 /* Update RX descriptor. */ 2301 ring->desc[ring->cur] = htole32(paddr >> 8); 2302 bus_dmamap_sync(ring->desc_dma.tag, ring->desc_dma.map, 2303 BUS_DMASYNC_PREWRITE); 2304 2305 /* Finalize mbuf. */ 2306 m->m_pkthdr.rcvif = ifp; 2307 m->m_data = head; 2308 m->m_pkthdr.len = m->m_len = len; 2309 2310 /* Grab a reference to the source node. */ 2311 wh = mtod(m, struct ieee80211_frame *); 2312 ni = ieee80211_find_rxnode(ic, (struct ieee80211_frame_min *)wh); 2313 nf = (ni != NULL && ni->ni_vap->iv_state == IEEE80211_S_RUN && 2314 (ic->ic_flags & IEEE80211_F_SCAN) == 0) ? sc->noise : -95; 2315 2316 rssi = ops->get_rssi(sc, stat); 2317 2318 if (ieee80211_radiotap_active(ic)) { 2319 struct iwn_rx_radiotap_header *tap = &sc->sc_rxtap; 2320 2321 tap->wr_flags = 0; 2322 if (stat->flags & htole16(IWN_STAT_FLAG_SHPREAMBLE)) 2323 tap->wr_flags |= IEEE80211_RADIOTAP_F_SHORTPRE; 2324 tap->wr_dbm_antsignal = (int8_t)rssi; 2325 tap->wr_dbm_antnoise = (int8_t)nf; 2326 tap->wr_tsft = stat->tstamp; 2327 switch (stat->rate) { 2328 /* CCK rates. */ 2329 case 10: tap->wr_rate = 2; break; 2330 case 20: tap->wr_rate = 4; break; 2331 case 55: tap->wr_rate = 11; break; 2332 case 110: tap->wr_rate = 22; break; 2333 /* OFDM rates. */ 2334 case 0xd: tap->wr_rate = 12; break; 2335 case 0xf: tap->wr_rate = 18; break; 2336 case 0x5: tap->wr_rate = 24; break; 2337 case 0x7: tap->wr_rate = 36; break; 2338 case 0x9: tap->wr_rate = 48; break; 2339 case 0xb: tap->wr_rate = 72; break; 2340 case 0x1: tap->wr_rate = 96; break; 2341 case 0x3: tap->wr_rate = 108; break; 2342 /* Unknown rate: should not happen. */ 2343 default: tap->wr_rate = 0; 2344 } 2345 } 2346 2347 IWN_UNLOCK(sc); 2348 2349 /* Send the frame to the 802.11 layer. */ 2350 if (ni != NULL) { 2351 (void)ieee80211_input(ni, m, rssi - nf, nf); 2352 /* Node is no longer needed. */ 2353 ieee80211_free_node(ni); 2354 } else 2355 (void)ieee80211_input_all(ic, m, rssi - nf, nf); 2356 2357 IWN_LOCK(sc); 2358 } 2359 2360 #if 0 /* HT */ 2361 /* Process an incoming Compressed BlockAck. */ 2362 static void 2363 iwn_rx_compressed_ba(struct iwn_softc *sc, struct iwn_rx_desc *desc, 2364 struct iwn_rx_data *data) 2365 { 2366 struct iwn_compressed_ba *ba = (struct iwn_compressed_ba *)(desc + 1); 2367 struct iwn_tx_ring *txq; 2368 2369 bus_dmamap_sync(sc->rxq.data_dmat, data->map, BUS_DMASYNC_POSTREAD); 2370 2371 txq = &sc->txq[letoh16(ba->qid)]; 2372 /* XXX TBD */ 2373 } 2374 #endif 2375 2376 /* 2377 * Process a CALIBRATION_RESULT notification sent by the initialization 2378 * firmware on response to a CMD_CALIB_CONFIG command (5000 only). 2379 */ 2380 static void 2381 iwn5000_rx_calib_results(struct iwn_softc *sc, struct iwn_rx_desc *desc, 2382 struct iwn_rx_data *data) 2383 { 2384 struct iwn_phy_calib *calib = (struct iwn_phy_calib *)(desc + 1); 2385 int len, idx = -1; 2386 2387 /* Runtime firmware should not send such a notification. */ 2388 if (sc->sc_flags & IWN_FLAG_CALIB_DONE) 2389 return; 2390 2391 len = (le32toh(desc->len) & 0x3fff) - 4; 2392 bus_dmamap_sync(sc->rxq.data_dmat, data->map, BUS_DMASYNC_POSTREAD); 2393 2394 switch (calib->code) { 2395 case IWN5000_PHY_CALIB_DC: 2396 if ((sc->sc_flags & IWN_FLAG_INTERNAL_PA) == 0 && 2397 (sc->hw_type == IWN_HW_REV_TYPE_5150 || 2398 sc->hw_type >= IWN_HW_REV_TYPE_6000)) 2399 idx = 0; 2400 break; 2401 case IWN5000_PHY_CALIB_LO: 2402 idx = 1; 2403 break; 2404 case IWN5000_PHY_CALIB_TX_IQ: 2405 idx = 2; 2406 break; 2407 case IWN5000_PHY_CALIB_TX_IQ_PERIODIC: 2408 if (sc->hw_type < IWN_HW_REV_TYPE_6000 && 2409 sc->hw_type != IWN_HW_REV_TYPE_5150) 2410 idx = 3; 2411 break; 2412 case IWN5000_PHY_CALIB_BASE_BAND: 2413 idx = 4; 2414 break; 2415 } 2416 if (idx == -1) /* Ignore other results. */ 2417 return; 2418 2419 /* Save calibration result. */ 2420 if (sc->calibcmd[idx].buf != NULL) 2421 free(sc->calibcmd[idx].buf, M_DEVBUF); 2422 sc->calibcmd[idx].buf = malloc(len, M_DEVBUF, M_NOWAIT); 2423 if (sc->calibcmd[idx].buf == NULL) { 2424 DPRINTF(sc, IWN_DEBUG_CALIBRATE, 2425 "not enough memory for calibration result %d\n", 2426 calib->code); 2427 return; 2428 } 2429 DPRINTF(sc, IWN_DEBUG_CALIBRATE, 2430 "saving calibration result code=%d len=%d\n", calib->code, len); 2431 sc->calibcmd[idx].len = len; 2432 memcpy(sc->calibcmd[idx].buf, calib, len); 2433 } 2434 2435 /* 2436 * Process an RX_STATISTICS or BEACON_STATISTICS firmware notification. 2437 * The latter is sent by the firmware after each received beacon. 2438 */ 2439 static void 2440 iwn_rx_statistics(struct iwn_softc *sc, struct iwn_rx_desc *desc, 2441 struct iwn_rx_data *data) 2442 { 2443 struct iwn_ops *ops = &sc->ops; 2444 struct ifnet *ifp = sc->sc_ifp; 2445 struct ieee80211com *ic = ifp->if_l2com; 2446 struct ieee80211vap *vap = TAILQ_FIRST(&ic->ic_vaps); 2447 struct iwn_calib_state *calib = &sc->calib; 2448 struct iwn_stats *stats = (struct iwn_stats *)(desc + 1); 2449 int temp; 2450 2451 /* Ignore statistics received during a scan. */ 2452 if (vap->iv_state != IEEE80211_S_RUN || 2453 (ic->ic_flags & IEEE80211_F_SCAN)) 2454 return; 2455 2456 bus_dmamap_sync(sc->rxq.data_dmat, data->map, BUS_DMASYNC_POSTREAD); 2457 2458 DPRINTF(sc, IWN_DEBUG_CALIBRATE, "%s: received statistics, cmd %d\n", 2459 __func__, desc->type); 2460 sc->calib_cnt = 0; /* Reset TX power calibration timeout. */ 2461 2462 /* Test if temperature has changed. */ 2463 if (stats->general.temp != sc->rawtemp) { 2464 /* Convert "raw" temperature to degC. */ 2465 sc->rawtemp = stats->general.temp; 2466 temp = ops->get_temperature(sc); 2467 DPRINTF(sc, IWN_DEBUG_CALIBRATE, "%s: temperature %d\n", 2468 __func__, temp); 2469 2470 /* Update TX power if need be (4965AGN only). */ 2471 if (sc->hw_type == IWN_HW_REV_TYPE_4965) 2472 iwn4965_power_calibration(sc, temp); 2473 } 2474 2475 if (desc->type != IWN_BEACON_STATISTICS) 2476 return; /* Reply to a statistics request. */ 2477 2478 sc->noise = iwn_get_noise(&stats->rx.general); 2479 DPRINTF(sc, IWN_DEBUG_CALIBRATE, "%s: noise %d\n", __func__, sc->noise); 2480 2481 /* Test that RSSI and noise are present in stats report. */ 2482 if (le32toh(stats->rx.general.flags) != 1) { 2483 DPRINTF(sc, IWN_DEBUG_ANY, "%s\n", 2484 "received statistics without RSSI"); 2485 return; 2486 } 2487 2488 if (calib->state == IWN_CALIB_STATE_ASSOC) 2489 iwn_collect_noise(sc, &stats->rx.general); 2490 else if (calib->state == IWN_CALIB_STATE_RUN) 2491 iwn_tune_sensitivity(sc, &stats->rx); 2492 } 2493 2494 /* 2495 * Process a TX_DONE firmware notification. Unfortunately, the 4965AGN 2496 * and 5000 adapters have different incompatible TX status formats. 2497 */ 2498 static void 2499 iwn4965_tx_done(struct iwn_softc *sc, struct iwn_rx_desc *desc, 2500 struct iwn_rx_data *data) 2501 { 2502 struct iwn4965_tx_stat *stat = (struct iwn4965_tx_stat *)(desc + 1); 2503 struct iwn_tx_ring *ring = &sc->txq[desc->qid & 0xf]; 2504 2505 DPRINTF(sc, IWN_DEBUG_XMIT, "%s: " 2506 "qid %d idx %d retries %d nkill %d rate %x duration %d status %x\n", 2507 __func__, desc->qid, desc->idx, stat->ackfailcnt, 2508 stat->btkillcnt, stat->rate, le16toh(stat->duration), 2509 le32toh(stat->status)); 2510 2511 bus_dmamap_sync(ring->data_dmat, data->map, BUS_DMASYNC_POSTREAD); 2512 iwn_tx_done(sc, desc, stat->ackfailcnt, le32toh(stat->status) & 0xff); 2513 } 2514 2515 static void 2516 iwn5000_tx_done(struct iwn_softc *sc, struct iwn_rx_desc *desc, 2517 struct iwn_rx_data *data) 2518 { 2519 struct iwn5000_tx_stat *stat = (struct iwn5000_tx_stat *)(desc + 1); 2520 struct iwn_tx_ring *ring = &sc->txq[desc->qid & 0xf]; 2521 2522 DPRINTF(sc, IWN_DEBUG_XMIT, "%s: " 2523 "qid %d idx %d retries %d nkill %d rate %x duration %d status %x\n", 2524 __func__, desc->qid, desc->idx, stat->ackfailcnt, 2525 stat->btkillcnt, stat->rate, le16toh(stat->duration), 2526 le32toh(stat->status)); 2527 2528 #ifdef notyet 2529 /* Reset TX scheduler slot. */ 2530 iwn5000_reset_sched(sc, desc->qid & 0xf, desc->idx); 2531 #endif 2532 2533 bus_dmamap_sync(ring->data_dmat, data->map, BUS_DMASYNC_POSTREAD); 2534 iwn_tx_done(sc, desc, stat->ackfailcnt, le16toh(stat->status) & 0xff); 2535 } 2536 2537 /* 2538 * Adapter-independent backend for TX_DONE firmware notifications. 2539 */ 2540 static void 2541 iwn_tx_done(struct iwn_softc *sc, struct iwn_rx_desc *desc, int ackfailcnt, 2542 uint8_t status) 2543 { 2544 struct ifnet *ifp = sc->sc_ifp; 2545 struct iwn_tx_ring *ring = &sc->txq[desc->qid & 0xf]; 2546 struct iwn_tx_data *data = &ring->data[desc->idx]; 2547 struct mbuf *m; 2548 struct ieee80211_node *ni; 2549 struct ieee80211vap *vap; 2550 2551 KASSERT(data->ni != NULL, ("no node")); 2552 2553 /* Unmap and free mbuf. */ 2554 bus_dmamap_sync(ring->data_dmat, data->map, BUS_DMASYNC_POSTWRITE); 2555 bus_dmamap_unload(ring->data_dmat, data->map); 2556 m = data->m, data->m = NULL; 2557 ni = data->ni, data->ni = NULL; 2558 vap = ni->ni_vap; 2559 2560 if (m->m_flags & M_TXCB) { 2561 /* 2562 * Channels marked for "radar" require traffic to be received 2563 * to unlock before we can transmit. Until traffic is seen 2564 * any attempt to transmit is returned immediately with status 2565 * set to IWN_TX_FAIL_TX_LOCKED. Unfortunately this can easily 2566 * happen on first authenticate after scanning. To workaround 2567 * this we ignore a failure of this sort in AUTH state so the 2568 * 802.11 layer will fall back to using a timeout to wait for 2569 * the AUTH reply. This allows the firmware time to see 2570 * traffic so a subsequent retry of AUTH succeeds. It's 2571 * unclear why the firmware does not maintain state for 2572 * channels recently visited as this would allow immediate 2573 * use of the channel after a scan (where we see traffic). 2574 */ 2575 if (status == IWN_TX_FAIL_TX_LOCKED && 2576 ni->ni_vap->iv_state == IEEE80211_S_AUTH) 2577 ieee80211_process_callback(ni, m, 0); 2578 else 2579 ieee80211_process_callback(ni, m, 2580 (status & IWN_TX_FAIL) != 0); 2581 } 2582 2583 /* 2584 * Update rate control statistics for the node. 2585 */ 2586 if (status & IWN_TX_FAIL) { 2587 ifp->if_oerrors++; 2588 ieee80211_ratectl_tx_complete(vap, ni, 2589 IEEE80211_RATECTL_TX_FAILURE, &ackfailcnt, NULL); 2590 } else { 2591 ifp->if_opackets++; 2592 ieee80211_ratectl_tx_complete(vap, ni, 2593 IEEE80211_RATECTL_TX_SUCCESS, &ackfailcnt, NULL); 2594 } 2595 m_freem(m); 2596 ieee80211_free_node(ni); 2597 2598 sc->sc_tx_timer = 0; 2599 if (--ring->queued < IWN_TX_RING_LOMARK) { 2600 sc->qfullmsk &= ~(1 << ring->qid); 2601 if (sc->qfullmsk == 0 && 2602 (ifp->if_drv_flags & IFF_DRV_OACTIVE)) { 2603 ifp->if_drv_flags &= ~IFF_DRV_OACTIVE; 2604 iwn_start_locked(ifp); 2605 } 2606 } 2607 } 2608 2609 /* 2610 * Process a "command done" firmware notification. This is where we wakeup 2611 * processes waiting for a synchronous command completion. 2612 */ 2613 static void 2614 iwn_cmd_done(struct iwn_softc *sc, struct iwn_rx_desc *desc) 2615 { 2616 struct iwn_tx_ring *ring = &sc->txq[4]; 2617 struct iwn_tx_data *data; 2618 2619 if ((desc->qid & 0xf) != 4) 2620 return; /* Not a command ack. */ 2621 2622 data = &ring->data[desc->idx]; 2623 2624 /* If the command was mapped in an mbuf, free it. */ 2625 if (data->m != NULL) { 2626 bus_dmamap_sync(ring->data_dmat, data->map, 2627 BUS_DMASYNC_POSTWRITE); 2628 bus_dmamap_unload(ring->data_dmat, data->map); 2629 m_freem(data->m); 2630 data->m = NULL; 2631 } 2632 wakeup(&ring->desc[desc->idx]); 2633 } 2634 2635 /* 2636 * Process an INT_FH_RX or INT_SW_RX interrupt. 2637 */ 2638 static void 2639 iwn_notif_intr(struct iwn_softc *sc) 2640 { 2641 struct iwn_ops *ops = &sc->ops; 2642 struct ifnet *ifp = sc->sc_ifp; 2643 struct ieee80211com *ic = ifp->if_l2com; 2644 struct ieee80211vap *vap = TAILQ_FIRST(&ic->ic_vaps); 2645 uint16_t hw; 2646 2647 bus_dmamap_sync(sc->rxq.stat_dma.tag, sc->rxq.stat_dma.map, 2648 BUS_DMASYNC_POSTREAD); 2649 2650 hw = le16toh(sc->rxq.stat->closed_count) & 0xfff; 2651 while (sc->rxq.cur != hw) { 2652 struct iwn_rx_data *data = &sc->rxq.data[sc->rxq.cur]; 2653 struct iwn_rx_desc *desc; 2654 2655 bus_dmamap_sync(sc->rxq.data_dmat, data->map, 2656 BUS_DMASYNC_POSTREAD); 2657 desc = mtod(data->m, struct iwn_rx_desc *); 2658 2659 DPRINTF(sc, IWN_DEBUG_RECV, 2660 "%s: qid %x idx %d flags %x type %d(%s) len %d\n", 2661 __func__, desc->qid & 0xf, desc->idx, desc->flags, 2662 desc->type, iwn_intr_str(desc->type), 2663 le16toh(desc->len)); 2664 2665 if (!(desc->qid & 0x80)) /* Reply to a command. */ 2666 iwn_cmd_done(sc, desc); 2667 2668 switch (desc->type) { 2669 case IWN_RX_PHY: 2670 iwn_rx_phy(sc, desc, data); 2671 break; 2672 2673 case IWN_RX_DONE: /* 4965AGN only. */ 2674 case IWN_MPDU_RX_DONE: 2675 /* An 802.11 frame has been received. */ 2676 iwn_rx_done(sc, desc, data); 2677 break; 2678 2679 #if 0 /* HT */ 2680 case IWN_RX_COMPRESSED_BA: 2681 /* A Compressed BlockAck has been received. */ 2682 iwn_rx_compressed_ba(sc, desc, data); 2683 break; 2684 #endif 2685 2686 case IWN_TX_DONE: 2687 /* An 802.11 frame has been transmitted. */ 2688 ops->tx_done(sc, desc, data); 2689 break; 2690 2691 case IWN_RX_STATISTICS: 2692 case IWN_BEACON_STATISTICS: 2693 iwn_rx_statistics(sc, desc, data); 2694 break; 2695 2696 case IWN_BEACON_MISSED: 2697 { 2698 struct iwn_beacon_missed *miss = 2699 (struct iwn_beacon_missed *)(desc + 1); 2700 int misses; 2701 2702 bus_dmamap_sync(sc->rxq.data_dmat, data->map, 2703 BUS_DMASYNC_POSTREAD); 2704 misses = le32toh(miss->consecutive); 2705 2706 DPRINTF(sc, IWN_DEBUG_STATE, 2707 "%s: beacons missed %d/%d\n", __func__, 2708 misses, le32toh(miss->total)); 2709 /* 2710 * If more than 5 consecutive beacons are missed, 2711 * reinitialize the sensitivity state machine. 2712 */ 2713 if (vap->iv_state == IEEE80211_S_RUN && 2714 (ic->ic_flags & IEEE80211_F_SCAN) != 0) { 2715 if (misses > 5) 2716 (void)iwn_init_sensitivity(sc); 2717 if (misses >= vap->iv_bmissthreshold) { 2718 IWN_UNLOCK(sc); 2719 ieee80211_beacon_miss(ic); 2720 IWN_LOCK(sc); 2721 } 2722 } 2723 break; 2724 } 2725 case IWN_UC_READY: 2726 { 2727 struct iwn_ucode_info *uc = 2728 (struct iwn_ucode_info *)(desc + 1); 2729 2730 /* The microcontroller is ready. */ 2731 bus_dmamap_sync(sc->rxq.data_dmat, data->map, 2732 BUS_DMASYNC_POSTREAD); 2733 DPRINTF(sc, IWN_DEBUG_RESET, 2734 "microcode alive notification version=%d.%d " 2735 "subtype=%x alive=%x\n", uc->major, uc->minor, 2736 uc->subtype, le32toh(uc->valid)); 2737 2738 if (le32toh(uc->valid) != 1) { 2739 device_printf(sc->sc_dev, 2740 "microcontroller initialization failed"); 2741 break; 2742 } 2743 if (uc->subtype == IWN_UCODE_INIT) { 2744 /* Save microcontroller report. */ 2745 memcpy(&sc->ucode_info, uc, sizeof (*uc)); 2746 } 2747 /* Save the address of the error log in SRAM. */ 2748 sc->errptr = le32toh(uc->errptr); 2749 break; 2750 } 2751 case IWN_STATE_CHANGED: 2752 { 2753 uint32_t *status = (uint32_t *)(desc + 1); 2754 2755 /* 2756 * State change allows hardware switch change to be 2757 * noted. However, we handle this in iwn_intr as we 2758 * get both the enable/disble intr. 2759 */ 2760 bus_dmamap_sync(sc->rxq.data_dmat, data->map, 2761 BUS_DMASYNC_POSTREAD); 2762 DPRINTF(sc, IWN_DEBUG_INTR, "state changed to %x\n", 2763 le32toh(*status)); 2764 break; 2765 } 2766 case IWN_START_SCAN: 2767 { 2768 struct iwn_start_scan *scan = 2769 (struct iwn_start_scan *)(desc + 1); 2770 2771 bus_dmamap_sync(sc->rxq.data_dmat, data->map, 2772 BUS_DMASYNC_POSTREAD); 2773 DPRINTF(sc, IWN_DEBUG_ANY, 2774 "%s: scanning channel %d status %x\n", 2775 __func__, scan->chan, le32toh(scan->status)); 2776 break; 2777 } 2778 case IWN_STOP_SCAN: 2779 { 2780 struct iwn_stop_scan *scan = 2781 (struct iwn_stop_scan *)(desc + 1); 2782 2783 bus_dmamap_sync(sc->rxq.data_dmat, data->map, 2784 BUS_DMASYNC_POSTREAD); 2785 DPRINTF(sc, IWN_DEBUG_STATE, 2786 "scan finished nchan=%d status=%d chan=%d\n", 2787 scan->nchan, scan->status, scan->chan); 2788 2789 IWN_UNLOCK(sc); 2790 ieee80211_scan_next(vap); 2791 IWN_LOCK(sc); 2792 break; 2793 } 2794 case IWN5000_CALIBRATION_RESULT: 2795 iwn5000_rx_calib_results(sc, desc, data); 2796 break; 2797 2798 case IWN5000_CALIBRATION_DONE: 2799 sc->sc_flags |= IWN_FLAG_CALIB_DONE; 2800 wakeup(sc); 2801 break; 2802 } 2803 2804 sc->rxq.cur = (sc->rxq.cur + 1) % IWN_RX_RING_COUNT; 2805 } 2806 2807 /* Tell the firmware what we have processed. */ 2808 hw = (hw == 0) ? IWN_RX_RING_COUNT - 1 : hw - 1; 2809 IWN_WRITE(sc, IWN_FH_RX_WPTR, hw & ~7); 2810 } 2811 2812 /* 2813 * Process an INT_WAKEUP interrupt raised when the microcontroller wakes up 2814 * from power-down sleep mode. 2815 */ 2816 static void 2817 iwn_wakeup_intr(struct iwn_softc *sc) 2818 { 2819 int qid; 2820 2821 DPRINTF(sc, IWN_DEBUG_RESET, "%s: ucode wakeup from power-down sleep\n", 2822 __func__); 2823 2824 /* Wakeup RX and TX rings. */ 2825 IWN_WRITE(sc, IWN_FH_RX_WPTR, sc->rxq.cur & ~7); 2826 for (qid = 0; qid < sc->ntxqs; qid++) { 2827 struct iwn_tx_ring *ring = &sc->txq[qid]; 2828 IWN_WRITE(sc, IWN_HBUS_TARG_WRPTR, qid << 8 | ring->cur); 2829 } 2830 } 2831 2832 static void 2833 iwn_rftoggle_intr(struct iwn_softc *sc) 2834 { 2835 struct ifnet *ifp = sc->sc_ifp; 2836 struct ieee80211com *ic = ifp->if_l2com; 2837 uint32_t tmp = IWN_READ(sc, IWN_GP_CNTRL); 2838 2839 IWN_LOCK_ASSERT(sc); 2840 2841 device_printf(sc->sc_dev, "RF switch: radio %s\n", 2842 (tmp & IWN_GP_CNTRL_RFKILL) ? "enabled" : "disabled"); 2843 if (tmp & IWN_GP_CNTRL_RFKILL) 2844 ieee80211_runtask(ic, &sc->sc_radioon_task); 2845 else 2846 ieee80211_runtask(ic, &sc->sc_radiooff_task); 2847 } 2848 2849 /* 2850 * Dump the error log of the firmware when a firmware panic occurs. Although 2851 * we can't debug the firmware because it is neither open source nor free, it 2852 * can help us to identify certain classes of problems. 2853 */ 2854 static void 2855 iwn_fatal_intr(struct iwn_softc *sc) 2856 { 2857 struct iwn_fw_dump dump; 2858 int i; 2859 2860 IWN_LOCK_ASSERT(sc); 2861 2862 /* Force a complete recalibration on next init. */ 2863 sc->sc_flags &= ~IWN_FLAG_CALIB_DONE; 2864 2865 /* Check that the error log address is valid. */ 2866 if (sc->errptr < IWN_FW_DATA_BASE || 2867 sc->errptr + sizeof (dump) > 2868 IWN_FW_DATA_BASE + sc->fw_data_maxsz) { 2869 printf("%s: bad firmware error log address 0x%08x\n", __func__, 2870 sc->errptr); 2871 return; 2872 } 2873 if (iwn_nic_lock(sc) != 0) { 2874 printf("%s: could not read firmware error log\n", __func__); 2875 return; 2876 } 2877 /* Read firmware error log from SRAM. */ 2878 iwn_mem_read_region_4(sc, sc->errptr, (uint32_t *)&dump, 2879 sizeof (dump) / sizeof (uint32_t)); 2880 iwn_nic_unlock(sc); 2881 2882 if (dump.valid == 0) { 2883 printf("%s: firmware error log is empty\n", __func__); 2884 return; 2885 } 2886 printf("firmware error log:\n"); 2887 printf(" error type = \"%s\" (0x%08X)\n", 2888 (dump.id < nitems(iwn_fw_errmsg)) ? 2889 iwn_fw_errmsg[dump.id] : "UNKNOWN", 2890 dump.id); 2891 printf(" program counter = 0x%08X\n", dump.pc); 2892 printf(" source line = 0x%08X\n", dump.src_line); 2893 printf(" error data = 0x%08X%08X\n", 2894 dump.error_data[0], dump.error_data[1]); 2895 printf(" branch link = 0x%08X%08X\n", 2896 dump.branch_link[0], dump.branch_link[1]); 2897 printf(" interrupt link = 0x%08X%08X\n", 2898 dump.interrupt_link[0], dump.interrupt_link[1]); 2899 printf(" time = %u\n", dump.time[0]); 2900 2901 /* Dump driver status (TX and RX rings) while we're here. */ 2902 printf("driver status:\n"); 2903 for (i = 0; i < sc->ntxqs; i++) { 2904 struct iwn_tx_ring *ring = &sc->txq[i]; 2905 printf(" tx ring %2d: qid=%-2d cur=%-3d queued=%-3d\n", 2906 i, ring->qid, ring->cur, ring->queued); 2907 } 2908 printf(" rx ring: cur=%d\n", sc->rxq.cur); 2909 } 2910 2911 static void 2912 iwn_intr(void *arg) 2913 { 2914 struct iwn_softc *sc = arg; 2915 struct ifnet *ifp = sc->sc_ifp; 2916 uint32_t r1, r2, tmp; 2917 2918 IWN_LOCK(sc); 2919 2920 /* Disable interrupts. */ 2921 IWN_WRITE(sc, IWN_INT_MASK, 0); 2922 2923 /* Read interrupts from ICT (fast) or from registers (slow). */ 2924 if (sc->sc_flags & IWN_FLAG_USE_ICT) { 2925 tmp = 0; 2926 while (sc->ict[sc->ict_cur] != 0) { 2927 tmp |= sc->ict[sc->ict_cur]; 2928 sc->ict[sc->ict_cur] = 0; /* Acknowledge. */ 2929 sc->ict_cur = (sc->ict_cur + 1) % IWN_ICT_COUNT; 2930 } 2931 tmp = le32toh(tmp); 2932 if (tmp == 0xffffffff) /* Shouldn't happen. */ 2933 tmp = 0; 2934 else if (tmp & 0xc0000) /* Workaround a HW bug. */ 2935 tmp |= 0x8000; 2936 r1 = (tmp & 0xff00) << 16 | (tmp & 0xff); 2937 r2 = 0; /* Unused. */ 2938 } else { 2939 r1 = IWN_READ(sc, IWN_INT); 2940 if (r1 == 0xffffffff || (r1 & 0xfffffff0) == 0xa5a5a5a0) 2941 return; /* Hardware gone! */ 2942 r2 = IWN_READ(sc, IWN_FH_INT); 2943 } 2944 2945 DPRINTF(sc, IWN_DEBUG_INTR, "interrupt reg1=%x reg2=%x\n", r1, r2); 2946 2947 if (r1 == 0 && r2 == 0) 2948 goto done; /* Interrupt not for us. */ 2949 2950 /* Acknowledge interrupts. */ 2951 IWN_WRITE(sc, IWN_INT, r1); 2952 if (!(sc->sc_flags & IWN_FLAG_USE_ICT)) 2953 IWN_WRITE(sc, IWN_FH_INT, r2); 2954 2955 if (r1 & IWN_INT_RF_TOGGLED) { 2956 iwn_rftoggle_intr(sc); 2957 goto done; 2958 } 2959 if (r1 & IWN_INT_CT_REACHED) { 2960 device_printf(sc->sc_dev, "%s: critical temperature reached!\n", 2961 __func__); 2962 } 2963 if (r1 & (IWN_INT_SW_ERR | IWN_INT_HW_ERR)) { 2964 device_printf(sc->sc_dev, "%s: fatal firmware error\n", 2965 __func__); 2966 /* Dump firmware error log and stop. */ 2967 iwn_fatal_intr(sc); 2968 ifp->if_flags &= ~IFF_UP; 2969 iwn_stop_locked(sc); 2970 goto done; 2971 } 2972 if ((r1 & (IWN_INT_FH_RX | IWN_INT_SW_RX | IWN_INT_RX_PERIODIC)) || 2973 (r2 & IWN_FH_INT_RX)) { 2974 if (sc->sc_flags & IWN_FLAG_USE_ICT) { 2975 if (r1 & (IWN_INT_FH_RX | IWN_INT_SW_RX)) 2976 IWN_WRITE(sc, IWN_FH_INT, IWN_FH_INT_RX); 2977 IWN_WRITE_1(sc, IWN_INT_PERIODIC, 2978 IWN_INT_PERIODIC_DIS); 2979 iwn_notif_intr(sc); 2980 if (r1 & (IWN_INT_FH_RX | IWN_INT_SW_RX)) { 2981 IWN_WRITE_1(sc, IWN_INT_PERIODIC, 2982 IWN_INT_PERIODIC_ENA); 2983 } 2984 } else 2985 iwn_notif_intr(sc); 2986 } 2987 2988 if ((r1 & IWN_INT_FH_TX) || (r2 & IWN_FH_INT_TX)) { 2989 if (sc->sc_flags & IWN_FLAG_USE_ICT) 2990 IWN_WRITE(sc, IWN_FH_INT, IWN_FH_INT_TX); 2991 wakeup(sc); /* FH DMA transfer completed. */ 2992 } 2993 2994 if (r1 & IWN_INT_ALIVE) 2995 wakeup(sc); /* Firmware is alive. */ 2996 2997 if (r1 & IWN_INT_WAKEUP) 2998 iwn_wakeup_intr(sc); 2999 3000 done: 3001 /* Re-enable interrupts. */ 3002 if (ifp->if_flags & IFF_UP) 3003 IWN_WRITE(sc, IWN_INT_MASK, sc->int_mask); 3004 3005 IWN_UNLOCK(sc); 3006 } 3007 3008 /* 3009 * Update TX scheduler ring when transmitting an 802.11 frame (4965AGN and 3010 * 5000 adapters use a slightly different format). 3011 */ 3012 static void 3013 iwn4965_update_sched(struct iwn_softc *sc, int qid, int idx, uint8_t id, 3014 uint16_t len) 3015 { 3016 uint16_t *w = &sc->sched[qid * IWN4965_SCHED_COUNT + idx]; 3017 3018 *w = htole16(len + 8); 3019 bus_dmamap_sync(sc->sched_dma.tag, sc->sched_dma.map, 3020 BUS_DMASYNC_PREWRITE); 3021 if (idx < IWN_SCHED_WINSZ) { 3022 *(w + IWN_TX_RING_COUNT) = *w; 3023 bus_dmamap_sync(sc->sched_dma.tag, sc->sched_dma.map, 3024 BUS_DMASYNC_PREWRITE); 3025 } 3026 } 3027 3028 static void 3029 iwn5000_update_sched(struct iwn_softc *sc, int qid, int idx, uint8_t id, 3030 uint16_t len) 3031 { 3032 uint16_t *w = &sc->sched[qid * IWN5000_SCHED_COUNT + idx]; 3033 3034 *w = htole16(id << 12 | (len + 8)); 3035 bus_dmamap_sync(sc->sched_dma.tag, sc->sched_dma.map, 3036 BUS_DMASYNC_PREWRITE); 3037 if (idx < IWN_SCHED_WINSZ) { 3038 *(w + IWN_TX_RING_COUNT) = *w; 3039 bus_dmamap_sync(sc->sched_dma.tag, sc->sched_dma.map, 3040 BUS_DMASYNC_PREWRITE); 3041 } 3042 } 3043 3044 #ifdef notyet 3045 static void 3046 iwn5000_reset_sched(struct iwn_softc *sc, int qid, int idx) 3047 { 3048 uint16_t *w = &sc->sched[qid * IWN5000_SCHED_COUNT + idx]; 3049 3050 *w = (*w & htole16(0xf000)) | htole16(1); 3051 bus_dmamap_sync(sc->sched_dma.tag, sc->sched_dma.map, 3052 BUS_DMASYNC_PREWRITE); 3053 if (idx < IWN_SCHED_WINSZ) { 3054 *(w + IWN_TX_RING_COUNT) = *w; 3055 bus_dmamap_sync(sc->sched_dma.tag, sc->sched_dma.map, 3056 BUS_DMASYNC_PREWRITE); 3057 } 3058 } 3059 #endif 3060 3061 static uint8_t 3062 iwn_plcp_signal(int rate) { 3063 int i; 3064 3065 for (i = 0; i < IWN_RIDX_MAX + 1; i++) { 3066 if ((rate & IEEE80211_RATE_VAL) == iwn_rates[i].rate) 3067 return i; 3068 } 3069 3070 return 0; 3071 } 3072 3073 static int 3074 iwn_tx_data(struct iwn_softc *sc, struct mbuf *m, struct ieee80211_node *ni) 3075 { 3076 const struct ieee80211_txparam *tp; 3077 struct ieee80211vap *vap = ni->ni_vap; 3078 struct ieee80211com *ic = ni->ni_ic; 3079 struct iwn_node *wn = (void *)ni; 3080 struct iwn_tx_ring *ring; 3081 struct iwn_tx_desc *desc; 3082 struct iwn_tx_data *data; 3083 struct iwn_tx_cmd *cmd; 3084 struct iwn_cmd_data *tx; 3085 const struct iwn_rate *rinfo; 3086 struct ieee80211_frame *wh; 3087 struct ieee80211_key *k = NULL; 3088 struct mbuf *m1; 3089 uint32_t flags; 3090 uint16_t qos; 3091 u_int hdrlen; 3092 bus_dma_segment_t *seg, segs[IWN_MAX_SCATTER]; 3093 uint8_t tid, ridx, txant, type; 3094 int ac, i, totlen, error, pad, nsegs = 0, rate; 3095 3096 IWN_LOCK_ASSERT(sc); 3097 3098 wh = mtod(m, struct ieee80211_frame *); 3099 hdrlen = ieee80211_anyhdrsize(wh); 3100 type = wh->i_fc[0] & IEEE80211_FC0_TYPE_MASK; 3101 3102 /* Select EDCA Access Category and TX ring for this frame. */ 3103 if (IEEE80211_QOS_HAS_SEQ(wh)) { 3104 qos = ((const struct ieee80211_qosframe *)wh)->i_qos[0]; 3105 tid = qos & IEEE80211_QOS_TID; 3106 } else { 3107 qos = 0; 3108 tid = 0; 3109 } 3110 ac = M_WME_GETAC(m); 3111 3112 ring = &sc->txq[ac]; 3113 desc = &ring->desc[ring->cur]; 3114 data = &ring->data[ring->cur]; 3115 3116 /* Choose a TX rate index. */ 3117 tp = &vap->iv_txparms[ieee80211_chan2mode(ni->ni_chan)]; 3118 if (type == IEEE80211_FC0_TYPE_MGT) 3119 rate = tp->mgmtrate; 3120 else if (IEEE80211_IS_MULTICAST(wh->i_addr1)) 3121 rate = tp->mcastrate; 3122 else if (tp->ucastrate != IEEE80211_FIXED_RATE_NONE) 3123 rate = tp->ucastrate; 3124 else { 3125 /* XXX pass pktlen */ 3126 (void) ieee80211_ratectl_rate(ni, NULL, 0); 3127 rate = ni->ni_txrate; 3128 } 3129 ridx = iwn_plcp_signal(rate); 3130 rinfo = &iwn_rates[ridx]; 3131 3132 /* Encrypt the frame if need be. */ 3133 if (wh->i_fc[1] & IEEE80211_FC1_WEP) { 3134 /* Retrieve key for TX. */ 3135 k = ieee80211_crypto_encap(ni, m); 3136 if (k == NULL) { 3137 m_freem(m); 3138 return ENOBUFS; 3139 } 3140 /* 802.11 header may have moved. */ 3141 wh = mtod(m, struct ieee80211_frame *); 3142 } 3143 totlen = m->m_pkthdr.len; 3144 3145 if (ieee80211_radiotap_active_vap(vap)) { 3146 struct iwn_tx_radiotap_header *tap = &sc->sc_txtap; 3147 3148 tap->wt_flags = 0; 3149 tap->wt_rate = rinfo->rate; 3150 if (k != NULL) 3151 tap->wt_flags |= IEEE80211_RADIOTAP_F_WEP; 3152 3153 ieee80211_radiotap_tx(vap, m); 3154 } 3155 3156 /* Prepare TX firmware command. */ 3157 cmd = &ring->cmd[ring->cur]; 3158 cmd->code = IWN_CMD_TX_DATA; 3159 cmd->flags = 0; 3160 cmd->qid = ring->qid; 3161 cmd->idx = ring->cur; 3162 3163 tx = (struct iwn_cmd_data *)cmd->data; 3164 /* NB: No need to clear tx, all fields are reinitialized here. */ 3165 tx->scratch = 0; /* clear "scratch" area */ 3166 3167 flags = 0; 3168 if (!IEEE80211_IS_MULTICAST(wh->i_addr1)) { 3169 /* Unicast frame, check if an ACK is expected. */ 3170 if (!qos || (qos & IEEE80211_QOS_ACKPOLICY) != 3171 IEEE80211_QOS_ACKPOLICY_NOACK) 3172 flags |= IWN_TX_NEED_ACK; 3173 } 3174 if ((wh->i_fc[0] & 3175 (IEEE80211_FC0_TYPE_MASK | IEEE80211_FC0_SUBTYPE_MASK)) == 3176 (IEEE80211_FC0_TYPE_CTL | IEEE80211_FC0_SUBTYPE_BAR)) 3177 flags |= IWN_TX_IMM_BA; /* Cannot happen yet. */ 3178 3179 if (wh->i_fc[1] & IEEE80211_FC1_MORE_FRAG) 3180 flags |= IWN_TX_MORE_FRAG; /* Cannot happen yet. */ 3181 3182 /* Check if frame must be protected using RTS/CTS or CTS-to-self. */ 3183 if (!IEEE80211_IS_MULTICAST(wh->i_addr1)) { 3184 /* NB: Group frames are sent using CCK in 802.11b/g. */ 3185 if (totlen + IEEE80211_CRC_LEN > vap->iv_rtsthreshold) { 3186 flags |= IWN_TX_NEED_RTS; 3187 } else if ((ic->ic_flags & IEEE80211_F_USEPROT) && 3188 ridx >= IWN_RIDX_OFDM6) { 3189 if (ic->ic_protmode == IEEE80211_PROT_CTSONLY) 3190 flags |= IWN_TX_NEED_CTS; 3191 else if (ic->ic_protmode == IEEE80211_PROT_RTSCTS) 3192 flags |= IWN_TX_NEED_RTS; 3193 } 3194 if (flags & (IWN_TX_NEED_RTS | IWN_TX_NEED_CTS)) { 3195 if (sc->hw_type != IWN_HW_REV_TYPE_4965) { 3196 /* 5000 autoselects RTS/CTS or CTS-to-self. */ 3197 flags &= ~(IWN_TX_NEED_RTS | IWN_TX_NEED_CTS); 3198 flags |= IWN_TX_NEED_PROTECTION; 3199 } else 3200 flags |= IWN_TX_FULL_TXOP; 3201 } 3202 } 3203 3204 if (IEEE80211_IS_MULTICAST(wh->i_addr1) || 3205 type != IEEE80211_FC0_TYPE_DATA) 3206 tx->id = sc->broadcast_id; 3207 else 3208 tx->id = wn->id; 3209 3210 if (type == IEEE80211_FC0_TYPE_MGT) { 3211 uint8_t subtype = wh->i_fc[0] & IEEE80211_FC0_SUBTYPE_MASK; 3212 3213 /* Tell HW to set timestamp in probe responses. */ 3214 if (subtype == IEEE80211_FC0_SUBTYPE_PROBE_RESP) 3215 flags |= IWN_TX_INSERT_TSTAMP; 3216 if (subtype == IEEE80211_FC0_SUBTYPE_ASSOC_REQ || 3217 subtype == IEEE80211_FC0_SUBTYPE_REASSOC_REQ) 3218 tx->timeout = htole16(3); 3219 else 3220 tx->timeout = htole16(2); 3221 } else 3222 tx->timeout = htole16(0); 3223 3224 if (hdrlen & 3) { 3225 /* First segment length must be a multiple of 4. */ 3226 flags |= IWN_TX_NEED_PADDING; 3227 pad = 4 - (hdrlen & 3); 3228 } else 3229 pad = 0; 3230 3231 tx->len = htole16(totlen); 3232 tx->tid = tid; 3233 tx->rts_ntries = 60; 3234 tx->data_ntries = 15; 3235 tx->lifetime = htole32(IWN_LIFETIME_INFINITE); 3236 tx->plcp = rinfo->plcp; 3237 tx->rflags = rinfo->flags; 3238 if (tx->id == sc->broadcast_id) { 3239 /* Group or management frame. */ 3240 tx->linkq = 0; 3241 /* XXX Alternate between antenna A and B? */ 3242 txant = IWN_LSB(sc->txchainmask); 3243 tx->rflags |= IWN_RFLAG_ANT(txant); 3244 } else { 3245 tx->linkq = ni->ni_rates.rs_nrates - ridx - 1; 3246 flags |= IWN_TX_LINKQ; /* enable MRR */ 3247 } 3248 /* Set physical address of "scratch area". */ 3249 tx->loaddr = htole32(IWN_LOADDR(data->scratch_paddr)); 3250 tx->hiaddr = IWN_HIADDR(data->scratch_paddr); 3251 3252 /* Copy 802.11 header in TX command. */ 3253 memcpy((uint8_t *)(tx + 1), wh, hdrlen); 3254 3255 /* Trim 802.11 header. */ 3256 m_adj(m, hdrlen); 3257 tx->security = 0; 3258 tx->flags = htole32(flags); 3259 3260 error = bus_dmamap_load_mbuf_sg(ring->data_dmat, data->map, m, segs, 3261 &nsegs, BUS_DMA_NOWAIT); 3262 if (error != 0) { 3263 if (error != EFBIG) { 3264 device_printf(sc->sc_dev, 3265 "%s: can't map mbuf (error %d)\n", __func__, error); 3266 m_freem(m); 3267 return error; 3268 } 3269 /* Too many DMA segments, linearize mbuf. */ 3270 m1 = m_collapse(m, M_DONTWAIT, IWN_MAX_SCATTER); 3271 if (m1 == NULL) { 3272 device_printf(sc->sc_dev, 3273 "%s: could not defrag mbuf\n", __func__); 3274 m_freem(m); 3275 return ENOBUFS; 3276 } 3277 m = m1; 3278 3279 error = bus_dmamap_load_mbuf_sg(ring->data_dmat, data->map, m, 3280 segs, &nsegs, BUS_DMA_NOWAIT); 3281 if (error != 0) { 3282 device_printf(sc->sc_dev, 3283 "%s: can't map mbuf (error %d)\n", __func__, error); 3284 m_freem(m); 3285 return error; 3286 } 3287 } 3288 3289 data->m = m; 3290 data->ni = ni; 3291 3292 DPRINTF(sc, IWN_DEBUG_XMIT, "%s: qid %d idx %d len %d nsegs %d\n", 3293 __func__, ring->qid, ring->cur, m->m_pkthdr.len, nsegs); 3294 3295 /* Fill TX descriptor. */ 3296 desc->nsegs = 1; 3297 if (m->m_len != 0) 3298 desc->nsegs += nsegs; 3299 /* First DMA segment is used by the TX command. */ 3300 desc->segs[0].addr = htole32(IWN_LOADDR(data->cmd_paddr)); 3301 desc->segs[0].len = htole16(IWN_HIADDR(data->cmd_paddr) | 3302 (4 + sizeof (*tx) + hdrlen + pad) << 4); 3303 /* Other DMA segments are for data payload. */ 3304 seg = &segs[0]; 3305 for (i = 1; i <= nsegs; i++) { 3306 desc->segs[i].addr = htole32(IWN_LOADDR(seg->ds_addr)); 3307 desc->segs[i].len = htole16(IWN_HIADDR(seg->ds_addr) | 3308 seg->ds_len << 4); 3309 seg++; 3310 } 3311 3312 bus_dmamap_sync(ring->data_dmat, data->map, BUS_DMASYNC_PREWRITE); 3313 bus_dmamap_sync(ring->data_dmat, ring->cmd_dma.map, 3314 BUS_DMASYNC_PREWRITE); 3315 bus_dmamap_sync(ring->desc_dma.tag, ring->desc_dma.map, 3316 BUS_DMASYNC_PREWRITE); 3317 3318 #ifdef notyet 3319 /* Update TX scheduler. */ 3320 ops->update_sched(sc, ring->qid, ring->cur, tx->id, totlen); 3321 #endif 3322 3323 /* Kick TX ring. */ 3324 ring->cur = (ring->cur + 1) % IWN_TX_RING_COUNT; 3325 IWN_WRITE(sc, IWN_HBUS_TARG_WRPTR, ring->qid << 8 | ring->cur); 3326 3327 /* Mark TX ring as full if we reach a certain threshold. */ 3328 if (++ring->queued > IWN_TX_RING_HIMARK) 3329 sc->qfullmsk |= 1 << ring->qid; 3330 3331 return 0; 3332 } 3333 3334 static int 3335 iwn_tx_data_raw(struct iwn_softc *sc, struct mbuf *m, 3336 struct ieee80211_node *ni, const struct ieee80211_bpf_params *params) 3337 { 3338 const struct iwn_rate *rinfo; 3339 struct ifnet *ifp = sc->sc_ifp; 3340 struct ieee80211vap *vap = ni->ni_vap; 3341 struct ieee80211com *ic = ifp->if_l2com; 3342 struct iwn_tx_cmd *cmd; 3343 struct iwn_cmd_data *tx; 3344 struct ieee80211_frame *wh; 3345 struct iwn_tx_ring *ring; 3346 struct iwn_tx_desc *desc; 3347 struct iwn_tx_data *data; 3348 struct mbuf *m1; 3349 bus_dma_segment_t *seg, segs[IWN_MAX_SCATTER]; 3350 uint32_t flags; 3351 u_int hdrlen; 3352 int ac, totlen, error, pad, nsegs = 0, i, rate; 3353 uint8_t ridx, type, txant; 3354 3355 IWN_LOCK_ASSERT(sc); 3356 3357 wh = mtod(m, struct ieee80211_frame *); 3358 hdrlen = ieee80211_anyhdrsize(wh); 3359 type = wh->i_fc[0] & IEEE80211_FC0_TYPE_MASK; 3360 3361 ac = params->ibp_pri & 3; 3362 3363 ring = &sc->txq[ac]; 3364 desc = &ring->desc[ring->cur]; 3365 data = &ring->data[ring->cur]; 3366 3367 /* Choose a TX rate index. */ 3368 rate = params->ibp_rate0; 3369 if (!ieee80211_isratevalid(ic->ic_rt, rate)) { 3370 /* XXX fall back to mcast/mgmt rate? */ 3371 m_freem(m); 3372 return EINVAL; 3373 } 3374 ridx = iwn_plcp_signal(rate); 3375 rinfo = &iwn_rates[ridx]; 3376 3377 totlen = m->m_pkthdr.len; 3378 3379 /* Prepare TX firmware command. */ 3380 cmd = &ring->cmd[ring->cur]; 3381 cmd->code = IWN_CMD_TX_DATA; 3382 cmd->flags = 0; 3383 cmd->qid = ring->qid; 3384 cmd->idx = ring->cur; 3385 3386 tx = (struct iwn_cmd_data *)cmd->data; 3387 /* NB: No need to clear tx, all fields are reinitialized here. */ 3388 tx->scratch = 0; /* clear "scratch" area */ 3389 3390 flags = 0; 3391 if ((params->ibp_flags & IEEE80211_BPF_NOACK) == 0) 3392 flags |= IWN_TX_NEED_ACK; 3393 if (params->ibp_flags & IEEE80211_BPF_RTS) { 3394 if (sc->hw_type != IWN_HW_REV_TYPE_4965) { 3395 /* 5000 autoselects RTS/CTS or CTS-to-self. */ 3396 flags &= ~IWN_TX_NEED_RTS; 3397 flags |= IWN_TX_NEED_PROTECTION; 3398 } else 3399 flags |= IWN_TX_NEED_RTS | IWN_TX_FULL_TXOP; 3400 } 3401 if (params->ibp_flags & IEEE80211_BPF_CTS) { 3402 if (sc->hw_type != IWN_HW_REV_TYPE_4965) { 3403 /* 5000 autoselects RTS/CTS or CTS-to-self. */ 3404 flags &= ~IWN_TX_NEED_CTS; 3405 flags |= IWN_TX_NEED_PROTECTION; 3406 } else 3407 flags |= IWN_TX_NEED_CTS | IWN_TX_FULL_TXOP; 3408 } 3409 if (type == IEEE80211_FC0_TYPE_MGT) { 3410 uint8_t subtype = wh->i_fc[0] & IEEE80211_FC0_SUBTYPE_MASK; 3411 3412 /* Tell HW to set timestamp in probe responses. */ 3413 if (subtype == IEEE80211_FC0_SUBTYPE_PROBE_RESP) 3414 flags |= IWN_TX_INSERT_TSTAMP; 3415 3416 if (subtype == IEEE80211_FC0_SUBTYPE_ASSOC_REQ || 3417 subtype == IEEE80211_FC0_SUBTYPE_REASSOC_REQ) 3418 tx->timeout = htole16(3); 3419 else 3420 tx->timeout = htole16(2); 3421 } else 3422 tx->timeout = htole16(0); 3423 3424 if (hdrlen & 3) { 3425 /* First segment length must be a multiple of 4. */ 3426 flags |= IWN_TX_NEED_PADDING; 3427 pad = 4 - (hdrlen & 3); 3428 } else 3429 pad = 0; 3430 3431 if (ieee80211_radiotap_active_vap(vap)) { 3432 struct iwn_tx_radiotap_header *tap = &sc->sc_txtap; 3433 3434 tap->wt_flags = 0; 3435 tap->wt_rate = rate; 3436 3437 ieee80211_radiotap_tx(vap, m); 3438 } 3439 3440 tx->len = htole16(totlen); 3441 tx->tid = 0; 3442 tx->id = sc->broadcast_id; 3443 tx->rts_ntries = params->ibp_try1; 3444 tx->data_ntries = params->ibp_try0; 3445 tx->lifetime = htole32(IWN_LIFETIME_INFINITE); 3446 tx->plcp = rinfo->plcp; 3447 tx->rflags = rinfo->flags; 3448 /* Group or management frame. */ 3449 tx->linkq = 0; 3450 txant = IWN_LSB(sc->txchainmask); 3451 tx->rflags |= IWN_RFLAG_ANT(txant); 3452 /* Set physical address of "scratch area". */ 3453 tx->loaddr = htole32(IWN_LOADDR(data->scratch_paddr)); 3454 tx->hiaddr = IWN_HIADDR(data->scratch_paddr); 3455 3456 /* Copy 802.11 header in TX command. */ 3457 memcpy((uint8_t *)(tx + 1), wh, hdrlen); 3458 3459 /* Trim 802.11 header. */ 3460 m_adj(m, hdrlen); 3461 tx->security = 0; 3462 tx->flags = htole32(flags); 3463 3464 error = bus_dmamap_load_mbuf_sg(ring->data_dmat, data->map, m, segs, 3465 &nsegs, BUS_DMA_NOWAIT); 3466 if (error != 0) { 3467 if (error != EFBIG) { 3468 device_printf(sc->sc_dev, 3469 "%s: can't map mbuf (error %d)\n", __func__, error); 3470 m_freem(m); 3471 return error; 3472 } 3473 /* Too many DMA segments, linearize mbuf. */ 3474 m1 = m_collapse(m, M_DONTWAIT, IWN_MAX_SCATTER); 3475 if (m1 == NULL) { 3476 device_printf(sc->sc_dev, 3477 "%s: could not defrag mbuf\n", __func__); 3478 m_freem(m); 3479 return ENOBUFS; 3480 } 3481 m = m1; 3482 3483 error = bus_dmamap_load_mbuf_sg(ring->data_dmat, data->map, m, 3484 segs, &nsegs, BUS_DMA_NOWAIT); 3485 if (error != 0) { 3486 device_printf(sc->sc_dev, 3487 "%s: can't map mbuf (error %d)\n", __func__, error); 3488 m_freem(m); 3489 return error; 3490 } 3491 } 3492 3493 data->m = m; 3494 data->ni = ni; 3495 3496 DPRINTF(sc, IWN_DEBUG_XMIT, "%s: qid %d idx %d len %d nsegs %d\n", 3497 __func__, ring->qid, ring->cur, m->m_pkthdr.len, nsegs); 3498 3499 /* Fill TX descriptor. */ 3500 desc->nsegs = 1; 3501 if (m->m_len != 0) 3502 desc->nsegs += nsegs; 3503 /* First DMA segment is used by the TX command. */ 3504 desc->segs[0].addr = htole32(IWN_LOADDR(data->cmd_paddr)); 3505 desc->segs[0].len = htole16(IWN_HIADDR(data->cmd_paddr) | 3506 (4 + sizeof (*tx) + hdrlen + pad) << 4); 3507 /* Other DMA segments are for data payload. */ 3508 seg = &segs[0]; 3509 for (i = 1; i <= nsegs; i++) { 3510 desc->segs[i].addr = htole32(IWN_LOADDR(seg->ds_addr)); 3511 desc->segs[i].len = htole16(IWN_HIADDR(seg->ds_addr) | 3512 seg->ds_len << 4); 3513 seg++; 3514 } 3515 3516 bus_dmamap_sync(ring->data_dmat, data->map, BUS_DMASYNC_PREWRITE); 3517 bus_dmamap_sync(ring->data_dmat, ring->cmd_dma.map, 3518 BUS_DMASYNC_PREWRITE); 3519 bus_dmamap_sync(ring->desc_dma.tag, ring->desc_dma.map, 3520 BUS_DMASYNC_PREWRITE); 3521 3522 #ifdef notyet 3523 /* Update TX scheduler. */ 3524 ops->update_sched(sc, ring->qid, ring->cur, tx->id, totlen); 3525 #endif 3526 3527 /* Kick TX ring. */ 3528 ring->cur = (ring->cur + 1) % IWN_TX_RING_COUNT; 3529 IWN_WRITE(sc, IWN_HBUS_TARG_WRPTR, ring->qid << 8 | ring->cur); 3530 3531 /* Mark TX ring as full if we reach a certain threshold. */ 3532 if (++ring->queued > IWN_TX_RING_HIMARK) 3533 sc->qfullmsk |= 1 << ring->qid; 3534 3535 return 0; 3536 } 3537 3538 static int 3539 iwn_raw_xmit(struct ieee80211_node *ni, struct mbuf *m, 3540 const struct ieee80211_bpf_params *params) 3541 { 3542 struct ieee80211com *ic = ni->ni_ic; 3543 struct ifnet *ifp = ic->ic_ifp; 3544 struct iwn_softc *sc = ifp->if_softc; 3545 int error = 0; 3546 3547 if ((ifp->if_drv_flags & IFF_DRV_RUNNING) == 0) { 3548 ieee80211_free_node(ni); 3549 m_freem(m); 3550 return ENETDOWN; 3551 } 3552 3553 IWN_LOCK(sc); 3554 if (params == NULL) { 3555 /* 3556 * Legacy path; interpret frame contents to decide 3557 * precisely how to send the frame. 3558 */ 3559 error = iwn_tx_data(sc, m, ni); 3560 } else { 3561 /* 3562 * Caller supplied explicit parameters to use in 3563 * sending the frame. 3564 */ 3565 error = iwn_tx_data_raw(sc, m, ni, params); 3566 } 3567 if (error != 0) { 3568 /* NB: m is reclaimed on tx failure */ 3569 ieee80211_free_node(ni); 3570 ifp->if_oerrors++; 3571 } 3572 sc->sc_tx_timer = 5; 3573 3574 IWN_UNLOCK(sc); 3575 return error; 3576 } 3577 3578 static void 3579 iwn_start(struct ifnet *ifp) 3580 { 3581 struct iwn_softc *sc = ifp->if_softc; 3582 3583 IWN_LOCK(sc); 3584 iwn_start_locked(ifp); 3585 IWN_UNLOCK(sc); 3586 } 3587 3588 static void 3589 iwn_start_locked(struct ifnet *ifp) 3590 { 3591 struct iwn_softc *sc = ifp->if_softc; 3592 struct ieee80211_node *ni; 3593 struct mbuf *m; 3594 3595 IWN_LOCK_ASSERT(sc); 3596 3597 if ((ifp->if_drv_flags & IFF_DRV_RUNNING) == 0 || 3598 (ifp->if_drv_flags & IFF_DRV_OACTIVE)) 3599 return; 3600 3601 for (;;) { 3602 if (sc->qfullmsk != 0) { 3603 ifp->if_drv_flags |= IFF_DRV_OACTIVE; 3604 break; 3605 } 3606 IFQ_DRV_DEQUEUE(&ifp->if_snd, m); 3607 if (m == NULL) 3608 break; 3609 ni = (struct ieee80211_node *)m->m_pkthdr.rcvif; 3610 if (iwn_tx_data(sc, m, ni) != 0) { 3611 ieee80211_free_node(ni); 3612 ifp->if_oerrors++; 3613 continue; 3614 } 3615 sc->sc_tx_timer = 5; 3616 } 3617 } 3618 3619 static void 3620 iwn_watchdog(void *arg) 3621 { 3622 struct iwn_softc *sc = arg; 3623 struct ifnet *ifp = sc->sc_ifp; 3624 struct ieee80211com *ic = ifp->if_l2com; 3625 3626 IWN_LOCK_ASSERT(sc); 3627 3628 KASSERT(ifp->if_drv_flags & IFF_DRV_RUNNING, ("not running")); 3629 3630 if (sc->sc_tx_timer > 0) { 3631 if (--sc->sc_tx_timer == 0) { 3632 if_printf(ifp, "device timeout\n"); 3633 ieee80211_runtask(ic, &sc->sc_reinit_task); 3634 return; 3635 } 3636 } 3637 callout_reset(&sc->watchdog_to, hz, iwn_watchdog, sc); 3638 } 3639 3640 static int 3641 iwn_ioctl(struct ifnet *ifp, u_long cmd, caddr_t data) 3642 { 3643 struct iwn_softc *sc = ifp->if_softc; 3644 struct ieee80211com *ic = ifp->if_l2com; 3645 struct ieee80211vap *vap = TAILQ_FIRST(&ic->ic_vaps); 3646 struct ifreq *ifr = (struct ifreq *) data; 3647 int error = 0, startall = 0, stop = 0; 3648 3649 switch (cmd) { 3650 case SIOCGIFADDR: 3651 error = ether_ioctl(ifp, cmd, data); 3652 break; 3653 case SIOCSIFFLAGS: 3654 IWN_LOCK(sc); 3655 if (ifp->if_flags & IFF_UP) { 3656 if (!(ifp->if_drv_flags & IFF_DRV_RUNNING)) { 3657 iwn_init_locked(sc); 3658 if (IWN_READ(sc, IWN_GP_CNTRL) & IWN_GP_CNTRL_RFKILL) 3659 startall = 1; 3660 else 3661 stop = 1; 3662 } 3663 } else { 3664 if (ifp->if_drv_flags & IFF_DRV_RUNNING) 3665 iwn_stop_locked(sc); 3666 } 3667 IWN_UNLOCK(sc); 3668 if (startall) 3669 ieee80211_start_all(ic); 3670 else if (vap != NULL && stop) 3671 ieee80211_stop(vap); 3672 break; 3673 case SIOCGIFMEDIA: 3674 error = ifmedia_ioctl(ifp, ifr, &ic->ic_media, cmd); 3675 break; 3676 default: 3677 error = EINVAL; 3678 break; 3679 } 3680 return error; 3681 } 3682 3683 /* 3684 * Send a command to the firmware. 3685 */ 3686 static int 3687 iwn_cmd(struct iwn_softc *sc, int code, const void *buf, int size, int async) 3688 { 3689 struct iwn_tx_ring *ring = &sc->txq[4]; 3690 struct iwn_tx_desc *desc; 3691 struct iwn_tx_data *data; 3692 struct iwn_tx_cmd *cmd; 3693 struct mbuf *m; 3694 bus_addr_t paddr; 3695 int totlen, error; 3696 3697 IWN_LOCK_ASSERT(sc); 3698 3699 desc = &ring->desc[ring->cur]; 3700 data = &ring->data[ring->cur]; 3701 totlen = 4 + size; 3702 3703 if (size > sizeof cmd->data) { 3704 /* Command is too large to fit in a descriptor. */ 3705 if (totlen > MCLBYTES) 3706 return EINVAL; 3707 m = m_getjcl(M_DONTWAIT, MT_DATA, M_PKTHDR, MJUMPAGESIZE); 3708 if (m == NULL) 3709 return ENOMEM; 3710 cmd = mtod(m, struct iwn_tx_cmd *); 3711 error = bus_dmamap_load(ring->data_dmat, data->map, cmd, 3712 totlen, iwn_dma_map_addr, &paddr, BUS_DMA_NOWAIT); 3713 if (error != 0) { 3714 m_freem(m); 3715 return error; 3716 } 3717 data->m = m; 3718 } else { 3719 cmd = &ring->cmd[ring->cur]; 3720 paddr = data->cmd_paddr; 3721 } 3722 3723 cmd->code = code; 3724 cmd->flags = 0; 3725 cmd->qid = ring->qid; 3726 cmd->idx = ring->cur; 3727 memcpy(cmd->data, buf, size); 3728 3729 desc->nsegs = 1; 3730 desc->segs[0].addr = htole32(IWN_LOADDR(paddr)); 3731 desc->segs[0].len = htole16(IWN_HIADDR(paddr) | totlen << 4); 3732 3733 DPRINTF(sc, IWN_DEBUG_CMD, "%s: %s (0x%x) flags %d qid %d idx %d\n", 3734 __func__, iwn_intr_str(cmd->code), cmd->code, 3735 cmd->flags, cmd->qid, cmd->idx); 3736 3737 if (size > sizeof cmd->data) { 3738 bus_dmamap_sync(ring->data_dmat, data->map, 3739 BUS_DMASYNC_PREWRITE); 3740 } else { 3741 bus_dmamap_sync(ring->data_dmat, ring->cmd_dma.map, 3742 BUS_DMASYNC_PREWRITE); 3743 } 3744 bus_dmamap_sync(ring->desc_dma.tag, ring->desc_dma.map, 3745 BUS_DMASYNC_PREWRITE); 3746 3747 #ifdef notyet 3748 /* Update TX scheduler. */ 3749 ops->update_sched(sc, ring->qid, ring->cur, 0, 0); 3750 #endif 3751 3752 /* Kick command ring. */ 3753 ring->cur = (ring->cur + 1) % IWN_TX_RING_COUNT; 3754 IWN_WRITE(sc, IWN_HBUS_TARG_WRPTR, ring->qid << 8 | ring->cur); 3755 3756 return async ? 0 : msleep(desc, &sc->sc_mtx, PCATCH, "iwncmd", hz); 3757 } 3758 3759 static int 3760 iwn4965_add_node(struct iwn_softc *sc, struct iwn_node_info *node, int async) 3761 { 3762 struct iwn4965_node_info hnode; 3763 caddr_t src, dst; 3764 3765 /* 3766 * We use the node structure for 5000 Series internally (it is 3767 * a superset of the one for 4965AGN). We thus copy the common 3768 * fields before sending the command. 3769 */ 3770 src = (caddr_t)node; 3771 dst = (caddr_t)&hnode; 3772 memcpy(dst, src, 48); 3773 /* Skip TSC, RX MIC and TX MIC fields from ``src''. */ 3774 memcpy(dst + 48, src + 72, 20); 3775 return iwn_cmd(sc, IWN_CMD_ADD_NODE, &hnode, sizeof hnode, async); 3776 } 3777 3778 static int 3779 iwn5000_add_node(struct iwn_softc *sc, struct iwn_node_info *node, int async) 3780 { 3781 /* Direct mapping. */ 3782 return iwn_cmd(sc, IWN_CMD_ADD_NODE, node, sizeof (*node), async); 3783 } 3784 3785 static int 3786 iwn_set_link_quality(struct iwn_softc *sc, struct ieee80211_node *ni) 3787 { 3788 struct iwn_node *wn = (void *)ni; 3789 struct ieee80211_rateset *rs = &ni->ni_rates; 3790 struct iwn_cmd_link_quality linkq; 3791 const struct iwn_rate *rinfo; 3792 uint8_t txant; 3793 int i, txrate; 3794 3795 /* Use the first valid TX antenna. */ 3796 txant = IWN_LSB(sc->txchainmask); 3797 3798 memset(&linkq, 0, sizeof linkq); 3799 linkq.id = wn->id; 3800 linkq.antmsk_1stream = txant; 3801 linkq.antmsk_2stream = IWN_ANT_AB; 3802 linkq.ampdu_max = 31; 3803 linkq.ampdu_threshold = 3; 3804 linkq.ampdu_limit = htole16(4000); /* 4ms */ 3805 3806 /* Start at highest available bit-rate. */ 3807 txrate = rs->rs_nrates - 1; 3808 for (i = 0; i < IWN_MAX_TX_RETRIES; i++) { 3809 rinfo = &iwn_rates[wn->ridx[txrate]]; 3810 linkq.retry[i].plcp = rinfo->plcp; 3811 linkq.retry[i].rflags = rinfo->flags; 3812 linkq.retry[i].rflags |= IWN_RFLAG_ANT(txant); 3813 /* Next retry at immediate lower bit-rate. */ 3814 if (txrate > 0) 3815 txrate--; 3816 } 3817 return iwn_cmd(sc, IWN_CMD_LINK_QUALITY, &linkq, sizeof linkq, 1); 3818 } 3819 3820 /* 3821 * Broadcast node is used to send group-addressed and management frames. 3822 */ 3823 static int 3824 iwn_add_broadcast_node(struct iwn_softc *sc, int async) 3825 { 3826 struct iwn_ops *ops = &sc->ops; 3827 struct ifnet *ifp = sc->sc_ifp; 3828 struct ieee80211com *ic = ifp->if_l2com; 3829 struct iwn_node_info node; 3830 struct iwn_cmd_link_quality linkq; 3831 const struct iwn_rate *rinfo; 3832 uint8_t txant; 3833 int i, error; 3834 3835 memset(&node, 0, sizeof node); 3836 IEEE80211_ADDR_COPY(node.macaddr, ifp->if_broadcastaddr); 3837 node.id = sc->broadcast_id; 3838 DPRINTF(sc, IWN_DEBUG_RESET, "%s: adding broadcast node\n", __func__); 3839 if ((error = ops->add_node(sc, &node, async)) != 0) 3840 return error; 3841 3842 /* Use the first valid TX antenna. */ 3843 txant = IWN_LSB(sc->txchainmask); 3844 3845 memset(&linkq, 0, sizeof linkq); 3846 linkq.id = sc->broadcast_id; 3847 linkq.antmsk_1stream = txant; 3848 linkq.antmsk_2stream = IWN_ANT_AB; 3849 linkq.ampdu_max = 64; 3850 linkq.ampdu_threshold = 3; 3851 linkq.ampdu_limit = htole16(4000); /* 4ms */ 3852 3853 /* Use lowest mandatory bit-rate. */ 3854 if (IEEE80211_IS_CHAN_5GHZ(ic->ic_curchan)) 3855 rinfo = &iwn_rates[IWN_RIDX_OFDM6]; 3856 else 3857 rinfo = &iwn_rates[IWN_RIDX_CCK1]; 3858 linkq.retry[0].plcp = rinfo->plcp; 3859 linkq.retry[0].rflags = rinfo->flags; 3860 linkq.retry[0].rflags |= IWN_RFLAG_ANT(txant); 3861 /* Use same bit-rate for all TX retries. */ 3862 for (i = 1; i < IWN_MAX_TX_RETRIES; i++) { 3863 linkq.retry[i].plcp = linkq.retry[0].plcp; 3864 linkq.retry[i].rflags = linkq.retry[0].rflags; 3865 } 3866 return iwn_cmd(sc, IWN_CMD_LINK_QUALITY, &linkq, sizeof linkq, async); 3867 } 3868 3869 static int 3870 iwn_updateedca(struct ieee80211com *ic) 3871 { 3872 #define IWN_EXP2(x) ((1 << (x)) - 1) /* CWmin = 2^ECWmin - 1 */ 3873 struct iwn_softc *sc = ic->ic_ifp->if_softc; 3874 struct iwn_edca_params cmd; 3875 int aci; 3876 3877 memset(&cmd, 0, sizeof cmd); 3878 cmd.flags = htole32(IWN_EDCA_UPDATE); 3879 for (aci = 0; aci < WME_NUM_AC; aci++) { 3880 const struct wmeParams *ac = 3881 &ic->ic_wme.wme_chanParams.cap_wmeParams[aci]; 3882 cmd.ac[aci].aifsn = ac->wmep_aifsn; 3883 cmd.ac[aci].cwmin = htole16(IWN_EXP2(ac->wmep_logcwmin)); 3884 cmd.ac[aci].cwmax = htole16(IWN_EXP2(ac->wmep_logcwmax)); 3885 cmd.ac[aci].txoplimit = 3886 htole16(IEEE80211_TXOP_TO_US(ac->wmep_txopLimit)); 3887 } 3888 IEEE80211_UNLOCK(ic); 3889 IWN_LOCK(sc); 3890 (void)iwn_cmd(sc, IWN_CMD_EDCA_PARAMS, &cmd, sizeof cmd, 1); 3891 IWN_UNLOCK(sc); 3892 IEEE80211_LOCK(ic); 3893 return 0; 3894 #undef IWN_EXP2 3895 } 3896 3897 static void 3898 iwn_update_mcast(struct ifnet *ifp) 3899 { 3900 /* Ignore */ 3901 } 3902 3903 static void 3904 iwn_set_led(struct iwn_softc *sc, uint8_t which, uint8_t off, uint8_t on) 3905 { 3906 struct iwn_cmd_led led; 3907 3908 /* Clear microcode LED ownership. */ 3909 IWN_CLRBITS(sc, IWN_LED, IWN_LED_BSM_CTRL); 3910 3911 led.which = which; 3912 led.unit = htole32(10000); /* on/off in unit of 100ms */ 3913 led.off = off; 3914 led.on = on; 3915 (void)iwn_cmd(sc, IWN_CMD_SET_LED, &led, sizeof led, 1); 3916 } 3917 3918 /* 3919 * Set the critical temperature at which the firmware will stop the radio 3920 * and notify us. 3921 */ 3922 static int 3923 iwn_set_critical_temp(struct iwn_softc *sc) 3924 { 3925 struct iwn_critical_temp crit; 3926 int32_t temp; 3927 3928 IWN_WRITE(sc, IWN_UCODE_GP1_CLR, IWN_UCODE_GP1_CTEMP_STOP_RF); 3929 3930 if (sc->hw_type == IWN_HW_REV_TYPE_5150) 3931 temp = (IWN_CTOK(110) - sc->temp_off) * -5; 3932 else if (sc->hw_type == IWN_HW_REV_TYPE_4965) 3933 temp = IWN_CTOK(110); 3934 else 3935 temp = 110; 3936 memset(&crit, 0, sizeof crit); 3937 crit.tempR = htole32(temp); 3938 DPRINTF(sc, IWN_DEBUG_RESET, "setting critical temp to %d\n", temp); 3939 return iwn_cmd(sc, IWN_CMD_SET_CRITICAL_TEMP, &crit, sizeof crit, 0); 3940 } 3941 3942 static int 3943 iwn_set_timing(struct iwn_softc *sc, struct ieee80211_node *ni) 3944 { 3945 struct iwn_cmd_timing cmd; 3946 uint64_t val, mod; 3947 3948 memset(&cmd, 0, sizeof cmd); 3949 memcpy(&cmd.tstamp, ni->ni_tstamp.data, sizeof (uint64_t)); 3950 cmd.bintval = htole16(ni->ni_intval); 3951 cmd.lintval = htole16(10); 3952 3953 /* Compute remaining time until next beacon. */ 3954 val = (uint64_t)ni->ni_intval * IEEE80211_DUR_TU; 3955 mod = le64toh(cmd.tstamp) % val; 3956 cmd.binitval = htole32((uint32_t)(val - mod)); 3957 3958 DPRINTF(sc, IWN_DEBUG_RESET, "timing bintval=%u tstamp=%ju, init=%u\n", 3959 ni->ni_intval, le64toh(cmd.tstamp), (uint32_t)(val - mod)); 3960 3961 return iwn_cmd(sc, IWN_CMD_TIMING, &cmd, sizeof cmd, 1); 3962 } 3963 3964 static void 3965 iwn4965_power_calibration(struct iwn_softc *sc, int temp) 3966 { 3967 struct ifnet *ifp = sc->sc_ifp; 3968 struct ieee80211com *ic = ifp->if_l2com; 3969 3970 /* Adjust TX power if need be (delta >= 3 degC). */ 3971 DPRINTF(sc, IWN_DEBUG_CALIBRATE, "%s: temperature %d->%d\n", 3972 __func__, sc->temp, temp); 3973 if (abs(temp - sc->temp) >= 3) { 3974 /* Record temperature of last calibration. */ 3975 sc->temp = temp; 3976 (void)iwn4965_set_txpower(sc, ic->ic_bsschan, 1); 3977 } 3978 } 3979 3980 /* 3981 * Set TX power for current channel (each rate has its own power settings). 3982 * This function takes into account the regulatory information from EEPROM, 3983 * the current temperature and the current voltage. 3984 */ 3985 static int 3986 iwn4965_set_txpower(struct iwn_softc *sc, struct ieee80211_channel *ch, 3987 int async) 3988 { 3989 /* Fixed-point arithmetic division using a n-bit fractional part. */ 3990 #define fdivround(a, b, n) \ 3991 ((((1 << n) * (a)) / (b) + (1 << n) / 2) / (1 << n)) 3992 /* Linear interpolation. */ 3993 #define interpolate(x, x1, y1, x2, y2, n) \ 3994 ((y1) + fdivround(((int)(x) - (x1)) * ((y2) - (y1)), (x2) - (x1), n)) 3995 3996 static const int tdiv[IWN_NATTEN_GROUPS] = { 9, 8, 8, 8, 6 }; 3997 struct iwn_ucode_info *uc = &sc->ucode_info; 3998 struct iwn4965_cmd_txpower cmd; 3999 struct iwn4965_eeprom_chan_samples *chans; 4000 const uint8_t *rf_gain, *dsp_gain; 4001 int32_t vdiff, tdiff; 4002 int i, c, grp, maxpwr; 4003 uint8_t chan; 4004 4005 /* Retrieve current channel from last RXON. */ 4006 chan = sc->rxon.chan; 4007 DPRINTF(sc, IWN_DEBUG_RESET, "setting TX power for channel %d\n", 4008 chan); 4009 4010 memset(&cmd, 0, sizeof cmd); 4011 cmd.band = IEEE80211_IS_CHAN_5GHZ(ch) ? 0 : 1; 4012 cmd.chan = chan; 4013 4014 if (IEEE80211_IS_CHAN_5GHZ(ch)) { 4015 maxpwr = sc->maxpwr5GHz; 4016 rf_gain = iwn4965_rf_gain_5ghz; 4017 dsp_gain = iwn4965_dsp_gain_5ghz; 4018 } else { 4019 maxpwr = sc->maxpwr2GHz; 4020 rf_gain = iwn4965_rf_gain_2ghz; 4021 dsp_gain = iwn4965_dsp_gain_2ghz; 4022 } 4023 4024 /* Compute voltage compensation. */ 4025 vdiff = ((int32_t)le32toh(uc->volt) - sc->eeprom_voltage) / 7; 4026 if (vdiff > 0) 4027 vdiff *= 2; 4028 if (abs(vdiff) > 2) 4029 vdiff = 0; 4030 DPRINTF(sc, IWN_DEBUG_CALIBRATE | IWN_DEBUG_TXPOW, 4031 "%s: voltage compensation=%d (UCODE=%d, EEPROM=%d)\n", 4032 __func__, vdiff, le32toh(uc->volt), sc->eeprom_voltage); 4033 4034 /* Get channel attenuation group. */ 4035 if (chan <= 20) /* 1-20 */ 4036 grp = 4; 4037 else if (chan <= 43) /* 34-43 */ 4038 grp = 0; 4039 else if (chan <= 70) /* 44-70 */ 4040 grp = 1; 4041 else if (chan <= 124) /* 71-124 */ 4042 grp = 2; 4043 else /* 125-200 */ 4044 grp = 3; 4045 DPRINTF(sc, IWN_DEBUG_CALIBRATE | IWN_DEBUG_TXPOW, 4046 "%s: chan %d, attenuation group=%d\n", __func__, chan, grp); 4047 4048 /* Get channel sub-band. */ 4049 for (i = 0; i < IWN_NBANDS; i++) 4050 if (sc->bands[i].lo != 0 && 4051 sc->bands[i].lo <= chan && chan <= sc->bands[i].hi) 4052 break; 4053 if (i == IWN_NBANDS) /* Can't happen in real-life. */ 4054 return EINVAL; 4055 chans = sc->bands[i].chans; 4056 DPRINTF(sc, IWN_DEBUG_CALIBRATE | IWN_DEBUG_TXPOW, 4057 "%s: chan %d sub-band=%d\n", __func__, chan, i); 4058 4059 for (c = 0; c < 2; c++) { 4060 uint8_t power, gain, temp; 4061 int maxchpwr, pwr, ridx, idx; 4062 4063 power = interpolate(chan, 4064 chans[0].num, chans[0].samples[c][1].power, 4065 chans[1].num, chans[1].samples[c][1].power, 1); 4066 gain = interpolate(chan, 4067 chans[0].num, chans[0].samples[c][1].gain, 4068 chans[1].num, chans[1].samples[c][1].gain, 1); 4069 temp = interpolate(chan, 4070 chans[0].num, chans[0].samples[c][1].temp, 4071 chans[1].num, chans[1].samples[c][1].temp, 1); 4072 DPRINTF(sc, IWN_DEBUG_CALIBRATE | IWN_DEBUG_TXPOW, 4073 "%s: Tx chain %d: power=%d gain=%d temp=%d\n", 4074 __func__, c, power, gain, temp); 4075 4076 /* Compute temperature compensation. */ 4077 tdiff = ((sc->temp - temp) * 2) / tdiv[grp]; 4078 DPRINTF(sc, IWN_DEBUG_CALIBRATE | IWN_DEBUG_TXPOW, 4079 "%s: temperature compensation=%d (current=%d, EEPROM=%d)\n", 4080 __func__, tdiff, sc->temp, temp); 4081 4082 for (ridx = 0; ridx <= IWN_RIDX_MAX; ridx++) { 4083 /* Convert dBm to half-dBm. */ 4084 maxchpwr = sc->maxpwr[chan] * 2; 4085 if ((ridx / 8) & 1) 4086 maxchpwr -= 6; /* MIMO 2T: -3dB */ 4087 4088 pwr = maxpwr; 4089 4090 /* Adjust TX power based on rate. */ 4091 if ((ridx % 8) == 5) 4092 pwr -= 15; /* OFDM48: -7.5dB */ 4093 else if ((ridx % 8) == 6) 4094 pwr -= 17; /* OFDM54: -8.5dB */ 4095 else if ((ridx % 8) == 7) 4096 pwr -= 20; /* OFDM60: -10dB */ 4097 else 4098 pwr -= 10; /* Others: -5dB */ 4099 4100 /* Do not exceed channel max TX power. */ 4101 if (pwr > maxchpwr) 4102 pwr = maxchpwr; 4103 4104 idx = gain - (pwr - power) - tdiff - vdiff; 4105 if ((ridx / 8) & 1) /* MIMO */ 4106 idx += (int32_t)le32toh(uc->atten[grp][c]); 4107 4108 if (cmd.band == 0) 4109 idx += 9; /* 5GHz */ 4110 if (ridx == IWN_RIDX_MAX) 4111 idx += 5; /* CCK */ 4112 4113 /* Make sure idx stays in a valid range. */ 4114 if (idx < 0) 4115 idx = 0; 4116 else if (idx > IWN4965_MAX_PWR_INDEX) 4117 idx = IWN4965_MAX_PWR_INDEX; 4118 4119 DPRINTF(sc, IWN_DEBUG_CALIBRATE | IWN_DEBUG_TXPOW, 4120 "%s: Tx chain %d, rate idx %d: power=%d\n", 4121 __func__, c, ridx, idx); 4122 cmd.power[ridx].rf_gain[c] = rf_gain[idx]; 4123 cmd.power[ridx].dsp_gain[c] = dsp_gain[idx]; 4124 } 4125 } 4126 4127 DPRINTF(sc, IWN_DEBUG_CALIBRATE | IWN_DEBUG_TXPOW, 4128 "%s: set tx power for chan %d\n", __func__, chan); 4129 return iwn_cmd(sc, IWN_CMD_TXPOWER, &cmd, sizeof cmd, async); 4130 4131 #undef interpolate 4132 #undef fdivround 4133 } 4134 4135 static int 4136 iwn5000_set_txpower(struct iwn_softc *sc, struct ieee80211_channel *ch, 4137 int async) 4138 { 4139 struct iwn5000_cmd_txpower cmd; 4140 4141 /* 4142 * TX power calibration is handled automatically by the firmware 4143 * for 5000 Series. 4144 */ 4145 memset(&cmd, 0, sizeof cmd); 4146 cmd.global_limit = 2 * IWN5000_TXPOWER_MAX_DBM; /* 16 dBm */ 4147 cmd.flags = IWN5000_TXPOWER_NO_CLOSED; 4148 cmd.srv_limit = IWN5000_TXPOWER_AUTO; 4149 DPRINTF(sc, IWN_DEBUG_CALIBRATE, "%s: setting TX power\n", __func__); 4150 return iwn_cmd(sc, IWN_CMD_TXPOWER_DBM, &cmd, sizeof cmd, async); 4151 } 4152 4153 /* 4154 * Retrieve the maximum RSSI (in dBm) among receivers. 4155 */ 4156 static int 4157 iwn4965_get_rssi(struct iwn_softc *sc, struct iwn_rx_stat *stat) 4158 { 4159 struct iwn4965_rx_phystat *phy = (void *)stat->phybuf; 4160 uint8_t mask, agc; 4161 int rssi; 4162 4163 mask = (le16toh(phy->antenna) >> 4) & IWN_ANT_ABC; 4164 agc = (le16toh(phy->agc) >> 7) & 0x7f; 4165 4166 rssi = 0; 4167 if (mask & IWN_ANT_A) 4168 rssi = MAX(rssi, phy->rssi[0]); 4169 if (mask & IWN_ANT_B) 4170 rssi = MAX(rssi, phy->rssi[2]); 4171 if (mask & IWN_ANT_C) 4172 rssi = MAX(rssi, phy->rssi[4]); 4173 4174 DPRINTF(sc, IWN_DEBUG_RECV, 4175 "%s: agc %d mask 0x%x rssi %d %d %d result %d\n", __func__, agc, 4176 mask, phy->rssi[0], phy->rssi[2], phy->rssi[4], 4177 rssi - agc - IWN_RSSI_TO_DBM); 4178 return rssi - agc - IWN_RSSI_TO_DBM; 4179 } 4180 4181 static int 4182 iwn5000_get_rssi(struct iwn_softc *sc, struct iwn_rx_stat *stat) 4183 { 4184 struct iwn5000_rx_phystat *phy = (void *)stat->phybuf; 4185 uint8_t agc; 4186 int rssi; 4187 4188 agc = (le32toh(phy->agc) >> 9) & 0x7f; 4189 4190 rssi = MAX(le16toh(phy->rssi[0]) & 0xff, 4191 le16toh(phy->rssi[1]) & 0xff); 4192 rssi = MAX(le16toh(phy->rssi[2]) & 0xff, rssi); 4193 4194 DPRINTF(sc, IWN_DEBUG_RECV, 4195 "%s: agc %d rssi %d %d %d result %d\n", __func__, agc, 4196 phy->rssi[0], phy->rssi[1], phy->rssi[2], 4197 rssi - agc - IWN_RSSI_TO_DBM); 4198 return rssi - agc - IWN_RSSI_TO_DBM; 4199 } 4200 4201 /* 4202 * Retrieve the average noise (in dBm) among receivers. 4203 */ 4204 static int 4205 iwn_get_noise(const struct iwn_rx_general_stats *stats) 4206 { 4207 int i, total, nbant, noise; 4208 4209 total = nbant = 0; 4210 for (i = 0; i < 3; i++) { 4211 if ((noise = le32toh(stats->noise[i]) & 0xff) == 0) 4212 continue; 4213 total += noise; 4214 nbant++; 4215 } 4216 /* There should be at least one antenna but check anyway. */ 4217 return (nbant == 0) ? -127 : (total / nbant) - 107; 4218 } 4219 4220 /* 4221 * Compute temperature (in degC) from last received statistics. 4222 */ 4223 static int 4224 iwn4965_get_temperature(struct iwn_softc *sc) 4225 { 4226 struct iwn_ucode_info *uc = &sc->ucode_info; 4227 int32_t r1, r2, r3, r4, temp; 4228 4229 r1 = le32toh(uc->temp[0].chan20MHz); 4230 r2 = le32toh(uc->temp[1].chan20MHz); 4231 r3 = le32toh(uc->temp[2].chan20MHz); 4232 r4 = le32toh(sc->rawtemp); 4233 4234 if (r1 == r3) /* Prevents division by 0 (should not happen). */ 4235 return 0; 4236 4237 /* Sign-extend 23-bit R4 value to 32-bit. */ 4238 r4 = ((r4 & 0xffffff) ^ 0x800000) - 0x800000; 4239 /* Compute temperature in Kelvin. */ 4240 temp = (259 * (r4 - r2)) / (r3 - r1); 4241 temp = (temp * 97) / 100 + 8; 4242 4243 DPRINTF(sc, IWN_DEBUG_ANY, "temperature %dK/%dC\n", temp, 4244 IWN_KTOC(temp)); 4245 return IWN_KTOC(temp); 4246 } 4247 4248 static int 4249 iwn5000_get_temperature(struct iwn_softc *sc) 4250 { 4251 int32_t temp; 4252 4253 /* 4254 * Temperature is not used by the driver for 5000 Series because 4255 * TX power calibration is handled by firmware. 4256 */ 4257 temp = le32toh(sc->rawtemp); 4258 if (sc->hw_type == IWN_HW_REV_TYPE_5150) { 4259 temp = (temp / -5) + sc->temp_off; 4260 temp = IWN_KTOC(temp); 4261 } 4262 return temp; 4263 } 4264 4265 /* 4266 * Initialize sensitivity calibration state machine. 4267 */ 4268 static int 4269 iwn_init_sensitivity(struct iwn_softc *sc) 4270 { 4271 struct iwn_ops *ops = &sc->ops; 4272 struct iwn_calib_state *calib = &sc->calib; 4273 uint32_t flags; 4274 int error; 4275 4276 /* Reset calibration state machine. */ 4277 memset(calib, 0, sizeof (*calib)); 4278 calib->state = IWN_CALIB_STATE_INIT; 4279 calib->cck_state = IWN_CCK_STATE_HIFA; 4280 /* Set initial correlation values. */ 4281 calib->ofdm_x1 = sc->limits->min_ofdm_x1; 4282 calib->ofdm_mrc_x1 = sc->limits->min_ofdm_mrc_x1; 4283 calib->ofdm_x4 = sc->limits->min_ofdm_x4; 4284 calib->ofdm_mrc_x4 = sc->limits->min_ofdm_mrc_x4; 4285 calib->cck_x4 = 125; 4286 calib->cck_mrc_x4 = sc->limits->min_cck_mrc_x4; 4287 calib->energy_cck = sc->limits->energy_cck; 4288 4289 /* Write initial sensitivity. */ 4290 if ((error = iwn_send_sensitivity(sc)) != 0) 4291 return error; 4292 4293 /* Write initial gains. */ 4294 if ((error = ops->init_gains(sc)) != 0) 4295 return error; 4296 4297 /* Request statistics at each beacon interval. */ 4298 flags = 0; 4299 DPRINTF(sc, IWN_DEBUG_CALIBRATE, "%s: sending request for statistics\n", 4300 __func__); 4301 return iwn_cmd(sc, IWN_CMD_GET_STATISTICS, &flags, sizeof flags, 1); 4302 } 4303 4304 /* 4305 * Collect noise and RSSI statistics for the first 20 beacons received 4306 * after association and use them to determine connected antennas and 4307 * to set differential gains. 4308 */ 4309 static void 4310 iwn_collect_noise(struct iwn_softc *sc, 4311 const struct iwn_rx_general_stats *stats) 4312 { 4313 struct iwn_ops *ops = &sc->ops; 4314 struct iwn_calib_state *calib = &sc->calib; 4315 uint32_t val; 4316 int i; 4317 4318 /* Accumulate RSSI and noise for all 3 antennas. */ 4319 for (i = 0; i < 3; i++) { 4320 calib->rssi[i] += le32toh(stats->rssi[i]) & 0xff; 4321 calib->noise[i] += le32toh(stats->noise[i]) & 0xff; 4322 } 4323 /* NB: We update differential gains only once after 20 beacons. */ 4324 if (++calib->nbeacons < 20) 4325 return; 4326 4327 /* Determine highest average RSSI. */ 4328 val = MAX(calib->rssi[0], calib->rssi[1]); 4329 val = MAX(calib->rssi[2], val); 4330 4331 /* Determine which antennas are connected. */ 4332 sc->chainmask = sc->rxchainmask; 4333 for (i = 0; i < 3; i++) 4334 if (val - calib->rssi[i] > 15 * 20) 4335 sc->chainmask &= ~(1 << i); 4336 DPRINTF(sc, IWN_DEBUG_CALIBRATE, 4337 "%s: RX chains mask: theoretical=0x%x, actual=0x%x\n", 4338 __func__, sc->rxchainmask, sc->chainmask); 4339 4340 /* If none of the TX antennas are connected, keep at least one. */ 4341 if ((sc->chainmask & sc->txchainmask) == 0) 4342 sc->chainmask |= IWN_LSB(sc->txchainmask); 4343 4344 (void)ops->set_gains(sc); 4345 calib->state = IWN_CALIB_STATE_RUN; 4346 4347 #ifdef notyet 4348 /* XXX Disable RX chains with no antennas connected. */ 4349 sc->rxon.rxchain = htole16(IWN_RXCHAIN_SEL(sc->chainmask)); 4350 (void)iwn_cmd(sc, IWN_CMD_RXON, &sc->rxon, sc->rxonsz, 1); 4351 #endif 4352 4353 #if 0 4354 /* XXX: not yet */ 4355 /* Enable power-saving mode if requested by user. */ 4356 if (sc->sc_ic.ic_flags & IEEE80211_F_PMGTON) 4357 (void)iwn_set_pslevel(sc, 0, 3, 1); 4358 #endif 4359 } 4360 4361 static int 4362 iwn4965_init_gains(struct iwn_softc *sc) 4363 { 4364 struct iwn_phy_calib_gain cmd; 4365 4366 memset(&cmd, 0, sizeof cmd); 4367 cmd.code = IWN4965_PHY_CALIB_DIFF_GAIN; 4368 /* Differential gains initially set to 0 for all 3 antennas. */ 4369 DPRINTF(sc, IWN_DEBUG_CALIBRATE, 4370 "%s: setting initial differential gains\n", __func__); 4371 return iwn_cmd(sc, IWN_CMD_PHY_CALIB, &cmd, sizeof cmd, 1); 4372 } 4373 4374 static int 4375 iwn5000_init_gains(struct iwn_softc *sc) 4376 { 4377 struct iwn_phy_calib cmd; 4378 4379 memset(&cmd, 0, sizeof cmd); 4380 cmd.code = sc->reset_noise_gain; 4381 cmd.ngroups = 1; 4382 cmd.isvalid = 1; 4383 DPRINTF(sc, IWN_DEBUG_CALIBRATE, 4384 "%s: setting initial differential gains\n", __func__); 4385 return iwn_cmd(sc, IWN_CMD_PHY_CALIB, &cmd, sizeof cmd, 1); 4386 } 4387 4388 static int 4389 iwn4965_set_gains(struct iwn_softc *sc) 4390 { 4391 struct iwn_calib_state *calib = &sc->calib; 4392 struct iwn_phy_calib_gain cmd; 4393 int i, delta, noise; 4394 4395 /* Get minimal noise among connected antennas. */ 4396 noise = INT_MAX; /* NB: There's at least one antenna. */ 4397 for (i = 0; i < 3; i++) 4398 if (sc->chainmask & (1 << i)) 4399 noise = MIN(calib->noise[i], noise); 4400 4401 memset(&cmd, 0, sizeof cmd); 4402 cmd.code = IWN4965_PHY_CALIB_DIFF_GAIN; 4403 /* Set differential gains for connected antennas. */ 4404 for (i = 0; i < 3; i++) { 4405 if (sc->chainmask & (1 << i)) { 4406 /* Compute attenuation (in unit of 1.5dB). */ 4407 delta = (noise - (int32_t)calib->noise[i]) / 30; 4408 /* NB: delta <= 0 */ 4409 /* Limit to [-4.5dB,0]. */ 4410 cmd.gain[i] = MIN(abs(delta), 3); 4411 if (delta < 0) 4412 cmd.gain[i] |= 1 << 2; /* sign bit */ 4413 } 4414 } 4415 DPRINTF(sc, IWN_DEBUG_CALIBRATE, 4416 "setting differential gains Ant A/B/C: %x/%x/%x (%x)\n", 4417 cmd.gain[0], cmd.gain[1], cmd.gain[2], sc->chainmask); 4418 return iwn_cmd(sc, IWN_CMD_PHY_CALIB, &cmd, sizeof cmd, 1); 4419 } 4420 4421 static int 4422 iwn5000_set_gains(struct iwn_softc *sc) 4423 { 4424 struct iwn_calib_state *calib = &sc->calib; 4425 struct iwn_phy_calib_gain cmd; 4426 int i, ant, div, delta; 4427 4428 /* We collected 20 beacons and !=6050 need a 1.5 factor. */ 4429 div = (sc->hw_type == IWN_HW_REV_TYPE_6050) ? 20 : 30; 4430 4431 memset(&cmd, 0, sizeof cmd); 4432 cmd.code = sc->noise_gain; 4433 cmd.ngroups = 1; 4434 cmd.isvalid = 1; 4435 /* Get first available RX antenna as referential. */ 4436 ant = IWN_LSB(sc->rxchainmask); 4437 /* Set differential gains for other antennas. */ 4438 for (i = ant + 1; i < 3; i++) { 4439 if (sc->chainmask & (1 << i)) { 4440 /* The delta is relative to antenna "ant". */ 4441 delta = ((int32_t)calib->noise[ant] - 4442 (int32_t)calib->noise[i]) / div; 4443 /* Limit to [-4.5dB,+4.5dB]. */ 4444 cmd.gain[i - 1] = MIN(abs(delta), 3); 4445 if (delta < 0) 4446 cmd.gain[i - 1] |= 1 << 2; /* sign bit */ 4447 } 4448 } 4449 DPRINTF(sc, IWN_DEBUG_CALIBRATE, 4450 "setting differential gains Ant B/C: %x/%x (%x)\n", 4451 cmd.gain[0], cmd.gain[1], sc->chainmask); 4452 return iwn_cmd(sc, IWN_CMD_PHY_CALIB, &cmd, sizeof cmd, 1); 4453 } 4454 4455 /* 4456 * Tune RF RX sensitivity based on the number of false alarms detected 4457 * during the last beacon period. 4458 */ 4459 static void 4460 iwn_tune_sensitivity(struct iwn_softc *sc, const struct iwn_rx_stats *stats) 4461 { 4462 #define inc(val, inc, max) \ 4463 if ((val) < (max)) { \ 4464 if ((val) < (max) - (inc)) \ 4465 (val) += (inc); \ 4466 else \ 4467 (val) = (max); \ 4468 needs_update = 1; \ 4469 } 4470 #define dec(val, dec, min) \ 4471 if ((val) > (min)) { \ 4472 if ((val) > (min) + (dec)) \ 4473 (val) -= (dec); \ 4474 else \ 4475 (val) = (min); \ 4476 needs_update = 1; \ 4477 } 4478 4479 const struct iwn_sensitivity_limits *limits = sc->limits; 4480 struct iwn_calib_state *calib = &sc->calib; 4481 uint32_t val, rxena, fa; 4482 uint32_t energy[3], energy_min; 4483 uint8_t noise[3], noise_ref; 4484 int i, needs_update = 0; 4485 4486 /* Check that we've been enabled long enough. */ 4487 if ((rxena = le32toh(stats->general.load)) == 0) 4488 return; 4489 4490 /* Compute number of false alarms since last call for OFDM. */ 4491 fa = le32toh(stats->ofdm.bad_plcp) - calib->bad_plcp_ofdm; 4492 fa += le32toh(stats->ofdm.fa) - calib->fa_ofdm; 4493 fa *= 200 * IEEE80211_DUR_TU; /* 200TU */ 4494 4495 /* Save counters values for next call. */ 4496 calib->bad_plcp_ofdm = le32toh(stats->ofdm.bad_plcp); 4497 calib->fa_ofdm = le32toh(stats->ofdm.fa); 4498 4499 if (fa > 50 * rxena) { 4500 /* High false alarm count, decrease sensitivity. */ 4501 DPRINTF(sc, IWN_DEBUG_CALIBRATE, 4502 "%s: OFDM high false alarm count: %u\n", __func__, fa); 4503 inc(calib->ofdm_x1, 1, limits->max_ofdm_x1); 4504 inc(calib->ofdm_mrc_x1, 1, limits->max_ofdm_mrc_x1); 4505 inc(calib->ofdm_x4, 1, limits->max_ofdm_x4); 4506 inc(calib->ofdm_mrc_x4, 1, limits->max_ofdm_mrc_x4); 4507 4508 } else if (fa < 5 * rxena) { 4509 /* Low false alarm count, increase sensitivity. */ 4510 DPRINTF(sc, IWN_DEBUG_CALIBRATE, 4511 "%s: OFDM low false alarm count: %u\n", __func__, fa); 4512 dec(calib->ofdm_x1, 1, limits->min_ofdm_x1); 4513 dec(calib->ofdm_mrc_x1, 1, limits->min_ofdm_mrc_x1); 4514 dec(calib->ofdm_x4, 1, limits->min_ofdm_x4); 4515 dec(calib->ofdm_mrc_x4, 1, limits->min_ofdm_mrc_x4); 4516 } 4517 4518 /* Compute maximum noise among 3 receivers. */ 4519 for (i = 0; i < 3; i++) 4520 noise[i] = (le32toh(stats->general.noise[i]) >> 8) & 0xff; 4521 val = MAX(noise[0], noise[1]); 4522 val = MAX(noise[2], val); 4523 /* Insert it into our samples table. */ 4524 calib->noise_samples[calib->cur_noise_sample] = val; 4525 calib->cur_noise_sample = (calib->cur_noise_sample + 1) % 20; 4526 4527 /* Compute maximum noise among last 20 samples. */ 4528 noise_ref = calib->noise_samples[0]; 4529 for (i = 1; i < 20; i++) 4530 noise_ref = MAX(noise_ref, calib->noise_samples[i]); 4531 4532 /* Compute maximum energy among 3 receivers. */ 4533 for (i = 0; i < 3; i++) 4534 energy[i] = le32toh(stats->general.energy[i]); 4535 val = MIN(energy[0], energy[1]); 4536 val = MIN(energy[2], val); 4537 /* Insert it into our samples table. */ 4538 calib->energy_samples[calib->cur_energy_sample] = val; 4539 calib->cur_energy_sample = (calib->cur_energy_sample + 1) % 10; 4540 4541 /* Compute minimum energy among last 10 samples. */ 4542 energy_min = calib->energy_samples[0]; 4543 for (i = 1; i < 10; i++) 4544 energy_min = MAX(energy_min, calib->energy_samples[i]); 4545 energy_min += 6; 4546 4547 /* Compute number of false alarms since last call for CCK. */ 4548 fa = le32toh(stats->cck.bad_plcp) - calib->bad_plcp_cck; 4549 fa += le32toh(stats->cck.fa) - calib->fa_cck; 4550 fa *= 200 * IEEE80211_DUR_TU; /* 200TU */ 4551 4552 /* Save counters values for next call. */ 4553 calib->bad_plcp_cck = le32toh(stats->cck.bad_plcp); 4554 calib->fa_cck = le32toh(stats->cck.fa); 4555 4556 if (fa > 50 * rxena) { 4557 /* High false alarm count, decrease sensitivity. */ 4558 DPRINTF(sc, IWN_DEBUG_CALIBRATE, 4559 "%s: CCK high false alarm count: %u\n", __func__, fa); 4560 calib->cck_state = IWN_CCK_STATE_HIFA; 4561 calib->low_fa = 0; 4562 4563 if (calib->cck_x4 > 160) { 4564 calib->noise_ref = noise_ref; 4565 if (calib->energy_cck > 2) 4566 dec(calib->energy_cck, 2, energy_min); 4567 } 4568 if (calib->cck_x4 < 160) { 4569 calib->cck_x4 = 161; 4570 needs_update = 1; 4571 } else 4572 inc(calib->cck_x4, 3, limits->max_cck_x4); 4573 4574 inc(calib->cck_mrc_x4, 3, limits->max_cck_mrc_x4); 4575 4576 } else if (fa < 5 * rxena) { 4577 /* Low false alarm count, increase sensitivity. */ 4578 DPRINTF(sc, IWN_DEBUG_CALIBRATE, 4579 "%s: CCK low false alarm count: %u\n", __func__, fa); 4580 calib->cck_state = IWN_CCK_STATE_LOFA; 4581 calib->low_fa++; 4582 4583 if (calib->cck_state != IWN_CCK_STATE_INIT && 4584 (((int32_t)calib->noise_ref - (int32_t)noise_ref) > 2 || 4585 calib->low_fa > 100)) { 4586 inc(calib->energy_cck, 2, limits->min_energy_cck); 4587 dec(calib->cck_x4, 3, limits->min_cck_x4); 4588 dec(calib->cck_mrc_x4, 3, limits->min_cck_mrc_x4); 4589 } 4590 } else { 4591 /* Not worth to increase or decrease sensitivity. */ 4592 DPRINTF(sc, IWN_DEBUG_CALIBRATE, 4593 "%s: CCK normal false alarm count: %u\n", __func__, fa); 4594 calib->low_fa = 0; 4595 calib->noise_ref = noise_ref; 4596 4597 if (calib->cck_state == IWN_CCK_STATE_HIFA) { 4598 /* Previous interval had many false alarms. */ 4599 dec(calib->energy_cck, 8, energy_min); 4600 } 4601 calib->cck_state = IWN_CCK_STATE_INIT; 4602 } 4603 4604 if (needs_update) 4605 (void)iwn_send_sensitivity(sc); 4606 #undef dec 4607 #undef inc 4608 } 4609 4610 static int 4611 iwn_send_sensitivity(struct iwn_softc *sc) 4612 { 4613 struct iwn_calib_state *calib = &sc->calib; 4614 struct iwn_enhanced_sensitivity_cmd cmd; 4615 int len; 4616 4617 memset(&cmd, 0, sizeof cmd); 4618 len = sizeof (struct iwn_sensitivity_cmd); 4619 cmd.which = IWN_SENSITIVITY_WORKTBL; 4620 /* OFDM modulation. */ 4621 cmd.corr_ofdm_x1 = htole16(calib->ofdm_x1); 4622 cmd.corr_ofdm_mrc_x1 = htole16(calib->ofdm_mrc_x1); 4623 cmd.corr_ofdm_x4 = htole16(calib->ofdm_x4); 4624 cmd.corr_ofdm_mrc_x4 = htole16(calib->ofdm_mrc_x4); 4625 cmd.energy_ofdm = htole16(sc->limits->energy_ofdm); 4626 cmd.energy_ofdm_th = htole16(62); 4627 /* CCK modulation. */ 4628 cmd.corr_cck_x4 = htole16(calib->cck_x4); 4629 cmd.corr_cck_mrc_x4 = htole16(calib->cck_mrc_x4); 4630 cmd.energy_cck = htole16(calib->energy_cck); 4631 /* Barker modulation: use default values. */ 4632 cmd.corr_barker = htole16(190); 4633 cmd.corr_barker_mrc = htole16(390); 4634 4635 DPRINTF(sc, IWN_DEBUG_CALIBRATE, 4636 "%s: set sensitivity %d/%d/%d/%d/%d/%d/%d\n", __func__, 4637 calib->ofdm_x1, calib->ofdm_mrc_x1, calib->ofdm_x4, 4638 calib->ofdm_mrc_x4, calib->cck_x4, 4639 calib->cck_mrc_x4, calib->energy_cck); 4640 4641 if (!(sc->sc_flags & IWN_FLAG_ENH_SENS)) 4642 goto send; 4643 /* Enhanced sensitivity settings. */ 4644 len = sizeof (struct iwn_enhanced_sensitivity_cmd); 4645 cmd.ofdm_det_slope_mrc = htole16(668); 4646 cmd.ofdm_det_icept_mrc = htole16(4); 4647 cmd.ofdm_det_slope = htole16(486); 4648 cmd.ofdm_det_icept = htole16(37); 4649 cmd.cck_det_slope_mrc = htole16(853); 4650 cmd.cck_det_icept_mrc = htole16(4); 4651 cmd.cck_det_slope = htole16(476); 4652 cmd.cck_det_icept = htole16(99); 4653 send: 4654 return iwn_cmd(sc, IWN_CMD_SET_SENSITIVITY, &cmd, len, 1); 4655 } 4656 4657 /* 4658 * Set STA mode power saving level (between 0 and 5). 4659 * Level 0 is CAM (Continuously Aware Mode), 5 is for maximum power saving. 4660 */ 4661 static int 4662 iwn_set_pslevel(struct iwn_softc *sc, int dtim, int level, int async) 4663 { 4664 struct iwn_pmgt_cmd cmd; 4665 const struct iwn_pmgt *pmgt; 4666 uint32_t max, skip_dtim; 4667 uint32_t reg; 4668 int i; 4669 4670 /* Select which PS parameters to use. */ 4671 if (dtim <= 2) 4672 pmgt = &iwn_pmgt[0][level]; 4673 else if (dtim <= 10) 4674 pmgt = &iwn_pmgt[1][level]; 4675 else 4676 pmgt = &iwn_pmgt[2][level]; 4677 4678 memset(&cmd, 0, sizeof cmd); 4679 if (level != 0) /* not CAM */ 4680 cmd.flags |= htole16(IWN_PS_ALLOW_SLEEP); 4681 if (level == 5) 4682 cmd.flags |= htole16(IWN_PS_FAST_PD); 4683 /* Retrieve PCIe Active State Power Management (ASPM). */ 4684 reg = pci_read_config(sc->sc_dev, sc->sc_cap_off + 0x10, 1); 4685 if (!(reg & 0x1)) /* L0s Entry disabled. */ 4686 cmd.flags |= htole16(IWN_PS_PCI_PMGT); 4687 cmd.rxtimeout = htole32(pmgt->rxtimeout * 1024); 4688 cmd.txtimeout = htole32(pmgt->txtimeout * 1024); 4689 4690 if (dtim == 0) { 4691 dtim = 1; 4692 skip_dtim = 0; 4693 } else 4694 skip_dtim = pmgt->skip_dtim; 4695 if (skip_dtim != 0) { 4696 cmd.flags |= htole16(IWN_PS_SLEEP_OVER_DTIM); 4697 max = pmgt->intval[4]; 4698 if (max == (uint32_t)-1) 4699 max = dtim * (skip_dtim + 1); 4700 else if (max > dtim) 4701 max = (max / dtim) * dtim; 4702 } else 4703 max = dtim; 4704 for (i = 0; i < 5; i++) 4705 cmd.intval[i] = htole32(MIN(max, pmgt->intval[i])); 4706 4707 DPRINTF(sc, IWN_DEBUG_RESET, "setting power saving level to %d\n", 4708 level); 4709 return iwn_cmd(sc, IWN_CMD_SET_POWER_MODE, &cmd, sizeof cmd, async); 4710 } 4711 4712 static int 4713 iwn_send_btcoex(struct iwn_softc *sc) 4714 { 4715 struct iwn_bluetooth cmd; 4716 4717 memset(&cmd, 0, sizeof cmd); 4718 cmd.flags = IWN_BT_COEX_CHAN_ANN | IWN_BT_COEX_BT_PRIO; 4719 cmd.lead_time = IWN_BT_LEAD_TIME_DEF; 4720 cmd.max_kill = IWN_BT_MAX_KILL_DEF; 4721 DPRINTF(sc, IWN_DEBUG_RESET, "%s: configuring bluetooth coexistence\n", 4722 __func__); 4723 return iwn_cmd(sc, IWN_CMD_BT_COEX, &cmd, sizeof(cmd), 0); 4724 } 4725 4726 static int 4727 iwn_send_advanced_btcoex(struct iwn_softc *sc) 4728 { 4729 static const uint32_t btcoex_3wire[12] = { 4730 0xaaaaaaaa, 0xaaaaaaaa, 0xaeaaaaaa, 0xaaaaaaaa, 4731 0xcc00ff28, 0x0000aaaa, 0xcc00aaaa, 0x0000aaaa, 4732 0xc0004000, 0x00004000, 0xf0005000, 0xf0005000, 4733 }; 4734 struct iwn6000_btcoex_config btconfig; 4735 struct iwn_btcoex_priotable btprio; 4736 struct iwn_btcoex_prot btprot; 4737 int error, i; 4738 4739 memset(&btconfig, 0, sizeof btconfig); 4740 btconfig.flags = 145; 4741 btconfig.max_kill = 5; 4742 btconfig.bt3_t7_timer = 1; 4743 btconfig.kill_ack = htole32(0xffff0000); 4744 btconfig.kill_cts = htole32(0xffff0000); 4745 btconfig.sample_time = 2; 4746 btconfig.bt3_t2_timer = 0xc; 4747 for (i = 0; i < 12; i++) 4748 btconfig.lookup_table[i] = htole32(btcoex_3wire[i]); 4749 btconfig.valid = htole16(0xff); 4750 btconfig.prio_boost = 0xf0; 4751 DPRINTF(sc, IWN_DEBUG_RESET, 4752 "%s: configuring advanced bluetooth coexistence\n", __func__); 4753 error = iwn_cmd(sc, IWN_CMD_BT_COEX, &btconfig, sizeof(btconfig), 1); 4754 if (error != 0) 4755 return error; 4756 4757 memset(&btprio, 0, sizeof btprio); 4758 btprio.calib_init1 = 0x6; 4759 btprio.calib_init2 = 0x7; 4760 btprio.calib_periodic_low1 = 0x2; 4761 btprio.calib_periodic_low2 = 0x3; 4762 btprio.calib_periodic_high1 = 0x4; 4763 btprio.calib_periodic_high2 = 0x5; 4764 btprio.dtim = 0x6; 4765 btprio.scan52 = 0x8; 4766 btprio.scan24 = 0xa; 4767 error = iwn_cmd(sc, IWN_CMD_BT_COEX_PRIOTABLE, &btprio, sizeof(btprio), 4768 1); 4769 if (error != 0) 4770 return error; 4771 4772 /* Force BT state machine change. */ 4773 memset(&btprot, 0, sizeof btprio); 4774 btprot.open = 1; 4775 btprot.type = 1; 4776 error = iwn_cmd(sc, IWN_CMD_BT_COEX_PROT, &btprot, sizeof(btprot), 1); 4777 if (error != 0) 4778 return error; 4779 btprot.open = 0; 4780 return iwn_cmd(sc, IWN_CMD_BT_COEX_PROT, &btprot, sizeof(btprot), 1); 4781 } 4782 4783 static int 4784 iwn_config(struct iwn_softc *sc) 4785 { 4786 struct iwn_ops *ops = &sc->ops; 4787 struct ifnet *ifp = sc->sc_ifp; 4788 struct ieee80211com *ic = ifp->if_l2com; 4789 uint32_t txmask; 4790 uint16_t rxchain; 4791 int error; 4792 4793 if (sc->hw_type == IWN_HW_REV_TYPE_6005) { 4794 /* Set radio temperature sensor offset. */ 4795 error = iwn5000_temp_offset_calib(sc); 4796 if (error != 0) { 4797 device_printf(sc->sc_dev, 4798 "%s: could not set temperature offset\n", __func__); 4799 return error; 4800 } 4801 } 4802 4803 /* Configure valid TX chains for >=5000 Series. */ 4804 if (sc->hw_type != IWN_HW_REV_TYPE_4965) { 4805 txmask = htole32(sc->txchainmask); 4806 DPRINTF(sc, IWN_DEBUG_RESET, 4807 "%s: configuring valid TX chains 0x%x\n", __func__, txmask); 4808 error = iwn_cmd(sc, IWN5000_CMD_TX_ANT_CONFIG, &txmask, 4809 sizeof txmask, 0); 4810 if (error != 0) { 4811 device_printf(sc->sc_dev, 4812 "%s: could not configure valid TX chains, " 4813 "error %d\n", __func__, error); 4814 return error; 4815 } 4816 } 4817 4818 /* Configure bluetooth coexistence. */ 4819 if (sc->sc_flags & IWN_FLAG_ADV_BTCOEX) 4820 error = iwn_send_advanced_btcoex(sc); 4821 else 4822 error = iwn_send_btcoex(sc); 4823 if (error != 0) { 4824 device_printf(sc->sc_dev, 4825 "%s: could not configure bluetooth coexistence, error %d\n", 4826 __func__, error); 4827 return error; 4828 } 4829 4830 /* Set mode, channel, RX filter and enable RX. */ 4831 memset(&sc->rxon, 0, sizeof (struct iwn_rxon)); 4832 IEEE80211_ADDR_COPY(sc->rxon.myaddr, IF_LLADDR(ifp)); 4833 IEEE80211_ADDR_COPY(sc->rxon.wlap, IF_LLADDR(ifp)); 4834 sc->rxon.chan = ieee80211_chan2ieee(ic, ic->ic_curchan); 4835 sc->rxon.flags = htole32(IWN_RXON_TSF | IWN_RXON_CTS_TO_SELF); 4836 if (IEEE80211_IS_CHAN_2GHZ(ic->ic_curchan)) 4837 sc->rxon.flags |= htole32(IWN_RXON_AUTO | IWN_RXON_24GHZ); 4838 switch (ic->ic_opmode) { 4839 case IEEE80211_M_STA: 4840 sc->rxon.mode = IWN_MODE_STA; 4841 sc->rxon.filter = htole32(IWN_FILTER_MULTICAST); 4842 break; 4843 case IEEE80211_M_MONITOR: 4844 sc->rxon.mode = IWN_MODE_MONITOR; 4845 sc->rxon.filter = htole32(IWN_FILTER_MULTICAST | 4846 IWN_FILTER_CTL | IWN_FILTER_PROMISC); 4847 break; 4848 default: 4849 /* Should not get there. */ 4850 break; 4851 } 4852 sc->rxon.cck_mask = 0x0f; /* not yet negotiated */ 4853 sc->rxon.ofdm_mask = 0xff; /* not yet negotiated */ 4854 sc->rxon.ht_single_mask = 0xff; 4855 sc->rxon.ht_dual_mask = 0xff; 4856 sc->rxon.ht_triple_mask = 0xff; 4857 rxchain = 4858 IWN_RXCHAIN_VALID(sc->rxchainmask) | 4859 IWN_RXCHAIN_MIMO_COUNT(2) | 4860 IWN_RXCHAIN_IDLE_COUNT(2); 4861 sc->rxon.rxchain = htole16(rxchain); 4862 DPRINTF(sc, IWN_DEBUG_RESET, "%s: setting configuration\n", __func__); 4863 error = iwn_cmd(sc, IWN_CMD_RXON, &sc->rxon, sc->rxonsz, 0); 4864 if (error != 0) { 4865 device_printf(sc->sc_dev, "%s: RXON command failed\n", 4866 __func__); 4867 return error; 4868 } 4869 4870 if ((error = iwn_add_broadcast_node(sc, 0)) != 0) { 4871 device_printf(sc->sc_dev, "%s: could not add broadcast node\n", 4872 __func__); 4873 return error; 4874 } 4875 4876 /* Configuration has changed, set TX power accordingly. */ 4877 if ((error = ops->set_txpower(sc, ic->ic_curchan, 0)) != 0) { 4878 device_printf(sc->sc_dev, "%s: could not set TX power\n", 4879 __func__); 4880 return error; 4881 } 4882 4883 if ((error = iwn_set_critical_temp(sc)) != 0) { 4884 device_printf(sc->sc_dev, 4885 "%s: could not set critical temperature\n", __func__); 4886 return error; 4887 } 4888 4889 /* Set power saving level to CAM during initialization. */ 4890 if ((error = iwn_set_pslevel(sc, 0, 0, 0)) != 0) { 4891 device_printf(sc->sc_dev, 4892 "%s: could not set power saving level\n", __func__); 4893 return error; 4894 } 4895 return 0; 4896 } 4897 4898 /* 4899 * Add an ssid element to a frame. 4900 */ 4901 static uint8_t * 4902 ieee80211_add_ssid(uint8_t *frm, const uint8_t *ssid, u_int len) 4903 { 4904 *frm++ = IEEE80211_ELEMID_SSID; 4905 *frm++ = len; 4906 memcpy(frm, ssid, len); 4907 return frm + len; 4908 } 4909 4910 static int 4911 iwn_scan(struct iwn_softc *sc) 4912 { 4913 struct ifnet *ifp = sc->sc_ifp; 4914 struct ieee80211com *ic = ifp->if_l2com; 4915 struct ieee80211_scan_state *ss = ic->ic_scan; /*XXX*/ 4916 struct iwn_scan_hdr *hdr; 4917 struct iwn_cmd_data *tx; 4918 struct iwn_scan_essid *essid; 4919 struct iwn_scan_chan *chan; 4920 struct ieee80211_frame *wh; 4921 struct ieee80211_rateset *rs; 4922 struct ieee80211_channel *c; 4923 uint8_t *buf, *frm; 4924 uint16_t rxchain; 4925 uint8_t txant; 4926 int buflen, error; 4927 4928 buf = malloc(IWN_SCAN_MAXSZ, M_DEVBUF, M_NOWAIT | M_ZERO); 4929 if (buf == NULL) { 4930 device_printf(sc->sc_dev, 4931 "%s: could not allocate buffer for scan command\n", 4932 __func__); 4933 return ENOMEM; 4934 } 4935 hdr = (struct iwn_scan_hdr *)buf; 4936 /* 4937 * Move to the next channel if no frames are received within 10ms 4938 * after sending the probe request. 4939 */ 4940 hdr->quiet_time = htole16(10); /* timeout in milliseconds */ 4941 hdr->quiet_threshold = htole16(1); /* min # of packets */ 4942 4943 /* Select antennas for scanning. */ 4944 rxchain = 4945 IWN_RXCHAIN_VALID(sc->rxchainmask) | 4946 IWN_RXCHAIN_FORCE_MIMO_SEL(sc->rxchainmask) | 4947 IWN_RXCHAIN_DRIVER_FORCE; 4948 if (IEEE80211_IS_CHAN_A(ic->ic_curchan) && 4949 sc->hw_type == IWN_HW_REV_TYPE_4965) { 4950 /* Ant A must be avoided in 5GHz because of an HW bug. */ 4951 rxchain |= IWN_RXCHAIN_FORCE_SEL(IWN_ANT_BC); 4952 } else /* Use all available RX antennas. */ 4953 rxchain |= IWN_RXCHAIN_FORCE_SEL(sc->rxchainmask); 4954 hdr->rxchain = htole16(rxchain); 4955 hdr->filter = htole32(IWN_FILTER_MULTICAST | IWN_FILTER_BEACON); 4956 4957 tx = (struct iwn_cmd_data *)(hdr + 1); 4958 tx->flags = htole32(IWN_TX_AUTO_SEQ); 4959 tx->id = sc->broadcast_id; 4960 tx->lifetime = htole32(IWN_LIFETIME_INFINITE); 4961 4962 if (IEEE80211_IS_CHAN_A(ic->ic_curchan)) { 4963 /* Send probe requests at 6Mbps. */ 4964 tx->plcp = iwn_rates[IWN_RIDX_OFDM6].plcp; 4965 rs = &ic->ic_sup_rates[IEEE80211_MODE_11A]; 4966 } else { 4967 hdr->flags = htole32(IWN_RXON_24GHZ | IWN_RXON_AUTO); 4968 /* Send probe requests at 1Mbps. */ 4969 tx->plcp = iwn_rates[IWN_RIDX_CCK1].plcp; 4970 tx->rflags = IWN_RFLAG_CCK; 4971 rs = &ic->ic_sup_rates[IEEE80211_MODE_11G]; 4972 } 4973 /* Use the first valid TX antenna. */ 4974 txant = IWN_LSB(sc->txchainmask); 4975 tx->rflags |= IWN_RFLAG_ANT(txant); 4976 4977 essid = (struct iwn_scan_essid *)(tx + 1); 4978 if (ss->ss_ssid[0].len != 0) { 4979 essid[0].id = IEEE80211_ELEMID_SSID; 4980 essid[0].len = ss->ss_ssid[0].len; 4981 memcpy(essid[0].data, ss->ss_ssid[0].ssid, ss->ss_ssid[0].len); 4982 } 4983 /* 4984 * Build a probe request frame. Most of the following code is a 4985 * copy & paste of what is done in net80211. 4986 */ 4987 wh = (struct ieee80211_frame *)(essid + 20); 4988 wh->i_fc[0] = IEEE80211_FC0_VERSION_0 | IEEE80211_FC0_TYPE_MGT | 4989 IEEE80211_FC0_SUBTYPE_PROBE_REQ; 4990 wh->i_fc[1] = IEEE80211_FC1_DIR_NODS; 4991 IEEE80211_ADDR_COPY(wh->i_addr1, ifp->if_broadcastaddr); 4992 IEEE80211_ADDR_COPY(wh->i_addr2, IF_LLADDR(ifp)); 4993 IEEE80211_ADDR_COPY(wh->i_addr3, ifp->if_broadcastaddr); 4994 *(uint16_t *)&wh->i_dur[0] = 0; /* filled by HW */ 4995 *(uint16_t *)&wh->i_seq[0] = 0; /* filled by HW */ 4996 4997 frm = (uint8_t *)(wh + 1); 4998 frm = ieee80211_add_ssid(frm, NULL, 0); 4999 frm = ieee80211_add_rates(frm, rs); 5000 if (rs->rs_nrates > IEEE80211_RATE_SIZE) 5001 frm = ieee80211_add_xrates(frm, rs); 5002 #if 0 /* HT */ 5003 if (ic->ic_flags & IEEE80211_F_HTON) 5004 frm = ieee80211_add_htcaps(frm, ic); 5005 #endif 5006 5007 /* Set length of probe request. */ 5008 tx->len = htole16(frm - (uint8_t *)wh); 5009 5010 c = ic->ic_curchan; 5011 chan = (struct iwn_scan_chan *)frm; 5012 chan->chan = htole16(ieee80211_chan2ieee(ic, c)); 5013 chan->flags = 0; 5014 if (ss->ss_nssid > 0) 5015 chan->flags |= htole32(IWN_CHAN_NPBREQS(1)); 5016 chan->dsp_gain = 0x6e; 5017 if (IEEE80211_IS_CHAN_5GHZ(c) && 5018 !(c->ic_flags & IEEE80211_CHAN_PASSIVE)) { 5019 chan->rf_gain = 0x3b; 5020 chan->active = htole16(24); 5021 chan->passive = htole16(110); 5022 chan->flags |= htole32(IWN_CHAN_ACTIVE); 5023 } else if (IEEE80211_IS_CHAN_5GHZ(c)) { 5024 chan->rf_gain = 0x3b; 5025 chan->active = htole16(24); 5026 if (sc->rxon.associd) 5027 chan->passive = htole16(78); 5028 else 5029 chan->passive = htole16(110); 5030 hdr->crc_threshold = 0xffff; 5031 } else if (!(c->ic_flags & IEEE80211_CHAN_PASSIVE)) { 5032 chan->rf_gain = 0x28; 5033 chan->active = htole16(36); 5034 chan->passive = htole16(120); 5035 chan->flags |= htole32(IWN_CHAN_ACTIVE); 5036 } else { 5037 chan->rf_gain = 0x28; 5038 chan->active = htole16(36); 5039 if (sc->rxon.associd) 5040 chan->passive = htole16(88); 5041 else 5042 chan->passive = htole16(120); 5043 hdr->crc_threshold = 0xffff; 5044 } 5045 5046 DPRINTF(sc, IWN_DEBUG_STATE, 5047 "%s: chan %u flags 0x%x rf_gain 0x%x " 5048 "dsp_gain 0x%x active 0x%x passive 0x%x\n", __func__, 5049 chan->chan, chan->flags, chan->rf_gain, chan->dsp_gain, 5050 chan->active, chan->passive); 5051 5052 hdr->nchan++; 5053 chan++; 5054 buflen = (uint8_t *)chan - buf; 5055 hdr->len = htole16(buflen); 5056 5057 DPRINTF(sc, IWN_DEBUG_STATE, "sending scan command nchan=%d\n", 5058 hdr->nchan); 5059 error = iwn_cmd(sc, IWN_CMD_SCAN, buf, buflen, 1); 5060 free(buf, M_DEVBUF); 5061 return error; 5062 } 5063 5064 static int 5065 iwn_auth(struct iwn_softc *sc, struct ieee80211vap *vap) 5066 { 5067 struct iwn_ops *ops = &sc->ops; 5068 struct ifnet *ifp = sc->sc_ifp; 5069 struct ieee80211com *ic = ifp->if_l2com; 5070 struct ieee80211_node *ni = vap->iv_bss; 5071 int error; 5072 5073 /* Update adapter configuration. */ 5074 IEEE80211_ADDR_COPY(sc->rxon.bssid, ni->ni_bssid); 5075 sc->rxon.chan = ieee80211_chan2ieee(ic, ni->ni_chan); 5076 sc->rxon.flags = htole32(IWN_RXON_TSF | IWN_RXON_CTS_TO_SELF); 5077 if (IEEE80211_IS_CHAN_2GHZ(ni->ni_chan)) 5078 sc->rxon.flags |= htole32(IWN_RXON_AUTO | IWN_RXON_24GHZ); 5079 if (ic->ic_flags & IEEE80211_F_SHSLOT) 5080 sc->rxon.flags |= htole32(IWN_RXON_SHSLOT); 5081 if (ic->ic_flags & IEEE80211_F_SHPREAMBLE) 5082 sc->rxon.flags |= htole32(IWN_RXON_SHPREAMBLE); 5083 if (IEEE80211_IS_CHAN_A(ni->ni_chan)) { 5084 sc->rxon.cck_mask = 0; 5085 sc->rxon.ofdm_mask = 0x15; 5086 } else if (IEEE80211_IS_CHAN_B(ni->ni_chan)) { 5087 sc->rxon.cck_mask = 0x03; 5088 sc->rxon.ofdm_mask = 0; 5089 } else { 5090 /* Assume 802.11b/g. */ 5091 sc->rxon.cck_mask = 0x0f; 5092 sc->rxon.ofdm_mask = 0x15; 5093 } 5094 DPRINTF(sc, IWN_DEBUG_STATE, "rxon chan %d flags %x cck %x ofdm %x\n", 5095 sc->rxon.chan, sc->rxon.flags, sc->rxon.cck_mask, 5096 sc->rxon.ofdm_mask); 5097 error = iwn_cmd(sc, IWN_CMD_RXON, &sc->rxon, sc->rxonsz, 1); 5098 if (error != 0) { 5099 device_printf(sc->sc_dev, "%s: RXON command failed, error %d\n", 5100 __func__, error); 5101 return error; 5102 } 5103 5104 /* Configuration has changed, set TX power accordingly. */ 5105 if ((error = ops->set_txpower(sc, ni->ni_chan, 1)) != 0) { 5106 device_printf(sc->sc_dev, 5107 "%s: could not set TX power, error %d\n", __func__, error); 5108 return error; 5109 } 5110 /* 5111 * Reconfiguring RXON clears the firmware nodes table so we must 5112 * add the broadcast node again. 5113 */ 5114 if ((error = iwn_add_broadcast_node(sc, 1)) != 0) { 5115 device_printf(sc->sc_dev, 5116 "%s: could not add broadcast node, error %d\n", __func__, 5117 error); 5118 return error; 5119 } 5120 return 0; 5121 } 5122 5123 static int 5124 iwn_run(struct iwn_softc *sc, struct ieee80211vap *vap) 5125 { 5126 #define MS(v,x) (((v) & x) >> x##_S) 5127 struct iwn_ops *ops = &sc->ops; 5128 struct ifnet *ifp = sc->sc_ifp; 5129 struct ieee80211com *ic = ifp->if_l2com; 5130 struct ieee80211_node *ni = vap->iv_bss; 5131 struct iwn_node_info node; 5132 int error; 5133 5134 if (ic->ic_opmode == IEEE80211_M_MONITOR) { 5135 /* Link LED blinks while monitoring. */ 5136 iwn_set_led(sc, IWN_LED_LINK, 5, 5); 5137 return 0; 5138 } 5139 if ((error = iwn_set_timing(sc, ni)) != 0) { 5140 device_printf(sc->sc_dev, 5141 "%s: could not set timing, error %d\n", __func__, error); 5142 return error; 5143 } 5144 5145 /* Update adapter configuration. */ 5146 IEEE80211_ADDR_COPY(sc->rxon.bssid, ni->ni_bssid); 5147 sc->rxon.associd = htole16(IEEE80211_AID(ni->ni_associd)); 5148 sc->rxon.chan = ieee80211_chan2ieee(ic, ni->ni_chan); 5149 sc->rxon.flags = htole32(IWN_RXON_TSF | IWN_RXON_CTS_TO_SELF); 5150 if (IEEE80211_IS_CHAN_2GHZ(ni->ni_chan)) 5151 sc->rxon.flags |= htole32(IWN_RXON_AUTO | IWN_RXON_24GHZ); 5152 if (ic->ic_flags & IEEE80211_F_SHSLOT) 5153 sc->rxon.flags |= htole32(IWN_RXON_SHSLOT); 5154 if (ic->ic_flags & IEEE80211_F_SHPREAMBLE) 5155 sc->rxon.flags |= htole32(IWN_RXON_SHPREAMBLE); 5156 if (IEEE80211_IS_CHAN_A(ni->ni_chan)) { 5157 sc->rxon.cck_mask = 0; 5158 sc->rxon.ofdm_mask = 0x15; 5159 } else if (IEEE80211_IS_CHAN_B(ni->ni_chan)) { 5160 sc->rxon.cck_mask = 0x03; 5161 sc->rxon.ofdm_mask = 0; 5162 } else { 5163 /* Assume 802.11b/g. */ 5164 sc->rxon.cck_mask = 0x0f; 5165 sc->rxon.ofdm_mask = 0x15; 5166 } 5167 #if 0 /* HT */ 5168 if (IEEE80211_IS_CHAN_HT(ni->ni_chan)) { 5169 sc->rxon.flags &= ~htole32(IWN_RXON_HT); 5170 if (IEEE80211_IS_CHAN_HT40U(ni->ni_chan)) 5171 sc->rxon.flags |= htole32(IWN_RXON_HT40U); 5172 else if (IEEE80211_IS_CHAN_HT40D(ni->ni_chan)) 5173 sc->rxon.flags |= htole32(IWN_RXON_HT40D); 5174 else 5175 sc->rxon.flags |= htole32(IWN_RXON_HT20); 5176 sc->rxon.rxchain = htole16( 5177 IWN_RXCHAIN_VALID(3) 5178 | IWN_RXCHAIN_MIMO_COUNT(3) 5179 | IWN_RXCHAIN_IDLE_COUNT(1) 5180 | IWN_RXCHAIN_MIMO_FORCE); 5181 5182 maxrxampdu = MS(ni->ni_htparam, IEEE80211_HTCAP_MAXRXAMPDU); 5183 ampdudensity = MS(ni->ni_htparam, IEEE80211_HTCAP_MPDUDENSITY); 5184 } else 5185 maxrxampdu = ampdudensity = 0; 5186 #endif 5187 sc->rxon.filter |= htole32(IWN_FILTER_BSS); 5188 DPRINTF(sc, IWN_DEBUG_STATE, "rxon chan %d flags %x\n", 5189 sc->rxon.chan, sc->rxon.flags); 5190 error = iwn_cmd(sc, IWN_CMD_RXON, &sc->rxon, sc->rxonsz, 1); 5191 if (error != 0) { 5192 device_printf(sc->sc_dev, 5193 "%s: could not update configuration, error %d\n", __func__, 5194 error); 5195 return error; 5196 } 5197 5198 /* Configuration has changed, set TX power accordingly. */ 5199 if ((error = ops->set_txpower(sc, ni->ni_chan, 1)) != 0) { 5200 device_printf(sc->sc_dev, 5201 "%s: could not set TX power, error %d\n", __func__, error); 5202 return error; 5203 } 5204 5205 /* Fake a join to initialize the TX rate. */ 5206 ((struct iwn_node *)ni)->id = IWN_ID_BSS; 5207 iwn_newassoc(ni, 1); 5208 5209 /* Add BSS node. */ 5210 memset(&node, 0, sizeof node); 5211 IEEE80211_ADDR_COPY(node.macaddr, ni->ni_macaddr); 5212 node.id = IWN_ID_BSS; 5213 #ifdef notyet 5214 node.htflags = htole32(IWN_AMDPU_SIZE_FACTOR(3) | 5215 IWN_AMDPU_DENSITY(5)); /* 2us */ 5216 #endif 5217 DPRINTF(sc, IWN_DEBUG_STATE, "%s: adding BSS node\n", __func__); 5218 error = ops->add_node(sc, &node, 1); 5219 if (error != 0) { 5220 device_printf(sc->sc_dev, 5221 "%s: could not add BSS node, error %d\n", __func__, error); 5222 return error; 5223 } 5224 DPRINTF(sc, IWN_DEBUG_STATE, "%s: setting link quality for node %d\n", 5225 __func__, node.id); 5226 if ((error = iwn_set_link_quality(sc, ni)) != 0) { 5227 device_printf(sc->sc_dev, 5228 "%s: could not setup link quality for node %d, error %d\n", 5229 __func__, node.id, error); 5230 return error; 5231 } 5232 5233 if ((error = iwn_init_sensitivity(sc)) != 0) { 5234 device_printf(sc->sc_dev, 5235 "%s: could not set sensitivity, error %d\n", __func__, 5236 error); 5237 return error; 5238 } 5239 /* Start periodic calibration timer. */ 5240 sc->calib.state = IWN_CALIB_STATE_ASSOC; 5241 sc->calib_cnt = 0; 5242 callout_reset(&sc->calib_to, msecs_to_ticks(500), iwn_calib_timeout, 5243 sc); 5244 5245 /* Link LED always on while associated. */ 5246 iwn_set_led(sc, IWN_LED_LINK, 0, 1); 5247 return 0; 5248 #undef MS 5249 } 5250 5251 #if 0 /* HT */ 5252 /* 5253 * This function is called by upper layer when an ADDBA request is received 5254 * from another STA and before the ADDBA response is sent. 5255 */ 5256 static int 5257 iwn_ampdu_rx_start(struct ieee80211com *ic, struct ieee80211_node *ni, 5258 uint8_t tid) 5259 { 5260 struct ieee80211_rx_ba *ba = &ni->ni_rx_ba[tid]; 5261 struct iwn_softc *sc = ic->ic_softc; 5262 struct iwn_ops *ops = &sc->ops; 5263 struct iwn_node *wn = (void *)ni; 5264 struct iwn_node_info node; 5265 5266 memset(&node, 0, sizeof node); 5267 node.id = wn->id; 5268 node.control = IWN_NODE_UPDATE; 5269 node.flags = IWN_FLAG_SET_ADDBA; 5270 node.addba_tid = tid; 5271 node.addba_ssn = htole16(ba->ba_winstart); 5272 DPRINTF(sc, IWN_DEBUG_RECV, "ADDBA RA=%d TID=%d SSN=%d\n", 5273 wn->id, tid, ba->ba_winstart); 5274 return ops->add_node(sc, &node, 1); 5275 } 5276 5277 /* 5278 * This function is called by upper layer on teardown of an HT-immediate 5279 * Block Ack agreement (eg. uppon receipt of a DELBA frame). 5280 */ 5281 static void 5282 iwn_ampdu_rx_stop(struct ieee80211com *ic, struct ieee80211_node *ni, 5283 uint8_t tid) 5284 { 5285 struct iwn_softc *sc = ic->ic_softc; 5286 struct iwn_ops *ops = &sc->ops; 5287 struct iwn_node *wn = (void *)ni; 5288 struct iwn_node_info node; 5289 5290 memset(&node, 0, sizeof node); 5291 node.id = wn->id; 5292 node.control = IWN_NODE_UPDATE; 5293 node.flags = IWN_FLAG_SET_DELBA; 5294 node.delba_tid = tid; 5295 DPRINTF(sc, IWN_DEBUG_RECV, "DELBA RA=%d TID=%d\n", wn->id, tid); 5296 (void)ops->add_node(sc, &node, 1); 5297 } 5298 5299 /* 5300 * This function is called by upper layer when an ADDBA response is received 5301 * from another STA. 5302 */ 5303 static int 5304 iwn_ampdu_tx_start(struct ieee80211com *ic, struct ieee80211_node *ni, 5305 uint8_t tid) 5306 { 5307 struct ieee80211_tx_ba *ba = &ni->ni_tx_ba[tid]; 5308 struct iwn_softc *sc = ic->ic_softc; 5309 struct iwn_ops *ops = &sc->ops; 5310 struct iwn_node *wn = (void *)ni; 5311 struct iwn_node_info node; 5312 int error; 5313 5314 /* Enable TX for the specified RA/TID. */ 5315 wn->disable_tid &= ~(1 << tid); 5316 memset(&node, 0, sizeof node); 5317 node.id = wn->id; 5318 node.control = IWN_NODE_UPDATE; 5319 node.flags = IWN_FLAG_SET_DISABLE_TID; 5320 node.disable_tid = htole16(wn->disable_tid); 5321 error = ops->add_node(sc, &node, 1); 5322 if (error != 0) 5323 return error; 5324 5325 if ((error = iwn_nic_lock(sc)) != 0) 5326 return error; 5327 ops->ampdu_tx_start(sc, ni, tid, ba->ba_winstart); 5328 iwn_nic_unlock(sc); 5329 return 0; 5330 } 5331 5332 static void 5333 iwn_ampdu_tx_stop(struct ieee80211com *ic, struct ieee80211_node *ni, 5334 uint8_t tid) 5335 { 5336 struct ieee80211_tx_ba *ba = &ni->ni_tx_ba[tid]; 5337 struct iwn_softc *sc = ic->ic_softc; 5338 struct iwn_ops *ops = &sc->ops; 5339 5340 if (iwn_nic_lock(sc) != 0) 5341 return; 5342 ops->ampdu_tx_stop(sc, tid, ba->ba_winstart); 5343 iwn_nic_unlock(sc); 5344 } 5345 5346 static void 5347 iwn4965_ampdu_tx_start(struct iwn_softc *sc, struct ieee80211_node *ni, 5348 uint8_t tid, uint16_t ssn) 5349 { 5350 struct iwn_node *wn = (void *)ni; 5351 int qid = 7 + tid; 5352 5353 /* Stop TX scheduler while we're changing its configuration. */ 5354 iwn_prph_write(sc, IWN4965_SCHED_QUEUE_STATUS(qid), 5355 IWN4965_TXQ_STATUS_CHGACT); 5356 5357 /* Assign RA/TID translation to the queue. */ 5358 iwn_mem_write_2(sc, sc->sched_base + IWN4965_SCHED_TRANS_TBL(qid), 5359 wn->id << 4 | tid); 5360 5361 /* Enable chain-building mode for the queue. */ 5362 iwn_prph_setbits(sc, IWN4965_SCHED_QCHAIN_SEL, 1 << qid); 5363 5364 /* Set starting sequence number from the ADDBA request. */ 5365 IWN_WRITE(sc, IWN_HBUS_TARG_WRPTR, qid << 8 | (ssn & 0xff)); 5366 iwn_prph_write(sc, IWN4965_SCHED_QUEUE_RDPTR(qid), ssn); 5367 5368 /* Set scheduler window size. */ 5369 iwn_mem_write(sc, sc->sched_base + IWN4965_SCHED_QUEUE_OFFSET(qid), 5370 IWN_SCHED_WINSZ); 5371 /* Set scheduler frame limit. */ 5372 iwn_mem_write(sc, sc->sched_base + IWN4965_SCHED_QUEUE_OFFSET(qid) + 4, 5373 IWN_SCHED_LIMIT << 16); 5374 5375 /* Enable interrupts for the queue. */ 5376 iwn_prph_setbits(sc, IWN4965_SCHED_INTR_MASK, 1 << qid); 5377 5378 /* Mark the queue as active. */ 5379 iwn_prph_write(sc, IWN4965_SCHED_QUEUE_STATUS(qid), 5380 IWN4965_TXQ_STATUS_ACTIVE | IWN4965_TXQ_STATUS_AGGR_ENA | 5381 iwn_tid2fifo[tid] << 1); 5382 } 5383 5384 static void 5385 iwn4965_ampdu_tx_stop(struct iwn_softc *sc, uint8_t tid, uint16_t ssn) 5386 { 5387 int qid = 7 + tid; 5388 5389 /* Stop TX scheduler while we're changing its configuration. */ 5390 iwn_prph_write(sc, IWN4965_SCHED_QUEUE_STATUS(qid), 5391 IWN4965_TXQ_STATUS_CHGACT); 5392 5393 /* Set starting sequence number from the ADDBA request. */ 5394 IWN_WRITE(sc, IWN_HBUS_TARG_WRPTR, qid << 8 | (ssn & 0xff)); 5395 iwn_prph_write(sc, IWN4965_SCHED_QUEUE_RDPTR(qid), ssn); 5396 5397 /* Disable interrupts for the queue. */ 5398 iwn_prph_clrbits(sc, IWN4965_SCHED_INTR_MASK, 1 << qid); 5399 5400 /* Mark the queue as inactive. */ 5401 iwn_prph_write(sc, IWN4965_SCHED_QUEUE_STATUS(qid), 5402 IWN4965_TXQ_STATUS_INACTIVE | iwn_tid2fifo[tid] << 1); 5403 } 5404 5405 static void 5406 iwn5000_ampdu_tx_start(struct iwn_softc *sc, struct ieee80211_node *ni, 5407 uint8_t tid, uint16_t ssn) 5408 { 5409 struct iwn_node *wn = (void *)ni; 5410 int qid = 10 + tid; 5411 5412 /* Stop TX scheduler while we're changing its configuration. */ 5413 iwn_prph_write(sc, IWN5000_SCHED_QUEUE_STATUS(qid), 5414 IWN5000_TXQ_STATUS_CHGACT); 5415 5416 /* Assign RA/TID translation to the queue. */ 5417 iwn_mem_write_2(sc, sc->sched_base + IWN5000_SCHED_TRANS_TBL(qid), 5418 wn->id << 4 | tid); 5419 5420 /* Enable chain-building mode for the queue. */ 5421 iwn_prph_setbits(sc, IWN5000_SCHED_QCHAIN_SEL, 1 << qid); 5422 5423 /* Enable aggregation for the queue. */ 5424 iwn_prph_setbits(sc, IWN5000_SCHED_AGGR_SEL, 1 << qid); 5425 5426 /* Set starting sequence number from the ADDBA request. */ 5427 IWN_WRITE(sc, IWN_HBUS_TARG_WRPTR, qid << 8 | (ssn & 0xff)); 5428 iwn_prph_write(sc, IWN5000_SCHED_QUEUE_RDPTR(qid), ssn); 5429 5430 /* Set scheduler window size and frame limit. */ 5431 iwn_mem_write(sc, sc->sched_base + IWN5000_SCHED_QUEUE_OFFSET(qid) + 4, 5432 IWN_SCHED_LIMIT << 16 | IWN_SCHED_WINSZ); 5433 5434 /* Enable interrupts for the queue. */ 5435 iwn_prph_setbits(sc, IWN5000_SCHED_INTR_MASK, 1 << qid); 5436 5437 /* Mark the queue as active. */ 5438 iwn_prph_write(sc, IWN5000_SCHED_QUEUE_STATUS(qid), 5439 IWN5000_TXQ_STATUS_ACTIVE | iwn_tid2fifo[tid]); 5440 } 5441 5442 static void 5443 iwn5000_ampdu_tx_stop(struct iwn_softc *sc, uint8_t tid, uint16_t ssn) 5444 { 5445 int qid = 10 + tid; 5446 5447 /* Stop TX scheduler while we're changing its configuration. */ 5448 iwn_prph_write(sc, IWN5000_SCHED_QUEUE_STATUS(qid), 5449 IWN5000_TXQ_STATUS_CHGACT); 5450 5451 /* Disable aggregation for the queue. */ 5452 iwn_prph_clrbits(sc, IWN5000_SCHED_AGGR_SEL, 1 << qid); 5453 5454 /* Set starting sequence number from the ADDBA request. */ 5455 IWN_WRITE(sc, IWN_HBUS_TARG_WRPTR, qid << 8 | (ssn & 0xff)); 5456 iwn_prph_write(sc, IWN5000_SCHED_QUEUE_RDPTR(qid), ssn); 5457 5458 /* Disable interrupts for the queue. */ 5459 iwn_prph_clrbits(sc, IWN5000_SCHED_INTR_MASK, 1 << qid); 5460 5461 /* Mark the queue as inactive. */ 5462 iwn_prph_write(sc, IWN5000_SCHED_QUEUE_STATUS(qid), 5463 IWN5000_TXQ_STATUS_INACTIVE | iwn_tid2fifo[tid]); 5464 } 5465 #endif 5466 5467 /* 5468 * Query calibration tables from the initialization firmware. We do this 5469 * only once at first boot. Called from a process context. 5470 */ 5471 static int 5472 iwn5000_query_calibration(struct iwn_softc *sc) 5473 { 5474 struct iwn5000_calib_config cmd; 5475 int error; 5476 5477 memset(&cmd, 0, sizeof cmd); 5478 cmd.ucode.once.enable = 0xffffffff; 5479 cmd.ucode.once.start = 0xffffffff; 5480 cmd.ucode.once.send = 0xffffffff; 5481 cmd.ucode.flags = 0xffffffff; 5482 DPRINTF(sc, IWN_DEBUG_CALIBRATE, "%s: sending calibration query\n", 5483 __func__); 5484 error = iwn_cmd(sc, IWN5000_CMD_CALIB_CONFIG, &cmd, sizeof cmd, 0); 5485 if (error != 0) 5486 return error; 5487 5488 /* Wait at most two seconds for calibration to complete. */ 5489 if (!(sc->sc_flags & IWN_FLAG_CALIB_DONE)) 5490 error = msleep(sc, &sc->sc_mtx, PCATCH, "iwncal", 2 * hz); 5491 return error; 5492 } 5493 5494 /* 5495 * Send calibration results to the runtime firmware. These results were 5496 * obtained on first boot from the initialization firmware. 5497 */ 5498 static int 5499 iwn5000_send_calibration(struct iwn_softc *sc) 5500 { 5501 int idx, error; 5502 5503 for (idx = 0; idx < 5; idx++) { 5504 if (sc->calibcmd[idx].buf == NULL) 5505 continue; /* No results available. */ 5506 DPRINTF(sc, IWN_DEBUG_CALIBRATE, 5507 "send calibration result idx=%d len=%d\n", idx, 5508 sc->calibcmd[idx].len); 5509 error = iwn_cmd(sc, IWN_CMD_PHY_CALIB, sc->calibcmd[idx].buf, 5510 sc->calibcmd[idx].len, 0); 5511 if (error != 0) { 5512 device_printf(sc->sc_dev, 5513 "%s: could not send calibration result, error %d\n", 5514 __func__, error); 5515 return error; 5516 } 5517 } 5518 return 0; 5519 } 5520 5521 static int 5522 iwn5000_send_wimax_coex(struct iwn_softc *sc) 5523 { 5524 struct iwn5000_wimax_coex wimax; 5525 5526 #ifdef notyet 5527 if (sc->hw_type == IWN_HW_REV_TYPE_6050) { 5528 /* Enable WiMAX coexistence for combo adapters. */ 5529 wimax.flags = 5530 IWN_WIMAX_COEX_ASSOC_WA_UNMASK | 5531 IWN_WIMAX_COEX_UNASSOC_WA_UNMASK | 5532 IWN_WIMAX_COEX_STA_TABLE_VALID | 5533 IWN_WIMAX_COEX_ENABLE; 5534 memcpy(wimax.events, iwn6050_wimax_events, 5535 sizeof iwn6050_wimax_events); 5536 } else 5537 #endif 5538 { 5539 /* Disable WiMAX coexistence. */ 5540 wimax.flags = 0; 5541 memset(wimax.events, 0, sizeof wimax.events); 5542 } 5543 DPRINTF(sc, IWN_DEBUG_RESET, "%s: Configuring WiMAX coexistence\n", 5544 __func__); 5545 return iwn_cmd(sc, IWN5000_CMD_WIMAX_COEX, &wimax, sizeof wimax, 0); 5546 } 5547 5548 static int 5549 iwn5000_crystal_calib(struct iwn_softc *sc) 5550 { 5551 struct iwn5000_phy_calib_crystal cmd; 5552 5553 memset(&cmd, 0, sizeof cmd); 5554 cmd.code = IWN5000_PHY_CALIB_CRYSTAL; 5555 cmd.ngroups = 1; 5556 cmd.isvalid = 1; 5557 cmd.cap_pin[0] = le32toh(sc->eeprom_crystal) & 0xff; 5558 cmd.cap_pin[1] = (le32toh(sc->eeprom_crystal) >> 16) & 0xff; 5559 DPRINTF(sc, IWN_DEBUG_CALIBRATE, "sending crystal calibration %d, %d\n", 5560 cmd.cap_pin[0], cmd.cap_pin[1]); 5561 return iwn_cmd(sc, IWN_CMD_PHY_CALIB, &cmd, sizeof cmd, 0); 5562 } 5563 5564 static int 5565 iwn5000_temp_offset_calib(struct iwn_softc *sc) 5566 { 5567 struct iwn5000_phy_calib_temp_offset cmd; 5568 5569 memset(&cmd, 0, sizeof cmd); 5570 cmd.code = IWN5000_PHY_CALIB_TEMP_OFFSET; 5571 cmd.ngroups = 1; 5572 cmd.isvalid = 1; 5573 if (sc->eeprom_temp != 0) 5574 cmd.offset = htole16(sc->eeprom_temp); 5575 else 5576 cmd.offset = htole16(IWN_DEFAULT_TEMP_OFFSET); 5577 DPRINTF(sc, IWN_DEBUG_CALIBRATE, "setting radio sensor offset to %d\n", 5578 le16toh(cmd.offset)); 5579 return iwn_cmd(sc, IWN_CMD_PHY_CALIB, &cmd, sizeof cmd, 0); 5580 } 5581 5582 /* 5583 * This function is called after the runtime firmware notifies us of its 5584 * readiness (called in a process context). 5585 */ 5586 static int 5587 iwn4965_post_alive(struct iwn_softc *sc) 5588 { 5589 int error, qid; 5590 5591 if ((error = iwn_nic_lock(sc)) != 0) 5592 return error; 5593 5594 /* Clear TX scheduler state in SRAM. */ 5595 sc->sched_base = iwn_prph_read(sc, IWN_SCHED_SRAM_ADDR); 5596 iwn_mem_set_region_4(sc, sc->sched_base + IWN4965_SCHED_CTX_OFF, 0, 5597 IWN4965_SCHED_CTX_LEN / sizeof (uint32_t)); 5598 5599 /* Set physical address of TX scheduler rings (1KB aligned). */ 5600 iwn_prph_write(sc, IWN4965_SCHED_DRAM_ADDR, sc->sched_dma.paddr >> 10); 5601 5602 IWN_SETBITS(sc, IWN_FH_TX_CHICKEN, IWN_FH_TX_CHICKEN_SCHED_RETRY); 5603 5604 /* Disable chain mode for all our 16 queues. */ 5605 iwn_prph_write(sc, IWN4965_SCHED_QCHAIN_SEL, 0); 5606 5607 for (qid = 0; qid < IWN4965_NTXQUEUES; qid++) { 5608 iwn_prph_write(sc, IWN4965_SCHED_QUEUE_RDPTR(qid), 0); 5609 IWN_WRITE(sc, IWN_HBUS_TARG_WRPTR, qid << 8 | 0); 5610 5611 /* Set scheduler window size. */ 5612 iwn_mem_write(sc, sc->sched_base + 5613 IWN4965_SCHED_QUEUE_OFFSET(qid), IWN_SCHED_WINSZ); 5614 /* Set scheduler frame limit. */ 5615 iwn_mem_write(sc, sc->sched_base + 5616 IWN4965_SCHED_QUEUE_OFFSET(qid) + 4, 5617 IWN_SCHED_LIMIT << 16); 5618 } 5619 5620 /* Enable interrupts for all our 16 queues. */ 5621 iwn_prph_write(sc, IWN4965_SCHED_INTR_MASK, 0xffff); 5622 /* Identify TX FIFO rings (0-7). */ 5623 iwn_prph_write(sc, IWN4965_SCHED_TXFACT, 0xff); 5624 5625 /* Mark TX rings (4 EDCA + cmd + 2 HCCA) as active. */ 5626 for (qid = 0; qid < 7; qid++) { 5627 static uint8_t qid2fifo[] = { 3, 2, 1, 0, 4, 5, 6 }; 5628 iwn_prph_write(sc, IWN4965_SCHED_QUEUE_STATUS(qid), 5629 IWN4965_TXQ_STATUS_ACTIVE | qid2fifo[qid] << 1); 5630 } 5631 iwn_nic_unlock(sc); 5632 return 0; 5633 } 5634 5635 /* 5636 * This function is called after the initialization or runtime firmware 5637 * notifies us of its readiness (called in a process context). 5638 */ 5639 static int 5640 iwn5000_post_alive(struct iwn_softc *sc) 5641 { 5642 int error, qid; 5643 5644 /* Switch to using ICT interrupt mode. */ 5645 iwn5000_ict_reset(sc); 5646 5647 if ((error = iwn_nic_lock(sc)) != 0) 5648 return error; 5649 5650 /* Clear TX scheduler state in SRAM. */ 5651 sc->sched_base = iwn_prph_read(sc, IWN_SCHED_SRAM_ADDR); 5652 iwn_mem_set_region_4(sc, sc->sched_base + IWN5000_SCHED_CTX_OFF, 0, 5653 IWN5000_SCHED_CTX_LEN / sizeof (uint32_t)); 5654 5655 /* Set physical address of TX scheduler rings (1KB aligned). */ 5656 iwn_prph_write(sc, IWN5000_SCHED_DRAM_ADDR, sc->sched_dma.paddr >> 10); 5657 5658 IWN_SETBITS(sc, IWN_FH_TX_CHICKEN, IWN_FH_TX_CHICKEN_SCHED_RETRY); 5659 5660 /* Enable chain mode for all queues, except command queue. */ 5661 iwn_prph_write(sc, IWN5000_SCHED_QCHAIN_SEL, 0xfffef); 5662 iwn_prph_write(sc, IWN5000_SCHED_AGGR_SEL, 0); 5663 5664 for (qid = 0; qid < IWN5000_NTXQUEUES; qid++) { 5665 iwn_prph_write(sc, IWN5000_SCHED_QUEUE_RDPTR(qid), 0); 5666 IWN_WRITE(sc, IWN_HBUS_TARG_WRPTR, qid << 8 | 0); 5667 5668 iwn_mem_write(sc, sc->sched_base + 5669 IWN5000_SCHED_QUEUE_OFFSET(qid), 0); 5670 /* Set scheduler window size and frame limit. */ 5671 iwn_mem_write(sc, sc->sched_base + 5672 IWN5000_SCHED_QUEUE_OFFSET(qid) + 4, 5673 IWN_SCHED_LIMIT << 16 | IWN_SCHED_WINSZ); 5674 } 5675 5676 /* Enable interrupts for all our 20 queues. */ 5677 iwn_prph_write(sc, IWN5000_SCHED_INTR_MASK, 0xfffff); 5678 /* Identify TX FIFO rings (0-7). */ 5679 iwn_prph_write(sc, IWN5000_SCHED_TXFACT, 0xff); 5680 5681 /* Mark TX rings (4 EDCA + cmd + 2 HCCA) as active. */ 5682 for (qid = 0; qid < 7; qid++) { 5683 static uint8_t qid2fifo[] = { 3, 2, 1, 0, 7, 5, 6 }; 5684 iwn_prph_write(sc, IWN5000_SCHED_QUEUE_STATUS(qid), 5685 IWN5000_TXQ_STATUS_ACTIVE | qid2fifo[qid]); 5686 } 5687 iwn_nic_unlock(sc); 5688 5689 /* Configure WiMAX coexistence for combo adapters. */ 5690 error = iwn5000_send_wimax_coex(sc); 5691 if (error != 0) { 5692 device_printf(sc->sc_dev, 5693 "%s: could not configure WiMAX coexistence, error %d\n", 5694 __func__, error); 5695 return error; 5696 } 5697 if (sc->hw_type != IWN_HW_REV_TYPE_5150) { 5698 /* Perform crystal calibration. */ 5699 error = iwn5000_crystal_calib(sc); 5700 if (error != 0) { 5701 device_printf(sc->sc_dev, 5702 "%s: crystal calibration failed, error %d\n", 5703 __func__, error); 5704 return error; 5705 } 5706 } 5707 if (!(sc->sc_flags & IWN_FLAG_CALIB_DONE)) { 5708 /* Query calibration from the initialization firmware. */ 5709 if ((error = iwn5000_query_calibration(sc)) != 0) { 5710 device_printf(sc->sc_dev, 5711 "%s: could not query calibration, error %d\n", 5712 __func__, error); 5713 return error; 5714 } 5715 /* 5716 * We have the calibration results now, reboot with the 5717 * runtime firmware (call ourselves recursively!) 5718 */ 5719 iwn_hw_stop(sc); 5720 error = iwn_hw_init(sc); 5721 } else { 5722 /* Send calibration results to runtime firmware. */ 5723 error = iwn5000_send_calibration(sc); 5724 } 5725 return error; 5726 } 5727 5728 /* 5729 * The firmware boot code is small and is intended to be copied directly into 5730 * the NIC internal memory (no DMA transfer). 5731 */ 5732 static int 5733 iwn4965_load_bootcode(struct iwn_softc *sc, const uint8_t *ucode, int size) 5734 { 5735 int error, ntries; 5736 5737 size /= sizeof (uint32_t); 5738 5739 if ((error = iwn_nic_lock(sc)) != 0) 5740 return error; 5741 5742 /* Copy microcode image into NIC memory. */ 5743 iwn_prph_write_region_4(sc, IWN_BSM_SRAM_BASE, 5744 (const uint32_t *)ucode, size); 5745 5746 iwn_prph_write(sc, IWN_BSM_WR_MEM_SRC, 0); 5747 iwn_prph_write(sc, IWN_BSM_WR_MEM_DST, IWN_FW_TEXT_BASE); 5748 iwn_prph_write(sc, IWN_BSM_WR_DWCOUNT, size); 5749 5750 /* Start boot load now. */ 5751 iwn_prph_write(sc, IWN_BSM_WR_CTRL, IWN_BSM_WR_CTRL_START); 5752 5753 /* Wait for transfer to complete. */ 5754 for (ntries = 0; ntries < 1000; ntries++) { 5755 if (!(iwn_prph_read(sc, IWN_BSM_WR_CTRL) & 5756 IWN_BSM_WR_CTRL_START)) 5757 break; 5758 DELAY(10); 5759 } 5760 if (ntries == 1000) { 5761 device_printf(sc->sc_dev, "%s: could not load boot firmware\n", 5762 __func__); 5763 iwn_nic_unlock(sc); 5764 return ETIMEDOUT; 5765 } 5766 5767 /* Enable boot after power up. */ 5768 iwn_prph_write(sc, IWN_BSM_WR_CTRL, IWN_BSM_WR_CTRL_START_EN); 5769 5770 iwn_nic_unlock(sc); 5771 return 0; 5772 } 5773 5774 static int 5775 iwn4965_load_firmware(struct iwn_softc *sc) 5776 { 5777 struct iwn_fw_info *fw = &sc->fw; 5778 struct iwn_dma_info *dma = &sc->fw_dma; 5779 int error; 5780 5781 /* Copy initialization sections into pre-allocated DMA-safe memory. */ 5782 memcpy(dma->vaddr, fw->init.data, fw->init.datasz); 5783 bus_dmamap_sync(dma->tag, dma->map, BUS_DMASYNC_PREWRITE); 5784 memcpy(dma->vaddr + IWN4965_FW_DATA_MAXSZ, 5785 fw->init.text, fw->init.textsz); 5786 bus_dmamap_sync(dma->tag, dma->map, BUS_DMASYNC_PREWRITE); 5787 5788 /* Tell adapter where to find initialization sections. */ 5789 if ((error = iwn_nic_lock(sc)) != 0) 5790 return error; 5791 iwn_prph_write(sc, IWN_BSM_DRAM_DATA_ADDR, dma->paddr >> 4); 5792 iwn_prph_write(sc, IWN_BSM_DRAM_DATA_SIZE, fw->init.datasz); 5793 iwn_prph_write(sc, IWN_BSM_DRAM_TEXT_ADDR, 5794 (dma->paddr + IWN4965_FW_DATA_MAXSZ) >> 4); 5795 iwn_prph_write(sc, IWN_BSM_DRAM_TEXT_SIZE, fw->init.textsz); 5796 iwn_nic_unlock(sc); 5797 5798 /* Load firmware boot code. */ 5799 error = iwn4965_load_bootcode(sc, fw->boot.text, fw->boot.textsz); 5800 if (error != 0) { 5801 device_printf(sc->sc_dev, "%s: could not load boot firmware\n", 5802 __func__); 5803 return error; 5804 } 5805 /* Now press "execute". */ 5806 IWN_WRITE(sc, IWN_RESET, 0); 5807 5808 /* Wait at most one second for first alive notification. */ 5809 if ((error = msleep(sc, &sc->sc_mtx, PCATCH, "iwninit", hz)) != 0) { 5810 device_printf(sc->sc_dev, 5811 "%s: timeout waiting for adapter to initialize, error %d\n", 5812 __func__, error); 5813 return error; 5814 } 5815 5816 /* Retrieve current temperature for initial TX power calibration. */ 5817 sc->rawtemp = sc->ucode_info.temp[3].chan20MHz; 5818 sc->temp = iwn4965_get_temperature(sc); 5819 5820 /* Copy runtime sections into pre-allocated DMA-safe memory. */ 5821 memcpy(dma->vaddr, fw->main.data, fw->main.datasz); 5822 bus_dmamap_sync(dma->tag, dma->map, BUS_DMASYNC_PREWRITE); 5823 memcpy(dma->vaddr + IWN4965_FW_DATA_MAXSZ, 5824 fw->main.text, fw->main.textsz); 5825 bus_dmamap_sync(dma->tag, dma->map, BUS_DMASYNC_PREWRITE); 5826 5827 /* Tell adapter where to find runtime sections. */ 5828 if ((error = iwn_nic_lock(sc)) != 0) 5829 return error; 5830 iwn_prph_write(sc, IWN_BSM_DRAM_DATA_ADDR, dma->paddr >> 4); 5831 iwn_prph_write(sc, IWN_BSM_DRAM_DATA_SIZE, fw->main.datasz); 5832 iwn_prph_write(sc, IWN_BSM_DRAM_TEXT_ADDR, 5833 (dma->paddr + IWN4965_FW_DATA_MAXSZ) >> 4); 5834 iwn_prph_write(sc, IWN_BSM_DRAM_TEXT_SIZE, 5835 IWN_FW_UPDATED | fw->main.textsz); 5836 iwn_nic_unlock(sc); 5837 5838 return 0; 5839 } 5840 5841 static int 5842 iwn5000_load_firmware_section(struct iwn_softc *sc, uint32_t dst, 5843 const uint8_t *section, int size) 5844 { 5845 struct iwn_dma_info *dma = &sc->fw_dma; 5846 int error; 5847 5848 /* Copy firmware section into pre-allocated DMA-safe memory. */ 5849 memcpy(dma->vaddr, section, size); 5850 bus_dmamap_sync(dma->tag, dma->map, BUS_DMASYNC_PREWRITE); 5851 5852 if ((error = iwn_nic_lock(sc)) != 0) 5853 return error; 5854 5855 IWN_WRITE(sc, IWN_FH_TX_CONFIG(IWN_SRVC_DMACHNL), 5856 IWN_FH_TX_CONFIG_DMA_PAUSE); 5857 5858 IWN_WRITE(sc, IWN_FH_SRAM_ADDR(IWN_SRVC_DMACHNL), dst); 5859 IWN_WRITE(sc, IWN_FH_TFBD_CTRL0(IWN_SRVC_DMACHNL), 5860 IWN_LOADDR(dma->paddr)); 5861 IWN_WRITE(sc, IWN_FH_TFBD_CTRL1(IWN_SRVC_DMACHNL), 5862 IWN_HIADDR(dma->paddr) << 28 | size); 5863 IWN_WRITE(sc, IWN_FH_TXBUF_STATUS(IWN_SRVC_DMACHNL), 5864 IWN_FH_TXBUF_STATUS_TBNUM(1) | 5865 IWN_FH_TXBUF_STATUS_TBIDX(1) | 5866 IWN_FH_TXBUF_STATUS_TFBD_VALID); 5867 5868 /* Kick Flow Handler to start DMA transfer. */ 5869 IWN_WRITE(sc, IWN_FH_TX_CONFIG(IWN_SRVC_DMACHNL), 5870 IWN_FH_TX_CONFIG_DMA_ENA | IWN_FH_TX_CONFIG_CIRQ_HOST_ENDTFD); 5871 5872 iwn_nic_unlock(sc); 5873 5874 /* Wait at most five seconds for FH DMA transfer to complete. */ 5875 return msleep(sc, &sc->sc_mtx, PCATCH, "iwninit", 5 * hz); 5876 } 5877 5878 static int 5879 iwn5000_load_firmware(struct iwn_softc *sc) 5880 { 5881 struct iwn_fw_part *fw; 5882 int error; 5883 5884 /* Load the initialization firmware on first boot only. */ 5885 fw = (sc->sc_flags & IWN_FLAG_CALIB_DONE) ? 5886 &sc->fw.main : &sc->fw.init; 5887 5888 error = iwn5000_load_firmware_section(sc, IWN_FW_TEXT_BASE, 5889 fw->text, fw->textsz); 5890 if (error != 0) { 5891 device_printf(sc->sc_dev, 5892 "%s: could not load firmware %s section, error %d\n", 5893 __func__, ".text", error); 5894 return error; 5895 } 5896 error = iwn5000_load_firmware_section(sc, IWN_FW_DATA_BASE, 5897 fw->data, fw->datasz); 5898 if (error != 0) { 5899 device_printf(sc->sc_dev, 5900 "%s: could not load firmware %s section, error %d\n", 5901 __func__, ".data", error); 5902 return error; 5903 } 5904 5905 /* Now press "execute". */ 5906 IWN_WRITE(sc, IWN_RESET, 0); 5907 return 0; 5908 } 5909 5910 /* 5911 * Extract text and data sections from a legacy firmware image. 5912 */ 5913 static int 5914 iwn_read_firmware_leg(struct iwn_softc *sc, struct iwn_fw_info *fw) 5915 { 5916 const uint32_t *ptr; 5917 size_t hdrlen = 24; 5918 uint32_t rev; 5919 5920 ptr = (const uint32_t *)fw->data; 5921 rev = le32toh(*ptr++); 5922 5923 /* Check firmware API version. */ 5924 if (IWN_FW_API(rev) <= 1) { 5925 device_printf(sc->sc_dev, 5926 "%s: bad firmware, need API version >=2\n", __func__); 5927 return EINVAL; 5928 } 5929 if (IWN_FW_API(rev) >= 3) { 5930 /* Skip build number (version 2 header). */ 5931 hdrlen += 4; 5932 ptr++; 5933 } 5934 if (fw->size < hdrlen) { 5935 device_printf(sc->sc_dev, "%s: firmware too short: %zu bytes\n", 5936 __func__, fw->size); 5937 return EINVAL; 5938 } 5939 fw->main.textsz = le32toh(*ptr++); 5940 fw->main.datasz = le32toh(*ptr++); 5941 fw->init.textsz = le32toh(*ptr++); 5942 fw->init.datasz = le32toh(*ptr++); 5943 fw->boot.textsz = le32toh(*ptr++); 5944 5945 /* Check that all firmware sections fit. */ 5946 if (fw->size < hdrlen + fw->main.textsz + fw->main.datasz + 5947 fw->init.textsz + fw->init.datasz + fw->boot.textsz) { 5948 device_printf(sc->sc_dev, "%s: firmware too short: %zu bytes\n", 5949 __func__, fw->size); 5950 return EINVAL; 5951 } 5952 5953 /* Get pointers to firmware sections. */ 5954 fw->main.text = (const uint8_t *)ptr; 5955 fw->main.data = fw->main.text + fw->main.textsz; 5956 fw->init.text = fw->main.data + fw->main.datasz; 5957 fw->init.data = fw->init.text + fw->init.textsz; 5958 fw->boot.text = fw->init.data + fw->init.datasz; 5959 return 0; 5960 } 5961 5962 /* 5963 * Extract text and data sections from a TLV firmware image. 5964 */ 5965 static int 5966 iwn_read_firmware_tlv(struct iwn_softc *sc, struct iwn_fw_info *fw, 5967 uint16_t alt) 5968 { 5969 const struct iwn_fw_tlv_hdr *hdr; 5970 const struct iwn_fw_tlv *tlv; 5971 const uint8_t *ptr, *end; 5972 uint64_t altmask; 5973 uint32_t len, tmp; 5974 5975 if (fw->size < sizeof (*hdr)) { 5976 device_printf(sc->sc_dev, "%s: firmware too short: %zu bytes\n", 5977 __func__, fw->size); 5978 return EINVAL; 5979 } 5980 hdr = (const struct iwn_fw_tlv_hdr *)fw->data; 5981 if (hdr->signature != htole32(IWN_FW_SIGNATURE)) { 5982 device_printf(sc->sc_dev, "%s: bad firmware signature 0x%08x\n", 5983 __func__, le32toh(hdr->signature)); 5984 return EINVAL; 5985 } 5986 DPRINTF(sc, IWN_DEBUG_RESET, "FW: \"%.64s\", build 0x%x\n", hdr->descr, 5987 le32toh(hdr->build)); 5988 5989 /* 5990 * Select the closest supported alternative that is less than 5991 * or equal to the specified one. 5992 */ 5993 altmask = le64toh(hdr->altmask); 5994 while (alt > 0 && !(altmask & (1ULL << alt))) 5995 alt--; /* Downgrade. */ 5996 DPRINTF(sc, IWN_DEBUG_RESET, "using alternative %d\n", alt); 5997 5998 ptr = (const uint8_t *)(hdr + 1); 5999 end = (const uint8_t *)(fw->data + fw->size); 6000 6001 /* Parse type-length-value fields. */ 6002 while (ptr + sizeof (*tlv) <= end) { 6003 tlv = (const struct iwn_fw_tlv *)ptr; 6004 len = le32toh(tlv->len); 6005 6006 ptr += sizeof (*tlv); 6007 if (ptr + len > end) { 6008 device_printf(sc->sc_dev, 6009 "%s: firmware too short: %zu bytes\n", __func__, 6010 fw->size); 6011 return EINVAL; 6012 } 6013 /* Skip other alternatives. */ 6014 if (tlv->alt != 0 && tlv->alt != htole16(alt)) 6015 goto next; 6016 6017 switch (le16toh(tlv->type)) { 6018 case IWN_FW_TLV_MAIN_TEXT: 6019 fw->main.text = ptr; 6020 fw->main.textsz = len; 6021 break; 6022 case IWN_FW_TLV_MAIN_DATA: 6023 fw->main.data = ptr; 6024 fw->main.datasz = len; 6025 break; 6026 case IWN_FW_TLV_INIT_TEXT: 6027 fw->init.text = ptr; 6028 fw->init.textsz = len; 6029 break; 6030 case IWN_FW_TLV_INIT_DATA: 6031 fw->init.data = ptr; 6032 fw->init.datasz = len; 6033 break; 6034 case IWN_FW_TLV_BOOT_TEXT: 6035 fw->boot.text = ptr; 6036 fw->boot.textsz = len; 6037 break; 6038 case IWN_FW_TLV_ENH_SENS: 6039 if (!len) 6040 sc->sc_flags |= IWN_FLAG_ENH_SENS; 6041 break; 6042 case IWN_FW_TLV_PHY_CALIB: 6043 tmp = htole32(*ptr); 6044 if (tmp < 253) { 6045 sc->reset_noise_gain = tmp; 6046 sc->noise_gain = tmp + 1; 6047 } 6048 break; 6049 default: 6050 DPRINTF(sc, IWN_DEBUG_RESET, 6051 "TLV type %d not handled\n", le16toh(tlv->type)); 6052 break; 6053 } 6054 next: /* TLV fields are 32-bit aligned. */ 6055 ptr += (len + 3) & ~3; 6056 } 6057 return 0; 6058 } 6059 6060 static int 6061 iwn_read_firmware(struct iwn_softc *sc) 6062 { 6063 struct iwn_fw_info *fw = &sc->fw; 6064 int error; 6065 6066 IWN_UNLOCK(sc); 6067 6068 memset(fw, 0, sizeof (*fw)); 6069 6070 /* Read firmware image from filesystem. */ 6071 sc->fw_fp = firmware_get(sc->fwname); 6072 if (sc->fw_fp == NULL) { 6073 device_printf(sc->sc_dev, "%s: could not read firmware %s\n", 6074 __func__, sc->fwname); 6075 IWN_LOCK(sc); 6076 return EINVAL; 6077 } 6078 IWN_LOCK(sc); 6079 6080 fw->size = sc->fw_fp->datasize; 6081 fw->data = (const uint8_t *)sc->fw_fp->data; 6082 if (fw->size < sizeof (uint32_t)) { 6083 device_printf(sc->sc_dev, "%s: firmware too short: %zu bytes\n", 6084 __func__, fw->size); 6085 firmware_put(sc->fw_fp, FIRMWARE_UNLOAD); 6086 sc->fw_fp = NULL; 6087 return EINVAL; 6088 } 6089 6090 /* Retrieve text and data sections. */ 6091 if (*(const uint32_t *)fw->data != 0) /* Legacy image. */ 6092 error = iwn_read_firmware_leg(sc, fw); 6093 else 6094 error = iwn_read_firmware_tlv(sc, fw, 1); 6095 if (error != 0) { 6096 device_printf(sc->sc_dev, 6097 "%s: could not read firmware sections, error %d\n", 6098 __func__, error); 6099 firmware_put(sc->fw_fp, FIRMWARE_UNLOAD); 6100 sc->fw_fp = NULL; 6101 return error; 6102 } 6103 6104 /* Make sure text and data sections fit in hardware memory. */ 6105 if (fw->main.textsz > sc->fw_text_maxsz || 6106 fw->main.datasz > sc->fw_data_maxsz || 6107 fw->init.textsz > sc->fw_text_maxsz || 6108 fw->init.datasz > sc->fw_data_maxsz || 6109 fw->boot.textsz > IWN_FW_BOOT_TEXT_MAXSZ || 6110 (fw->boot.textsz & 3) != 0) { 6111 device_printf(sc->sc_dev, "%s: firmware sections too large\n", 6112 __func__); 6113 firmware_put(sc->fw_fp, FIRMWARE_UNLOAD); 6114 sc->fw_fp = NULL; 6115 return EINVAL; 6116 } 6117 6118 /* We can proceed with loading the firmware. */ 6119 return 0; 6120 } 6121 6122 static int 6123 iwn_clock_wait(struct iwn_softc *sc) 6124 { 6125 int ntries; 6126 6127 /* Set "initialization complete" bit. */ 6128 IWN_SETBITS(sc, IWN_GP_CNTRL, IWN_GP_CNTRL_INIT_DONE); 6129 6130 /* Wait for clock stabilization. */ 6131 for (ntries = 0; ntries < 2500; ntries++) { 6132 if (IWN_READ(sc, IWN_GP_CNTRL) & IWN_GP_CNTRL_MAC_CLOCK_READY) 6133 return 0; 6134 DELAY(10); 6135 } 6136 device_printf(sc->sc_dev, 6137 "%s: timeout waiting for clock stabilization\n", __func__); 6138 return ETIMEDOUT; 6139 } 6140 6141 static int 6142 iwn_apm_init(struct iwn_softc *sc) 6143 { 6144 uint32_t reg; 6145 int error; 6146 6147 /* Disable L0s exit timer (NMI bug workaround). */ 6148 IWN_SETBITS(sc, IWN_GIO_CHICKEN, IWN_GIO_CHICKEN_DIS_L0S_TIMER); 6149 /* Don't wait for ICH L0s (ICH bug workaround). */ 6150 IWN_SETBITS(sc, IWN_GIO_CHICKEN, IWN_GIO_CHICKEN_L1A_NO_L0S_RX); 6151 6152 /* Set FH wait threshold to max (HW bug under stress workaround). */ 6153 IWN_SETBITS(sc, IWN_DBG_HPET_MEM, 0xffff0000); 6154 6155 /* Enable HAP INTA to move adapter from L1a to L0s. */ 6156 IWN_SETBITS(sc, IWN_HW_IF_CONFIG, IWN_HW_IF_CONFIG_HAP_WAKE_L1A); 6157 6158 /* Retrieve PCIe Active State Power Management (ASPM). */ 6159 reg = pci_read_config(sc->sc_dev, sc->sc_cap_off + 0x10, 1); 6160 /* Workaround for HW instability in PCIe L0->L0s->L1 transition. */ 6161 if (reg & 0x02) /* L1 Entry enabled. */ 6162 IWN_SETBITS(sc, IWN_GIO, IWN_GIO_L0S_ENA); 6163 else 6164 IWN_CLRBITS(sc, IWN_GIO, IWN_GIO_L0S_ENA); 6165 6166 if (sc->hw_type != IWN_HW_REV_TYPE_4965 && 6167 sc->hw_type <= IWN_HW_REV_TYPE_1000) 6168 IWN_SETBITS(sc, IWN_ANA_PLL, IWN_ANA_PLL_INIT); 6169 6170 /* Wait for clock stabilization before accessing prph. */ 6171 if ((error = iwn_clock_wait(sc)) != 0) 6172 return error; 6173 6174 if ((error = iwn_nic_lock(sc)) != 0) 6175 return error; 6176 if (sc->hw_type == IWN_HW_REV_TYPE_4965) { 6177 /* Enable DMA and BSM (Bootstrap State Machine). */ 6178 iwn_prph_write(sc, IWN_APMG_CLK_EN, 6179 IWN_APMG_CLK_CTRL_DMA_CLK_RQT | 6180 IWN_APMG_CLK_CTRL_BSM_CLK_RQT); 6181 } else { 6182 /* Enable DMA. */ 6183 iwn_prph_write(sc, IWN_APMG_CLK_EN, 6184 IWN_APMG_CLK_CTRL_DMA_CLK_RQT); 6185 } 6186 DELAY(20); 6187 /* Disable L1-Active. */ 6188 iwn_prph_setbits(sc, IWN_APMG_PCI_STT, IWN_APMG_PCI_STT_L1A_DIS); 6189 iwn_nic_unlock(sc); 6190 6191 return 0; 6192 } 6193 6194 static void 6195 iwn_apm_stop_master(struct iwn_softc *sc) 6196 { 6197 int ntries; 6198 6199 /* Stop busmaster DMA activity. */ 6200 IWN_SETBITS(sc, IWN_RESET, IWN_RESET_STOP_MASTER); 6201 for (ntries = 0; ntries < 100; ntries++) { 6202 if (IWN_READ(sc, IWN_RESET) & IWN_RESET_MASTER_DISABLED) 6203 return; 6204 DELAY(10); 6205 } 6206 device_printf(sc->sc_dev, "%s: timeout waiting for master\n", __func__); 6207 } 6208 6209 static void 6210 iwn_apm_stop(struct iwn_softc *sc) 6211 { 6212 iwn_apm_stop_master(sc); 6213 6214 /* Reset the entire device. */ 6215 IWN_SETBITS(sc, IWN_RESET, IWN_RESET_SW); 6216 DELAY(10); 6217 /* Clear "initialization complete" bit. */ 6218 IWN_CLRBITS(sc, IWN_GP_CNTRL, IWN_GP_CNTRL_INIT_DONE); 6219 } 6220 6221 static int 6222 iwn4965_nic_config(struct iwn_softc *sc) 6223 { 6224 if (IWN_RFCFG_TYPE(sc->rfcfg) == 1) { 6225 /* 6226 * I don't believe this to be correct but this is what the 6227 * vendor driver is doing. Probably the bits should not be 6228 * shifted in IWN_RFCFG_*. 6229 */ 6230 IWN_SETBITS(sc, IWN_HW_IF_CONFIG, 6231 IWN_RFCFG_TYPE(sc->rfcfg) | 6232 IWN_RFCFG_STEP(sc->rfcfg) | 6233 IWN_RFCFG_DASH(sc->rfcfg)); 6234 } 6235 IWN_SETBITS(sc, IWN_HW_IF_CONFIG, 6236 IWN_HW_IF_CONFIG_RADIO_SI | IWN_HW_IF_CONFIG_MAC_SI); 6237 return 0; 6238 } 6239 6240 static int 6241 iwn5000_nic_config(struct iwn_softc *sc) 6242 { 6243 uint32_t tmp; 6244 int error; 6245 6246 if (IWN_RFCFG_TYPE(sc->rfcfg) < 3) { 6247 IWN_SETBITS(sc, IWN_HW_IF_CONFIG, 6248 IWN_RFCFG_TYPE(sc->rfcfg) | 6249 IWN_RFCFG_STEP(sc->rfcfg) | 6250 IWN_RFCFG_DASH(sc->rfcfg)); 6251 } 6252 IWN_SETBITS(sc, IWN_HW_IF_CONFIG, 6253 IWN_HW_IF_CONFIG_RADIO_SI | IWN_HW_IF_CONFIG_MAC_SI); 6254 6255 if ((error = iwn_nic_lock(sc)) != 0) 6256 return error; 6257 iwn_prph_setbits(sc, IWN_APMG_PS, IWN_APMG_PS_EARLY_PWROFF_DIS); 6258 6259 if (sc->hw_type == IWN_HW_REV_TYPE_1000) { 6260 /* 6261 * Select first Switching Voltage Regulator (1.32V) to 6262 * solve a stability issue related to noisy DC2DC line 6263 * in the silicon of 1000 Series. 6264 */ 6265 tmp = iwn_prph_read(sc, IWN_APMG_DIGITAL_SVR); 6266 tmp &= ~IWN_APMG_DIGITAL_SVR_VOLTAGE_MASK; 6267 tmp |= IWN_APMG_DIGITAL_SVR_VOLTAGE_1_32; 6268 iwn_prph_write(sc, IWN_APMG_DIGITAL_SVR, tmp); 6269 } 6270 iwn_nic_unlock(sc); 6271 6272 if (sc->sc_flags & IWN_FLAG_INTERNAL_PA) { 6273 /* Use internal power amplifier only. */ 6274 IWN_WRITE(sc, IWN_GP_DRIVER, IWN_GP_DRIVER_RADIO_2X2_IPA); 6275 } 6276 if ((sc->hw_type == IWN_HW_REV_TYPE_6050 || 6277 sc->hw_type == IWN_HW_REV_TYPE_6005) && sc->calib_ver >= 6) { 6278 /* Indicate that ROM calibration version is >=6. */ 6279 IWN_SETBITS(sc, IWN_GP_DRIVER, IWN_GP_DRIVER_CALIB_VER6); 6280 } 6281 if (sc->hw_type == IWN_HW_REV_TYPE_6005) 6282 IWN_SETBITS(sc, IWN_GP_DRIVER, IWN_GP_DRIVER_6050_1X2); 6283 return 0; 6284 } 6285 6286 /* 6287 * Take NIC ownership over Intel Active Management Technology (AMT). 6288 */ 6289 static int 6290 iwn_hw_prepare(struct iwn_softc *sc) 6291 { 6292 int ntries; 6293 6294 /* Check if hardware is ready. */ 6295 IWN_SETBITS(sc, IWN_HW_IF_CONFIG, IWN_HW_IF_CONFIG_NIC_READY); 6296 for (ntries = 0; ntries < 5; ntries++) { 6297 if (IWN_READ(sc, IWN_HW_IF_CONFIG) & 6298 IWN_HW_IF_CONFIG_NIC_READY) 6299 return 0; 6300 DELAY(10); 6301 } 6302 6303 /* Hardware not ready, force into ready state. */ 6304 IWN_SETBITS(sc, IWN_HW_IF_CONFIG, IWN_HW_IF_CONFIG_PREPARE); 6305 for (ntries = 0; ntries < 15000; ntries++) { 6306 if (!(IWN_READ(sc, IWN_HW_IF_CONFIG) & 6307 IWN_HW_IF_CONFIG_PREPARE_DONE)) 6308 break; 6309 DELAY(10); 6310 } 6311 if (ntries == 15000) 6312 return ETIMEDOUT; 6313 6314 /* Hardware should be ready now. */ 6315 IWN_SETBITS(sc, IWN_HW_IF_CONFIG, IWN_HW_IF_CONFIG_NIC_READY); 6316 for (ntries = 0; ntries < 5; ntries++) { 6317 if (IWN_READ(sc, IWN_HW_IF_CONFIG) & 6318 IWN_HW_IF_CONFIG_NIC_READY) 6319 return 0; 6320 DELAY(10); 6321 } 6322 return ETIMEDOUT; 6323 } 6324 6325 static int 6326 iwn_hw_init(struct iwn_softc *sc) 6327 { 6328 struct iwn_ops *ops = &sc->ops; 6329 int error, chnl, qid; 6330 6331 /* Clear pending interrupts. */ 6332 IWN_WRITE(sc, IWN_INT, 0xffffffff); 6333 6334 if ((error = iwn_apm_init(sc)) != 0) { 6335 device_printf(sc->sc_dev, 6336 "%s: could not power ON adapter, error %d\n", __func__, 6337 error); 6338 return error; 6339 } 6340 6341 /* Select VMAIN power source. */ 6342 if ((error = iwn_nic_lock(sc)) != 0) 6343 return error; 6344 iwn_prph_clrbits(sc, IWN_APMG_PS, IWN_APMG_PS_PWR_SRC_MASK); 6345 iwn_nic_unlock(sc); 6346 6347 /* Perform adapter-specific initialization. */ 6348 if ((error = ops->nic_config(sc)) != 0) 6349 return error; 6350 6351 /* Initialize RX ring. */ 6352 if ((error = iwn_nic_lock(sc)) != 0) 6353 return error; 6354 IWN_WRITE(sc, IWN_FH_RX_CONFIG, 0); 6355 IWN_WRITE(sc, IWN_FH_RX_WPTR, 0); 6356 /* Set physical address of RX ring (256-byte aligned). */ 6357 IWN_WRITE(sc, IWN_FH_RX_BASE, sc->rxq.desc_dma.paddr >> 8); 6358 /* Set physical address of RX status (16-byte aligned). */ 6359 IWN_WRITE(sc, IWN_FH_STATUS_WPTR, sc->rxq.stat_dma.paddr >> 4); 6360 /* Enable RX. */ 6361 IWN_WRITE(sc, IWN_FH_RX_CONFIG, 6362 IWN_FH_RX_CONFIG_ENA | 6363 IWN_FH_RX_CONFIG_IGN_RXF_EMPTY | /* HW bug workaround */ 6364 IWN_FH_RX_CONFIG_IRQ_DST_HOST | 6365 IWN_FH_RX_CONFIG_SINGLE_FRAME | 6366 IWN_FH_RX_CONFIG_RB_TIMEOUT(0) | 6367 IWN_FH_RX_CONFIG_NRBD(IWN_RX_RING_COUNT_LOG)); 6368 iwn_nic_unlock(sc); 6369 IWN_WRITE(sc, IWN_FH_RX_WPTR, (IWN_RX_RING_COUNT - 1) & ~7); 6370 6371 if ((error = iwn_nic_lock(sc)) != 0) 6372 return error; 6373 6374 /* Initialize TX scheduler. */ 6375 iwn_prph_write(sc, sc->sched_txfact_addr, 0); 6376 6377 /* Set physical address of "keep warm" page (16-byte aligned). */ 6378 IWN_WRITE(sc, IWN_FH_KW_ADDR, sc->kw_dma.paddr >> 4); 6379 6380 /* Initialize TX rings. */ 6381 for (qid = 0; qid < sc->ntxqs; qid++) { 6382 struct iwn_tx_ring *txq = &sc->txq[qid]; 6383 6384 /* Set physical address of TX ring (256-byte aligned). */ 6385 IWN_WRITE(sc, IWN_FH_CBBC_QUEUE(qid), 6386 txq->desc_dma.paddr >> 8); 6387 } 6388 iwn_nic_unlock(sc); 6389 6390 /* Enable DMA channels. */ 6391 for (chnl = 0; chnl < sc->ndmachnls; chnl++) { 6392 IWN_WRITE(sc, IWN_FH_TX_CONFIG(chnl), 6393 IWN_FH_TX_CONFIG_DMA_ENA | 6394 IWN_FH_TX_CONFIG_DMA_CREDIT_ENA); 6395 } 6396 6397 /* Clear "radio off" and "commands blocked" bits. */ 6398 IWN_WRITE(sc, IWN_UCODE_GP1_CLR, IWN_UCODE_GP1_RFKILL); 6399 IWN_WRITE(sc, IWN_UCODE_GP1_CLR, IWN_UCODE_GP1_CMD_BLOCKED); 6400 6401 /* Clear pending interrupts. */ 6402 IWN_WRITE(sc, IWN_INT, 0xffffffff); 6403 /* Enable interrupt coalescing. */ 6404 IWN_WRITE(sc, IWN_INT_COALESCING, 512 / 8); 6405 /* Enable interrupts. */ 6406 IWN_WRITE(sc, IWN_INT_MASK, sc->int_mask); 6407 6408 /* _Really_ make sure "radio off" bit is cleared! */ 6409 IWN_WRITE(sc, IWN_UCODE_GP1_CLR, IWN_UCODE_GP1_RFKILL); 6410 IWN_WRITE(sc, IWN_UCODE_GP1_CLR, IWN_UCODE_GP1_RFKILL); 6411 6412 /* Enable shadow registers. */ 6413 if (sc->hw_type >= IWN_HW_REV_TYPE_6000) 6414 IWN_SETBITS(sc, IWN_SHADOW_REG_CTRL, 0x800fffff); 6415 6416 if ((error = ops->load_firmware(sc)) != 0) { 6417 device_printf(sc->sc_dev, 6418 "%s: could not load firmware, error %d\n", __func__, 6419 error); 6420 return error; 6421 } 6422 /* Wait at most one second for firmware alive notification. */ 6423 if ((error = msleep(sc, &sc->sc_mtx, PCATCH, "iwninit", hz)) != 0) { 6424 device_printf(sc->sc_dev, 6425 "%s: timeout waiting for adapter to initialize, error %d\n", 6426 __func__, error); 6427 return error; 6428 } 6429 /* Do post-firmware initialization. */ 6430 return ops->post_alive(sc); 6431 } 6432 6433 static void 6434 iwn_hw_stop(struct iwn_softc *sc) 6435 { 6436 int chnl, qid, ntries; 6437 6438 IWN_WRITE(sc, IWN_RESET, IWN_RESET_NEVO); 6439 6440 /* Disable interrupts. */ 6441 IWN_WRITE(sc, IWN_INT_MASK, 0); 6442 IWN_WRITE(sc, IWN_INT, 0xffffffff); 6443 IWN_WRITE(sc, IWN_FH_INT, 0xffffffff); 6444 sc->sc_flags &= ~IWN_FLAG_USE_ICT; 6445 6446 /* Make sure we no longer hold the NIC lock. */ 6447 iwn_nic_unlock(sc); 6448 6449 /* Stop TX scheduler. */ 6450 iwn_prph_write(sc, sc->sched_txfact_addr, 0); 6451 6452 /* Stop all DMA channels. */ 6453 if (iwn_nic_lock(sc) == 0) { 6454 for (chnl = 0; chnl < sc->ndmachnls; chnl++) { 6455 IWN_WRITE(sc, IWN_FH_TX_CONFIG(chnl), 0); 6456 for (ntries = 0; ntries < 200; ntries++) { 6457 if (IWN_READ(sc, IWN_FH_TX_STATUS) & 6458 IWN_FH_TX_STATUS_IDLE(chnl)) 6459 break; 6460 DELAY(10); 6461 } 6462 } 6463 iwn_nic_unlock(sc); 6464 } 6465 6466 /* Stop RX ring. */ 6467 iwn_reset_rx_ring(sc, &sc->rxq); 6468 6469 /* Reset all TX rings. */ 6470 for (qid = 0; qid < sc->ntxqs; qid++) 6471 iwn_reset_tx_ring(sc, &sc->txq[qid]); 6472 6473 if (iwn_nic_lock(sc) == 0) { 6474 iwn_prph_write(sc, IWN_APMG_CLK_DIS, 6475 IWN_APMG_CLK_CTRL_DMA_CLK_RQT); 6476 iwn_nic_unlock(sc); 6477 } 6478 DELAY(5); 6479 /* Power OFF adapter. */ 6480 iwn_apm_stop(sc); 6481 } 6482 6483 static void 6484 iwn_radio_on(void *arg0, int pending) 6485 { 6486 struct iwn_softc *sc = arg0; 6487 struct ifnet *ifp = sc->sc_ifp; 6488 struct ieee80211com *ic = ifp->if_l2com; 6489 struct ieee80211vap *vap = TAILQ_FIRST(&ic->ic_vaps); 6490 6491 if (vap != NULL) { 6492 iwn_init(sc); 6493 ieee80211_init(vap); 6494 } 6495 } 6496 6497 static void 6498 iwn_radio_off(void *arg0, int pending) 6499 { 6500 struct iwn_softc *sc = arg0; 6501 struct ifnet *ifp = sc->sc_ifp; 6502 struct ieee80211com *ic = ifp->if_l2com; 6503 struct ieee80211vap *vap = TAILQ_FIRST(&ic->ic_vaps); 6504 6505 iwn_stop(sc); 6506 if (vap != NULL) 6507 ieee80211_stop(vap); 6508 6509 /* Enable interrupts to get RF toggle notification. */ 6510 IWN_LOCK(sc); 6511 IWN_WRITE(sc, IWN_INT, 0xffffffff); 6512 IWN_WRITE(sc, IWN_INT_MASK, sc->int_mask); 6513 IWN_UNLOCK(sc); 6514 } 6515 6516 static void 6517 iwn_init_locked(struct iwn_softc *sc) 6518 { 6519 struct ifnet *ifp = sc->sc_ifp; 6520 int error; 6521 6522 IWN_LOCK_ASSERT(sc); 6523 6524 if ((error = iwn_hw_prepare(sc)) != 0) { 6525 device_printf(sc->sc_dev, "%s: hardware not ready, error %d\n", 6526 __func__, error); 6527 goto fail; 6528 } 6529 6530 /* Initialize interrupt mask to default value. */ 6531 sc->int_mask = IWN_INT_MASK_DEF; 6532 sc->sc_flags &= ~IWN_FLAG_USE_ICT; 6533 6534 /* Check that the radio is not disabled by hardware switch. */ 6535 if (!(IWN_READ(sc, IWN_GP_CNTRL) & IWN_GP_CNTRL_RFKILL)) { 6536 device_printf(sc->sc_dev, 6537 "radio is disabled by hardware switch\n"); 6538 /* Enable interrupts to get RF toggle notifications. */ 6539 IWN_WRITE(sc, IWN_INT, 0xffffffff); 6540 IWN_WRITE(sc, IWN_INT_MASK, sc->int_mask); 6541 return; 6542 } 6543 6544 /* Read firmware images from the filesystem. */ 6545 if ((error = iwn_read_firmware(sc)) != 0) { 6546 device_printf(sc->sc_dev, 6547 "%s: could not read firmware, error %d\n", __func__, 6548 error); 6549 goto fail; 6550 } 6551 6552 /* Initialize hardware and upload firmware. */ 6553 error = iwn_hw_init(sc); 6554 firmware_put(sc->fw_fp, FIRMWARE_UNLOAD); 6555 sc->fw_fp = NULL; 6556 if (error != 0) { 6557 device_printf(sc->sc_dev, 6558 "%s: could not initialize hardware, error %d\n", __func__, 6559 error); 6560 goto fail; 6561 } 6562 6563 /* Configure adapter now that it is ready. */ 6564 if ((error = iwn_config(sc)) != 0) { 6565 device_printf(sc->sc_dev, 6566 "%s: could not configure device, error %d\n", __func__, 6567 error); 6568 goto fail; 6569 } 6570 6571 ifp->if_drv_flags &= ~IFF_DRV_OACTIVE; 6572 ifp->if_drv_flags |= IFF_DRV_RUNNING; 6573 6574 callout_reset(&sc->watchdog_to, hz, iwn_watchdog, sc); 6575 return; 6576 6577 fail: iwn_stop_locked(sc); 6578 } 6579 6580 static void 6581 iwn_init(void *arg) 6582 { 6583 struct iwn_softc *sc = arg; 6584 struct ifnet *ifp = sc->sc_ifp; 6585 struct ieee80211com *ic = ifp->if_l2com; 6586 6587 IWN_LOCK(sc); 6588 iwn_init_locked(sc); 6589 IWN_UNLOCK(sc); 6590 6591 if (ifp->if_drv_flags & IFF_DRV_RUNNING) 6592 ieee80211_start_all(ic); 6593 } 6594 6595 static void 6596 iwn_stop_locked(struct iwn_softc *sc) 6597 { 6598 struct ifnet *ifp = sc->sc_ifp; 6599 6600 IWN_LOCK_ASSERT(sc); 6601 6602 sc->sc_tx_timer = 0; 6603 callout_stop(&sc->watchdog_to); 6604 callout_stop(&sc->calib_to); 6605 ifp->if_drv_flags &= ~(IFF_DRV_RUNNING | IFF_DRV_OACTIVE); 6606 6607 /* Power OFF hardware. */ 6608 iwn_hw_stop(sc); 6609 } 6610 6611 static void 6612 iwn_stop(struct iwn_softc *sc) 6613 { 6614 IWN_LOCK(sc); 6615 iwn_stop_locked(sc); 6616 IWN_UNLOCK(sc); 6617 } 6618 6619 /* 6620 * Callback from net80211 to start a scan. 6621 */ 6622 static void 6623 iwn_scan_start(struct ieee80211com *ic) 6624 { 6625 struct ifnet *ifp = ic->ic_ifp; 6626 struct iwn_softc *sc = ifp->if_softc; 6627 6628 IWN_LOCK(sc); 6629 /* make the link LED blink while we're scanning */ 6630 iwn_set_led(sc, IWN_LED_LINK, 20, 2); 6631 IWN_UNLOCK(sc); 6632 } 6633 6634 /* 6635 * Callback from net80211 to terminate a scan. 6636 */ 6637 static void 6638 iwn_scan_end(struct ieee80211com *ic) 6639 { 6640 struct ifnet *ifp = ic->ic_ifp; 6641 struct iwn_softc *sc = ifp->if_softc; 6642 struct ieee80211vap *vap = TAILQ_FIRST(&ic->ic_vaps); 6643 6644 IWN_LOCK(sc); 6645 if (vap->iv_state == IEEE80211_S_RUN) { 6646 /* Set link LED to ON status if we are associated */ 6647 iwn_set_led(sc, IWN_LED_LINK, 0, 1); 6648 } 6649 IWN_UNLOCK(sc); 6650 } 6651 6652 /* 6653 * Callback from net80211 to force a channel change. 6654 */ 6655 static void 6656 iwn_set_channel(struct ieee80211com *ic) 6657 { 6658 const struct ieee80211_channel *c = ic->ic_curchan; 6659 struct ifnet *ifp = ic->ic_ifp; 6660 struct iwn_softc *sc = ifp->if_softc; 6661 6662 IWN_LOCK(sc); 6663 sc->sc_rxtap.wr_chan_freq = htole16(c->ic_freq); 6664 sc->sc_rxtap.wr_chan_flags = htole16(c->ic_flags); 6665 sc->sc_txtap.wt_chan_freq = htole16(c->ic_freq); 6666 sc->sc_txtap.wt_chan_flags = htole16(c->ic_flags); 6667 IWN_UNLOCK(sc); 6668 } 6669 6670 /* 6671 * Callback from net80211 to start scanning of the current channel. 6672 */ 6673 static void 6674 iwn_scan_curchan(struct ieee80211_scan_state *ss, unsigned long maxdwell) 6675 { 6676 struct ieee80211vap *vap = ss->ss_vap; 6677 struct iwn_softc *sc = vap->iv_ic->ic_ifp->if_softc; 6678 int error; 6679 6680 IWN_LOCK(sc); 6681 error = iwn_scan(sc); 6682 IWN_UNLOCK(sc); 6683 if (error != 0) 6684 ieee80211_cancel_scan(vap); 6685 } 6686 6687 /* 6688 * Callback from net80211 to handle the minimum dwell time being met. 6689 * The intent is to terminate the scan but we just let the firmware 6690 * notify us when it's finished as we have no safe way to abort it. 6691 */ 6692 static void 6693 iwn_scan_mindwell(struct ieee80211_scan_state *ss) 6694 { 6695 /* NB: don't try to abort scan; wait for firmware to finish */ 6696 } 6697 6698 static void 6699 iwn_hw_reset(void *arg0, int pending) 6700 { 6701 struct iwn_softc *sc = arg0; 6702 struct ifnet *ifp = sc->sc_ifp; 6703 struct ieee80211com *ic = ifp->if_l2com; 6704 6705 iwn_stop(sc); 6706 iwn_init(sc); 6707 ieee80211_notify_radio(ic, 1); 6708 } 6709