1 /*- 2 * Copyright (c) 2007-2009 Damien Bergamini <damien.bergamini@free.fr> 3 * Copyright (c) 2008 Benjamin Close <benjsc@FreeBSD.org> 4 * Copyright (c) 2008 Sam Leffler, Errno Consulting 5 * Copyright (c) 2011 Intel Corporation 6 * Copyright (c) 2013 Cedric GROSS <c.gross@kreiz-it.fr> 7 * Copyright (c) 2013 Adrian Chadd <adrian@FreeBSD.org> 8 * 9 * Permission to use, copy, modify, and distribute this software for any 10 * purpose with or without fee is hereby granted, provided that the above 11 * copyright notice and this permission notice appear in all copies. 12 * 13 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 14 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 15 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR 16 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 17 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN 18 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF 19 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 20 */ 21 22 /* 23 * Driver for Intel WiFi Link 4965 and 1000/5000/6000 Series 802.11 network 24 * adapters. 25 */ 26 27 #include <sys/cdefs.h> 28 __FBSDID("$FreeBSD$"); 29 30 #include "opt_wlan.h" 31 #include "opt_iwn.h" 32 33 #include <sys/param.h> 34 #include <sys/sockio.h> 35 #include <sys/sysctl.h> 36 #include <sys/mbuf.h> 37 #include <sys/kernel.h> 38 #include <sys/socket.h> 39 #include <sys/systm.h> 40 #include <sys/malloc.h> 41 #include <sys/bus.h> 42 #include <sys/conf.h> 43 #include <sys/rman.h> 44 #include <sys/endian.h> 45 #include <sys/firmware.h> 46 #include <sys/limits.h> 47 #include <sys/module.h> 48 #include <sys/priv.h> 49 #include <sys/queue.h> 50 #include <sys/taskqueue.h> 51 52 #include <machine/bus.h> 53 #include <machine/resource.h> 54 #include <machine/clock.h> 55 56 #include <dev/pci/pcireg.h> 57 #include <dev/pci/pcivar.h> 58 59 #include <net/if.h> 60 #include <net/if_var.h> 61 #include <net/if_dl.h> 62 #include <net/if_media.h> 63 64 #include <netinet/in.h> 65 #include <netinet/if_ether.h> 66 67 #include <net80211/ieee80211_var.h> 68 #include <net80211/ieee80211_radiotap.h> 69 #include <net80211/ieee80211_regdomain.h> 70 #include <net80211/ieee80211_ratectl.h> 71 72 #include <dev/iwn/if_iwnreg.h> 73 #include <dev/iwn/if_iwnvar.h> 74 #include <dev/iwn/if_iwn_devid.h> 75 #include <dev/iwn/if_iwn_chip_cfg.h> 76 #include <dev/iwn/if_iwn_debug.h> 77 #include <dev/iwn/if_iwn_ioctl.h> 78 79 struct iwn_ident { 80 uint16_t vendor; 81 uint16_t device; 82 const char *name; 83 }; 84 85 static const struct iwn_ident iwn_ident_table[] = { 86 { 0x8086, IWN_DID_6x05_1, "Intel Centrino Advanced-N 6205" }, 87 { 0x8086, IWN_DID_1000_1, "Intel Centrino Wireless-N 1000" }, 88 { 0x8086, IWN_DID_1000_2, "Intel Centrino Wireless-N 1000" }, 89 { 0x8086, IWN_DID_6x05_2, "Intel Centrino Advanced-N 6205" }, 90 { 0x8086, IWN_DID_6050_1, "Intel Centrino Advanced-N + WiMAX 6250" }, 91 { 0x8086, IWN_DID_6050_2, "Intel Centrino Advanced-N + WiMAX 6250" }, 92 { 0x8086, IWN_DID_x030_1, "Intel Centrino Wireless-N 1030" }, 93 { 0x8086, IWN_DID_x030_2, "Intel Centrino Wireless-N 1030" }, 94 { 0x8086, IWN_DID_x030_3, "Intel Centrino Advanced-N 6230" }, 95 { 0x8086, IWN_DID_x030_4, "Intel Centrino Advanced-N 6230" }, 96 { 0x8086, IWN_DID_6150_1, "Intel Centrino Wireless-N + WiMAX 6150" }, 97 { 0x8086, IWN_DID_6150_2, "Intel Centrino Wireless-N + WiMAX 6150" }, 98 { 0x8086, IWN_DID_2x00_1, "Intel(R) Centrino(R) Wireless-N 2200 BGN" }, 99 { 0x8086, IWN_DID_2x00_2, "Intel(R) Centrino(R) Wireless-N 2200 BGN" }, 100 /* XXX 2200D is IWN_SDID_2x00_4; there's no way to express this here! */ 101 { 0x8086, IWN_DID_2x30_1, "Intel Centrino Wireless-N 2230" }, 102 { 0x8086, IWN_DID_2x30_2, "Intel Centrino Wireless-N 2230" }, 103 { 0x8086, IWN_DID_130_1, "Intel Centrino Wireless-N 130" }, 104 { 0x8086, IWN_DID_130_2, "Intel Centrino Wireless-N 130" }, 105 { 0x8086, IWN_DID_100_1, "Intel Centrino Wireless-N 100" }, 106 { 0x8086, IWN_DID_100_2, "Intel Centrino Wireless-N 100" }, 107 { 0x8086, IWN_DID_105_1, "Intel Centrino Wireless-N 105" }, 108 { 0x8086, IWN_DID_105_2, "Intel Centrino Wireless-N 105" }, 109 { 0x8086, IWN_DID_135_1, "Intel Centrino Wireless-N 135" }, 110 { 0x8086, IWN_DID_135_2, "Intel Centrino Wireless-N 135" }, 111 { 0x8086, IWN_DID_4965_1, "Intel Wireless WiFi Link 4965" }, 112 { 0x8086, IWN_DID_6x00_1, "Intel Centrino Ultimate-N 6300" }, 113 { 0x8086, IWN_DID_6x00_2, "Intel Centrino Advanced-N 6200" }, 114 { 0x8086, IWN_DID_4965_2, "Intel Wireless WiFi Link 4965" }, 115 { 0x8086, IWN_DID_4965_3, "Intel Wireless WiFi Link 4965" }, 116 { 0x8086, IWN_DID_5x00_1, "Intel WiFi Link 5100" }, 117 { 0x8086, IWN_DID_4965_4, "Intel Wireless WiFi Link 4965" }, 118 { 0x8086, IWN_DID_5x00_3, "Intel Ultimate N WiFi Link 5300" }, 119 { 0x8086, IWN_DID_5x00_4, "Intel Ultimate N WiFi Link 5300" }, 120 { 0x8086, IWN_DID_5x00_2, "Intel WiFi Link 5100" }, 121 { 0x8086, IWN_DID_6x00_3, "Intel Centrino Ultimate-N 6300" }, 122 { 0x8086, IWN_DID_6x00_4, "Intel Centrino Advanced-N 6200" }, 123 { 0x8086, IWN_DID_5x50_1, "Intel WiMAX/WiFi Link 5350" }, 124 { 0x8086, IWN_DID_5x50_2, "Intel WiMAX/WiFi Link 5350" }, 125 { 0x8086, IWN_DID_5x50_3, "Intel WiMAX/WiFi Link 5150" }, 126 { 0x8086, IWN_DID_5x50_4, "Intel WiMAX/WiFi Link 5150" }, 127 { 0x8086, IWN_DID_6035_1, "Intel Centrino Advanced 6235" }, 128 { 0x8086, IWN_DID_6035_2, "Intel Centrino Advanced 6235" }, 129 { 0, 0, NULL } 130 }; 131 132 static int iwn_probe(device_t); 133 static int iwn_attach(device_t); 134 static int iwn4965_attach(struct iwn_softc *, uint16_t); 135 static int iwn5000_attach(struct iwn_softc *, uint16_t); 136 static int iwn_config_specific(struct iwn_softc *, uint16_t); 137 static void iwn_radiotap_attach(struct iwn_softc *); 138 static void iwn_sysctlattach(struct iwn_softc *); 139 static struct ieee80211vap *iwn_vap_create(struct ieee80211com *, 140 const char [IFNAMSIZ], int, enum ieee80211_opmode, int, 141 const uint8_t [IEEE80211_ADDR_LEN], 142 const uint8_t [IEEE80211_ADDR_LEN]); 143 static void iwn_vap_delete(struct ieee80211vap *); 144 static int iwn_detach(device_t); 145 static int iwn_shutdown(device_t); 146 static int iwn_suspend(device_t); 147 static int iwn_resume(device_t); 148 static int iwn_nic_lock(struct iwn_softc *); 149 static int iwn_eeprom_lock(struct iwn_softc *); 150 static int iwn_init_otprom(struct iwn_softc *); 151 static int iwn_read_prom_data(struct iwn_softc *, uint32_t, void *, int); 152 static void iwn_dma_map_addr(void *, bus_dma_segment_t *, int, int); 153 static int iwn_dma_contig_alloc(struct iwn_softc *, struct iwn_dma_info *, 154 void **, bus_size_t, bus_size_t); 155 static void iwn_dma_contig_free(struct iwn_dma_info *); 156 static int iwn_alloc_sched(struct iwn_softc *); 157 static void iwn_free_sched(struct iwn_softc *); 158 static int iwn_alloc_kw(struct iwn_softc *); 159 static void iwn_free_kw(struct iwn_softc *); 160 static int iwn_alloc_ict(struct iwn_softc *); 161 static void iwn_free_ict(struct iwn_softc *); 162 static int iwn_alloc_fwmem(struct iwn_softc *); 163 static void iwn_free_fwmem(struct iwn_softc *); 164 static int iwn_alloc_rx_ring(struct iwn_softc *, struct iwn_rx_ring *); 165 static void iwn_reset_rx_ring(struct iwn_softc *, struct iwn_rx_ring *); 166 static void iwn_free_rx_ring(struct iwn_softc *, struct iwn_rx_ring *); 167 static int iwn_alloc_tx_ring(struct iwn_softc *, struct iwn_tx_ring *, 168 int); 169 static void iwn_reset_tx_ring(struct iwn_softc *, struct iwn_tx_ring *); 170 static void iwn_free_tx_ring(struct iwn_softc *, struct iwn_tx_ring *); 171 static void iwn5000_ict_reset(struct iwn_softc *); 172 static int iwn_read_eeprom(struct iwn_softc *, 173 uint8_t macaddr[IEEE80211_ADDR_LEN]); 174 static void iwn4965_read_eeprom(struct iwn_softc *); 175 #ifdef IWN_DEBUG 176 static void iwn4965_print_power_group(struct iwn_softc *, int); 177 #endif 178 static void iwn5000_read_eeprom(struct iwn_softc *); 179 static uint32_t iwn_eeprom_channel_flags(struct iwn_eeprom_chan *); 180 static void iwn_read_eeprom_band(struct iwn_softc *, int); 181 static void iwn_read_eeprom_ht40(struct iwn_softc *, int); 182 static void iwn_read_eeprom_channels(struct iwn_softc *, int, uint32_t); 183 static struct iwn_eeprom_chan *iwn_find_eeprom_channel(struct iwn_softc *, 184 struct ieee80211_channel *); 185 static int iwn_setregdomain(struct ieee80211com *, 186 struct ieee80211_regdomain *, int, 187 struct ieee80211_channel[]); 188 static void iwn_read_eeprom_enhinfo(struct iwn_softc *); 189 static struct ieee80211_node *iwn_node_alloc(struct ieee80211vap *, 190 const uint8_t mac[IEEE80211_ADDR_LEN]); 191 static void iwn_newassoc(struct ieee80211_node *, int); 192 static int iwn_media_change(struct ifnet *); 193 static int iwn_newstate(struct ieee80211vap *, enum ieee80211_state, int); 194 static void iwn_calib_timeout(void *); 195 static void iwn_rx_phy(struct iwn_softc *, struct iwn_rx_desc *, 196 struct iwn_rx_data *); 197 static void iwn_rx_done(struct iwn_softc *, struct iwn_rx_desc *, 198 struct iwn_rx_data *); 199 static void iwn_rx_compressed_ba(struct iwn_softc *, struct iwn_rx_desc *, 200 struct iwn_rx_data *); 201 static void iwn5000_rx_calib_results(struct iwn_softc *, 202 struct iwn_rx_desc *, struct iwn_rx_data *); 203 static void iwn_rx_statistics(struct iwn_softc *, struct iwn_rx_desc *, 204 struct iwn_rx_data *); 205 static void iwn4965_tx_done(struct iwn_softc *, struct iwn_rx_desc *, 206 struct iwn_rx_data *); 207 static void iwn5000_tx_done(struct iwn_softc *, struct iwn_rx_desc *, 208 struct iwn_rx_data *); 209 static void iwn_tx_done(struct iwn_softc *, struct iwn_rx_desc *, int, 210 uint8_t); 211 static void iwn_ampdu_tx_done(struct iwn_softc *, int, int, int, int, void *); 212 static void iwn_cmd_done(struct iwn_softc *, struct iwn_rx_desc *); 213 static void iwn_notif_intr(struct iwn_softc *); 214 static void iwn_wakeup_intr(struct iwn_softc *); 215 static void iwn_rftoggle_intr(struct iwn_softc *); 216 static void iwn_fatal_intr(struct iwn_softc *); 217 static void iwn_intr(void *); 218 static void iwn4965_update_sched(struct iwn_softc *, int, int, uint8_t, 219 uint16_t); 220 static void iwn5000_update_sched(struct iwn_softc *, int, int, uint8_t, 221 uint16_t); 222 #ifdef notyet 223 static void iwn5000_reset_sched(struct iwn_softc *, int, int); 224 #endif 225 static int iwn_tx_data(struct iwn_softc *, struct mbuf *, 226 struct ieee80211_node *); 227 static int iwn_tx_data_raw(struct iwn_softc *, struct mbuf *, 228 struct ieee80211_node *, 229 const struct ieee80211_bpf_params *params); 230 static void iwn_xmit_task(void *arg0, int pending); 231 static int iwn_raw_xmit(struct ieee80211_node *, struct mbuf *, 232 const struct ieee80211_bpf_params *); 233 static int iwn_transmit(struct ieee80211com *, struct mbuf *); 234 static void iwn_watchdog(void *); 235 static int iwn_ioctl(struct ieee80211com *, u_long , void *); 236 static void iwn_parent(struct ieee80211com *); 237 static int iwn_cmd(struct iwn_softc *, int, const void *, int, int); 238 static int iwn4965_add_node(struct iwn_softc *, struct iwn_node_info *, 239 int); 240 static int iwn5000_add_node(struct iwn_softc *, struct iwn_node_info *, 241 int); 242 static int iwn_set_link_quality(struct iwn_softc *, 243 struct ieee80211_node *); 244 static int iwn_add_broadcast_node(struct iwn_softc *, int); 245 static int iwn_updateedca(struct ieee80211com *); 246 static void iwn_update_mcast(struct ieee80211com *); 247 static void iwn_set_led(struct iwn_softc *, uint8_t, uint8_t, uint8_t); 248 static int iwn_set_critical_temp(struct iwn_softc *); 249 static int iwn_set_timing(struct iwn_softc *, struct ieee80211_node *); 250 static void iwn4965_power_calibration(struct iwn_softc *, int); 251 static int iwn4965_set_txpower(struct iwn_softc *, 252 struct ieee80211_channel *, int); 253 static int iwn5000_set_txpower(struct iwn_softc *, 254 struct ieee80211_channel *, int); 255 static int iwn4965_get_rssi(struct iwn_softc *, struct iwn_rx_stat *); 256 static int iwn5000_get_rssi(struct iwn_softc *, struct iwn_rx_stat *); 257 static int iwn_get_noise(const struct iwn_rx_general_stats *); 258 static int iwn4965_get_temperature(struct iwn_softc *); 259 static int iwn5000_get_temperature(struct iwn_softc *); 260 static int iwn_init_sensitivity(struct iwn_softc *); 261 static void iwn_collect_noise(struct iwn_softc *, 262 const struct iwn_rx_general_stats *); 263 static int iwn4965_init_gains(struct iwn_softc *); 264 static int iwn5000_init_gains(struct iwn_softc *); 265 static int iwn4965_set_gains(struct iwn_softc *); 266 static int iwn5000_set_gains(struct iwn_softc *); 267 static void iwn_tune_sensitivity(struct iwn_softc *, 268 const struct iwn_rx_stats *); 269 static void iwn_save_stats_counters(struct iwn_softc *, 270 const struct iwn_stats *); 271 static int iwn_send_sensitivity(struct iwn_softc *); 272 static void iwn_check_rx_recovery(struct iwn_softc *, struct iwn_stats *); 273 static int iwn_set_pslevel(struct iwn_softc *, int, int, int); 274 static int iwn_send_btcoex(struct iwn_softc *); 275 static int iwn_send_advanced_btcoex(struct iwn_softc *); 276 static int iwn5000_runtime_calib(struct iwn_softc *); 277 static int iwn_config(struct iwn_softc *); 278 static int iwn_scan(struct iwn_softc *, struct ieee80211vap *, 279 struct ieee80211_scan_state *, struct ieee80211_channel *); 280 static int iwn_auth(struct iwn_softc *, struct ieee80211vap *vap); 281 static int iwn_run(struct iwn_softc *, struct ieee80211vap *vap); 282 static int iwn_ampdu_rx_start(struct ieee80211_node *, 283 struct ieee80211_rx_ampdu *, int, int, int); 284 static void iwn_ampdu_rx_stop(struct ieee80211_node *, 285 struct ieee80211_rx_ampdu *); 286 static int iwn_addba_request(struct ieee80211_node *, 287 struct ieee80211_tx_ampdu *, int, int, int); 288 static int iwn_addba_response(struct ieee80211_node *, 289 struct ieee80211_tx_ampdu *, int, int, int); 290 static int iwn_ampdu_tx_start(struct ieee80211com *, 291 struct ieee80211_node *, uint8_t); 292 static void iwn_ampdu_tx_stop(struct ieee80211_node *, 293 struct ieee80211_tx_ampdu *); 294 static void iwn4965_ampdu_tx_start(struct iwn_softc *, 295 struct ieee80211_node *, int, uint8_t, uint16_t); 296 static void iwn4965_ampdu_tx_stop(struct iwn_softc *, int, 297 uint8_t, uint16_t); 298 static void iwn5000_ampdu_tx_start(struct iwn_softc *, 299 struct ieee80211_node *, int, uint8_t, uint16_t); 300 static void iwn5000_ampdu_tx_stop(struct iwn_softc *, int, 301 uint8_t, uint16_t); 302 static int iwn5000_query_calibration(struct iwn_softc *); 303 static int iwn5000_send_calibration(struct iwn_softc *); 304 static int iwn5000_send_wimax_coex(struct iwn_softc *); 305 static int iwn5000_crystal_calib(struct iwn_softc *); 306 static int iwn5000_temp_offset_calib(struct iwn_softc *); 307 static int iwn5000_temp_offset_calibv2(struct iwn_softc *); 308 static int iwn4965_post_alive(struct iwn_softc *); 309 static int iwn5000_post_alive(struct iwn_softc *); 310 static int iwn4965_load_bootcode(struct iwn_softc *, const uint8_t *, 311 int); 312 static int iwn4965_load_firmware(struct iwn_softc *); 313 static int iwn5000_load_firmware_section(struct iwn_softc *, uint32_t, 314 const uint8_t *, int); 315 static int iwn5000_load_firmware(struct iwn_softc *); 316 static int iwn_read_firmware_leg(struct iwn_softc *, 317 struct iwn_fw_info *); 318 static int iwn_read_firmware_tlv(struct iwn_softc *, 319 struct iwn_fw_info *, uint16_t); 320 static int iwn_read_firmware(struct iwn_softc *); 321 static int iwn_clock_wait(struct iwn_softc *); 322 static int iwn_apm_init(struct iwn_softc *); 323 static void iwn_apm_stop_master(struct iwn_softc *); 324 static void iwn_apm_stop(struct iwn_softc *); 325 static int iwn4965_nic_config(struct iwn_softc *); 326 static int iwn5000_nic_config(struct iwn_softc *); 327 static int iwn_hw_prepare(struct iwn_softc *); 328 static int iwn_hw_init(struct iwn_softc *); 329 static void iwn_hw_stop(struct iwn_softc *); 330 static void iwn_radio_on(void *, int); 331 static void iwn_radio_off(void *, int); 332 static void iwn_panicked(void *, int); 333 static void iwn_init_locked(struct iwn_softc *); 334 static void iwn_init(struct iwn_softc *); 335 static void iwn_stop_locked(struct iwn_softc *); 336 static void iwn_stop(struct iwn_softc *); 337 static void iwn_scan_start(struct ieee80211com *); 338 static void iwn_scan_end(struct ieee80211com *); 339 static void iwn_set_channel(struct ieee80211com *); 340 static void iwn_scan_curchan(struct ieee80211_scan_state *, unsigned long); 341 static void iwn_scan_mindwell(struct ieee80211_scan_state *); 342 static void iwn_hw_reset(void *, int); 343 #ifdef IWN_DEBUG 344 static char *iwn_get_csr_string(int); 345 static void iwn_debug_register(struct iwn_softc *); 346 #endif 347 348 static device_method_t iwn_methods[] = { 349 /* Device interface */ 350 DEVMETHOD(device_probe, iwn_probe), 351 DEVMETHOD(device_attach, iwn_attach), 352 DEVMETHOD(device_detach, iwn_detach), 353 DEVMETHOD(device_shutdown, iwn_shutdown), 354 DEVMETHOD(device_suspend, iwn_suspend), 355 DEVMETHOD(device_resume, iwn_resume), 356 357 DEVMETHOD_END 358 }; 359 360 static driver_t iwn_driver = { 361 "iwn", 362 iwn_methods, 363 sizeof(struct iwn_softc) 364 }; 365 static devclass_t iwn_devclass; 366 367 DRIVER_MODULE(iwn, pci, iwn_driver, iwn_devclass, NULL, NULL); 368 369 MODULE_VERSION(iwn, 1); 370 371 MODULE_DEPEND(iwn, firmware, 1, 1, 1); 372 MODULE_DEPEND(iwn, pci, 1, 1, 1); 373 MODULE_DEPEND(iwn, wlan, 1, 1, 1); 374 375 static d_ioctl_t iwn_cdev_ioctl; 376 static d_open_t iwn_cdev_open; 377 static d_close_t iwn_cdev_close; 378 379 static struct cdevsw iwn_cdevsw = { 380 .d_version = D_VERSION, 381 .d_flags = 0, 382 .d_open = iwn_cdev_open, 383 .d_close = iwn_cdev_close, 384 .d_ioctl = iwn_cdev_ioctl, 385 .d_name = "iwn", 386 }; 387 388 static int 389 iwn_probe(device_t dev) 390 { 391 const struct iwn_ident *ident; 392 393 for (ident = iwn_ident_table; ident->name != NULL; ident++) { 394 if (pci_get_vendor(dev) == ident->vendor && 395 pci_get_device(dev) == ident->device) { 396 device_set_desc(dev, ident->name); 397 return (BUS_PROBE_DEFAULT); 398 } 399 } 400 return ENXIO; 401 } 402 403 static int 404 iwn_is_3stream_device(struct iwn_softc *sc) 405 { 406 /* XXX for now only 5300, until the 5350 can be tested */ 407 if (sc->hw_type == IWN_HW_REV_TYPE_5300) 408 return (1); 409 return (0); 410 } 411 412 static int 413 iwn_attach(device_t dev) 414 { 415 struct iwn_softc *sc = (struct iwn_softc *)device_get_softc(dev); 416 struct ieee80211com *ic; 417 int i, error, rid; 418 419 sc->sc_dev = dev; 420 421 #ifdef IWN_DEBUG 422 error = resource_int_value(device_get_name(sc->sc_dev), 423 device_get_unit(sc->sc_dev), "debug", &(sc->sc_debug)); 424 if (error != 0) 425 sc->sc_debug = 0; 426 #else 427 sc->sc_debug = 0; 428 #endif 429 430 DPRINTF(sc, IWN_DEBUG_TRACE, "->%s: begin\n",__func__); 431 432 /* 433 * Get the offset of the PCI Express Capability Structure in PCI 434 * Configuration Space. 435 */ 436 error = pci_find_cap(dev, PCIY_EXPRESS, &sc->sc_cap_off); 437 if (error != 0) { 438 device_printf(dev, "PCIe capability structure not found!\n"); 439 return error; 440 } 441 442 /* Clear device-specific "PCI retry timeout" register (41h). */ 443 pci_write_config(dev, 0x41, 0, 1); 444 445 /* Enable bus-mastering. */ 446 pci_enable_busmaster(dev); 447 448 rid = PCIR_BAR(0); 449 sc->mem = bus_alloc_resource_any(dev, SYS_RES_MEMORY, &rid, 450 RF_ACTIVE); 451 if (sc->mem == NULL) { 452 device_printf(dev, "can't map mem space\n"); 453 error = ENOMEM; 454 return error; 455 } 456 sc->sc_st = rman_get_bustag(sc->mem); 457 sc->sc_sh = rman_get_bushandle(sc->mem); 458 459 i = 1; 460 rid = 0; 461 if (pci_alloc_msi(dev, &i) == 0) 462 rid = 1; 463 /* Install interrupt handler. */ 464 sc->irq = bus_alloc_resource_any(dev, SYS_RES_IRQ, &rid, RF_ACTIVE | 465 (rid != 0 ? 0 : RF_SHAREABLE)); 466 if (sc->irq == NULL) { 467 device_printf(dev, "can't map interrupt\n"); 468 error = ENOMEM; 469 goto fail; 470 } 471 472 IWN_LOCK_INIT(sc); 473 474 /* Read hardware revision and attach. */ 475 sc->hw_type = (IWN_READ(sc, IWN_HW_REV) >> IWN_HW_REV_TYPE_SHIFT) 476 & IWN_HW_REV_TYPE_MASK; 477 sc->subdevice_id = pci_get_subdevice(dev); 478 479 /* 480 * 4965 versus 5000 and later have different methods. 481 * Let's set those up first. 482 */ 483 if (sc->hw_type == IWN_HW_REV_TYPE_4965) 484 error = iwn4965_attach(sc, pci_get_device(dev)); 485 else 486 error = iwn5000_attach(sc, pci_get_device(dev)); 487 if (error != 0) { 488 device_printf(dev, "could not attach device, error %d\n", 489 error); 490 goto fail; 491 } 492 493 /* 494 * Next, let's setup the various parameters of each NIC. 495 */ 496 error = iwn_config_specific(sc, pci_get_device(dev)); 497 if (error != 0) { 498 device_printf(dev, "could not attach device, error %d\n", 499 error); 500 goto fail; 501 } 502 503 if ((error = iwn_hw_prepare(sc)) != 0) { 504 device_printf(dev, "hardware not ready, error %d\n", error); 505 goto fail; 506 } 507 508 /* Allocate DMA memory for firmware transfers. */ 509 if ((error = iwn_alloc_fwmem(sc)) != 0) { 510 device_printf(dev, 511 "could not allocate memory for firmware, error %d\n", 512 error); 513 goto fail; 514 } 515 516 /* Allocate "Keep Warm" page. */ 517 if ((error = iwn_alloc_kw(sc)) != 0) { 518 device_printf(dev, 519 "could not allocate keep warm page, error %d\n", error); 520 goto fail; 521 } 522 523 /* Allocate ICT table for 5000 Series. */ 524 if (sc->hw_type != IWN_HW_REV_TYPE_4965 && 525 (error = iwn_alloc_ict(sc)) != 0) { 526 device_printf(dev, "could not allocate ICT table, error %d\n", 527 error); 528 goto fail; 529 } 530 531 /* Allocate TX scheduler "rings". */ 532 if ((error = iwn_alloc_sched(sc)) != 0) { 533 device_printf(dev, 534 "could not allocate TX scheduler rings, error %d\n", error); 535 goto fail; 536 } 537 538 /* Allocate TX rings (16 on 4965AGN, 20 on >=5000). */ 539 for (i = 0; i < sc->ntxqs; i++) { 540 if ((error = iwn_alloc_tx_ring(sc, &sc->txq[i], i)) != 0) { 541 device_printf(dev, 542 "could not allocate TX ring %d, error %d\n", i, 543 error); 544 goto fail; 545 } 546 } 547 548 /* Allocate RX ring. */ 549 if ((error = iwn_alloc_rx_ring(sc, &sc->rxq)) != 0) { 550 device_printf(dev, "could not allocate RX ring, error %d\n", 551 error); 552 goto fail; 553 } 554 555 /* Clear pending interrupts. */ 556 IWN_WRITE(sc, IWN_INT, 0xffffffff); 557 558 ic = &sc->sc_ic; 559 ic->ic_softc = sc; 560 ic->ic_name = device_get_nameunit(dev); 561 ic->ic_phytype = IEEE80211_T_OFDM; /* not only, but not used */ 562 ic->ic_opmode = IEEE80211_M_STA; /* default to BSS mode */ 563 564 /* Set device capabilities. */ 565 ic->ic_caps = 566 IEEE80211_C_STA /* station mode supported */ 567 | IEEE80211_C_MONITOR /* monitor mode supported */ 568 #if 0 569 | IEEE80211_C_BGSCAN /* background scanning */ 570 #endif 571 | IEEE80211_C_TXPMGT /* tx power management */ 572 | IEEE80211_C_SHSLOT /* short slot time supported */ 573 | IEEE80211_C_WPA 574 | IEEE80211_C_SHPREAMBLE /* short preamble supported */ 575 #if 0 576 | IEEE80211_C_IBSS /* ibss/adhoc mode */ 577 #endif 578 | IEEE80211_C_WME /* WME */ 579 | IEEE80211_C_PMGT /* Station-side power mgmt */ 580 ; 581 582 /* Read MAC address, channels, etc from EEPROM. */ 583 if ((error = iwn_read_eeprom(sc, ic->ic_macaddr)) != 0) { 584 device_printf(dev, "could not read EEPROM, error %d\n", 585 error); 586 goto fail; 587 } 588 589 /* Count the number of available chains. */ 590 sc->ntxchains = 591 ((sc->txchainmask >> 2) & 1) + 592 ((sc->txchainmask >> 1) & 1) + 593 ((sc->txchainmask >> 0) & 1); 594 sc->nrxchains = 595 ((sc->rxchainmask >> 2) & 1) + 596 ((sc->rxchainmask >> 1) & 1) + 597 ((sc->rxchainmask >> 0) & 1); 598 if (bootverbose) { 599 device_printf(dev, "MIMO %dT%dR, %.4s, address %6D\n", 600 sc->ntxchains, sc->nrxchains, sc->eeprom_domain, 601 ic->ic_macaddr, ":"); 602 } 603 604 if (sc->sc_flags & IWN_FLAG_HAS_11N) { 605 ic->ic_rxstream = sc->nrxchains; 606 ic->ic_txstream = sc->ntxchains; 607 608 /* 609 * Some of the 3 antenna devices (ie, the 4965) only supports 610 * 2x2 operation. So correct the number of streams if 611 * it's not a 3-stream device. 612 */ 613 if (! iwn_is_3stream_device(sc)) { 614 if (ic->ic_rxstream > 2) 615 ic->ic_rxstream = 2; 616 if (ic->ic_txstream > 2) 617 ic->ic_txstream = 2; 618 } 619 620 ic->ic_htcaps = 621 IEEE80211_HTCAP_SMPS_OFF /* SMPS mode disabled */ 622 | IEEE80211_HTCAP_SHORTGI20 /* short GI in 20MHz */ 623 | IEEE80211_HTCAP_CHWIDTH40 /* 40MHz channel width*/ 624 | IEEE80211_HTCAP_SHORTGI40 /* short GI in 40MHz */ 625 #ifdef notyet 626 | IEEE80211_HTCAP_GREENFIELD 627 #if IWN_RBUF_SIZE == 8192 628 | IEEE80211_HTCAP_MAXAMSDU_7935 /* max A-MSDU length */ 629 #else 630 | IEEE80211_HTCAP_MAXAMSDU_3839 /* max A-MSDU length */ 631 #endif 632 #endif 633 /* s/w capabilities */ 634 | IEEE80211_HTC_HT /* HT operation */ 635 | IEEE80211_HTC_AMPDU /* tx A-MPDU */ 636 #ifdef notyet 637 | IEEE80211_HTC_AMSDU /* tx A-MSDU */ 638 #endif 639 ; 640 } 641 642 ieee80211_ifattach(ic); 643 ic->ic_vap_create = iwn_vap_create; 644 ic->ic_ioctl = iwn_ioctl; 645 ic->ic_parent = iwn_parent; 646 ic->ic_vap_delete = iwn_vap_delete; 647 ic->ic_transmit = iwn_transmit; 648 ic->ic_raw_xmit = iwn_raw_xmit; 649 ic->ic_node_alloc = iwn_node_alloc; 650 sc->sc_ampdu_rx_start = ic->ic_ampdu_rx_start; 651 ic->ic_ampdu_rx_start = iwn_ampdu_rx_start; 652 sc->sc_ampdu_rx_stop = ic->ic_ampdu_rx_stop; 653 ic->ic_ampdu_rx_stop = iwn_ampdu_rx_stop; 654 sc->sc_addba_request = ic->ic_addba_request; 655 ic->ic_addba_request = iwn_addba_request; 656 sc->sc_addba_response = ic->ic_addba_response; 657 ic->ic_addba_response = iwn_addba_response; 658 sc->sc_addba_stop = ic->ic_addba_stop; 659 ic->ic_addba_stop = iwn_ampdu_tx_stop; 660 ic->ic_newassoc = iwn_newassoc; 661 ic->ic_wme.wme_update = iwn_updateedca; 662 ic->ic_update_mcast = iwn_update_mcast; 663 ic->ic_scan_start = iwn_scan_start; 664 ic->ic_scan_end = iwn_scan_end; 665 ic->ic_set_channel = iwn_set_channel; 666 ic->ic_scan_curchan = iwn_scan_curchan; 667 ic->ic_scan_mindwell = iwn_scan_mindwell; 668 ic->ic_setregdomain = iwn_setregdomain; 669 670 iwn_radiotap_attach(sc); 671 672 callout_init_mtx(&sc->calib_to, &sc->sc_mtx, 0); 673 callout_init_mtx(&sc->watchdog_to, &sc->sc_mtx, 0); 674 TASK_INIT(&sc->sc_reinit_task, 0, iwn_hw_reset, sc); 675 TASK_INIT(&sc->sc_radioon_task, 0, iwn_radio_on, sc); 676 TASK_INIT(&sc->sc_radiooff_task, 0, iwn_radio_off, sc); 677 TASK_INIT(&sc->sc_panic_task, 0, iwn_panicked, sc); 678 TASK_INIT(&sc->sc_xmit_task, 0, iwn_xmit_task, sc); 679 680 mbufq_init(&sc->sc_xmit_queue, 1024); 681 682 sc->sc_tq = taskqueue_create("iwn_taskq", M_WAITOK, 683 taskqueue_thread_enqueue, &sc->sc_tq); 684 error = taskqueue_start_threads(&sc->sc_tq, 1, 0, "iwn_taskq"); 685 if (error != 0) { 686 device_printf(dev, "can't start threads, error %d\n", error); 687 goto fail; 688 } 689 690 iwn_sysctlattach(sc); 691 692 /* 693 * Hook our interrupt after all initialization is complete. 694 */ 695 error = bus_setup_intr(dev, sc->irq, INTR_TYPE_NET | INTR_MPSAFE, 696 NULL, iwn_intr, sc, &sc->sc_ih); 697 if (error != 0) { 698 device_printf(dev, "can't establish interrupt, error %d\n", 699 error); 700 goto fail; 701 } 702 703 #if 0 704 device_printf(sc->sc_dev, "%s: rx_stats=%d, rx_stats_bt=%d\n", 705 __func__, 706 sizeof(struct iwn_stats), 707 sizeof(struct iwn_stats_bt)); 708 #endif 709 710 if (bootverbose) 711 ieee80211_announce(ic); 712 DPRINTF(sc, IWN_DEBUG_TRACE, "->%s: end\n",__func__); 713 714 /* Add debug ioctl right at the end */ 715 sc->sc_cdev = make_dev(&iwn_cdevsw, device_get_unit(dev), 716 UID_ROOT, GID_WHEEL, 0600, "%s", device_get_nameunit(dev)); 717 if (sc->sc_cdev == NULL) { 718 device_printf(dev, "failed to create debug character device\n"); 719 } else { 720 sc->sc_cdev->si_drv1 = sc; 721 } 722 return 0; 723 fail: 724 iwn_detach(dev); 725 DPRINTF(sc, IWN_DEBUG_TRACE, "->%s: end in error\n",__func__); 726 return error; 727 } 728 729 /* 730 * Define specific configuration based on device id and subdevice id 731 * pid : PCI device id 732 */ 733 static int 734 iwn_config_specific(struct iwn_softc *sc, uint16_t pid) 735 { 736 737 switch (pid) { 738 /* 4965 series */ 739 case IWN_DID_4965_1: 740 case IWN_DID_4965_2: 741 case IWN_DID_4965_3: 742 case IWN_DID_4965_4: 743 sc->base_params = &iwn4965_base_params; 744 sc->limits = &iwn4965_sensitivity_limits; 745 sc->fwname = "iwn4965fw"; 746 /* Override chains masks, ROM is known to be broken. */ 747 sc->txchainmask = IWN_ANT_AB; 748 sc->rxchainmask = IWN_ANT_ABC; 749 /* Enable normal btcoex */ 750 sc->sc_flags |= IWN_FLAG_BTCOEX; 751 break; 752 /* 1000 Series */ 753 case IWN_DID_1000_1: 754 case IWN_DID_1000_2: 755 switch(sc->subdevice_id) { 756 case IWN_SDID_1000_1: 757 case IWN_SDID_1000_2: 758 case IWN_SDID_1000_3: 759 case IWN_SDID_1000_4: 760 case IWN_SDID_1000_5: 761 case IWN_SDID_1000_6: 762 case IWN_SDID_1000_7: 763 case IWN_SDID_1000_8: 764 case IWN_SDID_1000_9: 765 case IWN_SDID_1000_10: 766 case IWN_SDID_1000_11: 767 case IWN_SDID_1000_12: 768 sc->limits = &iwn1000_sensitivity_limits; 769 sc->base_params = &iwn1000_base_params; 770 sc->fwname = "iwn1000fw"; 771 break; 772 default: 773 device_printf(sc->sc_dev, "adapter type id : 0x%04x sub id :" 774 "0x%04x rev %d not supported (subdevice)\n", pid, 775 sc->subdevice_id,sc->hw_type); 776 return ENOTSUP; 777 } 778 break; 779 /* 6x00 Series */ 780 case IWN_DID_6x00_2: 781 case IWN_DID_6x00_4: 782 case IWN_DID_6x00_1: 783 case IWN_DID_6x00_3: 784 sc->fwname = "iwn6000fw"; 785 sc->limits = &iwn6000_sensitivity_limits; 786 switch(sc->subdevice_id) { 787 case IWN_SDID_6x00_1: 788 case IWN_SDID_6x00_2: 789 case IWN_SDID_6x00_8: 790 //iwl6000_3agn_cfg 791 sc->base_params = &iwn_6000_base_params; 792 break; 793 case IWN_SDID_6x00_3: 794 case IWN_SDID_6x00_6: 795 case IWN_SDID_6x00_9: 796 ////iwl6000i_2agn 797 case IWN_SDID_6x00_4: 798 case IWN_SDID_6x00_7: 799 case IWN_SDID_6x00_10: 800 //iwl6000i_2abg_cfg 801 case IWN_SDID_6x00_5: 802 //iwl6000i_2bg_cfg 803 sc->base_params = &iwn_6000i_base_params; 804 sc->sc_flags |= IWN_FLAG_INTERNAL_PA; 805 sc->txchainmask = IWN_ANT_BC; 806 sc->rxchainmask = IWN_ANT_BC; 807 break; 808 default: 809 device_printf(sc->sc_dev, "adapter type id : 0x%04x sub id :" 810 "0x%04x rev %d not supported (subdevice)\n", pid, 811 sc->subdevice_id,sc->hw_type); 812 return ENOTSUP; 813 } 814 break; 815 /* 6x05 Series */ 816 case IWN_DID_6x05_1: 817 case IWN_DID_6x05_2: 818 switch(sc->subdevice_id) { 819 case IWN_SDID_6x05_1: 820 case IWN_SDID_6x05_4: 821 case IWN_SDID_6x05_6: 822 //iwl6005_2agn_cfg 823 case IWN_SDID_6x05_2: 824 case IWN_SDID_6x05_5: 825 case IWN_SDID_6x05_7: 826 //iwl6005_2abg_cfg 827 case IWN_SDID_6x05_3: 828 //iwl6005_2bg_cfg 829 case IWN_SDID_6x05_8: 830 case IWN_SDID_6x05_9: 831 //iwl6005_2agn_sff_cfg 832 case IWN_SDID_6x05_10: 833 //iwl6005_2agn_d_cfg 834 case IWN_SDID_6x05_11: 835 //iwl6005_2agn_mow1_cfg 836 case IWN_SDID_6x05_12: 837 //iwl6005_2agn_mow2_cfg 838 sc->fwname = "iwn6000g2afw"; 839 sc->limits = &iwn6000_sensitivity_limits; 840 sc->base_params = &iwn_6000g2_base_params; 841 break; 842 default: 843 device_printf(sc->sc_dev, "adapter type id : 0x%04x sub id :" 844 "0x%04x rev %d not supported (subdevice)\n", pid, 845 sc->subdevice_id,sc->hw_type); 846 return ENOTSUP; 847 } 848 break; 849 /* 6x35 Series */ 850 case IWN_DID_6035_1: 851 case IWN_DID_6035_2: 852 switch(sc->subdevice_id) { 853 case IWN_SDID_6035_1: 854 case IWN_SDID_6035_2: 855 case IWN_SDID_6035_3: 856 case IWN_SDID_6035_4: 857 sc->fwname = "iwn6000g2bfw"; 858 sc->limits = &iwn6235_sensitivity_limits; 859 sc->base_params = &iwn_6235_base_params; 860 break; 861 default: 862 device_printf(sc->sc_dev, "adapter type id : 0x%04x sub id :" 863 "0x%04x rev %d not supported (subdevice)\n", pid, 864 sc->subdevice_id,sc->hw_type); 865 return ENOTSUP; 866 } 867 break; 868 /* 6x50 WiFi/WiMax Series */ 869 case IWN_DID_6050_1: 870 case IWN_DID_6050_2: 871 switch(sc->subdevice_id) { 872 case IWN_SDID_6050_1: 873 case IWN_SDID_6050_3: 874 case IWN_SDID_6050_5: 875 //iwl6050_2agn_cfg 876 case IWN_SDID_6050_2: 877 case IWN_SDID_6050_4: 878 case IWN_SDID_6050_6: 879 //iwl6050_2abg_cfg 880 sc->fwname = "iwn6050fw"; 881 sc->txchainmask = IWN_ANT_AB; 882 sc->rxchainmask = IWN_ANT_AB; 883 sc->limits = &iwn6000_sensitivity_limits; 884 sc->base_params = &iwn_6050_base_params; 885 break; 886 default: 887 device_printf(sc->sc_dev, "adapter type id : 0x%04x sub id :" 888 "0x%04x rev %d not supported (subdevice)\n", pid, 889 sc->subdevice_id,sc->hw_type); 890 return ENOTSUP; 891 } 892 break; 893 /* 6150 WiFi/WiMax Series */ 894 case IWN_DID_6150_1: 895 case IWN_DID_6150_2: 896 switch(sc->subdevice_id) { 897 case IWN_SDID_6150_1: 898 case IWN_SDID_6150_3: 899 case IWN_SDID_6150_5: 900 // iwl6150_bgn_cfg 901 case IWN_SDID_6150_2: 902 case IWN_SDID_6150_4: 903 case IWN_SDID_6150_6: 904 //iwl6150_bg_cfg 905 sc->fwname = "iwn6050fw"; 906 sc->limits = &iwn6000_sensitivity_limits; 907 sc->base_params = &iwn_6150_base_params; 908 break; 909 default: 910 device_printf(sc->sc_dev, "adapter type id : 0x%04x sub id :" 911 "0x%04x rev %d not supported (subdevice)\n", pid, 912 sc->subdevice_id,sc->hw_type); 913 return ENOTSUP; 914 } 915 break; 916 /* 6030 Series and 1030 Series */ 917 case IWN_DID_x030_1: 918 case IWN_DID_x030_2: 919 case IWN_DID_x030_3: 920 case IWN_DID_x030_4: 921 switch(sc->subdevice_id) { 922 case IWN_SDID_x030_1: 923 case IWN_SDID_x030_3: 924 case IWN_SDID_x030_5: 925 // iwl1030_bgn_cfg 926 case IWN_SDID_x030_2: 927 case IWN_SDID_x030_4: 928 case IWN_SDID_x030_6: 929 //iwl1030_bg_cfg 930 case IWN_SDID_x030_7: 931 case IWN_SDID_x030_10: 932 case IWN_SDID_x030_14: 933 //iwl6030_2agn_cfg 934 case IWN_SDID_x030_8: 935 case IWN_SDID_x030_11: 936 case IWN_SDID_x030_15: 937 // iwl6030_2bgn_cfg 938 case IWN_SDID_x030_9: 939 case IWN_SDID_x030_12: 940 case IWN_SDID_x030_16: 941 // iwl6030_2abg_cfg 942 case IWN_SDID_x030_13: 943 //iwl6030_2bg_cfg 944 sc->fwname = "iwn6000g2bfw"; 945 sc->limits = &iwn6000_sensitivity_limits; 946 sc->base_params = &iwn_6000g2b_base_params; 947 break; 948 default: 949 device_printf(sc->sc_dev, "adapter type id : 0x%04x sub id :" 950 "0x%04x rev %d not supported (subdevice)\n", pid, 951 sc->subdevice_id,sc->hw_type); 952 return ENOTSUP; 953 } 954 break; 955 /* 130 Series WiFi */ 956 /* XXX: This series will need adjustment for rate. 957 * see rx_with_siso_diversity in linux kernel 958 */ 959 case IWN_DID_130_1: 960 case IWN_DID_130_2: 961 switch(sc->subdevice_id) { 962 case IWN_SDID_130_1: 963 case IWN_SDID_130_3: 964 case IWN_SDID_130_5: 965 //iwl130_bgn_cfg 966 case IWN_SDID_130_2: 967 case IWN_SDID_130_4: 968 case IWN_SDID_130_6: 969 //iwl130_bg_cfg 970 sc->fwname = "iwn6000g2bfw"; 971 sc->limits = &iwn6000_sensitivity_limits; 972 sc->base_params = &iwn_6000g2b_base_params; 973 break; 974 default: 975 device_printf(sc->sc_dev, "adapter type id : 0x%04x sub id :" 976 "0x%04x rev %d not supported (subdevice)\n", pid, 977 sc->subdevice_id,sc->hw_type); 978 return ENOTSUP; 979 } 980 break; 981 /* 100 Series WiFi */ 982 case IWN_DID_100_1: 983 case IWN_DID_100_2: 984 switch(sc->subdevice_id) { 985 case IWN_SDID_100_1: 986 case IWN_SDID_100_2: 987 case IWN_SDID_100_3: 988 case IWN_SDID_100_4: 989 case IWN_SDID_100_5: 990 case IWN_SDID_100_6: 991 sc->limits = &iwn1000_sensitivity_limits; 992 sc->base_params = &iwn1000_base_params; 993 sc->fwname = "iwn100fw"; 994 break; 995 default: 996 device_printf(sc->sc_dev, "adapter type id : 0x%04x sub id :" 997 "0x%04x rev %d not supported (subdevice)\n", pid, 998 sc->subdevice_id,sc->hw_type); 999 return ENOTSUP; 1000 } 1001 break; 1002 1003 /* 105 Series */ 1004 /* XXX: This series will need adjustment for rate. 1005 * see rx_with_siso_diversity in linux kernel 1006 */ 1007 case IWN_DID_105_1: 1008 case IWN_DID_105_2: 1009 switch(sc->subdevice_id) { 1010 case IWN_SDID_105_1: 1011 case IWN_SDID_105_2: 1012 case IWN_SDID_105_3: 1013 //iwl105_bgn_cfg 1014 case IWN_SDID_105_4: 1015 //iwl105_bgn_d_cfg 1016 sc->limits = &iwn2030_sensitivity_limits; 1017 sc->base_params = &iwn2000_base_params; 1018 sc->fwname = "iwn105fw"; 1019 break; 1020 default: 1021 device_printf(sc->sc_dev, "adapter type id : 0x%04x sub id :" 1022 "0x%04x rev %d not supported (subdevice)\n", pid, 1023 sc->subdevice_id,sc->hw_type); 1024 return ENOTSUP; 1025 } 1026 break; 1027 1028 /* 135 Series */ 1029 /* XXX: This series will need adjustment for rate. 1030 * see rx_with_siso_diversity in linux kernel 1031 */ 1032 case IWN_DID_135_1: 1033 case IWN_DID_135_2: 1034 switch(sc->subdevice_id) { 1035 case IWN_SDID_135_1: 1036 case IWN_SDID_135_2: 1037 case IWN_SDID_135_3: 1038 sc->limits = &iwn2030_sensitivity_limits; 1039 sc->base_params = &iwn2030_base_params; 1040 sc->fwname = "iwn135fw"; 1041 break; 1042 default: 1043 device_printf(sc->sc_dev, "adapter type id : 0x%04x sub id :" 1044 "0x%04x rev %d not supported (subdevice)\n", pid, 1045 sc->subdevice_id,sc->hw_type); 1046 return ENOTSUP; 1047 } 1048 break; 1049 1050 /* 2x00 Series */ 1051 case IWN_DID_2x00_1: 1052 case IWN_DID_2x00_2: 1053 switch(sc->subdevice_id) { 1054 case IWN_SDID_2x00_1: 1055 case IWN_SDID_2x00_2: 1056 case IWN_SDID_2x00_3: 1057 //iwl2000_2bgn_cfg 1058 case IWN_SDID_2x00_4: 1059 //iwl2000_2bgn_d_cfg 1060 sc->limits = &iwn2030_sensitivity_limits; 1061 sc->base_params = &iwn2000_base_params; 1062 sc->fwname = "iwn2000fw"; 1063 break; 1064 default: 1065 device_printf(sc->sc_dev, "adapter type id : 0x%04x sub id :" 1066 "0x%04x rev %d not supported (subdevice) \n", 1067 pid, sc->subdevice_id, sc->hw_type); 1068 return ENOTSUP; 1069 } 1070 break; 1071 /* 2x30 Series */ 1072 case IWN_DID_2x30_1: 1073 case IWN_DID_2x30_2: 1074 switch(sc->subdevice_id) { 1075 case IWN_SDID_2x30_1: 1076 case IWN_SDID_2x30_3: 1077 case IWN_SDID_2x30_5: 1078 //iwl100_bgn_cfg 1079 case IWN_SDID_2x30_2: 1080 case IWN_SDID_2x30_4: 1081 case IWN_SDID_2x30_6: 1082 //iwl100_bg_cfg 1083 sc->limits = &iwn2030_sensitivity_limits; 1084 sc->base_params = &iwn2030_base_params; 1085 sc->fwname = "iwn2030fw"; 1086 break; 1087 default: 1088 device_printf(sc->sc_dev, "adapter type id : 0x%04x sub id :" 1089 "0x%04x rev %d not supported (subdevice)\n", pid, 1090 sc->subdevice_id,sc->hw_type); 1091 return ENOTSUP; 1092 } 1093 break; 1094 /* 5x00 Series */ 1095 case IWN_DID_5x00_1: 1096 case IWN_DID_5x00_2: 1097 case IWN_DID_5x00_3: 1098 case IWN_DID_5x00_4: 1099 sc->limits = &iwn5000_sensitivity_limits; 1100 sc->base_params = &iwn5000_base_params; 1101 sc->fwname = "iwn5000fw"; 1102 switch(sc->subdevice_id) { 1103 case IWN_SDID_5x00_1: 1104 case IWN_SDID_5x00_2: 1105 case IWN_SDID_5x00_3: 1106 case IWN_SDID_5x00_4: 1107 case IWN_SDID_5x00_9: 1108 case IWN_SDID_5x00_10: 1109 case IWN_SDID_5x00_11: 1110 case IWN_SDID_5x00_12: 1111 case IWN_SDID_5x00_17: 1112 case IWN_SDID_5x00_18: 1113 case IWN_SDID_5x00_19: 1114 case IWN_SDID_5x00_20: 1115 //iwl5100_agn_cfg 1116 sc->txchainmask = IWN_ANT_B; 1117 sc->rxchainmask = IWN_ANT_AB; 1118 break; 1119 case IWN_SDID_5x00_5: 1120 case IWN_SDID_5x00_6: 1121 case IWN_SDID_5x00_13: 1122 case IWN_SDID_5x00_14: 1123 case IWN_SDID_5x00_21: 1124 case IWN_SDID_5x00_22: 1125 //iwl5100_bgn_cfg 1126 sc->txchainmask = IWN_ANT_B; 1127 sc->rxchainmask = IWN_ANT_AB; 1128 break; 1129 case IWN_SDID_5x00_7: 1130 case IWN_SDID_5x00_8: 1131 case IWN_SDID_5x00_15: 1132 case IWN_SDID_5x00_16: 1133 case IWN_SDID_5x00_23: 1134 case IWN_SDID_5x00_24: 1135 //iwl5100_abg_cfg 1136 sc->txchainmask = IWN_ANT_B; 1137 sc->rxchainmask = IWN_ANT_AB; 1138 break; 1139 case IWN_SDID_5x00_25: 1140 case IWN_SDID_5x00_26: 1141 case IWN_SDID_5x00_27: 1142 case IWN_SDID_5x00_28: 1143 case IWN_SDID_5x00_29: 1144 case IWN_SDID_5x00_30: 1145 case IWN_SDID_5x00_31: 1146 case IWN_SDID_5x00_32: 1147 case IWN_SDID_5x00_33: 1148 case IWN_SDID_5x00_34: 1149 case IWN_SDID_5x00_35: 1150 case IWN_SDID_5x00_36: 1151 //iwl5300_agn_cfg 1152 sc->txchainmask = IWN_ANT_ABC; 1153 sc->rxchainmask = IWN_ANT_ABC; 1154 break; 1155 default: 1156 device_printf(sc->sc_dev, "adapter type id : 0x%04x sub id :" 1157 "0x%04x rev %d not supported (subdevice)\n", pid, 1158 sc->subdevice_id,sc->hw_type); 1159 return ENOTSUP; 1160 } 1161 break; 1162 /* 5x50 Series */ 1163 case IWN_DID_5x50_1: 1164 case IWN_DID_5x50_2: 1165 case IWN_DID_5x50_3: 1166 case IWN_DID_5x50_4: 1167 sc->limits = &iwn5000_sensitivity_limits; 1168 sc->base_params = &iwn5000_base_params; 1169 sc->fwname = "iwn5000fw"; 1170 switch(sc->subdevice_id) { 1171 case IWN_SDID_5x50_1: 1172 case IWN_SDID_5x50_2: 1173 case IWN_SDID_5x50_3: 1174 //iwl5350_agn_cfg 1175 sc->limits = &iwn5000_sensitivity_limits; 1176 sc->base_params = &iwn5000_base_params; 1177 sc->fwname = "iwn5000fw"; 1178 break; 1179 case IWN_SDID_5x50_4: 1180 case IWN_SDID_5x50_5: 1181 case IWN_SDID_5x50_8: 1182 case IWN_SDID_5x50_9: 1183 case IWN_SDID_5x50_10: 1184 case IWN_SDID_5x50_11: 1185 //iwl5150_agn_cfg 1186 case IWN_SDID_5x50_6: 1187 case IWN_SDID_5x50_7: 1188 case IWN_SDID_5x50_12: 1189 case IWN_SDID_5x50_13: 1190 //iwl5150_abg_cfg 1191 sc->limits = &iwn5000_sensitivity_limits; 1192 sc->fwname = "iwn5150fw"; 1193 sc->base_params = &iwn_5x50_base_params; 1194 break; 1195 default: 1196 device_printf(sc->sc_dev, "adapter type id : 0x%04x sub id :" 1197 "0x%04x rev %d not supported (subdevice)\n", pid, 1198 sc->subdevice_id,sc->hw_type); 1199 return ENOTSUP; 1200 } 1201 break; 1202 default: 1203 device_printf(sc->sc_dev, "adapter type id : 0x%04x sub id : 0x%04x" 1204 "rev 0x%08x not supported (device)\n", pid, sc->subdevice_id, 1205 sc->hw_type); 1206 return ENOTSUP; 1207 } 1208 return 0; 1209 } 1210 1211 static int 1212 iwn4965_attach(struct iwn_softc *sc, uint16_t pid) 1213 { 1214 struct iwn_ops *ops = &sc->ops; 1215 1216 DPRINTF(sc, IWN_DEBUG_TRACE, "->%s begin\n", __func__); 1217 ops->load_firmware = iwn4965_load_firmware; 1218 ops->read_eeprom = iwn4965_read_eeprom; 1219 ops->post_alive = iwn4965_post_alive; 1220 ops->nic_config = iwn4965_nic_config; 1221 ops->update_sched = iwn4965_update_sched; 1222 ops->get_temperature = iwn4965_get_temperature; 1223 ops->get_rssi = iwn4965_get_rssi; 1224 ops->set_txpower = iwn4965_set_txpower; 1225 ops->init_gains = iwn4965_init_gains; 1226 ops->set_gains = iwn4965_set_gains; 1227 ops->add_node = iwn4965_add_node; 1228 ops->tx_done = iwn4965_tx_done; 1229 ops->ampdu_tx_start = iwn4965_ampdu_tx_start; 1230 ops->ampdu_tx_stop = iwn4965_ampdu_tx_stop; 1231 sc->ntxqs = IWN4965_NTXQUEUES; 1232 sc->firstaggqueue = IWN4965_FIRSTAGGQUEUE; 1233 sc->ndmachnls = IWN4965_NDMACHNLS; 1234 sc->broadcast_id = IWN4965_ID_BROADCAST; 1235 sc->rxonsz = IWN4965_RXONSZ; 1236 sc->schedsz = IWN4965_SCHEDSZ; 1237 sc->fw_text_maxsz = IWN4965_FW_TEXT_MAXSZ; 1238 sc->fw_data_maxsz = IWN4965_FW_DATA_MAXSZ; 1239 sc->fwsz = IWN4965_FWSZ; 1240 sc->sched_txfact_addr = IWN4965_SCHED_TXFACT; 1241 sc->limits = &iwn4965_sensitivity_limits; 1242 sc->fwname = "iwn4965fw"; 1243 /* Override chains masks, ROM is known to be broken. */ 1244 sc->txchainmask = IWN_ANT_AB; 1245 sc->rxchainmask = IWN_ANT_ABC; 1246 /* Enable normal btcoex */ 1247 sc->sc_flags |= IWN_FLAG_BTCOEX; 1248 1249 DPRINTF(sc, IWN_DEBUG_TRACE, "%s: end\n",__func__); 1250 1251 return 0; 1252 } 1253 1254 static int 1255 iwn5000_attach(struct iwn_softc *sc, uint16_t pid) 1256 { 1257 struct iwn_ops *ops = &sc->ops; 1258 1259 DPRINTF(sc, IWN_DEBUG_TRACE, "->%s begin\n", __func__); 1260 1261 ops->load_firmware = iwn5000_load_firmware; 1262 ops->read_eeprom = iwn5000_read_eeprom; 1263 ops->post_alive = iwn5000_post_alive; 1264 ops->nic_config = iwn5000_nic_config; 1265 ops->update_sched = iwn5000_update_sched; 1266 ops->get_temperature = iwn5000_get_temperature; 1267 ops->get_rssi = iwn5000_get_rssi; 1268 ops->set_txpower = iwn5000_set_txpower; 1269 ops->init_gains = iwn5000_init_gains; 1270 ops->set_gains = iwn5000_set_gains; 1271 ops->add_node = iwn5000_add_node; 1272 ops->tx_done = iwn5000_tx_done; 1273 ops->ampdu_tx_start = iwn5000_ampdu_tx_start; 1274 ops->ampdu_tx_stop = iwn5000_ampdu_tx_stop; 1275 sc->ntxqs = IWN5000_NTXQUEUES; 1276 sc->firstaggqueue = IWN5000_FIRSTAGGQUEUE; 1277 sc->ndmachnls = IWN5000_NDMACHNLS; 1278 sc->broadcast_id = IWN5000_ID_BROADCAST; 1279 sc->rxonsz = IWN5000_RXONSZ; 1280 sc->schedsz = IWN5000_SCHEDSZ; 1281 sc->fw_text_maxsz = IWN5000_FW_TEXT_MAXSZ; 1282 sc->fw_data_maxsz = IWN5000_FW_DATA_MAXSZ; 1283 sc->fwsz = IWN5000_FWSZ; 1284 sc->sched_txfact_addr = IWN5000_SCHED_TXFACT; 1285 sc->reset_noise_gain = IWN5000_PHY_CALIB_RESET_NOISE_GAIN; 1286 sc->noise_gain = IWN5000_PHY_CALIB_NOISE_GAIN; 1287 1288 return 0; 1289 } 1290 1291 /* 1292 * Attach the interface to 802.11 radiotap. 1293 */ 1294 static void 1295 iwn_radiotap_attach(struct iwn_softc *sc) 1296 { 1297 1298 DPRINTF(sc, IWN_DEBUG_TRACE, "->%s begin\n", __func__); 1299 ieee80211_radiotap_attach(&sc->sc_ic, 1300 &sc->sc_txtap.wt_ihdr, sizeof(sc->sc_txtap), 1301 IWN_TX_RADIOTAP_PRESENT, 1302 &sc->sc_rxtap.wr_ihdr, sizeof(sc->sc_rxtap), 1303 IWN_RX_RADIOTAP_PRESENT); 1304 DPRINTF(sc, IWN_DEBUG_TRACE, "->%s end\n", __func__); 1305 } 1306 1307 static void 1308 iwn_sysctlattach(struct iwn_softc *sc) 1309 { 1310 #ifdef IWN_DEBUG 1311 struct sysctl_ctx_list *ctx = device_get_sysctl_ctx(sc->sc_dev); 1312 struct sysctl_oid *tree = device_get_sysctl_tree(sc->sc_dev); 1313 1314 SYSCTL_ADD_INT(ctx, SYSCTL_CHILDREN(tree), OID_AUTO, 1315 "debug", CTLFLAG_RW, &sc->sc_debug, sc->sc_debug, 1316 "control debugging printfs"); 1317 #endif 1318 } 1319 1320 static struct ieee80211vap * 1321 iwn_vap_create(struct ieee80211com *ic, const char name[IFNAMSIZ], int unit, 1322 enum ieee80211_opmode opmode, int flags, 1323 const uint8_t bssid[IEEE80211_ADDR_LEN], 1324 const uint8_t mac[IEEE80211_ADDR_LEN]) 1325 { 1326 struct iwn_softc *sc = ic->ic_softc; 1327 struct iwn_vap *ivp; 1328 struct ieee80211vap *vap; 1329 1330 if (!TAILQ_EMPTY(&ic->ic_vaps)) /* only one at a time */ 1331 return NULL; 1332 1333 ivp = malloc(sizeof(struct iwn_vap), M_80211_VAP, M_WAITOK | M_ZERO); 1334 vap = &ivp->iv_vap; 1335 ieee80211_vap_setup(ic, vap, name, unit, opmode, flags, bssid); 1336 ivp->ctx = IWN_RXON_BSS_CTX; 1337 vap->iv_bmissthreshold = 10; /* override default */ 1338 /* Override with driver methods. */ 1339 ivp->iv_newstate = vap->iv_newstate; 1340 vap->iv_newstate = iwn_newstate; 1341 sc->ivap[IWN_RXON_BSS_CTX] = vap; 1342 1343 ieee80211_ratectl_init(vap); 1344 /* Complete setup. */ 1345 ieee80211_vap_attach(vap, iwn_media_change, ieee80211_media_status, 1346 mac); 1347 ic->ic_opmode = opmode; 1348 return vap; 1349 } 1350 1351 static void 1352 iwn_vap_delete(struct ieee80211vap *vap) 1353 { 1354 struct iwn_vap *ivp = IWN_VAP(vap); 1355 1356 ieee80211_ratectl_deinit(vap); 1357 ieee80211_vap_detach(vap); 1358 free(ivp, M_80211_VAP); 1359 } 1360 1361 static void 1362 iwn_xmit_queue_drain(struct iwn_softc *sc) 1363 { 1364 struct mbuf *m; 1365 struct ieee80211_node *ni; 1366 1367 IWN_LOCK_ASSERT(sc); 1368 while ((m = mbufq_dequeue(&sc->sc_xmit_queue)) != NULL) { 1369 ni = (struct ieee80211_node *)m->m_pkthdr.rcvif; 1370 ieee80211_free_node(ni); 1371 m_freem(m); 1372 } 1373 } 1374 1375 static int 1376 iwn_xmit_queue_enqueue(struct iwn_softc *sc, struct mbuf *m) 1377 { 1378 1379 IWN_LOCK_ASSERT(sc); 1380 return (mbufq_enqueue(&sc->sc_xmit_queue, m)); 1381 } 1382 1383 static int 1384 iwn_detach(device_t dev) 1385 { 1386 struct iwn_softc *sc = device_get_softc(dev); 1387 int qid; 1388 1389 DPRINTF(sc, IWN_DEBUG_TRACE, "->%s begin\n", __func__); 1390 1391 if (sc->sc_ic.ic_softc != NULL) { 1392 /* Free the mbuf queue and node references */ 1393 IWN_LOCK(sc); 1394 iwn_xmit_queue_drain(sc); 1395 IWN_UNLOCK(sc); 1396 1397 ieee80211_draintask(&sc->sc_ic, &sc->sc_reinit_task); 1398 ieee80211_draintask(&sc->sc_ic, &sc->sc_radioon_task); 1399 ieee80211_draintask(&sc->sc_ic, &sc->sc_radiooff_task); 1400 iwn_stop(sc); 1401 1402 taskqueue_drain_all(sc->sc_tq); 1403 taskqueue_free(sc->sc_tq); 1404 1405 callout_drain(&sc->watchdog_to); 1406 callout_drain(&sc->calib_to); 1407 ieee80211_ifdetach(&sc->sc_ic); 1408 } 1409 1410 /* Uninstall interrupt handler. */ 1411 if (sc->irq != NULL) { 1412 bus_teardown_intr(dev, sc->irq, sc->sc_ih); 1413 bus_release_resource(dev, SYS_RES_IRQ, rman_get_rid(sc->irq), 1414 sc->irq); 1415 pci_release_msi(dev); 1416 } 1417 1418 /* Free DMA resources. */ 1419 iwn_free_rx_ring(sc, &sc->rxq); 1420 for (qid = 0; qid < sc->ntxqs; qid++) 1421 iwn_free_tx_ring(sc, &sc->txq[qid]); 1422 iwn_free_sched(sc); 1423 iwn_free_kw(sc); 1424 if (sc->ict != NULL) 1425 iwn_free_ict(sc); 1426 iwn_free_fwmem(sc); 1427 1428 if (sc->mem != NULL) 1429 bus_release_resource(dev, SYS_RES_MEMORY, 1430 rman_get_rid(sc->mem), sc->mem); 1431 1432 if (sc->sc_cdev) { 1433 destroy_dev(sc->sc_cdev); 1434 sc->sc_cdev = NULL; 1435 } 1436 1437 DPRINTF(sc, IWN_DEBUG_TRACE, "->%s: end\n", __func__); 1438 IWN_LOCK_DESTROY(sc); 1439 return 0; 1440 } 1441 1442 static int 1443 iwn_shutdown(device_t dev) 1444 { 1445 struct iwn_softc *sc = device_get_softc(dev); 1446 1447 iwn_stop(sc); 1448 return 0; 1449 } 1450 1451 static int 1452 iwn_suspend(device_t dev) 1453 { 1454 struct iwn_softc *sc = device_get_softc(dev); 1455 1456 ieee80211_suspend_all(&sc->sc_ic); 1457 return 0; 1458 } 1459 1460 static int 1461 iwn_resume(device_t dev) 1462 { 1463 struct iwn_softc *sc = device_get_softc(dev); 1464 1465 /* Clear device-specific "PCI retry timeout" register (41h). */ 1466 pci_write_config(dev, 0x41, 0, 1); 1467 1468 ieee80211_resume_all(&sc->sc_ic); 1469 return 0; 1470 } 1471 1472 static int 1473 iwn_nic_lock(struct iwn_softc *sc) 1474 { 1475 int ntries; 1476 1477 /* Request exclusive access to NIC. */ 1478 IWN_SETBITS(sc, IWN_GP_CNTRL, IWN_GP_CNTRL_MAC_ACCESS_REQ); 1479 1480 /* Spin until we actually get the lock. */ 1481 for (ntries = 0; ntries < 1000; ntries++) { 1482 if ((IWN_READ(sc, IWN_GP_CNTRL) & 1483 (IWN_GP_CNTRL_MAC_ACCESS_ENA | IWN_GP_CNTRL_SLEEP)) == 1484 IWN_GP_CNTRL_MAC_ACCESS_ENA) 1485 return 0; 1486 DELAY(10); 1487 } 1488 return ETIMEDOUT; 1489 } 1490 1491 static __inline void 1492 iwn_nic_unlock(struct iwn_softc *sc) 1493 { 1494 IWN_CLRBITS(sc, IWN_GP_CNTRL, IWN_GP_CNTRL_MAC_ACCESS_REQ); 1495 } 1496 1497 static __inline uint32_t 1498 iwn_prph_read(struct iwn_softc *sc, uint32_t addr) 1499 { 1500 IWN_WRITE(sc, IWN_PRPH_RADDR, IWN_PRPH_DWORD | addr); 1501 IWN_BARRIER_READ_WRITE(sc); 1502 return IWN_READ(sc, IWN_PRPH_RDATA); 1503 } 1504 1505 static __inline void 1506 iwn_prph_write(struct iwn_softc *sc, uint32_t addr, uint32_t data) 1507 { 1508 IWN_WRITE(sc, IWN_PRPH_WADDR, IWN_PRPH_DWORD | addr); 1509 IWN_BARRIER_WRITE(sc); 1510 IWN_WRITE(sc, IWN_PRPH_WDATA, data); 1511 } 1512 1513 static __inline void 1514 iwn_prph_setbits(struct iwn_softc *sc, uint32_t addr, uint32_t mask) 1515 { 1516 iwn_prph_write(sc, addr, iwn_prph_read(sc, addr) | mask); 1517 } 1518 1519 static __inline void 1520 iwn_prph_clrbits(struct iwn_softc *sc, uint32_t addr, uint32_t mask) 1521 { 1522 iwn_prph_write(sc, addr, iwn_prph_read(sc, addr) & ~mask); 1523 } 1524 1525 static __inline void 1526 iwn_prph_write_region_4(struct iwn_softc *sc, uint32_t addr, 1527 const uint32_t *data, int count) 1528 { 1529 for (; count > 0; count--, data++, addr += 4) 1530 iwn_prph_write(sc, addr, *data); 1531 } 1532 1533 static __inline uint32_t 1534 iwn_mem_read(struct iwn_softc *sc, uint32_t addr) 1535 { 1536 IWN_WRITE(sc, IWN_MEM_RADDR, addr); 1537 IWN_BARRIER_READ_WRITE(sc); 1538 return IWN_READ(sc, IWN_MEM_RDATA); 1539 } 1540 1541 static __inline void 1542 iwn_mem_write(struct iwn_softc *sc, uint32_t addr, uint32_t data) 1543 { 1544 IWN_WRITE(sc, IWN_MEM_WADDR, addr); 1545 IWN_BARRIER_WRITE(sc); 1546 IWN_WRITE(sc, IWN_MEM_WDATA, data); 1547 } 1548 1549 static __inline void 1550 iwn_mem_write_2(struct iwn_softc *sc, uint32_t addr, uint16_t data) 1551 { 1552 uint32_t tmp; 1553 1554 tmp = iwn_mem_read(sc, addr & ~3); 1555 if (addr & 3) 1556 tmp = (tmp & 0x0000ffff) | data << 16; 1557 else 1558 tmp = (tmp & 0xffff0000) | data; 1559 iwn_mem_write(sc, addr & ~3, tmp); 1560 } 1561 1562 static __inline void 1563 iwn_mem_read_region_4(struct iwn_softc *sc, uint32_t addr, uint32_t *data, 1564 int count) 1565 { 1566 for (; count > 0; count--, addr += 4) 1567 *data++ = iwn_mem_read(sc, addr); 1568 } 1569 1570 static __inline void 1571 iwn_mem_set_region_4(struct iwn_softc *sc, uint32_t addr, uint32_t val, 1572 int count) 1573 { 1574 for (; count > 0; count--, addr += 4) 1575 iwn_mem_write(sc, addr, val); 1576 } 1577 1578 static int 1579 iwn_eeprom_lock(struct iwn_softc *sc) 1580 { 1581 int i, ntries; 1582 1583 for (i = 0; i < 100; i++) { 1584 /* Request exclusive access to EEPROM. */ 1585 IWN_SETBITS(sc, IWN_HW_IF_CONFIG, 1586 IWN_HW_IF_CONFIG_EEPROM_LOCKED); 1587 1588 /* Spin until we actually get the lock. */ 1589 for (ntries = 0; ntries < 100; ntries++) { 1590 if (IWN_READ(sc, IWN_HW_IF_CONFIG) & 1591 IWN_HW_IF_CONFIG_EEPROM_LOCKED) 1592 return 0; 1593 DELAY(10); 1594 } 1595 } 1596 DPRINTF(sc, IWN_DEBUG_TRACE, "->%s end timeout\n", __func__); 1597 return ETIMEDOUT; 1598 } 1599 1600 static __inline void 1601 iwn_eeprom_unlock(struct iwn_softc *sc) 1602 { 1603 IWN_CLRBITS(sc, IWN_HW_IF_CONFIG, IWN_HW_IF_CONFIG_EEPROM_LOCKED); 1604 } 1605 1606 /* 1607 * Initialize access by host to One Time Programmable ROM. 1608 * NB: This kind of ROM can be found on 1000 or 6000 Series only. 1609 */ 1610 static int 1611 iwn_init_otprom(struct iwn_softc *sc) 1612 { 1613 uint16_t prev, base, next; 1614 int count, error; 1615 1616 DPRINTF(sc, IWN_DEBUG_TRACE, "->%s begin\n", __func__); 1617 1618 /* Wait for clock stabilization before accessing prph. */ 1619 if ((error = iwn_clock_wait(sc)) != 0) 1620 return error; 1621 1622 if ((error = iwn_nic_lock(sc)) != 0) 1623 return error; 1624 iwn_prph_setbits(sc, IWN_APMG_PS, IWN_APMG_PS_RESET_REQ); 1625 DELAY(5); 1626 iwn_prph_clrbits(sc, IWN_APMG_PS, IWN_APMG_PS_RESET_REQ); 1627 iwn_nic_unlock(sc); 1628 1629 /* Set auto clock gate disable bit for HW with OTP shadow RAM. */ 1630 if (sc->base_params->shadow_ram_support) { 1631 IWN_SETBITS(sc, IWN_DBG_LINK_PWR_MGMT, 1632 IWN_RESET_LINK_PWR_MGMT_DIS); 1633 } 1634 IWN_CLRBITS(sc, IWN_EEPROM_GP, IWN_EEPROM_GP_IF_OWNER); 1635 /* Clear ECC status. */ 1636 IWN_SETBITS(sc, IWN_OTP_GP, 1637 IWN_OTP_GP_ECC_CORR_STTS | IWN_OTP_GP_ECC_UNCORR_STTS); 1638 1639 /* 1640 * Find the block before last block (contains the EEPROM image) 1641 * for HW without OTP shadow RAM. 1642 */ 1643 if (! sc->base_params->shadow_ram_support) { 1644 /* Switch to absolute addressing mode. */ 1645 IWN_CLRBITS(sc, IWN_OTP_GP, IWN_OTP_GP_RELATIVE_ACCESS); 1646 base = prev = 0; 1647 for (count = 0; count < sc->base_params->max_ll_items; 1648 count++) { 1649 error = iwn_read_prom_data(sc, base, &next, 2); 1650 if (error != 0) 1651 return error; 1652 if (next == 0) /* End of linked-list. */ 1653 break; 1654 prev = base; 1655 base = le16toh(next); 1656 } 1657 if (count == 0 || count == sc->base_params->max_ll_items) 1658 return EIO; 1659 /* Skip "next" word. */ 1660 sc->prom_base = prev + 1; 1661 } 1662 1663 DPRINTF(sc, IWN_DEBUG_TRACE, "->%s end\n", __func__); 1664 1665 return 0; 1666 } 1667 1668 static int 1669 iwn_read_prom_data(struct iwn_softc *sc, uint32_t addr, void *data, int count) 1670 { 1671 uint8_t *out = data; 1672 uint32_t val, tmp; 1673 int ntries; 1674 1675 DPRINTF(sc, IWN_DEBUG_TRACE, "->%s begin\n", __func__); 1676 1677 addr += sc->prom_base; 1678 for (; count > 0; count -= 2, addr++) { 1679 IWN_WRITE(sc, IWN_EEPROM, addr << 2); 1680 for (ntries = 0; ntries < 10; ntries++) { 1681 val = IWN_READ(sc, IWN_EEPROM); 1682 if (val & IWN_EEPROM_READ_VALID) 1683 break; 1684 DELAY(5); 1685 } 1686 if (ntries == 10) { 1687 device_printf(sc->sc_dev, 1688 "timeout reading ROM at 0x%x\n", addr); 1689 return ETIMEDOUT; 1690 } 1691 if (sc->sc_flags & IWN_FLAG_HAS_OTPROM) { 1692 /* OTPROM, check for ECC errors. */ 1693 tmp = IWN_READ(sc, IWN_OTP_GP); 1694 if (tmp & IWN_OTP_GP_ECC_UNCORR_STTS) { 1695 device_printf(sc->sc_dev, 1696 "OTPROM ECC error at 0x%x\n", addr); 1697 return EIO; 1698 } 1699 if (tmp & IWN_OTP_GP_ECC_CORR_STTS) { 1700 /* Correctable ECC error, clear bit. */ 1701 IWN_SETBITS(sc, IWN_OTP_GP, 1702 IWN_OTP_GP_ECC_CORR_STTS); 1703 } 1704 } 1705 *out++ = val >> 16; 1706 if (count > 1) 1707 *out++ = val >> 24; 1708 } 1709 1710 DPRINTF(sc, IWN_DEBUG_TRACE, "->%s end\n", __func__); 1711 1712 return 0; 1713 } 1714 1715 static void 1716 iwn_dma_map_addr(void *arg, bus_dma_segment_t *segs, int nsegs, int error) 1717 { 1718 if (error != 0) 1719 return; 1720 KASSERT(nsegs == 1, ("too many DMA segments, %d should be 1", nsegs)); 1721 *(bus_addr_t *)arg = segs[0].ds_addr; 1722 } 1723 1724 static int 1725 iwn_dma_contig_alloc(struct iwn_softc *sc, struct iwn_dma_info *dma, 1726 void **kvap, bus_size_t size, bus_size_t alignment) 1727 { 1728 int error; 1729 1730 dma->tag = NULL; 1731 dma->size = size; 1732 1733 error = bus_dma_tag_create(bus_get_dma_tag(sc->sc_dev), alignment, 1734 0, BUS_SPACE_MAXADDR_32BIT, BUS_SPACE_MAXADDR, NULL, NULL, size, 1735 1, size, BUS_DMA_NOWAIT, NULL, NULL, &dma->tag); 1736 if (error != 0) 1737 goto fail; 1738 1739 error = bus_dmamem_alloc(dma->tag, (void **)&dma->vaddr, 1740 BUS_DMA_NOWAIT | BUS_DMA_ZERO | BUS_DMA_COHERENT, &dma->map); 1741 if (error != 0) 1742 goto fail; 1743 1744 error = bus_dmamap_load(dma->tag, dma->map, dma->vaddr, size, 1745 iwn_dma_map_addr, &dma->paddr, BUS_DMA_NOWAIT); 1746 if (error != 0) 1747 goto fail; 1748 1749 bus_dmamap_sync(dma->tag, dma->map, BUS_DMASYNC_PREWRITE); 1750 1751 if (kvap != NULL) 1752 *kvap = dma->vaddr; 1753 1754 return 0; 1755 1756 fail: iwn_dma_contig_free(dma); 1757 return error; 1758 } 1759 1760 static void 1761 iwn_dma_contig_free(struct iwn_dma_info *dma) 1762 { 1763 if (dma->vaddr != NULL) { 1764 bus_dmamap_sync(dma->tag, dma->map, 1765 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); 1766 bus_dmamap_unload(dma->tag, dma->map); 1767 bus_dmamem_free(dma->tag, dma->vaddr, dma->map); 1768 dma->vaddr = NULL; 1769 } 1770 if (dma->tag != NULL) { 1771 bus_dma_tag_destroy(dma->tag); 1772 dma->tag = NULL; 1773 } 1774 } 1775 1776 static int 1777 iwn_alloc_sched(struct iwn_softc *sc) 1778 { 1779 /* TX scheduler rings must be aligned on a 1KB boundary. */ 1780 return iwn_dma_contig_alloc(sc, &sc->sched_dma, (void **)&sc->sched, 1781 sc->schedsz, 1024); 1782 } 1783 1784 static void 1785 iwn_free_sched(struct iwn_softc *sc) 1786 { 1787 iwn_dma_contig_free(&sc->sched_dma); 1788 } 1789 1790 static int 1791 iwn_alloc_kw(struct iwn_softc *sc) 1792 { 1793 /* "Keep Warm" page must be aligned on a 4KB boundary. */ 1794 return iwn_dma_contig_alloc(sc, &sc->kw_dma, NULL, 4096, 4096); 1795 } 1796 1797 static void 1798 iwn_free_kw(struct iwn_softc *sc) 1799 { 1800 iwn_dma_contig_free(&sc->kw_dma); 1801 } 1802 1803 static int 1804 iwn_alloc_ict(struct iwn_softc *sc) 1805 { 1806 /* ICT table must be aligned on a 4KB boundary. */ 1807 return iwn_dma_contig_alloc(sc, &sc->ict_dma, (void **)&sc->ict, 1808 IWN_ICT_SIZE, 4096); 1809 } 1810 1811 static void 1812 iwn_free_ict(struct iwn_softc *sc) 1813 { 1814 iwn_dma_contig_free(&sc->ict_dma); 1815 } 1816 1817 static int 1818 iwn_alloc_fwmem(struct iwn_softc *sc) 1819 { 1820 /* Must be aligned on a 16-byte boundary. */ 1821 return iwn_dma_contig_alloc(sc, &sc->fw_dma, NULL, sc->fwsz, 16); 1822 } 1823 1824 static void 1825 iwn_free_fwmem(struct iwn_softc *sc) 1826 { 1827 iwn_dma_contig_free(&sc->fw_dma); 1828 } 1829 1830 static int 1831 iwn_alloc_rx_ring(struct iwn_softc *sc, struct iwn_rx_ring *ring) 1832 { 1833 bus_size_t size; 1834 int i, error; 1835 1836 ring->cur = 0; 1837 1838 DPRINTF(sc, IWN_DEBUG_TRACE, "->%s begin\n", __func__); 1839 1840 /* Allocate RX descriptors (256-byte aligned). */ 1841 size = IWN_RX_RING_COUNT * sizeof (uint32_t); 1842 error = iwn_dma_contig_alloc(sc, &ring->desc_dma, (void **)&ring->desc, 1843 size, 256); 1844 if (error != 0) { 1845 device_printf(sc->sc_dev, 1846 "%s: could not allocate RX ring DMA memory, error %d\n", 1847 __func__, error); 1848 goto fail; 1849 } 1850 1851 /* Allocate RX status area (16-byte aligned). */ 1852 error = iwn_dma_contig_alloc(sc, &ring->stat_dma, (void **)&ring->stat, 1853 sizeof (struct iwn_rx_status), 16); 1854 if (error != 0) { 1855 device_printf(sc->sc_dev, 1856 "%s: could not allocate RX status DMA memory, error %d\n", 1857 __func__, error); 1858 goto fail; 1859 } 1860 1861 /* Create RX buffer DMA tag. */ 1862 error = bus_dma_tag_create(bus_get_dma_tag(sc->sc_dev), 1, 0, 1863 BUS_SPACE_MAXADDR_32BIT, BUS_SPACE_MAXADDR, NULL, NULL, 1864 IWN_RBUF_SIZE, 1, IWN_RBUF_SIZE, BUS_DMA_NOWAIT, NULL, NULL, 1865 &ring->data_dmat); 1866 if (error != 0) { 1867 device_printf(sc->sc_dev, 1868 "%s: could not create RX buf DMA tag, error %d\n", 1869 __func__, error); 1870 goto fail; 1871 } 1872 1873 /* 1874 * Allocate and map RX buffers. 1875 */ 1876 for (i = 0; i < IWN_RX_RING_COUNT; i++) { 1877 struct iwn_rx_data *data = &ring->data[i]; 1878 bus_addr_t paddr; 1879 1880 error = bus_dmamap_create(ring->data_dmat, 0, &data->map); 1881 if (error != 0) { 1882 device_printf(sc->sc_dev, 1883 "%s: could not create RX buf DMA map, error %d\n", 1884 __func__, error); 1885 goto fail; 1886 } 1887 1888 data->m = m_getjcl(M_NOWAIT, MT_DATA, M_PKTHDR, 1889 IWN_RBUF_SIZE); 1890 if (data->m == NULL) { 1891 device_printf(sc->sc_dev, 1892 "%s: could not allocate RX mbuf\n", __func__); 1893 error = ENOBUFS; 1894 goto fail; 1895 } 1896 1897 error = bus_dmamap_load(ring->data_dmat, data->map, 1898 mtod(data->m, void *), IWN_RBUF_SIZE, iwn_dma_map_addr, 1899 &paddr, BUS_DMA_NOWAIT); 1900 if (error != 0 && error != EFBIG) { 1901 device_printf(sc->sc_dev, 1902 "%s: can't map mbuf, error %d\n", __func__, 1903 error); 1904 goto fail; 1905 } 1906 1907 /* Set physical address of RX buffer (256-byte aligned). */ 1908 ring->desc[i] = htole32(paddr >> 8); 1909 } 1910 1911 bus_dmamap_sync(ring->desc_dma.tag, ring->desc_dma.map, 1912 BUS_DMASYNC_PREWRITE); 1913 1914 DPRINTF(sc, IWN_DEBUG_TRACE, "->%s: end\n",__func__); 1915 1916 return 0; 1917 1918 fail: iwn_free_rx_ring(sc, ring); 1919 1920 DPRINTF(sc, IWN_DEBUG_TRACE, "->%s: end in error\n",__func__); 1921 1922 return error; 1923 } 1924 1925 static void 1926 iwn_reset_rx_ring(struct iwn_softc *sc, struct iwn_rx_ring *ring) 1927 { 1928 int ntries; 1929 1930 DPRINTF(sc, IWN_DEBUG_TRACE, "->Doing %s\n", __func__); 1931 1932 if (iwn_nic_lock(sc) == 0) { 1933 IWN_WRITE(sc, IWN_FH_RX_CONFIG, 0); 1934 for (ntries = 0; ntries < 1000; ntries++) { 1935 if (IWN_READ(sc, IWN_FH_RX_STATUS) & 1936 IWN_FH_RX_STATUS_IDLE) 1937 break; 1938 DELAY(10); 1939 } 1940 iwn_nic_unlock(sc); 1941 } 1942 ring->cur = 0; 1943 sc->last_rx_valid = 0; 1944 } 1945 1946 static void 1947 iwn_free_rx_ring(struct iwn_softc *sc, struct iwn_rx_ring *ring) 1948 { 1949 int i; 1950 1951 DPRINTF(sc, IWN_DEBUG_TRACE, "->Doing %s \n", __func__); 1952 1953 iwn_dma_contig_free(&ring->desc_dma); 1954 iwn_dma_contig_free(&ring->stat_dma); 1955 1956 for (i = 0; i < IWN_RX_RING_COUNT; i++) { 1957 struct iwn_rx_data *data = &ring->data[i]; 1958 1959 if (data->m != NULL) { 1960 bus_dmamap_sync(ring->data_dmat, data->map, 1961 BUS_DMASYNC_POSTREAD); 1962 bus_dmamap_unload(ring->data_dmat, data->map); 1963 m_freem(data->m); 1964 data->m = NULL; 1965 } 1966 if (data->map != NULL) 1967 bus_dmamap_destroy(ring->data_dmat, data->map); 1968 } 1969 if (ring->data_dmat != NULL) { 1970 bus_dma_tag_destroy(ring->data_dmat); 1971 ring->data_dmat = NULL; 1972 } 1973 } 1974 1975 static int 1976 iwn_alloc_tx_ring(struct iwn_softc *sc, struct iwn_tx_ring *ring, int qid) 1977 { 1978 bus_addr_t paddr; 1979 bus_size_t size; 1980 int i, error; 1981 1982 ring->qid = qid; 1983 ring->queued = 0; 1984 ring->cur = 0; 1985 1986 DPRINTF(sc, IWN_DEBUG_TRACE, "->%s begin\n", __func__); 1987 1988 /* Allocate TX descriptors (256-byte aligned). */ 1989 size = IWN_TX_RING_COUNT * sizeof (struct iwn_tx_desc); 1990 error = iwn_dma_contig_alloc(sc, &ring->desc_dma, (void **)&ring->desc, 1991 size, 256); 1992 if (error != 0) { 1993 device_printf(sc->sc_dev, 1994 "%s: could not allocate TX ring DMA memory, error %d\n", 1995 __func__, error); 1996 goto fail; 1997 } 1998 1999 size = IWN_TX_RING_COUNT * sizeof (struct iwn_tx_cmd); 2000 error = iwn_dma_contig_alloc(sc, &ring->cmd_dma, (void **)&ring->cmd, 2001 size, 4); 2002 if (error != 0) { 2003 device_printf(sc->sc_dev, 2004 "%s: could not allocate TX cmd DMA memory, error %d\n", 2005 __func__, error); 2006 goto fail; 2007 } 2008 2009 error = bus_dma_tag_create(bus_get_dma_tag(sc->sc_dev), 1, 0, 2010 BUS_SPACE_MAXADDR_32BIT, BUS_SPACE_MAXADDR, NULL, NULL, MCLBYTES, 2011 IWN_MAX_SCATTER - 1, MCLBYTES, BUS_DMA_NOWAIT, NULL, NULL, 2012 &ring->data_dmat); 2013 if (error != 0) { 2014 device_printf(sc->sc_dev, 2015 "%s: could not create TX buf DMA tag, error %d\n", 2016 __func__, error); 2017 goto fail; 2018 } 2019 2020 paddr = ring->cmd_dma.paddr; 2021 for (i = 0; i < IWN_TX_RING_COUNT; i++) { 2022 struct iwn_tx_data *data = &ring->data[i]; 2023 2024 data->cmd_paddr = paddr; 2025 data->scratch_paddr = paddr + 12; 2026 paddr += sizeof (struct iwn_tx_cmd); 2027 2028 error = bus_dmamap_create(ring->data_dmat, 0, &data->map); 2029 if (error != 0) { 2030 device_printf(sc->sc_dev, 2031 "%s: could not create TX buf DMA map, error %d\n", 2032 __func__, error); 2033 goto fail; 2034 } 2035 } 2036 2037 DPRINTF(sc, IWN_DEBUG_TRACE, "->%s end\n", __func__); 2038 2039 return 0; 2040 2041 fail: iwn_free_tx_ring(sc, ring); 2042 DPRINTF(sc, IWN_DEBUG_TRACE, "->%s end in error\n", __func__); 2043 return error; 2044 } 2045 2046 static void 2047 iwn_reset_tx_ring(struct iwn_softc *sc, struct iwn_tx_ring *ring) 2048 { 2049 int i; 2050 2051 DPRINTF(sc, IWN_DEBUG_TRACE, "->doing %s \n", __func__); 2052 2053 for (i = 0; i < IWN_TX_RING_COUNT; i++) { 2054 struct iwn_tx_data *data = &ring->data[i]; 2055 2056 if (data->m != NULL) { 2057 bus_dmamap_sync(ring->data_dmat, data->map, 2058 BUS_DMASYNC_POSTWRITE); 2059 bus_dmamap_unload(ring->data_dmat, data->map); 2060 m_freem(data->m); 2061 data->m = NULL; 2062 } 2063 if (data->ni != NULL) { 2064 ieee80211_free_node(data->ni); 2065 data->ni = NULL; 2066 } 2067 } 2068 /* Clear TX descriptors. */ 2069 memset(ring->desc, 0, ring->desc_dma.size); 2070 bus_dmamap_sync(ring->desc_dma.tag, ring->desc_dma.map, 2071 BUS_DMASYNC_PREWRITE); 2072 sc->qfullmsk &= ~(1 << ring->qid); 2073 ring->queued = 0; 2074 ring->cur = 0; 2075 } 2076 2077 static void 2078 iwn_free_tx_ring(struct iwn_softc *sc, struct iwn_tx_ring *ring) 2079 { 2080 int i; 2081 2082 DPRINTF(sc, IWN_DEBUG_TRACE, "->Doing %s \n", __func__); 2083 2084 iwn_dma_contig_free(&ring->desc_dma); 2085 iwn_dma_contig_free(&ring->cmd_dma); 2086 2087 for (i = 0; i < IWN_TX_RING_COUNT; i++) { 2088 struct iwn_tx_data *data = &ring->data[i]; 2089 2090 if (data->m != NULL) { 2091 bus_dmamap_sync(ring->data_dmat, data->map, 2092 BUS_DMASYNC_POSTWRITE); 2093 bus_dmamap_unload(ring->data_dmat, data->map); 2094 m_freem(data->m); 2095 } 2096 if (data->map != NULL) 2097 bus_dmamap_destroy(ring->data_dmat, data->map); 2098 } 2099 if (ring->data_dmat != NULL) { 2100 bus_dma_tag_destroy(ring->data_dmat); 2101 ring->data_dmat = NULL; 2102 } 2103 } 2104 2105 static void 2106 iwn5000_ict_reset(struct iwn_softc *sc) 2107 { 2108 /* Disable interrupts. */ 2109 IWN_WRITE(sc, IWN_INT_MASK, 0); 2110 2111 /* Reset ICT table. */ 2112 memset(sc->ict, 0, IWN_ICT_SIZE); 2113 sc->ict_cur = 0; 2114 2115 /* Set physical address of ICT table (4KB aligned). */ 2116 DPRINTF(sc, IWN_DEBUG_RESET, "%s: enabling ICT\n", __func__); 2117 IWN_WRITE(sc, IWN_DRAM_INT_TBL, IWN_DRAM_INT_TBL_ENABLE | 2118 IWN_DRAM_INT_TBL_WRAP_CHECK | sc->ict_dma.paddr >> 12); 2119 2120 /* Enable periodic RX interrupt. */ 2121 sc->int_mask |= IWN_INT_RX_PERIODIC; 2122 /* Switch to ICT interrupt mode in driver. */ 2123 sc->sc_flags |= IWN_FLAG_USE_ICT; 2124 2125 /* Re-enable interrupts. */ 2126 IWN_WRITE(sc, IWN_INT, 0xffffffff); 2127 IWN_WRITE(sc, IWN_INT_MASK, sc->int_mask); 2128 } 2129 2130 static int 2131 iwn_read_eeprom(struct iwn_softc *sc, uint8_t macaddr[IEEE80211_ADDR_LEN]) 2132 { 2133 struct iwn_ops *ops = &sc->ops; 2134 uint16_t val; 2135 int error; 2136 2137 DPRINTF(sc, IWN_DEBUG_TRACE, "->%s begin\n", __func__); 2138 2139 /* Check whether adapter has an EEPROM or an OTPROM. */ 2140 if (sc->hw_type >= IWN_HW_REV_TYPE_1000 && 2141 (IWN_READ(sc, IWN_OTP_GP) & IWN_OTP_GP_DEV_SEL_OTP)) 2142 sc->sc_flags |= IWN_FLAG_HAS_OTPROM; 2143 DPRINTF(sc, IWN_DEBUG_RESET, "%s found\n", 2144 (sc->sc_flags & IWN_FLAG_HAS_OTPROM) ? "OTPROM" : "EEPROM"); 2145 2146 /* Adapter has to be powered on for EEPROM access to work. */ 2147 if ((error = iwn_apm_init(sc)) != 0) { 2148 device_printf(sc->sc_dev, 2149 "%s: could not power ON adapter, error %d\n", __func__, 2150 error); 2151 return error; 2152 } 2153 2154 if ((IWN_READ(sc, IWN_EEPROM_GP) & 0x7) == 0) { 2155 device_printf(sc->sc_dev, "%s: bad ROM signature\n", __func__); 2156 return EIO; 2157 } 2158 if ((error = iwn_eeprom_lock(sc)) != 0) { 2159 device_printf(sc->sc_dev, "%s: could not lock ROM, error %d\n", 2160 __func__, error); 2161 return error; 2162 } 2163 if (sc->sc_flags & IWN_FLAG_HAS_OTPROM) { 2164 if ((error = iwn_init_otprom(sc)) != 0) { 2165 device_printf(sc->sc_dev, 2166 "%s: could not initialize OTPROM, error %d\n", 2167 __func__, error); 2168 return error; 2169 } 2170 } 2171 2172 iwn_read_prom_data(sc, IWN_EEPROM_SKU_CAP, &val, 2); 2173 DPRINTF(sc, IWN_DEBUG_RESET, "SKU capabilities=0x%04x\n", le16toh(val)); 2174 /* Check if HT support is bonded out. */ 2175 if (val & htole16(IWN_EEPROM_SKU_CAP_11N)) 2176 sc->sc_flags |= IWN_FLAG_HAS_11N; 2177 2178 iwn_read_prom_data(sc, IWN_EEPROM_RFCFG, &val, 2); 2179 sc->rfcfg = le16toh(val); 2180 DPRINTF(sc, IWN_DEBUG_RESET, "radio config=0x%04x\n", sc->rfcfg); 2181 /* Read Tx/Rx chains from ROM unless it's known to be broken. */ 2182 if (sc->txchainmask == 0) 2183 sc->txchainmask = IWN_RFCFG_TXANTMSK(sc->rfcfg); 2184 if (sc->rxchainmask == 0) 2185 sc->rxchainmask = IWN_RFCFG_RXANTMSK(sc->rfcfg); 2186 2187 /* Read MAC address. */ 2188 iwn_read_prom_data(sc, IWN_EEPROM_MAC, macaddr, 6); 2189 2190 /* Read adapter-specific information from EEPROM. */ 2191 ops->read_eeprom(sc); 2192 2193 iwn_apm_stop(sc); /* Power OFF adapter. */ 2194 2195 iwn_eeprom_unlock(sc); 2196 2197 DPRINTF(sc, IWN_DEBUG_TRACE, "->%s end\n", __func__); 2198 2199 return 0; 2200 } 2201 2202 static void 2203 iwn4965_read_eeprom(struct iwn_softc *sc) 2204 { 2205 uint32_t addr; 2206 uint16_t val; 2207 int i; 2208 2209 DPRINTF(sc, IWN_DEBUG_TRACE, "->%s begin\n", __func__); 2210 2211 /* Read regulatory domain (4 ASCII characters). */ 2212 iwn_read_prom_data(sc, IWN4965_EEPROM_DOMAIN, sc->eeprom_domain, 4); 2213 2214 /* Read the list of authorized channels (20MHz ones only). */ 2215 for (i = 0; i < IWN_NBANDS - 1; i++) { 2216 addr = iwn4965_regulatory_bands[i]; 2217 iwn_read_eeprom_channels(sc, i, addr); 2218 } 2219 2220 /* Read maximum allowed TX power for 2GHz and 5GHz bands. */ 2221 iwn_read_prom_data(sc, IWN4965_EEPROM_MAXPOW, &val, 2); 2222 sc->maxpwr2GHz = val & 0xff; 2223 sc->maxpwr5GHz = val >> 8; 2224 /* Check that EEPROM values are within valid range. */ 2225 if (sc->maxpwr5GHz < 20 || sc->maxpwr5GHz > 50) 2226 sc->maxpwr5GHz = 38; 2227 if (sc->maxpwr2GHz < 20 || sc->maxpwr2GHz > 50) 2228 sc->maxpwr2GHz = 38; 2229 DPRINTF(sc, IWN_DEBUG_RESET, "maxpwr 2GHz=%d 5GHz=%d\n", 2230 sc->maxpwr2GHz, sc->maxpwr5GHz); 2231 2232 /* Read samples for each TX power group. */ 2233 iwn_read_prom_data(sc, IWN4965_EEPROM_BANDS, sc->bands, 2234 sizeof sc->bands); 2235 2236 /* Read voltage at which samples were taken. */ 2237 iwn_read_prom_data(sc, IWN4965_EEPROM_VOLTAGE, &val, 2); 2238 sc->eeprom_voltage = (int16_t)le16toh(val); 2239 DPRINTF(sc, IWN_DEBUG_RESET, "voltage=%d (in 0.3V)\n", 2240 sc->eeprom_voltage); 2241 2242 #ifdef IWN_DEBUG 2243 /* Print samples. */ 2244 if (sc->sc_debug & IWN_DEBUG_ANY) { 2245 for (i = 0; i < IWN_NBANDS - 1; i++) 2246 iwn4965_print_power_group(sc, i); 2247 } 2248 #endif 2249 2250 DPRINTF(sc, IWN_DEBUG_TRACE, "->%s end\n", __func__); 2251 } 2252 2253 #ifdef IWN_DEBUG 2254 static void 2255 iwn4965_print_power_group(struct iwn_softc *sc, int i) 2256 { 2257 struct iwn4965_eeprom_band *band = &sc->bands[i]; 2258 struct iwn4965_eeprom_chan_samples *chans = band->chans; 2259 int j, c; 2260 2261 printf("===band %d===\n", i); 2262 printf("chan lo=%d, chan hi=%d\n", band->lo, band->hi); 2263 printf("chan1 num=%d\n", chans[0].num); 2264 for (c = 0; c < 2; c++) { 2265 for (j = 0; j < IWN_NSAMPLES; j++) { 2266 printf("chain %d, sample %d: temp=%d gain=%d " 2267 "power=%d pa_det=%d\n", c, j, 2268 chans[0].samples[c][j].temp, 2269 chans[0].samples[c][j].gain, 2270 chans[0].samples[c][j].power, 2271 chans[0].samples[c][j].pa_det); 2272 } 2273 } 2274 printf("chan2 num=%d\n", chans[1].num); 2275 for (c = 0; c < 2; c++) { 2276 for (j = 0; j < IWN_NSAMPLES; j++) { 2277 printf("chain %d, sample %d: temp=%d gain=%d " 2278 "power=%d pa_det=%d\n", c, j, 2279 chans[1].samples[c][j].temp, 2280 chans[1].samples[c][j].gain, 2281 chans[1].samples[c][j].power, 2282 chans[1].samples[c][j].pa_det); 2283 } 2284 } 2285 } 2286 #endif 2287 2288 static void 2289 iwn5000_read_eeprom(struct iwn_softc *sc) 2290 { 2291 struct iwn5000_eeprom_calib_hdr hdr; 2292 int32_t volt; 2293 uint32_t base, addr; 2294 uint16_t val; 2295 int i; 2296 2297 DPRINTF(sc, IWN_DEBUG_TRACE, "->%s begin\n", __func__); 2298 2299 /* Read regulatory domain (4 ASCII characters). */ 2300 iwn_read_prom_data(sc, IWN5000_EEPROM_REG, &val, 2); 2301 base = le16toh(val); 2302 iwn_read_prom_data(sc, base + IWN5000_EEPROM_DOMAIN, 2303 sc->eeprom_domain, 4); 2304 2305 /* Read the list of authorized channels (20MHz ones only). */ 2306 for (i = 0; i < IWN_NBANDS - 1; i++) { 2307 addr = base + sc->base_params->regulatory_bands[i]; 2308 iwn_read_eeprom_channels(sc, i, addr); 2309 } 2310 2311 /* Read enhanced TX power information for 6000 Series. */ 2312 if (sc->base_params->enhanced_TX_power) 2313 iwn_read_eeprom_enhinfo(sc); 2314 2315 iwn_read_prom_data(sc, IWN5000_EEPROM_CAL, &val, 2); 2316 base = le16toh(val); 2317 iwn_read_prom_data(sc, base, &hdr, sizeof hdr); 2318 DPRINTF(sc, IWN_DEBUG_CALIBRATE, 2319 "%s: calib version=%u pa type=%u voltage=%u\n", __func__, 2320 hdr.version, hdr.pa_type, le16toh(hdr.volt)); 2321 sc->calib_ver = hdr.version; 2322 2323 if (sc->base_params->calib_need & IWN_FLG_NEED_PHY_CALIB_TEMP_OFFSETv2) { 2324 sc->eeprom_voltage = le16toh(hdr.volt); 2325 iwn_read_prom_data(sc, base + IWN5000_EEPROM_TEMP, &val, 2); 2326 sc->eeprom_temp_high=le16toh(val); 2327 iwn_read_prom_data(sc, base + IWN5000_EEPROM_VOLT, &val, 2); 2328 sc->eeprom_temp = le16toh(val); 2329 } 2330 2331 if (sc->hw_type == IWN_HW_REV_TYPE_5150) { 2332 /* Compute temperature offset. */ 2333 iwn_read_prom_data(sc, base + IWN5000_EEPROM_TEMP, &val, 2); 2334 sc->eeprom_temp = le16toh(val); 2335 iwn_read_prom_data(sc, base + IWN5000_EEPROM_VOLT, &val, 2); 2336 volt = le16toh(val); 2337 sc->temp_off = sc->eeprom_temp - (volt / -5); 2338 DPRINTF(sc, IWN_DEBUG_CALIBRATE, "temp=%d volt=%d offset=%dK\n", 2339 sc->eeprom_temp, volt, sc->temp_off); 2340 } else { 2341 /* Read crystal calibration. */ 2342 iwn_read_prom_data(sc, base + IWN5000_EEPROM_CRYSTAL, 2343 &sc->eeprom_crystal, sizeof (uint32_t)); 2344 DPRINTF(sc, IWN_DEBUG_CALIBRATE, "crystal calibration 0x%08x\n", 2345 le32toh(sc->eeprom_crystal)); 2346 } 2347 2348 DPRINTF(sc, IWN_DEBUG_TRACE, "->%s end\n", __func__); 2349 2350 } 2351 2352 /* 2353 * Translate EEPROM flags to net80211. 2354 */ 2355 static uint32_t 2356 iwn_eeprom_channel_flags(struct iwn_eeprom_chan *channel) 2357 { 2358 uint32_t nflags; 2359 2360 nflags = 0; 2361 if ((channel->flags & IWN_EEPROM_CHAN_ACTIVE) == 0) 2362 nflags |= IEEE80211_CHAN_PASSIVE; 2363 if ((channel->flags & IWN_EEPROM_CHAN_IBSS) == 0) 2364 nflags |= IEEE80211_CHAN_NOADHOC; 2365 if (channel->flags & IWN_EEPROM_CHAN_RADAR) { 2366 nflags |= IEEE80211_CHAN_DFS; 2367 /* XXX apparently IBSS may still be marked */ 2368 nflags |= IEEE80211_CHAN_NOADHOC; 2369 } 2370 2371 return nflags; 2372 } 2373 2374 static void 2375 iwn_read_eeprom_band(struct iwn_softc *sc, int n) 2376 { 2377 struct ieee80211com *ic = &sc->sc_ic; 2378 struct iwn_eeprom_chan *channels = sc->eeprom_channels[n]; 2379 const struct iwn_chan_band *band = &iwn_bands[n]; 2380 struct ieee80211_channel *c; 2381 uint8_t chan; 2382 int i, nflags; 2383 2384 DPRINTF(sc, IWN_DEBUG_TRACE, "->%s begin\n", __func__); 2385 2386 for (i = 0; i < band->nchan; i++) { 2387 if (!(channels[i].flags & IWN_EEPROM_CHAN_VALID)) { 2388 DPRINTF(sc, IWN_DEBUG_RESET, 2389 "skip chan %d flags 0x%x maxpwr %d\n", 2390 band->chan[i], channels[i].flags, 2391 channels[i].maxpwr); 2392 continue; 2393 } 2394 chan = band->chan[i]; 2395 nflags = iwn_eeprom_channel_flags(&channels[i]); 2396 2397 c = &ic->ic_channels[ic->ic_nchans++]; 2398 c->ic_ieee = chan; 2399 c->ic_maxregpower = channels[i].maxpwr; 2400 c->ic_maxpower = 2*c->ic_maxregpower; 2401 2402 if (n == 0) { /* 2GHz band */ 2403 c->ic_freq = ieee80211_ieee2mhz(chan, IEEE80211_CHAN_G); 2404 /* G =>'s B is supported */ 2405 c->ic_flags = IEEE80211_CHAN_B | nflags; 2406 c = &ic->ic_channels[ic->ic_nchans++]; 2407 c[0] = c[-1]; 2408 c->ic_flags = IEEE80211_CHAN_G | nflags; 2409 } else { /* 5GHz band */ 2410 c->ic_freq = ieee80211_ieee2mhz(chan, IEEE80211_CHAN_A); 2411 c->ic_flags = IEEE80211_CHAN_A | nflags; 2412 } 2413 2414 /* Save maximum allowed TX power for this channel. */ 2415 sc->maxpwr[chan] = channels[i].maxpwr; 2416 2417 DPRINTF(sc, IWN_DEBUG_RESET, 2418 "add chan %d flags 0x%x maxpwr %d\n", chan, 2419 channels[i].flags, channels[i].maxpwr); 2420 2421 if (sc->sc_flags & IWN_FLAG_HAS_11N) { 2422 /* add HT20, HT40 added separately */ 2423 c = &ic->ic_channels[ic->ic_nchans++]; 2424 c[0] = c[-1]; 2425 c->ic_flags |= IEEE80211_CHAN_HT20; 2426 } 2427 } 2428 2429 DPRINTF(sc, IWN_DEBUG_TRACE, "->%s end\n", __func__); 2430 2431 } 2432 2433 static void 2434 iwn_read_eeprom_ht40(struct iwn_softc *sc, int n) 2435 { 2436 struct ieee80211com *ic = &sc->sc_ic; 2437 struct iwn_eeprom_chan *channels = sc->eeprom_channels[n]; 2438 const struct iwn_chan_band *band = &iwn_bands[n]; 2439 struct ieee80211_channel *c, *cent, *extc; 2440 uint8_t chan; 2441 int i, nflags; 2442 2443 DPRINTF(sc, IWN_DEBUG_TRACE, "->%s start\n", __func__); 2444 2445 if (!(sc->sc_flags & IWN_FLAG_HAS_11N)) { 2446 DPRINTF(sc, IWN_DEBUG_TRACE, "->%s end no 11n\n", __func__); 2447 return; 2448 } 2449 2450 for (i = 0; i < band->nchan; i++) { 2451 if (!(channels[i].flags & IWN_EEPROM_CHAN_VALID)) { 2452 DPRINTF(sc, IWN_DEBUG_RESET, 2453 "skip chan %d flags 0x%x maxpwr %d\n", 2454 band->chan[i], channels[i].flags, 2455 channels[i].maxpwr); 2456 continue; 2457 } 2458 chan = band->chan[i]; 2459 nflags = iwn_eeprom_channel_flags(&channels[i]); 2460 2461 /* 2462 * Each entry defines an HT40 channel pair; find the 2463 * center channel, then the extension channel above. 2464 */ 2465 cent = ieee80211_find_channel_byieee(ic, chan, 2466 (n == 5 ? IEEE80211_CHAN_G : IEEE80211_CHAN_A)); 2467 if (cent == NULL) { /* XXX shouldn't happen */ 2468 device_printf(sc->sc_dev, 2469 "%s: no entry for channel %d\n", __func__, chan); 2470 continue; 2471 } 2472 extc = ieee80211_find_channel(ic, cent->ic_freq+20, 2473 (n == 5 ? IEEE80211_CHAN_G : IEEE80211_CHAN_A)); 2474 if (extc == NULL) { 2475 DPRINTF(sc, IWN_DEBUG_RESET, 2476 "%s: skip chan %d, extension channel not found\n", 2477 __func__, chan); 2478 continue; 2479 } 2480 2481 DPRINTF(sc, IWN_DEBUG_RESET, 2482 "add ht40 chan %d flags 0x%x maxpwr %d\n", 2483 chan, channels[i].flags, channels[i].maxpwr); 2484 2485 c = &ic->ic_channels[ic->ic_nchans++]; 2486 c[0] = cent[0]; 2487 c->ic_extieee = extc->ic_ieee; 2488 c->ic_flags &= ~IEEE80211_CHAN_HT; 2489 c->ic_flags |= IEEE80211_CHAN_HT40U | nflags; 2490 c = &ic->ic_channels[ic->ic_nchans++]; 2491 c[0] = extc[0]; 2492 c->ic_extieee = cent->ic_ieee; 2493 c->ic_flags &= ~IEEE80211_CHAN_HT; 2494 c->ic_flags |= IEEE80211_CHAN_HT40D | nflags; 2495 } 2496 2497 DPRINTF(sc, IWN_DEBUG_TRACE, "->%s end\n", __func__); 2498 2499 } 2500 2501 static void 2502 iwn_read_eeprom_channels(struct iwn_softc *sc, int n, uint32_t addr) 2503 { 2504 struct ieee80211com *ic = &sc->sc_ic; 2505 2506 iwn_read_prom_data(sc, addr, &sc->eeprom_channels[n], 2507 iwn_bands[n].nchan * sizeof (struct iwn_eeprom_chan)); 2508 2509 if (n < 5) 2510 iwn_read_eeprom_band(sc, n); 2511 else 2512 iwn_read_eeprom_ht40(sc, n); 2513 ieee80211_sort_channels(ic->ic_channels, ic->ic_nchans); 2514 } 2515 2516 static struct iwn_eeprom_chan * 2517 iwn_find_eeprom_channel(struct iwn_softc *sc, struct ieee80211_channel *c) 2518 { 2519 int band, chan, i, j; 2520 2521 if (IEEE80211_IS_CHAN_HT40(c)) { 2522 band = IEEE80211_IS_CHAN_5GHZ(c) ? 6 : 5; 2523 if (IEEE80211_IS_CHAN_HT40D(c)) 2524 chan = c->ic_extieee; 2525 else 2526 chan = c->ic_ieee; 2527 for (i = 0; i < iwn_bands[band].nchan; i++) { 2528 if (iwn_bands[band].chan[i] == chan) 2529 return &sc->eeprom_channels[band][i]; 2530 } 2531 } else { 2532 for (j = 0; j < 5; j++) { 2533 for (i = 0; i < iwn_bands[j].nchan; i++) { 2534 if (iwn_bands[j].chan[i] == c->ic_ieee) 2535 return &sc->eeprom_channels[j][i]; 2536 } 2537 } 2538 } 2539 return NULL; 2540 } 2541 2542 /* 2543 * Enforce flags read from EEPROM. 2544 */ 2545 static int 2546 iwn_setregdomain(struct ieee80211com *ic, struct ieee80211_regdomain *rd, 2547 int nchan, struct ieee80211_channel chans[]) 2548 { 2549 struct iwn_softc *sc = ic->ic_softc; 2550 int i; 2551 2552 for (i = 0; i < nchan; i++) { 2553 struct ieee80211_channel *c = &chans[i]; 2554 struct iwn_eeprom_chan *channel; 2555 2556 channel = iwn_find_eeprom_channel(sc, c); 2557 if (channel == NULL) { 2558 ic_printf(ic, "%s: invalid channel %u freq %u/0x%x\n", 2559 __func__, c->ic_ieee, c->ic_freq, c->ic_flags); 2560 return EINVAL; 2561 } 2562 c->ic_flags |= iwn_eeprom_channel_flags(channel); 2563 } 2564 2565 return 0; 2566 } 2567 2568 static void 2569 iwn_read_eeprom_enhinfo(struct iwn_softc *sc) 2570 { 2571 struct iwn_eeprom_enhinfo enhinfo[35]; 2572 struct ieee80211com *ic = &sc->sc_ic; 2573 struct ieee80211_channel *c; 2574 uint16_t val, base; 2575 int8_t maxpwr; 2576 uint8_t flags; 2577 int i, j; 2578 2579 DPRINTF(sc, IWN_DEBUG_TRACE, "->%s begin\n", __func__); 2580 2581 iwn_read_prom_data(sc, IWN5000_EEPROM_REG, &val, 2); 2582 base = le16toh(val); 2583 iwn_read_prom_data(sc, base + IWN6000_EEPROM_ENHINFO, 2584 enhinfo, sizeof enhinfo); 2585 2586 for (i = 0; i < nitems(enhinfo); i++) { 2587 flags = enhinfo[i].flags; 2588 if (!(flags & IWN_ENHINFO_VALID)) 2589 continue; /* Skip invalid entries. */ 2590 2591 maxpwr = 0; 2592 if (sc->txchainmask & IWN_ANT_A) 2593 maxpwr = MAX(maxpwr, enhinfo[i].chain[0]); 2594 if (sc->txchainmask & IWN_ANT_B) 2595 maxpwr = MAX(maxpwr, enhinfo[i].chain[1]); 2596 if (sc->txchainmask & IWN_ANT_C) 2597 maxpwr = MAX(maxpwr, enhinfo[i].chain[2]); 2598 if (sc->ntxchains == 2) 2599 maxpwr = MAX(maxpwr, enhinfo[i].mimo2); 2600 else if (sc->ntxchains == 3) 2601 maxpwr = MAX(maxpwr, enhinfo[i].mimo3); 2602 2603 for (j = 0; j < ic->ic_nchans; j++) { 2604 c = &ic->ic_channels[j]; 2605 if ((flags & IWN_ENHINFO_5GHZ)) { 2606 if (!IEEE80211_IS_CHAN_A(c)) 2607 continue; 2608 } else if ((flags & IWN_ENHINFO_OFDM)) { 2609 if (!IEEE80211_IS_CHAN_G(c)) 2610 continue; 2611 } else if (!IEEE80211_IS_CHAN_B(c)) 2612 continue; 2613 if ((flags & IWN_ENHINFO_HT40)) { 2614 if (!IEEE80211_IS_CHAN_HT40(c)) 2615 continue; 2616 } else { 2617 if (IEEE80211_IS_CHAN_HT40(c)) 2618 continue; 2619 } 2620 if (enhinfo[i].chan != 0 && 2621 enhinfo[i].chan != c->ic_ieee) 2622 continue; 2623 2624 DPRINTF(sc, IWN_DEBUG_RESET, 2625 "channel %d(%x), maxpwr %d\n", c->ic_ieee, 2626 c->ic_flags, maxpwr / 2); 2627 c->ic_maxregpower = maxpwr / 2; 2628 c->ic_maxpower = maxpwr; 2629 } 2630 } 2631 2632 DPRINTF(sc, IWN_DEBUG_TRACE, "->%s end\n", __func__); 2633 2634 } 2635 2636 static struct ieee80211_node * 2637 iwn_node_alloc(struct ieee80211vap *vap, const uint8_t mac[IEEE80211_ADDR_LEN]) 2638 { 2639 return malloc(sizeof (struct iwn_node), M_80211_NODE,M_NOWAIT | M_ZERO); 2640 } 2641 2642 static __inline int 2643 rate2plcp(int rate) 2644 { 2645 switch (rate & 0xff) { 2646 case 12: return 0xd; 2647 case 18: return 0xf; 2648 case 24: return 0x5; 2649 case 36: return 0x7; 2650 case 48: return 0x9; 2651 case 72: return 0xb; 2652 case 96: return 0x1; 2653 case 108: return 0x3; 2654 case 2: return 10; 2655 case 4: return 20; 2656 case 11: return 55; 2657 case 22: return 110; 2658 } 2659 return 0; 2660 } 2661 2662 static int 2663 iwn_get_1stream_tx_antmask(struct iwn_softc *sc) 2664 { 2665 2666 return IWN_LSB(sc->txchainmask); 2667 } 2668 2669 static int 2670 iwn_get_2stream_tx_antmask(struct iwn_softc *sc) 2671 { 2672 int tx; 2673 2674 /* 2675 * The '2 stream' setup is a bit .. odd. 2676 * 2677 * For NICs that support only 1 antenna, default to IWN_ANT_AB or 2678 * the firmware panics (eg Intel 5100.) 2679 * 2680 * For NICs that support two antennas, we use ANT_AB. 2681 * 2682 * For NICs that support three antennas, we use the two that 2683 * wasn't the default one. 2684 * 2685 * XXX TODO: if bluetooth (full concurrent) is enabled, restrict 2686 * this to only one antenna. 2687 */ 2688 2689 /* Default - transmit on the other antennas */ 2690 tx = (sc->txchainmask & ~IWN_LSB(sc->txchainmask)); 2691 2692 /* Now, if it's zero, set it to IWN_ANT_AB, so to not panic firmware */ 2693 if (tx == 0) 2694 tx = IWN_ANT_AB; 2695 2696 /* 2697 * If the NIC is a two-stream TX NIC, configure the TX mask to 2698 * the default chainmask 2699 */ 2700 else if (sc->ntxchains == 2) 2701 tx = sc->txchainmask; 2702 2703 return (tx); 2704 } 2705 2706 2707 2708 /* 2709 * Calculate the required PLCP value from the given rate, 2710 * to the given node. 2711 * 2712 * This will take the node configuration (eg 11n, rate table 2713 * setup, etc) into consideration. 2714 */ 2715 static uint32_t 2716 iwn_rate_to_plcp(struct iwn_softc *sc, struct ieee80211_node *ni, 2717 uint8_t rate) 2718 { 2719 #define RV(v) ((v) & IEEE80211_RATE_VAL) 2720 struct ieee80211com *ic = ni->ni_ic; 2721 uint32_t plcp = 0; 2722 int ridx; 2723 2724 /* 2725 * If it's an MCS rate, let's set the plcp correctly 2726 * and set the relevant flags based on the node config. 2727 */ 2728 if (rate & IEEE80211_RATE_MCS) { 2729 /* 2730 * Set the initial PLCP value to be between 0->31 for 2731 * MCS 0 -> MCS 31, then set the "I'm an MCS rate!" 2732 * flag. 2733 */ 2734 plcp = RV(rate) | IWN_RFLAG_MCS; 2735 2736 /* 2737 * XXX the following should only occur if both 2738 * the local configuration _and_ the remote node 2739 * advertise these capabilities. Thus this code 2740 * may need fixing! 2741 */ 2742 2743 /* 2744 * Set the channel width and guard interval. 2745 */ 2746 if (IEEE80211_IS_CHAN_HT40(ni->ni_chan)) { 2747 plcp |= IWN_RFLAG_HT40; 2748 if (ni->ni_htcap & IEEE80211_HTCAP_SHORTGI40) 2749 plcp |= IWN_RFLAG_SGI; 2750 } else if (ni->ni_htcap & IEEE80211_HTCAP_SHORTGI20) { 2751 plcp |= IWN_RFLAG_SGI; 2752 } 2753 2754 /* 2755 * Ensure the selected rate matches the link quality 2756 * table entries being used. 2757 */ 2758 if (rate > 0x8f) 2759 plcp |= IWN_RFLAG_ANT(sc->txchainmask); 2760 else if (rate > 0x87) 2761 plcp |= IWN_RFLAG_ANT(iwn_get_2stream_tx_antmask(sc)); 2762 else 2763 plcp |= IWN_RFLAG_ANT(iwn_get_1stream_tx_antmask(sc)); 2764 } else { 2765 /* 2766 * Set the initial PLCP - fine for both 2767 * OFDM and CCK rates. 2768 */ 2769 plcp = rate2plcp(rate); 2770 2771 /* Set CCK flag if it's CCK */ 2772 2773 /* XXX It would be nice to have a method 2774 * to map the ridx -> phy table entry 2775 * so we could just query that, rather than 2776 * this hack to check against IWN_RIDX_OFDM6. 2777 */ 2778 ridx = ieee80211_legacy_rate_lookup(ic->ic_rt, 2779 rate & IEEE80211_RATE_VAL); 2780 if (ridx < IWN_RIDX_OFDM6 && 2781 IEEE80211_IS_CHAN_2GHZ(ni->ni_chan)) 2782 plcp |= IWN_RFLAG_CCK; 2783 2784 /* Set antenna configuration */ 2785 /* XXX TODO: is this the right antenna to use for legacy? */ 2786 plcp |= IWN_RFLAG_ANT(iwn_get_1stream_tx_antmask(sc)); 2787 } 2788 2789 DPRINTF(sc, IWN_DEBUG_TXRATE, "%s: rate=0x%02x, plcp=0x%08x\n", 2790 __func__, 2791 rate, 2792 plcp); 2793 2794 return (htole32(plcp)); 2795 #undef RV 2796 } 2797 2798 static void 2799 iwn_newassoc(struct ieee80211_node *ni, int isnew) 2800 { 2801 /* Doesn't do anything at the moment */ 2802 } 2803 2804 static int 2805 iwn_media_change(struct ifnet *ifp) 2806 { 2807 int error; 2808 2809 error = ieee80211_media_change(ifp); 2810 /* NB: only the fixed rate can change and that doesn't need a reset */ 2811 return (error == ENETRESET ? 0 : error); 2812 } 2813 2814 static int 2815 iwn_newstate(struct ieee80211vap *vap, enum ieee80211_state nstate, int arg) 2816 { 2817 struct iwn_vap *ivp = IWN_VAP(vap); 2818 struct ieee80211com *ic = vap->iv_ic; 2819 struct iwn_softc *sc = ic->ic_softc; 2820 int error = 0; 2821 2822 DPRINTF(sc, IWN_DEBUG_TRACE, "->%s begin\n", __func__); 2823 2824 DPRINTF(sc, IWN_DEBUG_STATE, "%s: %s -> %s\n", __func__, 2825 ieee80211_state_name[vap->iv_state], ieee80211_state_name[nstate]); 2826 2827 IEEE80211_UNLOCK(ic); 2828 IWN_LOCK(sc); 2829 callout_stop(&sc->calib_to); 2830 2831 sc->rxon = &sc->rx_on[IWN_RXON_BSS_CTX]; 2832 2833 switch (nstate) { 2834 case IEEE80211_S_ASSOC: 2835 if (vap->iv_state != IEEE80211_S_RUN) 2836 break; 2837 /* FALLTHROUGH */ 2838 case IEEE80211_S_AUTH: 2839 if (vap->iv_state == IEEE80211_S_AUTH) 2840 break; 2841 2842 /* 2843 * !AUTH -> AUTH transition requires state reset to handle 2844 * reassociations correctly. 2845 */ 2846 sc->rxon->associd = 0; 2847 sc->rxon->filter &= ~htole32(IWN_FILTER_BSS); 2848 sc->calib.state = IWN_CALIB_STATE_INIT; 2849 2850 /* Wait until we hear a beacon before we transmit */ 2851 sc->sc_beacon_wait = 1; 2852 2853 if ((error = iwn_auth(sc, vap)) != 0) { 2854 device_printf(sc->sc_dev, 2855 "%s: could not move to auth state\n", __func__); 2856 } 2857 break; 2858 2859 case IEEE80211_S_RUN: 2860 /* 2861 * RUN -> RUN transition; Just restart the timers. 2862 */ 2863 if (vap->iv_state == IEEE80211_S_RUN) { 2864 sc->calib_cnt = 0; 2865 break; 2866 } 2867 2868 /* Wait until we hear a beacon before we transmit */ 2869 sc->sc_beacon_wait = 1; 2870 2871 /* 2872 * !RUN -> RUN requires setting the association id 2873 * which is done with a firmware cmd. We also defer 2874 * starting the timers until that work is done. 2875 */ 2876 if ((error = iwn_run(sc, vap)) != 0) { 2877 device_printf(sc->sc_dev, 2878 "%s: could not move to run state\n", __func__); 2879 } 2880 break; 2881 2882 case IEEE80211_S_INIT: 2883 sc->calib.state = IWN_CALIB_STATE_INIT; 2884 /* 2885 * Purge the xmit queue so we don't have old frames 2886 * during a new association attempt. 2887 */ 2888 sc->sc_beacon_wait = 0; 2889 iwn_xmit_queue_drain(sc); 2890 break; 2891 2892 default: 2893 break; 2894 } 2895 IWN_UNLOCK(sc); 2896 IEEE80211_LOCK(ic); 2897 if (error != 0){ 2898 DPRINTF(sc, IWN_DEBUG_TRACE, "->%s end in error\n", __func__); 2899 return error; 2900 } 2901 2902 DPRINTF(sc, IWN_DEBUG_TRACE, "->%s: end\n",__func__); 2903 2904 return ivp->iv_newstate(vap, nstate, arg); 2905 } 2906 2907 static void 2908 iwn_calib_timeout(void *arg) 2909 { 2910 struct iwn_softc *sc = arg; 2911 2912 IWN_LOCK_ASSERT(sc); 2913 2914 /* Force automatic TX power calibration every 60 secs. */ 2915 if (++sc->calib_cnt >= 120) { 2916 uint32_t flags = 0; 2917 2918 DPRINTF(sc, IWN_DEBUG_CALIBRATE, "%s\n", 2919 "sending request for statistics"); 2920 (void)iwn_cmd(sc, IWN_CMD_GET_STATISTICS, &flags, 2921 sizeof flags, 1); 2922 sc->calib_cnt = 0; 2923 } 2924 callout_reset(&sc->calib_to, msecs_to_ticks(500), iwn_calib_timeout, 2925 sc); 2926 } 2927 2928 /* 2929 * Process an RX_PHY firmware notification. This is usually immediately 2930 * followed by an MPDU_RX_DONE notification. 2931 */ 2932 static void 2933 iwn_rx_phy(struct iwn_softc *sc, struct iwn_rx_desc *desc, 2934 struct iwn_rx_data *data) 2935 { 2936 struct iwn_rx_stat *stat = (struct iwn_rx_stat *)(desc + 1); 2937 2938 DPRINTF(sc, IWN_DEBUG_CALIBRATE, "%s: received PHY stats\n", __func__); 2939 bus_dmamap_sync(sc->rxq.data_dmat, data->map, BUS_DMASYNC_POSTREAD); 2940 2941 /* Save RX statistics, they will be used on MPDU_RX_DONE. */ 2942 memcpy(&sc->last_rx_stat, stat, sizeof (*stat)); 2943 sc->last_rx_valid = 1; 2944 } 2945 2946 /* 2947 * Process an RX_DONE (4965AGN only) or MPDU_RX_DONE firmware notification. 2948 * Each MPDU_RX_DONE notification must be preceded by an RX_PHY one. 2949 */ 2950 static void 2951 iwn_rx_done(struct iwn_softc *sc, struct iwn_rx_desc *desc, 2952 struct iwn_rx_data *data) 2953 { 2954 struct iwn_ops *ops = &sc->ops; 2955 struct ieee80211com *ic = &sc->sc_ic; 2956 struct iwn_rx_ring *ring = &sc->rxq; 2957 struct ieee80211_frame *wh; 2958 struct ieee80211_node *ni; 2959 struct mbuf *m, *m1; 2960 struct iwn_rx_stat *stat; 2961 caddr_t head; 2962 bus_addr_t paddr; 2963 uint32_t flags; 2964 int error, len, rssi, nf; 2965 2966 DPRINTF(sc, IWN_DEBUG_TRACE, "->%s begin\n", __func__); 2967 2968 if (desc->type == IWN_MPDU_RX_DONE) { 2969 /* Check for prior RX_PHY notification. */ 2970 if (!sc->last_rx_valid) { 2971 DPRINTF(sc, IWN_DEBUG_ANY, 2972 "%s: missing RX_PHY\n", __func__); 2973 return; 2974 } 2975 stat = &sc->last_rx_stat; 2976 } else 2977 stat = (struct iwn_rx_stat *)(desc + 1); 2978 2979 bus_dmamap_sync(ring->data_dmat, data->map, BUS_DMASYNC_POSTREAD); 2980 2981 if (stat->cfg_phy_len > IWN_STAT_MAXLEN) { 2982 device_printf(sc->sc_dev, 2983 "%s: invalid RX statistic header, len %d\n", __func__, 2984 stat->cfg_phy_len); 2985 return; 2986 } 2987 if (desc->type == IWN_MPDU_RX_DONE) { 2988 struct iwn_rx_mpdu *mpdu = (struct iwn_rx_mpdu *)(desc + 1); 2989 head = (caddr_t)(mpdu + 1); 2990 len = le16toh(mpdu->len); 2991 } else { 2992 head = (caddr_t)(stat + 1) + stat->cfg_phy_len; 2993 len = le16toh(stat->len); 2994 } 2995 2996 flags = le32toh(*(uint32_t *)(head + len)); 2997 2998 /* Discard frames with a bad FCS early. */ 2999 if ((flags & IWN_RX_NOERROR) != IWN_RX_NOERROR) { 3000 DPRINTF(sc, IWN_DEBUG_RECV, "%s: RX flags error %x\n", 3001 __func__, flags); 3002 counter_u64_add(ic->ic_ierrors, 1); 3003 return; 3004 } 3005 /* Discard frames that are too short. */ 3006 if (len < sizeof (struct ieee80211_frame_ack)) { 3007 DPRINTF(sc, IWN_DEBUG_RECV, "%s: frame too short: %d\n", 3008 __func__, len); 3009 counter_u64_add(ic->ic_ierrors, 1); 3010 return; 3011 } 3012 3013 m1 = m_getjcl(M_NOWAIT, MT_DATA, M_PKTHDR, IWN_RBUF_SIZE); 3014 if (m1 == NULL) { 3015 DPRINTF(sc, IWN_DEBUG_ANY, "%s: no mbuf to restock ring\n", 3016 __func__); 3017 counter_u64_add(ic->ic_ierrors, 1); 3018 return; 3019 } 3020 bus_dmamap_unload(ring->data_dmat, data->map); 3021 3022 error = bus_dmamap_load(ring->data_dmat, data->map, mtod(m1, void *), 3023 IWN_RBUF_SIZE, iwn_dma_map_addr, &paddr, BUS_DMA_NOWAIT); 3024 if (error != 0 && error != EFBIG) { 3025 device_printf(sc->sc_dev, 3026 "%s: bus_dmamap_load failed, error %d\n", __func__, error); 3027 m_freem(m1); 3028 3029 /* Try to reload the old mbuf. */ 3030 error = bus_dmamap_load(ring->data_dmat, data->map, 3031 mtod(data->m, void *), IWN_RBUF_SIZE, iwn_dma_map_addr, 3032 &paddr, BUS_DMA_NOWAIT); 3033 if (error != 0 && error != EFBIG) { 3034 panic("%s: could not load old RX mbuf", __func__); 3035 } 3036 /* Physical address may have changed. */ 3037 ring->desc[ring->cur] = htole32(paddr >> 8); 3038 bus_dmamap_sync(ring->data_dmat, ring->desc_dma.map, 3039 BUS_DMASYNC_PREWRITE); 3040 counter_u64_add(ic->ic_ierrors, 1); 3041 return; 3042 } 3043 3044 m = data->m; 3045 data->m = m1; 3046 /* Update RX descriptor. */ 3047 ring->desc[ring->cur] = htole32(paddr >> 8); 3048 bus_dmamap_sync(ring->desc_dma.tag, ring->desc_dma.map, 3049 BUS_DMASYNC_PREWRITE); 3050 3051 /* Finalize mbuf. */ 3052 m->m_data = head; 3053 m->m_pkthdr.len = m->m_len = len; 3054 3055 /* Grab a reference to the source node. */ 3056 wh = mtod(m, struct ieee80211_frame *); 3057 if (len >= sizeof(struct ieee80211_frame_min)) 3058 ni = ieee80211_find_rxnode(ic, (struct ieee80211_frame_min *)wh); 3059 else 3060 ni = NULL; 3061 nf = (ni != NULL && ni->ni_vap->iv_state == IEEE80211_S_RUN && 3062 (ic->ic_flags & IEEE80211_F_SCAN) == 0) ? sc->noise : -95; 3063 3064 rssi = ops->get_rssi(sc, stat); 3065 3066 if (ieee80211_radiotap_active(ic)) { 3067 struct iwn_rx_radiotap_header *tap = &sc->sc_rxtap; 3068 3069 tap->wr_flags = 0; 3070 if (stat->flags & htole16(IWN_STAT_FLAG_SHPREAMBLE)) 3071 tap->wr_flags |= IEEE80211_RADIOTAP_F_SHORTPRE; 3072 tap->wr_dbm_antsignal = (int8_t)rssi; 3073 tap->wr_dbm_antnoise = (int8_t)nf; 3074 tap->wr_tsft = stat->tstamp; 3075 switch (stat->rate) { 3076 /* CCK rates. */ 3077 case 10: tap->wr_rate = 2; break; 3078 case 20: tap->wr_rate = 4; break; 3079 case 55: tap->wr_rate = 11; break; 3080 case 110: tap->wr_rate = 22; break; 3081 /* OFDM rates. */ 3082 case 0xd: tap->wr_rate = 12; break; 3083 case 0xf: tap->wr_rate = 18; break; 3084 case 0x5: tap->wr_rate = 24; break; 3085 case 0x7: tap->wr_rate = 36; break; 3086 case 0x9: tap->wr_rate = 48; break; 3087 case 0xb: tap->wr_rate = 72; break; 3088 case 0x1: tap->wr_rate = 96; break; 3089 case 0x3: tap->wr_rate = 108; break; 3090 /* Unknown rate: should not happen. */ 3091 default: tap->wr_rate = 0; 3092 } 3093 } 3094 3095 /* 3096 * If it's a beacon and we're waiting, then do the 3097 * wakeup. This should unblock raw_xmit/start. 3098 */ 3099 if (sc->sc_beacon_wait) { 3100 uint8_t type, subtype; 3101 /* NB: Re-assign wh */ 3102 wh = mtod(m, struct ieee80211_frame *); 3103 type = wh->i_fc[0] & IEEE80211_FC0_TYPE_MASK; 3104 subtype = wh->i_fc[0] & IEEE80211_FC0_SUBTYPE_MASK; 3105 /* 3106 * This assumes at this point we've received our own 3107 * beacon. 3108 */ 3109 DPRINTF(sc, IWN_DEBUG_TRACE, 3110 "%s: beacon_wait, type=%d, subtype=%d\n", 3111 __func__, type, subtype); 3112 if (type == IEEE80211_FC0_TYPE_MGT && 3113 subtype == IEEE80211_FC0_SUBTYPE_BEACON) { 3114 DPRINTF(sc, IWN_DEBUG_TRACE | IWN_DEBUG_XMIT, 3115 "%s: waking things up\n", __func__); 3116 /* queue taskqueue to transmit! */ 3117 taskqueue_enqueue(sc->sc_tq, &sc->sc_xmit_task); 3118 } 3119 } 3120 3121 IWN_UNLOCK(sc); 3122 3123 /* Send the frame to the 802.11 layer. */ 3124 if (ni != NULL) { 3125 if (ni->ni_flags & IEEE80211_NODE_HT) 3126 m->m_flags |= M_AMPDU; 3127 (void)ieee80211_input(ni, m, rssi - nf, nf); 3128 /* Node is no longer needed. */ 3129 ieee80211_free_node(ni); 3130 } else 3131 (void)ieee80211_input_all(ic, m, rssi - nf, nf); 3132 3133 IWN_LOCK(sc); 3134 3135 DPRINTF(sc, IWN_DEBUG_TRACE, "->%s: end\n",__func__); 3136 3137 } 3138 3139 /* Process an incoming Compressed BlockAck. */ 3140 static void 3141 iwn_rx_compressed_ba(struct iwn_softc *sc, struct iwn_rx_desc *desc, 3142 struct iwn_rx_data *data) 3143 { 3144 struct iwn_ops *ops = &sc->ops; 3145 struct iwn_node *wn; 3146 struct ieee80211_node *ni; 3147 struct iwn_compressed_ba *ba = (struct iwn_compressed_ba *)(desc + 1); 3148 struct iwn_tx_ring *txq; 3149 struct iwn_tx_data *txdata; 3150 struct ieee80211_tx_ampdu *tap; 3151 struct mbuf *m; 3152 uint64_t bitmap; 3153 uint16_t ssn; 3154 uint8_t tid; 3155 int ackfailcnt = 0, i, lastidx, qid, *res, shift; 3156 int tx_ok = 0, tx_err = 0; 3157 3158 DPRINTF(sc, IWN_DEBUG_TRACE | IWN_DEBUG_XMIT, "->%s begin\n", __func__); 3159 3160 bus_dmamap_sync(sc->rxq.data_dmat, data->map, BUS_DMASYNC_POSTREAD); 3161 3162 qid = le16toh(ba->qid); 3163 txq = &sc->txq[ba->qid]; 3164 tap = sc->qid2tap[ba->qid]; 3165 tid = tap->txa_tid; 3166 wn = (void *)tap->txa_ni; 3167 3168 res = NULL; 3169 ssn = 0; 3170 if (!IEEE80211_AMPDU_RUNNING(tap)) { 3171 res = tap->txa_private; 3172 ssn = tap->txa_start & 0xfff; 3173 } 3174 3175 for (lastidx = le16toh(ba->ssn) & 0xff; txq->read != lastidx;) { 3176 txdata = &txq->data[txq->read]; 3177 3178 /* Unmap and free mbuf. */ 3179 bus_dmamap_sync(txq->data_dmat, txdata->map, 3180 BUS_DMASYNC_POSTWRITE); 3181 bus_dmamap_unload(txq->data_dmat, txdata->map); 3182 m = txdata->m, txdata->m = NULL; 3183 ni = txdata->ni, txdata->ni = NULL; 3184 3185 KASSERT(ni != NULL, ("no node")); 3186 KASSERT(m != NULL, ("no mbuf")); 3187 3188 DPRINTF(sc, IWN_DEBUG_XMIT, "%s: freeing m=%p\n", __func__, m); 3189 ieee80211_tx_complete(ni, m, 1); 3190 3191 txq->queued--; 3192 txq->read = (txq->read + 1) % IWN_TX_RING_COUNT; 3193 } 3194 3195 if (txq->queued == 0 && res != NULL) { 3196 iwn_nic_lock(sc); 3197 ops->ampdu_tx_stop(sc, qid, tid, ssn); 3198 iwn_nic_unlock(sc); 3199 sc->qid2tap[qid] = NULL; 3200 free(res, M_DEVBUF); 3201 return; 3202 } 3203 3204 if (wn->agg[tid].bitmap == 0) 3205 return; 3206 3207 shift = wn->agg[tid].startidx - ((le16toh(ba->seq) >> 4) & 0xff); 3208 if (shift < 0) 3209 shift += 0x100; 3210 3211 if (wn->agg[tid].nframes > (64 - shift)) 3212 return; 3213 3214 /* 3215 * Walk the bitmap and calculate how many successful and failed 3216 * attempts are made. 3217 * 3218 * Yes, the rate control code doesn't know these are A-MPDU 3219 * subframes and that it's okay to fail some of these. 3220 */ 3221 ni = tap->txa_ni; 3222 bitmap = (le64toh(ba->bitmap) >> shift) & wn->agg[tid].bitmap; 3223 for (i = 0; bitmap; i++) { 3224 if ((bitmap & 1) == 0) { 3225 tx_err ++; 3226 ieee80211_ratectl_tx_complete(ni->ni_vap, ni, 3227 IEEE80211_RATECTL_TX_FAILURE, &ackfailcnt, NULL); 3228 } else { 3229 tx_ok ++; 3230 ieee80211_ratectl_tx_complete(ni->ni_vap, ni, 3231 IEEE80211_RATECTL_TX_SUCCESS, &ackfailcnt, NULL); 3232 } 3233 bitmap >>= 1; 3234 } 3235 3236 DPRINTF(sc, IWN_DEBUG_TRACE | IWN_DEBUG_XMIT, 3237 "->%s: end; %d ok; %d err\n",__func__, tx_ok, tx_err); 3238 3239 } 3240 3241 /* 3242 * Process a CALIBRATION_RESULT notification sent by the initialization 3243 * firmware on response to a CMD_CALIB_CONFIG command (5000 only). 3244 */ 3245 static void 3246 iwn5000_rx_calib_results(struct iwn_softc *sc, struct iwn_rx_desc *desc, 3247 struct iwn_rx_data *data) 3248 { 3249 struct iwn_phy_calib *calib = (struct iwn_phy_calib *)(desc + 1); 3250 int len, idx = -1; 3251 3252 DPRINTF(sc, IWN_DEBUG_TRACE, "->%s begin\n", __func__); 3253 3254 /* Runtime firmware should not send such a notification. */ 3255 if (sc->sc_flags & IWN_FLAG_CALIB_DONE){ 3256 DPRINTF(sc, IWN_DEBUG_TRACE, "->%s received after clib done\n", 3257 __func__); 3258 return; 3259 } 3260 len = (le32toh(desc->len) & 0x3fff) - 4; 3261 bus_dmamap_sync(sc->rxq.data_dmat, data->map, BUS_DMASYNC_POSTREAD); 3262 3263 switch (calib->code) { 3264 case IWN5000_PHY_CALIB_DC: 3265 if (sc->base_params->calib_need & IWN_FLG_NEED_PHY_CALIB_DC) 3266 idx = 0; 3267 break; 3268 case IWN5000_PHY_CALIB_LO: 3269 if (sc->base_params->calib_need & IWN_FLG_NEED_PHY_CALIB_LO) 3270 idx = 1; 3271 break; 3272 case IWN5000_PHY_CALIB_TX_IQ: 3273 if (sc->base_params->calib_need & IWN_FLG_NEED_PHY_CALIB_TX_IQ) 3274 idx = 2; 3275 break; 3276 case IWN5000_PHY_CALIB_TX_IQ_PERIODIC: 3277 if (sc->base_params->calib_need & IWN_FLG_NEED_PHY_CALIB_TX_IQ_PERIODIC) 3278 idx = 3; 3279 break; 3280 case IWN5000_PHY_CALIB_BASE_BAND: 3281 if (sc->base_params->calib_need & IWN_FLG_NEED_PHY_CALIB_BASE_BAND) 3282 idx = 4; 3283 break; 3284 } 3285 if (idx == -1) /* Ignore other results. */ 3286 return; 3287 3288 /* Save calibration result. */ 3289 if (sc->calibcmd[idx].buf != NULL) 3290 free(sc->calibcmd[idx].buf, M_DEVBUF); 3291 sc->calibcmd[idx].buf = malloc(len, M_DEVBUF, M_NOWAIT); 3292 if (sc->calibcmd[idx].buf == NULL) { 3293 DPRINTF(sc, IWN_DEBUG_CALIBRATE, 3294 "not enough memory for calibration result %d\n", 3295 calib->code); 3296 return; 3297 } 3298 DPRINTF(sc, IWN_DEBUG_CALIBRATE, 3299 "saving calibration result idx=%d, code=%d len=%d\n", idx, calib->code, len); 3300 sc->calibcmd[idx].len = len; 3301 memcpy(sc->calibcmd[idx].buf, calib, len); 3302 } 3303 3304 static void 3305 iwn_stats_update(struct iwn_softc *sc, struct iwn_calib_state *calib, 3306 struct iwn_stats *stats, int len) 3307 { 3308 struct iwn_stats_bt *stats_bt; 3309 struct iwn_stats *lstats; 3310 3311 /* 3312 * First - check whether the length is the bluetooth or normal. 3313 * 3314 * If it's normal - just copy it and bump out. 3315 * Otherwise we have to convert things. 3316 */ 3317 3318 if (len == sizeof(struct iwn_stats) + 4) { 3319 memcpy(&sc->last_stat, stats, sizeof(struct iwn_stats)); 3320 sc->last_stat_valid = 1; 3321 return; 3322 } 3323 3324 /* 3325 * If it's not the bluetooth size - log, then just copy. 3326 */ 3327 if (len != sizeof(struct iwn_stats_bt) + 4) { 3328 DPRINTF(sc, IWN_DEBUG_STATS, 3329 "%s: size of rx statistics (%d) not an expected size!\n", 3330 __func__, 3331 len); 3332 memcpy(&sc->last_stat, stats, sizeof(struct iwn_stats)); 3333 sc->last_stat_valid = 1; 3334 return; 3335 } 3336 3337 /* 3338 * Ok. Time to copy. 3339 */ 3340 stats_bt = (struct iwn_stats_bt *) stats; 3341 lstats = &sc->last_stat; 3342 3343 /* flags */ 3344 lstats->flags = stats_bt->flags; 3345 /* rx_bt */ 3346 memcpy(&lstats->rx.ofdm, &stats_bt->rx_bt.ofdm, 3347 sizeof(struct iwn_rx_phy_stats)); 3348 memcpy(&lstats->rx.cck, &stats_bt->rx_bt.cck, 3349 sizeof(struct iwn_rx_phy_stats)); 3350 memcpy(&lstats->rx.general, &stats_bt->rx_bt.general_bt.common, 3351 sizeof(struct iwn_rx_general_stats)); 3352 memcpy(&lstats->rx.ht, &stats_bt->rx_bt.ht, 3353 sizeof(struct iwn_rx_ht_phy_stats)); 3354 /* tx */ 3355 memcpy(&lstats->tx, &stats_bt->tx, 3356 sizeof(struct iwn_tx_stats)); 3357 /* general */ 3358 memcpy(&lstats->general, &stats_bt->general, 3359 sizeof(struct iwn_general_stats)); 3360 3361 /* XXX TODO: Squirrel away the extra bluetooth stats somewhere */ 3362 sc->last_stat_valid = 1; 3363 } 3364 3365 /* 3366 * Process an RX_STATISTICS or BEACON_STATISTICS firmware notification. 3367 * The latter is sent by the firmware after each received beacon. 3368 */ 3369 static void 3370 iwn_rx_statistics(struct iwn_softc *sc, struct iwn_rx_desc *desc, 3371 struct iwn_rx_data *data) 3372 { 3373 struct iwn_ops *ops = &sc->ops; 3374 struct ieee80211com *ic = &sc->sc_ic; 3375 struct ieee80211vap *vap = TAILQ_FIRST(&ic->ic_vaps); 3376 struct iwn_calib_state *calib = &sc->calib; 3377 struct iwn_stats *stats = (struct iwn_stats *)(desc + 1); 3378 struct iwn_stats *lstats; 3379 int temp; 3380 3381 DPRINTF(sc, IWN_DEBUG_TRACE, "->%s begin\n", __func__); 3382 3383 /* Ignore statistics received during a scan. */ 3384 if (vap->iv_state != IEEE80211_S_RUN || 3385 (ic->ic_flags & IEEE80211_F_SCAN)){ 3386 DPRINTF(sc, IWN_DEBUG_TRACE, "->%s received during calib\n", 3387 __func__); 3388 return; 3389 } 3390 3391 bus_dmamap_sync(sc->rxq.data_dmat, data->map, BUS_DMASYNC_POSTREAD); 3392 3393 DPRINTF(sc, IWN_DEBUG_CALIBRATE | IWN_DEBUG_STATS, 3394 "%s: received statistics, cmd %d, len %d\n", 3395 __func__, desc->type, le16toh(desc->len)); 3396 sc->calib_cnt = 0; /* Reset TX power calibration timeout. */ 3397 3398 /* 3399 * Collect/track general statistics for reporting. 3400 * 3401 * This takes care of ensuring that the bluetooth sized message 3402 * will be correctly converted to the legacy sized message. 3403 */ 3404 iwn_stats_update(sc, calib, stats, le16toh(desc->len)); 3405 3406 /* 3407 * And now, let's take a reference of it to use! 3408 */ 3409 lstats = &sc->last_stat; 3410 3411 /* Test if temperature has changed. */ 3412 if (lstats->general.temp != sc->rawtemp) { 3413 /* Convert "raw" temperature to degC. */ 3414 sc->rawtemp = stats->general.temp; 3415 temp = ops->get_temperature(sc); 3416 DPRINTF(sc, IWN_DEBUG_CALIBRATE, "%s: temperature %d\n", 3417 __func__, temp); 3418 3419 /* Update TX power if need be (4965AGN only). */ 3420 if (sc->hw_type == IWN_HW_REV_TYPE_4965) 3421 iwn4965_power_calibration(sc, temp); 3422 } 3423 3424 if (desc->type != IWN_BEACON_STATISTICS) 3425 return; /* Reply to a statistics request. */ 3426 3427 sc->noise = iwn_get_noise(&lstats->rx.general); 3428 DPRINTF(sc, IWN_DEBUG_CALIBRATE, "%s: noise %d\n", __func__, sc->noise); 3429 3430 /* Test that RSSI and noise are present in stats report. */ 3431 if (le32toh(lstats->rx.general.flags) != 1) { 3432 DPRINTF(sc, IWN_DEBUG_ANY, "%s\n", 3433 "received statistics without RSSI"); 3434 return; 3435 } 3436 3437 if (calib->state == IWN_CALIB_STATE_ASSOC) 3438 iwn_collect_noise(sc, &lstats->rx.general); 3439 else if (calib->state == IWN_CALIB_STATE_RUN) { 3440 iwn_tune_sensitivity(sc, &lstats->rx); 3441 /* 3442 * XXX TODO: Only run the RX recovery if we're associated! 3443 */ 3444 iwn_check_rx_recovery(sc, lstats); 3445 iwn_save_stats_counters(sc, lstats); 3446 } 3447 3448 DPRINTF(sc, IWN_DEBUG_TRACE, "->%s: end\n",__func__); 3449 } 3450 3451 /* 3452 * Save the relevant statistic counters for the next calibration 3453 * pass. 3454 */ 3455 static void 3456 iwn_save_stats_counters(struct iwn_softc *sc, const struct iwn_stats *rs) 3457 { 3458 struct iwn_calib_state *calib = &sc->calib; 3459 3460 /* Save counters values for next call. */ 3461 calib->bad_plcp_cck = le32toh(rs->rx.cck.bad_plcp); 3462 calib->fa_cck = le32toh(rs->rx.cck.fa); 3463 calib->bad_plcp_ht = le32toh(rs->rx.ht.bad_plcp); 3464 calib->bad_plcp_ofdm = le32toh(rs->rx.ofdm.bad_plcp); 3465 calib->fa_ofdm = le32toh(rs->rx.ofdm.fa); 3466 3467 /* Last time we received these tick values */ 3468 sc->last_calib_ticks = ticks; 3469 } 3470 3471 /* 3472 * Process a TX_DONE firmware notification. Unfortunately, the 4965AGN 3473 * and 5000 adapters have different incompatible TX status formats. 3474 */ 3475 static void 3476 iwn4965_tx_done(struct iwn_softc *sc, struct iwn_rx_desc *desc, 3477 struct iwn_rx_data *data) 3478 { 3479 struct iwn4965_tx_stat *stat = (struct iwn4965_tx_stat *)(desc + 1); 3480 struct iwn_tx_ring *ring; 3481 int qid; 3482 3483 qid = desc->qid & 0xf; 3484 ring = &sc->txq[qid]; 3485 3486 DPRINTF(sc, IWN_DEBUG_XMIT, "%s: " 3487 "qid %d idx %d RTS retries %d ACK retries %d nkill %d rate %x duration %d status %x\n", 3488 __func__, desc->qid, desc->idx, 3489 stat->rtsfailcnt, 3490 stat->ackfailcnt, 3491 stat->btkillcnt, 3492 stat->rate, le16toh(stat->duration), 3493 le32toh(stat->status)); 3494 3495 bus_dmamap_sync(ring->data_dmat, data->map, BUS_DMASYNC_POSTREAD); 3496 if (qid >= sc->firstaggqueue) { 3497 iwn_ampdu_tx_done(sc, qid, desc->idx, stat->nframes, 3498 stat->ackfailcnt, &stat->status); 3499 } else { 3500 iwn_tx_done(sc, desc, stat->ackfailcnt, 3501 le32toh(stat->status) & 0xff); 3502 } 3503 } 3504 3505 static void 3506 iwn5000_tx_done(struct iwn_softc *sc, struct iwn_rx_desc *desc, 3507 struct iwn_rx_data *data) 3508 { 3509 struct iwn5000_tx_stat *stat = (struct iwn5000_tx_stat *)(desc + 1); 3510 struct iwn_tx_ring *ring; 3511 int qid; 3512 3513 qid = desc->qid & 0xf; 3514 ring = &sc->txq[qid]; 3515 3516 DPRINTF(sc, IWN_DEBUG_XMIT, "%s: " 3517 "qid %d idx %d RTS retries %d ACK retries %d nkill %d rate %x duration %d status %x\n", 3518 __func__, desc->qid, desc->idx, 3519 stat->rtsfailcnt, 3520 stat->ackfailcnt, 3521 stat->btkillcnt, 3522 stat->rate, le16toh(stat->duration), 3523 le32toh(stat->status)); 3524 3525 #ifdef notyet 3526 /* Reset TX scheduler slot. */ 3527 iwn5000_reset_sched(sc, desc->qid & 0xf, desc->idx); 3528 #endif 3529 3530 bus_dmamap_sync(ring->data_dmat, data->map, BUS_DMASYNC_POSTREAD); 3531 if (qid >= sc->firstaggqueue) { 3532 iwn_ampdu_tx_done(sc, qid, desc->idx, stat->nframes, 3533 stat->ackfailcnt, &stat->status); 3534 } else { 3535 iwn_tx_done(sc, desc, stat->ackfailcnt, 3536 le16toh(stat->status) & 0xff); 3537 } 3538 } 3539 3540 /* 3541 * Adapter-independent backend for TX_DONE firmware notifications. 3542 */ 3543 static void 3544 iwn_tx_done(struct iwn_softc *sc, struct iwn_rx_desc *desc, int ackfailcnt, 3545 uint8_t status) 3546 { 3547 struct iwn_tx_ring *ring = &sc->txq[desc->qid & 0xf]; 3548 struct iwn_tx_data *data = &ring->data[desc->idx]; 3549 struct mbuf *m; 3550 struct ieee80211_node *ni; 3551 struct ieee80211vap *vap; 3552 3553 KASSERT(data->ni != NULL, ("no node")); 3554 3555 DPRINTF(sc, IWN_DEBUG_TRACE, "->%s begin\n", __func__); 3556 3557 /* Unmap and free mbuf. */ 3558 bus_dmamap_sync(ring->data_dmat, data->map, BUS_DMASYNC_POSTWRITE); 3559 bus_dmamap_unload(ring->data_dmat, data->map); 3560 m = data->m, data->m = NULL; 3561 ni = data->ni, data->ni = NULL; 3562 vap = ni->ni_vap; 3563 3564 /* 3565 * Update rate control statistics for the node. 3566 */ 3567 if (status & IWN_TX_FAIL) 3568 ieee80211_ratectl_tx_complete(vap, ni, 3569 IEEE80211_RATECTL_TX_FAILURE, &ackfailcnt, NULL); 3570 else 3571 ieee80211_ratectl_tx_complete(vap, ni, 3572 IEEE80211_RATECTL_TX_SUCCESS, &ackfailcnt, NULL); 3573 3574 /* 3575 * Channels marked for "radar" require traffic to be received 3576 * to unlock before we can transmit. Until traffic is seen 3577 * any attempt to transmit is returned immediately with status 3578 * set to IWN_TX_FAIL_TX_LOCKED. Unfortunately this can easily 3579 * happen on first authenticate after scanning. To workaround 3580 * this we ignore a failure of this sort in AUTH state so the 3581 * 802.11 layer will fall back to using a timeout to wait for 3582 * the AUTH reply. This allows the firmware time to see 3583 * traffic so a subsequent retry of AUTH succeeds. It's 3584 * unclear why the firmware does not maintain state for 3585 * channels recently visited as this would allow immediate 3586 * use of the channel after a scan (where we see traffic). 3587 */ 3588 if (status == IWN_TX_FAIL_TX_LOCKED && 3589 ni->ni_vap->iv_state == IEEE80211_S_AUTH) 3590 ieee80211_tx_complete(ni, m, 0); 3591 else 3592 ieee80211_tx_complete(ni, m, 3593 (status & IWN_TX_FAIL) != 0); 3594 3595 sc->sc_tx_timer = 0; 3596 if (--ring->queued < IWN_TX_RING_LOMARK) 3597 sc->qfullmsk &= ~(1 << ring->qid); 3598 3599 DPRINTF(sc, IWN_DEBUG_TRACE, "->%s: end\n",__func__); 3600 } 3601 3602 /* 3603 * Process a "command done" firmware notification. This is where we wakeup 3604 * processes waiting for a synchronous command completion. 3605 */ 3606 static void 3607 iwn_cmd_done(struct iwn_softc *sc, struct iwn_rx_desc *desc) 3608 { 3609 struct iwn_tx_ring *ring; 3610 struct iwn_tx_data *data; 3611 int cmd_queue_num; 3612 3613 if (sc->sc_flags & IWN_FLAG_PAN_SUPPORT) 3614 cmd_queue_num = IWN_PAN_CMD_QUEUE; 3615 else 3616 cmd_queue_num = IWN_CMD_QUEUE_NUM; 3617 3618 if ((desc->qid & IWN_RX_DESC_QID_MSK) != cmd_queue_num) 3619 return; /* Not a command ack. */ 3620 3621 ring = &sc->txq[cmd_queue_num]; 3622 data = &ring->data[desc->idx]; 3623 3624 /* If the command was mapped in an mbuf, free it. */ 3625 if (data->m != NULL) { 3626 bus_dmamap_sync(ring->data_dmat, data->map, 3627 BUS_DMASYNC_POSTWRITE); 3628 bus_dmamap_unload(ring->data_dmat, data->map); 3629 m_freem(data->m); 3630 data->m = NULL; 3631 } 3632 wakeup(&ring->desc[desc->idx]); 3633 } 3634 3635 static void 3636 iwn_ampdu_tx_done(struct iwn_softc *sc, int qid, int idx, int nframes, 3637 int ackfailcnt, void *stat) 3638 { 3639 struct iwn_ops *ops = &sc->ops; 3640 struct iwn_tx_ring *ring = &sc->txq[qid]; 3641 struct iwn_tx_data *data; 3642 struct mbuf *m; 3643 struct iwn_node *wn; 3644 struct ieee80211_node *ni; 3645 struct ieee80211_tx_ampdu *tap; 3646 uint64_t bitmap; 3647 uint32_t *status = stat; 3648 uint16_t *aggstatus = stat; 3649 uint16_t ssn; 3650 uint8_t tid; 3651 int bit, i, lastidx, *res, seqno, shift, start; 3652 3653 /* XXX TODO: status is le16 field! Grr */ 3654 3655 DPRINTF(sc, IWN_DEBUG_TRACE, "->%s begin\n", __func__); 3656 DPRINTF(sc, IWN_DEBUG_XMIT, "%s: nframes=%d, status=0x%08x\n", 3657 __func__, 3658 nframes, 3659 *status); 3660 3661 tap = sc->qid2tap[qid]; 3662 tid = tap->txa_tid; 3663 wn = (void *)tap->txa_ni; 3664 ni = tap->txa_ni; 3665 3666 /* 3667 * XXX TODO: ACK and RTS failures would be nice here! 3668 */ 3669 3670 /* 3671 * A-MPDU single frame status - if we failed to transmit it 3672 * in A-MPDU, then it may be a permanent failure. 3673 * 3674 * XXX TODO: check what the Linux iwlwifi driver does here; 3675 * there's some permanent and temporary failures that may be 3676 * handled differently. 3677 */ 3678 if (nframes == 1) { 3679 if ((*status & 0xff) != 1 && (*status & 0xff) != 2) { 3680 #ifdef NOT_YET 3681 printf("ieee80211_send_bar()\n"); 3682 #endif 3683 /* 3684 * If we completely fail a transmit, make sure a 3685 * notification is pushed up to the rate control 3686 * layer. 3687 */ 3688 ieee80211_ratectl_tx_complete(ni->ni_vap, 3689 ni, 3690 IEEE80211_RATECTL_TX_FAILURE, 3691 &ackfailcnt, 3692 NULL); 3693 } else { 3694 /* 3695 * If nframes=1, then we won't be getting a BA for 3696 * this frame. Ensure that we correctly update the 3697 * rate control code with how many retries were 3698 * needed to send it. 3699 */ 3700 ieee80211_ratectl_tx_complete(ni->ni_vap, 3701 ni, 3702 IEEE80211_RATECTL_TX_SUCCESS, 3703 &ackfailcnt, 3704 NULL); 3705 } 3706 } 3707 3708 bitmap = 0; 3709 start = idx; 3710 for (i = 0; i < nframes; i++) { 3711 if (le16toh(aggstatus[i * 2]) & 0xc) 3712 continue; 3713 3714 idx = le16toh(aggstatus[2*i + 1]) & 0xff; 3715 bit = idx - start; 3716 shift = 0; 3717 if (bit >= 64) { 3718 shift = 0x100 - idx + start; 3719 bit = 0; 3720 start = idx; 3721 } else if (bit <= -64) 3722 bit = 0x100 - start + idx; 3723 else if (bit < 0) { 3724 shift = start - idx; 3725 start = idx; 3726 bit = 0; 3727 } 3728 bitmap = bitmap << shift; 3729 bitmap |= 1ULL << bit; 3730 } 3731 tap = sc->qid2tap[qid]; 3732 tid = tap->txa_tid; 3733 wn = (void *)tap->txa_ni; 3734 wn->agg[tid].bitmap = bitmap; 3735 wn->agg[tid].startidx = start; 3736 wn->agg[tid].nframes = nframes; 3737 3738 res = NULL; 3739 ssn = 0; 3740 if (!IEEE80211_AMPDU_RUNNING(tap)) { 3741 res = tap->txa_private; 3742 ssn = tap->txa_start & 0xfff; 3743 } 3744 3745 /* This is going nframes DWORDS into the descriptor? */ 3746 seqno = le32toh(*(status + nframes)) & 0xfff; 3747 for (lastidx = (seqno & 0xff); ring->read != lastidx;) { 3748 data = &ring->data[ring->read]; 3749 3750 /* Unmap and free mbuf. */ 3751 bus_dmamap_sync(ring->data_dmat, data->map, 3752 BUS_DMASYNC_POSTWRITE); 3753 bus_dmamap_unload(ring->data_dmat, data->map); 3754 m = data->m, data->m = NULL; 3755 ni = data->ni, data->ni = NULL; 3756 3757 KASSERT(ni != NULL, ("no node")); 3758 KASSERT(m != NULL, ("no mbuf")); 3759 DPRINTF(sc, IWN_DEBUG_XMIT, "%s: freeing m=%p\n", __func__, m); 3760 ieee80211_tx_complete(ni, m, 1); 3761 3762 ring->queued--; 3763 ring->read = (ring->read + 1) % IWN_TX_RING_COUNT; 3764 } 3765 3766 if (ring->queued == 0 && res != NULL) { 3767 iwn_nic_lock(sc); 3768 ops->ampdu_tx_stop(sc, qid, tid, ssn); 3769 iwn_nic_unlock(sc); 3770 sc->qid2tap[qid] = NULL; 3771 free(res, M_DEVBUF); 3772 return; 3773 } 3774 3775 sc->sc_tx_timer = 0; 3776 if (ring->queued < IWN_TX_RING_LOMARK) 3777 sc->qfullmsk &= ~(1 << ring->qid); 3778 3779 DPRINTF(sc, IWN_DEBUG_TRACE, "->%s: end\n",__func__); 3780 } 3781 3782 /* 3783 * Process an INT_FH_RX or INT_SW_RX interrupt. 3784 */ 3785 static void 3786 iwn_notif_intr(struct iwn_softc *sc) 3787 { 3788 struct iwn_ops *ops = &sc->ops; 3789 struct ieee80211com *ic = &sc->sc_ic; 3790 struct ieee80211vap *vap = TAILQ_FIRST(&ic->ic_vaps); 3791 uint16_t hw; 3792 3793 bus_dmamap_sync(sc->rxq.stat_dma.tag, sc->rxq.stat_dma.map, 3794 BUS_DMASYNC_POSTREAD); 3795 3796 hw = le16toh(sc->rxq.stat->closed_count) & 0xfff; 3797 while (sc->rxq.cur != hw) { 3798 struct iwn_rx_data *data = &sc->rxq.data[sc->rxq.cur]; 3799 struct iwn_rx_desc *desc; 3800 3801 bus_dmamap_sync(sc->rxq.data_dmat, data->map, 3802 BUS_DMASYNC_POSTREAD); 3803 desc = mtod(data->m, struct iwn_rx_desc *); 3804 3805 DPRINTF(sc, IWN_DEBUG_RECV, 3806 "%s: cur=%d; qid %x idx %d flags %x type %d(%s) len %d\n", 3807 __func__, sc->rxq.cur, desc->qid & 0xf, desc->idx, desc->flags, 3808 desc->type, iwn_intr_str(desc->type), 3809 le16toh(desc->len)); 3810 3811 if (!(desc->qid & IWN_UNSOLICITED_RX_NOTIF)) /* Reply to a command. */ 3812 iwn_cmd_done(sc, desc); 3813 3814 switch (desc->type) { 3815 case IWN_RX_PHY: 3816 iwn_rx_phy(sc, desc, data); 3817 break; 3818 3819 case IWN_RX_DONE: /* 4965AGN only. */ 3820 case IWN_MPDU_RX_DONE: 3821 /* An 802.11 frame has been received. */ 3822 iwn_rx_done(sc, desc, data); 3823 break; 3824 3825 case IWN_RX_COMPRESSED_BA: 3826 /* A Compressed BlockAck has been received. */ 3827 iwn_rx_compressed_ba(sc, desc, data); 3828 break; 3829 3830 case IWN_TX_DONE: 3831 /* An 802.11 frame has been transmitted. */ 3832 ops->tx_done(sc, desc, data); 3833 break; 3834 3835 case IWN_RX_STATISTICS: 3836 case IWN_BEACON_STATISTICS: 3837 iwn_rx_statistics(sc, desc, data); 3838 break; 3839 3840 case IWN_BEACON_MISSED: 3841 { 3842 struct iwn_beacon_missed *miss = 3843 (struct iwn_beacon_missed *)(desc + 1); 3844 int misses; 3845 3846 bus_dmamap_sync(sc->rxq.data_dmat, data->map, 3847 BUS_DMASYNC_POSTREAD); 3848 misses = le32toh(miss->consecutive); 3849 3850 DPRINTF(sc, IWN_DEBUG_STATE, 3851 "%s: beacons missed %d/%d\n", __func__, 3852 misses, le32toh(miss->total)); 3853 /* 3854 * If more than 5 consecutive beacons are missed, 3855 * reinitialize the sensitivity state machine. 3856 */ 3857 if (vap->iv_state == IEEE80211_S_RUN && 3858 (ic->ic_flags & IEEE80211_F_SCAN) == 0) { 3859 if (misses > 5) 3860 (void)iwn_init_sensitivity(sc); 3861 if (misses >= vap->iv_bmissthreshold) { 3862 IWN_UNLOCK(sc); 3863 ieee80211_beacon_miss(ic); 3864 IWN_LOCK(sc); 3865 } 3866 } 3867 break; 3868 } 3869 case IWN_UC_READY: 3870 { 3871 struct iwn_ucode_info *uc = 3872 (struct iwn_ucode_info *)(desc + 1); 3873 3874 /* The microcontroller is ready. */ 3875 bus_dmamap_sync(sc->rxq.data_dmat, data->map, 3876 BUS_DMASYNC_POSTREAD); 3877 DPRINTF(sc, IWN_DEBUG_RESET, 3878 "microcode alive notification version=%d.%d " 3879 "subtype=%x alive=%x\n", uc->major, uc->minor, 3880 uc->subtype, le32toh(uc->valid)); 3881 3882 if (le32toh(uc->valid) != 1) { 3883 device_printf(sc->sc_dev, 3884 "microcontroller initialization failed"); 3885 break; 3886 } 3887 if (uc->subtype == IWN_UCODE_INIT) { 3888 /* Save microcontroller report. */ 3889 memcpy(&sc->ucode_info, uc, sizeof (*uc)); 3890 } 3891 /* Save the address of the error log in SRAM. */ 3892 sc->errptr = le32toh(uc->errptr); 3893 break; 3894 } 3895 case IWN_STATE_CHANGED: 3896 { 3897 /* 3898 * State change allows hardware switch change to be 3899 * noted. However, we handle this in iwn_intr as we 3900 * get both the enable/disble intr. 3901 */ 3902 bus_dmamap_sync(sc->rxq.data_dmat, data->map, 3903 BUS_DMASYNC_POSTREAD); 3904 #ifdef IWN_DEBUG 3905 uint32_t *status = (uint32_t *)(desc + 1); 3906 DPRINTF(sc, IWN_DEBUG_INTR | IWN_DEBUG_STATE, 3907 "state changed to %x\n", 3908 le32toh(*status)); 3909 #endif 3910 break; 3911 } 3912 case IWN_START_SCAN: 3913 { 3914 bus_dmamap_sync(sc->rxq.data_dmat, data->map, 3915 BUS_DMASYNC_POSTREAD); 3916 #ifdef IWN_DEBUG 3917 struct iwn_start_scan *scan = 3918 (struct iwn_start_scan *)(desc + 1); 3919 DPRINTF(sc, IWN_DEBUG_ANY, 3920 "%s: scanning channel %d status %x\n", 3921 __func__, scan->chan, le32toh(scan->status)); 3922 #endif 3923 break; 3924 } 3925 case IWN_STOP_SCAN: 3926 { 3927 bus_dmamap_sync(sc->rxq.data_dmat, data->map, 3928 BUS_DMASYNC_POSTREAD); 3929 #ifdef IWN_DEBUG 3930 struct iwn_stop_scan *scan = 3931 (struct iwn_stop_scan *)(desc + 1); 3932 DPRINTF(sc, IWN_DEBUG_STATE | IWN_DEBUG_SCAN, 3933 "scan finished nchan=%d status=%d chan=%d\n", 3934 scan->nchan, scan->status, scan->chan); 3935 #endif 3936 sc->sc_is_scanning = 0; 3937 IWN_UNLOCK(sc); 3938 ieee80211_scan_next(vap); 3939 IWN_LOCK(sc); 3940 break; 3941 } 3942 case IWN5000_CALIBRATION_RESULT: 3943 iwn5000_rx_calib_results(sc, desc, data); 3944 break; 3945 3946 case IWN5000_CALIBRATION_DONE: 3947 sc->sc_flags |= IWN_FLAG_CALIB_DONE; 3948 wakeup(sc); 3949 break; 3950 } 3951 3952 sc->rxq.cur = (sc->rxq.cur + 1) % IWN_RX_RING_COUNT; 3953 } 3954 3955 /* Tell the firmware what we have processed. */ 3956 hw = (hw == 0) ? IWN_RX_RING_COUNT - 1 : hw - 1; 3957 IWN_WRITE(sc, IWN_FH_RX_WPTR, hw & ~7); 3958 } 3959 3960 /* 3961 * Process an INT_WAKEUP interrupt raised when the microcontroller wakes up 3962 * from power-down sleep mode. 3963 */ 3964 static void 3965 iwn_wakeup_intr(struct iwn_softc *sc) 3966 { 3967 int qid; 3968 3969 DPRINTF(sc, IWN_DEBUG_RESET, "%s: ucode wakeup from power-down sleep\n", 3970 __func__); 3971 3972 /* Wakeup RX and TX rings. */ 3973 IWN_WRITE(sc, IWN_FH_RX_WPTR, sc->rxq.cur & ~7); 3974 for (qid = 0; qid < sc->ntxqs; qid++) { 3975 struct iwn_tx_ring *ring = &sc->txq[qid]; 3976 IWN_WRITE(sc, IWN_HBUS_TARG_WRPTR, qid << 8 | ring->cur); 3977 } 3978 } 3979 3980 static void 3981 iwn_rftoggle_intr(struct iwn_softc *sc) 3982 { 3983 struct ieee80211com *ic = &sc->sc_ic; 3984 uint32_t tmp = IWN_READ(sc, IWN_GP_CNTRL); 3985 3986 IWN_LOCK_ASSERT(sc); 3987 3988 device_printf(sc->sc_dev, "RF switch: radio %s\n", 3989 (tmp & IWN_GP_CNTRL_RFKILL) ? "enabled" : "disabled"); 3990 if (tmp & IWN_GP_CNTRL_RFKILL) 3991 ieee80211_runtask(ic, &sc->sc_radioon_task); 3992 else 3993 ieee80211_runtask(ic, &sc->sc_radiooff_task); 3994 } 3995 3996 /* 3997 * Dump the error log of the firmware when a firmware panic occurs. Although 3998 * we can't debug the firmware because it is neither open source nor free, it 3999 * can help us to identify certain classes of problems. 4000 */ 4001 static void 4002 iwn_fatal_intr(struct iwn_softc *sc) 4003 { 4004 struct iwn_fw_dump dump; 4005 int i; 4006 4007 IWN_LOCK_ASSERT(sc); 4008 4009 /* Force a complete recalibration on next init. */ 4010 sc->sc_flags &= ~IWN_FLAG_CALIB_DONE; 4011 4012 /* Check that the error log address is valid. */ 4013 if (sc->errptr < IWN_FW_DATA_BASE || 4014 sc->errptr + sizeof (dump) > 4015 IWN_FW_DATA_BASE + sc->fw_data_maxsz) { 4016 printf("%s: bad firmware error log address 0x%08x\n", __func__, 4017 sc->errptr); 4018 return; 4019 } 4020 if (iwn_nic_lock(sc) != 0) { 4021 printf("%s: could not read firmware error log\n", __func__); 4022 return; 4023 } 4024 /* Read firmware error log from SRAM. */ 4025 iwn_mem_read_region_4(sc, sc->errptr, (uint32_t *)&dump, 4026 sizeof (dump) / sizeof (uint32_t)); 4027 iwn_nic_unlock(sc); 4028 4029 if (dump.valid == 0) { 4030 printf("%s: firmware error log is empty\n", __func__); 4031 return; 4032 } 4033 printf("firmware error log:\n"); 4034 printf(" error type = \"%s\" (0x%08X)\n", 4035 (dump.id < nitems(iwn_fw_errmsg)) ? 4036 iwn_fw_errmsg[dump.id] : "UNKNOWN", 4037 dump.id); 4038 printf(" program counter = 0x%08X\n", dump.pc); 4039 printf(" source line = 0x%08X\n", dump.src_line); 4040 printf(" error data = 0x%08X%08X\n", 4041 dump.error_data[0], dump.error_data[1]); 4042 printf(" branch link = 0x%08X%08X\n", 4043 dump.branch_link[0], dump.branch_link[1]); 4044 printf(" interrupt link = 0x%08X%08X\n", 4045 dump.interrupt_link[0], dump.interrupt_link[1]); 4046 printf(" time = %u\n", dump.time[0]); 4047 4048 /* Dump driver status (TX and RX rings) while we're here. */ 4049 printf("driver status:\n"); 4050 for (i = 0; i < sc->ntxqs; i++) { 4051 struct iwn_tx_ring *ring = &sc->txq[i]; 4052 printf(" tx ring %2d: qid=%-2d cur=%-3d queued=%-3d\n", 4053 i, ring->qid, ring->cur, ring->queued); 4054 } 4055 printf(" rx ring: cur=%d\n", sc->rxq.cur); 4056 } 4057 4058 static void 4059 iwn_intr(void *arg) 4060 { 4061 struct iwn_softc *sc = arg; 4062 uint32_t r1, r2, tmp; 4063 4064 IWN_LOCK(sc); 4065 4066 /* Disable interrupts. */ 4067 IWN_WRITE(sc, IWN_INT_MASK, 0); 4068 4069 /* Read interrupts from ICT (fast) or from registers (slow). */ 4070 if (sc->sc_flags & IWN_FLAG_USE_ICT) { 4071 tmp = 0; 4072 while (sc->ict[sc->ict_cur] != 0) { 4073 tmp |= sc->ict[sc->ict_cur]; 4074 sc->ict[sc->ict_cur] = 0; /* Acknowledge. */ 4075 sc->ict_cur = (sc->ict_cur + 1) % IWN_ICT_COUNT; 4076 } 4077 tmp = le32toh(tmp); 4078 if (tmp == 0xffffffff) /* Shouldn't happen. */ 4079 tmp = 0; 4080 else if (tmp & 0xc0000) /* Workaround a HW bug. */ 4081 tmp |= 0x8000; 4082 r1 = (tmp & 0xff00) << 16 | (tmp & 0xff); 4083 r2 = 0; /* Unused. */ 4084 } else { 4085 r1 = IWN_READ(sc, IWN_INT); 4086 if (r1 == 0xffffffff || (r1 & 0xfffffff0) == 0xa5a5a5a0) { 4087 IWN_UNLOCK(sc); 4088 return; /* Hardware gone! */ 4089 } 4090 r2 = IWN_READ(sc, IWN_FH_INT); 4091 } 4092 4093 DPRINTF(sc, IWN_DEBUG_INTR, "interrupt reg1=0x%08x reg2=0x%08x\n" 4094 , r1, r2); 4095 4096 if (r1 == 0 && r2 == 0) 4097 goto done; /* Interrupt not for us. */ 4098 4099 /* Acknowledge interrupts. */ 4100 IWN_WRITE(sc, IWN_INT, r1); 4101 if (!(sc->sc_flags & IWN_FLAG_USE_ICT)) 4102 IWN_WRITE(sc, IWN_FH_INT, r2); 4103 4104 if (r1 & IWN_INT_RF_TOGGLED) { 4105 iwn_rftoggle_intr(sc); 4106 goto done; 4107 } 4108 if (r1 & IWN_INT_CT_REACHED) { 4109 device_printf(sc->sc_dev, "%s: critical temperature reached!\n", 4110 __func__); 4111 } 4112 if (r1 & (IWN_INT_SW_ERR | IWN_INT_HW_ERR)) { 4113 device_printf(sc->sc_dev, "%s: fatal firmware error\n", 4114 __func__); 4115 #ifdef IWN_DEBUG 4116 iwn_debug_register(sc); 4117 #endif 4118 /* Dump firmware error log and stop. */ 4119 iwn_fatal_intr(sc); 4120 4121 taskqueue_enqueue(sc->sc_tq, &sc->sc_panic_task); 4122 goto done; 4123 } 4124 if ((r1 & (IWN_INT_FH_RX | IWN_INT_SW_RX | IWN_INT_RX_PERIODIC)) || 4125 (r2 & IWN_FH_INT_RX)) { 4126 if (sc->sc_flags & IWN_FLAG_USE_ICT) { 4127 if (r1 & (IWN_INT_FH_RX | IWN_INT_SW_RX)) 4128 IWN_WRITE(sc, IWN_FH_INT, IWN_FH_INT_RX); 4129 IWN_WRITE_1(sc, IWN_INT_PERIODIC, 4130 IWN_INT_PERIODIC_DIS); 4131 iwn_notif_intr(sc); 4132 if (r1 & (IWN_INT_FH_RX | IWN_INT_SW_RX)) { 4133 IWN_WRITE_1(sc, IWN_INT_PERIODIC, 4134 IWN_INT_PERIODIC_ENA); 4135 } 4136 } else 4137 iwn_notif_intr(sc); 4138 } 4139 4140 if ((r1 & IWN_INT_FH_TX) || (r2 & IWN_FH_INT_TX)) { 4141 if (sc->sc_flags & IWN_FLAG_USE_ICT) 4142 IWN_WRITE(sc, IWN_FH_INT, IWN_FH_INT_TX); 4143 wakeup(sc); /* FH DMA transfer completed. */ 4144 } 4145 4146 if (r1 & IWN_INT_ALIVE) 4147 wakeup(sc); /* Firmware is alive. */ 4148 4149 if (r1 & IWN_INT_WAKEUP) 4150 iwn_wakeup_intr(sc); 4151 4152 done: 4153 /* Re-enable interrupts. */ 4154 if (sc->sc_flags & IWN_FLAG_RUNNING) 4155 IWN_WRITE(sc, IWN_INT_MASK, sc->int_mask); 4156 4157 IWN_UNLOCK(sc); 4158 } 4159 4160 /* 4161 * Update TX scheduler ring when transmitting an 802.11 frame (4965AGN and 4162 * 5000 adapters use a slightly different format). 4163 */ 4164 static void 4165 iwn4965_update_sched(struct iwn_softc *sc, int qid, int idx, uint8_t id, 4166 uint16_t len) 4167 { 4168 uint16_t *w = &sc->sched[qid * IWN4965_SCHED_COUNT + idx]; 4169 4170 DPRINTF(sc, IWN_DEBUG_TRACE, "->Doing %s\n", __func__); 4171 4172 *w = htole16(len + 8); 4173 bus_dmamap_sync(sc->sched_dma.tag, sc->sched_dma.map, 4174 BUS_DMASYNC_PREWRITE); 4175 if (idx < IWN_SCHED_WINSZ) { 4176 *(w + IWN_TX_RING_COUNT) = *w; 4177 bus_dmamap_sync(sc->sched_dma.tag, sc->sched_dma.map, 4178 BUS_DMASYNC_PREWRITE); 4179 } 4180 } 4181 4182 static void 4183 iwn5000_update_sched(struct iwn_softc *sc, int qid, int idx, uint8_t id, 4184 uint16_t len) 4185 { 4186 uint16_t *w = &sc->sched[qid * IWN5000_SCHED_COUNT + idx]; 4187 4188 DPRINTF(sc, IWN_DEBUG_TRACE, "->Doing %s\n", __func__); 4189 4190 *w = htole16(id << 12 | (len + 8)); 4191 bus_dmamap_sync(sc->sched_dma.tag, sc->sched_dma.map, 4192 BUS_DMASYNC_PREWRITE); 4193 if (idx < IWN_SCHED_WINSZ) { 4194 *(w + IWN_TX_RING_COUNT) = *w; 4195 bus_dmamap_sync(sc->sched_dma.tag, sc->sched_dma.map, 4196 BUS_DMASYNC_PREWRITE); 4197 } 4198 } 4199 4200 #ifdef notyet 4201 static void 4202 iwn5000_reset_sched(struct iwn_softc *sc, int qid, int idx) 4203 { 4204 uint16_t *w = &sc->sched[qid * IWN5000_SCHED_COUNT + idx]; 4205 4206 DPRINTF(sc, IWN_DEBUG_TRACE, "->Doing %s\n", __func__); 4207 4208 *w = (*w & htole16(0xf000)) | htole16(1); 4209 bus_dmamap_sync(sc->sched_dma.tag, sc->sched_dma.map, 4210 BUS_DMASYNC_PREWRITE); 4211 if (idx < IWN_SCHED_WINSZ) { 4212 *(w + IWN_TX_RING_COUNT) = *w; 4213 bus_dmamap_sync(sc->sched_dma.tag, sc->sched_dma.map, 4214 BUS_DMASYNC_PREWRITE); 4215 } 4216 } 4217 #endif 4218 4219 /* 4220 * Check whether OFDM 11g protection will be enabled for the given rate. 4221 * 4222 * The original driver code only enabled protection for OFDM rates. 4223 * It didn't check to see whether it was operating in 11a or 11bg mode. 4224 */ 4225 static int 4226 iwn_check_rate_needs_protection(struct iwn_softc *sc, 4227 struct ieee80211vap *vap, uint8_t rate) 4228 { 4229 struct ieee80211com *ic = vap->iv_ic; 4230 4231 /* 4232 * Not in 2GHz mode? Then there's no need to enable OFDM 4233 * 11bg protection. 4234 */ 4235 if (! IEEE80211_IS_CHAN_2GHZ(ic->ic_curchan)) { 4236 return (0); 4237 } 4238 4239 /* 4240 * 11bg protection not enabled? Then don't use it. 4241 */ 4242 if ((ic->ic_flags & IEEE80211_F_USEPROT) == 0) 4243 return (0); 4244 4245 /* 4246 * If it's an 11n rate - no protection. 4247 * We'll do it via a specific 11n check. 4248 */ 4249 if (rate & IEEE80211_RATE_MCS) { 4250 return (0); 4251 } 4252 4253 /* 4254 * Do a rate table lookup. If the PHY is CCK, 4255 * don't do protection. 4256 */ 4257 if (ieee80211_rate2phytype(ic->ic_rt, rate) == IEEE80211_T_CCK) 4258 return (0); 4259 4260 /* 4261 * Yup, enable protection. 4262 */ 4263 return (1); 4264 } 4265 4266 /* 4267 * return a value between 0 and IWN_MAX_TX_RETRIES-1 as an index into 4268 * the link quality table that reflects this particular entry. 4269 */ 4270 static int 4271 iwn_tx_rate_to_linkq_offset(struct iwn_softc *sc, struct ieee80211_node *ni, 4272 uint8_t rate) 4273 { 4274 struct ieee80211_rateset *rs; 4275 int is_11n; 4276 int nr; 4277 int i; 4278 uint8_t cmp_rate; 4279 4280 /* 4281 * Figure out if we're using 11n or not here. 4282 */ 4283 if (IEEE80211_IS_CHAN_HT(ni->ni_chan) && ni->ni_htrates.rs_nrates > 0) 4284 is_11n = 1; 4285 else 4286 is_11n = 0; 4287 4288 /* 4289 * Use the correct rate table. 4290 */ 4291 if (is_11n) { 4292 rs = (struct ieee80211_rateset *) &ni->ni_htrates; 4293 nr = ni->ni_htrates.rs_nrates; 4294 } else { 4295 rs = &ni->ni_rates; 4296 nr = rs->rs_nrates; 4297 } 4298 4299 /* 4300 * Find the relevant link quality entry in the table. 4301 */ 4302 for (i = 0; i < nr && i < IWN_MAX_TX_RETRIES - 1 ; i++) { 4303 /* 4304 * The link quality table index starts at 0 == highest 4305 * rate, so we walk the rate table backwards. 4306 */ 4307 cmp_rate = rs->rs_rates[(nr - 1) - i]; 4308 if (rate & IEEE80211_RATE_MCS) 4309 cmp_rate |= IEEE80211_RATE_MCS; 4310 4311 #if 0 4312 DPRINTF(sc, IWN_DEBUG_XMIT, "%s: idx %d: nr=%d, rate=0x%02x, rateentry=0x%02x\n", 4313 __func__, 4314 i, 4315 nr, 4316 rate, 4317 cmp_rate); 4318 #endif 4319 4320 if (cmp_rate == rate) 4321 return (i); 4322 } 4323 4324 /* Failed? Start at the end */ 4325 return (IWN_MAX_TX_RETRIES - 1); 4326 } 4327 4328 static int 4329 iwn_tx_data(struct iwn_softc *sc, struct mbuf *m, struct ieee80211_node *ni) 4330 { 4331 struct iwn_ops *ops = &sc->ops; 4332 const struct ieee80211_txparam *tp; 4333 struct ieee80211vap *vap = ni->ni_vap; 4334 struct ieee80211com *ic = ni->ni_ic; 4335 struct iwn_node *wn = (void *)ni; 4336 struct iwn_tx_ring *ring; 4337 struct iwn_tx_desc *desc; 4338 struct iwn_tx_data *data; 4339 struct iwn_tx_cmd *cmd; 4340 struct iwn_cmd_data *tx; 4341 struct ieee80211_frame *wh; 4342 struct ieee80211_key *k = NULL; 4343 struct mbuf *m1; 4344 uint32_t flags; 4345 uint16_t qos; 4346 u_int hdrlen; 4347 bus_dma_segment_t *seg, segs[IWN_MAX_SCATTER]; 4348 uint8_t tid, type; 4349 int ac, i, totlen, error, pad, nsegs = 0, rate; 4350 4351 DPRINTF(sc, IWN_DEBUG_TRACE, "->%s begin\n", __func__); 4352 4353 IWN_LOCK_ASSERT(sc); 4354 4355 wh = mtod(m, struct ieee80211_frame *); 4356 hdrlen = ieee80211_anyhdrsize(wh); 4357 type = wh->i_fc[0] & IEEE80211_FC0_TYPE_MASK; 4358 4359 /* Select EDCA Access Category and TX ring for this frame. */ 4360 if (IEEE80211_QOS_HAS_SEQ(wh)) { 4361 qos = ((const struct ieee80211_qosframe *)wh)->i_qos[0]; 4362 tid = qos & IEEE80211_QOS_TID; 4363 } else { 4364 qos = 0; 4365 tid = 0; 4366 } 4367 ac = M_WME_GETAC(m); 4368 if (m->m_flags & M_AMPDU_MPDU) { 4369 uint16_t seqno; 4370 struct ieee80211_tx_ampdu *tap = &ni->ni_tx_ampdu[ac]; 4371 4372 if (!IEEE80211_AMPDU_RUNNING(tap)) { 4373 m_freem(m); 4374 return EINVAL; 4375 } 4376 4377 /* 4378 * Queue this frame to the hardware ring that we've 4379 * negotiated AMPDU TX on. 4380 * 4381 * Note that the sequence number must match the TX slot 4382 * being used! 4383 */ 4384 ac = *(int *)tap->txa_private; 4385 seqno = ni->ni_txseqs[tid]; 4386 *(uint16_t *)wh->i_seq = 4387 htole16(seqno << IEEE80211_SEQ_SEQ_SHIFT); 4388 ring = &sc->txq[ac]; 4389 if ((seqno % 256) != ring->cur) { 4390 device_printf(sc->sc_dev, 4391 "%s: m=%p: seqno (%d) (%d) != ring index (%d) !\n", 4392 __func__, 4393 m, 4394 seqno, 4395 seqno % 256, 4396 ring->cur); 4397 } 4398 ni->ni_txseqs[tid]++; 4399 } 4400 ring = &sc->txq[ac]; 4401 desc = &ring->desc[ring->cur]; 4402 data = &ring->data[ring->cur]; 4403 4404 /* Choose a TX rate index. */ 4405 tp = &vap->iv_txparms[ieee80211_chan2mode(ni->ni_chan)]; 4406 if (type == IEEE80211_FC0_TYPE_MGT) 4407 rate = tp->mgmtrate; 4408 else if (IEEE80211_IS_MULTICAST(wh->i_addr1)) 4409 rate = tp->mcastrate; 4410 else if (tp->ucastrate != IEEE80211_FIXED_RATE_NONE) 4411 rate = tp->ucastrate; 4412 else if (m->m_flags & M_EAPOL) 4413 rate = tp->mgmtrate; 4414 else { 4415 /* XXX pass pktlen */ 4416 (void) ieee80211_ratectl_rate(ni, NULL, 0); 4417 rate = ni->ni_txrate; 4418 } 4419 4420 /* Encrypt the frame if need be. */ 4421 if (wh->i_fc[1] & IEEE80211_FC1_PROTECTED) { 4422 /* Retrieve key for TX. */ 4423 k = ieee80211_crypto_encap(ni, m); 4424 if (k == NULL) { 4425 m_freem(m); 4426 return ENOBUFS; 4427 } 4428 /* 802.11 header may have moved. */ 4429 wh = mtod(m, struct ieee80211_frame *); 4430 } 4431 totlen = m->m_pkthdr.len; 4432 4433 if (ieee80211_radiotap_active_vap(vap)) { 4434 struct iwn_tx_radiotap_header *tap = &sc->sc_txtap; 4435 4436 tap->wt_flags = 0; 4437 tap->wt_rate = rate; 4438 if (k != NULL) 4439 tap->wt_flags |= IEEE80211_RADIOTAP_F_WEP; 4440 4441 ieee80211_radiotap_tx(vap, m); 4442 } 4443 4444 /* Prepare TX firmware command. */ 4445 cmd = &ring->cmd[ring->cur]; 4446 cmd->code = IWN_CMD_TX_DATA; 4447 cmd->flags = 0; 4448 cmd->qid = ring->qid; 4449 cmd->idx = ring->cur; 4450 4451 tx = (struct iwn_cmd_data *)cmd->data; 4452 /* NB: No need to clear tx, all fields are reinitialized here. */ 4453 tx->scratch = 0; /* clear "scratch" area */ 4454 4455 flags = 0; 4456 if (!IEEE80211_IS_MULTICAST(wh->i_addr1)) { 4457 /* Unicast frame, check if an ACK is expected. */ 4458 if (!qos || (qos & IEEE80211_QOS_ACKPOLICY) != 4459 IEEE80211_QOS_ACKPOLICY_NOACK) 4460 flags |= IWN_TX_NEED_ACK; 4461 } 4462 if ((wh->i_fc[0] & 4463 (IEEE80211_FC0_TYPE_MASK | IEEE80211_FC0_SUBTYPE_MASK)) == 4464 (IEEE80211_FC0_TYPE_CTL | IEEE80211_FC0_SUBTYPE_BAR)) 4465 flags |= IWN_TX_IMM_BA; /* Cannot happen yet. */ 4466 4467 if (wh->i_fc[1] & IEEE80211_FC1_MORE_FRAG) 4468 flags |= IWN_TX_MORE_FRAG; /* Cannot happen yet. */ 4469 4470 /* Check if frame must be protected using RTS/CTS or CTS-to-self. */ 4471 if (!IEEE80211_IS_MULTICAST(wh->i_addr1)) { 4472 /* NB: Group frames are sent using CCK in 802.11b/g. */ 4473 if (totlen + IEEE80211_CRC_LEN > vap->iv_rtsthreshold) { 4474 flags |= IWN_TX_NEED_RTS; 4475 } else if (iwn_check_rate_needs_protection(sc, vap, rate)) { 4476 if (ic->ic_protmode == IEEE80211_PROT_CTSONLY) 4477 flags |= IWN_TX_NEED_CTS; 4478 else if (ic->ic_protmode == IEEE80211_PROT_RTSCTS) 4479 flags |= IWN_TX_NEED_RTS; 4480 } else if ((rate & IEEE80211_RATE_MCS) && 4481 (ic->ic_htprotmode == IEEE80211_PROT_RTSCTS)) { 4482 flags |= IWN_TX_NEED_RTS; 4483 } 4484 4485 /* XXX HT protection? */ 4486 4487 if (flags & (IWN_TX_NEED_RTS | IWN_TX_NEED_CTS)) { 4488 if (sc->hw_type != IWN_HW_REV_TYPE_4965) { 4489 /* 5000 autoselects RTS/CTS or CTS-to-self. */ 4490 flags &= ~(IWN_TX_NEED_RTS | IWN_TX_NEED_CTS); 4491 flags |= IWN_TX_NEED_PROTECTION; 4492 } else 4493 flags |= IWN_TX_FULL_TXOP; 4494 } 4495 } 4496 4497 if (IEEE80211_IS_MULTICAST(wh->i_addr1) || 4498 type != IEEE80211_FC0_TYPE_DATA) 4499 tx->id = sc->broadcast_id; 4500 else 4501 tx->id = wn->id; 4502 4503 if (type == IEEE80211_FC0_TYPE_MGT) { 4504 uint8_t subtype = wh->i_fc[0] & IEEE80211_FC0_SUBTYPE_MASK; 4505 4506 /* Tell HW to set timestamp in probe responses. */ 4507 if (subtype == IEEE80211_FC0_SUBTYPE_PROBE_RESP) 4508 flags |= IWN_TX_INSERT_TSTAMP; 4509 if (subtype == IEEE80211_FC0_SUBTYPE_ASSOC_REQ || 4510 subtype == IEEE80211_FC0_SUBTYPE_REASSOC_REQ) 4511 tx->timeout = htole16(3); 4512 else 4513 tx->timeout = htole16(2); 4514 } else 4515 tx->timeout = htole16(0); 4516 4517 if (hdrlen & 3) { 4518 /* First segment length must be a multiple of 4. */ 4519 flags |= IWN_TX_NEED_PADDING; 4520 pad = 4 - (hdrlen & 3); 4521 } else 4522 pad = 0; 4523 4524 tx->len = htole16(totlen); 4525 tx->tid = tid; 4526 tx->rts_ntries = 60; 4527 tx->data_ntries = 15; 4528 tx->lifetime = htole32(IWN_LIFETIME_INFINITE); 4529 tx->rate = iwn_rate_to_plcp(sc, ni, rate); 4530 if (tx->id == sc->broadcast_id) { 4531 /* Group or management frame. */ 4532 tx->linkq = 0; 4533 } else { 4534 tx->linkq = iwn_tx_rate_to_linkq_offset(sc, ni, rate); 4535 flags |= IWN_TX_LINKQ; /* enable MRR */ 4536 } 4537 4538 /* Set physical address of "scratch area". */ 4539 tx->loaddr = htole32(IWN_LOADDR(data->scratch_paddr)); 4540 tx->hiaddr = IWN_HIADDR(data->scratch_paddr); 4541 4542 /* Copy 802.11 header in TX command. */ 4543 memcpy((uint8_t *)(tx + 1), wh, hdrlen); 4544 4545 /* Trim 802.11 header. */ 4546 m_adj(m, hdrlen); 4547 tx->security = 0; 4548 tx->flags = htole32(flags); 4549 4550 error = bus_dmamap_load_mbuf_sg(ring->data_dmat, data->map, m, segs, 4551 &nsegs, BUS_DMA_NOWAIT); 4552 if (error != 0) { 4553 if (error != EFBIG) { 4554 device_printf(sc->sc_dev, 4555 "%s: can't map mbuf (error %d)\n", __func__, error); 4556 m_freem(m); 4557 return error; 4558 } 4559 /* Too many DMA segments, linearize mbuf. */ 4560 m1 = m_collapse(m, M_NOWAIT, IWN_MAX_SCATTER - 1); 4561 if (m1 == NULL) { 4562 device_printf(sc->sc_dev, 4563 "%s: could not defrag mbuf\n", __func__); 4564 m_freem(m); 4565 return ENOBUFS; 4566 } 4567 m = m1; 4568 4569 error = bus_dmamap_load_mbuf_sg(ring->data_dmat, data->map, m, 4570 segs, &nsegs, BUS_DMA_NOWAIT); 4571 if (error != 0) { 4572 device_printf(sc->sc_dev, 4573 "%s: can't map mbuf (error %d)\n", __func__, error); 4574 m_freem(m); 4575 return error; 4576 } 4577 } 4578 4579 data->m = m; 4580 data->ni = ni; 4581 4582 DPRINTF(sc, IWN_DEBUG_XMIT, 4583 "%s: qid %d idx %d len %d nsegs %d flags 0x%08x rate 0x%04x plcp 0x%08x\n", 4584 __func__, 4585 ring->qid, 4586 ring->cur, 4587 m->m_pkthdr.len, 4588 nsegs, 4589 flags, 4590 rate, 4591 tx->rate); 4592 4593 /* Fill TX descriptor. */ 4594 desc->nsegs = 1; 4595 if (m->m_len != 0) 4596 desc->nsegs += nsegs; 4597 /* First DMA segment is used by the TX command. */ 4598 desc->segs[0].addr = htole32(IWN_LOADDR(data->cmd_paddr)); 4599 desc->segs[0].len = htole16(IWN_HIADDR(data->cmd_paddr) | 4600 (4 + sizeof (*tx) + hdrlen + pad) << 4); 4601 /* Other DMA segments are for data payload. */ 4602 seg = &segs[0]; 4603 for (i = 1; i <= nsegs; i++) { 4604 desc->segs[i].addr = htole32(IWN_LOADDR(seg->ds_addr)); 4605 desc->segs[i].len = htole16(IWN_HIADDR(seg->ds_addr) | 4606 seg->ds_len << 4); 4607 seg++; 4608 } 4609 4610 bus_dmamap_sync(ring->data_dmat, data->map, BUS_DMASYNC_PREWRITE); 4611 bus_dmamap_sync(ring->data_dmat, ring->cmd_dma.map, 4612 BUS_DMASYNC_PREWRITE); 4613 bus_dmamap_sync(ring->desc_dma.tag, ring->desc_dma.map, 4614 BUS_DMASYNC_PREWRITE); 4615 4616 /* Update TX scheduler. */ 4617 if (ring->qid >= sc->firstaggqueue) 4618 ops->update_sched(sc, ring->qid, ring->cur, tx->id, totlen); 4619 4620 /* Kick TX ring. */ 4621 ring->cur = (ring->cur + 1) % IWN_TX_RING_COUNT; 4622 IWN_WRITE(sc, IWN_HBUS_TARG_WRPTR, ring->qid << 8 | ring->cur); 4623 4624 /* Mark TX ring as full if we reach a certain threshold. */ 4625 if (++ring->queued > IWN_TX_RING_HIMARK) 4626 sc->qfullmsk |= 1 << ring->qid; 4627 4628 DPRINTF(sc, IWN_DEBUG_TRACE, "->%s: end\n",__func__); 4629 4630 return 0; 4631 } 4632 4633 static int 4634 iwn_tx_data_raw(struct iwn_softc *sc, struct mbuf *m, 4635 struct ieee80211_node *ni, const struct ieee80211_bpf_params *params) 4636 { 4637 struct iwn_ops *ops = &sc->ops; 4638 struct ieee80211vap *vap = ni->ni_vap; 4639 struct iwn_tx_cmd *cmd; 4640 struct iwn_cmd_data *tx; 4641 struct ieee80211_frame *wh; 4642 struct iwn_tx_ring *ring; 4643 struct iwn_tx_desc *desc; 4644 struct iwn_tx_data *data; 4645 struct mbuf *m1; 4646 bus_dma_segment_t *seg, segs[IWN_MAX_SCATTER]; 4647 uint32_t flags; 4648 u_int hdrlen; 4649 int ac, totlen, error, pad, nsegs = 0, i, rate; 4650 uint8_t type; 4651 4652 DPRINTF(sc, IWN_DEBUG_TRACE, "->%s begin\n", __func__); 4653 4654 IWN_LOCK_ASSERT(sc); 4655 4656 wh = mtod(m, struct ieee80211_frame *); 4657 hdrlen = ieee80211_anyhdrsize(wh); 4658 type = wh->i_fc[0] & IEEE80211_FC0_TYPE_MASK; 4659 4660 ac = params->ibp_pri & 3; 4661 4662 ring = &sc->txq[ac]; 4663 desc = &ring->desc[ring->cur]; 4664 data = &ring->data[ring->cur]; 4665 4666 /* Choose a TX rate. */ 4667 rate = params->ibp_rate0; 4668 totlen = m->m_pkthdr.len; 4669 4670 /* Prepare TX firmware command. */ 4671 cmd = &ring->cmd[ring->cur]; 4672 cmd->code = IWN_CMD_TX_DATA; 4673 cmd->flags = 0; 4674 cmd->qid = ring->qid; 4675 cmd->idx = ring->cur; 4676 4677 tx = (struct iwn_cmd_data *)cmd->data; 4678 /* NB: No need to clear tx, all fields are reinitialized here. */ 4679 tx->scratch = 0; /* clear "scratch" area */ 4680 4681 flags = 0; 4682 if ((params->ibp_flags & IEEE80211_BPF_NOACK) == 0) 4683 flags |= IWN_TX_NEED_ACK; 4684 if (params->ibp_flags & IEEE80211_BPF_RTS) { 4685 if (sc->hw_type != IWN_HW_REV_TYPE_4965) { 4686 /* 5000 autoselects RTS/CTS or CTS-to-self. */ 4687 flags &= ~IWN_TX_NEED_RTS; 4688 flags |= IWN_TX_NEED_PROTECTION; 4689 } else 4690 flags |= IWN_TX_NEED_RTS | IWN_TX_FULL_TXOP; 4691 } 4692 if (params->ibp_flags & IEEE80211_BPF_CTS) { 4693 if (sc->hw_type != IWN_HW_REV_TYPE_4965) { 4694 /* 5000 autoselects RTS/CTS or CTS-to-self. */ 4695 flags &= ~IWN_TX_NEED_CTS; 4696 flags |= IWN_TX_NEED_PROTECTION; 4697 } else 4698 flags |= IWN_TX_NEED_CTS | IWN_TX_FULL_TXOP; 4699 } 4700 if (type == IEEE80211_FC0_TYPE_MGT) { 4701 uint8_t subtype = wh->i_fc[0] & IEEE80211_FC0_SUBTYPE_MASK; 4702 4703 /* Tell HW to set timestamp in probe responses. */ 4704 if (subtype == IEEE80211_FC0_SUBTYPE_PROBE_RESP) 4705 flags |= IWN_TX_INSERT_TSTAMP; 4706 4707 if (subtype == IEEE80211_FC0_SUBTYPE_ASSOC_REQ || 4708 subtype == IEEE80211_FC0_SUBTYPE_REASSOC_REQ) 4709 tx->timeout = htole16(3); 4710 else 4711 tx->timeout = htole16(2); 4712 } else 4713 tx->timeout = htole16(0); 4714 4715 if (hdrlen & 3) { 4716 /* First segment length must be a multiple of 4. */ 4717 flags |= IWN_TX_NEED_PADDING; 4718 pad = 4 - (hdrlen & 3); 4719 } else 4720 pad = 0; 4721 4722 if (ieee80211_radiotap_active_vap(vap)) { 4723 struct iwn_tx_radiotap_header *tap = &sc->sc_txtap; 4724 4725 tap->wt_flags = 0; 4726 tap->wt_rate = rate; 4727 4728 ieee80211_radiotap_tx(vap, m); 4729 } 4730 4731 tx->len = htole16(totlen); 4732 tx->tid = 0; 4733 tx->id = sc->broadcast_id; 4734 tx->rts_ntries = params->ibp_try1; 4735 tx->data_ntries = params->ibp_try0; 4736 tx->lifetime = htole32(IWN_LIFETIME_INFINITE); 4737 tx->rate = iwn_rate_to_plcp(sc, ni, rate); 4738 4739 /* Group or management frame. */ 4740 tx->linkq = 0; 4741 4742 /* Set physical address of "scratch area". */ 4743 tx->loaddr = htole32(IWN_LOADDR(data->scratch_paddr)); 4744 tx->hiaddr = IWN_HIADDR(data->scratch_paddr); 4745 4746 /* Copy 802.11 header in TX command. */ 4747 memcpy((uint8_t *)(tx + 1), wh, hdrlen); 4748 4749 /* Trim 802.11 header. */ 4750 m_adj(m, hdrlen); 4751 tx->security = 0; 4752 tx->flags = htole32(flags); 4753 4754 error = bus_dmamap_load_mbuf_sg(ring->data_dmat, data->map, m, segs, 4755 &nsegs, BUS_DMA_NOWAIT); 4756 if (error != 0) { 4757 if (error != EFBIG) { 4758 device_printf(sc->sc_dev, 4759 "%s: can't map mbuf (error %d)\n", __func__, error); 4760 m_freem(m); 4761 return error; 4762 } 4763 /* Too many DMA segments, linearize mbuf. */ 4764 m1 = m_collapse(m, M_NOWAIT, IWN_MAX_SCATTER - 1); 4765 if (m1 == NULL) { 4766 device_printf(sc->sc_dev, 4767 "%s: could not defrag mbuf\n", __func__); 4768 m_freem(m); 4769 return ENOBUFS; 4770 } 4771 m = m1; 4772 4773 error = bus_dmamap_load_mbuf_sg(ring->data_dmat, data->map, m, 4774 segs, &nsegs, BUS_DMA_NOWAIT); 4775 if (error != 0) { 4776 device_printf(sc->sc_dev, 4777 "%s: can't map mbuf (error %d)\n", __func__, error); 4778 m_freem(m); 4779 return error; 4780 } 4781 } 4782 4783 data->m = m; 4784 data->ni = ni; 4785 4786 DPRINTF(sc, IWN_DEBUG_XMIT, "%s: qid %d idx %d len %d nsegs %d\n", 4787 __func__, ring->qid, ring->cur, m->m_pkthdr.len, nsegs); 4788 4789 /* Fill TX descriptor. */ 4790 desc->nsegs = 1; 4791 if (m->m_len != 0) 4792 desc->nsegs += nsegs; 4793 /* First DMA segment is used by the TX command. */ 4794 desc->segs[0].addr = htole32(IWN_LOADDR(data->cmd_paddr)); 4795 desc->segs[0].len = htole16(IWN_HIADDR(data->cmd_paddr) | 4796 (4 + sizeof (*tx) + hdrlen + pad) << 4); 4797 /* Other DMA segments are for data payload. */ 4798 seg = &segs[0]; 4799 for (i = 1; i <= nsegs; i++) { 4800 desc->segs[i].addr = htole32(IWN_LOADDR(seg->ds_addr)); 4801 desc->segs[i].len = htole16(IWN_HIADDR(seg->ds_addr) | 4802 seg->ds_len << 4); 4803 seg++; 4804 } 4805 4806 bus_dmamap_sync(ring->data_dmat, data->map, BUS_DMASYNC_PREWRITE); 4807 bus_dmamap_sync(ring->data_dmat, ring->cmd_dma.map, 4808 BUS_DMASYNC_PREWRITE); 4809 bus_dmamap_sync(ring->desc_dma.tag, ring->desc_dma.map, 4810 BUS_DMASYNC_PREWRITE); 4811 4812 /* Update TX scheduler. */ 4813 if (ring->qid >= sc->firstaggqueue) 4814 ops->update_sched(sc, ring->qid, ring->cur, tx->id, totlen); 4815 4816 /* Kick TX ring. */ 4817 ring->cur = (ring->cur + 1) % IWN_TX_RING_COUNT; 4818 IWN_WRITE(sc, IWN_HBUS_TARG_WRPTR, ring->qid << 8 | ring->cur); 4819 4820 /* Mark TX ring as full if we reach a certain threshold. */ 4821 if (++ring->queued > IWN_TX_RING_HIMARK) 4822 sc->qfullmsk |= 1 << ring->qid; 4823 4824 DPRINTF(sc, IWN_DEBUG_TRACE, "->%s: end\n",__func__); 4825 4826 return 0; 4827 } 4828 4829 static void 4830 iwn_xmit_task(void *arg0, int pending) 4831 { 4832 struct iwn_softc *sc = arg0; 4833 struct ieee80211_node *ni; 4834 struct mbuf *m; 4835 int error; 4836 struct ieee80211_bpf_params p; 4837 int have_p; 4838 4839 DPRINTF(sc, IWN_DEBUG_XMIT, "%s: called\n", __func__); 4840 4841 IWN_LOCK(sc); 4842 /* 4843 * Dequeue frames, attempt to transmit, 4844 * then disable beaconwait when we're done. 4845 */ 4846 while ((m = mbufq_dequeue(&sc->sc_xmit_queue)) != NULL) { 4847 have_p = 0; 4848 ni = (struct ieee80211_node *)m->m_pkthdr.rcvif; 4849 4850 /* Get xmit params if appropriate */ 4851 if (ieee80211_get_xmit_params(m, &p) == 0) 4852 have_p = 1; 4853 4854 DPRINTF(sc, IWN_DEBUG_XMIT, "%s: m=%p, have_p=%d\n", 4855 __func__, m, have_p); 4856 4857 /* If we have xmit params, use them */ 4858 if (have_p) 4859 error = iwn_tx_data_raw(sc, m, ni, &p); 4860 else 4861 error = iwn_tx_data(sc, m, ni); 4862 4863 if (error != 0) { 4864 if_inc_counter(ni->ni_vap->iv_ifp, 4865 IFCOUNTER_OERRORS, 1); 4866 ieee80211_free_node(ni); 4867 } 4868 } 4869 4870 sc->sc_beacon_wait = 0; 4871 IWN_UNLOCK(sc); 4872 } 4873 4874 static int 4875 iwn_raw_xmit(struct ieee80211_node *ni, struct mbuf *m, 4876 const struct ieee80211_bpf_params *params) 4877 { 4878 struct ieee80211com *ic = ni->ni_ic; 4879 struct iwn_softc *sc = ic->ic_softc; 4880 int error = 0; 4881 4882 DPRINTF(sc, IWN_DEBUG_XMIT | IWN_DEBUG_TRACE, "->%s begin\n", __func__); 4883 4884 if ((sc->sc_flags & IWN_FLAG_RUNNING) == 0) { 4885 ieee80211_free_node(ni); 4886 m_freem(m); 4887 return ENETDOWN; 4888 } 4889 4890 /* XXX? net80211 doesn't set this on xmit'ed raw frames? */ 4891 m->m_pkthdr.rcvif = (void *) ni; 4892 4893 IWN_LOCK(sc); 4894 4895 /* queue frame if we have to */ 4896 if (sc->sc_beacon_wait) { 4897 if (iwn_xmit_queue_enqueue(sc, m) != 0) { 4898 m_freem(m); 4899 if_inc_counter(ni->ni_vap->iv_ifp, 4900 IFCOUNTER_OERRORS, 1); 4901 ieee80211_free_node(ni); 4902 IWN_UNLOCK(sc); 4903 return (ENOBUFS); 4904 } 4905 /* Queued, so just return OK */ 4906 IWN_UNLOCK(sc); 4907 return (0); 4908 } 4909 4910 if (params == NULL) { 4911 /* 4912 * Legacy path; interpret frame contents to decide 4913 * precisely how to send the frame. 4914 */ 4915 error = iwn_tx_data(sc, m, ni); 4916 } else { 4917 /* 4918 * Caller supplied explicit parameters to use in 4919 * sending the frame. 4920 */ 4921 error = iwn_tx_data_raw(sc, m, ni, params); 4922 } 4923 if (error != 0) { 4924 /* NB: m is reclaimed on tx failure */ 4925 ieee80211_free_node(ni); 4926 } else 4927 sc->sc_tx_timer = 5; 4928 4929 IWN_UNLOCK(sc); 4930 4931 DPRINTF(sc, IWN_DEBUG_TRACE | IWN_DEBUG_XMIT, "->%s: end\n",__func__); 4932 4933 return error; 4934 } 4935 4936 static int 4937 iwn_transmit(struct ieee80211com *ic, struct mbuf *m) 4938 { 4939 struct iwn_softc *sc = ic->ic_softc; 4940 struct ieee80211_node *ni; 4941 int error; 4942 4943 IWN_LOCK(sc); 4944 if ((sc->sc_flags & IWN_FLAG_RUNNING) == 0 || sc->sc_beacon_wait) { 4945 IWN_UNLOCK(sc); 4946 return (ENXIO); 4947 } 4948 4949 if (sc->qfullmsk) { 4950 IWN_UNLOCK(sc); 4951 return (ENOBUFS); 4952 } 4953 4954 ni = (struct ieee80211_node *)m->m_pkthdr.rcvif; 4955 error = iwn_tx_data(sc, m, ni); 4956 if (error) { 4957 if_inc_counter(ni->ni_vap->iv_ifp, IFCOUNTER_OERRORS, 1); 4958 ieee80211_free_node(ni); 4959 } else 4960 sc->sc_tx_timer = 5; 4961 IWN_UNLOCK(sc); 4962 return (error); 4963 } 4964 4965 static void 4966 iwn_watchdog(void *arg) 4967 { 4968 struct iwn_softc *sc = arg; 4969 struct ieee80211com *ic = &sc->sc_ic; 4970 4971 IWN_LOCK_ASSERT(sc); 4972 4973 KASSERT(sc->sc_flags & IWN_FLAG_RUNNING, ("not running")); 4974 4975 DPRINTF(sc, IWN_DEBUG_TRACE, "->Doing %s\n", __func__); 4976 4977 if (sc->sc_tx_timer > 0) { 4978 if (--sc->sc_tx_timer == 0) { 4979 ic_printf(ic, "device timeout\n"); 4980 ieee80211_runtask(ic, &sc->sc_reinit_task); 4981 return; 4982 } 4983 } 4984 callout_reset(&sc->watchdog_to, hz, iwn_watchdog, sc); 4985 } 4986 4987 static int 4988 iwn_cdev_open(struct cdev *dev, int flags, int type, struct thread *td) 4989 { 4990 4991 return (0); 4992 } 4993 4994 static int 4995 iwn_cdev_close(struct cdev *dev, int flags, int type, struct thread *td) 4996 { 4997 4998 return (0); 4999 } 5000 5001 static int 5002 iwn_cdev_ioctl(struct cdev *dev, unsigned long cmd, caddr_t data, int fflag, 5003 struct thread *td) 5004 { 5005 int rc; 5006 struct iwn_softc *sc = dev->si_drv1; 5007 struct iwn_ioctl_data *d; 5008 5009 rc = priv_check(td, PRIV_DRIVER); 5010 if (rc != 0) 5011 return (0); 5012 5013 switch (cmd) { 5014 case SIOCGIWNSTATS: 5015 d = (struct iwn_ioctl_data *) data; 5016 IWN_LOCK(sc); 5017 /* XXX validate permissions/memory/etc? */ 5018 rc = copyout(&sc->last_stat, d->dst_addr, sizeof(struct iwn_stats)); 5019 IWN_UNLOCK(sc); 5020 break; 5021 case SIOCZIWNSTATS: 5022 IWN_LOCK(sc); 5023 memset(&sc->last_stat, 0, sizeof(struct iwn_stats)); 5024 IWN_UNLOCK(sc); 5025 break; 5026 default: 5027 rc = EINVAL; 5028 break; 5029 } 5030 return (rc); 5031 } 5032 5033 static int 5034 iwn_ioctl(struct ieee80211com *ic, u_long cmd, void *data) 5035 { 5036 5037 return (ENOTTY); 5038 } 5039 5040 static void 5041 iwn_parent(struct ieee80211com *ic) 5042 { 5043 struct iwn_softc *sc = ic->ic_softc; 5044 struct ieee80211vap *vap = TAILQ_FIRST(&ic->ic_vaps); 5045 int startall = 0, stop = 0; 5046 5047 IWN_LOCK(sc); 5048 if (ic->ic_nrunning > 0) { 5049 if (!(sc->sc_flags & IWN_FLAG_RUNNING)) { 5050 iwn_init_locked(sc); 5051 if (IWN_READ(sc, IWN_GP_CNTRL) & IWN_GP_CNTRL_RFKILL) 5052 startall = 1; 5053 else 5054 stop = 1; 5055 } 5056 } else if (sc->sc_flags & IWN_FLAG_RUNNING) 5057 iwn_stop_locked(sc); 5058 IWN_UNLOCK(sc); 5059 if (startall) 5060 ieee80211_start_all(ic); 5061 else if (vap != NULL && stop) 5062 ieee80211_stop(vap); 5063 } 5064 5065 /* 5066 * Send a command to the firmware. 5067 */ 5068 static int 5069 iwn_cmd(struct iwn_softc *sc, int code, const void *buf, int size, int async) 5070 { 5071 struct iwn_tx_ring *ring; 5072 struct iwn_tx_desc *desc; 5073 struct iwn_tx_data *data; 5074 struct iwn_tx_cmd *cmd; 5075 struct mbuf *m; 5076 bus_addr_t paddr; 5077 int totlen, error; 5078 int cmd_queue_num; 5079 5080 DPRINTF(sc, IWN_DEBUG_TRACE, "->%s begin\n", __func__); 5081 5082 if (async == 0) 5083 IWN_LOCK_ASSERT(sc); 5084 5085 if (sc->sc_flags & IWN_FLAG_PAN_SUPPORT) 5086 cmd_queue_num = IWN_PAN_CMD_QUEUE; 5087 else 5088 cmd_queue_num = IWN_CMD_QUEUE_NUM; 5089 5090 ring = &sc->txq[cmd_queue_num]; 5091 desc = &ring->desc[ring->cur]; 5092 data = &ring->data[ring->cur]; 5093 totlen = 4 + size; 5094 5095 if (size > sizeof cmd->data) { 5096 /* Command is too large to fit in a descriptor. */ 5097 if (totlen > MCLBYTES) 5098 return EINVAL; 5099 m = m_getjcl(M_NOWAIT, MT_DATA, M_PKTHDR, MJUMPAGESIZE); 5100 if (m == NULL) 5101 return ENOMEM; 5102 cmd = mtod(m, struct iwn_tx_cmd *); 5103 error = bus_dmamap_load(ring->data_dmat, data->map, cmd, 5104 totlen, iwn_dma_map_addr, &paddr, BUS_DMA_NOWAIT); 5105 if (error != 0) { 5106 m_freem(m); 5107 return error; 5108 } 5109 data->m = m; 5110 } else { 5111 cmd = &ring->cmd[ring->cur]; 5112 paddr = data->cmd_paddr; 5113 } 5114 5115 cmd->code = code; 5116 cmd->flags = 0; 5117 cmd->qid = ring->qid; 5118 cmd->idx = ring->cur; 5119 memcpy(cmd->data, buf, size); 5120 5121 desc->nsegs = 1; 5122 desc->segs[0].addr = htole32(IWN_LOADDR(paddr)); 5123 desc->segs[0].len = htole16(IWN_HIADDR(paddr) | totlen << 4); 5124 5125 DPRINTF(sc, IWN_DEBUG_CMD, "%s: %s (0x%x) flags %d qid %d idx %d\n", 5126 __func__, iwn_intr_str(cmd->code), cmd->code, 5127 cmd->flags, cmd->qid, cmd->idx); 5128 5129 if (size > sizeof cmd->data) { 5130 bus_dmamap_sync(ring->data_dmat, data->map, 5131 BUS_DMASYNC_PREWRITE); 5132 } else { 5133 bus_dmamap_sync(ring->data_dmat, ring->cmd_dma.map, 5134 BUS_DMASYNC_PREWRITE); 5135 } 5136 bus_dmamap_sync(ring->desc_dma.tag, ring->desc_dma.map, 5137 BUS_DMASYNC_PREWRITE); 5138 5139 /* Kick command ring. */ 5140 ring->cur = (ring->cur + 1) % IWN_TX_RING_COUNT; 5141 IWN_WRITE(sc, IWN_HBUS_TARG_WRPTR, ring->qid << 8 | ring->cur); 5142 5143 DPRINTF(sc, IWN_DEBUG_TRACE, "->%s: end\n",__func__); 5144 5145 return async ? 0 : msleep(desc, &sc->sc_mtx, PCATCH, "iwncmd", hz); 5146 } 5147 5148 static int 5149 iwn4965_add_node(struct iwn_softc *sc, struct iwn_node_info *node, int async) 5150 { 5151 struct iwn4965_node_info hnode; 5152 caddr_t src, dst; 5153 5154 DPRINTF(sc, IWN_DEBUG_TRACE, "->Doing %s\n", __func__); 5155 5156 /* 5157 * We use the node structure for 5000 Series internally (it is 5158 * a superset of the one for 4965AGN). We thus copy the common 5159 * fields before sending the command. 5160 */ 5161 src = (caddr_t)node; 5162 dst = (caddr_t)&hnode; 5163 memcpy(dst, src, 48); 5164 /* Skip TSC, RX MIC and TX MIC fields from ``src''. */ 5165 memcpy(dst + 48, src + 72, 20); 5166 return iwn_cmd(sc, IWN_CMD_ADD_NODE, &hnode, sizeof hnode, async); 5167 } 5168 5169 static int 5170 iwn5000_add_node(struct iwn_softc *sc, struct iwn_node_info *node, int async) 5171 { 5172 5173 DPRINTF(sc, IWN_DEBUG_TRACE, "->Doing %s\n", __func__); 5174 5175 /* Direct mapping. */ 5176 return iwn_cmd(sc, IWN_CMD_ADD_NODE, node, sizeof (*node), async); 5177 } 5178 5179 static int 5180 iwn_set_link_quality(struct iwn_softc *sc, struct ieee80211_node *ni) 5181 { 5182 #define RV(v) ((v) & IEEE80211_RATE_VAL) 5183 struct iwn_node *wn = (void *)ni; 5184 struct ieee80211_rateset *rs; 5185 struct iwn_cmd_link_quality linkq; 5186 int i, rate, txrate; 5187 int is_11n; 5188 5189 DPRINTF(sc, IWN_DEBUG_TRACE, "->%s begin\n", __func__); 5190 5191 memset(&linkq, 0, sizeof linkq); 5192 linkq.id = wn->id; 5193 linkq.antmsk_1stream = iwn_get_1stream_tx_antmask(sc); 5194 linkq.antmsk_2stream = iwn_get_2stream_tx_antmask(sc); 5195 5196 linkq.ampdu_max = 32; /* XXX negotiated? */ 5197 linkq.ampdu_threshold = 3; 5198 linkq.ampdu_limit = htole16(4000); /* 4ms */ 5199 5200 DPRINTF(sc, IWN_DEBUG_XMIT, 5201 "%s: 1stream antenna=0x%02x, 2stream antenna=0x%02x, ntxstreams=%d\n", 5202 __func__, 5203 linkq.antmsk_1stream, 5204 linkq.antmsk_2stream, 5205 sc->ntxchains); 5206 5207 /* 5208 * Are we using 11n rates? Ensure the channel is 5209 * 11n _and_ we have some 11n rates, or don't 5210 * try. 5211 */ 5212 if (IEEE80211_IS_CHAN_HT(ni->ni_chan) && ni->ni_htrates.rs_nrates > 0) { 5213 rs = (struct ieee80211_rateset *) &ni->ni_htrates; 5214 is_11n = 1; 5215 } else { 5216 rs = &ni->ni_rates; 5217 is_11n = 0; 5218 } 5219 5220 /* Start at highest available bit-rate. */ 5221 /* 5222 * XXX this is all very dirty! 5223 */ 5224 if (is_11n) 5225 txrate = ni->ni_htrates.rs_nrates - 1; 5226 else 5227 txrate = rs->rs_nrates - 1; 5228 for (i = 0; i < IWN_MAX_TX_RETRIES; i++) { 5229 uint32_t plcp; 5230 5231 /* 5232 * XXX TODO: ensure the last two slots are the two lowest 5233 * rate entries, just for now. 5234 */ 5235 if (i == 14 || i == 15) 5236 txrate = 0; 5237 5238 if (is_11n) 5239 rate = IEEE80211_RATE_MCS | rs->rs_rates[txrate]; 5240 else 5241 rate = RV(rs->rs_rates[txrate]); 5242 5243 /* Do rate -> PLCP config mapping */ 5244 plcp = iwn_rate_to_plcp(sc, ni, rate); 5245 linkq.retry[i] = plcp; 5246 DPRINTF(sc, IWN_DEBUG_XMIT, 5247 "%s: i=%d, txrate=%d, rate=0x%02x, plcp=0x%08x\n", 5248 __func__, 5249 i, 5250 txrate, 5251 rate, 5252 le32toh(plcp)); 5253 5254 /* 5255 * The mimo field is an index into the table which 5256 * indicates the first index where it and subsequent entries 5257 * will not be using MIMO. 5258 * 5259 * Since we're filling linkq from 0..15 and we're filling 5260 * from the higest MCS rates to the lowest rates, if we 5261 * _are_ doing a dual-stream rate, set mimo to idx+1 (ie, 5262 * the next entry.) That way if the next entry is a non-MIMO 5263 * entry, we're already pointing at it. 5264 */ 5265 if ((le32toh(plcp) & IWN_RFLAG_MCS) && 5266 RV(le32toh(plcp)) > 7) 5267 linkq.mimo = i + 1; 5268 5269 /* Next retry at immediate lower bit-rate. */ 5270 if (txrate > 0) 5271 txrate--; 5272 } 5273 /* 5274 * If we reached the end of the list and indeed we hit 5275 * all MIMO rates (eg 5300 doing MCS23-15) then yes, 5276 * set mimo to 15. Setting it to 16 panics the firmware. 5277 */ 5278 if (linkq.mimo > 15) 5279 linkq.mimo = 15; 5280 5281 DPRINTF(sc, IWN_DEBUG_XMIT, "%s: mimo = %d\n", __func__, linkq.mimo); 5282 5283 DPRINTF(sc, IWN_DEBUG_TRACE, "->%s: end\n",__func__); 5284 5285 return iwn_cmd(sc, IWN_CMD_LINK_QUALITY, &linkq, sizeof linkq, 1); 5286 #undef RV 5287 } 5288 5289 /* 5290 * Broadcast node is used to send group-addressed and management frames. 5291 */ 5292 static int 5293 iwn_add_broadcast_node(struct iwn_softc *sc, int async) 5294 { 5295 struct iwn_ops *ops = &sc->ops; 5296 struct ieee80211com *ic = &sc->sc_ic; 5297 struct iwn_node_info node; 5298 struct iwn_cmd_link_quality linkq; 5299 uint8_t txant; 5300 int i, error; 5301 5302 DPRINTF(sc, IWN_DEBUG_TRACE, "->%s begin\n", __func__); 5303 5304 sc->rxon = &sc->rx_on[IWN_RXON_BSS_CTX]; 5305 5306 memset(&node, 0, sizeof node); 5307 IEEE80211_ADDR_COPY(node.macaddr, ieee80211broadcastaddr); 5308 node.id = sc->broadcast_id; 5309 DPRINTF(sc, IWN_DEBUG_RESET, "%s: adding broadcast node\n", __func__); 5310 if ((error = ops->add_node(sc, &node, async)) != 0) 5311 return error; 5312 5313 /* Use the first valid TX antenna. */ 5314 txant = IWN_LSB(sc->txchainmask); 5315 5316 memset(&linkq, 0, sizeof linkq); 5317 linkq.id = sc->broadcast_id; 5318 linkq.antmsk_1stream = iwn_get_1stream_tx_antmask(sc); 5319 linkq.antmsk_2stream = iwn_get_2stream_tx_antmask(sc); 5320 linkq.ampdu_max = 64; 5321 linkq.ampdu_threshold = 3; 5322 linkq.ampdu_limit = htole16(4000); /* 4ms */ 5323 5324 /* Use lowest mandatory bit-rate. */ 5325 /* XXX rate table lookup? */ 5326 if (IEEE80211_IS_CHAN_5GHZ(ic->ic_curchan)) 5327 linkq.retry[0] = htole32(0xd); 5328 else 5329 linkq.retry[0] = htole32(10 | IWN_RFLAG_CCK); 5330 linkq.retry[0] |= htole32(IWN_RFLAG_ANT(txant)); 5331 /* Use same bit-rate for all TX retries. */ 5332 for (i = 1; i < IWN_MAX_TX_RETRIES; i++) { 5333 linkq.retry[i] = linkq.retry[0]; 5334 } 5335 5336 DPRINTF(sc, IWN_DEBUG_TRACE, "->%s: end\n",__func__); 5337 5338 return iwn_cmd(sc, IWN_CMD_LINK_QUALITY, &linkq, sizeof linkq, async); 5339 } 5340 5341 static int 5342 iwn_updateedca(struct ieee80211com *ic) 5343 { 5344 #define IWN_EXP2(x) ((1 << (x)) - 1) /* CWmin = 2^ECWmin - 1 */ 5345 struct iwn_softc *sc = ic->ic_softc; 5346 struct iwn_edca_params cmd; 5347 int aci; 5348 5349 DPRINTF(sc, IWN_DEBUG_TRACE, "->%s begin\n", __func__); 5350 5351 memset(&cmd, 0, sizeof cmd); 5352 cmd.flags = htole32(IWN_EDCA_UPDATE); 5353 for (aci = 0; aci < WME_NUM_AC; aci++) { 5354 const struct wmeParams *ac = 5355 &ic->ic_wme.wme_chanParams.cap_wmeParams[aci]; 5356 cmd.ac[aci].aifsn = ac->wmep_aifsn; 5357 cmd.ac[aci].cwmin = htole16(IWN_EXP2(ac->wmep_logcwmin)); 5358 cmd.ac[aci].cwmax = htole16(IWN_EXP2(ac->wmep_logcwmax)); 5359 cmd.ac[aci].txoplimit = 5360 htole16(IEEE80211_TXOP_TO_US(ac->wmep_txopLimit)); 5361 } 5362 IEEE80211_UNLOCK(ic); 5363 IWN_LOCK(sc); 5364 (void)iwn_cmd(sc, IWN_CMD_EDCA_PARAMS, &cmd, sizeof cmd, 1); 5365 IWN_UNLOCK(sc); 5366 IEEE80211_LOCK(ic); 5367 5368 DPRINTF(sc, IWN_DEBUG_TRACE, "->%s: end\n",__func__); 5369 5370 return 0; 5371 #undef IWN_EXP2 5372 } 5373 5374 static void 5375 iwn_update_mcast(struct ieee80211com *ic) 5376 { 5377 /* Ignore */ 5378 } 5379 5380 static void 5381 iwn_set_led(struct iwn_softc *sc, uint8_t which, uint8_t off, uint8_t on) 5382 { 5383 struct iwn_cmd_led led; 5384 5385 DPRINTF(sc, IWN_DEBUG_TRACE, "->Doing %s\n", __func__); 5386 5387 #if 0 5388 /* XXX don't set LEDs during scan? */ 5389 if (sc->sc_is_scanning) 5390 return; 5391 #endif 5392 5393 /* Clear microcode LED ownership. */ 5394 IWN_CLRBITS(sc, IWN_LED, IWN_LED_BSM_CTRL); 5395 5396 led.which = which; 5397 led.unit = htole32(10000); /* on/off in unit of 100ms */ 5398 led.off = off; 5399 led.on = on; 5400 (void)iwn_cmd(sc, IWN_CMD_SET_LED, &led, sizeof led, 1); 5401 } 5402 5403 /* 5404 * Set the critical temperature at which the firmware will stop the radio 5405 * and notify us. 5406 */ 5407 static int 5408 iwn_set_critical_temp(struct iwn_softc *sc) 5409 { 5410 struct iwn_critical_temp crit; 5411 int32_t temp; 5412 5413 DPRINTF(sc, IWN_DEBUG_TRACE, "->Doing %s\n", __func__); 5414 5415 IWN_WRITE(sc, IWN_UCODE_GP1_CLR, IWN_UCODE_GP1_CTEMP_STOP_RF); 5416 5417 if (sc->hw_type == IWN_HW_REV_TYPE_5150) 5418 temp = (IWN_CTOK(110) - sc->temp_off) * -5; 5419 else if (sc->hw_type == IWN_HW_REV_TYPE_4965) 5420 temp = IWN_CTOK(110); 5421 else 5422 temp = 110; 5423 memset(&crit, 0, sizeof crit); 5424 crit.tempR = htole32(temp); 5425 DPRINTF(sc, IWN_DEBUG_RESET, "setting critical temp to %d\n", temp); 5426 return iwn_cmd(sc, IWN_CMD_SET_CRITICAL_TEMP, &crit, sizeof crit, 0); 5427 } 5428 5429 static int 5430 iwn_set_timing(struct iwn_softc *sc, struct ieee80211_node *ni) 5431 { 5432 struct iwn_cmd_timing cmd; 5433 uint64_t val, mod; 5434 5435 DPRINTF(sc, IWN_DEBUG_TRACE, "->Doing %s\n", __func__); 5436 5437 memset(&cmd, 0, sizeof cmd); 5438 memcpy(&cmd.tstamp, ni->ni_tstamp.data, sizeof (uint64_t)); 5439 cmd.bintval = htole16(ni->ni_intval); 5440 cmd.lintval = htole16(10); 5441 5442 /* Compute remaining time until next beacon. */ 5443 val = (uint64_t)ni->ni_intval * IEEE80211_DUR_TU; 5444 mod = le64toh(cmd.tstamp) % val; 5445 cmd.binitval = htole32((uint32_t)(val - mod)); 5446 5447 DPRINTF(sc, IWN_DEBUG_RESET, "timing bintval=%u tstamp=%ju, init=%u\n", 5448 ni->ni_intval, le64toh(cmd.tstamp), (uint32_t)(val - mod)); 5449 5450 return iwn_cmd(sc, IWN_CMD_TIMING, &cmd, sizeof cmd, 1); 5451 } 5452 5453 static void 5454 iwn4965_power_calibration(struct iwn_softc *sc, int temp) 5455 { 5456 struct ieee80211com *ic = &sc->sc_ic; 5457 5458 DPRINTF(sc, IWN_DEBUG_TRACE, "->Doing %s\n", __func__); 5459 5460 /* Adjust TX power if need be (delta >= 3 degC). */ 5461 DPRINTF(sc, IWN_DEBUG_CALIBRATE, "%s: temperature %d->%d\n", 5462 __func__, sc->temp, temp); 5463 if (abs(temp - sc->temp) >= 3) { 5464 /* Record temperature of last calibration. */ 5465 sc->temp = temp; 5466 (void)iwn4965_set_txpower(sc, ic->ic_bsschan, 1); 5467 } 5468 } 5469 5470 /* 5471 * Set TX power for current channel (each rate has its own power settings). 5472 * This function takes into account the regulatory information from EEPROM, 5473 * the current temperature and the current voltage. 5474 */ 5475 static int 5476 iwn4965_set_txpower(struct iwn_softc *sc, struct ieee80211_channel *ch, 5477 int async) 5478 { 5479 /* Fixed-point arithmetic division using a n-bit fractional part. */ 5480 #define fdivround(a, b, n) \ 5481 ((((1 << n) * (a)) / (b) + (1 << n) / 2) / (1 << n)) 5482 /* Linear interpolation. */ 5483 #define interpolate(x, x1, y1, x2, y2, n) \ 5484 ((y1) + fdivround(((int)(x) - (x1)) * ((y2) - (y1)), (x2) - (x1), n)) 5485 5486 static const int tdiv[IWN_NATTEN_GROUPS] = { 9, 8, 8, 8, 6 }; 5487 struct iwn_ucode_info *uc = &sc->ucode_info; 5488 struct iwn4965_cmd_txpower cmd; 5489 struct iwn4965_eeprom_chan_samples *chans; 5490 const uint8_t *rf_gain, *dsp_gain; 5491 int32_t vdiff, tdiff; 5492 int i, c, grp, maxpwr; 5493 uint8_t chan; 5494 5495 sc->rxon = &sc->rx_on[IWN_RXON_BSS_CTX]; 5496 /* Retrieve current channel from last RXON. */ 5497 chan = sc->rxon->chan; 5498 DPRINTF(sc, IWN_DEBUG_RESET, "setting TX power for channel %d\n", 5499 chan); 5500 5501 memset(&cmd, 0, sizeof cmd); 5502 cmd.band = IEEE80211_IS_CHAN_5GHZ(ch) ? 0 : 1; 5503 cmd.chan = chan; 5504 5505 if (IEEE80211_IS_CHAN_5GHZ(ch)) { 5506 maxpwr = sc->maxpwr5GHz; 5507 rf_gain = iwn4965_rf_gain_5ghz; 5508 dsp_gain = iwn4965_dsp_gain_5ghz; 5509 } else { 5510 maxpwr = sc->maxpwr2GHz; 5511 rf_gain = iwn4965_rf_gain_2ghz; 5512 dsp_gain = iwn4965_dsp_gain_2ghz; 5513 } 5514 5515 /* Compute voltage compensation. */ 5516 vdiff = ((int32_t)le32toh(uc->volt) - sc->eeprom_voltage) / 7; 5517 if (vdiff > 0) 5518 vdiff *= 2; 5519 if (abs(vdiff) > 2) 5520 vdiff = 0; 5521 DPRINTF(sc, IWN_DEBUG_CALIBRATE | IWN_DEBUG_TXPOW, 5522 "%s: voltage compensation=%d (UCODE=%d, EEPROM=%d)\n", 5523 __func__, vdiff, le32toh(uc->volt), sc->eeprom_voltage); 5524 5525 /* Get channel attenuation group. */ 5526 if (chan <= 20) /* 1-20 */ 5527 grp = 4; 5528 else if (chan <= 43) /* 34-43 */ 5529 grp = 0; 5530 else if (chan <= 70) /* 44-70 */ 5531 grp = 1; 5532 else if (chan <= 124) /* 71-124 */ 5533 grp = 2; 5534 else /* 125-200 */ 5535 grp = 3; 5536 DPRINTF(sc, IWN_DEBUG_CALIBRATE | IWN_DEBUG_TXPOW, 5537 "%s: chan %d, attenuation group=%d\n", __func__, chan, grp); 5538 5539 /* Get channel sub-band. */ 5540 for (i = 0; i < IWN_NBANDS; i++) 5541 if (sc->bands[i].lo != 0 && 5542 sc->bands[i].lo <= chan && chan <= sc->bands[i].hi) 5543 break; 5544 if (i == IWN_NBANDS) /* Can't happen in real-life. */ 5545 return EINVAL; 5546 chans = sc->bands[i].chans; 5547 DPRINTF(sc, IWN_DEBUG_CALIBRATE | IWN_DEBUG_TXPOW, 5548 "%s: chan %d sub-band=%d\n", __func__, chan, i); 5549 5550 for (c = 0; c < 2; c++) { 5551 uint8_t power, gain, temp; 5552 int maxchpwr, pwr, ridx, idx; 5553 5554 power = interpolate(chan, 5555 chans[0].num, chans[0].samples[c][1].power, 5556 chans[1].num, chans[1].samples[c][1].power, 1); 5557 gain = interpolate(chan, 5558 chans[0].num, chans[0].samples[c][1].gain, 5559 chans[1].num, chans[1].samples[c][1].gain, 1); 5560 temp = interpolate(chan, 5561 chans[0].num, chans[0].samples[c][1].temp, 5562 chans[1].num, chans[1].samples[c][1].temp, 1); 5563 DPRINTF(sc, IWN_DEBUG_CALIBRATE | IWN_DEBUG_TXPOW, 5564 "%s: Tx chain %d: power=%d gain=%d temp=%d\n", 5565 __func__, c, power, gain, temp); 5566 5567 /* Compute temperature compensation. */ 5568 tdiff = ((sc->temp - temp) * 2) / tdiv[grp]; 5569 DPRINTF(sc, IWN_DEBUG_CALIBRATE | IWN_DEBUG_TXPOW, 5570 "%s: temperature compensation=%d (current=%d, EEPROM=%d)\n", 5571 __func__, tdiff, sc->temp, temp); 5572 5573 for (ridx = 0; ridx <= IWN_RIDX_MAX; ridx++) { 5574 /* Convert dBm to half-dBm. */ 5575 maxchpwr = sc->maxpwr[chan] * 2; 5576 if ((ridx / 8) & 1) 5577 maxchpwr -= 6; /* MIMO 2T: -3dB */ 5578 5579 pwr = maxpwr; 5580 5581 /* Adjust TX power based on rate. */ 5582 if ((ridx % 8) == 5) 5583 pwr -= 15; /* OFDM48: -7.5dB */ 5584 else if ((ridx % 8) == 6) 5585 pwr -= 17; /* OFDM54: -8.5dB */ 5586 else if ((ridx % 8) == 7) 5587 pwr -= 20; /* OFDM60: -10dB */ 5588 else 5589 pwr -= 10; /* Others: -5dB */ 5590 5591 /* Do not exceed channel max TX power. */ 5592 if (pwr > maxchpwr) 5593 pwr = maxchpwr; 5594 5595 idx = gain - (pwr - power) - tdiff - vdiff; 5596 if ((ridx / 8) & 1) /* MIMO */ 5597 idx += (int32_t)le32toh(uc->atten[grp][c]); 5598 5599 if (cmd.band == 0) 5600 idx += 9; /* 5GHz */ 5601 if (ridx == IWN_RIDX_MAX) 5602 idx += 5; /* CCK */ 5603 5604 /* Make sure idx stays in a valid range. */ 5605 if (idx < 0) 5606 idx = 0; 5607 else if (idx > IWN4965_MAX_PWR_INDEX) 5608 idx = IWN4965_MAX_PWR_INDEX; 5609 5610 DPRINTF(sc, IWN_DEBUG_CALIBRATE | IWN_DEBUG_TXPOW, 5611 "%s: Tx chain %d, rate idx %d: power=%d\n", 5612 __func__, c, ridx, idx); 5613 cmd.power[ridx].rf_gain[c] = rf_gain[idx]; 5614 cmd.power[ridx].dsp_gain[c] = dsp_gain[idx]; 5615 } 5616 } 5617 5618 DPRINTF(sc, IWN_DEBUG_CALIBRATE | IWN_DEBUG_TXPOW, 5619 "%s: set tx power for chan %d\n", __func__, chan); 5620 return iwn_cmd(sc, IWN_CMD_TXPOWER, &cmd, sizeof cmd, async); 5621 5622 #undef interpolate 5623 #undef fdivround 5624 } 5625 5626 static int 5627 iwn5000_set_txpower(struct iwn_softc *sc, struct ieee80211_channel *ch, 5628 int async) 5629 { 5630 struct iwn5000_cmd_txpower cmd; 5631 int cmdid; 5632 5633 DPRINTF(sc, IWN_DEBUG_TRACE, "->Doing %s\n", __func__); 5634 5635 /* 5636 * TX power calibration is handled automatically by the firmware 5637 * for 5000 Series. 5638 */ 5639 memset(&cmd, 0, sizeof cmd); 5640 cmd.global_limit = 2 * IWN5000_TXPOWER_MAX_DBM; /* 16 dBm */ 5641 cmd.flags = IWN5000_TXPOWER_NO_CLOSED; 5642 cmd.srv_limit = IWN5000_TXPOWER_AUTO; 5643 DPRINTF(sc, IWN_DEBUG_CALIBRATE | IWN_DEBUG_XMIT, 5644 "%s: setting TX power; rev=%d\n", 5645 __func__, 5646 IWN_UCODE_API(sc->ucode_rev)); 5647 if (IWN_UCODE_API(sc->ucode_rev) == 1) 5648 cmdid = IWN_CMD_TXPOWER_DBM_V1; 5649 else 5650 cmdid = IWN_CMD_TXPOWER_DBM; 5651 return iwn_cmd(sc, cmdid, &cmd, sizeof cmd, async); 5652 } 5653 5654 /* 5655 * Retrieve the maximum RSSI (in dBm) among receivers. 5656 */ 5657 static int 5658 iwn4965_get_rssi(struct iwn_softc *sc, struct iwn_rx_stat *stat) 5659 { 5660 struct iwn4965_rx_phystat *phy = (void *)stat->phybuf; 5661 uint8_t mask, agc; 5662 int rssi; 5663 5664 DPRINTF(sc, IWN_DEBUG_TRACE, "->Doing %s\n", __func__); 5665 5666 mask = (le16toh(phy->antenna) >> 4) & IWN_ANT_ABC; 5667 agc = (le16toh(phy->agc) >> 7) & 0x7f; 5668 5669 rssi = 0; 5670 if (mask & IWN_ANT_A) 5671 rssi = MAX(rssi, phy->rssi[0]); 5672 if (mask & IWN_ANT_B) 5673 rssi = MAX(rssi, phy->rssi[2]); 5674 if (mask & IWN_ANT_C) 5675 rssi = MAX(rssi, phy->rssi[4]); 5676 5677 DPRINTF(sc, IWN_DEBUG_RECV, 5678 "%s: agc %d mask 0x%x rssi %d %d %d result %d\n", __func__, agc, 5679 mask, phy->rssi[0], phy->rssi[2], phy->rssi[4], 5680 rssi - agc - IWN_RSSI_TO_DBM); 5681 return rssi - agc - IWN_RSSI_TO_DBM; 5682 } 5683 5684 static int 5685 iwn5000_get_rssi(struct iwn_softc *sc, struct iwn_rx_stat *stat) 5686 { 5687 struct iwn5000_rx_phystat *phy = (void *)stat->phybuf; 5688 uint8_t agc; 5689 int rssi; 5690 5691 DPRINTF(sc, IWN_DEBUG_TRACE, "->Doing %s\n", __func__); 5692 5693 agc = (le32toh(phy->agc) >> 9) & 0x7f; 5694 5695 rssi = MAX(le16toh(phy->rssi[0]) & 0xff, 5696 le16toh(phy->rssi[1]) & 0xff); 5697 rssi = MAX(le16toh(phy->rssi[2]) & 0xff, rssi); 5698 5699 DPRINTF(sc, IWN_DEBUG_RECV, 5700 "%s: agc %d rssi %d %d %d result %d\n", __func__, agc, 5701 phy->rssi[0], phy->rssi[1], phy->rssi[2], 5702 rssi - agc - IWN_RSSI_TO_DBM); 5703 return rssi - agc - IWN_RSSI_TO_DBM; 5704 } 5705 5706 /* 5707 * Retrieve the average noise (in dBm) among receivers. 5708 */ 5709 static int 5710 iwn_get_noise(const struct iwn_rx_general_stats *stats) 5711 { 5712 int i, total, nbant, noise; 5713 5714 total = nbant = 0; 5715 for (i = 0; i < 3; i++) { 5716 if ((noise = le32toh(stats->noise[i]) & 0xff) == 0) 5717 continue; 5718 total += noise; 5719 nbant++; 5720 } 5721 /* There should be at least one antenna but check anyway. */ 5722 return (nbant == 0) ? -127 : (total / nbant) - 107; 5723 } 5724 5725 /* 5726 * Compute temperature (in degC) from last received statistics. 5727 */ 5728 static int 5729 iwn4965_get_temperature(struct iwn_softc *sc) 5730 { 5731 struct iwn_ucode_info *uc = &sc->ucode_info; 5732 int32_t r1, r2, r3, r4, temp; 5733 5734 DPRINTF(sc, IWN_DEBUG_TRACE, "->Doing %s\n", __func__); 5735 5736 r1 = le32toh(uc->temp[0].chan20MHz); 5737 r2 = le32toh(uc->temp[1].chan20MHz); 5738 r3 = le32toh(uc->temp[2].chan20MHz); 5739 r4 = le32toh(sc->rawtemp); 5740 5741 if (r1 == r3) /* Prevents division by 0 (should not happen). */ 5742 return 0; 5743 5744 /* Sign-extend 23-bit R4 value to 32-bit. */ 5745 r4 = ((r4 & 0xffffff) ^ 0x800000) - 0x800000; 5746 /* Compute temperature in Kelvin. */ 5747 temp = (259 * (r4 - r2)) / (r3 - r1); 5748 temp = (temp * 97) / 100 + 8; 5749 5750 DPRINTF(sc, IWN_DEBUG_ANY, "temperature %dK/%dC\n", temp, 5751 IWN_KTOC(temp)); 5752 return IWN_KTOC(temp); 5753 } 5754 5755 static int 5756 iwn5000_get_temperature(struct iwn_softc *sc) 5757 { 5758 int32_t temp; 5759 5760 DPRINTF(sc, IWN_DEBUG_TRACE, "->Doing %s\n", __func__); 5761 5762 /* 5763 * Temperature is not used by the driver for 5000 Series because 5764 * TX power calibration is handled by firmware. 5765 */ 5766 temp = le32toh(sc->rawtemp); 5767 if (sc->hw_type == IWN_HW_REV_TYPE_5150) { 5768 temp = (temp / -5) + sc->temp_off; 5769 temp = IWN_KTOC(temp); 5770 } 5771 return temp; 5772 } 5773 5774 /* 5775 * Initialize sensitivity calibration state machine. 5776 */ 5777 static int 5778 iwn_init_sensitivity(struct iwn_softc *sc) 5779 { 5780 struct iwn_ops *ops = &sc->ops; 5781 struct iwn_calib_state *calib = &sc->calib; 5782 uint32_t flags; 5783 int error; 5784 5785 DPRINTF(sc, IWN_DEBUG_TRACE, "->Doing %s\n", __func__); 5786 5787 /* Reset calibration state machine. */ 5788 memset(calib, 0, sizeof (*calib)); 5789 calib->state = IWN_CALIB_STATE_INIT; 5790 calib->cck_state = IWN_CCK_STATE_HIFA; 5791 /* Set initial correlation values. */ 5792 calib->ofdm_x1 = sc->limits->min_ofdm_x1; 5793 calib->ofdm_mrc_x1 = sc->limits->min_ofdm_mrc_x1; 5794 calib->ofdm_x4 = sc->limits->min_ofdm_x4; 5795 calib->ofdm_mrc_x4 = sc->limits->min_ofdm_mrc_x4; 5796 calib->cck_x4 = 125; 5797 calib->cck_mrc_x4 = sc->limits->min_cck_mrc_x4; 5798 calib->energy_cck = sc->limits->energy_cck; 5799 5800 /* Write initial sensitivity. */ 5801 if ((error = iwn_send_sensitivity(sc)) != 0) 5802 return error; 5803 5804 /* Write initial gains. */ 5805 if ((error = ops->init_gains(sc)) != 0) 5806 return error; 5807 5808 /* Request statistics at each beacon interval. */ 5809 flags = 0; 5810 DPRINTF(sc, IWN_DEBUG_CALIBRATE, "%s: sending request for statistics\n", 5811 __func__); 5812 return iwn_cmd(sc, IWN_CMD_GET_STATISTICS, &flags, sizeof flags, 1); 5813 } 5814 5815 /* 5816 * Collect noise and RSSI statistics for the first 20 beacons received 5817 * after association and use them to determine connected antennas and 5818 * to set differential gains. 5819 */ 5820 static void 5821 iwn_collect_noise(struct iwn_softc *sc, 5822 const struct iwn_rx_general_stats *stats) 5823 { 5824 struct iwn_ops *ops = &sc->ops; 5825 struct iwn_calib_state *calib = &sc->calib; 5826 struct ieee80211com *ic = &sc->sc_ic; 5827 uint32_t val; 5828 int i; 5829 5830 DPRINTF(sc, IWN_DEBUG_TRACE, "->%s begin\n", __func__); 5831 5832 /* Accumulate RSSI and noise for all 3 antennas. */ 5833 for (i = 0; i < 3; i++) { 5834 calib->rssi[i] += le32toh(stats->rssi[i]) & 0xff; 5835 calib->noise[i] += le32toh(stats->noise[i]) & 0xff; 5836 } 5837 /* NB: We update differential gains only once after 20 beacons. */ 5838 if (++calib->nbeacons < 20) 5839 return; 5840 5841 /* Determine highest average RSSI. */ 5842 val = MAX(calib->rssi[0], calib->rssi[1]); 5843 val = MAX(calib->rssi[2], val); 5844 5845 /* Determine which antennas are connected. */ 5846 sc->chainmask = sc->rxchainmask; 5847 for (i = 0; i < 3; i++) 5848 if (val - calib->rssi[i] > 15 * 20) 5849 sc->chainmask &= ~(1 << i); 5850 DPRINTF(sc, IWN_DEBUG_CALIBRATE | IWN_DEBUG_XMIT, 5851 "%s: RX chains mask: theoretical=0x%x, actual=0x%x\n", 5852 __func__, sc->rxchainmask, sc->chainmask); 5853 5854 /* If none of the TX antennas are connected, keep at least one. */ 5855 if ((sc->chainmask & sc->txchainmask) == 0) 5856 sc->chainmask |= IWN_LSB(sc->txchainmask); 5857 5858 (void)ops->set_gains(sc); 5859 calib->state = IWN_CALIB_STATE_RUN; 5860 5861 #ifdef notyet 5862 /* XXX Disable RX chains with no antennas connected. */ 5863 sc->rxon->rxchain = htole16(IWN_RXCHAIN_SEL(sc->chainmask)); 5864 if (sc->sc_is_scanning) 5865 device_printf(sc->sc_dev, 5866 "%s: is_scanning set, before RXON\n", 5867 __func__); 5868 (void)iwn_cmd(sc, IWN_CMD_RXON, sc->rxon, sc->rxonsz, 1); 5869 #endif 5870 5871 /* Enable power-saving mode if requested by user. */ 5872 if (ic->ic_flags & IEEE80211_F_PMGTON) 5873 (void)iwn_set_pslevel(sc, 0, 3, 1); 5874 5875 DPRINTF(sc, IWN_DEBUG_TRACE, "->%s: end\n",__func__); 5876 5877 } 5878 5879 static int 5880 iwn4965_init_gains(struct iwn_softc *sc) 5881 { 5882 struct iwn_phy_calib_gain cmd; 5883 5884 DPRINTF(sc, IWN_DEBUG_TRACE, "->Doing %s\n", __func__); 5885 5886 memset(&cmd, 0, sizeof cmd); 5887 cmd.code = IWN4965_PHY_CALIB_DIFF_GAIN; 5888 /* Differential gains initially set to 0 for all 3 antennas. */ 5889 DPRINTF(sc, IWN_DEBUG_CALIBRATE, 5890 "%s: setting initial differential gains\n", __func__); 5891 return iwn_cmd(sc, IWN_CMD_PHY_CALIB, &cmd, sizeof cmd, 1); 5892 } 5893 5894 static int 5895 iwn5000_init_gains(struct iwn_softc *sc) 5896 { 5897 struct iwn_phy_calib cmd; 5898 5899 DPRINTF(sc, IWN_DEBUG_TRACE, "->Doing %s\n", __func__); 5900 5901 memset(&cmd, 0, sizeof cmd); 5902 cmd.code = sc->reset_noise_gain; 5903 cmd.ngroups = 1; 5904 cmd.isvalid = 1; 5905 DPRINTF(sc, IWN_DEBUG_CALIBRATE, 5906 "%s: setting initial differential gains\n", __func__); 5907 return iwn_cmd(sc, IWN_CMD_PHY_CALIB, &cmd, sizeof cmd, 1); 5908 } 5909 5910 static int 5911 iwn4965_set_gains(struct iwn_softc *sc) 5912 { 5913 struct iwn_calib_state *calib = &sc->calib; 5914 struct iwn_phy_calib_gain cmd; 5915 int i, delta, noise; 5916 5917 DPRINTF(sc, IWN_DEBUG_TRACE, "->Doing %s\n", __func__); 5918 5919 /* Get minimal noise among connected antennas. */ 5920 noise = INT_MAX; /* NB: There's at least one antenna. */ 5921 for (i = 0; i < 3; i++) 5922 if (sc->chainmask & (1 << i)) 5923 noise = MIN(calib->noise[i], noise); 5924 5925 memset(&cmd, 0, sizeof cmd); 5926 cmd.code = IWN4965_PHY_CALIB_DIFF_GAIN; 5927 /* Set differential gains for connected antennas. */ 5928 for (i = 0; i < 3; i++) { 5929 if (sc->chainmask & (1 << i)) { 5930 /* Compute attenuation (in unit of 1.5dB). */ 5931 delta = (noise - (int32_t)calib->noise[i]) / 30; 5932 /* NB: delta <= 0 */ 5933 /* Limit to [-4.5dB,0]. */ 5934 cmd.gain[i] = MIN(abs(delta), 3); 5935 if (delta < 0) 5936 cmd.gain[i] |= 1 << 2; /* sign bit */ 5937 } 5938 } 5939 DPRINTF(sc, IWN_DEBUG_CALIBRATE, 5940 "setting differential gains Ant A/B/C: %x/%x/%x (%x)\n", 5941 cmd.gain[0], cmd.gain[1], cmd.gain[2], sc->chainmask); 5942 return iwn_cmd(sc, IWN_CMD_PHY_CALIB, &cmd, sizeof cmd, 1); 5943 } 5944 5945 static int 5946 iwn5000_set_gains(struct iwn_softc *sc) 5947 { 5948 struct iwn_calib_state *calib = &sc->calib; 5949 struct iwn_phy_calib_gain cmd; 5950 int i, ant, div, delta; 5951 5952 DPRINTF(sc, IWN_DEBUG_TRACE, "->Doing %s\n", __func__); 5953 5954 /* We collected 20 beacons and !=6050 need a 1.5 factor. */ 5955 div = (sc->hw_type == IWN_HW_REV_TYPE_6050) ? 20 : 30; 5956 5957 memset(&cmd, 0, sizeof cmd); 5958 cmd.code = sc->noise_gain; 5959 cmd.ngroups = 1; 5960 cmd.isvalid = 1; 5961 /* Get first available RX antenna as referential. */ 5962 ant = IWN_LSB(sc->rxchainmask); 5963 /* Set differential gains for other antennas. */ 5964 for (i = ant + 1; i < 3; i++) { 5965 if (sc->chainmask & (1 << i)) { 5966 /* The delta is relative to antenna "ant". */ 5967 delta = ((int32_t)calib->noise[ant] - 5968 (int32_t)calib->noise[i]) / div; 5969 /* Limit to [-4.5dB,+4.5dB]. */ 5970 cmd.gain[i - 1] = MIN(abs(delta), 3); 5971 if (delta < 0) 5972 cmd.gain[i - 1] |= 1 << 2; /* sign bit */ 5973 } 5974 } 5975 DPRINTF(sc, IWN_DEBUG_CALIBRATE | IWN_DEBUG_XMIT, 5976 "setting differential gains Ant B/C: %x/%x (%x)\n", 5977 cmd.gain[0], cmd.gain[1], sc->chainmask); 5978 return iwn_cmd(sc, IWN_CMD_PHY_CALIB, &cmd, sizeof cmd, 1); 5979 } 5980 5981 /* 5982 * Tune RF RX sensitivity based on the number of false alarms detected 5983 * during the last beacon period. 5984 */ 5985 static void 5986 iwn_tune_sensitivity(struct iwn_softc *sc, const struct iwn_rx_stats *stats) 5987 { 5988 #define inc(val, inc, max) \ 5989 if ((val) < (max)) { \ 5990 if ((val) < (max) - (inc)) \ 5991 (val) += (inc); \ 5992 else \ 5993 (val) = (max); \ 5994 needs_update = 1; \ 5995 } 5996 #define dec(val, dec, min) \ 5997 if ((val) > (min)) { \ 5998 if ((val) > (min) + (dec)) \ 5999 (val) -= (dec); \ 6000 else \ 6001 (val) = (min); \ 6002 needs_update = 1; \ 6003 } 6004 6005 const struct iwn_sensitivity_limits *limits = sc->limits; 6006 struct iwn_calib_state *calib = &sc->calib; 6007 uint32_t val, rxena, fa; 6008 uint32_t energy[3], energy_min; 6009 uint8_t noise[3], noise_ref; 6010 int i, needs_update = 0; 6011 6012 DPRINTF(sc, IWN_DEBUG_TRACE, "->%s begin\n", __func__); 6013 6014 /* Check that we've been enabled long enough. */ 6015 if ((rxena = le32toh(stats->general.load)) == 0){ 6016 DPRINTF(sc, IWN_DEBUG_TRACE, "->%s end not so long\n", __func__); 6017 return; 6018 } 6019 6020 /* Compute number of false alarms since last call for OFDM. */ 6021 fa = le32toh(stats->ofdm.bad_plcp) - calib->bad_plcp_ofdm; 6022 fa += le32toh(stats->ofdm.fa) - calib->fa_ofdm; 6023 fa *= 200 * IEEE80211_DUR_TU; /* 200TU */ 6024 6025 if (fa > 50 * rxena) { 6026 /* High false alarm count, decrease sensitivity. */ 6027 DPRINTF(sc, IWN_DEBUG_CALIBRATE, 6028 "%s: OFDM high false alarm count: %u\n", __func__, fa); 6029 inc(calib->ofdm_x1, 1, limits->max_ofdm_x1); 6030 inc(calib->ofdm_mrc_x1, 1, limits->max_ofdm_mrc_x1); 6031 inc(calib->ofdm_x4, 1, limits->max_ofdm_x4); 6032 inc(calib->ofdm_mrc_x4, 1, limits->max_ofdm_mrc_x4); 6033 6034 } else if (fa < 5 * rxena) { 6035 /* Low false alarm count, increase sensitivity. */ 6036 DPRINTF(sc, IWN_DEBUG_CALIBRATE, 6037 "%s: OFDM low false alarm count: %u\n", __func__, fa); 6038 dec(calib->ofdm_x1, 1, limits->min_ofdm_x1); 6039 dec(calib->ofdm_mrc_x1, 1, limits->min_ofdm_mrc_x1); 6040 dec(calib->ofdm_x4, 1, limits->min_ofdm_x4); 6041 dec(calib->ofdm_mrc_x4, 1, limits->min_ofdm_mrc_x4); 6042 } 6043 6044 /* Compute maximum noise among 3 receivers. */ 6045 for (i = 0; i < 3; i++) 6046 noise[i] = (le32toh(stats->general.noise[i]) >> 8) & 0xff; 6047 val = MAX(noise[0], noise[1]); 6048 val = MAX(noise[2], val); 6049 /* Insert it into our samples table. */ 6050 calib->noise_samples[calib->cur_noise_sample] = val; 6051 calib->cur_noise_sample = (calib->cur_noise_sample + 1) % 20; 6052 6053 /* Compute maximum noise among last 20 samples. */ 6054 noise_ref = calib->noise_samples[0]; 6055 for (i = 1; i < 20; i++) 6056 noise_ref = MAX(noise_ref, calib->noise_samples[i]); 6057 6058 /* Compute maximum energy among 3 receivers. */ 6059 for (i = 0; i < 3; i++) 6060 energy[i] = le32toh(stats->general.energy[i]); 6061 val = MIN(energy[0], energy[1]); 6062 val = MIN(energy[2], val); 6063 /* Insert it into our samples table. */ 6064 calib->energy_samples[calib->cur_energy_sample] = val; 6065 calib->cur_energy_sample = (calib->cur_energy_sample + 1) % 10; 6066 6067 /* Compute minimum energy among last 10 samples. */ 6068 energy_min = calib->energy_samples[0]; 6069 for (i = 1; i < 10; i++) 6070 energy_min = MAX(energy_min, calib->energy_samples[i]); 6071 energy_min += 6; 6072 6073 /* Compute number of false alarms since last call for CCK. */ 6074 fa = le32toh(stats->cck.bad_plcp) - calib->bad_plcp_cck; 6075 fa += le32toh(stats->cck.fa) - calib->fa_cck; 6076 fa *= 200 * IEEE80211_DUR_TU; /* 200TU */ 6077 6078 if (fa > 50 * rxena) { 6079 /* High false alarm count, decrease sensitivity. */ 6080 DPRINTF(sc, IWN_DEBUG_CALIBRATE, 6081 "%s: CCK high false alarm count: %u\n", __func__, fa); 6082 calib->cck_state = IWN_CCK_STATE_HIFA; 6083 calib->low_fa = 0; 6084 6085 if (calib->cck_x4 > 160) { 6086 calib->noise_ref = noise_ref; 6087 if (calib->energy_cck > 2) 6088 dec(calib->energy_cck, 2, energy_min); 6089 } 6090 if (calib->cck_x4 < 160) { 6091 calib->cck_x4 = 161; 6092 needs_update = 1; 6093 } else 6094 inc(calib->cck_x4, 3, limits->max_cck_x4); 6095 6096 inc(calib->cck_mrc_x4, 3, limits->max_cck_mrc_x4); 6097 6098 } else if (fa < 5 * rxena) { 6099 /* Low false alarm count, increase sensitivity. */ 6100 DPRINTF(sc, IWN_DEBUG_CALIBRATE, 6101 "%s: CCK low false alarm count: %u\n", __func__, fa); 6102 calib->cck_state = IWN_CCK_STATE_LOFA; 6103 calib->low_fa++; 6104 6105 if (calib->cck_state != IWN_CCK_STATE_INIT && 6106 (((int32_t)calib->noise_ref - (int32_t)noise_ref) > 2 || 6107 calib->low_fa > 100)) { 6108 inc(calib->energy_cck, 2, limits->min_energy_cck); 6109 dec(calib->cck_x4, 3, limits->min_cck_x4); 6110 dec(calib->cck_mrc_x4, 3, limits->min_cck_mrc_x4); 6111 } 6112 } else { 6113 /* Not worth to increase or decrease sensitivity. */ 6114 DPRINTF(sc, IWN_DEBUG_CALIBRATE, 6115 "%s: CCK normal false alarm count: %u\n", __func__, fa); 6116 calib->low_fa = 0; 6117 calib->noise_ref = noise_ref; 6118 6119 if (calib->cck_state == IWN_CCK_STATE_HIFA) { 6120 /* Previous interval had many false alarms. */ 6121 dec(calib->energy_cck, 8, energy_min); 6122 } 6123 calib->cck_state = IWN_CCK_STATE_INIT; 6124 } 6125 6126 if (needs_update) 6127 (void)iwn_send_sensitivity(sc); 6128 6129 DPRINTF(sc, IWN_DEBUG_TRACE, "->%s: end\n",__func__); 6130 6131 #undef dec 6132 #undef inc 6133 } 6134 6135 static int 6136 iwn_send_sensitivity(struct iwn_softc *sc) 6137 { 6138 struct iwn_calib_state *calib = &sc->calib; 6139 struct iwn_enhanced_sensitivity_cmd cmd; 6140 int len; 6141 6142 memset(&cmd, 0, sizeof cmd); 6143 len = sizeof (struct iwn_sensitivity_cmd); 6144 cmd.which = IWN_SENSITIVITY_WORKTBL; 6145 /* OFDM modulation. */ 6146 cmd.corr_ofdm_x1 = htole16(calib->ofdm_x1); 6147 cmd.corr_ofdm_mrc_x1 = htole16(calib->ofdm_mrc_x1); 6148 cmd.corr_ofdm_x4 = htole16(calib->ofdm_x4); 6149 cmd.corr_ofdm_mrc_x4 = htole16(calib->ofdm_mrc_x4); 6150 cmd.energy_ofdm = htole16(sc->limits->energy_ofdm); 6151 cmd.energy_ofdm_th = htole16(62); 6152 /* CCK modulation. */ 6153 cmd.corr_cck_x4 = htole16(calib->cck_x4); 6154 cmd.corr_cck_mrc_x4 = htole16(calib->cck_mrc_x4); 6155 cmd.energy_cck = htole16(calib->energy_cck); 6156 /* Barker modulation: use default values. */ 6157 cmd.corr_barker = htole16(190); 6158 cmd.corr_barker_mrc = htole16(sc->limits->barker_mrc); 6159 6160 DPRINTF(sc, IWN_DEBUG_CALIBRATE, 6161 "%s: set sensitivity %d/%d/%d/%d/%d/%d/%d\n", __func__, 6162 calib->ofdm_x1, calib->ofdm_mrc_x1, calib->ofdm_x4, 6163 calib->ofdm_mrc_x4, calib->cck_x4, 6164 calib->cck_mrc_x4, calib->energy_cck); 6165 6166 if (!(sc->sc_flags & IWN_FLAG_ENH_SENS)) 6167 goto send; 6168 /* Enhanced sensitivity settings. */ 6169 len = sizeof (struct iwn_enhanced_sensitivity_cmd); 6170 cmd.ofdm_det_slope_mrc = htole16(668); 6171 cmd.ofdm_det_icept_mrc = htole16(4); 6172 cmd.ofdm_det_slope = htole16(486); 6173 cmd.ofdm_det_icept = htole16(37); 6174 cmd.cck_det_slope_mrc = htole16(853); 6175 cmd.cck_det_icept_mrc = htole16(4); 6176 cmd.cck_det_slope = htole16(476); 6177 cmd.cck_det_icept = htole16(99); 6178 send: 6179 return iwn_cmd(sc, IWN_CMD_SET_SENSITIVITY, &cmd, len, 1); 6180 } 6181 6182 /* 6183 * Look at the increase of PLCP errors over time; if it exceeds 6184 * a programmed threshold then trigger an RF retune. 6185 */ 6186 static void 6187 iwn_check_rx_recovery(struct iwn_softc *sc, struct iwn_stats *rs) 6188 { 6189 int32_t delta_ofdm, delta_ht, delta_cck; 6190 struct iwn_calib_state *calib = &sc->calib; 6191 int delta_ticks, cur_ticks; 6192 int delta_msec; 6193 int thresh; 6194 6195 /* 6196 * Calculate the difference between the current and 6197 * previous statistics. 6198 */ 6199 delta_cck = le32toh(rs->rx.cck.bad_plcp) - calib->bad_plcp_cck; 6200 delta_ofdm = le32toh(rs->rx.ofdm.bad_plcp) - calib->bad_plcp_ofdm; 6201 delta_ht = le32toh(rs->rx.ht.bad_plcp) - calib->bad_plcp_ht; 6202 6203 /* 6204 * Calculate the delta in time between successive statistics 6205 * messages. Yes, it can roll over; so we make sure that 6206 * this doesn't happen. 6207 * 6208 * XXX go figure out what to do about rollover 6209 * XXX go figure out what to do if ticks rolls over to -ve instead! 6210 * XXX go stab signed integer overflow undefined-ness in the face. 6211 */ 6212 cur_ticks = ticks; 6213 delta_ticks = cur_ticks - sc->last_calib_ticks; 6214 6215 /* 6216 * If any are negative, then the firmware likely reset; so just 6217 * bail. We'll pick this up next time. 6218 */ 6219 if (delta_cck < 0 || delta_ofdm < 0 || delta_ht < 0 || delta_ticks < 0) 6220 return; 6221 6222 /* 6223 * delta_ticks is in ticks; we need to convert it up to milliseconds 6224 * so we can do some useful math with it. 6225 */ 6226 delta_msec = ticks_to_msecs(delta_ticks); 6227 6228 /* 6229 * Calculate what our threshold is given the current delta_msec. 6230 */ 6231 thresh = sc->base_params->plcp_err_threshold * delta_msec; 6232 6233 DPRINTF(sc, IWN_DEBUG_STATE, 6234 "%s: time delta: %d; cck=%d, ofdm=%d, ht=%d, total=%d, thresh=%d\n", 6235 __func__, 6236 delta_msec, 6237 delta_cck, 6238 delta_ofdm, 6239 delta_ht, 6240 (delta_msec + delta_cck + delta_ofdm + delta_ht), 6241 thresh); 6242 6243 /* 6244 * If we need a retune, then schedule a single channel scan 6245 * to a channel that isn't the currently active one! 6246 * 6247 * The math from linux iwlwifi: 6248 * 6249 * if ((delta * 100 / msecs) > threshold) 6250 */ 6251 if (thresh > 0 && (delta_cck + delta_ofdm + delta_ht) * 100 > thresh) { 6252 DPRINTF(sc, IWN_DEBUG_ANY, 6253 "%s: PLCP error threshold raw (%d) comparison (%d) " 6254 "over limit (%d); retune!\n", 6255 __func__, 6256 (delta_cck + delta_ofdm + delta_ht), 6257 (delta_cck + delta_ofdm + delta_ht) * 100, 6258 thresh); 6259 } 6260 } 6261 6262 /* 6263 * Set STA mode power saving level (between 0 and 5). 6264 * Level 0 is CAM (Continuously Aware Mode), 5 is for maximum power saving. 6265 */ 6266 static int 6267 iwn_set_pslevel(struct iwn_softc *sc, int dtim, int level, int async) 6268 { 6269 struct iwn_pmgt_cmd cmd; 6270 const struct iwn_pmgt *pmgt; 6271 uint32_t max, skip_dtim; 6272 uint32_t reg; 6273 int i; 6274 6275 DPRINTF(sc, IWN_DEBUG_PWRSAVE, 6276 "%s: dtim=%d, level=%d, async=%d\n", 6277 __func__, 6278 dtim, 6279 level, 6280 async); 6281 6282 /* Select which PS parameters to use. */ 6283 if (dtim <= 2) 6284 pmgt = &iwn_pmgt[0][level]; 6285 else if (dtim <= 10) 6286 pmgt = &iwn_pmgt[1][level]; 6287 else 6288 pmgt = &iwn_pmgt[2][level]; 6289 6290 memset(&cmd, 0, sizeof cmd); 6291 if (level != 0) /* not CAM */ 6292 cmd.flags |= htole16(IWN_PS_ALLOW_SLEEP); 6293 if (level == 5) 6294 cmd.flags |= htole16(IWN_PS_FAST_PD); 6295 /* Retrieve PCIe Active State Power Management (ASPM). */ 6296 reg = pci_read_config(sc->sc_dev, sc->sc_cap_off + 0x10, 1); 6297 if (!(reg & 0x1)) /* L0s Entry disabled. */ 6298 cmd.flags |= htole16(IWN_PS_PCI_PMGT); 6299 cmd.rxtimeout = htole32(pmgt->rxtimeout * 1024); 6300 cmd.txtimeout = htole32(pmgt->txtimeout * 1024); 6301 6302 if (dtim == 0) { 6303 dtim = 1; 6304 skip_dtim = 0; 6305 } else 6306 skip_dtim = pmgt->skip_dtim; 6307 if (skip_dtim != 0) { 6308 cmd.flags |= htole16(IWN_PS_SLEEP_OVER_DTIM); 6309 max = pmgt->intval[4]; 6310 if (max == (uint32_t)-1) 6311 max = dtim * (skip_dtim + 1); 6312 else if (max > dtim) 6313 max = (max / dtim) * dtim; 6314 } else 6315 max = dtim; 6316 for (i = 0; i < 5; i++) 6317 cmd.intval[i] = htole32(MIN(max, pmgt->intval[i])); 6318 6319 DPRINTF(sc, IWN_DEBUG_RESET, "setting power saving level to %d\n", 6320 level); 6321 return iwn_cmd(sc, IWN_CMD_SET_POWER_MODE, &cmd, sizeof cmd, async); 6322 } 6323 6324 static int 6325 iwn_send_btcoex(struct iwn_softc *sc) 6326 { 6327 struct iwn_bluetooth cmd; 6328 6329 memset(&cmd, 0, sizeof cmd); 6330 cmd.flags = IWN_BT_COEX_CHAN_ANN | IWN_BT_COEX_BT_PRIO; 6331 cmd.lead_time = IWN_BT_LEAD_TIME_DEF; 6332 cmd.max_kill = IWN_BT_MAX_KILL_DEF; 6333 DPRINTF(sc, IWN_DEBUG_RESET, "%s: configuring bluetooth coexistence\n", 6334 __func__); 6335 return iwn_cmd(sc, IWN_CMD_BT_COEX, &cmd, sizeof(cmd), 0); 6336 } 6337 6338 static int 6339 iwn_send_advanced_btcoex(struct iwn_softc *sc) 6340 { 6341 static const uint32_t btcoex_3wire[12] = { 6342 0xaaaaaaaa, 0xaaaaaaaa, 0xaeaaaaaa, 0xaaaaaaaa, 6343 0xcc00ff28, 0x0000aaaa, 0xcc00aaaa, 0x0000aaaa, 6344 0xc0004000, 0x00004000, 0xf0005000, 0xf0005000, 6345 }; 6346 struct iwn6000_btcoex_config btconfig; 6347 struct iwn2000_btcoex_config btconfig2k; 6348 struct iwn_btcoex_priotable btprio; 6349 struct iwn_btcoex_prot btprot; 6350 int error, i; 6351 uint8_t flags; 6352 6353 memset(&btconfig, 0, sizeof btconfig); 6354 memset(&btconfig2k, 0, sizeof btconfig2k); 6355 6356 flags = IWN_BT_FLAG_COEX6000_MODE_3W << 6357 IWN_BT_FLAG_COEX6000_MODE_SHIFT; // Done as is in linux kernel 3.2 6358 6359 if (sc->base_params->bt_sco_disable) 6360 flags &= ~IWN_BT_FLAG_SYNC_2_BT_DISABLE; 6361 else 6362 flags |= IWN_BT_FLAG_SYNC_2_BT_DISABLE; 6363 6364 flags |= IWN_BT_FLAG_COEX6000_CHAN_INHIBITION; 6365 6366 /* Default flags result is 145 as old value */ 6367 6368 /* 6369 * Flags value has to be review. Values must change if we 6370 * which to disable it 6371 */ 6372 if (sc->base_params->bt_session_2) { 6373 btconfig2k.flags = flags; 6374 btconfig2k.max_kill = 5; 6375 btconfig2k.bt3_t7_timer = 1; 6376 btconfig2k.kill_ack = htole32(0xffff0000); 6377 btconfig2k.kill_cts = htole32(0xffff0000); 6378 btconfig2k.sample_time = 2; 6379 btconfig2k.bt3_t2_timer = 0xc; 6380 6381 for (i = 0; i < 12; i++) 6382 btconfig2k.lookup_table[i] = htole32(btcoex_3wire[i]); 6383 btconfig2k.valid = htole16(0xff); 6384 btconfig2k.prio_boost = htole32(0xf0); 6385 DPRINTF(sc, IWN_DEBUG_RESET, 6386 "%s: configuring advanced bluetooth coexistence" 6387 " session 2, flags : 0x%x\n", 6388 __func__, 6389 flags); 6390 error = iwn_cmd(sc, IWN_CMD_BT_COEX, &btconfig2k, 6391 sizeof(btconfig2k), 1); 6392 } else { 6393 btconfig.flags = flags; 6394 btconfig.max_kill = 5; 6395 btconfig.bt3_t7_timer = 1; 6396 btconfig.kill_ack = htole32(0xffff0000); 6397 btconfig.kill_cts = htole32(0xffff0000); 6398 btconfig.sample_time = 2; 6399 btconfig.bt3_t2_timer = 0xc; 6400 6401 for (i = 0; i < 12; i++) 6402 btconfig.lookup_table[i] = htole32(btcoex_3wire[i]); 6403 btconfig.valid = htole16(0xff); 6404 btconfig.prio_boost = 0xf0; 6405 DPRINTF(sc, IWN_DEBUG_RESET, 6406 "%s: configuring advanced bluetooth coexistence," 6407 " flags : 0x%x\n", 6408 __func__, 6409 flags); 6410 error = iwn_cmd(sc, IWN_CMD_BT_COEX, &btconfig, 6411 sizeof(btconfig), 1); 6412 } 6413 6414 if (error != 0) 6415 return error; 6416 6417 memset(&btprio, 0, sizeof btprio); 6418 btprio.calib_init1 = 0x6; 6419 btprio.calib_init2 = 0x7; 6420 btprio.calib_periodic_low1 = 0x2; 6421 btprio.calib_periodic_low2 = 0x3; 6422 btprio.calib_periodic_high1 = 0x4; 6423 btprio.calib_periodic_high2 = 0x5; 6424 btprio.dtim = 0x6; 6425 btprio.scan52 = 0x8; 6426 btprio.scan24 = 0xa; 6427 error = iwn_cmd(sc, IWN_CMD_BT_COEX_PRIOTABLE, &btprio, sizeof(btprio), 6428 1); 6429 if (error != 0) 6430 return error; 6431 6432 /* Force BT state machine change. */ 6433 memset(&btprot, 0, sizeof btprot); 6434 btprot.open = 1; 6435 btprot.type = 1; 6436 error = iwn_cmd(sc, IWN_CMD_BT_COEX_PROT, &btprot, sizeof(btprot), 1); 6437 if (error != 0) 6438 return error; 6439 btprot.open = 0; 6440 return iwn_cmd(sc, IWN_CMD_BT_COEX_PROT, &btprot, sizeof(btprot), 1); 6441 } 6442 6443 static int 6444 iwn5000_runtime_calib(struct iwn_softc *sc) 6445 { 6446 struct iwn5000_calib_config cmd; 6447 6448 memset(&cmd, 0, sizeof cmd); 6449 cmd.ucode.once.enable = 0xffffffff; 6450 cmd.ucode.once.start = IWN5000_CALIB_DC; 6451 DPRINTF(sc, IWN_DEBUG_CALIBRATE, 6452 "%s: configuring runtime calibration\n", __func__); 6453 return iwn_cmd(sc, IWN5000_CMD_CALIB_CONFIG, &cmd, sizeof(cmd), 0); 6454 } 6455 6456 static uint32_t 6457 iwn_get_rxon_ht_flags(struct iwn_softc *sc, struct ieee80211_channel *c) 6458 { 6459 struct ieee80211com *ic = &sc->sc_ic; 6460 uint32_t htflags = 0; 6461 6462 if (! IEEE80211_IS_CHAN_HT(c)) 6463 return (0); 6464 6465 htflags |= IWN_RXON_HT_PROTMODE(ic->ic_curhtprotmode); 6466 6467 if (IEEE80211_IS_CHAN_HT40(c)) { 6468 switch (ic->ic_curhtprotmode) { 6469 case IEEE80211_HTINFO_OPMODE_HT20PR: 6470 htflags |= IWN_RXON_HT_MODEPURE40; 6471 break; 6472 default: 6473 htflags |= IWN_RXON_HT_MODEMIXED; 6474 break; 6475 } 6476 } 6477 if (IEEE80211_IS_CHAN_HT40D(c)) 6478 htflags |= IWN_RXON_HT_HT40MINUS; 6479 6480 return (htflags); 6481 } 6482 6483 static int 6484 iwn_config(struct iwn_softc *sc) 6485 { 6486 struct iwn_ops *ops = &sc->ops; 6487 struct ieee80211com *ic = &sc->sc_ic; 6488 struct ieee80211vap *vap = TAILQ_FIRST(&ic->ic_vaps); 6489 const uint8_t *macaddr; 6490 uint32_t txmask; 6491 uint16_t rxchain; 6492 int error; 6493 6494 DPRINTF(sc, IWN_DEBUG_TRACE, "->%s begin\n", __func__); 6495 6496 if ((sc->base_params->calib_need & IWN_FLG_NEED_PHY_CALIB_TEMP_OFFSET) 6497 && (sc->base_params->calib_need & IWN_FLG_NEED_PHY_CALIB_TEMP_OFFSETv2)) { 6498 device_printf(sc->sc_dev,"%s: temp_offset and temp_offsetv2 are" 6499 " exclusive each together. Review NIC config file. Conf" 6500 " : 0x%08x Flags : 0x%08x \n", __func__, 6501 sc->base_params->calib_need, 6502 (IWN_FLG_NEED_PHY_CALIB_TEMP_OFFSET | 6503 IWN_FLG_NEED_PHY_CALIB_TEMP_OFFSETv2)); 6504 return (EINVAL); 6505 } 6506 6507 /* Compute temperature calib if needed. Will be send by send calib */ 6508 if (sc->base_params->calib_need & IWN_FLG_NEED_PHY_CALIB_TEMP_OFFSET) { 6509 error = iwn5000_temp_offset_calib(sc); 6510 if (error != 0) { 6511 device_printf(sc->sc_dev, 6512 "%s: could not set temperature offset\n", __func__); 6513 return (error); 6514 } 6515 } else if (sc->base_params->calib_need & IWN_FLG_NEED_PHY_CALIB_TEMP_OFFSETv2) { 6516 error = iwn5000_temp_offset_calibv2(sc); 6517 if (error != 0) { 6518 device_printf(sc->sc_dev, 6519 "%s: could not compute temperature offset v2\n", 6520 __func__); 6521 return (error); 6522 } 6523 } 6524 6525 if (sc->hw_type == IWN_HW_REV_TYPE_6050) { 6526 /* Configure runtime DC calibration. */ 6527 error = iwn5000_runtime_calib(sc); 6528 if (error != 0) { 6529 device_printf(sc->sc_dev, 6530 "%s: could not configure runtime calibration\n", 6531 __func__); 6532 return error; 6533 } 6534 } 6535 6536 /* Configure valid TX chains for >=5000 Series. */ 6537 if (sc->hw_type != IWN_HW_REV_TYPE_4965 && 6538 IWN_UCODE_API(sc->ucode_rev) > 1) { 6539 txmask = htole32(sc->txchainmask); 6540 DPRINTF(sc, IWN_DEBUG_RESET | IWN_DEBUG_XMIT, 6541 "%s: configuring valid TX chains 0x%x\n", __func__, txmask); 6542 error = iwn_cmd(sc, IWN5000_CMD_TX_ANT_CONFIG, &txmask, 6543 sizeof txmask, 0); 6544 if (error != 0) { 6545 device_printf(sc->sc_dev, 6546 "%s: could not configure valid TX chains, " 6547 "error %d\n", __func__, error); 6548 return error; 6549 } 6550 } 6551 6552 /* Configure bluetooth coexistence. */ 6553 error = 0; 6554 6555 /* Configure bluetooth coexistence if needed. */ 6556 if (sc->base_params->bt_mode == IWN_BT_ADVANCED) 6557 error = iwn_send_advanced_btcoex(sc); 6558 if (sc->base_params->bt_mode == IWN_BT_SIMPLE) 6559 error = iwn_send_btcoex(sc); 6560 6561 if (error != 0) { 6562 device_printf(sc->sc_dev, 6563 "%s: could not configure bluetooth coexistence, error %d\n", 6564 __func__, error); 6565 return error; 6566 } 6567 6568 /* Set mode, channel, RX filter and enable RX. */ 6569 sc->rxon = &sc->rx_on[IWN_RXON_BSS_CTX]; 6570 memset(sc->rxon, 0, sizeof (struct iwn_rxon)); 6571 macaddr = vap ? vap->iv_myaddr : ic->ic_macaddr; 6572 IEEE80211_ADDR_COPY(sc->rxon->myaddr, macaddr); 6573 IEEE80211_ADDR_COPY(sc->rxon->wlap, macaddr); 6574 sc->rxon->chan = ieee80211_chan2ieee(ic, ic->ic_curchan); 6575 sc->rxon->flags = htole32(IWN_RXON_TSF | IWN_RXON_CTS_TO_SELF); 6576 if (IEEE80211_IS_CHAN_2GHZ(ic->ic_curchan)) 6577 sc->rxon->flags |= htole32(IWN_RXON_AUTO | IWN_RXON_24GHZ); 6578 switch (ic->ic_opmode) { 6579 case IEEE80211_M_STA: 6580 sc->rxon->mode = IWN_MODE_STA; 6581 sc->rxon->filter = htole32(IWN_FILTER_MULTICAST); 6582 break; 6583 case IEEE80211_M_MONITOR: 6584 sc->rxon->mode = IWN_MODE_MONITOR; 6585 sc->rxon->filter = htole32(IWN_FILTER_MULTICAST | 6586 IWN_FILTER_CTL | IWN_FILTER_PROMISC); 6587 break; 6588 default: 6589 /* Should not get there. */ 6590 break; 6591 } 6592 sc->rxon->cck_mask = 0x0f; /* not yet negotiated */ 6593 sc->rxon->ofdm_mask = 0xff; /* not yet negotiated */ 6594 sc->rxon->ht_single_mask = 0xff; 6595 sc->rxon->ht_dual_mask = 0xff; 6596 sc->rxon->ht_triple_mask = 0xff; 6597 /* 6598 * In active association mode, ensure that 6599 * all the receive chains are enabled. 6600 * 6601 * Since we're not yet doing SMPS, don't allow the 6602 * number of idle RX chains to be less than the active 6603 * number. 6604 */ 6605 rxchain = 6606 IWN_RXCHAIN_VALID(sc->rxchainmask) | 6607 IWN_RXCHAIN_MIMO_COUNT(sc->nrxchains) | 6608 IWN_RXCHAIN_IDLE_COUNT(sc->nrxchains); 6609 sc->rxon->rxchain = htole16(rxchain); 6610 DPRINTF(sc, IWN_DEBUG_RESET | IWN_DEBUG_XMIT, 6611 "%s: rxchainmask=0x%x, nrxchains=%d\n", 6612 __func__, 6613 sc->rxchainmask, 6614 sc->nrxchains); 6615 6616 sc->rxon->flags |= htole32(iwn_get_rxon_ht_flags(sc, ic->ic_curchan)); 6617 6618 DPRINTF(sc, IWN_DEBUG_RESET, 6619 "%s: setting configuration; flags=0x%08x\n", 6620 __func__, le32toh(sc->rxon->flags)); 6621 if (sc->sc_is_scanning) 6622 device_printf(sc->sc_dev, 6623 "%s: is_scanning set, before RXON\n", 6624 __func__); 6625 error = iwn_cmd(sc, IWN_CMD_RXON, sc->rxon, sc->rxonsz, 0); 6626 if (error != 0) { 6627 device_printf(sc->sc_dev, "%s: RXON command failed\n", 6628 __func__); 6629 return error; 6630 } 6631 6632 if ((error = iwn_add_broadcast_node(sc, 0)) != 0) { 6633 device_printf(sc->sc_dev, "%s: could not add broadcast node\n", 6634 __func__); 6635 return error; 6636 } 6637 6638 /* Configuration has changed, set TX power accordingly. */ 6639 if ((error = ops->set_txpower(sc, ic->ic_curchan, 0)) != 0) { 6640 device_printf(sc->sc_dev, "%s: could not set TX power\n", 6641 __func__); 6642 return error; 6643 } 6644 6645 if ((error = iwn_set_critical_temp(sc)) != 0) { 6646 device_printf(sc->sc_dev, 6647 "%s: could not set critical temperature\n", __func__); 6648 return error; 6649 } 6650 6651 /* Set power saving level to CAM during initialization. */ 6652 if ((error = iwn_set_pslevel(sc, 0, 0, 0)) != 0) { 6653 device_printf(sc->sc_dev, 6654 "%s: could not set power saving level\n", __func__); 6655 return error; 6656 } 6657 6658 DPRINTF(sc, IWN_DEBUG_TRACE, "->%s: end\n",__func__); 6659 6660 return 0; 6661 } 6662 6663 static uint16_t 6664 iwn_get_active_dwell_time(struct iwn_softc *sc, 6665 struct ieee80211_channel *c, uint8_t n_probes) 6666 { 6667 /* No channel? Default to 2GHz settings */ 6668 if (c == NULL || IEEE80211_IS_CHAN_2GHZ(c)) { 6669 return (IWN_ACTIVE_DWELL_TIME_2GHZ + 6670 IWN_ACTIVE_DWELL_FACTOR_2GHZ * (n_probes + 1)); 6671 } 6672 6673 /* 5GHz dwell time */ 6674 return (IWN_ACTIVE_DWELL_TIME_5GHZ + 6675 IWN_ACTIVE_DWELL_FACTOR_5GHZ * (n_probes + 1)); 6676 } 6677 6678 /* 6679 * Limit the total dwell time to 85% of the beacon interval. 6680 * 6681 * Returns the dwell time in milliseconds. 6682 */ 6683 static uint16_t 6684 iwn_limit_dwell(struct iwn_softc *sc, uint16_t dwell_time) 6685 { 6686 struct ieee80211com *ic = &sc->sc_ic; 6687 struct ieee80211vap *vap = NULL; 6688 int bintval = 0; 6689 6690 /* bintval is in TU (1.024mS) */ 6691 if (! TAILQ_EMPTY(&ic->ic_vaps)) { 6692 vap = TAILQ_FIRST(&ic->ic_vaps); 6693 bintval = vap->iv_bss->ni_intval; 6694 } 6695 6696 /* 6697 * If it's non-zero, we should calculate the minimum of 6698 * it and the DWELL_BASE. 6699 * 6700 * XXX Yes, the math should take into account that bintval 6701 * is 1.024mS, not 1mS.. 6702 */ 6703 if (bintval > 0) { 6704 DPRINTF(sc, IWN_DEBUG_SCAN, 6705 "%s: bintval=%d\n", 6706 __func__, 6707 bintval); 6708 return (MIN(IWN_PASSIVE_DWELL_BASE, ((bintval * 85) / 100))); 6709 } 6710 6711 /* No association context? Default */ 6712 return (IWN_PASSIVE_DWELL_BASE); 6713 } 6714 6715 static uint16_t 6716 iwn_get_passive_dwell_time(struct iwn_softc *sc, struct ieee80211_channel *c) 6717 { 6718 uint16_t passive; 6719 6720 if (c == NULL || IEEE80211_IS_CHAN_2GHZ(c)) { 6721 passive = IWN_PASSIVE_DWELL_BASE + IWN_PASSIVE_DWELL_TIME_2GHZ; 6722 } else { 6723 passive = IWN_PASSIVE_DWELL_BASE + IWN_PASSIVE_DWELL_TIME_5GHZ; 6724 } 6725 6726 /* Clamp to the beacon interval if we're associated */ 6727 return (iwn_limit_dwell(sc, passive)); 6728 } 6729 6730 static int 6731 iwn_scan(struct iwn_softc *sc, struct ieee80211vap *vap, 6732 struct ieee80211_scan_state *ss, struct ieee80211_channel *c) 6733 { 6734 struct ieee80211com *ic = &sc->sc_ic; 6735 struct ieee80211_node *ni = vap->iv_bss; 6736 struct iwn_scan_hdr *hdr; 6737 struct iwn_cmd_data *tx; 6738 struct iwn_scan_essid *essid; 6739 struct iwn_scan_chan *chan; 6740 struct ieee80211_frame *wh; 6741 struct ieee80211_rateset *rs; 6742 uint8_t *buf, *frm; 6743 uint16_t rxchain; 6744 uint8_t txant; 6745 int buflen, error; 6746 int is_active; 6747 uint16_t dwell_active, dwell_passive; 6748 uint32_t extra, scan_service_time; 6749 6750 DPRINTF(sc, IWN_DEBUG_TRACE, "->%s begin\n", __func__); 6751 6752 /* 6753 * We are absolutely not allowed to send a scan command when another 6754 * scan command is pending. 6755 */ 6756 if (sc->sc_is_scanning) { 6757 device_printf(sc->sc_dev, "%s: called whilst scanning!\n", 6758 __func__); 6759 return (EAGAIN); 6760 } 6761 6762 /* Assign the scan channel */ 6763 c = ic->ic_curchan; 6764 6765 sc->rxon = &sc->rx_on[IWN_RXON_BSS_CTX]; 6766 buf = malloc(IWN_SCAN_MAXSZ, M_DEVBUF, M_NOWAIT | M_ZERO); 6767 if (buf == NULL) { 6768 device_printf(sc->sc_dev, 6769 "%s: could not allocate buffer for scan command\n", 6770 __func__); 6771 return ENOMEM; 6772 } 6773 hdr = (struct iwn_scan_hdr *)buf; 6774 /* 6775 * Move to the next channel if no frames are received within 10ms 6776 * after sending the probe request. 6777 */ 6778 hdr->quiet_time = htole16(10); /* timeout in milliseconds */ 6779 hdr->quiet_threshold = htole16(1); /* min # of packets */ 6780 /* 6781 * Max needs to be greater than active and passive and quiet! 6782 * It's also in microseconds! 6783 */ 6784 hdr->max_svc = htole32(250 * 1024); 6785 6786 /* 6787 * Reset scan: interval=100 6788 * Normal scan: interval=becaon interval 6789 * suspend_time: 100 (TU) 6790 * 6791 */ 6792 extra = (100 /* suspend_time */ / 100 /* beacon interval */) << 22; 6793 //scan_service_time = extra | ((100 /* susp */ % 100 /* int */) * 1024); 6794 scan_service_time = (4 << 22) | (100 * 1024); /* Hardcode for now! */ 6795 hdr->pause_svc = htole32(scan_service_time); 6796 6797 /* Select antennas for scanning. */ 6798 rxchain = 6799 IWN_RXCHAIN_VALID(sc->rxchainmask) | 6800 IWN_RXCHAIN_FORCE_MIMO_SEL(sc->rxchainmask) | 6801 IWN_RXCHAIN_DRIVER_FORCE; 6802 if (IEEE80211_IS_CHAN_A(c) && 6803 sc->hw_type == IWN_HW_REV_TYPE_4965) { 6804 /* Ant A must be avoided in 5GHz because of an HW bug. */ 6805 rxchain |= IWN_RXCHAIN_FORCE_SEL(IWN_ANT_B); 6806 } else /* Use all available RX antennas. */ 6807 rxchain |= IWN_RXCHAIN_FORCE_SEL(sc->rxchainmask); 6808 hdr->rxchain = htole16(rxchain); 6809 hdr->filter = htole32(IWN_FILTER_MULTICAST | IWN_FILTER_BEACON); 6810 6811 tx = (struct iwn_cmd_data *)(hdr + 1); 6812 tx->flags = htole32(IWN_TX_AUTO_SEQ); 6813 tx->id = sc->broadcast_id; 6814 tx->lifetime = htole32(IWN_LIFETIME_INFINITE); 6815 6816 if (IEEE80211_IS_CHAN_5GHZ(c)) { 6817 /* Send probe requests at 6Mbps. */ 6818 tx->rate = htole32(0xd); 6819 rs = &ic->ic_sup_rates[IEEE80211_MODE_11A]; 6820 } else { 6821 hdr->flags = htole32(IWN_RXON_24GHZ | IWN_RXON_AUTO); 6822 if (sc->hw_type == IWN_HW_REV_TYPE_4965 && 6823 sc->rxon->associd && sc->rxon->chan > 14) 6824 tx->rate = htole32(0xd); 6825 else { 6826 /* Send probe requests at 1Mbps. */ 6827 tx->rate = htole32(10 | IWN_RFLAG_CCK); 6828 } 6829 rs = &ic->ic_sup_rates[IEEE80211_MODE_11G]; 6830 } 6831 /* Use the first valid TX antenna. */ 6832 txant = IWN_LSB(sc->txchainmask); 6833 tx->rate |= htole32(IWN_RFLAG_ANT(txant)); 6834 6835 /* 6836 * Only do active scanning if we're announcing a probe request 6837 * for a given SSID (or more, if we ever add it to the driver.) 6838 */ 6839 is_active = 0; 6840 6841 /* 6842 * If we're scanning for a specific SSID, add it to the command. 6843 * 6844 * XXX maybe look at adding support for scanning multiple SSIDs? 6845 */ 6846 essid = (struct iwn_scan_essid *)(tx + 1); 6847 if (ss != NULL) { 6848 if (ss->ss_ssid[0].len != 0) { 6849 essid[0].id = IEEE80211_ELEMID_SSID; 6850 essid[0].len = ss->ss_ssid[0].len; 6851 memcpy(essid[0].data, ss->ss_ssid[0].ssid, ss->ss_ssid[0].len); 6852 } 6853 6854 DPRINTF(sc, IWN_DEBUG_SCAN, "%s: ssid_len=%d, ssid=%*s\n", 6855 __func__, 6856 ss->ss_ssid[0].len, 6857 ss->ss_ssid[0].len, 6858 ss->ss_ssid[0].ssid); 6859 6860 if (ss->ss_nssid > 0) 6861 is_active = 1; 6862 } 6863 6864 /* 6865 * Build a probe request frame. Most of the following code is a 6866 * copy & paste of what is done in net80211. 6867 */ 6868 wh = (struct ieee80211_frame *)(essid + 20); 6869 wh->i_fc[0] = IEEE80211_FC0_VERSION_0 | IEEE80211_FC0_TYPE_MGT | 6870 IEEE80211_FC0_SUBTYPE_PROBE_REQ; 6871 wh->i_fc[1] = IEEE80211_FC1_DIR_NODS; 6872 IEEE80211_ADDR_COPY(wh->i_addr1, vap->iv_ifp->if_broadcastaddr); 6873 IEEE80211_ADDR_COPY(wh->i_addr2, IF_LLADDR(vap->iv_ifp)); 6874 IEEE80211_ADDR_COPY(wh->i_addr3, vap->iv_ifp->if_broadcastaddr); 6875 *(uint16_t *)&wh->i_dur[0] = 0; /* filled by HW */ 6876 *(uint16_t *)&wh->i_seq[0] = 0; /* filled by HW */ 6877 6878 frm = (uint8_t *)(wh + 1); 6879 frm = ieee80211_add_ssid(frm, NULL, 0); 6880 frm = ieee80211_add_rates(frm, rs); 6881 if (rs->rs_nrates > IEEE80211_RATE_SIZE) 6882 frm = ieee80211_add_xrates(frm, rs); 6883 if (ic->ic_htcaps & IEEE80211_HTC_HT) 6884 frm = ieee80211_add_htcap(frm, ni); 6885 6886 /* Set length of probe request. */ 6887 tx->len = htole16(frm - (uint8_t *)wh); 6888 6889 /* 6890 * If active scanning is requested but a certain channel is 6891 * marked passive, we can do active scanning if we detect 6892 * transmissions. 6893 * 6894 * There is an issue with some firmware versions that triggers 6895 * a sysassert on a "good CRC threshold" of zero (== disabled), 6896 * on a radar channel even though this means that we should NOT 6897 * send probes. 6898 * 6899 * The "good CRC threshold" is the number of frames that we 6900 * need to receive during our dwell time on a channel before 6901 * sending out probes -- setting this to a huge value will 6902 * mean we never reach it, but at the same time work around 6903 * the aforementioned issue. Thus use IWL_GOOD_CRC_TH_NEVER 6904 * here instead of IWL_GOOD_CRC_TH_DISABLED. 6905 * 6906 * This was fixed in later versions along with some other 6907 * scan changes, and the threshold behaves as a flag in those 6908 * versions. 6909 */ 6910 6911 /* 6912 * If we're doing active scanning, set the crc_threshold 6913 * to a suitable value. This is different to active veruss 6914 * passive scanning depending upon the channel flags; the 6915 * firmware will obey that particular check for us. 6916 */ 6917 if (sc->tlv_feature_flags & IWN_UCODE_TLV_FLAGS_NEWSCAN) 6918 hdr->crc_threshold = is_active ? 6919 IWN_GOOD_CRC_TH_DEFAULT : IWN_GOOD_CRC_TH_DISABLED; 6920 else 6921 hdr->crc_threshold = is_active ? 6922 IWN_GOOD_CRC_TH_DEFAULT : IWN_GOOD_CRC_TH_NEVER; 6923 6924 chan = (struct iwn_scan_chan *)frm; 6925 chan->chan = htole16(ieee80211_chan2ieee(ic, c)); 6926 chan->flags = 0; 6927 if (ss->ss_nssid > 0) 6928 chan->flags |= htole32(IWN_CHAN_NPBREQS(1)); 6929 chan->dsp_gain = 0x6e; 6930 6931 /* 6932 * Set the passive/active flag depending upon the channel mode. 6933 * XXX TODO: take the is_active flag into account as well? 6934 */ 6935 if (c->ic_flags & IEEE80211_CHAN_PASSIVE) 6936 chan->flags |= htole32(IWN_CHAN_PASSIVE); 6937 else 6938 chan->flags |= htole32(IWN_CHAN_ACTIVE); 6939 6940 /* 6941 * Calculate the active/passive dwell times. 6942 */ 6943 6944 dwell_active = iwn_get_active_dwell_time(sc, c, ss->ss_nssid); 6945 dwell_passive = iwn_get_passive_dwell_time(sc, c); 6946 6947 /* Make sure they're valid */ 6948 if (dwell_passive <= dwell_active) 6949 dwell_passive = dwell_active + 1; 6950 6951 chan->active = htole16(dwell_active); 6952 chan->passive = htole16(dwell_passive); 6953 6954 if (IEEE80211_IS_CHAN_5GHZ(c)) 6955 chan->rf_gain = 0x3b; 6956 else 6957 chan->rf_gain = 0x28; 6958 6959 DPRINTF(sc, IWN_DEBUG_STATE, 6960 "%s: chan %u flags 0x%x rf_gain 0x%x " 6961 "dsp_gain 0x%x active %d passive %d scan_svc_time %d crc 0x%x " 6962 "isactive=%d numssid=%d\n", __func__, 6963 chan->chan, chan->flags, chan->rf_gain, chan->dsp_gain, 6964 dwell_active, dwell_passive, scan_service_time, 6965 hdr->crc_threshold, is_active, ss->ss_nssid); 6966 6967 hdr->nchan++; 6968 chan++; 6969 buflen = (uint8_t *)chan - buf; 6970 hdr->len = htole16(buflen); 6971 6972 if (sc->sc_is_scanning) { 6973 device_printf(sc->sc_dev, 6974 "%s: called with is_scanning set!\n", 6975 __func__); 6976 } 6977 sc->sc_is_scanning = 1; 6978 6979 DPRINTF(sc, IWN_DEBUG_STATE, "sending scan command nchan=%d\n", 6980 hdr->nchan); 6981 error = iwn_cmd(sc, IWN_CMD_SCAN, buf, buflen, 1); 6982 free(buf, M_DEVBUF); 6983 6984 DPRINTF(sc, IWN_DEBUG_TRACE, "->%s: end\n",__func__); 6985 6986 return error; 6987 } 6988 6989 static int 6990 iwn_auth(struct iwn_softc *sc, struct ieee80211vap *vap) 6991 { 6992 struct iwn_ops *ops = &sc->ops; 6993 struct ieee80211com *ic = &sc->sc_ic; 6994 struct ieee80211_node *ni = vap->iv_bss; 6995 int error; 6996 6997 DPRINTF(sc, IWN_DEBUG_TRACE, "->%s begin\n", __func__); 6998 6999 sc->rxon = &sc->rx_on[IWN_RXON_BSS_CTX]; 7000 /* Update adapter configuration. */ 7001 IEEE80211_ADDR_COPY(sc->rxon->bssid, ni->ni_bssid); 7002 sc->rxon->chan = ieee80211_chan2ieee(ic, ni->ni_chan); 7003 sc->rxon->flags = htole32(IWN_RXON_TSF | IWN_RXON_CTS_TO_SELF); 7004 if (IEEE80211_IS_CHAN_2GHZ(ni->ni_chan)) 7005 sc->rxon->flags |= htole32(IWN_RXON_AUTO | IWN_RXON_24GHZ); 7006 if (ic->ic_flags & IEEE80211_F_SHSLOT) 7007 sc->rxon->flags |= htole32(IWN_RXON_SHSLOT); 7008 if (ic->ic_flags & IEEE80211_F_SHPREAMBLE) 7009 sc->rxon->flags |= htole32(IWN_RXON_SHPREAMBLE); 7010 if (IEEE80211_IS_CHAN_A(ni->ni_chan)) { 7011 sc->rxon->cck_mask = 0; 7012 sc->rxon->ofdm_mask = 0x15; 7013 } else if (IEEE80211_IS_CHAN_B(ni->ni_chan)) { 7014 sc->rxon->cck_mask = 0x03; 7015 sc->rxon->ofdm_mask = 0; 7016 } else { 7017 /* Assume 802.11b/g. */ 7018 sc->rxon->cck_mask = 0x03; 7019 sc->rxon->ofdm_mask = 0x15; 7020 } 7021 7022 /* try HT */ 7023 sc->rxon->flags |= htole32(iwn_get_rxon_ht_flags(sc, ic->ic_curchan)); 7024 7025 DPRINTF(sc, IWN_DEBUG_STATE, "rxon chan %d flags %x cck %x ofdm %x\n", 7026 sc->rxon->chan, sc->rxon->flags, sc->rxon->cck_mask, 7027 sc->rxon->ofdm_mask); 7028 if (sc->sc_is_scanning) 7029 device_printf(sc->sc_dev, 7030 "%s: is_scanning set, before RXON\n", 7031 __func__); 7032 error = iwn_cmd(sc, IWN_CMD_RXON, sc->rxon, sc->rxonsz, 1); 7033 if (error != 0) { 7034 device_printf(sc->sc_dev, "%s: RXON command failed, error %d\n", 7035 __func__, error); 7036 return error; 7037 } 7038 7039 /* Configuration has changed, set TX power accordingly. */ 7040 if ((error = ops->set_txpower(sc, ni->ni_chan, 1)) != 0) { 7041 device_printf(sc->sc_dev, 7042 "%s: could not set TX power, error %d\n", __func__, error); 7043 return error; 7044 } 7045 /* 7046 * Reconfiguring RXON clears the firmware nodes table so we must 7047 * add the broadcast node again. 7048 */ 7049 if ((error = iwn_add_broadcast_node(sc, 1)) != 0) { 7050 device_printf(sc->sc_dev, 7051 "%s: could not add broadcast node, error %d\n", __func__, 7052 error); 7053 return error; 7054 } 7055 7056 DPRINTF(sc, IWN_DEBUG_TRACE, "->%s: end\n",__func__); 7057 7058 return 0; 7059 } 7060 7061 static int 7062 iwn_run(struct iwn_softc *sc, struct ieee80211vap *vap) 7063 { 7064 struct iwn_ops *ops = &sc->ops; 7065 struct ieee80211com *ic = &sc->sc_ic; 7066 struct ieee80211_node *ni = vap->iv_bss; 7067 struct iwn_node_info node; 7068 int error; 7069 7070 DPRINTF(sc, IWN_DEBUG_TRACE, "->%s begin\n", __func__); 7071 7072 sc->rxon = &sc->rx_on[IWN_RXON_BSS_CTX]; 7073 if (ic->ic_opmode == IEEE80211_M_MONITOR) { 7074 /* Link LED blinks while monitoring. */ 7075 iwn_set_led(sc, IWN_LED_LINK, 5, 5); 7076 return 0; 7077 } 7078 if ((error = iwn_set_timing(sc, ni)) != 0) { 7079 device_printf(sc->sc_dev, 7080 "%s: could not set timing, error %d\n", __func__, error); 7081 return error; 7082 } 7083 7084 /* Update adapter configuration. */ 7085 IEEE80211_ADDR_COPY(sc->rxon->bssid, ni->ni_bssid); 7086 sc->rxon->associd = htole16(IEEE80211_AID(ni->ni_associd)); 7087 sc->rxon->chan = ieee80211_chan2ieee(ic, ni->ni_chan); 7088 sc->rxon->flags = htole32(IWN_RXON_TSF | IWN_RXON_CTS_TO_SELF); 7089 if (IEEE80211_IS_CHAN_2GHZ(ni->ni_chan)) 7090 sc->rxon->flags |= htole32(IWN_RXON_AUTO | IWN_RXON_24GHZ); 7091 if (ic->ic_flags & IEEE80211_F_SHSLOT) 7092 sc->rxon->flags |= htole32(IWN_RXON_SHSLOT); 7093 if (ic->ic_flags & IEEE80211_F_SHPREAMBLE) 7094 sc->rxon->flags |= htole32(IWN_RXON_SHPREAMBLE); 7095 if (IEEE80211_IS_CHAN_A(ni->ni_chan)) { 7096 sc->rxon->cck_mask = 0; 7097 sc->rxon->ofdm_mask = 0x15; 7098 } else if (IEEE80211_IS_CHAN_B(ni->ni_chan)) { 7099 sc->rxon->cck_mask = 0x03; 7100 sc->rxon->ofdm_mask = 0; 7101 } else { 7102 /* Assume 802.11b/g. */ 7103 sc->rxon->cck_mask = 0x0f; 7104 sc->rxon->ofdm_mask = 0x15; 7105 } 7106 /* try HT */ 7107 sc->rxon->flags |= htole32(iwn_get_rxon_ht_flags(sc, ni->ni_chan)); 7108 sc->rxon->filter |= htole32(IWN_FILTER_BSS); 7109 DPRINTF(sc, IWN_DEBUG_STATE, "rxon chan %d flags %x, curhtprotmode=%d\n", 7110 sc->rxon->chan, le32toh(sc->rxon->flags), ic->ic_curhtprotmode); 7111 if (sc->sc_is_scanning) 7112 device_printf(sc->sc_dev, 7113 "%s: is_scanning set, before RXON\n", 7114 __func__); 7115 error = iwn_cmd(sc, IWN_CMD_RXON, sc->rxon, sc->rxonsz, 1); 7116 if (error != 0) { 7117 device_printf(sc->sc_dev, 7118 "%s: could not update configuration, error %d\n", __func__, 7119 error); 7120 return error; 7121 } 7122 7123 /* Configuration has changed, set TX power accordingly. */ 7124 if ((error = ops->set_txpower(sc, ni->ni_chan, 1)) != 0) { 7125 device_printf(sc->sc_dev, 7126 "%s: could not set TX power, error %d\n", __func__, error); 7127 return error; 7128 } 7129 7130 /* Fake a join to initialize the TX rate. */ 7131 ((struct iwn_node *)ni)->id = IWN_ID_BSS; 7132 iwn_newassoc(ni, 1); 7133 7134 /* Add BSS node. */ 7135 memset(&node, 0, sizeof node); 7136 IEEE80211_ADDR_COPY(node.macaddr, ni->ni_macaddr); 7137 node.id = IWN_ID_BSS; 7138 if (IEEE80211_IS_CHAN_HT(ni->ni_chan)) { 7139 switch (ni->ni_htcap & IEEE80211_HTCAP_SMPS) { 7140 case IEEE80211_HTCAP_SMPS_ENA: 7141 node.htflags |= htole32(IWN_SMPS_MIMO_DIS); 7142 break; 7143 case IEEE80211_HTCAP_SMPS_DYNAMIC: 7144 node.htflags |= htole32(IWN_SMPS_MIMO_PROT); 7145 break; 7146 } 7147 node.htflags |= htole32(IWN_AMDPU_SIZE_FACTOR(3) | 7148 IWN_AMDPU_DENSITY(5)); /* 4us */ 7149 if (IEEE80211_IS_CHAN_HT40(ni->ni_chan)) 7150 node.htflags |= htole32(IWN_NODE_HT40); 7151 } 7152 DPRINTF(sc, IWN_DEBUG_STATE, "%s: adding BSS node\n", __func__); 7153 error = ops->add_node(sc, &node, 1); 7154 if (error != 0) { 7155 device_printf(sc->sc_dev, 7156 "%s: could not add BSS node, error %d\n", __func__, error); 7157 return error; 7158 } 7159 DPRINTF(sc, IWN_DEBUG_STATE, "%s: setting link quality for node %d\n", 7160 __func__, node.id); 7161 if ((error = iwn_set_link_quality(sc, ni)) != 0) { 7162 device_printf(sc->sc_dev, 7163 "%s: could not setup link quality for node %d, error %d\n", 7164 __func__, node.id, error); 7165 return error; 7166 } 7167 7168 if ((error = iwn_init_sensitivity(sc)) != 0) { 7169 device_printf(sc->sc_dev, 7170 "%s: could not set sensitivity, error %d\n", __func__, 7171 error); 7172 return error; 7173 } 7174 /* Start periodic calibration timer. */ 7175 sc->calib.state = IWN_CALIB_STATE_ASSOC; 7176 sc->calib_cnt = 0; 7177 callout_reset(&sc->calib_to, msecs_to_ticks(500), iwn_calib_timeout, 7178 sc); 7179 7180 /* Link LED always on while associated. */ 7181 iwn_set_led(sc, IWN_LED_LINK, 0, 1); 7182 7183 DPRINTF(sc, IWN_DEBUG_TRACE, "->%s: end\n",__func__); 7184 7185 return 0; 7186 } 7187 7188 /* 7189 * This function is called by upper layer when an ADDBA request is received 7190 * from another STA and before the ADDBA response is sent. 7191 */ 7192 static int 7193 iwn_ampdu_rx_start(struct ieee80211_node *ni, struct ieee80211_rx_ampdu *rap, 7194 int baparamset, int batimeout, int baseqctl) 7195 { 7196 #define MS(_v, _f) (((_v) & _f) >> _f##_S) 7197 struct iwn_softc *sc = ni->ni_ic->ic_softc; 7198 struct iwn_ops *ops = &sc->ops; 7199 struct iwn_node *wn = (void *)ni; 7200 struct iwn_node_info node; 7201 uint16_t ssn; 7202 uint8_t tid; 7203 int error; 7204 7205 DPRINTF(sc, IWN_DEBUG_TRACE, "->Doing %s\n", __func__); 7206 7207 tid = MS(le16toh(baparamset), IEEE80211_BAPS_TID); 7208 ssn = MS(le16toh(baseqctl), IEEE80211_BASEQ_START); 7209 7210 memset(&node, 0, sizeof node); 7211 node.id = wn->id; 7212 node.control = IWN_NODE_UPDATE; 7213 node.flags = IWN_FLAG_SET_ADDBA; 7214 node.addba_tid = tid; 7215 node.addba_ssn = htole16(ssn); 7216 DPRINTF(sc, IWN_DEBUG_RECV, "ADDBA RA=%d TID=%d SSN=%d\n", 7217 wn->id, tid, ssn); 7218 error = ops->add_node(sc, &node, 1); 7219 if (error != 0) 7220 return error; 7221 return sc->sc_ampdu_rx_start(ni, rap, baparamset, batimeout, baseqctl); 7222 #undef MS 7223 } 7224 7225 /* 7226 * This function is called by upper layer on teardown of an HT-immediate 7227 * Block Ack agreement (eg. uppon receipt of a DELBA frame). 7228 */ 7229 static void 7230 iwn_ampdu_rx_stop(struct ieee80211_node *ni, struct ieee80211_rx_ampdu *rap) 7231 { 7232 struct ieee80211com *ic = ni->ni_ic; 7233 struct iwn_softc *sc = ic->ic_softc; 7234 struct iwn_ops *ops = &sc->ops; 7235 struct iwn_node *wn = (void *)ni; 7236 struct iwn_node_info node; 7237 uint8_t tid; 7238 7239 DPRINTF(sc, IWN_DEBUG_TRACE, "->Doing %s\n", __func__); 7240 7241 /* XXX: tid as an argument */ 7242 for (tid = 0; tid < WME_NUM_TID; tid++) { 7243 if (&ni->ni_rx_ampdu[tid] == rap) 7244 break; 7245 } 7246 7247 memset(&node, 0, sizeof node); 7248 node.id = wn->id; 7249 node.control = IWN_NODE_UPDATE; 7250 node.flags = IWN_FLAG_SET_DELBA; 7251 node.delba_tid = tid; 7252 DPRINTF(sc, IWN_DEBUG_RECV, "DELBA RA=%d TID=%d\n", wn->id, tid); 7253 (void)ops->add_node(sc, &node, 1); 7254 sc->sc_ampdu_rx_stop(ni, rap); 7255 } 7256 7257 static int 7258 iwn_addba_request(struct ieee80211_node *ni, struct ieee80211_tx_ampdu *tap, 7259 int dialogtoken, int baparamset, int batimeout) 7260 { 7261 struct iwn_softc *sc = ni->ni_ic->ic_softc; 7262 int qid; 7263 7264 DPRINTF(sc, IWN_DEBUG_TRACE, "->Doing %s\n", __func__); 7265 7266 for (qid = sc->firstaggqueue; qid < sc->ntxqs; qid++) { 7267 if (sc->qid2tap[qid] == NULL) 7268 break; 7269 } 7270 if (qid == sc->ntxqs) { 7271 DPRINTF(sc, IWN_DEBUG_XMIT, "%s: not free aggregation queue\n", 7272 __func__); 7273 return 0; 7274 } 7275 tap->txa_private = malloc(sizeof(int), M_DEVBUF, M_NOWAIT); 7276 if (tap->txa_private == NULL) { 7277 device_printf(sc->sc_dev, 7278 "%s: failed to alloc TX aggregation structure\n", __func__); 7279 return 0; 7280 } 7281 sc->qid2tap[qid] = tap; 7282 *(int *)tap->txa_private = qid; 7283 return sc->sc_addba_request(ni, tap, dialogtoken, baparamset, 7284 batimeout); 7285 } 7286 7287 static int 7288 iwn_addba_response(struct ieee80211_node *ni, struct ieee80211_tx_ampdu *tap, 7289 int code, int baparamset, int batimeout) 7290 { 7291 struct iwn_softc *sc = ni->ni_ic->ic_softc; 7292 int qid = *(int *)tap->txa_private; 7293 uint8_t tid = tap->txa_tid; 7294 int ret; 7295 7296 DPRINTF(sc, IWN_DEBUG_TRACE, "->Doing %s\n", __func__); 7297 7298 if (code == IEEE80211_STATUS_SUCCESS) { 7299 ni->ni_txseqs[tid] = tap->txa_start & 0xfff; 7300 ret = iwn_ampdu_tx_start(ni->ni_ic, ni, tid); 7301 if (ret != 1) 7302 return ret; 7303 } else { 7304 sc->qid2tap[qid] = NULL; 7305 free(tap->txa_private, M_DEVBUF); 7306 tap->txa_private = NULL; 7307 } 7308 return sc->sc_addba_response(ni, tap, code, baparamset, batimeout); 7309 } 7310 7311 /* 7312 * This function is called by upper layer when an ADDBA response is received 7313 * from another STA. 7314 */ 7315 static int 7316 iwn_ampdu_tx_start(struct ieee80211com *ic, struct ieee80211_node *ni, 7317 uint8_t tid) 7318 { 7319 struct ieee80211_tx_ampdu *tap = &ni->ni_tx_ampdu[tid]; 7320 struct iwn_softc *sc = ni->ni_ic->ic_softc; 7321 struct iwn_ops *ops = &sc->ops; 7322 struct iwn_node *wn = (void *)ni; 7323 struct iwn_node_info node; 7324 int error, qid; 7325 7326 DPRINTF(sc, IWN_DEBUG_TRACE, "->Doing %s\n", __func__); 7327 7328 /* Enable TX for the specified RA/TID. */ 7329 wn->disable_tid &= ~(1 << tid); 7330 memset(&node, 0, sizeof node); 7331 node.id = wn->id; 7332 node.control = IWN_NODE_UPDATE; 7333 node.flags = IWN_FLAG_SET_DISABLE_TID; 7334 node.disable_tid = htole16(wn->disable_tid); 7335 error = ops->add_node(sc, &node, 1); 7336 if (error != 0) 7337 return 0; 7338 7339 if ((error = iwn_nic_lock(sc)) != 0) 7340 return 0; 7341 qid = *(int *)tap->txa_private; 7342 DPRINTF(sc, IWN_DEBUG_XMIT, "%s: ra=%d tid=%d ssn=%d qid=%d\n", 7343 __func__, wn->id, tid, tap->txa_start, qid); 7344 ops->ampdu_tx_start(sc, ni, qid, tid, tap->txa_start & 0xfff); 7345 iwn_nic_unlock(sc); 7346 7347 iwn_set_link_quality(sc, ni); 7348 return 1; 7349 } 7350 7351 static void 7352 iwn_ampdu_tx_stop(struct ieee80211_node *ni, struct ieee80211_tx_ampdu *tap) 7353 { 7354 struct iwn_softc *sc = ni->ni_ic->ic_softc; 7355 struct iwn_ops *ops = &sc->ops; 7356 uint8_t tid = tap->txa_tid; 7357 int qid; 7358 7359 DPRINTF(sc, IWN_DEBUG_TRACE, "->Doing %s\n", __func__); 7360 7361 sc->sc_addba_stop(ni, tap); 7362 7363 if (tap->txa_private == NULL) 7364 return; 7365 7366 qid = *(int *)tap->txa_private; 7367 if (sc->txq[qid].queued != 0) 7368 return; 7369 if (iwn_nic_lock(sc) != 0) 7370 return; 7371 ops->ampdu_tx_stop(sc, qid, tid, tap->txa_start & 0xfff); 7372 iwn_nic_unlock(sc); 7373 sc->qid2tap[qid] = NULL; 7374 free(tap->txa_private, M_DEVBUF); 7375 tap->txa_private = NULL; 7376 } 7377 7378 static void 7379 iwn4965_ampdu_tx_start(struct iwn_softc *sc, struct ieee80211_node *ni, 7380 int qid, uint8_t tid, uint16_t ssn) 7381 { 7382 struct iwn_node *wn = (void *)ni; 7383 7384 DPRINTF(sc, IWN_DEBUG_TRACE, "->Doing %s\n", __func__); 7385 7386 /* Stop TX scheduler while we're changing its configuration. */ 7387 iwn_prph_write(sc, IWN4965_SCHED_QUEUE_STATUS(qid), 7388 IWN4965_TXQ_STATUS_CHGACT); 7389 7390 /* Assign RA/TID translation to the queue. */ 7391 iwn_mem_write_2(sc, sc->sched_base + IWN4965_SCHED_TRANS_TBL(qid), 7392 wn->id << 4 | tid); 7393 7394 /* Enable chain-building mode for the queue. */ 7395 iwn_prph_setbits(sc, IWN4965_SCHED_QCHAIN_SEL, 1 << qid); 7396 7397 /* Set starting sequence number from the ADDBA request. */ 7398 sc->txq[qid].cur = sc->txq[qid].read = (ssn & 0xff); 7399 IWN_WRITE(sc, IWN_HBUS_TARG_WRPTR, qid << 8 | (ssn & 0xff)); 7400 iwn_prph_write(sc, IWN4965_SCHED_QUEUE_RDPTR(qid), ssn); 7401 7402 /* Set scheduler window size. */ 7403 iwn_mem_write(sc, sc->sched_base + IWN4965_SCHED_QUEUE_OFFSET(qid), 7404 IWN_SCHED_WINSZ); 7405 /* Set scheduler frame limit. */ 7406 iwn_mem_write(sc, sc->sched_base + IWN4965_SCHED_QUEUE_OFFSET(qid) + 4, 7407 IWN_SCHED_LIMIT << 16); 7408 7409 /* Enable interrupts for the queue. */ 7410 iwn_prph_setbits(sc, IWN4965_SCHED_INTR_MASK, 1 << qid); 7411 7412 /* Mark the queue as active. */ 7413 iwn_prph_write(sc, IWN4965_SCHED_QUEUE_STATUS(qid), 7414 IWN4965_TXQ_STATUS_ACTIVE | IWN4965_TXQ_STATUS_AGGR_ENA | 7415 iwn_tid2fifo[tid] << 1); 7416 } 7417 7418 static void 7419 iwn4965_ampdu_tx_stop(struct iwn_softc *sc, int qid, uint8_t tid, uint16_t ssn) 7420 { 7421 DPRINTF(sc, IWN_DEBUG_TRACE, "->Doing %s\n", __func__); 7422 7423 /* Stop TX scheduler while we're changing its configuration. */ 7424 iwn_prph_write(sc, IWN4965_SCHED_QUEUE_STATUS(qid), 7425 IWN4965_TXQ_STATUS_CHGACT); 7426 7427 /* Set starting sequence number from the ADDBA request. */ 7428 IWN_WRITE(sc, IWN_HBUS_TARG_WRPTR, qid << 8 | (ssn & 0xff)); 7429 iwn_prph_write(sc, IWN4965_SCHED_QUEUE_RDPTR(qid), ssn); 7430 7431 /* Disable interrupts for the queue. */ 7432 iwn_prph_clrbits(sc, IWN4965_SCHED_INTR_MASK, 1 << qid); 7433 7434 /* Mark the queue as inactive. */ 7435 iwn_prph_write(sc, IWN4965_SCHED_QUEUE_STATUS(qid), 7436 IWN4965_TXQ_STATUS_INACTIVE | iwn_tid2fifo[tid] << 1); 7437 } 7438 7439 static void 7440 iwn5000_ampdu_tx_start(struct iwn_softc *sc, struct ieee80211_node *ni, 7441 int qid, uint8_t tid, uint16_t ssn) 7442 { 7443 DPRINTF(sc, IWN_DEBUG_TRACE, "->Doing %s\n", __func__); 7444 7445 struct iwn_node *wn = (void *)ni; 7446 7447 /* Stop TX scheduler while we're changing its configuration. */ 7448 iwn_prph_write(sc, IWN5000_SCHED_QUEUE_STATUS(qid), 7449 IWN5000_TXQ_STATUS_CHGACT); 7450 7451 /* Assign RA/TID translation to the queue. */ 7452 iwn_mem_write_2(sc, sc->sched_base + IWN5000_SCHED_TRANS_TBL(qid), 7453 wn->id << 4 | tid); 7454 7455 /* Enable chain-building mode for the queue. */ 7456 iwn_prph_setbits(sc, IWN5000_SCHED_QCHAIN_SEL, 1 << qid); 7457 7458 /* Enable aggregation for the queue. */ 7459 iwn_prph_setbits(sc, IWN5000_SCHED_AGGR_SEL, 1 << qid); 7460 7461 /* Set starting sequence number from the ADDBA request. */ 7462 sc->txq[qid].cur = sc->txq[qid].read = (ssn & 0xff); 7463 IWN_WRITE(sc, IWN_HBUS_TARG_WRPTR, qid << 8 | (ssn & 0xff)); 7464 iwn_prph_write(sc, IWN5000_SCHED_QUEUE_RDPTR(qid), ssn); 7465 7466 /* Set scheduler window size and frame limit. */ 7467 iwn_mem_write(sc, sc->sched_base + IWN5000_SCHED_QUEUE_OFFSET(qid) + 4, 7468 IWN_SCHED_LIMIT << 16 | IWN_SCHED_WINSZ); 7469 7470 /* Enable interrupts for the queue. */ 7471 iwn_prph_setbits(sc, IWN5000_SCHED_INTR_MASK, 1 << qid); 7472 7473 /* Mark the queue as active. */ 7474 iwn_prph_write(sc, IWN5000_SCHED_QUEUE_STATUS(qid), 7475 IWN5000_TXQ_STATUS_ACTIVE | iwn_tid2fifo[tid]); 7476 } 7477 7478 static void 7479 iwn5000_ampdu_tx_stop(struct iwn_softc *sc, int qid, uint8_t tid, uint16_t ssn) 7480 { 7481 DPRINTF(sc, IWN_DEBUG_TRACE, "->Doing %s\n", __func__); 7482 7483 /* Stop TX scheduler while we're changing its configuration. */ 7484 iwn_prph_write(sc, IWN5000_SCHED_QUEUE_STATUS(qid), 7485 IWN5000_TXQ_STATUS_CHGACT); 7486 7487 /* Disable aggregation for the queue. */ 7488 iwn_prph_clrbits(sc, IWN5000_SCHED_AGGR_SEL, 1 << qid); 7489 7490 /* Set starting sequence number from the ADDBA request. */ 7491 IWN_WRITE(sc, IWN_HBUS_TARG_WRPTR, qid << 8 | (ssn & 0xff)); 7492 iwn_prph_write(sc, IWN5000_SCHED_QUEUE_RDPTR(qid), ssn); 7493 7494 /* Disable interrupts for the queue. */ 7495 iwn_prph_clrbits(sc, IWN5000_SCHED_INTR_MASK, 1 << qid); 7496 7497 /* Mark the queue as inactive. */ 7498 iwn_prph_write(sc, IWN5000_SCHED_QUEUE_STATUS(qid), 7499 IWN5000_TXQ_STATUS_INACTIVE | iwn_tid2fifo[tid]); 7500 } 7501 7502 /* 7503 * Query calibration tables from the initialization firmware. We do this 7504 * only once at first boot. Called from a process context. 7505 */ 7506 static int 7507 iwn5000_query_calibration(struct iwn_softc *sc) 7508 { 7509 struct iwn5000_calib_config cmd; 7510 int error; 7511 7512 memset(&cmd, 0, sizeof cmd); 7513 cmd.ucode.once.enable = htole32(0xffffffff); 7514 cmd.ucode.once.start = htole32(0xffffffff); 7515 cmd.ucode.once.send = htole32(0xffffffff); 7516 cmd.ucode.flags = htole32(0xffffffff); 7517 DPRINTF(sc, IWN_DEBUG_CALIBRATE, "%s: sending calibration query\n", 7518 __func__); 7519 error = iwn_cmd(sc, IWN5000_CMD_CALIB_CONFIG, &cmd, sizeof cmd, 0); 7520 if (error != 0) 7521 return error; 7522 7523 /* Wait at most two seconds for calibration to complete. */ 7524 if (!(sc->sc_flags & IWN_FLAG_CALIB_DONE)) 7525 error = msleep(sc, &sc->sc_mtx, PCATCH, "iwncal", 2 * hz); 7526 return error; 7527 } 7528 7529 /* 7530 * Send calibration results to the runtime firmware. These results were 7531 * obtained on first boot from the initialization firmware. 7532 */ 7533 static int 7534 iwn5000_send_calibration(struct iwn_softc *sc) 7535 { 7536 int idx, error; 7537 7538 for (idx = 0; idx < IWN5000_PHY_CALIB_MAX_RESULT; idx++) { 7539 if (!(sc->base_params->calib_need & (1<<idx))) { 7540 DPRINTF(sc, IWN_DEBUG_CALIBRATE, 7541 "No need of calib %d\n", 7542 idx); 7543 continue; /* no need for this calib */ 7544 } 7545 if (sc->calibcmd[idx].buf == NULL) { 7546 DPRINTF(sc, IWN_DEBUG_CALIBRATE, 7547 "Need calib idx : %d but no available data\n", 7548 idx); 7549 continue; 7550 } 7551 7552 DPRINTF(sc, IWN_DEBUG_CALIBRATE, 7553 "send calibration result idx=%d len=%d\n", idx, 7554 sc->calibcmd[idx].len); 7555 error = iwn_cmd(sc, IWN_CMD_PHY_CALIB, sc->calibcmd[idx].buf, 7556 sc->calibcmd[idx].len, 0); 7557 if (error != 0) { 7558 device_printf(sc->sc_dev, 7559 "%s: could not send calibration result, error %d\n", 7560 __func__, error); 7561 return error; 7562 } 7563 } 7564 return 0; 7565 } 7566 7567 static int 7568 iwn5000_send_wimax_coex(struct iwn_softc *sc) 7569 { 7570 struct iwn5000_wimax_coex wimax; 7571 7572 #if 0 7573 if (sc->hw_type == IWN_HW_REV_TYPE_6050) { 7574 /* Enable WiMAX coexistence for combo adapters. */ 7575 wimax.flags = 7576 IWN_WIMAX_COEX_ASSOC_WA_UNMASK | 7577 IWN_WIMAX_COEX_UNASSOC_WA_UNMASK | 7578 IWN_WIMAX_COEX_STA_TABLE_VALID | 7579 IWN_WIMAX_COEX_ENABLE; 7580 memcpy(wimax.events, iwn6050_wimax_events, 7581 sizeof iwn6050_wimax_events); 7582 } else 7583 #endif 7584 { 7585 /* Disable WiMAX coexistence. */ 7586 wimax.flags = 0; 7587 memset(wimax.events, 0, sizeof wimax.events); 7588 } 7589 DPRINTF(sc, IWN_DEBUG_RESET, "%s: Configuring WiMAX coexistence\n", 7590 __func__); 7591 return iwn_cmd(sc, IWN5000_CMD_WIMAX_COEX, &wimax, sizeof wimax, 0); 7592 } 7593 7594 static int 7595 iwn5000_crystal_calib(struct iwn_softc *sc) 7596 { 7597 struct iwn5000_phy_calib_crystal cmd; 7598 7599 memset(&cmd, 0, sizeof cmd); 7600 cmd.code = IWN5000_PHY_CALIB_CRYSTAL; 7601 cmd.ngroups = 1; 7602 cmd.isvalid = 1; 7603 cmd.cap_pin[0] = le32toh(sc->eeprom_crystal) & 0xff; 7604 cmd.cap_pin[1] = (le32toh(sc->eeprom_crystal) >> 16) & 0xff; 7605 DPRINTF(sc, IWN_DEBUG_CALIBRATE, "sending crystal calibration %d, %d\n", 7606 cmd.cap_pin[0], cmd.cap_pin[1]); 7607 return iwn_cmd(sc, IWN_CMD_PHY_CALIB, &cmd, sizeof cmd, 0); 7608 } 7609 7610 static int 7611 iwn5000_temp_offset_calib(struct iwn_softc *sc) 7612 { 7613 struct iwn5000_phy_calib_temp_offset cmd; 7614 7615 memset(&cmd, 0, sizeof cmd); 7616 cmd.code = IWN5000_PHY_CALIB_TEMP_OFFSET; 7617 cmd.ngroups = 1; 7618 cmd.isvalid = 1; 7619 if (sc->eeprom_temp != 0) 7620 cmd.offset = htole16(sc->eeprom_temp); 7621 else 7622 cmd.offset = htole16(IWN_DEFAULT_TEMP_OFFSET); 7623 DPRINTF(sc, IWN_DEBUG_CALIBRATE, "setting radio sensor offset to %d\n", 7624 le16toh(cmd.offset)); 7625 return iwn_cmd(sc, IWN_CMD_PHY_CALIB, &cmd, sizeof cmd, 0); 7626 } 7627 7628 static int 7629 iwn5000_temp_offset_calibv2(struct iwn_softc *sc) 7630 { 7631 struct iwn5000_phy_calib_temp_offsetv2 cmd; 7632 7633 memset(&cmd, 0, sizeof cmd); 7634 cmd.code = IWN5000_PHY_CALIB_TEMP_OFFSET; 7635 cmd.ngroups = 1; 7636 cmd.isvalid = 1; 7637 if (sc->eeprom_temp != 0) { 7638 cmd.offset_low = htole16(sc->eeprom_temp); 7639 cmd.offset_high = htole16(sc->eeprom_temp_high); 7640 } else { 7641 cmd.offset_low = htole16(IWN_DEFAULT_TEMP_OFFSET); 7642 cmd.offset_high = htole16(IWN_DEFAULT_TEMP_OFFSET); 7643 } 7644 cmd.burnt_voltage_ref = htole16(sc->eeprom_voltage); 7645 7646 DPRINTF(sc, IWN_DEBUG_CALIBRATE, 7647 "setting radio sensor low offset to %d, high offset to %d, voltage to %d\n", 7648 le16toh(cmd.offset_low), 7649 le16toh(cmd.offset_high), 7650 le16toh(cmd.burnt_voltage_ref)); 7651 7652 return iwn_cmd(sc, IWN_CMD_PHY_CALIB, &cmd, sizeof cmd, 0); 7653 } 7654 7655 /* 7656 * This function is called after the runtime firmware notifies us of its 7657 * readiness (called in a process context). 7658 */ 7659 static int 7660 iwn4965_post_alive(struct iwn_softc *sc) 7661 { 7662 int error, qid; 7663 7664 if ((error = iwn_nic_lock(sc)) != 0) 7665 return error; 7666 7667 DPRINTF(sc, IWN_DEBUG_TRACE, "->Doing %s\n", __func__); 7668 7669 /* Clear TX scheduler state in SRAM. */ 7670 sc->sched_base = iwn_prph_read(sc, IWN_SCHED_SRAM_ADDR); 7671 iwn_mem_set_region_4(sc, sc->sched_base + IWN4965_SCHED_CTX_OFF, 0, 7672 IWN4965_SCHED_CTX_LEN / sizeof (uint32_t)); 7673 7674 /* Set physical address of TX scheduler rings (1KB aligned). */ 7675 iwn_prph_write(sc, IWN4965_SCHED_DRAM_ADDR, sc->sched_dma.paddr >> 10); 7676 7677 IWN_SETBITS(sc, IWN_FH_TX_CHICKEN, IWN_FH_TX_CHICKEN_SCHED_RETRY); 7678 7679 /* Disable chain mode for all our 16 queues. */ 7680 iwn_prph_write(sc, IWN4965_SCHED_QCHAIN_SEL, 0); 7681 7682 for (qid = 0; qid < IWN4965_NTXQUEUES; qid++) { 7683 iwn_prph_write(sc, IWN4965_SCHED_QUEUE_RDPTR(qid), 0); 7684 IWN_WRITE(sc, IWN_HBUS_TARG_WRPTR, qid << 8 | 0); 7685 7686 /* Set scheduler window size. */ 7687 iwn_mem_write(sc, sc->sched_base + 7688 IWN4965_SCHED_QUEUE_OFFSET(qid), IWN_SCHED_WINSZ); 7689 /* Set scheduler frame limit. */ 7690 iwn_mem_write(sc, sc->sched_base + 7691 IWN4965_SCHED_QUEUE_OFFSET(qid) + 4, 7692 IWN_SCHED_LIMIT << 16); 7693 } 7694 7695 /* Enable interrupts for all our 16 queues. */ 7696 iwn_prph_write(sc, IWN4965_SCHED_INTR_MASK, 0xffff); 7697 /* Identify TX FIFO rings (0-7). */ 7698 iwn_prph_write(sc, IWN4965_SCHED_TXFACT, 0xff); 7699 7700 /* Mark TX rings (4 EDCA + cmd + 2 HCCA) as active. */ 7701 for (qid = 0; qid < 7; qid++) { 7702 static uint8_t qid2fifo[] = { 3, 2, 1, 0, 4, 5, 6 }; 7703 iwn_prph_write(sc, IWN4965_SCHED_QUEUE_STATUS(qid), 7704 IWN4965_TXQ_STATUS_ACTIVE | qid2fifo[qid] << 1); 7705 } 7706 iwn_nic_unlock(sc); 7707 return 0; 7708 } 7709 7710 /* 7711 * This function is called after the initialization or runtime firmware 7712 * notifies us of its readiness (called in a process context). 7713 */ 7714 static int 7715 iwn5000_post_alive(struct iwn_softc *sc) 7716 { 7717 int error, qid; 7718 7719 DPRINTF(sc, IWN_DEBUG_TRACE, "->%s begin\n", __func__); 7720 7721 /* Switch to using ICT interrupt mode. */ 7722 iwn5000_ict_reset(sc); 7723 7724 if ((error = iwn_nic_lock(sc)) != 0){ 7725 DPRINTF(sc, IWN_DEBUG_TRACE, "->%s end in error\n", __func__); 7726 return error; 7727 } 7728 7729 /* Clear TX scheduler state in SRAM. */ 7730 sc->sched_base = iwn_prph_read(sc, IWN_SCHED_SRAM_ADDR); 7731 iwn_mem_set_region_4(sc, sc->sched_base + IWN5000_SCHED_CTX_OFF, 0, 7732 IWN5000_SCHED_CTX_LEN / sizeof (uint32_t)); 7733 7734 /* Set physical address of TX scheduler rings (1KB aligned). */ 7735 iwn_prph_write(sc, IWN5000_SCHED_DRAM_ADDR, sc->sched_dma.paddr >> 10); 7736 7737 IWN_SETBITS(sc, IWN_FH_TX_CHICKEN, IWN_FH_TX_CHICKEN_SCHED_RETRY); 7738 7739 /* Enable chain mode for all queues, except command queue. */ 7740 if (sc->sc_flags & IWN_FLAG_PAN_SUPPORT) 7741 iwn_prph_write(sc, IWN5000_SCHED_QCHAIN_SEL, 0xfffdf); 7742 else 7743 iwn_prph_write(sc, IWN5000_SCHED_QCHAIN_SEL, 0xfffef); 7744 iwn_prph_write(sc, IWN5000_SCHED_AGGR_SEL, 0); 7745 7746 for (qid = 0; qid < IWN5000_NTXQUEUES; qid++) { 7747 iwn_prph_write(sc, IWN5000_SCHED_QUEUE_RDPTR(qid), 0); 7748 IWN_WRITE(sc, IWN_HBUS_TARG_WRPTR, qid << 8 | 0); 7749 7750 iwn_mem_write(sc, sc->sched_base + 7751 IWN5000_SCHED_QUEUE_OFFSET(qid), 0); 7752 /* Set scheduler window size and frame limit. */ 7753 iwn_mem_write(sc, sc->sched_base + 7754 IWN5000_SCHED_QUEUE_OFFSET(qid) + 4, 7755 IWN_SCHED_LIMIT << 16 | IWN_SCHED_WINSZ); 7756 } 7757 7758 /* Enable interrupts for all our 20 queues. */ 7759 iwn_prph_write(sc, IWN5000_SCHED_INTR_MASK, 0xfffff); 7760 /* Identify TX FIFO rings (0-7). */ 7761 iwn_prph_write(sc, IWN5000_SCHED_TXFACT, 0xff); 7762 7763 /* Mark TX rings (4 EDCA + cmd + 2 HCCA) as active. */ 7764 if (sc->sc_flags & IWN_FLAG_PAN_SUPPORT) { 7765 /* Mark TX rings as active. */ 7766 for (qid = 0; qid < 11; qid++) { 7767 static uint8_t qid2fifo[] = { 3, 2, 1, 0, 0, 4, 2, 5, 4, 7, 5 }; 7768 iwn_prph_write(sc, IWN5000_SCHED_QUEUE_STATUS(qid), 7769 IWN5000_TXQ_STATUS_ACTIVE | qid2fifo[qid]); 7770 } 7771 } else { 7772 /* Mark TX rings (4 EDCA + cmd + 2 HCCA) as active. */ 7773 for (qid = 0; qid < 7; qid++) { 7774 static uint8_t qid2fifo[] = { 3, 2, 1, 0, 7, 5, 6 }; 7775 iwn_prph_write(sc, IWN5000_SCHED_QUEUE_STATUS(qid), 7776 IWN5000_TXQ_STATUS_ACTIVE | qid2fifo[qid]); 7777 } 7778 } 7779 iwn_nic_unlock(sc); 7780 7781 /* Configure WiMAX coexistence for combo adapters. */ 7782 error = iwn5000_send_wimax_coex(sc); 7783 if (error != 0) { 7784 device_printf(sc->sc_dev, 7785 "%s: could not configure WiMAX coexistence, error %d\n", 7786 __func__, error); 7787 return error; 7788 } 7789 if (sc->hw_type != IWN_HW_REV_TYPE_5150) { 7790 /* Perform crystal calibration. */ 7791 error = iwn5000_crystal_calib(sc); 7792 if (error != 0) { 7793 device_printf(sc->sc_dev, 7794 "%s: crystal calibration failed, error %d\n", 7795 __func__, error); 7796 return error; 7797 } 7798 } 7799 if (!(sc->sc_flags & IWN_FLAG_CALIB_DONE)) { 7800 /* Query calibration from the initialization firmware. */ 7801 if ((error = iwn5000_query_calibration(sc)) != 0) { 7802 device_printf(sc->sc_dev, 7803 "%s: could not query calibration, error %d\n", 7804 __func__, error); 7805 return error; 7806 } 7807 /* 7808 * We have the calibration results now, reboot with the 7809 * runtime firmware (call ourselves recursively!) 7810 */ 7811 iwn_hw_stop(sc); 7812 error = iwn_hw_init(sc); 7813 } else { 7814 /* Send calibration results to runtime firmware. */ 7815 error = iwn5000_send_calibration(sc); 7816 } 7817 7818 DPRINTF(sc, IWN_DEBUG_TRACE, "->%s: end\n",__func__); 7819 7820 return error; 7821 } 7822 7823 /* 7824 * The firmware boot code is small and is intended to be copied directly into 7825 * the NIC internal memory (no DMA transfer). 7826 */ 7827 static int 7828 iwn4965_load_bootcode(struct iwn_softc *sc, const uint8_t *ucode, int size) 7829 { 7830 int error, ntries; 7831 7832 size /= sizeof (uint32_t); 7833 7834 if ((error = iwn_nic_lock(sc)) != 0) 7835 return error; 7836 7837 /* Copy microcode image into NIC memory. */ 7838 iwn_prph_write_region_4(sc, IWN_BSM_SRAM_BASE, 7839 (const uint32_t *)ucode, size); 7840 7841 iwn_prph_write(sc, IWN_BSM_WR_MEM_SRC, 0); 7842 iwn_prph_write(sc, IWN_BSM_WR_MEM_DST, IWN_FW_TEXT_BASE); 7843 iwn_prph_write(sc, IWN_BSM_WR_DWCOUNT, size); 7844 7845 /* Start boot load now. */ 7846 iwn_prph_write(sc, IWN_BSM_WR_CTRL, IWN_BSM_WR_CTRL_START); 7847 7848 /* Wait for transfer to complete. */ 7849 for (ntries = 0; ntries < 1000; ntries++) { 7850 if (!(iwn_prph_read(sc, IWN_BSM_WR_CTRL) & 7851 IWN_BSM_WR_CTRL_START)) 7852 break; 7853 DELAY(10); 7854 } 7855 if (ntries == 1000) { 7856 device_printf(sc->sc_dev, "%s: could not load boot firmware\n", 7857 __func__); 7858 iwn_nic_unlock(sc); 7859 return ETIMEDOUT; 7860 } 7861 7862 /* Enable boot after power up. */ 7863 iwn_prph_write(sc, IWN_BSM_WR_CTRL, IWN_BSM_WR_CTRL_START_EN); 7864 7865 iwn_nic_unlock(sc); 7866 return 0; 7867 } 7868 7869 static int 7870 iwn4965_load_firmware(struct iwn_softc *sc) 7871 { 7872 struct iwn_fw_info *fw = &sc->fw; 7873 struct iwn_dma_info *dma = &sc->fw_dma; 7874 int error; 7875 7876 /* Copy initialization sections into pre-allocated DMA-safe memory. */ 7877 memcpy(dma->vaddr, fw->init.data, fw->init.datasz); 7878 bus_dmamap_sync(dma->tag, dma->map, BUS_DMASYNC_PREWRITE); 7879 memcpy(dma->vaddr + IWN4965_FW_DATA_MAXSZ, 7880 fw->init.text, fw->init.textsz); 7881 bus_dmamap_sync(dma->tag, dma->map, BUS_DMASYNC_PREWRITE); 7882 7883 /* Tell adapter where to find initialization sections. */ 7884 if ((error = iwn_nic_lock(sc)) != 0) 7885 return error; 7886 iwn_prph_write(sc, IWN_BSM_DRAM_DATA_ADDR, dma->paddr >> 4); 7887 iwn_prph_write(sc, IWN_BSM_DRAM_DATA_SIZE, fw->init.datasz); 7888 iwn_prph_write(sc, IWN_BSM_DRAM_TEXT_ADDR, 7889 (dma->paddr + IWN4965_FW_DATA_MAXSZ) >> 4); 7890 iwn_prph_write(sc, IWN_BSM_DRAM_TEXT_SIZE, fw->init.textsz); 7891 iwn_nic_unlock(sc); 7892 7893 /* Load firmware boot code. */ 7894 error = iwn4965_load_bootcode(sc, fw->boot.text, fw->boot.textsz); 7895 if (error != 0) { 7896 device_printf(sc->sc_dev, "%s: could not load boot firmware\n", 7897 __func__); 7898 return error; 7899 } 7900 /* Now press "execute". */ 7901 IWN_WRITE(sc, IWN_RESET, 0); 7902 7903 /* Wait at most one second for first alive notification. */ 7904 if ((error = msleep(sc, &sc->sc_mtx, PCATCH, "iwninit", hz)) != 0) { 7905 device_printf(sc->sc_dev, 7906 "%s: timeout waiting for adapter to initialize, error %d\n", 7907 __func__, error); 7908 return error; 7909 } 7910 7911 /* Retrieve current temperature for initial TX power calibration. */ 7912 sc->rawtemp = sc->ucode_info.temp[3].chan20MHz; 7913 sc->temp = iwn4965_get_temperature(sc); 7914 7915 /* Copy runtime sections into pre-allocated DMA-safe memory. */ 7916 memcpy(dma->vaddr, fw->main.data, fw->main.datasz); 7917 bus_dmamap_sync(dma->tag, dma->map, BUS_DMASYNC_PREWRITE); 7918 memcpy(dma->vaddr + IWN4965_FW_DATA_MAXSZ, 7919 fw->main.text, fw->main.textsz); 7920 bus_dmamap_sync(dma->tag, dma->map, BUS_DMASYNC_PREWRITE); 7921 7922 /* Tell adapter where to find runtime sections. */ 7923 if ((error = iwn_nic_lock(sc)) != 0) 7924 return error; 7925 iwn_prph_write(sc, IWN_BSM_DRAM_DATA_ADDR, dma->paddr >> 4); 7926 iwn_prph_write(sc, IWN_BSM_DRAM_DATA_SIZE, fw->main.datasz); 7927 iwn_prph_write(sc, IWN_BSM_DRAM_TEXT_ADDR, 7928 (dma->paddr + IWN4965_FW_DATA_MAXSZ) >> 4); 7929 iwn_prph_write(sc, IWN_BSM_DRAM_TEXT_SIZE, 7930 IWN_FW_UPDATED | fw->main.textsz); 7931 iwn_nic_unlock(sc); 7932 7933 return 0; 7934 } 7935 7936 static int 7937 iwn5000_load_firmware_section(struct iwn_softc *sc, uint32_t dst, 7938 const uint8_t *section, int size) 7939 { 7940 struct iwn_dma_info *dma = &sc->fw_dma; 7941 int error; 7942 7943 DPRINTF(sc, IWN_DEBUG_TRACE, "->Doing %s\n", __func__); 7944 7945 /* Copy firmware section into pre-allocated DMA-safe memory. */ 7946 memcpy(dma->vaddr, section, size); 7947 bus_dmamap_sync(dma->tag, dma->map, BUS_DMASYNC_PREWRITE); 7948 7949 if ((error = iwn_nic_lock(sc)) != 0) 7950 return error; 7951 7952 IWN_WRITE(sc, IWN_FH_TX_CONFIG(IWN_SRVC_DMACHNL), 7953 IWN_FH_TX_CONFIG_DMA_PAUSE); 7954 7955 IWN_WRITE(sc, IWN_FH_SRAM_ADDR(IWN_SRVC_DMACHNL), dst); 7956 IWN_WRITE(sc, IWN_FH_TFBD_CTRL0(IWN_SRVC_DMACHNL), 7957 IWN_LOADDR(dma->paddr)); 7958 IWN_WRITE(sc, IWN_FH_TFBD_CTRL1(IWN_SRVC_DMACHNL), 7959 IWN_HIADDR(dma->paddr) << 28 | size); 7960 IWN_WRITE(sc, IWN_FH_TXBUF_STATUS(IWN_SRVC_DMACHNL), 7961 IWN_FH_TXBUF_STATUS_TBNUM(1) | 7962 IWN_FH_TXBUF_STATUS_TBIDX(1) | 7963 IWN_FH_TXBUF_STATUS_TFBD_VALID); 7964 7965 /* Kick Flow Handler to start DMA transfer. */ 7966 IWN_WRITE(sc, IWN_FH_TX_CONFIG(IWN_SRVC_DMACHNL), 7967 IWN_FH_TX_CONFIG_DMA_ENA | IWN_FH_TX_CONFIG_CIRQ_HOST_ENDTFD); 7968 7969 iwn_nic_unlock(sc); 7970 7971 /* Wait at most five seconds for FH DMA transfer to complete. */ 7972 return msleep(sc, &sc->sc_mtx, PCATCH, "iwninit", 5 * hz); 7973 } 7974 7975 static int 7976 iwn5000_load_firmware(struct iwn_softc *sc) 7977 { 7978 struct iwn_fw_part *fw; 7979 int error; 7980 7981 DPRINTF(sc, IWN_DEBUG_TRACE, "->Doing %s\n", __func__); 7982 7983 /* Load the initialization firmware on first boot only. */ 7984 fw = (sc->sc_flags & IWN_FLAG_CALIB_DONE) ? 7985 &sc->fw.main : &sc->fw.init; 7986 7987 error = iwn5000_load_firmware_section(sc, IWN_FW_TEXT_BASE, 7988 fw->text, fw->textsz); 7989 if (error != 0) { 7990 device_printf(sc->sc_dev, 7991 "%s: could not load firmware %s section, error %d\n", 7992 __func__, ".text", error); 7993 return error; 7994 } 7995 error = iwn5000_load_firmware_section(sc, IWN_FW_DATA_BASE, 7996 fw->data, fw->datasz); 7997 if (error != 0) { 7998 device_printf(sc->sc_dev, 7999 "%s: could not load firmware %s section, error %d\n", 8000 __func__, ".data", error); 8001 return error; 8002 } 8003 8004 /* Now press "execute". */ 8005 IWN_WRITE(sc, IWN_RESET, 0); 8006 return 0; 8007 } 8008 8009 /* 8010 * Extract text and data sections from a legacy firmware image. 8011 */ 8012 static int 8013 iwn_read_firmware_leg(struct iwn_softc *sc, struct iwn_fw_info *fw) 8014 { 8015 const uint32_t *ptr; 8016 size_t hdrlen = 24; 8017 uint32_t rev; 8018 8019 ptr = (const uint32_t *)fw->data; 8020 rev = le32toh(*ptr++); 8021 8022 sc->ucode_rev = rev; 8023 8024 /* Check firmware API version. */ 8025 if (IWN_FW_API(rev) <= 1) { 8026 device_printf(sc->sc_dev, 8027 "%s: bad firmware, need API version >=2\n", __func__); 8028 return EINVAL; 8029 } 8030 if (IWN_FW_API(rev) >= 3) { 8031 /* Skip build number (version 2 header). */ 8032 hdrlen += 4; 8033 ptr++; 8034 } 8035 if (fw->size < hdrlen) { 8036 device_printf(sc->sc_dev, "%s: firmware too short: %zu bytes\n", 8037 __func__, fw->size); 8038 return EINVAL; 8039 } 8040 fw->main.textsz = le32toh(*ptr++); 8041 fw->main.datasz = le32toh(*ptr++); 8042 fw->init.textsz = le32toh(*ptr++); 8043 fw->init.datasz = le32toh(*ptr++); 8044 fw->boot.textsz = le32toh(*ptr++); 8045 8046 /* Check that all firmware sections fit. */ 8047 if (fw->size < hdrlen + fw->main.textsz + fw->main.datasz + 8048 fw->init.textsz + fw->init.datasz + fw->boot.textsz) { 8049 device_printf(sc->sc_dev, "%s: firmware too short: %zu bytes\n", 8050 __func__, fw->size); 8051 return EINVAL; 8052 } 8053 8054 /* Get pointers to firmware sections. */ 8055 fw->main.text = (const uint8_t *)ptr; 8056 fw->main.data = fw->main.text + fw->main.textsz; 8057 fw->init.text = fw->main.data + fw->main.datasz; 8058 fw->init.data = fw->init.text + fw->init.textsz; 8059 fw->boot.text = fw->init.data + fw->init.datasz; 8060 return 0; 8061 } 8062 8063 /* 8064 * Extract text and data sections from a TLV firmware image. 8065 */ 8066 static int 8067 iwn_read_firmware_tlv(struct iwn_softc *sc, struct iwn_fw_info *fw, 8068 uint16_t alt) 8069 { 8070 const struct iwn_fw_tlv_hdr *hdr; 8071 const struct iwn_fw_tlv *tlv; 8072 const uint8_t *ptr, *end; 8073 uint64_t altmask; 8074 uint32_t len, tmp; 8075 8076 if (fw->size < sizeof (*hdr)) { 8077 device_printf(sc->sc_dev, "%s: firmware too short: %zu bytes\n", 8078 __func__, fw->size); 8079 return EINVAL; 8080 } 8081 hdr = (const struct iwn_fw_tlv_hdr *)fw->data; 8082 if (hdr->signature != htole32(IWN_FW_SIGNATURE)) { 8083 device_printf(sc->sc_dev, "%s: bad firmware signature 0x%08x\n", 8084 __func__, le32toh(hdr->signature)); 8085 return EINVAL; 8086 } 8087 DPRINTF(sc, IWN_DEBUG_RESET, "FW: \"%.64s\", build 0x%x\n", hdr->descr, 8088 le32toh(hdr->build)); 8089 sc->ucode_rev = le32toh(hdr->rev); 8090 8091 /* 8092 * Select the closest supported alternative that is less than 8093 * or equal to the specified one. 8094 */ 8095 altmask = le64toh(hdr->altmask); 8096 while (alt > 0 && !(altmask & (1ULL << alt))) 8097 alt--; /* Downgrade. */ 8098 DPRINTF(sc, IWN_DEBUG_RESET, "using alternative %d\n", alt); 8099 8100 ptr = (const uint8_t *)(hdr + 1); 8101 end = (const uint8_t *)(fw->data + fw->size); 8102 8103 /* Parse type-length-value fields. */ 8104 while (ptr + sizeof (*tlv) <= end) { 8105 tlv = (const struct iwn_fw_tlv *)ptr; 8106 len = le32toh(tlv->len); 8107 8108 ptr += sizeof (*tlv); 8109 if (ptr + len > end) { 8110 device_printf(sc->sc_dev, 8111 "%s: firmware too short: %zu bytes\n", __func__, 8112 fw->size); 8113 return EINVAL; 8114 } 8115 /* Skip other alternatives. */ 8116 if (tlv->alt != 0 && tlv->alt != htole16(alt)) 8117 goto next; 8118 8119 switch (le16toh(tlv->type)) { 8120 case IWN_FW_TLV_MAIN_TEXT: 8121 fw->main.text = ptr; 8122 fw->main.textsz = len; 8123 break; 8124 case IWN_FW_TLV_MAIN_DATA: 8125 fw->main.data = ptr; 8126 fw->main.datasz = len; 8127 break; 8128 case IWN_FW_TLV_INIT_TEXT: 8129 fw->init.text = ptr; 8130 fw->init.textsz = len; 8131 break; 8132 case IWN_FW_TLV_INIT_DATA: 8133 fw->init.data = ptr; 8134 fw->init.datasz = len; 8135 break; 8136 case IWN_FW_TLV_BOOT_TEXT: 8137 fw->boot.text = ptr; 8138 fw->boot.textsz = len; 8139 break; 8140 case IWN_FW_TLV_ENH_SENS: 8141 if (!len) 8142 sc->sc_flags |= IWN_FLAG_ENH_SENS; 8143 break; 8144 case IWN_FW_TLV_PHY_CALIB: 8145 tmp = le32toh(*ptr); 8146 if (tmp < 253) { 8147 sc->reset_noise_gain = tmp; 8148 sc->noise_gain = tmp + 1; 8149 } 8150 break; 8151 case IWN_FW_TLV_PAN: 8152 sc->sc_flags |= IWN_FLAG_PAN_SUPPORT; 8153 DPRINTF(sc, IWN_DEBUG_RESET, 8154 "PAN Support found: %d\n", 1); 8155 break; 8156 case IWN_FW_TLV_FLAGS: 8157 if (len < sizeof(uint32_t)) 8158 break; 8159 if (len % sizeof(uint32_t)) 8160 break; 8161 sc->tlv_feature_flags = le32toh(*ptr); 8162 DPRINTF(sc, IWN_DEBUG_RESET, 8163 "%s: feature: 0x%08x\n", 8164 __func__, 8165 sc->tlv_feature_flags); 8166 break; 8167 case IWN_FW_TLV_PBREQ_MAXLEN: 8168 case IWN_FW_TLV_RUNT_EVTLOG_PTR: 8169 case IWN_FW_TLV_RUNT_EVTLOG_SIZE: 8170 case IWN_FW_TLV_RUNT_ERRLOG_PTR: 8171 case IWN_FW_TLV_INIT_EVTLOG_PTR: 8172 case IWN_FW_TLV_INIT_EVTLOG_SIZE: 8173 case IWN_FW_TLV_INIT_ERRLOG_PTR: 8174 case IWN_FW_TLV_WOWLAN_INST: 8175 case IWN_FW_TLV_WOWLAN_DATA: 8176 DPRINTF(sc, IWN_DEBUG_RESET, 8177 "TLV type %d recognized but not handled\n", 8178 le16toh(tlv->type)); 8179 break; 8180 default: 8181 DPRINTF(sc, IWN_DEBUG_RESET, 8182 "TLV type %d not handled\n", le16toh(tlv->type)); 8183 break; 8184 } 8185 next: /* TLV fields are 32-bit aligned. */ 8186 ptr += (len + 3) & ~3; 8187 } 8188 return 0; 8189 } 8190 8191 static int 8192 iwn_read_firmware(struct iwn_softc *sc) 8193 { 8194 struct iwn_fw_info *fw = &sc->fw; 8195 int error; 8196 8197 DPRINTF(sc, IWN_DEBUG_TRACE, "->Doing %s\n", __func__); 8198 8199 IWN_UNLOCK(sc); 8200 8201 memset(fw, 0, sizeof (*fw)); 8202 8203 /* Read firmware image from filesystem. */ 8204 sc->fw_fp = firmware_get(sc->fwname); 8205 if (sc->fw_fp == NULL) { 8206 device_printf(sc->sc_dev, "%s: could not read firmware %s\n", 8207 __func__, sc->fwname); 8208 IWN_LOCK(sc); 8209 return EINVAL; 8210 } 8211 IWN_LOCK(sc); 8212 8213 fw->size = sc->fw_fp->datasize; 8214 fw->data = (const uint8_t *)sc->fw_fp->data; 8215 if (fw->size < sizeof (uint32_t)) { 8216 device_printf(sc->sc_dev, "%s: firmware too short: %zu bytes\n", 8217 __func__, fw->size); 8218 firmware_put(sc->fw_fp, FIRMWARE_UNLOAD); 8219 sc->fw_fp = NULL; 8220 return EINVAL; 8221 } 8222 8223 /* Retrieve text and data sections. */ 8224 if (*(const uint32_t *)fw->data != 0) /* Legacy image. */ 8225 error = iwn_read_firmware_leg(sc, fw); 8226 else 8227 error = iwn_read_firmware_tlv(sc, fw, 1); 8228 if (error != 0) { 8229 device_printf(sc->sc_dev, 8230 "%s: could not read firmware sections, error %d\n", 8231 __func__, error); 8232 firmware_put(sc->fw_fp, FIRMWARE_UNLOAD); 8233 sc->fw_fp = NULL; 8234 return error; 8235 } 8236 8237 device_printf(sc->sc_dev, "%s: ucode rev=0x%08x\n", __func__, sc->ucode_rev); 8238 8239 /* Make sure text and data sections fit in hardware memory. */ 8240 if (fw->main.textsz > sc->fw_text_maxsz || 8241 fw->main.datasz > sc->fw_data_maxsz || 8242 fw->init.textsz > sc->fw_text_maxsz || 8243 fw->init.datasz > sc->fw_data_maxsz || 8244 fw->boot.textsz > IWN_FW_BOOT_TEXT_MAXSZ || 8245 (fw->boot.textsz & 3) != 0) { 8246 device_printf(sc->sc_dev, "%s: firmware sections too large\n", 8247 __func__); 8248 firmware_put(sc->fw_fp, FIRMWARE_UNLOAD); 8249 sc->fw_fp = NULL; 8250 return EINVAL; 8251 } 8252 8253 /* We can proceed with loading the firmware. */ 8254 return 0; 8255 } 8256 8257 static int 8258 iwn_clock_wait(struct iwn_softc *sc) 8259 { 8260 int ntries; 8261 8262 /* Set "initialization complete" bit. */ 8263 IWN_SETBITS(sc, IWN_GP_CNTRL, IWN_GP_CNTRL_INIT_DONE); 8264 8265 /* Wait for clock stabilization. */ 8266 for (ntries = 0; ntries < 2500; ntries++) { 8267 if (IWN_READ(sc, IWN_GP_CNTRL) & IWN_GP_CNTRL_MAC_CLOCK_READY) 8268 return 0; 8269 DELAY(10); 8270 } 8271 device_printf(sc->sc_dev, 8272 "%s: timeout waiting for clock stabilization\n", __func__); 8273 return ETIMEDOUT; 8274 } 8275 8276 static int 8277 iwn_apm_init(struct iwn_softc *sc) 8278 { 8279 uint32_t reg; 8280 int error; 8281 8282 DPRINTF(sc, IWN_DEBUG_TRACE, "->Doing %s\n", __func__); 8283 8284 /* Disable L0s exit timer (NMI bug workaround). */ 8285 IWN_SETBITS(sc, IWN_GIO_CHICKEN, IWN_GIO_CHICKEN_DIS_L0S_TIMER); 8286 /* Don't wait for ICH L0s (ICH bug workaround). */ 8287 IWN_SETBITS(sc, IWN_GIO_CHICKEN, IWN_GIO_CHICKEN_L1A_NO_L0S_RX); 8288 8289 /* Set FH wait threshold to max (HW bug under stress workaround). */ 8290 IWN_SETBITS(sc, IWN_DBG_HPET_MEM, 0xffff0000); 8291 8292 /* Enable HAP INTA to move adapter from L1a to L0s. */ 8293 IWN_SETBITS(sc, IWN_HW_IF_CONFIG, IWN_HW_IF_CONFIG_HAP_WAKE_L1A); 8294 8295 /* Retrieve PCIe Active State Power Management (ASPM). */ 8296 reg = pci_read_config(sc->sc_dev, sc->sc_cap_off + 0x10, 1); 8297 /* Workaround for HW instability in PCIe L0->L0s->L1 transition. */ 8298 if (reg & 0x02) /* L1 Entry enabled. */ 8299 IWN_SETBITS(sc, IWN_GIO, IWN_GIO_L0S_ENA); 8300 else 8301 IWN_CLRBITS(sc, IWN_GIO, IWN_GIO_L0S_ENA); 8302 8303 if (sc->base_params->pll_cfg_val) 8304 IWN_SETBITS(sc, IWN_ANA_PLL, sc->base_params->pll_cfg_val); 8305 8306 /* Wait for clock stabilization before accessing prph. */ 8307 if ((error = iwn_clock_wait(sc)) != 0) 8308 return error; 8309 8310 if ((error = iwn_nic_lock(sc)) != 0) 8311 return error; 8312 if (sc->hw_type == IWN_HW_REV_TYPE_4965) { 8313 /* Enable DMA and BSM (Bootstrap State Machine). */ 8314 iwn_prph_write(sc, IWN_APMG_CLK_EN, 8315 IWN_APMG_CLK_CTRL_DMA_CLK_RQT | 8316 IWN_APMG_CLK_CTRL_BSM_CLK_RQT); 8317 } else { 8318 /* Enable DMA. */ 8319 iwn_prph_write(sc, IWN_APMG_CLK_EN, 8320 IWN_APMG_CLK_CTRL_DMA_CLK_RQT); 8321 } 8322 DELAY(20); 8323 /* Disable L1-Active. */ 8324 iwn_prph_setbits(sc, IWN_APMG_PCI_STT, IWN_APMG_PCI_STT_L1A_DIS); 8325 iwn_nic_unlock(sc); 8326 8327 return 0; 8328 } 8329 8330 static void 8331 iwn_apm_stop_master(struct iwn_softc *sc) 8332 { 8333 int ntries; 8334 8335 /* Stop busmaster DMA activity. */ 8336 IWN_SETBITS(sc, IWN_RESET, IWN_RESET_STOP_MASTER); 8337 for (ntries = 0; ntries < 100; ntries++) { 8338 if (IWN_READ(sc, IWN_RESET) & IWN_RESET_MASTER_DISABLED) 8339 return; 8340 DELAY(10); 8341 } 8342 device_printf(sc->sc_dev, "%s: timeout waiting for master\n", __func__); 8343 } 8344 8345 static void 8346 iwn_apm_stop(struct iwn_softc *sc) 8347 { 8348 iwn_apm_stop_master(sc); 8349 8350 /* Reset the entire device. */ 8351 IWN_SETBITS(sc, IWN_RESET, IWN_RESET_SW); 8352 DELAY(10); 8353 /* Clear "initialization complete" bit. */ 8354 IWN_CLRBITS(sc, IWN_GP_CNTRL, IWN_GP_CNTRL_INIT_DONE); 8355 } 8356 8357 static int 8358 iwn4965_nic_config(struct iwn_softc *sc) 8359 { 8360 DPRINTF(sc, IWN_DEBUG_TRACE, "->Doing %s\n", __func__); 8361 8362 if (IWN_RFCFG_TYPE(sc->rfcfg) == 1) { 8363 /* 8364 * I don't believe this to be correct but this is what the 8365 * vendor driver is doing. Probably the bits should not be 8366 * shifted in IWN_RFCFG_*. 8367 */ 8368 IWN_SETBITS(sc, IWN_HW_IF_CONFIG, 8369 IWN_RFCFG_TYPE(sc->rfcfg) | 8370 IWN_RFCFG_STEP(sc->rfcfg) | 8371 IWN_RFCFG_DASH(sc->rfcfg)); 8372 } 8373 IWN_SETBITS(sc, IWN_HW_IF_CONFIG, 8374 IWN_HW_IF_CONFIG_RADIO_SI | IWN_HW_IF_CONFIG_MAC_SI); 8375 return 0; 8376 } 8377 8378 static int 8379 iwn5000_nic_config(struct iwn_softc *sc) 8380 { 8381 uint32_t tmp; 8382 int error; 8383 8384 DPRINTF(sc, IWN_DEBUG_TRACE, "->Doing %s\n", __func__); 8385 8386 if (IWN_RFCFG_TYPE(sc->rfcfg) < 3) { 8387 IWN_SETBITS(sc, IWN_HW_IF_CONFIG, 8388 IWN_RFCFG_TYPE(sc->rfcfg) | 8389 IWN_RFCFG_STEP(sc->rfcfg) | 8390 IWN_RFCFG_DASH(sc->rfcfg)); 8391 } 8392 IWN_SETBITS(sc, IWN_HW_IF_CONFIG, 8393 IWN_HW_IF_CONFIG_RADIO_SI | IWN_HW_IF_CONFIG_MAC_SI); 8394 8395 if ((error = iwn_nic_lock(sc)) != 0) 8396 return error; 8397 iwn_prph_setbits(sc, IWN_APMG_PS, IWN_APMG_PS_EARLY_PWROFF_DIS); 8398 8399 if (sc->hw_type == IWN_HW_REV_TYPE_1000) { 8400 /* 8401 * Select first Switching Voltage Regulator (1.32V) to 8402 * solve a stability issue related to noisy DC2DC line 8403 * in the silicon of 1000 Series. 8404 */ 8405 tmp = iwn_prph_read(sc, IWN_APMG_DIGITAL_SVR); 8406 tmp &= ~IWN_APMG_DIGITAL_SVR_VOLTAGE_MASK; 8407 tmp |= IWN_APMG_DIGITAL_SVR_VOLTAGE_1_32; 8408 iwn_prph_write(sc, IWN_APMG_DIGITAL_SVR, tmp); 8409 } 8410 iwn_nic_unlock(sc); 8411 8412 if (sc->sc_flags & IWN_FLAG_INTERNAL_PA) { 8413 /* Use internal power amplifier only. */ 8414 IWN_WRITE(sc, IWN_GP_DRIVER, IWN_GP_DRIVER_RADIO_2X2_IPA); 8415 } 8416 if (sc->base_params->additional_nic_config && sc->calib_ver >= 6) { 8417 /* Indicate that ROM calibration version is >=6. */ 8418 IWN_SETBITS(sc, IWN_GP_DRIVER, IWN_GP_DRIVER_CALIB_VER6); 8419 } 8420 if (sc->base_params->additional_gp_drv_bit) 8421 IWN_SETBITS(sc, IWN_GP_DRIVER, 8422 sc->base_params->additional_gp_drv_bit); 8423 return 0; 8424 } 8425 8426 /* 8427 * Take NIC ownership over Intel Active Management Technology (AMT). 8428 */ 8429 static int 8430 iwn_hw_prepare(struct iwn_softc *sc) 8431 { 8432 int ntries; 8433 8434 DPRINTF(sc, IWN_DEBUG_TRACE, "->Doing %s\n", __func__); 8435 8436 /* Check if hardware is ready. */ 8437 IWN_SETBITS(sc, IWN_HW_IF_CONFIG, IWN_HW_IF_CONFIG_NIC_READY); 8438 for (ntries = 0; ntries < 5; ntries++) { 8439 if (IWN_READ(sc, IWN_HW_IF_CONFIG) & 8440 IWN_HW_IF_CONFIG_NIC_READY) 8441 return 0; 8442 DELAY(10); 8443 } 8444 8445 /* Hardware not ready, force into ready state. */ 8446 IWN_SETBITS(sc, IWN_HW_IF_CONFIG, IWN_HW_IF_CONFIG_PREPARE); 8447 for (ntries = 0; ntries < 15000; ntries++) { 8448 if (!(IWN_READ(sc, IWN_HW_IF_CONFIG) & 8449 IWN_HW_IF_CONFIG_PREPARE_DONE)) 8450 break; 8451 DELAY(10); 8452 } 8453 if (ntries == 15000) 8454 return ETIMEDOUT; 8455 8456 /* Hardware should be ready now. */ 8457 IWN_SETBITS(sc, IWN_HW_IF_CONFIG, IWN_HW_IF_CONFIG_NIC_READY); 8458 for (ntries = 0; ntries < 5; ntries++) { 8459 if (IWN_READ(sc, IWN_HW_IF_CONFIG) & 8460 IWN_HW_IF_CONFIG_NIC_READY) 8461 return 0; 8462 DELAY(10); 8463 } 8464 return ETIMEDOUT; 8465 } 8466 8467 static int 8468 iwn_hw_init(struct iwn_softc *sc) 8469 { 8470 struct iwn_ops *ops = &sc->ops; 8471 int error, chnl, qid; 8472 8473 DPRINTF(sc, IWN_DEBUG_TRACE, "->%s begin\n", __func__); 8474 8475 /* Clear pending interrupts. */ 8476 IWN_WRITE(sc, IWN_INT, 0xffffffff); 8477 8478 if ((error = iwn_apm_init(sc)) != 0) { 8479 device_printf(sc->sc_dev, 8480 "%s: could not power ON adapter, error %d\n", __func__, 8481 error); 8482 return error; 8483 } 8484 8485 /* Select VMAIN power source. */ 8486 if ((error = iwn_nic_lock(sc)) != 0) 8487 return error; 8488 iwn_prph_clrbits(sc, IWN_APMG_PS, IWN_APMG_PS_PWR_SRC_MASK); 8489 iwn_nic_unlock(sc); 8490 8491 /* Perform adapter-specific initialization. */ 8492 if ((error = ops->nic_config(sc)) != 0) 8493 return error; 8494 8495 /* Initialize RX ring. */ 8496 if ((error = iwn_nic_lock(sc)) != 0) 8497 return error; 8498 IWN_WRITE(sc, IWN_FH_RX_CONFIG, 0); 8499 IWN_WRITE(sc, IWN_FH_RX_WPTR, 0); 8500 /* Set physical address of RX ring (256-byte aligned). */ 8501 IWN_WRITE(sc, IWN_FH_RX_BASE, sc->rxq.desc_dma.paddr >> 8); 8502 /* Set physical address of RX status (16-byte aligned). */ 8503 IWN_WRITE(sc, IWN_FH_STATUS_WPTR, sc->rxq.stat_dma.paddr >> 4); 8504 /* Enable RX. */ 8505 IWN_WRITE(sc, IWN_FH_RX_CONFIG, 8506 IWN_FH_RX_CONFIG_ENA | 8507 IWN_FH_RX_CONFIG_IGN_RXF_EMPTY | /* HW bug workaround */ 8508 IWN_FH_RX_CONFIG_IRQ_DST_HOST | 8509 IWN_FH_RX_CONFIG_SINGLE_FRAME | 8510 IWN_FH_RX_CONFIG_RB_TIMEOUT(0) | 8511 IWN_FH_RX_CONFIG_NRBD(IWN_RX_RING_COUNT_LOG)); 8512 iwn_nic_unlock(sc); 8513 IWN_WRITE(sc, IWN_FH_RX_WPTR, (IWN_RX_RING_COUNT - 1) & ~7); 8514 8515 if ((error = iwn_nic_lock(sc)) != 0) 8516 return error; 8517 8518 /* Initialize TX scheduler. */ 8519 iwn_prph_write(sc, sc->sched_txfact_addr, 0); 8520 8521 /* Set physical address of "keep warm" page (16-byte aligned). */ 8522 IWN_WRITE(sc, IWN_FH_KW_ADDR, sc->kw_dma.paddr >> 4); 8523 8524 /* Initialize TX rings. */ 8525 for (qid = 0; qid < sc->ntxqs; qid++) { 8526 struct iwn_tx_ring *txq = &sc->txq[qid]; 8527 8528 /* Set physical address of TX ring (256-byte aligned). */ 8529 IWN_WRITE(sc, IWN_FH_CBBC_QUEUE(qid), 8530 txq->desc_dma.paddr >> 8); 8531 } 8532 iwn_nic_unlock(sc); 8533 8534 /* Enable DMA channels. */ 8535 for (chnl = 0; chnl < sc->ndmachnls; chnl++) { 8536 IWN_WRITE(sc, IWN_FH_TX_CONFIG(chnl), 8537 IWN_FH_TX_CONFIG_DMA_ENA | 8538 IWN_FH_TX_CONFIG_DMA_CREDIT_ENA); 8539 } 8540 8541 /* Clear "radio off" and "commands blocked" bits. */ 8542 IWN_WRITE(sc, IWN_UCODE_GP1_CLR, IWN_UCODE_GP1_RFKILL); 8543 IWN_WRITE(sc, IWN_UCODE_GP1_CLR, IWN_UCODE_GP1_CMD_BLOCKED); 8544 8545 /* Clear pending interrupts. */ 8546 IWN_WRITE(sc, IWN_INT, 0xffffffff); 8547 /* Enable interrupt coalescing. */ 8548 IWN_WRITE(sc, IWN_INT_COALESCING, 512 / 8); 8549 /* Enable interrupts. */ 8550 IWN_WRITE(sc, IWN_INT_MASK, sc->int_mask); 8551 8552 /* _Really_ make sure "radio off" bit is cleared! */ 8553 IWN_WRITE(sc, IWN_UCODE_GP1_CLR, IWN_UCODE_GP1_RFKILL); 8554 IWN_WRITE(sc, IWN_UCODE_GP1_CLR, IWN_UCODE_GP1_RFKILL); 8555 8556 /* Enable shadow registers. */ 8557 if (sc->base_params->shadow_reg_enable) 8558 IWN_SETBITS(sc, IWN_SHADOW_REG_CTRL, 0x800fffff); 8559 8560 if ((error = ops->load_firmware(sc)) != 0) { 8561 device_printf(sc->sc_dev, 8562 "%s: could not load firmware, error %d\n", __func__, 8563 error); 8564 return error; 8565 } 8566 /* Wait at most one second for firmware alive notification. */ 8567 if ((error = msleep(sc, &sc->sc_mtx, PCATCH, "iwninit", hz)) != 0) { 8568 device_printf(sc->sc_dev, 8569 "%s: timeout waiting for adapter to initialize, error %d\n", 8570 __func__, error); 8571 return error; 8572 } 8573 /* Do post-firmware initialization. */ 8574 8575 DPRINTF(sc, IWN_DEBUG_TRACE, "->%s: end\n",__func__); 8576 8577 return ops->post_alive(sc); 8578 } 8579 8580 static void 8581 iwn_hw_stop(struct iwn_softc *sc) 8582 { 8583 int chnl, qid, ntries; 8584 8585 DPRINTF(sc, IWN_DEBUG_TRACE, "->Doing %s\n", __func__); 8586 8587 IWN_WRITE(sc, IWN_RESET, IWN_RESET_NEVO); 8588 8589 /* Disable interrupts. */ 8590 IWN_WRITE(sc, IWN_INT_MASK, 0); 8591 IWN_WRITE(sc, IWN_INT, 0xffffffff); 8592 IWN_WRITE(sc, IWN_FH_INT, 0xffffffff); 8593 sc->sc_flags &= ~IWN_FLAG_USE_ICT; 8594 8595 /* Make sure we no longer hold the NIC lock. */ 8596 iwn_nic_unlock(sc); 8597 8598 /* Stop TX scheduler. */ 8599 iwn_prph_write(sc, sc->sched_txfact_addr, 0); 8600 8601 /* Stop all DMA channels. */ 8602 if (iwn_nic_lock(sc) == 0) { 8603 for (chnl = 0; chnl < sc->ndmachnls; chnl++) { 8604 IWN_WRITE(sc, IWN_FH_TX_CONFIG(chnl), 0); 8605 for (ntries = 0; ntries < 200; ntries++) { 8606 if (IWN_READ(sc, IWN_FH_TX_STATUS) & 8607 IWN_FH_TX_STATUS_IDLE(chnl)) 8608 break; 8609 DELAY(10); 8610 } 8611 } 8612 iwn_nic_unlock(sc); 8613 } 8614 8615 /* Stop RX ring. */ 8616 iwn_reset_rx_ring(sc, &sc->rxq); 8617 8618 /* Reset all TX rings. */ 8619 for (qid = 0; qid < sc->ntxqs; qid++) 8620 iwn_reset_tx_ring(sc, &sc->txq[qid]); 8621 8622 if (iwn_nic_lock(sc) == 0) { 8623 iwn_prph_write(sc, IWN_APMG_CLK_DIS, 8624 IWN_APMG_CLK_CTRL_DMA_CLK_RQT); 8625 iwn_nic_unlock(sc); 8626 } 8627 DELAY(5); 8628 /* Power OFF adapter. */ 8629 iwn_apm_stop(sc); 8630 } 8631 8632 static void 8633 iwn_radio_on(void *arg0, int pending) 8634 { 8635 struct iwn_softc *sc = arg0; 8636 struct ieee80211com *ic = &sc->sc_ic; 8637 struct ieee80211vap *vap = TAILQ_FIRST(&ic->ic_vaps); 8638 8639 DPRINTF(sc, IWN_DEBUG_TRACE, "->Doing %s\n", __func__); 8640 8641 if (vap != NULL) { 8642 iwn_init(sc); 8643 ieee80211_init(vap); 8644 } 8645 } 8646 8647 static void 8648 iwn_radio_off(void *arg0, int pending) 8649 { 8650 struct iwn_softc *sc = arg0; 8651 struct ieee80211com *ic = &sc->sc_ic; 8652 struct ieee80211vap *vap = TAILQ_FIRST(&ic->ic_vaps); 8653 8654 DPRINTF(sc, IWN_DEBUG_TRACE, "->Doing %s\n", __func__); 8655 8656 iwn_stop(sc); 8657 if (vap != NULL) 8658 ieee80211_stop(vap); 8659 8660 /* Enable interrupts to get RF toggle notification. */ 8661 IWN_LOCK(sc); 8662 IWN_WRITE(sc, IWN_INT, 0xffffffff); 8663 IWN_WRITE(sc, IWN_INT_MASK, sc->int_mask); 8664 IWN_UNLOCK(sc); 8665 } 8666 8667 static void 8668 iwn_panicked(void *arg0, int pending) 8669 { 8670 struct iwn_softc *sc = arg0; 8671 struct ieee80211com *ic = &sc->sc_ic; 8672 struct ieee80211vap *vap = TAILQ_FIRST(&ic->ic_vaps); 8673 int error; 8674 8675 if (vap == NULL) { 8676 printf("%s: null vap\n", __func__); 8677 return; 8678 } 8679 8680 device_printf(sc->sc_dev, "%s: controller panicked, iv_state = %d; " 8681 "resetting...\n", __func__, vap->iv_state); 8682 8683 IWN_LOCK(sc); 8684 8685 iwn_stop_locked(sc); 8686 iwn_init_locked(sc); 8687 if (vap->iv_state >= IEEE80211_S_AUTH && 8688 (error = iwn_auth(sc, vap)) != 0) { 8689 device_printf(sc->sc_dev, 8690 "%s: could not move to auth state\n", __func__); 8691 } 8692 if (vap->iv_state >= IEEE80211_S_RUN && 8693 (error = iwn_run(sc, vap)) != 0) { 8694 device_printf(sc->sc_dev, 8695 "%s: could not move to run state\n", __func__); 8696 } 8697 8698 IWN_UNLOCK(sc); 8699 } 8700 8701 static void 8702 iwn_init_locked(struct iwn_softc *sc) 8703 { 8704 int error; 8705 8706 DPRINTF(sc, IWN_DEBUG_TRACE, "->%s begin\n", __func__); 8707 8708 IWN_LOCK_ASSERT(sc); 8709 8710 sc->sc_flags |= IWN_FLAG_RUNNING; 8711 8712 if ((error = iwn_hw_prepare(sc)) != 0) { 8713 device_printf(sc->sc_dev, "%s: hardware not ready, error %d\n", 8714 __func__, error); 8715 goto fail; 8716 } 8717 8718 /* Initialize interrupt mask to default value. */ 8719 sc->int_mask = IWN_INT_MASK_DEF; 8720 sc->sc_flags &= ~IWN_FLAG_USE_ICT; 8721 8722 /* Check that the radio is not disabled by hardware switch. */ 8723 if (!(IWN_READ(sc, IWN_GP_CNTRL) & IWN_GP_CNTRL_RFKILL)) { 8724 device_printf(sc->sc_dev, 8725 "radio is disabled by hardware switch\n"); 8726 /* Enable interrupts to get RF toggle notifications. */ 8727 IWN_WRITE(sc, IWN_INT, 0xffffffff); 8728 IWN_WRITE(sc, IWN_INT_MASK, sc->int_mask); 8729 return; 8730 } 8731 8732 /* Read firmware images from the filesystem. */ 8733 if ((error = iwn_read_firmware(sc)) != 0) { 8734 device_printf(sc->sc_dev, 8735 "%s: could not read firmware, error %d\n", __func__, 8736 error); 8737 goto fail; 8738 } 8739 8740 /* Initialize hardware and upload firmware. */ 8741 error = iwn_hw_init(sc); 8742 firmware_put(sc->fw_fp, FIRMWARE_UNLOAD); 8743 sc->fw_fp = NULL; 8744 if (error != 0) { 8745 device_printf(sc->sc_dev, 8746 "%s: could not initialize hardware, error %d\n", __func__, 8747 error); 8748 goto fail; 8749 } 8750 8751 /* Configure adapter now that it is ready. */ 8752 if ((error = iwn_config(sc)) != 0) { 8753 device_printf(sc->sc_dev, 8754 "%s: could not configure device, error %d\n", __func__, 8755 error); 8756 goto fail; 8757 } 8758 8759 callout_reset(&sc->watchdog_to, hz, iwn_watchdog, sc); 8760 8761 DPRINTF(sc, IWN_DEBUG_TRACE, "->%s: end\n",__func__); 8762 8763 return; 8764 8765 fail: 8766 sc->sc_flags &= ~IWN_FLAG_RUNNING; 8767 iwn_stop_locked(sc); 8768 DPRINTF(sc, IWN_DEBUG_TRACE, "->%s: end in error\n",__func__); 8769 } 8770 8771 static void 8772 iwn_init(struct iwn_softc *sc) 8773 { 8774 8775 IWN_LOCK(sc); 8776 iwn_init_locked(sc); 8777 IWN_UNLOCK(sc); 8778 8779 if (sc->sc_flags & IWN_FLAG_RUNNING) 8780 ieee80211_start_all(&sc->sc_ic); 8781 } 8782 8783 static void 8784 iwn_stop_locked(struct iwn_softc *sc) 8785 { 8786 8787 IWN_LOCK_ASSERT(sc); 8788 8789 sc->sc_is_scanning = 0; 8790 sc->sc_tx_timer = 0; 8791 callout_stop(&sc->watchdog_to); 8792 callout_stop(&sc->calib_to); 8793 sc->sc_flags &= ~IWN_FLAG_RUNNING; 8794 8795 /* Power OFF hardware. */ 8796 iwn_hw_stop(sc); 8797 } 8798 8799 static void 8800 iwn_stop(struct iwn_softc *sc) 8801 { 8802 IWN_LOCK(sc); 8803 iwn_stop_locked(sc); 8804 IWN_UNLOCK(sc); 8805 } 8806 8807 /* 8808 * Callback from net80211 to start a scan. 8809 */ 8810 static void 8811 iwn_scan_start(struct ieee80211com *ic) 8812 { 8813 struct iwn_softc *sc = ic->ic_softc; 8814 8815 IWN_LOCK(sc); 8816 /* make the link LED blink while we're scanning */ 8817 iwn_set_led(sc, IWN_LED_LINK, 20, 2); 8818 IWN_UNLOCK(sc); 8819 } 8820 8821 /* 8822 * Callback from net80211 to terminate a scan. 8823 */ 8824 static void 8825 iwn_scan_end(struct ieee80211com *ic) 8826 { 8827 struct iwn_softc *sc = ic->ic_softc; 8828 struct ieee80211vap *vap = TAILQ_FIRST(&ic->ic_vaps); 8829 8830 IWN_LOCK(sc); 8831 if (vap->iv_state == IEEE80211_S_RUN) { 8832 /* Set link LED to ON status if we are associated */ 8833 iwn_set_led(sc, IWN_LED_LINK, 0, 1); 8834 } 8835 IWN_UNLOCK(sc); 8836 } 8837 8838 /* 8839 * Callback from net80211 to force a channel change. 8840 */ 8841 static void 8842 iwn_set_channel(struct ieee80211com *ic) 8843 { 8844 const struct ieee80211_channel *c = ic->ic_curchan; 8845 struct iwn_softc *sc = ic->ic_softc; 8846 int error; 8847 8848 DPRINTF(sc, IWN_DEBUG_TRACE, "->Doing %s\n", __func__); 8849 8850 IWN_LOCK(sc); 8851 sc->sc_rxtap.wr_chan_freq = htole16(c->ic_freq); 8852 sc->sc_rxtap.wr_chan_flags = htole16(c->ic_flags); 8853 sc->sc_txtap.wt_chan_freq = htole16(c->ic_freq); 8854 sc->sc_txtap.wt_chan_flags = htole16(c->ic_flags); 8855 8856 /* 8857 * Only need to set the channel in Monitor mode. AP scanning and auth 8858 * are already taken care of by their respective firmware commands. 8859 */ 8860 if (ic->ic_opmode == IEEE80211_M_MONITOR) { 8861 error = iwn_config(sc); 8862 if (error != 0) 8863 device_printf(sc->sc_dev, 8864 "%s: error %d settting channel\n", __func__, error); 8865 } 8866 IWN_UNLOCK(sc); 8867 } 8868 8869 /* 8870 * Callback from net80211 to start scanning of the current channel. 8871 */ 8872 static void 8873 iwn_scan_curchan(struct ieee80211_scan_state *ss, unsigned long maxdwell) 8874 { 8875 struct ieee80211vap *vap = ss->ss_vap; 8876 struct ieee80211com *ic = vap->iv_ic; 8877 struct iwn_softc *sc = ic->ic_softc; 8878 int error; 8879 8880 IWN_LOCK(sc); 8881 error = iwn_scan(sc, vap, ss, ic->ic_curchan); 8882 IWN_UNLOCK(sc); 8883 if (error != 0) 8884 ieee80211_cancel_scan(vap); 8885 } 8886 8887 /* 8888 * Callback from net80211 to handle the minimum dwell time being met. 8889 * The intent is to terminate the scan but we just let the firmware 8890 * notify us when it's finished as we have no safe way to abort it. 8891 */ 8892 static void 8893 iwn_scan_mindwell(struct ieee80211_scan_state *ss) 8894 { 8895 /* NB: don't try to abort scan; wait for firmware to finish */ 8896 } 8897 8898 static void 8899 iwn_hw_reset(void *arg0, int pending) 8900 { 8901 struct iwn_softc *sc = arg0; 8902 struct ieee80211com *ic = &sc->sc_ic; 8903 8904 DPRINTF(sc, IWN_DEBUG_TRACE, "->Doing %s\n", __func__); 8905 8906 iwn_stop(sc); 8907 iwn_init(sc); 8908 ieee80211_notify_radio(ic, 1); 8909 } 8910 #ifdef IWN_DEBUG 8911 #define IWN_DESC(x) case x: return #x 8912 8913 /* 8914 * Translate CSR code to string 8915 */ 8916 static char *iwn_get_csr_string(int csr) 8917 { 8918 switch (csr) { 8919 IWN_DESC(IWN_HW_IF_CONFIG); 8920 IWN_DESC(IWN_INT_COALESCING); 8921 IWN_DESC(IWN_INT); 8922 IWN_DESC(IWN_INT_MASK); 8923 IWN_DESC(IWN_FH_INT); 8924 IWN_DESC(IWN_GPIO_IN); 8925 IWN_DESC(IWN_RESET); 8926 IWN_DESC(IWN_GP_CNTRL); 8927 IWN_DESC(IWN_HW_REV); 8928 IWN_DESC(IWN_EEPROM); 8929 IWN_DESC(IWN_EEPROM_GP); 8930 IWN_DESC(IWN_OTP_GP); 8931 IWN_DESC(IWN_GIO); 8932 IWN_DESC(IWN_GP_UCODE); 8933 IWN_DESC(IWN_GP_DRIVER); 8934 IWN_DESC(IWN_UCODE_GP1); 8935 IWN_DESC(IWN_UCODE_GP2); 8936 IWN_DESC(IWN_LED); 8937 IWN_DESC(IWN_DRAM_INT_TBL); 8938 IWN_DESC(IWN_GIO_CHICKEN); 8939 IWN_DESC(IWN_ANA_PLL); 8940 IWN_DESC(IWN_HW_REV_WA); 8941 IWN_DESC(IWN_DBG_HPET_MEM); 8942 default: 8943 return "UNKNOWN CSR"; 8944 } 8945 } 8946 8947 /* 8948 * This function print firmware register 8949 */ 8950 static void 8951 iwn_debug_register(struct iwn_softc *sc) 8952 { 8953 int i; 8954 static const uint32_t csr_tbl[] = { 8955 IWN_HW_IF_CONFIG, 8956 IWN_INT_COALESCING, 8957 IWN_INT, 8958 IWN_INT_MASK, 8959 IWN_FH_INT, 8960 IWN_GPIO_IN, 8961 IWN_RESET, 8962 IWN_GP_CNTRL, 8963 IWN_HW_REV, 8964 IWN_EEPROM, 8965 IWN_EEPROM_GP, 8966 IWN_OTP_GP, 8967 IWN_GIO, 8968 IWN_GP_UCODE, 8969 IWN_GP_DRIVER, 8970 IWN_UCODE_GP1, 8971 IWN_UCODE_GP2, 8972 IWN_LED, 8973 IWN_DRAM_INT_TBL, 8974 IWN_GIO_CHICKEN, 8975 IWN_ANA_PLL, 8976 IWN_HW_REV_WA, 8977 IWN_DBG_HPET_MEM, 8978 }; 8979 DPRINTF(sc, IWN_DEBUG_REGISTER, 8980 "CSR values: (2nd byte of IWN_INT_COALESCING is IWN_INT_PERIODIC)%s", 8981 "\n"); 8982 for (i = 0; i < nitems(csr_tbl); i++){ 8983 DPRINTF(sc, IWN_DEBUG_REGISTER," %10s: 0x%08x ", 8984 iwn_get_csr_string(csr_tbl[i]), IWN_READ(sc, csr_tbl[i])); 8985 if ((i+1) % 3 == 0) 8986 DPRINTF(sc, IWN_DEBUG_REGISTER,"%s","\n"); 8987 } 8988 DPRINTF(sc, IWN_DEBUG_REGISTER,"%s","\n"); 8989 } 8990 #endif 8991 8992 8993