1 /*- 2 * Copyright (c) 2007-2009 3 * Damien Bergamini <damien.bergamini@free.fr> 4 * Copyright (c) 2008 5 * Benjamin Close <benjsc@FreeBSD.org> 6 * Copyright (c) 2008 Sam Leffler, Errno Consulting 7 * 8 * Permission to use, copy, modify, and distribute this software for any 9 * purpose with or without fee is hereby granted, provided that the above 10 * copyright notice and this permission notice appear in all copies. 11 * 12 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 13 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 14 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR 15 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 16 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN 17 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF 18 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 19 */ 20 21 /* 22 * Driver for Intel WiFi Link 4965 and 1000/5000/6000 Series 802.11 network 23 * adapters. 24 */ 25 26 #include <sys/cdefs.h> 27 __FBSDID("$FreeBSD$"); 28 29 #include <sys/param.h> 30 #include <sys/sockio.h> 31 #include <sys/sysctl.h> 32 #include <sys/mbuf.h> 33 #include <sys/kernel.h> 34 #include <sys/socket.h> 35 #include <sys/systm.h> 36 #include <sys/malloc.h> 37 #include <sys/bus.h> 38 #include <sys/rman.h> 39 #include <sys/endian.h> 40 #include <sys/firmware.h> 41 #include <sys/limits.h> 42 #include <sys/module.h> 43 #include <sys/queue.h> 44 #include <sys/taskqueue.h> 45 46 #include <machine/bus.h> 47 #include <machine/resource.h> 48 #include <machine/clock.h> 49 50 #include <dev/pci/pcireg.h> 51 #include <dev/pci/pcivar.h> 52 53 #include <net/bpf.h> 54 #include <net/if.h> 55 #include <net/if_arp.h> 56 #include <net/ethernet.h> 57 #include <net/if_dl.h> 58 #include <net/if_media.h> 59 #include <net/if_types.h> 60 61 #include <netinet/in.h> 62 #include <netinet/in_systm.h> 63 #include <netinet/in_var.h> 64 #include <netinet/if_ether.h> 65 #include <netinet/ip.h> 66 67 #include <net80211/ieee80211_var.h> 68 #include <net80211/ieee80211_radiotap.h> 69 #include <net80211/ieee80211_regdomain.h> 70 #include <net80211/ieee80211_ratectl.h> 71 72 #include <dev/iwn/if_iwnreg.h> 73 #include <dev/iwn/if_iwnvar.h> 74 75 struct iwn_ident { 76 uint16_t vendor; 77 uint16_t device; 78 const char *name; 79 }; 80 81 static const struct iwn_ident iwn_ident_table[] = { 82 { 0x8086, 0x0082, "Intel(R) Centrino(R) Advanced-N 6205" }, 83 { 0x8086, 0x0083, "Intel(R) Centrino(R) Wireless-N 1000" }, 84 { 0x8086, 0x0084, "Intel(R) Centrino(R) Wireless-N 1000" }, 85 { 0x8086, 0x0085, "Intel(R) Centrino(R) Advanced-N 6205" }, 86 { 0x8086, 0x0087, "Intel(R) Centrino(R) Advanced-N + WiMAX 6250" }, 87 { 0x8086, 0x0089, "Intel(R) Centrino(R) Advanced-N + WiMAX 6250" }, 88 { 0x8086, 0x008a, "Intel(R) Centrino(R) Wireless-N 1030" }, 89 { 0x8086, 0x008b, "Intel(R) Centrino(R) Wireless-N 1030" }, 90 { 0x8086, 0x0090, "Intel(R) Centrino(R) Advanced-N 6230" }, 91 { 0x8086, 0x0091, "Intel(R) Centrino(R) Advanced-N 6230" }, 92 { 0x8086, 0x0896, "Intel(R) Centrino(R) Wireless-N 130" }, 93 { 0x8086, 0x4229, "Intel(R) Wireless WiFi Link 4965" }, 94 { 0x8086, 0x422b, "Intel(R) Centrino(R) Ultimate-N 6300" }, 95 { 0x8086, 0x422c, "Intel(R) Centrino(R) Advanced-N 6200" }, 96 { 0x8086, 0x422d, "Intel(R) Wireless WiFi Link 4965" }, 97 { 0x8086, 0x4230, "Intel(R) Wireless WiFi Link 4965" }, 98 { 0x8086, 0x4232, "Intel(R) WiFi Link 5100" }, 99 { 0x8086, 0x4233, "Intel(R) Wireless WiFi Link 4965" }, 100 { 0x8086, 0x4235, "Intel(R) Ultimate N WiFi Link 5300" }, 101 { 0x8086, 0x4236, "Intel(R) Ultimate N WiFi Link 5300" }, 102 { 0x8086, 0x4237, "Intel(R) WiFi Link 5100" }, 103 { 0x8086, 0x4238, "Intel(R) Centrino(R) Ultimate-N 6300" }, 104 { 0x8086, 0x4239, "Intel(R) Centrino(R) Advanced-N 6200" }, 105 { 0x8086, 0x423a, "Intel(R) WiMAX/WiFi Link 5350" }, 106 { 0x8086, 0x423b, "Intel(R) WiMAX/WiFi Link 5350" }, 107 { 0x8086, 0x423c, "Intel(R) WiMAX/WiFi Link 5150" }, 108 { 0x8086, 0x423d, "Intel(R) WiMAX/WiFi Link 5150" }, 109 { 0, 0, NULL } 110 }; 111 112 static int iwn_probe(device_t); 113 static int iwn_attach(device_t); 114 static int iwn4965_attach(struct iwn_softc *, uint16_t); 115 static int iwn5000_attach(struct iwn_softc *, uint16_t); 116 static void iwn_radiotap_attach(struct iwn_softc *); 117 static void iwn_sysctlattach(struct iwn_softc *); 118 static struct ieee80211vap *iwn_vap_create(struct ieee80211com *, 119 const char [IFNAMSIZ], int, enum ieee80211_opmode, int, 120 const uint8_t [IEEE80211_ADDR_LEN], 121 const uint8_t [IEEE80211_ADDR_LEN]); 122 static void iwn_vap_delete(struct ieee80211vap *); 123 static int iwn_detach(device_t); 124 static int iwn_shutdown(device_t); 125 static int iwn_suspend(device_t); 126 static int iwn_resume(device_t); 127 static int iwn_nic_lock(struct iwn_softc *); 128 static int iwn_eeprom_lock(struct iwn_softc *); 129 static int iwn_init_otprom(struct iwn_softc *); 130 static int iwn_read_prom_data(struct iwn_softc *, uint32_t, void *, int); 131 static void iwn_dma_map_addr(void *, bus_dma_segment_t *, int, int); 132 static int iwn_dma_contig_alloc(struct iwn_softc *, struct iwn_dma_info *, 133 void **, bus_size_t, bus_size_t); 134 static void iwn_dma_contig_free(struct iwn_dma_info *); 135 static int iwn_alloc_sched(struct iwn_softc *); 136 static void iwn_free_sched(struct iwn_softc *); 137 static int iwn_alloc_kw(struct iwn_softc *); 138 static void iwn_free_kw(struct iwn_softc *); 139 static int iwn_alloc_ict(struct iwn_softc *); 140 static void iwn_free_ict(struct iwn_softc *); 141 static int iwn_alloc_fwmem(struct iwn_softc *); 142 static void iwn_free_fwmem(struct iwn_softc *); 143 static int iwn_alloc_rx_ring(struct iwn_softc *, struct iwn_rx_ring *); 144 static void iwn_reset_rx_ring(struct iwn_softc *, struct iwn_rx_ring *); 145 static void iwn_free_rx_ring(struct iwn_softc *, struct iwn_rx_ring *); 146 static int iwn_alloc_tx_ring(struct iwn_softc *, struct iwn_tx_ring *, 147 int); 148 static void iwn_reset_tx_ring(struct iwn_softc *, struct iwn_tx_ring *); 149 static void iwn_free_tx_ring(struct iwn_softc *, struct iwn_tx_ring *); 150 static void iwn5000_ict_reset(struct iwn_softc *); 151 static int iwn_read_eeprom(struct iwn_softc *, 152 uint8_t macaddr[IEEE80211_ADDR_LEN]); 153 static void iwn4965_read_eeprom(struct iwn_softc *); 154 static void iwn4965_print_power_group(struct iwn_softc *, int); 155 static void iwn5000_read_eeprom(struct iwn_softc *); 156 static uint32_t iwn_eeprom_channel_flags(struct iwn_eeprom_chan *); 157 static void iwn_read_eeprom_band(struct iwn_softc *, int); 158 static void iwn_read_eeprom_ht40(struct iwn_softc *, int); 159 static void iwn_read_eeprom_channels(struct iwn_softc *, int, uint32_t); 160 static struct iwn_eeprom_chan *iwn_find_eeprom_channel(struct iwn_softc *, 161 struct ieee80211_channel *); 162 static int iwn_setregdomain(struct ieee80211com *, 163 struct ieee80211_regdomain *, int, 164 struct ieee80211_channel[]); 165 static void iwn_read_eeprom_enhinfo(struct iwn_softc *); 166 static struct ieee80211_node *iwn_node_alloc(struct ieee80211vap *, 167 const uint8_t mac[IEEE80211_ADDR_LEN]); 168 static void iwn_newassoc(struct ieee80211_node *, int); 169 static int iwn_media_change(struct ifnet *); 170 static int iwn_newstate(struct ieee80211vap *, enum ieee80211_state, int); 171 static void iwn_calib_timeout(void *); 172 static void iwn_rx_phy(struct iwn_softc *, struct iwn_rx_desc *, 173 struct iwn_rx_data *); 174 static void iwn_rx_done(struct iwn_softc *, struct iwn_rx_desc *, 175 struct iwn_rx_data *); 176 static void iwn_rx_compressed_ba(struct iwn_softc *, struct iwn_rx_desc *, 177 struct iwn_rx_data *); 178 static void iwn5000_rx_calib_results(struct iwn_softc *, 179 struct iwn_rx_desc *, struct iwn_rx_data *); 180 static void iwn_rx_statistics(struct iwn_softc *, struct iwn_rx_desc *, 181 struct iwn_rx_data *); 182 static void iwn4965_tx_done(struct iwn_softc *, struct iwn_rx_desc *, 183 struct iwn_rx_data *); 184 static void iwn5000_tx_done(struct iwn_softc *, struct iwn_rx_desc *, 185 struct iwn_rx_data *); 186 static void iwn_tx_done(struct iwn_softc *, struct iwn_rx_desc *, int, 187 uint8_t); 188 static void iwn_ampdu_tx_done(struct iwn_softc *, int, int, int, void *); 189 static void iwn_cmd_done(struct iwn_softc *, struct iwn_rx_desc *); 190 static void iwn_notif_intr(struct iwn_softc *); 191 static void iwn_wakeup_intr(struct iwn_softc *); 192 static void iwn_rftoggle_intr(struct iwn_softc *); 193 static void iwn_fatal_intr(struct iwn_softc *); 194 static void iwn_intr(void *); 195 static void iwn4965_update_sched(struct iwn_softc *, int, int, uint8_t, 196 uint16_t); 197 static void iwn5000_update_sched(struct iwn_softc *, int, int, uint8_t, 198 uint16_t); 199 #ifdef notyet 200 static void iwn5000_reset_sched(struct iwn_softc *, int, int); 201 #endif 202 static int iwn_tx_data(struct iwn_softc *, struct mbuf *, 203 struct ieee80211_node *); 204 static int iwn_tx_data_raw(struct iwn_softc *, struct mbuf *, 205 struct ieee80211_node *, 206 const struct ieee80211_bpf_params *params); 207 static int iwn_raw_xmit(struct ieee80211_node *, struct mbuf *, 208 const struct ieee80211_bpf_params *); 209 static void iwn_start(struct ifnet *); 210 static void iwn_start_locked(struct ifnet *); 211 static void iwn_watchdog(void *); 212 static int iwn_ioctl(struct ifnet *, u_long, caddr_t); 213 static int iwn_cmd(struct iwn_softc *, int, const void *, int, int); 214 static int iwn4965_add_node(struct iwn_softc *, struct iwn_node_info *, 215 int); 216 static int iwn5000_add_node(struct iwn_softc *, struct iwn_node_info *, 217 int); 218 static int iwn_set_link_quality(struct iwn_softc *, 219 struct ieee80211_node *); 220 static int iwn_add_broadcast_node(struct iwn_softc *, int); 221 static int iwn_updateedca(struct ieee80211com *); 222 static void iwn_update_mcast(struct ifnet *); 223 static void iwn_set_led(struct iwn_softc *, uint8_t, uint8_t, uint8_t); 224 static int iwn_set_critical_temp(struct iwn_softc *); 225 static int iwn_set_timing(struct iwn_softc *, struct ieee80211_node *); 226 static void iwn4965_power_calibration(struct iwn_softc *, int); 227 static int iwn4965_set_txpower(struct iwn_softc *, 228 struct ieee80211_channel *, int); 229 static int iwn5000_set_txpower(struct iwn_softc *, 230 struct ieee80211_channel *, int); 231 static int iwn4965_get_rssi(struct iwn_softc *, struct iwn_rx_stat *); 232 static int iwn5000_get_rssi(struct iwn_softc *, struct iwn_rx_stat *); 233 static int iwn_get_noise(const struct iwn_rx_general_stats *); 234 static int iwn4965_get_temperature(struct iwn_softc *); 235 static int iwn5000_get_temperature(struct iwn_softc *); 236 static int iwn_init_sensitivity(struct iwn_softc *); 237 static void iwn_collect_noise(struct iwn_softc *, 238 const struct iwn_rx_general_stats *); 239 static int iwn4965_init_gains(struct iwn_softc *); 240 static int iwn5000_init_gains(struct iwn_softc *); 241 static int iwn4965_set_gains(struct iwn_softc *); 242 static int iwn5000_set_gains(struct iwn_softc *); 243 static void iwn_tune_sensitivity(struct iwn_softc *, 244 const struct iwn_rx_stats *); 245 static int iwn_send_sensitivity(struct iwn_softc *); 246 static int iwn_set_pslevel(struct iwn_softc *, int, int, int); 247 static int iwn_send_btcoex(struct iwn_softc *); 248 static int iwn_send_advanced_btcoex(struct iwn_softc *); 249 static int iwn5000_runtime_calib(struct iwn_softc *); 250 static int iwn_config(struct iwn_softc *); 251 static uint8_t *ieee80211_add_ssid(uint8_t *, const uint8_t *, u_int); 252 static int iwn_scan(struct iwn_softc *); 253 static int iwn_auth(struct iwn_softc *, struct ieee80211vap *vap); 254 static int iwn_run(struct iwn_softc *, struct ieee80211vap *vap); 255 static int iwn_ampdu_rx_start(struct ieee80211_node *, 256 struct ieee80211_rx_ampdu *, int, int, int); 257 static void iwn_ampdu_rx_stop(struct ieee80211_node *, 258 struct ieee80211_rx_ampdu *); 259 static int iwn_addba_request(struct ieee80211_node *, 260 struct ieee80211_tx_ampdu *, int, int, int); 261 static int iwn_addba_response(struct ieee80211_node *, 262 struct ieee80211_tx_ampdu *, int, int, int); 263 static int iwn_ampdu_tx_start(struct ieee80211com *, 264 struct ieee80211_node *, uint8_t); 265 static void iwn_ampdu_tx_stop(struct ieee80211_node *, 266 struct ieee80211_tx_ampdu *); 267 static void iwn4965_ampdu_tx_start(struct iwn_softc *, 268 struct ieee80211_node *, int, uint8_t, uint16_t); 269 static void iwn4965_ampdu_tx_stop(struct iwn_softc *, int, 270 uint8_t, uint16_t); 271 static void iwn5000_ampdu_tx_start(struct iwn_softc *, 272 struct ieee80211_node *, int, uint8_t, uint16_t); 273 static void iwn5000_ampdu_tx_stop(struct iwn_softc *, int, 274 uint8_t, uint16_t); 275 static int iwn5000_query_calibration(struct iwn_softc *); 276 static int iwn5000_send_calibration(struct iwn_softc *); 277 static int iwn5000_send_wimax_coex(struct iwn_softc *); 278 static int iwn5000_crystal_calib(struct iwn_softc *); 279 static int iwn5000_temp_offset_calib(struct iwn_softc *); 280 static int iwn4965_post_alive(struct iwn_softc *); 281 static int iwn5000_post_alive(struct iwn_softc *); 282 static int iwn4965_load_bootcode(struct iwn_softc *, const uint8_t *, 283 int); 284 static int iwn4965_load_firmware(struct iwn_softc *); 285 static int iwn5000_load_firmware_section(struct iwn_softc *, uint32_t, 286 const uint8_t *, int); 287 static int iwn5000_load_firmware(struct iwn_softc *); 288 static int iwn_read_firmware_leg(struct iwn_softc *, 289 struct iwn_fw_info *); 290 static int iwn_read_firmware_tlv(struct iwn_softc *, 291 struct iwn_fw_info *, uint16_t); 292 static int iwn_read_firmware(struct iwn_softc *); 293 static int iwn_clock_wait(struct iwn_softc *); 294 static int iwn_apm_init(struct iwn_softc *); 295 static void iwn_apm_stop_master(struct iwn_softc *); 296 static void iwn_apm_stop(struct iwn_softc *); 297 static int iwn4965_nic_config(struct iwn_softc *); 298 static int iwn5000_nic_config(struct iwn_softc *); 299 static int iwn_hw_prepare(struct iwn_softc *); 300 static int iwn_hw_init(struct iwn_softc *); 301 static void iwn_hw_stop(struct iwn_softc *); 302 static void iwn_radio_on(void *, int); 303 static void iwn_radio_off(void *, int); 304 static void iwn_init_locked(struct iwn_softc *); 305 static void iwn_init(void *); 306 static void iwn_stop_locked(struct iwn_softc *); 307 static void iwn_stop(struct iwn_softc *); 308 static void iwn_scan_start(struct ieee80211com *); 309 static void iwn_scan_end(struct ieee80211com *); 310 static void iwn_set_channel(struct ieee80211com *); 311 static void iwn_scan_curchan(struct ieee80211_scan_state *, unsigned long); 312 static void iwn_scan_mindwell(struct ieee80211_scan_state *); 313 static void iwn_hw_reset(void *, int); 314 315 #define IWN_DEBUG 316 #ifdef IWN_DEBUG 317 enum { 318 IWN_DEBUG_XMIT = 0x00000001, /* basic xmit operation */ 319 IWN_DEBUG_RECV = 0x00000002, /* basic recv operation */ 320 IWN_DEBUG_STATE = 0x00000004, /* 802.11 state transitions */ 321 IWN_DEBUG_TXPOW = 0x00000008, /* tx power processing */ 322 IWN_DEBUG_RESET = 0x00000010, /* reset processing */ 323 IWN_DEBUG_OPS = 0x00000020, /* iwn_ops processing */ 324 IWN_DEBUG_BEACON = 0x00000040, /* beacon handling */ 325 IWN_DEBUG_WATCHDOG = 0x00000080, /* watchdog timeout */ 326 IWN_DEBUG_INTR = 0x00000100, /* ISR */ 327 IWN_DEBUG_CALIBRATE = 0x00000200, /* periodic calibration */ 328 IWN_DEBUG_NODE = 0x00000400, /* node management */ 329 IWN_DEBUG_LED = 0x00000800, /* led management */ 330 IWN_DEBUG_CMD = 0x00001000, /* cmd submission */ 331 IWN_DEBUG_FATAL = 0x80000000, /* fatal errors */ 332 IWN_DEBUG_ANY = 0xffffffff 333 }; 334 335 #define DPRINTF(sc, m, fmt, ...) do { \ 336 if (sc->sc_debug & (m)) \ 337 printf(fmt, __VA_ARGS__); \ 338 } while (0) 339 340 static const char * 341 iwn_intr_str(uint8_t cmd) 342 { 343 switch (cmd) { 344 /* Notifications */ 345 case IWN_UC_READY: return "UC_READY"; 346 case IWN_ADD_NODE_DONE: return "ADD_NODE_DONE"; 347 case IWN_TX_DONE: return "TX_DONE"; 348 case IWN_START_SCAN: return "START_SCAN"; 349 case IWN_STOP_SCAN: return "STOP_SCAN"; 350 case IWN_RX_STATISTICS: return "RX_STATS"; 351 case IWN_BEACON_STATISTICS: return "BEACON_STATS"; 352 case IWN_STATE_CHANGED: return "STATE_CHANGED"; 353 case IWN_BEACON_MISSED: return "BEACON_MISSED"; 354 case IWN_RX_PHY: return "RX_PHY"; 355 case IWN_MPDU_RX_DONE: return "MPDU_RX_DONE"; 356 case IWN_RX_DONE: return "RX_DONE"; 357 358 /* Command Notifications */ 359 case IWN_CMD_RXON: return "IWN_CMD_RXON"; 360 case IWN_CMD_RXON_ASSOC: return "IWN_CMD_RXON_ASSOC"; 361 case IWN_CMD_EDCA_PARAMS: return "IWN_CMD_EDCA_PARAMS"; 362 case IWN_CMD_TIMING: return "IWN_CMD_TIMING"; 363 case IWN_CMD_LINK_QUALITY: return "IWN_CMD_LINK_QUALITY"; 364 case IWN_CMD_SET_LED: return "IWN_CMD_SET_LED"; 365 case IWN5000_CMD_WIMAX_COEX: return "IWN5000_CMD_WIMAX_COEX"; 366 case IWN5000_CMD_CALIB_CONFIG: return "IWN5000_CMD_CALIB_CONFIG"; 367 case IWN5000_CMD_CALIB_RESULT: return "IWN5000_CMD_CALIB_RESULT"; 368 case IWN5000_CMD_CALIB_COMPLETE: return "IWN5000_CMD_CALIB_COMPLETE"; 369 case IWN_CMD_SET_POWER_MODE: return "IWN_CMD_SET_POWER_MODE"; 370 case IWN_CMD_SCAN: return "IWN_CMD_SCAN"; 371 case IWN_CMD_SCAN_RESULTS: return "IWN_CMD_SCAN_RESULTS"; 372 case IWN_CMD_TXPOWER: return "IWN_CMD_TXPOWER"; 373 case IWN_CMD_TXPOWER_DBM: return "IWN_CMD_TXPOWER_DBM"; 374 case IWN5000_CMD_TX_ANT_CONFIG: return "IWN5000_CMD_TX_ANT_CONFIG"; 375 case IWN_CMD_BT_COEX: return "IWN_CMD_BT_COEX"; 376 case IWN_CMD_SET_CRITICAL_TEMP: return "IWN_CMD_SET_CRITICAL_TEMP"; 377 case IWN_CMD_SET_SENSITIVITY: return "IWN_CMD_SET_SENSITIVITY"; 378 case IWN_CMD_PHY_CALIB: return "IWN_CMD_PHY_CALIB"; 379 } 380 return "UNKNOWN INTR NOTIF/CMD"; 381 } 382 #else 383 #define DPRINTF(sc, m, fmt, ...) do { (void) sc; } while (0) 384 #endif 385 386 static device_method_t iwn_methods[] = { 387 /* Device interface */ 388 DEVMETHOD(device_probe, iwn_probe), 389 DEVMETHOD(device_attach, iwn_attach), 390 DEVMETHOD(device_detach, iwn_detach), 391 DEVMETHOD(device_shutdown, iwn_shutdown), 392 DEVMETHOD(device_suspend, iwn_suspend), 393 DEVMETHOD(device_resume, iwn_resume), 394 { 0, 0 } 395 }; 396 397 static driver_t iwn_driver = { 398 "iwn", 399 iwn_methods, 400 sizeof(struct iwn_softc) 401 }; 402 static devclass_t iwn_devclass; 403 404 DRIVER_MODULE(iwn, pci, iwn_driver, iwn_devclass, 0, 0); 405 406 MODULE_VERSION(iwn, 1); 407 408 MODULE_DEPEND(iwn, firmware, 1, 1, 1); 409 MODULE_DEPEND(iwn, pci, 1, 1, 1); 410 MODULE_DEPEND(iwn, wlan, 1, 1, 1); 411 412 static int 413 iwn_probe(device_t dev) 414 { 415 const struct iwn_ident *ident; 416 417 for (ident = iwn_ident_table; ident->name != NULL; ident++) { 418 if (pci_get_vendor(dev) == ident->vendor && 419 pci_get_device(dev) == ident->device) { 420 device_set_desc(dev, ident->name); 421 return 0; 422 } 423 } 424 return ENXIO; 425 } 426 427 static int 428 iwn_attach(device_t dev) 429 { 430 struct iwn_softc *sc = (struct iwn_softc *)device_get_softc(dev); 431 struct ieee80211com *ic; 432 struct ifnet *ifp; 433 uint32_t reg; 434 int i, error, result; 435 uint8_t macaddr[IEEE80211_ADDR_LEN]; 436 437 sc->sc_dev = dev; 438 439 /* 440 * Get the offset of the PCI Express Capability Structure in PCI 441 * Configuration Space. 442 */ 443 error = pci_find_cap(dev, PCIY_EXPRESS, &sc->sc_cap_off); 444 if (error != 0) { 445 device_printf(dev, "PCIe capability structure not found!\n"); 446 return error; 447 } 448 449 /* Clear device-specific "PCI retry timeout" register (41h). */ 450 pci_write_config(dev, 0x41, 0, 1); 451 452 /* Hardware bug workaround. */ 453 reg = pci_read_config(dev, PCIR_COMMAND, 1); 454 if (reg & PCIM_CMD_INTxDIS) { 455 DPRINTF(sc, IWN_DEBUG_RESET, "%s: PCIe INTx Disable set\n", 456 __func__); 457 reg &= ~PCIM_CMD_INTxDIS; 458 pci_write_config(dev, PCIR_COMMAND, reg, 1); 459 } 460 461 /* Enable bus-mastering. */ 462 pci_enable_busmaster(dev); 463 464 sc->mem_rid = PCIR_BAR(0); 465 sc->mem = bus_alloc_resource_any(dev, SYS_RES_MEMORY, &sc->mem_rid, 466 RF_ACTIVE); 467 if (sc->mem == NULL) { 468 device_printf(dev, "can't map mem space\n"); 469 error = ENOMEM; 470 return error; 471 } 472 sc->sc_st = rman_get_bustag(sc->mem); 473 sc->sc_sh = rman_get_bushandle(sc->mem); 474 475 sc->irq_rid = 0; 476 if ((result = pci_msi_count(dev)) == 1 && 477 pci_alloc_msi(dev, &result) == 0) 478 sc->irq_rid = 1; 479 /* Install interrupt handler. */ 480 sc->irq = bus_alloc_resource_any(dev, SYS_RES_IRQ, &sc->irq_rid, 481 RF_ACTIVE | RF_SHAREABLE); 482 if (sc->irq == NULL) { 483 device_printf(dev, "can't map interrupt\n"); 484 error = ENOMEM; 485 goto fail; 486 } 487 488 IWN_LOCK_INIT(sc); 489 490 /* Read hardware revision and attach. */ 491 sc->hw_type = (IWN_READ(sc, IWN_HW_REV) >> 4) & 0xf; 492 if (sc->hw_type == IWN_HW_REV_TYPE_4965) 493 error = iwn4965_attach(sc, pci_get_device(dev)); 494 else 495 error = iwn5000_attach(sc, pci_get_device(dev)); 496 if (error != 0) { 497 device_printf(dev, "could not attach device, error %d\n", 498 error); 499 goto fail; 500 } 501 502 if ((error = iwn_hw_prepare(sc)) != 0) { 503 device_printf(dev, "hardware not ready, error %d\n", error); 504 goto fail; 505 } 506 507 /* Allocate DMA memory for firmware transfers. */ 508 if ((error = iwn_alloc_fwmem(sc)) != 0) { 509 device_printf(dev, 510 "could not allocate memory for firmware, error %d\n", 511 error); 512 goto fail; 513 } 514 515 /* Allocate "Keep Warm" page. */ 516 if ((error = iwn_alloc_kw(sc)) != 0) { 517 device_printf(dev, 518 "could not allocate keep warm page, error %d\n", error); 519 goto fail; 520 } 521 522 /* Allocate ICT table for 5000 Series. */ 523 if (sc->hw_type != IWN_HW_REV_TYPE_4965 && 524 (error = iwn_alloc_ict(sc)) != 0) { 525 device_printf(dev, "could not allocate ICT table, error %d\n", 526 error); 527 goto fail; 528 } 529 530 /* Allocate TX scheduler "rings". */ 531 if ((error = iwn_alloc_sched(sc)) != 0) { 532 device_printf(dev, 533 "could not allocate TX scheduler rings, error %d\n", error); 534 goto fail; 535 } 536 537 /* Allocate TX rings (16 on 4965AGN, 20 on >=5000). */ 538 for (i = 0; i < sc->ntxqs; i++) { 539 if ((error = iwn_alloc_tx_ring(sc, &sc->txq[i], i)) != 0) { 540 device_printf(dev, 541 "could not allocate TX ring %d, error %d\n", i, 542 error); 543 goto fail; 544 } 545 } 546 547 /* Allocate RX ring. */ 548 if ((error = iwn_alloc_rx_ring(sc, &sc->rxq)) != 0) { 549 device_printf(dev, "could not allocate RX ring, error %d\n", 550 error); 551 goto fail; 552 } 553 554 /* Clear pending interrupts. */ 555 IWN_WRITE(sc, IWN_INT, 0xffffffff); 556 557 ifp = sc->sc_ifp = if_alloc(IFT_IEEE80211); 558 if (ifp == NULL) { 559 device_printf(dev, "can not allocate ifnet structure\n"); 560 goto fail; 561 } 562 563 ic = ifp->if_l2com; 564 ic->ic_ifp = ifp; 565 ic->ic_phytype = IEEE80211_T_OFDM; /* not only, but not used */ 566 ic->ic_opmode = IEEE80211_M_STA; /* default to BSS mode */ 567 568 /* Set device capabilities. */ 569 ic->ic_caps = 570 IEEE80211_C_STA /* station mode supported */ 571 | IEEE80211_C_MONITOR /* monitor mode supported */ 572 | IEEE80211_C_BGSCAN /* background scanning */ 573 | IEEE80211_C_TXPMGT /* tx power management */ 574 | IEEE80211_C_SHSLOT /* short slot time supported */ 575 | IEEE80211_C_WPA 576 | IEEE80211_C_SHPREAMBLE /* short preamble supported */ 577 #if 0 578 | IEEE80211_C_IBSS /* ibss/adhoc mode */ 579 #endif 580 | IEEE80211_C_WME /* WME */ 581 ; 582 583 /* Read MAC address, channels, etc from EEPROM. */ 584 if ((error = iwn_read_eeprom(sc, macaddr)) != 0) { 585 device_printf(dev, "could not read EEPROM, error %d\n", 586 error); 587 goto fail; 588 } 589 590 /* Count the number of available chains. */ 591 sc->ntxchains = 592 ((sc->txchainmask >> 2) & 1) + 593 ((sc->txchainmask >> 1) & 1) + 594 ((sc->txchainmask >> 0) & 1); 595 sc->nrxchains = 596 ((sc->rxchainmask >> 2) & 1) + 597 ((sc->rxchainmask >> 1) & 1) + 598 ((sc->rxchainmask >> 0) & 1); 599 if (bootverbose) { 600 device_printf(dev, "MIMO %dT%dR, %.4s, address %6D\n", 601 sc->ntxchains, sc->nrxchains, sc->eeprom_domain, 602 macaddr, ":"); 603 } 604 605 if (sc->sc_flags & IWN_FLAG_HAS_11N) { 606 ic->ic_rxstream = sc->nrxchains; 607 ic->ic_txstream = sc->ntxchains; 608 ic->ic_htcaps = 609 IEEE80211_HTCAP_SMPS_OFF /* SMPS mode disabled */ 610 | IEEE80211_HTCAP_SHORTGI20 /* short GI in 20MHz */ 611 | IEEE80211_HTCAP_CHWIDTH40 /* 40MHz channel width*/ 612 | IEEE80211_HTCAP_SHORTGI40 /* short GI in 40MHz */ 613 #ifdef notyet 614 | IEEE80211_HTCAP_GREENFIELD 615 #if IWN_RBUF_SIZE == 8192 616 | IEEE80211_HTCAP_MAXAMSDU_7935 /* max A-MSDU length */ 617 #else 618 | IEEE80211_HTCAP_MAXAMSDU_3839 /* max A-MSDU length */ 619 #endif 620 #endif 621 /* s/w capabilities */ 622 | IEEE80211_HTC_HT /* HT operation */ 623 | IEEE80211_HTC_AMPDU /* tx A-MPDU */ 624 #ifdef notyet 625 | IEEE80211_HTC_AMSDU /* tx A-MSDU */ 626 #endif 627 ; 628 } 629 630 if_initname(ifp, device_get_name(dev), device_get_unit(dev)); 631 ifp->if_softc = sc; 632 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 633 ifp->if_init = iwn_init; 634 ifp->if_ioctl = iwn_ioctl; 635 ifp->if_start = iwn_start; 636 IFQ_SET_MAXLEN(&ifp->if_snd, ifqmaxlen); 637 ifp->if_snd.ifq_drv_maxlen = ifqmaxlen; 638 IFQ_SET_READY(&ifp->if_snd); 639 640 ieee80211_ifattach(ic, macaddr); 641 ic->ic_vap_create = iwn_vap_create; 642 ic->ic_vap_delete = iwn_vap_delete; 643 ic->ic_raw_xmit = iwn_raw_xmit; 644 ic->ic_node_alloc = iwn_node_alloc; 645 sc->sc_ampdu_rx_start = ic->ic_ampdu_rx_start; 646 ic->ic_ampdu_rx_start = iwn_ampdu_rx_start; 647 sc->sc_ampdu_rx_stop = ic->ic_ampdu_rx_stop; 648 ic->ic_ampdu_rx_stop = iwn_ampdu_rx_stop; 649 sc->sc_addba_request = ic->ic_addba_request; 650 ic->ic_addba_request = iwn_addba_request; 651 sc->sc_addba_response = ic->ic_addba_response; 652 ic->ic_addba_response = iwn_addba_response; 653 sc->sc_addba_stop = ic->ic_addba_stop; 654 ic->ic_addba_stop = iwn_ampdu_tx_stop; 655 ic->ic_newassoc = iwn_newassoc; 656 ic->ic_wme.wme_update = iwn_updateedca; 657 ic->ic_update_mcast = iwn_update_mcast; 658 ic->ic_scan_start = iwn_scan_start; 659 ic->ic_scan_end = iwn_scan_end; 660 ic->ic_set_channel = iwn_set_channel; 661 ic->ic_scan_curchan = iwn_scan_curchan; 662 ic->ic_scan_mindwell = iwn_scan_mindwell; 663 ic->ic_setregdomain = iwn_setregdomain; 664 665 iwn_radiotap_attach(sc); 666 667 callout_init_mtx(&sc->calib_to, &sc->sc_mtx, 0); 668 callout_init_mtx(&sc->watchdog_to, &sc->sc_mtx, 0); 669 TASK_INIT(&sc->sc_reinit_task, 0, iwn_hw_reset, sc); 670 TASK_INIT(&sc->sc_radioon_task, 0, iwn_radio_on, sc); 671 TASK_INIT(&sc->sc_radiooff_task, 0, iwn_radio_off, sc); 672 673 iwn_sysctlattach(sc); 674 675 /* 676 * Hook our interrupt after all initialization is complete. 677 */ 678 error = bus_setup_intr(dev, sc->irq, INTR_TYPE_NET | INTR_MPSAFE, 679 NULL, iwn_intr, sc, &sc->sc_ih); 680 if (error != 0) { 681 device_printf(dev, "can't establish interrupt, error %d\n", 682 error); 683 goto fail; 684 } 685 686 if (bootverbose) 687 ieee80211_announce(ic); 688 return 0; 689 fail: 690 iwn_detach(dev); 691 return error; 692 } 693 694 static int 695 iwn4965_attach(struct iwn_softc *sc, uint16_t pid) 696 { 697 struct iwn_ops *ops = &sc->ops; 698 699 ops->load_firmware = iwn4965_load_firmware; 700 ops->read_eeprom = iwn4965_read_eeprom; 701 ops->post_alive = iwn4965_post_alive; 702 ops->nic_config = iwn4965_nic_config; 703 ops->update_sched = iwn4965_update_sched; 704 ops->get_temperature = iwn4965_get_temperature; 705 ops->get_rssi = iwn4965_get_rssi; 706 ops->set_txpower = iwn4965_set_txpower; 707 ops->init_gains = iwn4965_init_gains; 708 ops->set_gains = iwn4965_set_gains; 709 ops->add_node = iwn4965_add_node; 710 ops->tx_done = iwn4965_tx_done; 711 ops->ampdu_tx_start = iwn4965_ampdu_tx_start; 712 ops->ampdu_tx_stop = iwn4965_ampdu_tx_stop; 713 sc->ntxqs = IWN4965_NTXQUEUES; 714 sc->firstaggqueue = IWN4965_FIRSTAGGQUEUE; 715 sc->ndmachnls = IWN4965_NDMACHNLS; 716 sc->broadcast_id = IWN4965_ID_BROADCAST; 717 sc->rxonsz = IWN4965_RXONSZ; 718 sc->schedsz = IWN4965_SCHEDSZ; 719 sc->fw_text_maxsz = IWN4965_FW_TEXT_MAXSZ; 720 sc->fw_data_maxsz = IWN4965_FW_DATA_MAXSZ; 721 sc->fwsz = IWN4965_FWSZ; 722 sc->sched_txfact_addr = IWN4965_SCHED_TXFACT; 723 sc->limits = &iwn4965_sensitivity_limits; 724 sc->fwname = "iwn4965fw"; 725 /* Override chains masks, ROM is known to be broken. */ 726 sc->txchainmask = IWN_ANT_AB; 727 sc->rxchainmask = IWN_ANT_ABC; 728 729 return 0; 730 } 731 732 static int 733 iwn5000_attach(struct iwn_softc *sc, uint16_t pid) 734 { 735 struct iwn_ops *ops = &sc->ops; 736 737 ops->load_firmware = iwn5000_load_firmware; 738 ops->read_eeprom = iwn5000_read_eeprom; 739 ops->post_alive = iwn5000_post_alive; 740 ops->nic_config = iwn5000_nic_config; 741 ops->update_sched = iwn5000_update_sched; 742 ops->get_temperature = iwn5000_get_temperature; 743 ops->get_rssi = iwn5000_get_rssi; 744 ops->set_txpower = iwn5000_set_txpower; 745 ops->init_gains = iwn5000_init_gains; 746 ops->set_gains = iwn5000_set_gains; 747 ops->add_node = iwn5000_add_node; 748 ops->tx_done = iwn5000_tx_done; 749 ops->ampdu_tx_start = iwn5000_ampdu_tx_start; 750 ops->ampdu_tx_stop = iwn5000_ampdu_tx_stop; 751 sc->ntxqs = IWN5000_NTXQUEUES; 752 sc->firstaggqueue = IWN5000_FIRSTAGGQUEUE; 753 sc->ndmachnls = IWN5000_NDMACHNLS; 754 sc->broadcast_id = IWN5000_ID_BROADCAST; 755 sc->rxonsz = IWN5000_RXONSZ; 756 sc->schedsz = IWN5000_SCHEDSZ; 757 sc->fw_text_maxsz = IWN5000_FW_TEXT_MAXSZ; 758 sc->fw_data_maxsz = IWN5000_FW_DATA_MAXSZ; 759 sc->fwsz = IWN5000_FWSZ; 760 sc->sched_txfact_addr = IWN5000_SCHED_TXFACT; 761 sc->reset_noise_gain = IWN5000_PHY_CALIB_RESET_NOISE_GAIN; 762 sc->noise_gain = IWN5000_PHY_CALIB_NOISE_GAIN; 763 764 switch (sc->hw_type) { 765 case IWN_HW_REV_TYPE_5100: 766 sc->limits = &iwn5000_sensitivity_limits; 767 sc->fwname = "iwn5000fw"; 768 /* Override chains masks, ROM is known to be broken. */ 769 sc->txchainmask = IWN_ANT_B; 770 sc->rxchainmask = IWN_ANT_AB; 771 break; 772 case IWN_HW_REV_TYPE_5150: 773 sc->limits = &iwn5150_sensitivity_limits; 774 sc->fwname = "iwn5150fw"; 775 break; 776 case IWN_HW_REV_TYPE_5300: 777 case IWN_HW_REV_TYPE_5350: 778 sc->limits = &iwn5000_sensitivity_limits; 779 sc->fwname = "iwn5000fw"; 780 break; 781 case IWN_HW_REV_TYPE_1000: 782 sc->limits = &iwn1000_sensitivity_limits; 783 sc->fwname = "iwn1000fw"; 784 break; 785 case IWN_HW_REV_TYPE_6000: 786 sc->limits = &iwn6000_sensitivity_limits; 787 sc->fwname = "iwn6000fw"; 788 if (pid == 0x422c || pid == 0x4239) { 789 sc->sc_flags |= IWN_FLAG_INTERNAL_PA; 790 /* Override chains masks, ROM is known to be broken. */ 791 sc->txchainmask = IWN_ANT_BC; 792 sc->rxchainmask = IWN_ANT_BC; 793 } 794 break; 795 case IWN_HW_REV_TYPE_6050: 796 sc->limits = &iwn6000_sensitivity_limits; 797 sc->fwname = "iwn6050fw"; 798 /* Override chains masks, ROM is known to be broken. */ 799 sc->txchainmask = IWN_ANT_AB; 800 sc->rxchainmask = IWN_ANT_AB; 801 break; 802 case IWN_HW_REV_TYPE_6005: 803 sc->limits = &iwn6000_sensitivity_limits; 804 if (pid != 0x0082 && pid != 0x0085) { 805 sc->fwname = "iwn6000g2bfw"; 806 sc->sc_flags |= IWN_FLAG_ADV_BTCOEX; 807 } else 808 sc->fwname = "iwn6000g2afw"; 809 break; 810 default: 811 device_printf(sc->sc_dev, "adapter type %d not supported\n", 812 sc->hw_type); 813 return ENOTSUP; 814 } 815 return 0; 816 } 817 818 /* 819 * Attach the interface to 802.11 radiotap. 820 */ 821 static void 822 iwn_radiotap_attach(struct iwn_softc *sc) 823 { 824 struct ifnet *ifp = sc->sc_ifp; 825 struct ieee80211com *ic = ifp->if_l2com; 826 827 ieee80211_radiotap_attach(ic, 828 &sc->sc_txtap.wt_ihdr, sizeof(sc->sc_txtap), 829 IWN_TX_RADIOTAP_PRESENT, 830 &sc->sc_rxtap.wr_ihdr, sizeof(sc->sc_rxtap), 831 IWN_RX_RADIOTAP_PRESENT); 832 } 833 834 static void 835 iwn_sysctlattach(struct iwn_softc *sc) 836 { 837 struct sysctl_ctx_list *ctx = device_get_sysctl_ctx(sc->sc_dev); 838 struct sysctl_oid *tree = device_get_sysctl_tree(sc->sc_dev); 839 840 #ifdef IWN_DEBUG 841 sc->sc_debug = 0; 842 SYSCTL_ADD_INT(ctx, SYSCTL_CHILDREN(tree), OID_AUTO, 843 "debug", CTLFLAG_RW, &sc->sc_debug, 0, "control debugging printfs"); 844 #endif 845 } 846 847 static struct ieee80211vap * 848 iwn_vap_create(struct ieee80211com *ic, const char name[IFNAMSIZ], int unit, 849 enum ieee80211_opmode opmode, int flags, 850 const uint8_t bssid[IEEE80211_ADDR_LEN], 851 const uint8_t mac[IEEE80211_ADDR_LEN]) 852 { 853 struct iwn_vap *ivp; 854 struct ieee80211vap *vap; 855 856 if (!TAILQ_EMPTY(&ic->ic_vaps)) /* only one at a time */ 857 return NULL; 858 ivp = (struct iwn_vap *) malloc(sizeof(struct iwn_vap), 859 M_80211_VAP, M_NOWAIT | M_ZERO); 860 if (ivp == NULL) 861 return NULL; 862 vap = &ivp->iv_vap; 863 ieee80211_vap_setup(ic, vap, name, unit, opmode, flags, bssid, mac); 864 vap->iv_bmissthreshold = 10; /* override default */ 865 /* Override with driver methods. */ 866 ivp->iv_newstate = vap->iv_newstate; 867 vap->iv_newstate = iwn_newstate; 868 869 ieee80211_ratectl_init(vap); 870 /* Complete setup. */ 871 ieee80211_vap_attach(vap, iwn_media_change, ieee80211_media_status); 872 ic->ic_opmode = opmode; 873 return vap; 874 } 875 876 static void 877 iwn_vap_delete(struct ieee80211vap *vap) 878 { 879 struct iwn_vap *ivp = IWN_VAP(vap); 880 881 ieee80211_ratectl_deinit(vap); 882 ieee80211_vap_detach(vap); 883 free(ivp, M_80211_VAP); 884 } 885 886 static int 887 iwn_detach(device_t dev) 888 { 889 struct iwn_softc *sc = device_get_softc(dev); 890 struct ifnet *ifp = sc->sc_ifp; 891 struct ieee80211com *ic; 892 int qid; 893 894 if (ifp != NULL) { 895 ic = ifp->if_l2com; 896 897 ieee80211_draintask(ic, &sc->sc_reinit_task); 898 ieee80211_draintask(ic, &sc->sc_radioon_task); 899 ieee80211_draintask(ic, &sc->sc_radiooff_task); 900 901 iwn_stop(sc); 902 callout_drain(&sc->watchdog_to); 903 callout_drain(&sc->calib_to); 904 ieee80211_ifdetach(ic); 905 } 906 907 /* Uninstall interrupt handler. */ 908 if (sc->irq != NULL) { 909 bus_teardown_intr(dev, sc->irq, sc->sc_ih); 910 bus_release_resource(dev, SYS_RES_IRQ, sc->irq_rid, sc->irq); 911 if (sc->irq_rid == 1) 912 pci_release_msi(dev); 913 } 914 915 /* Free DMA resources. */ 916 iwn_free_rx_ring(sc, &sc->rxq); 917 for (qid = 0; qid < sc->ntxqs; qid++) 918 iwn_free_tx_ring(sc, &sc->txq[qid]); 919 iwn_free_sched(sc); 920 iwn_free_kw(sc); 921 if (sc->ict != NULL) 922 iwn_free_ict(sc); 923 iwn_free_fwmem(sc); 924 925 if (sc->mem != NULL) 926 bus_release_resource(dev, SYS_RES_MEMORY, sc->mem_rid, sc->mem); 927 928 if (ifp != NULL) 929 if_free(ifp); 930 931 IWN_LOCK_DESTROY(sc); 932 return 0; 933 } 934 935 static int 936 iwn_shutdown(device_t dev) 937 { 938 struct iwn_softc *sc = device_get_softc(dev); 939 940 iwn_stop(sc); 941 return 0; 942 } 943 944 static int 945 iwn_suspend(device_t dev) 946 { 947 struct iwn_softc *sc = device_get_softc(dev); 948 struct ifnet *ifp = sc->sc_ifp; 949 struct ieee80211com *ic = ifp->if_l2com; 950 struct ieee80211vap *vap = TAILQ_FIRST(&ic->ic_vaps); 951 952 iwn_stop(sc); 953 if (vap != NULL) 954 ieee80211_stop(vap); 955 return 0; 956 } 957 958 static int 959 iwn_resume(device_t dev) 960 { 961 struct iwn_softc *sc = device_get_softc(dev); 962 struct ifnet *ifp = sc->sc_ifp; 963 struct ieee80211com *ic = ifp->if_l2com; 964 struct ieee80211vap *vap = TAILQ_FIRST(&ic->ic_vaps); 965 966 /* Clear device-specific "PCI retry timeout" register (41h). */ 967 pci_write_config(dev, 0x41, 0, 1); 968 969 if (ifp->if_flags & IFF_UP) { 970 iwn_init(sc); 971 if (vap != NULL) 972 ieee80211_init(vap); 973 if (ifp->if_drv_flags & IFF_DRV_RUNNING) 974 iwn_start(ifp); 975 } 976 return 0; 977 } 978 979 static int 980 iwn_nic_lock(struct iwn_softc *sc) 981 { 982 int ntries; 983 984 /* Request exclusive access to NIC. */ 985 IWN_SETBITS(sc, IWN_GP_CNTRL, IWN_GP_CNTRL_MAC_ACCESS_REQ); 986 987 /* Spin until we actually get the lock. */ 988 for (ntries = 0; ntries < 1000; ntries++) { 989 if ((IWN_READ(sc, IWN_GP_CNTRL) & 990 (IWN_GP_CNTRL_MAC_ACCESS_ENA | IWN_GP_CNTRL_SLEEP)) == 991 IWN_GP_CNTRL_MAC_ACCESS_ENA) 992 return 0; 993 DELAY(10); 994 } 995 return ETIMEDOUT; 996 } 997 998 static __inline void 999 iwn_nic_unlock(struct iwn_softc *sc) 1000 { 1001 IWN_CLRBITS(sc, IWN_GP_CNTRL, IWN_GP_CNTRL_MAC_ACCESS_REQ); 1002 } 1003 1004 static __inline uint32_t 1005 iwn_prph_read(struct iwn_softc *sc, uint32_t addr) 1006 { 1007 IWN_WRITE(sc, IWN_PRPH_RADDR, IWN_PRPH_DWORD | addr); 1008 IWN_BARRIER_READ_WRITE(sc); 1009 return IWN_READ(sc, IWN_PRPH_RDATA); 1010 } 1011 1012 static __inline void 1013 iwn_prph_write(struct iwn_softc *sc, uint32_t addr, uint32_t data) 1014 { 1015 IWN_WRITE(sc, IWN_PRPH_WADDR, IWN_PRPH_DWORD | addr); 1016 IWN_BARRIER_WRITE(sc); 1017 IWN_WRITE(sc, IWN_PRPH_WDATA, data); 1018 } 1019 1020 static __inline void 1021 iwn_prph_setbits(struct iwn_softc *sc, uint32_t addr, uint32_t mask) 1022 { 1023 iwn_prph_write(sc, addr, iwn_prph_read(sc, addr) | mask); 1024 } 1025 1026 static __inline void 1027 iwn_prph_clrbits(struct iwn_softc *sc, uint32_t addr, uint32_t mask) 1028 { 1029 iwn_prph_write(sc, addr, iwn_prph_read(sc, addr) & ~mask); 1030 } 1031 1032 static __inline void 1033 iwn_prph_write_region_4(struct iwn_softc *sc, uint32_t addr, 1034 const uint32_t *data, int count) 1035 { 1036 for (; count > 0; count--, data++, addr += 4) 1037 iwn_prph_write(sc, addr, *data); 1038 } 1039 1040 static __inline uint32_t 1041 iwn_mem_read(struct iwn_softc *sc, uint32_t addr) 1042 { 1043 IWN_WRITE(sc, IWN_MEM_RADDR, addr); 1044 IWN_BARRIER_READ_WRITE(sc); 1045 return IWN_READ(sc, IWN_MEM_RDATA); 1046 } 1047 1048 static __inline void 1049 iwn_mem_write(struct iwn_softc *sc, uint32_t addr, uint32_t data) 1050 { 1051 IWN_WRITE(sc, IWN_MEM_WADDR, addr); 1052 IWN_BARRIER_WRITE(sc); 1053 IWN_WRITE(sc, IWN_MEM_WDATA, data); 1054 } 1055 1056 static __inline void 1057 iwn_mem_write_2(struct iwn_softc *sc, uint32_t addr, uint16_t data) 1058 { 1059 uint32_t tmp; 1060 1061 tmp = iwn_mem_read(sc, addr & ~3); 1062 if (addr & 3) 1063 tmp = (tmp & 0x0000ffff) | data << 16; 1064 else 1065 tmp = (tmp & 0xffff0000) | data; 1066 iwn_mem_write(sc, addr & ~3, tmp); 1067 } 1068 1069 static __inline void 1070 iwn_mem_read_region_4(struct iwn_softc *sc, uint32_t addr, uint32_t *data, 1071 int count) 1072 { 1073 for (; count > 0; count--, addr += 4) 1074 *data++ = iwn_mem_read(sc, addr); 1075 } 1076 1077 static __inline void 1078 iwn_mem_set_region_4(struct iwn_softc *sc, uint32_t addr, uint32_t val, 1079 int count) 1080 { 1081 for (; count > 0; count--, addr += 4) 1082 iwn_mem_write(sc, addr, val); 1083 } 1084 1085 static int 1086 iwn_eeprom_lock(struct iwn_softc *sc) 1087 { 1088 int i, ntries; 1089 1090 for (i = 0; i < 100; i++) { 1091 /* Request exclusive access to EEPROM. */ 1092 IWN_SETBITS(sc, IWN_HW_IF_CONFIG, 1093 IWN_HW_IF_CONFIG_EEPROM_LOCKED); 1094 1095 /* Spin until we actually get the lock. */ 1096 for (ntries = 0; ntries < 100; ntries++) { 1097 if (IWN_READ(sc, IWN_HW_IF_CONFIG) & 1098 IWN_HW_IF_CONFIG_EEPROM_LOCKED) 1099 return 0; 1100 DELAY(10); 1101 } 1102 } 1103 return ETIMEDOUT; 1104 } 1105 1106 static __inline void 1107 iwn_eeprom_unlock(struct iwn_softc *sc) 1108 { 1109 IWN_CLRBITS(sc, IWN_HW_IF_CONFIG, IWN_HW_IF_CONFIG_EEPROM_LOCKED); 1110 } 1111 1112 /* 1113 * Initialize access by host to One Time Programmable ROM. 1114 * NB: This kind of ROM can be found on 1000 or 6000 Series only. 1115 */ 1116 static int 1117 iwn_init_otprom(struct iwn_softc *sc) 1118 { 1119 uint16_t prev, base, next; 1120 int count, error; 1121 1122 /* Wait for clock stabilization before accessing prph. */ 1123 if ((error = iwn_clock_wait(sc)) != 0) 1124 return error; 1125 1126 if ((error = iwn_nic_lock(sc)) != 0) 1127 return error; 1128 iwn_prph_setbits(sc, IWN_APMG_PS, IWN_APMG_PS_RESET_REQ); 1129 DELAY(5); 1130 iwn_prph_clrbits(sc, IWN_APMG_PS, IWN_APMG_PS_RESET_REQ); 1131 iwn_nic_unlock(sc); 1132 1133 /* Set auto clock gate disable bit for HW with OTP shadow RAM. */ 1134 if (sc->hw_type != IWN_HW_REV_TYPE_1000) { 1135 IWN_SETBITS(sc, IWN_DBG_LINK_PWR_MGMT, 1136 IWN_RESET_LINK_PWR_MGMT_DIS); 1137 } 1138 IWN_CLRBITS(sc, IWN_EEPROM_GP, IWN_EEPROM_GP_IF_OWNER); 1139 /* Clear ECC status. */ 1140 IWN_SETBITS(sc, IWN_OTP_GP, 1141 IWN_OTP_GP_ECC_CORR_STTS | IWN_OTP_GP_ECC_UNCORR_STTS); 1142 1143 /* 1144 * Find the block before last block (contains the EEPROM image) 1145 * for HW without OTP shadow RAM. 1146 */ 1147 if (sc->hw_type == IWN_HW_REV_TYPE_1000) { 1148 /* Switch to absolute addressing mode. */ 1149 IWN_CLRBITS(sc, IWN_OTP_GP, IWN_OTP_GP_RELATIVE_ACCESS); 1150 base = prev = 0; 1151 for (count = 0; count < IWN1000_OTP_NBLOCKS; count++) { 1152 error = iwn_read_prom_data(sc, base, &next, 2); 1153 if (error != 0) 1154 return error; 1155 if (next == 0) /* End of linked-list. */ 1156 break; 1157 prev = base; 1158 base = le16toh(next); 1159 } 1160 if (count == 0 || count == IWN1000_OTP_NBLOCKS) 1161 return EIO; 1162 /* Skip "next" word. */ 1163 sc->prom_base = prev + 1; 1164 } 1165 return 0; 1166 } 1167 1168 static int 1169 iwn_read_prom_data(struct iwn_softc *sc, uint32_t addr, void *data, int count) 1170 { 1171 uint8_t *out = data; 1172 uint32_t val, tmp; 1173 int ntries; 1174 1175 addr += sc->prom_base; 1176 for (; count > 0; count -= 2, addr++) { 1177 IWN_WRITE(sc, IWN_EEPROM, addr << 2); 1178 for (ntries = 0; ntries < 10; ntries++) { 1179 val = IWN_READ(sc, IWN_EEPROM); 1180 if (val & IWN_EEPROM_READ_VALID) 1181 break; 1182 DELAY(5); 1183 } 1184 if (ntries == 10) { 1185 device_printf(sc->sc_dev, 1186 "timeout reading ROM at 0x%x\n", addr); 1187 return ETIMEDOUT; 1188 } 1189 if (sc->sc_flags & IWN_FLAG_HAS_OTPROM) { 1190 /* OTPROM, check for ECC errors. */ 1191 tmp = IWN_READ(sc, IWN_OTP_GP); 1192 if (tmp & IWN_OTP_GP_ECC_UNCORR_STTS) { 1193 device_printf(sc->sc_dev, 1194 "OTPROM ECC error at 0x%x\n", addr); 1195 return EIO; 1196 } 1197 if (tmp & IWN_OTP_GP_ECC_CORR_STTS) { 1198 /* Correctable ECC error, clear bit. */ 1199 IWN_SETBITS(sc, IWN_OTP_GP, 1200 IWN_OTP_GP_ECC_CORR_STTS); 1201 } 1202 } 1203 *out++ = val >> 16; 1204 if (count > 1) 1205 *out++ = val >> 24; 1206 } 1207 return 0; 1208 } 1209 1210 static void 1211 iwn_dma_map_addr(void *arg, bus_dma_segment_t *segs, int nsegs, int error) 1212 { 1213 if (error != 0) 1214 return; 1215 KASSERT(nsegs == 1, ("too many DMA segments, %d should be 1", nsegs)); 1216 *(bus_addr_t *)arg = segs[0].ds_addr; 1217 } 1218 1219 static int 1220 iwn_dma_contig_alloc(struct iwn_softc *sc, struct iwn_dma_info *dma, 1221 void **kvap, bus_size_t size, bus_size_t alignment) 1222 { 1223 int error; 1224 1225 dma->tag = NULL; 1226 dma->size = size; 1227 1228 error = bus_dma_tag_create(bus_get_dma_tag(sc->sc_dev), alignment, 1229 0, BUS_SPACE_MAXADDR_32BIT, BUS_SPACE_MAXADDR, NULL, NULL, size, 1230 1, size, BUS_DMA_NOWAIT, NULL, NULL, &dma->tag); 1231 if (error != 0) 1232 goto fail; 1233 1234 error = bus_dmamem_alloc(dma->tag, (void **)&dma->vaddr, 1235 BUS_DMA_NOWAIT | BUS_DMA_ZERO | BUS_DMA_COHERENT, &dma->map); 1236 if (error != 0) 1237 goto fail; 1238 1239 error = bus_dmamap_load(dma->tag, dma->map, dma->vaddr, size, 1240 iwn_dma_map_addr, &dma->paddr, BUS_DMA_NOWAIT); 1241 if (error != 0) 1242 goto fail; 1243 1244 bus_dmamap_sync(dma->tag, dma->map, BUS_DMASYNC_PREWRITE); 1245 1246 if (kvap != NULL) 1247 *kvap = dma->vaddr; 1248 1249 return 0; 1250 1251 fail: iwn_dma_contig_free(dma); 1252 return error; 1253 } 1254 1255 static void 1256 iwn_dma_contig_free(struct iwn_dma_info *dma) 1257 { 1258 if (dma->map != NULL) { 1259 if (dma->vaddr != NULL) { 1260 bus_dmamap_sync(dma->tag, dma->map, 1261 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); 1262 bus_dmamap_unload(dma->tag, dma->map); 1263 bus_dmamem_free(dma->tag, &dma->vaddr, dma->map); 1264 dma->vaddr = NULL; 1265 } 1266 bus_dmamap_destroy(dma->tag, dma->map); 1267 dma->map = NULL; 1268 } 1269 if (dma->tag != NULL) { 1270 bus_dma_tag_destroy(dma->tag); 1271 dma->tag = NULL; 1272 } 1273 } 1274 1275 static int 1276 iwn_alloc_sched(struct iwn_softc *sc) 1277 { 1278 /* TX scheduler rings must be aligned on a 1KB boundary. */ 1279 return iwn_dma_contig_alloc(sc, &sc->sched_dma, (void **)&sc->sched, 1280 sc->schedsz, 1024); 1281 } 1282 1283 static void 1284 iwn_free_sched(struct iwn_softc *sc) 1285 { 1286 iwn_dma_contig_free(&sc->sched_dma); 1287 } 1288 1289 static int 1290 iwn_alloc_kw(struct iwn_softc *sc) 1291 { 1292 /* "Keep Warm" page must be aligned on a 4KB boundary. */ 1293 return iwn_dma_contig_alloc(sc, &sc->kw_dma, NULL, 4096, 4096); 1294 } 1295 1296 static void 1297 iwn_free_kw(struct iwn_softc *sc) 1298 { 1299 iwn_dma_contig_free(&sc->kw_dma); 1300 } 1301 1302 static int 1303 iwn_alloc_ict(struct iwn_softc *sc) 1304 { 1305 /* ICT table must be aligned on a 4KB boundary. */ 1306 return iwn_dma_contig_alloc(sc, &sc->ict_dma, (void **)&sc->ict, 1307 IWN_ICT_SIZE, 4096); 1308 } 1309 1310 static void 1311 iwn_free_ict(struct iwn_softc *sc) 1312 { 1313 iwn_dma_contig_free(&sc->ict_dma); 1314 } 1315 1316 static int 1317 iwn_alloc_fwmem(struct iwn_softc *sc) 1318 { 1319 /* Must be aligned on a 16-byte boundary. */ 1320 return iwn_dma_contig_alloc(sc, &sc->fw_dma, NULL, sc->fwsz, 16); 1321 } 1322 1323 static void 1324 iwn_free_fwmem(struct iwn_softc *sc) 1325 { 1326 iwn_dma_contig_free(&sc->fw_dma); 1327 } 1328 1329 static int 1330 iwn_alloc_rx_ring(struct iwn_softc *sc, struct iwn_rx_ring *ring) 1331 { 1332 bus_size_t size; 1333 int i, error; 1334 1335 ring->cur = 0; 1336 1337 /* Allocate RX descriptors (256-byte aligned). */ 1338 size = IWN_RX_RING_COUNT * sizeof (uint32_t); 1339 error = iwn_dma_contig_alloc(sc, &ring->desc_dma, (void **)&ring->desc, 1340 size, 256); 1341 if (error != 0) { 1342 device_printf(sc->sc_dev, 1343 "%s: could not allocate RX ring DMA memory, error %d\n", 1344 __func__, error); 1345 goto fail; 1346 } 1347 1348 /* Allocate RX status area (16-byte aligned). */ 1349 error = iwn_dma_contig_alloc(sc, &ring->stat_dma, (void **)&ring->stat, 1350 sizeof (struct iwn_rx_status), 16); 1351 if (error != 0) { 1352 device_printf(sc->sc_dev, 1353 "%s: could not allocate RX status DMA memory, error %d\n", 1354 __func__, error); 1355 goto fail; 1356 } 1357 1358 /* Create RX buffer DMA tag. */ 1359 error = bus_dma_tag_create(bus_get_dma_tag(sc->sc_dev), 1, 0, 1360 BUS_SPACE_MAXADDR_32BIT, BUS_SPACE_MAXADDR, NULL, NULL, 1361 IWN_RBUF_SIZE, 1, IWN_RBUF_SIZE, BUS_DMA_NOWAIT, NULL, NULL, 1362 &ring->data_dmat); 1363 if (error != 0) { 1364 device_printf(sc->sc_dev, 1365 "%s: could not create RX buf DMA tag, error %d\n", 1366 __func__, error); 1367 goto fail; 1368 } 1369 1370 /* 1371 * Allocate and map RX buffers. 1372 */ 1373 for (i = 0; i < IWN_RX_RING_COUNT; i++) { 1374 struct iwn_rx_data *data = &ring->data[i]; 1375 bus_addr_t paddr; 1376 1377 error = bus_dmamap_create(ring->data_dmat, 0, &data->map); 1378 if (error != 0) { 1379 device_printf(sc->sc_dev, 1380 "%s: could not create RX buf DMA map, error %d\n", 1381 __func__, error); 1382 goto fail; 1383 } 1384 1385 data->m = m_getjcl(M_DONTWAIT, MT_DATA, M_PKTHDR, 1386 IWN_RBUF_SIZE); 1387 if (data->m == NULL) { 1388 device_printf(sc->sc_dev, 1389 "%s: could not allocate RX mbuf\n", __func__); 1390 error = ENOBUFS; 1391 goto fail; 1392 } 1393 1394 error = bus_dmamap_load(ring->data_dmat, data->map, 1395 mtod(data->m, void *), IWN_RBUF_SIZE, iwn_dma_map_addr, 1396 &paddr, BUS_DMA_NOWAIT); 1397 if (error != 0 && error != EFBIG) { 1398 device_printf(sc->sc_dev, 1399 "%s: can't not map mbuf, error %d\n", __func__, 1400 error); 1401 goto fail; 1402 } 1403 1404 /* Set physical address of RX buffer (256-byte aligned). */ 1405 ring->desc[i] = htole32(paddr >> 8); 1406 } 1407 1408 bus_dmamap_sync(ring->desc_dma.tag, ring->desc_dma.map, 1409 BUS_DMASYNC_PREWRITE); 1410 1411 return 0; 1412 1413 fail: iwn_free_rx_ring(sc, ring); 1414 return error; 1415 } 1416 1417 static void 1418 iwn_reset_rx_ring(struct iwn_softc *sc, struct iwn_rx_ring *ring) 1419 { 1420 int ntries; 1421 1422 if (iwn_nic_lock(sc) == 0) { 1423 IWN_WRITE(sc, IWN_FH_RX_CONFIG, 0); 1424 for (ntries = 0; ntries < 1000; ntries++) { 1425 if (IWN_READ(sc, IWN_FH_RX_STATUS) & 1426 IWN_FH_RX_STATUS_IDLE) 1427 break; 1428 DELAY(10); 1429 } 1430 iwn_nic_unlock(sc); 1431 } 1432 ring->cur = 0; 1433 sc->last_rx_valid = 0; 1434 } 1435 1436 static void 1437 iwn_free_rx_ring(struct iwn_softc *sc, struct iwn_rx_ring *ring) 1438 { 1439 int i; 1440 1441 iwn_dma_contig_free(&ring->desc_dma); 1442 iwn_dma_contig_free(&ring->stat_dma); 1443 1444 for (i = 0; i < IWN_RX_RING_COUNT; i++) { 1445 struct iwn_rx_data *data = &ring->data[i]; 1446 1447 if (data->m != NULL) { 1448 bus_dmamap_sync(ring->data_dmat, data->map, 1449 BUS_DMASYNC_POSTREAD); 1450 bus_dmamap_unload(ring->data_dmat, data->map); 1451 m_freem(data->m); 1452 data->m = NULL; 1453 } 1454 if (data->map != NULL) 1455 bus_dmamap_destroy(ring->data_dmat, data->map); 1456 } 1457 if (ring->data_dmat != NULL) { 1458 bus_dma_tag_destroy(ring->data_dmat); 1459 ring->data_dmat = NULL; 1460 } 1461 } 1462 1463 static int 1464 iwn_alloc_tx_ring(struct iwn_softc *sc, struct iwn_tx_ring *ring, int qid) 1465 { 1466 bus_addr_t paddr; 1467 bus_size_t size; 1468 int i, error; 1469 1470 ring->qid = qid; 1471 ring->queued = 0; 1472 ring->cur = 0; 1473 1474 /* Allocate TX descriptors (256-byte aligned). */ 1475 size = IWN_TX_RING_COUNT * sizeof (struct iwn_tx_desc); 1476 error = iwn_dma_contig_alloc(sc, &ring->desc_dma, (void **)&ring->desc, 1477 size, 256); 1478 if (error != 0) { 1479 device_printf(sc->sc_dev, 1480 "%s: could not allocate TX ring DMA memory, error %d\n", 1481 __func__, error); 1482 goto fail; 1483 } 1484 1485 size = IWN_TX_RING_COUNT * sizeof (struct iwn_tx_cmd); 1486 error = iwn_dma_contig_alloc(sc, &ring->cmd_dma, (void **)&ring->cmd, 1487 size, 4); 1488 if (error != 0) { 1489 device_printf(sc->sc_dev, 1490 "%s: could not allocate TX cmd DMA memory, error %d\n", 1491 __func__, error); 1492 goto fail; 1493 } 1494 1495 error = bus_dma_tag_create(bus_get_dma_tag(sc->sc_dev), 1, 0, 1496 BUS_SPACE_MAXADDR_32BIT, BUS_SPACE_MAXADDR, NULL, NULL, MCLBYTES, 1497 IWN_MAX_SCATTER - 1, MCLBYTES, BUS_DMA_NOWAIT, NULL, NULL, 1498 &ring->data_dmat); 1499 if (error != 0) { 1500 device_printf(sc->sc_dev, 1501 "%s: could not create TX buf DMA tag, error %d\n", 1502 __func__, error); 1503 goto fail; 1504 } 1505 1506 paddr = ring->cmd_dma.paddr; 1507 for (i = 0; i < IWN_TX_RING_COUNT; i++) { 1508 struct iwn_tx_data *data = &ring->data[i]; 1509 1510 data->cmd_paddr = paddr; 1511 data->scratch_paddr = paddr + 12; 1512 paddr += sizeof (struct iwn_tx_cmd); 1513 1514 error = bus_dmamap_create(ring->data_dmat, 0, &data->map); 1515 if (error != 0) { 1516 device_printf(sc->sc_dev, 1517 "%s: could not create TX buf DMA map, error %d\n", 1518 __func__, error); 1519 goto fail; 1520 } 1521 } 1522 return 0; 1523 1524 fail: iwn_free_tx_ring(sc, ring); 1525 return error; 1526 } 1527 1528 static void 1529 iwn_reset_tx_ring(struct iwn_softc *sc, struct iwn_tx_ring *ring) 1530 { 1531 int i; 1532 1533 for (i = 0; i < IWN_TX_RING_COUNT; i++) { 1534 struct iwn_tx_data *data = &ring->data[i]; 1535 1536 if (data->m != NULL) { 1537 bus_dmamap_sync(ring->data_dmat, data->map, 1538 BUS_DMASYNC_POSTWRITE); 1539 bus_dmamap_unload(ring->data_dmat, data->map); 1540 m_freem(data->m); 1541 data->m = NULL; 1542 } 1543 } 1544 /* Clear TX descriptors. */ 1545 memset(ring->desc, 0, ring->desc_dma.size); 1546 bus_dmamap_sync(ring->desc_dma.tag, ring->desc_dma.map, 1547 BUS_DMASYNC_PREWRITE); 1548 sc->qfullmsk &= ~(1 << ring->qid); 1549 ring->queued = 0; 1550 ring->cur = 0; 1551 } 1552 1553 static void 1554 iwn_free_tx_ring(struct iwn_softc *sc, struct iwn_tx_ring *ring) 1555 { 1556 int i; 1557 1558 iwn_dma_contig_free(&ring->desc_dma); 1559 iwn_dma_contig_free(&ring->cmd_dma); 1560 1561 for (i = 0; i < IWN_TX_RING_COUNT; i++) { 1562 struct iwn_tx_data *data = &ring->data[i]; 1563 1564 if (data->m != NULL) { 1565 bus_dmamap_sync(ring->data_dmat, data->map, 1566 BUS_DMASYNC_POSTWRITE); 1567 bus_dmamap_unload(ring->data_dmat, data->map); 1568 m_freem(data->m); 1569 } 1570 if (data->map != NULL) 1571 bus_dmamap_destroy(ring->data_dmat, data->map); 1572 } 1573 if (ring->data_dmat != NULL) { 1574 bus_dma_tag_destroy(ring->data_dmat); 1575 ring->data_dmat = NULL; 1576 } 1577 } 1578 1579 static void 1580 iwn5000_ict_reset(struct iwn_softc *sc) 1581 { 1582 /* Disable interrupts. */ 1583 IWN_WRITE(sc, IWN_INT_MASK, 0); 1584 1585 /* Reset ICT table. */ 1586 memset(sc->ict, 0, IWN_ICT_SIZE); 1587 sc->ict_cur = 0; 1588 1589 /* Set physical address of ICT table (4KB aligned). */ 1590 DPRINTF(sc, IWN_DEBUG_RESET, "%s: enabling ICT\n", __func__); 1591 IWN_WRITE(sc, IWN_DRAM_INT_TBL, IWN_DRAM_INT_TBL_ENABLE | 1592 IWN_DRAM_INT_TBL_WRAP_CHECK | sc->ict_dma.paddr >> 12); 1593 1594 /* Enable periodic RX interrupt. */ 1595 sc->int_mask |= IWN_INT_RX_PERIODIC; 1596 /* Switch to ICT interrupt mode in driver. */ 1597 sc->sc_flags |= IWN_FLAG_USE_ICT; 1598 1599 /* Re-enable interrupts. */ 1600 IWN_WRITE(sc, IWN_INT, 0xffffffff); 1601 IWN_WRITE(sc, IWN_INT_MASK, sc->int_mask); 1602 } 1603 1604 static int 1605 iwn_read_eeprom(struct iwn_softc *sc, uint8_t macaddr[IEEE80211_ADDR_LEN]) 1606 { 1607 struct iwn_ops *ops = &sc->ops; 1608 uint16_t val; 1609 int error; 1610 1611 /* Check whether adapter has an EEPROM or an OTPROM. */ 1612 if (sc->hw_type >= IWN_HW_REV_TYPE_1000 && 1613 (IWN_READ(sc, IWN_OTP_GP) & IWN_OTP_GP_DEV_SEL_OTP)) 1614 sc->sc_flags |= IWN_FLAG_HAS_OTPROM; 1615 DPRINTF(sc, IWN_DEBUG_RESET, "%s found\n", 1616 (sc->sc_flags & IWN_FLAG_HAS_OTPROM) ? "OTPROM" : "EEPROM"); 1617 1618 /* Adapter has to be powered on for EEPROM access to work. */ 1619 if ((error = iwn_apm_init(sc)) != 0) { 1620 device_printf(sc->sc_dev, 1621 "%s: could not power ON adapter, error %d\n", __func__, 1622 error); 1623 return error; 1624 } 1625 1626 if ((IWN_READ(sc, IWN_EEPROM_GP) & 0x7) == 0) { 1627 device_printf(sc->sc_dev, "%s: bad ROM signature\n", __func__); 1628 return EIO; 1629 } 1630 if ((error = iwn_eeprom_lock(sc)) != 0) { 1631 device_printf(sc->sc_dev, "%s: could not lock ROM, error %d\n", 1632 __func__, error); 1633 return error; 1634 } 1635 if (sc->sc_flags & IWN_FLAG_HAS_OTPROM) { 1636 if ((error = iwn_init_otprom(sc)) != 0) { 1637 device_printf(sc->sc_dev, 1638 "%s: could not initialize OTPROM, error %d\n", 1639 __func__, error); 1640 return error; 1641 } 1642 } 1643 1644 iwn_read_prom_data(sc, IWN_EEPROM_SKU_CAP, &val, 2); 1645 DPRINTF(sc, IWN_DEBUG_RESET, "SKU capabilities=0x%04x\n", le16toh(val)); 1646 /* Check if HT support is bonded out. */ 1647 if (val & htole16(IWN_EEPROM_SKU_CAP_11N)) 1648 sc->sc_flags |= IWN_FLAG_HAS_11N; 1649 1650 iwn_read_prom_data(sc, IWN_EEPROM_RFCFG, &val, 2); 1651 sc->rfcfg = le16toh(val); 1652 DPRINTF(sc, IWN_DEBUG_RESET, "radio config=0x%04x\n", sc->rfcfg); 1653 /* Read Tx/Rx chains from ROM unless it's known to be broken. */ 1654 if (sc->txchainmask == 0) 1655 sc->txchainmask = IWN_RFCFG_TXANTMSK(sc->rfcfg); 1656 if (sc->rxchainmask == 0) 1657 sc->rxchainmask = IWN_RFCFG_RXANTMSK(sc->rfcfg); 1658 1659 /* Read MAC address. */ 1660 iwn_read_prom_data(sc, IWN_EEPROM_MAC, macaddr, 6); 1661 1662 /* Read adapter-specific information from EEPROM. */ 1663 ops->read_eeprom(sc); 1664 1665 iwn_apm_stop(sc); /* Power OFF adapter. */ 1666 1667 iwn_eeprom_unlock(sc); 1668 return 0; 1669 } 1670 1671 static void 1672 iwn4965_read_eeprom(struct iwn_softc *sc) 1673 { 1674 uint32_t addr; 1675 uint16_t val; 1676 int i; 1677 1678 /* Read regulatory domain (4 ASCII characters). */ 1679 iwn_read_prom_data(sc, IWN4965_EEPROM_DOMAIN, sc->eeprom_domain, 4); 1680 1681 /* Read the list of authorized channels (20MHz ones only). */ 1682 for (i = 0; i < 7; i++) { 1683 addr = iwn4965_regulatory_bands[i]; 1684 iwn_read_eeprom_channels(sc, i, addr); 1685 } 1686 1687 /* Read maximum allowed TX power for 2GHz and 5GHz bands. */ 1688 iwn_read_prom_data(sc, IWN4965_EEPROM_MAXPOW, &val, 2); 1689 sc->maxpwr2GHz = val & 0xff; 1690 sc->maxpwr5GHz = val >> 8; 1691 /* Check that EEPROM values are within valid range. */ 1692 if (sc->maxpwr5GHz < 20 || sc->maxpwr5GHz > 50) 1693 sc->maxpwr5GHz = 38; 1694 if (sc->maxpwr2GHz < 20 || sc->maxpwr2GHz > 50) 1695 sc->maxpwr2GHz = 38; 1696 DPRINTF(sc, IWN_DEBUG_RESET, "maxpwr 2GHz=%d 5GHz=%d\n", 1697 sc->maxpwr2GHz, sc->maxpwr5GHz); 1698 1699 /* Read samples for each TX power group. */ 1700 iwn_read_prom_data(sc, IWN4965_EEPROM_BANDS, sc->bands, 1701 sizeof sc->bands); 1702 1703 /* Read voltage at which samples were taken. */ 1704 iwn_read_prom_data(sc, IWN4965_EEPROM_VOLTAGE, &val, 2); 1705 sc->eeprom_voltage = (int16_t)le16toh(val); 1706 DPRINTF(sc, IWN_DEBUG_RESET, "voltage=%d (in 0.3V)\n", 1707 sc->eeprom_voltage); 1708 1709 #ifdef IWN_DEBUG 1710 /* Print samples. */ 1711 if (sc->sc_debug & IWN_DEBUG_ANY) { 1712 for (i = 0; i < IWN_NBANDS; i++) 1713 iwn4965_print_power_group(sc, i); 1714 } 1715 #endif 1716 } 1717 1718 #ifdef IWN_DEBUG 1719 static void 1720 iwn4965_print_power_group(struct iwn_softc *sc, int i) 1721 { 1722 struct iwn4965_eeprom_band *band = &sc->bands[i]; 1723 struct iwn4965_eeprom_chan_samples *chans = band->chans; 1724 int j, c; 1725 1726 printf("===band %d===\n", i); 1727 printf("chan lo=%d, chan hi=%d\n", band->lo, band->hi); 1728 printf("chan1 num=%d\n", chans[0].num); 1729 for (c = 0; c < 2; c++) { 1730 for (j = 0; j < IWN_NSAMPLES; j++) { 1731 printf("chain %d, sample %d: temp=%d gain=%d " 1732 "power=%d pa_det=%d\n", c, j, 1733 chans[0].samples[c][j].temp, 1734 chans[0].samples[c][j].gain, 1735 chans[0].samples[c][j].power, 1736 chans[0].samples[c][j].pa_det); 1737 } 1738 } 1739 printf("chan2 num=%d\n", chans[1].num); 1740 for (c = 0; c < 2; c++) { 1741 for (j = 0; j < IWN_NSAMPLES; j++) { 1742 printf("chain %d, sample %d: temp=%d gain=%d " 1743 "power=%d pa_det=%d\n", c, j, 1744 chans[1].samples[c][j].temp, 1745 chans[1].samples[c][j].gain, 1746 chans[1].samples[c][j].power, 1747 chans[1].samples[c][j].pa_det); 1748 } 1749 } 1750 } 1751 #endif 1752 1753 static void 1754 iwn5000_read_eeprom(struct iwn_softc *sc) 1755 { 1756 struct iwn5000_eeprom_calib_hdr hdr; 1757 int32_t volt; 1758 uint32_t base, addr; 1759 uint16_t val; 1760 int i; 1761 1762 /* Read regulatory domain (4 ASCII characters). */ 1763 iwn_read_prom_data(sc, IWN5000_EEPROM_REG, &val, 2); 1764 base = le16toh(val); 1765 iwn_read_prom_data(sc, base + IWN5000_EEPROM_DOMAIN, 1766 sc->eeprom_domain, 4); 1767 1768 /* Read the list of authorized channels (20MHz ones only). */ 1769 for (i = 0; i < 7; i++) { 1770 if (sc->hw_type >= IWN_HW_REV_TYPE_6000) 1771 addr = base + iwn6000_regulatory_bands[i]; 1772 else 1773 addr = base + iwn5000_regulatory_bands[i]; 1774 iwn_read_eeprom_channels(sc, i, addr); 1775 } 1776 1777 /* Read enhanced TX power information for 6000 Series. */ 1778 if (sc->hw_type >= IWN_HW_REV_TYPE_6000) 1779 iwn_read_eeprom_enhinfo(sc); 1780 1781 iwn_read_prom_data(sc, IWN5000_EEPROM_CAL, &val, 2); 1782 base = le16toh(val); 1783 iwn_read_prom_data(sc, base, &hdr, sizeof hdr); 1784 DPRINTF(sc, IWN_DEBUG_CALIBRATE, 1785 "%s: calib version=%u pa type=%u voltage=%u\n", __func__, 1786 hdr.version, hdr.pa_type, le16toh(hdr.volt)); 1787 sc->calib_ver = hdr.version; 1788 1789 if (sc->hw_type == IWN_HW_REV_TYPE_5150) { 1790 /* Compute temperature offset. */ 1791 iwn_read_prom_data(sc, base + IWN5000_EEPROM_TEMP, &val, 2); 1792 sc->eeprom_temp = le16toh(val); 1793 iwn_read_prom_data(sc, base + IWN5000_EEPROM_VOLT, &val, 2); 1794 volt = le16toh(val); 1795 sc->temp_off = sc->eeprom_temp - (volt / -5); 1796 DPRINTF(sc, IWN_DEBUG_CALIBRATE, "temp=%d volt=%d offset=%dK\n", 1797 sc->eeprom_temp, volt, sc->temp_off); 1798 } else { 1799 /* Read crystal calibration. */ 1800 iwn_read_prom_data(sc, base + IWN5000_EEPROM_CRYSTAL, 1801 &sc->eeprom_crystal, sizeof (uint32_t)); 1802 DPRINTF(sc, IWN_DEBUG_CALIBRATE, "crystal calibration 0x%08x\n", 1803 le32toh(sc->eeprom_crystal)); 1804 } 1805 } 1806 1807 /* 1808 * Translate EEPROM flags to net80211. 1809 */ 1810 static uint32_t 1811 iwn_eeprom_channel_flags(struct iwn_eeprom_chan *channel) 1812 { 1813 uint32_t nflags; 1814 1815 nflags = 0; 1816 if ((channel->flags & IWN_EEPROM_CHAN_ACTIVE) == 0) 1817 nflags |= IEEE80211_CHAN_PASSIVE; 1818 if ((channel->flags & IWN_EEPROM_CHAN_IBSS) == 0) 1819 nflags |= IEEE80211_CHAN_NOADHOC; 1820 if (channel->flags & IWN_EEPROM_CHAN_RADAR) { 1821 nflags |= IEEE80211_CHAN_DFS; 1822 /* XXX apparently IBSS may still be marked */ 1823 nflags |= IEEE80211_CHAN_NOADHOC; 1824 } 1825 1826 return nflags; 1827 } 1828 1829 static void 1830 iwn_read_eeprom_band(struct iwn_softc *sc, int n) 1831 { 1832 struct ifnet *ifp = sc->sc_ifp; 1833 struct ieee80211com *ic = ifp->if_l2com; 1834 struct iwn_eeprom_chan *channels = sc->eeprom_channels[n]; 1835 const struct iwn_chan_band *band = &iwn_bands[n]; 1836 struct ieee80211_channel *c; 1837 uint8_t chan; 1838 int i, nflags; 1839 1840 for (i = 0; i < band->nchan; i++) { 1841 if (!(channels[i].flags & IWN_EEPROM_CHAN_VALID)) { 1842 DPRINTF(sc, IWN_DEBUG_RESET, 1843 "skip chan %d flags 0x%x maxpwr %d\n", 1844 band->chan[i], channels[i].flags, 1845 channels[i].maxpwr); 1846 continue; 1847 } 1848 chan = band->chan[i]; 1849 nflags = iwn_eeprom_channel_flags(&channels[i]); 1850 1851 c = &ic->ic_channels[ic->ic_nchans++]; 1852 c->ic_ieee = chan; 1853 c->ic_maxregpower = channels[i].maxpwr; 1854 c->ic_maxpower = 2*c->ic_maxregpower; 1855 1856 if (n == 0) { /* 2GHz band */ 1857 c->ic_freq = ieee80211_ieee2mhz(chan, IEEE80211_CHAN_G); 1858 /* G =>'s B is supported */ 1859 c->ic_flags = IEEE80211_CHAN_B | nflags; 1860 c = &ic->ic_channels[ic->ic_nchans++]; 1861 c[0] = c[-1]; 1862 c->ic_flags = IEEE80211_CHAN_G | nflags; 1863 } else { /* 5GHz band */ 1864 c->ic_freq = ieee80211_ieee2mhz(chan, IEEE80211_CHAN_A); 1865 c->ic_flags = IEEE80211_CHAN_A | nflags; 1866 } 1867 1868 /* Save maximum allowed TX power for this channel. */ 1869 sc->maxpwr[chan] = channels[i].maxpwr; 1870 1871 DPRINTF(sc, IWN_DEBUG_RESET, 1872 "add chan %d flags 0x%x maxpwr %d\n", chan, 1873 channels[i].flags, channels[i].maxpwr); 1874 1875 if (sc->sc_flags & IWN_FLAG_HAS_11N) { 1876 /* add HT20, HT40 added separately */ 1877 c = &ic->ic_channels[ic->ic_nchans++]; 1878 c[0] = c[-1]; 1879 c->ic_flags |= IEEE80211_CHAN_HT20; 1880 } 1881 } 1882 } 1883 1884 static void 1885 iwn_read_eeprom_ht40(struct iwn_softc *sc, int n) 1886 { 1887 struct ifnet *ifp = sc->sc_ifp; 1888 struct ieee80211com *ic = ifp->if_l2com; 1889 struct iwn_eeprom_chan *channels = sc->eeprom_channels[n]; 1890 const struct iwn_chan_band *band = &iwn_bands[n]; 1891 struct ieee80211_channel *c, *cent, *extc; 1892 uint8_t chan; 1893 int i, nflags; 1894 1895 if (!(sc->sc_flags & IWN_FLAG_HAS_11N)) 1896 return; 1897 1898 for (i = 0; i < band->nchan; i++) { 1899 if (!(channels[i].flags & IWN_EEPROM_CHAN_VALID)) { 1900 DPRINTF(sc, IWN_DEBUG_RESET, 1901 "skip chan %d flags 0x%x maxpwr %d\n", 1902 band->chan[i], channels[i].flags, 1903 channels[i].maxpwr); 1904 continue; 1905 } 1906 chan = band->chan[i]; 1907 nflags = iwn_eeprom_channel_flags(&channels[i]); 1908 1909 /* 1910 * Each entry defines an HT40 channel pair; find the 1911 * center channel, then the extension channel above. 1912 */ 1913 cent = ieee80211_find_channel_byieee(ic, chan, 1914 (n == 5 ? IEEE80211_CHAN_G : IEEE80211_CHAN_A)); 1915 if (cent == NULL) { /* XXX shouldn't happen */ 1916 device_printf(sc->sc_dev, 1917 "%s: no entry for channel %d\n", __func__, chan); 1918 continue; 1919 } 1920 extc = ieee80211_find_channel(ic, cent->ic_freq+20, 1921 (n == 5 ? IEEE80211_CHAN_G : IEEE80211_CHAN_A)); 1922 if (extc == NULL) { 1923 DPRINTF(sc, IWN_DEBUG_RESET, 1924 "%s: skip chan %d, extension channel not found\n", 1925 __func__, chan); 1926 continue; 1927 } 1928 1929 DPRINTF(sc, IWN_DEBUG_RESET, 1930 "add ht40 chan %d flags 0x%x maxpwr %d\n", 1931 chan, channels[i].flags, channels[i].maxpwr); 1932 1933 c = &ic->ic_channels[ic->ic_nchans++]; 1934 c[0] = cent[0]; 1935 c->ic_extieee = extc->ic_ieee; 1936 c->ic_flags &= ~IEEE80211_CHAN_HT; 1937 c->ic_flags |= IEEE80211_CHAN_HT40U | nflags; 1938 c = &ic->ic_channels[ic->ic_nchans++]; 1939 c[0] = extc[0]; 1940 c->ic_extieee = cent->ic_ieee; 1941 c->ic_flags &= ~IEEE80211_CHAN_HT; 1942 c->ic_flags |= IEEE80211_CHAN_HT40D | nflags; 1943 } 1944 } 1945 1946 static void 1947 iwn_read_eeprom_channels(struct iwn_softc *sc, int n, uint32_t addr) 1948 { 1949 struct ifnet *ifp = sc->sc_ifp; 1950 struct ieee80211com *ic = ifp->if_l2com; 1951 1952 iwn_read_prom_data(sc, addr, &sc->eeprom_channels[n], 1953 iwn_bands[n].nchan * sizeof (struct iwn_eeprom_chan)); 1954 1955 if (n < 5) 1956 iwn_read_eeprom_band(sc, n); 1957 else 1958 iwn_read_eeprom_ht40(sc, n); 1959 ieee80211_sort_channels(ic->ic_channels, ic->ic_nchans); 1960 } 1961 1962 static struct iwn_eeprom_chan * 1963 iwn_find_eeprom_channel(struct iwn_softc *sc, struct ieee80211_channel *c) 1964 { 1965 int band, chan, i, j; 1966 1967 if (IEEE80211_IS_CHAN_HT40(c)) { 1968 band = IEEE80211_IS_CHAN_5GHZ(c) ? 6 : 5; 1969 if (IEEE80211_IS_CHAN_HT40D(c)) 1970 chan = c->ic_extieee; 1971 else 1972 chan = c->ic_ieee; 1973 for (i = 0; i < iwn_bands[band].nchan; i++) { 1974 if (iwn_bands[band].chan[i] == chan) 1975 return &sc->eeprom_channels[band][i]; 1976 } 1977 } else { 1978 for (j = 0; j < 5; j++) { 1979 for (i = 0; i < iwn_bands[j].nchan; i++) { 1980 if (iwn_bands[j].chan[i] == c->ic_ieee) 1981 return &sc->eeprom_channels[j][i]; 1982 } 1983 } 1984 } 1985 return NULL; 1986 } 1987 1988 /* 1989 * Enforce flags read from EEPROM. 1990 */ 1991 static int 1992 iwn_setregdomain(struct ieee80211com *ic, struct ieee80211_regdomain *rd, 1993 int nchan, struct ieee80211_channel chans[]) 1994 { 1995 struct iwn_softc *sc = ic->ic_ifp->if_softc; 1996 int i; 1997 1998 for (i = 0; i < nchan; i++) { 1999 struct ieee80211_channel *c = &chans[i]; 2000 struct iwn_eeprom_chan *channel; 2001 2002 channel = iwn_find_eeprom_channel(sc, c); 2003 if (channel == NULL) { 2004 if_printf(ic->ic_ifp, 2005 "%s: invalid channel %u freq %u/0x%x\n", 2006 __func__, c->ic_ieee, c->ic_freq, c->ic_flags); 2007 return EINVAL; 2008 } 2009 c->ic_flags |= iwn_eeprom_channel_flags(channel); 2010 } 2011 2012 return 0; 2013 } 2014 2015 #define nitems(_a) (sizeof((_a)) / sizeof((_a)[0])) 2016 2017 static void 2018 iwn_read_eeprom_enhinfo(struct iwn_softc *sc) 2019 { 2020 struct iwn_eeprom_enhinfo enhinfo[35]; 2021 struct ifnet *ifp = sc->sc_ifp; 2022 struct ieee80211com *ic = ifp->if_l2com; 2023 struct ieee80211_channel *c; 2024 uint16_t val, base; 2025 int8_t maxpwr; 2026 uint8_t flags; 2027 int i, j; 2028 2029 iwn_read_prom_data(sc, IWN5000_EEPROM_REG, &val, 2); 2030 base = le16toh(val); 2031 iwn_read_prom_data(sc, base + IWN6000_EEPROM_ENHINFO, 2032 enhinfo, sizeof enhinfo); 2033 2034 for (i = 0; i < nitems(enhinfo); i++) { 2035 flags = enhinfo[i].flags; 2036 if (!(flags & IWN_ENHINFO_VALID)) 2037 continue; /* Skip invalid entries. */ 2038 2039 maxpwr = 0; 2040 if (sc->txchainmask & IWN_ANT_A) 2041 maxpwr = MAX(maxpwr, enhinfo[i].chain[0]); 2042 if (sc->txchainmask & IWN_ANT_B) 2043 maxpwr = MAX(maxpwr, enhinfo[i].chain[1]); 2044 if (sc->txchainmask & IWN_ANT_C) 2045 maxpwr = MAX(maxpwr, enhinfo[i].chain[2]); 2046 if (sc->ntxchains == 2) 2047 maxpwr = MAX(maxpwr, enhinfo[i].mimo2); 2048 else if (sc->ntxchains == 3) 2049 maxpwr = MAX(maxpwr, enhinfo[i].mimo3); 2050 2051 for (j = 0; j < ic->ic_nchans; j++) { 2052 c = &ic->ic_channels[j]; 2053 if ((flags & IWN_ENHINFO_5GHZ)) { 2054 if (!IEEE80211_IS_CHAN_A(c)) 2055 continue; 2056 } else if ((flags & IWN_ENHINFO_OFDM)) { 2057 if (!IEEE80211_IS_CHAN_G(c)) 2058 continue; 2059 } else if (!IEEE80211_IS_CHAN_B(c)) 2060 continue; 2061 if ((flags & IWN_ENHINFO_HT40)) { 2062 if (!IEEE80211_IS_CHAN_HT40(c)) 2063 continue; 2064 } else { 2065 if (IEEE80211_IS_CHAN_HT40(c)) 2066 continue; 2067 } 2068 if (enhinfo[i].chan != 0 && 2069 enhinfo[i].chan != c->ic_ieee) 2070 continue; 2071 2072 DPRINTF(sc, IWN_DEBUG_RESET, 2073 "channel %d(%x), maxpwr %d\n", c->ic_ieee, 2074 c->ic_flags, maxpwr / 2); 2075 c->ic_maxregpower = maxpwr / 2; 2076 c->ic_maxpower = maxpwr; 2077 } 2078 } 2079 } 2080 2081 static struct ieee80211_node * 2082 iwn_node_alloc(struct ieee80211vap *vap, const uint8_t mac[IEEE80211_ADDR_LEN]) 2083 { 2084 return malloc(sizeof (struct iwn_node), M_80211_NODE,M_NOWAIT | M_ZERO); 2085 } 2086 2087 static __inline int 2088 rate2plcp(int rate) 2089 { 2090 switch (rate & 0xff) { 2091 case 12: return 0xd; 2092 case 18: return 0xf; 2093 case 24: return 0x5; 2094 case 36: return 0x7; 2095 case 48: return 0x9; 2096 case 72: return 0xb; 2097 case 96: return 0x1; 2098 case 108: return 0x3; 2099 case 2: return 10; 2100 case 4: return 20; 2101 case 11: return 55; 2102 case 22: return 110; 2103 } 2104 return 0; 2105 } 2106 2107 static void 2108 iwn_newassoc(struct ieee80211_node *ni, int isnew) 2109 { 2110 #define RV(v) ((v) & IEEE80211_RATE_VAL) 2111 struct ieee80211com *ic = ni->ni_ic; 2112 struct iwn_softc *sc = ic->ic_ifp->if_softc; 2113 struct iwn_node *wn = (void *)ni; 2114 uint8_t txant1, txant2; 2115 int i, plcp, rate, ridx; 2116 2117 /* Use the first valid TX antenna. */ 2118 txant1 = IWN_LSB(sc->txchainmask); 2119 txant2 = IWN_LSB(sc->txchainmask & ~txant1); 2120 2121 if (IEEE80211_IS_CHAN_HT(ni->ni_chan)) { 2122 ridx = ni->ni_rates.rs_nrates - 1; 2123 for (i = ni->ni_htrates.rs_nrates - 1; i >= 0; i--) { 2124 plcp = RV(ni->ni_htrates.rs_rates[i]) | IWN_RFLAG_MCS; 2125 if (IEEE80211_IS_CHAN_HT40(ni->ni_chan)) { 2126 plcp |= IWN_RFLAG_HT40; 2127 if (ni->ni_htcap & IEEE80211_HTCAP_SHORTGI40) 2128 plcp |= IWN_RFLAG_SGI; 2129 } else if (ni->ni_htcap & IEEE80211_HTCAP_SHORTGI20) 2130 plcp |= IWN_RFLAG_SGI; 2131 if (RV(ni->ni_htrates.rs_rates[i]) > 7) 2132 plcp |= IWN_RFLAG_ANT(txant1 | txant2); 2133 else 2134 plcp |= IWN_RFLAG_ANT(txant1); 2135 if (ridx >= 0) { 2136 rate = RV(ni->ni_rates.rs_rates[ridx]); 2137 wn->ridx[rate] = plcp; 2138 } 2139 wn->ridx[IEEE80211_RATE_MCS | i] = plcp; 2140 ridx--; 2141 } 2142 } else { 2143 for (i = 0; i < ni->ni_rates.rs_nrates; i++) { 2144 rate = RV(ni->ni_rates.rs_rates[i]); 2145 plcp = rate2plcp(rate); 2146 ridx = ic->ic_rt->rateCodeToIndex[rate]; 2147 if (ridx < IWN_RIDX_OFDM6 && 2148 IEEE80211_IS_CHAN_2GHZ(ni->ni_chan)) 2149 plcp |= IWN_RFLAG_CCK; 2150 plcp |= IWN_RFLAG_ANT(txant1); 2151 wn->ridx[rate] = htole32(plcp); 2152 } 2153 } 2154 #undef RV 2155 } 2156 2157 static int 2158 iwn_media_change(struct ifnet *ifp) 2159 { 2160 int error; 2161 2162 error = ieee80211_media_change(ifp); 2163 /* NB: only the fixed rate can change and that doesn't need a reset */ 2164 return (error == ENETRESET ? 0 : error); 2165 } 2166 2167 static int 2168 iwn_newstate(struct ieee80211vap *vap, enum ieee80211_state nstate, int arg) 2169 { 2170 struct iwn_vap *ivp = IWN_VAP(vap); 2171 struct ieee80211com *ic = vap->iv_ic; 2172 struct iwn_softc *sc = ic->ic_ifp->if_softc; 2173 int error = 0; 2174 2175 DPRINTF(sc, IWN_DEBUG_STATE, "%s: %s -> %s\n", __func__, 2176 ieee80211_state_name[vap->iv_state], ieee80211_state_name[nstate]); 2177 2178 IEEE80211_UNLOCK(ic); 2179 IWN_LOCK(sc); 2180 callout_stop(&sc->calib_to); 2181 2182 switch (nstate) { 2183 case IEEE80211_S_ASSOC: 2184 if (vap->iv_state != IEEE80211_S_RUN) 2185 break; 2186 /* FALLTHROUGH */ 2187 case IEEE80211_S_AUTH: 2188 if (vap->iv_state == IEEE80211_S_AUTH) 2189 break; 2190 2191 /* 2192 * !AUTH -> AUTH transition requires state reset to handle 2193 * reassociations correctly. 2194 */ 2195 sc->rxon.associd = 0; 2196 sc->rxon.filter &= ~htole32(IWN_FILTER_BSS); 2197 sc->calib.state = IWN_CALIB_STATE_INIT; 2198 2199 if ((error = iwn_auth(sc, vap)) != 0) { 2200 device_printf(sc->sc_dev, 2201 "%s: could not move to auth state\n", __func__); 2202 } 2203 break; 2204 2205 case IEEE80211_S_RUN: 2206 /* 2207 * RUN -> RUN transition; Just restart the timers. 2208 */ 2209 if (vap->iv_state == IEEE80211_S_RUN) { 2210 sc->calib_cnt = 0; 2211 break; 2212 } 2213 2214 /* 2215 * !RUN -> RUN requires setting the association id 2216 * which is done with a firmware cmd. We also defer 2217 * starting the timers until that work is done. 2218 */ 2219 if ((error = iwn_run(sc, vap)) != 0) { 2220 device_printf(sc->sc_dev, 2221 "%s: could not move to run state\n", __func__); 2222 } 2223 break; 2224 2225 case IEEE80211_S_INIT: 2226 sc->calib.state = IWN_CALIB_STATE_INIT; 2227 break; 2228 2229 default: 2230 break; 2231 } 2232 IWN_UNLOCK(sc); 2233 IEEE80211_LOCK(ic); 2234 if (error != 0) 2235 return error; 2236 return ivp->iv_newstate(vap, nstate, arg); 2237 } 2238 2239 static void 2240 iwn_calib_timeout(void *arg) 2241 { 2242 struct iwn_softc *sc = arg; 2243 2244 IWN_LOCK_ASSERT(sc); 2245 2246 /* Force automatic TX power calibration every 60 secs. */ 2247 if (++sc->calib_cnt >= 120) { 2248 uint32_t flags = 0; 2249 2250 DPRINTF(sc, IWN_DEBUG_CALIBRATE, "%s\n", 2251 "sending request for statistics"); 2252 (void)iwn_cmd(sc, IWN_CMD_GET_STATISTICS, &flags, 2253 sizeof flags, 1); 2254 sc->calib_cnt = 0; 2255 } 2256 callout_reset(&sc->calib_to, msecs_to_ticks(500), iwn_calib_timeout, 2257 sc); 2258 } 2259 2260 /* 2261 * Process an RX_PHY firmware notification. This is usually immediately 2262 * followed by an MPDU_RX_DONE notification. 2263 */ 2264 static void 2265 iwn_rx_phy(struct iwn_softc *sc, struct iwn_rx_desc *desc, 2266 struct iwn_rx_data *data) 2267 { 2268 struct iwn_rx_stat *stat = (struct iwn_rx_stat *)(desc + 1); 2269 2270 DPRINTF(sc, IWN_DEBUG_CALIBRATE, "%s: received PHY stats\n", __func__); 2271 bus_dmamap_sync(sc->rxq.data_dmat, data->map, BUS_DMASYNC_POSTREAD); 2272 2273 /* Save RX statistics, they will be used on MPDU_RX_DONE. */ 2274 memcpy(&sc->last_rx_stat, stat, sizeof (*stat)); 2275 sc->last_rx_valid = 1; 2276 } 2277 2278 /* 2279 * Process an RX_DONE (4965AGN only) or MPDU_RX_DONE firmware notification. 2280 * Each MPDU_RX_DONE notification must be preceded by an RX_PHY one. 2281 */ 2282 static void 2283 iwn_rx_done(struct iwn_softc *sc, struct iwn_rx_desc *desc, 2284 struct iwn_rx_data *data) 2285 { 2286 struct iwn_ops *ops = &sc->ops; 2287 struct ifnet *ifp = sc->sc_ifp; 2288 struct ieee80211com *ic = ifp->if_l2com; 2289 struct iwn_rx_ring *ring = &sc->rxq; 2290 struct ieee80211_frame *wh; 2291 struct ieee80211_node *ni; 2292 struct mbuf *m, *m1; 2293 struct iwn_rx_stat *stat; 2294 caddr_t head; 2295 bus_addr_t paddr; 2296 uint32_t flags; 2297 int error, len, rssi, nf; 2298 2299 if (desc->type == IWN_MPDU_RX_DONE) { 2300 /* Check for prior RX_PHY notification. */ 2301 if (!sc->last_rx_valid) { 2302 DPRINTF(sc, IWN_DEBUG_ANY, 2303 "%s: missing RX_PHY\n", __func__); 2304 return; 2305 } 2306 stat = &sc->last_rx_stat; 2307 } else 2308 stat = (struct iwn_rx_stat *)(desc + 1); 2309 2310 bus_dmamap_sync(ring->data_dmat, data->map, BUS_DMASYNC_POSTREAD); 2311 2312 if (stat->cfg_phy_len > IWN_STAT_MAXLEN) { 2313 device_printf(sc->sc_dev, 2314 "%s: invalid RX statistic header, len %d\n", __func__, 2315 stat->cfg_phy_len); 2316 return; 2317 } 2318 if (desc->type == IWN_MPDU_RX_DONE) { 2319 struct iwn_rx_mpdu *mpdu = (struct iwn_rx_mpdu *)(desc + 1); 2320 head = (caddr_t)(mpdu + 1); 2321 len = le16toh(mpdu->len); 2322 } else { 2323 head = (caddr_t)(stat + 1) + stat->cfg_phy_len; 2324 len = le16toh(stat->len); 2325 } 2326 2327 flags = le32toh(*(uint32_t *)(head + len)); 2328 2329 /* Discard frames with a bad FCS early. */ 2330 if ((flags & IWN_RX_NOERROR) != IWN_RX_NOERROR) { 2331 DPRINTF(sc, IWN_DEBUG_RECV, "%s: RX flags error %x\n", 2332 __func__, flags); 2333 ifp->if_ierrors++; 2334 return; 2335 } 2336 /* Discard frames that are too short. */ 2337 if (len < sizeof (*wh)) { 2338 DPRINTF(sc, IWN_DEBUG_RECV, "%s: frame too short: %d\n", 2339 __func__, len); 2340 ifp->if_ierrors++; 2341 return; 2342 } 2343 2344 m1 = m_getjcl(M_DONTWAIT, MT_DATA, M_PKTHDR, IWN_RBUF_SIZE); 2345 if (m1 == NULL) { 2346 DPRINTF(sc, IWN_DEBUG_ANY, "%s: no mbuf to restock ring\n", 2347 __func__); 2348 ifp->if_ierrors++; 2349 return; 2350 } 2351 bus_dmamap_unload(ring->data_dmat, data->map); 2352 2353 error = bus_dmamap_load(ring->data_dmat, data->map, mtod(m1, void *), 2354 IWN_RBUF_SIZE, iwn_dma_map_addr, &paddr, BUS_DMA_NOWAIT); 2355 if (error != 0 && error != EFBIG) { 2356 device_printf(sc->sc_dev, 2357 "%s: bus_dmamap_load failed, error %d\n", __func__, error); 2358 m_freem(m1); 2359 2360 /* Try to reload the old mbuf. */ 2361 error = bus_dmamap_load(ring->data_dmat, data->map, 2362 mtod(data->m, void *), IWN_RBUF_SIZE, iwn_dma_map_addr, 2363 &paddr, BUS_DMA_NOWAIT); 2364 if (error != 0 && error != EFBIG) { 2365 panic("%s: could not load old RX mbuf", __func__); 2366 } 2367 /* Physical address may have changed. */ 2368 ring->desc[ring->cur] = htole32(paddr >> 8); 2369 bus_dmamap_sync(ring->data_dmat, ring->desc_dma.map, 2370 BUS_DMASYNC_PREWRITE); 2371 ifp->if_ierrors++; 2372 return; 2373 } 2374 2375 m = data->m; 2376 data->m = m1; 2377 /* Update RX descriptor. */ 2378 ring->desc[ring->cur] = htole32(paddr >> 8); 2379 bus_dmamap_sync(ring->desc_dma.tag, ring->desc_dma.map, 2380 BUS_DMASYNC_PREWRITE); 2381 2382 /* Finalize mbuf. */ 2383 m->m_pkthdr.rcvif = ifp; 2384 m->m_data = head; 2385 m->m_pkthdr.len = m->m_len = len; 2386 2387 /* Grab a reference to the source node. */ 2388 wh = mtod(m, struct ieee80211_frame *); 2389 ni = ieee80211_find_rxnode(ic, (struct ieee80211_frame_min *)wh); 2390 nf = (ni != NULL && ni->ni_vap->iv_state == IEEE80211_S_RUN && 2391 (ic->ic_flags & IEEE80211_F_SCAN) == 0) ? sc->noise : -95; 2392 2393 rssi = ops->get_rssi(sc, stat); 2394 2395 if (ieee80211_radiotap_active(ic)) { 2396 struct iwn_rx_radiotap_header *tap = &sc->sc_rxtap; 2397 2398 tap->wr_flags = 0; 2399 if (stat->flags & htole16(IWN_STAT_FLAG_SHPREAMBLE)) 2400 tap->wr_flags |= IEEE80211_RADIOTAP_F_SHORTPRE; 2401 tap->wr_dbm_antsignal = (int8_t)rssi; 2402 tap->wr_dbm_antnoise = (int8_t)nf; 2403 tap->wr_tsft = stat->tstamp; 2404 switch (stat->rate) { 2405 /* CCK rates. */ 2406 case 10: tap->wr_rate = 2; break; 2407 case 20: tap->wr_rate = 4; break; 2408 case 55: tap->wr_rate = 11; break; 2409 case 110: tap->wr_rate = 22; break; 2410 /* OFDM rates. */ 2411 case 0xd: tap->wr_rate = 12; break; 2412 case 0xf: tap->wr_rate = 18; break; 2413 case 0x5: tap->wr_rate = 24; break; 2414 case 0x7: tap->wr_rate = 36; break; 2415 case 0x9: tap->wr_rate = 48; break; 2416 case 0xb: tap->wr_rate = 72; break; 2417 case 0x1: tap->wr_rate = 96; break; 2418 case 0x3: tap->wr_rate = 108; break; 2419 /* Unknown rate: should not happen. */ 2420 default: tap->wr_rate = 0; 2421 } 2422 } 2423 2424 IWN_UNLOCK(sc); 2425 2426 /* Send the frame to the 802.11 layer. */ 2427 if (ni != NULL) { 2428 if (ni->ni_flags & IEEE80211_NODE_HT) 2429 m->m_flags |= M_AMPDU; 2430 (void)ieee80211_input(ni, m, rssi - nf, nf); 2431 /* Node is no longer needed. */ 2432 ieee80211_free_node(ni); 2433 } else 2434 (void)ieee80211_input_all(ic, m, rssi - nf, nf); 2435 2436 IWN_LOCK(sc); 2437 } 2438 2439 /* Process an incoming Compressed BlockAck. */ 2440 static void 2441 iwn_rx_compressed_ba(struct iwn_softc *sc, struct iwn_rx_desc *desc, 2442 struct iwn_rx_data *data) 2443 { 2444 struct ifnet *ifp = sc->sc_ifp; 2445 struct iwn_node *wn; 2446 struct ieee80211_node *ni; 2447 struct iwn_compressed_ba *ba = (struct iwn_compressed_ba *)(desc + 1); 2448 struct iwn_tx_ring *txq; 2449 struct ieee80211_tx_ampdu *tap; 2450 uint64_t bitmap; 2451 uint8_t tid; 2452 int ackfailcnt = 0, i, shift; 2453 2454 bus_dmamap_sync(sc->rxq.data_dmat, data->map, BUS_DMASYNC_POSTREAD); 2455 2456 txq = &sc->txq[le16toh(ba->qid)]; 2457 tap = sc->qid2tap[le16toh(ba->qid)]; 2458 tid = WME_AC_TO_TID(tap->txa_ac); 2459 ni = tap->txa_ni; 2460 wn = (void *)ni; 2461 2462 if (wn->agg[tid].bitmap == 0) 2463 return; 2464 2465 shift = wn->agg[tid].startidx - ((le16toh(ba->seq) >> 4) & 0xff); 2466 if (shift < 0) 2467 shift += 0x100; 2468 2469 if (wn->agg[tid].nframes > (64 - shift)) 2470 return; 2471 2472 bitmap = (le64toh(ba->bitmap) >> shift) & wn->agg[tid].bitmap; 2473 for (i = 0; bitmap; i++) { 2474 if ((bitmap & 1) == 0) { 2475 ifp->if_oerrors++; 2476 ieee80211_ratectl_tx_complete(ni->ni_vap, ni, 2477 IEEE80211_RATECTL_TX_FAILURE, &ackfailcnt, NULL); 2478 } else { 2479 ifp->if_opackets++; 2480 ieee80211_ratectl_tx_complete(ni->ni_vap, ni, 2481 IEEE80211_RATECTL_TX_SUCCESS, &ackfailcnt, NULL); 2482 } 2483 bitmap >>= 1; 2484 } 2485 } 2486 2487 /* 2488 * Process a CALIBRATION_RESULT notification sent by the initialization 2489 * firmware on response to a CMD_CALIB_CONFIG command (5000 only). 2490 */ 2491 static void 2492 iwn5000_rx_calib_results(struct iwn_softc *sc, struct iwn_rx_desc *desc, 2493 struct iwn_rx_data *data) 2494 { 2495 struct iwn_phy_calib *calib = (struct iwn_phy_calib *)(desc + 1); 2496 int len, idx = -1; 2497 2498 /* Runtime firmware should not send such a notification. */ 2499 if (sc->sc_flags & IWN_FLAG_CALIB_DONE) 2500 return; 2501 2502 len = (le32toh(desc->len) & 0x3fff) - 4; 2503 bus_dmamap_sync(sc->rxq.data_dmat, data->map, BUS_DMASYNC_POSTREAD); 2504 2505 switch (calib->code) { 2506 case IWN5000_PHY_CALIB_DC: 2507 if ((sc->sc_flags & IWN_FLAG_INTERNAL_PA) == 0 && 2508 (sc->hw_type == IWN_HW_REV_TYPE_5150 || 2509 sc->hw_type >= IWN_HW_REV_TYPE_6000) && 2510 sc->hw_type != IWN_HW_REV_TYPE_6050) 2511 idx = 0; 2512 break; 2513 case IWN5000_PHY_CALIB_LO: 2514 idx = 1; 2515 break; 2516 case IWN5000_PHY_CALIB_TX_IQ: 2517 idx = 2; 2518 break; 2519 case IWN5000_PHY_CALIB_TX_IQ_PERIODIC: 2520 if (sc->hw_type < IWN_HW_REV_TYPE_6000 && 2521 sc->hw_type != IWN_HW_REV_TYPE_5150) 2522 idx = 3; 2523 break; 2524 case IWN5000_PHY_CALIB_BASE_BAND: 2525 idx = 4; 2526 break; 2527 } 2528 if (idx == -1) /* Ignore other results. */ 2529 return; 2530 2531 /* Save calibration result. */ 2532 if (sc->calibcmd[idx].buf != NULL) 2533 free(sc->calibcmd[idx].buf, M_DEVBUF); 2534 sc->calibcmd[idx].buf = malloc(len, M_DEVBUF, M_NOWAIT); 2535 if (sc->calibcmd[idx].buf == NULL) { 2536 DPRINTF(sc, IWN_DEBUG_CALIBRATE, 2537 "not enough memory for calibration result %d\n", 2538 calib->code); 2539 return; 2540 } 2541 DPRINTF(sc, IWN_DEBUG_CALIBRATE, 2542 "saving calibration result code=%d len=%d\n", calib->code, len); 2543 sc->calibcmd[idx].len = len; 2544 memcpy(sc->calibcmd[idx].buf, calib, len); 2545 } 2546 2547 /* 2548 * Process an RX_STATISTICS or BEACON_STATISTICS firmware notification. 2549 * The latter is sent by the firmware after each received beacon. 2550 */ 2551 static void 2552 iwn_rx_statistics(struct iwn_softc *sc, struct iwn_rx_desc *desc, 2553 struct iwn_rx_data *data) 2554 { 2555 struct iwn_ops *ops = &sc->ops; 2556 struct ifnet *ifp = sc->sc_ifp; 2557 struct ieee80211com *ic = ifp->if_l2com; 2558 struct ieee80211vap *vap = TAILQ_FIRST(&ic->ic_vaps); 2559 struct iwn_calib_state *calib = &sc->calib; 2560 struct iwn_stats *stats = (struct iwn_stats *)(desc + 1); 2561 int temp; 2562 2563 /* Ignore statistics received during a scan. */ 2564 if (vap->iv_state != IEEE80211_S_RUN || 2565 (ic->ic_flags & IEEE80211_F_SCAN)) 2566 return; 2567 2568 bus_dmamap_sync(sc->rxq.data_dmat, data->map, BUS_DMASYNC_POSTREAD); 2569 2570 DPRINTF(sc, IWN_DEBUG_CALIBRATE, "%s: received statistics, cmd %d\n", 2571 __func__, desc->type); 2572 sc->calib_cnt = 0; /* Reset TX power calibration timeout. */ 2573 2574 /* Test if temperature has changed. */ 2575 if (stats->general.temp != sc->rawtemp) { 2576 /* Convert "raw" temperature to degC. */ 2577 sc->rawtemp = stats->general.temp; 2578 temp = ops->get_temperature(sc); 2579 DPRINTF(sc, IWN_DEBUG_CALIBRATE, "%s: temperature %d\n", 2580 __func__, temp); 2581 2582 /* Update TX power if need be (4965AGN only). */ 2583 if (sc->hw_type == IWN_HW_REV_TYPE_4965) 2584 iwn4965_power_calibration(sc, temp); 2585 } 2586 2587 if (desc->type != IWN_BEACON_STATISTICS) 2588 return; /* Reply to a statistics request. */ 2589 2590 sc->noise = iwn_get_noise(&stats->rx.general); 2591 DPRINTF(sc, IWN_DEBUG_CALIBRATE, "%s: noise %d\n", __func__, sc->noise); 2592 2593 /* Test that RSSI and noise are present in stats report. */ 2594 if (le32toh(stats->rx.general.flags) != 1) { 2595 DPRINTF(sc, IWN_DEBUG_ANY, "%s\n", 2596 "received statistics without RSSI"); 2597 return; 2598 } 2599 2600 if (calib->state == IWN_CALIB_STATE_ASSOC) 2601 iwn_collect_noise(sc, &stats->rx.general); 2602 else if (calib->state == IWN_CALIB_STATE_RUN) 2603 iwn_tune_sensitivity(sc, &stats->rx); 2604 } 2605 2606 /* 2607 * Process a TX_DONE firmware notification. Unfortunately, the 4965AGN 2608 * and 5000 adapters have different incompatible TX status formats. 2609 */ 2610 static void 2611 iwn4965_tx_done(struct iwn_softc *sc, struct iwn_rx_desc *desc, 2612 struct iwn_rx_data *data) 2613 { 2614 struct iwn4965_tx_stat *stat = (struct iwn4965_tx_stat *)(desc + 1); 2615 struct iwn_tx_ring *ring; 2616 int qid; 2617 2618 qid = desc->qid & 0xf; 2619 ring = &sc->txq[qid]; 2620 2621 DPRINTF(sc, IWN_DEBUG_XMIT, "%s: " 2622 "qid %d idx %d retries %d nkill %d rate %x duration %d status %x\n", 2623 __func__, desc->qid, desc->idx, stat->ackfailcnt, 2624 stat->btkillcnt, stat->rate, le16toh(stat->duration), 2625 le32toh(stat->status)); 2626 2627 bus_dmamap_sync(ring->data_dmat, data->map, BUS_DMASYNC_POSTREAD); 2628 if (qid >= sc->firstaggqueue) { 2629 iwn_ampdu_tx_done(sc, qid, desc->idx, stat->nframes, 2630 &stat->status); 2631 } else { 2632 iwn_tx_done(sc, desc, stat->ackfailcnt, 2633 le32toh(stat->status) & 0xff); 2634 } 2635 } 2636 2637 static void 2638 iwn5000_tx_done(struct iwn_softc *sc, struct iwn_rx_desc *desc, 2639 struct iwn_rx_data *data) 2640 { 2641 struct iwn5000_tx_stat *stat = (struct iwn5000_tx_stat *)(desc + 1); 2642 struct iwn_tx_ring *ring; 2643 int qid; 2644 2645 qid = desc->qid & 0xf; 2646 ring = &sc->txq[qid]; 2647 2648 DPRINTF(sc, IWN_DEBUG_XMIT, "%s: " 2649 "qid %d idx %d retries %d nkill %d rate %x duration %d status %x\n", 2650 __func__, desc->qid, desc->idx, stat->ackfailcnt, 2651 stat->btkillcnt, stat->rate, le16toh(stat->duration), 2652 le32toh(stat->status)); 2653 2654 #ifdef notyet 2655 /* Reset TX scheduler slot. */ 2656 iwn5000_reset_sched(sc, desc->qid & 0xf, desc->idx); 2657 #endif 2658 2659 bus_dmamap_sync(ring->data_dmat, data->map, BUS_DMASYNC_POSTREAD); 2660 if (qid >= sc->firstaggqueue) { 2661 iwn_ampdu_tx_done(sc, qid, desc->idx, stat->nframes, 2662 &stat->status); 2663 } else { 2664 iwn_tx_done(sc, desc, stat->ackfailcnt, 2665 le16toh(stat->status) & 0xff); 2666 } 2667 } 2668 2669 /* 2670 * Adapter-independent backend for TX_DONE firmware notifications. 2671 */ 2672 static void 2673 iwn_tx_done(struct iwn_softc *sc, struct iwn_rx_desc *desc, int ackfailcnt, 2674 uint8_t status) 2675 { 2676 struct ifnet *ifp = sc->sc_ifp; 2677 struct iwn_tx_ring *ring = &sc->txq[desc->qid & 0xf]; 2678 struct iwn_tx_data *data = &ring->data[desc->idx]; 2679 struct mbuf *m; 2680 struct ieee80211_node *ni; 2681 struct ieee80211vap *vap; 2682 2683 KASSERT(data->ni != NULL, ("no node")); 2684 2685 /* Unmap and free mbuf. */ 2686 bus_dmamap_sync(ring->data_dmat, data->map, BUS_DMASYNC_POSTWRITE); 2687 bus_dmamap_unload(ring->data_dmat, data->map); 2688 m = data->m, data->m = NULL; 2689 ni = data->ni, data->ni = NULL; 2690 vap = ni->ni_vap; 2691 2692 if (m->m_flags & M_TXCB) { 2693 /* 2694 * Channels marked for "radar" require traffic to be received 2695 * to unlock before we can transmit. Until traffic is seen 2696 * any attempt to transmit is returned immediately with status 2697 * set to IWN_TX_FAIL_TX_LOCKED. Unfortunately this can easily 2698 * happen on first authenticate after scanning. To workaround 2699 * this we ignore a failure of this sort in AUTH state so the 2700 * 802.11 layer will fall back to using a timeout to wait for 2701 * the AUTH reply. This allows the firmware time to see 2702 * traffic so a subsequent retry of AUTH succeeds. It's 2703 * unclear why the firmware does not maintain state for 2704 * channels recently visited as this would allow immediate 2705 * use of the channel after a scan (where we see traffic). 2706 */ 2707 if (status == IWN_TX_FAIL_TX_LOCKED && 2708 ni->ni_vap->iv_state == IEEE80211_S_AUTH) 2709 ieee80211_process_callback(ni, m, 0); 2710 else 2711 ieee80211_process_callback(ni, m, 2712 (status & IWN_TX_FAIL) != 0); 2713 } 2714 2715 /* 2716 * Update rate control statistics for the node. 2717 */ 2718 if (status & IWN_TX_FAIL) { 2719 ifp->if_oerrors++; 2720 ieee80211_ratectl_tx_complete(vap, ni, 2721 IEEE80211_RATECTL_TX_FAILURE, &ackfailcnt, NULL); 2722 } else { 2723 ifp->if_opackets++; 2724 ieee80211_ratectl_tx_complete(vap, ni, 2725 IEEE80211_RATECTL_TX_SUCCESS, &ackfailcnt, NULL); 2726 } 2727 m_freem(m); 2728 ieee80211_free_node(ni); 2729 2730 sc->sc_tx_timer = 0; 2731 if (--ring->queued < IWN_TX_RING_LOMARK) { 2732 sc->qfullmsk &= ~(1 << ring->qid); 2733 if (sc->qfullmsk == 0 && 2734 (ifp->if_drv_flags & IFF_DRV_OACTIVE)) { 2735 ifp->if_drv_flags &= ~IFF_DRV_OACTIVE; 2736 iwn_start_locked(ifp); 2737 } 2738 } 2739 } 2740 2741 /* 2742 * Process a "command done" firmware notification. This is where we wakeup 2743 * processes waiting for a synchronous command completion. 2744 */ 2745 static void 2746 iwn_cmd_done(struct iwn_softc *sc, struct iwn_rx_desc *desc) 2747 { 2748 struct iwn_tx_ring *ring = &sc->txq[4]; 2749 struct iwn_tx_data *data; 2750 2751 if ((desc->qid & 0xf) != 4) 2752 return; /* Not a command ack. */ 2753 2754 data = &ring->data[desc->idx]; 2755 2756 /* If the command was mapped in an mbuf, free it. */ 2757 if (data->m != NULL) { 2758 bus_dmamap_sync(ring->data_dmat, data->map, 2759 BUS_DMASYNC_POSTWRITE); 2760 bus_dmamap_unload(ring->data_dmat, data->map); 2761 m_freem(data->m); 2762 data->m = NULL; 2763 } 2764 wakeup(&ring->desc[desc->idx]); 2765 } 2766 2767 static void 2768 iwn_ampdu_tx_done(struct iwn_softc *sc, int qid, int idx, int nframes, 2769 void *stat) 2770 { 2771 struct ifnet *ifp = sc->sc_ifp; 2772 struct iwn_tx_ring *ring = &sc->txq[qid]; 2773 struct iwn_tx_data *data; 2774 struct mbuf *m; 2775 struct iwn_node *wn; 2776 struct ieee80211_node *ni; 2777 struct ieee80211vap *vap; 2778 struct ieee80211_tx_ampdu *tap; 2779 uint64_t bitmap; 2780 uint32_t *status = stat; 2781 uint16_t *aggstatus = stat; 2782 uint8_t tid; 2783 int bit, i, lastidx, seqno, shift, start; 2784 2785 #ifdef NOT_YET 2786 if (nframes == 1) { 2787 if ((*status & 0xff) != 1 && (*status & 0xff) != 2) 2788 printf("ieee80211_send_bar()\n"); 2789 } 2790 #endif 2791 2792 bitmap = 0; 2793 start = idx; 2794 for (i = 0; i < nframes; i++) { 2795 if (le16toh(aggstatus[i * 2]) & 0xc) 2796 continue; 2797 2798 idx = le16toh(aggstatus[2*i + 1]) & 0xff; 2799 bit = idx - start; 2800 shift = 0; 2801 if (bit >= 64) { 2802 shift = 0x100 - idx + start; 2803 bit = 0; 2804 start = idx; 2805 } else if (bit <= -64) 2806 bit = 0x100 - start + idx; 2807 else if (bit < 0) { 2808 shift = start - idx; 2809 start = idx; 2810 bit = 0; 2811 } 2812 bitmap = bitmap << shift; 2813 bitmap |= 1ULL << bit; 2814 } 2815 tap = sc->qid2tap[qid]; 2816 if (tap != NULL) { 2817 tid = WME_AC_TO_TID(tap->txa_ac); 2818 wn = (void *)tap->txa_ni; 2819 wn->agg[tid].bitmap = bitmap; 2820 wn->agg[tid].startidx = start; 2821 wn->agg[tid].nframes = nframes; 2822 } 2823 2824 seqno = le32toh(*(status + nframes)) & 0xfff; 2825 for (lastidx = (seqno & 0xff); ring->read != lastidx;) { 2826 data = &ring->data[ring->read]; 2827 2828 KASSERT(data->ni != NULL, ("no node")); 2829 2830 /* Unmap and free mbuf. */ 2831 bus_dmamap_sync(ring->data_dmat, data->map, 2832 BUS_DMASYNC_POSTWRITE); 2833 bus_dmamap_unload(ring->data_dmat, data->map); 2834 m = data->m, data->m = NULL; 2835 ni = data->ni, data->ni = NULL; 2836 vap = ni->ni_vap; 2837 2838 if (m->m_flags & M_TXCB) 2839 ieee80211_process_callback(ni, m, 1); 2840 2841 m_freem(m); 2842 ieee80211_free_node(ni); 2843 2844 ring->queued--; 2845 ring->read = (ring->read + 1) % IWN_TX_RING_COUNT; 2846 } 2847 2848 sc->sc_tx_timer = 0; 2849 if (ring->queued < IWN_TX_RING_LOMARK) { 2850 sc->qfullmsk &= ~(1 << ring->qid); 2851 if (sc->qfullmsk == 0 && 2852 (ifp->if_drv_flags & IFF_DRV_OACTIVE)) { 2853 ifp->if_drv_flags &= ~IFF_DRV_OACTIVE; 2854 iwn_start_locked(ifp); 2855 } 2856 } 2857 } 2858 2859 /* 2860 * Process an INT_FH_RX or INT_SW_RX interrupt. 2861 */ 2862 static void 2863 iwn_notif_intr(struct iwn_softc *sc) 2864 { 2865 struct iwn_ops *ops = &sc->ops; 2866 struct ifnet *ifp = sc->sc_ifp; 2867 struct ieee80211com *ic = ifp->if_l2com; 2868 struct ieee80211vap *vap = TAILQ_FIRST(&ic->ic_vaps); 2869 uint16_t hw; 2870 2871 bus_dmamap_sync(sc->rxq.stat_dma.tag, sc->rxq.stat_dma.map, 2872 BUS_DMASYNC_POSTREAD); 2873 2874 hw = le16toh(sc->rxq.stat->closed_count) & 0xfff; 2875 while (sc->rxq.cur != hw) { 2876 struct iwn_rx_data *data = &sc->rxq.data[sc->rxq.cur]; 2877 struct iwn_rx_desc *desc; 2878 2879 bus_dmamap_sync(sc->rxq.data_dmat, data->map, 2880 BUS_DMASYNC_POSTREAD); 2881 desc = mtod(data->m, struct iwn_rx_desc *); 2882 2883 DPRINTF(sc, IWN_DEBUG_RECV, 2884 "%s: qid %x idx %d flags %x type %d(%s) len %d\n", 2885 __func__, desc->qid & 0xf, desc->idx, desc->flags, 2886 desc->type, iwn_intr_str(desc->type), 2887 le16toh(desc->len)); 2888 2889 if (!(desc->qid & 0x80)) /* Reply to a command. */ 2890 iwn_cmd_done(sc, desc); 2891 2892 switch (desc->type) { 2893 case IWN_RX_PHY: 2894 iwn_rx_phy(sc, desc, data); 2895 break; 2896 2897 case IWN_RX_DONE: /* 4965AGN only. */ 2898 case IWN_MPDU_RX_DONE: 2899 /* An 802.11 frame has been received. */ 2900 iwn_rx_done(sc, desc, data); 2901 break; 2902 2903 case IWN_RX_COMPRESSED_BA: 2904 /* A Compressed BlockAck has been received. */ 2905 iwn_rx_compressed_ba(sc, desc, data); 2906 break; 2907 2908 case IWN_TX_DONE: 2909 /* An 802.11 frame has been transmitted. */ 2910 ops->tx_done(sc, desc, data); 2911 break; 2912 2913 case IWN_RX_STATISTICS: 2914 case IWN_BEACON_STATISTICS: 2915 iwn_rx_statistics(sc, desc, data); 2916 break; 2917 2918 case IWN_BEACON_MISSED: 2919 { 2920 struct iwn_beacon_missed *miss = 2921 (struct iwn_beacon_missed *)(desc + 1); 2922 int misses; 2923 2924 bus_dmamap_sync(sc->rxq.data_dmat, data->map, 2925 BUS_DMASYNC_POSTREAD); 2926 misses = le32toh(miss->consecutive); 2927 2928 DPRINTF(sc, IWN_DEBUG_STATE, 2929 "%s: beacons missed %d/%d\n", __func__, 2930 misses, le32toh(miss->total)); 2931 /* 2932 * If more than 5 consecutive beacons are missed, 2933 * reinitialize the sensitivity state machine. 2934 */ 2935 if (vap->iv_state == IEEE80211_S_RUN && 2936 (ic->ic_flags & IEEE80211_F_SCAN) == 0) { 2937 if (misses > 5) 2938 (void)iwn_init_sensitivity(sc); 2939 if (misses >= vap->iv_bmissthreshold) { 2940 IWN_UNLOCK(sc); 2941 ieee80211_beacon_miss(ic); 2942 IWN_LOCK(sc); 2943 } 2944 } 2945 break; 2946 } 2947 case IWN_UC_READY: 2948 { 2949 struct iwn_ucode_info *uc = 2950 (struct iwn_ucode_info *)(desc + 1); 2951 2952 /* The microcontroller is ready. */ 2953 bus_dmamap_sync(sc->rxq.data_dmat, data->map, 2954 BUS_DMASYNC_POSTREAD); 2955 DPRINTF(sc, IWN_DEBUG_RESET, 2956 "microcode alive notification version=%d.%d " 2957 "subtype=%x alive=%x\n", uc->major, uc->minor, 2958 uc->subtype, le32toh(uc->valid)); 2959 2960 if (le32toh(uc->valid) != 1) { 2961 device_printf(sc->sc_dev, 2962 "microcontroller initialization failed"); 2963 break; 2964 } 2965 if (uc->subtype == IWN_UCODE_INIT) { 2966 /* Save microcontroller report. */ 2967 memcpy(&sc->ucode_info, uc, sizeof (*uc)); 2968 } 2969 /* Save the address of the error log in SRAM. */ 2970 sc->errptr = le32toh(uc->errptr); 2971 break; 2972 } 2973 case IWN_STATE_CHANGED: 2974 { 2975 uint32_t *status = (uint32_t *)(desc + 1); 2976 2977 /* 2978 * State change allows hardware switch change to be 2979 * noted. However, we handle this in iwn_intr as we 2980 * get both the enable/disble intr. 2981 */ 2982 bus_dmamap_sync(sc->rxq.data_dmat, data->map, 2983 BUS_DMASYNC_POSTREAD); 2984 DPRINTF(sc, IWN_DEBUG_INTR, "state changed to %x\n", 2985 le32toh(*status)); 2986 break; 2987 } 2988 case IWN_START_SCAN: 2989 { 2990 struct iwn_start_scan *scan = 2991 (struct iwn_start_scan *)(desc + 1); 2992 2993 bus_dmamap_sync(sc->rxq.data_dmat, data->map, 2994 BUS_DMASYNC_POSTREAD); 2995 DPRINTF(sc, IWN_DEBUG_ANY, 2996 "%s: scanning channel %d status %x\n", 2997 __func__, scan->chan, le32toh(scan->status)); 2998 break; 2999 } 3000 case IWN_STOP_SCAN: 3001 { 3002 struct iwn_stop_scan *scan = 3003 (struct iwn_stop_scan *)(desc + 1); 3004 3005 bus_dmamap_sync(sc->rxq.data_dmat, data->map, 3006 BUS_DMASYNC_POSTREAD); 3007 DPRINTF(sc, IWN_DEBUG_STATE, 3008 "scan finished nchan=%d status=%d chan=%d\n", 3009 scan->nchan, scan->status, scan->chan); 3010 3011 IWN_UNLOCK(sc); 3012 ieee80211_scan_next(vap); 3013 IWN_LOCK(sc); 3014 break; 3015 } 3016 case IWN5000_CALIBRATION_RESULT: 3017 iwn5000_rx_calib_results(sc, desc, data); 3018 break; 3019 3020 case IWN5000_CALIBRATION_DONE: 3021 sc->sc_flags |= IWN_FLAG_CALIB_DONE; 3022 wakeup(sc); 3023 break; 3024 } 3025 3026 sc->rxq.cur = (sc->rxq.cur + 1) % IWN_RX_RING_COUNT; 3027 } 3028 3029 /* Tell the firmware what we have processed. */ 3030 hw = (hw == 0) ? IWN_RX_RING_COUNT - 1 : hw - 1; 3031 IWN_WRITE(sc, IWN_FH_RX_WPTR, hw & ~7); 3032 } 3033 3034 /* 3035 * Process an INT_WAKEUP interrupt raised when the microcontroller wakes up 3036 * from power-down sleep mode. 3037 */ 3038 static void 3039 iwn_wakeup_intr(struct iwn_softc *sc) 3040 { 3041 int qid; 3042 3043 DPRINTF(sc, IWN_DEBUG_RESET, "%s: ucode wakeup from power-down sleep\n", 3044 __func__); 3045 3046 /* Wakeup RX and TX rings. */ 3047 IWN_WRITE(sc, IWN_FH_RX_WPTR, sc->rxq.cur & ~7); 3048 for (qid = 0; qid < sc->ntxqs; qid++) { 3049 struct iwn_tx_ring *ring = &sc->txq[qid]; 3050 IWN_WRITE(sc, IWN_HBUS_TARG_WRPTR, qid << 8 | ring->cur); 3051 } 3052 } 3053 3054 static void 3055 iwn_rftoggle_intr(struct iwn_softc *sc) 3056 { 3057 struct ifnet *ifp = sc->sc_ifp; 3058 struct ieee80211com *ic = ifp->if_l2com; 3059 uint32_t tmp = IWN_READ(sc, IWN_GP_CNTRL); 3060 3061 IWN_LOCK_ASSERT(sc); 3062 3063 device_printf(sc->sc_dev, "RF switch: radio %s\n", 3064 (tmp & IWN_GP_CNTRL_RFKILL) ? "enabled" : "disabled"); 3065 if (tmp & IWN_GP_CNTRL_RFKILL) 3066 ieee80211_runtask(ic, &sc->sc_radioon_task); 3067 else 3068 ieee80211_runtask(ic, &sc->sc_radiooff_task); 3069 } 3070 3071 /* 3072 * Dump the error log of the firmware when a firmware panic occurs. Although 3073 * we can't debug the firmware because it is neither open source nor free, it 3074 * can help us to identify certain classes of problems. 3075 */ 3076 static void 3077 iwn_fatal_intr(struct iwn_softc *sc) 3078 { 3079 struct iwn_fw_dump dump; 3080 int i; 3081 3082 IWN_LOCK_ASSERT(sc); 3083 3084 /* Force a complete recalibration on next init. */ 3085 sc->sc_flags &= ~IWN_FLAG_CALIB_DONE; 3086 3087 /* Check that the error log address is valid. */ 3088 if (sc->errptr < IWN_FW_DATA_BASE || 3089 sc->errptr + sizeof (dump) > 3090 IWN_FW_DATA_BASE + sc->fw_data_maxsz) { 3091 printf("%s: bad firmware error log address 0x%08x\n", __func__, 3092 sc->errptr); 3093 return; 3094 } 3095 if (iwn_nic_lock(sc) != 0) { 3096 printf("%s: could not read firmware error log\n", __func__); 3097 return; 3098 } 3099 /* Read firmware error log from SRAM. */ 3100 iwn_mem_read_region_4(sc, sc->errptr, (uint32_t *)&dump, 3101 sizeof (dump) / sizeof (uint32_t)); 3102 iwn_nic_unlock(sc); 3103 3104 if (dump.valid == 0) { 3105 printf("%s: firmware error log is empty\n", __func__); 3106 return; 3107 } 3108 printf("firmware error log:\n"); 3109 printf(" error type = \"%s\" (0x%08X)\n", 3110 (dump.id < nitems(iwn_fw_errmsg)) ? 3111 iwn_fw_errmsg[dump.id] : "UNKNOWN", 3112 dump.id); 3113 printf(" program counter = 0x%08X\n", dump.pc); 3114 printf(" source line = 0x%08X\n", dump.src_line); 3115 printf(" error data = 0x%08X%08X\n", 3116 dump.error_data[0], dump.error_data[1]); 3117 printf(" branch link = 0x%08X%08X\n", 3118 dump.branch_link[0], dump.branch_link[1]); 3119 printf(" interrupt link = 0x%08X%08X\n", 3120 dump.interrupt_link[0], dump.interrupt_link[1]); 3121 printf(" time = %u\n", dump.time[0]); 3122 3123 /* Dump driver status (TX and RX rings) while we're here. */ 3124 printf("driver status:\n"); 3125 for (i = 0; i < sc->ntxqs; i++) { 3126 struct iwn_tx_ring *ring = &sc->txq[i]; 3127 printf(" tx ring %2d: qid=%-2d cur=%-3d queued=%-3d\n", 3128 i, ring->qid, ring->cur, ring->queued); 3129 } 3130 printf(" rx ring: cur=%d\n", sc->rxq.cur); 3131 } 3132 3133 static void 3134 iwn_intr(void *arg) 3135 { 3136 struct iwn_softc *sc = arg; 3137 struct ifnet *ifp = sc->sc_ifp; 3138 uint32_t r1, r2, tmp; 3139 3140 IWN_LOCK(sc); 3141 3142 /* Disable interrupts. */ 3143 IWN_WRITE(sc, IWN_INT_MASK, 0); 3144 3145 /* Read interrupts from ICT (fast) or from registers (slow). */ 3146 if (sc->sc_flags & IWN_FLAG_USE_ICT) { 3147 tmp = 0; 3148 while (sc->ict[sc->ict_cur] != 0) { 3149 tmp |= sc->ict[sc->ict_cur]; 3150 sc->ict[sc->ict_cur] = 0; /* Acknowledge. */ 3151 sc->ict_cur = (sc->ict_cur + 1) % IWN_ICT_COUNT; 3152 } 3153 tmp = le32toh(tmp); 3154 if (tmp == 0xffffffff) /* Shouldn't happen. */ 3155 tmp = 0; 3156 else if (tmp & 0xc0000) /* Workaround a HW bug. */ 3157 tmp |= 0x8000; 3158 r1 = (tmp & 0xff00) << 16 | (tmp & 0xff); 3159 r2 = 0; /* Unused. */ 3160 } else { 3161 r1 = IWN_READ(sc, IWN_INT); 3162 if (r1 == 0xffffffff || (r1 & 0xfffffff0) == 0xa5a5a5a0) 3163 return; /* Hardware gone! */ 3164 r2 = IWN_READ(sc, IWN_FH_INT); 3165 } 3166 3167 DPRINTF(sc, IWN_DEBUG_INTR, "interrupt reg1=%x reg2=%x\n", r1, r2); 3168 3169 if (r1 == 0 && r2 == 0) 3170 goto done; /* Interrupt not for us. */ 3171 3172 /* Acknowledge interrupts. */ 3173 IWN_WRITE(sc, IWN_INT, r1); 3174 if (!(sc->sc_flags & IWN_FLAG_USE_ICT)) 3175 IWN_WRITE(sc, IWN_FH_INT, r2); 3176 3177 if (r1 & IWN_INT_RF_TOGGLED) { 3178 iwn_rftoggle_intr(sc); 3179 goto done; 3180 } 3181 if (r1 & IWN_INT_CT_REACHED) { 3182 device_printf(sc->sc_dev, "%s: critical temperature reached!\n", 3183 __func__); 3184 } 3185 if (r1 & (IWN_INT_SW_ERR | IWN_INT_HW_ERR)) { 3186 device_printf(sc->sc_dev, "%s: fatal firmware error\n", 3187 __func__); 3188 /* Dump firmware error log and stop. */ 3189 iwn_fatal_intr(sc); 3190 ifp->if_flags &= ~IFF_UP; 3191 iwn_stop_locked(sc); 3192 goto done; 3193 } 3194 if ((r1 & (IWN_INT_FH_RX | IWN_INT_SW_RX | IWN_INT_RX_PERIODIC)) || 3195 (r2 & IWN_FH_INT_RX)) { 3196 if (sc->sc_flags & IWN_FLAG_USE_ICT) { 3197 if (r1 & (IWN_INT_FH_RX | IWN_INT_SW_RX)) 3198 IWN_WRITE(sc, IWN_FH_INT, IWN_FH_INT_RX); 3199 IWN_WRITE_1(sc, IWN_INT_PERIODIC, 3200 IWN_INT_PERIODIC_DIS); 3201 iwn_notif_intr(sc); 3202 if (r1 & (IWN_INT_FH_RX | IWN_INT_SW_RX)) { 3203 IWN_WRITE_1(sc, IWN_INT_PERIODIC, 3204 IWN_INT_PERIODIC_ENA); 3205 } 3206 } else 3207 iwn_notif_intr(sc); 3208 } 3209 3210 if ((r1 & IWN_INT_FH_TX) || (r2 & IWN_FH_INT_TX)) { 3211 if (sc->sc_flags & IWN_FLAG_USE_ICT) 3212 IWN_WRITE(sc, IWN_FH_INT, IWN_FH_INT_TX); 3213 wakeup(sc); /* FH DMA transfer completed. */ 3214 } 3215 3216 if (r1 & IWN_INT_ALIVE) 3217 wakeup(sc); /* Firmware is alive. */ 3218 3219 if (r1 & IWN_INT_WAKEUP) 3220 iwn_wakeup_intr(sc); 3221 3222 done: 3223 /* Re-enable interrupts. */ 3224 if (ifp->if_flags & IFF_UP) 3225 IWN_WRITE(sc, IWN_INT_MASK, sc->int_mask); 3226 3227 IWN_UNLOCK(sc); 3228 } 3229 3230 /* 3231 * Update TX scheduler ring when transmitting an 802.11 frame (4965AGN and 3232 * 5000 adapters use a slightly different format). 3233 */ 3234 static void 3235 iwn4965_update_sched(struct iwn_softc *sc, int qid, int idx, uint8_t id, 3236 uint16_t len) 3237 { 3238 uint16_t *w = &sc->sched[qid * IWN4965_SCHED_COUNT + idx]; 3239 3240 *w = htole16(len + 8); 3241 bus_dmamap_sync(sc->sched_dma.tag, sc->sched_dma.map, 3242 BUS_DMASYNC_PREWRITE); 3243 if (idx < IWN_SCHED_WINSZ) { 3244 *(w + IWN_TX_RING_COUNT) = *w; 3245 bus_dmamap_sync(sc->sched_dma.tag, sc->sched_dma.map, 3246 BUS_DMASYNC_PREWRITE); 3247 } 3248 } 3249 3250 static void 3251 iwn5000_update_sched(struct iwn_softc *sc, int qid, int idx, uint8_t id, 3252 uint16_t len) 3253 { 3254 uint16_t *w = &sc->sched[qid * IWN5000_SCHED_COUNT + idx]; 3255 3256 *w = htole16(id << 12 | (len + 8)); 3257 bus_dmamap_sync(sc->sched_dma.tag, sc->sched_dma.map, 3258 BUS_DMASYNC_PREWRITE); 3259 if (idx < IWN_SCHED_WINSZ) { 3260 *(w + IWN_TX_RING_COUNT) = *w; 3261 bus_dmamap_sync(sc->sched_dma.tag, sc->sched_dma.map, 3262 BUS_DMASYNC_PREWRITE); 3263 } 3264 } 3265 3266 #ifdef notyet 3267 static void 3268 iwn5000_reset_sched(struct iwn_softc *sc, int qid, int idx) 3269 { 3270 uint16_t *w = &sc->sched[qid * IWN5000_SCHED_COUNT + idx]; 3271 3272 *w = (*w & htole16(0xf000)) | htole16(1); 3273 bus_dmamap_sync(sc->sched_dma.tag, sc->sched_dma.map, 3274 BUS_DMASYNC_PREWRITE); 3275 if (idx < IWN_SCHED_WINSZ) { 3276 *(w + IWN_TX_RING_COUNT) = *w; 3277 bus_dmamap_sync(sc->sched_dma.tag, sc->sched_dma.map, 3278 BUS_DMASYNC_PREWRITE); 3279 } 3280 } 3281 #endif 3282 3283 static int 3284 iwn_tx_data(struct iwn_softc *sc, struct mbuf *m, struct ieee80211_node *ni) 3285 { 3286 struct iwn_ops *ops = &sc->ops; 3287 const struct ieee80211_txparam *tp; 3288 struct ieee80211vap *vap = ni->ni_vap; 3289 struct ieee80211com *ic = ni->ni_ic; 3290 struct iwn_node *wn = (void *)ni; 3291 struct iwn_tx_ring *ring; 3292 struct iwn_tx_desc *desc; 3293 struct iwn_tx_data *data; 3294 struct iwn_tx_cmd *cmd; 3295 struct iwn_cmd_data *tx; 3296 struct ieee80211_frame *wh; 3297 struct ieee80211_key *k = NULL; 3298 struct mbuf *m1; 3299 uint32_t flags; 3300 uint16_t qos; 3301 u_int hdrlen; 3302 bus_dma_segment_t *seg, segs[IWN_MAX_SCATTER]; 3303 uint8_t tid, ridx, txant, type; 3304 int ac, i, totlen, error, pad, nsegs = 0, rate; 3305 3306 IWN_LOCK_ASSERT(sc); 3307 3308 wh = mtod(m, struct ieee80211_frame *); 3309 hdrlen = ieee80211_anyhdrsize(wh); 3310 type = wh->i_fc[0] & IEEE80211_FC0_TYPE_MASK; 3311 3312 /* Select EDCA Access Category and TX ring for this frame. */ 3313 if (IEEE80211_QOS_HAS_SEQ(wh)) { 3314 qos = ((const struct ieee80211_qosframe *)wh)->i_qos[0]; 3315 tid = qos & IEEE80211_QOS_TID; 3316 } else { 3317 qos = 0; 3318 tid = 0; 3319 } 3320 ac = M_WME_GETAC(m); 3321 3322 if (IEEE80211_QOS_HAS_SEQ(wh) && 3323 IEEE80211_AMPDU_RUNNING(&ni->ni_tx_ampdu[ac])) { 3324 struct ieee80211_tx_ampdu *tap = &ni->ni_tx_ampdu[ac]; 3325 3326 ring = &sc->txq[*(int *)tap->txa_private]; 3327 *(uint16_t *)wh->i_seq = 3328 htole16(ni->ni_txseqs[tid] << IEEE80211_SEQ_SEQ_SHIFT); 3329 ni->ni_txseqs[tid]++; 3330 } else { 3331 ring = &sc->txq[ac]; 3332 } 3333 desc = &ring->desc[ring->cur]; 3334 data = &ring->data[ring->cur]; 3335 3336 /* Choose a TX rate index. */ 3337 tp = &vap->iv_txparms[ieee80211_chan2mode(ni->ni_chan)]; 3338 if (type == IEEE80211_FC0_TYPE_MGT) 3339 rate = tp->mgmtrate; 3340 else if (IEEE80211_IS_MULTICAST(wh->i_addr1)) 3341 rate = tp->mcastrate; 3342 else if (tp->ucastrate != IEEE80211_FIXED_RATE_NONE) 3343 rate = tp->ucastrate; 3344 else { 3345 /* XXX pass pktlen */ 3346 (void) ieee80211_ratectl_rate(ni, NULL, 0); 3347 rate = ni->ni_txrate; 3348 } 3349 ridx = ic->ic_rt->rateCodeToIndex[rate]; 3350 3351 /* Encrypt the frame if need be. */ 3352 if (wh->i_fc[1] & IEEE80211_FC1_WEP) { 3353 /* Retrieve key for TX. */ 3354 k = ieee80211_crypto_encap(ni, m); 3355 if (k == NULL) { 3356 m_freem(m); 3357 return ENOBUFS; 3358 } 3359 /* 802.11 header may have moved. */ 3360 wh = mtod(m, struct ieee80211_frame *); 3361 } 3362 totlen = m->m_pkthdr.len; 3363 3364 if (ieee80211_radiotap_active_vap(vap)) { 3365 struct iwn_tx_radiotap_header *tap = &sc->sc_txtap; 3366 3367 tap->wt_flags = 0; 3368 tap->wt_rate = rate; 3369 if (k != NULL) 3370 tap->wt_flags |= IEEE80211_RADIOTAP_F_WEP; 3371 3372 ieee80211_radiotap_tx(vap, m); 3373 } 3374 3375 /* Prepare TX firmware command. */ 3376 cmd = &ring->cmd[ring->cur]; 3377 cmd->code = IWN_CMD_TX_DATA; 3378 cmd->flags = 0; 3379 cmd->qid = ring->qid; 3380 cmd->idx = ring->cur; 3381 3382 tx = (struct iwn_cmd_data *)cmd->data; 3383 /* NB: No need to clear tx, all fields are reinitialized here. */ 3384 tx->scratch = 0; /* clear "scratch" area */ 3385 3386 flags = 0; 3387 if (!IEEE80211_IS_MULTICAST(wh->i_addr1)) { 3388 /* Unicast frame, check if an ACK is expected. */ 3389 if (!qos || (qos & IEEE80211_QOS_ACKPOLICY) != 3390 IEEE80211_QOS_ACKPOLICY_NOACK) 3391 flags |= IWN_TX_NEED_ACK; 3392 } 3393 if ((wh->i_fc[0] & 3394 (IEEE80211_FC0_TYPE_MASK | IEEE80211_FC0_SUBTYPE_MASK)) == 3395 (IEEE80211_FC0_TYPE_CTL | IEEE80211_FC0_SUBTYPE_BAR)) 3396 flags |= IWN_TX_IMM_BA; /* Cannot happen yet. */ 3397 3398 if (wh->i_fc[1] & IEEE80211_FC1_MORE_FRAG) 3399 flags |= IWN_TX_MORE_FRAG; /* Cannot happen yet. */ 3400 3401 /* Check if frame must be protected using RTS/CTS or CTS-to-self. */ 3402 if (!IEEE80211_IS_MULTICAST(wh->i_addr1)) { 3403 /* NB: Group frames are sent using CCK in 802.11b/g. */ 3404 if (totlen + IEEE80211_CRC_LEN > vap->iv_rtsthreshold) { 3405 flags |= IWN_TX_NEED_RTS; 3406 } else if ((ic->ic_flags & IEEE80211_F_USEPROT) && 3407 ridx >= IWN_RIDX_OFDM6) { 3408 if (ic->ic_protmode == IEEE80211_PROT_CTSONLY) 3409 flags |= IWN_TX_NEED_CTS; 3410 else if (ic->ic_protmode == IEEE80211_PROT_RTSCTS) 3411 flags |= IWN_TX_NEED_RTS; 3412 } 3413 if (flags & (IWN_TX_NEED_RTS | IWN_TX_NEED_CTS)) { 3414 if (sc->hw_type != IWN_HW_REV_TYPE_4965) { 3415 /* 5000 autoselects RTS/CTS or CTS-to-self. */ 3416 flags &= ~(IWN_TX_NEED_RTS | IWN_TX_NEED_CTS); 3417 flags |= IWN_TX_NEED_PROTECTION; 3418 } else 3419 flags |= IWN_TX_FULL_TXOP; 3420 } 3421 } 3422 3423 if (IEEE80211_IS_MULTICAST(wh->i_addr1) || 3424 type != IEEE80211_FC0_TYPE_DATA) 3425 tx->id = sc->broadcast_id; 3426 else 3427 tx->id = wn->id; 3428 3429 if (type == IEEE80211_FC0_TYPE_MGT) { 3430 uint8_t subtype = wh->i_fc[0] & IEEE80211_FC0_SUBTYPE_MASK; 3431 3432 /* Tell HW to set timestamp in probe responses. */ 3433 if (subtype == IEEE80211_FC0_SUBTYPE_PROBE_RESP) 3434 flags |= IWN_TX_INSERT_TSTAMP; 3435 if (subtype == IEEE80211_FC0_SUBTYPE_ASSOC_REQ || 3436 subtype == IEEE80211_FC0_SUBTYPE_REASSOC_REQ) 3437 tx->timeout = htole16(3); 3438 else 3439 tx->timeout = htole16(2); 3440 } else 3441 tx->timeout = htole16(0); 3442 3443 if (hdrlen & 3) { 3444 /* First segment length must be a multiple of 4. */ 3445 flags |= IWN_TX_NEED_PADDING; 3446 pad = 4 - (hdrlen & 3); 3447 } else 3448 pad = 0; 3449 3450 tx->len = htole16(totlen); 3451 tx->tid = tid; 3452 tx->rts_ntries = 60; 3453 tx->data_ntries = 15; 3454 tx->lifetime = htole32(IWN_LIFETIME_INFINITE); 3455 tx->rate = wn->ridx[rate]; 3456 if (tx->id == sc->broadcast_id) { 3457 /* Group or management frame. */ 3458 tx->linkq = 0; 3459 /* XXX Alternate between antenna A and B? */ 3460 txant = IWN_LSB(sc->txchainmask); 3461 tx->rate |= htole32(IWN_RFLAG_ANT(txant)); 3462 } else { 3463 tx->linkq = ni->ni_rates.rs_nrates - ridx - 1; 3464 flags |= IWN_TX_LINKQ; /* enable MRR */ 3465 } 3466 /* Set physical address of "scratch area". */ 3467 tx->loaddr = htole32(IWN_LOADDR(data->scratch_paddr)); 3468 tx->hiaddr = IWN_HIADDR(data->scratch_paddr); 3469 3470 /* Copy 802.11 header in TX command. */ 3471 memcpy((uint8_t *)(tx + 1), wh, hdrlen); 3472 3473 /* Trim 802.11 header. */ 3474 m_adj(m, hdrlen); 3475 tx->security = 0; 3476 tx->flags = htole32(flags); 3477 3478 error = bus_dmamap_load_mbuf_sg(ring->data_dmat, data->map, m, segs, 3479 &nsegs, BUS_DMA_NOWAIT); 3480 if (error != 0) { 3481 if (error != EFBIG) { 3482 device_printf(sc->sc_dev, 3483 "%s: can't map mbuf (error %d)\n", __func__, error); 3484 m_freem(m); 3485 return error; 3486 } 3487 /* Too many DMA segments, linearize mbuf. */ 3488 m1 = m_collapse(m, M_DONTWAIT, IWN_MAX_SCATTER); 3489 if (m1 == NULL) { 3490 device_printf(sc->sc_dev, 3491 "%s: could not defrag mbuf\n", __func__); 3492 m_freem(m); 3493 return ENOBUFS; 3494 } 3495 m = m1; 3496 3497 error = bus_dmamap_load_mbuf_sg(ring->data_dmat, data->map, m, 3498 segs, &nsegs, BUS_DMA_NOWAIT); 3499 if (error != 0) { 3500 device_printf(sc->sc_dev, 3501 "%s: can't map mbuf (error %d)\n", __func__, error); 3502 m_freem(m); 3503 return error; 3504 } 3505 } 3506 3507 data->m = m; 3508 data->ni = ni; 3509 3510 DPRINTF(sc, IWN_DEBUG_XMIT, "%s: qid %d idx %d len %d nsegs %d\n", 3511 __func__, ring->qid, ring->cur, m->m_pkthdr.len, nsegs); 3512 3513 /* Fill TX descriptor. */ 3514 desc->nsegs = 1; 3515 if (m->m_len != 0) 3516 desc->nsegs += nsegs; 3517 /* First DMA segment is used by the TX command. */ 3518 desc->segs[0].addr = htole32(IWN_LOADDR(data->cmd_paddr)); 3519 desc->segs[0].len = htole16(IWN_HIADDR(data->cmd_paddr) | 3520 (4 + sizeof (*tx) + hdrlen + pad) << 4); 3521 /* Other DMA segments are for data payload. */ 3522 seg = &segs[0]; 3523 for (i = 1; i <= nsegs; i++) { 3524 desc->segs[i].addr = htole32(IWN_LOADDR(seg->ds_addr)); 3525 desc->segs[i].len = htole16(IWN_HIADDR(seg->ds_addr) | 3526 seg->ds_len << 4); 3527 seg++; 3528 } 3529 3530 bus_dmamap_sync(ring->data_dmat, data->map, BUS_DMASYNC_PREWRITE); 3531 bus_dmamap_sync(ring->data_dmat, ring->cmd_dma.map, 3532 BUS_DMASYNC_PREWRITE); 3533 bus_dmamap_sync(ring->desc_dma.tag, ring->desc_dma.map, 3534 BUS_DMASYNC_PREWRITE); 3535 3536 /* Update TX scheduler. */ 3537 if (ring->qid >= sc->firstaggqueue) 3538 ops->update_sched(sc, ring->qid, ring->cur, tx->id, totlen); 3539 3540 /* Kick TX ring. */ 3541 ring->cur = (ring->cur + 1) % IWN_TX_RING_COUNT; 3542 IWN_WRITE(sc, IWN_HBUS_TARG_WRPTR, ring->qid << 8 | ring->cur); 3543 3544 /* Mark TX ring as full if we reach a certain threshold. */ 3545 if (++ring->queued > IWN_TX_RING_HIMARK) 3546 sc->qfullmsk |= 1 << ring->qid; 3547 3548 return 0; 3549 } 3550 3551 static int 3552 iwn_tx_data_raw(struct iwn_softc *sc, struct mbuf *m, 3553 struct ieee80211_node *ni, const struct ieee80211_bpf_params *params) 3554 { 3555 struct iwn_ops *ops = &sc->ops; 3556 struct ifnet *ifp = sc->sc_ifp; 3557 struct ieee80211vap *vap = ni->ni_vap; 3558 struct ieee80211com *ic = ifp->if_l2com; 3559 struct iwn_tx_cmd *cmd; 3560 struct iwn_cmd_data *tx; 3561 struct ieee80211_frame *wh; 3562 struct iwn_tx_ring *ring; 3563 struct iwn_tx_desc *desc; 3564 struct iwn_tx_data *data; 3565 struct mbuf *m1; 3566 bus_dma_segment_t *seg, segs[IWN_MAX_SCATTER]; 3567 uint32_t flags; 3568 u_int hdrlen; 3569 int ac, totlen, error, pad, nsegs = 0, i, rate; 3570 uint8_t ridx, type, txant; 3571 3572 IWN_LOCK_ASSERT(sc); 3573 3574 wh = mtod(m, struct ieee80211_frame *); 3575 hdrlen = ieee80211_anyhdrsize(wh); 3576 type = wh->i_fc[0] & IEEE80211_FC0_TYPE_MASK; 3577 3578 ac = params->ibp_pri & 3; 3579 3580 ring = &sc->txq[ac]; 3581 desc = &ring->desc[ring->cur]; 3582 data = &ring->data[ring->cur]; 3583 3584 /* Choose a TX rate index. */ 3585 rate = params->ibp_rate0; 3586 ridx = ic->ic_rt->rateCodeToIndex[rate]; 3587 if (ridx == (uint8_t)-1) { 3588 /* XXX fall back to mcast/mgmt rate? */ 3589 m_freem(m); 3590 return EINVAL; 3591 } 3592 3593 totlen = m->m_pkthdr.len; 3594 3595 /* Prepare TX firmware command. */ 3596 cmd = &ring->cmd[ring->cur]; 3597 cmd->code = IWN_CMD_TX_DATA; 3598 cmd->flags = 0; 3599 cmd->qid = ring->qid; 3600 cmd->idx = ring->cur; 3601 3602 tx = (struct iwn_cmd_data *)cmd->data; 3603 /* NB: No need to clear tx, all fields are reinitialized here. */ 3604 tx->scratch = 0; /* clear "scratch" area */ 3605 3606 flags = 0; 3607 if ((params->ibp_flags & IEEE80211_BPF_NOACK) == 0) 3608 flags |= IWN_TX_NEED_ACK; 3609 if (params->ibp_flags & IEEE80211_BPF_RTS) { 3610 if (sc->hw_type != IWN_HW_REV_TYPE_4965) { 3611 /* 5000 autoselects RTS/CTS or CTS-to-self. */ 3612 flags &= ~IWN_TX_NEED_RTS; 3613 flags |= IWN_TX_NEED_PROTECTION; 3614 } else 3615 flags |= IWN_TX_NEED_RTS | IWN_TX_FULL_TXOP; 3616 } 3617 if (params->ibp_flags & IEEE80211_BPF_CTS) { 3618 if (sc->hw_type != IWN_HW_REV_TYPE_4965) { 3619 /* 5000 autoselects RTS/CTS or CTS-to-self. */ 3620 flags &= ~IWN_TX_NEED_CTS; 3621 flags |= IWN_TX_NEED_PROTECTION; 3622 } else 3623 flags |= IWN_TX_NEED_CTS | IWN_TX_FULL_TXOP; 3624 } 3625 if (type == IEEE80211_FC0_TYPE_MGT) { 3626 uint8_t subtype = wh->i_fc[0] & IEEE80211_FC0_SUBTYPE_MASK; 3627 3628 /* Tell HW to set timestamp in probe responses. */ 3629 if (subtype == IEEE80211_FC0_SUBTYPE_PROBE_RESP) 3630 flags |= IWN_TX_INSERT_TSTAMP; 3631 3632 if (subtype == IEEE80211_FC0_SUBTYPE_ASSOC_REQ || 3633 subtype == IEEE80211_FC0_SUBTYPE_REASSOC_REQ) 3634 tx->timeout = htole16(3); 3635 else 3636 tx->timeout = htole16(2); 3637 } else 3638 tx->timeout = htole16(0); 3639 3640 if (hdrlen & 3) { 3641 /* First segment length must be a multiple of 4. */ 3642 flags |= IWN_TX_NEED_PADDING; 3643 pad = 4 - (hdrlen & 3); 3644 } else 3645 pad = 0; 3646 3647 if (ieee80211_radiotap_active_vap(vap)) { 3648 struct iwn_tx_radiotap_header *tap = &sc->sc_txtap; 3649 3650 tap->wt_flags = 0; 3651 tap->wt_rate = rate; 3652 3653 ieee80211_radiotap_tx(vap, m); 3654 } 3655 3656 tx->len = htole16(totlen); 3657 tx->tid = 0; 3658 tx->id = sc->broadcast_id; 3659 tx->rts_ntries = params->ibp_try1; 3660 tx->data_ntries = params->ibp_try0; 3661 tx->lifetime = htole32(IWN_LIFETIME_INFINITE); 3662 tx->rate = htole32(rate2plcp(rate)); 3663 if (ridx < IWN_RIDX_OFDM6 && 3664 IEEE80211_IS_CHAN_2GHZ(ni->ni_chan)) 3665 tx->rate |= htole32(IWN_RFLAG_CCK); 3666 /* Group or management frame. */ 3667 tx->linkq = 0; 3668 txant = IWN_LSB(sc->txchainmask); 3669 tx->rate |= htole32(IWN_RFLAG_ANT(txant)); 3670 /* Set physical address of "scratch area". */ 3671 tx->loaddr = htole32(IWN_LOADDR(data->scratch_paddr)); 3672 tx->hiaddr = IWN_HIADDR(data->scratch_paddr); 3673 3674 /* Copy 802.11 header in TX command. */ 3675 memcpy((uint8_t *)(tx + 1), wh, hdrlen); 3676 3677 /* Trim 802.11 header. */ 3678 m_adj(m, hdrlen); 3679 tx->security = 0; 3680 tx->flags = htole32(flags); 3681 3682 error = bus_dmamap_load_mbuf_sg(ring->data_dmat, data->map, m, segs, 3683 &nsegs, BUS_DMA_NOWAIT); 3684 if (error != 0) { 3685 if (error != EFBIG) { 3686 device_printf(sc->sc_dev, 3687 "%s: can't map mbuf (error %d)\n", __func__, error); 3688 m_freem(m); 3689 return error; 3690 } 3691 /* Too many DMA segments, linearize mbuf. */ 3692 m1 = m_collapse(m, M_DONTWAIT, IWN_MAX_SCATTER); 3693 if (m1 == NULL) { 3694 device_printf(sc->sc_dev, 3695 "%s: could not defrag mbuf\n", __func__); 3696 m_freem(m); 3697 return ENOBUFS; 3698 } 3699 m = m1; 3700 3701 error = bus_dmamap_load_mbuf_sg(ring->data_dmat, data->map, m, 3702 segs, &nsegs, BUS_DMA_NOWAIT); 3703 if (error != 0) { 3704 device_printf(sc->sc_dev, 3705 "%s: can't map mbuf (error %d)\n", __func__, error); 3706 m_freem(m); 3707 return error; 3708 } 3709 } 3710 3711 data->m = m; 3712 data->ni = ni; 3713 3714 DPRINTF(sc, IWN_DEBUG_XMIT, "%s: qid %d idx %d len %d nsegs %d\n", 3715 __func__, ring->qid, ring->cur, m->m_pkthdr.len, nsegs); 3716 3717 /* Fill TX descriptor. */ 3718 desc->nsegs = 1; 3719 if (m->m_len != 0) 3720 desc->nsegs += nsegs; 3721 /* First DMA segment is used by the TX command. */ 3722 desc->segs[0].addr = htole32(IWN_LOADDR(data->cmd_paddr)); 3723 desc->segs[0].len = htole16(IWN_HIADDR(data->cmd_paddr) | 3724 (4 + sizeof (*tx) + hdrlen + pad) << 4); 3725 /* Other DMA segments are for data payload. */ 3726 seg = &segs[0]; 3727 for (i = 1; i <= nsegs; i++) { 3728 desc->segs[i].addr = htole32(IWN_LOADDR(seg->ds_addr)); 3729 desc->segs[i].len = htole16(IWN_HIADDR(seg->ds_addr) | 3730 seg->ds_len << 4); 3731 seg++; 3732 } 3733 3734 bus_dmamap_sync(ring->data_dmat, data->map, BUS_DMASYNC_PREWRITE); 3735 bus_dmamap_sync(ring->data_dmat, ring->cmd_dma.map, 3736 BUS_DMASYNC_PREWRITE); 3737 bus_dmamap_sync(ring->desc_dma.tag, ring->desc_dma.map, 3738 BUS_DMASYNC_PREWRITE); 3739 3740 /* Update TX scheduler. */ 3741 if (ring->qid >= sc->firstaggqueue) 3742 ops->update_sched(sc, ring->qid, ring->cur, tx->id, totlen); 3743 3744 /* Kick TX ring. */ 3745 ring->cur = (ring->cur + 1) % IWN_TX_RING_COUNT; 3746 IWN_WRITE(sc, IWN_HBUS_TARG_WRPTR, ring->qid << 8 | ring->cur); 3747 3748 /* Mark TX ring as full if we reach a certain threshold. */ 3749 if (++ring->queued > IWN_TX_RING_HIMARK) 3750 sc->qfullmsk |= 1 << ring->qid; 3751 3752 return 0; 3753 } 3754 3755 static int 3756 iwn_raw_xmit(struct ieee80211_node *ni, struct mbuf *m, 3757 const struct ieee80211_bpf_params *params) 3758 { 3759 struct ieee80211com *ic = ni->ni_ic; 3760 struct ifnet *ifp = ic->ic_ifp; 3761 struct iwn_softc *sc = ifp->if_softc; 3762 int error = 0; 3763 3764 if ((ifp->if_drv_flags & IFF_DRV_RUNNING) == 0) { 3765 ieee80211_free_node(ni); 3766 m_freem(m); 3767 return ENETDOWN; 3768 } 3769 3770 IWN_LOCK(sc); 3771 if (params == NULL) { 3772 /* 3773 * Legacy path; interpret frame contents to decide 3774 * precisely how to send the frame. 3775 */ 3776 error = iwn_tx_data(sc, m, ni); 3777 } else { 3778 /* 3779 * Caller supplied explicit parameters to use in 3780 * sending the frame. 3781 */ 3782 error = iwn_tx_data_raw(sc, m, ni, params); 3783 } 3784 if (error != 0) { 3785 /* NB: m is reclaimed on tx failure */ 3786 ieee80211_free_node(ni); 3787 ifp->if_oerrors++; 3788 } 3789 sc->sc_tx_timer = 5; 3790 3791 IWN_UNLOCK(sc); 3792 return error; 3793 } 3794 3795 static void 3796 iwn_start(struct ifnet *ifp) 3797 { 3798 struct iwn_softc *sc = ifp->if_softc; 3799 3800 IWN_LOCK(sc); 3801 iwn_start_locked(ifp); 3802 IWN_UNLOCK(sc); 3803 } 3804 3805 static void 3806 iwn_start_locked(struct ifnet *ifp) 3807 { 3808 struct iwn_softc *sc = ifp->if_softc; 3809 struct ieee80211_node *ni; 3810 struct mbuf *m; 3811 3812 IWN_LOCK_ASSERT(sc); 3813 3814 if ((ifp->if_drv_flags & IFF_DRV_RUNNING) == 0 || 3815 (ifp->if_drv_flags & IFF_DRV_OACTIVE)) 3816 return; 3817 3818 for (;;) { 3819 if (sc->qfullmsk != 0) { 3820 ifp->if_drv_flags |= IFF_DRV_OACTIVE; 3821 break; 3822 } 3823 IFQ_DRV_DEQUEUE(&ifp->if_snd, m); 3824 if (m == NULL) 3825 break; 3826 ni = (struct ieee80211_node *)m->m_pkthdr.rcvif; 3827 if (iwn_tx_data(sc, m, ni) != 0) { 3828 ieee80211_free_node(ni); 3829 ifp->if_oerrors++; 3830 continue; 3831 } 3832 sc->sc_tx_timer = 5; 3833 } 3834 } 3835 3836 static void 3837 iwn_watchdog(void *arg) 3838 { 3839 struct iwn_softc *sc = arg; 3840 struct ifnet *ifp = sc->sc_ifp; 3841 struct ieee80211com *ic = ifp->if_l2com; 3842 3843 IWN_LOCK_ASSERT(sc); 3844 3845 KASSERT(ifp->if_drv_flags & IFF_DRV_RUNNING, ("not running")); 3846 3847 if (sc->sc_tx_timer > 0) { 3848 if (--sc->sc_tx_timer == 0) { 3849 if_printf(ifp, "device timeout\n"); 3850 ieee80211_runtask(ic, &sc->sc_reinit_task); 3851 return; 3852 } 3853 } 3854 callout_reset(&sc->watchdog_to, hz, iwn_watchdog, sc); 3855 } 3856 3857 static int 3858 iwn_ioctl(struct ifnet *ifp, u_long cmd, caddr_t data) 3859 { 3860 struct iwn_softc *sc = ifp->if_softc; 3861 struct ieee80211com *ic = ifp->if_l2com; 3862 struct ieee80211vap *vap = TAILQ_FIRST(&ic->ic_vaps); 3863 struct ifreq *ifr = (struct ifreq *) data; 3864 int error = 0, startall = 0, stop = 0; 3865 3866 switch (cmd) { 3867 case SIOCGIFADDR: 3868 error = ether_ioctl(ifp, cmd, data); 3869 break; 3870 case SIOCSIFFLAGS: 3871 IWN_LOCK(sc); 3872 if (ifp->if_flags & IFF_UP) { 3873 if (!(ifp->if_drv_flags & IFF_DRV_RUNNING)) { 3874 iwn_init_locked(sc); 3875 if (IWN_READ(sc, IWN_GP_CNTRL) & IWN_GP_CNTRL_RFKILL) 3876 startall = 1; 3877 else 3878 stop = 1; 3879 } 3880 } else { 3881 if (ifp->if_drv_flags & IFF_DRV_RUNNING) 3882 iwn_stop_locked(sc); 3883 } 3884 IWN_UNLOCK(sc); 3885 if (startall) 3886 ieee80211_start_all(ic); 3887 else if (vap != NULL && stop) 3888 ieee80211_stop(vap); 3889 break; 3890 case SIOCGIFMEDIA: 3891 error = ifmedia_ioctl(ifp, ifr, &ic->ic_media, cmd); 3892 break; 3893 default: 3894 error = EINVAL; 3895 break; 3896 } 3897 return error; 3898 } 3899 3900 /* 3901 * Send a command to the firmware. 3902 */ 3903 static int 3904 iwn_cmd(struct iwn_softc *sc, int code, const void *buf, int size, int async) 3905 { 3906 struct iwn_tx_ring *ring = &sc->txq[4]; 3907 struct iwn_tx_desc *desc; 3908 struct iwn_tx_data *data; 3909 struct iwn_tx_cmd *cmd; 3910 struct mbuf *m; 3911 bus_addr_t paddr; 3912 int totlen, error; 3913 3914 if (async == 0) 3915 IWN_LOCK_ASSERT(sc); 3916 3917 desc = &ring->desc[ring->cur]; 3918 data = &ring->data[ring->cur]; 3919 totlen = 4 + size; 3920 3921 if (size > sizeof cmd->data) { 3922 /* Command is too large to fit in a descriptor. */ 3923 if (totlen > MCLBYTES) 3924 return EINVAL; 3925 m = m_getjcl(M_DONTWAIT, MT_DATA, M_PKTHDR, MJUMPAGESIZE); 3926 if (m == NULL) 3927 return ENOMEM; 3928 cmd = mtod(m, struct iwn_tx_cmd *); 3929 error = bus_dmamap_load(ring->data_dmat, data->map, cmd, 3930 totlen, iwn_dma_map_addr, &paddr, BUS_DMA_NOWAIT); 3931 if (error != 0) { 3932 m_freem(m); 3933 return error; 3934 } 3935 data->m = m; 3936 } else { 3937 cmd = &ring->cmd[ring->cur]; 3938 paddr = data->cmd_paddr; 3939 } 3940 3941 cmd->code = code; 3942 cmd->flags = 0; 3943 cmd->qid = ring->qid; 3944 cmd->idx = ring->cur; 3945 memcpy(cmd->data, buf, size); 3946 3947 desc->nsegs = 1; 3948 desc->segs[0].addr = htole32(IWN_LOADDR(paddr)); 3949 desc->segs[0].len = htole16(IWN_HIADDR(paddr) | totlen << 4); 3950 3951 DPRINTF(sc, IWN_DEBUG_CMD, "%s: %s (0x%x) flags %d qid %d idx %d\n", 3952 __func__, iwn_intr_str(cmd->code), cmd->code, 3953 cmd->flags, cmd->qid, cmd->idx); 3954 3955 if (size > sizeof cmd->data) { 3956 bus_dmamap_sync(ring->data_dmat, data->map, 3957 BUS_DMASYNC_PREWRITE); 3958 } else { 3959 bus_dmamap_sync(ring->data_dmat, ring->cmd_dma.map, 3960 BUS_DMASYNC_PREWRITE); 3961 } 3962 bus_dmamap_sync(ring->desc_dma.tag, ring->desc_dma.map, 3963 BUS_DMASYNC_PREWRITE); 3964 3965 /* Kick command ring. */ 3966 ring->cur = (ring->cur + 1) % IWN_TX_RING_COUNT; 3967 IWN_WRITE(sc, IWN_HBUS_TARG_WRPTR, ring->qid << 8 | ring->cur); 3968 3969 return async ? 0 : msleep(desc, &sc->sc_mtx, PCATCH, "iwncmd", hz); 3970 } 3971 3972 static int 3973 iwn4965_add_node(struct iwn_softc *sc, struct iwn_node_info *node, int async) 3974 { 3975 struct iwn4965_node_info hnode; 3976 caddr_t src, dst; 3977 3978 /* 3979 * We use the node structure for 5000 Series internally (it is 3980 * a superset of the one for 4965AGN). We thus copy the common 3981 * fields before sending the command. 3982 */ 3983 src = (caddr_t)node; 3984 dst = (caddr_t)&hnode; 3985 memcpy(dst, src, 48); 3986 /* Skip TSC, RX MIC and TX MIC fields from ``src''. */ 3987 memcpy(dst + 48, src + 72, 20); 3988 return iwn_cmd(sc, IWN_CMD_ADD_NODE, &hnode, sizeof hnode, async); 3989 } 3990 3991 static int 3992 iwn5000_add_node(struct iwn_softc *sc, struct iwn_node_info *node, int async) 3993 { 3994 /* Direct mapping. */ 3995 return iwn_cmd(sc, IWN_CMD_ADD_NODE, node, sizeof (*node), async); 3996 } 3997 3998 static int 3999 iwn_set_link_quality(struct iwn_softc *sc, struct ieee80211_node *ni) 4000 { 4001 #define RV(v) ((v) & IEEE80211_RATE_VAL) 4002 struct iwn_node *wn = (void *)ni; 4003 struct ieee80211_rateset *rs = &ni->ni_rates; 4004 struct iwn_cmd_link_quality linkq; 4005 uint8_t txant; 4006 int i, rate, txrate; 4007 4008 /* Use the first valid TX antenna. */ 4009 txant = IWN_LSB(sc->txchainmask); 4010 4011 memset(&linkq, 0, sizeof linkq); 4012 linkq.id = wn->id; 4013 linkq.antmsk_1stream = txant; 4014 linkq.antmsk_2stream = IWN_ANT_AB; 4015 linkq.ampdu_max = 64; 4016 linkq.ampdu_threshold = 3; 4017 linkq.ampdu_limit = htole16(4000); /* 4ms */ 4018 4019 /* Start at highest available bit-rate. */ 4020 if (IEEE80211_IS_CHAN_HT(ni->ni_chan)) 4021 txrate = ni->ni_htrates.rs_nrates - 1; 4022 else 4023 txrate = rs->rs_nrates - 1; 4024 for (i = 0; i < IWN_MAX_TX_RETRIES; i++) { 4025 if (IEEE80211_IS_CHAN_HT(ni->ni_chan)) 4026 rate = IEEE80211_RATE_MCS | txrate; 4027 else 4028 rate = RV(rs->rs_rates[txrate]); 4029 linkq.retry[i] = wn->ridx[rate]; 4030 4031 if ((le32toh(wn->ridx[rate]) & IWN_RFLAG_MCS) && 4032 RV(le32toh(wn->ridx[rate])) > 7) 4033 linkq.mimo = i + 1; 4034 4035 /* Next retry at immediate lower bit-rate. */ 4036 if (txrate > 0) 4037 txrate--; 4038 } 4039 return iwn_cmd(sc, IWN_CMD_LINK_QUALITY, &linkq, sizeof linkq, 1); 4040 #undef RV 4041 } 4042 4043 /* 4044 * Broadcast node is used to send group-addressed and management frames. 4045 */ 4046 static int 4047 iwn_add_broadcast_node(struct iwn_softc *sc, int async) 4048 { 4049 struct iwn_ops *ops = &sc->ops; 4050 struct ifnet *ifp = sc->sc_ifp; 4051 struct ieee80211com *ic = ifp->if_l2com; 4052 struct iwn_node_info node; 4053 struct iwn_cmd_link_quality linkq; 4054 uint8_t txant; 4055 int i, error; 4056 4057 memset(&node, 0, sizeof node); 4058 IEEE80211_ADDR_COPY(node.macaddr, ifp->if_broadcastaddr); 4059 node.id = sc->broadcast_id; 4060 DPRINTF(sc, IWN_DEBUG_RESET, "%s: adding broadcast node\n", __func__); 4061 if ((error = ops->add_node(sc, &node, async)) != 0) 4062 return error; 4063 4064 /* Use the first valid TX antenna. */ 4065 txant = IWN_LSB(sc->txchainmask); 4066 4067 memset(&linkq, 0, sizeof linkq); 4068 linkq.id = sc->broadcast_id; 4069 linkq.antmsk_1stream = txant; 4070 linkq.antmsk_2stream = IWN_ANT_AB; 4071 linkq.ampdu_max = 64; 4072 linkq.ampdu_threshold = 3; 4073 linkq.ampdu_limit = htole16(4000); /* 4ms */ 4074 4075 /* Use lowest mandatory bit-rate. */ 4076 if (IEEE80211_IS_CHAN_5GHZ(ic->ic_curchan)) 4077 linkq.retry[0] = htole32(0xd); 4078 else 4079 linkq.retry[0] = htole32(10 | IWN_RFLAG_CCK); 4080 linkq.retry[0] |= htole32(IWN_RFLAG_ANT(txant)); 4081 /* Use same bit-rate for all TX retries. */ 4082 for (i = 1; i < IWN_MAX_TX_RETRIES; i++) { 4083 linkq.retry[i] = linkq.retry[0]; 4084 } 4085 return iwn_cmd(sc, IWN_CMD_LINK_QUALITY, &linkq, sizeof linkq, async); 4086 } 4087 4088 static int 4089 iwn_updateedca(struct ieee80211com *ic) 4090 { 4091 #define IWN_EXP2(x) ((1 << (x)) - 1) /* CWmin = 2^ECWmin - 1 */ 4092 struct iwn_softc *sc = ic->ic_ifp->if_softc; 4093 struct iwn_edca_params cmd; 4094 int aci; 4095 4096 memset(&cmd, 0, sizeof cmd); 4097 cmd.flags = htole32(IWN_EDCA_UPDATE); 4098 for (aci = 0; aci < WME_NUM_AC; aci++) { 4099 const struct wmeParams *ac = 4100 &ic->ic_wme.wme_chanParams.cap_wmeParams[aci]; 4101 cmd.ac[aci].aifsn = ac->wmep_aifsn; 4102 cmd.ac[aci].cwmin = htole16(IWN_EXP2(ac->wmep_logcwmin)); 4103 cmd.ac[aci].cwmax = htole16(IWN_EXP2(ac->wmep_logcwmax)); 4104 cmd.ac[aci].txoplimit = 4105 htole16(IEEE80211_TXOP_TO_US(ac->wmep_txopLimit)); 4106 } 4107 IEEE80211_UNLOCK(ic); 4108 IWN_LOCK(sc); 4109 (void)iwn_cmd(sc, IWN_CMD_EDCA_PARAMS, &cmd, sizeof cmd, 1); 4110 IWN_UNLOCK(sc); 4111 IEEE80211_LOCK(ic); 4112 return 0; 4113 #undef IWN_EXP2 4114 } 4115 4116 static void 4117 iwn_update_mcast(struct ifnet *ifp) 4118 { 4119 /* Ignore */ 4120 } 4121 4122 static void 4123 iwn_set_led(struct iwn_softc *sc, uint8_t which, uint8_t off, uint8_t on) 4124 { 4125 struct iwn_cmd_led led; 4126 4127 /* Clear microcode LED ownership. */ 4128 IWN_CLRBITS(sc, IWN_LED, IWN_LED_BSM_CTRL); 4129 4130 led.which = which; 4131 led.unit = htole32(10000); /* on/off in unit of 100ms */ 4132 led.off = off; 4133 led.on = on; 4134 (void)iwn_cmd(sc, IWN_CMD_SET_LED, &led, sizeof led, 1); 4135 } 4136 4137 /* 4138 * Set the critical temperature at which the firmware will stop the radio 4139 * and notify us. 4140 */ 4141 static int 4142 iwn_set_critical_temp(struct iwn_softc *sc) 4143 { 4144 struct iwn_critical_temp crit; 4145 int32_t temp; 4146 4147 IWN_WRITE(sc, IWN_UCODE_GP1_CLR, IWN_UCODE_GP1_CTEMP_STOP_RF); 4148 4149 if (sc->hw_type == IWN_HW_REV_TYPE_5150) 4150 temp = (IWN_CTOK(110) - sc->temp_off) * -5; 4151 else if (sc->hw_type == IWN_HW_REV_TYPE_4965) 4152 temp = IWN_CTOK(110); 4153 else 4154 temp = 110; 4155 memset(&crit, 0, sizeof crit); 4156 crit.tempR = htole32(temp); 4157 DPRINTF(sc, IWN_DEBUG_RESET, "setting critical temp to %d\n", temp); 4158 return iwn_cmd(sc, IWN_CMD_SET_CRITICAL_TEMP, &crit, sizeof crit, 0); 4159 } 4160 4161 static int 4162 iwn_set_timing(struct iwn_softc *sc, struct ieee80211_node *ni) 4163 { 4164 struct iwn_cmd_timing cmd; 4165 uint64_t val, mod; 4166 4167 memset(&cmd, 0, sizeof cmd); 4168 memcpy(&cmd.tstamp, ni->ni_tstamp.data, sizeof (uint64_t)); 4169 cmd.bintval = htole16(ni->ni_intval); 4170 cmd.lintval = htole16(10); 4171 4172 /* Compute remaining time until next beacon. */ 4173 val = (uint64_t)ni->ni_intval * IEEE80211_DUR_TU; 4174 mod = le64toh(cmd.tstamp) % val; 4175 cmd.binitval = htole32((uint32_t)(val - mod)); 4176 4177 DPRINTF(sc, IWN_DEBUG_RESET, "timing bintval=%u tstamp=%ju, init=%u\n", 4178 ni->ni_intval, le64toh(cmd.tstamp), (uint32_t)(val - mod)); 4179 4180 return iwn_cmd(sc, IWN_CMD_TIMING, &cmd, sizeof cmd, 1); 4181 } 4182 4183 static void 4184 iwn4965_power_calibration(struct iwn_softc *sc, int temp) 4185 { 4186 struct ifnet *ifp = sc->sc_ifp; 4187 struct ieee80211com *ic = ifp->if_l2com; 4188 4189 /* Adjust TX power if need be (delta >= 3 degC). */ 4190 DPRINTF(sc, IWN_DEBUG_CALIBRATE, "%s: temperature %d->%d\n", 4191 __func__, sc->temp, temp); 4192 if (abs(temp - sc->temp) >= 3) { 4193 /* Record temperature of last calibration. */ 4194 sc->temp = temp; 4195 (void)iwn4965_set_txpower(sc, ic->ic_bsschan, 1); 4196 } 4197 } 4198 4199 /* 4200 * Set TX power for current channel (each rate has its own power settings). 4201 * This function takes into account the regulatory information from EEPROM, 4202 * the current temperature and the current voltage. 4203 */ 4204 static int 4205 iwn4965_set_txpower(struct iwn_softc *sc, struct ieee80211_channel *ch, 4206 int async) 4207 { 4208 /* Fixed-point arithmetic division using a n-bit fractional part. */ 4209 #define fdivround(a, b, n) \ 4210 ((((1 << n) * (a)) / (b) + (1 << n) / 2) / (1 << n)) 4211 /* Linear interpolation. */ 4212 #define interpolate(x, x1, y1, x2, y2, n) \ 4213 ((y1) + fdivround(((int)(x) - (x1)) * ((y2) - (y1)), (x2) - (x1), n)) 4214 4215 static const int tdiv[IWN_NATTEN_GROUPS] = { 9, 8, 8, 8, 6 }; 4216 struct iwn_ucode_info *uc = &sc->ucode_info; 4217 struct iwn4965_cmd_txpower cmd; 4218 struct iwn4965_eeprom_chan_samples *chans; 4219 const uint8_t *rf_gain, *dsp_gain; 4220 int32_t vdiff, tdiff; 4221 int i, c, grp, maxpwr; 4222 uint8_t chan; 4223 4224 /* Retrieve current channel from last RXON. */ 4225 chan = sc->rxon.chan; 4226 DPRINTF(sc, IWN_DEBUG_RESET, "setting TX power for channel %d\n", 4227 chan); 4228 4229 memset(&cmd, 0, sizeof cmd); 4230 cmd.band = IEEE80211_IS_CHAN_5GHZ(ch) ? 0 : 1; 4231 cmd.chan = chan; 4232 4233 if (IEEE80211_IS_CHAN_5GHZ(ch)) { 4234 maxpwr = sc->maxpwr5GHz; 4235 rf_gain = iwn4965_rf_gain_5ghz; 4236 dsp_gain = iwn4965_dsp_gain_5ghz; 4237 } else { 4238 maxpwr = sc->maxpwr2GHz; 4239 rf_gain = iwn4965_rf_gain_2ghz; 4240 dsp_gain = iwn4965_dsp_gain_2ghz; 4241 } 4242 4243 /* Compute voltage compensation. */ 4244 vdiff = ((int32_t)le32toh(uc->volt) - sc->eeprom_voltage) / 7; 4245 if (vdiff > 0) 4246 vdiff *= 2; 4247 if (abs(vdiff) > 2) 4248 vdiff = 0; 4249 DPRINTF(sc, IWN_DEBUG_CALIBRATE | IWN_DEBUG_TXPOW, 4250 "%s: voltage compensation=%d (UCODE=%d, EEPROM=%d)\n", 4251 __func__, vdiff, le32toh(uc->volt), sc->eeprom_voltage); 4252 4253 /* Get channel attenuation group. */ 4254 if (chan <= 20) /* 1-20 */ 4255 grp = 4; 4256 else if (chan <= 43) /* 34-43 */ 4257 grp = 0; 4258 else if (chan <= 70) /* 44-70 */ 4259 grp = 1; 4260 else if (chan <= 124) /* 71-124 */ 4261 grp = 2; 4262 else /* 125-200 */ 4263 grp = 3; 4264 DPRINTF(sc, IWN_DEBUG_CALIBRATE | IWN_DEBUG_TXPOW, 4265 "%s: chan %d, attenuation group=%d\n", __func__, chan, grp); 4266 4267 /* Get channel sub-band. */ 4268 for (i = 0; i < IWN_NBANDS; i++) 4269 if (sc->bands[i].lo != 0 && 4270 sc->bands[i].lo <= chan && chan <= sc->bands[i].hi) 4271 break; 4272 if (i == IWN_NBANDS) /* Can't happen in real-life. */ 4273 return EINVAL; 4274 chans = sc->bands[i].chans; 4275 DPRINTF(sc, IWN_DEBUG_CALIBRATE | IWN_DEBUG_TXPOW, 4276 "%s: chan %d sub-band=%d\n", __func__, chan, i); 4277 4278 for (c = 0; c < 2; c++) { 4279 uint8_t power, gain, temp; 4280 int maxchpwr, pwr, ridx, idx; 4281 4282 power = interpolate(chan, 4283 chans[0].num, chans[0].samples[c][1].power, 4284 chans[1].num, chans[1].samples[c][1].power, 1); 4285 gain = interpolate(chan, 4286 chans[0].num, chans[0].samples[c][1].gain, 4287 chans[1].num, chans[1].samples[c][1].gain, 1); 4288 temp = interpolate(chan, 4289 chans[0].num, chans[0].samples[c][1].temp, 4290 chans[1].num, chans[1].samples[c][1].temp, 1); 4291 DPRINTF(sc, IWN_DEBUG_CALIBRATE | IWN_DEBUG_TXPOW, 4292 "%s: Tx chain %d: power=%d gain=%d temp=%d\n", 4293 __func__, c, power, gain, temp); 4294 4295 /* Compute temperature compensation. */ 4296 tdiff = ((sc->temp - temp) * 2) / tdiv[grp]; 4297 DPRINTF(sc, IWN_DEBUG_CALIBRATE | IWN_DEBUG_TXPOW, 4298 "%s: temperature compensation=%d (current=%d, EEPROM=%d)\n", 4299 __func__, tdiff, sc->temp, temp); 4300 4301 for (ridx = 0; ridx <= IWN_RIDX_MAX; ridx++) { 4302 /* Convert dBm to half-dBm. */ 4303 maxchpwr = sc->maxpwr[chan] * 2; 4304 if ((ridx / 8) & 1) 4305 maxchpwr -= 6; /* MIMO 2T: -3dB */ 4306 4307 pwr = maxpwr; 4308 4309 /* Adjust TX power based on rate. */ 4310 if ((ridx % 8) == 5) 4311 pwr -= 15; /* OFDM48: -7.5dB */ 4312 else if ((ridx % 8) == 6) 4313 pwr -= 17; /* OFDM54: -8.5dB */ 4314 else if ((ridx % 8) == 7) 4315 pwr -= 20; /* OFDM60: -10dB */ 4316 else 4317 pwr -= 10; /* Others: -5dB */ 4318 4319 /* Do not exceed channel max TX power. */ 4320 if (pwr > maxchpwr) 4321 pwr = maxchpwr; 4322 4323 idx = gain - (pwr - power) - tdiff - vdiff; 4324 if ((ridx / 8) & 1) /* MIMO */ 4325 idx += (int32_t)le32toh(uc->atten[grp][c]); 4326 4327 if (cmd.band == 0) 4328 idx += 9; /* 5GHz */ 4329 if (ridx == IWN_RIDX_MAX) 4330 idx += 5; /* CCK */ 4331 4332 /* Make sure idx stays in a valid range. */ 4333 if (idx < 0) 4334 idx = 0; 4335 else if (idx > IWN4965_MAX_PWR_INDEX) 4336 idx = IWN4965_MAX_PWR_INDEX; 4337 4338 DPRINTF(sc, IWN_DEBUG_CALIBRATE | IWN_DEBUG_TXPOW, 4339 "%s: Tx chain %d, rate idx %d: power=%d\n", 4340 __func__, c, ridx, idx); 4341 cmd.power[ridx].rf_gain[c] = rf_gain[idx]; 4342 cmd.power[ridx].dsp_gain[c] = dsp_gain[idx]; 4343 } 4344 } 4345 4346 DPRINTF(sc, IWN_DEBUG_CALIBRATE | IWN_DEBUG_TXPOW, 4347 "%s: set tx power for chan %d\n", __func__, chan); 4348 return iwn_cmd(sc, IWN_CMD_TXPOWER, &cmd, sizeof cmd, async); 4349 4350 #undef interpolate 4351 #undef fdivround 4352 } 4353 4354 static int 4355 iwn5000_set_txpower(struct iwn_softc *sc, struct ieee80211_channel *ch, 4356 int async) 4357 { 4358 struct iwn5000_cmd_txpower cmd; 4359 4360 /* 4361 * TX power calibration is handled automatically by the firmware 4362 * for 5000 Series. 4363 */ 4364 memset(&cmd, 0, sizeof cmd); 4365 cmd.global_limit = 2 * IWN5000_TXPOWER_MAX_DBM; /* 16 dBm */ 4366 cmd.flags = IWN5000_TXPOWER_NO_CLOSED; 4367 cmd.srv_limit = IWN5000_TXPOWER_AUTO; 4368 DPRINTF(sc, IWN_DEBUG_CALIBRATE, "%s: setting TX power\n", __func__); 4369 return iwn_cmd(sc, IWN_CMD_TXPOWER_DBM, &cmd, sizeof cmd, async); 4370 } 4371 4372 /* 4373 * Retrieve the maximum RSSI (in dBm) among receivers. 4374 */ 4375 static int 4376 iwn4965_get_rssi(struct iwn_softc *sc, struct iwn_rx_stat *stat) 4377 { 4378 struct iwn4965_rx_phystat *phy = (void *)stat->phybuf; 4379 uint8_t mask, agc; 4380 int rssi; 4381 4382 mask = (le16toh(phy->antenna) >> 4) & IWN_ANT_ABC; 4383 agc = (le16toh(phy->agc) >> 7) & 0x7f; 4384 4385 rssi = 0; 4386 if (mask & IWN_ANT_A) 4387 rssi = MAX(rssi, phy->rssi[0]); 4388 if (mask & IWN_ANT_B) 4389 rssi = MAX(rssi, phy->rssi[2]); 4390 if (mask & IWN_ANT_C) 4391 rssi = MAX(rssi, phy->rssi[4]); 4392 4393 DPRINTF(sc, IWN_DEBUG_RECV, 4394 "%s: agc %d mask 0x%x rssi %d %d %d result %d\n", __func__, agc, 4395 mask, phy->rssi[0], phy->rssi[2], phy->rssi[4], 4396 rssi - agc - IWN_RSSI_TO_DBM); 4397 return rssi - agc - IWN_RSSI_TO_DBM; 4398 } 4399 4400 static int 4401 iwn5000_get_rssi(struct iwn_softc *sc, struct iwn_rx_stat *stat) 4402 { 4403 struct iwn5000_rx_phystat *phy = (void *)stat->phybuf; 4404 uint8_t agc; 4405 int rssi; 4406 4407 agc = (le32toh(phy->agc) >> 9) & 0x7f; 4408 4409 rssi = MAX(le16toh(phy->rssi[0]) & 0xff, 4410 le16toh(phy->rssi[1]) & 0xff); 4411 rssi = MAX(le16toh(phy->rssi[2]) & 0xff, rssi); 4412 4413 DPRINTF(sc, IWN_DEBUG_RECV, 4414 "%s: agc %d rssi %d %d %d result %d\n", __func__, agc, 4415 phy->rssi[0], phy->rssi[1], phy->rssi[2], 4416 rssi - agc - IWN_RSSI_TO_DBM); 4417 return rssi - agc - IWN_RSSI_TO_DBM; 4418 } 4419 4420 /* 4421 * Retrieve the average noise (in dBm) among receivers. 4422 */ 4423 static int 4424 iwn_get_noise(const struct iwn_rx_general_stats *stats) 4425 { 4426 int i, total, nbant, noise; 4427 4428 total = nbant = 0; 4429 for (i = 0; i < 3; i++) { 4430 if ((noise = le32toh(stats->noise[i]) & 0xff) == 0) 4431 continue; 4432 total += noise; 4433 nbant++; 4434 } 4435 /* There should be at least one antenna but check anyway. */ 4436 return (nbant == 0) ? -127 : (total / nbant) - 107; 4437 } 4438 4439 /* 4440 * Compute temperature (in degC) from last received statistics. 4441 */ 4442 static int 4443 iwn4965_get_temperature(struct iwn_softc *sc) 4444 { 4445 struct iwn_ucode_info *uc = &sc->ucode_info; 4446 int32_t r1, r2, r3, r4, temp; 4447 4448 r1 = le32toh(uc->temp[0].chan20MHz); 4449 r2 = le32toh(uc->temp[1].chan20MHz); 4450 r3 = le32toh(uc->temp[2].chan20MHz); 4451 r4 = le32toh(sc->rawtemp); 4452 4453 if (r1 == r3) /* Prevents division by 0 (should not happen). */ 4454 return 0; 4455 4456 /* Sign-extend 23-bit R4 value to 32-bit. */ 4457 r4 = ((r4 & 0xffffff) ^ 0x800000) - 0x800000; 4458 /* Compute temperature in Kelvin. */ 4459 temp = (259 * (r4 - r2)) / (r3 - r1); 4460 temp = (temp * 97) / 100 + 8; 4461 4462 DPRINTF(sc, IWN_DEBUG_ANY, "temperature %dK/%dC\n", temp, 4463 IWN_KTOC(temp)); 4464 return IWN_KTOC(temp); 4465 } 4466 4467 static int 4468 iwn5000_get_temperature(struct iwn_softc *sc) 4469 { 4470 int32_t temp; 4471 4472 /* 4473 * Temperature is not used by the driver for 5000 Series because 4474 * TX power calibration is handled by firmware. 4475 */ 4476 temp = le32toh(sc->rawtemp); 4477 if (sc->hw_type == IWN_HW_REV_TYPE_5150) { 4478 temp = (temp / -5) + sc->temp_off; 4479 temp = IWN_KTOC(temp); 4480 } 4481 return temp; 4482 } 4483 4484 /* 4485 * Initialize sensitivity calibration state machine. 4486 */ 4487 static int 4488 iwn_init_sensitivity(struct iwn_softc *sc) 4489 { 4490 struct iwn_ops *ops = &sc->ops; 4491 struct iwn_calib_state *calib = &sc->calib; 4492 uint32_t flags; 4493 int error; 4494 4495 /* Reset calibration state machine. */ 4496 memset(calib, 0, sizeof (*calib)); 4497 calib->state = IWN_CALIB_STATE_INIT; 4498 calib->cck_state = IWN_CCK_STATE_HIFA; 4499 /* Set initial correlation values. */ 4500 calib->ofdm_x1 = sc->limits->min_ofdm_x1; 4501 calib->ofdm_mrc_x1 = sc->limits->min_ofdm_mrc_x1; 4502 calib->ofdm_x4 = sc->limits->min_ofdm_x4; 4503 calib->ofdm_mrc_x4 = sc->limits->min_ofdm_mrc_x4; 4504 calib->cck_x4 = 125; 4505 calib->cck_mrc_x4 = sc->limits->min_cck_mrc_x4; 4506 calib->energy_cck = sc->limits->energy_cck; 4507 4508 /* Write initial sensitivity. */ 4509 if ((error = iwn_send_sensitivity(sc)) != 0) 4510 return error; 4511 4512 /* Write initial gains. */ 4513 if ((error = ops->init_gains(sc)) != 0) 4514 return error; 4515 4516 /* Request statistics at each beacon interval. */ 4517 flags = 0; 4518 DPRINTF(sc, IWN_DEBUG_CALIBRATE, "%s: sending request for statistics\n", 4519 __func__); 4520 return iwn_cmd(sc, IWN_CMD_GET_STATISTICS, &flags, sizeof flags, 1); 4521 } 4522 4523 /* 4524 * Collect noise and RSSI statistics for the first 20 beacons received 4525 * after association and use them to determine connected antennas and 4526 * to set differential gains. 4527 */ 4528 static void 4529 iwn_collect_noise(struct iwn_softc *sc, 4530 const struct iwn_rx_general_stats *stats) 4531 { 4532 struct iwn_ops *ops = &sc->ops; 4533 struct iwn_calib_state *calib = &sc->calib; 4534 uint32_t val; 4535 int i; 4536 4537 /* Accumulate RSSI and noise for all 3 antennas. */ 4538 for (i = 0; i < 3; i++) { 4539 calib->rssi[i] += le32toh(stats->rssi[i]) & 0xff; 4540 calib->noise[i] += le32toh(stats->noise[i]) & 0xff; 4541 } 4542 /* NB: We update differential gains only once after 20 beacons. */ 4543 if (++calib->nbeacons < 20) 4544 return; 4545 4546 /* Determine highest average RSSI. */ 4547 val = MAX(calib->rssi[0], calib->rssi[1]); 4548 val = MAX(calib->rssi[2], val); 4549 4550 /* Determine which antennas are connected. */ 4551 sc->chainmask = sc->rxchainmask; 4552 for (i = 0; i < 3; i++) 4553 if (val - calib->rssi[i] > 15 * 20) 4554 sc->chainmask &= ~(1 << i); 4555 DPRINTF(sc, IWN_DEBUG_CALIBRATE, 4556 "%s: RX chains mask: theoretical=0x%x, actual=0x%x\n", 4557 __func__, sc->rxchainmask, sc->chainmask); 4558 4559 /* If none of the TX antennas are connected, keep at least one. */ 4560 if ((sc->chainmask & sc->txchainmask) == 0) 4561 sc->chainmask |= IWN_LSB(sc->txchainmask); 4562 4563 (void)ops->set_gains(sc); 4564 calib->state = IWN_CALIB_STATE_RUN; 4565 4566 #ifdef notyet 4567 /* XXX Disable RX chains with no antennas connected. */ 4568 sc->rxon.rxchain = htole16(IWN_RXCHAIN_SEL(sc->chainmask)); 4569 (void)iwn_cmd(sc, IWN_CMD_RXON, &sc->rxon, sc->rxonsz, 1); 4570 #endif 4571 4572 #if 0 4573 /* XXX: not yet */ 4574 /* Enable power-saving mode if requested by user. */ 4575 if (sc->sc_ic.ic_flags & IEEE80211_F_PMGTON) 4576 (void)iwn_set_pslevel(sc, 0, 3, 1); 4577 #endif 4578 } 4579 4580 static int 4581 iwn4965_init_gains(struct iwn_softc *sc) 4582 { 4583 struct iwn_phy_calib_gain cmd; 4584 4585 memset(&cmd, 0, sizeof cmd); 4586 cmd.code = IWN4965_PHY_CALIB_DIFF_GAIN; 4587 /* Differential gains initially set to 0 for all 3 antennas. */ 4588 DPRINTF(sc, IWN_DEBUG_CALIBRATE, 4589 "%s: setting initial differential gains\n", __func__); 4590 return iwn_cmd(sc, IWN_CMD_PHY_CALIB, &cmd, sizeof cmd, 1); 4591 } 4592 4593 static int 4594 iwn5000_init_gains(struct iwn_softc *sc) 4595 { 4596 struct iwn_phy_calib cmd; 4597 4598 memset(&cmd, 0, sizeof cmd); 4599 cmd.code = sc->reset_noise_gain; 4600 cmd.ngroups = 1; 4601 cmd.isvalid = 1; 4602 DPRINTF(sc, IWN_DEBUG_CALIBRATE, 4603 "%s: setting initial differential gains\n", __func__); 4604 return iwn_cmd(sc, IWN_CMD_PHY_CALIB, &cmd, sizeof cmd, 1); 4605 } 4606 4607 static int 4608 iwn4965_set_gains(struct iwn_softc *sc) 4609 { 4610 struct iwn_calib_state *calib = &sc->calib; 4611 struct iwn_phy_calib_gain cmd; 4612 int i, delta, noise; 4613 4614 /* Get minimal noise among connected antennas. */ 4615 noise = INT_MAX; /* NB: There's at least one antenna. */ 4616 for (i = 0; i < 3; i++) 4617 if (sc->chainmask & (1 << i)) 4618 noise = MIN(calib->noise[i], noise); 4619 4620 memset(&cmd, 0, sizeof cmd); 4621 cmd.code = IWN4965_PHY_CALIB_DIFF_GAIN; 4622 /* Set differential gains for connected antennas. */ 4623 for (i = 0; i < 3; i++) { 4624 if (sc->chainmask & (1 << i)) { 4625 /* Compute attenuation (in unit of 1.5dB). */ 4626 delta = (noise - (int32_t)calib->noise[i]) / 30; 4627 /* NB: delta <= 0 */ 4628 /* Limit to [-4.5dB,0]. */ 4629 cmd.gain[i] = MIN(abs(delta), 3); 4630 if (delta < 0) 4631 cmd.gain[i] |= 1 << 2; /* sign bit */ 4632 } 4633 } 4634 DPRINTF(sc, IWN_DEBUG_CALIBRATE, 4635 "setting differential gains Ant A/B/C: %x/%x/%x (%x)\n", 4636 cmd.gain[0], cmd.gain[1], cmd.gain[2], sc->chainmask); 4637 return iwn_cmd(sc, IWN_CMD_PHY_CALIB, &cmd, sizeof cmd, 1); 4638 } 4639 4640 static int 4641 iwn5000_set_gains(struct iwn_softc *sc) 4642 { 4643 struct iwn_calib_state *calib = &sc->calib; 4644 struct iwn_phy_calib_gain cmd; 4645 int i, ant, div, delta; 4646 4647 /* We collected 20 beacons and !=6050 need a 1.5 factor. */ 4648 div = (sc->hw_type == IWN_HW_REV_TYPE_6050) ? 20 : 30; 4649 4650 memset(&cmd, 0, sizeof cmd); 4651 cmd.code = sc->noise_gain; 4652 cmd.ngroups = 1; 4653 cmd.isvalid = 1; 4654 /* Get first available RX antenna as referential. */ 4655 ant = IWN_LSB(sc->rxchainmask); 4656 /* Set differential gains for other antennas. */ 4657 for (i = ant + 1; i < 3; i++) { 4658 if (sc->chainmask & (1 << i)) { 4659 /* The delta is relative to antenna "ant". */ 4660 delta = ((int32_t)calib->noise[ant] - 4661 (int32_t)calib->noise[i]) / div; 4662 /* Limit to [-4.5dB,+4.5dB]. */ 4663 cmd.gain[i - 1] = MIN(abs(delta), 3); 4664 if (delta < 0) 4665 cmd.gain[i - 1] |= 1 << 2; /* sign bit */ 4666 } 4667 } 4668 DPRINTF(sc, IWN_DEBUG_CALIBRATE, 4669 "setting differential gains Ant B/C: %x/%x (%x)\n", 4670 cmd.gain[0], cmd.gain[1], sc->chainmask); 4671 return iwn_cmd(sc, IWN_CMD_PHY_CALIB, &cmd, sizeof cmd, 1); 4672 } 4673 4674 /* 4675 * Tune RF RX sensitivity based on the number of false alarms detected 4676 * during the last beacon period. 4677 */ 4678 static void 4679 iwn_tune_sensitivity(struct iwn_softc *sc, const struct iwn_rx_stats *stats) 4680 { 4681 #define inc(val, inc, max) \ 4682 if ((val) < (max)) { \ 4683 if ((val) < (max) - (inc)) \ 4684 (val) += (inc); \ 4685 else \ 4686 (val) = (max); \ 4687 needs_update = 1; \ 4688 } 4689 #define dec(val, dec, min) \ 4690 if ((val) > (min)) { \ 4691 if ((val) > (min) + (dec)) \ 4692 (val) -= (dec); \ 4693 else \ 4694 (val) = (min); \ 4695 needs_update = 1; \ 4696 } 4697 4698 const struct iwn_sensitivity_limits *limits = sc->limits; 4699 struct iwn_calib_state *calib = &sc->calib; 4700 uint32_t val, rxena, fa; 4701 uint32_t energy[3], energy_min; 4702 uint8_t noise[3], noise_ref; 4703 int i, needs_update = 0; 4704 4705 /* Check that we've been enabled long enough. */ 4706 if ((rxena = le32toh(stats->general.load)) == 0) 4707 return; 4708 4709 /* Compute number of false alarms since last call for OFDM. */ 4710 fa = le32toh(stats->ofdm.bad_plcp) - calib->bad_plcp_ofdm; 4711 fa += le32toh(stats->ofdm.fa) - calib->fa_ofdm; 4712 fa *= 200 * IEEE80211_DUR_TU; /* 200TU */ 4713 4714 /* Save counters values for next call. */ 4715 calib->bad_plcp_ofdm = le32toh(stats->ofdm.bad_plcp); 4716 calib->fa_ofdm = le32toh(stats->ofdm.fa); 4717 4718 if (fa > 50 * rxena) { 4719 /* High false alarm count, decrease sensitivity. */ 4720 DPRINTF(sc, IWN_DEBUG_CALIBRATE, 4721 "%s: OFDM high false alarm count: %u\n", __func__, fa); 4722 inc(calib->ofdm_x1, 1, limits->max_ofdm_x1); 4723 inc(calib->ofdm_mrc_x1, 1, limits->max_ofdm_mrc_x1); 4724 inc(calib->ofdm_x4, 1, limits->max_ofdm_x4); 4725 inc(calib->ofdm_mrc_x4, 1, limits->max_ofdm_mrc_x4); 4726 4727 } else if (fa < 5 * rxena) { 4728 /* Low false alarm count, increase sensitivity. */ 4729 DPRINTF(sc, IWN_DEBUG_CALIBRATE, 4730 "%s: OFDM low false alarm count: %u\n", __func__, fa); 4731 dec(calib->ofdm_x1, 1, limits->min_ofdm_x1); 4732 dec(calib->ofdm_mrc_x1, 1, limits->min_ofdm_mrc_x1); 4733 dec(calib->ofdm_x4, 1, limits->min_ofdm_x4); 4734 dec(calib->ofdm_mrc_x4, 1, limits->min_ofdm_mrc_x4); 4735 } 4736 4737 /* Compute maximum noise among 3 receivers. */ 4738 for (i = 0; i < 3; i++) 4739 noise[i] = (le32toh(stats->general.noise[i]) >> 8) & 0xff; 4740 val = MAX(noise[0], noise[1]); 4741 val = MAX(noise[2], val); 4742 /* Insert it into our samples table. */ 4743 calib->noise_samples[calib->cur_noise_sample] = val; 4744 calib->cur_noise_sample = (calib->cur_noise_sample + 1) % 20; 4745 4746 /* Compute maximum noise among last 20 samples. */ 4747 noise_ref = calib->noise_samples[0]; 4748 for (i = 1; i < 20; i++) 4749 noise_ref = MAX(noise_ref, calib->noise_samples[i]); 4750 4751 /* Compute maximum energy among 3 receivers. */ 4752 for (i = 0; i < 3; i++) 4753 energy[i] = le32toh(stats->general.energy[i]); 4754 val = MIN(energy[0], energy[1]); 4755 val = MIN(energy[2], val); 4756 /* Insert it into our samples table. */ 4757 calib->energy_samples[calib->cur_energy_sample] = val; 4758 calib->cur_energy_sample = (calib->cur_energy_sample + 1) % 10; 4759 4760 /* Compute minimum energy among last 10 samples. */ 4761 energy_min = calib->energy_samples[0]; 4762 for (i = 1; i < 10; i++) 4763 energy_min = MAX(energy_min, calib->energy_samples[i]); 4764 energy_min += 6; 4765 4766 /* Compute number of false alarms since last call for CCK. */ 4767 fa = le32toh(stats->cck.bad_plcp) - calib->bad_plcp_cck; 4768 fa += le32toh(stats->cck.fa) - calib->fa_cck; 4769 fa *= 200 * IEEE80211_DUR_TU; /* 200TU */ 4770 4771 /* Save counters values for next call. */ 4772 calib->bad_plcp_cck = le32toh(stats->cck.bad_plcp); 4773 calib->fa_cck = le32toh(stats->cck.fa); 4774 4775 if (fa > 50 * rxena) { 4776 /* High false alarm count, decrease sensitivity. */ 4777 DPRINTF(sc, IWN_DEBUG_CALIBRATE, 4778 "%s: CCK high false alarm count: %u\n", __func__, fa); 4779 calib->cck_state = IWN_CCK_STATE_HIFA; 4780 calib->low_fa = 0; 4781 4782 if (calib->cck_x4 > 160) { 4783 calib->noise_ref = noise_ref; 4784 if (calib->energy_cck > 2) 4785 dec(calib->energy_cck, 2, energy_min); 4786 } 4787 if (calib->cck_x4 < 160) { 4788 calib->cck_x4 = 161; 4789 needs_update = 1; 4790 } else 4791 inc(calib->cck_x4, 3, limits->max_cck_x4); 4792 4793 inc(calib->cck_mrc_x4, 3, limits->max_cck_mrc_x4); 4794 4795 } else if (fa < 5 * rxena) { 4796 /* Low false alarm count, increase sensitivity. */ 4797 DPRINTF(sc, IWN_DEBUG_CALIBRATE, 4798 "%s: CCK low false alarm count: %u\n", __func__, fa); 4799 calib->cck_state = IWN_CCK_STATE_LOFA; 4800 calib->low_fa++; 4801 4802 if (calib->cck_state != IWN_CCK_STATE_INIT && 4803 (((int32_t)calib->noise_ref - (int32_t)noise_ref) > 2 || 4804 calib->low_fa > 100)) { 4805 inc(calib->energy_cck, 2, limits->min_energy_cck); 4806 dec(calib->cck_x4, 3, limits->min_cck_x4); 4807 dec(calib->cck_mrc_x4, 3, limits->min_cck_mrc_x4); 4808 } 4809 } else { 4810 /* Not worth to increase or decrease sensitivity. */ 4811 DPRINTF(sc, IWN_DEBUG_CALIBRATE, 4812 "%s: CCK normal false alarm count: %u\n", __func__, fa); 4813 calib->low_fa = 0; 4814 calib->noise_ref = noise_ref; 4815 4816 if (calib->cck_state == IWN_CCK_STATE_HIFA) { 4817 /* Previous interval had many false alarms. */ 4818 dec(calib->energy_cck, 8, energy_min); 4819 } 4820 calib->cck_state = IWN_CCK_STATE_INIT; 4821 } 4822 4823 if (needs_update) 4824 (void)iwn_send_sensitivity(sc); 4825 #undef dec 4826 #undef inc 4827 } 4828 4829 static int 4830 iwn_send_sensitivity(struct iwn_softc *sc) 4831 { 4832 struct iwn_calib_state *calib = &sc->calib; 4833 struct iwn_enhanced_sensitivity_cmd cmd; 4834 int len; 4835 4836 memset(&cmd, 0, sizeof cmd); 4837 len = sizeof (struct iwn_sensitivity_cmd); 4838 cmd.which = IWN_SENSITIVITY_WORKTBL; 4839 /* OFDM modulation. */ 4840 cmd.corr_ofdm_x1 = htole16(calib->ofdm_x1); 4841 cmd.corr_ofdm_mrc_x1 = htole16(calib->ofdm_mrc_x1); 4842 cmd.corr_ofdm_x4 = htole16(calib->ofdm_x4); 4843 cmd.corr_ofdm_mrc_x4 = htole16(calib->ofdm_mrc_x4); 4844 cmd.energy_ofdm = htole16(sc->limits->energy_ofdm); 4845 cmd.energy_ofdm_th = htole16(62); 4846 /* CCK modulation. */ 4847 cmd.corr_cck_x4 = htole16(calib->cck_x4); 4848 cmd.corr_cck_mrc_x4 = htole16(calib->cck_mrc_x4); 4849 cmd.energy_cck = htole16(calib->energy_cck); 4850 /* Barker modulation: use default values. */ 4851 cmd.corr_barker = htole16(190); 4852 cmd.corr_barker_mrc = htole16(390); 4853 4854 DPRINTF(sc, IWN_DEBUG_CALIBRATE, 4855 "%s: set sensitivity %d/%d/%d/%d/%d/%d/%d\n", __func__, 4856 calib->ofdm_x1, calib->ofdm_mrc_x1, calib->ofdm_x4, 4857 calib->ofdm_mrc_x4, calib->cck_x4, 4858 calib->cck_mrc_x4, calib->energy_cck); 4859 4860 if (!(sc->sc_flags & IWN_FLAG_ENH_SENS)) 4861 goto send; 4862 /* Enhanced sensitivity settings. */ 4863 len = sizeof (struct iwn_enhanced_sensitivity_cmd); 4864 cmd.ofdm_det_slope_mrc = htole16(668); 4865 cmd.ofdm_det_icept_mrc = htole16(4); 4866 cmd.ofdm_det_slope = htole16(486); 4867 cmd.ofdm_det_icept = htole16(37); 4868 cmd.cck_det_slope_mrc = htole16(853); 4869 cmd.cck_det_icept_mrc = htole16(4); 4870 cmd.cck_det_slope = htole16(476); 4871 cmd.cck_det_icept = htole16(99); 4872 send: 4873 return iwn_cmd(sc, IWN_CMD_SET_SENSITIVITY, &cmd, len, 1); 4874 } 4875 4876 /* 4877 * Set STA mode power saving level (between 0 and 5). 4878 * Level 0 is CAM (Continuously Aware Mode), 5 is for maximum power saving. 4879 */ 4880 static int 4881 iwn_set_pslevel(struct iwn_softc *sc, int dtim, int level, int async) 4882 { 4883 struct iwn_pmgt_cmd cmd; 4884 const struct iwn_pmgt *pmgt; 4885 uint32_t max, skip_dtim; 4886 uint32_t reg; 4887 int i; 4888 4889 /* Select which PS parameters to use. */ 4890 if (dtim <= 2) 4891 pmgt = &iwn_pmgt[0][level]; 4892 else if (dtim <= 10) 4893 pmgt = &iwn_pmgt[1][level]; 4894 else 4895 pmgt = &iwn_pmgt[2][level]; 4896 4897 memset(&cmd, 0, sizeof cmd); 4898 if (level != 0) /* not CAM */ 4899 cmd.flags |= htole16(IWN_PS_ALLOW_SLEEP); 4900 if (level == 5) 4901 cmd.flags |= htole16(IWN_PS_FAST_PD); 4902 /* Retrieve PCIe Active State Power Management (ASPM). */ 4903 reg = pci_read_config(sc->sc_dev, sc->sc_cap_off + 0x10, 1); 4904 if (!(reg & 0x1)) /* L0s Entry disabled. */ 4905 cmd.flags |= htole16(IWN_PS_PCI_PMGT); 4906 cmd.rxtimeout = htole32(pmgt->rxtimeout * 1024); 4907 cmd.txtimeout = htole32(pmgt->txtimeout * 1024); 4908 4909 if (dtim == 0) { 4910 dtim = 1; 4911 skip_dtim = 0; 4912 } else 4913 skip_dtim = pmgt->skip_dtim; 4914 if (skip_dtim != 0) { 4915 cmd.flags |= htole16(IWN_PS_SLEEP_OVER_DTIM); 4916 max = pmgt->intval[4]; 4917 if (max == (uint32_t)-1) 4918 max = dtim * (skip_dtim + 1); 4919 else if (max > dtim) 4920 max = (max / dtim) * dtim; 4921 } else 4922 max = dtim; 4923 for (i = 0; i < 5; i++) 4924 cmd.intval[i] = htole32(MIN(max, pmgt->intval[i])); 4925 4926 DPRINTF(sc, IWN_DEBUG_RESET, "setting power saving level to %d\n", 4927 level); 4928 return iwn_cmd(sc, IWN_CMD_SET_POWER_MODE, &cmd, sizeof cmd, async); 4929 } 4930 4931 static int 4932 iwn_send_btcoex(struct iwn_softc *sc) 4933 { 4934 struct iwn_bluetooth cmd; 4935 4936 memset(&cmd, 0, sizeof cmd); 4937 cmd.flags = IWN_BT_COEX_CHAN_ANN | IWN_BT_COEX_BT_PRIO; 4938 cmd.lead_time = IWN_BT_LEAD_TIME_DEF; 4939 cmd.max_kill = IWN_BT_MAX_KILL_DEF; 4940 DPRINTF(sc, IWN_DEBUG_RESET, "%s: configuring bluetooth coexistence\n", 4941 __func__); 4942 return iwn_cmd(sc, IWN_CMD_BT_COEX, &cmd, sizeof(cmd), 0); 4943 } 4944 4945 static int 4946 iwn_send_advanced_btcoex(struct iwn_softc *sc) 4947 { 4948 static const uint32_t btcoex_3wire[12] = { 4949 0xaaaaaaaa, 0xaaaaaaaa, 0xaeaaaaaa, 0xaaaaaaaa, 4950 0xcc00ff28, 0x0000aaaa, 0xcc00aaaa, 0x0000aaaa, 4951 0xc0004000, 0x00004000, 0xf0005000, 0xf0005000, 4952 }; 4953 struct iwn6000_btcoex_config btconfig; 4954 struct iwn_btcoex_priotable btprio; 4955 struct iwn_btcoex_prot btprot; 4956 int error, i; 4957 4958 memset(&btconfig, 0, sizeof btconfig); 4959 btconfig.flags = 145; 4960 btconfig.max_kill = 5; 4961 btconfig.bt3_t7_timer = 1; 4962 btconfig.kill_ack = htole32(0xffff0000); 4963 btconfig.kill_cts = htole32(0xffff0000); 4964 btconfig.sample_time = 2; 4965 btconfig.bt3_t2_timer = 0xc; 4966 for (i = 0; i < 12; i++) 4967 btconfig.lookup_table[i] = htole32(btcoex_3wire[i]); 4968 btconfig.valid = htole16(0xff); 4969 btconfig.prio_boost = 0xf0; 4970 DPRINTF(sc, IWN_DEBUG_RESET, 4971 "%s: configuring advanced bluetooth coexistence\n", __func__); 4972 error = iwn_cmd(sc, IWN_CMD_BT_COEX, &btconfig, sizeof(btconfig), 1); 4973 if (error != 0) 4974 return error; 4975 4976 memset(&btprio, 0, sizeof btprio); 4977 btprio.calib_init1 = 0x6; 4978 btprio.calib_init2 = 0x7; 4979 btprio.calib_periodic_low1 = 0x2; 4980 btprio.calib_periodic_low2 = 0x3; 4981 btprio.calib_periodic_high1 = 0x4; 4982 btprio.calib_periodic_high2 = 0x5; 4983 btprio.dtim = 0x6; 4984 btprio.scan52 = 0x8; 4985 btprio.scan24 = 0xa; 4986 error = iwn_cmd(sc, IWN_CMD_BT_COEX_PRIOTABLE, &btprio, sizeof(btprio), 4987 1); 4988 if (error != 0) 4989 return error; 4990 4991 /* Force BT state machine change. */ 4992 memset(&btprot, 0, sizeof btprio); 4993 btprot.open = 1; 4994 btprot.type = 1; 4995 error = iwn_cmd(sc, IWN_CMD_BT_COEX_PROT, &btprot, sizeof(btprot), 1); 4996 if (error != 0) 4997 return error; 4998 btprot.open = 0; 4999 return iwn_cmd(sc, IWN_CMD_BT_COEX_PROT, &btprot, sizeof(btprot), 1); 5000 } 5001 5002 static int 5003 iwn5000_runtime_calib(struct iwn_softc *sc) 5004 { 5005 struct iwn5000_calib_config cmd; 5006 5007 memset(&cmd, 0, sizeof cmd); 5008 cmd.ucode.once.enable = 0xffffffff; 5009 cmd.ucode.once.start = IWN5000_CALIB_DC; 5010 DPRINTF(sc, IWN_DEBUG_CALIBRATE, 5011 "%s: configuring runtime calibration\n", __func__); 5012 return iwn_cmd(sc, IWN5000_CMD_CALIB_CONFIG, &cmd, sizeof(cmd), 0); 5013 } 5014 5015 static int 5016 iwn_config(struct iwn_softc *sc) 5017 { 5018 struct iwn_ops *ops = &sc->ops; 5019 struct ifnet *ifp = sc->sc_ifp; 5020 struct ieee80211com *ic = ifp->if_l2com; 5021 uint32_t txmask; 5022 uint16_t rxchain; 5023 int error; 5024 5025 if (sc->hw_type == IWN_HW_REV_TYPE_6005) { 5026 /* Set radio temperature sensor offset. */ 5027 error = iwn5000_temp_offset_calib(sc); 5028 if (error != 0) { 5029 device_printf(sc->sc_dev, 5030 "%s: could not set temperature offset\n", __func__); 5031 return error; 5032 } 5033 } 5034 5035 if (sc->hw_type == IWN_HW_REV_TYPE_6050) { 5036 /* Configure runtime DC calibration. */ 5037 error = iwn5000_runtime_calib(sc); 5038 if (error != 0) { 5039 device_printf(sc->sc_dev, 5040 "%s: could not configure runtime calibration\n", 5041 __func__); 5042 return error; 5043 } 5044 } 5045 5046 /* Configure valid TX chains for >=5000 Series. */ 5047 if (sc->hw_type != IWN_HW_REV_TYPE_4965) { 5048 txmask = htole32(sc->txchainmask); 5049 DPRINTF(sc, IWN_DEBUG_RESET, 5050 "%s: configuring valid TX chains 0x%x\n", __func__, txmask); 5051 error = iwn_cmd(sc, IWN5000_CMD_TX_ANT_CONFIG, &txmask, 5052 sizeof txmask, 0); 5053 if (error != 0) { 5054 device_printf(sc->sc_dev, 5055 "%s: could not configure valid TX chains, " 5056 "error %d\n", __func__, error); 5057 return error; 5058 } 5059 } 5060 5061 /* Configure bluetooth coexistence. */ 5062 if (sc->sc_flags & IWN_FLAG_ADV_BTCOEX) 5063 error = iwn_send_advanced_btcoex(sc); 5064 else 5065 error = iwn_send_btcoex(sc); 5066 if (error != 0) { 5067 device_printf(sc->sc_dev, 5068 "%s: could not configure bluetooth coexistence, error %d\n", 5069 __func__, error); 5070 return error; 5071 } 5072 5073 /* Set mode, channel, RX filter and enable RX. */ 5074 memset(&sc->rxon, 0, sizeof (struct iwn_rxon)); 5075 IEEE80211_ADDR_COPY(sc->rxon.myaddr, IF_LLADDR(ifp)); 5076 IEEE80211_ADDR_COPY(sc->rxon.wlap, IF_LLADDR(ifp)); 5077 sc->rxon.chan = ieee80211_chan2ieee(ic, ic->ic_curchan); 5078 sc->rxon.flags = htole32(IWN_RXON_TSF | IWN_RXON_CTS_TO_SELF); 5079 if (IEEE80211_IS_CHAN_2GHZ(ic->ic_curchan)) 5080 sc->rxon.flags |= htole32(IWN_RXON_AUTO | IWN_RXON_24GHZ); 5081 switch (ic->ic_opmode) { 5082 case IEEE80211_M_STA: 5083 sc->rxon.mode = IWN_MODE_STA; 5084 sc->rxon.filter = htole32(IWN_FILTER_MULTICAST); 5085 break; 5086 case IEEE80211_M_MONITOR: 5087 sc->rxon.mode = IWN_MODE_MONITOR; 5088 sc->rxon.filter = htole32(IWN_FILTER_MULTICAST | 5089 IWN_FILTER_CTL | IWN_FILTER_PROMISC); 5090 break; 5091 default: 5092 /* Should not get there. */ 5093 break; 5094 } 5095 sc->rxon.cck_mask = 0x0f; /* not yet negotiated */ 5096 sc->rxon.ofdm_mask = 0xff; /* not yet negotiated */ 5097 sc->rxon.ht_single_mask = 0xff; 5098 sc->rxon.ht_dual_mask = 0xff; 5099 sc->rxon.ht_triple_mask = 0xff; 5100 rxchain = 5101 IWN_RXCHAIN_VALID(sc->rxchainmask) | 5102 IWN_RXCHAIN_MIMO_COUNT(2) | 5103 IWN_RXCHAIN_IDLE_COUNT(2); 5104 sc->rxon.rxchain = htole16(rxchain); 5105 DPRINTF(sc, IWN_DEBUG_RESET, "%s: setting configuration\n", __func__); 5106 error = iwn_cmd(sc, IWN_CMD_RXON, &sc->rxon, sc->rxonsz, 0); 5107 if (error != 0) { 5108 device_printf(sc->sc_dev, "%s: RXON command failed\n", 5109 __func__); 5110 return error; 5111 } 5112 5113 if ((error = iwn_add_broadcast_node(sc, 0)) != 0) { 5114 device_printf(sc->sc_dev, "%s: could not add broadcast node\n", 5115 __func__); 5116 return error; 5117 } 5118 5119 /* Configuration has changed, set TX power accordingly. */ 5120 if ((error = ops->set_txpower(sc, ic->ic_curchan, 0)) != 0) { 5121 device_printf(sc->sc_dev, "%s: could not set TX power\n", 5122 __func__); 5123 return error; 5124 } 5125 5126 if ((error = iwn_set_critical_temp(sc)) != 0) { 5127 device_printf(sc->sc_dev, 5128 "%s: could not set critical temperature\n", __func__); 5129 return error; 5130 } 5131 5132 /* Set power saving level to CAM during initialization. */ 5133 if ((error = iwn_set_pslevel(sc, 0, 0, 0)) != 0) { 5134 device_printf(sc->sc_dev, 5135 "%s: could not set power saving level\n", __func__); 5136 return error; 5137 } 5138 return 0; 5139 } 5140 5141 /* 5142 * Add an ssid element to a frame. 5143 */ 5144 static uint8_t * 5145 ieee80211_add_ssid(uint8_t *frm, const uint8_t *ssid, u_int len) 5146 { 5147 *frm++ = IEEE80211_ELEMID_SSID; 5148 *frm++ = len; 5149 memcpy(frm, ssid, len); 5150 return frm + len; 5151 } 5152 5153 static int 5154 iwn_scan(struct iwn_softc *sc) 5155 { 5156 struct ifnet *ifp = sc->sc_ifp; 5157 struct ieee80211com *ic = ifp->if_l2com; 5158 struct ieee80211_scan_state *ss = ic->ic_scan; /*XXX*/ 5159 struct ieee80211_node *ni = ss->ss_vap->iv_bss; 5160 struct iwn_scan_hdr *hdr; 5161 struct iwn_cmd_data *tx; 5162 struct iwn_scan_essid *essid; 5163 struct iwn_scan_chan *chan; 5164 struct ieee80211_frame *wh; 5165 struct ieee80211_rateset *rs; 5166 struct ieee80211_channel *c; 5167 uint8_t *buf, *frm; 5168 uint16_t rxchain; 5169 uint8_t txant; 5170 int buflen, error; 5171 5172 buf = malloc(IWN_SCAN_MAXSZ, M_DEVBUF, M_NOWAIT | M_ZERO); 5173 if (buf == NULL) { 5174 device_printf(sc->sc_dev, 5175 "%s: could not allocate buffer for scan command\n", 5176 __func__); 5177 return ENOMEM; 5178 } 5179 hdr = (struct iwn_scan_hdr *)buf; 5180 /* 5181 * Move to the next channel if no frames are received within 10ms 5182 * after sending the probe request. 5183 */ 5184 hdr->quiet_time = htole16(10); /* timeout in milliseconds */ 5185 hdr->quiet_threshold = htole16(1); /* min # of packets */ 5186 5187 /* Select antennas for scanning. */ 5188 rxchain = 5189 IWN_RXCHAIN_VALID(sc->rxchainmask) | 5190 IWN_RXCHAIN_FORCE_MIMO_SEL(sc->rxchainmask) | 5191 IWN_RXCHAIN_DRIVER_FORCE; 5192 if (IEEE80211_IS_CHAN_A(ic->ic_curchan) && 5193 sc->hw_type == IWN_HW_REV_TYPE_4965) { 5194 /* Ant A must be avoided in 5GHz because of an HW bug. */ 5195 rxchain |= IWN_RXCHAIN_FORCE_SEL(IWN_ANT_B); 5196 } else /* Use all available RX antennas. */ 5197 rxchain |= IWN_RXCHAIN_FORCE_SEL(sc->rxchainmask); 5198 hdr->rxchain = htole16(rxchain); 5199 hdr->filter = htole32(IWN_FILTER_MULTICAST | IWN_FILTER_BEACON); 5200 5201 tx = (struct iwn_cmd_data *)(hdr + 1); 5202 tx->flags = htole32(IWN_TX_AUTO_SEQ); 5203 tx->id = sc->broadcast_id; 5204 tx->lifetime = htole32(IWN_LIFETIME_INFINITE); 5205 5206 if (IEEE80211_IS_CHAN_5GHZ(ic->ic_curchan)) { 5207 /* Send probe requests at 6Mbps. */ 5208 tx->rate = htole32(0xd); 5209 rs = &ic->ic_sup_rates[IEEE80211_MODE_11A]; 5210 } else { 5211 hdr->flags = htole32(IWN_RXON_24GHZ | IWN_RXON_AUTO); 5212 if (sc->hw_type == IWN_HW_REV_TYPE_4965 && 5213 sc->rxon.associd && sc->rxon.chan > 14) 5214 tx->rate = htole32(0xd); 5215 else { 5216 /* Send probe requests at 1Mbps. */ 5217 tx->rate = htole32(10 | IWN_RFLAG_CCK); 5218 } 5219 rs = &ic->ic_sup_rates[IEEE80211_MODE_11G]; 5220 } 5221 /* Use the first valid TX antenna. */ 5222 txant = IWN_LSB(sc->txchainmask); 5223 tx->rate |= htole32(IWN_RFLAG_ANT(txant)); 5224 5225 essid = (struct iwn_scan_essid *)(tx + 1); 5226 if (ss->ss_ssid[0].len != 0) { 5227 essid[0].id = IEEE80211_ELEMID_SSID; 5228 essid[0].len = ss->ss_ssid[0].len; 5229 memcpy(essid[0].data, ss->ss_ssid[0].ssid, ss->ss_ssid[0].len); 5230 } 5231 /* 5232 * Build a probe request frame. Most of the following code is a 5233 * copy & paste of what is done in net80211. 5234 */ 5235 wh = (struct ieee80211_frame *)(essid + 20); 5236 wh->i_fc[0] = IEEE80211_FC0_VERSION_0 | IEEE80211_FC0_TYPE_MGT | 5237 IEEE80211_FC0_SUBTYPE_PROBE_REQ; 5238 wh->i_fc[1] = IEEE80211_FC1_DIR_NODS; 5239 IEEE80211_ADDR_COPY(wh->i_addr1, ifp->if_broadcastaddr); 5240 IEEE80211_ADDR_COPY(wh->i_addr2, IF_LLADDR(ifp)); 5241 IEEE80211_ADDR_COPY(wh->i_addr3, ifp->if_broadcastaddr); 5242 *(uint16_t *)&wh->i_dur[0] = 0; /* filled by HW */ 5243 *(uint16_t *)&wh->i_seq[0] = 0; /* filled by HW */ 5244 5245 frm = (uint8_t *)(wh + 1); 5246 frm = ieee80211_add_ssid(frm, NULL, 0); 5247 frm = ieee80211_add_rates(frm, rs); 5248 if (rs->rs_nrates > IEEE80211_RATE_SIZE) 5249 frm = ieee80211_add_xrates(frm, rs); 5250 if (ic->ic_htcaps & IEEE80211_HTC_HT) 5251 frm = ieee80211_add_htcap(frm, ni); 5252 5253 /* Set length of probe request. */ 5254 tx->len = htole16(frm - (uint8_t *)wh); 5255 5256 c = ic->ic_curchan; 5257 chan = (struct iwn_scan_chan *)frm; 5258 chan->chan = htole16(ieee80211_chan2ieee(ic, c)); 5259 chan->flags = 0; 5260 if (ss->ss_nssid > 0) 5261 chan->flags |= htole32(IWN_CHAN_NPBREQS(1)); 5262 chan->dsp_gain = 0x6e; 5263 if (IEEE80211_IS_CHAN_5GHZ(c) && 5264 !(c->ic_flags & IEEE80211_CHAN_PASSIVE)) { 5265 chan->rf_gain = 0x3b; 5266 chan->active = htole16(24); 5267 chan->passive = htole16(110); 5268 chan->flags |= htole32(IWN_CHAN_ACTIVE); 5269 } else if (IEEE80211_IS_CHAN_5GHZ(c)) { 5270 chan->rf_gain = 0x3b; 5271 chan->active = htole16(24); 5272 if (sc->rxon.associd) 5273 chan->passive = htole16(78); 5274 else 5275 chan->passive = htole16(110); 5276 hdr->crc_threshold = 0xffff; 5277 } else if (!(c->ic_flags & IEEE80211_CHAN_PASSIVE)) { 5278 chan->rf_gain = 0x28; 5279 chan->active = htole16(36); 5280 chan->passive = htole16(120); 5281 chan->flags |= htole32(IWN_CHAN_ACTIVE); 5282 } else { 5283 chan->rf_gain = 0x28; 5284 chan->active = htole16(36); 5285 if (sc->rxon.associd) 5286 chan->passive = htole16(88); 5287 else 5288 chan->passive = htole16(120); 5289 hdr->crc_threshold = 0xffff; 5290 } 5291 5292 DPRINTF(sc, IWN_DEBUG_STATE, 5293 "%s: chan %u flags 0x%x rf_gain 0x%x " 5294 "dsp_gain 0x%x active 0x%x passive 0x%x\n", __func__, 5295 chan->chan, chan->flags, chan->rf_gain, chan->dsp_gain, 5296 chan->active, chan->passive); 5297 5298 hdr->nchan++; 5299 chan++; 5300 buflen = (uint8_t *)chan - buf; 5301 hdr->len = htole16(buflen); 5302 5303 DPRINTF(sc, IWN_DEBUG_STATE, "sending scan command nchan=%d\n", 5304 hdr->nchan); 5305 error = iwn_cmd(sc, IWN_CMD_SCAN, buf, buflen, 1); 5306 free(buf, M_DEVBUF); 5307 return error; 5308 } 5309 5310 static int 5311 iwn_auth(struct iwn_softc *sc, struct ieee80211vap *vap) 5312 { 5313 struct iwn_ops *ops = &sc->ops; 5314 struct ifnet *ifp = sc->sc_ifp; 5315 struct ieee80211com *ic = ifp->if_l2com; 5316 struct ieee80211_node *ni = vap->iv_bss; 5317 int error; 5318 5319 /* Update adapter configuration. */ 5320 IEEE80211_ADDR_COPY(sc->rxon.bssid, ni->ni_bssid); 5321 sc->rxon.chan = ieee80211_chan2ieee(ic, ni->ni_chan); 5322 sc->rxon.flags = htole32(IWN_RXON_TSF | IWN_RXON_CTS_TO_SELF); 5323 if (IEEE80211_IS_CHAN_2GHZ(ni->ni_chan)) 5324 sc->rxon.flags |= htole32(IWN_RXON_AUTO | IWN_RXON_24GHZ); 5325 if (ic->ic_flags & IEEE80211_F_SHSLOT) 5326 sc->rxon.flags |= htole32(IWN_RXON_SHSLOT); 5327 if (ic->ic_flags & IEEE80211_F_SHPREAMBLE) 5328 sc->rxon.flags |= htole32(IWN_RXON_SHPREAMBLE); 5329 if (IEEE80211_IS_CHAN_A(ni->ni_chan)) { 5330 sc->rxon.cck_mask = 0; 5331 sc->rxon.ofdm_mask = 0x15; 5332 } else if (IEEE80211_IS_CHAN_B(ni->ni_chan)) { 5333 sc->rxon.cck_mask = 0x03; 5334 sc->rxon.ofdm_mask = 0; 5335 } else { 5336 /* Assume 802.11b/g. */ 5337 sc->rxon.cck_mask = 0x0f; 5338 sc->rxon.ofdm_mask = 0x15; 5339 } 5340 DPRINTF(sc, IWN_DEBUG_STATE, "rxon chan %d flags %x cck %x ofdm %x\n", 5341 sc->rxon.chan, sc->rxon.flags, sc->rxon.cck_mask, 5342 sc->rxon.ofdm_mask); 5343 error = iwn_cmd(sc, IWN_CMD_RXON, &sc->rxon, sc->rxonsz, 1); 5344 if (error != 0) { 5345 device_printf(sc->sc_dev, "%s: RXON command failed, error %d\n", 5346 __func__, error); 5347 return error; 5348 } 5349 5350 /* Configuration has changed, set TX power accordingly. */ 5351 if ((error = ops->set_txpower(sc, ni->ni_chan, 1)) != 0) { 5352 device_printf(sc->sc_dev, 5353 "%s: could not set TX power, error %d\n", __func__, error); 5354 return error; 5355 } 5356 /* 5357 * Reconfiguring RXON clears the firmware nodes table so we must 5358 * add the broadcast node again. 5359 */ 5360 if ((error = iwn_add_broadcast_node(sc, 1)) != 0) { 5361 device_printf(sc->sc_dev, 5362 "%s: could not add broadcast node, error %d\n", __func__, 5363 error); 5364 return error; 5365 } 5366 return 0; 5367 } 5368 5369 static int 5370 iwn_run(struct iwn_softc *sc, struct ieee80211vap *vap) 5371 { 5372 struct iwn_ops *ops = &sc->ops; 5373 struct ifnet *ifp = sc->sc_ifp; 5374 struct ieee80211com *ic = ifp->if_l2com; 5375 struct ieee80211_node *ni = vap->iv_bss; 5376 struct iwn_node_info node; 5377 uint32_t htflags = 0; 5378 int error; 5379 5380 if (ic->ic_opmode == IEEE80211_M_MONITOR) { 5381 /* Link LED blinks while monitoring. */ 5382 iwn_set_led(sc, IWN_LED_LINK, 5, 5); 5383 return 0; 5384 } 5385 if ((error = iwn_set_timing(sc, ni)) != 0) { 5386 device_printf(sc->sc_dev, 5387 "%s: could not set timing, error %d\n", __func__, error); 5388 return error; 5389 } 5390 5391 /* Update adapter configuration. */ 5392 IEEE80211_ADDR_COPY(sc->rxon.bssid, ni->ni_bssid); 5393 sc->rxon.associd = htole16(IEEE80211_AID(ni->ni_associd)); 5394 sc->rxon.chan = ieee80211_chan2ieee(ic, ni->ni_chan); 5395 sc->rxon.flags = htole32(IWN_RXON_TSF | IWN_RXON_CTS_TO_SELF); 5396 if (IEEE80211_IS_CHAN_2GHZ(ni->ni_chan)) 5397 sc->rxon.flags |= htole32(IWN_RXON_AUTO | IWN_RXON_24GHZ); 5398 if (ic->ic_flags & IEEE80211_F_SHSLOT) 5399 sc->rxon.flags |= htole32(IWN_RXON_SHSLOT); 5400 if (ic->ic_flags & IEEE80211_F_SHPREAMBLE) 5401 sc->rxon.flags |= htole32(IWN_RXON_SHPREAMBLE); 5402 if (IEEE80211_IS_CHAN_A(ni->ni_chan)) { 5403 sc->rxon.cck_mask = 0; 5404 sc->rxon.ofdm_mask = 0x15; 5405 } else if (IEEE80211_IS_CHAN_B(ni->ni_chan)) { 5406 sc->rxon.cck_mask = 0x03; 5407 sc->rxon.ofdm_mask = 0; 5408 } else { 5409 /* Assume 802.11b/g. */ 5410 sc->rxon.cck_mask = 0x0f; 5411 sc->rxon.ofdm_mask = 0x15; 5412 } 5413 if (IEEE80211_IS_CHAN_HT(ni->ni_chan)) { 5414 htflags |= IWN_RXON_HT_PROTMODE(ic->ic_curhtprotmode); 5415 if (IEEE80211_IS_CHAN_HT40(ni->ni_chan)) { 5416 switch (ic->ic_curhtprotmode) { 5417 case IEEE80211_HTINFO_OPMODE_HT20PR: 5418 htflags |= IWN_RXON_HT_MODEPURE40; 5419 break; 5420 default: 5421 htflags |= IWN_RXON_HT_MODEMIXED; 5422 break; 5423 } 5424 } 5425 if (IEEE80211_IS_CHAN_HT40D(ni->ni_chan)) 5426 htflags |= IWN_RXON_HT_HT40MINUS; 5427 } 5428 sc->rxon.flags |= htole32(htflags); 5429 sc->rxon.filter |= htole32(IWN_FILTER_BSS); 5430 DPRINTF(sc, IWN_DEBUG_STATE, "rxon chan %d flags %x\n", 5431 sc->rxon.chan, sc->rxon.flags); 5432 error = iwn_cmd(sc, IWN_CMD_RXON, &sc->rxon, sc->rxonsz, 1); 5433 if (error != 0) { 5434 device_printf(sc->sc_dev, 5435 "%s: could not update configuration, error %d\n", __func__, 5436 error); 5437 return error; 5438 } 5439 5440 /* Configuration has changed, set TX power accordingly. */ 5441 if ((error = ops->set_txpower(sc, ni->ni_chan, 1)) != 0) { 5442 device_printf(sc->sc_dev, 5443 "%s: could not set TX power, error %d\n", __func__, error); 5444 return error; 5445 } 5446 5447 /* Fake a join to initialize the TX rate. */ 5448 ((struct iwn_node *)ni)->id = IWN_ID_BSS; 5449 iwn_newassoc(ni, 1); 5450 5451 /* Add BSS node. */ 5452 memset(&node, 0, sizeof node); 5453 IEEE80211_ADDR_COPY(node.macaddr, ni->ni_macaddr); 5454 node.id = IWN_ID_BSS; 5455 if (IEEE80211_IS_CHAN_HT(ni->ni_chan)) { 5456 switch (ni->ni_htcap & IEEE80211_HTCAP_SMPS) { 5457 case IEEE80211_HTCAP_SMPS_ENA: 5458 node.htflags |= htole32(IWN_SMPS_MIMO_DIS); 5459 break; 5460 case IEEE80211_HTCAP_SMPS_DYNAMIC: 5461 node.htflags |= htole32(IWN_SMPS_MIMO_PROT); 5462 break; 5463 } 5464 node.htflags |= htole32(IWN_AMDPU_SIZE_FACTOR(3) | 5465 IWN_AMDPU_DENSITY(5)); /* 4us */ 5466 if (IEEE80211_IS_CHAN_HT40(ni->ni_chan)) 5467 node.htflags |= htole32(IWN_NODE_HT40); 5468 } 5469 DPRINTF(sc, IWN_DEBUG_STATE, "%s: adding BSS node\n", __func__); 5470 error = ops->add_node(sc, &node, 1); 5471 if (error != 0) { 5472 device_printf(sc->sc_dev, 5473 "%s: could not add BSS node, error %d\n", __func__, error); 5474 return error; 5475 } 5476 DPRINTF(sc, IWN_DEBUG_STATE, "%s: setting link quality for node %d\n", 5477 __func__, node.id); 5478 if ((error = iwn_set_link_quality(sc, ni)) != 0) { 5479 device_printf(sc->sc_dev, 5480 "%s: could not setup link quality for node %d, error %d\n", 5481 __func__, node.id, error); 5482 return error; 5483 } 5484 5485 if ((error = iwn_init_sensitivity(sc)) != 0) { 5486 device_printf(sc->sc_dev, 5487 "%s: could not set sensitivity, error %d\n", __func__, 5488 error); 5489 return error; 5490 } 5491 /* Start periodic calibration timer. */ 5492 sc->calib.state = IWN_CALIB_STATE_ASSOC; 5493 sc->calib_cnt = 0; 5494 callout_reset(&sc->calib_to, msecs_to_ticks(500), iwn_calib_timeout, 5495 sc); 5496 5497 /* Link LED always on while associated. */ 5498 iwn_set_led(sc, IWN_LED_LINK, 0, 1); 5499 return 0; 5500 } 5501 5502 /* 5503 * This function is called by upper layer when an ADDBA request is received 5504 * from another STA and before the ADDBA response is sent. 5505 */ 5506 static int 5507 iwn_ampdu_rx_start(struct ieee80211_node *ni, struct ieee80211_rx_ampdu *rap, 5508 int baparamset, int batimeout, int baseqctl) 5509 { 5510 #define MS(_v, _f) (((_v) & _f) >> _f##_S) 5511 struct iwn_softc *sc = ni->ni_ic->ic_ifp->if_softc; 5512 struct iwn_ops *ops = &sc->ops; 5513 struct iwn_node *wn = (void *)ni; 5514 struct iwn_node_info node; 5515 uint16_t ssn; 5516 uint8_t tid; 5517 int error; 5518 5519 tid = MS(le16toh(baparamset), IEEE80211_BAPS_TID); 5520 ssn = MS(le16toh(baseqctl), IEEE80211_BASEQ_START); 5521 5522 memset(&node, 0, sizeof node); 5523 node.id = wn->id; 5524 node.control = IWN_NODE_UPDATE; 5525 node.flags = IWN_FLAG_SET_ADDBA; 5526 node.addba_tid = tid; 5527 node.addba_ssn = htole16(ssn); 5528 DPRINTF(sc, IWN_DEBUG_RECV, "ADDBA RA=%d TID=%d SSN=%d\n", 5529 wn->id, tid, ssn); 5530 error = ops->add_node(sc, &node, 1); 5531 if (error != 0) 5532 return error; 5533 return sc->sc_ampdu_rx_start(ni, rap, baparamset, batimeout, baseqctl); 5534 #undef MS 5535 } 5536 5537 /* 5538 * This function is called by upper layer on teardown of an HT-immediate 5539 * Block Ack agreement (eg. uppon receipt of a DELBA frame). 5540 */ 5541 static void 5542 iwn_ampdu_rx_stop(struct ieee80211_node *ni, struct ieee80211_rx_ampdu *rap) 5543 { 5544 struct ieee80211com *ic = ni->ni_ic; 5545 struct iwn_softc *sc = ic->ic_ifp->if_softc; 5546 struct iwn_ops *ops = &sc->ops; 5547 struct iwn_node *wn = (void *)ni; 5548 struct iwn_node_info node; 5549 uint8_t tid; 5550 5551 /* XXX: tid as an argument */ 5552 for (tid = 0; tid < WME_NUM_TID; tid++) { 5553 if (&ni->ni_rx_ampdu[tid] == rap) 5554 break; 5555 } 5556 5557 memset(&node, 0, sizeof node); 5558 node.id = wn->id; 5559 node.control = IWN_NODE_UPDATE; 5560 node.flags = IWN_FLAG_SET_DELBA; 5561 node.delba_tid = tid; 5562 DPRINTF(sc, IWN_DEBUG_RECV, "DELBA RA=%d TID=%d\n", wn->id, tid); 5563 (void)ops->add_node(sc, &node, 1); 5564 sc->sc_ampdu_rx_stop(ni, rap); 5565 } 5566 5567 static int 5568 iwn_addba_request(struct ieee80211_node *ni, struct ieee80211_tx_ampdu *tap, 5569 int dialogtoken, int baparamset, int batimeout) 5570 { 5571 struct iwn_softc *sc = ni->ni_ic->ic_ifp->if_softc; 5572 int qid; 5573 5574 for (qid = sc->firstaggqueue; qid < sc->ntxqs; qid++) { 5575 if (sc->qid2tap[qid] == NULL) 5576 break; 5577 } 5578 if (qid == sc->ntxqs) { 5579 DPRINTF(sc, IWN_DEBUG_XMIT, "%s: not free aggregation queue\n", 5580 __func__); 5581 return 0; 5582 } 5583 tap->txa_private = malloc(sizeof(int), M_DEVBUF, M_NOWAIT); 5584 if (tap->txa_private == NULL) { 5585 device_printf(sc->sc_dev, 5586 "%s: failed to alloc TX aggregation structure\n", __func__); 5587 return 0; 5588 } 5589 sc->qid2tap[qid] = tap; 5590 *(int *)tap->txa_private = qid; 5591 return sc->sc_addba_request(ni, tap, dialogtoken, baparamset, 5592 batimeout); 5593 } 5594 5595 static int 5596 iwn_addba_response(struct ieee80211_node *ni, struct ieee80211_tx_ampdu *tap, 5597 int code, int baparamset, int batimeout) 5598 { 5599 struct iwn_softc *sc = ni->ni_ic->ic_ifp->if_softc; 5600 int qid = *(int *)tap->txa_private; 5601 uint8_t tid = WME_AC_TO_TID(tap->txa_ac); 5602 int ret; 5603 5604 if (code == IEEE80211_STATUS_SUCCESS) { 5605 ni->ni_txseqs[tid] = tap->txa_start & 0xfff; 5606 ret = iwn_ampdu_tx_start(ni->ni_ic, ni, tid); 5607 if (ret != 1) 5608 return ret; 5609 } else { 5610 sc->qid2tap[qid] = NULL; 5611 free(tap->txa_private, M_DEVBUF); 5612 tap->txa_private = NULL; 5613 } 5614 return sc->sc_addba_response(ni, tap, code, baparamset, batimeout); 5615 } 5616 5617 /* 5618 * This function is called by upper layer when an ADDBA response is received 5619 * from another STA. 5620 */ 5621 static int 5622 iwn_ampdu_tx_start(struct ieee80211com *ic, struct ieee80211_node *ni, 5623 uint8_t tid) 5624 { 5625 struct ieee80211_tx_ampdu *tap = &ni->ni_tx_ampdu[TID_TO_WME_AC(tid)]; 5626 struct iwn_softc *sc = ni->ni_ic->ic_ifp->if_softc; 5627 struct iwn_ops *ops = &sc->ops; 5628 struct iwn_node *wn = (void *)ni; 5629 struct iwn_node_info node; 5630 int error, qid; 5631 5632 /* Enable TX for the specified RA/TID. */ 5633 wn->disable_tid &= ~(1 << tid); 5634 memset(&node, 0, sizeof node); 5635 node.id = wn->id; 5636 node.control = IWN_NODE_UPDATE; 5637 node.flags = IWN_FLAG_SET_DISABLE_TID; 5638 node.disable_tid = htole16(wn->disable_tid); 5639 error = ops->add_node(sc, &node, 1); 5640 if (error != 0) 5641 return 0; 5642 5643 if ((error = iwn_nic_lock(sc)) != 0) 5644 return 0; 5645 qid = *(int *)tap->txa_private; 5646 ops->ampdu_tx_start(sc, ni, qid, tid, tap->txa_start & 0xfff); 5647 iwn_nic_unlock(sc); 5648 5649 iwn_set_link_quality(sc, ni); 5650 return 1; 5651 } 5652 5653 static void 5654 iwn_ampdu_tx_stop(struct ieee80211_node *ni, struct ieee80211_tx_ampdu *tap) 5655 { 5656 struct iwn_softc *sc = ni->ni_ic->ic_ifp->if_softc; 5657 struct iwn_ops *ops = &sc->ops; 5658 uint8_t tid = WME_AC_TO_TID(tap->txa_ac); 5659 int qid; 5660 5661 if (tap->txa_private == NULL) 5662 return; 5663 5664 qid = *(int *)tap->txa_private; 5665 if (iwn_nic_lock(sc) != 0) 5666 return; 5667 ops->ampdu_tx_stop(sc, qid, tid, tap->txa_start & 0xfff); 5668 iwn_nic_unlock(sc); 5669 sc->qid2tap[qid] = NULL; 5670 free(tap->txa_private, M_DEVBUF); 5671 tap->txa_private = NULL; 5672 sc->sc_addba_stop(ni, tap); 5673 } 5674 5675 static void 5676 iwn4965_ampdu_tx_start(struct iwn_softc *sc, struct ieee80211_node *ni, 5677 int qid, uint8_t tid, uint16_t ssn) 5678 { 5679 struct iwn_node *wn = (void *)ni; 5680 5681 /* Stop TX scheduler while we're changing its configuration. */ 5682 iwn_prph_write(sc, IWN4965_SCHED_QUEUE_STATUS(qid), 5683 IWN4965_TXQ_STATUS_CHGACT); 5684 5685 /* Assign RA/TID translation to the queue. */ 5686 iwn_mem_write_2(sc, sc->sched_base + IWN4965_SCHED_TRANS_TBL(qid), 5687 wn->id << 4 | tid); 5688 5689 /* Enable chain-building mode for the queue. */ 5690 iwn_prph_setbits(sc, IWN4965_SCHED_QCHAIN_SEL, 1 << qid); 5691 5692 /* Set starting sequence number from the ADDBA request. */ 5693 sc->txq[qid].cur = sc->txq[qid].read = (ssn & 0xff); 5694 IWN_WRITE(sc, IWN_HBUS_TARG_WRPTR, qid << 8 | (ssn & 0xff)); 5695 iwn_prph_write(sc, IWN4965_SCHED_QUEUE_RDPTR(qid), ssn); 5696 5697 /* Set scheduler window size. */ 5698 iwn_mem_write(sc, sc->sched_base + IWN4965_SCHED_QUEUE_OFFSET(qid), 5699 IWN_SCHED_WINSZ); 5700 /* Set scheduler frame limit. */ 5701 iwn_mem_write(sc, sc->sched_base + IWN4965_SCHED_QUEUE_OFFSET(qid) + 4, 5702 IWN_SCHED_LIMIT << 16); 5703 5704 /* Enable interrupts for the queue. */ 5705 iwn_prph_setbits(sc, IWN4965_SCHED_INTR_MASK, 1 << qid); 5706 5707 /* Mark the queue as active. */ 5708 iwn_prph_write(sc, IWN4965_SCHED_QUEUE_STATUS(qid), 5709 IWN4965_TXQ_STATUS_ACTIVE | IWN4965_TXQ_STATUS_AGGR_ENA | 5710 iwn_tid2fifo[tid] << 1); 5711 } 5712 5713 static void 5714 iwn4965_ampdu_tx_stop(struct iwn_softc *sc, int qid, uint8_t tid, uint16_t ssn) 5715 { 5716 /* Stop TX scheduler while we're changing its configuration. */ 5717 iwn_prph_write(sc, IWN4965_SCHED_QUEUE_STATUS(qid), 5718 IWN4965_TXQ_STATUS_CHGACT); 5719 5720 /* Set starting sequence number from the ADDBA request. */ 5721 IWN_WRITE(sc, IWN_HBUS_TARG_WRPTR, qid << 8 | (ssn & 0xff)); 5722 iwn_prph_write(sc, IWN4965_SCHED_QUEUE_RDPTR(qid), ssn); 5723 5724 /* Disable interrupts for the queue. */ 5725 iwn_prph_clrbits(sc, IWN4965_SCHED_INTR_MASK, 1 << qid); 5726 5727 /* Mark the queue as inactive. */ 5728 iwn_prph_write(sc, IWN4965_SCHED_QUEUE_STATUS(qid), 5729 IWN4965_TXQ_STATUS_INACTIVE | iwn_tid2fifo[tid] << 1); 5730 } 5731 5732 static void 5733 iwn5000_ampdu_tx_start(struct iwn_softc *sc, struct ieee80211_node *ni, 5734 int qid, uint8_t tid, uint16_t ssn) 5735 { 5736 struct iwn_node *wn = (void *)ni; 5737 5738 /* Stop TX scheduler while we're changing its configuration. */ 5739 iwn_prph_write(sc, IWN5000_SCHED_QUEUE_STATUS(qid), 5740 IWN5000_TXQ_STATUS_CHGACT); 5741 5742 /* Assign RA/TID translation to the queue. */ 5743 iwn_mem_write_2(sc, sc->sched_base + IWN5000_SCHED_TRANS_TBL(qid), 5744 wn->id << 4 | tid); 5745 5746 /* Enable chain-building mode for the queue. */ 5747 iwn_prph_setbits(sc, IWN5000_SCHED_QCHAIN_SEL, 1 << qid); 5748 5749 /* Enable aggregation for the queue. */ 5750 iwn_prph_setbits(sc, IWN5000_SCHED_AGGR_SEL, 1 << qid); 5751 5752 /* Set starting sequence number from the ADDBA request. */ 5753 sc->txq[qid].cur = sc->txq[qid].read = (ssn & 0xff); 5754 IWN_WRITE(sc, IWN_HBUS_TARG_WRPTR, qid << 8 | (ssn & 0xff)); 5755 iwn_prph_write(sc, IWN5000_SCHED_QUEUE_RDPTR(qid), ssn); 5756 5757 /* Set scheduler window size and frame limit. */ 5758 iwn_mem_write(sc, sc->sched_base + IWN5000_SCHED_QUEUE_OFFSET(qid) + 4, 5759 IWN_SCHED_LIMIT << 16 | IWN_SCHED_WINSZ); 5760 5761 /* Enable interrupts for the queue. */ 5762 iwn_prph_setbits(sc, IWN5000_SCHED_INTR_MASK, 1 << qid); 5763 5764 /* Mark the queue as active. */ 5765 iwn_prph_write(sc, IWN5000_SCHED_QUEUE_STATUS(qid), 5766 IWN5000_TXQ_STATUS_ACTIVE | iwn_tid2fifo[tid]); 5767 } 5768 5769 static void 5770 iwn5000_ampdu_tx_stop(struct iwn_softc *sc, int qid, uint8_t tid, uint16_t ssn) 5771 { 5772 /* Stop TX scheduler while we're changing its configuration. */ 5773 iwn_prph_write(sc, IWN5000_SCHED_QUEUE_STATUS(qid), 5774 IWN5000_TXQ_STATUS_CHGACT); 5775 5776 /* Disable aggregation for the queue. */ 5777 iwn_prph_clrbits(sc, IWN5000_SCHED_AGGR_SEL, 1 << qid); 5778 5779 /* Set starting sequence number from the ADDBA request. */ 5780 IWN_WRITE(sc, IWN_HBUS_TARG_WRPTR, qid << 8 | (ssn & 0xff)); 5781 iwn_prph_write(sc, IWN5000_SCHED_QUEUE_RDPTR(qid), ssn); 5782 5783 /* Disable interrupts for the queue. */ 5784 iwn_prph_clrbits(sc, IWN5000_SCHED_INTR_MASK, 1 << qid); 5785 5786 /* Mark the queue as inactive. */ 5787 iwn_prph_write(sc, IWN5000_SCHED_QUEUE_STATUS(qid), 5788 IWN5000_TXQ_STATUS_INACTIVE | iwn_tid2fifo[tid]); 5789 } 5790 5791 /* 5792 * Query calibration tables from the initialization firmware. We do this 5793 * only once at first boot. Called from a process context. 5794 */ 5795 static int 5796 iwn5000_query_calibration(struct iwn_softc *sc) 5797 { 5798 struct iwn5000_calib_config cmd; 5799 int error; 5800 5801 memset(&cmd, 0, sizeof cmd); 5802 cmd.ucode.once.enable = 0xffffffff; 5803 cmd.ucode.once.start = 0xffffffff; 5804 cmd.ucode.once.send = 0xffffffff; 5805 cmd.ucode.flags = 0xffffffff; 5806 DPRINTF(sc, IWN_DEBUG_CALIBRATE, "%s: sending calibration query\n", 5807 __func__); 5808 error = iwn_cmd(sc, IWN5000_CMD_CALIB_CONFIG, &cmd, sizeof cmd, 0); 5809 if (error != 0) 5810 return error; 5811 5812 /* Wait at most two seconds for calibration to complete. */ 5813 if (!(sc->sc_flags & IWN_FLAG_CALIB_DONE)) 5814 error = msleep(sc, &sc->sc_mtx, PCATCH, "iwncal", 2 * hz); 5815 return error; 5816 } 5817 5818 /* 5819 * Send calibration results to the runtime firmware. These results were 5820 * obtained on first boot from the initialization firmware. 5821 */ 5822 static int 5823 iwn5000_send_calibration(struct iwn_softc *sc) 5824 { 5825 int idx, error; 5826 5827 for (idx = 0; idx < 5; idx++) { 5828 if (sc->calibcmd[idx].buf == NULL) 5829 continue; /* No results available. */ 5830 DPRINTF(sc, IWN_DEBUG_CALIBRATE, 5831 "send calibration result idx=%d len=%d\n", idx, 5832 sc->calibcmd[idx].len); 5833 error = iwn_cmd(sc, IWN_CMD_PHY_CALIB, sc->calibcmd[idx].buf, 5834 sc->calibcmd[idx].len, 0); 5835 if (error != 0) { 5836 device_printf(sc->sc_dev, 5837 "%s: could not send calibration result, error %d\n", 5838 __func__, error); 5839 return error; 5840 } 5841 } 5842 return 0; 5843 } 5844 5845 static int 5846 iwn5000_send_wimax_coex(struct iwn_softc *sc) 5847 { 5848 struct iwn5000_wimax_coex wimax; 5849 5850 #ifdef notyet 5851 if (sc->hw_type == IWN_HW_REV_TYPE_6050) { 5852 /* Enable WiMAX coexistence for combo adapters. */ 5853 wimax.flags = 5854 IWN_WIMAX_COEX_ASSOC_WA_UNMASK | 5855 IWN_WIMAX_COEX_UNASSOC_WA_UNMASK | 5856 IWN_WIMAX_COEX_STA_TABLE_VALID | 5857 IWN_WIMAX_COEX_ENABLE; 5858 memcpy(wimax.events, iwn6050_wimax_events, 5859 sizeof iwn6050_wimax_events); 5860 } else 5861 #endif 5862 { 5863 /* Disable WiMAX coexistence. */ 5864 wimax.flags = 0; 5865 memset(wimax.events, 0, sizeof wimax.events); 5866 } 5867 DPRINTF(sc, IWN_DEBUG_RESET, "%s: Configuring WiMAX coexistence\n", 5868 __func__); 5869 return iwn_cmd(sc, IWN5000_CMD_WIMAX_COEX, &wimax, sizeof wimax, 0); 5870 } 5871 5872 static int 5873 iwn5000_crystal_calib(struct iwn_softc *sc) 5874 { 5875 struct iwn5000_phy_calib_crystal cmd; 5876 5877 memset(&cmd, 0, sizeof cmd); 5878 cmd.code = IWN5000_PHY_CALIB_CRYSTAL; 5879 cmd.ngroups = 1; 5880 cmd.isvalid = 1; 5881 cmd.cap_pin[0] = le32toh(sc->eeprom_crystal) & 0xff; 5882 cmd.cap_pin[1] = (le32toh(sc->eeprom_crystal) >> 16) & 0xff; 5883 DPRINTF(sc, IWN_DEBUG_CALIBRATE, "sending crystal calibration %d, %d\n", 5884 cmd.cap_pin[0], cmd.cap_pin[1]); 5885 return iwn_cmd(sc, IWN_CMD_PHY_CALIB, &cmd, sizeof cmd, 0); 5886 } 5887 5888 static int 5889 iwn5000_temp_offset_calib(struct iwn_softc *sc) 5890 { 5891 struct iwn5000_phy_calib_temp_offset cmd; 5892 5893 memset(&cmd, 0, sizeof cmd); 5894 cmd.code = IWN5000_PHY_CALIB_TEMP_OFFSET; 5895 cmd.ngroups = 1; 5896 cmd.isvalid = 1; 5897 if (sc->eeprom_temp != 0) 5898 cmd.offset = htole16(sc->eeprom_temp); 5899 else 5900 cmd.offset = htole16(IWN_DEFAULT_TEMP_OFFSET); 5901 DPRINTF(sc, IWN_DEBUG_CALIBRATE, "setting radio sensor offset to %d\n", 5902 le16toh(cmd.offset)); 5903 return iwn_cmd(sc, IWN_CMD_PHY_CALIB, &cmd, sizeof cmd, 0); 5904 } 5905 5906 /* 5907 * This function is called after the runtime firmware notifies us of its 5908 * readiness (called in a process context). 5909 */ 5910 static int 5911 iwn4965_post_alive(struct iwn_softc *sc) 5912 { 5913 int error, qid; 5914 5915 if ((error = iwn_nic_lock(sc)) != 0) 5916 return error; 5917 5918 /* Clear TX scheduler state in SRAM. */ 5919 sc->sched_base = iwn_prph_read(sc, IWN_SCHED_SRAM_ADDR); 5920 iwn_mem_set_region_4(sc, sc->sched_base + IWN4965_SCHED_CTX_OFF, 0, 5921 IWN4965_SCHED_CTX_LEN / sizeof (uint32_t)); 5922 5923 /* Set physical address of TX scheduler rings (1KB aligned). */ 5924 iwn_prph_write(sc, IWN4965_SCHED_DRAM_ADDR, sc->sched_dma.paddr >> 10); 5925 5926 IWN_SETBITS(sc, IWN_FH_TX_CHICKEN, IWN_FH_TX_CHICKEN_SCHED_RETRY); 5927 5928 /* Disable chain mode for all our 16 queues. */ 5929 iwn_prph_write(sc, IWN4965_SCHED_QCHAIN_SEL, 0); 5930 5931 for (qid = 0; qid < IWN4965_NTXQUEUES; qid++) { 5932 iwn_prph_write(sc, IWN4965_SCHED_QUEUE_RDPTR(qid), 0); 5933 IWN_WRITE(sc, IWN_HBUS_TARG_WRPTR, qid << 8 | 0); 5934 5935 /* Set scheduler window size. */ 5936 iwn_mem_write(sc, sc->sched_base + 5937 IWN4965_SCHED_QUEUE_OFFSET(qid), IWN_SCHED_WINSZ); 5938 /* Set scheduler frame limit. */ 5939 iwn_mem_write(sc, sc->sched_base + 5940 IWN4965_SCHED_QUEUE_OFFSET(qid) + 4, 5941 IWN_SCHED_LIMIT << 16); 5942 } 5943 5944 /* Enable interrupts for all our 16 queues. */ 5945 iwn_prph_write(sc, IWN4965_SCHED_INTR_MASK, 0xffff); 5946 /* Identify TX FIFO rings (0-7). */ 5947 iwn_prph_write(sc, IWN4965_SCHED_TXFACT, 0xff); 5948 5949 /* Mark TX rings (4 EDCA + cmd + 2 HCCA) as active. */ 5950 for (qid = 0; qid < 7; qid++) { 5951 static uint8_t qid2fifo[] = { 3, 2, 1, 0, 4, 5, 6 }; 5952 iwn_prph_write(sc, IWN4965_SCHED_QUEUE_STATUS(qid), 5953 IWN4965_TXQ_STATUS_ACTIVE | qid2fifo[qid] << 1); 5954 } 5955 iwn_nic_unlock(sc); 5956 return 0; 5957 } 5958 5959 /* 5960 * This function is called after the initialization or runtime firmware 5961 * notifies us of its readiness (called in a process context). 5962 */ 5963 static int 5964 iwn5000_post_alive(struct iwn_softc *sc) 5965 { 5966 int error, qid; 5967 5968 /* Switch to using ICT interrupt mode. */ 5969 iwn5000_ict_reset(sc); 5970 5971 if ((error = iwn_nic_lock(sc)) != 0) 5972 return error; 5973 5974 /* Clear TX scheduler state in SRAM. */ 5975 sc->sched_base = iwn_prph_read(sc, IWN_SCHED_SRAM_ADDR); 5976 iwn_mem_set_region_4(sc, sc->sched_base + IWN5000_SCHED_CTX_OFF, 0, 5977 IWN5000_SCHED_CTX_LEN / sizeof (uint32_t)); 5978 5979 /* Set physical address of TX scheduler rings (1KB aligned). */ 5980 iwn_prph_write(sc, IWN5000_SCHED_DRAM_ADDR, sc->sched_dma.paddr >> 10); 5981 5982 IWN_SETBITS(sc, IWN_FH_TX_CHICKEN, IWN_FH_TX_CHICKEN_SCHED_RETRY); 5983 5984 /* Enable chain mode for all queues, except command queue. */ 5985 iwn_prph_write(sc, IWN5000_SCHED_QCHAIN_SEL, 0xfffef); 5986 iwn_prph_write(sc, IWN5000_SCHED_AGGR_SEL, 0); 5987 5988 for (qid = 0; qid < IWN5000_NTXQUEUES; qid++) { 5989 iwn_prph_write(sc, IWN5000_SCHED_QUEUE_RDPTR(qid), 0); 5990 IWN_WRITE(sc, IWN_HBUS_TARG_WRPTR, qid << 8 | 0); 5991 5992 iwn_mem_write(sc, sc->sched_base + 5993 IWN5000_SCHED_QUEUE_OFFSET(qid), 0); 5994 /* Set scheduler window size and frame limit. */ 5995 iwn_mem_write(sc, sc->sched_base + 5996 IWN5000_SCHED_QUEUE_OFFSET(qid) + 4, 5997 IWN_SCHED_LIMIT << 16 | IWN_SCHED_WINSZ); 5998 } 5999 6000 /* Enable interrupts for all our 20 queues. */ 6001 iwn_prph_write(sc, IWN5000_SCHED_INTR_MASK, 0xfffff); 6002 /* Identify TX FIFO rings (0-7). */ 6003 iwn_prph_write(sc, IWN5000_SCHED_TXFACT, 0xff); 6004 6005 /* Mark TX rings (4 EDCA + cmd + 2 HCCA) as active. */ 6006 for (qid = 0; qid < 7; qid++) { 6007 static uint8_t qid2fifo[] = { 3, 2, 1, 0, 7, 5, 6 }; 6008 iwn_prph_write(sc, IWN5000_SCHED_QUEUE_STATUS(qid), 6009 IWN5000_TXQ_STATUS_ACTIVE | qid2fifo[qid]); 6010 } 6011 iwn_nic_unlock(sc); 6012 6013 /* Configure WiMAX coexistence for combo adapters. */ 6014 error = iwn5000_send_wimax_coex(sc); 6015 if (error != 0) { 6016 device_printf(sc->sc_dev, 6017 "%s: could not configure WiMAX coexistence, error %d\n", 6018 __func__, error); 6019 return error; 6020 } 6021 if (sc->hw_type != IWN_HW_REV_TYPE_5150) { 6022 /* Perform crystal calibration. */ 6023 error = iwn5000_crystal_calib(sc); 6024 if (error != 0) { 6025 device_printf(sc->sc_dev, 6026 "%s: crystal calibration failed, error %d\n", 6027 __func__, error); 6028 return error; 6029 } 6030 } 6031 if (!(sc->sc_flags & IWN_FLAG_CALIB_DONE)) { 6032 /* Query calibration from the initialization firmware. */ 6033 if ((error = iwn5000_query_calibration(sc)) != 0) { 6034 device_printf(sc->sc_dev, 6035 "%s: could not query calibration, error %d\n", 6036 __func__, error); 6037 return error; 6038 } 6039 /* 6040 * We have the calibration results now, reboot with the 6041 * runtime firmware (call ourselves recursively!) 6042 */ 6043 iwn_hw_stop(sc); 6044 error = iwn_hw_init(sc); 6045 } else { 6046 /* Send calibration results to runtime firmware. */ 6047 error = iwn5000_send_calibration(sc); 6048 } 6049 return error; 6050 } 6051 6052 /* 6053 * The firmware boot code is small and is intended to be copied directly into 6054 * the NIC internal memory (no DMA transfer). 6055 */ 6056 static int 6057 iwn4965_load_bootcode(struct iwn_softc *sc, const uint8_t *ucode, int size) 6058 { 6059 int error, ntries; 6060 6061 size /= sizeof (uint32_t); 6062 6063 if ((error = iwn_nic_lock(sc)) != 0) 6064 return error; 6065 6066 /* Copy microcode image into NIC memory. */ 6067 iwn_prph_write_region_4(sc, IWN_BSM_SRAM_BASE, 6068 (const uint32_t *)ucode, size); 6069 6070 iwn_prph_write(sc, IWN_BSM_WR_MEM_SRC, 0); 6071 iwn_prph_write(sc, IWN_BSM_WR_MEM_DST, IWN_FW_TEXT_BASE); 6072 iwn_prph_write(sc, IWN_BSM_WR_DWCOUNT, size); 6073 6074 /* Start boot load now. */ 6075 iwn_prph_write(sc, IWN_BSM_WR_CTRL, IWN_BSM_WR_CTRL_START); 6076 6077 /* Wait for transfer to complete. */ 6078 for (ntries = 0; ntries < 1000; ntries++) { 6079 if (!(iwn_prph_read(sc, IWN_BSM_WR_CTRL) & 6080 IWN_BSM_WR_CTRL_START)) 6081 break; 6082 DELAY(10); 6083 } 6084 if (ntries == 1000) { 6085 device_printf(sc->sc_dev, "%s: could not load boot firmware\n", 6086 __func__); 6087 iwn_nic_unlock(sc); 6088 return ETIMEDOUT; 6089 } 6090 6091 /* Enable boot after power up. */ 6092 iwn_prph_write(sc, IWN_BSM_WR_CTRL, IWN_BSM_WR_CTRL_START_EN); 6093 6094 iwn_nic_unlock(sc); 6095 return 0; 6096 } 6097 6098 static int 6099 iwn4965_load_firmware(struct iwn_softc *sc) 6100 { 6101 struct iwn_fw_info *fw = &sc->fw; 6102 struct iwn_dma_info *dma = &sc->fw_dma; 6103 int error; 6104 6105 /* Copy initialization sections into pre-allocated DMA-safe memory. */ 6106 memcpy(dma->vaddr, fw->init.data, fw->init.datasz); 6107 bus_dmamap_sync(dma->tag, dma->map, BUS_DMASYNC_PREWRITE); 6108 memcpy(dma->vaddr + IWN4965_FW_DATA_MAXSZ, 6109 fw->init.text, fw->init.textsz); 6110 bus_dmamap_sync(dma->tag, dma->map, BUS_DMASYNC_PREWRITE); 6111 6112 /* Tell adapter where to find initialization sections. */ 6113 if ((error = iwn_nic_lock(sc)) != 0) 6114 return error; 6115 iwn_prph_write(sc, IWN_BSM_DRAM_DATA_ADDR, dma->paddr >> 4); 6116 iwn_prph_write(sc, IWN_BSM_DRAM_DATA_SIZE, fw->init.datasz); 6117 iwn_prph_write(sc, IWN_BSM_DRAM_TEXT_ADDR, 6118 (dma->paddr + IWN4965_FW_DATA_MAXSZ) >> 4); 6119 iwn_prph_write(sc, IWN_BSM_DRAM_TEXT_SIZE, fw->init.textsz); 6120 iwn_nic_unlock(sc); 6121 6122 /* Load firmware boot code. */ 6123 error = iwn4965_load_bootcode(sc, fw->boot.text, fw->boot.textsz); 6124 if (error != 0) { 6125 device_printf(sc->sc_dev, "%s: could not load boot firmware\n", 6126 __func__); 6127 return error; 6128 } 6129 /* Now press "execute". */ 6130 IWN_WRITE(sc, IWN_RESET, 0); 6131 6132 /* Wait at most one second for first alive notification. */ 6133 if ((error = msleep(sc, &sc->sc_mtx, PCATCH, "iwninit", hz)) != 0) { 6134 device_printf(sc->sc_dev, 6135 "%s: timeout waiting for adapter to initialize, error %d\n", 6136 __func__, error); 6137 return error; 6138 } 6139 6140 /* Retrieve current temperature for initial TX power calibration. */ 6141 sc->rawtemp = sc->ucode_info.temp[3].chan20MHz; 6142 sc->temp = iwn4965_get_temperature(sc); 6143 6144 /* Copy runtime sections into pre-allocated DMA-safe memory. */ 6145 memcpy(dma->vaddr, fw->main.data, fw->main.datasz); 6146 bus_dmamap_sync(dma->tag, dma->map, BUS_DMASYNC_PREWRITE); 6147 memcpy(dma->vaddr + IWN4965_FW_DATA_MAXSZ, 6148 fw->main.text, fw->main.textsz); 6149 bus_dmamap_sync(dma->tag, dma->map, BUS_DMASYNC_PREWRITE); 6150 6151 /* Tell adapter where to find runtime sections. */ 6152 if ((error = iwn_nic_lock(sc)) != 0) 6153 return error; 6154 iwn_prph_write(sc, IWN_BSM_DRAM_DATA_ADDR, dma->paddr >> 4); 6155 iwn_prph_write(sc, IWN_BSM_DRAM_DATA_SIZE, fw->main.datasz); 6156 iwn_prph_write(sc, IWN_BSM_DRAM_TEXT_ADDR, 6157 (dma->paddr + IWN4965_FW_DATA_MAXSZ) >> 4); 6158 iwn_prph_write(sc, IWN_BSM_DRAM_TEXT_SIZE, 6159 IWN_FW_UPDATED | fw->main.textsz); 6160 iwn_nic_unlock(sc); 6161 6162 return 0; 6163 } 6164 6165 static int 6166 iwn5000_load_firmware_section(struct iwn_softc *sc, uint32_t dst, 6167 const uint8_t *section, int size) 6168 { 6169 struct iwn_dma_info *dma = &sc->fw_dma; 6170 int error; 6171 6172 /* Copy firmware section into pre-allocated DMA-safe memory. */ 6173 memcpy(dma->vaddr, section, size); 6174 bus_dmamap_sync(dma->tag, dma->map, BUS_DMASYNC_PREWRITE); 6175 6176 if ((error = iwn_nic_lock(sc)) != 0) 6177 return error; 6178 6179 IWN_WRITE(sc, IWN_FH_TX_CONFIG(IWN_SRVC_DMACHNL), 6180 IWN_FH_TX_CONFIG_DMA_PAUSE); 6181 6182 IWN_WRITE(sc, IWN_FH_SRAM_ADDR(IWN_SRVC_DMACHNL), dst); 6183 IWN_WRITE(sc, IWN_FH_TFBD_CTRL0(IWN_SRVC_DMACHNL), 6184 IWN_LOADDR(dma->paddr)); 6185 IWN_WRITE(sc, IWN_FH_TFBD_CTRL1(IWN_SRVC_DMACHNL), 6186 IWN_HIADDR(dma->paddr) << 28 | size); 6187 IWN_WRITE(sc, IWN_FH_TXBUF_STATUS(IWN_SRVC_DMACHNL), 6188 IWN_FH_TXBUF_STATUS_TBNUM(1) | 6189 IWN_FH_TXBUF_STATUS_TBIDX(1) | 6190 IWN_FH_TXBUF_STATUS_TFBD_VALID); 6191 6192 /* Kick Flow Handler to start DMA transfer. */ 6193 IWN_WRITE(sc, IWN_FH_TX_CONFIG(IWN_SRVC_DMACHNL), 6194 IWN_FH_TX_CONFIG_DMA_ENA | IWN_FH_TX_CONFIG_CIRQ_HOST_ENDTFD); 6195 6196 iwn_nic_unlock(sc); 6197 6198 /* Wait at most five seconds for FH DMA transfer to complete. */ 6199 return msleep(sc, &sc->sc_mtx, PCATCH, "iwninit", 5 * hz); 6200 } 6201 6202 static int 6203 iwn5000_load_firmware(struct iwn_softc *sc) 6204 { 6205 struct iwn_fw_part *fw; 6206 int error; 6207 6208 /* Load the initialization firmware on first boot only. */ 6209 fw = (sc->sc_flags & IWN_FLAG_CALIB_DONE) ? 6210 &sc->fw.main : &sc->fw.init; 6211 6212 error = iwn5000_load_firmware_section(sc, IWN_FW_TEXT_BASE, 6213 fw->text, fw->textsz); 6214 if (error != 0) { 6215 device_printf(sc->sc_dev, 6216 "%s: could not load firmware %s section, error %d\n", 6217 __func__, ".text", error); 6218 return error; 6219 } 6220 error = iwn5000_load_firmware_section(sc, IWN_FW_DATA_BASE, 6221 fw->data, fw->datasz); 6222 if (error != 0) { 6223 device_printf(sc->sc_dev, 6224 "%s: could not load firmware %s section, error %d\n", 6225 __func__, ".data", error); 6226 return error; 6227 } 6228 6229 /* Now press "execute". */ 6230 IWN_WRITE(sc, IWN_RESET, 0); 6231 return 0; 6232 } 6233 6234 /* 6235 * Extract text and data sections from a legacy firmware image. 6236 */ 6237 static int 6238 iwn_read_firmware_leg(struct iwn_softc *sc, struct iwn_fw_info *fw) 6239 { 6240 const uint32_t *ptr; 6241 size_t hdrlen = 24; 6242 uint32_t rev; 6243 6244 ptr = (const uint32_t *)fw->data; 6245 rev = le32toh(*ptr++); 6246 6247 /* Check firmware API version. */ 6248 if (IWN_FW_API(rev) <= 1) { 6249 device_printf(sc->sc_dev, 6250 "%s: bad firmware, need API version >=2\n", __func__); 6251 return EINVAL; 6252 } 6253 if (IWN_FW_API(rev) >= 3) { 6254 /* Skip build number (version 2 header). */ 6255 hdrlen += 4; 6256 ptr++; 6257 } 6258 if (fw->size < hdrlen) { 6259 device_printf(sc->sc_dev, "%s: firmware too short: %zu bytes\n", 6260 __func__, fw->size); 6261 return EINVAL; 6262 } 6263 fw->main.textsz = le32toh(*ptr++); 6264 fw->main.datasz = le32toh(*ptr++); 6265 fw->init.textsz = le32toh(*ptr++); 6266 fw->init.datasz = le32toh(*ptr++); 6267 fw->boot.textsz = le32toh(*ptr++); 6268 6269 /* Check that all firmware sections fit. */ 6270 if (fw->size < hdrlen + fw->main.textsz + fw->main.datasz + 6271 fw->init.textsz + fw->init.datasz + fw->boot.textsz) { 6272 device_printf(sc->sc_dev, "%s: firmware too short: %zu bytes\n", 6273 __func__, fw->size); 6274 return EINVAL; 6275 } 6276 6277 /* Get pointers to firmware sections. */ 6278 fw->main.text = (const uint8_t *)ptr; 6279 fw->main.data = fw->main.text + fw->main.textsz; 6280 fw->init.text = fw->main.data + fw->main.datasz; 6281 fw->init.data = fw->init.text + fw->init.textsz; 6282 fw->boot.text = fw->init.data + fw->init.datasz; 6283 return 0; 6284 } 6285 6286 /* 6287 * Extract text and data sections from a TLV firmware image. 6288 */ 6289 static int 6290 iwn_read_firmware_tlv(struct iwn_softc *sc, struct iwn_fw_info *fw, 6291 uint16_t alt) 6292 { 6293 const struct iwn_fw_tlv_hdr *hdr; 6294 const struct iwn_fw_tlv *tlv; 6295 const uint8_t *ptr, *end; 6296 uint64_t altmask; 6297 uint32_t len, tmp; 6298 6299 if (fw->size < sizeof (*hdr)) { 6300 device_printf(sc->sc_dev, "%s: firmware too short: %zu bytes\n", 6301 __func__, fw->size); 6302 return EINVAL; 6303 } 6304 hdr = (const struct iwn_fw_tlv_hdr *)fw->data; 6305 if (hdr->signature != htole32(IWN_FW_SIGNATURE)) { 6306 device_printf(sc->sc_dev, "%s: bad firmware signature 0x%08x\n", 6307 __func__, le32toh(hdr->signature)); 6308 return EINVAL; 6309 } 6310 DPRINTF(sc, IWN_DEBUG_RESET, "FW: \"%.64s\", build 0x%x\n", hdr->descr, 6311 le32toh(hdr->build)); 6312 6313 /* 6314 * Select the closest supported alternative that is less than 6315 * or equal to the specified one. 6316 */ 6317 altmask = le64toh(hdr->altmask); 6318 while (alt > 0 && !(altmask & (1ULL << alt))) 6319 alt--; /* Downgrade. */ 6320 DPRINTF(sc, IWN_DEBUG_RESET, "using alternative %d\n", alt); 6321 6322 ptr = (const uint8_t *)(hdr + 1); 6323 end = (const uint8_t *)(fw->data + fw->size); 6324 6325 /* Parse type-length-value fields. */ 6326 while (ptr + sizeof (*tlv) <= end) { 6327 tlv = (const struct iwn_fw_tlv *)ptr; 6328 len = le32toh(tlv->len); 6329 6330 ptr += sizeof (*tlv); 6331 if (ptr + len > end) { 6332 device_printf(sc->sc_dev, 6333 "%s: firmware too short: %zu bytes\n", __func__, 6334 fw->size); 6335 return EINVAL; 6336 } 6337 /* Skip other alternatives. */ 6338 if (tlv->alt != 0 && tlv->alt != htole16(alt)) 6339 goto next; 6340 6341 switch (le16toh(tlv->type)) { 6342 case IWN_FW_TLV_MAIN_TEXT: 6343 fw->main.text = ptr; 6344 fw->main.textsz = len; 6345 break; 6346 case IWN_FW_TLV_MAIN_DATA: 6347 fw->main.data = ptr; 6348 fw->main.datasz = len; 6349 break; 6350 case IWN_FW_TLV_INIT_TEXT: 6351 fw->init.text = ptr; 6352 fw->init.textsz = len; 6353 break; 6354 case IWN_FW_TLV_INIT_DATA: 6355 fw->init.data = ptr; 6356 fw->init.datasz = len; 6357 break; 6358 case IWN_FW_TLV_BOOT_TEXT: 6359 fw->boot.text = ptr; 6360 fw->boot.textsz = len; 6361 break; 6362 case IWN_FW_TLV_ENH_SENS: 6363 if (!len) 6364 sc->sc_flags |= IWN_FLAG_ENH_SENS; 6365 break; 6366 case IWN_FW_TLV_PHY_CALIB: 6367 tmp = htole32(*ptr); 6368 if (tmp < 253) { 6369 sc->reset_noise_gain = tmp; 6370 sc->noise_gain = tmp + 1; 6371 } 6372 break; 6373 default: 6374 DPRINTF(sc, IWN_DEBUG_RESET, 6375 "TLV type %d not handled\n", le16toh(tlv->type)); 6376 break; 6377 } 6378 next: /* TLV fields are 32-bit aligned. */ 6379 ptr += (len + 3) & ~3; 6380 } 6381 return 0; 6382 } 6383 6384 static int 6385 iwn_read_firmware(struct iwn_softc *sc) 6386 { 6387 struct iwn_fw_info *fw = &sc->fw; 6388 int error; 6389 6390 IWN_UNLOCK(sc); 6391 6392 memset(fw, 0, sizeof (*fw)); 6393 6394 /* Read firmware image from filesystem. */ 6395 sc->fw_fp = firmware_get(sc->fwname); 6396 if (sc->fw_fp == NULL) { 6397 device_printf(sc->sc_dev, "%s: could not read firmware %s\n", 6398 __func__, sc->fwname); 6399 IWN_LOCK(sc); 6400 return EINVAL; 6401 } 6402 IWN_LOCK(sc); 6403 6404 fw->size = sc->fw_fp->datasize; 6405 fw->data = (const uint8_t *)sc->fw_fp->data; 6406 if (fw->size < sizeof (uint32_t)) { 6407 device_printf(sc->sc_dev, "%s: firmware too short: %zu bytes\n", 6408 __func__, fw->size); 6409 firmware_put(sc->fw_fp, FIRMWARE_UNLOAD); 6410 sc->fw_fp = NULL; 6411 return EINVAL; 6412 } 6413 6414 /* Retrieve text and data sections. */ 6415 if (*(const uint32_t *)fw->data != 0) /* Legacy image. */ 6416 error = iwn_read_firmware_leg(sc, fw); 6417 else 6418 error = iwn_read_firmware_tlv(sc, fw, 1); 6419 if (error != 0) { 6420 device_printf(sc->sc_dev, 6421 "%s: could not read firmware sections, error %d\n", 6422 __func__, error); 6423 firmware_put(sc->fw_fp, FIRMWARE_UNLOAD); 6424 sc->fw_fp = NULL; 6425 return error; 6426 } 6427 6428 /* Make sure text and data sections fit in hardware memory. */ 6429 if (fw->main.textsz > sc->fw_text_maxsz || 6430 fw->main.datasz > sc->fw_data_maxsz || 6431 fw->init.textsz > sc->fw_text_maxsz || 6432 fw->init.datasz > sc->fw_data_maxsz || 6433 fw->boot.textsz > IWN_FW_BOOT_TEXT_MAXSZ || 6434 (fw->boot.textsz & 3) != 0) { 6435 device_printf(sc->sc_dev, "%s: firmware sections too large\n", 6436 __func__); 6437 firmware_put(sc->fw_fp, FIRMWARE_UNLOAD); 6438 sc->fw_fp = NULL; 6439 return EINVAL; 6440 } 6441 6442 /* We can proceed with loading the firmware. */ 6443 return 0; 6444 } 6445 6446 static int 6447 iwn_clock_wait(struct iwn_softc *sc) 6448 { 6449 int ntries; 6450 6451 /* Set "initialization complete" bit. */ 6452 IWN_SETBITS(sc, IWN_GP_CNTRL, IWN_GP_CNTRL_INIT_DONE); 6453 6454 /* Wait for clock stabilization. */ 6455 for (ntries = 0; ntries < 2500; ntries++) { 6456 if (IWN_READ(sc, IWN_GP_CNTRL) & IWN_GP_CNTRL_MAC_CLOCK_READY) 6457 return 0; 6458 DELAY(10); 6459 } 6460 device_printf(sc->sc_dev, 6461 "%s: timeout waiting for clock stabilization\n", __func__); 6462 return ETIMEDOUT; 6463 } 6464 6465 static int 6466 iwn_apm_init(struct iwn_softc *sc) 6467 { 6468 uint32_t reg; 6469 int error; 6470 6471 /* Disable L0s exit timer (NMI bug workaround). */ 6472 IWN_SETBITS(sc, IWN_GIO_CHICKEN, IWN_GIO_CHICKEN_DIS_L0S_TIMER); 6473 /* Don't wait for ICH L0s (ICH bug workaround). */ 6474 IWN_SETBITS(sc, IWN_GIO_CHICKEN, IWN_GIO_CHICKEN_L1A_NO_L0S_RX); 6475 6476 /* Set FH wait threshold to max (HW bug under stress workaround). */ 6477 IWN_SETBITS(sc, IWN_DBG_HPET_MEM, 0xffff0000); 6478 6479 /* Enable HAP INTA to move adapter from L1a to L0s. */ 6480 IWN_SETBITS(sc, IWN_HW_IF_CONFIG, IWN_HW_IF_CONFIG_HAP_WAKE_L1A); 6481 6482 /* Retrieve PCIe Active State Power Management (ASPM). */ 6483 reg = pci_read_config(sc->sc_dev, sc->sc_cap_off + 0x10, 1); 6484 /* Workaround for HW instability in PCIe L0->L0s->L1 transition. */ 6485 if (reg & 0x02) /* L1 Entry enabled. */ 6486 IWN_SETBITS(sc, IWN_GIO, IWN_GIO_L0S_ENA); 6487 else 6488 IWN_CLRBITS(sc, IWN_GIO, IWN_GIO_L0S_ENA); 6489 6490 if (sc->hw_type != IWN_HW_REV_TYPE_4965 && 6491 sc->hw_type <= IWN_HW_REV_TYPE_1000) 6492 IWN_SETBITS(sc, IWN_ANA_PLL, IWN_ANA_PLL_INIT); 6493 6494 /* Wait for clock stabilization before accessing prph. */ 6495 if ((error = iwn_clock_wait(sc)) != 0) 6496 return error; 6497 6498 if ((error = iwn_nic_lock(sc)) != 0) 6499 return error; 6500 if (sc->hw_type == IWN_HW_REV_TYPE_4965) { 6501 /* Enable DMA and BSM (Bootstrap State Machine). */ 6502 iwn_prph_write(sc, IWN_APMG_CLK_EN, 6503 IWN_APMG_CLK_CTRL_DMA_CLK_RQT | 6504 IWN_APMG_CLK_CTRL_BSM_CLK_RQT); 6505 } else { 6506 /* Enable DMA. */ 6507 iwn_prph_write(sc, IWN_APMG_CLK_EN, 6508 IWN_APMG_CLK_CTRL_DMA_CLK_RQT); 6509 } 6510 DELAY(20); 6511 /* Disable L1-Active. */ 6512 iwn_prph_setbits(sc, IWN_APMG_PCI_STT, IWN_APMG_PCI_STT_L1A_DIS); 6513 iwn_nic_unlock(sc); 6514 6515 return 0; 6516 } 6517 6518 static void 6519 iwn_apm_stop_master(struct iwn_softc *sc) 6520 { 6521 int ntries; 6522 6523 /* Stop busmaster DMA activity. */ 6524 IWN_SETBITS(sc, IWN_RESET, IWN_RESET_STOP_MASTER); 6525 for (ntries = 0; ntries < 100; ntries++) { 6526 if (IWN_READ(sc, IWN_RESET) & IWN_RESET_MASTER_DISABLED) 6527 return; 6528 DELAY(10); 6529 } 6530 device_printf(sc->sc_dev, "%s: timeout waiting for master\n", __func__); 6531 } 6532 6533 static void 6534 iwn_apm_stop(struct iwn_softc *sc) 6535 { 6536 iwn_apm_stop_master(sc); 6537 6538 /* Reset the entire device. */ 6539 IWN_SETBITS(sc, IWN_RESET, IWN_RESET_SW); 6540 DELAY(10); 6541 /* Clear "initialization complete" bit. */ 6542 IWN_CLRBITS(sc, IWN_GP_CNTRL, IWN_GP_CNTRL_INIT_DONE); 6543 } 6544 6545 static int 6546 iwn4965_nic_config(struct iwn_softc *sc) 6547 { 6548 if (IWN_RFCFG_TYPE(sc->rfcfg) == 1) { 6549 /* 6550 * I don't believe this to be correct but this is what the 6551 * vendor driver is doing. Probably the bits should not be 6552 * shifted in IWN_RFCFG_*. 6553 */ 6554 IWN_SETBITS(sc, IWN_HW_IF_CONFIG, 6555 IWN_RFCFG_TYPE(sc->rfcfg) | 6556 IWN_RFCFG_STEP(sc->rfcfg) | 6557 IWN_RFCFG_DASH(sc->rfcfg)); 6558 } 6559 IWN_SETBITS(sc, IWN_HW_IF_CONFIG, 6560 IWN_HW_IF_CONFIG_RADIO_SI | IWN_HW_IF_CONFIG_MAC_SI); 6561 return 0; 6562 } 6563 6564 static int 6565 iwn5000_nic_config(struct iwn_softc *sc) 6566 { 6567 uint32_t tmp; 6568 int error; 6569 6570 if (IWN_RFCFG_TYPE(sc->rfcfg) < 3) { 6571 IWN_SETBITS(sc, IWN_HW_IF_CONFIG, 6572 IWN_RFCFG_TYPE(sc->rfcfg) | 6573 IWN_RFCFG_STEP(sc->rfcfg) | 6574 IWN_RFCFG_DASH(sc->rfcfg)); 6575 } 6576 IWN_SETBITS(sc, IWN_HW_IF_CONFIG, 6577 IWN_HW_IF_CONFIG_RADIO_SI | IWN_HW_IF_CONFIG_MAC_SI); 6578 6579 if ((error = iwn_nic_lock(sc)) != 0) 6580 return error; 6581 iwn_prph_setbits(sc, IWN_APMG_PS, IWN_APMG_PS_EARLY_PWROFF_DIS); 6582 6583 if (sc->hw_type == IWN_HW_REV_TYPE_1000) { 6584 /* 6585 * Select first Switching Voltage Regulator (1.32V) to 6586 * solve a stability issue related to noisy DC2DC line 6587 * in the silicon of 1000 Series. 6588 */ 6589 tmp = iwn_prph_read(sc, IWN_APMG_DIGITAL_SVR); 6590 tmp &= ~IWN_APMG_DIGITAL_SVR_VOLTAGE_MASK; 6591 tmp |= IWN_APMG_DIGITAL_SVR_VOLTAGE_1_32; 6592 iwn_prph_write(sc, IWN_APMG_DIGITAL_SVR, tmp); 6593 } 6594 iwn_nic_unlock(sc); 6595 6596 if (sc->sc_flags & IWN_FLAG_INTERNAL_PA) { 6597 /* Use internal power amplifier only. */ 6598 IWN_WRITE(sc, IWN_GP_DRIVER, IWN_GP_DRIVER_RADIO_2X2_IPA); 6599 } 6600 if ((sc->hw_type == IWN_HW_REV_TYPE_6050 || 6601 sc->hw_type == IWN_HW_REV_TYPE_6005) && sc->calib_ver >= 6) { 6602 /* Indicate that ROM calibration version is >=6. */ 6603 IWN_SETBITS(sc, IWN_GP_DRIVER, IWN_GP_DRIVER_CALIB_VER6); 6604 } 6605 if (sc->hw_type == IWN_HW_REV_TYPE_6005) 6606 IWN_SETBITS(sc, IWN_GP_DRIVER, IWN_GP_DRIVER_6050_1X2); 6607 return 0; 6608 } 6609 6610 /* 6611 * Take NIC ownership over Intel Active Management Technology (AMT). 6612 */ 6613 static int 6614 iwn_hw_prepare(struct iwn_softc *sc) 6615 { 6616 int ntries; 6617 6618 /* Check if hardware is ready. */ 6619 IWN_SETBITS(sc, IWN_HW_IF_CONFIG, IWN_HW_IF_CONFIG_NIC_READY); 6620 for (ntries = 0; ntries < 5; ntries++) { 6621 if (IWN_READ(sc, IWN_HW_IF_CONFIG) & 6622 IWN_HW_IF_CONFIG_NIC_READY) 6623 return 0; 6624 DELAY(10); 6625 } 6626 6627 /* Hardware not ready, force into ready state. */ 6628 IWN_SETBITS(sc, IWN_HW_IF_CONFIG, IWN_HW_IF_CONFIG_PREPARE); 6629 for (ntries = 0; ntries < 15000; ntries++) { 6630 if (!(IWN_READ(sc, IWN_HW_IF_CONFIG) & 6631 IWN_HW_IF_CONFIG_PREPARE_DONE)) 6632 break; 6633 DELAY(10); 6634 } 6635 if (ntries == 15000) 6636 return ETIMEDOUT; 6637 6638 /* Hardware should be ready now. */ 6639 IWN_SETBITS(sc, IWN_HW_IF_CONFIG, IWN_HW_IF_CONFIG_NIC_READY); 6640 for (ntries = 0; ntries < 5; ntries++) { 6641 if (IWN_READ(sc, IWN_HW_IF_CONFIG) & 6642 IWN_HW_IF_CONFIG_NIC_READY) 6643 return 0; 6644 DELAY(10); 6645 } 6646 return ETIMEDOUT; 6647 } 6648 6649 static int 6650 iwn_hw_init(struct iwn_softc *sc) 6651 { 6652 struct iwn_ops *ops = &sc->ops; 6653 int error, chnl, qid; 6654 6655 /* Clear pending interrupts. */ 6656 IWN_WRITE(sc, IWN_INT, 0xffffffff); 6657 6658 if ((error = iwn_apm_init(sc)) != 0) { 6659 device_printf(sc->sc_dev, 6660 "%s: could not power ON adapter, error %d\n", __func__, 6661 error); 6662 return error; 6663 } 6664 6665 /* Select VMAIN power source. */ 6666 if ((error = iwn_nic_lock(sc)) != 0) 6667 return error; 6668 iwn_prph_clrbits(sc, IWN_APMG_PS, IWN_APMG_PS_PWR_SRC_MASK); 6669 iwn_nic_unlock(sc); 6670 6671 /* Perform adapter-specific initialization. */ 6672 if ((error = ops->nic_config(sc)) != 0) 6673 return error; 6674 6675 /* Initialize RX ring. */ 6676 if ((error = iwn_nic_lock(sc)) != 0) 6677 return error; 6678 IWN_WRITE(sc, IWN_FH_RX_CONFIG, 0); 6679 IWN_WRITE(sc, IWN_FH_RX_WPTR, 0); 6680 /* Set physical address of RX ring (256-byte aligned). */ 6681 IWN_WRITE(sc, IWN_FH_RX_BASE, sc->rxq.desc_dma.paddr >> 8); 6682 /* Set physical address of RX status (16-byte aligned). */ 6683 IWN_WRITE(sc, IWN_FH_STATUS_WPTR, sc->rxq.stat_dma.paddr >> 4); 6684 /* Enable RX. */ 6685 IWN_WRITE(sc, IWN_FH_RX_CONFIG, 6686 IWN_FH_RX_CONFIG_ENA | 6687 IWN_FH_RX_CONFIG_IGN_RXF_EMPTY | /* HW bug workaround */ 6688 IWN_FH_RX_CONFIG_IRQ_DST_HOST | 6689 IWN_FH_RX_CONFIG_SINGLE_FRAME | 6690 IWN_FH_RX_CONFIG_RB_TIMEOUT(0) | 6691 IWN_FH_RX_CONFIG_NRBD(IWN_RX_RING_COUNT_LOG)); 6692 iwn_nic_unlock(sc); 6693 IWN_WRITE(sc, IWN_FH_RX_WPTR, (IWN_RX_RING_COUNT - 1) & ~7); 6694 6695 if ((error = iwn_nic_lock(sc)) != 0) 6696 return error; 6697 6698 /* Initialize TX scheduler. */ 6699 iwn_prph_write(sc, sc->sched_txfact_addr, 0); 6700 6701 /* Set physical address of "keep warm" page (16-byte aligned). */ 6702 IWN_WRITE(sc, IWN_FH_KW_ADDR, sc->kw_dma.paddr >> 4); 6703 6704 /* Initialize TX rings. */ 6705 for (qid = 0; qid < sc->ntxqs; qid++) { 6706 struct iwn_tx_ring *txq = &sc->txq[qid]; 6707 6708 /* Set physical address of TX ring (256-byte aligned). */ 6709 IWN_WRITE(sc, IWN_FH_CBBC_QUEUE(qid), 6710 txq->desc_dma.paddr >> 8); 6711 } 6712 iwn_nic_unlock(sc); 6713 6714 /* Enable DMA channels. */ 6715 for (chnl = 0; chnl < sc->ndmachnls; chnl++) { 6716 IWN_WRITE(sc, IWN_FH_TX_CONFIG(chnl), 6717 IWN_FH_TX_CONFIG_DMA_ENA | 6718 IWN_FH_TX_CONFIG_DMA_CREDIT_ENA); 6719 } 6720 6721 /* Clear "radio off" and "commands blocked" bits. */ 6722 IWN_WRITE(sc, IWN_UCODE_GP1_CLR, IWN_UCODE_GP1_RFKILL); 6723 IWN_WRITE(sc, IWN_UCODE_GP1_CLR, IWN_UCODE_GP1_CMD_BLOCKED); 6724 6725 /* Clear pending interrupts. */ 6726 IWN_WRITE(sc, IWN_INT, 0xffffffff); 6727 /* Enable interrupt coalescing. */ 6728 IWN_WRITE(sc, IWN_INT_COALESCING, 512 / 8); 6729 /* Enable interrupts. */ 6730 IWN_WRITE(sc, IWN_INT_MASK, sc->int_mask); 6731 6732 /* _Really_ make sure "radio off" bit is cleared! */ 6733 IWN_WRITE(sc, IWN_UCODE_GP1_CLR, IWN_UCODE_GP1_RFKILL); 6734 IWN_WRITE(sc, IWN_UCODE_GP1_CLR, IWN_UCODE_GP1_RFKILL); 6735 6736 /* Enable shadow registers. */ 6737 if (sc->hw_type >= IWN_HW_REV_TYPE_6000) 6738 IWN_SETBITS(sc, IWN_SHADOW_REG_CTRL, 0x800fffff); 6739 6740 if ((error = ops->load_firmware(sc)) != 0) { 6741 device_printf(sc->sc_dev, 6742 "%s: could not load firmware, error %d\n", __func__, 6743 error); 6744 return error; 6745 } 6746 /* Wait at most one second for firmware alive notification. */ 6747 if ((error = msleep(sc, &sc->sc_mtx, PCATCH, "iwninit", hz)) != 0) { 6748 device_printf(sc->sc_dev, 6749 "%s: timeout waiting for adapter to initialize, error %d\n", 6750 __func__, error); 6751 return error; 6752 } 6753 /* Do post-firmware initialization. */ 6754 return ops->post_alive(sc); 6755 } 6756 6757 static void 6758 iwn_hw_stop(struct iwn_softc *sc) 6759 { 6760 int chnl, qid, ntries; 6761 6762 IWN_WRITE(sc, IWN_RESET, IWN_RESET_NEVO); 6763 6764 /* Disable interrupts. */ 6765 IWN_WRITE(sc, IWN_INT_MASK, 0); 6766 IWN_WRITE(sc, IWN_INT, 0xffffffff); 6767 IWN_WRITE(sc, IWN_FH_INT, 0xffffffff); 6768 sc->sc_flags &= ~IWN_FLAG_USE_ICT; 6769 6770 /* Make sure we no longer hold the NIC lock. */ 6771 iwn_nic_unlock(sc); 6772 6773 /* Stop TX scheduler. */ 6774 iwn_prph_write(sc, sc->sched_txfact_addr, 0); 6775 6776 /* Stop all DMA channels. */ 6777 if (iwn_nic_lock(sc) == 0) { 6778 for (chnl = 0; chnl < sc->ndmachnls; chnl++) { 6779 IWN_WRITE(sc, IWN_FH_TX_CONFIG(chnl), 0); 6780 for (ntries = 0; ntries < 200; ntries++) { 6781 if (IWN_READ(sc, IWN_FH_TX_STATUS) & 6782 IWN_FH_TX_STATUS_IDLE(chnl)) 6783 break; 6784 DELAY(10); 6785 } 6786 } 6787 iwn_nic_unlock(sc); 6788 } 6789 6790 /* Stop RX ring. */ 6791 iwn_reset_rx_ring(sc, &sc->rxq); 6792 6793 /* Reset all TX rings. */ 6794 for (qid = 0; qid < sc->ntxqs; qid++) 6795 iwn_reset_tx_ring(sc, &sc->txq[qid]); 6796 6797 if (iwn_nic_lock(sc) == 0) { 6798 iwn_prph_write(sc, IWN_APMG_CLK_DIS, 6799 IWN_APMG_CLK_CTRL_DMA_CLK_RQT); 6800 iwn_nic_unlock(sc); 6801 } 6802 DELAY(5); 6803 /* Power OFF adapter. */ 6804 iwn_apm_stop(sc); 6805 } 6806 6807 static void 6808 iwn_radio_on(void *arg0, int pending) 6809 { 6810 struct iwn_softc *sc = arg0; 6811 struct ifnet *ifp = sc->sc_ifp; 6812 struct ieee80211com *ic = ifp->if_l2com; 6813 struct ieee80211vap *vap = TAILQ_FIRST(&ic->ic_vaps); 6814 6815 if (vap != NULL) { 6816 iwn_init(sc); 6817 ieee80211_init(vap); 6818 } 6819 } 6820 6821 static void 6822 iwn_radio_off(void *arg0, int pending) 6823 { 6824 struct iwn_softc *sc = arg0; 6825 struct ifnet *ifp = sc->sc_ifp; 6826 struct ieee80211com *ic = ifp->if_l2com; 6827 struct ieee80211vap *vap = TAILQ_FIRST(&ic->ic_vaps); 6828 6829 iwn_stop(sc); 6830 if (vap != NULL) 6831 ieee80211_stop(vap); 6832 6833 /* Enable interrupts to get RF toggle notification. */ 6834 IWN_LOCK(sc); 6835 IWN_WRITE(sc, IWN_INT, 0xffffffff); 6836 IWN_WRITE(sc, IWN_INT_MASK, sc->int_mask); 6837 IWN_UNLOCK(sc); 6838 } 6839 6840 static void 6841 iwn_init_locked(struct iwn_softc *sc) 6842 { 6843 struct ifnet *ifp = sc->sc_ifp; 6844 int error; 6845 6846 IWN_LOCK_ASSERT(sc); 6847 6848 if ((error = iwn_hw_prepare(sc)) != 0) { 6849 device_printf(sc->sc_dev, "%s: hardware not ready, error %d\n", 6850 __func__, error); 6851 goto fail; 6852 } 6853 6854 /* Initialize interrupt mask to default value. */ 6855 sc->int_mask = IWN_INT_MASK_DEF; 6856 sc->sc_flags &= ~IWN_FLAG_USE_ICT; 6857 6858 /* Check that the radio is not disabled by hardware switch. */ 6859 if (!(IWN_READ(sc, IWN_GP_CNTRL) & IWN_GP_CNTRL_RFKILL)) { 6860 device_printf(sc->sc_dev, 6861 "radio is disabled by hardware switch\n"); 6862 /* Enable interrupts to get RF toggle notifications. */ 6863 IWN_WRITE(sc, IWN_INT, 0xffffffff); 6864 IWN_WRITE(sc, IWN_INT_MASK, sc->int_mask); 6865 return; 6866 } 6867 6868 /* Read firmware images from the filesystem. */ 6869 if ((error = iwn_read_firmware(sc)) != 0) { 6870 device_printf(sc->sc_dev, 6871 "%s: could not read firmware, error %d\n", __func__, 6872 error); 6873 goto fail; 6874 } 6875 6876 /* Initialize hardware and upload firmware. */ 6877 error = iwn_hw_init(sc); 6878 firmware_put(sc->fw_fp, FIRMWARE_UNLOAD); 6879 sc->fw_fp = NULL; 6880 if (error != 0) { 6881 device_printf(sc->sc_dev, 6882 "%s: could not initialize hardware, error %d\n", __func__, 6883 error); 6884 goto fail; 6885 } 6886 6887 /* Configure adapter now that it is ready. */ 6888 if ((error = iwn_config(sc)) != 0) { 6889 device_printf(sc->sc_dev, 6890 "%s: could not configure device, error %d\n", __func__, 6891 error); 6892 goto fail; 6893 } 6894 6895 ifp->if_drv_flags &= ~IFF_DRV_OACTIVE; 6896 ifp->if_drv_flags |= IFF_DRV_RUNNING; 6897 6898 callout_reset(&sc->watchdog_to, hz, iwn_watchdog, sc); 6899 return; 6900 6901 fail: iwn_stop_locked(sc); 6902 } 6903 6904 static void 6905 iwn_init(void *arg) 6906 { 6907 struct iwn_softc *sc = arg; 6908 struct ifnet *ifp = sc->sc_ifp; 6909 struct ieee80211com *ic = ifp->if_l2com; 6910 6911 IWN_LOCK(sc); 6912 iwn_init_locked(sc); 6913 IWN_UNLOCK(sc); 6914 6915 if (ifp->if_drv_flags & IFF_DRV_RUNNING) 6916 ieee80211_start_all(ic); 6917 } 6918 6919 static void 6920 iwn_stop_locked(struct iwn_softc *sc) 6921 { 6922 struct ifnet *ifp = sc->sc_ifp; 6923 6924 IWN_LOCK_ASSERT(sc); 6925 6926 sc->sc_tx_timer = 0; 6927 callout_stop(&sc->watchdog_to); 6928 callout_stop(&sc->calib_to); 6929 ifp->if_drv_flags &= ~(IFF_DRV_RUNNING | IFF_DRV_OACTIVE); 6930 6931 /* Power OFF hardware. */ 6932 iwn_hw_stop(sc); 6933 } 6934 6935 static void 6936 iwn_stop(struct iwn_softc *sc) 6937 { 6938 IWN_LOCK(sc); 6939 iwn_stop_locked(sc); 6940 IWN_UNLOCK(sc); 6941 } 6942 6943 /* 6944 * Callback from net80211 to start a scan. 6945 */ 6946 static void 6947 iwn_scan_start(struct ieee80211com *ic) 6948 { 6949 struct ifnet *ifp = ic->ic_ifp; 6950 struct iwn_softc *sc = ifp->if_softc; 6951 6952 IWN_LOCK(sc); 6953 /* make the link LED blink while we're scanning */ 6954 iwn_set_led(sc, IWN_LED_LINK, 20, 2); 6955 IWN_UNLOCK(sc); 6956 } 6957 6958 /* 6959 * Callback from net80211 to terminate a scan. 6960 */ 6961 static void 6962 iwn_scan_end(struct ieee80211com *ic) 6963 { 6964 struct ifnet *ifp = ic->ic_ifp; 6965 struct iwn_softc *sc = ifp->if_softc; 6966 struct ieee80211vap *vap = TAILQ_FIRST(&ic->ic_vaps); 6967 6968 IWN_LOCK(sc); 6969 if (vap->iv_state == IEEE80211_S_RUN) { 6970 /* Set link LED to ON status if we are associated */ 6971 iwn_set_led(sc, IWN_LED_LINK, 0, 1); 6972 } 6973 IWN_UNLOCK(sc); 6974 } 6975 6976 /* 6977 * Callback from net80211 to force a channel change. 6978 */ 6979 static void 6980 iwn_set_channel(struct ieee80211com *ic) 6981 { 6982 const struct ieee80211_channel *c = ic->ic_curchan; 6983 struct ifnet *ifp = ic->ic_ifp; 6984 struct iwn_softc *sc = ifp->if_softc; 6985 int error; 6986 6987 IWN_LOCK(sc); 6988 sc->sc_rxtap.wr_chan_freq = htole16(c->ic_freq); 6989 sc->sc_rxtap.wr_chan_flags = htole16(c->ic_flags); 6990 sc->sc_txtap.wt_chan_freq = htole16(c->ic_freq); 6991 sc->sc_txtap.wt_chan_flags = htole16(c->ic_flags); 6992 6993 /* 6994 * Only need to set the channel in Monitor mode. AP scanning and auth 6995 * are already taken care of by their respective firmware commands. 6996 */ 6997 if (ic->ic_opmode == IEEE80211_M_MONITOR) { 6998 error = iwn_config(sc); 6999 if (error != 0) 7000 device_printf(sc->sc_dev, 7001 "%s: error %d settting channel\n", __func__, error); 7002 } 7003 IWN_UNLOCK(sc); 7004 } 7005 7006 /* 7007 * Callback from net80211 to start scanning of the current channel. 7008 */ 7009 static void 7010 iwn_scan_curchan(struct ieee80211_scan_state *ss, unsigned long maxdwell) 7011 { 7012 struct ieee80211vap *vap = ss->ss_vap; 7013 struct iwn_softc *sc = vap->iv_ic->ic_ifp->if_softc; 7014 int error; 7015 7016 IWN_LOCK(sc); 7017 error = iwn_scan(sc); 7018 IWN_UNLOCK(sc); 7019 if (error != 0) 7020 ieee80211_cancel_scan(vap); 7021 } 7022 7023 /* 7024 * Callback from net80211 to handle the minimum dwell time being met. 7025 * The intent is to terminate the scan but we just let the firmware 7026 * notify us when it's finished as we have no safe way to abort it. 7027 */ 7028 static void 7029 iwn_scan_mindwell(struct ieee80211_scan_state *ss) 7030 { 7031 /* NB: don't try to abort scan; wait for firmware to finish */ 7032 } 7033 7034 static void 7035 iwn_hw_reset(void *arg0, int pending) 7036 { 7037 struct iwn_softc *sc = arg0; 7038 struct ifnet *ifp = sc->sc_ifp; 7039 struct ieee80211com *ic = ifp->if_l2com; 7040 7041 iwn_stop(sc); 7042 iwn_init(sc); 7043 ieee80211_notify_radio(ic, 1); 7044 } 7045