1 /*- 2 * Copyright (c) 2007-2009 Damien Bergamini <damien.bergamini@free.fr> 3 * Copyright (c) 2008 Benjamin Close <benjsc@FreeBSD.org> 4 * Copyright (c) 2008 Sam Leffler, Errno Consulting 5 * Copyright (c) 2011 Intel Corporation 6 * Copyright (c) 2013 Cedric GROSS <c.gross@kreiz-it.fr> 7 * Copyright (c) 2013 Adrian Chadd <adrian@FreeBSD.org> 8 * 9 * Permission to use, copy, modify, and distribute this software for any 10 * purpose with or without fee is hereby granted, provided that the above 11 * copyright notice and this permission notice appear in all copies. 12 * 13 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 14 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 15 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR 16 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 17 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN 18 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF 19 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 20 */ 21 22 /* 23 * Driver for Intel WiFi Link 4965 and 1000/5000/6000 Series 802.11 network 24 * adapters. 25 */ 26 27 #include <sys/cdefs.h> 28 #include "opt_wlan.h" 29 #include "opt_iwn.h" 30 31 #include <sys/param.h> 32 #include <sys/sockio.h> 33 #include <sys/sysctl.h> 34 #include <sys/mbuf.h> 35 #include <sys/kernel.h> 36 #include <sys/socket.h> 37 #include <sys/systm.h> 38 #include <sys/malloc.h> 39 #include <sys/bus.h> 40 #include <sys/conf.h> 41 #include <sys/rman.h> 42 #include <sys/endian.h> 43 #include <sys/firmware.h> 44 #include <sys/limits.h> 45 #include <sys/module.h> 46 #include <sys/priv.h> 47 #include <sys/queue.h> 48 #include <sys/taskqueue.h> 49 50 #include <machine/bus.h> 51 #include <machine/resource.h> 52 #include <machine/clock.h> 53 54 #include <dev/pci/pcireg.h> 55 #include <dev/pci/pcivar.h> 56 57 #include <net/if.h> 58 #include <net/if_var.h> 59 #include <net/if_dl.h> 60 #include <net/if_media.h> 61 62 #include <netinet/in.h> 63 #include <netinet/if_ether.h> 64 65 #include <net80211/ieee80211_var.h> 66 #include <net80211/ieee80211_radiotap.h> 67 #include <net80211/ieee80211_regdomain.h> 68 #include <net80211/ieee80211_ratectl.h> 69 70 #include <dev/iwn/if_iwnreg.h> 71 #include <dev/iwn/if_iwnvar.h> 72 #include <dev/iwn/if_iwn_devid.h> 73 #include <dev/iwn/if_iwn_chip_cfg.h> 74 #include <dev/iwn/if_iwn_debug.h> 75 #include <dev/iwn/if_iwn_ioctl.h> 76 77 struct iwn_ident { 78 uint16_t vendor; 79 uint16_t device; 80 const char *name; 81 }; 82 83 static const struct iwn_ident iwn_ident_table[] = { 84 { 0x8086, IWN_DID_6x05_1, "Intel Centrino Advanced-N 6205" }, 85 { 0x8086, IWN_DID_1000_1, "Intel Centrino Wireless-N 1000" }, 86 { 0x8086, IWN_DID_1000_2, "Intel Centrino Wireless-N 1000" }, 87 { 0x8086, IWN_DID_6x05_2, "Intel Centrino Advanced-N 6205" }, 88 { 0x8086, IWN_DID_6050_1, "Intel Centrino Advanced-N + WiMAX 6250" }, 89 { 0x8086, IWN_DID_6050_2, "Intel Centrino Advanced-N + WiMAX 6250" }, 90 { 0x8086, IWN_DID_x030_1, "Intel Centrino Wireless-N 1030" }, 91 { 0x8086, IWN_DID_x030_2, "Intel Centrino Wireless-N 1030" }, 92 { 0x8086, IWN_DID_x030_3, "Intel Centrino Advanced-N 6230" }, 93 { 0x8086, IWN_DID_x030_4, "Intel Centrino Advanced-N 6230" }, 94 { 0x8086, IWN_DID_6150_1, "Intel Centrino Wireless-N + WiMAX 6150" }, 95 { 0x8086, IWN_DID_6150_2, "Intel Centrino Wireless-N + WiMAX 6150" }, 96 { 0x8086, IWN_DID_2x00_1, "Intel(R) Centrino(R) Wireless-N 2200 BGN" }, 97 { 0x8086, IWN_DID_2x00_2, "Intel(R) Centrino(R) Wireless-N 2200 BGN" }, 98 /* XXX 2200D is IWN_SDID_2x00_4; there's no way to express this here! */ 99 { 0x8086, IWN_DID_2x30_1, "Intel Centrino Wireless-N 2230" }, 100 { 0x8086, IWN_DID_2x30_2, "Intel Centrino Wireless-N 2230" }, 101 { 0x8086, IWN_DID_130_1, "Intel Centrino Wireless-N 130" }, 102 { 0x8086, IWN_DID_130_2, "Intel Centrino Wireless-N 130" }, 103 { 0x8086, IWN_DID_100_1, "Intel Centrino Wireless-N 100" }, 104 { 0x8086, IWN_DID_100_2, "Intel Centrino Wireless-N 100" }, 105 { 0x8086, IWN_DID_105_1, "Intel Centrino Wireless-N 105" }, 106 { 0x8086, IWN_DID_105_2, "Intel Centrino Wireless-N 105" }, 107 { 0x8086, IWN_DID_135_1, "Intel Centrino Wireless-N 135" }, 108 { 0x8086, IWN_DID_135_2, "Intel Centrino Wireless-N 135" }, 109 { 0x8086, IWN_DID_4965_1, "Intel Wireless WiFi Link 4965" }, 110 { 0x8086, IWN_DID_6x00_1, "Intel Centrino Ultimate-N 6300" }, 111 { 0x8086, IWN_DID_6x00_2, "Intel Centrino Advanced-N 6200" }, 112 { 0x8086, IWN_DID_4965_2, "Intel Wireless WiFi Link 4965" }, 113 { 0x8086, IWN_DID_4965_3, "Intel Wireless WiFi Link 4965" }, 114 { 0x8086, IWN_DID_5x00_1, "Intel WiFi Link 5100" }, 115 { 0x8086, IWN_DID_4965_4, "Intel Wireless WiFi Link 4965" }, 116 { 0x8086, IWN_DID_5x00_3, "Intel Ultimate N WiFi Link 5300" }, 117 { 0x8086, IWN_DID_5x00_4, "Intel Ultimate N WiFi Link 5300" }, 118 { 0x8086, IWN_DID_5x00_2, "Intel WiFi Link 5100" }, 119 { 0x8086, IWN_DID_6x00_3, "Intel Centrino Ultimate-N 6300" }, 120 { 0x8086, IWN_DID_6x00_4, "Intel Centrino Advanced-N 6200" }, 121 { 0x8086, IWN_DID_5x50_1, "Intel WiMAX/WiFi Link 5350" }, 122 { 0x8086, IWN_DID_5x50_2, "Intel WiMAX/WiFi Link 5350" }, 123 { 0x8086, IWN_DID_5x50_3, "Intel WiMAX/WiFi Link 5150" }, 124 { 0x8086, IWN_DID_5x50_4, "Intel WiMAX/WiFi Link 5150" }, 125 { 0x8086, IWN_DID_6035_1, "Intel Centrino Advanced 6235" }, 126 { 0x8086, IWN_DID_6035_2, "Intel Centrino Advanced 6235" }, 127 { 0, 0, NULL } 128 }; 129 130 static int iwn_probe(device_t); 131 static int iwn_attach(device_t); 132 static void iwn4965_attach(struct iwn_softc *, uint16_t); 133 static void iwn5000_attach(struct iwn_softc *, uint16_t); 134 static int iwn_config_specific(struct iwn_softc *, uint16_t); 135 static void iwn_radiotap_attach(struct iwn_softc *); 136 static void iwn_sysctlattach(struct iwn_softc *); 137 static struct ieee80211vap *iwn_vap_create(struct ieee80211com *, 138 const char [IFNAMSIZ], int, enum ieee80211_opmode, int, 139 const uint8_t [IEEE80211_ADDR_LEN], 140 const uint8_t [IEEE80211_ADDR_LEN]); 141 static void iwn_vap_delete(struct ieee80211vap *); 142 static int iwn_detach(device_t); 143 static int iwn_shutdown(device_t); 144 static int iwn_suspend(device_t); 145 static int iwn_resume(device_t); 146 static int iwn_nic_lock(struct iwn_softc *); 147 static int iwn_eeprom_lock(struct iwn_softc *); 148 static int iwn_init_otprom(struct iwn_softc *); 149 static int iwn_read_prom_data(struct iwn_softc *, uint32_t, void *, int); 150 static void iwn_dma_map_addr(void *, bus_dma_segment_t *, int, int); 151 static int iwn_dma_contig_alloc(struct iwn_softc *, struct iwn_dma_info *, 152 void **, bus_size_t, bus_size_t); 153 static void iwn_dma_contig_free(struct iwn_dma_info *); 154 static int iwn_alloc_sched(struct iwn_softc *); 155 static void iwn_free_sched(struct iwn_softc *); 156 static int iwn_alloc_kw(struct iwn_softc *); 157 static void iwn_free_kw(struct iwn_softc *); 158 static int iwn_alloc_ict(struct iwn_softc *); 159 static void iwn_free_ict(struct iwn_softc *); 160 static int iwn_alloc_fwmem(struct iwn_softc *); 161 static void iwn_free_fwmem(struct iwn_softc *); 162 static int iwn_alloc_rx_ring(struct iwn_softc *, struct iwn_rx_ring *); 163 static void iwn_reset_rx_ring(struct iwn_softc *, struct iwn_rx_ring *); 164 static void iwn_free_rx_ring(struct iwn_softc *, struct iwn_rx_ring *); 165 static int iwn_alloc_tx_ring(struct iwn_softc *, struct iwn_tx_ring *, 166 int); 167 static void iwn_reset_tx_ring(struct iwn_softc *, struct iwn_tx_ring *); 168 static void iwn_free_tx_ring(struct iwn_softc *, struct iwn_tx_ring *); 169 static void iwn_check_tx_ring(struct iwn_softc *, int); 170 static void iwn5000_ict_reset(struct iwn_softc *); 171 static int iwn_read_eeprom(struct iwn_softc *, 172 uint8_t macaddr[IEEE80211_ADDR_LEN]); 173 static void iwn4965_read_eeprom(struct iwn_softc *); 174 #ifdef IWN_DEBUG 175 static void iwn4965_print_power_group(struct iwn_softc *, int); 176 #endif 177 static void iwn5000_read_eeprom(struct iwn_softc *); 178 static uint32_t iwn_eeprom_channel_flags(struct iwn_eeprom_chan *); 179 static void iwn_read_eeprom_band(struct iwn_softc *, int, int, int *, 180 struct ieee80211_channel[]); 181 static void iwn_read_eeprom_ht40(struct iwn_softc *, int, int, int *, 182 struct ieee80211_channel[]); 183 static void iwn_read_eeprom_channels(struct iwn_softc *, int, uint32_t); 184 static struct iwn_eeprom_chan *iwn_find_eeprom_channel(struct iwn_softc *, 185 struct ieee80211_channel *); 186 static void iwn_getradiocaps(struct ieee80211com *, int, int *, 187 struct ieee80211_channel[]); 188 static int iwn_setregdomain(struct ieee80211com *, 189 struct ieee80211_regdomain *, int, 190 struct ieee80211_channel[]); 191 static void iwn_read_eeprom_enhinfo(struct iwn_softc *); 192 static struct ieee80211_node *iwn_node_alloc(struct ieee80211vap *, 193 const uint8_t mac[IEEE80211_ADDR_LEN]); 194 static void iwn_newassoc(struct ieee80211_node *, int); 195 static int iwn_newstate(struct ieee80211vap *, enum ieee80211_state, int); 196 static void iwn_calib_timeout(void *); 197 static void iwn_rx_phy(struct iwn_softc *, struct iwn_rx_desc *); 198 static void iwn_rx_done(struct iwn_softc *, struct iwn_rx_desc *, 199 struct iwn_rx_data *); 200 static void iwn_agg_tx_complete(struct iwn_softc *, struct iwn_tx_ring *, 201 int, int, int); 202 static void iwn_rx_compressed_ba(struct iwn_softc *, struct iwn_rx_desc *); 203 static void iwn5000_rx_calib_results(struct iwn_softc *, 204 struct iwn_rx_desc *); 205 static void iwn_rx_statistics(struct iwn_softc *, struct iwn_rx_desc *); 206 static void iwn4965_tx_done(struct iwn_softc *, struct iwn_rx_desc *, 207 struct iwn_rx_data *); 208 static void iwn5000_tx_done(struct iwn_softc *, struct iwn_rx_desc *, 209 struct iwn_rx_data *); 210 static void iwn_adj_ampdu_ptr(struct iwn_softc *, struct iwn_tx_ring *); 211 static void iwn_tx_done(struct iwn_softc *, struct iwn_rx_desc *, int, int, 212 uint8_t); 213 static int iwn_ampdu_check_bitmap(uint64_t, int, int); 214 static int iwn_ampdu_index_check(struct iwn_softc *, struct iwn_tx_ring *, 215 uint64_t, int, int); 216 static void iwn_ampdu_tx_done(struct iwn_softc *, int, int, int, void *); 217 static void iwn_cmd_done(struct iwn_softc *, struct iwn_rx_desc *); 218 static void iwn_notif_intr(struct iwn_softc *); 219 static void iwn_wakeup_intr(struct iwn_softc *); 220 static void iwn_rftoggle_task(void *, int); 221 static void iwn_fatal_intr(struct iwn_softc *); 222 static void iwn_intr(void *); 223 static void iwn4965_update_sched(struct iwn_softc *, int, int, uint8_t, 224 uint16_t); 225 static void iwn5000_update_sched(struct iwn_softc *, int, int, uint8_t, 226 uint16_t); 227 #ifdef notyet 228 static void iwn5000_reset_sched(struct iwn_softc *, int, int); 229 #endif 230 static int iwn_tx_data(struct iwn_softc *, struct mbuf *, 231 struct ieee80211_node *); 232 static int iwn_tx_data_raw(struct iwn_softc *, struct mbuf *, 233 struct ieee80211_node *, 234 const struct ieee80211_bpf_params *params); 235 static int iwn_tx_cmd(struct iwn_softc *, struct mbuf *, 236 struct ieee80211_node *, struct iwn_tx_ring *); 237 static void iwn_xmit_task(void *arg0, int pending); 238 static int iwn_raw_xmit(struct ieee80211_node *, struct mbuf *, 239 const struct ieee80211_bpf_params *); 240 static int iwn_transmit(struct ieee80211com *, struct mbuf *); 241 static void iwn_scan_timeout(void *); 242 static void iwn_watchdog(void *); 243 static int iwn_ioctl(struct ieee80211com *, u_long , void *); 244 static void iwn_parent(struct ieee80211com *); 245 static int iwn_cmd(struct iwn_softc *, int, const void *, int, int); 246 static int iwn4965_add_node(struct iwn_softc *, struct iwn_node_info *, 247 int); 248 static int iwn5000_add_node(struct iwn_softc *, struct iwn_node_info *, 249 int); 250 static int iwn_set_link_quality(struct iwn_softc *, 251 struct ieee80211_node *); 252 static int iwn_add_broadcast_node(struct iwn_softc *, int); 253 static int iwn_updateedca(struct ieee80211com *); 254 static void iwn_set_promisc(struct iwn_softc *); 255 static void iwn_update_promisc(struct ieee80211com *); 256 static void iwn_update_mcast(struct ieee80211com *); 257 static void iwn_set_led(struct iwn_softc *, uint8_t, uint8_t, uint8_t); 258 static int iwn_set_critical_temp(struct iwn_softc *); 259 static int iwn_set_timing(struct iwn_softc *, struct ieee80211_node *); 260 static void iwn4965_power_calibration(struct iwn_softc *, int); 261 static int iwn4965_set_txpower(struct iwn_softc *, int); 262 static int iwn5000_set_txpower(struct iwn_softc *, int); 263 static int iwn4965_get_rssi(struct iwn_softc *, struct iwn_rx_stat *); 264 static int iwn5000_get_rssi(struct iwn_softc *, struct iwn_rx_stat *); 265 static int iwn_get_noise(const struct iwn_rx_general_stats *); 266 static int iwn4965_get_temperature(struct iwn_softc *); 267 static int iwn5000_get_temperature(struct iwn_softc *); 268 static int iwn_init_sensitivity(struct iwn_softc *); 269 static void iwn_collect_noise(struct iwn_softc *, 270 const struct iwn_rx_general_stats *); 271 static int iwn4965_init_gains(struct iwn_softc *); 272 static int iwn5000_init_gains(struct iwn_softc *); 273 static int iwn4965_set_gains(struct iwn_softc *); 274 static int iwn5000_set_gains(struct iwn_softc *); 275 static void iwn_tune_sensitivity(struct iwn_softc *, 276 const struct iwn_rx_stats *); 277 static void iwn_save_stats_counters(struct iwn_softc *, 278 const struct iwn_stats *); 279 static int iwn_send_sensitivity(struct iwn_softc *); 280 static void iwn_check_rx_recovery(struct iwn_softc *, struct iwn_stats *); 281 static int iwn_set_pslevel(struct iwn_softc *, int, int, int); 282 static int iwn_send_btcoex(struct iwn_softc *); 283 static int iwn_send_advanced_btcoex(struct iwn_softc *); 284 static int iwn5000_runtime_calib(struct iwn_softc *); 285 static int iwn_check_bss_filter(struct iwn_softc *); 286 static int iwn4965_rxon_assoc(struct iwn_softc *, int); 287 static int iwn5000_rxon_assoc(struct iwn_softc *, int); 288 static int iwn_send_rxon(struct iwn_softc *, int, int); 289 static int iwn_config(struct iwn_softc *); 290 static int iwn_scan(struct iwn_softc *, struct ieee80211vap *, 291 struct ieee80211_scan_state *, struct ieee80211_channel *); 292 static int iwn_auth(struct iwn_softc *, struct ieee80211vap *vap); 293 static int iwn_run(struct iwn_softc *, struct ieee80211vap *vap); 294 static int iwn_ampdu_rx_start(struct ieee80211_node *, 295 struct ieee80211_rx_ampdu *, int, int, int); 296 static void iwn_ampdu_rx_stop(struct ieee80211_node *, 297 struct ieee80211_rx_ampdu *); 298 static int iwn_addba_request(struct ieee80211_node *, 299 struct ieee80211_tx_ampdu *, int, int, int); 300 static int iwn_addba_response(struct ieee80211_node *, 301 struct ieee80211_tx_ampdu *, int, int, int); 302 static int iwn_ampdu_tx_start(struct ieee80211com *, 303 struct ieee80211_node *, uint8_t); 304 static void iwn_ampdu_tx_stop(struct ieee80211_node *, 305 struct ieee80211_tx_ampdu *); 306 static void iwn4965_ampdu_tx_start(struct iwn_softc *, 307 struct ieee80211_node *, int, uint8_t, uint16_t); 308 static void iwn4965_ampdu_tx_stop(struct iwn_softc *, int, 309 uint8_t, uint16_t); 310 static void iwn5000_ampdu_tx_start(struct iwn_softc *, 311 struct ieee80211_node *, int, uint8_t, uint16_t); 312 static void iwn5000_ampdu_tx_stop(struct iwn_softc *, int, 313 uint8_t, uint16_t); 314 static int iwn5000_query_calibration(struct iwn_softc *); 315 static int iwn5000_send_calibration(struct iwn_softc *); 316 static int iwn5000_send_wimax_coex(struct iwn_softc *); 317 static int iwn5000_crystal_calib(struct iwn_softc *); 318 static int iwn5000_temp_offset_calib(struct iwn_softc *); 319 static int iwn5000_temp_offset_calibv2(struct iwn_softc *); 320 static int iwn4965_post_alive(struct iwn_softc *); 321 static int iwn5000_post_alive(struct iwn_softc *); 322 static int iwn4965_load_bootcode(struct iwn_softc *, const uint8_t *, 323 int); 324 static int iwn4965_load_firmware(struct iwn_softc *); 325 static int iwn5000_load_firmware_section(struct iwn_softc *, uint32_t, 326 const uint8_t *, int); 327 static int iwn5000_load_firmware(struct iwn_softc *); 328 static int iwn_read_firmware_leg(struct iwn_softc *, 329 struct iwn_fw_info *); 330 static int iwn_read_firmware_tlv(struct iwn_softc *, 331 struct iwn_fw_info *, uint16_t); 332 static int iwn_read_firmware(struct iwn_softc *); 333 static void iwn_unload_firmware(struct iwn_softc *); 334 static int iwn_clock_wait(struct iwn_softc *); 335 static int iwn_apm_init(struct iwn_softc *); 336 static void iwn_apm_stop_master(struct iwn_softc *); 337 static void iwn_apm_stop(struct iwn_softc *); 338 static int iwn4965_nic_config(struct iwn_softc *); 339 static int iwn5000_nic_config(struct iwn_softc *); 340 static int iwn_hw_prepare(struct iwn_softc *); 341 static int iwn_hw_init(struct iwn_softc *); 342 static void iwn_hw_stop(struct iwn_softc *); 343 static void iwn_panicked(void *, int); 344 static int iwn_init_locked(struct iwn_softc *); 345 static int iwn_init(struct iwn_softc *); 346 static void iwn_stop_locked(struct iwn_softc *); 347 static void iwn_stop(struct iwn_softc *); 348 static void iwn_scan_start(struct ieee80211com *); 349 static void iwn_scan_end(struct ieee80211com *); 350 static void iwn_set_channel(struct ieee80211com *); 351 static void iwn_scan_curchan(struct ieee80211_scan_state *, unsigned long); 352 static void iwn_scan_mindwell(struct ieee80211_scan_state *); 353 #ifdef IWN_DEBUG 354 static char *iwn_get_csr_string(int); 355 static void iwn_debug_register(struct iwn_softc *); 356 #endif 357 358 static device_method_t iwn_methods[] = { 359 /* Device interface */ 360 DEVMETHOD(device_probe, iwn_probe), 361 DEVMETHOD(device_attach, iwn_attach), 362 DEVMETHOD(device_detach, iwn_detach), 363 DEVMETHOD(device_shutdown, iwn_shutdown), 364 DEVMETHOD(device_suspend, iwn_suspend), 365 DEVMETHOD(device_resume, iwn_resume), 366 367 DEVMETHOD_END 368 }; 369 370 static driver_t iwn_driver = { 371 "iwn", 372 iwn_methods, 373 sizeof(struct iwn_softc) 374 }; 375 376 DRIVER_MODULE(iwn, pci, iwn_driver, NULL, NULL); 377 MODULE_PNP_INFO("U16:vendor;U16:device;D:#", pci, iwn, iwn_ident_table, 378 nitems(iwn_ident_table) - 1); 379 MODULE_VERSION(iwn, 1); 380 381 MODULE_DEPEND(iwn, firmware, 1, 1, 1); 382 MODULE_DEPEND(iwn, pci, 1, 1, 1); 383 MODULE_DEPEND(iwn, wlan, 1, 1, 1); 384 385 static d_ioctl_t iwn_cdev_ioctl; 386 static d_open_t iwn_cdev_open; 387 static d_close_t iwn_cdev_close; 388 389 static struct cdevsw iwn_cdevsw = { 390 .d_version = D_VERSION, 391 .d_flags = 0, 392 .d_open = iwn_cdev_open, 393 .d_close = iwn_cdev_close, 394 .d_ioctl = iwn_cdev_ioctl, 395 .d_name = "iwn", 396 }; 397 398 static int 399 iwn_probe(device_t dev) 400 { 401 const struct iwn_ident *ident; 402 403 for (ident = iwn_ident_table; ident->name != NULL; ident++) { 404 if (pci_get_vendor(dev) == ident->vendor && 405 pci_get_device(dev) == ident->device) { 406 device_set_desc(dev, ident->name); 407 return (BUS_PROBE_DEFAULT); 408 } 409 } 410 return ENXIO; 411 } 412 413 static int 414 iwn_is_3stream_device(struct iwn_softc *sc) 415 { 416 /* XXX for now only 5300, until the 5350 can be tested */ 417 if (sc->hw_type == IWN_HW_REV_TYPE_5300) 418 return (1); 419 return (0); 420 } 421 422 static int 423 iwn_attach(device_t dev) 424 { 425 struct iwn_softc *sc = device_get_softc(dev); 426 struct ieee80211com *ic; 427 int i, error, rid; 428 429 sc->sc_dev = dev; 430 431 #ifdef IWN_DEBUG 432 error = resource_int_value(device_get_name(sc->sc_dev), 433 device_get_unit(sc->sc_dev), "debug", &(sc->sc_debug)); 434 if (error != 0) 435 sc->sc_debug = 0; 436 #else 437 sc->sc_debug = 0; 438 #endif 439 440 DPRINTF(sc, IWN_DEBUG_TRACE, "->%s: begin\n",__func__); 441 442 /* 443 * Get the offset of the PCI Express Capability Structure in PCI 444 * Configuration Space. 445 */ 446 error = pci_find_cap(dev, PCIY_EXPRESS, &sc->sc_cap_off); 447 if (error != 0) { 448 device_printf(dev, "PCIe capability structure not found!\n"); 449 return error; 450 } 451 452 /* Clear device-specific "PCI retry timeout" register (41h). */ 453 pci_write_config(dev, 0x41, 0, 1); 454 455 /* Enable bus-mastering. */ 456 pci_enable_busmaster(dev); 457 458 rid = PCIR_BAR(0); 459 sc->mem = bus_alloc_resource_any(dev, SYS_RES_MEMORY, &rid, 460 RF_ACTIVE); 461 if (sc->mem == NULL) { 462 device_printf(dev, "can't map mem space\n"); 463 error = ENOMEM; 464 return error; 465 } 466 sc->sc_st = rman_get_bustag(sc->mem); 467 sc->sc_sh = rman_get_bushandle(sc->mem); 468 469 i = 1; 470 rid = 0; 471 if (pci_alloc_msi(dev, &i) == 0) 472 rid = 1; 473 /* Install interrupt handler. */ 474 sc->irq = bus_alloc_resource_any(dev, SYS_RES_IRQ, &rid, RF_ACTIVE | 475 (rid != 0 ? 0 : RF_SHAREABLE)); 476 if (sc->irq == NULL) { 477 device_printf(dev, "can't map interrupt\n"); 478 error = ENOMEM; 479 goto fail; 480 } 481 482 IWN_LOCK_INIT(sc); 483 484 /* Read hardware revision and attach. */ 485 sc->hw_type = (IWN_READ(sc, IWN_HW_REV) >> IWN_HW_REV_TYPE_SHIFT) 486 & IWN_HW_REV_TYPE_MASK; 487 sc->subdevice_id = pci_get_subdevice(dev); 488 489 /* 490 * 4965 versus 5000 and later have different methods. 491 * Let's set those up first. 492 */ 493 if (sc->hw_type == IWN_HW_REV_TYPE_4965) 494 iwn4965_attach(sc, pci_get_device(dev)); 495 else 496 iwn5000_attach(sc, pci_get_device(dev)); 497 498 /* 499 * Next, let's setup the various parameters of each NIC. 500 */ 501 error = iwn_config_specific(sc, pci_get_device(dev)); 502 if (error != 0) { 503 device_printf(dev, "could not attach device, error %d\n", 504 error); 505 goto fail; 506 } 507 508 if ((error = iwn_hw_prepare(sc)) != 0) { 509 device_printf(dev, "hardware not ready, error %d\n", error); 510 goto fail; 511 } 512 513 /* Allocate DMA memory for firmware transfers. */ 514 if ((error = iwn_alloc_fwmem(sc)) != 0) { 515 device_printf(dev, 516 "could not allocate memory for firmware, error %d\n", 517 error); 518 goto fail; 519 } 520 521 /* Allocate "Keep Warm" page. */ 522 if ((error = iwn_alloc_kw(sc)) != 0) { 523 device_printf(dev, 524 "could not allocate keep warm page, error %d\n", error); 525 goto fail; 526 } 527 528 /* Allocate ICT table for 5000 Series. */ 529 if (sc->hw_type != IWN_HW_REV_TYPE_4965 && 530 (error = iwn_alloc_ict(sc)) != 0) { 531 device_printf(dev, "could not allocate ICT table, error %d\n", 532 error); 533 goto fail; 534 } 535 536 /* Allocate TX scheduler "rings". */ 537 if ((error = iwn_alloc_sched(sc)) != 0) { 538 device_printf(dev, 539 "could not allocate TX scheduler rings, error %d\n", error); 540 goto fail; 541 } 542 543 /* Allocate TX rings (16 on 4965AGN, 20 on >=5000). */ 544 for (i = 0; i < sc->ntxqs; i++) { 545 if ((error = iwn_alloc_tx_ring(sc, &sc->txq[i], i)) != 0) { 546 device_printf(dev, 547 "could not allocate TX ring %d, error %d\n", i, 548 error); 549 goto fail; 550 } 551 } 552 553 /* Allocate RX ring. */ 554 if ((error = iwn_alloc_rx_ring(sc, &sc->rxq)) != 0) { 555 device_printf(dev, "could not allocate RX ring, error %d\n", 556 error); 557 goto fail; 558 } 559 560 /* Clear pending interrupts. */ 561 IWN_WRITE(sc, IWN_INT, 0xffffffff); 562 563 ic = &sc->sc_ic; 564 ic->ic_softc = sc; 565 ic->ic_name = device_get_nameunit(dev); 566 ic->ic_phytype = IEEE80211_T_OFDM; /* not only, but not used */ 567 ic->ic_opmode = IEEE80211_M_STA; /* default to BSS mode */ 568 569 /* Set device capabilities. */ 570 ic->ic_caps = 571 IEEE80211_C_STA /* station mode supported */ 572 | IEEE80211_C_MONITOR /* monitor mode supported */ 573 #if 0 574 | IEEE80211_C_BGSCAN /* background scanning */ 575 #endif 576 | IEEE80211_C_TXPMGT /* tx power management */ 577 | IEEE80211_C_SHSLOT /* short slot time supported */ 578 | IEEE80211_C_WPA 579 | IEEE80211_C_SHPREAMBLE /* short preamble supported */ 580 #if 0 581 | IEEE80211_C_IBSS /* ibss/adhoc mode */ 582 #endif 583 | IEEE80211_C_WME /* WME */ 584 | IEEE80211_C_PMGT /* Station-side power mgmt */ 585 ; 586 587 /* Read MAC address, channels, etc from EEPROM. */ 588 if ((error = iwn_read_eeprom(sc, ic->ic_macaddr)) != 0) { 589 device_printf(dev, "could not read EEPROM, error %d\n", 590 error); 591 goto fail; 592 } 593 594 /* Count the number of available chains. */ 595 sc->ntxchains = 596 ((sc->txchainmask >> 2) & 1) + 597 ((sc->txchainmask >> 1) & 1) + 598 ((sc->txchainmask >> 0) & 1); 599 sc->nrxchains = 600 ((sc->rxchainmask >> 2) & 1) + 601 ((sc->rxchainmask >> 1) & 1) + 602 ((sc->rxchainmask >> 0) & 1); 603 if (bootverbose) { 604 device_printf(dev, "MIMO %dT%dR, %.4s, address %6D\n", 605 sc->ntxchains, sc->nrxchains, sc->eeprom_domain, 606 ic->ic_macaddr, ":"); 607 } 608 609 if (sc->sc_flags & IWN_FLAG_HAS_11N) { 610 ic->ic_rxstream = sc->nrxchains; 611 ic->ic_txstream = sc->ntxchains; 612 613 /* 614 * Some of the 3 antenna devices (ie, the 4965) only supports 615 * 2x2 operation. So correct the number of streams if 616 * it's not a 3-stream device. 617 */ 618 if (! iwn_is_3stream_device(sc)) { 619 if (ic->ic_rxstream > 2) 620 ic->ic_rxstream = 2; 621 if (ic->ic_txstream > 2) 622 ic->ic_txstream = 2; 623 } 624 625 ic->ic_htcaps = 626 IEEE80211_HTCAP_SMPS_OFF /* SMPS mode disabled */ 627 | IEEE80211_HTCAP_SHORTGI20 /* short GI in 20MHz */ 628 | IEEE80211_HTCAP_CHWIDTH40 /* 40MHz channel width*/ 629 | IEEE80211_HTCAP_SHORTGI40 /* short GI in 40MHz */ 630 #ifdef notyet 631 | IEEE80211_HTCAP_GREENFIELD 632 #if IWN_RBUF_SIZE == 8192 633 | IEEE80211_HTCAP_MAXAMSDU_7935 /* max A-MSDU length */ 634 #else 635 | IEEE80211_HTCAP_MAXAMSDU_3839 /* max A-MSDU length */ 636 #endif 637 #endif 638 /* s/w capabilities */ 639 | IEEE80211_HTC_HT /* HT operation */ 640 | IEEE80211_HTC_AMPDU /* tx A-MPDU */ 641 #ifdef notyet 642 | IEEE80211_HTC_AMSDU /* tx A-MSDU */ 643 #endif 644 ; 645 } 646 647 ieee80211_ifattach(ic); 648 ic->ic_vap_create = iwn_vap_create; 649 ic->ic_ioctl = iwn_ioctl; 650 ic->ic_parent = iwn_parent; 651 ic->ic_vap_delete = iwn_vap_delete; 652 ic->ic_transmit = iwn_transmit; 653 ic->ic_raw_xmit = iwn_raw_xmit; 654 ic->ic_node_alloc = iwn_node_alloc; 655 sc->sc_ampdu_rx_start = ic->ic_ampdu_rx_start; 656 ic->ic_ampdu_rx_start = iwn_ampdu_rx_start; 657 sc->sc_ampdu_rx_stop = ic->ic_ampdu_rx_stop; 658 ic->ic_ampdu_rx_stop = iwn_ampdu_rx_stop; 659 sc->sc_addba_request = ic->ic_addba_request; 660 ic->ic_addba_request = iwn_addba_request; 661 sc->sc_addba_response = ic->ic_addba_response; 662 ic->ic_addba_response = iwn_addba_response; 663 sc->sc_addba_stop = ic->ic_addba_stop; 664 ic->ic_addba_stop = iwn_ampdu_tx_stop; 665 ic->ic_newassoc = iwn_newassoc; 666 ic->ic_wme.wme_update = iwn_updateedca; 667 ic->ic_update_promisc = iwn_update_promisc; 668 ic->ic_update_mcast = iwn_update_mcast; 669 ic->ic_scan_start = iwn_scan_start; 670 ic->ic_scan_end = iwn_scan_end; 671 ic->ic_set_channel = iwn_set_channel; 672 ic->ic_scan_curchan = iwn_scan_curchan; 673 ic->ic_scan_mindwell = iwn_scan_mindwell; 674 ic->ic_getradiocaps = iwn_getradiocaps; 675 ic->ic_setregdomain = iwn_setregdomain; 676 677 iwn_radiotap_attach(sc); 678 679 callout_init_mtx(&sc->calib_to, &sc->sc_mtx, 0); 680 callout_init_mtx(&sc->scan_timeout, &sc->sc_mtx, 0); 681 callout_init_mtx(&sc->watchdog_to, &sc->sc_mtx, 0); 682 TASK_INIT(&sc->sc_rftoggle_task, 0, iwn_rftoggle_task, sc); 683 TASK_INIT(&sc->sc_panic_task, 0, iwn_panicked, sc); 684 TASK_INIT(&sc->sc_xmit_task, 0, iwn_xmit_task, sc); 685 686 mbufq_init(&sc->sc_xmit_queue, 1024); 687 688 sc->sc_tq = taskqueue_create("iwn_taskq", M_WAITOK, 689 taskqueue_thread_enqueue, &sc->sc_tq); 690 error = taskqueue_start_threads(&sc->sc_tq, 1, 0, "iwn_taskq"); 691 if (error != 0) { 692 device_printf(dev, "can't start threads, error %d\n", error); 693 goto fail; 694 } 695 696 iwn_sysctlattach(sc); 697 698 /* 699 * Hook our interrupt after all initialization is complete. 700 */ 701 error = bus_setup_intr(dev, sc->irq, INTR_TYPE_NET | INTR_MPSAFE, 702 NULL, iwn_intr, sc, &sc->sc_ih); 703 if (error != 0) { 704 device_printf(dev, "can't establish interrupt, error %d\n", 705 error); 706 goto fail; 707 } 708 709 #if 0 710 device_printf(sc->sc_dev, "%s: rx_stats=%d, rx_stats_bt=%d\n", 711 __func__, 712 sizeof(struct iwn_stats), 713 sizeof(struct iwn_stats_bt)); 714 #endif 715 716 if (bootverbose) 717 ieee80211_announce(ic); 718 DPRINTF(sc, IWN_DEBUG_TRACE, "->%s: end\n",__func__); 719 720 /* Add debug ioctl right at the end */ 721 sc->sc_cdev = make_dev(&iwn_cdevsw, device_get_unit(dev), 722 UID_ROOT, GID_WHEEL, 0600, "%s", device_get_nameunit(dev)); 723 if (sc->sc_cdev == NULL) { 724 device_printf(dev, "failed to create debug character device\n"); 725 } else { 726 sc->sc_cdev->si_drv1 = sc; 727 } 728 return 0; 729 fail: 730 iwn_detach(dev); 731 DPRINTF(sc, IWN_DEBUG_TRACE, "->%s: end in error\n",__func__); 732 return error; 733 } 734 735 /* 736 * Define specific configuration based on device id and subdevice id 737 * pid : PCI device id 738 */ 739 static int 740 iwn_config_specific(struct iwn_softc *sc, uint16_t pid) 741 { 742 743 switch (pid) { 744 /* 4965 series */ 745 case IWN_DID_4965_1: 746 case IWN_DID_4965_2: 747 case IWN_DID_4965_3: 748 case IWN_DID_4965_4: 749 sc->base_params = &iwn4965_base_params; 750 sc->limits = &iwn4965_sensitivity_limits; 751 sc->fwname = "iwn4965fw"; 752 /* Override chains masks, ROM is known to be broken. */ 753 sc->txchainmask = IWN_ANT_AB; 754 sc->rxchainmask = IWN_ANT_ABC; 755 /* Enable normal btcoex */ 756 sc->sc_flags |= IWN_FLAG_BTCOEX; 757 break; 758 /* 1000 Series */ 759 case IWN_DID_1000_1: 760 case IWN_DID_1000_2: 761 switch(sc->subdevice_id) { 762 case IWN_SDID_1000_1: 763 case IWN_SDID_1000_2: 764 case IWN_SDID_1000_3: 765 case IWN_SDID_1000_4: 766 case IWN_SDID_1000_5: 767 case IWN_SDID_1000_6: 768 case IWN_SDID_1000_7: 769 case IWN_SDID_1000_8: 770 case IWN_SDID_1000_9: 771 case IWN_SDID_1000_10: 772 case IWN_SDID_1000_11: 773 case IWN_SDID_1000_12: 774 sc->limits = &iwn1000_sensitivity_limits; 775 sc->base_params = &iwn1000_base_params; 776 sc->fwname = "iwn1000fw"; 777 break; 778 default: 779 device_printf(sc->sc_dev, "adapter type id : 0x%04x sub id :" 780 "0x%04x rev %d not supported (subdevice)\n", pid, 781 sc->subdevice_id,sc->hw_type); 782 return ENOTSUP; 783 } 784 break; 785 /* 6x00 Series */ 786 case IWN_DID_6x00_2: 787 case IWN_DID_6x00_4: 788 case IWN_DID_6x00_1: 789 case IWN_DID_6x00_3: 790 sc->fwname = "iwn6000fw"; 791 sc->limits = &iwn6000_sensitivity_limits; 792 switch(sc->subdevice_id) { 793 case IWN_SDID_6x00_1: 794 case IWN_SDID_6x00_2: 795 case IWN_SDID_6x00_8: 796 //iwl6000_3agn_cfg 797 sc->base_params = &iwn_6000_base_params; 798 break; 799 case IWN_SDID_6x00_3: 800 case IWN_SDID_6x00_6: 801 case IWN_SDID_6x00_9: 802 ////iwl6000i_2agn 803 case IWN_SDID_6x00_4: 804 case IWN_SDID_6x00_7: 805 case IWN_SDID_6x00_10: 806 //iwl6000i_2abg_cfg 807 case IWN_SDID_6x00_5: 808 //iwl6000i_2bg_cfg 809 sc->base_params = &iwn_6000i_base_params; 810 sc->sc_flags |= IWN_FLAG_INTERNAL_PA; 811 sc->txchainmask = IWN_ANT_BC; 812 sc->rxchainmask = IWN_ANT_BC; 813 break; 814 default: 815 device_printf(sc->sc_dev, "adapter type id : 0x%04x sub id :" 816 "0x%04x rev %d not supported (subdevice)\n", pid, 817 sc->subdevice_id,sc->hw_type); 818 return ENOTSUP; 819 } 820 break; 821 /* 6x05 Series */ 822 case IWN_DID_6x05_1: 823 case IWN_DID_6x05_2: 824 switch(sc->subdevice_id) { 825 case IWN_SDID_6x05_1: 826 case IWN_SDID_6x05_4: 827 case IWN_SDID_6x05_6: 828 //iwl6005_2agn_cfg 829 case IWN_SDID_6x05_2: 830 case IWN_SDID_6x05_5: 831 case IWN_SDID_6x05_7: 832 //iwl6005_2abg_cfg 833 case IWN_SDID_6x05_3: 834 //iwl6005_2bg_cfg 835 case IWN_SDID_6x05_8: 836 case IWN_SDID_6x05_9: 837 //iwl6005_2agn_sff_cfg 838 case IWN_SDID_6x05_10: 839 //iwl6005_2agn_d_cfg 840 case IWN_SDID_6x05_11: 841 //iwl6005_2agn_mow1_cfg 842 case IWN_SDID_6x05_12: 843 //iwl6005_2agn_mow2_cfg 844 sc->fwname = "iwn6000g2afw"; 845 sc->limits = &iwn6000_sensitivity_limits; 846 sc->base_params = &iwn_6000g2_base_params; 847 break; 848 default: 849 device_printf(sc->sc_dev, "adapter type id : 0x%04x sub id :" 850 "0x%04x rev %d not supported (subdevice)\n", pid, 851 sc->subdevice_id,sc->hw_type); 852 return ENOTSUP; 853 } 854 break; 855 /* 6x35 Series */ 856 case IWN_DID_6035_1: 857 case IWN_DID_6035_2: 858 switch(sc->subdevice_id) { 859 case IWN_SDID_6035_1: 860 case IWN_SDID_6035_2: 861 case IWN_SDID_6035_3: 862 case IWN_SDID_6035_4: 863 case IWN_SDID_6035_5: 864 sc->fwname = "iwn6000g2bfw"; 865 sc->limits = &iwn6235_sensitivity_limits; 866 sc->base_params = &iwn_6235_base_params; 867 break; 868 default: 869 device_printf(sc->sc_dev, "adapter type id : 0x%04x sub id :" 870 "0x%04x rev %d not supported (subdevice)\n", pid, 871 sc->subdevice_id,sc->hw_type); 872 return ENOTSUP; 873 } 874 break; 875 /* 6x50 WiFi/WiMax Series */ 876 case IWN_DID_6050_1: 877 case IWN_DID_6050_2: 878 switch(sc->subdevice_id) { 879 case IWN_SDID_6050_1: 880 case IWN_SDID_6050_3: 881 case IWN_SDID_6050_5: 882 //iwl6050_2agn_cfg 883 case IWN_SDID_6050_2: 884 case IWN_SDID_6050_4: 885 case IWN_SDID_6050_6: 886 //iwl6050_2abg_cfg 887 sc->fwname = "iwn6050fw"; 888 sc->txchainmask = IWN_ANT_AB; 889 sc->rxchainmask = IWN_ANT_AB; 890 sc->limits = &iwn6000_sensitivity_limits; 891 sc->base_params = &iwn_6050_base_params; 892 break; 893 default: 894 device_printf(sc->sc_dev, "adapter type id : 0x%04x sub id :" 895 "0x%04x rev %d not supported (subdevice)\n", pid, 896 sc->subdevice_id,sc->hw_type); 897 return ENOTSUP; 898 } 899 break; 900 /* 6150 WiFi/WiMax Series */ 901 case IWN_DID_6150_1: 902 case IWN_DID_6150_2: 903 switch(sc->subdevice_id) { 904 case IWN_SDID_6150_1: 905 case IWN_SDID_6150_3: 906 case IWN_SDID_6150_5: 907 // iwl6150_bgn_cfg 908 case IWN_SDID_6150_2: 909 case IWN_SDID_6150_4: 910 case IWN_SDID_6150_6: 911 //iwl6150_bg_cfg 912 sc->fwname = "iwn6050fw"; 913 sc->limits = &iwn6000_sensitivity_limits; 914 sc->base_params = &iwn_6150_base_params; 915 break; 916 default: 917 device_printf(sc->sc_dev, "adapter type id : 0x%04x sub id :" 918 "0x%04x rev %d not supported (subdevice)\n", pid, 919 sc->subdevice_id,sc->hw_type); 920 return ENOTSUP; 921 } 922 break; 923 /* 6030 Series and 1030 Series */ 924 case IWN_DID_x030_1: 925 case IWN_DID_x030_2: 926 case IWN_DID_x030_3: 927 case IWN_DID_x030_4: 928 switch(sc->subdevice_id) { 929 case IWN_SDID_x030_1: 930 case IWN_SDID_x030_3: 931 case IWN_SDID_x030_5: 932 // iwl1030_bgn_cfg 933 case IWN_SDID_x030_2: 934 case IWN_SDID_x030_4: 935 case IWN_SDID_x030_6: 936 //iwl1030_bg_cfg 937 case IWN_SDID_x030_7: 938 case IWN_SDID_x030_10: 939 case IWN_SDID_x030_14: 940 //iwl6030_2agn_cfg 941 case IWN_SDID_x030_8: 942 case IWN_SDID_x030_11: 943 case IWN_SDID_x030_15: 944 // iwl6030_2bgn_cfg 945 case IWN_SDID_x030_9: 946 case IWN_SDID_x030_12: 947 case IWN_SDID_x030_16: 948 // iwl6030_2abg_cfg 949 case IWN_SDID_x030_13: 950 //iwl6030_2bg_cfg 951 sc->fwname = "iwn6000g2bfw"; 952 sc->limits = &iwn6000_sensitivity_limits; 953 sc->base_params = &iwn_6000g2b_base_params; 954 break; 955 default: 956 device_printf(sc->sc_dev, "adapter type id : 0x%04x sub id :" 957 "0x%04x rev %d not supported (subdevice)\n", pid, 958 sc->subdevice_id,sc->hw_type); 959 return ENOTSUP; 960 } 961 break; 962 /* 130 Series WiFi */ 963 /* XXX: This series will need adjustment for rate. 964 * see rx_with_siso_diversity in linux kernel 965 */ 966 case IWN_DID_130_1: 967 case IWN_DID_130_2: 968 switch(sc->subdevice_id) { 969 case IWN_SDID_130_1: 970 case IWN_SDID_130_3: 971 case IWN_SDID_130_5: 972 //iwl130_bgn_cfg 973 case IWN_SDID_130_2: 974 case IWN_SDID_130_4: 975 case IWN_SDID_130_6: 976 //iwl130_bg_cfg 977 sc->fwname = "iwn6000g2bfw"; 978 sc->limits = &iwn6000_sensitivity_limits; 979 sc->base_params = &iwn_6000g2b_base_params; 980 break; 981 default: 982 device_printf(sc->sc_dev, "adapter type id : 0x%04x sub id :" 983 "0x%04x rev %d not supported (subdevice)\n", pid, 984 sc->subdevice_id,sc->hw_type); 985 return ENOTSUP; 986 } 987 break; 988 /* 100 Series WiFi */ 989 case IWN_DID_100_1: 990 case IWN_DID_100_2: 991 switch(sc->subdevice_id) { 992 case IWN_SDID_100_1: 993 case IWN_SDID_100_2: 994 case IWN_SDID_100_3: 995 case IWN_SDID_100_4: 996 case IWN_SDID_100_5: 997 case IWN_SDID_100_6: 998 sc->limits = &iwn1000_sensitivity_limits; 999 sc->base_params = &iwn1000_base_params; 1000 sc->fwname = "iwn100fw"; 1001 break; 1002 default: 1003 device_printf(sc->sc_dev, "adapter type id : 0x%04x sub id :" 1004 "0x%04x rev %d not supported (subdevice)\n", pid, 1005 sc->subdevice_id,sc->hw_type); 1006 return ENOTSUP; 1007 } 1008 break; 1009 1010 /* 105 Series */ 1011 /* XXX: This series will need adjustment for rate. 1012 * see rx_with_siso_diversity in linux kernel 1013 */ 1014 case IWN_DID_105_1: 1015 case IWN_DID_105_2: 1016 switch(sc->subdevice_id) { 1017 case IWN_SDID_105_1: 1018 case IWN_SDID_105_2: 1019 case IWN_SDID_105_3: 1020 //iwl105_bgn_cfg 1021 case IWN_SDID_105_4: 1022 //iwl105_bgn_d_cfg 1023 sc->limits = &iwn2030_sensitivity_limits; 1024 sc->base_params = &iwn2000_base_params; 1025 sc->fwname = "iwn105fw"; 1026 break; 1027 default: 1028 device_printf(sc->sc_dev, "adapter type id : 0x%04x sub id :" 1029 "0x%04x rev %d not supported (subdevice)\n", pid, 1030 sc->subdevice_id,sc->hw_type); 1031 return ENOTSUP; 1032 } 1033 break; 1034 1035 /* 135 Series */ 1036 /* XXX: This series will need adjustment for rate. 1037 * see rx_with_siso_diversity in linux kernel 1038 */ 1039 case IWN_DID_135_1: 1040 case IWN_DID_135_2: 1041 switch(sc->subdevice_id) { 1042 case IWN_SDID_135_1: 1043 case IWN_SDID_135_2: 1044 case IWN_SDID_135_3: 1045 sc->limits = &iwn2030_sensitivity_limits; 1046 sc->base_params = &iwn2030_base_params; 1047 sc->fwname = "iwn135fw"; 1048 break; 1049 default: 1050 device_printf(sc->sc_dev, "adapter type id : 0x%04x sub id :" 1051 "0x%04x rev %d not supported (subdevice)\n", pid, 1052 sc->subdevice_id,sc->hw_type); 1053 return ENOTSUP; 1054 } 1055 break; 1056 1057 /* 2x00 Series */ 1058 case IWN_DID_2x00_1: 1059 case IWN_DID_2x00_2: 1060 switch(sc->subdevice_id) { 1061 case IWN_SDID_2x00_1: 1062 case IWN_SDID_2x00_2: 1063 case IWN_SDID_2x00_3: 1064 //iwl2000_2bgn_cfg 1065 case IWN_SDID_2x00_4: 1066 //iwl2000_2bgn_d_cfg 1067 sc->limits = &iwn2030_sensitivity_limits; 1068 sc->base_params = &iwn2000_base_params; 1069 sc->fwname = "iwn2000fw"; 1070 break; 1071 default: 1072 device_printf(sc->sc_dev, "adapter type id : 0x%04x sub id :" 1073 "0x%04x rev %d not supported (subdevice) \n", 1074 pid, sc->subdevice_id, sc->hw_type); 1075 return ENOTSUP; 1076 } 1077 break; 1078 /* 2x30 Series */ 1079 case IWN_DID_2x30_1: 1080 case IWN_DID_2x30_2: 1081 switch(sc->subdevice_id) { 1082 case IWN_SDID_2x30_1: 1083 case IWN_SDID_2x30_3: 1084 case IWN_SDID_2x30_5: 1085 //iwl100_bgn_cfg 1086 case IWN_SDID_2x30_2: 1087 case IWN_SDID_2x30_4: 1088 case IWN_SDID_2x30_6: 1089 //iwl100_bg_cfg 1090 sc->limits = &iwn2030_sensitivity_limits; 1091 sc->base_params = &iwn2030_base_params; 1092 sc->fwname = "iwn2030fw"; 1093 break; 1094 default: 1095 device_printf(sc->sc_dev, "adapter type id : 0x%04x sub id :" 1096 "0x%04x rev %d not supported (subdevice)\n", pid, 1097 sc->subdevice_id,sc->hw_type); 1098 return ENOTSUP; 1099 } 1100 break; 1101 /* 5x00 Series */ 1102 case IWN_DID_5x00_1: 1103 case IWN_DID_5x00_2: 1104 case IWN_DID_5x00_3: 1105 case IWN_DID_5x00_4: 1106 sc->limits = &iwn5000_sensitivity_limits; 1107 sc->base_params = &iwn5000_base_params; 1108 sc->fwname = "iwn5000fw"; 1109 switch(sc->subdevice_id) { 1110 case IWN_SDID_5x00_1: 1111 case IWN_SDID_5x00_2: 1112 case IWN_SDID_5x00_3: 1113 case IWN_SDID_5x00_4: 1114 case IWN_SDID_5x00_9: 1115 case IWN_SDID_5x00_10: 1116 case IWN_SDID_5x00_11: 1117 case IWN_SDID_5x00_12: 1118 case IWN_SDID_5x00_17: 1119 case IWN_SDID_5x00_18: 1120 case IWN_SDID_5x00_19: 1121 case IWN_SDID_5x00_20: 1122 //iwl5100_agn_cfg 1123 sc->txchainmask = IWN_ANT_B; 1124 sc->rxchainmask = IWN_ANT_AB; 1125 break; 1126 case IWN_SDID_5x00_5: 1127 case IWN_SDID_5x00_6: 1128 case IWN_SDID_5x00_13: 1129 case IWN_SDID_5x00_14: 1130 case IWN_SDID_5x00_21: 1131 case IWN_SDID_5x00_22: 1132 //iwl5100_bgn_cfg 1133 sc->txchainmask = IWN_ANT_B; 1134 sc->rxchainmask = IWN_ANT_AB; 1135 break; 1136 case IWN_SDID_5x00_7: 1137 case IWN_SDID_5x00_8: 1138 case IWN_SDID_5x00_15: 1139 case IWN_SDID_5x00_16: 1140 case IWN_SDID_5x00_23: 1141 case IWN_SDID_5x00_24: 1142 //iwl5100_abg_cfg 1143 sc->txchainmask = IWN_ANT_B; 1144 sc->rxchainmask = IWN_ANT_AB; 1145 break; 1146 case IWN_SDID_5x00_25: 1147 case IWN_SDID_5x00_26: 1148 case IWN_SDID_5x00_27: 1149 case IWN_SDID_5x00_28: 1150 case IWN_SDID_5x00_29: 1151 case IWN_SDID_5x00_30: 1152 case IWN_SDID_5x00_31: 1153 case IWN_SDID_5x00_32: 1154 case IWN_SDID_5x00_33: 1155 case IWN_SDID_5x00_34: 1156 case IWN_SDID_5x00_35: 1157 case IWN_SDID_5x00_36: 1158 //iwl5300_agn_cfg 1159 sc->txchainmask = IWN_ANT_ABC; 1160 sc->rxchainmask = IWN_ANT_ABC; 1161 break; 1162 default: 1163 device_printf(sc->sc_dev, "adapter type id : 0x%04x sub id :" 1164 "0x%04x rev %d not supported (subdevice)\n", pid, 1165 sc->subdevice_id,sc->hw_type); 1166 return ENOTSUP; 1167 } 1168 break; 1169 /* 5x50 Series */ 1170 case IWN_DID_5x50_1: 1171 case IWN_DID_5x50_2: 1172 case IWN_DID_5x50_3: 1173 case IWN_DID_5x50_4: 1174 sc->limits = &iwn5000_sensitivity_limits; 1175 sc->base_params = &iwn5000_base_params; 1176 sc->fwname = "iwn5000fw"; 1177 switch(sc->subdevice_id) { 1178 case IWN_SDID_5x50_1: 1179 case IWN_SDID_5x50_2: 1180 case IWN_SDID_5x50_3: 1181 //iwl5350_agn_cfg 1182 sc->limits = &iwn5000_sensitivity_limits; 1183 sc->base_params = &iwn5000_base_params; 1184 sc->fwname = "iwn5000fw"; 1185 break; 1186 case IWN_SDID_5x50_4: 1187 case IWN_SDID_5x50_5: 1188 case IWN_SDID_5x50_8: 1189 case IWN_SDID_5x50_9: 1190 case IWN_SDID_5x50_10: 1191 case IWN_SDID_5x50_11: 1192 //iwl5150_agn_cfg 1193 case IWN_SDID_5x50_6: 1194 case IWN_SDID_5x50_7: 1195 case IWN_SDID_5x50_12: 1196 case IWN_SDID_5x50_13: 1197 //iwl5150_abg_cfg 1198 sc->limits = &iwn5000_sensitivity_limits; 1199 sc->fwname = "iwn5150fw"; 1200 sc->base_params = &iwn_5x50_base_params; 1201 break; 1202 default: 1203 device_printf(sc->sc_dev, "adapter type id : 0x%04x sub id :" 1204 "0x%04x rev %d not supported (subdevice)\n", pid, 1205 sc->subdevice_id,sc->hw_type); 1206 return ENOTSUP; 1207 } 1208 break; 1209 default: 1210 device_printf(sc->sc_dev, "adapter type id : 0x%04x sub id : 0x%04x" 1211 "rev 0x%08x not supported (device)\n", pid, sc->subdevice_id, 1212 sc->hw_type); 1213 return ENOTSUP; 1214 } 1215 return 0; 1216 } 1217 1218 static void 1219 iwn4965_attach(struct iwn_softc *sc, uint16_t pid) 1220 { 1221 struct iwn_ops *ops = &sc->ops; 1222 1223 DPRINTF(sc, IWN_DEBUG_TRACE, "->%s begin\n", __func__); 1224 1225 ops->load_firmware = iwn4965_load_firmware; 1226 ops->read_eeprom = iwn4965_read_eeprom; 1227 ops->post_alive = iwn4965_post_alive; 1228 ops->nic_config = iwn4965_nic_config; 1229 ops->update_sched = iwn4965_update_sched; 1230 ops->get_temperature = iwn4965_get_temperature; 1231 ops->get_rssi = iwn4965_get_rssi; 1232 ops->set_txpower = iwn4965_set_txpower; 1233 ops->init_gains = iwn4965_init_gains; 1234 ops->set_gains = iwn4965_set_gains; 1235 ops->rxon_assoc = iwn4965_rxon_assoc; 1236 ops->add_node = iwn4965_add_node; 1237 ops->tx_done = iwn4965_tx_done; 1238 ops->ampdu_tx_start = iwn4965_ampdu_tx_start; 1239 ops->ampdu_tx_stop = iwn4965_ampdu_tx_stop; 1240 sc->ntxqs = IWN4965_NTXQUEUES; 1241 sc->firstaggqueue = IWN4965_FIRSTAGGQUEUE; 1242 sc->ndmachnls = IWN4965_NDMACHNLS; 1243 sc->broadcast_id = IWN4965_ID_BROADCAST; 1244 sc->rxonsz = IWN4965_RXONSZ; 1245 sc->schedsz = IWN4965_SCHEDSZ; 1246 sc->fw_text_maxsz = IWN4965_FW_TEXT_MAXSZ; 1247 sc->fw_data_maxsz = IWN4965_FW_DATA_MAXSZ; 1248 sc->fwsz = IWN4965_FWSZ; 1249 sc->sched_txfact_addr = IWN4965_SCHED_TXFACT; 1250 sc->limits = &iwn4965_sensitivity_limits; 1251 sc->fwname = "iwn4965fw"; 1252 /* Override chains masks, ROM is known to be broken. */ 1253 sc->txchainmask = IWN_ANT_AB; 1254 sc->rxchainmask = IWN_ANT_ABC; 1255 /* Enable normal btcoex */ 1256 sc->sc_flags |= IWN_FLAG_BTCOEX; 1257 1258 DPRINTF(sc, IWN_DEBUG_TRACE, "%s: end\n",__func__); 1259 } 1260 1261 static void 1262 iwn5000_attach(struct iwn_softc *sc, uint16_t pid) 1263 { 1264 struct iwn_ops *ops = &sc->ops; 1265 1266 DPRINTF(sc, IWN_DEBUG_TRACE, "->%s begin\n", __func__); 1267 1268 ops->load_firmware = iwn5000_load_firmware; 1269 ops->read_eeprom = iwn5000_read_eeprom; 1270 ops->post_alive = iwn5000_post_alive; 1271 ops->nic_config = iwn5000_nic_config; 1272 ops->update_sched = iwn5000_update_sched; 1273 ops->get_temperature = iwn5000_get_temperature; 1274 ops->get_rssi = iwn5000_get_rssi; 1275 ops->set_txpower = iwn5000_set_txpower; 1276 ops->init_gains = iwn5000_init_gains; 1277 ops->set_gains = iwn5000_set_gains; 1278 ops->rxon_assoc = iwn5000_rxon_assoc; 1279 ops->add_node = iwn5000_add_node; 1280 ops->tx_done = iwn5000_tx_done; 1281 ops->ampdu_tx_start = iwn5000_ampdu_tx_start; 1282 ops->ampdu_tx_stop = iwn5000_ampdu_tx_stop; 1283 sc->ntxqs = IWN5000_NTXQUEUES; 1284 sc->firstaggqueue = IWN5000_FIRSTAGGQUEUE; 1285 sc->ndmachnls = IWN5000_NDMACHNLS; 1286 sc->broadcast_id = IWN5000_ID_BROADCAST; 1287 sc->rxonsz = IWN5000_RXONSZ; 1288 sc->schedsz = IWN5000_SCHEDSZ; 1289 sc->fw_text_maxsz = IWN5000_FW_TEXT_MAXSZ; 1290 sc->fw_data_maxsz = IWN5000_FW_DATA_MAXSZ; 1291 sc->fwsz = IWN5000_FWSZ; 1292 sc->sched_txfact_addr = IWN5000_SCHED_TXFACT; 1293 sc->reset_noise_gain = IWN5000_PHY_CALIB_RESET_NOISE_GAIN; 1294 sc->noise_gain = IWN5000_PHY_CALIB_NOISE_GAIN; 1295 1296 DPRINTF(sc, IWN_DEBUG_TRACE, "%s: end\n",__func__); 1297 } 1298 1299 /* 1300 * Attach the interface to 802.11 radiotap. 1301 */ 1302 static void 1303 iwn_radiotap_attach(struct iwn_softc *sc) 1304 { 1305 1306 DPRINTF(sc, IWN_DEBUG_TRACE, "->%s begin\n", __func__); 1307 ieee80211_radiotap_attach(&sc->sc_ic, 1308 &sc->sc_txtap.wt_ihdr, sizeof(sc->sc_txtap), 1309 IWN_TX_RADIOTAP_PRESENT, 1310 &sc->sc_rxtap.wr_ihdr, sizeof(sc->sc_rxtap), 1311 IWN_RX_RADIOTAP_PRESENT); 1312 DPRINTF(sc, IWN_DEBUG_TRACE, "->%s end\n", __func__); 1313 } 1314 1315 static void 1316 iwn_sysctlattach(struct iwn_softc *sc) 1317 { 1318 #ifdef IWN_DEBUG 1319 struct sysctl_ctx_list *ctx = device_get_sysctl_ctx(sc->sc_dev); 1320 struct sysctl_oid *tree = device_get_sysctl_tree(sc->sc_dev); 1321 1322 SYSCTL_ADD_INT(ctx, SYSCTL_CHILDREN(tree), OID_AUTO, 1323 "debug", CTLFLAG_RW, &sc->sc_debug, sc->sc_debug, 1324 "control debugging printfs"); 1325 #endif 1326 } 1327 1328 static struct ieee80211vap * 1329 iwn_vap_create(struct ieee80211com *ic, const char name[IFNAMSIZ], int unit, 1330 enum ieee80211_opmode opmode, int flags, 1331 const uint8_t bssid[IEEE80211_ADDR_LEN], 1332 const uint8_t mac[IEEE80211_ADDR_LEN]) 1333 { 1334 struct iwn_softc *sc = ic->ic_softc; 1335 struct iwn_vap *ivp; 1336 struct ieee80211vap *vap; 1337 1338 if (!TAILQ_EMPTY(&ic->ic_vaps)) /* only one at a time */ 1339 return NULL; 1340 1341 ivp = malloc(sizeof(struct iwn_vap), M_80211_VAP, M_WAITOK | M_ZERO); 1342 vap = &ivp->iv_vap; 1343 ieee80211_vap_setup(ic, vap, name, unit, opmode, flags, bssid); 1344 ivp->ctx = IWN_RXON_BSS_CTX; 1345 vap->iv_bmissthreshold = 10; /* override default */ 1346 /* Override with driver methods. */ 1347 ivp->iv_newstate = vap->iv_newstate; 1348 vap->iv_newstate = iwn_newstate; 1349 sc->ivap[IWN_RXON_BSS_CTX] = vap; 1350 vap->iv_ampdu_rxmax = IEEE80211_HTCAP_MAXRXAMPDU_64K; 1351 vap->iv_ampdu_density = IEEE80211_HTCAP_MPDUDENSITY_4; /* 4uS */ 1352 1353 ieee80211_ratectl_init(vap); 1354 /* Complete setup. */ 1355 ieee80211_vap_attach(vap, ieee80211_media_change, 1356 ieee80211_media_status, mac); 1357 ic->ic_opmode = opmode; 1358 return vap; 1359 } 1360 1361 static void 1362 iwn_vap_delete(struct ieee80211vap *vap) 1363 { 1364 struct iwn_vap *ivp = IWN_VAP(vap); 1365 1366 ieee80211_ratectl_deinit(vap); 1367 ieee80211_vap_detach(vap); 1368 free(ivp, M_80211_VAP); 1369 } 1370 1371 static void 1372 iwn_xmit_queue_drain(struct iwn_softc *sc) 1373 { 1374 struct mbuf *m; 1375 struct ieee80211_node *ni; 1376 1377 IWN_LOCK_ASSERT(sc); 1378 while ((m = mbufq_dequeue(&sc->sc_xmit_queue)) != NULL) { 1379 ni = (struct ieee80211_node *)m->m_pkthdr.rcvif; 1380 ieee80211_free_node(ni); 1381 m_freem(m); 1382 } 1383 } 1384 1385 static int 1386 iwn_xmit_queue_enqueue(struct iwn_softc *sc, struct mbuf *m) 1387 { 1388 1389 IWN_LOCK_ASSERT(sc); 1390 return (mbufq_enqueue(&sc->sc_xmit_queue, m)); 1391 } 1392 1393 static int 1394 iwn_detach(device_t dev) 1395 { 1396 struct iwn_softc *sc = device_get_softc(dev); 1397 int qid; 1398 1399 DPRINTF(sc, IWN_DEBUG_TRACE, "->%s begin\n", __func__); 1400 1401 if (sc->sc_ic.ic_softc != NULL) { 1402 /* Free the mbuf queue and node references */ 1403 IWN_LOCK(sc); 1404 iwn_xmit_queue_drain(sc); 1405 IWN_UNLOCK(sc); 1406 1407 iwn_stop(sc); 1408 1409 taskqueue_drain_all(sc->sc_tq); 1410 taskqueue_free(sc->sc_tq); 1411 1412 callout_drain(&sc->watchdog_to); 1413 callout_drain(&sc->scan_timeout); 1414 callout_drain(&sc->calib_to); 1415 ieee80211_ifdetach(&sc->sc_ic); 1416 } 1417 1418 /* Uninstall interrupt handler. */ 1419 if (sc->irq != NULL) { 1420 bus_teardown_intr(dev, sc->irq, sc->sc_ih); 1421 bus_release_resource(dev, SYS_RES_IRQ, rman_get_rid(sc->irq), 1422 sc->irq); 1423 pci_release_msi(dev); 1424 } 1425 1426 /* Free DMA resources. */ 1427 iwn_free_rx_ring(sc, &sc->rxq); 1428 for (qid = 0; qid < sc->ntxqs; qid++) 1429 iwn_free_tx_ring(sc, &sc->txq[qid]); 1430 iwn_free_sched(sc); 1431 iwn_free_kw(sc); 1432 if (sc->ict != NULL) 1433 iwn_free_ict(sc); 1434 iwn_free_fwmem(sc); 1435 1436 if (sc->mem != NULL) 1437 bus_release_resource(dev, SYS_RES_MEMORY, 1438 rman_get_rid(sc->mem), sc->mem); 1439 1440 if (sc->sc_cdev) { 1441 destroy_dev(sc->sc_cdev); 1442 sc->sc_cdev = NULL; 1443 } 1444 1445 DPRINTF(sc, IWN_DEBUG_TRACE, "->%s: end\n", __func__); 1446 IWN_LOCK_DESTROY(sc); 1447 return 0; 1448 } 1449 1450 static int 1451 iwn_shutdown(device_t dev) 1452 { 1453 struct iwn_softc *sc = device_get_softc(dev); 1454 1455 iwn_stop(sc); 1456 return 0; 1457 } 1458 1459 static int 1460 iwn_suspend(device_t dev) 1461 { 1462 struct iwn_softc *sc = device_get_softc(dev); 1463 1464 ieee80211_suspend_all(&sc->sc_ic); 1465 return 0; 1466 } 1467 1468 static int 1469 iwn_resume(device_t dev) 1470 { 1471 struct iwn_softc *sc = device_get_softc(dev); 1472 1473 /* Clear device-specific "PCI retry timeout" register (41h). */ 1474 pci_write_config(dev, 0x41, 0, 1); 1475 1476 ieee80211_resume_all(&sc->sc_ic); 1477 return 0; 1478 } 1479 1480 static int 1481 iwn_nic_lock(struct iwn_softc *sc) 1482 { 1483 int ntries; 1484 1485 /* Request exclusive access to NIC. */ 1486 IWN_SETBITS(sc, IWN_GP_CNTRL, IWN_GP_CNTRL_MAC_ACCESS_REQ); 1487 1488 /* Spin until we actually get the lock. */ 1489 for (ntries = 0; ntries < 1000; ntries++) { 1490 if ((IWN_READ(sc, IWN_GP_CNTRL) & 1491 (IWN_GP_CNTRL_MAC_ACCESS_ENA | IWN_GP_CNTRL_SLEEP)) == 1492 IWN_GP_CNTRL_MAC_ACCESS_ENA) 1493 return 0; 1494 DELAY(10); 1495 } 1496 return ETIMEDOUT; 1497 } 1498 1499 static __inline void 1500 iwn_nic_unlock(struct iwn_softc *sc) 1501 { 1502 IWN_CLRBITS(sc, IWN_GP_CNTRL, IWN_GP_CNTRL_MAC_ACCESS_REQ); 1503 } 1504 1505 static __inline uint32_t 1506 iwn_prph_read(struct iwn_softc *sc, uint32_t addr) 1507 { 1508 IWN_WRITE(sc, IWN_PRPH_RADDR, IWN_PRPH_DWORD | addr); 1509 IWN_BARRIER_READ_WRITE(sc); 1510 return IWN_READ(sc, IWN_PRPH_RDATA); 1511 } 1512 1513 static __inline void 1514 iwn_prph_write(struct iwn_softc *sc, uint32_t addr, uint32_t data) 1515 { 1516 IWN_WRITE(sc, IWN_PRPH_WADDR, IWN_PRPH_DWORD | addr); 1517 IWN_BARRIER_WRITE(sc); 1518 IWN_WRITE(sc, IWN_PRPH_WDATA, data); 1519 } 1520 1521 static __inline void 1522 iwn_prph_setbits(struct iwn_softc *sc, uint32_t addr, uint32_t mask) 1523 { 1524 iwn_prph_write(sc, addr, iwn_prph_read(sc, addr) | mask); 1525 } 1526 1527 static __inline void 1528 iwn_prph_clrbits(struct iwn_softc *sc, uint32_t addr, uint32_t mask) 1529 { 1530 iwn_prph_write(sc, addr, iwn_prph_read(sc, addr) & ~mask); 1531 } 1532 1533 static __inline void 1534 iwn_prph_write_region_4(struct iwn_softc *sc, uint32_t addr, 1535 const uint32_t *data, int count) 1536 { 1537 for (; count > 0; count--, data++, addr += 4) 1538 iwn_prph_write(sc, addr, *data); 1539 } 1540 1541 static __inline uint32_t 1542 iwn_mem_read(struct iwn_softc *sc, uint32_t addr) 1543 { 1544 IWN_WRITE(sc, IWN_MEM_RADDR, addr); 1545 IWN_BARRIER_READ_WRITE(sc); 1546 return IWN_READ(sc, IWN_MEM_RDATA); 1547 } 1548 1549 static __inline void 1550 iwn_mem_write(struct iwn_softc *sc, uint32_t addr, uint32_t data) 1551 { 1552 IWN_WRITE(sc, IWN_MEM_WADDR, addr); 1553 IWN_BARRIER_WRITE(sc); 1554 IWN_WRITE(sc, IWN_MEM_WDATA, data); 1555 } 1556 1557 static __inline void 1558 iwn_mem_write_2(struct iwn_softc *sc, uint32_t addr, uint16_t data) 1559 { 1560 uint32_t tmp; 1561 1562 tmp = iwn_mem_read(sc, addr & ~3); 1563 if (addr & 3) 1564 tmp = (tmp & 0x0000ffff) | data << 16; 1565 else 1566 tmp = (tmp & 0xffff0000) | data; 1567 iwn_mem_write(sc, addr & ~3, tmp); 1568 } 1569 1570 static __inline void 1571 iwn_mem_read_region_4(struct iwn_softc *sc, uint32_t addr, uint32_t *data, 1572 int count) 1573 { 1574 for (; count > 0; count--, addr += 4) 1575 *data++ = iwn_mem_read(sc, addr); 1576 } 1577 1578 static __inline void 1579 iwn_mem_set_region_4(struct iwn_softc *sc, uint32_t addr, uint32_t val, 1580 int count) 1581 { 1582 for (; count > 0; count--, addr += 4) 1583 iwn_mem_write(sc, addr, val); 1584 } 1585 1586 static int 1587 iwn_eeprom_lock(struct iwn_softc *sc) 1588 { 1589 int i, ntries; 1590 1591 for (i = 0; i < 100; i++) { 1592 /* Request exclusive access to EEPROM. */ 1593 IWN_SETBITS(sc, IWN_HW_IF_CONFIG, 1594 IWN_HW_IF_CONFIG_EEPROM_LOCKED); 1595 1596 /* Spin until we actually get the lock. */ 1597 for (ntries = 0; ntries < 100; ntries++) { 1598 if (IWN_READ(sc, IWN_HW_IF_CONFIG) & 1599 IWN_HW_IF_CONFIG_EEPROM_LOCKED) 1600 return 0; 1601 DELAY(10); 1602 } 1603 } 1604 DPRINTF(sc, IWN_DEBUG_TRACE, "->%s end timeout\n", __func__); 1605 return ETIMEDOUT; 1606 } 1607 1608 static __inline void 1609 iwn_eeprom_unlock(struct iwn_softc *sc) 1610 { 1611 IWN_CLRBITS(sc, IWN_HW_IF_CONFIG, IWN_HW_IF_CONFIG_EEPROM_LOCKED); 1612 } 1613 1614 /* 1615 * Initialize access by host to One Time Programmable ROM. 1616 * NB: This kind of ROM can be found on 1000 or 6000 Series only. 1617 */ 1618 static int 1619 iwn_init_otprom(struct iwn_softc *sc) 1620 { 1621 uint16_t prev, base, next; 1622 int count, error; 1623 1624 DPRINTF(sc, IWN_DEBUG_TRACE, "->%s begin\n", __func__); 1625 1626 /* Wait for clock stabilization before accessing prph. */ 1627 if ((error = iwn_clock_wait(sc)) != 0) 1628 return error; 1629 1630 if ((error = iwn_nic_lock(sc)) != 0) 1631 return error; 1632 iwn_prph_setbits(sc, IWN_APMG_PS, IWN_APMG_PS_RESET_REQ); 1633 DELAY(5); 1634 iwn_prph_clrbits(sc, IWN_APMG_PS, IWN_APMG_PS_RESET_REQ); 1635 iwn_nic_unlock(sc); 1636 1637 /* Set auto clock gate disable bit for HW with OTP shadow RAM. */ 1638 if (sc->base_params->shadow_ram_support) { 1639 IWN_SETBITS(sc, IWN_DBG_LINK_PWR_MGMT, 1640 IWN_RESET_LINK_PWR_MGMT_DIS); 1641 } 1642 IWN_CLRBITS(sc, IWN_EEPROM_GP, IWN_EEPROM_GP_IF_OWNER); 1643 /* Clear ECC status. */ 1644 IWN_SETBITS(sc, IWN_OTP_GP, 1645 IWN_OTP_GP_ECC_CORR_STTS | IWN_OTP_GP_ECC_UNCORR_STTS); 1646 1647 /* 1648 * Find the block before last block (contains the EEPROM image) 1649 * for HW without OTP shadow RAM. 1650 */ 1651 if (! sc->base_params->shadow_ram_support) { 1652 /* Switch to absolute addressing mode. */ 1653 IWN_CLRBITS(sc, IWN_OTP_GP, IWN_OTP_GP_RELATIVE_ACCESS); 1654 base = prev = 0; 1655 for (count = 0; count < sc->base_params->max_ll_items; 1656 count++) { 1657 error = iwn_read_prom_data(sc, base, &next, 2); 1658 if (error != 0) 1659 return error; 1660 if (next == 0) /* End of linked-list. */ 1661 break; 1662 prev = base; 1663 base = le16toh(next); 1664 } 1665 if (count == 0 || count == sc->base_params->max_ll_items) 1666 return EIO; 1667 /* Skip "next" word. */ 1668 sc->prom_base = prev + 1; 1669 } 1670 1671 DPRINTF(sc, IWN_DEBUG_TRACE, "->%s end\n", __func__); 1672 1673 return 0; 1674 } 1675 1676 static int 1677 iwn_read_prom_data(struct iwn_softc *sc, uint32_t addr, void *data, int count) 1678 { 1679 uint8_t *out = data; 1680 uint32_t val, tmp; 1681 int ntries; 1682 1683 DPRINTF(sc, IWN_DEBUG_TRACE, "->%s begin\n", __func__); 1684 1685 addr += sc->prom_base; 1686 for (; count > 0; count -= 2, addr++) { 1687 IWN_WRITE(sc, IWN_EEPROM, addr << 2); 1688 for (ntries = 0; ntries < 20; ntries++) { 1689 val = IWN_READ(sc, IWN_EEPROM); 1690 if (val & IWN_EEPROM_READ_VALID) 1691 break; 1692 DELAY(5); 1693 } 1694 if (ntries == 20) { 1695 device_printf(sc->sc_dev, 1696 "timeout reading ROM at 0x%x\n", addr); 1697 return ETIMEDOUT; 1698 } 1699 if (sc->sc_flags & IWN_FLAG_HAS_OTPROM) { 1700 /* OTPROM, check for ECC errors. */ 1701 tmp = IWN_READ(sc, IWN_OTP_GP); 1702 if (tmp & IWN_OTP_GP_ECC_UNCORR_STTS) { 1703 device_printf(sc->sc_dev, 1704 "OTPROM ECC error at 0x%x\n", addr); 1705 return EIO; 1706 } 1707 if (tmp & IWN_OTP_GP_ECC_CORR_STTS) { 1708 /* Correctable ECC error, clear bit. */ 1709 IWN_SETBITS(sc, IWN_OTP_GP, 1710 IWN_OTP_GP_ECC_CORR_STTS); 1711 } 1712 } 1713 *out++ = val >> 16; 1714 if (count > 1) 1715 *out++ = val >> 24; 1716 } 1717 1718 DPRINTF(sc, IWN_DEBUG_TRACE, "->%s end\n", __func__); 1719 1720 return 0; 1721 } 1722 1723 static void 1724 iwn_dma_map_addr(void *arg, bus_dma_segment_t *segs, int nsegs, int error) 1725 { 1726 if (error != 0) 1727 return; 1728 KASSERT(nsegs == 1, ("too many DMA segments, %d should be 1", nsegs)); 1729 *(bus_addr_t *)arg = segs[0].ds_addr; 1730 } 1731 1732 static int 1733 iwn_dma_contig_alloc(struct iwn_softc *sc, struct iwn_dma_info *dma, 1734 void **kvap, bus_size_t size, bus_size_t alignment) 1735 { 1736 int error; 1737 1738 dma->tag = NULL; 1739 dma->size = size; 1740 1741 error = bus_dma_tag_create(bus_get_dma_tag(sc->sc_dev), alignment, 1742 0, BUS_SPACE_MAXADDR_32BIT, BUS_SPACE_MAXADDR, NULL, NULL, size, 1743 1, size, 0, NULL, NULL, &dma->tag); 1744 if (error != 0) 1745 goto fail; 1746 1747 error = bus_dmamem_alloc(dma->tag, (void **)&dma->vaddr, 1748 BUS_DMA_NOWAIT | BUS_DMA_ZERO | BUS_DMA_COHERENT, &dma->map); 1749 if (error != 0) 1750 goto fail; 1751 1752 error = bus_dmamap_load(dma->tag, dma->map, dma->vaddr, size, 1753 iwn_dma_map_addr, &dma->paddr, BUS_DMA_NOWAIT); 1754 if (error != 0) 1755 goto fail; 1756 1757 bus_dmamap_sync(dma->tag, dma->map, BUS_DMASYNC_PREWRITE); 1758 1759 if (kvap != NULL) 1760 *kvap = dma->vaddr; 1761 1762 return 0; 1763 1764 fail: iwn_dma_contig_free(dma); 1765 return error; 1766 } 1767 1768 static void 1769 iwn_dma_contig_free(struct iwn_dma_info *dma) 1770 { 1771 if (dma->vaddr != NULL) { 1772 bus_dmamap_sync(dma->tag, dma->map, 1773 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); 1774 bus_dmamap_unload(dma->tag, dma->map); 1775 bus_dmamem_free(dma->tag, dma->vaddr, dma->map); 1776 dma->vaddr = NULL; 1777 } 1778 if (dma->tag != NULL) { 1779 bus_dma_tag_destroy(dma->tag); 1780 dma->tag = NULL; 1781 } 1782 } 1783 1784 static int 1785 iwn_alloc_sched(struct iwn_softc *sc) 1786 { 1787 /* TX scheduler rings must be aligned on a 1KB boundary. */ 1788 return iwn_dma_contig_alloc(sc, &sc->sched_dma, (void **)&sc->sched, 1789 sc->schedsz, 1024); 1790 } 1791 1792 static void 1793 iwn_free_sched(struct iwn_softc *sc) 1794 { 1795 iwn_dma_contig_free(&sc->sched_dma); 1796 } 1797 1798 static int 1799 iwn_alloc_kw(struct iwn_softc *sc) 1800 { 1801 /* "Keep Warm" page must be aligned on a 4KB boundary. */ 1802 return iwn_dma_contig_alloc(sc, &sc->kw_dma, NULL, 4096, 4096); 1803 } 1804 1805 static void 1806 iwn_free_kw(struct iwn_softc *sc) 1807 { 1808 iwn_dma_contig_free(&sc->kw_dma); 1809 } 1810 1811 static int 1812 iwn_alloc_ict(struct iwn_softc *sc) 1813 { 1814 /* ICT table must be aligned on a 4KB boundary. */ 1815 return iwn_dma_contig_alloc(sc, &sc->ict_dma, (void **)&sc->ict, 1816 IWN_ICT_SIZE, 4096); 1817 } 1818 1819 static void 1820 iwn_free_ict(struct iwn_softc *sc) 1821 { 1822 iwn_dma_contig_free(&sc->ict_dma); 1823 } 1824 1825 static int 1826 iwn_alloc_fwmem(struct iwn_softc *sc) 1827 { 1828 /* Must be aligned on a 16-byte boundary. */ 1829 return iwn_dma_contig_alloc(sc, &sc->fw_dma, NULL, sc->fwsz, 16); 1830 } 1831 1832 static void 1833 iwn_free_fwmem(struct iwn_softc *sc) 1834 { 1835 iwn_dma_contig_free(&sc->fw_dma); 1836 } 1837 1838 static int 1839 iwn_alloc_rx_ring(struct iwn_softc *sc, struct iwn_rx_ring *ring) 1840 { 1841 bus_size_t size; 1842 int i, error; 1843 1844 ring->cur = 0; 1845 1846 DPRINTF(sc, IWN_DEBUG_TRACE, "->%s begin\n", __func__); 1847 1848 /* Allocate RX descriptors (256-byte aligned). */ 1849 size = IWN_RX_RING_COUNT * sizeof (uint32_t); 1850 error = iwn_dma_contig_alloc(sc, &ring->desc_dma, (void **)&ring->desc, 1851 size, 256); 1852 if (error != 0) { 1853 device_printf(sc->sc_dev, 1854 "%s: could not allocate RX ring DMA memory, error %d\n", 1855 __func__, error); 1856 goto fail; 1857 } 1858 1859 /* Allocate RX status area (16-byte aligned). */ 1860 error = iwn_dma_contig_alloc(sc, &ring->stat_dma, (void **)&ring->stat, 1861 sizeof (struct iwn_rx_status), 16); 1862 if (error != 0) { 1863 device_printf(sc->sc_dev, 1864 "%s: could not allocate RX status DMA memory, error %d\n", 1865 __func__, error); 1866 goto fail; 1867 } 1868 1869 /* Create RX buffer DMA tag. */ 1870 error = bus_dma_tag_create(bus_get_dma_tag(sc->sc_dev), 1, 0, 1871 BUS_SPACE_MAXADDR_32BIT, BUS_SPACE_MAXADDR, NULL, NULL, 1872 IWN_RBUF_SIZE, 1, IWN_RBUF_SIZE, 0, NULL, NULL, &ring->data_dmat); 1873 if (error != 0) { 1874 device_printf(sc->sc_dev, 1875 "%s: could not create RX buf DMA tag, error %d\n", 1876 __func__, error); 1877 goto fail; 1878 } 1879 1880 /* 1881 * Allocate and map RX buffers. 1882 */ 1883 for (i = 0; i < IWN_RX_RING_COUNT; i++) { 1884 struct iwn_rx_data *data = &ring->data[i]; 1885 bus_addr_t paddr; 1886 1887 error = bus_dmamap_create(ring->data_dmat, 0, &data->map); 1888 if (error != 0) { 1889 device_printf(sc->sc_dev, 1890 "%s: could not create RX buf DMA map, error %d\n", 1891 __func__, error); 1892 goto fail; 1893 } 1894 1895 data->m = m_getjcl(M_NOWAIT, MT_DATA, M_PKTHDR, 1896 IWN_RBUF_SIZE); 1897 if (data->m == NULL) { 1898 device_printf(sc->sc_dev, 1899 "%s: could not allocate RX mbuf\n", __func__); 1900 error = ENOBUFS; 1901 goto fail; 1902 } 1903 1904 error = bus_dmamap_load(ring->data_dmat, data->map, 1905 mtod(data->m, void *), IWN_RBUF_SIZE, iwn_dma_map_addr, 1906 &paddr, BUS_DMA_NOWAIT); 1907 if (error != 0 && error != EFBIG) { 1908 device_printf(sc->sc_dev, 1909 "%s: can't map mbuf, error %d\n", __func__, 1910 error); 1911 goto fail; 1912 } 1913 1914 bus_dmamap_sync(ring->data_dmat, data->map, 1915 BUS_DMASYNC_PREREAD); 1916 1917 /* Set physical address of RX buffer (256-byte aligned). */ 1918 ring->desc[i] = htole32(paddr >> 8); 1919 } 1920 1921 bus_dmamap_sync(ring->desc_dma.tag, ring->desc_dma.map, 1922 BUS_DMASYNC_PREWRITE); 1923 1924 DPRINTF(sc, IWN_DEBUG_TRACE, "->%s: end\n",__func__); 1925 1926 return 0; 1927 1928 fail: iwn_free_rx_ring(sc, ring); 1929 1930 DPRINTF(sc, IWN_DEBUG_TRACE, "->%s: end in error\n",__func__); 1931 1932 return error; 1933 } 1934 1935 static void 1936 iwn_reset_rx_ring(struct iwn_softc *sc, struct iwn_rx_ring *ring) 1937 { 1938 int ntries; 1939 1940 DPRINTF(sc, IWN_DEBUG_TRACE, "->Doing %s\n", __func__); 1941 1942 if (iwn_nic_lock(sc) == 0) { 1943 IWN_WRITE(sc, IWN_FH_RX_CONFIG, 0); 1944 for (ntries = 0; ntries < 1000; ntries++) { 1945 if (IWN_READ(sc, IWN_FH_RX_STATUS) & 1946 IWN_FH_RX_STATUS_IDLE) 1947 break; 1948 DELAY(10); 1949 } 1950 iwn_nic_unlock(sc); 1951 } 1952 ring->cur = 0; 1953 sc->last_rx_valid = 0; 1954 } 1955 1956 static void 1957 iwn_free_rx_ring(struct iwn_softc *sc, struct iwn_rx_ring *ring) 1958 { 1959 int i; 1960 1961 DPRINTF(sc, IWN_DEBUG_TRACE, "->Doing %s \n", __func__); 1962 1963 iwn_dma_contig_free(&ring->desc_dma); 1964 iwn_dma_contig_free(&ring->stat_dma); 1965 1966 for (i = 0; i < IWN_RX_RING_COUNT; i++) { 1967 struct iwn_rx_data *data = &ring->data[i]; 1968 1969 if (data->m != NULL) { 1970 bus_dmamap_sync(ring->data_dmat, data->map, 1971 BUS_DMASYNC_POSTREAD); 1972 bus_dmamap_unload(ring->data_dmat, data->map); 1973 m_freem(data->m); 1974 data->m = NULL; 1975 } 1976 if (data->map != NULL) 1977 bus_dmamap_destroy(ring->data_dmat, data->map); 1978 } 1979 if (ring->data_dmat != NULL) { 1980 bus_dma_tag_destroy(ring->data_dmat); 1981 ring->data_dmat = NULL; 1982 } 1983 } 1984 1985 static int 1986 iwn_alloc_tx_ring(struct iwn_softc *sc, struct iwn_tx_ring *ring, int qid) 1987 { 1988 bus_addr_t paddr; 1989 bus_size_t size; 1990 int i, error; 1991 1992 ring->qid = qid; 1993 ring->queued = 0; 1994 ring->cur = 0; 1995 1996 DPRINTF(sc, IWN_DEBUG_TRACE, "->%s begin\n", __func__); 1997 1998 /* Allocate TX descriptors (256-byte aligned). */ 1999 size = IWN_TX_RING_COUNT * sizeof (struct iwn_tx_desc); 2000 error = iwn_dma_contig_alloc(sc, &ring->desc_dma, (void **)&ring->desc, 2001 size, 256); 2002 if (error != 0) { 2003 device_printf(sc->sc_dev, 2004 "%s: could not allocate TX ring DMA memory, error %d\n", 2005 __func__, error); 2006 goto fail; 2007 } 2008 2009 size = IWN_TX_RING_COUNT * sizeof (struct iwn_tx_cmd); 2010 error = iwn_dma_contig_alloc(sc, &ring->cmd_dma, (void **)&ring->cmd, 2011 size, 4); 2012 if (error != 0) { 2013 device_printf(sc->sc_dev, 2014 "%s: could not allocate TX cmd DMA memory, error %d\n", 2015 __func__, error); 2016 goto fail; 2017 } 2018 2019 error = bus_dma_tag_create(bus_get_dma_tag(sc->sc_dev), 1, 0, 2020 BUS_SPACE_MAXADDR_32BIT, BUS_SPACE_MAXADDR, NULL, NULL, MCLBYTES, 2021 IWN_MAX_SCATTER - 1, MCLBYTES, 0, NULL, NULL, &ring->data_dmat); 2022 if (error != 0) { 2023 device_printf(sc->sc_dev, 2024 "%s: could not create TX buf DMA tag, error %d\n", 2025 __func__, error); 2026 goto fail; 2027 } 2028 2029 paddr = ring->cmd_dma.paddr; 2030 for (i = 0; i < IWN_TX_RING_COUNT; i++) { 2031 struct iwn_tx_data *data = &ring->data[i]; 2032 2033 data->cmd_paddr = paddr; 2034 data->scratch_paddr = paddr + 12; 2035 paddr += sizeof (struct iwn_tx_cmd); 2036 2037 error = bus_dmamap_create(ring->data_dmat, 0, &data->map); 2038 if (error != 0) { 2039 device_printf(sc->sc_dev, 2040 "%s: could not create TX buf DMA map, error %d\n", 2041 __func__, error); 2042 goto fail; 2043 } 2044 } 2045 2046 DPRINTF(sc, IWN_DEBUG_TRACE, "->%s end\n", __func__); 2047 2048 return 0; 2049 2050 fail: iwn_free_tx_ring(sc, ring); 2051 DPRINTF(sc, IWN_DEBUG_TRACE, "->%s end in error\n", __func__); 2052 return error; 2053 } 2054 2055 static void 2056 iwn_reset_tx_ring(struct iwn_softc *sc, struct iwn_tx_ring *ring) 2057 { 2058 int i; 2059 2060 DPRINTF(sc, IWN_DEBUG_TRACE, "->doing %s \n", __func__); 2061 2062 for (i = 0; i < IWN_TX_RING_COUNT; i++) { 2063 struct iwn_tx_data *data = &ring->data[i]; 2064 2065 if (data->m != NULL) { 2066 bus_dmamap_sync(ring->data_dmat, data->map, 2067 BUS_DMASYNC_POSTWRITE); 2068 bus_dmamap_unload(ring->data_dmat, data->map); 2069 m_freem(data->m); 2070 data->m = NULL; 2071 } 2072 if (data->ni != NULL) { 2073 ieee80211_free_node(data->ni); 2074 data->ni = NULL; 2075 } 2076 data->remapped = 0; 2077 data->long_retries = 0; 2078 } 2079 /* Clear TX descriptors. */ 2080 memset(ring->desc, 0, ring->desc_dma.size); 2081 bus_dmamap_sync(ring->desc_dma.tag, ring->desc_dma.map, 2082 BUS_DMASYNC_PREWRITE); 2083 sc->qfullmsk &= ~(1 << ring->qid); 2084 ring->queued = 0; 2085 ring->cur = 0; 2086 } 2087 2088 static void 2089 iwn_free_tx_ring(struct iwn_softc *sc, struct iwn_tx_ring *ring) 2090 { 2091 int i; 2092 2093 DPRINTF(sc, IWN_DEBUG_TRACE, "->Doing %s \n", __func__); 2094 2095 iwn_dma_contig_free(&ring->desc_dma); 2096 iwn_dma_contig_free(&ring->cmd_dma); 2097 2098 for (i = 0; i < IWN_TX_RING_COUNT; i++) { 2099 struct iwn_tx_data *data = &ring->data[i]; 2100 2101 if (data->m != NULL) { 2102 bus_dmamap_sync(ring->data_dmat, data->map, 2103 BUS_DMASYNC_POSTWRITE); 2104 bus_dmamap_unload(ring->data_dmat, data->map); 2105 m_freem(data->m); 2106 } 2107 if (data->map != NULL) 2108 bus_dmamap_destroy(ring->data_dmat, data->map); 2109 } 2110 if (ring->data_dmat != NULL) { 2111 bus_dma_tag_destroy(ring->data_dmat); 2112 ring->data_dmat = NULL; 2113 } 2114 } 2115 2116 static void 2117 iwn_check_tx_ring(struct iwn_softc *sc, int qid) 2118 { 2119 struct iwn_tx_ring *ring = &sc->txq[qid]; 2120 2121 KASSERT(ring->queued >= 0, ("%s: ring->queued (%d) for queue %d < 0!", 2122 __func__, ring->queued, qid)); 2123 2124 if (qid >= sc->firstaggqueue) { 2125 struct iwn_ops *ops = &sc->ops; 2126 struct ieee80211_tx_ampdu *tap = sc->qid2tap[qid]; 2127 2128 if (ring->queued == 0 && !IEEE80211_AMPDU_RUNNING(tap)) { 2129 uint16_t ssn = tap->txa_start & 0xfff; 2130 uint8_t tid = tap->txa_tid; 2131 int *res = tap->txa_private; 2132 2133 iwn_nic_lock(sc); 2134 ops->ampdu_tx_stop(sc, qid, tid, ssn); 2135 iwn_nic_unlock(sc); 2136 2137 sc->qid2tap[qid] = NULL; 2138 free(res, M_DEVBUF); 2139 } 2140 } 2141 2142 if (ring->queued < IWN_TX_RING_LOMARK) { 2143 sc->qfullmsk &= ~(1 << qid); 2144 2145 if (ring->queued == 0) 2146 sc->sc_tx_timer = 0; 2147 else 2148 sc->sc_tx_timer = 5; 2149 } 2150 } 2151 2152 static void 2153 iwn5000_ict_reset(struct iwn_softc *sc) 2154 { 2155 /* Disable interrupts. */ 2156 IWN_WRITE(sc, IWN_INT_MASK, 0); 2157 2158 /* Reset ICT table. */ 2159 memset(sc->ict, 0, IWN_ICT_SIZE); 2160 sc->ict_cur = 0; 2161 2162 bus_dmamap_sync(sc->ict_dma.tag, sc->ict_dma.map, 2163 BUS_DMASYNC_PREWRITE); 2164 2165 /* Set physical address of ICT table (4KB aligned). */ 2166 DPRINTF(sc, IWN_DEBUG_RESET, "%s: enabling ICT\n", __func__); 2167 IWN_WRITE(sc, IWN_DRAM_INT_TBL, IWN_DRAM_INT_TBL_ENABLE | 2168 IWN_DRAM_INT_TBL_WRAP_CHECK | sc->ict_dma.paddr >> 12); 2169 2170 /* Enable periodic RX interrupt. */ 2171 sc->int_mask |= IWN_INT_RX_PERIODIC; 2172 /* Switch to ICT interrupt mode in driver. */ 2173 sc->sc_flags |= IWN_FLAG_USE_ICT; 2174 2175 /* Re-enable interrupts. */ 2176 IWN_WRITE(sc, IWN_INT, 0xffffffff); 2177 IWN_WRITE(sc, IWN_INT_MASK, sc->int_mask); 2178 } 2179 2180 static int 2181 iwn_read_eeprom(struct iwn_softc *sc, uint8_t macaddr[IEEE80211_ADDR_LEN]) 2182 { 2183 struct iwn_ops *ops = &sc->ops; 2184 uint16_t val; 2185 int error; 2186 2187 DPRINTF(sc, IWN_DEBUG_TRACE, "->%s begin\n", __func__); 2188 2189 /* Check whether adapter has an EEPROM or an OTPROM. */ 2190 if (sc->hw_type >= IWN_HW_REV_TYPE_1000 && 2191 (IWN_READ(sc, IWN_OTP_GP) & IWN_OTP_GP_DEV_SEL_OTP)) 2192 sc->sc_flags |= IWN_FLAG_HAS_OTPROM; 2193 DPRINTF(sc, IWN_DEBUG_RESET, "%s found\n", 2194 (sc->sc_flags & IWN_FLAG_HAS_OTPROM) ? "OTPROM" : "EEPROM"); 2195 2196 /* Adapter has to be powered on for EEPROM access to work. */ 2197 if ((error = iwn_apm_init(sc)) != 0) { 2198 device_printf(sc->sc_dev, 2199 "%s: could not power ON adapter, error %d\n", __func__, 2200 error); 2201 return error; 2202 } 2203 2204 if ((IWN_READ(sc, IWN_EEPROM_GP) & 0x7) == 0) { 2205 device_printf(sc->sc_dev, "%s: bad ROM signature\n", __func__); 2206 return EIO; 2207 } 2208 if ((error = iwn_eeprom_lock(sc)) != 0) { 2209 device_printf(sc->sc_dev, "%s: could not lock ROM, error %d\n", 2210 __func__, error); 2211 return error; 2212 } 2213 if (sc->sc_flags & IWN_FLAG_HAS_OTPROM) { 2214 if ((error = iwn_init_otprom(sc)) != 0) { 2215 device_printf(sc->sc_dev, 2216 "%s: could not initialize OTPROM, error %d\n", 2217 __func__, error); 2218 return error; 2219 } 2220 } 2221 2222 iwn_read_prom_data(sc, IWN_EEPROM_SKU_CAP, &val, 2); 2223 DPRINTF(sc, IWN_DEBUG_RESET, "SKU capabilities=0x%04x\n", le16toh(val)); 2224 /* Check if HT support is bonded out. */ 2225 if (val & htole16(IWN_EEPROM_SKU_CAP_11N)) 2226 sc->sc_flags |= IWN_FLAG_HAS_11N; 2227 2228 iwn_read_prom_data(sc, IWN_EEPROM_RFCFG, &val, 2); 2229 sc->rfcfg = le16toh(val); 2230 DPRINTF(sc, IWN_DEBUG_RESET, "radio config=0x%04x\n", sc->rfcfg); 2231 /* Read Tx/Rx chains from ROM unless it's known to be broken. */ 2232 if (sc->txchainmask == 0) 2233 sc->txchainmask = IWN_RFCFG_TXANTMSK(sc->rfcfg); 2234 if (sc->rxchainmask == 0) 2235 sc->rxchainmask = IWN_RFCFG_RXANTMSK(sc->rfcfg); 2236 2237 /* Read MAC address. */ 2238 iwn_read_prom_data(sc, IWN_EEPROM_MAC, macaddr, 6); 2239 2240 /* Read adapter-specific information from EEPROM. */ 2241 ops->read_eeprom(sc); 2242 2243 iwn_apm_stop(sc); /* Power OFF adapter. */ 2244 2245 iwn_eeprom_unlock(sc); 2246 2247 DPRINTF(sc, IWN_DEBUG_TRACE, "->%s end\n", __func__); 2248 2249 return 0; 2250 } 2251 2252 static void 2253 iwn4965_read_eeprom(struct iwn_softc *sc) 2254 { 2255 uint32_t addr; 2256 uint16_t val; 2257 int i; 2258 2259 DPRINTF(sc, IWN_DEBUG_TRACE, "->%s begin\n", __func__); 2260 2261 /* Read regulatory domain (4 ASCII characters). */ 2262 iwn_read_prom_data(sc, IWN4965_EEPROM_DOMAIN, sc->eeprom_domain, 4); 2263 2264 /* Read the list of authorized channels (20MHz & 40MHz). */ 2265 for (i = 0; i < IWN_NBANDS - 1; i++) { 2266 addr = iwn4965_regulatory_bands[i]; 2267 iwn_read_eeprom_channels(sc, i, addr); 2268 } 2269 2270 /* Read maximum allowed TX power for 2GHz and 5GHz bands. */ 2271 iwn_read_prom_data(sc, IWN4965_EEPROM_MAXPOW, &val, 2); 2272 sc->maxpwr2GHz = val & 0xff; 2273 sc->maxpwr5GHz = val >> 8; 2274 /* Check that EEPROM values are within valid range. */ 2275 if (sc->maxpwr5GHz < 20 || sc->maxpwr5GHz > 50) 2276 sc->maxpwr5GHz = 38; 2277 if (sc->maxpwr2GHz < 20 || sc->maxpwr2GHz > 50) 2278 sc->maxpwr2GHz = 38; 2279 DPRINTF(sc, IWN_DEBUG_RESET, "maxpwr 2GHz=%d 5GHz=%d\n", 2280 sc->maxpwr2GHz, sc->maxpwr5GHz); 2281 2282 /* Read samples for each TX power group. */ 2283 iwn_read_prom_data(sc, IWN4965_EEPROM_BANDS, sc->bands, 2284 sizeof sc->bands); 2285 2286 /* Read voltage at which samples were taken. */ 2287 iwn_read_prom_data(sc, IWN4965_EEPROM_VOLTAGE, &val, 2); 2288 sc->eeprom_voltage = (int16_t)le16toh(val); 2289 DPRINTF(sc, IWN_DEBUG_RESET, "voltage=%d (in 0.3V)\n", 2290 sc->eeprom_voltage); 2291 2292 #ifdef IWN_DEBUG 2293 /* Print samples. */ 2294 if (sc->sc_debug & IWN_DEBUG_ANY) { 2295 for (i = 0; i < IWN_NBANDS - 1; i++) 2296 iwn4965_print_power_group(sc, i); 2297 } 2298 #endif 2299 2300 DPRINTF(sc, IWN_DEBUG_TRACE, "->%s end\n", __func__); 2301 } 2302 2303 #ifdef IWN_DEBUG 2304 static void 2305 iwn4965_print_power_group(struct iwn_softc *sc, int i) 2306 { 2307 struct iwn4965_eeprom_band *band = &sc->bands[i]; 2308 struct iwn4965_eeprom_chan_samples *chans = band->chans; 2309 int j, c; 2310 2311 printf("===band %d===\n", i); 2312 printf("chan lo=%d, chan hi=%d\n", band->lo, band->hi); 2313 printf("chan1 num=%d\n", chans[0].num); 2314 for (c = 0; c < 2; c++) { 2315 for (j = 0; j < IWN_NSAMPLES; j++) { 2316 printf("chain %d, sample %d: temp=%d gain=%d " 2317 "power=%d pa_det=%d\n", c, j, 2318 chans[0].samples[c][j].temp, 2319 chans[0].samples[c][j].gain, 2320 chans[0].samples[c][j].power, 2321 chans[0].samples[c][j].pa_det); 2322 } 2323 } 2324 printf("chan2 num=%d\n", chans[1].num); 2325 for (c = 0; c < 2; c++) { 2326 for (j = 0; j < IWN_NSAMPLES; j++) { 2327 printf("chain %d, sample %d: temp=%d gain=%d " 2328 "power=%d pa_det=%d\n", c, j, 2329 chans[1].samples[c][j].temp, 2330 chans[1].samples[c][j].gain, 2331 chans[1].samples[c][j].power, 2332 chans[1].samples[c][j].pa_det); 2333 } 2334 } 2335 } 2336 #endif 2337 2338 static void 2339 iwn5000_read_eeprom(struct iwn_softc *sc) 2340 { 2341 struct iwn5000_eeprom_calib_hdr hdr; 2342 int32_t volt; 2343 uint32_t base, addr; 2344 uint16_t val; 2345 int i; 2346 2347 DPRINTF(sc, IWN_DEBUG_TRACE, "->%s begin\n", __func__); 2348 2349 /* Read regulatory domain (4 ASCII characters). */ 2350 iwn_read_prom_data(sc, IWN5000_EEPROM_REG, &val, 2); 2351 base = le16toh(val); 2352 iwn_read_prom_data(sc, base + IWN5000_EEPROM_DOMAIN, 2353 sc->eeprom_domain, 4); 2354 2355 /* Read the list of authorized channels (20MHz & 40MHz). */ 2356 for (i = 0; i < IWN_NBANDS - 1; i++) { 2357 addr = base + sc->base_params->regulatory_bands[i]; 2358 iwn_read_eeprom_channels(sc, i, addr); 2359 } 2360 2361 /* Read enhanced TX power information for 6000 Series. */ 2362 if (sc->base_params->enhanced_TX_power) 2363 iwn_read_eeprom_enhinfo(sc); 2364 2365 iwn_read_prom_data(sc, IWN5000_EEPROM_CAL, &val, 2); 2366 base = le16toh(val); 2367 iwn_read_prom_data(sc, base, &hdr, sizeof hdr); 2368 DPRINTF(sc, IWN_DEBUG_CALIBRATE, 2369 "%s: calib version=%u pa type=%u voltage=%u\n", __func__, 2370 hdr.version, hdr.pa_type, le16toh(hdr.volt)); 2371 sc->calib_ver = hdr.version; 2372 2373 if (sc->base_params->calib_need & IWN_FLG_NEED_PHY_CALIB_TEMP_OFFSETv2) { 2374 sc->eeprom_voltage = le16toh(hdr.volt); 2375 iwn_read_prom_data(sc, base + IWN5000_EEPROM_TEMP, &val, 2); 2376 sc->eeprom_temp_high=le16toh(val); 2377 iwn_read_prom_data(sc, base + IWN5000_EEPROM_VOLT, &val, 2); 2378 sc->eeprom_temp = le16toh(val); 2379 } 2380 2381 if (sc->hw_type == IWN_HW_REV_TYPE_5150) { 2382 /* Compute temperature offset. */ 2383 iwn_read_prom_data(sc, base + IWN5000_EEPROM_TEMP, &val, 2); 2384 sc->eeprom_temp = le16toh(val); 2385 iwn_read_prom_data(sc, base + IWN5000_EEPROM_VOLT, &val, 2); 2386 volt = le16toh(val); 2387 sc->temp_off = sc->eeprom_temp - (volt / -5); 2388 DPRINTF(sc, IWN_DEBUG_CALIBRATE, "temp=%d volt=%d offset=%dK\n", 2389 sc->eeprom_temp, volt, sc->temp_off); 2390 } else { 2391 /* Read crystal calibration. */ 2392 iwn_read_prom_data(sc, base + IWN5000_EEPROM_CRYSTAL, 2393 &sc->eeprom_crystal, sizeof (uint32_t)); 2394 DPRINTF(sc, IWN_DEBUG_CALIBRATE, "crystal calibration 0x%08x\n", 2395 le32toh(sc->eeprom_crystal)); 2396 } 2397 2398 DPRINTF(sc, IWN_DEBUG_TRACE, "->%s end\n", __func__); 2399 2400 } 2401 2402 /* 2403 * Translate EEPROM flags to net80211. 2404 */ 2405 static uint32_t 2406 iwn_eeprom_channel_flags(struct iwn_eeprom_chan *channel) 2407 { 2408 uint32_t nflags; 2409 2410 nflags = 0; 2411 if ((channel->flags & IWN_EEPROM_CHAN_ACTIVE) == 0) 2412 nflags |= IEEE80211_CHAN_PASSIVE; 2413 if ((channel->flags & IWN_EEPROM_CHAN_IBSS) == 0) 2414 nflags |= IEEE80211_CHAN_NOADHOC; 2415 if (channel->flags & IWN_EEPROM_CHAN_RADAR) { 2416 nflags |= IEEE80211_CHAN_DFS; 2417 /* XXX apparently IBSS may still be marked */ 2418 nflags |= IEEE80211_CHAN_NOADHOC; 2419 } 2420 2421 return nflags; 2422 } 2423 2424 static void 2425 iwn_read_eeprom_band(struct iwn_softc *sc, int n, int maxchans, int *nchans, 2426 struct ieee80211_channel chans[]) 2427 { 2428 struct iwn_eeprom_chan *channels = sc->eeprom_channels[n]; 2429 const struct iwn_chan_band *band = &iwn_bands[n]; 2430 uint8_t bands[IEEE80211_MODE_BYTES]; 2431 uint8_t chan; 2432 int i, error, nflags; 2433 2434 DPRINTF(sc, IWN_DEBUG_TRACE, "->%s begin\n", __func__); 2435 2436 memset(bands, 0, sizeof(bands)); 2437 if (n == 0) { 2438 setbit(bands, IEEE80211_MODE_11B); 2439 setbit(bands, IEEE80211_MODE_11G); 2440 if (sc->sc_flags & IWN_FLAG_HAS_11N) 2441 setbit(bands, IEEE80211_MODE_11NG); 2442 } else { 2443 setbit(bands, IEEE80211_MODE_11A); 2444 if (sc->sc_flags & IWN_FLAG_HAS_11N) 2445 setbit(bands, IEEE80211_MODE_11NA); 2446 } 2447 2448 for (i = 0; i < band->nchan; i++) { 2449 if (!(channels[i].flags & IWN_EEPROM_CHAN_VALID)) { 2450 DPRINTF(sc, IWN_DEBUG_RESET, 2451 "skip chan %d flags 0x%x maxpwr %d\n", 2452 band->chan[i], channels[i].flags, 2453 channels[i].maxpwr); 2454 continue; 2455 } 2456 2457 chan = band->chan[i]; 2458 nflags = iwn_eeprom_channel_flags(&channels[i]); 2459 error = ieee80211_add_channel(chans, maxchans, nchans, 2460 chan, 0, channels[i].maxpwr, nflags, bands); 2461 if (error != 0) 2462 break; 2463 2464 /* Save maximum allowed TX power for this channel. */ 2465 /* XXX wrong */ 2466 sc->maxpwr[chan] = channels[i].maxpwr; 2467 2468 DPRINTF(sc, IWN_DEBUG_RESET, 2469 "add chan %d flags 0x%x maxpwr %d\n", chan, 2470 channels[i].flags, channels[i].maxpwr); 2471 } 2472 2473 DPRINTF(sc, IWN_DEBUG_TRACE, "->%s end\n", __func__); 2474 2475 } 2476 2477 static void 2478 iwn_read_eeprom_ht40(struct iwn_softc *sc, int n, int maxchans, int *nchans, 2479 struct ieee80211_channel chans[]) 2480 { 2481 struct iwn_eeprom_chan *channels = sc->eeprom_channels[n]; 2482 const struct iwn_chan_band *band = &iwn_bands[n]; 2483 uint8_t chan; 2484 int i, error, nflags; 2485 2486 DPRINTF(sc, IWN_DEBUG_TRACE, "->%s start\n", __func__); 2487 2488 if (!(sc->sc_flags & IWN_FLAG_HAS_11N)) { 2489 DPRINTF(sc, IWN_DEBUG_TRACE, "->%s end no 11n\n", __func__); 2490 return; 2491 } 2492 2493 for (i = 0; i < band->nchan; i++) { 2494 if (!(channels[i].flags & IWN_EEPROM_CHAN_VALID)) { 2495 DPRINTF(sc, IWN_DEBUG_RESET, 2496 "skip chan %d flags 0x%x maxpwr %d\n", 2497 band->chan[i], channels[i].flags, 2498 channels[i].maxpwr); 2499 continue; 2500 } 2501 2502 chan = band->chan[i]; 2503 nflags = iwn_eeprom_channel_flags(&channels[i]); 2504 nflags |= (n == 5 ? IEEE80211_CHAN_G : IEEE80211_CHAN_A); 2505 error = ieee80211_add_channel_ht40(chans, maxchans, nchans, 2506 chan, channels[i].maxpwr, nflags); 2507 switch (error) { 2508 case EINVAL: 2509 device_printf(sc->sc_dev, 2510 "%s: no entry for channel %d\n", __func__, chan); 2511 continue; 2512 case ENOENT: 2513 DPRINTF(sc, IWN_DEBUG_RESET, 2514 "%s: skip chan %d, extension channel not found\n", 2515 __func__, chan); 2516 continue; 2517 case ENOBUFS: 2518 device_printf(sc->sc_dev, 2519 "%s: channel table is full!\n", __func__); 2520 break; 2521 case 0: 2522 DPRINTF(sc, IWN_DEBUG_RESET, 2523 "add ht40 chan %d flags 0x%x maxpwr %d\n", 2524 chan, channels[i].flags, channels[i].maxpwr); 2525 /* FALLTHROUGH */ 2526 default: 2527 break; 2528 } 2529 } 2530 2531 DPRINTF(sc, IWN_DEBUG_TRACE, "->%s end\n", __func__); 2532 2533 } 2534 2535 static void 2536 iwn_read_eeprom_channels(struct iwn_softc *sc, int n, uint32_t addr) 2537 { 2538 struct ieee80211com *ic = &sc->sc_ic; 2539 2540 iwn_read_prom_data(sc, addr, &sc->eeprom_channels[n], 2541 iwn_bands[n].nchan * sizeof (struct iwn_eeprom_chan)); 2542 2543 if (n < 5) { 2544 iwn_read_eeprom_band(sc, n, IEEE80211_CHAN_MAX, &ic->ic_nchans, 2545 ic->ic_channels); 2546 } else { 2547 iwn_read_eeprom_ht40(sc, n, IEEE80211_CHAN_MAX, &ic->ic_nchans, 2548 ic->ic_channels); 2549 } 2550 ieee80211_sort_channels(ic->ic_channels, ic->ic_nchans); 2551 } 2552 2553 static struct iwn_eeprom_chan * 2554 iwn_find_eeprom_channel(struct iwn_softc *sc, struct ieee80211_channel *c) 2555 { 2556 int band, chan, i, j; 2557 2558 if (IEEE80211_IS_CHAN_HT40(c)) { 2559 band = IEEE80211_IS_CHAN_5GHZ(c) ? 6 : 5; 2560 if (IEEE80211_IS_CHAN_HT40D(c)) 2561 chan = c->ic_extieee; 2562 else 2563 chan = c->ic_ieee; 2564 for (i = 0; i < iwn_bands[band].nchan; i++) { 2565 if (iwn_bands[band].chan[i] == chan) 2566 return &sc->eeprom_channels[band][i]; 2567 } 2568 } else { 2569 for (j = 0; j < 5; j++) { 2570 for (i = 0; i < iwn_bands[j].nchan; i++) { 2571 if (iwn_bands[j].chan[i] == c->ic_ieee && 2572 ((j == 0) ^ IEEE80211_IS_CHAN_A(c)) == 1) 2573 return &sc->eeprom_channels[j][i]; 2574 } 2575 } 2576 } 2577 return NULL; 2578 } 2579 2580 static void 2581 iwn_getradiocaps(struct ieee80211com *ic, 2582 int maxchans, int *nchans, struct ieee80211_channel chans[]) 2583 { 2584 struct iwn_softc *sc = ic->ic_softc; 2585 int i; 2586 2587 /* Parse the list of authorized channels. */ 2588 for (i = 0; i < 5 && *nchans < maxchans; i++) 2589 iwn_read_eeprom_band(sc, i, maxchans, nchans, chans); 2590 for (i = 5; i < IWN_NBANDS - 1 && *nchans < maxchans; i++) 2591 iwn_read_eeprom_ht40(sc, i, maxchans, nchans, chans); 2592 } 2593 2594 /* 2595 * Enforce flags read from EEPROM. 2596 */ 2597 static int 2598 iwn_setregdomain(struct ieee80211com *ic, struct ieee80211_regdomain *rd, 2599 int nchan, struct ieee80211_channel chans[]) 2600 { 2601 struct iwn_softc *sc = ic->ic_softc; 2602 int i; 2603 2604 for (i = 0; i < nchan; i++) { 2605 struct ieee80211_channel *c = &chans[i]; 2606 struct iwn_eeprom_chan *channel; 2607 2608 channel = iwn_find_eeprom_channel(sc, c); 2609 if (channel == NULL) { 2610 ic_printf(ic, "%s: invalid channel %u freq %u/0x%x\n", 2611 __func__, c->ic_ieee, c->ic_freq, c->ic_flags); 2612 return EINVAL; 2613 } 2614 c->ic_flags |= iwn_eeprom_channel_flags(channel); 2615 } 2616 2617 return 0; 2618 } 2619 2620 static void 2621 iwn_read_eeprom_enhinfo(struct iwn_softc *sc) 2622 { 2623 struct iwn_eeprom_enhinfo enhinfo[35]; 2624 struct ieee80211com *ic = &sc->sc_ic; 2625 struct ieee80211_channel *c; 2626 uint16_t val, base; 2627 int8_t maxpwr; 2628 uint8_t flags; 2629 int i, j; 2630 2631 DPRINTF(sc, IWN_DEBUG_TRACE, "->%s begin\n", __func__); 2632 2633 iwn_read_prom_data(sc, IWN5000_EEPROM_REG, &val, 2); 2634 base = le16toh(val); 2635 iwn_read_prom_data(sc, base + IWN6000_EEPROM_ENHINFO, 2636 enhinfo, sizeof enhinfo); 2637 2638 for (i = 0; i < nitems(enhinfo); i++) { 2639 flags = enhinfo[i].flags; 2640 if (!(flags & IWN_ENHINFO_VALID)) 2641 continue; /* Skip invalid entries. */ 2642 2643 maxpwr = 0; 2644 if (sc->txchainmask & IWN_ANT_A) 2645 maxpwr = MAX(maxpwr, enhinfo[i].chain[0]); 2646 if (sc->txchainmask & IWN_ANT_B) 2647 maxpwr = MAX(maxpwr, enhinfo[i].chain[1]); 2648 if (sc->txchainmask & IWN_ANT_C) 2649 maxpwr = MAX(maxpwr, enhinfo[i].chain[2]); 2650 if (sc->ntxchains == 2) 2651 maxpwr = MAX(maxpwr, enhinfo[i].mimo2); 2652 else if (sc->ntxchains == 3) 2653 maxpwr = MAX(maxpwr, enhinfo[i].mimo3); 2654 2655 for (j = 0; j < ic->ic_nchans; j++) { 2656 c = &ic->ic_channels[j]; 2657 if ((flags & IWN_ENHINFO_5GHZ)) { 2658 if (!IEEE80211_IS_CHAN_A(c)) 2659 continue; 2660 } else if ((flags & IWN_ENHINFO_OFDM)) { 2661 if (!IEEE80211_IS_CHAN_G(c)) 2662 continue; 2663 } else if (!IEEE80211_IS_CHAN_B(c)) 2664 continue; 2665 if ((flags & IWN_ENHINFO_HT40)) { 2666 if (!IEEE80211_IS_CHAN_HT40(c)) 2667 continue; 2668 } else { 2669 if (IEEE80211_IS_CHAN_HT40(c)) 2670 continue; 2671 } 2672 if (enhinfo[i].chan != 0 && 2673 enhinfo[i].chan != c->ic_ieee) 2674 continue; 2675 2676 DPRINTF(sc, IWN_DEBUG_RESET, 2677 "channel %d(%x), maxpwr %d\n", c->ic_ieee, 2678 c->ic_flags, maxpwr / 2); 2679 c->ic_maxregpower = maxpwr / 2; 2680 c->ic_maxpower = maxpwr; 2681 } 2682 } 2683 2684 DPRINTF(sc, IWN_DEBUG_TRACE, "->%s end\n", __func__); 2685 2686 } 2687 2688 static struct ieee80211_node * 2689 iwn_node_alloc(struct ieee80211vap *vap, const uint8_t mac[IEEE80211_ADDR_LEN]) 2690 { 2691 struct iwn_node *wn; 2692 2693 wn = malloc(sizeof (struct iwn_node), M_80211_NODE, M_NOWAIT | M_ZERO); 2694 if (wn == NULL) 2695 return (NULL); 2696 2697 wn->id = IWN_ID_UNDEFINED; 2698 2699 return (&wn->ni); 2700 } 2701 2702 static __inline int 2703 rate2plcp(int rate) 2704 { 2705 switch (rate & 0xff) { 2706 case 12: return 0xd; 2707 case 18: return 0xf; 2708 case 24: return 0x5; 2709 case 36: return 0x7; 2710 case 48: return 0x9; 2711 case 72: return 0xb; 2712 case 96: return 0x1; 2713 case 108: return 0x3; 2714 case 2: return 10; 2715 case 4: return 20; 2716 case 11: return 55; 2717 case 22: return 110; 2718 } 2719 return 0; 2720 } 2721 2722 static __inline uint8_t 2723 plcp2rate(const uint8_t rate_plcp) 2724 { 2725 switch (rate_plcp) { 2726 case 0xd: return 12; 2727 case 0xf: return 18; 2728 case 0x5: return 24; 2729 case 0x7: return 36; 2730 case 0x9: return 48; 2731 case 0xb: return 72; 2732 case 0x1: return 96; 2733 case 0x3: return 108; 2734 case 10: return 2; 2735 case 20: return 4; 2736 case 55: return 11; 2737 case 110: return 22; 2738 default: return 0; 2739 } 2740 } 2741 2742 static int 2743 iwn_get_1stream_tx_antmask(struct iwn_softc *sc) 2744 { 2745 2746 return IWN_LSB(sc->txchainmask); 2747 } 2748 2749 static int 2750 iwn_get_2stream_tx_antmask(struct iwn_softc *sc) 2751 { 2752 int tx; 2753 2754 /* 2755 * The '2 stream' setup is a bit .. odd. 2756 * 2757 * For NICs that support only 1 antenna, default to IWN_ANT_AB or 2758 * the firmware panics (eg Intel 5100.) 2759 * 2760 * For NICs that support two antennas, we use ANT_AB. 2761 * 2762 * For NICs that support three antennas, we use the two that 2763 * wasn't the default one. 2764 * 2765 * XXX TODO: if bluetooth (full concurrent) is enabled, restrict 2766 * this to only one antenna. 2767 */ 2768 2769 /* Default - transmit on the other antennas */ 2770 tx = (sc->txchainmask & ~IWN_LSB(sc->txchainmask)); 2771 2772 /* Now, if it's zero, set it to IWN_ANT_AB, so to not panic firmware */ 2773 if (tx == 0) 2774 tx = IWN_ANT_AB; 2775 2776 /* 2777 * If the NIC is a two-stream TX NIC, configure the TX mask to 2778 * the default chainmask 2779 */ 2780 else if (sc->ntxchains == 2) 2781 tx = sc->txchainmask; 2782 2783 return (tx); 2784 } 2785 2786 2787 2788 /* 2789 * Calculate the required PLCP value from the given rate, 2790 * to the given node. 2791 * 2792 * This will take the node configuration (eg 11n, rate table 2793 * setup, etc) into consideration. 2794 */ 2795 static uint32_t 2796 iwn_rate_to_plcp(struct iwn_softc *sc, struct ieee80211_node *ni, 2797 uint8_t rate) 2798 { 2799 struct ieee80211com *ic = ni->ni_ic; 2800 uint32_t plcp = 0; 2801 int ridx; 2802 2803 /* 2804 * If it's an MCS rate, let's set the plcp correctly 2805 * and set the relevant flags based on the node config. 2806 */ 2807 if (rate & IEEE80211_RATE_MCS) { 2808 /* 2809 * Set the initial PLCP value to be between 0->31 for 2810 * MCS 0 -> MCS 31, then set the "I'm an MCS rate!" 2811 * flag. 2812 */ 2813 plcp = IEEE80211_RV(rate) | IWN_RFLAG_MCS; 2814 2815 /* 2816 * Set the channel width and guard interval. 2817 * 2818 * Take into account the local configuration and 2819 * the node/peer advertised abilities. 2820 */ 2821 if (IEEE80211_IS_CHAN_HT40(ni->ni_chan)) { 2822 plcp |= IWN_RFLAG_HT40; 2823 if (ieee80211_ht_check_tx_shortgi_40(ni)) 2824 plcp |= IWN_RFLAG_SGI; 2825 } else if (ieee80211_ht_check_tx_shortgi_20(ni)) 2826 plcp |= IWN_RFLAG_SGI; 2827 2828 /* 2829 * Ensure the selected rate matches the link quality 2830 * table entries being used. 2831 */ 2832 if (rate > 0x8f) 2833 plcp |= IWN_RFLAG_ANT(sc->txchainmask); 2834 else if (rate > 0x87) 2835 plcp |= IWN_RFLAG_ANT(iwn_get_2stream_tx_antmask(sc)); 2836 else 2837 plcp |= IWN_RFLAG_ANT(iwn_get_1stream_tx_antmask(sc)); 2838 } else { 2839 /* 2840 * Set the initial PLCP - fine for both 2841 * OFDM and CCK rates. 2842 */ 2843 plcp = rate2plcp(rate); 2844 2845 /* Set CCK flag if it's CCK */ 2846 2847 /* XXX It would be nice to have a method 2848 * to map the ridx -> phy table entry 2849 * so we could just query that, rather than 2850 * this hack to check against IWN_RIDX_OFDM6. 2851 */ 2852 ridx = ieee80211_legacy_rate_lookup(ic->ic_rt, 2853 rate & IEEE80211_RATE_VAL); 2854 if (ridx < IWN_RIDX_OFDM6 && 2855 IEEE80211_IS_CHAN_2GHZ(ni->ni_chan)) 2856 plcp |= IWN_RFLAG_CCK; 2857 2858 /* Set antenna configuration */ 2859 /* XXX TODO: is this the right antenna to use for legacy? */ 2860 plcp |= IWN_RFLAG_ANT(iwn_get_1stream_tx_antmask(sc)); 2861 } 2862 2863 DPRINTF(sc, IWN_DEBUG_TXRATE, "%s: rate=0x%02x, plcp=0x%08x\n", 2864 __func__, 2865 rate, 2866 plcp); 2867 2868 return (htole32(plcp)); 2869 } 2870 2871 static void 2872 iwn_newassoc(struct ieee80211_node *ni, int isnew) 2873 { 2874 /* Doesn't do anything at the moment */ 2875 } 2876 2877 static int 2878 iwn_newstate(struct ieee80211vap *vap, enum ieee80211_state nstate, int arg) 2879 { 2880 struct iwn_vap *ivp = IWN_VAP(vap); 2881 struct ieee80211com *ic = vap->iv_ic; 2882 struct iwn_softc *sc = ic->ic_softc; 2883 int error = 0; 2884 2885 DPRINTF(sc, IWN_DEBUG_TRACE, "->%s begin\n", __func__); 2886 2887 DPRINTF(sc, IWN_DEBUG_STATE, "%s: %s -> %s\n", __func__, 2888 ieee80211_state_name[vap->iv_state], ieee80211_state_name[nstate]); 2889 2890 IEEE80211_UNLOCK(ic); 2891 IWN_LOCK(sc); 2892 callout_stop(&sc->calib_to); 2893 2894 sc->rxon = &sc->rx_on[IWN_RXON_BSS_CTX]; 2895 2896 switch (nstate) { 2897 case IEEE80211_S_ASSOC: 2898 if (vap->iv_state != IEEE80211_S_RUN) 2899 break; 2900 /* FALLTHROUGH */ 2901 case IEEE80211_S_AUTH: 2902 if (vap->iv_state == IEEE80211_S_AUTH) 2903 break; 2904 2905 /* 2906 * !AUTH -> AUTH transition requires state reset to handle 2907 * reassociations correctly. 2908 */ 2909 sc->rxon->associd = 0; 2910 sc->rxon->filter &= ~htole32(IWN_FILTER_BSS); 2911 sc->calib.state = IWN_CALIB_STATE_INIT; 2912 2913 /* Wait until we hear a beacon before we transmit */ 2914 if (IEEE80211_IS_CHAN_PASSIVE(ic->ic_curchan)) 2915 sc->sc_beacon_wait = 1; 2916 2917 if ((error = iwn_auth(sc, vap)) != 0) { 2918 device_printf(sc->sc_dev, 2919 "%s: could not move to auth state\n", __func__); 2920 } 2921 break; 2922 2923 case IEEE80211_S_RUN: 2924 /* 2925 * RUN -> RUN transition; Just restart the timers. 2926 */ 2927 if (vap->iv_state == IEEE80211_S_RUN) { 2928 sc->calib_cnt = 0; 2929 break; 2930 } 2931 2932 /* Wait until we hear a beacon before we transmit */ 2933 if (IEEE80211_IS_CHAN_PASSIVE(ic->ic_curchan)) 2934 sc->sc_beacon_wait = 1; 2935 2936 /* 2937 * !RUN -> RUN requires setting the association id 2938 * which is done with a firmware cmd. We also defer 2939 * starting the timers until that work is done. 2940 */ 2941 if ((error = iwn_run(sc, vap)) != 0) { 2942 device_printf(sc->sc_dev, 2943 "%s: could not move to run state\n", __func__); 2944 } 2945 break; 2946 2947 case IEEE80211_S_INIT: 2948 sc->calib.state = IWN_CALIB_STATE_INIT; 2949 /* 2950 * Purge the xmit queue so we don't have old frames 2951 * during a new association attempt. 2952 */ 2953 sc->sc_beacon_wait = 0; 2954 iwn_xmit_queue_drain(sc); 2955 break; 2956 2957 default: 2958 break; 2959 } 2960 IWN_UNLOCK(sc); 2961 IEEE80211_LOCK(ic); 2962 if (error != 0){ 2963 DPRINTF(sc, IWN_DEBUG_TRACE, "->%s end in error\n", __func__); 2964 return error; 2965 } 2966 2967 DPRINTF(sc, IWN_DEBUG_TRACE, "->%s: end\n",__func__); 2968 2969 return ivp->iv_newstate(vap, nstate, arg); 2970 } 2971 2972 static void 2973 iwn_calib_timeout(void *arg) 2974 { 2975 struct iwn_softc *sc = arg; 2976 2977 IWN_LOCK_ASSERT(sc); 2978 2979 /* Force automatic TX power calibration every 60 secs. */ 2980 if (++sc->calib_cnt >= 120) { 2981 uint32_t flags = 0; 2982 2983 DPRINTF(sc, IWN_DEBUG_CALIBRATE, "%s\n", 2984 "sending request for statistics"); 2985 (void)iwn_cmd(sc, IWN_CMD_GET_STATISTICS, &flags, 2986 sizeof flags, 1); 2987 sc->calib_cnt = 0; 2988 } 2989 callout_reset(&sc->calib_to, msecs_to_ticks(500), iwn_calib_timeout, 2990 sc); 2991 } 2992 2993 /* 2994 * Process an RX_PHY firmware notification. This is usually immediately 2995 * followed by an MPDU_RX_DONE notification. 2996 */ 2997 static void 2998 iwn_rx_phy(struct iwn_softc *sc, struct iwn_rx_desc *desc) 2999 { 3000 struct iwn_rx_stat *stat = (struct iwn_rx_stat *)(desc + 1); 3001 3002 DPRINTF(sc, IWN_DEBUG_CALIBRATE, "%s: received PHY stats\n", __func__); 3003 3004 /* Save RX statistics, they will be used on MPDU_RX_DONE. */ 3005 memcpy(&sc->last_rx_stat, stat, sizeof (*stat)); 3006 sc->last_rx_valid = 1; 3007 } 3008 3009 /* 3010 * Process an RX_DONE (4965AGN only) or MPDU_RX_DONE firmware notification. 3011 * Each MPDU_RX_DONE notification must be preceded by an RX_PHY one. 3012 */ 3013 static void 3014 iwn_rx_done(struct iwn_softc *sc, struct iwn_rx_desc *desc, 3015 struct iwn_rx_data *data) 3016 { 3017 struct iwn_ops *ops = &sc->ops; 3018 struct ieee80211com *ic = &sc->sc_ic; 3019 struct iwn_rx_ring *ring = &sc->rxq; 3020 struct ieee80211_frame_min *wh; 3021 struct ieee80211_node *ni; 3022 struct mbuf *m, *m1; 3023 struct iwn_rx_stat *stat; 3024 caddr_t head; 3025 bus_addr_t paddr; 3026 uint32_t flags; 3027 int error, len, rssi, nf; 3028 3029 DPRINTF(sc, IWN_DEBUG_TRACE, "->%s begin\n", __func__); 3030 3031 if (desc->type == IWN_MPDU_RX_DONE) { 3032 /* Check for prior RX_PHY notification. */ 3033 if (!sc->last_rx_valid) { 3034 DPRINTF(sc, IWN_DEBUG_ANY, 3035 "%s: missing RX_PHY\n", __func__); 3036 return; 3037 } 3038 stat = &sc->last_rx_stat; 3039 } else 3040 stat = (struct iwn_rx_stat *)(desc + 1); 3041 3042 if (stat->cfg_phy_len > IWN_STAT_MAXLEN) { 3043 device_printf(sc->sc_dev, 3044 "%s: invalid RX statistic header, len %d\n", __func__, 3045 stat->cfg_phy_len); 3046 return; 3047 } 3048 if (desc->type == IWN_MPDU_RX_DONE) { 3049 struct iwn_rx_mpdu *mpdu = (struct iwn_rx_mpdu *)(desc + 1); 3050 head = (caddr_t)(mpdu + 1); 3051 len = le16toh(mpdu->len); 3052 } else { 3053 head = (caddr_t)(stat + 1) + stat->cfg_phy_len; 3054 len = le16toh(stat->len); 3055 } 3056 3057 flags = le32toh(*(uint32_t *)(head + len)); 3058 3059 /* Discard frames with a bad FCS early. */ 3060 if ((flags & IWN_RX_NOERROR) != IWN_RX_NOERROR) { 3061 DPRINTF(sc, IWN_DEBUG_RECV, "%s: RX flags error %x\n", 3062 __func__, flags); 3063 counter_u64_add(ic->ic_ierrors, 1); 3064 return; 3065 } 3066 /* Discard frames that are too short. */ 3067 if (len < sizeof (struct ieee80211_frame_ack)) { 3068 DPRINTF(sc, IWN_DEBUG_RECV, "%s: frame too short: %d\n", 3069 __func__, len); 3070 counter_u64_add(ic->ic_ierrors, 1); 3071 return; 3072 } 3073 3074 m1 = m_getjcl(M_NOWAIT, MT_DATA, M_PKTHDR, IWN_RBUF_SIZE); 3075 if (m1 == NULL) { 3076 DPRINTF(sc, IWN_DEBUG_ANY, "%s: no mbuf to restock ring\n", 3077 __func__); 3078 counter_u64_add(ic->ic_ierrors, 1); 3079 return; 3080 } 3081 bus_dmamap_unload(ring->data_dmat, data->map); 3082 3083 error = bus_dmamap_load(ring->data_dmat, data->map, mtod(m1, void *), 3084 IWN_RBUF_SIZE, iwn_dma_map_addr, &paddr, BUS_DMA_NOWAIT); 3085 if (error != 0 && error != EFBIG) { 3086 device_printf(sc->sc_dev, 3087 "%s: bus_dmamap_load failed, error %d\n", __func__, error); 3088 m_freem(m1); 3089 3090 /* Try to reload the old mbuf. */ 3091 error = bus_dmamap_load(ring->data_dmat, data->map, 3092 mtod(data->m, void *), IWN_RBUF_SIZE, iwn_dma_map_addr, 3093 &paddr, BUS_DMA_NOWAIT); 3094 if (error != 0 && error != EFBIG) { 3095 panic("%s: could not load old RX mbuf", __func__); 3096 } 3097 bus_dmamap_sync(ring->data_dmat, data->map, 3098 BUS_DMASYNC_PREREAD); 3099 /* Physical address may have changed. */ 3100 ring->desc[ring->cur] = htole32(paddr >> 8); 3101 bus_dmamap_sync(ring->desc_dma.tag, ring->desc_dma.map, 3102 BUS_DMASYNC_PREWRITE); 3103 counter_u64_add(ic->ic_ierrors, 1); 3104 return; 3105 } 3106 3107 bus_dmamap_sync(ring->data_dmat, data->map, 3108 BUS_DMASYNC_PREREAD); 3109 3110 m = data->m; 3111 data->m = m1; 3112 /* Update RX descriptor. */ 3113 ring->desc[ring->cur] = htole32(paddr >> 8); 3114 bus_dmamap_sync(ring->desc_dma.tag, ring->desc_dma.map, 3115 BUS_DMASYNC_PREWRITE); 3116 3117 /* Finalize mbuf. */ 3118 m->m_data = head; 3119 m->m_pkthdr.len = m->m_len = len; 3120 3121 /* Grab a reference to the source node. */ 3122 wh = mtod(m, struct ieee80211_frame_min *); 3123 if (len >= sizeof(struct ieee80211_frame_min)) 3124 ni = ieee80211_find_rxnode(ic, wh); 3125 else 3126 ni = NULL; 3127 nf = (ni != NULL && ni->ni_vap->iv_state == IEEE80211_S_RUN && 3128 (ic->ic_flags & IEEE80211_F_SCAN) == 0) ? sc->noise : -95; 3129 3130 rssi = ops->get_rssi(sc, stat); 3131 3132 if (ieee80211_radiotap_active(ic)) { 3133 struct iwn_rx_radiotap_header *tap = &sc->sc_rxtap; 3134 uint32_t rate = le32toh(stat->rate); 3135 3136 tap->wr_flags = 0; 3137 if (stat->flags & htole16(IWN_STAT_FLAG_SHPREAMBLE)) 3138 tap->wr_flags |= IEEE80211_RADIOTAP_F_SHORTPRE; 3139 tap->wr_dbm_antsignal = (int8_t)rssi; 3140 tap->wr_dbm_antnoise = (int8_t)nf; 3141 tap->wr_tsft = stat->tstamp; 3142 if (rate & IWN_RFLAG_MCS) { 3143 tap->wr_rate = rate & IWN_RFLAG_RATE_MCS; 3144 tap->wr_rate |= IEEE80211_RATE_MCS; 3145 } else 3146 tap->wr_rate = plcp2rate(rate & IWN_RFLAG_RATE); 3147 } 3148 3149 /* 3150 * If it's a beacon and we're waiting, then do the 3151 * wakeup. This should unblock raw_xmit/start. 3152 */ 3153 if (sc->sc_beacon_wait) { 3154 uint8_t type, subtype; 3155 /* NB: Re-assign wh */ 3156 wh = mtod(m, struct ieee80211_frame_min *); 3157 type = wh->i_fc[0] & IEEE80211_FC0_TYPE_MASK; 3158 subtype = wh->i_fc[0] & IEEE80211_FC0_SUBTYPE_MASK; 3159 /* 3160 * This assumes at this point we've received our own 3161 * beacon. 3162 */ 3163 DPRINTF(sc, IWN_DEBUG_TRACE, 3164 "%s: beacon_wait, type=%d, subtype=%d\n", 3165 __func__, type, subtype); 3166 if (type == IEEE80211_FC0_TYPE_MGT && 3167 subtype == IEEE80211_FC0_SUBTYPE_BEACON) { 3168 DPRINTF(sc, IWN_DEBUG_TRACE | IWN_DEBUG_XMIT, 3169 "%s: waking things up\n", __func__); 3170 /* queue taskqueue to transmit! */ 3171 taskqueue_enqueue(sc->sc_tq, &sc->sc_xmit_task); 3172 } 3173 } 3174 3175 IWN_UNLOCK(sc); 3176 3177 /* Send the frame to the 802.11 layer. */ 3178 if (ni != NULL) { 3179 if (ni->ni_flags & IEEE80211_NODE_HT) 3180 m->m_flags |= M_AMPDU; 3181 (void)ieee80211_input(ni, m, rssi - nf, nf); 3182 /* Node is no longer needed. */ 3183 ieee80211_free_node(ni); 3184 } else 3185 (void)ieee80211_input_all(ic, m, rssi - nf, nf); 3186 3187 IWN_LOCK(sc); 3188 3189 DPRINTF(sc, IWN_DEBUG_TRACE, "->%s: end\n",__func__); 3190 3191 } 3192 3193 static void 3194 iwn_agg_tx_complete(struct iwn_softc *sc, struct iwn_tx_ring *ring, int tid, 3195 int idx, int success) 3196 { 3197 struct ieee80211_ratectl_tx_status *txs = &sc->sc_txs; 3198 struct iwn_tx_data *data = &ring->data[idx]; 3199 struct iwn_node *wn; 3200 struct mbuf *m; 3201 struct ieee80211_node *ni; 3202 3203 KASSERT(data->ni != NULL, ("idx %d: no node", idx)); 3204 KASSERT(data->m != NULL, ("idx %d: no mbuf", idx)); 3205 3206 /* Unmap and free mbuf. */ 3207 bus_dmamap_sync(ring->data_dmat, data->map, 3208 BUS_DMASYNC_POSTWRITE); 3209 bus_dmamap_unload(ring->data_dmat, data->map); 3210 m = data->m, data->m = NULL; 3211 ni = data->ni, data->ni = NULL; 3212 wn = (void *)ni; 3213 3214 #if 0 3215 /* XXX causes significant performance degradation. */ 3216 txs->flags = IEEE80211_RATECTL_STATUS_SHORT_RETRY | 3217 IEEE80211_RATECTL_STATUS_LONG_RETRY; 3218 txs->long_retries = data->long_retries - 1; 3219 #else 3220 txs->flags = IEEE80211_RATECTL_STATUS_SHORT_RETRY; 3221 #endif 3222 txs->short_retries = wn->agg[tid].short_retries; 3223 if (success) 3224 txs->status = IEEE80211_RATECTL_TX_SUCCESS; 3225 else 3226 txs->status = IEEE80211_RATECTL_TX_FAIL_UNSPECIFIED; 3227 3228 wn->agg[tid].short_retries = 0; 3229 data->long_retries = 0; 3230 3231 DPRINTF(sc, IWN_DEBUG_AMPDU, "%s: freeing m %p ni %p idx %d qid %d\n", 3232 __func__, m, ni, idx, ring->qid); 3233 ieee80211_ratectl_tx_complete(ni, txs); 3234 ieee80211_tx_complete(ni, m, !success); 3235 } 3236 3237 /* Process an incoming Compressed BlockAck. */ 3238 static void 3239 iwn_rx_compressed_ba(struct iwn_softc *sc, struct iwn_rx_desc *desc) 3240 { 3241 struct iwn_tx_ring *ring; 3242 struct iwn_tx_data *data; 3243 struct iwn_node *wn; 3244 struct iwn_compressed_ba *ba = (struct iwn_compressed_ba *)(desc + 1); 3245 struct ieee80211_tx_ampdu *tap; 3246 uint64_t bitmap; 3247 uint8_t tid; 3248 int i, qid, shift; 3249 int tx_ok = 0; 3250 3251 DPRINTF(sc, IWN_DEBUG_TRACE, "->%s begin\n", __func__); 3252 3253 qid = le16toh(ba->qid); 3254 tap = sc->qid2tap[qid]; 3255 ring = &sc->txq[qid]; 3256 tid = tap->txa_tid; 3257 wn = (void *)tap->txa_ni; 3258 3259 DPRINTF(sc, IWN_DEBUG_AMPDU, "%s: qid %d tid %d seq %04X ssn %04X\n" 3260 "bitmap: ba %016jX wn %016jX, start %d\n", 3261 __func__, qid, tid, le16toh(ba->seq), le16toh(ba->ssn), 3262 (uintmax_t)le64toh(ba->bitmap), (uintmax_t)wn->agg[tid].bitmap, 3263 wn->agg[tid].startidx); 3264 3265 if (wn->agg[tid].bitmap == 0) 3266 return; 3267 3268 shift = wn->agg[tid].startidx - ((le16toh(ba->seq) >> 4) & 0xff); 3269 if (shift <= -64) 3270 shift += 0x100; 3271 3272 /* 3273 * Walk the bitmap and calculate how many successful attempts 3274 * are made. 3275 * 3276 * Yes, the rate control code doesn't know these are A-MPDU 3277 * subframes; due to that long_retries stats are not used here. 3278 */ 3279 bitmap = le64toh(ba->bitmap); 3280 if (shift >= 0) 3281 bitmap >>= shift; 3282 else 3283 bitmap <<= -shift; 3284 bitmap &= wn->agg[tid].bitmap; 3285 wn->agg[tid].bitmap = 0; 3286 3287 for (i = wn->agg[tid].startidx; 3288 bitmap; 3289 bitmap >>= 1, i = (i + 1) % IWN_TX_RING_COUNT) { 3290 if ((bitmap & 1) == 0) 3291 continue; 3292 3293 data = &ring->data[i]; 3294 if (__predict_false(data->m == NULL)) { 3295 /* 3296 * There is no frame; skip this entry. 3297 * 3298 * NB: it is "ok" to have both 3299 * 'tx done' + 'compressed BA' replies for frame 3300 * with STATE_SCD_QUERY status. 3301 */ 3302 DPRINTF(sc, IWN_DEBUG_AMPDU, 3303 "%s: ring %d: no entry %d\n", __func__, qid, i); 3304 continue; 3305 } 3306 3307 tx_ok++; 3308 iwn_agg_tx_complete(sc, ring, tid, i, 1); 3309 } 3310 3311 ring->queued -= tx_ok; 3312 iwn_check_tx_ring(sc, qid); 3313 3314 DPRINTF(sc, IWN_DEBUG_TRACE | IWN_DEBUG_AMPDU, 3315 "->%s: end; %d ok\n",__func__, tx_ok); 3316 } 3317 3318 /* 3319 * Process a CALIBRATION_RESULT notification sent by the initialization 3320 * firmware on response to a CMD_CALIB_CONFIG command (5000 only). 3321 */ 3322 static void 3323 iwn5000_rx_calib_results(struct iwn_softc *sc, struct iwn_rx_desc *desc) 3324 { 3325 struct iwn_phy_calib *calib = (struct iwn_phy_calib *)(desc + 1); 3326 int len, idx = -1; 3327 3328 DPRINTF(sc, IWN_DEBUG_TRACE, "->%s begin\n", __func__); 3329 3330 /* Runtime firmware should not send such a notification. */ 3331 if (sc->sc_flags & IWN_FLAG_CALIB_DONE){ 3332 DPRINTF(sc, IWN_DEBUG_TRACE, 3333 "->%s received after calib done\n", __func__); 3334 return; 3335 } 3336 len = (le32toh(desc->len) & 0x3fff) - 4; 3337 3338 switch (calib->code) { 3339 case IWN5000_PHY_CALIB_DC: 3340 if (sc->base_params->calib_need & IWN_FLG_NEED_PHY_CALIB_DC) 3341 idx = 0; 3342 break; 3343 case IWN5000_PHY_CALIB_LO: 3344 if (sc->base_params->calib_need & IWN_FLG_NEED_PHY_CALIB_LO) 3345 idx = 1; 3346 break; 3347 case IWN5000_PHY_CALIB_TX_IQ: 3348 if (sc->base_params->calib_need & IWN_FLG_NEED_PHY_CALIB_TX_IQ) 3349 idx = 2; 3350 break; 3351 case IWN5000_PHY_CALIB_TX_IQ_PERIODIC: 3352 if (sc->base_params->calib_need & IWN_FLG_NEED_PHY_CALIB_TX_IQ_PERIODIC) 3353 idx = 3; 3354 break; 3355 case IWN5000_PHY_CALIB_BASE_BAND: 3356 if (sc->base_params->calib_need & IWN_FLG_NEED_PHY_CALIB_BASE_BAND) 3357 idx = 4; 3358 break; 3359 } 3360 if (idx == -1) /* Ignore other results. */ 3361 return; 3362 3363 /* Save calibration result. */ 3364 if (sc->calibcmd[idx].buf != NULL) 3365 free(sc->calibcmd[idx].buf, M_DEVBUF); 3366 sc->calibcmd[idx].buf = malloc(len, M_DEVBUF, M_NOWAIT); 3367 if (sc->calibcmd[idx].buf == NULL) { 3368 DPRINTF(sc, IWN_DEBUG_CALIBRATE, 3369 "not enough memory for calibration result %d\n", 3370 calib->code); 3371 return; 3372 } 3373 DPRINTF(sc, IWN_DEBUG_CALIBRATE, 3374 "saving calibration result idx=%d, code=%d len=%d\n", idx, calib->code, len); 3375 sc->calibcmd[idx].len = len; 3376 memcpy(sc->calibcmd[idx].buf, calib, len); 3377 } 3378 3379 static void 3380 iwn_stats_update(struct iwn_softc *sc, struct iwn_calib_state *calib, 3381 struct iwn_stats *stats, int len) 3382 { 3383 struct iwn_stats_bt *stats_bt; 3384 struct iwn_stats *lstats; 3385 3386 /* 3387 * First - check whether the length is the bluetooth or normal. 3388 * 3389 * If it's normal - just copy it and bump out. 3390 * Otherwise we have to convert things. 3391 */ 3392 3393 if (len == sizeof(struct iwn_stats) + 4) { 3394 memcpy(&sc->last_stat, stats, sizeof(struct iwn_stats)); 3395 sc->last_stat_valid = 1; 3396 return; 3397 } 3398 3399 /* 3400 * If it's not the bluetooth size - log, then just copy. 3401 */ 3402 if (len != sizeof(struct iwn_stats_bt) + 4) { 3403 DPRINTF(sc, IWN_DEBUG_STATS, 3404 "%s: size of rx statistics (%d) not an expected size!\n", 3405 __func__, 3406 len); 3407 memcpy(&sc->last_stat, stats, sizeof(struct iwn_stats)); 3408 sc->last_stat_valid = 1; 3409 return; 3410 } 3411 3412 /* 3413 * Ok. Time to copy. 3414 */ 3415 stats_bt = (struct iwn_stats_bt *) stats; 3416 lstats = &sc->last_stat; 3417 3418 /* flags */ 3419 lstats->flags = stats_bt->flags; 3420 /* rx_bt */ 3421 memcpy(&lstats->rx.ofdm, &stats_bt->rx_bt.ofdm, 3422 sizeof(struct iwn_rx_phy_stats)); 3423 memcpy(&lstats->rx.cck, &stats_bt->rx_bt.cck, 3424 sizeof(struct iwn_rx_phy_stats)); 3425 memcpy(&lstats->rx.general, &stats_bt->rx_bt.general_bt.common, 3426 sizeof(struct iwn_rx_general_stats)); 3427 memcpy(&lstats->rx.ht, &stats_bt->rx_bt.ht, 3428 sizeof(struct iwn_rx_ht_phy_stats)); 3429 /* tx */ 3430 memcpy(&lstats->tx, &stats_bt->tx, 3431 sizeof(struct iwn_tx_stats)); 3432 /* general */ 3433 memcpy(&lstats->general, &stats_bt->general, 3434 sizeof(struct iwn_general_stats)); 3435 3436 /* XXX TODO: Squirrel away the extra bluetooth stats somewhere */ 3437 sc->last_stat_valid = 1; 3438 } 3439 3440 /* 3441 * Process an RX_STATISTICS or BEACON_STATISTICS firmware notification. 3442 * The latter is sent by the firmware after each received beacon. 3443 */ 3444 static void 3445 iwn_rx_statistics(struct iwn_softc *sc, struct iwn_rx_desc *desc) 3446 { 3447 struct iwn_ops *ops = &sc->ops; 3448 struct ieee80211com *ic = &sc->sc_ic; 3449 struct ieee80211vap *vap = TAILQ_FIRST(&ic->ic_vaps); 3450 struct iwn_calib_state *calib = &sc->calib; 3451 struct iwn_stats *stats = (struct iwn_stats *)(desc + 1); 3452 struct iwn_stats *lstats; 3453 int temp; 3454 3455 DPRINTF(sc, IWN_DEBUG_TRACE, "->%s begin\n", __func__); 3456 3457 /* Ignore statistics received during a scan. */ 3458 if (vap->iv_state != IEEE80211_S_RUN || 3459 (ic->ic_flags & IEEE80211_F_SCAN)){ 3460 DPRINTF(sc, IWN_DEBUG_TRACE, "->%s received during calib\n", 3461 __func__); 3462 return; 3463 } 3464 3465 DPRINTF(sc, IWN_DEBUG_CALIBRATE | IWN_DEBUG_STATS, 3466 "%s: received statistics, cmd %d, len %d\n", 3467 __func__, desc->type, le16toh(desc->len)); 3468 sc->calib_cnt = 0; /* Reset TX power calibration timeout. */ 3469 3470 /* 3471 * Collect/track general statistics for reporting. 3472 * 3473 * This takes care of ensuring that the bluetooth sized message 3474 * will be correctly converted to the legacy sized message. 3475 */ 3476 iwn_stats_update(sc, calib, stats, le16toh(desc->len)); 3477 3478 /* 3479 * And now, let's take a reference of it to use! 3480 */ 3481 lstats = &sc->last_stat; 3482 3483 /* Test if temperature has changed. */ 3484 if (lstats->general.temp != sc->rawtemp) { 3485 /* Convert "raw" temperature to degC. */ 3486 sc->rawtemp = stats->general.temp; 3487 temp = ops->get_temperature(sc); 3488 DPRINTF(sc, IWN_DEBUG_CALIBRATE, "%s: temperature %d\n", 3489 __func__, temp); 3490 3491 /* Update TX power if need be (4965AGN only). */ 3492 if (sc->hw_type == IWN_HW_REV_TYPE_4965) 3493 iwn4965_power_calibration(sc, temp); 3494 } 3495 3496 if (desc->type != IWN_BEACON_STATISTICS) 3497 return; /* Reply to a statistics request. */ 3498 3499 sc->noise = iwn_get_noise(&lstats->rx.general); 3500 DPRINTF(sc, IWN_DEBUG_CALIBRATE, "%s: noise %d\n", __func__, sc->noise); 3501 3502 /* Test that RSSI and noise are present in stats report. */ 3503 if (le32toh(lstats->rx.general.flags) != 1) { 3504 DPRINTF(sc, IWN_DEBUG_ANY, "%s\n", 3505 "received statistics without RSSI"); 3506 return; 3507 } 3508 3509 if (calib->state == IWN_CALIB_STATE_ASSOC) 3510 iwn_collect_noise(sc, &lstats->rx.general); 3511 else if (calib->state == IWN_CALIB_STATE_RUN) { 3512 iwn_tune_sensitivity(sc, &lstats->rx); 3513 /* 3514 * XXX TODO: Only run the RX recovery if we're associated! 3515 */ 3516 iwn_check_rx_recovery(sc, lstats); 3517 iwn_save_stats_counters(sc, lstats); 3518 } 3519 3520 DPRINTF(sc, IWN_DEBUG_TRACE, "->%s: end\n",__func__); 3521 } 3522 3523 /* 3524 * Save the relevant statistic counters for the next calibration 3525 * pass. 3526 */ 3527 static void 3528 iwn_save_stats_counters(struct iwn_softc *sc, const struct iwn_stats *rs) 3529 { 3530 struct iwn_calib_state *calib = &sc->calib; 3531 3532 /* Save counters values for next call. */ 3533 calib->bad_plcp_cck = le32toh(rs->rx.cck.bad_plcp); 3534 calib->fa_cck = le32toh(rs->rx.cck.fa); 3535 calib->bad_plcp_ht = le32toh(rs->rx.ht.bad_plcp); 3536 calib->bad_plcp_ofdm = le32toh(rs->rx.ofdm.bad_plcp); 3537 calib->fa_ofdm = le32toh(rs->rx.ofdm.fa); 3538 3539 /* Last time we received these tick values */ 3540 sc->last_calib_ticks = ticks; 3541 } 3542 3543 /* 3544 * Process a TX_DONE firmware notification. Unfortunately, the 4965AGN 3545 * and 5000 adapters have different incompatible TX status formats. 3546 */ 3547 static void 3548 iwn4965_tx_done(struct iwn_softc *sc, struct iwn_rx_desc *desc, 3549 struct iwn_rx_data *data) 3550 { 3551 struct iwn4965_tx_stat *stat = (struct iwn4965_tx_stat *)(desc + 1); 3552 int qid = desc->qid & IWN_RX_DESC_QID_MSK; 3553 3554 DPRINTF(sc, IWN_DEBUG_XMIT, "%s: " 3555 "qid %d idx %d RTS retries %d ACK retries %d nkill %d rate %x duration %d status %x\n", 3556 __func__, desc->qid, desc->idx, 3557 stat->rtsfailcnt, 3558 stat->ackfailcnt, 3559 stat->btkillcnt, 3560 stat->rate, le16toh(stat->duration), 3561 le32toh(stat->status)); 3562 3563 if (qid >= sc->firstaggqueue && stat->nframes != 1) { 3564 iwn_ampdu_tx_done(sc, qid, stat->nframes, stat->rtsfailcnt, 3565 &stat->status); 3566 } else { 3567 iwn_tx_done(sc, desc, stat->rtsfailcnt, stat->ackfailcnt, 3568 le32toh(stat->status) & 0xff); 3569 } 3570 } 3571 3572 static void 3573 iwn5000_tx_done(struct iwn_softc *sc, struct iwn_rx_desc *desc, 3574 struct iwn_rx_data *data) 3575 { 3576 struct iwn5000_tx_stat *stat = (struct iwn5000_tx_stat *)(desc + 1); 3577 int qid = desc->qid & IWN_RX_DESC_QID_MSK; 3578 3579 DPRINTF(sc, IWN_DEBUG_XMIT, "%s: " 3580 "qid %d idx %d RTS retries %d ACK retries %d nkill %d rate %x duration %d status %x\n", 3581 __func__, desc->qid, desc->idx, 3582 stat->rtsfailcnt, 3583 stat->ackfailcnt, 3584 stat->btkillcnt, 3585 stat->rate, le16toh(stat->duration), 3586 le32toh(stat->status)); 3587 3588 #ifdef notyet 3589 /* Reset TX scheduler slot. */ 3590 iwn5000_reset_sched(sc, qid, desc->idx); 3591 #endif 3592 3593 if (qid >= sc->firstaggqueue && stat->nframes != 1) { 3594 iwn_ampdu_tx_done(sc, qid, stat->nframes, stat->rtsfailcnt, 3595 &stat->status); 3596 } else { 3597 iwn_tx_done(sc, desc, stat->rtsfailcnt, stat->ackfailcnt, 3598 le16toh(stat->status) & 0xff); 3599 } 3600 } 3601 3602 static void 3603 iwn_adj_ampdu_ptr(struct iwn_softc *sc, struct iwn_tx_ring *ring) 3604 { 3605 int i; 3606 3607 for (i = ring->read; i != ring->cur; i = (i + 1) % IWN_TX_RING_COUNT) { 3608 struct iwn_tx_data *data = &ring->data[i]; 3609 3610 if (data->m != NULL) 3611 break; 3612 3613 data->remapped = 0; 3614 } 3615 3616 ring->read = i; 3617 } 3618 3619 /* 3620 * Adapter-independent backend for TX_DONE firmware notifications. 3621 */ 3622 static void 3623 iwn_tx_done(struct iwn_softc *sc, struct iwn_rx_desc *desc, int rtsfailcnt, 3624 int ackfailcnt, uint8_t status) 3625 { 3626 struct ieee80211_ratectl_tx_status *txs = &sc->sc_txs; 3627 struct iwn_tx_ring *ring = &sc->txq[desc->qid & IWN_RX_DESC_QID_MSK]; 3628 struct iwn_tx_data *data = &ring->data[desc->idx]; 3629 struct mbuf *m; 3630 struct ieee80211_node *ni; 3631 3632 if (__predict_false(data->m == NULL && 3633 ring->qid >= sc->firstaggqueue)) { 3634 /* 3635 * There is no frame; skip this entry. 3636 */ 3637 DPRINTF(sc, IWN_DEBUG_AMPDU, "%s: ring %d: no entry %d\n", 3638 __func__, ring->qid, desc->idx); 3639 return; 3640 } 3641 3642 KASSERT(data->ni != NULL, ("no node")); 3643 KASSERT(data->m != NULL, ("no mbuf")); 3644 3645 DPRINTF(sc, IWN_DEBUG_TRACE, "->%s begin\n", __func__); 3646 3647 /* Unmap and free mbuf. */ 3648 bus_dmamap_sync(ring->data_dmat, data->map, BUS_DMASYNC_POSTWRITE); 3649 bus_dmamap_unload(ring->data_dmat, data->map); 3650 m = data->m, data->m = NULL; 3651 ni = data->ni, data->ni = NULL; 3652 3653 data->long_retries = 0; 3654 3655 if (ring->qid >= sc->firstaggqueue) 3656 iwn_adj_ampdu_ptr(sc, ring); 3657 3658 /* 3659 * XXX f/w may hang (device timeout) when desc->idx - ring->read == 64 3660 * (aggregation queues only). 3661 */ 3662 3663 ring->queued--; 3664 iwn_check_tx_ring(sc, ring->qid); 3665 3666 /* 3667 * Update rate control statistics for the node. 3668 */ 3669 txs->flags = IEEE80211_RATECTL_STATUS_SHORT_RETRY | 3670 IEEE80211_RATECTL_STATUS_LONG_RETRY; 3671 txs->short_retries = rtsfailcnt; 3672 txs->long_retries = ackfailcnt; 3673 if (!(status & IWN_TX_FAIL)) 3674 txs->status = IEEE80211_RATECTL_TX_SUCCESS; 3675 else { 3676 switch (status) { 3677 case IWN_TX_FAIL_SHORT_LIMIT: 3678 txs->status = IEEE80211_RATECTL_TX_FAIL_SHORT; 3679 break; 3680 case IWN_TX_FAIL_LONG_LIMIT: 3681 txs->status = IEEE80211_RATECTL_TX_FAIL_LONG; 3682 break; 3683 case IWN_TX_STATUS_FAIL_LIFE_EXPIRE: 3684 txs->status = IEEE80211_RATECTL_TX_FAIL_EXPIRED; 3685 break; 3686 default: 3687 txs->status = IEEE80211_RATECTL_TX_FAIL_UNSPECIFIED; 3688 break; 3689 } 3690 } 3691 ieee80211_ratectl_tx_complete(ni, txs); 3692 3693 /* 3694 * Channels marked for "radar" require traffic to be received 3695 * to unlock before we can transmit. Until traffic is seen 3696 * any attempt to transmit is returned immediately with status 3697 * set to IWN_TX_FAIL_TX_LOCKED. Unfortunately this can easily 3698 * happen on first authenticate after scanning. To workaround 3699 * this we ignore a failure of this sort in AUTH state so the 3700 * 802.11 layer will fall back to using a timeout to wait for 3701 * the AUTH reply. This allows the firmware time to see 3702 * traffic so a subsequent retry of AUTH succeeds. It's 3703 * unclear why the firmware does not maintain state for 3704 * channels recently visited as this would allow immediate 3705 * use of the channel after a scan (where we see traffic). 3706 */ 3707 if (status == IWN_TX_FAIL_TX_LOCKED && 3708 ni->ni_vap->iv_state == IEEE80211_S_AUTH) 3709 ieee80211_tx_complete(ni, m, 0); 3710 else 3711 ieee80211_tx_complete(ni, m, 3712 (status & IWN_TX_FAIL) != 0); 3713 3714 DPRINTF(sc, IWN_DEBUG_TRACE, "->%s: end\n",__func__); 3715 } 3716 3717 /* 3718 * Process a "command done" firmware notification. This is where we wakeup 3719 * processes waiting for a synchronous command completion. 3720 */ 3721 static void 3722 iwn_cmd_done(struct iwn_softc *sc, struct iwn_rx_desc *desc) 3723 { 3724 struct iwn_tx_ring *ring; 3725 struct iwn_tx_data *data; 3726 int cmd_queue_num; 3727 3728 if (sc->sc_flags & IWN_FLAG_PAN_SUPPORT) 3729 cmd_queue_num = IWN_PAN_CMD_QUEUE; 3730 else 3731 cmd_queue_num = IWN_CMD_QUEUE_NUM; 3732 3733 if ((desc->qid & IWN_RX_DESC_QID_MSK) != cmd_queue_num) 3734 return; /* Not a command ack. */ 3735 3736 ring = &sc->txq[cmd_queue_num]; 3737 data = &ring->data[desc->idx]; 3738 3739 /* If the command was mapped in an mbuf, free it. */ 3740 if (data->m != NULL) { 3741 bus_dmamap_sync(ring->data_dmat, data->map, 3742 BUS_DMASYNC_POSTWRITE); 3743 bus_dmamap_unload(ring->data_dmat, data->map); 3744 m_freem(data->m); 3745 data->m = NULL; 3746 } 3747 wakeup(&ring->desc[desc->idx]); 3748 } 3749 3750 static int 3751 iwn_ampdu_check_bitmap(uint64_t bitmap, int start, int idx) 3752 { 3753 int bit, shift; 3754 3755 bit = idx - start; 3756 shift = 0; 3757 if (bit >= 64) { 3758 shift = 0x100 - bit; 3759 bit = 0; 3760 } else if (bit <= -64) 3761 bit = 0x100 + bit; 3762 else if (bit < 0) { 3763 shift = -bit; 3764 bit = 0; 3765 } 3766 3767 if (bit - shift >= 64) 3768 return (0); 3769 3770 return ((bitmap & (1ULL << (bit - shift))) != 0); 3771 } 3772 3773 /* 3774 * Firmware bug workaround: in case if 'retries' counter 3775 * overflows 'seqno' field will be incremented: 3776 * status|sequence|status|sequence|status|sequence 3777 * 0000 0A48 0001 0A49 0000 0A6A 3778 * 1000 0A48 1000 0A49 1000 0A6A 3779 * 2000 0A48 2000 0A49 2000 0A6A 3780 * ... 3781 * E000 0A48 E000 0A49 E000 0A6A 3782 * F000 0A48 F000 0A49 F000 0A6A 3783 * 0000 0A49 0000 0A49 0000 0A6B 3784 * 1000 0A49 1000 0A49 1000 0A6B 3785 * ... 3786 * D000 0A49 D000 0A49 D000 0A6B 3787 * E000 0A49 E001 0A49 E000 0A6B 3788 * F000 0A49 F001 0A49 F000 0A6B 3789 * 0000 0A4A 0000 0A4B 0000 0A6A 3790 * 1000 0A4A 1000 0A4B 1000 0A6A 3791 * ... 3792 * 3793 * Odd 'seqno' numbers are incremened by 2 every 2 overflows. 3794 * For even 'seqno' % 4 != 0 overflow is cyclic (0 -> +1 -> 0). 3795 * Not checked with nretries >= 64. 3796 * 3797 */ 3798 static int 3799 iwn_ampdu_index_check(struct iwn_softc *sc, struct iwn_tx_ring *ring, 3800 uint64_t bitmap, int start, int idx) 3801 { 3802 struct ieee80211com *ic = &sc->sc_ic; 3803 struct iwn_tx_data *data; 3804 int diff, min_retries, max_retries, new_idx, loop_end; 3805 3806 new_idx = idx - IWN_LONG_RETRY_LIMIT_LOG; 3807 if (new_idx < 0) 3808 new_idx += IWN_TX_RING_COUNT; 3809 3810 /* 3811 * Corner case: check if retry count is not too big; 3812 * reset device otherwise. 3813 */ 3814 if (!iwn_ampdu_check_bitmap(bitmap, start, new_idx)) { 3815 data = &ring->data[new_idx]; 3816 if (data->long_retries > IWN_LONG_RETRY_LIMIT) { 3817 device_printf(sc->sc_dev, 3818 "%s: retry count (%d) for idx %d/%d overflow, " 3819 "resetting...\n", __func__, data->long_retries, 3820 ring->qid, new_idx); 3821 ieee80211_restart_all(ic); 3822 return (-1); 3823 } 3824 } 3825 3826 /* Correct index if needed. */ 3827 loop_end = idx; 3828 do { 3829 data = &ring->data[new_idx]; 3830 diff = idx - new_idx; 3831 if (diff < 0) 3832 diff += IWN_TX_RING_COUNT; 3833 3834 min_retries = IWN_LONG_RETRY_FW_OVERFLOW * diff; 3835 if ((new_idx % 2) == 0) 3836 max_retries = IWN_LONG_RETRY_FW_OVERFLOW * (diff + 1); 3837 else 3838 max_retries = IWN_LONG_RETRY_FW_OVERFLOW * (diff + 2); 3839 3840 if (!iwn_ampdu_check_bitmap(bitmap, start, new_idx) && 3841 ((data->long_retries >= min_retries && 3842 data->long_retries < max_retries) || 3843 (diff == 1 && 3844 (new_idx & 0x03) == 0x02 && 3845 data->long_retries >= IWN_LONG_RETRY_FW_OVERFLOW))) { 3846 DPRINTF(sc, IWN_DEBUG_AMPDU, 3847 "%s: correcting index %d -> %d in queue %d" 3848 " (retries %d)\n", __func__, idx, new_idx, 3849 ring->qid, data->long_retries); 3850 return (new_idx); 3851 } 3852 3853 new_idx = (new_idx + 1) % IWN_TX_RING_COUNT; 3854 } while (new_idx != loop_end); 3855 3856 return (idx); 3857 } 3858 3859 static void 3860 iwn_ampdu_tx_done(struct iwn_softc *sc, int qid, int nframes, int rtsfailcnt, 3861 void *stat) 3862 { 3863 struct iwn_tx_ring *ring = &sc->txq[qid]; 3864 struct ieee80211_tx_ampdu *tap = sc->qid2tap[qid]; 3865 struct iwn_node *wn = (void *)tap->txa_ni; 3866 struct iwn_tx_data *data; 3867 uint64_t bitmap = 0; 3868 uint16_t *aggstatus = stat; 3869 uint8_t tid = tap->txa_tid; 3870 int bit, i, idx, shift, start, tx_err; 3871 3872 DPRINTF(sc, IWN_DEBUG_TRACE, "->%s begin\n", __func__); 3873 3874 start = le16toh(*(aggstatus + nframes * 2)) & 0xff; 3875 3876 for (i = 0; i < nframes; i++) { 3877 uint16_t status = le16toh(aggstatus[i * 2]); 3878 3879 if (status & IWN_AGG_TX_STATE_IGNORE_MASK) 3880 continue; 3881 3882 idx = le16toh(aggstatus[i * 2 + 1]) & 0xff; 3883 data = &ring->data[idx]; 3884 if (data->remapped) { 3885 idx = iwn_ampdu_index_check(sc, ring, bitmap, start, idx); 3886 if (idx == -1) { 3887 /* skip error (device will be restarted anyway). */ 3888 continue; 3889 } 3890 3891 /* Index may have changed. */ 3892 data = &ring->data[idx]; 3893 } 3894 3895 /* 3896 * XXX Sometimes (rarely) some frames are excluded from events. 3897 * XXX Due to that long_retries counter may be wrong. 3898 */ 3899 data->long_retries &= ~0x0f; 3900 data->long_retries += IWN_AGG_TX_TRY_COUNT(status) + 1; 3901 3902 if (data->long_retries >= IWN_LONG_RETRY_FW_OVERFLOW) { 3903 int diff, wrong_idx; 3904 3905 diff = data->long_retries / IWN_LONG_RETRY_FW_OVERFLOW; 3906 wrong_idx = (idx + diff) % IWN_TX_RING_COUNT; 3907 3908 /* 3909 * Mark the entry so the above code will check it 3910 * next time. 3911 */ 3912 ring->data[wrong_idx].remapped = 1; 3913 } 3914 3915 if (status & IWN_AGG_TX_STATE_UNDERRUN_MSK) { 3916 /* 3917 * NB: count retries but postpone - it was not 3918 * transmitted. 3919 */ 3920 continue; 3921 } 3922 3923 bit = idx - start; 3924 shift = 0; 3925 if (bit >= 64) { 3926 shift = 0x100 - bit; 3927 bit = 0; 3928 } else if (bit <= -64) 3929 bit = 0x100 + bit; 3930 else if (bit < 0) { 3931 shift = -bit; 3932 bit = 0; 3933 } 3934 bitmap = bitmap << shift; 3935 bitmap |= 1ULL << bit; 3936 } 3937 wn->agg[tid].startidx = start; 3938 wn->agg[tid].bitmap = bitmap; 3939 wn->agg[tid].short_retries = rtsfailcnt; 3940 3941 DPRINTF(sc, IWN_DEBUG_AMPDU, "%s: nframes %d start %d bitmap %016jX\n", 3942 __func__, nframes, start, (uintmax_t)bitmap); 3943 3944 i = ring->read; 3945 3946 for (tx_err = 0; 3947 i != wn->agg[tid].startidx; 3948 i = (i + 1) % IWN_TX_RING_COUNT) { 3949 data = &ring->data[i]; 3950 data->remapped = 0; 3951 if (data->m == NULL) 3952 continue; 3953 3954 tx_err++; 3955 iwn_agg_tx_complete(sc, ring, tid, i, 0); 3956 } 3957 3958 ring->read = wn->agg[tid].startidx; 3959 ring->queued -= tx_err; 3960 3961 iwn_check_tx_ring(sc, qid); 3962 3963 DPRINTF(sc, IWN_DEBUG_TRACE, "->%s: end\n",__func__); 3964 } 3965 3966 /* 3967 * Process an INT_FH_RX or INT_SW_RX interrupt. 3968 */ 3969 static void 3970 iwn_notif_intr(struct iwn_softc *sc) 3971 { 3972 struct iwn_ops *ops = &sc->ops; 3973 struct ieee80211com *ic = &sc->sc_ic; 3974 struct ieee80211vap *vap = TAILQ_FIRST(&ic->ic_vaps); 3975 uint16_t hw; 3976 int is_stopped; 3977 3978 bus_dmamap_sync(sc->rxq.stat_dma.tag, sc->rxq.stat_dma.map, 3979 BUS_DMASYNC_POSTREAD); 3980 3981 hw = le16toh(sc->rxq.stat->closed_count) & 0xfff; 3982 while (sc->rxq.cur != hw) { 3983 struct iwn_rx_data *data = &sc->rxq.data[sc->rxq.cur]; 3984 struct iwn_rx_desc *desc; 3985 3986 bus_dmamap_sync(sc->rxq.data_dmat, data->map, 3987 BUS_DMASYNC_POSTREAD); 3988 desc = mtod(data->m, struct iwn_rx_desc *); 3989 3990 DPRINTF(sc, IWN_DEBUG_RECV, 3991 "%s: cur=%d; qid %x idx %d flags %x type %d(%s) len %d\n", 3992 __func__, sc->rxq.cur, desc->qid & IWN_RX_DESC_QID_MSK, 3993 desc->idx, desc->flags, desc->type, 3994 iwn_intr_str(desc->type), le16toh(desc->len)); 3995 3996 if (!(desc->qid & IWN_UNSOLICITED_RX_NOTIF)) /* Reply to a command. */ 3997 iwn_cmd_done(sc, desc); 3998 3999 switch (desc->type) { 4000 case IWN_RX_PHY: 4001 iwn_rx_phy(sc, desc); 4002 break; 4003 4004 case IWN_RX_DONE: /* 4965AGN only. */ 4005 case IWN_MPDU_RX_DONE: 4006 /* An 802.11 frame has been received. */ 4007 iwn_rx_done(sc, desc, data); 4008 4009 is_stopped = (sc->sc_flags & IWN_FLAG_RUNNING) == 0; 4010 if (__predict_false(is_stopped)) 4011 return; 4012 4013 break; 4014 4015 case IWN_RX_COMPRESSED_BA: 4016 /* A Compressed BlockAck has been received. */ 4017 iwn_rx_compressed_ba(sc, desc); 4018 break; 4019 4020 case IWN_TX_DONE: 4021 /* An 802.11 frame has been transmitted. */ 4022 ops->tx_done(sc, desc, data); 4023 break; 4024 4025 case IWN_RX_STATISTICS: 4026 case IWN_BEACON_STATISTICS: 4027 iwn_rx_statistics(sc, desc); 4028 break; 4029 4030 case IWN_BEACON_MISSED: 4031 { 4032 struct iwn_beacon_missed *miss = 4033 (struct iwn_beacon_missed *)(desc + 1); 4034 int misses; 4035 4036 misses = le32toh(miss->consecutive); 4037 4038 DPRINTF(sc, IWN_DEBUG_STATE, 4039 "%s: beacons missed %d/%d\n", __func__, 4040 misses, le32toh(miss->total)); 4041 /* 4042 * If more than 5 consecutive beacons are missed, 4043 * reinitialize the sensitivity state machine. 4044 */ 4045 if (vap->iv_state == IEEE80211_S_RUN && 4046 (ic->ic_flags & IEEE80211_F_SCAN) == 0) { 4047 if (misses > 5) 4048 (void)iwn_init_sensitivity(sc); 4049 if (misses >= vap->iv_bmissthreshold) { 4050 IWN_UNLOCK(sc); 4051 ieee80211_beacon_miss(ic); 4052 IWN_LOCK(sc); 4053 4054 is_stopped = (sc->sc_flags & 4055 IWN_FLAG_RUNNING) == 0; 4056 if (__predict_false(is_stopped)) 4057 return; 4058 } 4059 } 4060 break; 4061 } 4062 case IWN_UC_READY: 4063 { 4064 struct iwn_ucode_info *uc = 4065 (struct iwn_ucode_info *)(desc + 1); 4066 4067 /* The microcontroller is ready. */ 4068 DPRINTF(sc, IWN_DEBUG_RESET, 4069 "microcode alive notification version=%d.%d " 4070 "subtype=%x alive=%x\n", uc->major, uc->minor, 4071 uc->subtype, le32toh(uc->valid)); 4072 4073 if (le32toh(uc->valid) != 1) { 4074 device_printf(sc->sc_dev, 4075 "microcontroller initialization failed"); 4076 break; 4077 } 4078 if (uc->subtype == IWN_UCODE_INIT) { 4079 /* Save microcontroller report. */ 4080 memcpy(&sc->ucode_info, uc, sizeof (*uc)); 4081 } 4082 /* Save the address of the error log in SRAM. */ 4083 sc->errptr = le32toh(uc->errptr); 4084 break; 4085 } 4086 #ifdef IWN_DEBUG 4087 case IWN_STATE_CHANGED: 4088 { 4089 /* 4090 * State change allows hardware switch change to be 4091 * noted. However, we handle this in iwn_intr as we 4092 * get both the enable/disble intr. 4093 */ 4094 uint32_t *status = (uint32_t *)(desc + 1); 4095 DPRINTF(sc, IWN_DEBUG_INTR | IWN_DEBUG_STATE, 4096 "state changed to %x\n", 4097 le32toh(*status)); 4098 break; 4099 } 4100 case IWN_START_SCAN: 4101 { 4102 struct iwn_start_scan *scan = 4103 (struct iwn_start_scan *)(desc + 1); 4104 DPRINTF(sc, IWN_DEBUG_ANY, 4105 "%s: scanning channel %d status %x\n", 4106 __func__, scan->chan, le32toh(scan->status)); 4107 break; 4108 } 4109 #endif 4110 case IWN_STOP_SCAN: 4111 { 4112 #ifdef IWN_DEBUG 4113 struct iwn_stop_scan *scan = 4114 (struct iwn_stop_scan *)(desc + 1); 4115 DPRINTF(sc, IWN_DEBUG_STATE | IWN_DEBUG_SCAN, 4116 "scan finished nchan=%d status=%d chan=%d\n", 4117 scan->nchan, scan->status, scan->chan); 4118 #endif 4119 sc->sc_is_scanning = 0; 4120 callout_stop(&sc->scan_timeout); 4121 IWN_UNLOCK(sc); 4122 ieee80211_scan_next(vap); 4123 IWN_LOCK(sc); 4124 4125 is_stopped = (sc->sc_flags & IWN_FLAG_RUNNING) == 0; 4126 if (__predict_false(is_stopped)) 4127 return; 4128 4129 break; 4130 } 4131 case IWN5000_CALIBRATION_RESULT: 4132 iwn5000_rx_calib_results(sc, desc); 4133 break; 4134 4135 case IWN5000_CALIBRATION_DONE: 4136 sc->sc_flags |= IWN_FLAG_CALIB_DONE; 4137 wakeup(sc); 4138 break; 4139 } 4140 4141 sc->rxq.cur = (sc->rxq.cur + 1) % IWN_RX_RING_COUNT; 4142 } 4143 4144 /* Tell the firmware what we have processed. */ 4145 hw = (hw == 0) ? IWN_RX_RING_COUNT - 1 : hw - 1; 4146 IWN_WRITE(sc, IWN_FH_RX_WPTR, hw & ~7); 4147 } 4148 4149 /* 4150 * Process an INT_WAKEUP interrupt raised when the microcontroller wakes up 4151 * from power-down sleep mode. 4152 */ 4153 static void 4154 iwn_wakeup_intr(struct iwn_softc *sc) 4155 { 4156 int qid; 4157 4158 DPRINTF(sc, IWN_DEBUG_RESET, "%s: ucode wakeup from power-down sleep\n", 4159 __func__); 4160 4161 /* Wakeup RX and TX rings. */ 4162 IWN_WRITE(sc, IWN_FH_RX_WPTR, sc->rxq.cur & ~7); 4163 for (qid = 0; qid < sc->ntxqs; qid++) { 4164 struct iwn_tx_ring *ring = &sc->txq[qid]; 4165 IWN_WRITE(sc, IWN_HBUS_TARG_WRPTR, qid << 8 | ring->cur); 4166 } 4167 } 4168 4169 static void 4170 iwn_rftoggle_task(void *arg, int npending) 4171 { 4172 struct iwn_softc *sc = arg; 4173 struct ieee80211com *ic = &sc->sc_ic; 4174 uint32_t tmp; 4175 4176 IWN_LOCK(sc); 4177 tmp = IWN_READ(sc, IWN_GP_CNTRL); 4178 IWN_UNLOCK(sc); 4179 4180 device_printf(sc->sc_dev, "RF switch: radio %s\n", 4181 (tmp & IWN_GP_CNTRL_RFKILL) ? "enabled" : "disabled"); 4182 if (!(tmp & IWN_GP_CNTRL_RFKILL)) { 4183 ieee80211_suspend_all(ic); 4184 4185 /* Enable interrupts to get RF toggle notification. */ 4186 IWN_LOCK(sc); 4187 IWN_WRITE(sc, IWN_INT, 0xffffffff); 4188 IWN_WRITE(sc, IWN_INT_MASK, sc->int_mask); 4189 IWN_UNLOCK(sc); 4190 } else 4191 ieee80211_resume_all(ic); 4192 } 4193 4194 /* 4195 * Dump the error log of the firmware when a firmware panic occurs. Although 4196 * we can't debug the firmware because it is neither open source nor free, it 4197 * can help us to identify certain classes of problems. 4198 */ 4199 static void 4200 iwn_fatal_intr(struct iwn_softc *sc) 4201 { 4202 struct iwn_fw_dump dump; 4203 int i; 4204 4205 IWN_LOCK_ASSERT(sc); 4206 4207 /* Force a complete recalibration on next init. */ 4208 sc->sc_flags &= ~IWN_FLAG_CALIB_DONE; 4209 4210 /* Check that the error log address is valid. */ 4211 if (sc->errptr < IWN_FW_DATA_BASE || 4212 sc->errptr + sizeof (dump) > 4213 IWN_FW_DATA_BASE + sc->fw_data_maxsz) { 4214 printf("%s: bad firmware error log address 0x%08x\n", __func__, 4215 sc->errptr); 4216 return; 4217 } 4218 if (iwn_nic_lock(sc) != 0) { 4219 printf("%s: could not read firmware error log\n", __func__); 4220 return; 4221 } 4222 /* Read firmware error log from SRAM. */ 4223 iwn_mem_read_region_4(sc, sc->errptr, (uint32_t *)&dump, 4224 sizeof (dump) / sizeof (uint32_t)); 4225 iwn_nic_unlock(sc); 4226 4227 if (dump.valid == 0) { 4228 printf("%s: firmware error log is empty\n", __func__); 4229 return; 4230 } 4231 printf("firmware error log:\n"); 4232 printf(" error type = \"%s\" (0x%08X)\n", 4233 (dump.id < nitems(iwn_fw_errmsg)) ? 4234 iwn_fw_errmsg[dump.id] : "UNKNOWN", 4235 dump.id); 4236 printf(" program counter = 0x%08X\n", dump.pc); 4237 printf(" source line = 0x%08X\n", dump.src_line); 4238 printf(" error data = 0x%08X%08X\n", 4239 dump.error_data[0], dump.error_data[1]); 4240 printf(" branch link = 0x%08X%08X\n", 4241 dump.branch_link[0], dump.branch_link[1]); 4242 printf(" interrupt link = 0x%08X%08X\n", 4243 dump.interrupt_link[0], dump.interrupt_link[1]); 4244 printf(" time = %u\n", dump.time[0]); 4245 4246 /* Dump driver status (TX and RX rings) while we're here. */ 4247 printf("driver status:\n"); 4248 for (i = 0; i < sc->ntxqs; i++) { 4249 struct iwn_tx_ring *ring = &sc->txq[i]; 4250 printf(" tx ring %2d: qid=%-2d cur=%-3d queued=%-3d\n", 4251 i, ring->qid, ring->cur, ring->queued); 4252 } 4253 printf(" rx ring: cur=%d\n", sc->rxq.cur); 4254 } 4255 4256 static void 4257 iwn_intr(void *arg) 4258 { 4259 struct iwn_softc *sc = arg; 4260 uint32_t r1, r2, tmp; 4261 4262 IWN_LOCK(sc); 4263 4264 /* Disable interrupts. */ 4265 IWN_WRITE(sc, IWN_INT_MASK, 0); 4266 4267 /* Read interrupts from ICT (fast) or from registers (slow). */ 4268 if (sc->sc_flags & IWN_FLAG_USE_ICT) { 4269 bus_dmamap_sync(sc->ict_dma.tag, sc->ict_dma.map, 4270 BUS_DMASYNC_POSTREAD); 4271 tmp = 0; 4272 while (sc->ict[sc->ict_cur] != 0) { 4273 tmp |= sc->ict[sc->ict_cur]; 4274 sc->ict[sc->ict_cur] = 0; /* Acknowledge. */ 4275 sc->ict_cur = (sc->ict_cur + 1) % IWN_ICT_COUNT; 4276 } 4277 tmp = le32toh(tmp); 4278 if (tmp == 0xffffffff) /* Shouldn't happen. */ 4279 tmp = 0; 4280 else if (tmp & 0xc0000) /* Workaround a HW bug. */ 4281 tmp |= 0x8000; 4282 r1 = (tmp & 0xff00) << 16 | (tmp & 0xff); 4283 r2 = 0; /* Unused. */ 4284 } else { 4285 r1 = IWN_READ(sc, IWN_INT); 4286 if (r1 == 0xffffffff || (r1 & 0xfffffff0) == 0xa5a5a5a0) { 4287 IWN_UNLOCK(sc); 4288 return; /* Hardware gone! */ 4289 } 4290 r2 = IWN_READ(sc, IWN_FH_INT); 4291 } 4292 4293 DPRINTF(sc, IWN_DEBUG_INTR, "interrupt reg1=0x%08x reg2=0x%08x\n" 4294 , r1, r2); 4295 4296 if (r1 == 0 && r2 == 0) 4297 goto done; /* Interrupt not for us. */ 4298 4299 /* Acknowledge interrupts. */ 4300 IWN_WRITE(sc, IWN_INT, r1); 4301 if (!(sc->sc_flags & IWN_FLAG_USE_ICT)) 4302 IWN_WRITE(sc, IWN_FH_INT, r2); 4303 4304 if (r1 & IWN_INT_RF_TOGGLED) { 4305 taskqueue_enqueue(sc->sc_tq, &sc->sc_rftoggle_task); 4306 goto done; 4307 } 4308 if (r1 & IWN_INT_CT_REACHED) { 4309 device_printf(sc->sc_dev, "%s: critical temperature reached!\n", 4310 __func__); 4311 } 4312 if (r1 & (IWN_INT_SW_ERR | IWN_INT_HW_ERR)) { 4313 device_printf(sc->sc_dev, "%s: fatal firmware error\n", 4314 __func__); 4315 #ifdef IWN_DEBUG 4316 iwn_debug_register(sc); 4317 #endif 4318 /* Dump firmware error log and stop. */ 4319 iwn_fatal_intr(sc); 4320 4321 taskqueue_enqueue(sc->sc_tq, &sc->sc_panic_task); 4322 goto done; 4323 } 4324 if ((r1 & (IWN_INT_FH_RX | IWN_INT_SW_RX | IWN_INT_RX_PERIODIC)) || 4325 (r2 & IWN_FH_INT_RX)) { 4326 if (sc->sc_flags & IWN_FLAG_USE_ICT) { 4327 if (r1 & (IWN_INT_FH_RX | IWN_INT_SW_RX)) 4328 IWN_WRITE(sc, IWN_FH_INT, IWN_FH_INT_RX); 4329 IWN_WRITE_1(sc, IWN_INT_PERIODIC, 4330 IWN_INT_PERIODIC_DIS); 4331 iwn_notif_intr(sc); 4332 if (r1 & (IWN_INT_FH_RX | IWN_INT_SW_RX)) { 4333 IWN_WRITE_1(sc, IWN_INT_PERIODIC, 4334 IWN_INT_PERIODIC_ENA); 4335 } 4336 } else 4337 iwn_notif_intr(sc); 4338 } 4339 4340 if ((r1 & IWN_INT_FH_TX) || (r2 & IWN_FH_INT_TX)) { 4341 if (sc->sc_flags & IWN_FLAG_USE_ICT) 4342 IWN_WRITE(sc, IWN_FH_INT, IWN_FH_INT_TX); 4343 wakeup(sc); /* FH DMA transfer completed. */ 4344 } 4345 4346 if (r1 & IWN_INT_ALIVE) 4347 wakeup(sc); /* Firmware is alive. */ 4348 4349 if (r1 & IWN_INT_WAKEUP) 4350 iwn_wakeup_intr(sc); 4351 4352 done: 4353 /* Re-enable interrupts. */ 4354 if (sc->sc_flags & IWN_FLAG_RUNNING) 4355 IWN_WRITE(sc, IWN_INT_MASK, sc->int_mask); 4356 4357 IWN_UNLOCK(sc); 4358 } 4359 4360 /* 4361 * Update TX scheduler ring when transmitting an 802.11 frame (4965AGN and 4362 * 5000 adapters use a slightly different format). 4363 */ 4364 static void 4365 iwn4965_update_sched(struct iwn_softc *sc, int qid, int idx, uint8_t id, 4366 uint16_t len) 4367 { 4368 uint16_t *w = &sc->sched[qid * IWN4965_SCHED_COUNT + idx]; 4369 4370 DPRINTF(sc, IWN_DEBUG_TRACE, "->Doing %s\n", __func__); 4371 4372 *w = htole16(len + 8); 4373 bus_dmamap_sync(sc->sched_dma.tag, sc->sched_dma.map, 4374 BUS_DMASYNC_PREWRITE); 4375 if (idx < IWN_SCHED_WINSZ) { 4376 *(w + IWN_TX_RING_COUNT) = *w; 4377 bus_dmamap_sync(sc->sched_dma.tag, sc->sched_dma.map, 4378 BUS_DMASYNC_PREWRITE); 4379 } 4380 } 4381 4382 static void 4383 iwn5000_update_sched(struct iwn_softc *sc, int qid, int idx, uint8_t id, 4384 uint16_t len) 4385 { 4386 uint16_t *w = &sc->sched[qid * IWN5000_SCHED_COUNT + idx]; 4387 4388 DPRINTF(sc, IWN_DEBUG_TRACE, "->Doing %s\n", __func__); 4389 4390 *w = htole16(id << 12 | (len + 8)); 4391 bus_dmamap_sync(sc->sched_dma.tag, sc->sched_dma.map, 4392 BUS_DMASYNC_PREWRITE); 4393 if (idx < IWN_SCHED_WINSZ) { 4394 *(w + IWN_TX_RING_COUNT) = *w; 4395 bus_dmamap_sync(sc->sched_dma.tag, sc->sched_dma.map, 4396 BUS_DMASYNC_PREWRITE); 4397 } 4398 } 4399 4400 #ifdef notyet 4401 static void 4402 iwn5000_reset_sched(struct iwn_softc *sc, int qid, int idx) 4403 { 4404 uint16_t *w = &sc->sched[qid * IWN5000_SCHED_COUNT + idx]; 4405 4406 DPRINTF(sc, IWN_DEBUG_TRACE, "->Doing %s\n", __func__); 4407 4408 *w = (*w & htole16(0xf000)) | htole16(1); 4409 bus_dmamap_sync(sc->sched_dma.tag, sc->sched_dma.map, 4410 BUS_DMASYNC_PREWRITE); 4411 if (idx < IWN_SCHED_WINSZ) { 4412 *(w + IWN_TX_RING_COUNT) = *w; 4413 bus_dmamap_sync(sc->sched_dma.tag, sc->sched_dma.map, 4414 BUS_DMASYNC_PREWRITE); 4415 } 4416 } 4417 #endif 4418 4419 /* 4420 * Check whether OFDM 11g protection will be enabled for the given rate. 4421 * 4422 * The original driver code only enabled protection for OFDM rates. 4423 * It didn't check to see whether it was operating in 11a or 11bg mode. 4424 */ 4425 static int 4426 iwn_check_rate_needs_protection(struct iwn_softc *sc, 4427 struct ieee80211vap *vap, uint8_t rate) 4428 { 4429 struct ieee80211com *ic = vap->iv_ic; 4430 4431 /* 4432 * Not in 2GHz mode? Then there's no need to enable OFDM 4433 * 11bg protection. 4434 */ 4435 if (! IEEE80211_IS_CHAN_2GHZ(ic->ic_curchan)) { 4436 return (0); 4437 } 4438 4439 /* 4440 * 11bg protection not enabled? Then don't use it. 4441 */ 4442 if ((vap->iv_flags & IEEE80211_F_USEPROT) == 0) 4443 return (0); 4444 4445 /* 4446 * If it's an 11n rate - no protection. 4447 * We'll do it via a specific 11n check. 4448 */ 4449 if (rate & IEEE80211_RATE_MCS) { 4450 return (0); 4451 } 4452 4453 /* 4454 * Do a rate table lookup. If the PHY is CCK, 4455 * don't do protection. 4456 */ 4457 if (ieee80211_rate2phytype(ic->ic_rt, rate) == IEEE80211_T_CCK) 4458 return (0); 4459 4460 /* 4461 * Yup, enable protection. 4462 */ 4463 return (1); 4464 } 4465 4466 /* 4467 * return a value between 0 and IWN_MAX_TX_RETRIES-1 as an index into 4468 * the link quality table that reflects this particular entry. 4469 */ 4470 static int 4471 iwn_tx_rate_to_linkq_offset(struct iwn_softc *sc, struct ieee80211_node *ni, 4472 uint8_t rate) 4473 { 4474 struct ieee80211_rateset *rs; 4475 int is_11n; 4476 int nr; 4477 int i; 4478 uint8_t cmp_rate; 4479 4480 /* 4481 * Figure out if we're using 11n or not here. 4482 */ 4483 if (ieee80211_ht_check_tx_ht(ni)) 4484 is_11n = 1; 4485 else 4486 is_11n = 0; 4487 4488 /* 4489 * Use the correct rate table. 4490 */ 4491 if (is_11n) { 4492 rs = (struct ieee80211_rateset *) &ni->ni_htrates; 4493 nr = ni->ni_htrates.rs_nrates; 4494 } else { 4495 rs = &ni->ni_rates; 4496 nr = rs->rs_nrates; 4497 } 4498 4499 /* 4500 * Find the relevant link quality entry in the table. 4501 */ 4502 for (i = 0; i < nr && i < IWN_MAX_TX_RETRIES - 1 ; i++) { 4503 /* 4504 * The link quality table index starts at 0 == highest 4505 * rate, so we walk the rate table backwards. 4506 */ 4507 cmp_rate = rs->rs_rates[(nr - 1) - i]; 4508 if (rate & IEEE80211_RATE_MCS) 4509 cmp_rate |= IEEE80211_RATE_MCS; 4510 4511 #if 0 4512 DPRINTF(sc, IWN_DEBUG_XMIT, "%s: idx %d: nr=%d, rate=0x%02x, rateentry=0x%02x\n", 4513 __func__, 4514 i, 4515 nr, 4516 rate, 4517 cmp_rate); 4518 #endif 4519 4520 if (cmp_rate == rate) 4521 return (i); 4522 } 4523 4524 /* Failed? Start at the end */ 4525 return (IWN_MAX_TX_RETRIES - 1); 4526 } 4527 4528 static int 4529 iwn_tx_data(struct iwn_softc *sc, struct mbuf *m, struct ieee80211_node *ni) 4530 { 4531 const struct ieee80211_txparam *tp = ni->ni_txparms; 4532 struct ieee80211vap *vap = ni->ni_vap; 4533 struct ieee80211com *ic = ni->ni_ic; 4534 struct iwn_node *wn = (void *)ni; 4535 struct iwn_tx_ring *ring; 4536 struct iwn_tx_cmd *cmd; 4537 struct iwn_cmd_data *tx; 4538 struct ieee80211_frame *wh; 4539 struct ieee80211_key *k = NULL; 4540 uint32_t flags; 4541 uint16_t qos; 4542 uint8_t tid, type; 4543 int ac, totlen, rate; 4544 4545 DPRINTF(sc, IWN_DEBUG_TRACE, "->%s begin\n", __func__); 4546 4547 IWN_LOCK_ASSERT(sc); 4548 4549 wh = mtod(m, struct ieee80211_frame *); 4550 type = wh->i_fc[0] & IEEE80211_FC0_TYPE_MASK; 4551 4552 /* Select EDCA Access Category and TX ring for this frame. */ 4553 if (IEEE80211_QOS_HAS_SEQ(wh)) { 4554 qos = ((const struct ieee80211_qosframe *)wh)->i_qos[0]; 4555 tid = qos & IEEE80211_QOS_TID; 4556 } else { 4557 qos = 0; 4558 tid = 0; 4559 } 4560 4561 /* Choose a TX rate index. */ 4562 if (type == IEEE80211_FC0_TYPE_MGT || 4563 type == IEEE80211_FC0_TYPE_CTL || 4564 (m->m_flags & M_EAPOL) != 0) 4565 rate = tp->mgmtrate; 4566 else if (IEEE80211_IS_MULTICAST(wh->i_addr1)) 4567 rate = tp->mcastrate; 4568 else if (tp->ucastrate != IEEE80211_FIXED_RATE_NONE) 4569 rate = tp->ucastrate; 4570 else { 4571 /* XXX pass pktlen */ 4572 (void) ieee80211_ratectl_rate(ni, NULL, 0); 4573 rate = ni->ni_txrate; 4574 } 4575 4576 /* 4577 * XXX TODO: Group addressed frames aren't aggregated and must 4578 * go to the normal non-aggregation queue, and have a NONQOS TID 4579 * assigned from net80211. 4580 */ 4581 4582 ac = M_WME_GETAC(m); 4583 if (m->m_flags & M_AMPDU_MPDU) { 4584 struct ieee80211_tx_ampdu *tap = &ni->ni_tx_ampdu[ac]; 4585 4586 if (!IEEE80211_AMPDU_RUNNING(tap)) 4587 return (EINVAL); 4588 4589 ac = *(int *)tap->txa_private; 4590 } 4591 4592 /* Encrypt the frame if need be. */ 4593 if (wh->i_fc[1] & IEEE80211_FC1_PROTECTED) { 4594 /* Retrieve key for TX. */ 4595 k = ieee80211_crypto_encap(ni, m); 4596 if (k == NULL) { 4597 return ENOBUFS; 4598 } 4599 /* 802.11 header may have moved. */ 4600 wh = mtod(m, struct ieee80211_frame *); 4601 } 4602 totlen = m->m_pkthdr.len; 4603 4604 if (ieee80211_radiotap_active_vap(vap)) { 4605 struct iwn_tx_radiotap_header *tap = &sc->sc_txtap; 4606 4607 tap->wt_flags = 0; 4608 tap->wt_rate = rate; 4609 if (k != NULL) 4610 tap->wt_flags |= IEEE80211_RADIOTAP_F_WEP; 4611 4612 ieee80211_radiotap_tx(vap, m); 4613 } 4614 4615 flags = 0; 4616 if (!IEEE80211_IS_MULTICAST(wh->i_addr1)) { 4617 /* Unicast frame, check if an ACK is expected. */ 4618 if (!qos || (qos & IEEE80211_QOS_ACKPOLICY) != 4619 IEEE80211_QOS_ACKPOLICY_NOACK) 4620 flags |= IWN_TX_NEED_ACK; 4621 } 4622 if (IEEE80211_IS_CTL_BAR(wh)) 4623 flags |= IWN_TX_IMM_BA; /* Cannot happen yet. */ 4624 4625 if (wh->i_fc[1] & IEEE80211_FC1_MORE_FRAG) 4626 flags |= IWN_TX_MORE_FRAG; /* Cannot happen yet. */ 4627 4628 /* Check if frame must be protected using RTS/CTS or CTS-to-self. */ 4629 if (!IEEE80211_IS_MULTICAST(wh->i_addr1)) { 4630 /* NB: Group frames are sent using CCK in 802.11b/g. */ 4631 if (totlen + IEEE80211_CRC_LEN > vap->iv_rtsthreshold) { 4632 flags |= IWN_TX_NEED_RTS; 4633 } else if (iwn_check_rate_needs_protection(sc, vap, rate)) { 4634 if (ic->ic_protmode == IEEE80211_PROT_CTSONLY) 4635 flags |= IWN_TX_NEED_CTS; 4636 else if (ic->ic_protmode == IEEE80211_PROT_RTSCTS) 4637 flags |= IWN_TX_NEED_RTS; 4638 } else if ((rate & IEEE80211_RATE_MCS) && 4639 (ic->ic_htprotmode == IEEE80211_PROT_RTSCTS)) { 4640 flags |= IWN_TX_NEED_RTS; 4641 } 4642 4643 /* XXX HT protection? */ 4644 4645 if (flags & (IWN_TX_NEED_RTS | IWN_TX_NEED_CTS)) { 4646 if (sc->hw_type != IWN_HW_REV_TYPE_4965) { 4647 /* 5000 autoselects RTS/CTS or CTS-to-self. */ 4648 flags &= ~(IWN_TX_NEED_RTS | IWN_TX_NEED_CTS); 4649 flags |= IWN_TX_NEED_PROTECTION; 4650 } else 4651 flags |= IWN_TX_FULL_TXOP; 4652 } 4653 } 4654 4655 ring = &sc->txq[ac]; 4656 if (m->m_flags & M_AMPDU_MPDU) { 4657 uint16_t seqno = ni->ni_txseqs[tid]; 4658 4659 if (ring->queued > IWN_TX_RING_COUNT / 2 && 4660 (ring->cur + 1) % IWN_TX_RING_COUNT == ring->read) { 4661 DPRINTF(sc, IWN_DEBUG_AMPDU, "%s: no more space " 4662 "(queued %d) left in %d queue!\n", 4663 __func__, ring->queued, ac); 4664 return (ENOBUFS); 4665 } 4666 4667 /* 4668 * Queue this frame to the hardware ring that we've 4669 * negotiated AMPDU TX on. 4670 * 4671 * Note that the sequence number must match the TX slot 4672 * being used! 4673 */ 4674 if ((seqno % 256) != ring->cur) { 4675 device_printf(sc->sc_dev, 4676 "%s: m=%p: seqno (%d) (%d) != ring index (%d) !\n", 4677 __func__, 4678 m, 4679 seqno, 4680 seqno % 256, 4681 ring->cur); 4682 4683 /* XXX until D9195 will not be committed */ 4684 ni->ni_txseqs[tid] &= ~0xff; 4685 ni->ni_txseqs[tid] += ring->cur; 4686 seqno = ni->ni_txseqs[tid]; 4687 } 4688 4689 *(uint16_t *)wh->i_seq = 4690 htole16(seqno << IEEE80211_SEQ_SEQ_SHIFT); 4691 ni->ni_txseqs[tid]++; 4692 } 4693 4694 /* Prepare TX firmware command. */ 4695 cmd = &ring->cmd[ring->cur]; 4696 tx = (struct iwn_cmd_data *)cmd->data; 4697 4698 /* NB: No need to clear tx, all fields are reinitialized here. */ 4699 tx->scratch = 0; /* clear "scratch" area */ 4700 4701 if (IEEE80211_IS_MULTICAST(wh->i_addr1) || 4702 type != IEEE80211_FC0_TYPE_DATA) 4703 tx->id = sc->broadcast_id; 4704 else 4705 tx->id = wn->id; 4706 4707 if (type == IEEE80211_FC0_TYPE_MGT) { 4708 uint8_t subtype = wh->i_fc[0] & IEEE80211_FC0_SUBTYPE_MASK; 4709 4710 /* Tell HW to set timestamp in probe responses. */ 4711 if (subtype == IEEE80211_FC0_SUBTYPE_PROBE_RESP) 4712 flags |= IWN_TX_INSERT_TSTAMP; 4713 if (subtype == IEEE80211_FC0_SUBTYPE_ASSOC_REQ || 4714 subtype == IEEE80211_FC0_SUBTYPE_REASSOC_REQ) 4715 tx->timeout = htole16(3); 4716 else 4717 tx->timeout = htole16(2); 4718 } else 4719 tx->timeout = htole16(0); 4720 4721 if (tx->id == sc->broadcast_id) { 4722 /* Group or management frame. */ 4723 tx->linkq = 0; 4724 } else { 4725 tx->linkq = iwn_tx_rate_to_linkq_offset(sc, ni, rate); 4726 flags |= IWN_TX_LINKQ; /* enable MRR */ 4727 } 4728 4729 tx->tid = tid; 4730 tx->rts_ntries = 60; 4731 tx->data_ntries = 15; 4732 tx->lifetime = htole32(IWN_LIFETIME_INFINITE); 4733 tx->rate = iwn_rate_to_plcp(sc, ni, rate); 4734 tx->security = 0; 4735 tx->flags = htole32(flags); 4736 4737 return (iwn_tx_cmd(sc, m, ni, ring)); 4738 } 4739 4740 static int 4741 iwn_tx_data_raw(struct iwn_softc *sc, struct mbuf *m, 4742 struct ieee80211_node *ni, const struct ieee80211_bpf_params *params) 4743 { 4744 struct ieee80211vap *vap = ni->ni_vap; 4745 struct iwn_tx_cmd *cmd; 4746 struct iwn_cmd_data *tx; 4747 struct ieee80211_frame *wh; 4748 struct iwn_tx_ring *ring; 4749 uint32_t flags; 4750 int ac, rate; 4751 uint8_t type; 4752 4753 DPRINTF(sc, IWN_DEBUG_TRACE, "->%s begin\n", __func__); 4754 4755 IWN_LOCK_ASSERT(sc); 4756 4757 wh = mtod(m, struct ieee80211_frame *); 4758 type = wh->i_fc[0] & IEEE80211_FC0_TYPE_MASK; 4759 4760 ac = params->ibp_pri & 3; 4761 4762 /* Choose a TX rate. */ 4763 rate = params->ibp_rate0; 4764 4765 flags = 0; 4766 if ((params->ibp_flags & IEEE80211_BPF_NOACK) == 0) 4767 flags |= IWN_TX_NEED_ACK; 4768 if (params->ibp_flags & IEEE80211_BPF_RTS) { 4769 if (sc->hw_type != IWN_HW_REV_TYPE_4965) { 4770 /* 5000 autoselects RTS/CTS or CTS-to-self. */ 4771 flags &= ~IWN_TX_NEED_RTS; 4772 flags |= IWN_TX_NEED_PROTECTION; 4773 } else 4774 flags |= IWN_TX_NEED_RTS | IWN_TX_FULL_TXOP; 4775 } 4776 if (params->ibp_flags & IEEE80211_BPF_CTS) { 4777 if (sc->hw_type != IWN_HW_REV_TYPE_4965) { 4778 /* 5000 autoselects RTS/CTS or CTS-to-self. */ 4779 flags &= ~IWN_TX_NEED_CTS; 4780 flags |= IWN_TX_NEED_PROTECTION; 4781 } else 4782 flags |= IWN_TX_NEED_CTS | IWN_TX_FULL_TXOP; 4783 } 4784 4785 if (ieee80211_radiotap_active_vap(vap)) { 4786 struct iwn_tx_radiotap_header *tap = &sc->sc_txtap; 4787 4788 tap->wt_flags = 0; 4789 tap->wt_rate = rate; 4790 4791 ieee80211_radiotap_tx(vap, m); 4792 } 4793 4794 ring = &sc->txq[ac]; 4795 cmd = &ring->cmd[ring->cur]; 4796 4797 tx = (struct iwn_cmd_data *)cmd->data; 4798 /* NB: No need to clear tx, all fields are reinitialized here. */ 4799 tx->scratch = 0; /* clear "scratch" area */ 4800 4801 if (type == IEEE80211_FC0_TYPE_MGT) { 4802 uint8_t subtype = wh->i_fc[0] & IEEE80211_FC0_SUBTYPE_MASK; 4803 4804 /* Tell HW to set timestamp in probe responses. */ 4805 if (subtype == IEEE80211_FC0_SUBTYPE_PROBE_RESP) 4806 flags |= IWN_TX_INSERT_TSTAMP; 4807 4808 if (subtype == IEEE80211_FC0_SUBTYPE_ASSOC_REQ || 4809 subtype == IEEE80211_FC0_SUBTYPE_REASSOC_REQ) 4810 tx->timeout = htole16(3); 4811 else 4812 tx->timeout = htole16(2); 4813 } else 4814 tx->timeout = htole16(0); 4815 4816 tx->tid = 0; 4817 tx->id = sc->broadcast_id; 4818 tx->rts_ntries = params->ibp_try1; 4819 tx->data_ntries = params->ibp_try0; 4820 tx->lifetime = htole32(IWN_LIFETIME_INFINITE); 4821 tx->rate = iwn_rate_to_plcp(sc, ni, rate); 4822 tx->security = 0; 4823 tx->flags = htole32(flags); 4824 4825 /* Group or management frame. */ 4826 tx->linkq = 0; 4827 4828 return (iwn_tx_cmd(sc, m, ni, ring)); 4829 } 4830 4831 static int 4832 iwn_tx_cmd(struct iwn_softc *sc, struct mbuf *m, struct ieee80211_node *ni, 4833 struct iwn_tx_ring *ring) 4834 { 4835 struct iwn_ops *ops = &sc->ops; 4836 struct iwn_tx_cmd *cmd; 4837 struct iwn_cmd_data *tx; 4838 struct ieee80211_frame *wh; 4839 struct iwn_tx_desc *desc; 4840 struct iwn_tx_data *data; 4841 bus_dma_segment_t *seg, segs[IWN_MAX_SCATTER]; 4842 struct mbuf *m1; 4843 u_int hdrlen; 4844 int totlen, error, pad, nsegs = 0, i; 4845 4846 wh = mtod(m, struct ieee80211_frame *); 4847 hdrlen = ieee80211_anyhdrsize(wh); 4848 totlen = m->m_pkthdr.len; 4849 4850 desc = &ring->desc[ring->cur]; 4851 data = &ring->data[ring->cur]; 4852 4853 if (__predict_false(data->m != NULL || data->ni != NULL)) { 4854 device_printf(sc->sc_dev, "%s: ni (%p) or m (%p) for idx %d " 4855 "in queue %d is not NULL!\n", __func__, data->ni, data->m, 4856 ring->cur, ring->qid); 4857 return EIO; 4858 } 4859 4860 /* Prepare TX firmware command. */ 4861 cmd = &ring->cmd[ring->cur]; 4862 cmd->code = IWN_CMD_TX_DATA; 4863 cmd->flags = 0; 4864 cmd->qid = ring->qid; 4865 cmd->idx = ring->cur; 4866 4867 tx = (struct iwn_cmd_data *)cmd->data; 4868 tx->len = htole16(totlen); 4869 4870 /* Set physical address of "scratch area". */ 4871 tx->loaddr = htole32(IWN_LOADDR(data->scratch_paddr)); 4872 tx->hiaddr = IWN_HIADDR(data->scratch_paddr); 4873 if (hdrlen & 3) { 4874 /* First segment length must be a multiple of 4. */ 4875 tx->flags |= htole32(IWN_TX_NEED_PADDING); 4876 pad = 4 - (hdrlen & 3); 4877 } else 4878 pad = 0; 4879 4880 /* Copy 802.11 header in TX command. */ 4881 memcpy((uint8_t *)(tx + 1), wh, hdrlen); 4882 4883 /* Trim 802.11 header. */ 4884 m_adj(m, hdrlen); 4885 4886 error = bus_dmamap_load_mbuf_sg(ring->data_dmat, data->map, m, segs, 4887 &nsegs, BUS_DMA_NOWAIT); 4888 if (error != 0) { 4889 if (error != EFBIG) { 4890 device_printf(sc->sc_dev, 4891 "%s: can't map mbuf (error %d)\n", __func__, error); 4892 return error; 4893 } 4894 /* Too many DMA segments, linearize mbuf. */ 4895 m1 = m_collapse(m, M_NOWAIT, IWN_MAX_SCATTER - 1); 4896 if (m1 == NULL) { 4897 device_printf(sc->sc_dev, 4898 "%s: could not defrag mbuf\n", __func__); 4899 return ENOBUFS; 4900 } 4901 m = m1; 4902 4903 error = bus_dmamap_load_mbuf_sg(ring->data_dmat, data->map, m, 4904 segs, &nsegs, BUS_DMA_NOWAIT); 4905 if (error != 0) { 4906 /* XXX fix this */ 4907 /* 4908 * NB: Do not return error; 4909 * original mbuf does not exist anymore. 4910 */ 4911 device_printf(sc->sc_dev, 4912 "%s: can't map mbuf (error %d)\n", 4913 __func__, error); 4914 if_inc_counter(ni->ni_vap->iv_ifp, 4915 IFCOUNTER_OERRORS, 1); 4916 ieee80211_free_node(ni); 4917 m_freem(m); 4918 return 0; 4919 } 4920 } 4921 4922 data->m = m; 4923 data->ni = ni; 4924 4925 DPRINTF(sc, IWN_DEBUG_XMIT, "%s: qid %d idx %d len %d nsegs %d " 4926 "plcp 0x%x\n", 4927 __func__, ring->qid, ring->cur, totlen, nsegs, tx->rate); 4928 4929 /* Fill TX descriptor. */ 4930 desc->nsegs = 1; 4931 if (m->m_len != 0) 4932 desc->nsegs += nsegs; 4933 /* First DMA segment is used by the TX command. */ 4934 desc->segs[0].addr = htole32(IWN_LOADDR(data->cmd_paddr)); 4935 desc->segs[0].len = htole16(IWN_HIADDR(data->cmd_paddr) | 4936 (4 + sizeof (*tx) + hdrlen + pad) << 4); 4937 /* Other DMA segments are for data payload. */ 4938 seg = &segs[0]; 4939 for (i = 1; i <= nsegs; i++) { 4940 desc->segs[i].addr = htole32(IWN_LOADDR(seg->ds_addr)); 4941 desc->segs[i].len = htole16(IWN_HIADDR(seg->ds_addr) | 4942 seg->ds_len << 4); 4943 seg++; 4944 } 4945 4946 bus_dmamap_sync(ring->data_dmat, data->map, BUS_DMASYNC_PREWRITE); 4947 bus_dmamap_sync(ring->cmd_dma.tag, ring->cmd_dma.map, 4948 BUS_DMASYNC_PREWRITE); 4949 bus_dmamap_sync(ring->desc_dma.tag, ring->desc_dma.map, 4950 BUS_DMASYNC_PREWRITE); 4951 4952 /* Update TX scheduler. */ 4953 if (ring->qid >= sc->firstaggqueue) 4954 ops->update_sched(sc, ring->qid, ring->cur, tx->id, totlen); 4955 4956 /* Kick TX ring. */ 4957 ring->cur = (ring->cur + 1) % IWN_TX_RING_COUNT; 4958 IWN_WRITE(sc, IWN_HBUS_TARG_WRPTR, ring->qid << 8 | ring->cur); 4959 4960 /* Mark TX ring as full if we reach a certain threshold. */ 4961 if (++ring->queued > IWN_TX_RING_HIMARK) 4962 sc->qfullmsk |= 1 << ring->qid; 4963 4964 DPRINTF(sc, IWN_DEBUG_TRACE, "->%s: end\n",__func__); 4965 4966 return 0; 4967 } 4968 4969 static void 4970 iwn_xmit_task(void *arg0, int pending) 4971 { 4972 struct iwn_softc *sc = arg0; 4973 struct ieee80211_node *ni; 4974 struct mbuf *m; 4975 int error; 4976 struct ieee80211_bpf_params p; 4977 int have_p; 4978 4979 DPRINTF(sc, IWN_DEBUG_XMIT, "%s: called\n", __func__); 4980 4981 IWN_LOCK(sc); 4982 /* 4983 * Dequeue frames, attempt to transmit, 4984 * then disable beaconwait when we're done. 4985 */ 4986 while ((m = mbufq_dequeue(&sc->sc_xmit_queue)) != NULL) { 4987 have_p = 0; 4988 ni = (struct ieee80211_node *)m->m_pkthdr.rcvif; 4989 4990 /* Get xmit params if appropriate */ 4991 if (ieee80211_get_xmit_params(m, &p) == 0) 4992 have_p = 1; 4993 4994 DPRINTF(sc, IWN_DEBUG_XMIT, "%s: m=%p, have_p=%d\n", 4995 __func__, m, have_p); 4996 4997 /* If we have xmit params, use them */ 4998 if (have_p) 4999 error = iwn_tx_data_raw(sc, m, ni, &p); 5000 else 5001 error = iwn_tx_data(sc, m, ni); 5002 5003 if (error != 0) { 5004 if_inc_counter(ni->ni_vap->iv_ifp, 5005 IFCOUNTER_OERRORS, 1); 5006 ieee80211_free_node(ni); 5007 m_freem(m); 5008 } 5009 } 5010 5011 sc->sc_beacon_wait = 0; 5012 IWN_UNLOCK(sc); 5013 } 5014 5015 /* 5016 * raw frame xmit - free node/reference if failed. 5017 */ 5018 static int 5019 iwn_raw_xmit(struct ieee80211_node *ni, struct mbuf *m, 5020 const struct ieee80211_bpf_params *params) 5021 { 5022 struct ieee80211com *ic = ni->ni_ic; 5023 struct iwn_softc *sc = ic->ic_softc; 5024 int error = 0; 5025 5026 DPRINTF(sc, IWN_DEBUG_XMIT | IWN_DEBUG_TRACE, "->%s begin\n", __func__); 5027 5028 IWN_LOCK(sc); 5029 if ((sc->sc_flags & IWN_FLAG_RUNNING) == 0) { 5030 m_freem(m); 5031 IWN_UNLOCK(sc); 5032 return (ENETDOWN); 5033 } 5034 5035 /* queue frame if we have to */ 5036 if (sc->sc_beacon_wait) { 5037 if (iwn_xmit_queue_enqueue(sc, m) != 0) { 5038 m_freem(m); 5039 IWN_UNLOCK(sc); 5040 return (ENOBUFS); 5041 } 5042 /* Queued, so just return OK */ 5043 IWN_UNLOCK(sc); 5044 return (0); 5045 } 5046 5047 if (params == NULL) { 5048 /* 5049 * Legacy path; interpret frame contents to decide 5050 * precisely how to send the frame. 5051 */ 5052 error = iwn_tx_data(sc, m, ni); 5053 } else { 5054 /* 5055 * Caller supplied explicit parameters to use in 5056 * sending the frame. 5057 */ 5058 error = iwn_tx_data_raw(sc, m, ni, params); 5059 } 5060 if (error == 0) 5061 sc->sc_tx_timer = 5; 5062 else 5063 m_freem(m); 5064 5065 IWN_UNLOCK(sc); 5066 5067 DPRINTF(sc, IWN_DEBUG_TRACE | IWN_DEBUG_XMIT, "->%s: end\n",__func__); 5068 5069 return (error); 5070 } 5071 5072 /* 5073 * transmit - don't free mbuf if failed; don't free node ref if failed. 5074 */ 5075 static int 5076 iwn_transmit(struct ieee80211com *ic, struct mbuf *m) 5077 { 5078 struct iwn_softc *sc = ic->ic_softc; 5079 struct ieee80211_node *ni; 5080 int error; 5081 5082 ni = (struct ieee80211_node *)m->m_pkthdr.rcvif; 5083 5084 IWN_LOCK(sc); 5085 if ((sc->sc_flags & IWN_FLAG_RUNNING) == 0 || sc->sc_beacon_wait) { 5086 IWN_UNLOCK(sc); 5087 return (ENXIO); 5088 } 5089 5090 if (sc->qfullmsk) { 5091 IWN_UNLOCK(sc); 5092 return (ENOBUFS); 5093 } 5094 5095 error = iwn_tx_data(sc, m, ni); 5096 if (!error) 5097 sc->sc_tx_timer = 5; 5098 IWN_UNLOCK(sc); 5099 return (error); 5100 } 5101 5102 static void 5103 iwn_scan_timeout(void *arg) 5104 { 5105 struct iwn_softc *sc = arg; 5106 struct ieee80211com *ic = &sc->sc_ic; 5107 5108 ic_printf(ic, "scan timeout\n"); 5109 ieee80211_restart_all(ic); 5110 } 5111 5112 static void 5113 iwn_watchdog(void *arg) 5114 { 5115 struct iwn_softc *sc = arg; 5116 struct ieee80211com *ic = &sc->sc_ic; 5117 5118 IWN_LOCK_ASSERT(sc); 5119 5120 KASSERT(sc->sc_flags & IWN_FLAG_RUNNING, ("not running")); 5121 5122 DPRINTF(sc, IWN_DEBUG_TRACE, "->Doing %s\n", __func__); 5123 5124 if (sc->sc_tx_timer > 0) { 5125 if (--sc->sc_tx_timer == 0) { 5126 ic_printf(ic, "device timeout\n"); 5127 ieee80211_restart_all(ic); 5128 return; 5129 } 5130 } 5131 callout_reset(&sc->watchdog_to, hz, iwn_watchdog, sc); 5132 } 5133 5134 static int 5135 iwn_cdev_open(struct cdev *dev, int flags, int type, struct thread *td) 5136 { 5137 5138 return (0); 5139 } 5140 5141 static int 5142 iwn_cdev_close(struct cdev *dev, int flags, int type, struct thread *td) 5143 { 5144 5145 return (0); 5146 } 5147 5148 static int 5149 iwn_cdev_ioctl(struct cdev *dev, unsigned long cmd, caddr_t data, int fflag, 5150 struct thread *td) 5151 { 5152 int rc; 5153 struct iwn_softc *sc = dev->si_drv1; 5154 struct iwn_ioctl_data *d; 5155 5156 rc = priv_check(td, PRIV_DRIVER); 5157 if (rc != 0) 5158 return (0); 5159 5160 switch (cmd) { 5161 case SIOCGIWNSTATS: 5162 d = (struct iwn_ioctl_data *) data; 5163 IWN_LOCK(sc); 5164 /* XXX validate permissions/memory/etc? */ 5165 rc = copyout(&sc->last_stat, d->dst_addr, sizeof(struct iwn_stats)); 5166 IWN_UNLOCK(sc); 5167 break; 5168 case SIOCZIWNSTATS: 5169 IWN_LOCK(sc); 5170 memset(&sc->last_stat, 0, sizeof(struct iwn_stats)); 5171 IWN_UNLOCK(sc); 5172 break; 5173 default: 5174 rc = EINVAL; 5175 break; 5176 } 5177 return (rc); 5178 } 5179 5180 static int 5181 iwn_ioctl(struct ieee80211com *ic, u_long cmd, void *data) 5182 { 5183 5184 return (ENOTTY); 5185 } 5186 5187 static void 5188 iwn_parent(struct ieee80211com *ic) 5189 { 5190 struct iwn_softc *sc = ic->ic_softc; 5191 struct ieee80211vap *vap; 5192 int error; 5193 5194 if (ic->ic_nrunning > 0) { 5195 error = iwn_init(sc); 5196 5197 switch (error) { 5198 case 0: 5199 ieee80211_start_all(ic); 5200 break; 5201 case 1: 5202 /* radio is disabled via RFkill switch */ 5203 taskqueue_enqueue(sc->sc_tq, &sc->sc_rftoggle_task); 5204 break; 5205 default: 5206 vap = TAILQ_FIRST(&ic->ic_vaps); 5207 if (vap != NULL) 5208 ieee80211_stop(vap); 5209 break; 5210 } 5211 } else 5212 iwn_stop(sc); 5213 } 5214 5215 /* 5216 * Send a command to the firmware. 5217 */ 5218 static int 5219 iwn_cmd(struct iwn_softc *sc, int code, const void *buf, int size, int async) 5220 { 5221 struct iwn_tx_ring *ring; 5222 struct iwn_tx_desc *desc; 5223 struct iwn_tx_data *data; 5224 struct iwn_tx_cmd *cmd; 5225 struct mbuf *m; 5226 bus_addr_t paddr; 5227 int totlen, error; 5228 int cmd_queue_num; 5229 5230 DPRINTF(sc, IWN_DEBUG_TRACE, "->%s begin\n", __func__); 5231 5232 if (async == 0) 5233 IWN_LOCK_ASSERT(sc); 5234 5235 if (sc->sc_flags & IWN_FLAG_PAN_SUPPORT) 5236 cmd_queue_num = IWN_PAN_CMD_QUEUE; 5237 else 5238 cmd_queue_num = IWN_CMD_QUEUE_NUM; 5239 5240 ring = &sc->txq[cmd_queue_num]; 5241 desc = &ring->desc[ring->cur]; 5242 data = &ring->data[ring->cur]; 5243 totlen = 4 + size; 5244 5245 if (size > sizeof cmd->data) { 5246 /* Command is too large to fit in a descriptor. */ 5247 if (totlen > MCLBYTES) 5248 return EINVAL; 5249 m = m_getjcl(M_NOWAIT, MT_DATA, M_PKTHDR, MJUMPAGESIZE); 5250 if (m == NULL) 5251 return ENOMEM; 5252 cmd = mtod(m, struct iwn_tx_cmd *); 5253 error = bus_dmamap_load(ring->data_dmat, data->map, cmd, 5254 totlen, iwn_dma_map_addr, &paddr, BUS_DMA_NOWAIT); 5255 if (error != 0) { 5256 m_freem(m); 5257 return error; 5258 } 5259 data->m = m; 5260 } else { 5261 cmd = &ring->cmd[ring->cur]; 5262 paddr = data->cmd_paddr; 5263 } 5264 5265 cmd->code = code; 5266 cmd->flags = 0; 5267 cmd->qid = ring->qid; 5268 cmd->idx = ring->cur; 5269 memcpy(cmd->data, buf, size); 5270 5271 desc->nsegs = 1; 5272 desc->segs[0].addr = htole32(IWN_LOADDR(paddr)); 5273 desc->segs[0].len = htole16(IWN_HIADDR(paddr) | totlen << 4); 5274 5275 DPRINTF(sc, IWN_DEBUG_CMD, "%s: %s (0x%x) flags %d qid %d idx %d\n", 5276 __func__, iwn_intr_str(cmd->code), cmd->code, 5277 cmd->flags, cmd->qid, cmd->idx); 5278 5279 if (size > sizeof cmd->data) { 5280 bus_dmamap_sync(ring->data_dmat, data->map, 5281 BUS_DMASYNC_PREWRITE); 5282 } else { 5283 bus_dmamap_sync(ring->cmd_dma.tag, ring->cmd_dma.map, 5284 BUS_DMASYNC_PREWRITE); 5285 } 5286 bus_dmamap_sync(ring->desc_dma.tag, ring->desc_dma.map, 5287 BUS_DMASYNC_PREWRITE); 5288 5289 /* Kick command ring. */ 5290 ring->cur = (ring->cur + 1) % IWN_TX_RING_COUNT; 5291 IWN_WRITE(sc, IWN_HBUS_TARG_WRPTR, ring->qid << 8 | ring->cur); 5292 5293 DPRINTF(sc, IWN_DEBUG_TRACE, "->%s: end\n",__func__); 5294 5295 return async ? 0 : msleep(desc, &sc->sc_mtx, PCATCH, "iwncmd", hz); 5296 } 5297 5298 static int 5299 iwn4965_add_node(struct iwn_softc *sc, struct iwn_node_info *node, int async) 5300 { 5301 struct iwn4965_node_info hnode; 5302 caddr_t src, dst; 5303 5304 DPRINTF(sc, IWN_DEBUG_TRACE, "->Doing %s\n", __func__); 5305 5306 /* 5307 * We use the node structure for 5000 Series internally (it is 5308 * a superset of the one for 4965AGN). We thus copy the common 5309 * fields before sending the command. 5310 */ 5311 src = (caddr_t)node; 5312 dst = (caddr_t)&hnode; 5313 memcpy(dst, src, 48); 5314 /* Skip TSC, RX MIC and TX MIC fields from ``src''. */ 5315 memcpy(dst + 48, src + 72, 20); 5316 return iwn_cmd(sc, IWN_CMD_ADD_NODE, &hnode, sizeof hnode, async); 5317 } 5318 5319 static int 5320 iwn5000_add_node(struct iwn_softc *sc, struct iwn_node_info *node, int async) 5321 { 5322 5323 DPRINTF(sc, IWN_DEBUG_TRACE, "->Doing %s\n", __func__); 5324 5325 /* Direct mapping. */ 5326 return iwn_cmd(sc, IWN_CMD_ADD_NODE, node, sizeof (*node), async); 5327 } 5328 5329 static int 5330 iwn_set_link_quality(struct iwn_softc *sc, struct ieee80211_node *ni) 5331 { 5332 struct iwn_node *wn = (void *)ni; 5333 struct ieee80211_rateset *rs; 5334 struct iwn_cmd_link_quality linkq; 5335 int i, rate, txrate; 5336 int is_11n; 5337 5338 DPRINTF(sc, IWN_DEBUG_TRACE, "->%s begin\n", __func__); 5339 5340 memset(&linkq, 0, sizeof linkq); 5341 linkq.id = wn->id; 5342 linkq.antmsk_1stream = iwn_get_1stream_tx_antmask(sc); 5343 linkq.antmsk_2stream = iwn_get_2stream_tx_antmask(sc); 5344 5345 linkq.ampdu_max = 32; /* XXX negotiated? */ 5346 linkq.ampdu_threshold = 3; 5347 linkq.ampdu_limit = htole16(4000); /* 4ms */ 5348 5349 DPRINTF(sc, IWN_DEBUG_XMIT, 5350 "%s: 1stream antenna=0x%02x, 2stream antenna=0x%02x, ntxstreams=%d\n", 5351 __func__, 5352 linkq.antmsk_1stream, 5353 linkq.antmsk_2stream, 5354 sc->ntxchains); 5355 5356 /* 5357 * Are we using 11n rates? Ensure the channel is 5358 * 11n _and_ we have some 11n rates, or don't 5359 * try. 5360 */ 5361 if (ieee80211_ht_check_tx_ht(ni)) { 5362 rs = (struct ieee80211_rateset *) &ni->ni_htrates; 5363 is_11n = 1; 5364 } else { 5365 rs = &ni->ni_rates; 5366 is_11n = 0; 5367 } 5368 5369 /* Start at highest available bit-rate. */ 5370 /* 5371 * XXX this is all very dirty! 5372 */ 5373 if (is_11n) 5374 txrate = ni->ni_htrates.rs_nrates - 1; 5375 else 5376 txrate = rs->rs_nrates - 1; 5377 for (i = 0; i < IWN_MAX_TX_RETRIES; i++) { 5378 uint32_t plcp; 5379 5380 /* 5381 * XXX TODO: ensure the last two slots are the two lowest 5382 * rate entries, just for now. 5383 */ 5384 if (i == 14 || i == 15) 5385 txrate = 0; 5386 5387 if (is_11n) 5388 rate = IEEE80211_RATE_MCS | rs->rs_rates[txrate]; 5389 else 5390 rate = IEEE80211_RV(rs->rs_rates[txrate]); 5391 5392 /* Do rate -> PLCP config mapping */ 5393 plcp = iwn_rate_to_plcp(sc, ni, rate); 5394 linkq.retry[i] = plcp; 5395 DPRINTF(sc, IWN_DEBUG_XMIT, 5396 "%s: i=%d, txrate=%d, rate=0x%02x, plcp=0x%08x\n", 5397 __func__, 5398 i, 5399 txrate, 5400 rate, 5401 le32toh(plcp)); 5402 5403 /* 5404 * The mimo field is an index into the table which 5405 * indicates the first index where it and subsequent entries 5406 * will not be using MIMO. 5407 * 5408 * Since we're filling linkq from 0..15 and we're filling 5409 * from the highest MCS rates to the lowest rates, if we 5410 * _are_ doing a dual-stream rate, set mimo to idx+1 (ie, 5411 * the next entry.) That way if the next entry is a non-MIMO 5412 * entry, we're already pointing at it. 5413 */ 5414 if ((le32toh(plcp) & IWN_RFLAG_MCS) && 5415 IEEE80211_RV(le32toh(plcp)) > 7) 5416 linkq.mimo = i + 1; 5417 5418 /* Next retry at immediate lower bit-rate. */ 5419 if (txrate > 0) 5420 txrate--; 5421 } 5422 /* 5423 * If we reached the end of the list and indeed we hit 5424 * all MIMO rates (eg 5300 doing MCS23-15) then yes, 5425 * set mimo to 15. Setting it to 16 panics the firmware. 5426 */ 5427 if (linkq.mimo > 15) 5428 linkq.mimo = 15; 5429 5430 DPRINTF(sc, IWN_DEBUG_XMIT, "%s: mimo = %d\n", __func__, linkq.mimo); 5431 5432 DPRINTF(sc, IWN_DEBUG_TRACE, "->%s: end\n",__func__); 5433 5434 return iwn_cmd(sc, IWN_CMD_LINK_QUALITY, &linkq, sizeof linkq, 1); 5435 } 5436 5437 /* 5438 * Broadcast node is used to send group-addressed and management frames. 5439 */ 5440 static int 5441 iwn_add_broadcast_node(struct iwn_softc *sc, int async) 5442 { 5443 struct iwn_ops *ops = &sc->ops; 5444 struct ieee80211com *ic = &sc->sc_ic; 5445 struct iwn_node_info node; 5446 struct iwn_cmd_link_quality linkq; 5447 uint8_t txant; 5448 int i, error; 5449 5450 DPRINTF(sc, IWN_DEBUG_TRACE, "->%s begin\n", __func__); 5451 5452 sc->rxon = &sc->rx_on[IWN_RXON_BSS_CTX]; 5453 5454 memset(&node, 0, sizeof node); 5455 IEEE80211_ADDR_COPY(node.macaddr, ieee80211broadcastaddr); 5456 node.id = sc->broadcast_id; 5457 DPRINTF(sc, IWN_DEBUG_RESET, "%s: adding broadcast node\n", __func__); 5458 if ((error = ops->add_node(sc, &node, async)) != 0) 5459 return error; 5460 5461 /* Use the first valid TX antenna. */ 5462 txant = IWN_LSB(sc->txchainmask); 5463 5464 memset(&linkq, 0, sizeof linkq); 5465 linkq.id = sc->broadcast_id; 5466 linkq.antmsk_1stream = iwn_get_1stream_tx_antmask(sc); 5467 linkq.antmsk_2stream = iwn_get_2stream_tx_antmask(sc); 5468 linkq.ampdu_max = 64; 5469 linkq.ampdu_threshold = 3; 5470 linkq.ampdu_limit = htole16(4000); /* 4ms */ 5471 5472 /* Use lowest mandatory bit-rate. */ 5473 /* XXX rate table lookup? */ 5474 if (IEEE80211_IS_CHAN_5GHZ(ic->ic_curchan)) 5475 linkq.retry[0] = htole32(0xd); 5476 else 5477 linkq.retry[0] = htole32(10 | IWN_RFLAG_CCK); 5478 linkq.retry[0] |= htole32(IWN_RFLAG_ANT(txant)); 5479 /* Use same bit-rate for all TX retries. */ 5480 for (i = 1; i < IWN_MAX_TX_RETRIES; i++) { 5481 linkq.retry[i] = linkq.retry[0]; 5482 } 5483 5484 DPRINTF(sc, IWN_DEBUG_TRACE, "->%s: end\n",__func__); 5485 5486 return iwn_cmd(sc, IWN_CMD_LINK_QUALITY, &linkq, sizeof linkq, async); 5487 } 5488 5489 static int 5490 iwn_updateedca(struct ieee80211com *ic) 5491 { 5492 #define IWN_EXP2(x) ((1 << (x)) - 1) /* CWmin = 2^ECWmin - 1 */ 5493 struct iwn_softc *sc = ic->ic_softc; 5494 struct iwn_edca_params cmd; 5495 struct chanAccParams chp; 5496 int aci; 5497 5498 DPRINTF(sc, IWN_DEBUG_TRACE, "->%s begin\n", __func__); 5499 5500 ieee80211_wme_ic_getparams(ic, &chp); 5501 5502 memset(&cmd, 0, sizeof cmd); 5503 cmd.flags = htole32(IWN_EDCA_UPDATE); 5504 5505 IEEE80211_LOCK(ic); 5506 for (aci = 0; aci < WME_NUM_AC; aci++) { 5507 const struct wmeParams *ac = &chp.cap_wmeParams[aci]; 5508 cmd.ac[aci].aifsn = ac->wmep_aifsn; 5509 cmd.ac[aci].cwmin = htole16(IWN_EXP2(ac->wmep_logcwmin)); 5510 cmd.ac[aci].cwmax = htole16(IWN_EXP2(ac->wmep_logcwmax)); 5511 cmd.ac[aci].txoplimit = 5512 htole16(IEEE80211_TXOP_TO_US(ac->wmep_txopLimit)); 5513 } 5514 IEEE80211_UNLOCK(ic); 5515 5516 IWN_LOCK(sc); 5517 (void)iwn_cmd(sc, IWN_CMD_EDCA_PARAMS, &cmd, sizeof cmd, 1); 5518 IWN_UNLOCK(sc); 5519 5520 DPRINTF(sc, IWN_DEBUG_TRACE, "->%s: end\n",__func__); 5521 5522 return 0; 5523 #undef IWN_EXP2 5524 } 5525 5526 static void 5527 iwn_set_promisc(struct iwn_softc *sc) 5528 { 5529 struct ieee80211com *ic = &sc->sc_ic; 5530 uint32_t promisc_filter; 5531 5532 promisc_filter = IWN_FILTER_CTL | IWN_FILTER_PROMISC; 5533 if (ic->ic_promisc > 0 || ic->ic_opmode == IEEE80211_M_MONITOR) 5534 sc->rxon->filter |= htole32(promisc_filter); 5535 else 5536 sc->rxon->filter &= ~htole32(promisc_filter); 5537 } 5538 5539 static void 5540 iwn_update_promisc(struct ieee80211com *ic) 5541 { 5542 struct iwn_softc *sc = ic->ic_softc; 5543 int error; 5544 5545 if (ic->ic_opmode == IEEE80211_M_MONITOR) 5546 return; /* nothing to do */ 5547 5548 IWN_LOCK(sc); 5549 if (!(sc->sc_flags & IWN_FLAG_RUNNING)) { 5550 IWN_UNLOCK(sc); 5551 return; 5552 } 5553 5554 iwn_set_promisc(sc); 5555 if ((error = iwn_send_rxon(sc, 1, 1)) != 0) { 5556 device_printf(sc->sc_dev, 5557 "%s: could not send RXON, error %d\n", 5558 __func__, error); 5559 } 5560 IWN_UNLOCK(sc); 5561 } 5562 5563 static void 5564 iwn_update_mcast(struct ieee80211com *ic) 5565 { 5566 /* Ignore */ 5567 } 5568 5569 static void 5570 iwn_set_led(struct iwn_softc *sc, uint8_t which, uint8_t off, uint8_t on) 5571 { 5572 struct iwn_cmd_led led; 5573 5574 DPRINTF(sc, IWN_DEBUG_TRACE, "->Doing %s\n", __func__); 5575 5576 #if 0 5577 /* XXX don't set LEDs during scan? */ 5578 if (sc->sc_is_scanning) 5579 return; 5580 #endif 5581 5582 /* Clear microcode LED ownership. */ 5583 IWN_CLRBITS(sc, IWN_LED, IWN_LED_BSM_CTRL); 5584 5585 led.which = which; 5586 led.unit = htole32(10000); /* on/off in unit of 100ms */ 5587 led.off = off; 5588 led.on = on; 5589 (void)iwn_cmd(sc, IWN_CMD_SET_LED, &led, sizeof led, 1); 5590 } 5591 5592 /* 5593 * Set the critical temperature at which the firmware will stop the radio 5594 * and notify us. 5595 */ 5596 static int 5597 iwn_set_critical_temp(struct iwn_softc *sc) 5598 { 5599 struct iwn_critical_temp crit; 5600 int32_t temp; 5601 5602 DPRINTF(sc, IWN_DEBUG_TRACE, "->Doing %s\n", __func__); 5603 5604 IWN_WRITE(sc, IWN_UCODE_GP1_CLR, IWN_UCODE_GP1_CTEMP_STOP_RF); 5605 5606 if (sc->hw_type == IWN_HW_REV_TYPE_5150) 5607 temp = (IWN_CTOK(110) - sc->temp_off) * -5; 5608 else if (sc->hw_type == IWN_HW_REV_TYPE_4965) 5609 temp = IWN_CTOK(110); 5610 else 5611 temp = 110; 5612 memset(&crit, 0, sizeof crit); 5613 crit.tempR = htole32(temp); 5614 DPRINTF(sc, IWN_DEBUG_RESET, "setting critical temp to %d\n", temp); 5615 return iwn_cmd(sc, IWN_CMD_SET_CRITICAL_TEMP, &crit, sizeof crit, 0); 5616 } 5617 5618 static int 5619 iwn_set_timing(struct iwn_softc *sc, struct ieee80211_node *ni) 5620 { 5621 struct iwn_cmd_timing cmd; 5622 uint64_t val, mod; 5623 5624 DPRINTF(sc, IWN_DEBUG_TRACE, "->Doing %s\n", __func__); 5625 5626 memset(&cmd, 0, sizeof cmd); 5627 memcpy(&cmd.tstamp, ni->ni_tstamp.data, sizeof (uint64_t)); 5628 cmd.bintval = htole16(ni->ni_intval); 5629 cmd.lintval = htole16(10); 5630 5631 /* Compute remaining time until next beacon. */ 5632 val = (uint64_t)ni->ni_intval * IEEE80211_DUR_TU; 5633 mod = le64toh(cmd.tstamp) % val; 5634 cmd.binitval = htole32((uint32_t)(val - mod)); 5635 5636 DPRINTF(sc, IWN_DEBUG_RESET, "timing bintval=%u tstamp=%ju, init=%u\n", 5637 ni->ni_intval, le64toh(cmd.tstamp), (uint32_t)(val - mod)); 5638 5639 return iwn_cmd(sc, IWN_CMD_TIMING, &cmd, sizeof cmd, 1); 5640 } 5641 5642 static void 5643 iwn4965_power_calibration(struct iwn_softc *sc, int temp) 5644 { 5645 5646 DPRINTF(sc, IWN_DEBUG_TRACE, "->Doing %s\n", __func__); 5647 5648 /* Adjust TX power if need be (delta >= 3 degC). */ 5649 DPRINTF(sc, IWN_DEBUG_CALIBRATE, "%s: temperature %d->%d\n", 5650 __func__, sc->temp, temp); 5651 if (abs(temp - sc->temp) >= 3) { 5652 /* Record temperature of last calibration. */ 5653 sc->temp = temp; 5654 (void)iwn4965_set_txpower(sc, 1); 5655 } 5656 } 5657 5658 /* 5659 * Set TX power for current channel (each rate has its own power settings). 5660 * This function takes into account the regulatory information from EEPROM, 5661 * the current temperature and the current voltage. 5662 */ 5663 static int 5664 iwn4965_set_txpower(struct iwn_softc *sc, int async) 5665 { 5666 /* Fixed-point arithmetic division using a n-bit fractional part. */ 5667 #define fdivround(a, b, n) \ 5668 ((((1 << n) * (a)) / (b) + (1 << n) / 2) / (1 << n)) 5669 /* Linear interpolation. */ 5670 #define interpolate(x, x1, y1, x2, y2, n) \ 5671 ((y1) + fdivround(((int)(x) - (x1)) * ((y2) - (y1)), (x2) - (x1), n)) 5672 5673 static const int tdiv[IWN_NATTEN_GROUPS] = { 9, 8, 8, 8, 6 }; 5674 struct iwn_ucode_info *uc = &sc->ucode_info; 5675 struct iwn4965_cmd_txpower cmd; 5676 struct iwn4965_eeprom_chan_samples *chans; 5677 const uint8_t *rf_gain, *dsp_gain; 5678 int32_t vdiff, tdiff; 5679 int i, is_chan_5ghz, c, grp, maxpwr; 5680 uint8_t chan; 5681 5682 sc->rxon = &sc->rx_on[IWN_RXON_BSS_CTX]; 5683 /* Retrieve current channel from last RXON. */ 5684 chan = sc->rxon->chan; 5685 is_chan_5ghz = (sc->rxon->flags & htole32(IWN_RXON_24GHZ)) == 0; 5686 DPRINTF(sc, IWN_DEBUG_RESET, "setting TX power for channel %d\n", 5687 chan); 5688 5689 memset(&cmd, 0, sizeof cmd); 5690 cmd.band = is_chan_5ghz ? 0 : 1; 5691 cmd.chan = chan; 5692 5693 if (is_chan_5ghz) { 5694 maxpwr = sc->maxpwr5GHz; 5695 rf_gain = iwn4965_rf_gain_5ghz; 5696 dsp_gain = iwn4965_dsp_gain_5ghz; 5697 } else { 5698 maxpwr = sc->maxpwr2GHz; 5699 rf_gain = iwn4965_rf_gain_2ghz; 5700 dsp_gain = iwn4965_dsp_gain_2ghz; 5701 } 5702 5703 /* Compute voltage compensation. */ 5704 vdiff = ((int32_t)le32toh(uc->volt) - sc->eeprom_voltage) / 7; 5705 if (vdiff > 0) 5706 vdiff *= 2; 5707 if (abs(vdiff) > 2) 5708 vdiff = 0; 5709 DPRINTF(sc, IWN_DEBUG_CALIBRATE | IWN_DEBUG_TXPOW, 5710 "%s: voltage compensation=%d (UCODE=%d, EEPROM=%d)\n", 5711 __func__, vdiff, le32toh(uc->volt), sc->eeprom_voltage); 5712 5713 /* Get channel attenuation group. */ 5714 if (chan <= 20) /* 1-20 */ 5715 grp = 4; 5716 else if (chan <= 43) /* 34-43 */ 5717 grp = 0; 5718 else if (chan <= 70) /* 44-70 */ 5719 grp = 1; 5720 else if (chan <= 124) /* 71-124 */ 5721 grp = 2; 5722 else /* 125-200 */ 5723 grp = 3; 5724 DPRINTF(sc, IWN_DEBUG_CALIBRATE | IWN_DEBUG_TXPOW, 5725 "%s: chan %d, attenuation group=%d\n", __func__, chan, grp); 5726 5727 /* Get channel sub-band. */ 5728 for (i = 0; i < IWN_NBANDS; i++) 5729 if (sc->bands[i].lo != 0 && 5730 sc->bands[i].lo <= chan && chan <= sc->bands[i].hi) 5731 break; 5732 if (i == IWN_NBANDS) /* Can't happen in real-life. */ 5733 return EINVAL; 5734 chans = sc->bands[i].chans; 5735 DPRINTF(sc, IWN_DEBUG_CALIBRATE | IWN_DEBUG_TXPOW, 5736 "%s: chan %d sub-band=%d\n", __func__, chan, i); 5737 5738 for (c = 0; c < 2; c++) { 5739 uint8_t power, gain, temp; 5740 int maxchpwr, pwr, ridx, idx; 5741 5742 power = interpolate(chan, 5743 chans[0].num, chans[0].samples[c][1].power, 5744 chans[1].num, chans[1].samples[c][1].power, 1); 5745 gain = interpolate(chan, 5746 chans[0].num, chans[0].samples[c][1].gain, 5747 chans[1].num, chans[1].samples[c][1].gain, 1); 5748 temp = interpolate(chan, 5749 chans[0].num, chans[0].samples[c][1].temp, 5750 chans[1].num, chans[1].samples[c][1].temp, 1); 5751 DPRINTF(sc, IWN_DEBUG_CALIBRATE | IWN_DEBUG_TXPOW, 5752 "%s: Tx chain %d: power=%d gain=%d temp=%d\n", 5753 __func__, c, power, gain, temp); 5754 5755 /* Compute temperature compensation. */ 5756 tdiff = ((sc->temp - temp) * 2) / tdiv[grp]; 5757 DPRINTF(sc, IWN_DEBUG_CALIBRATE | IWN_DEBUG_TXPOW, 5758 "%s: temperature compensation=%d (current=%d, EEPROM=%d)\n", 5759 __func__, tdiff, sc->temp, temp); 5760 5761 for (ridx = 0; ridx <= IWN_RIDX_MAX; ridx++) { 5762 /* Convert dBm to half-dBm. */ 5763 maxchpwr = sc->maxpwr[chan] * 2; 5764 if ((ridx / 8) & 1) 5765 maxchpwr -= 6; /* MIMO 2T: -3dB */ 5766 5767 pwr = maxpwr; 5768 5769 /* Adjust TX power based on rate. */ 5770 if ((ridx % 8) == 5) 5771 pwr -= 15; /* OFDM48: -7.5dB */ 5772 else if ((ridx % 8) == 6) 5773 pwr -= 17; /* OFDM54: -8.5dB */ 5774 else if ((ridx % 8) == 7) 5775 pwr -= 20; /* OFDM60: -10dB */ 5776 else 5777 pwr -= 10; /* Others: -5dB */ 5778 5779 /* Do not exceed channel max TX power. */ 5780 if (pwr > maxchpwr) 5781 pwr = maxchpwr; 5782 5783 idx = gain - (pwr - power) - tdiff - vdiff; 5784 if ((ridx / 8) & 1) /* MIMO */ 5785 idx += (int32_t)le32toh(uc->atten[grp][c]); 5786 5787 if (cmd.band == 0) 5788 idx += 9; /* 5GHz */ 5789 if (ridx == IWN_RIDX_MAX) 5790 idx += 5; /* CCK */ 5791 5792 /* Make sure idx stays in a valid range. */ 5793 if (idx < 0) 5794 idx = 0; 5795 else if (idx > IWN4965_MAX_PWR_INDEX) 5796 idx = IWN4965_MAX_PWR_INDEX; 5797 5798 DPRINTF(sc, IWN_DEBUG_CALIBRATE | IWN_DEBUG_TXPOW, 5799 "%s: Tx chain %d, rate idx %d: power=%d\n", 5800 __func__, c, ridx, idx); 5801 cmd.power[ridx].rf_gain[c] = rf_gain[idx]; 5802 cmd.power[ridx].dsp_gain[c] = dsp_gain[idx]; 5803 } 5804 } 5805 5806 DPRINTF(sc, IWN_DEBUG_CALIBRATE | IWN_DEBUG_TXPOW, 5807 "%s: set tx power for chan %d\n", __func__, chan); 5808 return iwn_cmd(sc, IWN_CMD_TXPOWER, &cmd, sizeof cmd, async); 5809 5810 #undef interpolate 5811 #undef fdivround 5812 } 5813 5814 static int 5815 iwn5000_set_txpower(struct iwn_softc *sc, int async) 5816 { 5817 struct iwn5000_cmd_txpower cmd; 5818 int cmdid; 5819 5820 DPRINTF(sc, IWN_DEBUG_TRACE, "->Doing %s\n", __func__); 5821 5822 /* 5823 * TX power calibration is handled automatically by the firmware 5824 * for 5000 Series. 5825 */ 5826 memset(&cmd, 0, sizeof cmd); 5827 cmd.global_limit = 2 * IWN5000_TXPOWER_MAX_DBM; /* 16 dBm */ 5828 cmd.flags = IWN5000_TXPOWER_NO_CLOSED; 5829 cmd.srv_limit = IWN5000_TXPOWER_AUTO; 5830 DPRINTF(sc, IWN_DEBUG_CALIBRATE | IWN_DEBUG_XMIT, 5831 "%s: setting TX power; rev=%d\n", 5832 __func__, 5833 IWN_UCODE_API(sc->ucode_rev)); 5834 if (IWN_UCODE_API(sc->ucode_rev) == 1) 5835 cmdid = IWN_CMD_TXPOWER_DBM_V1; 5836 else 5837 cmdid = IWN_CMD_TXPOWER_DBM; 5838 return iwn_cmd(sc, cmdid, &cmd, sizeof cmd, async); 5839 } 5840 5841 /* 5842 * Retrieve the maximum RSSI (in dBm) among receivers. 5843 */ 5844 static int 5845 iwn4965_get_rssi(struct iwn_softc *sc, struct iwn_rx_stat *stat) 5846 { 5847 struct iwn4965_rx_phystat *phy = (void *)stat->phybuf; 5848 uint8_t mask, agc; 5849 int rssi; 5850 5851 DPRINTF(sc, IWN_DEBUG_TRACE, "->Doing %s\n", __func__); 5852 5853 mask = (le16toh(phy->antenna) >> 4) & IWN_ANT_ABC; 5854 agc = (le16toh(phy->agc) >> 7) & 0x7f; 5855 5856 rssi = 0; 5857 if (mask & IWN_ANT_A) 5858 rssi = MAX(rssi, phy->rssi[0]); 5859 if (mask & IWN_ANT_B) 5860 rssi = MAX(rssi, phy->rssi[2]); 5861 if (mask & IWN_ANT_C) 5862 rssi = MAX(rssi, phy->rssi[4]); 5863 5864 DPRINTF(sc, IWN_DEBUG_RECV, 5865 "%s: agc %d mask 0x%x rssi %d %d %d result %d\n", __func__, agc, 5866 mask, phy->rssi[0], phy->rssi[2], phy->rssi[4], 5867 rssi - agc - IWN_RSSI_TO_DBM); 5868 return rssi - agc - IWN_RSSI_TO_DBM; 5869 } 5870 5871 static int 5872 iwn5000_get_rssi(struct iwn_softc *sc, struct iwn_rx_stat *stat) 5873 { 5874 struct iwn5000_rx_phystat *phy = (void *)stat->phybuf; 5875 uint8_t agc; 5876 int rssi; 5877 5878 DPRINTF(sc, IWN_DEBUG_TRACE, "->Doing %s\n", __func__); 5879 5880 agc = (le32toh(phy->agc) >> 9) & 0x7f; 5881 5882 rssi = MAX(le16toh(phy->rssi[0]) & 0xff, 5883 le16toh(phy->rssi[1]) & 0xff); 5884 rssi = MAX(le16toh(phy->rssi[2]) & 0xff, rssi); 5885 5886 DPRINTF(sc, IWN_DEBUG_RECV, 5887 "%s: agc %d rssi %d %d %d result %d\n", __func__, agc, 5888 phy->rssi[0], phy->rssi[1], phy->rssi[2], 5889 rssi - agc - IWN_RSSI_TO_DBM); 5890 return rssi - agc - IWN_RSSI_TO_DBM; 5891 } 5892 5893 /* 5894 * Retrieve the average noise (in dBm) among receivers. 5895 */ 5896 static int 5897 iwn_get_noise(const struct iwn_rx_general_stats *stats) 5898 { 5899 int i, total, nbant, noise; 5900 5901 total = nbant = 0; 5902 for (i = 0; i < 3; i++) { 5903 if ((noise = le32toh(stats->noise[i]) & 0xff) == 0) 5904 continue; 5905 total += noise; 5906 nbant++; 5907 } 5908 /* There should be at least one antenna but check anyway. */ 5909 return (nbant == 0) ? -127 : (total / nbant) - 107; 5910 } 5911 5912 /* 5913 * Compute temperature (in degC) from last received statistics. 5914 */ 5915 static int 5916 iwn4965_get_temperature(struct iwn_softc *sc) 5917 { 5918 struct iwn_ucode_info *uc = &sc->ucode_info; 5919 int32_t r1, r2, r3, r4, temp; 5920 5921 DPRINTF(sc, IWN_DEBUG_TRACE, "->Doing %s\n", __func__); 5922 5923 r1 = le32toh(uc->temp[0].chan20MHz); 5924 r2 = le32toh(uc->temp[1].chan20MHz); 5925 r3 = le32toh(uc->temp[2].chan20MHz); 5926 r4 = le32toh(sc->rawtemp); 5927 5928 if (r1 == r3) /* Prevents division by 0 (should not happen). */ 5929 return 0; 5930 5931 /* Sign-extend 23-bit R4 value to 32-bit. */ 5932 r4 = ((r4 & 0xffffff) ^ 0x800000) - 0x800000; 5933 /* Compute temperature in Kelvin. */ 5934 temp = (259 * (r4 - r2)) / (r3 - r1); 5935 temp = (temp * 97) / 100 + 8; 5936 5937 DPRINTF(sc, IWN_DEBUG_ANY, "temperature %dK/%dC\n", temp, 5938 IWN_KTOC(temp)); 5939 return IWN_KTOC(temp); 5940 } 5941 5942 static int 5943 iwn5000_get_temperature(struct iwn_softc *sc) 5944 { 5945 int32_t temp; 5946 5947 DPRINTF(sc, IWN_DEBUG_TRACE, "->Doing %s\n", __func__); 5948 5949 /* 5950 * Temperature is not used by the driver for 5000 Series because 5951 * TX power calibration is handled by firmware. 5952 */ 5953 temp = le32toh(sc->rawtemp); 5954 if (sc->hw_type == IWN_HW_REV_TYPE_5150) { 5955 temp = (temp / -5) + sc->temp_off; 5956 temp = IWN_KTOC(temp); 5957 } 5958 return temp; 5959 } 5960 5961 /* 5962 * Initialize sensitivity calibration state machine. 5963 */ 5964 static int 5965 iwn_init_sensitivity(struct iwn_softc *sc) 5966 { 5967 struct iwn_ops *ops = &sc->ops; 5968 struct iwn_calib_state *calib = &sc->calib; 5969 uint32_t flags; 5970 int error; 5971 5972 DPRINTF(sc, IWN_DEBUG_TRACE, "->Doing %s\n", __func__); 5973 5974 /* Reset calibration state machine. */ 5975 memset(calib, 0, sizeof (*calib)); 5976 calib->state = IWN_CALIB_STATE_INIT; 5977 calib->cck_state = IWN_CCK_STATE_HIFA; 5978 /* Set initial correlation values. */ 5979 calib->ofdm_x1 = sc->limits->min_ofdm_x1; 5980 calib->ofdm_mrc_x1 = sc->limits->min_ofdm_mrc_x1; 5981 calib->ofdm_x4 = sc->limits->min_ofdm_x4; 5982 calib->ofdm_mrc_x4 = sc->limits->min_ofdm_mrc_x4; 5983 calib->cck_x4 = 125; 5984 calib->cck_mrc_x4 = sc->limits->min_cck_mrc_x4; 5985 calib->energy_cck = sc->limits->energy_cck; 5986 5987 /* Write initial sensitivity. */ 5988 if ((error = iwn_send_sensitivity(sc)) != 0) 5989 return error; 5990 5991 /* Write initial gains. */ 5992 if ((error = ops->init_gains(sc)) != 0) 5993 return error; 5994 5995 /* Request statistics at each beacon interval. */ 5996 flags = 0; 5997 DPRINTF(sc, IWN_DEBUG_CALIBRATE, "%s: sending request for statistics\n", 5998 __func__); 5999 return iwn_cmd(sc, IWN_CMD_GET_STATISTICS, &flags, sizeof flags, 1); 6000 } 6001 6002 /* 6003 * Collect noise and RSSI statistics for the first 20 beacons received 6004 * after association and use them to determine connected antennas and 6005 * to set differential gains. 6006 */ 6007 static void 6008 iwn_collect_noise(struct iwn_softc *sc, 6009 const struct iwn_rx_general_stats *stats) 6010 { 6011 struct iwn_ops *ops = &sc->ops; 6012 struct iwn_calib_state *calib = &sc->calib; 6013 struct ieee80211com *ic = &sc->sc_ic; 6014 uint32_t val; 6015 int i; 6016 6017 DPRINTF(sc, IWN_DEBUG_TRACE, "->%s begin\n", __func__); 6018 6019 /* Accumulate RSSI and noise for all 3 antennas. */ 6020 for (i = 0; i < 3; i++) { 6021 calib->rssi[i] += le32toh(stats->rssi[i]) & 0xff; 6022 calib->noise[i] += le32toh(stats->noise[i]) & 0xff; 6023 } 6024 /* NB: We update differential gains only once after 20 beacons. */ 6025 if (++calib->nbeacons < 20) 6026 return; 6027 6028 /* Determine highest average RSSI. */ 6029 val = MAX(calib->rssi[0], calib->rssi[1]); 6030 val = MAX(calib->rssi[2], val); 6031 6032 /* Determine which antennas are connected. */ 6033 sc->chainmask = sc->rxchainmask; 6034 for (i = 0; i < 3; i++) 6035 if (val - calib->rssi[i] > 15 * 20) 6036 sc->chainmask &= ~(1 << i); 6037 DPRINTF(sc, IWN_DEBUG_CALIBRATE | IWN_DEBUG_XMIT, 6038 "%s: RX chains mask: theoretical=0x%x, actual=0x%x\n", 6039 __func__, sc->rxchainmask, sc->chainmask); 6040 6041 /* If none of the TX antennas are connected, keep at least one. */ 6042 if ((sc->chainmask & sc->txchainmask) == 0) 6043 sc->chainmask |= IWN_LSB(sc->txchainmask); 6044 6045 (void)ops->set_gains(sc); 6046 calib->state = IWN_CALIB_STATE_RUN; 6047 6048 #ifdef notyet 6049 /* XXX Disable RX chains with no antennas connected. */ 6050 sc->rxon->rxchain = htole16(IWN_RXCHAIN_SEL(sc->chainmask)); 6051 if (sc->sc_is_scanning) 6052 device_printf(sc->sc_dev, 6053 "%s: is_scanning set, before RXON\n", 6054 __func__); 6055 (void)iwn_cmd(sc, IWN_CMD_RXON, sc->rxon, sc->rxonsz, 1); 6056 #endif 6057 6058 /* Enable power-saving mode if requested by user. */ 6059 if (ic->ic_flags & IEEE80211_F_PMGTON) 6060 (void)iwn_set_pslevel(sc, 0, 3, 1); 6061 6062 DPRINTF(sc, IWN_DEBUG_TRACE, "->%s: end\n",__func__); 6063 6064 } 6065 6066 static int 6067 iwn4965_init_gains(struct iwn_softc *sc) 6068 { 6069 struct iwn_phy_calib_gain cmd; 6070 6071 DPRINTF(sc, IWN_DEBUG_TRACE, "->Doing %s\n", __func__); 6072 6073 memset(&cmd, 0, sizeof cmd); 6074 cmd.code = IWN4965_PHY_CALIB_DIFF_GAIN; 6075 /* Differential gains initially set to 0 for all 3 antennas. */ 6076 DPRINTF(sc, IWN_DEBUG_CALIBRATE, 6077 "%s: setting initial differential gains\n", __func__); 6078 return iwn_cmd(sc, IWN_CMD_PHY_CALIB, &cmd, sizeof cmd, 1); 6079 } 6080 6081 static int 6082 iwn5000_init_gains(struct iwn_softc *sc) 6083 { 6084 struct iwn_phy_calib cmd; 6085 6086 DPRINTF(sc, IWN_DEBUG_TRACE, "->Doing %s\n", __func__); 6087 6088 memset(&cmd, 0, sizeof cmd); 6089 cmd.code = sc->reset_noise_gain; 6090 cmd.ngroups = 1; 6091 cmd.isvalid = 1; 6092 DPRINTF(sc, IWN_DEBUG_CALIBRATE, 6093 "%s: setting initial differential gains\n", __func__); 6094 return iwn_cmd(sc, IWN_CMD_PHY_CALIB, &cmd, sizeof cmd, 1); 6095 } 6096 6097 static int 6098 iwn4965_set_gains(struct iwn_softc *sc) 6099 { 6100 struct iwn_calib_state *calib = &sc->calib; 6101 struct iwn_phy_calib_gain cmd; 6102 int i, delta, noise; 6103 6104 DPRINTF(sc, IWN_DEBUG_TRACE, "->Doing %s\n", __func__); 6105 6106 /* Get minimal noise among connected antennas. */ 6107 noise = INT_MAX; /* NB: There's at least one antenna. */ 6108 for (i = 0; i < 3; i++) 6109 if (sc->chainmask & (1 << i)) 6110 noise = MIN(calib->noise[i], noise); 6111 6112 memset(&cmd, 0, sizeof cmd); 6113 cmd.code = IWN4965_PHY_CALIB_DIFF_GAIN; 6114 /* Set differential gains for connected antennas. */ 6115 for (i = 0; i < 3; i++) { 6116 if (sc->chainmask & (1 << i)) { 6117 /* Compute attenuation (in unit of 1.5dB). */ 6118 delta = (noise - (int32_t)calib->noise[i]) / 30; 6119 /* NB: delta <= 0 */ 6120 /* Limit to [-4.5dB,0]. */ 6121 cmd.gain[i] = MIN(abs(delta), 3); 6122 if (delta < 0) 6123 cmd.gain[i] |= 1 << 2; /* sign bit */ 6124 } 6125 } 6126 DPRINTF(sc, IWN_DEBUG_CALIBRATE, 6127 "setting differential gains Ant A/B/C: %x/%x/%x (%x)\n", 6128 cmd.gain[0], cmd.gain[1], cmd.gain[2], sc->chainmask); 6129 return iwn_cmd(sc, IWN_CMD_PHY_CALIB, &cmd, sizeof cmd, 1); 6130 } 6131 6132 static int 6133 iwn5000_set_gains(struct iwn_softc *sc) 6134 { 6135 struct iwn_calib_state *calib = &sc->calib; 6136 struct iwn_phy_calib_gain cmd; 6137 int i, ant, div, delta; 6138 6139 DPRINTF(sc, IWN_DEBUG_TRACE, "->Doing %s\n", __func__); 6140 6141 /* We collected 20 beacons and !=6050 need a 1.5 factor. */ 6142 div = (sc->hw_type == IWN_HW_REV_TYPE_6050) ? 20 : 30; 6143 6144 memset(&cmd, 0, sizeof cmd); 6145 cmd.code = sc->noise_gain; 6146 cmd.ngroups = 1; 6147 cmd.isvalid = 1; 6148 /* Get first available RX antenna as referential. */ 6149 ant = IWN_LSB(sc->rxchainmask); 6150 /* Set differential gains for other antennas. */ 6151 for (i = ant + 1; i < 3; i++) { 6152 if (sc->chainmask & (1 << i)) { 6153 /* The delta is relative to antenna "ant". */ 6154 delta = ((int32_t)calib->noise[ant] - 6155 (int32_t)calib->noise[i]) / div; 6156 /* Limit to [-4.5dB,+4.5dB]. */ 6157 cmd.gain[i - 1] = MIN(abs(delta), 3); 6158 if (delta < 0) 6159 cmd.gain[i - 1] |= 1 << 2; /* sign bit */ 6160 } 6161 } 6162 DPRINTF(sc, IWN_DEBUG_CALIBRATE | IWN_DEBUG_XMIT, 6163 "setting differential gains Ant B/C: %x/%x (%x)\n", 6164 cmd.gain[0], cmd.gain[1], sc->chainmask); 6165 return iwn_cmd(sc, IWN_CMD_PHY_CALIB, &cmd, sizeof cmd, 1); 6166 } 6167 6168 /* 6169 * Tune RF RX sensitivity based on the number of false alarms detected 6170 * during the last beacon period. 6171 */ 6172 static void 6173 iwn_tune_sensitivity(struct iwn_softc *sc, const struct iwn_rx_stats *stats) 6174 { 6175 #define inc(val, inc, max) \ 6176 if ((val) < (max)) { \ 6177 if ((val) < (max) - (inc)) \ 6178 (val) += (inc); \ 6179 else \ 6180 (val) = (max); \ 6181 needs_update = 1; \ 6182 } 6183 #define dec(val, dec, min) \ 6184 if ((val) > (min)) { \ 6185 if ((val) > (min) + (dec)) \ 6186 (val) -= (dec); \ 6187 else \ 6188 (val) = (min); \ 6189 needs_update = 1; \ 6190 } 6191 6192 const struct iwn_sensitivity_limits *limits = sc->limits; 6193 struct iwn_calib_state *calib = &sc->calib; 6194 uint32_t val, rxena, fa; 6195 uint32_t energy[3], energy_min; 6196 uint8_t noise[3], noise_ref; 6197 int i, needs_update = 0; 6198 6199 DPRINTF(sc, IWN_DEBUG_TRACE, "->%s begin\n", __func__); 6200 6201 /* Check that we've been enabled long enough. */ 6202 if ((rxena = le32toh(stats->general.load)) == 0){ 6203 DPRINTF(sc, IWN_DEBUG_TRACE, "->%s end not so long\n", __func__); 6204 return; 6205 } 6206 6207 /* Compute number of false alarms since last call for OFDM. */ 6208 fa = le32toh(stats->ofdm.bad_plcp) - calib->bad_plcp_ofdm; 6209 fa += le32toh(stats->ofdm.fa) - calib->fa_ofdm; 6210 fa *= 200 * IEEE80211_DUR_TU; /* 200TU */ 6211 6212 if (fa > 50 * rxena) { 6213 /* High false alarm count, decrease sensitivity. */ 6214 DPRINTF(sc, IWN_DEBUG_CALIBRATE, 6215 "%s: OFDM high false alarm count: %u\n", __func__, fa); 6216 inc(calib->ofdm_x1, 1, limits->max_ofdm_x1); 6217 inc(calib->ofdm_mrc_x1, 1, limits->max_ofdm_mrc_x1); 6218 inc(calib->ofdm_x4, 1, limits->max_ofdm_x4); 6219 inc(calib->ofdm_mrc_x4, 1, limits->max_ofdm_mrc_x4); 6220 6221 } else if (fa < 5 * rxena) { 6222 /* Low false alarm count, increase sensitivity. */ 6223 DPRINTF(sc, IWN_DEBUG_CALIBRATE, 6224 "%s: OFDM low false alarm count: %u\n", __func__, fa); 6225 dec(calib->ofdm_x1, 1, limits->min_ofdm_x1); 6226 dec(calib->ofdm_mrc_x1, 1, limits->min_ofdm_mrc_x1); 6227 dec(calib->ofdm_x4, 1, limits->min_ofdm_x4); 6228 dec(calib->ofdm_mrc_x4, 1, limits->min_ofdm_mrc_x4); 6229 } 6230 6231 /* Compute maximum noise among 3 receivers. */ 6232 for (i = 0; i < 3; i++) 6233 noise[i] = (le32toh(stats->general.noise[i]) >> 8) & 0xff; 6234 val = MAX(noise[0], noise[1]); 6235 val = MAX(noise[2], val); 6236 /* Insert it into our samples table. */ 6237 calib->noise_samples[calib->cur_noise_sample] = val; 6238 calib->cur_noise_sample = (calib->cur_noise_sample + 1) % 20; 6239 6240 /* Compute maximum noise among last 20 samples. */ 6241 noise_ref = calib->noise_samples[0]; 6242 for (i = 1; i < 20; i++) 6243 noise_ref = MAX(noise_ref, calib->noise_samples[i]); 6244 6245 /* Compute maximum energy among 3 receivers. */ 6246 for (i = 0; i < 3; i++) 6247 energy[i] = le32toh(stats->general.energy[i]); 6248 val = MIN(energy[0], energy[1]); 6249 val = MIN(energy[2], val); 6250 /* Insert it into our samples table. */ 6251 calib->energy_samples[calib->cur_energy_sample] = val; 6252 calib->cur_energy_sample = (calib->cur_energy_sample + 1) % 10; 6253 6254 /* Compute minimum energy among last 10 samples. */ 6255 energy_min = calib->energy_samples[0]; 6256 for (i = 1; i < 10; i++) 6257 energy_min = MAX(energy_min, calib->energy_samples[i]); 6258 energy_min += 6; 6259 6260 /* Compute number of false alarms since last call for CCK. */ 6261 fa = le32toh(stats->cck.bad_plcp) - calib->bad_plcp_cck; 6262 fa += le32toh(stats->cck.fa) - calib->fa_cck; 6263 fa *= 200 * IEEE80211_DUR_TU; /* 200TU */ 6264 6265 if (fa > 50 * rxena) { 6266 /* High false alarm count, decrease sensitivity. */ 6267 DPRINTF(sc, IWN_DEBUG_CALIBRATE, 6268 "%s: CCK high false alarm count: %u\n", __func__, fa); 6269 calib->cck_state = IWN_CCK_STATE_HIFA; 6270 calib->low_fa = 0; 6271 6272 if (calib->cck_x4 > 160) { 6273 calib->noise_ref = noise_ref; 6274 if (calib->energy_cck > 2) 6275 dec(calib->energy_cck, 2, energy_min); 6276 } 6277 if (calib->cck_x4 < 160) { 6278 calib->cck_x4 = 161; 6279 needs_update = 1; 6280 } else 6281 inc(calib->cck_x4, 3, limits->max_cck_x4); 6282 6283 inc(calib->cck_mrc_x4, 3, limits->max_cck_mrc_x4); 6284 6285 } else if (fa < 5 * rxena) { 6286 /* Low false alarm count, increase sensitivity. */ 6287 DPRINTF(sc, IWN_DEBUG_CALIBRATE, 6288 "%s: CCK low false alarm count: %u\n", __func__, fa); 6289 calib->cck_state = IWN_CCK_STATE_LOFA; 6290 calib->low_fa++; 6291 6292 if (calib->cck_state != IWN_CCK_STATE_INIT && 6293 (((int32_t)calib->noise_ref - (int32_t)noise_ref) > 2 || 6294 calib->low_fa > 100)) { 6295 inc(calib->energy_cck, 2, limits->min_energy_cck); 6296 dec(calib->cck_x4, 3, limits->min_cck_x4); 6297 dec(calib->cck_mrc_x4, 3, limits->min_cck_mrc_x4); 6298 } 6299 } else { 6300 /* Not worth to increase or decrease sensitivity. */ 6301 DPRINTF(sc, IWN_DEBUG_CALIBRATE, 6302 "%s: CCK normal false alarm count: %u\n", __func__, fa); 6303 calib->low_fa = 0; 6304 calib->noise_ref = noise_ref; 6305 6306 if (calib->cck_state == IWN_CCK_STATE_HIFA) { 6307 /* Previous interval had many false alarms. */ 6308 dec(calib->energy_cck, 8, energy_min); 6309 } 6310 calib->cck_state = IWN_CCK_STATE_INIT; 6311 } 6312 6313 if (needs_update) 6314 (void)iwn_send_sensitivity(sc); 6315 6316 DPRINTF(sc, IWN_DEBUG_TRACE, "->%s: end\n",__func__); 6317 6318 #undef dec 6319 #undef inc 6320 } 6321 6322 static int 6323 iwn_send_sensitivity(struct iwn_softc *sc) 6324 { 6325 struct iwn_calib_state *calib = &sc->calib; 6326 struct iwn_enhanced_sensitivity_cmd cmd; 6327 int len; 6328 6329 memset(&cmd, 0, sizeof cmd); 6330 len = sizeof (struct iwn_sensitivity_cmd); 6331 cmd.which = IWN_SENSITIVITY_WORKTBL; 6332 /* OFDM modulation. */ 6333 cmd.corr_ofdm_x1 = htole16(calib->ofdm_x1); 6334 cmd.corr_ofdm_mrc_x1 = htole16(calib->ofdm_mrc_x1); 6335 cmd.corr_ofdm_x4 = htole16(calib->ofdm_x4); 6336 cmd.corr_ofdm_mrc_x4 = htole16(calib->ofdm_mrc_x4); 6337 cmd.energy_ofdm = htole16(sc->limits->energy_ofdm); 6338 cmd.energy_ofdm_th = htole16(62); 6339 /* CCK modulation. */ 6340 cmd.corr_cck_x4 = htole16(calib->cck_x4); 6341 cmd.corr_cck_mrc_x4 = htole16(calib->cck_mrc_x4); 6342 cmd.energy_cck = htole16(calib->energy_cck); 6343 /* Barker modulation: use default values. */ 6344 cmd.corr_barker = htole16(190); 6345 cmd.corr_barker_mrc = htole16(sc->limits->barker_mrc); 6346 6347 DPRINTF(sc, IWN_DEBUG_CALIBRATE, 6348 "%s: set sensitivity %d/%d/%d/%d/%d/%d/%d\n", __func__, 6349 calib->ofdm_x1, calib->ofdm_mrc_x1, calib->ofdm_x4, 6350 calib->ofdm_mrc_x4, calib->cck_x4, 6351 calib->cck_mrc_x4, calib->energy_cck); 6352 6353 if (!(sc->sc_flags & IWN_FLAG_ENH_SENS)) 6354 goto send; 6355 /* Enhanced sensitivity settings. */ 6356 len = sizeof (struct iwn_enhanced_sensitivity_cmd); 6357 cmd.ofdm_det_slope_mrc = htole16(668); 6358 cmd.ofdm_det_icept_mrc = htole16(4); 6359 cmd.ofdm_det_slope = htole16(486); 6360 cmd.ofdm_det_icept = htole16(37); 6361 cmd.cck_det_slope_mrc = htole16(853); 6362 cmd.cck_det_icept_mrc = htole16(4); 6363 cmd.cck_det_slope = htole16(476); 6364 cmd.cck_det_icept = htole16(99); 6365 send: 6366 return iwn_cmd(sc, IWN_CMD_SET_SENSITIVITY, &cmd, len, 1); 6367 } 6368 6369 /* 6370 * Look at the increase of PLCP errors over time; if it exceeds 6371 * a programmed threshold then trigger an RF retune. 6372 */ 6373 static void 6374 iwn_check_rx_recovery(struct iwn_softc *sc, struct iwn_stats *rs) 6375 { 6376 int32_t delta_ofdm, delta_ht, delta_cck; 6377 struct iwn_calib_state *calib = &sc->calib; 6378 int delta_ticks, cur_ticks; 6379 int delta_msec; 6380 int thresh; 6381 6382 /* 6383 * Calculate the difference between the current and 6384 * previous statistics. 6385 */ 6386 delta_cck = le32toh(rs->rx.cck.bad_plcp) - calib->bad_plcp_cck; 6387 delta_ofdm = le32toh(rs->rx.ofdm.bad_plcp) - calib->bad_plcp_ofdm; 6388 delta_ht = le32toh(rs->rx.ht.bad_plcp) - calib->bad_plcp_ht; 6389 6390 /* 6391 * Calculate the delta in time between successive statistics 6392 * messages. Yes, it can roll over; so we make sure that 6393 * this doesn't happen. 6394 * 6395 * XXX go figure out what to do about rollover 6396 * XXX go figure out what to do if ticks rolls over to -ve instead! 6397 * XXX go stab signed integer overflow undefined-ness in the face. 6398 */ 6399 cur_ticks = ticks; 6400 delta_ticks = cur_ticks - sc->last_calib_ticks; 6401 6402 /* 6403 * If any are negative, then the firmware likely reset; so just 6404 * bail. We'll pick this up next time. 6405 */ 6406 if (delta_cck < 0 || delta_ofdm < 0 || delta_ht < 0 || delta_ticks < 0) 6407 return; 6408 6409 /* 6410 * delta_ticks is in ticks; we need to convert it up to milliseconds 6411 * so we can do some useful math with it. 6412 */ 6413 delta_msec = ticks_to_msecs(delta_ticks); 6414 6415 /* 6416 * Calculate what our threshold is given the current delta_msec. 6417 */ 6418 thresh = sc->base_params->plcp_err_threshold * delta_msec; 6419 6420 DPRINTF(sc, IWN_DEBUG_STATE, 6421 "%s: time delta: %d; cck=%d, ofdm=%d, ht=%d, total=%d, thresh=%d\n", 6422 __func__, 6423 delta_msec, 6424 delta_cck, 6425 delta_ofdm, 6426 delta_ht, 6427 (delta_msec + delta_cck + delta_ofdm + delta_ht), 6428 thresh); 6429 6430 /* 6431 * If we need a retune, then schedule a single channel scan 6432 * to a channel that isn't the currently active one! 6433 * 6434 * The math from linux iwlwifi: 6435 * 6436 * if ((delta * 100 / msecs) > threshold) 6437 */ 6438 if (thresh > 0 && (delta_cck + delta_ofdm + delta_ht) * 100 > thresh) { 6439 DPRINTF(sc, IWN_DEBUG_ANY, 6440 "%s: PLCP error threshold raw (%d) comparison (%d) " 6441 "over limit (%d); retune!\n", 6442 __func__, 6443 (delta_cck + delta_ofdm + delta_ht), 6444 (delta_cck + delta_ofdm + delta_ht) * 100, 6445 thresh); 6446 } 6447 } 6448 6449 /* 6450 * Set STA mode power saving level (between 0 and 5). 6451 * Level 0 is CAM (Continuously Aware Mode), 5 is for maximum power saving. 6452 */ 6453 static int 6454 iwn_set_pslevel(struct iwn_softc *sc, int dtim, int level, int async) 6455 { 6456 struct iwn_pmgt_cmd cmd; 6457 const struct iwn_pmgt *pmgt; 6458 uint32_t max, skip_dtim; 6459 uint32_t reg; 6460 int i; 6461 6462 DPRINTF(sc, IWN_DEBUG_PWRSAVE, 6463 "%s: dtim=%d, level=%d, async=%d\n", 6464 __func__, 6465 dtim, 6466 level, 6467 async); 6468 6469 /* Select which PS parameters to use. */ 6470 if (dtim <= 2) 6471 pmgt = &iwn_pmgt[0][level]; 6472 else if (dtim <= 10) 6473 pmgt = &iwn_pmgt[1][level]; 6474 else 6475 pmgt = &iwn_pmgt[2][level]; 6476 6477 memset(&cmd, 0, sizeof cmd); 6478 if (level != 0) /* not CAM */ 6479 cmd.flags |= htole16(IWN_PS_ALLOW_SLEEP); 6480 if (level == 5) 6481 cmd.flags |= htole16(IWN_PS_FAST_PD); 6482 /* Retrieve PCIe Active State Power Management (ASPM). */ 6483 reg = pci_read_config(sc->sc_dev, sc->sc_cap_off + PCIER_LINK_CTL, 4); 6484 if (!(reg & PCIEM_LINK_CTL_ASPMC_L0S)) /* L0s Entry disabled. */ 6485 cmd.flags |= htole16(IWN_PS_PCI_PMGT); 6486 cmd.rxtimeout = htole32(pmgt->rxtimeout * 1024); 6487 cmd.txtimeout = htole32(pmgt->txtimeout * 1024); 6488 6489 if (dtim == 0) { 6490 dtim = 1; 6491 skip_dtim = 0; 6492 } else 6493 skip_dtim = pmgt->skip_dtim; 6494 if (skip_dtim != 0) { 6495 cmd.flags |= htole16(IWN_PS_SLEEP_OVER_DTIM); 6496 max = pmgt->intval[4]; 6497 if (max == (uint32_t)-1) 6498 max = dtim * (skip_dtim + 1); 6499 else if (max > dtim) 6500 max = rounddown(max, dtim); 6501 } else 6502 max = dtim; 6503 for (i = 0; i < 5; i++) 6504 cmd.intval[i] = htole32(MIN(max, pmgt->intval[i])); 6505 6506 DPRINTF(sc, IWN_DEBUG_RESET, "setting power saving level to %d\n", 6507 level); 6508 return iwn_cmd(sc, IWN_CMD_SET_POWER_MODE, &cmd, sizeof cmd, async); 6509 } 6510 6511 static int 6512 iwn_send_btcoex(struct iwn_softc *sc) 6513 { 6514 struct iwn_bluetooth cmd; 6515 6516 memset(&cmd, 0, sizeof cmd); 6517 cmd.flags = IWN_BT_COEX_CHAN_ANN | IWN_BT_COEX_BT_PRIO; 6518 cmd.lead_time = IWN_BT_LEAD_TIME_DEF; 6519 cmd.max_kill = IWN_BT_MAX_KILL_DEF; 6520 DPRINTF(sc, IWN_DEBUG_RESET, "%s: configuring bluetooth coexistence\n", 6521 __func__); 6522 return iwn_cmd(sc, IWN_CMD_BT_COEX, &cmd, sizeof(cmd), 0); 6523 } 6524 6525 static int 6526 iwn_send_advanced_btcoex(struct iwn_softc *sc) 6527 { 6528 static const uint32_t btcoex_3wire[12] = { 6529 0xaaaaaaaa, 0xaaaaaaaa, 0xaeaaaaaa, 0xaaaaaaaa, 6530 0xcc00ff28, 0x0000aaaa, 0xcc00aaaa, 0x0000aaaa, 6531 0xc0004000, 0x00004000, 0xf0005000, 0xf0005000, 6532 }; 6533 struct iwn6000_btcoex_config btconfig; 6534 struct iwn2000_btcoex_config btconfig2k; 6535 struct iwn_btcoex_priotable btprio; 6536 struct iwn_btcoex_prot btprot; 6537 int error, i; 6538 uint8_t flags; 6539 6540 memset(&btconfig, 0, sizeof btconfig); 6541 memset(&btconfig2k, 0, sizeof btconfig2k); 6542 6543 flags = IWN_BT_FLAG_COEX6000_MODE_3W << 6544 IWN_BT_FLAG_COEX6000_MODE_SHIFT; // Done as is in linux kernel 3.2 6545 6546 if (sc->base_params->bt_sco_disable) 6547 flags &= ~IWN_BT_FLAG_SYNC_2_BT_DISABLE; 6548 else 6549 flags |= IWN_BT_FLAG_SYNC_2_BT_DISABLE; 6550 6551 flags |= IWN_BT_FLAG_COEX6000_CHAN_INHIBITION; 6552 6553 /* Default flags result is 145 as old value */ 6554 6555 /* 6556 * Flags value has to be review. Values must change if we 6557 * which to disable it 6558 */ 6559 if (sc->base_params->bt_session_2) { 6560 btconfig2k.flags = flags; 6561 btconfig2k.max_kill = 5; 6562 btconfig2k.bt3_t7_timer = 1; 6563 btconfig2k.kill_ack = htole32(0xffff0000); 6564 btconfig2k.kill_cts = htole32(0xffff0000); 6565 btconfig2k.sample_time = 2; 6566 btconfig2k.bt3_t2_timer = 0xc; 6567 6568 for (i = 0; i < 12; i++) 6569 btconfig2k.lookup_table[i] = htole32(btcoex_3wire[i]); 6570 btconfig2k.valid = htole16(0xff); 6571 btconfig2k.prio_boost = htole32(0xf0); 6572 DPRINTF(sc, IWN_DEBUG_RESET, 6573 "%s: configuring advanced bluetooth coexistence" 6574 " session 2, flags : 0x%x\n", 6575 __func__, 6576 flags); 6577 error = iwn_cmd(sc, IWN_CMD_BT_COEX, &btconfig2k, 6578 sizeof(btconfig2k), 1); 6579 } else { 6580 btconfig.flags = flags; 6581 btconfig.max_kill = 5; 6582 btconfig.bt3_t7_timer = 1; 6583 btconfig.kill_ack = htole32(0xffff0000); 6584 btconfig.kill_cts = htole32(0xffff0000); 6585 btconfig.sample_time = 2; 6586 btconfig.bt3_t2_timer = 0xc; 6587 6588 for (i = 0; i < 12; i++) 6589 btconfig.lookup_table[i] = htole32(btcoex_3wire[i]); 6590 btconfig.valid = htole16(0xff); 6591 btconfig.prio_boost = 0xf0; 6592 DPRINTF(sc, IWN_DEBUG_RESET, 6593 "%s: configuring advanced bluetooth coexistence," 6594 " flags : 0x%x\n", 6595 __func__, 6596 flags); 6597 error = iwn_cmd(sc, IWN_CMD_BT_COEX, &btconfig, 6598 sizeof(btconfig), 1); 6599 } 6600 6601 if (error != 0) 6602 return error; 6603 6604 memset(&btprio, 0, sizeof btprio); 6605 btprio.calib_init1 = 0x6; 6606 btprio.calib_init2 = 0x7; 6607 btprio.calib_periodic_low1 = 0x2; 6608 btprio.calib_periodic_low2 = 0x3; 6609 btprio.calib_periodic_high1 = 0x4; 6610 btprio.calib_periodic_high2 = 0x5; 6611 btprio.dtim = 0x6; 6612 btprio.scan52 = 0x8; 6613 btprio.scan24 = 0xa; 6614 error = iwn_cmd(sc, IWN_CMD_BT_COEX_PRIOTABLE, &btprio, sizeof(btprio), 6615 1); 6616 if (error != 0) 6617 return error; 6618 6619 /* Force BT state machine change. */ 6620 memset(&btprot, 0, sizeof btprot); 6621 btprot.open = 1; 6622 btprot.type = 1; 6623 error = iwn_cmd(sc, IWN_CMD_BT_COEX_PROT, &btprot, sizeof(btprot), 1); 6624 if (error != 0) 6625 return error; 6626 btprot.open = 0; 6627 return iwn_cmd(sc, IWN_CMD_BT_COEX_PROT, &btprot, sizeof(btprot), 1); 6628 } 6629 6630 static int 6631 iwn5000_runtime_calib(struct iwn_softc *sc) 6632 { 6633 struct iwn5000_calib_config cmd; 6634 6635 memset(&cmd, 0, sizeof cmd); 6636 cmd.ucode.once.enable = 0xffffffff; 6637 cmd.ucode.once.start = IWN5000_CALIB_DC; 6638 DPRINTF(sc, IWN_DEBUG_CALIBRATE, 6639 "%s: configuring runtime calibration\n", __func__); 6640 return iwn_cmd(sc, IWN5000_CMD_CALIB_CONFIG, &cmd, sizeof(cmd), 0); 6641 } 6642 6643 static uint32_t 6644 iwn_get_rxon_ht_flags(struct iwn_softc *sc, struct ieee80211vap *vap, 6645 struct ieee80211_channel *c) 6646 { 6647 uint32_t htflags = 0; 6648 6649 if (! IEEE80211_IS_CHAN_HT(c)) 6650 return (0); 6651 6652 htflags |= IWN_RXON_HT_PROTMODE(vap->iv_curhtprotmode); 6653 6654 if (IEEE80211_IS_CHAN_HT40(c)) { 6655 switch (vap->iv_curhtprotmode) { 6656 case IEEE80211_HTINFO_OPMODE_HT20PR: 6657 htflags |= IWN_RXON_HT_MODEPURE40; 6658 break; 6659 default: 6660 htflags |= IWN_RXON_HT_MODEMIXED; 6661 break; 6662 } 6663 } 6664 if (IEEE80211_IS_CHAN_HT40D(c)) 6665 htflags |= IWN_RXON_HT_HT40MINUS; 6666 6667 return (htflags); 6668 } 6669 6670 static int 6671 iwn_check_bss_filter(struct iwn_softc *sc) 6672 { 6673 return ((sc->rxon->filter & htole32(IWN_FILTER_BSS)) != 0); 6674 } 6675 6676 static int 6677 iwn4965_rxon_assoc(struct iwn_softc *sc, int async) 6678 { 6679 struct iwn4965_rxon_assoc cmd; 6680 struct iwn_rxon *rxon = sc->rxon; 6681 6682 cmd.flags = rxon->flags; 6683 cmd.filter = rxon->filter; 6684 cmd.ofdm_mask = rxon->ofdm_mask; 6685 cmd.cck_mask = rxon->cck_mask; 6686 cmd.ht_single_mask = rxon->ht_single_mask; 6687 cmd.ht_dual_mask = rxon->ht_dual_mask; 6688 cmd.rxchain = rxon->rxchain; 6689 cmd.reserved = 0; 6690 6691 return (iwn_cmd(sc, IWN_CMD_RXON_ASSOC, &cmd, sizeof(cmd), async)); 6692 } 6693 6694 static int 6695 iwn5000_rxon_assoc(struct iwn_softc *sc, int async) 6696 { 6697 struct iwn5000_rxon_assoc cmd; 6698 struct iwn_rxon *rxon = sc->rxon; 6699 6700 cmd.flags = rxon->flags; 6701 cmd.filter = rxon->filter; 6702 cmd.ofdm_mask = rxon->ofdm_mask; 6703 cmd.cck_mask = rxon->cck_mask; 6704 cmd.reserved1 = 0; 6705 cmd.ht_single_mask = rxon->ht_single_mask; 6706 cmd.ht_dual_mask = rxon->ht_dual_mask; 6707 cmd.ht_triple_mask = rxon->ht_triple_mask; 6708 cmd.reserved2 = 0; 6709 cmd.rxchain = rxon->rxchain; 6710 cmd.acquisition = rxon->acquisition; 6711 cmd.reserved3 = 0; 6712 6713 return (iwn_cmd(sc, IWN_CMD_RXON_ASSOC, &cmd, sizeof(cmd), async)); 6714 } 6715 6716 static int 6717 iwn_send_rxon(struct iwn_softc *sc, int assoc, int async) 6718 { 6719 struct iwn_ops *ops = &sc->ops; 6720 int error; 6721 6722 IWN_LOCK_ASSERT(sc); 6723 6724 if (assoc && iwn_check_bss_filter(sc) != 0) { 6725 error = ops->rxon_assoc(sc, async); 6726 if (error != 0) { 6727 device_printf(sc->sc_dev, 6728 "%s: RXON_ASSOC command failed, error %d\n", 6729 __func__, error); 6730 return (error); 6731 } 6732 } else { 6733 if (sc->sc_is_scanning) 6734 device_printf(sc->sc_dev, 6735 "%s: is_scanning set, before RXON\n", 6736 __func__); 6737 6738 error = iwn_cmd(sc, IWN_CMD_RXON, sc->rxon, sc->rxonsz, async); 6739 if (error != 0) { 6740 device_printf(sc->sc_dev, 6741 "%s: RXON command failed, error %d\n", 6742 __func__, error); 6743 return (error); 6744 } 6745 6746 /* 6747 * Reconfiguring RXON clears the firmware nodes table so 6748 * we must add the broadcast node again. 6749 */ 6750 if (iwn_check_bss_filter(sc) == 0 && 6751 (error = iwn_add_broadcast_node(sc, async)) != 0) { 6752 device_printf(sc->sc_dev, 6753 "%s: could not add broadcast node, error %d\n", 6754 __func__, error); 6755 return (error); 6756 } 6757 } 6758 6759 /* Configuration has changed, set TX power accordingly. */ 6760 if ((error = ops->set_txpower(sc, async)) != 0) { 6761 device_printf(sc->sc_dev, 6762 "%s: could not set TX power, error %d\n", 6763 __func__, error); 6764 return (error); 6765 } 6766 6767 return (0); 6768 } 6769 6770 static int 6771 iwn_config(struct iwn_softc *sc) 6772 { 6773 struct ieee80211com *ic = &sc->sc_ic; 6774 struct ieee80211vap *vap = TAILQ_FIRST(&ic->ic_vaps); 6775 const uint8_t *macaddr; 6776 uint32_t txmask; 6777 uint16_t rxchain; 6778 int error; 6779 6780 DPRINTF(sc, IWN_DEBUG_TRACE, "->%s begin\n", __func__); 6781 6782 if ((sc->base_params->calib_need & IWN_FLG_NEED_PHY_CALIB_TEMP_OFFSET) 6783 && (sc->base_params->calib_need & IWN_FLG_NEED_PHY_CALIB_TEMP_OFFSETv2)) { 6784 device_printf(sc->sc_dev,"%s: temp_offset and temp_offsetv2 are" 6785 " exclusive each together. Review NIC config file. Conf" 6786 " : 0x%08x Flags : 0x%08x \n", __func__, 6787 sc->base_params->calib_need, 6788 (IWN_FLG_NEED_PHY_CALIB_TEMP_OFFSET | 6789 IWN_FLG_NEED_PHY_CALIB_TEMP_OFFSETv2)); 6790 return (EINVAL); 6791 } 6792 6793 /* Compute temperature calib if needed. Will be send by send calib */ 6794 if (sc->base_params->calib_need & IWN_FLG_NEED_PHY_CALIB_TEMP_OFFSET) { 6795 error = iwn5000_temp_offset_calib(sc); 6796 if (error != 0) { 6797 device_printf(sc->sc_dev, 6798 "%s: could not set temperature offset\n", __func__); 6799 return (error); 6800 } 6801 } else if (sc->base_params->calib_need & IWN_FLG_NEED_PHY_CALIB_TEMP_OFFSETv2) { 6802 error = iwn5000_temp_offset_calibv2(sc); 6803 if (error != 0) { 6804 device_printf(sc->sc_dev, 6805 "%s: could not compute temperature offset v2\n", 6806 __func__); 6807 return (error); 6808 } 6809 } 6810 6811 if (sc->hw_type == IWN_HW_REV_TYPE_6050) { 6812 /* Configure runtime DC calibration. */ 6813 error = iwn5000_runtime_calib(sc); 6814 if (error != 0) { 6815 device_printf(sc->sc_dev, 6816 "%s: could not configure runtime calibration\n", 6817 __func__); 6818 return error; 6819 } 6820 } 6821 6822 /* Configure valid TX chains for >=5000 Series. */ 6823 if (sc->hw_type != IWN_HW_REV_TYPE_4965 && 6824 IWN_UCODE_API(sc->ucode_rev) > 1) { 6825 txmask = htole32(sc->txchainmask); 6826 DPRINTF(sc, IWN_DEBUG_RESET | IWN_DEBUG_XMIT, 6827 "%s: configuring valid TX chains 0x%x\n", __func__, txmask); 6828 error = iwn_cmd(sc, IWN5000_CMD_TX_ANT_CONFIG, &txmask, 6829 sizeof txmask, 0); 6830 if (error != 0) { 6831 device_printf(sc->sc_dev, 6832 "%s: could not configure valid TX chains, " 6833 "error %d\n", __func__, error); 6834 return error; 6835 } 6836 } 6837 6838 /* Configure bluetooth coexistence. */ 6839 error = 0; 6840 6841 /* Configure bluetooth coexistence if needed. */ 6842 if (sc->base_params->bt_mode == IWN_BT_ADVANCED) 6843 error = iwn_send_advanced_btcoex(sc); 6844 if (sc->base_params->bt_mode == IWN_BT_SIMPLE) 6845 error = iwn_send_btcoex(sc); 6846 6847 if (error != 0) { 6848 device_printf(sc->sc_dev, 6849 "%s: could not configure bluetooth coexistence, error %d\n", 6850 __func__, error); 6851 return error; 6852 } 6853 6854 /* Set mode, channel, RX filter and enable RX. */ 6855 sc->rxon = &sc->rx_on[IWN_RXON_BSS_CTX]; 6856 memset(sc->rxon, 0, sizeof (struct iwn_rxon)); 6857 macaddr = vap ? vap->iv_myaddr : ic->ic_macaddr; 6858 IEEE80211_ADDR_COPY(sc->rxon->myaddr, macaddr); 6859 IEEE80211_ADDR_COPY(sc->rxon->wlap, macaddr); 6860 sc->rxon->chan = ieee80211_chan2ieee(ic, ic->ic_curchan); 6861 sc->rxon->flags = htole32(IWN_RXON_TSF | IWN_RXON_CTS_TO_SELF); 6862 if (IEEE80211_IS_CHAN_2GHZ(ic->ic_curchan)) 6863 sc->rxon->flags |= htole32(IWN_RXON_AUTO | IWN_RXON_24GHZ); 6864 6865 sc->rxon->filter = htole32(IWN_FILTER_MULTICAST); 6866 switch (ic->ic_opmode) { 6867 case IEEE80211_M_STA: 6868 sc->rxon->mode = IWN_MODE_STA; 6869 break; 6870 case IEEE80211_M_MONITOR: 6871 sc->rxon->mode = IWN_MODE_MONITOR; 6872 break; 6873 default: 6874 /* Should not get there. */ 6875 break; 6876 } 6877 iwn_set_promisc(sc); 6878 sc->rxon->cck_mask = 0x0f; /* not yet negotiated */ 6879 sc->rxon->ofdm_mask = 0xff; /* not yet negotiated */ 6880 sc->rxon->ht_single_mask = 0xff; 6881 sc->rxon->ht_dual_mask = 0xff; 6882 sc->rxon->ht_triple_mask = 0xff; 6883 /* 6884 * In active association mode, ensure that 6885 * all the receive chains are enabled. 6886 * 6887 * Since we're not yet doing SMPS, don't allow the 6888 * number of idle RX chains to be less than the active 6889 * number. 6890 */ 6891 rxchain = 6892 IWN_RXCHAIN_VALID(sc->rxchainmask) | 6893 IWN_RXCHAIN_MIMO_COUNT(sc->nrxchains) | 6894 IWN_RXCHAIN_IDLE_COUNT(sc->nrxchains); 6895 sc->rxon->rxchain = htole16(rxchain); 6896 DPRINTF(sc, IWN_DEBUG_RESET | IWN_DEBUG_XMIT, 6897 "%s: rxchainmask=0x%x, nrxchains=%d\n", 6898 __func__, 6899 sc->rxchainmask, 6900 sc->nrxchains); 6901 6902 sc->rxon->flags |= htole32(iwn_get_rxon_ht_flags(sc, vap, ic->ic_curchan)); 6903 6904 DPRINTF(sc, IWN_DEBUG_RESET, 6905 "%s: setting configuration; flags=0x%08x\n", 6906 __func__, le32toh(sc->rxon->flags)); 6907 if ((error = iwn_send_rxon(sc, 0, 0)) != 0) { 6908 device_printf(sc->sc_dev, "%s: could not send RXON\n", 6909 __func__); 6910 return error; 6911 } 6912 6913 if ((error = iwn_set_critical_temp(sc)) != 0) { 6914 device_printf(sc->sc_dev, 6915 "%s: could not set critical temperature\n", __func__); 6916 return error; 6917 } 6918 6919 /* Set power saving level to CAM during initialization. */ 6920 if ((error = iwn_set_pslevel(sc, 0, 0, 0)) != 0) { 6921 device_printf(sc->sc_dev, 6922 "%s: could not set power saving level\n", __func__); 6923 return error; 6924 } 6925 6926 DPRINTF(sc, IWN_DEBUG_TRACE, "->%s: end\n",__func__); 6927 6928 return 0; 6929 } 6930 6931 static uint16_t 6932 iwn_get_active_dwell_time(struct iwn_softc *sc, 6933 struct ieee80211_channel *c, uint8_t n_probes) 6934 { 6935 /* No channel? Default to 2GHz settings */ 6936 if (c == NULL || IEEE80211_IS_CHAN_2GHZ(c)) { 6937 return (IWN_ACTIVE_DWELL_TIME_2GHZ + 6938 IWN_ACTIVE_DWELL_FACTOR_2GHZ * (n_probes + 1)); 6939 } 6940 6941 /* 5GHz dwell time */ 6942 return (IWN_ACTIVE_DWELL_TIME_5GHZ + 6943 IWN_ACTIVE_DWELL_FACTOR_5GHZ * (n_probes + 1)); 6944 } 6945 6946 /* 6947 * Limit the total dwell time to 85% of the beacon interval. 6948 * 6949 * Returns the dwell time in milliseconds. 6950 */ 6951 static uint16_t 6952 iwn_limit_dwell(struct iwn_softc *sc, uint16_t dwell_time) 6953 { 6954 struct ieee80211com *ic = &sc->sc_ic; 6955 struct ieee80211vap *vap = NULL; 6956 int bintval = 0; 6957 6958 /* bintval is in TU (1.024mS) */ 6959 if (! TAILQ_EMPTY(&ic->ic_vaps)) { 6960 vap = TAILQ_FIRST(&ic->ic_vaps); 6961 bintval = vap->iv_bss->ni_intval; 6962 } 6963 6964 /* 6965 * If it's non-zero, we should calculate the minimum of 6966 * it and the DWELL_BASE. 6967 * 6968 * XXX Yes, the math should take into account that bintval 6969 * is 1.024mS, not 1mS.. 6970 */ 6971 if (bintval > 0) { 6972 DPRINTF(sc, IWN_DEBUG_SCAN, 6973 "%s: bintval=%d\n", 6974 __func__, 6975 bintval); 6976 return (MIN(IWN_PASSIVE_DWELL_BASE, ((bintval * 85) / 100))); 6977 } 6978 6979 /* No association context? Default */ 6980 return (IWN_PASSIVE_DWELL_BASE); 6981 } 6982 6983 static uint16_t 6984 iwn_get_passive_dwell_time(struct iwn_softc *sc, struct ieee80211_channel *c) 6985 { 6986 uint16_t passive; 6987 6988 if (c == NULL || IEEE80211_IS_CHAN_2GHZ(c)) { 6989 passive = IWN_PASSIVE_DWELL_BASE + IWN_PASSIVE_DWELL_TIME_2GHZ; 6990 } else { 6991 passive = IWN_PASSIVE_DWELL_BASE + IWN_PASSIVE_DWELL_TIME_5GHZ; 6992 } 6993 6994 /* Clamp to the beacon interval if we're associated */ 6995 return (iwn_limit_dwell(sc, passive)); 6996 } 6997 6998 static int 6999 iwn_scan(struct iwn_softc *sc, struct ieee80211vap *vap, 7000 struct ieee80211_scan_state *ss, struct ieee80211_channel *c) 7001 { 7002 struct ieee80211com *ic = &sc->sc_ic; 7003 struct ieee80211_node *ni = vap->iv_bss; 7004 struct iwn_scan_hdr *hdr; 7005 struct iwn_cmd_data *tx; 7006 struct iwn_scan_essid *essid; 7007 struct iwn_scan_chan *chan; 7008 struct ieee80211_frame *wh; 7009 struct ieee80211_rateset *rs; 7010 uint8_t *buf, *frm; 7011 uint16_t rxchain; 7012 uint8_t txant; 7013 int buflen, error; 7014 int is_active; 7015 uint16_t dwell_active, dwell_passive; 7016 uint32_t scan_service_time; 7017 7018 DPRINTF(sc, IWN_DEBUG_TRACE, "->%s begin\n", __func__); 7019 7020 /* 7021 * We are absolutely not allowed to send a scan command when another 7022 * scan command is pending. 7023 */ 7024 if (sc->sc_is_scanning) { 7025 device_printf(sc->sc_dev, "%s: called whilst scanning!\n", 7026 __func__); 7027 return (EAGAIN); 7028 } 7029 7030 /* Assign the scan channel */ 7031 c = ic->ic_curchan; 7032 7033 sc->rxon = &sc->rx_on[IWN_RXON_BSS_CTX]; 7034 buf = malloc(IWN_SCAN_MAXSZ, M_DEVBUF, M_NOWAIT | M_ZERO); 7035 if (buf == NULL) { 7036 device_printf(sc->sc_dev, 7037 "%s: could not allocate buffer for scan command\n", 7038 __func__); 7039 return ENOMEM; 7040 } 7041 hdr = (struct iwn_scan_hdr *)buf; 7042 /* 7043 * Move to the next channel if no frames are received within 10ms 7044 * after sending the probe request. 7045 */ 7046 hdr->quiet_time = htole16(10); /* timeout in milliseconds */ 7047 hdr->quiet_threshold = htole16(1); /* min # of packets */ 7048 /* 7049 * Max needs to be greater than active and passive and quiet! 7050 * It's also in microseconds! 7051 */ 7052 hdr->max_svc = htole32(250 * 1024); 7053 7054 /* 7055 * Reset scan: interval=100 7056 * Normal scan: interval=becaon interval 7057 * suspend_time: 100 (TU) 7058 * 7059 */ 7060 #if 0 7061 extra = (100 /* suspend_time */ / 100 /* beacon interval */) << 22; 7062 scan_service_time = extra | ((100 /* susp */ % 100 /* int */) * 1024); 7063 #else 7064 scan_service_time = (4 << 22) | (100 * 1024); /* Hardcode for now! */ 7065 #endif 7066 hdr->pause_svc = htole32(scan_service_time); 7067 7068 /* Select antennas for scanning. */ 7069 rxchain = 7070 IWN_RXCHAIN_VALID(sc->rxchainmask) | 7071 IWN_RXCHAIN_FORCE_MIMO_SEL(sc->rxchainmask) | 7072 IWN_RXCHAIN_DRIVER_FORCE; 7073 if (IEEE80211_IS_CHAN_A(c) && 7074 sc->hw_type == IWN_HW_REV_TYPE_4965) { 7075 /* Ant A must be avoided in 5GHz because of an HW bug. */ 7076 rxchain |= IWN_RXCHAIN_FORCE_SEL(IWN_ANT_B); 7077 } else /* Use all available RX antennas. */ 7078 rxchain |= IWN_RXCHAIN_FORCE_SEL(sc->rxchainmask); 7079 hdr->rxchain = htole16(rxchain); 7080 hdr->filter = htole32(IWN_FILTER_MULTICAST | IWN_FILTER_BEACON); 7081 7082 tx = (struct iwn_cmd_data *)(hdr + 1); 7083 tx->flags = htole32(IWN_TX_AUTO_SEQ); 7084 tx->id = sc->broadcast_id; 7085 tx->lifetime = htole32(IWN_LIFETIME_INFINITE); 7086 7087 if (IEEE80211_IS_CHAN_5GHZ(c)) { 7088 /* Send probe requests at 6Mbps. */ 7089 tx->rate = htole32(0xd); 7090 rs = &ic->ic_sup_rates[IEEE80211_MODE_11A]; 7091 } else { 7092 hdr->flags = htole32(IWN_RXON_24GHZ | IWN_RXON_AUTO); 7093 if (sc->hw_type == IWN_HW_REV_TYPE_4965 && 7094 sc->rxon->associd && sc->rxon->chan > 14) 7095 tx->rate = htole32(0xd); 7096 else { 7097 /* Send probe requests at 1Mbps. */ 7098 tx->rate = htole32(10 | IWN_RFLAG_CCK); 7099 } 7100 rs = &ic->ic_sup_rates[IEEE80211_MODE_11G]; 7101 } 7102 /* Use the first valid TX antenna. */ 7103 txant = IWN_LSB(sc->txchainmask); 7104 tx->rate |= htole32(IWN_RFLAG_ANT(txant)); 7105 7106 /* 7107 * Only do active scanning if we're announcing a probe request 7108 * for a given SSID (or more, if we ever add it to the driver.) 7109 */ 7110 is_active = 0; 7111 7112 /* 7113 * If we're scanning for a specific SSID, add it to the command. 7114 * 7115 * XXX maybe look at adding support for scanning multiple SSIDs? 7116 */ 7117 essid = (struct iwn_scan_essid *)(tx + 1); 7118 if (ss != NULL) { 7119 if (ss->ss_ssid[0].len != 0) { 7120 essid[0].id = IEEE80211_ELEMID_SSID; 7121 essid[0].len = ss->ss_ssid[0].len; 7122 memcpy(essid[0].data, ss->ss_ssid[0].ssid, ss->ss_ssid[0].len); 7123 } 7124 7125 DPRINTF(sc, IWN_DEBUG_SCAN, "%s: ssid_len=%d, ssid=%*s\n", 7126 __func__, 7127 ss->ss_ssid[0].len, 7128 ss->ss_ssid[0].len, 7129 ss->ss_ssid[0].ssid); 7130 7131 if (ss->ss_nssid > 0) 7132 is_active = 1; 7133 } 7134 7135 /* 7136 * Build a probe request frame. Most of the following code is a 7137 * copy & paste of what is done in net80211. 7138 */ 7139 wh = (struct ieee80211_frame *)(essid + 20); 7140 wh->i_fc[0] = IEEE80211_FC0_VERSION_0 | IEEE80211_FC0_TYPE_MGT | 7141 IEEE80211_FC0_SUBTYPE_PROBE_REQ; 7142 wh->i_fc[1] = IEEE80211_FC1_DIR_NODS; 7143 IEEE80211_ADDR_COPY(wh->i_addr1, if_getbroadcastaddr(vap->iv_ifp)); 7144 IEEE80211_ADDR_COPY(wh->i_addr2, if_getlladdr(vap->iv_ifp)); 7145 IEEE80211_ADDR_COPY(wh->i_addr3, if_getbroadcastaddr(vap->iv_ifp)); 7146 *(uint16_t *)&wh->i_dur[0] = 0; /* filled by HW */ 7147 *(uint16_t *)&wh->i_seq[0] = 0; /* filled by HW */ 7148 7149 frm = (uint8_t *)(wh + 1); 7150 frm = ieee80211_add_ssid(frm, NULL, 0); 7151 frm = ieee80211_add_rates(frm, rs); 7152 if (rs->rs_nrates > IEEE80211_RATE_SIZE) 7153 frm = ieee80211_add_xrates(frm, rs); 7154 if (ic->ic_htcaps & IEEE80211_HTC_HT) 7155 frm = ieee80211_add_htcap(frm, ni); 7156 7157 /* Set length of probe request. */ 7158 tx->len = htole16(frm - (uint8_t *)wh); 7159 7160 /* 7161 * If active scanning is requested but a certain channel is 7162 * marked passive, we can do active scanning if we detect 7163 * transmissions. 7164 * 7165 * There is an issue with some firmware versions that triggers 7166 * a sysassert on a "good CRC threshold" of zero (== disabled), 7167 * on a radar channel even though this means that we should NOT 7168 * send probes. 7169 * 7170 * The "good CRC threshold" is the number of frames that we 7171 * need to receive during our dwell time on a channel before 7172 * sending out probes -- setting this to a huge value will 7173 * mean we never reach it, but at the same time work around 7174 * the aforementioned issue. Thus use IWL_GOOD_CRC_TH_NEVER 7175 * here instead of IWL_GOOD_CRC_TH_DISABLED. 7176 * 7177 * This was fixed in later versions along with some other 7178 * scan changes, and the threshold behaves as a flag in those 7179 * versions. 7180 */ 7181 7182 /* 7183 * If we're doing active scanning, set the crc_threshold 7184 * to a suitable value. This is different to active veruss 7185 * passive scanning depending upon the channel flags; the 7186 * firmware will obey that particular check for us. 7187 */ 7188 if (sc->tlv_feature_flags & IWN_UCODE_TLV_FLAGS_NEWSCAN) 7189 hdr->crc_threshold = is_active ? 7190 IWN_GOOD_CRC_TH_DEFAULT : IWN_GOOD_CRC_TH_DISABLED; 7191 else 7192 hdr->crc_threshold = is_active ? 7193 IWN_GOOD_CRC_TH_DEFAULT : IWN_GOOD_CRC_TH_NEVER; 7194 7195 chan = (struct iwn_scan_chan *)frm; 7196 chan->chan = htole16(ieee80211_chan2ieee(ic, c)); 7197 chan->flags = 0; 7198 if (ss->ss_nssid > 0) 7199 chan->flags |= htole32(IWN_CHAN_NPBREQS(1)); 7200 chan->dsp_gain = 0x6e; 7201 7202 /* 7203 * Set the passive/active flag depending upon the channel mode. 7204 * XXX TODO: take the is_active flag into account as well? 7205 */ 7206 if (c->ic_flags & IEEE80211_CHAN_PASSIVE) 7207 chan->flags |= htole32(IWN_CHAN_PASSIVE); 7208 else 7209 chan->flags |= htole32(IWN_CHAN_ACTIVE); 7210 7211 /* 7212 * Calculate the active/passive dwell times. 7213 */ 7214 7215 dwell_active = iwn_get_active_dwell_time(sc, c, ss->ss_nssid); 7216 dwell_passive = iwn_get_passive_dwell_time(sc, c); 7217 7218 /* Make sure they're valid */ 7219 if (dwell_passive <= dwell_active) 7220 dwell_passive = dwell_active + 1; 7221 7222 chan->active = htole16(dwell_active); 7223 chan->passive = htole16(dwell_passive); 7224 7225 if (IEEE80211_IS_CHAN_5GHZ(c)) 7226 chan->rf_gain = 0x3b; 7227 else 7228 chan->rf_gain = 0x28; 7229 7230 DPRINTF(sc, IWN_DEBUG_STATE, 7231 "%s: chan %u flags 0x%x rf_gain 0x%x " 7232 "dsp_gain 0x%x active %d passive %d scan_svc_time %d crc 0x%x " 7233 "isactive=%d numssid=%d\n", __func__, 7234 chan->chan, chan->flags, chan->rf_gain, chan->dsp_gain, 7235 dwell_active, dwell_passive, scan_service_time, 7236 hdr->crc_threshold, is_active, ss->ss_nssid); 7237 7238 hdr->nchan++; 7239 chan++; 7240 buflen = (uint8_t *)chan - buf; 7241 hdr->len = htole16(buflen); 7242 7243 if (sc->sc_is_scanning) { 7244 device_printf(sc->sc_dev, 7245 "%s: called with is_scanning set!\n", 7246 __func__); 7247 } 7248 sc->sc_is_scanning = 1; 7249 7250 DPRINTF(sc, IWN_DEBUG_STATE, "sending scan command nchan=%d\n", 7251 hdr->nchan); 7252 error = iwn_cmd(sc, IWN_CMD_SCAN, buf, buflen, 1); 7253 free(buf, M_DEVBUF); 7254 if (error == 0) 7255 callout_reset(&sc->scan_timeout, 5*hz, iwn_scan_timeout, sc); 7256 7257 DPRINTF(sc, IWN_DEBUG_TRACE, "->%s: end\n",__func__); 7258 7259 return error; 7260 } 7261 7262 static int 7263 iwn_auth(struct iwn_softc *sc, struct ieee80211vap *vap) 7264 { 7265 struct ieee80211com *ic = &sc->sc_ic; 7266 struct ieee80211_node *ni = vap->iv_bss; 7267 int error; 7268 7269 DPRINTF(sc, IWN_DEBUG_TRACE, "->%s begin\n", __func__); 7270 7271 sc->rxon = &sc->rx_on[IWN_RXON_BSS_CTX]; 7272 /* Update adapter configuration. */ 7273 IEEE80211_ADDR_COPY(sc->rxon->bssid, ni->ni_bssid); 7274 sc->rxon->chan = ieee80211_chan2ieee(ic, ni->ni_chan); 7275 sc->rxon->flags = htole32(IWN_RXON_TSF | IWN_RXON_CTS_TO_SELF); 7276 if (IEEE80211_IS_CHAN_2GHZ(ni->ni_chan)) 7277 sc->rxon->flags |= htole32(IWN_RXON_AUTO | IWN_RXON_24GHZ); 7278 7279 /* 7280 * We always set short slot on 5GHz channels. 7281 * We optionally set it for 2.4GHz channels. 7282 */ 7283 if (IEEE80211_IS_CHAN_5GHZ(ni->ni_chan)) 7284 sc->rxon->flags |= htole32(IWN_RXON_SHSLOT); 7285 else if (vap->iv_flags & IEEE80211_F_SHSLOT) 7286 sc->rxon->flags |= htole32(IWN_RXON_SHSLOT); 7287 7288 if (vap->iv_flags & IEEE80211_F_SHPREAMBLE) 7289 sc->rxon->flags |= htole32(IWN_RXON_SHPREAMBLE); 7290 if (IEEE80211_IS_CHAN_A(ni->ni_chan)) { 7291 sc->rxon->cck_mask = 0; 7292 sc->rxon->ofdm_mask = 0x15; 7293 } else if (IEEE80211_IS_CHAN_B(ni->ni_chan)) { 7294 sc->rxon->cck_mask = 0x03; 7295 sc->rxon->ofdm_mask = 0; 7296 } else { 7297 /* Assume 802.11b/g. */ 7298 sc->rxon->cck_mask = 0x03; 7299 sc->rxon->ofdm_mask = 0x15; 7300 } 7301 7302 /* try HT */ 7303 sc->rxon->flags |= htole32(iwn_get_rxon_ht_flags(sc, vap, ic->ic_curchan)); 7304 7305 DPRINTF(sc, IWN_DEBUG_STATE, "rxon chan %d flags %x cck %x ofdm %x\n", 7306 sc->rxon->chan, sc->rxon->flags, sc->rxon->cck_mask, 7307 sc->rxon->ofdm_mask); 7308 7309 if ((error = iwn_send_rxon(sc, 0, 1)) != 0) { 7310 device_printf(sc->sc_dev, "%s: could not send RXON\n", 7311 __func__); 7312 return (error); 7313 } 7314 7315 DPRINTF(sc, IWN_DEBUG_TRACE, "->%s: end\n",__func__); 7316 7317 return (0); 7318 } 7319 7320 static int 7321 iwn_run(struct iwn_softc *sc, struct ieee80211vap *vap) 7322 { 7323 struct iwn_ops *ops = &sc->ops; 7324 struct ieee80211com *ic = &sc->sc_ic; 7325 struct ieee80211_node *ni = vap->iv_bss; 7326 struct iwn_node_info node; 7327 int error; 7328 7329 DPRINTF(sc, IWN_DEBUG_TRACE, "->%s begin\n", __func__); 7330 7331 sc->rxon = &sc->rx_on[IWN_RXON_BSS_CTX]; 7332 if (ic->ic_opmode == IEEE80211_M_MONITOR) { 7333 /* Link LED blinks while monitoring. */ 7334 iwn_set_led(sc, IWN_LED_LINK, 5, 5); 7335 return 0; 7336 } 7337 if ((error = iwn_set_timing(sc, ni)) != 0) { 7338 device_printf(sc->sc_dev, 7339 "%s: could not set timing, error %d\n", __func__, error); 7340 return error; 7341 } 7342 7343 /* Update adapter configuration. */ 7344 IEEE80211_ADDR_COPY(sc->rxon->bssid, ni->ni_bssid); 7345 sc->rxon->associd = htole16(IEEE80211_AID(ni->ni_associd)); 7346 sc->rxon->chan = ieee80211_chan2ieee(ic, ni->ni_chan); 7347 sc->rxon->flags = htole32(IWN_RXON_TSF | IWN_RXON_CTS_TO_SELF); 7348 if (IEEE80211_IS_CHAN_2GHZ(ni->ni_chan)) 7349 sc->rxon->flags |= htole32(IWN_RXON_AUTO | IWN_RXON_24GHZ); 7350 7351 /* As previously - short slot only on 5GHz */ 7352 if (IEEE80211_IS_CHAN_5GHZ(ni->ni_chan)) 7353 sc->rxon->flags |= htole32(IWN_RXON_SHSLOT); 7354 else if (vap->iv_flags & IEEE80211_F_SHSLOT) 7355 sc->rxon->flags |= htole32(IWN_RXON_SHSLOT); 7356 7357 if (vap->iv_flags & IEEE80211_F_SHPREAMBLE) 7358 sc->rxon->flags |= htole32(IWN_RXON_SHPREAMBLE); 7359 if (IEEE80211_IS_CHAN_A(ni->ni_chan)) { 7360 sc->rxon->cck_mask = 0; 7361 sc->rxon->ofdm_mask = 0x15; 7362 } else if (IEEE80211_IS_CHAN_B(ni->ni_chan)) { 7363 sc->rxon->cck_mask = 0x03; 7364 sc->rxon->ofdm_mask = 0; 7365 } else { 7366 /* Assume 802.11b/g. */ 7367 sc->rxon->cck_mask = 0x0f; 7368 sc->rxon->ofdm_mask = 0x15; 7369 } 7370 /* try HT */ 7371 sc->rxon->flags |= htole32(iwn_get_rxon_ht_flags(sc, vap, ni->ni_chan)); 7372 sc->rxon->filter |= htole32(IWN_FILTER_BSS); 7373 DPRINTF(sc, IWN_DEBUG_STATE, "rxon chan %d flags %x, curhtprotmode=%d\n", 7374 sc->rxon->chan, le32toh(sc->rxon->flags), vap->iv_curhtprotmode); 7375 7376 if ((error = iwn_send_rxon(sc, 0, 1)) != 0) { 7377 device_printf(sc->sc_dev, "%s: could not send RXON\n", 7378 __func__); 7379 return error; 7380 } 7381 7382 /* Fake a join to initialize the TX rate. */ 7383 ((struct iwn_node *)ni)->id = IWN_ID_BSS; 7384 iwn_newassoc(ni, 1); 7385 7386 /* Add BSS node. */ 7387 memset(&node, 0, sizeof node); 7388 IEEE80211_ADDR_COPY(node.macaddr, ni->ni_macaddr); 7389 node.id = IWN_ID_BSS; 7390 if (IEEE80211_IS_CHAN_HT(ni->ni_chan)) { 7391 switch (ni->ni_htcap & IEEE80211_HTCAP_SMPS) { 7392 case IEEE80211_HTCAP_SMPS_ENA: 7393 node.htflags |= htole32(IWN_SMPS_MIMO_DIS); 7394 break; 7395 case IEEE80211_HTCAP_SMPS_DYNAMIC: 7396 node.htflags |= htole32(IWN_SMPS_MIMO_PROT); 7397 break; 7398 } 7399 node.htflags |= htole32(IWN_AMDPU_SIZE_FACTOR(3) | 7400 IWN_AMDPU_DENSITY(5)); /* 4us */ 7401 if (IEEE80211_IS_CHAN_HT40(ni->ni_chan)) 7402 node.htflags |= htole32(IWN_NODE_HT40); 7403 } 7404 DPRINTF(sc, IWN_DEBUG_STATE, "%s: adding BSS node\n", __func__); 7405 error = ops->add_node(sc, &node, 1); 7406 if (error != 0) { 7407 device_printf(sc->sc_dev, 7408 "%s: could not add BSS node, error %d\n", __func__, error); 7409 return error; 7410 } 7411 DPRINTF(sc, IWN_DEBUG_STATE, "%s: setting link quality for node %d\n", 7412 __func__, node.id); 7413 if ((error = iwn_set_link_quality(sc, ni)) != 0) { 7414 device_printf(sc->sc_dev, 7415 "%s: could not setup link quality for node %d, error %d\n", 7416 __func__, node.id, error); 7417 return error; 7418 } 7419 7420 if ((error = iwn_init_sensitivity(sc)) != 0) { 7421 device_printf(sc->sc_dev, 7422 "%s: could not set sensitivity, error %d\n", __func__, 7423 error); 7424 return error; 7425 } 7426 /* Start periodic calibration timer. */ 7427 sc->calib.state = IWN_CALIB_STATE_ASSOC; 7428 sc->calib_cnt = 0; 7429 callout_reset(&sc->calib_to, msecs_to_ticks(500), iwn_calib_timeout, 7430 sc); 7431 7432 /* Link LED always on while associated. */ 7433 iwn_set_led(sc, IWN_LED_LINK, 0, 1); 7434 7435 DPRINTF(sc, IWN_DEBUG_TRACE, "->%s: end\n",__func__); 7436 7437 return 0; 7438 } 7439 7440 /* 7441 * This function is called by upper layer when an ADDBA request is received 7442 * from another STA and before the ADDBA response is sent. 7443 */ 7444 static int 7445 iwn_ampdu_rx_start(struct ieee80211_node *ni, struct ieee80211_rx_ampdu *rap, 7446 int baparamset, int batimeout, int baseqctl) 7447 { 7448 struct iwn_softc *sc = ni->ni_ic->ic_softc; 7449 struct iwn_ops *ops = &sc->ops; 7450 struct iwn_node *wn = (void *)ni; 7451 struct iwn_node_info node; 7452 uint16_t ssn; 7453 uint8_t tid; 7454 int error; 7455 7456 DPRINTF(sc, IWN_DEBUG_TRACE, "->Doing %s\n", __func__); 7457 7458 tid = _IEEE80211_MASKSHIFT(le16toh(baparamset), IEEE80211_BAPS_TID); 7459 ssn = _IEEE80211_MASKSHIFT(le16toh(baseqctl), IEEE80211_BASEQ_START); 7460 7461 if (wn->id == IWN_ID_UNDEFINED) 7462 return (ENOENT); 7463 7464 memset(&node, 0, sizeof node); 7465 node.id = wn->id; 7466 node.control = IWN_NODE_UPDATE; 7467 node.flags = IWN_FLAG_SET_ADDBA; 7468 node.addba_tid = tid; 7469 node.addba_ssn = htole16(ssn); 7470 DPRINTF(sc, IWN_DEBUG_RECV, "ADDBA RA=%d TID=%d SSN=%d\n", 7471 wn->id, tid, ssn); 7472 error = ops->add_node(sc, &node, 1); 7473 if (error != 0) 7474 return error; 7475 return sc->sc_ampdu_rx_start(ni, rap, baparamset, batimeout, baseqctl); 7476 } 7477 7478 /* 7479 * This function is called by upper layer on teardown of an HT-immediate 7480 * Block Ack agreement (eg. uppon receipt of a DELBA frame). 7481 */ 7482 static void 7483 iwn_ampdu_rx_stop(struct ieee80211_node *ni, struct ieee80211_rx_ampdu *rap) 7484 { 7485 struct ieee80211com *ic = ni->ni_ic; 7486 struct iwn_softc *sc = ic->ic_softc; 7487 struct iwn_ops *ops = &sc->ops; 7488 struct iwn_node *wn = (void *)ni; 7489 struct iwn_node_info node; 7490 uint8_t tid; 7491 7492 DPRINTF(sc, IWN_DEBUG_TRACE, "->Doing %s\n", __func__); 7493 7494 if (wn->id == IWN_ID_UNDEFINED) 7495 goto end; 7496 7497 /* XXX: tid as an argument */ 7498 for (tid = 0; tid < WME_NUM_TID; tid++) { 7499 if (&ni->ni_rx_ampdu[tid] == rap) 7500 break; 7501 } 7502 7503 memset(&node, 0, sizeof node); 7504 node.id = wn->id; 7505 node.control = IWN_NODE_UPDATE; 7506 node.flags = IWN_FLAG_SET_DELBA; 7507 node.delba_tid = tid; 7508 DPRINTF(sc, IWN_DEBUG_RECV, "DELBA RA=%d TID=%d\n", wn->id, tid); 7509 (void)ops->add_node(sc, &node, 1); 7510 end: 7511 sc->sc_ampdu_rx_stop(ni, rap); 7512 } 7513 7514 static int 7515 iwn_addba_request(struct ieee80211_node *ni, struct ieee80211_tx_ampdu *tap, 7516 int dialogtoken, int baparamset, int batimeout) 7517 { 7518 struct iwn_softc *sc = ni->ni_ic->ic_softc; 7519 int qid; 7520 7521 DPRINTF(sc, IWN_DEBUG_TRACE, "->Doing %s\n", __func__); 7522 7523 for (qid = sc->firstaggqueue; qid < sc->ntxqs; qid++) { 7524 if (sc->qid2tap[qid] == NULL) 7525 break; 7526 } 7527 if (qid == sc->ntxqs) { 7528 DPRINTF(sc, IWN_DEBUG_XMIT, "%s: no free aggregation queue\n", 7529 __func__); 7530 return 0; 7531 } 7532 tap->txa_private = malloc(sizeof(int), M_DEVBUF, M_NOWAIT); 7533 if (tap->txa_private == NULL) { 7534 device_printf(sc->sc_dev, 7535 "%s: failed to alloc TX aggregation structure\n", __func__); 7536 return 0; 7537 } 7538 sc->qid2tap[qid] = tap; 7539 *(int *)tap->txa_private = qid; 7540 return sc->sc_addba_request(ni, tap, dialogtoken, baparamset, 7541 batimeout); 7542 } 7543 7544 static int 7545 iwn_addba_response(struct ieee80211_node *ni, struct ieee80211_tx_ampdu *tap, 7546 int code, int baparamset, int batimeout) 7547 { 7548 struct iwn_softc *sc = ni->ni_ic->ic_softc; 7549 int qid = *(int *)tap->txa_private; 7550 uint8_t tid = tap->txa_tid; 7551 int ret; 7552 7553 DPRINTF(sc, IWN_DEBUG_TRACE, "->Doing %s\n", __func__); 7554 7555 if (code == IEEE80211_STATUS_SUCCESS) { 7556 ni->ni_txseqs[tid] = tap->txa_start & 0xfff; 7557 ret = iwn_ampdu_tx_start(ni->ni_ic, ni, tid); 7558 if (ret != 1) 7559 return ret; 7560 } else { 7561 sc->qid2tap[qid] = NULL; 7562 free(tap->txa_private, M_DEVBUF); 7563 tap->txa_private = NULL; 7564 } 7565 return sc->sc_addba_response(ni, tap, code, baparamset, batimeout); 7566 } 7567 7568 /* 7569 * This function is called by upper layer when an ADDBA response is received 7570 * from another STA. 7571 */ 7572 static int 7573 iwn_ampdu_tx_start(struct ieee80211com *ic, struct ieee80211_node *ni, 7574 uint8_t tid) 7575 { 7576 struct ieee80211_tx_ampdu *tap = &ni->ni_tx_ampdu[tid]; 7577 struct iwn_softc *sc = ni->ni_ic->ic_softc; 7578 struct iwn_ops *ops = &sc->ops; 7579 struct iwn_node *wn = (void *)ni; 7580 struct iwn_node_info node; 7581 int error, qid; 7582 7583 DPRINTF(sc, IWN_DEBUG_TRACE, "->Doing %s\n", __func__); 7584 7585 if (wn->id == IWN_ID_UNDEFINED) 7586 return (0); 7587 7588 /* Enable TX for the specified RA/TID. */ 7589 wn->disable_tid &= ~(1 << tid); 7590 memset(&node, 0, sizeof node); 7591 node.id = wn->id; 7592 node.control = IWN_NODE_UPDATE; 7593 node.flags = IWN_FLAG_SET_DISABLE_TID; 7594 node.disable_tid = htole16(wn->disable_tid); 7595 error = ops->add_node(sc, &node, 1); 7596 if (error != 0) 7597 return 0; 7598 7599 if ((error = iwn_nic_lock(sc)) != 0) 7600 return 0; 7601 qid = *(int *)tap->txa_private; 7602 DPRINTF(sc, IWN_DEBUG_XMIT, "%s: ra=%d tid=%d ssn=%d qid=%d\n", 7603 __func__, wn->id, tid, tap->txa_start, qid); 7604 ops->ampdu_tx_start(sc, ni, qid, tid, tap->txa_start & 0xfff); 7605 iwn_nic_unlock(sc); 7606 7607 iwn_set_link_quality(sc, ni); 7608 return 1; 7609 } 7610 7611 static void 7612 iwn_ampdu_tx_stop(struct ieee80211_node *ni, struct ieee80211_tx_ampdu *tap) 7613 { 7614 struct iwn_softc *sc = ni->ni_ic->ic_softc; 7615 struct iwn_ops *ops = &sc->ops; 7616 uint8_t tid = tap->txa_tid; 7617 int qid; 7618 7619 DPRINTF(sc, IWN_DEBUG_TRACE, "->Doing %s\n", __func__); 7620 7621 sc->sc_addba_stop(ni, tap); 7622 7623 if (tap->txa_private == NULL) 7624 return; 7625 7626 qid = *(int *)tap->txa_private; 7627 if (sc->txq[qid].queued != 0) 7628 return; 7629 if (iwn_nic_lock(sc) != 0) 7630 return; 7631 ops->ampdu_tx_stop(sc, qid, tid, tap->txa_start & 0xfff); 7632 iwn_nic_unlock(sc); 7633 sc->qid2tap[qid] = NULL; 7634 free(tap->txa_private, M_DEVBUF); 7635 tap->txa_private = NULL; 7636 } 7637 7638 static void 7639 iwn4965_ampdu_tx_start(struct iwn_softc *sc, struct ieee80211_node *ni, 7640 int qid, uint8_t tid, uint16_t ssn) 7641 { 7642 struct iwn_node *wn = (void *)ni; 7643 7644 DPRINTF(sc, IWN_DEBUG_TRACE, "->Doing %s\n", __func__); 7645 7646 /* Stop TX scheduler while we're changing its configuration. */ 7647 iwn_prph_write(sc, IWN4965_SCHED_QUEUE_STATUS(qid), 7648 IWN4965_TXQ_STATUS_CHGACT); 7649 7650 /* Assign RA/TID translation to the queue. */ 7651 iwn_mem_write_2(sc, sc->sched_base + IWN4965_SCHED_TRANS_TBL(qid), 7652 wn->id << 4 | tid); 7653 7654 /* Enable chain-building mode for the queue. */ 7655 iwn_prph_setbits(sc, IWN4965_SCHED_QCHAIN_SEL, 1 << qid); 7656 7657 /* Set starting sequence number from the ADDBA request. */ 7658 sc->txq[qid].cur = sc->txq[qid].read = (ssn & 0xff); 7659 IWN_WRITE(sc, IWN_HBUS_TARG_WRPTR, qid << 8 | (ssn & 0xff)); 7660 iwn_prph_write(sc, IWN4965_SCHED_QUEUE_RDPTR(qid), ssn); 7661 7662 /* Set scheduler window size. */ 7663 iwn_mem_write(sc, sc->sched_base + IWN4965_SCHED_QUEUE_OFFSET(qid), 7664 IWN_SCHED_WINSZ); 7665 /* Set scheduler frame limit. */ 7666 iwn_mem_write(sc, sc->sched_base + IWN4965_SCHED_QUEUE_OFFSET(qid) + 4, 7667 IWN_SCHED_LIMIT << 16); 7668 7669 /* Enable interrupts for the queue. */ 7670 iwn_prph_setbits(sc, IWN4965_SCHED_INTR_MASK, 1 << qid); 7671 7672 /* Mark the queue as active. */ 7673 iwn_prph_write(sc, IWN4965_SCHED_QUEUE_STATUS(qid), 7674 IWN4965_TXQ_STATUS_ACTIVE | IWN4965_TXQ_STATUS_AGGR_ENA | 7675 iwn_tid2fifo[tid] << 1); 7676 } 7677 7678 static void 7679 iwn4965_ampdu_tx_stop(struct iwn_softc *sc, int qid, uint8_t tid, uint16_t ssn) 7680 { 7681 DPRINTF(sc, IWN_DEBUG_TRACE, "->Doing %s\n", __func__); 7682 7683 /* Stop TX scheduler while we're changing its configuration. */ 7684 iwn_prph_write(sc, IWN4965_SCHED_QUEUE_STATUS(qid), 7685 IWN4965_TXQ_STATUS_CHGACT); 7686 7687 /* Set starting sequence number from the ADDBA request. */ 7688 IWN_WRITE(sc, IWN_HBUS_TARG_WRPTR, qid << 8 | (ssn & 0xff)); 7689 iwn_prph_write(sc, IWN4965_SCHED_QUEUE_RDPTR(qid), ssn); 7690 7691 /* Disable interrupts for the queue. */ 7692 iwn_prph_clrbits(sc, IWN4965_SCHED_INTR_MASK, 1 << qid); 7693 7694 /* Mark the queue as inactive. */ 7695 iwn_prph_write(sc, IWN4965_SCHED_QUEUE_STATUS(qid), 7696 IWN4965_TXQ_STATUS_INACTIVE | iwn_tid2fifo[tid] << 1); 7697 } 7698 7699 static void 7700 iwn5000_ampdu_tx_start(struct iwn_softc *sc, struct ieee80211_node *ni, 7701 int qid, uint8_t tid, uint16_t ssn) 7702 { 7703 DPRINTF(sc, IWN_DEBUG_TRACE, "->Doing %s\n", __func__); 7704 7705 struct iwn_node *wn = (void *)ni; 7706 7707 /* Stop TX scheduler while we're changing its configuration. */ 7708 iwn_prph_write(sc, IWN5000_SCHED_QUEUE_STATUS(qid), 7709 IWN5000_TXQ_STATUS_CHGACT); 7710 7711 /* Assign RA/TID translation to the queue. */ 7712 iwn_mem_write_2(sc, sc->sched_base + IWN5000_SCHED_TRANS_TBL(qid), 7713 wn->id << 4 | tid); 7714 7715 /* Enable chain-building mode for the queue. */ 7716 iwn_prph_setbits(sc, IWN5000_SCHED_QCHAIN_SEL, 1 << qid); 7717 7718 /* Enable aggregation for the queue. */ 7719 iwn_prph_setbits(sc, IWN5000_SCHED_AGGR_SEL, 1 << qid); 7720 7721 /* Set starting sequence number from the ADDBA request. */ 7722 sc->txq[qid].cur = sc->txq[qid].read = (ssn & 0xff); 7723 IWN_WRITE(sc, IWN_HBUS_TARG_WRPTR, qid << 8 | (ssn & 0xff)); 7724 iwn_prph_write(sc, IWN5000_SCHED_QUEUE_RDPTR(qid), ssn); 7725 7726 /* Set scheduler window size and frame limit. */ 7727 iwn_mem_write(sc, sc->sched_base + IWN5000_SCHED_QUEUE_OFFSET(qid) + 4, 7728 IWN_SCHED_LIMIT << 16 | IWN_SCHED_WINSZ); 7729 7730 /* Enable interrupts for the queue. */ 7731 iwn_prph_setbits(sc, IWN5000_SCHED_INTR_MASK, 1 << qid); 7732 7733 /* Mark the queue as active. */ 7734 iwn_prph_write(sc, IWN5000_SCHED_QUEUE_STATUS(qid), 7735 IWN5000_TXQ_STATUS_ACTIVE | iwn_tid2fifo[tid]); 7736 } 7737 7738 static void 7739 iwn5000_ampdu_tx_stop(struct iwn_softc *sc, int qid, uint8_t tid, uint16_t ssn) 7740 { 7741 DPRINTF(sc, IWN_DEBUG_TRACE, "->Doing %s\n", __func__); 7742 7743 /* Stop TX scheduler while we're changing its configuration. */ 7744 iwn_prph_write(sc, IWN5000_SCHED_QUEUE_STATUS(qid), 7745 IWN5000_TXQ_STATUS_CHGACT); 7746 7747 /* Disable aggregation for the queue. */ 7748 iwn_prph_clrbits(sc, IWN5000_SCHED_AGGR_SEL, 1 << qid); 7749 7750 /* Set starting sequence number from the ADDBA request. */ 7751 IWN_WRITE(sc, IWN_HBUS_TARG_WRPTR, qid << 8 | (ssn & 0xff)); 7752 iwn_prph_write(sc, IWN5000_SCHED_QUEUE_RDPTR(qid), ssn); 7753 7754 /* Disable interrupts for the queue. */ 7755 iwn_prph_clrbits(sc, IWN5000_SCHED_INTR_MASK, 1 << qid); 7756 7757 /* Mark the queue as inactive. */ 7758 iwn_prph_write(sc, IWN5000_SCHED_QUEUE_STATUS(qid), 7759 IWN5000_TXQ_STATUS_INACTIVE | iwn_tid2fifo[tid]); 7760 } 7761 7762 /* 7763 * Query calibration tables from the initialization firmware. We do this 7764 * only once at first boot. Called from a process context. 7765 */ 7766 static int 7767 iwn5000_query_calibration(struct iwn_softc *sc) 7768 { 7769 struct iwn5000_calib_config cmd; 7770 int error; 7771 7772 memset(&cmd, 0, sizeof cmd); 7773 cmd.ucode.once.enable = htole32(0xffffffff); 7774 cmd.ucode.once.start = htole32(0xffffffff); 7775 cmd.ucode.once.send = htole32(0xffffffff); 7776 cmd.ucode.flags = htole32(0xffffffff); 7777 DPRINTF(sc, IWN_DEBUG_CALIBRATE, "%s: sending calibration query\n", 7778 __func__); 7779 error = iwn_cmd(sc, IWN5000_CMD_CALIB_CONFIG, &cmd, sizeof cmd, 0); 7780 if (error != 0) 7781 return error; 7782 7783 /* Wait at most two seconds for calibration to complete. */ 7784 if (!(sc->sc_flags & IWN_FLAG_CALIB_DONE)) 7785 error = msleep(sc, &sc->sc_mtx, PCATCH, "iwncal", 2 * hz); 7786 return error; 7787 } 7788 7789 /* 7790 * Send calibration results to the runtime firmware. These results were 7791 * obtained on first boot from the initialization firmware. 7792 */ 7793 static int 7794 iwn5000_send_calibration(struct iwn_softc *sc) 7795 { 7796 int idx, error; 7797 7798 for (idx = 0; idx < IWN5000_PHY_CALIB_MAX_RESULT; idx++) { 7799 if (!(sc->base_params->calib_need & (1<<idx))) { 7800 DPRINTF(sc, IWN_DEBUG_CALIBRATE, 7801 "No need of calib %d\n", 7802 idx); 7803 continue; /* no need for this calib */ 7804 } 7805 if (sc->calibcmd[idx].buf == NULL) { 7806 DPRINTF(sc, IWN_DEBUG_CALIBRATE, 7807 "Need calib idx : %d but no available data\n", 7808 idx); 7809 continue; 7810 } 7811 7812 DPRINTF(sc, IWN_DEBUG_CALIBRATE, 7813 "send calibration result idx=%d len=%d\n", idx, 7814 sc->calibcmd[idx].len); 7815 error = iwn_cmd(sc, IWN_CMD_PHY_CALIB, sc->calibcmd[idx].buf, 7816 sc->calibcmd[idx].len, 0); 7817 if (error != 0) { 7818 device_printf(sc->sc_dev, 7819 "%s: could not send calibration result, error %d\n", 7820 __func__, error); 7821 return error; 7822 } 7823 } 7824 return 0; 7825 } 7826 7827 static int 7828 iwn5000_send_wimax_coex(struct iwn_softc *sc) 7829 { 7830 struct iwn5000_wimax_coex wimax; 7831 7832 #if 0 7833 if (sc->hw_type == IWN_HW_REV_TYPE_6050) { 7834 /* Enable WiMAX coexistence for combo adapters. */ 7835 wimax.flags = 7836 IWN_WIMAX_COEX_ASSOC_WA_UNMASK | 7837 IWN_WIMAX_COEX_UNASSOC_WA_UNMASK | 7838 IWN_WIMAX_COEX_STA_TABLE_VALID | 7839 IWN_WIMAX_COEX_ENABLE; 7840 memcpy(wimax.events, iwn6050_wimax_events, 7841 sizeof iwn6050_wimax_events); 7842 } else 7843 #endif 7844 { 7845 /* Disable WiMAX coexistence. */ 7846 wimax.flags = 0; 7847 memset(wimax.events, 0, sizeof wimax.events); 7848 } 7849 DPRINTF(sc, IWN_DEBUG_RESET, "%s: Configuring WiMAX coexistence\n", 7850 __func__); 7851 return iwn_cmd(sc, IWN5000_CMD_WIMAX_COEX, &wimax, sizeof wimax, 0); 7852 } 7853 7854 static int 7855 iwn5000_crystal_calib(struct iwn_softc *sc) 7856 { 7857 struct iwn5000_phy_calib_crystal cmd; 7858 7859 memset(&cmd, 0, sizeof cmd); 7860 cmd.code = IWN5000_PHY_CALIB_CRYSTAL; 7861 cmd.ngroups = 1; 7862 cmd.isvalid = 1; 7863 cmd.cap_pin[0] = le32toh(sc->eeprom_crystal) & 0xff; 7864 cmd.cap_pin[1] = (le32toh(sc->eeprom_crystal) >> 16) & 0xff; 7865 DPRINTF(sc, IWN_DEBUG_CALIBRATE, "sending crystal calibration %d, %d\n", 7866 cmd.cap_pin[0], cmd.cap_pin[1]); 7867 return iwn_cmd(sc, IWN_CMD_PHY_CALIB, &cmd, sizeof cmd, 0); 7868 } 7869 7870 static int 7871 iwn5000_temp_offset_calib(struct iwn_softc *sc) 7872 { 7873 struct iwn5000_phy_calib_temp_offset cmd; 7874 7875 memset(&cmd, 0, sizeof cmd); 7876 cmd.code = IWN5000_PHY_CALIB_TEMP_OFFSET; 7877 cmd.ngroups = 1; 7878 cmd.isvalid = 1; 7879 if (sc->eeprom_temp != 0) 7880 cmd.offset = htole16(sc->eeprom_temp); 7881 else 7882 cmd.offset = htole16(IWN_DEFAULT_TEMP_OFFSET); 7883 DPRINTF(sc, IWN_DEBUG_CALIBRATE, "setting radio sensor offset to %d\n", 7884 le16toh(cmd.offset)); 7885 return iwn_cmd(sc, IWN_CMD_PHY_CALIB, &cmd, sizeof cmd, 0); 7886 } 7887 7888 static int 7889 iwn5000_temp_offset_calibv2(struct iwn_softc *sc) 7890 { 7891 struct iwn5000_phy_calib_temp_offsetv2 cmd; 7892 7893 memset(&cmd, 0, sizeof cmd); 7894 cmd.code = IWN5000_PHY_CALIB_TEMP_OFFSET; 7895 cmd.ngroups = 1; 7896 cmd.isvalid = 1; 7897 if (sc->eeprom_temp != 0) { 7898 cmd.offset_low = htole16(sc->eeprom_temp); 7899 cmd.offset_high = htole16(sc->eeprom_temp_high); 7900 } else { 7901 cmd.offset_low = htole16(IWN_DEFAULT_TEMP_OFFSET); 7902 cmd.offset_high = htole16(IWN_DEFAULT_TEMP_OFFSET); 7903 } 7904 cmd.burnt_voltage_ref = htole16(sc->eeprom_voltage); 7905 7906 DPRINTF(sc, IWN_DEBUG_CALIBRATE, 7907 "setting radio sensor low offset to %d, high offset to %d, voltage to %d\n", 7908 le16toh(cmd.offset_low), 7909 le16toh(cmd.offset_high), 7910 le16toh(cmd.burnt_voltage_ref)); 7911 7912 return iwn_cmd(sc, IWN_CMD_PHY_CALIB, &cmd, sizeof cmd, 0); 7913 } 7914 7915 /* 7916 * This function is called after the runtime firmware notifies us of its 7917 * readiness (called in a process context). 7918 */ 7919 static int 7920 iwn4965_post_alive(struct iwn_softc *sc) 7921 { 7922 int error, qid; 7923 7924 if ((error = iwn_nic_lock(sc)) != 0) 7925 return error; 7926 7927 DPRINTF(sc, IWN_DEBUG_TRACE, "->Doing %s\n", __func__); 7928 7929 /* Clear TX scheduler state in SRAM. */ 7930 sc->sched_base = iwn_prph_read(sc, IWN_SCHED_SRAM_ADDR); 7931 iwn_mem_set_region_4(sc, sc->sched_base + IWN4965_SCHED_CTX_OFF, 0, 7932 IWN4965_SCHED_CTX_LEN / sizeof (uint32_t)); 7933 7934 /* Set physical address of TX scheduler rings (1KB aligned). */ 7935 iwn_prph_write(sc, IWN4965_SCHED_DRAM_ADDR, sc->sched_dma.paddr >> 10); 7936 7937 IWN_SETBITS(sc, IWN_FH_TX_CHICKEN, IWN_FH_TX_CHICKEN_SCHED_RETRY); 7938 7939 /* Disable chain mode for all our 16 queues. */ 7940 iwn_prph_write(sc, IWN4965_SCHED_QCHAIN_SEL, 0); 7941 7942 for (qid = 0; qid < IWN4965_NTXQUEUES; qid++) { 7943 iwn_prph_write(sc, IWN4965_SCHED_QUEUE_RDPTR(qid), 0); 7944 IWN_WRITE(sc, IWN_HBUS_TARG_WRPTR, qid << 8 | 0); 7945 7946 /* Set scheduler window size. */ 7947 iwn_mem_write(sc, sc->sched_base + 7948 IWN4965_SCHED_QUEUE_OFFSET(qid), IWN_SCHED_WINSZ); 7949 /* Set scheduler frame limit. */ 7950 iwn_mem_write(sc, sc->sched_base + 7951 IWN4965_SCHED_QUEUE_OFFSET(qid) + 4, 7952 IWN_SCHED_LIMIT << 16); 7953 } 7954 7955 /* Enable interrupts for all our 16 queues. */ 7956 iwn_prph_write(sc, IWN4965_SCHED_INTR_MASK, 0xffff); 7957 /* Identify TX FIFO rings (0-7). */ 7958 iwn_prph_write(sc, IWN4965_SCHED_TXFACT, 0xff); 7959 7960 /* Mark TX rings (4 EDCA + cmd + 2 HCCA) as active. */ 7961 for (qid = 0; qid < 7; qid++) { 7962 static uint8_t qid2fifo[] = { 3, 2, 1, 0, 4, 5, 6 }; 7963 iwn_prph_write(sc, IWN4965_SCHED_QUEUE_STATUS(qid), 7964 IWN4965_TXQ_STATUS_ACTIVE | qid2fifo[qid] << 1); 7965 } 7966 iwn_nic_unlock(sc); 7967 return 0; 7968 } 7969 7970 /* 7971 * This function is called after the initialization or runtime firmware 7972 * notifies us of its readiness (called in a process context). 7973 */ 7974 static int 7975 iwn5000_post_alive(struct iwn_softc *sc) 7976 { 7977 int error, qid; 7978 7979 DPRINTF(sc, IWN_DEBUG_TRACE, "->%s begin\n", __func__); 7980 7981 /* Switch to using ICT interrupt mode. */ 7982 iwn5000_ict_reset(sc); 7983 7984 if ((error = iwn_nic_lock(sc)) != 0){ 7985 DPRINTF(sc, IWN_DEBUG_TRACE, "->%s end in error\n", __func__); 7986 return error; 7987 } 7988 7989 /* Clear TX scheduler state in SRAM. */ 7990 sc->sched_base = iwn_prph_read(sc, IWN_SCHED_SRAM_ADDR); 7991 iwn_mem_set_region_4(sc, sc->sched_base + IWN5000_SCHED_CTX_OFF, 0, 7992 IWN5000_SCHED_CTX_LEN / sizeof (uint32_t)); 7993 7994 /* Set physical address of TX scheduler rings (1KB aligned). */ 7995 iwn_prph_write(sc, IWN5000_SCHED_DRAM_ADDR, sc->sched_dma.paddr >> 10); 7996 7997 IWN_SETBITS(sc, IWN_FH_TX_CHICKEN, IWN_FH_TX_CHICKEN_SCHED_RETRY); 7998 7999 /* Enable chain mode for all queues, except command queue. */ 8000 if (sc->sc_flags & IWN_FLAG_PAN_SUPPORT) 8001 iwn_prph_write(sc, IWN5000_SCHED_QCHAIN_SEL, 0xfffdf); 8002 else 8003 iwn_prph_write(sc, IWN5000_SCHED_QCHAIN_SEL, 0xfffef); 8004 iwn_prph_write(sc, IWN5000_SCHED_AGGR_SEL, 0); 8005 8006 for (qid = 0; qid < IWN5000_NTXQUEUES; qid++) { 8007 iwn_prph_write(sc, IWN5000_SCHED_QUEUE_RDPTR(qid), 0); 8008 IWN_WRITE(sc, IWN_HBUS_TARG_WRPTR, qid << 8 | 0); 8009 8010 iwn_mem_write(sc, sc->sched_base + 8011 IWN5000_SCHED_QUEUE_OFFSET(qid), 0); 8012 /* Set scheduler window size and frame limit. */ 8013 iwn_mem_write(sc, sc->sched_base + 8014 IWN5000_SCHED_QUEUE_OFFSET(qid) + 4, 8015 IWN_SCHED_LIMIT << 16 | IWN_SCHED_WINSZ); 8016 } 8017 8018 /* Enable interrupts for all our 20 queues. */ 8019 iwn_prph_write(sc, IWN5000_SCHED_INTR_MASK, 0xfffff); 8020 /* Identify TX FIFO rings (0-7). */ 8021 iwn_prph_write(sc, IWN5000_SCHED_TXFACT, 0xff); 8022 8023 /* Mark TX rings (4 EDCA + cmd + 2 HCCA) as active. */ 8024 if (sc->sc_flags & IWN_FLAG_PAN_SUPPORT) { 8025 /* Mark TX rings as active. */ 8026 for (qid = 0; qid < 11; qid++) { 8027 static uint8_t qid2fifo[] = { 3, 2, 1, 0, 0, 4, 2, 5, 4, 7, 5 }; 8028 iwn_prph_write(sc, IWN5000_SCHED_QUEUE_STATUS(qid), 8029 IWN5000_TXQ_STATUS_ACTIVE | qid2fifo[qid]); 8030 } 8031 } else { 8032 /* Mark TX rings (4 EDCA + cmd + 2 HCCA) as active. */ 8033 for (qid = 0; qid < 7; qid++) { 8034 static uint8_t qid2fifo[] = { 3, 2, 1, 0, 7, 5, 6 }; 8035 iwn_prph_write(sc, IWN5000_SCHED_QUEUE_STATUS(qid), 8036 IWN5000_TXQ_STATUS_ACTIVE | qid2fifo[qid]); 8037 } 8038 } 8039 iwn_nic_unlock(sc); 8040 8041 /* Configure WiMAX coexistence for combo adapters. */ 8042 error = iwn5000_send_wimax_coex(sc); 8043 if (error != 0) { 8044 device_printf(sc->sc_dev, 8045 "%s: could not configure WiMAX coexistence, error %d\n", 8046 __func__, error); 8047 return error; 8048 } 8049 if (sc->hw_type != IWN_HW_REV_TYPE_5150) { 8050 /* Perform crystal calibration. */ 8051 error = iwn5000_crystal_calib(sc); 8052 if (error != 0) { 8053 device_printf(sc->sc_dev, 8054 "%s: crystal calibration failed, error %d\n", 8055 __func__, error); 8056 return error; 8057 } 8058 } 8059 if (!(sc->sc_flags & IWN_FLAG_CALIB_DONE)) { 8060 /* Query calibration from the initialization firmware. */ 8061 if ((error = iwn5000_query_calibration(sc)) != 0) { 8062 device_printf(sc->sc_dev, 8063 "%s: could not query calibration, error %d\n", 8064 __func__, error); 8065 return error; 8066 } 8067 /* 8068 * We have the calibration results now, reboot with the 8069 * runtime firmware (call ourselves recursively!) 8070 */ 8071 iwn_hw_stop(sc); 8072 error = iwn_hw_init(sc); 8073 } else { 8074 /* Send calibration results to runtime firmware. */ 8075 error = iwn5000_send_calibration(sc); 8076 } 8077 8078 DPRINTF(sc, IWN_DEBUG_TRACE, "->%s: end\n",__func__); 8079 8080 return error; 8081 } 8082 8083 /* 8084 * The firmware boot code is small and is intended to be copied directly into 8085 * the NIC internal memory (no DMA transfer). 8086 */ 8087 static int 8088 iwn4965_load_bootcode(struct iwn_softc *sc, const uint8_t *ucode, int size) 8089 { 8090 int error, ntries; 8091 8092 size /= sizeof (uint32_t); 8093 8094 if ((error = iwn_nic_lock(sc)) != 0) 8095 return error; 8096 8097 /* Copy microcode image into NIC memory. */ 8098 iwn_prph_write_region_4(sc, IWN_BSM_SRAM_BASE, 8099 (const uint32_t *)ucode, size); 8100 8101 iwn_prph_write(sc, IWN_BSM_WR_MEM_SRC, 0); 8102 iwn_prph_write(sc, IWN_BSM_WR_MEM_DST, IWN_FW_TEXT_BASE); 8103 iwn_prph_write(sc, IWN_BSM_WR_DWCOUNT, size); 8104 8105 /* Start boot load now. */ 8106 iwn_prph_write(sc, IWN_BSM_WR_CTRL, IWN_BSM_WR_CTRL_START); 8107 8108 /* Wait for transfer to complete. */ 8109 for (ntries = 0; ntries < 1000; ntries++) { 8110 if (!(iwn_prph_read(sc, IWN_BSM_WR_CTRL) & 8111 IWN_BSM_WR_CTRL_START)) 8112 break; 8113 DELAY(10); 8114 } 8115 if (ntries == 1000) { 8116 device_printf(sc->sc_dev, "%s: could not load boot firmware\n", 8117 __func__); 8118 iwn_nic_unlock(sc); 8119 return ETIMEDOUT; 8120 } 8121 8122 /* Enable boot after power up. */ 8123 iwn_prph_write(sc, IWN_BSM_WR_CTRL, IWN_BSM_WR_CTRL_START_EN); 8124 8125 iwn_nic_unlock(sc); 8126 return 0; 8127 } 8128 8129 static int 8130 iwn4965_load_firmware(struct iwn_softc *sc) 8131 { 8132 struct iwn_fw_info *fw = &sc->fw; 8133 struct iwn_dma_info *dma = &sc->fw_dma; 8134 int error; 8135 8136 /* Copy initialization sections into pre-allocated DMA-safe memory. */ 8137 memcpy(dma->vaddr, fw->init.data, fw->init.datasz); 8138 bus_dmamap_sync(dma->tag, dma->map, BUS_DMASYNC_PREWRITE); 8139 memcpy(dma->vaddr + IWN4965_FW_DATA_MAXSZ, 8140 fw->init.text, fw->init.textsz); 8141 bus_dmamap_sync(dma->tag, dma->map, BUS_DMASYNC_PREWRITE); 8142 8143 /* Tell adapter where to find initialization sections. */ 8144 if ((error = iwn_nic_lock(sc)) != 0) 8145 return error; 8146 iwn_prph_write(sc, IWN_BSM_DRAM_DATA_ADDR, dma->paddr >> 4); 8147 iwn_prph_write(sc, IWN_BSM_DRAM_DATA_SIZE, fw->init.datasz); 8148 iwn_prph_write(sc, IWN_BSM_DRAM_TEXT_ADDR, 8149 (dma->paddr + IWN4965_FW_DATA_MAXSZ) >> 4); 8150 iwn_prph_write(sc, IWN_BSM_DRAM_TEXT_SIZE, fw->init.textsz); 8151 iwn_nic_unlock(sc); 8152 8153 /* Load firmware boot code. */ 8154 error = iwn4965_load_bootcode(sc, fw->boot.text, fw->boot.textsz); 8155 if (error != 0) { 8156 device_printf(sc->sc_dev, "%s: could not load boot firmware\n", 8157 __func__); 8158 return error; 8159 } 8160 /* Now press "execute". */ 8161 IWN_WRITE(sc, IWN_RESET, 0); 8162 8163 /* Wait at most one second for first alive notification. */ 8164 if ((error = msleep(sc, &sc->sc_mtx, PCATCH, "iwninit", hz)) != 0) { 8165 device_printf(sc->sc_dev, 8166 "%s: timeout waiting for adapter to initialize, error %d\n", 8167 __func__, error); 8168 return error; 8169 } 8170 8171 /* Retrieve current temperature for initial TX power calibration. */ 8172 sc->rawtemp = sc->ucode_info.temp[3].chan20MHz; 8173 sc->temp = iwn4965_get_temperature(sc); 8174 8175 /* Copy runtime sections into pre-allocated DMA-safe memory. */ 8176 memcpy(dma->vaddr, fw->main.data, fw->main.datasz); 8177 bus_dmamap_sync(dma->tag, dma->map, BUS_DMASYNC_PREWRITE); 8178 memcpy(dma->vaddr + IWN4965_FW_DATA_MAXSZ, 8179 fw->main.text, fw->main.textsz); 8180 bus_dmamap_sync(dma->tag, dma->map, BUS_DMASYNC_PREWRITE); 8181 8182 /* Tell adapter where to find runtime sections. */ 8183 if ((error = iwn_nic_lock(sc)) != 0) 8184 return error; 8185 iwn_prph_write(sc, IWN_BSM_DRAM_DATA_ADDR, dma->paddr >> 4); 8186 iwn_prph_write(sc, IWN_BSM_DRAM_DATA_SIZE, fw->main.datasz); 8187 iwn_prph_write(sc, IWN_BSM_DRAM_TEXT_ADDR, 8188 (dma->paddr + IWN4965_FW_DATA_MAXSZ) >> 4); 8189 iwn_prph_write(sc, IWN_BSM_DRAM_TEXT_SIZE, 8190 IWN_FW_UPDATED | fw->main.textsz); 8191 iwn_nic_unlock(sc); 8192 8193 return 0; 8194 } 8195 8196 static int 8197 iwn5000_load_firmware_section(struct iwn_softc *sc, uint32_t dst, 8198 const uint8_t *section, int size) 8199 { 8200 struct iwn_dma_info *dma = &sc->fw_dma; 8201 int error; 8202 8203 DPRINTF(sc, IWN_DEBUG_TRACE, "->Doing %s\n", __func__); 8204 8205 /* Copy firmware section into pre-allocated DMA-safe memory. */ 8206 memcpy(dma->vaddr, section, size); 8207 bus_dmamap_sync(dma->tag, dma->map, BUS_DMASYNC_PREWRITE); 8208 8209 if ((error = iwn_nic_lock(sc)) != 0) 8210 return error; 8211 8212 IWN_WRITE(sc, IWN_FH_TX_CONFIG(IWN_SRVC_DMACHNL), 8213 IWN_FH_TX_CONFIG_DMA_PAUSE); 8214 8215 IWN_WRITE(sc, IWN_FH_SRAM_ADDR(IWN_SRVC_DMACHNL), dst); 8216 IWN_WRITE(sc, IWN_FH_TFBD_CTRL0(IWN_SRVC_DMACHNL), 8217 IWN_LOADDR(dma->paddr)); 8218 IWN_WRITE(sc, IWN_FH_TFBD_CTRL1(IWN_SRVC_DMACHNL), 8219 IWN_HIADDR(dma->paddr) << 28 | size); 8220 IWN_WRITE(sc, IWN_FH_TXBUF_STATUS(IWN_SRVC_DMACHNL), 8221 IWN_FH_TXBUF_STATUS_TBNUM(1) | 8222 IWN_FH_TXBUF_STATUS_TBIDX(1) | 8223 IWN_FH_TXBUF_STATUS_TFBD_VALID); 8224 8225 /* Kick Flow Handler to start DMA transfer. */ 8226 IWN_WRITE(sc, IWN_FH_TX_CONFIG(IWN_SRVC_DMACHNL), 8227 IWN_FH_TX_CONFIG_DMA_ENA | IWN_FH_TX_CONFIG_CIRQ_HOST_ENDTFD); 8228 8229 iwn_nic_unlock(sc); 8230 8231 /* Wait at most five seconds for FH DMA transfer to complete. */ 8232 return msleep(sc, &sc->sc_mtx, PCATCH, "iwninit", 5 * hz); 8233 } 8234 8235 static int 8236 iwn5000_load_firmware(struct iwn_softc *sc) 8237 { 8238 struct iwn_fw_part *fw; 8239 int error; 8240 8241 DPRINTF(sc, IWN_DEBUG_TRACE, "->Doing %s\n", __func__); 8242 8243 /* Load the initialization firmware on first boot only. */ 8244 fw = (sc->sc_flags & IWN_FLAG_CALIB_DONE) ? 8245 &sc->fw.main : &sc->fw.init; 8246 8247 error = iwn5000_load_firmware_section(sc, IWN_FW_TEXT_BASE, 8248 fw->text, fw->textsz); 8249 if (error != 0) { 8250 device_printf(sc->sc_dev, 8251 "%s: could not load firmware %s section, error %d\n", 8252 __func__, ".text", error); 8253 return error; 8254 } 8255 error = iwn5000_load_firmware_section(sc, IWN_FW_DATA_BASE, 8256 fw->data, fw->datasz); 8257 if (error != 0) { 8258 device_printf(sc->sc_dev, 8259 "%s: could not load firmware %s section, error %d\n", 8260 __func__, ".data", error); 8261 return error; 8262 } 8263 8264 /* Now press "execute". */ 8265 IWN_WRITE(sc, IWN_RESET, 0); 8266 return 0; 8267 } 8268 8269 /* 8270 * Extract text and data sections from a legacy firmware image. 8271 */ 8272 static int 8273 iwn_read_firmware_leg(struct iwn_softc *sc, struct iwn_fw_info *fw) 8274 { 8275 const uint32_t *ptr; 8276 size_t hdrlen = 24; 8277 uint32_t rev; 8278 8279 ptr = (const uint32_t *)fw->data; 8280 rev = le32toh(*ptr++); 8281 8282 sc->ucode_rev = rev; 8283 8284 /* Check firmware API version. */ 8285 if (IWN_FW_API(rev) <= 1) { 8286 device_printf(sc->sc_dev, 8287 "%s: bad firmware, need API version >=2\n", __func__); 8288 return EINVAL; 8289 } 8290 if (IWN_FW_API(rev) >= 3) { 8291 /* Skip build number (version 2 header). */ 8292 hdrlen += 4; 8293 ptr++; 8294 } 8295 if (fw->size < hdrlen) { 8296 device_printf(sc->sc_dev, "%s: firmware too short: %zu bytes\n", 8297 __func__, fw->size); 8298 return EINVAL; 8299 } 8300 fw->main.textsz = le32toh(*ptr++); 8301 fw->main.datasz = le32toh(*ptr++); 8302 fw->init.textsz = le32toh(*ptr++); 8303 fw->init.datasz = le32toh(*ptr++); 8304 fw->boot.textsz = le32toh(*ptr++); 8305 8306 /* Check that all firmware sections fit. */ 8307 if (fw->size < hdrlen + fw->main.textsz + fw->main.datasz + 8308 fw->init.textsz + fw->init.datasz + fw->boot.textsz) { 8309 device_printf(sc->sc_dev, "%s: firmware too short: %zu bytes\n", 8310 __func__, fw->size); 8311 return EINVAL; 8312 } 8313 8314 /* Get pointers to firmware sections. */ 8315 fw->main.text = (const uint8_t *)ptr; 8316 fw->main.data = fw->main.text + fw->main.textsz; 8317 fw->init.text = fw->main.data + fw->main.datasz; 8318 fw->init.data = fw->init.text + fw->init.textsz; 8319 fw->boot.text = fw->init.data + fw->init.datasz; 8320 return 0; 8321 } 8322 8323 /* 8324 * Extract text and data sections from a TLV firmware image. 8325 */ 8326 static int 8327 iwn_read_firmware_tlv(struct iwn_softc *sc, struct iwn_fw_info *fw, 8328 uint16_t alt) 8329 { 8330 const struct iwn_fw_tlv_hdr *hdr; 8331 const struct iwn_fw_tlv *tlv; 8332 const uint8_t *ptr, *end; 8333 uint64_t altmask; 8334 uint32_t len, tmp; 8335 8336 if (fw->size < sizeof (*hdr)) { 8337 device_printf(sc->sc_dev, "%s: firmware too short: %zu bytes\n", 8338 __func__, fw->size); 8339 return EINVAL; 8340 } 8341 hdr = (const struct iwn_fw_tlv_hdr *)fw->data; 8342 if (hdr->signature != htole32(IWN_FW_SIGNATURE)) { 8343 device_printf(sc->sc_dev, "%s: bad firmware signature 0x%08x\n", 8344 __func__, le32toh(hdr->signature)); 8345 return EINVAL; 8346 } 8347 DPRINTF(sc, IWN_DEBUG_RESET, "FW: \"%.64s\", build 0x%x\n", hdr->descr, 8348 le32toh(hdr->build)); 8349 sc->ucode_rev = le32toh(hdr->rev); 8350 8351 /* 8352 * Select the closest supported alternative that is less than 8353 * or equal to the specified one. 8354 */ 8355 altmask = le64toh(hdr->altmask); 8356 while (alt > 0 && !(altmask & (1ULL << alt))) 8357 alt--; /* Downgrade. */ 8358 DPRINTF(sc, IWN_DEBUG_RESET, "using alternative %d\n", alt); 8359 8360 ptr = (const uint8_t *)(hdr + 1); 8361 end = (const uint8_t *)(fw->data + fw->size); 8362 8363 /* Parse type-length-value fields. */ 8364 while (ptr + sizeof (*tlv) <= end) { 8365 tlv = (const struct iwn_fw_tlv *)ptr; 8366 len = le32toh(tlv->len); 8367 8368 ptr += sizeof (*tlv); 8369 if (ptr + len > end) { 8370 device_printf(sc->sc_dev, 8371 "%s: firmware too short: %zu bytes\n", __func__, 8372 fw->size); 8373 return EINVAL; 8374 } 8375 /* Skip other alternatives. */ 8376 if (tlv->alt != 0 && tlv->alt != htole16(alt)) 8377 goto next; 8378 8379 switch (le16toh(tlv->type)) { 8380 case IWN_FW_TLV_MAIN_TEXT: 8381 fw->main.text = ptr; 8382 fw->main.textsz = len; 8383 break; 8384 case IWN_FW_TLV_MAIN_DATA: 8385 fw->main.data = ptr; 8386 fw->main.datasz = len; 8387 break; 8388 case IWN_FW_TLV_INIT_TEXT: 8389 fw->init.text = ptr; 8390 fw->init.textsz = len; 8391 break; 8392 case IWN_FW_TLV_INIT_DATA: 8393 fw->init.data = ptr; 8394 fw->init.datasz = len; 8395 break; 8396 case IWN_FW_TLV_BOOT_TEXT: 8397 fw->boot.text = ptr; 8398 fw->boot.textsz = len; 8399 break; 8400 case IWN_FW_TLV_ENH_SENS: 8401 if (!len) 8402 sc->sc_flags |= IWN_FLAG_ENH_SENS; 8403 break; 8404 case IWN_FW_TLV_PHY_CALIB: 8405 tmp = le32toh(*ptr); 8406 if (tmp < 253) { 8407 sc->reset_noise_gain = tmp; 8408 sc->noise_gain = tmp + 1; 8409 } 8410 break; 8411 case IWN_FW_TLV_PAN: 8412 sc->sc_flags |= IWN_FLAG_PAN_SUPPORT; 8413 DPRINTF(sc, IWN_DEBUG_RESET, 8414 "PAN Support found: %d\n", 1); 8415 break; 8416 case IWN_FW_TLV_FLAGS: 8417 if (len < sizeof(uint32_t)) 8418 break; 8419 if (len % sizeof(uint32_t)) 8420 break; 8421 sc->tlv_feature_flags = le32toh(*ptr); 8422 DPRINTF(sc, IWN_DEBUG_RESET, 8423 "%s: feature: 0x%08x\n", 8424 __func__, 8425 sc->tlv_feature_flags); 8426 break; 8427 case IWN_FW_TLV_PBREQ_MAXLEN: 8428 case IWN_FW_TLV_RUNT_EVTLOG_PTR: 8429 case IWN_FW_TLV_RUNT_EVTLOG_SIZE: 8430 case IWN_FW_TLV_RUNT_ERRLOG_PTR: 8431 case IWN_FW_TLV_INIT_EVTLOG_PTR: 8432 case IWN_FW_TLV_INIT_EVTLOG_SIZE: 8433 case IWN_FW_TLV_INIT_ERRLOG_PTR: 8434 case IWN_FW_TLV_WOWLAN_INST: 8435 case IWN_FW_TLV_WOWLAN_DATA: 8436 DPRINTF(sc, IWN_DEBUG_RESET, 8437 "TLV type %d recognized but not handled\n", 8438 le16toh(tlv->type)); 8439 break; 8440 default: 8441 DPRINTF(sc, IWN_DEBUG_RESET, 8442 "TLV type %d not handled\n", le16toh(tlv->type)); 8443 break; 8444 } 8445 next: /* TLV fields are 32-bit aligned. */ 8446 ptr += (len + 3) & ~3; 8447 } 8448 return 0; 8449 } 8450 8451 static int 8452 iwn_read_firmware(struct iwn_softc *sc) 8453 { 8454 struct iwn_fw_info *fw = &sc->fw; 8455 int error; 8456 8457 DPRINTF(sc, IWN_DEBUG_TRACE, "->Doing %s\n", __func__); 8458 8459 IWN_UNLOCK(sc); 8460 8461 memset(fw, 0, sizeof (*fw)); 8462 8463 /* Read firmware image from filesystem. */ 8464 sc->fw_fp = firmware_get(sc->fwname); 8465 if (sc->fw_fp == NULL) { 8466 device_printf(sc->sc_dev, "%s: could not read firmware %s\n", 8467 __func__, sc->fwname); 8468 IWN_LOCK(sc); 8469 return EINVAL; 8470 } 8471 IWN_LOCK(sc); 8472 8473 fw->size = sc->fw_fp->datasize; 8474 fw->data = (const uint8_t *)sc->fw_fp->data; 8475 if (fw->size < sizeof (uint32_t)) { 8476 device_printf(sc->sc_dev, "%s: firmware too short: %zu bytes\n", 8477 __func__, fw->size); 8478 error = EINVAL; 8479 goto fail; 8480 } 8481 8482 /* Retrieve text and data sections. */ 8483 if (*(const uint32_t *)fw->data != 0) /* Legacy image. */ 8484 error = iwn_read_firmware_leg(sc, fw); 8485 else 8486 error = iwn_read_firmware_tlv(sc, fw, 1); 8487 if (error != 0) { 8488 device_printf(sc->sc_dev, 8489 "%s: could not read firmware sections, error %d\n", 8490 __func__, error); 8491 goto fail; 8492 } 8493 8494 device_printf(sc->sc_dev, "%s: ucode rev=0x%08x\n", __func__, sc->ucode_rev); 8495 8496 /* Make sure text and data sections fit in hardware memory. */ 8497 if (fw->main.textsz > sc->fw_text_maxsz || 8498 fw->main.datasz > sc->fw_data_maxsz || 8499 fw->init.textsz > sc->fw_text_maxsz || 8500 fw->init.datasz > sc->fw_data_maxsz || 8501 fw->boot.textsz > IWN_FW_BOOT_TEXT_MAXSZ || 8502 (fw->boot.textsz & 3) != 0) { 8503 device_printf(sc->sc_dev, "%s: firmware sections too large\n", 8504 __func__); 8505 error = EINVAL; 8506 goto fail; 8507 } 8508 8509 /* We can proceed with loading the firmware. */ 8510 return 0; 8511 8512 fail: iwn_unload_firmware(sc); 8513 return error; 8514 } 8515 8516 static void 8517 iwn_unload_firmware(struct iwn_softc *sc) 8518 { 8519 firmware_put(sc->fw_fp, FIRMWARE_UNLOAD); 8520 sc->fw_fp = NULL; 8521 } 8522 8523 static int 8524 iwn_clock_wait(struct iwn_softc *sc) 8525 { 8526 int ntries; 8527 8528 /* Set "initialization complete" bit. */ 8529 IWN_SETBITS(sc, IWN_GP_CNTRL, IWN_GP_CNTRL_INIT_DONE); 8530 8531 /* Wait for clock stabilization. */ 8532 for (ntries = 0; ntries < 2500; ntries++) { 8533 if (IWN_READ(sc, IWN_GP_CNTRL) & IWN_GP_CNTRL_MAC_CLOCK_READY) 8534 return 0; 8535 DELAY(10); 8536 } 8537 device_printf(sc->sc_dev, 8538 "%s: timeout waiting for clock stabilization\n", __func__); 8539 return ETIMEDOUT; 8540 } 8541 8542 static int 8543 iwn_apm_init(struct iwn_softc *sc) 8544 { 8545 uint32_t reg; 8546 int error; 8547 8548 DPRINTF(sc, IWN_DEBUG_TRACE, "->Doing %s\n", __func__); 8549 8550 /* Disable L0s exit timer (NMI bug workaround). */ 8551 IWN_SETBITS(sc, IWN_GIO_CHICKEN, IWN_GIO_CHICKEN_DIS_L0S_TIMER); 8552 /* Don't wait for ICH L0s (ICH bug workaround). */ 8553 IWN_SETBITS(sc, IWN_GIO_CHICKEN, IWN_GIO_CHICKEN_L1A_NO_L0S_RX); 8554 8555 /* Set FH wait threshold to max (HW bug under stress workaround). */ 8556 IWN_SETBITS(sc, IWN_DBG_HPET_MEM, 0xffff0000); 8557 8558 /* Enable HAP INTA to move adapter from L1a to L0s. */ 8559 IWN_SETBITS(sc, IWN_HW_IF_CONFIG, IWN_HW_IF_CONFIG_HAP_WAKE_L1A); 8560 8561 /* Retrieve PCIe Active State Power Management (ASPM). */ 8562 reg = pci_read_config(sc->sc_dev, sc->sc_cap_off + PCIER_LINK_CTL, 4); 8563 /* Workaround for HW instability in PCIe L0->L0s->L1 transition. */ 8564 if (reg & PCIEM_LINK_CTL_ASPMC_L1) /* L1 Entry enabled. */ 8565 IWN_SETBITS(sc, IWN_GIO, IWN_GIO_L0S_ENA); 8566 else 8567 IWN_CLRBITS(sc, IWN_GIO, IWN_GIO_L0S_ENA); 8568 8569 if (sc->base_params->pll_cfg_val) 8570 IWN_SETBITS(sc, IWN_ANA_PLL, sc->base_params->pll_cfg_val); 8571 8572 /* Wait for clock stabilization before accessing prph. */ 8573 if ((error = iwn_clock_wait(sc)) != 0) 8574 return error; 8575 8576 if ((error = iwn_nic_lock(sc)) != 0) 8577 return error; 8578 if (sc->hw_type == IWN_HW_REV_TYPE_4965) { 8579 /* Enable DMA and BSM (Bootstrap State Machine). */ 8580 iwn_prph_write(sc, IWN_APMG_CLK_EN, 8581 IWN_APMG_CLK_CTRL_DMA_CLK_RQT | 8582 IWN_APMG_CLK_CTRL_BSM_CLK_RQT); 8583 } else { 8584 /* Enable DMA. */ 8585 iwn_prph_write(sc, IWN_APMG_CLK_EN, 8586 IWN_APMG_CLK_CTRL_DMA_CLK_RQT); 8587 } 8588 DELAY(20); 8589 /* Disable L1-Active. */ 8590 iwn_prph_setbits(sc, IWN_APMG_PCI_STT, IWN_APMG_PCI_STT_L1A_DIS); 8591 iwn_nic_unlock(sc); 8592 8593 return 0; 8594 } 8595 8596 static void 8597 iwn_apm_stop_master(struct iwn_softc *sc) 8598 { 8599 int ntries; 8600 8601 /* Stop busmaster DMA activity. */ 8602 IWN_SETBITS(sc, IWN_RESET, IWN_RESET_STOP_MASTER); 8603 for (ntries = 0; ntries < 100; ntries++) { 8604 if (IWN_READ(sc, IWN_RESET) & IWN_RESET_MASTER_DISABLED) 8605 return; 8606 DELAY(10); 8607 } 8608 device_printf(sc->sc_dev, "%s: timeout waiting for master\n", __func__); 8609 } 8610 8611 static void 8612 iwn_apm_stop(struct iwn_softc *sc) 8613 { 8614 iwn_apm_stop_master(sc); 8615 8616 /* Reset the entire device. */ 8617 IWN_SETBITS(sc, IWN_RESET, IWN_RESET_SW); 8618 DELAY(10); 8619 /* Clear "initialization complete" bit. */ 8620 IWN_CLRBITS(sc, IWN_GP_CNTRL, IWN_GP_CNTRL_INIT_DONE); 8621 } 8622 8623 static int 8624 iwn4965_nic_config(struct iwn_softc *sc) 8625 { 8626 DPRINTF(sc, IWN_DEBUG_TRACE, "->Doing %s\n", __func__); 8627 8628 if (IWN_RFCFG_TYPE(sc->rfcfg) == 1) { 8629 /* 8630 * I don't believe this to be correct but this is what the 8631 * vendor driver is doing. Probably the bits should not be 8632 * shifted in IWN_RFCFG_*. 8633 */ 8634 IWN_SETBITS(sc, IWN_HW_IF_CONFIG, 8635 IWN_RFCFG_TYPE(sc->rfcfg) | 8636 IWN_RFCFG_STEP(sc->rfcfg) | 8637 IWN_RFCFG_DASH(sc->rfcfg)); 8638 } 8639 IWN_SETBITS(sc, IWN_HW_IF_CONFIG, 8640 IWN_HW_IF_CONFIG_RADIO_SI | IWN_HW_IF_CONFIG_MAC_SI); 8641 return 0; 8642 } 8643 8644 static int 8645 iwn5000_nic_config(struct iwn_softc *sc) 8646 { 8647 uint32_t tmp; 8648 int error; 8649 8650 DPRINTF(sc, IWN_DEBUG_TRACE, "->Doing %s\n", __func__); 8651 8652 if (IWN_RFCFG_TYPE(sc->rfcfg) < 3) { 8653 IWN_SETBITS(sc, IWN_HW_IF_CONFIG, 8654 IWN_RFCFG_TYPE(sc->rfcfg) | 8655 IWN_RFCFG_STEP(sc->rfcfg) | 8656 IWN_RFCFG_DASH(sc->rfcfg)); 8657 } 8658 IWN_SETBITS(sc, IWN_HW_IF_CONFIG, 8659 IWN_HW_IF_CONFIG_RADIO_SI | IWN_HW_IF_CONFIG_MAC_SI); 8660 8661 if ((error = iwn_nic_lock(sc)) != 0) 8662 return error; 8663 iwn_prph_setbits(sc, IWN_APMG_PS, IWN_APMG_PS_EARLY_PWROFF_DIS); 8664 8665 if (sc->hw_type == IWN_HW_REV_TYPE_1000) { 8666 /* 8667 * Select first Switching Voltage Regulator (1.32V) to 8668 * solve a stability issue related to noisy DC2DC line 8669 * in the silicon of 1000 Series. 8670 */ 8671 tmp = iwn_prph_read(sc, IWN_APMG_DIGITAL_SVR); 8672 tmp &= ~IWN_APMG_DIGITAL_SVR_VOLTAGE_MASK; 8673 tmp |= IWN_APMG_DIGITAL_SVR_VOLTAGE_1_32; 8674 iwn_prph_write(sc, IWN_APMG_DIGITAL_SVR, tmp); 8675 } 8676 iwn_nic_unlock(sc); 8677 8678 if (sc->sc_flags & IWN_FLAG_INTERNAL_PA) { 8679 /* Use internal power amplifier only. */ 8680 IWN_WRITE(sc, IWN_GP_DRIVER, IWN_GP_DRIVER_RADIO_2X2_IPA); 8681 } 8682 if (sc->base_params->additional_nic_config && sc->calib_ver >= 6) { 8683 /* Indicate that ROM calibration version is >=6. */ 8684 IWN_SETBITS(sc, IWN_GP_DRIVER, IWN_GP_DRIVER_CALIB_VER6); 8685 } 8686 if (sc->base_params->additional_gp_drv_bit) 8687 IWN_SETBITS(sc, IWN_GP_DRIVER, 8688 sc->base_params->additional_gp_drv_bit); 8689 return 0; 8690 } 8691 8692 /* 8693 * Take NIC ownership over Intel Active Management Technology (AMT). 8694 */ 8695 static int 8696 iwn_hw_prepare(struct iwn_softc *sc) 8697 { 8698 int ntries; 8699 8700 DPRINTF(sc, IWN_DEBUG_TRACE, "->Doing %s\n", __func__); 8701 8702 /* Check if hardware is ready. */ 8703 IWN_SETBITS(sc, IWN_HW_IF_CONFIG, IWN_HW_IF_CONFIG_NIC_READY); 8704 for (ntries = 0; ntries < 5; ntries++) { 8705 if (IWN_READ(sc, IWN_HW_IF_CONFIG) & 8706 IWN_HW_IF_CONFIG_NIC_READY) 8707 return 0; 8708 DELAY(10); 8709 } 8710 8711 /* Hardware not ready, force into ready state. */ 8712 IWN_SETBITS(sc, IWN_HW_IF_CONFIG, IWN_HW_IF_CONFIG_PREPARE); 8713 for (ntries = 0; ntries < 15000; ntries++) { 8714 if (!(IWN_READ(sc, IWN_HW_IF_CONFIG) & 8715 IWN_HW_IF_CONFIG_PREPARE_DONE)) 8716 break; 8717 DELAY(10); 8718 } 8719 if (ntries == 15000) 8720 return ETIMEDOUT; 8721 8722 /* Hardware should be ready now. */ 8723 IWN_SETBITS(sc, IWN_HW_IF_CONFIG, IWN_HW_IF_CONFIG_NIC_READY); 8724 for (ntries = 0; ntries < 5; ntries++) { 8725 if (IWN_READ(sc, IWN_HW_IF_CONFIG) & 8726 IWN_HW_IF_CONFIG_NIC_READY) 8727 return 0; 8728 DELAY(10); 8729 } 8730 return ETIMEDOUT; 8731 } 8732 8733 static int 8734 iwn_hw_init(struct iwn_softc *sc) 8735 { 8736 struct iwn_ops *ops = &sc->ops; 8737 int error, chnl, qid; 8738 8739 DPRINTF(sc, IWN_DEBUG_TRACE, "->%s begin\n", __func__); 8740 8741 /* Clear pending interrupts. */ 8742 IWN_WRITE(sc, IWN_INT, 0xffffffff); 8743 8744 if ((error = iwn_apm_init(sc)) != 0) { 8745 device_printf(sc->sc_dev, 8746 "%s: could not power ON adapter, error %d\n", __func__, 8747 error); 8748 return error; 8749 } 8750 8751 /* Select VMAIN power source. */ 8752 if ((error = iwn_nic_lock(sc)) != 0) 8753 return error; 8754 iwn_prph_clrbits(sc, IWN_APMG_PS, IWN_APMG_PS_PWR_SRC_MASK); 8755 iwn_nic_unlock(sc); 8756 8757 /* Perform adapter-specific initialization. */ 8758 if ((error = ops->nic_config(sc)) != 0) 8759 return error; 8760 8761 /* Initialize RX ring. */ 8762 if ((error = iwn_nic_lock(sc)) != 0) 8763 return error; 8764 IWN_WRITE(sc, IWN_FH_RX_CONFIG, 0); 8765 IWN_WRITE(sc, IWN_FH_RX_WPTR, 0); 8766 /* Set physical address of RX ring (256-byte aligned). */ 8767 IWN_WRITE(sc, IWN_FH_RX_BASE, sc->rxq.desc_dma.paddr >> 8); 8768 /* Set physical address of RX status (16-byte aligned). */ 8769 IWN_WRITE(sc, IWN_FH_STATUS_WPTR, sc->rxq.stat_dma.paddr >> 4); 8770 /* Enable RX. */ 8771 IWN_WRITE(sc, IWN_FH_RX_CONFIG, 8772 IWN_FH_RX_CONFIG_ENA | 8773 IWN_FH_RX_CONFIG_IGN_RXF_EMPTY | /* HW bug workaround */ 8774 IWN_FH_RX_CONFIG_IRQ_DST_HOST | 8775 IWN_FH_RX_CONFIG_SINGLE_FRAME | 8776 IWN_FH_RX_CONFIG_RB_TIMEOUT(0) | 8777 IWN_FH_RX_CONFIG_NRBD(IWN_RX_RING_COUNT_LOG)); 8778 iwn_nic_unlock(sc); 8779 IWN_WRITE(sc, IWN_FH_RX_WPTR, (IWN_RX_RING_COUNT - 1) & ~7); 8780 8781 if ((error = iwn_nic_lock(sc)) != 0) 8782 return error; 8783 8784 /* Initialize TX scheduler. */ 8785 iwn_prph_write(sc, sc->sched_txfact_addr, 0); 8786 8787 /* Set physical address of "keep warm" page (16-byte aligned). */ 8788 IWN_WRITE(sc, IWN_FH_KW_ADDR, sc->kw_dma.paddr >> 4); 8789 8790 /* Initialize TX rings. */ 8791 for (qid = 0; qid < sc->ntxqs; qid++) { 8792 struct iwn_tx_ring *txq = &sc->txq[qid]; 8793 8794 /* Set physical address of TX ring (256-byte aligned). */ 8795 IWN_WRITE(sc, IWN_FH_CBBC_QUEUE(qid), 8796 txq->desc_dma.paddr >> 8); 8797 } 8798 iwn_nic_unlock(sc); 8799 8800 /* Enable DMA channels. */ 8801 for (chnl = 0; chnl < sc->ndmachnls; chnl++) { 8802 IWN_WRITE(sc, IWN_FH_TX_CONFIG(chnl), 8803 IWN_FH_TX_CONFIG_DMA_ENA | 8804 IWN_FH_TX_CONFIG_DMA_CREDIT_ENA); 8805 } 8806 8807 /* Clear "radio off" and "commands blocked" bits. */ 8808 IWN_WRITE(sc, IWN_UCODE_GP1_CLR, IWN_UCODE_GP1_RFKILL); 8809 IWN_WRITE(sc, IWN_UCODE_GP1_CLR, IWN_UCODE_GP1_CMD_BLOCKED); 8810 8811 /* Clear pending interrupts. */ 8812 IWN_WRITE(sc, IWN_INT, 0xffffffff); 8813 /* Enable interrupt coalescing. */ 8814 IWN_WRITE(sc, IWN_INT_COALESCING, 512 / 8); 8815 /* Enable interrupts. */ 8816 IWN_WRITE(sc, IWN_INT_MASK, sc->int_mask); 8817 8818 /* _Really_ make sure "radio off" bit is cleared! */ 8819 IWN_WRITE(sc, IWN_UCODE_GP1_CLR, IWN_UCODE_GP1_RFKILL); 8820 IWN_WRITE(sc, IWN_UCODE_GP1_CLR, IWN_UCODE_GP1_RFKILL); 8821 8822 /* Enable shadow registers. */ 8823 if (sc->base_params->shadow_reg_enable) 8824 IWN_SETBITS(sc, IWN_SHADOW_REG_CTRL, 0x800fffff); 8825 8826 if ((error = ops->load_firmware(sc)) != 0) { 8827 device_printf(sc->sc_dev, 8828 "%s: could not load firmware, error %d\n", __func__, 8829 error); 8830 return error; 8831 } 8832 /* Wait at most one second for firmware alive notification. */ 8833 if ((error = msleep(sc, &sc->sc_mtx, PCATCH, "iwninit", hz)) != 0) { 8834 device_printf(sc->sc_dev, 8835 "%s: timeout waiting for adapter to initialize, error %d\n", 8836 __func__, error); 8837 return error; 8838 } 8839 /* Do post-firmware initialization. */ 8840 8841 DPRINTF(sc, IWN_DEBUG_TRACE, "->%s: end\n",__func__); 8842 8843 return ops->post_alive(sc); 8844 } 8845 8846 static void 8847 iwn_hw_stop(struct iwn_softc *sc) 8848 { 8849 int chnl, qid, ntries; 8850 8851 DPRINTF(sc, IWN_DEBUG_TRACE, "->Doing %s\n", __func__); 8852 8853 IWN_WRITE(sc, IWN_RESET, IWN_RESET_NEVO); 8854 8855 /* Disable interrupts. */ 8856 IWN_WRITE(sc, IWN_INT_MASK, 0); 8857 IWN_WRITE(sc, IWN_INT, 0xffffffff); 8858 IWN_WRITE(sc, IWN_FH_INT, 0xffffffff); 8859 sc->sc_flags &= ~IWN_FLAG_USE_ICT; 8860 8861 /* Make sure we no longer hold the NIC lock. */ 8862 iwn_nic_unlock(sc); 8863 8864 /* Stop TX scheduler. */ 8865 iwn_prph_write(sc, sc->sched_txfact_addr, 0); 8866 8867 /* Stop all DMA channels. */ 8868 if (iwn_nic_lock(sc) == 0) { 8869 for (chnl = 0; chnl < sc->ndmachnls; chnl++) { 8870 IWN_WRITE(sc, IWN_FH_TX_CONFIG(chnl), 0); 8871 for (ntries = 0; ntries < 200; ntries++) { 8872 if (IWN_READ(sc, IWN_FH_TX_STATUS) & 8873 IWN_FH_TX_STATUS_IDLE(chnl)) 8874 break; 8875 DELAY(10); 8876 } 8877 } 8878 iwn_nic_unlock(sc); 8879 } 8880 8881 /* Stop RX ring. */ 8882 iwn_reset_rx_ring(sc, &sc->rxq); 8883 8884 /* Reset all TX rings. */ 8885 for (qid = 0; qid < sc->ntxqs; qid++) 8886 iwn_reset_tx_ring(sc, &sc->txq[qid]); 8887 8888 if (iwn_nic_lock(sc) == 0) { 8889 iwn_prph_write(sc, IWN_APMG_CLK_DIS, 8890 IWN_APMG_CLK_CTRL_DMA_CLK_RQT); 8891 iwn_nic_unlock(sc); 8892 } 8893 DELAY(5); 8894 /* Power OFF adapter. */ 8895 iwn_apm_stop(sc); 8896 } 8897 8898 static void 8899 iwn_panicked(void *arg0, int pending) 8900 { 8901 struct iwn_softc *sc = arg0; 8902 struct ieee80211com *ic = &sc->sc_ic; 8903 struct ieee80211vap *vap = TAILQ_FIRST(&ic->ic_vaps); 8904 #if 0 8905 int error; 8906 #endif 8907 8908 if (vap == NULL) { 8909 printf("%s: null vap\n", __func__); 8910 return; 8911 } 8912 8913 device_printf(sc->sc_dev, "%s: controller panicked, iv_state = %d; " 8914 "restarting\n", __func__, vap->iv_state); 8915 8916 /* 8917 * This is not enough work. We need to also reinitialise 8918 * the correct transmit state for aggregation enabled queues, 8919 * which has a very specific requirement of 8920 * ring index = 802.11 seqno % 256. If we don't do this (which 8921 * we definitely don't!) then the firmware will just panic again. 8922 */ 8923 #if 1 8924 ieee80211_restart_all(ic); 8925 #else 8926 IWN_LOCK(sc); 8927 8928 iwn_stop_locked(sc); 8929 if ((error = iwn_init_locked(sc)) != 0) { 8930 device_printf(sc->sc_dev, 8931 "%s: could not init hardware\n", __func__); 8932 goto unlock; 8933 } 8934 if (vap->iv_state >= IEEE80211_S_AUTH && 8935 (error = iwn_auth(sc, vap)) != 0) { 8936 device_printf(sc->sc_dev, 8937 "%s: could not move to auth state\n", __func__); 8938 } 8939 if (vap->iv_state >= IEEE80211_S_RUN && 8940 (error = iwn_run(sc, vap)) != 0) { 8941 device_printf(sc->sc_dev, 8942 "%s: could not move to run state\n", __func__); 8943 } 8944 8945 unlock: 8946 IWN_UNLOCK(sc); 8947 #endif 8948 } 8949 8950 static int 8951 iwn_init_locked(struct iwn_softc *sc) 8952 { 8953 int error; 8954 8955 DPRINTF(sc, IWN_DEBUG_TRACE, "->%s begin\n", __func__); 8956 8957 IWN_LOCK_ASSERT(sc); 8958 8959 if (sc->sc_flags & IWN_FLAG_RUNNING) 8960 goto end; 8961 8962 sc->sc_flags |= IWN_FLAG_RUNNING; 8963 8964 if ((error = iwn_hw_prepare(sc)) != 0) { 8965 device_printf(sc->sc_dev, "%s: hardware not ready, error %d\n", 8966 __func__, error); 8967 goto fail; 8968 } 8969 8970 /* Initialize interrupt mask to default value. */ 8971 sc->int_mask = IWN_INT_MASK_DEF; 8972 sc->sc_flags &= ~IWN_FLAG_USE_ICT; 8973 8974 /* Check that the radio is not disabled by hardware switch. */ 8975 if (!(IWN_READ(sc, IWN_GP_CNTRL) & IWN_GP_CNTRL_RFKILL)) { 8976 iwn_stop_locked(sc); 8977 DPRINTF(sc, IWN_DEBUG_TRACE, "->%s: end\n",__func__); 8978 8979 return (1); 8980 } 8981 8982 /* Read firmware images from the filesystem. */ 8983 if ((error = iwn_read_firmware(sc)) != 0) { 8984 device_printf(sc->sc_dev, 8985 "%s: could not read firmware, error %d\n", __func__, 8986 error); 8987 goto fail; 8988 } 8989 8990 /* Initialize hardware and upload firmware. */ 8991 error = iwn_hw_init(sc); 8992 iwn_unload_firmware(sc); 8993 if (error != 0) { 8994 device_printf(sc->sc_dev, 8995 "%s: could not initialize hardware, error %d\n", __func__, 8996 error); 8997 goto fail; 8998 } 8999 9000 /* Configure adapter now that it is ready. */ 9001 if ((error = iwn_config(sc)) != 0) { 9002 device_printf(sc->sc_dev, 9003 "%s: could not configure device, error %d\n", __func__, 9004 error); 9005 goto fail; 9006 } 9007 9008 callout_reset(&sc->watchdog_to, hz, iwn_watchdog, sc); 9009 9010 end: 9011 DPRINTF(sc, IWN_DEBUG_TRACE, "->%s: end\n",__func__); 9012 9013 return (0); 9014 9015 fail: 9016 iwn_stop_locked(sc); 9017 9018 DPRINTF(sc, IWN_DEBUG_TRACE, "->%s: end in error\n",__func__); 9019 9020 return (-1); 9021 } 9022 9023 static int 9024 iwn_init(struct iwn_softc *sc) 9025 { 9026 int error; 9027 9028 IWN_LOCK(sc); 9029 error = iwn_init_locked(sc); 9030 IWN_UNLOCK(sc); 9031 9032 return (error); 9033 } 9034 9035 static void 9036 iwn_stop_locked(struct iwn_softc *sc) 9037 { 9038 9039 IWN_LOCK_ASSERT(sc); 9040 9041 if (!(sc->sc_flags & IWN_FLAG_RUNNING)) 9042 return; 9043 9044 sc->sc_is_scanning = 0; 9045 sc->sc_tx_timer = 0; 9046 callout_stop(&sc->watchdog_to); 9047 callout_stop(&sc->scan_timeout); 9048 callout_stop(&sc->calib_to); 9049 sc->sc_flags &= ~IWN_FLAG_RUNNING; 9050 9051 /* Power OFF hardware. */ 9052 iwn_hw_stop(sc); 9053 } 9054 9055 static void 9056 iwn_stop(struct iwn_softc *sc) 9057 { 9058 IWN_LOCK(sc); 9059 iwn_stop_locked(sc); 9060 IWN_UNLOCK(sc); 9061 } 9062 9063 /* 9064 * Callback from net80211 to start a scan. 9065 */ 9066 static void 9067 iwn_scan_start(struct ieee80211com *ic) 9068 { 9069 struct iwn_softc *sc = ic->ic_softc; 9070 9071 IWN_LOCK(sc); 9072 /* make the link LED blink while we're scanning */ 9073 iwn_set_led(sc, IWN_LED_LINK, 20, 2); 9074 IWN_UNLOCK(sc); 9075 } 9076 9077 /* 9078 * Callback from net80211 to terminate a scan. 9079 */ 9080 static void 9081 iwn_scan_end(struct ieee80211com *ic) 9082 { 9083 struct iwn_softc *sc = ic->ic_softc; 9084 struct ieee80211vap *vap = TAILQ_FIRST(&ic->ic_vaps); 9085 9086 IWN_LOCK(sc); 9087 if (vap->iv_state == IEEE80211_S_RUN) { 9088 /* Set link LED to ON status if we are associated */ 9089 iwn_set_led(sc, IWN_LED_LINK, 0, 1); 9090 } 9091 IWN_UNLOCK(sc); 9092 } 9093 9094 /* 9095 * Callback from net80211 to force a channel change. 9096 */ 9097 static void 9098 iwn_set_channel(struct ieee80211com *ic) 9099 { 9100 struct iwn_softc *sc = ic->ic_softc; 9101 int error; 9102 9103 DPRINTF(sc, IWN_DEBUG_TRACE, "->Doing %s\n", __func__); 9104 9105 IWN_LOCK(sc); 9106 /* 9107 * Only need to set the channel in Monitor mode. AP scanning and auth 9108 * are already taken care of by their respective firmware commands. 9109 */ 9110 if (ic->ic_opmode == IEEE80211_M_MONITOR) { 9111 error = iwn_config(sc); 9112 if (error != 0) 9113 device_printf(sc->sc_dev, 9114 "%s: error %d setting channel\n", __func__, error); 9115 } 9116 IWN_UNLOCK(sc); 9117 } 9118 9119 /* 9120 * Callback from net80211 to start scanning of the current channel. 9121 */ 9122 static void 9123 iwn_scan_curchan(struct ieee80211_scan_state *ss, unsigned long maxdwell) 9124 { 9125 struct ieee80211vap *vap = ss->ss_vap; 9126 struct ieee80211com *ic = vap->iv_ic; 9127 struct iwn_softc *sc = ic->ic_softc; 9128 int error; 9129 9130 IWN_LOCK(sc); 9131 error = iwn_scan(sc, vap, ss, ic->ic_curchan); 9132 IWN_UNLOCK(sc); 9133 if (error != 0) 9134 ieee80211_cancel_scan(vap); 9135 } 9136 9137 /* 9138 * Callback from net80211 to handle the minimum dwell time being met. 9139 * The intent is to terminate the scan but we just let the firmware 9140 * notify us when it's finished as we have no safe way to abort it. 9141 */ 9142 static void 9143 iwn_scan_mindwell(struct ieee80211_scan_state *ss) 9144 { 9145 /* NB: don't try to abort scan; wait for firmware to finish */ 9146 } 9147 #ifdef IWN_DEBUG 9148 #define IWN_DESC(x) case x: return #x 9149 9150 /* 9151 * Translate CSR code to string 9152 */ 9153 static char *iwn_get_csr_string(int csr) 9154 { 9155 switch (csr) { 9156 IWN_DESC(IWN_HW_IF_CONFIG); 9157 IWN_DESC(IWN_INT_COALESCING); 9158 IWN_DESC(IWN_INT); 9159 IWN_DESC(IWN_INT_MASK); 9160 IWN_DESC(IWN_FH_INT); 9161 IWN_DESC(IWN_GPIO_IN); 9162 IWN_DESC(IWN_RESET); 9163 IWN_DESC(IWN_GP_CNTRL); 9164 IWN_DESC(IWN_HW_REV); 9165 IWN_DESC(IWN_EEPROM); 9166 IWN_DESC(IWN_EEPROM_GP); 9167 IWN_DESC(IWN_OTP_GP); 9168 IWN_DESC(IWN_GIO); 9169 IWN_DESC(IWN_GP_UCODE); 9170 IWN_DESC(IWN_GP_DRIVER); 9171 IWN_DESC(IWN_UCODE_GP1); 9172 IWN_DESC(IWN_UCODE_GP2); 9173 IWN_DESC(IWN_LED); 9174 IWN_DESC(IWN_DRAM_INT_TBL); 9175 IWN_DESC(IWN_GIO_CHICKEN); 9176 IWN_DESC(IWN_ANA_PLL); 9177 IWN_DESC(IWN_HW_REV_WA); 9178 IWN_DESC(IWN_DBG_HPET_MEM); 9179 default: 9180 return "UNKNOWN CSR"; 9181 } 9182 } 9183 9184 /* 9185 * This function print firmware register 9186 */ 9187 static void 9188 iwn_debug_register(struct iwn_softc *sc) 9189 { 9190 int i; 9191 static const uint32_t csr_tbl[] = { 9192 IWN_HW_IF_CONFIG, 9193 IWN_INT_COALESCING, 9194 IWN_INT, 9195 IWN_INT_MASK, 9196 IWN_FH_INT, 9197 IWN_GPIO_IN, 9198 IWN_RESET, 9199 IWN_GP_CNTRL, 9200 IWN_HW_REV, 9201 IWN_EEPROM, 9202 IWN_EEPROM_GP, 9203 IWN_OTP_GP, 9204 IWN_GIO, 9205 IWN_GP_UCODE, 9206 IWN_GP_DRIVER, 9207 IWN_UCODE_GP1, 9208 IWN_UCODE_GP2, 9209 IWN_LED, 9210 IWN_DRAM_INT_TBL, 9211 IWN_GIO_CHICKEN, 9212 IWN_ANA_PLL, 9213 IWN_HW_REV_WA, 9214 IWN_DBG_HPET_MEM, 9215 }; 9216 DPRINTF(sc, IWN_DEBUG_REGISTER, 9217 "CSR values: (2nd byte of IWN_INT_COALESCING is IWN_INT_PERIODIC)%s", 9218 "\n"); 9219 for (i = 0; i < nitems(csr_tbl); i++){ 9220 DPRINTF(sc, IWN_DEBUG_REGISTER," %10s: 0x%08x ", 9221 iwn_get_csr_string(csr_tbl[i]), IWN_READ(sc, csr_tbl[i])); 9222 if ((i+1) % 3 == 0) 9223 DPRINTF(sc, IWN_DEBUG_REGISTER,"%s","\n"); 9224 } 9225 DPRINTF(sc, IWN_DEBUG_REGISTER,"%s","\n"); 9226 } 9227 #endif 9228 9229 9230