1 /*- 2 * Copyright (c) 2007-2009 3 * Damien Bergamini <damien.bergamini@free.fr> 4 * Copyright (c) 2008 5 * Benjamin Close <benjsc@FreeBSD.org> 6 * Copyright (c) 2008 Sam Leffler, Errno Consulting 7 * 8 * Permission to use, copy, modify, and distribute this software for any 9 * purpose with or without fee is hereby granted, provided that the above 10 * copyright notice and this permission notice appear in all copies. 11 * 12 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 13 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 14 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR 15 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 16 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN 17 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF 18 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 19 */ 20 21 /* 22 * Driver for Intel WiFi Link 4965 and 1000/5000/6000 Series 802.11 network 23 * adapters. 24 */ 25 26 #include <sys/cdefs.h> 27 __FBSDID("$FreeBSD$"); 28 29 #include <sys/param.h> 30 #include <sys/sockio.h> 31 #include <sys/sysctl.h> 32 #include <sys/mbuf.h> 33 #include <sys/kernel.h> 34 #include <sys/socket.h> 35 #include <sys/systm.h> 36 #include <sys/malloc.h> 37 #include <sys/bus.h> 38 #include <sys/rman.h> 39 #include <sys/endian.h> 40 #include <sys/firmware.h> 41 #include <sys/limits.h> 42 #include <sys/module.h> 43 #include <sys/queue.h> 44 #include <sys/taskqueue.h> 45 46 #include <machine/bus.h> 47 #include <machine/resource.h> 48 #include <machine/clock.h> 49 50 #include <dev/pci/pcireg.h> 51 #include <dev/pci/pcivar.h> 52 53 #include <net/bpf.h> 54 #include <net/if.h> 55 #include <net/if_arp.h> 56 #include <net/ethernet.h> 57 #include <net/if_dl.h> 58 #include <net/if_media.h> 59 #include <net/if_types.h> 60 61 #include <netinet/in.h> 62 #include <netinet/in_systm.h> 63 #include <netinet/in_var.h> 64 #include <netinet/if_ether.h> 65 #include <netinet/ip.h> 66 67 #include <net80211/ieee80211_var.h> 68 #include <net80211/ieee80211_radiotap.h> 69 #include <net80211/ieee80211_regdomain.h> 70 #include <net80211/ieee80211_ratectl.h> 71 72 #include <dev/iwn/if_iwnreg.h> 73 #include <dev/iwn/if_iwnvar.h> 74 75 static int iwn_probe(device_t); 76 static int iwn_attach(device_t); 77 static const struct iwn_hal *iwn_hal_attach(struct iwn_softc *); 78 static void iwn_radiotap_attach(struct iwn_softc *); 79 static struct ieee80211vap *iwn_vap_create(struct ieee80211com *, 80 const char name[IFNAMSIZ], int unit, int opmode, 81 int flags, const uint8_t bssid[IEEE80211_ADDR_LEN], 82 const uint8_t mac[IEEE80211_ADDR_LEN]); 83 static void iwn_vap_delete(struct ieee80211vap *); 84 static int iwn_cleanup(device_t); 85 static int iwn_detach(device_t); 86 static int iwn_nic_lock(struct iwn_softc *); 87 static int iwn_eeprom_lock(struct iwn_softc *); 88 static int iwn_init_otprom(struct iwn_softc *); 89 static int iwn_read_prom_data(struct iwn_softc *, uint32_t, void *, int); 90 static void iwn_dma_map_addr(void *, bus_dma_segment_t *, int, int); 91 static int iwn_dma_contig_alloc(struct iwn_softc *, struct iwn_dma_info *, 92 void **, bus_size_t, bus_size_t, int); 93 static void iwn_dma_contig_free(struct iwn_dma_info *); 94 static int iwn_alloc_sched(struct iwn_softc *); 95 static void iwn_free_sched(struct iwn_softc *); 96 static int iwn_alloc_kw(struct iwn_softc *); 97 static void iwn_free_kw(struct iwn_softc *); 98 static int iwn_alloc_ict(struct iwn_softc *); 99 static void iwn_free_ict(struct iwn_softc *); 100 static int iwn_alloc_fwmem(struct iwn_softc *); 101 static void iwn_free_fwmem(struct iwn_softc *); 102 static int iwn_alloc_rx_ring(struct iwn_softc *, struct iwn_rx_ring *); 103 static void iwn_reset_rx_ring(struct iwn_softc *, struct iwn_rx_ring *); 104 static void iwn_free_rx_ring(struct iwn_softc *, struct iwn_rx_ring *); 105 static int iwn_alloc_tx_ring(struct iwn_softc *, struct iwn_tx_ring *, 106 int); 107 static void iwn_reset_tx_ring(struct iwn_softc *, struct iwn_tx_ring *); 108 static void iwn_free_tx_ring(struct iwn_softc *, struct iwn_tx_ring *); 109 static void iwn5000_ict_reset(struct iwn_softc *); 110 static int iwn_read_eeprom(struct iwn_softc *, 111 uint8_t macaddr[IEEE80211_ADDR_LEN]); 112 static void iwn4965_read_eeprom(struct iwn_softc *); 113 static void iwn4965_print_power_group(struct iwn_softc *, int); 114 static void iwn5000_read_eeprom(struct iwn_softc *); 115 static uint32_t iwn_eeprom_channel_flags(struct iwn_eeprom_chan *); 116 static void iwn_read_eeprom_band(struct iwn_softc *, int); 117 #if 0 /* HT */ 118 static void iwn_read_eeprom_ht40(struct iwn_softc *, int); 119 #endif 120 static void iwn_read_eeprom_channels(struct iwn_softc *, int, 121 uint32_t); 122 static void iwn_read_eeprom_enhinfo(struct iwn_softc *); 123 static struct ieee80211_node *iwn_node_alloc(struct ieee80211vap *, 124 const uint8_t mac[IEEE80211_ADDR_LEN]); 125 static void iwn_newassoc(struct ieee80211_node *, int); 126 static int iwn_media_change(struct ifnet *); 127 static int iwn_newstate(struct ieee80211vap *, enum ieee80211_state, int); 128 static void iwn_rx_phy(struct iwn_softc *, struct iwn_rx_desc *, 129 struct iwn_rx_data *); 130 static void iwn_timer_timeout(void *); 131 static void iwn_calib_reset(struct iwn_softc *); 132 static void iwn_rx_done(struct iwn_softc *, struct iwn_rx_desc *, 133 struct iwn_rx_data *); 134 #if 0 /* HT */ 135 static void iwn_rx_compressed_ba(struct iwn_softc *, struct iwn_rx_desc *, 136 struct iwn_rx_data *); 137 #endif 138 static void iwn5000_rx_calib_results(struct iwn_softc *, 139 struct iwn_rx_desc *, struct iwn_rx_data *); 140 static void iwn_rx_statistics(struct iwn_softc *, struct iwn_rx_desc *, 141 struct iwn_rx_data *); 142 static void iwn4965_tx_done(struct iwn_softc *, struct iwn_rx_desc *, 143 struct iwn_rx_data *); 144 static void iwn5000_tx_done(struct iwn_softc *, struct iwn_rx_desc *, 145 struct iwn_rx_data *); 146 static void iwn_tx_done(struct iwn_softc *, struct iwn_rx_desc *, int, 147 uint8_t); 148 static void iwn_cmd_done(struct iwn_softc *, struct iwn_rx_desc *); 149 static void iwn_notif_intr(struct iwn_softc *); 150 static void iwn_wakeup_intr(struct iwn_softc *); 151 static void iwn_rftoggle_intr(struct iwn_softc *); 152 static void iwn_fatal_intr(struct iwn_softc *); 153 static void iwn_intr(void *); 154 static void iwn4965_update_sched(struct iwn_softc *, int, int, uint8_t, 155 uint16_t); 156 static void iwn5000_update_sched(struct iwn_softc *, int, int, uint8_t, 157 uint16_t); 158 #ifdef notyet 159 static void iwn5000_reset_sched(struct iwn_softc *, int, int); 160 #endif 161 static uint8_t iwn_plcp_signal(int); 162 static int iwn_tx_data(struct iwn_softc *, struct mbuf *, 163 struct ieee80211_node *, struct iwn_tx_ring *); 164 static int iwn_raw_xmit(struct ieee80211_node *, struct mbuf *, 165 const struct ieee80211_bpf_params *); 166 static void iwn_start(struct ifnet *); 167 static void iwn_start_locked(struct ifnet *); 168 static void iwn_watchdog(struct iwn_softc *sc); 169 static int iwn_ioctl(struct ifnet *, u_long, caddr_t); 170 static int iwn_cmd(struct iwn_softc *, int, const void *, int, int); 171 static int iwn4965_add_node(struct iwn_softc *, struct iwn_node_info *, 172 int); 173 static int iwn5000_add_node(struct iwn_softc *, struct iwn_node_info *, 174 int); 175 static int iwn_set_link_quality(struct iwn_softc *, uint8_t, int); 176 static int iwn_add_broadcast_node(struct iwn_softc *, int); 177 static int iwn_wme_update(struct ieee80211com *); 178 static void iwn_update_mcast(struct ifnet *); 179 static void iwn_set_led(struct iwn_softc *, uint8_t, uint8_t, uint8_t); 180 static int iwn_set_critical_temp(struct iwn_softc *); 181 static int iwn_set_timing(struct iwn_softc *, struct ieee80211_node *); 182 static void iwn4965_power_calibration(struct iwn_softc *, int); 183 static int iwn4965_set_txpower(struct iwn_softc *, 184 struct ieee80211_channel *, int); 185 static int iwn5000_set_txpower(struct iwn_softc *, 186 struct ieee80211_channel *, int); 187 static int iwn4965_get_rssi(struct iwn_softc *, struct iwn_rx_stat *); 188 static int iwn5000_get_rssi(struct iwn_softc *, struct iwn_rx_stat *); 189 static int iwn_get_noise(const struct iwn_rx_general_stats *); 190 static int iwn4965_get_temperature(struct iwn_softc *); 191 static int iwn5000_get_temperature(struct iwn_softc *); 192 static int iwn_init_sensitivity(struct iwn_softc *); 193 static void iwn_collect_noise(struct iwn_softc *, 194 const struct iwn_rx_general_stats *); 195 static int iwn4965_init_gains(struct iwn_softc *); 196 static int iwn5000_init_gains(struct iwn_softc *); 197 static int iwn4965_set_gains(struct iwn_softc *); 198 static int iwn5000_set_gains(struct iwn_softc *); 199 static void iwn_tune_sensitivity(struct iwn_softc *, 200 const struct iwn_rx_stats *); 201 static int iwn_send_sensitivity(struct iwn_softc *); 202 static int iwn_set_pslevel(struct iwn_softc *, int, int, int); 203 static int iwn_config(struct iwn_softc *); 204 static int iwn_scan(struct iwn_softc *); 205 static int iwn_auth(struct iwn_softc *, struct ieee80211vap *vap); 206 static int iwn_run(struct iwn_softc *, struct ieee80211vap *vap); 207 #if 0 /* HT */ 208 static int iwn_ampdu_rx_start(struct ieee80211com *, 209 struct ieee80211_node *, uint8_t); 210 static void iwn_ampdu_rx_stop(struct ieee80211com *, 211 struct ieee80211_node *, uint8_t); 212 static int iwn_ampdu_tx_start(struct ieee80211com *, 213 struct ieee80211_node *, uint8_t); 214 static void iwn_ampdu_tx_stop(struct ieee80211com *, 215 struct ieee80211_node *, uint8_t); 216 static void iwn4965_ampdu_tx_start(struct iwn_softc *, 217 struct ieee80211_node *, uint8_t, uint16_t); 218 static void iwn4965_ampdu_tx_stop(struct iwn_softc *, uint8_t, uint16_t); 219 static void iwn5000_ampdu_tx_start(struct iwn_softc *, 220 struct ieee80211_node *, uint8_t, uint16_t); 221 static void iwn5000_ampdu_tx_stop(struct iwn_softc *, uint8_t, uint16_t); 222 #endif 223 static int iwn5000_query_calibration(struct iwn_softc *); 224 static int iwn5000_send_calibration(struct iwn_softc *); 225 static int iwn5000_send_wimax_coex(struct iwn_softc *); 226 static int iwn4965_post_alive(struct iwn_softc *); 227 static int iwn5000_post_alive(struct iwn_softc *); 228 static int iwn4965_load_bootcode(struct iwn_softc *, const uint8_t *, 229 int); 230 static int iwn4965_load_firmware(struct iwn_softc *); 231 static int iwn5000_load_firmware_section(struct iwn_softc *, uint32_t, 232 const uint8_t *, int); 233 static int iwn5000_load_firmware(struct iwn_softc *); 234 static int iwn_read_firmware_leg(struct iwn_softc *, 235 struct iwn_fw_info *); 236 static int iwn_read_firmware_tlv(struct iwn_softc *, 237 struct iwn_fw_info *, uint16_t); 238 static int iwn_read_firmware(struct iwn_softc *); 239 static int iwn_clock_wait(struct iwn_softc *); 240 static int iwn_apm_init(struct iwn_softc *); 241 static void iwn_apm_stop_master(struct iwn_softc *); 242 static void iwn_apm_stop(struct iwn_softc *); 243 static int iwn4965_nic_config(struct iwn_softc *); 244 static int iwn5000_nic_config(struct iwn_softc *); 245 static int iwn_hw_prepare(struct iwn_softc *); 246 static int iwn_hw_init(struct iwn_softc *); 247 static void iwn_hw_stop(struct iwn_softc *); 248 static void iwn_init_locked(struct iwn_softc *); 249 static void iwn_init(void *); 250 static void iwn_stop_locked(struct iwn_softc *); 251 static void iwn_stop(struct iwn_softc *); 252 static void iwn_scan_start(struct ieee80211com *); 253 static void iwn_scan_end(struct ieee80211com *); 254 static void iwn_set_channel(struct ieee80211com *); 255 static void iwn_scan_curchan(struct ieee80211_scan_state *, unsigned long); 256 static void iwn_scan_mindwell(struct ieee80211_scan_state *); 257 static struct iwn_eeprom_chan *iwn_find_eeprom_channel(struct iwn_softc *, 258 struct ieee80211_channel *); 259 static int iwn_setregdomain(struct ieee80211com *, 260 struct ieee80211_regdomain *, int, 261 struct ieee80211_channel []); 262 static void iwn_hw_reset(void *, int); 263 static void iwn_radio_on(void *, int); 264 static void iwn_radio_off(void *, int); 265 static void iwn_sysctlattach(struct iwn_softc *); 266 static int iwn_shutdown(device_t); 267 static int iwn_suspend(device_t); 268 static int iwn_resume(device_t); 269 270 #define IWN_DEBUG 271 #ifdef IWN_DEBUG 272 enum { 273 IWN_DEBUG_XMIT = 0x00000001, /* basic xmit operation */ 274 IWN_DEBUG_RECV = 0x00000002, /* basic recv operation */ 275 IWN_DEBUG_STATE = 0x00000004, /* 802.11 state transitions */ 276 IWN_DEBUG_TXPOW = 0x00000008, /* tx power processing */ 277 IWN_DEBUG_RESET = 0x00000010, /* reset processing */ 278 IWN_DEBUG_OPS = 0x00000020, /* iwn_ops processing */ 279 IWN_DEBUG_BEACON = 0x00000040, /* beacon handling */ 280 IWN_DEBUG_WATCHDOG = 0x00000080, /* watchdog timeout */ 281 IWN_DEBUG_INTR = 0x00000100, /* ISR */ 282 IWN_DEBUG_CALIBRATE = 0x00000200, /* periodic calibration */ 283 IWN_DEBUG_NODE = 0x00000400, /* node management */ 284 IWN_DEBUG_LED = 0x00000800, /* led management */ 285 IWN_DEBUG_CMD = 0x00001000, /* cmd submission */ 286 IWN_DEBUG_FATAL = 0x80000000, /* fatal errors */ 287 IWN_DEBUG_ANY = 0xffffffff 288 }; 289 290 #define DPRINTF(sc, m, fmt, ...) do { \ 291 if (sc->sc_debug & (m)) \ 292 printf(fmt, __VA_ARGS__); \ 293 } while (0) 294 295 static const char *iwn_intr_str(uint8_t); 296 #else 297 #define DPRINTF(sc, m, fmt, ...) do { (void) sc; } while (0) 298 #endif 299 300 struct iwn_ident { 301 uint16_t vendor; 302 uint16_t device; 303 const char *name; 304 }; 305 306 static const struct iwn_ident iwn_ident_table [] = { 307 { 0x8086, 0x4229, "Intel(R) PRO/Wireless 4965BGN" }, 308 { 0x8086, 0x422D, "Intel(R) PRO/Wireless 4965BGN" }, 309 { 0x8086, 0x4230, "Intel(R) PRO/Wireless 4965BGN" }, 310 { 0x8086, 0x4233, "Intel(R) PRO/Wireless 4965BGN" }, 311 { 0x8086, 0x4232, "Intel(R) PRO/Wireless 5100" }, 312 { 0x8086, 0x4237, "Intel(R) PRO/Wireless 5100" }, 313 { 0x8086, 0x423C, "Intel(R) PRO/Wireless 5150" }, 314 { 0x8086, 0x423D, "Intel(R) PRO/Wireless 5150" }, 315 { 0x8086, 0x4235, "Intel(R) PRO/Wireless 5300" }, 316 { 0x8086, 0x4236, "Intel(R) PRO/Wireless 5300" }, 317 { 0x8086, 0x423A, "Intel(R) PRO/Wireless 5350" }, 318 { 0x8086, 0x423B, "Intel(R) PRO/Wireless 5350" }, 319 { 0x8086, 0x0083, "Intel(R) PRO/Wireless 1000" }, 320 { 0x8086, 0x0084, "Intel(R) PRO/Wireless 1000" }, 321 { 0x8086, 0x008D, "Intel(R) PRO/Wireless 6000" }, 322 { 0x8086, 0x008E, "Intel(R) PRO/Wireless 6000" }, 323 { 0x8086, 0x4238, "Intel(R) PRO/Wireless 6000" }, 324 { 0x8086, 0x4239, "Intel(R) PRO/Wireless 6000" }, 325 { 0x8086, 0x422B, "Intel(R) PRO/Wireless 6000" }, 326 { 0x8086, 0x422C, "Intel(R) PRO/Wireless 6000" }, 327 { 0x8086, 0x0087, "Intel(R) PRO/Wireless 6250" }, 328 { 0x8086, 0x0089, "Intel(R) PRO/Wireless 6250" }, 329 { 0x8086, 0x0082, "Intel(R) PRO/Wireless 6205a" }, 330 { 0x8086, 0x0085, "Intel(R) PRO/Wireless 6205a" }, 331 #ifdef notyet 332 { 0x8086, 0x008a, "Intel(R) PRO/Wireless 6205b" }, 333 { 0x8086, 0x008b, "Intel(R) PRO/Wireless 6205b" }, 334 { 0x8086, 0x008f, "Intel(R) PRO/Wireless 6205b" }, 335 { 0x8086, 0x0090, "Intel(R) PRO/Wireless 6205b" }, 336 { 0x8086, 0x0091, "Intel(R) PRO/Wireless 6205b" }, 337 #endif 338 { 0, 0, NULL } 339 }; 340 341 static const struct iwn_hal iwn4965_hal = { 342 iwn4965_load_firmware, 343 iwn4965_read_eeprom, 344 iwn4965_post_alive, 345 iwn4965_nic_config, 346 iwn4965_update_sched, 347 iwn4965_get_temperature, 348 iwn4965_get_rssi, 349 iwn4965_set_txpower, 350 iwn4965_init_gains, 351 iwn4965_set_gains, 352 iwn4965_add_node, 353 iwn4965_tx_done, 354 #if 0 /* HT */ 355 iwn4965_ampdu_tx_start, 356 iwn4965_ampdu_tx_stop, 357 #endif 358 IWN4965_NTXQUEUES, 359 IWN4965_NDMACHNLS, 360 IWN4965_ID_BROADCAST, 361 IWN4965_RXONSZ, 362 IWN4965_SCHEDSZ, 363 IWN4965_FW_TEXT_MAXSZ, 364 IWN4965_FW_DATA_MAXSZ, 365 IWN4965_FWSZ, 366 IWN4965_SCHED_TXFACT 367 }; 368 369 static const struct iwn_hal iwn5000_hal = { 370 iwn5000_load_firmware, 371 iwn5000_read_eeprom, 372 iwn5000_post_alive, 373 iwn5000_nic_config, 374 iwn5000_update_sched, 375 iwn5000_get_temperature, 376 iwn5000_get_rssi, 377 iwn5000_set_txpower, 378 iwn5000_init_gains, 379 iwn5000_set_gains, 380 iwn5000_add_node, 381 iwn5000_tx_done, 382 #if 0 /* HT */ 383 iwn5000_ampdu_tx_start, 384 iwn5000_ampdu_tx_stop, 385 #endif 386 IWN5000_NTXQUEUES, 387 IWN5000_NDMACHNLS, 388 IWN5000_ID_BROADCAST, 389 IWN5000_RXONSZ, 390 IWN5000_SCHEDSZ, 391 IWN5000_FW_TEXT_MAXSZ, 392 IWN5000_FW_DATA_MAXSZ, 393 IWN5000_FWSZ, 394 IWN5000_SCHED_TXFACT 395 }; 396 397 static int 398 iwn_probe(device_t dev) 399 { 400 const struct iwn_ident *ident; 401 402 for (ident = iwn_ident_table; ident->name != NULL; ident++) { 403 if (pci_get_vendor(dev) == ident->vendor && 404 pci_get_device(dev) == ident->device) { 405 device_set_desc(dev, ident->name); 406 return 0; 407 } 408 } 409 return ENXIO; 410 } 411 412 static int 413 iwn_attach(device_t dev) 414 { 415 struct iwn_softc *sc = (struct iwn_softc *)device_get_softc(dev); 416 struct ieee80211com *ic; 417 struct ifnet *ifp; 418 const struct iwn_hal *hal; 419 uint32_t tmp; 420 int i, error, result; 421 uint8_t macaddr[IEEE80211_ADDR_LEN]; 422 423 sc->sc_dev = dev; 424 425 /* 426 * Get the offset of the PCI Express Capability Structure in PCI 427 * Configuration Space. 428 */ 429 error = pci_find_extcap(dev, PCIY_EXPRESS, &sc->sc_cap_off); 430 if (error != 0) { 431 device_printf(dev, "PCIe capability structure not found!\n"); 432 return error; 433 } 434 435 /* Clear device-specific "PCI retry timeout" register (41h). */ 436 pci_write_config(dev, 0x41, 0, 1); 437 438 /* Hardware bug workaround. */ 439 tmp = pci_read_config(dev, PCIR_COMMAND, 1); 440 if (tmp & PCIM_CMD_INTxDIS) { 441 DPRINTF(sc, IWN_DEBUG_RESET, "%s: PCIe INTx Disable set\n", 442 __func__); 443 tmp &= ~PCIM_CMD_INTxDIS; 444 pci_write_config(dev, PCIR_COMMAND, tmp, 1); 445 } 446 447 /* Enable bus-mastering. */ 448 pci_enable_busmaster(dev); 449 450 sc->mem_rid = PCIR_BAR(0); 451 sc->mem = bus_alloc_resource_any(dev, SYS_RES_MEMORY, &sc->mem_rid, 452 RF_ACTIVE); 453 if (sc->mem == NULL ) { 454 device_printf(dev, "could not allocate memory resources\n"); 455 error = ENOMEM; 456 return error; 457 } 458 459 sc->sc_st = rman_get_bustag(sc->mem); 460 sc->sc_sh = rman_get_bushandle(sc->mem); 461 sc->irq_rid = 0; 462 if ((result = pci_msi_count(dev)) == 1 && 463 pci_alloc_msi(dev, &result) == 0) 464 sc->irq_rid = 1; 465 sc->irq = bus_alloc_resource_any(dev, SYS_RES_IRQ, &sc->irq_rid, 466 RF_ACTIVE | RF_SHAREABLE); 467 if (sc->irq == NULL) { 468 device_printf(dev, "could not allocate interrupt resource\n"); 469 error = ENOMEM; 470 goto fail; 471 } 472 473 IWN_LOCK_INIT(sc); 474 callout_init_mtx(&sc->sc_timer_to, &sc->sc_mtx, 0); 475 TASK_INIT(&sc->sc_reinit_task, 0, iwn_hw_reset, sc ); 476 TASK_INIT(&sc->sc_radioon_task, 0, iwn_radio_on, sc ); 477 TASK_INIT(&sc->sc_radiooff_task, 0, iwn_radio_off, sc ); 478 479 /* Attach Hardware Abstraction Layer. */ 480 hal = iwn_hal_attach(sc); 481 if (hal == NULL) { 482 error = ENXIO; /* XXX: Wrong error code? */ 483 goto fail; 484 } 485 486 error = iwn_hw_prepare(sc); 487 if (error != 0) { 488 device_printf(dev, "hardware not ready, error %d\n", error); 489 goto fail; 490 } 491 492 /* Allocate DMA memory for firmware transfers. */ 493 error = iwn_alloc_fwmem(sc); 494 if (error != 0) { 495 device_printf(dev, 496 "could not allocate memory for firmware, error %d\n", 497 error); 498 goto fail; 499 } 500 501 /* Allocate "Keep Warm" page. */ 502 error = iwn_alloc_kw(sc); 503 if (error != 0) { 504 device_printf(dev, 505 "could not allocate \"Keep Warm\" page, error %d\n", error); 506 goto fail; 507 } 508 509 /* Allocate ICT table for 5000 Series. */ 510 if (sc->hw_type != IWN_HW_REV_TYPE_4965 && 511 (error = iwn_alloc_ict(sc)) != 0) { 512 device_printf(dev, 513 "%s: could not allocate ICT table, error %d\n", 514 __func__, error); 515 goto fail; 516 } 517 518 /* Allocate TX scheduler "rings". */ 519 error = iwn_alloc_sched(sc); 520 if (error != 0) { 521 device_printf(dev, 522 "could not allocate TX scheduler rings, error %d\n", 523 error); 524 goto fail; 525 } 526 527 /* Allocate TX rings (16 on 4965AGN, 20 on 5000). */ 528 for (i = 0; i < hal->ntxqs; i++) { 529 error = iwn_alloc_tx_ring(sc, &sc->txq[i], i); 530 if (error != 0) { 531 device_printf(dev, 532 "could not allocate Tx ring %d, error %d\n", 533 i, error); 534 goto fail; 535 } 536 } 537 538 /* Allocate RX ring. */ 539 error = iwn_alloc_rx_ring(sc, &sc->rxq); 540 if (error != 0 ){ 541 device_printf(dev, 542 "could not allocate Rx ring, error %d\n", error); 543 goto fail; 544 } 545 546 /* Clear pending interrupts. */ 547 IWN_WRITE(sc, IWN_INT, 0xffffffff); 548 549 /* Count the number of available chains. */ 550 sc->ntxchains = 551 ((sc->txchainmask >> 2) & 1) + 552 ((sc->txchainmask >> 1) & 1) + 553 ((sc->txchainmask >> 0) & 1); 554 sc->nrxchains = 555 ((sc->rxchainmask >> 2) & 1) + 556 ((sc->rxchainmask >> 1) & 1) + 557 ((sc->rxchainmask >> 0) & 1); 558 559 ifp = sc->sc_ifp = if_alloc(IFT_IEEE80211); 560 if (ifp == NULL) { 561 device_printf(dev, "can not allocate ifnet structure\n"); 562 goto fail; 563 } 564 ic = ifp->if_l2com; 565 566 ic->ic_ifp = ifp; 567 ic->ic_phytype = IEEE80211_T_OFDM; /* not only, but not used */ 568 ic->ic_opmode = IEEE80211_M_STA; /* default to BSS mode */ 569 570 /* Set device capabilities. */ 571 ic->ic_caps = 572 IEEE80211_C_STA /* station mode supported */ 573 | IEEE80211_C_MONITOR /* monitor mode supported */ 574 | IEEE80211_C_TXPMGT /* tx power management */ 575 | IEEE80211_C_SHSLOT /* short slot time supported */ 576 | IEEE80211_C_WPA 577 | IEEE80211_C_SHPREAMBLE /* short preamble supported */ 578 | IEEE80211_C_BGSCAN /* background scanning */ 579 #if 0 580 | IEEE80211_C_IBSS /* ibss/adhoc mode */ 581 #endif 582 | IEEE80211_C_WME /* WME */ 583 ; 584 #if 0 /* HT */ 585 /* XXX disable until HT channel setup works */ 586 ic->ic_htcaps = 587 IEEE80211_HTCAP_SMPS_ENA /* SM PS mode enabled */ 588 | IEEE80211_HTCAP_CHWIDTH40 /* 40MHz channel width */ 589 | IEEE80211_HTCAP_SHORTGI20 /* short GI in 20MHz */ 590 | IEEE80211_HTCAP_SHORTGI40 /* short GI in 40MHz */ 591 | IEEE80211_HTCAP_RXSTBC_2STREAM/* 1-2 spatial streams */ 592 | IEEE80211_HTCAP_MAXAMSDU_3839 /* max A-MSDU length */ 593 /* s/w capabilities */ 594 | IEEE80211_HTC_HT /* HT operation */ 595 | IEEE80211_HTC_AMPDU /* tx A-MPDU */ 596 | IEEE80211_HTC_AMSDU /* tx A-MSDU */ 597 ; 598 599 /* Set HT capabilities. */ 600 ic->ic_htcaps = 601 #if IWN_RBUF_SIZE == 8192 602 IEEE80211_HTCAP_AMSDU7935 | 603 #endif 604 IEEE80211_HTCAP_CBW20_40 | 605 IEEE80211_HTCAP_SGI20 | 606 IEEE80211_HTCAP_SGI40; 607 if (sc->hw_type != IWN_HW_REV_TYPE_4965) 608 ic->ic_htcaps |= IEEE80211_HTCAP_GF; 609 if (sc->hw_type == IWN_HW_REV_TYPE_6050) 610 ic->ic_htcaps |= IEEE80211_HTCAP_SMPS_DYN; 611 else 612 ic->ic_htcaps |= IEEE80211_HTCAP_SMPS_DIS; 613 #endif 614 615 /* Read MAC address, channels, etc from EEPROM. */ 616 error = iwn_read_eeprom(sc, macaddr); 617 if (error != 0) { 618 device_printf(dev, "could not read EEPROM, error %d\n", 619 error); 620 goto fail; 621 } 622 623 device_printf(sc->sc_dev, "MIMO %dT%dR, %.4s, address %6D\n", 624 sc->ntxchains, sc->nrxchains, sc->eeprom_domain, 625 macaddr, ":"); 626 627 #if 0 /* HT */ 628 /* Set supported HT rates. */ 629 ic->ic_sup_mcs[0] = 0xff; 630 if (sc->nrxchains > 1) 631 ic->ic_sup_mcs[1] = 0xff; 632 if (sc->nrxchains > 2) 633 ic->ic_sup_mcs[2] = 0xff; 634 #endif 635 636 if_initname(ifp, device_get_name(dev), device_get_unit(dev)); 637 ifp->if_softc = sc; 638 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 639 ifp->if_init = iwn_init; 640 ifp->if_ioctl = iwn_ioctl; 641 ifp->if_start = iwn_start; 642 IFQ_SET_MAXLEN(&ifp->if_snd, ifqmaxlen); 643 ifp->if_snd.ifq_drv_maxlen = ifqmaxlen; 644 IFQ_SET_READY(&ifp->if_snd); 645 646 ieee80211_ifattach(ic, macaddr); 647 ic->ic_vap_create = iwn_vap_create; 648 ic->ic_vap_delete = iwn_vap_delete; 649 ic->ic_raw_xmit = iwn_raw_xmit; 650 ic->ic_node_alloc = iwn_node_alloc; 651 ic->ic_newassoc = iwn_newassoc; 652 ic->ic_wme.wme_update = iwn_wme_update; 653 ic->ic_update_mcast = iwn_update_mcast; 654 ic->ic_scan_start = iwn_scan_start; 655 ic->ic_scan_end = iwn_scan_end; 656 ic->ic_set_channel = iwn_set_channel; 657 ic->ic_scan_curchan = iwn_scan_curchan; 658 ic->ic_scan_mindwell = iwn_scan_mindwell; 659 ic->ic_setregdomain = iwn_setregdomain; 660 #if 0 /* HT */ 661 ic->ic_ampdu_rx_start = iwn_ampdu_rx_start; 662 ic->ic_ampdu_rx_stop = iwn_ampdu_rx_stop; 663 ic->ic_ampdu_tx_start = iwn_ampdu_tx_start; 664 ic->ic_ampdu_tx_stop = iwn_ampdu_tx_stop; 665 #endif 666 667 iwn_radiotap_attach(sc); 668 iwn_sysctlattach(sc); 669 670 /* 671 * Hook our interrupt after all initialization is complete. 672 */ 673 error = bus_setup_intr(dev, sc->irq, INTR_TYPE_NET | INTR_MPSAFE, 674 NULL, iwn_intr, sc, &sc->sc_ih); 675 if (error != 0) { 676 device_printf(dev, "could not set up interrupt, error %d\n", 677 error); 678 goto fail; 679 } 680 681 ieee80211_announce(ic); 682 return 0; 683 fail: 684 iwn_cleanup(dev); 685 return error; 686 } 687 688 static const struct iwn_hal * 689 iwn_hal_attach(struct iwn_softc *sc) 690 { 691 sc->hw_type = (IWN_READ(sc, IWN_HW_REV) >> 4) & 0xf; 692 693 switch (sc->hw_type) { 694 case IWN_HW_REV_TYPE_4965: 695 sc->sc_hal = &iwn4965_hal; 696 sc->limits = &iwn4965_sensitivity_limits; 697 sc->fwname = "iwn4965fw"; 698 sc->txchainmask = IWN_ANT_AB; 699 sc->rxchainmask = IWN_ANT_ABC; 700 break; 701 case IWN_HW_REV_TYPE_5100: 702 sc->sc_hal = &iwn5000_hal; 703 sc->limits = &iwn5000_sensitivity_limits; 704 sc->fwname = "iwn5000fw"; 705 sc->txchainmask = IWN_ANT_B; 706 sc->rxchainmask = IWN_ANT_AB; 707 break; 708 case IWN_HW_REV_TYPE_5150: 709 sc->sc_hal = &iwn5000_hal; 710 sc->limits = &iwn5150_sensitivity_limits; 711 sc->fwname = "iwn5150fw"; 712 sc->txchainmask = IWN_ANT_A; 713 sc->rxchainmask = IWN_ANT_AB; 714 break; 715 case IWN_HW_REV_TYPE_5300: 716 case IWN_HW_REV_TYPE_5350: 717 sc->sc_hal = &iwn5000_hal; 718 sc->limits = &iwn5000_sensitivity_limits; 719 sc->fwname = "iwn5000fw"; 720 sc->txchainmask = IWN_ANT_ABC; 721 sc->rxchainmask = IWN_ANT_ABC; 722 break; 723 case IWN_HW_REV_TYPE_1000: 724 sc->sc_hal = &iwn5000_hal; 725 sc->limits = &iwn1000_sensitivity_limits; 726 sc->fwname = "iwn1000fw"; 727 sc->txchainmask = IWN_ANT_A; 728 sc->rxchainmask = IWN_ANT_AB; 729 break; 730 case IWN_HW_REV_TYPE_6000: 731 sc->sc_hal = &iwn5000_hal; 732 sc->limits = &iwn6000_sensitivity_limits; 733 sc->fwname = "iwn6000fw"; 734 switch (pci_get_device(sc->sc_dev)) { 735 case 0x422C: 736 case 0x4239: 737 sc->sc_flags |= IWN_FLAG_INTERNAL_PA; 738 sc->txchainmask = IWN_ANT_BC; 739 sc->rxchainmask = IWN_ANT_BC; 740 break; 741 default: 742 sc->txchainmask = IWN_ANT_ABC; 743 sc->rxchainmask = IWN_ANT_ABC; 744 break; 745 } 746 break; 747 case IWN_HW_REV_TYPE_6050: 748 sc->sc_hal = &iwn5000_hal; 749 sc->limits = &iwn6000_sensitivity_limits; 750 sc->fwname = "iwn6050fw"; 751 sc->txchainmask = IWN_ANT_AB; 752 sc->rxchainmask = IWN_ANT_AB; 753 break; 754 case IWN_HW_REV_TYPE_6005: 755 sc->sc_hal = &iwn5000_hal; 756 sc->limits = &iwn6000_sensitivity_limits; 757 sc->fwname = "iwn6005fw"; 758 sc->txchainmask = IWN_ANT_AB; 759 sc->rxchainmask = IWN_ANT_AB; 760 break; 761 default: 762 device_printf(sc->sc_dev, "adapter type %d not supported\n", 763 sc->hw_type); 764 return NULL; 765 } 766 return sc->sc_hal; 767 } 768 769 /* 770 * Attach the interface to 802.11 radiotap. 771 */ 772 static void 773 iwn_radiotap_attach(struct iwn_softc *sc) 774 { 775 struct ifnet *ifp = sc->sc_ifp; 776 struct ieee80211com *ic = ifp->if_l2com; 777 778 ieee80211_radiotap_attach(ic, 779 &sc->sc_txtap.wt_ihdr, sizeof(sc->sc_txtap), 780 IWN_TX_RADIOTAP_PRESENT, 781 &sc->sc_rxtap.wr_ihdr, sizeof(sc->sc_rxtap), 782 IWN_RX_RADIOTAP_PRESENT); 783 } 784 785 static struct ieee80211vap * 786 iwn_vap_create(struct ieee80211com *ic, 787 const char name[IFNAMSIZ], int unit, int opmode, int flags, 788 const uint8_t bssid[IEEE80211_ADDR_LEN], 789 const uint8_t mac[IEEE80211_ADDR_LEN]) 790 { 791 struct iwn_vap *ivp; 792 struct ieee80211vap *vap; 793 794 if (!TAILQ_EMPTY(&ic->ic_vaps)) /* only one at a time */ 795 return NULL; 796 ivp = (struct iwn_vap *) malloc(sizeof(struct iwn_vap), 797 M_80211_VAP, M_NOWAIT | M_ZERO); 798 if (ivp == NULL) 799 return NULL; 800 vap = &ivp->iv_vap; 801 ieee80211_vap_setup(ic, vap, name, unit, opmode, flags, bssid, mac); 802 vap->iv_bmissthreshold = 10; /* override default */ 803 /* Override with driver methods. */ 804 ivp->iv_newstate = vap->iv_newstate; 805 vap->iv_newstate = iwn_newstate; 806 807 ieee80211_ratectl_init(vap); 808 /* Complete setup. */ 809 ieee80211_vap_attach(vap, iwn_media_change, ieee80211_media_status); 810 ic->ic_opmode = opmode; 811 return vap; 812 } 813 814 static void 815 iwn_vap_delete(struct ieee80211vap *vap) 816 { 817 struct iwn_vap *ivp = IWN_VAP(vap); 818 819 ieee80211_ratectl_deinit(vap); 820 ieee80211_vap_detach(vap); 821 free(ivp, M_80211_VAP); 822 } 823 824 static int 825 iwn_cleanup(device_t dev) 826 { 827 struct iwn_softc *sc = device_get_softc(dev); 828 struct ifnet *ifp = sc->sc_ifp; 829 struct ieee80211com *ic; 830 int i; 831 832 if (ifp != NULL) { 833 ic = ifp->if_l2com; 834 835 ieee80211_draintask(ic, &sc->sc_reinit_task); 836 ieee80211_draintask(ic, &sc->sc_radioon_task); 837 ieee80211_draintask(ic, &sc->sc_radiooff_task); 838 839 iwn_stop(sc); 840 callout_drain(&sc->sc_timer_to); 841 ieee80211_ifdetach(ic); 842 } 843 844 /* Free DMA resources. */ 845 iwn_free_rx_ring(sc, &sc->rxq); 846 if (sc->sc_hal != NULL) 847 for (i = 0; i < sc->sc_hal->ntxqs; i++) 848 iwn_free_tx_ring(sc, &sc->txq[i]); 849 iwn_free_sched(sc); 850 iwn_free_kw(sc); 851 if (sc->ict != NULL) 852 iwn_free_ict(sc); 853 iwn_free_fwmem(sc); 854 855 if (sc->irq != NULL) { 856 bus_teardown_intr(dev, sc->irq, sc->sc_ih); 857 bus_release_resource(dev, SYS_RES_IRQ, sc->irq_rid, sc->irq); 858 if (sc->irq_rid == 1) 859 pci_release_msi(dev); 860 } 861 862 if (sc->mem != NULL) 863 bus_release_resource(dev, SYS_RES_MEMORY, sc->mem_rid, sc->mem); 864 865 if (ifp != NULL) 866 if_free(ifp); 867 868 IWN_LOCK_DESTROY(sc); 869 return 0; 870 } 871 872 static int 873 iwn_detach(device_t dev) 874 { 875 iwn_cleanup(dev); 876 return 0; 877 } 878 879 static int 880 iwn_nic_lock(struct iwn_softc *sc) 881 { 882 int ntries; 883 884 /* Request exclusive access to NIC. */ 885 IWN_SETBITS(sc, IWN_GP_CNTRL, IWN_GP_CNTRL_MAC_ACCESS_REQ); 886 887 /* Spin until we actually get the lock. */ 888 for (ntries = 0; ntries < 1000; ntries++) { 889 if ((IWN_READ(sc, IWN_GP_CNTRL) & 890 (IWN_GP_CNTRL_MAC_ACCESS_ENA | IWN_GP_CNTRL_SLEEP)) == 891 IWN_GP_CNTRL_MAC_ACCESS_ENA) 892 return 0; 893 DELAY(10); 894 } 895 return ETIMEDOUT; 896 } 897 898 static __inline void 899 iwn_nic_unlock(struct iwn_softc *sc) 900 { 901 IWN_CLRBITS(sc, IWN_GP_CNTRL, IWN_GP_CNTRL_MAC_ACCESS_REQ); 902 } 903 904 static __inline uint32_t 905 iwn_prph_read(struct iwn_softc *sc, uint32_t addr) 906 { 907 IWN_WRITE(sc, IWN_PRPH_RADDR, IWN_PRPH_DWORD | addr); 908 IWN_BARRIER_READ_WRITE(sc); 909 return IWN_READ(sc, IWN_PRPH_RDATA); 910 } 911 912 static __inline void 913 iwn_prph_write(struct iwn_softc *sc, uint32_t addr, uint32_t data) 914 { 915 IWN_WRITE(sc, IWN_PRPH_WADDR, IWN_PRPH_DWORD | addr); 916 IWN_BARRIER_WRITE(sc); 917 IWN_WRITE(sc, IWN_PRPH_WDATA, data); 918 } 919 920 static __inline void 921 iwn_prph_setbits(struct iwn_softc *sc, uint32_t addr, uint32_t mask) 922 { 923 iwn_prph_write(sc, addr, iwn_prph_read(sc, addr) | mask); 924 } 925 926 static __inline void 927 iwn_prph_clrbits(struct iwn_softc *sc, uint32_t addr, uint32_t mask) 928 { 929 iwn_prph_write(sc, addr, iwn_prph_read(sc, addr) & ~mask); 930 } 931 932 static __inline void 933 iwn_prph_write_region_4(struct iwn_softc *sc, uint32_t addr, 934 const uint32_t *data, int count) 935 { 936 for (; count > 0; count--, data++, addr += 4) 937 iwn_prph_write(sc, addr, *data); 938 } 939 940 static __inline uint32_t 941 iwn_mem_read(struct iwn_softc *sc, uint32_t addr) 942 { 943 IWN_WRITE(sc, IWN_MEM_RADDR, addr); 944 IWN_BARRIER_READ_WRITE(sc); 945 return IWN_READ(sc, IWN_MEM_RDATA); 946 } 947 948 static __inline void 949 iwn_mem_write(struct iwn_softc *sc, uint32_t addr, uint32_t data) 950 { 951 IWN_WRITE(sc, IWN_MEM_WADDR, addr); 952 IWN_BARRIER_WRITE(sc); 953 IWN_WRITE(sc, IWN_MEM_WDATA, data); 954 } 955 956 static __inline void 957 iwn_mem_write_2(struct iwn_softc *sc, uint32_t addr, uint16_t data) 958 { 959 uint32_t tmp; 960 961 tmp = iwn_mem_read(sc, addr & ~3); 962 if (addr & 3) 963 tmp = (tmp & 0x0000ffff) | data << 16; 964 else 965 tmp = (tmp & 0xffff0000) | data; 966 iwn_mem_write(sc, addr & ~3, tmp); 967 } 968 969 static __inline void 970 iwn_mem_read_region_4(struct iwn_softc *sc, uint32_t addr, uint32_t *data, 971 int count) 972 { 973 for (; count > 0; count--, addr += 4) 974 *data++ = iwn_mem_read(sc, addr); 975 } 976 977 static __inline void 978 iwn_mem_set_region_4(struct iwn_softc *sc, uint32_t addr, uint32_t val, 979 int count) 980 { 981 for (; count > 0; count--, addr += 4) 982 iwn_mem_write(sc, addr, val); 983 } 984 985 static int 986 iwn_eeprom_lock(struct iwn_softc *sc) 987 { 988 int i, ntries; 989 990 for (i = 0; i < 100; i++) { 991 /* Request exclusive access to EEPROM. */ 992 IWN_SETBITS(sc, IWN_HW_IF_CONFIG, 993 IWN_HW_IF_CONFIG_EEPROM_LOCKED); 994 995 /* Spin until we actually get the lock. */ 996 for (ntries = 0; ntries < 100; ntries++) { 997 if (IWN_READ(sc, IWN_HW_IF_CONFIG) & 998 IWN_HW_IF_CONFIG_EEPROM_LOCKED) 999 return 0; 1000 DELAY(10); 1001 } 1002 } 1003 return ETIMEDOUT; 1004 } 1005 1006 static __inline void 1007 iwn_eeprom_unlock(struct iwn_softc *sc) 1008 { 1009 IWN_CLRBITS(sc, IWN_HW_IF_CONFIG, IWN_HW_IF_CONFIG_EEPROM_LOCKED); 1010 } 1011 1012 /* 1013 * Initialize access by host to One Time Programmable ROM. 1014 * NB: This kind of ROM can be found on 1000 or 6000 Series only. 1015 */ 1016 static int 1017 iwn_init_otprom(struct iwn_softc *sc) 1018 { 1019 uint16_t prev, base, next; 1020 int count, error; 1021 1022 /* Wait for clock stabilization before accessing prph. */ 1023 error = iwn_clock_wait(sc); 1024 if (error != 0) 1025 return error; 1026 1027 error = iwn_nic_lock(sc); 1028 if (error != 0) 1029 return error; 1030 iwn_prph_setbits(sc, IWN_APMG_PS, IWN_APMG_PS_RESET_REQ); 1031 DELAY(5); 1032 iwn_prph_clrbits(sc, IWN_APMG_PS, IWN_APMG_PS_RESET_REQ); 1033 iwn_nic_unlock(sc); 1034 1035 /* Set auto clock gate disable bit for HW with OTP shadow RAM. */ 1036 if (sc->hw_type != IWN_HW_REV_TYPE_1000) { 1037 IWN_SETBITS(sc, IWN_DBG_LINK_PWR_MGMT, 1038 IWN_RESET_LINK_PWR_MGMT_DIS); 1039 } 1040 IWN_CLRBITS(sc, IWN_EEPROM_GP, IWN_EEPROM_GP_IF_OWNER); 1041 /* Clear ECC status. */ 1042 IWN_SETBITS(sc, IWN_OTP_GP, 1043 IWN_OTP_GP_ECC_CORR_STTS | IWN_OTP_GP_ECC_UNCORR_STTS); 1044 1045 /* 1046 * Find the block before last block (contains the EEPROM image) 1047 * for HW without OTP shadow RAM. 1048 */ 1049 if (sc->hw_type == IWN_HW_REV_TYPE_1000) { 1050 /* Switch to absolute addressing mode. */ 1051 IWN_CLRBITS(sc, IWN_OTP_GP, IWN_OTP_GP_RELATIVE_ACCESS); 1052 base = prev = 0; 1053 for (count = 0; count < IWN1000_OTP_NBLOCKS; count++) { 1054 error = iwn_read_prom_data(sc, base, &next, 2); 1055 if (error != 0) 1056 return error; 1057 if (next == 0) /* End of linked-list. */ 1058 break; 1059 prev = base; 1060 base = le16toh(next); 1061 } 1062 if (count == 0 || count == IWN1000_OTP_NBLOCKS) 1063 return EIO; 1064 /* Skip "next" word. */ 1065 sc->prom_base = prev + 1; 1066 } 1067 return 0; 1068 } 1069 1070 static int 1071 iwn_read_prom_data(struct iwn_softc *sc, uint32_t addr, void *data, int count) 1072 { 1073 uint32_t val, tmp; 1074 int ntries; 1075 uint8_t *out = data; 1076 1077 addr += sc->prom_base; 1078 for (; count > 0; count -= 2, addr++) { 1079 IWN_WRITE(sc, IWN_EEPROM, addr << 2); 1080 for (ntries = 0; ntries < 10; ntries++) { 1081 val = IWN_READ(sc, IWN_EEPROM); 1082 if (val & IWN_EEPROM_READ_VALID) 1083 break; 1084 DELAY(5); 1085 } 1086 if (ntries == 10) { 1087 device_printf(sc->sc_dev, 1088 "timeout reading ROM at 0x%x\n", addr); 1089 return ETIMEDOUT; 1090 } 1091 if (sc->sc_flags & IWN_FLAG_HAS_OTPROM) { 1092 /* OTPROM, check for ECC errors. */ 1093 tmp = IWN_READ(sc, IWN_OTP_GP); 1094 if (tmp & IWN_OTP_GP_ECC_UNCORR_STTS) { 1095 device_printf(sc->sc_dev, 1096 "OTPROM ECC error at 0x%x\n", addr); 1097 return EIO; 1098 } 1099 if (tmp & IWN_OTP_GP_ECC_CORR_STTS) { 1100 /* Correctable ECC error, clear bit. */ 1101 IWN_SETBITS(sc, IWN_OTP_GP, 1102 IWN_OTP_GP_ECC_CORR_STTS); 1103 } 1104 } 1105 *out++ = val >> 16; 1106 if (count > 1) 1107 *out++ = val >> 24; 1108 } 1109 return 0; 1110 } 1111 1112 static void 1113 iwn_dma_map_addr(void *arg, bus_dma_segment_t *segs, int nsegs, int error) 1114 { 1115 if (error != 0) 1116 return; 1117 KASSERT(nsegs == 1, ("too many DMA segments, %d should be 1", nsegs)); 1118 *(bus_addr_t *)arg = segs[0].ds_addr; 1119 } 1120 1121 static int 1122 iwn_dma_contig_alloc(struct iwn_softc *sc, struct iwn_dma_info *dma, 1123 void **kvap, bus_size_t size, bus_size_t alignment, int flags) 1124 { 1125 int error; 1126 1127 dma->size = size; 1128 dma->tag = NULL; 1129 1130 error = bus_dma_tag_create(bus_get_dma_tag(sc->sc_dev), alignment, 1131 0, BUS_SPACE_MAXADDR_32BIT, BUS_SPACE_MAXADDR, NULL, NULL, size, 1132 1, size, flags, NULL, NULL, &dma->tag); 1133 if (error != 0) { 1134 device_printf(sc->sc_dev, 1135 "%s: bus_dma_tag_create failed, error %d\n", 1136 __func__, error); 1137 goto fail; 1138 } 1139 error = bus_dmamem_alloc(dma->tag, (void **)&dma->vaddr, 1140 flags | BUS_DMA_ZERO, &dma->map); 1141 if (error != 0) { 1142 device_printf(sc->sc_dev, 1143 "%s: bus_dmamem_alloc failed, error %d\n", __func__, error); 1144 goto fail; 1145 } 1146 error = bus_dmamap_load(dma->tag, dma->map, dma->vaddr, 1147 size, iwn_dma_map_addr, &dma->paddr, flags); 1148 if (error != 0) { 1149 device_printf(sc->sc_dev, 1150 "%s: bus_dmamap_load failed, error %d\n", __func__, error); 1151 goto fail; 1152 } 1153 1154 if (kvap != NULL) 1155 *kvap = dma->vaddr; 1156 return 0; 1157 fail: 1158 iwn_dma_contig_free(dma); 1159 return error; 1160 } 1161 1162 static void 1163 iwn_dma_contig_free(struct iwn_dma_info *dma) 1164 { 1165 if (dma->tag != NULL) { 1166 if (dma->map != NULL) { 1167 if (dma->paddr == 0) { 1168 bus_dmamap_sync(dma->tag, dma->map, 1169 BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE); 1170 bus_dmamap_unload(dma->tag, dma->map); 1171 } 1172 bus_dmamem_free(dma->tag, &dma->vaddr, dma->map); 1173 } 1174 bus_dma_tag_destroy(dma->tag); 1175 } 1176 } 1177 1178 static int 1179 iwn_alloc_sched(struct iwn_softc *sc) 1180 { 1181 /* TX scheduler rings must be aligned on a 1KB boundary. */ 1182 return iwn_dma_contig_alloc(sc, &sc->sched_dma, 1183 (void **)&sc->sched, sc->sc_hal->schedsz, 1024, BUS_DMA_NOWAIT); 1184 } 1185 1186 static void 1187 iwn_free_sched(struct iwn_softc *sc) 1188 { 1189 iwn_dma_contig_free(&sc->sched_dma); 1190 } 1191 1192 static int 1193 iwn_alloc_kw(struct iwn_softc *sc) 1194 { 1195 /* "Keep Warm" page must be aligned on a 4KB boundary. */ 1196 return iwn_dma_contig_alloc(sc, &sc->kw_dma, NULL, 4096, 4096, 1197 BUS_DMA_NOWAIT); 1198 } 1199 1200 static void 1201 iwn_free_kw(struct iwn_softc *sc) 1202 { 1203 iwn_dma_contig_free(&sc->kw_dma); 1204 } 1205 1206 static int 1207 iwn_alloc_ict(struct iwn_softc *sc) 1208 { 1209 /* ICT table must be aligned on a 4KB boundary. */ 1210 return iwn_dma_contig_alloc(sc, &sc->ict_dma, 1211 (void **)&sc->ict, IWN_ICT_SIZE, 4096, BUS_DMA_NOWAIT); 1212 } 1213 1214 static void 1215 iwn_free_ict(struct iwn_softc *sc) 1216 { 1217 iwn_dma_contig_free(&sc->ict_dma); 1218 } 1219 1220 static int 1221 iwn_alloc_fwmem(struct iwn_softc *sc) 1222 { 1223 /* Must be aligned on a 16-byte boundary. */ 1224 return iwn_dma_contig_alloc(sc, &sc->fw_dma, NULL, 1225 sc->sc_hal->fwsz, 16, BUS_DMA_NOWAIT); 1226 } 1227 1228 static void 1229 iwn_free_fwmem(struct iwn_softc *sc) 1230 { 1231 iwn_dma_contig_free(&sc->fw_dma); 1232 } 1233 1234 static int 1235 iwn_alloc_rx_ring(struct iwn_softc *sc, struct iwn_rx_ring *ring) 1236 { 1237 bus_size_t size; 1238 int i, error; 1239 1240 ring->cur = 0; 1241 1242 /* Allocate RX descriptors (256-byte aligned). */ 1243 size = IWN_RX_RING_COUNT * sizeof (uint32_t); 1244 error = iwn_dma_contig_alloc(sc, &ring->desc_dma, 1245 (void **)&ring->desc, size, 256, BUS_DMA_NOWAIT); 1246 if (error != 0) { 1247 device_printf(sc->sc_dev, 1248 "%s: could not allocate Rx ring DMA memory, error %d\n", 1249 __func__, error); 1250 goto fail; 1251 } 1252 1253 error = bus_dma_tag_create(bus_get_dma_tag(sc->sc_dev), 1, 0, 1254 BUS_SPACE_MAXADDR_32BIT, 1255 BUS_SPACE_MAXADDR, NULL, NULL, MJUMPAGESIZE, 1, 1256 MJUMPAGESIZE, BUS_DMA_NOWAIT, NULL, NULL, &ring->data_dmat); 1257 if (error != 0) { 1258 device_printf(sc->sc_dev, 1259 "%s: bus_dma_tag_create_failed, error %d\n", 1260 __func__, error); 1261 goto fail; 1262 } 1263 1264 /* Allocate RX status area (16-byte aligned). */ 1265 error = iwn_dma_contig_alloc(sc, &ring->stat_dma, 1266 (void **)&ring->stat, sizeof (struct iwn_rx_status), 1267 16, BUS_DMA_NOWAIT); 1268 if (error != 0) { 1269 device_printf(sc->sc_dev, 1270 "%s: could not allocate Rx status DMA memory, error %d\n", 1271 __func__, error); 1272 goto fail; 1273 } 1274 1275 /* 1276 * Allocate and map RX buffers. 1277 */ 1278 for (i = 0; i < IWN_RX_RING_COUNT; i++) { 1279 struct iwn_rx_data *data = &ring->data[i]; 1280 bus_addr_t paddr; 1281 1282 error = bus_dmamap_create(ring->data_dmat, 0, &data->map); 1283 if (error != 0) { 1284 device_printf(sc->sc_dev, 1285 "%s: bus_dmamap_create failed, error %d\n", 1286 __func__, error); 1287 goto fail; 1288 } 1289 1290 data->m = m_getjcl(M_DONTWAIT, MT_DATA, M_PKTHDR, MJUMPAGESIZE); 1291 if (data->m == NULL) { 1292 device_printf(sc->sc_dev, 1293 "%s: could not allocate rx mbuf\n", __func__); 1294 error = ENOMEM; 1295 goto fail; 1296 } 1297 1298 /* Map page. */ 1299 error = bus_dmamap_load(ring->data_dmat, data->map, 1300 mtod(data->m, caddr_t), MJUMPAGESIZE, 1301 iwn_dma_map_addr, &paddr, BUS_DMA_NOWAIT); 1302 if (error != 0 && error != EFBIG) { 1303 device_printf(sc->sc_dev, 1304 "%s: bus_dmamap_load failed, error %d\n", 1305 __func__, error); 1306 m_freem(data->m); 1307 error = ENOMEM; /* XXX unique code */ 1308 goto fail; 1309 } 1310 bus_dmamap_sync(ring->data_dmat, data->map, 1311 BUS_DMASYNC_PREWRITE); 1312 1313 /* Set physical address of RX buffer (256-byte aligned). */ 1314 ring->desc[i] = htole32(paddr >> 8); 1315 } 1316 bus_dmamap_sync(ring->desc_dma.tag, ring->desc_dma.map, 1317 BUS_DMASYNC_PREWRITE); 1318 return 0; 1319 fail: 1320 iwn_free_rx_ring(sc, ring); 1321 return error; 1322 } 1323 1324 static void 1325 iwn_reset_rx_ring(struct iwn_softc *sc, struct iwn_rx_ring *ring) 1326 { 1327 int ntries; 1328 1329 if (iwn_nic_lock(sc) == 0) { 1330 IWN_WRITE(sc, IWN_FH_RX_CONFIG, 0); 1331 for (ntries = 0; ntries < 1000; ntries++) { 1332 if (IWN_READ(sc, IWN_FH_RX_STATUS) & 1333 IWN_FH_RX_STATUS_IDLE) 1334 break; 1335 DELAY(10); 1336 } 1337 iwn_nic_unlock(sc); 1338 #ifdef IWN_DEBUG 1339 if (ntries == 1000) 1340 DPRINTF(sc, IWN_DEBUG_ANY, "%s\n", 1341 "timeout resetting Rx ring"); 1342 #endif 1343 } 1344 ring->cur = 0; 1345 sc->last_rx_valid = 0; 1346 } 1347 1348 static void 1349 iwn_free_rx_ring(struct iwn_softc *sc, struct iwn_rx_ring *ring) 1350 { 1351 int i; 1352 1353 iwn_dma_contig_free(&ring->desc_dma); 1354 iwn_dma_contig_free(&ring->stat_dma); 1355 1356 for (i = 0; i < IWN_RX_RING_COUNT; i++) { 1357 struct iwn_rx_data *data = &ring->data[i]; 1358 1359 if (data->m != NULL) { 1360 bus_dmamap_sync(ring->data_dmat, data->map, 1361 BUS_DMASYNC_POSTREAD); 1362 bus_dmamap_unload(ring->data_dmat, data->map); 1363 m_freem(data->m); 1364 } 1365 if (data->map != NULL) 1366 bus_dmamap_destroy(ring->data_dmat, data->map); 1367 } 1368 } 1369 1370 static int 1371 iwn_alloc_tx_ring(struct iwn_softc *sc, struct iwn_tx_ring *ring, int qid) 1372 { 1373 bus_size_t size; 1374 bus_addr_t paddr; 1375 int i, error; 1376 1377 ring->qid = qid; 1378 ring->queued = 0; 1379 ring->cur = 0; 1380 1381 /* Allocate TX descriptors (256-byte aligned.) */ 1382 size = IWN_TX_RING_COUNT * sizeof(struct iwn_tx_desc); 1383 error = iwn_dma_contig_alloc(sc, &ring->desc_dma, 1384 (void **)&ring->desc, size, 256, BUS_DMA_NOWAIT); 1385 if (error != 0) { 1386 device_printf(sc->sc_dev, 1387 "%s: could not allocate TX ring DMA memory, error %d\n", 1388 __func__, error); 1389 goto fail; 1390 } 1391 1392 /* 1393 * We only use rings 0 through 4 (4 EDCA + cmd) so there is no need 1394 * to allocate commands space for other rings. 1395 */ 1396 if (qid > 4) 1397 return 0; 1398 1399 size = IWN_TX_RING_COUNT * sizeof(struct iwn_tx_cmd); 1400 error = iwn_dma_contig_alloc(sc, &ring->cmd_dma, 1401 (void **)&ring->cmd, size, 4, BUS_DMA_NOWAIT); 1402 if (error != 0) { 1403 device_printf(sc->sc_dev, 1404 "%s: could not allocate TX cmd DMA memory, error %d\n", 1405 __func__, error); 1406 goto fail; 1407 } 1408 1409 error = bus_dma_tag_create(bus_get_dma_tag(sc->sc_dev), 1, 0, 1410 BUS_SPACE_MAXADDR_32BIT, 1411 BUS_SPACE_MAXADDR, NULL, NULL, MCLBYTES, IWN_MAX_SCATTER - 1, 1412 MCLBYTES, BUS_DMA_NOWAIT, NULL, NULL, &ring->data_dmat); 1413 if (error != 0) { 1414 device_printf(sc->sc_dev, 1415 "%s: bus_dma_tag_create_failed, error %d\n", 1416 __func__, error); 1417 goto fail; 1418 } 1419 1420 paddr = ring->cmd_dma.paddr; 1421 for (i = 0; i < IWN_TX_RING_COUNT; i++) { 1422 struct iwn_tx_data *data = &ring->data[i]; 1423 1424 data->cmd_paddr = paddr; 1425 data->scratch_paddr = paddr + 12; 1426 paddr += sizeof (struct iwn_tx_cmd); 1427 1428 error = bus_dmamap_create(ring->data_dmat, 0, &data->map); 1429 if (error != 0) { 1430 device_printf(sc->sc_dev, 1431 "%s: bus_dmamap_create failed, error %d\n", 1432 __func__, error); 1433 goto fail; 1434 } 1435 bus_dmamap_sync(ring->data_dmat, data->map, 1436 BUS_DMASYNC_PREWRITE); 1437 } 1438 return 0; 1439 fail: 1440 iwn_free_tx_ring(sc, ring); 1441 return error; 1442 } 1443 1444 static void 1445 iwn_reset_tx_ring(struct iwn_softc *sc, struct iwn_tx_ring *ring) 1446 { 1447 int i; 1448 1449 for (i = 0; i < IWN_TX_RING_COUNT; i++) { 1450 struct iwn_tx_data *data = &ring->data[i]; 1451 1452 if (data->m != NULL) { 1453 bus_dmamap_unload(ring->data_dmat, data->map); 1454 m_freem(data->m); 1455 data->m = NULL; 1456 } 1457 } 1458 /* Clear TX descriptors. */ 1459 memset(ring->desc, 0, ring->desc_dma.size); 1460 bus_dmamap_sync(ring->desc_dma.tag, ring->desc_dma.map, 1461 BUS_DMASYNC_PREWRITE); 1462 sc->qfullmsk &= ~(1 << ring->qid); 1463 ring->queued = 0; 1464 ring->cur = 0; 1465 } 1466 1467 static void 1468 iwn_free_tx_ring(struct iwn_softc *sc, struct iwn_tx_ring *ring) 1469 { 1470 int i; 1471 1472 iwn_dma_contig_free(&ring->desc_dma); 1473 iwn_dma_contig_free(&ring->cmd_dma); 1474 1475 for (i = 0; i < IWN_TX_RING_COUNT; i++) { 1476 struct iwn_tx_data *data = &ring->data[i]; 1477 1478 if (data->m != NULL) { 1479 bus_dmamap_sync(ring->data_dmat, data->map, 1480 BUS_DMASYNC_POSTWRITE); 1481 bus_dmamap_unload(ring->data_dmat, data->map); 1482 m_freem(data->m); 1483 } 1484 if (data->map != NULL) 1485 bus_dmamap_destroy(ring->data_dmat, data->map); 1486 } 1487 } 1488 1489 static void 1490 iwn5000_ict_reset(struct iwn_softc *sc) 1491 { 1492 /* Disable interrupts. */ 1493 IWN_WRITE(sc, IWN_INT_MASK, 0); 1494 1495 /* Reset ICT table. */ 1496 memset(sc->ict, 0, IWN_ICT_SIZE); 1497 sc->ict_cur = 0; 1498 1499 /* Set physical address of ICT table (4KB aligned.) */ 1500 DPRINTF(sc, IWN_DEBUG_RESET, "%s: enabling ICT\n", __func__); 1501 IWN_WRITE(sc, IWN_DRAM_INT_TBL, IWN_DRAM_INT_TBL_ENABLE | 1502 IWN_DRAM_INT_TBL_WRAP_CHECK | sc->ict_dma.paddr >> 12); 1503 1504 /* Enable periodic RX interrupt. */ 1505 sc->int_mask |= IWN_INT_RX_PERIODIC; 1506 /* Switch to ICT interrupt mode in driver. */ 1507 sc->sc_flags |= IWN_FLAG_USE_ICT; 1508 1509 /* Re-enable interrupts. */ 1510 IWN_WRITE(sc, IWN_INT, 0xffffffff); 1511 IWN_WRITE(sc, IWN_INT_MASK, sc->int_mask); 1512 } 1513 1514 static int 1515 iwn_read_eeprom(struct iwn_softc *sc, uint8_t macaddr[IEEE80211_ADDR_LEN]) 1516 { 1517 const struct iwn_hal *hal = sc->sc_hal; 1518 int error; 1519 uint16_t val; 1520 1521 /* Check whether adapter has an EEPROM or an OTPROM. */ 1522 if (sc->hw_type >= IWN_HW_REV_TYPE_1000 && 1523 (IWN_READ(sc, IWN_OTP_GP) & IWN_OTP_GP_DEV_SEL_OTP)) 1524 sc->sc_flags |= IWN_FLAG_HAS_OTPROM; 1525 DPRINTF(sc, IWN_DEBUG_RESET, "%s found\n", 1526 (sc->sc_flags & IWN_FLAG_HAS_OTPROM) ? "OTPROM" : "EEPROM"); 1527 1528 /* Adapter has to be powered on for EEPROM access to work. */ 1529 error = iwn_apm_init(sc); 1530 if (error != 0) { 1531 device_printf(sc->sc_dev, 1532 "%s: could not power ON adapter, error %d\n", 1533 __func__, error); 1534 return error; 1535 } 1536 1537 if ((IWN_READ(sc, IWN_EEPROM_GP) & 0x7) == 0) { 1538 device_printf(sc->sc_dev, "%s: bad ROM signature\n", __func__); 1539 return EIO; 1540 } 1541 error = iwn_eeprom_lock(sc); 1542 if (error != 0) { 1543 device_printf(sc->sc_dev, 1544 "%s: could not lock ROM, error %d\n", 1545 __func__, error); 1546 return error; 1547 } 1548 1549 if (sc->sc_flags & IWN_FLAG_HAS_OTPROM) { 1550 error = iwn_init_otprom(sc); 1551 if (error != 0) { 1552 device_printf(sc->sc_dev, 1553 "%s: could not initialize OTPROM, error %d\n", 1554 __func__, error); 1555 return error; 1556 } 1557 } 1558 1559 iwn_read_prom_data(sc, IWN_EEPROM_RFCFG, &val, 2); 1560 sc->rfcfg = le16toh(val); 1561 DPRINTF(sc, IWN_DEBUG_RESET, "radio config=0x%04x\n", sc->rfcfg); 1562 1563 /* Read MAC address. */ 1564 iwn_read_prom_data(sc, IWN_EEPROM_MAC, macaddr, 6); 1565 1566 /* Read adapter-specific information from EEPROM. */ 1567 hal->read_eeprom(sc); 1568 1569 iwn_apm_stop(sc); /* Power OFF adapter. */ 1570 1571 iwn_eeprom_unlock(sc); 1572 return 0; 1573 } 1574 1575 static void 1576 iwn4965_read_eeprom(struct iwn_softc *sc) 1577 { 1578 uint32_t addr; 1579 int i; 1580 uint16_t val; 1581 1582 /* Read regulatory domain (4 ASCII characters.) */ 1583 iwn_read_prom_data(sc, IWN4965_EEPROM_DOMAIN, sc->eeprom_domain, 4); 1584 1585 /* Read the list of authorized channels (20MHz ones only.) */ 1586 for (i = 0; i < 5; i++) { 1587 addr = iwn4965_regulatory_bands[i]; 1588 iwn_read_eeprom_channels(sc, i, addr); 1589 } 1590 1591 /* Read maximum allowed TX power for 2GHz and 5GHz bands. */ 1592 iwn_read_prom_data(sc, IWN4965_EEPROM_MAXPOW, &val, 2); 1593 sc->maxpwr2GHz = val & 0xff; 1594 sc->maxpwr5GHz = val >> 8; 1595 /* Check that EEPROM values are within valid range. */ 1596 if (sc->maxpwr5GHz < 20 || sc->maxpwr5GHz > 50) 1597 sc->maxpwr5GHz = 38; 1598 if (sc->maxpwr2GHz < 20 || sc->maxpwr2GHz > 50) 1599 sc->maxpwr2GHz = 38; 1600 DPRINTF(sc, IWN_DEBUG_RESET, "maxpwr 2GHz=%d 5GHz=%d\n", 1601 sc->maxpwr2GHz, sc->maxpwr5GHz); 1602 1603 /* Read samples for each TX power group. */ 1604 iwn_read_prom_data(sc, IWN4965_EEPROM_BANDS, sc->bands, 1605 sizeof sc->bands); 1606 1607 /* Read voltage at which samples were taken. */ 1608 iwn_read_prom_data(sc, IWN4965_EEPROM_VOLTAGE, &val, 2); 1609 sc->eeprom_voltage = (int16_t)le16toh(val); 1610 DPRINTF(sc, IWN_DEBUG_RESET, "voltage=%d (in 0.3V)\n", 1611 sc->eeprom_voltage); 1612 1613 #ifdef IWN_DEBUG 1614 /* Print samples. */ 1615 if (sc->sc_debug & IWN_DEBUG_ANY) { 1616 for (i = 0; i < IWN_NBANDS; i++) 1617 iwn4965_print_power_group(sc, i); 1618 } 1619 #endif 1620 } 1621 1622 #ifdef IWN_DEBUG 1623 static void 1624 iwn4965_print_power_group(struct iwn_softc *sc, int i) 1625 { 1626 struct iwn4965_eeprom_band *band = &sc->bands[i]; 1627 struct iwn4965_eeprom_chan_samples *chans = band->chans; 1628 int j, c; 1629 1630 printf("===band %d===\n", i); 1631 printf("chan lo=%d, chan hi=%d\n", band->lo, band->hi); 1632 printf("chan1 num=%d\n", chans[0].num); 1633 for (c = 0; c < 2; c++) { 1634 for (j = 0; j < IWN_NSAMPLES; j++) { 1635 printf("chain %d, sample %d: temp=%d gain=%d " 1636 "power=%d pa_det=%d\n", c, j, 1637 chans[0].samples[c][j].temp, 1638 chans[0].samples[c][j].gain, 1639 chans[0].samples[c][j].power, 1640 chans[0].samples[c][j].pa_det); 1641 } 1642 } 1643 printf("chan2 num=%d\n", chans[1].num); 1644 for (c = 0; c < 2; c++) { 1645 for (j = 0; j < IWN_NSAMPLES; j++) { 1646 printf("chain %d, sample %d: temp=%d gain=%d " 1647 "power=%d pa_det=%d\n", c, j, 1648 chans[1].samples[c][j].temp, 1649 chans[1].samples[c][j].gain, 1650 chans[1].samples[c][j].power, 1651 chans[1].samples[c][j].pa_det); 1652 } 1653 } 1654 } 1655 #endif 1656 1657 static void 1658 iwn5000_read_eeprom(struct iwn_softc *sc) 1659 { 1660 struct iwn5000_eeprom_calib_hdr hdr; 1661 int32_t temp, volt; 1662 uint32_t addr, base; 1663 int i; 1664 uint16_t val; 1665 1666 /* Read regulatory domain (4 ASCII characters.) */ 1667 iwn_read_prom_data(sc, IWN5000_EEPROM_REG, &val, 2); 1668 base = le16toh(val); 1669 iwn_read_prom_data(sc, base + IWN5000_EEPROM_DOMAIN, 1670 sc->eeprom_domain, 4); 1671 1672 /* Read the list of authorized channels (20MHz ones only.) */ 1673 for (i = 0; i < 5; i++) { 1674 addr = base + iwn5000_regulatory_bands[i]; 1675 iwn_read_eeprom_channels(sc, i, addr); 1676 } 1677 1678 /* Read enhanced TX power information for 6000 Series. */ 1679 if (sc->hw_type >= IWN_HW_REV_TYPE_6000) 1680 iwn_read_eeprom_enhinfo(sc); 1681 1682 iwn_read_prom_data(sc, IWN5000_EEPROM_CAL, &val, 2); 1683 base = le16toh(val); 1684 iwn_read_prom_data(sc, base, &hdr, sizeof hdr); 1685 DPRINTF(sc, IWN_DEBUG_CALIBRATE, 1686 "%s: calib version=%u pa type=%u voltage=%u\n", 1687 __func__, hdr.version, hdr.pa_type, le16toh(hdr.volt)); 1688 sc->calib_ver = hdr.version; 1689 1690 if (sc->hw_type == IWN_HW_REV_TYPE_5150) { 1691 /* Compute temperature offset. */ 1692 iwn_read_prom_data(sc, base + IWN5000_EEPROM_TEMP, &val, 2); 1693 temp = le16toh(val); 1694 iwn_read_prom_data(sc, base + IWN5000_EEPROM_VOLT, &val, 2); 1695 volt = le16toh(val); 1696 sc->temp_off = temp - (volt / -5); 1697 DPRINTF(sc, IWN_DEBUG_CALIBRATE, "temp=%d volt=%d offset=%dK\n", 1698 temp, volt, sc->temp_off); 1699 } else { 1700 /* Read crystal calibration. */ 1701 iwn_read_prom_data(sc, base + IWN5000_EEPROM_CRYSTAL, 1702 &sc->eeprom_crystal, sizeof (uint32_t)); 1703 DPRINTF(sc, IWN_DEBUG_CALIBRATE, "crystal calibration 0x%08x\n", 1704 le32toh(sc->eeprom_crystal)); 1705 } 1706 } 1707 1708 /* 1709 * Translate EEPROM flags to net80211. 1710 */ 1711 static uint32_t 1712 iwn_eeprom_channel_flags(struct iwn_eeprom_chan *channel) 1713 { 1714 uint32_t nflags; 1715 1716 nflags = 0; 1717 if ((channel->flags & IWN_EEPROM_CHAN_ACTIVE) == 0) 1718 nflags |= IEEE80211_CHAN_PASSIVE; 1719 if ((channel->flags & IWN_EEPROM_CHAN_IBSS) == 0) 1720 nflags |= IEEE80211_CHAN_NOADHOC; 1721 if (channel->flags & IWN_EEPROM_CHAN_RADAR) { 1722 nflags |= IEEE80211_CHAN_DFS; 1723 /* XXX apparently IBSS may still be marked */ 1724 nflags |= IEEE80211_CHAN_NOADHOC; 1725 } 1726 1727 return nflags; 1728 } 1729 1730 static void 1731 iwn_read_eeprom_band(struct iwn_softc *sc, int n) 1732 { 1733 struct ifnet *ifp = sc->sc_ifp; 1734 struct ieee80211com *ic = ifp->if_l2com; 1735 struct iwn_eeprom_chan *channels = sc->eeprom_channels[n]; 1736 const struct iwn_chan_band *band = &iwn_bands[n]; 1737 struct ieee80211_channel *c; 1738 int i, chan, nflags; 1739 1740 for (i = 0; i < band->nchan; i++) { 1741 if (!(channels[i].flags & IWN_EEPROM_CHAN_VALID)) { 1742 DPRINTF(sc, IWN_DEBUG_RESET, 1743 "skip chan %d flags 0x%x maxpwr %d\n", 1744 band->chan[i], channels[i].flags, 1745 channels[i].maxpwr); 1746 continue; 1747 } 1748 chan = band->chan[i]; 1749 nflags = iwn_eeprom_channel_flags(&channels[i]); 1750 1751 DPRINTF(sc, IWN_DEBUG_RESET, 1752 "add chan %d flags 0x%x maxpwr %d\n", 1753 chan, channels[i].flags, channels[i].maxpwr); 1754 1755 c = &ic->ic_channels[ic->ic_nchans++]; 1756 c->ic_ieee = chan; 1757 c->ic_maxregpower = channels[i].maxpwr; 1758 c->ic_maxpower = 2*c->ic_maxregpower; 1759 1760 /* Save maximum allowed TX power for this channel. */ 1761 sc->maxpwr[chan] = channels[i].maxpwr; 1762 1763 if (n == 0) { /* 2GHz band */ 1764 c->ic_freq = ieee80211_ieee2mhz(chan, 1765 IEEE80211_CHAN_G); 1766 1767 /* G =>'s B is supported */ 1768 c->ic_flags = IEEE80211_CHAN_B | nflags; 1769 1770 c = &ic->ic_channels[ic->ic_nchans++]; 1771 c[0] = c[-1]; 1772 c->ic_flags = IEEE80211_CHAN_G | nflags; 1773 } else { /* 5GHz band */ 1774 c->ic_freq = ieee80211_ieee2mhz(chan, 1775 IEEE80211_CHAN_A); 1776 c->ic_flags = IEEE80211_CHAN_A | nflags; 1777 sc->sc_flags |= IWN_FLAG_HAS_5GHZ; 1778 } 1779 #if 0 /* HT */ 1780 /* XXX no constraints on using HT20 */ 1781 /* add HT20, HT40 added separately */ 1782 c = &ic->ic_channels[ic->ic_nchans++]; 1783 c[0] = c[-1]; 1784 c->ic_flags |= IEEE80211_CHAN_HT20; 1785 /* XXX NARROW =>'s 1/2 and 1/4 width? */ 1786 #endif 1787 } 1788 } 1789 1790 #if 0 /* HT */ 1791 static void 1792 iwn_read_eeprom_ht40(struct iwn_softc *sc, int n) 1793 { 1794 struct ifnet *ifp = sc->sc_ifp; 1795 struct ieee80211com *ic = ifp->if_l2com; 1796 struct iwn_eeprom_chan *channels = sc->eeprom_channels[n]; 1797 const struct iwn_chan_band *band = &iwn_bands[n]; 1798 struct ieee80211_channel *c, *cent, *extc; 1799 int i; 1800 1801 for (i = 0; i < band->nchan; i++) { 1802 if (!(channels[i].flags & IWN_EEPROM_CHAN_VALID) || 1803 !(channels[i].flags & IWN_EEPROM_CHAN_WIDE)) { 1804 DPRINTF(sc, IWN_DEBUG_RESET, 1805 "skip chan %d flags 0x%x maxpwr %d\n", 1806 band->chan[i], channels[i].flags, 1807 channels[i].maxpwr); 1808 continue; 1809 } 1810 /* 1811 * Each entry defines an HT40 channel pair; find the 1812 * center channel, then the extension channel above. 1813 */ 1814 cent = ieee80211_find_channel_byieee(ic, band->chan[i], 1815 band->flags & ~IEEE80211_CHAN_HT); 1816 if (cent == NULL) { /* XXX shouldn't happen */ 1817 device_printf(sc->sc_dev, 1818 "%s: no entry for channel %d\n", 1819 __func__, band->chan[i]); 1820 continue; 1821 } 1822 extc = ieee80211_find_channel(ic, cent->ic_freq+20, 1823 band->flags & ~IEEE80211_CHAN_HT); 1824 if (extc == NULL) { 1825 DPRINTF(sc, IWN_DEBUG_RESET, 1826 "skip chan %d, extension channel not found\n", 1827 band->chan[i]); 1828 continue; 1829 } 1830 1831 DPRINTF(sc, IWN_DEBUG_RESET, 1832 "add ht40 chan %d flags 0x%x maxpwr %d\n", 1833 band->chan[i], channels[i].flags, channels[i].maxpwr); 1834 1835 c = &ic->ic_channels[ic->ic_nchans++]; 1836 c[0] = cent[0]; 1837 c->ic_extieee = extc->ic_ieee; 1838 c->ic_flags &= ~IEEE80211_CHAN_HT; 1839 c->ic_flags |= IEEE80211_CHAN_HT40U; 1840 c = &ic->ic_channels[ic->ic_nchans++]; 1841 c[0] = extc[0]; 1842 c->ic_extieee = cent->ic_ieee; 1843 c->ic_flags &= ~IEEE80211_CHAN_HT; 1844 c->ic_flags |= IEEE80211_CHAN_HT40D; 1845 } 1846 } 1847 #endif 1848 1849 static void 1850 iwn_read_eeprom_channels(struct iwn_softc *sc, int n, uint32_t addr) 1851 { 1852 struct ifnet *ifp = sc->sc_ifp; 1853 struct ieee80211com *ic = ifp->if_l2com; 1854 1855 iwn_read_prom_data(sc, addr, &sc->eeprom_channels[n], 1856 iwn_bands[n].nchan * sizeof (struct iwn_eeprom_chan)); 1857 1858 if (n < 5) 1859 iwn_read_eeprom_band(sc, n); 1860 #if 0 /* HT */ 1861 else 1862 iwn_read_eeprom_ht40(sc, n); 1863 #endif 1864 ieee80211_sort_channels(ic->ic_channels, ic->ic_nchans); 1865 } 1866 1867 #define nitems(_a) (sizeof((_a)) / sizeof((_a)[0])) 1868 1869 static void 1870 iwn_read_eeprom_enhinfo(struct iwn_softc *sc) 1871 { 1872 struct iwn_eeprom_enhinfo enhinfo[35]; 1873 uint16_t val, base; 1874 int8_t maxpwr; 1875 int i; 1876 1877 iwn_read_prom_data(sc, IWN5000_EEPROM_REG, &val, 2); 1878 base = le16toh(val); 1879 iwn_read_prom_data(sc, base + IWN6000_EEPROM_ENHINFO, 1880 enhinfo, sizeof enhinfo); 1881 1882 memset(sc->enh_maxpwr, 0, sizeof sc->enh_maxpwr); 1883 for (i = 0; i < nitems(enhinfo); i++) { 1884 if (enhinfo[i].chan == 0 || enhinfo[i].reserved != 0) 1885 continue; /* Skip invalid entries. */ 1886 1887 maxpwr = 0; 1888 if (sc->txchainmask & IWN_ANT_A) 1889 maxpwr = MAX(maxpwr, enhinfo[i].chain[0]); 1890 if (sc->txchainmask & IWN_ANT_B) 1891 maxpwr = MAX(maxpwr, enhinfo[i].chain[1]); 1892 if (sc->txchainmask & IWN_ANT_C) 1893 maxpwr = MAX(maxpwr, enhinfo[i].chain[2]); 1894 if (sc->ntxchains == 2) 1895 maxpwr = MAX(maxpwr, enhinfo[i].mimo2); 1896 else if (sc->ntxchains == 3) 1897 maxpwr = MAX(maxpwr, enhinfo[i].mimo3); 1898 maxpwr /= 2; /* Convert half-dBm to dBm. */ 1899 1900 DPRINTF(sc, IWN_DEBUG_RESET, "enhinfo %d, maxpwr=%d\n", i, 1901 maxpwr); 1902 sc->enh_maxpwr[i] = maxpwr; 1903 } 1904 } 1905 1906 static struct ieee80211_node * 1907 iwn_node_alloc(struct ieee80211vap *vap, const uint8_t mac[IEEE80211_ADDR_LEN]) 1908 { 1909 return malloc(sizeof (struct iwn_node), M_80211_NODE,M_NOWAIT | M_ZERO); 1910 } 1911 1912 static void 1913 iwn_newassoc(struct ieee80211_node *ni, int isnew) 1914 { 1915 /* XXX move */ 1916 ieee80211_ratectl_node_init(ni); 1917 } 1918 1919 static int 1920 iwn_media_change(struct ifnet *ifp) 1921 { 1922 int error = ieee80211_media_change(ifp); 1923 /* NB: only the fixed rate can change and that doesn't need a reset */ 1924 return (error == ENETRESET ? 0 : error); 1925 } 1926 1927 static int 1928 iwn_newstate(struct ieee80211vap *vap, enum ieee80211_state nstate, int arg) 1929 { 1930 struct iwn_vap *ivp = IWN_VAP(vap); 1931 struct ieee80211com *ic = vap->iv_ic; 1932 struct iwn_softc *sc = ic->ic_ifp->if_softc; 1933 int error; 1934 1935 DPRINTF(sc, IWN_DEBUG_STATE, "%s: %s -> %s\n", __func__, 1936 ieee80211_state_name[vap->iv_state], 1937 ieee80211_state_name[nstate]); 1938 1939 IEEE80211_UNLOCK(ic); 1940 IWN_LOCK(sc); 1941 callout_stop(&sc->sc_timer_to); 1942 1943 if (nstate == IEEE80211_S_AUTH && vap->iv_state != IEEE80211_S_AUTH) { 1944 /* !AUTH -> AUTH requires adapter config */ 1945 /* Reset state to handle reassociations correctly. */ 1946 sc->rxon.associd = 0; 1947 sc->rxon.filter &= ~htole32(IWN_FILTER_BSS); 1948 iwn_calib_reset(sc); 1949 error = iwn_auth(sc, vap); 1950 } 1951 if (nstate == IEEE80211_S_RUN && vap->iv_state != IEEE80211_S_RUN) { 1952 /* 1953 * !RUN -> RUN requires setting the association id 1954 * which is done with a firmware cmd. We also defer 1955 * starting the timers until that work is done. 1956 */ 1957 error = iwn_run(sc, vap); 1958 } 1959 if (nstate == IEEE80211_S_RUN) { 1960 /* 1961 * RUN -> RUN transition; just restart the timers. 1962 */ 1963 iwn_calib_reset(sc); 1964 } 1965 IWN_UNLOCK(sc); 1966 IEEE80211_LOCK(ic); 1967 return ivp->iv_newstate(vap, nstate, arg); 1968 } 1969 1970 /* 1971 * Process an RX_PHY firmware notification. This is usually immediately 1972 * followed by an MPDU_RX_DONE notification. 1973 */ 1974 static void 1975 iwn_rx_phy(struct iwn_softc *sc, struct iwn_rx_desc *desc, 1976 struct iwn_rx_data *data) 1977 { 1978 struct iwn_rx_stat *stat = (struct iwn_rx_stat *)(desc + 1); 1979 1980 DPRINTF(sc, IWN_DEBUG_CALIBRATE, "%s: received PHY stats\n", __func__); 1981 bus_dmamap_sync(sc->rxq.data_dmat, data->map, BUS_DMASYNC_POSTREAD); 1982 1983 /* Save RX statistics, they will be used on MPDU_RX_DONE. */ 1984 memcpy(&sc->last_rx_stat, stat, sizeof (*stat)); 1985 sc->last_rx_valid = 1; 1986 } 1987 1988 static void 1989 iwn_timer_timeout(void *arg) 1990 { 1991 struct iwn_softc *sc = arg; 1992 uint32_t flags = 0; 1993 1994 IWN_LOCK_ASSERT(sc); 1995 1996 if (sc->calib_cnt && --sc->calib_cnt == 0) { 1997 DPRINTF(sc, IWN_DEBUG_CALIBRATE, "%s\n", 1998 "send statistics request"); 1999 (void) iwn_cmd(sc, IWN_CMD_GET_STATISTICS, &flags, 2000 sizeof flags, 1); 2001 sc->calib_cnt = 60; /* do calibration every 60s */ 2002 } 2003 iwn_watchdog(sc); /* NB: piggyback tx watchdog */ 2004 callout_reset(&sc->sc_timer_to, hz, iwn_timer_timeout, sc); 2005 } 2006 2007 static void 2008 iwn_calib_reset(struct iwn_softc *sc) 2009 { 2010 callout_reset(&sc->sc_timer_to, hz, iwn_timer_timeout, sc); 2011 sc->calib_cnt = 60; /* do calibration every 60s */ 2012 } 2013 2014 /* 2015 * Process an RX_DONE (4965AGN only) or MPDU_RX_DONE firmware notification. 2016 * Each MPDU_RX_DONE notification must be preceded by an RX_PHY one. 2017 */ 2018 static void 2019 iwn_rx_done(struct iwn_softc *sc, struct iwn_rx_desc *desc, 2020 struct iwn_rx_data *data) 2021 { 2022 const struct iwn_hal *hal = sc->sc_hal; 2023 struct ifnet *ifp = sc->sc_ifp; 2024 struct ieee80211com *ic = ifp->if_l2com; 2025 struct iwn_rx_ring *ring = &sc->rxq; 2026 struct ieee80211_frame *wh; 2027 struct ieee80211_node *ni; 2028 struct mbuf *m, *m1; 2029 struct iwn_rx_stat *stat; 2030 caddr_t head; 2031 bus_addr_t paddr; 2032 uint32_t flags; 2033 int error, len, rssi, nf; 2034 2035 if (desc->type == IWN_MPDU_RX_DONE) { 2036 /* Check for prior RX_PHY notification. */ 2037 if (!sc->last_rx_valid) { 2038 DPRINTF(sc, IWN_DEBUG_ANY, 2039 "%s: missing RX_PHY\n", __func__); 2040 ifp->if_ierrors++; 2041 return; 2042 } 2043 sc->last_rx_valid = 0; 2044 stat = &sc->last_rx_stat; 2045 } else 2046 stat = (struct iwn_rx_stat *)(desc + 1); 2047 2048 bus_dmamap_sync(ring->data_dmat, data->map, BUS_DMASYNC_POSTREAD); 2049 2050 if (stat->cfg_phy_len > IWN_STAT_MAXLEN) { 2051 device_printf(sc->sc_dev, 2052 "%s: invalid rx statistic header, len %d\n", 2053 __func__, stat->cfg_phy_len); 2054 ifp->if_ierrors++; 2055 return; 2056 } 2057 if (desc->type == IWN_MPDU_RX_DONE) { 2058 struct iwn_rx_mpdu *mpdu = (struct iwn_rx_mpdu *)(desc + 1); 2059 head = (caddr_t)(mpdu + 1); 2060 len = le16toh(mpdu->len); 2061 } else { 2062 head = (caddr_t)(stat + 1) + stat->cfg_phy_len; 2063 len = le16toh(stat->len); 2064 } 2065 2066 flags = le32toh(*(uint32_t *)(head + len)); 2067 2068 /* Discard frames with a bad FCS early. */ 2069 if ((flags & IWN_RX_NOERROR) != IWN_RX_NOERROR) { 2070 DPRINTF(sc, IWN_DEBUG_RECV, "%s: rx flags error %x\n", 2071 __func__, flags); 2072 ifp->if_ierrors++; 2073 return; 2074 } 2075 /* Discard frames that are too short. */ 2076 if (len < sizeof (*wh)) { 2077 DPRINTF(sc, IWN_DEBUG_RECV, "%s: frame too short: %d\n", 2078 __func__, len); 2079 ifp->if_ierrors++; 2080 return; 2081 } 2082 2083 /* XXX don't need mbuf, just dma buffer */ 2084 m1 = m_getjcl(M_DONTWAIT, MT_DATA, M_PKTHDR, MJUMPAGESIZE); 2085 if (m1 == NULL) { 2086 DPRINTF(sc, IWN_DEBUG_ANY, "%s: no mbuf to restock ring\n", 2087 __func__); 2088 ifp->if_ierrors++; 2089 return; 2090 } 2091 bus_dmamap_unload(ring->data_dmat, data->map); 2092 2093 error = bus_dmamap_load(ring->data_dmat, data->map, 2094 mtod(m1, caddr_t), MJUMPAGESIZE, 2095 iwn_dma_map_addr, &paddr, BUS_DMA_NOWAIT); 2096 if (error != 0 && error != EFBIG) { 2097 device_printf(sc->sc_dev, 2098 "%s: bus_dmamap_load failed, error %d\n", __func__, error); 2099 m_freem(m1); 2100 ifp->if_ierrors++; 2101 return; 2102 } 2103 2104 m = data->m; 2105 data->m = m1; 2106 /* Update RX descriptor. */ 2107 ring->desc[ring->cur] = htole32(paddr >> 8); 2108 bus_dmamap_sync(ring->desc_dma.tag, ring->desc_dma.map, 2109 BUS_DMASYNC_PREWRITE); 2110 2111 /* Finalize mbuf. */ 2112 m->m_pkthdr.rcvif = ifp; 2113 m->m_data = head; 2114 m->m_pkthdr.len = m->m_len = len; 2115 2116 rssi = hal->get_rssi(sc, stat); 2117 2118 /* Grab a reference to the source node. */ 2119 wh = mtod(m, struct ieee80211_frame *); 2120 ni = ieee80211_find_rxnode(ic, (struct ieee80211_frame_min *)wh); 2121 nf = (ni != NULL && ni->ni_vap->iv_state == IEEE80211_S_RUN && 2122 (ic->ic_flags & IEEE80211_F_SCAN) == 0) ? sc->noise : -95; 2123 2124 if (ieee80211_radiotap_active(ic)) { 2125 struct iwn_rx_radiotap_header *tap = &sc->sc_rxtap; 2126 2127 tap->wr_tsft = htole64(stat->tstamp); 2128 tap->wr_flags = 0; 2129 if (stat->flags & htole16(IWN_STAT_FLAG_SHPREAMBLE)) 2130 tap->wr_flags |= IEEE80211_RADIOTAP_F_SHORTPRE; 2131 switch (stat->rate) { 2132 /* CCK rates. */ 2133 case 10: tap->wr_rate = 2; break; 2134 case 20: tap->wr_rate = 4; break; 2135 case 55: tap->wr_rate = 11; break; 2136 case 110: tap->wr_rate = 22; break; 2137 /* OFDM rates. */ 2138 case 0xd: tap->wr_rate = 12; break; 2139 case 0xf: tap->wr_rate = 18; break; 2140 case 0x5: tap->wr_rate = 24; break; 2141 case 0x7: tap->wr_rate = 36; break; 2142 case 0x9: tap->wr_rate = 48; break; 2143 case 0xb: tap->wr_rate = 72; break; 2144 case 0x1: tap->wr_rate = 96; break; 2145 case 0x3: tap->wr_rate = 108; break; 2146 /* Unknown rate: should not happen. */ 2147 default: tap->wr_rate = 0; 2148 } 2149 tap->wr_dbm_antsignal = rssi; 2150 tap->wr_dbm_antnoise = nf; 2151 } 2152 2153 IWN_UNLOCK(sc); 2154 2155 /* Send the frame to the 802.11 layer. */ 2156 if (ni != NULL) { 2157 (void) ieee80211_input(ni, m, rssi - nf, nf); 2158 /* Node is no longer needed. */ 2159 ieee80211_free_node(ni); 2160 } else 2161 (void) ieee80211_input_all(ic, m, rssi - nf, nf); 2162 2163 IWN_LOCK(sc); 2164 } 2165 2166 #if 0 /* HT */ 2167 /* Process an incoming Compressed BlockAck. */ 2168 static void 2169 iwn_rx_compressed_ba(struct iwn_softc *sc, struct iwn_rx_desc *desc, 2170 struct iwn_rx_data *data) 2171 { 2172 struct iwn_compressed_ba *ba = (struct iwn_compressed_ba *)(desc + 1); 2173 struct iwn_tx_ring *txq; 2174 2175 txq = &sc->txq[letoh16(ba->qid)]; 2176 /* XXX TBD */ 2177 } 2178 #endif 2179 2180 /* 2181 * Process a CALIBRATION_RESULT notification sent by the initialization 2182 * firmware on response to a CMD_CALIB_CONFIG command (5000 only.) 2183 */ 2184 static void 2185 iwn5000_rx_calib_results(struct iwn_softc *sc, struct iwn_rx_desc *desc, 2186 struct iwn_rx_data *data) 2187 { 2188 struct iwn_phy_calib *calib = (struct iwn_phy_calib *)(desc + 1); 2189 int len, idx = -1; 2190 2191 /* Runtime firmware should not send such a notification. */ 2192 if (sc->sc_flags & IWN_FLAG_CALIB_DONE) 2193 return; 2194 2195 bus_dmamap_sync(sc->rxq.data_dmat, data->map, BUS_DMASYNC_POSTREAD); 2196 len = (le32toh(desc->len) & 0x3fff) - 4; 2197 2198 switch (calib->code) { 2199 case IWN5000_PHY_CALIB_DC: 2200 if (sc->hw_type == IWN_HW_REV_TYPE_5150 || 2201 sc->hw_type == IWN_HW_REV_TYPE_6050) 2202 idx = 0; 2203 break; 2204 case IWN5000_PHY_CALIB_LO: 2205 idx = 1; 2206 break; 2207 case IWN5000_PHY_CALIB_TX_IQ: 2208 idx = 2; 2209 break; 2210 case IWN5000_PHY_CALIB_TX_IQ_PERIODIC: 2211 if (sc->hw_type < IWN_HW_REV_TYPE_6000 && 2212 sc->hw_type != IWN_HW_REV_TYPE_5150) 2213 idx = 3; 2214 break; 2215 case IWN5000_PHY_CALIB_BASE_BAND: 2216 idx = 4; 2217 break; 2218 } 2219 if (idx == -1) /* Ignore other results. */ 2220 return; 2221 2222 /* Save calibration result. */ 2223 if (sc->calibcmd[idx].buf != NULL) 2224 free(sc->calibcmd[idx].buf, M_DEVBUF); 2225 sc->calibcmd[idx].buf = malloc(len, M_DEVBUF, M_NOWAIT); 2226 if (sc->calibcmd[idx].buf == NULL) { 2227 DPRINTF(sc, IWN_DEBUG_CALIBRATE, 2228 "not enough memory for calibration result %d\n", 2229 calib->code); 2230 return; 2231 } 2232 DPRINTF(sc, IWN_DEBUG_CALIBRATE, 2233 "saving calibration result code=%d len=%d\n", calib->code, len); 2234 sc->calibcmd[idx].len = len; 2235 memcpy(sc->calibcmd[idx].buf, calib, len); 2236 } 2237 2238 /* 2239 * Process an RX_STATISTICS or BEACON_STATISTICS firmware notification. 2240 * The latter is sent by the firmware after each received beacon. 2241 */ 2242 static void 2243 iwn_rx_statistics(struct iwn_softc *sc, struct iwn_rx_desc *desc, 2244 struct iwn_rx_data *data) 2245 { 2246 const struct iwn_hal *hal = sc->sc_hal; 2247 struct ifnet *ifp = sc->sc_ifp; 2248 struct ieee80211com *ic = ifp->if_l2com; 2249 struct ieee80211vap *vap = TAILQ_FIRST(&ic->ic_vaps); 2250 struct iwn_calib_state *calib = &sc->calib; 2251 struct iwn_stats *stats = (struct iwn_stats *)(desc + 1); 2252 int temp; 2253 2254 /* Beacon stats are meaningful only when associated and not scanning. */ 2255 if (vap->iv_state != IEEE80211_S_RUN || 2256 (ic->ic_flags & IEEE80211_F_SCAN)) 2257 return; 2258 2259 bus_dmamap_sync(sc->rxq.data_dmat, data->map, BUS_DMASYNC_POSTREAD); 2260 DPRINTF(sc, IWN_DEBUG_CALIBRATE, "%s: cmd %d\n", __func__, desc->type); 2261 iwn_calib_reset(sc); /* Reset TX power calibration timeout. */ 2262 2263 /* Test if temperature has changed. */ 2264 if (stats->general.temp != sc->rawtemp) { 2265 /* Convert "raw" temperature to degC. */ 2266 sc->rawtemp = stats->general.temp; 2267 temp = hal->get_temperature(sc); 2268 DPRINTF(sc, IWN_DEBUG_CALIBRATE, "%s: temperature %d\n", 2269 __func__, temp); 2270 2271 /* Update TX power if need be (4965AGN only.) */ 2272 if (sc->hw_type == IWN_HW_REV_TYPE_4965) 2273 iwn4965_power_calibration(sc, temp); 2274 } 2275 2276 if (desc->type != IWN_BEACON_STATISTICS) 2277 return; /* Reply to a statistics request. */ 2278 2279 sc->noise = iwn_get_noise(&stats->rx.general); 2280 DPRINTF(sc, IWN_DEBUG_CALIBRATE, "%s: noise %d\n", __func__, sc->noise); 2281 2282 /* Test that RSSI and noise are present in stats report. */ 2283 if (le32toh(stats->rx.general.flags) != 1) { 2284 DPRINTF(sc, IWN_DEBUG_ANY, "%s\n", 2285 "received statistics without RSSI"); 2286 return; 2287 } 2288 2289 if (calib->state == IWN_CALIB_STATE_ASSOC) 2290 iwn_collect_noise(sc, &stats->rx.general); 2291 else if (calib->state == IWN_CALIB_STATE_RUN) 2292 iwn_tune_sensitivity(sc, &stats->rx); 2293 } 2294 2295 /* 2296 * Process a TX_DONE firmware notification. Unfortunately, the 4965AGN 2297 * and 5000 adapters have different incompatible TX status formats. 2298 */ 2299 static void 2300 iwn4965_tx_done(struct iwn_softc *sc, struct iwn_rx_desc *desc, 2301 struct iwn_rx_data *data) 2302 { 2303 struct iwn4965_tx_stat *stat = (struct iwn4965_tx_stat *)(desc + 1); 2304 struct iwn_tx_ring *ring = &sc->txq[desc->qid & 0xf]; 2305 2306 DPRINTF(sc, IWN_DEBUG_XMIT, "%s: " 2307 "qid %d idx %d retries %d nkill %d rate %x duration %d status %x\n", 2308 __func__, desc->qid, desc->idx, stat->ackfailcnt, 2309 stat->btkillcnt, stat->rate, le16toh(stat->duration), 2310 le32toh(stat->status)); 2311 2312 bus_dmamap_sync(ring->data_dmat, data->map, BUS_DMASYNC_POSTREAD); 2313 iwn_tx_done(sc, desc, stat->ackfailcnt, le32toh(stat->status) & 0xff); 2314 } 2315 2316 static void 2317 iwn5000_tx_done(struct iwn_softc *sc, struct iwn_rx_desc *desc, 2318 struct iwn_rx_data *data) 2319 { 2320 struct iwn5000_tx_stat *stat = (struct iwn5000_tx_stat *)(desc + 1); 2321 struct iwn_tx_ring *ring = &sc->txq[desc->qid & 0xf]; 2322 2323 DPRINTF(sc, IWN_DEBUG_XMIT, "%s: " 2324 "qid %d idx %d retries %d nkill %d rate %x duration %d status %x\n", 2325 __func__, desc->qid, desc->idx, stat->ackfailcnt, 2326 stat->btkillcnt, stat->rate, le16toh(stat->duration), 2327 le32toh(stat->status)); 2328 2329 #ifdef notyet 2330 /* Reset TX scheduler slot. */ 2331 iwn5000_reset_sched(sc, desc->qid & 0xf, desc->idx); 2332 #endif 2333 2334 bus_dmamap_sync(ring->data_dmat, data->map, BUS_DMASYNC_POSTREAD); 2335 iwn_tx_done(sc, desc, stat->ackfailcnt, le16toh(stat->status) & 0xff); 2336 } 2337 2338 /* 2339 * Adapter-independent backend for TX_DONE firmware notifications. 2340 */ 2341 static void 2342 iwn_tx_done(struct iwn_softc *sc, struct iwn_rx_desc *desc, int ackfailcnt, 2343 uint8_t status) 2344 { 2345 struct ifnet *ifp = sc->sc_ifp; 2346 struct iwn_tx_ring *ring = &sc->txq[desc->qid & 0xf]; 2347 struct iwn_tx_data *data = &ring->data[desc->idx]; 2348 struct mbuf *m; 2349 struct ieee80211_node *ni; 2350 struct ieee80211vap *vap; 2351 2352 KASSERT(data->ni != NULL, ("no node")); 2353 2354 /* Unmap and free mbuf. */ 2355 bus_dmamap_sync(ring->data_dmat, data->map, BUS_DMASYNC_POSTWRITE); 2356 bus_dmamap_unload(ring->data_dmat, data->map); 2357 m = data->m, data->m = NULL; 2358 ni = data->ni, data->ni = NULL; 2359 vap = ni->ni_vap; 2360 2361 if (m->m_flags & M_TXCB) { 2362 /* 2363 * Channels marked for "radar" require traffic to be received 2364 * to unlock before we can transmit. Until traffic is seen 2365 * any attempt to transmit is returned immediately with status 2366 * set to IWN_TX_FAIL_TX_LOCKED. Unfortunately this can easily 2367 * happen on first authenticate after scanning. To workaround 2368 * this we ignore a failure of this sort in AUTH state so the 2369 * 802.11 layer will fall back to using a timeout to wait for 2370 * the AUTH reply. This allows the firmware time to see 2371 * traffic so a subsequent retry of AUTH succeeds. It's 2372 * unclear why the firmware does not maintain state for 2373 * channels recently visited as this would allow immediate 2374 * use of the channel after a scan (where we see traffic). 2375 */ 2376 if (status == IWN_TX_FAIL_TX_LOCKED && 2377 ni->ni_vap->iv_state == IEEE80211_S_AUTH) 2378 ieee80211_process_callback(ni, m, 0); 2379 else 2380 ieee80211_process_callback(ni, m, 2381 (status & IWN_TX_FAIL) != 0); 2382 } 2383 2384 /* 2385 * Update rate control statistics for the node. 2386 */ 2387 if (status & 0x80) { 2388 ifp->if_oerrors++; 2389 ieee80211_ratectl_tx_complete(vap, ni, 2390 IEEE80211_RATECTL_TX_FAILURE, &ackfailcnt, NULL); 2391 } else { 2392 ieee80211_ratectl_tx_complete(vap, ni, 2393 IEEE80211_RATECTL_TX_SUCCESS, &ackfailcnt, NULL); 2394 } 2395 m_freem(m); 2396 ieee80211_free_node(ni); 2397 2398 sc->sc_tx_timer = 0; 2399 if (--ring->queued < IWN_TX_RING_LOMARK) { 2400 sc->qfullmsk &= ~(1 << ring->qid); 2401 if (sc->qfullmsk == 0 && 2402 (ifp->if_drv_flags & IFF_DRV_OACTIVE)) { 2403 ifp->if_drv_flags &= ~IFF_DRV_OACTIVE; 2404 iwn_start_locked(ifp); 2405 } 2406 } 2407 } 2408 2409 /* 2410 * Process a "command done" firmware notification. This is where we wakeup 2411 * processes waiting for a synchronous command completion. 2412 */ 2413 static void 2414 iwn_cmd_done(struct iwn_softc *sc, struct iwn_rx_desc *desc) 2415 { 2416 struct iwn_tx_ring *ring = &sc->txq[4]; 2417 struct iwn_tx_data *data; 2418 2419 if ((desc->qid & 0xf) != 4) 2420 return; /* Not a command ack. */ 2421 2422 data = &ring->data[desc->idx]; 2423 2424 /* If the command was mapped in an mbuf, free it. */ 2425 if (data->m != NULL) { 2426 bus_dmamap_unload(ring->data_dmat, data->map); 2427 m_freem(data->m); 2428 data->m = NULL; 2429 } 2430 wakeup(&ring->desc[desc->idx]); 2431 } 2432 2433 /* 2434 * Process an INT_FH_RX or INT_SW_RX interrupt. 2435 */ 2436 static void 2437 iwn_notif_intr(struct iwn_softc *sc) 2438 { 2439 struct ifnet *ifp = sc->sc_ifp; 2440 struct ieee80211com *ic = ifp->if_l2com; 2441 struct ieee80211vap *vap = TAILQ_FIRST(&ic->ic_vaps); 2442 uint16_t hw; 2443 2444 bus_dmamap_sync(sc->rxq.stat_dma.tag, sc->rxq.stat_dma.map, 2445 BUS_DMASYNC_POSTREAD); 2446 2447 hw = le16toh(sc->rxq.stat->closed_count) & 0xfff; 2448 while (sc->rxq.cur != hw) { 2449 struct iwn_rx_data *data = &sc->rxq.data[sc->rxq.cur]; 2450 struct iwn_rx_desc *desc; 2451 2452 bus_dmamap_sync(sc->rxq.data_dmat, data->map, 2453 BUS_DMASYNC_POSTREAD); 2454 desc = mtod(data->m, struct iwn_rx_desc *); 2455 2456 DPRINTF(sc, IWN_DEBUG_RECV, 2457 "%s: qid %x idx %d flags %x type %d(%s) len %d\n", 2458 __func__, desc->qid & 0xf, desc->idx, desc->flags, 2459 desc->type, iwn_intr_str(desc->type), 2460 le16toh(desc->len)); 2461 2462 if (!(desc->qid & 0x80)) /* Reply to a command. */ 2463 iwn_cmd_done(sc, desc); 2464 2465 switch (desc->type) { 2466 case IWN_RX_PHY: 2467 iwn_rx_phy(sc, desc, data); 2468 break; 2469 2470 case IWN_RX_DONE: /* 4965AGN only. */ 2471 case IWN_MPDU_RX_DONE: 2472 /* An 802.11 frame has been received. */ 2473 iwn_rx_done(sc, desc, data); 2474 break; 2475 2476 #if 0 /* HT */ 2477 case IWN_RX_COMPRESSED_BA: 2478 /* A Compressed BlockAck has been received. */ 2479 iwn_rx_compressed_ba(sc, desc, data); 2480 break; 2481 #endif 2482 2483 case IWN_TX_DONE: 2484 /* An 802.11 frame has been transmitted. */ 2485 sc->sc_hal->tx_done(sc, desc, data); 2486 break; 2487 2488 case IWN_RX_STATISTICS: 2489 case IWN_BEACON_STATISTICS: 2490 iwn_rx_statistics(sc, desc, data); 2491 break; 2492 2493 case IWN_BEACON_MISSED: 2494 { 2495 struct iwn_beacon_missed *miss = 2496 (struct iwn_beacon_missed *)(desc + 1); 2497 int misses; 2498 2499 bus_dmamap_sync(sc->rxq.data_dmat, data->map, 2500 BUS_DMASYNC_POSTREAD); 2501 misses = le32toh(miss->consecutive); 2502 2503 /* XXX not sure why we're notified w/ zero */ 2504 if (misses == 0) 2505 break; 2506 DPRINTF(sc, IWN_DEBUG_STATE, 2507 "%s: beacons missed %d/%d\n", __func__, 2508 misses, le32toh(miss->total)); 2509 2510 /* 2511 * If more than 5 consecutive beacons are missed, 2512 * reinitialize the sensitivity state machine. 2513 */ 2514 if (vap->iv_state == IEEE80211_S_RUN && misses > 5) 2515 (void) iwn_init_sensitivity(sc); 2516 if (misses >= vap->iv_bmissthreshold) { 2517 IWN_UNLOCK(sc); 2518 ieee80211_beacon_miss(ic); 2519 IWN_LOCK(sc); 2520 } 2521 break; 2522 } 2523 case IWN_UC_READY: 2524 { 2525 struct iwn_ucode_info *uc = 2526 (struct iwn_ucode_info *)(desc + 1); 2527 2528 /* The microcontroller is ready. */ 2529 bus_dmamap_sync(sc->rxq.data_dmat, data->map, 2530 BUS_DMASYNC_POSTREAD); 2531 DPRINTF(sc, IWN_DEBUG_RESET, 2532 "microcode alive notification version=%d.%d " 2533 "subtype=%x alive=%x\n", uc->major, uc->minor, 2534 uc->subtype, le32toh(uc->valid)); 2535 2536 if (le32toh(uc->valid) != 1) { 2537 device_printf(sc->sc_dev, 2538 "microcontroller initialization failed"); 2539 break; 2540 } 2541 if (uc->subtype == IWN_UCODE_INIT) { 2542 /* Save microcontroller report. */ 2543 memcpy(&sc->ucode_info, uc, sizeof (*uc)); 2544 } 2545 /* Save the address of the error log in SRAM. */ 2546 sc->errptr = le32toh(uc->errptr); 2547 break; 2548 } 2549 case IWN_STATE_CHANGED: 2550 { 2551 uint32_t *status = (uint32_t *)(desc + 1); 2552 2553 /* 2554 * State change allows hardware switch change to be 2555 * noted. However, we handle this in iwn_intr as we 2556 * get both the enable/disble intr. 2557 */ 2558 bus_dmamap_sync(sc->rxq.data_dmat, data->map, 2559 BUS_DMASYNC_POSTREAD); 2560 DPRINTF(sc, IWN_DEBUG_INTR, "state changed to %x\n", 2561 le32toh(*status)); 2562 break; 2563 } 2564 case IWN_START_SCAN: 2565 { 2566 struct iwn_start_scan *scan = 2567 (struct iwn_start_scan *)(desc + 1); 2568 2569 bus_dmamap_sync(sc->rxq.data_dmat, data->map, 2570 BUS_DMASYNC_POSTREAD); 2571 DPRINTF(sc, IWN_DEBUG_ANY, 2572 "%s: scanning channel %d status %x\n", 2573 __func__, scan->chan, le32toh(scan->status)); 2574 break; 2575 } 2576 case IWN_STOP_SCAN: 2577 { 2578 struct iwn_stop_scan *scan = 2579 (struct iwn_stop_scan *)(desc + 1); 2580 2581 bus_dmamap_sync(sc->rxq.data_dmat, data->map, 2582 BUS_DMASYNC_POSTREAD); 2583 DPRINTF(sc, IWN_DEBUG_STATE, 2584 "scan finished nchan=%d status=%d chan=%d\n", 2585 scan->nchan, scan->status, scan->chan); 2586 2587 IWN_UNLOCK(sc); 2588 ieee80211_scan_next(vap); 2589 IWN_LOCK(sc); 2590 break; 2591 } 2592 case IWN5000_CALIBRATION_RESULT: 2593 iwn5000_rx_calib_results(sc, desc, data); 2594 break; 2595 2596 case IWN5000_CALIBRATION_DONE: 2597 sc->sc_flags |= IWN_FLAG_CALIB_DONE; 2598 wakeup(sc); 2599 break; 2600 } 2601 2602 sc->rxq.cur = (sc->rxq.cur + 1) % IWN_RX_RING_COUNT; 2603 } 2604 2605 /* Tell the firmware what we have processed. */ 2606 hw = (hw == 0) ? IWN_RX_RING_COUNT - 1 : hw - 1; 2607 IWN_WRITE(sc, IWN_FH_RX_WPTR, hw & ~7); 2608 } 2609 2610 /* 2611 * Process an INT_WAKEUP interrupt raised when the microcontroller wakes up 2612 * from power-down sleep mode. 2613 */ 2614 static void 2615 iwn_wakeup_intr(struct iwn_softc *sc) 2616 { 2617 int qid; 2618 2619 DPRINTF(sc, IWN_DEBUG_RESET, "%s: ucode wakeup from power-down sleep\n", 2620 __func__); 2621 2622 /* Wakeup RX and TX rings. */ 2623 IWN_WRITE(sc, IWN_FH_RX_WPTR, sc->rxq.cur & ~7); 2624 for (qid = 0; qid < sc->sc_hal->ntxqs; qid++) { 2625 struct iwn_tx_ring *ring = &sc->txq[qid]; 2626 IWN_WRITE(sc, IWN_HBUS_TARG_WRPTR, qid << 8 | ring->cur); 2627 } 2628 } 2629 2630 static void 2631 iwn_rftoggle_intr(struct iwn_softc *sc) 2632 { 2633 struct ifnet *ifp = sc->sc_ifp; 2634 struct ieee80211com *ic = ifp->if_l2com; 2635 uint32_t tmp = IWN_READ(sc, IWN_GP_CNTRL); 2636 2637 IWN_LOCK_ASSERT(sc); 2638 2639 device_printf(sc->sc_dev, "RF switch: radio %s\n", 2640 (tmp & IWN_GP_CNTRL_RFKILL) ? "enabled" : "disabled"); 2641 if (tmp & IWN_GP_CNTRL_RFKILL) 2642 ieee80211_runtask(ic, &sc->sc_radioon_task); 2643 else 2644 ieee80211_runtask(ic, &sc->sc_radiooff_task); 2645 } 2646 2647 /* 2648 * Dump the error log of the firmware when a firmware panic occurs. Although 2649 * we can't debug the firmware because it is neither open source nor free, it 2650 * can help us to identify certain classes of problems. 2651 */ 2652 static void 2653 iwn_fatal_intr(struct iwn_softc *sc) 2654 { 2655 const struct iwn_hal *hal = sc->sc_hal; 2656 struct iwn_fw_dump dump; 2657 int i; 2658 2659 IWN_LOCK_ASSERT(sc); 2660 2661 /* Force a complete recalibration on next init. */ 2662 sc->sc_flags &= ~IWN_FLAG_CALIB_DONE; 2663 2664 /* Check that the error log address is valid. */ 2665 if (sc->errptr < IWN_FW_DATA_BASE || 2666 sc->errptr + sizeof (dump) > 2667 IWN_FW_DATA_BASE + hal->fw_data_maxsz) { 2668 printf("%s: bad firmware error log address 0x%08x\n", 2669 __func__, sc->errptr); 2670 return; 2671 } 2672 if (iwn_nic_lock(sc) != 0) { 2673 printf("%s: could not read firmware error log\n", 2674 __func__); 2675 return; 2676 } 2677 /* Read firmware error log from SRAM. */ 2678 iwn_mem_read_region_4(sc, sc->errptr, (uint32_t *)&dump, 2679 sizeof (dump) / sizeof (uint32_t)); 2680 iwn_nic_unlock(sc); 2681 2682 if (dump.valid == 0) { 2683 printf("%s: firmware error log is empty\n", 2684 __func__); 2685 return; 2686 } 2687 printf("firmware error log:\n"); 2688 printf(" error type = \"%s\" (0x%08X)\n", 2689 (dump.id < nitems(iwn_fw_errmsg)) ? 2690 iwn_fw_errmsg[dump.id] : "UNKNOWN", 2691 dump.id); 2692 printf(" program counter = 0x%08X\n", dump.pc); 2693 printf(" source line = 0x%08X\n", dump.src_line); 2694 printf(" error data = 0x%08X%08X\n", 2695 dump.error_data[0], dump.error_data[1]); 2696 printf(" branch link = 0x%08X%08X\n", 2697 dump.branch_link[0], dump.branch_link[1]); 2698 printf(" interrupt link = 0x%08X%08X\n", 2699 dump.interrupt_link[0], dump.interrupt_link[1]); 2700 printf(" time = %u\n", dump.time[0]); 2701 2702 /* Dump driver status (TX and RX rings) while we're here. */ 2703 printf("driver status:\n"); 2704 for (i = 0; i < hal->ntxqs; i++) { 2705 struct iwn_tx_ring *ring = &sc->txq[i]; 2706 printf(" tx ring %2d: qid=%-2d cur=%-3d queued=%-3d\n", 2707 i, ring->qid, ring->cur, ring->queued); 2708 } 2709 printf(" rx ring: cur=%d\n", sc->rxq.cur); 2710 } 2711 2712 static void 2713 iwn_intr(void *arg) 2714 { 2715 struct iwn_softc *sc = arg; 2716 struct ifnet *ifp = sc->sc_ifp; 2717 uint32_t r1, r2, tmp; 2718 2719 IWN_LOCK(sc); 2720 2721 /* Disable interrupts. */ 2722 IWN_WRITE(sc, IWN_INT_MASK, 0); 2723 2724 /* Read interrupts from ICT (fast) or from registers (slow). */ 2725 if (sc->sc_flags & IWN_FLAG_USE_ICT) { 2726 tmp = 0; 2727 while (sc->ict[sc->ict_cur] != 0) { 2728 tmp |= sc->ict[sc->ict_cur]; 2729 sc->ict[sc->ict_cur] = 0; /* Acknowledge. */ 2730 sc->ict_cur = (sc->ict_cur + 1) % IWN_ICT_COUNT; 2731 } 2732 tmp = le32toh(tmp); 2733 if (tmp == 0xffffffff) /* Shouldn't happen. */ 2734 tmp = 0; 2735 else if (tmp & 0xc0000) /* Workaround a HW bug. */ 2736 tmp |= 0x8000; 2737 r1 = (tmp & 0xff00) << 16 | (tmp & 0xff); 2738 r2 = 0; /* Unused. */ 2739 } else { 2740 r1 = IWN_READ(sc, IWN_INT); 2741 if (r1 == 0xffffffff || (r1 & 0xfffffff0) == 0xa5a5a5a0) 2742 return; /* Hardware gone! */ 2743 r2 = IWN_READ(sc, IWN_FH_INT); 2744 } 2745 2746 DPRINTF(sc, IWN_DEBUG_INTR, "interrupt reg1=%x reg2=%x\n", r1, r2); 2747 2748 if (r1 == 0 && r2 == 0) 2749 goto done; /* Interrupt not for us. */ 2750 2751 /* Acknowledge interrupts. */ 2752 IWN_WRITE(sc, IWN_INT, r1); 2753 if (!(sc->sc_flags & IWN_FLAG_USE_ICT)) 2754 IWN_WRITE(sc, IWN_FH_INT, r2); 2755 2756 if (r1 & IWN_INT_RF_TOGGLED) { 2757 iwn_rftoggle_intr(sc); 2758 goto done; 2759 } 2760 if (r1 & IWN_INT_CT_REACHED) { 2761 device_printf(sc->sc_dev, "%s: critical temperature reached!\n", 2762 __func__); 2763 } 2764 if (r1 & (IWN_INT_SW_ERR | IWN_INT_HW_ERR)) { 2765 iwn_fatal_intr(sc); 2766 ifp->if_flags &= ~IFF_UP; 2767 iwn_stop_locked(sc); 2768 goto done; 2769 } 2770 if ((r1 & (IWN_INT_FH_RX | IWN_INT_SW_RX | IWN_INT_RX_PERIODIC)) || 2771 (r2 & IWN_FH_INT_RX)) { 2772 if (sc->sc_flags & IWN_FLAG_USE_ICT) { 2773 if (r1 & (IWN_INT_FH_RX | IWN_INT_SW_RX)) 2774 IWN_WRITE(sc, IWN_FH_INT, IWN_FH_INT_RX); 2775 IWN_WRITE_1(sc, IWN_INT_PERIODIC, 2776 IWN_INT_PERIODIC_DIS); 2777 iwn_notif_intr(sc); 2778 if (r1 & (IWN_INT_FH_RX | IWN_INT_SW_RX)) { 2779 IWN_WRITE_1(sc, IWN_INT_PERIODIC, 2780 IWN_INT_PERIODIC_ENA); 2781 } 2782 } else 2783 iwn_notif_intr(sc); 2784 } 2785 2786 if ((r1 & IWN_INT_FH_TX) || (r2 & IWN_FH_INT_TX)) { 2787 if (sc->sc_flags & IWN_FLAG_USE_ICT) 2788 IWN_WRITE(sc, IWN_FH_INT, IWN_FH_INT_TX); 2789 wakeup(sc); /* FH DMA transfer completed. */ 2790 } 2791 2792 if (r1 & IWN_INT_ALIVE) 2793 wakeup(sc); /* Firmware is alive. */ 2794 2795 if (r1 & IWN_INT_WAKEUP) 2796 iwn_wakeup_intr(sc); 2797 2798 done: 2799 /* Re-enable interrupts. */ 2800 if (ifp->if_flags & IFF_UP) 2801 IWN_WRITE(sc, IWN_INT_MASK, sc->int_mask); 2802 2803 IWN_UNLOCK(sc); 2804 } 2805 2806 /* 2807 * Update TX scheduler ring when transmitting an 802.11 frame (4965AGN and 2808 * 5000 adapters use a slightly different format.) 2809 */ 2810 static void 2811 iwn4965_update_sched(struct iwn_softc *sc, int qid, int idx, uint8_t id, 2812 uint16_t len) 2813 { 2814 uint16_t *w = &sc->sched[qid * IWN4965_SCHED_COUNT + idx]; 2815 2816 *w = htole16(len + 8); 2817 bus_dmamap_sync(sc->sched_dma.tag, sc->sched_dma.map, 2818 BUS_DMASYNC_PREWRITE); 2819 if (idx < IWN_SCHED_WINSZ) { 2820 *(w + IWN_TX_RING_COUNT) = *w; 2821 bus_dmamap_sync(sc->sched_dma.tag, sc->sched_dma.map, 2822 BUS_DMASYNC_PREWRITE); 2823 } 2824 } 2825 2826 static void 2827 iwn5000_update_sched(struct iwn_softc *sc, int qid, int idx, uint8_t id, 2828 uint16_t len) 2829 { 2830 uint16_t *w = &sc->sched[qid * IWN5000_SCHED_COUNT + idx]; 2831 2832 *w = htole16(id << 12 | (len + 8)); 2833 2834 bus_dmamap_sync(sc->sched_dma.tag, sc->sched_dma.map, 2835 BUS_DMASYNC_PREWRITE); 2836 if (idx < IWN_SCHED_WINSZ) { 2837 *(w + IWN_TX_RING_COUNT) = *w; 2838 bus_dmamap_sync(sc->sched_dma.tag, sc->sched_dma.map, 2839 BUS_DMASYNC_PREWRITE); 2840 } 2841 } 2842 2843 #ifdef notyet 2844 static void 2845 iwn5000_reset_sched(struct iwn_softc *sc, int qid, int idx) 2846 { 2847 uint16_t *w = &sc->sched[qid * IWN5000_SCHED_COUNT + idx]; 2848 2849 *w = (*w & htole16(0xf000)) | htole16(1); 2850 bus_dmamap_sync(sc->sched_dma.tag, sc->sched_dma.map, 2851 BUS_DMASYNC_PREWRITE); 2852 if (idx < IWN_SCHED_WINSZ) { 2853 *(w + IWN_TX_RING_COUNT) = *w; 2854 bus_dmamap_sync(sc->sched_dma.tag, sc->sched_dma.map, 2855 BUS_DMASYNC_PREWRITE); 2856 } 2857 } 2858 #endif 2859 2860 static uint8_t 2861 iwn_plcp_signal(int rate) { 2862 int i; 2863 2864 for (i = 0; i < IWN_RIDX_MAX + 1; i++) { 2865 if (rate == iwn_rates[i].rate) 2866 return i; 2867 } 2868 2869 return 0; 2870 } 2871 2872 static int 2873 iwn_tx_data(struct iwn_softc *sc, struct mbuf *m, struct ieee80211_node *ni, 2874 struct iwn_tx_ring *ring) 2875 { 2876 const struct iwn_hal *hal = sc->sc_hal; 2877 const struct ieee80211_txparam *tp; 2878 const struct iwn_rate *rinfo; 2879 struct ieee80211vap *vap = ni->ni_vap; 2880 struct ieee80211com *ic = ni->ni_ic; 2881 struct iwn_node *wn = (void *)ni; 2882 struct iwn_tx_desc *desc; 2883 struct iwn_tx_data *data; 2884 struct iwn_tx_cmd *cmd; 2885 struct iwn_cmd_data *tx; 2886 struct ieee80211_frame *wh; 2887 struct ieee80211_key *k = NULL; 2888 struct mbuf *mnew; 2889 bus_dma_segment_t segs[IWN_MAX_SCATTER]; 2890 uint32_t flags; 2891 u_int hdrlen; 2892 int totlen, error, pad, nsegs = 0, i, rate; 2893 uint8_t ridx, type, txant; 2894 2895 IWN_LOCK_ASSERT(sc); 2896 2897 wh = mtod(m, struct ieee80211_frame *); 2898 hdrlen = ieee80211_anyhdrsize(wh); 2899 type = wh->i_fc[0] & IEEE80211_FC0_TYPE_MASK; 2900 2901 desc = &ring->desc[ring->cur]; 2902 data = &ring->data[ring->cur]; 2903 2904 /* Choose a TX rate index. */ 2905 tp = &vap->iv_txparms[ieee80211_chan2mode(ni->ni_chan)]; 2906 if (type == IEEE80211_FC0_TYPE_MGT) 2907 rate = tp->mgmtrate; 2908 else if (IEEE80211_IS_MULTICAST(wh->i_addr1)) 2909 rate = tp->mcastrate; 2910 else if (tp->ucastrate != IEEE80211_FIXED_RATE_NONE) 2911 rate = tp->ucastrate; 2912 else { 2913 /* XXX pass pktlen */ 2914 (void) ieee80211_ratectl_rate(ni, NULL, 0); 2915 rate = ni->ni_txrate; 2916 } 2917 ridx = iwn_plcp_signal(rate); 2918 rinfo = &iwn_rates[ridx]; 2919 2920 /* Encrypt the frame if need be. */ 2921 if (wh->i_fc[1] & IEEE80211_FC1_WEP) { 2922 k = ieee80211_crypto_encap(ni, m); 2923 if (k == NULL) { 2924 m_freem(m); 2925 return ENOBUFS; 2926 } 2927 /* Packet header may have moved, reset our local pointer. */ 2928 wh = mtod(m, struct ieee80211_frame *); 2929 } 2930 totlen = m->m_pkthdr.len; 2931 2932 if (ieee80211_radiotap_active_vap(vap)) { 2933 struct iwn_tx_radiotap_header *tap = &sc->sc_txtap; 2934 2935 tap->wt_flags = 0; 2936 tap->wt_rate = rinfo->rate; 2937 if (k != NULL) 2938 tap->wt_flags |= IEEE80211_RADIOTAP_F_WEP; 2939 2940 ieee80211_radiotap_tx(vap, m); 2941 } 2942 2943 /* Prepare TX firmware command. */ 2944 cmd = &ring->cmd[ring->cur]; 2945 cmd->code = IWN_CMD_TX_DATA; 2946 cmd->flags = 0; 2947 cmd->qid = ring->qid; 2948 cmd->idx = ring->cur; 2949 2950 tx = (struct iwn_cmd_data *)cmd->data; 2951 /* NB: No need to clear tx, all fields are reinitialized here. */ 2952 tx->scratch = 0; /* clear "scratch" area */ 2953 2954 flags = 0; 2955 if (!IEEE80211_IS_MULTICAST(wh->i_addr1)) 2956 flags |= IWN_TX_NEED_ACK; 2957 if ((wh->i_fc[0] & 2958 (IEEE80211_FC0_TYPE_MASK | IEEE80211_FC0_SUBTYPE_MASK)) == 2959 (IEEE80211_FC0_TYPE_CTL | IEEE80211_FC0_SUBTYPE_BAR)) 2960 flags |= IWN_TX_IMM_BA; /* Cannot happen yet. */ 2961 2962 if (wh->i_fc[1] & IEEE80211_FC1_MORE_FRAG) 2963 flags |= IWN_TX_MORE_FRAG; /* Cannot happen yet. */ 2964 2965 /* Check if frame must be protected using RTS/CTS or CTS-to-self. */ 2966 if (!IEEE80211_IS_MULTICAST(wh->i_addr1)) { 2967 /* NB: Group frames are sent using CCK in 802.11b/g. */ 2968 if (totlen + IEEE80211_CRC_LEN > vap->iv_rtsthreshold) { 2969 flags |= IWN_TX_NEED_RTS; 2970 } else if ((ic->ic_flags & IEEE80211_F_USEPROT) && 2971 ridx >= IWN_RIDX_OFDM6) { 2972 if (ic->ic_protmode == IEEE80211_PROT_CTSONLY) 2973 flags |= IWN_TX_NEED_CTS; 2974 else if (ic->ic_protmode == IEEE80211_PROT_RTSCTS) 2975 flags |= IWN_TX_NEED_RTS; 2976 } 2977 if (flags & (IWN_TX_NEED_RTS | IWN_TX_NEED_CTS)) { 2978 if (sc->hw_type != IWN_HW_REV_TYPE_4965) { 2979 /* 5000 autoselects RTS/CTS or CTS-to-self. */ 2980 flags &= ~(IWN_TX_NEED_RTS | IWN_TX_NEED_CTS); 2981 flags |= IWN_TX_NEED_PROTECTION; 2982 } else 2983 flags |= IWN_TX_FULL_TXOP; 2984 } 2985 } 2986 2987 if (IEEE80211_IS_MULTICAST(wh->i_addr1) || 2988 type != IEEE80211_FC0_TYPE_DATA) 2989 tx->id = hal->broadcast_id; 2990 else 2991 tx->id = wn->id; 2992 2993 if (type == IEEE80211_FC0_TYPE_MGT) { 2994 uint8_t subtype = wh->i_fc[0] & IEEE80211_FC0_SUBTYPE_MASK; 2995 2996 /* Tell HW to set timestamp in probe responses. */ 2997 if (subtype == IEEE80211_FC0_SUBTYPE_PROBE_RESP) 2998 flags |= IWN_TX_INSERT_TSTAMP; 2999 3000 if (subtype == IEEE80211_FC0_SUBTYPE_ASSOC_REQ || 3001 subtype == IEEE80211_FC0_SUBTYPE_REASSOC_REQ) 3002 tx->timeout = htole16(3); 3003 else 3004 tx->timeout = htole16(2); 3005 } else 3006 tx->timeout = htole16(0); 3007 3008 if (hdrlen & 3) { 3009 /* First segment length must be a multiple of 4. */ 3010 flags |= IWN_TX_NEED_PADDING; 3011 pad = 4 - (hdrlen & 3); 3012 } else 3013 pad = 0; 3014 3015 tx->len = htole16(totlen); 3016 tx->tid = 0; 3017 tx->rts_ntries = 60; 3018 tx->data_ntries = 15; 3019 tx->lifetime = htole32(IWN_LIFETIME_INFINITE); 3020 tx->plcp = rinfo->plcp; 3021 tx->rflags = rinfo->flags; 3022 if (tx->id == hal->broadcast_id) { 3023 /* Group or management frame. */ 3024 tx->linkq = 0; 3025 /* XXX Alternate between antenna A and B? */ 3026 txant = IWN_LSB(sc->txchainmask); 3027 tx->rflags |= IWN_RFLAG_ANT(txant); 3028 } else { 3029 tx->linkq = IWN_RIDX_OFDM54 - ridx; 3030 flags |= IWN_TX_LINKQ; /* enable MRR */ 3031 } 3032 3033 /* Set physical address of "scratch area". */ 3034 tx->loaddr = htole32(IWN_LOADDR(data->scratch_paddr)); 3035 tx->hiaddr = IWN_HIADDR(data->scratch_paddr); 3036 3037 /* Copy 802.11 header in TX command. */ 3038 memcpy((uint8_t *)(tx + 1), wh, hdrlen); 3039 3040 /* Trim 802.11 header. */ 3041 m_adj(m, hdrlen); 3042 tx->security = 0; 3043 tx->flags = htole32(flags); 3044 3045 if (m->m_len > 0) { 3046 error = bus_dmamap_load_mbuf_sg(ring->data_dmat, data->map, 3047 m, segs, &nsegs, BUS_DMA_NOWAIT); 3048 if (error == EFBIG) { 3049 /* too many fragments, linearize */ 3050 mnew = m_collapse(m, M_DONTWAIT, IWN_MAX_SCATTER); 3051 if (mnew == NULL) { 3052 device_printf(sc->sc_dev, 3053 "%s: could not defrag mbuf\n", __func__); 3054 m_freem(m); 3055 return ENOBUFS; 3056 } 3057 m = mnew; 3058 error = bus_dmamap_load_mbuf_sg(ring->data_dmat, 3059 data->map, m, segs, &nsegs, BUS_DMA_NOWAIT); 3060 } 3061 if (error != 0) { 3062 device_printf(sc->sc_dev, 3063 "%s: bus_dmamap_load_mbuf_sg failed, error %d\n", 3064 __func__, error); 3065 m_freem(m); 3066 return error; 3067 } 3068 } 3069 3070 data->m = m; 3071 data->ni = ni; 3072 3073 DPRINTF(sc, IWN_DEBUG_XMIT, "%s: qid %d idx %d len %d nsegs %d\n", 3074 __func__, ring->qid, ring->cur, m->m_pkthdr.len, nsegs); 3075 3076 /* Fill TX descriptor. */ 3077 desc->nsegs = 1 + nsegs; 3078 /* First DMA segment is used by the TX command. */ 3079 desc->segs[0].addr = htole32(IWN_LOADDR(data->cmd_paddr)); 3080 desc->segs[0].len = htole16(IWN_HIADDR(data->cmd_paddr) | 3081 (4 + sizeof (*tx) + hdrlen + pad) << 4); 3082 /* Other DMA segments are for data payload. */ 3083 for (i = 1; i <= nsegs; i++) { 3084 desc->segs[i].addr = htole32(IWN_LOADDR(segs[i - 1].ds_addr)); 3085 desc->segs[i].len = htole16(IWN_HIADDR(segs[i - 1].ds_addr) | 3086 segs[i - 1].ds_len << 4); 3087 } 3088 3089 bus_dmamap_sync(ring->data_dmat, data->map, BUS_DMASYNC_PREWRITE); 3090 bus_dmamap_sync(ring->data_dmat, ring->cmd_dma.map, 3091 BUS_DMASYNC_PREWRITE); 3092 bus_dmamap_sync(ring->desc_dma.tag, ring->desc_dma.map, 3093 BUS_DMASYNC_PREWRITE); 3094 3095 #ifdef notyet 3096 /* Update TX scheduler. */ 3097 hal->update_sched(sc, ring->qid, ring->cur, tx->id, totlen); 3098 #endif 3099 3100 /* Kick TX ring. */ 3101 ring->cur = (ring->cur + 1) % IWN_TX_RING_COUNT; 3102 IWN_WRITE(sc, IWN_HBUS_TARG_WRPTR, ring->qid << 8 | ring->cur); 3103 3104 /* Mark TX ring as full if we reach a certain threshold. */ 3105 if (++ring->queued > IWN_TX_RING_HIMARK) 3106 sc->qfullmsk |= 1 << ring->qid; 3107 3108 return 0; 3109 } 3110 3111 static int 3112 iwn_tx_data_raw(struct iwn_softc *sc, struct mbuf *m, 3113 struct ieee80211_node *ni, struct iwn_tx_ring *ring, 3114 const struct ieee80211_bpf_params *params) 3115 { 3116 const struct iwn_hal *hal = sc->sc_hal; 3117 const struct iwn_rate *rinfo; 3118 struct ifnet *ifp = sc->sc_ifp; 3119 struct ieee80211vap *vap = ni->ni_vap; 3120 struct ieee80211com *ic = ifp->if_l2com; 3121 struct iwn_tx_cmd *cmd; 3122 struct iwn_cmd_data *tx; 3123 struct ieee80211_frame *wh; 3124 struct iwn_tx_desc *desc; 3125 struct iwn_tx_data *data; 3126 struct mbuf *mnew; 3127 bus_addr_t paddr; 3128 bus_dma_segment_t segs[IWN_MAX_SCATTER]; 3129 uint32_t flags; 3130 u_int hdrlen; 3131 int totlen, error, pad, nsegs = 0, i, rate; 3132 uint8_t ridx, type, txant; 3133 3134 IWN_LOCK_ASSERT(sc); 3135 3136 wh = mtod(m, struct ieee80211_frame *); 3137 hdrlen = ieee80211_anyhdrsize(wh); 3138 type = wh->i_fc[0] & IEEE80211_FC0_TYPE_MASK; 3139 3140 desc = &ring->desc[ring->cur]; 3141 data = &ring->data[ring->cur]; 3142 3143 /* Choose a TX rate index. */ 3144 rate = params->ibp_rate0; 3145 if (!ieee80211_isratevalid(ic->ic_rt, rate)) { 3146 /* XXX fall back to mcast/mgmt rate? */ 3147 m_freem(m); 3148 return EINVAL; 3149 } 3150 ridx = iwn_plcp_signal(rate); 3151 rinfo = &iwn_rates[ridx]; 3152 3153 totlen = m->m_pkthdr.len; 3154 3155 /* Prepare TX firmware command. */ 3156 cmd = &ring->cmd[ring->cur]; 3157 cmd->code = IWN_CMD_TX_DATA; 3158 cmd->flags = 0; 3159 cmd->qid = ring->qid; 3160 cmd->idx = ring->cur; 3161 3162 tx = (struct iwn_cmd_data *)cmd->data; 3163 /* NB: No need to clear tx, all fields are reinitialized here. */ 3164 tx->scratch = 0; /* clear "scratch" area */ 3165 3166 flags = 0; 3167 if ((params->ibp_flags & IEEE80211_BPF_NOACK) == 0) 3168 flags |= IWN_TX_NEED_ACK; 3169 if (params->ibp_flags & IEEE80211_BPF_RTS) { 3170 if (sc->hw_type != IWN_HW_REV_TYPE_4965) { 3171 /* 5000 autoselects RTS/CTS or CTS-to-self. */ 3172 flags &= ~IWN_TX_NEED_RTS; 3173 flags |= IWN_TX_NEED_PROTECTION; 3174 } else 3175 flags |= IWN_TX_NEED_RTS | IWN_TX_FULL_TXOP; 3176 } 3177 if (params->ibp_flags & IEEE80211_BPF_CTS) { 3178 if (sc->hw_type != IWN_HW_REV_TYPE_4965) { 3179 /* 5000 autoselects RTS/CTS or CTS-to-self. */ 3180 flags &= ~IWN_TX_NEED_CTS; 3181 flags |= IWN_TX_NEED_PROTECTION; 3182 } else 3183 flags |= IWN_TX_NEED_CTS | IWN_TX_FULL_TXOP; 3184 } 3185 if (type == IEEE80211_FC0_TYPE_MGT) { 3186 uint8_t subtype = wh->i_fc[0] & IEEE80211_FC0_SUBTYPE_MASK; 3187 3188 if (subtype == IEEE80211_FC0_SUBTYPE_PROBE_RESP) 3189 flags |= IWN_TX_INSERT_TSTAMP; 3190 3191 if (subtype == IEEE80211_FC0_SUBTYPE_ASSOC_REQ || 3192 subtype == IEEE80211_FC0_SUBTYPE_REASSOC_REQ) 3193 tx->timeout = htole16(3); 3194 else 3195 tx->timeout = htole16(2); 3196 } else 3197 tx->timeout = htole16(0); 3198 3199 if (hdrlen & 3) { 3200 /* First segment length must be a multiple of 4. */ 3201 flags |= IWN_TX_NEED_PADDING; 3202 pad = 4 - (hdrlen & 3); 3203 } else 3204 pad = 0; 3205 3206 if (ieee80211_radiotap_active_vap(vap)) { 3207 struct iwn_tx_radiotap_header *tap = &sc->sc_txtap; 3208 3209 tap->wt_flags = 0; 3210 tap->wt_rate = rate; 3211 3212 ieee80211_radiotap_tx(vap, m); 3213 } 3214 3215 tx->len = htole16(totlen); 3216 tx->tid = 0; 3217 tx->id = hal->broadcast_id; 3218 tx->rts_ntries = params->ibp_try1; 3219 tx->data_ntries = params->ibp_try0; 3220 tx->lifetime = htole32(IWN_LIFETIME_INFINITE); 3221 tx->plcp = rinfo->plcp; 3222 tx->rflags = rinfo->flags; 3223 /* Group or management frame. */ 3224 tx->linkq = 0; 3225 txant = IWN_LSB(sc->txchainmask); 3226 tx->rflags |= IWN_RFLAG_ANT(txant); 3227 /* Set physical address of "scratch area". */ 3228 paddr = ring->cmd_dma.paddr + ring->cur * sizeof (struct iwn_tx_cmd); 3229 tx->loaddr = htole32(IWN_LOADDR(paddr)); 3230 tx->hiaddr = IWN_HIADDR(paddr); 3231 3232 /* Copy 802.11 header in TX command. */ 3233 memcpy((uint8_t *)(tx + 1), wh, hdrlen); 3234 3235 /* Trim 802.11 header. */ 3236 m_adj(m, hdrlen); 3237 tx->security = 0; 3238 tx->flags = htole32(flags); 3239 3240 if (m->m_len > 0) { 3241 error = bus_dmamap_load_mbuf_sg(ring->data_dmat, data->map, 3242 m, segs, &nsegs, BUS_DMA_NOWAIT); 3243 if (error == EFBIG) { 3244 /* Too many fragments, linearize. */ 3245 mnew = m_collapse(m, M_DONTWAIT, IWN_MAX_SCATTER); 3246 if (mnew == NULL) { 3247 device_printf(sc->sc_dev, 3248 "%s: could not defrag mbuf\n", __func__); 3249 m_freem(m); 3250 return ENOBUFS; 3251 } 3252 m = mnew; 3253 error = bus_dmamap_load_mbuf_sg(ring->data_dmat, 3254 data->map, m, segs, &nsegs, BUS_DMA_NOWAIT); 3255 } 3256 if (error != 0) { 3257 device_printf(sc->sc_dev, 3258 "%s: bus_dmamap_load_mbuf_sg failed, error %d\n", 3259 __func__, error); 3260 m_freem(m); 3261 return error; 3262 } 3263 } 3264 3265 data->m = m; 3266 data->ni = ni; 3267 3268 DPRINTF(sc, IWN_DEBUG_XMIT, "%s: qid %d idx %d len %d nsegs %d\n", 3269 __func__, ring->qid, ring->cur, m->m_pkthdr.len, nsegs); 3270 3271 /* Fill TX descriptor. */ 3272 desc->nsegs = 1 + nsegs; 3273 /* First DMA segment is used by the TX command. */ 3274 desc->segs[0].addr = htole32(IWN_LOADDR(data->cmd_paddr)); 3275 desc->segs[0].len = htole16(IWN_HIADDR(data->cmd_paddr) | 3276 (4 + sizeof (*tx) + hdrlen + pad) << 4); 3277 /* Other DMA segments are for data payload. */ 3278 for (i = 1; i <= nsegs; i++) { 3279 desc->segs[i].addr = htole32(IWN_LOADDR(segs[i - 1].ds_addr)); 3280 desc->segs[i].len = htole16(IWN_HIADDR(segs[i - 1].ds_addr) | 3281 segs[i - 1].ds_len << 4); 3282 } 3283 3284 bus_dmamap_sync(ring->data_dmat, data->map, BUS_DMASYNC_PREWRITE); 3285 bus_dmamap_sync(ring->data_dmat, ring->cmd_dma.map, 3286 BUS_DMASYNC_PREWRITE); 3287 bus_dmamap_sync(ring->desc_dma.tag, ring->desc_dma.map, 3288 BUS_DMASYNC_PREWRITE); 3289 3290 #ifdef notyet 3291 /* Update TX scheduler. */ 3292 hal->update_sched(sc, ring->qid, ring->cur, tx->id, totlen); 3293 #endif 3294 3295 /* Kick TX ring. */ 3296 ring->cur = (ring->cur + 1) % IWN_TX_RING_COUNT; 3297 IWN_WRITE(sc, IWN_HBUS_TARG_WRPTR, ring->qid << 8 | ring->cur); 3298 3299 /* Mark TX ring as full if we reach a certain threshold. */ 3300 if (++ring->queued > IWN_TX_RING_HIMARK) 3301 sc->qfullmsk |= 1 << ring->qid; 3302 3303 return 0; 3304 } 3305 3306 static int 3307 iwn_raw_xmit(struct ieee80211_node *ni, struct mbuf *m, 3308 const struct ieee80211_bpf_params *params) 3309 { 3310 struct ieee80211com *ic = ni->ni_ic; 3311 struct ifnet *ifp = ic->ic_ifp; 3312 struct iwn_softc *sc = ifp->if_softc; 3313 struct iwn_tx_ring *txq; 3314 int error = 0; 3315 3316 if ((ifp->if_drv_flags & IFF_DRV_RUNNING) == 0) { 3317 ieee80211_free_node(ni); 3318 m_freem(m); 3319 return ENETDOWN; 3320 } 3321 3322 IWN_LOCK(sc); 3323 if (params == NULL) 3324 txq = &sc->txq[M_WME_GETAC(m)]; 3325 else 3326 txq = &sc->txq[params->ibp_pri & 3]; 3327 3328 if (params == NULL) { 3329 /* 3330 * Legacy path; interpret frame contents to decide 3331 * precisely how to send the frame. 3332 */ 3333 error = iwn_tx_data(sc, m, ni, txq); 3334 } else { 3335 /* 3336 * Caller supplied explicit parameters to use in 3337 * sending the frame. 3338 */ 3339 error = iwn_tx_data_raw(sc, m, ni, txq, params); 3340 } 3341 if (error != 0) { 3342 /* NB: m is reclaimed on tx failure */ 3343 ieee80211_free_node(ni); 3344 ifp->if_oerrors++; 3345 } 3346 IWN_UNLOCK(sc); 3347 return error; 3348 } 3349 3350 static void 3351 iwn_start(struct ifnet *ifp) 3352 { 3353 struct iwn_softc *sc = ifp->if_softc; 3354 3355 IWN_LOCK(sc); 3356 iwn_start_locked(ifp); 3357 IWN_UNLOCK(sc); 3358 } 3359 3360 static void 3361 iwn_start_locked(struct ifnet *ifp) 3362 { 3363 struct iwn_softc *sc = ifp->if_softc; 3364 struct ieee80211_node *ni; 3365 struct iwn_tx_ring *txq; 3366 struct mbuf *m; 3367 int pri; 3368 3369 IWN_LOCK_ASSERT(sc); 3370 3371 for (;;) { 3372 if (sc->qfullmsk != 0) { 3373 ifp->if_drv_flags |= IFF_DRV_OACTIVE; 3374 break; 3375 } 3376 IFQ_DRV_DEQUEUE(&ifp->if_snd, m); 3377 if (m == NULL) 3378 break; 3379 ni = (struct ieee80211_node *)m->m_pkthdr.rcvif; 3380 pri = M_WME_GETAC(m); 3381 txq = &sc->txq[pri]; 3382 if (iwn_tx_data(sc, m, ni, txq) != 0) { 3383 ifp->if_oerrors++; 3384 ieee80211_free_node(ni); 3385 break; 3386 } 3387 sc->sc_tx_timer = 5; 3388 } 3389 } 3390 3391 static void 3392 iwn_watchdog(struct iwn_softc *sc) 3393 { 3394 if (sc->sc_tx_timer > 0 && --sc->sc_tx_timer == 0) { 3395 struct ifnet *ifp = sc->sc_ifp; 3396 struct ieee80211com *ic = ifp->if_l2com; 3397 3398 if_printf(ifp, "device timeout\n"); 3399 ieee80211_runtask(ic, &sc->sc_reinit_task); 3400 } 3401 } 3402 3403 static int 3404 iwn_ioctl(struct ifnet *ifp, u_long cmd, caddr_t data) 3405 { 3406 struct iwn_softc *sc = ifp->if_softc; 3407 struct ieee80211com *ic = ifp->if_l2com; 3408 struct ieee80211vap *vap = TAILQ_FIRST(&ic->ic_vaps); 3409 struct ifreq *ifr = (struct ifreq *) data; 3410 int error = 0, startall = 0, stop = 0; 3411 3412 switch (cmd) { 3413 case SIOCSIFFLAGS: 3414 IWN_LOCK(sc); 3415 if (ifp->if_flags & IFF_UP) { 3416 if (!(ifp->if_drv_flags & IFF_DRV_RUNNING)) { 3417 iwn_init_locked(sc); 3418 if (IWN_READ(sc, IWN_GP_CNTRL) & IWN_GP_CNTRL_RFKILL) 3419 startall = 1; 3420 else 3421 stop = 1; 3422 } 3423 } else { 3424 if (ifp->if_drv_flags & IFF_DRV_RUNNING) 3425 iwn_stop_locked(sc); 3426 } 3427 IWN_UNLOCK(sc); 3428 if (startall) 3429 ieee80211_start_all(ic); 3430 else if (vap != NULL && stop) 3431 ieee80211_stop(vap); 3432 break; 3433 case SIOCGIFMEDIA: 3434 error = ifmedia_ioctl(ifp, ifr, &ic->ic_media, cmd); 3435 break; 3436 case SIOCGIFADDR: 3437 error = ether_ioctl(ifp, cmd, data); 3438 break; 3439 default: 3440 error = EINVAL; 3441 break; 3442 } 3443 return error; 3444 } 3445 3446 /* 3447 * Send a command to the firmware. 3448 */ 3449 static int 3450 iwn_cmd(struct iwn_softc *sc, int code, const void *buf, int size, int async) 3451 { 3452 struct iwn_tx_ring *ring = &sc->txq[4]; 3453 struct iwn_tx_desc *desc; 3454 struct iwn_tx_data *data; 3455 struct iwn_tx_cmd *cmd; 3456 struct mbuf *m; 3457 bus_addr_t paddr; 3458 int totlen, error; 3459 3460 IWN_LOCK_ASSERT(sc); 3461 3462 desc = &ring->desc[ring->cur]; 3463 data = &ring->data[ring->cur]; 3464 totlen = 4 + size; 3465 3466 if (size > sizeof cmd->data) { 3467 /* Command is too large to fit in a descriptor. */ 3468 if (totlen > MCLBYTES) 3469 return EINVAL; 3470 m = m_getjcl(M_DONTWAIT, MT_DATA, M_PKTHDR, MJUMPAGESIZE); 3471 if (m == NULL) 3472 return ENOMEM; 3473 cmd = mtod(m, struct iwn_tx_cmd *); 3474 error = bus_dmamap_load(ring->data_dmat, data->map, cmd, 3475 totlen, iwn_dma_map_addr, &paddr, BUS_DMA_NOWAIT); 3476 if (error != 0) { 3477 m_freem(m); 3478 return error; 3479 } 3480 data->m = m; 3481 } else { 3482 cmd = &ring->cmd[ring->cur]; 3483 paddr = data->cmd_paddr; 3484 } 3485 3486 cmd->code = code; 3487 cmd->flags = 0; 3488 cmd->qid = ring->qid; 3489 cmd->idx = ring->cur; 3490 memcpy(cmd->data, buf, size); 3491 3492 desc->nsegs = 1; 3493 desc->segs[0].addr = htole32(IWN_LOADDR(paddr)); 3494 desc->segs[0].len = htole16(IWN_HIADDR(paddr) | totlen << 4); 3495 3496 DPRINTF(sc, IWN_DEBUG_CMD, "%s: %s (0x%x) flags %d qid %d idx %d\n", 3497 __func__, iwn_intr_str(cmd->code), cmd->code, 3498 cmd->flags, cmd->qid, cmd->idx); 3499 3500 if (size > sizeof cmd->data) { 3501 bus_dmamap_sync(ring->data_dmat, data->map, 3502 BUS_DMASYNC_PREWRITE); 3503 } else { 3504 bus_dmamap_sync(ring->data_dmat, ring->cmd_dma.map, 3505 BUS_DMASYNC_PREWRITE); 3506 } 3507 bus_dmamap_sync(ring->desc_dma.tag, ring->desc_dma.map, 3508 BUS_DMASYNC_PREWRITE); 3509 3510 #ifdef notyet 3511 /* Update TX scheduler. */ 3512 sc->sc_hal->update_sched(sc, ring->qid, ring->cur, 0, 0); 3513 #endif 3514 3515 /* Kick command ring. */ 3516 ring->cur = (ring->cur + 1) % IWN_TX_RING_COUNT; 3517 IWN_WRITE(sc, IWN_HBUS_TARG_WRPTR, ring->qid << 8 | ring->cur); 3518 3519 return async ? 0 : msleep(desc, &sc->sc_mtx, PCATCH, "iwncmd", hz); 3520 } 3521 3522 static int 3523 iwn4965_add_node(struct iwn_softc *sc, struct iwn_node_info *node, int async) 3524 { 3525 struct iwn4965_node_info hnode; 3526 caddr_t src, dst; 3527 3528 /* 3529 * We use the node structure for 5000 Series internally (it is 3530 * a superset of the one for 4965AGN). We thus copy the common 3531 * fields before sending the command. 3532 */ 3533 src = (caddr_t)node; 3534 dst = (caddr_t)&hnode; 3535 memcpy(dst, src, 48); 3536 /* Skip TSC, RX MIC and TX MIC fields from ``src''. */ 3537 memcpy(dst + 48, src + 72, 20); 3538 return iwn_cmd(sc, IWN_CMD_ADD_NODE, &hnode, sizeof hnode, async); 3539 } 3540 3541 static int 3542 iwn5000_add_node(struct iwn_softc *sc, struct iwn_node_info *node, int async) 3543 { 3544 /* Direct mapping. */ 3545 return iwn_cmd(sc, IWN_CMD_ADD_NODE, node, sizeof (*node), async); 3546 } 3547 3548 #if 0 /* HT */ 3549 static const uint8_t iwn_ridx_to_plcp[] = { 3550 10, 20, 55, 110, /* CCK */ 3551 0xd, 0xf, 0x5, 0x7, 0x9, 0xb, 0x1, 0x3, 0x3 /* OFDM R1-R4 */ 3552 }; 3553 static const uint8_t iwn_siso_mcs_to_plcp[] = { 3554 0, 0, 0, 0, /* CCK */ 3555 0, 0, 1, 2, 3, 4, 5, 6, 7 /* HT */ 3556 }; 3557 static const uint8_t iwn_mimo_mcs_to_plcp[] = { 3558 0, 0, 0, 0, /* CCK */ 3559 8, 8, 9, 10, 11, 12, 13, 14, 15 /* HT */ 3560 }; 3561 #endif 3562 static const uint8_t iwn_prev_ridx[] = { 3563 /* NB: allow fallback from CCK11 to OFDM9 and from OFDM6 to CCK5 */ 3564 0, 0, 1, 5, /* CCK */ 3565 2, 4, 3, 6, 7, 8, 9, 10, 10 /* OFDM */ 3566 }; 3567 3568 /* 3569 * Configure hardware link parameters for the specified 3570 * node operating on the specified channel. 3571 */ 3572 static int 3573 iwn_set_link_quality(struct iwn_softc *sc, uint8_t id, int async) 3574 { 3575 struct ifnet *ifp = sc->sc_ifp; 3576 struct ieee80211com *ic = ifp->if_l2com; 3577 struct iwn_cmd_link_quality linkq; 3578 const struct iwn_rate *rinfo; 3579 int i; 3580 uint8_t txant, ridx; 3581 3582 /* Use the first valid TX antenna. */ 3583 txant = IWN_LSB(sc->txchainmask); 3584 3585 memset(&linkq, 0, sizeof linkq); 3586 linkq.id = id; 3587 linkq.antmsk_1stream = txant; 3588 linkq.antmsk_2stream = IWN_ANT_AB; 3589 linkq.ampdu_max = 31; 3590 linkq.ampdu_threshold = 3; 3591 linkq.ampdu_limit = htole16(4000); /* 4ms */ 3592 3593 #if 0 /* HT */ 3594 if (IEEE80211_IS_CHAN_HT(c)) 3595 linkq.mimo = 1; 3596 #endif 3597 3598 if (id == IWN_ID_BSS) 3599 ridx = IWN_RIDX_OFDM54; 3600 else if (IEEE80211_IS_CHAN_A(ic->ic_curchan)) 3601 ridx = IWN_RIDX_OFDM6; 3602 else 3603 ridx = IWN_RIDX_CCK1; 3604 3605 for (i = 0; i < IWN_MAX_TX_RETRIES; i++) { 3606 rinfo = &iwn_rates[ridx]; 3607 #if 0 /* HT */ 3608 if (IEEE80211_IS_CHAN_HT40(c)) { 3609 linkq.retry[i].plcp = iwn_mimo_mcs_to_plcp[ridx] 3610 | IWN_RIDX_MCS; 3611 linkq.retry[i].rflags = IWN_RFLAG_HT 3612 | IWN_RFLAG_HT40; 3613 /* XXX shortGI */ 3614 } else if (IEEE80211_IS_CHAN_HT(c)) { 3615 linkq.retry[i].plcp = iwn_siso_mcs_to_plcp[ridx] 3616 | IWN_RIDX_MCS; 3617 linkq.retry[i].rflags = IWN_RFLAG_HT; 3618 /* XXX shortGI */ 3619 } else 3620 #endif 3621 { 3622 linkq.retry[i].plcp = rinfo->plcp; 3623 linkq.retry[i].rflags = rinfo->flags; 3624 } 3625 linkq.retry[i].rflags |= IWN_RFLAG_ANT(txant); 3626 ridx = iwn_prev_ridx[ridx]; 3627 } 3628 #ifdef IWN_DEBUG 3629 if (sc->sc_debug & IWN_DEBUG_STATE) { 3630 printf("%s: set link quality for node %d, mimo %d ssmask %d\n", 3631 __func__, id, linkq.mimo, linkq.antmsk_1stream); 3632 printf("%s:", __func__); 3633 for (i = 0; i < IWN_MAX_TX_RETRIES; i++) 3634 printf(" %d:%x", linkq.retry[i].plcp, 3635 linkq.retry[i].rflags); 3636 printf("\n"); 3637 } 3638 #endif 3639 return iwn_cmd(sc, IWN_CMD_LINK_QUALITY, &linkq, sizeof linkq, async); 3640 } 3641 3642 /* 3643 * Broadcast node is used to send group-addressed and management frames. 3644 */ 3645 static int 3646 iwn_add_broadcast_node(struct iwn_softc *sc, int async) 3647 { 3648 const struct iwn_hal *hal = sc->sc_hal; 3649 struct ifnet *ifp = sc->sc_ifp; 3650 struct iwn_node_info node; 3651 int error; 3652 3653 memset(&node, 0, sizeof node); 3654 IEEE80211_ADDR_COPY(node.macaddr, ifp->if_broadcastaddr); 3655 node.id = hal->broadcast_id; 3656 DPRINTF(sc, IWN_DEBUG_RESET, "%s: adding broadcast node\n", __func__); 3657 error = hal->add_node(sc, &node, async); 3658 if (error != 0) 3659 return error; 3660 3661 error = iwn_set_link_quality(sc, hal->broadcast_id, async); 3662 return error; 3663 } 3664 3665 static int 3666 iwn_wme_update(struct ieee80211com *ic) 3667 { 3668 #define IWN_EXP2(x) ((1 << (x)) - 1) /* CWmin = 2^ECWmin - 1 */ 3669 #define IWN_TXOP_TO_US(v) (v<<5) 3670 struct iwn_softc *sc = ic->ic_ifp->if_softc; 3671 struct iwn_edca_params cmd; 3672 int i; 3673 3674 memset(&cmd, 0, sizeof cmd); 3675 cmd.flags = htole32(IWN_EDCA_UPDATE); 3676 for (i = 0; i < WME_NUM_AC; i++) { 3677 const struct wmeParams *wmep = 3678 &ic->ic_wme.wme_chanParams.cap_wmeParams[i]; 3679 cmd.ac[i].aifsn = wmep->wmep_aifsn; 3680 cmd.ac[i].cwmin = htole16(IWN_EXP2(wmep->wmep_logcwmin)); 3681 cmd.ac[i].cwmax = htole16(IWN_EXP2(wmep->wmep_logcwmax)); 3682 cmd.ac[i].txoplimit = 3683 htole16(IWN_TXOP_TO_US(wmep->wmep_txopLimit)); 3684 } 3685 IEEE80211_UNLOCK(ic); 3686 IWN_LOCK(sc); 3687 (void) iwn_cmd(sc, IWN_CMD_EDCA_PARAMS, &cmd, sizeof cmd, 1 /*async*/); 3688 IWN_UNLOCK(sc); 3689 IEEE80211_LOCK(ic); 3690 return 0; 3691 #undef IWN_TXOP_TO_US 3692 #undef IWN_EXP2 3693 } 3694 3695 static void 3696 iwn_update_mcast(struct ifnet *ifp) 3697 { 3698 /* Ignore */ 3699 } 3700 3701 static void 3702 iwn_set_led(struct iwn_softc *sc, uint8_t which, uint8_t off, uint8_t on) 3703 { 3704 struct iwn_cmd_led led; 3705 3706 /* Clear microcode LED ownership. */ 3707 IWN_CLRBITS(sc, IWN_LED, IWN_LED_BSM_CTRL); 3708 3709 led.which = which; 3710 led.unit = htole32(10000); /* on/off in unit of 100ms */ 3711 led.off = off; 3712 led.on = on; 3713 (void)iwn_cmd(sc, IWN_CMD_SET_LED, &led, sizeof led, 1); 3714 } 3715 3716 /* 3717 * Set the critical temperature at which the firmware will stop the radio 3718 * and notify us. 3719 */ 3720 static int 3721 iwn_set_critical_temp(struct iwn_softc *sc) 3722 { 3723 struct iwn_critical_temp crit; 3724 int32_t temp; 3725 3726 IWN_WRITE(sc, IWN_UCODE_GP1_CLR, IWN_UCODE_GP1_CTEMP_STOP_RF); 3727 3728 if (sc->hw_type == IWN_HW_REV_TYPE_5150) 3729 temp = (IWN_CTOK(110) - sc->temp_off) * -5; 3730 else if (sc->hw_type == IWN_HW_REV_TYPE_4965) 3731 temp = IWN_CTOK(110); 3732 else 3733 temp = 110; 3734 memset(&crit, 0, sizeof crit); 3735 crit.tempR = htole32(temp); 3736 DPRINTF(sc, IWN_DEBUG_RESET, "setting critical temp to %d\n", 3737 temp); 3738 return iwn_cmd(sc, IWN_CMD_SET_CRITICAL_TEMP, &crit, sizeof crit, 0); 3739 } 3740 3741 static int 3742 iwn_set_timing(struct iwn_softc *sc, struct ieee80211_node *ni) 3743 { 3744 struct iwn_cmd_timing cmd; 3745 uint64_t val, mod; 3746 3747 memset(&cmd, 0, sizeof cmd); 3748 memcpy(&cmd.tstamp, ni->ni_tstamp.data, sizeof (uint64_t)); 3749 cmd.bintval = htole16(ni->ni_intval); 3750 cmd.lintval = htole16(10); 3751 3752 /* Compute remaining time until next beacon. */ 3753 val = (uint64_t)ni->ni_intval * 1024; /* msecs -> usecs */ 3754 mod = le64toh(cmd.tstamp) % val; 3755 cmd.binitval = htole32((uint32_t)(val - mod)); 3756 3757 DPRINTF(sc, IWN_DEBUG_RESET, "timing bintval=%u tstamp=%ju, init=%u\n", 3758 ni->ni_intval, le64toh(cmd.tstamp), (uint32_t)(val - mod)); 3759 3760 return iwn_cmd(sc, IWN_CMD_TIMING, &cmd, sizeof cmd, 1); 3761 } 3762 3763 static void 3764 iwn4965_power_calibration(struct iwn_softc *sc, int temp) 3765 { 3766 struct ifnet *ifp = sc->sc_ifp; 3767 struct ieee80211com *ic = ifp->if_l2com; 3768 3769 /* Adjust TX power if need be (delta >= 3 degC.) */ 3770 DPRINTF(sc, IWN_DEBUG_CALIBRATE, "%s: temperature %d->%d\n", 3771 __func__, sc->temp, temp); 3772 if (abs(temp - sc->temp) >= 3) { 3773 /* Record temperature of last calibration. */ 3774 sc->temp = temp; 3775 (void)iwn4965_set_txpower(sc, ic->ic_bsschan, 1); 3776 } 3777 } 3778 3779 /* 3780 * Set TX power for current channel (each rate has its own power settings). 3781 * This function takes into account the regulatory information from EEPROM, 3782 * the current temperature and the current voltage. 3783 */ 3784 static int 3785 iwn4965_set_txpower(struct iwn_softc *sc, struct ieee80211_channel *ch, 3786 int async) 3787 { 3788 /* Fixed-point arithmetic division using a n-bit fractional part. */ 3789 #define fdivround(a, b, n) \ 3790 ((((1 << n) * (a)) / (b) + (1 << n) / 2) / (1 << n)) 3791 /* Linear interpolation. */ 3792 #define interpolate(x, x1, y1, x2, y2, n) \ 3793 ((y1) + fdivround(((int)(x) - (x1)) * ((y2) - (y1)), (x2) - (x1), n)) 3794 3795 static const int tdiv[IWN_NATTEN_GROUPS] = { 9, 8, 8, 8, 6 }; 3796 struct ifnet *ifp = sc->sc_ifp; 3797 struct ieee80211com *ic = ifp->if_l2com; 3798 struct iwn_ucode_info *uc = &sc->ucode_info; 3799 struct iwn4965_cmd_txpower cmd; 3800 struct iwn4965_eeprom_chan_samples *chans; 3801 int32_t vdiff, tdiff; 3802 int i, c, grp, maxpwr; 3803 const uint8_t *rf_gain, *dsp_gain; 3804 uint8_t chan; 3805 3806 /* Retrieve channel number. */ 3807 chan = ieee80211_chan2ieee(ic, ch); 3808 DPRINTF(sc, IWN_DEBUG_RESET, "setting TX power for channel %d\n", 3809 chan); 3810 3811 memset(&cmd, 0, sizeof cmd); 3812 cmd.band = IEEE80211_IS_CHAN_5GHZ(ch) ? 0 : 1; 3813 cmd.chan = chan; 3814 3815 if (IEEE80211_IS_CHAN_5GHZ(ch)) { 3816 maxpwr = sc->maxpwr5GHz; 3817 rf_gain = iwn4965_rf_gain_5ghz; 3818 dsp_gain = iwn4965_dsp_gain_5ghz; 3819 } else { 3820 maxpwr = sc->maxpwr2GHz; 3821 rf_gain = iwn4965_rf_gain_2ghz; 3822 dsp_gain = iwn4965_dsp_gain_2ghz; 3823 } 3824 3825 /* Compute voltage compensation. */ 3826 vdiff = ((int32_t)le32toh(uc->volt) - sc->eeprom_voltage) / 7; 3827 if (vdiff > 0) 3828 vdiff *= 2; 3829 if (abs(vdiff) > 2) 3830 vdiff = 0; 3831 DPRINTF(sc, IWN_DEBUG_CALIBRATE | IWN_DEBUG_TXPOW, 3832 "%s: voltage compensation=%d (UCODE=%d, EEPROM=%d)\n", 3833 __func__, vdiff, le32toh(uc->volt), sc->eeprom_voltage); 3834 3835 /* Get channel attenuation group. */ 3836 if (chan <= 20) /* 1-20 */ 3837 grp = 4; 3838 else if (chan <= 43) /* 34-43 */ 3839 grp = 0; 3840 else if (chan <= 70) /* 44-70 */ 3841 grp = 1; 3842 else if (chan <= 124) /* 71-124 */ 3843 grp = 2; 3844 else /* 125-200 */ 3845 grp = 3; 3846 DPRINTF(sc, IWN_DEBUG_CALIBRATE | IWN_DEBUG_TXPOW, 3847 "%s: chan %d, attenuation group=%d\n", __func__, chan, grp); 3848 3849 /* Get channel sub-band. */ 3850 for (i = 0; i < IWN_NBANDS; i++) 3851 if (sc->bands[i].lo != 0 && 3852 sc->bands[i].lo <= chan && chan <= sc->bands[i].hi) 3853 break; 3854 if (i == IWN_NBANDS) /* Can't happen in real-life. */ 3855 return EINVAL; 3856 chans = sc->bands[i].chans; 3857 DPRINTF(sc, IWN_DEBUG_CALIBRATE | IWN_DEBUG_TXPOW, 3858 "%s: chan %d sub-band=%d\n", __func__, chan, i); 3859 3860 for (c = 0; c < 2; c++) { 3861 uint8_t power, gain, temp; 3862 int maxchpwr, pwr, ridx, idx; 3863 3864 power = interpolate(chan, 3865 chans[0].num, chans[0].samples[c][1].power, 3866 chans[1].num, chans[1].samples[c][1].power, 1); 3867 gain = interpolate(chan, 3868 chans[0].num, chans[0].samples[c][1].gain, 3869 chans[1].num, chans[1].samples[c][1].gain, 1); 3870 temp = interpolate(chan, 3871 chans[0].num, chans[0].samples[c][1].temp, 3872 chans[1].num, chans[1].samples[c][1].temp, 1); 3873 DPRINTF(sc, IWN_DEBUG_CALIBRATE | IWN_DEBUG_TXPOW, 3874 "%s: Tx chain %d: power=%d gain=%d temp=%d\n", 3875 __func__, c, power, gain, temp); 3876 3877 /* Compute temperature compensation. */ 3878 tdiff = ((sc->temp - temp) * 2) / tdiv[grp]; 3879 DPRINTF(sc, IWN_DEBUG_CALIBRATE | IWN_DEBUG_TXPOW, 3880 "%s: temperature compensation=%d (current=%d, EEPROM=%d)\n", 3881 __func__, tdiff, sc->temp, temp); 3882 3883 for (ridx = 0; ridx <= IWN_RIDX_MAX; ridx++) { 3884 /* Convert dBm to half-dBm. */ 3885 maxchpwr = sc->maxpwr[chan] * 2; 3886 if ((ridx / 8) & 1) 3887 maxchpwr -= 6; /* MIMO 2T: -3dB */ 3888 3889 pwr = maxpwr; 3890 3891 /* Adjust TX power based on rate. */ 3892 if ((ridx % 8) == 5) 3893 pwr -= 15; /* OFDM48: -7.5dB */ 3894 else if ((ridx % 8) == 6) 3895 pwr -= 17; /* OFDM54: -8.5dB */ 3896 else if ((ridx % 8) == 7) 3897 pwr -= 20; /* OFDM60: -10dB */ 3898 else 3899 pwr -= 10; /* Others: -5dB */ 3900 3901 /* Do not exceed channel max TX power. */ 3902 if (pwr > maxchpwr) 3903 pwr = maxchpwr; 3904 3905 idx = gain - (pwr - power) - tdiff - vdiff; 3906 if ((ridx / 8) & 1) /* MIMO */ 3907 idx += (int32_t)le32toh(uc->atten[grp][c]); 3908 3909 if (cmd.band == 0) 3910 idx += 9; /* 5GHz */ 3911 if (ridx == IWN_RIDX_MAX) 3912 idx += 5; /* CCK */ 3913 3914 /* Make sure idx stays in a valid range. */ 3915 if (idx < 0) 3916 idx = 0; 3917 else if (idx > IWN4965_MAX_PWR_INDEX) 3918 idx = IWN4965_MAX_PWR_INDEX; 3919 3920 DPRINTF(sc, IWN_DEBUG_CALIBRATE | IWN_DEBUG_TXPOW, 3921 "%s: Tx chain %d, rate idx %d: power=%d\n", 3922 __func__, c, ridx, idx); 3923 cmd.power[ridx].rf_gain[c] = rf_gain[idx]; 3924 cmd.power[ridx].dsp_gain[c] = dsp_gain[idx]; 3925 } 3926 } 3927 3928 DPRINTF(sc, IWN_DEBUG_CALIBRATE | IWN_DEBUG_TXPOW, 3929 "%s: set tx power for chan %d\n", __func__, chan); 3930 return iwn_cmd(sc, IWN_CMD_TXPOWER, &cmd, sizeof cmd, async); 3931 3932 #undef interpolate 3933 #undef fdivround 3934 } 3935 3936 static int 3937 iwn5000_set_txpower(struct iwn_softc *sc, struct ieee80211_channel *ch, 3938 int async) 3939 { 3940 struct iwn5000_cmd_txpower cmd; 3941 3942 /* 3943 * TX power calibration is handled automatically by the firmware 3944 * for 5000 Series. 3945 */ 3946 memset(&cmd, 0, sizeof cmd); 3947 cmd.global_limit = 2 * IWN5000_TXPOWER_MAX_DBM; /* 16 dBm */ 3948 cmd.flags = IWN5000_TXPOWER_NO_CLOSED; 3949 cmd.srv_limit = IWN5000_TXPOWER_AUTO; 3950 DPRINTF(sc, IWN_DEBUG_CALIBRATE, "%s: setting TX power\n", __func__); 3951 return iwn_cmd(sc, IWN_CMD_TXPOWER_DBM, &cmd, sizeof cmd, async); 3952 } 3953 3954 /* 3955 * Retrieve the maximum RSSI (in dBm) among receivers. 3956 */ 3957 static int 3958 iwn4965_get_rssi(struct iwn_softc *sc, struct iwn_rx_stat *stat) 3959 { 3960 struct iwn4965_rx_phystat *phy = (void *)stat->phybuf; 3961 uint8_t mask, agc; 3962 int rssi; 3963 3964 mask = (le16toh(phy->antenna) >> 4) & IWN_ANT_ABC; 3965 agc = (le16toh(phy->agc) >> 7) & 0x7f; 3966 3967 rssi = 0; 3968 #if 0 3969 if (mask & IWN_ANT_A) /* Ant A */ 3970 rssi = max(rssi, phy->rssi[0]); 3971 if (mask & IWN_ATH_B) /* Ant B */ 3972 rssi = max(rssi, phy->rssi[2]); 3973 if (mask & IWN_ANT_C) /* Ant C */ 3974 rssi = max(rssi, phy->rssi[4]); 3975 #else 3976 rssi = max(rssi, phy->rssi[0]); 3977 rssi = max(rssi, phy->rssi[2]); 3978 rssi = max(rssi, phy->rssi[4]); 3979 #endif 3980 3981 DPRINTF(sc, IWN_DEBUG_RECV, "%s: agc %d mask 0x%x rssi %d %d %d " 3982 "result %d\n", __func__, agc, mask, 3983 phy->rssi[0], phy->rssi[2], phy->rssi[4], 3984 rssi - agc - IWN_RSSI_TO_DBM); 3985 return rssi - agc - IWN_RSSI_TO_DBM; 3986 } 3987 3988 static int 3989 iwn5000_get_rssi(struct iwn_softc *sc, struct iwn_rx_stat *stat) 3990 { 3991 struct iwn5000_rx_phystat *phy = (void *)stat->phybuf; 3992 int rssi; 3993 uint8_t agc; 3994 3995 agc = (le32toh(phy->agc) >> 9) & 0x7f; 3996 3997 rssi = MAX(le16toh(phy->rssi[0]) & 0xff, 3998 le16toh(phy->rssi[1]) & 0xff); 3999 rssi = MAX(le16toh(phy->rssi[2]) & 0xff, rssi); 4000 4001 DPRINTF(sc, IWN_DEBUG_RECV, "%s: agc %d rssi %d %d %d " 4002 "result %d\n", __func__, agc, 4003 phy->rssi[0], phy->rssi[1], phy->rssi[2], 4004 rssi - agc - IWN_RSSI_TO_DBM); 4005 return rssi - agc - IWN_RSSI_TO_DBM; 4006 } 4007 4008 /* 4009 * Retrieve the average noise (in dBm) among receivers. 4010 */ 4011 static int 4012 iwn_get_noise(const struct iwn_rx_general_stats *stats) 4013 { 4014 int i, total, nbant, noise; 4015 4016 total = nbant = 0; 4017 for (i = 0; i < 3; i++) { 4018 if ((noise = le32toh(stats->noise[i]) & 0xff) == 0) 4019 continue; 4020 total += noise; 4021 nbant++; 4022 } 4023 /* There should be at least one antenna but check anyway. */ 4024 return (nbant == 0) ? -127 : (total / nbant) - 107; 4025 } 4026 4027 /* 4028 * Compute temperature (in degC) from last received statistics. 4029 */ 4030 static int 4031 iwn4965_get_temperature(struct iwn_softc *sc) 4032 { 4033 struct iwn_ucode_info *uc = &sc->ucode_info; 4034 int32_t r1, r2, r3, r4, temp; 4035 4036 r1 = le32toh(uc->temp[0].chan20MHz); 4037 r2 = le32toh(uc->temp[1].chan20MHz); 4038 r3 = le32toh(uc->temp[2].chan20MHz); 4039 r4 = le32toh(sc->rawtemp); 4040 4041 if (r1 == r3) /* Prevents division by 0 (should not happen.) */ 4042 return 0; 4043 4044 /* Sign-extend 23-bit R4 value to 32-bit. */ 4045 r4 = (r4 << 8) >> 8; 4046 /* Compute temperature in Kelvin. */ 4047 temp = (259 * (r4 - r2)) / (r3 - r1); 4048 temp = (temp * 97) / 100 + 8; 4049 4050 DPRINTF(sc, IWN_DEBUG_ANY, "temperature %dK/%dC\n", temp, 4051 IWN_KTOC(temp)); 4052 return IWN_KTOC(temp); 4053 } 4054 4055 static int 4056 iwn5000_get_temperature(struct iwn_softc *sc) 4057 { 4058 int32_t temp; 4059 4060 /* 4061 * Temperature is not used by the driver for 5000 Series because 4062 * TX power calibration is handled by firmware. We export it to 4063 * users through the sensor framework though. 4064 */ 4065 temp = le32toh(sc->rawtemp); 4066 if (sc->hw_type == IWN_HW_REV_TYPE_5150) { 4067 temp = (temp / -5) + sc->temp_off; 4068 temp = IWN_KTOC(temp); 4069 } 4070 return temp; 4071 } 4072 4073 /* 4074 * Initialize sensitivity calibration state machine. 4075 */ 4076 static int 4077 iwn_init_sensitivity(struct iwn_softc *sc) 4078 { 4079 const struct iwn_hal *hal = sc->sc_hal; 4080 struct iwn_calib_state *calib = &sc->calib; 4081 uint32_t flags; 4082 int error; 4083 4084 /* Reset calibration state machine. */ 4085 memset(calib, 0, sizeof (*calib)); 4086 calib->state = IWN_CALIB_STATE_INIT; 4087 calib->cck_state = IWN_CCK_STATE_HIFA; 4088 /* Set initial correlation values. */ 4089 calib->ofdm_x1 = sc->limits->min_ofdm_x1; 4090 calib->ofdm_mrc_x1 = sc->limits->min_ofdm_mrc_x1; 4091 calib->ofdm_x4 = sc->limits->min_ofdm_x4; 4092 calib->ofdm_mrc_x4 = sc->limits->min_ofdm_mrc_x4; 4093 calib->cck_x4 = 125; 4094 calib->cck_mrc_x4 = sc->limits->min_cck_mrc_x4; 4095 calib->energy_cck = sc->limits->energy_cck; 4096 4097 /* Write initial sensitivity. */ 4098 error = iwn_send_sensitivity(sc); 4099 if (error != 0) 4100 return error; 4101 4102 /* Write initial gains. */ 4103 error = hal->init_gains(sc); 4104 if (error != 0) 4105 return error; 4106 4107 /* Request statistics at each beacon interval. */ 4108 flags = 0; 4109 DPRINTF(sc, IWN_DEBUG_CALIBRATE, "%s: calibrate phy\n", __func__); 4110 return iwn_cmd(sc, IWN_CMD_GET_STATISTICS, &flags, sizeof flags, 1); 4111 } 4112 4113 /* 4114 * Collect noise and RSSI statistics for the first 20 beacons received 4115 * after association and use them to determine connected antennas and 4116 * to set differential gains. 4117 */ 4118 static void 4119 iwn_collect_noise(struct iwn_softc *sc, 4120 const struct iwn_rx_general_stats *stats) 4121 { 4122 const struct iwn_hal *hal = sc->sc_hal; 4123 struct iwn_calib_state *calib = &sc->calib; 4124 uint32_t val; 4125 int i; 4126 4127 /* Accumulate RSSI and noise for all 3 antennas. */ 4128 for (i = 0; i < 3; i++) { 4129 calib->rssi[i] += le32toh(stats->rssi[i]) & 0xff; 4130 calib->noise[i] += le32toh(stats->noise[i]) & 0xff; 4131 } 4132 /* NB: We update differential gains only once after 20 beacons. */ 4133 if (++calib->nbeacons < 20) 4134 return; 4135 4136 /* Determine highest average RSSI. */ 4137 val = MAX(calib->rssi[0], calib->rssi[1]); 4138 val = MAX(calib->rssi[2], val); 4139 4140 /* Determine which antennas are connected. */ 4141 sc->chainmask = sc->rxchainmask; 4142 for (i = 0; i < 3; i++) 4143 if (val - calib->rssi[i] > 15 * 20) 4144 sc->chainmask &= ~(1 << i); 4145 DPRINTF(sc, IWN_DEBUG_CALIBRATE, 4146 "%s: RX chains mask: theoretical=0x%x, actual=0x%x\n", 4147 __func__, sc->rxchainmask, sc->chainmask); 4148 4149 /* If none of the TX antennas are connected, keep at least one. */ 4150 if ((sc->chainmask & sc->txchainmask) == 0) 4151 sc->chainmask |= IWN_LSB(sc->txchainmask); 4152 4153 (void)hal->set_gains(sc); 4154 calib->state = IWN_CALIB_STATE_RUN; 4155 4156 #ifdef notyet 4157 /* XXX Disable RX chains with no antennas connected. */ 4158 sc->rxon.rxchain = htole16(IWN_RXCHAIN_SEL(sc->chainmask)); 4159 (void)iwn_cmd(sc, IWN_CMD_RXON, &sc->rxon, hal->rxonsz, 1); 4160 #endif 4161 4162 #if 0 4163 /* XXX: not yet */ 4164 /* Enable power-saving mode if requested by user. */ 4165 if (sc->sc_ic.ic_flags & IEEE80211_F_PMGTON) 4166 (void)iwn_set_pslevel(sc, 0, 3, 1); 4167 #endif 4168 } 4169 4170 static int 4171 iwn4965_init_gains(struct iwn_softc *sc) 4172 { 4173 struct iwn_phy_calib_gain cmd; 4174 4175 memset(&cmd, 0, sizeof cmd); 4176 cmd.code = IWN4965_PHY_CALIB_DIFF_GAIN; 4177 /* Differential gains initially set to 0 for all 3 antennas. */ 4178 DPRINTF(sc, IWN_DEBUG_CALIBRATE, 4179 "%s: setting initial differential gains\n", __func__); 4180 return iwn_cmd(sc, IWN_CMD_PHY_CALIB, &cmd, sizeof cmd, 1); 4181 } 4182 4183 static int 4184 iwn5000_init_gains(struct iwn_softc *sc) 4185 { 4186 struct iwn_phy_calib cmd; 4187 4188 memset(&cmd, 0, sizeof cmd); 4189 cmd.code = IWN5000_PHY_CALIB_RESET_NOISE_GAIN; 4190 cmd.ngroups = 1; 4191 cmd.isvalid = 1; 4192 DPRINTF(sc, IWN_DEBUG_CALIBRATE, 4193 "%s: setting initial differential gains\n", __func__); 4194 return iwn_cmd(sc, IWN_CMD_PHY_CALIB, &cmd, sizeof cmd, 1); 4195 } 4196 4197 static int 4198 iwn4965_set_gains(struct iwn_softc *sc) 4199 { 4200 struct iwn_calib_state *calib = &sc->calib; 4201 struct iwn_phy_calib_gain cmd; 4202 int i, delta, noise; 4203 4204 /* Get minimal noise among connected antennas. */ 4205 noise = INT_MAX; /* NB: There's at least one antenna. */ 4206 for (i = 0; i < 3; i++) 4207 if (sc->chainmask & (1 << i)) 4208 noise = MIN(calib->noise[i], noise); 4209 4210 memset(&cmd, 0, sizeof cmd); 4211 cmd.code = IWN4965_PHY_CALIB_DIFF_GAIN; 4212 /* Set differential gains for connected antennas. */ 4213 for (i = 0; i < 3; i++) { 4214 if (sc->chainmask & (1 << i)) { 4215 /* Compute attenuation (in unit of 1.5dB). */ 4216 delta = (noise - (int32_t)calib->noise[i]) / 30; 4217 /* NB: delta <= 0 */ 4218 /* Limit to [-4.5dB,0]. */ 4219 cmd.gain[i] = MIN(abs(delta), 3); 4220 if (delta < 0) 4221 cmd.gain[i] |= 1 << 2; /* sign bit */ 4222 } 4223 } 4224 DPRINTF(sc, IWN_DEBUG_CALIBRATE, 4225 "setting differential gains Ant A/B/C: %x/%x/%x (%x)\n", 4226 cmd.gain[0], cmd.gain[1], cmd.gain[2], sc->chainmask); 4227 return iwn_cmd(sc, IWN_CMD_PHY_CALIB, &cmd, sizeof cmd, 1); 4228 } 4229 4230 static int 4231 iwn5000_set_gains(struct iwn_softc *sc) 4232 { 4233 struct iwn_calib_state *calib = &sc->calib; 4234 struct iwn_phy_calib_gain cmd; 4235 int i, ant, delta, div; 4236 4237 /* We collected 20 beacons and !=6050 need a 1.5 factor. */ 4238 div = (sc->hw_type == IWN_HW_REV_TYPE_6050) ? 20 : 30; 4239 4240 memset(&cmd, 0, sizeof cmd); 4241 cmd.code = IWN5000_PHY_CALIB_NOISE_GAIN; 4242 cmd.ngroups = 1; 4243 cmd.isvalid = 1; 4244 /* Get first available RX antenna as referential. */ 4245 ant = IWN_LSB(sc->rxchainmask); 4246 /* Set differential gains for other antennas. */ 4247 for (i = ant + 1; i < 3; i++) { 4248 if (sc->chainmask & (1 << i)) { 4249 /* The delta is relative to antenna "ant". */ 4250 delta = ((int32_t)calib->noise[ant] - 4251 (int32_t)calib->noise[i]) / div; 4252 /* Limit to [-4.5dB,+4.5dB]. */ 4253 cmd.gain[i - 1] = MIN(abs(delta), 3); 4254 if (delta < 0) 4255 cmd.gain[i - 1] |= 1 << 2; /* sign bit */ 4256 } 4257 } 4258 DPRINTF(sc, IWN_DEBUG_CALIBRATE, 4259 "setting differential gains Ant B/C: %x/%x (%x)\n", 4260 cmd.gain[0], cmd.gain[1], sc->chainmask); 4261 return iwn_cmd(sc, IWN_CMD_PHY_CALIB, &cmd, sizeof cmd, 1); 4262 } 4263 4264 /* 4265 * Tune RF RX sensitivity based on the number of false alarms detected 4266 * during the last beacon period. 4267 */ 4268 static void 4269 iwn_tune_sensitivity(struct iwn_softc *sc, const struct iwn_rx_stats *stats) 4270 { 4271 #define inc(val, inc, max) \ 4272 if ((val) < (max)) { \ 4273 if ((val) < (max) - (inc)) \ 4274 (val) += (inc); \ 4275 else \ 4276 (val) = (max); \ 4277 needs_update = 1; \ 4278 } 4279 #define dec(val, dec, min) \ 4280 if ((val) > (min)) { \ 4281 if ((val) > (min) + (dec)) \ 4282 (val) -= (dec); \ 4283 else \ 4284 (val) = (min); \ 4285 needs_update = 1; \ 4286 } 4287 4288 const struct iwn_sensitivity_limits *limits = sc->limits; 4289 struct iwn_calib_state *calib = &sc->calib; 4290 uint32_t val, rxena, fa; 4291 uint32_t energy[3], energy_min; 4292 uint8_t noise[3], noise_ref; 4293 int i, needs_update = 0; 4294 4295 /* Check that we've been enabled long enough. */ 4296 rxena = le32toh(stats->general.load); 4297 if (rxena == 0) 4298 return; 4299 4300 /* Compute number of false alarms since last call for OFDM. */ 4301 fa = le32toh(stats->ofdm.bad_plcp) - calib->bad_plcp_ofdm; 4302 fa += le32toh(stats->ofdm.fa) - calib->fa_ofdm; 4303 fa *= 200 * 1024; /* 200TU */ 4304 4305 /* Save counters values for next call. */ 4306 calib->bad_plcp_ofdm = le32toh(stats->ofdm.bad_plcp); 4307 calib->fa_ofdm = le32toh(stats->ofdm.fa); 4308 4309 if (fa > 50 * rxena) { 4310 /* High false alarm count, decrease sensitivity. */ 4311 DPRINTF(sc, IWN_DEBUG_CALIBRATE, 4312 "%s: OFDM high false alarm count: %u\n", __func__, fa); 4313 inc(calib->ofdm_x1, 1, limits->max_ofdm_x1); 4314 inc(calib->ofdm_mrc_x1, 1, limits->max_ofdm_mrc_x1); 4315 inc(calib->ofdm_x4, 1, limits->max_ofdm_x4); 4316 inc(calib->ofdm_mrc_x4, 1, limits->max_ofdm_mrc_x4); 4317 4318 } else if (fa < 5 * rxena) { 4319 /* Low false alarm count, increase sensitivity. */ 4320 DPRINTF(sc, IWN_DEBUG_CALIBRATE, 4321 "%s: OFDM low false alarm count: %u\n", __func__, fa); 4322 dec(calib->ofdm_x1, 1, limits->min_ofdm_x1); 4323 dec(calib->ofdm_mrc_x1, 1, limits->min_ofdm_mrc_x1); 4324 dec(calib->ofdm_x4, 1, limits->min_ofdm_x4); 4325 dec(calib->ofdm_mrc_x4, 1, limits->min_ofdm_mrc_x4); 4326 } 4327 4328 /* Compute maximum noise among 3 receivers. */ 4329 for (i = 0; i < 3; i++) 4330 noise[i] = (le32toh(stats->general.noise[i]) >> 8) & 0xff; 4331 val = MAX(noise[0], noise[1]); 4332 val = MAX(noise[2], val); 4333 /* Insert it into our samples table. */ 4334 calib->noise_samples[calib->cur_noise_sample] = val; 4335 calib->cur_noise_sample = (calib->cur_noise_sample + 1) % 20; 4336 4337 /* Compute maximum noise among last 20 samples. */ 4338 noise_ref = calib->noise_samples[0]; 4339 for (i = 1; i < 20; i++) 4340 noise_ref = MAX(noise_ref, calib->noise_samples[i]); 4341 4342 /* Compute maximum energy among 3 receivers. */ 4343 for (i = 0; i < 3; i++) 4344 energy[i] = le32toh(stats->general.energy[i]); 4345 val = MIN(energy[0], energy[1]); 4346 val = MIN(energy[2], val); 4347 /* Insert it into our samples table. */ 4348 calib->energy_samples[calib->cur_energy_sample] = val; 4349 calib->cur_energy_sample = (calib->cur_energy_sample + 1) % 10; 4350 4351 /* Compute minimum energy among last 10 samples. */ 4352 energy_min = calib->energy_samples[0]; 4353 for (i = 1; i < 10; i++) 4354 energy_min = MAX(energy_min, calib->energy_samples[i]); 4355 energy_min += 6; 4356 4357 /* Compute number of false alarms since last call for CCK. */ 4358 fa = le32toh(stats->cck.bad_plcp) - calib->bad_plcp_cck; 4359 fa += le32toh(stats->cck.fa) - calib->fa_cck; 4360 fa *= 200 * 1024; /* 200TU */ 4361 4362 /* Save counters values for next call. */ 4363 calib->bad_plcp_cck = le32toh(stats->cck.bad_plcp); 4364 calib->fa_cck = le32toh(stats->cck.fa); 4365 4366 if (fa > 50 * rxena) { 4367 /* High false alarm count, decrease sensitivity. */ 4368 DPRINTF(sc, IWN_DEBUG_CALIBRATE, 4369 "%s: CCK high false alarm count: %u\n", __func__, fa); 4370 calib->cck_state = IWN_CCK_STATE_HIFA; 4371 calib->low_fa = 0; 4372 4373 if (calib->cck_x4 > 160) { 4374 calib->noise_ref = noise_ref; 4375 if (calib->energy_cck > 2) 4376 dec(calib->energy_cck, 2, energy_min); 4377 } 4378 if (calib->cck_x4 < 160) { 4379 calib->cck_x4 = 161; 4380 needs_update = 1; 4381 } else 4382 inc(calib->cck_x4, 3, limits->max_cck_x4); 4383 4384 inc(calib->cck_mrc_x4, 3, limits->max_cck_mrc_x4); 4385 4386 } else if (fa < 5 * rxena) { 4387 /* Low false alarm count, increase sensitivity. */ 4388 DPRINTF(sc, IWN_DEBUG_CALIBRATE, 4389 "%s: CCK low false alarm count: %u\n", __func__, fa); 4390 calib->cck_state = IWN_CCK_STATE_LOFA; 4391 calib->low_fa++; 4392 4393 if (calib->cck_state != IWN_CCK_STATE_INIT && 4394 (((int32_t)calib->noise_ref - (int32_t)noise_ref) > 2 || 4395 calib->low_fa > 100)) { 4396 inc(calib->energy_cck, 2, limits->min_energy_cck); 4397 dec(calib->cck_x4, 3, limits->min_cck_x4); 4398 dec(calib->cck_mrc_x4, 3, limits->min_cck_mrc_x4); 4399 } 4400 } else { 4401 /* Not worth to increase or decrease sensitivity. */ 4402 DPRINTF(sc, IWN_DEBUG_CALIBRATE, 4403 "%s: CCK normal false alarm count: %u\n", __func__, fa); 4404 calib->low_fa = 0; 4405 calib->noise_ref = noise_ref; 4406 4407 if (calib->cck_state == IWN_CCK_STATE_HIFA) { 4408 /* Previous interval had many false alarms. */ 4409 dec(calib->energy_cck, 8, energy_min); 4410 } 4411 calib->cck_state = IWN_CCK_STATE_INIT; 4412 } 4413 4414 if (needs_update) 4415 (void)iwn_send_sensitivity(sc); 4416 #undef dec 4417 #undef inc 4418 } 4419 4420 static int 4421 iwn_send_sensitivity(struct iwn_softc *sc) 4422 { 4423 struct iwn_calib_state *calib = &sc->calib; 4424 struct iwn_sensitivity_cmd cmd; 4425 4426 memset(&cmd, 0, sizeof cmd); 4427 cmd.which = IWN_SENSITIVITY_WORKTBL; 4428 /* OFDM modulation. */ 4429 cmd.corr_ofdm_x1 = htole16(calib->ofdm_x1); 4430 cmd.corr_ofdm_mrc_x1 = htole16(calib->ofdm_mrc_x1); 4431 cmd.corr_ofdm_x4 = htole16(calib->ofdm_x4); 4432 cmd.corr_ofdm_mrc_x4 = htole16(calib->ofdm_mrc_x4); 4433 cmd.energy_ofdm = htole16(sc->limits->energy_ofdm); 4434 cmd.energy_ofdm_th = htole16(62); 4435 /* CCK modulation. */ 4436 cmd.corr_cck_x4 = htole16(calib->cck_x4); 4437 cmd.corr_cck_mrc_x4 = htole16(calib->cck_mrc_x4); 4438 cmd.energy_cck = htole16(calib->energy_cck); 4439 /* Barker modulation: use default values. */ 4440 cmd.corr_barker = htole16(190); 4441 cmd.corr_barker_mrc = htole16(390); 4442 4443 DPRINTF(sc, IWN_DEBUG_CALIBRATE, 4444 "%s: set sensitivity %d/%d/%d/%d/%d/%d/%d\n", __func__, 4445 calib->ofdm_x1, calib->ofdm_mrc_x1, calib->ofdm_x4, 4446 calib->ofdm_mrc_x4, calib->cck_x4, 4447 calib->cck_mrc_x4, calib->energy_cck); 4448 return iwn_cmd(sc, IWN_CMD_SET_SENSITIVITY, &cmd, sizeof cmd, 1); 4449 } 4450 4451 /* 4452 * Set STA mode power saving level (between 0 and 5). 4453 * Level 0 is CAM (Continuously Aware Mode), 5 is for maximum power saving. 4454 */ 4455 static int 4456 iwn_set_pslevel(struct iwn_softc *sc, int dtim, int level, int async) 4457 { 4458 const struct iwn_pmgt *pmgt; 4459 struct iwn_pmgt_cmd cmd; 4460 uint32_t max, skip_dtim; 4461 uint32_t tmp; 4462 int i; 4463 4464 /* Select which PS parameters to use. */ 4465 if (dtim <= 2) 4466 pmgt = &iwn_pmgt[0][level]; 4467 else if (dtim <= 10) 4468 pmgt = &iwn_pmgt[1][level]; 4469 else 4470 pmgt = &iwn_pmgt[2][level]; 4471 4472 memset(&cmd, 0, sizeof cmd); 4473 if (level != 0) /* not CAM */ 4474 cmd.flags |= htole16(IWN_PS_ALLOW_SLEEP); 4475 if (level == 5) 4476 cmd.flags |= htole16(IWN_PS_FAST_PD); 4477 /* Retrieve PCIe Active State Power Management (ASPM). */ 4478 tmp = pci_read_config(sc->sc_dev, sc->sc_cap_off + 0x10, 1); 4479 if (!(tmp & 0x1)) /* L0s Entry disabled. */ 4480 cmd.flags |= htole16(IWN_PS_PCI_PMGT); 4481 cmd.rxtimeout = htole32(pmgt->rxtimeout * 1024); 4482 cmd.txtimeout = htole32(pmgt->txtimeout * 1024); 4483 4484 if (dtim == 0) { 4485 dtim = 1; 4486 skip_dtim = 0; 4487 } else 4488 skip_dtim = pmgt->skip_dtim; 4489 if (skip_dtim != 0) { 4490 cmd.flags |= htole16(IWN_PS_SLEEP_OVER_DTIM); 4491 max = pmgt->intval[4]; 4492 if (max == (uint32_t)-1) 4493 max = dtim * (skip_dtim + 1); 4494 else if (max > dtim) 4495 max = (max / dtim) * dtim; 4496 } else 4497 max = dtim; 4498 for (i = 0; i < 5; i++) 4499 cmd.intval[i] = htole32(MIN(max, pmgt->intval[i])); 4500 4501 DPRINTF(sc, IWN_DEBUG_RESET, "setting power saving level to %d\n", 4502 level); 4503 return iwn_cmd(sc, IWN_CMD_SET_POWER_MODE, &cmd, sizeof cmd, async); 4504 } 4505 4506 static int 4507 iwn_config(struct iwn_softc *sc) 4508 { 4509 const struct iwn_hal *hal = sc->sc_hal; 4510 struct ifnet *ifp = sc->sc_ifp; 4511 struct ieee80211com *ic = ifp->if_l2com; 4512 struct iwn_bluetooth bluetooth; 4513 uint32_t txmask; 4514 int error; 4515 uint16_t rxchain; 4516 4517 /* Configure valid TX chains for 5000 Series. */ 4518 if (sc->hw_type != IWN_HW_REV_TYPE_4965) { 4519 txmask = htole32(sc->txchainmask); 4520 DPRINTF(sc, IWN_DEBUG_RESET, 4521 "%s: configuring valid TX chains 0x%x\n", __func__, txmask); 4522 error = iwn_cmd(sc, IWN5000_CMD_TX_ANT_CONFIG, &txmask, 4523 sizeof txmask, 0); 4524 if (error != 0) { 4525 device_printf(sc->sc_dev, 4526 "%s: could not configure valid TX chains, " 4527 "error %d\n", __func__, error); 4528 return error; 4529 } 4530 } 4531 4532 /* Configure bluetooth coexistence. */ 4533 memset(&bluetooth, 0, sizeof bluetooth); 4534 bluetooth.flags = IWN_BT_COEX_CHAN_ANN | IWN_BT_COEX_BT_PRIO; 4535 bluetooth.lead_time = IWN_BT_LEAD_TIME_DEF; 4536 bluetooth.max_kill = IWN_BT_MAX_KILL_DEF; 4537 DPRINTF(sc, IWN_DEBUG_RESET, "%s: config bluetooth coexistence\n", 4538 __func__); 4539 error = iwn_cmd(sc, IWN_CMD_BT_COEX, &bluetooth, sizeof bluetooth, 0); 4540 if (error != 0) { 4541 device_printf(sc->sc_dev, 4542 "%s: could not configure bluetooth coexistence, error %d\n", 4543 __func__, error); 4544 return error; 4545 } 4546 4547 /* Set mode, channel, RX filter and enable RX. */ 4548 memset(&sc->rxon, 0, sizeof (struct iwn_rxon)); 4549 IEEE80211_ADDR_COPY(sc->rxon.myaddr, IF_LLADDR(ifp)); 4550 IEEE80211_ADDR_COPY(sc->rxon.wlap, IF_LLADDR(ifp)); 4551 sc->rxon.chan = ieee80211_chan2ieee(ic, ic->ic_curchan); 4552 sc->rxon.flags = htole32(IWN_RXON_TSF | IWN_RXON_CTS_TO_SELF); 4553 if (IEEE80211_IS_CHAN_2GHZ(ic->ic_curchan)) 4554 sc->rxon.flags |= htole32(IWN_RXON_AUTO | IWN_RXON_24GHZ); 4555 switch (ic->ic_opmode) { 4556 case IEEE80211_M_STA: 4557 sc->rxon.mode = IWN_MODE_STA; 4558 sc->rxon.filter = htole32(IWN_FILTER_MULTICAST); 4559 break; 4560 case IEEE80211_M_MONITOR: 4561 sc->rxon.mode = IWN_MODE_MONITOR; 4562 sc->rxon.filter = htole32(IWN_FILTER_MULTICAST | 4563 IWN_FILTER_CTL | IWN_FILTER_PROMISC); 4564 break; 4565 default: 4566 /* Should not get there. */ 4567 break; 4568 } 4569 sc->rxon.cck_mask = 0x0f; /* not yet negotiated */ 4570 sc->rxon.ofdm_mask = 0xff; /* not yet negotiated */ 4571 sc->rxon.ht_single_mask = 0xff; 4572 sc->rxon.ht_dual_mask = 0xff; 4573 sc->rxon.ht_triple_mask = 0xff; 4574 rxchain = 4575 IWN_RXCHAIN_VALID(sc->rxchainmask) | 4576 IWN_RXCHAIN_MIMO_COUNT(2) | 4577 IWN_RXCHAIN_IDLE_COUNT(2); 4578 sc->rxon.rxchain = htole16(rxchain); 4579 DPRINTF(sc, IWN_DEBUG_RESET, "%s: setting configuration\n", __func__); 4580 error = iwn_cmd(sc, IWN_CMD_RXON, &sc->rxon, hal->rxonsz, 0); 4581 if (error != 0) { 4582 device_printf(sc->sc_dev, 4583 "%s: RXON command failed\n", __func__); 4584 return error; 4585 } 4586 4587 error = iwn_add_broadcast_node(sc, 0); 4588 if (error != 0) { 4589 device_printf(sc->sc_dev, 4590 "%s: could not add broadcast node\n", __func__); 4591 return error; 4592 } 4593 4594 /* Configuration has changed, set TX power accordingly. */ 4595 error = hal->set_txpower(sc, ic->ic_curchan, 0); 4596 if (error != 0) { 4597 device_printf(sc->sc_dev, 4598 "%s: could not set TX power\n", __func__); 4599 return error; 4600 } 4601 4602 error = iwn_set_critical_temp(sc); 4603 if (error != 0) { 4604 device_printf(sc->sc_dev, 4605 "%s: ccould not set critical temperature\n", __func__); 4606 return error; 4607 } 4608 4609 /* Set power saving level to CAM during initialization. */ 4610 error = iwn_set_pslevel(sc, 0, 0, 0); 4611 if (error != 0) { 4612 device_printf(sc->sc_dev, 4613 "%s: could not set power saving level\n", __func__); 4614 return error; 4615 } 4616 return 0; 4617 } 4618 4619 static int 4620 iwn_scan(struct iwn_softc *sc) 4621 { 4622 struct ifnet *ifp = sc->sc_ifp; 4623 struct ieee80211com *ic = ifp->if_l2com; 4624 struct ieee80211_scan_state *ss = ic->ic_scan; /*XXX*/ 4625 struct iwn_scan_hdr *hdr; 4626 struct iwn_cmd_data *tx; 4627 struct iwn_scan_essid *essid; 4628 struct iwn_scan_chan *chan; 4629 struct ieee80211_frame *wh; 4630 struct ieee80211_rateset *rs; 4631 struct ieee80211_channel *c; 4632 int buflen, error, nrates; 4633 uint16_t rxchain; 4634 uint8_t *buf, *frm, txant; 4635 4636 buf = malloc(IWN_SCAN_MAXSZ, M_DEVBUF, M_NOWAIT | M_ZERO); 4637 if (buf == NULL) { 4638 device_printf(sc->sc_dev, 4639 "%s: could not allocate buffer for scan command\n", 4640 __func__); 4641 return ENOMEM; 4642 } 4643 hdr = (struct iwn_scan_hdr *)buf; 4644 4645 /* 4646 * Move to the next channel if no frames are received within 10ms 4647 * after sending the probe request. 4648 */ 4649 hdr->quiet_time = htole16(10); /* timeout in milliseconds */ 4650 hdr->quiet_threshold = htole16(1); /* min # of packets */ 4651 4652 /* Select antennas for scanning. */ 4653 rxchain = 4654 IWN_RXCHAIN_VALID(sc->rxchainmask) | 4655 IWN_RXCHAIN_FORCE_MIMO_SEL(sc->rxchainmask) | 4656 IWN_RXCHAIN_DRIVER_FORCE; 4657 if (IEEE80211_IS_CHAN_A(ic->ic_curchan) && 4658 sc->hw_type == IWN_HW_REV_TYPE_4965) { 4659 /* Ant A must be avoided in 5GHz because of an HW bug. */ 4660 rxchain |= IWN_RXCHAIN_FORCE_SEL(IWN_ANT_BC); 4661 } else /* Use all available RX antennas. */ 4662 rxchain |= IWN_RXCHAIN_FORCE_SEL(sc->rxchainmask); 4663 hdr->rxchain = htole16(rxchain); 4664 hdr->filter = htole32(IWN_FILTER_MULTICAST | IWN_FILTER_BEACON); 4665 4666 tx = (struct iwn_cmd_data *)(hdr + 1); 4667 tx->flags = htole32(IWN_TX_AUTO_SEQ); 4668 tx->id = sc->sc_hal->broadcast_id; 4669 tx->lifetime = htole32(IWN_LIFETIME_INFINITE); 4670 4671 if (IEEE80211_IS_CHAN_A(ic->ic_curchan)) { 4672 /* Send probe requests at 6Mbps. */ 4673 tx->plcp = iwn_rates[IWN_RIDX_OFDM6].plcp; 4674 rs = &ic->ic_sup_rates[IEEE80211_MODE_11A]; 4675 } else { 4676 hdr->flags = htole32(IWN_RXON_24GHZ | IWN_RXON_AUTO); 4677 /* Send probe requests at 1Mbps. */ 4678 tx->plcp = iwn_rates[IWN_RIDX_CCK1].plcp; 4679 tx->rflags = IWN_RFLAG_CCK; 4680 rs = &ic->ic_sup_rates[IEEE80211_MODE_11G]; 4681 } 4682 /* Use the first valid TX antenna. */ 4683 txant = IWN_LSB(sc->txchainmask); 4684 tx->rflags |= IWN_RFLAG_ANT(txant); 4685 4686 essid = (struct iwn_scan_essid *)(tx + 1); 4687 if (ss->ss_ssid[0].len != 0) { 4688 essid[0].id = IEEE80211_ELEMID_SSID; 4689 essid[0].len = ss->ss_ssid[0].len; 4690 memcpy(essid[0].data, ss->ss_ssid[0].ssid, ss->ss_ssid[0].len); 4691 } 4692 4693 /* 4694 * Build a probe request frame. Most of the following code is a 4695 * copy & paste of what is done in net80211. 4696 */ 4697 wh = (struct ieee80211_frame *)(essid + 20); 4698 wh->i_fc[0] = IEEE80211_FC0_VERSION_0 | IEEE80211_FC0_TYPE_MGT | 4699 IEEE80211_FC0_SUBTYPE_PROBE_REQ; 4700 wh->i_fc[1] = IEEE80211_FC1_DIR_NODS; 4701 IEEE80211_ADDR_COPY(wh->i_addr1, ifp->if_broadcastaddr); 4702 IEEE80211_ADDR_COPY(wh->i_addr2, IF_LLADDR(ifp)); 4703 IEEE80211_ADDR_COPY(wh->i_addr3, ifp->if_broadcastaddr); 4704 *(uint16_t *)&wh->i_dur[0] = 0; /* filled by HW */ 4705 *(uint16_t *)&wh->i_seq[0] = 0; /* filled by HW */ 4706 4707 frm = (uint8_t *)(wh + 1); 4708 4709 /* Add SSID IE. */ 4710 *frm++ = IEEE80211_ELEMID_SSID; 4711 *frm++ = ss->ss_ssid[0].len; 4712 memcpy(frm, ss->ss_ssid[0].ssid, ss->ss_ssid[0].len); 4713 frm += ss->ss_ssid[0].len; 4714 4715 /* Add supported rates IE. */ 4716 *frm++ = IEEE80211_ELEMID_RATES; 4717 nrates = rs->rs_nrates; 4718 if (nrates > IEEE80211_RATE_SIZE) 4719 nrates = IEEE80211_RATE_SIZE; 4720 *frm++ = nrates; 4721 memcpy(frm, rs->rs_rates, nrates); 4722 frm += nrates; 4723 4724 /* Add supported xrates IE. */ 4725 if (rs->rs_nrates > IEEE80211_RATE_SIZE) { 4726 nrates = rs->rs_nrates - IEEE80211_RATE_SIZE; 4727 *frm++ = IEEE80211_ELEMID_XRATES; 4728 *frm++ = (uint8_t)nrates; 4729 memcpy(frm, rs->rs_rates + IEEE80211_RATE_SIZE, nrates); 4730 frm += nrates; 4731 } 4732 4733 /* Set length of probe request. */ 4734 tx->len = htole16(frm - (uint8_t *)wh); 4735 4736 c = ic->ic_curchan; 4737 chan = (struct iwn_scan_chan *)frm; 4738 chan->chan = htole16(ieee80211_chan2ieee(ic, c)); 4739 chan->flags = 0; 4740 if (ss->ss_nssid > 0) 4741 chan->flags |= htole32(IWN_CHAN_NPBREQS(1)); 4742 chan->dsp_gain = 0x6e; 4743 if (IEEE80211_IS_CHAN_5GHZ(c) && 4744 !(c->ic_flags & IEEE80211_CHAN_PASSIVE)) { 4745 chan->rf_gain = 0x3b; 4746 chan->active = htole16(24); 4747 chan->passive = htole16(110); 4748 chan->flags |= htole32(IWN_CHAN_ACTIVE); 4749 } else if (IEEE80211_IS_CHAN_5GHZ(c)) { 4750 chan->rf_gain = 0x3b; 4751 chan->active = htole16(24); 4752 if (sc->rxon.associd) 4753 chan->passive = htole16(78); 4754 else 4755 chan->passive = htole16(110); 4756 hdr->crc_threshold = 0xffff; 4757 } else if (!(c->ic_flags & IEEE80211_CHAN_PASSIVE)) { 4758 chan->rf_gain = 0x28; 4759 chan->active = htole16(36); 4760 chan->passive = htole16(120); 4761 chan->flags |= htole32(IWN_CHAN_ACTIVE); 4762 } else { 4763 chan->rf_gain = 0x28; 4764 chan->active = htole16(36); 4765 if (sc->rxon.associd) 4766 chan->passive = htole16(88); 4767 else 4768 chan->passive = htole16(120); 4769 hdr->crc_threshold = 0xffff; 4770 } 4771 4772 DPRINTF(sc, IWN_DEBUG_STATE, 4773 "%s: chan %u flags 0x%x rf_gain 0x%x " 4774 "dsp_gain 0x%x active 0x%x passive 0x%x\n", __func__, 4775 chan->chan, chan->flags, chan->rf_gain, chan->dsp_gain, 4776 chan->active, chan->passive); 4777 4778 hdr->nchan++; 4779 chan++; 4780 buflen = (uint8_t *)chan - buf; 4781 hdr->len = htole16(buflen); 4782 4783 DPRINTF(sc, IWN_DEBUG_STATE, "sending scan command nchan=%d\n", 4784 hdr->nchan); 4785 error = iwn_cmd(sc, IWN_CMD_SCAN, buf, buflen, 1); 4786 free(buf, M_DEVBUF); 4787 return error; 4788 } 4789 4790 static int 4791 iwn_auth(struct iwn_softc *sc, struct ieee80211vap *vap) 4792 { 4793 const struct iwn_hal *hal = sc->sc_hal; 4794 struct ifnet *ifp = sc->sc_ifp; 4795 struct ieee80211com *ic = ifp->if_l2com; 4796 struct ieee80211_node *ni = vap->iv_bss; 4797 int error; 4798 4799 sc->calib.state = IWN_CALIB_STATE_INIT; 4800 4801 /* Update adapter configuration. */ 4802 IEEE80211_ADDR_COPY(sc->rxon.bssid, ni->ni_bssid); 4803 sc->rxon.chan = htole16(ieee80211_chan2ieee(ic, ni->ni_chan)); 4804 sc->rxon.flags = htole32(IWN_RXON_TSF | IWN_RXON_CTS_TO_SELF); 4805 if (IEEE80211_IS_CHAN_2GHZ(ni->ni_chan)) 4806 sc->rxon.flags |= htole32(IWN_RXON_AUTO | IWN_RXON_24GHZ); 4807 if (ic->ic_flags & IEEE80211_F_SHSLOT) 4808 sc->rxon.flags |= htole32(IWN_RXON_SHSLOT); 4809 if (ic->ic_flags & IEEE80211_F_SHPREAMBLE) 4810 sc->rxon.flags |= htole32(IWN_RXON_SHPREAMBLE); 4811 if (IEEE80211_IS_CHAN_A(ni->ni_chan)) { 4812 sc->rxon.cck_mask = 0; 4813 sc->rxon.ofdm_mask = 0x15; 4814 } else if (IEEE80211_IS_CHAN_B(ni->ni_chan)) { 4815 sc->rxon.cck_mask = 0x03; 4816 sc->rxon.ofdm_mask = 0; 4817 } else { 4818 /* XXX assume 802.11b/g */ 4819 sc->rxon.cck_mask = 0x0f; 4820 sc->rxon.ofdm_mask = 0x15; 4821 } 4822 DPRINTF(sc, IWN_DEBUG_STATE, 4823 "%s: config chan %d mode %d flags 0x%x cck 0x%x ofdm 0x%x " 4824 "ht_single 0x%x ht_dual 0x%x rxchain 0x%x " 4825 "myaddr %6D wlap %6D bssid %6D associd %d filter 0x%x\n", 4826 __func__, 4827 le16toh(sc->rxon.chan), sc->rxon.mode, le32toh(sc->rxon.flags), 4828 sc->rxon.cck_mask, sc->rxon.ofdm_mask, 4829 sc->rxon.ht_single_mask, sc->rxon.ht_dual_mask, 4830 le16toh(sc->rxon.rxchain), 4831 sc->rxon.myaddr, ":", sc->rxon.wlap, ":", sc->rxon.bssid, ":", 4832 le16toh(sc->rxon.associd), le32toh(sc->rxon.filter)); 4833 error = iwn_cmd(sc, IWN_CMD_RXON, &sc->rxon, hal->rxonsz, 1); 4834 if (error != 0) { 4835 device_printf(sc->sc_dev, 4836 "%s: RXON command failed, error %d\n", __func__, error); 4837 return error; 4838 } 4839 4840 /* Configuration has changed, set TX power accordingly. */ 4841 error = hal->set_txpower(sc, ni->ni_chan, 1); 4842 if (error != 0) { 4843 device_printf(sc->sc_dev, 4844 "%s: could not set Tx power, error %d\n", __func__, error); 4845 return error; 4846 } 4847 /* 4848 * Reconfiguring RXON clears the firmware nodes table so we must 4849 * add the broadcast node again. 4850 */ 4851 error = iwn_add_broadcast_node(sc, 1); 4852 if (error != 0) { 4853 device_printf(sc->sc_dev, 4854 "%s: could not add broadcast node, error %d\n", 4855 __func__, error); 4856 return error; 4857 } 4858 return 0; 4859 } 4860 4861 /* 4862 * Configure the adapter for associated state. 4863 */ 4864 static int 4865 iwn_run(struct iwn_softc *sc, struct ieee80211vap *vap) 4866 { 4867 #define MS(v,x) (((v) & x) >> x##_S) 4868 const struct iwn_hal *hal = sc->sc_hal; 4869 struct ifnet *ifp = sc->sc_ifp; 4870 struct ieee80211com *ic = ifp->if_l2com; 4871 struct ieee80211_node *ni = vap->iv_bss; 4872 struct iwn_node_info node; 4873 int error; 4874 4875 sc->calib.state = IWN_CALIB_STATE_INIT; 4876 4877 if (ic->ic_opmode == IEEE80211_M_MONITOR) { 4878 /* Link LED blinks while monitoring. */ 4879 iwn_set_led(sc, IWN_LED_LINK, 5, 5); 4880 return 0; 4881 } 4882 error = iwn_set_timing(sc, ni); 4883 if (error != 0) { 4884 device_printf(sc->sc_dev, 4885 "%s: could not set timing, error %d\n", __func__, error); 4886 return error; 4887 } 4888 4889 /* Update adapter configuration. */ 4890 IEEE80211_ADDR_COPY(sc->rxon.bssid, ni->ni_bssid); 4891 sc->rxon.chan = htole16(ieee80211_chan2ieee(ic, ni->ni_chan)); 4892 sc->rxon.associd = htole16(IEEE80211_AID(ni->ni_associd)); 4893 /* Short preamble and slot time are negotiated when associating. */ 4894 sc->rxon.flags &= ~htole32(IWN_RXON_SHPREAMBLE | IWN_RXON_SHSLOT); 4895 sc->rxon.flags |= htole32(IWN_RXON_TSF | IWN_RXON_CTS_TO_SELF); 4896 if (IEEE80211_IS_CHAN_2GHZ(ni->ni_chan)) 4897 sc->rxon.flags |= htole32(IWN_RXON_AUTO | IWN_RXON_24GHZ); 4898 else 4899 sc->rxon.flags &= ~htole32(IWN_RXON_AUTO | IWN_RXON_24GHZ); 4900 if (ic->ic_flags & IEEE80211_F_SHSLOT) 4901 sc->rxon.flags |= htole32(IWN_RXON_SHSLOT); 4902 if (ic->ic_flags & IEEE80211_F_SHPREAMBLE) 4903 sc->rxon.flags |= htole32(IWN_RXON_SHPREAMBLE); 4904 if (IEEE80211_IS_CHAN_A(ni->ni_chan)) { 4905 sc->rxon.cck_mask = 0; 4906 sc->rxon.ofdm_mask = 0x15; 4907 } else if (IEEE80211_IS_CHAN_B(ni->ni_chan)) { 4908 sc->rxon.cck_mask = 0x03; 4909 sc->rxon.ofdm_mask = 0; 4910 } else { 4911 /* XXX assume 802.11b/g */ 4912 sc->rxon.cck_mask = 0x0f; 4913 sc->rxon.ofdm_mask = 0x15; 4914 } 4915 #if 0 /* HT */ 4916 if (IEEE80211_IS_CHAN_HT(ni->ni_chan)) { 4917 sc->rxon.flags &= ~htole32(IWN_RXON_HT); 4918 if (IEEE80211_IS_CHAN_HT40U(ni->ni_chan)) 4919 sc->rxon.flags |= htole32(IWN_RXON_HT40U); 4920 else if (IEEE80211_IS_CHAN_HT40D(ni->ni_chan)) 4921 sc->rxon.flags |= htole32(IWN_RXON_HT40D); 4922 else 4923 sc->rxon.flags |= htole32(IWN_RXON_HT20); 4924 sc->rxon.rxchain = htole16( 4925 IWN_RXCHAIN_VALID(3) 4926 | IWN_RXCHAIN_MIMO_COUNT(3) 4927 | IWN_RXCHAIN_IDLE_COUNT(1) 4928 | IWN_RXCHAIN_MIMO_FORCE); 4929 4930 maxrxampdu = MS(ni->ni_htparam, IEEE80211_HTCAP_MAXRXAMPDU); 4931 ampdudensity = MS(ni->ni_htparam, IEEE80211_HTCAP_MPDUDENSITY); 4932 } else 4933 maxrxampdu = ampdudensity = 0; 4934 #endif 4935 sc->rxon.filter |= htole32(IWN_FILTER_BSS); 4936 4937 DPRINTF(sc, IWN_DEBUG_STATE, 4938 "%s: config chan %d mode %d flags 0x%x cck 0x%x ofdm 0x%x " 4939 "ht_single 0x%x ht_dual 0x%x rxchain 0x%x " 4940 "myaddr %6D wlap %6D bssid %6D associd %d filter 0x%x\n", 4941 __func__, 4942 le16toh(sc->rxon.chan), sc->rxon.mode, le32toh(sc->rxon.flags), 4943 sc->rxon.cck_mask, sc->rxon.ofdm_mask, 4944 sc->rxon.ht_single_mask, sc->rxon.ht_dual_mask, 4945 le16toh(sc->rxon.rxchain), 4946 sc->rxon.myaddr, ":", sc->rxon.wlap, ":", sc->rxon.bssid, ":", 4947 le16toh(sc->rxon.associd), le32toh(sc->rxon.filter)); 4948 error = iwn_cmd(sc, IWN_CMD_RXON, &sc->rxon, hal->rxonsz, 1); 4949 if (error != 0) { 4950 device_printf(sc->sc_dev, 4951 "%s: could not update configuration, error %d\n", 4952 __func__, error); 4953 return error; 4954 } 4955 4956 /* Configuration has changed, set TX power accordingly. */ 4957 error = hal->set_txpower(sc, ni->ni_chan, 1); 4958 if (error != 0) { 4959 device_printf(sc->sc_dev, 4960 "%s: could not set Tx power, error %d\n", __func__, error); 4961 return error; 4962 } 4963 4964 /* Add BSS node. */ 4965 memset(&node, 0, sizeof node); 4966 IEEE80211_ADDR_COPY(node.macaddr, ni->ni_macaddr); 4967 node.id = IWN_ID_BSS; 4968 #ifdef notyet 4969 node.htflags = htole32(IWN_AMDPU_SIZE_FACTOR(3) | 4970 IWN_AMDPU_DENSITY(5)); /* 2us */ 4971 #endif 4972 DPRINTF(sc, IWN_DEBUG_STATE, "%s: add BSS node, id %d htflags 0x%x\n", 4973 __func__, node.id, le32toh(node.htflags)); 4974 error = hal->add_node(sc, &node, 1); 4975 if (error != 0) { 4976 device_printf(sc->sc_dev, "could not add BSS node\n"); 4977 return error; 4978 } 4979 DPRINTF(sc, IWN_DEBUG_STATE, "setting link quality for node %d\n", 4980 node.id); 4981 error = iwn_set_link_quality(sc, node.id, 1); 4982 if (error != 0) { 4983 device_printf(sc->sc_dev, 4984 "%s: could not setup MRR for node %d, error %d\n", 4985 __func__, node.id, error); 4986 return error; 4987 } 4988 4989 error = iwn_init_sensitivity(sc); 4990 if (error != 0) { 4991 device_printf(sc->sc_dev, 4992 "%s: could not set sensitivity, error %d\n", 4993 __func__, error); 4994 return error; 4995 } 4996 4997 /* Start periodic calibration timer. */ 4998 sc->calib.state = IWN_CALIB_STATE_ASSOC; 4999 iwn_calib_reset(sc); 5000 5001 /* Link LED always on while associated. */ 5002 iwn_set_led(sc, IWN_LED_LINK, 0, 1); 5003 5004 return 0; 5005 #undef MS 5006 } 5007 5008 #if 0 /* HT */ 5009 /* 5010 * This function is called by upper layer when an ADDBA request is received 5011 * from another STA and before the ADDBA response is sent. 5012 */ 5013 static int 5014 iwn_ampdu_rx_start(struct ieee80211com *ic, struct ieee80211_node *ni, 5015 uint8_t tid) 5016 { 5017 struct ieee80211_rx_ba *ba = &ni->ni_rx_ba[tid]; 5018 struct iwn_softc *sc = ic->ic_softc; 5019 struct iwn_node *wn = (void *)ni; 5020 struct iwn_node_info node; 5021 5022 memset(&node, 0, sizeof node); 5023 node.id = wn->id; 5024 node.control = IWN_NODE_UPDATE; 5025 node.flags = IWN_FLAG_SET_ADDBA; 5026 node.addba_tid = tid; 5027 node.addba_ssn = htole16(ba->ba_winstart); 5028 DPRINTF(sc, IWN_DEBUG_RECV, "ADDBA RA=%d TID=%d SSN=%d\n", 5029 wn->id, tid, ba->ba_winstart)); 5030 return sc->sc_hal->add_node(sc, &node, 1); 5031 } 5032 5033 /* 5034 * This function is called by upper layer on teardown of an HT-immediate 5035 * Block Ack agreement (eg. uppon receipt of a DELBA frame.) 5036 */ 5037 static void 5038 iwn_ampdu_rx_stop(struct ieee80211com *ic, struct ieee80211_node *ni, 5039 uint8_t tid) 5040 { 5041 struct iwn_softc *sc = ic->ic_softc; 5042 struct iwn_node *wn = (void *)ni; 5043 struct iwn_node_info node; 5044 5045 memset(&node, 0, sizeof node); 5046 node.id = wn->id; 5047 node.control = IWN_NODE_UPDATE; 5048 node.flags = IWN_FLAG_SET_DELBA; 5049 node.delba_tid = tid; 5050 DPRINTF(sc, IWN_DEBUG_RECV, "DELBA RA=%d TID=%d\n", wn->id, tid); 5051 (void)sc->sc_hal->add_node(sc, &node, 1); 5052 } 5053 5054 /* 5055 * This function is called by upper layer when an ADDBA response is received 5056 * from another STA. 5057 */ 5058 static int 5059 iwn_ampdu_tx_start(struct ieee80211com *ic, struct ieee80211_node *ni, 5060 uint8_t tid) 5061 { 5062 struct ieee80211_tx_ba *ba = &ni->ni_tx_ba[tid]; 5063 struct iwn_softc *sc = ic->ic_softc; 5064 const struct iwn_hal *hal = sc->sc_hal; 5065 struct iwn_node *wn = (void *)ni; 5066 struct iwn_node_info node; 5067 int error; 5068 5069 /* Enable TX for the specified RA/TID. */ 5070 wn->disable_tid &= ~(1 << tid); 5071 memset(&node, 0, sizeof node); 5072 node.id = wn->id; 5073 node.control = IWN_NODE_UPDATE; 5074 node.flags = IWN_FLAG_SET_DISABLE_TID; 5075 node.disable_tid = htole16(wn->disable_tid); 5076 error = hal->add_node(sc, &node, 1); 5077 if (error != 0) 5078 return error; 5079 5080 if ((error = iwn_nic_lock(sc)) != 0) 5081 return error; 5082 hal->ampdu_tx_start(sc, ni, tid, ba->ba_winstart); 5083 iwn_nic_unlock(sc); 5084 return 0; 5085 } 5086 5087 static void 5088 iwn_ampdu_tx_stop(struct ieee80211com *ic, struct ieee80211_node *ni, 5089 uint8_t tid) 5090 { 5091 struct ieee80211_tx_ba *ba = &ni->ni_tx_ba[tid]; 5092 struct iwn_softc *sc = ic->ic_softc; 5093 int error; 5094 5095 error = iwn_nic_lock(sc); 5096 if (error != 0) 5097 return; 5098 sc->sc_hal->ampdu_tx_stop(sc, tid, ba->ba_winstart); 5099 iwn_nic_unlock(sc); 5100 } 5101 5102 static void 5103 iwn4965_ampdu_tx_start(struct iwn_softc *sc, struct ieee80211_node *ni, 5104 uint8_t tid, uint16_t ssn) 5105 { 5106 struct iwn_node *wn = (void *)ni; 5107 int qid = 7 + tid; 5108 5109 /* Stop TX scheduler while we're changing its configuration. */ 5110 iwn_prph_write(sc, IWN4965_SCHED_QUEUE_STATUS(qid), 5111 IWN4965_TXQ_STATUS_CHGACT); 5112 5113 /* Assign RA/TID translation to the queue. */ 5114 iwn_mem_write_2(sc, sc->sched_base + IWN4965_SCHED_TRANS_TBL(qid), 5115 wn->id << 4 | tid); 5116 5117 /* Enable chain-building mode for the queue. */ 5118 iwn_prph_setbits(sc, IWN4965_SCHED_QCHAIN_SEL, 1 << qid); 5119 5120 /* Set starting sequence number from the ADDBA request. */ 5121 IWN_WRITE(sc, IWN_HBUS_TARG_WRPTR, qid << 8 | (ssn & 0xff)); 5122 iwn_prph_write(sc, IWN4965_SCHED_QUEUE_RDPTR(qid), ssn); 5123 5124 /* Set scheduler window size. */ 5125 iwn_mem_write(sc, sc->sched_base + IWN4965_SCHED_QUEUE_OFFSET(qid), 5126 IWN_SCHED_WINSZ); 5127 /* Set scheduler frame limit. */ 5128 iwn_mem_write(sc, sc->sched_base + IWN4965_SCHED_QUEUE_OFFSET(qid) + 4, 5129 IWN_SCHED_LIMIT << 16); 5130 5131 /* Enable interrupts for the queue. */ 5132 iwn_prph_setbits(sc, IWN4965_SCHED_INTR_MASK, 1 << qid); 5133 5134 /* Mark the queue as active. */ 5135 iwn_prph_write(sc, IWN4965_SCHED_QUEUE_STATUS(qid), 5136 IWN4965_TXQ_STATUS_ACTIVE | IWN4965_TXQ_STATUS_AGGR_ENA | 5137 iwn_tid2fifo[tid] << 1); 5138 } 5139 5140 static void 5141 iwn4965_ampdu_tx_stop(struct iwn_softc *sc, uint8_t tid, uint16_t ssn) 5142 { 5143 int qid = 7 + tid; 5144 5145 /* Stop TX scheduler while we're changing its configuration. */ 5146 iwn_prph_write(sc, IWN4965_SCHED_QUEUE_STATUS(qid), 5147 IWN4965_TXQ_STATUS_CHGACT); 5148 5149 /* Set starting sequence number from the ADDBA request. */ 5150 IWN_WRITE(sc, IWN_HBUS_TARG_WRPTR, qid << 8 | (ssn & 0xff)); 5151 iwn_prph_write(sc, IWN4965_SCHED_QUEUE_RDPTR(qid), ssn); 5152 5153 /* Disable interrupts for the queue. */ 5154 iwn_prph_clrbits(sc, IWN4965_SCHED_INTR_MASK, 1 << qid); 5155 5156 /* Mark the queue as inactive. */ 5157 iwn_prph_write(sc, IWN4965_SCHED_QUEUE_STATUS(qid), 5158 IWN4965_TXQ_STATUS_INACTIVE | iwn_tid2fifo[tid] << 1); 5159 } 5160 5161 static void 5162 iwn5000_ampdu_tx_start(struct iwn_softc *sc, struct ieee80211_node *ni, 5163 uint8_t tid, uint16_t ssn) 5164 { 5165 struct iwn_node *wn = (void *)ni; 5166 int qid = 10 + tid; 5167 5168 /* Stop TX scheduler while we're changing its configuration. */ 5169 iwn_prph_write(sc, IWN5000_SCHED_QUEUE_STATUS(qid), 5170 IWN5000_TXQ_STATUS_CHGACT); 5171 5172 /* Assign RA/TID translation to the queue. */ 5173 iwn_mem_write_2(sc, sc->sched_base + IWN5000_SCHED_TRANS_TBL(qid), 5174 wn->id << 4 | tid); 5175 5176 /* Enable chain-building mode for the queue. */ 5177 iwn_prph_setbits(sc, IWN5000_SCHED_QCHAIN_SEL, 1 << qid); 5178 5179 /* Enable aggregation for the queue. */ 5180 iwn_prph_setbits(sc, IWN5000_SCHED_AGGR_SEL, 1 << qid); 5181 5182 /* Set starting sequence number from the ADDBA request. */ 5183 IWN_WRITE(sc, IWN_HBUS_TARG_WRPTR, qid << 8 | (ssn & 0xff)); 5184 iwn_prph_write(sc, IWN5000_SCHED_QUEUE_RDPTR(qid), ssn); 5185 5186 /* Set scheduler window size and frame limit. */ 5187 iwn_mem_write(sc, sc->sched_base + IWN5000_SCHED_QUEUE_OFFSET(qid) + 4, 5188 IWN_SCHED_LIMIT << 16 | IWN_SCHED_WINSZ); 5189 5190 /* Enable interrupts for the queue. */ 5191 iwn_prph_setbits(sc, IWN5000_SCHED_INTR_MASK, 1 << qid); 5192 5193 /* Mark the queue as active. */ 5194 iwn_prph_write(sc, IWN5000_SCHED_QUEUE_STATUS(qid), 5195 IWN5000_TXQ_STATUS_ACTIVE | iwn_tid2fifo[tid]); 5196 } 5197 5198 static void 5199 iwn5000_ampdu_tx_stop(struct iwn_softc *sc, uint8_t tid, uint16_t ssn) 5200 { 5201 int qid = 10 + tid; 5202 5203 /* Stop TX scheduler while we're changing its configuration. */ 5204 iwn_prph_write(sc, IWN5000_SCHED_QUEUE_STATUS(qid), 5205 IWN5000_TXQ_STATUS_CHGACT); 5206 5207 /* Disable aggregation for the queue. */ 5208 iwn_prph_clrbits(sc, IWN5000_SCHED_AGGR_SEL, 1 << qid); 5209 5210 /* Set starting sequence number from the ADDBA request. */ 5211 IWN_WRITE(sc, IWN_HBUS_TARG_WRPTR, qid << 8 | (ssn & 0xff)); 5212 iwn_prph_write(sc, IWN5000_SCHED_QUEUE_RDPTR(qid), ssn); 5213 5214 /* Disable interrupts for the queue. */ 5215 iwn_prph_clrbits(sc, IWN5000_SCHED_INTR_MASK, 1 << qid); 5216 5217 /* Mark the queue as inactive. */ 5218 iwn_prph_write(sc, IWN5000_SCHED_QUEUE_STATUS(qid), 5219 IWN5000_TXQ_STATUS_INACTIVE | iwn_tid2fifo[tid]); 5220 } 5221 #endif 5222 5223 /* 5224 * Query calibration tables from the initialization firmware. We do this 5225 * only once at first boot. Called from a process context. 5226 */ 5227 static int 5228 iwn5000_query_calibration(struct iwn_softc *sc) 5229 { 5230 struct iwn5000_calib_config cmd; 5231 int error; 5232 5233 memset(&cmd, 0, sizeof cmd); 5234 cmd.ucode.once.enable = 0xffffffff; 5235 cmd.ucode.once.start = 0xffffffff; 5236 cmd.ucode.once.send = 0xffffffff; 5237 cmd.ucode.flags = 0xffffffff; 5238 DPRINTF(sc, IWN_DEBUG_CALIBRATE, "%s: sending calibration query\n", 5239 __func__); 5240 error = iwn_cmd(sc, IWN5000_CMD_CALIB_CONFIG, &cmd, sizeof cmd, 0); 5241 if (error != 0) 5242 return error; 5243 5244 /* Wait at most two seconds for calibration to complete. */ 5245 if (!(sc->sc_flags & IWN_FLAG_CALIB_DONE)) 5246 error = msleep(sc, &sc->sc_mtx, PCATCH, "iwninit", 2 * hz); 5247 return error; 5248 } 5249 5250 /* 5251 * Send calibration results to the runtime firmware. These results were 5252 * obtained on first boot from the initialization firmware. 5253 */ 5254 static int 5255 iwn5000_send_calibration(struct iwn_softc *sc) 5256 { 5257 int idx, error; 5258 5259 for (idx = 0; idx < 5; idx++) { 5260 if (sc->calibcmd[idx].buf == NULL) 5261 continue; /* No results available. */ 5262 DPRINTF(sc, IWN_DEBUG_CALIBRATE, 5263 "send calibration result idx=%d len=%d\n", 5264 idx, sc->calibcmd[idx].len); 5265 error = iwn_cmd(sc, IWN_CMD_PHY_CALIB, sc->calibcmd[idx].buf, 5266 sc->calibcmd[idx].len, 0); 5267 if (error != 0) { 5268 device_printf(sc->sc_dev, 5269 "%s: could not send calibration result, error %d\n", 5270 __func__, error); 5271 return error; 5272 } 5273 } 5274 return 0; 5275 } 5276 5277 static int 5278 iwn5000_send_wimax_coex(struct iwn_softc *sc) 5279 { 5280 struct iwn5000_wimax_coex wimax; 5281 5282 #ifdef notyet 5283 if (sc->hw_type == IWN_HW_REV_TYPE_6050) { 5284 /* Enable WiMAX coexistence for combo adapters. */ 5285 wimax.flags = 5286 IWN_WIMAX_COEX_ASSOC_WA_UNMASK | 5287 IWN_WIMAX_COEX_UNASSOC_WA_UNMASK | 5288 IWN_WIMAX_COEX_STA_TABLE_VALID | 5289 IWN_WIMAX_COEX_ENABLE; 5290 memcpy(wimax.events, iwn6050_wimax_events, 5291 sizeof iwn6050_wimax_events); 5292 } else 5293 #endif 5294 { 5295 /* Disable WiMAX coexistence. */ 5296 wimax.flags = 0; 5297 memset(wimax.events, 0, sizeof wimax.events); 5298 } 5299 DPRINTF(sc, IWN_DEBUG_RESET, "%s: Configuring WiMAX coexistence\n", 5300 __func__); 5301 return iwn_cmd(sc, IWN5000_CMD_WIMAX_COEX, &wimax, sizeof wimax, 0); 5302 } 5303 5304 /* 5305 * This function is called after the runtime firmware notifies us of its 5306 * readiness (called in a process context.) 5307 */ 5308 static int 5309 iwn4965_post_alive(struct iwn_softc *sc) 5310 { 5311 int error, qid; 5312 5313 if ((error = iwn_nic_lock(sc)) != 0) 5314 return error; 5315 5316 /* Clear TX scheduler state in SRAM. */ 5317 sc->sched_base = iwn_prph_read(sc, IWN_SCHED_SRAM_ADDR); 5318 iwn_mem_set_region_4(sc, sc->sched_base + IWN4965_SCHED_CTX_OFF, 0, 5319 IWN4965_SCHED_CTX_LEN / sizeof (uint32_t)); 5320 5321 /* Set physical address of TX scheduler rings (1KB aligned.) */ 5322 iwn_prph_write(sc, IWN4965_SCHED_DRAM_ADDR, sc->sched_dma.paddr >> 10); 5323 5324 IWN_SETBITS(sc, IWN_FH_TX_CHICKEN, IWN_FH_TX_CHICKEN_SCHED_RETRY); 5325 5326 /* Disable chain mode for all our 16 queues. */ 5327 iwn_prph_write(sc, IWN4965_SCHED_QCHAIN_SEL, 0); 5328 5329 for (qid = 0; qid < IWN4965_NTXQUEUES; qid++) { 5330 iwn_prph_write(sc, IWN4965_SCHED_QUEUE_RDPTR(qid), 0); 5331 IWN_WRITE(sc, IWN_HBUS_TARG_WRPTR, qid << 8 | 0); 5332 5333 /* Set scheduler window size. */ 5334 iwn_mem_write(sc, sc->sched_base + 5335 IWN4965_SCHED_QUEUE_OFFSET(qid), IWN_SCHED_WINSZ); 5336 /* Set scheduler frame limit. */ 5337 iwn_mem_write(sc, sc->sched_base + 5338 IWN4965_SCHED_QUEUE_OFFSET(qid) + 4, 5339 IWN_SCHED_LIMIT << 16); 5340 } 5341 5342 /* Enable interrupts for all our 16 queues. */ 5343 iwn_prph_write(sc, IWN4965_SCHED_INTR_MASK, 0xffff); 5344 /* Identify TX FIFO rings (0-7). */ 5345 iwn_prph_write(sc, IWN4965_SCHED_TXFACT, 0xff); 5346 5347 /* Mark TX rings (4 EDCA + cmd + 2 HCCA) as active. */ 5348 for (qid = 0; qid < 7; qid++) { 5349 static uint8_t qid2fifo[] = { 3, 2, 1, 0, 4, 5, 6 }; 5350 iwn_prph_write(sc, IWN4965_SCHED_QUEUE_STATUS(qid), 5351 IWN4965_TXQ_STATUS_ACTIVE | qid2fifo[qid] << 1); 5352 } 5353 iwn_nic_unlock(sc); 5354 return 0; 5355 } 5356 5357 /* 5358 * This function is called after the initialization or runtime firmware 5359 * notifies us of its readiness (called in a process context.) 5360 */ 5361 static int 5362 iwn5000_post_alive(struct iwn_softc *sc) 5363 { 5364 int error, qid; 5365 5366 /* Switch to using ICT interrupt mode. */ 5367 iwn5000_ict_reset(sc); 5368 5369 error = iwn_nic_lock(sc); 5370 if (error != 0) 5371 return error; 5372 5373 /* Clear TX scheduler state in SRAM. */ 5374 sc->sched_base = iwn_prph_read(sc, IWN_SCHED_SRAM_ADDR); 5375 iwn_mem_set_region_4(sc, sc->sched_base + IWN5000_SCHED_CTX_OFF, 0, 5376 IWN5000_SCHED_CTX_LEN / sizeof (uint32_t)); 5377 5378 /* Set physical address of TX scheduler rings (1KB aligned.) */ 5379 iwn_prph_write(sc, IWN5000_SCHED_DRAM_ADDR, sc->sched_dma.paddr >> 10); 5380 5381 IWN_SETBITS(sc, IWN_FH_TX_CHICKEN, IWN_FH_TX_CHICKEN_SCHED_RETRY); 5382 5383 /* Enable chain mode for all queues, except command queue. */ 5384 iwn_prph_write(sc, IWN5000_SCHED_QCHAIN_SEL, 0xfffef); 5385 iwn_prph_write(sc, IWN5000_SCHED_AGGR_SEL, 0); 5386 5387 for (qid = 0; qid < IWN5000_NTXQUEUES; qid++) { 5388 iwn_prph_write(sc, IWN5000_SCHED_QUEUE_RDPTR(qid), 0); 5389 IWN_WRITE(sc, IWN_HBUS_TARG_WRPTR, qid << 8 | 0); 5390 5391 iwn_mem_write(sc, sc->sched_base + 5392 IWN5000_SCHED_QUEUE_OFFSET(qid), 0); 5393 /* Set scheduler window size and frame limit. */ 5394 iwn_mem_write(sc, sc->sched_base + 5395 IWN5000_SCHED_QUEUE_OFFSET(qid) + 4, 5396 IWN_SCHED_LIMIT << 16 | IWN_SCHED_WINSZ); 5397 } 5398 5399 /* Enable interrupts for all our 20 queues. */ 5400 iwn_prph_write(sc, IWN5000_SCHED_INTR_MASK, 0xfffff); 5401 /* Identify TX FIFO rings (0-7). */ 5402 iwn_prph_write(sc, IWN5000_SCHED_TXFACT, 0xff); 5403 5404 /* Mark TX rings (4 EDCA + cmd + 2 HCCA) as active. */ 5405 for (qid = 0; qid < 7; qid++) { 5406 static uint8_t qid2fifo[] = { 3, 2, 1, 0, 7, 5, 6 }; 5407 iwn_prph_write(sc, IWN5000_SCHED_QUEUE_STATUS(qid), 5408 IWN5000_TXQ_STATUS_ACTIVE | qid2fifo[qid]); 5409 } 5410 iwn_nic_unlock(sc); 5411 5412 /* Configure WiMAX coexistence for combo adapters. */ 5413 error = iwn5000_send_wimax_coex(sc); 5414 if (error != 0) { 5415 device_printf(sc->sc_dev, 5416 "%s: could not configure WiMAX coexistence, error %d\n", 5417 __func__, error); 5418 return error; 5419 } 5420 if (sc->hw_type != IWN_HW_REV_TYPE_5150) { 5421 struct iwn5000_phy_calib_crystal cmd; 5422 5423 /* Perform crystal calibration. */ 5424 memset(&cmd, 0, sizeof cmd); 5425 cmd.code = IWN5000_PHY_CALIB_CRYSTAL; 5426 cmd.ngroups = 1; 5427 cmd.isvalid = 1; 5428 cmd.cap_pin[0] = le32toh(sc->eeprom_crystal) & 0xff; 5429 cmd.cap_pin[1] = (le32toh(sc->eeprom_crystal) >> 16) & 0xff; 5430 DPRINTF(sc, IWN_DEBUG_CALIBRATE, 5431 "sending crystal calibration %d, %d\n", 5432 cmd.cap_pin[0], cmd.cap_pin[1]); 5433 error = iwn_cmd(sc, IWN_CMD_PHY_CALIB, &cmd, sizeof cmd, 0); 5434 if (error != 0) { 5435 device_printf(sc->sc_dev, 5436 "%s: crystal calibration failed, error %d\n", 5437 __func__, error); 5438 return error; 5439 } 5440 } 5441 if (!(sc->sc_flags & IWN_FLAG_CALIB_DONE)) { 5442 /* Query calibration from the initialization firmware. */ 5443 error = iwn5000_query_calibration(sc); 5444 if (error != 0) { 5445 device_printf(sc->sc_dev, 5446 "%s: could not query calibration, error %d\n", 5447 __func__, error); 5448 return error; 5449 } 5450 /* 5451 * We have the calibration results now, reboot with the 5452 * runtime firmware (call ourselves recursively!) 5453 */ 5454 iwn_hw_stop(sc); 5455 error = iwn_hw_init(sc); 5456 } else { 5457 /* Send calibration results to runtime firmware. */ 5458 error = iwn5000_send_calibration(sc); 5459 } 5460 return error; 5461 } 5462 5463 /* 5464 * The firmware boot code is small and is intended to be copied directly into 5465 * the NIC internal memory (no DMA transfer.) 5466 */ 5467 static int 5468 iwn4965_load_bootcode(struct iwn_softc *sc, const uint8_t *ucode, int size) 5469 { 5470 int error, ntries; 5471 5472 size /= sizeof (uint32_t); 5473 5474 error = iwn_nic_lock(sc); 5475 if (error != 0) 5476 return error; 5477 5478 /* Copy microcode image into NIC memory. */ 5479 iwn_prph_write_region_4(sc, IWN_BSM_SRAM_BASE, 5480 (const uint32_t *)ucode, size); 5481 5482 iwn_prph_write(sc, IWN_BSM_WR_MEM_SRC, 0); 5483 iwn_prph_write(sc, IWN_BSM_WR_MEM_DST, IWN_FW_TEXT_BASE); 5484 iwn_prph_write(sc, IWN_BSM_WR_DWCOUNT, size); 5485 5486 /* Start boot load now. */ 5487 iwn_prph_write(sc, IWN_BSM_WR_CTRL, IWN_BSM_WR_CTRL_START); 5488 5489 /* Wait for transfer to complete. */ 5490 for (ntries = 0; ntries < 1000; ntries++) { 5491 if (!(iwn_prph_read(sc, IWN_BSM_WR_CTRL) & 5492 IWN_BSM_WR_CTRL_START)) 5493 break; 5494 DELAY(10); 5495 } 5496 if (ntries == 1000) { 5497 device_printf(sc->sc_dev, "%s: could not load boot firmware\n", 5498 __func__); 5499 iwn_nic_unlock(sc); 5500 return ETIMEDOUT; 5501 } 5502 5503 /* Enable boot after power up. */ 5504 iwn_prph_write(sc, IWN_BSM_WR_CTRL, IWN_BSM_WR_CTRL_START_EN); 5505 5506 iwn_nic_unlock(sc); 5507 return 0; 5508 } 5509 5510 static int 5511 iwn4965_load_firmware(struct iwn_softc *sc) 5512 { 5513 struct iwn_fw_info *fw = &sc->fw; 5514 struct iwn_dma_info *dma = &sc->fw_dma; 5515 int error; 5516 5517 /* Copy initialization sections into pre-allocated DMA-safe memory. */ 5518 memcpy(dma->vaddr, fw->init.data, fw->init.datasz); 5519 bus_dmamap_sync(sc->fw_dma.tag, dma->map, BUS_DMASYNC_PREWRITE); 5520 memcpy(dma->vaddr + IWN4965_FW_DATA_MAXSZ, 5521 fw->init.text, fw->init.textsz); 5522 bus_dmamap_sync(sc->fw_dma.tag, dma->map, BUS_DMASYNC_PREWRITE); 5523 5524 /* Tell adapter where to find initialization sections. */ 5525 error = iwn_nic_lock(sc); 5526 if (error != 0) 5527 return error; 5528 iwn_prph_write(sc, IWN_BSM_DRAM_DATA_ADDR, dma->paddr >> 4); 5529 iwn_prph_write(sc, IWN_BSM_DRAM_DATA_SIZE, fw->init.datasz); 5530 iwn_prph_write(sc, IWN_BSM_DRAM_TEXT_ADDR, 5531 (dma->paddr + IWN4965_FW_DATA_MAXSZ) >> 4); 5532 iwn_prph_write(sc, IWN_BSM_DRAM_TEXT_SIZE, fw->init.textsz); 5533 iwn_nic_unlock(sc); 5534 5535 /* Load firmware boot code. */ 5536 error = iwn4965_load_bootcode(sc, fw->boot.text, fw->boot.textsz); 5537 if (error != 0) { 5538 device_printf(sc->sc_dev, "%s: could not load boot firmware\n", 5539 __func__); 5540 return error; 5541 } 5542 /* Now press "execute". */ 5543 IWN_WRITE(sc, IWN_RESET, 0); 5544 5545 /* Wait at most one second for first alive notification. */ 5546 error = msleep(sc, &sc->sc_mtx, PCATCH, "iwninit", hz); 5547 if (error) { 5548 device_printf(sc->sc_dev, 5549 "%s: timeout waiting for adapter to initialize, error %d\n", 5550 __func__, error); 5551 return error; 5552 } 5553 5554 /* Retrieve current temperature for initial TX power calibration. */ 5555 sc->rawtemp = sc->ucode_info.temp[3].chan20MHz; 5556 sc->temp = iwn4965_get_temperature(sc); 5557 5558 /* Copy runtime sections into pre-allocated DMA-safe memory. */ 5559 memcpy(dma->vaddr, fw->main.data, fw->main.datasz); 5560 bus_dmamap_sync(sc->fw_dma.tag, dma->map, BUS_DMASYNC_PREWRITE); 5561 memcpy(dma->vaddr + IWN4965_FW_DATA_MAXSZ, 5562 fw->main.text, fw->main.textsz); 5563 bus_dmamap_sync(sc->fw_dma.tag, dma->map, BUS_DMASYNC_PREWRITE); 5564 5565 /* Tell adapter where to find runtime sections. */ 5566 error = iwn_nic_lock(sc); 5567 if (error != 0) 5568 return error; 5569 5570 iwn_prph_write(sc, IWN_BSM_DRAM_DATA_ADDR, dma->paddr >> 4); 5571 iwn_prph_write(sc, IWN_BSM_DRAM_DATA_SIZE, fw->main.datasz); 5572 iwn_prph_write(sc, IWN_BSM_DRAM_TEXT_ADDR, 5573 (dma->paddr + IWN4965_FW_DATA_MAXSZ) >> 4); 5574 iwn_prph_write(sc, IWN_BSM_DRAM_TEXT_SIZE, 5575 IWN_FW_UPDATED | fw->main.textsz); 5576 iwn_nic_unlock(sc); 5577 5578 return 0; 5579 } 5580 5581 static int 5582 iwn5000_load_firmware_section(struct iwn_softc *sc, uint32_t dst, 5583 const uint8_t *section, int size) 5584 { 5585 struct iwn_dma_info *dma = &sc->fw_dma; 5586 int error; 5587 5588 /* Copy firmware section into pre-allocated DMA-safe memory. */ 5589 memcpy(dma->vaddr, section, size); 5590 bus_dmamap_sync(sc->fw_dma.tag, dma->map, BUS_DMASYNC_PREWRITE); 5591 5592 error = iwn_nic_lock(sc); 5593 if (error != 0) 5594 return error; 5595 5596 IWN_WRITE(sc, IWN_FH_TX_CONFIG(IWN_SRVC_DMACHNL), 5597 IWN_FH_TX_CONFIG_DMA_PAUSE); 5598 5599 IWN_WRITE(sc, IWN_FH_SRAM_ADDR(IWN_SRVC_DMACHNL), dst); 5600 IWN_WRITE(sc, IWN_FH_TFBD_CTRL0(IWN_SRVC_DMACHNL), 5601 IWN_LOADDR(dma->paddr)); 5602 IWN_WRITE(sc, IWN_FH_TFBD_CTRL1(IWN_SRVC_DMACHNL), 5603 IWN_HIADDR(dma->paddr) << 28 | size); 5604 IWN_WRITE(sc, IWN_FH_TXBUF_STATUS(IWN_SRVC_DMACHNL), 5605 IWN_FH_TXBUF_STATUS_TBNUM(1) | 5606 IWN_FH_TXBUF_STATUS_TBIDX(1) | 5607 IWN_FH_TXBUF_STATUS_TFBD_VALID); 5608 5609 /* Kick Flow Handler to start DMA transfer. */ 5610 IWN_WRITE(sc, IWN_FH_TX_CONFIG(IWN_SRVC_DMACHNL), 5611 IWN_FH_TX_CONFIG_DMA_ENA | IWN_FH_TX_CONFIG_CIRQ_HOST_ENDTFD); 5612 5613 iwn_nic_unlock(sc); 5614 5615 /* Wait at most five seconds for FH DMA transfer to complete. */ 5616 return msleep(sc, &sc->sc_mtx, PCATCH, "iwninit", hz); 5617 } 5618 5619 static int 5620 iwn5000_load_firmware(struct iwn_softc *sc) 5621 { 5622 struct iwn_fw_part *fw; 5623 int error; 5624 5625 /* Load the initialization firmware on first boot only. */ 5626 fw = (sc->sc_flags & IWN_FLAG_CALIB_DONE) ? 5627 &sc->fw.main : &sc->fw.init; 5628 5629 error = iwn5000_load_firmware_section(sc, IWN_FW_TEXT_BASE, 5630 fw->text, fw->textsz); 5631 if (error != 0) { 5632 device_printf(sc->sc_dev, 5633 "%s: could not load firmware %s section, error %d\n", 5634 __func__, ".text", error); 5635 return error; 5636 } 5637 error = iwn5000_load_firmware_section(sc, IWN_FW_DATA_BASE, 5638 fw->data, fw->datasz); 5639 if (error != 0) { 5640 device_printf(sc->sc_dev, 5641 "%s: could not load firmware %s section, error %d\n", 5642 __func__, ".data", error); 5643 return error; 5644 } 5645 5646 /* Now press "execute". */ 5647 IWN_WRITE(sc, IWN_RESET, 0); 5648 return 0; 5649 } 5650 5651 /* 5652 * Extract text and data sections from a legacy firmware image. 5653 */ 5654 static int 5655 iwn_read_firmware_leg(struct iwn_softc *sc, struct iwn_fw_info *fw) 5656 { 5657 const uint32_t *ptr; 5658 size_t hdrlen = 24; 5659 uint32_t rev; 5660 5661 ptr = (const uint32_t *)sc->fw_fp->data; 5662 rev = le32toh(*ptr++); 5663 5664 /* Check firmware API version. */ 5665 if (IWN_FW_API(rev) <= 1) { 5666 device_printf(sc->sc_dev, 5667 "%s: bad firmware, need API version >=2\n", __func__); 5668 return EINVAL; 5669 } 5670 if (IWN_FW_API(rev) >= 3) { 5671 /* Skip build number (version 2 header). */ 5672 hdrlen += 4; 5673 ptr++; 5674 } 5675 if (fw->size < hdrlen) { 5676 device_printf(sc->sc_dev, 5677 "%s: firmware file too short: %zu bytes\n", 5678 __func__, fw->size); 5679 return EINVAL; 5680 } 5681 fw->main.textsz = le32toh(*ptr++); 5682 fw->main.datasz = le32toh(*ptr++); 5683 fw->init.textsz = le32toh(*ptr++); 5684 fw->init.datasz = le32toh(*ptr++); 5685 fw->boot.textsz = le32toh(*ptr++); 5686 5687 /* Check that all firmware sections fit. */ 5688 if (fw->size < hdrlen + fw->main.textsz + fw->main.datasz + 5689 fw->init.textsz + fw->init.datasz + fw->boot.textsz) { 5690 device_printf(sc->sc_dev, 5691 "%s: firmware file too short: %zu bytes\n", 5692 __func__, fw->size); 5693 return EINVAL; 5694 } 5695 5696 /* Get pointers to firmware sections. */ 5697 fw->main.text = (const uint8_t *)ptr; 5698 fw->main.data = fw->main.text + fw->main.textsz; 5699 fw->init.text = fw->main.data + fw->main.datasz; 5700 fw->init.data = fw->init.text + fw->init.textsz; 5701 fw->boot.text = fw->init.data + fw->init.datasz; 5702 5703 return 0; 5704 } 5705 5706 /* 5707 * Extract text and data sections from a TLV firmware image. 5708 */ 5709 int 5710 iwn_read_firmware_tlv(struct iwn_softc *sc, struct iwn_fw_info *fw, 5711 uint16_t alt) 5712 { 5713 const struct iwn_fw_tlv_hdr *hdr; 5714 const struct iwn_fw_tlv *tlv; 5715 const uint8_t *ptr, *end; 5716 uint64_t altmask; 5717 uint32_t len; 5718 5719 if (fw->size < sizeof (*hdr)) { 5720 device_printf(sc->sc_dev, 5721 "%s: firmware file too short: %zu bytes\n", 5722 __func__, fw->size); 5723 return EINVAL; 5724 } 5725 hdr = (const struct iwn_fw_tlv_hdr *)fw->data; 5726 if (hdr->signature != htole32(IWN_FW_SIGNATURE)) { 5727 device_printf(sc->sc_dev, 5728 "%s: bad firmware file signature 0x%08x\n", 5729 __func__, le32toh(hdr->signature)); 5730 return EINVAL; 5731 } 5732 5733 /* 5734 * Select the closest supported alternative that is less than 5735 * or equal to the specified one. 5736 */ 5737 altmask = le64toh(hdr->altmask); 5738 while (alt > 0 && !(altmask & (1ULL << alt))) 5739 alt--; /* Downgrade. */ 5740 5741 ptr = (const uint8_t *)(hdr + 1); 5742 end = (const uint8_t *)(fw->data + fw->size); 5743 5744 /* Parse type-length-value fields. */ 5745 while (ptr + sizeof (*tlv) <= end) { 5746 tlv = (const struct iwn_fw_tlv *)ptr; 5747 len = le32toh(tlv->len); 5748 5749 ptr += sizeof (*tlv); 5750 if (ptr + len > end) { 5751 device_printf(sc->sc_dev, 5752 "%s: firmware file too short: %zu bytes\n", 5753 __func__, fw->size); 5754 return EINVAL; 5755 } 5756 /* Skip other alternatives. */ 5757 if (tlv->alt != 0 && tlv->alt != htole16(alt)) 5758 goto next; 5759 5760 switch (le16toh(tlv->type)) { 5761 case IWN_FW_TLV_MAIN_TEXT: 5762 fw->main.text = ptr; 5763 fw->main.textsz = len; 5764 break; 5765 case IWN_FW_TLV_MAIN_DATA: 5766 fw->main.data = ptr; 5767 fw->main.datasz = len; 5768 break; 5769 case IWN_FW_TLV_INIT_TEXT: 5770 fw->init.text = ptr; 5771 fw->init.textsz = len; 5772 break; 5773 case IWN_FW_TLV_INIT_DATA: 5774 fw->init.data = ptr; 5775 fw->init.datasz = len; 5776 break; 5777 case IWN_FW_TLV_BOOT_TEXT: 5778 fw->boot.text = ptr; 5779 fw->boot.textsz = len; 5780 break; 5781 default: 5782 DPRINTF(sc, IWN_DEBUG_RESET, 5783 "%s: TLV type %d not handled\n", 5784 __func__, le16toh(tlv->type)); 5785 break; 5786 } 5787 next: /* TLV fields are 32-bit aligned. */ 5788 ptr += (len + 3) & ~3; 5789 } 5790 return 0; 5791 } 5792 5793 static int 5794 iwn_read_firmware(struct iwn_softc *sc) 5795 { 5796 const struct iwn_hal *hal = sc->sc_hal; 5797 struct iwn_fw_info *fw = &sc->fw; 5798 int error; 5799 5800 IWN_UNLOCK(sc); 5801 5802 memset(fw, 0, sizeof (*fw)); 5803 5804 /* Read firmware image from filesystem. */ 5805 sc->fw_fp = firmware_get(sc->fwname); 5806 if (sc->fw_fp == NULL) { 5807 device_printf(sc->sc_dev, 5808 "%s: could not load firmare image \"%s\"\n", __func__, 5809 sc->fwname); 5810 IWN_LOCK(sc); 5811 return EINVAL; 5812 } 5813 IWN_LOCK(sc); 5814 5815 fw->size = sc->fw_fp->datasize; 5816 fw->data = (const uint8_t *)sc->fw_fp->data; 5817 if (fw->size < sizeof (uint32_t)) { 5818 device_printf(sc->sc_dev, 5819 "%s: firmware file too short: %zu bytes\n", 5820 __func__, fw->size); 5821 return EINVAL; 5822 } 5823 5824 /* Retrieve text and data sections. */ 5825 if (*(const uint32_t *)fw->data != 0) /* Legacy image. */ 5826 error = iwn_read_firmware_leg(sc, fw); 5827 else 5828 error = iwn_read_firmware_tlv(sc, fw, 1); 5829 if (error != 0) { 5830 device_printf(sc->sc_dev, 5831 "%s: could not read firmware sections\n", __func__); 5832 return error; 5833 } 5834 5835 /* Make sure text and data sections fit in hardware memory. */ 5836 if (fw->main.textsz > hal->fw_text_maxsz || 5837 fw->main.datasz > hal->fw_data_maxsz || 5838 fw->init.textsz > hal->fw_text_maxsz || 5839 fw->init.datasz > hal->fw_data_maxsz || 5840 fw->boot.textsz > IWN_FW_BOOT_TEXT_MAXSZ || 5841 (fw->boot.textsz & 3) != 0) { 5842 device_printf(sc->sc_dev, 5843 "%s: firmware sections too large\n", __func__); 5844 return EINVAL; 5845 } 5846 5847 /* We can proceed with loading the firmware. */ 5848 return 0; 5849 } 5850 5851 static int 5852 iwn_clock_wait(struct iwn_softc *sc) 5853 { 5854 int ntries; 5855 5856 /* Set "initialization complete" bit. */ 5857 IWN_SETBITS(sc, IWN_GP_CNTRL, IWN_GP_CNTRL_INIT_DONE); 5858 5859 /* Wait for clock stabilization. */ 5860 for (ntries = 0; ntries < 2500; ntries++) { 5861 if (IWN_READ(sc, IWN_GP_CNTRL) & IWN_GP_CNTRL_MAC_CLOCK_READY) 5862 return 0; 5863 DELAY(10); 5864 } 5865 device_printf(sc->sc_dev, 5866 "%s: timeout waiting for clock stabilization\n", __func__); 5867 return ETIMEDOUT; 5868 } 5869 5870 static int 5871 iwn_apm_init(struct iwn_softc *sc) 5872 { 5873 uint32_t tmp; 5874 int error; 5875 5876 /* Disable L0s exit timer (NMI bug workaround.) */ 5877 IWN_SETBITS(sc, IWN_GIO_CHICKEN, IWN_GIO_CHICKEN_DIS_L0S_TIMER); 5878 /* Don't wait for ICH L0s (ICH bug workaround.) */ 5879 IWN_SETBITS(sc, IWN_GIO_CHICKEN, IWN_GIO_CHICKEN_L1A_NO_L0S_RX); 5880 5881 /* Set FH wait threshold to max (HW bug under stress workaround.) */ 5882 IWN_SETBITS(sc, IWN_DBG_HPET_MEM, 0xffff0000); 5883 5884 /* Enable HAP INTA to move adapter from L1a to L0s. */ 5885 IWN_SETBITS(sc, IWN_HW_IF_CONFIG, IWN_HW_IF_CONFIG_HAP_WAKE_L1A); 5886 5887 /* Retrieve PCIe Active State Power Management (ASPM). */ 5888 tmp = pci_read_config(sc->sc_dev, sc->sc_cap_off + 0x10, 1); 5889 /* Workaround for HW instability in PCIe L0->L0s->L1 transition. */ 5890 if (tmp & 0x02) /* L1 Entry enabled. */ 5891 IWN_SETBITS(sc, IWN_GIO, IWN_GIO_L0S_ENA); 5892 else 5893 IWN_CLRBITS(sc, IWN_GIO, IWN_GIO_L0S_ENA); 5894 5895 if (sc->hw_type != IWN_HW_REV_TYPE_4965 && 5896 sc->hw_type <= IWN_HW_REV_TYPE_1000) 5897 IWN_SETBITS(sc, IWN_ANA_PLL, IWN_ANA_PLL_INIT); 5898 5899 /* Wait for clock stabilization before accessing prph. */ 5900 error = iwn_clock_wait(sc); 5901 if (error != 0) 5902 return error; 5903 5904 error = iwn_nic_lock(sc); 5905 if (error != 0) 5906 return error; 5907 5908 if (sc->hw_type == IWN_HW_REV_TYPE_4965) { 5909 /* Enable DMA and BSM (Bootstrap State Machine.) */ 5910 iwn_prph_write(sc, IWN_APMG_CLK_EN, 5911 IWN_APMG_CLK_CTRL_DMA_CLK_RQT | 5912 IWN_APMG_CLK_CTRL_BSM_CLK_RQT); 5913 } else { 5914 /* Enable DMA. */ 5915 iwn_prph_write(sc, IWN_APMG_CLK_EN, 5916 IWN_APMG_CLK_CTRL_DMA_CLK_RQT); 5917 } 5918 DELAY(20); 5919 5920 /* Disable L1-Active. */ 5921 iwn_prph_setbits(sc, IWN_APMG_PCI_STT, IWN_APMG_PCI_STT_L1A_DIS); 5922 iwn_nic_unlock(sc); 5923 5924 return 0; 5925 } 5926 5927 static void 5928 iwn_apm_stop_master(struct iwn_softc *sc) 5929 { 5930 int ntries; 5931 5932 /* Stop busmaster DMA activity. */ 5933 IWN_SETBITS(sc, IWN_RESET, IWN_RESET_STOP_MASTER); 5934 for (ntries = 0; ntries < 100; ntries++) { 5935 if (IWN_READ(sc, IWN_RESET) & IWN_RESET_MASTER_DISABLED) 5936 return; 5937 DELAY(10); 5938 } 5939 device_printf(sc->sc_dev, "%s: timeout waiting for master\n", 5940 __func__); 5941 } 5942 5943 static void 5944 iwn_apm_stop(struct iwn_softc *sc) 5945 { 5946 iwn_apm_stop_master(sc); 5947 5948 /* Reset the entire device. */ 5949 IWN_SETBITS(sc, IWN_RESET, IWN_RESET_SW); 5950 DELAY(10); 5951 /* Clear "initialization complete" bit. */ 5952 IWN_CLRBITS(sc, IWN_GP_CNTRL, IWN_GP_CNTRL_INIT_DONE); 5953 } 5954 5955 static int 5956 iwn4965_nic_config(struct iwn_softc *sc) 5957 { 5958 if (IWN_RFCFG_TYPE(sc->rfcfg) == 1) { 5959 /* 5960 * I don't believe this to be correct but this is what the 5961 * vendor driver is doing. Probably the bits should not be 5962 * shifted in IWN_RFCFG_*. 5963 */ 5964 IWN_SETBITS(sc, IWN_HW_IF_CONFIG, 5965 IWN_RFCFG_TYPE(sc->rfcfg) | 5966 IWN_RFCFG_STEP(sc->rfcfg) | 5967 IWN_RFCFG_DASH(sc->rfcfg)); 5968 } 5969 IWN_SETBITS(sc, IWN_HW_IF_CONFIG, 5970 IWN_HW_IF_CONFIG_RADIO_SI | IWN_HW_IF_CONFIG_MAC_SI); 5971 return 0; 5972 } 5973 5974 static int 5975 iwn5000_nic_config(struct iwn_softc *sc) 5976 { 5977 uint32_t tmp; 5978 int error; 5979 5980 if (IWN_RFCFG_TYPE(sc->rfcfg) < 3) { 5981 IWN_SETBITS(sc, IWN_HW_IF_CONFIG, 5982 IWN_RFCFG_TYPE(sc->rfcfg) | 5983 IWN_RFCFG_STEP(sc->rfcfg) | 5984 IWN_RFCFG_DASH(sc->rfcfg)); 5985 } 5986 IWN_SETBITS(sc, IWN_HW_IF_CONFIG, 5987 IWN_HW_IF_CONFIG_RADIO_SI | IWN_HW_IF_CONFIG_MAC_SI); 5988 5989 error = iwn_nic_lock(sc); 5990 if (error != 0) 5991 return error; 5992 iwn_prph_setbits(sc, IWN_APMG_PS, IWN_APMG_PS_EARLY_PWROFF_DIS); 5993 5994 if (sc->hw_type == IWN_HW_REV_TYPE_1000) { 5995 /* 5996 * Select first Switching Voltage Regulator (1.32V) to 5997 * solve a stability issue related to noisy DC2DC line 5998 * in the silicon of 1000 Series. 5999 */ 6000 tmp = iwn_prph_read(sc, IWN_APMG_DIGITAL_SVR); 6001 tmp &= ~IWN_APMG_DIGITAL_SVR_VOLTAGE_MASK; 6002 tmp |= IWN_APMG_DIGITAL_SVR_VOLTAGE_1_32; 6003 iwn_prph_write(sc, IWN_APMG_DIGITAL_SVR, tmp); 6004 } 6005 iwn_nic_unlock(sc); 6006 6007 if (sc->sc_flags & IWN_FLAG_INTERNAL_PA) { 6008 /* Use internal power amplifier only. */ 6009 IWN_WRITE(sc, IWN_GP_DRIVER, IWN_GP_DRIVER_RADIO_2X2_IPA); 6010 } 6011 if (sc->hw_type == IWN_HW_REV_TYPE_6050 && sc->calib_ver >= 6) { 6012 /* Indicate that ROM calibration version is >=6. */ 6013 IWN_SETBITS(sc, IWN_GP_DRIVER, IWN_GP_DRIVER_CALIB_VER6); 6014 } 6015 return 0; 6016 } 6017 6018 /* 6019 * Take NIC ownership over Intel Active Management Technology (AMT). 6020 */ 6021 static int 6022 iwn_hw_prepare(struct iwn_softc *sc) 6023 { 6024 int ntries; 6025 6026 /* Check if hardware is ready. */ 6027 IWN_SETBITS(sc, IWN_HW_IF_CONFIG, IWN_HW_IF_CONFIG_NIC_READY); 6028 for (ntries = 0; ntries < 5; ntries++) { 6029 if (IWN_READ(sc, IWN_HW_IF_CONFIG) & 6030 IWN_HW_IF_CONFIG_NIC_READY) 6031 return 0; 6032 DELAY(10); 6033 } 6034 6035 /* Hardware not ready, force into ready state. */ 6036 IWN_SETBITS(sc, IWN_HW_IF_CONFIG, IWN_HW_IF_CONFIG_PREPARE); 6037 for (ntries = 0; ntries < 15000; ntries++) { 6038 if (!(IWN_READ(sc, IWN_HW_IF_CONFIG) & 6039 IWN_HW_IF_CONFIG_PREPARE_DONE)) 6040 break; 6041 DELAY(10); 6042 } 6043 if (ntries == 15000) 6044 return ETIMEDOUT; 6045 6046 /* Hardware should be ready now. */ 6047 IWN_SETBITS(sc, IWN_HW_IF_CONFIG, IWN_HW_IF_CONFIG_NIC_READY); 6048 for (ntries = 0; ntries < 5; ntries++) { 6049 if (IWN_READ(sc, IWN_HW_IF_CONFIG) & 6050 IWN_HW_IF_CONFIG_NIC_READY) 6051 return 0; 6052 DELAY(10); 6053 } 6054 return ETIMEDOUT; 6055 } 6056 6057 static int 6058 iwn_hw_init(struct iwn_softc *sc) 6059 { 6060 const struct iwn_hal *hal = sc->sc_hal; 6061 int error, chnl, qid; 6062 6063 /* Clear pending interrupts. */ 6064 IWN_WRITE(sc, IWN_INT, 0xffffffff); 6065 6066 error = iwn_apm_init(sc); 6067 if (error != 0) { 6068 device_printf(sc->sc_dev, 6069 "%s: could not power ON adapter, error %d\n", 6070 __func__, error); 6071 return error; 6072 } 6073 6074 /* Select VMAIN power source. */ 6075 error = iwn_nic_lock(sc); 6076 if (error != 0) 6077 return error; 6078 iwn_prph_clrbits(sc, IWN_APMG_PS, IWN_APMG_PS_PWR_SRC_MASK); 6079 iwn_nic_unlock(sc); 6080 6081 /* Perform adapter-specific initialization. */ 6082 error = hal->nic_config(sc); 6083 if (error != 0) 6084 return error; 6085 6086 /* Initialize RX ring. */ 6087 error = iwn_nic_lock(sc); 6088 if (error != 0) 6089 return error; 6090 IWN_WRITE(sc, IWN_FH_RX_CONFIG, 0); 6091 IWN_WRITE(sc, IWN_FH_RX_WPTR, 0); 6092 /* Set physical address of RX ring (256-byte aligned.) */ 6093 IWN_WRITE(sc, IWN_FH_RX_BASE, sc->rxq.desc_dma.paddr >> 8); 6094 /* Set physical address of RX status (16-byte aligned.) */ 6095 IWN_WRITE(sc, IWN_FH_STATUS_WPTR, sc->rxq.stat_dma.paddr >> 4); 6096 /* Enable RX. */ 6097 IWN_WRITE(sc, IWN_FH_RX_CONFIG, 6098 IWN_FH_RX_CONFIG_ENA | 6099 IWN_FH_RX_CONFIG_IGN_RXF_EMPTY | /* HW bug workaround */ 6100 IWN_FH_RX_CONFIG_IRQ_DST_HOST | 6101 IWN_FH_RX_CONFIG_SINGLE_FRAME | 6102 IWN_FH_RX_CONFIG_RB_TIMEOUT(0) | 6103 IWN_FH_RX_CONFIG_NRBD(IWN_RX_RING_COUNT_LOG)); 6104 iwn_nic_unlock(sc); 6105 IWN_WRITE(sc, IWN_FH_RX_WPTR, (IWN_RX_RING_COUNT - 1) & ~7); 6106 6107 error = iwn_nic_lock(sc); 6108 if (error != 0) 6109 return error; 6110 6111 /* Initialize TX scheduler. */ 6112 iwn_prph_write(sc, hal->sched_txfact_addr, 0); 6113 6114 /* Set physical address of "keep warm" page (16-byte aligned.) */ 6115 IWN_WRITE(sc, IWN_FH_KW_ADDR, sc->kw_dma.paddr >> 4); 6116 6117 /* Initialize TX rings. */ 6118 for (qid = 0; qid < hal->ntxqs; qid++) { 6119 struct iwn_tx_ring *txq = &sc->txq[qid]; 6120 6121 /* Set physical address of TX ring (256-byte aligned.) */ 6122 IWN_WRITE(sc, IWN_FH_CBBC_QUEUE(qid), 6123 txq->desc_dma.paddr >> 8); 6124 } 6125 iwn_nic_unlock(sc); 6126 6127 /* Enable DMA channels. */ 6128 for (chnl = 0; chnl < hal->ndmachnls; chnl++) { 6129 IWN_WRITE(sc, IWN_FH_TX_CONFIG(chnl), 6130 IWN_FH_TX_CONFIG_DMA_ENA | 6131 IWN_FH_TX_CONFIG_DMA_CREDIT_ENA); 6132 } 6133 6134 /* Clear "radio off" and "commands blocked" bits. */ 6135 IWN_WRITE(sc, IWN_UCODE_GP1_CLR, IWN_UCODE_GP1_RFKILL); 6136 IWN_WRITE(sc, IWN_UCODE_GP1_CLR, IWN_UCODE_GP1_CMD_BLOCKED); 6137 6138 /* Clear pending interrupts. */ 6139 IWN_WRITE(sc, IWN_INT, 0xffffffff); 6140 /* Enable interrupt coalescing. */ 6141 IWN_WRITE(sc, IWN_INT_COALESCING, 512 / 8); 6142 /* Enable interrupts. */ 6143 IWN_WRITE(sc, IWN_INT_MASK, sc->int_mask); 6144 6145 /* _Really_ make sure "radio off" bit is cleared! */ 6146 IWN_WRITE(sc, IWN_UCODE_GP1_CLR, IWN_UCODE_GP1_RFKILL); 6147 IWN_WRITE(sc, IWN_UCODE_GP1_CLR, IWN_UCODE_GP1_RFKILL); 6148 6149 error = hal->load_firmware(sc); 6150 if (error != 0) { 6151 device_printf(sc->sc_dev, 6152 "%s: could not load firmware, error %d\n", 6153 __func__, error); 6154 return error; 6155 } 6156 /* Wait at most one second for firmware alive notification. */ 6157 error = msleep(sc, &sc->sc_mtx, PCATCH, "iwninit", hz); 6158 if (error != 0) { 6159 device_printf(sc->sc_dev, 6160 "%s: timeout waiting for adapter to initialize, error %d\n", 6161 __func__, error); 6162 return error; 6163 } 6164 /* Do post-firmware initialization. */ 6165 return hal->post_alive(sc); 6166 } 6167 6168 static void 6169 iwn_hw_stop(struct iwn_softc *sc) 6170 { 6171 const struct iwn_hal *hal = sc->sc_hal; 6172 uint32_t tmp; 6173 int chnl, qid, ntries; 6174 6175 IWN_WRITE(sc, IWN_RESET, IWN_RESET_NEVO); 6176 6177 /* Disable interrupts. */ 6178 IWN_WRITE(sc, IWN_INT_MASK, 0); 6179 IWN_WRITE(sc, IWN_INT, 0xffffffff); 6180 IWN_WRITE(sc, IWN_FH_INT, 0xffffffff); 6181 sc->sc_flags &= ~IWN_FLAG_USE_ICT; 6182 6183 /* Make sure we no longer hold the NIC lock. */ 6184 iwn_nic_unlock(sc); 6185 6186 /* Stop TX scheduler. */ 6187 iwn_prph_write(sc, hal->sched_txfact_addr, 0); 6188 6189 /* Stop all DMA channels. */ 6190 if (iwn_nic_lock(sc) == 0) { 6191 for (chnl = 0; chnl < hal->ndmachnls; chnl++) { 6192 IWN_WRITE(sc, IWN_FH_TX_CONFIG(chnl), 0); 6193 for (ntries = 0; ntries < 200; ntries++) { 6194 tmp = IWN_READ(sc, IWN_FH_TX_STATUS); 6195 if ((tmp & IWN_FH_TX_STATUS_IDLE(chnl)) == 6196 IWN_FH_TX_STATUS_IDLE(chnl)) 6197 break; 6198 DELAY(10); 6199 } 6200 } 6201 iwn_nic_unlock(sc); 6202 } 6203 6204 /* Stop RX ring. */ 6205 iwn_reset_rx_ring(sc, &sc->rxq); 6206 6207 /* Reset all TX rings. */ 6208 for (qid = 0; qid < hal->ntxqs; qid++) 6209 iwn_reset_tx_ring(sc, &sc->txq[qid]); 6210 6211 if (iwn_nic_lock(sc) == 0) { 6212 iwn_prph_write(sc, IWN_APMG_CLK_DIS, 6213 IWN_APMG_CLK_CTRL_DMA_CLK_RQT); 6214 iwn_nic_unlock(sc); 6215 } 6216 DELAY(5); 6217 6218 /* Power OFF adapter. */ 6219 iwn_apm_stop(sc); 6220 } 6221 6222 static void 6223 iwn_init_locked(struct iwn_softc *sc) 6224 { 6225 struct ifnet *ifp = sc->sc_ifp; 6226 int error; 6227 6228 IWN_LOCK_ASSERT(sc); 6229 6230 error = iwn_hw_prepare(sc); 6231 if (error != 0) { 6232 device_printf(sc->sc_dev, "%s: hardware not ready, eror %d\n", 6233 __func__, error); 6234 goto fail; 6235 } 6236 6237 /* Initialize interrupt mask to default value. */ 6238 sc->int_mask = IWN_INT_MASK_DEF; 6239 sc->sc_flags &= ~IWN_FLAG_USE_ICT; 6240 6241 /* Check that the radio is not disabled by hardware switch. */ 6242 if (!(IWN_READ(sc, IWN_GP_CNTRL) & IWN_GP_CNTRL_RFKILL)) { 6243 device_printf(sc->sc_dev, 6244 "radio is disabled by hardware switch\n"); 6245 6246 /* Enable interrupts to get RF toggle notifications. */ 6247 IWN_WRITE(sc, IWN_INT, 0xffffffff); 6248 IWN_WRITE(sc, IWN_INT_MASK, sc->int_mask); 6249 return; 6250 } 6251 6252 /* Read firmware images from the filesystem. */ 6253 error = iwn_read_firmware(sc); 6254 if (error != 0) { 6255 device_printf(sc->sc_dev, 6256 "%s: could not read firmware, error %d\n", 6257 __func__, error); 6258 goto fail; 6259 } 6260 6261 /* Initialize hardware and upload firmware. */ 6262 error = iwn_hw_init(sc); 6263 firmware_put(sc->fw_fp, FIRMWARE_UNLOAD); 6264 sc->fw_fp = NULL; 6265 if (error != 0) { 6266 device_printf(sc->sc_dev, 6267 "%s: could not initialize hardware, error %d\n", 6268 __func__, error); 6269 goto fail; 6270 } 6271 6272 /* Configure adapter now that it is ready. */ 6273 error = iwn_config(sc); 6274 if (error != 0) { 6275 device_printf(sc->sc_dev, 6276 "%s: could not configure device, error %d\n", 6277 __func__, error); 6278 goto fail; 6279 } 6280 6281 ifp->if_drv_flags &= ~IFF_DRV_OACTIVE; 6282 ifp->if_drv_flags |= IFF_DRV_RUNNING; 6283 6284 return; 6285 6286 fail: 6287 iwn_stop_locked(sc); 6288 } 6289 6290 static void 6291 iwn_init(void *arg) 6292 { 6293 struct iwn_softc *sc = arg; 6294 struct ifnet *ifp = sc->sc_ifp; 6295 struct ieee80211com *ic = ifp->if_l2com; 6296 6297 IWN_LOCK(sc); 6298 iwn_init_locked(sc); 6299 IWN_UNLOCK(sc); 6300 6301 if (ifp->if_drv_flags & IFF_DRV_RUNNING) 6302 ieee80211_start_all(ic); 6303 } 6304 6305 static void 6306 iwn_stop_locked(struct iwn_softc *sc) 6307 { 6308 struct ifnet *ifp = sc->sc_ifp; 6309 6310 IWN_LOCK_ASSERT(sc); 6311 6312 sc->sc_tx_timer = 0; 6313 callout_stop(&sc->sc_timer_to); 6314 ifp->if_drv_flags &= ~(IFF_DRV_RUNNING | IFF_DRV_OACTIVE); 6315 6316 /* Power OFF hardware. */ 6317 iwn_hw_stop(sc); 6318 } 6319 6320 static void 6321 iwn_stop(struct iwn_softc *sc) 6322 { 6323 IWN_LOCK(sc); 6324 iwn_stop_locked(sc); 6325 IWN_UNLOCK(sc); 6326 } 6327 6328 /* 6329 * Callback from net80211 to start a scan. 6330 */ 6331 static void 6332 iwn_scan_start(struct ieee80211com *ic) 6333 { 6334 struct ifnet *ifp = ic->ic_ifp; 6335 struct iwn_softc *sc = ifp->if_softc; 6336 6337 IWN_LOCK(sc); 6338 /* make the link LED blink while we're scanning */ 6339 iwn_set_led(sc, IWN_LED_LINK, 20, 2); 6340 IWN_UNLOCK(sc); 6341 } 6342 6343 /* 6344 * Callback from net80211 to terminate a scan. 6345 */ 6346 static void 6347 iwn_scan_end(struct ieee80211com *ic) 6348 { 6349 struct ifnet *ifp = ic->ic_ifp; 6350 struct iwn_softc *sc = ifp->if_softc; 6351 struct ieee80211vap *vap = TAILQ_FIRST(&ic->ic_vaps); 6352 6353 IWN_LOCK(sc); 6354 if (vap->iv_state == IEEE80211_S_RUN) { 6355 /* Set link LED to ON status if we are associated */ 6356 iwn_set_led(sc, IWN_LED_LINK, 0, 1); 6357 } 6358 IWN_UNLOCK(sc); 6359 } 6360 6361 /* 6362 * Callback from net80211 to force a channel change. 6363 */ 6364 static void 6365 iwn_set_channel(struct ieee80211com *ic) 6366 { 6367 const struct ieee80211_channel *c = ic->ic_curchan; 6368 struct ifnet *ifp = ic->ic_ifp; 6369 struct iwn_softc *sc = ifp->if_softc; 6370 6371 IWN_LOCK(sc); 6372 sc->sc_rxtap.wr_chan_freq = htole16(c->ic_freq); 6373 sc->sc_rxtap.wr_chan_flags = htole16(c->ic_flags); 6374 sc->sc_txtap.wt_chan_freq = htole16(c->ic_freq); 6375 sc->sc_txtap.wt_chan_flags = htole16(c->ic_flags); 6376 IWN_UNLOCK(sc); 6377 } 6378 6379 /* 6380 * Callback from net80211 to start scanning of the current channel. 6381 */ 6382 static void 6383 iwn_scan_curchan(struct ieee80211_scan_state *ss, unsigned long maxdwell) 6384 { 6385 struct ieee80211vap *vap = ss->ss_vap; 6386 struct iwn_softc *sc = vap->iv_ic->ic_ifp->if_softc; 6387 int error; 6388 6389 IWN_LOCK(sc); 6390 error = iwn_scan(sc); 6391 IWN_UNLOCK(sc); 6392 if (error != 0) 6393 ieee80211_cancel_scan(vap); 6394 } 6395 6396 /* 6397 * Callback from net80211 to handle the minimum dwell time being met. 6398 * The intent is to terminate the scan but we just let the firmware 6399 * notify us when it's finished as we have no safe way to abort it. 6400 */ 6401 static void 6402 iwn_scan_mindwell(struct ieee80211_scan_state *ss) 6403 { 6404 /* NB: don't try to abort scan; wait for firmware to finish */ 6405 } 6406 6407 static struct iwn_eeprom_chan * 6408 iwn_find_eeprom_channel(struct iwn_softc *sc, struct ieee80211_channel *c) 6409 { 6410 int i, j; 6411 6412 for (j = 0; j < 7; j++) { 6413 for (i = 0; i < iwn_bands[j].nchan; i++) { 6414 if (iwn_bands[j].chan[i] == c->ic_ieee) 6415 return &sc->eeprom_channels[j][i]; 6416 } 6417 } 6418 6419 return NULL; 6420 } 6421 6422 /* 6423 * Enforce flags read from EEPROM. 6424 */ 6425 static int 6426 iwn_setregdomain(struct ieee80211com *ic, struct ieee80211_regdomain *rd, 6427 int nchan, struct ieee80211_channel chans[]) 6428 { 6429 struct iwn_softc *sc = ic->ic_ifp->if_softc; 6430 int i; 6431 6432 for (i = 0; i < nchan; i++) { 6433 struct ieee80211_channel *c = &chans[i]; 6434 struct iwn_eeprom_chan *channel; 6435 6436 channel = iwn_find_eeprom_channel(sc, c); 6437 if (channel == NULL) { 6438 if_printf(ic->ic_ifp, 6439 "%s: invalid channel %u freq %u/0x%x\n", 6440 __func__, c->ic_ieee, c->ic_freq, c->ic_flags); 6441 return EINVAL; 6442 } 6443 c->ic_flags |= iwn_eeprom_channel_flags(channel); 6444 } 6445 6446 return 0; 6447 } 6448 6449 static void 6450 iwn_hw_reset(void *arg0, int pending) 6451 { 6452 struct iwn_softc *sc = arg0; 6453 struct ifnet *ifp = sc->sc_ifp; 6454 struct ieee80211com *ic = ifp->if_l2com; 6455 6456 iwn_stop(sc); 6457 iwn_init(sc); 6458 ieee80211_notify_radio(ic, 1); 6459 } 6460 6461 static void 6462 iwn_radio_on(void *arg0, int pending) 6463 { 6464 struct iwn_softc *sc = arg0; 6465 struct ifnet *ifp = sc->sc_ifp; 6466 struct ieee80211com *ic = ifp->if_l2com; 6467 struct ieee80211vap *vap = TAILQ_FIRST(&ic->ic_vaps); 6468 6469 if (vap != NULL) { 6470 iwn_init(sc); 6471 ieee80211_init(vap); 6472 } 6473 } 6474 6475 static void 6476 iwn_radio_off(void *arg0, int pending) 6477 { 6478 struct iwn_softc *sc = arg0; 6479 struct ifnet *ifp = sc->sc_ifp; 6480 struct ieee80211com *ic = ifp->if_l2com; 6481 struct ieee80211vap *vap = TAILQ_FIRST(&ic->ic_vaps); 6482 6483 iwn_stop(sc); 6484 if (vap != NULL) 6485 ieee80211_stop(vap); 6486 6487 /* Enable interrupts to get RF toggle notification. */ 6488 IWN_LOCK(sc); 6489 IWN_WRITE(sc, IWN_INT, 0xffffffff); 6490 IWN_WRITE(sc, IWN_INT_MASK, sc->int_mask); 6491 IWN_UNLOCK(sc); 6492 } 6493 6494 static void 6495 iwn_sysctlattach(struct iwn_softc *sc) 6496 { 6497 struct sysctl_ctx_list *ctx = device_get_sysctl_ctx(sc->sc_dev); 6498 struct sysctl_oid *tree = device_get_sysctl_tree(sc->sc_dev); 6499 6500 #ifdef IWN_DEBUG 6501 sc->sc_debug = 0; 6502 SYSCTL_ADD_INT(ctx, SYSCTL_CHILDREN(tree), OID_AUTO, 6503 "debug", CTLFLAG_RW, &sc->sc_debug, 0, "control debugging printfs"); 6504 #endif 6505 } 6506 6507 static int 6508 iwn_shutdown(device_t dev) 6509 { 6510 struct iwn_softc *sc = device_get_softc(dev); 6511 6512 iwn_stop(sc); 6513 return 0; 6514 } 6515 6516 static int 6517 iwn_suspend(device_t dev) 6518 { 6519 struct iwn_softc *sc = device_get_softc(dev); 6520 struct ifnet *ifp = sc->sc_ifp; 6521 struct ieee80211com *ic = ifp->if_l2com; 6522 struct ieee80211vap *vap = TAILQ_FIRST(&ic->ic_vaps); 6523 6524 iwn_stop(sc); 6525 if (vap != NULL) 6526 ieee80211_stop(vap); 6527 return 0; 6528 } 6529 6530 static int 6531 iwn_resume(device_t dev) 6532 { 6533 struct iwn_softc *sc = device_get_softc(dev); 6534 struct ifnet *ifp = sc->sc_ifp; 6535 struct ieee80211com *ic = ifp->if_l2com; 6536 struct ieee80211vap *vap = TAILQ_FIRST(&ic->ic_vaps); 6537 6538 /* Clear device-specific "PCI retry timeout" register (41h). */ 6539 pci_write_config(dev, 0x41, 0, 1); 6540 6541 if (ifp->if_flags & IFF_UP) { 6542 iwn_init(sc); 6543 if (vap != NULL) 6544 ieee80211_init(vap); 6545 if (ifp->if_drv_flags & IFF_DRV_RUNNING) 6546 iwn_start(ifp); 6547 } 6548 return 0; 6549 } 6550 6551 #ifdef IWN_DEBUG 6552 static const char * 6553 iwn_intr_str(uint8_t cmd) 6554 { 6555 switch (cmd) { 6556 /* Notifications */ 6557 case IWN_UC_READY: return "UC_READY"; 6558 case IWN_ADD_NODE_DONE: return "ADD_NODE_DONE"; 6559 case IWN_TX_DONE: return "TX_DONE"; 6560 case IWN_START_SCAN: return "START_SCAN"; 6561 case IWN_STOP_SCAN: return "STOP_SCAN"; 6562 case IWN_RX_STATISTICS: return "RX_STATS"; 6563 case IWN_BEACON_STATISTICS: return "BEACON_STATS"; 6564 case IWN_STATE_CHANGED: return "STATE_CHANGED"; 6565 case IWN_BEACON_MISSED: return "BEACON_MISSED"; 6566 case IWN_RX_PHY: return "RX_PHY"; 6567 case IWN_MPDU_RX_DONE: return "MPDU_RX_DONE"; 6568 case IWN_RX_DONE: return "RX_DONE"; 6569 6570 /* Command Notifications */ 6571 case IWN_CMD_RXON: return "IWN_CMD_RXON"; 6572 case IWN_CMD_RXON_ASSOC: return "IWN_CMD_RXON_ASSOC"; 6573 case IWN_CMD_EDCA_PARAMS: return "IWN_CMD_EDCA_PARAMS"; 6574 case IWN_CMD_TIMING: return "IWN_CMD_TIMING"; 6575 case IWN_CMD_LINK_QUALITY: return "IWN_CMD_LINK_QUALITY"; 6576 case IWN_CMD_SET_LED: return "IWN_CMD_SET_LED"; 6577 case IWN5000_CMD_WIMAX_COEX: return "IWN5000_CMD_WIMAX_COEX"; 6578 case IWN5000_CMD_CALIB_CONFIG: return "IWN5000_CMD_CALIB_CONFIG"; 6579 case IWN5000_CMD_CALIB_RESULT: return "IWN5000_CMD_CALIB_RESULT"; 6580 case IWN5000_CMD_CALIB_COMPLETE: return "IWN5000_CMD_CALIB_COMPLETE"; 6581 case IWN_CMD_SET_POWER_MODE: return "IWN_CMD_SET_POWER_MODE"; 6582 case IWN_CMD_SCAN: return "IWN_CMD_SCAN"; 6583 case IWN_CMD_SCAN_RESULTS: return "IWN_CMD_SCAN_RESULTS"; 6584 case IWN_CMD_TXPOWER: return "IWN_CMD_TXPOWER"; 6585 case IWN_CMD_TXPOWER_DBM: return "IWN_CMD_TXPOWER_DBM"; 6586 case IWN5000_CMD_TX_ANT_CONFIG: return "IWN5000_CMD_TX_ANT_CONFIG"; 6587 case IWN_CMD_BT_COEX: return "IWN_CMD_BT_COEX"; 6588 case IWN_CMD_SET_CRITICAL_TEMP: return "IWN_CMD_SET_CRITICAL_TEMP"; 6589 case IWN_CMD_SET_SENSITIVITY: return "IWN_CMD_SET_SENSITIVITY"; 6590 case IWN_CMD_PHY_CALIB: return "IWN_CMD_PHY_CALIB"; 6591 } 6592 return "UNKNOWN INTR NOTIF/CMD"; 6593 } 6594 #endif /* IWN_DEBUG */ 6595 6596 static device_method_t iwn_methods[] = { 6597 /* Device interface */ 6598 DEVMETHOD(device_probe, iwn_probe), 6599 DEVMETHOD(device_attach, iwn_attach), 6600 DEVMETHOD(device_detach, iwn_detach), 6601 DEVMETHOD(device_shutdown, iwn_shutdown), 6602 DEVMETHOD(device_suspend, iwn_suspend), 6603 DEVMETHOD(device_resume, iwn_resume), 6604 { 0, 0 } 6605 }; 6606 6607 static driver_t iwn_driver = { 6608 "iwn", 6609 iwn_methods, 6610 sizeof (struct iwn_softc) 6611 }; 6612 static devclass_t iwn_devclass; 6613 6614 DRIVER_MODULE(iwn, pci, iwn_driver, iwn_devclass, 0, 0); 6615 MODULE_DEPEND(iwn, pci, 1, 1, 1); 6616 MODULE_DEPEND(iwn, firmware, 1, 1, 1); 6617 MODULE_DEPEND(iwn, wlan, 1, 1, 1); 6618