1 /*- 2 * Copyright (c) 2007-2009 3 * Damien Bergamini <damien.bergamini@free.fr> 4 * Copyright (c) 2008 5 * Benjamin Close <benjsc@FreeBSD.org> 6 * Copyright (c) 2008 Sam Leffler, Errno Consulting 7 * 8 * Permission to use, copy, modify, and distribute this software for any 9 * purpose with or without fee is hereby granted, provided that the above 10 * copyright notice and this permission notice appear in all copies. 11 * 12 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 13 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 14 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR 15 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 16 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN 17 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF 18 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 19 */ 20 21 /* 22 * Driver for Intel WiFi Link 4965 and 1000/5000/6000 Series 802.11 network 23 * adapters. 24 */ 25 26 #include <sys/cdefs.h> 27 __FBSDID("$FreeBSD$"); 28 29 #include <sys/param.h> 30 #include <sys/sockio.h> 31 #include <sys/sysctl.h> 32 #include <sys/mbuf.h> 33 #include <sys/kernel.h> 34 #include <sys/socket.h> 35 #include <sys/systm.h> 36 #include <sys/malloc.h> 37 #include <sys/bus.h> 38 #include <sys/rman.h> 39 #include <sys/endian.h> 40 #include <sys/firmware.h> 41 #include <sys/limits.h> 42 #include <sys/module.h> 43 #include <sys/queue.h> 44 #include <sys/taskqueue.h> 45 46 #include <machine/bus.h> 47 #include <machine/resource.h> 48 #include <machine/clock.h> 49 50 #include <dev/pci/pcireg.h> 51 #include <dev/pci/pcivar.h> 52 53 #include <net/bpf.h> 54 #include <net/if.h> 55 #include <net/if_arp.h> 56 #include <net/ethernet.h> 57 #include <net/if_dl.h> 58 #include <net/if_media.h> 59 #include <net/if_types.h> 60 61 #include <netinet/in.h> 62 #include <netinet/in_systm.h> 63 #include <netinet/in_var.h> 64 #include <netinet/if_ether.h> 65 #include <netinet/ip.h> 66 67 #include <net80211/ieee80211_var.h> 68 #include <net80211/ieee80211_radiotap.h> 69 #include <net80211/ieee80211_regdomain.h> 70 #include <net80211/ieee80211_ratectl.h> 71 72 #include <dev/iwn/if_iwnreg.h> 73 #include <dev/iwn/if_iwnvar.h> 74 75 struct iwn_ident { 76 uint16_t vendor; 77 uint16_t device; 78 const char *name; 79 }; 80 81 static const struct iwn_ident iwn_ident_table[] = { 82 { 0x8086, 0x0082, "Intel(R) Centrino(R) Advanced-N 6205" }, 83 { 0x8086, 0x0083, "Intel(R) Centrino(R) Wireless-N 1000" }, 84 { 0x8086, 0x0084, "Intel(R) Centrino(R) Wireless-N 1000" }, 85 { 0x8086, 0x0085, "Intel(R) Centrino(R) Advanced-N 6205" }, 86 { 0x8086, 0x0087, "Intel(R) Centrino(R) Advanced-N + WiMAX 6250" }, 87 { 0x8086, 0x0089, "Intel(R) Centrino(R) Advanced-N + WiMAX 6250" }, 88 { 0x8086, 0x008a, "Intel(R) Centrino(R) Wireless-N 1030" }, 89 { 0x8086, 0x008b, "Intel(R) Centrino(R) Wireless-N 1030" }, 90 { 0x8086, 0x0090, "Intel(R) Centrino(R) Advanced-N 6230" }, 91 { 0x8086, 0x0091, "Intel(R) Centrino(R) Advanced-N 6230" }, 92 { 0x8086, 0x4229, "Intel(R) Wireless WiFi Link 4965" }, 93 { 0x8086, 0x422b, "Intel(R) Centrino(R) Ultimate-N 6300" }, 94 { 0x8086, 0x422c, "Intel(R) Centrino(R) Advanced-N 6200" }, 95 { 0x8086, 0x422d, "Intel(R) Wireless WiFi Link 4965" }, 96 { 0x8086, 0x4230, "Intel(R) Wireless WiFi Link 4965" }, 97 { 0x8086, 0x4232, "Intel(R) WiFi Link 5100" }, 98 { 0x8086, 0x4233, "Intel(R) Wireless WiFi Link 4965" }, 99 { 0x8086, 0x4235, "Intel(R) Ultimate N WiFi Link 5300" }, 100 { 0x8086, 0x4236, "Intel(R) Ultimate N WiFi Link 5300" }, 101 { 0x8086, 0x4237, "Intel(R) WiFi Link 5100" }, 102 { 0x8086, 0x4238, "Intel(R) Centrino(R) Ultimate-N 6300" }, 103 { 0x8086, 0x4239, "Intel(R) Centrino(R) Advanced-N 6200" }, 104 { 0x8086, 0x423a, "Intel(R) WiMAX/WiFi Link 5350" }, 105 { 0x8086, 0x423b, "Intel(R) WiMAX/WiFi Link 5350" }, 106 { 0x8086, 0x423c, "Intel(R) WiMAX/WiFi Link 5150" }, 107 { 0x8086, 0x423d, "Intel(R) WiMAX/WiFi Link 5150" }, 108 { 0, 0, NULL } 109 }; 110 111 static int iwn_probe(device_t); 112 static int iwn_attach(device_t); 113 static int iwn4965_attach(struct iwn_softc *, uint16_t); 114 static int iwn5000_attach(struct iwn_softc *, uint16_t); 115 static void iwn_radiotap_attach(struct iwn_softc *); 116 static void iwn_sysctlattach(struct iwn_softc *); 117 static struct ieee80211vap *iwn_vap_create(struct ieee80211com *, 118 const char name[IFNAMSIZ], int unit, int opmode, 119 int flags, const uint8_t bssid[IEEE80211_ADDR_LEN], 120 const uint8_t mac[IEEE80211_ADDR_LEN]); 121 static void iwn_vap_delete(struct ieee80211vap *); 122 static int iwn_detach(device_t); 123 static int iwn_shutdown(device_t); 124 static int iwn_suspend(device_t); 125 static int iwn_resume(device_t); 126 static int iwn_nic_lock(struct iwn_softc *); 127 static int iwn_eeprom_lock(struct iwn_softc *); 128 static int iwn_init_otprom(struct iwn_softc *); 129 static int iwn_read_prom_data(struct iwn_softc *, uint32_t, void *, int); 130 static void iwn_dma_map_addr(void *, bus_dma_segment_t *, int, int); 131 static int iwn_dma_contig_alloc(struct iwn_softc *, struct iwn_dma_info *, 132 void **, bus_size_t, bus_size_t); 133 static void iwn_dma_contig_free(struct iwn_dma_info *); 134 static int iwn_alloc_sched(struct iwn_softc *); 135 static void iwn_free_sched(struct iwn_softc *); 136 static int iwn_alloc_kw(struct iwn_softc *); 137 static void iwn_free_kw(struct iwn_softc *); 138 static int iwn_alloc_ict(struct iwn_softc *); 139 static void iwn_free_ict(struct iwn_softc *); 140 static int iwn_alloc_fwmem(struct iwn_softc *); 141 static void iwn_free_fwmem(struct iwn_softc *); 142 static int iwn_alloc_rx_ring(struct iwn_softc *, struct iwn_rx_ring *); 143 static void iwn_reset_rx_ring(struct iwn_softc *, struct iwn_rx_ring *); 144 static void iwn_free_rx_ring(struct iwn_softc *, struct iwn_rx_ring *); 145 static int iwn_alloc_tx_ring(struct iwn_softc *, struct iwn_tx_ring *, 146 int); 147 static void iwn_reset_tx_ring(struct iwn_softc *, struct iwn_tx_ring *); 148 static void iwn_free_tx_ring(struct iwn_softc *, struct iwn_tx_ring *); 149 static void iwn5000_ict_reset(struct iwn_softc *); 150 static int iwn_read_eeprom(struct iwn_softc *, 151 uint8_t macaddr[IEEE80211_ADDR_LEN]); 152 static void iwn4965_read_eeprom(struct iwn_softc *); 153 static void iwn4965_print_power_group(struct iwn_softc *, int); 154 static void iwn5000_read_eeprom(struct iwn_softc *); 155 static uint32_t iwn_eeprom_channel_flags(struct iwn_eeprom_chan *); 156 static void iwn_read_eeprom_band(struct iwn_softc *, int); 157 static void iwn_read_eeprom_ht40(struct iwn_softc *, int); 158 static void iwn_read_eeprom_channels(struct iwn_softc *, int, uint32_t); 159 static struct iwn_eeprom_chan *iwn_find_eeprom_channel(struct iwn_softc *, 160 struct ieee80211_channel *); 161 static int iwn_setregdomain(struct ieee80211com *, 162 struct ieee80211_regdomain *, int, 163 struct ieee80211_channel[]); 164 static void iwn_read_eeprom_enhinfo(struct iwn_softc *); 165 static struct ieee80211_node *iwn_node_alloc(struct ieee80211vap *, 166 const uint8_t mac[IEEE80211_ADDR_LEN]); 167 static void iwn_newassoc(struct ieee80211_node *, int); 168 static int iwn_media_change(struct ifnet *); 169 static int iwn_newstate(struct ieee80211vap *, enum ieee80211_state, int); 170 static void iwn_calib_timeout(void *); 171 static void iwn_rx_phy(struct iwn_softc *, struct iwn_rx_desc *, 172 struct iwn_rx_data *); 173 static void iwn_rx_done(struct iwn_softc *, struct iwn_rx_desc *, 174 struct iwn_rx_data *); 175 static void iwn_rx_compressed_ba(struct iwn_softc *, struct iwn_rx_desc *, 176 struct iwn_rx_data *); 177 static void iwn5000_rx_calib_results(struct iwn_softc *, 178 struct iwn_rx_desc *, struct iwn_rx_data *); 179 static void iwn_rx_statistics(struct iwn_softc *, struct iwn_rx_desc *, 180 struct iwn_rx_data *); 181 static void iwn4965_tx_done(struct iwn_softc *, struct iwn_rx_desc *, 182 struct iwn_rx_data *); 183 static void iwn5000_tx_done(struct iwn_softc *, struct iwn_rx_desc *, 184 struct iwn_rx_data *); 185 static void iwn_tx_done(struct iwn_softc *, struct iwn_rx_desc *, int, 186 uint8_t); 187 static void iwn_ampdu_tx_done(struct iwn_softc *, int, int, int, void *); 188 static void iwn_cmd_done(struct iwn_softc *, struct iwn_rx_desc *); 189 static void iwn_notif_intr(struct iwn_softc *); 190 static void iwn_wakeup_intr(struct iwn_softc *); 191 static void iwn_rftoggle_intr(struct iwn_softc *); 192 static void iwn_fatal_intr(struct iwn_softc *); 193 static void iwn_intr(void *); 194 static void iwn4965_update_sched(struct iwn_softc *, int, int, uint8_t, 195 uint16_t); 196 static void iwn5000_update_sched(struct iwn_softc *, int, int, uint8_t, 197 uint16_t); 198 #ifdef notyet 199 static void iwn5000_reset_sched(struct iwn_softc *, int, int); 200 #endif 201 static int iwn_tx_data(struct iwn_softc *, struct mbuf *, 202 struct ieee80211_node *); 203 static int iwn_tx_data_raw(struct iwn_softc *, struct mbuf *, 204 struct ieee80211_node *, 205 const struct ieee80211_bpf_params *params); 206 static int iwn_raw_xmit(struct ieee80211_node *, struct mbuf *, 207 const struct ieee80211_bpf_params *); 208 static void iwn_start(struct ifnet *); 209 static void iwn_start_locked(struct ifnet *); 210 static void iwn_watchdog(void *); 211 static int iwn_ioctl(struct ifnet *, u_long, caddr_t); 212 static int iwn_cmd(struct iwn_softc *, int, const void *, int, int); 213 static int iwn4965_add_node(struct iwn_softc *, struct iwn_node_info *, 214 int); 215 static int iwn5000_add_node(struct iwn_softc *, struct iwn_node_info *, 216 int); 217 static int iwn_set_link_quality(struct iwn_softc *, 218 struct ieee80211_node *); 219 static int iwn_add_broadcast_node(struct iwn_softc *, int); 220 static int iwn_updateedca(struct ieee80211com *); 221 static void iwn_update_mcast(struct ifnet *); 222 static void iwn_set_led(struct iwn_softc *, uint8_t, uint8_t, uint8_t); 223 static int iwn_set_critical_temp(struct iwn_softc *); 224 static int iwn_set_timing(struct iwn_softc *, struct ieee80211_node *); 225 static void iwn4965_power_calibration(struct iwn_softc *, int); 226 static int iwn4965_set_txpower(struct iwn_softc *, 227 struct ieee80211_channel *, int); 228 static int iwn5000_set_txpower(struct iwn_softc *, 229 struct ieee80211_channel *, int); 230 static int iwn4965_get_rssi(struct iwn_softc *, struct iwn_rx_stat *); 231 static int iwn5000_get_rssi(struct iwn_softc *, struct iwn_rx_stat *); 232 static int iwn_get_noise(const struct iwn_rx_general_stats *); 233 static int iwn4965_get_temperature(struct iwn_softc *); 234 static int iwn5000_get_temperature(struct iwn_softc *); 235 static int iwn_init_sensitivity(struct iwn_softc *); 236 static void iwn_collect_noise(struct iwn_softc *, 237 const struct iwn_rx_general_stats *); 238 static int iwn4965_init_gains(struct iwn_softc *); 239 static int iwn5000_init_gains(struct iwn_softc *); 240 static int iwn4965_set_gains(struct iwn_softc *); 241 static int iwn5000_set_gains(struct iwn_softc *); 242 static void iwn_tune_sensitivity(struct iwn_softc *, 243 const struct iwn_rx_stats *); 244 static int iwn_send_sensitivity(struct iwn_softc *); 245 static int iwn_set_pslevel(struct iwn_softc *, int, int, int); 246 static int iwn_send_btcoex(struct iwn_softc *); 247 static int iwn_send_advanced_btcoex(struct iwn_softc *); 248 static int iwn_config(struct iwn_softc *); 249 static uint8_t *ieee80211_add_ssid(uint8_t *, const uint8_t *, u_int); 250 static int iwn_scan(struct iwn_softc *); 251 static int iwn_auth(struct iwn_softc *, struct ieee80211vap *vap); 252 static int iwn_run(struct iwn_softc *, struct ieee80211vap *vap); 253 static int iwn_ampdu_rx_start(struct ieee80211_node *, 254 struct ieee80211_rx_ampdu *, int, int, int); 255 static void iwn_ampdu_rx_stop(struct ieee80211_node *, 256 struct ieee80211_rx_ampdu *); 257 static int iwn_addba_request(struct ieee80211_node *, 258 struct ieee80211_tx_ampdu *, int, int, int); 259 static int iwn_addba_response(struct ieee80211_node *, 260 struct ieee80211_tx_ampdu *, int, int, int); 261 static int iwn_ampdu_tx_start(struct ieee80211com *, 262 struct ieee80211_node *, uint8_t); 263 static void iwn_ampdu_tx_stop(struct ieee80211_node *, 264 struct ieee80211_tx_ampdu *); 265 static void iwn4965_ampdu_tx_start(struct iwn_softc *, 266 struct ieee80211_node *, int, uint8_t, uint16_t); 267 static void iwn4965_ampdu_tx_stop(struct iwn_softc *, int, 268 uint8_t, uint16_t); 269 static void iwn5000_ampdu_tx_start(struct iwn_softc *, 270 struct ieee80211_node *, int, uint8_t, uint16_t); 271 static void iwn5000_ampdu_tx_stop(struct iwn_softc *, int, 272 uint8_t, uint16_t); 273 static int iwn5000_query_calibration(struct iwn_softc *); 274 static int iwn5000_send_calibration(struct iwn_softc *); 275 static int iwn5000_send_wimax_coex(struct iwn_softc *); 276 static int iwn5000_crystal_calib(struct iwn_softc *); 277 static int iwn5000_temp_offset_calib(struct iwn_softc *); 278 static int iwn4965_post_alive(struct iwn_softc *); 279 static int iwn5000_post_alive(struct iwn_softc *); 280 static int iwn4965_load_bootcode(struct iwn_softc *, const uint8_t *, 281 int); 282 static int iwn4965_load_firmware(struct iwn_softc *); 283 static int iwn5000_load_firmware_section(struct iwn_softc *, uint32_t, 284 const uint8_t *, int); 285 static int iwn5000_load_firmware(struct iwn_softc *); 286 static int iwn_read_firmware_leg(struct iwn_softc *, 287 struct iwn_fw_info *); 288 static int iwn_read_firmware_tlv(struct iwn_softc *, 289 struct iwn_fw_info *, uint16_t); 290 static int iwn_read_firmware(struct iwn_softc *); 291 static int iwn_clock_wait(struct iwn_softc *); 292 static int iwn_apm_init(struct iwn_softc *); 293 static void iwn_apm_stop_master(struct iwn_softc *); 294 static void iwn_apm_stop(struct iwn_softc *); 295 static int iwn4965_nic_config(struct iwn_softc *); 296 static int iwn5000_nic_config(struct iwn_softc *); 297 static int iwn_hw_prepare(struct iwn_softc *); 298 static int iwn_hw_init(struct iwn_softc *); 299 static void iwn_hw_stop(struct iwn_softc *); 300 static void iwn_radio_on(void *, int); 301 static void iwn_radio_off(void *, int); 302 static void iwn_init_locked(struct iwn_softc *); 303 static void iwn_init(void *); 304 static void iwn_stop_locked(struct iwn_softc *); 305 static void iwn_stop(struct iwn_softc *); 306 static void iwn_scan_start(struct ieee80211com *); 307 static void iwn_scan_end(struct ieee80211com *); 308 static void iwn_set_channel(struct ieee80211com *); 309 static void iwn_scan_curchan(struct ieee80211_scan_state *, unsigned long); 310 static void iwn_scan_mindwell(struct ieee80211_scan_state *); 311 static void iwn_hw_reset(void *, int); 312 313 #define IWN_DEBUG 314 #ifdef IWN_DEBUG 315 enum { 316 IWN_DEBUG_XMIT = 0x00000001, /* basic xmit operation */ 317 IWN_DEBUG_RECV = 0x00000002, /* basic recv operation */ 318 IWN_DEBUG_STATE = 0x00000004, /* 802.11 state transitions */ 319 IWN_DEBUG_TXPOW = 0x00000008, /* tx power processing */ 320 IWN_DEBUG_RESET = 0x00000010, /* reset processing */ 321 IWN_DEBUG_OPS = 0x00000020, /* iwn_ops processing */ 322 IWN_DEBUG_BEACON = 0x00000040, /* beacon handling */ 323 IWN_DEBUG_WATCHDOG = 0x00000080, /* watchdog timeout */ 324 IWN_DEBUG_INTR = 0x00000100, /* ISR */ 325 IWN_DEBUG_CALIBRATE = 0x00000200, /* periodic calibration */ 326 IWN_DEBUG_NODE = 0x00000400, /* node management */ 327 IWN_DEBUG_LED = 0x00000800, /* led management */ 328 IWN_DEBUG_CMD = 0x00001000, /* cmd submission */ 329 IWN_DEBUG_FATAL = 0x80000000, /* fatal errors */ 330 IWN_DEBUG_ANY = 0xffffffff 331 }; 332 333 #define DPRINTF(sc, m, fmt, ...) do { \ 334 if (sc->sc_debug & (m)) \ 335 printf(fmt, __VA_ARGS__); \ 336 } while (0) 337 338 static const char * 339 iwn_intr_str(uint8_t cmd) 340 { 341 switch (cmd) { 342 /* Notifications */ 343 case IWN_UC_READY: return "UC_READY"; 344 case IWN_ADD_NODE_DONE: return "ADD_NODE_DONE"; 345 case IWN_TX_DONE: return "TX_DONE"; 346 case IWN_START_SCAN: return "START_SCAN"; 347 case IWN_STOP_SCAN: return "STOP_SCAN"; 348 case IWN_RX_STATISTICS: return "RX_STATS"; 349 case IWN_BEACON_STATISTICS: return "BEACON_STATS"; 350 case IWN_STATE_CHANGED: return "STATE_CHANGED"; 351 case IWN_BEACON_MISSED: return "BEACON_MISSED"; 352 case IWN_RX_PHY: return "RX_PHY"; 353 case IWN_MPDU_RX_DONE: return "MPDU_RX_DONE"; 354 case IWN_RX_DONE: return "RX_DONE"; 355 356 /* Command Notifications */ 357 case IWN_CMD_RXON: return "IWN_CMD_RXON"; 358 case IWN_CMD_RXON_ASSOC: return "IWN_CMD_RXON_ASSOC"; 359 case IWN_CMD_EDCA_PARAMS: return "IWN_CMD_EDCA_PARAMS"; 360 case IWN_CMD_TIMING: return "IWN_CMD_TIMING"; 361 case IWN_CMD_LINK_QUALITY: return "IWN_CMD_LINK_QUALITY"; 362 case IWN_CMD_SET_LED: return "IWN_CMD_SET_LED"; 363 case IWN5000_CMD_WIMAX_COEX: return "IWN5000_CMD_WIMAX_COEX"; 364 case IWN5000_CMD_CALIB_CONFIG: return "IWN5000_CMD_CALIB_CONFIG"; 365 case IWN5000_CMD_CALIB_RESULT: return "IWN5000_CMD_CALIB_RESULT"; 366 case IWN5000_CMD_CALIB_COMPLETE: return "IWN5000_CMD_CALIB_COMPLETE"; 367 case IWN_CMD_SET_POWER_MODE: return "IWN_CMD_SET_POWER_MODE"; 368 case IWN_CMD_SCAN: return "IWN_CMD_SCAN"; 369 case IWN_CMD_SCAN_RESULTS: return "IWN_CMD_SCAN_RESULTS"; 370 case IWN_CMD_TXPOWER: return "IWN_CMD_TXPOWER"; 371 case IWN_CMD_TXPOWER_DBM: return "IWN_CMD_TXPOWER_DBM"; 372 case IWN5000_CMD_TX_ANT_CONFIG: return "IWN5000_CMD_TX_ANT_CONFIG"; 373 case IWN_CMD_BT_COEX: return "IWN_CMD_BT_COEX"; 374 case IWN_CMD_SET_CRITICAL_TEMP: return "IWN_CMD_SET_CRITICAL_TEMP"; 375 case IWN_CMD_SET_SENSITIVITY: return "IWN_CMD_SET_SENSITIVITY"; 376 case IWN_CMD_PHY_CALIB: return "IWN_CMD_PHY_CALIB"; 377 } 378 return "UNKNOWN INTR NOTIF/CMD"; 379 } 380 #else 381 #define DPRINTF(sc, m, fmt, ...) do { (void) sc; } while (0) 382 #endif 383 384 static device_method_t iwn_methods[] = { 385 /* Device interface */ 386 DEVMETHOD(device_probe, iwn_probe), 387 DEVMETHOD(device_attach, iwn_attach), 388 DEVMETHOD(device_detach, iwn_detach), 389 DEVMETHOD(device_shutdown, iwn_shutdown), 390 DEVMETHOD(device_suspend, iwn_suspend), 391 DEVMETHOD(device_resume, iwn_resume), 392 { 0, 0 } 393 }; 394 395 static driver_t iwn_driver = { 396 "iwn", 397 iwn_methods, 398 sizeof(struct iwn_softc) 399 }; 400 static devclass_t iwn_devclass; 401 402 DRIVER_MODULE(iwn, pci, iwn_driver, iwn_devclass, 0, 0); 403 404 MODULE_VERSION(iwn, 1); 405 406 MODULE_DEPEND(iwn, firmware, 1, 1, 1); 407 MODULE_DEPEND(iwn, pci, 1, 1, 1); 408 MODULE_DEPEND(iwn, wlan, 1, 1, 1); 409 410 static int 411 iwn_probe(device_t dev) 412 { 413 const struct iwn_ident *ident; 414 415 for (ident = iwn_ident_table; ident->name != NULL; ident++) { 416 if (pci_get_vendor(dev) == ident->vendor && 417 pci_get_device(dev) == ident->device) { 418 device_set_desc(dev, ident->name); 419 return 0; 420 } 421 } 422 return ENXIO; 423 } 424 425 static int 426 iwn_attach(device_t dev) 427 { 428 struct iwn_softc *sc = (struct iwn_softc *)device_get_softc(dev); 429 struct ieee80211com *ic; 430 struct ifnet *ifp; 431 uint32_t reg; 432 int i, error, result; 433 uint8_t macaddr[IEEE80211_ADDR_LEN]; 434 435 sc->sc_dev = dev; 436 437 /* 438 * Get the offset of the PCI Express Capability Structure in PCI 439 * Configuration Space. 440 */ 441 error = pci_find_cap(dev, PCIY_EXPRESS, &sc->sc_cap_off); 442 if (error != 0) { 443 device_printf(dev, "PCIe capability structure not found!\n"); 444 return error; 445 } 446 447 /* Clear device-specific "PCI retry timeout" register (41h). */ 448 pci_write_config(dev, 0x41, 0, 1); 449 450 /* Hardware bug workaround. */ 451 reg = pci_read_config(dev, PCIR_COMMAND, 1); 452 if (reg & PCIM_CMD_INTxDIS) { 453 DPRINTF(sc, IWN_DEBUG_RESET, "%s: PCIe INTx Disable set\n", 454 __func__); 455 reg &= ~PCIM_CMD_INTxDIS; 456 pci_write_config(dev, PCIR_COMMAND, reg, 1); 457 } 458 459 /* Enable bus-mastering. */ 460 pci_enable_busmaster(dev); 461 462 sc->mem_rid = PCIR_BAR(0); 463 sc->mem = bus_alloc_resource_any(dev, SYS_RES_MEMORY, &sc->mem_rid, 464 RF_ACTIVE); 465 if (sc->mem == NULL) { 466 device_printf(dev, "can't map mem space\n"); 467 error = ENOMEM; 468 return error; 469 } 470 sc->sc_st = rman_get_bustag(sc->mem); 471 sc->sc_sh = rman_get_bushandle(sc->mem); 472 473 sc->irq_rid = 0; 474 if ((result = pci_msi_count(dev)) == 1 && 475 pci_alloc_msi(dev, &result) == 0) 476 sc->irq_rid = 1; 477 /* Install interrupt handler. */ 478 sc->irq = bus_alloc_resource_any(dev, SYS_RES_IRQ, &sc->irq_rid, 479 RF_ACTIVE | RF_SHAREABLE); 480 if (sc->irq == NULL) { 481 device_printf(dev, "can't map interrupt\n"); 482 error = ENOMEM; 483 goto fail; 484 } 485 486 IWN_LOCK_INIT(sc); 487 488 /* Read hardware revision and attach. */ 489 sc->hw_type = (IWN_READ(sc, IWN_HW_REV) >> 4) & 0xf; 490 if (sc->hw_type == IWN_HW_REV_TYPE_4965) 491 error = iwn4965_attach(sc, pci_get_device(dev)); 492 else 493 error = iwn5000_attach(sc, pci_get_device(dev)); 494 if (error != 0) { 495 device_printf(dev, "could not attach device, error %d\n", 496 error); 497 goto fail; 498 } 499 500 if ((error = iwn_hw_prepare(sc)) != 0) { 501 device_printf(dev, "hardware not ready, error %d\n", error); 502 goto fail; 503 } 504 505 /* Allocate DMA memory for firmware transfers. */ 506 if ((error = iwn_alloc_fwmem(sc)) != 0) { 507 device_printf(dev, 508 "could not allocate memory for firmware, error %d\n", 509 error); 510 goto fail; 511 } 512 513 /* Allocate "Keep Warm" page. */ 514 if ((error = iwn_alloc_kw(sc)) != 0) { 515 device_printf(dev, 516 "could not allocate keep warm page, error %d\n", error); 517 goto fail; 518 } 519 520 /* Allocate ICT table for 5000 Series. */ 521 if (sc->hw_type != IWN_HW_REV_TYPE_4965 && 522 (error = iwn_alloc_ict(sc)) != 0) { 523 device_printf(dev, "could not allocate ICT table, error %d\n", 524 error); 525 goto fail; 526 } 527 528 /* Allocate TX scheduler "rings". */ 529 if ((error = iwn_alloc_sched(sc)) != 0) { 530 device_printf(dev, 531 "could not allocate TX scheduler rings, error %d\n", error); 532 goto fail; 533 } 534 535 /* Allocate TX rings (16 on 4965AGN, 20 on >=5000). */ 536 for (i = 0; i < sc->ntxqs; i++) { 537 if ((error = iwn_alloc_tx_ring(sc, &sc->txq[i], i)) != 0) { 538 device_printf(dev, 539 "could not allocate TX ring %d, error %d\n", i, 540 error); 541 goto fail; 542 } 543 } 544 545 /* Allocate RX ring. */ 546 if ((error = iwn_alloc_rx_ring(sc, &sc->rxq)) != 0) { 547 device_printf(dev, "could not allocate RX ring, error %d\n", 548 error); 549 goto fail; 550 } 551 552 /* Clear pending interrupts. */ 553 IWN_WRITE(sc, IWN_INT, 0xffffffff); 554 555 ifp = sc->sc_ifp = if_alloc(IFT_IEEE80211); 556 if (ifp == NULL) { 557 device_printf(dev, "can not allocate ifnet structure\n"); 558 goto fail; 559 } 560 561 ic = ifp->if_l2com; 562 ic->ic_ifp = ifp; 563 ic->ic_phytype = IEEE80211_T_OFDM; /* not only, but not used */ 564 ic->ic_opmode = IEEE80211_M_STA; /* default to BSS mode */ 565 566 /* Set device capabilities. */ 567 ic->ic_caps = 568 IEEE80211_C_STA /* station mode supported */ 569 | IEEE80211_C_MONITOR /* monitor mode supported */ 570 | IEEE80211_C_BGSCAN /* background scanning */ 571 | IEEE80211_C_TXPMGT /* tx power management */ 572 | IEEE80211_C_SHSLOT /* short slot time supported */ 573 | IEEE80211_C_WPA 574 | IEEE80211_C_SHPREAMBLE /* short preamble supported */ 575 #if 0 576 | IEEE80211_C_IBSS /* ibss/adhoc mode */ 577 #endif 578 | IEEE80211_C_WME /* WME */ 579 ; 580 581 /* Read MAC address, channels, etc from EEPROM. */ 582 if ((error = iwn_read_eeprom(sc, macaddr)) != 0) { 583 device_printf(dev, "could not read EEPROM, error %d\n", 584 error); 585 goto fail; 586 } 587 588 /* Count the number of available chains. */ 589 sc->ntxchains = 590 ((sc->txchainmask >> 2) & 1) + 591 ((sc->txchainmask >> 1) & 1) + 592 ((sc->txchainmask >> 0) & 1); 593 sc->nrxchains = 594 ((sc->rxchainmask >> 2) & 1) + 595 ((sc->rxchainmask >> 1) & 1) + 596 ((sc->rxchainmask >> 0) & 1); 597 if (bootverbose) { 598 device_printf(dev, "MIMO %dT%dR, %.4s, address %6D\n", 599 sc->ntxchains, sc->nrxchains, sc->eeprom_domain, 600 macaddr, ":"); 601 } 602 603 if (sc->sc_flags & IWN_FLAG_HAS_11N) { 604 ic->ic_rxstream = sc->nrxchains; 605 ic->ic_txstream = sc->ntxchains; 606 ic->ic_htcaps = 607 IEEE80211_HTCAP_SMPS_OFF /* SMPS mode disabled */ 608 | IEEE80211_HTCAP_SHORTGI20 /* short GI in 20MHz */ 609 | IEEE80211_HTCAP_CHWIDTH40 /* 40MHz channel width*/ 610 | IEEE80211_HTCAP_SHORTGI40 /* short GI in 40MHz */ 611 #ifdef notyet 612 | IEEE80211_HTCAP_GREENFIELD 613 #if IWN_RBUF_SIZE == 8192 614 | IEEE80211_HTCAP_MAXAMSDU_7935 /* max A-MSDU length */ 615 #else 616 | IEEE80211_HTCAP_MAXAMSDU_3839 /* max A-MSDU length */ 617 #endif 618 #endif 619 /* s/w capabilities */ 620 | IEEE80211_HTC_HT /* HT operation */ 621 | IEEE80211_HTC_AMPDU /* tx A-MPDU */ 622 #ifdef notyet 623 | IEEE80211_HTC_AMSDU /* tx A-MSDU */ 624 #endif 625 ; 626 } 627 628 if_initname(ifp, device_get_name(dev), device_get_unit(dev)); 629 ifp->if_softc = sc; 630 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 631 ifp->if_init = iwn_init; 632 ifp->if_ioctl = iwn_ioctl; 633 ifp->if_start = iwn_start; 634 IFQ_SET_MAXLEN(&ifp->if_snd, ifqmaxlen); 635 ifp->if_snd.ifq_drv_maxlen = ifqmaxlen; 636 IFQ_SET_READY(&ifp->if_snd); 637 638 ieee80211_ifattach(ic, macaddr); 639 ic->ic_vap_create = iwn_vap_create; 640 ic->ic_vap_delete = iwn_vap_delete; 641 ic->ic_raw_xmit = iwn_raw_xmit; 642 ic->ic_node_alloc = iwn_node_alloc; 643 sc->sc_ampdu_rx_start = ic->ic_ampdu_rx_start; 644 ic->ic_ampdu_rx_start = iwn_ampdu_rx_start; 645 sc->sc_ampdu_rx_stop = ic->ic_ampdu_rx_stop; 646 ic->ic_ampdu_rx_stop = iwn_ampdu_rx_stop; 647 sc->sc_addba_request = ic->ic_addba_request; 648 ic->ic_addba_request = iwn_addba_request; 649 sc->sc_addba_response = ic->ic_addba_response; 650 ic->ic_addba_response = iwn_addba_response; 651 sc->sc_addba_stop = ic->ic_addba_stop; 652 ic->ic_addba_stop = iwn_ampdu_tx_stop; 653 ic->ic_newassoc = iwn_newassoc; 654 ic->ic_wme.wme_update = iwn_updateedca; 655 ic->ic_update_mcast = iwn_update_mcast; 656 ic->ic_scan_start = iwn_scan_start; 657 ic->ic_scan_end = iwn_scan_end; 658 ic->ic_set_channel = iwn_set_channel; 659 ic->ic_scan_curchan = iwn_scan_curchan; 660 ic->ic_scan_mindwell = iwn_scan_mindwell; 661 ic->ic_setregdomain = iwn_setregdomain; 662 663 iwn_radiotap_attach(sc); 664 665 callout_init_mtx(&sc->calib_to, &sc->sc_mtx, 0); 666 callout_init_mtx(&sc->watchdog_to, &sc->sc_mtx, 0); 667 TASK_INIT(&sc->sc_reinit_task, 0, iwn_hw_reset, sc); 668 TASK_INIT(&sc->sc_radioon_task, 0, iwn_radio_on, sc); 669 TASK_INIT(&sc->sc_radiooff_task, 0, iwn_radio_off, sc); 670 671 iwn_sysctlattach(sc); 672 673 /* 674 * Hook our interrupt after all initialization is complete. 675 */ 676 error = bus_setup_intr(dev, sc->irq, INTR_TYPE_NET | INTR_MPSAFE, 677 NULL, iwn_intr, sc, &sc->sc_ih); 678 if (error != 0) { 679 device_printf(dev, "can't establish interrupt, error %d\n", 680 error); 681 goto fail; 682 } 683 684 if (bootverbose) 685 ieee80211_announce(ic); 686 return 0; 687 fail: 688 iwn_detach(dev); 689 return error; 690 } 691 692 static int 693 iwn4965_attach(struct iwn_softc *sc, uint16_t pid) 694 { 695 struct iwn_ops *ops = &sc->ops; 696 697 ops->load_firmware = iwn4965_load_firmware; 698 ops->read_eeprom = iwn4965_read_eeprom; 699 ops->post_alive = iwn4965_post_alive; 700 ops->nic_config = iwn4965_nic_config; 701 ops->update_sched = iwn4965_update_sched; 702 ops->get_temperature = iwn4965_get_temperature; 703 ops->get_rssi = iwn4965_get_rssi; 704 ops->set_txpower = iwn4965_set_txpower; 705 ops->init_gains = iwn4965_init_gains; 706 ops->set_gains = iwn4965_set_gains; 707 ops->add_node = iwn4965_add_node; 708 ops->tx_done = iwn4965_tx_done; 709 ops->ampdu_tx_start = iwn4965_ampdu_tx_start; 710 ops->ampdu_tx_stop = iwn4965_ampdu_tx_stop; 711 sc->ntxqs = IWN4965_NTXQUEUES; 712 sc->firstaggqueue = IWN4965_FIRSTAGGQUEUE; 713 sc->ndmachnls = IWN4965_NDMACHNLS; 714 sc->broadcast_id = IWN4965_ID_BROADCAST; 715 sc->rxonsz = IWN4965_RXONSZ; 716 sc->schedsz = IWN4965_SCHEDSZ; 717 sc->fw_text_maxsz = IWN4965_FW_TEXT_MAXSZ; 718 sc->fw_data_maxsz = IWN4965_FW_DATA_MAXSZ; 719 sc->fwsz = IWN4965_FWSZ; 720 sc->sched_txfact_addr = IWN4965_SCHED_TXFACT; 721 sc->limits = &iwn4965_sensitivity_limits; 722 sc->fwname = "iwn4965fw"; 723 /* Override chains masks, ROM is known to be broken. */ 724 sc->txchainmask = IWN_ANT_AB; 725 sc->rxchainmask = IWN_ANT_ABC; 726 727 return 0; 728 } 729 730 static int 731 iwn5000_attach(struct iwn_softc *sc, uint16_t pid) 732 { 733 struct iwn_ops *ops = &sc->ops; 734 735 ops->load_firmware = iwn5000_load_firmware; 736 ops->read_eeprom = iwn5000_read_eeprom; 737 ops->post_alive = iwn5000_post_alive; 738 ops->nic_config = iwn5000_nic_config; 739 ops->update_sched = iwn5000_update_sched; 740 ops->get_temperature = iwn5000_get_temperature; 741 ops->get_rssi = iwn5000_get_rssi; 742 ops->set_txpower = iwn5000_set_txpower; 743 ops->init_gains = iwn5000_init_gains; 744 ops->set_gains = iwn5000_set_gains; 745 ops->add_node = iwn5000_add_node; 746 ops->tx_done = iwn5000_tx_done; 747 ops->ampdu_tx_start = iwn5000_ampdu_tx_start; 748 ops->ampdu_tx_stop = iwn5000_ampdu_tx_stop; 749 sc->ntxqs = IWN5000_NTXQUEUES; 750 sc->firstaggqueue = IWN5000_FIRSTAGGQUEUE; 751 sc->ndmachnls = IWN5000_NDMACHNLS; 752 sc->broadcast_id = IWN5000_ID_BROADCAST; 753 sc->rxonsz = IWN5000_RXONSZ; 754 sc->schedsz = IWN5000_SCHEDSZ; 755 sc->fw_text_maxsz = IWN5000_FW_TEXT_MAXSZ; 756 sc->fw_data_maxsz = IWN5000_FW_DATA_MAXSZ; 757 sc->fwsz = IWN5000_FWSZ; 758 sc->sched_txfact_addr = IWN5000_SCHED_TXFACT; 759 sc->reset_noise_gain = IWN5000_PHY_CALIB_RESET_NOISE_GAIN; 760 sc->noise_gain = IWN5000_PHY_CALIB_NOISE_GAIN; 761 762 switch (sc->hw_type) { 763 case IWN_HW_REV_TYPE_5100: 764 sc->limits = &iwn5000_sensitivity_limits; 765 sc->fwname = "iwn5000fw"; 766 /* Override chains masks, ROM is known to be broken. */ 767 sc->txchainmask = IWN_ANT_B; 768 sc->rxchainmask = IWN_ANT_AB; 769 break; 770 case IWN_HW_REV_TYPE_5150: 771 sc->limits = &iwn5150_sensitivity_limits; 772 sc->fwname = "iwn5150fw"; 773 break; 774 case IWN_HW_REV_TYPE_5300: 775 case IWN_HW_REV_TYPE_5350: 776 sc->limits = &iwn5000_sensitivity_limits; 777 sc->fwname = "iwn5000fw"; 778 break; 779 case IWN_HW_REV_TYPE_1000: 780 sc->limits = &iwn1000_sensitivity_limits; 781 sc->fwname = "iwn1000fw"; 782 break; 783 case IWN_HW_REV_TYPE_6000: 784 sc->limits = &iwn6000_sensitivity_limits; 785 sc->fwname = "iwn6000fw"; 786 if (pid == 0x422c || pid == 0x4239) { 787 sc->sc_flags |= IWN_FLAG_INTERNAL_PA; 788 /* Override chains masks, ROM is known to be broken. */ 789 sc->txchainmask = IWN_ANT_BC; 790 sc->rxchainmask = IWN_ANT_BC; 791 } 792 break; 793 case IWN_HW_REV_TYPE_6050: 794 sc->limits = &iwn6000_sensitivity_limits; 795 sc->fwname = "iwn6050fw"; 796 /* Override chains masks, ROM is known to be broken. */ 797 sc->txchainmask = IWN_ANT_AB; 798 sc->rxchainmask = IWN_ANT_AB; 799 break; 800 case IWN_HW_REV_TYPE_6005: 801 sc->limits = &iwn6000_sensitivity_limits; 802 if (pid != 0x0082 && pid != 0x0085) { 803 sc->fwname = "iwn6000g2bfw"; 804 sc->sc_flags |= IWN_FLAG_ADV_BTCOEX; 805 } else 806 sc->fwname = "iwn6000g2afw"; 807 break; 808 default: 809 device_printf(sc->sc_dev, "adapter type %d not supported\n", 810 sc->hw_type); 811 return ENOTSUP; 812 } 813 return 0; 814 } 815 816 /* 817 * Attach the interface to 802.11 radiotap. 818 */ 819 static void 820 iwn_radiotap_attach(struct iwn_softc *sc) 821 { 822 struct ifnet *ifp = sc->sc_ifp; 823 struct ieee80211com *ic = ifp->if_l2com; 824 825 ieee80211_radiotap_attach(ic, 826 &sc->sc_txtap.wt_ihdr, sizeof(sc->sc_txtap), 827 IWN_TX_RADIOTAP_PRESENT, 828 &sc->sc_rxtap.wr_ihdr, sizeof(sc->sc_rxtap), 829 IWN_RX_RADIOTAP_PRESENT); 830 } 831 832 static void 833 iwn_sysctlattach(struct iwn_softc *sc) 834 { 835 struct sysctl_ctx_list *ctx = device_get_sysctl_ctx(sc->sc_dev); 836 struct sysctl_oid *tree = device_get_sysctl_tree(sc->sc_dev); 837 838 #ifdef IWN_DEBUG 839 sc->sc_debug = 0; 840 SYSCTL_ADD_INT(ctx, SYSCTL_CHILDREN(tree), OID_AUTO, 841 "debug", CTLFLAG_RW, &sc->sc_debug, 0, "control debugging printfs"); 842 #endif 843 } 844 845 static struct ieee80211vap * 846 iwn_vap_create(struct ieee80211com *ic, 847 const char name[IFNAMSIZ], int unit, int opmode, int flags, 848 const uint8_t bssid[IEEE80211_ADDR_LEN], 849 const uint8_t mac[IEEE80211_ADDR_LEN]) 850 { 851 struct iwn_vap *ivp; 852 struct ieee80211vap *vap; 853 854 if (!TAILQ_EMPTY(&ic->ic_vaps)) /* only one at a time */ 855 return NULL; 856 ivp = (struct iwn_vap *) malloc(sizeof(struct iwn_vap), 857 M_80211_VAP, M_NOWAIT | M_ZERO); 858 if (ivp == NULL) 859 return NULL; 860 vap = &ivp->iv_vap; 861 ieee80211_vap_setup(ic, vap, name, unit, opmode, flags, bssid, mac); 862 vap->iv_bmissthreshold = 10; /* override default */ 863 /* Override with driver methods. */ 864 ivp->iv_newstate = vap->iv_newstate; 865 vap->iv_newstate = iwn_newstate; 866 867 ieee80211_ratectl_init(vap); 868 /* Complete setup. */ 869 ieee80211_vap_attach(vap, iwn_media_change, ieee80211_media_status); 870 ic->ic_opmode = opmode; 871 return vap; 872 } 873 874 static void 875 iwn_vap_delete(struct ieee80211vap *vap) 876 { 877 struct iwn_vap *ivp = IWN_VAP(vap); 878 879 ieee80211_ratectl_deinit(vap); 880 ieee80211_vap_detach(vap); 881 free(ivp, M_80211_VAP); 882 } 883 884 static int 885 iwn_detach(device_t dev) 886 { 887 struct iwn_softc *sc = device_get_softc(dev); 888 struct ifnet *ifp = sc->sc_ifp; 889 struct ieee80211com *ic; 890 int qid; 891 892 if (ifp != NULL) { 893 ic = ifp->if_l2com; 894 895 ieee80211_draintask(ic, &sc->sc_reinit_task); 896 ieee80211_draintask(ic, &sc->sc_radioon_task); 897 ieee80211_draintask(ic, &sc->sc_radiooff_task); 898 899 iwn_stop(sc); 900 callout_drain(&sc->watchdog_to); 901 callout_drain(&sc->calib_to); 902 ieee80211_ifdetach(ic); 903 } 904 905 /* Uninstall interrupt handler. */ 906 if (sc->irq != NULL) { 907 bus_teardown_intr(dev, sc->irq, sc->sc_ih); 908 bus_release_resource(dev, SYS_RES_IRQ, sc->irq_rid, sc->irq); 909 if (sc->irq_rid == 1) 910 pci_release_msi(dev); 911 } 912 913 /* Free DMA resources. */ 914 iwn_free_rx_ring(sc, &sc->rxq); 915 for (qid = 0; qid < sc->ntxqs; qid++) 916 iwn_free_tx_ring(sc, &sc->txq[qid]); 917 iwn_free_sched(sc); 918 iwn_free_kw(sc); 919 if (sc->ict != NULL) 920 iwn_free_ict(sc); 921 iwn_free_fwmem(sc); 922 923 if (sc->mem != NULL) 924 bus_release_resource(dev, SYS_RES_MEMORY, sc->mem_rid, sc->mem); 925 926 if (ifp != NULL) 927 if_free(ifp); 928 929 IWN_LOCK_DESTROY(sc); 930 return 0; 931 } 932 933 static int 934 iwn_shutdown(device_t dev) 935 { 936 struct iwn_softc *sc = device_get_softc(dev); 937 938 iwn_stop(sc); 939 return 0; 940 } 941 942 static int 943 iwn_suspend(device_t dev) 944 { 945 struct iwn_softc *sc = device_get_softc(dev); 946 struct ifnet *ifp = sc->sc_ifp; 947 struct ieee80211com *ic = ifp->if_l2com; 948 struct ieee80211vap *vap = TAILQ_FIRST(&ic->ic_vaps); 949 950 iwn_stop(sc); 951 if (vap != NULL) 952 ieee80211_stop(vap); 953 return 0; 954 } 955 956 static int 957 iwn_resume(device_t dev) 958 { 959 struct iwn_softc *sc = device_get_softc(dev); 960 struct ifnet *ifp = sc->sc_ifp; 961 struct ieee80211com *ic = ifp->if_l2com; 962 struct ieee80211vap *vap = TAILQ_FIRST(&ic->ic_vaps); 963 964 /* Clear device-specific "PCI retry timeout" register (41h). */ 965 pci_write_config(dev, 0x41, 0, 1); 966 967 if (ifp->if_flags & IFF_UP) { 968 iwn_init(sc); 969 if (vap != NULL) 970 ieee80211_init(vap); 971 if (ifp->if_drv_flags & IFF_DRV_RUNNING) 972 iwn_start(ifp); 973 } 974 return 0; 975 } 976 977 static int 978 iwn_nic_lock(struct iwn_softc *sc) 979 { 980 int ntries; 981 982 /* Request exclusive access to NIC. */ 983 IWN_SETBITS(sc, IWN_GP_CNTRL, IWN_GP_CNTRL_MAC_ACCESS_REQ); 984 985 /* Spin until we actually get the lock. */ 986 for (ntries = 0; ntries < 1000; ntries++) { 987 if ((IWN_READ(sc, IWN_GP_CNTRL) & 988 (IWN_GP_CNTRL_MAC_ACCESS_ENA | IWN_GP_CNTRL_SLEEP)) == 989 IWN_GP_CNTRL_MAC_ACCESS_ENA) 990 return 0; 991 DELAY(10); 992 } 993 return ETIMEDOUT; 994 } 995 996 static __inline void 997 iwn_nic_unlock(struct iwn_softc *sc) 998 { 999 IWN_CLRBITS(sc, IWN_GP_CNTRL, IWN_GP_CNTRL_MAC_ACCESS_REQ); 1000 } 1001 1002 static __inline uint32_t 1003 iwn_prph_read(struct iwn_softc *sc, uint32_t addr) 1004 { 1005 IWN_WRITE(sc, IWN_PRPH_RADDR, IWN_PRPH_DWORD | addr); 1006 IWN_BARRIER_READ_WRITE(sc); 1007 return IWN_READ(sc, IWN_PRPH_RDATA); 1008 } 1009 1010 static __inline void 1011 iwn_prph_write(struct iwn_softc *sc, uint32_t addr, uint32_t data) 1012 { 1013 IWN_WRITE(sc, IWN_PRPH_WADDR, IWN_PRPH_DWORD | addr); 1014 IWN_BARRIER_WRITE(sc); 1015 IWN_WRITE(sc, IWN_PRPH_WDATA, data); 1016 } 1017 1018 static __inline void 1019 iwn_prph_setbits(struct iwn_softc *sc, uint32_t addr, uint32_t mask) 1020 { 1021 iwn_prph_write(sc, addr, iwn_prph_read(sc, addr) | mask); 1022 } 1023 1024 static __inline void 1025 iwn_prph_clrbits(struct iwn_softc *sc, uint32_t addr, uint32_t mask) 1026 { 1027 iwn_prph_write(sc, addr, iwn_prph_read(sc, addr) & ~mask); 1028 } 1029 1030 static __inline void 1031 iwn_prph_write_region_4(struct iwn_softc *sc, uint32_t addr, 1032 const uint32_t *data, int count) 1033 { 1034 for (; count > 0; count--, data++, addr += 4) 1035 iwn_prph_write(sc, addr, *data); 1036 } 1037 1038 static __inline uint32_t 1039 iwn_mem_read(struct iwn_softc *sc, uint32_t addr) 1040 { 1041 IWN_WRITE(sc, IWN_MEM_RADDR, addr); 1042 IWN_BARRIER_READ_WRITE(sc); 1043 return IWN_READ(sc, IWN_MEM_RDATA); 1044 } 1045 1046 static __inline void 1047 iwn_mem_write(struct iwn_softc *sc, uint32_t addr, uint32_t data) 1048 { 1049 IWN_WRITE(sc, IWN_MEM_WADDR, addr); 1050 IWN_BARRIER_WRITE(sc); 1051 IWN_WRITE(sc, IWN_MEM_WDATA, data); 1052 } 1053 1054 static __inline void 1055 iwn_mem_write_2(struct iwn_softc *sc, uint32_t addr, uint16_t data) 1056 { 1057 uint32_t tmp; 1058 1059 tmp = iwn_mem_read(sc, addr & ~3); 1060 if (addr & 3) 1061 tmp = (tmp & 0x0000ffff) | data << 16; 1062 else 1063 tmp = (tmp & 0xffff0000) | data; 1064 iwn_mem_write(sc, addr & ~3, tmp); 1065 } 1066 1067 static __inline void 1068 iwn_mem_read_region_4(struct iwn_softc *sc, uint32_t addr, uint32_t *data, 1069 int count) 1070 { 1071 for (; count > 0; count--, addr += 4) 1072 *data++ = iwn_mem_read(sc, addr); 1073 } 1074 1075 static __inline void 1076 iwn_mem_set_region_4(struct iwn_softc *sc, uint32_t addr, uint32_t val, 1077 int count) 1078 { 1079 for (; count > 0; count--, addr += 4) 1080 iwn_mem_write(sc, addr, val); 1081 } 1082 1083 static int 1084 iwn_eeprom_lock(struct iwn_softc *sc) 1085 { 1086 int i, ntries; 1087 1088 for (i = 0; i < 100; i++) { 1089 /* Request exclusive access to EEPROM. */ 1090 IWN_SETBITS(sc, IWN_HW_IF_CONFIG, 1091 IWN_HW_IF_CONFIG_EEPROM_LOCKED); 1092 1093 /* Spin until we actually get the lock. */ 1094 for (ntries = 0; ntries < 100; ntries++) { 1095 if (IWN_READ(sc, IWN_HW_IF_CONFIG) & 1096 IWN_HW_IF_CONFIG_EEPROM_LOCKED) 1097 return 0; 1098 DELAY(10); 1099 } 1100 } 1101 return ETIMEDOUT; 1102 } 1103 1104 static __inline void 1105 iwn_eeprom_unlock(struct iwn_softc *sc) 1106 { 1107 IWN_CLRBITS(sc, IWN_HW_IF_CONFIG, IWN_HW_IF_CONFIG_EEPROM_LOCKED); 1108 } 1109 1110 /* 1111 * Initialize access by host to One Time Programmable ROM. 1112 * NB: This kind of ROM can be found on 1000 or 6000 Series only. 1113 */ 1114 static int 1115 iwn_init_otprom(struct iwn_softc *sc) 1116 { 1117 uint16_t prev, base, next; 1118 int count, error; 1119 1120 /* Wait for clock stabilization before accessing prph. */ 1121 if ((error = iwn_clock_wait(sc)) != 0) 1122 return error; 1123 1124 if ((error = iwn_nic_lock(sc)) != 0) 1125 return error; 1126 iwn_prph_setbits(sc, IWN_APMG_PS, IWN_APMG_PS_RESET_REQ); 1127 DELAY(5); 1128 iwn_prph_clrbits(sc, IWN_APMG_PS, IWN_APMG_PS_RESET_REQ); 1129 iwn_nic_unlock(sc); 1130 1131 /* Set auto clock gate disable bit for HW with OTP shadow RAM. */ 1132 if (sc->hw_type != IWN_HW_REV_TYPE_1000) { 1133 IWN_SETBITS(sc, IWN_DBG_LINK_PWR_MGMT, 1134 IWN_RESET_LINK_PWR_MGMT_DIS); 1135 } 1136 IWN_CLRBITS(sc, IWN_EEPROM_GP, IWN_EEPROM_GP_IF_OWNER); 1137 /* Clear ECC status. */ 1138 IWN_SETBITS(sc, IWN_OTP_GP, 1139 IWN_OTP_GP_ECC_CORR_STTS | IWN_OTP_GP_ECC_UNCORR_STTS); 1140 1141 /* 1142 * Find the block before last block (contains the EEPROM image) 1143 * for HW without OTP shadow RAM. 1144 */ 1145 if (sc->hw_type == IWN_HW_REV_TYPE_1000) { 1146 /* Switch to absolute addressing mode. */ 1147 IWN_CLRBITS(sc, IWN_OTP_GP, IWN_OTP_GP_RELATIVE_ACCESS); 1148 base = prev = 0; 1149 for (count = 0; count < IWN1000_OTP_NBLOCKS; count++) { 1150 error = iwn_read_prom_data(sc, base, &next, 2); 1151 if (error != 0) 1152 return error; 1153 if (next == 0) /* End of linked-list. */ 1154 break; 1155 prev = base; 1156 base = le16toh(next); 1157 } 1158 if (count == 0 || count == IWN1000_OTP_NBLOCKS) 1159 return EIO; 1160 /* Skip "next" word. */ 1161 sc->prom_base = prev + 1; 1162 } 1163 return 0; 1164 } 1165 1166 static int 1167 iwn_read_prom_data(struct iwn_softc *sc, uint32_t addr, void *data, int count) 1168 { 1169 uint8_t *out = data; 1170 uint32_t val, tmp; 1171 int ntries; 1172 1173 addr += sc->prom_base; 1174 for (; count > 0; count -= 2, addr++) { 1175 IWN_WRITE(sc, IWN_EEPROM, addr << 2); 1176 for (ntries = 0; ntries < 10; ntries++) { 1177 val = IWN_READ(sc, IWN_EEPROM); 1178 if (val & IWN_EEPROM_READ_VALID) 1179 break; 1180 DELAY(5); 1181 } 1182 if (ntries == 10) { 1183 device_printf(sc->sc_dev, 1184 "timeout reading ROM at 0x%x\n", addr); 1185 return ETIMEDOUT; 1186 } 1187 if (sc->sc_flags & IWN_FLAG_HAS_OTPROM) { 1188 /* OTPROM, check for ECC errors. */ 1189 tmp = IWN_READ(sc, IWN_OTP_GP); 1190 if (tmp & IWN_OTP_GP_ECC_UNCORR_STTS) { 1191 device_printf(sc->sc_dev, 1192 "OTPROM ECC error at 0x%x\n", addr); 1193 return EIO; 1194 } 1195 if (tmp & IWN_OTP_GP_ECC_CORR_STTS) { 1196 /* Correctable ECC error, clear bit. */ 1197 IWN_SETBITS(sc, IWN_OTP_GP, 1198 IWN_OTP_GP_ECC_CORR_STTS); 1199 } 1200 } 1201 *out++ = val >> 16; 1202 if (count > 1) 1203 *out++ = val >> 24; 1204 } 1205 return 0; 1206 } 1207 1208 static void 1209 iwn_dma_map_addr(void *arg, bus_dma_segment_t *segs, int nsegs, int error) 1210 { 1211 if (error != 0) 1212 return; 1213 KASSERT(nsegs == 1, ("too many DMA segments, %d should be 1", nsegs)); 1214 *(bus_addr_t *)arg = segs[0].ds_addr; 1215 } 1216 1217 static int 1218 iwn_dma_contig_alloc(struct iwn_softc *sc, struct iwn_dma_info *dma, 1219 void **kvap, bus_size_t size, bus_size_t alignment) 1220 { 1221 int error; 1222 1223 dma->tag = NULL; 1224 dma->size = size; 1225 1226 error = bus_dma_tag_create(bus_get_dma_tag(sc->sc_dev), alignment, 1227 0, BUS_SPACE_MAXADDR_32BIT, BUS_SPACE_MAXADDR, NULL, NULL, size, 1228 1, size, BUS_DMA_NOWAIT, NULL, NULL, &dma->tag); 1229 if (error != 0) 1230 goto fail; 1231 1232 error = bus_dmamem_alloc(dma->tag, (void **)&dma->vaddr, 1233 BUS_DMA_NOWAIT | BUS_DMA_ZERO | BUS_DMA_COHERENT, &dma->map); 1234 if (error != 0) 1235 goto fail; 1236 1237 error = bus_dmamap_load(dma->tag, dma->map, dma->vaddr, size, 1238 iwn_dma_map_addr, &dma->paddr, BUS_DMA_NOWAIT); 1239 if (error != 0) 1240 goto fail; 1241 1242 bus_dmamap_sync(dma->tag, dma->map, BUS_DMASYNC_PREWRITE); 1243 1244 if (kvap != NULL) 1245 *kvap = dma->vaddr; 1246 1247 return 0; 1248 1249 fail: iwn_dma_contig_free(dma); 1250 return error; 1251 } 1252 1253 static void 1254 iwn_dma_contig_free(struct iwn_dma_info *dma) 1255 { 1256 if (dma->map != NULL) { 1257 if (dma->vaddr != NULL) { 1258 bus_dmamap_sync(dma->tag, dma->map, 1259 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); 1260 bus_dmamap_unload(dma->tag, dma->map); 1261 bus_dmamem_free(dma->tag, &dma->vaddr, dma->map); 1262 dma->vaddr = NULL; 1263 } 1264 bus_dmamap_destroy(dma->tag, dma->map); 1265 dma->map = NULL; 1266 } 1267 if (dma->tag != NULL) { 1268 bus_dma_tag_destroy(dma->tag); 1269 dma->tag = NULL; 1270 } 1271 } 1272 1273 static int 1274 iwn_alloc_sched(struct iwn_softc *sc) 1275 { 1276 /* TX scheduler rings must be aligned on a 1KB boundary. */ 1277 return iwn_dma_contig_alloc(sc, &sc->sched_dma, (void **)&sc->sched, 1278 sc->schedsz, 1024); 1279 } 1280 1281 static void 1282 iwn_free_sched(struct iwn_softc *sc) 1283 { 1284 iwn_dma_contig_free(&sc->sched_dma); 1285 } 1286 1287 static int 1288 iwn_alloc_kw(struct iwn_softc *sc) 1289 { 1290 /* "Keep Warm" page must be aligned on a 4KB boundary. */ 1291 return iwn_dma_contig_alloc(sc, &sc->kw_dma, NULL, 4096, 4096); 1292 } 1293 1294 static void 1295 iwn_free_kw(struct iwn_softc *sc) 1296 { 1297 iwn_dma_contig_free(&sc->kw_dma); 1298 } 1299 1300 static int 1301 iwn_alloc_ict(struct iwn_softc *sc) 1302 { 1303 /* ICT table must be aligned on a 4KB boundary. */ 1304 return iwn_dma_contig_alloc(sc, &sc->ict_dma, (void **)&sc->ict, 1305 IWN_ICT_SIZE, 4096); 1306 } 1307 1308 static void 1309 iwn_free_ict(struct iwn_softc *sc) 1310 { 1311 iwn_dma_contig_free(&sc->ict_dma); 1312 } 1313 1314 static int 1315 iwn_alloc_fwmem(struct iwn_softc *sc) 1316 { 1317 /* Must be aligned on a 16-byte boundary. */ 1318 return iwn_dma_contig_alloc(sc, &sc->fw_dma, NULL, sc->fwsz, 16); 1319 } 1320 1321 static void 1322 iwn_free_fwmem(struct iwn_softc *sc) 1323 { 1324 iwn_dma_contig_free(&sc->fw_dma); 1325 } 1326 1327 static int 1328 iwn_alloc_rx_ring(struct iwn_softc *sc, struct iwn_rx_ring *ring) 1329 { 1330 bus_size_t size; 1331 int i, error; 1332 1333 ring->cur = 0; 1334 1335 /* Allocate RX descriptors (256-byte aligned). */ 1336 size = IWN_RX_RING_COUNT * sizeof (uint32_t); 1337 error = iwn_dma_contig_alloc(sc, &ring->desc_dma, (void **)&ring->desc, 1338 size, 256); 1339 if (error != 0) { 1340 device_printf(sc->sc_dev, 1341 "%s: could not allocate RX ring DMA memory, error %d\n", 1342 __func__, error); 1343 goto fail; 1344 } 1345 1346 /* Allocate RX status area (16-byte aligned). */ 1347 error = iwn_dma_contig_alloc(sc, &ring->stat_dma, (void **)&ring->stat, 1348 sizeof (struct iwn_rx_status), 16); 1349 if (error != 0) { 1350 device_printf(sc->sc_dev, 1351 "%s: could not allocate RX status DMA memory, error %d\n", 1352 __func__, error); 1353 goto fail; 1354 } 1355 1356 /* Create RX buffer DMA tag. */ 1357 error = bus_dma_tag_create(bus_get_dma_tag(sc->sc_dev), 1, 0, 1358 BUS_SPACE_MAXADDR_32BIT, BUS_SPACE_MAXADDR, NULL, NULL, 1359 IWN_RBUF_SIZE, 1, IWN_RBUF_SIZE, BUS_DMA_NOWAIT, NULL, NULL, 1360 &ring->data_dmat); 1361 if (error != 0) { 1362 device_printf(sc->sc_dev, 1363 "%s: could not create RX buf DMA tag, error %d\n", 1364 __func__, error); 1365 goto fail; 1366 } 1367 1368 /* 1369 * Allocate and map RX buffers. 1370 */ 1371 for (i = 0; i < IWN_RX_RING_COUNT; i++) { 1372 struct iwn_rx_data *data = &ring->data[i]; 1373 bus_addr_t paddr; 1374 1375 error = bus_dmamap_create(ring->data_dmat, 0, &data->map); 1376 if (error != 0) { 1377 device_printf(sc->sc_dev, 1378 "%s: could not create RX buf DMA map, error %d\n", 1379 __func__, error); 1380 goto fail; 1381 } 1382 1383 data->m = m_getjcl(M_DONTWAIT, MT_DATA, M_PKTHDR, 1384 IWN_RBUF_SIZE); 1385 if (data->m == NULL) { 1386 device_printf(sc->sc_dev, 1387 "%s: could not allocate RX mbuf\n", __func__); 1388 error = ENOBUFS; 1389 goto fail; 1390 } 1391 1392 error = bus_dmamap_load(ring->data_dmat, data->map, 1393 mtod(data->m, void *), IWN_RBUF_SIZE, iwn_dma_map_addr, 1394 &paddr, BUS_DMA_NOWAIT); 1395 if (error != 0 && error != EFBIG) { 1396 device_printf(sc->sc_dev, 1397 "%s: can't not map mbuf, error %d\n", __func__, 1398 error); 1399 goto fail; 1400 } 1401 1402 /* Set physical address of RX buffer (256-byte aligned). */ 1403 ring->desc[i] = htole32(paddr >> 8); 1404 } 1405 1406 bus_dmamap_sync(ring->desc_dma.tag, ring->desc_dma.map, 1407 BUS_DMASYNC_PREWRITE); 1408 1409 return 0; 1410 1411 fail: iwn_free_rx_ring(sc, ring); 1412 return error; 1413 } 1414 1415 static void 1416 iwn_reset_rx_ring(struct iwn_softc *sc, struct iwn_rx_ring *ring) 1417 { 1418 int ntries; 1419 1420 if (iwn_nic_lock(sc) == 0) { 1421 IWN_WRITE(sc, IWN_FH_RX_CONFIG, 0); 1422 for (ntries = 0; ntries < 1000; ntries++) { 1423 if (IWN_READ(sc, IWN_FH_RX_STATUS) & 1424 IWN_FH_RX_STATUS_IDLE) 1425 break; 1426 DELAY(10); 1427 } 1428 iwn_nic_unlock(sc); 1429 } 1430 ring->cur = 0; 1431 sc->last_rx_valid = 0; 1432 } 1433 1434 static void 1435 iwn_free_rx_ring(struct iwn_softc *sc, struct iwn_rx_ring *ring) 1436 { 1437 int i; 1438 1439 iwn_dma_contig_free(&ring->desc_dma); 1440 iwn_dma_contig_free(&ring->stat_dma); 1441 1442 for (i = 0; i < IWN_RX_RING_COUNT; i++) { 1443 struct iwn_rx_data *data = &ring->data[i]; 1444 1445 if (data->m != NULL) { 1446 bus_dmamap_sync(ring->data_dmat, data->map, 1447 BUS_DMASYNC_POSTREAD); 1448 bus_dmamap_unload(ring->data_dmat, data->map); 1449 m_freem(data->m); 1450 data->m = NULL; 1451 } 1452 if (data->map != NULL) 1453 bus_dmamap_destroy(ring->data_dmat, data->map); 1454 } 1455 if (ring->data_dmat != NULL) { 1456 bus_dma_tag_destroy(ring->data_dmat); 1457 ring->data_dmat = NULL; 1458 } 1459 } 1460 1461 static int 1462 iwn_alloc_tx_ring(struct iwn_softc *sc, struct iwn_tx_ring *ring, int qid) 1463 { 1464 bus_addr_t paddr; 1465 bus_size_t size; 1466 int i, error; 1467 1468 ring->qid = qid; 1469 ring->queued = 0; 1470 ring->cur = 0; 1471 1472 /* Allocate TX descriptors (256-byte aligned). */ 1473 size = IWN_TX_RING_COUNT * sizeof (struct iwn_tx_desc); 1474 error = iwn_dma_contig_alloc(sc, &ring->desc_dma, (void **)&ring->desc, 1475 size, 256); 1476 if (error != 0) { 1477 device_printf(sc->sc_dev, 1478 "%s: could not allocate TX ring DMA memory, error %d\n", 1479 __func__, error); 1480 goto fail; 1481 } 1482 1483 size = IWN_TX_RING_COUNT * sizeof (struct iwn_tx_cmd); 1484 error = iwn_dma_contig_alloc(sc, &ring->cmd_dma, (void **)&ring->cmd, 1485 size, 4); 1486 if (error != 0) { 1487 device_printf(sc->sc_dev, 1488 "%s: could not allocate TX cmd DMA memory, error %d\n", 1489 __func__, error); 1490 goto fail; 1491 } 1492 1493 error = bus_dma_tag_create(bus_get_dma_tag(sc->sc_dev), 1, 0, 1494 BUS_SPACE_MAXADDR_32BIT, BUS_SPACE_MAXADDR, NULL, NULL, MCLBYTES, 1495 IWN_MAX_SCATTER - 1, MCLBYTES, BUS_DMA_NOWAIT, NULL, NULL, 1496 &ring->data_dmat); 1497 if (error != 0) { 1498 device_printf(sc->sc_dev, 1499 "%s: could not create TX buf DMA tag, error %d\n", 1500 __func__, error); 1501 goto fail; 1502 } 1503 1504 paddr = ring->cmd_dma.paddr; 1505 for (i = 0; i < IWN_TX_RING_COUNT; i++) { 1506 struct iwn_tx_data *data = &ring->data[i]; 1507 1508 data->cmd_paddr = paddr; 1509 data->scratch_paddr = paddr + 12; 1510 paddr += sizeof (struct iwn_tx_cmd); 1511 1512 error = bus_dmamap_create(ring->data_dmat, 0, &data->map); 1513 if (error != 0) { 1514 device_printf(sc->sc_dev, 1515 "%s: could not create TX buf DMA map, error %d\n", 1516 __func__, error); 1517 goto fail; 1518 } 1519 } 1520 return 0; 1521 1522 fail: iwn_free_tx_ring(sc, ring); 1523 return error; 1524 } 1525 1526 static void 1527 iwn_reset_tx_ring(struct iwn_softc *sc, struct iwn_tx_ring *ring) 1528 { 1529 int i; 1530 1531 for (i = 0; i < IWN_TX_RING_COUNT; i++) { 1532 struct iwn_tx_data *data = &ring->data[i]; 1533 1534 if (data->m != NULL) { 1535 bus_dmamap_sync(ring->data_dmat, data->map, 1536 BUS_DMASYNC_POSTWRITE); 1537 bus_dmamap_unload(ring->data_dmat, data->map); 1538 m_freem(data->m); 1539 data->m = NULL; 1540 } 1541 } 1542 /* Clear TX descriptors. */ 1543 memset(ring->desc, 0, ring->desc_dma.size); 1544 bus_dmamap_sync(ring->desc_dma.tag, ring->desc_dma.map, 1545 BUS_DMASYNC_PREWRITE); 1546 sc->qfullmsk &= ~(1 << ring->qid); 1547 ring->queued = 0; 1548 ring->cur = 0; 1549 } 1550 1551 static void 1552 iwn_free_tx_ring(struct iwn_softc *sc, struct iwn_tx_ring *ring) 1553 { 1554 int i; 1555 1556 iwn_dma_contig_free(&ring->desc_dma); 1557 iwn_dma_contig_free(&ring->cmd_dma); 1558 1559 for (i = 0; i < IWN_TX_RING_COUNT; i++) { 1560 struct iwn_tx_data *data = &ring->data[i]; 1561 1562 if (data->m != NULL) { 1563 bus_dmamap_sync(ring->data_dmat, data->map, 1564 BUS_DMASYNC_POSTWRITE); 1565 bus_dmamap_unload(ring->data_dmat, data->map); 1566 m_freem(data->m); 1567 } 1568 if (data->map != NULL) 1569 bus_dmamap_destroy(ring->data_dmat, data->map); 1570 } 1571 if (ring->data_dmat != NULL) { 1572 bus_dma_tag_destroy(ring->data_dmat); 1573 ring->data_dmat = NULL; 1574 } 1575 } 1576 1577 static void 1578 iwn5000_ict_reset(struct iwn_softc *sc) 1579 { 1580 /* Disable interrupts. */ 1581 IWN_WRITE(sc, IWN_INT_MASK, 0); 1582 1583 /* Reset ICT table. */ 1584 memset(sc->ict, 0, IWN_ICT_SIZE); 1585 sc->ict_cur = 0; 1586 1587 /* Set physical address of ICT table (4KB aligned). */ 1588 DPRINTF(sc, IWN_DEBUG_RESET, "%s: enabling ICT\n", __func__); 1589 IWN_WRITE(sc, IWN_DRAM_INT_TBL, IWN_DRAM_INT_TBL_ENABLE | 1590 IWN_DRAM_INT_TBL_WRAP_CHECK | sc->ict_dma.paddr >> 12); 1591 1592 /* Enable periodic RX interrupt. */ 1593 sc->int_mask |= IWN_INT_RX_PERIODIC; 1594 /* Switch to ICT interrupt mode in driver. */ 1595 sc->sc_flags |= IWN_FLAG_USE_ICT; 1596 1597 /* Re-enable interrupts. */ 1598 IWN_WRITE(sc, IWN_INT, 0xffffffff); 1599 IWN_WRITE(sc, IWN_INT_MASK, sc->int_mask); 1600 } 1601 1602 static int 1603 iwn_read_eeprom(struct iwn_softc *sc, uint8_t macaddr[IEEE80211_ADDR_LEN]) 1604 { 1605 struct iwn_ops *ops = &sc->ops; 1606 uint16_t val; 1607 int error; 1608 1609 /* Check whether adapter has an EEPROM or an OTPROM. */ 1610 if (sc->hw_type >= IWN_HW_REV_TYPE_1000 && 1611 (IWN_READ(sc, IWN_OTP_GP) & IWN_OTP_GP_DEV_SEL_OTP)) 1612 sc->sc_flags |= IWN_FLAG_HAS_OTPROM; 1613 DPRINTF(sc, IWN_DEBUG_RESET, "%s found\n", 1614 (sc->sc_flags & IWN_FLAG_HAS_OTPROM) ? "OTPROM" : "EEPROM"); 1615 1616 /* Adapter has to be powered on for EEPROM access to work. */ 1617 if ((error = iwn_apm_init(sc)) != 0) { 1618 device_printf(sc->sc_dev, 1619 "%s: could not power ON adapter, error %d\n", __func__, 1620 error); 1621 return error; 1622 } 1623 1624 if ((IWN_READ(sc, IWN_EEPROM_GP) & 0x7) == 0) { 1625 device_printf(sc->sc_dev, "%s: bad ROM signature\n", __func__); 1626 return EIO; 1627 } 1628 if ((error = iwn_eeprom_lock(sc)) != 0) { 1629 device_printf(sc->sc_dev, "%s: could not lock ROM, error %d\n", 1630 __func__, error); 1631 return error; 1632 } 1633 if (sc->sc_flags & IWN_FLAG_HAS_OTPROM) { 1634 if ((error = iwn_init_otprom(sc)) != 0) { 1635 device_printf(sc->sc_dev, 1636 "%s: could not initialize OTPROM, error %d\n", 1637 __func__, error); 1638 return error; 1639 } 1640 } 1641 1642 iwn_read_prom_data(sc, IWN_EEPROM_SKU_CAP, &val, 2); 1643 DPRINTF(sc, IWN_DEBUG_RESET, "SKU capabilities=0x%04x\n", le16toh(val)); 1644 /* Check if HT support is bonded out. */ 1645 if (val & htole16(IWN_EEPROM_SKU_CAP_11N)) 1646 sc->sc_flags |= IWN_FLAG_HAS_11N; 1647 1648 iwn_read_prom_data(sc, IWN_EEPROM_RFCFG, &val, 2); 1649 sc->rfcfg = le16toh(val); 1650 DPRINTF(sc, IWN_DEBUG_RESET, "radio config=0x%04x\n", sc->rfcfg); 1651 /* Read Tx/Rx chains from ROM unless it's known to be broken. */ 1652 if (sc->txchainmask == 0) 1653 sc->txchainmask = IWN_RFCFG_TXANTMSK(sc->rfcfg); 1654 if (sc->rxchainmask == 0) 1655 sc->rxchainmask = IWN_RFCFG_RXANTMSK(sc->rfcfg); 1656 1657 /* Read MAC address. */ 1658 iwn_read_prom_data(sc, IWN_EEPROM_MAC, macaddr, 6); 1659 1660 /* Read adapter-specific information from EEPROM. */ 1661 ops->read_eeprom(sc); 1662 1663 iwn_apm_stop(sc); /* Power OFF adapter. */ 1664 1665 iwn_eeprom_unlock(sc); 1666 return 0; 1667 } 1668 1669 static void 1670 iwn4965_read_eeprom(struct iwn_softc *sc) 1671 { 1672 uint32_t addr; 1673 uint16_t val; 1674 int i; 1675 1676 /* Read regulatory domain (4 ASCII characters). */ 1677 iwn_read_prom_data(sc, IWN4965_EEPROM_DOMAIN, sc->eeprom_domain, 4); 1678 1679 /* Read the list of authorized channels (20MHz ones only). */ 1680 for (i = 0; i < 7; i++) { 1681 addr = iwn4965_regulatory_bands[i]; 1682 iwn_read_eeprom_channels(sc, i, addr); 1683 } 1684 1685 /* Read maximum allowed TX power for 2GHz and 5GHz bands. */ 1686 iwn_read_prom_data(sc, IWN4965_EEPROM_MAXPOW, &val, 2); 1687 sc->maxpwr2GHz = val & 0xff; 1688 sc->maxpwr5GHz = val >> 8; 1689 /* Check that EEPROM values are within valid range. */ 1690 if (sc->maxpwr5GHz < 20 || sc->maxpwr5GHz > 50) 1691 sc->maxpwr5GHz = 38; 1692 if (sc->maxpwr2GHz < 20 || sc->maxpwr2GHz > 50) 1693 sc->maxpwr2GHz = 38; 1694 DPRINTF(sc, IWN_DEBUG_RESET, "maxpwr 2GHz=%d 5GHz=%d\n", 1695 sc->maxpwr2GHz, sc->maxpwr5GHz); 1696 1697 /* Read samples for each TX power group. */ 1698 iwn_read_prom_data(sc, IWN4965_EEPROM_BANDS, sc->bands, 1699 sizeof sc->bands); 1700 1701 /* Read voltage at which samples were taken. */ 1702 iwn_read_prom_data(sc, IWN4965_EEPROM_VOLTAGE, &val, 2); 1703 sc->eeprom_voltage = (int16_t)le16toh(val); 1704 DPRINTF(sc, IWN_DEBUG_RESET, "voltage=%d (in 0.3V)\n", 1705 sc->eeprom_voltage); 1706 1707 #ifdef IWN_DEBUG 1708 /* Print samples. */ 1709 if (sc->sc_debug & IWN_DEBUG_ANY) { 1710 for (i = 0; i < IWN_NBANDS; i++) 1711 iwn4965_print_power_group(sc, i); 1712 } 1713 #endif 1714 } 1715 1716 #ifdef IWN_DEBUG 1717 static void 1718 iwn4965_print_power_group(struct iwn_softc *sc, int i) 1719 { 1720 struct iwn4965_eeprom_band *band = &sc->bands[i]; 1721 struct iwn4965_eeprom_chan_samples *chans = band->chans; 1722 int j, c; 1723 1724 printf("===band %d===\n", i); 1725 printf("chan lo=%d, chan hi=%d\n", band->lo, band->hi); 1726 printf("chan1 num=%d\n", chans[0].num); 1727 for (c = 0; c < 2; c++) { 1728 for (j = 0; j < IWN_NSAMPLES; j++) { 1729 printf("chain %d, sample %d: temp=%d gain=%d " 1730 "power=%d pa_det=%d\n", c, j, 1731 chans[0].samples[c][j].temp, 1732 chans[0].samples[c][j].gain, 1733 chans[0].samples[c][j].power, 1734 chans[0].samples[c][j].pa_det); 1735 } 1736 } 1737 printf("chan2 num=%d\n", chans[1].num); 1738 for (c = 0; c < 2; c++) { 1739 for (j = 0; j < IWN_NSAMPLES; j++) { 1740 printf("chain %d, sample %d: temp=%d gain=%d " 1741 "power=%d pa_det=%d\n", c, j, 1742 chans[1].samples[c][j].temp, 1743 chans[1].samples[c][j].gain, 1744 chans[1].samples[c][j].power, 1745 chans[1].samples[c][j].pa_det); 1746 } 1747 } 1748 } 1749 #endif 1750 1751 static void 1752 iwn5000_read_eeprom(struct iwn_softc *sc) 1753 { 1754 struct iwn5000_eeprom_calib_hdr hdr; 1755 int32_t volt; 1756 uint32_t base, addr; 1757 uint16_t val; 1758 int i; 1759 1760 /* Read regulatory domain (4 ASCII characters). */ 1761 iwn_read_prom_data(sc, IWN5000_EEPROM_REG, &val, 2); 1762 base = le16toh(val); 1763 iwn_read_prom_data(sc, base + IWN5000_EEPROM_DOMAIN, 1764 sc->eeprom_domain, 4); 1765 1766 /* Read the list of authorized channels (20MHz ones only). */ 1767 for (i = 0; i < 7; i++) { 1768 if (sc->hw_type >= IWN_HW_REV_TYPE_6000) 1769 addr = base + iwn6000_regulatory_bands[i]; 1770 else 1771 addr = base + iwn5000_regulatory_bands[i]; 1772 iwn_read_eeprom_channels(sc, i, addr); 1773 } 1774 1775 /* Read enhanced TX power information for 6000 Series. */ 1776 if (sc->hw_type >= IWN_HW_REV_TYPE_6000) 1777 iwn_read_eeprom_enhinfo(sc); 1778 1779 iwn_read_prom_data(sc, IWN5000_EEPROM_CAL, &val, 2); 1780 base = le16toh(val); 1781 iwn_read_prom_data(sc, base, &hdr, sizeof hdr); 1782 DPRINTF(sc, IWN_DEBUG_CALIBRATE, 1783 "%s: calib version=%u pa type=%u voltage=%u\n", __func__, 1784 hdr.version, hdr.pa_type, le16toh(hdr.volt)); 1785 sc->calib_ver = hdr.version; 1786 1787 if (sc->hw_type == IWN_HW_REV_TYPE_5150) { 1788 /* Compute temperature offset. */ 1789 iwn_read_prom_data(sc, base + IWN5000_EEPROM_TEMP, &val, 2); 1790 sc->eeprom_temp = le16toh(val); 1791 iwn_read_prom_data(sc, base + IWN5000_EEPROM_VOLT, &val, 2); 1792 volt = le16toh(val); 1793 sc->temp_off = sc->eeprom_temp - (volt / -5); 1794 DPRINTF(sc, IWN_DEBUG_CALIBRATE, "temp=%d volt=%d offset=%dK\n", 1795 sc->eeprom_temp, volt, sc->temp_off); 1796 } else { 1797 /* Read crystal calibration. */ 1798 iwn_read_prom_data(sc, base + IWN5000_EEPROM_CRYSTAL, 1799 &sc->eeprom_crystal, sizeof (uint32_t)); 1800 DPRINTF(sc, IWN_DEBUG_CALIBRATE, "crystal calibration 0x%08x\n", 1801 le32toh(sc->eeprom_crystal)); 1802 } 1803 } 1804 1805 /* 1806 * Translate EEPROM flags to net80211. 1807 */ 1808 static uint32_t 1809 iwn_eeprom_channel_flags(struct iwn_eeprom_chan *channel) 1810 { 1811 uint32_t nflags; 1812 1813 nflags = 0; 1814 if ((channel->flags & IWN_EEPROM_CHAN_ACTIVE) == 0) 1815 nflags |= IEEE80211_CHAN_PASSIVE; 1816 if ((channel->flags & IWN_EEPROM_CHAN_IBSS) == 0) 1817 nflags |= IEEE80211_CHAN_NOADHOC; 1818 if (channel->flags & IWN_EEPROM_CHAN_RADAR) { 1819 nflags |= IEEE80211_CHAN_DFS; 1820 /* XXX apparently IBSS may still be marked */ 1821 nflags |= IEEE80211_CHAN_NOADHOC; 1822 } 1823 1824 return nflags; 1825 } 1826 1827 static void 1828 iwn_read_eeprom_band(struct iwn_softc *sc, int n) 1829 { 1830 struct ifnet *ifp = sc->sc_ifp; 1831 struct ieee80211com *ic = ifp->if_l2com; 1832 struct iwn_eeprom_chan *channels = sc->eeprom_channels[n]; 1833 const struct iwn_chan_band *band = &iwn_bands[n]; 1834 struct ieee80211_channel *c; 1835 uint8_t chan; 1836 int i, nflags; 1837 1838 for (i = 0; i < band->nchan; i++) { 1839 if (!(channels[i].flags & IWN_EEPROM_CHAN_VALID)) { 1840 DPRINTF(sc, IWN_DEBUG_RESET, 1841 "skip chan %d flags 0x%x maxpwr %d\n", 1842 band->chan[i], channels[i].flags, 1843 channels[i].maxpwr); 1844 continue; 1845 } 1846 chan = band->chan[i]; 1847 nflags = iwn_eeprom_channel_flags(&channels[i]); 1848 1849 c = &ic->ic_channels[ic->ic_nchans++]; 1850 c->ic_ieee = chan; 1851 c->ic_maxregpower = channels[i].maxpwr; 1852 c->ic_maxpower = 2*c->ic_maxregpower; 1853 1854 if (n == 0) { /* 2GHz band */ 1855 c->ic_freq = ieee80211_ieee2mhz(chan, IEEE80211_CHAN_G); 1856 /* G =>'s B is supported */ 1857 c->ic_flags = IEEE80211_CHAN_B | nflags; 1858 c = &ic->ic_channels[ic->ic_nchans++]; 1859 c[0] = c[-1]; 1860 c->ic_flags = IEEE80211_CHAN_G | nflags; 1861 } else { /* 5GHz band */ 1862 c->ic_freq = ieee80211_ieee2mhz(chan, IEEE80211_CHAN_A); 1863 c->ic_flags = IEEE80211_CHAN_A | nflags; 1864 } 1865 1866 /* Save maximum allowed TX power for this channel. */ 1867 sc->maxpwr[chan] = channels[i].maxpwr; 1868 1869 DPRINTF(sc, IWN_DEBUG_RESET, 1870 "add chan %d flags 0x%x maxpwr %d\n", chan, 1871 channels[i].flags, channels[i].maxpwr); 1872 1873 if (sc->sc_flags & IWN_FLAG_HAS_11N) { 1874 /* add HT20, HT40 added separately */ 1875 c = &ic->ic_channels[ic->ic_nchans++]; 1876 c[0] = c[-1]; 1877 c->ic_flags |= IEEE80211_CHAN_HT20; 1878 } 1879 } 1880 } 1881 1882 static void 1883 iwn_read_eeprom_ht40(struct iwn_softc *sc, int n) 1884 { 1885 struct ifnet *ifp = sc->sc_ifp; 1886 struct ieee80211com *ic = ifp->if_l2com; 1887 struct iwn_eeprom_chan *channels = sc->eeprom_channels[n]; 1888 const struct iwn_chan_band *band = &iwn_bands[n]; 1889 struct ieee80211_channel *c, *cent, *extc; 1890 uint8_t chan; 1891 int i, nflags; 1892 1893 if (!(sc->sc_flags & IWN_FLAG_HAS_11N)) 1894 return; 1895 1896 for (i = 0; i < band->nchan; i++) { 1897 if (!(channels[i].flags & IWN_EEPROM_CHAN_VALID)) { 1898 DPRINTF(sc, IWN_DEBUG_RESET, 1899 "skip chan %d flags 0x%x maxpwr %d\n", 1900 band->chan[i], channels[i].flags, 1901 channels[i].maxpwr); 1902 continue; 1903 } 1904 chan = band->chan[i]; 1905 nflags = iwn_eeprom_channel_flags(&channels[i]); 1906 1907 /* 1908 * Each entry defines an HT40 channel pair; find the 1909 * center channel, then the extension channel above. 1910 */ 1911 cent = ieee80211_find_channel_byieee(ic, chan, 1912 (n == 5 ? IEEE80211_CHAN_G : IEEE80211_CHAN_A)); 1913 if (cent == NULL) { /* XXX shouldn't happen */ 1914 device_printf(sc->sc_dev, 1915 "%s: no entry for channel %d\n", __func__, chan); 1916 continue; 1917 } 1918 extc = ieee80211_find_channel(ic, cent->ic_freq+20, 1919 (n == 5 ? IEEE80211_CHAN_G : IEEE80211_CHAN_A)); 1920 if (extc == NULL) { 1921 DPRINTF(sc, IWN_DEBUG_RESET, 1922 "%s: skip chan %d, extension channel not found\n", 1923 __func__, chan); 1924 continue; 1925 } 1926 1927 DPRINTF(sc, IWN_DEBUG_RESET, 1928 "add ht40 chan %d flags 0x%x maxpwr %d\n", 1929 chan, channels[i].flags, channels[i].maxpwr); 1930 1931 c = &ic->ic_channels[ic->ic_nchans++]; 1932 c[0] = cent[0]; 1933 c->ic_extieee = extc->ic_ieee; 1934 c->ic_flags &= ~IEEE80211_CHAN_HT; 1935 c->ic_flags |= IEEE80211_CHAN_HT40U | nflags; 1936 c = &ic->ic_channels[ic->ic_nchans++]; 1937 c[0] = extc[0]; 1938 c->ic_extieee = cent->ic_ieee; 1939 c->ic_flags &= ~IEEE80211_CHAN_HT; 1940 c->ic_flags |= IEEE80211_CHAN_HT40D | nflags; 1941 } 1942 } 1943 1944 static void 1945 iwn_read_eeprom_channels(struct iwn_softc *sc, int n, uint32_t addr) 1946 { 1947 struct ifnet *ifp = sc->sc_ifp; 1948 struct ieee80211com *ic = ifp->if_l2com; 1949 1950 iwn_read_prom_data(sc, addr, &sc->eeprom_channels[n], 1951 iwn_bands[n].nchan * sizeof (struct iwn_eeprom_chan)); 1952 1953 if (n < 5) 1954 iwn_read_eeprom_band(sc, n); 1955 else 1956 iwn_read_eeprom_ht40(sc, n); 1957 ieee80211_sort_channels(ic->ic_channels, ic->ic_nchans); 1958 } 1959 1960 static struct iwn_eeprom_chan * 1961 iwn_find_eeprom_channel(struct iwn_softc *sc, struct ieee80211_channel *c) 1962 { 1963 int band, chan, i, j; 1964 1965 if (IEEE80211_IS_CHAN_HT40(c)) { 1966 band = IEEE80211_IS_CHAN_5GHZ(c) ? 6 : 5; 1967 if (IEEE80211_IS_CHAN_HT40D(c)) 1968 chan = c->ic_extieee; 1969 else 1970 chan = c->ic_ieee; 1971 for (i = 0; i < iwn_bands[band].nchan; i++) { 1972 if (iwn_bands[band].chan[i] == chan) 1973 return &sc->eeprom_channels[band][i]; 1974 } 1975 } else { 1976 for (j = 0; j < 5; j++) { 1977 for (i = 0; i < iwn_bands[j].nchan; i++) { 1978 if (iwn_bands[j].chan[i] == c->ic_ieee) 1979 return &sc->eeprom_channels[j][i]; 1980 } 1981 } 1982 } 1983 return NULL; 1984 } 1985 1986 /* 1987 * Enforce flags read from EEPROM. 1988 */ 1989 static int 1990 iwn_setregdomain(struct ieee80211com *ic, struct ieee80211_regdomain *rd, 1991 int nchan, struct ieee80211_channel chans[]) 1992 { 1993 struct iwn_softc *sc = ic->ic_ifp->if_softc; 1994 int i; 1995 1996 for (i = 0; i < nchan; i++) { 1997 struct ieee80211_channel *c = &chans[i]; 1998 struct iwn_eeprom_chan *channel; 1999 2000 channel = iwn_find_eeprom_channel(sc, c); 2001 if (channel == NULL) { 2002 if_printf(ic->ic_ifp, 2003 "%s: invalid channel %u freq %u/0x%x\n", 2004 __func__, c->ic_ieee, c->ic_freq, c->ic_flags); 2005 return EINVAL; 2006 } 2007 c->ic_flags |= iwn_eeprom_channel_flags(channel); 2008 } 2009 2010 return 0; 2011 } 2012 2013 #define nitems(_a) (sizeof((_a)) / sizeof((_a)[0])) 2014 2015 static void 2016 iwn_read_eeprom_enhinfo(struct iwn_softc *sc) 2017 { 2018 struct iwn_eeprom_enhinfo enhinfo[35]; 2019 struct ifnet *ifp = sc->sc_ifp; 2020 struct ieee80211com *ic = ifp->if_l2com; 2021 struct ieee80211_channel *c; 2022 uint16_t val, base; 2023 int8_t maxpwr; 2024 uint8_t flags; 2025 int i, j; 2026 2027 iwn_read_prom_data(sc, IWN5000_EEPROM_REG, &val, 2); 2028 base = le16toh(val); 2029 iwn_read_prom_data(sc, base + IWN6000_EEPROM_ENHINFO, 2030 enhinfo, sizeof enhinfo); 2031 2032 for (i = 0; i < nitems(enhinfo); i++) { 2033 flags = enhinfo[i].flags; 2034 if (!(flags & IWN_ENHINFO_VALID)) 2035 continue; /* Skip invalid entries. */ 2036 2037 maxpwr = 0; 2038 if (sc->txchainmask & IWN_ANT_A) 2039 maxpwr = MAX(maxpwr, enhinfo[i].chain[0]); 2040 if (sc->txchainmask & IWN_ANT_B) 2041 maxpwr = MAX(maxpwr, enhinfo[i].chain[1]); 2042 if (sc->txchainmask & IWN_ANT_C) 2043 maxpwr = MAX(maxpwr, enhinfo[i].chain[2]); 2044 if (sc->ntxchains == 2) 2045 maxpwr = MAX(maxpwr, enhinfo[i].mimo2); 2046 else if (sc->ntxchains == 3) 2047 maxpwr = MAX(maxpwr, enhinfo[i].mimo3); 2048 2049 for (j = 0; j < ic->ic_nchans; j++) { 2050 c = &ic->ic_channels[j]; 2051 if ((flags & IWN_ENHINFO_5GHZ)) { 2052 if (!IEEE80211_IS_CHAN_A(c)) 2053 continue; 2054 } else if ((flags & IWN_ENHINFO_OFDM)) { 2055 if (!IEEE80211_IS_CHAN_G(c)) 2056 continue; 2057 } else if (!IEEE80211_IS_CHAN_B(c)) 2058 continue; 2059 if ((flags & IWN_ENHINFO_HT40)) { 2060 if (!IEEE80211_IS_CHAN_HT40(c)) 2061 continue; 2062 } else { 2063 if (IEEE80211_IS_CHAN_HT40(c)) 2064 continue; 2065 } 2066 if (enhinfo[i].chan != 0 && 2067 enhinfo[i].chan != c->ic_ieee) 2068 continue; 2069 2070 DPRINTF(sc, IWN_DEBUG_RESET, 2071 "channel %d(%x), maxpwr %d\n", c->ic_ieee, 2072 c->ic_flags, maxpwr / 2); 2073 c->ic_maxregpower = maxpwr / 2; 2074 c->ic_maxpower = maxpwr; 2075 } 2076 } 2077 } 2078 2079 static struct ieee80211_node * 2080 iwn_node_alloc(struct ieee80211vap *vap, const uint8_t mac[IEEE80211_ADDR_LEN]) 2081 { 2082 return malloc(sizeof (struct iwn_node), M_80211_NODE,M_NOWAIT | M_ZERO); 2083 } 2084 2085 static __inline int 2086 rate2plcp(int rate) 2087 { 2088 switch (rate & 0xff) { 2089 case 12: return 0xd; 2090 case 18: return 0xf; 2091 case 24: return 0x5; 2092 case 36: return 0x7; 2093 case 48: return 0x9; 2094 case 72: return 0xb; 2095 case 96: return 0x1; 2096 case 108: return 0x3; 2097 case 2: return 10; 2098 case 4: return 20; 2099 case 11: return 55; 2100 case 22: return 110; 2101 } 2102 return 0; 2103 } 2104 2105 static void 2106 iwn_newassoc(struct ieee80211_node *ni, int isnew) 2107 { 2108 #define RV(v) ((v) & IEEE80211_RATE_VAL) 2109 struct ieee80211com *ic = ni->ni_ic; 2110 struct iwn_softc *sc = ic->ic_ifp->if_softc; 2111 struct iwn_node *wn = (void *)ni; 2112 uint8_t txant1, txant2; 2113 int i, plcp, rate, ridx; 2114 2115 /* Use the first valid TX antenna. */ 2116 txant1 = IWN_LSB(sc->txchainmask); 2117 txant2 = IWN_LSB(sc->txchainmask & ~txant1); 2118 2119 if (IEEE80211_IS_CHAN_HT(ni->ni_chan)) { 2120 ridx = ni->ni_rates.rs_nrates - 1; 2121 for (i = ni->ni_htrates.rs_nrates - 1; i >= 0; i--) { 2122 plcp = RV(ni->ni_htrates.rs_rates[i]) | IWN_RFLAG_MCS; 2123 if (IEEE80211_IS_CHAN_HT40(ni->ni_chan)) { 2124 plcp |= IWN_RFLAG_HT40; 2125 if (ni->ni_htcap & IEEE80211_HTCAP_SHORTGI40) 2126 plcp |= IWN_RFLAG_SGI; 2127 } else if (ni->ni_htcap & IEEE80211_HTCAP_SHORTGI20) 2128 plcp |= IWN_RFLAG_SGI; 2129 if (i > 7) 2130 plcp |= IWN_RFLAG_ANT(txant1 | txant2); 2131 else 2132 plcp |= IWN_RFLAG_ANT(txant1); 2133 if (ridx >= 0) { 2134 rate = RV(ni->ni_rates.rs_rates[ridx]); 2135 wn->ridx[rate] = plcp; 2136 } 2137 wn->ridx[IEEE80211_RATE_MCS | i] = plcp; 2138 ridx--; 2139 } 2140 } else { 2141 for (i = 0; i < ni->ni_rates.rs_nrates; i++) { 2142 rate = RV(ni->ni_rates.rs_rates[i]); 2143 plcp = rate2plcp(rate); 2144 ridx = ic->ic_rt->rateCodeToIndex[rate]; 2145 if (ridx < IWN_RIDX_OFDM6 && 2146 IEEE80211_IS_CHAN_2GHZ(ni->ni_chan)) 2147 plcp |= IWN_RFLAG_CCK; 2148 plcp |= IWN_RFLAG_ANT(txant1); 2149 wn->ridx[rate] = htole32(plcp); 2150 } 2151 } 2152 #undef RV 2153 } 2154 2155 static int 2156 iwn_media_change(struct ifnet *ifp) 2157 { 2158 int error; 2159 2160 error = ieee80211_media_change(ifp); 2161 /* NB: only the fixed rate can change and that doesn't need a reset */ 2162 return (error == ENETRESET ? 0 : error); 2163 } 2164 2165 static int 2166 iwn_newstate(struct ieee80211vap *vap, enum ieee80211_state nstate, int arg) 2167 { 2168 struct iwn_vap *ivp = IWN_VAP(vap); 2169 struct ieee80211com *ic = vap->iv_ic; 2170 struct iwn_softc *sc = ic->ic_ifp->if_softc; 2171 int error = 0; 2172 2173 DPRINTF(sc, IWN_DEBUG_STATE, "%s: %s -> %s\n", __func__, 2174 ieee80211_state_name[vap->iv_state], ieee80211_state_name[nstate]); 2175 2176 IEEE80211_UNLOCK(ic); 2177 IWN_LOCK(sc); 2178 callout_stop(&sc->calib_to); 2179 2180 switch (nstate) { 2181 case IEEE80211_S_ASSOC: 2182 if (vap->iv_state != IEEE80211_S_RUN) 2183 break; 2184 /* FALLTHROUGH */ 2185 case IEEE80211_S_AUTH: 2186 if (vap->iv_state == IEEE80211_S_AUTH) 2187 break; 2188 2189 /* 2190 * !AUTH -> AUTH transition requires state reset to handle 2191 * reassociations correctly. 2192 */ 2193 sc->rxon.associd = 0; 2194 sc->rxon.filter &= ~htole32(IWN_FILTER_BSS); 2195 sc->calib.state = IWN_CALIB_STATE_INIT; 2196 2197 if ((error = iwn_auth(sc, vap)) != 0) { 2198 device_printf(sc->sc_dev, 2199 "%s: could not move to auth state\n", __func__); 2200 } 2201 break; 2202 2203 case IEEE80211_S_RUN: 2204 /* 2205 * RUN -> RUN transition; Just restart the timers. 2206 */ 2207 if (vap->iv_state == IEEE80211_S_RUN) { 2208 sc->calib_cnt = 0; 2209 break; 2210 } 2211 2212 /* 2213 * !RUN -> RUN requires setting the association id 2214 * which is done with a firmware cmd. We also defer 2215 * starting the timers until that work is done. 2216 */ 2217 if ((error = iwn_run(sc, vap)) != 0) { 2218 device_printf(sc->sc_dev, 2219 "%s: could not move to run state\n", __func__); 2220 } 2221 break; 2222 2223 case IEEE80211_S_INIT: 2224 sc->calib.state = IWN_CALIB_STATE_INIT; 2225 break; 2226 2227 default: 2228 break; 2229 } 2230 IWN_UNLOCK(sc); 2231 IEEE80211_LOCK(ic); 2232 if (error != 0) 2233 return error; 2234 return ivp->iv_newstate(vap, nstate, arg); 2235 } 2236 2237 static void 2238 iwn_calib_timeout(void *arg) 2239 { 2240 struct iwn_softc *sc = arg; 2241 2242 IWN_LOCK_ASSERT(sc); 2243 2244 /* Force automatic TX power calibration every 60 secs. */ 2245 if (++sc->calib_cnt >= 120) { 2246 uint32_t flags = 0; 2247 2248 DPRINTF(sc, IWN_DEBUG_CALIBRATE, "%s\n", 2249 "sending request for statistics"); 2250 (void)iwn_cmd(sc, IWN_CMD_GET_STATISTICS, &flags, 2251 sizeof flags, 1); 2252 sc->calib_cnt = 0; 2253 } 2254 callout_reset(&sc->calib_to, msecs_to_ticks(500), iwn_calib_timeout, 2255 sc); 2256 } 2257 2258 /* 2259 * Process an RX_PHY firmware notification. This is usually immediately 2260 * followed by an MPDU_RX_DONE notification. 2261 */ 2262 static void 2263 iwn_rx_phy(struct iwn_softc *sc, struct iwn_rx_desc *desc, 2264 struct iwn_rx_data *data) 2265 { 2266 struct iwn_rx_stat *stat = (struct iwn_rx_stat *)(desc + 1); 2267 2268 DPRINTF(sc, IWN_DEBUG_CALIBRATE, "%s: received PHY stats\n", __func__); 2269 bus_dmamap_sync(sc->rxq.data_dmat, data->map, BUS_DMASYNC_POSTREAD); 2270 2271 /* Save RX statistics, they will be used on MPDU_RX_DONE. */ 2272 memcpy(&sc->last_rx_stat, stat, sizeof (*stat)); 2273 sc->last_rx_valid = 1; 2274 } 2275 2276 /* 2277 * Process an RX_DONE (4965AGN only) or MPDU_RX_DONE firmware notification. 2278 * Each MPDU_RX_DONE notification must be preceded by an RX_PHY one. 2279 */ 2280 static void 2281 iwn_rx_done(struct iwn_softc *sc, struct iwn_rx_desc *desc, 2282 struct iwn_rx_data *data) 2283 { 2284 struct iwn_ops *ops = &sc->ops; 2285 struct ifnet *ifp = sc->sc_ifp; 2286 struct ieee80211com *ic = ifp->if_l2com; 2287 struct iwn_rx_ring *ring = &sc->rxq; 2288 struct ieee80211_frame *wh; 2289 struct ieee80211_node *ni; 2290 struct mbuf *m, *m1; 2291 struct iwn_rx_stat *stat; 2292 caddr_t head; 2293 bus_addr_t paddr; 2294 uint32_t flags; 2295 int error, len, rssi, nf; 2296 2297 if (desc->type == IWN_MPDU_RX_DONE) { 2298 /* Check for prior RX_PHY notification. */ 2299 if (!sc->last_rx_valid) { 2300 DPRINTF(sc, IWN_DEBUG_ANY, 2301 "%s: missing RX_PHY\n", __func__); 2302 return; 2303 } 2304 stat = &sc->last_rx_stat; 2305 } else 2306 stat = (struct iwn_rx_stat *)(desc + 1); 2307 2308 bus_dmamap_sync(ring->data_dmat, data->map, BUS_DMASYNC_POSTREAD); 2309 2310 if (stat->cfg_phy_len > IWN_STAT_MAXLEN) { 2311 device_printf(sc->sc_dev, 2312 "%s: invalid RX statistic header, len %d\n", __func__, 2313 stat->cfg_phy_len); 2314 return; 2315 } 2316 if (desc->type == IWN_MPDU_RX_DONE) { 2317 struct iwn_rx_mpdu *mpdu = (struct iwn_rx_mpdu *)(desc + 1); 2318 head = (caddr_t)(mpdu + 1); 2319 len = le16toh(mpdu->len); 2320 } else { 2321 head = (caddr_t)(stat + 1) + stat->cfg_phy_len; 2322 len = le16toh(stat->len); 2323 } 2324 2325 flags = le32toh(*(uint32_t *)(head + len)); 2326 2327 /* Discard frames with a bad FCS early. */ 2328 if ((flags & IWN_RX_NOERROR) != IWN_RX_NOERROR) { 2329 DPRINTF(sc, IWN_DEBUG_RECV, "%s: RX flags error %x\n", 2330 __func__, flags); 2331 ifp->if_ierrors++; 2332 return; 2333 } 2334 /* Discard frames that are too short. */ 2335 if (len < sizeof (*wh)) { 2336 DPRINTF(sc, IWN_DEBUG_RECV, "%s: frame too short: %d\n", 2337 __func__, len); 2338 ifp->if_ierrors++; 2339 return; 2340 } 2341 2342 m1 = m_getjcl(M_DONTWAIT, MT_DATA, M_PKTHDR, IWN_RBUF_SIZE); 2343 if (m1 == NULL) { 2344 DPRINTF(sc, IWN_DEBUG_ANY, "%s: no mbuf to restock ring\n", 2345 __func__); 2346 ifp->if_ierrors++; 2347 return; 2348 } 2349 bus_dmamap_unload(ring->data_dmat, data->map); 2350 2351 error = bus_dmamap_load(ring->data_dmat, data->map, mtod(m1, void *), 2352 IWN_RBUF_SIZE, iwn_dma_map_addr, &paddr, BUS_DMA_NOWAIT); 2353 if (error != 0 && error != EFBIG) { 2354 device_printf(sc->sc_dev, 2355 "%s: bus_dmamap_load failed, error %d\n", __func__, error); 2356 m_freem(m1); 2357 2358 /* Try to reload the old mbuf. */ 2359 error = bus_dmamap_load(ring->data_dmat, data->map, 2360 mtod(data->m, void *), IWN_RBUF_SIZE, iwn_dma_map_addr, 2361 &paddr, BUS_DMA_NOWAIT); 2362 if (error != 0 && error != EFBIG) { 2363 panic("%s: could not load old RX mbuf", __func__); 2364 } 2365 /* Physical address may have changed. */ 2366 ring->desc[ring->cur] = htole32(paddr >> 8); 2367 bus_dmamap_sync(ring->data_dmat, ring->desc_dma.map, 2368 BUS_DMASYNC_PREWRITE); 2369 ifp->if_ierrors++; 2370 return; 2371 } 2372 2373 m = data->m; 2374 data->m = m1; 2375 /* Update RX descriptor. */ 2376 ring->desc[ring->cur] = htole32(paddr >> 8); 2377 bus_dmamap_sync(ring->desc_dma.tag, ring->desc_dma.map, 2378 BUS_DMASYNC_PREWRITE); 2379 2380 /* Finalize mbuf. */ 2381 m->m_pkthdr.rcvif = ifp; 2382 m->m_data = head; 2383 m->m_pkthdr.len = m->m_len = len; 2384 2385 /* Grab a reference to the source node. */ 2386 wh = mtod(m, struct ieee80211_frame *); 2387 ni = ieee80211_find_rxnode(ic, (struct ieee80211_frame_min *)wh); 2388 nf = (ni != NULL && ni->ni_vap->iv_state == IEEE80211_S_RUN && 2389 (ic->ic_flags & IEEE80211_F_SCAN) == 0) ? sc->noise : -95; 2390 2391 rssi = ops->get_rssi(sc, stat); 2392 2393 if (ieee80211_radiotap_active(ic)) { 2394 struct iwn_rx_radiotap_header *tap = &sc->sc_rxtap; 2395 2396 tap->wr_flags = 0; 2397 if (stat->flags & htole16(IWN_STAT_FLAG_SHPREAMBLE)) 2398 tap->wr_flags |= IEEE80211_RADIOTAP_F_SHORTPRE; 2399 tap->wr_dbm_antsignal = (int8_t)rssi; 2400 tap->wr_dbm_antnoise = (int8_t)nf; 2401 tap->wr_tsft = stat->tstamp; 2402 switch (stat->rate) { 2403 /* CCK rates. */ 2404 case 10: tap->wr_rate = 2; break; 2405 case 20: tap->wr_rate = 4; break; 2406 case 55: tap->wr_rate = 11; break; 2407 case 110: tap->wr_rate = 22; break; 2408 /* OFDM rates. */ 2409 case 0xd: tap->wr_rate = 12; break; 2410 case 0xf: tap->wr_rate = 18; break; 2411 case 0x5: tap->wr_rate = 24; break; 2412 case 0x7: tap->wr_rate = 36; break; 2413 case 0x9: tap->wr_rate = 48; break; 2414 case 0xb: tap->wr_rate = 72; break; 2415 case 0x1: tap->wr_rate = 96; break; 2416 case 0x3: tap->wr_rate = 108; break; 2417 /* Unknown rate: should not happen. */ 2418 default: tap->wr_rate = 0; 2419 } 2420 } 2421 2422 IWN_UNLOCK(sc); 2423 2424 /* Send the frame to the 802.11 layer. */ 2425 if (ni != NULL) { 2426 if (ni->ni_flags & IEEE80211_NODE_HT) 2427 m->m_flags |= M_AMPDU; 2428 (void)ieee80211_input(ni, m, rssi - nf, nf); 2429 /* Node is no longer needed. */ 2430 ieee80211_free_node(ni); 2431 } else 2432 (void)ieee80211_input_all(ic, m, rssi - nf, nf); 2433 2434 IWN_LOCK(sc); 2435 } 2436 2437 /* Process an incoming Compressed BlockAck. */ 2438 static void 2439 iwn_rx_compressed_ba(struct iwn_softc *sc, struct iwn_rx_desc *desc, 2440 struct iwn_rx_data *data) 2441 { 2442 struct ifnet *ifp = sc->sc_ifp; 2443 struct iwn_node *wn; 2444 struct ieee80211_node *ni; 2445 struct iwn_compressed_ba *ba = (struct iwn_compressed_ba *)(desc + 1); 2446 struct iwn_tx_ring *txq; 2447 struct ieee80211_tx_ampdu *tap; 2448 uint64_t bitmap; 2449 uint8_t tid; 2450 int ackfailcnt = 0, i, shift; 2451 2452 bus_dmamap_sync(sc->rxq.data_dmat, data->map, BUS_DMASYNC_POSTREAD); 2453 2454 txq = &sc->txq[le16toh(ba->qid)]; 2455 tap = sc->qid2tap[le16toh(ba->qid)]; 2456 tid = WME_AC_TO_TID(tap->txa_ac); 2457 ni = tap->txa_ni; 2458 wn = (void *)ni; 2459 2460 if (wn->agg[tid].bitmap == 0) 2461 return; 2462 2463 shift = wn->agg[tid].startidx - ((le16toh(ba->seq) >> 4) & 0xff); 2464 if (shift < 0) 2465 shift += 0x100; 2466 2467 if (wn->agg[tid].nframes > (64 - shift)) 2468 return; 2469 2470 bitmap = (le64toh(ba->bitmap) >> shift) & wn->agg[tid].bitmap; 2471 for (i = 0; bitmap; i++) { 2472 if ((bitmap & 1) == 0) { 2473 ifp->if_oerrors++; 2474 ieee80211_ratectl_tx_complete(ni->ni_vap, ni, 2475 IEEE80211_RATECTL_TX_FAILURE, &ackfailcnt, NULL); 2476 } else { 2477 ifp->if_opackets++; 2478 ieee80211_ratectl_tx_complete(ni->ni_vap, ni, 2479 IEEE80211_RATECTL_TX_SUCCESS, &ackfailcnt, NULL); 2480 } 2481 bitmap >>= 1; 2482 } 2483 } 2484 2485 /* 2486 * Process a CALIBRATION_RESULT notification sent by the initialization 2487 * firmware on response to a CMD_CALIB_CONFIG command (5000 only). 2488 */ 2489 static void 2490 iwn5000_rx_calib_results(struct iwn_softc *sc, struct iwn_rx_desc *desc, 2491 struct iwn_rx_data *data) 2492 { 2493 struct iwn_phy_calib *calib = (struct iwn_phy_calib *)(desc + 1); 2494 int len, idx = -1; 2495 2496 /* Runtime firmware should not send such a notification. */ 2497 if (sc->sc_flags & IWN_FLAG_CALIB_DONE) 2498 return; 2499 2500 len = (le32toh(desc->len) & 0x3fff) - 4; 2501 bus_dmamap_sync(sc->rxq.data_dmat, data->map, BUS_DMASYNC_POSTREAD); 2502 2503 switch (calib->code) { 2504 case IWN5000_PHY_CALIB_DC: 2505 if ((sc->sc_flags & IWN_FLAG_INTERNAL_PA) == 0 && 2506 (sc->hw_type == IWN_HW_REV_TYPE_5150 || 2507 sc->hw_type >= IWN_HW_REV_TYPE_6000)) 2508 idx = 0; 2509 break; 2510 case IWN5000_PHY_CALIB_LO: 2511 idx = 1; 2512 break; 2513 case IWN5000_PHY_CALIB_TX_IQ: 2514 idx = 2; 2515 break; 2516 case IWN5000_PHY_CALIB_TX_IQ_PERIODIC: 2517 if (sc->hw_type < IWN_HW_REV_TYPE_6000 && 2518 sc->hw_type != IWN_HW_REV_TYPE_5150) 2519 idx = 3; 2520 break; 2521 case IWN5000_PHY_CALIB_BASE_BAND: 2522 idx = 4; 2523 break; 2524 } 2525 if (idx == -1) /* Ignore other results. */ 2526 return; 2527 2528 /* Save calibration result. */ 2529 if (sc->calibcmd[idx].buf != NULL) 2530 free(sc->calibcmd[idx].buf, M_DEVBUF); 2531 sc->calibcmd[idx].buf = malloc(len, M_DEVBUF, M_NOWAIT); 2532 if (sc->calibcmd[idx].buf == NULL) { 2533 DPRINTF(sc, IWN_DEBUG_CALIBRATE, 2534 "not enough memory for calibration result %d\n", 2535 calib->code); 2536 return; 2537 } 2538 DPRINTF(sc, IWN_DEBUG_CALIBRATE, 2539 "saving calibration result code=%d len=%d\n", calib->code, len); 2540 sc->calibcmd[idx].len = len; 2541 memcpy(sc->calibcmd[idx].buf, calib, len); 2542 } 2543 2544 /* 2545 * Process an RX_STATISTICS or BEACON_STATISTICS firmware notification. 2546 * The latter is sent by the firmware after each received beacon. 2547 */ 2548 static void 2549 iwn_rx_statistics(struct iwn_softc *sc, struct iwn_rx_desc *desc, 2550 struct iwn_rx_data *data) 2551 { 2552 struct iwn_ops *ops = &sc->ops; 2553 struct ifnet *ifp = sc->sc_ifp; 2554 struct ieee80211com *ic = ifp->if_l2com; 2555 struct ieee80211vap *vap = TAILQ_FIRST(&ic->ic_vaps); 2556 struct iwn_calib_state *calib = &sc->calib; 2557 struct iwn_stats *stats = (struct iwn_stats *)(desc + 1); 2558 int temp; 2559 2560 /* Ignore statistics received during a scan. */ 2561 if (vap->iv_state != IEEE80211_S_RUN || 2562 (ic->ic_flags & IEEE80211_F_SCAN)) 2563 return; 2564 2565 bus_dmamap_sync(sc->rxq.data_dmat, data->map, BUS_DMASYNC_POSTREAD); 2566 2567 DPRINTF(sc, IWN_DEBUG_CALIBRATE, "%s: received statistics, cmd %d\n", 2568 __func__, desc->type); 2569 sc->calib_cnt = 0; /* Reset TX power calibration timeout. */ 2570 2571 /* Test if temperature has changed. */ 2572 if (stats->general.temp != sc->rawtemp) { 2573 /* Convert "raw" temperature to degC. */ 2574 sc->rawtemp = stats->general.temp; 2575 temp = ops->get_temperature(sc); 2576 DPRINTF(sc, IWN_DEBUG_CALIBRATE, "%s: temperature %d\n", 2577 __func__, temp); 2578 2579 /* Update TX power if need be (4965AGN only). */ 2580 if (sc->hw_type == IWN_HW_REV_TYPE_4965) 2581 iwn4965_power_calibration(sc, temp); 2582 } 2583 2584 if (desc->type != IWN_BEACON_STATISTICS) 2585 return; /* Reply to a statistics request. */ 2586 2587 sc->noise = iwn_get_noise(&stats->rx.general); 2588 DPRINTF(sc, IWN_DEBUG_CALIBRATE, "%s: noise %d\n", __func__, sc->noise); 2589 2590 /* Test that RSSI and noise are present in stats report. */ 2591 if (le32toh(stats->rx.general.flags) != 1) { 2592 DPRINTF(sc, IWN_DEBUG_ANY, "%s\n", 2593 "received statistics without RSSI"); 2594 return; 2595 } 2596 2597 if (calib->state == IWN_CALIB_STATE_ASSOC) 2598 iwn_collect_noise(sc, &stats->rx.general); 2599 else if (calib->state == IWN_CALIB_STATE_RUN) 2600 iwn_tune_sensitivity(sc, &stats->rx); 2601 } 2602 2603 /* 2604 * Process a TX_DONE firmware notification. Unfortunately, the 4965AGN 2605 * and 5000 adapters have different incompatible TX status formats. 2606 */ 2607 static void 2608 iwn4965_tx_done(struct iwn_softc *sc, struct iwn_rx_desc *desc, 2609 struct iwn_rx_data *data) 2610 { 2611 struct iwn4965_tx_stat *stat = (struct iwn4965_tx_stat *)(desc + 1); 2612 struct iwn_tx_ring *ring; 2613 int qid; 2614 2615 qid = desc->qid & 0xf; 2616 ring = &sc->txq[qid]; 2617 2618 DPRINTF(sc, IWN_DEBUG_XMIT, "%s: " 2619 "qid %d idx %d retries %d nkill %d rate %x duration %d status %x\n", 2620 __func__, desc->qid, desc->idx, stat->ackfailcnt, 2621 stat->btkillcnt, stat->rate, le16toh(stat->duration), 2622 le32toh(stat->status)); 2623 2624 bus_dmamap_sync(ring->data_dmat, data->map, BUS_DMASYNC_POSTREAD); 2625 if (qid >= sc->firstaggqueue) { 2626 iwn_ampdu_tx_done(sc, qid, desc->idx, stat->nframes, 2627 &stat->status); 2628 } else { 2629 iwn_tx_done(sc, desc, stat->ackfailcnt, 2630 le32toh(stat->status) & 0xff); 2631 } 2632 } 2633 2634 static void 2635 iwn5000_tx_done(struct iwn_softc *sc, struct iwn_rx_desc *desc, 2636 struct iwn_rx_data *data) 2637 { 2638 struct iwn5000_tx_stat *stat = (struct iwn5000_tx_stat *)(desc + 1); 2639 struct iwn_tx_ring *ring; 2640 int qid; 2641 2642 qid = desc->qid & 0xf; 2643 ring = &sc->txq[qid]; 2644 2645 DPRINTF(sc, IWN_DEBUG_XMIT, "%s: " 2646 "qid %d idx %d retries %d nkill %d rate %x duration %d status %x\n", 2647 __func__, desc->qid, desc->idx, stat->ackfailcnt, 2648 stat->btkillcnt, stat->rate, le16toh(stat->duration), 2649 le32toh(stat->status)); 2650 2651 #ifdef notyet 2652 /* Reset TX scheduler slot. */ 2653 iwn5000_reset_sched(sc, desc->qid & 0xf, desc->idx); 2654 #endif 2655 2656 bus_dmamap_sync(ring->data_dmat, data->map, BUS_DMASYNC_POSTREAD); 2657 if (qid >= sc->firstaggqueue) { 2658 iwn_ampdu_tx_done(sc, qid, desc->idx, stat->nframes, 2659 &stat->status); 2660 } else { 2661 iwn_tx_done(sc, desc, stat->ackfailcnt, 2662 le16toh(stat->status) & 0xff); 2663 } 2664 } 2665 2666 /* 2667 * Adapter-independent backend for TX_DONE firmware notifications. 2668 */ 2669 static void 2670 iwn_tx_done(struct iwn_softc *sc, struct iwn_rx_desc *desc, int ackfailcnt, 2671 uint8_t status) 2672 { 2673 struct ifnet *ifp = sc->sc_ifp; 2674 struct iwn_tx_ring *ring = &sc->txq[desc->qid & 0xf]; 2675 struct iwn_tx_data *data = &ring->data[desc->idx]; 2676 struct mbuf *m; 2677 struct ieee80211_node *ni; 2678 struct ieee80211vap *vap; 2679 2680 KASSERT(data->ni != NULL, ("no node")); 2681 2682 /* Unmap and free mbuf. */ 2683 bus_dmamap_sync(ring->data_dmat, data->map, BUS_DMASYNC_POSTWRITE); 2684 bus_dmamap_unload(ring->data_dmat, data->map); 2685 m = data->m, data->m = NULL; 2686 ni = data->ni, data->ni = NULL; 2687 vap = ni->ni_vap; 2688 2689 if (m->m_flags & M_TXCB) { 2690 /* 2691 * Channels marked for "radar" require traffic to be received 2692 * to unlock before we can transmit. Until traffic is seen 2693 * any attempt to transmit is returned immediately with status 2694 * set to IWN_TX_FAIL_TX_LOCKED. Unfortunately this can easily 2695 * happen on first authenticate after scanning. To workaround 2696 * this we ignore a failure of this sort in AUTH state so the 2697 * 802.11 layer will fall back to using a timeout to wait for 2698 * the AUTH reply. This allows the firmware time to see 2699 * traffic so a subsequent retry of AUTH succeeds. It's 2700 * unclear why the firmware does not maintain state for 2701 * channels recently visited as this would allow immediate 2702 * use of the channel after a scan (where we see traffic). 2703 */ 2704 if (status == IWN_TX_FAIL_TX_LOCKED && 2705 ni->ni_vap->iv_state == IEEE80211_S_AUTH) 2706 ieee80211_process_callback(ni, m, 0); 2707 else 2708 ieee80211_process_callback(ni, m, 2709 (status & IWN_TX_FAIL) != 0); 2710 } 2711 2712 /* 2713 * Update rate control statistics for the node. 2714 */ 2715 if (status & IWN_TX_FAIL) { 2716 ifp->if_oerrors++; 2717 ieee80211_ratectl_tx_complete(vap, ni, 2718 IEEE80211_RATECTL_TX_FAILURE, &ackfailcnt, NULL); 2719 } else { 2720 ifp->if_opackets++; 2721 ieee80211_ratectl_tx_complete(vap, ni, 2722 IEEE80211_RATECTL_TX_SUCCESS, &ackfailcnt, NULL); 2723 } 2724 m_freem(m); 2725 ieee80211_free_node(ni); 2726 2727 sc->sc_tx_timer = 0; 2728 if (--ring->queued < IWN_TX_RING_LOMARK) { 2729 sc->qfullmsk &= ~(1 << ring->qid); 2730 if (sc->qfullmsk == 0 && 2731 (ifp->if_drv_flags & IFF_DRV_OACTIVE)) { 2732 ifp->if_drv_flags &= ~IFF_DRV_OACTIVE; 2733 iwn_start_locked(ifp); 2734 } 2735 } 2736 } 2737 2738 /* 2739 * Process a "command done" firmware notification. This is where we wakeup 2740 * processes waiting for a synchronous command completion. 2741 */ 2742 static void 2743 iwn_cmd_done(struct iwn_softc *sc, struct iwn_rx_desc *desc) 2744 { 2745 struct iwn_tx_ring *ring = &sc->txq[4]; 2746 struct iwn_tx_data *data; 2747 2748 if ((desc->qid & 0xf) != 4) 2749 return; /* Not a command ack. */ 2750 2751 data = &ring->data[desc->idx]; 2752 2753 /* If the command was mapped in an mbuf, free it. */ 2754 if (data->m != NULL) { 2755 bus_dmamap_sync(ring->data_dmat, data->map, 2756 BUS_DMASYNC_POSTWRITE); 2757 bus_dmamap_unload(ring->data_dmat, data->map); 2758 m_freem(data->m); 2759 data->m = NULL; 2760 } 2761 wakeup(&ring->desc[desc->idx]); 2762 } 2763 2764 static void 2765 iwn_ampdu_tx_done(struct iwn_softc *sc, int qid, int idx, int nframes, 2766 void *stat) 2767 { 2768 struct ifnet *ifp = sc->sc_ifp; 2769 struct iwn_tx_ring *ring = &sc->txq[qid]; 2770 struct iwn_tx_data *data; 2771 struct mbuf *m; 2772 struct iwn_node *wn; 2773 struct ieee80211_node *ni; 2774 struct ieee80211vap *vap; 2775 struct ieee80211_tx_ampdu *tap; 2776 uint64_t bitmap; 2777 uint32_t *status = stat; 2778 uint16_t *aggstatus = stat; 2779 uint8_t tid; 2780 int bit, i, lastidx, seqno, shift, start; 2781 2782 #ifdef NOT_YET 2783 if (nframes == 1) { 2784 if ((*status & 0xff) != 1 && (*status & 0xff) != 2) 2785 printf("ieee80211_send_bar()\n"); 2786 } 2787 #endif 2788 2789 bitmap = 0; 2790 start = idx; 2791 for (i = 0; i < nframes; i++) { 2792 if (le16toh(aggstatus[i * 2]) & 0xc) 2793 continue; 2794 2795 idx = le16toh(aggstatus[2*i + 1]) & 0xff; 2796 bit = idx - start; 2797 shift = 0; 2798 if (bit >= 64) { 2799 shift = 0x100 - idx + start; 2800 bit = 0; 2801 start = idx; 2802 } else if (bit <= -64) 2803 bit = 0x100 - start + idx; 2804 else if (bit < 0) { 2805 shift = start - idx; 2806 start = idx; 2807 bit = 0; 2808 } 2809 bitmap = bitmap << shift; 2810 bitmap |= 1ULL << bit; 2811 } 2812 tap = sc->qid2tap[qid]; 2813 tid = WME_AC_TO_TID(tap->txa_ac); 2814 wn = (void *)tap->txa_ni; 2815 wn->agg[tid].bitmap = bitmap; 2816 wn->agg[tid].startidx = start; 2817 wn->agg[tid].nframes = nframes; 2818 2819 seqno = le32toh(*(status + nframes)) & 0xfff; 2820 for (lastidx = (seqno & 0xff); ring->read != lastidx;) { 2821 data = &ring->data[ring->read]; 2822 2823 KASSERT(data->ni != NULL, ("no node")); 2824 2825 /* Unmap and free mbuf. */ 2826 bus_dmamap_sync(ring->data_dmat, data->map, 2827 BUS_DMASYNC_POSTWRITE); 2828 bus_dmamap_unload(ring->data_dmat, data->map); 2829 m = data->m, data->m = NULL; 2830 ni = data->ni, data->ni = NULL; 2831 vap = ni->ni_vap; 2832 2833 if (m->m_flags & M_TXCB) 2834 ieee80211_process_callback(ni, m, 1); 2835 2836 m_freem(m); 2837 ieee80211_free_node(ni); 2838 2839 ring->queued--; 2840 ring->read = (ring->read + 1) % IWN_TX_RING_COUNT; 2841 } 2842 2843 sc->sc_tx_timer = 0; 2844 if (ring->queued < IWN_TX_RING_LOMARK) { 2845 sc->qfullmsk &= ~(1 << ring->qid); 2846 if (sc->qfullmsk == 0 && 2847 (ifp->if_drv_flags & IFF_DRV_OACTIVE)) { 2848 ifp->if_drv_flags &= ~IFF_DRV_OACTIVE; 2849 iwn_start_locked(ifp); 2850 } 2851 } 2852 } 2853 2854 /* 2855 * Process an INT_FH_RX or INT_SW_RX interrupt. 2856 */ 2857 static void 2858 iwn_notif_intr(struct iwn_softc *sc) 2859 { 2860 struct iwn_ops *ops = &sc->ops; 2861 struct ifnet *ifp = sc->sc_ifp; 2862 struct ieee80211com *ic = ifp->if_l2com; 2863 struct ieee80211vap *vap = TAILQ_FIRST(&ic->ic_vaps); 2864 uint16_t hw; 2865 2866 bus_dmamap_sync(sc->rxq.stat_dma.tag, sc->rxq.stat_dma.map, 2867 BUS_DMASYNC_POSTREAD); 2868 2869 hw = le16toh(sc->rxq.stat->closed_count) & 0xfff; 2870 while (sc->rxq.cur != hw) { 2871 struct iwn_rx_data *data = &sc->rxq.data[sc->rxq.cur]; 2872 struct iwn_rx_desc *desc; 2873 2874 bus_dmamap_sync(sc->rxq.data_dmat, data->map, 2875 BUS_DMASYNC_POSTREAD); 2876 desc = mtod(data->m, struct iwn_rx_desc *); 2877 2878 DPRINTF(sc, IWN_DEBUG_RECV, 2879 "%s: qid %x idx %d flags %x type %d(%s) len %d\n", 2880 __func__, desc->qid & 0xf, desc->idx, desc->flags, 2881 desc->type, iwn_intr_str(desc->type), 2882 le16toh(desc->len)); 2883 2884 if (!(desc->qid & 0x80)) /* Reply to a command. */ 2885 iwn_cmd_done(sc, desc); 2886 2887 switch (desc->type) { 2888 case IWN_RX_PHY: 2889 iwn_rx_phy(sc, desc, data); 2890 break; 2891 2892 case IWN_RX_DONE: /* 4965AGN only. */ 2893 case IWN_MPDU_RX_DONE: 2894 /* An 802.11 frame has been received. */ 2895 iwn_rx_done(sc, desc, data); 2896 break; 2897 2898 case IWN_RX_COMPRESSED_BA: 2899 /* A Compressed BlockAck has been received. */ 2900 iwn_rx_compressed_ba(sc, desc, data); 2901 break; 2902 2903 case IWN_TX_DONE: 2904 /* An 802.11 frame has been transmitted. */ 2905 ops->tx_done(sc, desc, data); 2906 break; 2907 2908 case IWN_RX_STATISTICS: 2909 case IWN_BEACON_STATISTICS: 2910 iwn_rx_statistics(sc, desc, data); 2911 break; 2912 2913 case IWN_BEACON_MISSED: 2914 { 2915 struct iwn_beacon_missed *miss = 2916 (struct iwn_beacon_missed *)(desc + 1); 2917 int misses; 2918 2919 bus_dmamap_sync(sc->rxq.data_dmat, data->map, 2920 BUS_DMASYNC_POSTREAD); 2921 misses = le32toh(miss->consecutive); 2922 2923 DPRINTF(sc, IWN_DEBUG_STATE, 2924 "%s: beacons missed %d/%d\n", __func__, 2925 misses, le32toh(miss->total)); 2926 /* 2927 * If more than 5 consecutive beacons are missed, 2928 * reinitialize the sensitivity state machine. 2929 */ 2930 if (vap->iv_state == IEEE80211_S_RUN && 2931 (ic->ic_flags & IEEE80211_F_SCAN) != 0) { 2932 if (misses > 5) 2933 (void)iwn_init_sensitivity(sc); 2934 if (misses >= vap->iv_bmissthreshold) { 2935 IWN_UNLOCK(sc); 2936 ieee80211_beacon_miss(ic); 2937 IWN_LOCK(sc); 2938 } 2939 } 2940 break; 2941 } 2942 case IWN_UC_READY: 2943 { 2944 struct iwn_ucode_info *uc = 2945 (struct iwn_ucode_info *)(desc + 1); 2946 2947 /* The microcontroller is ready. */ 2948 bus_dmamap_sync(sc->rxq.data_dmat, data->map, 2949 BUS_DMASYNC_POSTREAD); 2950 DPRINTF(sc, IWN_DEBUG_RESET, 2951 "microcode alive notification version=%d.%d " 2952 "subtype=%x alive=%x\n", uc->major, uc->minor, 2953 uc->subtype, le32toh(uc->valid)); 2954 2955 if (le32toh(uc->valid) != 1) { 2956 device_printf(sc->sc_dev, 2957 "microcontroller initialization failed"); 2958 break; 2959 } 2960 if (uc->subtype == IWN_UCODE_INIT) { 2961 /* Save microcontroller report. */ 2962 memcpy(&sc->ucode_info, uc, sizeof (*uc)); 2963 } 2964 /* Save the address of the error log in SRAM. */ 2965 sc->errptr = le32toh(uc->errptr); 2966 break; 2967 } 2968 case IWN_STATE_CHANGED: 2969 { 2970 uint32_t *status = (uint32_t *)(desc + 1); 2971 2972 /* 2973 * State change allows hardware switch change to be 2974 * noted. However, we handle this in iwn_intr as we 2975 * get both the enable/disble intr. 2976 */ 2977 bus_dmamap_sync(sc->rxq.data_dmat, data->map, 2978 BUS_DMASYNC_POSTREAD); 2979 DPRINTF(sc, IWN_DEBUG_INTR, "state changed to %x\n", 2980 le32toh(*status)); 2981 break; 2982 } 2983 case IWN_START_SCAN: 2984 { 2985 struct iwn_start_scan *scan = 2986 (struct iwn_start_scan *)(desc + 1); 2987 2988 bus_dmamap_sync(sc->rxq.data_dmat, data->map, 2989 BUS_DMASYNC_POSTREAD); 2990 DPRINTF(sc, IWN_DEBUG_ANY, 2991 "%s: scanning channel %d status %x\n", 2992 __func__, scan->chan, le32toh(scan->status)); 2993 break; 2994 } 2995 case IWN_STOP_SCAN: 2996 { 2997 struct iwn_stop_scan *scan = 2998 (struct iwn_stop_scan *)(desc + 1); 2999 3000 bus_dmamap_sync(sc->rxq.data_dmat, data->map, 3001 BUS_DMASYNC_POSTREAD); 3002 DPRINTF(sc, IWN_DEBUG_STATE, 3003 "scan finished nchan=%d status=%d chan=%d\n", 3004 scan->nchan, scan->status, scan->chan); 3005 3006 IWN_UNLOCK(sc); 3007 ieee80211_scan_next(vap); 3008 IWN_LOCK(sc); 3009 break; 3010 } 3011 case IWN5000_CALIBRATION_RESULT: 3012 iwn5000_rx_calib_results(sc, desc, data); 3013 break; 3014 3015 case IWN5000_CALIBRATION_DONE: 3016 sc->sc_flags |= IWN_FLAG_CALIB_DONE; 3017 wakeup(sc); 3018 break; 3019 } 3020 3021 sc->rxq.cur = (sc->rxq.cur + 1) % IWN_RX_RING_COUNT; 3022 } 3023 3024 /* Tell the firmware what we have processed. */ 3025 hw = (hw == 0) ? IWN_RX_RING_COUNT - 1 : hw - 1; 3026 IWN_WRITE(sc, IWN_FH_RX_WPTR, hw & ~7); 3027 } 3028 3029 /* 3030 * Process an INT_WAKEUP interrupt raised when the microcontroller wakes up 3031 * from power-down sleep mode. 3032 */ 3033 static void 3034 iwn_wakeup_intr(struct iwn_softc *sc) 3035 { 3036 int qid; 3037 3038 DPRINTF(sc, IWN_DEBUG_RESET, "%s: ucode wakeup from power-down sleep\n", 3039 __func__); 3040 3041 /* Wakeup RX and TX rings. */ 3042 IWN_WRITE(sc, IWN_FH_RX_WPTR, sc->rxq.cur & ~7); 3043 for (qid = 0; qid < sc->ntxqs; qid++) { 3044 struct iwn_tx_ring *ring = &sc->txq[qid]; 3045 IWN_WRITE(sc, IWN_HBUS_TARG_WRPTR, qid << 8 | ring->cur); 3046 } 3047 } 3048 3049 static void 3050 iwn_rftoggle_intr(struct iwn_softc *sc) 3051 { 3052 struct ifnet *ifp = sc->sc_ifp; 3053 struct ieee80211com *ic = ifp->if_l2com; 3054 uint32_t tmp = IWN_READ(sc, IWN_GP_CNTRL); 3055 3056 IWN_LOCK_ASSERT(sc); 3057 3058 device_printf(sc->sc_dev, "RF switch: radio %s\n", 3059 (tmp & IWN_GP_CNTRL_RFKILL) ? "enabled" : "disabled"); 3060 if (tmp & IWN_GP_CNTRL_RFKILL) 3061 ieee80211_runtask(ic, &sc->sc_radioon_task); 3062 else 3063 ieee80211_runtask(ic, &sc->sc_radiooff_task); 3064 } 3065 3066 /* 3067 * Dump the error log of the firmware when a firmware panic occurs. Although 3068 * we can't debug the firmware because it is neither open source nor free, it 3069 * can help us to identify certain classes of problems. 3070 */ 3071 static void 3072 iwn_fatal_intr(struct iwn_softc *sc) 3073 { 3074 struct iwn_fw_dump dump; 3075 int i; 3076 3077 IWN_LOCK_ASSERT(sc); 3078 3079 /* Force a complete recalibration on next init. */ 3080 sc->sc_flags &= ~IWN_FLAG_CALIB_DONE; 3081 3082 /* Check that the error log address is valid. */ 3083 if (sc->errptr < IWN_FW_DATA_BASE || 3084 sc->errptr + sizeof (dump) > 3085 IWN_FW_DATA_BASE + sc->fw_data_maxsz) { 3086 printf("%s: bad firmware error log address 0x%08x\n", __func__, 3087 sc->errptr); 3088 return; 3089 } 3090 if (iwn_nic_lock(sc) != 0) { 3091 printf("%s: could not read firmware error log\n", __func__); 3092 return; 3093 } 3094 /* Read firmware error log from SRAM. */ 3095 iwn_mem_read_region_4(sc, sc->errptr, (uint32_t *)&dump, 3096 sizeof (dump) / sizeof (uint32_t)); 3097 iwn_nic_unlock(sc); 3098 3099 if (dump.valid == 0) { 3100 printf("%s: firmware error log is empty\n", __func__); 3101 return; 3102 } 3103 printf("firmware error log:\n"); 3104 printf(" error type = \"%s\" (0x%08X)\n", 3105 (dump.id < nitems(iwn_fw_errmsg)) ? 3106 iwn_fw_errmsg[dump.id] : "UNKNOWN", 3107 dump.id); 3108 printf(" program counter = 0x%08X\n", dump.pc); 3109 printf(" source line = 0x%08X\n", dump.src_line); 3110 printf(" error data = 0x%08X%08X\n", 3111 dump.error_data[0], dump.error_data[1]); 3112 printf(" branch link = 0x%08X%08X\n", 3113 dump.branch_link[0], dump.branch_link[1]); 3114 printf(" interrupt link = 0x%08X%08X\n", 3115 dump.interrupt_link[0], dump.interrupt_link[1]); 3116 printf(" time = %u\n", dump.time[0]); 3117 3118 /* Dump driver status (TX and RX rings) while we're here. */ 3119 printf("driver status:\n"); 3120 for (i = 0; i < sc->ntxqs; i++) { 3121 struct iwn_tx_ring *ring = &sc->txq[i]; 3122 printf(" tx ring %2d: qid=%-2d cur=%-3d queued=%-3d\n", 3123 i, ring->qid, ring->cur, ring->queued); 3124 } 3125 printf(" rx ring: cur=%d\n", sc->rxq.cur); 3126 } 3127 3128 static void 3129 iwn_intr(void *arg) 3130 { 3131 struct iwn_softc *sc = arg; 3132 struct ifnet *ifp = sc->sc_ifp; 3133 uint32_t r1, r2, tmp; 3134 3135 IWN_LOCK(sc); 3136 3137 /* Disable interrupts. */ 3138 IWN_WRITE(sc, IWN_INT_MASK, 0); 3139 3140 /* Read interrupts from ICT (fast) or from registers (slow). */ 3141 if (sc->sc_flags & IWN_FLAG_USE_ICT) { 3142 tmp = 0; 3143 while (sc->ict[sc->ict_cur] != 0) { 3144 tmp |= sc->ict[sc->ict_cur]; 3145 sc->ict[sc->ict_cur] = 0; /* Acknowledge. */ 3146 sc->ict_cur = (sc->ict_cur + 1) % IWN_ICT_COUNT; 3147 } 3148 tmp = le32toh(tmp); 3149 if (tmp == 0xffffffff) /* Shouldn't happen. */ 3150 tmp = 0; 3151 else if (tmp & 0xc0000) /* Workaround a HW bug. */ 3152 tmp |= 0x8000; 3153 r1 = (tmp & 0xff00) << 16 | (tmp & 0xff); 3154 r2 = 0; /* Unused. */ 3155 } else { 3156 r1 = IWN_READ(sc, IWN_INT); 3157 if (r1 == 0xffffffff || (r1 & 0xfffffff0) == 0xa5a5a5a0) 3158 return; /* Hardware gone! */ 3159 r2 = IWN_READ(sc, IWN_FH_INT); 3160 } 3161 3162 DPRINTF(sc, IWN_DEBUG_INTR, "interrupt reg1=%x reg2=%x\n", r1, r2); 3163 3164 if (r1 == 0 && r2 == 0) 3165 goto done; /* Interrupt not for us. */ 3166 3167 /* Acknowledge interrupts. */ 3168 IWN_WRITE(sc, IWN_INT, r1); 3169 if (!(sc->sc_flags & IWN_FLAG_USE_ICT)) 3170 IWN_WRITE(sc, IWN_FH_INT, r2); 3171 3172 if (r1 & IWN_INT_RF_TOGGLED) { 3173 iwn_rftoggle_intr(sc); 3174 goto done; 3175 } 3176 if (r1 & IWN_INT_CT_REACHED) { 3177 device_printf(sc->sc_dev, "%s: critical temperature reached!\n", 3178 __func__); 3179 } 3180 if (r1 & (IWN_INT_SW_ERR | IWN_INT_HW_ERR)) { 3181 device_printf(sc->sc_dev, "%s: fatal firmware error\n", 3182 __func__); 3183 /* Dump firmware error log and stop. */ 3184 iwn_fatal_intr(sc); 3185 ifp->if_flags &= ~IFF_UP; 3186 iwn_stop_locked(sc); 3187 goto done; 3188 } 3189 if ((r1 & (IWN_INT_FH_RX | IWN_INT_SW_RX | IWN_INT_RX_PERIODIC)) || 3190 (r2 & IWN_FH_INT_RX)) { 3191 if (sc->sc_flags & IWN_FLAG_USE_ICT) { 3192 if (r1 & (IWN_INT_FH_RX | IWN_INT_SW_RX)) 3193 IWN_WRITE(sc, IWN_FH_INT, IWN_FH_INT_RX); 3194 IWN_WRITE_1(sc, IWN_INT_PERIODIC, 3195 IWN_INT_PERIODIC_DIS); 3196 iwn_notif_intr(sc); 3197 if (r1 & (IWN_INT_FH_RX | IWN_INT_SW_RX)) { 3198 IWN_WRITE_1(sc, IWN_INT_PERIODIC, 3199 IWN_INT_PERIODIC_ENA); 3200 } 3201 } else 3202 iwn_notif_intr(sc); 3203 } 3204 3205 if ((r1 & IWN_INT_FH_TX) || (r2 & IWN_FH_INT_TX)) { 3206 if (sc->sc_flags & IWN_FLAG_USE_ICT) 3207 IWN_WRITE(sc, IWN_FH_INT, IWN_FH_INT_TX); 3208 wakeup(sc); /* FH DMA transfer completed. */ 3209 } 3210 3211 if (r1 & IWN_INT_ALIVE) 3212 wakeup(sc); /* Firmware is alive. */ 3213 3214 if (r1 & IWN_INT_WAKEUP) 3215 iwn_wakeup_intr(sc); 3216 3217 done: 3218 /* Re-enable interrupts. */ 3219 if (ifp->if_flags & IFF_UP) 3220 IWN_WRITE(sc, IWN_INT_MASK, sc->int_mask); 3221 3222 IWN_UNLOCK(sc); 3223 } 3224 3225 /* 3226 * Update TX scheduler ring when transmitting an 802.11 frame (4965AGN and 3227 * 5000 adapters use a slightly different format). 3228 */ 3229 static void 3230 iwn4965_update_sched(struct iwn_softc *sc, int qid, int idx, uint8_t id, 3231 uint16_t len) 3232 { 3233 uint16_t *w = &sc->sched[qid * IWN4965_SCHED_COUNT + idx]; 3234 3235 *w = htole16(len + 8); 3236 bus_dmamap_sync(sc->sched_dma.tag, sc->sched_dma.map, 3237 BUS_DMASYNC_PREWRITE); 3238 if (idx < IWN_SCHED_WINSZ) { 3239 *(w + IWN_TX_RING_COUNT) = *w; 3240 bus_dmamap_sync(sc->sched_dma.tag, sc->sched_dma.map, 3241 BUS_DMASYNC_PREWRITE); 3242 } 3243 } 3244 3245 static void 3246 iwn5000_update_sched(struct iwn_softc *sc, int qid, int idx, uint8_t id, 3247 uint16_t len) 3248 { 3249 uint16_t *w = &sc->sched[qid * IWN5000_SCHED_COUNT + idx]; 3250 3251 *w = htole16(id << 12 | (len + 8)); 3252 bus_dmamap_sync(sc->sched_dma.tag, sc->sched_dma.map, 3253 BUS_DMASYNC_PREWRITE); 3254 if (idx < IWN_SCHED_WINSZ) { 3255 *(w + IWN_TX_RING_COUNT) = *w; 3256 bus_dmamap_sync(sc->sched_dma.tag, sc->sched_dma.map, 3257 BUS_DMASYNC_PREWRITE); 3258 } 3259 } 3260 3261 #ifdef notyet 3262 static void 3263 iwn5000_reset_sched(struct iwn_softc *sc, int qid, int idx) 3264 { 3265 uint16_t *w = &sc->sched[qid * IWN5000_SCHED_COUNT + idx]; 3266 3267 *w = (*w & htole16(0xf000)) | htole16(1); 3268 bus_dmamap_sync(sc->sched_dma.tag, sc->sched_dma.map, 3269 BUS_DMASYNC_PREWRITE); 3270 if (idx < IWN_SCHED_WINSZ) { 3271 *(w + IWN_TX_RING_COUNT) = *w; 3272 bus_dmamap_sync(sc->sched_dma.tag, sc->sched_dma.map, 3273 BUS_DMASYNC_PREWRITE); 3274 } 3275 } 3276 #endif 3277 3278 static int 3279 iwn_tx_data(struct iwn_softc *sc, struct mbuf *m, struct ieee80211_node *ni) 3280 { 3281 struct iwn_ops *ops = &sc->ops; 3282 const struct ieee80211_txparam *tp; 3283 struct ieee80211vap *vap = ni->ni_vap; 3284 struct ieee80211com *ic = ni->ni_ic; 3285 struct iwn_node *wn = (void *)ni; 3286 struct iwn_tx_ring *ring; 3287 struct iwn_tx_desc *desc; 3288 struct iwn_tx_data *data; 3289 struct iwn_tx_cmd *cmd; 3290 struct iwn_cmd_data *tx; 3291 struct ieee80211_frame *wh; 3292 struct ieee80211_key *k = NULL; 3293 struct mbuf *m1; 3294 uint32_t flags; 3295 uint16_t qos; 3296 u_int hdrlen; 3297 bus_dma_segment_t *seg, segs[IWN_MAX_SCATTER]; 3298 uint8_t tid, ridx, txant, type; 3299 int ac, i, totlen, error, pad, nsegs = 0, rate; 3300 3301 IWN_LOCK_ASSERT(sc); 3302 3303 wh = mtod(m, struct ieee80211_frame *); 3304 hdrlen = ieee80211_anyhdrsize(wh); 3305 type = wh->i_fc[0] & IEEE80211_FC0_TYPE_MASK; 3306 3307 /* Select EDCA Access Category and TX ring for this frame. */ 3308 if (IEEE80211_QOS_HAS_SEQ(wh)) { 3309 qos = ((const struct ieee80211_qosframe *)wh)->i_qos[0]; 3310 tid = qos & IEEE80211_QOS_TID; 3311 } else { 3312 qos = 0; 3313 tid = 0; 3314 } 3315 ac = M_WME_GETAC(m); 3316 3317 if (IEEE80211_QOS_HAS_SEQ(wh) && 3318 IEEE80211_AMPDU_RUNNING(&ni->ni_tx_ampdu[ac])) { 3319 struct ieee80211_tx_ampdu *tap = &ni->ni_tx_ampdu[ac]; 3320 3321 ring = &sc->txq[*(int *)tap->txa_private]; 3322 *(uint16_t *)wh->i_seq = 3323 htole16(ni->ni_txseqs[tid] << IEEE80211_SEQ_SEQ_SHIFT); 3324 ni->ni_txseqs[tid]++; 3325 } else { 3326 ring = &sc->txq[ac]; 3327 } 3328 desc = &ring->desc[ring->cur]; 3329 data = &ring->data[ring->cur]; 3330 3331 /* Choose a TX rate index. */ 3332 tp = &vap->iv_txparms[ieee80211_chan2mode(ni->ni_chan)]; 3333 if (type == IEEE80211_FC0_TYPE_MGT) 3334 rate = tp->mgmtrate; 3335 else if (IEEE80211_IS_MULTICAST(wh->i_addr1)) 3336 rate = tp->mcastrate; 3337 else if (tp->ucastrate != IEEE80211_FIXED_RATE_NONE) 3338 rate = tp->ucastrate; 3339 else { 3340 /* XXX pass pktlen */ 3341 (void) ieee80211_ratectl_rate(ni, NULL, 0); 3342 rate = ni->ni_txrate; 3343 } 3344 ridx = ic->ic_rt->rateCodeToIndex[rate]; 3345 3346 /* Encrypt the frame if need be. */ 3347 if (wh->i_fc[1] & IEEE80211_FC1_WEP) { 3348 /* Retrieve key for TX. */ 3349 k = ieee80211_crypto_encap(ni, m); 3350 if (k == NULL) { 3351 m_freem(m); 3352 return ENOBUFS; 3353 } 3354 /* 802.11 header may have moved. */ 3355 wh = mtod(m, struct ieee80211_frame *); 3356 } 3357 totlen = m->m_pkthdr.len; 3358 3359 if (ieee80211_radiotap_active_vap(vap)) { 3360 struct iwn_tx_radiotap_header *tap = &sc->sc_txtap; 3361 3362 tap->wt_flags = 0; 3363 tap->wt_rate = rate; 3364 if (k != NULL) 3365 tap->wt_flags |= IEEE80211_RADIOTAP_F_WEP; 3366 3367 ieee80211_radiotap_tx(vap, m); 3368 } 3369 3370 /* Prepare TX firmware command. */ 3371 cmd = &ring->cmd[ring->cur]; 3372 cmd->code = IWN_CMD_TX_DATA; 3373 cmd->flags = 0; 3374 cmd->qid = ring->qid; 3375 cmd->idx = ring->cur; 3376 3377 tx = (struct iwn_cmd_data *)cmd->data; 3378 /* NB: No need to clear tx, all fields are reinitialized here. */ 3379 tx->scratch = 0; /* clear "scratch" area */ 3380 3381 flags = 0; 3382 if (!IEEE80211_IS_MULTICAST(wh->i_addr1)) { 3383 /* Unicast frame, check if an ACK is expected. */ 3384 if (!qos || (qos & IEEE80211_QOS_ACKPOLICY) != 3385 IEEE80211_QOS_ACKPOLICY_NOACK) 3386 flags |= IWN_TX_NEED_ACK; 3387 } 3388 if ((wh->i_fc[0] & 3389 (IEEE80211_FC0_TYPE_MASK | IEEE80211_FC0_SUBTYPE_MASK)) == 3390 (IEEE80211_FC0_TYPE_CTL | IEEE80211_FC0_SUBTYPE_BAR)) 3391 flags |= IWN_TX_IMM_BA; /* Cannot happen yet. */ 3392 3393 if (wh->i_fc[1] & IEEE80211_FC1_MORE_FRAG) 3394 flags |= IWN_TX_MORE_FRAG; /* Cannot happen yet. */ 3395 3396 /* Check if frame must be protected using RTS/CTS or CTS-to-self. */ 3397 if (!IEEE80211_IS_MULTICAST(wh->i_addr1)) { 3398 /* NB: Group frames are sent using CCK in 802.11b/g. */ 3399 if (totlen + IEEE80211_CRC_LEN > vap->iv_rtsthreshold) { 3400 flags |= IWN_TX_NEED_RTS; 3401 } else if ((ic->ic_flags & IEEE80211_F_USEPROT) && 3402 ridx >= IWN_RIDX_OFDM6) { 3403 if (ic->ic_protmode == IEEE80211_PROT_CTSONLY) 3404 flags |= IWN_TX_NEED_CTS; 3405 else if (ic->ic_protmode == IEEE80211_PROT_RTSCTS) 3406 flags |= IWN_TX_NEED_RTS; 3407 } 3408 if (flags & (IWN_TX_NEED_RTS | IWN_TX_NEED_CTS)) { 3409 if (sc->hw_type != IWN_HW_REV_TYPE_4965) { 3410 /* 5000 autoselects RTS/CTS or CTS-to-self. */ 3411 flags &= ~(IWN_TX_NEED_RTS | IWN_TX_NEED_CTS); 3412 flags |= IWN_TX_NEED_PROTECTION; 3413 } else 3414 flags |= IWN_TX_FULL_TXOP; 3415 } 3416 } 3417 3418 if (IEEE80211_IS_MULTICAST(wh->i_addr1) || 3419 type != IEEE80211_FC0_TYPE_DATA) 3420 tx->id = sc->broadcast_id; 3421 else 3422 tx->id = wn->id; 3423 3424 if (type == IEEE80211_FC0_TYPE_MGT) { 3425 uint8_t subtype = wh->i_fc[0] & IEEE80211_FC0_SUBTYPE_MASK; 3426 3427 /* Tell HW to set timestamp in probe responses. */ 3428 if (subtype == IEEE80211_FC0_SUBTYPE_PROBE_RESP) 3429 flags |= IWN_TX_INSERT_TSTAMP; 3430 if (subtype == IEEE80211_FC0_SUBTYPE_ASSOC_REQ || 3431 subtype == IEEE80211_FC0_SUBTYPE_REASSOC_REQ) 3432 tx->timeout = htole16(3); 3433 else 3434 tx->timeout = htole16(2); 3435 } else 3436 tx->timeout = htole16(0); 3437 3438 if (hdrlen & 3) { 3439 /* First segment length must be a multiple of 4. */ 3440 flags |= IWN_TX_NEED_PADDING; 3441 pad = 4 - (hdrlen & 3); 3442 } else 3443 pad = 0; 3444 3445 tx->len = htole16(totlen); 3446 tx->tid = tid; 3447 tx->rts_ntries = 60; 3448 tx->data_ntries = 15; 3449 tx->lifetime = htole32(IWN_LIFETIME_INFINITE); 3450 tx->rate = wn->ridx[rate]; 3451 if (tx->id == sc->broadcast_id) { 3452 /* Group or management frame. */ 3453 tx->linkq = 0; 3454 /* XXX Alternate between antenna A and B? */ 3455 txant = IWN_LSB(sc->txchainmask); 3456 tx->rate |= htole32(IWN_RFLAG_ANT(txant)); 3457 } else { 3458 tx->linkq = ni->ni_rates.rs_nrates - ridx - 1; 3459 flags |= IWN_TX_LINKQ; /* enable MRR */ 3460 } 3461 /* Set physical address of "scratch area". */ 3462 tx->loaddr = htole32(IWN_LOADDR(data->scratch_paddr)); 3463 tx->hiaddr = IWN_HIADDR(data->scratch_paddr); 3464 3465 /* Copy 802.11 header in TX command. */ 3466 memcpy((uint8_t *)(tx + 1), wh, hdrlen); 3467 3468 /* Trim 802.11 header. */ 3469 m_adj(m, hdrlen); 3470 tx->security = 0; 3471 tx->flags = htole32(flags); 3472 3473 error = bus_dmamap_load_mbuf_sg(ring->data_dmat, data->map, m, segs, 3474 &nsegs, BUS_DMA_NOWAIT); 3475 if (error != 0) { 3476 if (error != EFBIG) { 3477 device_printf(sc->sc_dev, 3478 "%s: can't map mbuf (error %d)\n", __func__, error); 3479 m_freem(m); 3480 return error; 3481 } 3482 /* Too many DMA segments, linearize mbuf. */ 3483 m1 = m_collapse(m, M_DONTWAIT, IWN_MAX_SCATTER); 3484 if (m1 == NULL) { 3485 device_printf(sc->sc_dev, 3486 "%s: could not defrag mbuf\n", __func__); 3487 m_freem(m); 3488 return ENOBUFS; 3489 } 3490 m = m1; 3491 3492 error = bus_dmamap_load_mbuf_sg(ring->data_dmat, data->map, m, 3493 segs, &nsegs, BUS_DMA_NOWAIT); 3494 if (error != 0) { 3495 device_printf(sc->sc_dev, 3496 "%s: can't map mbuf (error %d)\n", __func__, error); 3497 m_freem(m); 3498 return error; 3499 } 3500 } 3501 3502 data->m = m; 3503 data->ni = ni; 3504 3505 DPRINTF(sc, IWN_DEBUG_XMIT, "%s: qid %d idx %d len %d nsegs %d\n", 3506 __func__, ring->qid, ring->cur, m->m_pkthdr.len, nsegs); 3507 3508 /* Fill TX descriptor. */ 3509 desc->nsegs = 1; 3510 if (m->m_len != 0) 3511 desc->nsegs += nsegs; 3512 /* First DMA segment is used by the TX command. */ 3513 desc->segs[0].addr = htole32(IWN_LOADDR(data->cmd_paddr)); 3514 desc->segs[0].len = htole16(IWN_HIADDR(data->cmd_paddr) | 3515 (4 + sizeof (*tx) + hdrlen + pad) << 4); 3516 /* Other DMA segments are for data payload. */ 3517 seg = &segs[0]; 3518 for (i = 1; i <= nsegs; i++) { 3519 desc->segs[i].addr = htole32(IWN_LOADDR(seg->ds_addr)); 3520 desc->segs[i].len = htole16(IWN_HIADDR(seg->ds_addr) | 3521 seg->ds_len << 4); 3522 seg++; 3523 } 3524 3525 bus_dmamap_sync(ring->data_dmat, data->map, BUS_DMASYNC_PREWRITE); 3526 bus_dmamap_sync(ring->data_dmat, ring->cmd_dma.map, 3527 BUS_DMASYNC_PREWRITE); 3528 bus_dmamap_sync(ring->desc_dma.tag, ring->desc_dma.map, 3529 BUS_DMASYNC_PREWRITE); 3530 3531 /* Update TX scheduler. */ 3532 if (ring->qid >= sc->firstaggqueue) 3533 ops->update_sched(sc, ring->qid, ring->cur, tx->id, totlen); 3534 3535 /* Kick TX ring. */ 3536 ring->cur = (ring->cur + 1) % IWN_TX_RING_COUNT; 3537 IWN_WRITE(sc, IWN_HBUS_TARG_WRPTR, ring->qid << 8 | ring->cur); 3538 3539 /* Mark TX ring as full if we reach a certain threshold. */ 3540 if (++ring->queued > IWN_TX_RING_HIMARK) 3541 sc->qfullmsk |= 1 << ring->qid; 3542 3543 return 0; 3544 } 3545 3546 static int 3547 iwn_tx_data_raw(struct iwn_softc *sc, struct mbuf *m, 3548 struct ieee80211_node *ni, const struct ieee80211_bpf_params *params) 3549 { 3550 struct iwn_ops *ops = &sc->ops; 3551 struct ifnet *ifp = sc->sc_ifp; 3552 struct ieee80211vap *vap = ni->ni_vap; 3553 struct ieee80211com *ic = ifp->if_l2com; 3554 struct iwn_tx_cmd *cmd; 3555 struct iwn_cmd_data *tx; 3556 struct ieee80211_frame *wh; 3557 struct iwn_tx_ring *ring; 3558 struct iwn_tx_desc *desc; 3559 struct iwn_tx_data *data; 3560 struct mbuf *m1; 3561 bus_dma_segment_t *seg, segs[IWN_MAX_SCATTER]; 3562 uint32_t flags; 3563 u_int hdrlen; 3564 int ac, totlen, error, pad, nsegs = 0, i, rate; 3565 uint8_t ridx, type, txant; 3566 3567 IWN_LOCK_ASSERT(sc); 3568 3569 wh = mtod(m, struct ieee80211_frame *); 3570 hdrlen = ieee80211_anyhdrsize(wh); 3571 type = wh->i_fc[0] & IEEE80211_FC0_TYPE_MASK; 3572 3573 ac = params->ibp_pri & 3; 3574 3575 ring = &sc->txq[ac]; 3576 desc = &ring->desc[ring->cur]; 3577 data = &ring->data[ring->cur]; 3578 3579 /* Choose a TX rate index. */ 3580 rate = params->ibp_rate0; 3581 ridx = ic->ic_rt->rateCodeToIndex[rate]; 3582 if (ridx == (uint8_t)-1) { 3583 /* XXX fall back to mcast/mgmt rate? */ 3584 m_freem(m); 3585 return EINVAL; 3586 } 3587 3588 totlen = m->m_pkthdr.len; 3589 3590 /* Prepare TX firmware command. */ 3591 cmd = &ring->cmd[ring->cur]; 3592 cmd->code = IWN_CMD_TX_DATA; 3593 cmd->flags = 0; 3594 cmd->qid = ring->qid; 3595 cmd->idx = ring->cur; 3596 3597 tx = (struct iwn_cmd_data *)cmd->data; 3598 /* NB: No need to clear tx, all fields are reinitialized here. */ 3599 tx->scratch = 0; /* clear "scratch" area */ 3600 3601 flags = 0; 3602 if ((params->ibp_flags & IEEE80211_BPF_NOACK) == 0) 3603 flags |= IWN_TX_NEED_ACK; 3604 if (params->ibp_flags & IEEE80211_BPF_RTS) { 3605 if (sc->hw_type != IWN_HW_REV_TYPE_4965) { 3606 /* 5000 autoselects RTS/CTS or CTS-to-self. */ 3607 flags &= ~IWN_TX_NEED_RTS; 3608 flags |= IWN_TX_NEED_PROTECTION; 3609 } else 3610 flags |= IWN_TX_NEED_RTS | IWN_TX_FULL_TXOP; 3611 } 3612 if (params->ibp_flags & IEEE80211_BPF_CTS) { 3613 if (sc->hw_type != IWN_HW_REV_TYPE_4965) { 3614 /* 5000 autoselects RTS/CTS or CTS-to-self. */ 3615 flags &= ~IWN_TX_NEED_CTS; 3616 flags |= IWN_TX_NEED_PROTECTION; 3617 } else 3618 flags |= IWN_TX_NEED_CTS | IWN_TX_FULL_TXOP; 3619 } 3620 if (type == IEEE80211_FC0_TYPE_MGT) { 3621 uint8_t subtype = wh->i_fc[0] & IEEE80211_FC0_SUBTYPE_MASK; 3622 3623 /* Tell HW to set timestamp in probe responses. */ 3624 if (subtype == IEEE80211_FC0_SUBTYPE_PROBE_RESP) 3625 flags |= IWN_TX_INSERT_TSTAMP; 3626 3627 if (subtype == IEEE80211_FC0_SUBTYPE_ASSOC_REQ || 3628 subtype == IEEE80211_FC0_SUBTYPE_REASSOC_REQ) 3629 tx->timeout = htole16(3); 3630 else 3631 tx->timeout = htole16(2); 3632 } else 3633 tx->timeout = htole16(0); 3634 3635 if (hdrlen & 3) { 3636 /* First segment length must be a multiple of 4. */ 3637 flags |= IWN_TX_NEED_PADDING; 3638 pad = 4 - (hdrlen & 3); 3639 } else 3640 pad = 0; 3641 3642 if (ieee80211_radiotap_active_vap(vap)) { 3643 struct iwn_tx_radiotap_header *tap = &sc->sc_txtap; 3644 3645 tap->wt_flags = 0; 3646 tap->wt_rate = rate; 3647 3648 ieee80211_radiotap_tx(vap, m); 3649 } 3650 3651 tx->len = htole16(totlen); 3652 tx->tid = 0; 3653 tx->id = sc->broadcast_id; 3654 tx->rts_ntries = params->ibp_try1; 3655 tx->data_ntries = params->ibp_try0; 3656 tx->lifetime = htole32(IWN_LIFETIME_INFINITE); 3657 tx->rate = htole32(rate2plcp(rate)); 3658 if (ridx < IWN_RIDX_OFDM6 && 3659 IEEE80211_IS_CHAN_2GHZ(ni->ni_chan)) 3660 tx->rate |= htole32(IWN_RFLAG_CCK); 3661 /* Group or management frame. */ 3662 tx->linkq = 0; 3663 txant = IWN_LSB(sc->txchainmask); 3664 tx->rate |= htole32(IWN_RFLAG_ANT(txant)); 3665 /* Set physical address of "scratch area". */ 3666 tx->loaddr = htole32(IWN_LOADDR(data->scratch_paddr)); 3667 tx->hiaddr = IWN_HIADDR(data->scratch_paddr); 3668 3669 /* Copy 802.11 header in TX command. */ 3670 memcpy((uint8_t *)(tx + 1), wh, hdrlen); 3671 3672 /* Trim 802.11 header. */ 3673 m_adj(m, hdrlen); 3674 tx->security = 0; 3675 tx->flags = htole32(flags); 3676 3677 error = bus_dmamap_load_mbuf_sg(ring->data_dmat, data->map, m, segs, 3678 &nsegs, BUS_DMA_NOWAIT); 3679 if (error != 0) { 3680 if (error != EFBIG) { 3681 device_printf(sc->sc_dev, 3682 "%s: can't map mbuf (error %d)\n", __func__, error); 3683 m_freem(m); 3684 return error; 3685 } 3686 /* Too many DMA segments, linearize mbuf. */ 3687 m1 = m_collapse(m, M_DONTWAIT, IWN_MAX_SCATTER); 3688 if (m1 == NULL) { 3689 device_printf(sc->sc_dev, 3690 "%s: could not defrag mbuf\n", __func__); 3691 m_freem(m); 3692 return ENOBUFS; 3693 } 3694 m = m1; 3695 3696 error = bus_dmamap_load_mbuf_sg(ring->data_dmat, data->map, m, 3697 segs, &nsegs, BUS_DMA_NOWAIT); 3698 if (error != 0) { 3699 device_printf(sc->sc_dev, 3700 "%s: can't map mbuf (error %d)\n", __func__, error); 3701 m_freem(m); 3702 return error; 3703 } 3704 } 3705 3706 data->m = m; 3707 data->ni = ni; 3708 3709 DPRINTF(sc, IWN_DEBUG_XMIT, "%s: qid %d idx %d len %d nsegs %d\n", 3710 __func__, ring->qid, ring->cur, m->m_pkthdr.len, nsegs); 3711 3712 /* Fill TX descriptor. */ 3713 desc->nsegs = 1; 3714 if (m->m_len != 0) 3715 desc->nsegs += nsegs; 3716 /* First DMA segment is used by the TX command. */ 3717 desc->segs[0].addr = htole32(IWN_LOADDR(data->cmd_paddr)); 3718 desc->segs[0].len = htole16(IWN_HIADDR(data->cmd_paddr) | 3719 (4 + sizeof (*tx) + hdrlen + pad) << 4); 3720 /* Other DMA segments are for data payload. */ 3721 seg = &segs[0]; 3722 for (i = 1; i <= nsegs; i++) { 3723 desc->segs[i].addr = htole32(IWN_LOADDR(seg->ds_addr)); 3724 desc->segs[i].len = htole16(IWN_HIADDR(seg->ds_addr) | 3725 seg->ds_len << 4); 3726 seg++; 3727 } 3728 3729 bus_dmamap_sync(ring->data_dmat, data->map, BUS_DMASYNC_PREWRITE); 3730 bus_dmamap_sync(ring->data_dmat, ring->cmd_dma.map, 3731 BUS_DMASYNC_PREWRITE); 3732 bus_dmamap_sync(ring->desc_dma.tag, ring->desc_dma.map, 3733 BUS_DMASYNC_PREWRITE); 3734 3735 /* Update TX scheduler. */ 3736 if (ring->qid >= sc->firstaggqueue) 3737 ops->update_sched(sc, ring->qid, ring->cur, tx->id, totlen); 3738 3739 /* Kick TX ring. */ 3740 ring->cur = (ring->cur + 1) % IWN_TX_RING_COUNT; 3741 IWN_WRITE(sc, IWN_HBUS_TARG_WRPTR, ring->qid << 8 | ring->cur); 3742 3743 /* Mark TX ring as full if we reach a certain threshold. */ 3744 if (++ring->queued > IWN_TX_RING_HIMARK) 3745 sc->qfullmsk |= 1 << ring->qid; 3746 3747 return 0; 3748 } 3749 3750 static int 3751 iwn_raw_xmit(struct ieee80211_node *ni, struct mbuf *m, 3752 const struct ieee80211_bpf_params *params) 3753 { 3754 struct ieee80211com *ic = ni->ni_ic; 3755 struct ifnet *ifp = ic->ic_ifp; 3756 struct iwn_softc *sc = ifp->if_softc; 3757 int error = 0; 3758 3759 if ((ifp->if_drv_flags & IFF_DRV_RUNNING) == 0) { 3760 ieee80211_free_node(ni); 3761 m_freem(m); 3762 return ENETDOWN; 3763 } 3764 3765 IWN_LOCK(sc); 3766 if (params == NULL) { 3767 /* 3768 * Legacy path; interpret frame contents to decide 3769 * precisely how to send the frame. 3770 */ 3771 error = iwn_tx_data(sc, m, ni); 3772 } else { 3773 /* 3774 * Caller supplied explicit parameters to use in 3775 * sending the frame. 3776 */ 3777 error = iwn_tx_data_raw(sc, m, ni, params); 3778 } 3779 if (error != 0) { 3780 /* NB: m is reclaimed on tx failure */ 3781 ieee80211_free_node(ni); 3782 ifp->if_oerrors++; 3783 } 3784 sc->sc_tx_timer = 5; 3785 3786 IWN_UNLOCK(sc); 3787 return error; 3788 } 3789 3790 static void 3791 iwn_start(struct ifnet *ifp) 3792 { 3793 struct iwn_softc *sc = ifp->if_softc; 3794 3795 IWN_LOCK(sc); 3796 iwn_start_locked(ifp); 3797 IWN_UNLOCK(sc); 3798 } 3799 3800 static void 3801 iwn_start_locked(struct ifnet *ifp) 3802 { 3803 struct iwn_softc *sc = ifp->if_softc; 3804 struct ieee80211_node *ni; 3805 struct mbuf *m; 3806 3807 IWN_LOCK_ASSERT(sc); 3808 3809 if ((ifp->if_drv_flags & IFF_DRV_RUNNING) == 0 || 3810 (ifp->if_drv_flags & IFF_DRV_OACTIVE)) 3811 return; 3812 3813 for (;;) { 3814 if (sc->qfullmsk != 0) { 3815 ifp->if_drv_flags |= IFF_DRV_OACTIVE; 3816 break; 3817 } 3818 IFQ_DRV_DEQUEUE(&ifp->if_snd, m); 3819 if (m == NULL) 3820 break; 3821 ni = (struct ieee80211_node *)m->m_pkthdr.rcvif; 3822 if (iwn_tx_data(sc, m, ni) != 0) { 3823 ieee80211_free_node(ni); 3824 ifp->if_oerrors++; 3825 continue; 3826 } 3827 sc->sc_tx_timer = 5; 3828 } 3829 } 3830 3831 static void 3832 iwn_watchdog(void *arg) 3833 { 3834 struct iwn_softc *sc = arg; 3835 struct ifnet *ifp = sc->sc_ifp; 3836 struct ieee80211com *ic = ifp->if_l2com; 3837 3838 IWN_LOCK_ASSERT(sc); 3839 3840 KASSERT(ifp->if_drv_flags & IFF_DRV_RUNNING, ("not running")); 3841 3842 if (sc->sc_tx_timer > 0) { 3843 if (--sc->sc_tx_timer == 0) { 3844 if_printf(ifp, "device timeout\n"); 3845 ieee80211_runtask(ic, &sc->sc_reinit_task); 3846 return; 3847 } 3848 } 3849 callout_reset(&sc->watchdog_to, hz, iwn_watchdog, sc); 3850 } 3851 3852 static int 3853 iwn_ioctl(struct ifnet *ifp, u_long cmd, caddr_t data) 3854 { 3855 struct iwn_softc *sc = ifp->if_softc; 3856 struct ieee80211com *ic = ifp->if_l2com; 3857 struct ieee80211vap *vap = TAILQ_FIRST(&ic->ic_vaps); 3858 struct ifreq *ifr = (struct ifreq *) data; 3859 int error = 0, startall = 0, stop = 0; 3860 3861 switch (cmd) { 3862 case SIOCGIFADDR: 3863 error = ether_ioctl(ifp, cmd, data); 3864 break; 3865 case SIOCSIFFLAGS: 3866 IWN_LOCK(sc); 3867 if (ifp->if_flags & IFF_UP) { 3868 if (!(ifp->if_drv_flags & IFF_DRV_RUNNING)) { 3869 iwn_init_locked(sc); 3870 if (IWN_READ(sc, IWN_GP_CNTRL) & IWN_GP_CNTRL_RFKILL) 3871 startall = 1; 3872 else 3873 stop = 1; 3874 } 3875 } else { 3876 if (ifp->if_drv_flags & IFF_DRV_RUNNING) 3877 iwn_stop_locked(sc); 3878 } 3879 IWN_UNLOCK(sc); 3880 if (startall) 3881 ieee80211_start_all(ic); 3882 else if (vap != NULL && stop) 3883 ieee80211_stop(vap); 3884 break; 3885 case SIOCGIFMEDIA: 3886 error = ifmedia_ioctl(ifp, ifr, &ic->ic_media, cmd); 3887 break; 3888 default: 3889 error = EINVAL; 3890 break; 3891 } 3892 return error; 3893 } 3894 3895 /* 3896 * Send a command to the firmware. 3897 */ 3898 static int 3899 iwn_cmd(struct iwn_softc *sc, int code, const void *buf, int size, int async) 3900 { 3901 struct iwn_tx_ring *ring = &sc->txq[4]; 3902 struct iwn_tx_desc *desc; 3903 struct iwn_tx_data *data; 3904 struct iwn_tx_cmd *cmd; 3905 struct mbuf *m; 3906 bus_addr_t paddr; 3907 int totlen, error; 3908 3909 if (async == 0) 3910 IWN_LOCK_ASSERT(sc); 3911 3912 desc = &ring->desc[ring->cur]; 3913 data = &ring->data[ring->cur]; 3914 totlen = 4 + size; 3915 3916 if (size > sizeof cmd->data) { 3917 /* Command is too large to fit in a descriptor. */ 3918 if (totlen > MCLBYTES) 3919 return EINVAL; 3920 m = m_getjcl(M_DONTWAIT, MT_DATA, M_PKTHDR, MJUMPAGESIZE); 3921 if (m == NULL) 3922 return ENOMEM; 3923 cmd = mtod(m, struct iwn_tx_cmd *); 3924 error = bus_dmamap_load(ring->data_dmat, data->map, cmd, 3925 totlen, iwn_dma_map_addr, &paddr, BUS_DMA_NOWAIT); 3926 if (error != 0) { 3927 m_freem(m); 3928 return error; 3929 } 3930 data->m = m; 3931 } else { 3932 cmd = &ring->cmd[ring->cur]; 3933 paddr = data->cmd_paddr; 3934 } 3935 3936 cmd->code = code; 3937 cmd->flags = 0; 3938 cmd->qid = ring->qid; 3939 cmd->idx = ring->cur; 3940 memcpy(cmd->data, buf, size); 3941 3942 desc->nsegs = 1; 3943 desc->segs[0].addr = htole32(IWN_LOADDR(paddr)); 3944 desc->segs[0].len = htole16(IWN_HIADDR(paddr) | totlen << 4); 3945 3946 DPRINTF(sc, IWN_DEBUG_CMD, "%s: %s (0x%x) flags %d qid %d idx %d\n", 3947 __func__, iwn_intr_str(cmd->code), cmd->code, 3948 cmd->flags, cmd->qid, cmd->idx); 3949 3950 if (size > sizeof cmd->data) { 3951 bus_dmamap_sync(ring->data_dmat, data->map, 3952 BUS_DMASYNC_PREWRITE); 3953 } else { 3954 bus_dmamap_sync(ring->data_dmat, ring->cmd_dma.map, 3955 BUS_DMASYNC_PREWRITE); 3956 } 3957 bus_dmamap_sync(ring->desc_dma.tag, ring->desc_dma.map, 3958 BUS_DMASYNC_PREWRITE); 3959 3960 /* Kick command ring. */ 3961 ring->cur = (ring->cur + 1) % IWN_TX_RING_COUNT; 3962 IWN_WRITE(sc, IWN_HBUS_TARG_WRPTR, ring->qid << 8 | ring->cur); 3963 3964 return async ? 0 : msleep(desc, &sc->sc_mtx, PCATCH, "iwncmd", hz); 3965 } 3966 3967 static int 3968 iwn4965_add_node(struct iwn_softc *sc, struct iwn_node_info *node, int async) 3969 { 3970 struct iwn4965_node_info hnode; 3971 caddr_t src, dst; 3972 3973 /* 3974 * We use the node structure for 5000 Series internally (it is 3975 * a superset of the one for 4965AGN). We thus copy the common 3976 * fields before sending the command. 3977 */ 3978 src = (caddr_t)node; 3979 dst = (caddr_t)&hnode; 3980 memcpy(dst, src, 48); 3981 /* Skip TSC, RX MIC and TX MIC fields from ``src''. */ 3982 memcpy(dst + 48, src + 72, 20); 3983 return iwn_cmd(sc, IWN_CMD_ADD_NODE, &hnode, sizeof hnode, async); 3984 } 3985 3986 static int 3987 iwn5000_add_node(struct iwn_softc *sc, struct iwn_node_info *node, int async) 3988 { 3989 /* Direct mapping. */ 3990 return iwn_cmd(sc, IWN_CMD_ADD_NODE, node, sizeof (*node), async); 3991 } 3992 3993 static int 3994 iwn_set_link_quality(struct iwn_softc *sc, struct ieee80211_node *ni) 3995 { 3996 #define RV(v) ((v) & IEEE80211_RATE_VAL) 3997 struct iwn_node *wn = (void *)ni; 3998 struct ieee80211_rateset *rs = &ni->ni_rates; 3999 struct iwn_cmd_link_quality linkq; 4000 uint8_t txant; 4001 int i, rate, txrate; 4002 4003 /* Use the first valid TX antenna. */ 4004 txant = IWN_LSB(sc->txchainmask); 4005 4006 memset(&linkq, 0, sizeof linkq); 4007 linkq.id = wn->id; 4008 linkq.antmsk_1stream = txant; 4009 linkq.antmsk_2stream = IWN_ANT_AB; 4010 linkq.ampdu_max = 64; 4011 linkq.ampdu_threshold = 3; 4012 linkq.ampdu_limit = htole16(4000); /* 4ms */ 4013 4014 /* Start at highest available bit-rate. */ 4015 if (IEEE80211_IS_CHAN_HT(ni->ni_chan)) 4016 txrate = ni->ni_htrates.rs_nrates - 1; 4017 else 4018 txrate = rs->rs_nrates - 1; 4019 for (i = 0; i < IWN_MAX_TX_RETRIES; i++) { 4020 if (IEEE80211_IS_CHAN_HT(ni->ni_chan)) 4021 rate = IEEE80211_RATE_MCS | txrate; 4022 else 4023 rate = RV(rs->rs_rates[txrate]); 4024 linkq.retry[i] = wn->ridx[rate]; 4025 4026 if ((le32toh(wn->ridx[rate]) & IWN_RFLAG_MCS) && 4027 RV(le32toh(wn->ridx[rate])) > 7) 4028 linkq.mimo = i + 1; 4029 4030 /* Next retry at immediate lower bit-rate. */ 4031 if (txrate > 0) 4032 txrate--; 4033 } 4034 return iwn_cmd(sc, IWN_CMD_LINK_QUALITY, &linkq, sizeof linkq, 1); 4035 #undef RV 4036 } 4037 4038 /* 4039 * Broadcast node is used to send group-addressed and management frames. 4040 */ 4041 static int 4042 iwn_add_broadcast_node(struct iwn_softc *sc, int async) 4043 { 4044 struct iwn_ops *ops = &sc->ops; 4045 struct ifnet *ifp = sc->sc_ifp; 4046 struct ieee80211com *ic = ifp->if_l2com; 4047 struct iwn_node_info node; 4048 struct iwn_cmd_link_quality linkq; 4049 uint8_t txant; 4050 int i, error; 4051 4052 memset(&node, 0, sizeof node); 4053 IEEE80211_ADDR_COPY(node.macaddr, ifp->if_broadcastaddr); 4054 node.id = sc->broadcast_id; 4055 DPRINTF(sc, IWN_DEBUG_RESET, "%s: adding broadcast node\n", __func__); 4056 if ((error = ops->add_node(sc, &node, async)) != 0) 4057 return error; 4058 4059 /* Use the first valid TX antenna. */ 4060 txant = IWN_LSB(sc->txchainmask); 4061 4062 memset(&linkq, 0, sizeof linkq); 4063 linkq.id = sc->broadcast_id; 4064 linkq.antmsk_1stream = txant; 4065 linkq.antmsk_2stream = IWN_ANT_AB; 4066 linkq.ampdu_max = 64; 4067 linkq.ampdu_threshold = 3; 4068 linkq.ampdu_limit = htole16(4000); /* 4ms */ 4069 4070 /* Use lowest mandatory bit-rate. */ 4071 if (IEEE80211_IS_CHAN_5GHZ(ic->ic_curchan)) 4072 linkq.retry[0] = htole32(0xd); 4073 else 4074 linkq.retry[0] = htole32(10 | IWN_RFLAG_CCK); 4075 linkq.retry[0] |= htole32(IWN_RFLAG_ANT(txant)); 4076 /* Use same bit-rate for all TX retries. */ 4077 for (i = 1; i < IWN_MAX_TX_RETRIES; i++) { 4078 linkq.retry[i] = linkq.retry[0]; 4079 } 4080 return iwn_cmd(sc, IWN_CMD_LINK_QUALITY, &linkq, sizeof linkq, async); 4081 } 4082 4083 static int 4084 iwn_updateedca(struct ieee80211com *ic) 4085 { 4086 #define IWN_EXP2(x) ((1 << (x)) - 1) /* CWmin = 2^ECWmin - 1 */ 4087 struct iwn_softc *sc = ic->ic_ifp->if_softc; 4088 struct iwn_edca_params cmd; 4089 int aci; 4090 4091 memset(&cmd, 0, sizeof cmd); 4092 cmd.flags = htole32(IWN_EDCA_UPDATE); 4093 for (aci = 0; aci < WME_NUM_AC; aci++) { 4094 const struct wmeParams *ac = 4095 &ic->ic_wme.wme_chanParams.cap_wmeParams[aci]; 4096 cmd.ac[aci].aifsn = ac->wmep_aifsn; 4097 cmd.ac[aci].cwmin = htole16(IWN_EXP2(ac->wmep_logcwmin)); 4098 cmd.ac[aci].cwmax = htole16(IWN_EXP2(ac->wmep_logcwmax)); 4099 cmd.ac[aci].txoplimit = 4100 htole16(IEEE80211_TXOP_TO_US(ac->wmep_txopLimit)); 4101 } 4102 IEEE80211_UNLOCK(ic); 4103 IWN_LOCK(sc); 4104 (void)iwn_cmd(sc, IWN_CMD_EDCA_PARAMS, &cmd, sizeof cmd, 1); 4105 IWN_UNLOCK(sc); 4106 IEEE80211_LOCK(ic); 4107 return 0; 4108 #undef IWN_EXP2 4109 } 4110 4111 static void 4112 iwn_update_mcast(struct ifnet *ifp) 4113 { 4114 /* Ignore */ 4115 } 4116 4117 static void 4118 iwn_set_led(struct iwn_softc *sc, uint8_t which, uint8_t off, uint8_t on) 4119 { 4120 struct iwn_cmd_led led; 4121 4122 /* Clear microcode LED ownership. */ 4123 IWN_CLRBITS(sc, IWN_LED, IWN_LED_BSM_CTRL); 4124 4125 led.which = which; 4126 led.unit = htole32(10000); /* on/off in unit of 100ms */ 4127 led.off = off; 4128 led.on = on; 4129 (void)iwn_cmd(sc, IWN_CMD_SET_LED, &led, sizeof led, 1); 4130 } 4131 4132 /* 4133 * Set the critical temperature at which the firmware will stop the radio 4134 * and notify us. 4135 */ 4136 static int 4137 iwn_set_critical_temp(struct iwn_softc *sc) 4138 { 4139 struct iwn_critical_temp crit; 4140 int32_t temp; 4141 4142 IWN_WRITE(sc, IWN_UCODE_GP1_CLR, IWN_UCODE_GP1_CTEMP_STOP_RF); 4143 4144 if (sc->hw_type == IWN_HW_REV_TYPE_5150) 4145 temp = (IWN_CTOK(110) - sc->temp_off) * -5; 4146 else if (sc->hw_type == IWN_HW_REV_TYPE_4965) 4147 temp = IWN_CTOK(110); 4148 else 4149 temp = 110; 4150 memset(&crit, 0, sizeof crit); 4151 crit.tempR = htole32(temp); 4152 DPRINTF(sc, IWN_DEBUG_RESET, "setting critical temp to %d\n", temp); 4153 return iwn_cmd(sc, IWN_CMD_SET_CRITICAL_TEMP, &crit, sizeof crit, 0); 4154 } 4155 4156 static int 4157 iwn_set_timing(struct iwn_softc *sc, struct ieee80211_node *ni) 4158 { 4159 struct iwn_cmd_timing cmd; 4160 uint64_t val, mod; 4161 4162 memset(&cmd, 0, sizeof cmd); 4163 memcpy(&cmd.tstamp, ni->ni_tstamp.data, sizeof (uint64_t)); 4164 cmd.bintval = htole16(ni->ni_intval); 4165 cmd.lintval = htole16(10); 4166 4167 /* Compute remaining time until next beacon. */ 4168 val = (uint64_t)ni->ni_intval * IEEE80211_DUR_TU; 4169 mod = le64toh(cmd.tstamp) % val; 4170 cmd.binitval = htole32((uint32_t)(val - mod)); 4171 4172 DPRINTF(sc, IWN_DEBUG_RESET, "timing bintval=%u tstamp=%ju, init=%u\n", 4173 ni->ni_intval, le64toh(cmd.tstamp), (uint32_t)(val - mod)); 4174 4175 return iwn_cmd(sc, IWN_CMD_TIMING, &cmd, sizeof cmd, 1); 4176 } 4177 4178 static void 4179 iwn4965_power_calibration(struct iwn_softc *sc, int temp) 4180 { 4181 struct ifnet *ifp = sc->sc_ifp; 4182 struct ieee80211com *ic = ifp->if_l2com; 4183 4184 /* Adjust TX power if need be (delta >= 3 degC). */ 4185 DPRINTF(sc, IWN_DEBUG_CALIBRATE, "%s: temperature %d->%d\n", 4186 __func__, sc->temp, temp); 4187 if (abs(temp - sc->temp) >= 3) { 4188 /* Record temperature of last calibration. */ 4189 sc->temp = temp; 4190 (void)iwn4965_set_txpower(sc, ic->ic_bsschan, 1); 4191 } 4192 } 4193 4194 /* 4195 * Set TX power for current channel (each rate has its own power settings). 4196 * This function takes into account the regulatory information from EEPROM, 4197 * the current temperature and the current voltage. 4198 */ 4199 static int 4200 iwn4965_set_txpower(struct iwn_softc *sc, struct ieee80211_channel *ch, 4201 int async) 4202 { 4203 /* Fixed-point arithmetic division using a n-bit fractional part. */ 4204 #define fdivround(a, b, n) \ 4205 ((((1 << n) * (a)) / (b) + (1 << n) / 2) / (1 << n)) 4206 /* Linear interpolation. */ 4207 #define interpolate(x, x1, y1, x2, y2, n) \ 4208 ((y1) + fdivround(((int)(x) - (x1)) * ((y2) - (y1)), (x2) - (x1), n)) 4209 4210 static const int tdiv[IWN_NATTEN_GROUPS] = { 9, 8, 8, 8, 6 }; 4211 struct iwn_ucode_info *uc = &sc->ucode_info; 4212 struct iwn4965_cmd_txpower cmd; 4213 struct iwn4965_eeprom_chan_samples *chans; 4214 const uint8_t *rf_gain, *dsp_gain; 4215 int32_t vdiff, tdiff; 4216 int i, c, grp, maxpwr; 4217 uint8_t chan; 4218 4219 /* Retrieve current channel from last RXON. */ 4220 chan = sc->rxon.chan; 4221 DPRINTF(sc, IWN_DEBUG_RESET, "setting TX power for channel %d\n", 4222 chan); 4223 4224 memset(&cmd, 0, sizeof cmd); 4225 cmd.band = IEEE80211_IS_CHAN_5GHZ(ch) ? 0 : 1; 4226 cmd.chan = chan; 4227 4228 if (IEEE80211_IS_CHAN_5GHZ(ch)) { 4229 maxpwr = sc->maxpwr5GHz; 4230 rf_gain = iwn4965_rf_gain_5ghz; 4231 dsp_gain = iwn4965_dsp_gain_5ghz; 4232 } else { 4233 maxpwr = sc->maxpwr2GHz; 4234 rf_gain = iwn4965_rf_gain_2ghz; 4235 dsp_gain = iwn4965_dsp_gain_2ghz; 4236 } 4237 4238 /* Compute voltage compensation. */ 4239 vdiff = ((int32_t)le32toh(uc->volt) - sc->eeprom_voltage) / 7; 4240 if (vdiff > 0) 4241 vdiff *= 2; 4242 if (abs(vdiff) > 2) 4243 vdiff = 0; 4244 DPRINTF(sc, IWN_DEBUG_CALIBRATE | IWN_DEBUG_TXPOW, 4245 "%s: voltage compensation=%d (UCODE=%d, EEPROM=%d)\n", 4246 __func__, vdiff, le32toh(uc->volt), sc->eeprom_voltage); 4247 4248 /* Get channel attenuation group. */ 4249 if (chan <= 20) /* 1-20 */ 4250 grp = 4; 4251 else if (chan <= 43) /* 34-43 */ 4252 grp = 0; 4253 else if (chan <= 70) /* 44-70 */ 4254 grp = 1; 4255 else if (chan <= 124) /* 71-124 */ 4256 grp = 2; 4257 else /* 125-200 */ 4258 grp = 3; 4259 DPRINTF(sc, IWN_DEBUG_CALIBRATE | IWN_DEBUG_TXPOW, 4260 "%s: chan %d, attenuation group=%d\n", __func__, chan, grp); 4261 4262 /* Get channel sub-band. */ 4263 for (i = 0; i < IWN_NBANDS; i++) 4264 if (sc->bands[i].lo != 0 && 4265 sc->bands[i].lo <= chan && chan <= sc->bands[i].hi) 4266 break; 4267 if (i == IWN_NBANDS) /* Can't happen in real-life. */ 4268 return EINVAL; 4269 chans = sc->bands[i].chans; 4270 DPRINTF(sc, IWN_DEBUG_CALIBRATE | IWN_DEBUG_TXPOW, 4271 "%s: chan %d sub-band=%d\n", __func__, chan, i); 4272 4273 for (c = 0; c < 2; c++) { 4274 uint8_t power, gain, temp; 4275 int maxchpwr, pwr, ridx, idx; 4276 4277 power = interpolate(chan, 4278 chans[0].num, chans[0].samples[c][1].power, 4279 chans[1].num, chans[1].samples[c][1].power, 1); 4280 gain = interpolate(chan, 4281 chans[0].num, chans[0].samples[c][1].gain, 4282 chans[1].num, chans[1].samples[c][1].gain, 1); 4283 temp = interpolate(chan, 4284 chans[0].num, chans[0].samples[c][1].temp, 4285 chans[1].num, chans[1].samples[c][1].temp, 1); 4286 DPRINTF(sc, IWN_DEBUG_CALIBRATE | IWN_DEBUG_TXPOW, 4287 "%s: Tx chain %d: power=%d gain=%d temp=%d\n", 4288 __func__, c, power, gain, temp); 4289 4290 /* Compute temperature compensation. */ 4291 tdiff = ((sc->temp - temp) * 2) / tdiv[grp]; 4292 DPRINTF(sc, IWN_DEBUG_CALIBRATE | IWN_DEBUG_TXPOW, 4293 "%s: temperature compensation=%d (current=%d, EEPROM=%d)\n", 4294 __func__, tdiff, sc->temp, temp); 4295 4296 for (ridx = 0; ridx <= IWN_RIDX_MAX; ridx++) { 4297 /* Convert dBm to half-dBm. */ 4298 maxchpwr = sc->maxpwr[chan] * 2; 4299 if ((ridx / 8) & 1) 4300 maxchpwr -= 6; /* MIMO 2T: -3dB */ 4301 4302 pwr = maxpwr; 4303 4304 /* Adjust TX power based on rate. */ 4305 if ((ridx % 8) == 5) 4306 pwr -= 15; /* OFDM48: -7.5dB */ 4307 else if ((ridx % 8) == 6) 4308 pwr -= 17; /* OFDM54: -8.5dB */ 4309 else if ((ridx % 8) == 7) 4310 pwr -= 20; /* OFDM60: -10dB */ 4311 else 4312 pwr -= 10; /* Others: -5dB */ 4313 4314 /* Do not exceed channel max TX power. */ 4315 if (pwr > maxchpwr) 4316 pwr = maxchpwr; 4317 4318 idx = gain - (pwr - power) - tdiff - vdiff; 4319 if ((ridx / 8) & 1) /* MIMO */ 4320 idx += (int32_t)le32toh(uc->atten[grp][c]); 4321 4322 if (cmd.band == 0) 4323 idx += 9; /* 5GHz */ 4324 if (ridx == IWN_RIDX_MAX) 4325 idx += 5; /* CCK */ 4326 4327 /* Make sure idx stays in a valid range. */ 4328 if (idx < 0) 4329 idx = 0; 4330 else if (idx > IWN4965_MAX_PWR_INDEX) 4331 idx = IWN4965_MAX_PWR_INDEX; 4332 4333 DPRINTF(sc, IWN_DEBUG_CALIBRATE | IWN_DEBUG_TXPOW, 4334 "%s: Tx chain %d, rate idx %d: power=%d\n", 4335 __func__, c, ridx, idx); 4336 cmd.power[ridx].rf_gain[c] = rf_gain[idx]; 4337 cmd.power[ridx].dsp_gain[c] = dsp_gain[idx]; 4338 } 4339 } 4340 4341 DPRINTF(sc, IWN_DEBUG_CALIBRATE | IWN_DEBUG_TXPOW, 4342 "%s: set tx power for chan %d\n", __func__, chan); 4343 return iwn_cmd(sc, IWN_CMD_TXPOWER, &cmd, sizeof cmd, async); 4344 4345 #undef interpolate 4346 #undef fdivround 4347 } 4348 4349 static int 4350 iwn5000_set_txpower(struct iwn_softc *sc, struct ieee80211_channel *ch, 4351 int async) 4352 { 4353 struct iwn5000_cmd_txpower cmd; 4354 4355 /* 4356 * TX power calibration is handled automatically by the firmware 4357 * for 5000 Series. 4358 */ 4359 memset(&cmd, 0, sizeof cmd); 4360 cmd.global_limit = 2 * IWN5000_TXPOWER_MAX_DBM; /* 16 dBm */ 4361 cmd.flags = IWN5000_TXPOWER_NO_CLOSED; 4362 cmd.srv_limit = IWN5000_TXPOWER_AUTO; 4363 DPRINTF(sc, IWN_DEBUG_CALIBRATE, "%s: setting TX power\n", __func__); 4364 return iwn_cmd(sc, IWN_CMD_TXPOWER_DBM, &cmd, sizeof cmd, async); 4365 } 4366 4367 /* 4368 * Retrieve the maximum RSSI (in dBm) among receivers. 4369 */ 4370 static int 4371 iwn4965_get_rssi(struct iwn_softc *sc, struct iwn_rx_stat *stat) 4372 { 4373 struct iwn4965_rx_phystat *phy = (void *)stat->phybuf; 4374 uint8_t mask, agc; 4375 int rssi; 4376 4377 mask = (le16toh(phy->antenna) >> 4) & IWN_ANT_ABC; 4378 agc = (le16toh(phy->agc) >> 7) & 0x7f; 4379 4380 rssi = 0; 4381 if (mask & IWN_ANT_A) 4382 rssi = MAX(rssi, phy->rssi[0]); 4383 if (mask & IWN_ANT_B) 4384 rssi = MAX(rssi, phy->rssi[2]); 4385 if (mask & IWN_ANT_C) 4386 rssi = MAX(rssi, phy->rssi[4]); 4387 4388 DPRINTF(sc, IWN_DEBUG_RECV, 4389 "%s: agc %d mask 0x%x rssi %d %d %d result %d\n", __func__, agc, 4390 mask, phy->rssi[0], phy->rssi[2], phy->rssi[4], 4391 rssi - agc - IWN_RSSI_TO_DBM); 4392 return rssi - agc - IWN_RSSI_TO_DBM; 4393 } 4394 4395 static int 4396 iwn5000_get_rssi(struct iwn_softc *sc, struct iwn_rx_stat *stat) 4397 { 4398 struct iwn5000_rx_phystat *phy = (void *)stat->phybuf; 4399 uint8_t agc; 4400 int rssi; 4401 4402 agc = (le32toh(phy->agc) >> 9) & 0x7f; 4403 4404 rssi = MAX(le16toh(phy->rssi[0]) & 0xff, 4405 le16toh(phy->rssi[1]) & 0xff); 4406 rssi = MAX(le16toh(phy->rssi[2]) & 0xff, rssi); 4407 4408 DPRINTF(sc, IWN_DEBUG_RECV, 4409 "%s: agc %d rssi %d %d %d result %d\n", __func__, agc, 4410 phy->rssi[0], phy->rssi[1], phy->rssi[2], 4411 rssi - agc - IWN_RSSI_TO_DBM); 4412 return rssi - agc - IWN_RSSI_TO_DBM; 4413 } 4414 4415 /* 4416 * Retrieve the average noise (in dBm) among receivers. 4417 */ 4418 static int 4419 iwn_get_noise(const struct iwn_rx_general_stats *stats) 4420 { 4421 int i, total, nbant, noise; 4422 4423 total = nbant = 0; 4424 for (i = 0; i < 3; i++) { 4425 if ((noise = le32toh(stats->noise[i]) & 0xff) == 0) 4426 continue; 4427 total += noise; 4428 nbant++; 4429 } 4430 /* There should be at least one antenna but check anyway. */ 4431 return (nbant == 0) ? -127 : (total / nbant) - 107; 4432 } 4433 4434 /* 4435 * Compute temperature (in degC) from last received statistics. 4436 */ 4437 static int 4438 iwn4965_get_temperature(struct iwn_softc *sc) 4439 { 4440 struct iwn_ucode_info *uc = &sc->ucode_info; 4441 int32_t r1, r2, r3, r4, temp; 4442 4443 r1 = le32toh(uc->temp[0].chan20MHz); 4444 r2 = le32toh(uc->temp[1].chan20MHz); 4445 r3 = le32toh(uc->temp[2].chan20MHz); 4446 r4 = le32toh(sc->rawtemp); 4447 4448 if (r1 == r3) /* Prevents division by 0 (should not happen). */ 4449 return 0; 4450 4451 /* Sign-extend 23-bit R4 value to 32-bit. */ 4452 r4 = ((r4 & 0xffffff) ^ 0x800000) - 0x800000; 4453 /* Compute temperature in Kelvin. */ 4454 temp = (259 * (r4 - r2)) / (r3 - r1); 4455 temp = (temp * 97) / 100 + 8; 4456 4457 DPRINTF(sc, IWN_DEBUG_ANY, "temperature %dK/%dC\n", temp, 4458 IWN_KTOC(temp)); 4459 return IWN_KTOC(temp); 4460 } 4461 4462 static int 4463 iwn5000_get_temperature(struct iwn_softc *sc) 4464 { 4465 int32_t temp; 4466 4467 /* 4468 * Temperature is not used by the driver for 5000 Series because 4469 * TX power calibration is handled by firmware. 4470 */ 4471 temp = le32toh(sc->rawtemp); 4472 if (sc->hw_type == IWN_HW_REV_TYPE_5150) { 4473 temp = (temp / -5) + sc->temp_off; 4474 temp = IWN_KTOC(temp); 4475 } 4476 return temp; 4477 } 4478 4479 /* 4480 * Initialize sensitivity calibration state machine. 4481 */ 4482 static int 4483 iwn_init_sensitivity(struct iwn_softc *sc) 4484 { 4485 struct iwn_ops *ops = &sc->ops; 4486 struct iwn_calib_state *calib = &sc->calib; 4487 uint32_t flags; 4488 int error; 4489 4490 /* Reset calibration state machine. */ 4491 memset(calib, 0, sizeof (*calib)); 4492 calib->state = IWN_CALIB_STATE_INIT; 4493 calib->cck_state = IWN_CCK_STATE_HIFA; 4494 /* Set initial correlation values. */ 4495 calib->ofdm_x1 = sc->limits->min_ofdm_x1; 4496 calib->ofdm_mrc_x1 = sc->limits->min_ofdm_mrc_x1; 4497 calib->ofdm_x4 = sc->limits->min_ofdm_x4; 4498 calib->ofdm_mrc_x4 = sc->limits->min_ofdm_mrc_x4; 4499 calib->cck_x4 = 125; 4500 calib->cck_mrc_x4 = sc->limits->min_cck_mrc_x4; 4501 calib->energy_cck = sc->limits->energy_cck; 4502 4503 /* Write initial sensitivity. */ 4504 if ((error = iwn_send_sensitivity(sc)) != 0) 4505 return error; 4506 4507 /* Write initial gains. */ 4508 if ((error = ops->init_gains(sc)) != 0) 4509 return error; 4510 4511 /* Request statistics at each beacon interval. */ 4512 flags = 0; 4513 DPRINTF(sc, IWN_DEBUG_CALIBRATE, "%s: sending request for statistics\n", 4514 __func__); 4515 return iwn_cmd(sc, IWN_CMD_GET_STATISTICS, &flags, sizeof flags, 1); 4516 } 4517 4518 /* 4519 * Collect noise and RSSI statistics for the first 20 beacons received 4520 * after association and use them to determine connected antennas and 4521 * to set differential gains. 4522 */ 4523 static void 4524 iwn_collect_noise(struct iwn_softc *sc, 4525 const struct iwn_rx_general_stats *stats) 4526 { 4527 struct iwn_ops *ops = &sc->ops; 4528 struct iwn_calib_state *calib = &sc->calib; 4529 uint32_t val; 4530 int i; 4531 4532 /* Accumulate RSSI and noise for all 3 antennas. */ 4533 for (i = 0; i < 3; i++) { 4534 calib->rssi[i] += le32toh(stats->rssi[i]) & 0xff; 4535 calib->noise[i] += le32toh(stats->noise[i]) & 0xff; 4536 } 4537 /* NB: We update differential gains only once after 20 beacons. */ 4538 if (++calib->nbeacons < 20) 4539 return; 4540 4541 /* Determine highest average RSSI. */ 4542 val = MAX(calib->rssi[0], calib->rssi[1]); 4543 val = MAX(calib->rssi[2], val); 4544 4545 /* Determine which antennas are connected. */ 4546 sc->chainmask = sc->rxchainmask; 4547 for (i = 0; i < 3; i++) 4548 if (val - calib->rssi[i] > 15 * 20) 4549 sc->chainmask &= ~(1 << i); 4550 DPRINTF(sc, IWN_DEBUG_CALIBRATE, 4551 "%s: RX chains mask: theoretical=0x%x, actual=0x%x\n", 4552 __func__, sc->rxchainmask, sc->chainmask); 4553 4554 /* If none of the TX antennas are connected, keep at least one. */ 4555 if ((sc->chainmask & sc->txchainmask) == 0) 4556 sc->chainmask |= IWN_LSB(sc->txchainmask); 4557 4558 (void)ops->set_gains(sc); 4559 calib->state = IWN_CALIB_STATE_RUN; 4560 4561 #ifdef notyet 4562 /* XXX Disable RX chains with no antennas connected. */ 4563 sc->rxon.rxchain = htole16(IWN_RXCHAIN_SEL(sc->chainmask)); 4564 (void)iwn_cmd(sc, IWN_CMD_RXON, &sc->rxon, sc->rxonsz, 1); 4565 #endif 4566 4567 #if 0 4568 /* XXX: not yet */ 4569 /* Enable power-saving mode if requested by user. */ 4570 if (sc->sc_ic.ic_flags & IEEE80211_F_PMGTON) 4571 (void)iwn_set_pslevel(sc, 0, 3, 1); 4572 #endif 4573 } 4574 4575 static int 4576 iwn4965_init_gains(struct iwn_softc *sc) 4577 { 4578 struct iwn_phy_calib_gain cmd; 4579 4580 memset(&cmd, 0, sizeof cmd); 4581 cmd.code = IWN4965_PHY_CALIB_DIFF_GAIN; 4582 /* Differential gains initially set to 0 for all 3 antennas. */ 4583 DPRINTF(sc, IWN_DEBUG_CALIBRATE, 4584 "%s: setting initial differential gains\n", __func__); 4585 return iwn_cmd(sc, IWN_CMD_PHY_CALIB, &cmd, sizeof cmd, 1); 4586 } 4587 4588 static int 4589 iwn5000_init_gains(struct iwn_softc *sc) 4590 { 4591 struct iwn_phy_calib cmd; 4592 4593 memset(&cmd, 0, sizeof cmd); 4594 cmd.code = sc->reset_noise_gain; 4595 cmd.ngroups = 1; 4596 cmd.isvalid = 1; 4597 DPRINTF(sc, IWN_DEBUG_CALIBRATE, 4598 "%s: setting initial differential gains\n", __func__); 4599 return iwn_cmd(sc, IWN_CMD_PHY_CALIB, &cmd, sizeof cmd, 1); 4600 } 4601 4602 static int 4603 iwn4965_set_gains(struct iwn_softc *sc) 4604 { 4605 struct iwn_calib_state *calib = &sc->calib; 4606 struct iwn_phy_calib_gain cmd; 4607 int i, delta, noise; 4608 4609 /* Get minimal noise among connected antennas. */ 4610 noise = INT_MAX; /* NB: There's at least one antenna. */ 4611 for (i = 0; i < 3; i++) 4612 if (sc->chainmask & (1 << i)) 4613 noise = MIN(calib->noise[i], noise); 4614 4615 memset(&cmd, 0, sizeof cmd); 4616 cmd.code = IWN4965_PHY_CALIB_DIFF_GAIN; 4617 /* Set differential gains for connected antennas. */ 4618 for (i = 0; i < 3; i++) { 4619 if (sc->chainmask & (1 << i)) { 4620 /* Compute attenuation (in unit of 1.5dB). */ 4621 delta = (noise - (int32_t)calib->noise[i]) / 30; 4622 /* NB: delta <= 0 */ 4623 /* Limit to [-4.5dB,0]. */ 4624 cmd.gain[i] = MIN(abs(delta), 3); 4625 if (delta < 0) 4626 cmd.gain[i] |= 1 << 2; /* sign bit */ 4627 } 4628 } 4629 DPRINTF(sc, IWN_DEBUG_CALIBRATE, 4630 "setting differential gains Ant A/B/C: %x/%x/%x (%x)\n", 4631 cmd.gain[0], cmd.gain[1], cmd.gain[2], sc->chainmask); 4632 return iwn_cmd(sc, IWN_CMD_PHY_CALIB, &cmd, sizeof cmd, 1); 4633 } 4634 4635 static int 4636 iwn5000_set_gains(struct iwn_softc *sc) 4637 { 4638 struct iwn_calib_state *calib = &sc->calib; 4639 struct iwn_phy_calib_gain cmd; 4640 int i, ant, div, delta; 4641 4642 /* We collected 20 beacons and !=6050 need a 1.5 factor. */ 4643 div = (sc->hw_type == IWN_HW_REV_TYPE_6050) ? 20 : 30; 4644 4645 memset(&cmd, 0, sizeof cmd); 4646 cmd.code = sc->noise_gain; 4647 cmd.ngroups = 1; 4648 cmd.isvalid = 1; 4649 /* Get first available RX antenna as referential. */ 4650 ant = IWN_LSB(sc->rxchainmask); 4651 /* Set differential gains for other antennas. */ 4652 for (i = ant + 1; i < 3; i++) { 4653 if (sc->chainmask & (1 << i)) { 4654 /* The delta is relative to antenna "ant". */ 4655 delta = ((int32_t)calib->noise[ant] - 4656 (int32_t)calib->noise[i]) / div; 4657 /* Limit to [-4.5dB,+4.5dB]. */ 4658 cmd.gain[i - 1] = MIN(abs(delta), 3); 4659 if (delta < 0) 4660 cmd.gain[i - 1] |= 1 << 2; /* sign bit */ 4661 } 4662 } 4663 DPRINTF(sc, IWN_DEBUG_CALIBRATE, 4664 "setting differential gains Ant B/C: %x/%x (%x)\n", 4665 cmd.gain[0], cmd.gain[1], sc->chainmask); 4666 return iwn_cmd(sc, IWN_CMD_PHY_CALIB, &cmd, sizeof cmd, 1); 4667 } 4668 4669 /* 4670 * Tune RF RX sensitivity based on the number of false alarms detected 4671 * during the last beacon period. 4672 */ 4673 static void 4674 iwn_tune_sensitivity(struct iwn_softc *sc, const struct iwn_rx_stats *stats) 4675 { 4676 #define inc(val, inc, max) \ 4677 if ((val) < (max)) { \ 4678 if ((val) < (max) - (inc)) \ 4679 (val) += (inc); \ 4680 else \ 4681 (val) = (max); \ 4682 needs_update = 1; \ 4683 } 4684 #define dec(val, dec, min) \ 4685 if ((val) > (min)) { \ 4686 if ((val) > (min) + (dec)) \ 4687 (val) -= (dec); \ 4688 else \ 4689 (val) = (min); \ 4690 needs_update = 1; \ 4691 } 4692 4693 const struct iwn_sensitivity_limits *limits = sc->limits; 4694 struct iwn_calib_state *calib = &sc->calib; 4695 uint32_t val, rxena, fa; 4696 uint32_t energy[3], energy_min; 4697 uint8_t noise[3], noise_ref; 4698 int i, needs_update = 0; 4699 4700 /* Check that we've been enabled long enough. */ 4701 if ((rxena = le32toh(stats->general.load)) == 0) 4702 return; 4703 4704 /* Compute number of false alarms since last call for OFDM. */ 4705 fa = le32toh(stats->ofdm.bad_plcp) - calib->bad_plcp_ofdm; 4706 fa += le32toh(stats->ofdm.fa) - calib->fa_ofdm; 4707 fa *= 200 * IEEE80211_DUR_TU; /* 200TU */ 4708 4709 /* Save counters values for next call. */ 4710 calib->bad_plcp_ofdm = le32toh(stats->ofdm.bad_plcp); 4711 calib->fa_ofdm = le32toh(stats->ofdm.fa); 4712 4713 if (fa > 50 * rxena) { 4714 /* High false alarm count, decrease sensitivity. */ 4715 DPRINTF(sc, IWN_DEBUG_CALIBRATE, 4716 "%s: OFDM high false alarm count: %u\n", __func__, fa); 4717 inc(calib->ofdm_x1, 1, limits->max_ofdm_x1); 4718 inc(calib->ofdm_mrc_x1, 1, limits->max_ofdm_mrc_x1); 4719 inc(calib->ofdm_x4, 1, limits->max_ofdm_x4); 4720 inc(calib->ofdm_mrc_x4, 1, limits->max_ofdm_mrc_x4); 4721 4722 } else if (fa < 5 * rxena) { 4723 /* Low false alarm count, increase sensitivity. */ 4724 DPRINTF(sc, IWN_DEBUG_CALIBRATE, 4725 "%s: OFDM low false alarm count: %u\n", __func__, fa); 4726 dec(calib->ofdm_x1, 1, limits->min_ofdm_x1); 4727 dec(calib->ofdm_mrc_x1, 1, limits->min_ofdm_mrc_x1); 4728 dec(calib->ofdm_x4, 1, limits->min_ofdm_x4); 4729 dec(calib->ofdm_mrc_x4, 1, limits->min_ofdm_mrc_x4); 4730 } 4731 4732 /* Compute maximum noise among 3 receivers. */ 4733 for (i = 0; i < 3; i++) 4734 noise[i] = (le32toh(stats->general.noise[i]) >> 8) & 0xff; 4735 val = MAX(noise[0], noise[1]); 4736 val = MAX(noise[2], val); 4737 /* Insert it into our samples table. */ 4738 calib->noise_samples[calib->cur_noise_sample] = val; 4739 calib->cur_noise_sample = (calib->cur_noise_sample + 1) % 20; 4740 4741 /* Compute maximum noise among last 20 samples. */ 4742 noise_ref = calib->noise_samples[0]; 4743 for (i = 1; i < 20; i++) 4744 noise_ref = MAX(noise_ref, calib->noise_samples[i]); 4745 4746 /* Compute maximum energy among 3 receivers. */ 4747 for (i = 0; i < 3; i++) 4748 energy[i] = le32toh(stats->general.energy[i]); 4749 val = MIN(energy[0], energy[1]); 4750 val = MIN(energy[2], val); 4751 /* Insert it into our samples table. */ 4752 calib->energy_samples[calib->cur_energy_sample] = val; 4753 calib->cur_energy_sample = (calib->cur_energy_sample + 1) % 10; 4754 4755 /* Compute minimum energy among last 10 samples. */ 4756 energy_min = calib->energy_samples[0]; 4757 for (i = 1; i < 10; i++) 4758 energy_min = MAX(energy_min, calib->energy_samples[i]); 4759 energy_min += 6; 4760 4761 /* Compute number of false alarms since last call for CCK. */ 4762 fa = le32toh(stats->cck.bad_plcp) - calib->bad_plcp_cck; 4763 fa += le32toh(stats->cck.fa) - calib->fa_cck; 4764 fa *= 200 * IEEE80211_DUR_TU; /* 200TU */ 4765 4766 /* Save counters values for next call. */ 4767 calib->bad_plcp_cck = le32toh(stats->cck.bad_plcp); 4768 calib->fa_cck = le32toh(stats->cck.fa); 4769 4770 if (fa > 50 * rxena) { 4771 /* High false alarm count, decrease sensitivity. */ 4772 DPRINTF(sc, IWN_DEBUG_CALIBRATE, 4773 "%s: CCK high false alarm count: %u\n", __func__, fa); 4774 calib->cck_state = IWN_CCK_STATE_HIFA; 4775 calib->low_fa = 0; 4776 4777 if (calib->cck_x4 > 160) { 4778 calib->noise_ref = noise_ref; 4779 if (calib->energy_cck > 2) 4780 dec(calib->energy_cck, 2, energy_min); 4781 } 4782 if (calib->cck_x4 < 160) { 4783 calib->cck_x4 = 161; 4784 needs_update = 1; 4785 } else 4786 inc(calib->cck_x4, 3, limits->max_cck_x4); 4787 4788 inc(calib->cck_mrc_x4, 3, limits->max_cck_mrc_x4); 4789 4790 } else if (fa < 5 * rxena) { 4791 /* Low false alarm count, increase sensitivity. */ 4792 DPRINTF(sc, IWN_DEBUG_CALIBRATE, 4793 "%s: CCK low false alarm count: %u\n", __func__, fa); 4794 calib->cck_state = IWN_CCK_STATE_LOFA; 4795 calib->low_fa++; 4796 4797 if (calib->cck_state != IWN_CCK_STATE_INIT && 4798 (((int32_t)calib->noise_ref - (int32_t)noise_ref) > 2 || 4799 calib->low_fa > 100)) { 4800 inc(calib->energy_cck, 2, limits->min_energy_cck); 4801 dec(calib->cck_x4, 3, limits->min_cck_x4); 4802 dec(calib->cck_mrc_x4, 3, limits->min_cck_mrc_x4); 4803 } 4804 } else { 4805 /* Not worth to increase or decrease sensitivity. */ 4806 DPRINTF(sc, IWN_DEBUG_CALIBRATE, 4807 "%s: CCK normal false alarm count: %u\n", __func__, fa); 4808 calib->low_fa = 0; 4809 calib->noise_ref = noise_ref; 4810 4811 if (calib->cck_state == IWN_CCK_STATE_HIFA) { 4812 /* Previous interval had many false alarms. */ 4813 dec(calib->energy_cck, 8, energy_min); 4814 } 4815 calib->cck_state = IWN_CCK_STATE_INIT; 4816 } 4817 4818 if (needs_update) 4819 (void)iwn_send_sensitivity(sc); 4820 #undef dec 4821 #undef inc 4822 } 4823 4824 static int 4825 iwn_send_sensitivity(struct iwn_softc *sc) 4826 { 4827 struct iwn_calib_state *calib = &sc->calib; 4828 struct iwn_enhanced_sensitivity_cmd cmd; 4829 int len; 4830 4831 memset(&cmd, 0, sizeof cmd); 4832 len = sizeof (struct iwn_sensitivity_cmd); 4833 cmd.which = IWN_SENSITIVITY_WORKTBL; 4834 /* OFDM modulation. */ 4835 cmd.corr_ofdm_x1 = htole16(calib->ofdm_x1); 4836 cmd.corr_ofdm_mrc_x1 = htole16(calib->ofdm_mrc_x1); 4837 cmd.corr_ofdm_x4 = htole16(calib->ofdm_x4); 4838 cmd.corr_ofdm_mrc_x4 = htole16(calib->ofdm_mrc_x4); 4839 cmd.energy_ofdm = htole16(sc->limits->energy_ofdm); 4840 cmd.energy_ofdm_th = htole16(62); 4841 /* CCK modulation. */ 4842 cmd.corr_cck_x4 = htole16(calib->cck_x4); 4843 cmd.corr_cck_mrc_x4 = htole16(calib->cck_mrc_x4); 4844 cmd.energy_cck = htole16(calib->energy_cck); 4845 /* Barker modulation: use default values. */ 4846 cmd.corr_barker = htole16(190); 4847 cmd.corr_barker_mrc = htole16(390); 4848 4849 DPRINTF(sc, IWN_DEBUG_CALIBRATE, 4850 "%s: set sensitivity %d/%d/%d/%d/%d/%d/%d\n", __func__, 4851 calib->ofdm_x1, calib->ofdm_mrc_x1, calib->ofdm_x4, 4852 calib->ofdm_mrc_x4, calib->cck_x4, 4853 calib->cck_mrc_x4, calib->energy_cck); 4854 4855 if (!(sc->sc_flags & IWN_FLAG_ENH_SENS)) 4856 goto send; 4857 /* Enhanced sensitivity settings. */ 4858 len = sizeof (struct iwn_enhanced_sensitivity_cmd); 4859 cmd.ofdm_det_slope_mrc = htole16(668); 4860 cmd.ofdm_det_icept_mrc = htole16(4); 4861 cmd.ofdm_det_slope = htole16(486); 4862 cmd.ofdm_det_icept = htole16(37); 4863 cmd.cck_det_slope_mrc = htole16(853); 4864 cmd.cck_det_icept_mrc = htole16(4); 4865 cmd.cck_det_slope = htole16(476); 4866 cmd.cck_det_icept = htole16(99); 4867 send: 4868 return iwn_cmd(sc, IWN_CMD_SET_SENSITIVITY, &cmd, len, 1); 4869 } 4870 4871 /* 4872 * Set STA mode power saving level (between 0 and 5). 4873 * Level 0 is CAM (Continuously Aware Mode), 5 is for maximum power saving. 4874 */ 4875 static int 4876 iwn_set_pslevel(struct iwn_softc *sc, int dtim, int level, int async) 4877 { 4878 struct iwn_pmgt_cmd cmd; 4879 const struct iwn_pmgt *pmgt; 4880 uint32_t max, skip_dtim; 4881 uint32_t reg; 4882 int i; 4883 4884 /* Select which PS parameters to use. */ 4885 if (dtim <= 2) 4886 pmgt = &iwn_pmgt[0][level]; 4887 else if (dtim <= 10) 4888 pmgt = &iwn_pmgt[1][level]; 4889 else 4890 pmgt = &iwn_pmgt[2][level]; 4891 4892 memset(&cmd, 0, sizeof cmd); 4893 if (level != 0) /* not CAM */ 4894 cmd.flags |= htole16(IWN_PS_ALLOW_SLEEP); 4895 if (level == 5) 4896 cmd.flags |= htole16(IWN_PS_FAST_PD); 4897 /* Retrieve PCIe Active State Power Management (ASPM). */ 4898 reg = pci_read_config(sc->sc_dev, sc->sc_cap_off + 0x10, 1); 4899 if (!(reg & 0x1)) /* L0s Entry disabled. */ 4900 cmd.flags |= htole16(IWN_PS_PCI_PMGT); 4901 cmd.rxtimeout = htole32(pmgt->rxtimeout * 1024); 4902 cmd.txtimeout = htole32(pmgt->txtimeout * 1024); 4903 4904 if (dtim == 0) { 4905 dtim = 1; 4906 skip_dtim = 0; 4907 } else 4908 skip_dtim = pmgt->skip_dtim; 4909 if (skip_dtim != 0) { 4910 cmd.flags |= htole16(IWN_PS_SLEEP_OVER_DTIM); 4911 max = pmgt->intval[4]; 4912 if (max == (uint32_t)-1) 4913 max = dtim * (skip_dtim + 1); 4914 else if (max > dtim) 4915 max = (max / dtim) * dtim; 4916 } else 4917 max = dtim; 4918 for (i = 0; i < 5; i++) 4919 cmd.intval[i] = htole32(MIN(max, pmgt->intval[i])); 4920 4921 DPRINTF(sc, IWN_DEBUG_RESET, "setting power saving level to %d\n", 4922 level); 4923 return iwn_cmd(sc, IWN_CMD_SET_POWER_MODE, &cmd, sizeof cmd, async); 4924 } 4925 4926 static int 4927 iwn_send_btcoex(struct iwn_softc *sc) 4928 { 4929 struct iwn_bluetooth cmd; 4930 4931 memset(&cmd, 0, sizeof cmd); 4932 cmd.flags = IWN_BT_COEX_CHAN_ANN | IWN_BT_COEX_BT_PRIO; 4933 cmd.lead_time = IWN_BT_LEAD_TIME_DEF; 4934 cmd.max_kill = IWN_BT_MAX_KILL_DEF; 4935 DPRINTF(sc, IWN_DEBUG_RESET, "%s: configuring bluetooth coexistence\n", 4936 __func__); 4937 return iwn_cmd(sc, IWN_CMD_BT_COEX, &cmd, sizeof(cmd), 0); 4938 } 4939 4940 static int 4941 iwn_send_advanced_btcoex(struct iwn_softc *sc) 4942 { 4943 static const uint32_t btcoex_3wire[12] = { 4944 0xaaaaaaaa, 0xaaaaaaaa, 0xaeaaaaaa, 0xaaaaaaaa, 4945 0xcc00ff28, 0x0000aaaa, 0xcc00aaaa, 0x0000aaaa, 4946 0xc0004000, 0x00004000, 0xf0005000, 0xf0005000, 4947 }; 4948 struct iwn6000_btcoex_config btconfig; 4949 struct iwn_btcoex_priotable btprio; 4950 struct iwn_btcoex_prot btprot; 4951 int error, i; 4952 4953 memset(&btconfig, 0, sizeof btconfig); 4954 btconfig.flags = 145; 4955 btconfig.max_kill = 5; 4956 btconfig.bt3_t7_timer = 1; 4957 btconfig.kill_ack = htole32(0xffff0000); 4958 btconfig.kill_cts = htole32(0xffff0000); 4959 btconfig.sample_time = 2; 4960 btconfig.bt3_t2_timer = 0xc; 4961 for (i = 0; i < 12; i++) 4962 btconfig.lookup_table[i] = htole32(btcoex_3wire[i]); 4963 btconfig.valid = htole16(0xff); 4964 btconfig.prio_boost = 0xf0; 4965 DPRINTF(sc, IWN_DEBUG_RESET, 4966 "%s: configuring advanced bluetooth coexistence\n", __func__); 4967 error = iwn_cmd(sc, IWN_CMD_BT_COEX, &btconfig, sizeof(btconfig), 1); 4968 if (error != 0) 4969 return error; 4970 4971 memset(&btprio, 0, sizeof btprio); 4972 btprio.calib_init1 = 0x6; 4973 btprio.calib_init2 = 0x7; 4974 btprio.calib_periodic_low1 = 0x2; 4975 btprio.calib_periodic_low2 = 0x3; 4976 btprio.calib_periodic_high1 = 0x4; 4977 btprio.calib_periodic_high2 = 0x5; 4978 btprio.dtim = 0x6; 4979 btprio.scan52 = 0x8; 4980 btprio.scan24 = 0xa; 4981 error = iwn_cmd(sc, IWN_CMD_BT_COEX_PRIOTABLE, &btprio, sizeof(btprio), 4982 1); 4983 if (error != 0) 4984 return error; 4985 4986 /* Force BT state machine change. */ 4987 memset(&btprot, 0, sizeof btprio); 4988 btprot.open = 1; 4989 btprot.type = 1; 4990 error = iwn_cmd(sc, IWN_CMD_BT_COEX_PROT, &btprot, sizeof(btprot), 1); 4991 if (error != 0) 4992 return error; 4993 btprot.open = 0; 4994 return iwn_cmd(sc, IWN_CMD_BT_COEX_PROT, &btprot, sizeof(btprot), 1); 4995 } 4996 4997 static int 4998 iwn_config(struct iwn_softc *sc) 4999 { 5000 struct iwn_ops *ops = &sc->ops; 5001 struct ifnet *ifp = sc->sc_ifp; 5002 struct ieee80211com *ic = ifp->if_l2com; 5003 uint32_t txmask; 5004 uint16_t rxchain; 5005 int error; 5006 5007 if (sc->hw_type == IWN_HW_REV_TYPE_6005) { 5008 /* Set radio temperature sensor offset. */ 5009 error = iwn5000_temp_offset_calib(sc); 5010 if (error != 0) { 5011 device_printf(sc->sc_dev, 5012 "%s: could not set temperature offset\n", __func__); 5013 return error; 5014 } 5015 } 5016 5017 /* Configure valid TX chains for >=5000 Series. */ 5018 if (sc->hw_type != IWN_HW_REV_TYPE_4965) { 5019 txmask = htole32(sc->txchainmask); 5020 DPRINTF(sc, IWN_DEBUG_RESET, 5021 "%s: configuring valid TX chains 0x%x\n", __func__, txmask); 5022 error = iwn_cmd(sc, IWN5000_CMD_TX_ANT_CONFIG, &txmask, 5023 sizeof txmask, 0); 5024 if (error != 0) { 5025 device_printf(sc->sc_dev, 5026 "%s: could not configure valid TX chains, " 5027 "error %d\n", __func__, error); 5028 return error; 5029 } 5030 } 5031 5032 /* Configure bluetooth coexistence. */ 5033 if (sc->sc_flags & IWN_FLAG_ADV_BTCOEX) 5034 error = iwn_send_advanced_btcoex(sc); 5035 else 5036 error = iwn_send_btcoex(sc); 5037 if (error != 0) { 5038 device_printf(sc->sc_dev, 5039 "%s: could not configure bluetooth coexistence, error %d\n", 5040 __func__, error); 5041 return error; 5042 } 5043 5044 /* Set mode, channel, RX filter and enable RX. */ 5045 memset(&sc->rxon, 0, sizeof (struct iwn_rxon)); 5046 IEEE80211_ADDR_COPY(sc->rxon.myaddr, IF_LLADDR(ifp)); 5047 IEEE80211_ADDR_COPY(sc->rxon.wlap, IF_LLADDR(ifp)); 5048 sc->rxon.chan = ieee80211_chan2ieee(ic, ic->ic_curchan); 5049 sc->rxon.flags = htole32(IWN_RXON_TSF | IWN_RXON_CTS_TO_SELF); 5050 if (IEEE80211_IS_CHAN_2GHZ(ic->ic_curchan)) 5051 sc->rxon.flags |= htole32(IWN_RXON_AUTO | IWN_RXON_24GHZ); 5052 switch (ic->ic_opmode) { 5053 case IEEE80211_M_STA: 5054 sc->rxon.mode = IWN_MODE_STA; 5055 sc->rxon.filter = htole32(IWN_FILTER_MULTICAST); 5056 break; 5057 case IEEE80211_M_MONITOR: 5058 sc->rxon.mode = IWN_MODE_MONITOR; 5059 sc->rxon.filter = htole32(IWN_FILTER_MULTICAST | 5060 IWN_FILTER_CTL | IWN_FILTER_PROMISC); 5061 break; 5062 default: 5063 /* Should not get there. */ 5064 break; 5065 } 5066 sc->rxon.cck_mask = 0x0f; /* not yet negotiated */ 5067 sc->rxon.ofdm_mask = 0xff; /* not yet negotiated */ 5068 sc->rxon.ht_single_mask = 0xff; 5069 sc->rxon.ht_dual_mask = 0xff; 5070 sc->rxon.ht_triple_mask = 0xff; 5071 rxchain = 5072 IWN_RXCHAIN_VALID(sc->rxchainmask) | 5073 IWN_RXCHAIN_MIMO_COUNT(2) | 5074 IWN_RXCHAIN_IDLE_COUNT(2); 5075 sc->rxon.rxchain = htole16(rxchain); 5076 DPRINTF(sc, IWN_DEBUG_RESET, "%s: setting configuration\n", __func__); 5077 error = iwn_cmd(sc, IWN_CMD_RXON, &sc->rxon, sc->rxonsz, 0); 5078 if (error != 0) { 5079 device_printf(sc->sc_dev, "%s: RXON command failed\n", 5080 __func__); 5081 return error; 5082 } 5083 5084 if ((error = iwn_add_broadcast_node(sc, 0)) != 0) { 5085 device_printf(sc->sc_dev, "%s: could not add broadcast node\n", 5086 __func__); 5087 return error; 5088 } 5089 5090 /* Configuration has changed, set TX power accordingly. */ 5091 if ((error = ops->set_txpower(sc, ic->ic_curchan, 0)) != 0) { 5092 device_printf(sc->sc_dev, "%s: could not set TX power\n", 5093 __func__); 5094 return error; 5095 } 5096 5097 if ((error = iwn_set_critical_temp(sc)) != 0) { 5098 device_printf(sc->sc_dev, 5099 "%s: could not set critical temperature\n", __func__); 5100 return error; 5101 } 5102 5103 /* Set power saving level to CAM during initialization. */ 5104 if ((error = iwn_set_pslevel(sc, 0, 0, 0)) != 0) { 5105 device_printf(sc->sc_dev, 5106 "%s: could not set power saving level\n", __func__); 5107 return error; 5108 } 5109 return 0; 5110 } 5111 5112 /* 5113 * Add an ssid element to a frame. 5114 */ 5115 static uint8_t * 5116 ieee80211_add_ssid(uint8_t *frm, const uint8_t *ssid, u_int len) 5117 { 5118 *frm++ = IEEE80211_ELEMID_SSID; 5119 *frm++ = len; 5120 memcpy(frm, ssid, len); 5121 return frm + len; 5122 } 5123 5124 static int 5125 iwn_scan(struct iwn_softc *sc) 5126 { 5127 struct ifnet *ifp = sc->sc_ifp; 5128 struct ieee80211com *ic = ifp->if_l2com; 5129 struct ieee80211_scan_state *ss = ic->ic_scan; /*XXX*/ 5130 struct ieee80211_node *ni = ss->ss_vap->iv_bss; 5131 struct iwn_scan_hdr *hdr; 5132 struct iwn_cmd_data *tx; 5133 struct iwn_scan_essid *essid; 5134 struct iwn_scan_chan *chan; 5135 struct ieee80211_frame *wh; 5136 struct ieee80211_rateset *rs; 5137 struct ieee80211_channel *c; 5138 uint8_t *buf, *frm; 5139 uint16_t rxchain; 5140 uint8_t txant; 5141 int buflen, error; 5142 5143 buf = malloc(IWN_SCAN_MAXSZ, M_DEVBUF, M_NOWAIT | M_ZERO); 5144 if (buf == NULL) { 5145 device_printf(sc->sc_dev, 5146 "%s: could not allocate buffer for scan command\n", 5147 __func__); 5148 return ENOMEM; 5149 } 5150 hdr = (struct iwn_scan_hdr *)buf; 5151 /* 5152 * Move to the next channel if no frames are received within 10ms 5153 * after sending the probe request. 5154 */ 5155 hdr->quiet_time = htole16(10); /* timeout in milliseconds */ 5156 hdr->quiet_threshold = htole16(1); /* min # of packets */ 5157 5158 /* Select antennas for scanning. */ 5159 rxchain = 5160 IWN_RXCHAIN_VALID(sc->rxchainmask) | 5161 IWN_RXCHAIN_FORCE_MIMO_SEL(sc->rxchainmask) | 5162 IWN_RXCHAIN_DRIVER_FORCE; 5163 if (IEEE80211_IS_CHAN_A(ic->ic_curchan) && 5164 sc->hw_type == IWN_HW_REV_TYPE_4965) { 5165 /* Ant A must be avoided in 5GHz because of an HW bug. */ 5166 rxchain |= IWN_RXCHAIN_FORCE_SEL(IWN_ANT_B); 5167 } else /* Use all available RX antennas. */ 5168 rxchain |= IWN_RXCHAIN_FORCE_SEL(sc->rxchainmask); 5169 hdr->rxchain = htole16(rxchain); 5170 hdr->filter = htole32(IWN_FILTER_MULTICAST | IWN_FILTER_BEACON); 5171 5172 tx = (struct iwn_cmd_data *)(hdr + 1); 5173 tx->flags = htole32(IWN_TX_AUTO_SEQ); 5174 tx->id = sc->broadcast_id; 5175 tx->lifetime = htole32(IWN_LIFETIME_INFINITE); 5176 5177 if (IEEE80211_IS_CHAN_5GHZ(ic->ic_curchan)) { 5178 /* Send probe requests at 6Mbps. */ 5179 tx->rate = htole32(0xd); 5180 rs = &ic->ic_sup_rates[IEEE80211_MODE_11A]; 5181 } else { 5182 hdr->flags = htole32(IWN_RXON_24GHZ | IWN_RXON_AUTO); 5183 if (sc->hw_type == IWN_HW_REV_TYPE_4965 && 5184 sc->rxon.associd && sc->rxon.chan > 14) 5185 tx->rate = htole32(0xd); 5186 else { 5187 /* Send probe requests at 1Mbps. */ 5188 tx->rate = htole32(10 | IWN_RFLAG_CCK); 5189 } 5190 rs = &ic->ic_sup_rates[IEEE80211_MODE_11G]; 5191 } 5192 /* Use the first valid TX antenna. */ 5193 txant = IWN_LSB(sc->txchainmask); 5194 tx->rate |= htole32(IWN_RFLAG_ANT(txant)); 5195 5196 essid = (struct iwn_scan_essid *)(tx + 1); 5197 if (ss->ss_ssid[0].len != 0) { 5198 essid[0].id = IEEE80211_ELEMID_SSID; 5199 essid[0].len = ss->ss_ssid[0].len; 5200 memcpy(essid[0].data, ss->ss_ssid[0].ssid, ss->ss_ssid[0].len); 5201 } 5202 /* 5203 * Build a probe request frame. Most of the following code is a 5204 * copy & paste of what is done in net80211. 5205 */ 5206 wh = (struct ieee80211_frame *)(essid + 20); 5207 wh->i_fc[0] = IEEE80211_FC0_VERSION_0 | IEEE80211_FC0_TYPE_MGT | 5208 IEEE80211_FC0_SUBTYPE_PROBE_REQ; 5209 wh->i_fc[1] = IEEE80211_FC1_DIR_NODS; 5210 IEEE80211_ADDR_COPY(wh->i_addr1, ifp->if_broadcastaddr); 5211 IEEE80211_ADDR_COPY(wh->i_addr2, IF_LLADDR(ifp)); 5212 IEEE80211_ADDR_COPY(wh->i_addr3, ifp->if_broadcastaddr); 5213 *(uint16_t *)&wh->i_dur[0] = 0; /* filled by HW */ 5214 *(uint16_t *)&wh->i_seq[0] = 0; /* filled by HW */ 5215 5216 frm = (uint8_t *)(wh + 1); 5217 frm = ieee80211_add_ssid(frm, NULL, 0); 5218 frm = ieee80211_add_rates(frm, rs); 5219 if (rs->rs_nrates > IEEE80211_RATE_SIZE) 5220 frm = ieee80211_add_xrates(frm, rs); 5221 if (ic->ic_htcaps & IEEE80211_HTC_HT) 5222 frm = ieee80211_add_htcap(frm, ni); 5223 5224 /* Set length of probe request. */ 5225 tx->len = htole16(frm - (uint8_t *)wh); 5226 5227 c = ic->ic_curchan; 5228 chan = (struct iwn_scan_chan *)frm; 5229 chan->chan = htole16(ieee80211_chan2ieee(ic, c)); 5230 chan->flags = 0; 5231 if (ss->ss_nssid > 0) 5232 chan->flags |= htole32(IWN_CHAN_NPBREQS(1)); 5233 chan->dsp_gain = 0x6e; 5234 if (IEEE80211_IS_CHAN_5GHZ(c) && 5235 !(c->ic_flags & IEEE80211_CHAN_PASSIVE)) { 5236 chan->rf_gain = 0x3b; 5237 chan->active = htole16(24); 5238 chan->passive = htole16(110); 5239 chan->flags |= htole32(IWN_CHAN_ACTIVE); 5240 } else if (IEEE80211_IS_CHAN_5GHZ(c)) { 5241 chan->rf_gain = 0x3b; 5242 chan->active = htole16(24); 5243 if (sc->rxon.associd) 5244 chan->passive = htole16(78); 5245 else 5246 chan->passive = htole16(110); 5247 hdr->crc_threshold = 0xffff; 5248 } else if (!(c->ic_flags & IEEE80211_CHAN_PASSIVE)) { 5249 chan->rf_gain = 0x28; 5250 chan->active = htole16(36); 5251 chan->passive = htole16(120); 5252 chan->flags |= htole32(IWN_CHAN_ACTIVE); 5253 } else { 5254 chan->rf_gain = 0x28; 5255 chan->active = htole16(36); 5256 if (sc->rxon.associd) 5257 chan->passive = htole16(88); 5258 else 5259 chan->passive = htole16(120); 5260 hdr->crc_threshold = 0xffff; 5261 } 5262 5263 DPRINTF(sc, IWN_DEBUG_STATE, 5264 "%s: chan %u flags 0x%x rf_gain 0x%x " 5265 "dsp_gain 0x%x active 0x%x passive 0x%x\n", __func__, 5266 chan->chan, chan->flags, chan->rf_gain, chan->dsp_gain, 5267 chan->active, chan->passive); 5268 5269 hdr->nchan++; 5270 chan++; 5271 buflen = (uint8_t *)chan - buf; 5272 hdr->len = htole16(buflen); 5273 5274 DPRINTF(sc, IWN_DEBUG_STATE, "sending scan command nchan=%d\n", 5275 hdr->nchan); 5276 error = iwn_cmd(sc, IWN_CMD_SCAN, buf, buflen, 1); 5277 free(buf, M_DEVBUF); 5278 return error; 5279 } 5280 5281 static int 5282 iwn_auth(struct iwn_softc *sc, struct ieee80211vap *vap) 5283 { 5284 struct iwn_ops *ops = &sc->ops; 5285 struct ifnet *ifp = sc->sc_ifp; 5286 struct ieee80211com *ic = ifp->if_l2com; 5287 struct ieee80211_node *ni = vap->iv_bss; 5288 int error; 5289 5290 /* Update adapter configuration. */ 5291 IEEE80211_ADDR_COPY(sc->rxon.bssid, ni->ni_bssid); 5292 sc->rxon.chan = ieee80211_chan2ieee(ic, ni->ni_chan); 5293 sc->rxon.flags = htole32(IWN_RXON_TSF | IWN_RXON_CTS_TO_SELF); 5294 if (IEEE80211_IS_CHAN_2GHZ(ni->ni_chan)) 5295 sc->rxon.flags |= htole32(IWN_RXON_AUTO | IWN_RXON_24GHZ); 5296 if (ic->ic_flags & IEEE80211_F_SHSLOT) 5297 sc->rxon.flags |= htole32(IWN_RXON_SHSLOT); 5298 if (ic->ic_flags & IEEE80211_F_SHPREAMBLE) 5299 sc->rxon.flags |= htole32(IWN_RXON_SHPREAMBLE); 5300 if (IEEE80211_IS_CHAN_A(ni->ni_chan)) { 5301 sc->rxon.cck_mask = 0; 5302 sc->rxon.ofdm_mask = 0x15; 5303 } else if (IEEE80211_IS_CHAN_B(ni->ni_chan)) { 5304 sc->rxon.cck_mask = 0x03; 5305 sc->rxon.ofdm_mask = 0; 5306 } else { 5307 /* Assume 802.11b/g. */ 5308 sc->rxon.cck_mask = 0x0f; 5309 sc->rxon.ofdm_mask = 0x15; 5310 } 5311 DPRINTF(sc, IWN_DEBUG_STATE, "rxon chan %d flags %x cck %x ofdm %x\n", 5312 sc->rxon.chan, sc->rxon.flags, sc->rxon.cck_mask, 5313 sc->rxon.ofdm_mask); 5314 error = iwn_cmd(sc, IWN_CMD_RXON, &sc->rxon, sc->rxonsz, 1); 5315 if (error != 0) { 5316 device_printf(sc->sc_dev, "%s: RXON command failed, error %d\n", 5317 __func__, error); 5318 return error; 5319 } 5320 5321 /* Configuration has changed, set TX power accordingly. */ 5322 if ((error = ops->set_txpower(sc, ni->ni_chan, 1)) != 0) { 5323 device_printf(sc->sc_dev, 5324 "%s: could not set TX power, error %d\n", __func__, error); 5325 return error; 5326 } 5327 /* 5328 * Reconfiguring RXON clears the firmware nodes table so we must 5329 * add the broadcast node again. 5330 */ 5331 if ((error = iwn_add_broadcast_node(sc, 1)) != 0) { 5332 device_printf(sc->sc_dev, 5333 "%s: could not add broadcast node, error %d\n", __func__, 5334 error); 5335 return error; 5336 } 5337 return 0; 5338 } 5339 5340 static int 5341 iwn_run(struct iwn_softc *sc, struct ieee80211vap *vap) 5342 { 5343 struct iwn_ops *ops = &sc->ops; 5344 struct ifnet *ifp = sc->sc_ifp; 5345 struct ieee80211com *ic = ifp->if_l2com; 5346 struct ieee80211_node *ni = vap->iv_bss; 5347 struct iwn_node_info node; 5348 uint32_t htflags = 0; 5349 int error; 5350 5351 if (ic->ic_opmode == IEEE80211_M_MONITOR) { 5352 /* Link LED blinks while monitoring. */ 5353 iwn_set_led(sc, IWN_LED_LINK, 5, 5); 5354 return 0; 5355 } 5356 if ((error = iwn_set_timing(sc, ni)) != 0) { 5357 device_printf(sc->sc_dev, 5358 "%s: could not set timing, error %d\n", __func__, error); 5359 return error; 5360 } 5361 5362 /* Update adapter configuration. */ 5363 IEEE80211_ADDR_COPY(sc->rxon.bssid, ni->ni_bssid); 5364 sc->rxon.associd = htole16(IEEE80211_AID(ni->ni_associd)); 5365 sc->rxon.chan = ieee80211_chan2ieee(ic, ni->ni_chan); 5366 sc->rxon.flags = htole32(IWN_RXON_TSF | IWN_RXON_CTS_TO_SELF); 5367 if (IEEE80211_IS_CHAN_2GHZ(ni->ni_chan)) 5368 sc->rxon.flags |= htole32(IWN_RXON_AUTO | IWN_RXON_24GHZ); 5369 if (ic->ic_flags & IEEE80211_F_SHSLOT) 5370 sc->rxon.flags |= htole32(IWN_RXON_SHSLOT); 5371 if (ic->ic_flags & IEEE80211_F_SHPREAMBLE) 5372 sc->rxon.flags |= htole32(IWN_RXON_SHPREAMBLE); 5373 if (IEEE80211_IS_CHAN_A(ni->ni_chan)) { 5374 sc->rxon.cck_mask = 0; 5375 sc->rxon.ofdm_mask = 0x15; 5376 } else if (IEEE80211_IS_CHAN_B(ni->ni_chan)) { 5377 sc->rxon.cck_mask = 0x03; 5378 sc->rxon.ofdm_mask = 0; 5379 } else { 5380 /* Assume 802.11b/g. */ 5381 sc->rxon.cck_mask = 0x0f; 5382 sc->rxon.ofdm_mask = 0x15; 5383 } 5384 if (IEEE80211_IS_CHAN_HT(ni->ni_chan)) { 5385 htflags |= IWN_RXON_HT_PROTMODE(ic->ic_curhtprotmode); 5386 if (IEEE80211_IS_CHAN_HT40(ni->ni_chan)) { 5387 switch (ic->ic_curhtprotmode) { 5388 case IEEE80211_HTINFO_OPMODE_HT20PR: 5389 htflags |= IWN_RXON_HT_MODEPURE40; 5390 break; 5391 default: 5392 htflags |= IWN_RXON_HT_MODEMIXED; 5393 break; 5394 } 5395 } 5396 if (IEEE80211_IS_CHAN_HT40D(ni->ni_chan)) 5397 htflags |= IWN_RXON_HT_HT40MINUS; 5398 } 5399 sc->rxon.flags |= htole32(htflags); 5400 sc->rxon.filter |= htole32(IWN_FILTER_BSS); 5401 DPRINTF(sc, IWN_DEBUG_STATE, "rxon chan %d flags %x\n", 5402 sc->rxon.chan, sc->rxon.flags); 5403 error = iwn_cmd(sc, IWN_CMD_RXON, &sc->rxon, sc->rxonsz, 1); 5404 if (error != 0) { 5405 device_printf(sc->sc_dev, 5406 "%s: could not update configuration, error %d\n", __func__, 5407 error); 5408 return error; 5409 } 5410 5411 /* Configuration has changed, set TX power accordingly. */ 5412 if ((error = ops->set_txpower(sc, ni->ni_chan, 1)) != 0) { 5413 device_printf(sc->sc_dev, 5414 "%s: could not set TX power, error %d\n", __func__, error); 5415 return error; 5416 } 5417 5418 /* Fake a join to initialize the TX rate. */ 5419 ((struct iwn_node *)ni)->id = IWN_ID_BSS; 5420 iwn_newassoc(ni, 1); 5421 5422 /* Add BSS node. */ 5423 memset(&node, 0, sizeof node); 5424 IEEE80211_ADDR_COPY(node.macaddr, ni->ni_macaddr); 5425 node.id = IWN_ID_BSS; 5426 if (IEEE80211_IS_CHAN_HT(ni->ni_chan)) { 5427 switch (ni->ni_htcap & IEEE80211_HTCAP_SMPS) { 5428 case IEEE80211_HTCAP_SMPS_ENA: 5429 node.htflags |= htole32(IWN_SMPS_MIMO_DIS); 5430 break; 5431 case IEEE80211_HTCAP_SMPS_DYNAMIC: 5432 node.htflags |= htole32(IWN_SMPS_MIMO_PROT); 5433 break; 5434 } 5435 node.htflags |= htole32(IWN_AMDPU_SIZE_FACTOR(3) | 5436 IWN_AMDPU_DENSITY(5)); /* 4us */ 5437 if (IEEE80211_IS_CHAN_HT40(ni->ni_chan)) 5438 node.htflags |= htole32(IWN_NODE_HT40); 5439 } 5440 DPRINTF(sc, IWN_DEBUG_STATE, "%s: adding BSS node\n", __func__); 5441 error = ops->add_node(sc, &node, 1); 5442 if (error != 0) { 5443 device_printf(sc->sc_dev, 5444 "%s: could not add BSS node, error %d\n", __func__, error); 5445 return error; 5446 } 5447 DPRINTF(sc, IWN_DEBUG_STATE, "%s: setting link quality for node %d\n", 5448 __func__, node.id); 5449 if ((error = iwn_set_link_quality(sc, ni)) != 0) { 5450 device_printf(sc->sc_dev, 5451 "%s: could not setup link quality for node %d, error %d\n", 5452 __func__, node.id, error); 5453 return error; 5454 } 5455 5456 if ((error = iwn_init_sensitivity(sc)) != 0) { 5457 device_printf(sc->sc_dev, 5458 "%s: could not set sensitivity, error %d\n", __func__, 5459 error); 5460 return error; 5461 } 5462 /* Start periodic calibration timer. */ 5463 sc->calib.state = IWN_CALIB_STATE_ASSOC; 5464 sc->calib_cnt = 0; 5465 callout_reset(&sc->calib_to, msecs_to_ticks(500), iwn_calib_timeout, 5466 sc); 5467 5468 /* Link LED always on while associated. */ 5469 iwn_set_led(sc, IWN_LED_LINK, 0, 1); 5470 return 0; 5471 } 5472 5473 /* 5474 * This function is called by upper layer when an ADDBA request is received 5475 * from another STA and before the ADDBA response is sent. 5476 */ 5477 static int 5478 iwn_ampdu_rx_start(struct ieee80211_node *ni, struct ieee80211_rx_ampdu *rap, 5479 int baparamset, int batimeout, int baseqctl) 5480 { 5481 #define MS(_v, _f) (((_v) & _f) >> _f##_S) 5482 struct iwn_softc *sc = ni->ni_ic->ic_ifp->if_softc; 5483 struct iwn_ops *ops = &sc->ops; 5484 struct iwn_node *wn = (void *)ni; 5485 struct iwn_node_info node; 5486 uint16_t ssn; 5487 uint8_t tid; 5488 int error; 5489 5490 tid = MS(le16toh(baparamset), IEEE80211_BAPS_TID); 5491 ssn = MS(le16toh(baseqctl), IEEE80211_BASEQ_START); 5492 5493 memset(&node, 0, sizeof node); 5494 node.id = wn->id; 5495 node.control = IWN_NODE_UPDATE; 5496 node.flags = IWN_FLAG_SET_ADDBA; 5497 node.addba_tid = tid; 5498 node.addba_ssn = htole16(ssn); 5499 DPRINTF(sc, IWN_DEBUG_RECV, "ADDBA RA=%d TID=%d SSN=%d\n", 5500 wn->id, tid, ssn); 5501 error = ops->add_node(sc, &node, 1); 5502 if (error != 0) 5503 return error; 5504 return sc->sc_ampdu_rx_start(ni, rap, baparamset, batimeout, baseqctl); 5505 #undef MS 5506 } 5507 5508 /* 5509 * This function is called by upper layer on teardown of an HT-immediate 5510 * Block Ack agreement (eg. uppon receipt of a DELBA frame). 5511 */ 5512 static void 5513 iwn_ampdu_rx_stop(struct ieee80211_node *ni, struct ieee80211_rx_ampdu *rap) 5514 { 5515 struct ieee80211com *ic = ni->ni_ic; 5516 struct iwn_softc *sc = ic->ic_ifp->if_softc; 5517 struct iwn_ops *ops = &sc->ops; 5518 struct iwn_node *wn = (void *)ni; 5519 struct iwn_node_info node; 5520 uint8_t tid; 5521 5522 /* XXX: tid as an argument */ 5523 for (tid = 0; tid < WME_NUM_TID; tid++) { 5524 if (&ni->ni_rx_ampdu[tid] == rap) 5525 break; 5526 } 5527 5528 memset(&node, 0, sizeof node); 5529 node.id = wn->id; 5530 node.control = IWN_NODE_UPDATE; 5531 node.flags = IWN_FLAG_SET_DELBA; 5532 node.delba_tid = tid; 5533 DPRINTF(sc, IWN_DEBUG_RECV, "DELBA RA=%d TID=%d\n", wn->id, tid); 5534 (void)ops->add_node(sc, &node, 1); 5535 sc->sc_ampdu_rx_stop(ni, rap); 5536 } 5537 5538 static int 5539 iwn_addba_request(struct ieee80211_node *ni, struct ieee80211_tx_ampdu *tap, 5540 int dialogtoken, int baparamset, int batimeout) 5541 { 5542 struct iwn_softc *sc = ni->ni_ic->ic_ifp->if_softc; 5543 int qid; 5544 5545 for (qid = sc->firstaggqueue; qid < sc->ntxqs; qid++) { 5546 if (sc->qid2tap[qid] == NULL) 5547 break; 5548 } 5549 if (qid == sc->ntxqs) { 5550 DPRINTF(sc, IWN_DEBUG_XMIT, "%s: not free aggregation queue\n", 5551 __func__); 5552 return 0; 5553 } 5554 tap->txa_private = malloc(sizeof(int), M_DEVBUF, M_NOWAIT); 5555 if (tap->txa_private == NULL) { 5556 device_printf(sc->sc_dev, 5557 "%s: failed to alloc TX aggregation structure\n", __func__); 5558 return 0; 5559 } 5560 sc->qid2tap[qid] = tap; 5561 *(int *)tap->txa_private = qid; 5562 return sc->sc_addba_request(ni, tap, dialogtoken, baparamset, 5563 batimeout); 5564 } 5565 5566 static int 5567 iwn_addba_response(struct ieee80211_node *ni, struct ieee80211_tx_ampdu *tap, 5568 int code, int baparamset, int batimeout) 5569 { 5570 struct iwn_softc *sc = ni->ni_ic->ic_ifp->if_softc; 5571 int qid = *(int *)tap->txa_private; 5572 uint8_t tid = WME_AC_TO_TID(tap->txa_ac); 5573 int ret; 5574 5575 if (code == IEEE80211_STATUS_SUCCESS) { 5576 ni->ni_txseqs[tid] = tap->txa_start & 0xfff; 5577 ret = iwn_ampdu_tx_start(ni->ni_ic, ni, tid); 5578 if (ret != 1) 5579 return ret; 5580 } else { 5581 sc->qid2tap[qid] = NULL; 5582 free(tap->txa_private, M_DEVBUF); 5583 tap->txa_private = NULL; 5584 } 5585 return sc->sc_addba_response(ni, tap, code, baparamset, batimeout); 5586 } 5587 5588 /* 5589 * This function is called by upper layer when an ADDBA response is received 5590 * from another STA. 5591 */ 5592 static int 5593 iwn_ampdu_tx_start(struct ieee80211com *ic, struct ieee80211_node *ni, 5594 uint8_t tid) 5595 { 5596 struct ieee80211_tx_ampdu *tap = &ni->ni_tx_ampdu[TID_TO_WME_AC(tid)]; 5597 struct iwn_softc *sc = ni->ni_ic->ic_ifp->if_softc; 5598 struct iwn_ops *ops = &sc->ops; 5599 struct iwn_node *wn = (void *)ni; 5600 struct iwn_node_info node; 5601 int error, qid; 5602 5603 /* Enable TX for the specified RA/TID. */ 5604 wn->disable_tid &= ~(1 << tid); 5605 memset(&node, 0, sizeof node); 5606 node.id = wn->id; 5607 node.control = IWN_NODE_UPDATE; 5608 node.flags = IWN_FLAG_SET_DISABLE_TID; 5609 node.disable_tid = htole16(wn->disable_tid); 5610 error = ops->add_node(sc, &node, 1); 5611 if (error != 0) 5612 return 0; 5613 5614 if ((error = iwn_nic_lock(sc)) != 0) 5615 return 0; 5616 qid = *(int *)tap->txa_private; 5617 ops->ampdu_tx_start(sc, ni, qid, tid, tap->txa_start & 0xfff); 5618 iwn_nic_unlock(sc); 5619 5620 iwn_set_link_quality(sc, ni); 5621 return 1; 5622 } 5623 5624 static void 5625 iwn_ampdu_tx_stop(struct ieee80211_node *ni, struct ieee80211_tx_ampdu *tap) 5626 { 5627 struct iwn_softc *sc = ni->ni_ic->ic_ifp->if_softc; 5628 struct iwn_ops *ops = &sc->ops; 5629 uint8_t tid = WME_AC_TO_TID(tap->txa_ac); 5630 int qid; 5631 5632 if (tap->txa_private == NULL) 5633 return; 5634 5635 qid = *(int *)tap->txa_private; 5636 if (iwn_nic_lock(sc) != 0) 5637 return; 5638 ops->ampdu_tx_stop(sc, qid, tid, tap->txa_start & 0xfff); 5639 iwn_nic_unlock(sc); 5640 sc->qid2tap[qid] = NULL; 5641 free(tap->txa_private, M_DEVBUF); 5642 tap->txa_private = NULL; 5643 } 5644 5645 static void 5646 iwn4965_ampdu_tx_start(struct iwn_softc *sc, struct ieee80211_node *ni, 5647 int qid, uint8_t tid, uint16_t ssn) 5648 { 5649 struct iwn_node *wn = (void *)ni; 5650 5651 /* Stop TX scheduler while we're changing its configuration. */ 5652 iwn_prph_write(sc, IWN4965_SCHED_QUEUE_STATUS(qid), 5653 IWN4965_TXQ_STATUS_CHGACT); 5654 5655 /* Assign RA/TID translation to the queue. */ 5656 iwn_mem_write_2(sc, sc->sched_base + IWN4965_SCHED_TRANS_TBL(qid), 5657 wn->id << 4 | tid); 5658 5659 /* Enable chain-building mode for the queue. */ 5660 iwn_prph_setbits(sc, IWN4965_SCHED_QCHAIN_SEL, 1 << qid); 5661 5662 /* Set starting sequence number from the ADDBA request. */ 5663 sc->txq[qid].cur = sc->txq[qid].read = (ssn & 0xff); 5664 IWN_WRITE(sc, IWN_HBUS_TARG_WRPTR, qid << 8 | (ssn & 0xff)); 5665 iwn_prph_write(sc, IWN4965_SCHED_QUEUE_RDPTR(qid), ssn); 5666 5667 /* Set scheduler window size. */ 5668 iwn_mem_write(sc, sc->sched_base + IWN4965_SCHED_QUEUE_OFFSET(qid), 5669 IWN_SCHED_WINSZ); 5670 /* Set scheduler frame limit. */ 5671 iwn_mem_write(sc, sc->sched_base + IWN4965_SCHED_QUEUE_OFFSET(qid) + 4, 5672 IWN_SCHED_LIMIT << 16); 5673 5674 /* Enable interrupts for the queue. */ 5675 iwn_prph_setbits(sc, IWN4965_SCHED_INTR_MASK, 1 << qid); 5676 5677 /* Mark the queue as active. */ 5678 iwn_prph_write(sc, IWN4965_SCHED_QUEUE_STATUS(qid), 5679 IWN4965_TXQ_STATUS_ACTIVE | IWN4965_TXQ_STATUS_AGGR_ENA | 5680 iwn_tid2fifo[tid] << 1); 5681 } 5682 5683 static void 5684 iwn4965_ampdu_tx_stop(struct iwn_softc *sc, int qid, uint8_t tid, uint16_t ssn) 5685 { 5686 /* Stop TX scheduler while we're changing its configuration. */ 5687 iwn_prph_write(sc, IWN4965_SCHED_QUEUE_STATUS(qid), 5688 IWN4965_TXQ_STATUS_CHGACT); 5689 5690 /* Set starting sequence number from the ADDBA request. */ 5691 IWN_WRITE(sc, IWN_HBUS_TARG_WRPTR, qid << 8 | (ssn & 0xff)); 5692 iwn_prph_write(sc, IWN4965_SCHED_QUEUE_RDPTR(qid), ssn); 5693 5694 /* Disable interrupts for the queue. */ 5695 iwn_prph_clrbits(sc, IWN4965_SCHED_INTR_MASK, 1 << qid); 5696 5697 /* Mark the queue as inactive. */ 5698 iwn_prph_write(sc, IWN4965_SCHED_QUEUE_STATUS(qid), 5699 IWN4965_TXQ_STATUS_INACTIVE | iwn_tid2fifo[tid] << 1); 5700 } 5701 5702 static void 5703 iwn5000_ampdu_tx_start(struct iwn_softc *sc, struct ieee80211_node *ni, 5704 int qid, uint8_t tid, uint16_t ssn) 5705 { 5706 struct iwn_node *wn = (void *)ni; 5707 5708 /* Stop TX scheduler while we're changing its configuration. */ 5709 iwn_prph_write(sc, IWN5000_SCHED_QUEUE_STATUS(qid), 5710 IWN5000_TXQ_STATUS_CHGACT); 5711 5712 /* Assign RA/TID translation to the queue. */ 5713 iwn_mem_write_2(sc, sc->sched_base + IWN5000_SCHED_TRANS_TBL(qid), 5714 wn->id << 4 | tid); 5715 5716 /* Enable chain-building mode for the queue. */ 5717 iwn_prph_setbits(sc, IWN5000_SCHED_QCHAIN_SEL, 1 << qid); 5718 5719 /* Enable aggregation for the queue. */ 5720 iwn_prph_setbits(sc, IWN5000_SCHED_AGGR_SEL, 1 << qid); 5721 5722 /* Set starting sequence number from the ADDBA request. */ 5723 sc->txq[qid].cur = sc->txq[qid].read = (ssn & 0xff); 5724 IWN_WRITE(sc, IWN_HBUS_TARG_WRPTR, qid << 8 | (ssn & 0xff)); 5725 iwn_prph_write(sc, IWN5000_SCHED_QUEUE_RDPTR(qid), ssn); 5726 5727 /* Set scheduler window size and frame limit. */ 5728 iwn_mem_write(sc, sc->sched_base + IWN5000_SCHED_QUEUE_OFFSET(qid) + 4, 5729 IWN_SCHED_LIMIT << 16 | IWN_SCHED_WINSZ); 5730 5731 /* Enable interrupts for the queue. */ 5732 iwn_prph_setbits(sc, IWN5000_SCHED_INTR_MASK, 1 << qid); 5733 5734 /* Mark the queue as active. */ 5735 iwn_prph_write(sc, IWN5000_SCHED_QUEUE_STATUS(qid), 5736 IWN5000_TXQ_STATUS_ACTIVE | iwn_tid2fifo[tid]); 5737 } 5738 5739 static void 5740 iwn5000_ampdu_tx_stop(struct iwn_softc *sc, int qid, uint8_t tid, uint16_t ssn) 5741 { 5742 /* Stop TX scheduler while we're changing its configuration. */ 5743 iwn_prph_write(sc, IWN5000_SCHED_QUEUE_STATUS(qid), 5744 IWN5000_TXQ_STATUS_CHGACT); 5745 5746 /* Disable aggregation for the queue. */ 5747 iwn_prph_clrbits(sc, IWN5000_SCHED_AGGR_SEL, 1 << qid); 5748 5749 /* Set starting sequence number from the ADDBA request. */ 5750 IWN_WRITE(sc, IWN_HBUS_TARG_WRPTR, qid << 8 | (ssn & 0xff)); 5751 iwn_prph_write(sc, IWN5000_SCHED_QUEUE_RDPTR(qid), ssn); 5752 5753 /* Disable interrupts for the queue. */ 5754 iwn_prph_clrbits(sc, IWN5000_SCHED_INTR_MASK, 1 << qid); 5755 5756 /* Mark the queue as inactive. */ 5757 iwn_prph_write(sc, IWN5000_SCHED_QUEUE_STATUS(qid), 5758 IWN5000_TXQ_STATUS_INACTIVE | iwn_tid2fifo[tid]); 5759 } 5760 5761 /* 5762 * Query calibration tables from the initialization firmware. We do this 5763 * only once at first boot. Called from a process context. 5764 */ 5765 static int 5766 iwn5000_query_calibration(struct iwn_softc *sc) 5767 { 5768 struct iwn5000_calib_config cmd; 5769 int error; 5770 5771 memset(&cmd, 0, sizeof cmd); 5772 cmd.ucode.once.enable = 0xffffffff; 5773 cmd.ucode.once.start = 0xffffffff; 5774 cmd.ucode.once.send = 0xffffffff; 5775 cmd.ucode.flags = 0xffffffff; 5776 DPRINTF(sc, IWN_DEBUG_CALIBRATE, "%s: sending calibration query\n", 5777 __func__); 5778 error = iwn_cmd(sc, IWN5000_CMD_CALIB_CONFIG, &cmd, sizeof cmd, 0); 5779 if (error != 0) 5780 return error; 5781 5782 /* Wait at most two seconds for calibration to complete. */ 5783 if (!(sc->sc_flags & IWN_FLAG_CALIB_DONE)) 5784 error = msleep(sc, &sc->sc_mtx, PCATCH, "iwncal", 2 * hz); 5785 return error; 5786 } 5787 5788 /* 5789 * Send calibration results to the runtime firmware. These results were 5790 * obtained on first boot from the initialization firmware. 5791 */ 5792 static int 5793 iwn5000_send_calibration(struct iwn_softc *sc) 5794 { 5795 int idx, error; 5796 5797 for (idx = 0; idx < 5; idx++) { 5798 if (sc->calibcmd[idx].buf == NULL) 5799 continue; /* No results available. */ 5800 DPRINTF(sc, IWN_DEBUG_CALIBRATE, 5801 "send calibration result idx=%d len=%d\n", idx, 5802 sc->calibcmd[idx].len); 5803 error = iwn_cmd(sc, IWN_CMD_PHY_CALIB, sc->calibcmd[idx].buf, 5804 sc->calibcmd[idx].len, 0); 5805 if (error != 0) { 5806 device_printf(sc->sc_dev, 5807 "%s: could not send calibration result, error %d\n", 5808 __func__, error); 5809 return error; 5810 } 5811 } 5812 return 0; 5813 } 5814 5815 static int 5816 iwn5000_send_wimax_coex(struct iwn_softc *sc) 5817 { 5818 struct iwn5000_wimax_coex wimax; 5819 5820 #ifdef notyet 5821 if (sc->hw_type == IWN_HW_REV_TYPE_6050) { 5822 /* Enable WiMAX coexistence for combo adapters. */ 5823 wimax.flags = 5824 IWN_WIMAX_COEX_ASSOC_WA_UNMASK | 5825 IWN_WIMAX_COEX_UNASSOC_WA_UNMASK | 5826 IWN_WIMAX_COEX_STA_TABLE_VALID | 5827 IWN_WIMAX_COEX_ENABLE; 5828 memcpy(wimax.events, iwn6050_wimax_events, 5829 sizeof iwn6050_wimax_events); 5830 } else 5831 #endif 5832 { 5833 /* Disable WiMAX coexistence. */ 5834 wimax.flags = 0; 5835 memset(wimax.events, 0, sizeof wimax.events); 5836 } 5837 DPRINTF(sc, IWN_DEBUG_RESET, "%s: Configuring WiMAX coexistence\n", 5838 __func__); 5839 return iwn_cmd(sc, IWN5000_CMD_WIMAX_COEX, &wimax, sizeof wimax, 0); 5840 } 5841 5842 static int 5843 iwn5000_crystal_calib(struct iwn_softc *sc) 5844 { 5845 struct iwn5000_phy_calib_crystal cmd; 5846 5847 memset(&cmd, 0, sizeof cmd); 5848 cmd.code = IWN5000_PHY_CALIB_CRYSTAL; 5849 cmd.ngroups = 1; 5850 cmd.isvalid = 1; 5851 cmd.cap_pin[0] = le32toh(sc->eeprom_crystal) & 0xff; 5852 cmd.cap_pin[1] = (le32toh(sc->eeprom_crystal) >> 16) & 0xff; 5853 DPRINTF(sc, IWN_DEBUG_CALIBRATE, "sending crystal calibration %d, %d\n", 5854 cmd.cap_pin[0], cmd.cap_pin[1]); 5855 return iwn_cmd(sc, IWN_CMD_PHY_CALIB, &cmd, sizeof cmd, 0); 5856 } 5857 5858 static int 5859 iwn5000_temp_offset_calib(struct iwn_softc *sc) 5860 { 5861 struct iwn5000_phy_calib_temp_offset cmd; 5862 5863 memset(&cmd, 0, sizeof cmd); 5864 cmd.code = IWN5000_PHY_CALIB_TEMP_OFFSET; 5865 cmd.ngroups = 1; 5866 cmd.isvalid = 1; 5867 if (sc->eeprom_temp != 0) 5868 cmd.offset = htole16(sc->eeprom_temp); 5869 else 5870 cmd.offset = htole16(IWN_DEFAULT_TEMP_OFFSET); 5871 DPRINTF(sc, IWN_DEBUG_CALIBRATE, "setting radio sensor offset to %d\n", 5872 le16toh(cmd.offset)); 5873 return iwn_cmd(sc, IWN_CMD_PHY_CALIB, &cmd, sizeof cmd, 0); 5874 } 5875 5876 /* 5877 * This function is called after the runtime firmware notifies us of its 5878 * readiness (called in a process context). 5879 */ 5880 static int 5881 iwn4965_post_alive(struct iwn_softc *sc) 5882 { 5883 int error, qid; 5884 5885 if ((error = iwn_nic_lock(sc)) != 0) 5886 return error; 5887 5888 /* Clear TX scheduler state in SRAM. */ 5889 sc->sched_base = iwn_prph_read(sc, IWN_SCHED_SRAM_ADDR); 5890 iwn_mem_set_region_4(sc, sc->sched_base + IWN4965_SCHED_CTX_OFF, 0, 5891 IWN4965_SCHED_CTX_LEN / sizeof (uint32_t)); 5892 5893 /* Set physical address of TX scheduler rings (1KB aligned). */ 5894 iwn_prph_write(sc, IWN4965_SCHED_DRAM_ADDR, sc->sched_dma.paddr >> 10); 5895 5896 IWN_SETBITS(sc, IWN_FH_TX_CHICKEN, IWN_FH_TX_CHICKEN_SCHED_RETRY); 5897 5898 /* Disable chain mode for all our 16 queues. */ 5899 iwn_prph_write(sc, IWN4965_SCHED_QCHAIN_SEL, 0); 5900 5901 for (qid = 0; qid < IWN4965_NTXQUEUES; qid++) { 5902 iwn_prph_write(sc, IWN4965_SCHED_QUEUE_RDPTR(qid), 0); 5903 IWN_WRITE(sc, IWN_HBUS_TARG_WRPTR, qid << 8 | 0); 5904 5905 /* Set scheduler window size. */ 5906 iwn_mem_write(sc, sc->sched_base + 5907 IWN4965_SCHED_QUEUE_OFFSET(qid), IWN_SCHED_WINSZ); 5908 /* Set scheduler frame limit. */ 5909 iwn_mem_write(sc, sc->sched_base + 5910 IWN4965_SCHED_QUEUE_OFFSET(qid) + 4, 5911 IWN_SCHED_LIMIT << 16); 5912 } 5913 5914 /* Enable interrupts for all our 16 queues. */ 5915 iwn_prph_write(sc, IWN4965_SCHED_INTR_MASK, 0xffff); 5916 /* Identify TX FIFO rings (0-7). */ 5917 iwn_prph_write(sc, IWN4965_SCHED_TXFACT, 0xff); 5918 5919 /* Mark TX rings (4 EDCA + cmd + 2 HCCA) as active. */ 5920 for (qid = 0; qid < 7; qid++) { 5921 static uint8_t qid2fifo[] = { 3, 2, 1, 0, 4, 5, 6 }; 5922 iwn_prph_write(sc, IWN4965_SCHED_QUEUE_STATUS(qid), 5923 IWN4965_TXQ_STATUS_ACTIVE | qid2fifo[qid] << 1); 5924 } 5925 iwn_nic_unlock(sc); 5926 return 0; 5927 } 5928 5929 /* 5930 * This function is called after the initialization or runtime firmware 5931 * notifies us of its readiness (called in a process context). 5932 */ 5933 static int 5934 iwn5000_post_alive(struct iwn_softc *sc) 5935 { 5936 int error, qid; 5937 5938 /* Switch to using ICT interrupt mode. */ 5939 iwn5000_ict_reset(sc); 5940 5941 if ((error = iwn_nic_lock(sc)) != 0) 5942 return error; 5943 5944 /* Clear TX scheduler state in SRAM. */ 5945 sc->sched_base = iwn_prph_read(sc, IWN_SCHED_SRAM_ADDR); 5946 iwn_mem_set_region_4(sc, sc->sched_base + IWN5000_SCHED_CTX_OFF, 0, 5947 IWN5000_SCHED_CTX_LEN / sizeof (uint32_t)); 5948 5949 /* Set physical address of TX scheduler rings (1KB aligned). */ 5950 iwn_prph_write(sc, IWN5000_SCHED_DRAM_ADDR, sc->sched_dma.paddr >> 10); 5951 5952 IWN_SETBITS(sc, IWN_FH_TX_CHICKEN, IWN_FH_TX_CHICKEN_SCHED_RETRY); 5953 5954 /* Enable chain mode for all queues, except command queue. */ 5955 iwn_prph_write(sc, IWN5000_SCHED_QCHAIN_SEL, 0xfffef); 5956 iwn_prph_write(sc, IWN5000_SCHED_AGGR_SEL, 0); 5957 5958 for (qid = 0; qid < IWN5000_NTXQUEUES; qid++) { 5959 iwn_prph_write(sc, IWN5000_SCHED_QUEUE_RDPTR(qid), 0); 5960 IWN_WRITE(sc, IWN_HBUS_TARG_WRPTR, qid << 8 | 0); 5961 5962 iwn_mem_write(sc, sc->sched_base + 5963 IWN5000_SCHED_QUEUE_OFFSET(qid), 0); 5964 /* Set scheduler window size and frame limit. */ 5965 iwn_mem_write(sc, sc->sched_base + 5966 IWN5000_SCHED_QUEUE_OFFSET(qid) + 4, 5967 IWN_SCHED_LIMIT << 16 | IWN_SCHED_WINSZ); 5968 } 5969 5970 /* Enable interrupts for all our 20 queues. */ 5971 iwn_prph_write(sc, IWN5000_SCHED_INTR_MASK, 0xfffff); 5972 /* Identify TX FIFO rings (0-7). */ 5973 iwn_prph_write(sc, IWN5000_SCHED_TXFACT, 0xff); 5974 5975 /* Mark TX rings (4 EDCA + cmd + 2 HCCA) as active. */ 5976 for (qid = 0; qid < 7; qid++) { 5977 static uint8_t qid2fifo[] = { 3, 2, 1, 0, 7, 5, 6 }; 5978 iwn_prph_write(sc, IWN5000_SCHED_QUEUE_STATUS(qid), 5979 IWN5000_TXQ_STATUS_ACTIVE | qid2fifo[qid]); 5980 } 5981 iwn_nic_unlock(sc); 5982 5983 /* Configure WiMAX coexistence for combo adapters. */ 5984 error = iwn5000_send_wimax_coex(sc); 5985 if (error != 0) { 5986 device_printf(sc->sc_dev, 5987 "%s: could not configure WiMAX coexistence, error %d\n", 5988 __func__, error); 5989 return error; 5990 } 5991 if (sc->hw_type != IWN_HW_REV_TYPE_5150) { 5992 /* Perform crystal calibration. */ 5993 error = iwn5000_crystal_calib(sc); 5994 if (error != 0) { 5995 device_printf(sc->sc_dev, 5996 "%s: crystal calibration failed, error %d\n", 5997 __func__, error); 5998 return error; 5999 } 6000 } 6001 if (!(sc->sc_flags & IWN_FLAG_CALIB_DONE)) { 6002 /* Query calibration from the initialization firmware. */ 6003 if ((error = iwn5000_query_calibration(sc)) != 0) { 6004 device_printf(sc->sc_dev, 6005 "%s: could not query calibration, error %d\n", 6006 __func__, error); 6007 return error; 6008 } 6009 /* 6010 * We have the calibration results now, reboot with the 6011 * runtime firmware (call ourselves recursively!) 6012 */ 6013 iwn_hw_stop(sc); 6014 error = iwn_hw_init(sc); 6015 } else { 6016 /* Send calibration results to runtime firmware. */ 6017 error = iwn5000_send_calibration(sc); 6018 } 6019 return error; 6020 } 6021 6022 /* 6023 * The firmware boot code is small and is intended to be copied directly into 6024 * the NIC internal memory (no DMA transfer). 6025 */ 6026 static int 6027 iwn4965_load_bootcode(struct iwn_softc *sc, const uint8_t *ucode, int size) 6028 { 6029 int error, ntries; 6030 6031 size /= sizeof (uint32_t); 6032 6033 if ((error = iwn_nic_lock(sc)) != 0) 6034 return error; 6035 6036 /* Copy microcode image into NIC memory. */ 6037 iwn_prph_write_region_4(sc, IWN_BSM_SRAM_BASE, 6038 (const uint32_t *)ucode, size); 6039 6040 iwn_prph_write(sc, IWN_BSM_WR_MEM_SRC, 0); 6041 iwn_prph_write(sc, IWN_BSM_WR_MEM_DST, IWN_FW_TEXT_BASE); 6042 iwn_prph_write(sc, IWN_BSM_WR_DWCOUNT, size); 6043 6044 /* Start boot load now. */ 6045 iwn_prph_write(sc, IWN_BSM_WR_CTRL, IWN_BSM_WR_CTRL_START); 6046 6047 /* Wait for transfer to complete. */ 6048 for (ntries = 0; ntries < 1000; ntries++) { 6049 if (!(iwn_prph_read(sc, IWN_BSM_WR_CTRL) & 6050 IWN_BSM_WR_CTRL_START)) 6051 break; 6052 DELAY(10); 6053 } 6054 if (ntries == 1000) { 6055 device_printf(sc->sc_dev, "%s: could not load boot firmware\n", 6056 __func__); 6057 iwn_nic_unlock(sc); 6058 return ETIMEDOUT; 6059 } 6060 6061 /* Enable boot after power up. */ 6062 iwn_prph_write(sc, IWN_BSM_WR_CTRL, IWN_BSM_WR_CTRL_START_EN); 6063 6064 iwn_nic_unlock(sc); 6065 return 0; 6066 } 6067 6068 static int 6069 iwn4965_load_firmware(struct iwn_softc *sc) 6070 { 6071 struct iwn_fw_info *fw = &sc->fw; 6072 struct iwn_dma_info *dma = &sc->fw_dma; 6073 int error; 6074 6075 /* Copy initialization sections into pre-allocated DMA-safe memory. */ 6076 memcpy(dma->vaddr, fw->init.data, fw->init.datasz); 6077 bus_dmamap_sync(dma->tag, dma->map, BUS_DMASYNC_PREWRITE); 6078 memcpy(dma->vaddr + IWN4965_FW_DATA_MAXSZ, 6079 fw->init.text, fw->init.textsz); 6080 bus_dmamap_sync(dma->tag, dma->map, BUS_DMASYNC_PREWRITE); 6081 6082 /* Tell adapter where to find initialization sections. */ 6083 if ((error = iwn_nic_lock(sc)) != 0) 6084 return error; 6085 iwn_prph_write(sc, IWN_BSM_DRAM_DATA_ADDR, dma->paddr >> 4); 6086 iwn_prph_write(sc, IWN_BSM_DRAM_DATA_SIZE, fw->init.datasz); 6087 iwn_prph_write(sc, IWN_BSM_DRAM_TEXT_ADDR, 6088 (dma->paddr + IWN4965_FW_DATA_MAXSZ) >> 4); 6089 iwn_prph_write(sc, IWN_BSM_DRAM_TEXT_SIZE, fw->init.textsz); 6090 iwn_nic_unlock(sc); 6091 6092 /* Load firmware boot code. */ 6093 error = iwn4965_load_bootcode(sc, fw->boot.text, fw->boot.textsz); 6094 if (error != 0) { 6095 device_printf(sc->sc_dev, "%s: could not load boot firmware\n", 6096 __func__); 6097 return error; 6098 } 6099 /* Now press "execute". */ 6100 IWN_WRITE(sc, IWN_RESET, 0); 6101 6102 /* Wait at most one second for first alive notification. */ 6103 if ((error = msleep(sc, &sc->sc_mtx, PCATCH, "iwninit", hz)) != 0) { 6104 device_printf(sc->sc_dev, 6105 "%s: timeout waiting for adapter to initialize, error %d\n", 6106 __func__, error); 6107 return error; 6108 } 6109 6110 /* Retrieve current temperature for initial TX power calibration. */ 6111 sc->rawtemp = sc->ucode_info.temp[3].chan20MHz; 6112 sc->temp = iwn4965_get_temperature(sc); 6113 6114 /* Copy runtime sections into pre-allocated DMA-safe memory. */ 6115 memcpy(dma->vaddr, fw->main.data, fw->main.datasz); 6116 bus_dmamap_sync(dma->tag, dma->map, BUS_DMASYNC_PREWRITE); 6117 memcpy(dma->vaddr + IWN4965_FW_DATA_MAXSZ, 6118 fw->main.text, fw->main.textsz); 6119 bus_dmamap_sync(dma->tag, dma->map, BUS_DMASYNC_PREWRITE); 6120 6121 /* Tell adapter where to find runtime sections. */ 6122 if ((error = iwn_nic_lock(sc)) != 0) 6123 return error; 6124 iwn_prph_write(sc, IWN_BSM_DRAM_DATA_ADDR, dma->paddr >> 4); 6125 iwn_prph_write(sc, IWN_BSM_DRAM_DATA_SIZE, fw->main.datasz); 6126 iwn_prph_write(sc, IWN_BSM_DRAM_TEXT_ADDR, 6127 (dma->paddr + IWN4965_FW_DATA_MAXSZ) >> 4); 6128 iwn_prph_write(sc, IWN_BSM_DRAM_TEXT_SIZE, 6129 IWN_FW_UPDATED | fw->main.textsz); 6130 iwn_nic_unlock(sc); 6131 6132 return 0; 6133 } 6134 6135 static int 6136 iwn5000_load_firmware_section(struct iwn_softc *sc, uint32_t dst, 6137 const uint8_t *section, int size) 6138 { 6139 struct iwn_dma_info *dma = &sc->fw_dma; 6140 int error; 6141 6142 /* Copy firmware section into pre-allocated DMA-safe memory. */ 6143 memcpy(dma->vaddr, section, size); 6144 bus_dmamap_sync(dma->tag, dma->map, BUS_DMASYNC_PREWRITE); 6145 6146 if ((error = iwn_nic_lock(sc)) != 0) 6147 return error; 6148 6149 IWN_WRITE(sc, IWN_FH_TX_CONFIG(IWN_SRVC_DMACHNL), 6150 IWN_FH_TX_CONFIG_DMA_PAUSE); 6151 6152 IWN_WRITE(sc, IWN_FH_SRAM_ADDR(IWN_SRVC_DMACHNL), dst); 6153 IWN_WRITE(sc, IWN_FH_TFBD_CTRL0(IWN_SRVC_DMACHNL), 6154 IWN_LOADDR(dma->paddr)); 6155 IWN_WRITE(sc, IWN_FH_TFBD_CTRL1(IWN_SRVC_DMACHNL), 6156 IWN_HIADDR(dma->paddr) << 28 | size); 6157 IWN_WRITE(sc, IWN_FH_TXBUF_STATUS(IWN_SRVC_DMACHNL), 6158 IWN_FH_TXBUF_STATUS_TBNUM(1) | 6159 IWN_FH_TXBUF_STATUS_TBIDX(1) | 6160 IWN_FH_TXBUF_STATUS_TFBD_VALID); 6161 6162 /* Kick Flow Handler to start DMA transfer. */ 6163 IWN_WRITE(sc, IWN_FH_TX_CONFIG(IWN_SRVC_DMACHNL), 6164 IWN_FH_TX_CONFIG_DMA_ENA | IWN_FH_TX_CONFIG_CIRQ_HOST_ENDTFD); 6165 6166 iwn_nic_unlock(sc); 6167 6168 /* Wait at most five seconds for FH DMA transfer to complete. */ 6169 return msleep(sc, &sc->sc_mtx, PCATCH, "iwninit", 5 * hz); 6170 } 6171 6172 static int 6173 iwn5000_load_firmware(struct iwn_softc *sc) 6174 { 6175 struct iwn_fw_part *fw; 6176 int error; 6177 6178 /* Load the initialization firmware on first boot only. */ 6179 fw = (sc->sc_flags & IWN_FLAG_CALIB_DONE) ? 6180 &sc->fw.main : &sc->fw.init; 6181 6182 error = iwn5000_load_firmware_section(sc, IWN_FW_TEXT_BASE, 6183 fw->text, fw->textsz); 6184 if (error != 0) { 6185 device_printf(sc->sc_dev, 6186 "%s: could not load firmware %s section, error %d\n", 6187 __func__, ".text", error); 6188 return error; 6189 } 6190 error = iwn5000_load_firmware_section(sc, IWN_FW_DATA_BASE, 6191 fw->data, fw->datasz); 6192 if (error != 0) { 6193 device_printf(sc->sc_dev, 6194 "%s: could not load firmware %s section, error %d\n", 6195 __func__, ".data", error); 6196 return error; 6197 } 6198 6199 /* Now press "execute". */ 6200 IWN_WRITE(sc, IWN_RESET, 0); 6201 return 0; 6202 } 6203 6204 /* 6205 * Extract text and data sections from a legacy firmware image. 6206 */ 6207 static int 6208 iwn_read_firmware_leg(struct iwn_softc *sc, struct iwn_fw_info *fw) 6209 { 6210 const uint32_t *ptr; 6211 size_t hdrlen = 24; 6212 uint32_t rev; 6213 6214 ptr = (const uint32_t *)fw->data; 6215 rev = le32toh(*ptr++); 6216 6217 /* Check firmware API version. */ 6218 if (IWN_FW_API(rev) <= 1) { 6219 device_printf(sc->sc_dev, 6220 "%s: bad firmware, need API version >=2\n", __func__); 6221 return EINVAL; 6222 } 6223 if (IWN_FW_API(rev) >= 3) { 6224 /* Skip build number (version 2 header). */ 6225 hdrlen += 4; 6226 ptr++; 6227 } 6228 if (fw->size < hdrlen) { 6229 device_printf(sc->sc_dev, "%s: firmware too short: %zu bytes\n", 6230 __func__, fw->size); 6231 return EINVAL; 6232 } 6233 fw->main.textsz = le32toh(*ptr++); 6234 fw->main.datasz = le32toh(*ptr++); 6235 fw->init.textsz = le32toh(*ptr++); 6236 fw->init.datasz = le32toh(*ptr++); 6237 fw->boot.textsz = le32toh(*ptr++); 6238 6239 /* Check that all firmware sections fit. */ 6240 if (fw->size < hdrlen + fw->main.textsz + fw->main.datasz + 6241 fw->init.textsz + fw->init.datasz + fw->boot.textsz) { 6242 device_printf(sc->sc_dev, "%s: firmware too short: %zu bytes\n", 6243 __func__, fw->size); 6244 return EINVAL; 6245 } 6246 6247 /* Get pointers to firmware sections. */ 6248 fw->main.text = (const uint8_t *)ptr; 6249 fw->main.data = fw->main.text + fw->main.textsz; 6250 fw->init.text = fw->main.data + fw->main.datasz; 6251 fw->init.data = fw->init.text + fw->init.textsz; 6252 fw->boot.text = fw->init.data + fw->init.datasz; 6253 return 0; 6254 } 6255 6256 /* 6257 * Extract text and data sections from a TLV firmware image. 6258 */ 6259 static int 6260 iwn_read_firmware_tlv(struct iwn_softc *sc, struct iwn_fw_info *fw, 6261 uint16_t alt) 6262 { 6263 const struct iwn_fw_tlv_hdr *hdr; 6264 const struct iwn_fw_tlv *tlv; 6265 const uint8_t *ptr, *end; 6266 uint64_t altmask; 6267 uint32_t len, tmp; 6268 6269 if (fw->size < sizeof (*hdr)) { 6270 device_printf(sc->sc_dev, "%s: firmware too short: %zu bytes\n", 6271 __func__, fw->size); 6272 return EINVAL; 6273 } 6274 hdr = (const struct iwn_fw_tlv_hdr *)fw->data; 6275 if (hdr->signature != htole32(IWN_FW_SIGNATURE)) { 6276 device_printf(sc->sc_dev, "%s: bad firmware signature 0x%08x\n", 6277 __func__, le32toh(hdr->signature)); 6278 return EINVAL; 6279 } 6280 DPRINTF(sc, IWN_DEBUG_RESET, "FW: \"%.64s\", build 0x%x\n", hdr->descr, 6281 le32toh(hdr->build)); 6282 6283 /* 6284 * Select the closest supported alternative that is less than 6285 * or equal to the specified one. 6286 */ 6287 altmask = le64toh(hdr->altmask); 6288 while (alt > 0 && !(altmask & (1ULL << alt))) 6289 alt--; /* Downgrade. */ 6290 DPRINTF(sc, IWN_DEBUG_RESET, "using alternative %d\n", alt); 6291 6292 ptr = (const uint8_t *)(hdr + 1); 6293 end = (const uint8_t *)(fw->data + fw->size); 6294 6295 /* Parse type-length-value fields. */ 6296 while (ptr + sizeof (*tlv) <= end) { 6297 tlv = (const struct iwn_fw_tlv *)ptr; 6298 len = le32toh(tlv->len); 6299 6300 ptr += sizeof (*tlv); 6301 if (ptr + len > end) { 6302 device_printf(sc->sc_dev, 6303 "%s: firmware too short: %zu bytes\n", __func__, 6304 fw->size); 6305 return EINVAL; 6306 } 6307 /* Skip other alternatives. */ 6308 if (tlv->alt != 0 && tlv->alt != htole16(alt)) 6309 goto next; 6310 6311 switch (le16toh(tlv->type)) { 6312 case IWN_FW_TLV_MAIN_TEXT: 6313 fw->main.text = ptr; 6314 fw->main.textsz = len; 6315 break; 6316 case IWN_FW_TLV_MAIN_DATA: 6317 fw->main.data = ptr; 6318 fw->main.datasz = len; 6319 break; 6320 case IWN_FW_TLV_INIT_TEXT: 6321 fw->init.text = ptr; 6322 fw->init.textsz = len; 6323 break; 6324 case IWN_FW_TLV_INIT_DATA: 6325 fw->init.data = ptr; 6326 fw->init.datasz = len; 6327 break; 6328 case IWN_FW_TLV_BOOT_TEXT: 6329 fw->boot.text = ptr; 6330 fw->boot.textsz = len; 6331 break; 6332 case IWN_FW_TLV_ENH_SENS: 6333 if (!len) 6334 sc->sc_flags |= IWN_FLAG_ENH_SENS; 6335 break; 6336 case IWN_FW_TLV_PHY_CALIB: 6337 tmp = htole32(*ptr); 6338 if (tmp < 253) { 6339 sc->reset_noise_gain = tmp; 6340 sc->noise_gain = tmp + 1; 6341 } 6342 break; 6343 default: 6344 DPRINTF(sc, IWN_DEBUG_RESET, 6345 "TLV type %d not handled\n", le16toh(tlv->type)); 6346 break; 6347 } 6348 next: /* TLV fields are 32-bit aligned. */ 6349 ptr += (len + 3) & ~3; 6350 } 6351 return 0; 6352 } 6353 6354 static int 6355 iwn_read_firmware(struct iwn_softc *sc) 6356 { 6357 struct iwn_fw_info *fw = &sc->fw; 6358 int error; 6359 6360 IWN_UNLOCK(sc); 6361 6362 memset(fw, 0, sizeof (*fw)); 6363 6364 /* Read firmware image from filesystem. */ 6365 sc->fw_fp = firmware_get(sc->fwname); 6366 if (sc->fw_fp == NULL) { 6367 device_printf(sc->sc_dev, "%s: could not read firmware %s\n", 6368 __func__, sc->fwname); 6369 IWN_LOCK(sc); 6370 return EINVAL; 6371 } 6372 IWN_LOCK(sc); 6373 6374 fw->size = sc->fw_fp->datasize; 6375 fw->data = (const uint8_t *)sc->fw_fp->data; 6376 if (fw->size < sizeof (uint32_t)) { 6377 device_printf(sc->sc_dev, "%s: firmware too short: %zu bytes\n", 6378 __func__, fw->size); 6379 firmware_put(sc->fw_fp, FIRMWARE_UNLOAD); 6380 sc->fw_fp = NULL; 6381 return EINVAL; 6382 } 6383 6384 /* Retrieve text and data sections. */ 6385 if (*(const uint32_t *)fw->data != 0) /* Legacy image. */ 6386 error = iwn_read_firmware_leg(sc, fw); 6387 else 6388 error = iwn_read_firmware_tlv(sc, fw, 1); 6389 if (error != 0) { 6390 device_printf(sc->sc_dev, 6391 "%s: could not read firmware sections, error %d\n", 6392 __func__, error); 6393 firmware_put(sc->fw_fp, FIRMWARE_UNLOAD); 6394 sc->fw_fp = NULL; 6395 return error; 6396 } 6397 6398 /* Make sure text and data sections fit in hardware memory. */ 6399 if (fw->main.textsz > sc->fw_text_maxsz || 6400 fw->main.datasz > sc->fw_data_maxsz || 6401 fw->init.textsz > sc->fw_text_maxsz || 6402 fw->init.datasz > sc->fw_data_maxsz || 6403 fw->boot.textsz > IWN_FW_BOOT_TEXT_MAXSZ || 6404 (fw->boot.textsz & 3) != 0) { 6405 device_printf(sc->sc_dev, "%s: firmware sections too large\n", 6406 __func__); 6407 firmware_put(sc->fw_fp, FIRMWARE_UNLOAD); 6408 sc->fw_fp = NULL; 6409 return EINVAL; 6410 } 6411 6412 /* We can proceed with loading the firmware. */ 6413 return 0; 6414 } 6415 6416 static int 6417 iwn_clock_wait(struct iwn_softc *sc) 6418 { 6419 int ntries; 6420 6421 /* Set "initialization complete" bit. */ 6422 IWN_SETBITS(sc, IWN_GP_CNTRL, IWN_GP_CNTRL_INIT_DONE); 6423 6424 /* Wait for clock stabilization. */ 6425 for (ntries = 0; ntries < 2500; ntries++) { 6426 if (IWN_READ(sc, IWN_GP_CNTRL) & IWN_GP_CNTRL_MAC_CLOCK_READY) 6427 return 0; 6428 DELAY(10); 6429 } 6430 device_printf(sc->sc_dev, 6431 "%s: timeout waiting for clock stabilization\n", __func__); 6432 return ETIMEDOUT; 6433 } 6434 6435 static int 6436 iwn_apm_init(struct iwn_softc *sc) 6437 { 6438 uint32_t reg; 6439 int error; 6440 6441 /* Disable L0s exit timer (NMI bug workaround). */ 6442 IWN_SETBITS(sc, IWN_GIO_CHICKEN, IWN_GIO_CHICKEN_DIS_L0S_TIMER); 6443 /* Don't wait for ICH L0s (ICH bug workaround). */ 6444 IWN_SETBITS(sc, IWN_GIO_CHICKEN, IWN_GIO_CHICKEN_L1A_NO_L0S_RX); 6445 6446 /* Set FH wait threshold to max (HW bug under stress workaround). */ 6447 IWN_SETBITS(sc, IWN_DBG_HPET_MEM, 0xffff0000); 6448 6449 /* Enable HAP INTA to move adapter from L1a to L0s. */ 6450 IWN_SETBITS(sc, IWN_HW_IF_CONFIG, IWN_HW_IF_CONFIG_HAP_WAKE_L1A); 6451 6452 /* Retrieve PCIe Active State Power Management (ASPM). */ 6453 reg = pci_read_config(sc->sc_dev, sc->sc_cap_off + 0x10, 1); 6454 /* Workaround for HW instability in PCIe L0->L0s->L1 transition. */ 6455 if (reg & 0x02) /* L1 Entry enabled. */ 6456 IWN_SETBITS(sc, IWN_GIO, IWN_GIO_L0S_ENA); 6457 else 6458 IWN_CLRBITS(sc, IWN_GIO, IWN_GIO_L0S_ENA); 6459 6460 if (sc->hw_type != IWN_HW_REV_TYPE_4965 && 6461 sc->hw_type <= IWN_HW_REV_TYPE_1000) 6462 IWN_SETBITS(sc, IWN_ANA_PLL, IWN_ANA_PLL_INIT); 6463 6464 /* Wait for clock stabilization before accessing prph. */ 6465 if ((error = iwn_clock_wait(sc)) != 0) 6466 return error; 6467 6468 if ((error = iwn_nic_lock(sc)) != 0) 6469 return error; 6470 if (sc->hw_type == IWN_HW_REV_TYPE_4965) { 6471 /* Enable DMA and BSM (Bootstrap State Machine). */ 6472 iwn_prph_write(sc, IWN_APMG_CLK_EN, 6473 IWN_APMG_CLK_CTRL_DMA_CLK_RQT | 6474 IWN_APMG_CLK_CTRL_BSM_CLK_RQT); 6475 } else { 6476 /* Enable DMA. */ 6477 iwn_prph_write(sc, IWN_APMG_CLK_EN, 6478 IWN_APMG_CLK_CTRL_DMA_CLK_RQT); 6479 } 6480 DELAY(20); 6481 /* Disable L1-Active. */ 6482 iwn_prph_setbits(sc, IWN_APMG_PCI_STT, IWN_APMG_PCI_STT_L1A_DIS); 6483 iwn_nic_unlock(sc); 6484 6485 return 0; 6486 } 6487 6488 static void 6489 iwn_apm_stop_master(struct iwn_softc *sc) 6490 { 6491 int ntries; 6492 6493 /* Stop busmaster DMA activity. */ 6494 IWN_SETBITS(sc, IWN_RESET, IWN_RESET_STOP_MASTER); 6495 for (ntries = 0; ntries < 100; ntries++) { 6496 if (IWN_READ(sc, IWN_RESET) & IWN_RESET_MASTER_DISABLED) 6497 return; 6498 DELAY(10); 6499 } 6500 device_printf(sc->sc_dev, "%s: timeout waiting for master\n", __func__); 6501 } 6502 6503 static void 6504 iwn_apm_stop(struct iwn_softc *sc) 6505 { 6506 iwn_apm_stop_master(sc); 6507 6508 /* Reset the entire device. */ 6509 IWN_SETBITS(sc, IWN_RESET, IWN_RESET_SW); 6510 DELAY(10); 6511 /* Clear "initialization complete" bit. */ 6512 IWN_CLRBITS(sc, IWN_GP_CNTRL, IWN_GP_CNTRL_INIT_DONE); 6513 } 6514 6515 static int 6516 iwn4965_nic_config(struct iwn_softc *sc) 6517 { 6518 if (IWN_RFCFG_TYPE(sc->rfcfg) == 1) { 6519 /* 6520 * I don't believe this to be correct but this is what the 6521 * vendor driver is doing. Probably the bits should not be 6522 * shifted in IWN_RFCFG_*. 6523 */ 6524 IWN_SETBITS(sc, IWN_HW_IF_CONFIG, 6525 IWN_RFCFG_TYPE(sc->rfcfg) | 6526 IWN_RFCFG_STEP(sc->rfcfg) | 6527 IWN_RFCFG_DASH(sc->rfcfg)); 6528 } 6529 IWN_SETBITS(sc, IWN_HW_IF_CONFIG, 6530 IWN_HW_IF_CONFIG_RADIO_SI | IWN_HW_IF_CONFIG_MAC_SI); 6531 return 0; 6532 } 6533 6534 static int 6535 iwn5000_nic_config(struct iwn_softc *sc) 6536 { 6537 uint32_t tmp; 6538 int error; 6539 6540 if (IWN_RFCFG_TYPE(sc->rfcfg) < 3) { 6541 IWN_SETBITS(sc, IWN_HW_IF_CONFIG, 6542 IWN_RFCFG_TYPE(sc->rfcfg) | 6543 IWN_RFCFG_STEP(sc->rfcfg) | 6544 IWN_RFCFG_DASH(sc->rfcfg)); 6545 } 6546 IWN_SETBITS(sc, IWN_HW_IF_CONFIG, 6547 IWN_HW_IF_CONFIG_RADIO_SI | IWN_HW_IF_CONFIG_MAC_SI); 6548 6549 if ((error = iwn_nic_lock(sc)) != 0) 6550 return error; 6551 iwn_prph_setbits(sc, IWN_APMG_PS, IWN_APMG_PS_EARLY_PWROFF_DIS); 6552 6553 if (sc->hw_type == IWN_HW_REV_TYPE_1000) { 6554 /* 6555 * Select first Switching Voltage Regulator (1.32V) to 6556 * solve a stability issue related to noisy DC2DC line 6557 * in the silicon of 1000 Series. 6558 */ 6559 tmp = iwn_prph_read(sc, IWN_APMG_DIGITAL_SVR); 6560 tmp &= ~IWN_APMG_DIGITAL_SVR_VOLTAGE_MASK; 6561 tmp |= IWN_APMG_DIGITAL_SVR_VOLTAGE_1_32; 6562 iwn_prph_write(sc, IWN_APMG_DIGITAL_SVR, tmp); 6563 } 6564 iwn_nic_unlock(sc); 6565 6566 if (sc->sc_flags & IWN_FLAG_INTERNAL_PA) { 6567 /* Use internal power amplifier only. */ 6568 IWN_WRITE(sc, IWN_GP_DRIVER, IWN_GP_DRIVER_RADIO_2X2_IPA); 6569 } 6570 if ((sc->hw_type == IWN_HW_REV_TYPE_6050 || 6571 sc->hw_type == IWN_HW_REV_TYPE_6005) && sc->calib_ver >= 6) { 6572 /* Indicate that ROM calibration version is >=6. */ 6573 IWN_SETBITS(sc, IWN_GP_DRIVER, IWN_GP_DRIVER_CALIB_VER6); 6574 } 6575 if (sc->hw_type == IWN_HW_REV_TYPE_6005) 6576 IWN_SETBITS(sc, IWN_GP_DRIVER, IWN_GP_DRIVER_6050_1X2); 6577 return 0; 6578 } 6579 6580 /* 6581 * Take NIC ownership over Intel Active Management Technology (AMT). 6582 */ 6583 static int 6584 iwn_hw_prepare(struct iwn_softc *sc) 6585 { 6586 int ntries; 6587 6588 /* Check if hardware is ready. */ 6589 IWN_SETBITS(sc, IWN_HW_IF_CONFIG, IWN_HW_IF_CONFIG_NIC_READY); 6590 for (ntries = 0; ntries < 5; ntries++) { 6591 if (IWN_READ(sc, IWN_HW_IF_CONFIG) & 6592 IWN_HW_IF_CONFIG_NIC_READY) 6593 return 0; 6594 DELAY(10); 6595 } 6596 6597 /* Hardware not ready, force into ready state. */ 6598 IWN_SETBITS(sc, IWN_HW_IF_CONFIG, IWN_HW_IF_CONFIG_PREPARE); 6599 for (ntries = 0; ntries < 15000; ntries++) { 6600 if (!(IWN_READ(sc, IWN_HW_IF_CONFIG) & 6601 IWN_HW_IF_CONFIG_PREPARE_DONE)) 6602 break; 6603 DELAY(10); 6604 } 6605 if (ntries == 15000) 6606 return ETIMEDOUT; 6607 6608 /* Hardware should be ready now. */ 6609 IWN_SETBITS(sc, IWN_HW_IF_CONFIG, IWN_HW_IF_CONFIG_NIC_READY); 6610 for (ntries = 0; ntries < 5; ntries++) { 6611 if (IWN_READ(sc, IWN_HW_IF_CONFIG) & 6612 IWN_HW_IF_CONFIG_NIC_READY) 6613 return 0; 6614 DELAY(10); 6615 } 6616 return ETIMEDOUT; 6617 } 6618 6619 static int 6620 iwn_hw_init(struct iwn_softc *sc) 6621 { 6622 struct iwn_ops *ops = &sc->ops; 6623 int error, chnl, qid; 6624 6625 /* Clear pending interrupts. */ 6626 IWN_WRITE(sc, IWN_INT, 0xffffffff); 6627 6628 if ((error = iwn_apm_init(sc)) != 0) { 6629 device_printf(sc->sc_dev, 6630 "%s: could not power ON adapter, error %d\n", __func__, 6631 error); 6632 return error; 6633 } 6634 6635 /* Select VMAIN power source. */ 6636 if ((error = iwn_nic_lock(sc)) != 0) 6637 return error; 6638 iwn_prph_clrbits(sc, IWN_APMG_PS, IWN_APMG_PS_PWR_SRC_MASK); 6639 iwn_nic_unlock(sc); 6640 6641 /* Perform adapter-specific initialization. */ 6642 if ((error = ops->nic_config(sc)) != 0) 6643 return error; 6644 6645 /* Initialize RX ring. */ 6646 if ((error = iwn_nic_lock(sc)) != 0) 6647 return error; 6648 IWN_WRITE(sc, IWN_FH_RX_CONFIG, 0); 6649 IWN_WRITE(sc, IWN_FH_RX_WPTR, 0); 6650 /* Set physical address of RX ring (256-byte aligned). */ 6651 IWN_WRITE(sc, IWN_FH_RX_BASE, sc->rxq.desc_dma.paddr >> 8); 6652 /* Set physical address of RX status (16-byte aligned). */ 6653 IWN_WRITE(sc, IWN_FH_STATUS_WPTR, sc->rxq.stat_dma.paddr >> 4); 6654 /* Enable RX. */ 6655 IWN_WRITE(sc, IWN_FH_RX_CONFIG, 6656 IWN_FH_RX_CONFIG_ENA | 6657 IWN_FH_RX_CONFIG_IGN_RXF_EMPTY | /* HW bug workaround */ 6658 IWN_FH_RX_CONFIG_IRQ_DST_HOST | 6659 IWN_FH_RX_CONFIG_SINGLE_FRAME | 6660 IWN_FH_RX_CONFIG_RB_TIMEOUT(0) | 6661 IWN_FH_RX_CONFIG_NRBD(IWN_RX_RING_COUNT_LOG)); 6662 iwn_nic_unlock(sc); 6663 IWN_WRITE(sc, IWN_FH_RX_WPTR, (IWN_RX_RING_COUNT - 1) & ~7); 6664 6665 if ((error = iwn_nic_lock(sc)) != 0) 6666 return error; 6667 6668 /* Initialize TX scheduler. */ 6669 iwn_prph_write(sc, sc->sched_txfact_addr, 0); 6670 6671 /* Set physical address of "keep warm" page (16-byte aligned). */ 6672 IWN_WRITE(sc, IWN_FH_KW_ADDR, sc->kw_dma.paddr >> 4); 6673 6674 /* Initialize TX rings. */ 6675 for (qid = 0; qid < sc->ntxqs; qid++) { 6676 struct iwn_tx_ring *txq = &sc->txq[qid]; 6677 6678 /* Set physical address of TX ring (256-byte aligned). */ 6679 IWN_WRITE(sc, IWN_FH_CBBC_QUEUE(qid), 6680 txq->desc_dma.paddr >> 8); 6681 } 6682 iwn_nic_unlock(sc); 6683 6684 /* Enable DMA channels. */ 6685 for (chnl = 0; chnl < sc->ndmachnls; chnl++) { 6686 IWN_WRITE(sc, IWN_FH_TX_CONFIG(chnl), 6687 IWN_FH_TX_CONFIG_DMA_ENA | 6688 IWN_FH_TX_CONFIG_DMA_CREDIT_ENA); 6689 } 6690 6691 /* Clear "radio off" and "commands blocked" bits. */ 6692 IWN_WRITE(sc, IWN_UCODE_GP1_CLR, IWN_UCODE_GP1_RFKILL); 6693 IWN_WRITE(sc, IWN_UCODE_GP1_CLR, IWN_UCODE_GP1_CMD_BLOCKED); 6694 6695 /* Clear pending interrupts. */ 6696 IWN_WRITE(sc, IWN_INT, 0xffffffff); 6697 /* Enable interrupt coalescing. */ 6698 IWN_WRITE(sc, IWN_INT_COALESCING, 512 / 8); 6699 /* Enable interrupts. */ 6700 IWN_WRITE(sc, IWN_INT_MASK, sc->int_mask); 6701 6702 /* _Really_ make sure "radio off" bit is cleared! */ 6703 IWN_WRITE(sc, IWN_UCODE_GP1_CLR, IWN_UCODE_GP1_RFKILL); 6704 IWN_WRITE(sc, IWN_UCODE_GP1_CLR, IWN_UCODE_GP1_RFKILL); 6705 6706 /* Enable shadow registers. */ 6707 if (sc->hw_type >= IWN_HW_REV_TYPE_6000) 6708 IWN_SETBITS(sc, IWN_SHADOW_REG_CTRL, 0x800fffff); 6709 6710 if ((error = ops->load_firmware(sc)) != 0) { 6711 device_printf(sc->sc_dev, 6712 "%s: could not load firmware, error %d\n", __func__, 6713 error); 6714 return error; 6715 } 6716 /* Wait at most one second for firmware alive notification. */ 6717 if ((error = msleep(sc, &sc->sc_mtx, PCATCH, "iwninit", hz)) != 0) { 6718 device_printf(sc->sc_dev, 6719 "%s: timeout waiting for adapter to initialize, error %d\n", 6720 __func__, error); 6721 return error; 6722 } 6723 /* Do post-firmware initialization. */ 6724 return ops->post_alive(sc); 6725 } 6726 6727 static void 6728 iwn_hw_stop(struct iwn_softc *sc) 6729 { 6730 int chnl, qid, ntries; 6731 6732 IWN_WRITE(sc, IWN_RESET, IWN_RESET_NEVO); 6733 6734 /* Disable interrupts. */ 6735 IWN_WRITE(sc, IWN_INT_MASK, 0); 6736 IWN_WRITE(sc, IWN_INT, 0xffffffff); 6737 IWN_WRITE(sc, IWN_FH_INT, 0xffffffff); 6738 sc->sc_flags &= ~IWN_FLAG_USE_ICT; 6739 6740 /* Make sure we no longer hold the NIC lock. */ 6741 iwn_nic_unlock(sc); 6742 6743 /* Stop TX scheduler. */ 6744 iwn_prph_write(sc, sc->sched_txfact_addr, 0); 6745 6746 /* Stop all DMA channels. */ 6747 if (iwn_nic_lock(sc) == 0) { 6748 for (chnl = 0; chnl < sc->ndmachnls; chnl++) { 6749 IWN_WRITE(sc, IWN_FH_TX_CONFIG(chnl), 0); 6750 for (ntries = 0; ntries < 200; ntries++) { 6751 if (IWN_READ(sc, IWN_FH_TX_STATUS) & 6752 IWN_FH_TX_STATUS_IDLE(chnl)) 6753 break; 6754 DELAY(10); 6755 } 6756 } 6757 iwn_nic_unlock(sc); 6758 } 6759 6760 /* Stop RX ring. */ 6761 iwn_reset_rx_ring(sc, &sc->rxq); 6762 6763 /* Reset all TX rings. */ 6764 for (qid = 0; qid < sc->ntxqs; qid++) 6765 iwn_reset_tx_ring(sc, &sc->txq[qid]); 6766 6767 if (iwn_nic_lock(sc) == 0) { 6768 iwn_prph_write(sc, IWN_APMG_CLK_DIS, 6769 IWN_APMG_CLK_CTRL_DMA_CLK_RQT); 6770 iwn_nic_unlock(sc); 6771 } 6772 DELAY(5); 6773 /* Power OFF adapter. */ 6774 iwn_apm_stop(sc); 6775 } 6776 6777 static void 6778 iwn_radio_on(void *arg0, int pending) 6779 { 6780 struct iwn_softc *sc = arg0; 6781 struct ifnet *ifp = sc->sc_ifp; 6782 struct ieee80211com *ic = ifp->if_l2com; 6783 struct ieee80211vap *vap = TAILQ_FIRST(&ic->ic_vaps); 6784 6785 if (vap != NULL) { 6786 iwn_init(sc); 6787 ieee80211_init(vap); 6788 } 6789 } 6790 6791 static void 6792 iwn_radio_off(void *arg0, int pending) 6793 { 6794 struct iwn_softc *sc = arg0; 6795 struct ifnet *ifp = sc->sc_ifp; 6796 struct ieee80211com *ic = ifp->if_l2com; 6797 struct ieee80211vap *vap = TAILQ_FIRST(&ic->ic_vaps); 6798 6799 iwn_stop(sc); 6800 if (vap != NULL) 6801 ieee80211_stop(vap); 6802 6803 /* Enable interrupts to get RF toggle notification. */ 6804 IWN_LOCK(sc); 6805 IWN_WRITE(sc, IWN_INT, 0xffffffff); 6806 IWN_WRITE(sc, IWN_INT_MASK, sc->int_mask); 6807 IWN_UNLOCK(sc); 6808 } 6809 6810 static void 6811 iwn_init_locked(struct iwn_softc *sc) 6812 { 6813 struct ifnet *ifp = sc->sc_ifp; 6814 int error; 6815 6816 IWN_LOCK_ASSERT(sc); 6817 6818 if ((error = iwn_hw_prepare(sc)) != 0) { 6819 device_printf(sc->sc_dev, "%s: hardware not ready, error %d\n", 6820 __func__, error); 6821 goto fail; 6822 } 6823 6824 /* Initialize interrupt mask to default value. */ 6825 sc->int_mask = IWN_INT_MASK_DEF; 6826 sc->sc_flags &= ~IWN_FLAG_USE_ICT; 6827 6828 /* Check that the radio is not disabled by hardware switch. */ 6829 if (!(IWN_READ(sc, IWN_GP_CNTRL) & IWN_GP_CNTRL_RFKILL)) { 6830 device_printf(sc->sc_dev, 6831 "radio is disabled by hardware switch\n"); 6832 /* Enable interrupts to get RF toggle notifications. */ 6833 IWN_WRITE(sc, IWN_INT, 0xffffffff); 6834 IWN_WRITE(sc, IWN_INT_MASK, sc->int_mask); 6835 return; 6836 } 6837 6838 /* Read firmware images from the filesystem. */ 6839 if ((error = iwn_read_firmware(sc)) != 0) { 6840 device_printf(sc->sc_dev, 6841 "%s: could not read firmware, error %d\n", __func__, 6842 error); 6843 goto fail; 6844 } 6845 6846 /* Initialize hardware and upload firmware. */ 6847 error = iwn_hw_init(sc); 6848 firmware_put(sc->fw_fp, FIRMWARE_UNLOAD); 6849 sc->fw_fp = NULL; 6850 if (error != 0) { 6851 device_printf(sc->sc_dev, 6852 "%s: could not initialize hardware, error %d\n", __func__, 6853 error); 6854 goto fail; 6855 } 6856 6857 /* Configure adapter now that it is ready. */ 6858 if ((error = iwn_config(sc)) != 0) { 6859 device_printf(sc->sc_dev, 6860 "%s: could not configure device, error %d\n", __func__, 6861 error); 6862 goto fail; 6863 } 6864 6865 ifp->if_drv_flags &= ~IFF_DRV_OACTIVE; 6866 ifp->if_drv_flags |= IFF_DRV_RUNNING; 6867 6868 callout_reset(&sc->watchdog_to, hz, iwn_watchdog, sc); 6869 return; 6870 6871 fail: iwn_stop_locked(sc); 6872 } 6873 6874 static void 6875 iwn_init(void *arg) 6876 { 6877 struct iwn_softc *sc = arg; 6878 struct ifnet *ifp = sc->sc_ifp; 6879 struct ieee80211com *ic = ifp->if_l2com; 6880 6881 IWN_LOCK(sc); 6882 iwn_init_locked(sc); 6883 IWN_UNLOCK(sc); 6884 6885 if (ifp->if_drv_flags & IFF_DRV_RUNNING) 6886 ieee80211_start_all(ic); 6887 } 6888 6889 static void 6890 iwn_stop_locked(struct iwn_softc *sc) 6891 { 6892 struct ifnet *ifp = sc->sc_ifp; 6893 6894 IWN_LOCK_ASSERT(sc); 6895 6896 sc->sc_tx_timer = 0; 6897 callout_stop(&sc->watchdog_to); 6898 callout_stop(&sc->calib_to); 6899 ifp->if_drv_flags &= ~(IFF_DRV_RUNNING | IFF_DRV_OACTIVE); 6900 6901 /* Power OFF hardware. */ 6902 iwn_hw_stop(sc); 6903 } 6904 6905 static void 6906 iwn_stop(struct iwn_softc *sc) 6907 { 6908 IWN_LOCK(sc); 6909 iwn_stop_locked(sc); 6910 IWN_UNLOCK(sc); 6911 } 6912 6913 /* 6914 * Callback from net80211 to start a scan. 6915 */ 6916 static void 6917 iwn_scan_start(struct ieee80211com *ic) 6918 { 6919 struct ifnet *ifp = ic->ic_ifp; 6920 struct iwn_softc *sc = ifp->if_softc; 6921 6922 IWN_LOCK(sc); 6923 /* make the link LED blink while we're scanning */ 6924 iwn_set_led(sc, IWN_LED_LINK, 20, 2); 6925 IWN_UNLOCK(sc); 6926 } 6927 6928 /* 6929 * Callback from net80211 to terminate a scan. 6930 */ 6931 static void 6932 iwn_scan_end(struct ieee80211com *ic) 6933 { 6934 struct ifnet *ifp = ic->ic_ifp; 6935 struct iwn_softc *sc = ifp->if_softc; 6936 struct ieee80211vap *vap = TAILQ_FIRST(&ic->ic_vaps); 6937 6938 IWN_LOCK(sc); 6939 if (vap->iv_state == IEEE80211_S_RUN) { 6940 /* Set link LED to ON status if we are associated */ 6941 iwn_set_led(sc, IWN_LED_LINK, 0, 1); 6942 } 6943 IWN_UNLOCK(sc); 6944 } 6945 6946 /* 6947 * Callback from net80211 to force a channel change. 6948 */ 6949 static void 6950 iwn_set_channel(struct ieee80211com *ic) 6951 { 6952 const struct ieee80211_channel *c = ic->ic_curchan; 6953 struct ifnet *ifp = ic->ic_ifp; 6954 struct iwn_softc *sc = ifp->if_softc; 6955 6956 IWN_LOCK(sc); 6957 sc->sc_rxtap.wr_chan_freq = htole16(c->ic_freq); 6958 sc->sc_rxtap.wr_chan_flags = htole16(c->ic_flags); 6959 sc->sc_txtap.wt_chan_freq = htole16(c->ic_freq); 6960 sc->sc_txtap.wt_chan_flags = htole16(c->ic_flags); 6961 IWN_UNLOCK(sc); 6962 } 6963 6964 /* 6965 * Callback from net80211 to start scanning of the current channel. 6966 */ 6967 static void 6968 iwn_scan_curchan(struct ieee80211_scan_state *ss, unsigned long maxdwell) 6969 { 6970 struct ieee80211vap *vap = ss->ss_vap; 6971 struct iwn_softc *sc = vap->iv_ic->ic_ifp->if_softc; 6972 int error; 6973 6974 IWN_LOCK(sc); 6975 error = iwn_scan(sc); 6976 IWN_UNLOCK(sc); 6977 if (error != 0) 6978 ieee80211_cancel_scan(vap); 6979 } 6980 6981 /* 6982 * Callback from net80211 to handle the minimum dwell time being met. 6983 * The intent is to terminate the scan but we just let the firmware 6984 * notify us when it's finished as we have no safe way to abort it. 6985 */ 6986 static void 6987 iwn_scan_mindwell(struct ieee80211_scan_state *ss) 6988 { 6989 /* NB: don't try to abort scan; wait for firmware to finish */ 6990 } 6991 6992 static void 6993 iwn_hw_reset(void *arg0, int pending) 6994 { 6995 struct iwn_softc *sc = arg0; 6996 struct ifnet *ifp = sc->sc_ifp; 6997 struct ieee80211com *ic = ifp->if_l2com; 6998 6999 iwn_stop(sc); 7000 iwn_init(sc); 7001 ieee80211_notify_radio(ic, 1); 7002 } 7003