1 /*- 2 * Copyright (c) 2007-2009 3 * Damien Bergamini <damien.bergamini@free.fr> 4 * Copyright (c) 2008 5 * Benjamin Close <benjsc@FreeBSD.org> 6 * Copyright (c) 2008 Sam Leffler, Errno Consulting 7 * 8 * Permission to use, copy, modify, and distribute this software for any 9 * purpose with or without fee is hereby granted, provided that the above 10 * copyright notice and this permission notice appear in all copies. 11 * 12 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 13 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 14 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR 15 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 16 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN 17 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF 18 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 19 */ 20 21 /* 22 * Driver for Intel WiFi Link 4965 and 1000/5000/6000 Series 802.11 network 23 * adapters. 24 */ 25 26 #include <sys/cdefs.h> 27 __FBSDID("$FreeBSD$"); 28 29 #include <sys/param.h> 30 #include <sys/sockio.h> 31 #include <sys/sysctl.h> 32 #include <sys/mbuf.h> 33 #include <sys/kernel.h> 34 #include <sys/socket.h> 35 #include <sys/systm.h> 36 #include <sys/malloc.h> 37 #include <sys/bus.h> 38 #include <sys/rman.h> 39 #include <sys/endian.h> 40 #include <sys/firmware.h> 41 #include <sys/limits.h> 42 #include <sys/module.h> 43 #include <sys/queue.h> 44 #include <sys/taskqueue.h> 45 46 #include <machine/bus.h> 47 #include <machine/resource.h> 48 #include <machine/clock.h> 49 50 #include <dev/pci/pcireg.h> 51 #include <dev/pci/pcivar.h> 52 53 #include <net/bpf.h> 54 #include <net/if.h> 55 #include <net/if_arp.h> 56 #include <net/ethernet.h> 57 #include <net/if_dl.h> 58 #include <net/if_media.h> 59 #include <net/if_types.h> 60 61 #include <netinet/in.h> 62 #include <netinet/in_systm.h> 63 #include <netinet/in_var.h> 64 #include <netinet/if_ether.h> 65 #include <netinet/ip.h> 66 67 #include <net80211/ieee80211_var.h> 68 #include <net80211/ieee80211_radiotap.h> 69 #include <net80211/ieee80211_regdomain.h> 70 #include <net80211/ieee80211_ratectl.h> 71 72 #include <dev/iwn/if_iwnreg.h> 73 #include <dev/iwn/if_iwnvar.h> 74 75 struct iwn_ident { 76 uint16_t vendor; 77 uint16_t device; 78 const char *name; 79 }; 80 81 static const struct iwn_ident iwn_ident_table[] = { 82 { 0x8086, 0x0082, "Intel(R) Centrino(R) Advanced-N 6205" }, 83 { 0x8086, 0x0083, "Intel(R) Centrino(R) Wireless-N 1000" }, 84 { 0x8086, 0x0084, "Intel(R) Centrino(R) Wireless-N 1000" }, 85 { 0x8086, 0x0085, "Intel(R) Centrino(R) Advanced-N 6205" }, 86 { 0x8086, 0x0087, "Intel(R) Centrino(R) Advanced-N + WiMAX 6250" }, 87 { 0x8086, 0x0089, "Intel(R) Centrino(R) Advanced-N + WiMAX 6250" }, 88 { 0x8086, 0x008a, "Intel(R) Centrino(R) Wireless-N 1030" }, 89 { 0x8086, 0x008b, "Intel(R) Centrino(R) Wireless-N 1030" }, 90 { 0x8086, 0x0090, "Intel(R) Centrino(R) Advanced-N 6230" }, 91 { 0x8086, 0x0091, "Intel(R) Centrino(R) Advanced-N 6230" }, 92 { 0x8086, 0x4229, "Intel(R) Wireless WiFi Link 4965" }, 93 { 0x8086, 0x422b, "Intel(R) Centrino(R) Ultimate-N 6300" }, 94 { 0x8086, 0x422c, "Intel(R) Centrino(R) Advanced-N 6200" }, 95 { 0x8086, 0x4230, "Intel(R) Wireless WiFi Link 4965" }, 96 { 0x8086, 0x4232, "Intel(R) WiFi Link 5100" }, 97 { 0x8086, 0x4235, "Intel(R) Ultimate N WiFi Link 5300" }, 98 { 0x8086, 0x4236, "Intel(R) Ultimate N WiFi Link 5300" }, 99 { 0x8086, 0x4237, "Intel(R) WiFi Link 5100" }, 100 { 0x8086, 0x4238, "Intel(R) Centrino(R) Ultimate-N 6300" }, 101 { 0x8086, 0x4239, "Intel(R) Centrino(R) Advanced-N 6200" }, 102 { 0x8086, 0x423a, "Intel(R) WiMAX/WiFi Link 5350" }, 103 { 0x8086, 0x423b, "Intel(R) WiMAX/WiFi Link 5350" }, 104 { 0x8086, 0x423c, "Intel(R) WiMAX/WiFi Link 5150" }, 105 { 0x8086, 0x423d, "Intel(R) WiMAX/WiFi Link 5150" }, 106 { 0, 0, NULL } 107 }; 108 109 static int iwn_probe(device_t); 110 static int iwn_attach(device_t); 111 static int iwn4965_attach(struct iwn_softc *, uint16_t); 112 static int iwn5000_attach(struct iwn_softc *, uint16_t); 113 static void iwn_radiotap_attach(struct iwn_softc *); 114 static void iwn_sysctlattach(struct iwn_softc *); 115 static struct ieee80211vap *iwn_vap_create(struct ieee80211com *, 116 const char name[IFNAMSIZ], int unit, int opmode, 117 int flags, const uint8_t bssid[IEEE80211_ADDR_LEN], 118 const uint8_t mac[IEEE80211_ADDR_LEN]); 119 static void iwn_vap_delete(struct ieee80211vap *); 120 static int iwn_detach(device_t); 121 static int iwn_shutdown(device_t); 122 static int iwn_suspend(device_t); 123 static int iwn_resume(device_t); 124 static int iwn_nic_lock(struct iwn_softc *); 125 static int iwn_eeprom_lock(struct iwn_softc *); 126 static int iwn_init_otprom(struct iwn_softc *); 127 static int iwn_read_prom_data(struct iwn_softc *, uint32_t, void *, int); 128 static void iwn_dma_map_addr(void *, bus_dma_segment_t *, int, int); 129 static int iwn_dma_contig_alloc(struct iwn_softc *, struct iwn_dma_info *, 130 void **, bus_size_t, bus_size_t); 131 static void iwn_dma_contig_free(struct iwn_dma_info *); 132 static int iwn_alloc_sched(struct iwn_softc *); 133 static void iwn_free_sched(struct iwn_softc *); 134 static int iwn_alloc_kw(struct iwn_softc *); 135 static void iwn_free_kw(struct iwn_softc *); 136 static int iwn_alloc_ict(struct iwn_softc *); 137 static void iwn_free_ict(struct iwn_softc *); 138 static int iwn_alloc_fwmem(struct iwn_softc *); 139 static void iwn_free_fwmem(struct iwn_softc *); 140 static int iwn_alloc_rx_ring(struct iwn_softc *, struct iwn_rx_ring *); 141 static void iwn_reset_rx_ring(struct iwn_softc *, struct iwn_rx_ring *); 142 static void iwn_free_rx_ring(struct iwn_softc *, struct iwn_rx_ring *); 143 static int iwn_alloc_tx_ring(struct iwn_softc *, struct iwn_tx_ring *, 144 int); 145 static void iwn_reset_tx_ring(struct iwn_softc *, struct iwn_tx_ring *); 146 static void iwn_free_tx_ring(struct iwn_softc *, struct iwn_tx_ring *); 147 static void iwn5000_ict_reset(struct iwn_softc *); 148 static int iwn_read_eeprom(struct iwn_softc *, 149 uint8_t macaddr[IEEE80211_ADDR_LEN]); 150 static void iwn4965_read_eeprom(struct iwn_softc *); 151 static void iwn4965_print_power_group(struct iwn_softc *, int); 152 static void iwn5000_read_eeprom(struct iwn_softc *); 153 static uint32_t iwn_eeprom_channel_flags(struct iwn_eeprom_chan *); 154 static void iwn_read_eeprom_band(struct iwn_softc *, int); 155 #if 0 /* HT */ 156 static void iwn_read_eeprom_ht40(struct iwn_softc *, int); 157 #endif 158 static void iwn_read_eeprom_channels(struct iwn_softc *, int, uint32_t); 159 static struct iwn_eeprom_chan *iwn_find_eeprom_channel(struct iwn_softc *, 160 struct ieee80211_channel *); 161 static int iwn_setregdomain(struct ieee80211com *, 162 struct ieee80211_regdomain *, int, 163 struct ieee80211_channel[]); 164 static void iwn_read_eeprom_enhinfo(struct iwn_softc *); 165 static struct ieee80211_node *iwn_node_alloc(struct ieee80211vap *, 166 const uint8_t mac[IEEE80211_ADDR_LEN]); 167 static void iwn_newassoc(struct ieee80211_node *, int); 168 static int iwn_media_change(struct ifnet *); 169 static int iwn_newstate(struct ieee80211vap *, enum ieee80211_state, int); 170 static void iwn_calib_timeout(void *); 171 static void iwn_rx_phy(struct iwn_softc *, struct iwn_rx_desc *, 172 struct iwn_rx_data *); 173 static void iwn_rx_done(struct iwn_softc *, struct iwn_rx_desc *, 174 struct iwn_rx_data *); 175 #if 0 /* HT */ 176 static void iwn_rx_compressed_ba(struct iwn_softc *, struct iwn_rx_desc *, 177 struct iwn_rx_data *); 178 #endif 179 static void iwn5000_rx_calib_results(struct iwn_softc *, 180 struct iwn_rx_desc *, struct iwn_rx_data *); 181 static void iwn_rx_statistics(struct iwn_softc *, struct iwn_rx_desc *, 182 struct iwn_rx_data *); 183 static void iwn4965_tx_done(struct iwn_softc *, struct iwn_rx_desc *, 184 struct iwn_rx_data *); 185 static void iwn5000_tx_done(struct iwn_softc *, struct iwn_rx_desc *, 186 struct iwn_rx_data *); 187 static void iwn_tx_done(struct iwn_softc *, struct iwn_rx_desc *, int, 188 uint8_t); 189 static void iwn_cmd_done(struct iwn_softc *, struct iwn_rx_desc *); 190 static void iwn_notif_intr(struct iwn_softc *); 191 static void iwn_wakeup_intr(struct iwn_softc *); 192 static void iwn_rftoggle_intr(struct iwn_softc *); 193 static void iwn_fatal_intr(struct iwn_softc *); 194 static void iwn_intr(void *); 195 static void iwn4965_update_sched(struct iwn_softc *, int, int, uint8_t, 196 uint16_t); 197 static void iwn5000_update_sched(struct iwn_softc *, int, int, uint8_t, 198 uint16_t); 199 #ifdef notyet 200 static void iwn5000_reset_sched(struct iwn_softc *, int, int); 201 #endif 202 static uint8_t iwn_plcp_signal(int); 203 static int iwn_tx_data(struct iwn_softc *, struct mbuf *, 204 struct ieee80211_node *); 205 static int iwn_tx_data_raw(struct iwn_softc *, struct mbuf *, 206 struct ieee80211_node *, 207 const struct ieee80211_bpf_params *params); 208 static int iwn_raw_xmit(struct ieee80211_node *, struct mbuf *, 209 const struct ieee80211_bpf_params *); 210 static void iwn_start(struct ifnet *); 211 static void iwn_start_locked(struct ifnet *); 212 static void iwn_watchdog(void *); 213 static int iwn_ioctl(struct ifnet *, u_long, caddr_t); 214 static int iwn_cmd(struct iwn_softc *, int, const void *, int, int); 215 static int iwn4965_add_node(struct iwn_softc *, struct iwn_node_info *, 216 int); 217 static int iwn5000_add_node(struct iwn_softc *, struct iwn_node_info *, 218 int); 219 static int iwn_set_link_quality(struct iwn_softc *, 220 struct ieee80211_node *); 221 static int iwn_add_broadcast_node(struct iwn_softc *, int); 222 static int iwn_updateedca(struct ieee80211com *); 223 static void iwn_update_mcast(struct ifnet *); 224 static void iwn_set_led(struct iwn_softc *, uint8_t, uint8_t, uint8_t); 225 static int iwn_set_critical_temp(struct iwn_softc *); 226 static int iwn_set_timing(struct iwn_softc *, struct ieee80211_node *); 227 static void iwn4965_power_calibration(struct iwn_softc *, int); 228 static int iwn4965_set_txpower(struct iwn_softc *, 229 struct ieee80211_channel *, int); 230 static int iwn5000_set_txpower(struct iwn_softc *, 231 struct ieee80211_channel *, int); 232 static int iwn4965_get_rssi(struct iwn_softc *, struct iwn_rx_stat *); 233 static int iwn5000_get_rssi(struct iwn_softc *, struct iwn_rx_stat *); 234 static int iwn_get_noise(const struct iwn_rx_general_stats *); 235 static int iwn4965_get_temperature(struct iwn_softc *); 236 static int iwn5000_get_temperature(struct iwn_softc *); 237 static int iwn_init_sensitivity(struct iwn_softc *); 238 static void iwn_collect_noise(struct iwn_softc *, 239 const struct iwn_rx_general_stats *); 240 static int iwn4965_init_gains(struct iwn_softc *); 241 static int iwn5000_init_gains(struct iwn_softc *); 242 static int iwn4965_set_gains(struct iwn_softc *); 243 static int iwn5000_set_gains(struct iwn_softc *); 244 static void iwn_tune_sensitivity(struct iwn_softc *, 245 const struct iwn_rx_stats *); 246 static int iwn_send_sensitivity(struct iwn_softc *); 247 static int iwn_set_pslevel(struct iwn_softc *, int, int, int); 248 static int iwn_send_btcoex(struct iwn_softc *); 249 static int iwn_send_advanced_btcoex(struct iwn_softc *); 250 static int iwn_config(struct iwn_softc *); 251 static uint8_t *ieee80211_add_ssid(uint8_t *, const uint8_t *, u_int); 252 static int iwn_scan(struct iwn_softc *); 253 static int iwn_auth(struct iwn_softc *, struct ieee80211vap *vap); 254 static int iwn_run(struct iwn_softc *, struct ieee80211vap *vap); 255 #if 0 /* HT */ 256 static int iwn_ampdu_rx_start(struct ieee80211com *, 257 struct ieee80211_node *, uint8_t); 258 static void iwn_ampdu_rx_stop(struct ieee80211com *, 259 struct ieee80211_node *, uint8_t); 260 static int iwn_ampdu_tx_start(struct ieee80211com *, 261 struct ieee80211_node *, uint8_t); 262 static void iwn_ampdu_tx_stop(struct ieee80211com *, 263 struct ieee80211_node *, uint8_t); 264 static void iwn4965_ampdu_tx_start(struct iwn_softc *, 265 struct ieee80211_node *, uint8_t, uint16_t); 266 static void iwn4965_ampdu_tx_stop(struct iwn_softc *, 267 uint8_t, uint16_t); 268 static void iwn5000_ampdu_tx_start(struct iwn_softc *, 269 struct ieee80211_node *, uint8_t, uint16_t); 270 static void iwn5000_ampdu_tx_stop(struct iwn_softc *, 271 uint8_t, uint16_t); 272 #endif 273 static int iwn5000_query_calibration(struct iwn_softc *); 274 static int iwn5000_send_calibration(struct iwn_softc *); 275 static int iwn5000_send_wimax_coex(struct iwn_softc *); 276 static int iwn5000_crystal_calib(struct iwn_softc *); 277 static int iwn5000_temp_offset_calib(struct iwn_softc *); 278 static int iwn4965_post_alive(struct iwn_softc *); 279 static int iwn5000_post_alive(struct iwn_softc *); 280 static int iwn4965_load_bootcode(struct iwn_softc *, const uint8_t *, 281 int); 282 static int iwn4965_load_firmware(struct iwn_softc *); 283 static int iwn5000_load_firmware_section(struct iwn_softc *, uint32_t, 284 const uint8_t *, int); 285 static int iwn5000_load_firmware(struct iwn_softc *); 286 static int iwn_read_firmware_leg(struct iwn_softc *, 287 struct iwn_fw_info *); 288 static int iwn_read_firmware_tlv(struct iwn_softc *, 289 struct iwn_fw_info *, uint16_t); 290 static int iwn_read_firmware(struct iwn_softc *); 291 static int iwn_clock_wait(struct iwn_softc *); 292 static int iwn_apm_init(struct iwn_softc *); 293 static void iwn_apm_stop_master(struct iwn_softc *); 294 static void iwn_apm_stop(struct iwn_softc *); 295 static int iwn4965_nic_config(struct iwn_softc *); 296 static int iwn5000_nic_config(struct iwn_softc *); 297 static int iwn_hw_prepare(struct iwn_softc *); 298 static int iwn_hw_init(struct iwn_softc *); 299 static void iwn_hw_stop(struct iwn_softc *); 300 static void iwn_radio_on(void *, int); 301 static void iwn_radio_off(void *, int); 302 static void iwn_init_locked(struct iwn_softc *); 303 static void iwn_init(void *); 304 static void iwn_stop_locked(struct iwn_softc *); 305 static void iwn_stop(struct iwn_softc *); 306 static void iwn_scan_start(struct ieee80211com *); 307 static void iwn_scan_end(struct ieee80211com *); 308 static void iwn_set_channel(struct ieee80211com *); 309 static void iwn_scan_curchan(struct ieee80211_scan_state *, unsigned long); 310 static void iwn_scan_mindwell(struct ieee80211_scan_state *); 311 static void iwn_hw_reset(void *, int); 312 313 #define IWN_DEBUG 314 #ifdef IWN_DEBUG 315 enum { 316 IWN_DEBUG_XMIT = 0x00000001, /* basic xmit operation */ 317 IWN_DEBUG_RECV = 0x00000002, /* basic recv operation */ 318 IWN_DEBUG_STATE = 0x00000004, /* 802.11 state transitions */ 319 IWN_DEBUG_TXPOW = 0x00000008, /* tx power processing */ 320 IWN_DEBUG_RESET = 0x00000010, /* reset processing */ 321 IWN_DEBUG_OPS = 0x00000020, /* iwn_ops processing */ 322 IWN_DEBUG_BEACON = 0x00000040, /* beacon handling */ 323 IWN_DEBUG_WATCHDOG = 0x00000080, /* watchdog timeout */ 324 IWN_DEBUG_INTR = 0x00000100, /* ISR */ 325 IWN_DEBUG_CALIBRATE = 0x00000200, /* periodic calibration */ 326 IWN_DEBUG_NODE = 0x00000400, /* node management */ 327 IWN_DEBUG_LED = 0x00000800, /* led management */ 328 IWN_DEBUG_CMD = 0x00001000, /* cmd submission */ 329 IWN_DEBUG_FATAL = 0x80000000, /* fatal errors */ 330 IWN_DEBUG_ANY = 0xffffffff 331 }; 332 333 #define DPRINTF(sc, m, fmt, ...) do { \ 334 if (sc->sc_debug & (m)) \ 335 printf(fmt, __VA_ARGS__); \ 336 } while (0) 337 338 static const char * 339 iwn_intr_str(uint8_t cmd) 340 { 341 switch (cmd) { 342 /* Notifications */ 343 case IWN_UC_READY: return "UC_READY"; 344 case IWN_ADD_NODE_DONE: return "ADD_NODE_DONE"; 345 case IWN_TX_DONE: return "TX_DONE"; 346 case IWN_START_SCAN: return "START_SCAN"; 347 case IWN_STOP_SCAN: return "STOP_SCAN"; 348 case IWN_RX_STATISTICS: return "RX_STATS"; 349 case IWN_BEACON_STATISTICS: return "BEACON_STATS"; 350 case IWN_STATE_CHANGED: return "STATE_CHANGED"; 351 case IWN_BEACON_MISSED: return "BEACON_MISSED"; 352 case IWN_RX_PHY: return "RX_PHY"; 353 case IWN_MPDU_RX_DONE: return "MPDU_RX_DONE"; 354 case IWN_RX_DONE: return "RX_DONE"; 355 356 /* Command Notifications */ 357 case IWN_CMD_RXON: return "IWN_CMD_RXON"; 358 case IWN_CMD_RXON_ASSOC: return "IWN_CMD_RXON_ASSOC"; 359 case IWN_CMD_EDCA_PARAMS: return "IWN_CMD_EDCA_PARAMS"; 360 case IWN_CMD_TIMING: return "IWN_CMD_TIMING"; 361 case IWN_CMD_LINK_QUALITY: return "IWN_CMD_LINK_QUALITY"; 362 case IWN_CMD_SET_LED: return "IWN_CMD_SET_LED"; 363 case IWN5000_CMD_WIMAX_COEX: return "IWN5000_CMD_WIMAX_COEX"; 364 case IWN5000_CMD_CALIB_CONFIG: return "IWN5000_CMD_CALIB_CONFIG"; 365 case IWN5000_CMD_CALIB_RESULT: return "IWN5000_CMD_CALIB_RESULT"; 366 case IWN5000_CMD_CALIB_COMPLETE: return "IWN5000_CMD_CALIB_COMPLETE"; 367 case IWN_CMD_SET_POWER_MODE: return "IWN_CMD_SET_POWER_MODE"; 368 case IWN_CMD_SCAN: return "IWN_CMD_SCAN"; 369 case IWN_CMD_SCAN_RESULTS: return "IWN_CMD_SCAN_RESULTS"; 370 case IWN_CMD_TXPOWER: return "IWN_CMD_TXPOWER"; 371 case IWN_CMD_TXPOWER_DBM: return "IWN_CMD_TXPOWER_DBM"; 372 case IWN5000_CMD_TX_ANT_CONFIG: return "IWN5000_CMD_TX_ANT_CONFIG"; 373 case IWN_CMD_BT_COEX: return "IWN_CMD_BT_COEX"; 374 case IWN_CMD_SET_CRITICAL_TEMP: return "IWN_CMD_SET_CRITICAL_TEMP"; 375 case IWN_CMD_SET_SENSITIVITY: return "IWN_CMD_SET_SENSITIVITY"; 376 case IWN_CMD_PHY_CALIB: return "IWN_CMD_PHY_CALIB"; 377 } 378 return "UNKNOWN INTR NOTIF/CMD"; 379 } 380 #else 381 #define DPRINTF(sc, m, fmt, ...) do { (void) sc; } while (0) 382 #endif 383 384 static device_method_t iwn_methods[] = { 385 /* Device interface */ 386 DEVMETHOD(device_probe, iwn_probe), 387 DEVMETHOD(device_attach, iwn_attach), 388 DEVMETHOD(device_detach, iwn_detach), 389 DEVMETHOD(device_shutdown, iwn_shutdown), 390 DEVMETHOD(device_suspend, iwn_suspend), 391 DEVMETHOD(device_resume, iwn_resume), 392 { 0, 0 } 393 }; 394 395 static driver_t iwn_driver = { 396 "iwn", 397 iwn_methods, 398 sizeof(struct iwn_softc) 399 }; 400 static devclass_t iwn_devclass; 401 402 DRIVER_MODULE(iwn, pci, iwn_driver, iwn_devclass, 0, 0); 403 404 MODULE_DEPEND(iwn, firmware, 1, 1, 1); 405 MODULE_DEPEND(iwn, pci, 1, 1, 1); 406 MODULE_DEPEND(iwn, wlan, 1, 1, 1); 407 408 static int 409 iwn_probe(device_t dev) 410 { 411 const struct iwn_ident *ident; 412 413 for (ident = iwn_ident_table; ident->name != NULL; ident++) { 414 if (pci_get_vendor(dev) == ident->vendor && 415 pci_get_device(dev) == ident->device) { 416 device_set_desc(dev, ident->name); 417 return 0; 418 } 419 } 420 return ENXIO; 421 } 422 423 static int 424 iwn_attach(device_t dev) 425 { 426 struct iwn_softc *sc = (struct iwn_softc *)device_get_softc(dev); 427 struct ieee80211com *ic; 428 struct ifnet *ifp; 429 uint32_t reg; 430 int i, error, result; 431 uint8_t macaddr[IEEE80211_ADDR_LEN]; 432 433 sc->sc_dev = dev; 434 435 /* 436 * Get the offset of the PCI Express Capability Structure in PCI 437 * Configuration Space. 438 */ 439 error = pci_find_cap(dev, PCIY_EXPRESS, &sc->sc_cap_off); 440 if (error != 0) { 441 device_printf(dev, "PCIe capability structure not found!\n"); 442 return error; 443 } 444 445 /* Clear device-specific "PCI retry timeout" register (41h). */ 446 pci_write_config(dev, 0x41, 0, 1); 447 448 /* Hardware bug workaround. */ 449 reg = pci_read_config(dev, PCIR_COMMAND, 1); 450 if (reg & PCIM_CMD_INTxDIS) { 451 DPRINTF(sc, IWN_DEBUG_RESET, "%s: PCIe INTx Disable set\n", 452 __func__); 453 reg &= ~PCIM_CMD_INTxDIS; 454 pci_write_config(dev, PCIR_COMMAND, reg, 1); 455 } 456 457 /* Enable bus-mastering. */ 458 pci_enable_busmaster(dev); 459 460 sc->mem_rid = PCIR_BAR(0); 461 sc->mem = bus_alloc_resource_any(dev, SYS_RES_MEMORY, &sc->mem_rid, 462 RF_ACTIVE); 463 if (sc->mem == NULL) { 464 device_printf(dev, "can't map mem space\n"); 465 error = ENOMEM; 466 return error; 467 } 468 sc->sc_st = rman_get_bustag(sc->mem); 469 sc->sc_sh = rman_get_bushandle(sc->mem); 470 471 sc->irq_rid = 0; 472 if ((result = pci_msi_count(dev)) == 1 && 473 pci_alloc_msi(dev, &result) == 0) 474 sc->irq_rid = 1; 475 /* Install interrupt handler. */ 476 sc->irq = bus_alloc_resource_any(dev, SYS_RES_IRQ, &sc->irq_rid, 477 RF_ACTIVE | RF_SHAREABLE); 478 if (sc->irq == NULL) { 479 device_printf(dev, "can't map interrupt\n"); 480 error = ENOMEM; 481 goto fail; 482 } 483 484 IWN_LOCK_INIT(sc); 485 486 /* Read hardware revision and attach. */ 487 sc->hw_type = (IWN_READ(sc, IWN_HW_REV) >> 4) & 0xf; 488 if (sc->hw_type == IWN_HW_REV_TYPE_4965) 489 error = iwn4965_attach(sc, pci_get_device(dev)); 490 else 491 error = iwn5000_attach(sc, pci_get_device(dev)); 492 if (error != 0) { 493 device_printf(dev, "could not attach device, error %d\n", 494 error); 495 goto fail; 496 } 497 498 if ((error = iwn_hw_prepare(sc)) != 0) { 499 device_printf(dev, "hardware not ready, error %d\n", error); 500 goto fail; 501 } 502 503 /* Allocate DMA memory for firmware transfers. */ 504 if ((error = iwn_alloc_fwmem(sc)) != 0) { 505 device_printf(dev, 506 "could not allocate memory for firmware, error %d\n", 507 error); 508 goto fail; 509 } 510 511 /* Allocate "Keep Warm" page. */ 512 if ((error = iwn_alloc_kw(sc)) != 0) { 513 device_printf(dev, 514 "could not allocate keep warm page, error %d\n", error); 515 goto fail; 516 } 517 518 /* Allocate ICT table for 5000 Series. */ 519 if (sc->hw_type != IWN_HW_REV_TYPE_4965 && 520 (error = iwn_alloc_ict(sc)) != 0) { 521 device_printf(dev, "could not allocate ICT table, error %d\n", 522 error); 523 goto fail; 524 } 525 526 /* Allocate TX scheduler "rings". */ 527 if ((error = iwn_alloc_sched(sc)) != 0) { 528 device_printf(dev, 529 "could not allocate TX scheduler rings, error %d\n", error); 530 goto fail; 531 } 532 533 /* Allocate TX rings (16 on 4965AGN, 20 on >=5000). */ 534 for (i = 0; i < sc->ntxqs; i++) { 535 if ((error = iwn_alloc_tx_ring(sc, &sc->txq[i], i)) != 0) { 536 device_printf(dev, 537 "could not allocate TX ring %d, error %d\n", i, 538 error); 539 goto fail; 540 } 541 } 542 543 /* Allocate RX ring. */ 544 if ((error = iwn_alloc_rx_ring(sc, &sc->rxq)) != 0) { 545 device_printf(dev, "could not allocate RX ring, error %d\n", 546 error); 547 goto fail; 548 } 549 550 /* Clear pending interrupts. */ 551 IWN_WRITE(sc, IWN_INT, 0xffffffff); 552 553 /* Count the number of available chains. */ 554 sc->ntxchains = 555 ((sc->txchainmask >> 2) & 1) + 556 ((sc->txchainmask >> 1) & 1) + 557 ((sc->txchainmask >> 0) & 1); 558 sc->nrxchains = 559 ((sc->rxchainmask >> 2) & 1) + 560 ((sc->rxchainmask >> 1) & 1) + 561 ((sc->rxchainmask >> 0) & 1); 562 if (bootverbose) { 563 device_printf(dev, "MIMO %dT%dR, %.4s, address %6D\n", 564 sc->ntxchains, sc->nrxchains, sc->eeprom_domain, 565 macaddr, ":"); 566 } 567 568 ifp = sc->sc_ifp = if_alloc(IFT_IEEE80211); 569 if (ifp == NULL) { 570 device_printf(dev, "can not allocate ifnet structure\n"); 571 goto fail; 572 } 573 574 ic = ifp->if_l2com; 575 ic->ic_ifp = ifp; 576 ic->ic_phytype = IEEE80211_T_OFDM; /* not only, but not used */ 577 ic->ic_opmode = IEEE80211_M_STA; /* default to BSS mode */ 578 579 /* Set device capabilities. */ 580 ic->ic_caps = 581 IEEE80211_C_STA /* station mode supported */ 582 | IEEE80211_C_MONITOR /* monitor mode supported */ 583 | IEEE80211_C_TXPMGT /* tx power management */ 584 | IEEE80211_C_SHSLOT /* short slot time supported */ 585 | IEEE80211_C_WPA 586 | IEEE80211_C_SHPREAMBLE /* short preamble supported */ 587 | IEEE80211_C_BGSCAN /* background scanning */ 588 #if 0 589 | IEEE80211_C_IBSS /* ibss/adhoc mode */ 590 #endif 591 | IEEE80211_C_WME /* WME */ 592 ; 593 #if 0 /* HT */ 594 /* XXX disable until HT channel setup works */ 595 ic->ic_htcaps = 596 IEEE80211_HTCAP_SMPS_ENA /* SM PS mode enabled */ 597 | IEEE80211_HTCAP_CHWIDTH40 /* 40MHz channel width */ 598 | IEEE80211_HTCAP_SHORTGI20 /* short GI in 20MHz */ 599 | IEEE80211_HTCAP_SHORTGI40 /* short GI in 40MHz */ 600 | IEEE80211_HTCAP_RXSTBC_2STREAM/* 1-2 spatial streams */ 601 | IEEE80211_HTCAP_MAXAMSDU_3839 /* max A-MSDU length */ 602 /* s/w capabilities */ 603 | IEEE80211_HTC_HT /* HT operation */ 604 | IEEE80211_HTC_AMPDU /* tx A-MPDU */ 605 | IEEE80211_HTC_AMSDU /* tx A-MSDU */ 606 ; 607 608 /* Set HT capabilities. */ 609 ic->ic_htcaps = 610 #if IWN_RBUF_SIZE == 8192 611 IEEE80211_HTCAP_AMSDU7935 | 612 #endif 613 IEEE80211_HTCAP_CBW20_40 | 614 IEEE80211_HTCAP_SGI20 | 615 IEEE80211_HTCAP_SGI40; 616 if (sc->hw_type != IWN_HW_REV_TYPE_4965) 617 ic->ic_htcaps |= IEEE80211_HTCAP_GF; 618 if (sc->hw_type == IWN_HW_REV_TYPE_6050) 619 ic->ic_htcaps |= IEEE80211_HTCAP_SMPS_DYN; 620 else 621 ic->ic_htcaps |= IEEE80211_HTCAP_SMPS_DIS; 622 #endif 623 624 /* Read MAC address, channels, etc from EEPROM. */ 625 if ((error = iwn_read_eeprom(sc, macaddr)) != 0) { 626 device_printf(dev, "could not read EEPROM, error %d\n", 627 error); 628 goto fail; 629 } 630 631 #if 0 /* HT */ 632 /* Set supported HT rates. */ 633 ic->ic_sup_mcs[0] = 0xff; 634 if (sc->nrxchains > 1) 635 ic->ic_sup_mcs[1] = 0xff; 636 if (sc->nrxchains > 2) 637 ic->ic_sup_mcs[2] = 0xff; 638 #endif 639 640 if_initname(ifp, device_get_name(dev), device_get_unit(dev)); 641 ifp->if_softc = sc; 642 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 643 ifp->if_init = iwn_init; 644 ifp->if_ioctl = iwn_ioctl; 645 ifp->if_start = iwn_start; 646 IFQ_SET_MAXLEN(&ifp->if_snd, ifqmaxlen); 647 ifp->if_snd.ifq_drv_maxlen = ifqmaxlen; 648 IFQ_SET_READY(&ifp->if_snd); 649 650 ieee80211_ifattach(ic, macaddr); 651 ic->ic_vap_create = iwn_vap_create; 652 ic->ic_vap_delete = iwn_vap_delete; 653 ic->ic_raw_xmit = iwn_raw_xmit; 654 ic->ic_node_alloc = iwn_node_alloc; 655 #if 0 /* HT */ 656 ic->ic_ampdu_rx_start = iwn_ampdu_rx_start; 657 ic->ic_ampdu_rx_stop = iwn_ampdu_rx_stop; 658 ic->ic_ampdu_tx_start = iwn_ampdu_tx_start; 659 ic->ic_ampdu_tx_stop = iwn_ampdu_tx_stop; 660 #endif 661 ic->ic_newassoc = iwn_newassoc; 662 ic->ic_wme.wme_update = iwn_updateedca; 663 ic->ic_update_mcast = iwn_update_mcast; 664 ic->ic_scan_start = iwn_scan_start; 665 ic->ic_scan_end = iwn_scan_end; 666 ic->ic_set_channel = iwn_set_channel; 667 ic->ic_scan_curchan = iwn_scan_curchan; 668 ic->ic_scan_mindwell = iwn_scan_mindwell; 669 ic->ic_setregdomain = iwn_setregdomain; 670 671 iwn_radiotap_attach(sc); 672 673 callout_init_mtx(&sc->calib_to, &sc->sc_mtx, 0); 674 callout_init_mtx(&sc->watchdog_to, &sc->sc_mtx, 0); 675 TASK_INIT(&sc->sc_reinit_task, 0, iwn_hw_reset, sc); 676 TASK_INIT(&sc->sc_radioon_task, 0, iwn_radio_on, sc); 677 TASK_INIT(&sc->sc_radiooff_task, 0, iwn_radio_off, sc); 678 679 iwn_sysctlattach(sc); 680 681 /* 682 * Hook our interrupt after all initialization is complete. 683 */ 684 error = bus_setup_intr(dev, sc->irq, INTR_TYPE_NET | INTR_MPSAFE, 685 NULL, iwn_intr, sc, &sc->sc_ih); 686 if (error != 0) { 687 device_printf(dev, "can't establish interrupt, error %d\n", 688 error); 689 goto fail; 690 } 691 692 if (bootverbose) 693 ieee80211_announce(ic); 694 return 0; 695 fail: 696 iwn_detach(dev); 697 return error; 698 } 699 700 static int 701 iwn4965_attach(struct iwn_softc *sc, uint16_t pid) 702 { 703 struct iwn_ops *ops = &sc->ops; 704 705 ops->load_firmware = iwn4965_load_firmware; 706 ops->read_eeprom = iwn4965_read_eeprom; 707 ops->post_alive = iwn4965_post_alive; 708 ops->nic_config = iwn4965_nic_config; 709 ops->update_sched = iwn4965_update_sched; 710 ops->get_temperature = iwn4965_get_temperature; 711 ops->get_rssi = iwn4965_get_rssi; 712 ops->set_txpower = iwn4965_set_txpower; 713 ops->init_gains = iwn4965_init_gains; 714 ops->set_gains = iwn4965_set_gains; 715 ops->add_node = iwn4965_add_node; 716 ops->tx_done = iwn4965_tx_done; 717 #if 0 /* HT */ 718 ops->ampdu_tx_start = iwn4965_ampdu_tx_start; 719 ops->ampdu_tx_stop = iwn4965_ampdu_tx_stop; 720 #endif 721 sc->ntxqs = IWN4965_NTXQUEUES; 722 sc->ndmachnls = IWN4965_NDMACHNLS; 723 sc->broadcast_id = IWN4965_ID_BROADCAST; 724 sc->rxonsz = IWN4965_RXONSZ; 725 sc->schedsz = IWN4965_SCHEDSZ; 726 sc->fw_text_maxsz = IWN4965_FW_TEXT_MAXSZ; 727 sc->fw_data_maxsz = IWN4965_FW_DATA_MAXSZ; 728 sc->fwsz = IWN4965_FWSZ; 729 sc->sched_txfact_addr = IWN4965_SCHED_TXFACT; 730 sc->limits = &iwn4965_sensitivity_limits; 731 sc->fwname = "iwn4965fw"; 732 /* Override chains masks, ROM is known to be broken. */ 733 sc->txchainmask = IWN_ANT_AB; 734 sc->rxchainmask = IWN_ANT_ABC; 735 736 return 0; 737 } 738 739 static int 740 iwn5000_attach(struct iwn_softc *sc, uint16_t pid) 741 { 742 struct iwn_ops *ops = &sc->ops; 743 744 ops->load_firmware = iwn5000_load_firmware; 745 ops->read_eeprom = iwn5000_read_eeprom; 746 ops->post_alive = iwn5000_post_alive; 747 ops->nic_config = iwn5000_nic_config; 748 ops->update_sched = iwn5000_update_sched; 749 ops->get_temperature = iwn5000_get_temperature; 750 ops->get_rssi = iwn5000_get_rssi; 751 ops->set_txpower = iwn5000_set_txpower; 752 ops->init_gains = iwn5000_init_gains; 753 ops->set_gains = iwn5000_set_gains; 754 ops->add_node = iwn5000_add_node; 755 ops->tx_done = iwn5000_tx_done; 756 #if 0 /* HT */ 757 ops->ampdu_tx_start = iwn5000_ampdu_tx_start; 758 ops->ampdu_tx_stop = iwn5000_ampdu_tx_stop; 759 #endif 760 sc->ntxqs = IWN5000_NTXQUEUES; 761 sc->ndmachnls = IWN5000_NDMACHNLS; 762 sc->broadcast_id = IWN5000_ID_BROADCAST; 763 sc->rxonsz = IWN5000_RXONSZ; 764 sc->schedsz = IWN5000_SCHEDSZ; 765 sc->fw_text_maxsz = IWN5000_FW_TEXT_MAXSZ; 766 sc->fw_data_maxsz = IWN5000_FW_DATA_MAXSZ; 767 sc->fwsz = IWN5000_FWSZ; 768 sc->sched_txfact_addr = IWN5000_SCHED_TXFACT; 769 sc->reset_noise_gain = IWN5000_PHY_CALIB_RESET_NOISE_GAIN; 770 sc->noise_gain = IWN5000_PHY_CALIB_NOISE_GAIN; 771 772 switch (sc->hw_type) { 773 case IWN_HW_REV_TYPE_5100: 774 sc->limits = &iwn5000_sensitivity_limits; 775 sc->fwname = "iwn5000fw"; 776 /* Override chains masks, ROM is known to be broken. */ 777 sc->txchainmask = IWN_ANT_B; 778 sc->rxchainmask = IWN_ANT_AB; 779 break; 780 case IWN_HW_REV_TYPE_5150: 781 sc->limits = &iwn5150_sensitivity_limits; 782 sc->fwname = "iwn5150fw"; 783 break; 784 case IWN_HW_REV_TYPE_5300: 785 case IWN_HW_REV_TYPE_5350: 786 sc->limits = &iwn5000_sensitivity_limits; 787 sc->fwname = "iwn5000fw"; 788 break; 789 case IWN_HW_REV_TYPE_1000: 790 sc->limits = &iwn1000_sensitivity_limits; 791 sc->fwname = "iwn1000fw"; 792 break; 793 case IWN_HW_REV_TYPE_6000: 794 sc->limits = &iwn6000_sensitivity_limits; 795 sc->fwname = "iwn6000fw"; 796 if (pid == 0x422c || pid == 0x4239) { 797 sc->sc_flags |= IWN_FLAG_INTERNAL_PA; 798 /* Override chains masks, ROM is known to be broken. */ 799 sc->txchainmask = IWN_ANT_BC; 800 sc->rxchainmask = IWN_ANT_BC; 801 } 802 break; 803 case IWN_HW_REV_TYPE_6050: 804 sc->limits = &iwn6000_sensitivity_limits; 805 sc->fwname = "iwn6050fw"; 806 /* Override chains masks, ROM is known to be broken. */ 807 sc->txchainmask = IWN_ANT_AB; 808 sc->rxchainmask = IWN_ANT_AB; 809 break; 810 case IWN_HW_REV_TYPE_6005: 811 sc->limits = &iwn6000_sensitivity_limits; 812 if (pid != 0x0082 && pid != 0x0085) { 813 sc->fwname = "iwn6000g2bfw"; 814 sc->sc_flags |= IWN_FLAG_ADV_BTCOEX; 815 } else 816 sc->fwname = "iwn6000g2afw"; 817 break; 818 default: 819 device_printf(sc->sc_dev, "adapter type %d not supported\n", 820 sc->hw_type); 821 return ENOTSUP; 822 } 823 return 0; 824 } 825 826 /* 827 * Attach the interface to 802.11 radiotap. 828 */ 829 static void 830 iwn_radiotap_attach(struct iwn_softc *sc) 831 { 832 struct ifnet *ifp = sc->sc_ifp; 833 struct ieee80211com *ic = ifp->if_l2com; 834 835 ieee80211_radiotap_attach(ic, 836 &sc->sc_txtap.wt_ihdr, sizeof(sc->sc_txtap), 837 IWN_TX_RADIOTAP_PRESENT, 838 &sc->sc_rxtap.wr_ihdr, sizeof(sc->sc_rxtap), 839 IWN_RX_RADIOTAP_PRESENT); 840 } 841 842 static void 843 iwn_sysctlattach(struct iwn_softc *sc) 844 { 845 struct sysctl_ctx_list *ctx = device_get_sysctl_ctx(sc->sc_dev); 846 struct sysctl_oid *tree = device_get_sysctl_tree(sc->sc_dev); 847 848 #ifdef IWN_DEBUG 849 sc->sc_debug = 0; 850 SYSCTL_ADD_INT(ctx, SYSCTL_CHILDREN(tree), OID_AUTO, 851 "debug", CTLFLAG_RW, &sc->sc_debug, 0, "control debugging printfs"); 852 #endif 853 } 854 855 static struct ieee80211vap * 856 iwn_vap_create(struct ieee80211com *ic, 857 const char name[IFNAMSIZ], int unit, int opmode, int flags, 858 const uint8_t bssid[IEEE80211_ADDR_LEN], 859 const uint8_t mac[IEEE80211_ADDR_LEN]) 860 { 861 struct iwn_vap *ivp; 862 struct ieee80211vap *vap; 863 864 if (!TAILQ_EMPTY(&ic->ic_vaps)) /* only one at a time */ 865 return NULL; 866 ivp = (struct iwn_vap *) malloc(sizeof(struct iwn_vap), 867 M_80211_VAP, M_NOWAIT | M_ZERO); 868 if (ivp == NULL) 869 return NULL; 870 vap = &ivp->iv_vap; 871 ieee80211_vap_setup(ic, vap, name, unit, opmode, flags, bssid, mac); 872 vap->iv_bmissthreshold = 10; /* override default */ 873 /* Override with driver methods. */ 874 ivp->iv_newstate = vap->iv_newstate; 875 vap->iv_newstate = iwn_newstate; 876 877 ieee80211_ratectl_init(vap); 878 /* Complete setup. */ 879 ieee80211_vap_attach(vap, iwn_media_change, ieee80211_media_status); 880 ic->ic_opmode = opmode; 881 return vap; 882 } 883 884 static void 885 iwn_vap_delete(struct ieee80211vap *vap) 886 { 887 struct iwn_vap *ivp = IWN_VAP(vap); 888 889 ieee80211_ratectl_deinit(vap); 890 ieee80211_vap_detach(vap); 891 free(ivp, M_80211_VAP); 892 } 893 894 static int 895 iwn_detach(device_t dev) 896 { 897 struct iwn_softc *sc = device_get_softc(dev); 898 struct ifnet *ifp = sc->sc_ifp; 899 struct ieee80211com *ic; 900 int qid; 901 902 if (ifp != NULL) { 903 ic = ifp->if_l2com; 904 905 ieee80211_draintask(ic, &sc->sc_reinit_task); 906 ieee80211_draintask(ic, &sc->sc_radioon_task); 907 ieee80211_draintask(ic, &sc->sc_radiooff_task); 908 909 iwn_stop(sc); 910 callout_drain(&sc->watchdog_to); 911 callout_drain(&sc->calib_to); 912 ieee80211_ifdetach(ic); 913 } 914 915 /* Uninstall interrupt handler. */ 916 if (sc->irq != NULL) { 917 bus_teardown_intr(dev, sc->irq, sc->sc_ih); 918 bus_release_resource(dev, SYS_RES_IRQ, sc->irq_rid, sc->irq); 919 if (sc->irq_rid == 1) 920 pci_release_msi(dev); 921 } 922 923 /* Free DMA resources. */ 924 iwn_free_rx_ring(sc, &sc->rxq); 925 for (qid = 0; qid < sc->ntxqs; qid++) 926 iwn_free_tx_ring(sc, &sc->txq[qid]); 927 iwn_free_sched(sc); 928 iwn_free_kw(sc); 929 if (sc->ict != NULL) 930 iwn_free_ict(sc); 931 iwn_free_fwmem(sc); 932 933 if (sc->mem != NULL) 934 bus_release_resource(dev, SYS_RES_MEMORY, sc->mem_rid, sc->mem); 935 936 if (ifp != NULL) 937 if_free(ifp); 938 939 IWN_LOCK_DESTROY(sc); 940 return 0; 941 } 942 943 static int 944 iwn_shutdown(device_t dev) 945 { 946 struct iwn_softc *sc = device_get_softc(dev); 947 948 iwn_stop(sc); 949 return 0; 950 } 951 952 static int 953 iwn_suspend(device_t dev) 954 { 955 struct iwn_softc *sc = device_get_softc(dev); 956 struct ifnet *ifp = sc->sc_ifp; 957 struct ieee80211com *ic = ifp->if_l2com; 958 struct ieee80211vap *vap = TAILQ_FIRST(&ic->ic_vaps); 959 960 iwn_stop(sc); 961 if (vap != NULL) 962 ieee80211_stop(vap); 963 return 0; 964 } 965 966 static int 967 iwn_resume(device_t dev) 968 { 969 struct iwn_softc *sc = device_get_softc(dev); 970 struct ifnet *ifp = sc->sc_ifp; 971 struct ieee80211com *ic = ifp->if_l2com; 972 struct ieee80211vap *vap = TAILQ_FIRST(&ic->ic_vaps); 973 974 /* Clear device-specific "PCI retry timeout" register (41h). */ 975 pci_write_config(dev, 0x41, 0, 1); 976 977 if (ifp->if_flags & IFF_UP) { 978 iwn_init(sc); 979 if (vap != NULL) 980 ieee80211_init(vap); 981 if (ifp->if_drv_flags & IFF_DRV_RUNNING) 982 iwn_start(ifp); 983 } 984 return 0; 985 } 986 987 static int 988 iwn_nic_lock(struct iwn_softc *sc) 989 { 990 int ntries; 991 992 /* Request exclusive access to NIC. */ 993 IWN_SETBITS(sc, IWN_GP_CNTRL, IWN_GP_CNTRL_MAC_ACCESS_REQ); 994 995 /* Spin until we actually get the lock. */ 996 for (ntries = 0; ntries < 1000; ntries++) { 997 if ((IWN_READ(sc, IWN_GP_CNTRL) & 998 (IWN_GP_CNTRL_MAC_ACCESS_ENA | IWN_GP_CNTRL_SLEEP)) == 999 IWN_GP_CNTRL_MAC_ACCESS_ENA) 1000 return 0; 1001 DELAY(10); 1002 } 1003 return ETIMEDOUT; 1004 } 1005 1006 static __inline void 1007 iwn_nic_unlock(struct iwn_softc *sc) 1008 { 1009 IWN_CLRBITS(sc, IWN_GP_CNTRL, IWN_GP_CNTRL_MAC_ACCESS_REQ); 1010 } 1011 1012 static __inline uint32_t 1013 iwn_prph_read(struct iwn_softc *sc, uint32_t addr) 1014 { 1015 IWN_WRITE(sc, IWN_PRPH_RADDR, IWN_PRPH_DWORD | addr); 1016 IWN_BARRIER_READ_WRITE(sc); 1017 return IWN_READ(sc, IWN_PRPH_RDATA); 1018 } 1019 1020 static __inline void 1021 iwn_prph_write(struct iwn_softc *sc, uint32_t addr, uint32_t data) 1022 { 1023 IWN_WRITE(sc, IWN_PRPH_WADDR, IWN_PRPH_DWORD | addr); 1024 IWN_BARRIER_WRITE(sc); 1025 IWN_WRITE(sc, IWN_PRPH_WDATA, data); 1026 } 1027 1028 static __inline void 1029 iwn_prph_setbits(struct iwn_softc *sc, uint32_t addr, uint32_t mask) 1030 { 1031 iwn_prph_write(sc, addr, iwn_prph_read(sc, addr) | mask); 1032 } 1033 1034 static __inline void 1035 iwn_prph_clrbits(struct iwn_softc *sc, uint32_t addr, uint32_t mask) 1036 { 1037 iwn_prph_write(sc, addr, iwn_prph_read(sc, addr) & ~mask); 1038 } 1039 1040 static __inline void 1041 iwn_prph_write_region_4(struct iwn_softc *sc, uint32_t addr, 1042 const uint32_t *data, int count) 1043 { 1044 for (; count > 0; count--, data++, addr += 4) 1045 iwn_prph_write(sc, addr, *data); 1046 } 1047 1048 static __inline uint32_t 1049 iwn_mem_read(struct iwn_softc *sc, uint32_t addr) 1050 { 1051 IWN_WRITE(sc, IWN_MEM_RADDR, addr); 1052 IWN_BARRIER_READ_WRITE(sc); 1053 return IWN_READ(sc, IWN_MEM_RDATA); 1054 } 1055 1056 static __inline void 1057 iwn_mem_write(struct iwn_softc *sc, uint32_t addr, uint32_t data) 1058 { 1059 IWN_WRITE(sc, IWN_MEM_WADDR, addr); 1060 IWN_BARRIER_WRITE(sc); 1061 IWN_WRITE(sc, IWN_MEM_WDATA, data); 1062 } 1063 1064 static __inline void 1065 iwn_mem_write_2(struct iwn_softc *sc, uint32_t addr, uint16_t data) 1066 { 1067 uint32_t tmp; 1068 1069 tmp = iwn_mem_read(sc, addr & ~3); 1070 if (addr & 3) 1071 tmp = (tmp & 0x0000ffff) | data << 16; 1072 else 1073 tmp = (tmp & 0xffff0000) | data; 1074 iwn_mem_write(sc, addr & ~3, tmp); 1075 } 1076 1077 static __inline void 1078 iwn_mem_read_region_4(struct iwn_softc *sc, uint32_t addr, uint32_t *data, 1079 int count) 1080 { 1081 for (; count > 0; count--, addr += 4) 1082 *data++ = iwn_mem_read(sc, addr); 1083 } 1084 1085 static __inline void 1086 iwn_mem_set_region_4(struct iwn_softc *sc, uint32_t addr, uint32_t val, 1087 int count) 1088 { 1089 for (; count > 0; count--, addr += 4) 1090 iwn_mem_write(sc, addr, val); 1091 } 1092 1093 static int 1094 iwn_eeprom_lock(struct iwn_softc *sc) 1095 { 1096 int i, ntries; 1097 1098 for (i = 0; i < 100; i++) { 1099 /* Request exclusive access to EEPROM. */ 1100 IWN_SETBITS(sc, IWN_HW_IF_CONFIG, 1101 IWN_HW_IF_CONFIG_EEPROM_LOCKED); 1102 1103 /* Spin until we actually get the lock. */ 1104 for (ntries = 0; ntries < 100; ntries++) { 1105 if (IWN_READ(sc, IWN_HW_IF_CONFIG) & 1106 IWN_HW_IF_CONFIG_EEPROM_LOCKED) 1107 return 0; 1108 DELAY(10); 1109 } 1110 } 1111 return ETIMEDOUT; 1112 } 1113 1114 static __inline void 1115 iwn_eeprom_unlock(struct iwn_softc *sc) 1116 { 1117 IWN_CLRBITS(sc, IWN_HW_IF_CONFIG, IWN_HW_IF_CONFIG_EEPROM_LOCKED); 1118 } 1119 1120 /* 1121 * Initialize access by host to One Time Programmable ROM. 1122 * NB: This kind of ROM can be found on 1000 or 6000 Series only. 1123 */ 1124 static int 1125 iwn_init_otprom(struct iwn_softc *sc) 1126 { 1127 uint16_t prev, base, next; 1128 int count, error; 1129 1130 /* Wait for clock stabilization before accessing prph. */ 1131 if ((error = iwn_clock_wait(sc)) != 0) 1132 return error; 1133 1134 if ((error = iwn_nic_lock(sc)) != 0) 1135 return error; 1136 iwn_prph_setbits(sc, IWN_APMG_PS, IWN_APMG_PS_RESET_REQ); 1137 DELAY(5); 1138 iwn_prph_clrbits(sc, IWN_APMG_PS, IWN_APMG_PS_RESET_REQ); 1139 iwn_nic_unlock(sc); 1140 1141 /* Set auto clock gate disable bit for HW with OTP shadow RAM. */ 1142 if (sc->hw_type != IWN_HW_REV_TYPE_1000) { 1143 IWN_SETBITS(sc, IWN_DBG_LINK_PWR_MGMT, 1144 IWN_RESET_LINK_PWR_MGMT_DIS); 1145 } 1146 IWN_CLRBITS(sc, IWN_EEPROM_GP, IWN_EEPROM_GP_IF_OWNER); 1147 /* Clear ECC status. */ 1148 IWN_SETBITS(sc, IWN_OTP_GP, 1149 IWN_OTP_GP_ECC_CORR_STTS | IWN_OTP_GP_ECC_UNCORR_STTS); 1150 1151 /* 1152 * Find the block before last block (contains the EEPROM image) 1153 * for HW without OTP shadow RAM. 1154 */ 1155 if (sc->hw_type == IWN_HW_REV_TYPE_1000) { 1156 /* Switch to absolute addressing mode. */ 1157 IWN_CLRBITS(sc, IWN_OTP_GP, IWN_OTP_GP_RELATIVE_ACCESS); 1158 base = prev = 0; 1159 for (count = 0; count < IWN1000_OTP_NBLOCKS; count++) { 1160 error = iwn_read_prom_data(sc, base, &next, 2); 1161 if (error != 0) 1162 return error; 1163 if (next == 0) /* End of linked-list. */ 1164 break; 1165 prev = base; 1166 base = le16toh(next); 1167 } 1168 if (count == 0 || count == IWN1000_OTP_NBLOCKS) 1169 return EIO; 1170 /* Skip "next" word. */ 1171 sc->prom_base = prev + 1; 1172 } 1173 return 0; 1174 } 1175 1176 static int 1177 iwn_read_prom_data(struct iwn_softc *sc, uint32_t addr, void *data, int count) 1178 { 1179 uint8_t *out = data; 1180 uint32_t val, tmp; 1181 int ntries; 1182 1183 addr += sc->prom_base; 1184 for (; count > 0; count -= 2, addr++) { 1185 IWN_WRITE(sc, IWN_EEPROM, addr << 2); 1186 for (ntries = 0; ntries < 10; ntries++) { 1187 val = IWN_READ(sc, IWN_EEPROM); 1188 if (val & IWN_EEPROM_READ_VALID) 1189 break; 1190 DELAY(5); 1191 } 1192 if (ntries == 10) { 1193 device_printf(sc->sc_dev, 1194 "timeout reading ROM at 0x%x\n", addr); 1195 return ETIMEDOUT; 1196 } 1197 if (sc->sc_flags & IWN_FLAG_HAS_OTPROM) { 1198 /* OTPROM, check for ECC errors. */ 1199 tmp = IWN_READ(sc, IWN_OTP_GP); 1200 if (tmp & IWN_OTP_GP_ECC_UNCORR_STTS) { 1201 device_printf(sc->sc_dev, 1202 "OTPROM ECC error at 0x%x\n", addr); 1203 return EIO; 1204 } 1205 if (tmp & IWN_OTP_GP_ECC_CORR_STTS) { 1206 /* Correctable ECC error, clear bit. */ 1207 IWN_SETBITS(sc, IWN_OTP_GP, 1208 IWN_OTP_GP_ECC_CORR_STTS); 1209 } 1210 } 1211 *out++ = val >> 16; 1212 if (count > 1) 1213 *out++ = val >> 24; 1214 } 1215 return 0; 1216 } 1217 1218 static void 1219 iwn_dma_map_addr(void *arg, bus_dma_segment_t *segs, int nsegs, int error) 1220 { 1221 if (error != 0) 1222 return; 1223 KASSERT(nsegs == 1, ("too many DMA segments, %d should be 1", nsegs)); 1224 *(bus_addr_t *)arg = segs[0].ds_addr; 1225 } 1226 1227 static int 1228 iwn_dma_contig_alloc(struct iwn_softc *sc, struct iwn_dma_info *dma, 1229 void **kvap, bus_size_t size, bus_size_t alignment) 1230 { 1231 int error; 1232 1233 dma->tag = NULL; 1234 dma->size = size; 1235 1236 error = bus_dma_tag_create(bus_get_dma_tag(sc->sc_dev), alignment, 1237 0, BUS_SPACE_MAXADDR_32BIT, BUS_SPACE_MAXADDR, NULL, NULL, size, 1238 1, size, BUS_DMA_NOWAIT, NULL, NULL, &dma->tag); 1239 if (error != 0) 1240 goto fail; 1241 1242 error = bus_dmamem_alloc(dma->tag, (void **)&dma->vaddr, 1243 BUS_DMA_NOWAIT | BUS_DMA_ZERO | BUS_DMA_COHERENT, &dma->map); 1244 if (error != 0) 1245 goto fail; 1246 1247 error = bus_dmamap_load(dma->tag, dma->map, dma->vaddr, size, 1248 iwn_dma_map_addr, &dma->paddr, BUS_DMA_NOWAIT); 1249 if (error != 0) 1250 goto fail; 1251 1252 bus_dmamap_sync(dma->tag, dma->map, BUS_DMASYNC_PREWRITE); 1253 1254 if (kvap != NULL) 1255 *kvap = dma->vaddr; 1256 1257 return 0; 1258 1259 fail: iwn_dma_contig_free(dma); 1260 return error; 1261 } 1262 1263 static void 1264 iwn_dma_contig_free(struct iwn_dma_info *dma) 1265 { 1266 if (dma->map != NULL) { 1267 if (dma->vaddr != NULL) { 1268 bus_dmamap_sync(dma->tag, dma->map, 1269 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); 1270 bus_dmamap_unload(dma->tag, dma->map); 1271 bus_dmamem_free(dma->tag, &dma->vaddr, dma->map); 1272 dma->vaddr = NULL; 1273 } 1274 bus_dmamap_destroy(dma->tag, dma->map); 1275 dma->map = NULL; 1276 } 1277 if (dma->tag != NULL) { 1278 bus_dma_tag_destroy(dma->tag); 1279 dma->tag = NULL; 1280 } 1281 } 1282 1283 static int 1284 iwn_alloc_sched(struct iwn_softc *sc) 1285 { 1286 /* TX scheduler rings must be aligned on a 1KB boundary. */ 1287 return iwn_dma_contig_alloc(sc, &sc->sched_dma, (void **)&sc->sched, 1288 sc->schedsz, 1024); 1289 } 1290 1291 static void 1292 iwn_free_sched(struct iwn_softc *sc) 1293 { 1294 iwn_dma_contig_free(&sc->sched_dma); 1295 } 1296 1297 static int 1298 iwn_alloc_kw(struct iwn_softc *sc) 1299 { 1300 /* "Keep Warm" page must be aligned on a 4KB boundary. */ 1301 return iwn_dma_contig_alloc(sc, &sc->kw_dma, NULL, 4096, 4096); 1302 } 1303 1304 static void 1305 iwn_free_kw(struct iwn_softc *sc) 1306 { 1307 iwn_dma_contig_free(&sc->kw_dma); 1308 } 1309 1310 static int 1311 iwn_alloc_ict(struct iwn_softc *sc) 1312 { 1313 /* ICT table must be aligned on a 4KB boundary. */ 1314 return iwn_dma_contig_alloc(sc, &sc->ict_dma, (void **)&sc->ict, 1315 IWN_ICT_SIZE, 4096); 1316 } 1317 1318 static void 1319 iwn_free_ict(struct iwn_softc *sc) 1320 { 1321 iwn_dma_contig_free(&sc->ict_dma); 1322 } 1323 1324 static int 1325 iwn_alloc_fwmem(struct iwn_softc *sc) 1326 { 1327 /* Must be aligned on a 16-byte boundary. */ 1328 return iwn_dma_contig_alloc(sc, &sc->fw_dma, NULL, sc->fwsz, 16); 1329 } 1330 1331 static void 1332 iwn_free_fwmem(struct iwn_softc *sc) 1333 { 1334 iwn_dma_contig_free(&sc->fw_dma); 1335 } 1336 1337 static int 1338 iwn_alloc_rx_ring(struct iwn_softc *sc, struct iwn_rx_ring *ring) 1339 { 1340 bus_size_t size; 1341 int i, error; 1342 1343 ring->cur = 0; 1344 1345 /* Allocate RX descriptors (256-byte aligned). */ 1346 size = IWN_RX_RING_COUNT * sizeof (uint32_t); 1347 error = iwn_dma_contig_alloc(sc, &ring->desc_dma, (void **)&ring->desc, 1348 size, 256); 1349 if (error != 0) { 1350 device_printf(sc->sc_dev, 1351 "%s: could not allocate RX ring DMA memory, error %d\n", 1352 __func__, error); 1353 goto fail; 1354 } 1355 1356 /* Allocate RX status area (16-byte aligned). */ 1357 error = iwn_dma_contig_alloc(sc, &ring->stat_dma, (void **)&ring->stat, 1358 sizeof (struct iwn_rx_status), 16); 1359 if (error != 0) { 1360 device_printf(sc->sc_dev, 1361 "%s: could not allocate RX status DMA memory, error %d\n", 1362 __func__, error); 1363 goto fail; 1364 } 1365 1366 /* Create RX buffer DMA tag. */ 1367 error = bus_dma_tag_create(bus_get_dma_tag(sc->sc_dev), 1, 0, 1368 BUS_SPACE_MAXADDR_32BIT, BUS_SPACE_MAXADDR, NULL, NULL, 1369 IWN_RBUF_SIZE, 1, IWN_RBUF_SIZE, BUS_DMA_NOWAIT, NULL, NULL, 1370 &ring->data_dmat); 1371 if (error != 0) { 1372 device_printf(sc->sc_dev, 1373 "%s: could not create RX buf DMA tag, error %d\n", 1374 __func__, error); 1375 goto fail; 1376 } 1377 1378 /* 1379 * Allocate and map RX buffers. 1380 */ 1381 for (i = 0; i < IWN_RX_RING_COUNT; i++) { 1382 struct iwn_rx_data *data = &ring->data[i]; 1383 bus_addr_t paddr; 1384 1385 error = bus_dmamap_create(ring->data_dmat, 0, &data->map); 1386 if (error != 0) { 1387 device_printf(sc->sc_dev, 1388 "%s: could not create RX buf DMA map, error %d\n", 1389 __func__, error); 1390 goto fail; 1391 } 1392 1393 data->m = m_getjcl(M_DONTWAIT, MT_DATA, M_PKTHDR, 1394 IWN_RBUF_SIZE); 1395 if (data->m == NULL) { 1396 device_printf(sc->sc_dev, 1397 "%s: could not allocate RX mbuf\n", __func__); 1398 error = ENOBUFS; 1399 goto fail; 1400 } 1401 1402 error = bus_dmamap_load(ring->data_dmat, data->map, 1403 mtod(data->m, void *), IWN_RBUF_SIZE, iwn_dma_map_addr, 1404 &paddr, BUS_DMA_NOWAIT); 1405 if (error != 0 && error != EFBIG) { 1406 device_printf(sc->sc_dev, 1407 "%s: can't not map mbuf, error %d\n", __func__, 1408 error); 1409 goto fail; 1410 } 1411 1412 /* Set physical address of RX buffer (256-byte aligned). */ 1413 ring->desc[i] = htole32(paddr >> 8); 1414 } 1415 1416 bus_dmamap_sync(ring->desc_dma.tag, ring->desc_dma.map, 1417 BUS_DMASYNC_PREWRITE); 1418 1419 return 0; 1420 1421 fail: iwn_free_rx_ring(sc, ring); 1422 return error; 1423 } 1424 1425 static void 1426 iwn_reset_rx_ring(struct iwn_softc *sc, struct iwn_rx_ring *ring) 1427 { 1428 int ntries; 1429 1430 if (iwn_nic_lock(sc) == 0) { 1431 IWN_WRITE(sc, IWN_FH_RX_CONFIG, 0); 1432 for (ntries = 0; ntries < 1000; ntries++) { 1433 if (IWN_READ(sc, IWN_FH_RX_STATUS) & 1434 IWN_FH_RX_STATUS_IDLE) 1435 break; 1436 DELAY(10); 1437 } 1438 iwn_nic_unlock(sc); 1439 } 1440 ring->cur = 0; 1441 sc->last_rx_valid = 0; 1442 } 1443 1444 static void 1445 iwn_free_rx_ring(struct iwn_softc *sc, struct iwn_rx_ring *ring) 1446 { 1447 int i; 1448 1449 iwn_dma_contig_free(&ring->desc_dma); 1450 iwn_dma_contig_free(&ring->stat_dma); 1451 1452 for (i = 0; i < IWN_RX_RING_COUNT; i++) { 1453 struct iwn_rx_data *data = &ring->data[i]; 1454 1455 if (data->m != NULL) { 1456 bus_dmamap_sync(ring->data_dmat, data->map, 1457 BUS_DMASYNC_POSTREAD); 1458 bus_dmamap_unload(ring->data_dmat, data->map); 1459 m_freem(data->m); 1460 data->m = NULL; 1461 } 1462 if (data->map != NULL) 1463 bus_dmamap_destroy(ring->data_dmat, data->map); 1464 } 1465 if (ring->data_dmat != NULL) { 1466 bus_dma_tag_destroy(ring->data_dmat); 1467 ring->data_dmat = NULL; 1468 } 1469 } 1470 1471 static int 1472 iwn_alloc_tx_ring(struct iwn_softc *sc, struct iwn_tx_ring *ring, int qid) 1473 { 1474 bus_addr_t paddr; 1475 bus_size_t size; 1476 int i, error; 1477 1478 ring->qid = qid; 1479 ring->queued = 0; 1480 ring->cur = 0; 1481 1482 /* Allocate TX descriptors (256-byte aligned). */ 1483 size = IWN_TX_RING_COUNT * sizeof (struct iwn_tx_desc); 1484 error = iwn_dma_contig_alloc(sc, &ring->desc_dma, (void **)&ring->desc, 1485 size, 256); 1486 if (error != 0) { 1487 device_printf(sc->sc_dev, 1488 "%s: could not allocate TX ring DMA memory, error %d\n", 1489 __func__, error); 1490 goto fail; 1491 } 1492 /* 1493 * We only use rings 0 through 4 (4 EDCA + cmd) so there is no need 1494 * to allocate commands space for other rings. 1495 * XXX Do we really need to allocate descriptors for other rings? 1496 */ 1497 if (qid > 4) 1498 return 0; 1499 1500 size = IWN_TX_RING_COUNT * sizeof (struct iwn_tx_cmd); 1501 error = iwn_dma_contig_alloc(sc, &ring->cmd_dma, (void **)&ring->cmd, 1502 size, 4); 1503 if (error != 0) { 1504 device_printf(sc->sc_dev, 1505 "%s: could not allocate TX cmd DMA memory, error %d\n", 1506 __func__, error); 1507 goto fail; 1508 } 1509 1510 error = bus_dma_tag_create(bus_get_dma_tag(sc->sc_dev), 1, 0, 1511 BUS_SPACE_MAXADDR_32BIT, BUS_SPACE_MAXADDR, NULL, NULL, MCLBYTES, 1512 IWN_MAX_SCATTER - 1, MCLBYTES, BUS_DMA_NOWAIT, NULL, NULL, 1513 &ring->data_dmat); 1514 if (error != 0) { 1515 device_printf(sc->sc_dev, 1516 "%s: could not create TX buf DMA tag, error %d\n", 1517 __func__, error); 1518 goto fail; 1519 } 1520 1521 paddr = ring->cmd_dma.paddr; 1522 for (i = 0; i < IWN_TX_RING_COUNT; i++) { 1523 struct iwn_tx_data *data = &ring->data[i]; 1524 1525 data->cmd_paddr = paddr; 1526 data->scratch_paddr = paddr + 12; 1527 paddr += sizeof (struct iwn_tx_cmd); 1528 1529 error = bus_dmamap_create(ring->data_dmat, 0, &data->map); 1530 if (error != 0) { 1531 device_printf(sc->sc_dev, 1532 "%s: could not create TX buf DMA map, error %d\n", 1533 __func__, error); 1534 goto fail; 1535 } 1536 } 1537 return 0; 1538 1539 fail: iwn_free_tx_ring(sc, ring); 1540 return error; 1541 } 1542 1543 static void 1544 iwn_reset_tx_ring(struct iwn_softc *sc, struct iwn_tx_ring *ring) 1545 { 1546 int i; 1547 1548 for (i = 0; i < IWN_TX_RING_COUNT; i++) { 1549 struct iwn_tx_data *data = &ring->data[i]; 1550 1551 if (data->m != NULL) { 1552 bus_dmamap_sync(ring->data_dmat, data->map, 1553 BUS_DMASYNC_POSTWRITE); 1554 bus_dmamap_unload(ring->data_dmat, data->map); 1555 m_freem(data->m); 1556 data->m = NULL; 1557 } 1558 } 1559 /* Clear TX descriptors. */ 1560 memset(ring->desc, 0, ring->desc_dma.size); 1561 bus_dmamap_sync(ring->desc_dma.tag, ring->desc_dma.map, 1562 BUS_DMASYNC_PREWRITE); 1563 sc->qfullmsk &= ~(1 << ring->qid); 1564 ring->queued = 0; 1565 ring->cur = 0; 1566 } 1567 1568 static void 1569 iwn_free_tx_ring(struct iwn_softc *sc, struct iwn_tx_ring *ring) 1570 { 1571 int i; 1572 1573 iwn_dma_contig_free(&ring->desc_dma); 1574 iwn_dma_contig_free(&ring->cmd_dma); 1575 1576 for (i = 0; i < IWN_TX_RING_COUNT; i++) { 1577 struct iwn_tx_data *data = &ring->data[i]; 1578 1579 if (data->m != NULL) { 1580 bus_dmamap_sync(ring->data_dmat, data->map, 1581 BUS_DMASYNC_POSTWRITE); 1582 bus_dmamap_unload(ring->data_dmat, data->map); 1583 m_freem(data->m); 1584 } 1585 if (data->map != NULL) 1586 bus_dmamap_destroy(ring->data_dmat, data->map); 1587 } 1588 if (ring->data_dmat != NULL) { 1589 bus_dma_tag_destroy(ring->data_dmat); 1590 ring->data_dmat = NULL; 1591 } 1592 } 1593 1594 static void 1595 iwn5000_ict_reset(struct iwn_softc *sc) 1596 { 1597 /* Disable interrupts. */ 1598 IWN_WRITE(sc, IWN_INT_MASK, 0); 1599 1600 /* Reset ICT table. */ 1601 memset(sc->ict, 0, IWN_ICT_SIZE); 1602 sc->ict_cur = 0; 1603 1604 /* Set physical address of ICT table (4KB aligned). */ 1605 DPRINTF(sc, IWN_DEBUG_RESET, "%s: enabling ICT\n", __func__); 1606 IWN_WRITE(sc, IWN_DRAM_INT_TBL, IWN_DRAM_INT_TBL_ENABLE | 1607 IWN_DRAM_INT_TBL_WRAP_CHECK | sc->ict_dma.paddr >> 12); 1608 1609 /* Enable periodic RX interrupt. */ 1610 sc->int_mask |= IWN_INT_RX_PERIODIC; 1611 /* Switch to ICT interrupt mode in driver. */ 1612 sc->sc_flags |= IWN_FLAG_USE_ICT; 1613 1614 /* Re-enable interrupts. */ 1615 IWN_WRITE(sc, IWN_INT, 0xffffffff); 1616 IWN_WRITE(sc, IWN_INT_MASK, sc->int_mask); 1617 } 1618 1619 static int 1620 iwn_read_eeprom(struct iwn_softc *sc, uint8_t macaddr[IEEE80211_ADDR_LEN]) 1621 { 1622 struct iwn_ops *ops = &sc->ops; 1623 uint16_t val; 1624 int error; 1625 1626 /* Check whether adapter has an EEPROM or an OTPROM. */ 1627 if (sc->hw_type >= IWN_HW_REV_TYPE_1000 && 1628 (IWN_READ(sc, IWN_OTP_GP) & IWN_OTP_GP_DEV_SEL_OTP)) 1629 sc->sc_flags |= IWN_FLAG_HAS_OTPROM; 1630 DPRINTF(sc, IWN_DEBUG_RESET, "%s found\n", 1631 (sc->sc_flags & IWN_FLAG_HAS_OTPROM) ? "OTPROM" : "EEPROM"); 1632 1633 /* Adapter has to be powered on for EEPROM access to work. */ 1634 if ((error = iwn_apm_init(sc)) != 0) { 1635 device_printf(sc->sc_dev, 1636 "%s: could not power ON adapter, error %d\n", __func__, 1637 error); 1638 return error; 1639 } 1640 1641 if ((IWN_READ(sc, IWN_EEPROM_GP) & 0x7) == 0) { 1642 device_printf(sc->sc_dev, "%s: bad ROM signature\n", __func__); 1643 return EIO; 1644 } 1645 if ((error = iwn_eeprom_lock(sc)) != 0) { 1646 device_printf(sc->sc_dev, "%s: could not lock ROM, error %d\n", 1647 __func__, error); 1648 return error; 1649 } 1650 if (sc->sc_flags & IWN_FLAG_HAS_OTPROM) { 1651 if ((error = iwn_init_otprom(sc)) != 0) { 1652 device_printf(sc->sc_dev, 1653 "%s: could not initialize OTPROM, error %d\n", 1654 __func__, error); 1655 return error; 1656 } 1657 } 1658 1659 iwn_read_prom_data(sc, IWN_EEPROM_SKU_CAP, &val, 2); 1660 DPRINTF(sc, IWN_DEBUG_RESET, "SKU capabilities=0x%04x\n", le16toh(val)); 1661 /* Check if HT support is bonded out. */ 1662 if (val & htole16(IWN_EEPROM_SKU_CAP_11N)) 1663 sc->sc_flags |= IWN_FLAG_HAS_11N; 1664 1665 iwn_read_prom_data(sc, IWN_EEPROM_RFCFG, &val, 2); 1666 sc->rfcfg = le16toh(val); 1667 DPRINTF(sc, IWN_DEBUG_RESET, "radio config=0x%04x\n", sc->rfcfg); 1668 /* Read Tx/Rx chains from ROM unless it's known to be broken. */ 1669 if (sc->txchainmask == 0) 1670 sc->txchainmask = IWN_RFCFG_TXANTMSK(sc->rfcfg); 1671 if (sc->rxchainmask == 0) 1672 sc->rxchainmask = IWN_RFCFG_RXANTMSK(sc->rfcfg); 1673 1674 /* Read MAC address. */ 1675 iwn_read_prom_data(sc, IWN_EEPROM_MAC, macaddr, 6); 1676 1677 /* Read adapter-specific information from EEPROM. */ 1678 ops->read_eeprom(sc); 1679 1680 iwn_apm_stop(sc); /* Power OFF adapter. */ 1681 1682 iwn_eeprom_unlock(sc); 1683 return 0; 1684 } 1685 1686 static void 1687 iwn4965_read_eeprom(struct iwn_softc *sc) 1688 { 1689 uint32_t addr; 1690 uint16_t val; 1691 int i; 1692 1693 /* Read regulatory domain (4 ASCII characters). */ 1694 iwn_read_prom_data(sc, IWN4965_EEPROM_DOMAIN, sc->eeprom_domain, 4); 1695 1696 /* Read the list of authorized channels (20MHz ones only). */ 1697 for (i = 0; i < 5; i++) { 1698 addr = iwn4965_regulatory_bands[i]; 1699 iwn_read_eeprom_channels(sc, i, addr); 1700 } 1701 1702 /* Read maximum allowed TX power for 2GHz and 5GHz bands. */ 1703 iwn_read_prom_data(sc, IWN4965_EEPROM_MAXPOW, &val, 2); 1704 sc->maxpwr2GHz = val & 0xff; 1705 sc->maxpwr5GHz = val >> 8; 1706 /* Check that EEPROM values are within valid range. */ 1707 if (sc->maxpwr5GHz < 20 || sc->maxpwr5GHz > 50) 1708 sc->maxpwr5GHz = 38; 1709 if (sc->maxpwr2GHz < 20 || sc->maxpwr2GHz > 50) 1710 sc->maxpwr2GHz = 38; 1711 DPRINTF(sc, IWN_DEBUG_RESET, "maxpwr 2GHz=%d 5GHz=%d\n", 1712 sc->maxpwr2GHz, sc->maxpwr5GHz); 1713 1714 /* Read samples for each TX power group. */ 1715 iwn_read_prom_data(sc, IWN4965_EEPROM_BANDS, sc->bands, 1716 sizeof sc->bands); 1717 1718 /* Read voltage at which samples were taken. */ 1719 iwn_read_prom_data(sc, IWN4965_EEPROM_VOLTAGE, &val, 2); 1720 sc->eeprom_voltage = (int16_t)le16toh(val); 1721 DPRINTF(sc, IWN_DEBUG_RESET, "voltage=%d (in 0.3V)\n", 1722 sc->eeprom_voltage); 1723 1724 #ifdef IWN_DEBUG 1725 /* Print samples. */ 1726 if (sc->sc_debug & IWN_DEBUG_ANY) { 1727 for (i = 0; i < IWN_NBANDS; i++) 1728 iwn4965_print_power_group(sc, i); 1729 } 1730 #endif 1731 } 1732 1733 #ifdef IWN_DEBUG 1734 static void 1735 iwn4965_print_power_group(struct iwn_softc *sc, int i) 1736 { 1737 struct iwn4965_eeprom_band *band = &sc->bands[i]; 1738 struct iwn4965_eeprom_chan_samples *chans = band->chans; 1739 int j, c; 1740 1741 printf("===band %d===\n", i); 1742 printf("chan lo=%d, chan hi=%d\n", band->lo, band->hi); 1743 printf("chan1 num=%d\n", chans[0].num); 1744 for (c = 0; c < 2; c++) { 1745 for (j = 0; j < IWN_NSAMPLES; j++) { 1746 printf("chain %d, sample %d: temp=%d gain=%d " 1747 "power=%d pa_det=%d\n", c, j, 1748 chans[0].samples[c][j].temp, 1749 chans[0].samples[c][j].gain, 1750 chans[0].samples[c][j].power, 1751 chans[0].samples[c][j].pa_det); 1752 } 1753 } 1754 printf("chan2 num=%d\n", chans[1].num); 1755 for (c = 0; c < 2; c++) { 1756 for (j = 0; j < IWN_NSAMPLES; j++) { 1757 printf("chain %d, sample %d: temp=%d gain=%d " 1758 "power=%d pa_det=%d\n", c, j, 1759 chans[1].samples[c][j].temp, 1760 chans[1].samples[c][j].gain, 1761 chans[1].samples[c][j].power, 1762 chans[1].samples[c][j].pa_det); 1763 } 1764 } 1765 } 1766 #endif 1767 1768 static void 1769 iwn5000_read_eeprom(struct iwn_softc *sc) 1770 { 1771 struct iwn5000_eeprom_calib_hdr hdr; 1772 int32_t volt; 1773 uint32_t base, addr; 1774 uint16_t val; 1775 int i; 1776 1777 /* Read regulatory domain (4 ASCII characters). */ 1778 iwn_read_prom_data(sc, IWN5000_EEPROM_REG, &val, 2); 1779 base = le16toh(val); 1780 iwn_read_prom_data(sc, base + IWN5000_EEPROM_DOMAIN, 1781 sc->eeprom_domain, 4); 1782 1783 /* Read the list of authorized channels (20MHz ones only). */ 1784 for (i = 0; i < 5; i++) { 1785 addr = base + iwn5000_regulatory_bands[i]; 1786 iwn_read_eeprom_channels(sc, i, addr); 1787 } 1788 1789 /* Read enhanced TX power information for 6000 Series. */ 1790 if (sc->hw_type >= IWN_HW_REV_TYPE_6000) 1791 iwn_read_eeprom_enhinfo(sc); 1792 1793 iwn_read_prom_data(sc, IWN5000_EEPROM_CAL, &val, 2); 1794 base = le16toh(val); 1795 iwn_read_prom_data(sc, base, &hdr, sizeof hdr); 1796 DPRINTF(sc, IWN_DEBUG_CALIBRATE, 1797 "%s: calib version=%u pa type=%u voltage=%u\n", __func__, 1798 hdr.version, hdr.pa_type, le16toh(hdr.volt)); 1799 sc->calib_ver = hdr.version; 1800 1801 if (sc->hw_type == IWN_HW_REV_TYPE_5150) { 1802 /* Compute temperature offset. */ 1803 iwn_read_prom_data(sc, base + IWN5000_EEPROM_TEMP, &val, 2); 1804 sc->eeprom_temp = le16toh(val); 1805 iwn_read_prom_data(sc, base + IWN5000_EEPROM_VOLT, &val, 2); 1806 volt = le16toh(val); 1807 sc->temp_off = sc->eeprom_temp - (volt / -5); 1808 DPRINTF(sc, IWN_DEBUG_CALIBRATE, "temp=%d volt=%d offset=%dK\n", 1809 sc->eeprom_temp, volt, sc->temp_off); 1810 } else { 1811 /* Read crystal calibration. */ 1812 iwn_read_prom_data(sc, base + IWN5000_EEPROM_CRYSTAL, 1813 &sc->eeprom_crystal, sizeof (uint32_t)); 1814 DPRINTF(sc, IWN_DEBUG_CALIBRATE, "crystal calibration 0x%08x\n", 1815 le32toh(sc->eeprom_crystal)); 1816 } 1817 } 1818 1819 /* 1820 * Translate EEPROM flags to net80211. 1821 */ 1822 static uint32_t 1823 iwn_eeprom_channel_flags(struct iwn_eeprom_chan *channel) 1824 { 1825 uint32_t nflags; 1826 1827 nflags = 0; 1828 if ((channel->flags & IWN_EEPROM_CHAN_ACTIVE) == 0) 1829 nflags |= IEEE80211_CHAN_PASSIVE; 1830 if ((channel->flags & IWN_EEPROM_CHAN_IBSS) == 0) 1831 nflags |= IEEE80211_CHAN_NOADHOC; 1832 if (channel->flags & IWN_EEPROM_CHAN_RADAR) { 1833 nflags |= IEEE80211_CHAN_DFS; 1834 /* XXX apparently IBSS may still be marked */ 1835 nflags |= IEEE80211_CHAN_NOADHOC; 1836 } 1837 1838 return nflags; 1839 } 1840 1841 static void 1842 iwn_read_eeprom_band(struct iwn_softc *sc, int n) 1843 { 1844 struct ifnet *ifp = sc->sc_ifp; 1845 struct ieee80211com *ic = ifp->if_l2com; 1846 struct iwn_eeprom_chan *channels = sc->eeprom_channels[n]; 1847 const struct iwn_chan_band *band = &iwn_bands[n]; 1848 struct ieee80211_channel *c; 1849 uint8_t chan; 1850 int i, nflags; 1851 1852 for (i = 0; i < band->nchan; i++) { 1853 if (!(channels[i].flags & IWN_EEPROM_CHAN_VALID)) { 1854 DPRINTF(sc, IWN_DEBUG_RESET, 1855 "skip chan %d flags 0x%x maxpwr %d\n", 1856 band->chan[i], channels[i].flags, 1857 channels[i].maxpwr); 1858 continue; 1859 } 1860 chan = band->chan[i]; 1861 nflags = iwn_eeprom_channel_flags(&channels[i]); 1862 1863 c = &ic->ic_channels[ic->ic_nchans++]; 1864 c->ic_ieee = chan; 1865 c->ic_maxregpower = channels[i].maxpwr; 1866 c->ic_maxpower = 2*c->ic_maxregpower; 1867 1868 if (n == 0) { /* 2GHz band */ 1869 c->ic_freq = ieee80211_ieee2mhz(chan, IEEE80211_CHAN_G); 1870 /* G =>'s B is supported */ 1871 c->ic_flags = IEEE80211_CHAN_B | nflags; 1872 c = &ic->ic_channels[ic->ic_nchans++]; 1873 c[0] = c[-1]; 1874 c->ic_flags = IEEE80211_CHAN_G | nflags; 1875 } else { /* 5GHz band */ 1876 c->ic_freq = ieee80211_ieee2mhz(chan, IEEE80211_CHAN_A); 1877 c->ic_flags = IEEE80211_CHAN_A | nflags; 1878 } 1879 1880 /* Save maximum allowed TX power for this channel. */ 1881 sc->maxpwr[chan] = channels[i].maxpwr; 1882 1883 DPRINTF(sc, IWN_DEBUG_RESET, 1884 "add chan %d flags 0x%x maxpwr %d\n", chan, 1885 channels[i].flags, channels[i].maxpwr); 1886 1887 #if 0 /* HT */ 1888 /* XXX no constraints on using HT20 */ 1889 /* add HT20, HT40 added separately */ 1890 c = &ic->ic_channels[ic->ic_nchans++]; 1891 c[0] = c[-1]; 1892 c->ic_flags |= IEEE80211_CHAN_HT20; 1893 /* XXX NARROW =>'s 1/2 and 1/4 width? */ 1894 #endif 1895 } 1896 } 1897 1898 #if 0 /* HT */ 1899 static void 1900 iwn_read_eeprom_ht40(struct iwn_softc *sc, int n) 1901 { 1902 struct ifnet *ifp = sc->sc_ifp; 1903 struct ieee80211com *ic = ifp->if_l2com; 1904 struct iwn_eeprom_chan *channels = sc->eeprom_channels[n]; 1905 const struct iwn_chan_band *band = &iwn_bands[n]; 1906 struct ieee80211_channel *c, *cent, *extc; 1907 int i; 1908 1909 for (i = 0; i < band->nchan; i++) { 1910 if (!(channels[i].flags & IWN_EEPROM_CHAN_VALID) || 1911 !(channels[i].flags & IWN_EEPROM_CHAN_WIDE)) { 1912 DPRINTF(sc, IWN_DEBUG_RESET, 1913 "skip chan %d flags 0x%x maxpwr %d\n", 1914 band->chan[i], channels[i].flags, 1915 channels[i].maxpwr); 1916 continue; 1917 } 1918 /* 1919 * Each entry defines an HT40 channel pair; find the 1920 * center channel, then the extension channel above. 1921 */ 1922 cent = ieee80211_find_channel_byieee(ic, band->chan[i], 1923 band->flags & ~IEEE80211_CHAN_HT); 1924 if (cent == NULL) { /* XXX shouldn't happen */ 1925 device_printf(sc->sc_dev, 1926 "%s: no entry for channel %d\n", 1927 __func__, band->chan[i]); 1928 continue; 1929 } 1930 extc = ieee80211_find_channel(ic, cent->ic_freq+20, 1931 band->flags & ~IEEE80211_CHAN_HT); 1932 if (extc == NULL) { 1933 DPRINTF(sc, IWN_DEBUG_RESET, 1934 "skip chan %d, extension channel not found\n", 1935 band->chan[i]); 1936 continue; 1937 } 1938 1939 DPRINTF(sc, IWN_DEBUG_RESET, 1940 "add ht40 chan %d flags 0x%x maxpwr %d\n", 1941 band->chan[i], channels[i].flags, channels[i].maxpwr); 1942 1943 c = &ic->ic_channels[ic->ic_nchans++]; 1944 c[0] = cent[0]; 1945 c->ic_extieee = extc->ic_ieee; 1946 c->ic_flags &= ~IEEE80211_CHAN_HT; 1947 c->ic_flags |= IEEE80211_CHAN_HT40U; 1948 c = &ic->ic_channels[ic->ic_nchans++]; 1949 c[0] = extc[0]; 1950 c->ic_extieee = cent->ic_ieee; 1951 c->ic_flags &= ~IEEE80211_CHAN_HT; 1952 c->ic_flags |= IEEE80211_CHAN_HT40D; 1953 } 1954 } 1955 #endif 1956 1957 static void 1958 iwn_read_eeprom_channels(struct iwn_softc *sc, int n, uint32_t addr) 1959 { 1960 struct ifnet *ifp = sc->sc_ifp; 1961 struct ieee80211com *ic = ifp->if_l2com; 1962 1963 iwn_read_prom_data(sc, addr, &sc->eeprom_channels[n], 1964 iwn_bands[n].nchan * sizeof (struct iwn_eeprom_chan)); 1965 1966 if (n < 5) 1967 iwn_read_eeprom_band(sc, n); 1968 #if 0 /* HT */ 1969 else 1970 iwn_read_eeprom_ht40(sc, n); 1971 #endif 1972 ieee80211_sort_channels(ic->ic_channels, ic->ic_nchans); 1973 } 1974 1975 static struct iwn_eeprom_chan * 1976 iwn_find_eeprom_channel(struct iwn_softc *sc, struct ieee80211_channel *c) 1977 { 1978 int i, j; 1979 1980 for (j = 0; j < 7; j++) { 1981 for (i = 0; i < iwn_bands[j].nchan; i++) { 1982 if (iwn_bands[j].chan[i] == c->ic_ieee) 1983 return &sc->eeprom_channels[j][i]; 1984 } 1985 } 1986 1987 return NULL; 1988 } 1989 1990 /* 1991 * Enforce flags read from EEPROM. 1992 */ 1993 static int 1994 iwn_setregdomain(struct ieee80211com *ic, struct ieee80211_regdomain *rd, 1995 int nchan, struct ieee80211_channel chans[]) 1996 { 1997 struct iwn_softc *sc = ic->ic_ifp->if_softc; 1998 int i; 1999 2000 for (i = 0; i < nchan; i++) { 2001 struct ieee80211_channel *c = &chans[i]; 2002 struct iwn_eeprom_chan *channel; 2003 2004 channel = iwn_find_eeprom_channel(sc, c); 2005 if (channel == NULL) { 2006 if_printf(ic->ic_ifp, 2007 "%s: invalid channel %u freq %u/0x%x\n", 2008 __func__, c->ic_ieee, c->ic_freq, c->ic_flags); 2009 return EINVAL; 2010 } 2011 c->ic_flags |= iwn_eeprom_channel_flags(channel); 2012 } 2013 2014 return 0; 2015 } 2016 2017 #define nitems(_a) (sizeof((_a)) / sizeof((_a)[0])) 2018 2019 static void 2020 iwn_read_eeprom_enhinfo(struct iwn_softc *sc) 2021 { 2022 struct iwn_eeprom_enhinfo enhinfo[35]; 2023 uint16_t val, base; 2024 int8_t maxpwr; 2025 int i; 2026 2027 iwn_read_prom_data(sc, IWN5000_EEPROM_REG, &val, 2); 2028 base = le16toh(val); 2029 iwn_read_prom_data(sc, base + IWN6000_EEPROM_ENHINFO, 2030 enhinfo, sizeof enhinfo); 2031 2032 memset(sc->enh_maxpwr, 0, sizeof sc->enh_maxpwr); 2033 for (i = 0; i < nitems(enhinfo); i++) { 2034 if (enhinfo[i].chan == 0 || enhinfo[i].reserved != 0) 2035 continue; /* Skip invalid entries. */ 2036 2037 maxpwr = 0; 2038 if (sc->txchainmask & IWN_ANT_A) 2039 maxpwr = MAX(maxpwr, enhinfo[i].chain[0]); 2040 if (sc->txchainmask & IWN_ANT_B) 2041 maxpwr = MAX(maxpwr, enhinfo[i].chain[1]); 2042 if (sc->txchainmask & IWN_ANT_C) 2043 maxpwr = MAX(maxpwr, enhinfo[i].chain[2]); 2044 if (sc->ntxchains == 2) 2045 maxpwr = MAX(maxpwr, enhinfo[i].mimo2); 2046 else if (sc->ntxchains == 3) 2047 maxpwr = MAX(maxpwr, enhinfo[i].mimo3); 2048 maxpwr /= 2; /* Convert half-dBm to dBm. */ 2049 2050 DPRINTF(sc, IWN_DEBUG_RESET, "enhinfo %d, maxpwr=%d\n", i, 2051 maxpwr); 2052 sc->enh_maxpwr[i] = maxpwr; 2053 } 2054 } 2055 2056 static struct ieee80211_node * 2057 iwn_node_alloc(struct ieee80211vap *vap, const uint8_t mac[IEEE80211_ADDR_LEN]) 2058 { 2059 return malloc(sizeof (struct iwn_node), M_80211_NODE,M_NOWAIT | M_ZERO); 2060 } 2061 2062 static void 2063 iwn_newassoc(struct ieee80211_node *ni, int isnew) 2064 { 2065 struct iwn_node *wn = (void *)ni; 2066 int ridx, i; 2067 2068 for (i = 0; i < ni->ni_rates.rs_nrates; i++) { 2069 ridx = iwn_plcp_signal(ni->ni_rates.rs_rates[i]); 2070 wn->ridx[i] = ridx; 2071 } 2072 } 2073 2074 static int 2075 iwn_media_change(struct ifnet *ifp) 2076 { 2077 int error; 2078 2079 error = ieee80211_media_change(ifp); 2080 /* NB: only the fixed rate can change and that doesn't need a reset */ 2081 return (error == ENETRESET ? 0 : error); 2082 } 2083 2084 static int 2085 iwn_newstate(struct ieee80211vap *vap, enum ieee80211_state nstate, int arg) 2086 { 2087 struct iwn_vap *ivp = IWN_VAP(vap); 2088 struct ieee80211com *ic = vap->iv_ic; 2089 struct iwn_softc *sc = ic->ic_ifp->if_softc; 2090 int error = 0; 2091 2092 DPRINTF(sc, IWN_DEBUG_STATE, "%s: %s -> %s\n", __func__, 2093 ieee80211_state_name[vap->iv_state], ieee80211_state_name[nstate]); 2094 2095 IEEE80211_UNLOCK(ic); 2096 IWN_LOCK(sc); 2097 callout_stop(&sc->calib_to); 2098 2099 switch (nstate) { 2100 case IEEE80211_S_ASSOC: 2101 if (vap->iv_state != IEEE80211_S_RUN) 2102 break; 2103 /* FALLTHROUGH */ 2104 case IEEE80211_S_AUTH: 2105 if (vap->iv_state == IEEE80211_S_AUTH) 2106 break; 2107 2108 /* 2109 * !AUTH -> AUTH transition requires state reset to handle 2110 * reassociations correctly. 2111 */ 2112 sc->rxon.associd = 0; 2113 sc->rxon.filter &= ~htole32(IWN_FILTER_BSS); 2114 sc->calib.state = IWN_CALIB_STATE_INIT; 2115 2116 if ((error = iwn_auth(sc, vap)) != 0) { 2117 device_printf(sc->sc_dev, 2118 "%s: could not move to auth state\n", __func__); 2119 } 2120 break; 2121 2122 case IEEE80211_S_RUN: 2123 /* 2124 * RUN -> RUN transition; Just restart the timers. 2125 */ 2126 if (vap->iv_state == IEEE80211_S_RUN) { 2127 sc->calib_cnt = 0; 2128 break; 2129 } 2130 2131 /* 2132 * !RUN -> RUN requires setting the association id 2133 * which is done with a firmware cmd. We also defer 2134 * starting the timers until that work is done. 2135 */ 2136 if ((error = iwn_run(sc, vap)) != 0) { 2137 device_printf(sc->sc_dev, 2138 "%s: could not move to run state\n", __func__); 2139 } 2140 break; 2141 2142 case IEEE80211_S_INIT: 2143 sc->calib.state = IWN_CALIB_STATE_INIT; 2144 break; 2145 2146 default: 2147 break; 2148 } 2149 IWN_UNLOCK(sc); 2150 IEEE80211_LOCK(ic); 2151 if (error != 0) 2152 return error; 2153 return ivp->iv_newstate(vap, nstate, arg); 2154 } 2155 2156 static void 2157 iwn_calib_timeout(void *arg) 2158 { 2159 struct iwn_softc *sc = arg; 2160 2161 IWN_LOCK_ASSERT(sc); 2162 2163 /* Force automatic TX power calibration every 60 secs. */ 2164 if (++sc->calib_cnt >= 120) { 2165 uint32_t flags = 0; 2166 2167 DPRINTF(sc, IWN_DEBUG_CALIBRATE, "%s\n", 2168 "sending request for statistics"); 2169 (void)iwn_cmd(sc, IWN_CMD_GET_STATISTICS, &flags, 2170 sizeof flags, 1); 2171 sc->calib_cnt = 0; 2172 } 2173 callout_reset(&sc->calib_to, msecs_to_ticks(500), iwn_calib_timeout, 2174 sc); 2175 } 2176 2177 /* 2178 * Process an RX_PHY firmware notification. This is usually immediately 2179 * followed by an MPDU_RX_DONE notification. 2180 */ 2181 static void 2182 iwn_rx_phy(struct iwn_softc *sc, struct iwn_rx_desc *desc, 2183 struct iwn_rx_data *data) 2184 { 2185 struct iwn_rx_stat *stat = (struct iwn_rx_stat *)(desc + 1); 2186 2187 DPRINTF(sc, IWN_DEBUG_CALIBRATE, "%s: received PHY stats\n", __func__); 2188 bus_dmamap_sync(sc->rxq.data_dmat, data->map, BUS_DMASYNC_POSTREAD); 2189 2190 /* Save RX statistics, they will be used on MPDU_RX_DONE. */ 2191 memcpy(&sc->last_rx_stat, stat, sizeof (*stat)); 2192 sc->last_rx_valid = 1; 2193 } 2194 2195 /* 2196 * Process an RX_DONE (4965AGN only) or MPDU_RX_DONE firmware notification. 2197 * Each MPDU_RX_DONE notification must be preceded by an RX_PHY one. 2198 */ 2199 static void 2200 iwn_rx_done(struct iwn_softc *sc, struct iwn_rx_desc *desc, 2201 struct iwn_rx_data *data) 2202 { 2203 struct iwn_ops *ops = &sc->ops; 2204 struct ifnet *ifp = sc->sc_ifp; 2205 struct ieee80211com *ic = ifp->if_l2com; 2206 struct iwn_rx_ring *ring = &sc->rxq; 2207 struct ieee80211_frame *wh; 2208 struct ieee80211_node *ni; 2209 struct mbuf *m, *m1; 2210 struct iwn_rx_stat *stat; 2211 caddr_t head; 2212 bus_addr_t paddr; 2213 uint32_t flags; 2214 int error, len, rssi, nf; 2215 2216 if (desc->type == IWN_MPDU_RX_DONE) { 2217 /* Check for prior RX_PHY notification. */ 2218 if (!sc->last_rx_valid) { 2219 DPRINTF(sc, IWN_DEBUG_ANY, 2220 "%s: missing RX_PHY\n", __func__); 2221 return; 2222 } 2223 sc->last_rx_valid = 0; 2224 stat = &sc->last_rx_stat; 2225 } else 2226 stat = (struct iwn_rx_stat *)(desc + 1); 2227 2228 bus_dmamap_sync(ring->data_dmat, data->map, BUS_DMASYNC_POSTREAD); 2229 2230 if (stat->cfg_phy_len > IWN_STAT_MAXLEN) { 2231 device_printf(sc->sc_dev, 2232 "%s: invalid RX statistic header, len %d\n", __func__, 2233 stat->cfg_phy_len); 2234 return; 2235 } 2236 if (desc->type == IWN_MPDU_RX_DONE) { 2237 struct iwn_rx_mpdu *mpdu = (struct iwn_rx_mpdu *)(desc + 1); 2238 head = (caddr_t)(mpdu + 1); 2239 len = le16toh(mpdu->len); 2240 } else { 2241 head = (caddr_t)(stat + 1) + stat->cfg_phy_len; 2242 len = le16toh(stat->len); 2243 } 2244 2245 flags = le32toh(*(uint32_t *)(head + len)); 2246 2247 /* Discard frames with a bad FCS early. */ 2248 if ((flags & IWN_RX_NOERROR) != IWN_RX_NOERROR) { 2249 DPRINTF(sc, IWN_DEBUG_RECV, "%s: RX flags error %x\n", 2250 __func__, flags); 2251 ifp->if_ierrors++; 2252 return; 2253 } 2254 /* Discard frames that are too short. */ 2255 if (len < sizeof (*wh)) { 2256 DPRINTF(sc, IWN_DEBUG_RECV, "%s: frame too short: %d\n", 2257 __func__, len); 2258 ifp->if_ierrors++; 2259 return; 2260 } 2261 2262 m1 = m_getjcl(M_DONTWAIT, MT_DATA, M_PKTHDR, IWN_RBUF_SIZE); 2263 if (m1 == NULL) { 2264 DPRINTF(sc, IWN_DEBUG_ANY, "%s: no mbuf to restock ring\n", 2265 __func__); 2266 ifp->if_ierrors++; 2267 return; 2268 } 2269 bus_dmamap_unload(ring->data_dmat, data->map); 2270 2271 error = bus_dmamap_load(ring->data_dmat, data->map, mtod(m1, void *), 2272 IWN_RBUF_SIZE, iwn_dma_map_addr, &paddr, BUS_DMA_NOWAIT); 2273 if (error != 0 && error != EFBIG) { 2274 device_printf(sc->sc_dev, 2275 "%s: bus_dmamap_load failed, error %d\n", __func__, error); 2276 m_freem(m1); 2277 2278 /* Try to reload the old mbuf. */ 2279 error = bus_dmamap_load(ring->data_dmat, data->map, 2280 mtod(data->m, void *), IWN_RBUF_SIZE, iwn_dma_map_addr, 2281 &paddr, BUS_DMA_NOWAIT); 2282 if (error != 0 && error != EFBIG) { 2283 panic("%s: could not load old RX mbuf", __func__); 2284 } 2285 /* Physical address may have changed. */ 2286 ring->desc[ring->cur] = htole32(paddr >> 8); 2287 bus_dmamap_sync(ring->data_dmat, ring->desc_dma.map, 2288 BUS_DMASYNC_PREWRITE); 2289 ifp->if_ierrors++; 2290 return; 2291 } 2292 2293 m = data->m; 2294 data->m = m1; 2295 /* Update RX descriptor. */ 2296 ring->desc[ring->cur] = htole32(paddr >> 8); 2297 bus_dmamap_sync(ring->desc_dma.tag, ring->desc_dma.map, 2298 BUS_DMASYNC_PREWRITE); 2299 2300 /* Finalize mbuf. */ 2301 m->m_pkthdr.rcvif = ifp; 2302 m->m_data = head; 2303 m->m_pkthdr.len = m->m_len = len; 2304 2305 /* Grab a reference to the source node. */ 2306 wh = mtod(m, struct ieee80211_frame *); 2307 ni = ieee80211_find_rxnode(ic, (struct ieee80211_frame_min *)wh); 2308 nf = (ni != NULL && ni->ni_vap->iv_state == IEEE80211_S_RUN && 2309 (ic->ic_flags & IEEE80211_F_SCAN) == 0) ? sc->noise : -95; 2310 2311 rssi = ops->get_rssi(sc, stat); 2312 2313 if (ieee80211_radiotap_active(ic)) { 2314 struct iwn_rx_radiotap_header *tap = &sc->sc_rxtap; 2315 2316 tap->wr_flags = 0; 2317 if (stat->flags & htole16(IWN_STAT_FLAG_SHPREAMBLE)) 2318 tap->wr_flags |= IEEE80211_RADIOTAP_F_SHORTPRE; 2319 tap->wr_dbm_antsignal = (int8_t)rssi; 2320 tap->wr_dbm_antnoise = (int8_t)nf; 2321 tap->wr_tsft = stat->tstamp; 2322 switch (stat->rate) { 2323 /* CCK rates. */ 2324 case 10: tap->wr_rate = 2; break; 2325 case 20: tap->wr_rate = 4; break; 2326 case 55: tap->wr_rate = 11; break; 2327 case 110: tap->wr_rate = 22; break; 2328 /* OFDM rates. */ 2329 case 0xd: tap->wr_rate = 12; break; 2330 case 0xf: tap->wr_rate = 18; break; 2331 case 0x5: tap->wr_rate = 24; break; 2332 case 0x7: tap->wr_rate = 36; break; 2333 case 0x9: tap->wr_rate = 48; break; 2334 case 0xb: tap->wr_rate = 72; break; 2335 case 0x1: tap->wr_rate = 96; break; 2336 case 0x3: tap->wr_rate = 108; break; 2337 /* Unknown rate: should not happen. */ 2338 default: tap->wr_rate = 0; 2339 } 2340 } 2341 2342 IWN_UNLOCK(sc); 2343 2344 /* Send the frame to the 802.11 layer. */ 2345 if (ni != NULL) { 2346 (void)ieee80211_input(ni, m, rssi - nf, nf); 2347 /* Node is no longer needed. */ 2348 ieee80211_free_node(ni); 2349 } else 2350 (void)ieee80211_input_all(ic, m, rssi - nf, nf); 2351 2352 IWN_LOCK(sc); 2353 } 2354 2355 #if 0 /* HT */ 2356 /* Process an incoming Compressed BlockAck. */ 2357 static void 2358 iwn_rx_compressed_ba(struct iwn_softc *sc, struct iwn_rx_desc *desc, 2359 struct iwn_rx_data *data) 2360 { 2361 struct iwn_compressed_ba *ba = (struct iwn_compressed_ba *)(desc + 1); 2362 struct iwn_tx_ring *txq; 2363 2364 bus_dmamap_sync(sc->rxq.data_dmat, data->map, BUS_DMASYNC_POSTREAD); 2365 2366 txq = &sc->txq[letoh16(ba->qid)]; 2367 /* XXX TBD */ 2368 } 2369 #endif 2370 2371 /* 2372 * Process a CALIBRATION_RESULT notification sent by the initialization 2373 * firmware on response to a CMD_CALIB_CONFIG command (5000 only). 2374 */ 2375 static void 2376 iwn5000_rx_calib_results(struct iwn_softc *sc, struct iwn_rx_desc *desc, 2377 struct iwn_rx_data *data) 2378 { 2379 struct iwn_phy_calib *calib = (struct iwn_phy_calib *)(desc + 1); 2380 int len, idx = -1; 2381 2382 /* Runtime firmware should not send such a notification. */ 2383 if (sc->sc_flags & IWN_FLAG_CALIB_DONE) 2384 return; 2385 2386 len = (le32toh(desc->len) & 0x3fff) - 4; 2387 bus_dmamap_sync(sc->rxq.data_dmat, data->map, BUS_DMASYNC_POSTREAD); 2388 2389 switch (calib->code) { 2390 case IWN5000_PHY_CALIB_DC: 2391 if ((sc->sc_flags & IWN_FLAG_INTERNAL_PA) == 0 && 2392 (sc->hw_type == IWN_HW_REV_TYPE_5150 || 2393 sc->hw_type >= IWN_HW_REV_TYPE_6000)) 2394 idx = 0; 2395 break; 2396 case IWN5000_PHY_CALIB_LO: 2397 idx = 1; 2398 break; 2399 case IWN5000_PHY_CALIB_TX_IQ: 2400 idx = 2; 2401 break; 2402 case IWN5000_PHY_CALIB_TX_IQ_PERIODIC: 2403 if (sc->hw_type < IWN_HW_REV_TYPE_6000 && 2404 sc->hw_type != IWN_HW_REV_TYPE_5150) 2405 idx = 3; 2406 break; 2407 case IWN5000_PHY_CALIB_BASE_BAND: 2408 idx = 4; 2409 break; 2410 } 2411 if (idx == -1) /* Ignore other results. */ 2412 return; 2413 2414 /* Save calibration result. */ 2415 if (sc->calibcmd[idx].buf != NULL) 2416 free(sc->calibcmd[idx].buf, M_DEVBUF); 2417 sc->calibcmd[idx].buf = malloc(len, M_DEVBUF, M_NOWAIT); 2418 if (sc->calibcmd[idx].buf == NULL) { 2419 DPRINTF(sc, IWN_DEBUG_CALIBRATE, 2420 "not enough memory for calibration result %d\n", 2421 calib->code); 2422 return; 2423 } 2424 DPRINTF(sc, IWN_DEBUG_CALIBRATE, 2425 "saving calibration result code=%d len=%d\n", calib->code, len); 2426 sc->calibcmd[idx].len = len; 2427 memcpy(sc->calibcmd[idx].buf, calib, len); 2428 } 2429 2430 /* 2431 * Process an RX_STATISTICS or BEACON_STATISTICS firmware notification. 2432 * The latter is sent by the firmware after each received beacon. 2433 */ 2434 static void 2435 iwn_rx_statistics(struct iwn_softc *sc, struct iwn_rx_desc *desc, 2436 struct iwn_rx_data *data) 2437 { 2438 struct iwn_ops *ops = &sc->ops; 2439 struct ifnet *ifp = sc->sc_ifp; 2440 struct ieee80211com *ic = ifp->if_l2com; 2441 struct ieee80211vap *vap = TAILQ_FIRST(&ic->ic_vaps); 2442 struct iwn_calib_state *calib = &sc->calib; 2443 struct iwn_stats *stats = (struct iwn_stats *)(desc + 1); 2444 int temp; 2445 2446 /* Ignore statistics received during a scan. */ 2447 if (vap->iv_state != IEEE80211_S_RUN || 2448 (ic->ic_flags & IEEE80211_F_SCAN)) 2449 return; 2450 2451 bus_dmamap_sync(sc->rxq.data_dmat, data->map, BUS_DMASYNC_POSTREAD); 2452 2453 DPRINTF(sc, IWN_DEBUG_CALIBRATE, "%s: received statistics, cmd %d\n", 2454 __func__, desc->type); 2455 sc->calib_cnt = 0; /* Reset TX power calibration timeout. */ 2456 2457 /* Test if temperature has changed. */ 2458 if (stats->general.temp != sc->rawtemp) { 2459 /* Convert "raw" temperature to degC. */ 2460 sc->rawtemp = stats->general.temp; 2461 temp = ops->get_temperature(sc); 2462 DPRINTF(sc, IWN_DEBUG_CALIBRATE, "%s: temperature %d\n", 2463 __func__, temp); 2464 2465 /* Update TX power if need be (4965AGN only). */ 2466 if (sc->hw_type == IWN_HW_REV_TYPE_4965) 2467 iwn4965_power_calibration(sc, temp); 2468 } 2469 2470 if (desc->type != IWN_BEACON_STATISTICS) 2471 return; /* Reply to a statistics request. */ 2472 2473 sc->noise = iwn_get_noise(&stats->rx.general); 2474 DPRINTF(sc, IWN_DEBUG_CALIBRATE, "%s: noise %d\n", __func__, sc->noise); 2475 2476 /* Test that RSSI and noise are present in stats report. */ 2477 if (le32toh(stats->rx.general.flags) != 1) { 2478 DPRINTF(sc, IWN_DEBUG_ANY, "%s\n", 2479 "received statistics without RSSI"); 2480 return; 2481 } 2482 2483 if (calib->state == IWN_CALIB_STATE_ASSOC) 2484 iwn_collect_noise(sc, &stats->rx.general); 2485 else if (calib->state == IWN_CALIB_STATE_RUN) 2486 iwn_tune_sensitivity(sc, &stats->rx); 2487 } 2488 2489 /* 2490 * Process a TX_DONE firmware notification. Unfortunately, the 4965AGN 2491 * and 5000 adapters have different incompatible TX status formats. 2492 */ 2493 static void 2494 iwn4965_tx_done(struct iwn_softc *sc, struct iwn_rx_desc *desc, 2495 struct iwn_rx_data *data) 2496 { 2497 struct iwn4965_tx_stat *stat = (struct iwn4965_tx_stat *)(desc + 1); 2498 struct iwn_tx_ring *ring = &sc->txq[desc->qid & 0xf]; 2499 2500 DPRINTF(sc, IWN_DEBUG_XMIT, "%s: " 2501 "qid %d idx %d retries %d nkill %d rate %x duration %d status %x\n", 2502 __func__, desc->qid, desc->idx, stat->ackfailcnt, 2503 stat->btkillcnt, stat->rate, le16toh(stat->duration), 2504 le32toh(stat->status)); 2505 2506 bus_dmamap_sync(ring->data_dmat, data->map, BUS_DMASYNC_POSTREAD); 2507 iwn_tx_done(sc, desc, stat->ackfailcnt, le32toh(stat->status) & 0xff); 2508 } 2509 2510 static void 2511 iwn5000_tx_done(struct iwn_softc *sc, struct iwn_rx_desc *desc, 2512 struct iwn_rx_data *data) 2513 { 2514 struct iwn5000_tx_stat *stat = (struct iwn5000_tx_stat *)(desc + 1); 2515 struct iwn_tx_ring *ring = &sc->txq[desc->qid & 0xf]; 2516 2517 DPRINTF(sc, IWN_DEBUG_XMIT, "%s: " 2518 "qid %d idx %d retries %d nkill %d rate %x duration %d status %x\n", 2519 __func__, desc->qid, desc->idx, stat->ackfailcnt, 2520 stat->btkillcnt, stat->rate, le16toh(stat->duration), 2521 le32toh(stat->status)); 2522 2523 #ifdef notyet 2524 /* Reset TX scheduler slot. */ 2525 iwn5000_reset_sched(sc, desc->qid & 0xf, desc->idx); 2526 #endif 2527 2528 bus_dmamap_sync(ring->data_dmat, data->map, BUS_DMASYNC_POSTREAD); 2529 iwn_tx_done(sc, desc, stat->ackfailcnt, le16toh(stat->status) & 0xff); 2530 } 2531 2532 /* 2533 * Adapter-independent backend for TX_DONE firmware notifications. 2534 */ 2535 static void 2536 iwn_tx_done(struct iwn_softc *sc, struct iwn_rx_desc *desc, int ackfailcnt, 2537 uint8_t status) 2538 { 2539 struct ifnet *ifp = sc->sc_ifp; 2540 struct iwn_tx_ring *ring = &sc->txq[desc->qid & 0xf]; 2541 struct iwn_tx_data *data = &ring->data[desc->idx]; 2542 struct mbuf *m; 2543 struct ieee80211_node *ni; 2544 struct ieee80211vap *vap; 2545 2546 KASSERT(data->ni != NULL, ("no node")); 2547 2548 /* Unmap and free mbuf. */ 2549 bus_dmamap_sync(ring->data_dmat, data->map, BUS_DMASYNC_POSTWRITE); 2550 bus_dmamap_unload(ring->data_dmat, data->map); 2551 m = data->m, data->m = NULL; 2552 ni = data->ni, data->ni = NULL; 2553 vap = ni->ni_vap; 2554 2555 if (m->m_flags & M_TXCB) { 2556 /* 2557 * Channels marked for "radar" require traffic to be received 2558 * to unlock before we can transmit. Until traffic is seen 2559 * any attempt to transmit is returned immediately with status 2560 * set to IWN_TX_FAIL_TX_LOCKED. Unfortunately this can easily 2561 * happen on first authenticate after scanning. To workaround 2562 * this we ignore a failure of this sort in AUTH state so the 2563 * 802.11 layer will fall back to using a timeout to wait for 2564 * the AUTH reply. This allows the firmware time to see 2565 * traffic so a subsequent retry of AUTH succeeds. It's 2566 * unclear why the firmware does not maintain state for 2567 * channels recently visited as this would allow immediate 2568 * use of the channel after a scan (where we see traffic). 2569 */ 2570 if (status == IWN_TX_FAIL_TX_LOCKED && 2571 ni->ni_vap->iv_state == IEEE80211_S_AUTH) 2572 ieee80211_process_callback(ni, m, 0); 2573 else 2574 ieee80211_process_callback(ni, m, 2575 (status & IWN_TX_FAIL) != 0); 2576 } 2577 2578 /* 2579 * Update rate control statistics for the node. 2580 */ 2581 if (status & IWN_TX_FAIL) { 2582 ifp->if_oerrors++; 2583 ieee80211_ratectl_tx_complete(vap, ni, 2584 IEEE80211_RATECTL_TX_FAILURE, &ackfailcnt, NULL); 2585 } else { 2586 ifp->if_opackets++; 2587 ieee80211_ratectl_tx_complete(vap, ni, 2588 IEEE80211_RATECTL_TX_SUCCESS, &ackfailcnt, NULL); 2589 } 2590 m_freem(m); 2591 ieee80211_free_node(ni); 2592 2593 sc->sc_tx_timer = 0; 2594 if (--ring->queued < IWN_TX_RING_LOMARK) { 2595 sc->qfullmsk &= ~(1 << ring->qid); 2596 if (sc->qfullmsk == 0 && 2597 (ifp->if_drv_flags & IFF_DRV_OACTIVE)) { 2598 ifp->if_drv_flags &= ~IFF_DRV_OACTIVE; 2599 iwn_start_locked(ifp); 2600 } 2601 } 2602 } 2603 2604 /* 2605 * Process a "command done" firmware notification. This is where we wakeup 2606 * processes waiting for a synchronous command completion. 2607 */ 2608 static void 2609 iwn_cmd_done(struct iwn_softc *sc, struct iwn_rx_desc *desc) 2610 { 2611 struct iwn_tx_ring *ring = &sc->txq[4]; 2612 struct iwn_tx_data *data; 2613 2614 if ((desc->qid & 0xf) != 4) 2615 return; /* Not a command ack. */ 2616 2617 data = &ring->data[desc->idx]; 2618 2619 /* If the command was mapped in an mbuf, free it. */ 2620 if (data->m != NULL) { 2621 bus_dmamap_sync(ring->data_dmat, data->map, 2622 BUS_DMASYNC_POSTWRITE); 2623 bus_dmamap_unload(ring->data_dmat, data->map); 2624 m_freem(data->m); 2625 data->m = NULL; 2626 } 2627 wakeup(&ring->desc[desc->idx]); 2628 } 2629 2630 /* 2631 * Process an INT_FH_RX or INT_SW_RX interrupt. 2632 */ 2633 static void 2634 iwn_notif_intr(struct iwn_softc *sc) 2635 { 2636 struct iwn_ops *ops = &sc->ops; 2637 struct ifnet *ifp = sc->sc_ifp; 2638 struct ieee80211com *ic = ifp->if_l2com; 2639 struct ieee80211vap *vap = TAILQ_FIRST(&ic->ic_vaps); 2640 uint16_t hw; 2641 2642 bus_dmamap_sync(sc->rxq.stat_dma.tag, sc->rxq.stat_dma.map, 2643 BUS_DMASYNC_POSTREAD); 2644 2645 hw = le16toh(sc->rxq.stat->closed_count) & 0xfff; 2646 while (sc->rxq.cur != hw) { 2647 struct iwn_rx_data *data = &sc->rxq.data[sc->rxq.cur]; 2648 struct iwn_rx_desc *desc; 2649 2650 bus_dmamap_sync(sc->rxq.data_dmat, data->map, 2651 BUS_DMASYNC_POSTREAD); 2652 desc = mtod(data->m, struct iwn_rx_desc *); 2653 2654 DPRINTF(sc, IWN_DEBUG_RECV, 2655 "%s: qid %x idx %d flags %x type %d(%s) len %d\n", 2656 __func__, desc->qid & 0xf, desc->idx, desc->flags, 2657 desc->type, iwn_intr_str(desc->type), 2658 le16toh(desc->len)); 2659 2660 if (!(desc->qid & 0x80)) /* Reply to a command. */ 2661 iwn_cmd_done(sc, desc); 2662 2663 switch (desc->type) { 2664 case IWN_RX_PHY: 2665 iwn_rx_phy(sc, desc, data); 2666 break; 2667 2668 case IWN_RX_DONE: /* 4965AGN only. */ 2669 case IWN_MPDU_RX_DONE: 2670 /* An 802.11 frame has been received. */ 2671 iwn_rx_done(sc, desc, data); 2672 break; 2673 2674 #if 0 /* HT */ 2675 case IWN_RX_COMPRESSED_BA: 2676 /* A Compressed BlockAck has been received. */ 2677 iwn_rx_compressed_ba(sc, desc, data); 2678 break; 2679 #endif 2680 2681 case IWN_TX_DONE: 2682 /* An 802.11 frame has been transmitted. */ 2683 ops->tx_done(sc, desc, data); 2684 break; 2685 2686 case IWN_RX_STATISTICS: 2687 case IWN_BEACON_STATISTICS: 2688 iwn_rx_statistics(sc, desc, data); 2689 break; 2690 2691 case IWN_BEACON_MISSED: 2692 { 2693 struct iwn_beacon_missed *miss = 2694 (struct iwn_beacon_missed *)(desc + 1); 2695 int misses; 2696 2697 bus_dmamap_sync(sc->rxq.data_dmat, data->map, 2698 BUS_DMASYNC_POSTREAD); 2699 misses = le32toh(miss->consecutive); 2700 2701 DPRINTF(sc, IWN_DEBUG_STATE, 2702 "%s: beacons missed %d/%d\n", __func__, 2703 misses, le32toh(miss->total)); 2704 /* 2705 * If more than 5 consecutive beacons are missed, 2706 * reinitialize the sensitivity state machine. 2707 */ 2708 if (vap->iv_state == IEEE80211_S_RUN && 2709 (ic->ic_flags & IEEE80211_F_SCAN) != 0) { 2710 if (misses > 5) 2711 (void)iwn_init_sensitivity(sc); 2712 if (misses >= vap->iv_bmissthreshold) { 2713 IWN_UNLOCK(sc); 2714 ieee80211_beacon_miss(ic); 2715 IWN_LOCK(sc); 2716 } 2717 } 2718 break; 2719 } 2720 case IWN_UC_READY: 2721 { 2722 struct iwn_ucode_info *uc = 2723 (struct iwn_ucode_info *)(desc + 1); 2724 2725 /* The microcontroller is ready. */ 2726 bus_dmamap_sync(sc->rxq.data_dmat, data->map, 2727 BUS_DMASYNC_POSTREAD); 2728 DPRINTF(sc, IWN_DEBUG_RESET, 2729 "microcode alive notification version=%d.%d " 2730 "subtype=%x alive=%x\n", uc->major, uc->minor, 2731 uc->subtype, le32toh(uc->valid)); 2732 2733 if (le32toh(uc->valid) != 1) { 2734 device_printf(sc->sc_dev, 2735 "microcontroller initialization failed"); 2736 break; 2737 } 2738 if (uc->subtype == IWN_UCODE_INIT) { 2739 /* Save microcontroller report. */ 2740 memcpy(&sc->ucode_info, uc, sizeof (*uc)); 2741 } 2742 /* Save the address of the error log in SRAM. */ 2743 sc->errptr = le32toh(uc->errptr); 2744 break; 2745 } 2746 case IWN_STATE_CHANGED: 2747 { 2748 uint32_t *status = (uint32_t *)(desc + 1); 2749 2750 /* 2751 * State change allows hardware switch change to be 2752 * noted. However, we handle this in iwn_intr as we 2753 * get both the enable/disble intr. 2754 */ 2755 bus_dmamap_sync(sc->rxq.data_dmat, data->map, 2756 BUS_DMASYNC_POSTREAD); 2757 DPRINTF(sc, IWN_DEBUG_INTR, "state changed to %x\n", 2758 le32toh(*status)); 2759 break; 2760 } 2761 case IWN_START_SCAN: 2762 { 2763 struct iwn_start_scan *scan = 2764 (struct iwn_start_scan *)(desc + 1); 2765 2766 bus_dmamap_sync(sc->rxq.data_dmat, data->map, 2767 BUS_DMASYNC_POSTREAD); 2768 DPRINTF(sc, IWN_DEBUG_ANY, 2769 "%s: scanning channel %d status %x\n", 2770 __func__, scan->chan, le32toh(scan->status)); 2771 break; 2772 } 2773 case IWN_STOP_SCAN: 2774 { 2775 struct iwn_stop_scan *scan = 2776 (struct iwn_stop_scan *)(desc + 1); 2777 2778 bus_dmamap_sync(sc->rxq.data_dmat, data->map, 2779 BUS_DMASYNC_POSTREAD); 2780 DPRINTF(sc, IWN_DEBUG_STATE, 2781 "scan finished nchan=%d status=%d chan=%d\n", 2782 scan->nchan, scan->status, scan->chan); 2783 2784 IWN_UNLOCK(sc); 2785 ieee80211_scan_next(vap); 2786 IWN_LOCK(sc); 2787 break; 2788 } 2789 case IWN5000_CALIBRATION_RESULT: 2790 iwn5000_rx_calib_results(sc, desc, data); 2791 break; 2792 2793 case IWN5000_CALIBRATION_DONE: 2794 sc->sc_flags |= IWN_FLAG_CALIB_DONE; 2795 wakeup(sc); 2796 break; 2797 } 2798 2799 sc->rxq.cur = (sc->rxq.cur + 1) % IWN_RX_RING_COUNT; 2800 } 2801 2802 /* Tell the firmware what we have processed. */ 2803 hw = (hw == 0) ? IWN_RX_RING_COUNT - 1 : hw - 1; 2804 IWN_WRITE(sc, IWN_FH_RX_WPTR, hw & ~7); 2805 } 2806 2807 /* 2808 * Process an INT_WAKEUP interrupt raised when the microcontroller wakes up 2809 * from power-down sleep mode. 2810 */ 2811 static void 2812 iwn_wakeup_intr(struct iwn_softc *sc) 2813 { 2814 int qid; 2815 2816 DPRINTF(sc, IWN_DEBUG_RESET, "%s: ucode wakeup from power-down sleep\n", 2817 __func__); 2818 2819 /* Wakeup RX and TX rings. */ 2820 IWN_WRITE(sc, IWN_FH_RX_WPTR, sc->rxq.cur & ~7); 2821 for (qid = 0; qid < sc->ntxqs; qid++) { 2822 struct iwn_tx_ring *ring = &sc->txq[qid]; 2823 IWN_WRITE(sc, IWN_HBUS_TARG_WRPTR, qid << 8 | ring->cur); 2824 } 2825 } 2826 2827 static void 2828 iwn_rftoggle_intr(struct iwn_softc *sc) 2829 { 2830 struct ifnet *ifp = sc->sc_ifp; 2831 struct ieee80211com *ic = ifp->if_l2com; 2832 uint32_t tmp = IWN_READ(sc, IWN_GP_CNTRL); 2833 2834 IWN_LOCK_ASSERT(sc); 2835 2836 device_printf(sc->sc_dev, "RF switch: radio %s\n", 2837 (tmp & IWN_GP_CNTRL_RFKILL) ? "enabled" : "disabled"); 2838 if (tmp & IWN_GP_CNTRL_RFKILL) 2839 ieee80211_runtask(ic, &sc->sc_radioon_task); 2840 else 2841 ieee80211_runtask(ic, &sc->sc_radiooff_task); 2842 } 2843 2844 /* 2845 * Dump the error log of the firmware when a firmware panic occurs. Although 2846 * we can't debug the firmware because it is neither open source nor free, it 2847 * can help us to identify certain classes of problems. 2848 */ 2849 static void 2850 iwn_fatal_intr(struct iwn_softc *sc) 2851 { 2852 struct iwn_fw_dump dump; 2853 int i; 2854 2855 IWN_LOCK_ASSERT(sc); 2856 2857 /* Force a complete recalibration on next init. */ 2858 sc->sc_flags &= ~IWN_FLAG_CALIB_DONE; 2859 2860 /* Check that the error log address is valid. */ 2861 if (sc->errptr < IWN_FW_DATA_BASE || 2862 sc->errptr + sizeof (dump) > 2863 IWN_FW_DATA_BASE + sc->fw_data_maxsz) { 2864 printf("%s: bad firmware error log address 0x%08x\n", __func__, 2865 sc->errptr); 2866 return; 2867 } 2868 if (iwn_nic_lock(sc) != 0) { 2869 printf("%s: could not read firmware error log\n", __func__); 2870 return; 2871 } 2872 /* Read firmware error log from SRAM. */ 2873 iwn_mem_read_region_4(sc, sc->errptr, (uint32_t *)&dump, 2874 sizeof (dump) / sizeof (uint32_t)); 2875 iwn_nic_unlock(sc); 2876 2877 if (dump.valid == 0) { 2878 printf("%s: firmware error log is empty\n", __func__); 2879 return; 2880 } 2881 printf("firmware error log:\n"); 2882 printf(" error type = \"%s\" (0x%08X)\n", 2883 (dump.id < nitems(iwn_fw_errmsg)) ? 2884 iwn_fw_errmsg[dump.id] : "UNKNOWN", 2885 dump.id); 2886 printf(" program counter = 0x%08X\n", dump.pc); 2887 printf(" source line = 0x%08X\n", dump.src_line); 2888 printf(" error data = 0x%08X%08X\n", 2889 dump.error_data[0], dump.error_data[1]); 2890 printf(" branch link = 0x%08X%08X\n", 2891 dump.branch_link[0], dump.branch_link[1]); 2892 printf(" interrupt link = 0x%08X%08X\n", 2893 dump.interrupt_link[0], dump.interrupt_link[1]); 2894 printf(" time = %u\n", dump.time[0]); 2895 2896 /* Dump driver status (TX and RX rings) while we're here. */ 2897 printf("driver status:\n"); 2898 for (i = 0; i < sc->ntxqs; i++) { 2899 struct iwn_tx_ring *ring = &sc->txq[i]; 2900 printf(" tx ring %2d: qid=%-2d cur=%-3d queued=%-3d\n", 2901 i, ring->qid, ring->cur, ring->queued); 2902 } 2903 printf(" rx ring: cur=%d\n", sc->rxq.cur); 2904 } 2905 2906 static void 2907 iwn_intr(void *arg) 2908 { 2909 struct iwn_softc *sc = arg; 2910 struct ifnet *ifp = sc->sc_ifp; 2911 uint32_t r1, r2, tmp; 2912 2913 IWN_LOCK(sc); 2914 2915 /* Disable interrupts. */ 2916 IWN_WRITE(sc, IWN_INT_MASK, 0); 2917 2918 /* Read interrupts from ICT (fast) or from registers (slow). */ 2919 if (sc->sc_flags & IWN_FLAG_USE_ICT) { 2920 tmp = 0; 2921 while (sc->ict[sc->ict_cur] != 0) { 2922 tmp |= sc->ict[sc->ict_cur]; 2923 sc->ict[sc->ict_cur] = 0; /* Acknowledge. */ 2924 sc->ict_cur = (sc->ict_cur + 1) % IWN_ICT_COUNT; 2925 } 2926 tmp = le32toh(tmp); 2927 if (tmp == 0xffffffff) /* Shouldn't happen. */ 2928 tmp = 0; 2929 else if (tmp & 0xc0000) /* Workaround a HW bug. */ 2930 tmp |= 0x8000; 2931 r1 = (tmp & 0xff00) << 16 | (tmp & 0xff); 2932 r2 = 0; /* Unused. */ 2933 } else { 2934 r1 = IWN_READ(sc, IWN_INT); 2935 if (r1 == 0xffffffff || (r1 & 0xfffffff0) == 0xa5a5a5a0) 2936 return; /* Hardware gone! */ 2937 r2 = IWN_READ(sc, IWN_FH_INT); 2938 } 2939 2940 DPRINTF(sc, IWN_DEBUG_INTR, "interrupt reg1=%x reg2=%x\n", r1, r2); 2941 2942 if (r1 == 0 && r2 == 0) 2943 goto done; /* Interrupt not for us. */ 2944 2945 /* Acknowledge interrupts. */ 2946 IWN_WRITE(sc, IWN_INT, r1); 2947 if (!(sc->sc_flags & IWN_FLAG_USE_ICT)) 2948 IWN_WRITE(sc, IWN_FH_INT, r2); 2949 2950 if (r1 & IWN_INT_RF_TOGGLED) { 2951 iwn_rftoggle_intr(sc); 2952 goto done; 2953 } 2954 if (r1 & IWN_INT_CT_REACHED) { 2955 device_printf(sc->sc_dev, "%s: critical temperature reached!\n", 2956 __func__); 2957 } 2958 if (r1 & (IWN_INT_SW_ERR | IWN_INT_HW_ERR)) { 2959 device_printf(sc->sc_dev, "%s: fatal firmware error\n", 2960 __func__); 2961 /* Dump firmware error log and stop. */ 2962 iwn_fatal_intr(sc); 2963 ifp->if_flags &= ~IFF_UP; 2964 iwn_stop_locked(sc); 2965 goto done; 2966 } 2967 if ((r1 & (IWN_INT_FH_RX | IWN_INT_SW_RX | IWN_INT_RX_PERIODIC)) || 2968 (r2 & IWN_FH_INT_RX)) { 2969 if (sc->sc_flags & IWN_FLAG_USE_ICT) { 2970 if (r1 & (IWN_INT_FH_RX | IWN_INT_SW_RX)) 2971 IWN_WRITE(sc, IWN_FH_INT, IWN_FH_INT_RX); 2972 IWN_WRITE_1(sc, IWN_INT_PERIODIC, 2973 IWN_INT_PERIODIC_DIS); 2974 iwn_notif_intr(sc); 2975 if (r1 & (IWN_INT_FH_RX | IWN_INT_SW_RX)) { 2976 IWN_WRITE_1(sc, IWN_INT_PERIODIC, 2977 IWN_INT_PERIODIC_ENA); 2978 } 2979 } else 2980 iwn_notif_intr(sc); 2981 } 2982 2983 if ((r1 & IWN_INT_FH_TX) || (r2 & IWN_FH_INT_TX)) { 2984 if (sc->sc_flags & IWN_FLAG_USE_ICT) 2985 IWN_WRITE(sc, IWN_FH_INT, IWN_FH_INT_TX); 2986 wakeup(sc); /* FH DMA transfer completed. */ 2987 } 2988 2989 if (r1 & IWN_INT_ALIVE) 2990 wakeup(sc); /* Firmware is alive. */ 2991 2992 if (r1 & IWN_INT_WAKEUP) 2993 iwn_wakeup_intr(sc); 2994 2995 done: 2996 /* Re-enable interrupts. */ 2997 if (ifp->if_flags & IFF_UP) 2998 IWN_WRITE(sc, IWN_INT_MASK, sc->int_mask); 2999 3000 IWN_UNLOCK(sc); 3001 } 3002 3003 /* 3004 * Update TX scheduler ring when transmitting an 802.11 frame (4965AGN and 3005 * 5000 adapters use a slightly different format). 3006 */ 3007 static void 3008 iwn4965_update_sched(struct iwn_softc *sc, int qid, int idx, uint8_t id, 3009 uint16_t len) 3010 { 3011 uint16_t *w = &sc->sched[qid * IWN4965_SCHED_COUNT + idx]; 3012 3013 *w = htole16(len + 8); 3014 bus_dmamap_sync(sc->sched_dma.tag, sc->sched_dma.map, 3015 BUS_DMASYNC_PREWRITE); 3016 if (idx < IWN_SCHED_WINSZ) { 3017 *(w + IWN_TX_RING_COUNT) = *w; 3018 bus_dmamap_sync(sc->sched_dma.tag, sc->sched_dma.map, 3019 BUS_DMASYNC_PREWRITE); 3020 } 3021 } 3022 3023 static void 3024 iwn5000_update_sched(struct iwn_softc *sc, int qid, int idx, uint8_t id, 3025 uint16_t len) 3026 { 3027 uint16_t *w = &sc->sched[qid * IWN5000_SCHED_COUNT + idx]; 3028 3029 *w = htole16(id << 12 | (len + 8)); 3030 bus_dmamap_sync(sc->sched_dma.tag, sc->sched_dma.map, 3031 BUS_DMASYNC_PREWRITE); 3032 if (idx < IWN_SCHED_WINSZ) { 3033 *(w + IWN_TX_RING_COUNT) = *w; 3034 bus_dmamap_sync(sc->sched_dma.tag, sc->sched_dma.map, 3035 BUS_DMASYNC_PREWRITE); 3036 } 3037 } 3038 3039 #ifdef notyet 3040 static void 3041 iwn5000_reset_sched(struct iwn_softc *sc, int qid, int idx) 3042 { 3043 uint16_t *w = &sc->sched[qid * IWN5000_SCHED_COUNT + idx]; 3044 3045 *w = (*w & htole16(0xf000)) | htole16(1); 3046 bus_dmamap_sync(sc->sched_dma.tag, sc->sched_dma.map, 3047 BUS_DMASYNC_PREWRITE); 3048 if (idx < IWN_SCHED_WINSZ) { 3049 *(w + IWN_TX_RING_COUNT) = *w; 3050 bus_dmamap_sync(sc->sched_dma.tag, sc->sched_dma.map, 3051 BUS_DMASYNC_PREWRITE); 3052 } 3053 } 3054 #endif 3055 3056 static uint8_t 3057 iwn_plcp_signal(int rate) { 3058 int i; 3059 3060 for (i = 0; i < IWN_RIDX_MAX + 1; i++) { 3061 if ((rate & IEEE80211_RATE_VAL) == iwn_rates[i].rate) 3062 return i; 3063 } 3064 3065 return 0; 3066 } 3067 3068 static int 3069 iwn_tx_data(struct iwn_softc *sc, struct mbuf *m, struct ieee80211_node *ni) 3070 { 3071 const struct ieee80211_txparam *tp; 3072 struct ieee80211vap *vap = ni->ni_vap; 3073 struct ieee80211com *ic = ni->ni_ic; 3074 struct iwn_node *wn = (void *)ni; 3075 struct iwn_tx_ring *ring; 3076 struct iwn_tx_desc *desc; 3077 struct iwn_tx_data *data; 3078 struct iwn_tx_cmd *cmd; 3079 struct iwn_cmd_data *tx; 3080 const struct iwn_rate *rinfo; 3081 struct ieee80211_frame *wh; 3082 struct ieee80211_key *k = NULL; 3083 struct mbuf *m1; 3084 uint32_t flags; 3085 uint16_t qos; 3086 u_int hdrlen; 3087 bus_dma_segment_t *seg, segs[IWN_MAX_SCATTER]; 3088 uint8_t tid, ridx, txant, type; 3089 int ac, i, totlen, error, pad, nsegs = 0, rate; 3090 3091 IWN_LOCK_ASSERT(sc); 3092 3093 wh = mtod(m, struct ieee80211_frame *); 3094 hdrlen = ieee80211_anyhdrsize(wh); 3095 type = wh->i_fc[0] & IEEE80211_FC0_TYPE_MASK; 3096 3097 /* Select EDCA Access Category and TX ring for this frame. */ 3098 if (IEEE80211_QOS_HAS_SEQ(wh)) { 3099 qos = ((const struct ieee80211_qosframe *)wh)->i_qos[0]; 3100 tid = qos & IEEE80211_QOS_TID; 3101 } else { 3102 qos = 0; 3103 tid = 0; 3104 } 3105 ac = M_WME_GETAC(m); 3106 3107 ring = &sc->txq[ac]; 3108 desc = &ring->desc[ring->cur]; 3109 data = &ring->data[ring->cur]; 3110 3111 /* Choose a TX rate index. */ 3112 tp = &vap->iv_txparms[ieee80211_chan2mode(ni->ni_chan)]; 3113 if (type == IEEE80211_FC0_TYPE_MGT) 3114 rate = tp->mgmtrate; 3115 else if (IEEE80211_IS_MULTICAST(wh->i_addr1)) 3116 rate = tp->mcastrate; 3117 else if (tp->ucastrate != IEEE80211_FIXED_RATE_NONE) 3118 rate = tp->ucastrate; 3119 else { 3120 /* XXX pass pktlen */ 3121 (void) ieee80211_ratectl_rate(ni, NULL, 0); 3122 rate = ni->ni_txrate; 3123 } 3124 ridx = iwn_plcp_signal(rate); 3125 rinfo = &iwn_rates[ridx]; 3126 3127 /* Encrypt the frame if need be. */ 3128 if (wh->i_fc[1] & IEEE80211_FC1_WEP) { 3129 /* Retrieve key for TX. */ 3130 k = ieee80211_crypto_encap(ni, m); 3131 if (k == NULL) { 3132 m_freem(m); 3133 return ENOBUFS; 3134 } 3135 /* 802.11 header may have moved. */ 3136 wh = mtod(m, struct ieee80211_frame *); 3137 } 3138 totlen = m->m_pkthdr.len; 3139 3140 if (ieee80211_radiotap_active_vap(vap)) { 3141 struct iwn_tx_radiotap_header *tap = &sc->sc_txtap; 3142 3143 tap->wt_flags = 0; 3144 tap->wt_rate = rinfo->rate; 3145 if (k != NULL) 3146 tap->wt_flags |= IEEE80211_RADIOTAP_F_WEP; 3147 3148 ieee80211_radiotap_tx(vap, m); 3149 } 3150 3151 /* Prepare TX firmware command. */ 3152 cmd = &ring->cmd[ring->cur]; 3153 cmd->code = IWN_CMD_TX_DATA; 3154 cmd->flags = 0; 3155 cmd->qid = ring->qid; 3156 cmd->idx = ring->cur; 3157 3158 tx = (struct iwn_cmd_data *)cmd->data; 3159 /* NB: No need to clear tx, all fields are reinitialized here. */ 3160 tx->scratch = 0; /* clear "scratch" area */ 3161 3162 flags = 0; 3163 if (!IEEE80211_IS_MULTICAST(wh->i_addr1)) { 3164 /* Unicast frame, check if an ACK is expected. */ 3165 if (!qos || (qos & IEEE80211_QOS_ACKPOLICY) != 3166 IEEE80211_QOS_ACKPOLICY_NOACK) 3167 flags |= IWN_TX_NEED_ACK; 3168 } 3169 if ((wh->i_fc[0] & 3170 (IEEE80211_FC0_TYPE_MASK | IEEE80211_FC0_SUBTYPE_MASK)) == 3171 (IEEE80211_FC0_TYPE_CTL | IEEE80211_FC0_SUBTYPE_BAR)) 3172 flags |= IWN_TX_IMM_BA; /* Cannot happen yet. */ 3173 3174 if (wh->i_fc[1] & IEEE80211_FC1_MORE_FRAG) 3175 flags |= IWN_TX_MORE_FRAG; /* Cannot happen yet. */ 3176 3177 /* Check if frame must be protected using RTS/CTS or CTS-to-self. */ 3178 if (!IEEE80211_IS_MULTICAST(wh->i_addr1)) { 3179 /* NB: Group frames are sent using CCK in 802.11b/g. */ 3180 if (totlen + IEEE80211_CRC_LEN > vap->iv_rtsthreshold) { 3181 flags |= IWN_TX_NEED_RTS; 3182 } else if ((ic->ic_flags & IEEE80211_F_USEPROT) && 3183 ridx >= IWN_RIDX_OFDM6) { 3184 if (ic->ic_protmode == IEEE80211_PROT_CTSONLY) 3185 flags |= IWN_TX_NEED_CTS; 3186 else if (ic->ic_protmode == IEEE80211_PROT_RTSCTS) 3187 flags |= IWN_TX_NEED_RTS; 3188 } 3189 if (flags & (IWN_TX_NEED_RTS | IWN_TX_NEED_CTS)) { 3190 if (sc->hw_type != IWN_HW_REV_TYPE_4965) { 3191 /* 5000 autoselects RTS/CTS or CTS-to-self. */ 3192 flags &= ~(IWN_TX_NEED_RTS | IWN_TX_NEED_CTS); 3193 flags |= IWN_TX_NEED_PROTECTION; 3194 } else 3195 flags |= IWN_TX_FULL_TXOP; 3196 } 3197 } 3198 3199 if (IEEE80211_IS_MULTICAST(wh->i_addr1) || 3200 type != IEEE80211_FC0_TYPE_DATA) 3201 tx->id = sc->broadcast_id; 3202 else 3203 tx->id = wn->id; 3204 3205 if (type == IEEE80211_FC0_TYPE_MGT) { 3206 uint8_t subtype = wh->i_fc[0] & IEEE80211_FC0_SUBTYPE_MASK; 3207 3208 /* Tell HW to set timestamp in probe responses. */ 3209 if (subtype == IEEE80211_FC0_SUBTYPE_PROBE_RESP) 3210 flags |= IWN_TX_INSERT_TSTAMP; 3211 if (subtype == IEEE80211_FC0_SUBTYPE_ASSOC_REQ || 3212 subtype == IEEE80211_FC0_SUBTYPE_REASSOC_REQ) 3213 tx->timeout = htole16(3); 3214 else 3215 tx->timeout = htole16(2); 3216 } else 3217 tx->timeout = htole16(0); 3218 3219 if (hdrlen & 3) { 3220 /* First segment length must be a multiple of 4. */ 3221 flags |= IWN_TX_NEED_PADDING; 3222 pad = 4 - (hdrlen & 3); 3223 } else 3224 pad = 0; 3225 3226 tx->len = htole16(totlen); 3227 tx->tid = tid; 3228 tx->rts_ntries = 60; 3229 tx->data_ntries = 15; 3230 tx->lifetime = htole32(IWN_LIFETIME_INFINITE); 3231 tx->plcp = rinfo->plcp; 3232 tx->rflags = rinfo->flags; 3233 if (tx->id == sc->broadcast_id) { 3234 /* Group or management frame. */ 3235 tx->linkq = 0; 3236 /* XXX Alternate between antenna A and B? */ 3237 txant = IWN_LSB(sc->txchainmask); 3238 tx->rflags |= IWN_RFLAG_ANT(txant); 3239 } else { 3240 tx->linkq = ni->ni_rates.rs_nrates - ridx - 1; 3241 flags |= IWN_TX_LINKQ; /* enable MRR */ 3242 } 3243 /* Set physical address of "scratch area". */ 3244 tx->loaddr = htole32(IWN_LOADDR(data->scratch_paddr)); 3245 tx->hiaddr = IWN_HIADDR(data->scratch_paddr); 3246 3247 /* Copy 802.11 header in TX command. */ 3248 memcpy((uint8_t *)(tx + 1), wh, hdrlen); 3249 3250 /* Trim 802.11 header. */ 3251 m_adj(m, hdrlen); 3252 tx->security = 0; 3253 tx->flags = htole32(flags); 3254 3255 error = bus_dmamap_load_mbuf_sg(ring->data_dmat, data->map, m, segs, 3256 &nsegs, BUS_DMA_NOWAIT); 3257 if (error != 0) { 3258 if (error != EFBIG) { 3259 device_printf(sc->sc_dev, 3260 "%s: can't map mbuf (error %d)\n", __func__, error); 3261 m_freem(m); 3262 return error; 3263 } 3264 /* Too many DMA segments, linearize mbuf. */ 3265 m1 = m_collapse(m, M_DONTWAIT, IWN_MAX_SCATTER); 3266 if (m1 == NULL) { 3267 device_printf(sc->sc_dev, 3268 "%s: could not defrag mbuf\n", __func__); 3269 m_freem(m); 3270 return ENOBUFS; 3271 } 3272 m = m1; 3273 3274 error = bus_dmamap_load_mbuf_sg(ring->data_dmat, data->map, m, 3275 segs, &nsegs, BUS_DMA_NOWAIT); 3276 if (error != 0) { 3277 device_printf(sc->sc_dev, 3278 "%s: can't map mbuf (error %d)\n", __func__, error); 3279 m_freem(m); 3280 return error; 3281 } 3282 } 3283 3284 data->m = m; 3285 data->ni = ni; 3286 3287 DPRINTF(sc, IWN_DEBUG_XMIT, "%s: qid %d idx %d len %d nsegs %d\n", 3288 __func__, ring->qid, ring->cur, m->m_pkthdr.len, nsegs); 3289 3290 /* Fill TX descriptor. */ 3291 desc->nsegs = 1; 3292 if (m->m_len != 0) 3293 desc->nsegs += nsegs; 3294 /* First DMA segment is used by the TX command. */ 3295 desc->segs[0].addr = htole32(IWN_LOADDR(data->cmd_paddr)); 3296 desc->segs[0].len = htole16(IWN_HIADDR(data->cmd_paddr) | 3297 (4 + sizeof (*tx) + hdrlen + pad) << 4); 3298 /* Other DMA segments are for data payload. */ 3299 seg = &segs[0]; 3300 for (i = 1; i <= nsegs; i++) { 3301 desc->segs[i].addr = htole32(IWN_LOADDR(seg->ds_addr)); 3302 desc->segs[i].len = htole16(IWN_HIADDR(seg->ds_addr) | 3303 seg->ds_len << 4); 3304 seg++; 3305 } 3306 3307 bus_dmamap_sync(ring->data_dmat, data->map, BUS_DMASYNC_PREWRITE); 3308 bus_dmamap_sync(ring->data_dmat, ring->cmd_dma.map, 3309 BUS_DMASYNC_PREWRITE); 3310 bus_dmamap_sync(ring->desc_dma.tag, ring->desc_dma.map, 3311 BUS_DMASYNC_PREWRITE); 3312 3313 #ifdef notyet 3314 /* Update TX scheduler. */ 3315 ops->update_sched(sc, ring->qid, ring->cur, tx->id, totlen); 3316 #endif 3317 3318 /* Kick TX ring. */ 3319 ring->cur = (ring->cur + 1) % IWN_TX_RING_COUNT; 3320 IWN_WRITE(sc, IWN_HBUS_TARG_WRPTR, ring->qid << 8 | ring->cur); 3321 3322 /* Mark TX ring as full if we reach a certain threshold. */ 3323 if (++ring->queued > IWN_TX_RING_HIMARK) 3324 sc->qfullmsk |= 1 << ring->qid; 3325 3326 return 0; 3327 } 3328 3329 static int 3330 iwn_tx_data_raw(struct iwn_softc *sc, struct mbuf *m, 3331 struct ieee80211_node *ni, const struct ieee80211_bpf_params *params) 3332 { 3333 const struct iwn_rate *rinfo; 3334 struct ifnet *ifp = sc->sc_ifp; 3335 struct ieee80211vap *vap = ni->ni_vap; 3336 struct ieee80211com *ic = ifp->if_l2com; 3337 struct iwn_tx_cmd *cmd; 3338 struct iwn_cmd_data *tx; 3339 struct ieee80211_frame *wh; 3340 struct iwn_tx_ring *ring; 3341 struct iwn_tx_desc *desc; 3342 struct iwn_tx_data *data; 3343 struct mbuf *m1; 3344 bus_dma_segment_t *seg, segs[IWN_MAX_SCATTER]; 3345 uint32_t flags; 3346 u_int hdrlen; 3347 int ac, totlen, error, pad, nsegs = 0, i, rate; 3348 uint8_t ridx, type, txant; 3349 3350 IWN_LOCK_ASSERT(sc); 3351 3352 wh = mtod(m, struct ieee80211_frame *); 3353 hdrlen = ieee80211_anyhdrsize(wh); 3354 type = wh->i_fc[0] & IEEE80211_FC0_TYPE_MASK; 3355 3356 ac = params->ibp_pri & 3; 3357 3358 ring = &sc->txq[ac]; 3359 desc = &ring->desc[ring->cur]; 3360 data = &ring->data[ring->cur]; 3361 3362 /* Choose a TX rate index. */ 3363 rate = params->ibp_rate0; 3364 if (!ieee80211_isratevalid(ic->ic_rt, rate)) { 3365 /* XXX fall back to mcast/mgmt rate? */ 3366 m_freem(m); 3367 return EINVAL; 3368 } 3369 ridx = iwn_plcp_signal(rate); 3370 rinfo = &iwn_rates[ridx]; 3371 3372 totlen = m->m_pkthdr.len; 3373 3374 /* Prepare TX firmware command. */ 3375 cmd = &ring->cmd[ring->cur]; 3376 cmd->code = IWN_CMD_TX_DATA; 3377 cmd->flags = 0; 3378 cmd->qid = ring->qid; 3379 cmd->idx = ring->cur; 3380 3381 tx = (struct iwn_cmd_data *)cmd->data; 3382 /* NB: No need to clear tx, all fields are reinitialized here. */ 3383 tx->scratch = 0; /* clear "scratch" area */ 3384 3385 flags = 0; 3386 if ((params->ibp_flags & IEEE80211_BPF_NOACK) == 0) 3387 flags |= IWN_TX_NEED_ACK; 3388 if (params->ibp_flags & IEEE80211_BPF_RTS) { 3389 if (sc->hw_type != IWN_HW_REV_TYPE_4965) { 3390 /* 5000 autoselects RTS/CTS or CTS-to-self. */ 3391 flags &= ~IWN_TX_NEED_RTS; 3392 flags |= IWN_TX_NEED_PROTECTION; 3393 } else 3394 flags |= IWN_TX_NEED_RTS | IWN_TX_FULL_TXOP; 3395 } 3396 if (params->ibp_flags & IEEE80211_BPF_CTS) { 3397 if (sc->hw_type != IWN_HW_REV_TYPE_4965) { 3398 /* 5000 autoselects RTS/CTS or CTS-to-self. */ 3399 flags &= ~IWN_TX_NEED_CTS; 3400 flags |= IWN_TX_NEED_PROTECTION; 3401 } else 3402 flags |= IWN_TX_NEED_CTS | IWN_TX_FULL_TXOP; 3403 } 3404 if (type == IEEE80211_FC0_TYPE_MGT) { 3405 uint8_t subtype = wh->i_fc[0] & IEEE80211_FC0_SUBTYPE_MASK; 3406 3407 /* Tell HW to set timestamp in probe responses. */ 3408 if (subtype == IEEE80211_FC0_SUBTYPE_PROBE_RESP) 3409 flags |= IWN_TX_INSERT_TSTAMP; 3410 3411 if (subtype == IEEE80211_FC0_SUBTYPE_ASSOC_REQ || 3412 subtype == IEEE80211_FC0_SUBTYPE_REASSOC_REQ) 3413 tx->timeout = htole16(3); 3414 else 3415 tx->timeout = htole16(2); 3416 } else 3417 tx->timeout = htole16(0); 3418 3419 if (hdrlen & 3) { 3420 /* First segment length must be a multiple of 4. */ 3421 flags |= IWN_TX_NEED_PADDING; 3422 pad = 4 - (hdrlen & 3); 3423 } else 3424 pad = 0; 3425 3426 if (ieee80211_radiotap_active_vap(vap)) { 3427 struct iwn_tx_radiotap_header *tap = &sc->sc_txtap; 3428 3429 tap->wt_flags = 0; 3430 tap->wt_rate = rate; 3431 3432 ieee80211_radiotap_tx(vap, m); 3433 } 3434 3435 tx->len = htole16(totlen); 3436 tx->tid = 0; 3437 tx->id = sc->broadcast_id; 3438 tx->rts_ntries = params->ibp_try1; 3439 tx->data_ntries = params->ibp_try0; 3440 tx->lifetime = htole32(IWN_LIFETIME_INFINITE); 3441 tx->plcp = rinfo->plcp; 3442 tx->rflags = rinfo->flags; 3443 /* Group or management frame. */ 3444 tx->linkq = 0; 3445 txant = IWN_LSB(sc->txchainmask); 3446 tx->rflags |= IWN_RFLAG_ANT(txant); 3447 /* Set physical address of "scratch area". */ 3448 tx->loaddr = htole32(IWN_LOADDR(data->scratch_paddr)); 3449 tx->hiaddr = IWN_HIADDR(data->scratch_paddr); 3450 3451 /* Copy 802.11 header in TX command. */ 3452 memcpy((uint8_t *)(tx + 1), wh, hdrlen); 3453 3454 /* Trim 802.11 header. */ 3455 m_adj(m, hdrlen); 3456 tx->security = 0; 3457 tx->flags = htole32(flags); 3458 3459 error = bus_dmamap_load_mbuf_sg(ring->data_dmat, data->map, m, segs, 3460 &nsegs, BUS_DMA_NOWAIT); 3461 if (error != 0) { 3462 if (error != EFBIG) { 3463 device_printf(sc->sc_dev, 3464 "%s: can't map mbuf (error %d)\n", __func__, error); 3465 m_freem(m); 3466 return error; 3467 } 3468 /* Too many DMA segments, linearize mbuf. */ 3469 m1 = m_collapse(m, M_DONTWAIT, IWN_MAX_SCATTER); 3470 if (m1 == NULL) { 3471 device_printf(sc->sc_dev, 3472 "%s: could not defrag mbuf\n", __func__); 3473 m_freem(m); 3474 return ENOBUFS; 3475 } 3476 m = m1; 3477 3478 error = bus_dmamap_load_mbuf_sg(ring->data_dmat, data->map, m, 3479 segs, &nsegs, BUS_DMA_NOWAIT); 3480 if (error != 0) { 3481 device_printf(sc->sc_dev, 3482 "%s: can't map mbuf (error %d)\n", __func__, error); 3483 m_freem(m); 3484 return error; 3485 } 3486 } 3487 3488 data->m = m; 3489 data->ni = ni; 3490 3491 DPRINTF(sc, IWN_DEBUG_XMIT, "%s: qid %d idx %d len %d nsegs %d\n", 3492 __func__, ring->qid, ring->cur, m->m_pkthdr.len, nsegs); 3493 3494 /* Fill TX descriptor. */ 3495 desc->nsegs = 1; 3496 if (m->m_len != 0) 3497 desc->nsegs += nsegs; 3498 /* First DMA segment is used by the TX command. */ 3499 desc->segs[0].addr = htole32(IWN_LOADDR(data->cmd_paddr)); 3500 desc->segs[0].len = htole16(IWN_HIADDR(data->cmd_paddr) | 3501 (4 + sizeof (*tx) + hdrlen + pad) << 4); 3502 /* Other DMA segments are for data payload. */ 3503 seg = &segs[0]; 3504 for (i = 1; i <= nsegs; i++) { 3505 desc->segs[i].addr = htole32(IWN_LOADDR(seg->ds_addr)); 3506 desc->segs[i].len = htole16(IWN_HIADDR(seg->ds_addr) | 3507 seg->ds_len << 4); 3508 seg++; 3509 } 3510 3511 bus_dmamap_sync(ring->data_dmat, data->map, BUS_DMASYNC_PREWRITE); 3512 bus_dmamap_sync(ring->data_dmat, ring->cmd_dma.map, 3513 BUS_DMASYNC_PREWRITE); 3514 bus_dmamap_sync(ring->desc_dma.tag, ring->desc_dma.map, 3515 BUS_DMASYNC_PREWRITE); 3516 3517 #ifdef notyet 3518 /* Update TX scheduler. */ 3519 ops->update_sched(sc, ring->qid, ring->cur, tx->id, totlen); 3520 #endif 3521 3522 /* Kick TX ring. */ 3523 ring->cur = (ring->cur + 1) % IWN_TX_RING_COUNT; 3524 IWN_WRITE(sc, IWN_HBUS_TARG_WRPTR, ring->qid << 8 | ring->cur); 3525 3526 /* Mark TX ring as full if we reach a certain threshold. */ 3527 if (++ring->queued > IWN_TX_RING_HIMARK) 3528 sc->qfullmsk |= 1 << ring->qid; 3529 3530 return 0; 3531 } 3532 3533 static int 3534 iwn_raw_xmit(struct ieee80211_node *ni, struct mbuf *m, 3535 const struct ieee80211_bpf_params *params) 3536 { 3537 struct ieee80211com *ic = ni->ni_ic; 3538 struct ifnet *ifp = ic->ic_ifp; 3539 struct iwn_softc *sc = ifp->if_softc; 3540 int error = 0; 3541 3542 if ((ifp->if_drv_flags & IFF_DRV_RUNNING) == 0) { 3543 ieee80211_free_node(ni); 3544 m_freem(m); 3545 return ENETDOWN; 3546 } 3547 3548 IWN_LOCK(sc); 3549 if (params == NULL) { 3550 /* 3551 * Legacy path; interpret frame contents to decide 3552 * precisely how to send the frame. 3553 */ 3554 error = iwn_tx_data(sc, m, ni); 3555 } else { 3556 /* 3557 * Caller supplied explicit parameters to use in 3558 * sending the frame. 3559 */ 3560 error = iwn_tx_data_raw(sc, m, ni, params); 3561 } 3562 if (error != 0) { 3563 /* NB: m is reclaimed on tx failure */ 3564 ieee80211_free_node(ni); 3565 ifp->if_oerrors++; 3566 } 3567 sc->sc_tx_timer = 5; 3568 3569 IWN_UNLOCK(sc); 3570 return error; 3571 } 3572 3573 static void 3574 iwn_start(struct ifnet *ifp) 3575 { 3576 struct iwn_softc *sc = ifp->if_softc; 3577 3578 IWN_LOCK(sc); 3579 iwn_start_locked(ifp); 3580 IWN_UNLOCK(sc); 3581 } 3582 3583 static void 3584 iwn_start_locked(struct ifnet *ifp) 3585 { 3586 struct iwn_softc *sc = ifp->if_softc; 3587 struct ieee80211_node *ni; 3588 struct mbuf *m; 3589 3590 IWN_LOCK_ASSERT(sc); 3591 3592 if ((ifp->if_drv_flags & IFF_DRV_RUNNING) == 0 || 3593 (ifp->if_drv_flags & IFF_DRV_OACTIVE)) 3594 return; 3595 3596 for (;;) { 3597 if (sc->qfullmsk != 0) { 3598 ifp->if_drv_flags |= IFF_DRV_OACTIVE; 3599 break; 3600 } 3601 IFQ_DRV_DEQUEUE(&ifp->if_snd, m); 3602 if (m == NULL) 3603 break; 3604 ni = (struct ieee80211_node *)m->m_pkthdr.rcvif; 3605 if (iwn_tx_data(sc, m, ni) != 0) { 3606 ieee80211_free_node(ni); 3607 ifp->if_oerrors++; 3608 continue; 3609 } 3610 sc->sc_tx_timer = 5; 3611 } 3612 } 3613 3614 static void 3615 iwn_watchdog(void *arg) 3616 { 3617 struct iwn_softc *sc = arg; 3618 struct ifnet *ifp = sc->sc_ifp; 3619 struct ieee80211com *ic = ifp->if_l2com; 3620 3621 IWN_LOCK_ASSERT(sc); 3622 3623 KASSERT(ifp->if_drv_flags & IFF_DRV_RUNNING, ("not running")); 3624 3625 if (sc->sc_tx_timer > 0) { 3626 if (--sc->sc_tx_timer == 0) { 3627 if_printf(ifp, "device timeout\n"); 3628 ieee80211_runtask(ic, &sc->sc_reinit_task); 3629 return; 3630 } 3631 } 3632 callout_reset(&sc->watchdog_to, hz, iwn_watchdog, sc); 3633 } 3634 3635 static int 3636 iwn_ioctl(struct ifnet *ifp, u_long cmd, caddr_t data) 3637 { 3638 struct iwn_softc *sc = ifp->if_softc; 3639 struct ieee80211com *ic = ifp->if_l2com; 3640 struct ieee80211vap *vap = TAILQ_FIRST(&ic->ic_vaps); 3641 struct ifreq *ifr = (struct ifreq *) data; 3642 int error = 0, startall = 0, stop = 0; 3643 3644 switch (cmd) { 3645 case SIOCGIFADDR: 3646 error = ether_ioctl(ifp, cmd, data); 3647 break; 3648 case SIOCSIFFLAGS: 3649 IWN_LOCK(sc); 3650 if (ifp->if_flags & IFF_UP) { 3651 if (!(ifp->if_drv_flags & IFF_DRV_RUNNING)) { 3652 iwn_init_locked(sc); 3653 if (IWN_READ(sc, IWN_GP_CNTRL) & IWN_GP_CNTRL_RFKILL) 3654 startall = 1; 3655 else 3656 stop = 1; 3657 } 3658 } else { 3659 if (ifp->if_drv_flags & IFF_DRV_RUNNING) 3660 iwn_stop_locked(sc); 3661 } 3662 IWN_UNLOCK(sc); 3663 if (startall) 3664 ieee80211_start_all(ic); 3665 else if (vap != NULL && stop) 3666 ieee80211_stop(vap); 3667 break; 3668 case SIOCGIFMEDIA: 3669 error = ifmedia_ioctl(ifp, ifr, &ic->ic_media, cmd); 3670 break; 3671 default: 3672 error = EINVAL; 3673 break; 3674 } 3675 return error; 3676 } 3677 3678 /* 3679 * Send a command to the firmware. 3680 */ 3681 static int 3682 iwn_cmd(struct iwn_softc *sc, int code, const void *buf, int size, int async) 3683 { 3684 struct iwn_tx_ring *ring = &sc->txq[4]; 3685 struct iwn_tx_desc *desc; 3686 struct iwn_tx_data *data; 3687 struct iwn_tx_cmd *cmd; 3688 struct mbuf *m; 3689 bus_addr_t paddr; 3690 int totlen, error; 3691 3692 IWN_LOCK_ASSERT(sc); 3693 3694 desc = &ring->desc[ring->cur]; 3695 data = &ring->data[ring->cur]; 3696 totlen = 4 + size; 3697 3698 if (size > sizeof cmd->data) { 3699 /* Command is too large to fit in a descriptor. */ 3700 if (totlen > MCLBYTES) 3701 return EINVAL; 3702 m = m_getjcl(M_DONTWAIT, MT_DATA, M_PKTHDR, MJUMPAGESIZE); 3703 if (m == NULL) 3704 return ENOMEM; 3705 cmd = mtod(m, struct iwn_tx_cmd *); 3706 error = bus_dmamap_load(ring->data_dmat, data->map, cmd, 3707 totlen, iwn_dma_map_addr, &paddr, BUS_DMA_NOWAIT); 3708 if (error != 0) { 3709 m_freem(m); 3710 return error; 3711 } 3712 data->m = m; 3713 } else { 3714 cmd = &ring->cmd[ring->cur]; 3715 paddr = data->cmd_paddr; 3716 } 3717 3718 cmd->code = code; 3719 cmd->flags = 0; 3720 cmd->qid = ring->qid; 3721 cmd->idx = ring->cur; 3722 memcpy(cmd->data, buf, size); 3723 3724 desc->nsegs = 1; 3725 desc->segs[0].addr = htole32(IWN_LOADDR(paddr)); 3726 desc->segs[0].len = htole16(IWN_HIADDR(paddr) | totlen << 4); 3727 3728 DPRINTF(sc, IWN_DEBUG_CMD, "%s: %s (0x%x) flags %d qid %d idx %d\n", 3729 __func__, iwn_intr_str(cmd->code), cmd->code, 3730 cmd->flags, cmd->qid, cmd->idx); 3731 3732 if (size > sizeof cmd->data) { 3733 bus_dmamap_sync(ring->data_dmat, data->map, 3734 BUS_DMASYNC_PREWRITE); 3735 } else { 3736 bus_dmamap_sync(ring->data_dmat, ring->cmd_dma.map, 3737 BUS_DMASYNC_PREWRITE); 3738 } 3739 bus_dmamap_sync(ring->desc_dma.tag, ring->desc_dma.map, 3740 BUS_DMASYNC_PREWRITE); 3741 3742 #ifdef notyet 3743 /* Update TX scheduler. */ 3744 ops->update_sched(sc, ring->qid, ring->cur, 0, 0); 3745 #endif 3746 3747 /* Kick command ring. */ 3748 ring->cur = (ring->cur + 1) % IWN_TX_RING_COUNT; 3749 IWN_WRITE(sc, IWN_HBUS_TARG_WRPTR, ring->qid << 8 | ring->cur); 3750 3751 return async ? 0 : msleep(desc, &sc->sc_mtx, PCATCH, "iwncmd", hz); 3752 } 3753 3754 static int 3755 iwn4965_add_node(struct iwn_softc *sc, struct iwn_node_info *node, int async) 3756 { 3757 struct iwn4965_node_info hnode; 3758 caddr_t src, dst; 3759 3760 /* 3761 * We use the node structure for 5000 Series internally (it is 3762 * a superset of the one for 4965AGN). We thus copy the common 3763 * fields before sending the command. 3764 */ 3765 src = (caddr_t)node; 3766 dst = (caddr_t)&hnode; 3767 memcpy(dst, src, 48); 3768 /* Skip TSC, RX MIC and TX MIC fields from ``src''. */ 3769 memcpy(dst + 48, src + 72, 20); 3770 return iwn_cmd(sc, IWN_CMD_ADD_NODE, &hnode, sizeof hnode, async); 3771 } 3772 3773 static int 3774 iwn5000_add_node(struct iwn_softc *sc, struct iwn_node_info *node, int async) 3775 { 3776 /* Direct mapping. */ 3777 return iwn_cmd(sc, IWN_CMD_ADD_NODE, node, sizeof (*node), async); 3778 } 3779 3780 static int 3781 iwn_set_link_quality(struct iwn_softc *sc, struct ieee80211_node *ni) 3782 { 3783 struct iwn_node *wn = (void *)ni; 3784 struct ieee80211_rateset *rs = &ni->ni_rates; 3785 struct iwn_cmd_link_quality linkq; 3786 const struct iwn_rate *rinfo; 3787 uint8_t txant; 3788 int i, txrate; 3789 3790 /* Use the first valid TX antenna. */ 3791 txant = IWN_LSB(sc->txchainmask); 3792 3793 memset(&linkq, 0, sizeof linkq); 3794 linkq.id = wn->id; 3795 linkq.antmsk_1stream = txant; 3796 linkq.antmsk_2stream = IWN_ANT_AB; 3797 linkq.ampdu_max = 31; 3798 linkq.ampdu_threshold = 3; 3799 linkq.ampdu_limit = htole16(4000); /* 4ms */ 3800 3801 /* Start at highest available bit-rate. */ 3802 txrate = rs->rs_nrates - 1; 3803 for (i = 0; i < IWN_MAX_TX_RETRIES; i++) { 3804 rinfo = &iwn_rates[wn->ridx[txrate]]; 3805 linkq.retry[i].plcp = rinfo->plcp; 3806 linkq.retry[i].rflags = rinfo->flags; 3807 linkq.retry[i].rflags |= IWN_RFLAG_ANT(txant); 3808 /* Next retry at immediate lower bit-rate. */ 3809 if (txrate > 0) 3810 txrate--; 3811 } 3812 return iwn_cmd(sc, IWN_CMD_LINK_QUALITY, &linkq, sizeof linkq, 1); 3813 } 3814 3815 /* 3816 * Broadcast node is used to send group-addressed and management frames. 3817 */ 3818 static int 3819 iwn_add_broadcast_node(struct iwn_softc *sc, int async) 3820 { 3821 struct iwn_ops *ops = &sc->ops; 3822 struct ifnet *ifp = sc->sc_ifp; 3823 struct ieee80211com *ic = ifp->if_l2com; 3824 struct iwn_node_info node; 3825 struct iwn_cmd_link_quality linkq; 3826 const struct iwn_rate *rinfo; 3827 uint8_t txant; 3828 int i, error; 3829 3830 memset(&node, 0, sizeof node); 3831 IEEE80211_ADDR_COPY(node.macaddr, ifp->if_broadcastaddr); 3832 node.id = sc->broadcast_id; 3833 DPRINTF(sc, IWN_DEBUG_RESET, "%s: adding broadcast node\n", __func__); 3834 if ((error = ops->add_node(sc, &node, async)) != 0) 3835 return error; 3836 3837 /* Use the first valid TX antenna. */ 3838 txant = IWN_LSB(sc->txchainmask); 3839 3840 memset(&linkq, 0, sizeof linkq); 3841 linkq.id = sc->broadcast_id; 3842 linkq.antmsk_1stream = txant; 3843 linkq.antmsk_2stream = IWN_ANT_AB; 3844 linkq.ampdu_max = 64; 3845 linkq.ampdu_threshold = 3; 3846 linkq.ampdu_limit = htole16(4000); /* 4ms */ 3847 3848 /* Use lowest mandatory bit-rate. */ 3849 if (IEEE80211_IS_CHAN_5GHZ(ic->ic_curchan)) 3850 rinfo = &iwn_rates[IWN_RIDX_OFDM6]; 3851 else 3852 rinfo = &iwn_rates[IWN_RIDX_CCK1]; 3853 linkq.retry[0].plcp = rinfo->plcp; 3854 linkq.retry[0].rflags = rinfo->flags; 3855 linkq.retry[0].rflags |= IWN_RFLAG_ANT(txant); 3856 /* Use same bit-rate for all TX retries. */ 3857 for (i = 1; i < IWN_MAX_TX_RETRIES; i++) { 3858 linkq.retry[i].plcp = linkq.retry[0].plcp; 3859 linkq.retry[i].rflags = linkq.retry[0].rflags; 3860 } 3861 return iwn_cmd(sc, IWN_CMD_LINK_QUALITY, &linkq, sizeof linkq, async); 3862 } 3863 3864 static int 3865 iwn_updateedca(struct ieee80211com *ic) 3866 { 3867 #define IWN_EXP2(x) ((1 << (x)) - 1) /* CWmin = 2^ECWmin - 1 */ 3868 struct iwn_softc *sc = ic->ic_ifp->if_softc; 3869 struct iwn_edca_params cmd; 3870 int aci; 3871 3872 memset(&cmd, 0, sizeof cmd); 3873 cmd.flags = htole32(IWN_EDCA_UPDATE); 3874 for (aci = 0; aci < WME_NUM_AC; aci++) { 3875 const struct wmeParams *ac = 3876 &ic->ic_wme.wme_chanParams.cap_wmeParams[aci]; 3877 cmd.ac[aci].aifsn = ac->wmep_aifsn; 3878 cmd.ac[aci].cwmin = htole16(IWN_EXP2(ac->wmep_logcwmin)); 3879 cmd.ac[aci].cwmax = htole16(IWN_EXP2(ac->wmep_logcwmax)); 3880 cmd.ac[aci].txoplimit = 3881 htole16(IEEE80211_TXOP_TO_US(ac->wmep_txopLimit)); 3882 } 3883 IEEE80211_UNLOCK(ic); 3884 IWN_LOCK(sc); 3885 (void)iwn_cmd(sc, IWN_CMD_EDCA_PARAMS, &cmd, sizeof cmd, 1); 3886 IWN_UNLOCK(sc); 3887 IEEE80211_LOCK(ic); 3888 return 0; 3889 #undef IWN_EXP2 3890 } 3891 3892 static void 3893 iwn_update_mcast(struct ifnet *ifp) 3894 { 3895 /* Ignore */ 3896 } 3897 3898 static void 3899 iwn_set_led(struct iwn_softc *sc, uint8_t which, uint8_t off, uint8_t on) 3900 { 3901 struct iwn_cmd_led led; 3902 3903 /* Clear microcode LED ownership. */ 3904 IWN_CLRBITS(sc, IWN_LED, IWN_LED_BSM_CTRL); 3905 3906 led.which = which; 3907 led.unit = htole32(10000); /* on/off in unit of 100ms */ 3908 led.off = off; 3909 led.on = on; 3910 (void)iwn_cmd(sc, IWN_CMD_SET_LED, &led, sizeof led, 1); 3911 } 3912 3913 /* 3914 * Set the critical temperature at which the firmware will stop the radio 3915 * and notify us. 3916 */ 3917 static int 3918 iwn_set_critical_temp(struct iwn_softc *sc) 3919 { 3920 struct iwn_critical_temp crit; 3921 int32_t temp; 3922 3923 IWN_WRITE(sc, IWN_UCODE_GP1_CLR, IWN_UCODE_GP1_CTEMP_STOP_RF); 3924 3925 if (sc->hw_type == IWN_HW_REV_TYPE_5150) 3926 temp = (IWN_CTOK(110) - sc->temp_off) * -5; 3927 else if (sc->hw_type == IWN_HW_REV_TYPE_4965) 3928 temp = IWN_CTOK(110); 3929 else 3930 temp = 110; 3931 memset(&crit, 0, sizeof crit); 3932 crit.tempR = htole32(temp); 3933 DPRINTF(sc, IWN_DEBUG_RESET, "setting critical temp to %d\n", temp); 3934 return iwn_cmd(sc, IWN_CMD_SET_CRITICAL_TEMP, &crit, sizeof crit, 0); 3935 } 3936 3937 static int 3938 iwn_set_timing(struct iwn_softc *sc, struct ieee80211_node *ni) 3939 { 3940 struct iwn_cmd_timing cmd; 3941 uint64_t val, mod; 3942 3943 memset(&cmd, 0, sizeof cmd); 3944 memcpy(&cmd.tstamp, ni->ni_tstamp.data, sizeof (uint64_t)); 3945 cmd.bintval = htole16(ni->ni_intval); 3946 cmd.lintval = htole16(10); 3947 3948 /* Compute remaining time until next beacon. */ 3949 val = (uint64_t)ni->ni_intval * IEEE80211_DUR_TU; 3950 mod = le64toh(cmd.tstamp) % val; 3951 cmd.binitval = htole32((uint32_t)(val - mod)); 3952 3953 DPRINTF(sc, IWN_DEBUG_RESET, "timing bintval=%u tstamp=%ju, init=%u\n", 3954 ni->ni_intval, le64toh(cmd.tstamp), (uint32_t)(val - mod)); 3955 3956 return iwn_cmd(sc, IWN_CMD_TIMING, &cmd, sizeof cmd, 1); 3957 } 3958 3959 static void 3960 iwn4965_power_calibration(struct iwn_softc *sc, int temp) 3961 { 3962 struct ifnet *ifp = sc->sc_ifp; 3963 struct ieee80211com *ic = ifp->if_l2com; 3964 3965 /* Adjust TX power if need be (delta >= 3 degC). */ 3966 DPRINTF(sc, IWN_DEBUG_CALIBRATE, "%s: temperature %d->%d\n", 3967 __func__, sc->temp, temp); 3968 if (abs(temp - sc->temp) >= 3) { 3969 /* Record temperature of last calibration. */ 3970 sc->temp = temp; 3971 (void)iwn4965_set_txpower(sc, ic->ic_bsschan, 1); 3972 } 3973 } 3974 3975 /* 3976 * Set TX power for current channel (each rate has its own power settings). 3977 * This function takes into account the regulatory information from EEPROM, 3978 * the current temperature and the current voltage. 3979 */ 3980 static int 3981 iwn4965_set_txpower(struct iwn_softc *sc, struct ieee80211_channel *ch, 3982 int async) 3983 { 3984 /* Fixed-point arithmetic division using a n-bit fractional part. */ 3985 #define fdivround(a, b, n) \ 3986 ((((1 << n) * (a)) / (b) + (1 << n) / 2) / (1 << n)) 3987 /* Linear interpolation. */ 3988 #define interpolate(x, x1, y1, x2, y2, n) \ 3989 ((y1) + fdivround(((int)(x) - (x1)) * ((y2) - (y1)), (x2) - (x1), n)) 3990 3991 static const int tdiv[IWN_NATTEN_GROUPS] = { 9, 8, 8, 8, 6 }; 3992 struct iwn_ucode_info *uc = &sc->ucode_info; 3993 struct iwn4965_cmd_txpower cmd; 3994 struct iwn4965_eeprom_chan_samples *chans; 3995 const uint8_t *rf_gain, *dsp_gain; 3996 int32_t vdiff, tdiff; 3997 int i, c, grp, maxpwr; 3998 uint8_t chan; 3999 4000 /* Retrieve current channel from last RXON. */ 4001 chan = sc->rxon.chan; 4002 DPRINTF(sc, IWN_DEBUG_RESET, "setting TX power for channel %d\n", 4003 chan); 4004 4005 memset(&cmd, 0, sizeof cmd); 4006 cmd.band = IEEE80211_IS_CHAN_5GHZ(ch) ? 0 : 1; 4007 cmd.chan = chan; 4008 4009 if (IEEE80211_IS_CHAN_5GHZ(ch)) { 4010 maxpwr = sc->maxpwr5GHz; 4011 rf_gain = iwn4965_rf_gain_5ghz; 4012 dsp_gain = iwn4965_dsp_gain_5ghz; 4013 } else { 4014 maxpwr = sc->maxpwr2GHz; 4015 rf_gain = iwn4965_rf_gain_2ghz; 4016 dsp_gain = iwn4965_dsp_gain_2ghz; 4017 } 4018 4019 /* Compute voltage compensation. */ 4020 vdiff = ((int32_t)le32toh(uc->volt) - sc->eeprom_voltage) / 7; 4021 if (vdiff > 0) 4022 vdiff *= 2; 4023 if (abs(vdiff) > 2) 4024 vdiff = 0; 4025 DPRINTF(sc, IWN_DEBUG_CALIBRATE | IWN_DEBUG_TXPOW, 4026 "%s: voltage compensation=%d (UCODE=%d, EEPROM=%d)\n", 4027 __func__, vdiff, le32toh(uc->volt), sc->eeprom_voltage); 4028 4029 /* Get channel attenuation group. */ 4030 if (chan <= 20) /* 1-20 */ 4031 grp = 4; 4032 else if (chan <= 43) /* 34-43 */ 4033 grp = 0; 4034 else if (chan <= 70) /* 44-70 */ 4035 grp = 1; 4036 else if (chan <= 124) /* 71-124 */ 4037 grp = 2; 4038 else /* 125-200 */ 4039 grp = 3; 4040 DPRINTF(sc, IWN_DEBUG_CALIBRATE | IWN_DEBUG_TXPOW, 4041 "%s: chan %d, attenuation group=%d\n", __func__, chan, grp); 4042 4043 /* Get channel sub-band. */ 4044 for (i = 0; i < IWN_NBANDS; i++) 4045 if (sc->bands[i].lo != 0 && 4046 sc->bands[i].lo <= chan && chan <= sc->bands[i].hi) 4047 break; 4048 if (i == IWN_NBANDS) /* Can't happen in real-life. */ 4049 return EINVAL; 4050 chans = sc->bands[i].chans; 4051 DPRINTF(sc, IWN_DEBUG_CALIBRATE | IWN_DEBUG_TXPOW, 4052 "%s: chan %d sub-band=%d\n", __func__, chan, i); 4053 4054 for (c = 0; c < 2; c++) { 4055 uint8_t power, gain, temp; 4056 int maxchpwr, pwr, ridx, idx; 4057 4058 power = interpolate(chan, 4059 chans[0].num, chans[0].samples[c][1].power, 4060 chans[1].num, chans[1].samples[c][1].power, 1); 4061 gain = interpolate(chan, 4062 chans[0].num, chans[0].samples[c][1].gain, 4063 chans[1].num, chans[1].samples[c][1].gain, 1); 4064 temp = interpolate(chan, 4065 chans[0].num, chans[0].samples[c][1].temp, 4066 chans[1].num, chans[1].samples[c][1].temp, 1); 4067 DPRINTF(sc, IWN_DEBUG_CALIBRATE | IWN_DEBUG_TXPOW, 4068 "%s: Tx chain %d: power=%d gain=%d temp=%d\n", 4069 __func__, c, power, gain, temp); 4070 4071 /* Compute temperature compensation. */ 4072 tdiff = ((sc->temp - temp) * 2) / tdiv[grp]; 4073 DPRINTF(sc, IWN_DEBUG_CALIBRATE | IWN_DEBUG_TXPOW, 4074 "%s: temperature compensation=%d (current=%d, EEPROM=%d)\n", 4075 __func__, tdiff, sc->temp, temp); 4076 4077 for (ridx = 0; ridx <= IWN_RIDX_MAX; ridx++) { 4078 /* Convert dBm to half-dBm. */ 4079 maxchpwr = sc->maxpwr[chan] * 2; 4080 if ((ridx / 8) & 1) 4081 maxchpwr -= 6; /* MIMO 2T: -3dB */ 4082 4083 pwr = maxpwr; 4084 4085 /* Adjust TX power based on rate. */ 4086 if ((ridx % 8) == 5) 4087 pwr -= 15; /* OFDM48: -7.5dB */ 4088 else if ((ridx % 8) == 6) 4089 pwr -= 17; /* OFDM54: -8.5dB */ 4090 else if ((ridx % 8) == 7) 4091 pwr -= 20; /* OFDM60: -10dB */ 4092 else 4093 pwr -= 10; /* Others: -5dB */ 4094 4095 /* Do not exceed channel max TX power. */ 4096 if (pwr > maxchpwr) 4097 pwr = maxchpwr; 4098 4099 idx = gain - (pwr - power) - tdiff - vdiff; 4100 if ((ridx / 8) & 1) /* MIMO */ 4101 idx += (int32_t)le32toh(uc->atten[grp][c]); 4102 4103 if (cmd.band == 0) 4104 idx += 9; /* 5GHz */ 4105 if (ridx == IWN_RIDX_MAX) 4106 idx += 5; /* CCK */ 4107 4108 /* Make sure idx stays in a valid range. */ 4109 if (idx < 0) 4110 idx = 0; 4111 else if (idx > IWN4965_MAX_PWR_INDEX) 4112 idx = IWN4965_MAX_PWR_INDEX; 4113 4114 DPRINTF(sc, IWN_DEBUG_CALIBRATE | IWN_DEBUG_TXPOW, 4115 "%s: Tx chain %d, rate idx %d: power=%d\n", 4116 __func__, c, ridx, idx); 4117 cmd.power[ridx].rf_gain[c] = rf_gain[idx]; 4118 cmd.power[ridx].dsp_gain[c] = dsp_gain[idx]; 4119 } 4120 } 4121 4122 DPRINTF(sc, IWN_DEBUG_CALIBRATE | IWN_DEBUG_TXPOW, 4123 "%s: set tx power for chan %d\n", __func__, chan); 4124 return iwn_cmd(sc, IWN_CMD_TXPOWER, &cmd, sizeof cmd, async); 4125 4126 #undef interpolate 4127 #undef fdivround 4128 } 4129 4130 static int 4131 iwn5000_set_txpower(struct iwn_softc *sc, struct ieee80211_channel *ch, 4132 int async) 4133 { 4134 struct iwn5000_cmd_txpower cmd; 4135 4136 /* 4137 * TX power calibration is handled automatically by the firmware 4138 * for 5000 Series. 4139 */ 4140 memset(&cmd, 0, sizeof cmd); 4141 cmd.global_limit = 2 * IWN5000_TXPOWER_MAX_DBM; /* 16 dBm */ 4142 cmd.flags = IWN5000_TXPOWER_NO_CLOSED; 4143 cmd.srv_limit = IWN5000_TXPOWER_AUTO; 4144 DPRINTF(sc, IWN_DEBUG_CALIBRATE, "%s: setting TX power\n", __func__); 4145 return iwn_cmd(sc, IWN_CMD_TXPOWER_DBM, &cmd, sizeof cmd, async); 4146 } 4147 4148 /* 4149 * Retrieve the maximum RSSI (in dBm) among receivers. 4150 */ 4151 static int 4152 iwn4965_get_rssi(struct iwn_softc *sc, struct iwn_rx_stat *stat) 4153 { 4154 struct iwn4965_rx_phystat *phy = (void *)stat->phybuf; 4155 uint8_t mask, agc; 4156 int rssi; 4157 4158 mask = (le16toh(phy->antenna) >> 4) & IWN_ANT_ABC; 4159 agc = (le16toh(phy->agc) >> 7) & 0x7f; 4160 4161 rssi = 0; 4162 if (mask & IWN_ANT_A) 4163 rssi = MAX(rssi, phy->rssi[0]); 4164 if (mask & IWN_ANT_B) 4165 rssi = MAX(rssi, phy->rssi[2]); 4166 if (mask & IWN_ANT_C) 4167 rssi = MAX(rssi, phy->rssi[4]); 4168 4169 DPRINTF(sc, IWN_DEBUG_RECV, 4170 "%s: agc %d mask 0x%x rssi %d %d %d result %d\n", __func__, agc, 4171 mask, phy->rssi[0], phy->rssi[2], phy->rssi[4], 4172 rssi - agc - IWN_RSSI_TO_DBM); 4173 return rssi - agc - IWN_RSSI_TO_DBM; 4174 } 4175 4176 static int 4177 iwn5000_get_rssi(struct iwn_softc *sc, struct iwn_rx_stat *stat) 4178 { 4179 struct iwn5000_rx_phystat *phy = (void *)stat->phybuf; 4180 uint8_t agc; 4181 int rssi; 4182 4183 agc = (le32toh(phy->agc) >> 9) & 0x7f; 4184 4185 rssi = MAX(le16toh(phy->rssi[0]) & 0xff, 4186 le16toh(phy->rssi[1]) & 0xff); 4187 rssi = MAX(le16toh(phy->rssi[2]) & 0xff, rssi); 4188 4189 DPRINTF(sc, IWN_DEBUG_RECV, 4190 "%s: agc %d rssi %d %d %d result %d\n", __func__, agc, 4191 phy->rssi[0], phy->rssi[1], phy->rssi[2], 4192 rssi - agc - IWN_RSSI_TO_DBM); 4193 return rssi - agc - IWN_RSSI_TO_DBM; 4194 } 4195 4196 /* 4197 * Retrieve the average noise (in dBm) among receivers. 4198 */ 4199 static int 4200 iwn_get_noise(const struct iwn_rx_general_stats *stats) 4201 { 4202 int i, total, nbant, noise; 4203 4204 total = nbant = 0; 4205 for (i = 0; i < 3; i++) { 4206 if ((noise = le32toh(stats->noise[i]) & 0xff) == 0) 4207 continue; 4208 total += noise; 4209 nbant++; 4210 } 4211 /* There should be at least one antenna but check anyway. */ 4212 return (nbant == 0) ? -127 : (total / nbant) - 107; 4213 } 4214 4215 /* 4216 * Compute temperature (in degC) from last received statistics. 4217 */ 4218 static int 4219 iwn4965_get_temperature(struct iwn_softc *sc) 4220 { 4221 struct iwn_ucode_info *uc = &sc->ucode_info; 4222 int32_t r1, r2, r3, r4, temp; 4223 4224 r1 = le32toh(uc->temp[0].chan20MHz); 4225 r2 = le32toh(uc->temp[1].chan20MHz); 4226 r3 = le32toh(uc->temp[2].chan20MHz); 4227 r4 = le32toh(sc->rawtemp); 4228 4229 if (r1 == r3) /* Prevents division by 0 (should not happen). */ 4230 return 0; 4231 4232 /* Sign-extend 23-bit R4 value to 32-bit. */ 4233 r4 = ((r4 & 0xffffff) ^ 0x800000) - 0x800000; 4234 /* Compute temperature in Kelvin. */ 4235 temp = (259 * (r4 - r2)) / (r3 - r1); 4236 temp = (temp * 97) / 100 + 8; 4237 4238 DPRINTF(sc, IWN_DEBUG_ANY, "temperature %dK/%dC\n", temp, 4239 IWN_KTOC(temp)); 4240 return IWN_KTOC(temp); 4241 } 4242 4243 static int 4244 iwn5000_get_temperature(struct iwn_softc *sc) 4245 { 4246 int32_t temp; 4247 4248 /* 4249 * Temperature is not used by the driver for 5000 Series because 4250 * TX power calibration is handled by firmware. 4251 */ 4252 temp = le32toh(sc->rawtemp); 4253 if (sc->hw_type == IWN_HW_REV_TYPE_5150) { 4254 temp = (temp / -5) + sc->temp_off; 4255 temp = IWN_KTOC(temp); 4256 } 4257 return temp; 4258 } 4259 4260 /* 4261 * Initialize sensitivity calibration state machine. 4262 */ 4263 static int 4264 iwn_init_sensitivity(struct iwn_softc *sc) 4265 { 4266 struct iwn_ops *ops = &sc->ops; 4267 struct iwn_calib_state *calib = &sc->calib; 4268 uint32_t flags; 4269 int error; 4270 4271 /* Reset calibration state machine. */ 4272 memset(calib, 0, sizeof (*calib)); 4273 calib->state = IWN_CALIB_STATE_INIT; 4274 calib->cck_state = IWN_CCK_STATE_HIFA; 4275 /* Set initial correlation values. */ 4276 calib->ofdm_x1 = sc->limits->min_ofdm_x1; 4277 calib->ofdm_mrc_x1 = sc->limits->min_ofdm_mrc_x1; 4278 calib->ofdm_x4 = sc->limits->min_ofdm_x4; 4279 calib->ofdm_mrc_x4 = sc->limits->min_ofdm_mrc_x4; 4280 calib->cck_x4 = 125; 4281 calib->cck_mrc_x4 = sc->limits->min_cck_mrc_x4; 4282 calib->energy_cck = sc->limits->energy_cck; 4283 4284 /* Write initial sensitivity. */ 4285 if ((error = iwn_send_sensitivity(sc)) != 0) 4286 return error; 4287 4288 /* Write initial gains. */ 4289 if ((error = ops->init_gains(sc)) != 0) 4290 return error; 4291 4292 /* Request statistics at each beacon interval. */ 4293 flags = 0; 4294 DPRINTF(sc, IWN_DEBUG_CALIBRATE, "%s: sending request for statistics\n", 4295 __func__); 4296 return iwn_cmd(sc, IWN_CMD_GET_STATISTICS, &flags, sizeof flags, 1); 4297 } 4298 4299 /* 4300 * Collect noise and RSSI statistics for the first 20 beacons received 4301 * after association and use them to determine connected antennas and 4302 * to set differential gains. 4303 */ 4304 static void 4305 iwn_collect_noise(struct iwn_softc *sc, 4306 const struct iwn_rx_general_stats *stats) 4307 { 4308 struct iwn_ops *ops = &sc->ops; 4309 struct iwn_calib_state *calib = &sc->calib; 4310 uint32_t val; 4311 int i; 4312 4313 /* Accumulate RSSI and noise for all 3 antennas. */ 4314 for (i = 0; i < 3; i++) { 4315 calib->rssi[i] += le32toh(stats->rssi[i]) & 0xff; 4316 calib->noise[i] += le32toh(stats->noise[i]) & 0xff; 4317 } 4318 /* NB: We update differential gains only once after 20 beacons. */ 4319 if (++calib->nbeacons < 20) 4320 return; 4321 4322 /* Determine highest average RSSI. */ 4323 val = MAX(calib->rssi[0], calib->rssi[1]); 4324 val = MAX(calib->rssi[2], val); 4325 4326 /* Determine which antennas are connected. */ 4327 sc->chainmask = sc->rxchainmask; 4328 for (i = 0; i < 3; i++) 4329 if (val - calib->rssi[i] > 15 * 20) 4330 sc->chainmask &= ~(1 << i); 4331 DPRINTF(sc, IWN_DEBUG_CALIBRATE, 4332 "%s: RX chains mask: theoretical=0x%x, actual=0x%x\n", 4333 __func__, sc->rxchainmask, sc->chainmask); 4334 4335 /* If none of the TX antennas are connected, keep at least one. */ 4336 if ((sc->chainmask & sc->txchainmask) == 0) 4337 sc->chainmask |= IWN_LSB(sc->txchainmask); 4338 4339 (void)ops->set_gains(sc); 4340 calib->state = IWN_CALIB_STATE_RUN; 4341 4342 #ifdef notyet 4343 /* XXX Disable RX chains with no antennas connected. */ 4344 sc->rxon.rxchain = htole16(IWN_RXCHAIN_SEL(sc->chainmask)); 4345 (void)iwn_cmd(sc, IWN_CMD_RXON, &sc->rxon, sc->rxonsz, 1); 4346 #endif 4347 4348 #if 0 4349 /* XXX: not yet */ 4350 /* Enable power-saving mode if requested by user. */ 4351 if (sc->sc_ic.ic_flags & IEEE80211_F_PMGTON) 4352 (void)iwn_set_pslevel(sc, 0, 3, 1); 4353 #endif 4354 } 4355 4356 static int 4357 iwn4965_init_gains(struct iwn_softc *sc) 4358 { 4359 struct iwn_phy_calib_gain cmd; 4360 4361 memset(&cmd, 0, sizeof cmd); 4362 cmd.code = IWN4965_PHY_CALIB_DIFF_GAIN; 4363 /* Differential gains initially set to 0 for all 3 antennas. */ 4364 DPRINTF(sc, IWN_DEBUG_CALIBRATE, 4365 "%s: setting initial differential gains\n", __func__); 4366 return iwn_cmd(sc, IWN_CMD_PHY_CALIB, &cmd, sizeof cmd, 1); 4367 } 4368 4369 static int 4370 iwn5000_init_gains(struct iwn_softc *sc) 4371 { 4372 struct iwn_phy_calib cmd; 4373 4374 memset(&cmd, 0, sizeof cmd); 4375 cmd.code = sc->reset_noise_gain; 4376 cmd.ngroups = 1; 4377 cmd.isvalid = 1; 4378 DPRINTF(sc, IWN_DEBUG_CALIBRATE, 4379 "%s: setting initial differential gains\n", __func__); 4380 return iwn_cmd(sc, IWN_CMD_PHY_CALIB, &cmd, sizeof cmd, 1); 4381 } 4382 4383 static int 4384 iwn4965_set_gains(struct iwn_softc *sc) 4385 { 4386 struct iwn_calib_state *calib = &sc->calib; 4387 struct iwn_phy_calib_gain cmd; 4388 int i, delta, noise; 4389 4390 /* Get minimal noise among connected antennas. */ 4391 noise = INT_MAX; /* NB: There's at least one antenna. */ 4392 for (i = 0; i < 3; i++) 4393 if (sc->chainmask & (1 << i)) 4394 noise = MIN(calib->noise[i], noise); 4395 4396 memset(&cmd, 0, sizeof cmd); 4397 cmd.code = IWN4965_PHY_CALIB_DIFF_GAIN; 4398 /* Set differential gains for connected antennas. */ 4399 for (i = 0; i < 3; i++) { 4400 if (sc->chainmask & (1 << i)) { 4401 /* Compute attenuation (in unit of 1.5dB). */ 4402 delta = (noise - (int32_t)calib->noise[i]) / 30; 4403 /* NB: delta <= 0 */ 4404 /* Limit to [-4.5dB,0]. */ 4405 cmd.gain[i] = MIN(abs(delta), 3); 4406 if (delta < 0) 4407 cmd.gain[i] |= 1 << 2; /* sign bit */ 4408 } 4409 } 4410 DPRINTF(sc, IWN_DEBUG_CALIBRATE, 4411 "setting differential gains Ant A/B/C: %x/%x/%x (%x)\n", 4412 cmd.gain[0], cmd.gain[1], cmd.gain[2], sc->chainmask); 4413 return iwn_cmd(sc, IWN_CMD_PHY_CALIB, &cmd, sizeof cmd, 1); 4414 } 4415 4416 static int 4417 iwn5000_set_gains(struct iwn_softc *sc) 4418 { 4419 struct iwn_calib_state *calib = &sc->calib; 4420 struct iwn_phy_calib_gain cmd; 4421 int i, ant, div, delta; 4422 4423 /* We collected 20 beacons and !=6050 need a 1.5 factor. */ 4424 div = (sc->hw_type == IWN_HW_REV_TYPE_6050) ? 20 : 30; 4425 4426 memset(&cmd, 0, sizeof cmd); 4427 cmd.code = sc->noise_gain; 4428 cmd.ngroups = 1; 4429 cmd.isvalid = 1; 4430 /* Get first available RX antenna as referential. */ 4431 ant = IWN_LSB(sc->rxchainmask); 4432 /* Set differential gains for other antennas. */ 4433 for (i = ant + 1; i < 3; i++) { 4434 if (sc->chainmask & (1 << i)) { 4435 /* The delta is relative to antenna "ant". */ 4436 delta = ((int32_t)calib->noise[ant] - 4437 (int32_t)calib->noise[i]) / div; 4438 /* Limit to [-4.5dB,+4.5dB]. */ 4439 cmd.gain[i - 1] = MIN(abs(delta), 3); 4440 if (delta < 0) 4441 cmd.gain[i - 1] |= 1 << 2; /* sign bit */ 4442 } 4443 } 4444 DPRINTF(sc, IWN_DEBUG_CALIBRATE, 4445 "setting differential gains Ant B/C: %x/%x (%x)\n", 4446 cmd.gain[0], cmd.gain[1], sc->chainmask); 4447 return iwn_cmd(sc, IWN_CMD_PHY_CALIB, &cmd, sizeof cmd, 1); 4448 } 4449 4450 /* 4451 * Tune RF RX sensitivity based on the number of false alarms detected 4452 * during the last beacon period. 4453 */ 4454 static void 4455 iwn_tune_sensitivity(struct iwn_softc *sc, const struct iwn_rx_stats *stats) 4456 { 4457 #define inc(val, inc, max) \ 4458 if ((val) < (max)) { \ 4459 if ((val) < (max) - (inc)) \ 4460 (val) += (inc); \ 4461 else \ 4462 (val) = (max); \ 4463 needs_update = 1; \ 4464 } 4465 #define dec(val, dec, min) \ 4466 if ((val) > (min)) { \ 4467 if ((val) > (min) + (dec)) \ 4468 (val) -= (dec); \ 4469 else \ 4470 (val) = (min); \ 4471 needs_update = 1; \ 4472 } 4473 4474 const struct iwn_sensitivity_limits *limits = sc->limits; 4475 struct iwn_calib_state *calib = &sc->calib; 4476 uint32_t val, rxena, fa; 4477 uint32_t energy[3], energy_min; 4478 uint8_t noise[3], noise_ref; 4479 int i, needs_update = 0; 4480 4481 /* Check that we've been enabled long enough. */ 4482 if ((rxena = le32toh(stats->general.load)) == 0) 4483 return; 4484 4485 /* Compute number of false alarms since last call for OFDM. */ 4486 fa = le32toh(stats->ofdm.bad_plcp) - calib->bad_plcp_ofdm; 4487 fa += le32toh(stats->ofdm.fa) - calib->fa_ofdm; 4488 fa *= 200 * IEEE80211_DUR_TU; /* 200TU */ 4489 4490 /* Save counters values for next call. */ 4491 calib->bad_plcp_ofdm = le32toh(stats->ofdm.bad_plcp); 4492 calib->fa_ofdm = le32toh(stats->ofdm.fa); 4493 4494 if (fa > 50 * rxena) { 4495 /* High false alarm count, decrease sensitivity. */ 4496 DPRINTF(sc, IWN_DEBUG_CALIBRATE, 4497 "%s: OFDM high false alarm count: %u\n", __func__, fa); 4498 inc(calib->ofdm_x1, 1, limits->max_ofdm_x1); 4499 inc(calib->ofdm_mrc_x1, 1, limits->max_ofdm_mrc_x1); 4500 inc(calib->ofdm_x4, 1, limits->max_ofdm_x4); 4501 inc(calib->ofdm_mrc_x4, 1, limits->max_ofdm_mrc_x4); 4502 4503 } else if (fa < 5 * rxena) { 4504 /* Low false alarm count, increase sensitivity. */ 4505 DPRINTF(sc, IWN_DEBUG_CALIBRATE, 4506 "%s: OFDM low false alarm count: %u\n", __func__, fa); 4507 dec(calib->ofdm_x1, 1, limits->min_ofdm_x1); 4508 dec(calib->ofdm_mrc_x1, 1, limits->min_ofdm_mrc_x1); 4509 dec(calib->ofdm_x4, 1, limits->min_ofdm_x4); 4510 dec(calib->ofdm_mrc_x4, 1, limits->min_ofdm_mrc_x4); 4511 } 4512 4513 /* Compute maximum noise among 3 receivers. */ 4514 for (i = 0; i < 3; i++) 4515 noise[i] = (le32toh(stats->general.noise[i]) >> 8) & 0xff; 4516 val = MAX(noise[0], noise[1]); 4517 val = MAX(noise[2], val); 4518 /* Insert it into our samples table. */ 4519 calib->noise_samples[calib->cur_noise_sample] = val; 4520 calib->cur_noise_sample = (calib->cur_noise_sample + 1) % 20; 4521 4522 /* Compute maximum noise among last 20 samples. */ 4523 noise_ref = calib->noise_samples[0]; 4524 for (i = 1; i < 20; i++) 4525 noise_ref = MAX(noise_ref, calib->noise_samples[i]); 4526 4527 /* Compute maximum energy among 3 receivers. */ 4528 for (i = 0; i < 3; i++) 4529 energy[i] = le32toh(stats->general.energy[i]); 4530 val = MIN(energy[0], energy[1]); 4531 val = MIN(energy[2], val); 4532 /* Insert it into our samples table. */ 4533 calib->energy_samples[calib->cur_energy_sample] = val; 4534 calib->cur_energy_sample = (calib->cur_energy_sample + 1) % 10; 4535 4536 /* Compute minimum energy among last 10 samples. */ 4537 energy_min = calib->energy_samples[0]; 4538 for (i = 1; i < 10; i++) 4539 energy_min = MAX(energy_min, calib->energy_samples[i]); 4540 energy_min += 6; 4541 4542 /* Compute number of false alarms since last call for CCK. */ 4543 fa = le32toh(stats->cck.bad_plcp) - calib->bad_plcp_cck; 4544 fa += le32toh(stats->cck.fa) - calib->fa_cck; 4545 fa *= 200 * IEEE80211_DUR_TU; /* 200TU */ 4546 4547 /* Save counters values for next call. */ 4548 calib->bad_plcp_cck = le32toh(stats->cck.bad_plcp); 4549 calib->fa_cck = le32toh(stats->cck.fa); 4550 4551 if (fa > 50 * rxena) { 4552 /* High false alarm count, decrease sensitivity. */ 4553 DPRINTF(sc, IWN_DEBUG_CALIBRATE, 4554 "%s: CCK high false alarm count: %u\n", __func__, fa); 4555 calib->cck_state = IWN_CCK_STATE_HIFA; 4556 calib->low_fa = 0; 4557 4558 if (calib->cck_x4 > 160) { 4559 calib->noise_ref = noise_ref; 4560 if (calib->energy_cck > 2) 4561 dec(calib->energy_cck, 2, energy_min); 4562 } 4563 if (calib->cck_x4 < 160) { 4564 calib->cck_x4 = 161; 4565 needs_update = 1; 4566 } else 4567 inc(calib->cck_x4, 3, limits->max_cck_x4); 4568 4569 inc(calib->cck_mrc_x4, 3, limits->max_cck_mrc_x4); 4570 4571 } else if (fa < 5 * rxena) { 4572 /* Low false alarm count, increase sensitivity. */ 4573 DPRINTF(sc, IWN_DEBUG_CALIBRATE, 4574 "%s: CCK low false alarm count: %u\n", __func__, fa); 4575 calib->cck_state = IWN_CCK_STATE_LOFA; 4576 calib->low_fa++; 4577 4578 if (calib->cck_state != IWN_CCK_STATE_INIT && 4579 (((int32_t)calib->noise_ref - (int32_t)noise_ref) > 2 || 4580 calib->low_fa > 100)) { 4581 inc(calib->energy_cck, 2, limits->min_energy_cck); 4582 dec(calib->cck_x4, 3, limits->min_cck_x4); 4583 dec(calib->cck_mrc_x4, 3, limits->min_cck_mrc_x4); 4584 } 4585 } else { 4586 /* Not worth to increase or decrease sensitivity. */ 4587 DPRINTF(sc, IWN_DEBUG_CALIBRATE, 4588 "%s: CCK normal false alarm count: %u\n", __func__, fa); 4589 calib->low_fa = 0; 4590 calib->noise_ref = noise_ref; 4591 4592 if (calib->cck_state == IWN_CCK_STATE_HIFA) { 4593 /* Previous interval had many false alarms. */ 4594 dec(calib->energy_cck, 8, energy_min); 4595 } 4596 calib->cck_state = IWN_CCK_STATE_INIT; 4597 } 4598 4599 if (needs_update) 4600 (void)iwn_send_sensitivity(sc); 4601 #undef dec 4602 #undef inc 4603 } 4604 4605 static int 4606 iwn_send_sensitivity(struct iwn_softc *sc) 4607 { 4608 struct iwn_calib_state *calib = &sc->calib; 4609 struct iwn_enhanced_sensitivity_cmd cmd; 4610 int len; 4611 4612 memset(&cmd, 0, sizeof cmd); 4613 len = sizeof (struct iwn_sensitivity_cmd); 4614 cmd.which = IWN_SENSITIVITY_WORKTBL; 4615 /* OFDM modulation. */ 4616 cmd.corr_ofdm_x1 = htole16(calib->ofdm_x1); 4617 cmd.corr_ofdm_mrc_x1 = htole16(calib->ofdm_mrc_x1); 4618 cmd.corr_ofdm_x4 = htole16(calib->ofdm_x4); 4619 cmd.corr_ofdm_mrc_x4 = htole16(calib->ofdm_mrc_x4); 4620 cmd.energy_ofdm = htole16(sc->limits->energy_ofdm); 4621 cmd.energy_ofdm_th = htole16(62); 4622 /* CCK modulation. */ 4623 cmd.corr_cck_x4 = htole16(calib->cck_x4); 4624 cmd.corr_cck_mrc_x4 = htole16(calib->cck_mrc_x4); 4625 cmd.energy_cck = htole16(calib->energy_cck); 4626 /* Barker modulation: use default values. */ 4627 cmd.corr_barker = htole16(190); 4628 cmd.corr_barker_mrc = htole16(390); 4629 4630 DPRINTF(sc, IWN_DEBUG_CALIBRATE, 4631 "%s: set sensitivity %d/%d/%d/%d/%d/%d/%d\n", __func__, 4632 calib->ofdm_x1, calib->ofdm_mrc_x1, calib->ofdm_x4, 4633 calib->ofdm_mrc_x4, calib->cck_x4, 4634 calib->cck_mrc_x4, calib->energy_cck); 4635 4636 if (!(sc->sc_flags & IWN_FLAG_ENH_SENS)) 4637 goto send; 4638 /* Enhanced sensitivity settings. */ 4639 len = sizeof (struct iwn_enhanced_sensitivity_cmd); 4640 cmd.ofdm_det_slope_mrc = htole16(668); 4641 cmd.ofdm_det_icept_mrc = htole16(4); 4642 cmd.ofdm_det_slope = htole16(486); 4643 cmd.ofdm_det_icept = htole16(37); 4644 cmd.cck_det_slope_mrc = htole16(853); 4645 cmd.cck_det_icept_mrc = htole16(4); 4646 cmd.cck_det_slope = htole16(476); 4647 cmd.cck_det_icept = htole16(99); 4648 send: 4649 return iwn_cmd(sc, IWN_CMD_SET_SENSITIVITY, &cmd, len, 1); 4650 } 4651 4652 /* 4653 * Set STA mode power saving level (between 0 and 5). 4654 * Level 0 is CAM (Continuously Aware Mode), 5 is for maximum power saving. 4655 */ 4656 static int 4657 iwn_set_pslevel(struct iwn_softc *sc, int dtim, int level, int async) 4658 { 4659 struct iwn_pmgt_cmd cmd; 4660 const struct iwn_pmgt *pmgt; 4661 uint32_t max, skip_dtim; 4662 uint32_t reg; 4663 int i; 4664 4665 /* Select which PS parameters to use. */ 4666 if (dtim <= 2) 4667 pmgt = &iwn_pmgt[0][level]; 4668 else if (dtim <= 10) 4669 pmgt = &iwn_pmgt[1][level]; 4670 else 4671 pmgt = &iwn_pmgt[2][level]; 4672 4673 memset(&cmd, 0, sizeof cmd); 4674 if (level != 0) /* not CAM */ 4675 cmd.flags |= htole16(IWN_PS_ALLOW_SLEEP); 4676 if (level == 5) 4677 cmd.flags |= htole16(IWN_PS_FAST_PD); 4678 /* Retrieve PCIe Active State Power Management (ASPM). */ 4679 reg = pci_read_config(sc->sc_dev, sc->sc_cap_off + 0x10, 1); 4680 if (!(reg & 0x1)) /* L0s Entry disabled. */ 4681 cmd.flags |= htole16(IWN_PS_PCI_PMGT); 4682 cmd.rxtimeout = htole32(pmgt->rxtimeout * 1024); 4683 cmd.txtimeout = htole32(pmgt->txtimeout * 1024); 4684 4685 if (dtim == 0) { 4686 dtim = 1; 4687 skip_dtim = 0; 4688 } else 4689 skip_dtim = pmgt->skip_dtim; 4690 if (skip_dtim != 0) { 4691 cmd.flags |= htole16(IWN_PS_SLEEP_OVER_DTIM); 4692 max = pmgt->intval[4]; 4693 if (max == (uint32_t)-1) 4694 max = dtim * (skip_dtim + 1); 4695 else if (max > dtim) 4696 max = (max / dtim) * dtim; 4697 } else 4698 max = dtim; 4699 for (i = 0; i < 5; i++) 4700 cmd.intval[i] = htole32(MIN(max, pmgt->intval[i])); 4701 4702 DPRINTF(sc, IWN_DEBUG_RESET, "setting power saving level to %d\n", 4703 level); 4704 return iwn_cmd(sc, IWN_CMD_SET_POWER_MODE, &cmd, sizeof cmd, async); 4705 } 4706 4707 static int 4708 iwn_send_btcoex(struct iwn_softc *sc) 4709 { 4710 struct iwn_bluetooth cmd; 4711 4712 memset(&cmd, 0, sizeof cmd); 4713 cmd.flags = IWN_BT_COEX_CHAN_ANN | IWN_BT_COEX_BT_PRIO; 4714 cmd.lead_time = IWN_BT_LEAD_TIME_DEF; 4715 cmd.max_kill = IWN_BT_MAX_KILL_DEF; 4716 DPRINTF(sc, IWN_DEBUG_RESET, "%s: configuring bluetooth coexistence\n", 4717 __func__); 4718 return iwn_cmd(sc, IWN_CMD_BT_COEX, &cmd, sizeof(cmd), 0); 4719 } 4720 4721 static int 4722 iwn_send_advanced_btcoex(struct iwn_softc *sc) 4723 { 4724 static const uint32_t btcoex_3wire[12] = { 4725 0xaaaaaaaa, 0xaaaaaaaa, 0xaeaaaaaa, 0xaaaaaaaa, 4726 0xcc00ff28, 0x0000aaaa, 0xcc00aaaa, 0x0000aaaa, 4727 0xc0004000, 0x00004000, 0xf0005000, 0xf0005000, 4728 }; 4729 struct iwn6000_btcoex_config btconfig; 4730 struct iwn_btcoex_priotable btprio; 4731 struct iwn_btcoex_prot btprot; 4732 int error, i; 4733 4734 memset(&btconfig, 0, sizeof btconfig); 4735 btconfig.flags = 145; 4736 btconfig.max_kill = 5; 4737 btconfig.bt3_t7_timer = 1; 4738 btconfig.kill_ack = htole32(0xffff0000); 4739 btconfig.kill_cts = htole32(0xffff0000); 4740 btconfig.sample_time = 2; 4741 btconfig.bt3_t2_timer = 0xc; 4742 for (i = 0; i < 12; i++) 4743 btconfig.lookup_table[i] = htole32(btcoex_3wire[i]); 4744 btconfig.valid = htole16(0xff); 4745 btconfig.prio_boost = 0xf0; 4746 DPRINTF(sc, IWN_DEBUG_RESET, 4747 "%s: configuring advanced bluetooth coexistence\n", __func__); 4748 error = iwn_cmd(sc, IWN_CMD_BT_COEX, &btconfig, sizeof(btconfig), 1); 4749 if (error != 0) 4750 return error; 4751 4752 memset(&btprio, 0, sizeof btprio); 4753 btprio.calib_init1 = 0x6; 4754 btprio.calib_init2 = 0x7; 4755 btprio.calib_periodic_low1 = 0x2; 4756 btprio.calib_periodic_low2 = 0x3; 4757 btprio.calib_periodic_high1 = 0x4; 4758 btprio.calib_periodic_high2 = 0x5; 4759 btprio.dtim = 0x6; 4760 btprio.scan52 = 0x8; 4761 btprio.scan24 = 0xa; 4762 error = iwn_cmd(sc, IWN_CMD_BT_COEX_PRIOTABLE, &btprio, sizeof(btprio), 4763 1); 4764 if (error != 0) 4765 return error; 4766 4767 /* Force BT state machine change. */ 4768 memset(&btprot, 0, sizeof btprio); 4769 btprot.open = 1; 4770 btprot.type = 1; 4771 error = iwn_cmd(sc, IWN_CMD_BT_COEX_PROT, &btprot, sizeof(btprot), 1); 4772 if (error != 0) 4773 return error; 4774 btprot.open = 0; 4775 return iwn_cmd(sc, IWN_CMD_BT_COEX_PROT, &btprot, sizeof(btprot), 1); 4776 } 4777 4778 static int 4779 iwn_config(struct iwn_softc *sc) 4780 { 4781 struct iwn_ops *ops = &sc->ops; 4782 struct ifnet *ifp = sc->sc_ifp; 4783 struct ieee80211com *ic = ifp->if_l2com; 4784 uint32_t txmask; 4785 uint16_t rxchain; 4786 int error; 4787 4788 if (sc->hw_type == IWN_HW_REV_TYPE_6005) { 4789 /* Set radio temperature sensor offset. */ 4790 error = iwn5000_temp_offset_calib(sc); 4791 if (error != 0) { 4792 device_printf(sc->sc_dev, 4793 "%s: could not set temperature offset\n", __func__); 4794 return error; 4795 } 4796 } 4797 4798 /* Configure valid TX chains for >=5000 Series. */ 4799 if (sc->hw_type != IWN_HW_REV_TYPE_4965) { 4800 txmask = htole32(sc->txchainmask); 4801 DPRINTF(sc, IWN_DEBUG_RESET, 4802 "%s: configuring valid TX chains 0x%x\n", __func__, txmask); 4803 error = iwn_cmd(sc, IWN5000_CMD_TX_ANT_CONFIG, &txmask, 4804 sizeof txmask, 0); 4805 if (error != 0) { 4806 device_printf(sc->sc_dev, 4807 "%s: could not configure valid TX chains, " 4808 "error %d\n", __func__, error); 4809 return error; 4810 } 4811 } 4812 4813 /* Configure bluetooth coexistence. */ 4814 if (sc->sc_flags & IWN_FLAG_ADV_BTCOEX) 4815 error = iwn_send_advanced_btcoex(sc); 4816 else 4817 error = iwn_send_btcoex(sc); 4818 if (error != 0) { 4819 device_printf(sc->sc_dev, 4820 "%s: could not configure bluetooth coexistence, error %d\n", 4821 __func__, error); 4822 return error; 4823 } 4824 4825 /* Set mode, channel, RX filter and enable RX. */ 4826 memset(&sc->rxon, 0, sizeof (struct iwn_rxon)); 4827 IEEE80211_ADDR_COPY(sc->rxon.myaddr, IF_LLADDR(ifp)); 4828 IEEE80211_ADDR_COPY(sc->rxon.wlap, IF_LLADDR(ifp)); 4829 sc->rxon.chan = ieee80211_chan2ieee(ic, ic->ic_curchan); 4830 sc->rxon.flags = htole32(IWN_RXON_TSF | IWN_RXON_CTS_TO_SELF); 4831 if (IEEE80211_IS_CHAN_2GHZ(ic->ic_curchan)) 4832 sc->rxon.flags |= htole32(IWN_RXON_AUTO | IWN_RXON_24GHZ); 4833 switch (ic->ic_opmode) { 4834 case IEEE80211_M_STA: 4835 sc->rxon.mode = IWN_MODE_STA; 4836 sc->rxon.filter = htole32(IWN_FILTER_MULTICAST); 4837 break; 4838 case IEEE80211_M_MONITOR: 4839 sc->rxon.mode = IWN_MODE_MONITOR; 4840 sc->rxon.filter = htole32(IWN_FILTER_MULTICAST | 4841 IWN_FILTER_CTL | IWN_FILTER_PROMISC); 4842 break; 4843 default: 4844 /* Should not get there. */ 4845 break; 4846 } 4847 sc->rxon.cck_mask = 0x0f; /* not yet negotiated */ 4848 sc->rxon.ofdm_mask = 0xff; /* not yet negotiated */ 4849 sc->rxon.ht_single_mask = 0xff; 4850 sc->rxon.ht_dual_mask = 0xff; 4851 sc->rxon.ht_triple_mask = 0xff; 4852 rxchain = 4853 IWN_RXCHAIN_VALID(sc->rxchainmask) | 4854 IWN_RXCHAIN_MIMO_COUNT(2) | 4855 IWN_RXCHAIN_IDLE_COUNT(2); 4856 sc->rxon.rxchain = htole16(rxchain); 4857 DPRINTF(sc, IWN_DEBUG_RESET, "%s: setting configuration\n", __func__); 4858 error = iwn_cmd(sc, IWN_CMD_RXON, &sc->rxon, sc->rxonsz, 0); 4859 if (error != 0) { 4860 device_printf(sc->sc_dev, "%s: RXON command failed\n", 4861 __func__); 4862 return error; 4863 } 4864 4865 if ((error = iwn_add_broadcast_node(sc, 0)) != 0) { 4866 device_printf(sc->sc_dev, "%s: could not add broadcast node\n", 4867 __func__); 4868 return error; 4869 } 4870 4871 /* Configuration has changed, set TX power accordingly. */ 4872 if ((error = ops->set_txpower(sc, ic->ic_curchan, 0)) != 0) { 4873 device_printf(sc->sc_dev, "%s: could not set TX power\n", 4874 __func__); 4875 return error; 4876 } 4877 4878 if ((error = iwn_set_critical_temp(sc)) != 0) { 4879 device_printf(sc->sc_dev, 4880 "%s: could not set critical temperature\n", __func__); 4881 return error; 4882 } 4883 4884 /* Set power saving level to CAM during initialization. */ 4885 if ((error = iwn_set_pslevel(sc, 0, 0, 0)) != 0) { 4886 device_printf(sc->sc_dev, 4887 "%s: could not set power saving level\n", __func__); 4888 return error; 4889 } 4890 return 0; 4891 } 4892 4893 /* 4894 * Add an ssid element to a frame. 4895 */ 4896 static uint8_t * 4897 ieee80211_add_ssid(uint8_t *frm, const uint8_t *ssid, u_int len) 4898 { 4899 *frm++ = IEEE80211_ELEMID_SSID; 4900 *frm++ = len; 4901 memcpy(frm, ssid, len); 4902 return frm + len; 4903 } 4904 4905 static int 4906 iwn_scan(struct iwn_softc *sc) 4907 { 4908 struct ifnet *ifp = sc->sc_ifp; 4909 struct ieee80211com *ic = ifp->if_l2com; 4910 struct ieee80211_scan_state *ss = ic->ic_scan; /*XXX*/ 4911 struct iwn_scan_hdr *hdr; 4912 struct iwn_cmd_data *tx; 4913 struct iwn_scan_essid *essid; 4914 struct iwn_scan_chan *chan; 4915 struct ieee80211_frame *wh; 4916 struct ieee80211_rateset *rs; 4917 struct ieee80211_channel *c; 4918 uint8_t *buf, *frm; 4919 uint16_t rxchain; 4920 uint8_t txant; 4921 int buflen, error; 4922 4923 buf = malloc(IWN_SCAN_MAXSZ, M_DEVBUF, M_NOWAIT | M_ZERO); 4924 if (buf == NULL) { 4925 device_printf(sc->sc_dev, 4926 "%s: could not allocate buffer for scan command\n", 4927 __func__); 4928 return ENOMEM; 4929 } 4930 hdr = (struct iwn_scan_hdr *)buf; 4931 /* 4932 * Move to the next channel if no frames are received within 10ms 4933 * after sending the probe request. 4934 */ 4935 hdr->quiet_time = htole16(10); /* timeout in milliseconds */ 4936 hdr->quiet_threshold = htole16(1); /* min # of packets */ 4937 4938 /* Select antennas for scanning. */ 4939 rxchain = 4940 IWN_RXCHAIN_VALID(sc->rxchainmask) | 4941 IWN_RXCHAIN_FORCE_MIMO_SEL(sc->rxchainmask) | 4942 IWN_RXCHAIN_DRIVER_FORCE; 4943 if (IEEE80211_IS_CHAN_A(ic->ic_curchan) && 4944 sc->hw_type == IWN_HW_REV_TYPE_4965) { 4945 /* Ant A must be avoided in 5GHz because of an HW bug. */ 4946 rxchain |= IWN_RXCHAIN_FORCE_SEL(IWN_ANT_BC); 4947 } else /* Use all available RX antennas. */ 4948 rxchain |= IWN_RXCHAIN_FORCE_SEL(sc->rxchainmask); 4949 hdr->rxchain = htole16(rxchain); 4950 hdr->filter = htole32(IWN_FILTER_MULTICAST | IWN_FILTER_BEACON); 4951 4952 tx = (struct iwn_cmd_data *)(hdr + 1); 4953 tx->flags = htole32(IWN_TX_AUTO_SEQ); 4954 tx->id = sc->broadcast_id; 4955 tx->lifetime = htole32(IWN_LIFETIME_INFINITE); 4956 4957 if (IEEE80211_IS_CHAN_A(ic->ic_curchan)) { 4958 /* Send probe requests at 6Mbps. */ 4959 tx->plcp = iwn_rates[IWN_RIDX_OFDM6].plcp; 4960 rs = &ic->ic_sup_rates[IEEE80211_MODE_11A]; 4961 } else { 4962 hdr->flags = htole32(IWN_RXON_24GHZ | IWN_RXON_AUTO); 4963 /* Send probe requests at 1Mbps. */ 4964 tx->plcp = iwn_rates[IWN_RIDX_CCK1].plcp; 4965 tx->rflags = IWN_RFLAG_CCK; 4966 rs = &ic->ic_sup_rates[IEEE80211_MODE_11G]; 4967 } 4968 /* Use the first valid TX antenna. */ 4969 txant = IWN_LSB(sc->txchainmask); 4970 tx->rflags |= IWN_RFLAG_ANT(txant); 4971 4972 essid = (struct iwn_scan_essid *)(tx + 1); 4973 if (ss->ss_ssid[0].len != 0) { 4974 essid[0].id = IEEE80211_ELEMID_SSID; 4975 essid[0].len = ss->ss_ssid[0].len; 4976 memcpy(essid[0].data, ss->ss_ssid[0].ssid, ss->ss_ssid[0].len); 4977 } 4978 /* 4979 * Build a probe request frame. Most of the following code is a 4980 * copy & paste of what is done in net80211. 4981 */ 4982 wh = (struct ieee80211_frame *)(essid + 20); 4983 wh->i_fc[0] = IEEE80211_FC0_VERSION_0 | IEEE80211_FC0_TYPE_MGT | 4984 IEEE80211_FC0_SUBTYPE_PROBE_REQ; 4985 wh->i_fc[1] = IEEE80211_FC1_DIR_NODS; 4986 IEEE80211_ADDR_COPY(wh->i_addr1, ifp->if_broadcastaddr); 4987 IEEE80211_ADDR_COPY(wh->i_addr2, IF_LLADDR(ifp)); 4988 IEEE80211_ADDR_COPY(wh->i_addr3, ifp->if_broadcastaddr); 4989 *(uint16_t *)&wh->i_dur[0] = 0; /* filled by HW */ 4990 *(uint16_t *)&wh->i_seq[0] = 0; /* filled by HW */ 4991 4992 frm = (uint8_t *)(wh + 1); 4993 frm = ieee80211_add_ssid(frm, NULL, 0); 4994 frm = ieee80211_add_rates(frm, rs); 4995 if (rs->rs_nrates > IEEE80211_RATE_SIZE) 4996 frm = ieee80211_add_xrates(frm, rs); 4997 #if 0 /* HT */ 4998 if (ic->ic_flags & IEEE80211_F_HTON) 4999 frm = ieee80211_add_htcaps(frm, ic); 5000 #endif 5001 5002 /* Set length of probe request. */ 5003 tx->len = htole16(frm - (uint8_t *)wh); 5004 5005 c = ic->ic_curchan; 5006 chan = (struct iwn_scan_chan *)frm; 5007 chan->chan = htole16(ieee80211_chan2ieee(ic, c)); 5008 chan->flags = 0; 5009 if (ss->ss_nssid > 0) 5010 chan->flags |= htole32(IWN_CHAN_NPBREQS(1)); 5011 chan->dsp_gain = 0x6e; 5012 if (IEEE80211_IS_CHAN_5GHZ(c) && 5013 !(c->ic_flags & IEEE80211_CHAN_PASSIVE)) { 5014 chan->rf_gain = 0x3b; 5015 chan->active = htole16(24); 5016 chan->passive = htole16(110); 5017 chan->flags |= htole32(IWN_CHAN_ACTIVE); 5018 } else if (IEEE80211_IS_CHAN_5GHZ(c)) { 5019 chan->rf_gain = 0x3b; 5020 chan->active = htole16(24); 5021 if (sc->rxon.associd) 5022 chan->passive = htole16(78); 5023 else 5024 chan->passive = htole16(110); 5025 hdr->crc_threshold = 0xffff; 5026 } else if (!(c->ic_flags & IEEE80211_CHAN_PASSIVE)) { 5027 chan->rf_gain = 0x28; 5028 chan->active = htole16(36); 5029 chan->passive = htole16(120); 5030 chan->flags |= htole32(IWN_CHAN_ACTIVE); 5031 } else { 5032 chan->rf_gain = 0x28; 5033 chan->active = htole16(36); 5034 if (sc->rxon.associd) 5035 chan->passive = htole16(88); 5036 else 5037 chan->passive = htole16(120); 5038 hdr->crc_threshold = 0xffff; 5039 } 5040 5041 DPRINTF(sc, IWN_DEBUG_STATE, 5042 "%s: chan %u flags 0x%x rf_gain 0x%x " 5043 "dsp_gain 0x%x active 0x%x passive 0x%x\n", __func__, 5044 chan->chan, chan->flags, chan->rf_gain, chan->dsp_gain, 5045 chan->active, chan->passive); 5046 5047 hdr->nchan++; 5048 chan++; 5049 buflen = (uint8_t *)chan - buf; 5050 hdr->len = htole16(buflen); 5051 5052 DPRINTF(sc, IWN_DEBUG_STATE, "sending scan command nchan=%d\n", 5053 hdr->nchan); 5054 error = iwn_cmd(sc, IWN_CMD_SCAN, buf, buflen, 1); 5055 free(buf, M_DEVBUF); 5056 return error; 5057 } 5058 5059 static int 5060 iwn_auth(struct iwn_softc *sc, struct ieee80211vap *vap) 5061 { 5062 struct iwn_ops *ops = &sc->ops; 5063 struct ifnet *ifp = sc->sc_ifp; 5064 struct ieee80211com *ic = ifp->if_l2com; 5065 struct ieee80211_node *ni = vap->iv_bss; 5066 int error; 5067 5068 /* Update adapter configuration. */ 5069 IEEE80211_ADDR_COPY(sc->rxon.bssid, ni->ni_bssid); 5070 sc->rxon.chan = ieee80211_chan2ieee(ic, ni->ni_chan); 5071 sc->rxon.flags = htole32(IWN_RXON_TSF | IWN_RXON_CTS_TO_SELF); 5072 if (IEEE80211_IS_CHAN_2GHZ(ni->ni_chan)) 5073 sc->rxon.flags |= htole32(IWN_RXON_AUTO | IWN_RXON_24GHZ); 5074 if (ic->ic_flags & IEEE80211_F_SHSLOT) 5075 sc->rxon.flags |= htole32(IWN_RXON_SHSLOT); 5076 if (ic->ic_flags & IEEE80211_F_SHPREAMBLE) 5077 sc->rxon.flags |= htole32(IWN_RXON_SHPREAMBLE); 5078 if (IEEE80211_IS_CHAN_A(ni->ni_chan)) { 5079 sc->rxon.cck_mask = 0; 5080 sc->rxon.ofdm_mask = 0x15; 5081 } else if (IEEE80211_IS_CHAN_B(ni->ni_chan)) { 5082 sc->rxon.cck_mask = 0x03; 5083 sc->rxon.ofdm_mask = 0; 5084 } else { 5085 /* Assume 802.11b/g. */ 5086 sc->rxon.cck_mask = 0x0f; 5087 sc->rxon.ofdm_mask = 0x15; 5088 } 5089 DPRINTF(sc, IWN_DEBUG_STATE, "rxon chan %d flags %x cck %x ofdm %x\n", 5090 sc->rxon.chan, sc->rxon.flags, sc->rxon.cck_mask, 5091 sc->rxon.ofdm_mask); 5092 error = iwn_cmd(sc, IWN_CMD_RXON, &sc->rxon, sc->rxonsz, 1); 5093 if (error != 0) { 5094 device_printf(sc->sc_dev, "%s: RXON command failed, error %d\n", 5095 __func__, error); 5096 return error; 5097 } 5098 5099 /* Configuration has changed, set TX power accordingly. */ 5100 if ((error = ops->set_txpower(sc, ni->ni_chan, 1)) != 0) { 5101 device_printf(sc->sc_dev, 5102 "%s: could not set TX power, error %d\n", __func__, error); 5103 return error; 5104 } 5105 /* 5106 * Reconfiguring RXON clears the firmware nodes table so we must 5107 * add the broadcast node again. 5108 */ 5109 if ((error = iwn_add_broadcast_node(sc, 1)) != 0) { 5110 device_printf(sc->sc_dev, 5111 "%s: could not add broadcast node, error %d\n", __func__, 5112 error); 5113 return error; 5114 } 5115 return 0; 5116 } 5117 5118 static int 5119 iwn_run(struct iwn_softc *sc, struct ieee80211vap *vap) 5120 { 5121 #define MS(v,x) (((v) & x) >> x##_S) 5122 struct iwn_ops *ops = &sc->ops; 5123 struct ifnet *ifp = sc->sc_ifp; 5124 struct ieee80211com *ic = ifp->if_l2com; 5125 struct ieee80211_node *ni = vap->iv_bss; 5126 struct iwn_node_info node; 5127 int error; 5128 5129 if (ic->ic_opmode == IEEE80211_M_MONITOR) { 5130 /* Link LED blinks while monitoring. */ 5131 iwn_set_led(sc, IWN_LED_LINK, 5, 5); 5132 return 0; 5133 } 5134 if ((error = iwn_set_timing(sc, ni)) != 0) { 5135 device_printf(sc->sc_dev, 5136 "%s: could not set timing, error %d\n", __func__, error); 5137 return error; 5138 } 5139 5140 /* Update adapter configuration. */ 5141 IEEE80211_ADDR_COPY(sc->rxon.bssid, ni->ni_bssid); 5142 sc->rxon.associd = htole16(IEEE80211_AID(ni->ni_associd)); 5143 sc->rxon.chan = ieee80211_chan2ieee(ic, ni->ni_chan); 5144 sc->rxon.flags = htole32(IWN_RXON_TSF | IWN_RXON_CTS_TO_SELF); 5145 if (IEEE80211_IS_CHAN_2GHZ(ni->ni_chan)) 5146 sc->rxon.flags |= htole32(IWN_RXON_AUTO | IWN_RXON_24GHZ); 5147 if (ic->ic_flags & IEEE80211_F_SHSLOT) 5148 sc->rxon.flags |= htole32(IWN_RXON_SHSLOT); 5149 if (ic->ic_flags & IEEE80211_F_SHPREAMBLE) 5150 sc->rxon.flags |= htole32(IWN_RXON_SHPREAMBLE); 5151 if (IEEE80211_IS_CHAN_A(ni->ni_chan)) { 5152 sc->rxon.cck_mask = 0; 5153 sc->rxon.ofdm_mask = 0x15; 5154 } else if (IEEE80211_IS_CHAN_B(ni->ni_chan)) { 5155 sc->rxon.cck_mask = 0x03; 5156 sc->rxon.ofdm_mask = 0; 5157 } else { 5158 /* Assume 802.11b/g. */ 5159 sc->rxon.cck_mask = 0x0f; 5160 sc->rxon.ofdm_mask = 0x15; 5161 } 5162 #if 0 /* HT */ 5163 if (IEEE80211_IS_CHAN_HT(ni->ni_chan)) { 5164 sc->rxon.flags &= ~htole32(IWN_RXON_HT); 5165 if (IEEE80211_IS_CHAN_HT40U(ni->ni_chan)) 5166 sc->rxon.flags |= htole32(IWN_RXON_HT40U); 5167 else if (IEEE80211_IS_CHAN_HT40D(ni->ni_chan)) 5168 sc->rxon.flags |= htole32(IWN_RXON_HT40D); 5169 else 5170 sc->rxon.flags |= htole32(IWN_RXON_HT20); 5171 sc->rxon.rxchain = htole16( 5172 IWN_RXCHAIN_VALID(3) 5173 | IWN_RXCHAIN_MIMO_COUNT(3) 5174 | IWN_RXCHAIN_IDLE_COUNT(1) 5175 | IWN_RXCHAIN_MIMO_FORCE); 5176 5177 maxrxampdu = MS(ni->ni_htparam, IEEE80211_HTCAP_MAXRXAMPDU); 5178 ampdudensity = MS(ni->ni_htparam, IEEE80211_HTCAP_MPDUDENSITY); 5179 } else 5180 maxrxampdu = ampdudensity = 0; 5181 #endif 5182 sc->rxon.filter |= htole32(IWN_FILTER_BSS); 5183 DPRINTF(sc, IWN_DEBUG_STATE, "rxon chan %d flags %x\n", 5184 sc->rxon.chan, sc->rxon.flags); 5185 error = iwn_cmd(sc, IWN_CMD_RXON, &sc->rxon, sc->rxonsz, 1); 5186 if (error != 0) { 5187 device_printf(sc->sc_dev, 5188 "%s: could not update configuration, error %d\n", __func__, 5189 error); 5190 return error; 5191 } 5192 5193 /* Configuration has changed, set TX power accordingly. */ 5194 if ((error = ops->set_txpower(sc, ni->ni_chan, 1)) != 0) { 5195 device_printf(sc->sc_dev, 5196 "%s: could not set TX power, error %d\n", __func__, error); 5197 return error; 5198 } 5199 5200 /* Fake a join to initialize the TX rate. */ 5201 ((struct iwn_node *)ni)->id = IWN_ID_BSS; 5202 iwn_newassoc(ni, 1); 5203 5204 /* Add BSS node. */ 5205 memset(&node, 0, sizeof node); 5206 IEEE80211_ADDR_COPY(node.macaddr, ni->ni_macaddr); 5207 node.id = IWN_ID_BSS; 5208 #ifdef notyet 5209 node.htflags = htole32(IWN_AMDPU_SIZE_FACTOR(3) | 5210 IWN_AMDPU_DENSITY(5)); /* 2us */ 5211 #endif 5212 DPRINTF(sc, IWN_DEBUG_STATE, "%s: adding BSS node\n", __func__); 5213 error = ops->add_node(sc, &node, 1); 5214 if (error != 0) { 5215 device_printf(sc->sc_dev, 5216 "%s: could not add BSS node, error %d\n", __func__, error); 5217 return error; 5218 } 5219 DPRINTF(sc, IWN_DEBUG_STATE, "%s: setting link quality for node %d\n", 5220 __func__, node.id); 5221 if ((error = iwn_set_link_quality(sc, ni)) != 0) { 5222 device_printf(sc->sc_dev, 5223 "%s: could not setup link quality for node %d, error %d\n", 5224 __func__, node.id, error); 5225 return error; 5226 } 5227 5228 if ((error = iwn_init_sensitivity(sc)) != 0) { 5229 device_printf(sc->sc_dev, 5230 "%s: could not set sensitivity, error %d\n", __func__, 5231 error); 5232 return error; 5233 } 5234 /* Start periodic calibration timer. */ 5235 sc->calib.state = IWN_CALIB_STATE_ASSOC; 5236 sc->calib_cnt = 0; 5237 callout_reset(&sc->calib_to, msecs_to_ticks(500), iwn_calib_timeout, 5238 sc); 5239 5240 /* Link LED always on while associated. */ 5241 iwn_set_led(sc, IWN_LED_LINK, 0, 1); 5242 return 0; 5243 #undef MS 5244 } 5245 5246 #if 0 /* HT */ 5247 /* 5248 * This function is called by upper layer when an ADDBA request is received 5249 * from another STA and before the ADDBA response is sent. 5250 */ 5251 static int 5252 iwn_ampdu_rx_start(struct ieee80211com *ic, struct ieee80211_node *ni, 5253 uint8_t tid) 5254 { 5255 struct ieee80211_rx_ba *ba = &ni->ni_rx_ba[tid]; 5256 struct iwn_softc *sc = ic->ic_softc; 5257 struct iwn_ops *ops = &sc->ops; 5258 struct iwn_node *wn = (void *)ni; 5259 struct iwn_node_info node; 5260 5261 memset(&node, 0, sizeof node); 5262 node.id = wn->id; 5263 node.control = IWN_NODE_UPDATE; 5264 node.flags = IWN_FLAG_SET_ADDBA; 5265 node.addba_tid = tid; 5266 node.addba_ssn = htole16(ba->ba_winstart); 5267 DPRINTF(sc, IWN_DEBUG_RECV, "ADDBA RA=%d TID=%d SSN=%d\n", 5268 wn->id, tid, ba->ba_winstart); 5269 return ops->add_node(sc, &node, 1); 5270 } 5271 5272 /* 5273 * This function is called by upper layer on teardown of an HT-immediate 5274 * Block Ack agreement (eg. uppon receipt of a DELBA frame). 5275 */ 5276 static void 5277 iwn_ampdu_rx_stop(struct ieee80211com *ic, struct ieee80211_node *ni, 5278 uint8_t tid) 5279 { 5280 struct iwn_softc *sc = ic->ic_softc; 5281 struct iwn_ops *ops = &sc->ops; 5282 struct iwn_node *wn = (void *)ni; 5283 struct iwn_node_info node; 5284 5285 memset(&node, 0, sizeof node); 5286 node.id = wn->id; 5287 node.control = IWN_NODE_UPDATE; 5288 node.flags = IWN_FLAG_SET_DELBA; 5289 node.delba_tid = tid; 5290 DPRINTF(sc, IWN_DEBUG_RECV, "DELBA RA=%d TID=%d\n", wn->id, tid); 5291 (void)ops->add_node(sc, &node, 1); 5292 } 5293 5294 /* 5295 * This function is called by upper layer when an ADDBA response is received 5296 * from another STA. 5297 */ 5298 static int 5299 iwn_ampdu_tx_start(struct ieee80211com *ic, struct ieee80211_node *ni, 5300 uint8_t tid) 5301 { 5302 struct ieee80211_tx_ba *ba = &ni->ni_tx_ba[tid]; 5303 struct iwn_softc *sc = ic->ic_softc; 5304 struct iwn_ops *ops = &sc->ops; 5305 struct iwn_node *wn = (void *)ni; 5306 struct iwn_node_info node; 5307 int error; 5308 5309 /* Enable TX for the specified RA/TID. */ 5310 wn->disable_tid &= ~(1 << tid); 5311 memset(&node, 0, sizeof node); 5312 node.id = wn->id; 5313 node.control = IWN_NODE_UPDATE; 5314 node.flags = IWN_FLAG_SET_DISABLE_TID; 5315 node.disable_tid = htole16(wn->disable_tid); 5316 error = ops->add_node(sc, &node, 1); 5317 if (error != 0) 5318 return error; 5319 5320 if ((error = iwn_nic_lock(sc)) != 0) 5321 return error; 5322 ops->ampdu_tx_start(sc, ni, tid, ba->ba_winstart); 5323 iwn_nic_unlock(sc); 5324 return 0; 5325 } 5326 5327 static void 5328 iwn_ampdu_tx_stop(struct ieee80211com *ic, struct ieee80211_node *ni, 5329 uint8_t tid) 5330 { 5331 struct ieee80211_tx_ba *ba = &ni->ni_tx_ba[tid]; 5332 struct iwn_softc *sc = ic->ic_softc; 5333 struct iwn_ops *ops = &sc->ops; 5334 5335 if (iwn_nic_lock(sc) != 0) 5336 return; 5337 ops->ampdu_tx_stop(sc, tid, ba->ba_winstart); 5338 iwn_nic_unlock(sc); 5339 } 5340 5341 static void 5342 iwn4965_ampdu_tx_start(struct iwn_softc *sc, struct ieee80211_node *ni, 5343 uint8_t tid, uint16_t ssn) 5344 { 5345 struct iwn_node *wn = (void *)ni; 5346 int qid = 7 + tid; 5347 5348 /* Stop TX scheduler while we're changing its configuration. */ 5349 iwn_prph_write(sc, IWN4965_SCHED_QUEUE_STATUS(qid), 5350 IWN4965_TXQ_STATUS_CHGACT); 5351 5352 /* Assign RA/TID translation to the queue. */ 5353 iwn_mem_write_2(sc, sc->sched_base + IWN4965_SCHED_TRANS_TBL(qid), 5354 wn->id << 4 | tid); 5355 5356 /* Enable chain-building mode for the queue. */ 5357 iwn_prph_setbits(sc, IWN4965_SCHED_QCHAIN_SEL, 1 << qid); 5358 5359 /* Set starting sequence number from the ADDBA request. */ 5360 IWN_WRITE(sc, IWN_HBUS_TARG_WRPTR, qid << 8 | (ssn & 0xff)); 5361 iwn_prph_write(sc, IWN4965_SCHED_QUEUE_RDPTR(qid), ssn); 5362 5363 /* Set scheduler window size. */ 5364 iwn_mem_write(sc, sc->sched_base + IWN4965_SCHED_QUEUE_OFFSET(qid), 5365 IWN_SCHED_WINSZ); 5366 /* Set scheduler frame limit. */ 5367 iwn_mem_write(sc, sc->sched_base + IWN4965_SCHED_QUEUE_OFFSET(qid) + 4, 5368 IWN_SCHED_LIMIT << 16); 5369 5370 /* Enable interrupts for the queue. */ 5371 iwn_prph_setbits(sc, IWN4965_SCHED_INTR_MASK, 1 << qid); 5372 5373 /* Mark the queue as active. */ 5374 iwn_prph_write(sc, IWN4965_SCHED_QUEUE_STATUS(qid), 5375 IWN4965_TXQ_STATUS_ACTIVE | IWN4965_TXQ_STATUS_AGGR_ENA | 5376 iwn_tid2fifo[tid] << 1); 5377 } 5378 5379 static void 5380 iwn4965_ampdu_tx_stop(struct iwn_softc *sc, uint8_t tid, uint16_t ssn) 5381 { 5382 int qid = 7 + tid; 5383 5384 /* Stop TX scheduler while we're changing its configuration. */ 5385 iwn_prph_write(sc, IWN4965_SCHED_QUEUE_STATUS(qid), 5386 IWN4965_TXQ_STATUS_CHGACT); 5387 5388 /* Set starting sequence number from the ADDBA request. */ 5389 IWN_WRITE(sc, IWN_HBUS_TARG_WRPTR, qid << 8 | (ssn & 0xff)); 5390 iwn_prph_write(sc, IWN4965_SCHED_QUEUE_RDPTR(qid), ssn); 5391 5392 /* Disable interrupts for the queue. */ 5393 iwn_prph_clrbits(sc, IWN4965_SCHED_INTR_MASK, 1 << qid); 5394 5395 /* Mark the queue as inactive. */ 5396 iwn_prph_write(sc, IWN4965_SCHED_QUEUE_STATUS(qid), 5397 IWN4965_TXQ_STATUS_INACTIVE | iwn_tid2fifo[tid] << 1); 5398 } 5399 5400 static void 5401 iwn5000_ampdu_tx_start(struct iwn_softc *sc, struct ieee80211_node *ni, 5402 uint8_t tid, uint16_t ssn) 5403 { 5404 struct iwn_node *wn = (void *)ni; 5405 int qid = 10 + tid; 5406 5407 /* Stop TX scheduler while we're changing its configuration. */ 5408 iwn_prph_write(sc, IWN5000_SCHED_QUEUE_STATUS(qid), 5409 IWN5000_TXQ_STATUS_CHGACT); 5410 5411 /* Assign RA/TID translation to the queue. */ 5412 iwn_mem_write_2(sc, sc->sched_base + IWN5000_SCHED_TRANS_TBL(qid), 5413 wn->id << 4 | tid); 5414 5415 /* Enable chain-building mode for the queue. */ 5416 iwn_prph_setbits(sc, IWN5000_SCHED_QCHAIN_SEL, 1 << qid); 5417 5418 /* Enable aggregation for the queue. */ 5419 iwn_prph_setbits(sc, IWN5000_SCHED_AGGR_SEL, 1 << qid); 5420 5421 /* Set starting sequence number from the ADDBA request. */ 5422 IWN_WRITE(sc, IWN_HBUS_TARG_WRPTR, qid << 8 | (ssn & 0xff)); 5423 iwn_prph_write(sc, IWN5000_SCHED_QUEUE_RDPTR(qid), ssn); 5424 5425 /* Set scheduler window size and frame limit. */ 5426 iwn_mem_write(sc, sc->sched_base + IWN5000_SCHED_QUEUE_OFFSET(qid) + 4, 5427 IWN_SCHED_LIMIT << 16 | IWN_SCHED_WINSZ); 5428 5429 /* Enable interrupts for the queue. */ 5430 iwn_prph_setbits(sc, IWN5000_SCHED_INTR_MASK, 1 << qid); 5431 5432 /* Mark the queue as active. */ 5433 iwn_prph_write(sc, IWN5000_SCHED_QUEUE_STATUS(qid), 5434 IWN5000_TXQ_STATUS_ACTIVE | iwn_tid2fifo[tid]); 5435 } 5436 5437 static void 5438 iwn5000_ampdu_tx_stop(struct iwn_softc *sc, uint8_t tid, uint16_t ssn) 5439 { 5440 int qid = 10 + tid; 5441 5442 /* Stop TX scheduler while we're changing its configuration. */ 5443 iwn_prph_write(sc, IWN5000_SCHED_QUEUE_STATUS(qid), 5444 IWN5000_TXQ_STATUS_CHGACT); 5445 5446 /* Disable aggregation for the queue. */ 5447 iwn_prph_clrbits(sc, IWN5000_SCHED_AGGR_SEL, 1 << qid); 5448 5449 /* Set starting sequence number from the ADDBA request. */ 5450 IWN_WRITE(sc, IWN_HBUS_TARG_WRPTR, qid << 8 | (ssn & 0xff)); 5451 iwn_prph_write(sc, IWN5000_SCHED_QUEUE_RDPTR(qid), ssn); 5452 5453 /* Disable interrupts for the queue. */ 5454 iwn_prph_clrbits(sc, IWN5000_SCHED_INTR_MASK, 1 << qid); 5455 5456 /* Mark the queue as inactive. */ 5457 iwn_prph_write(sc, IWN5000_SCHED_QUEUE_STATUS(qid), 5458 IWN5000_TXQ_STATUS_INACTIVE | iwn_tid2fifo[tid]); 5459 } 5460 #endif 5461 5462 /* 5463 * Query calibration tables from the initialization firmware. We do this 5464 * only once at first boot. Called from a process context. 5465 */ 5466 static int 5467 iwn5000_query_calibration(struct iwn_softc *sc) 5468 { 5469 struct iwn5000_calib_config cmd; 5470 int error; 5471 5472 memset(&cmd, 0, sizeof cmd); 5473 cmd.ucode.once.enable = 0xffffffff; 5474 cmd.ucode.once.start = 0xffffffff; 5475 cmd.ucode.once.send = 0xffffffff; 5476 cmd.ucode.flags = 0xffffffff; 5477 DPRINTF(sc, IWN_DEBUG_CALIBRATE, "%s: sending calibration query\n", 5478 __func__); 5479 error = iwn_cmd(sc, IWN5000_CMD_CALIB_CONFIG, &cmd, sizeof cmd, 0); 5480 if (error != 0) 5481 return error; 5482 5483 /* Wait at most two seconds for calibration to complete. */ 5484 if (!(sc->sc_flags & IWN_FLAG_CALIB_DONE)) 5485 error = msleep(sc, &sc->sc_mtx, PCATCH, "iwncal", 2 * hz); 5486 return error; 5487 } 5488 5489 /* 5490 * Send calibration results to the runtime firmware. These results were 5491 * obtained on first boot from the initialization firmware. 5492 */ 5493 static int 5494 iwn5000_send_calibration(struct iwn_softc *sc) 5495 { 5496 int idx, error; 5497 5498 for (idx = 0; idx < 5; idx++) { 5499 if (sc->calibcmd[idx].buf == NULL) 5500 continue; /* No results available. */ 5501 DPRINTF(sc, IWN_DEBUG_CALIBRATE, 5502 "send calibration result idx=%d len=%d\n", idx, 5503 sc->calibcmd[idx].len); 5504 error = iwn_cmd(sc, IWN_CMD_PHY_CALIB, sc->calibcmd[idx].buf, 5505 sc->calibcmd[idx].len, 0); 5506 if (error != 0) { 5507 device_printf(sc->sc_dev, 5508 "%s: could not send calibration result, error %d\n", 5509 __func__, error); 5510 return error; 5511 } 5512 } 5513 return 0; 5514 } 5515 5516 static int 5517 iwn5000_send_wimax_coex(struct iwn_softc *sc) 5518 { 5519 struct iwn5000_wimax_coex wimax; 5520 5521 #ifdef notyet 5522 if (sc->hw_type == IWN_HW_REV_TYPE_6050) { 5523 /* Enable WiMAX coexistence for combo adapters. */ 5524 wimax.flags = 5525 IWN_WIMAX_COEX_ASSOC_WA_UNMASK | 5526 IWN_WIMAX_COEX_UNASSOC_WA_UNMASK | 5527 IWN_WIMAX_COEX_STA_TABLE_VALID | 5528 IWN_WIMAX_COEX_ENABLE; 5529 memcpy(wimax.events, iwn6050_wimax_events, 5530 sizeof iwn6050_wimax_events); 5531 } else 5532 #endif 5533 { 5534 /* Disable WiMAX coexistence. */ 5535 wimax.flags = 0; 5536 memset(wimax.events, 0, sizeof wimax.events); 5537 } 5538 DPRINTF(sc, IWN_DEBUG_RESET, "%s: Configuring WiMAX coexistence\n", 5539 __func__); 5540 return iwn_cmd(sc, IWN5000_CMD_WIMAX_COEX, &wimax, sizeof wimax, 0); 5541 } 5542 5543 static int 5544 iwn5000_crystal_calib(struct iwn_softc *sc) 5545 { 5546 struct iwn5000_phy_calib_crystal cmd; 5547 5548 memset(&cmd, 0, sizeof cmd); 5549 cmd.code = IWN5000_PHY_CALIB_CRYSTAL; 5550 cmd.ngroups = 1; 5551 cmd.isvalid = 1; 5552 cmd.cap_pin[0] = le32toh(sc->eeprom_crystal) & 0xff; 5553 cmd.cap_pin[1] = (le32toh(sc->eeprom_crystal) >> 16) & 0xff; 5554 DPRINTF(sc, IWN_DEBUG_CALIBRATE, "sending crystal calibration %d, %d\n", 5555 cmd.cap_pin[0], cmd.cap_pin[1]); 5556 return iwn_cmd(sc, IWN_CMD_PHY_CALIB, &cmd, sizeof cmd, 0); 5557 } 5558 5559 static int 5560 iwn5000_temp_offset_calib(struct iwn_softc *sc) 5561 { 5562 struct iwn5000_phy_calib_temp_offset cmd; 5563 5564 memset(&cmd, 0, sizeof cmd); 5565 cmd.code = IWN5000_PHY_CALIB_TEMP_OFFSET; 5566 cmd.ngroups = 1; 5567 cmd.isvalid = 1; 5568 if (sc->eeprom_temp != 0) 5569 cmd.offset = htole16(sc->eeprom_temp); 5570 else 5571 cmd.offset = htole16(IWN_DEFAULT_TEMP_OFFSET); 5572 DPRINTF(sc, IWN_DEBUG_CALIBRATE, "setting radio sensor offset to %d\n", 5573 le16toh(cmd.offset)); 5574 return iwn_cmd(sc, IWN_CMD_PHY_CALIB, &cmd, sizeof cmd, 0); 5575 } 5576 5577 /* 5578 * This function is called after the runtime firmware notifies us of its 5579 * readiness (called in a process context). 5580 */ 5581 static int 5582 iwn4965_post_alive(struct iwn_softc *sc) 5583 { 5584 int error, qid; 5585 5586 if ((error = iwn_nic_lock(sc)) != 0) 5587 return error; 5588 5589 /* Clear TX scheduler state in SRAM. */ 5590 sc->sched_base = iwn_prph_read(sc, IWN_SCHED_SRAM_ADDR); 5591 iwn_mem_set_region_4(sc, sc->sched_base + IWN4965_SCHED_CTX_OFF, 0, 5592 IWN4965_SCHED_CTX_LEN / sizeof (uint32_t)); 5593 5594 /* Set physical address of TX scheduler rings (1KB aligned). */ 5595 iwn_prph_write(sc, IWN4965_SCHED_DRAM_ADDR, sc->sched_dma.paddr >> 10); 5596 5597 IWN_SETBITS(sc, IWN_FH_TX_CHICKEN, IWN_FH_TX_CHICKEN_SCHED_RETRY); 5598 5599 /* Disable chain mode for all our 16 queues. */ 5600 iwn_prph_write(sc, IWN4965_SCHED_QCHAIN_SEL, 0); 5601 5602 for (qid = 0; qid < IWN4965_NTXQUEUES; qid++) { 5603 iwn_prph_write(sc, IWN4965_SCHED_QUEUE_RDPTR(qid), 0); 5604 IWN_WRITE(sc, IWN_HBUS_TARG_WRPTR, qid << 8 | 0); 5605 5606 /* Set scheduler window size. */ 5607 iwn_mem_write(sc, sc->sched_base + 5608 IWN4965_SCHED_QUEUE_OFFSET(qid), IWN_SCHED_WINSZ); 5609 /* Set scheduler frame limit. */ 5610 iwn_mem_write(sc, sc->sched_base + 5611 IWN4965_SCHED_QUEUE_OFFSET(qid) + 4, 5612 IWN_SCHED_LIMIT << 16); 5613 } 5614 5615 /* Enable interrupts for all our 16 queues. */ 5616 iwn_prph_write(sc, IWN4965_SCHED_INTR_MASK, 0xffff); 5617 /* Identify TX FIFO rings (0-7). */ 5618 iwn_prph_write(sc, IWN4965_SCHED_TXFACT, 0xff); 5619 5620 /* Mark TX rings (4 EDCA + cmd + 2 HCCA) as active. */ 5621 for (qid = 0; qid < 7; qid++) { 5622 static uint8_t qid2fifo[] = { 3, 2, 1, 0, 4, 5, 6 }; 5623 iwn_prph_write(sc, IWN4965_SCHED_QUEUE_STATUS(qid), 5624 IWN4965_TXQ_STATUS_ACTIVE | qid2fifo[qid] << 1); 5625 } 5626 iwn_nic_unlock(sc); 5627 return 0; 5628 } 5629 5630 /* 5631 * This function is called after the initialization or runtime firmware 5632 * notifies us of its readiness (called in a process context). 5633 */ 5634 static int 5635 iwn5000_post_alive(struct iwn_softc *sc) 5636 { 5637 int error, qid; 5638 5639 /* Switch to using ICT interrupt mode. */ 5640 iwn5000_ict_reset(sc); 5641 5642 if ((error = iwn_nic_lock(sc)) != 0) 5643 return error; 5644 5645 /* Clear TX scheduler state in SRAM. */ 5646 sc->sched_base = iwn_prph_read(sc, IWN_SCHED_SRAM_ADDR); 5647 iwn_mem_set_region_4(sc, sc->sched_base + IWN5000_SCHED_CTX_OFF, 0, 5648 IWN5000_SCHED_CTX_LEN / sizeof (uint32_t)); 5649 5650 /* Set physical address of TX scheduler rings (1KB aligned). */ 5651 iwn_prph_write(sc, IWN5000_SCHED_DRAM_ADDR, sc->sched_dma.paddr >> 10); 5652 5653 IWN_SETBITS(sc, IWN_FH_TX_CHICKEN, IWN_FH_TX_CHICKEN_SCHED_RETRY); 5654 5655 /* Enable chain mode for all queues, except command queue. */ 5656 iwn_prph_write(sc, IWN5000_SCHED_QCHAIN_SEL, 0xfffef); 5657 iwn_prph_write(sc, IWN5000_SCHED_AGGR_SEL, 0); 5658 5659 for (qid = 0; qid < IWN5000_NTXQUEUES; qid++) { 5660 iwn_prph_write(sc, IWN5000_SCHED_QUEUE_RDPTR(qid), 0); 5661 IWN_WRITE(sc, IWN_HBUS_TARG_WRPTR, qid << 8 | 0); 5662 5663 iwn_mem_write(sc, sc->sched_base + 5664 IWN5000_SCHED_QUEUE_OFFSET(qid), 0); 5665 /* Set scheduler window size and frame limit. */ 5666 iwn_mem_write(sc, sc->sched_base + 5667 IWN5000_SCHED_QUEUE_OFFSET(qid) + 4, 5668 IWN_SCHED_LIMIT << 16 | IWN_SCHED_WINSZ); 5669 } 5670 5671 /* Enable interrupts for all our 20 queues. */ 5672 iwn_prph_write(sc, IWN5000_SCHED_INTR_MASK, 0xfffff); 5673 /* Identify TX FIFO rings (0-7). */ 5674 iwn_prph_write(sc, IWN5000_SCHED_TXFACT, 0xff); 5675 5676 /* Mark TX rings (4 EDCA + cmd + 2 HCCA) as active. */ 5677 for (qid = 0; qid < 7; qid++) { 5678 static uint8_t qid2fifo[] = { 3, 2, 1, 0, 7, 5, 6 }; 5679 iwn_prph_write(sc, IWN5000_SCHED_QUEUE_STATUS(qid), 5680 IWN5000_TXQ_STATUS_ACTIVE | qid2fifo[qid]); 5681 } 5682 iwn_nic_unlock(sc); 5683 5684 /* Configure WiMAX coexistence for combo adapters. */ 5685 error = iwn5000_send_wimax_coex(sc); 5686 if (error != 0) { 5687 device_printf(sc->sc_dev, 5688 "%s: could not configure WiMAX coexistence, error %d\n", 5689 __func__, error); 5690 return error; 5691 } 5692 if (sc->hw_type != IWN_HW_REV_TYPE_5150) { 5693 /* Perform crystal calibration. */ 5694 error = iwn5000_crystal_calib(sc); 5695 if (error != 0) { 5696 device_printf(sc->sc_dev, 5697 "%s: crystal calibration failed, error %d\n", 5698 __func__, error); 5699 return error; 5700 } 5701 } 5702 if (!(sc->sc_flags & IWN_FLAG_CALIB_DONE)) { 5703 /* Query calibration from the initialization firmware. */ 5704 if ((error = iwn5000_query_calibration(sc)) != 0) { 5705 device_printf(sc->sc_dev, 5706 "%s: could not query calibration, error %d\n", 5707 __func__, error); 5708 return error; 5709 } 5710 /* 5711 * We have the calibration results now, reboot with the 5712 * runtime firmware (call ourselves recursively!) 5713 */ 5714 iwn_hw_stop(sc); 5715 error = iwn_hw_init(sc); 5716 } else { 5717 /* Send calibration results to runtime firmware. */ 5718 error = iwn5000_send_calibration(sc); 5719 } 5720 return error; 5721 } 5722 5723 /* 5724 * The firmware boot code is small and is intended to be copied directly into 5725 * the NIC internal memory (no DMA transfer). 5726 */ 5727 static int 5728 iwn4965_load_bootcode(struct iwn_softc *sc, const uint8_t *ucode, int size) 5729 { 5730 int error, ntries; 5731 5732 size /= sizeof (uint32_t); 5733 5734 if ((error = iwn_nic_lock(sc)) != 0) 5735 return error; 5736 5737 /* Copy microcode image into NIC memory. */ 5738 iwn_prph_write_region_4(sc, IWN_BSM_SRAM_BASE, 5739 (const uint32_t *)ucode, size); 5740 5741 iwn_prph_write(sc, IWN_BSM_WR_MEM_SRC, 0); 5742 iwn_prph_write(sc, IWN_BSM_WR_MEM_DST, IWN_FW_TEXT_BASE); 5743 iwn_prph_write(sc, IWN_BSM_WR_DWCOUNT, size); 5744 5745 /* Start boot load now. */ 5746 iwn_prph_write(sc, IWN_BSM_WR_CTRL, IWN_BSM_WR_CTRL_START); 5747 5748 /* Wait for transfer to complete. */ 5749 for (ntries = 0; ntries < 1000; ntries++) { 5750 if (!(iwn_prph_read(sc, IWN_BSM_WR_CTRL) & 5751 IWN_BSM_WR_CTRL_START)) 5752 break; 5753 DELAY(10); 5754 } 5755 if (ntries == 1000) { 5756 device_printf(sc->sc_dev, "%s: could not load boot firmware\n", 5757 __func__); 5758 iwn_nic_unlock(sc); 5759 return ETIMEDOUT; 5760 } 5761 5762 /* Enable boot after power up. */ 5763 iwn_prph_write(sc, IWN_BSM_WR_CTRL, IWN_BSM_WR_CTRL_START_EN); 5764 5765 iwn_nic_unlock(sc); 5766 return 0; 5767 } 5768 5769 static int 5770 iwn4965_load_firmware(struct iwn_softc *sc) 5771 { 5772 struct iwn_fw_info *fw = &sc->fw; 5773 struct iwn_dma_info *dma = &sc->fw_dma; 5774 int error; 5775 5776 /* Copy initialization sections into pre-allocated DMA-safe memory. */ 5777 memcpy(dma->vaddr, fw->init.data, fw->init.datasz); 5778 bus_dmamap_sync(dma->tag, dma->map, BUS_DMASYNC_PREWRITE); 5779 memcpy(dma->vaddr + IWN4965_FW_DATA_MAXSZ, 5780 fw->init.text, fw->init.textsz); 5781 bus_dmamap_sync(dma->tag, dma->map, BUS_DMASYNC_PREWRITE); 5782 5783 /* Tell adapter where to find initialization sections. */ 5784 if ((error = iwn_nic_lock(sc)) != 0) 5785 return error; 5786 iwn_prph_write(sc, IWN_BSM_DRAM_DATA_ADDR, dma->paddr >> 4); 5787 iwn_prph_write(sc, IWN_BSM_DRAM_DATA_SIZE, fw->init.datasz); 5788 iwn_prph_write(sc, IWN_BSM_DRAM_TEXT_ADDR, 5789 (dma->paddr + IWN4965_FW_DATA_MAXSZ) >> 4); 5790 iwn_prph_write(sc, IWN_BSM_DRAM_TEXT_SIZE, fw->init.textsz); 5791 iwn_nic_unlock(sc); 5792 5793 /* Load firmware boot code. */ 5794 error = iwn4965_load_bootcode(sc, fw->boot.text, fw->boot.textsz); 5795 if (error != 0) { 5796 device_printf(sc->sc_dev, "%s: could not load boot firmware\n", 5797 __func__); 5798 return error; 5799 } 5800 /* Now press "execute". */ 5801 IWN_WRITE(sc, IWN_RESET, 0); 5802 5803 /* Wait at most one second for first alive notification. */ 5804 if ((error = msleep(sc, &sc->sc_mtx, PCATCH, "iwninit", hz)) != 0) { 5805 device_printf(sc->sc_dev, 5806 "%s: timeout waiting for adapter to initialize, error %d\n", 5807 __func__, error); 5808 return error; 5809 } 5810 5811 /* Retrieve current temperature for initial TX power calibration. */ 5812 sc->rawtemp = sc->ucode_info.temp[3].chan20MHz; 5813 sc->temp = iwn4965_get_temperature(sc); 5814 5815 /* Copy runtime sections into pre-allocated DMA-safe memory. */ 5816 memcpy(dma->vaddr, fw->main.data, fw->main.datasz); 5817 bus_dmamap_sync(dma->tag, dma->map, BUS_DMASYNC_PREWRITE); 5818 memcpy(dma->vaddr + IWN4965_FW_DATA_MAXSZ, 5819 fw->main.text, fw->main.textsz); 5820 bus_dmamap_sync(dma->tag, dma->map, BUS_DMASYNC_PREWRITE); 5821 5822 /* Tell adapter where to find runtime sections. */ 5823 if ((error = iwn_nic_lock(sc)) != 0) 5824 return error; 5825 iwn_prph_write(sc, IWN_BSM_DRAM_DATA_ADDR, dma->paddr >> 4); 5826 iwn_prph_write(sc, IWN_BSM_DRAM_DATA_SIZE, fw->main.datasz); 5827 iwn_prph_write(sc, IWN_BSM_DRAM_TEXT_ADDR, 5828 (dma->paddr + IWN4965_FW_DATA_MAXSZ) >> 4); 5829 iwn_prph_write(sc, IWN_BSM_DRAM_TEXT_SIZE, 5830 IWN_FW_UPDATED | fw->main.textsz); 5831 iwn_nic_unlock(sc); 5832 5833 return 0; 5834 } 5835 5836 static int 5837 iwn5000_load_firmware_section(struct iwn_softc *sc, uint32_t dst, 5838 const uint8_t *section, int size) 5839 { 5840 struct iwn_dma_info *dma = &sc->fw_dma; 5841 int error; 5842 5843 /* Copy firmware section into pre-allocated DMA-safe memory. */ 5844 memcpy(dma->vaddr, section, size); 5845 bus_dmamap_sync(dma->tag, dma->map, BUS_DMASYNC_PREWRITE); 5846 5847 if ((error = iwn_nic_lock(sc)) != 0) 5848 return error; 5849 5850 IWN_WRITE(sc, IWN_FH_TX_CONFIG(IWN_SRVC_DMACHNL), 5851 IWN_FH_TX_CONFIG_DMA_PAUSE); 5852 5853 IWN_WRITE(sc, IWN_FH_SRAM_ADDR(IWN_SRVC_DMACHNL), dst); 5854 IWN_WRITE(sc, IWN_FH_TFBD_CTRL0(IWN_SRVC_DMACHNL), 5855 IWN_LOADDR(dma->paddr)); 5856 IWN_WRITE(sc, IWN_FH_TFBD_CTRL1(IWN_SRVC_DMACHNL), 5857 IWN_HIADDR(dma->paddr) << 28 | size); 5858 IWN_WRITE(sc, IWN_FH_TXBUF_STATUS(IWN_SRVC_DMACHNL), 5859 IWN_FH_TXBUF_STATUS_TBNUM(1) | 5860 IWN_FH_TXBUF_STATUS_TBIDX(1) | 5861 IWN_FH_TXBUF_STATUS_TFBD_VALID); 5862 5863 /* Kick Flow Handler to start DMA transfer. */ 5864 IWN_WRITE(sc, IWN_FH_TX_CONFIG(IWN_SRVC_DMACHNL), 5865 IWN_FH_TX_CONFIG_DMA_ENA | IWN_FH_TX_CONFIG_CIRQ_HOST_ENDTFD); 5866 5867 iwn_nic_unlock(sc); 5868 5869 /* Wait at most five seconds for FH DMA transfer to complete. */ 5870 return msleep(sc, &sc->sc_mtx, PCATCH, "iwninit", 5 * hz); 5871 } 5872 5873 static int 5874 iwn5000_load_firmware(struct iwn_softc *sc) 5875 { 5876 struct iwn_fw_part *fw; 5877 int error; 5878 5879 /* Load the initialization firmware on first boot only. */ 5880 fw = (sc->sc_flags & IWN_FLAG_CALIB_DONE) ? 5881 &sc->fw.main : &sc->fw.init; 5882 5883 error = iwn5000_load_firmware_section(sc, IWN_FW_TEXT_BASE, 5884 fw->text, fw->textsz); 5885 if (error != 0) { 5886 device_printf(sc->sc_dev, 5887 "%s: could not load firmware %s section, error %d\n", 5888 __func__, ".text", error); 5889 return error; 5890 } 5891 error = iwn5000_load_firmware_section(sc, IWN_FW_DATA_BASE, 5892 fw->data, fw->datasz); 5893 if (error != 0) { 5894 device_printf(sc->sc_dev, 5895 "%s: could not load firmware %s section, error %d\n", 5896 __func__, ".data", error); 5897 return error; 5898 } 5899 5900 /* Now press "execute". */ 5901 IWN_WRITE(sc, IWN_RESET, 0); 5902 return 0; 5903 } 5904 5905 /* 5906 * Extract text and data sections from a legacy firmware image. 5907 */ 5908 static int 5909 iwn_read_firmware_leg(struct iwn_softc *sc, struct iwn_fw_info *fw) 5910 { 5911 const uint32_t *ptr; 5912 size_t hdrlen = 24; 5913 uint32_t rev; 5914 5915 ptr = (const uint32_t *)fw->data; 5916 rev = le32toh(*ptr++); 5917 5918 /* Check firmware API version. */ 5919 if (IWN_FW_API(rev) <= 1) { 5920 device_printf(sc->sc_dev, 5921 "%s: bad firmware, need API version >=2\n", __func__); 5922 return EINVAL; 5923 } 5924 if (IWN_FW_API(rev) >= 3) { 5925 /* Skip build number (version 2 header). */ 5926 hdrlen += 4; 5927 ptr++; 5928 } 5929 if (fw->size < hdrlen) { 5930 device_printf(sc->sc_dev, "%s: firmware too short: %zu bytes\n", 5931 __func__, fw->size); 5932 return EINVAL; 5933 } 5934 fw->main.textsz = le32toh(*ptr++); 5935 fw->main.datasz = le32toh(*ptr++); 5936 fw->init.textsz = le32toh(*ptr++); 5937 fw->init.datasz = le32toh(*ptr++); 5938 fw->boot.textsz = le32toh(*ptr++); 5939 5940 /* Check that all firmware sections fit. */ 5941 if (fw->size < hdrlen + fw->main.textsz + fw->main.datasz + 5942 fw->init.textsz + fw->init.datasz + fw->boot.textsz) { 5943 device_printf(sc->sc_dev, "%s: firmware too short: %zu bytes\n", 5944 __func__, fw->size); 5945 return EINVAL; 5946 } 5947 5948 /* Get pointers to firmware sections. */ 5949 fw->main.text = (const uint8_t *)ptr; 5950 fw->main.data = fw->main.text + fw->main.textsz; 5951 fw->init.text = fw->main.data + fw->main.datasz; 5952 fw->init.data = fw->init.text + fw->init.textsz; 5953 fw->boot.text = fw->init.data + fw->init.datasz; 5954 return 0; 5955 } 5956 5957 /* 5958 * Extract text and data sections from a TLV firmware image. 5959 */ 5960 static int 5961 iwn_read_firmware_tlv(struct iwn_softc *sc, struct iwn_fw_info *fw, 5962 uint16_t alt) 5963 { 5964 const struct iwn_fw_tlv_hdr *hdr; 5965 const struct iwn_fw_tlv *tlv; 5966 const uint8_t *ptr, *end; 5967 uint64_t altmask; 5968 uint32_t len, tmp; 5969 5970 if (fw->size < sizeof (*hdr)) { 5971 device_printf(sc->sc_dev, "%s: firmware too short: %zu bytes\n", 5972 __func__, fw->size); 5973 return EINVAL; 5974 } 5975 hdr = (const struct iwn_fw_tlv_hdr *)fw->data; 5976 if (hdr->signature != htole32(IWN_FW_SIGNATURE)) { 5977 device_printf(sc->sc_dev, "%s: bad firmware signature 0x%08x\n", 5978 __func__, le32toh(hdr->signature)); 5979 return EINVAL; 5980 } 5981 DPRINTF(sc, IWN_DEBUG_RESET, "FW: \"%.64s\", build 0x%x\n", hdr->descr, 5982 le32toh(hdr->build)); 5983 5984 /* 5985 * Select the closest supported alternative that is less than 5986 * or equal to the specified one. 5987 */ 5988 altmask = le64toh(hdr->altmask); 5989 while (alt > 0 && !(altmask & (1ULL << alt))) 5990 alt--; /* Downgrade. */ 5991 DPRINTF(sc, IWN_DEBUG_RESET, "using alternative %d\n", alt); 5992 5993 ptr = (const uint8_t *)(hdr + 1); 5994 end = (const uint8_t *)(fw->data + fw->size); 5995 5996 /* Parse type-length-value fields. */ 5997 while (ptr + sizeof (*tlv) <= end) { 5998 tlv = (const struct iwn_fw_tlv *)ptr; 5999 len = le32toh(tlv->len); 6000 6001 ptr += sizeof (*tlv); 6002 if (ptr + len > end) { 6003 device_printf(sc->sc_dev, 6004 "%s: firmware too short: %zu bytes\n", __func__, 6005 fw->size); 6006 return EINVAL; 6007 } 6008 /* Skip other alternatives. */ 6009 if (tlv->alt != 0 && tlv->alt != htole16(alt)) 6010 goto next; 6011 6012 switch (le16toh(tlv->type)) { 6013 case IWN_FW_TLV_MAIN_TEXT: 6014 fw->main.text = ptr; 6015 fw->main.textsz = len; 6016 break; 6017 case IWN_FW_TLV_MAIN_DATA: 6018 fw->main.data = ptr; 6019 fw->main.datasz = len; 6020 break; 6021 case IWN_FW_TLV_INIT_TEXT: 6022 fw->init.text = ptr; 6023 fw->init.textsz = len; 6024 break; 6025 case IWN_FW_TLV_INIT_DATA: 6026 fw->init.data = ptr; 6027 fw->init.datasz = len; 6028 break; 6029 case IWN_FW_TLV_BOOT_TEXT: 6030 fw->boot.text = ptr; 6031 fw->boot.textsz = len; 6032 break; 6033 case IWN_FW_TLV_ENH_SENS: 6034 if (!len) 6035 sc->sc_flags |= IWN_FLAG_ENH_SENS; 6036 break; 6037 case IWN_FW_TLV_PHY_CALIB: 6038 tmp = htole32(*ptr); 6039 if (tmp < 253) { 6040 sc->reset_noise_gain = tmp; 6041 sc->noise_gain = tmp + 1; 6042 } 6043 break; 6044 default: 6045 DPRINTF(sc, IWN_DEBUG_RESET, 6046 "TLV type %d not handled\n", le16toh(tlv->type)); 6047 break; 6048 } 6049 next: /* TLV fields are 32-bit aligned. */ 6050 ptr += (len + 3) & ~3; 6051 } 6052 return 0; 6053 } 6054 6055 static int 6056 iwn_read_firmware(struct iwn_softc *sc) 6057 { 6058 struct iwn_fw_info *fw = &sc->fw; 6059 int error; 6060 6061 IWN_UNLOCK(sc); 6062 6063 memset(fw, 0, sizeof (*fw)); 6064 6065 /* Read firmware image from filesystem. */ 6066 sc->fw_fp = firmware_get(sc->fwname); 6067 if (sc->fw_fp == NULL) { 6068 device_printf(sc->sc_dev, "%s: could not read firmware %s\n", 6069 __func__, sc->fwname); 6070 IWN_LOCK(sc); 6071 return EINVAL; 6072 } 6073 IWN_LOCK(sc); 6074 6075 fw->size = sc->fw_fp->datasize; 6076 fw->data = (const uint8_t *)sc->fw_fp->data; 6077 if (fw->size < sizeof (uint32_t)) { 6078 device_printf(sc->sc_dev, "%s: firmware too short: %zu bytes\n", 6079 __func__, fw->size); 6080 firmware_put(sc->fw_fp, FIRMWARE_UNLOAD); 6081 sc->fw_fp = NULL; 6082 return EINVAL; 6083 } 6084 6085 /* Retrieve text and data sections. */ 6086 if (*(const uint32_t *)fw->data != 0) /* Legacy image. */ 6087 error = iwn_read_firmware_leg(sc, fw); 6088 else 6089 error = iwn_read_firmware_tlv(sc, fw, 1); 6090 if (error != 0) { 6091 device_printf(sc->sc_dev, 6092 "%s: could not read firmware sections, error %d\n", 6093 __func__, error); 6094 firmware_put(sc->fw_fp, FIRMWARE_UNLOAD); 6095 sc->fw_fp = NULL; 6096 return error; 6097 } 6098 6099 /* Make sure text and data sections fit in hardware memory. */ 6100 if (fw->main.textsz > sc->fw_text_maxsz || 6101 fw->main.datasz > sc->fw_data_maxsz || 6102 fw->init.textsz > sc->fw_text_maxsz || 6103 fw->init.datasz > sc->fw_data_maxsz || 6104 fw->boot.textsz > IWN_FW_BOOT_TEXT_MAXSZ || 6105 (fw->boot.textsz & 3) != 0) { 6106 device_printf(sc->sc_dev, "%s: firmware sections too large\n", 6107 __func__); 6108 firmware_put(sc->fw_fp, FIRMWARE_UNLOAD); 6109 sc->fw_fp = NULL; 6110 return EINVAL; 6111 } 6112 6113 /* We can proceed with loading the firmware. */ 6114 return 0; 6115 } 6116 6117 static int 6118 iwn_clock_wait(struct iwn_softc *sc) 6119 { 6120 int ntries; 6121 6122 /* Set "initialization complete" bit. */ 6123 IWN_SETBITS(sc, IWN_GP_CNTRL, IWN_GP_CNTRL_INIT_DONE); 6124 6125 /* Wait for clock stabilization. */ 6126 for (ntries = 0; ntries < 2500; ntries++) { 6127 if (IWN_READ(sc, IWN_GP_CNTRL) & IWN_GP_CNTRL_MAC_CLOCK_READY) 6128 return 0; 6129 DELAY(10); 6130 } 6131 device_printf(sc->sc_dev, 6132 "%s: timeout waiting for clock stabilization\n", __func__); 6133 return ETIMEDOUT; 6134 } 6135 6136 static int 6137 iwn_apm_init(struct iwn_softc *sc) 6138 { 6139 uint32_t reg; 6140 int error; 6141 6142 /* Disable L0s exit timer (NMI bug workaround). */ 6143 IWN_SETBITS(sc, IWN_GIO_CHICKEN, IWN_GIO_CHICKEN_DIS_L0S_TIMER); 6144 /* Don't wait for ICH L0s (ICH bug workaround). */ 6145 IWN_SETBITS(sc, IWN_GIO_CHICKEN, IWN_GIO_CHICKEN_L1A_NO_L0S_RX); 6146 6147 /* Set FH wait threshold to max (HW bug under stress workaround). */ 6148 IWN_SETBITS(sc, IWN_DBG_HPET_MEM, 0xffff0000); 6149 6150 /* Enable HAP INTA to move adapter from L1a to L0s. */ 6151 IWN_SETBITS(sc, IWN_HW_IF_CONFIG, IWN_HW_IF_CONFIG_HAP_WAKE_L1A); 6152 6153 /* Retrieve PCIe Active State Power Management (ASPM). */ 6154 reg = pci_read_config(sc->sc_dev, sc->sc_cap_off + 0x10, 1); 6155 /* Workaround for HW instability in PCIe L0->L0s->L1 transition. */ 6156 if (reg & 0x02) /* L1 Entry enabled. */ 6157 IWN_SETBITS(sc, IWN_GIO, IWN_GIO_L0S_ENA); 6158 else 6159 IWN_CLRBITS(sc, IWN_GIO, IWN_GIO_L0S_ENA); 6160 6161 if (sc->hw_type != IWN_HW_REV_TYPE_4965 && 6162 sc->hw_type <= IWN_HW_REV_TYPE_1000) 6163 IWN_SETBITS(sc, IWN_ANA_PLL, IWN_ANA_PLL_INIT); 6164 6165 /* Wait for clock stabilization before accessing prph. */ 6166 if ((error = iwn_clock_wait(sc)) != 0) 6167 return error; 6168 6169 if ((error = iwn_nic_lock(sc)) != 0) 6170 return error; 6171 if (sc->hw_type == IWN_HW_REV_TYPE_4965) { 6172 /* Enable DMA and BSM (Bootstrap State Machine). */ 6173 iwn_prph_write(sc, IWN_APMG_CLK_EN, 6174 IWN_APMG_CLK_CTRL_DMA_CLK_RQT | 6175 IWN_APMG_CLK_CTRL_BSM_CLK_RQT); 6176 } else { 6177 /* Enable DMA. */ 6178 iwn_prph_write(sc, IWN_APMG_CLK_EN, 6179 IWN_APMG_CLK_CTRL_DMA_CLK_RQT); 6180 } 6181 DELAY(20); 6182 /* Disable L1-Active. */ 6183 iwn_prph_setbits(sc, IWN_APMG_PCI_STT, IWN_APMG_PCI_STT_L1A_DIS); 6184 iwn_nic_unlock(sc); 6185 6186 return 0; 6187 } 6188 6189 static void 6190 iwn_apm_stop_master(struct iwn_softc *sc) 6191 { 6192 int ntries; 6193 6194 /* Stop busmaster DMA activity. */ 6195 IWN_SETBITS(sc, IWN_RESET, IWN_RESET_STOP_MASTER); 6196 for (ntries = 0; ntries < 100; ntries++) { 6197 if (IWN_READ(sc, IWN_RESET) & IWN_RESET_MASTER_DISABLED) 6198 return; 6199 DELAY(10); 6200 } 6201 device_printf(sc->sc_dev, "%s: timeout waiting for master\n", __func__); 6202 } 6203 6204 static void 6205 iwn_apm_stop(struct iwn_softc *sc) 6206 { 6207 iwn_apm_stop_master(sc); 6208 6209 /* Reset the entire device. */ 6210 IWN_SETBITS(sc, IWN_RESET, IWN_RESET_SW); 6211 DELAY(10); 6212 /* Clear "initialization complete" bit. */ 6213 IWN_CLRBITS(sc, IWN_GP_CNTRL, IWN_GP_CNTRL_INIT_DONE); 6214 } 6215 6216 static int 6217 iwn4965_nic_config(struct iwn_softc *sc) 6218 { 6219 if (IWN_RFCFG_TYPE(sc->rfcfg) == 1) { 6220 /* 6221 * I don't believe this to be correct but this is what the 6222 * vendor driver is doing. Probably the bits should not be 6223 * shifted in IWN_RFCFG_*. 6224 */ 6225 IWN_SETBITS(sc, IWN_HW_IF_CONFIG, 6226 IWN_RFCFG_TYPE(sc->rfcfg) | 6227 IWN_RFCFG_STEP(sc->rfcfg) | 6228 IWN_RFCFG_DASH(sc->rfcfg)); 6229 } 6230 IWN_SETBITS(sc, IWN_HW_IF_CONFIG, 6231 IWN_HW_IF_CONFIG_RADIO_SI | IWN_HW_IF_CONFIG_MAC_SI); 6232 return 0; 6233 } 6234 6235 static int 6236 iwn5000_nic_config(struct iwn_softc *sc) 6237 { 6238 uint32_t tmp; 6239 int error; 6240 6241 if (IWN_RFCFG_TYPE(sc->rfcfg) < 3) { 6242 IWN_SETBITS(sc, IWN_HW_IF_CONFIG, 6243 IWN_RFCFG_TYPE(sc->rfcfg) | 6244 IWN_RFCFG_STEP(sc->rfcfg) | 6245 IWN_RFCFG_DASH(sc->rfcfg)); 6246 } 6247 IWN_SETBITS(sc, IWN_HW_IF_CONFIG, 6248 IWN_HW_IF_CONFIG_RADIO_SI | IWN_HW_IF_CONFIG_MAC_SI); 6249 6250 if ((error = iwn_nic_lock(sc)) != 0) 6251 return error; 6252 iwn_prph_setbits(sc, IWN_APMG_PS, IWN_APMG_PS_EARLY_PWROFF_DIS); 6253 6254 if (sc->hw_type == IWN_HW_REV_TYPE_1000) { 6255 /* 6256 * Select first Switching Voltage Regulator (1.32V) to 6257 * solve a stability issue related to noisy DC2DC line 6258 * in the silicon of 1000 Series. 6259 */ 6260 tmp = iwn_prph_read(sc, IWN_APMG_DIGITAL_SVR); 6261 tmp &= ~IWN_APMG_DIGITAL_SVR_VOLTAGE_MASK; 6262 tmp |= IWN_APMG_DIGITAL_SVR_VOLTAGE_1_32; 6263 iwn_prph_write(sc, IWN_APMG_DIGITAL_SVR, tmp); 6264 } 6265 iwn_nic_unlock(sc); 6266 6267 if (sc->sc_flags & IWN_FLAG_INTERNAL_PA) { 6268 /* Use internal power amplifier only. */ 6269 IWN_WRITE(sc, IWN_GP_DRIVER, IWN_GP_DRIVER_RADIO_2X2_IPA); 6270 } 6271 if ((sc->hw_type == IWN_HW_REV_TYPE_6050 || 6272 sc->hw_type == IWN_HW_REV_TYPE_6005) && sc->calib_ver >= 6) { 6273 /* Indicate that ROM calibration version is >=6. */ 6274 IWN_SETBITS(sc, IWN_GP_DRIVER, IWN_GP_DRIVER_CALIB_VER6); 6275 } 6276 if (sc->hw_type == IWN_HW_REV_TYPE_6005) 6277 IWN_SETBITS(sc, IWN_GP_DRIVER, IWN_GP_DRIVER_6050_1X2); 6278 return 0; 6279 } 6280 6281 /* 6282 * Take NIC ownership over Intel Active Management Technology (AMT). 6283 */ 6284 static int 6285 iwn_hw_prepare(struct iwn_softc *sc) 6286 { 6287 int ntries; 6288 6289 /* Check if hardware is ready. */ 6290 IWN_SETBITS(sc, IWN_HW_IF_CONFIG, IWN_HW_IF_CONFIG_NIC_READY); 6291 for (ntries = 0; ntries < 5; ntries++) { 6292 if (IWN_READ(sc, IWN_HW_IF_CONFIG) & 6293 IWN_HW_IF_CONFIG_NIC_READY) 6294 return 0; 6295 DELAY(10); 6296 } 6297 6298 /* Hardware not ready, force into ready state. */ 6299 IWN_SETBITS(sc, IWN_HW_IF_CONFIG, IWN_HW_IF_CONFIG_PREPARE); 6300 for (ntries = 0; ntries < 15000; ntries++) { 6301 if (!(IWN_READ(sc, IWN_HW_IF_CONFIG) & 6302 IWN_HW_IF_CONFIG_PREPARE_DONE)) 6303 break; 6304 DELAY(10); 6305 } 6306 if (ntries == 15000) 6307 return ETIMEDOUT; 6308 6309 /* Hardware should be ready now. */ 6310 IWN_SETBITS(sc, IWN_HW_IF_CONFIG, IWN_HW_IF_CONFIG_NIC_READY); 6311 for (ntries = 0; ntries < 5; ntries++) { 6312 if (IWN_READ(sc, IWN_HW_IF_CONFIG) & 6313 IWN_HW_IF_CONFIG_NIC_READY) 6314 return 0; 6315 DELAY(10); 6316 } 6317 return ETIMEDOUT; 6318 } 6319 6320 static int 6321 iwn_hw_init(struct iwn_softc *sc) 6322 { 6323 struct iwn_ops *ops = &sc->ops; 6324 int error, chnl, qid; 6325 6326 /* Clear pending interrupts. */ 6327 IWN_WRITE(sc, IWN_INT, 0xffffffff); 6328 6329 if ((error = iwn_apm_init(sc)) != 0) { 6330 device_printf(sc->sc_dev, 6331 "%s: could not power ON adapter, error %d\n", __func__, 6332 error); 6333 return error; 6334 } 6335 6336 /* Select VMAIN power source. */ 6337 if ((error = iwn_nic_lock(sc)) != 0) 6338 return error; 6339 iwn_prph_clrbits(sc, IWN_APMG_PS, IWN_APMG_PS_PWR_SRC_MASK); 6340 iwn_nic_unlock(sc); 6341 6342 /* Perform adapter-specific initialization. */ 6343 if ((error = ops->nic_config(sc)) != 0) 6344 return error; 6345 6346 /* Initialize RX ring. */ 6347 if ((error = iwn_nic_lock(sc)) != 0) 6348 return error; 6349 IWN_WRITE(sc, IWN_FH_RX_CONFIG, 0); 6350 IWN_WRITE(sc, IWN_FH_RX_WPTR, 0); 6351 /* Set physical address of RX ring (256-byte aligned). */ 6352 IWN_WRITE(sc, IWN_FH_RX_BASE, sc->rxq.desc_dma.paddr >> 8); 6353 /* Set physical address of RX status (16-byte aligned). */ 6354 IWN_WRITE(sc, IWN_FH_STATUS_WPTR, sc->rxq.stat_dma.paddr >> 4); 6355 /* Enable RX. */ 6356 IWN_WRITE(sc, IWN_FH_RX_CONFIG, 6357 IWN_FH_RX_CONFIG_ENA | 6358 IWN_FH_RX_CONFIG_IGN_RXF_EMPTY | /* HW bug workaround */ 6359 IWN_FH_RX_CONFIG_IRQ_DST_HOST | 6360 IWN_FH_RX_CONFIG_SINGLE_FRAME | 6361 IWN_FH_RX_CONFIG_RB_TIMEOUT(0) | 6362 IWN_FH_RX_CONFIG_NRBD(IWN_RX_RING_COUNT_LOG)); 6363 iwn_nic_unlock(sc); 6364 IWN_WRITE(sc, IWN_FH_RX_WPTR, (IWN_RX_RING_COUNT - 1) & ~7); 6365 6366 if ((error = iwn_nic_lock(sc)) != 0) 6367 return error; 6368 6369 /* Initialize TX scheduler. */ 6370 iwn_prph_write(sc, sc->sched_txfact_addr, 0); 6371 6372 /* Set physical address of "keep warm" page (16-byte aligned). */ 6373 IWN_WRITE(sc, IWN_FH_KW_ADDR, sc->kw_dma.paddr >> 4); 6374 6375 /* Initialize TX rings. */ 6376 for (qid = 0; qid < sc->ntxqs; qid++) { 6377 struct iwn_tx_ring *txq = &sc->txq[qid]; 6378 6379 /* Set physical address of TX ring (256-byte aligned). */ 6380 IWN_WRITE(sc, IWN_FH_CBBC_QUEUE(qid), 6381 txq->desc_dma.paddr >> 8); 6382 } 6383 iwn_nic_unlock(sc); 6384 6385 /* Enable DMA channels. */ 6386 for (chnl = 0; chnl < sc->ndmachnls; chnl++) { 6387 IWN_WRITE(sc, IWN_FH_TX_CONFIG(chnl), 6388 IWN_FH_TX_CONFIG_DMA_ENA | 6389 IWN_FH_TX_CONFIG_DMA_CREDIT_ENA); 6390 } 6391 6392 /* Clear "radio off" and "commands blocked" bits. */ 6393 IWN_WRITE(sc, IWN_UCODE_GP1_CLR, IWN_UCODE_GP1_RFKILL); 6394 IWN_WRITE(sc, IWN_UCODE_GP1_CLR, IWN_UCODE_GP1_CMD_BLOCKED); 6395 6396 /* Clear pending interrupts. */ 6397 IWN_WRITE(sc, IWN_INT, 0xffffffff); 6398 /* Enable interrupt coalescing. */ 6399 IWN_WRITE(sc, IWN_INT_COALESCING, 512 / 8); 6400 /* Enable interrupts. */ 6401 IWN_WRITE(sc, IWN_INT_MASK, sc->int_mask); 6402 6403 /* _Really_ make sure "radio off" bit is cleared! */ 6404 IWN_WRITE(sc, IWN_UCODE_GP1_CLR, IWN_UCODE_GP1_RFKILL); 6405 IWN_WRITE(sc, IWN_UCODE_GP1_CLR, IWN_UCODE_GP1_RFKILL); 6406 6407 /* Enable shadow registers. */ 6408 if (sc->hw_type >= IWN_HW_REV_TYPE_6000) 6409 IWN_SETBITS(sc, IWN_SHADOW_REG_CTRL, 0x800fffff); 6410 6411 if ((error = ops->load_firmware(sc)) != 0) { 6412 device_printf(sc->sc_dev, 6413 "%s: could not load firmware, error %d\n", __func__, 6414 error); 6415 return error; 6416 } 6417 /* Wait at most one second for firmware alive notification. */ 6418 if ((error = msleep(sc, &sc->sc_mtx, PCATCH, "iwninit", hz)) != 0) { 6419 device_printf(sc->sc_dev, 6420 "%s: timeout waiting for adapter to initialize, error %d\n", 6421 __func__, error); 6422 return error; 6423 } 6424 /* Do post-firmware initialization. */ 6425 return ops->post_alive(sc); 6426 } 6427 6428 static void 6429 iwn_hw_stop(struct iwn_softc *sc) 6430 { 6431 int chnl, qid, ntries; 6432 6433 IWN_WRITE(sc, IWN_RESET, IWN_RESET_NEVO); 6434 6435 /* Disable interrupts. */ 6436 IWN_WRITE(sc, IWN_INT_MASK, 0); 6437 IWN_WRITE(sc, IWN_INT, 0xffffffff); 6438 IWN_WRITE(sc, IWN_FH_INT, 0xffffffff); 6439 sc->sc_flags &= ~IWN_FLAG_USE_ICT; 6440 6441 /* Make sure we no longer hold the NIC lock. */ 6442 iwn_nic_unlock(sc); 6443 6444 /* Stop TX scheduler. */ 6445 iwn_prph_write(sc, sc->sched_txfact_addr, 0); 6446 6447 /* Stop all DMA channels. */ 6448 if (iwn_nic_lock(sc) == 0) { 6449 for (chnl = 0; chnl < sc->ndmachnls; chnl++) { 6450 IWN_WRITE(sc, IWN_FH_TX_CONFIG(chnl), 0); 6451 for (ntries = 0; ntries < 200; ntries++) { 6452 if (IWN_READ(sc, IWN_FH_TX_STATUS) & 6453 IWN_FH_TX_STATUS_IDLE(chnl)) 6454 break; 6455 DELAY(10); 6456 } 6457 } 6458 iwn_nic_unlock(sc); 6459 } 6460 6461 /* Stop RX ring. */ 6462 iwn_reset_rx_ring(sc, &sc->rxq); 6463 6464 /* Reset all TX rings. */ 6465 for (qid = 0; qid < sc->ntxqs; qid++) 6466 iwn_reset_tx_ring(sc, &sc->txq[qid]); 6467 6468 if (iwn_nic_lock(sc) == 0) { 6469 iwn_prph_write(sc, IWN_APMG_CLK_DIS, 6470 IWN_APMG_CLK_CTRL_DMA_CLK_RQT); 6471 iwn_nic_unlock(sc); 6472 } 6473 DELAY(5); 6474 /* Power OFF adapter. */ 6475 iwn_apm_stop(sc); 6476 } 6477 6478 static void 6479 iwn_radio_on(void *arg0, int pending) 6480 { 6481 struct iwn_softc *sc = arg0; 6482 struct ifnet *ifp = sc->sc_ifp; 6483 struct ieee80211com *ic = ifp->if_l2com; 6484 struct ieee80211vap *vap = TAILQ_FIRST(&ic->ic_vaps); 6485 6486 if (vap != NULL) { 6487 iwn_init(sc); 6488 ieee80211_init(vap); 6489 } 6490 } 6491 6492 static void 6493 iwn_radio_off(void *arg0, int pending) 6494 { 6495 struct iwn_softc *sc = arg0; 6496 struct ifnet *ifp = sc->sc_ifp; 6497 struct ieee80211com *ic = ifp->if_l2com; 6498 struct ieee80211vap *vap = TAILQ_FIRST(&ic->ic_vaps); 6499 6500 iwn_stop(sc); 6501 if (vap != NULL) 6502 ieee80211_stop(vap); 6503 6504 /* Enable interrupts to get RF toggle notification. */ 6505 IWN_LOCK(sc); 6506 IWN_WRITE(sc, IWN_INT, 0xffffffff); 6507 IWN_WRITE(sc, IWN_INT_MASK, sc->int_mask); 6508 IWN_UNLOCK(sc); 6509 } 6510 6511 static void 6512 iwn_init_locked(struct iwn_softc *sc) 6513 { 6514 struct ifnet *ifp = sc->sc_ifp; 6515 int error; 6516 6517 IWN_LOCK_ASSERT(sc); 6518 6519 if ((error = iwn_hw_prepare(sc)) != 0) { 6520 device_printf(sc->sc_dev, "%s: hardware not ready, error %d\n", 6521 __func__, error); 6522 goto fail; 6523 } 6524 6525 /* Initialize interrupt mask to default value. */ 6526 sc->int_mask = IWN_INT_MASK_DEF; 6527 sc->sc_flags &= ~IWN_FLAG_USE_ICT; 6528 6529 /* Check that the radio is not disabled by hardware switch. */ 6530 if (!(IWN_READ(sc, IWN_GP_CNTRL) & IWN_GP_CNTRL_RFKILL)) { 6531 device_printf(sc->sc_dev, 6532 "radio is disabled by hardware switch\n"); 6533 /* Enable interrupts to get RF toggle notifications. */ 6534 IWN_WRITE(sc, IWN_INT, 0xffffffff); 6535 IWN_WRITE(sc, IWN_INT_MASK, sc->int_mask); 6536 return; 6537 } 6538 6539 /* Read firmware images from the filesystem. */ 6540 if ((error = iwn_read_firmware(sc)) != 0) { 6541 device_printf(sc->sc_dev, 6542 "%s: could not read firmware, error %d\n", __func__, 6543 error); 6544 goto fail; 6545 } 6546 6547 /* Initialize hardware and upload firmware. */ 6548 error = iwn_hw_init(sc); 6549 firmware_put(sc->fw_fp, FIRMWARE_UNLOAD); 6550 sc->fw_fp = NULL; 6551 if (error != 0) { 6552 device_printf(sc->sc_dev, 6553 "%s: could not initialize hardware, error %d\n", __func__, 6554 error); 6555 goto fail; 6556 } 6557 6558 /* Configure adapter now that it is ready. */ 6559 if ((error = iwn_config(sc)) != 0) { 6560 device_printf(sc->sc_dev, 6561 "%s: could not configure device, error %d\n", __func__, 6562 error); 6563 goto fail; 6564 } 6565 6566 ifp->if_drv_flags &= ~IFF_DRV_OACTIVE; 6567 ifp->if_drv_flags |= IFF_DRV_RUNNING; 6568 6569 callout_reset(&sc->watchdog_to, hz, iwn_watchdog, sc); 6570 return; 6571 6572 fail: iwn_stop_locked(sc); 6573 } 6574 6575 static void 6576 iwn_init(void *arg) 6577 { 6578 struct iwn_softc *sc = arg; 6579 struct ifnet *ifp = sc->sc_ifp; 6580 struct ieee80211com *ic = ifp->if_l2com; 6581 6582 IWN_LOCK(sc); 6583 iwn_init_locked(sc); 6584 IWN_UNLOCK(sc); 6585 6586 if (ifp->if_drv_flags & IFF_DRV_RUNNING) 6587 ieee80211_start_all(ic); 6588 } 6589 6590 static void 6591 iwn_stop_locked(struct iwn_softc *sc) 6592 { 6593 struct ifnet *ifp = sc->sc_ifp; 6594 6595 IWN_LOCK_ASSERT(sc); 6596 6597 sc->sc_tx_timer = 0; 6598 callout_stop(&sc->watchdog_to); 6599 callout_stop(&sc->calib_to); 6600 ifp->if_drv_flags &= ~(IFF_DRV_RUNNING | IFF_DRV_OACTIVE); 6601 6602 /* Power OFF hardware. */ 6603 iwn_hw_stop(sc); 6604 } 6605 6606 static void 6607 iwn_stop(struct iwn_softc *sc) 6608 { 6609 IWN_LOCK(sc); 6610 iwn_stop_locked(sc); 6611 IWN_UNLOCK(sc); 6612 } 6613 6614 /* 6615 * Callback from net80211 to start a scan. 6616 */ 6617 static void 6618 iwn_scan_start(struct ieee80211com *ic) 6619 { 6620 struct ifnet *ifp = ic->ic_ifp; 6621 struct iwn_softc *sc = ifp->if_softc; 6622 6623 IWN_LOCK(sc); 6624 /* make the link LED blink while we're scanning */ 6625 iwn_set_led(sc, IWN_LED_LINK, 20, 2); 6626 IWN_UNLOCK(sc); 6627 } 6628 6629 /* 6630 * Callback from net80211 to terminate a scan. 6631 */ 6632 static void 6633 iwn_scan_end(struct ieee80211com *ic) 6634 { 6635 struct ifnet *ifp = ic->ic_ifp; 6636 struct iwn_softc *sc = ifp->if_softc; 6637 struct ieee80211vap *vap = TAILQ_FIRST(&ic->ic_vaps); 6638 6639 IWN_LOCK(sc); 6640 if (vap->iv_state == IEEE80211_S_RUN) { 6641 /* Set link LED to ON status if we are associated */ 6642 iwn_set_led(sc, IWN_LED_LINK, 0, 1); 6643 } 6644 IWN_UNLOCK(sc); 6645 } 6646 6647 /* 6648 * Callback from net80211 to force a channel change. 6649 */ 6650 static void 6651 iwn_set_channel(struct ieee80211com *ic) 6652 { 6653 const struct ieee80211_channel *c = ic->ic_curchan; 6654 struct ifnet *ifp = ic->ic_ifp; 6655 struct iwn_softc *sc = ifp->if_softc; 6656 6657 IWN_LOCK(sc); 6658 sc->sc_rxtap.wr_chan_freq = htole16(c->ic_freq); 6659 sc->sc_rxtap.wr_chan_flags = htole16(c->ic_flags); 6660 sc->sc_txtap.wt_chan_freq = htole16(c->ic_freq); 6661 sc->sc_txtap.wt_chan_flags = htole16(c->ic_flags); 6662 IWN_UNLOCK(sc); 6663 } 6664 6665 /* 6666 * Callback from net80211 to start scanning of the current channel. 6667 */ 6668 static void 6669 iwn_scan_curchan(struct ieee80211_scan_state *ss, unsigned long maxdwell) 6670 { 6671 struct ieee80211vap *vap = ss->ss_vap; 6672 struct iwn_softc *sc = vap->iv_ic->ic_ifp->if_softc; 6673 int error; 6674 6675 IWN_LOCK(sc); 6676 error = iwn_scan(sc); 6677 IWN_UNLOCK(sc); 6678 if (error != 0) 6679 ieee80211_cancel_scan(vap); 6680 } 6681 6682 /* 6683 * Callback from net80211 to handle the minimum dwell time being met. 6684 * The intent is to terminate the scan but we just let the firmware 6685 * notify us when it's finished as we have no safe way to abort it. 6686 */ 6687 static void 6688 iwn_scan_mindwell(struct ieee80211_scan_state *ss) 6689 { 6690 /* NB: don't try to abort scan; wait for firmware to finish */ 6691 } 6692 6693 static void 6694 iwn_hw_reset(void *arg0, int pending) 6695 { 6696 struct iwn_softc *sc = arg0; 6697 struct ifnet *ifp = sc->sc_ifp; 6698 struct ieee80211com *ic = ifp->if_l2com; 6699 6700 iwn_stop(sc); 6701 iwn_init(sc); 6702 ieee80211_notify_radio(ic, 1); 6703 } 6704