xref: /freebsd/sys/dev/iwn/if_iwn.c (revision 298022457a9a016cbdda4e22d751abb5cd91c919)
1 /*-
2  * Copyright (c) 2007-2009 Damien Bergamini <damien.bergamini@free.fr>
3  * Copyright (c) 2008 Benjamin Close <benjsc@FreeBSD.org>
4  * Copyright (c) 2008 Sam Leffler, Errno Consulting
5  * Copyright (c) 2011 Intel Corporation
6  * Copyright (c) 2013 Cedric GROSS <c.gross@kreiz-it.fr>
7  * Copyright (c) 2013 Adrian Chadd <adrian@FreeBSD.org>
8  *
9  * Permission to use, copy, modify, and distribute this software for any
10  * purpose with or without fee is hereby granted, provided that the above
11  * copyright notice and this permission notice appear in all copies.
12  *
13  * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
14  * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
15  * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
16  * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
17  * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
18  * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
19  * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
20  */
21 
22 /*
23  * Driver for Intel WiFi Link 4965 and 1000/5000/6000 Series 802.11 network
24  * adapters.
25  */
26 
27 #include <sys/cdefs.h>
28 __FBSDID("$FreeBSD$");
29 
30 #include "opt_wlan.h"
31 #include "opt_iwn.h"
32 
33 #include <sys/param.h>
34 #include <sys/sockio.h>
35 #include <sys/sysctl.h>
36 #include <sys/mbuf.h>
37 #include <sys/kernel.h>
38 #include <sys/socket.h>
39 #include <sys/systm.h>
40 #include <sys/malloc.h>
41 #include <sys/bus.h>
42 #include <sys/rman.h>
43 #include <sys/endian.h>
44 #include <sys/firmware.h>
45 #include <sys/limits.h>
46 #include <sys/module.h>
47 #include <sys/queue.h>
48 #include <sys/taskqueue.h>
49 
50 #include <machine/bus.h>
51 #include <machine/resource.h>
52 #include <machine/clock.h>
53 
54 #include <dev/pci/pcireg.h>
55 #include <dev/pci/pcivar.h>
56 
57 #include <net/bpf.h>
58 #include <net/if.h>
59 #include <net/if_var.h>
60 #include <net/if_arp.h>
61 #include <net/ethernet.h>
62 #include <net/if_dl.h>
63 #include <net/if_media.h>
64 #include <net/if_types.h>
65 
66 #include <netinet/in.h>
67 #include <netinet/in_systm.h>
68 #include <netinet/in_var.h>
69 #include <netinet/if_ether.h>
70 #include <netinet/ip.h>
71 
72 #include <net80211/ieee80211_var.h>
73 #include <net80211/ieee80211_radiotap.h>
74 #include <net80211/ieee80211_regdomain.h>
75 #include <net80211/ieee80211_ratectl.h>
76 
77 #include <dev/iwn/if_iwnreg.h>
78 #include <dev/iwn/if_iwnvar.h>
79 #include <dev/iwn/if_iwn_devid.h>
80 #include <dev/iwn/if_iwn_chip_cfg.h>
81 #include <dev/iwn/if_iwn_debug.h>
82 #include <dev/iwn/if_iwn_ioctl.h>
83 
84 struct iwn_ident {
85 	uint16_t	vendor;
86 	uint16_t	device;
87 	const char	*name;
88 };
89 
90 static const struct iwn_ident iwn_ident_table[] = {
91 	{ 0x8086, IWN_DID_6x05_1, "Intel Centrino Advanced-N 6205"		},
92 	{ 0x8086, IWN_DID_1000_1, "Intel Centrino Wireless-N 1000"		},
93 	{ 0x8086, IWN_DID_1000_2, "Intel Centrino Wireless-N 1000"		},
94 	{ 0x8086, IWN_DID_6x05_2, "Intel Centrino Advanced-N 6205"		},
95 	{ 0x8086, IWN_DID_6050_1, "Intel Centrino Advanced-N + WiMAX 6250"	},
96 	{ 0x8086, IWN_DID_6050_2, "Intel Centrino Advanced-N + WiMAX 6250"	},
97 	{ 0x8086, IWN_DID_x030_1, "Intel Centrino Wireless-N 1030"		},
98 	{ 0x8086, IWN_DID_x030_2, "Intel Centrino Wireless-N 1030"		},
99 	{ 0x8086, IWN_DID_x030_3, "Intel Centrino Advanced-N 6230"		},
100 	{ 0x8086, IWN_DID_x030_4, "Intel Centrino Advanced-N 6230"		},
101 	{ 0x8086, IWN_DID_6150_1, "Intel Centrino Wireless-N + WiMAX 6150"	},
102 	{ 0x8086, IWN_DID_6150_2, "Intel Centrino Wireless-N + WiMAX 6150"	},
103 	{ 0x8086, IWN_DID_2x00_1, "Intel(R) Centrino(R) Wireless-N 2200 BGN"	},
104 	{ 0x8086, IWN_DID_2x00_2, "Intel(R) Centrino(R) Wireless-N 2200 BGN"	},
105 	/* XXX 2200D is IWN_SDID_2x00_4; there's no way to express this here! */
106 	{ 0x8086, IWN_DID_2x30_1, "Intel Centrino Wireless-N 2230"		},
107 	{ 0x8086, IWN_DID_2x30_2, "Intel Centrino Wireless-N 2230"		},
108 	{ 0x8086, IWN_DID_130_1, "Intel Centrino Wireless-N 130"		},
109 	{ 0x8086, IWN_DID_130_2, "Intel Centrino Wireless-N 130"		},
110 	{ 0x8086, IWN_DID_100_1, "Intel Centrino Wireless-N 100"		},
111 	{ 0x8086, IWN_DID_100_2, "Intel Centrino Wireless-N 100"		},
112 	{ 0x8086, IWN_DID_105_1, "Intel Centrino Wireless-N 105"		},
113 	{ 0x8086, IWN_DID_105_2, "Intel Centrino Wireless-N 105"		},
114 	{ 0x8086, IWN_DID_135_1, "Intel Centrino Wireless-N 135"		},
115 	{ 0x8086, IWN_DID_135_2, "Intel Centrino Wireless-N 135"		},
116 	{ 0x8086, IWN_DID_4965_1, "Intel Wireless WiFi Link 4965"		},
117 	{ 0x8086, IWN_DID_6x00_1, "Intel Centrino Ultimate-N 6300"		},
118 	{ 0x8086, IWN_DID_6x00_2, "Intel Centrino Advanced-N 6200"		},
119 	{ 0x8086, IWN_DID_4965_2, "Intel Wireless WiFi Link 4965"		},
120 	{ 0x8086, IWN_DID_4965_3, "Intel Wireless WiFi Link 4965"		},
121 	{ 0x8086, IWN_DID_5x00_1, "Intel WiFi Link 5100"			},
122 	{ 0x8086, IWN_DID_4965_4, "Intel Wireless WiFi Link 4965"		},
123 	{ 0x8086, IWN_DID_5x00_3, "Intel Ultimate N WiFi Link 5300"		},
124 	{ 0x8086, IWN_DID_5x00_4, "Intel Ultimate N WiFi Link 5300"		},
125 	{ 0x8086, IWN_DID_5x00_2, "Intel WiFi Link 5100"			},
126 	{ 0x8086, IWN_DID_6x00_3, "Intel Centrino Ultimate-N 6300"		},
127 	{ 0x8086, IWN_DID_6x00_4, "Intel Centrino Advanced-N 6200"		},
128 	{ 0x8086, IWN_DID_5x50_1, "Intel WiMAX/WiFi Link 5350"			},
129 	{ 0x8086, IWN_DID_5x50_2, "Intel WiMAX/WiFi Link 5350"			},
130 	{ 0x8086, IWN_DID_5x50_3, "Intel WiMAX/WiFi Link 5150"			},
131 	{ 0x8086, IWN_DID_5x50_4, "Intel WiMAX/WiFi Link 5150"			},
132 	{ 0x8086, IWN_DID_6035_1, "Intel Centrino Advanced 6235"		},
133 	{ 0x8086, IWN_DID_6035_2, "Intel Centrino Advanced 6235"		},
134 	{ 0, 0, NULL }
135 };
136 
137 static int	iwn_probe(device_t);
138 static int	iwn_attach(device_t);
139 static int	iwn4965_attach(struct iwn_softc *, uint16_t);
140 static int	iwn5000_attach(struct iwn_softc *, uint16_t);
141 static int	iwn_config_specific(struct iwn_softc *, uint16_t);
142 static void	iwn_radiotap_attach(struct iwn_softc *);
143 static void	iwn_sysctlattach(struct iwn_softc *);
144 static struct ieee80211vap *iwn_vap_create(struct ieee80211com *,
145 		    const char [IFNAMSIZ], int, enum ieee80211_opmode, int,
146 		    const uint8_t [IEEE80211_ADDR_LEN],
147 		    const uint8_t [IEEE80211_ADDR_LEN]);
148 static void	iwn_vap_delete(struct ieee80211vap *);
149 static int	iwn_detach(device_t);
150 static int	iwn_shutdown(device_t);
151 static int	iwn_suspend(device_t);
152 static int	iwn_resume(device_t);
153 static int	iwn_nic_lock(struct iwn_softc *);
154 static int	iwn_eeprom_lock(struct iwn_softc *);
155 static int	iwn_init_otprom(struct iwn_softc *);
156 static int	iwn_read_prom_data(struct iwn_softc *, uint32_t, void *, int);
157 static void	iwn_dma_map_addr(void *, bus_dma_segment_t *, int, int);
158 static int	iwn_dma_contig_alloc(struct iwn_softc *, struct iwn_dma_info *,
159 		    void **, bus_size_t, bus_size_t);
160 static void	iwn_dma_contig_free(struct iwn_dma_info *);
161 static int	iwn_alloc_sched(struct iwn_softc *);
162 static void	iwn_free_sched(struct iwn_softc *);
163 static int	iwn_alloc_kw(struct iwn_softc *);
164 static void	iwn_free_kw(struct iwn_softc *);
165 static int	iwn_alloc_ict(struct iwn_softc *);
166 static void	iwn_free_ict(struct iwn_softc *);
167 static int	iwn_alloc_fwmem(struct iwn_softc *);
168 static void	iwn_free_fwmem(struct iwn_softc *);
169 static int	iwn_alloc_rx_ring(struct iwn_softc *, struct iwn_rx_ring *);
170 static void	iwn_reset_rx_ring(struct iwn_softc *, struct iwn_rx_ring *);
171 static void	iwn_free_rx_ring(struct iwn_softc *, struct iwn_rx_ring *);
172 static int	iwn_alloc_tx_ring(struct iwn_softc *, struct iwn_tx_ring *,
173 		    int);
174 static void	iwn_reset_tx_ring(struct iwn_softc *, struct iwn_tx_ring *);
175 static void	iwn_free_tx_ring(struct iwn_softc *, struct iwn_tx_ring *);
176 static void	iwn5000_ict_reset(struct iwn_softc *);
177 static int	iwn_read_eeprom(struct iwn_softc *,
178 		    uint8_t macaddr[IEEE80211_ADDR_LEN]);
179 static void	iwn4965_read_eeprom(struct iwn_softc *);
180 #ifdef	IWN_DEBUG
181 static void	iwn4965_print_power_group(struct iwn_softc *, int);
182 #endif
183 static void	iwn5000_read_eeprom(struct iwn_softc *);
184 static uint32_t	iwn_eeprom_channel_flags(struct iwn_eeprom_chan *);
185 static void	iwn_read_eeprom_band(struct iwn_softc *, int);
186 static void	iwn_read_eeprom_ht40(struct iwn_softc *, int);
187 static void	iwn_read_eeprom_channels(struct iwn_softc *, int, uint32_t);
188 static struct iwn_eeprom_chan *iwn_find_eeprom_channel(struct iwn_softc *,
189 		    struct ieee80211_channel *);
190 static int	iwn_setregdomain(struct ieee80211com *,
191 		    struct ieee80211_regdomain *, int,
192 		    struct ieee80211_channel[]);
193 static void	iwn_read_eeprom_enhinfo(struct iwn_softc *);
194 static struct ieee80211_node *iwn_node_alloc(struct ieee80211vap *,
195 		    const uint8_t mac[IEEE80211_ADDR_LEN]);
196 static void	iwn_newassoc(struct ieee80211_node *, int);
197 static int	iwn_media_change(struct ifnet *);
198 static int	iwn_newstate(struct ieee80211vap *, enum ieee80211_state, int);
199 static void	iwn_calib_timeout(void *);
200 static void	iwn_rx_phy(struct iwn_softc *, struct iwn_rx_desc *,
201 		    struct iwn_rx_data *);
202 static void	iwn_rx_done(struct iwn_softc *, struct iwn_rx_desc *,
203 		    struct iwn_rx_data *);
204 static void	iwn_rx_compressed_ba(struct iwn_softc *, struct iwn_rx_desc *,
205 		    struct iwn_rx_data *);
206 static void	iwn5000_rx_calib_results(struct iwn_softc *,
207 		    struct iwn_rx_desc *, struct iwn_rx_data *);
208 static void	iwn_rx_statistics(struct iwn_softc *, struct iwn_rx_desc *,
209 		    struct iwn_rx_data *);
210 static void	iwn4965_tx_done(struct iwn_softc *, struct iwn_rx_desc *,
211 		    struct iwn_rx_data *);
212 static void	iwn5000_tx_done(struct iwn_softc *, struct iwn_rx_desc *,
213 		    struct iwn_rx_data *);
214 static void	iwn_tx_done(struct iwn_softc *, struct iwn_rx_desc *, int,
215 		    uint8_t);
216 static void	iwn_ampdu_tx_done(struct iwn_softc *, int, int, int, int, void *);
217 static void	iwn_cmd_done(struct iwn_softc *, struct iwn_rx_desc *);
218 static void	iwn_notif_intr(struct iwn_softc *);
219 static void	iwn_wakeup_intr(struct iwn_softc *);
220 static void	iwn_rftoggle_intr(struct iwn_softc *);
221 static void	iwn_fatal_intr(struct iwn_softc *);
222 static void	iwn_intr(void *);
223 static void	iwn4965_update_sched(struct iwn_softc *, int, int, uint8_t,
224 		    uint16_t);
225 static void	iwn5000_update_sched(struct iwn_softc *, int, int, uint8_t,
226 		    uint16_t);
227 #ifdef notyet
228 static void	iwn5000_reset_sched(struct iwn_softc *, int, int);
229 #endif
230 static int	iwn_tx_data(struct iwn_softc *, struct mbuf *,
231 		    struct ieee80211_node *);
232 static int	iwn_tx_data_raw(struct iwn_softc *, struct mbuf *,
233 		    struct ieee80211_node *,
234 		    const struct ieee80211_bpf_params *params);
235 static void	iwn_xmit_task(void *arg0, int pending);
236 static int	iwn_raw_xmit(struct ieee80211_node *, struct mbuf *,
237 		    const struct ieee80211_bpf_params *);
238 static void	iwn_start(struct ifnet *);
239 static void	iwn_start_locked(struct ifnet *);
240 static void	iwn_watchdog(void *);
241 static int	iwn_ioctl(struct ifnet *, u_long, caddr_t);
242 static int	iwn_cmd(struct iwn_softc *, int, const void *, int, int);
243 static int	iwn4965_add_node(struct iwn_softc *, struct iwn_node_info *,
244 		    int);
245 static int	iwn5000_add_node(struct iwn_softc *, struct iwn_node_info *,
246 		    int);
247 static int	iwn_set_link_quality(struct iwn_softc *,
248 		    struct ieee80211_node *);
249 static int	iwn_add_broadcast_node(struct iwn_softc *, int);
250 static int	iwn_updateedca(struct ieee80211com *);
251 static void	iwn_update_mcast(struct ieee80211com *);
252 static void	iwn_set_led(struct iwn_softc *, uint8_t, uint8_t, uint8_t);
253 static int	iwn_set_critical_temp(struct iwn_softc *);
254 static int	iwn_set_timing(struct iwn_softc *, struct ieee80211_node *);
255 static void	iwn4965_power_calibration(struct iwn_softc *, int);
256 static int	iwn4965_set_txpower(struct iwn_softc *,
257 		    struct ieee80211_channel *, int);
258 static int	iwn5000_set_txpower(struct iwn_softc *,
259 		    struct ieee80211_channel *, int);
260 static int	iwn4965_get_rssi(struct iwn_softc *, struct iwn_rx_stat *);
261 static int	iwn5000_get_rssi(struct iwn_softc *, struct iwn_rx_stat *);
262 static int	iwn_get_noise(const struct iwn_rx_general_stats *);
263 static int	iwn4965_get_temperature(struct iwn_softc *);
264 static int	iwn5000_get_temperature(struct iwn_softc *);
265 static int	iwn_init_sensitivity(struct iwn_softc *);
266 static void	iwn_collect_noise(struct iwn_softc *,
267 		    const struct iwn_rx_general_stats *);
268 static int	iwn4965_init_gains(struct iwn_softc *);
269 static int	iwn5000_init_gains(struct iwn_softc *);
270 static int	iwn4965_set_gains(struct iwn_softc *);
271 static int	iwn5000_set_gains(struct iwn_softc *);
272 static void	iwn_tune_sensitivity(struct iwn_softc *,
273 		    const struct iwn_rx_stats *);
274 static void	iwn_save_stats_counters(struct iwn_softc *,
275 		    const struct iwn_stats *);
276 static int	iwn_send_sensitivity(struct iwn_softc *);
277 static void	iwn_check_rx_recovery(struct iwn_softc *, struct iwn_stats *);
278 static int	iwn_set_pslevel(struct iwn_softc *, int, int, int);
279 static int	iwn_send_btcoex(struct iwn_softc *);
280 static int	iwn_send_advanced_btcoex(struct iwn_softc *);
281 static int	iwn5000_runtime_calib(struct iwn_softc *);
282 static int	iwn_config(struct iwn_softc *);
283 static int	iwn_scan(struct iwn_softc *, struct ieee80211vap *,
284 		    struct ieee80211_scan_state *, struct ieee80211_channel *);
285 static int	iwn_auth(struct iwn_softc *, struct ieee80211vap *vap);
286 static int	iwn_run(struct iwn_softc *, struct ieee80211vap *vap);
287 static int	iwn_ampdu_rx_start(struct ieee80211_node *,
288 		    struct ieee80211_rx_ampdu *, int, int, int);
289 static void	iwn_ampdu_rx_stop(struct ieee80211_node *,
290 		    struct ieee80211_rx_ampdu *);
291 static int	iwn_addba_request(struct ieee80211_node *,
292 		    struct ieee80211_tx_ampdu *, int, int, int);
293 static int	iwn_addba_response(struct ieee80211_node *,
294 		    struct ieee80211_tx_ampdu *, int, int, int);
295 static int	iwn_ampdu_tx_start(struct ieee80211com *,
296 		    struct ieee80211_node *, uint8_t);
297 static void	iwn_ampdu_tx_stop(struct ieee80211_node *,
298 		    struct ieee80211_tx_ampdu *);
299 static void	iwn4965_ampdu_tx_start(struct iwn_softc *,
300 		    struct ieee80211_node *, int, uint8_t, uint16_t);
301 static void	iwn4965_ampdu_tx_stop(struct iwn_softc *, int,
302 		    uint8_t, uint16_t);
303 static void	iwn5000_ampdu_tx_start(struct iwn_softc *,
304 		    struct ieee80211_node *, int, uint8_t, uint16_t);
305 static void	iwn5000_ampdu_tx_stop(struct iwn_softc *, int,
306 		    uint8_t, uint16_t);
307 static int	iwn5000_query_calibration(struct iwn_softc *);
308 static int	iwn5000_send_calibration(struct iwn_softc *);
309 static int	iwn5000_send_wimax_coex(struct iwn_softc *);
310 static int	iwn5000_crystal_calib(struct iwn_softc *);
311 static int	iwn5000_temp_offset_calib(struct iwn_softc *);
312 static int	iwn5000_temp_offset_calibv2(struct iwn_softc *);
313 static int	iwn4965_post_alive(struct iwn_softc *);
314 static int	iwn5000_post_alive(struct iwn_softc *);
315 static int	iwn4965_load_bootcode(struct iwn_softc *, const uint8_t *,
316 		    int);
317 static int	iwn4965_load_firmware(struct iwn_softc *);
318 static int	iwn5000_load_firmware_section(struct iwn_softc *, uint32_t,
319 		    const uint8_t *, int);
320 static int	iwn5000_load_firmware(struct iwn_softc *);
321 static int	iwn_read_firmware_leg(struct iwn_softc *,
322 		    struct iwn_fw_info *);
323 static int	iwn_read_firmware_tlv(struct iwn_softc *,
324 		    struct iwn_fw_info *, uint16_t);
325 static int	iwn_read_firmware(struct iwn_softc *);
326 static int	iwn_clock_wait(struct iwn_softc *);
327 static int	iwn_apm_init(struct iwn_softc *);
328 static void	iwn_apm_stop_master(struct iwn_softc *);
329 static void	iwn_apm_stop(struct iwn_softc *);
330 static int	iwn4965_nic_config(struct iwn_softc *);
331 static int	iwn5000_nic_config(struct iwn_softc *);
332 static int	iwn_hw_prepare(struct iwn_softc *);
333 static int	iwn_hw_init(struct iwn_softc *);
334 static void	iwn_hw_stop(struct iwn_softc *);
335 static void	iwn_radio_on(void *, int);
336 static void	iwn_radio_off(void *, int);
337 static void	iwn_panicked(void *, int);
338 static void	iwn_init_locked(struct iwn_softc *);
339 static void	iwn_init(void *);
340 static void	iwn_stop_locked(struct iwn_softc *);
341 static void	iwn_stop(struct iwn_softc *);
342 static void	iwn_scan_start(struct ieee80211com *);
343 static void	iwn_scan_end(struct ieee80211com *);
344 static void	iwn_set_channel(struct ieee80211com *);
345 static void	iwn_scan_curchan(struct ieee80211_scan_state *, unsigned long);
346 static void	iwn_scan_mindwell(struct ieee80211_scan_state *);
347 static void	iwn_hw_reset(void *, int);
348 #ifdef	IWN_DEBUG
349 static char	*iwn_get_csr_string(int);
350 static void	iwn_debug_register(struct iwn_softc *);
351 #endif
352 
353 static device_method_t iwn_methods[] = {
354 	/* Device interface */
355 	DEVMETHOD(device_probe,		iwn_probe),
356 	DEVMETHOD(device_attach,	iwn_attach),
357 	DEVMETHOD(device_detach,	iwn_detach),
358 	DEVMETHOD(device_shutdown,	iwn_shutdown),
359 	DEVMETHOD(device_suspend,	iwn_suspend),
360 	DEVMETHOD(device_resume,	iwn_resume),
361 
362 	DEVMETHOD_END
363 };
364 
365 static driver_t iwn_driver = {
366 	"iwn",
367 	iwn_methods,
368 	sizeof(struct iwn_softc)
369 };
370 static devclass_t iwn_devclass;
371 
372 DRIVER_MODULE(iwn, pci, iwn_driver, iwn_devclass, NULL, NULL);
373 
374 MODULE_VERSION(iwn, 1);
375 
376 MODULE_DEPEND(iwn, firmware, 1, 1, 1);
377 MODULE_DEPEND(iwn, pci, 1, 1, 1);
378 MODULE_DEPEND(iwn, wlan, 1, 1, 1);
379 
380 static int
381 iwn_probe(device_t dev)
382 {
383 	const struct iwn_ident *ident;
384 
385 	for (ident = iwn_ident_table; ident->name != NULL; ident++) {
386 		if (pci_get_vendor(dev) == ident->vendor &&
387 		    pci_get_device(dev) == ident->device) {
388 			device_set_desc(dev, ident->name);
389 			return (BUS_PROBE_DEFAULT);
390 		}
391 	}
392 	return ENXIO;
393 }
394 
395 static int
396 iwn_is_3stream_device(struct iwn_softc *sc)
397 {
398 	/* XXX for now only 5300, until the 5350 can be tested */
399 	if (sc->hw_type == IWN_HW_REV_TYPE_5300)
400 		return (1);
401 	return (0);
402 }
403 
404 static int
405 iwn_attach(device_t dev)
406 {
407 	struct iwn_softc *sc = (struct iwn_softc *)device_get_softc(dev);
408 	struct ieee80211com *ic;
409 	struct ifnet *ifp;
410 	int i, error, rid;
411 	uint8_t macaddr[IEEE80211_ADDR_LEN];
412 
413 	sc->sc_dev = dev;
414 
415 #ifdef	IWN_DEBUG
416 	error = resource_int_value(device_get_name(sc->sc_dev),
417 	    device_get_unit(sc->sc_dev), "debug", &(sc->sc_debug));
418 	if (error != 0)
419 		sc->sc_debug = 0;
420 #else
421 	sc->sc_debug = 0;
422 #endif
423 
424 	DPRINTF(sc, IWN_DEBUG_TRACE, "->%s: begin\n",__func__);
425 
426 	/*
427 	 * Get the offset of the PCI Express Capability Structure in PCI
428 	 * Configuration Space.
429 	 */
430 	error = pci_find_cap(dev, PCIY_EXPRESS, &sc->sc_cap_off);
431 	if (error != 0) {
432 		device_printf(dev, "PCIe capability structure not found!\n");
433 		return error;
434 	}
435 
436 	/* Clear device-specific "PCI retry timeout" register (41h). */
437 	pci_write_config(dev, 0x41, 0, 1);
438 
439 	/* Enable bus-mastering. */
440 	pci_enable_busmaster(dev);
441 
442 	rid = PCIR_BAR(0);
443 	sc->mem = bus_alloc_resource_any(dev, SYS_RES_MEMORY, &rid,
444 	    RF_ACTIVE);
445 	if (sc->mem == NULL) {
446 		device_printf(dev, "can't map mem space\n");
447 		error = ENOMEM;
448 		return error;
449 	}
450 	sc->sc_st = rman_get_bustag(sc->mem);
451 	sc->sc_sh = rman_get_bushandle(sc->mem);
452 
453 	i = 1;
454 	rid = 0;
455 	if (pci_alloc_msi(dev, &i) == 0)
456 		rid = 1;
457 	/* Install interrupt handler. */
458 	sc->irq = bus_alloc_resource_any(dev, SYS_RES_IRQ, &rid, RF_ACTIVE |
459 	    (rid != 0 ? 0 : RF_SHAREABLE));
460 	if (sc->irq == NULL) {
461 		device_printf(dev, "can't map interrupt\n");
462 		error = ENOMEM;
463 		goto fail;
464 	}
465 
466 	IWN_LOCK_INIT(sc);
467 
468 	/* Read hardware revision and attach. */
469 	sc->hw_type = (IWN_READ(sc, IWN_HW_REV) >> IWN_HW_REV_TYPE_SHIFT)
470 	    & IWN_HW_REV_TYPE_MASK;
471 	sc->subdevice_id = pci_get_subdevice(dev);
472 
473 	/*
474 	 * 4965 versus 5000 and later have different methods.
475 	 * Let's set those up first.
476 	 */
477 	if (sc->hw_type == IWN_HW_REV_TYPE_4965)
478 		error = iwn4965_attach(sc, pci_get_device(dev));
479 	else
480 		error = iwn5000_attach(sc, pci_get_device(dev));
481 	if (error != 0) {
482 		device_printf(dev, "could not attach device, error %d\n",
483 		    error);
484 		goto fail;
485 	}
486 
487 	/*
488 	 * Next, let's setup the various parameters of each NIC.
489 	 */
490 	error = iwn_config_specific(sc, pci_get_device(dev));
491 	if (error != 0) {
492 		device_printf(dev, "could not attach device, error %d\n",
493 		    error);
494 		goto fail;
495 	}
496 
497 	if ((error = iwn_hw_prepare(sc)) != 0) {
498 		device_printf(dev, "hardware not ready, error %d\n", error);
499 		goto fail;
500 	}
501 
502 	/* Allocate DMA memory for firmware transfers. */
503 	if ((error = iwn_alloc_fwmem(sc)) != 0) {
504 		device_printf(dev,
505 		    "could not allocate memory for firmware, error %d\n",
506 		    error);
507 		goto fail;
508 	}
509 
510 	/* Allocate "Keep Warm" page. */
511 	if ((error = iwn_alloc_kw(sc)) != 0) {
512 		device_printf(dev,
513 		    "could not allocate keep warm page, error %d\n", error);
514 		goto fail;
515 	}
516 
517 	/* Allocate ICT table for 5000 Series. */
518 	if (sc->hw_type != IWN_HW_REV_TYPE_4965 &&
519 	    (error = iwn_alloc_ict(sc)) != 0) {
520 		device_printf(dev, "could not allocate ICT table, error %d\n",
521 		    error);
522 		goto fail;
523 	}
524 
525 	/* Allocate TX scheduler "rings". */
526 	if ((error = iwn_alloc_sched(sc)) != 0) {
527 		device_printf(dev,
528 		    "could not allocate TX scheduler rings, error %d\n", error);
529 		goto fail;
530 	}
531 
532 	/* Allocate TX rings (16 on 4965AGN, 20 on >=5000). */
533 	for (i = 0; i < sc->ntxqs; i++) {
534 		if ((error = iwn_alloc_tx_ring(sc, &sc->txq[i], i)) != 0) {
535 			device_printf(dev,
536 			    "could not allocate TX ring %d, error %d\n", i,
537 			    error);
538 			goto fail;
539 		}
540 	}
541 
542 	/* Allocate RX ring. */
543 	if ((error = iwn_alloc_rx_ring(sc, &sc->rxq)) != 0) {
544 		device_printf(dev, "could not allocate RX ring, error %d\n",
545 		    error);
546 		goto fail;
547 	}
548 
549 	/* Clear pending interrupts. */
550 	IWN_WRITE(sc, IWN_INT, 0xffffffff);
551 
552 	ifp = sc->sc_ifp = if_alloc(IFT_IEEE80211);
553 	if (ifp == NULL) {
554 		device_printf(dev, "can not allocate ifnet structure\n");
555 		goto fail;
556 	}
557 
558 	ic = ifp->if_l2com;
559 	ic->ic_ifp = ifp;
560 	ic->ic_softc = sc;
561 	ic->ic_name = device_get_nameunit(dev);
562 	ic->ic_phytype = IEEE80211_T_OFDM;	/* not only, but not used */
563 	ic->ic_opmode = IEEE80211_M_STA;	/* default to BSS mode */
564 
565 	/* Set device capabilities. */
566 	ic->ic_caps =
567 		  IEEE80211_C_STA		/* station mode supported */
568 		| IEEE80211_C_MONITOR		/* monitor mode supported */
569 #if 0
570 		| IEEE80211_C_BGSCAN		/* background scanning */
571 #endif
572 		| IEEE80211_C_TXPMGT		/* tx power management */
573 		| IEEE80211_C_SHSLOT		/* short slot time supported */
574 		| IEEE80211_C_WPA
575 		| IEEE80211_C_SHPREAMBLE	/* short preamble supported */
576 #if 0
577 		| IEEE80211_C_IBSS		/* ibss/adhoc mode */
578 #endif
579 		| IEEE80211_C_WME		/* WME */
580 		| IEEE80211_C_PMGT		/* Station-side power mgmt */
581 		;
582 
583 	/* Read MAC address, channels, etc from EEPROM. */
584 	if ((error = iwn_read_eeprom(sc, macaddr)) != 0) {
585 		device_printf(dev, "could not read EEPROM, error %d\n",
586 		    error);
587 		goto fail;
588 	}
589 
590 	/* Count the number of available chains. */
591 	sc->ntxchains =
592 	    ((sc->txchainmask >> 2) & 1) +
593 	    ((sc->txchainmask >> 1) & 1) +
594 	    ((sc->txchainmask >> 0) & 1);
595 	sc->nrxchains =
596 	    ((sc->rxchainmask >> 2) & 1) +
597 	    ((sc->rxchainmask >> 1) & 1) +
598 	    ((sc->rxchainmask >> 0) & 1);
599 	if (bootverbose) {
600 		device_printf(dev, "MIMO %dT%dR, %.4s, address %6D\n",
601 		    sc->ntxchains, sc->nrxchains, sc->eeprom_domain,
602 		    macaddr, ":");
603 	}
604 
605 	if (sc->sc_flags & IWN_FLAG_HAS_11N) {
606 		ic->ic_rxstream = sc->nrxchains;
607 		ic->ic_txstream = sc->ntxchains;
608 
609 		/*
610 		 * Some of the 3 antenna devices (ie, the 4965) only supports
611 		 * 2x2 operation.  So correct the number of streams if
612 		 * it's not a 3-stream device.
613 		 */
614 		if (! iwn_is_3stream_device(sc)) {
615 			if (ic->ic_rxstream > 2)
616 				ic->ic_rxstream = 2;
617 			if (ic->ic_txstream > 2)
618 				ic->ic_txstream = 2;
619 		}
620 
621 		ic->ic_htcaps =
622 			  IEEE80211_HTCAP_SMPS_OFF	/* SMPS mode disabled */
623 			| IEEE80211_HTCAP_SHORTGI20	/* short GI in 20MHz */
624 			| IEEE80211_HTCAP_CHWIDTH40	/* 40MHz channel width*/
625 			| IEEE80211_HTCAP_SHORTGI40	/* short GI in 40MHz */
626 #ifdef notyet
627 			| IEEE80211_HTCAP_GREENFIELD
628 #if IWN_RBUF_SIZE == 8192
629 			| IEEE80211_HTCAP_MAXAMSDU_7935	/* max A-MSDU length */
630 #else
631 			| IEEE80211_HTCAP_MAXAMSDU_3839	/* max A-MSDU length */
632 #endif
633 #endif
634 			/* s/w capabilities */
635 			| IEEE80211_HTC_HT		/* HT operation */
636 			| IEEE80211_HTC_AMPDU		/* tx A-MPDU */
637 #ifdef notyet
638 			| IEEE80211_HTC_AMSDU		/* tx A-MSDU */
639 #endif
640 			;
641 	}
642 
643 	if_initname(ifp, device_get_name(dev), device_get_unit(dev));
644 	ifp->if_softc = sc;
645 	ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST;
646 	ifp->if_init = iwn_init;
647 	ifp->if_ioctl = iwn_ioctl;
648 	ifp->if_start = iwn_start;
649 	IFQ_SET_MAXLEN(&ifp->if_snd, ifqmaxlen);
650 	ifp->if_snd.ifq_drv_maxlen = ifqmaxlen;
651 	IFQ_SET_READY(&ifp->if_snd);
652 
653 	ieee80211_ifattach(ic, macaddr);
654 	ic->ic_vap_create = iwn_vap_create;
655 	ic->ic_vap_delete = iwn_vap_delete;
656 	ic->ic_raw_xmit = iwn_raw_xmit;
657 	ic->ic_node_alloc = iwn_node_alloc;
658 	sc->sc_ampdu_rx_start = ic->ic_ampdu_rx_start;
659 	ic->ic_ampdu_rx_start = iwn_ampdu_rx_start;
660 	sc->sc_ampdu_rx_stop = ic->ic_ampdu_rx_stop;
661 	ic->ic_ampdu_rx_stop = iwn_ampdu_rx_stop;
662 	sc->sc_addba_request = ic->ic_addba_request;
663 	ic->ic_addba_request = iwn_addba_request;
664 	sc->sc_addba_response = ic->ic_addba_response;
665 	ic->ic_addba_response = iwn_addba_response;
666 	sc->sc_addba_stop = ic->ic_addba_stop;
667 	ic->ic_addba_stop = iwn_ampdu_tx_stop;
668 	ic->ic_newassoc = iwn_newassoc;
669 	ic->ic_wme.wme_update = iwn_updateedca;
670 	ic->ic_update_mcast = iwn_update_mcast;
671 	ic->ic_scan_start = iwn_scan_start;
672 	ic->ic_scan_end = iwn_scan_end;
673 	ic->ic_set_channel = iwn_set_channel;
674 	ic->ic_scan_curchan = iwn_scan_curchan;
675 	ic->ic_scan_mindwell = iwn_scan_mindwell;
676 	ic->ic_setregdomain = iwn_setregdomain;
677 
678 	iwn_radiotap_attach(sc);
679 
680 	callout_init_mtx(&sc->calib_to, &sc->sc_mtx, 0);
681 	callout_init_mtx(&sc->watchdog_to, &sc->sc_mtx, 0);
682 	TASK_INIT(&sc->sc_reinit_task, 0, iwn_hw_reset, sc);
683 	TASK_INIT(&sc->sc_radioon_task, 0, iwn_radio_on, sc);
684 	TASK_INIT(&sc->sc_radiooff_task, 0, iwn_radio_off, sc);
685 	TASK_INIT(&sc->sc_panic_task, 0, iwn_panicked, sc);
686 	TASK_INIT(&sc->sc_xmit_task, 0, iwn_xmit_task, sc);
687 
688 	mbufq_init(&sc->sc_xmit_queue, 1024);
689 
690 	sc->sc_tq = taskqueue_create("iwn_taskq", M_WAITOK,
691 	    taskqueue_thread_enqueue, &sc->sc_tq);
692 	error = taskqueue_start_threads(&sc->sc_tq, 1, 0, "iwn_taskq");
693 	if (error != 0) {
694 		device_printf(dev, "can't start threads, error %d\n", error);
695 		goto fail;
696 	}
697 
698 	iwn_sysctlattach(sc);
699 
700 	/*
701 	 * Hook our interrupt after all initialization is complete.
702 	 */
703 	error = bus_setup_intr(dev, sc->irq, INTR_TYPE_NET | INTR_MPSAFE,
704 	    NULL, iwn_intr, sc, &sc->sc_ih);
705 	if (error != 0) {
706 		device_printf(dev, "can't establish interrupt, error %d\n",
707 		    error);
708 		goto fail;
709 	}
710 
711 #if 0
712 	device_printf(sc->sc_dev, "%s: rx_stats=%d, rx_stats_bt=%d\n",
713 	    __func__,
714 	    sizeof(struct iwn_stats),
715 	    sizeof(struct iwn_stats_bt));
716 #endif
717 
718 	if (bootverbose)
719 		ieee80211_announce(ic);
720 	DPRINTF(sc, IWN_DEBUG_TRACE, "->%s: end\n",__func__);
721 	return 0;
722 fail:
723 	iwn_detach(dev);
724 	DPRINTF(sc, IWN_DEBUG_TRACE, "->%s: end in error\n",__func__);
725 	return error;
726 }
727 
728 /*
729  * Define specific configuration based on device id and subdevice id
730  * pid : PCI device id
731  */
732 static int
733 iwn_config_specific(struct iwn_softc *sc, uint16_t pid)
734 {
735 
736 	switch (pid) {
737 /* 4965 series */
738 	case IWN_DID_4965_1:
739 	case IWN_DID_4965_2:
740 	case IWN_DID_4965_3:
741 	case IWN_DID_4965_4:
742 		sc->base_params = &iwn4965_base_params;
743 		sc->limits = &iwn4965_sensitivity_limits;
744 		sc->fwname = "iwn4965fw";
745 		/* Override chains masks, ROM is known to be broken. */
746 		sc->txchainmask = IWN_ANT_AB;
747 		sc->rxchainmask = IWN_ANT_ABC;
748 		/* Enable normal btcoex */
749 		sc->sc_flags |= IWN_FLAG_BTCOEX;
750 		break;
751 /* 1000 Series */
752 	case IWN_DID_1000_1:
753 	case IWN_DID_1000_2:
754 		switch(sc->subdevice_id) {
755 			case	IWN_SDID_1000_1:
756 			case	IWN_SDID_1000_2:
757 			case	IWN_SDID_1000_3:
758 			case	IWN_SDID_1000_4:
759 			case	IWN_SDID_1000_5:
760 			case	IWN_SDID_1000_6:
761 			case	IWN_SDID_1000_7:
762 			case	IWN_SDID_1000_8:
763 			case	IWN_SDID_1000_9:
764 			case	IWN_SDID_1000_10:
765 			case	IWN_SDID_1000_11:
766 			case	IWN_SDID_1000_12:
767 				sc->limits = &iwn1000_sensitivity_limits;
768 				sc->base_params = &iwn1000_base_params;
769 				sc->fwname = "iwn1000fw";
770 				break;
771 			default:
772 				device_printf(sc->sc_dev, "adapter type id : 0x%04x sub id :"
773 				    "0x%04x rev %d not supported (subdevice)\n", pid,
774 				    sc->subdevice_id,sc->hw_type);
775 				return ENOTSUP;
776 		}
777 		break;
778 /* 6x00 Series */
779 	case IWN_DID_6x00_2:
780 	case IWN_DID_6x00_4:
781 	case IWN_DID_6x00_1:
782 	case IWN_DID_6x00_3:
783 		sc->fwname = "iwn6000fw";
784 		sc->limits = &iwn6000_sensitivity_limits;
785 		switch(sc->subdevice_id) {
786 			case IWN_SDID_6x00_1:
787 			case IWN_SDID_6x00_2:
788 			case IWN_SDID_6x00_8:
789 				//iwl6000_3agn_cfg
790 				sc->base_params = &iwn_6000_base_params;
791 				break;
792 			case IWN_SDID_6x00_3:
793 			case IWN_SDID_6x00_6:
794 			case IWN_SDID_6x00_9:
795 				////iwl6000i_2agn
796 			case IWN_SDID_6x00_4:
797 			case IWN_SDID_6x00_7:
798 			case IWN_SDID_6x00_10:
799 				//iwl6000i_2abg_cfg
800 			case IWN_SDID_6x00_5:
801 				//iwl6000i_2bg_cfg
802 				sc->base_params = &iwn_6000i_base_params;
803 				sc->sc_flags |= IWN_FLAG_INTERNAL_PA;
804 				sc->txchainmask = IWN_ANT_BC;
805 				sc->rxchainmask = IWN_ANT_BC;
806 				break;
807 			default:
808 				device_printf(sc->sc_dev, "adapter type id : 0x%04x sub id :"
809 				    "0x%04x rev %d not supported (subdevice)\n", pid,
810 				    sc->subdevice_id,sc->hw_type);
811 				return ENOTSUP;
812 		}
813 		break;
814 /* 6x05 Series */
815 	case IWN_DID_6x05_1:
816 	case IWN_DID_6x05_2:
817 		switch(sc->subdevice_id) {
818 			case IWN_SDID_6x05_1:
819 			case IWN_SDID_6x05_4:
820 			case IWN_SDID_6x05_6:
821 				//iwl6005_2agn_cfg
822 			case IWN_SDID_6x05_2:
823 			case IWN_SDID_6x05_5:
824 			case IWN_SDID_6x05_7:
825 				//iwl6005_2abg_cfg
826 			case IWN_SDID_6x05_3:
827 				//iwl6005_2bg_cfg
828 			case IWN_SDID_6x05_8:
829 			case IWN_SDID_6x05_9:
830 				//iwl6005_2agn_sff_cfg
831 			case IWN_SDID_6x05_10:
832 				//iwl6005_2agn_d_cfg
833 			case IWN_SDID_6x05_11:
834 				//iwl6005_2agn_mow1_cfg
835 			case IWN_SDID_6x05_12:
836 				//iwl6005_2agn_mow2_cfg
837 				sc->fwname = "iwn6000g2afw";
838 				sc->limits = &iwn6000_sensitivity_limits;
839 				sc->base_params = &iwn_6000g2_base_params;
840 				break;
841 			default:
842 				device_printf(sc->sc_dev, "adapter type id : 0x%04x sub id :"
843 				    "0x%04x rev %d not supported (subdevice)\n", pid,
844 				    sc->subdevice_id,sc->hw_type);
845 				return ENOTSUP;
846 		}
847 		break;
848 /* 6x35 Series */
849 	case IWN_DID_6035_1:
850 	case IWN_DID_6035_2:
851 		switch(sc->subdevice_id) {
852 			case IWN_SDID_6035_1:
853 			case IWN_SDID_6035_2:
854 			case IWN_SDID_6035_3:
855 			case IWN_SDID_6035_4:
856 				sc->fwname = "iwn6000g2bfw";
857 				sc->limits = &iwn6235_sensitivity_limits;
858 				sc->base_params = &iwn_6235_base_params;
859 				break;
860 			default:
861 				device_printf(sc->sc_dev, "adapter type id : 0x%04x sub id :"
862 				    "0x%04x rev %d not supported (subdevice)\n", pid,
863 				    sc->subdevice_id,sc->hw_type);
864 				return ENOTSUP;
865 		}
866 		break;
867 /* 6x50 WiFi/WiMax Series */
868 	case IWN_DID_6050_1:
869 	case IWN_DID_6050_2:
870 		switch(sc->subdevice_id) {
871 			case IWN_SDID_6050_1:
872 			case IWN_SDID_6050_3:
873 			case IWN_SDID_6050_5:
874 				//iwl6050_2agn_cfg
875 			case IWN_SDID_6050_2:
876 			case IWN_SDID_6050_4:
877 			case IWN_SDID_6050_6:
878 				//iwl6050_2abg_cfg
879 				sc->fwname = "iwn6050fw";
880 				sc->txchainmask = IWN_ANT_AB;
881 				sc->rxchainmask = IWN_ANT_AB;
882 				sc->limits = &iwn6000_sensitivity_limits;
883 				sc->base_params = &iwn_6050_base_params;
884 				break;
885 			default:
886 				device_printf(sc->sc_dev, "adapter type id : 0x%04x sub id :"
887 				    "0x%04x rev %d not supported (subdevice)\n", pid,
888 				    sc->subdevice_id,sc->hw_type);
889 				return ENOTSUP;
890 		}
891 		break;
892 /* 6150 WiFi/WiMax Series */
893 	case IWN_DID_6150_1:
894 	case IWN_DID_6150_2:
895 		switch(sc->subdevice_id) {
896 			case IWN_SDID_6150_1:
897 			case IWN_SDID_6150_3:
898 			case IWN_SDID_6150_5:
899 				// iwl6150_bgn_cfg
900 			case IWN_SDID_6150_2:
901 			case IWN_SDID_6150_4:
902 			case IWN_SDID_6150_6:
903 				//iwl6150_bg_cfg
904 				sc->fwname = "iwn6050fw";
905 				sc->limits = &iwn6000_sensitivity_limits;
906 				sc->base_params = &iwn_6150_base_params;
907 				break;
908 			default:
909 				device_printf(sc->sc_dev, "adapter type id : 0x%04x sub id :"
910 				    "0x%04x rev %d not supported (subdevice)\n", pid,
911 				    sc->subdevice_id,sc->hw_type);
912 				return ENOTSUP;
913 		}
914 		break;
915 /* 6030 Series and 1030 Series */
916 	case IWN_DID_x030_1:
917 	case IWN_DID_x030_2:
918 	case IWN_DID_x030_3:
919 	case IWN_DID_x030_4:
920 		switch(sc->subdevice_id) {
921 			case IWN_SDID_x030_1:
922 			case IWN_SDID_x030_3:
923 			case IWN_SDID_x030_5:
924 			// iwl1030_bgn_cfg
925 			case IWN_SDID_x030_2:
926 			case IWN_SDID_x030_4:
927 			case IWN_SDID_x030_6:
928 			//iwl1030_bg_cfg
929 			case IWN_SDID_x030_7:
930 			case IWN_SDID_x030_10:
931 			case IWN_SDID_x030_14:
932 			//iwl6030_2agn_cfg
933 			case IWN_SDID_x030_8:
934 			case IWN_SDID_x030_11:
935 			case IWN_SDID_x030_15:
936 			// iwl6030_2bgn_cfg
937 			case IWN_SDID_x030_9:
938 			case IWN_SDID_x030_12:
939 			case IWN_SDID_x030_16:
940 			// iwl6030_2abg_cfg
941 			case IWN_SDID_x030_13:
942 			//iwl6030_2bg_cfg
943 				sc->fwname = "iwn6000g2bfw";
944 				sc->limits = &iwn6000_sensitivity_limits;
945 				sc->base_params = &iwn_6000g2b_base_params;
946 				break;
947 			default:
948 				device_printf(sc->sc_dev, "adapter type id : 0x%04x sub id :"
949 				    "0x%04x rev %d not supported (subdevice)\n", pid,
950 				    sc->subdevice_id,sc->hw_type);
951 				return ENOTSUP;
952 		}
953 		break;
954 /* 130 Series WiFi */
955 /* XXX: This series will need adjustment for rate.
956  * see rx_with_siso_diversity in linux kernel
957  */
958 	case IWN_DID_130_1:
959 	case IWN_DID_130_2:
960 		switch(sc->subdevice_id) {
961 			case IWN_SDID_130_1:
962 			case IWN_SDID_130_3:
963 			case IWN_SDID_130_5:
964 			//iwl130_bgn_cfg
965 			case IWN_SDID_130_2:
966 			case IWN_SDID_130_4:
967 			case IWN_SDID_130_6:
968 			//iwl130_bg_cfg
969 				sc->fwname = "iwn6000g2bfw";
970 				sc->limits = &iwn6000_sensitivity_limits;
971 				sc->base_params = &iwn_6000g2b_base_params;
972 				break;
973 			default:
974 				device_printf(sc->sc_dev, "adapter type id : 0x%04x sub id :"
975 				    "0x%04x rev %d not supported (subdevice)\n", pid,
976 				    sc->subdevice_id,sc->hw_type);
977 				return ENOTSUP;
978 		}
979 		break;
980 /* 100 Series WiFi */
981 	case IWN_DID_100_1:
982 	case IWN_DID_100_2:
983 		switch(sc->subdevice_id) {
984 			case IWN_SDID_100_1:
985 			case IWN_SDID_100_2:
986 			case IWN_SDID_100_3:
987 			case IWN_SDID_100_4:
988 			case IWN_SDID_100_5:
989 			case IWN_SDID_100_6:
990 				sc->limits = &iwn1000_sensitivity_limits;
991 				sc->base_params = &iwn1000_base_params;
992 				sc->fwname = "iwn100fw";
993 				break;
994 			default:
995 				device_printf(sc->sc_dev, "adapter type id : 0x%04x sub id :"
996 				    "0x%04x rev %d not supported (subdevice)\n", pid,
997 				    sc->subdevice_id,sc->hw_type);
998 				return ENOTSUP;
999 		}
1000 		break;
1001 
1002 /* 105 Series */
1003 /* XXX: This series will need adjustment for rate.
1004  * see rx_with_siso_diversity in linux kernel
1005  */
1006 	case IWN_DID_105_1:
1007 	case IWN_DID_105_2:
1008 		switch(sc->subdevice_id) {
1009 			case IWN_SDID_105_1:
1010 			case IWN_SDID_105_2:
1011 			case IWN_SDID_105_3:
1012 			//iwl105_bgn_cfg
1013 			case IWN_SDID_105_4:
1014 			//iwl105_bgn_d_cfg
1015 				sc->limits = &iwn2030_sensitivity_limits;
1016 				sc->base_params = &iwn2000_base_params;
1017 				sc->fwname = "iwn105fw";
1018 				break;
1019 			default:
1020 				device_printf(sc->sc_dev, "adapter type id : 0x%04x sub id :"
1021 				    "0x%04x rev %d not supported (subdevice)\n", pid,
1022 				    sc->subdevice_id,sc->hw_type);
1023 				return ENOTSUP;
1024 		}
1025 		break;
1026 
1027 /* 135 Series */
1028 /* XXX: This series will need adjustment for rate.
1029  * see rx_with_siso_diversity in linux kernel
1030  */
1031 	case IWN_DID_135_1:
1032 	case IWN_DID_135_2:
1033 		switch(sc->subdevice_id) {
1034 			case IWN_SDID_135_1:
1035 			case IWN_SDID_135_2:
1036 			case IWN_SDID_135_3:
1037 				sc->limits = &iwn2030_sensitivity_limits;
1038 				sc->base_params = &iwn2030_base_params;
1039 				sc->fwname = "iwn135fw";
1040 				break;
1041 			default:
1042 				device_printf(sc->sc_dev, "adapter type id : 0x%04x sub id :"
1043 				    "0x%04x rev %d not supported (subdevice)\n", pid,
1044 				    sc->subdevice_id,sc->hw_type);
1045 				return ENOTSUP;
1046 		}
1047 		break;
1048 
1049 /* 2x00 Series */
1050 	case IWN_DID_2x00_1:
1051 	case IWN_DID_2x00_2:
1052 		switch(sc->subdevice_id) {
1053 			case IWN_SDID_2x00_1:
1054 			case IWN_SDID_2x00_2:
1055 			case IWN_SDID_2x00_3:
1056 			//iwl2000_2bgn_cfg
1057 			case IWN_SDID_2x00_4:
1058 			//iwl2000_2bgn_d_cfg
1059 				sc->limits = &iwn2030_sensitivity_limits;
1060 				sc->base_params = &iwn2000_base_params;
1061 				sc->fwname = "iwn2000fw";
1062 				break;
1063 			default:
1064 				device_printf(sc->sc_dev, "adapter type id : 0x%04x sub id :"
1065 				    "0x%04x rev %d not supported (subdevice) \n",
1066 				    pid, sc->subdevice_id, sc->hw_type);
1067 				return ENOTSUP;
1068 		}
1069 		break;
1070 /* 2x30 Series */
1071 	case IWN_DID_2x30_1:
1072 	case IWN_DID_2x30_2:
1073 		switch(sc->subdevice_id) {
1074 			case IWN_SDID_2x30_1:
1075 			case IWN_SDID_2x30_3:
1076 			case IWN_SDID_2x30_5:
1077 			//iwl100_bgn_cfg
1078 			case IWN_SDID_2x30_2:
1079 			case IWN_SDID_2x30_4:
1080 			case IWN_SDID_2x30_6:
1081 			//iwl100_bg_cfg
1082 				sc->limits = &iwn2030_sensitivity_limits;
1083 				sc->base_params = &iwn2030_base_params;
1084 				sc->fwname = "iwn2030fw";
1085 				break;
1086 			default:
1087 				device_printf(sc->sc_dev, "adapter type id : 0x%04x sub id :"
1088 				    "0x%04x rev %d not supported (subdevice)\n", pid,
1089 				    sc->subdevice_id,sc->hw_type);
1090 				return ENOTSUP;
1091 		}
1092 		break;
1093 /* 5x00 Series */
1094 	case IWN_DID_5x00_1:
1095 	case IWN_DID_5x00_2:
1096 	case IWN_DID_5x00_3:
1097 	case IWN_DID_5x00_4:
1098 		sc->limits = &iwn5000_sensitivity_limits;
1099 		sc->base_params = &iwn5000_base_params;
1100 		sc->fwname = "iwn5000fw";
1101 		switch(sc->subdevice_id) {
1102 			case IWN_SDID_5x00_1:
1103 			case IWN_SDID_5x00_2:
1104 			case IWN_SDID_5x00_3:
1105 			case IWN_SDID_5x00_4:
1106 			case IWN_SDID_5x00_9:
1107 			case IWN_SDID_5x00_10:
1108 			case IWN_SDID_5x00_11:
1109 			case IWN_SDID_5x00_12:
1110 			case IWN_SDID_5x00_17:
1111 			case IWN_SDID_5x00_18:
1112 			case IWN_SDID_5x00_19:
1113 			case IWN_SDID_5x00_20:
1114 			//iwl5100_agn_cfg
1115 				sc->txchainmask = IWN_ANT_B;
1116 				sc->rxchainmask = IWN_ANT_AB;
1117 				break;
1118 			case IWN_SDID_5x00_5:
1119 			case IWN_SDID_5x00_6:
1120 			case IWN_SDID_5x00_13:
1121 			case IWN_SDID_5x00_14:
1122 			case IWN_SDID_5x00_21:
1123 			case IWN_SDID_5x00_22:
1124 			//iwl5100_bgn_cfg
1125 				sc->txchainmask = IWN_ANT_B;
1126 				sc->rxchainmask = IWN_ANT_AB;
1127 				break;
1128 			case IWN_SDID_5x00_7:
1129 			case IWN_SDID_5x00_8:
1130 			case IWN_SDID_5x00_15:
1131 			case IWN_SDID_5x00_16:
1132 			case IWN_SDID_5x00_23:
1133 			case IWN_SDID_5x00_24:
1134 			//iwl5100_abg_cfg
1135 				sc->txchainmask = IWN_ANT_B;
1136 				sc->rxchainmask = IWN_ANT_AB;
1137 				break;
1138 			case IWN_SDID_5x00_25:
1139 			case IWN_SDID_5x00_26:
1140 			case IWN_SDID_5x00_27:
1141 			case IWN_SDID_5x00_28:
1142 			case IWN_SDID_5x00_29:
1143 			case IWN_SDID_5x00_30:
1144 			case IWN_SDID_5x00_31:
1145 			case IWN_SDID_5x00_32:
1146 			case IWN_SDID_5x00_33:
1147 			case IWN_SDID_5x00_34:
1148 			case IWN_SDID_5x00_35:
1149 			case IWN_SDID_5x00_36:
1150 			//iwl5300_agn_cfg
1151 				sc->txchainmask = IWN_ANT_ABC;
1152 				sc->rxchainmask = IWN_ANT_ABC;
1153 				break;
1154 			default:
1155 				device_printf(sc->sc_dev, "adapter type id : 0x%04x sub id :"
1156 				    "0x%04x rev %d not supported (subdevice)\n", pid,
1157 				    sc->subdevice_id,sc->hw_type);
1158 				return ENOTSUP;
1159 		}
1160 		break;
1161 /* 5x50 Series */
1162 	case IWN_DID_5x50_1:
1163 	case IWN_DID_5x50_2:
1164 	case IWN_DID_5x50_3:
1165 	case IWN_DID_5x50_4:
1166 		sc->limits = &iwn5000_sensitivity_limits;
1167 		sc->base_params = &iwn5000_base_params;
1168 		sc->fwname = "iwn5000fw";
1169 		switch(sc->subdevice_id) {
1170 			case IWN_SDID_5x50_1:
1171 			case IWN_SDID_5x50_2:
1172 			case IWN_SDID_5x50_3:
1173 			//iwl5350_agn_cfg
1174 				sc->limits = &iwn5000_sensitivity_limits;
1175 				sc->base_params = &iwn5000_base_params;
1176 				sc->fwname = "iwn5000fw";
1177 				break;
1178 			case IWN_SDID_5x50_4:
1179 			case IWN_SDID_5x50_5:
1180 			case IWN_SDID_5x50_8:
1181 			case IWN_SDID_5x50_9:
1182 			case IWN_SDID_5x50_10:
1183 			case IWN_SDID_5x50_11:
1184 			//iwl5150_agn_cfg
1185 			case IWN_SDID_5x50_6:
1186 			case IWN_SDID_5x50_7:
1187 			case IWN_SDID_5x50_12:
1188 			case IWN_SDID_5x50_13:
1189 			//iwl5150_abg_cfg
1190 				sc->limits = &iwn5000_sensitivity_limits;
1191 				sc->fwname = "iwn5150fw";
1192 				sc->base_params = &iwn_5x50_base_params;
1193 				break;
1194 			default:
1195 				device_printf(sc->sc_dev, "adapter type id : 0x%04x sub id :"
1196 				    "0x%04x rev %d not supported (subdevice)\n", pid,
1197 				    sc->subdevice_id,sc->hw_type);
1198 				return ENOTSUP;
1199 		}
1200 		break;
1201 	default:
1202 		device_printf(sc->sc_dev, "adapter type id : 0x%04x sub id : 0x%04x"
1203 		    "rev 0x%08x not supported (device)\n", pid, sc->subdevice_id,
1204 		     sc->hw_type);
1205 		return ENOTSUP;
1206 	}
1207 	return 0;
1208 }
1209 
1210 static int
1211 iwn4965_attach(struct iwn_softc *sc, uint16_t pid)
1212 {
1213 	struct iwn_ops *ops = &sc->ops;
1214 
1215 	DPRINTF(sc, IWN_DEBUG_TRACE, "->%s begin\n", __func__);
1216 	ops->load_firmware = iwn4965_load_firmware;
1217 	ops->read_eeprom = iwn4965_read_eeprom;
1218 	ops->post_alive = iwn4965_post_alive;
1219 	ops->nic_config = iwn4965_nic_config;
1220 	ops->update_sched = iwn4965_update_sched;
1221 	ops->get_temperature = iwn4965_get_temperature;
1222 	ops->get_rssi = iwn4965_get_rssi;
1223 	ops->set_txpower = iwn4965_set_txpower;
1224 	ops->init_gains = iwn4965_init_gains;
1225 	ops->set_gains = iwn4965_set_gains;
1226 	ops->add_node = iwn4965_add_node;
1227 	ops->tx_done = iwn4965_tx_done;
1228 	ops->ampdu_tx_start = iwn4965_ampdu_tx_start;
1229 	ops->ampdu_tx_stop = iwn4965_ampdu_tx_stop;
1230 	sc->ntxqs = IWN4965_NTXQUEUES;
1231 	sc->firstaggqueue = IWN4965_FIRSTAGGQUEUE;
1232 	sc->ndmachnls = IWN4965_NDMACHNLS;
1233 	sc->broadcast_id = IWN4965_ID_BROADCAST;
1234 	sc->rxonsz = IWN4965_RXONSZ;
1235 	sc->schedsz = IWN4965_SCHEDSZ;
1236 	sc->fw_text_maxsz = IWN4965_FW_TEXT_MAXSZ;
1237 	sc->fw_data_maxsz = IWN4965_FW_DATA_MAXSZ;
1238 	sc->fwsz = IWN4965_FWSZ;
1239 	sc->sched_txfact_addr = IWN4965_SCHED_TXFACT;
1240 	sc->limits = &iwn4965_sensitivity_limits;
1241 	sc->fwname = "iwn4965fw";
1242 	/* Override chains masks, ROM is known to be broken. */
1243 	sc->txchainmask = IWN_ANT_AB;
1244 	sc->rxchainmask = IWN_ANT_ABC;
1245 	/* Enable normal btcoex */
1246 	sc->sc_flags |= IWN_FLAG_BTCOEX;
1247 
1248 	DPRINTF(sc, IWN_DEBUG_TRACE, "%s: end\n",__func__);
1249 
1250 	return 0;
1251 }
1252 
1253 static int
1254 iwn5000_attach(struct iwn_softc *sc, uint16_t pid)
1255 {
1256 	struct iwn_ops *ops = &sc->ops;
1257 
1258 	DPRINTF(sc, IWN_DEBUG_TRACE, "->%s begin\n", __func__);
1259 
1260 	ops->load_firmware = iwn5000_load_firmware;
1261 	ops->read_eeprom = iwn5000_read_eeprom;
1262 	ops->post_alive = iwn5000_post_alive;
1263 	ops->nic_config = iwn5000_nic_config;
1264 	ops->update_sched = iwn5000_update_sched;
1265 	ops->get_temperature = iwn5000_get_temperature;
1266 	ops->get_rssi = iwn5000_get_rssi;
1267 	ops->set_txpower = iwn5000_set_txpower;
1268 	ops->init_gains = iwn5000_init_gains;
1269 	ops->set_gains = iwn5000_set_gains;
1270 	ops->add_node = iwn5000_add_node;
1271 	ops->tx_done = iwn5000_tx_done;
1272 	ops->ampdu_tx_start = iwn5000_ampdu_tx_start;
1273 	ops->ampdu_tx_stop = iwn5000_ampdu_tx_stop;
1274 	sc->ntxqs = IWN5000_NTXQUEUES;
1275 	sc->firstaggqueue = IWN5000_FIRSTAGGQUEUE;
1276 	sc->ndmachnls = IWN5000_NDMACHNLS;
1277 	sc->broadcast_id = IWN5000_ID_BROADCAST;
1278 	sc->rxonsz = IWN5000_RXONSZ;
1279 	sc->schedsz = IWN5000_SCHEDSZ;
1280 	sc->fw_text_maxsz = IWN5000_FW_TEXT_MAXSZ;
1281 	sc->fw_data_maxsz = IWN5000_FW_DATA_MAXSZ;
1282 	sc->fwsz = IWN5000_FWSZ;
1283 	sc->sched_txfact_addr = IWN5000_SCHED_TXFACT;
1284 	sc->reset_noise_gain = IWN5000_PHY_CALIB_RESET_NOISE_GAIN;
1285 	sc->noise_gain = IWN5000_PHY_CALIB_NOISE_GAIN;
1286 
1287 	return 0;
1288 }
1289 
1290 /*
1291  * Attach the interface to 802.11 radiotap.
1292  */
1293 static void
1294 iwn_radiotap_attach(struct iwn_softc *sc)
1295 {
1296 	struct ifnet *ifp = sc->sc_ifp;
1297 	struct ieee80211com *ic = ifp->if_l2com;
1298 	DPRINTF(sc, IWN_DEBUG_TRACE, "->%s begin\n", __func__);
1299 	ieee80211_radiotap_attach(ic,
1300 	    &sc->sc_txtap.wt_ihdr, sizeof(sc->sc_txtap),
1301 		IWN_TX_RADIOTAP_PRESENT,
1302 	    &sc->sc_rxtap.wr_ihdr, sizeof(sc->sc_rxtap),
1303 		IWN_RX_RADIOTAP_PRESENT);
1304 	DPRINTF(sc, IWN_DEBUG_TRACE, "->%s end\n", __func__);
1305 }
1306 
1307 static void
1308 iwn_sysctlattach(struct iwn_softc *sc)
1309 {
1310 #ifdef	IWN_DEBUG
1311 	struct sysctl_ctx_list *ctx = device_get_sysctl_ctx(sc->sc_dev);
1312 	struct sysctl_oid *tree = device_get_sysctl_tree(sc->sc_dev);
1313 
1314 	SYSCTL_ADD_INT(ctx, SYSCTL_CHILDREN(tree), OID_AUTO,
1315 	    "debug", CTLFLAG_RW, &sc->sc_debug, sc->sc_debug,
1316 		"control debugging printfs");
1317 #endif
1318 }
1319 
1320 static struct ieee80211vap *
1321 iwn_vap_create(struct ieee80211com *ic, const char name[IFNAMSIZ], int unit,
1322     enum ieee80211_opmode opmode, int flags,
1323     const uint8_t bssid[IEEE80211_ADDR_LEN],
1324     const uint8_t mac[IEEE80211_ADDR_LEN])
1325 {
1326 	struct iwn_softc *sc = ic->ic_softc;
1327 	struct iwn_vap *ivp;
1328 	struct ieee80211vap *vap;
1329 	uint8_t mac1[IEEE80211_ADDR_LEN];
1330 
1331 	if (!TAILQ_EMPTY(&ic->ic_vaps))		/* only one at a time */
1332 		return NULL;
1333 
1334 	IEEE80211_ADDR_COPY(mac1, mac);
1335 
1336 	ivp = (struct iwn_vap *) malloc(sizeof(struct iwn_vap),
1337 	    M_80211_VAP, M_NOWAIT | M_ZERO);
1338 	if (ivp == NULL)
1339 		return NULL;
1340 	vap = &ivp->iv_vap;
1341 	ieee80211_vap_setup(ic, vap, name, unit, opmode, flags, bssid, mac1);
1342 	ivp->ctx = IWN_RXON_BSS_CTX;
1343 	IEEE80211_ADDR_COPY(ivp->macaddr, mac1);
1344 	vap->iv_bmissthreshold = 10;		/* override default */
1345 	/* Override with driver methods. */
1346 	ivp->iv_newstate = vap->iv_newstate;
1347 	vap->iv_newstate = iwn_newstate;
1348 	sc->ivap[IWN_RXON_BSS_CTX] = vap;
1349 
1350 	ieee80211_ratectl_init(vap);
1351 	/* Complete setup. */
1352 	ieee80211_vap_attach(vap, iwn_media_change, ieee80211_media_status);
1353 	ic->ic_opmode = opmode;
1354 	return vap;
1355 }
1356 
1357 static void
1358 iwn_vap_delete(struct ieee80211vap *vap)
1359 {
1360 	struct iwn_vap *ivp = IWN_VAP(vap);
1361 
1362 	ieee80211_ratectl_deinit(vap);
1363 	ieee80211_vap_detach(vap);
1364 	free(ivp, M_80211_VAP);
1365 }
1366 
1367 static void
1368 iwn_xmit_queue_drain(struct iwn_softc *sc)
1369 {
1370 	struct mbuf *m;
1371 	struct ieee80211_node *ni;
1372 
1373 	IWN_LOCK_ASSERT(sc);
1374 	while ((m = mbufq_dequeue(&sc->sc_xmit_queue)) != NULL) {
1375 		ni = (struct ieee80211_node *)m->m_pkthdr.rcvif;
1376 		ieee80211_free_node(ni);
1377 		m_freem(m);
1378 	}
1379 }
1380 
1381 static int
1382 iwn_xmit_queue_enqueue(struct iwn_softc *sc, struct mbuf *m)
1383 {
1384 
1385 	IWN_LOCK_ASSERT(sc);
1386 	return (mbufq_enqueue(&sc->sc_xmit_queue, m));
1387 }
1388 
1389 static int
1390 iwn_detach(device_t dev)
1391 {
1392 	struct iwn_softc *sc = device_get_softc(dev);
1393 	struct ifnet *ifp = sc->sc_ifp;
1394 	struct ieee80211com *ic;
1395 	int qid;
1396 
1397 	DPRINTF(sc, IWN_DEBUG_TRACE, "->%s begin\n", __func__);
1398 
1399 	if (ifp != NULL) {
1400 		ic = ifp->if_l2com;
1401 
1402 		/* Free the mbuf queue and node references */
1403 		IWN_LOCK(sc);
1404 		iwn_xmit_queue_drain(sc);
1405 		IWN_UNLOCK(sc);
1406 
1407 		ieee80211_draintask(ic, &sc->sc_reinit_task);
1408 		ieee80211_draintask(ic, &sc->sc_radioon_task);
1409 		ieee80211_draintask(ic, &sc->sc_radiooff_task);
1410 
1411 		iwn_stop(sc);
1412 
1413 		taskqueue_drain_all(sc->sc_tq);
1414 		taskqueue_free(sc->sc_tq);
1415 
1416 		callout_drain(&sc->watchdog_to);
1417 		callout_drain(&sc->calib_to);
1418 		ieee80211_ifdetach(ic);
1419 	}
1420 
1421 	/* Uninstall interrupt handler. */
1422 	if (sc->irq != NULL) {
1423 		bus_teardown_intr(dev, sc->irq, sc->sc_ih);
1424 		bus_release_resource(dev, SYS_RES_IRQ, rman_get_rid(sc->irq),
1425 		    sc->irq);
1426 		pci_release_msi(dev);
1427 	}
1428 
1429 	/* Free DMA resources. */
1430 	iwn_free_rx_ring(sc, &sc->rxq);
1431 	for (qid = 0; qid < sc->ntxqs; qid++)
1432 		iwn_free_tx_ring(sc, &sc->txq[qid]);
1433 	iwn_free_sched(sc);
1434 	iwn_free_kw(sc);
1435 	if (sc->ict != NULL)
1436 		iwn_free_ict(sc);
1437 	iwn_free_fwmem(sc);
1438 
1439 	if (sc->mem != NULL)
1440 		bus_release_resource(dev, SYS_RES_MEMORY,
1441 		    rman_get_rid(sc->mem), sc->mem);
1442 
1443 	if (ifp != NULL)
1444 		if_free(ifp);
1445 
1446 	DPRINTF(sc, IWN_DEBUG_TRACE, "->%s: end\n", __func__);
1447 	IWN_LOCK_DESTROY(sc);
1448 	return 0;
1449 }
1450 
1451 static int
1452 iwn_shutdown(device_t dev)
1453 {
1454 	struct iwn_softc *sc = device_get_softc(dev);
1455 
1456 	iwn_stop(sc);
1457 	return 0;
1458 }
1459 
1460 static int
1461 iwn_suspend(device_t dev)
1462 {
1463 	struct iwn_softc *sc = device_get_softc(dev);
1464 	struct ieee80211com *ic = sc->sc_ifp->if_l2com;
1465 
1466 	ieee80211_suspend_all(ic);
1467 	return 0;
1468 }
1469 
1470 static int
1471 iwn_resume(device_t dev)
1472 {
1473 	struct iwn_softc *sc = device_get_softc(dev);
1474 	struct ieee80211com *ic = sc->sc_ifp->if_l2com;
1475 
1476 	/* Clear device-specific "PCI retry timeout" register (41h). */
1477 	pci_write_config(dev, 0x41, 0, 1);
1478 
1479 	ieee80211_resume_all(ic);
1480 	return 0;
1481 }
1482 
1483 static int
1484 iwn_nic_lock(struct iwn_softc *sc)
1485 {
1486 	int ntries;
1487 
1488 	/* Request exclusive access to NIC. */
1489 	IWN_SETBITS(sc, IWN_GP_CNTRL, IWN_GP_CNTRL_MAC_ACCESS_REQ);
1490 
1491 	/* Spin until we actually get the lock. */
1492 	for (ntries = 0; ntries < 1000; ntries++) {
1493 		if ((IWN_READ(sc, IWN_GP_CNTRL) &
1494 		     (IWN_GP_CNTRL_MAC_ACCESS_ENA | IWN_GP_CNTRL_SLEEP)) ==
1495 		    IWN_GP_CNTRL_MAC_ACCESS_ENA)
1496 			return 0;
1497 		DELAY(10);
1498 	}
1499 	return ETIMEDOUT;
1500 }
1501 
1502 static __inline void
1503 iwn_nic_unlock(struct iwn_softc *sc)
1504 {
1505 	IWN_CLRBITS(sc, IWN_GP_CNTRL, IWN_GP_CNTRL_MAC_ACCESS_REQ);
1506 }
1507 
1508 static __inline uint32_t
1509 iwn_prph_read(struct iwn_softc *sc, uint32_t addr)
1510 {
1511 	IWN_WRITE(sc, IWN_PRPH_RADDR, IWN_PRPH_DWORD | addr);
1512 	IWN_BARRIER_READ_WRITE(sc);
1513 	return IWN_READ(sc, IWN_PRPH_RDATA);
1514 }
1515 
1516 static __inline void
1517 iwn_prph_write(struct iwn_softc *sc, uint32_t addr, uint32_t data)
1518 {
1519 	IWN_WRITE(sc, IWN_PRPH_WADDR, IWN_PRPH_DWORD | addr);
1520 	IWN_BARRIER_WRITE(sc);
1521 	IWN_WRITE(sc, IWN_PRPH_WDATA, data);
1522 }
1523 
1524 static __inline void
1525 iwn_prph_setbits(struct iwn_softc *sc, uint32_t addr, uint32_t mask)
1526 {
1527 	iwn_prph_write(sc, addr, iwn_prph_read(sc, addr) | mask);
1528 }
1529 
1530 static __inline void
1531 iwn_prph_clrbits(struct iwn_softc *sc, uint32_t addr, uint32_t mask)
1532 {
1533 	iwn_prph_write(sc, addr, iwn_prph_read(sc, addr) & ~mask);
1534 }
1535 
1536 static __inline void
1537 iwn_prph_write_region_4(struct iwn_softc *sc, uint32_t addr,
1538     const uint32_t *data, int count)
1539 {
1540 	for (; count > 0; count--, data++, addr += 4)
1541 		iwn_prph_write(sc, addr, *data);
1542 }
1543 
1544 static __inline uint32_t
1545 iwn_mem_read(struct iwn_softc *sc, uint32_t addr)
1546 {
1547 	IWN_WRITE(sc, IWN_MEM_RADDR, addr);
1548 	IWN_BARRIER_READ_WRITE(sc);
1549 	return IWN_READ(sc, IWN_MEM_RDATA);
1550 }
1551 
1552 static __inline void
1553 iwn_mem_write(struct iwn_softc *sc, uint32_t addr, uint32_t data)
1554 {
1555 	IWN_WRITE(sc, IWN_MEM_WADDR, addr);
1556 	IWN_BARRIER_WRITE(sc);
1557 	IWN_WRITE(sc, IWN_MEM_WDATA, data);
1558 }
1559 
1560 static __inline void
1561 iwn_mem_write_2(struct iwn_softc *sc, uint32_t addr, uint16_t data)
1562 {
1563 	uint32_t tmp;
1564 
1565 	tmp = iwn_mem_read(sc, addr & ~3);
1566 	if (addr & 3)
1567 		tmp = (tmp & 0x0000ffff) | data << 16;
1568 	else
1569 		tmp = (tmp & 0xffff0000) | data;
1570 	iwn_mem_write(sc, addr & ~3, tmp);
1571 }
1572 
1573 static __inline void
1574 iwn_mem_read_region_4(struct iwn_softc *sc, uint32_t addr, uint32_t *data,
1575     int count)
1576 {
1577 	for (; count > 0; count--, addr += 4)
1578 		*data++ = iwn_mem_read(sc, addr);
1579 }
1580 
1581 static __inline void
1582 iwn_mem_set_region_4(struct iwn_softc *sc, uint32_t addr, uint32_t val,
1583     int count)
1584 {
1585 	for (; count > 0; count--, addr += 4)
1586 		iwn_mem_write(sc, addr, val);
1587 }
1588 
1589 static int
1590 iwn_eeprom_lock(struct iwn_softc *sc)
1591 {
1592 	int i, ntries;
1593 
1594 	for (i = 0; i < 100; i++) {
1595 		/* Request exclusive access to EEPROM. */
1596 		IWN_SETBITS(sc, IWN_HW_IF_CONFIG,
1597 		    IWN_HW_IF_CONFIG_EEPROM_LOCKED);
1598 
1599 		/* Spin until we actually get the lock. */
1600 		for (ntries = 0; ntries < 100; ntries++) {
1601 			if (IWN_READ(sc, IWN_HW_IF_CONFIG) &
1602 			    IWN_HW_IF_CONFIG_EEPROM_LOCKED)
1603 				return 0;
1604 			DELAY(10);
1605 		}
1606 	}
1607 	DPRINTF(sc, IWN_DEBUG_TRACE, "->%s end timeout\n", __func__);
1608 	return ETIMEDOUT;
1609 }
1610 
1611 static __inline void
1612 iwn_eeprom_unlock(struct iwn_softc *sc)
1613 {
1614 	IWN_CLRBITS(sc, IWN_HW_IF_CONFIG, IWN_HW_IF_CONFIG_EEPROM_LOCKED);
1615 }
1616 
1617 /*
1618  * Initialize access by host to One Time Programmable ROM.
1619  * NB: This kind of ROM can be found on 1000 or 6000 Series only.
1620  */
1621 static int
1622 iwn_init_otprom(struct iwn_softc *sc)
1623 {
1624 	uint16_t prev, base, next;
1625 	int count, error;
1626 
1627 	DPRINTF(sc, IWN_DEBUG_TRACE, "->%s begin\n", __func__);
1628 
1629 	/* Wait for clock stabilization before accessing prph. */
1630 	if ((error = iwn_clock_wait(sc)) != 0)
1631 		return error;
1632 
1633 	if ((error = iwn_nic_lock(sc)) != 0)
1634 		return error;
1635 	iwn_prph_setbits(sc, IWN_APMG_PS, IWN_APMG_PS_RESET_REQ);
1636 	DELAY(5);
1637 	iwn_prph_clrbits(sc, IWN_APMG_PS, IWN_APMG_PS_RESET_REQ);
1638 	iwn_nic_unlock(sc);
1639 
1640 	/* Set auto clock gate disable bit for HW with OTP shadow RAM. */
1641 	if (sc->base_params->shadow_ram_support) {
1642 		IWN_SETBITS(sc, IWN_DBG_LINK_PWR_MGMT,
1643 		    IWN_RESET_LINK_PWR_MGMT_DIS);
1644 	}
1645 	IWN_CLRBITS(sc, IWN_EEPROM_GP, IWN_EEPROM_GP_IF_OWNER);
1646 	/* Clear ECC status. */
1647 	IWN_SETBITS(sc, IWN_OTP_GP,
1648 	    IWN_OTP_GP_ECC_CORR_STTS | IWN_OTP_GP_ECC_UNCORR_STTS);
1649 
1650 	/*
1651 	 * Find the block before last block (contains the EEPROM image)
1652 	 * for HW without OTP shadow RAM.
1653 	 */
1654 	if (! sc->base_params->shadow_ram_support) {
1655 		/* Switch to absolute addressing mode. */
1656 		IWN_CLRBITS(sc, IWN_OTP_GP, IWN_OTP_GP_RELATIVE_ACCESS);
1657 		base = prev = 0;
1658 		for (count = 0; count < sc->base_params->max_ll_items;
1659 		    count++) {
1660 			error = iwn_read_prom_data(sc, base, &next, 2);
1661 			if (error != 0)
1662 				return error;
1663 			if (next == 0)	/* End of linked-list. */
1664 				break;
1665 			prev = base;
1666 			base = le16toh(next);
1667 		}
1668 		if (count == 0 || count == sc->base_params->max_ll_items)
1669 			return EIO;
1670 		/* Skip "next" word. */
1671 		sc->prom_base = prev + 1;
1672 	}
1673 
1674 	DPRINTF(sc, IWN_DEBUG_TRACE, "->%s end\n", __func__);
1675 
1676 	return 0;
1677 }
1678 
1679 static int
1680 iwn_read_prom_data(struct iwn_softc *sc, uint32_t addr, void *data, int count)
1681 {
1682 	uint8_t *out = data;
1683 	uint32_t val, tmp;
1684 	int ntries;
1685 
1686 	DPRINTF(sc, IWN_DEBUG_TRACE, "->%s begin\n", __func__);
1687 
1688 	addr += sc->prom_base;
1689 	for (; count > 0; count -= 2, addr++) {
1690 		IWN_WRITE(sc, IWN_EEPROM, addr << 2);
1691 		for (ntries = 0; ntries < 10; ntries++) {
1692 			val = IWN_READ(sc, IWN_EEPROM);
1693 			if (val & IWN_EEPROM_READ_VALID)
1694 				break;
1695 			DELAY(5);
1696 		}
1697 		if (ntries == 10) {
1698 			device_printf(sc->sc_dev,
1699 			    "timeout reading ROM at 0x%x\n", addr);
1700 			return ETIMEDOUT;
1701 		}
1702 		if (sc->sc_flags & IWN_FLAG_HAS_OTPROM) {
1703 			/* OTPROM, check for ECC errors. */
1704 			tmp = IWN_READ(sc, IWN_OTP_GP);
1705 			if (tmp & IWN_OTP_GP_ECC_UNCORR_STTS) {
1706 				device_printf(sc->sc_dev,
1707 				    "OTPROM ECC error at 0x%x\n", addr);
1708 				return EIO;
1709 			}
1710 			if (tmp & IWN_OTP_GP_ECC_CORR_STTS) {
1711 				/* Correctable ECC error, clear bit. */
1712 				IWN_SETBITS(sc, IWN_OTP_GP,
1713 				    IWN_OTP_GP_ECC_CORR_STTS);
1714 			}
1715 		}
1716 		*out++ = val >> 16;
1717 		if (count > 1)
1718 			*out++ = val >> 24;
1719 	}
1720 
1721 	DPRINTF(sc, IWN_DEBUG_TRACE, "->%s end\n", __func__);
1722 
1723 	return 0;
1724 }
1725 
1726 static void
1727 iwn_dma_map_addr(void *arg, bus_dma_segment_t *segs, int nsegs, int error)
1728 {
1729 	if (error != 0)
1730 		return;
1731 	KASSERT(nsegs == 1, ("too many DMA segments, %d should be 1", nsegs));
1732 	*(bus_addr_t *)arg = segs[0].ds_addr;
1733 }
1734 
1735 static int
1736 iwn_dma_contig_alloc(struct iwn_softc *sc, struct iwn_dma_info *dma,
1737     void **kvap, bus_size_t size, bus_size_t alignment)
1738 {
1739 	int error;
1740 
1741 	dma->tag = NULL;
1742 	dma->size = size;
1743 
1744 	error = bus_dma_tag_create(bus_get_dma_tag(sc->sc_dev), alignment,
1745 	    0, BUS_SPACE_MAXADDR_32BIT, BUS_SPACE_MAXADDR, NULL, NULL, size,
1746 	    1, size, BUS_DMA_NOWAIT, NULL, NULL, &dma->tag);
1747 	if (error != 0)
1748 		goto fail;
1749 
1750 	error = bus_dmamem_alloc(dma->tag, (void **)&dma->vaddr,
1751 	    BUS_DMA_NOWAIT | BUS_DMA_ZERO | BUS_DMA_COHERENT, &dma->map);
1752 	if (error != 0)
1753 		goto fail;
1754 
1755 	error = bus_dmamap_load(dma->tag, dma->map, dma->vaddr, size,
1756 	    iwn_dma_map_addr, &dma->paddr, BUS_DMA_NOWAIT);
1757 	if (error != 0)
1758 		goto fail;
1759 
1760 	bus_dmamap_sync(dma->tag, dma->map, BUS_DMASYNC_PREWRITE);
1761 
1762 	if (kvap != NULL)
1763 		*kvap = dma->vaddr;
1764 
1765 	return 0;
1766 
1767 fail:	iwn_dma_contig_free(dma);
1768 	return error;
1769 }
1770 
1771 static void
1772 iwn_dma_contig_free(struct iwn_dma_info *dma)
1773 {
1774 	if (dma->vaddr != NULL) {
1775 		bus_dmamap_sync(dma->tag, dma->map,
1776 		    BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE);
1777 		bus_dmamap_unload(dma->tag, dma->map);
1778 		bus_dmamem_free(dma->tag, dma->vaddr, dma->map);
1779 		dma->vaddr = NULL;
1780 	}
1781 	if (dma->tag != NULL) {
1782 		bus_dma_tag_destroy(dma->tag);
1783 		dma->tag = NULL;
1784 	}
1785 }
1786 
1787 static int
1788 iwn_alloc_sched(struct iwn_softc *sc)
1789 {
1790 	/* TX scheduler rings must be aligned on a 1KB boundary. */
1791 	return iwn_dma_contig_alloc(sc, &sc->sched_dma, (void **)&sc->sched,
1792 	    sc->schedsz, 1024);
1793 }
1794 
1795 static void
1796 iwn_free_sched(struct iwn_softc *sc)
1797 {
1798 	iwn_dma_contig_free(&sc->sched_dma);
1799 }
1800 
1801 static int
1802 iwn_alloc_kw(struct iwn_softc *sc)
1803 {
1804 	/* "Keep Warm" page must be aligned on a 4KB boundary. */
1805 	return iwn_dma_contig_alloc(sc, &sc->kw_dma, NULL, 4096, 4096);
1806 }
1807 
1808 static void
1809 iwn_free_kw(struct iwn_softc *sc)
1810 {
1811 	iwn_dma_contig_free(&sc->kw_dma);
1812 }
1813 
1814 static int
1815 iwn_alloc_ict(struct iwn_softc *sc)
1816 {
1817 	/* ICT table must be aligned on a 4KB boundary. */
1818 	return iwn_dma_contig_alloc(sc, &sc->ict_dma, (void **)&sc->ict,
1819 	    IWN_ICT_SIZE, 4096);
1820 }
1821 
1822 static void
1823 iwn_free_ict(struct iwn_softc *sc)
1824 {
1825 	iwn_dma_contig_free(&sc->ict_dma);
1826 }
1827 
1828 static int
1829 iwn_alloc_fwmem(struct iwn_softc *sc)
1830 {
1831 	/* Must be aligned on a 16-byte boundary. */
1832 	return iwn_dma_contig_alloc(sc, &sc->fw_dma, NULL, sc->fwsz, 16);
1833 }
1834 
1835 static void
1836 iwn_free_fwmem(struct iwn_softc *sc)
1837 {
1838 	iwn_dma_contig_free(&sc->fw_dma);
1839 }
1840 
1841 static int
1842 iwn_alloc_rx_ring(struct iwn_softc *sc, struct iwn_rx_ring *ring)
1843 {
1844 	bus_size_t size;
1845 	int i, error;
1846 
1847 	ring->cur = 0;
1848 
1849 	DPRINTF(sc, IWN_DEBUG_TRACE, "->%s begin\n", __func__);
1850 
1851 	/* Allocate RX descriptors (256-byte aligned). */
1852 	size = IWN_RX_RING_COUNT * sizeof (uint32_t);
1853 	error = iwn_dma_contig_alloc(sc, &ring->desc_dma, (void **)&ring->desc,
1854 	    size, 256);
1855 	if (error != 0) {
1856 		device_printf(sc->sc_dev,
1857 		    "%s: could not allocate RX ring DMA memory, error %d\n",
1858 		    __func__, error);
1859 		goto fail;
1860 	}
1861 
1862 	/* Allocate RX status area (16-byte aligned). */
1863 	error = iwn_dma_contig_alloc(sc, &ring->stat_dma, (void **)&ring->stat,
1864 	    sizeof (struct iwn_rx_status), 16);
1865 	if (error != 0) {
1866 		device_printf(sc->sc_dev,
1867 		    "%s: could not allocate RX status DMA memory, error %d\n",
1868 		    __func__, error);
1869 		goto fail;
1870 	}
1871 
1872 	/* Create RX buffer DMA tag. */
1873 	error = bus_dma_tag_create(bus_get_dma_tag(sc->sc_dev), 1, 0,
1874 	    BUS_SPACE_MAXADDR_32BIT, BUS_SPACE_MAXADDR, NULL, NULL,
1875 	    IWN_RBUF_SIZE, 1, IWN_RBUF_SIZE, BUS_DMA_NOWAIT, NULL, NULL,
1876 	    &ring->data_dmat);
1877 	if (error != 0) {
1878 		device_printf(sc->sc_dev,
1879 		    "%s: could not create RX buf DMA tag, error %d\n",
1880 		    __func__, error);
1881 		goto fail;
1882 	}
1883 
1884 	/*
1885 	 * Allocate and map RX buffers.
1886 	 */
1887 	for (i = 0; i < IWN_RX_RING_COUNT; i++) {
1888 		struct iwn_rx_data *data = &ring->data[i];
1889 		bus_addr_t paddr;
1890 
1891 		error = bus_dmamap_create(ring->data_dmat, 0, &data->map);
1892 		if (error != 0) {
1893 			device_printf(sc->sc_dev,
1894 			    "%s: could not create RX buf DMA map, error %d\n",
1895 			    __func__, error);
1896 			goto fail;
1897 		}
1898 
1899 		data->m = m_getjcl(M_NOWAIT, MT_DATA, M_PKTHDR,
1900 		    IWN_RBUF_SIZE);
1901 		if (data->m == NULL) {
1902 			device_printf(sc->sc_dev,
1903 			    "%s: could not allocate RX mbuf\n", __func__);
1904 			error = ENOBUFS;
1905 			goto fail;
1906 		}
1907 
1908 		error = bus_dmamap_load(ring->data_dmat, data->map,
1909 		    mtod(data->m, void *), IWN_RBUF_SIZE, iwn_dma_map_addr,
1910 		    &paddr, BUS_DMA_NOWAIT);
1911 		if (error != 0 && error != EFBIG) {
1912 			device_printf(sc->sc_dev,
1913 			    "%s: can't map mbuf, error %d\n", __func__,
1914 			    error);
1915 			goto fail;
1916 		}
1917 
1918 		/* Set physical address of RX buffer (256-byte aligned). */
1919 		ring->desc[i] = htole32(paddr >> 8);
1920 	}
1921 
1922 	bus_dmamap_sync(ring->desc_dma.tag, ring->desc_dma.map,
1923 	    BUS_DMASYNC_PREWRITE);
1924 
1925 	DPRINTF(sc, IWN_DEBUG_TRACE, "->%s: end\n",__func__);
1926 
1927 	return 0;
1928 
1929 fail:	iwn_free_rx_ring(sc, ring);
1930 
1931 	DPRINTF(sc, IWN_DEBUG_TRACE, "->%s: end in error\n",__func__);
1932 
1933 	return error;
1934 }
1935 
1936 static void
1937 iwn_reset_rx_ring(struct iwn_softc *sc, struct iwn_rx_ring *ring)
1938 {
1939 	int ntries;
1940 
1941 	DPRINTF(sc, IWN_DEBUG_TRACE, "->Doing %s\n", __func__);
1942 
1943 	if (iwn_nic_lock(sc) == 0) {
1944 		IWN_WRITE(sc, IWN_FH_RX_CONFIG, 0);
1945 		for (ntries = 0; ntries < 1000; ntries++) {
1946 			if (IWN_READ(sc, IWN_FH_RX_STATUS) &
1947 			    IWN_FH_RX_STATUS_IDLE)
1948 				break;
1949 			DELAY(10);
1950 		}
1951 		iwn_nic_unlock(sc);
1952 	}
1953 	ring->cur = 0;
1954 	sc->last_rx_valid = 0;
1955 }
1956 
1957 static void
1958 iwn_free_rx_ring(struct iwn_softc *sc, struct iwn_rx_ring *ring)
1959 {
1960 	int i;
1961 
1962 	DPRINTF(sc, IWN_DEBUG_TRACE, "->Doing %s \n", __func__);
1963 
1964 	iwn_dma_contig_free(&ring->desc_dma);
1965 	iwn_dma_contig_free(&ring->stat_dma);
1966 
1967 	for (i = 0; i < IWN_RX_RING_COUNT; i++) {
1968 		struct iwn_rx_data *data = &ring->data[i];
1969 
1970 		if (data->m != NULL) {
1971 			bus_dmamap_sync(ring->data_dmat, data->map,
1972 			    BUS_DMASYNC_POSTREAD);
1973 			bus_dmamap_unload(ring->data_dmat, data->map);
1974 			m_freem(data->m);
1975 			data->m = NULL;
1976 		}
1977 		if (data->map != NULL)
1978 			bus_dmamap_destroy(ring->data_dmat, data->map);
1979 	}
1980 	if (ring->data_dmat != NULL) {
1981 		bus_dma_tag_destroy(ring->data_dmat);
1982 		ring->data_dmat = NULL;
1983 	}
1984 }
1985 
1986 static int
1987 iwn_alloc_tx_ring(struct iwn_softc *sc, struct iwn_tx_ring *ring, int qid)
1988 {
1989 	bus_addr_t paddr;
1990 	bus_size_t size;
1991 	int i, error;
1992 
1993 	ring->qid = qid;
1994 	ring->queued = 0;
1995 	ring->cur = 0;
1996 
1997 	DPRINTF(sc, IWN_DEBUG_TRACE, "->%s begin\n", __func__);
1998 
1999 	/* Allocate TX descriptors (256-byte aligned). */
2000 	size = IWN_TX_RING_COUNT * sizeof (struct iwn_tx_desc);
2001 	error = iwn_dma_contig_alloc(sc, &ring->desc_dma, (void **)&ring->desc,
2002 	    size, 256);
2003 	if (error != 0) {
2004 		device_printf(sc->sc_dev,
2005 		    "%s: could not allocate TX ring DMA memory, error %d\n",
2006 		    __func__, error);
2007 		goto fail;
2008 	}
2009 
2010 	size = IWN_TX_RING_COUNT * sizeof (struct iwn_tx_cmd);
2011 	error = iwn_dma_contig_alloc(sc, &ring->cmd_dma, (void **)&ring->cmd,
2012 	    size, 4);
2013 	if (error != 0) {
2014 		device_printf(sc->sc_dev,
2015 		    "%s: could not allocate TX cmd DMA memory, error %d\n",
2016 		    __func__, error);
2017 		goto fail;
2018 	}
2019 
2020 	error = bus_dma_tag_create(bus_get_dma_tag(sc->sc_dev), 1, 0,
2021 	    BUS_SPACE_MAXADDR_32BIT, BUS_SPACE_MAXADDR, NULL, NULL, MCLBYTES,
2022 	    IWN_MAX_SCATTER - 1, MCLBYTES, BUS_DMA_NOWAIT, NULL, NULL,
2023 	    &ring->data_dmat);
2024 	if (error != 0) {
2025 		device_printf(sc->sc_dev,
2026 		    "%s: could not create TX buf DMA tag, error %d\n",
2027 		    __func__, error);
2028 		goto fail;
2029 	}
2030 
2031 	paddr = ring->cmd_dma.paddr;
2032 	for (i = 0; i < IWN_TX_RING_COUNT; i++) {
2033 		struct iwn_tx_data *data = &ring->data[i];
2034 
2035 		data->cmd_paddr = paddr;
2036 		data->scratch_paddr = paddr + 12;
2037 		paddr += sizeof (struct iwn_tx_cmd);
2038 
2039 		error = bus_dmamap_create(ring->data_dmat, 0, &data->map);
2040 		if (error != 0) {
2041 			device_printf(sc->sc_dev,
2042 			    "%s: could not create TX buf DMA map, error %d\n",
2043 			    __func__, error);
2044 			goto fail;
2045 		}
2046 	}
2047 
2048 	DPRINTF(sc, IWN_DEBUG_TRACE, "->%s end\n", __func__);
2049 
2050 	return 0;
2051 
2052 fail:	iwn_free_tx_ring(sc, ring);
2053 	DPRINTF(sc, IWN_DEBUG_TRACE, "->%s end in error\n", __func__);
2054 	return error;
2055 }
2056 
2057 static void
2058 iwn_reset_tx_ring(struct iwn_softc *sc, struct iwn_tx_ring *ring)
2059 {
2060 	int i;
2061 
2062 	DPRINTF(sc, IWN_DEBUG_TRACE, "->doing %s \n", __func__);
2063 
2064 	for (i = 0; i < IWN_TX_RING_COUNT; i++) {
2065 		struct iwn_tx_data *data = &ring->data[i];
2066 
2067 		if (data->m != NULL) {
2068 			bus_dmamap_sync(ring->data_dmat, data->map,
2069 			    BUS_DMASYNC_POSTWRITE);
2070 			bus_dmamap_unload(ring->data_dmat, data->map);
2071 			m_freem(data->m);
2072 			data->m = NULL;
2073 		}
2074 		if (data->ni != NULL) {
2075 			ieee80211_free_node(data->ni);
2076 			data->ni = NULL;
2077 		}
2078 	}
2079 	/* Clear TX descriptors. */
2080 	memset(ring->desc, 0, ring->desc_dma.size);
2081 	bus_dmamap_sync(ring->desc_dma.tag, ring->desc_dma.map,
2082 	    BUS_DMASYNC_PREWRITE);
2083 	sc->qfullmsk &= ~(1 << ring->qid);
2084 	ring->queued = 0;
2085 	ring->cur = 0;
2086 }
2087 
2088 static void
2089 iwn_free_tx_ring(struct iwn_softc *sc, struct iwn_tx_ring *ring)
2090 {
2091 	int i;
2092 
2093 	DPRINTF(sc, IWN_DEBUG_TRACE, "->Doing %s \n", __func__);
2094 
2095 	iwn_dma_contig_free(&ring->desc_dma);
2096 	iwn_dma_contig_free(&ring->cmd_dma);
2097 
2098 	for (i = 0; i < IWN_TX_RING_COUNT; i++) {
2099 		struct iwn_tx_data *data = &ring->data[i];
2100 
2101 		if (data->m != NULL) {
2102 			bus_dmamap_sync(ring->data_dmat, data->map,
2103 			    BUS_DMASYNC_POSTWRITE);
2104 			bus_dmamap_unload(ring->data_dmat, data->map);
2105 			m_freem(data->m);
2106 		}
2107 		if (data->map != NULL)
2108 			bus_dmamap_destroy(ring->data_dmat, data->map);
2109 	}
2110 	if (ring->data_dmat != NULL) {
2111 		bus_dma_tag_destroy(ring->data_dmat);
2112 		ring->data_dmat = NULL;
2113 	}
2114 }
2115 
2116 static void
2117 iwn5000_ict_reset(struct iwn_softc *sc)
2118 {
2119 	/* Disable interrupts. */
2120 	IWN_WRITE(sc, IWN_INT_MASK, 0);
2121 
2122 	/* Reset ICT table. */
2123 	memset(sc->ict, 0, IWN_ICT_SIZE);
2124 	sc->ict_cur = 0;
2125 
2126 	/* Set physical address of ICT table (4KB aligned). */
2127 	DPRINTF(sc, IWN_DEBUG_RESET, "%s: enabling ICT\n", __func__);
2128 	IWN_WRITE(sc, IWN_DRAM_INT_TBL, IWN_DRAM_INT_TBL_ENABLE |
2129 	    IWN_DRAM_INT_TBL_WRAP_CHECK | sc->ict_dma.paddr >> 12);
2130 
2131 	/* Enable periodic RX interrupt. */
2132 	sc->int_mask |= IWN_INT_RX_PERIODIC;
2133 	/* Switch to ICT interrupt mode in driver. */
2134 	sc->sc_flags |= IWN_FLAG_USE_ICT;
2135 
2136 	/* Re-enable interrupts. */
2137 	IWN_WRITE(sc, IWN_INT, 0xffffffff);
2138 	IWN_WRITE(sc, IWN_INT_MASK, sc->int_mask);
2139 }
2140 
2141 static int
2142 iwn_read_eeprom(struct iwn_softc *sc, uint8_t macaddr[IEEE80211_ADDR_LEN])
2143 {
2144 	struct iwn_ops *ops = &sc->ops;
2145 	uint16_t val;
2146 	int error;
2147 
2148 	DPRINTF(sc, IWN_DEBUG_TRACE, "->%s begin\n", __func__);
2149 
2150 	/* Check whether adapter has an EEPROM or an OTPROM. */
2151 	if (sc->hw_type >= IWN_HW_REV_TYPE_1000 &&
2152 	    (IWN_READ(sc, IWN_OTP_GP) & IWN_OTP_GP_DEV_SEL_OTP))
2153 		sc->sc_flags |= IWN_FLAG_HAS_OTPROM;
2154 	DPRINTF(sc, IWN_DEBUG_RESET, "%s found\n",
2155 	    (sc->sc_flags & IWN_FLAG_HAS_OTPROM) ? "OTPROM" : "EEPROM");
2156 
2157 	/* Adapter has to be powered on for EEPROM access to work. */
2158 	if ((error = iwn_apm_init(sc)) != 0) {
2159 		device_printf(sc->sc_dev,
2160 		    "%s: could not power ON adapter, error %d\n", __func__,
2161 		    error);
2162 		return error;
2163 	}
2164 
2165 	if ((IWN_READ(sc, IWN_EEPROM_GP) & 0x7) == 0) {
2166 		device_printf(sc->sc_dev, "%s: bad ROM signature\n", __func__);
2167 		return EIO;
2168 	}
2169 	if ((error = iwn_eeprom_lock(sc)) != 0) {
2170 		device_printf(sc->sc_dev, "%s: could not lock ROM, error %d\n",
2171 		    __func__, error);
2172 		return error;
2173 	}
2174 	if (sc->sc_flags & IWN_FLAG_HAS_OTPROM) {
2175 		if ((error = iwn_init_otprom(sc)) != 0) {
2176 			device_printf(sc->sc_dev,
2177 			    "%s: could not initialize OTPROM, error %d\n",
2178 			    __func__, error);
2179 			return error;
2180 		}
2181 	}
2182 
2183 	iwn_read_prom_data(sc, IWN_EEPROM_SKU_CAP, &val, 2);
2184 	DPRINTF(sc, IWN_DEBUG_RESET, "SKU capabilities=0x%04x\n", le16toh(val));
2185 	/* Check if HT support is bonded out. */
2186 	if (val & htole16(IWN_EEPROM_SKU_CAP_11N))
2187 		sc->sc_flags |= IWN_FLAG_HAS_11N;
2188 
2189 	iwn_read_prom_data(sc, IWN_EEPROM_RFCFG, &val, 2);
2190 	sc->rfcfg = le16toh(val);
2191 	DPRINTF(sc, IWN_DEBUG_RESET, "radio config=0x%04x\n", sc->rfcfg);
2192 	/* Read Tx/Rx chains from ROM unless it's known to be broken. */
2193 	if (sc->txchainmask == 0)
2194 		sc->txchainmask = IWN_RFCFG_TXANTMSK(sc->rfcfg);
2195 	if (sc->rxchainmask == 0)
2196 		sc->rxchainmask = IWN_RFCFG_RXANTMSK(sc->rfcfg);
2197 
2198 	/* Read MAC address. */
2199 	iwn_read_prom_data(sc, IWN_EEPROM_MAC, macaddr, 6);
2200 
2201 	/* Read adapter-specific information from EEPROM. */
2202 	ops->read_eeprom(sc);
2203 
2204 	iwn_apm_stop(sc);	/* Power OFF adapter. */
2205 
2206 	iwn_eeprom_unlock(sc);
2207 
2208 	DPRINTF(sc, IWN_DEBUG_TRACE, "->%s end\n", __func__);
2209 
2210 	return 0;
2211 }
2212 
2213 static void
2214 iwn4965_read_eeprom(struct iwn_softc *sc)
2215 {
2216 	uint32_t addr;
2217 	uint16_t val;
2218 	int i;
2219 
2220 	DPRINTF(sc, IWN_DEBUG_TRACE, "->%s begin\n", __func__);
2221 
2222 	/* Read regulatory domain (4 ASCII characters). */
2223 	iwn_read_prom_data(sc, IWN4965_EEPROM_DOMAIN, sc->eeprom_domain, 4);
2224 
2225 	/* Read the list of authorized channels (20MHz ones only). */
2226 	for (i = 0; i < IWN_NBANDS - 1; i++) {
2227 		addr = iwn4965_regulatory_bands[i];
2228 		iwn_read_eeprom_channels(sc, i, addr);
2229 	}
2230 
2231 	/* Read maximum allowed TX power for 2GHz and 5GHz bands. */
2232 	iwn_read_prom_data(sc, IWN4965_EEPROM_MAXPOW, &val, 2);
2233 	sc->maxpwr2GHz = val & 0xff;
2234 	sc->maxpwr5GHz = val >> 8;
2235 	/* Check that EEPROM values are within valid range. */
2236 	if (sc->maxpwr5GHz < 20 || sc->maxpwr5GHz > 50)
2237 		sc->maxpwr5GHz = 38;
2238 	if (sc->maxpwr2GHz < 20 || sc->maxpwr2GHz > 50)
2239 		sc->maxpwr2GHz = 38;
2240 	DPRINTF(sc, IWN_DEBUG_RESET, "maxpwr 2GHz=%d 5GHz=%d\n",
2241 	    sc->maxpwr2GHz, sc->maxpwr5GHz);
2242 
2243 	/* Read samples for each TX power group. */
2244 	iwn_read_prom_data(sc, IWN4965_EEPROM_BANDS, sc->bands,
2245 	    sizeof sc->bands);
2246 
2247 	/* Read voltage at which samples were taken. */
2248 	iwn_read_prom_data(sc, IWN4965_EEPROM_VOLTAGE, &val, 2);
2249 	sc->eeprom_voltage = (int16_t)le16toh(val);
2250 	DPRINTF(sc, IWN_DEBUG_RESET, "voltage=%d (in 0.3V)\n",
2251 	    sc->eeprom_voltage);
2252 
2253 #ifdef IWN_DEBUG
2254 	/* Print samples. */
2255 	if (sc->sc_debug & IWN_DEBUG_ANY) {
2256 		for (i = 0; i < IWN_NBANDS - 1; i++)
2257 			iwn4965_print_power_group(sc, i);
2258 	}
2259 #endif
2260 
2261 	DPRINTF(sc, IWN_DEBUG_TRACE, "->%s end\n", __func__);
2262 }
2263 
2264 #ifdef IWN_DEBUG
2265 static void
2266 iwn4965_print_power_group(struct iwn_softc *sc, int i)
2267 {
2268 	struct iwn4965_eeprom_band *band = &sc->bands[i];
2269 	struct iwn4965_eeprom_chan_samples *chans = band->chans;
2270 	int j, c;
2271 
2272 	printf("===band %d===\n", i);
2273 	printf("chan lo=%d, chan hi=%d\n", band->lo, band->hi);
2274 	printf("chan1 num=%d\n", chans[0].num);
2275 	for (c = 0; c < 2; c++) {
2276 		for (j = 0; j < IWN_NSAMPLES; j++) {
2277 			printf("chain %d, sample %d: temp=%d gain=%d "
2278 			    "power=%d pa_det=%d\n", c, j,
2279 			    chans[0].samples[c][j].temp,
2280 			    chans[0].samples[c][j].gain,
2281 			    chans[0].samples[c][j].power,
2282 			    chans[0].samples[c][j].pa_det);
2283 		}
2284 	}
2285 	printf("chan2 num=%d\n", chans[1].num);
2286 	for (c = 0; c < 2; c++) {
2287 		for (j = 0; j < IWN_NSAMPLES; j++) {
2288 			printf("chain %d, sample %d: temp=%d gain=%d "
2289 			    "power=%d pa_det=%d\n", c, j,
2290 			    chans[1].samples[c][j].temp,
2291 			    chans[1].samples[c][j].gain,
2292 			    chans[1].samples[c][j].power,
2293 			    chans[1].samples[c][j].pa_det);
2294 		}
2295 	}
2296 }
2297 #endif
2298 
2299 static void
2300 iwn5000_read_eeprom(struct iwn_softc *sc)
2301 {
2302 	struct iwn5000_eeprom_calib_hdr hdr;
2303 	int32_t volt;
2304 	uint32_t base, addr;
2305 	uint16_t val;
2306 	int i;
2307 
2308 	DPRINTF(sc, IWN_DEBUG_TRACE, "->%s begin\n", __func__);
2309 
2310 	/* Read regulatory domain (4 ASCII characters). */
2311 	iwn_read_prom_data(sc, IWN5000_EEPROM_REG, &val, 2);
2312 	base = le16toh(val);
2313 	iwn_read_prom_data(sc, base + IWN5000_EEPROM_DOMAIN,
2314 	    sc->eeprom_domain, 4);
2315 
2316 	/* Read the list of authorized channels (20MHz ones only). */
2317 	for (i = 0; i < IWN_NBANDS - 1; i++) {
2318 		addr =  base + sc->base_params->regulatory_bands[i];
2319 		iwn_read_eeprom_channels(sc, i, addr);
2320 	}
2321 
2322 	/* Read enhanced TX power information for 6000 Series. */
2323 	if (sc->base_params->enhanced_TX_power)
2324 		iwn_read_eeprom_enhinfo(sc);
2325 
2326 	iwn_read_prom_data(sc, IWN5000_EEPROM_CAL, &val, 2);
2327 	base = le16toh(val);
2328 	iwn_read_prom_data(sc, base, &hdr, sizeof hdr);
2329 	DPRINTF(sc, IWN_DEBUG_CALIBRATE,
2330 	    "%s: calib version=%u pa type=%u voltage=%u\n", __func__,
2331 	    hdr.version, hdr.pa_type, le16toh(hdr.volt));
2332 	sc->calib_ver = hdr.version;
2333 
2334 	if (sc->base_params->calib_need & IWN_FLG_NEED_PHY_CALIB_TEMP_OFFSETv2) {
2335 		sc->eeprom_voltage = le16toh(hdr.volt);
2336 		iwn_read_prom_data(sc, base + IWN5000_EEPROM_TEMP, &val, 2);
2337 		sc->eeprom_temp_high=le16toh(val);
2338 		iwn_read_prom_data(sc, base + IWN5000_EEPROM_VOLT, &val, 2);
2339 		sc->eeprom_temp = le16toh(val);
2340 	}
2341 
2342 	if (sc->hw_type == IWN_HW_REV_TYPE_5150) {
2343 		/* Compute temperature offset. */
2344 		iwn_read_prom_data(sc, base + IWN5000_EEPROM_TEMP, &val, 2);
2345 		sc->eeprom_temp = le16toh(val);
2346 		iwn_read_prom_data(sc, base + IWN5000_EEPROM_VOLT, &val, 2);
2347 		volt = le16toh(val);
2348 		sc->temp_off = sc->eeprom_temp - (volt / -5);
2349 		DPRINTF(sc, IWN_DEBUG_CALIBRATE, "temp=%d volt=%d offset=%dK\n",
2350 		    sc->eeprom_temp, volt, sc->temp_off);
2351 	} else {
2352 		/* Read crystal calibration. */
2353 		iwn_read_prom_data(sc, base + IWN5000_EEPROM_CRYSTAL,
2354 		    &sc->eeprom_crystal, sizeof (uint32_t));
2355 		DPRINTF(sc, IWN_DEBUG_CALIBRATE, "crystal calibration 0x%08x\n",
2356 		    le32toh(sc->eeprom_crystal));
2357 	}
2358 
2359 	DPRINTF(sc, IWN_DEBUG_TRACE, "->%s end\n", __func__);
2360 
2361 }
2362 
2363 /*
2364  * Translate EEPROM flags to net80211.
2365  */
2366 static uint32_t
2367 iwn_eeprom_channel_flags(struct iwn_eeprom_chan *channel)
2368 {
2369 	uint32_t nflags;
2370 
2371 	nflags = 0;
2372 	if ((channel->flags & IWN_EEPROM_CHAN_ACTIVE) == 0)
2373 		nflags |= IEEE80211_CHAN_PASSIVE;
2374 	if ((channel->flags & IWN_EEPROM_CHAN_IBSS) == 0)
2375 		nflags |= IEEE80211_CHAN_NOADHOC;
2376 	if (channel->flags & IWN_EEPROM_CHAN_RADAR) {
2377 		nflags |= IEEE80211_CHAN_DFS;
2378 		/* XXX apparently IBSS may still be marked */
2379 		nflags |= IEEE80211_CHAN_NOADHOC;
2380 	}
2381 
2382 	return nflags;
2383 }
2384 
2385 static void
2386 iwn_read_eeprom_band(struct iwn_softc *sc, int n)
2387 {
2388 	struct ifnet *ifp = sc->sc_ifp;
2389 	struct ieee80211com *ic = ifp->if_l2com;
2390 	struct iwn_eeprom_chan *channels = sc->eeprom_channels[n];
2391 	const struct iwn_chan_band *band = &iwn_bands[n];
2392 	struct ieee80211_channel *c;
2393 	uint8_t chan;
2394 	int i, nflags;
2395 
2396 	DPRINTF(sc, IWN_DEBUG_TRACE, "->%s begin\n", __func__);
2397 
2398 	for (i = 0; i < band->nchan; i++) {
2399 		if (!(channels[i].flags & IWN_EEPROM_CHAN_VALID)) {
2400 			DPRINTF(sc, IWN_DEBUG_RESET,
2401 			    "skip chan %d flags 0x%x maxpwr %d\n",
2402 			    band->chan[i], channels[i].flags,
2403 			    channels[i].maxpwr);
2404 			continue;
2405 		}
2406 		chan = band->chan[i];
2407 		nflags = iwn_eeprom_channel_flags(&channels[i]);
2408 
2409 		c = &ic->ic_channels[ic->ic_nchans++];
2410 		c->ic_ieee = chan;
2411 		c->ic_maxregpower = channels[i].maxpwr;
2412 		c->ic_maxpower = 2*c->ic_maxregpower;
2413 
2414 		if (n == 0) {	/* 2GHz band */
2415 			c->ic_freq = ieee80211_ieee2mhz(chan, IEEE80211_CHAN_G);
2416 			/* G =>'s B is supported */
2417 			c->ic_flags = IEEE80211_CHAN_B | nflags;
2418 			c = &ic->ic_channels[ic->ic_nchans++];
2419 			c[0] = c[-1];
2420 			c->ic_flags = IEEE80211_CHAN_G | nflags;
2421 		} else {	/* 5GHz band */
2422 			c->ic_freq = ieee80211_ieee2mhz(chan, IEEE80211_CHAN_A);
2423 			c->ic_flags = IEEE80211_CHAN_A | nflags;
2424 		}
2425 
2426 		/* Save maximum allowed TX power for this channel. */
2427 		sc->maxpwr[chan] = channels[i].maxpwr;
2428 
2429 		DPRINTF(sc, IWN_DEBUG_RESET,
2430 		    "add chan %d flags 0x%x maxpwr %d\n", chan,
2431 		    channels[i].flags, channels[i].maxpwr);
2432 
2433 		if (sc->sc_flags & IWN_FLAG_HAS_11N) {
2434 			/* add HT20, HT40 added separately */
2435 			c = &ic->ic_channels[ic->ic_nchans++];
2436 			c[0] = c[-1];
2437 			c->ic_flags |= IEEE80211_CHAN_HT20;
2438 		}
2439 	}
2440 
2441 	DPRINTF(sc, IWN_DEBUG_TRACE, "->%s end\n", __func__);
2442 
2443 }
2444 
2445 static void
2446 iwn_read_eeprom_ht40(struct iwn_softc *sc, int n)
2447 {
2448 	struct ifnet *ifp = sc->sc_ifp;
2449 	struct ieee80211com *ic = ifp->if_l2com;
2450 	struct iwn_eeprom_chan *channels = sc->eeprom_channels[n];
2451 	const struct iwn_chan_band *band = &iwn_bands[n];
2452 	struct ieee80211_channel *c, *cent, *extc;
2453 	uint8_t chan;
2454 	int i, nflags;
2455 
2456 	DPRINTF(sc, IWN_DEBUG_TRACE, "->%s start\n", __func__);
2457 
2458 	if (!(sc->sc_flags & IWN_FLAG_HAS_11N)) {
2459 		DPRINTF(sc, IWN_DEBUG_TRACE, "->%s end no 11n\n", __func__);
2460 		return;
2461 	}
2462 
2463 	for (i = 0; i < band->nchan; i++) {
2464 		if (!(channels[i].flags & IWN_EEPROM_CHAN_VALID)) {
2465 			DPRINTF(sc, IWN_DEBUG_RESET,
2466 			    "skip chan %d flags 0x%x maxpwr %d\n",
2467 			    band->chan[i], channels[i].flags,
2468 			    channels[i].maxpwr);
2469 			continue;
2470 		}
2471 		chan = band->chan[i];
2472 		nflags = iwn_eeprom_channel_flags(&channels[i]);
2473 
2474 		/*
2475 		 * Each entry defines an HT40 channel pair; find the
2476 		 * center channel, then the extension channel above.
2477 		 */
2478 		cent = ieee80211_find_channel_byieee(ic, chan,
2479 		    (n == 5 ? IEEE80211_CHAN_G : IEEE80211_CHAN_A));
2480 		if (cent == NULL) {	/* XXX shouldn't happen */
2481 			device_printf(sc->sc_dev,
2482 			    "%s: no entry for channel %d\n", __func__, chan);
2483 			continue;
2484 		}
2485 		extc = ieee80211_find_channel(ic, cent->ic_freq+20,
2486 		    (n == 5 ? IEEE80211_CHAN_G : IEEE80211_CHAN_A));
2487 		if (extc == NULL) {
2488 			DPRINTF(sc, IWN_DEBUG_RESET,
2489 			    "%s: skip chan %d, extension channel not found\n",
2490 			    __func__, chan);
2491 			continue;
2492 		}
2493 
2494 		DPRINTF(sc, IWN_DEBUG_RESET,
2495 		    "add ht40 chan %d flags 0x%x maxpwr %d\n",
2496 		    chan, channels[i].flags, channels[i].maxpwr);
2497 
2498 		c = &ic->ic_channels[ic->ic_nchans++];
2499 		c[0] = cent[0];
2500 		c->ic_extieee = extc->ic_ieee;
2501 		c->ic_flags &= ~IEEE80211_CHAN_HT;
2502 		c->ic_flags |= IEEE80211_CHAN_HT40U | nflags;
2503 		c = &ic->ic_channels[ic->ic_nchans++];
2504 		c[0] = extc[0];
2505 		c->ic_extieee = cent->ic_ieee;
2506 		c->ic_flags &= ~IEEE80211_CHAN_HT;
2507 		c->ic_flags |= IEEE80211_CHAN_HT40D | nflags;
2508 	}
2509 
2510 	DPRINTF(sc, IWN_DEBUG_TRACE, "->%s end\n", __func__);
2511 
2512 }
2513 
2514 static void
2515 iwn_read_eeprom_channels(struct iwn_softc *sc, int n, uint32_t addr)
2516 {
2517 	struct ifnet *ifp = sc->sc_ifp;
2518 	struct ieee80211com *ic = ifp->if_l2com;
2519 
2520 	iwn_read_prom_data(sc, addr, &sc->eeprom_channels[n],
2521 	    iwn_bands[n].nchan * sizeof (struct iwn_eeprom_chan));
2522 
2523 	if (n < 5)
2524 		iwn_read_eeprom_band(sc, n);
2525 	else
2526 		iwn_read_eeprom_ht40(sc, n);
2527 	ieee80211_sort_channels(ic->ic_channels, ic->ic_nchans);
2528 }
2529 
2530 static struct iwn_eeprom_chan *
2531 iwn_find_eeprom_channel(struct iwn_softc *sc, struct ieee80211_channel *c)
2532 {
2533 	int band, chan, i, j;
2534 
2535 	if (IEEE80211_IS_CHAN_HT40(c)) {
2536 		band = IEEE80211_IS_CHAN_5GHZ(c) ? 6 : 5;
2537 		if (IEEE80211_IS_CHAN_HT40D(c))
2538 			chan = c->ic_extieee;
2539 		else
2540 			chan = c->ic_ieee;
2541 		for (i = 0; i < iwn_bands[band].nchan; i++) {
2542 			if (iwn_bands[band].chan[i] == chan)
2543 				return &sc->eeprom_channels[band][i];
2544 		}
2545 	} else {
2546 		for (j = 0; j < 5; j++) {
2547 			for (i = 0; i < iwn_bands[j].nchan; i++) {
2548 				if (iwn_bands[j].chan[i] == c->ic_ieee)
2549 					return &sc->eeprom_channels[j][i];
2550 			}
2551 		}
2552 	}
2553 	return NULL;
2554 }
2555 
2556 /*
2557  * Enforce flags read from EEPROM.
2558  */
2559 static int
2560 iwn_setregdomain(struct ieee80211com *ic, struct ieee80211_regdomain *rd,
2561     int nchan, struct ieee80211_channel chans[])
2562 {
2563 	struct iwn_softc *sc = ic->ic_softc;
2564 	int i;
2565 
2566 	for (i = 0; i < nchan; i++) {
2567 		struct ieee80211_channel *c = &chans[i];
2568 		struct iwn_eeprom_chan *channel;
2569 
2570 		channel = iwn_find_eeprom_channel(sc, c);
2571 		if (channel == NULL) {
2572 			ic_printf(ic, "%s: invalid channel %u freq %u/0x%x\n",
2573 			    __func__, c->ic_ieee, c->ic_freq, c->ic_flags);
2574 			return EINVAL;
2575 		}
2576 		c->ic_flags |= iwn_eeprom_channel_flags(channel);
2577 	}
2578 
2579 	return 0;
2580 }
2581 
2582 static void
2583 iwn_read_eeprom_enhinfo(struct iwn_softc *sc)
2584 {
2585 	struct iwn_eeprom_enhinfo enhinfo[35];
2586 	struct ifnet *ifp = sc->sc_ifp;
2587 	struct ieee80211com *ic = ifp->if_l2com;
2588 	struct ieee80211_channel *c;
2589 	uint16_t val, base;
2590 	int8_t maxpwr;
2591 	uint8_t flags;
2592 	int i, j;
2593 
2594 	DPRINTF(sc, IWN_DEBUG_TRACE, "->%s begin\n", __func__);
2595 
2596 	iwn_read_prom_data(sc, IWN5000_EEPROM_REG, &val, 2);
2597 	base = le16toh(val);
2598 	iwn_read_prom_data(sc, base + IWN6000_EEPROM_ENHINFO,
2599 	    enhinfo, sizeof enhinfo);
2600 
2601 	for (i = 0; i < nitems(enhinfo); i++) {
2602 		flags = enhinfo[i].flags;
2603 		if (!(flags & IWN_ENHINFO_VALID))
2604 			continue;	/* Skip invalid entries. */
2605 
2606 		maxpwr = 0;
2607 		if (sc->txchainmask & IWN_ANT_A)
2608 			maxpwr = MAX(maxpwr, enhinfo[i].chain[0]);
2609 		if (sc->txchainmask & IWN_ANT_B)
2610 			maxpwr = MAX(maxpwr, enhinfo[i].chain[1]);
2611 		if (sc->txchainmask & IWN_ANT_C)
2612 			maxpwr = MAX(maxpwr, enhinfo[i].chain[2]);
2613 		if (sc->ntxchains == 2)
2614 			maxpwr = MAX(maxpwr, enhinfo[i].mimo2);
2615 		else if (sc->ntxchains == 3)
2616 			maxpwr = MAX(maxpwr, enhinfo[i].mimo3);
2617 
2618 		for (j = 0; j < ic->ic_nchans; j++) {
2619 			c = &ic->ic_channels[j];
2620 			if ((flags & IWN_ENHINFO_5GHZ)) {
2621 				if (!IEEE80211_IS_CHAN_A(c))
2622 					continue;
2623 			} else if ((flags & IWN_ENHINFO_OFDM)) {
2624 				if (!IEEE80211_IS_CHAN_G(c))
2625 					continue;
2626 			} else if (!IEEE80211_IS_CHAN_B(c))
2627 				continue;
2628 			if ((flags & IWN_ENHINFO_HT40)) {
2629 				if (!IEEE80211_IS_CHAN_HT40(c))
2630 					continue;
2631 			} else {
2632 				if (IEEE80211_IS_CHAN_HT40(c))
2633 					continue;
2634 			}
2635 			if (enhinfo[i].chan != 0 &&
2636 			    enhinfo[i].chan != c->ic_ieee)
2637 				continue;
2638 
2639 			DPRINTF(sc, IWN_DEBUG_RESET,
2640 			    "channel %d(%x), maxpwr %d\n", c->ic_ieee,
2641 			    c->ic_flags, maxpwr / 2);
2642 			c->ic_maxregpower = maxpwr / 2;
2643 			c->ic_maxpower = maxpwr;
2644 		}
2645 	}
2646 
2647 	DPRINTF(sc, IWN_DEBUG_TRACE, "->%s end\n", __func__);
2648 
2649 }
2650 
2651 static struct ieee80211_node *
2652 iwn_node_alloc(struct ieee80211vap *vap, const uint8_t mac[IEEE80211_ADDR_LEN])
2653 {
2654 	return malloc(sizeof (struct iwn_node), M_80211_NODE,M_NOWAIT | M_ZERO);
2655 }
2656 
2657 static __inline int
2658 rate2plcp(int rate)
2659 {
2660 	switch (rate & 0xff) {
2661 	case 12:	return 0xd;
2662 	case 18:	return 0xf;
2663 	case 24:	return 0x5;
2664 	case 36:	return 0x7;
2665 	case 48:	return 0x9;
2666 	case 72:	return 0xb;
2667 	case 96:	return 0x1;
2668 	case 108:	return 0x3;
2669 	case 2:		return 10;
2670 	case 4:		return 20;
2671 	case 11:	return 55;
2672 	case 22:	return 110;
2673 	}
2674 	return 0;
2675 }
2676 
2677 static int
2678 iwn_get_1stream_tx_antmask(struct iwn_softc *sc)
2679 {
2680 
2681 	return IWN_LSB(sc->txchainmask);
2682 }
2683 
2684 static int
2685 iwn_get_2stream_tx_antmask(struct iwn_softc *sc)
2686 {
2687 	int tx;
2688 
2689 	/*
2690 	 * The '2 stream' setup is a bit .. odd.
2691 	 *
2692 	 * For NICs that support only 1 antenna, default to IWN_ANT_AB or
2693 	 * the firmware panics (eg Intel 5100.)
2694 	 *
2695 	 * For NICs that support two antennas, we use ANT_AB.
2696 	 *
2697 	 * For NICs that support three antennas, we use the two that
2698 	 * wasn't the default one.
2699 	 *
2700 	 * XXX TODO: if bluetooth (full concurrent) is enabled, restrict
2701 	 * this to only one antenna.
2702 	 */
2703 
2704 	/* Default - transmit on the other antennas */
2705 	tx = (sc->txchainmask & ~IWN_LSB(sc->txchainmask));
2706 
2707 	/* Now, if it's zero, set it to IWN_ANT_AB, so to not panic firmware */
2708 	if (tx == 0)
2709 		tx = IWN_ANT_AB;
2710 
2711 	/*
2712 	 * If the NIC is a two-stream TX NIC, configure the TX mask to
2713 	 * the default chainmask
2714 	 */
2715 	else if (sc->ntxchains == 2)
2716 		tx = sc->txchainmask;
2717 
2718 	return (tx);
2719 }
2720 
2721 
2722 
2723 /*
2724  * Calculate the required PLCP value from the given rate,
2725  * to the given node.
2726  *
2727  * This will take the node configuration (eg 11n, rate table
2728  * setup, etc) into consideration.
2729  */
2730 static uint32_t
2731 iwn_rate_to_plcp(struct iwn_softc *sc, struct ieee80211_node *ni,
2732     uint8_t rate)
2733 {
2734 #define	RV(v)	((v) & IEEE80211_RATE_VAL)
2735 	struct ieee80211com *ic = ni->ni_ic;
2736 	uint32_t plcp = 0;
2737 	int ridx;
2738 
2739 	/*
2740 	 * If it's an MCS rate, let's set the plcp correctly
2741 	 * and set the relevant flags based on the node config.
2742 	 */
2743 	if (rate & IEEE80211_RATE_MCS) {
2744 		/*
2745 		 * Set the initial PLCP value to be between 0->31 for
2746 		 * MCS 0 -> MCS 31, then set the "I'm an MCS rate!"
2747 		 * flag.
2748 		 */
2749 		plcp = RV(rate) | IWN_RFLAG_MCS;
2750 
2751 		/*
2752 		 * XXX the following should only occur if both
2753 		 * the local configuration _and_ the remote node
2754 		 * advertise these capabilities.  Thus this code
2755 		 * may need fixing!
2756 		 */
2757 
2758 		/*
2759 		 * Set the channel width and guard interval.
2760 		 */
2761 		if (IEEE80211_IS_CHAN_HT40(ni->ni_chan)) {
2762 			plcp |= IWN_RFLAG_HT40;
2763 			if (ni->ni_htcap & IEEE80211_HTCAP_SHORTGI40)
2764 				plcp |= IWN_RFLAG_SGI;
2765 		} else if (ni->ni_htcap & IEEE80211_HTCAP_SHORTGI20) {
2766 			plcp |= IWN_RFLAG_SGI;
2767 		}
2768 
2769 		/*
2770 		 * Ensure the selected rate matches the link quality
2771 		 * table entries being used.
2772 		 */
2773 		if (rate > 0x8f)
2774 			plcp |= IWN_RFLAG_ANT(sc->txchainmask);
2775 		else if (rate > 0x87)
2776 			plcp |= IWN_RFLAG_ANT(iwn_get_2stream_tx_antmask(sc));
2777 		else
2778 			plcp |= IWN_RFLAG_ANT(iwn_get_1stream_tx_antmask(sc));
2779 	} else {
2780 		/*
2781 		 * Set the initial PLCP - fine for both
2782 		 * OFDM and CCK rates.
2783 		 */
2784 		plcp = rate2plcp(rate);
2785 
2786 		/* Set CCK flag if it's CCK */
2787 
2788 		/* XXX It would be nice to have a method
2789 		 * to map the ridx -> phy table entry
2790 		 * so we could just query that, rather than
2791 		 * this hack to check against IWN_RIDX_OFDM6.
2792 		 */
2793 		ridx = ieee80211_legacy_rate_lookup(ic->ic_rt,
2794 		    rate & IEEE80211_RATE_VAL);
2795 		if (ridx < IWN_RIDX_OFDM6 &&
2796 		    IEEE80211_IS_CHAN_2GHZ(ni->ni_chan))
2797 			plcp |= IWN_RFLAG_CCK;
2798 
2799 		/* Set antenna configuration */
2800 		/* XXX TODO: is this the right antenna to use for legacy? */
2801 		plcp |= IWN_RFLAG_ANT(iwn_get_1stream_tx_antmask(sc));
2802 	}
2803 
2804 	DPRINTF(sc, IWN_DEBUG_TXRATE, "%s: rate=0x%02x, plcp=0x%08x\n",
2805 	    __func__,
2806 	    rate,
2807 	    plcp);
2808 
2809 	return (htole32(plcp));
2810 #undef	RV
2811 }
2812 
2813 static void
2814 iwn_newassoc(struct ieee80211_node *ni, int isnew)
2815 {
2816 	/* Doesn't do anything at the moment */
2817 }
2818 
2819 static int
2820 iwn_media_change(struct ifnet *ifp)
2821 {
2822 	int error;
2823 
2824 	error = ieee80211_media_change(ifp);
2825 	/* NB: only the fixed rate can change and that doesn't need a reset */
2826 	return (error == ENETRESET ? 0 : error);
2827 }
2828 
2829 static int
2830 iwn_newstate(struct ieee80211vap *vap, enum ieee80211_state nstate, int arg)
2831 {
2832 	struct iwn_vap *ivp = IWN_VAP(vap);
2833 	struct ieee80211com *ic = vap->iv_ic;
2834 	struct iwn_softc *sc = ic->ic_softc;
2835 	int error = 0;
2836 
2837 	DPRINTF(sc, IWN_DEBUG_TRACE, "->%s begin\n", __func__);
2838 
2839 	DPRINTF(sc, IWN_DEBUG_STATE, "%s: %s -> %s\n", __func__,
2840 	    ieee80211_state_name[vap->iv_state], ieee80211_state_name[nstate]);
2841 
2842 	IEEE80211_UNLOCK(ic);
2843 	IWN_LOCK(sc);
2844 	callout_stop(&sc->calib_to);
2845 
2846 	sc->rxon = &sc->rx_on[IWN_RXON_BSS_CTX];
2847 
2848 	switch (nstate) {
2849 	case IEEE80211_S_ASSOC:
2850 		if (vap->iv_state != IEEE80211_S_RUN)
2851 			break;
2852 		/* FALLTHROUGH */
2853 	case IEEE80211_S_AUTH:
2854 		if (vap->iv_state == IEEE80211_S_AUTH)
2855 			break;
2856 
2857 		/*
2858 		 * !AUTH -> AUTH transition requires state reset to handle
2859 		 * reassociations correctly.
2860 		 */
2861 		sc->rxon->associd = 0;
2862 		sc->rxon->filter &= ~htole32(IWN_FILTER_BSS);
2863 		sc->calib.state = IWN_CALIB_STATE_INIT;
2864 
2865 		/* Wait until we hear a beacon before we transmit */
2866 		sc->sc_beacon_wait = 1;
2867 
2868 		if ((error = iwn_auth(sc, vap)) != 0) {
2869 			device_printf(sc->sc_dev,
2870 			    "%s: could not move to auth state\n", __func__);
2871 		}
2872 		break;
2873 
2874 	case IEEE80211_S_RUN:
2875 		/*
2876 		 * RUN -> RUN transition; Just restart the timers.
2877 		 */
2878 		if (vap->iv_state == IEEE80211_S_RUN) {
2879 			sc->calib_cnt = 0;
2880 			break;
2881 		}
2882 
2883 		/* Wait until we hear a beacon before we transmit */
2884 		sc->sc_beacon_wait = 1;
2885 
2886 		/*
2887 		 * !RUN -> RUN requires setting the association id
2888 		 * which is done with a firmware cmd.  We also defer
2889 		 * starting the timers until that work is done.
2890 		 */
2891 		if ((error = iwn_run(sc, vap)) != 0) {
2892 			device_printf(sc->sc_dev,
2893 			    "%s: could not move to run state\n", __func__);
2894 		}
2895 		break;
2896 
2897 	case IEEE80211_S_INIT:
2898 		sc->calib.state = IWN_CALIB_STATE_INIT;
2899 		/*
2900 		 * Purge the xmit queue so we don't have old frames
2901 		 * during a new association attempt.
2902 		 */
2903 		sc->sc_beacon_wait = 0;
2904 		iwn_xmit_queue_drain(sc);
2905 		break;
2906 
2907 	default:
2908 		break;
2909 	}
2910 	IWN_UNLOCK(sc);
2911 	IEEE80211_LOCK(ic);
2912 	if (error != 0){
2913 		DPRINTF(sc, IWN_DEBUG_TRACE, "->%s end in error\n", __func__);
2914 		return error;
2915 	}
2916 
2917 	DPRINTF(sc, IWN_DEBUG_TRACE, "->%s: end\n",__func__);
2918 
2919 	return ivp->iv_newstate(vap, nstate, arg);
2920 }
2921 
2922 static void
2923 iwn_calib_timeout(void *arg)
2924 {
2925 	struct iwn_softc *sc = arg;
2926 
2927 	IWN_LOCK_ASSERT(sc);
2928 
2929 	/* Force automatic TX power calibration every 60 secs. */
2930 	if (++sc->calib_cnt >= 120) {
2931 		uint32_t flags = 0;
2932 
2933 		DPRINTF(sc, IWN_DEBUG_CALIBRATE, "%s\n",
2934 		    "sending request for statistics");
2935 		(void)iwn_cmd(sc, IWN_CMD_GET_STATISTICS, &flags,
2936 		    sizeof flags, 1);
2937 		sc->calib_cnt = 0;
2938 	}
2939 	callout_reset(&sc->calib_to, msecs_to_ticks(500), iwn_calib_timeout,
2940 	    sc);
2941 }
2942 
2943 /*
2944  * Process an RX_PHY firmware notification.  This is usually immediately
2945  * followed by an MPDU_RX_DONE notification.
2946  */
2947 static void
2948 iwn_rx_phy(struct iwn_softc *sc, struct iwn_rx_desc *desc,
2949     struct iwn_rx_data *data)
2950 {
2951 	struct iwn_rx_stat *stat = (struct iwn_rx_stat *)(desc + 1);
2952 
2953 	DPRINTF(sc, IWN_DEBUG_CALIBRATE, "%s: received PHY stats\n", __func__);
2954 	bus_dmamap_sync(sc->rxq.data_dmat, data->map, BUS_DMASYNC_POSTREAD);
2955 
2956 	/* Save RX statistics, they will be used on MPDU_RX_DONE. */
2957 	memcpy(&sc->last_rx_stat, stat, sizeof (*stat));
2958 	sc->last_rx_valid = 1;
2959 }
2960 
2961 /*
2962  * Process an RX_DONE (4965AGN only) or MPDU_RX_DONE firmware notification.
2963  * Each MPDU_RX_DONE notification must be preceded by an RX_PHY one.
2964  */
2965 static void
2966 iwn_rx_done(struct iwn_softc *sc, struct iwn_rx_desc *desc,
2967     struct iwn_rx_data *data)
2968 {
2969 	struct iwn_ops *ops = &sc->ops;
2970 	struct ifnet *ifp = sc->sc_ifp;
2971 	struct ieee80211com *ic = ifp->if_l2com;
2972 	struct iwn_rx_ring *ring = &sc->rxq;
2973 	struct ieee80211_frame *wh;
2974 	struct ieee80211_node *ni;
2975 	struct mbuf *m, *m1;
2976 	struct iwn_rx_stat *stat;
2977 	caddr_t head;
2978 	bus_addr_t paddr;
2979 	uint32_t flags;
2980 	int error, len, rssi, nf;
2981 
2982 	DPRINTF(sc, IWN_DEBUG_TRACE, "->%s begin\n", __func__);
2983 
2984 	if (desc->type == IWN_MPDU_RX_DONE) {
2985 		/* Check for prior RX_PHY notification. */
2986 		if (!sc->last_rx_valid) {
2987 			DPRINTF(sc, IWN_DEBUG_ANY,
2988 			    "%s: missing RX_PHY\n", __func__);
2989 			return;
2990 		}
2991 		stat = &sc->last_rx_stat;
2992 	} else
2993 		stat = (struct iwn_rx_stat *)(desc + 1);
2994 
2995 	bus_dmamap_sync(ring->data_dmat, data->map, BUS_DMASYNC_POSTREAD);
2996 
2997 	if (stat->cfg_phy_len > IWN_STAT_MAXLEN) {
2998 		device_printf(sc->sc_dev,
2999 		    "%s: invalid RX statistic header, len %d\n", __func__,
3000 		    stat->cfg_phy_len);
3001 		return;
3002 	}
3003 	if (desc->type == IWN_MPDU_RX_DONE) {
3004 		struct iwn_rx_mpdu *mpdu = (struct iwn_rx_mpdu *)(desc + 1);
3005 		head = (caddr_t)(mpdu + 1);
3006 		len = le16toh(mpdu->len);
3007 	} else {
3008 		head = (caddr_t)(stat + 1) + stat->cfg_phy_len;
3009 		len = le16toh(stat->len);
3010 	}
3011 
3012 	flags = le32toh(*(uint32_t *)(head + len));
3013 
3014 	/* Discard frames with a bad FCS early. */
3015 	if ((flags & IWN_RX_NOERROR) != IWN_RX_NOERROR) {
3016 		DPRINTF(sc, IWN_DEBUG_RECV, "%s: RX flags error %x\n",
3017 		    __func__, flags);
3018 		if_inc_counter(ifp, IFCOUNTER_IERRORS, 1);
3019 		return;
3020 	}
3021 	/* Discard frames that are too short. */
3022 	if (len < sizeof (struct ieee80211_frame_ack)) {
3023 		DPRINTF(sc, IWN_DEBUG_RECV, "%s: frame too short: %d\n",
3024 		    __func__, len);
3025 		if_inc_counter(ifp, IFCOUNTER_IERRORS, 1);
3026 		return;
3027 	}
3028 
3029 	m1 = m_getjcl(M_NOWAIT, MT_DATA, M_PKTHDR, IWN_RBUF_SIZE);
3030 	if (m1 == NULL) {
3031 		DPRINTF(sc, IWN_DEBUG_ANY, "%s: no mbuf to restock ring\n",
3032 		    __func__);
3033 		if_inc_counter(ifp, IFCOUNTER_IERRORS, 1);
3034 		return;
3035 	}
3036 	bus_dmamap_unload(ring->data_dmat, data->map);
3037 
3038 	error = bus_dmamap_load(ring->data_dmat, data->map, mtod(m1, void *),
3039 	    IWN_RBUF_SIZE, iwn_dma_map_addr, &paddr, BUS_DMA_NOWAIT);
3040 	if (error != 0 && error != EFBIG) {
3041 		device_printf(sc->sc_dev,
3042 		    "%s: bus_dmamap_load failed, error %d\n", __func__, error);
3043 		m_freem(m1);
3044 
3045 		/* Try to reload the old mbuf. */
3046 		error = bus_dmamap_load(ring->data_dmat, data->map,
3047 		    mtod(data->m, void *), IWN_RBUF_SIZE, iwn_dma_map_addr,
3048 		    &paddr, BUS_DMA_NOWAIT);
3049 		if (error != 0 && error != EFBIG) {
3050 			panic("%s: could not load old RX mbuf", __func__);
3051 		}
3052 		/* Physical address may have changed. */
3053 		ring->desc[ring->cur] = htole32(paddr >> 8);
3054 		bus_dmamap_sync(ring->data_dmat, ring->desc_dma.map,
3055 		    BUS_DMASYNC_PREWRITE);
3056 		if_inc_counter(ifp, IFCOUNTER_IERRORS, 1);
3057 		return;
3058 	}
3059 
3060 	m = data->m;
3061 	data->m = m1;
3062 	/* Update RX descriptor. */
3063 	ring->desc[ring->cur] = htole32(paddr >> 8);
3064 	bus_dmamap_sync(ring->desc_dma.tag, ring->desc_dma.map,
3065 	    BUS_DMASYNC_PREWRITE);
3066 
3067 	/* Finalize mbuf. */
3068 	m->m_pkthdr.rcvif = ifp;
3069 	m->m_data = head;
3070 	m->m_pkthdr.len = m->m_len = len;
3071 
3072 	/* Grab a reference to the source node. */
3073 	wh = mtod(m, struct ieee80211_frame *);
3074 	if (len >= sizeof(struct ieee80211_frame_min))
3075 		ni = ieee80211_find_rxnode(ic, (struct ieee80211_frame_min *)wh);
3076 	else
3077 		ni = NULL;
3078 	nf = (ni != NULL && ni->ni_vap->iv_state == IEEE80211_S_RUN &&
3079 	    (ic->ic_flags & IEEE80211_F_SCAN) == 0) ? sc->noise : -95;
3080 
3081 	rssi = ops->get_rssi(sc, stat);
3082 
3083 	if (ieee80211_radiotap_active(ic)) {
3084 		struct iwn_rx_radiotap_header *tap = &sc->sc_rxtap;
3085 
3086 		tap->wr_flags = 0;
3087 		if (stat->flags & htole16(IWN_STAT_FLAG_SHPREAMBLE))
3088 			tap->wr_flags |= IEEE80211_RADIOTAP_F_SHORTPRE;
3089 		tap->wr_dbm_antsignal = (int8_t)rssi;
3090 		tap->wr_dbm_antnoise = (int8_t)nf;
3091 		tap->wr_tsft = stat->tstamp;
3092 		switch (stat->rate) {
3093 		/* CCK rates. */
3094 		case  10: tap->wr_rate =   2; break;
3095 		case  20: tap->wr_rate =   4; break;
3096 		case  55: tap->wr_rate =  11; break;
3097 		case 110: tap->wr_rate =  22; break;
3098 		/* OFDM rates. */
3099 		case 0xd: tap->wr_rate =  12; break;
3100 		case 0xf: tap->wr_rate =  18; break;
3101 		case 0x5: tap->wr_rate =  24; break;
3102 		case 0x7: tap->wr_rate =  36; break;
3103 		case 0x9: tap->wr_rate =  48; break;
3104 		case 0xb: tap->wr_rate =  72; break;
3105 		case 0x1: tap->wr_rate =  96; break;
3106 		case 0x3: tap->wr_rate = 108; break;
3107 		/* Unknown rate: should not happen. */
3108 		default:  tap->wr_rate =   0;
3109 		}
3110 	}
3111 
3112 	/*
3113 	 * If it's a beacon and we're waiting, then do the
3114 	 * wakeup.  This should unblock raw_xmit/start.
3115 	 */
3116 	if (sc->sc_beacon_wait) {
3117 		uint8_t type, subtype;
3118 		/* NB: Re-assign wh */
3119 		wh = mtod(m, struct ieee80211_frame *);
3120 		type = wh->i_fc[0] & IEEE80211_FC0_TYPE_MASK;
3121 		subtype = wh->i_fc[0] & IEEE80211_FC0_SUBTYPE_MASK;
3122 		/*
3123 		 * This assumes at this point we've received our own
3124 		 * beacon.
3125 		 */
3126 		DPRINTF(sc, IWN_DEBUG_TRACE,
3127 		    "%s: beacon_wait, type=%d, subtype=%d\n",
3128 		    __func__, type, subtype);
3129 		if (type == IEEE80211_FC0_TYPE_MGT &&
3130 		    subtype == IEEE80211_FC0_SUBTYPE_BEACON) {
3131 			DPRINTF(sc, IWN_DEBUG_TRACE | IWN_DEBUG_XMIT,
3132 			    "%s: waking things up\n", __func__);
3133 			/* queue taskqueue to transmit! */
3134 			taskqueue_enqueue(sc->sc_tq, &sc->sc_xmit_task);
3135 		}
3136 	}
3137 
3138 	IWN_UNLOCK(sc);
3139 
3140 	/* Send the frame to the 802.11 layer. */
3141 	if (ni != NULL) {
3142 		if (ni->ni_flags & IEEE80211_NODE_HT)
3143 			m->m_flags |= M_AMPDU;
3144 		(void)ieee80211_input(ni, m, rssi - nf, nf);
3145 		/* Node is no longer needed. */
3146 		ieee80211_free_node(ni);
3147 	} else
3148 		(void)ieee80211_input_all(ic, m, rssi - nf, nf);
3149 
3150 	IWN_LOCK(sc);
3151 
3152 	DPRINTF(sc, IWN_DEBUG_TRACE, "->%s: end\n",__func__);
3153 
3154 }
3155 
3156 /* Process an incoming Compressed BlockAck. */
3157 static void
3158 iwn_rx_compressed_ba(struct iwn_softc *sc, struct iwn_rx_desc *desc,
3159     struct iwn_rx_data *data)
3160 {
3161 	struct iwn_ops *ops = &sc->ops;
3162 	struct ifnet *ifp = sc->sc_ifp;
3163 	struct iwn_node *wn;
3164 	struct ieee80211_node *ni;
3165 	struct iwn_compressed_ba *ba = (struct iwn_compressed_ba *)(desc + 1);
3166 	struct iwn_tx_ring *txq;
3167 	struct iwn_tx_data *txdata;
3168 	struct ieee80211_tx_ampdu *tap;
3169 	struct mbuf *m;
3170 	uint64_t bitmap;
3171 	uint16_t ssn;
3172 	uint8_t tid;
3173 	int ackfailcnt = 0, i, lastidx, qid, *res, shift;
3174 	int tx_ok = 0, tx_err = 0;
3175 
3176 	DPRINTF(sc, IWN_DEBUG_TRACE | IWN_DEBUG_XMIT, "->%s begin\n", __func__);
3177 
3178 	bus_dmamap_sync(sc->rxq.data_dmat, data->map, BUS_DMASYNC_POSTREAD);
3179 
3180 	qid = le16toh(ba->qid);
3181 	txq = &sc->txq[ba->qid];
3182 	tap = sc->qid2tap[ba->qid];
3183 	tid = tap->txa_tid;
3184 	wn = (void *)tap->txa_ni;
3185 
3186 	res = NULL;
3187 	ssn = 0;
3188 	if (!IEEE80211_AMPDU_RUNNING(tap)) {
3189 		res = tap->txa_private;
3190 		ssn = tap->txa_start & 0xfff;
3191 	}
3192 
3193 	for (lastidx = le16toh(ba->ssn) & 0xff; txq->read != lastidx;) {
3194 		txdata = &txq->data[txq->read];
3195 
3196 		/* Unmap and free mbuf. */
3197 		bus_dmamap_sync(txq->data_dmat, txdata->map,
3198 		    BUS_DMASYNC_POSTWRITE);
3199 		bus_dmamap_unload(txq->data_dmat, txdata->map);
3200 		m = txdata->m, txdata->m = NULL;
3201 		ni = txdata->ni, txdata->ni = NULL;
3202 
3203 		KASSERT(ni != NULL, ("no node"));
3204 		KASSERT(m != NULL, ("no mbuf"));
3205 
3206 		DPRINTF(sc, IWN_DEBUG_XMIT, "%s: freeing m=%p\n", __func__, m);
3207 		ieee80211_tx_complete(ni, m, 1);
3208 
3209 		txq->queued--;
3210 		txq->read = (txq->read + 1) % IWN_TX_RING_COUNT;
3211 	}
3212 
3213 	if (txq->queued == 0 && res != NULL) {
3214 		iwn_nic_lock(sc);
3215 		ops->ampdu_tx_stop(sc, qid, tid, ssn);
3216 		iwn_nic_unlock(sc);
3217 		sc->qid2tap[qid] = NULL;
3218 		free(res, M_DEVBUF);
3219 		return;
3220 	}
3221 
3222 	if (wn->agg[tid].bitmap == 0)
3223 		return;
3224 
3225 	shift = wn->agg[tid].startidx - ((le16toh(ba->seq) >> 4) & 0xff);
3226 	if (shift < 0)
3227 		shift += 0x100;
3228 
3229 	if (wn->agg[tid].nframes > (64 - shift))
3230 		return;
3231 
3232 	/*
3233 	 * Walk the bitmap and calculate how many successful and failed
3234 	 * attempts are made.
3235 	 *
3236 	 * Yes, the rate control code doesn't know these are A-MPDU
3237 	 * subframes and that it's okay to fail some of these.
3238 	 */
3239 	ni = tap->txa_ni;
3240 	bitmap = (le64toh(ba->bitmap) >> shift) & wn->agg[tid].bitmap;
3241 	for (i = 0; bitmap; i++) {
3242 		if ((bitmap & 1) == 0) {
3243 			if_inc_counter(ifp, IFCOUNTER_OERRORS, 1);
3244 			tx_err ++;
3245 			ieee80211_ratectl_tx_complete(ni->ni_vap, ni,
3246 			    IEEE80211_RATECTL_TX_FAILURE, &ackfailcnt, NULL);
3247 		} else {
3248 			if_inc_counter(ifp, IFCOUNTER_OPACKETS, 1);
3249 			tx_ok ++;
3250 			ieee80211_ratectl_tx_complete(ni->ni_vap, ni,
3251 			    IEEE80211_RATECTL_TX_SUCCESS, &ackfailcnt, NULL);
3252 		}
3253 		bitmap >>= 1;
3254 	}
3255 
3256 	DPRINTF(sc, IWN_DEBUG_TRACE | IWN_DEBUG_XMIT,
3257 	    "->%s: end; %d ok; %d err\n",__func__, tx_ok, tx_err);
3258 
3259 }
3260 
3261 /*
3262  * Process a CALIBRATION_RESULT notification sent by the initialization
3263  * firmware on response to a CMD_CALIB_CONFIG command (5000 only).
3264  */
3265 static void
3266 iwn5000_rx_calib_results(struct iwn_softc *sc, struct iwn_rx_desc *desc,
3267     struct iwn_rx_data *data)
3268 {
3269 	struct iwn_phy_calib *calib = (struct iwn_phy_calib *)(desc + 1);
3270 	int len, idx = -1;
3271 
3272 	DPRINTF(sc, IWN_DEBUG_TRACE, "->%s begin\n", __func__);
3273 
3274 	/* Runtime firmware should not send such a notification. */
3275 	if (sc->sc_flags & IWN_FLAG_CALIB_DONE){
3276 		DPRINTF(sc, IWN_DEBUG_TRACE, "->%s received after clib done\n",
3277 	    __func__);
3278 		return;
3279 	}
3280 	len = (le32toh(desc->len) & 0x3fff) - 4;
3281 	bus_dmamap_sync(sc->rxq.data_dmat, data->map, BUS_DMASYNC_POSTREAD);
3282 
3283 	switch (calib->code) {
3284 	case IWN5000_PHY_CALIB_DC:
3285 		if (sc->base_params->calib_need & IWN_FLG_NEED_PHY_CALIB_DC)
3286 			idx = 0;
3287 		break;
3288 	case IWN5000_PHY_CALIB_LO:
3289 		if (sc->base_params->calib_need & IWN_FLG_NEED_PHY_CALIB_LO)
3290 			idx = 1;
3291 		break;
3292 	case IWN5000_PHY_CALIB_TX_IQ:
3293 		if (sc->base_params->calib_need & IWN_FLG_NEED_PHY_CALIB_TX_IQ)
3294 			idx = 2;
3295 		break;
3296 	case IWN5000_PHY_CALIB_TX_IQ_PERIODIC:
3297 		if (sc->base_params->calib_need & IWN_FLG_NEED_PHY_CALIB_TX_IQ_PERIODIC)
3298 			idx = 3;
3299 		break;
3300 	case IWN5000_PHY_CALIB_BASE_BAND:
3301 		if (sc->base_params->calib_need & IWN_FLG_NEED_PHY_CALIB_BASE_BAND)
3302 			idx = 4;
3303 		break;
3304 	}
3305 	if (idx == -1)	/* Ignore other results. */
3306 		return;
3307 
3308 	/* Save calibration result. */
3309 	if (sc->calibcmd[idx].buf != NULL)
3310 		free(sc->calibcmd[idx].buf, M_DEVBUF);
3311 	sc->calibcmd[idx].buf = malloc(len, M_DEVBUF, M_NOWAIT);
3312 	if (sc->calibcmd[idx].buf == NULL) {
3313 		DPRINTF(sc, IWN_DEBUG_CALIBRATE,
3314 		    "not enough memory for calibration result %d\n",
3315 		    calib->code);
3316 		return;
3317 	}
3318 	DPRINTF(sc, IWN_DEBUG_CALIBRATE,
3319 	    "saving calibration result idx=%d, code=%d len=%d\n", idx, calib->code, len);
3320 	sc->calibcmd[idx].len = len;
3321 	memcpy(sc->calibcmd[idx].buf, calib, len);
3322 }
3323 
3324 static void
3325 iwn_stats_update(struct iwn_softc *sc, struct iwn_calib_state *calib,
3326     struct iwn_stats *stats, int len)
3327 {
3328 	struct iwn_stats_bt *stats_bt;
3329 	struct iwn_stats *lstats;
3330 
3331 	/*
3332 	 * First - check whether the length is the bluetooth or normal.
3333 	 *
3334 	 * If it's normal - just copy it and bump out.
3335 	 * Otherwise we have to convert things.
3336 	 */
3337 
3338 	if (len == sizeof(struct iwn_stats) + 4) {
3339 		memcpy(&sc->last_stat, stats, sizeof(struct iwn_stats));
3340 		sc->last_stat_valid = 1;
3341 		return;
3342 	}
3343 
3344 	/*
3345 	 * If it's not the bluetooth size - log, then just copy.
3346 	 */
3347 	if (len != sizeof(struct iwn_stats_bt) + 4) {
3348 		DPRINTF(sc, IWN_DEBUG_STATS,
3349 		    "%s: size of rx statistics (%d) not an expected size!\n",
3350 		    __func__,
3351 		    len);
3352 		memcpy(&sc->last_stat, stats, sizeof(struct iwn_stats));
3353 		sc->last_stat_valid = 1;
3354 		return;
3355 	}
3356 
3357 	/*
3358 	 * Ok. Time to copy.
3359 	 */
3360 	stats_bt = (struct iwn_stats_bt *) stats;
3361 	lstats = &sc->last_stat;
3362 
3363 	/* flags */
3364 	lstats->flags = stats_bt->flags;
3365 	/* rx_bt */
3366 	memcpy(&lstats->rx.ofdm, &stats_bt->rx_bt.ofdm,
3367 	    sizeof(struct iwn_rx_phy_stats));
3368 	memcpy(&lstats->rx.cck, &stats_bt->rx_bt.cck,
3369 	    sizeof(struct iwn_rx_phy_stats));
3370 	memcpy(&lstats->rx.general, &stats_bt->rx_bt.general_bt.common,
3371 	    sizeof(struct iwn_rx_general_stats));
3372 	memcpy(&lstats->rx.ht, &stats_bt->rx_bt.ht,
3373 	    sizeof(struct iwn_rx_ht_phy_stats));
3374 	/* tx */
3375 	memcpy(&lstats->tx, &stats_bt->tx,
3376 	    sizeof(struct iwn_tx_stats));
3377 	/* general */
3378 	memcpy(&lstats->general, &stats_bt->general,
3379 	    sizeof(struct iwn_general_stats));
3380 
3381 	/* XXX TODO: Squirrel away the extra bluetooth stats somewhere */
3382 	sc->last_stat_valid = 1;
3383 }
3384 
3385 /*
3386  * Process an RX_STATISTICS or BEACON_STATISTICS firmware notification.
3387  * The latter is sent by the firmware after each received beacon.
3388  */
3389 static void
3390 iwn_rx_statistics(struct iwn_softc *sc, struct iwn_rx_desc *desc,
3391     struct iwn_rx_data *data)
3392 {
3393 	struct iwn_ops *ops = &sc->ops;
3394 	struct ifnet *ifp = sc->sc_ifp;
3395 	struct ieee80211com *ic = ifp->if_l2com;
3396 	struct ieee80211vap *vap = TAILQ_FIRST(&ic->ic_vaps);
3397 	struct iwn_calib_state *calib = &sc->calib;
3398 	struct iwn_stats *stats = (struct iwn_stats *)(desc + 1);
3399 	struct iwn_stats *lstats;
3400 	int temp;
3401 
3402 	DPRINTF(sc, IWN_DEBUG_TRACE, "->%s begin\n", __func__);
3403 
3404 	/* Ignore statistics received during a scan. */
3405 	if (vap->iv_state != IEEE80211_S_RUN ||
3406 	    (ic->ic_flags & IEEE80211_F_SCAN)){
3407 		DPRINTF(sc, IWN_DEBUG_TRACE, "->%s received during calib\n",
3408 	    __func__);
3409 		return;
3410 	}
3411 
3412 	bus_dmamap_sync(sc->rxq.data_dmat, data->map, BUS_DMASYNC_POSTREAD);
3413 
3414 	DPRINTF(sc, IWN_DEBUG_CALIBRATE | IWN_DEBUG_STATS,
3415 	    "%s: received statistics, cmd %d, len %d\n",
3416 	    __func__, desc->type, le16toh(desc->len));
3417 	sc->calib_cnt = 0;	/* Reset TX power calibration timeout. */
3418 
3419 	/*
3420 	 * Collect/track general statistics for reporting.
3421 	 *
3422 	 * This takes care of ensuring that the bluetooth sized message
3423 	 * will be correctly converted to the legacy sized message.
3424 	 */
3425 	iwn_stats_update(sc, calib, stats, le16toh(desc->len));
3426 
3427 	/*
3428 	 * And now, let's take a reference of it to use!
3429 	 */
3430 	lstats = &sc->last_stat;
3431 
3432 	/* Test if temperature has changed. */
3433 	if (lstats->general.temp != sc->rawtemp) {
3434 		/* Convert "raw" temperature to degC. */
3435 		sc->rawtemp = stats->general.temp;
3436 		temp = ops->get_temperature(sc);
3437 		DPRINTF(sc, IWN_DEBUG_CALIBRATE, "%s: temperature %d\n",
3438 		    __func__, temp);
3439 
3440 		/* Update TX power if need be (4965AGN only). */
3441 		if (sc->hw_type == IWN_HW_REV_TYPE_4965)
3442 			iwn4965_power_calibration(sc, temp);
3443 	}
3444 
3445 	if (desc->type != IWN_BEACON_STATISTICS)
3446 		return;	/* Reply to a statistics request. */
3447 
3448 	sc->noise = iwn_get_noise(&lstats->rx.general);
3449 	DPRINTF(sc, IWN_DEBUG_CALIBRATE, "%s: noise %d\n", __func__, sc->noise);
3450 
3451 	/* Test that RSSI and noise are present in stats report. */
3452 	if (le32toh(lstats->rx.general.flags) != 1) {
3453 		DPRINTF(sc, IWN_DEBUG_ANY, "%s\n",
3454 		    "received statistics without RSSI");
3455 		return;
3456 	}
3457 
3458 	if (calib->state == IWN_CALIB_STATE_ASSOC)
3459 		iwn_collect_noise(sc, &lstats->rx.general);
3460 	else if (calib->state == IWN_CALIB_STATE_RUN) {
3461 		iwn_tune_sensitivity(sc, &lstats->rx);
3462 		/*
3463 		 * XXX TODO: Only run the RX recovery if we're associated!
3464 		 */
3465 		iwn_check_rx_recovery(sc, lstats);
3466 		iwn_save_stats_counters(sc, lstats);
3467 	}
3468 
3469 	DPRINTF(sc, IWN_DEBUG_TRACE, "->%s: end\n",__func__);
3470 }
3471 
3472 /*
3473  * Save the relevant statistic counters for the next calibration
3474  * pass.
3475  */
3476 static void
3477 iwn_save_stats_counters(struct iwn_softc *sc, const struct iwn_stats *rs)
3478 {
3479 	struct iwn_calib_state *calib = &sc->calib;
3480 
3481 	/* Save counters values for next call. */
3482 	calib->bad_plcp_cck = le32toh(rs->rx.cck.bad_plcp);
3483 	calib->fa_cck = le32toh(rs->rx.cck.fa);
3484 	calib->bad_plcp_ht = le32toh(rs->rx.ht.bad_plcp);
3485 	calib->bad_plcp_ofdm = le32toh(rs->rx.ofdm.bad_plcp);
3486 	calib->fa_ofdm = le32toh(rs->rx.ofdm.fa);
3487 
3488 	/* Last time we received these tick values */
3489 	sc->last_calib_ticks = ticks;
3490 }
3491 
3492 /*
3493  * Process a TX_DONE firmware notification.  Unfortunately, the 4965AGN
3494  * and 5000 adapters have different incompatible TX status formats.
3495  */
3496 static void
3497 iwn4965_tx_done(struct iwn_softc *sc, struct iwn_rx_desc *desc,
3498     struct iwn_rx_data *data)
3499 {
3500 	struct iwn4965_tx_stat *stat = (struct iwn4965_tx_stat *)(desc + 1);
3501 	struct iwn_tx_ring *ring;
3502 	int qid;
3503 
3504 	qid = desc->qid & 0xf;
3505 	ring = &sc->txq[qid];
3506 
3507 	DPRINTF(sc, IWN_DEBUG_XMIT, "%s: "
3508 	    "qid %d idx %d RTS retries %d ACK retries %d nkill %d rate %x duration %d status %x\n",
3509 	    __func__, desc->qid, desc->idx,
3510 	    stat->rtsfailcnt,
3511 	    stat->ackfailcnt,
3512 	    stat->btkillcnt,
3513 	    stat->rate, le16toh(stat->duration),
3514 	    le32toh(stat->status));
3515 
3516 	bus_dmamap_sync(ring->data_dmat, data->map, BUS_DMASYNC_POSTREAD);
3517 	if (qid >= sc->firstaggqueue) {
3518 		iwn_ampdu_tx_done(sc, qid, desc->idx, stat->nframes,
3519 		    stat->ackfailcnt, &stat->status);
3520 	} else {
3521 		iwn_tx_done(sc, desc, stat->ackfailcnt,
3522 		    le32toh(stat->status) & 0xff);
3523 	}
3524 }
3525 
3526 static void
3527 iwn5000_tx_done(struct iwn_softc *sc, struct iwn_rx_desc *desc,
3528     struct iwn_rx_data *data)
3529 {
3530 	struct iwn5000_tx_stat *stat = (struct iwn5000_tx_stat *)(desc + 1);
3531 	struct iwn_tx_ring *ring;
3532 	int qid;
3533 
3534 	qid = desc->qid & 0xf;
3535 	ring = &sc->txq[qid];
3536 
3537 	DPRINTF(sc, IWN_DEBUG_XMIT, "%s: "
3538 	    "qid %d idx %d RTS retries %d ACK retries %d nkill %d rate %x duration %d status %x\n",
3539 	    __func__, desc->qid, desc->idx,
3540 	    stat->rtsfailcnt,
3541 	    stat->ackfailcnt,
3542 	    stat->btkillcnt,
3543 	    stat->rate, le16toh(stat->duration),
3544 	    le32toh(stat->status));
3545 
3546 #ifdef notyet
3547 	/* Reset TX scheduler slot. */
3548 	iwn5000_reset_sched(sc, desc->qid & 0xf, desc->idx);
3549 #endif
3550 
3551 	bus_dmamap_sync(ring->data_dmat, data->map, BUS_DMASYNC_POSTREAD);
3552 	if (qid >= sc->firstaggqueue) {
3553 		iwn_ampdu_tx_done(sc, qid, desc->idx, stat->nframes,
3554 		    stat->ackfailcnt, &stat->status);
3555 	} else {
3556 		iwn_tx_done(sc, desc, stat->ackfailcnt,
3557 		    le16toh(stat->status) & 0xff);
3558 	}
3559 }
3560 
3561 /*
3562  * Adapter-independent backend for TX_DONE firmware notifications.
3563  */
3564 static void
3565 iwn_tx_done(struct iwn_softc *sc, struct iwn_rx_desc *desc, int ackfailcnt,
3566     uint8_t status)
3567 {
3568 	struct ifnet *ifp = sc->sc_ifp;
3569 	struct iwn_tx_ring *ring = &sc->txq[desc->qid & 0xf];
3570 	struct iwn_tx_data *data = &ring->data[desc->idx];
3571 	struct mbuf *m;
3572 	struct ieee80211_node *ni;
3573 	struct ieee80211vap *vap;
3574 
3575 	KASSERT(data->ni != NULL, ("no node"));
3576 
3577 	DPRINTF(sc, IWN_DEBUG_TRACE, "->%s begin\n", __func__);
3578 
3579 	/* Unmap and free mbuf. */
3580 	bus_dmamap_sync(ring->data_dmat, data->map, BUS_DMASYNC_POSTWRITE);
3581 	bus_dmamap_unload(ring->data_dmat, data->map);
3582 	m = data->m, data->m = NULL;
3583 	ni = data->ni, data->ni = NULL;
3584 	vap = ni->ni_vap;
3585 
3586 	/*
3587 	 * Update rate control statistics for the node.
3588 	 */
3589 	if (status & IWN_TX_FAIL) {
3590 		if_inc_counter(ifp, IFCOUNTER_OERRORS, 1);
3591 		ieee80211_ratectl_tx_complete(vap, ni,
3592 		    IEEE80211_RATECTL_TX_FAILURE, &ackfailcnt, NULL);
3593 	} else {
3594 		if_inc_counter(ifp, IFCOUNTER_OPACKETS, 1);
3595 		ieee80211_ratectl_tx_complete(vap, ni,
3596 		    IEEE80211_RATECTL_TX_SUCCESS, &ackfailcnt, NULL);
3597 	}
3598 
3599 	/*
3600 	 * Channels marked for "radar" require traffic to be received
3601 	 * to unlock before we can transmit.  Until traffic is seen
3602 	 * any attempt to transmit is returned immediately with status
3603 	 * set to IWN_TX_FAIL_TX_LOCKED.  Unfortunately this can easily
3604 	 * happen on first authenticate after scanning.  To workaround
3605 	 * this we ignore a failure of this sort in AUTH state so the
3606 	 * 802.11 layer will fall back to using a timeout to wait for
3607 	 * the AUTH reply.  This allows the firmware time to see
3608 	 * traffic so a subsequent retry of AUTH succeeds.  It's
3609 	 * unclear why the firmware does not maintain state for
3610 	 * channels recently visited as this would allow immediate
3611 	 * use of the channel after a scan (where we see traffic).
3612 	 */
3613 	if (status == IWN_TX_FAIL_TX_LOCKED &&
3614 	    ni->ni_vap->iv_state == IEEE80211_S_AUTH)
3615 		ieee80211_tx_complete(ni, m, 0);
3616 	else
3617 		ieee80211_tx_complete(ni, m,
3618 		    (status & IWN_TX_FAIL) != 0);
3619 
3620 	sc->sc_tx_timer = 0;
3621 	if (--ring->queued < IWN_TX_RING_LOMARK) {
3622 		sc->qfullmsk &= ~(1 << ring->qid);
3623 		if (sc->qfullmsk == 0 &&
3624 		    (ifp->if_drv_flags & IFF_DRV_OACTIVE)) {
3625 			ifp->if_drv_flags &= ~IFF_DRV_OACTIVE;
3626 			iwn_start_locked(ifp);
3627 		}
3628 	}
3629 
3630 	DPRINTF(sc, IWN_DEBUG_TRACE, "->%s: end\n",__func__);
3631 
3632 }
3633 
3634 /*
3635  * Process a "command done" firmware notification.  This is where we wakeup
3636  * processes waiting for a synchronous command completion.
3637  */
3638 static void
3639 iwn_cmd_done(struct iwn_softc *sc, struct iwn_rx_desc *desc)
3640 {
3641 	struct iwn_tx_ring *ring;
3642 	struct iwn_tx_data *data;
3643 	int cmd_queue_num;
3644 
3645 	if (sc->sc_flags & IWN_FLAG_PAN_SUPPORT)
3646 		cmd_queue_num = IWN_PAN_CMD_QUEUE;
3647 	else
3648 		cmd_queue_num = IWN_CMD_QUEUE_NUM;
3649 
3650 	if ((desc->qid & IWN_RX_DESC_QID_MSK) != cmd_queue_num)
3651 		return;	/* Not a command ack. */
3652 
3653 	ring = &sc->txq[cmd_queue_num];
3654 	data = &ring->data[desc->idx];
3655 
3656 	/* If the command was mapped in an mbuf, free it. */
3657 	if (data->m != NULL) {
3658 		bus_dmamap_sync(ring->data_dmat, data->map,
3659 		    BUS_DMASYNC_POSTWRITE);
3660 		bus_dmamap_unload(ring->data_dmat, data->map);
3661 		m_freem(data->m);
3662 		data->m = NULL;
3663 	}
3664 	wakeup(&ring->desc[desc->idx]);
3665 }
3666 
3667 static void
3668 iwn_ampdu_tx_done(struct iwn_softc *sc, int qid, int idx, int nframes,
3669     int ackfailcnt, void *stat)
3670 {
3671 	struct iwn_ops *ops = &sc->ops;
3672 	struct ifnet *ifp = sc->sc_ifp;
3673 	struct iwn_tx_ring *ring = &sc->txq[qid];
3674 	struct iwn_tx_data *data;
3675 	struct mbuf *m;
3676 	struct iwn_node *wn;
3677 	struct ieee80211_node *ni;
3678 	struct ieee80211_tx_ampdu *tap;
3679 	uint64_t bitmap;
3680 	uint32_t *status = stat;
3681 	uint16_t *aggstatus = stat;
3682 	uint16_t ssn;
3683 	uint8_t tid;
3684 	int bit, i, lastidx, *res, seqno, shift, start;
3685 
3686 	/* XXX TODO: status is le16 field! Grr */
3687 
3688 	DPRINTF(sc, IWN_DEBUG_TRACE, "->%s begin\n", __func__);
3689 	DPRINTF(sc, IWN_DEBUG_XMIT, "%s: nframes=%d, status=0x%08x\n",
3690 	    __func__,
3691 	    nframes,
3692 	    *status);
3693 
3694 	tap = sc->qid2tap[qid];
3695 	tid = tap->txa_tid;
3696 	wn = (void *)tap->txa_ni;
3697 	ni = tap->txa_ni;
3698 
3699 	/*
3700 	 * XXX TODO: ACK and RTS failures would be nice here!
3701 	 */
3702 
3703 	/*
3704 	 * A-MPDU single frame status - if we failed to transmit it
3705 	 * in A-MPDU, then it may be a permanent failure.
3706 	 *
3707 	 * XXX TODO: check what the Linux iwlwifi driver does here;
3708 	 * there's some permanent and temporary failures that may be
3709 	 * handled differently.
3710 	 */
3711 	if (nframes == 1) {
3712 		if ((*status & 0xff) != 1 && (*status & 0xff) != 2) {
3713 #ifdef	NOT_YET
3714 			printf("ieee80211_send_bar()\n");
3715 #endif
3716 			/*
3717 			 * If we completely fail a transmit, make sure a
3718 			 * notification is pushed up to the rate control
3719 			 * layer.
3720 			 */
3721 			ieee80211_ratectl_tx_complete(ni->ni_vap,
3722 			    ni,
3723 			    IEEE80211_RATECTL_TX_FAILURE,
3724 			    &ackfailcnt,
3725 			    NULL);
3726 		} else {
3727 			/*
3728 			 * If nframes=1, then we won't be getting a BA for
3729 			 * this frame.  Ensure that we correctly update the
3730 			 * rate control code with how many retries were
3731 			 * needed to send it.
3732 			 */
3733 			ieee80211_ratectl_tx_complete(ni->ni_vap,
3734 			    ni,
3735 			    IEEE80211_RATECTL_TX_SUCCESS,
3736 			    &ackfailcnt,
3737 			    NULL);
3738 		}
3739 	}
3740 
3741 	bitmap = 0;
3742 	start = idx;
3743 	for (i = 0; i < nframes; i++) {
3744 		if (le16toh(aggstatus[i * 2]) & 0xc)
3745 			continue;
3746 
3747 		idx = le16toh(aggstatus[2*i + 1]) & 0xff;
3748 		bit = idx - start;
3749 		shift = 0;
3750 		if (bit >= 64) {
3751 			shift = 0x100 - idx + start;
3752 			bit = 0;
3753 			start = idx;
3754 		} else if (bit <= -64)
3755 			bit = 0x100 - start + idx;
3756 		else if (bit < 0) {
3757 			shift = start - idx;
3758 			start = idx;
3759 			bit = 0;
3760 		}
3761 		bitmap = bitmap << shift;
3762 		bitmap |= 1ULL << bit;
3763 	}
3764 	tap = sc->qid2tap[qid];
3765 	tid = tap->txa_tid;
3766 	wn = (void *)tap->txa_ni;
3767 	wn->agg[tid].bitmap = bitmap;
3768 	wn->agg[tid].startidx = start;
3769 	wn->agg[tid].nframes = nframes;
3770 
3771 	res = NULL;
3772 	ssn = 0;
3773 	if (!IEEE80211_AMPDU_RUNNING(tap)) {
3774 		res = tap->txa_private;
3775 		ssn = tap->txa_start & 0xfff;
3776 	}
3777 
3778 	/* This is going nframes DWORDS into the descriptor? */
3779 	seqno = le32toh(*(status + nframes)) & 0xfff;
3780 	for (lastidx = (seqno & 0xff); ring->read != lastidx;) {
3781 		data = &ring->data[ring->read];
3782 
3783 		/* Unmap and free mbuf. */
3784 		bus_dmamap_sync(ring->data_dmat, data->map,
3785 		    BUS_DMASYNC_POSTWRITE);
3786 		bus_dmamap_unload(ring->data_dmat, data->map);
3787 		m = data->m, data->m = NULL;
3788 		ni = data->ni, data->ni = NULL;
3789 
3790 		KASSERT(ni != NULL, ("no node"));
3791 		KASSERT(m != NULL, ("no mbuf"));
3792 		DPRINTF(sc, IWN_DEBUG_XMIT, "%s: freeing m=%p\n", __func__, m);
3793 		ieee80211_tx_complete(ni, m, 1);
3794 
3795 		ring->queued--;
3796 		ring->read = (ring->read + 1) % IWN_TX_RING_COUNT;
3797 	}
3798 
3799 	if (ring->queued == 0 && res != NULL) {
3800 		iwn_nic_lock(sc);
3801 		ops->ampdu_tx_stop(sc, qid, tid, ssn);
3802 		iwn_nic_unlock(sc);
3803 		sc->qid2tap[qid] = NULL;
3804 		free(res, M_DEVBUF);
3805 		return;
3806 	}
3807 
3808 	sc->sc_tx_timer = 0;
3809 	if (ring->queued < IWN_TX_RING_LOMARK) {
3810 		sc->qfullmsk &= ~(1 << ring->qid);
3811 		if (sc->qfullmsk == 0 &&
3812 		    (ifp->if_drv_flags & IFF_DRV_OACTIVE)) {
3813 			ifp->if_drv_flags &= ~IFF_DRV_OACTIVE;
3814 			iwn_start_locked(ifp);
3815 		}
3816 	}
3817 
3818 	DPRINTF(sc, IWN_DEBUG_TRACE, "->%s: end\n",__func__);
3819 
3820 }
3821 
3822 /*
3823  * Process an INT_FH_RX or INT_SW_RX interrupt.
3824  */
3825 static void
3826 iwn_notif_intr(struct iwn_softc *sc)
3827 {
3828 	struct iwn_ops *ops = &sc->ops;
3829 	struct ifnet *ifp = sc->sc_ifp;
3830 	struct ieee80211com *ic = ifp->if_l2com;
3831 	struct ieee80211vap *vap = TAILQ_FIRST(&ic->ic_vaps);
3832 	uint16_t hw;
3833 
3834 	bus_dmamap_sync(sc->rxq.stat_dma.tag, sc->rxq.stat_dma.map,
3835 	    BUS_DMASYNC_POSTREAD);
3836 
3837 	hw = le16toh(sc->rxq.stat->closed_count) & 0xfff;
3838 	while (sc->rxq.cur != hw) {
3839 		struct iwn_rx_data *data = &sc->rxq.data[sc->rxq.cur];
3840 		struct iwn_rx_desc *desc;
3841 
3842 		bus_dmamap_sync(sc->rxq.data_dmat, data->map,
3843 		    BUS_DMASYNC_POSTREAD);
3844 		desc = mtod(data->m, struct iwn_rx_desc *);
3845 
3846 		DPRINTF(sc, IWN_DEBUG_RECV,
3847 		    "%s: cur=%d; qid %x idx %d flags %x type %d(%s) len %d\n",
3848 		    __func__, sc->rxq.cur, desc->qid & 0xf, desc->idx, desc->flags,
3849 		    desc->type, iwn_intr_str(desc->type),
3850 		    le16toh(desc->len));
3851 
3852 		if (!(desc->qid & IWN_UNSOLICITED_RX_NOTIF))	/* Reply to a command. */
3853 			iwn_cmd_done(sc, desc);
3854 
3855 		switch (desc->type) {
3856 		case IWN_RX_PHY:
3857 			iwn_rx_phy(sc, desc, data);
3858 			break;
3859 
3860 		case IWN_RX_DONE:		/* 4965AGN only. */
3861 		case IWN_MPDU_RX_DONE:
3862 			/* An 802.11 frame has been received. */
3863 			iwn_rx_done(sc, desc, data);
3864 			break;
3865 
3866 		case IWN_RX_COMPRESSED_BA:
3867 			/* A Compressed BlockAck has been received. */
3868 			iwn_rx_compressed_ba(sc, desc, data);
3869 			break;
3870 
3871 		case IWN_TX_DONE:
3872 			/* An 802.11 frame has been transmitted. */
3873 			ops->tx_done(sc, desc, data);
3874 			break;
3875 
3876 		case IWN_RX_STATISTICS:
3877 		case IWN_BEACON_STATISTICS:
3878 			iwn_rx_statistics(sc, desc, data);
3879 			break;
3880 
3881 		case IWN_BEACON_MISSED:
3882 		{
3883 			struct iwn_beacon_missed *miss =
3884 			    (struct iwn_beacon_missed *)(desc + 1);
3885 			int misses;
3886 
3887 			bus_dmamap_sync(sc->rxq.data_dmat, data->map,
3888 			    BUS_DMASYNC_POSTREAD);
3889 			misses = le32toh(miss->consecutive);
3890 
3891 			DPRINTF(sc, IWN_DEBUG_STATE,
3892 			    "%s: beacons missed %d/%d\n", __func__,
3893 			    misses, le32toh(miss->total));
3894 			/*
3895 			 * If more than 5 consecutive beacons are missed,
3896 			 * reinitialize the sensitivity state machine.
3897 			 */
3898 			if (vap->iv_state == IEEE80211_S_RUN &&
3899 			    (ic->ic_flags & IEEE80211_F_SCAN) == 0) {
3900 				if (misses > 5)
3901 					(void)iwn_init_sensitivity(sc);
3902 				if (misses >= vap->iv_bmissthreshold) {
3903 					IWN_UNLOCK(sc);
3904 					ieee80211_beacon_miss(ic);
3905 					IWN_LOCK(sc);
3906 				}
3907 			}
3908 			break;
3909 		}
3910 		case IWN_UC_READY:
3911 		{
3912 			struct iwn_ucode_info *uc =
3913 			    (struct iwn_ucode_info *)(desc + 1);
3914 
3915 			/* The microcontroller is ready. */
3916 			bus_dmamap_sync(sc->rxq.data_dmat, data->map,
3917 			    BUS_DMASYNC_POSTREAD);
3918 			DPRINTF(sc, IWN_DEBUG_RESET,
3919 			    "microcode alive notification version=%d.%d "
3920 			    "subtype=%x alive=%x\n", uc->major, uc->minor,
3921 			    uc->subtype, le32toh(uc->valid));
3922 
3923 			if (le32toh(uc->valid) != 1) {
3924 				device_printf(sc->sc_dev,
3925 				    "microcontroller initialization failed");
3926 				break;
3927 			}
3928 			if (uc->subtype == IWN_UCODE_INIT) {
3929 				/* Save microcontroller report. */
3930 				memcpy(&sc->ucode_info, uc, sizeof (*uc));
3931 			}
3932 			/* Save the address of the error log in SRAM. */
3933 			sc->errptr = le32toh(uc->errptr);
3934 			break;
3935 		}
3936 		case IWN_STATE_CHANGED:
3937 		{
3938 			/*
3939 			 * State change allows hardware switch change to be
3940 			 * noted. However, we handle this in iwn_intr as we
3941 			 * get both the enable/disble intr.
3942 			 */
3943 			bus_dmamap_sync(sc->rxq.data_dmat, data->map,
3944 			    BUS_DMASYNC_POSTREAD);
3945 #ifdef	IWN_DEBUG
3946 			uint32_t *status = (uint32_t *)(desc + 1);
3947 			DPRINTF(sc, IWN_DEBUG_INTR | IWN_DEBUG_STATE,
3948 			    "state changed to %x\n",
3949 			    le32toh(*status));
3950 #endif
3951 			break;
3952 		}
3953 		case IWN_START_SCAN:
3954 		{
3955 			bus_dmamap_sync(sc->rxq.data_dmat, data->map,
3956 			    BUS_DMASYNC_POSTREAD);
3957 #ifdef	IWN_DEBUG
3958 			struct iwn_start_scan *scan =
3959 			    (struct iwn_start_scan *)(desc + 1);
3960 			DPRINTF(sc, IWN_DEBUG_ANY,
3961 			    "%s: scanning channel %d status %x\n",
3962 			    __func__, scan->chan, le32toh(scan->status));
3963 #endif
3964 			break;
3965 		}
3966 		case IWN_STOP_SCAN:
3967 		{
3968 			bus_dmamap_sync(sc->rxq.data_dmat, data->map,
3969 			    BUS_DMASYNC_POSTREAD);
3970 #ifdef	IWN_DEBUG
3971 			struct iwn_stop_scan *scan =
3972 			    (struct iwn_stop_scan *)(desc + 1);
3973 			DPRINTF(sc, IWN_DEBUG_STATE | IWN_DEBUG_SCAN,
3974 			    "scan finished nchan=%d status=%d chan=%d\n",
3975 			    scan->nchan, scan->status, scan->chan);
3976 #endif
3977 			sc->sc_is_scanning = 0;
3978 			IWN_UNLOCK(sc);
3979 			ieee80211_scan_next(vap);
3980 			IWN_LOCK(sc);
3981 			break;
3982 		}
3983 		case IWN5000_CALIBRATION_RESULT:
3984 			iwn5000_rx_calib_results(sc, desc, data);
3985 			break;
3986 
3987 		case IWN5000_CALIBRATION_DONE:
3988 			sc->sc_flags |= IWN_FLAG_CALIB_DONE;
3989 			wakeup(sc);
3990 			break;
3991 		}
3992 
3993 		sc->rxq.cur = (sc->rxq.cur + 1) % IWN_RX_RING_COUNT;
3994 	}
3995 
3996 	/* Tell the firmware what we have processed. */
3997 	hw = (hw == 0) ? IWN_RX_RING_COUNT - 1 : hw - 1;
3998 	IWN_WRITE(sc, IWN_FH_RX_WPTR, hw & ~7);
3999 }
4000 
4001 /*
4002  * Process an INT_WAKEUP interrupt raised when the microcontroller wakes up
4003  * from power-down sleep mode.
4004  */
4005 static void
4006 iwn_wakeup_intr(struct iwn_softc *sc)
4007 {
4008 	int qid;
4009 
4010 	DPRINTF(sc, IWN_DEBUG_RESET, "%s: ucode wakeup from power-down sleep\n",
4011 	    __func__);
4012 
4013 	/* Wakeup RX and TX rings. */
4014 	IWN_WRITE(sc, IWN_FH_RX_WPTR, sc->rxq.cur & ~7);
4015 	for (qid = 0; qid < sc->ntxqs; qid++) {
4016 		struct iwn_tx_ring *ring = &sc->txq[qid];
4017 		IWN_WRITE(sc, IWN_HBUS_TARG_WRPTR, qid << 8 | ring->cur);
4018 	}
4019 }
4020 
4021 static void
4022 iwn_rftoggle_intr(struct iwn_softc *sc)
4023 {
4024 	struct ifnet *ifp = sc->sc_ifp;
4025 	struct ieee80211com *ic = ifp->if_l2com;
4026 	uint32_t tmp = IWN_READ(sc, IWN_GP_CNTRL);
4027 
4028 	IWN_LOCK_ASSERT(sc);
4029 
4030 	device_printf(sc->sc_dev, "RF switch: radio %s\n",
4031 	    (tmp & IWN_GP_CNTRL_RFKILL) ? "enabled" : "disabled");
4032 	if (tmp & IWN_GP_CNTRL_RFKILL)
4033 		ieee80211_runtask(ic, &sc->sc_radioon_task);
4034 	else
4035 		ieee80211_runtask(ic, &sc->sc_radiooff_task);
4036 }
4037 
4038 /*
4039  * Dump the error log of the firmware when a firmware panic occurs.  Although
4040  * we can't debug the firmware because it is neither open source nor free, it
4041  * can help us to identify certain classes of problems.
4042  */
4043 static void
4044 iwn_fatal_intr(struct iwn_softc *sc)
4045 {
4046 	struct iwn_fw_dump dump;
4047 	int i;
4048 
4049 	IWN_LOCK_ASSERT(sc);
4050 
4051 	/* Force a complete recalibration on next init. */
4052 	sc->sc_flags &= ~IWN_FLAG_CALIB_DONE;
4053 
4054 	/* Check that the error log address is valid. */
4055 	if (sc->errptr < IWN_FW_DATA_BASE ||
4056 	    sc->errptr + sizeof (dump) >
4057 	    IWN_FW_DATA_BASE + sc->fw_data_maxsz) {
4058 		printf("%s: bad firmware error log address 0x%08x\n", __func__,
4059 		    sc->errptr);
4060 		return;
4061 	}
4062 	if (iwn_nic_lock(sc) != 0) {
4063 		printf("%s: could not read firmware error log\n", __func__);
4064 		return;
4065 	}
4066 	/* Read firmware error log from SRAM. */
4067 	iwn_mem_read_region_4(sc, sc->errptr, (uint32_t *)&dump,
4068 	    sizeof (dump) / sizeof (uint32_t));
4069 	iwn_nic_unlock(sc);
4070 
4071 	if (dump.valid == 0) {
4072 		printf("%s: firmware error log is empty\n", __func__);
4073 		return;
4074 	}
4075 	printf("firmware error log:\n");
4076 	printf("  error type      = \"%s\" (0x%08X)\n",
4077 	    (dump.id < nitems(iwn_fw_errmsg)) ?
4078 		iwn_fw_errmsg[dump.id] : "UNKNOWN",
4079 	    dump.id);
4080 	printf("  program counter = 0x%08X\n", dump.pc);
4081 	printf("  source line     = 0x%08X\n", dump.src_line);
4082 	printf("  error data      = 0x%08X%08X\n",
4083 	    dump.error_data[0], dump.error_data[1]);
4084 	printf("  branch link     = 0x%08X%08X\n",
4085 	    dump.branch_link[0], dump.branch_link[1]);
4086 	printf("  interrupt link  = 0x%08X%08X\n",
4087 	    dump.interrupt_link[0], dump.interrupt_link[1]);
4088 	printf("  time            = %u\n", dump.time[0]);
4089 
4090 	/* Dump driver status (TX and RX rings) while we're here. */
4091 	printf("driver status:\n");
4092 	for (i = 0; i < sc->ntxqs; i++) {
4093 		struct iwn_tx_ring *ring = &sc->txq[i];
4094 		printf("  tx ring %2d: qid=%-2d cur=%-3d queued=%-3d\n",
4095 		    i, ring->qid, ring->cur, ring->queued);
4096 	}
4097 	printf("  rx ring: cur=%d\n", sc->rxq.cur);
4098 }
4099 
4100 static void
4101 iwn_intr(void *arg)
4102 {
4103 	struct iwn_softc *sc = arg;
4104 	struct ifnet *ifp = sc->sc_ifp;
4105 	uint32_t r1, r2, tmp;
4106 
4107 	IWN_LOCK(sc);
4108 
4109 	/* Disable interrupts. */
4110 	IWN_WRITE(sc, IWN_INT_MASK, 0);
4111 
4112 	/* Read interrupts from ICT (fast) or from registers (slow). */
4113 	if (sc->sc_flags & IWN_FLAG_USE_ICT) {
4114 		tmp = 0;
4115 		while (sc->ict[sc->ict_cur] != 0) {
4116 			tmp |= sc->ict[sc->ict_cur];
4117 			sc->ict[sc->ict_cur] = 0;	/* Acknowledge. */
4118 			sc->ict_cur = (sc->ict_cur + 1) % IWN_ICT_COUNT;
4119 		}
4120 		tmp = le32toh(tmp);
4121 		if (tmp == 0xffffffff)	/* Shouldn't happen. */
4122 			tmp = 0;
4123 		else if (tmp & 0xc0000)	/* Workaround a HW bug. */
4124 			tmp |= 0x8000;
4125 		r1 = (tmp & 0xff00) << 16 | (tmp & 0xff);
4126 		r2 = 0;	/* Unused. */
4127 	} else {
4128 		r1 = IWN_READ(sc, IWN_INT);
4129 		if (r1 == 0xffffffff || (r1 & 0xfffffff0) == 0xa5a5a5a0) {
4130 			IWN_UNLOCK(sc);
4131 			return;	/* Hardware gone! */
4132 		}
4133 		r2 = IWN_READ(sc, IWN_FH_INT);
4134 	}
4135 
4136 	DPRINTF(sc, IWN_DEBUG_INTR, "interrupt reg1=0x%08x reg2=0x%08x\n"
4137     , r1, r2);
4138 
4139 	if (r1 == 0 && r2 == 0)
4140 		goto done;	/* Interrupt not for us. */
4141 
4142 	/* Acknowledge interrupts. */
4143 	IWN_WRITE(sc, IWN_INT, r1);
4144 	if (!(sc->sc_flags & IWN_FLAG_USE_ICT))
4145 		IWN_WRITE(sc, IWN_FH_INT, r2);
4146 
4147 	if (r1 & IWN_INT_RF_TOGGLED) {
4148 		iwn_rftoggle_intr(sc);
4149 		goto done;
4150 	}
4151 	if (r1 & IWN_INT_CT_REACHED) {
4152 		device_printf(sc->sc_dev, "%s: critical temperature reached!\n",
4153 		    __func__);
4154 	}
4155 	if (r1 & (IWN_INT_SW_ERR | IWN_INT_HW_ERR)) {
4156 		device_printf(sc->sc_dev, "%s: fatal firmware error\n",
4157 		    __func__);
4158 #ifdef	IWN_DEBUG
4159 		iwn_debug_register(sc);
4160 #endif
4161 		/* Dump firmware error log and stop. */
4162 		iwn_fatal_intr(sc);
4163 
4164 		taskqueue_enqueue(sc->sc_tq, &sc->sc_panic_task);
4165 		goto done;
4166 	}
4167 	if ((r1 & (IWN_INT_FH_RX | IWN_INT_SW_RX | IWN_INT_RX_PERIODIC)) ||
4168 	    (r2 & IWN_FH_INT_RX)) {
4169 		if (sc->sc_flags & IWN_FLAG_USE_ICT) {
4170 			if (r1 & (IWN_INT_FH_RX | IWN_INT_SW_RX))
4171 				IWN_WRITE(sc, IWN_FH_INT, IWN_FH_INT_RX);
4172 			IWN_WRITE_1(sc, IWN_INT_PERIODIC,
4173 			    IWN_INT_PERIODIC_DIS);
4174 			iwn_notif_intr(sc);
4175 			if (r1 & (IWN_INT_FH_RX | IWN_INT_SW_RX)) {
4176 				IWN_WRITE_1(sc, IWN_INT_PERIODIC,
4177 				    IWN_INT_PERIODIC_ENA);
4178 			}
4179 		} else
4180 			iwn_notif_intr(sc);
4181 	}
4182 
4183 	if ((r1 & IWN_INT_FH_TX) || (r2 & IWN_FH_INT_TX)) {
4184 		if (sc->sc_flags & IWN_FLAG_USE_ICT)
4185 			IWN_WRITE(sc, IWN_FH_INT, IWN_FH_INT_TX);
4186 		wakeup(sc);	/* FH DMA transfer completed. */
4187 	}
4188 
4189 	if (r1 & IWN_INT_ALIVE)
4190 		wakeup(sc);	/* Firmware is alive. */
4191 
4192 	if (r1 & IWN_INT_WAKEUP)
4193 		iwn_wakeup_intr(sc);
4194 
4195 done:
4196 	/* Re-enable interrupts. */
4197 	if (ifp->if_flags & IFF_UP)
4198 		IWN_WRITE(sc, IWN_INT_MASK, sc->int_mask);
4199 
4200 	IWN_UNLOCK(sc);
4201 }
4202 
4203 /*
4204  * Update TX scheduler ring when transmitting an 802.11 frame (4965AGN and
4205  * 5000 adapters use a slightly different format).
4206  */
4207 static void
4208 iwn4965_update_sched(struct iwn_softc *sc, int qid, int idx, uint8_t id,
4209     uint16_t len)
4210 {
4211 	uint16_t *w = &sc->sched[qid * IWN4965_SCHED_COUNT + idx];
4212 
4213 	DPRINTF(sc, IWN_DEBUG_TRACE, "->Doing %s\n", __func__);
4214 
4215 	*w = htole16(len + 8);
4216 	bus_dmamap_sync(sc->sched_dma.tag, sc->sched_dma.map,
4217 	    BUS_DMASYNC_PREWRITE);
4218 	if (idx < IWN_SCHED_WINSZ) {
4219 		*(w + IWN_TX_RING_COUNT) = *w;
4220 		bus_dmamap_sync(sc->sched_dma.tag, sc->sched_dma.map,
4221 		    BUS_DMASYNC_PREWRITE);
4222 	}
4223 }
4224 
4225 static void
4226 iwn5000_update_sched(struct iwn_softc *sc, int qid, int idx, uint8_t id,
4227     uint16_t len)
4228 {
4229 	uint16_t *w = &sc->sched[qid * IWN5000_SCHED_COUNT + idx];
4230 
4231 	DPRINTF(sc, IWN_DEBUG_TRACE, "->Doing %s\n", __func__);
4232 
4233 	*w = htole16(id << 12 | (len + 8));
4234 	bus_dmamap_sync(sc->sched_dma.tag, sc->sched_dma.map,
4235 	    BUS_DMASYNC_PREWRITE);
4236 	if (idx < IWN_SCHED_WINSZ) {
4237 		*(w + IWN_TX_RING_COUNT) = *w;
4238 		bus_dmamap_sync(sc->sched_dma.tag, sc->sched_dma.map,
4239 		    BUS_DMASYNC_PREWRITE);
4240 	}
4241 }
4242 
4243 #ifdef notyet
4244 static void
4245 iwn5000_reset_sched(struct iwn_softc *sc, int qid, int idx)
4246 {
4247 	uint16_t *w = &sc->sched[qid * IWN5000_SCHED_COUNT + idx];
4248 
4249 	DPRINTF(sc, IWN_DEBUG_TRACE, "->Doing %s\n", __func__);
4250 
4251 	*w = (*w & htole16(0xf000)) | htole16(1);
4252 	bus_dmamap_sync(sc->sched_dma.tag, sc->sched_dma.map,
4253 	    BUS_DMASYNC_PREWRITE);
4254 	if (idx < IWN_SCHED_WINSZ) {
4255 		*(w + IWN_TX_RING_COUNT) = *w;
4256 		bus_dmamap_sync(sc->sched_dma.tag, sc->sched_dma.map,
4257 		    BUS_DMASYNC_PREWRITE);
4258 	}
4259 }
4260 #endif
4261 
4262 /*
4263  * Check whether OFDM 11g protection will be enabled for the given rate.
4264  *
4265  * The original driver code only enabled protection for OFDM rates.
4266  * It didn't check to see whether it was operating in 11a or 11bg mode.
4267  */
4268 static int
4269 iwn_check_rate_needs_protection(struct iwn_softc *sc,
4270     struct ieee80211vap *vap, uint8_t rate)
4271 {
4272 	struct ieee80211com *ic = vap->iv_ic;
4273 
4274 	/*
4275 	 * Not in 2GHz mode? Then there's no need to enable OFDM
4276 	 * 11bg protection.
4277 	 */
4278 	if (! IEEE80211_IS_CHAN_2GHZ(ic->ic_curchan)) {
4279 		return (0);
4280 	}
4281 
4282 	/*
4283 	 * 11bg protection not enabled? Then don't use it.
4284 	 */
4285 	if ((ic->ic_flags & IEEE80211_F_USEPROT) == 0)
4286 		return (0);
4287 
4288 	/*
4289 	 * If it's an 11n rate - no protection.
4290 	 * We'll do it via a specific 11n check.
4291 	 */
4292 	if (rate & IEEE80211_RATE_MCS) {
4293 		return (0);
4294 	}
4295 
4296 	/*
4297 	 * Do a rate table lookup.  If the PHY is CCK,
4298 	 * don't do protection.
4299 	 */
4300 	if (ieee80211_rate2phytype(ic->ic_rt, rate) == IEEE80211_T_CCK)
4301 		return (0);
4302 
4303 	/*
4304 	 * Yup, enable protection.
4305 	 */
4306 	return (1);
4307 }
4308 
4309 /*
4310  * return a value between 0 and IWN_MAX_TX_RETRIES-1 as an index into
4311  * the link quality table that reflects this particular entry.
4312  */
4313 static int
4314 iwn_tx_rate_to_linkq_offset(struct iwn_softc *sc, struct ieee80211_node *ni,
4315     uint8_t rate)
4316 {
4317 	struct ieee80211_rateset *rs;
4318 	int is_11n;
4319 	int nr;
4320 	int i;
4321 	uint8_t cmp_rate;
4322 
4323 	/*
4324 	 * Figure out if we're using 11n or not here.
4325 	 */
4326 	if (IEEE80211_IS_CHAN_HT(ni->ni_chan) && ni->ni_htrates.rs_nrates > 0)
4327 		is_11n = 1;
4328 	else
4329 		is_11n = 0;
4330 
4331 	/*
4332 	 * Use the correct rate table.
4333 	 */
4334 	if (is_11n) {
4335 		rs = (struct ieee80211_rateset *) &ni->ni_htrates;
4336 		nr = ni->ni_htrates.rs_nrates;
4337 	} else {
4338 		rs = &ni->ni_rates;
4339 		nr = rs->rs_nrates;
4340 	}
4341 
4342 	/*
4343 	 * Find the relevant link quality entry in the table.
4344 	 */
4345 	for (i = 0; i < nr && i < IWN_MAX_TX_RETRIES - 1 ; i++) {
4346 		/*
4347 		 * The link quality table index starts at 0 == highest
4348 		 * rate, so we walk the rate table backwards.
4349 		 */
4350 		cmp_rate = rs->rs_rates[(nr - 1) - i];
4351 		if (rate & IEEE80211_RATE_MCS)
4352 			cmp_rate |= IEEE80211_RATE_MCS;
4353 
4354 #if 0
4355 		DPRINTF(sc, IWN_DEBUG_XMIT, "%s: idx %d: nr=%d, rate=0x%02x, rateentry=0x%02x\n",
4356 		    __func__,
4357 		    i,
4358 		    nr,
4359 		    rate,
4360 		    cmp_rate);
4361 #endif
4362 
4363 		if (cmp_rate == rate)
4364 			return (i);
4365 	}
4366 
4367 	/* Failed? Start at the end */
4368 	return (IWN_MAX_TX_RETRIES - 1);
4369 }
4370 
4371 static int
4372 iwn_tx_data(struct iwn_softc *sc, struct mbuf *m, struct ieee80211_node *ni)
4373 {
4374 	struct iwn_ops *ops = &sc->ops;
4375 	const struct ieee80211_txparam *tp;
4376 	struct ieee80211vap *vap = ni->ni_vap;
4377 	struct ieee80211com *ic = ni->ni_ic;
4378 	struct iwn_node *wn = (void *)ni;
4379 	struct iwn_tx_ring *ring;
4380 	struct iwn_tx_desc *desc;
4381 	struct iwn_tx_data *data;
4382 	struct iwn_tx_cmd *cmd;
4383 	struct iwn_cmd_data *tx;
4384 	struct ieee80211_frame *wh;
4385 	struct ieee80211_key *k = NULL;
4386 	struct mbuf *m1;
4387 	uint32_t flags;
4388 	uint16_t qos;
4389 	u_int hdrlen;
4390 	bus_dma_segment_t *seg, segs[IWN_MAX_SCATTER];
4391 	uint8_t tid, type;
4392 	int ac, i, totlen, error, pad, nsegs = 0, rate;
4393 
4394 	DPRINTF(sc, IWN_DEBUG_TRACE, "->%s begin\n", __func__);
4395 
4396 	IWN_LOCK_ASSERT(sc);
4397 
4398 	wh = mtod(m, struct ieee80211_frame *);
4399 	hdrlen = ieee80211_anyhdrsize(wh);
4400 	type = wh->i_fc[0] & IEEE80211_FC0_TYPE_MASK;
4401 
4402 	/* Select EDCA Access Category and TX ring for this frame. */
4403 	if (IEEE80211_QOS_HAS_SEQ(wh)) {
4404 		qos = ((const struct ieee80211_qosframe *)wh)->i_qos[0];
4405 		tid = qos & IEEE80211_QOS_TID;
4406 	} else {
4407 		qos = 0;
4408 		tid = 0;
4409 	}
4410 	ac = M_WME_GETAC(m);
4411 	if (m->m_flags & M_AMPDU_MPDU) {
4412 		uint16_t seqno;
4413 		struct ieee80211_tx_ampdu *tap = &ni->ni_tx_ampdu[ac];
4414 
4415 		if (!IEEE80211_AMPDU_RUNNING(tap)) {
4416 			m_freem(m);
4417 			return EINVAL;
4418 		}
4419 
4420 		/*
4421 		 * Queue this frame to the hardware ring that we've
4422 		 * negotiated AMPDU TX on.
4423 		 *
4424 		 * Note that the sequence number must match the TX slot
4425 		 * being used!
4426 		 */
4427 		ac = *(int *)tap->txa_private;
4428 		seqno = ni->ni_txseqs[tid];
4429 		*(uint16_t *)wh->i_seq =
4430 		    htole16(seqno << IEEE80211_SEQ_SEQ_SHIFT);
4431 		ring = &sc->txq[ac];
4432 		if ((seqno % 256) != ring->cur) {
4433 			device_printf(sc->sc_dev,
4434 			    "%s: m=%p: seqno (%d) (%d) != ring index (%d) !\n",
4435 			    __func__,
4436 			    m,
4437 			    seqno,
4438 			    seqno % 256,
4439 			    ring->cur);
4440 		}
4441 		ni->ni_txseqs[tid]++;
4442 	}
4443 	ring = &sc->txq[ac];
4444 	desc = &ring->desc[ring->cur];
4445 	data = &ring->data[ring->cur];
4446 
4447 	/* Choose a TX rate index. */
4448 	tp = &vap->iv_txparms[ieee80211_chan2mode(ni->ni_chan)];
4449 	if (type == IEEE80211_FC0_TYPE_MGT)
4450 		rate = tp->mgmtrate;
4451 	else if (IEEE80211_IS_MULTICAST(wh->i_addr1))
4452 		rate = tp->mcastrate;
4453 	else if (tp->ucastrate != IEEE80211_FIXED_RATE_NONE)
4454 		rate = tp->ucastrate;
4455 	else if (m->m_flags & M_EAPOL)
4456 		rate = tp->mgmtrate;
4457 	else {
4458 		/* XXX pass pktlen */
4459 		(void) ieee80211_ratectl_rate(ni, NULL, 0);
4460 		rate = ni->ni_txrate;
4461 	}
4462 
4463 	/* Encrypt the frame if need be. */
4464 	if (wh->i_fc[1] & IEEE80211_FC1_PROTECTED) {
4465 		/* Retrieve key for TX. */
4466 		k = ieee80211_crypto_encap(ni, m);
4467 		if (k == NULL) {
4468 			m_freem(m);
4469 			return ENOBUFS;
4470 		}
4471 		/* 802.11 header may have moved. */
4472 		wh = mtod(m, struct ieee80211_frame *);
4473 	}
4474 	totlen = m->m_pkthdr.len;
4475 
4476 	if (ieee80211_radiotap_active_vap(vap)) {
4477 		struct iwn_tx_radiotap_header *tap = &sc->sc_txtap;
4478 
4479 		tap->wt_flags = 0;
4480 		tap->wt_rate = rate;
4481 		if (k != NULL)
4482 			tap->wt_flags |= IEEE80211_RADIOTAP_F_WEP;
4483 
4484 		ieee80211_radiotap_tx(vap, m);
4485 	}
4486 
4487 	/* Prepare TX firmware command. */
4488 	cmd = &ring->cmd[ring->cur];
4489 	cmd->code = IWN_CMD_TX_DATA;
4490 	cmd->flags = 0;
4491 	cmd->qid = ring->qid;
4492 	cmd->idx = ring->cur;
4493 
4494 	tx = (struct iwn_cmd_data *)cmd->data;
4495 	/* NB: No need to clear tx, all fields are reinitialized here. */
4496 	tx->scratch = 0;	/* clear "scratch" area */
4497 
4498 	flags = 0;
4499 	if (!IEEE80211_IS_MULTICAST(wh->i_addr1)) {
4500 		/* Unicast frame, check if an ACK is expected. */
4501 		if (!qos || (qos & IEEE80211_QOS_ACKPOLICY) !=
4502 		    IEEE80211_QOS_ACKPOLICY_NOACK)
4503 			flags |= IWN_TX_NEED_ACK;
4504 	}
4505 	if ((wh->i_fc[0] &
4506 	    (IEEE80211_FC0_TYPE_MASK | IEEE80211_FC0_SUBTYPE_MASK)) ==
4507 	    (IEEE80211_FC0_TYPE_CTL | IEEE80211_FC0_SUBTYPE_BAR))
4508 		flags |= IWN_TX_IMM_BA;		/* Cannot happen yet. */
4509 
4510 	if (wh->i_fc[1] & IEEE80211_FC1_MORE_FRAG)
4511 		flags |= IWN_TX_MORE_FRAG;	/* Cannot happen yet. */
4512 
4513 	/* Check if frame must be protected using RTS/CTS or CTS-to-self. */
4514 	if (!IEEE80211_IS_MULTICAST(wh->i_addr1)) {
4515 		/* NB: Group frames are sent using CCK in 802.11b/g. */
4516 		if (totlen + IEEE80211_CRC_LEN > vap->iv_rtsthreshold) {
4517 			flags |= IWN_TX_NEED_RTS;
4518 		} else if (iwn_check_rate_needs_protection(sc, vap, rate)) {
4519 			if (ic->ic_protmode == IEEE80211_PROT_CTSONLY)
4520 				flags |= IWN_TX_NEED_CTS;
4521 			else if (ic->ic_protmode == IEEE80211_PROT_RTSCTS)
4522 				flags |= IWN_TX_NEED_RTS;
4523 		} else if ((rate & IEEE80211_RATE_MCS) &&
4524 			(ic->ic_htprotmode == IEEE80211_PROT_RTSCTS)) {
4525 			flags |= IWN_TX_NEED_RTS;
4526 		}
4527 
4528 		/* XXX HT protection? */
4529 
4530 		if (flags & (IWN_TX_NEED_RTS | IWN_TX_NEED_CTS)) {
4531 			if (sc->hw_type != IWN_HW_REV_TYPE_4965) {
4532 				/* 5000 autoselects RTS/CTS or CTS-to-self. */
4533 				flags &= ~(IWN_TX_NEED_RTS | IWN_TX_NEED_CTS);
4534 				flags |= IWN_TX_NEED_PROTECTION;
4535 			} else
4536 				flags |= IWN_TX_FULL_TXOP;
4537 		}
4538 	}
4539 
4540 	if (IEEE80211_IS_MULTICAST(wh->i_addr1) ||
4541 	    type != IEEE80211_FC0_TYPE_DATA)
4542 		tx->id = sc->broadcast_id;
4543 	else
4544 		tx->id = wn->id;
4545 
4546 	if (type == IEEE80211_FC0_TYPE_MGT) {
4547 		uint8_t subtype = wh->i_fc[0] & IEEE80211_FC0_SUBTYPE_MASK;
4548 
4549 		/* Tell HW to set timestamp in probe responses. */
4550 		if (subtype == IEEE80211_FC0_SUBTYPE_PROBE_RESP)
4551 			flags |= IWN_TX_INSERT_TSTAMP;
4552 		if (subtype == IEEE80211_FC0_SUBTYPE_ASSOC_REQ ||
4553 		    subtype == IEEE80211_FC0_SUBTYPE_REASSOC_REQ)
4554 			tx->timeout = htole16(3);
4555 		else
4556 			tx->timeout = htole16(2);
4557 	} else
4558 		tx->timeout = htole16(0);
4559 
4560 	if (hdrlen & 3) {
4561 		/* First segment length must be a multiple of 4. */
4562 		flags |= IWN_TX_NEED_PADDING;
4563 		pad = 4 - (hdrlen & 3);
4564 	} else
4565 		pad = 0;
4566 
4567 	tx->len = htole16(totlen);
4568 	tx->tid = tid;
4569 	tx->rts_ntries = 60;
4570 	tx->data_ntries = 15;
4571 	tx->lifetime = htole32(IWN_LIFETIME_INFINITE);
4572 	tx->rate = iwn_rate_to_plcp(sc, ni, rate);
4573 	if (tx->id == sc->broadcast_id) {
4574 		/* Group or management frame. */
4575 		tx->linkq = 0;
4576 	} else {
4577 		tx->linkq = iwn_tx_rate_to_linkq_offset(sc, ni, rate);
4578 		flags |= IWN_TX_LINKQ;	/* enable MRR */
4579 	}
4580 
4581 	/* Set physical address of "scratch area". */
4582 	tx->loaddr = htole32(IWN_LOADDR(data->scratch_paddr));
4583 	tx->hiaddr = IWN_HIADDR(data->scratch_paddr);
4584 
4585 	/* Copy 802.11 header in TX command. */
4586 	memcpy((uint8_t *)(tx + 1), wh, hdrlen);
4587 
4588 	/* Trim 802.11 header. */
4589 	m_adj(m, hdrlen);
4590 	tx->security = 0;
4591 	tx->flags = htole32(flags);
4592 
4593 	error = bus_dmamap_load_mbuf_sg(ring->data_dmat, data->map, m, segs,
4594 	    &nsegs, BUS_DMA_NOWAIT);
4595 	if (error != 0) {
4596 		if (error != EFBIG) {
4597 			device_printf(sc->sc_dev,
4598 			    "%s: can't map mbuf (error %d)\n", __func__, error);
4599 			m_freem(m);
4600 			return error;
4601 		}
4602 		/* Too many DMA segments, linearize mbuf. */
4603 		m1 = m_collapse(m, M_NOWAIT, IWN_MAX_SCATTER - 1);
4604 		if (m1 == NULL) {
4605 			device_printf(sc->sc_dev,
4606 			    "%s: could not defrag mbuf\n", __func__);
4607 			m_freem(m);
4608 			return ENOBUFS;
4609 		}
4610 		m = m1;
4611 
4612 		error = bus_dmamap_load_mbuf_sg(ring->data_dmat, data->map, m,
4613 		    segs, &nsegs, BUS_DMA_NOWAIT);
4614 		if (error != 0) {
4615 			device_printf(sc->sc_dev,
4616 			    "%s: can't map mbuf (error %d)\n", __func__, error);
4617 			m_freem(m);
4618 			return error;
4619 		}
4620 	}
4621 
4622 	data->m = m;
4623 	data->ni = ni;
4624 
4625 	DPRINTF(sc, IWN_DEBUG_XMIT,
4626 	    "%s: qid %d idx %d len %d nsegs %d flags 0x%08x rate 0x%04x plcp 0x%08x\n",
4627 	    __func__,
4628 	    ring->qid,
4629 	    ring->cur,
4630 	    m->m_pkthdr.len,
4631 	    nsegs,
4632 	    flags,
4633 	    rate,
4634 	    tx->rate);
4635 
4636 	/* Fill TX descriptor. */
4637 	desc->nsegs = 1;
4638 	if (m->m_len != 0)
4639 		desc->nsegs += nsegs;
4640 	/* First DMA segment is used by the TX command. */
4641 	desc->segs[0].addr = htole32(IWN_LOADDR(data->cmd_paddr));
4642 	desc->segs[0].len  = htole16(IWN_HIADDR(data->cmd_paddr) |
4643 	    (4 + sizeof (*tx) + hdrlen + pad) << 4);
4644 	/* Other DMA segments are for data payload. */
4645 	seg = &segs[0];
4646 	for (i = 1; i <= nsegs; i++) {
4647 		desc->segs[i].addr = htole32(IWN_LOADDR(seg->ds_addr));
4648 		desc->segs[i].len  = htole16(IWN_HIADDR(seg->ds_addr) |
4649 		    seg->ds_len << 4);
4650 		seg++;
4651 	}
4652 
4653 	bus_dmamap_sync(ring->data_dmat, data->map, BUS_DMASYNC_PREWRITE);
4654 	bus_dmamap_sync(ring->data_dmat, ring->cmd_dma.map,
4655 	    BUS_DMASYNC_PREWRITE);
4656 	bus_dmamap_sync(ring->desc_dma.tag, ring->desc_dma.map,
4657 	    BUS_DMASYNC_PREWRITE);
4658 
4659 	/* Update TX scheduler. */
4660 	if (ring->qid >= sc->firstaggqueue)
4661 		ops->update_sched(sc, ring->qid, ring->cur, tx->id, totlen);
4662 
4663 	/* Kick TX ring. */
4664 	ring->cur = (ring->cur + 1) % IWN_TX_RING_COUNT;
4665 	IWN_WRITE(sc, IWN_HBUS_TARG_WRPTR, ring->qid << 8 | ring->cur);
4666 
4667 	/* Mark TX ring as full if we reach a certain threshold. */
4668 	if (++ring->queued > IWN_TX_RING_HIMARK)
4669 		sc->qfullmsk |= 1 << ring->qid;
4670 
4671 	DPRINTF(sc, IWN_DEBUG_TRACE, "->%s: end\n",__func__);
4672 
4673 	return 0;
4674 }
4675 
4676 static int
4677 iwn_tx_data_raw(struct iwn_softc *sc, struct mbuf *m,
4678     struct ieee80211_node *ni, const struct ieee80211_bpf_params *params)
4679 {
4680 	struct iwn_ops *ops = &sc->ops;
4681 //	struct ifnet *ifp = sc->sc_ifp;
4682 	struct ieee80211vap *vap = ni->ni_vap;
4683 //	struct ieee80211com *ic = ifp->if_l2com;
4684 	struct iwn_tx_cmd *cmd;
4685 	struct iwn_cmd_data *tx;
4686 	struct ieee80211_frame *wh;
4687 	struct iwn_tx_ring *ring;
4688 	struct iwn_tx_desc *desc;
4689 	struct iwn_tx_data *data;
4690 	struct mbuf *m1;
4691 	bus_dma_segment_t *seg, segs[IWN_MAX_SCATTER];
4692 	uint32_t flags;
4693 	u_int hdrlen;
4694 	int ac, totlen, error, pad, nsegs = 0, i, rate;
4695 	uint8_t type;
4696 
4697 	DPRINTF(sc, IWN_DEBUG_TRACE, "->%s begin\n", __func__);
4698 
4699 	IWN_LOCK_ASSERT(sc);
4700 
4701 	wh = mtod(m, struct ieee80211_frame *);
4702 	hdrlen = ieee80211_anyhdrsize(wh);
4703 	type = wh->i_fc[0] & IEEE80211_FC0_TYPE_MASK;
4704 
4705 	ac = params->ibp_pri & 3;
4706 
4707 	ring = &sc->txq[ac];
4708 	desc = &ring->desc[ring->cur];
4709 	data = &ring->data[ring->cur];
4710 
4711 	/* Choose a TX rate. */
4712 	rate = params->ibp_rate0;
4713 	totlen = m->m_pkthdr.len;
4714 
4715 	/* Prepare TX firmware command. */
4716 	cmd = &ring->cmd[ring->cur];
4717 	cmd->code = IWN_CMD_TX_DATA;
4718 	cmd->flags = 0;
4719 	cmd->qid = ring->qid;
4720 	cmd->idx = ring->cur;
4721 
4722 	tx = (struct iwn_cmd_data *)cmd->data;
4723 	/* NB: No need to clear tx, all fields are reinitialized here. */
4724 	tx->scratch = 0;	/* clear "scratch" area */
4725 
4726 	flags = 0;
4727 	if ((params->ibp_flags & IEEE80211_BPF_NOACK) == 0)
4728 		flags |= IWN_TX_NEED_ACK;
4729 	if (params->ibp_flags & IEEE80211_BPF_RTS) {
4730 		if (sc->hw_type != IWN_HW_REV_TYPE_4965) {
4731 			/* 5000 autoselects RTS/CTS or CTS-to-self. */
4732 			flags &= ~IWN_TX_NEED_RTS;
4733 			flags |= IWN_TX_NEED_PROTECTION;
4734 		} else
4735 			flags |= IWN_TX_NEED_RTS | IWN_TX_FULL_TXOP;
4736 	}
4737 	if (params->ibp_flags & IEEE80211_BPF_CTS) {
4738 		if (sc->hw_type != IWN_HW_REV_TYPE_4965) {
4739 			/* 5000 autoselects RTS/CTS or CTS-to-self. */
4740 			flags &= ~IWN_TX_NEED_CTS;
4741 			flags |= IWN_TX_NEED_PROTECTION;
4742 		} else
4743 			flags |= IWN_TX_NEED_CTS | IWN_TX_FULL_TXOP;
4744 	}
4745 	if (type == IEEE80211_FC0_TYPE_MGT) {
4746 		uint8_t subtype = wh->i_fc[0] & IEEE80211_FC0_SUBTYPE_MASK;
4747 
4748 		/* Tell HW to set timestamp in probe responses. */
4749 		if (subtype == IEEE80211_FC0_SUBTYPE_PROBE_RESP)
4750 			flags |= IWN_TX_INSERT_TSTAMP;
4751 
4752 		if (subtype == IEEE80211_FC0_SUBTYPE_ASSOC_REQ ||
4753 		    subtype == IEEE80211_FC0_SUBTYPE_REASSOC_REQ)
4754 			tx->timeout = htole16(3);
4755 		else
4756 			tx->timeout = htole16(2);
4757 	} else
4758 		tx->timeout = htole16(0);
4759 
4760 	if (hdrlen & 3) {
4761 		/* First segment length must be a multiple of 4. */
4762 		flags |= IWN_TX_NEED_PADDING;
4763 		pad = 4 - (hdrlen & 3);
4764 	} else
4765 		pad = 0;
4766 
4767 	if (ieee80211_radiotap_active_vap(vap)) {
4768 		struct iwn_tx_radiotap_header *tap = &sc->sc_txtap;
4769 
4770 		tap->wt_flags = 0;
4771 		tap->wt_rate = rate;
4772 
4773 		ieee80211_radiotap_tx(vap, m);
4774 	}
4775 
4776 	tx->len = htole16(totlen);
4777 	tx->tid = 0;
4778 	tx->id = sc->broadcast_id;
4779 	tx->rts_ntries = params->ibp_try1;
4780 	tx->data_ntries = params->ibp_try0;
4781 	tx->lifetime = htole32(IWN_LIFETIME_INFINITE);
4782 	tx->rate = iwn_rate_to_plcp(sc, ni, rate);
4783 
4784 	/* Group or management frame. */
4785 	tx->linkq = 0;
4786 
4787 	/* Set physical address of "scratch area". */
4788 	tx->loaddr = htole32(IWN_LOADDR(data->scratch_paddr));
4789 	tx->hiaddr = IWN_HIADDR(data->scratch_paddr);
4790 
4791 	/* Copy 802.11 header in TX command. */
4792 	memcpy((uint8_t *)(tx + 1), wh, hdrlen);
4793 
4794 	/* Trim 802.11 header. */
4795 	m_adj(m, hdrlen);
4796 	tx->security = 0;
4797 	tx->flags = htole32(flags);
4798 
4799 	error = bus_dmamap_load_mbuf_sg(ring->data_dmat, data->map, m, segs,
4800 	    &nsegs, BUS_DMA_NOWAIT);
4801 	if (error != 0) {
4802 		if (error != EFBIG) {
4803 			device_printf(sc->sc_dev,
4804 			    "%s: can't map mbuf (error %d)\n", __func__, error);
4805 			m_freem(m);
4806 			return error;
4807 		}
4808 		/* Too many DMA segments, linearize mbuf. */
4809 		m1 = m_collapse(m, M_NOWAIT, IWN_MAX_SCATTER - 1);
4810 		if (m1 == NULL) {
4811 			device_printf(sc->sc_dev,
4812 			    "%s: could not defrag mbuf\n", __func__);
4813 			m_freem(m);
4814 			return ENOBUFS;
4815 		}
4816 		m = m1;
4817 
4818 		error = bus_dmamap_load_mbuf_sg(ring->data_dmat, data->map, m,
4819 		    segs, &nsegs, BUS_DMA_NOWAIT);
4820 		if (error != 0) {
4821 			device_printf(sc->sc_dev,
4822 			    "%s: can't map mbuf (error %d)\n", __func__, error);
4823 			m_freem(m);
4824 			return error;
4825 		}
4826 	}
4827 
4828 	data->m = m;
4829 	data->ni = ni;
4830 
4831 	DPRINTF(sc, IWN_DEBUG_XMIT, "%s: qid %d idx %d len %d nsegs %d\n",
4832 	    __func__, ring->qid, ring->cur, m->m_pkthdr.len, nsegs);
4833 
4834 	/* Fill TX descriptor. */
4835 	desc->nsegs = 1;
4836 	if (m->m_len != 0)
4837 		desc->nsegs += nsegs;
4838 	/* First DMA segment is used by the TX command. */
4839 	desc->segs[0].addr = htole32(IWN_LOADDR(data->cmd_paddr));
4840 	desc->segs[0].len  = htole16(IWN_HIADDR(data->cmd_paddr) |
4841 	    (4 + sizeof (*tx) + hdrlen + pad) << 4);
4842 	/* Other DMA segments are for data payload. */
4843 	seg = &segs[0];
4844 	for (i = 1; i <= nsegs; i++) {
4845 		desc->segs[i].addr = htole32(IWN_LOADDR(seg->ds_addr));
4846 		desc->segs[i].len  = htole16(IWN_HIADDR(seg->ds_addr) |
4847 		    seg->ds_len << 4);
4848 		seg++;
4849 	}
4850 
4851 	bus_dmamap_sync(ring->data_dmat, data->map, BUS_DMASYNC_PREWRITE);
4852 	bus_dmamap_sync(ring->data_dmat, ring->cmd_dma.map,
4853 	    BUS_DMASYNC_PREWRITE);
4854 	bus_dmamap_sync(ring->desc_dma.tag, ring->desc_dma.map,
4855 	    BUS_DMASYNC_PREWRITE);
4856 
4857 	/* Update TX scheduler. */
4858 	if (ring->qid >= sc->firstaggqueue)
4859 		ops->update_sched(sc, ring->qid, ring->cur, tx->id, totlen);
4860 
4861 	/* Kick TX ring. */
4862 	ring->cur = (ring->cur + 1) % IWN_TX_RING_COUNT;
4863 	IWN_WRITE(sc, IWN_HBUS_TARG_WRPTR, ring->qid << 8 | ring->cur);
4864 
4865 	/* Mark TX ring as full if we reach a certain threshold. */
4866 	if (++ring->queued > IWN_TX_RING_HIMARK)
4867 		sc->qfullmsk |= 1 << ring->qid;
4868 
4869 	DPRINTF(sc, IWN_DEBUG_TRACE, "->%s: end\n",__func__);
4870 
4871 	return 0;
4872 }
4873 
4874 static void
4875 iwn_xmit_task(void *arg0, int pending)
4876 {
4877 	struct iwn_softc *sc = arg0;
4878 	struct ifnet *ifp = sc->sc_ifp;
4879 	struct ieee80211_node *ni;
4880 	struct mbuf *m;
4881 	int error;
4882 	struct ieee80211_bpf_params p;
4883 	int have_p;
4884 
4885 	DPRINTF(sc, IWN_DEBUG_XMIT, "%s: called\n", __func__);
4886 
4887 	IWN_LOCK(sc);
4888 	/*
4889 	 * Dequeue frames, attempt to transmit,
4890 	 * then disable beaconwait when we're done.
4891 	 */
4892 	while ((m = mbufq_dequeue(&sc->sc_xmit_queue)) != NULL) {
4893 		have_p = 0;
4894 		ni = (struct ieee80211_node *)m->m_pkthdr.rcvif;
4895 
4896 		/* Get xmit params if appropriate */
4897 		if (ieee80211_get_xmit_params(m, &p) == 0)
4898 			have_p = 1;
4899 
4900 		DPRINTF(sc, IWN_DEBUG_XMIT, "%s: m=%p, have_p=%d\n",
4901 		    __func__, m, have_p);
4902 
4903 		/* If we have xmit params, use them */
4904 		if (have_p)
4905 			error = iwn_tx_data_raw(sc, m, ni, &p);
4906 		else
4907 			error = iwn_tx_data(sc, m, ni);
4908 
4909 		if (error != 0) {
4910 			ieee80211_free_node(ni);
4911 			if_inc_counter(ifp, IFCOUNTER_OERRORS, 1);
4912 		}
4913 	}
4914 
4915 	sc->sc_beacon_wait = 0;
4916 	IWN_UNLOCK(sc);
4917 }
4918 
4919 static int
4920 iwn_raw_xmit(struct ieee80211_node *ni, struct mbuf *m,
4921     const struct ieee80211_bpf_params *params)
4922 {
4923 	struct ieee80211com *ic = ni->ni_ic;
4924 	struct ifnet *ifp = ic->ic_ifp;
4925 	struct iwn_softc *sc = ifp->if_softc;
4926 	int error = 0;
4927 
4928 	DPRINTF(sc, IWN_DEBUG_XMIT | IWN_DEBUG_TRACE, "->%s begin\n", __func__);
4929 
4930 	if ((ifp->if_drv_flags & IFF_DRV_RUNNING) == 0) {
4931 		ieee80211_free_node(ni);
4932 		m_freem(m);
4933 		return ENETDOWN;
4934 	}
4935 
4936 	/* XXX? net80211 doesn't set this on xmit'ed raw frames? */
4937 	m->m_pkthdr.rcvif = (void *) ni;
4938 
4939 	IWN_LOCK(sc);
4940 
4941 	/* queue frame if we have to */
4942 	if (sc->sc_beacon_wait) {
4943 		if (iwn_xmit_queue_enqueue(sc, m) != 0) {
4944 			m_freem(m);
4945 			ieee80211_free_node(ni);
4946 			if_inc_counter(ifp, IFCOUNTER_OERRORS, 1);
4947 			IWN_UNLOCK(sc);
4948 			return (ENOBUFS);
4949 		}
4950 		/* Queued, so just return OK */
4951 		IWN_UNLOCK(sc);
4952 		return (0);
4953 	}
4954 
4955 	if (params == NULL) {
4956 		/*
4957 		 * Legacy path; interpret frame contents to decide
4958 		 * precisely how to send the frame.
4959 		 */
4960 		error = iwn_tx_data(sc, m, ni);
4961 	} else {
4962 		/*
4963 		 * Caller supplied explicit parameters to use in
4964 		 * sending the frame.
4965 		 */
4966 		error = iwn_tx_data_raw(sc, m, ni, params);
4967 	}
4968 	if (error != 0) {
4969 		/* NB: m is reclaimed on tx failure */
4970 		ieee80211_free_node(ni);
4971 		if_inc_counter(ifp, IFCOUNTER_OERRORS, 1);
4972 	} else
4973 		sc->sc_tx_timer = 5;
4974 
4975 	IWN_UNLOCK(sc);
4976 
4977 	DPRINTF(sc, IWN_DEBUG_TRACE | IWN_DEBUG_XMIT, "->%s: end\n",__func__);
4978 
4979 	return error;
4980 }
4981 
4982 static void
4983 iwn_start(struct ifnet *ifp)
4984 {
4985 	struct iwn_softc *sc = ifp->if_softc;
4986 
4987 	IWN_LOCK(sc);
4988 	iwn_start_locked(ifp);
4989 	IWN_UNLOCK(sc);
4990 }
4991 
4992 static void
4993 iwn_start_locked(struct ifnet *ifp)
4994 {
4995 	struct iwn_softc *sc = ifp->if_softc;
4996 	struct ieee80211_node *ni;
4997 	struct mbuf *m;
4998 
4999 	IWN_LOCK_ASSERT(sc);
5000 
5001 	/*
5002 	 * If we're waiting for a beacon, we can just exit out here
5003 	 * and wait for the taskqueue to be kicked.
5004 	 */
5005 	if (sc->sc_beacon_wait) {
5006 		return;
5007 	}
5008 
5009 	DPRINTF(sc, IWN_DEBUG_XMIT, "%s: called\n", __func__);
5010 
5011 	if ((ifp->if_drv_flags & IFF_DRV_RUNNING) == 0 ||
5012 	    (ifp->if_drv_flags & IFF_DRV_OACTIVE))
5013 		return;
5014 
5015 	for (;;) {
5016 		if (sc->qfullmsk != 0) {
5017 			ifp->if_drv_flags |= IFF_DRV_OACTIVE;
5018 			break;
5019 		}
5020 		IFQ_DRV_DEQUEUE(&ifp->if_snd, m);
5021 		if (m == NULL)
5022 			break;
5023 		ni = (struct ieee80211_node *)m->m_pkthdr.rcvif;
5024 		if (iwn_tx_data(sc, m, ni) != 0) {
5025 			ieee80211_free_node(ni);
5026 			if_inc_counter(ifp, IFCOUNTER_OERRORS, 1);
5027 		} else
5028 			sc->sc_tx_timer = 5;
5029 	}
5030 
5031 	DPRINTF(sc, IWN_DEBUG_XMIT, "%s: done\n", __func__);
5032 }
5033 
5034 static void
5035 iwn_watchdog(void *arg)
5036 {
5037 	struct iwn_softc *sc = arg;
5038 	struct ifnet *ifp = sc->sc_ifp;
5039 	struct ieee80211com *ic = ifp->if_l2com;
5040 
5041 	IWN_LOCK_ASSERT(sc);
5042 
5043 	KASSERT(ifp->if_drv_flags & IFF_DRV_RUNNING, ("not running"));
5044 
5045 	DPRINTF(sc, IWN_DEBUG_TRACE, "->Doing %s\n", __func__);
5046 
5047 	if (sc->sc_tx_timer > 0) {
5048 		if (--sc->sc_tx_timer == 0) {
5049 			ic_printf(ic, "device timeout\n");
5050 			ieee80211_runtask(ic, &sc->sc_reinit_task);
5051 			return;
5052 		}
5053 	}
5054 	callout_reset(&sc->watchdog_to, hz, iwn_watchdog, sc);
5055 }
5056 
5057 static int
5058 iwn_ioctl(struct ifnet *ifp, u_long cmd, caddr_t data)
5059 {
5060 	struct iwn_softc *sc = ifp->if_softc;
5061 	struct ieee80211com *ic = ifp->if_l2com;
5062 	struct ieee80211vap *vap = TAILQ_FIRST(&ic->ic_vaps);
5063 	struct ifreq *ifr = (struct ifreq *) data;
5064 	int error = 0, startall = 0, stop = 0;
5065 
5066 	switch (cmd) {
5067 	case SIOCGIFADDR:
5068 		error = ether_ioctl(ifp, cmd, data);
5069 		break;
5070 	case SIOCSIFFLAGS:
5071 		IWN_LOCK(sc);
5072 		if (ifp->if_flags & IFF_UP) {
5073 			if (!(ifp->if_drv_flags & IFF_DRV_RUNNING)) {
5074 				iwn_init_locked(sc);
5075 				if (IWN_READ(sc, IWN_GP_CNTRL) & IWN_GP_CNTRL_RFKILL)
5076 					startall = 1;
5077 				else
5078 					stop = 1;
5079 			}
5080 		} else {
5081 			if (ifp->if_drv_flags & IFF_DRV_RUNNING)
5082 				iwn_stop_locked(sc);
5083 		}
5084 		IWN_UNLOCK(sc);
5085 		if (startall)
5086 			ieee80211_start_all(ic);
5087 		else if (vap != NULL && stop)
5088 			ieee80211_stop(vap);
5089 		break;
5090 	case SIOCGIFMEDIA:
5091 		error = ifmedia_ioctl(ifp, ifr, &ic->ic_media, cmd);
5092 		break;
5093 	case SIOCGIWNSTATS:
5094 		IWN_LOCK(sc);
5095 		/* XXX validate permissions/memory/etc? */
5096 		error = copyout(&sc->last_stat, ifr->ifr_data,
5097 		    sizeof(struct iwn_stats));
5098 		IWN_UNLOCK(sc);
5099 		break;
5100 	case SIOCZIWNSTATS:
5101 		IWN_LOCK(sc);
5102 		memset(&sc->last_stat, 0, sizeof(struct iwn_stats));
5103 		IWN_UNLOCK(sc);
5104 		break;
5105 	default:
5106 		error = EINVAL;
5107 		break;
5108 	}
5109 	return error;
5110 }
5111 
5112 /*
5113  * Send a command to the firmware.
5114  */
5115 static int
5116 iwn_cmd(struct iwn_softc *sc, int code, const void *buf, int size, int async)
5117 {
5118 	struct iwn_tx_ring *ring;
5119 	struct iwn_tx_desc *desc;
5120 	struct iwn_tx_data *data;
5121 	struct iwn_tx_cmd *cmd;
5122 	struct mbuf *m;
5123 	bus_addr_t paddr;
5124 	int totlen, error;
5125 	int cmd_queue_num;
5126 
5127 	DPRINTF(sc, IWN_DEBUG_TRACE, "->%s begin\n", __func__);
5128 
5129 	if (async == 0)
5130 		IWN_LOCK_ASSERT(sc);
5131 
5132 	if (sc->sc_flags & IWN_FLAG_PAN_SUPPORT)
5133 		cmd_queue_num = IWN_PAN_CMD_QUEUE;
5134 	else
5135 		cmd_queue_num = IWN_CMD_QUEUE_NUM;
5136 
5137 	ring = &sc->txq[cmd_queue_num];
5138 	desc = &ring->desc[ring->cur];
5139 	data = &ring->data[ring->cur];
5140 	totlen = 4 + size;
5141 
5142 	if (size > sizeof cmd->data) {
5143 		/* Command is too large to fit in a descriptor. */
5144 		if (totlen > MCLBYTES)
5145 			return EINVAL;
5146 		m = m_getjcl(M_NOWAIT, MT_DATA, M_PKTHDR, MJUMPAGESIZE);
5147 		if (m == NULL)
5148 			return ENOMEM;
5149 		cmd = mtod(m, struct iwn_tx_cmd *);
5150 		error = bus_dmamap_load(ring->data_dmat, data->map, cmd,
5151 		    totlen, iwn_dma_map_addr, &paddr, BUS_DMA_NOWAIT);
5152 		if (error != 0) {
5153 			m_freem(m);
5154 			return error;
5155 		}
5156 		data->m = m;
5157 	} else {
5158 		cmd = &ring->cmd[ring->cur];
5159 		paddr = data->cmd_paddr;
5160 	}
5161 
5162 	cmd->code = code;
5163 	cmd->flags = 0;
5164 	cmd->qid = ring->qid;
5165 	cmd->idx = ring->cur;
5166 	memcpy(cmd->data, buf, size);
5167 
5168 	desc->nsegs = 1;
5169 	desc->segs[0].addr = htole32(IWN_LOADDR(paddr));
5170 	desc->segs[0].len  = htole16(IWN_HIADDR(paddr) | totlen << 4);
5171 
5172 	DPRINTF(sc, IWN_DEBUG_CMD, "%s: %s (0x%x) flags %d qid %d idx %d\n",
5173 	    __func__, iwn_intr_str(cmd->code), cmd->code,
5174 	    cmd->flags, cmd->qid, cmd->idx);
5175 
5176 	if (size > sizeof cmd->data) {
5177 		bus_dmamap_sync(ring->data_dmat, data->map,
5178 		    BUS_DMASYNC_PREWRITE);
5179 	} else {
5180 		bus_dmamap_sync(ring->data_dmat, ring->cmd_dma.map,
5181 		    BUS_DMASYNC_PREWRITE);
5182 	}
5183 	bus_dmamap_sync(ring->desc_dma.tag, ring->desc_dma.map,
5184 	    BUS_DMASYNC_PREWRITE);
5185 
5186 	/* Kick command ring. */
5187 	ring->cur = (ring->cur + 1) % IWN_TX_RING_COUNT;
5188 	IWN_WRITE(sc, IWN_HBUS_TARG_WRPTR, ring->qid << 8 | ring->cur);
5189 
5190 	DPRINTF(sc, IWN_DEBUG_TRACE, "->%s: end\n",__func__);
5191 
5192 	return async ? 0 : msleep(desc, &sc->sc_mtx, PCATCH, "iwncmd", hz);
5193 }
5194 
5195 static int
5196 iwn4965_add_node(struct iwn_softc *sc, struct iwn_node_info *node, int async)
5197 {
5198 	struct iwn4965_node_info hnode;
5199 	caddr_t src, dst;
5200 
5201 	DPRINTF(sc, IWN_DEBUG_TRACE, "->Doing %s\n", __func__);
5202 
5203 	/*
5204 	 * We use the node structure for 5000 Series internally (it is
5205 	 * a superset of the one for 4965AGN). We thus copy the common
5206 	 * fields before sending the command.
5207 	 */
5208 	src = (caddr_t)node;
5209 	dst = (caddr_t)&hnode;
5210 	memcpy(dst, src, 48);
5211 	/* Skip TSC, RX MIC and TX MIC fields from ``src''. */
5212 	memcpy(dst + 48, src + 72, 20);
5213 	return iwn_cmd(sc, IWN_CMD_ADD_NODE, &hnode, sizeof hnode, async);
5214 }
5215 
5216 static int
5217 iwn5000_add_node(struct iwn_softc *sc, struct iwn_node_info *node, int async)
5218 {
5219 
5220 	DPRINTF(sc, IWN_DEBUG_TRACE, "->Doing %s\n", __func__);
5221 
5222 	/* Direct mapping. */
5223 	return iwn_cmd(sc, IWN_CMD_ADD_NODE, node, sizeof (*node), async);
5224 }
5225 
5226 static int
5227 iwn_set_link_quality(struct iwn_softc *sc, struct ieee80211_node *ni)
5228 {
5229 #define	RV(v)	((v) & IEEE80211_RATE_VAL)
5230 	struct iwn_node *wn = (void *)ni;
5231 	struct ieee80211_rateset *rs;
5232 	struct iwn_cmd_link_quality linkq;
5233 	int i, rate, txrate;
5234 	int is_11n;
5235 
5236 	DPRINTF(sc, IWN_DEBUG_TRACE, "->%s begin\n", __func__);
5237 
5238 	memset(&linkq, 0, sizeof linkq);
5239 	linkq.id = wn->id;
5240 	linkq.antmsk_1stream = iwn_get_1stream_tx_antmask(sc);
5241 	linkq.antmsk_2stream = iwn_get_2stream_tx_antmask(sc);
5242 
5243 	linkq.ampdu_max = 32;		/* XXX negotiated? */
5244 	linkq.ampdu_threshold = 3;
5245 	linkq.ampdu_limit = htole16(4000);	/* 4ms */
5246 
5247 	DPRINTF(sc, IWN_DEBUG_XMIT,
5248 	    "%s: 1stream antenna=0x%02x, 2stream antenna=0x%02x, ntxstreams=%d\n",
5249 	    __func__,
5250 	    linkq.antmsk_1stream,
5251 	    linkq.antmsk_2stream,
5252 	    sc->ntxchains);
5253 
5254 	/*
5255 	 * Are we using 11n rates? Ensure the channel is
5256 	 * 11n _and_ we have some 11n rates, or don't
5257 	 * try.
5258 	 */
5259 	if (IEEE80211_IS_CHAN_HT(ni->ni_chan) && ni->ni_htrates.rs_nrates > 0) {
5260 		rs = (struct ieee80211_rateset *) &ni->ni_htrates;
5261 		is_11n = 1;
5262 	} else {
5263 		rs = &ni->ni_rates;
5264 		is_11n = 0;
5265 	}
5266 
5267 	/* Start at highest available bit-rate. */
5268 	/*
5269 	 * XXX this is all very dirty!
5270 	 */
5271 	if (is_11n)
5272 		txrate = ni->ni_htrates.rs_nrates - 1;
5273 	else
5274 		txrate = rs->rs_nrates - 1;
5275 	for (i = 0; i < IWN_MAX_TX_RETRIES; i++) {
5276 		uint32_t plcp;
5277 
5278 		/*
5279 		 * XXX TODO: ensure the last two slots are the two lowest
5280 		 * rate entries, just for now.
5281 		 */
5282 		if (i == 14 || i == 15)
5283 			txrate = 0;
5284 
5285 		if (is_11n)
5286 			rate = IEEE80211_RATE_MCS | rs->rs_rates[txrate];
5287 		else
5288 			rate = RV(rs->rs_rates[txrate]);
5289 
5290 		/* Do rate -> PLCP config mapping */
5291 		plcp = iwn_rate_to_plcp(sc, ni, rate);
5292 		linkq.retry[i] = plcp;
5293 		DPRINTF(sc, IWN_DEBUG_XMIT,
5294 		    "%s: i=%d, txrate=%d, rate=0x%02x, plcp=0x%08x\n",
5295 		    __func__,
5296 		    i,
5297 		    txrate,
5298 		    rate,
5299 		    le32toh(plcp));
5300 
5301 		/*
5302 		 * The mimo field is an index into the table which
5303 		 * indicates the first index where it and subsequent entries
5304 		 * will not be using MIMO.
5305 		 *
5306 		 * Since we're filling linkq from 0..15 and we're filling
5307 		 * from the higest MCS rates to the lowest rates, if we
5308 		 * _are_ doing a dual-stream rate, set mimo to idx+1 (ie,
5309 		 * the next entry.)  That way if the next entry is a non-MIMO
5310 		 * entry, we're already pointing at it.
5311 		 */
5312 		if ((le32toh(plcp) & IWN_RFLAG_MCS) &&
5313 		    RV(le32toh(plcp)) > 7)
5314 			linkq.mimo = i + 1;
5315 
5316 		/* Next retry at immediate lower bit-rate. */
5317 		if (txrate > 0)
5318 			txrate--;
5319 	}
5320 	/*
5321 	 * If we reached the end of the list and indeed we hit
5322 	 * all MIMO rates (eg 5300 doing MCS23-15) then yes,
5323 	 * set mimo to 15.  Setting it to 16 panics the firmware.
5324 	 */
5325 	if (linkq.mimo > 15)
5326 		linkq.mimo = 15;
5327 
5328 	DPRINTF(sc, IWN_DEBUG_XMIT, "%s: mimo = %d\n", __func__, linkq.mimo);
5329 
5330 	DPRINTF(sc, IWN_DEBUG_TRACE, "->%s: end\n",__func__);
5331 
5332 	return iwn_cmd(sc, IWN_CMD_LINK_QUALITY, &linkq, sizeof linkq, 1);
5333 #undef	RV
5334 }
5335 
5336 /*
5337  * Broadcast node is used to send group-addressed and management frames.
5338  */
5339 static int
5340 iwn_add_broadcast_node(struct iwn_softc *sc, int async)
5341 {
5342 	struct iwn_ops *ops = &sc->ops;
5343 	struct ifnet *ifp = sc->sc_ifp;
5344 	struct ieee80211com *ic = ifp->if_l2com;
5345 	struct iwn_node_info node;
5346 	struct iwn_cmd_link_quality linkq;
5347 	uint8_t txant;
5348 	int i, error;
5349 
5350 	DPRINTF(sc, IWN_DEBUG_TRACE, "->%s begin\n", __func__);
5351 
5352 	sc->rxon = &sc->rx_on[IWN_RXON_BSS_CTX];
5353 
5354 	memset(&node, 0, sizeof node);
5355 	IEEE80211_ADDR_COPY(node.macaddr, ifp->if_broadcastaddr);
5356 	node.id = sc->broadcast_id;
5357 	DPRINTF(sc, IWN_DEBUG_RESET, "%s: adding broadcast node\n", __func__);
5358 	if ((error = ops->add_node(sc, &node, async)) != 0)
5359 		return error;
5360 
5361 	/* Use the first valid TX antenna. */
5362 	txant = IWN_LSB(sc->txchainmask);
5363 
5364 	memset(&linkq, 0, sizeof linkq);
5365 	linkq.id = sc->broadcast_id;
5366 	linkq.antmsk_1stream = iwn_get_1stream_tx_antmask(sc);
5367 	linkq.antmsk_2stream = iwn_get_2stream_tx_antmask(sc);
5368 	linkq.ampdu_max = 64;
5369 	linkq.ampdu_threshold = 3;
5370 	linkq.ampdu_limit = htole16(4000);	/* 4ms */
5371 
5372 	/* Use lowest mandatory bit-rate. */
5373 	/* XXX rate table lookup? */
5374 	if (IEEE80211_IS_CHAN_5GHZ(ic->ic_curchan))
5375 		linkq.retry[0] = htole32(0xd);
5376 	else
5377 		linkq.retry[0] = htole32(10 | IWN_RFLAG_CCK);
5378 	linkq.retry[0] |= htole32(IWN_RFLAG_ANT(txant));
5379 	/* Use same bit-rate for all TX retries. */
5380 	for (i = 1; i < IWN_MAX_TX_RETRIES; i++) {
5381 		linkq.retry[i] = linkq.retry[0];
5382 	}
5383 
5384 	DPRINTF(sc, IWN_DEBUG_TRACE, "->%s: end\n",__func__);
5385 
5386 	return iwn_cmd(sc, IWN_CMD_LINK_QUALITY, &linkq, sizeof linkq, async);
5387 }
5388 
5389 static int
5390 iwn_updateedca(struct ieee80211com *ic)
5391 {
5392 #define IWN_EXP2(x)	((1 << (x)) - 1)	/* CWmin = 2^ECWmin - 1 */
5393 	struct iwn_softc *sc = ic->ic_softc;
5394 	struct iwn_edca_params cmd;
5395 	int aci;
5396 
5397 	DPRINTF(sc, IWN_DEBUG_TRACE, "->%s begin\n", __func__);
5398 
5399 	memset(&cmd, 0, sizeof cmd);
5400 	cmd.flags = htole32(IWN_EDCA_UPDATE);
5401 	for (aci = 0; aci < WME_NUM_AC; aci++) {
5402 		const struct wmeParams *ac =
5403 		    &ic->ic_wme.wme_chanParams.cap_wmeParams[aci];
5404 		cmd.ac[aci].aifsn = ac->wmep_aifsn;
5405 		cmd.ac[aci].cwmin = htole16(IWN_EXP2(ac->wmep_logcwmin));
5406 		cmd.ac[aci].cwmax = htole16(IWN_EXP2(ac->wmep_logcwmax));
5407 		cmd.ac[aci].txoplimit =
5408 		    htole16(IEEE80211_TXOP_TO_US(ac->wmep_txopLimit));
5409 	}
5410 	IEEE80211_UNLOCK(ic);
5411 	IWN_LOCK(sc);
5412 	(void)iwn_cmd(sc, IWN_CMD_EDCA_PARAMS, &cmd, sizeof cmd, 1);
5413 	IWN_UNLOCK(sc);
5414 	IEEE80211_LOCK(ic);
5415 
5416 	DPRINTF(sc, IWN_DEBUG_TRACE, "->%s: end\n",__func__);
5417 
5418 	return 0;
5419 #undef IWN_EXP2
5420 }
5421 
5422 static void
5423 iwn_update_mcast(struct ieee80211com *ic)
5424 {
5425 	/* Ignore */
5426 }
5427 
5428 static void
5429 iwn_set_led(struct iwn_softc *sc, uint8_t which, uint8_t off, uint8_t on)
5430 {
5431 	struct iwn_cmd_led led;
5432 
5433 	DPRINTF(sc, IWN_DEBUG_TRACE, "->Doing %s\n", __func__);
5434 
5435 #if 0
5436 	/* XXX don't set LEDs during scan? */
5437 	if (sc->sc_is_scanning)
5438 		return;
5439 #endif
5440 
5441 	/* Clear microcode LED ownership. */
5442 	IWN_CLRBITS(sc, IWN_LED, IWN_LED_BSM_CTRL);
5443 
5444 	led.which = which;
5445 	led.unit = htole32(10000);	/* on/off in unit of 100ms */
5446 	led.off = off;
5447 	led.on = on;
5448 	(void)iwn_cmd(sc, IWN_CMD_SET_LED, &led, sizeof led, 1);
5449 }
5450 
5451 /*
5452  * Set the critical temperature at which the firmware will stop the radio
5453  * and notify us.
5454  */
5455 static int
5456 iwn_set_critical_temp(struct iwn_softc *sc)
5457 {
5458 	struct iwn_critical_temp crit;
5459 	int32_t temp;
5460 
5461 	DPRINTF(sc, IWN_DEBUG_TRACE, "->Doing %s\n", __func__);
5462 
5463 	IWN_WRITE(sc, IWN_UCODE_GP1_CLR, IWN_UCODE_GP1_CTEMP_STOP_RF);
5464 
5465 	if (sc->hw_type == IWN_HW_REV_TYPE_5150)
5466 		temp = (IWN_CTOK(110) - sc->temp_off) * -5;
5467 	else if (sc->hw_type == IWN_HW_REV_TYPE_4965)
5468 		temp = IWN_CTOK(110);
5469 	else
5470 		temp = 110;
5471 	memset(&crit, 0, sizeof crit);
5472 	crit.tempR = htole32(temp);
5473 	DPRINTF(sc, IWN_DEBUG_RESET, "setting critical temp to %d\n", temp);
5474 	return iwn_cmd(sc, IWN_CMD_SET_CRITICAL_TEMP, &crit, sizeof crit, 0);
5475 }
5476 
5477 static int
5478 iwn_set_timing(struct iwn_softc *sc, struct ieee80211_node *ni)
5479 {
5480 	struct iwn_cmd_timing cmd;
5481 	uint64_t val, mod;
5482 
5483 	DPRINTF(sc, IWN_DEBUG_TRACE, "->Doing %s\n", __func__);
5484 
5485 	memset(&cmd, 0, sizeof cmd);
5486 	memcpy(&cmd.tstamp, ni->ni_tstamp.data, sizeof (uint64_t));
5487 	cmd.bintval = htole16(ni->ni_intval);
5488 	cmd.lintval = htole16(10);
5489 
5490 	/* Compute remaining time until next beacon. */
5491 	val = (uint64_t)ni->ni_intval * IEEE80211_DUR_TU;
5492 	mod = le64toh(cmd.tstamp) % val;
5493 	cmd.binitval = htole32((uint32_t)(val - mod));
5494 
5495 	DPRINTF(sc, IWN_DEBUG_RESET, "timing bintval=%u tstamp=%ju, init=%u\n",
5496 	    ni->ni_intval, le64toh(cmd.tstamp), (uint32_t)(val - mod));
5497 
5498 	return iwn_cmd(sc, IWN_CMD_TIMING, &cmd, sizeof cmd, 1);
5499 }
5500 
5501 static void
5502 iwn4965_power_calibration(struct iwn_softc *sc, int temp)
5503 {
5504 	struct ifnet *ifp = sc->sc_ifp;
5505 	struct ieee80211com *ic = ifp->if_l2com;
5506 
5507 	DPRINTF(sc, IWN_DEBUG_TRACE, "->Doing %s\n", __func__);
5508 
5509 	/* Adjust TX power if need be (delta >= 3 degC). */
5510 	DPRINTF(sc, IWN_DEBUG_CALIBRATE, "%s: temperature %d->%d\n",
5511 	    __func__, sc->temp, temp);
5512 	if (abs(temp - sc->temp) >= 3) {
5513 		/* Record temperature of last calibration. */
5514 		sc->temp = temp;
5515 		(void)iwn4965_set_txpower(sc, ic->ic_bsschan, 1);
5516 	}
5517 }
5518 
5519 /*
5520  * Set TX power for current channel (each rate has its own power settings).
5521  * This function takes into account the regulatory information from EEPROM,
5522  * the current temperature and the current voltage.
5523  */
5524 static int
5525 iwn4965_set_txpower(struct iwn_softc *sc, struct ieee80211_channel *ch,
5526     int async)
5527 {
5528 /* Fixed-point arithmetic division using a n-bit fractional part. */
5529 #define fdivround(a, b, n)	\
5530 	((((1 << n) * (a)) / (b) + (1 << n) / 2) / (1 << n))
5531 /* Linear interpolation. */
5532 #define interpolate(x, x1, y1, x2, y2, n)	\
5533 	((y1) + fdivround(((int)(x) - (x1)) * ((y2) - (y1)), (x2) - (x1), n))
5534 
5535 	static const int tdiv[IWN_NATTEN_GROUPS] = { 9, 8, 8, 8, 6 };
5536 	struct iwn_ucode_info *uc = &sc->ucode_info;
5537 	struct iwn4965_cmd_txpower cmd;
5538 	struct iwn4965_eeprom_chan_samples *chans;
5539 	const uint8_t *rf_gain, *dsp_gain;
5540 	int32_t vdiff, tdiff;
5541 	int i, c, grp, maxpwr;
5542 	uint8_t chan;
5543 
5544 	sc->rxon = &sc->rx_on[IWN_RXON_BSS_CTX];
5545 	/* Retrieve current channel from last RXON. */
5546 	chan = sc->rxon->chan;
5547 	DPRINTF(sc, IWN_DEBUG_RESET, "setting TX power for channel %d\n",
5548 	    chan);
5549 
5550 	memset(&cmd, 0, sizeof cmd);
5551 	cmd.band = IEEE80211_IS_CHAN_5GHZ(ch) ? 0 : 1;
5552 	cmd.chan = chan;
5553 
5554 	if (IEEE80211_IS_CHAN_5GHZ(ch)) {
5555 		maxpwr   = sc->maxpwr5GHz;
5556 		rf_gain  = iwn4965_rf_gain_5ghz;
5557 		dsp_gain = iwn4965_dsp_gain_5ghz;
5558 	} else {
5559 		maxpwr   = sc->maxpwr2GHz;
5560 		rf_gain  = iwn4965_rf_gain_2ghz;
5561 		dsp_gain = iwn4965_dsp_gain_2ghz;
5562 	}
5563 
5564 	/* Compute voltage compensation. */
5565 	vdiff = ((int32_t)le32toh(uc->volt) - sc->eeprom_voltage) / 7;
5566 	if (vdiff > 0)
5567 		vdiff *= 2;
5568 	if (abs(vdiff) > 2)
5569 		vdiff = 0;
5570 	DPRINTF(sc, IWN_DEBUG_CALIBRATE | IWN_DEBUG_TXPOW,
5571 	    "%s: voltage compensation=%d (UCODE=%d, EEPROM=%d)\n",
5572 	    __func__, vdiff, le32toh(uc->volt), sc->eeprom_voltage);
5573 
5574 	/* Get channel attenuation group. */
5575 	if (chan <= 20)		/* 1-20 */
5576 		grp = 4;
5577 	else if (chan <= 43)	/* 34-43 */
5578 		grp = 0;
5579 	else if (chan <= 70)	/* 44-70 */
5580 		grp = 1;
5581 	else if (chan <= 124)	/* 71-124 */
5582 		grp = 2;
5583 	else			/* 125-200 */
5584 		grp = 3;
5585 	DPRINTF(sc, IWN_DEBUG_CALIBRATE | IWN_DEBUG_TXPOW,
5586 	    "%s: chan %d, attenuation group=%d\n", __func__, chan, grp);
5587 
5588 	/* Get channel sub-band. */
5589 	for (i = 0; i < IWN_NBANDS; i++)
5590 		if (sc->bands[i].lo != 0 &&
5591 		    sc->bands[i].lo <= chan && chan <= sc->bands[i].hi)
5592 			break;
5593 	if (i == IWN_NBANDS)	/* Can't happen in real-life. */
5594 		return EINVAL;
5595 	chans = sc->bands[i].chans;
5596 	DPRINTF(sc, IWN_DEBUG_CALIBRATE | IWN_DEBUG_TXPOW,
5597 	    "%s: chan %d sub-band=%d\n", __func__, chan, i);
5598 
5599 	for (c = 0; c < 2; c++) {
5600 		uint8_t power, gain, temp;
5601 		int maxchpwr, pwr, ridx, idx;
5602 
5603 		power = interpolate(chan,
5604 		    chans[0].num, chans[0].samples[c][1].power,
5605 		    chans[1].num, chans[1].samples[c][1].power, 1);
5606 		gain  = interpolate(chan,
5607 		    chans[0].num, chans[0].samples[c][1].gain,
5608 		    chans[1].num, chans[1].samples[c][1].gain, 1);
5609 		temp  = interpolate(chan,
5610 		    chans[0].num, chans[0].samples[c][1].temp,
5611 		    chans[1].num, chans[1].samples[c][1].temp, 1);
5612 		DPRINTF(sc, IWN_DEBUG_CALIBRATE | IWN_DEBUG_TXPOW,
5613 		    "%s: Tx chain %d: power=%d gain=%d temp=%d\n",
5614 		    __func__, c, power, gain, temp);
5615 
5616 		/* Compute temperature compensation. */
5617 		tdiff = ((sc->temp - temp) * 2) / tdiv[grp];
5618 		DPRINTF(sc, IWN_DEBUG_CALIBRATE | IWN_DEBUG_TXPOW,
5619 		    "%s: temperature compensation=%d (current=%d, EEPROM=%d)\n",
5620 		    __func__, tdiff, sc->temp, temp);
5621 
5622 		for (ridx = 0; ridx <= IWN_RIDX_MAX; ridx++) {
5623 			/* Convert dBm to half-dBm. */
5624 			maxchpwr = sc->maxpwr[chan] * 2;
5625 			if ((ridx / 8) & 1)
5626 				maxchpwr -= 6;	/* MIMO 2T: -3dB */
5627 
5628 			pwr = maxpwr;
5629 
5630 			/* Adjust TX power based on rate. */
5631 			if ((ridx % 8) == 5)
5632 				pwr -= 15;	/* OFDM48: -7.5dB */
5633 			else if ((ridx % 8) == 6)
5634 				pwr -= 17;	/* OFDM54: -8.5dB */
5635 			else if ((ridx % 8) == 7)
5636 				pwr -= 20;	/* OFDM60: -10dB */
5637 			else
5638 				pwr -= 10;	/* Others: -5dB */
5639 
5640 			/* Do not exceed channel max TX power. */
5641 			if (pwr > maxchpwr)
5642 				pwr = maxchpwr;
5643 
5644 			idx = gain - (pwr - power) - tdiff - vdiff;
5645 			if ((ridx / 8) & 1)	/* MIMO */
5646 				idx += (int32_t)le32toh(uc->atten[grp][c]);
5647 
5648 			if (cmd.band == 0)
5649 				idx += 9;	/* 5GHz */
5650 			if (ridx == IWN_RIDX_MAX)
5651 				idx += 5;	/* CCK */
5652 
5653 			/* Make sure idx stays in a valid range. */
5654 			if (idx < 0)
5655 				idx = 0;
5656 			else if (idx > IWN4965_MAX_PWR_INDEX)
5657 				idx = IWN4965_MAX_PWR_INDEX;
5658 
5659 			DPRINTF(sc, IWN_DEBUG_CALIBRATE | IWN_DEBUG_TXPOW,
5660 			    "%s: Tx chain %d, rate idx %d: power=%d\n",
5661 			    __func__, c, ridx, idx);
5662 			cmd.power[ridx].rf_gain[c] = rf_gain[idx];
5663 			cmd.power[ridx].dsp_gain[c] = dsp_gain[idx];
5664 		}
5665 	}
5666 
5667 	DPRINTF(sc, IWN_DEBUG_CALIBRATE | IWN_DEBUG_TXPOW,
5668 	    "%s: set tx power for chan %d\n", __func__, chan);
5669 	return iwn_cmd(sc, IWN_CMD_TXPOWER, &cmd, sizeof cmd, async);
5670 
5671 #undef interpolate
5672 #undef fdivround
5673 }
5674 
5675 static int
5676 iwn5000_set_txpower(struct iwn_softc *sc, struct ieee80211_channel *ch,
5677     int async)
5678 {
5679 	struct iwn5000_cmd_txpower cmd;
5680 	int cmdid;
5681 
5682 	DPRINTF(sc, IWN_DEBUG_TRACE, "->Doing %s\n", __func__);
5683 
5684 	/*
5685 	 * TX power calibration is handled automatically by the firmware
5686 	 * for 5000 Series.
5687 	 */
5688 	memset(&cmd, 0, sizeof cmd);
5689 	cmd.global_limit = 2 * IWN5000_TXPOWER_MAX_DBM;	/* 16 dBm */
5690 	cmd.flags = IWN5000_TXPOWER_NO_CLOSED;
5691 	cmd.srv_limit = IWN5000_TXPOWER_AUTO;
5692 	DPRINTF(sc, IWN_DEBUG_CALIBRATE | IWN_DEBUG_XMIT,
5693 	    "%s: setting TX power; rev=%d\n",
5694 	    __func__,
5695 	    IWN_UCODE_API(sc->ucode_rev));
5696 	if (IWN_UCODE_API(sc->ucode_rev) == 1)
5697 		cmdid = IWN_CMD_TXPOWER_DBM_V1;
5698 	else
5699 		cmdid = IWN_CMD_TXPOWER_DBM;
5700 	return iwn_cmd(sc, cmdid, &cmd, sizeof cmd, async);
5701 }
5702 
5703 /*
5704  * Retrieve the maximum RSSI (in dBm) among receivers.
5705  */
5706 static int
5707 iwn4965_get_rssi(struct iwn_softc *sc, struct iwn_rx_stat *stat)
5708 {
5709 	struct iwn4965_rx_phystat *phy = (void *)stat->phybuf;
5710 	uint8_t mask, agc;
5711 	int rssi;
5712 
5713 	DPRINTF(sc, IWN_DEBUG_TRACE, "->Doing %s\n", __func__);
5714 
5715 	mask = (le16toh(phy->antenna) >> 4) & IWN_ANT_ABC;
5716 	agc  = (le16toh(phy->agc) >> 7) & 0x7f;
5717 
5718 	rssi = 0;
5719 	if (mask & IWN_ANT_A)
5720 		rssi = MAX(rssi, phy->rssi[0]);
5721 	if (mask & IWN_ANT_B)
5722 		rssi = MAX(rssi, phy->rssi[2]);
5723 	if (mask & IWN_ANT_C)
5724 		rssi = MAX(rssi, phy->rssi[4]);
5725 
5726 	DPRINTF(sc, IWN_DEBUG_RECV,
5727 	    "%s: agc %d mask 0x%x rssi %d %d %d result %d\n", __func__, agc,
5728 	    mask, phy->rssi[0], phy->rssi[2], phy->rssi[4],
5729 	    rssi - agc - IWN_RSSI_TO_DBM);
5730 	return rssi - agc - IWN_RSSI_TO_DBM;
5731 }
5732 
5733 static int
5734 iwn5000_get_rssi(struct iwn_softc *sc, struct iwn_rx_stat *stat)
5735 {
5736 	struct iwn5000_rx_phystat *phy = (void *)stat->phybuf;
5737 	uint8_t agc;
5738 	int rssi;
5739 
5740 	DPRINTF(sc, IWN_DEBUG_TRACE, "->Doing %s\n", __func__);
5741 
5742 	agc = (le32toh(phy->agc) >> 9) & 0x7f;
5743 
5744 	rssi = MAX(le16toh(phy->rssi[0]) & 0xff,
5745 		   le16toh(phy->rssi[1]) & 0xff);
5746 	rssi = MAX(le16toh(phy->rssi[2]) & 0xff, rssi);
5747 
5748 	DPRINTF(sc, IWN_DEBUG_RECV,
5749 	    "%s: agc %d rssi %d %d %d result %d\n", __func__, agc,
5750 	    phy->rssi[0], phy->rssi[1], phy->rssi[2],
5751 	    rssi - agc - IWN_RSSI_TO_DBM);
5752 	return rssi - agc - IWN_RSSI_TO_DBM;
5753 }
5754 
5755 /*
5756  * Retrieve the average noise (in dBm) among receivers.
5757  */
5758 static int
5759 iwn_get_noise(const struct iwn_rx_general_stats *stats)
5760 {
5761 	int i, total, nbant, noise;
5762 
5763 	total = nbant = 0;
5764 	for (i = 0; i < 3; i++) {
5765 		if ((noise = le32toh(stats->noise[i]) & 0xff) == 0)
5766 			continue;
5767 		total += noise;
5768 		nbant++;
5769 	}
5770 	/* There should be at least one antenna but check anyway. */
5771 	return (nbant == 0) ? -127 : (total / nbant) - 107;
5772 }
5773 
5774 /*
5775  * Compute temperature (in degC) from last received statistics.
5776  */
5777 static int
5778 iwn4965_get_temperature(struct iwn_softc *sc)
5779 {
5780 	struct iwn_ucode_info *uc = &sc->ucode_info;
5781 	int32_t r1, r2, r3, r4, temp;
5782 
5783 	DPRINTF(sc, IWN_DEBUG_TRACE, "->Doing %s\n", __func__);
5784 
5785 	r1 = le32toh(uc->temp[0].chan20MHz);
5786 	r2 = le32toh(uc->temp[1].chan20MHz);
5787 	r3 = le32toh(uc->temp[2].chan20MHz);
5788 	r4 = le32toh(sc->rawtemp);
5789 
5790 	if (r1 == r3)	/* Prevents division by 0 (should not happen). */
5791 		return 0;
5792 
5793 	/* Sign-extend 23-bit R4 value to 32-bit. */
5794 	r4 = ((r4 & 0xffffff) ^ 0x800000) - 0x800000;
5795 	/* Compute temperature in Kelvin. */
5796 	temp = (259 * (r4 - r2)) / (r3 - r1);
5797 	temp = (temp * 97) / 100 + 8;
5798 
5799 	DPRINTF(sc, IWN_DEBUG_ANY, "temperature %dK/%dC\n", temp,
5800 	    IWN_KTOC(temp));
5801 	return IWN_KTOC(temp);
5802 }
5803 
5804 static int
5805 iwn5000_get_temperature(struct iwn_softc *sc)
5806 {
5807 	int32_t temp;
5808 
5809 	DPRINTF(sc, IWN_DEBUG_TRACE, "->Doing %s\n", __func__);
5810 
5811 	/*
5812 	 * Temperature is not used by the driver for 5000 Series because
5813 	 * TX power calibration is handled by firmware.
5814 	 */
5815 	temp = le32toh(sc->rawtemp);
5816 	if (sc->hw_type == IWN_HW_REV_TYPE_5150) {
5817 		temp = (temp / -5) + sc->temp_off;
5818 		temp = IWN_KTOC(temp);
5819 	}
5820 	return temp;
5821 }
5822 
5823 /*
5824  * Initialize sensitivity calibration state machine.
5825  */
5826 static int
5827 iwn_init_sensitivity(struct iwn_softc *sc)
5828 {
5829 	struct iwn_ops *ops = &sc->ops;
5830 	struct iwn_calib_state *calib = &sc->calib;
5831 	uint32_t flags;
5832 	int error;
5833 
5834 	DPRINTF(sc, IWN_DEBUG_TRACE, "->Doing %s\n", __func__);
5835 
5836 	/* Reset calibration state machine. */
5837 	memset(calib, 0, sizeof (*calib));
5838 	calib->state = IWN_CALIB_STATE_INIT;
5839 	calib->cck_state = IWN_CCK_STATE_HIFA;
5840 	/* Set initial correlation values. */
5841 	calib->ofdm_x1     = sc->limits->min_ofdm_x1;
5842 	calib->ofdm_mrc_x1 = sc->limits->min_ofdm_mrc_x1;
5843 	calib->ofdm_x4     = sc->limits->min_ofdm_x4;
5844 	calib->ofdm_mrc_x4 = sc->limits->min_ofdm_mrc_x4;
5845 	calib->cck_x4      = 125;
5846 	calib->cck_mrc_x4  = sc->limits->min_cck_mrc_x4;
5847 	calib->energy_cck  = sc->limits->energy_cck;
5848 
5849 	/* Write initial sensitivity. */
5850 	if ((error = iwn_send_sensitivity(sc)) != 0)
5851 		return error;
5852 
5853 	/* Write initial gains. */
5854 	if ((error = ops->init_gains(sc)) != 0)
5855 		return error;
5856 
5857 	/* Request statistics at each beacon interval. */
5858 	flags = 0;
5859 	DPRINTF(sc, IWN_DEBUG_CALIBRATE, "%s: sending request for statistics\n",
5860 	    __func__);
5861 	return iwn_cmd(sc, IWN_CMD_GET_STATISTICS, &flags, sizeof flags, 1);
5862 }
5863 
5864 /*
5865  * Collect noise and RSSI statistics for the first 20 beacons received
5866  * after association and use them to determine connected antennas and
5867  * to set differential gains.
5868  */
5869 static void
5870 iwn_collect_noise(struct iwn_softc *sc,
5871     const struct iwn_rx_general_stats *stats)
5872 {
5873 	struct iwn_ops *ops = &sc->ops;
5874 	struct iwn_calib_state *calib = &sc->calib;
5875 	struct ifnet *ifp = sc->sc_ifp;
5876 	struct ieee80211com *ic = ifp->if_l2com;
5877 	uint32_t val;
5878 	int i;
5879 
5880 	DPRINTF(sc, IWN_DEBUG_TRACE, "->%s begin\n", __func__);
5881 
5882 	/* Accumulate RSSI and noise for all 3 antennas. */
5883 	for (i = 0; i < 3; i++) {
5884 		calib->rssi[i] += le32toh(stats->rssi[i]) & 0xff;
5885 		calib->noise[i] += le32toh(stats->noise[i]) & 0xff;
5886 	}
5887 	/* NB: We update differential gains only once after 20 beacons. */
5888 	if (++calib->nbeacons < 20)
5889 		return;
5890 
5891 	/* Determine highest average RSSI. */
5892 	val = MAX(calib->rssi[0], calib->rssi[1]);
5893 	val = MAX(calib->rssi[2], val);
5894 
5895 	/* Determine which antennas are connected. */
5896 	sc->chainmask = sc->rxchainmask;
5897 	for (i = 0; i < 3; i++)
5898 		if (val - calib->rssi[i] > 15 * 20)
5899 			sc->chainmask &= ~(1 << i);
5900 	DPRINTF(sc, IWN_DEBUG_CALIBRATE | IWN_DEBUG_XMIT,
5901 	    "%s: RX chains mask: theoretical=0x%x, actual=0x%x\n",
5902 	    __func__, sc->rxchainmask, sc->chainmask);
5903 
5904 	/* If none of the TX antennas are connected, keep at least one. */
5905 	if ((sc->chainmask & sc->txchainmask) == 0)
5906 		sc->chainmask |= IWN_LSB(sc->txchainmask);
5907 
5908 	(void)ops->set_gains(sc);
5909 	calib->state = IWN_CALIB_STATE_RUN;
5910 
5911 #ifdef notyet
5912 	/* XXX Disable RX chains with no antennas connected. */
5913 	sc->rxon->rxchain = htole16(IWN_RXCHAIN_SEL(sc->chainmask));
5914 	if (sc->sc_is_scanning)
5915 		device_printf(sc->sc_dev,
5916 		    "%s: is_scanning set, before RXON\n",
5917 		    __func__);
5918 	(void)iwn_cmd(sc, IWN_CMD_RXON, sc->rxon, sc->rxonsz, 1);
5919 #endif
5920 
5921 	/* Enable power-saving mode if requested by user. */
5922 	if (ic->ic_flags & IEEE80211_F_PMGTON)
5923 		(void)iwn_set_pslevel(sc, 0, 3, 1);
5924 
5925 	DPRINTF(sc, IWN_DEBUG_TRACE, "->%s: end\n",__func__);
5926 
5927 }
5928 
5929 static int
5930 iwn4965_init_gains(struct iwn_softc *sc)
5931 {
5932 	struct iwn_phy_calib_gain cmd;
5933 
5934 	DPRINTF(sc, IWN_DEBUG_TRACE, "->Doing %s\n", __func__);
5935 
5936 	memset(&cmd, 0, sizeof cmd);
5937 	cmd.code = IWN4965_PHY_CALIB_DIFF_GAIN;
5938 	/* Differential gains initially set to 0 for all 3 antennas. */
5939 	DPRINTF(sc, IWN_DEBUG_CALIBRATE,
5940 	    "%s: setting initial differential gains\n", __func__);
5941 	return iwn_cmd(sc, IWN_CMD_PHY_CALIB, &cmd, sizeof cmd, 1);
5942 }
5943 
5944 static int
5945 iwn5000_init_gains(struct iwn_softc *sc)
5946 {
5947 	struct iwn_phy_calib cmd;
5948 
5949 	DPRINTF(sc, IWN_DEBUG_TRACE, "->Doing %s\n", __func__);
5950 
5951 	memset(&cmd, 0, sizeof cmd);
5952 	cmd.code = sc->reset_noise_gain;
5953 	cmd.ngroups = 1;
5954 	cmd.isvalid = 1;
5955 	DPRINTF(sc, IWN_DEBUG_CALIBRATE,
5956 	    "%s: setting initial differential gains\n", __func__);
5957 	return iwn_cmd(sc, IWN_CMD_PHY_CALIB, &cmd, sizeof cmd, 1);
5958 }
5959 
5960 static int
5961 iwn4965_set_gains(struct iwn_softc *sc)
5962 {
5963 	struct iwn_calib_state *calib = &sc->calib;
5964 	struct iwn_phy_calib_gain cmd;
5965 	int i, delta, noise;
5966 
5967 	DPRINTF(sc, IWN_DEBUG_TRACE, "->Doing %s\n", __func__);
5968 
5969 	/* Get minimal noise among connected antennas. */
5970 	noise = INT_MAX;	/* NB: There's at least one antenna. */
5971 	for (i = 0; i < 3; i++)
5972 		if (sc->chainmask & (1 << i))
5973 			noise = MIN(calib->noise[i], noise);
5974 
5975 	memset(&cmd, 0, sizeof cmd);
5976 	cmd.code = IWN4965_PHY_CALIB_DIFF_GAIN;
5977 	/* Set differential gains for connected antennas. */
5978 	for (i = 0; i < 3; i++) {
5979 		if (sc->chainmask & (1 << i)) {
5980 			/* Compute attenuation (in unit of 1.5dB). */
5981 			delta = (noise - (int32_t)calib->noise[i]) / 30;
5982 			/* NB: delta <= 0 */
5983 			/* Limit to [-4.5dB,0]. */
5984 			cmd.gain[i] = MIN(abs(delta), 3);
5985 			if (delta < 0)
5986 				cmd.gain[i] |= 1 << 2;	/* sign bit */
5987 		}
5988 	}
5989 	DPRINTF(sc, IWN_DEBUG_CALIBRATE,
5990 	    "setting differential gains Ant A/B/C: %x/%x/%x (%x)\n",
5991 	    cmd.gain[0], cmd.gain[1], cmd.gain[2], sc->chainmask);
5992 	return iwn_cmd(sc, IWN_CMD_PHY_CALIB, &cmd, sizeof cmd, 1);
5993 }
5994 
5995 static int
5996 iwn5000_set_gains(struct iwn_softc *sc)
5997 {
5998 	struct iwn_calib_state *calib = &sc->calib;
5999 	struct iwn_phy_calib_gain cmd;
6000 	int i, ant, div, delta;
6001 
6002 	DPRINTF(sc, IWN_DEBUG_TRACE, "->Doing %s\n", __func__);
6003 
6004 	/* We collected 20 beacons and !=6050 need a 1.5 factor. */
6005 	div = (sc->hw_type == IWN_HW_REV_TYPE_6050) ? 20 : 30;
6006 
6007 	memset(&cmd, 0, sizeof cmd);
6008 	cmd.code = sc->noise_gain;
6009 	cmd.ngroups = 1;
6010 	cmd.isvalid = 1;
6011 	/* Get first available RX antenna as referential. */
6012 	ant = IWN_LSB(sc->rxchainmask);
6013 	/* Set differential gains for other antennas. */
6014 	for (i = ant + 1; i < 3; i++) {
6015 		if (sc->chainmask & (1 << i)) {
6016 			/* The delta is relative to antenna "ant". */
6017 			delta = ((int32_t)calib->noise[ant] -
6018 			    (int32_t)calib->noise[i]) / div;
6019 			/* Limit to [-4.5dB,+4.5dB]. */
6020 			cmd.gain[i - 1] = MIN(abs(delta), 3);
6021 			if (delta < 0)
6022 				cmd.gain[i - 1] |= 1 << 2;	/* sign bit */
6023 		}
6024 	}
6025 	DPRINTF(sc, IWN_DEBUG_CALIBRATE | IWN_DEBUG_XMIT,
6026 	    "setting differential gains Ant B/C: %x/%x (%x)\n",
6027 	    cmd.gain[0], cmd.gain[1], sc->chainmask);
6028 	return iwn_cmd(sc, IWN_CMD_PHY_CALIB, &cmd, sizeof cmd, 1);
6029 }
6030 
6031 /*
6032  * Tune RF RX sensitivity based on the number of false alarms detected
6033  * during the last beacon period.
6034  */
6035 static void
6036 iwn_tune_sensitivity(struct iwn_softc *sc, const struct iwn_rx_stats *stats)
6037 {
6038 #define inc(val, inc, max)			\
6039 	if ((val) < (max)) {			\
6040 		if ((val) < (max) - (inc))	\
6041 			(val) += (inc);		\
6042 		else				\
6043 			(val) = (max);		\
6044 		needs_update = 1;		\
6045 	}
6046 #define dec(val, dec, min)			\
6047 	if ((val) > (min)) {			\
6048 		if ((val) > (min) + (dec))	\
6049 			(val) -= (dec);		\
6050 		else				\
6051 			(val) = (min);		\
6052 		needs_update = 1;		\
6053 	}
6054 
6055 	const struct iwn_sensitivity_limits *limits = sc->limits;
6056 	struct iwn_calib_state *calib = &sc->calib;
6057 	uint32_t val, rxena, fa;
6058 	uint32_t energy[3], energy_min;
6059 	uint8_t noise[3], noise_ref;
6060 	int i, needs_update = 0;
6061 
6062 	DPRINTF(sc, IWN_DEBUG_TRACE, "->%s begin\n", __func__);
6063 
6064 	/* Check that we've been enabled long enough. */
6065 	if ((rxena = le32toh(stats->general.load)) == 0){
6066 		DPRINTF(sc, IWN_DEBUG_TRACE, "->%s end not so long\n", __func__);
6067 		return;
6068 	}
6069 
6070 	/* Compute number of false alarms since last call for OFDM. */
6071 	fa  = le32toh(stats->ofdm.bad_plcp) - calib->bad_plcp_ofdm;
6072 	fa += le32toh(stats->ofdm.fa) - calib->fa_ofdm;
6073 	fa *= 200 * IEEE80211_DUR_TU;	/* 200TU */
6074 
6075 	if (fa > 50 * rxena) {
6076 		/* High false alarm count, decrease sensitivity. */
6077 		DPRINTF(sc, IWN_DEBUG_CALIBRATE,
6078 		    "%s: OFDM high false alarm count: %u\n", __func__, fa);
6079 		inc(calib->ofdm_x1,     1, limits->max_ofdm_x1);
6080 		inc(calib->ofdm_mrc_x1, 1, limits->max_ofdm_mrc_x1);
6081 		inc(calib->ofdm_x4,     1, limits->max_ofdm_x4);
6082 		inc(calib->ofdm_mrc_x4, 1, limits->max_ofdm_mrc_x4);
6083 
6084 	} else if (fa < 5 * rxena) {
6085 		/* Low false alarm count, increase sensitivity. */
6086 		DPRINTF(sc, IWN_DEBUG_CALIBRATE,
6087 		    "%s: OFDM low false alarm count: %u\n", __func__, fa);
6088 		dec(calib->ofdm_x1,     1, limits->min_ofdm_x1);
6089 		dec(calib->ofdm_mrc_x1, 1, limits->min_ofdm_mrc_x1);
6090 		dec(calib->ofdm_x4,     1, limits->min_ofdm_x4);
6091 		dec(calib->ofdm_mrc_x4, 1, limits->min_ofdm_mrc_x4);
6092 	}
6093 
6094 	/* Compute maximum noise among 3 receivers. */
6095 	for (i = 0; i < 3; i++)
6096 		noise[i] = (le32toh(stats->general.noise[i]) >> 8) & 0xff;
6097 	val = MAX(noise[0], noise[1]);
6098 	val = MAX(noise[2], val);
6099 	/* Insert it into our samples table. */
6100 	calib->noise_samples[calib->cur_noise_sample] = val;
6101 	calib->cur_noise_sample = (calib->cur_noise_sample + 1) % 20;
6102 
6103 	/* Compute maximum noise among last 20 samples. */
6104 	noise_ref = calib->noise_samples[0];
6105 	for (i = 1; i < 20; i++)
6106 		noise_ref = MAX(noise_ref, calib->noise_samples[i]);
6107 
6108 	/* Compute maximum energy among 3 receivers. */
6109 	for (i = 0; i < 3; i++)
6110 		energy[i] = le32toh(stats->general.energy[i]);
6111 	val = MIN(energy[0], energy[1]);
6112 	val = MIN(energy[2], val);
6113 	/* Insert it into our samples table. */
6114 	calib->energy_samples[calib->cur_energy_sample] = val;
6115 	calib->cur_energy_sample = (calib->cur_energy_sample + 1) % 10;
6116 
6117 	/* Compute minimum energy among last 10 samples. */
6118 	energy_min = calib->energy_samples[0];
6119 	for (i = 1; i < 10; i++)
6120 		energy_min = MAX(energy_min, calib->energy_samples[i]);
6121 	energy_min += 6;
6122 
6123 	/* Compute number of false alarms since last call for CCK. */
6124 	fa  = le32toh(stats->cck.bad_plcp) - calib->bad_plcp_cck;
6125 	fa += le32toh(stats->cck.fa) - calib->fa_cck;
6126 	fa *= 200 * IEEE80211_DUR_TU;	/* 200TU */
6127 
6128 	if (fa > 50 * rxena) {
6129 		/* High false alarm count, decrease sensitivity. */
6130 		DPRINTF(sc, IWN_DEBUG_CALIBRATE,
6131 		    "%s: CCK high false alarm count: %u\n", __func__, fa);
6132 		calib->cck_state = IWN_CCK_STATE_HIFA;
6133 		calib->low_fa = 0;
6134 
6135 		if (calib->cck_x4 > 160) {
6136 			calib->noise_ref = noise_ref;
6137 			if (calib->energy_cck > 2)
6138 				dec(calib->energy_cck, 2, energy_min);
6139 		}
6140 		if (calib->cck_x4 < 160) {
6141 			calib->cck_x4 = 161;
6142 			needs_update = 1;
6143 		} else
6144 			inc(calib->cck_x4, 3, limits->max_cck_x4);
6145 
6146 		inc(calib->cck_mrc_x4, 3, limits->max_cck_mrc_x4);
6147 
6148 	} else if (fa < 5 * rxena) {
6149 		/* Low false alarm count, increase sensitivity. */
6150 		DPRINTF(sc, IWN_DEBUG_CALIBRATE,
6151 		    "%s: CCK low false alarm count: %u\n", __func__, fa);
6152 		calib->cck_state = IWN_CCK_STATE_LOFA;
6153 		calib->low_fa++;
6154 
6155 		if (calib->cck_state != IWN_CCK_STATE_INIT &&
6156 		    (((int32_t)calib->noise_ref - (int32_t)noise_ref) > 2 ||
6157 		     calib->low_fa > 100)) {
6158 			inc(calib->energy_cck, 2, limits->min_energy_cck);
6159 			dec(calib->cck_x4,     3, limits->min_cck_x4);
6160 			dec(calib->cck_mrc_x4, 3, limits->min_cck_mrc_x4);
6161 		}
6162 	} else {
6163 		/* Not worth to increase or decrease sensitivity. */
6164 		DPRINTF(sc, IWN_DEBUG_CALIBRATE,
6165 		    "%s: CCK normal false alarm count: %u\n", __func__, fa);
6166 		calib->low_fa = 0;
6167 		calib->noise_ref = noise_ref;
6168 
6169 		if (calib->cck_state == IWN_CCK_STATE_HIFA) {
6170 			/* Previous interval had many false alarms. */
6171 			dec(calib->energy_cck, 8, energy_min);
6172 		}
6173 		calib->cck_state = IWN_CCK_STATE_INIT;
6174 	}
6175 
6176 	if (needs_update)
6177 		(void)iwn_send_sensitivity(sc);
6178 
6179 	DPRINTF(sc, IWN_DEBUG_TRACE, "->%s: end\n",__func__);
6180 
6181 #undef dec
6182 #undef inc
6183 }
6184 
6185 static int
6186 iwn_send_sensitivity(struct iwn_softc *sc)
6187 {
6188 	struct iwn_calib_state *calib = &sc->calib;
6189 	struct iwn_enhanced_sensitivity_cmd cmd;
6190 	int len;
6191 
6192 	memset(&cmd, 0, sizeof cmd);
6193 	len = sizeof (struct iwn_sensitivity_cmd);
6194 	cmd.which = IWN_SENSITIVITY_WORKTBL;
6195 	/* OFDM modulation. */
6196 	cmd.corr_ofdm_x1       = htole16(calib->ofdm_x1);
6197 	cmd.corr_ofdm_mrc_x1   = htole16(calib->ofdm_mrc_x1);
6198 	cmd.corr_ofdm_x4       = htole16(calib->ofdm_x4);
6199 	cmd.corr_ofdm_mrc_x4   = htole16(calib->ofdm_mrc_x4);
6200 	cmd.energy_ofdm        = htole16(sc->limits->energy_ofdm);
6201 	cmd.energy_ofdm_th     = htole16(62);
6202 	/* CCK modulation. */
6203 	cmd.corr_cck_x4        = htole16(calib->cck_x4);
6204 	cmd.corr_cck_mrc_x4    = htole16(calib->cck_mrc_x4);
6205 	cmd.energy_cck         = htole16(calib->energy_cck);
6206 	/* Barker modulation: use default values. */
6207 	cmd.corr_barker        = htole16(190);
6208 	cmd.corr_barker_mrc    = htole16(sc->limits->barker_mrc);
6209 
6210 	DPRINTF(sc, IWN_DEBUG_CALIBRATE,
6211 	    "%s: set sensitivity %d/%d/%d/%d/%d/%d/%d\n", __func__,
6212 	    calib->ofdm_x1, calib->ofdm_mrc_x1, calib->ofdm_x4,
6213 	    calib->ofdm_mrc_x4, calib->cck_x4,
6214 	    calib->cck_mrc_x4, calib->energy_cck);
6215 
6216 	if (!(sc->sc_flags & IWN_FLAG_ENH_SENS))
6217 		goto send;
6218 	/* Enhanced sensitivity settings. */
6219 	len = sizeof (struct iwn_enhanced_sensitivity_cmd);
6220 	cmd.ofdm_det_slope_mrc = htole16(668);
6221 	cmd.ofdm_det_icept_mrc = htole16(4);
6222 	cmd.ofdm_det_slope     = htole16(486);
6223 	cmd.ofdm_det_icept     = htole16(37);
6224 	cmd.cck_det_slope_mrc  = htole16(853);
6225 	cmd.cck_det_icept_mrc  = htole16(4);
6226 	cmd.cck_det_slope      = htole16(476);
6227 	cmd.cck_det_icept      = htole16(99);
6228 send:
6229 	return iwn_cmd(sc, IWN_CMD_SET_SENSITIVITY, &cmd, len, 1);
6230 }
6231 
6232 /*
6233  * Look at the increase of PLCP errors over time; if it exceeds
6234  * a programmed threshold then trigger an RF retune.
6235  */
6236 static void
6237 iwn_check_rx_recovery(struct iwn_softc *sc, struct iwn_stats *rs)
6238 {
6239 	int32_t delta_ofdm, delta_ht, delta_cck;
6240 	struct iwn_calib_state *calib = &sc->calib;
6241 	int delta_ticks, cur_ticks;
6242 	int delta_msec;
6243 	int thresh;
6244 
6245 	/*
6246 	 * Calculate the difference between the current and
6247 	 * previous statistics.
6248 	 */
6249 	delta_cck = le32toh(rs->rx.cck.bad_plcp) - calib->bad_plcp_cck;
6250 	delta_ofdm = le32toh(rs->rx.ofdm.bad_plcp) - calib->bad_plcp_ofdm;
6251 	delta_ht = le32toh(rs->rx.ht.bad_plcp) - calib->bad_plcp_ht;
6252 
6253 	/*
6254 	 * Calculate the delta in time between successive statistics
6255 	 * messages.  Yes, it can roll over; so we make sure that
6256 	 * this doesn't happen.
6257 	 *
6258 	 * XXX go figure out what to do about rollover
6259 	 * XXX go figure out what to do if ticks rolls over to -ve instead!
6260 	 * XXX go stab signed integer overflow undefined-ness in the face.
6261 	 */
6262 	cur_ticks = ticks;
6263 	delta_ticks = cur_ticks - sc->last_calib_ticks;
6264 
6265 	/*
6266 	 * If any are negative, then the firmware likely reset; so just
6267 	 * bail.  We'll pick this up next time.
6268 	 */
6269 	if (delta_cck < 0 || delta_ofdm < 0 || delta_ht < 0 || delta_ticks < 0)
6270 		return;
6271 
6272 	/*
6273 	 * delta_ticks is in ticks; we need to convert it up to milliseconds
6274 	 * so we can do some useful math with it.
6275 	 */
6276 	delta_msec = ticks_to_msecs(delta_ticks);
6277 
6278 	/*
6279 	 * Calculate what our threshold is given the current delta_msec.
6280 	 */
6281 	thresh = sc->base_params->plcp_err_threshold * delta_msec;
6282 
6283 	DPRINTF(sc, IWN_DEBUG_STATE,
6284 	    "%s: time delta: %d; cck=%d, ofdm=%d, ht=%d, total=%d, thresh=%d\n",
6285 	    __func__,
6286 	    delta_msec,
6287 	    delta_cck,
6288 	    delta_ofdm,
6289 	    delta_ht,
6290 	    (delta_msec + delta_cck + delta_ofdm + delta_ht),
6291 	    thresh);
6292 
6293 	/*
6294 	 * If we need a retune, then schedule a single channel scan
6295 	 * to a channel that isn't the currently active one!
6296 	 *
6297 	 * The math from linux iwlwifi:
6298 	 *
6299 	 * if ((delta * 100 / msecs) > threshold)
6300 	 */
6301 	if (thresh > 0 && (delta_cck + delta_ofdm + delta_ht) * 100 > thresh) {
6302 		DPRINTF(sc, IWN_DEBUG_ANY,
6303 		    "%s: PLCP error threshold raw (%d) comparison (%d) "
6304 		    "over limit (%d); retune!\n",
6305 		    __func__,
6306 		    (delta_cck + delta_ofdm + delta_ht),
6307 		    (delta_cck + delta_ofdm + delta_ht) * 100,
6308 		    thresh);
6309 	}
6310 }
6311 
6312 /*
6313  * Set STA mode power saving level (between 0 and 5).
6314  * Level 0 is CAM (Continuously Aware Mode), 5 is for maximum power saving.
6315  */
6316 static int
6317 iwn_set_pslevel(struct iwn_softc *sc, int dtim, int level, int async)
6318 {
6319 	struct iwn_pmgt_cmd cmd;
6320 	const struct iwn_pmgt *pmgt;
6321 	uint32_t max, skip_dtim;
6322 	uint32_t reg;
6323 	int i;
6324 
6325 	DPRINTF(sc, IWN_DEBUG_PWRSAVE,
6326 	    "%s: dtim=%d, level=%d, async=%d\n",
6327 	    __func__,
6328 	    dtim,
6329 	    level,
6330 	    async);
6331 
6332 	/* Select which PS parameters to use. */
6333 	if (dtim <= 2)
6334 		pmgt = &iwn_pmgt[0][level];
6335 	else if (dtim <= 10)
6336 		pmgt = &iwn_pmgt[1][level];
6337 	else
6338 		pmgt = &iwn_pmgt[2][level];
6339 
6340 	memset(&cmd, 0, sizeof cmd);
6341 	if (level != 0)	/* not CAM */
6342 		cmd.flags |= htole16(IWN_PS_ALLOW_SLEEP);
6343 	if (level == 5)
6344 		cmd.flags |= htole16(IWN_PS_FAST_PD);
6345 	/* Retrieve PCIe Active State Power Management (ASPM). */
6346 	reg = pci_read_config(sc->sc_dev, sc->sc_cap_off + 0x10, 1);
6347 	if (!(reg & 0x1))	/* L0s Entry disabled. */
6348 		cmd.flags |= htole16(IWN_PS_PCI_PMGT);
6349 	cmd.rxtimeout = htole32(pmgt->rxtimeout * 1024);
6350 	cmd.txtimeout = htole32(pmgt->txtimeout * 1024);
6351 
6352 	if (dtim == 0) {
6353 		dtim = 1;
6354 		skip_dtim = 0;
6355 	} else
6356 		skip_dtim = pmgt->skip_dtim;
6357 	if (skip_dtim != 0) {
6358 		cmd.flags |= htole16(IWN_PS_SLEEP_OVER_DTIM);
6359 		max = pmgt->intval[4];
6360 		if (max == (uint32_t)-1)
6361 			max = dtim * (skip_dtim + 1);
6362 		else if (max > dtim)
6363 			max = (max / dtim) * dtim;
6364 	} else
6365 		max = dtim;
6366 	for (i = 0; i < 5; i++)
6367 		cmd.intval[i] = htole32(MIN(max, pmgt->intval[i]));
6368 
6369 	DPRINTF(sc, IWN_DEBUG_RESET, "setting power saving level to %d\n",
6370 	    level);
6371 	return iwn_cmd(sc, IWN_CMD_SET_POWER_MODE, &cmd, sizeof cmd, async);
6372 }
6373 
6374 static int
6375 iwn_send_btcoex(struct iwn_softc *sc)
6376 {
6377 	struct iwn_bluetooth cmd;
6378 
6379 	memset(&cmd, 0, sizeof cmd);
6380 	cmd.flags = IWN_BT_COEX_CHAN_ANN | IWN_BT_COEX_BT_PRIO;
6381 	cmd.lead_time = IWN_BT_LEAD_TIME_DEF;
6382 	cmd.max_kill = IWN_BT_MAX_KILL_DEF;
6383 	DPRINTF(sc, IWN_DEBUG_RESET, "%s: configuring bluetooth coexistence\n",
6384 	    __func__);
6385 	return iwn_cmd(sc, IWN_CMD_BT_COEX, &cmd, sizeof(cmd), 0);
6386 }
6387 
6388 static int
6389 iwn_send_advanced_btcoex(struct iwn_softc *sc)
6390 {
6391 	static const uint32_t btcoex_3wire[12] = {
6392 		0xaaaaaaaa, 0xaaaaaaaa, 0xaeaaaaaa, 0xaaaaaaaa,
6393 		0xcc00ff28, 0x0000aaaa, 0xcc00aaaa, 0x0000aaaa,
6394 		0xc0004000, 0x00004000, 0xf0005000, 0xf0005000,
6395 	};
6396 	struct iwn6000_btcoex_config btconfig;
6397 	struct iwn2000_btcoex_config btconfig2k;
6398 	struct iwn_btcoex_priotable btprio;
6399 	struct iwn_btcoex_prot btprot;
6400 	int error, i;
6401 	uint8_t flags;
6402 
6403 	memset(&btconfig, 0, sizeof btconfig);
6404 	memset(&btconfig2k, 0, sizeof btconfig2k);
6405 
6406 	flags = IWN_BT_FLAG_COEX6000_MODE_3W <<
6407 	    IWN_BT_FLAG_COEX6000_MODE_SHIFT; // Done as is in linux kernel 3.2
6408 
6409 	if (sc->base_params->bt_sco_disable)
6410 		flags &= ~IWN_BT_FLAG_SYNC_2_BT_DISABLE;
6411 	else
6412 		flags |= IWN_BT_FLAG_SYNC_2_BT_DISABLE;
6413 
6414 	flags |= IWN_BT_FLAG_COEX6000_CHAN_INHIBITION;
6415 
6416 	/* Default flags result is 145 as old value */
6417 
6418 	/*
6419 	 * Flags value has to be review. Values must change if we
6420 	 * which to disable it
6421 	 */
6422 	if (sc->base_params->bt_session_2) {
6423 		btconfig2k.flags = flags;
6424 		btconfig2k.max_kill = 5;
6425 		btconfig2k.bt3_t7_timer = 1;
6426 		btconfig2k.kill_ack = htole32(0xffff0000);
6427 		btconfig2k.kill_cts = htole32(0xffff0000);
6428 		btconfig2k.sample_time = 2;
6429 		btconfig2k.bt3_t2_timer = 0xc;
6430 
6431 		for (i = 0; i < 12; i++)
6432 			btconfig2k.lookup_table[i] = htole32(btcoex_3wire[i]);
6433 		btconfig2k.valid = htole16(0xff);
6434 		btconfig2k.prio_boost = htole32(0xf0);
6435 		DPRINTF(sc, IWN_DEBUG_RESET,
6436 		    "%s: configuring advanced bluetooth coexistence"
6437 		    " session 2, flags : 0x%x\n",
6438 		    __func__,
6439 		    flags);
6440 		error = iwn_cmd(sc, IWN_CMD_BT_COEX, &btconfig2k,
6441 		    sizeof(btconfig2k), 1);
6442 	} else {
6443 		btconfig.flags = flags;
6444 		btconfig.max_kill = 5;
6445 		btconfig.bt3_t7_timer = 1;
6446 		btconfig.kill_ack = htole32(0xffff0000);
6447 		btconfig.kill_cts = htole32(0xffff0000);
6448 		btconfig.sample_time = 2;
6449 		btconfig.bt3_t2_timer = 0xc;
6450 
6451 		for (i = 0; i < 12; i++)
6452 			btconfig.lookup_table[i] = htole32(btcoex_3wire[i]);
6453 		btconfig.valid = htole16(0xff);
6454 		btconfig.prio_boost = 0xf0;
6455 		DPRINTF(sc, IWN_DEBUG_RESET,
6456 		    "%s: configuring advanced bluetooth coexistence,"
6457 		    " flags : 0x%x\n",
6458 		    __func__,
6459 		    flags);
6460 		error = iwn_cmd(sc, IWN_CMD_BT_COEX, &btconfig,
6461 		    sizeof(btconfig), 1);
6462 	}
6463 
6464 	if (error != 0)
6465 		return error;
6466 
6467 	memset(&btprio, 0, sizeof btprio);
6468 	btprio.calib_init1 = 0x6;
6469 	btprio.calib_init2 = 0x7;
6470 	btprio.calib_periodic_low1 = 0x2;
6471 	btprio.calib_periodic_low2 = 0x3;
6472 	btprio.calib_periodic_high1 = 0x4;
6473 	btprio.calib_periodic_high2 = 0x5;
6474 	btprio.dtim = 0x6;
6475 	btprio.scan52 = 0x8;
6476 	btprio.scan24 = 0xa;
6477 	error = iwn_cmd(sc, IWN_CMD_BT_COEX_PRIOTABLE, &btprio, sizeof(btprio),
6478 	    1);
6479 	if (error != 0)
6480 		return error;
6481 
6482 	/* Force BT state machine change. */
6483 	memset(&btprot, 0, sizeof btprot);
6484 	btprot.open = 1;
6485 	btprot.type = 1;
6486 	error = iwn_cmd(sc, IWN_CMD_BT_COEX_PROT, &btprot, sizeof(btprot), 1);
6487 	if (error != 0)
6488 		return error;
6489 	btprot.open = 0;
6490 	return iwn_cmd(sc, IWN_CMD_BT_COEX_PROT, &btprot, sizeof(btprot), 1);
6491 }
6492 
6493 static int
6494 iwn5000_runtime_calib(struct iwn_softc *sc)
6495 {
6496 	struct iwn5000_calib_config cmd;
6497 
6498 	memset(&cmd, 0, sizeof cmd);
6499 	cmd.ucode.once.enable = 0xffffffff;
6500 	cmd.ucode.once.start = IWN5000_CALIB_DC;
6501 	DPRINTF(sc, IWN_DEBUG_CALIBRATE,
6502 	    "%s: configuring runtime calibration\n", __func__);
6503 	return iwn_cmd(sc, IWN5000_CMD_CALIB_CONFIG, &cmd, sizeof(cmd), 0);
6504 }
6505 
6506 static int
6507 iwn_config(struct iwn_softc *sc)
6508 {
6509 	struct iwn_ops *ops = &sc->ops;
6510 	struct ifnet *ifp = sc->sc_ifp;
6511 	struct ieee80211com *ic = ifp->if_l2com;
6512 	uint32_t txmask;
6513 	uint16_t rxchain;
6514 	int error;
6515 
6516 	DPRINTF(sc, IWN_DEBUG_TRACE, "->%s begin\n", __func__);
6517 
6518 	if ((sc->base_params->calib_need & IWN_FLG_NEED_PHY_CALIB_TEMP_OFFSET)
6519 	    && (sc->base_params->calib_need & IWN_FLG_NEED_PHY_CALIB_TEMP_OFFSETv2)) {
6520 		device_printf(sc->sc_dev,"%s: temp_offset and temp_offsetv2 are"
6521 		    " exclusive each together. Review NIC config file. Conf"
6522 		    " :  0x%08x Flags :  0x%08x  \n", __func__,
6523 		    sc->base_params->calib_need,
6524 		    (IWN_FLG_NEED_PHY_CALIB_TEMP_OFFSET |
6525 		    IWN_FLG_NEED_PHY_CALIB_TEMP_OFFSETv2));
6526 		return (EINVAL);
6527 	}
6528 
6529 	/* Compute temperature calib if needed. Will be send by send calib */
6530 	if (sc->base_params->calib_need & IWN_FLG_NEED_PHY_CALIB_TEMP_OFFSET) {
6531 		error = iwn5000_temp_offset_calib(sc);
6532 		if (error != 0) {
6533 			device_printf(sc->sc_dev,
6534 			    "%s: could not set temperature offset\n", __func__);
6535 			return (error);
6536 		}
6537 	} else if (sc->base_params->calib_need & IWN_FLG_NEED_PHY_CALIB_TEMP_OFFSETv2) {
6538 		error = iwn5000_temp_offset_calibv2(sc);
6539 		if (error != 0) {
6540 			device_printf(sc->sc_dev,
6541 			    "%s: could not compute temperature offset v2\n",
6542 			    __func__);
6543 			return (error);
6544 		}
6545 	}
6546 
6547 	if (sc->hw_type == IWN_HW_REV_TYPE_6050) {
6548 		/* Configure runtime DC calibration. */
6549 		error = iwn5000_runtime_calib(sc);
6550 		if (error != 0) {
6551 			device_printf(sc->sc_dev,
6552 			    "%s: could not configure runtime calibration\n",
6553 			    __func__);
6554 			return error;
6555 		}
6556 	}
6557 
6558 	/* Configure valid TX chains for >=5000 Series. */
6559 	if (sc->hw_type != IWN_HW_REV_TYPE_4965 &&
6560 	    IWN_UCODE_API(sc->ucode_rev) > 1) {
6561 		txmask = htole32(sc->txchainmask);
6562 		DPRINTF(sc, IWN_DEBUG_RESET | IWN_DEBUG_XMIT,
6563 		    "%s: configuring valid TX chains 0x%x\n", __func__, txmask);
6564 		error = iwn_cmd(sc, IWN5000_CMD_TX_ANT_CONFIG, &txmask,
6565 		    sizeof txmask, 0);
6566 		if (error != 0) {
6567 			device_printf(sc->sc_dev,
6568 			    "%s: could not configure valid TX chains, "
6569 			    "error %d\n", __func__, error);
6570 			return error;
6571 		}
6572 	}
6573 
6574 	/* Configure bluetooth coexistence. */
6575 	error = 0;
6576 
6577 	/* Configure bluetooth coexistence if needed. */
6578 	if (sc->base_params->bt_mode == IWN_BT_ADVANCED)
6579 		error = iwn_send_advanced_btcoex(sc);
6580 	if (sc->base_params->bt_mode == IWN_BT_SIMPLE)
6581 		error = iwn_send_btcoex(sc);
6582 
6583 	if (error != 0) {
6584 		device_printf(sc->sc_dev,
6585 		    "%s: could not configure bluetooth coexistence, error %d\n",
6586 		    __func__, error);
6587 		return error;
6588 	}
6589 
6590 	/* Set mode, channel, RX filter and enable RX. */
6591 	sc->rxon = &sc->rx_on[IWN_RXON_BSS_CTX];
6592 	memset(sc->rxon, 0, sizeof (struct iwn_rxon));
6593 	IEEE80211_ADDR_COPY(sc->rxon->myaddr, IF_LLADDR(ifp));
6594 	IEEE80211_ADDR_COPY(sc->rxon->wlap, IF_LLADDR(ifp));
6595 	sc->rxon->chan = ieee80211_chan2ieee(ic, ic->ic_curchan);
6596 	sc->rxon->flags = htole32(IWN_RXON_TSF | IWN_RXON_CTS_TO_SELF);
6597 	if (IEEE80211_IS_CHAN_2GHZ(ic->ic_curchan))
6598 		sc->rxon->flags |= htole32(IWN_RXON_AUTO | IWN_RXON_24GHZ);
6599 	switch (ic->ic_opmode) {
6600 	case IEEE80211_M_STA:
6601 		sc->rxon->mode = IWN_MODE_STA;
6602 		sc->rxon->filter = htole32(IWN_FILTER_MULTICAST);
6603 		break;
6604 	case IEEE80211_M_MONITOR:
6605 		sc->rxon->mode = IWN_MODE_MONITOR;
6606 		sc->rxon->filter = htole32(IWN_FILTER_MULTICAST |
6607 		    IWN_FILTER_CTL | IWN_FILTER_PROMISC);
6608 		break;
6609 	default:
6610 		/* Should not get there. */
6611 		break;
6612 	}
6613 	sc->rxon->cck_mask  = 0x0f;	/* not yet negotiated */
6614 	sc->rxon->ofdm_mask = 0xff;	/* not yet negotiated */
6615 	sc->rxon->ht_single_mask = 0xff;
6616 	sc->rxon->ht_dual_mask = 0xff;
6617 	sc->rxon->ht_triple_mask = 0xff;
6618 	/*
6619 	 * In active association mode, ensure that
6620 	 * all the receive chains are enabled.
6621 	 *
6622 	 * Since we're not yet doing SMPS, don't allow the
6623 	 * number of idle RX chains to be less than the active
6624 	 * number.
6625 	 */
6626 	rxchain =
6627 	    IWN_RXCHAIN_VALID(sc->rxchainmask) |
6628 	    IWN_RXCHAIN_MIMO_COUNT(sc->nrxchains) |
6629 	    IWN_RXCHAIN_IDLE_COUNT(sc->nrxchains);
6630 	sc->rxon->rxchain = htole16(rxchain);
6631 	DPRINTF(sc, IWN_DEBUG_RESET | IWN_DEBUG_XMIT,
6632 	    "%s: rxchainmask=0x%x, nrxchains=%d\n",
6633 	    __func__,
6634 	    sc->rxchainmask,
6635 	    sc->nrxchains);
6636 	DPRINTF(sc, IWN_DEBUG_RESET, "%s: setting configuration\n", __func__);
6637 	if (sc->sc_is_scanning)
6638 		device_printf(sc->sc_dev,
6639 		    "%s: is_scanning set, before RXON\n",
6640 		    __func__);
6641 	error = iwn_cmd(sc, IWN_CMD_RXON, sc->rxon, sc->rxonsz, 0);
6642 	if (error != 0) {
6643 		device_printf(sc->sc_dev, "%s: RXON command failed\n",
6644 		    __func__);
6645 		return error;
6646 	}
6647 
6648 	if ((error = iwn_add_broadcast_node(sc, 0)) != 0) {
6649 		device_printf(sc->sc_dev, "%s: could not add broadcast node\n",
6650 		    __func__);
6651 		return error;
6652 	}
6653 
6654 	/* Configuration has changed, set TX power accordingly. */
6655 	if ((error = ops->set_txpower(sc, ic->ic_curchan, 0)) != 0) {
6656 		device_printf(sc->sc_dev, "%s: could not set TX power\n",
6657 		    __func__);
6658 		return error;
6659 	}
6660 
6661 	if ((error = iwn_set_critical_temp(sc)) != 0) {
6662 		device_printf(sc->sc_dev,
6663 		    "%s: could not set critical temperature\n", __func__);
6664 		return error;
6665 	}
6666 
6667 	/* Set power saving level to CAM during initialization. */
6668 	if ((error = iwn_set_pslevel(sc, 0, 0, 0)) != 0) {
6669 		device_printf(sc->sc_dev,
6670 		    "%s: could not set power saving level\n", __func__);
6671 		return error;
6672 	}
6673 
6674 	DPRINTF(sc, IWN_DEBUG_TRACE, "->%s: end\n",__func__);
6675 
6676 	return 0;
6677 }
6678 
6679 static uint16_t
6680 iwn_get_active_dwell_time(struct iwn_softc *sc,
6681     struct ieee80211_channel *c, uint8_t n_probes)
6682 {
6683 	/* No channel? Default to 2GHz settings */
6684 	if (c == NULL || IEEE80211_IS_CHAN_2GHZ(c)) {
6685 		return (IWN_ACTIVE_DWELL_TIME_2GHZ +
6686 		IWN_ACTIVE_DWELL_FACTOR_2GHZ * (n_probes + 1));
6687 	}
6688 
6689 	/* 5GHz dwell time */
6690 	return (IWN_ACTIVE_DWELL_TIME_5GHZ +
6691 	    IWN_ACTIVE_DWELL_FACTOR_5GHZ * (n_probes + 1));
6692 }
6693 
6694 /*
6695  * Limit the total dwell time to 85% of the beacon interval.
6696  *
6697  * Returns the dwell time in milliseconds.
6698  */
6699 static uint16_t
6700 iwn_limit_dwell(struct iwn_softc *sc, uint16_t dwell_time)
6701 {
6702 	struct ieee80211com *ic = sc->sc_ifp->if_l2com;
6703 	struct ieee80211vap *vap = NULL;
6704 	int bintval = 0;
6705 
6706 	/* bintval is in TU (1.024mS) */
6707 	if (! TAILQ_EMPTY(&ic->ic_vaps)) {
6708 		vap = TAILQ_FIRST(&ic->ic_vaps);
6709 		bintval = vap->iv_bss->ni_intval;
6710 	}
6711 
6712 	/*
6713 	 * If it's non-zero, we should calculate the minimum of
6714 	 * it and the DWELL_BASE.
6715 	 *
6716 	 * XXX Yes, the math should take into account that bintval
6717 	 * is 1.024mS, not 1mS..
6718 	 */
6719 	if (bintval > 0) {
6720 		DPRINTF(sc, IWN_DEBUG_SCAN,
6721 		    "%s: bintval=%d\n",
6722 		    __func__,
6723 		    bintval);
6724 		return (MIN(IWN_PASSIVE_DWELL_BASE, ((bintval * 85) / 100)));
6725 	}
6726 
6727 	/* No association context? Default */
6728 	return (IWN_PASSIVE_DWELL_BASE);
6729 }
6730 
6731 static uint16_t
6732 iwn_get_passive_dwell_time(struct iwn_softc *sc, struct ieee80211_channel *c)
6733 {
6734 	uint16_t passive;
6735 
6736 	if (c == NULL || IEEE80211_IS_CHAN_2GHZ(c)) {
6737 		passive = IWN_PASSIVE_DWELL_BASE + IWN_PASSIVE_DWELL_TIME_2GHZ;
6738 	} else {
6739 		passive = IWN_PASSIVE_DWELL_BASE + IWN_PASSIVE_DWELL_TIME_5GHZ;
6740 	}
6741 
6742 	/* Clamp to the beacon interval if we're associated */
6743 	return (iwn_limit_dwell(sc, passive));
6744 }
6745 
6746 static int
6747 iwn_scan(struct iwn_softc *sc, struct ieee80211vap *vap,
6748     struct ieee80211_scan_state *ss, struct ieee80211_channel *c)
6749 {
6750 	struct ifnet *ifp = sc->sc_ifp;
6751 	struct ieee80211com *ic = ifp->if_l2com;
6752 	struct ieee80211_node *ni = vap->iv_bss;
6753 	struct iwn_scan_hdr *hdr;
6754 	struct iwn_cmd_data *tx;
6755 	struct iwn_scan_essid *essid;
6756 	struct iwn_scan_chan *chan;
6757 	struct ieee80211_frame *wh;
6758 	struct ieee80211_rateset *rs;
6759 	uint8_t *buf, *frm;
6760 	uint16_t rxchain;
6761 	uint8_t txant;
6762 	int buflen, error;
6763 	int is_active;
6764 	uint16_t dwell_active, dwell_passive;
6765 	uint32_t extra, scan_service_time;
6766 
6767 	DPRINTF(sc, IWN_DEBUG_TRACE, "->%s begin\n", __func__);
6768 
6769 	/*
6770 	 * We are absolutely not allowed to send a scan command when another
6771 	 * scan command is pending.
6772 	 */
6773 	if (sc->sc_is_scanning) {
6774 		device_printf(sc->sc_dev, "%s: called whilst scanning!\n",
6775 		    __func__);
6776 		return (EAGAIN);
6777 	}
6778 
6779 	/* Assign the scan channel */
6780 	c = ic->ic_curchan;
6781 
6782 	sc->rxon = &sc->rx_on[IWN_RXON_BSS_CTX];
6783 	buf = malloc(IWN_SCAN_MAXSZ, M_DEVBUF, M_NOWAIT | M_ZERO);
6784 	if (buf == NULL) {
6785 		device_printf(sc->sc_dev,
6786 		    "%s: could not allocate buffer for scan command\n",
6787 		    __func__);
6788 		return ENOMEM;
6789 	}
6790 	hdr = (struct iwn_scan_hdr *)buf;
6791 	/*
6792 	 * Move to the next channel if no frames are received within 10ms
6793 	 * after sending the probe request.
6794 	 */
6795 	hdr->quiet_time = htole16(10);		/* timeout in milliseconds */
6796 	hdr->quiet_threshold = htole16(1);	/* min # of packets */
6797 	/*
6798 	 * Max needs to be greater than active and passive and quiet!
6799 	 * It's also in microseconds!
6800 	 */
6801 	hdr->max_svc = htole32(250 * 1024);
6802 
6803 	/*
6804 	 * Reset scan: interval=100
6805 	 * Normal scan: interval=becaon interval
6806 	 * suspend_time: 100 (TU)
6807 	 *
6808 	 */
6809 	extra = (100 /* suspend_time */ / 100 /* beacon interval */) << 22;
6810 	//scan_service_time = extra | ((100 /* susp */ % 100 /* int */) * 1024);
6811 	scan_service_time = (4 << 22) | (100 * 1024);	/* Hardcode for now! */
6812 	hdr->pause_svc = htole32(scan_service_time);
6813 
6814 	/* Select antennas for scanning. */
6815 	rxchain =
6816 	    IWN_RXCHAIN_VALID(sc->rxchainmask) |
6817 	    IWN_RXCHAIN_FORCE_MIMO_SEL(sc->rxchainmask) |
6818 	    IWN_RXCHAIN_DRIVER_FORCE;
6819 	if (IEEE80211_IS_CHAN_A(c) &&
6820 	    sc->hw_type == IWN_HW_REV_TYPE_4965) {
6821 		/* Ant A must be avoided in 5GHz because of an HW bug. */
6822 		rxchain |= IWN_RXCHAIN_FORCE_SEL(IWN_ANT_B);
6823 	} else	/* Use all available RX antennas. */
6824 		rxchain |= IWN_RXCHAIN_FORCE_SEL(sc->rxchainmask);
6825 	hdr->rxchain = htole16(rxchain);
6826 	hdr->filter = htole32(IWN_FILTER_MULTICAST | IWN_FILTER_BEACON);
6827 
6828 	tx = (struct iwn_cmd_data *)(hdr + 1);
6829 	tx->flags = htole32(IWN_TX_AUTO_SEQ);
6830 	tx->id = sc->broadcast_id;
6831 	tx->lifetime = htole32(IWN_LIFETIME_INFINITE);
6832 
6833 	if (IEEE80211_IS_CHAN_5GHZ(c)) {
6834 		/* Send probe requests at 6Mbps. */
6835 		tx->rate = htole32(0xd);
6836 		rs = &ic->ic_sup_rates[IEEE80211_MODE_11A];
6837 	} else {
6838 		hdr->flags = htole32(IWN_RXON_24GHZ | IWN_RXON_AUTO);
6839 		if (sc->hw_type == IWN_HW_REV_TYPE_4965 &&
6840 		    sc->rxon->associd && sc->rxon->chan > 14)
6841 			tx->rate = htole32(0xd);
6842 		else {
6843 			/* Send probe requests at 1Mbps. */
6844 			tx->rate = htole32(10 | IWN_RFLAG_CCK);
6845 		}
6846 		rs = &ic->ic_sup_rates[IEEE80211_MODE_11G];
6847 	}
6848 	/* Use the first valid TX antenna. */
6849 	txant = IWN_LSB(sc->txchainmask);
6850 	tx->rate |= htole32(IWN_RFLAG_ANT(txant));
6851 
6852 	/*
6853 	 * Only do active scanning if we're announcing a probe request
6854 	 * for a given SSID (or more, if we ever add it to the driver.)
6855 	 */
6856 	is_active = 0;
6857 
6858 	/*
6859 	 * If we're scanning for a specific SSID, add it to the command.
6860 	 *
6861 	 * XXX maybe look at adding support for scanning multiple SSIDs?
6862 	 */
6863 	essid = (struct iwn_scan_essid *)(tx + 1);
6864 	if (ss != NULL) {
6865 		if (ss->ss_ssid[0].len != 0) {
6866 			essid[0].id = IEEE80211_ELEMID_SSID;
6867 			essid[0].len = ss->ss_ssid[0].len;
6868 			memcpy(essid[0].data, ss->ss_ssid[0].ssid, ss->ss_ssid[0].len);
6869 		}
6870 
6871 		DPRINTF(sc, IWN_DEBUG_SCAN, "%s: ssid_len=%d, ssid=%*s\n",
6872 		    __func__,
6873 		    ss->ss_ssid[0].len,
6874 		    ss->ss_ssid[0].len,
6875 		    ss->ss_ssid[0].ssid);
6876 
6877 		if (ss->ss_nssid > 0)
6878 			is_active = 1;
6879 	}
6880 
6881 	/*
6882 	 * Build a probe request frame.  Most of the following code is a
6883 	 * copy & paste of what is done in net80211.
6884 	 */
6885 	wh = (struct ieee80211_frame *)(essid + 20);
6886 	wh->i_fc[0] = IEEE80211_FC0_VERSION_0 | IEEE80211_FC0_TYPE_MGT |
6887 	    IEEE80211_FC0_SUBTYPE_PROBE_REQ;
6888 	wh->i_fc[1] = IEEE80211_FC1_DIR_NODS;
6889 	IEEE80211_ADDR_COPY(wh->i_addr1, ifp->if_broadcastaddr);
6890 	IEEE80211_ADDR_COPY(wh->i_addr2, IF_LLADDR(ifp));
6891 	IEEE80211_ADDR_COPY(wh->i_addr3, ifp->if_broadcastaddr);
6892 	*(uint16_t *)&wh->i_dur[0] = 0;	/* filled by HW */
6893 	*(uint16_t *)&wh->i_seq[0] = 0;	/* filled by HW */
6894 
6895 	frm = (uint8_t *)(wh + 1);
6896 	frm = ieee80211_add_ssid(frm, NULL, 0);
6897 	frm = ieee80211_add_rates(frm, rs);
6898 	if (rs->rs_nrates > IEEE80211_RATE_SIZE)
6899 		frm = ieee80211_add_xrates(frm, rs);
6900 	if (ic->ic_htcaps & IEEE80211_HTC_HT)
6901 		frm = ieee80211_add_htcap(frm, ni);
6902 
6903 	/* Set length of probe request. */
6904 	tx->len = htole16(frm - (uint8_t *)wh);
6905 
6906 	/*
6907 	 * If active scanning is requested but a certain channel is
6908 	 * marked passive, we can do active scanning if we detect
6909 	 * transmissions.
6910 	 *
6911 	 * There is an issue with some firmware versions that triggers
6912 	 * a sysassert on a "good CRC threshold" of zero (== disabled),
6913 	 * on a radar channel even though this means that we should NOT
6914 	 * send probes.
6915 	 *
6916 	 * The "good CRC threshold" is the number of frames that we
6917 	 * need to receive during our dwell time on a channel before
6918 	 * sending out probes -- setting this to a huge value will
6919 	 * mean we never reach it, but at the same time work around
6920 	 * the aforementioned issue. Thus use IWL_GOOD_CRC_TH_NEVER
6921 	 * here instead of IWL_GOOD_CRC_TH_DISABLED.
6922 	 *
6923 	 * This was fixed in later versions along with some other
6924 	 * scan changes, and the threshold behaves as a flag in those
6925 	 * versions.
6926 	 */
6927 
6928 	/*
6929 	 * If we're doing active scanning, set the crc_threshold
6930 	 * to a suitable value.  This is different to active veruss
6931 	 * passive scanning depending upon the channel flags; the
6932 	 * firmware will obey that particular check for us.
6933 	 */
6934 	if (sc->tlv_feature_flags & IWN_UCODE_TLV_FLAGS_NEWSCAN)
6935 		hdr->crc_threshold = is_active ?
6936 		    IWN_GOOD_CRC_TH_DEFAULT : IWN_GOOD_CRC_TH_DISABLED;
6937 	else
6938 		hdr->crc_threshold = is_active ?
6939 		    IWN_GOOD_CRC_TH_DEFAULT : IWN_GOOD_CRC_TH_NEVER;
6940 
6941 	chan = (struct iwn_scan_chan *)frm;
6942 	chan->chan = htole16(ieee80211_chan2ieee(ic, c));
6943 	chan->flags = 0;
6944 	if (ss->ss_nssid > 0)
6945 		chan->flags |= htole32(IWN_CHAN_NPBREQS(1));
6946 	chan->dsp_gain = 0x6e;
6947 
6948 	/*
6949 	 * Set the passive/active flag depending upon the channel mode.
6950 	 * XXX TODO: take the is_active flag into account as well?
6951 	 */
6952 	if (c->ic_flags & IEEE80211_CHAN_PASSIVE)
6953 		chan->flags |= htole32(IWN_CHAN_PASSIVE);
6954 	else
6955 		chan->flags |= htole32(IWN_CHAN_ACTIVE);
6956 
6957 	/*
6958 	 * Calculate the active/passive dwell times.
6959 	 */
6960 
6961 	dwell_active = iwn_get_active_dwell_time(sc, c, ss->ss_nssid);
6962 	dwell_passive = iwn_get_passive_dwell_time(sc, c);
6963 
6964 	/* Make sure they're valid */
6965 	if (dwell_passive <= dwell_active)
6966 		dwell_passive = dwell_active + 1;
6967 
6968 	chan->active = htole16(dwell_active);
6969 	chan->passive = htole16(dwell_passive);
6970 
6971 	if (IEEE80211_IS_CHAN_5GHZ(c))
6972 		chan->rf_gain = 0x3b;
6973 	else
6974 		chan->rf_gain = 0x28;
6975 
6976 	DPRINTF(sc, IWN_DEBUG_STATE,
6977 	    "%s: chan %u flags 0x%x rf_gain 0x%x "
6978 	    "dsp_gain 0x%x active %d passive %d scan_svc_time %d crc 0x%x "
6979 	    "isactive=%d numssid=%d\n", __func__,
6980 	    chan->chan, chan->flags, chan->rf_gain, chan->dsp_gain,
6981 	    dwell_active, dwell_passive, scan_service_time,
6982 	    hdr->crc_threshold, is_active, ss->ss_nssid);
6983 
6984 	hdr->nchan++;
6985 	chan++;
6986 	buflen = (uint8_t *)chan - buf;
6987 	hdr->len = htole16(buflen);
6988 
6989 	if (sc->sc_is_scanning) {
6990 		device_printf(sc->sc_dev,
6991 		    "%s: called with is_scanning set!\n",
6992 		    __func__);
6993 	}
6994 	sc->sc_is_scanning = 1;
6995 
6996 	DPRINTF(sc, IWN_DEBUG_STATE, "sending scan command nchan=%d\n",
6997 	    hdr->nchan);
6998 	error = iwn_cmd(sc, IWN_CMD_SCAN, buf, buflen, 1);
6999 	free(buf, M_DEVBUF);
7000 
7001 	DPRINTF(sc, IWN_DEBUG_TRACE, "->%s: end\n",__func__);
7002 
7003 	return error;
7004 }
7005 
7006 static int
7007 iwn_auth(struct iwn_softc *sc, struct ieee80211vap *vap)
7008 {
7009 	struct iwn_ops *ops = &sc->ops;
7010 	struct ifnet *ifp = sc->sc_ifp;
7011 	struct ieee80211com *ic = ifp->if_l2com;
7012 	struct ieee80211_node *ni = vap->iv_bss;
7013 	int error;
7014 
7015 	DPRINTF(sc, IWN_DEBUG_TRACE, "->%s begin\n", __func__);
7016 
7017 	sc->rxon = &sc->rx_on[IWN_RXON_BSS_CTX];
7018 	/* Update adapter configuration. */
7019 	IEEE80211_ADDR_COPY(sc->rxon->bssid, ni->ni_bssid);
7020 	sc->rxon->chan = ieee80211_chan2ieee(ic, ni->ni_chan);
7021 	sc->rxon->flags = htole32(IWN_RXON_TSF | IWN_RXON_CTS_TO_SELF);
7022 	if (IEEE80211_IS_CHAN_2GHZ(ni->ni_chan))
7023 		sc->rxon->flags |= htole32(IWN_RXON_AUTO | IWN_RXON_24GHZ);
7024 	if (ic->ic_flags & IEEE80211_F_SHSLOT)
7025 		sc->rxon->flags |= htole32(IWN_RXON_SHSLOT);
7026 	if (ic->ic_flags & IEEE80211_F_SHPREAMBLE)
7027 		sc->rxon->flags |= htole32(IWN_RXON_SHPREAMBLE);
7028 	if (IEEE80211_IS_CHAN_A(ni->ni_chan)) {
7029 		sc->rxon->cck_mask  = 0;
7030 		sc->rxon->ofdm_mask = 0x15;
7031 	} else if (IEEE80211_IS_CHAN_B(ni->ni_chan)) {
7032 		sc->rxon->cck_mask  = 0x03;
7033 		sc->rxon->ofdm_mask = 0;
7034 	} else {
7035 		/* Assume 802.11b/g. */
7036 		sc->rxon->cck_mask  = 0x03;
7037 		sc->rxon->ofdm_mask = 0x15;
7038 	}
7039 	DPRINTF(sc, IWN_DEBUG_STATE, "rxon chan %d flags %x cck %x ofdm %x\n",
7040 	    sc->rxon->chan, sc->rxon->flags, sc->rxon->cck_mask,
7041 	    sc->rxon->ofdm_mask);
7042 	if (sc->sc_is_scanning)
7043 		device_printf(sc->sc_dev,
7044 		    "%s: is_scanning set, before RXON\n",
7045 		    __func__);
7046 	error = iwn_cmd(sc, IWN_CMD_RXON, sc->rxon, sc->rxonsz, 1);
7047 	if (error != 0) {
7048 		device_printf(sc->sc_dev, "%s: RXON command failed, error %d\n",
7049 		    __func__, error);
7050 		return error;
7051 	}
7052 
7053 	/* Configuration has changed, set TX power accordingly. */
7054 	if ((error = ops->set_txpower(sc, ni->ni_chan, 1)) != 0) {
7055 		device_printf(sc->sc_dev,
7056 		    "%s: could not set TX power, error %d\n", __func__, error);
7057 		return error;
7058 	}
7059 	/*
7060 	 * Reconfiguring RXON clears the firmware nodes table so we must
7061 	 * add the broadcast node again.
7062 	 */
7063 	if ((error = iwn_add_broadcast_node(sc, 1)) != 0) {
7064 		device_printf(sc->sc_dev,
7065 		    "%s: could not add broadcast node, error %d\n", __func__,
7066 		    error);
7067 		return error;
7068 	}
7069 
7070 	DPRINTF(sc, IWN_DEBUG_TRACE, "->%s: end\n",__func__);
7071 
7072 	return 0;
7073 }
7074 
7075 static int
7076 iwn_run(struct iwn_softc *sc, struct ieee80211vap *vap)
7077 {
7078 	struct iwn_ops *ops = &sc->ops;
7079 	struct ifnet *ifp = sc->sc_ifp;
7080 	struct ieee80211com *ic = ifp->if_l2com;
7081 	struct ieee80211_node *ni = vap->iv_bss;
7082 	struct iwn_node_info node;
7083 	uint32_t htflags = 0;
7084 	int error;
7085 
7086 	DPRINTF(sc, IWN_DEBUG_TRACE, "->%s begin\n", __func__);
7087 
7088 	sc->rxon = &sc->rx_on[IWN_RXON_BSS_CTX];
7089 	if (ic->ic_opmode == IEEE80211_M_MONITOR) {
7090 		/* Link LED blinks while monitoring. */
7091 		iwn_set_led(sc, IWN_LED_LINK, 5, 5);
7092 		return 0;
7093 	}
7094 	if ((error = iwn_set_timing(sc, ni)) != 0) {
7095 		device_printf(sc->sc_dev,
7096 		    "%s: could not set timing, error %d\n", __func__, error);
7097 		return error;
7098 	}
7099 
7100 	/* Update adapter configuration. */
7101 	IEEE80211_ADDR_COPY(sc->rxon->bssid, ni->ni_bssid);
7102 	sc->rxon->associd = htole16(IEEE80211_AID(ni->ni_associd));
7103 	sc->rxon->chan = ieee80211_chan2ieee(ic, ni->ni_chan);
7104 	sc->rxon->flags = htole32(IWN_RXON_TSF | IWN_RXON_CTS_TO_SELF);
7105 	if (IEEE80211_IS_CHAN_2GHZ(ni->ni_chan))
7106 		sc->rxon->flags |= htole32(IWN_RXON_AUTO | IWN_RXON_24GHZ);
7107 	if (ic->ic_flags & IEEE80211_F_SHSLOT)
7108 		sc->rxon->flags |= htole32(IWN_RXON_SHSLOT);
7109 	if (ic->ic_flags & IEEE80211_F_SHPREAMBLE)
7110 		sc->rxon->flags |= htole32(IWN_RXON_SHPREAMBLE);
7111 	if (IEEE80211_IS_CHAN_A(ni->ni_chan)) {
7112 		sc->rxon->cck_mask  = 0;
7113 		sc->rxon->ofdm_mask = 0x15;
7114 	} else if (IEEE80211_IS_CHAN_B(ni->ni_chan)) {
7115 		sc->rxon->cck_mask  = 0x03;
7116 		sc->rxon->ofdm_mask = 0;
7117 	} else {
7118 		/* Assume 802.11b/g. */
7119 		sc->rxon->cck_mask  = 0x0f;
7120 		sc->rxon->ofdm_mask = 0x15;
7121 	}
7122 	if (IEEE80211_IS_CHAN_HT(ni->ni_chan)) {
7123 		htflags |= IWN_RXON_HT_PROTMODE(ic->ic_curhtprotmode);
7124 		if (IEEE80211_IS_CHAN_HT40(ni->ni_chan)) {
7125 			switch (ic->ic_curhtprotmode) {
7126 			case IEEE80211_HTINFO_OPMODE_HT20PR:
7127 				htflags |= IWN_RXON_HT_MODEPURE40;
7128 				break;
7129 			default:
7130 				htflags |= IWN_RXON_HT_MODEMIXED;
7131 				break;
7132 			}
7133 		}
7134 		if (IEEE80211_IS_CHAN_HT40D(ni->ni_chan))
7135 			htflags |= IWN_RXON_HT_HT40MINUS;
7136 	}
7137 	sc->rxon->flags |= htole32(htflags);
7138 	sc->rxon->filter |= htole32(IWN_FILTER_BSS);
7139 	DPRINTF(sc, IWN_DEBUG_STATE, "rxon chan %d flags %x\n",
7140 	    sc->rxon->chan, sc->rxon->flags);
7141 	if (sc->sc_is_scanning)
7142 		device_printf(sc->sc_dev,
7143 		    "%s: is_scanning set, before RXON\n",
7144 		    __func__);
7145 	error = iwn_cmd(sc, IWN_CMD_RXON, sc->rxon, sc->rxonsz, 1);
7146 	if (error != 0) {
7147 		device_printf(sc->sc_dev,
7148 		    "%s: could not update configuration, error %d\n", __func__,
7149 		    error);
7150 		return error;
7151 	}
7152 
7153 	/* Configuration has changed, set TX power accordingly. */
7154 	if ((error = ops->set_txpower(sc, ni->ni_chan, 1)) != 0) {
7155 		device_printf(sc->sc_dev,
7156 		    "%s: could not set TX power, error %d\n", __func__, error);
7157 		return error;
7158 	}
7159 
7160 	/* Fake a join to initialize the TX rate. */
7161 	((struct iwn_node *)ni)->id = IWN_ID_BSS;
7162 	iwn_newassoc(ni, 1);
7163 
7164 	/* Add BSS node. */
7165 	memset(&node, 0, sizeof node);
7166 	IEEE80211_ADDR_COPY(node.macaddr, ni->ni_macaddr);
7167 	node.id = IWN_ID_BSS;
7168 	if (IEEE80211_IS_CHAN_HT(ni->ni_chan)) {
7169 		switch (ni->ni_htcap & IEEE80211_HTCAP_SMPS) {
7170 		case IEEE80211_HTCAP_SMPS_ENA:
7171 			node.htflags |= htole32(IWN_SMPS_MIMO_DIS);
7172 			break;
7173 		case IEEE80211_HTCAP_SMPS_DYNAMIC:
7174 			node.htflags |= htole32(IWN_SMPS_MIMO_PROT);
7175 			break;
7176 		}
7177 		node.htflags |= htole32(IWN_AMDPU_SIZE_FACTOR(3) |
7178 		    IWN_AMDPU_DENSITY(5));	/* 4us */
7179 		if (IEEE80211_IS_CHAN_HT40(ni->ni_chan))
7180 			node.htflags |= htole32(IWN_NODE_HT40);
7181 	}
7182 	DPRINTF(sc, IWN_DEBUG_STATE, "%s: adding BSS node\n", __func__);
7183 	error = ops->add_node(sc, &node, 1);
7184 	if (error != 0) {
7185 		device_printf(sc->sc_dev,
7186 		    "%s: could not add BSS node, error %d\n", __func__, error);
7187 		return error;
7188 	}
7189 	DPRINTF(sc, IWN_DEBUG_STATE, "%s: setting link quality for node %d\n",
7190 	    __func__, node.id);
7191 	if ((error = iwn_set_link_quality(sc, ni)) != 0) {
7192 		device_printf(sc->sc_dev,
7193 		    "%s: could not setup link quality for node %d, error %d\n",
7194 		    __func__, node.id, error);
7195 		return error;
7196 	}
7197 
7198 	if ((error = iwn_init_sensitivity(sc)) != 0) {
7199 		device_printf(sc->sc_dev,
7200 		    "%s: could not set sensitivity, error %d\n", __func__,
7201 		    error);
7202 		return error;
7203 	}
7204 	/* Start periodic calibration timer. */
7205 	sc->calib.state = IWN_CALIB_STATE_ASSOC;
7206 	sc->calib_cnt = 0;
7207 	callout_reset(&sc->calib_to, msecs_to_ticks(500), iwn_calib_timeout,
7208 	    sc);
7209 
7210 	/* Link LED always on while associated. */
7211 	iwn_set_led(sc, IWN_LED_LINK, 0, 1);
7212 
7213 	DPRINTF(sc, IWN_DEBUG_TRACE, "->%s: end\n",__func__);
7214 
7215 	return 0;
7216 }
7217 
7218 /*
7219  * This function is called by upper layer when an ADDBA request is received
7220  * from another STA and before the ADDBA response is sent.
7221  */
7222 static int
7223 iwn_ampdu_rx_start(struct ieee80211_node *ni, struct ieee80211_rx_ampdu *rap,
7224     int baparamset, int batimeout, int baseqctl)
7225 {
7226 #define MS(_v, _f)	(((_v) & _f) >> _f##_S)
7227 	struct iwn_softc *sc = ni->ni_ic->ic_softc;
7228 	struct iwn_ops *ops = &sc->ops;
7229 	struct iwn_node *wn = (void *)ni;
7230 	struct iwn_node_info node;
7231 	uint16_t ssn;
7232 	uint8_t tid;
7233 	int error;
7234 
7235 	DPRINTF(sc, IWN_DEBUG_TRACE, "->Doing %s\n", __func__);
7236 
7237 	tid = MS(le16toh(baparamset), IEEE80211_BAPS_TID);
7238 	ssn = MS(le16toh(baseqctl), IEEE80211_BASEQ_START);
7239 
7240 	memset(&node, 0, sizeof node);
7241 	node.id = wn->id;
7242 	node.control = IWN_NODE_UPDATE;
7243 	node.flags = IWN_FLAG_SET_ADDBA;
7244 	node.addba_tid = tid;
7245 	node.addba_ssn = htole16(ssn);
7246 	DPRINTF(sc, IWN_DEBUG_RECV, "ADDBA RA=%d TID=%d SSN=%d\n",
7247 	    wn->id, tid, ssn);
7248 	error = ops->add_node(sc, &node, 1);
7249 	if (error != 0)
7250 		return error;
7251 	return sc->sc_ampdu_rx_start(ni, rap, baparamset, batimeout, baseqctl);
7252 #undef MS
7253 }
7254 
7255 /*
7256  * This function is called by upper layer on teardown of an HT-immediate
7257  * Block Ack agreement (eg. uppon receipt of a DELBA frame).
7258  */
7259 static void
7260 iwn_ampdu_rx_stop(struct ieee80211_node *ni, struct ieee80211_rx_ampdu *rap)
7261 {
7262 	struct ieee80211com *ic = ni->ni_ic;
7263 	struct iwn_softc *sc = ic->ic_softc;
7264 	struct iwn_ops *ops = &sc->ops;
7265 	struct iwn_node *wn = (void *)ni;
7266 	struct iwn_node_info node;
7267 	uint8_t tid;
7268 
7269 	DPRINTF(sc, IWN_DEBUG_TRACE, "->Doing %s\n", __func__);
7270 
7271 	/* XXX: tid as an argument */
7272 	for (tid = 0; tid < WME_NUM_TID; tid++) {
7273 		if (&ni->ni_rx_ampdu[tid] == rap)
7274 			break;
7275 	}
7276 
7277 	memset(&node, 0, sizeof node);
7278 	node.id = wn->id;
7279 	node.control = IWN_NODE_UPDATE;
7280 	node.flags = IWN_FLAG_SET_DELBA;
7281 	node.delba_tid = tid;
7282 	DPRINTF(sc, IWN_DEBUG_RECV, "DELBA RA=%d TID=%d\n", wn->id, tid);
7283 	(void)ops->add_node(sc, &node, 1);
7284 	sc->sc_ampdu_rx_stop(ni, rap);
7285 }
7286 
7287 static int
7288 iwn_addba_request(struct ieee80211_node *ni, struct ieee80211_tx_ampdu *tap,
7289     int dialogtoken, int baparamset, int batimeout)
7290 {
7291 	struct iwn_softc *sc = ni->ni_ic->ic_softc;
7292 	int qid;
7293 
7294 	DPRINTF(sc, IWN_DEBUG_TRACE, "->Doing %s\n", __func__);
7295 
7296 	for (qid = sc->firstaggqueue; qid < sc->ntxqs; qid++) {
7297 		if (sc->qid2tap[qid] == NULL)
7298 			break;
7299 	}
7300 	if (qid == sc->ntxqs) {
7301 		DPRINTF(sc, IWN_DEBUG_XMIT, "%s: not free aggregation queue\n",
7302 		    __func__);
7303 		return 0;
7304 	}
7305 	tap->txa_private = malloc(sizeof(int), M_DEVBUF, M_NOWAIT);
7306 	if (tap->txa_private == NULL) {
7307 		device_printf(sc->sc_dev,
7308 		    "%s: failed to alloc TX aggregation structure\n", __func__);
7309 		return 0;
7310 	}
7311 	sc->qid2tap[qid] = tap;
7312 	*(int *)tap->txa_private = qid;
7313 	return sc->sc_addba_request(ni, tap, dialogtoken, baparamset,
7314 	    batimeout);
7315 }
7316 
7317 static int
7318 iwn_addba_response(struct ieee80211_node *ni, struct ieee80211_tx_ampdu *tap,
7319     int code, int baparamset, int batimeout)
7320 {
7321 	struct iwn_softc *sc = ni->ni_ic->ic_softc;
7322 	int qid = *(int *)tap->txa_private;
7323 	uint8_t tid = tap->txa_tid;
7324 	int ret;
7325 
7326 	DPRINTF(sc, IWN_DEBUG_TRACE, "->Doing %s\n", __func__);
7327 
7328 	if (code == IEEE80211_STATUS_SUCCESS) {
7329 		ni->ni_txseqs[tid] = tap->txa_start & 0xfff;
7330 		ret = iwn_ampdu_tx_start(ni->ni_ic, ni, tid);
7331 		if (ret != 1)
7332 			return ret;
7333 	} else {
7334 		sc->qid2tap[qid] = NULL;
7335 		free(tap->txa_private, M_DEVBUF);
7336 		tap->txa_private = NULL;
7337 	}
7338 	return sc->sc_addba_response(ni, tap, code, baparamset, batimeout);
7339 }
7340 
7341 /*
7342  * This function is called by upper layer when an ADDBA response is received
7343  * from another STA.
7344  */
7345 static int
7346 iwn_ampdu_tx_start(struct ieee80211com *ic, struct ieee80211_node *ni,
7347     uint8_t tid)
7348 {
7349 	struct ieee80211_tx_ampdu *tap = &ni->ni_tx_ampdu[tid];
7350 	struct iwn_softc *sc = ni->ni_ic->ic_softc;
7351 	struct iwn_ops *ops = &sc->ops;
7352 	struct iwn_node *wn = (void *)ni;
7353 	struct iwn_node_info node;
7354 	int error, qid;
7355 
7356 	DPRINTF(sc, IWN_DEBUG_TRACE, "->Doing %s\n", __func__);
7357 
7358 	/* Enable TX for the specified RA/TID. */
7359 	wn->disable_tid &= ~(1 << tid);
7360 	memset(&node, 0, sizeof node);
7361 	node.id = wn->id;
7362 	node.control = IWN_NODE_UPDATE;
7363 	node.flags = IWN_FLAG_SET_DISABLE_TID;
7364 	node.disable_tid = htole16(wn->disable_tid);
7365 	error = ops->add_node(sc, &node, 1);
7366 	if (error != 0)
7367 		return 0;
7368 
7369 	if ((error = iwn_nic_lock(sc)) != 0)
7370 		return 0;
7371 	qid = *(int *)tap->txa_private;
7372 	DPRINTF(sc, IWN_DEBUG_XMIT, "%s: ra=%d tid=%d ssn=%d qid=%d\n",
7373 	    __func__, wn->id, tid, tap->txa_start, qid);
7374 	ops->ampdu_tx_start(sc, ni, qid, tid, tap->txa_start & 0xfff);
7375 	iwn_nic_unlock(sc);
7376 
7377 	iwn_set_link_quality(sc, ni);
7378 	return 1;
7379 }
7380 
7381 static void
7382 iwn_ampdu_tx_stop(struct ieee80211_node *ni, struct ieee80211_tx_ampdu *tap)
7383 {
7384 	struct iwn_softc *sc = ni->ni_ic->ic_softc;
7385 	struct iwn_ops *ops = &sc->ops;
7386 	uint8_t tid = tap->txa_tid;
7387 	int qid;
7388 
7389 	DPRINTF(sc, IWN_DEBUG_TRACE, "->Doing %s\n", __func__);
7390 
7391 	sc->sc_addba_stop(ni, tap);
7392 
7393 	if (tap->txa_private == NULL)
7394 		return;
7395 
7396 	qid = *(int *)tap->txa_private;
7397 	if (sc->txq[qid].queued != 0)
7398 		return;
7399 	if (iwn_nic_lock(sc) != 0)
7400 		return;
7401 	ops->ampdu_tx_stop(sc, qid, tid, tap->txa_start & 0xfff);
7402 	iwn_nic_unlock(sc);
7403 	sc->qid2tap[qid] = NULL;
7404 	free(tap->txa_private, M_DEVBUF);
7405 	tap->txa_private = NULL;
7406 }
7407 
7408 static void
7409 iwn4965_ampdu_tx_start(struct iwn_softc *sc, struct ieee80211_node *ni,
7410     int qid, uint8_t tid, uint16_t ssn)
7411 {
7412 	struct iwn_node *wn = (void *)ni;
7413 
7414 	DPRINTF(sc, IWN_DEBUG_TRACE, "->Doing %s\n", __func__);
7415 
7416 	/* Stop TX scheduler while we're changing its configuration. */
7417 	iwn_prph_write(sc, IWN4965_SCHED_QUEUE_STATUS(qid),
7418 	    IWN4965_TXQ_STATUS_CHGACT);
7419 
7420 	/* Assign RA/TID translation to the queue. */
7421 	iwn_mem_write_2(sc, sc->sched_base + IWN4965_SCHED_TRANS_TBL(qid),
7422 	    wn->id << 4 | tid);
7423 
7424 	/* Enable chain-building mode for the queue. */
7425 	iwn_prph_setbits(sc, IWN4965_SCHED_QCHAIN_SEL, 1 << qid);
7426 
7427 	/* Set starting sequence number from the ADDBA request. */
7428 	sc->txq[qid].cur = sc->txq[qid].read = (ssn & 0xff);
7429 	IWN_WRITE(sc, IWN_HBUS_TARG_WRPTR, qid << 8 | (ssn & 0xff));
7430 	iwn_prph_write(sc, IWN4965_SCHED_QUEUE_RDPTR(qid), ssn);
7431 
7432 	/* Set scheduler window size. */
7433 	iwn_mem_write(sc, sc->sched_base + IWN4965_SCHED_QUEUE_OFFSET(qid),
7434 	    IWN_SCHED_WINSZ);
7435 	/* Set scheduler frame limit. */
7436 	iwn_mem_write(sc, sc->sched_base + IWN4965_SCHED_QUEUE_OFFSET(qid) + 4,
7437 	    IWN_SCHED_LIMIT << 16);
7438 
7439 	/* Enable interrupts for the queue. */
7440 	iwn_prph_setbits(sc, IWN4965_SCHED_INTR_MASK, 1 << qid);
7441 
7442 	/* Mark the queue as active. */
7443 	iwn_prph_write(sc, IWN4965_SCHED_QUEUE_STATUS(qid),
7444 	    IWN4965_TXQ_STATUS_ACTIVE | IWN4965_TXQ_STATUS_AGGR_ENA |
7445 	    iwn_tid2fifo[tid] << 1);
7446 }
7447 
7448 static void
7449 iwn4965_ampdu_tx_stop(struct iwn_softc *sc, int qid, uint8_t tid, uint16_t ssn)
7450 {
7451 	DPRINTF(sc, IWN_DEBUG_TRACE, "->Doing %s\n", __func__);
7452 
7453 	/* Stop TX scheduler while we're changing its configuration. */
7454 	iwn_prph_write(sc, IWN4965_SCHED_QUEUE_STATUS(qid),
7455 	    IWN4965_TXQ_STATUS_CHGACT);
7456 
7457 	/* Set starting sequence number from the ADDBA request. */
7458 	IWN_WRITE(sc, IWN_HBUS_TARG_WRPTR, qid << 8 | (ssn & 0xff));
7459 	iwn_prph_write(sc, IWN4965_SCHED_QUEUE_RDPTR(qid), ssn);
7460 
7461 	/* Disable interrupts for the queue. */
7462 	iwn_prph_clrbits(sc, IWN4965_SCHED_INTR_MASK, 1 << qid);
7463 
7464 	/* Mark the queue as inactive. */
7465 	iwn_prph_write(sc, IWN4965_SCHED_QUEUE_STATUS(qid),
7466 	    IWN4965_TXQ_STATUS_INACTIVE | iwn_tid2fifo[tid] << 1);
7467 }
7468 
7469 static void
7470 iwn5000_ampdu_tx_start(struct iwn_softc *sc, struct ieee80211_node *ni,
7471     int qid, uint8_t tid, uint16_t ssn)
7472 {
7473 	DPRINTF(sc, IWN_DEBUG_TRACE, "->Doing %s\n", __func__);
7474 
7475 	struct iwn_node *wn = (void *)ni;
7476 
7477 	/* Stop TX scheduler while we're changing its configuration. */
7478 	iwn_prph_write(sc, IWN5000_SCHED_QUEUE_STATUS(qid),
7479 	    IWN5000_TXQ_STATUS_CHGACT);
7480 
7481 	/* Assign RA/TID translation to the queue. */
7482 	iwn_mem_write_2(sc, sc->sched_base + IWN5000_SCHED_TRANS_TBL(qid),
7483 	    wn->id << 4 | tid);
7484 
7485 	/* Enable chain-building mode for the queue. */
7486 	iwn_prph_setbits(sc, IWN5000_SCHED_QCHAIN_SEL, 1 << qid);
7487 
7488 	/* Enable aggregation for the queue. */
7489 	iwn_prph_setbits(sc, IWN5000_SCHED_AGGR_SEL, 1 << qid);
7490 
7491 	/* Set starting sequence number from the ADDBA request. */
7492 	sc->txq[qid].cur = sc->txq[qid].read = (ssn & 0xff);
7493 	IWN_WRITE(sc, IWN_HBUS_TARG_WRPTR, qid << 8 | (ssn & 0xff));
7494 	iwn_prph_write(sc, IWN5000_SCHED_QUEUE_RDPTR(qid), ssn);
7495 
7496 	/* Set scheduler window size and frame limit. */
7497 	iwn_mem_write(sc, sc->sched_base + IWN5000_SCHED_QUEUE_OFFSET(qid) + 4,
7498 	    IWN_SCHED_LIMIT << 16 | IWN_SCHED_WINSZ);
7499 
7500 	/* Enable interrupts for the queue. */
7501 	iwn_prph_setbits(sc, IWN5000_SCHED_INTR_MASK, 1 << qid);
7502 
7503 	/* Mark the queue as active. */
7504 	iwn_prph_write(sc, IWN5000_SCHED_QUEUE_STATUS(qid),
7505 	    IWN5000_TXQ_STATUS_ACTIVE | iwn_tid2fifo[tid]);
7506 }
7507 
7508 static void
7509 iwn5000_ampdu_tx_stop(struct iwn_softc *sc, int qid, uint8_t tid, uint16_t ssn)
7510 {
7511 	DPRINTF(sc, IWN_DEBUG_TRACE, "->Doing %s\n", __func__);
7512 
7513 	/* Stop TX scheduler while we're changing its configuration. */
7514 	iwn_prph_write(sc, IWN5000_SCHED_QUEUE_STATUS(qid),
7515 	    IWN5000_TXQ_STATUS_CHGACT);
7516 
7517 	/* Disable aggregation for the queue. */
7518 	iwn_prph_clrbits(sc, IWN5000_SCHED_AGGR_SEL, 1 << qid);
7519 
7520 	/* Set starting sequence number from the ADDBA request. */
7521 	IWN_WRITE(sc, IWN_HBUS_TARG_WRPTR, qid << 8 | (ssn & 0xff));
7522 	iwn_prph_write(sc, IWN5000_SCHED_QUEUE_RDPTR(qid), ssn);
7523 
7524 	/* Disable interrupts for the queue. */
7525 	iwn_prph_clrbits(sc, IWN5000_SCHED_INTR_MASK, 1 << qid);
7526 
7527 	/* Mark the queue as inactive. */
7528 	iwn_prph_write(sc, IWN5000_SCHED_QUEUE_STATUS(qid),
7529 	    IWN5000_TXQ_STATUS_INACTIVE | iwn_tid2fifo[tid]);
7530 }
7531 
7532 /*
7533  * Query calibration tables from the initialization firmware.  We do this
7534  * only once at first boot.  Called from a process context.
7535  */
7536 static int
7537 iwn5000_query_calibration(struct iwn_softc *sc)
7538 {
7539 	struct iwn5000_calib_config cmd;
7540 	int error;
7541 
7542 	memset(&cmd, 0, sizeof cmd);
7543 	cmd.ucode.once.enable = htole32(0xffffffff);
7544 	cmd.ucode.once.start  = htole32(0xffffffff);
7545 	cmd.ucode.once.send   = htole32(0xffffffff);
7546 	cmd.ucode.flags       = htole32(0xffffffff);
7547 	DPRINTF(sc, IWN_DEBUG_CALIBRATE, "%s: sending calibration query\n",
7548 	    __func__);
7549 	error = iwn_cmd(sc, IWN5000_CMD_CALIB_CONFIG, &cmd, sizeof cmd, 0);
7550 	if (error != 0)
7551 		return error;
7552 
7553 	/* Wait at most two seconds for calibration to complete. */
7554 	if (!(sc->sc_flags & IWN_FLAG_CALIB_DONE))
7555 		error = msleep(sc, &sc->sc_mtx, PCATCH, "iwncal", 2 * hz);
7556 	return error;
7557 }
7558 
7559 /*
7560  * Send calibration results to the runtime firmware.  These results were
7561  * obtained on first boot from the initialization firmware.
7562  */
7563 static int
7564 iwn5000_send_calibration(struct iwn_softc *sc)
7565 {
7566 	int idx, error;
7567 
7568 	for (idx = 0; idx < IWN5000_PHY_CALIB_MAX_RESULT; idx++) {
7569 		if (!(sc->base_params->calib_need & (1<<idx))) {
7570 			DPRINTF(sc, IWN_DEBUG_CALIBRATE,
7571 			    "No need of calib %d\n",
7572 			    idx);
7573 			continue; /* no need for this calib */
7574 		}
7575 		if (sc->calibcmd[idx].buf == NULL) {
7576 			DPRINTF(sc, IWN_DEBUG_CALIBRATE,
7577 			    "Need calib idx : %d but no available data\n",
7578 			    idx);
7579 			continue;
7580 		}
7581 
7582 		DPRINTF(sc, IWN_DEBUG_CALIBRATE,
7583 		    "send calibration result idx=%d len=%d\n", idx,
7584 		    sc->calibcmd[idx].len);
7585 		error = iwn_cmd(sc, IWN_CMD_PHY_CALIB, sc->calibcmd[idx].buf,
7586 		    sc->calibcmd[idx].len, 0);
7587 		if (error != 0) {
7588 			device_printf(sc->sc_dev,
7589 			    "%s: could not send calibration result, error %d\n",
7590 			    __func__, error);
7591 			return error;
7592 		}
7593 	}
7594 	return 0;
7595 }
7596 
7597 static int
7598 iwn5000_send_wimax_coex(struct iwn_softc *sc)
7599 {
7600 	struct iwn5000_wimax_coex wimax;
7601 
7602 #if 0
7603 	if (sc->hw_type == IWN_HW_REV_TYPE_6050) {
7604 		/* Enable WiMAX coexistence for combo adapters. */
7605 		wimax.flags =
7606 		    IWN_WIMAX_COEX_ASSOC_WA_UNMASK |
7607 		    IWN_WIMAX_COEX_UNASSOC_WA_UNMASK |
7608 		    IWN_WIMAX_COEX_STA_TABLE_VALID |
7609 		    IWN_WIMAX_COEX_ENABLE;
7610 		memcpy(wimax.events, iwn6050_wimax_events,
7611 		    sizeof iwn6050_wimax_events);
7612 	} else
7613 #endif
7614 	{
7615 		/* Disable WiMAX coexistence. */
7616 		wimax.flags = 0;
7617 		memset(wimax.events, 0, sizeof wimax.events);
7618 	}
7619 	DPRINTF(sc, IWN_DEBUG_RESET, "%s: Configuring WiMAX coexistence\n",
7620 	    __func__);
7621 	return iwn_cmd(sc, IWN5000_CMD_WIMAX_COEX, &wimax, sizeof wimax, 0);
7622 }
7623 
7624 static int
7625 iwn5000_crystal_calib(struct iwn_softc *sc)
7626 {
7627 	struct iwn5000_phy_calib_crystal cmd;
7628 
7629 	memset(&cmd, 0, sizeof cmd);
7630 	cmd.code = IWN5000_PHY_CALIB_CRYSTAL;
7631 	cmd.ngroups = 1;
7632 	cmd.isvalid = 1;
7633 	cmd.cap_pin[0] = le32toh(sc->eeprom_crystal) & 0xff;
7634 	cmd.cap_pin[1] = (le32toh(sc->eeprom_crystal) >> 16) & 0xff;
7635 	DPRINTF(sc, IWN_DEBUG_CALIBRATE, "sending crystal calibration %d, %d\n",
7636 	    cmd.cap_pin[0], cmd.cap_pin[1]);
7637 	return iwn_cmd(sc, IWN_CMD_PHY_CALIB, &cmd, sizeof cmd, 0);
7638 }
7639 
7640 static int
7641 iwn5000_temp_offset_calib(struct iwn_softc *sc)
7642 {
7643 	struct iwn5000_phy_calib_temp_offset cmd;
7644 
7645 	memset(&cmd, 0, sizeof cmd);
7646 	cmd.code = IWN5000_PHY_CALIB_TEMP_OFFSET;
7647 	cmd.ngroups = 1;
7648 	cmd.isvalid = 1;
7649 	if (sc->eeprom_temp != 0)
7650 		cmd.offset = htole16(sc->eeprom_temp);
7651 	else
7652 		cmd.offset = htole16(IWN_DEFAULT_TEMP_OFFSET);
7653 	DPRINTF(sc, IWN_DEBUG_CALIBRATE, "setting radio sensor offset to %d\n",
7654 	    le16toh(cmd.offset));
7655 	return iwn_cmd(sc, IWN_CMD_PHY_CALIB, &cmd, sizeof cmd, 0);
7656 }
7657 
7658 static int
7659 iwn5000_temp_offset_calibv2(struct iwn_softc *sc)
7660 {
7661 	struct iwn5000_phy_calib_temp_offsetv2 cmd;
7662 
7663 	memset(&cmd, 0, sizeof cmd);
7664 	cmd.code = IWN5000_PHY_CALIB_TEMP_OFFSET;
7665 	cmd.ngroups = 1;
7666 	cmd.isvalid = 1;
7667 	if (sc->eeprom_temp != 0) {
7668 		cmd.offset_low = htole16(sc->eeprom_temp);
7669 		cmd.offset_high = htole16(sc->eeprom_temp_high);
7670 	} else {
7671 		cmd.offset_low = htole16(IWN_DEFAULT_TEMP_OFFSET);
7672 		cmd.offset_high = htole16(IWN_DEFAULT_TEMP_OFFSET);
7673 	}
7674 	cmd.burnt_voltage_ref = htole16(sc->eeprom_voltage);
7675 
7676 	DPRINTF(sc, IWN_DEBUG_CALIBRATE,
7677 	    "setting radio sensor low offset to %d, high offset to %d, voltage to %d\n",
7678 	    le16toh(cmd.offset_low),
7679 	    le16toh(cmd.offset_high),
7680 	    le16toh(cmd.burnt_voltage_ref));
7681 
7682 	return iwn_cmd(sc, IWN_CMD_PHY_CALIB, &cmd, sizeof cmd, 0);
7683 }
7684 
7685 /*
7686  * This function is called after the runtime firmware notifies us of its
7687  * readiness (called in a process context).
7688  */
7689 static int
7690 iwn4965_post_alive(struct iwn_softc *sc)
7691 {
7692 	int error, qid;
7693 
7694 	if ((error = iwn_nic_lock(sc)) != 0)
7695 		return error;
7696 
7697 	DPRINTF(sc, IWN_DEBUG_TRACE, "->Doing %s\n", __func__);
7698 
7699 	/* Clear TX scheduler state in SRAM. */
7700 	sc->sched_base = iwn_prph_read(sc, IWN_SCHED_SRAM_ADDR);
7701 	iwn_mem_set_region_4(sc, sc->sched_base + IWN4965_SCHED_CTX_OFF, 0,
7702 	    IWN4965_SCHED_CTX_LEN / sizeof (uint32_t));
7703 
7704 	/* Set physical address of TX scheduler rings (1KB aligned). */
7705 	iwn_prph_write(sc, IWN4965_SCHED_DRAM_ADDR, sc->sched_dma.paddr >> 10);
7706 
7707 	IWN_SETBITS(sc, IWN_FH_TX_CHICKEN, IWN_FH_TX_CHICKEN_SCHED_RETRY);
7708 
7709 	/* Disable chain mode for all our 16 queues. */
7710 	iwn_prph_write(sc, IWN4965_SCHED_QCHAIN_SEL, 0);
7711 
7712 	for (qid = 0; qid < IWN4965_NTXQUEUES; qid++) {
7713 		iwn_prph_write(sc, IWN4965_SCHED_QUEUE_RDPTR(qid), 0);
7714 		IWN_WRITE(sc, IWN_HBUS_TARG_WRPTR, qid << 8 | 0);
7715 
7716 		/* Set scheduler window size. */
7717 		iwn_mem_write(sc, sc->sched_base +
7718 		    IWN4965_SCHED_QUEUE_OFFSET(qid), IWN_SCHED_WINSZ);
7719 		/* Set scheduler frame limit. */
7720 		iwn_mem_write(sc, sc->sched_base +
7721 		    IWN4965_SCHED_QUEUE_OFFSET(qid) + 4,
7722 		    IWN_SCHED_LIMIT << 16);
7723 	}
7724 
7725 	/* Enable interrupts for all our 16 queues. */
7726 	iwn_prph_write(sc, IWN4965_SCHED_INTR_MASK, 0xffff);
7727 	/* Identify TX FIFO rings (0-7). */
7728 	iwn_prph_write(sc, IWN4965_SCHED_TXFACT, 0xff);
7729 
7730 	/* Mark TX rings (4 EDCA + cmd + 2 HCCA) as active. */
7731 	for (qid = 0; qid < 7; qid++) {
7732 		static uint8_t qid2fifo[] = { 3, 2, 1, 0, 4, 5, 6 };
7733 		iwn_prph_write(sc, IWN4965_SCHED_QUEUE_STATUS(qid),
7734 		    IWN4965_TXQ_STATUS_ACTIVE | qid2fifo[qid] << 1);
7735 	}
7736 	iwn_nic_unlock(sc);
7737 	return 0;
7738 }
7739 
7740 /*
7741  * This function is called after the initialization or runtime firmware
7742  * notifies us of its readiness (called in a process context).
7743  */
7744 static int
7745 iwn5000_post_alive(struct iwn_softc *sc)
7746 {
7747 	int error, qid;
7748 
7749 	DPRINTF(sc, IWN_DEBUG_TRACE, "->%s begin\n", __func__);
7750 
7751 	/* Switch to using ICT interrupt mode. */
7752 	iwn5000_ict_reset(sc);
7753 
7754 	if ((error = iwn_nic_lock(sc)) != 0){
7755 		DPRINTF(sc, IWN_DEBUG_TRACE, "->%s end in error\n", __func__);
7756 		return error;
7757 	}
7758 
7759 	/* Clear TX scheduler state in SRAM. */
7760 	sc->sched_base = iwn_prph_read(sc, IWN_SCHED_SRAM_ADDR);
7761 	iwn_mem_set_region_4(sc, sc->sched_base + IWN5000_SCHED_CTX_OFF, 0,
7762 	    IWN5000_SCHED_CTX_LEN / sizeof (uint32_t));
7763 
7764 	/* Set physical address of TX scheduler rings (1KB aligned). */
7765 	iwn_prph_write(sc, IWN5000_SCHED_DRAM_ADDR, sc->sched_dma.paddr >> 10);
7766 
7767 	IWN_SETBITS(sc, IWN_FH_TX_CHICKEN, IWN_FH_TX_CHICKEN_SCHED_RETRY);
7768 
7769 	/* Enable chain mode for all queues, except command queue. */
7770 	if (sc->sc_flags & IWN_FLAG_PAN_SUPPORT)
7771 		iwn_prph_write(sc, IWN5000_SCHED_QCHAIN_SEL, 0xfffdf);
7772 	else
7773 		iwn_prph_write(sc, IWN5000_SCHED_QCHAIN_SEL, 0xfffef);
7774 	iwn_prph_write(sc, IWN5000_SCHED_AGGR_SEL, 0);
7775 
7776 	for (qid = 0; qid < IWN5000_NTXQUEUES; qid++) {
7777 		iwn_prph_write(sc, IWN5000_SCHED_QUEUE_RDPTR(qid), 0);
7778 		IWN_WRITE(sc, IWN_HBUS_TARG_WRPTR, qid << 8 | 0);
7779 
7780 		iwn_mem_write(sc, sc->sched_base +
7781 		    IWN5000_SCHED_QUEUE_OFFSET(qid), 0);
7782 		/* Set scheduler window size and frame limit. */
7783 		iwn_mem_write(sc, sc->sched_base +
7784 		    IWN5000_SCHED_QUEUE_OFFSET(qid) + 4,
7785 		    IWN_SCHED_LIMIT << 16 | IWN_SCHED_WINSZ);
7786 	}
7787 
7788 	/* Enable interrupts for all our 20 queues. */
7789 	iwn_prph_write(sc, IWN5000_SCHED_INTR_MASK, 0xfffff);
7790 	/* Identify TX FIFO rings (0-7). */
7791 	iwn_prph_write(sc, IWN5000_SCHED_TXFACT, 0xff);
7792 
7793 	/* Mark TX rings (4 EDCA + cmd + 2 HCCA) as active. */
7794 	if (sc->sc_flags & IWN_FLAG_PAN_SUPPORT) {
7795 		/* Mark TX rings as active. */
7796 		for (qid = 0; qid < 11; qid++) {
7797 			static uint8_t qid2fifo[] = { 3, 2, 1, 0, 0, 4, 2, 5, 4, 7, 5 };
7798 			iwn_prph_write(sc, IWN5000_SCHED_QUEUE_STATUS(qid),
7799 			    IWN5000_TXQ_STATUS_ACTIVE | qid2fifo[qid]);
7800 		}
7801 	} else {
7802 		/* Mark TX rings (4 EDCA + cmd + 2 HCCA) as active. */
7803 		for (qid = 0; qid < 7; qid++) {
7804 			static uint8_t qid2fifo[] = { 3, 2, 1, 0, 7, 5, 6 };
7805 			iwn_prph_write(sc, IWN5000_SCHED_QUEUE_STATUS(qid),
7806 			    IWN5000_TXQ_STATUS_ACTIVE | qid2fifo[qid]);
7807 		}
7808 	}
7809 	iwn_nic_unlock(sc);
7810 
7811 	/* Configure WiMAX coexistence for combo adapters. */
7812 	error = iwn5000_send_wimax_coex(sc);
7813 	if (error != 0) {
7814 		device_printf(sc->sc_dev,
7815 		    "%s: could not configure WiMAX coexistence, error %d\n",
7816 		    __func__, error);
7817 		return error;
7818 	}
7819 	if (sc->hw_type != IWN_HW_REV_TYPE_5150) {
7820 		/* Perform crystal calibration. */
7821 		error = iwn5000_crystal_calib(sc);
7822 		if (error != 0) {
7823 			device_printf(sc->sc_dev,
7824 			    "%s: crystal calibration failed, error %d\n",
7825 			    __func__, error);
7826 			return error;
7827 		}
7828 	}
7829 	if (!(sc->sc_flags & IWN_FLAG_CALIB_DONE)) {
7830 		/* Query calibration from the initialization firmware. */
7831 		if ((error = iwn5000_query_calibration(sc)) != 0) {
7832 			device_printf(sc->sc_dev,
7833 			    "%s: could not query calibration, error %d\n",
7834 			    __func__, error);
7835 			return error;
7836 		}
7837 		/*
7838 		 * We have the calibration results now, reboot with the
7839 		 * runtime firmware (call ourselves recursively!)
7840 		 */
7841 		iwn_hw_stop(sc);
7842 		error = iwn_hw_init(sc);
7843 	} else {
7844 		/* Send calibration results to runtime firmware. */
7845 		error = iwn5000_send_calibration(sc);
7846 	}
7847 
7848 	DPRINTF(sc, IWN_DEBUG_TRACE, "->%s: end\n",__func__);
7849 
7850 	return error;
7851 }
7852 
7853 /*
7854  * The firmware boot code is small and is intended to be copied directly into
7855  * the NIC internal memory (no DMA transfer).
7856  */
7857 static int
7858 iwn4965_load_bootcode(struct iwn_softc *sc, const uint8_t *ucode, int size)
7859 {
7860 	int error, ntries;
7861 
7862 	size /= sizeof (uint32_t);
7863 
7864 	if ((error = iwn_nic_lock(sc)) != 0)
7865 		return error;
7866 
7867 	/* Copy microcode image into NIC memory. */
7868 	iwn_prph_write_region_4(sc, IWN_BSM_SRAM_BASE,
7869 	    (const uint32_t *)ucode, size);
7870 
7871 	iwn_prph_write(sc, IWN_BSM_WR_MEM_SRC, 0);
7872 	iwn_prph_write(sc, IWN_BSM_WR_MEM_DST, IWN_FW_TEXT_BASE);
7873 	iwn_prph_write(sc, IWN_BSM_WR_DWCOUNT, size);
7874 
7875 	/* Start boot load now. */
7876 	iwn_prph_write(sc, IWN_BSM_WR_CTRL, IWN_BSM_WR_CTRL_START);
7877 
7878 	/* Wait for transfer to complete. */
7879 	for (ntries = 0; ntries < 1000; ntries++) {
7880 		if (!(iwn_prph_read(sc, IWN_BSM_WR_CTRL) &
7881 		    IWN_BSM_WR_CTRL_START))
7882 			break;
7883 		DELAY(10);
7884 	}
7885 	if (ntries == 1000) {
7886 		device_printf(sc->sc_dev, "%s: could not load boot firmware\n",
7887 		    __func__);
7888 		iwn_nic_unlock(sc);
7889 		return ETIMEDOUT;
7890 	}
7891 
7892 	/* Enable boot after power up. */
7893 	iwn_prph_write(sc, IWN_BSM_WR_CTRL, IWN_BSM_WR_CTRL_START_EN);
7894 
7895 	iwn_nic_unlock(sc);
7896 	return 0;
7897 }
7898 
7899 static int
7900 iwn4965_load_firmware(struct iwn_softc *sc)
7901 {
7902 	struct iwn_fw_info *fw = &sc->fw;
7903 	struct iwn_dma_info *dma = &sc->fw_dma;
7904 	int error;
7905 
7906 	/* Copy initialization sections into pre-allocated DMA-safe memory. */
7907 	memcpy(dma->vaddr, fw->init.data, fw->init.datasz);
7908 	bus_dmamap_sync(dma->tag, dma->map, BUS_DMASYNC_PREWRITE);
7909 	memcpy(dma->vaddr + IWN4965_FW_DATA_MAXSZ,
7910 	    fw->init.text, fw->init.textsz);
7911 	bus_dmamap_sync(dma->tag, dma->map, BUS_DMASYNC_PREWRITE);
7912 
7913 	/* Tell adapter where to find initialization sections. */
7914 	if ((error = iwn_nic_lock(sc)) != 0)
7915 		return error;
7916 	iwn_prph_write(sc, IWN_BSM_DRAM_DATA_ADDR, dma->paddr >> 4);
7917 	iwn_prph_write(sc, IWN_BSM_DRAM_DATA_SIZE, fw->init.datasz);
7918 	iwn_prph_write(sc, IWN_BSM_DRAM_TEXT_ADDR,
7919 	    (dma->paddr + IWN4965_FW_DATA_MAXSZ) >> 4);
7920 	iwn_prph_write(sc, IWN_BSM_DRAM_TEXT_SIZE, fw->init.textsz);
7921 	iwn_nic_unlock(sc);
7922 
7923 	/* Load firmware boot code. */
7924 	error = iwn4965_load_bootcode(sc, fw->boot.text, fw->boot.textsz);
7925 	if (error != 0) {
7926 		device_printf(sc->sc_dev, "%s: could not load boot firmware\n",
7927 		    __func__);
7928 		return error;
7929 	}
7930 	/* Now press "execute". */
7931 	IWN_WRITE(sc, IWN_RESET, 0);
7932 
7933 	/* Wait at most one second for first alive notification. */
7934 	if ((error = msleep(sc, &sc->sc_mtx, PCATCH, "iwninit", hz)) != 0) {
7935 		device_printf(sc->sc_dev,
7936 		    "%s: timeout waiting for adapter to initialize, error %d\n",
7937 		    __func__, error);
7938 		return error;
7939 	}
7940 
7941 	/* Retrieve current temperature for initial TX power calibration. */
7942 	sc->rawtemp = sc->ucode_info.temp[3].chan20MHz;
7943 	sc->temp = iwn4965_get_temperature(sc);
7944 
7945 	/* Copy runtime sections into pre-allocated DMA-safe memory. */
7946 	memcpy(dma->vaddr, fw->main.data, fw->main.datasz);
7947 	bus_dmamap_sync(dma->tag, dma->map, BUS_DMASYNC_PREWRITE);
7948 	memcpy(dma->vaddr + IWN4965_FW_DATA_MAXSZ,
7949 	    fw->main.text, fw->main.textsz);
7950 	bus_dmamap_sync(dma->tag, dma->map, BUS_DMASYNC_PREWRITE);
7951 
7952 	/* Tell adapter where to find runtime sections. */
7953 	if ((error = iwn_nic_lock(sc)) != 0)
7954 		return error;
7955 	iwn_prph_write(sc, IWN_BSM_DRAM_DATA_ADDR, dma->paddr >> 4);
7956 	iwn_prph_write(sc, IWN_BSM_DRAM_DATA_SIZE, fw->main.datasz);
7957 	iwn_prph_write(sc, IWN_BSM_DRAM_TEXT_ADDR,
7958 	    (dma->paddr + IWN4965_FW_DATA_MAXSZ) >> 4);
7959 	iwn_prph_write(sc, IWN_BSM_DRAM_TEXT_SIZE,
7960 	    IWN_FW_UPDATED | fw->main.textsz);
7961 	iwn_nic_unlock(sc);
7962 
7963 	return 0;
7964 }
7965 
7966 static int
7967 iwn5000_load_firmware_section(struct iwn_softc *sc, uint32_t dst,
7968     const uint8_t *section, int size)
7969 {
7970 	struct iwn_dma_info *dma = &sc->fw_dma;
7971 	int error;
7972 
7973 	DPRINTF(sc, IWN_DEBUG_TRACE, "->Doing %s\n", __func__);
7974 
7975 	/* Copy firmware section into pre-allocated DMA-safe memory. */
7976 	memcpy(dma->vaddr, section, size);
7977 	bus_dmamap_sync(dma->tag, dma->map, BUS_DMASYNC_PREWRITE);
7978 
7979 	if ((error = iwn_nic_lock(sc)) != 0)
7980 		return error;
7981 
7982 	IWN_WRITE(sc, IWN_FH_TX_CONFIG(IWN_SRVC_DMACHNL),
7983 	    IWN_FH_TX_CONFIG_DMA_PAUSE);
7984 
7985 	IWN_WRITE(sc, IWN_FH_SRAM_ADDR(IWN_SRVC_DMACHNL), dst);
7986 	IWN_WRITE(sc, IWN_FH_TFBD_CTRL0(IWN_SRVC_DMACHNL),
7987 	    IWN_LOADDR(dma->paddr));
7988 	IWN_WRITE(sc, IWN_FH_TFBD_CTRL1(IWN_SRVC_DMACHNL),
7989 	    IWN_HIADDR(dma->paddr) << 28 | size);
7990 	IWN_WRITE(sc, IWN_FH_TXBUF_STATUS(IWN_SRVC_DMACHNL),
7991 	    IWN_FH_TXBUF_STATUS_TBNUM(1) |
7992 	    IWN_FH_TXBUF_STATUS_TBIDX(1) |
7993 	    IWN_FH_TXBUF_STATUS_TFBD_VALID);
7994 
7995 	/* Kick Flow Handler to start DMA transfer. */
7996 	IWN_WRITE(sc, IWN_FH_TX_CONFIG(IWN_SRVC_DMACHNL),
7997 	    IWN_FH_TX_CONFIG_DMA_ENA | IWN_FH_TX_CONFIG_CIRQ_HOST_ENDTFD);
7998 
7999 	iwn_nic_unlock(sc);
8000 
8001 	/* Wait at most five seconds for FH DMA transfer to complete. */
8002 	return msleep(sc, &sc->sc_mtx, PCATCH, "iwninit", 5 * hz);
8003 }
8004 
8005 static int
8006 iwn5000_load_firmware(struct iwn_softc *sc)
8007 {
8008 	struct iwn_fw_part *fw;
8009 	int error;
8010 
8011 	DPRINTF(sc, IWN_DEBUG_TRACE, "->Doing %s\n", __func__);
8012 
8013 	/* Load the initialization firmware on first boot only. */
8014 	fw = (sc->sc_flags & IWN_FLAG_CALIB_DONE) ?
8015 	    &sc->fw.main : &sc->fw.init;
8016 
8017 	error = iwn5000_load_firmware_section(sc, IWN_FW_TEXT_BASE,
8018 	    fw->text, fw->textsz);
8019 	if (error != 0) {
8020 		device_printf(sc->sc_dev,
8021 		    "%s: could not load firmware %s section, error %d\n",
8022 		    __func__, ".text", error);
8023 		return error;
8024 	}
8025 	error = iwn5000_load_firmware_section(sc, IWN_FW_DATA_BASE,
8026 	    fw->data, fw->datasz);
8027 	if (error != 0) {
8028 		device_printf(sc->sc_dev,
8029 		    "%s: could not load firmware %s section, error %d\n",
8030 		    __func__, ".data", error);
8031 		return error;
8032 	}
8033 
8034 	/* Now press "execute". */
8035 	IWN_WRITE(sc, IWN_RESET, 0);
8036 	return 0;
8037 }
8038 
8039 /*
8040  * Extract text and data sections from a legacy firmware image.
8041  */
8042 static int
8043 iwn_read_firmware_leg(struct iwn_softc *sc, struct iwn_fw_info *fw)
8044 {
8045 	const uint32_t *ptr;
8046 	size_t hdrlen = 24;
8047 	uint32_t rev;
8048 
8049 	ptr = (const uint32_t *)fw->data;
8050 	rev = le32toh(*ptr++);
8051 
8052 	sc->ucode_rev = rev;
8053 
8054 	/* Check firmware API version. */
8055 	if (IWN_FW_API(rev) <= 1) {
8056 		device_printf(sc->sc_dev,
8057 		    "%s: bad firmware, need API version >=2\n", __func__);
8058 		return EINVAL;
8059 	}
8060 	if (IWN_FW_API(rev) >= 3) {
8061 		/* Skip build number (version 2 header). */
8062 		hdrlen += 4;
8063 		ptr++;
8064 	}
8065 	if (fw->size < hdrlen) {
8066 		device_printf(sc->sc_dev, "%s: firmware too short: %zu bytes\n",
8067 		    __func__, fw->size);
8068 		return EINVAL;
8069 	}
8070 	fw->main.textsz = le32toh(*ptr++);
8071 	fw->main.datasz = le32toh(*ptr++);
8072 	fw->init.textsz = le32toh(*ptr++);
8073 	fw->init.datasz = le32toh(*ptr++);
8074 	fw->boot.textsz = le32toh(*ptr++);
8075 
8076 	/* Check that all firmware sections fit. */
8077 	if (fw->size < hdrlen + fw->main.textsz + fw->main.datasz +
8078 	    fw->init.textsz + fw->init.datasz + fw->boot.textsz) {
8079 		device_printf(sc->sc_dev, "%s: firmware too short: %zu bytes\n",
8080 		    __func__, fw->size);
8081 		return EINVAL;
8082 	}
8083 
8084 	/* Get pointers to firmware sections. */
8085 	fw->main.text = (const uint8_t *)ptr;
8086 	fw->main.data = fw->main.text + fw->main.textsz;
8087 	fw->init.text = fw->main.data + fw->main.datasz;
8088 	fw->init.data = fw->init.text + fw->init.textsz;
8089 	fw->boot.text = fw->init.data + fw->init.datasz;
8090 	return 0;
8091 }
8092 
8093 /*
8094  * Extract text and data sections from a TLV firmware image.
8095  */
8096 static int
8097 iwn_read_firmware_tlv(struct iwn_softc *sc, struct iwn_fw_info *fw,
8098     uint16_t alt)
8099 {
8100 	const struct iwn_fw_tlv_hdr *hdr;
8101 	const struct iwn_fw_tlv *tlv;
8102 	const uint8_t *ptr, *end;
8103 	uint64_t altmask;
8104 	uint32_t len, tmp;
8105 
8106 	if (fw->size < sizeof (*hdr)) {
8107 		device_printf(sc->sc_dev, "%s: firmware too short: %zu bytes\n",
8108 		    __func__, fw->size);
8109 		return EINVAL;
8110 	}
8111 	hdr = (const struct iwn_fw_tlv_hdr *)fw->data;
8112 	if (hdr->signature != htole32(IWN_FW_SIGNATURE)) {
8113 		device_printf(sc->sc_dev, "%s: bad firmware signature 0x%08x\n",
8114 		    __func__, le32toh(hdr->signature));
8115 		return EINVAL;
8116 	}
8117 	DPRINTF(sc, IWN_DEBUG_RESET, "FW: \"%.64s\", build 0x%x\n", hdr->descr,
8118 	    le32toh(hdr->build));
8119 	sc->ucode_rev = le32toh(hdr->rev);
8120 
8121 	/*
8122 	 * Select the closest supported alternative that is less than
8123 	 * or equal to the specified one.
8124 	 */
8125 	altmask = le64toh(hdr->altmask);
8126 	while (alt > 0 && !(altmask & (1ULL << alt)))
8127 		alt--;	/* Downgrade. */
8128 	DPRINTF(sc, IWN_DEBUG_RESET, "using alternative %d\n", alt);
8129 
8130 	ptr = (const uint8_t *)(hdr + 1);
8131 	end = (const uint8_t *)(fw->data + fw->size);
8132 
8133 	/* Parse type-length-value fields. */
8134 	while (ptr + sizeof (*tlv) <= end) {
8135 		tlv = (const struct iwn_fw_tlv *)ptr;
8136 		len = le32toh(tlv->len);
8137 
8138 		ptr += sizeof (*tlv);
8139 		if (ptr + len > end) {
8140 			device_printf(sc->sc_dev,
8141 			    "%s: firmware too short: %zu bytes\n", __func__,
8142 			    fw->size);
8143 			return EINVAL;
8144 		}
8145 		/* Skip other alternatives. */
8146 		if (tlv->alt != 0 && tlv->alt != htole16(alt))
8147 			goto next;
8148 
8149 		switch (le16toh(tlv->type)) {
8150 		case IWN_FW_TLV_MAIN_TEXT:
8151 			fw->main.text = ptr;
8152 			fw->main.textsz = len;
8153 			break;
8154 		case IWN_FW_TLV_MAIN_DATA:
8155 			fw->main.data = ptr;
8156 			fw->main.datasz = len;
8157 			break;
8158 		case IWN_FW_TLV_INIT_TEXT:
8159 			fw->init.text = ptr;
8160 			fw->init.textsz = len;
8161 			break;
8162 		case IWN_FW_TLV_INIT_DATA:
8163 			fw->init.data = ptr;
8164 			fw->init.datasz = len;
8165 			break;
8166 		case IWN_FW_TLV_BOOT_TEXT:
8167 			fw->boot.text = ptr;
8168 			fw->boot.textsz = len;
8169 			break;
8170 		case IWN_FW_TLV_ENH_SENS:
8171 			if (!len)
8172 				sc->sc_flags |= IWN_FLAG_ENH_SENS;
8173 			break;
8174 		case IWN_FW_TLV_PHY_CALIB:
8175 			tmp = le32toh(*ptr);
8176 			if (tmp < 253) {
8177 				sc->reset_noise_gain = tmp;
8178 				sc->noise_gain = tmp + 1;
8179 			}
8180 			break;
8181 		case IWN_FW_TLV_PAN:
8182 			sc->sc_flags |= IWN_FLAG_PAN_SUPPORT;
8183 			DPRINTF(sc, IWN_DEBUG_RESET,
8184 			    "PAN Support found: %d\n", 1);
8185 			break;
8186 		case IWN_FW_TLV_FLAGS:
8187 			if (len < sizeof(uint32_t))
8188 				break;
8189 			if (len % sizeof(uint32_t))
8190 				break;
8191 			sc->tlv_feature_flags = le32toh(*ptr);
8192 			DPRINTF(sc, IWN_DEBUG_RESET,
8193 			    "%s: feature: 0x%08x\n",
8194 			    __func__,
8195 			    sc->tlv_feature_flags);
8196 			break;
8197 		case IWN_FW_TLV_PBREQ_MAXLEN:
8198 		case IWN_FW_TLV_RUNT_EVTLOG_PTR:
8199 		case IWN_FW_TLV_RUNT_EVTLOG_SIZE:
8200 		case IWN_FW_TLV_RUNT_ERRLOG_PTR:
8201 		case IWN_FW_TLV_INIT_EVTLOG_PTR:
8202 		case IWN_FW_TLV_INIT_EVTLOG_SIZE:
8203 		case IWN_FW_TLV_INIT_ERRLOG_PTR:
8204 		case IWN_FW_TLV_WOWLAN_INST:
8205 		case IWN_FW_TLV_WOWLAN_DATA:
8206 			DPRINTF(sc, IWN_DEBUG_RESET,
8207 			    "TLV type %d recognized but not handled\n",
8208 			    le16toh(tlv->type));
8209 			break;
8210 		default:
8211 			DPRINTF(sc, IWN_DEBUG_RESET,
8212 			    "TLV type %d not handled\n", le16toh(tlv->type));
8213 			break;
8214 		}
8215  next:		/* TLV fields are 32-bit aligned. */
8216 		ptr += (len + 3) & ~3;
8217 	}
8218 	return 0;
8219 }
8220 
8221 static int
8222 iwn_read_firmware(struct iwn_softc *sc)
8223 {
8224 	struct iwn_fw_info *fw = &sc->fw;
8225 	int error;
8226 
8227 	DPRINTF(sc, IWN_DEBUG_TRACE, "->Doing %s\n", __func__);
8228 
8229 	IWN_UNLOCK(sc);
8230 
8231 	memset(fw, 0, sizeof (*fw));
8232 
8233 	/* Read firmware image from filesystem. */
8234 	sc->fw_fp = firmware_get(sc->fwname);
8235 	if (sc->fw_fp == NULL) {
8236 		device_printf(sc->sc_dev, "%s: could not read firmware %s\n",
8237 		    __func__, sc->fwname);
8238 		IWN_LOCK(sc);
8239 		return EINVAL;
8240 	}
8241 	IWN_LOCK(sc);
8242 
8243 	fw->size = sc->fw_fp->datasize;
8244 	fw->data = (const uint8_t *)sc->fw_fp->data;
8245 	if (fw->size < sizeof (uint32_t)) {
8246 		device_printf(sc->sc_dev, "%s: firmware too short: %zu bytes\n",
8247 		    __func__, fw->size);
8248 		firmware_put(sc->fw_fp, FIRMWARE_UNLOAD);
8249 		sc->fw_fp = NULL;
8250 		return EINVAL;
8251 	}
8252 
8253 	/* Retrieve text and data sections. */
8254 	if (*(const uint32_t *)fw->data != 0)	/* Legacy image. */
8255 		error = iwn_read_firmware_leg(sc, fw);
8256 	else
8257 		error = iwn_read_firmware_tlv(sc, fw, 1);
8258 	if (error != 0) {
8259 		device_printf(sc->sc_dev,
8260 		    "%s: could not read firmware sections, error %d\n",
8261 		    __func__, error);
8262 		firmware_put(sc->fw_fp, FIRMWARE_UNLOAD);
8263 		sc->fw_fp = NULL;
8264 		return error;
8265 	}
8266 
8267 	device_printf(sc->sc_dev, "%s: ucode rev=0x%08x\n", __func__, sc->ucode_rev);
8268 
8269 	/* Make sure text and data sections fit in hardware memory. */
8270 	if (fw->main.textsz > sc->fw_text_maxsz ||
8271 	    fw->main.datasz > sc->fw_data_maxsz ||
8272 	    fw->init.textsz > sc->fw_text_maxsz ||
8273 	    fw->init.datasz > sc->fw_data_maxsz ||
8274 	    fw->boot.textsz > IWN_FW_BOOT_TEXT_MAXSZ ||
8275 	    (fw->boot.textsz & 3) != 0) {
8276 		device_printf(sc->sc_dev, "%s: firmware sections too large\n",
8277 		    __func__);
8278 		firmware_put(sc->fw_fp, FIRMWARE_UNLOAD);
8279 		sc->fw_fp = NULL;
8280 		return EINVAL;
8281 	}
8282 
8283 	/* We can proceed with loading the firmware. */
8284 	return 0;
8285 }
8286 
8287 static int
8288 iwn_clock_wait(struct iwn_softc *sc)
8289 {
8290 	int ntries;
8291 
8292 	/* Set "initialization complete" bit. */
8293 	IWN_SETBITS(sc, IWN_GP_CNTRL, IWN_GP_CNTRL_INIT_DONE);
8294 
8295 	/* Wait for clock stabilization. */
8296 	for (ntries = 0; ntries < 2500; ntries++) {
8297 		if (IWN_READ(sc, IWN_GP_CNTRL) & IWN_GP_CNTRL_MAC_CLOCK_READY)
8298 			return 0;
8299 		DELAY(10);
8300 	}
8301 	device_printf(sc->sc_dev,
8302 	    "%s: timeout waiting for clock stabilization\n", __func__);
8303 	return ETIMEDOUT;
8304 }
8305 
8306 static int
8307 iwn_apm_init(struct iwn_softc *sc)
8308 {
8309 	uint32_t reg;
8310 	int error;
8311 
8312 	DPRINTF(sc, IWN_DEBUG_TRACE, "->Doing %s\n", __func__);
8313 
8314 	/* Disable L0s exit timer (NMI bug workaround). */
8315 	IWN_SETBITS(sc, IWN_GIO_CHICKEN, IWN_GIO_CHICKEN_DIS_L0S_TIMER);
8316 	/* Don't wait for ICH L0s (ICH bug workaround). */
8317 	IWN_SETBITS(sc, IWN_GIO_CHICKEN, IWN_GIO_CHICKEN_L1A_NO_L0S_RX);
8318 
8319 	/* Set FH wait threshold to max (HW bug under stress workaround). */
8320 	IWN_SETBITS(sc, IWN_DBG_HPET_MEM, 0xffff0000);
8321 
8322 	/* Enable HAP INTA to move adapter from L1a to L0s. */
8323 	IWN_SETBITS(sc, IWN_HW_IF_CONFIG, IWN_HW_IF_CONFIG_HAP_WAKE_L1A);
8324 
8325 	/* Retrieve PCIe Active State Power Management (ASPM). */
8326 	reg = pci_read_config(sc->sc_dev, sc->sc_cap_off + 0x10, 1);
8327 	/* Workaround for HW instability in PCIe L0->L0s->L1 transition. */
8328 	if (reg & 0x02)	/* L1 Entry enabled. */
8329 		IWN_SETBITS(sc, IWN_GIO, IWN_GIO_L0S_ENA);
8330 	else
8331 		IWN_CLRBITS(sc, IWN_GIO, IWN_GIO_L0S_ENA);
8332 
8333 	if (sc->base_params->pll_cfg_val)
8334 		IWN_SETBITS(sc, IWN_ANA_PLL, sc->base_params->pll_cfg_val);
8335 
8336 	/* Wait for clock stabilization before accessing prph. */
8337 	if ((error = iwn_clock_wait(sc)) != 0)
8338 		return error;
8339 
8340 	if ((error = iwn_nic_lock(sc)) != 0)
8341 		return error;
8342 	if (sc->hw_type == IWN_HW_REV_TYPE_4965) {
8343 		/* Enable DMA and BSM (Bootstrap State Machine). */
8344 		iwn_prph_write(sc, IWN_APMG_CLK_EN,
8345 		    IWN_APMG_CLK_CTRL_DMA_CLK_RQT |
8346 		    IWN_APMG_CLK_CTRL_BSM_CLK_RQT);
8347 	} else {
8348 		/* Enable DMA. */
8349 		iwn_prph_write(sc, IWN_APMG_CLK_EN,
8350 		    IWN_APMG_CLK_CTRL_DMA_CLK_RQT);
8351 	}
8352 	DELAY(20);
8353 	/* Disable L1-Active. */
8354 	iwn_prph_setbits(sc, IWN_APMG_PCI_STT, IWN_APMG_PCI_STT_L1A_DIS);
8355 	iwn_nic_unlock(sc);
8356 
8357 	return 0;
8358 }
8359 
8360 static void
8361 iwn_apm_stop_master(struct iwn_softc *sc)
8362 {
8363 	int ntries;
8364 
8365 	/* Stop busmaster DMA activity. */
8366 	IWN_SETBITS(sc, IWN_RESET, IWN_RESET_STOP_MASTER);
8367 	for (ntries = 0; ntries < 100; ntries++) {
8368 		if (IWN_READ(sc, IWN_RESET) & IWN_RESET_MASTER_DISABLED)
8369 			return;
8370 		DELAY(10);
8371 	}
8372 	device_printf(sc->sc_dev, "%s: timeout waiting for master\n", __func__);
8373 }
8374 
8375 static void
8376 iwn_apm_stop(struct iwn_softc *sc)
8377 {
8378 	iwn_apm_stop_master(sc);
8379 
8380 	/* Reset the entire device. */
8381 	IWN_SETBITS(sc, IWN_RESET, IWN_RESET_SW);
8382 	DELAY(10);
8383 	/* Clear "initialization complete" bit. */
8384 	IWN_CLRBITS(sc, IWN_GP_CNTRL, IWN_GP_CNTRL_INIT_DONE);
8385 }
8386 
8387 static int
8388 iwn4965_nic_config(struct iwn_softc *sc)
8389 {
8390 	DPRINTF(sc, IWN_DEBUG_TRACE, "->Doing %s\n", __func__);
8391 
8392 	if (IWN_RFCFG_TYPE(sc->rfcfg) == 1) {
8393 		/*
8394 		 * I don't believe this to be correct but this is what the
8395 		 * vendor driver is doing. Probably the bits should not be
8396 		 * shifted in IWN_RFCFG_*.
8397 		 */
8398 		IWN_SETBITS(sc, IWN_HW_IF_CONFIG,
8399 		    IWN_RFCFG_TYPE(sc->rfcfg) |
8400 		    IWN_RFCFG_STEP(sc->rfcfg) |
8401 		    IWN_RFCFG_DASH(sc->rfcfg));
8402 	}
8403 	IWN_SETBITS(sc, IWN_HW_IF_CONFIG,
8404 	    IWN_HW_IF_CONFIG_RADIO_SI | IWN_HW_IF_CONFIG_MAC_SI);
8405 	return 0;
8406 }
8407 
8408 static int
8409 iwn5000_nic_config(struct iwn_softc *sc)
8410 {
8411 	uint32_t tmp;
8412 	int error;
8413 
8414 	DPRINTF(sc, IWN_DEBUG_TRACE, "->Doing %s\n", __func__);
8415 
8416 	if (IWN_RFCFG_TYPE(sc->rfcfg) < 3) {
8417 		IWN_SETBITS(sc, IWN_HW_IF_CONFIG,
8418 		    IWN_RFCFG_TYPE(sc->rfcfg) |
8419 		    IWN_RFCFG_STEP(sc->rfcfg) |
8420 		    IWN_RFCFG_DASH(sc->rfcfg));
8421 	}
8422 	IWN_SETBITS(sc, IWN_HW_IF_CONFIG,
8423 	    IWN_HW_IF_CONFIG_RADIO_SI | IWN_HW_IF_CONFIG_MAC_SI);
8424 
8425 	if ((error = iwn_nic_lock(sc)) != 0)
8426 		return error;
8427 	iwn_prph_setbits(sc, IWN_APMG_PS, IWN_APMG_PS_EARLY_PWROFF_DIS);
8428 
8429 	if (sc->hw_type == IWN_HW_REV_TYPE_1000) {
8430 		/*
8431 		 * Select first Switching Voltage Regulator (1.32V) to
8432 		 * solve a stability issue related to noisy DC2DC line
8433 		 * in the silicon of 1000 Series.
8434 		 */
8435 		tmp = iwn_prph_read(sc, IWN_APMG_DIGITAL_SVR);
8436 		tmp &= ~IWN_APMG_DIGITAL_SVR_VOLTAGE_MASK;
8437 		tmp |= IWN_APMG_DIGITAL_SVR_VOLTAGE_1_32;
8438 		iwn_prph_write(sc, IWN_APMG_DIGITAL_SVR, tmp);
8439 	}
8440 	iwn_nic_unlock(sc);
8441 
8442 	if (sc->sc_flags & IWN_FLAG_INTERNAL_PA) {
8443 		/* Use internal power amplifier only. */
8444 		IWN_WRITE(sc, IWN_GP_DRIVER, IWN_GP_DRIVER_RADIO_2X2_IPA);
8445 	}
8446 	if (sc->base_params->additional_nic_config && sc->calib_ver >= 6) {
8447 		/* Indicate that ROM calibration version is >=6. */
8448 		IWN_SETBITS(sc, IWN_GP_DRIVER, IWN_GP_DRIVER_CALIB_VER6);
8449 	}
8450 	if (sc->base_params->additional_gp_drv_bit)
8451 		IWN_SETBITS(sc, IWN_GP_DRIVER,
8452 		    sc->base_params->additional_gp_drv_bit);
8453 	return 0;
8454 }
8455 
8456 /*
8457  * Take NIC ownership over Intel Active Management Technology (AMT).
8458  */
8459 static int
8460 iwn_hw_prepare(struct iwn_softc *sc)
8461 {
8462 	int ntries;
8463 
8464 	DPRINTF(sc, IWN_DEBUG_TRACE, "->Doing %s\n", __func__);
8465 
8466 	/* Check if hardware is ready. */
8467 	IWN_SETBITS(sc, IWN_HW_IF_CONFIG, IWN_HW_IF_CONFIG_NIC_READY);
8468 	for (ntries = 0; ntries < 5; ntries++) {
8469 		if (IWN_READ(sc, IWN_HW_IF_CONFIG) &
8470 		    IWN_HW_IF_CONFIG_NIC_READY)
8471 			return 0;
8472 		DELAY(10);
8473 	}
8474 
8475 	/* Hardware not ready, force into ready state. */
8476 	IWN_SETBITS(sc, IWN_HW_IF_CONFIG, IWN_HW_IF_CONFIG_PREPARE);
8477 	for (ntries = 0; ntries < 15000; ntries++) {
8478 		if (!(IWN_READ(sc, IWN_HW_IF_CONFIG) &
8479 		    IWN_HW_IF_CONFIG_PREPARE_DONE))
8480 			break;
8481 		DELAY(10);
8482 	}
8483 	if (ntries == 15000)
8484 		return ETIMEDOUT;
8485 
8486 	/* Hardware should be ready now. */
8487 	IWN_SETBITS(sc, IWN_HW_IF_CONFIG, IWN_HW_IF_CONFIG_NIC_READY);
8488 	for (ntries = 0; ntries < 5; ntries++) {
8489 		if (IWN_READ(sc, IWN_HW_IF_CONFIG) &
8490 		    IWN_HW_IF_CONFIG_NIC_READY)
8491 			return 0;
8492 		DELAY(10);
8493 	}
8494 	return ETIMEDOUT;
8495 }
8496 
8497 static int
8498 iwn_hw_init(struct iwn_softc *sc)
8499 {
8500 	struct iwn_ops *ops = &sc->ops;
8501 	int error, chnl, qid;
8502 
8503 	DPRINTF(sc, IWN_DEBUG_TRACE, "->%s begin\n", __func__);
8504 
8505 	/* Clear pending interrupts. */
8506 	IWN_WRITE(sc, IWN_INT, 0xffffffff);
8507 
8508 	if ((error = iwn_apm_init(sc)) != 0) {
8509 		device_printf(sc->sc_dev,
8510 		    "%s: could not power ON adapter, error %d\n", __func__,
8511 		    error);
8512 		return error;
8513 	}
8514 
8515 	/* Select VMAIN power source. */
8516 	if ((error = iwn_nic_lock(sc)) != 0)
8517 		return error;
8518 	iwn_prph_clrbits(sc, IWN_APMG_PS, IWN_APMG_PS_PWR_SRC_MASK);
8519 	iwn_nic_unlock(sc);
8520 
8521 	/* Perform adapter-specific initialization. */
8522 	if ((error = ops->nic_config(sc)) != 0)
8523 		return error;
8524 
8525 	/* Initialize RX ring. */
8526 	if ((error = iwn_nic_lock(sc)) != 0)
8527 		return error;
8528 	IWN_WRITE(sc, IWN_FH_RX_CONFIG, 0);
8529 	IWN_WRITE(sc, IWN_FH_RX_WPTR, 0);
8530 	/* Set physical address of RX ring (256-byte aligned). */
8531 	IWN_WRITE(sc, IWN_FH_RX_BASE, sc->rxq.desc_dma.paddr >> 8);
8532 	/* Set physical address of RX status (16-byte aligned). */
8533 	IWN_WRITE(sc, IWN_FH_STATUS_WPTR, sc->rxq.stat_dma.paddr >> 4);
8534 	/* Enable RX. */
8535 	IWN_WRITE(sc, IWN_FH_RX_CONFIG,
8536 	    IWN_FH_RX_CONFIG_ENA           |
8537 	    IWN_FH_RX_CONFIG_IGN_RXF_EMPTY |	/* HW bug workaround */
8538 	    IWN_FH_RX_CONFIG_IRQ_DST_HOST  |
8539 	    IWN_FH_RX_CONFIG_SINGLE_FRAME  |
8540 	    IWN_FH_RX_CONFIG_RB_TIMEOUT(0) |
8541 	    IWN_FH_RX_CONFIG_NRBD(IWN_RX_RING_COUNT_LOG));
8542 	iwn_nic_unlock(sc);
8543 	IWN_WRITE(sc, IWN_FH_RX_WPTR, (IWN_RX_RING_COUNT - 1) & ~7);
8544 
8545 	if ((error = iwn_nic_lock(sc)) != 0)
8546 		return error;
8547 
8548 	/* Initialize TX scheduler. */
8549 	iwn_prph_write(sc, sc->sched_txfact_addr, 0);
8550 
8551 	/* Set physical address of "keep warm" page (16-byte aligned). */
8552 	IWN_WRITE(sc, IWN_FH_KW_ADDR, sc->kw_dma.paddr >> 4);
8553 
8554 	/* Initialize TX rings. */
8555 	for (qid = 0; qid < sc->ntxqs; qid++) {
8556 		struct iwn_tx_ring *txq = &sc->txq[qid];
8557 
8558 		/* Set physical address of TX ring (256-byte aligned). */
8559 		IWN_WRITE(sc, IWN_FH_CBBC_QUEUE(qid),
8560 		    txq->desc_dma.paddr >> 8);
8561 	}
8562 	iwn_nic_unlock(sc);
8563 
8564 	/* Enable DMA channels. */
8565 	for (chnl = 0; chnl < sc->ndmachnls; chnl++) {
8566 		IWN_WRITE(sc, IWN_FH_TX_CONFIG(chnl),
8567 		    IWN_FH_TX_CONFIG_DMA_ENA |
8568 		    IWN_FH_TX_CONFIG_DMA_CREDIT_ENA);
8569 	}
8570 
8571 	/* Clear "radio off" and "commands blocked" bits. */
8572 	IWN_WRITE(sc, IWN_UCODE_GP1_CLR, IWN_UCODE_GP1_RFKILL);
8573 	IWN_WRITE(sc, IWN_UCODE_GP1_CLR, IWN_UCODE_GP1_CMD_BLOCKED);
8574 
8575 	/* Clear pending interrupts. */
8576 	IWN_WRITE(sc, IWN_INT, 0xffffffff);
8577 	/* Enable interrupt coalescing. */
8578 	IWN_WRITE(sc, IWN_INT_COALESCING, 512 / 8);
8579 	/* Enable interrupts. */
8580 	IWN_WRITE(sc, IWN_INT_MASK, sc->int_mask);
8581 
8582 	/* _Really_ make sure "radio off" bit is cleared! */
8583 	IWN_WRITE(sc, IWN_UCODE_GP1_CLR, IWN_UCODE_GP1_RFKILL);
8584 	IWN_WRITE(sc, IWN_UCODE_GP1_CLR, IWN_UCODE_GP1_RFKILL);
8585 
8586 	/* Enable shadow registers. */
8587 	if (sc->base_params->shadow_reg_enable)
8588 		IWN_SETBITS(sc, IWN_SHADOW_REG_CTRL, 0x800fffff);
8589 
8590 	if ((error = ops->load_firmware(sc)) != 0) {
8591 		device_printf(sc->sc_dev,
8592 		    "%s: could not load firmware, error %d\n", __func__,
8593 		    error);
8594 		return error;
8595 	}
8596 	/* Wait at most one second for firmware alive notification. */
8597 	if ((error = msleep(sc, &sc->sc_mtx, PCATCH, "iwninit", hz)) != 0) {
8598 		device_printf(sc->sc_dev,
8599 		    "%s: timeout waiting for adapter to initialize, error %d\n",
8600 		    __func__, error);
8601 		return error;
8602 	}
8603 	/* Do post-firmware initialization. */
8604 
8605 	DPRINTF(sc, IWN_DEBUG_TRACE, "->%s: end\n",__func__);
8606 
8607 	return ops->post_alive(sc);
8608 }
8609 
8610 static void
8611 iwn_hw_stop(struct iwn_softc *sc)
8612 {
8613 	int chnl, qid, ntries;
8614 
8615 	DPRINTF(sc, IWN_DEBUG_TRACE, "->Doing %s\n", __func__);
8616 
8617 	IWN_WRITE(sc, IWN_RESET, IWN_RESET_NEVO);
8618 
8619 	/* Disable interrupts. */
8620 	IWN_WRITE(sc, IWN_INT_MASK, 0);
8621 	IWN_WRITE(sc, IWN_INT, 0xffffffff);
8622 	IWN_WRITE(sc, IWN_FH_INT, 0xffffffff);
8623 	sc->sc_flags &= ~IWN_FLAG_USE_ICT;
8624 
8625 	/* Make sure we no longer hold the NIC lock. */
8626 	iwn_nic_unlock(sc);
8627 
8628 	/* Stop TX scheduler. */
8629 	iwn_prph_write(sc, sc->sched_txfact_addr, 0);
8630 
8631 	/* Stop all DMA channels. */
8632 	if (iwn_nic_lock(sc) == 0) {
8633 		for (chnl = 0; chnl < sc->ndmachnls; chnl++) {
8634 			IWN_WRITE(sc, IWN_FH_TX_CONFIG(chnl), 0);
8635 			for (ntries = 0; ntries < 200; ntries++) {
8636 				if (IWN_READ(sc, IWN_FH_TX_STATUS) &
8637 				    IWN_FH_TX_STATUS_IDLE(chnl))
8638 					break;
8639 				DELAY(10);
8640 			}
8641 		}
8642 		iwn_nic_unlock(sc);
8643 	}
8644 
8645 	/* Stop RX ring. */
8646 	iwn_reset_rx_ring(sc, &sc->rxq);
8647 
8648 	/* Reset all TX rings. */
8649 	for (qid = 0; qid < sc->ntxqs; qid++)
8650 		iwn_reset_tx_ring(sc, &sc->txq[qid]);
8651 
8652 	if (iwn_nic_lock(sc) == 0) {
8653 		iwn_prph_write(sc, IWN_APMG_CLK_DIS,
8654 		    IWN_APMG_CLK_CTRL_DMA_CLK_RQT);
8655 		iwn_nic_unlock(sc);
8656 	}
8657 	DELAY(5);
8658 	/* Power OFF adapter. */
8659 	iwn_apm_stop(sc);
8660 }
8661 
8662 static void
8663 iwn_radio_on(void *arg0, int pending)
8664 {
8665 	struct iwn_softc *sc = arg0;
8666 	struct ifnet *ifp = sc->sc_ifp;
8667 	struct ieee80211com *ic = ifp->if_l2com;
8668 	struct ieee80211vap *vap = TAILQ_FIRST(&ic->ic_vaps);
8669 
8670 	DPRINTF(sc, IWN_DEBUG_TRACE, "->Doing %s\n", __func__);
8671 
8672 	if (vap != NULL) {
8673 		iwn_init(sc);
8674 		ieee80211_init(vap);
8675 	}
8676 }
8677 
8678 static void
8679 iwn_radio_off(void *arg0, int pending)
8680 {
8681 	struct iwn_softc *sc = arg0;
8682 	struct ifnet *ifp = sc->sc_ifp;
8683 	struct ieee80211com *ic = ifp->if_l2com;
8684 	struct ieee80211vap *vap = TAILQ_FIRST(&ic->ic_vaps);
8685 
8686 	DPRINTF(sc, IWN_DEBUG_TRACE, "->Doing %s\n", __func__);
8687 
8688 	iwn_stop(sc);
8689 	if (vap != NULL)
8690 		ieee80211_stop(vap);
8691 
8692 	/* Enable interrupts to get RF toggle notification. */
8693 	IWN_LOCK(sc);
8694 	IWN_WRITE(sc, IWN_INT, 0xffffffff);
8695 	IWN_WRITE(sc, IWN_INT_MASK, sc->int_mask);
8696 	IWN_UNLOCK(sc);
8697 }
8698 
8699 static void
8700 iwn_panicked(void *arg0, int pending)
8701 {
8702 	struct iwn_softc *sc = arg0;
8703 	struct ifnet *ifp = sc->sc_ifp;
8704 	struct ieee80211com *ic = ifp->if_l2com;
8705 	struct ieee80211vap *vap = TAILQ_FIRST(&ic->ic_vaps);
8706 	int error;
8707 
8708 	if (vap == NULL) {
8709 		printf("%s: null vap\n", __func__);
8710 		return;
8711 	}
8712 
8713 	device_printf(sc->sc_dev, "%s: controller panicked, iv_state = %d; "
8714 	    "resetting...\n", __func__, vap->iv_state);
8715 
8716 	IWN_LOCK(sc);
8717 
8718 	iwn_stop_locked(sc);
8719 	iwn_init_locked(sc);
8720 	if (vap->iv_state >= IEEE80211_S_AUTH &&
8721 	    (error = iwn_auth(sc, vap)) != 0) {
8722 		device_printf(sc->sc_dev,
8723 		    "%s: could not move to auth state\n", __func__);
8724 	}
8725 	if (vap->iv_state >= IEEE80211_S_RUN &&
8726 	    (error = iwn_run(sc, vap)) != 0) {
8727 		device_printf(sc->sc_dev,
8728 		    "%s: could not move to run state\n", __func__);
8729 	}
8730 
8731 	/* Only run start once the NIC is in a useful state, like associated */
8732 	iwn_start_locked(sc->sc_ifp);
8733 
8734 	IWN_UNLOCK(sc);
8735 }
8736 
8737 static void
8738 iwn_init_locked(struct iwn_softc *sc)
8739 {
8740 	struct ifnet *ifp = sc->sc_ifp;
8741 	int error;
8742 
8743 	DPRINTF(sc, IWN_DEBUG_TRACE, "->%s begin\n", __func__);
8744 
8745 	IWN_LOCK_ASSERT(sc);
8746 
8747 	if ((error = iwn_hw_prepare(sc)) != 0) {
8748 		device_printf(sc->sc_dev, "%s: hardware not ready, error %d\n",
8749 		    __func__, error);
8750 		goto fail;
8751 	}
8752 
8753 	/* Initialize interrupt mask to default value. */
8754 	sc->int_mask = IWN_INT_MASK_DEF;
8755 	sc->sc_flags &= ~IWN_FLAG_USE_ICT;
8756 
8757 	/* Check that the radio is not disabled by hardware switch. */
8758 	if (!(IWN_READ(sc, IWN_GP_CNTRL) & IWN_GP_CNTRL_RFKILL)) {
8759 		device_printf(sc->sc_dev,
8760 		    "radio is disabled by hardware switch\n");
8761 		/* Enable interrupts to get RF toggle notifications. */
8762 		IWN_WRITE(sc, IWN_INT, 0xffffffff);
8763 		IWN_WRITE(sc, IWN_INT_MASK, sc->int_mask);
8764 		return;
8765 	}
8766 
8767 	/* Read firmware images from the filesystem. */
8768 	if ((error = iwn_read_firmware(sc)) != 0) {
8769 		device_printf(sc->sc_dev,
8770 		    "%s: could not read firmware, error %d\n", __func__,
8771 		    error);
8772 		goto fail;
8773 	}
8774 
8775 	/* Initialize hardware and upload firmware. */
8776 	error = iwn_hw_init(sc);
8777 	firmware_put(sc->fw_fp, FIRMWARE_UNLOAD);
8778 	sc->fw_fp = NULL;
8779 	if (error != 0) {
8780 		device_printf(sc->sc_dev,
8781 		    "%s: could not initialize hardware, error %d\n", __func__,
8782 		    error);
8783 		goto fail;
8784 	}
8785 
8786 	/* Configure adapter now that it is ready. */
8787 	if ((error = iwn_config(sc)) != 0) {
8788 		device_printf(sc->sc_dev,
8789 		    "%s: could not configure device, error %d\n", __func__,
8790 		    error);
8791 		goto fail;
8792 	}
8793 
8794 	ifp->if_drv_flags &= ~IFF_DRV_OACTIVE;
8795 	ifp->if_drv_flags |= IFF_DRV_RUNNING;
8796 
8797 	callout_reset(&sc->watchdog_to, hz, iwn_watchdog, sc);
8798 
8799 	DPRINTF(sc, IWN_DEBUG_TRACE, "->%s: end\n",__func__);
8800 
8801 	return;
8802 
8803 fail:	iwn_stop_locked(sc);
8804 	DPRINTF(sc, IWN_DEBUG_TRACE, "->%s: end in error\n",__func__);
8805 }
8806 
8807 static void
8808 iwn_init(void *arg)
8809 {
8810 	struct iwn_softc *sc = arg;
8811 	struct ifnet *ifp = sc->sc_ifp;
8812 	struct ieee80211com *ic = ifp->if_l2com;
8813 
8814 	IWN_LOCK(sc);
8815 	iwn_init_locked(sc);
8816 	IWN_UNLOCK(sc);
8817 
8818 	if (ifp->if_drv_flags & IFF_DRV_RUNNING)
8819 		ieee80211_start_all(ic);
8820 }
8821 
8822 static void
8823 iwn_stop_locked(struct iwn_softc *sc)
8824 {
8825 	struct ifnet *ifp = sc->sc_ifp;
8826 
8827 	IWN_LOCK_ASSERT(sc);
8828 
8829 	sc->sc_is_scanning = 0;
8830 	sc->sc_tx_timer = 0;
8831 	callout_stop(&sc->watchdog_to);
8832 	callout_stop(&sc->calib_to);
8833 	ifp->if_drv_flags &= ~(IFF_DRV_RUNNING | IFF_DRV_OACTIVE);
8834 
8835 	/* Power OFF hardware. */
8836 	iwn_hw_stop(sc);
8837 }
8838 
8839 static void
8840 iwn_stop(struct iwn_softc *sc)
8841 {
8842 	IWN_LOCK(sc);
8843 	iwn_stop_locked(sc);
8844 	IWN_UNLOCK(sc);
8845 }
8846 
8847 /*
8848  * Callback from net80211 to start a scan.
8849  */
8850 static void
8851 iwn_scan_start(struct ieee80211com *ic)
8852 {
8853 	struct ifnet *ifp = ic->ic_ifp;
8854 	struct iwn_softc *sc = ifp->if_softc;
8855 
8856 	IWN_LOCK(sc);
8857 	/* make the link LED blink while we're scanning */
8858 	iwn_set_led(sc, IWN_LED_LINK, 20, 2);
8859 	IWN_UNLOCK(sc);
8860 }
8861 
8862 /*
8863  * Callback from net80211 to terminate a scan.
8864  */
8865 static void
8866 iwn_scan_end(struct ieee80211com *ic)
8867 {
8868 	struct ifnet *ifp = ic->ic_ifp;
8869 	struct iwn_softc *sc = ifp->if_softc;
8870 	struct ieee80211vap *vap = TAILQ_FIRST(&ic->ic_vaps);
8871 
8872 	IWN_LOCK(sc);
8873 	if (vap->iv_state == IEEE80211_S_RUN) {
8874 		/* Set link LED to ON status if we are associated */
8875 		iwn_set_led(sc, IWN_LED_LINK, 0, 1);
8876 	}
8877 	IWN_UNLOCK(sc);
8878 }
8879 
8880 /*
8881  * Callback from net80211 to force a channel change.
8882  */
8883 static void
8884 iwn_set_channel(struct ieee80211com *ic)
8885 {
8886 	const struct ieee80211_channel *c = ic->ic_curchan;
8887 	struct ifnet *ifp = ic->ic_ifp;
8888 	struct iwn_softc *sc = ifp->if_softc;
8889 	int error;
8890 
8891 	DPRINTF(sc, IWN_DEBUG_TRACE, "->Doing %s\n", __func__);
8892 
8893 	IWN_LOCK(sc);
8894 	sc->sc_rxtap.wr_chan_freq = htole16(c->ic_freq);
8895 	sc->sc_rxtap.wr_chan_flags = htole16(c->ic_flags);
8896 	sc->sc_txtap.wt_chan_freq = htole16(c->ic_freq);
8897 	sc->sc_txtap.wt_chan_flags = htole16(c->ic_flags);
8898 
8899 	/*
8900 	 * Only need to set the channel in Monitor mode. AP scanning and auth
8901 	 * are already taken care of by their respective firmware commands.
8902 	 */
8903 	if (ic->ic_opmode == IEEE80211_M_MONITOR) {
8904 		error = iwn_config(sc);
8905 		if (error != 0)
8906 		device_printf(sc->sc_dev,
8907 		    "%s: error %d settting channel\n", __func__, error);
8908 	}
8909 	IWN_UNLOCK(sc);
8910 }
8911 
8912 /*
8913  * Callback from net80211 to start scanning of the current channel.
8914  */
8915 static void
8916 iwn_scan_curchan(struct ieee80211_scan_state *ss, unsigned long maxdwell)
8917 {
8918 	struct ieee80211vap *vap = ss->ss_vap;
8919 	struct ieee80211com *ic = vap->iv_ic;
8920 	struct iwn_softc *sc = ic->ic_softc;
8921 	int error;
8922 
8923 	IWN_LOCK(sc);
8924 	error = iwn_scan(sc, vap, ss, ic->ic_curchan);
8925 	IWN_UNLOCK(sc);
8926 	if (error != 0)
8927 		ieee80211_cancel_scan(vap);
8928 }
8929 
8930 /*
8931  * Callback from net80211 to handle the minimum dwell time being met.
8932  * The intent is to terminate the scan but we just let the firmware
8933  * notify us when it's finished as we have no safe way to abort it.
8934  */
8935 static void
8936 iwn_scan_mindwell(struct ieee80211_scan_state *ss)
8937 {
8938 	/* NB: don't try to abort scan; wait for firmware to finish */
8939 }
8940 
8941 static void
8942 iwn_hw_reset(void *arg0, int pending)
8943 {
8944 	struct iwn_softc *sc = arg0;
8945 	struct ifnet *ifp = sc->sc_ifp;
8946 	struct ieee80211com *ic = ifp->if_l2com;
8947 
8948 	DPRINTF(sc, IWN_DEBUG_TRACE, "->Doing %s\n", __func__);
8949 
8950 	iwn_stop(sc);
8951 	iwn_init(sc);
8952 	ieee80211_notify_radio(ic, 1);
8953 }
8954 #ifdef	IWN_DEBUG
8955 #define	IWN_DESC(x) case x:	return #x
8956 
8957 /*
8958  * Translate CSR code to string
8959  */
8960 static char *iwn_get_csr_string(int csr)
8961 {
8962 	switch (csr) {
8963 		IWN_DESC(IWN_HW_IF_CONFIG);
8964 		IWN_DESC(IWN_INT_COALESCING);
8965 		IWN_DESC(IWN_INT);
8966 		IWN_DESC(IWN_INT_MASK);
8967 		IWN_DESC(IWN_FH_INT);
8968 		IWN_DESC(IWN_GPIO_IN);
8969 		IWN_DESC(IWN_RESET);
8970 		IWN_DESC(IWN_GP_CNTRL);
8971 		IWN_DESC(IWN_HW_REV);
8972 		IWN_DESC(IWN_EEPROM);
8973 		IWN_DESC(IWN_EEPROM_GP);
8974 		IWN_DESC(IWN_OTP_GP);
8975 		IWN_DESC(IWN_GIO);
8976 		IWN_DESC(IWN_GP_UCODE);
8977 		IWN_DESC(IWN_GP_DRIVER);
8978 		IWN_DESC(IWN_UCODE_GP1);
8979 		IWN_DESC(IWN_UCODE_GP2);
8980 		IWN_DESC(IWN_LED);
8981 		IWN_DESC(IWN_DRAM_INT_TBL);
8982 		IWN_DESC(IWN_GIO_CHICKEN);
8983 		IWN_DESC(IWN_ANA_PLL);
8984 		IWN_DESC(IWN_HW_REV_WA);
8985 		IWN_DESC(IWN_DBG_HPET_MEM);
8986 	default:
8987 		return "UNKNOWN CSR";
8988 	}
8989 }
8990 
8991 /*
8992  * This function print firmware register
8993  */
8994 static void
8995 iwn_debug_register(struct iwn_softc *sc)
8996 {
8997 	int i;
8998 	static const uint32_t csr_tbl[] = {
8999 		IWN_HW_IF_CONFIG,
9000 		IWN_INT_COALESCING,
9001 		IWN_INT,
9002 		IWN_INT_MASK,
9003 		IWN_FH_INT,
9004 		IWN_GPIO_IN,
9005 		IWN_RESET,
9006 		IWN_GP_CNTRL,
9007 		IWN_HW_REV,
9008 		IWN_EEPROM,
9009 		IWN_EEPROM_GP,
9010 		IWN_OTP_GP,
9011 		IWN_GIO,
9012 		IWN_GP_UCODE,
9013 		IWN_GP_DRIVER,
9014 		IWN_UCODE_GP1,
9015 		IWN_UCODE_GP2,
9016 		IWN_LED,
9017 		IWN_DRAM_INT_TBL,
9018 		IWN_GIO_CHICKEN,
9019 		IWN_ANA_PLL,
9020 		IWN_HW_REV_WA,
9021 		IWN_DBG_HPET_MEM,
9022 	};
9023 	DPRINTF(sc, IWN_DEBUG_REGISTER,
9024 	    "CSR values: (2nd byte of IWN_INT_COALESCING is IWN_INT_PERIODIC)%s",
9025 	    "\n");
9026 	for (i = 0; i <  nitems(csr_tbl); i++){
9027 		DPRINTF(sc, IWN_DEBUG_REGISTER,"  %10s: 0x%08x ",
9028 			iwn_get_csr_string(csr_tbl[i]), IWN_READ(sc, csr_tbl[i]));
9029 		if ((i+1) % 3 == 0)
9030 			DPRINTF(sc, IWN_DEBUG_REGISTER,"%s","\n");
9031 	}
9032 	DPRINTF(sc, IWN_DEBUG_REGISTER,"%s","\n");
9033 }
9034 #endif
9035