1 /*- 2 * Copyright (c) 2007-2009 Damien Bergamini <damien.bergamini@free.fr> 3 * Copyright (c) 2008 Benjamin Close <benjsc@FreeBSD.org> 4 * Copyright (c) 2008 Sam Leffler, Errno Consulting 5 * Copyright (c) 2011 Intel Corporation 6 * Copyright (c) 2013 Cedric GROSS <c.gross@kreiz-it.fr> 7 * Copyright (c) 2013 Adrian Chadd <adrian@FreeBSD.org> 8 * 9 * Permission to use, copy, modify, and distribute this software for any 10 * purpose with or without fee is hereby granted, provided that the above 11 * copyright notice and this permission notice appear in all copies. 12 * 13 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 14 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 15 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR 16 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 17 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN 18 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF 19 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 20 */ 21 22 /* 23 * Driver for Intel WiFi Link 4965 and 1000/5000/6000 Series 802.11 network 24 * adapters. 25 */ 26 27 #include <sys/cdefs.h> 28 __FBSDID("$FreeBSD$"); 29 30 #include "opt_wlan.h" 31 #include "opt_iwn.h" 32 33 #include <sys/param.h> 34 #include <sys/sockio.h> 35 #include <sys/sysctl.h> 36 #include <sys/mbuf.h> 37 #include <sys/kernel.h> 38 #include <sys/socket.h> 39 #include <sys/systm.h> 40 #include <sys/malloc.h> 41 #include <sys/bus.h> 42 #include <sys/conf.h> 43 #include <sys/rman.h> 44 #include <sys/endian.h> 45 #include <sys/firmware.h> 46 #include <sys/limits.h> 47 #include <sys/module.h> 48 #include <sys/priv.h> 49 #include <sys/queue.h> 50 #include <sys/taskqueue.h> 51 52 #include <machine/bus.h> 53 #include <machine/resource.h> 54 #include <machine/clock.h> 55 56 #include <dev/pci/pcireg.h> 57 #include <dev/pci/pcivar.h> 58 59 #include <net/if.h> 60 #include <net/if_var.h> 61 #include <net/if_dl.h> 62 #include <net/if_media.h> 63 64 #include <netinet/in.h> 65 #include <netinet/if_ether.h> 66 67 #include <net80211/ieee80211_var.h> 68 #include <net80211/ieee80211_radiotap.h> 69 #include <net80211/ieee80211_regdomain.h> 70 #include <net80211/ieee80211_ratectl.h> 71 72 #include <dev/iwn/if_iwnreg.h> 73 #include <dev/iwn/if_iwnvar.h> 74 #include <dev/iwn/if_iwn_devid.h> 75 #include <dev/iwn/if_iwn_chip_cfg.h> 76 #include <dev/iwn/if_iwn_debug.h> 77 #include <dev/iwn/if_iwn_ioctl.h> 78 79 struct iwn_ident { 80 uint16_t vendor; 81 uint16_t device; 82 const char *name; 83 }; 84 85 static const struct iwn_ident iwn_ident_table[] = { 86 { 0x8086, IWN_DID_6x05_1, "Intel Centrino Advanced-N 6205" }, 87 { 0x8086, IWN_DID_1000_1, "Intel Centrino Wireless-N 1000" }, 88 { 0x8086, IWN_DID_1000_2, "Intel Centrino Wireless-N 1000" }, 89 { 0x8086, IWN_DID_6x05_2, "Intel Centrino Advanced-N 6205" }, 90 { 0x8086, IWN_DID_6050_1, "Intel Centrino Advanced-N + WiMAX 6250" }, 91 { 0x8086, IWN_DID_6050_2, "Intel Centrino Advanced-N + WiMAX 6250" }, 92 { 0x8086, IWN_DID_x030_1, "Intel Centrino Wireless-N 1030" }, 93 { 0x8086, IWN_DID_x030_2, "Intel Centrino Wireless-N 1030" }, 94 { 0x8086, IWN_DID_x030_3, "Intel Centrino Advanced-N 6230" }, 95 { 0x8086, IWN_DID_x030_4, "Intel Centrino Advanced-N 6230" }, 96 { 0x8086, IWN_DID_6150_1, "Intel Centrino Wireless-N + WiMAX 6150" }, 97 { 0x8086, IWN_DID_6150_2, "Intel Centrino Wireless-N + WiMAX 6150" }, 98 { 0x8086, IWN_DID_2x00_1, "Intel(R) Centrino(R) Wireless-N 2200 BGN" }, 99 { 0x8086, IWN_DID_2x00_2, "Intel(R) Centrino(R) Wireless-N 2200 BGN" }, 100 /* XXX 2200D is IWN_SDID_2x00_4; there's no way to express this here! */ 101 { 0x8086, IWN_DID_2x30_1, "Intel Centrino Wireless-N 2230" }, 102 { 0x8086, IWN_DID_2x30_2, "Intel Centrino Wireless-N 2230" }, 103 { 0x8086, IWN_DID_130_1, "Intel Centrino Wireless-N 130" }, 104 { 0x8086, IWN_DID_130_2, "Intel Centrino Wireless-N 130" }, 105 { 0x8086, IWN_DID_100_1, "Intel Centrino Wireless-N 100" }, 106 { 0x8086, IWN_DID_100_2, "Intel Centrino Wireless-N 100" }, 107 { 0x8086, IWN_DID_105_1, "Intel Centrino Wireless-N 105" }, 108 { 0x8086, IWN_DID_105_2, "Intel Centrino Wireless-N 105" }, 109 { 0x8086, IWN_DID_135_1, "Intel Centrino Wireless-N 135" }, 110 { 0x8086, IWN_DID_135_2, "Intel Centrino Wireless-N 135" }, 111 { 0x8086, IWN_DID_4965_1, "Intel Wireless WiFi Link 4965" }, 112 { 0x8086, IWN_DID_6x00_1, "Intel Centrino Ultimate-N 6300" }, 113 { 0x8086, IWN_DID_6x00_2, "Intel Centrino Advanced-N 6200" }, 114 { 0x8086, IWN_DID_4965_2, "Intel Wireless WiFi Link 4965" }, 115 { 0x8086, IWN_DID_4965_3, "Intel Wireless WiFi Link 4965" }, 116 { 0x8086, IWN_DID_5x00_1, "Intel WiFi Link 5100" }, 117 { 0x8086, IWN_DID_4965_4, "Intel Wireless WiFi Link 4965" }, 118 { 0x8086, IWN_DID_5x00_3, "Intel Ultimate N WiFi Link 5300" }, 119 { 0x8086, IWN_DID_5x00_4, "Intel Ultimate N WiFi Link 5300" }, 120 { 0x8086, IWN_DID_5x00_2, "Intel WiFi Link 5100" }, 121 { 0x8086, IWN_DID_6x00_3, "Intel Centrino Ultimate-N 6300" }, 122 { 0x8086, IWN_DID_6x00_4, "Intel Centrino Advanced-N 6200" }, 123 { 0x8086, IWN_DID_5x50_1, "Intel WiMAX/WiFi Link 5350" }, 124 { 0x8086, IWN_DID_5x50_2, "Intel WiMAX/WiFi Link 5350" }, 125 { 0x8086, IWN_DID_5x50_3, "Intel WiMAX/WiFi Link 5150" }, 126 { 0x8086, IWN_DID_5x50_4, "Intel WiMAX/WiFi Link 5150" }, 127 { 0x8086, IWN_DID_6035_1, "Intel Centrino Advanced 6235" }, 128 { 0x8086, IWN_DID_6035_2, "Intel Centrino Advanced 6235" }, 129 { 0, 0, NULL } 130 }; 131 132 static int iwn_probe(device_t); 133 static int iwn_attach(device_t); 134 static void iwn4965_attach(struct iwn_softc *, uint16_t); 135 static void iwn5000_attach(struct iwn_softc *, uint16_t); 136 static int iwn_config_specific(struct iwn_softc *, uint16_t); 137 static void iwn_radiotap_attach(struct iwn_softc *); 138 static void iwn_sysctlattach(struct iwn_softc *); 139 static struct ieee80211vap *iwn_vap_create(struct ieee80211com *, 140 const char [IFNAMSIZ], int, enum ieee80211_opmode, int, 141 const uint8_t [IEEE80211_ADDR_LEN], 142 const uint8_t [IEEE80211_ADDR_LEN]); 143 static void iwn_vap_delete(struct ieee80211vap *); 144 static int iwn_detach(device_t); 145 static int iwn_shutdown(device_t); 146 static int iwn_suspend(device_t); 147 static int iwn_resume(device_t); 148 static int iwn_nic_lock(struct iwn_softc *); 149 static int iwn_eeprom_lock(struct iwn_softc *); 150 static int iwn_init_otprom(struct iwn_softc *); 151 static int iwn_read_prom_data(struct iwn_softc *, uint32_t, void *, int); 152 static void iwn_dma_map_addr(void *, bus_dma_segment_t *, int, int); 153 static int iwn_dma_contig_alloc(struct iwn_softc *, struct iwn_dma_info *, 154 void **, bus_size_t, bus_size_t); 155 static void iwn_dma_contig_free(struct iwn_dma_info *); 156 static int iwn_alloc_sched(struct iwn_softc *); 157 static void iwn_free_sched(struct iwn_softc *); 158 static int iwn_alloc_kw(struct iwn_softc *); 159 static void iwn_free_kw(struct iwn_softc *); 160 static int iwn_alloc_ict(struct iwn_softc *); 161 static void iwn_free_ict(struct iwn_softc *); 162 static int iwn_alloc_fwmem(struct iwn_softc *); 163 static void iwn_free_fwmem(struct iwn_softc *); 164 static int iwn_alloc_rx_ring(struct iwn_softc *, struct iwn_rx_ring *); 165 static void iwn_reset_rx_ring(struct iwn_softc *, struct iwn_rx_ring *); 166 static void iwn_free_rx_ring(struct iwn_softc *, struct iwn_rx_ring *); 167 static int iwn_alloc_tx_ring(struct iwn_softc *, struct iwn_tx_ring *, 168 int); 169 static void iwn_reset_tx_ring(struct iwn_softc *, struct iwn_tx_ring *); 170 static void iwn_free_tx_ring(struct iwn_softc *, struct iwn_tx_ring *); 171 static void iwn_check_tx_ring(struct iwn_softc *, int); 172 static void iwn5000_ict_reset(struct iwn_softc *); 173 static int iwn_read_eeprom(struct iwn_softc *, 174 uint8_t macaddr[IEEE80211_ADDR_LEN]); 175 static void iwn4965_read_eeprom(struct iwn_softc *); 176 #ifdef IWN_DEBUG 177 static void iwn4965_print_power_group(struct iwn_softc *, int); 178 #endif 179 static void iwn5000_read_eeprom(struct iwn_softc *); 180 static uint32_t iwn_eeprom_channel_flags(struct iwn_eeprom_chan *); 181 static void iwn_read_eeprom_band(struct iwn_softc *, int, int, int *, 182 struct ieee80211_channel[]); 183 static void iwn_read_eeprom_ht40(struct iwn_softc *, int, int, int *, 184 struct ieee80211_channel[]); 185 static void iwn_read_eeprom_channels(struct iwn_softc *, int, uint32_t); 186 static struct iwn_eeprom_chan *iwn_find_eeprom_channel(struct iwn_softc *, 187 struct ieee80211_channel *); 188 static void iwn_getradiocaps(struct ieee80211com *, int, int *, 189 struct ieee80211_channel[]); 190 static int iwn_setregdomain(struct ieee80211com *, 191 struct ieee80211_regdomain *, int, 192 struct ieee80211_channel[]); 193 static void iwn_read_eeprom_enhinfo(struct iwn_softc *); 194 static struct ieee80211_node *iwn_node_alloc(struct ieee80211vap *, 195 const uint8_t mac[IEEE80211_ADDR_LEN]); 196 static void iwn_newassoc(struct ieee80211_node *, int); 197 static int iwn_media_change(struct ifnet *); 198 static int iwn_newstate(struct ieee80211vap *, enum ieee80211_state, int); 199 static void iwn_calib_timeout(void *); 200 static void iwn_rx_phy(struct iwn_softc *, struct iwn_rx_desc *); 201 static void iwn_rx_done(struct iwn_softc *, struct iwn_rx_desc *, 202 struct iwn_rx_data *); 203 static void iwn_agg_tx_complete(struct iwn_softc *, struct iwn_tx_ring *, 204 int, int, int); 205 static void iwn_rx_compressed_ba(struct iwn_softc *, struct iwn_rx_desc *); 206 static void iwn5000_rx_calib_results(struct iwn_softc *, 207 struct iwn_rx_desc *); 208 static void iwn_rx_statistics(struct iwn_softc *, struct iwn_rx_desc *); 209 static void iwn4965_tx_done(struct iwn_softc *, struct iwn_rx_desc *, 210 struct iwn_rx_data *); 211 static void iwn5000_tx_done(struct iwn_softc *, struct iwn_rx_desc *, 212 struct iwn_rx_data *); 213 static void iwn_adj_ampdu_ptr(struct iwn_softc *, struct iwn_tx_ring *); 214 static void iwn_tx_done(struct iwn_softc *, struct iwn_rx_desc *, int, int, 215 uint8_t); 216 static int iwn_ampdu_check_bitmap(uint64_t, int, int); 217 static int iwn_ampdu_index_check(struct iwn_softc *, struct iwn_tx_ring *, 218 uint64_t, int, int); 219 static void iwn_ampdu_tx_done(struct iwn_softc *, int, int, int, void *); 220 static void iwn_cmd_done(struct iwn_softc *, struct iwn_rx_desc *); 221 static void iwn_notif_intr(struct iwn_softc *); 222 static void iwn_wakeup_intr(struct iwn_softc *); 223 static void iwn_rftoggle_task(void *, int); 224 static void iwn_fatal_intr(struct iwn_softc *); 225 static void iwn_intr(void *); 226 static void iwn4965_update_sched(struct iwn_softc *, int, int, uint8_t, 227 uint16_t); 228 static void iwn5000_update_sched(struct iwn_softc *, int, int, uint8_t, 229 uint16_t); 230 #ifdef notyet 231 static void iwn5000_reset_sched(struct iwn_softc *, int, int); 232 #endif 233 static int iwn_tx_data(struct iwn_softc *, struct mbuf *, 234 struct ieee80211_node *); 235 static int iwn_tx_data_raw(struct iwn_softc *, struct mbuf *, 236 struct ieee80211_node *, 237 const struct ieee80211_bpf_params *params); 238 static int iwn_tx_cmd(struct iwn_softc *, struct mbuf *, 239 struct ieee80211_node *, struct iwn_tx_ring *); 240 static void iwn_xmit_task(void *arg0, int pending); 241 static int iwn_raw_xmit(struct ieee80211_node *, struct mbuf *, 242 const struct ieee80211_bpf_params *); 243 static int iwn_transmit(struct ieee80211com *, struct mbuf *); 244 static void iwn_scan_timeout(void *); 245 static void iwn_watchdog(void *); 246 static int iwn_ioctl(struct ieee80211com *, u_long , void *); 247 static void iwn_parent(struct ieee80211com *); 248 static int iwn_cmd(struct iwn_softc *, int, const void *, int, int); 249 static int iwn4965_add_node(struct iwn_softc *, struct iwn_node_info *, 250 int); 251 static int iwn5000_add_node(struct iwn_softc *, struct iwn_node_info *, 252 int); 253 static int iwn_set_link_quality(struct iwn_softc *, 254 struct ieee80211_node *); 255 static int iwn_add_broadcast_node(struct iwn_softc *, int); 256 static int iwn_updateedca(struct ieee80211com *); 257 static void iwn_set_promisc(struct iwn_softc *); 258 static void iwn_update_promisc(struct ieee80211com *); 259 static void iwn_update_mcast(struct ieee80211com *); 260 static void iwn_set_led(struct iwn_softc *, uint8_t, uint8_t, uint8_t); 261 static int iwn_set_critical_temp(struct iwn_softc *); 262 static int iwn_set_timing(struct iwn_softc *, struct ieee80211_node *); 263 static void iwn4965_power_calibration(struct iwn_softc *, int); 264 static int iwn4965_set_txpower(struct iwn_softc *, int); 265 static int iwn5000_set_txpower(struct iwn_softc *, int); 266 static int iwn4965_get_rssi(struct iwn_softc *, struct iwn_rx_stat *); 267 static int iwn5000_get_rssi(struct iwn_softc *, struct iwn_rx_stat *); 268 static int iwn_get_noise(const struct iwn_rx_general_stats *); 269 static int iwn4965_get_temperature(struct iwn_softc *); 270 static int iwn5000_get_temperature(struct iwn_softc *); 271 static int iwn_init_sensitivity(struct iwn_softc *); 272 static void iwn_collect_noise(struct iwn_softc *, 273 const struct iwn_rx_general_stats *); 274 static int iwn4965_init_gains(struct iwn_softc *); 275 static int iwn5000_init_gains(struct iwn_softc *); 276 static int iwn4965_set_gains(struct iwn_softc *); 277 static int iwn5000_set_gains(struct iwn_softc *); 278 static void iwn_tune_sensitivity(struct iwn_softc *, 279 const struct iwn_rx_stats *); 280 static void iwn_save_stats_counters(struct iwn_softc *, 281 const struct iwn_stats *); 282 static int iwn_send_sensitivity(struct iwn_softc *); 283 static void iwn_check_rx_recovery(struct iwn_softc *, struct iwn_stats *); 284 static int iwn_set_pslevel(struct iwn_softc *, int, int, int); 285 static int iwn_send_btcoex(struct iwn_softc *); 286 static int iwn_send_advanced_btcoex(struct iwn_softc *); 287 static int iwn5000_runtime_calib(struct iwn_softc *); 288 static int iwn_check_bss_filter(struct iwn_softc *); 289 static int iwn4965_rxon_assoc(struct iwn_softc *, int); 290 static int iwn5000_rxon_assoc(struct iwn_softc *, int); 291 static int iwn_send_rxon(struct iwn_softc *, int, int); 292 static int iwn_config(struct iwn_softc *); 293 static int iwn_scan(struct iwn_softc *, struct ieee80211vap *, 294 struct ieee80211_scan_state *, struct ieee80211_channel *); 295 static int iwn_auth(struct iwn_softc *, struct ieee80211vap *vap); 296 static int iwn_run(struct iwn_softc *, struct ieee80211vap *vap); 297 static int iwn_ampdu_rx_start(struct ieee80211_node *, 298 struct ieee80211_rx_ampdu *, int, int, int); 299 static void iwn_ampdu_rx_stop(struct ieee80211_node *, 300 struct ieee80211_rx_ampdu *); 301 static int iwn_addba_request(struct ieee80211_node *, 302 struct ieee80211_tx_ampdu *, int, int, int); 303 static int iwn_addba_response(struct ieee80211_node *, 304 struct ieee80211_tx_ampdu *, int, int, int); 305 static int iwn_ampdu_tx_start(struct ieee80211com *, 306 struct ieee80211_node *, uint8_t); 307 static void iwn_ampdu_tx_stop(struct ieee80211_node *, 308 struct ieee80211_tx_ampdu *); 309 static void iwn4965_ampdu_tx_start(struct iwn_softc *, 310 struct ieee80211_node *, int, uint8_t, uint16_t); 311 static void iwn4965_ampdu_tx_stop(struct iwn_softc *, int, 312 uint8_t, uint16_t); 313 static void iwn5000_ampdu_tx_start(struct iwn_softc *, 314 struct ieee80211_node *, int, uint8_t, uint16_t); 315 static void iwn5000_ampdu_tx_stop(struct iwn_softc *, int, 316 uint8_t, uint16_t); 317 static int iwn5000_query_calibration(struct iwn_softc *); 318 static int iwn5000_send_calibration(struct iwn_softc *); 319 static int iwn5000_send_wimax_coex(struct iwn_softc *); 320 static int iwn5000_crystal_calib(struct iwn_softc *); 321 static int iwn5000_temp_offset_calib(struct iwn_softc *); 322 static int iwn5000_temp_offset_calibv2(struct iwn_softc *); 323 static int iwn4965_post_alive(struct iwn_softc *); 324 static int iwn5000_post_alive(struct iwn_softc *); 325 static int iwn4965_load_bootcode(struct iwn_softc *, const uint8_t *, 326 int); 327 static int iwn4965_load_firmware(struct iwn_softc *); 328 static int iwn5000_load_firmware_section(struct iwn_softc *, uint32_t, 329 const uint8_t *, int); 330 static int iwn5000_load_firmware(struct iwn_softc *); 331 static int iwn_read_firmware_leg(struct iwn_softc *, 332 struct iwn_fw_info *); 333 static int iwn_read_firmware_tlv(struct iwn_softc *, 334 struct iwn_fw_info *, uint16_t); 335 static int iwn_read_firmware(struct iwn_softc *); 336 static void iwn_unload_firmware(struct iwn_softc *); 337 static int iwn_clock_wait(struct iwn_softc *); 338 static int iwn_apm_init(struct iwn_softc *); 339 static void iwn_apm_stop_master(struct iwn_softc *); 340 static void iwn_apm_stop(struct iwn_softc *); 341 static int iwn4965_nic_config(struct iwn_softc *); 342 static int iwn5000_nic_config(struct iwn_softc *); 343 static int iwn_hw_prepare(struct iwn_softc *); 344 static int iwn_hw_init(struct iwn_softc *); 345 static void iwn_hw_stop(struct iwn_softc *); 346 static void iwn_panicked(void *, int); 347 static int iwn_init_locked(struct iwn_softc *); 348 static int iwn_init(struct iwn_softc *); 349 static void iwn_stop_locked(struct iwn_softc *); 350 static void iwn_stop(struct iwn_softc *); 351 static void iwn_scan_start(struct ieee80211com *); 352 static void iwn_scan_end(struct ieee80211com *); 353 static void iwn_set_channel(struct ieee80211com *); 354 static void iwn_scan_curchan(struct ieee80211_scan_state *, unsigned long); 355 static void iwn_scan_mindwell(struct ieee80211_scan_state *); 356 #ifdef IWN_DEBUG 357 static char *iwn_get_csr_string(int); 358 static void iwn_debug_register(struct iwn_softc *); 359 #endif 360 361 static device_method_t iwn_methods[] = { 362 /* Device interface */ 363 DEVMETHOD(device_probe, iwn_probe), 364 DEVMETHOD(device_attach, iwn_attach), 365 DEVMETHOD(device_detach, iwn_detach), 366 DEVMETHOD(device_shutdown, iwn_shutdown), 367 DEVMETHOD(device_suspend, iwn_suspend), 368 DEVMETHOD(device_resume, iwn_resume), 369 370 DEVMETHOD_END 371 }; 372 373 static driver_t iwn_driver = { 374 "iwn", 375 iwn_methods, 376 sizeof(struct iwn_softc) 377 }; 378 static devclass_t iwn_devclass; 379 380 DRIVER_MODULE(iwn, pci, iwn_driver, iwn_devclass, NULL, NULL); 381 MODULE_PNP_INFO("U16:vendor;U16:device;D:#", pci, iwn, iwn_ident_table, 382 nitems(iwn_ident_table) - 1); 383 MODULE_VERSION(iwn, 1); 384 385 MODULE_DEPEND(iwn, firmware, 1, 1, 1); 386 MODULE_DEPEND(iwn, pci, 1, 1, 1); 387 MODULE_DEPEND(iwn, wlan, 1, 1, 1); 388 389 static d_ioctl_t iwn_cdev_ioctl; 390 static d_open_t iwn_cdev_open; 391 static d_close_t iwn_cdev_close; 392 393 static struct cdevsw iwn_cdevsw = { 394 .d_version = D_VERSION, 395 .d_flags = 0, 396 .d_open = iwn_cdev_open, 397 .d_close = iwn_cdev_close, 398 .d_ioctl = iwn_cdev_ioctl, 399 .d_name = "iwn", 400 }; 401 402 static int 403 iwn_probe(device_t dev) 404 { 405 const struct iwn_ident *ident; 406 407 for (ident = iwn_ident_table; ident->name != NULL; ident++) { 408 if (pci_get_vendor(dev) == ident->vendor && 409 pci_get_device(dev) == ident->device) { 410 device_set_desc(dev, ident->name); 411 return (BUS_PROBE_DEFAULT); 412 } 413 } 414 return ENXIO; 415 } 416 417 static int 418 iwn_is_3stream_device(struct iwn_softc *sc) 419 { 420 /* XXX for now only 5300, until the 5350 can be tested */ 421 if (sc->hw_type == IWN_HW_REV_TYPE_5300) 422 return (1); 423 return (0); 424 } 425 426 static int 427 iwn_attach(device_t dev) 428 { 429 struct iwn_softc *sc = device_get_softc(dev); 430 struct ieee80211com *ic; 431 int i, error, rid; 432 433 sc->sc_dev = dev; 434 435 #ifdef IWN_DEBUG 436 error = resource_int_value(device_get_name(sc->sc_dev), 437 device_get_unit(sc->sc_dev), "debug", &(sc->sc_debug)); 438 if (error != 0) 439 sc->sc_debug = 0; 440 #else 441 sc->sc_debug = 0; 442 #endif 443 444 DPRINTF(sc, IWN_DEBUG_TRACE, "->%s: begin\n",__func__); 445 446 /* 447 * Get the offset of the PCI Express Capability Structure in PCI 448 * Configuration Space. 449 */ 450 error = pci_find_cap(dev, PCIY_EXPRESS, &sc->sc_cap_off); 451 if (error != 0) { 452 device_printf(dev, "PCIe capability structure not found!\n"); 453 return error; 454 } 455 456 /* Clear device-specific "PCI retry timeout" register (41h). */ 457 pci_write_config(dev, 0x41, 0, 1); 458 459 /* Enable bus-mastering. */ 460 pci_enable_busmaster(dev); 461 462 rid = PCIR_BAR(0); 463 sc->mem = bus_alloc_resource_any(dev, SYS_RES_MEMORY, &rid, 464 RF_ACTIVE); 465 if (sc->mem == NULL) { 466 device_printf(dev, "can't map mem space\n"); 467 error = ENOMEM; 468 return error; 469 } 470 sc->sc_st = rman_get_bustag(sc->mem); 471 sc->sc_sh = rman_get_bushandle(sc->mem); 472 473 i = 1; 474 rid = 0; 475 if (pci_alloc_msi(dev, &i) == 0) 476 rid = 1; 477 /* Install interrupt handler. */ 478 sc->irq = bus_alloc_resource_any(dev, SYS_RES_IRQ, &rid, RF_ACTIVE | 479 (rid != 0 ? 0 : RF_SHAREABLE)); 480 if (sc->irq == NULL) { 481 device_printf(dev, "can't map interrupt\n"); 482 error = ENOMEM; 483 goto fail; 484 } 485 486 IWN_LOCK_INIT(sc); 487 488 /* Read hardware revision and attach. */ 489 sc->hw_type = (IWN_READ(sc, IWN_HW_REV) >> IWN_HW_REV_TYPE_SHIFT) 490 & IWN_HW_REV_TYPE_MASK; 491 sc->subdevice_id = pci_get_subdevice(dev); 492 493 /* 494 * 4965 versus 5000 and later have different methods. 495 * Let's set those up first. 496 */ 497 if (sc->hw_type == IWN_HW_REV_TYPE_4965) 498 iwn4965_attach(sc, pci_get_device(dev)); 499 else 500 iwn5000_attach(sc, pci_get_device(dev)); 501 502 /* 503 * Next, let's setup the various parameters of each NIC. 504 */ 505 error = iwn_config_specific(sc, pci_get_device(dev)); 506 if (error != 0) { 507 device_printf(dev, "could not attach device, error %d\n", 508 error); 509 goto fail; 510 } 511 512 if ((error = iwn_hw_prepare(sc)) != 0) { 513 device_printf(dev, "hardware not ready, error %d\n", error); 514 goto fail; 515 } 516 517 /* Allocate DMA memory for firmware transfers. */ 518 if ((error = iwn_alloc_fwmem(sc)) != 0) { 519 device_printf(dev, 520 "could not allocate memory for firmware, error %d\n", 521 error); 522 goto fail; 523 } 524 525 /* Allocate "Keep Warm" page. */ 526 if ((error = iwn_alloc_kw(sc)) != 0) { 527 device_printf(dev, 528 "could not allocate keep warm page, error %d\n", error); 529 goto fail; 530 } 531 532 /* Allocate ICT table for 5000 Series. */ 533 if (sc->hw_type != IWN_HW_REV_TYPE_4965 && 534 (error = iwn_alloc_ict(sc)) != 0) { 535 device_printf(dev, "could not allocate ICT table, error %d\n", 536 error); 537 goto fail; 538 } 539 540 /* Allocate TX scheduler "rings". */ 541 if ((error = iwn_alloc_sched(sc)) != 0) { 542 device_printf(dev, 543 "could not allocate TX scheduler rings, error %d\n", error); 544 goto fail; 545 } 546 547 /* Allocate TX rings (16 on 4965AGN, 20 on >=5000). */ 548 for (i = 0; i < sc->ntxqs; i++) { 549 if ((error = iwn_alloc_tx_ring(sc, &sc->txq[i], i)) != 0) { 550 device_printf(dev, 551 "could not allocate TX ring %d, error %d\n", i, 552 error); 553 goto fail; 554 } 555 } 556 557 /* Allocate RX ring. */ 558 if ((error = iwn_alloc_rx_ring(sc, &sc->rxq)) != 0) { 559 device_printf(dev, "could not allocate RX ring, error %d\n", 560 error); 561 goto fail; 562 } 563 564 /* Clear pending interrupts. */ 565 IWN_WRITE(sc, IWN_INT, 0xffffffff); 566 567 ic = &sc->sc_ic; 568 ic->ic_softc = sc; 569 ic->ic_name = device_get_nameunit(dev); 570 ic->ic_phytype = IEEE80211_T_OFDM; /* not only, but not used */ 571 ic->ic_opmode = IEEE80211_M_STA; /* default to BSS mode */ 572 573 /* Set device capabilities. */ 574 ic->ic_caps = 575 IEEE80211_C_STA /* station mode supported */ 576 | IEEE80211_C_MONITOR /* monitor mode supported */ 577 #if 0 578 | IEEE80211_C_BGSCAN /* background scanning */ 579 #endif 580 | IEEE80211_C_TXPMGT /* tx power management */ 581 | IEEE80211_C_SHSLOT /* short slot time supported */ 582 | IEEE80211_C_WPA 583 | IEEE80211_C_SHPREAMBLE /* short preamble supported */ 584 #if 0 585 | IEEE80211_C_IBSS /* ibss/adhoc mode */ 586 #endif 587 | IEEE80211_C_WME /* WME */ 588 | IEEE80211_C_PMGT /* Station-side power mgmt */ 589 ; 590 591 /* Read MAC address, channels, etc from EEPROM. */ 592 if ((error = iwn_read_eeprom(sc, ic->ic_macaddr)) != 0) { 593 device_printf(dev, "could not read EEPROM, error %d\n", 594 error); 595 goto fail; 596 } 597 598 /* Count the number of available chains. */ 599 sc->ntxchains = 600 ((sc->txchainmask >> 2) & 1) + 601 ((sc->txchainmask >> 1) & 1) + 602 ((sc->txchainmask >> 0) & 1); 603 sc->nrxchains = 604 ((sc->rxchainmask >> 2) & 1) + 605 ((sc->rxchainmask >> 1) & 1) + 606 ((sc->rxchainmask >> 0) & 1); 607 if (bootverbose) { 608 device_printf(dev, "MIMO %dT%dR, %.4s, address %6D\n", 609 sc->ntxchains, sc->nrxchains, sc->eeprom_domain, 610 ic->ic_macaddr, ":"); 611 } 612 613 if (sc->sc_flags & IWN_FLAG_HAS_11N) { 614 ic->ic_rxstream = sc->nrxchains; 615 ic->ic_txstream = sc->ntxchains; 616 617 /* 618 * Some of the 3 antenna devices (ie, the 4965) only supports 619 * 2x2 operation. So correct the number of streams if 620 * it's not a 3-stream device. 621 */ 622 if (! iwn_is_3stream_device(sc)) { 623 if (ic->ic_rxstream > 2) 624 ic->ic_rxstream = 2; 625 if (ic->ic_txstream > 2) 626 ic->ic_txstream = 2; 627 } 628 629 ic->ic_htcaps = 630 IEEE80211_HTCAP_SMPS_OFF /* SMPS mode disabled */ 631 | IEEE80211_HTCAP_SHORTGI20 /* short GI in 20MHz */ 632 | IEEE80211_HTCAP_CHWIDTH40 /* 40MHz channel width*/ 633 | IEEE80211_HTCAP_SHORTGI40 /* short GI in 40MHz */ 634 #ifdef notyet 635 | IEEE80211_HTCAP_GREENFIELD 636 #if IWN_RBUF_SIZE == 8192 637 | IEEE80211_HTCAP_MAXAMSDU_7935 /* max A-MSDU length */ 638 #else 639 | IEEE80211_HTCAP_MAXAMSDU_3839 /* max A-MSDU length */ 640 #endif 641 #endif 642 /* s/w capabilities */ 643 | IEEE80211_HTC_HT /* HT operation */ 644 | IEEE80211_HTC_AMPDU /* tx A-MPDU */ 645 #ifdef notyet 646 | IEEE80211_HTC_AMSDU /* tx A-MSDU */ 647 #endif 648 ; 649 } 650 651 ieee80211_ifattach(ic); 652 ic->ic_vap_create = iwn_vap_create; 653 ic->ic_ioctl = iwn_ioctl; 654 ic->ic_parent = iwn_parent; 655 ic->ic_vap_delete = iwn_vap_delete; 656 ic->ic_transmit = iwn_transmit; 657 ic->ic_raw_xmit = iwn_raw_xmit; 658 ic->ic_node_alloc = iwn_node_alloc; 659 sc->sc_ampdu_rx_start = ic->ic_ampdu_rx_start; 660 ic->ic_ampdu_rx_start = iwn_ampdu_rx_start; 661 sc->sc_ampdu_rx_stop = ic->ic_ampdu_rx_stop; 662 ic->ic_ampdu_rx_stop = iwn_ampdu_rx_stop; 663 sc->sc_addba_request = ic->ic_addba_request; 664 ic->ic_addba_request = iwn_addba_request; 665 sc->sc_addba_response = ic->ic_addba_response; 666 ic->ic_addba_response = iwn_addba_response; 667 sc->sc_addba_stop = ic->ic_addba_stop; 668 ic->ic_addba_stop = iwn_ampdu_tx_stop; 669 ic->ic_newassoc = iwn_newassoc; 670 ic->ic_wme.wme_update = iwn_updateedca; 671 ic->ic_update_promisc = iwn_update_promisc; 672 ic->ic_update_mcast = iwn_update_mcast; 673 ic->ic_scan_start = iwn_scan_start; 674 ic->ic_scan_end = iwn_scan_end; 675 ic->ic_set_channel = iwn_set_channel; 676 ic->ic_scan_curchan = iwn_scan_curchan; 677 ic->ic_scan_mindwell = iwn_scan_mindwell; 678 ic->ic_getradiocaps = iwn_getradiocaps; 679 ic->ic_setregdomain = iwn_setregdomain; 680 681 iwn_radiotap_attach(sc); 682 683 callout_init_mtx(&sc->calib_to, &sc->sc_mtx, 0); 684 callout_init_mtx(&sc->scan_timeout, &sc->sc_mtx, 0); 685 callout_init_mtx(&sc->watchdog_to, &sc->sc_mtx, 0); 686 TASK_INIT(&sc->sc_rftoggle_task, 0, iwn_rftoggle_task, sc); 687 TASK_INIT(&sc->sc_panic_task, 0, iwn_panicked, sc); 688 TASK_INIT(&sc->sc_xmit_task, 0, iwn_xmit_task, sc); 689 690 mbufq_init(&sc->sc_xmit_queue, 1024); 691 692 sc->sc_tq = taskqueue_create("iwn_taskq", M_WAITOK, 693 taskqueue_thread_enqueue, &sc->sc_tq); 694 error = taskqueue_start_threads(&sc->sc_tq, 1, 0, "iwn_taskq"); 695 if (error != 0) { 696 device_printf(dev, "can't start threads, error %d\n", error); 697 goto fail; 698 } 699 700 iwn_sysctlattach(sc); 701 702 /* 703 * Hook our interrupt after all initialization is complete. 704 */ 705 error = bus_setup_intr(dev, sc->irq, INTR_TYPE_NET | INTR_MPSAFE, 706 NULL, iwn_intr, sc, &sc->sc_ih); 707 if (error != 0) { 708 device_printf(dev, "can't establish interrupt, error %d\n", 709 error); 710 goto fail; 711 } 712 713 #if 0 714 device_printf(sc->sc_dev, "%s: rx_stats=%d, rx_stats_bt=%d\n", 715 __func__, 716 sizeof(struct iwn_stats), 717 sizeof(struct iwn_stats_bt)); 718 #endif 719 720 if (bootverbose) 721 ieee80211_announce(ic); 722 DPRINTF(sc, IWN_DEBUG_TRACE, "->%s: end\n",__func__); 723 724 /* Add debug ioctl right at the end */ 725 sc->sc_cdev = make_dev(&iwn_cdevsw, device_get_unit(dev), 726 UID_ROOT, GID_WHEEL, 0600, "%s", device_get_nameunit(dev)); 727 if (sc->sc_cdev == NULL) { 728 device_printf(dev, "failed to create debug character device\n"); 729 } else { 730 sc->sc_cdev->si_drv1 = sc; 731 } 732 return 0; 733 fail: 734 iwn_detach(dev); 735 DPRINTF(sc, IWN_DEBUG_TRACE, "->%s: end in error\n",__func__); 736 return error; 737 } 738 739 /* 740 * Define specific configuration based on device id and subdevice id 741 * pid : PCI device id 742 */ 743 static int 744 iwn_config_specific(struct iwn_softc *sc, uint16_t pid) 745 { 746 747 switch (pid) { 748 /* 4965 series */ 749 case IWN_DID_4965_1: 750 case IWN_DID_4965_2: 751 case IWN_DID_4965_3: 752 case IWN_DID_4965_4: 753 sc->base_params = &iwn4965_base_params; 754 sc->limits = &iwn4965_sensitivity_limits; 755 sc->fwname = "iwn4965fw"; 756 /* Override chains masks, ROM is known to be broken. */ 757 sc->txchainmask = IWN_ANT_AB; 758 sc->rxchainmask = IWN_ANT_ABC; 759 /* Enable normal btcoex */ 760 sc->sc_flags |= IWN_FLAG_BTCOEX; 761 break; 762 /* 1000 Series */ 763 case IWN_DID_1000_1: 764 case IWN_DID_1000_2: 765 switch(sc->subdevice_id) { 766 case IWN_SDID_1000_1: 767 case IWN_SDID_1000_2: 768 case IWN_SDID_1000_3: 769 case IWN_SDID_1000_4: 770 case IWN_SDID_1000_5: 771 case IWN_SDID_1000_6: 772 case IWN_SDID_1000_7: 773 case IWN_SDID_1000_8: 774 case IWN_SDID_1000_9: 775 case IWN_SDID_1000_10: 776 case IWN_SDID_1000_11: 777 case IWN_SDID_1000_12: 778 sc->limits = &iwn1000_sensitivity_limits; 779 sc->base_params = &iwn1000_base_params; 780 sc->fwname = "iwn1000fw"; 781 break; 782 default: 783 device_printf(sc->sc_dev, "adapter type id : 0x%04x sub id :" 784 "0x%04x rev %d not supported (subdevice)\n", pid, 785 sc->subdevice_id,sc->hw_type); 786 return ENOTSUP; 787 } 788 break; 789 /* 6x00 Series */ 790 case IWN_DID_6x00_2: 791 case IWN_DID_6x00_4: 792 case IWN_DID_6x00_1: 793 case IWN_DID_6x00_3: 794 sc->fwname = "iwn6000fw"; 795 sc->limits = &iwn6000_sensitivity_limits; 796 switch(sc->subdevice_id) { 797 case IWN_SDID_6x00_1: 798 case IWN_SDID_6x00_2: 799 case IWN_SDID_6x00_8: 800 //iwl6000_3agn_cfg 801 sc->base_params = &iwn_6000_base_params; 802 break; 803 case IWN_SDID_6x00_3: 804 case IWN_SDID_6x00_6: 805 case IWN_SDID_6x00_9: 806 ////iwl6000i_2agn 807 case IWN_SDID_6x00_4: 808 case IWN_SDID_6x00_7: 809 case IWN_SDID_6x00_10: 810 //iwl6000i_2abg_cfg 811 case IWN_SDID_6x00_5: 812 //iwl6000i_2bg_cfg 813 sc->base_params = &iwn_6000i_base_params; 814 sc->sc_flags |= IWN_FLAG_INTERNAL_PA; 815 sc->txchainmask = IWN_ANT_BC; 816 sc->rxchainmask = IWN_ANT_BC; 817 break; 818 default: 819 device_printf(sc->sc_dev, "adapter type id : 0x%04x sub id :" 820 "0x%04x rev %d not supported (subdevice)\n", pid, 821 sc->subdevice_id,sc->hw_type); 822 return ENOTSUP; 823 } 824 break; 825 /* 6x05 Series */ 826 case IWN_DID_6x05_1: 827 case IWN_DID_6x05_2: 828 switch(sc->subdevice_id) { 829 case IWN_SDID_6x05_1: 830 case IWN_SDID_6x05_4: 831 case IWN_SDID_6x05_6: 832 //iwl6005_2agn_cfg 833 case IWN_SDID_6x05_2: 834 case IWN_SDID_6x05_5: 835 case IWN_SDID_6x05_7: 836 //iwl6005_2abg_cfg 837 case IWN_SDID_6x05_3: 838 //iwl6005_2bg_cfg 839 case IWN_SDID_6x05_8: 840 case IWN_SDID_6x05_9: 841 //iwl6005_2agn_sff_cfg 842 case IWN_SDID_6x05_10: 843 //iwl6005_2agn_d_cfg 844 case IWN_SDID_6x05_11: 845 //iwl6005_2agn_mow1_cfg 846 case IWN_SDID_6x05_12: 847 //iwl6005_2agn_mow2_cfg 848 sc->fwname = "iwn6000g2afw"; 849 sc->limits = &iwn6000_sensitivity_limits; 850 sc->base_params = &iwn_6000g2_base_params; 851 break; 852 default: 853 device_printf(sc->sc_dev, "adapter type id : 0x%04x sub id :" 854 "0x%04x rev %d not supported (subdevice)\n", pid, 855 sc->subdevice_id,sc->hw_type); 856 return ENOTSUP; 857 } 858 break; 859 /* 6x35 Series */ 860 case IWN_DID_6035_1: 861 case IWN_DID_6035_2: 862 switch(sc->subdevice_id) { 863 case IWN_SDID_6035_1: 864 case IWN_SDID_6035_2: 865 case IWN_SDID_6035_3: 866 case IWN_SDID_6035_4: 867 case IWN_SDID_6035_5: 868 sc->fwname = "iwn6000g2bfw"; 869 sc->limits = &iwn6235_sensitivity_limits; 870 sc->base_params = &iwn_6235_base_params; 871 break; 872 default: 873 device_printf(sc->sc_dev, "adapter type id : 0x%04x sub id :" 874 "0x%04x rev %d not supported (subdevice)\n", pid, 875 sc->subdevice_id,sc->hw_type); 876 return ENOTSUP; 877 } 878 break; 879 /* 6x50 WiFi/WiMax Series */ 880 case IWN_DID_6050_1: 881 case IWN_DID_6050_2: 882 switch(sc->subdevice_id) { 883 case IWN_SDID_6050_1: 884 case IWN_SDID_6050_3: 885 case IWN_SDID_6050_5: 886 //iwl6050_2agn_cfg 887 case IWN_SDID_6050_2: 888 case IWN_SDID_6050_4: 889 case IWN_SDID_6050_6: 890 //iwl6050_2abg_cfg 891 sc->fwname = "iwn6050fw"; 892 sc->txchainmask = IWN_ANT_AB; 893 sc->rxchainmask = IWN_ANT_AB; 894 sc->limits = &iwn6000_sensitivity_limits; 895 sc->base_params = &iwn_6050_base_params; 896 break; 897 default: 898 device_printf(sc->sc_dev, "adapter type id : 0x%04x sub id :" 899 "0x%04x rev %d not supported (subdevice)\n", pid, 900 sc->subdevice_id,sc->hw_type); 901 return ENOTSUP; 902 } 903 break; 904 /* 6150 WiFi/WiMax Series */ 905 case IWN_DID_6150_1: 906 case IWN_DID_6150_2: 907 switch(sc->subdevice_id) { 908 case IWN_SDID_6150_1: 909 case IWN_SDID_6150_3: 910 case IWN_SDID_6150_5: 911 // iwl6150_bgn_cfg 912 case IWN_SDID_6150_2: 913 case IWN_SDID_6150_4: 914 case IWN_SDID_6150_6: 915 //iwl6150_bg_cfg 916 sc->fwname = "iwn6050fw"; 917 sc->limits = &iwn6000_sensitivity_limits; 918 sc->base_params = &iwn_6150_base_params; 919 break; 920 default: 921 device_printf(sc->sc_dev, "adapter type id : 0x%04x sub id :" 922 "0x%04x rev %d not supported (subdevice)\n", pid, 923 sc->subdevice_id,sc->hw_type); 924 return ENOTSUP; 925 } 926 break; 927 /* 6030 Series and 1030 Series */ 928 case IWN_DID_x030_1: 929 case IWN_DID_x030_2: 930 case IWN_DID_x030_3: 931 case IWN_DID_x030_4: 932 switch(sc->subdevice_id) { 933 case IWN_SDID_x030_1: 934 case IWN_SDID_x030_3: 935 case IWN_SDID_x030_5: 936 // iwl1030_bgn_cfg 937 case IWN_SDID_x030_2: 938 case IWN_SDID_x030_4: 939 case IWN_SDID_x030_6: 940 //iwl1030_bg_cfg 941 case IWN_SDID_x030_7: 942 case IWN_SDID_x030_10: 943 case IWN_SDID_x030_14: 944 //iwl6030_2agn_cfg 945 case IWN_SDID_x030_8: 946 case IWN_SDID_x030_11: 947 case IWN_SDID_x030_15: 948 // iwl6030_2bgn_cfg 949 case IWN_SDID_x030_9: 950 case IWN_SDID_x030_12: 951 case IWN_SDID_x030_16: 952 // iwl6030_2abg_cfg 953 case IWN_SDID_x030_13: 954 //iwl6030_2bg_cfg 955 sc->fwname = "iwn6000g2bfw"; 956 sc->limits = &iwn6000_sensitivity_limits; 957 sc->base_params = &iwn_6000g2b_base_params; 958 break; 959 default: 960 device_printf(sc->sc_dev, "adapter type id : 0x%04x sub id :" 961 "0x%04x rev %d not supported (subdevice)\n", pid, 962 sc->subdevice_id,sc->hw_type); 963 return ENOTSUP; 964 } 965 break; 966 /* 130 Series WiFi */ 967 /* XXX: This series will need adjustment for rate. 968 * see rx_with_siso_diversity in linux kernel 969 */ 970 case IWN_DID_130_1: 971 case IWN_DID_130_2: 972 switch(sc->subdevice_id) { 973 case IWN_SDID_130_1: 974 case IWN_SDID_130_3: 975 case IWN_SDID_130_5: 976 //iwl130_bgn_cfg 977 case IWN_SDID_130_2: 978 case IWN_SDID_130_4: 979 case IWN_SDID_130_6: 980 //iwl130_bg_cfg 981 sc->fwname = "iwn6000g2bfw"; 982 sc->limits = &iwn6000_sensitivity_limits; 983 sc->base_params = &iwn_6000g2b_base_params; 984 break; 985 default: 986 device_printf(sc->sc_dev, "adapter type id : 0x%04x sub id :" 987 "0x%04x rev %d not supported (subdevice)\n", pid, 988 sc->subdevice_id,sc->hw_type); 989 return ENOTSUP; 990 } 991 break; 992 /* 100 Series WiFi */ 993 case IWN_DID_100_1: 994 case IWN_DID_100_2: 995 switch(sc->subdevice_id) { 996 case IWN_SDID_100_1: 997 case IWN_SDID_100_2: 998 case IWN_SDID_100_3: 999 case IWN_SDID_100_4: 1000 case IWN_SDID_100_5: 1001 case IWN_SDID_100_6: 1002 sc->limits = &iwn1000_sensitivity_limits; 1003 sc->base_params = &iwn1000_base_params; 1004 sc->fwname = "iwn100fw"; 1005 break; 1006 default: 1007 device_printf(sc->sc_dev, "adapter type id : 0x%04x sub id :" 1008 "0x%04x rev %d not supported (subdevice)\n", pid, 1009 sc->subdevice_id,sc->hw_type); 1010 return ENOTSUP; 1011 } 1012 break; 1013 1014 /* 105 Series */ 1015 /* XXX: This series will need adjustment for rate. 1016 * see rx_with_siso_diversity in linux kernel 1017 */ 1018 case IWN_DID_105_1: 1019 case IWN_DID_105_2: 1020 switch(sc->subdevice_id) { 1021 case IWN_SDID_105_1: 1022 case IWN_SDID_105_2: 1023 case IWN_SDID_105_3: 1024 //iwl105_bgn_cfg 1025 case IWN_SDID_105_4: 1026 //iwl105_bgn_d_cfg 1027 sc->limits = &iwn2030_sensitivity_limits; 1028 sc->base_params = &iwn2000_base_params; 1029 sc->fwname = "iwn105fw"; 1030 break; 1031 default: 1032 device_printf(sc->sc_dev, "adapter type id : 0x%04x sub id :" 1033 "0x%04x rev %d not supported (subdevice)\n", pid, 1034 sc->subdevice_id,sc->hw_type); 1035 return ENOTSUP; 1036 } 1037 break; 1038 1039 /* 135 Series */ 1040 /* XXX: This series will need adjustment for rate. 1041 * see rx_with_siso_diversity in linux kernel 1042 */ 1043 case IWN_DID_135_1: 1044 case IWN_DID_135_2: 1045 switch(sc->subdevice_id) { 1046 case IWN_SDID_135_1: 1047 case IWN_SDID_135_2: 1048 case IWN_SDID_135_3: 1049 sc->limits = &iwn2030_sensitivity_limits; 1050 sc->base_params = &iwn2030_base_params; 1051 sc->fwname = "iwn135fw"; 1052 break; 1053 default: 1054 device_printf(sc->sc_dev, "adapter type id : 0x%04x sub id :" 1055 "0x%04x rev %d not supported (subdevice)\n", pid, 1056 sc->subdevice_id,sc->hw_type); 1057 return ENOTSUP; 1058 } 1059 break; 1060 1061 /* 2x00 Series */ 1062 case IWN_DID_2x00_1: 1063 case IWN_DID_2x00_2: 1064 switch(sc->subdevice_id) { 1065 case IWN_SDID_2x00_1: 1066 case IWN_SDID_2x00_2: 1067 case IWN_SDID_2x00_3: 1068 //iwl2000_2bgn_cfg 1069 case IWN_SDID_2x00_4: 1070 //iwl2000_2bgn_d_cfg 1071 sc->limits = &iwn2030_sensitivity_limits; 1072 sc->base_params = &iwn2000_base_params; 1073 sc->fwname = "iwn2000fw"; 1074 break; 1075 default: 1076 device_printf(sc->sc_dev, "adapter type id : 0x%04x sub id :" 1077 "0x%04x rev %d not supported (subdevice) \n", 1078 pid, sc->subdevice_id, sc->hw_type); 1079 return ENOTSUP; 1080 } 1081 break; 1082 /* 2x30 Series */ 1083 case IWN_DID_2x30_1: 1084 case IWN_DID_2x30_2: 1085 switch(sc->subdevice_id) { 1086 case IWN_SDID_2x30_1: 1087 case IWN_SDID_2x30_3: 1088 case IWN_SDID_2x30_5: 1089 //iwl100_bgn_cfg 1090 case IWN_SDID_2x30_2: 1091 case IWN_SDID_2x30_4: 1092 case IWN_SDID_2x30_6: 1093 //iwl100_bg_cfg 1094 sc->limits = &iwn2030_sensitivity_limits; 1095 sc->base_params = &iwn2030_base_params; 1096 sc->fwname = "iwn2030fw"; 1097 break; 1098 default: 1099 device_printf(sc->sc_dev, "adapter type id : 0x%04x sub id :" 1100 "0x%04x rev %d not supported (subdevice)\n", pid, 1101 sc->subdevice_id,sc->hw_type); 1102 return ENOTSUP; 1103 } 1104 break; 1105 /* 5x00 Series */ 1106 case IWN_DID_5x00_1: 1107 case IWN_DID_5x00_2: 1108 case IWN_DID_5x00_3: 1109 case IWN_DID_5x00_4: 1110 sc->limits = &iwn5000_sensitivity_limits; 1111 sc->base_params = &iwn5000_base_params; 1112 sc->fwname = "iwn5000fw"; 1113 switch(sc->subdevice_id) { 1114 case IWN_SDID_5x00_1: 1115 case IWN_SDID_5x00_2: 1116 case IWN_SDID_5x00_3: 1117 case IWN_SDID_5x00_4: 1118 case IWN_SDID_5x00_9: 1119 case IWN_SDID_5x00_10: 1120 case IWN_SDID_5x00_11: 1121 case IWN_SDID_5x00_12: 1122 case IWN_SDID_5x00_17: 1123 case IWN_SDID_5x00_18: 1124 case IWN_SDID_5x00_19: 1125 case IWN_SDID_5x00_20: 1126 //iwl5100_agn_cfg 1127 sc->txchainmask = IWN_ANT_B; 1128 sc->rxchainmask = IWN_ANT_AB; 1129 break; 1130 case IWN_SDID_5x00_5: 1131 case IWN_SDID_5x00_6: 1132 case IWN_SDID_5x00_13: 1133 case IWN_SDID_5x00_14: 1134 case IWN_SDID_5x00_21: 1135 case IWN_SDID_5x00_22: 1136 //iwl5100_bgn_cfg 1137 sc->txchainmask = IWN_ANT_B; 1138 sc->rxchainmask = IWN_ANT_AB; 1139 break; 1140 case IWN_SDID_5x00_7: 1141 case IWN_SDID_5x00_8: 1142 case IWN_SDID_5x00_15: 1143 case IWN_SDID_5x00_16: 1144 case IWN_SDID_5x00_23: 1145 case IWN_SDID_5x00_24: 1146 //iwl5100_abg_cfg 1147 sc->txchainmask = IWN_ANT_B; 1148 sc->rxchainmask = IWN_ANT_AB; 1149 break; 1150 case IWN_SDID_5x00_25: 1151 case IWN_SDID_5x00_26: 1152 case IWN_SDID_5x00_27: 1153 case IWN_SDID_5x00_28: 1154 case IWN_SDID_5x00_29: 1155 case IWN_SDID_5x00_30: 1156 case IWN_SDID_5x00_31: 1157 case IWN_SDID_5x00_32: 1158 case IWN_SDID_5x00_33: 1159 case IWN_SDID_5x00_34: 1160 case IWN_SDID_5x00_35: 1161 case IWN_SDID_5x00_36: 1162 //iwl5300_agn_cfg 1163 sc->txchainmask = IWN_ANT_ABC; 1164 sc->rxchainmask = IWN_ANT_ABC; 1165 break; 1166 default: 1167 device_printf(sc->sc_dev, "adapter type id : 0x%04x sub id :" 1168 "0x%04x rev %d not supported (subdevice)\n", pid, 1169 sc->subdevice_id,sc->hw_type); 1170 return ENOTSUP; 1171 } 1172 break; 1173 /* 5x50 Series */ 1174 case IWN_DID_5x50_1: 1175 case IWN_DID_5x50_2: 1176 case IWN_DID_5x50_3: 1177 case IWN_DID_5x50_4: 1178 sc->limits = &iwn5000_sensitivity_limits; 1179 sc->base_params = &iwn5000_base_params; 1180 sc->fwname = "iwn5000fw"; 1181 switch(sc->subdevice_id) { 1182 case IWN_SDID_5x50_1: 1183 case IWN_SDID_5x50_2: 1184 case IWN_SDID_5x50_3: 1185 //iwl5350_agn_cfg 1186 sc->limits = &iwn5000_sensitivity_limits; 1187 sc->base_params = &iwn5000_base_params; 1188 sc->fwname = "iwn5000fw"; 1189 break; 1190 case IWN_SDID_5x50_4: 1191 case IWN_SDID_5x50_5: 1192 case IWN_SDID_5x50_8: 1193 case IWN_SDID_5x50_9: 1194 case IWN_SDID_5x50_10: 1195 case IWN_SDID_5x50_11: 1196 //iwl5150_agn_cfg 1197 case IWN_SDID_5x50_6: 1198 case IWN_SDID_5x50_7: 1199 case IWN_SDID_5x50_12: 1200 case IWN_SDID_5x50_13: 1201 //iwl5150_abg_cfg 1202 sc->limits = &iwn5000_sensitivity_limits; 1203 sc->fwname = "iwn5150fw"; 1204 sc->base_params = &iwn_5x50_base_params; 1205 break; 1206 default: 1207 device_printf(sc->sc_dev, "adapter type id : 0x%04x sub id :" 1208 "0x%04x rev %d not supported (subdevice)\n", pid, 1209 sc->subdevice_id,sc->hw_type); 1210 return ENOTSUP; 1211 } 1212 break; 1213 default: 1214 device_printf(sc->sc_dev, "adapter type id : 0x%04x sub id : 0x%04x" 1215 "rev 0x%08x not supported (device)\n", pid, sc->subdevice_id, 1216 sc->hw_type); 1217 return ENOTSUP; 1218 } 1219 return 0; 1220 } 1221 1222 static void 1223 iwn4965_attach(struct iwn_softc *sc, uint16_t pid) 1224 { 1225 struct iwn_ops *ops = &sc->ops; 1226 1227 DPRINTF(sc, IWN_DEBUG_TRACE, "->%s begin\n", __func__); 1228 1229 ops->load_firmware = iwn4965_load_firmware; 1230 ops->read_eeprom = iwn4965_read_eeprom; 1231 ops->post_alive = iwn4965_post_alive; 1232 ops->nic_config = iwn4965_nic_config; 1233 ops->update_sched = iwn4965_update_sched; 1234 ops->get_temperature = iwn4965_get_temperature; 1235 ops->get_rssi = iwn4965_get_rssi; 1236 ops->set_txpower = iwn4965_set_txpower; 1237 ops->init_gains = iwn4965_init_gains; 1238 ops->set_gains = iwn4965_set_gains; 1239 ops->rxon_assoc = iwn4965_rxon_assoc; 1240 ops->add_node = iwn4965_add_node; 1241 ops->tx_done = iwn4965_tx_done; 1242 ops->ampdu_tx_start = iwn4965_ampdu_tx_start; 1243 ops->ampdu_tx_stop = iwn4965_ampdu_tx_stop; 1244 sc->ntxqs = IWN4965_NTXQUEUES; 1245 sc->firstaggqueue = IWN4965_FIRSTAGGQUEUE; 1246 sc->ndmachnls = IWN4965_NDMACHNLS; 1247 sc->broadcast_id = IWN4965_ID_BROADCAST; 1248 sc->rxonsz = IWN4965_RXONSZ; 1249 sc->schedsz = IWN4965_SCHEDSZ; 1250 sc->fw_text_maxsz = IWN4965_FW_TEXT_MAXSZ; 1251 sc->fw_data_maxsz = IWN4965_FW_DATA_MAXSZ; 1252 sc->fwsz = IWN4965_FWSZ; 1253 sc->sched_txfact_addr = IWN4965_SCHED_TXFACT; 1254 sc->limits = &iwn4965_sensitivity_limits; 1255 sc->fwname = "iwn4965fw"; 1256 /* Override chains masks, ROM is known to be broken. */ 1257 sc->txchainmask = IWN_ANT_AB; 1258 sc->rxchainmask = IWN_ANT_ABC; 1259 /* Enable normal btcoex */ 1260 sc->sc_flags |= IWN_FLAG_BTCOEX; 1261 1262 DPRINTF(sc, IWN_DEBUG_TRACE, "%s: end\n",__func__); 1263 } 1264 1265 static void 1266 iwn5000_attach(struct iwn_softc *sc, uint16_t pid) 1267 { 1268 struct iwn_ops *ops = &sc->ops; 1269 1270 DPRINTF(sc, IWN_DEBUG_TRACE, "->%s begin\n", __func__); 1271 1272 ops->load_firmware = iwn5000_load_firmware; 1273 ops->read_eeprom = iwn5000_read_eeprom; 1274 ops->post_alive = iwn5000_post_alive; 1275 ops->nic_config = iwn5000_nic_config; 1276 ops->update_sched = iwn5000_update_sched; 1277 ops->get_temperature = iwn5000_get_temperature; 1278 ops->get_rssi = iwn5000_get_rssi; 1279 ops->set_txpower = iwn5000_set_txpower; 1280 ops->init_gains = iwn5000_init_gains; 1281 ops->set_gains = iwn5000_set_gains; 1282 ops->rxon_assoc = iwn5000_rxon_assoc; 1283 ops->add_node = iwn5000_add_node; 1284 ops->tx_done = iwn5000_tx_done; 1285 ops->ampdu_tx_start = iwn5000_ampdu_tx_start; 1286 ops->ampdu_tx_stop = iwn5000_ampdu_tx_stop; 1287 sc->ntxqs = IWN5000_NTXQUEUES; 1288 sc->firstaggqueue = IWN5000_FIRSTAGGQUEUE; 1289 sc->ndmachnls = IWN5000_NDMACHNLS; 1290 sc->broadcast_id = IWN5000_ID_BROADCAST; 1291 sc->rxonsz = IWN5000_RXONSZ; 1292 sc->schedsz = IWN5000_SCHEDSZ; 1293 sc->fw_text_maxsz = IWN5000_FW_TEXT_MAXSZ; 1294 sc->fw_data_maxsz = IWN5000_FW_DATA_MAXSZ; 1295 sc->fwsz = IWN5000_FWSZ; 1296 sc->sched_txfact_addr = IWN5000_SCHED_TXFACT; 1297 sc->reset_noise_gain = IWN5000_PHY_CALIB_RESET_NOISE_GAIN; 1298 sc->noise_gain = IWN5000_PHY_CALIB_NOISE_GAIN; 1299 1300 DPRINTF(sc, IWN_DEBUG_TRACE, "%s: end\n",__func__); 1301 } 1302 1303 /* 1304 * Attach the interface to 802.11 radiotap. 1305 */ 1306 static void 1307 iwn_radiotap_attach(struct iwn_softc *sc) 1308 { 1309 1310 DPRINTF(sc, IWN_DEBUG_TRACE, "->%s begin\n", __func__); 1311 ieee80211_radiotap_attach(&sc->sc_ic, 1312 &sc->sc_txtap.wt_ihdr, sizeof(sc->sc_txtap), 1313 IWN_TX_RADIOTAP_PRESENT, 1314 &sc->sc_rxtap.wr_ihdr, sizeof(sc->sc_rxtap), 1315 IWN_RX_RADIOTAP_PRESENT); 1316 DPRINTF(sc, IWN_DEBUG_TRACE, "->%s end\n", __func__); 1317 } 1318 1319 static void 1320 iwn_sysctlattach(struct iwn_softc *sc) 1321 { 1322 #ifdef IWN_DEBUG 1323 struct sysctl_ctx_list *ctx = device_get_sysctl_ctx(sc->sc_dev); 1324 struct sysctl_oid *tree = device_get_sysctl_tree(sc->sc_dev); 1325 1326 SYSCTL_ADD_INT(ctx, SYSCTL_CHILDREN(tree), OID_AUTO, 1327 "debug", CTLFLAG_RW, &sc->sc_debug, sc->sc_debug, 1328 "control debugging printfs"); 1329 #endif 1330 } 1331 1332 static struct ieee80211vap * 1333 iwn_vap_create(struct ieee80211com *ic, const char name[IFNAMSIZ], int unit, 1334 enum ieee80211_opmode opmode, int flags, 1335 const uint8_t bssid[IEEE80211_ADDR_LEN], 1336 const uint8_t mac[IEEE80211_ADDR_LEN]) 1337 { 1338 struct iwn_softc *sc = ic->ic_softc; 1339 struct iwn_vap *ivp; 1340 struct ieee80211vap *vap; 1341 1342 if (!TAILQ_EMPTY(&ic->ic_vaps)) /* only one at a time */ 1343 return NULL; 1344 1345 ivp = malloc(sizeof(struct iwn_vap), M_80211_VAP, M_WAITOK | M_ZERO); 1346 vap = &ivp->iv_vap; 1347 ieee80211_vap_setup(ic, vap, name, unit, opmode, flags, bssid); 1348 ivp->ctx = IWN_RXON_BSS_CTX; 1349 vap->iv_bmissthreshold = 10; /* override default */ 1350 /* Override with driver methods. */ 1351 ivp->iv_newstate = vap->iv_newstate; 1352 vap->iv_newstate = iwn_newstate; 1353 sc->ivap[IWN_RXON_BSS_CTX] = vap; 1354 1355 ieee80211_ratectl_init(vap); 1356 /* Complete setup. */ 1357 ieee80211_vap_attach(vap, iwn_media_change, ieee80211_media_status, 1358 mac); 1359 ic->ic_opmode = opmode; 1360 return vap; 1361 } 1362 1363 static void 1364 iwn_vap_delete(struct ieee80211vap *vap) 1365 { 1366 struct iwn_vap *ivp = IWN_VAP(vap); 1367 1368 ieee80211_ratectl_deinit(vap); 1369 ieee80211_vap_detach(vap); 1370 free(ivp, M_80211_VAP); 1371 } 1372 1373 static void 1374 iwn_xmit_queue_drain(struct iwn_softc *sc) 1375 { 1376 struct mbuf *m; 1377 struct ieee80211_node *ni; 1378 1379 IWN_LOCK_ASSERT(sc); 1380 while ((m = mbufq_dequeue(&sc->sc_xmit_queue)) != NULL) { 1381 ni = (struct ieee80211_node *)m->m_pkthdr.rcvif; 1382 ieee80211_free_node(ni); 1383 m_freem(m); 1384 } 1385 } 1386 1387 static int 1388 iwn_xmit_queue_enqueue(struct iwn_softc *sc, struct mbuf *m) 1389 { 1390 1391 IWN_LOCK_ASSERT(sc); 1392 return (mbufq_enqueue(&sc->sc_xmit_queue, m)); 1393 } 1394 1395 static int 1396 iwn_detach(device_t dev) 1397 { 1398 struct iwn_softc *sc = device_get_softc(dev); 1399 int qid; 1400 1401 DPRINTF(sc, IWN_DEBUG_TRACE, "->%s begin\n", __func__); 1402 1403 if (sc->sc_ic.ic_softc != NULL) { 1404 /* Free the mbuf queue and node references */ 1405 IWN_LOCK(sc); 1406 iwn_xmit_queue_drain(sc); 1407 IWN_UNLOCK(sc); 1408 1409 iwn_stop(sc); 1410 1411 taskqueue_drain_all(sc->sc_tq); 1412 taskqueue_free(sc->sc_tq); 1413 1414 callout_drain(&sc->watchdog_to); 1415 callout_drain(&sc->scan_timeout); 1416 callout_drain(&sc->calib_to); 1417 ieee80211_ifdetach(&sc->sc_ic); 1418 } 1419 1420 /* Uninstall interrupt handler. */ 1421 if (sc->irq != NULL) { 1422 bus_teardown_intr(dev, sc->irq, sc->sc_ih); 1423 bus_release_resource(dev, SYS_RES_IRQ, rman_get_rid(sc->irq), 1424 sc->irq); 1425 pci_release_msi(dev); 1426 } 1427 1428 /* Free DMA resources. */ 1429 iwn_free_rx_ring(sc, &sc->rxq); 1430 for (qid = 0; qid < sc->ntxqs; qid++) 1431 iwn_free_tx_ring(sc, &sc->txq[qid]); 1432 iwn_free_sched(sc); 1433 iwn_free_kw(sc); 1434 if (sc->ict != NULL) 1435 iwn_free_ict(sc); 1436 iwn_free_fwmem(sc); 1437 1438 if (sc->mem != NULL) 1439 bus_release_resource(dev, SYS_RES_MEMORY, 1440 rman_get_rid(sc->mem), sc->mem); 1441 1442 if (sc->sc_cdev) { 1443 destroy_dev(sc->sc_cdev); 1444 sc->sc_cdev = NULL; 1445 } 1446 1447 DPRINTF(sc, IWN_DEBUG_TRACE, "->%s: end\n", __func__); 1448 IWN_LOCK_DESTROY(sc); 1449 return 0; 1450 } 1451 1452 static int 1453 iwn_shutdown(device_t dev) 1454 { 1455 struct iwn_softc *sc = device_get_softc(dev); 1456 1457 iwn_stop(sc); 1458 return 0; 1459 } 1460 1461 static int 1462 iwn_suspend(device_t dev) 1463 { 1464 struct iwn_softc *sc = device_get_softc(dev); 1465 1466 ieee80211_suspend_all(&sc->sc_ic); 1467 return 0; 1468 } 1469 1470 static int 1471 iwn_resume(device_t dev) 1472 { 1473 struct iwn_softc *sc = device_get_softc(dev); 1474 1475 /* Clear device-specific "PCI retry timeout" register (41h). */ 1476 pci_write_config(dev, 0x41, 0, 1); 1477 1478 ieee80211_resume_all(&sc->sc_ic); 1479 return 0; 1480 } 1481 1482 static int 1483 iwn_nic_lock(struct iwn_softc *sc) 1484 { 1485 int ntries; 1486 1487 /* Request exclusive access to NIC. */ 1488 IWN_SETBITS(sc, IWN_GP_CNTRL, IWN_GP_CNTRL_MAC_ACCESS_REQ); 1489 1490 /* Spin until we actually get the lock. */ 1491 for (ntries = 0; ntries < 1000; ntries++) { 1492 if ((IWN_READ(sc, IWN_GP_CNTRL) & 1493 (IWN_GP_CNTRL_MAC_ACCESS_ENA | IWN_GP_CNTRL_SLEEP)) == 1494 IWN_GP_CNTRL_MAC_ACCESS_ENA) 1495 return 0; 1496 DELAY(10); 1497 } 1498 return ETIMEDOUT; 1499 } 1500 1501 static __inline void 1502 iwn_nic_unlock(struct iwn_softc *sc) 1503 { 1504 IWN_CLRBITS(sc, IWN_GP_CNTRL, IWN_GP_CNTRL_MAC_ACCESS_REQ); 1505 } 1506 1507 static __inline uint32_t 1508 iwn_prph_read(struct iwn_softc *sc, uint32_t addr) 1509 { 1510 IWN_WRITE(sc, IWN_PRPH_RADDR, IWN_PRPH_DWORD | addr); 1511 IWN_BARRIER_READ_WRITE(sc); 1512 return IWN_READ(sc, IWN_PRPH_RDATA); 1513 } 1514 1515 static __inline void 1516 iwn_prph_write(struct iwn_softc *sc, uint32_t addr, uint32_t data) 1517 { 1518 IWN_WRITE(sc, IWN_PRPH_WADDR, IWN_PRPH_DWORD | addr); 1519 IWN_BARRIER_WRITE(sc); 1520 IWN_WRITE(sc, IWN_PRPH_WDATA, data); 1521 } 1522 1523 static __inline void 1524 iwn_prph_setbits(struct iwn_softc *sc, uint32_t addr, uint32_t mask) 1525 { 1526 iwn_prph_write(sc, addr, iwn_prph_read(sc, addr) | mask); 1527 } 1528 1529 static __inline void 1530 iwn_prph_clrbits(struct iwn_softc *sc, uint32_t addr, uint32_t mask) 1531 { 1532 iwn_prph_write(sc, addr, iwn_prph_read(sc, addr) & ~mask); 1533 } 1534 1535 static __inline void 1536 iwn_prph_write_region_4(struct iwn_softc *sc, uint32_t addr, 1537 const uint32_t *data, int count) 1538 { 1539 for (; count > 0; count--, data++, addr += 4) 1540 iwn_prph_write(sc, addr, *data); 1541 } 1542 1543 static __inline uint32_t 1544 iwn_mem_read(struct iwn_softc *sc, uint32_t addr) 1545 { 1546 IWN_WRITE(sc, IWN_MEM_RADDR, addr); 1547 IWN_BARRIER_READ_WRITE(sc); 1548 return IWN_READ(sc, IWN_MEM_RDATA); 1549 } 1550 1551 static __inline void 1552 iwn_mem_write(struct iwn_softc *sc, uint32_t addr, uint32_t data) 1553 { 1554 IWN_WRITE(sc, IWN_MEM_WADDR, addr); 1555 IWN_BARRIER_WRITE(sc); 1556 IWN_WRITE(sc, IWN_MEM_WDATA, data); 1557 } 1558 1559 static __inline void 1560 iwn_mem_write_2(struct iwn_softc *sc, uint32_t addr, uint16_t data) 1561 { 1562 uint32_t tmp; 1563 1564 tmp = iwn_mem_read(sc, addr & ~3); 1565 if (addr & 3) 1566 tmp = (tmp & 0x0000ffff) | data << 16; 1567 else 1568 tmp = (tmp & 0xffff0000) | data; 1569 iwn_mem_write(sc, addr & ~3, tmp); 1570 } 1571 1572 static __inline void 1573 iwn_mem_read_region_4(struct iwn_softc *sc, uint32_t addr, uint32_t *data, 1574 int count) 1575 { 1576 for (; count > 0; count--, addr += 4) 1577 *data++ = iwn_mem_read(sc, addr); 1578 } 1579 1580 static __inline void 1581 iwn_mem_set_region_4(struct iwn_softc *sc, uint32_t addr, uint32_t val, 1582 int count) 1583 { 1584 for (; count > 0; count--, addr += 4) 1585 iwn_mem_write(sc, addr, val); 1586 } 1587 1588 static int 1589 iwn_eeprom_lock(struct iwn_softc *sc) 1590 { 1591 int i, ntries; 1592 1593 for (i = 0; i < 100; i++) { 1594 /* Request exclusive access to EEPROM. */ 1595 IWN_SETBITS(sc, IWN_HW_IF_CONFIG, 1596 IWN_HW_IF_CONFIG_EEPROM_LOCKED); 1597 1598 /* Spin until we actually get the lock. */ 1599 for (ntries = 0; ntries < 100; ntries++) { 1600 if (IWN_READ(sc, IWN_HW_IF_CONFIG) & 1601 IWN_HW_IF_CONFIG_EEPROM_LOCKED) 1602 return 0; 1603 DELAY(10); 1604 } 1605 } 1606 DPRINTF(sc, IWN_DEBUG_TRACE, "->%s end timeout\n", __func__); 1607 return ETIMEDOUT; 1608 } 1609 1610 static __inline void 1611 iwn_eeprom_unlock(struct iwn_softc *sc) 1612 { 1613 IWN_CLRBITS(sc, IWN_HW_IF_CONFIG, IWN_HW_IF_CONFIG_EEPROM_LOCKED); 1614 } 1615 1616 /* 1617 * Initialize access by host to One Time Programmable ROM. 1618 * NB: This kind of ROM can be found on 1000 or 6000 Series only. 1619 */ 1620 static int 1621 iwn_init_otprom(struct iwn_softc *sc) 1622 { 1623 uint16_t prev, base, next; 1624 int count, error; 1625 1626 DPRINTF(sc, IWN_DEBUG_TRACE, "->%s begin\n", __func__); 1627 1628 /* Wait for clock stabilization before accessing prph. */ 1629 if ((error = iwn_clock_wait(sc)) != 0) 1630 return error; 1631 1632 if ((error = iwn_nic_lock(sc)) != 0) 1633 return error; 1634 iwn_prph_setbits(sc, IWN_APMG_PS, IWN_APMG_PS_RESET_REQ); 1635 DELAY(5); 1636 iwn_prph_clrbits(sc, IWN_APMG_PS, IWN_APMG_PS_RESET_REQ); 1637 iwn_nic_unlock(sc); 1638 1639 /* Set auto clock gate disable bit for HW with OTP shadow RAM. */ 1640 if (sc->base_params->shadow_ram_support) { 1641 IWN_SETBITS(sc, IWN_DBG_LINK_PWR_MGMT, 1642 IWN_RESET_LINK_PWR_MGMT_DIS); 1643 } 1644 IWN_CLRBITS(sc, IWN_EEPROM_GP, IWN_EEPROM_GP_IF_OWNER); 1645 /* Clear ECC status. */ 1646 IWN_SETBITS(sc, IWN_OTP_GP, 1647 IWN_OTP_GP_ECC_CORR_STTS | IWN_OTP_GP_ECC_UNCORR_STTS); 1648 1649 /* 1650 * Find the block before last block (contains the EEPROM image) 1651 * for HW without OTP shadow RAM. 1652 */ 1653 if (! sc->base_params->shadow_ram_support) { 1654 /* Switch to absolute addressing mode. */ 1655 IWN_CLRBITS(sc, IWN_OTP_GP, IWN_OTP_GP_RELATIVE_ACCESS); 1656 base = prev = 0; 1657 for (count = 0; count < sc->base_params->max_ll_items; 1658 count++) { 1659 error = iwn_read_prom_data(sc, base, &next, 2); 1660 if (error != 0) 1661 return error; 1662 if (next == 0) /* End of linked-list. */ 1663 break; 1664 prev = base; 1665 base = le16toh(next); 1666 } 1667 if (count == 0 || count == sc->base_params->max_ll_items) 1668 return EIO; 1669 /* Skip "next" word. */ 1670 sc->prom_base = prev + 1; 1671 } 1672 1673 DPRINTF(sc, IWN_DEBUG_TRACE, "->%s end\n", __func__); 1674 1675 return 0; 1676 } 1677 1678 static int 1679 iwn_read_prom_data(struct iwn_softc *sc, uint32_t addr, void *data, int count) 1680 { 1681 uint8_t *out = data; 1682 uint32_t val, tmp; 1683 int ntries; 1684 1685 DPRINTF(sc, IWN_DEBUG_TRACE, "->%s begin\n", __func__); 1686 1687 addr += sc->prom_base; 1688 for (; count > 0; count -= 2, addr++) { 1689 IWN_WRITE(sc, IWN_EEPROM, addr << 2); 1690 for (ntries = 0; ntries < 10; ntries++) { 1691 val = IWN_READ(sc, IWN_EEPROM); 1692 if (val & IWN_EEPROM_READ_VALID) 1693 break; 1694 DELAY(5); 1695 } 1696 if (ntries == 10) { 1697 device_printf(sc->sc_dev, 1698 "timeout reading ROM at 0x%x\n", addr); 1699 return ETIMEDOUT; 1700 } 1701 if (sc->sc_flags & IWN_FLAG_HAS_OTPROM) { 1702 /* OTPROM, check for ECC errors. */ 1703 tmp = IWN_READ(sc, IWN_OTP_GP); 1704 if (tmp & IWN_OTP_GP_ECC_UNCORR_STTS) { 1705 device_printf(sc->sc_dev, 1706 "OTPROM ECC error at 0x%x\n", addr); 1707 return EIO; 1708 } 1709 if (tmp & IWN_OTP_GP_ECC_CORR_STTS) { 1710 /* Correctable ECC error, clear bit. */ 1711 IWN_SETBITS(sc, IWN_OTP_GP, 1712 IWN_OTP_GP_ECC_CORR_STTS); 1713 } 1714 } 1715 *out++ = val >> 16; 1716 if (count > 1) 1717 *out++ = val >> 24; 1718 } 1719 1720 DPRINTF(sc, IWN_DEBUG_TRACE, "->%s end\n", __func__); 1721 1722 return 0; 1723 } 1724 1725 static void 1726 iwn_dma_map_addr(void *arg, bus_dma_segment_t *segs, int nsegs, int error) 1727 { 1728 if (error != 0) 1729 return; 1730 KASSERT(nsegs == 1, ("too many DMA segments, %d should be 1", nsegs)); 1731 *(bus_addr_t *)arg = segs[0].ds_addr; 1732 } 1733 1734 static int 1735 iwn_dma_contig_alloc(struct iwn_softc *sc, struct iwn_dma_info *dma, 1736 void **kvap, bus_size_t size, bus_size_t alignment) 1737 { 1738 int error; 1739 1740 dma->tag = NULL; 1741 dma->size = size; 1742 1743 error = bus_dma_tag_create(bus_get_dma_tag(sc->sc_dev), alignment, 1744 0, BUS_SPACE_MAXADDR_32BIT, BUS_SPACE_MAXADDR, NULL, NULL, size, 1745 1, size, 0, NULL, NULL, &dma->tag); 1746 if (error != 0) 1747 goto fail; 1748 1749 error = bus_dmamem_alloc(dma->tag, (void **)&dma->vaddr, 1750 BUS_DMA_NOWAIT | BUS_DMA_ZERO | BUS_DMA_COHERENT, &dma->map); 1751 if (error != 0) 1752 goto fail; 1753 1754 error = bus_dmamap_load(dma->tag, dma->map, dma->vaddr, size, 1755 iwn_dma_map_addr, &dma->paddr, BUS_DMA_NOWAIT); 1756 if (error != 0) 1757 goto fail; 1758 1759 bus_dmamap_sync(dma->tag, dma->map, BUS_DMASYNC_PREWRITE); 1760 1761 if (kvap != NULL) 1762 *kvap = dma->vaddr; 1763 1764 return 0; 1765 1766 fail: iwn_dma_contig_free(dma); 1767 return error; 1768 } 1769 1770 static void 1771 iwn_dma_contig_free(struct iwn_dma_info *dma) 1772 { 1773 if (dma->vaddr != NULL) { 1774 bus_dmamap_sync(dma->tag, dma->map, 1775 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); 1776 bus_dmamap_unload(dma->tag, dma->map); 1777 bus_dmamem_free(dma->tag, dma->vaddr, dma->map); 1778 dma->vaddr = NULL; 1779 } 1780 if (dma->tag != NULL) { 1781 bus_dma_tag_destroy(dma->tag); 1782 dma->tag = NULL; 1783 } 1784 } 1785 1786 static int 1787 iwn_alloc_sched(struct iwn_softc *sc) 1788 { 1789 /* TX scheduler rings must be aligned on a 1KB boundary. */ 1790 return iwn_dma_contig_alloc(sc, &sc->sched_dma, (void **)&sc->sched, 1791 sc->schedsz, 1024); 1792 } 1793 1794 static void 1795 iwn_free_sched(struct iwn_softc *sc) 1796 { 1797 iwn_dma_contig_free(&sc->sched_dma); 1798 } 1799 1800 static int 1801 iwn_alloc_kw(struct iwn_softc *sc) 1802 { 1803 /* "Keep Warm" page must be aligned on a 4KB boundary. */ 1804 return iwn_dma_contig_alloc(sc, &sc->kw_dma, NULL, 4096, 4096); 1805 } 1806 1807 static void 1808 iwn_free_kw(struct iwn_softc *sc) 1809 { 1810 iwn_dma_contig_free(&sc->kw_dma); 1811 } 1812 1813 static int 1814 iwn_alloc_ict(struct iwn_softc *sc) 1815 { 1816 /* ICT table must be aligned on a 4KB boundary. */ 1817 return iwn_dma_contig_alloc(sc, &sc->ict_dma, (void **)&sc->ict, 1818 IWN_ICT_SIZE, 4096); 1819 } 1820 1821 static void 1822 iwn_free_ict(struct iwn_softc *sc) 1823 { 1824 iwn_dma_contig_free(&sc->ict_dma); 1825 } 1826 1827 static int 1828 iwn_alloc_fwmem(struct iwn_softc *sc) 1829 { 1830 /* Must be aligned on a 16-byte boundary. */ 1831 return iwn_dma_contig_alloc(sc, &sc->fw_dma, NULL, sc->fwsz, 16); 1832 } 1833 1834 static void 1835 iwn_free_fwmem(struct iwn_softc *sc) 1836 { 1837 iwn_dma_contig_free(&sc->fw_dma); 1838 } 1839 1840 static int 1841 iwn_alloc_rx_ring(struct iwn_softc *sc, struct iwn_rx_ring *ring) 1842 { 1843 bus_size_t size; 1844 int i, error; 1845 1846 ring->cur = 0; 1847 1848 DPRINTF(sc, IWN_DEBUG_TRACE, "->%s begin\n", __func__); 1849 1850 /* Allocate RX descriptors (256-byte aligned). */ 1851 size = IWN_RX_RING_COUNT * sizeof (uint32_t); 1852 error = iwn_dma_contig_alloc(sc, &ring->desc_dma, (void **)&ring->desc, 1853 size, 256); 1854 if (error != 0) { 1855 device_printf(sc->sc_dev, 1856 "%s: could not allocate RX ring DMA memory, error %d\n", 1857 __func__, error); 1858 goto fail; 1859 } 1860 1861 /* Allocate RX status area (16-byte aligned). */ 1862 error = iwn_dma_contig_alloc(sc, &ring->stat_dma, (void **)&ring->stat, 1863 sizeof (struct iwn_rx_status), 16); 1864 if (error != 0) { 1865 device_printf(sc->sc_dev, 1866 "%s: could not allocate RX status DMA memory, error %d\n", 1867 __func__, error); 1868 goto fail; 1869 } 1870 1871 /* Create RX buffer DMA tag. */ 1872 error = bus_dma_tag_create(bus_get_dma_tag(sc->sc_dev), 1, 0, 1873 BUS_SPACE_MAXADDR_32BIT, BUS_SPACE_MAXADDR, NULL, NULL, 1874 IWN_RBUF_SIZE, 1, IWN_RBUF_SIZE, 0, NULL, NULL, &ring->data_dmat); 1875 if (error != 0) { 1876 device_printf(sc->sc_dev, 1877 "%s: could not create RX buf DMA tag, error %d\n", 1878 __func__, error); 1879 goto fail; 1880 } 1881 1882 /* 1883 * Allocate and map RX buffers. 1884 */ 1885 for (i = 0; i < IWN_RX_RING_COUNT; i++) { 1886 struct iwn_rx_data *data = &ring->data[i]; 1887 bus_addr_t paddr; 1888 1889 error = bus_dmamap_create(ring->data_dmat, 0, &data->map); 1890 if (error != 0) { 1891 device_printf(sc->sc_dev, 1892 "%s: could not create RX buf DMA map, error %d\n", 1893 __func__, error); 1894 goto fail; 1895 } 1896 1897 data->m = m_getjcl(M_NOWAIT, MT_DATA, M_PKTHDR, 1898 IWN_RBUF_SIZE); 1899 if (data->m == NULL) { 1900 device_printf(sc->sc_dev, 1901 "%s: could not allocate RX mbuf\n", __func__); 1902 error = ENOBUFS; 1903 goto fail; 1904 } 1905 1906 error = bus_dmamap_load(ring->data_dmat, data->map, 1907 mtod(data->m, void *), IWN_RBUF_SIZE, iwn_dma_map_addr, 1908 &paddr, BUS_DMA_NOWAIT); 1909 if (error != 0 && error != EFBIG) { 1910 device_printf(sc->sc_dev, 1911 "%s: can't map mbuf, error %d\n", __func__, 1912 error); 1913 goto fail; 1914 } 1915 1916 bus_dmamap_sync(ring->data_dmat, data->map, 1917 BUS_DMASYNC_PREREAD); 1918 1919 /* Set physical address of RX buffer (256-byte aligned). */ 1920 ring->desc[i] = htole32(paddr >> 8); 1921 } 1922 1923 bus_dmamap_sync(ring->desc_dma.tag, ring->desc_dma.map, 1924 BUS_DMASYNC_PREWRITE); 1925 1926 DPRINTF(sc, IWN_DEBUG_TRACE, "->%s: end\n",__func__); 1927 1928 return 0; 1929 1930 fail: iwn_free_rx_ring(sc, ring); 1931 1932 DPRINTF(sc, IWN_DEBUG_TRACE, "->%s: end in error\n",__func__); 1933 1934 return error; 1935 } 1936 1937 static void 1938 iwn_reset_rx_ring(struct iwn_softc *sc, struct iwn_rx_ring *ring) 1939 { 1940 int ntries; 1941 1942 DPRINTF(sc, IWN_DEBUG_TRACE, "->Doing %s\n", __func__); 1943 1944 if (iwn_nic_lock(sc) == 0) { 1945 IWN_WRITE(sc, IWN_FH_RX_CONFIG, 0); 1946 for (ntries = 0; ntries < 1000; ntries++) { 1947 if (IWN_READ(sc, IWN_FH_RX_STATUS) & 1948 IWN_FH_RX_STATUS_IDLE) 1949 break; 1950 DELAY(10); 1951 } 1952 iwn_nic_unlock(sc); 1953 } 1954 ring->cur = 0; 1955 sc->last_rx_valid = 0; 1956 } 1957 1958 static void 1959 iwn_free_rx_ring(struct iwn_softc *sc, struct iwn_rx_ring *ring) 1960 { 1961 int i; 1962 1963 DPRINTF(sc, IWN_DEBUG_TRACE, "->Doing %s \n", __func__); 1964 1965 iwn_dma_contig_free(&ring->desc_dma); 1966 iwn_dma_contig_free(&ring->stat_dma); 1967 1968 for (i = 0; i < IWN_RX_RING_COUNT; i++) { 1969 struct iwn_rx_data *data = &ring->data[i]; 1970 1971 if (data->m != NULL) { 1972 bus_dmamap_sync(ring->data_dmat, data->map, 1973 BUS_DMASYNC_POSTREAD); 1974 bus_dmamap_unload(ring->data_dmat, data->map); 1975 m_freem(data->m); 1976 data->m = NULL; 1977 } 1978 if (data->map != NULL) 1979 bus_dmamap_destroy(ring->data_dmat, data->map); 1980 } 1981 if (ring->data_dmat != NULL) { 1982 bus_dma_tag_destroy(ring->data_dmat); 1983 ring->data_dmat = NULL; 1984 } 1985 } 1986 1987 static int 1988 iwn_alloc_tx_ring(struct iwn_softc *sc, struct iwn_tx_ring *ring, int qid) 1989 { 1990 bus_addr_t paddr; 1991 bus_size_t size; 1992 int i, error; 1993 1994 ring->qid = qid; 1995 ring->queued = 0; 1996 ring->cur = 0; 1997 1998 DPRINTF(sc, IWN_DEBUG_TRACE, "->%s begin\n", __func__); 1999 2000 /* Allocate TX descriptors (256-byte aligned). */ 2001 size = IWN_TX_RING_COUNT * sizeof (struct iwn_tx_desc); 2002 error = iwn_dma_contig_alloc(sc, &ring->desc_dma, (void **)&ring->desc, 2003 size, 256); 2004 if (error != 0) { 2005 device_printf(sc->sc_dev, 2006 "%s: could not allocate TX ring DMA memory, error %d\n", 2007 __func__, error); 2008 goto fail; 2009 } 2010 2011 size = IWN_TX_RING_COUNT * sizeof (struct iwn_tx_cmd); 2012 error = iwn_dma_contig_alloc(sc, &ring->cmd_dma, (void **)&ring->cmd, 2013 size, 4); 2014 if (error != 0) { 2015 device_printf(sc->sc_dev, 2016 "%s: could not allocate TX cmd DMA memory, error %d\n", 2017 __func__, error); 2018 goto fail; 2019 } 2020 2021 error = bus_dma_tag_create(bus_get_dma_tag(sc->sc_dev), 1, 0, 2022 BUS_SPACE_MAXADDR_32BIT, BUS_SPACE_MAXADDR, NULL, NULL, MCLBYTES, 2023 IWN_MAX_SCATTER - 1, MCLBYTES, 0, NULL, NULL, &ring->data_dmat); 2024 if (error != 0) { 2025 device_printf(sc->sc_dev, 2026 "%s: could not create TX buf DMA tag, error %d\n", 2027 __func__, error); 2028 goto fail; 2029 } 2030 2031 paddr = ring->cmd_dma.paddr; 2032 for (i = 0; i < IWN_TX_RING_COUNT; i++) { 2033 struct iwn_tx_data *data = &ring->data[i]; 2034 2035 data->cmd_paddr = paddr; 2036 data->scratch_paddr = paddr + 12; 2037 paddr += sizeof (struct iwn_tx_cmd); 2038 2039 error = bus_dmamap_create(ring->data_dmat, 0, &data->map); 2040 if (error != 0) { 2041 device_printf(sc->sc_dev, 2042 "%s: could not create TX buf DMA map, error %d\n", 2043 __func__, error); 2044 goto fail; 2045 } 2046 } 2047 2048 DPRINTF(sc, IWN_DEBUG_TRACE, "->%s end\n", __func__); 2049 2050 return 0; 2051 2052 fail: iwn_free_tx_ring(sc, ring); 2053 DPRINTF(sc, IWN_DEBUG_TRACE, "->%s end in error\n", __func__); 2054 return error; 2055 } 2056 2057 static void 2058 iwn_reset_tx_ring(struct iwn_softc *sc, struct iwn_tx_ring *ring) 2059 { 2060 int i; 2061 2062 DPRINTF(sc, IWN_DEBUG_TRACE, "->doing %s \n", __func__); 2063 2064 for (i = 0; i < IWN_TX_RING_COUNT; i++) { 2065 struct iwn_tx_data *data = &ring->data[i]; 2066 2067 if (data->m != NULL) { 2068 bus_dmamap_sync(ring->data_dmat, data->map, 2069 BUS_DMASYNC_POSTWRITE); 2070 bus_dmamap_unload(ring->data_dmat, data->map); 2071 m_freem(data->m); 2072 data->m = NULL; 2073 } 2074 if (data->ni != NULL) { 2075 ieee80211_free_node(data->ni); 2076 data->ni = NULL; 2077 } 2078 data->remapped = 0; 2079 data->long_retries = 0; 2080 } 2081 /* Clear TX descriptors. */ 2082 memset(ring->desc, 0, ring->desc_dma.size); 2083 bus_dmamap_sync(ring->desc_dma.tag, ring->desc_dma.map, 2084 BUS_DMASYNC_PREWRITE); 2085 sc->qfullmsk &= ~(1 << ring->qid); 2086 ring->queued = 0; 2087 ring->cur = 0; 2088 } 2089 2090 static void 2091 iwn_free_tx_ring(struct iwn_softc *sc, struct iwn_tx_ring *ring) 2092 { 2093 int i; 2094 2095 DPRINTF(sc, IWN_DEBUG_TRACE, "->Doing %s \n", __func__); 2096 2097 iwn_dma_contig_free(&ring->desc_dma); 2098 iwn_dma_contig_free(&ring->cmd_dma); 2099 2100 for (i = 0; i < IWN_TX_RING_COUNT; i++) { 2101 struct iwn_tx_data *data = &ring->data[i]; 2102 2103 if (data->m != NULL) { 2104 bus_dmamap_sync(ring->data_dmat, data->map, 2105 BUS_DMASYNC_POSTWRITE); 2106 bus_dmamap_unload(ring->data_dmat, data->map); 2107 m_freem(data->m); 2108 } 2109 if (data->map != NULL) 2110 bus_dmamap_destroy(ring->data_dmat, data->map); 2111 } 2112 if (ring->data_dmat != NULL) { 2113 bus_dma_tag_destroy(ring->data_dmat); 2114 ring->data_dmat = NULL; 2115 } 2116 } 2117 2118 static void 2119 iwn_check_tx_ring(struct iwn_softc *sc, int qid) 2120 { 2121 struct iwn_tx_ring *ring = &sc->txq[qid]; 2122 2123 KASSERT(ring->queued >= 0, ("%s: ring->queued (%d) for queue %d < 0!", 2124 __func__, ring->queued, qid)); 2125 2126 if (qid >= sc->firstaggqueue) { 2127 struct iwn_ops *ops = &sc->ops; 2128 struct ieee80211_tx_ampdu *tap = sc->qid2tap[qid]; 2129 2130 if (ring->queued == 0 && !IEEE80211_AMPDU_RUNNING(tap)) { 2131 uint16_t ssn = tap->txa_start & 0xfff; 2132 uint8_t tid = tap->txa_tid; 2133 int *res = tap->txa_private; 2134 2135 iwn_nic_lock(sc); 2136 ops->ampdu_tx_stop(sc, qid, tid, ssn); 2137 iwn_nic_unlock(sc); 2138 2139 sc->qid2tap[qid] = NULL; 2140 free(res, M_DEVBUF); 2141 } 2142 } 2143 2144 if (ring->queued < IWN_TX_RING_LOMARK) { 2145 sc->qfullmsk &= ~(1 << qid); 2146 2147 if (ring->queued == 0) 2148 sc->sc_tx_timer = 0; 2149 else 2150 sc->sc_tx_timer = 5; 2151 } 2152 } 2153 2154 static void 2155 iwn5000_ict_reset(struct iwn_softc *sc) 2156 { 2157 /* Disable interrupts. */ 2158 IWN_WRITE(sc, IWN_INT_MASK, 0); 2159 2160 /* Reset ICT table. */ 2161 memset(sc->ict, 0, IWN_ICT_SIZE); 2162 sc->ict_cur = 0; 2163 2164 bus_dmamap_sync(sc->ict_dma.tag, sc->ict_dma.map, 2165 BUS_DMASYNC_PREWRITE); 2166 2167 /* Set physical address of ICT table (4KB aligned). */ 2168 DPRINTF(sc, IWN_DEBUG_RESET, "%s: enabling ICT\n", __func__); 2169 IWN_WRITE(sc, IWN_DRAM_INT_TBL, IWN_DRAM_INT_TBL_ENABLE | 2170 IWN_DRAM_INT_TBL_WRAP_CHECK | sc->ict_dma.paddr >> 12); 2171 2172 /* Enable periodic RX interrupt. */ 2173 sc->int_mask |= IWN_INT_RX_PERIODIC; 2174 /* Switch to ICT interrupt mode in driver. */ 2175 sc->sc_flags |= IWN_FLAG_USE_ICT; 2176 2177 /* Re-enable interrupts. */ 2178 IWN_WRITE(sc, IWN_INT, 0xffffffff); 2179 IWN_WRITE(sc, IWN_INT_MASK, sc->int_mask); 2180 } 2181 2182 static int 2183 iwn_read_eeprom(struct iwn_softc *sc, uint8_t macaddr[IEEE80211_ADDR_LEN]) 2184 { 2185 struct iwn_ops *ops = &sc->ops; 2186 uint16_t val; 2187 int error; 2188 2189 DPRINTF(sc, IWN_DEBUG_TRACE, "->%s begin\n", __func__); 2190 2191 /* Check whether adapter has an EEPROM or an OTPROM. */ 2192 if (sc->hw_type >= IWN_HW_REV_TYPE_1000 && 2193 (IWN_READ(sc, IWN_OTP_GP) & IWN_OTP_GP_DEV_SEL_OTP)) 2194 sc->sc_flags |= IWN_FLAG_HAS_OTPROM; 2195 DPRINTF(sc, IWN_DEBUG_RESET, "%s found\n", 2196 (sc->sc_flags & IWN_FLAG_HAS_OTPROM) ? "OTPROM" : "EEPROM"); 2197 2198 /* Adapter has to be powered on for EEPROM access to work. */ 2199 if ((error = iwn_apm_init(sc)) != 0) { 2200 device_printf(sc->sc_dev, 2201 "%s: could not power ON adapter, error %d\n", __func__, 2202 error); 2203 return error; 2204 } 2205 2206 if ((IWN_READ(sc, IWN_EEPROM_GP) & 0x7) == 0) { 2207 device_printf(sc->sc_dev, "%s: bad ROM signature\n", __func__); 2208 return EIO; 2209 } 2210 if ((error = iwn_eeprom_lock(sc)) != 0) { 2211 device_printf(sc->sc_dev, "%s: could not lock ROM, error %d\n", 2212 __func__, error); 2213 return error; 2214 } 2215 if (sc->sc_flags & IWN_FLAG_HAS_OTPROM) { 2216 if ((error = iwn_init_otprom(sc)) != 0) { 2217 device_printf(sc->sc_dev, 2218 "%s: could not initialize OTPROM, error %d\n", 2219 __func__, error); 2220 return error; 2221 } 2222 } 2223 2224 iwn_read_prom_data(sc, IWN_EEPROM_SKU_CAP, &val, 2); 2225 DPRINTF(sc, IWN_DEBUG_RESET, "SKU capabilities=0x%04x\n", le16toh(val)); 2226 /* Check if HT support is bonded out. */ 2227 if (val & htole16(IWN_EEPROM_SKU_CAP_11N)) 2228 sc->sc_flags |= IWN_FLAG_HAS_11N; 2229 2230 iwn_read_prom_data(sc, IWN_EEPROM_RFCFG, &val, 2); 2231 sc->rfcfg = le16toh(val); 2232 DPRINTF(sc, IWN_DEBUG_RESET, "radio config=0x%04x\n", sc->rfcfg); 2233 /* Read Tx/Rx chains from ROM unless it's known to be broken. */ 2234 if (sc->txchainmask == 0) 2235 sc->txchainmask = IWN_RFCFG_TXANTMSK(sc->rfcfg); 2236 if (sc->rxchainmask == 0) 2237 sc->rxchainmask = IWN_RFCFG_RXANTMSK(sc->rfcfg); 2238 2239 /* Read MAC address. */ 2240 iwn_read_prom_data(sc, IWN_EEPROM_MAC, macaddr, 6); 2241 2242 /* Read adapter-specific information from EEPROM. */ 2243 ops->read_eeprom(sc); 2244 2245 iwn_apm_stop(sc); /* Power OFF adapter. */ 2246 2247 iwn_eeprom_unlock(sc); 2248 2249 DPRINTF(sc, IWN_DEBUG_TRACE, "->%s end\n", __func__); 2250 2251 return 0; 2252 } 2253 2254 static void 2255 iwn4965_read_eeprom(struct iwn_softc *sc) 2256 { 2257 uint32_t addr; 2258 uint16_t val; 2259 int i; 2260 2261 DPRINTF(sc, IWN_DEBUG_TRACE, "->%s begin\n", __func__); 2262 2263 /* Read regulatory domain (4 ASCII characters). */ 2264 iwn_read_prom_data(sc, IWN4965_EEPROM_DOMAIN, sc->eeprom_domain, 4); 2265 2266 /* Read the list of authorized channels (20MHz & 40MHz). */ 2267 for (i = 0; i < IWN_NBANDS - 1; i++) { 2268 addr = iwn4965_regulatory_bands[i]; 2269 iwn_read_eeprom_channels(sc, i, addr); 2270 } 2271 2272 /* Read maximum allowed TX power for 2GHz and 5GHz bands. */ 2273 iwn_read_prom_data(sc, IWN4965_EEPROM_MAXPOW, &val, 2); 2274 sc->maxpwr2GHz = val & 0xff; 2275 sc->maxpwr5GHz = val >> 8; 2276 /* Check that EEPROM values are within valid range. */ 2277 if (sc->maxpwr5GHz < 20 || sc->maxpwr5GHz > 50) 2278 sc->maxpwr5GHz = 38; 2279 if (sc->maxpwr2GHz < 20 || sc->maxpwr2GHz > 50) 2280 sc->maxpwr2GHz = 38; 2281 DPRINTF(sc, IWN_DEBUG_RESET, "maxpwr 2GHz=%d 5GHz=%d\n", 2282 sc->maxpwr2GHz, sc->maxpwr5GHz); 2283 2284 /* Read samples for each TX power group. */ 2285 iwn_read_prom_data(sc, IWN4965_EEPROM_BANDS, sc->bands, 2286 sizeof sc->bands); 2287 2288 /* Read voltage at which samples were taken. */ 2289 iwn_read_prom_data(sc, IWN4965_EEPROM_VOLTAGE, &val, 2); 2290 sc->eeprom_voltage = (int16_t)le16toh(val); 2291 DPRINTF(sc, IWN_DEBUG_RESET, "voltage=%d (in 0.3V)\n", 2292 sc->eeprom_voltage); 2293 2294 #ifdef IWN_DEBUG 2295 /* Print samples. */ 2296 if (sc->sc_debug & IWN_DEBUG_ANY) { 2297 for (i = 0; i < IWN_NBANDS - 1; i++) 2298 iwn4965_print_power_group(sc, i); 2299 } 2300 #endif 2301 2302 DPRINTF(sc, IWN_DEBUG_TRACE, "->%s end\n", __func__); 2303 } 2304 2305 #ifdef IWN_DEBUG 2306 static void 2307 iwn4965_print_power_group(struct iwn_softc *sc, int i) 2308 { 2309 struct iwn4965_eeprom_band *band = &sc->bands[i]; 2310 struct iwn4965_eeprom_chan_samples *chans = band->chans; 2311 int j, c; 2312 2313 printf("===band %d===\n", i); 2314 printf("chan lo=%d, chan hi=%d\n", band->lo, band->hi); 2315 printf("chan1 num=%d\n", chans[0].num); 2316 for (c = 0; c < 2; c++) { 2317 for (j = 0; j < IWN_NSAMPLES; j++) { 2318 printf("chain %d, sample %d: temp=%d gain=%d " 2319 "power=%d pa_det=%d\n", c, j, 2320 chans[0].samples[c][j].temp, 2321 chans[0].samples[c][j].gain, 2322 chans[0].samples[c][j].power, 2323 chans[0].samples[c][j].pa_det); 2324 } 2325 } 2326 printf("chan2 num=%d\n", chans[1].num); 2327 for (c = 0; c < 2; c++) { 2328 for (j = 0; j < IWN_NSAMPLES; j++) { 2329 printf("chain %d, sample %d: temp=%d gain=%d " 2330 "power=%d pa_det=%d\n", c, j, 2331 chans[1].samples[c][j].temp, 2332 chans[1].samples[c][j].gain, 2333 chans[1].samples[c][j].power, 2334 chans[1].samples[c][j].pa_det); 2335 } 2336 } 2337 } 2338 #endif 2339 2340 static void 2341 iwn5000_read_eeprom(struct iwn_softc *sc) 2342 { 2343 struct iwn5000_eeprom_calib_hdr hdr; 2344 int32_t volt; 2345 uint32_t base, addr; 2346 uint16_t val; 2347 int i; 2348 2349 DPRINTF(sc, IWN_DEBUG_TRACE, "->%s begin\n", __func__); 2350 2351 /* Read regulatory domain (4 ASCII characters). */ 2352 iwn_read_prom_data(sc, IWN5000_EEPROM_REG, &val, 2); 2353 base = le16toh(val); 2354 iwn_read_prom_data(sc, base + IWN5000_EEPROM_DOMAIN, 2355 sc->eeprom_domain, 4); 2356 2357 /* Read the list of authorized channels (20MHz & 40MHz). */ 2358 for (i = 0; i < IWN_NBANDS - 1; i++) { 2359 addr = base + sc->base_params->regulatory_bands[i]; 2360 iwn_read_eeprom_channels(sc, i, addr); 2361 } 2362 2363 /* Read enhanced TX power information for 6000 Series. */ 2364 if (sc->base_params->enhanced_TX_power) 2365 iwn_read_eeprom_enhinfo(sc); 2366 2367 iwn_read_prom_data(sc, IWN5000_EEPROM_CAL, &val, 2); 2368 base = le16toh(val); 2369 iwn_read_prom_data(sc, base, &hdr, sizeof hdr); 2370 DPRINTF(sc, IWN_DEBUG_CALIBRATE, 2371 "%s: calib version=%u pa type=%u voltage=%u\n", __func__, 2372 hdr.version, hdr.pa_type, le16toh(hdr.volt)); 2373 sc->calib_ver = hdr.version; 2374 2375 if (sc->base_params->calib_need & IWN_FLG_NEED_PHY_CALIB_TEMP_OFFSETv2) { 2376 sc->eeprom_voltage = le16toh(hdr.volt); 2377 iwn_read_prom_data(sc, base + IWN5000_EEPROM_TEMP, &val, 2); 2378 sc->eeprom_temp_high=le16toh(val); 2379 iwn_read_prom_data(sc, base + IWN5000_EEPROM_VOLT, &val, 2); 2380 sc->eeprom_temp = le16toh(val); 2381 } 2382 2383 if (sc->hw_type == IWN_HW_REV_TYPE_5150) { 2384 /* Compute temperature offset. */ 2385 iwn_read_prom_data(sc, base + IWN5000_EEPROM_TEMP, &val, 2); 2386 sc->eeprom_temp = le16toh(val); 2387 iwn_read_prom_data(sc, base + IWN5000_EEPROM_VOLT, &val, 2); 2388 volt = le16toh(val); 2389 sc->temp_off = sc->eeprom_temp - (volt / -5); 2390 DPRINTF(sc, IWN_DEBUG_CALIBRATE, "temp=%d volt=%d offset=%dK\n", 2391 sc->eeprom_temp, volt, sc->temp_off); 2392 } else { 2393 /* Read crystal calibration. */ 2394 iwn_read_prom_data(sc, base + IWN5000_EEPROM_CRYSTAL, 2395 &sc->eeprom_crystal, sizeof (uint32_t)); 2396 DPRINTF(sc, IWN_DEBUG_CALIBRATE, "crystal calibration 0x%08x\n", 2397 le32toh(sc->eeprom_crystal)); 2398 } 2399 2400 DPRINTF(sc, IWN_DEBUG_TRACE, "->%s end\n", __func__); 2401 2402 } 2403 2404 /* 2405 * Translate EEPROM flags to net80211. 2406 */ 2407 static uint32_t 2408 iwn_eeprom_channel_flags(struct iwn_eeprom_chan *channel) 2409 { 2410 uint32_t nflags; 2411 2412 nflags = 0; 2413 if ((channel->flags & IWN_EEPROM_CHAN_ACTIVE) == 0) 2414 nflags |= IEEE80211_CHAN_PASSIVE; 2415 if ((channel->flags & IWN_EEPROM_CHAN_IBSS) == 0) 2416 nflags |= IEEE80211_CHAN_NOADHOC; 2417 if (channel->flags & IWN_EEPROM_CHAN_RADAR) { 2418 nflags |= IEEE80211_CHAN_DFS; 2419 /* XXX apparently IBSS may still be marked */ 2420 nflags |= IEEE80211_CHAN_NOADHOC; 2421 } 2422 2423 return nflags; 2424 } 2425 2426 static void 2427 iwn_read_eeprom_band(struct iwn_softc *sc, int n, int maxchans, int *nchans, 2428 struct ieee80211_channel chans[]) 2429 { 2430 struct iwn_eeprom_chan *channels = sc->eeprom_channels[n]; 2431 const struct iwn_chan_band *band = &iwn_bands[n]; 2432 uint8_t bands[IEEE80211_MODE_BYTES]; 2433 uint8_t chan; 2434 int i, error, nflags; 2435 2436 DPRINTF(sc, IWN_DEBUG_TRACE, "->%s begin\n", __func__); 2437 2438 memset(bands, 0, sizeof(bands)); 2439 if (n == 0) { 2440 setbit(bands, IEEE80211_MODE_11B); 2441 setbit(bands, IEEE80211_MODE_11G); 2442 if (sc->sc_flags & IWN_FLAG_HAS_11N) 2443 setbit(bands, IEEE80211_MODE_11NG); 2444 } else { 2445 setbit(bands, IEEE80211_MODE_11A); 2446 if (sc->sc_flags & IWN_FLAG_HAS_11N) 2447 setbit(bands, IEEE80211_MODE_11NA); 2448 } 2449 2450 for (i = 0; i < band->nchan; i++) { 2451 if (!(channels[i].flags & IWN_EEPROM_CHAN_VALID)) { 2452 DPRINTF(sc, IWN_DEBUG_RESET, 2453 "skip chan %d flags 0x%x maxpwr %d\n", 2454 band->chan[i], channels[i].flags, 2455 channels[i].maxpwr); 2456 continue; 2457 } 2458 2459 chan = band->chan[i]; 2460 nflags = iwn_eeprom_channel_flags(&channels[i]); 2461 error = ieee80211_add_channel(chans, maxchans, nchans, 2462 chan, 0, channels[i].maxpwr, nflags, bands); 2463 if (error != 0) 2464 break; 2465 2466 /* Save maximum allowed TX power for this channel. */ 2467 /* XXX wrong */ 2468 sc->maxpwr[chan] = channels[i].maxpwr; 2469 2470 DPRINTF(sc, IWN_DEBUG_RESET, 2471 "add chan %d flags 0x%x maxpwr %d\n", chan, 2472 channels[i].flags, channels[i].maxpwr); 2473 } 2474 2475 DPRINTF(sc, IWN_DEBUG_TRACE, "->%s end\n", __func__); 2476 2477 } 2478 2479 static void 2480 iwn_read_eeprom_ht40(struct iwn_softc *sc, int n, int maxchans, int *nchans, 2481 struct ieee80211_channel chans[]) 2482 { 2483 struct iwn_eeprom_chan *channels = sc->eeprom_channels[n]; 2484 const struct iwn_chan_band *band = &iwn_bands[n]; 2485 uint8_t chan; 2486 int i, error, nflags; 2487 2488 DPRINTF(sc, IWN_DEBUG_TRACE, "->%s start\n", __func__); 2489 2490 if (!(sc->sc_flags & IWN_FLAG_HAS_11N)) { 2491 DPRINTF(sc, IWN_DEBUG_TRACE, "->%s end no 11n\n", __func__); 2492 return; 2493 } 2494 2495 for (i = 0; i < band->nchan; i++) { 2496 if (!(channels[i].flags & IWN_EEPROM_CHAN_VALID)) { 2497 DPRINTF(sc, IWN_DEBUG_RESET, 2498 "skip chan %d flags 0x%x maxpwr %d\n", 2499 band->chan[i], channels[i].flags, 2500 channels[i].maxpwr); 2501 continue; 2502 } 2503 2504 chan = band->chan[i]; 2505 nflags = iwn_eeprom_channel_flags(&channels[i]); 2506 nflags |= (n == 5 ? IEEE80211_CHAN_G : IEEE80211_CHAN_A); 2507 error = ieee80211_add_channel_ht40(chans, maxchans, nchans, 2508 chan, channels[i].maxpwr, nflags); 2509 switch (error) { 2510 case EINVAL: 2511 device_printf(sc->sc_dev, 2512 "%s: no entry for channel %d\n", __func__, chan); 2513 continue; 2514 case ENOENT: 2515 DPRINTF(sc, IWN_DEBUG_RESET, 2516 "%s: skip chan %d, extension channel not found\n", 2517 __func__, chan); 2518 continue; 2519 case ENOBUFS: 2520 device_printf(sc->sc_dev, 2521 "%s: channel table is full!\n", __func__); 2522 break; 2523 case 0: 2524 DPRINTF(sc, IWN_DEBUG_RESET, 2525 "add ht40 chan %d flags 0x%x maxpwr %d\n", 2526 chan, channels[i].flags, channels[i].maxpwr); 2527 /* FALLTHROUGH */ 2528 default: 2529 break; 2530 } 2531 } 2532 2533 DPRINTF(sc, IWN_DEBUG_TRACE, "->%s end\n", __func__); 2534 2535 } 2536 2537 static void 2538 iwn_read_eeprom_channels(struct iwn_softc *sc, int n, uint32_t addr) 2539 { 2540 struct ieee80211com *ic = &sc->sc_ic; 2541 2542 iwn_read_prom_data(sc, addr, &sc->eeprom_channels[n], 2543 iwn_bands[n].nchan * sizeof (struct iwn_eeprom_chan)); 2544 2545 if (n < 5) { 2546 iwn_read_eeprom_band(sc, n, IEEE80211_CHAN_MAX, &ic->ic_nchans, 2547 ic->ic_channels); 2548 } else { 2549 iwn_read_eeprom_ht40(sc, n, IEEE80211_CHAN_MAX, &ic->ic_nchans, 2550 ic->ic_channels); 2551 } 2552 ieee80211_sort_channels(ic->ic_channels, ic->ic_nchans); 2553 } 2554 2555 static struct iwn_eeprom_chan * 2556 iwn_find_eeprom_channel(struct iwn_softc *sc, struct ieee80211_channel *c) 2557 { 2558 int band, chan, i, j; 2559 2560 if (IEEE80211_IS_CHAN_HT40(c)) { 2561 band = IEEE80211_IS_CHAN_5GHZ(c) ? 6 : 5; 2562 if (IEEE80211_IS_CHAN_HT40D(c)) 2563 chan = c->ic_extieee; 2564 else 2565 chan = c->ic_ieee; 2566 for (i = 0; i < iwn_bands[band].nchan; i++) { 2567 if (iwn_bands[band].chan[i] == chan) 2568 return &sc->eeprom_channels[band][i]; 2569 } 2570 } else { 2571 for (j = 0; j < 5; j++) { 2572 for (i = 0; i < iwn_bands[j].nchan; i++) { 2573 if (iwn_bands[j].chan[i] == c->ic_ieee && 2574 ((j == 0) ^ IEEE80211_IS_CHAN_A(c)) == 1) 2575 return &sc->eeprom_channels[j][i]; 2576 } 2577 } 2578 } 2579 return NULL; 2580 } 2581 2582 static void 2583 iwn_getradiocaps(struct ieee80211com *ic, 2584 int maxchans, int *nchans, struct ieee80211_channel chans[]) 2585 { 2586 struct iwn_softc *sc = ic->ic_softc; 2587 int i; 2588 2589 /* Parse the list of authorized channels. */ 2590 for (i = 0; i < 5 && *nchans < maxchans; i++) 2591 iwn_read_eeprom_band(sc, i, maxchans, nchans, chans); 2592 for (i = 5; i < IWN_NBANDS - 1 && *nchans < maxchans; i++) 2593 iwn_read_eeprom_ht40(sc, i, maxchans, nchans, chans); 2594 } 2595 2596 /* 2597 * Enforce flags read from EEPROM. 2598 */ 2599 static int 2600 iwn_setregdomain(struct ieee80211com *ic, struct ieee80211_regdomain *rd, 2601 int nchan, struct ieee80211_channel chans[]) 2602 { 2603 struct iwn_softc *sc = ic->ic_softc; 2604 int i; 2605 2606 for (i = 0; i < nchan; i++) { 2607 struct ieee80211_channel *c = &chans[i]; 2608 struct iwn_eeprom_chan *channel; 2609 2610 channel = iwn_find_eeprom_channel(sc, c); 2611 if (channel == NULL) { 2612 ic_printf(ic, "%s: invalid channel %u freq %u/0x%x\n", 2613 __func__, c->ic_ieee, c->ic_freq, c->ic_flags); 2614 return EINVAL; 2615 } 2616 c->ic_flags |= iwn_eeprom_channel_flags(channel); 2617 } 2618 2619 return 0; 2620 } 2621 2622 static void 2623 iwn_read_eeprom_enhinfo(struct iwn_softc *sc) 2624 { 2625 struct iwn_eeprom_enhinfo enhinfo[35]; 2626 struct ieee80211com *ic = &sc->sc_ic; 2627 struct ieee80211_channel *c; 2628 uint16_t val, base; 2629 int8_t maxpwr; 2630 uint8_t flags; 2631 int i, j; 2632 2633 DPRINTF(sc, IWN_DEBUG_TRACE, "->%s begin\n", __func__); 2634 2635 iwn_read_prom_data(sc, IWN5000_EEPROM_REG, &val, 2); 2636 base = le16toh(val); 2637 iwn_read_prom_data(sc, base + IWN6000_EEPROM_ENHINFO, 2638 enhinfo, sizeof enhinfo); 2639 2640 for (i = 0; i < nitems(enhinfo); i++) { 2641 flags = enhinfo[i].flags; 2642 if (!(flags & IWN_ENHINFO_VALID)) 2643 continue; /* Skip invalid entries. */ 2644 2645 maxpwr = 0; 2646 if (sc->txchainmask & IWN_ANT_A) 2647 maxpwr = MAX(maxpwr, enhinfo[i].chain[0]); 2648 if (sc->txchainmask & IWN_ANT_B) 2649 maxpwr = MAX(maxpwr, enhinfo[i].chain[1]); 2650 if (sc->txchainmask & IWN_ANT_C) 2651 maxpwr = MAX(maxpwr, enhinfo[i].chain[2]); 2652 if (sc->ntxchains == 2) 2653 maxpwr = MAX(maxpwr, enhinfo[i].mimo2); 2654 else if (sc->ntxchains == 3) 2655 maxpwr = MAX(maxpwr, enhinfo[i].mimo3); 2656 2657 for (j = 0; j < ic->ic_nchans; j++) { 2658 c = &ic->ic_channels[j]; 2659 if ((flags & IWN_ENHINFO_5GHZ)) { 2660 if (!IEEE80211_IS_CHAN_A(c)) 2661 continue; 2662 } else if ((flags & IWN_ENHINFO_OFDM)) { 2663 if (!IEEE80211_IS_CHAN_G(c)) 2664 continue; 2665 } else if (!IEEE80211_IS_CHAN_B(c)) 2666 continue; 2667 if ((flags & IWN_ENHINFO_HT40)) { 2668 if (!IEEE80211_IS_CHAN_HT40(c)) 2669 continue; 2670 } else { 2671 if (IEEE80211_IS_CHAN_HT40(c)) 2672 continue; 2673 } 2674 if (enhinfo[i].chan != 0 && 2675 enhinfo[i].chan != c->ic_ieee) 2676 continue; 2677 2678 DPRINTF(sc, IWN_DEBUG_RESET, 2679 "channel %d(%x), maxpwr %d\n", c->ic_ieee, 2680 c->ic_flags, maxpwr / 2); 2681 c->ic_maxregpower = maxpwr / 2; 2682 c->ic_maxpower = maxpwr; 2683 } 2684 } 2685 2686 DPRINTF(sc, IWN_DEBUG_TRACE, "->%s end\n", __func__); 2687 2688 } 2689 2690 static struct ieee80211_node * 2691 iwn_node_alloc(struct ieee80211vap *vap, const uint8_t mac[IEEE80211_ADDR_LEN]) 2692 { 2693 struct iwn_node *wn; 2694 2695 wn = malloc(sizeof (struct iwn_node), M_80211_NODE, M_NOWAIT | M_ZERO); 2696 if (wn == NULL) 2697 return (NULL); 2698 2699 wn->id = IWN_ID_UNDEFINED; 2700 2701 return (&wn->ni); 2702 } 2703 2704 static __inline int 2705 rate2plcp(int rate) 2706 { 2707 switch (rate & 0xff) { 2708 case 12: return 0xd; 2709 case 18: return 0xf; 2710 case 24: return 0x5; 2711 case 36: return 0x7; 2712 case 48: return 0x9; 2713 case 72: return 0xb; 2714 case 96: return 0x1; 2715 case 108: return 0x3; 2716 case 2: return 10; 2717 case 4: return 20; 2718 case 11: return 55; 2719 case 22: return 110; 2720 } 2721 return 0; 2722 } 2723 2724 static __inline uint8_t 2725 plcp2rate(const uint8_t rate_plcp) 2726 { 2727 switch (rate_plcp) { 2728 case 0xd: return 12; 2729 case 0xf: return 18; 2730 case 0x5: return 24; 2731 case 0x7: return 36; 2732 case 0x9: return 48; 2733 case 0xb: return 72; 2734 case 0x1: return 96; 2735 case 0x3: return 108; 2736 case 10: return 2; 2737 case 20: return 4; 2738 case 55: return 11; 2739 case 110: return 22; 2740 default: return 0; 2741 } 2742 } 2743 2744 static int 2745 iwn_get_1stream_tx_antmask(struct iwn_softc *sc) 2746 { 2747 2748 return IWN_LSB(sc->txchainmask); 2749 } 2750 2751 static int 2752 iwn_get_2stream_tx_antmask(struct iwn_softc *sc) 2753 { 2754 int tx; 2755 2756 /* 2757 * The '2 stream' setup is a bit .. odd. 2758 * 2759 * For NICs that support only 1 antenna, default to IWN_ANT_AB or 2760 * the firmware panics (eg Intel 5100.) 2761 * 2762 * For NICs that support two antennas, we use ANT_AB. 2763 * 2764 * For NICs that support three antennas, we use the two that 2765 * wasn't the default one. 2766 * 2767 * XXX TODO: if bluetooth (full concurrent) is enabled, restrict 2768 * this to only one antenna. 2769 */ 2770 2771 /* Default - transmit on the other antennas */ 2772 tx = (sc->txchainmask & ~IWN_LSB(sc->txchainmask)); 2773 2774 /* Now, if it's zero, set it to IWN_ANT_AB, so to not panic firmware */ 2775 if (tx == 0) 2776 tx = IWN_ANT_AB; 2777 2778 /* 2779 * If the NIC is a two-stream TX NIC, configure the TX mask to 2780 * the default chainmask 2781 */ 2782 else if (sc->ntxchains == 2) 2783 tx = sc->txchainmask; 2784 2785 return (tx); 2786 } 2787 2788 2789 2790 /* 2791 * Calculate the required PLCP value from the given rate, 2792 * to the given node. 2793 * 2794 * This will take the node configuration (eg 11n, rate table 2795 * setup, etc) into consideration. 2796 */ 2797 static uint32_t 2798 iwn_rate_to_plcp(struct iwn_softc *sc, struct ieee80211_node *ni, 2799 uint8_t rate) 2800 { 2801 struct ieee80211com *ic = ni->ni_ic; 2802 uint32_t plcp = 0; 2803 int ridx; 2804 2805 /* 2806 * If it's an MCS rate, let's set the plcp correctly 2807 * and set the relevant flags based on the node config. 2808 */ 2809 if (rate & IEEE80211_RATE_MCS) { 2810 /* 2811 * Set the initial PLCP value to be between 0->31 for 2812 * MCS 0 -> MCS 31, then set the "I'm an MCS rate!" 2813 * flag. 2814 */ 2815 plcp = IEEE80211_RV(rate) | IWN_RFLAG_MCS; 2816 2817 /* 2818 * XXX the following should only occur if both 2819 * the local configuration _and_ the remote node 2820 * advertise these capabilities. Thus this code 2821 * may need fixing! 2822 */ 2823 2824 /* 2825 * Set the channel width and guard interval. 2826 */ 2827 if (IEEE80211_IS_CHAN_HT40(ni->ni_chan)) { 2828 plcp |= IWN_RFLAG_HT40; 2829 if (ni->ni_htcap & IEEE80211_HTCAP_SHORTGI40) 2830 plcp |= IWN_RFLAG_SGI; 2831 } else if (ni->ni_htcap & IEEE80211_HTCAP_SHORTGI20) { 2832 plcp |= IWN_RFLAG_SGI; 2833 } 2834 2835 /* 2836 * Ensure the selected rate matches the link quality 2837 * table entries being used. 2838 */ 2839 if (rate > 0x8f) 2840 plcp |= IWN_RFLAG_ANT(sc->txchainmask); 2841 else if (rate > 0x87) 2842 plcp |= IWN_RFLAG_ANT(iwn_get_2stream_tx_antmask(sc)); 2843 else 2844 plcp |= IWN_RFLAG_ANT(iwn_get_1stream_tx_antmask(sc)); 2845 } else { 2846 /* 2847 * Set the initial PLCP - fine for both 2848 * OFDM and CCK rates. 2849 */ 2850 plcp = rate2plcp(rate); 2851 2852 /* Set CCK flag if it's CCK */ 2853 2854 /* XXX It would be nice to have a method 2855 * to map the ridx -> phy table entry 2856 * so we could just query that, rather than 2857 * this hack to check against IWN_RIDX_OFDM6. 2858 */ 2859 ridx = ieee80211_legacy_rate_lookup(ic->ic_rt, 2860 rate & IEEE80211_RATE_VAL); 2861 if (ridx < IWN_RIDX_OFDM6 && 2862 IEEE80211_IS_CHAN_2GHZ(ni->ni_chan)) 2863 plcp |= IWN_RFLAG_CCK; 2864 2865 /* Set antenna configuration */ 2866 /* XXX TODO: is this the right antenna to use for legacy? */ 2867 plcp |= IWN_RFLAG_ANT(iwn_get_1stream_tx_antmask(sc)); 2868 } 2869 2870 DPRINTF(sc, IWN_DEBUG_TXRATE, "%s: rate=0x%02x, plcp=0x%08x\n", 2871 __func__, 2872 rate, 2873 plcp); 2874 2875 return (htole32(plcp)); 2876 } 2877 2878 static void 2879 iwn_newassoc(struct ieee80211_node *ni, int isnew) 2880 { 2881 /* Doesn't do anything at the moment */ 2882 } 2883 2884 static int 2885 iwn_media_change(struct ifnet *ifp) 2886 { 2887 int error; 2888 2889 error = ieee80211_media_change(ifp); 2890 /* NB: only the fixed rate can change and that doesn't need a reset */ 2891 return (error == ENETRESET ? 0 : error); 2892 } 2893 2894 static int 2895 iwn_newstate(struct ieee80211vap *vap, enum ieee80211_state nstate, int arg) 2896 { 2897 struct iwn_vap *ivp = IWN_VAP(vap); 2898 struct ieee80211com *ic = vap->iv_ic; 2899 struct iwn_softc *sc = ic->ic_softc; 2900 int error = 0; 2901 2902 DPRINTF(sc, IWN_DEBUG_TRACE, "->%s begin\n", __func__); 2903 2904 DPRINTF(sc, IWN_DEBUG_STATE, "%s: %s -> %s\n", __func__, 2905 ieee80211_state_name[vap->iv_state], ieee80211_state_name[nstate]); 2906 2907 IEEE80211_UNLOCK(ic); 2908 IWN_LOCK(sc); 2909 callout_stop(&sc->calib_to); 2910 2911 sc->rxon = &sc->rx_on[IWN_RXON_BSS_CTX]; 2912 2913 switch (nstate) { 2914 case IEEE80211_S_ASSOC: 2915 if (vap->iv_state != IEEE80211_S_RUN) 2916 break; 2917 /* FALLTHROUGH */ 2918 case IEEE80211_S_AUTH: 2919 if (vap->iv_state == IEEE80211_S_AUTH) 2920 break; 2921 2922 /* 2923 * !AUTH -> AUTH transition requires state reset to handle 2924 * reassociations correctly. 2925 */ 2926 sc->rxon->associd = 0; 2927 sc->rxon->filter &= ~htole32(IWN_FILTER_BSS); 2928 sc->calib.state = IWN_CALIB_STATE_INIT; 2929 2930 /* Wait until we hear a beacon before we transmit */ 2931 if (IEEE80211_IS_CHAN_PASSIVE(ic->ic_curchan)) 2932 sc->sc_beacon_wait = 1; 2933 2934 if ((error = iwn_auth(sc, vap)) != 0) { 2935 device_printf(sc->sc_dev, 2936 "%s: could not move to auth state\n", __func__); 2937 } 2938 break; 2939 2940 case IEEE80211_S_RUN: 2941 /* 2942 * RUN -> RUN transition; Just restart the timers. 2943 */ 2944 if (vap->iv_state == IEEE80211_S_RUN) { 2945 sc->calib_cnt = 0; 2946 break; 2947 } 2948 2949 /* Wait until we hear a beacon before we transmit */ 2950 if (IEEE80211_IS_CHAN_PASSIVE(ic->ic_curchan)) 2951 sc->sc_beacon_wait = 1; 2952 2953 /* 2954 * !RUN -> RUN requires setting the association id 2955 * which is done with a firmware cmd. We also defer 2956 * starting the timers until that work is done. 2957 */ 2958 if ((error = iwn_run(sc, vap)) != 0) { 2959 device_printf(sc->sc_dev, 2960 "%s: could not move to run state\n", __func__); 2961 } 2962 break; 2963 2964 case IEEE80211_S_INIT: 2965 sc->calib.state = IWN_CALIB_STATE_INIT; 2966 /* 2967 * Purge the xmit queue so we don't have old frames 2968 * during a new association attempt. 2969 */ 2970 sc->sc_beacon_wait = 0; 2971 iwn_xmit_queue_drain(sc); 2972 break; 2973 2974 default: 2975 break; 2976 } 2977 IWN_UNLOCK(sc); 2978 IEEE80211_LOCK(ic); 2979 if (error != 0){ 2980 DPRINTF(sc, IWN_DEBUG_TRACE, "->%s end in error\n", __func__); 2981 return error; 2982 } 2983 2984 DPRINTF(sc, IWN_DEBUG_TRACE, "->%s: end\n",__func__); 2985 2986 return ivp->iv_newstate(vap, nstate, arg); 2987 } 2988 2989 static void 2990 iwn_calib_timeout(void *arg) 2991 { 2992 struct iwn_softc *sc = arg; 2993 2994 IWN_LOCK_ASSERT(sc); 2995 2996 /* Force automatic TX power calibration every 60 secs. */ 2997 if (++sc->calib_cnt >= 120) { 2998 uint32_t flags = 0; 2999 3000 DPRINTF(sc, IWN_DEBUG_CALIBRATE, "%s\n", 3001 "sending request for statistics"); 3002 (void)iwn_cmd(sc, IWN_CMD_GET_STATISTICS, &flags, 3003 sizeof flags, 1); 3004 sc->calib_cnt = 0; 3005 } 3006 callout_reset(&sc->calib_to, msecs_to_ticks(500), iwn_calib_timeout, 3007 sc); 3008 } 3009 3010 /* 3011 * Process an RX_PHY firmware notification. This is usually immediately 3012 * followed by an MPDU_RX_DONE notification. 3013 */ 3014 static void 3015 iwn_rx_phy(struct iwn_softc *sc, struct iwn_rx_desc *desc) 3016 { 3017 struct iwn_rx_stat *stat = (struct iwn_rx_stat *)(desc + 1); 3018 3019 DPRINTF(sc, IWN_DEBUG_CALIBRATE, "%s: received PHY stats\n", __func__); 3020 3021 /* Save RX statistics, they will be used on MPDU_RX_DONE. */ 3022 memcpy(&sc->last_rx_stat, stat, sizeof (*stat)); 3023 sc->last_rx_valid = 1; 3024 } 3025 3026 /* 3027 * Process an RX_DONE (4965AGN only) or MPDU_RX_DONE firmware notification. 3028 * Each MPDU_RX_DONE notification must be preceded by an RX_PHY one. 3029 */ 3030 static void 3031 iwn_rx_done(struct iwn_softc *sc, struct iwn_rx_desc *desc, 3032 struct iwn_rx_data *data) 3033 { 3034 struct iwn_ops *ops = &sc->ops; 3035 struct ieee80211com *ic = &sc->sc_ic; 3036 struct iwn_rx_ring *ring = &sc->rxq; 3037 struct ieee80211_frame_min *wh; 3038 struct ieee80211_node *ni; 3039 struct mbuf *m, *m1; 3040 struct iwn_rx_stat *stat; 3041 caddr_t head; 3042 bus_addr_t paddr; 3043 uint32_t flags; 3044 int error, len, rssi, nf; 3045 3046 DPRINTF(sc, IWN_DEBUG_TRACE, "->%s begin\n", __func__); 3047 3048 if (desc->type == IWN_MPDU_RX_DONE) { 3049 /* Check for prior RX_PHY notification. */ 3050 if (!sc->last_rx_valid) { 3051 DPRINTF(sc, IWN_DEBUG_ANY, 3052 "%s: missing RX_PHY\n", __func__); 3053 return; 3054 } 3055 stat = &sc->last_rx_stat; 3056 } else 3057 stat = (struct iwn_rx_stat *)(desc + 1); 3058 3059 if (stat->cfg_phy_len > IWN_STAT_MAXLEN) { 3060 device_printf(sc->sc_dev, 3061 "%s: invalid RX statistic header, len %d\n", __func__, 3062 stat->cfg_phy_len); 3063 return; 3064 } 3065 if (desc->type == IWN_MPDU_RX_DONE) { 3066 struct iwn_rx_mpdu *mpdu = (struct iwn_rx_mpdu *)(desc + 1); 3067 head = (caddr_t)(mpdu + 1); 3068 len = le16toh(mpdu->len); 3069 } else { 3070 head = (caddr_t)(stat + 1) + stat->cfg_phy_len; 3071 len = le16toh(stat->len); 3072 } 3073 3074 flags = le32toh(*(uint32_t *)(head + len)); 3075 3076 /* Discard frames with a bad FCS early. */ 3077 if ((flags & IWN_RX_NOERROR) != IWN_RX_NOERROR) { 3078 DPRINTF(sc, IWN_DEBUG_RECV, "%s: RX flags error %x\n", 3079 __func__, flags); 3080 counter_u64_add(ic->ic_ierrors, 1); 3081 return; 3082 } 3083 /* Discard frames that are too short. */ 3084 if (len < sizeof (struct ieee80211_frame_ack)) { 3085 DPRINTF(sc, IWN_DEBUG_RECV, "%s: frame too short: %d\n", 3086 __func__, len); 3087 counter_u64_add(ic->ic_ierrors, 1); 3088 return; 3089 } 3090 3091 m1 = m_getjcl(M_NOWAIT, MT_DATA, M_PKTHDR, IWN_RBUF_SIZE); 3092 if (m1 == NULL) { 3093 DPRINTF(sc, IWN_DEBUG_ANY, "%s: no mbuf to restock ring\n", 3094 __func__); 3095 counter_u64_add(ic->ic_ierrors, 1); 3096 return; 3097 } 3098 bus_dmamap_unload(ring->data_dmat, data->map); 3099 3100 error = bus_dmamap_load(ring->data_dmat, data->map, mtod(m1, void *), 3101 IWN_RBUF_SIZE, iwn_dma_map_addr, &paddr, BUS_DMA_NOWAIT); 3102 if (error != 0 && error != EFBIG) { 3103 device_printf(sc->sc_dev, 3104 "%s: bus_dmamap_load failed, error %d\n", __func__, error); 3105 m_freem(m1); 3106 3107 /* Try to reload the old mbuf. */ 3108 error = bus_dmamap_load(ring->data_dmat, data->map, 3109 mtod(data->m, void *), IWN_RBUF_SIZE, iwn_dma_map_addr, 3110 &paddr, BUS_DMA_NOWAIT); 3111 if (error != 0 && error != EFBIG) { 3112 panic("%s: could not load old RX mbuf", __func__); 3113 } 3114 bus_dmamap_sync(ring->data_dmat, data->map, 3115 BUS_DMASYNC_PREREAD); 3116 /* Physical address may have changed. */ 3117 ring->desc[ring->cur] = htole32(paddr >> 8); 3118 bus_dmamap_sync(ring->desc_dma.tag, ring->desc_dma.map, 3119 BUS_DMASYNC_PREWRITE); 3120 counter_u64_add(ic->ic_ierrors, 1); 3121 return; 3122 } 3123 3124 bus_dmamap_sync(ring->data_dmat, data->map, 3125 BUS_DMASYNC_PREREAD); 3126 3127 m = data->m; 3128 data->m = m1; 3129 /* Update RX descriptor. */ 3130 ring->desc[ring->cur] = htole32(paddr >> 8); 3131 bus_dmamap_sync(ring->desc_dma.tag, ring->desc_dma.map, 3132 BUS_DMASYNC_PREWRITE); 3133 3134 /* Finalize mbuf. */ 3135 m->m_data = head; 3136 m->m_pkthdr.len = m->m_len = len; 3137 3138 /* Grab a reference to the source node. */ 3139 wh = mtod(m, struct ieee80211_frame_min *); 3140 if (len >= sizeof(struct ieee80211_frame_min)) 3141 ni = ieee80211_find_rxnode(ic, wh); 3142 else 3143 ni = NULL; 3144 nf = (ni != NULL && ni->ni_vap->iv_state == IEEE80211_S_RUN && 3145 (ic->ic_flags & IEEE80211_F_SCAN) == 0) ? sc->noise : -95; 3146 3147 rssi = ops->get_rssi(sc, stat); 3148 3149 if (ieee80211_radiotap_active(ic)) { 3150 struct iwn_rx_radiotap_header *tap = &sc->sc_rxtap; 3151 uint32_t rate = le32toh(stat->rate); 3152 3153 tap->wr_flags = 0; 3154 if (stat->flags & htole16(IWN_STAT_FLAG_SHPREAMBLE)) 3155 tap->wr_flags |= IEEE80211_RADIOTAP_F_SHORTPRE; 3156 tap->wr_dbm_antsignal = (int8_t)rssi; 3157 tap->wr_dbm_antnoise = (int8_t)nf; 3158 tap->wr_tsft = stat->tstamp; 3159 if (rate & IWN_RFLAG_MCS) { 3160 tap->wr_rate = rate & IWN_RFLAG_RATE_MCS; 3161 tap->wr_rate |= IEEE80211_RATE_MCS; 3162 } else 3163 tap->wr_rate = plcp2rate(rate & IWN_RFLAG_RATE); 3164 } 3165 3166 /* 3167 * If it's a beacon and we're waiting, then do the 3168 * wakeup. This should unblock raw_xmit/start. 3169 */ 3170 if (sc->sc_beacon_wait) { 3171 uint8_t type, subtype; 3172 /* NB: Re-assign wh */ 3173 wh = mtod(m, struct ieee80211_frame_min *); 3174 type = wh->i_fc[0] & IEEE80211_FC0_TYPE_MASK; 3175 subtype = wh->i_fc[0] & IEEE80211_FC0_SUBTYPE_MASK; 3176 /* 3177 * This assumes at this point we've received our own 3178 * beacon. 3179 */ 3180 DPRINTF(sc, IWN_DEBUG_TRACE, 3181 "%s: beacon_wait, type=%d, subtype=%d\n", 3182 __func__, type, subtype); 3183 if (type == IEEE80211_FC0_TYPE_MGT && 3184 subtype == IEEE80211_FC0_SUBTYPE_BEACON) { 3185 DPRINTF(sc, IWN_DEBUG_TRACE | IWN_DEBUG_XMIT, 3186 "%s: waking things up\n", __func__); 3187 /* queue taskqueue to transmit! */ 3188 taskqueue_enqueue(sc->sc_tq, &sc->sc_xmit_task); 3189 } 3190 } 3191 3192 IWN_UNLOCK(sc); 3193 3194 /* Send the frame to the 802.11 layer. */ 3195 if (ni != NULL) { 3196 if (ni->ni_flags & IEEE80211_NODE_HT) 3197 m->m_flags |= M_AMPDU; 3198 (void)ieee80211_input(ni, m, rssi - nf, nf); 3199 /* Node is no longer needed. */ 3200 ieee80211_free_node(ni); 3201 } else 3202 (void)ieee80211_input_all(ic, m, rssi - nf, nf); 3203 3204 IWN_LOCK(sc); 3205 3206 DPRINTF(sc, IWN_DEBUG_TRACE, "->%s: end\n",__func__); 3207 3208 } 3209 3210 static void 3211 iwn_agg_tx_complete(struct iwn_softc *sc, struct iwn_tx_ring *ring, int tid, 3212 int idx, int success) 3213 { 3214 struct ieee80211_ratectl_tx_status *txs = &sc->sc_txs; 3215 struct iwn_tx_data *data = &ring->data[idx]; 3216 struct iwn_node *wn; 3217 struct mbuf *m; 3218 struct ieee80211_node *ni; 3219 3220 KASSERT(data->ni != NULL, ("idx %d: no node", idx)); 3221 KASSERT(data->m != NULL, ("idx %d: no mbuf", idx)); 3222 3223 /* Unmap and free mbuf. */ 3224 bus_dmamap_sync(ring->data_dmat, data->map, 3225 BUS_DMASYNC_POSTWRITE); 3226 bus_dmamap_unload(ring->data_dmat, data->map); 3227 m = data->m, data->m = NULL; 3228 ni = data->ni, data->ni = NULL; 3229 wn = (void *)ni; 3230 3231 #if 0 3232 /* XXX causes significant performance degradation. */ 3233 txs->flags = IEEE80211_RATECTL_STATUS_SHORT_RETRY | 3234 IEEE80211_RATECTL_STATUS_LONG_RETRY; 3235 txs->long_retries = data->long_retries - 1; 3236 #else 3237 txs->flags = IEEE80211_RATECTL_STATUS_SHORT_RETRY; 3238 #endif 3239 txs->short_retries = wn->agg[tid].short_retries; 3240 if (success) 3241 txs->status = IEEE80211_RATECTL_TX_SUCCESS; 3242 else 3243 txs->status = IEEE80211_RATECTL_TX_FAIL_UNSPECIFIED; 3244 3245 wn->agg[tid].short_retries = 0; 3246 data->long_retries = 0; 3247 3248 DPRINTF(sc, IWN_DEBUG_AMPDU, "%s: freeing m %p ni %p idx %d qid %d\n", 3249 __func__, m, ni, idx, ring->qid); 3250 ieee80211_ratectl_tx_complete(ni, txs); 3251 ieee80211_tx_complete(ni, m, !success); 3252 } 3253 3254 /* Process an incoming Compressed BlockAck. */ 3255 static void 3256 iwn_rx_compressed_ba(struct iwn_softc *sc, struct iwn_rx_desc *desc) 3257 { 3258 struct iwn_tx_ring *ring; 3259 struct iwn_tx_data *data; 3260 struct iwn_node *wn; 3261 struct iwn_compressed_ba *ba = (struct iwn_compressed_ba *)(desc + 1); 3262 struct ieee80211_tx_ampdu *tap; 3263 uint64_t bitmap; 3264 uint8_t tid; 3265 int i, qid, shift; 3266 int tx_ok = 0; 3267 3268 DPRINTF(sc, IWN_DEBUG_TRACE, "->%s begin\n", __func__); 3269 3270 qid = le16toh(ba->qid); 3271 tap = sc->qid2tap[qid]; 3272 ring = &sc->txq[qid]; 3273 tid = tap->txa_tid; 3274 wn = (void *)tap->txa_ni; 3275 3276 DPRINTF(sc, IWN_DEBUG_AMPDU, "%s: qid %d tid %d seq %04X ssn %04X\n" 3277 "bitmap: ba %016jX wn %016jX, start %d\n", 3278 __func__, qid, tid, le16toh(ba->seq), le16toh(ba->ssn), 3279 (uintmax_t)le64toh(ba->bitmap), (uintmax_t)wn->agg[tid].bitmap, 3280 wn->agg[tid].startidx); 3281 3282 if (wn->agg[tid].bitmap == 0) 3283 return; 3284 3285 shift = wn->agg[tid].startidx - ((le16toh(ba->seq) >> 4) & 0xff); 3286 if (shift <= -64) 3287 shift += 0x100; 3288 3289 /* 3290 * Walk the bitmap and calculate how many successful attempts 3291 * are made. 3292 * 3293 * Yes, the rate control code doesn't know these are A-MPDU 3294 * subframes; due to that long_retries stats are not used here. 3295 */ 3296 bitmap = le64toh(ba->bitmap); 3297 if (shift >= 0) 3298 bitmap >>= shift; 3299 else 3300 bitmap <<= -shift; 3301 bitmap &= wn->agg[tid].bitmap; 3302 wn->agg[tid].bitmap = 0; 3303 3304 for (i = wn->agg[tid].startidx; 3305 bitmap; 3306 bitmap >>= 1, i = (i + 1) % IWN_TX_RING_COUNT) { 3307 if ((bitmap & 1) == 0) 3308 continue; 3309 3310 data = &ring->data[i]; 3311 if (__predict_false(data->m == NULL)) { 3312 /* 3313 * There is no frame; skip this entry. 3314 * 3315 * NB: it is "ok" to have both 3316 * 'tx done' + 'compressed BA' replies for frame 3317 * with STATE_SCD_QUERY status. 3318 */ 3319 DPRINTF(sc, IWN_DEBUG_AMPDU, 3320 "%s: ring %d: no entry %d\n", __func__, qid, i); 3321 continue; 3322 } 3323 3324 tx_ok++; 3325 iwn_agg_tx_complete(sc, ring, tid, i, 1); 3326 } 3327 3328 ring->queued -= tx_ok; 3329 iwn_check_tx_ring(sc, qid); 3330 3331 DPRINTF(sc, IWN_DEBUG_TRACE | IWN_DEBUG_AMPDU, 3332 "->%s: end; %d ok\n",__func__, tx_ok); 3333 } 3334 3335 /* 3336 * Process a CALIBRATION_RESULT notification sent by the initialization 3337 * firmware on response to a CMD_CALIB_CONFIG command (5000 only). 3338 */ 3339 static void 3340 iwn5000_rx_calib_results(struct iwn_softc *sc, struct iwn_rx_desc *desc) 3341 { 3342 struct iwn_phy_calib *calib = (struct iwn_phy_calib *)(desc + 1); 3343 int len, idx = -1; 3344 3345 DPRINTF(sc, IWN_DEBUG_TRACE, "->%s begin\n", __func__); 3346 3347 /* Runtime firmware should not send such a notification. */ 3348 if (sc->sc_flags & IWN_FLAG_CALIB_DONE){ 3349 DPRINTF(sc, IWN_DEBUG_TRACE, 3350 "->%s received after calib done\n", __func__); 3351 return; 3352 } 3353 len = (le32toh(desc->len) & 0x3fff) - 4; 3354 3355 switch (calib->code) { 3356 case IWN5000_PHY_CALIB_DC: 3357 if (sc->base_params->calib_need & IWN_FLG_NEED_PHY_CALIB_DC) 3358 idx = 0; 3359 break; 3360 case IWN5000_PHY_CALIB_LO: 3361 if (sc->base_params->calib_need & IWN_FLG_NEED_PHY_CALIB_LO) 3362 idx = 1; 3363 break; 3364 case IWN5000_PHY_CALIB_TX_IQ: 3365 if (sc->base_params->calib_need & IWN_FLG_NEED_PHY_CALIB_TX_IQ) 3366 idx = 2; 3367 break; 3368 case IWN5000_PHY_CALIB_TX_IQ_PERIODIC: 3369 if (sc->base_params->calib_need & IWN_FLG_NEED_PHY_CALIB_TX_IQ_PERIODIC) 3370 idx = 3; 3371 break; 3372 case IWN5000_PHY_CALIB_BASE_BAND: 3373 if (sc->base_params->calib_need & IWN_FLG_NEED_PHY_CALIB_BASE_BAND) 3374 idx = 4; 3375 break; 3376 } 3377 if (idx == -1) /* Ignore other results. */ 3378 return; 3379 3380 /* Save calibration result. */ 3381 if (sc->calibcmd[idx].buf != NULL) 3382 free(sc->calibcmd[idx].buf, M_DEVBUF); 3383 sc->calibcmd[idx].buf = malloc(len, M_DEVBUF, M_NOWAIT); 3384 if (sc->calibcmd[idx].buf == NULL) { 3385 DPRINTF(sc, IWN_DEBUG_CALIBRATE, 3386 "not enough memory for calibration result %d\n", 3387 calib->code); 3388 return; 3389 } 3390 DPRINTF(sc, IWN_DEBUG_CALIBRATE, 3391 "saving calibration result idx=%d, code=%d len=%d\n", idx, calib->code, len); 3392 sc->calibcmd[idx].len = len; 3393 memcpy(sc->calibcmd[idx].buf, calib, len); 3394 } 3395 3396 static void 3397 iwn_stats_update(struct iwn_softc *sc, struct iwn_calib_state *calib, 3398 struct iwn_stats *stats, int len) 3399 { 3400 struct iwn_stats_bt *stats_bt; 3401 struct iwn_stats *lstats; 3402 3403 /* 3404 * First - check whether the length is the bluetooth or normal. 3405 * 3406 * If it's normal - just copy it and bump out. 3407 * Otherwise we have to convert things. 3408 */ 3409 3410 if (len == sizeof(struct iwn_stats) + 4) { 3411 memcpy(&sc->last_stat, stats, sizeof(struct iwn_stats)); 3412 sc->last_stat_valid = 1; 3413 return; 3414 } 3415 3416 /* 3417 * If it's not the bluetooth size - log, then just copy. 3418 */ 3419 if (len != sizeof(struct iwn_stats_bt) + 4) { 3420 DPRINTF(sc, IWN_DEBUG_STATS, 3421 "%s: size of rx statistics (%d) not an expected size!\n", 3422 __func__, 3423 len); 3424 memcpy(&sc->last_stat, stats, sizeof(struct iwn_stats)); 3425 sc->last_stat_valid = 1; 3426 return; 3427 } 3428 3429 /* 3430 * Ok. Time to copy. 3431 */ 3432 stats_bt = (struct iwn_stats_bt *) stats; 3433 lstats = &sc->last_stat; 3434 3435 /* flags */ 3436 lstats->flags = stats_bt->flags; 3437 /* rx_bt */ 3438 memcpy(&lstats->rx.ofdm, &stats_bt->rx_bt.ofdm, 3439 sizeof(struct iwn_rx_phy_stats)); 3440 memcpy(&lstats->rx.cck, &stats_bt->rx_bt.cck, 3441 sizeof(struct iwn_rx_phy_stats)); 3442 memcpy(&lstats->rx.general, &stats_bt->rx_bt.general_bt.common, 3443 sizeof(struct iwn_rx_general_stats)); 3444 memcpy(&lstats->rx.ht, &stats_bt->rx_bt.ht, 3445 sizeof(struct iwn_rx_ht_phy_stats)); 3446 /* tx */ 3447 memcpy(&lstats->tx, &stats_bt->tx, 3448 sizeof(struct iwn_tx_stats)); 3449 /* general */ 3450 memcpy(&lstats->general, &stats_bt->general, 3451 sizeof(struct iwn_general_stats)); 3452 3453 /* XXX TODO: Squirrel away the extra bluetooth stats somewhere */ 3454 sc->last_stat_valid = 1; 3455 } 3456 3457 /* 3458 * Process an RX_STATISTICS or BEACON_STATISTICS firmware notification. 3459 * The latter is sent by the firmware after each received beacon. 3460 */ 3461 static void 3462 iwn_rx_statistics(struct iwn_softc *sc, struct iwn_rx_desc *desc) 3463 { 3464 struct iwn_ops *ops = &sc->ops; 3465 struct ieee80211com *ic = &sc->sc_ic; 3466 struct ieee80211vap *vap = TAILQ_FIRST(&ic->ic_vaps); 3467 struct iwn_calib_state *calib = &sc->calib; 3468 struct iwn_stats *stats = (struct iwn_stats *)(desc + 1); 3469 struct iwn_stats *lstats; 3470 int temp; 3471 3472 DPRINTF(sc, IWN_DEBUG_TRACE, "->%s begin\n", __func__); 3473 3474 /* Ignore statistics received during a scan. */ 3475 if (vap->iv_state != IEEE80211_S_RUN || 3476 (ic->ic_flags & IEEE80211_F_SCAN)){ 3477 DPRINTF(sc, IWN_DEBUG_TRACE, "->%s received during calib\n", 3478 __func__); 3479 return; 3480 } 3481 3482 DPRINTF(sc, IWN_DEBUG_CALIBRATE | IWN_DEBUG_STATS, 3483 "%s: received statistics, cmd %d, len %d\n", 3484 __func__, desc->type, le16toh(desc->len)); 3485 sc->calib_cnt = 0; /* Reset TX power calibration timeout. */ 3486 3487 /* 3488 * Collect/track general statistics for reporting. 3489 * 3490 * This takes care of ensuring that the bluetooth sized message 3491 * will be correctly converted to the legacy sized message. 3492 */ 3493 iwn_stats_update(sc, calib, stats, le16toh(desc->len)); 3494 3495 /* 3496 * And now, let's take a reference of it to use! 3497 */ 3498 lstats = &sc->last_stat; 3499 3500 /* Test if temperature has changed. */ 3501 if (lstats->general.temp != sc->rawtemp) { 3502 /* Convert "raw" temperature to degC. */ 3503 sc->rawtemp = stats->general.temp; 3504 temp = ops->get_temperature(sc); 3505 DPRINTF(sc, IWN_DEBUG_CALIBRATE, "%s: temperature %d\n", 3506 __func__, temp); 3507 3508 /* Update TX power if need be (4965AGN only). */ 3509 if (sc->hw_type == IWN_HW_REV_TYPE_4965) 3510 iwn4965_power_calibration(sc, temp); 3511 } 3512 3513 if (desc->type != IWN_BEACON_STATISTICS) 3514 return; /* Reply to a statistics request. */ 3515 3516 sc->noise = iwn_get_noise(&lstats->rx.general); 3517 DPRINTF(sc, IWN_DEBUG_CALIBRATE, "%s: noise %d\n", __func__, sc->noise); 3518 3519 /* Test that RSSI and noise are present in stats report. */ 3520 if (le32toh(lstats->rx.general.flags) != 1) { 3521 DPRINTF(sc, IWN_DEBUG_ANY, "%s\n", 3522 "received statistics without RSSI"); 3523 return; 3524 } 3525 3526 if (calib->state == IWN_CALIB_STATE_ASSOC) 3527 iwn_collect_noise(sc, &lstats->rx.general); 3528 else if (calib->state == IWN_CALIB_STATE_RUN) { 3529 iwn_tune_sensitivity(sc, &lstats->rx); 3530 /* 3531 * XXX TODO: Only run the RX recovery if we're associated! 3532 */ 3533 iwn_check_rx_recovery(sc, lstats); 3534 iwn_save_stats_counters(sc, lstats); 3535 } 3536 3537 DPRINTF(sc, IWN_DEBUG_TRACE, "->%s: end\n",__func__); 3538 } 3539 3540 /* 3541 * Save the relevant statistic counters for the next calibration 3542 * pass. 3543 */ 3544 static void 3545 iwn_save_stats_counters(struct iwn_softc *sc, const struct iwn_stats *rs) 3546 { 3547 struct iwn_calib_state *calib = &sc->calib; 3548 3549 /* Save counters values for next call. */ 3550 calib->bad_plcp_cck = le32toh(rs->rx.cck.bad_plcp); 3551 calib->fa_cck = le32toh(rs->rx.cck.fa); 3552 calib->bad_plcp_ht = le32toh(rs->rx.ht.bad_plcp); 3553 calib->bad_plcp_ofdm = le32toh(rs->rx.ofdm.bad_plcp); 3554 calib->fa_ofdm = le32toh(rs->rx.ofdm.fa); 3555 3556 /* Last time we received these tick values */ 3557 sc->last_calib_ticks = ticks; 3558 } 3559 3560 /* 3561 * Process a TX_DONE firmware notification. Unfortunately, the 4965AGN 3562 * and 5000 adapters have different incompatible TX status formats. 3563 */ 3564 static void 3565 iwn4965_tx_done(struct iwn_softc *sc, struct iwn_rx_desc *desc, 3566 struct iwn_rx_data *data) 3567 { 3568 struct iwn4965_tx_stat *stat = (struct iwn4965_tx_stat *)(desc + 1); 3569 int qid = desc->qid & IWN_RX_DESC_QID_MSK; 3570 3571 DPRINTF(sc, IWN_DEBUG_XMIT, "%s: " 3572 "qid %d idx %d RTS retries %d ACK retries %d nkill %d rate %x duration %d status %x\n", 3573 __func__, desc->qid, desc->idx, 3574 stat->rtsfailcnt, 3575 stat->ackfailcnt, 3576 stat->btkillcnt, 3577 stat->rate, le16toh(stat->duration), 3578 le32toh(stat->status)); 3579 3580 if (qid >= sc->firstaggqueue && stat->nframes != 1) { 3581 iwn_ampdu_tx_done(sc, qid, stat->nframes, stat->rtsfailcnt, 3582 &stat->status); 3583 } else { 3584 iwn_tx_done(sc, desc, stat->rtsfailcnt, stat->ackfailcnt, 3585 le32toh(stat->status) & 0xff); 3586 } 3587 } 3588 3589 static void 3590 iwn5000_tx_done(struct iwn_softc *sc, struct iwn_rx_desc *desc, 3591 struct iwn_rx_data *data) 3592 { 3593 struct iwn5000_tx_stat *stat = (struct iwn5000_tx_stat *)(desc + 1); 3594 int qid = desc->qid & IWN_RX_DESC_QID_MSK; 3595 3596 DPRINTF(sc, IWN_DEBUG_XMIT, "%s: " 3597 "qid %d idx %d RTS retries %d ACK retries %d nkill %d rate %x duration %d status %x\n", 3598 __func__, desc->qid, desc->idx, 3599 stat->rtsfailcnt, 3600 stat->ackfailcnt, 3601 stat->btkillcnt, 3602 stat->rate, le16toh(stat->duration), 3603 le32toh(stat->status)); 3604 3605 #ifdef notyet 3606 /* Reset TX scheduler slot. */ 3607 iwn5000_reset_sched(sc, qid, desc->idx); 3608 #endif 3609 3610 if (qid >= sc->firstaggqueue && stat->nframes != 1) { 3611 iwn_ampdu_tx_done(sc, qid, stat->nframes, stat->rtsfailcnt, 3612 &stat->status); 3613 } else { 3614 iwn_tx_done(sc, desc, stat->rtsfailcnt, stat->ackfailcnt, 3615 le16toh(stat->status) & 0xff); 3616 } 3617 } 3618 3619 static void 3620 iwn_adj_ampdu_ptr(struct iwn_softc *sc, struct iwn_tx_ring *ring) 3621 { 3622 int i; 3623 3624 for (i = ring->read; i != ring->cur; i = (i + 1) % IWN_TX_RING_COUNT) { 3625 struct iwn_tx_data *data = &ring->data[i]; 3626 3627 if (data->m != NULL) 3628 break; 3629 3630 data->remapped = 0; 3631 } 3632 3633 ring->read = i; 3634 } 3635 3636 /* 3637 * Adapter-independent backend for TX_DONE firmware notifications. 3638 */ 3639 static void 3640 iwn_tx_done(struct iwn_softc *sc, struct iwn_rx_desc *desc, int rtsfailcnt, 3641 int ackfailcnt, uint8_t status) 3642 { 3643 struct ieee80211_ratectl_tx_status *txs = &sc->sc_txs; 3644 struct iwn_tx_ring *ring = &sc->txq[desc->qid & IWN_RX_DESC_QID_MSK]; 3645 struct iwn_tx_data *data = &ring->data[desc->idx]; 3646 struct mbuf *m; 3647 struct ieee80211_node *ni; 3648 3649 if (__predict_false(data->m == NULL && 3650 ring->qid >= sc->firstaggqueue)) { 3651 /* 3652 * There is no frame; skip this entry. 3653 */ 3654 DPRINTF(sc, IWN_DEBUG_AMPDU, "%s: ring %d: no entry %d\n", 3655 __func__, ring->qid, desc->idx); 3656 return; 3657 } 3658 3659 KASSERT(data->ni != NULL, ("no node")); 3660 KASSERT(data->m != NULL, ("no mbuf")); 3661 3662 DPRINTF(sc, IWN_DEBUG_TRACE, "->%s begin\n", __func__); 3663 3664 /* Unmap and free mbuf. */ 3665 bus_dmamap_sync(ring->data_dmat, data->map, BUS_DMASYNC_POSTWRITE); 3666 bus_dmamap_unload(ring->data_dmat, data->map); 3667 m = data->m, data->m = NULL; 3668 ni = data->ni, data->ni = NULL; 3669 3670 data->long_retries = 0; 3671 3672 if (ring->qid >= sc->firstaggqueue) 3673 iwn_adj_ampdu_ptr(sc, ring); 3674 3675 /* 3676 * XXX f/w may hang (device timeout) when desc->idx - ring->read == 64 3677 * (aggregation queues only). 3678 */ 3679 3680 ring->queued--; 3681 iwn_check_tx_ring(sc, ring->qid); 3682 3683 /* 3684 * Update rate control statistics for the node. 3685 */ 3686 txs->flags = IEEE80211_RATECTL_STATUS_SHORT_RETRY | 3687 IEEE80211_RATECTL_STATUS_LONG_RETRY; 3688 txs->short_retries = rtsfailcnt; 3689 txs->long_retries = ackfailcnt; 3690 if (!(status & IWN_TX_FAIL)) 3691 txs->status = IEEE80211_RATECTL_TX_SUCCESS; 3692 else { 3693 switch (status) { 3694 case IWN_TX_FAIL_SHORT_LIMIT: 3695 txs->status = IEEE80211_RATECTL_TX_FAIL_SHORT; 3696 break; 3697 case IWN_TX_FAIL_LONG_LIMIT: 3698 txs->status = IEEE80211_RATECTL_TX_FAIL_LONG; 3699 break; 3700 case IWN_TX_STATUS_FAIL_LIFE_EXPIRE: 3701 txs->status = IEEE80211_RATECTL_TX_FAIL_EXPIRED; 3702 break; 3703 default: 3704 txs->status = IEEE80211_RATECTL_TX_FAIL_UNSPECIFIED; 3705 break; 3706 } 3707 } 3708 ieee80211_ratectl_tx_complete(ni, txs); 3709 3710 /* 3711 * Channels marked for "radar" require traffic to be received 3712 * to unlock before we can transmit. Until traffic is seen 3713 * any attempt to transmit is returned immediately with status 3714 * set to IWN_TX_FAIL_TX_LOCKED. Unfortunately this can easily 3715 * happen on first authenticate after scanning. To workaround 3716 * this we ignore a failure of this sort in AUTH state so the 3717 * 802.11 layer will fall back to using a timeout to wait for 3718 * the AUTH reply. This allows the firmware time to see 3719 * traffic so a subsequent retry of AUTH succeeds. It's 3720 * unclear why the firmware does not maintain state for 3721 * channels recently visited as this would allow immediate 3722 * use of the channel after a scan (where we see traffic). 3723 */ 3724 if (status == IWN_TX_FAIL_TX_LOCKED && 3725 ni->ni_vap->iv_state == IEEE80211_S_AUTH) 3726 ieee80211_tx_complete(ni, m, 0); 3727 else 3728 ieee80211_tx_complete(ni, m, 3729 (status & IWN_TX_FAIL) != 0); 3730 3731 DPRINTF(sc, IWN_DEBUG_TRACE, "->%s: end\n",__func__); 3732 } 3733 3734 /* 3735 * Process a "command done" firmware notification. This is where we wakeup 3736 * processes waiting for a synchronous command completion. 3737 */ 3738 static void 3739 iwn_cmd_done(struct iwn_softc *sc, struct iwn_rx_desc *desc) 3740 { 3741 struct iwn_tx_ring *ring; 3742 struct iwn_tx_data *data; 3743 int cmd_queue_num; 3744 3745 if (sc->sc_flags & IWN_FLAG_PAN_SUPPORT) 3746 cmd_queue_num = IWN_PAN_CMD_QUEUE; 3747 else 3748 cmd_queue_num = IWN_CMD_QUEUE_NUM; 3749 3750 if ((desc->qid & IWN_RX_DESC_QID_MSK) != cmd_queue_num) 3751 return; /* Not a command ack. */ 3752 3753 ring = &sc->txq[cmd_queue_num]; 3754 data = &ring->data[desc->idx]; 3755 3756 /* If the command was mapped in an mbuf, free it. */ 3757 if (data->m != NULL) { 3758 bus_dmamap_sync(ring->data_dmat, data->map, 3759 BUS_DMASYNC_POSTWRITE); 3760 bus_dmamap_unload(ring->data_dmat, data->map); 3761 m_freem(data->m); 3762 data->m = NULL; 3763 } 3764 wakeup(&ring->desc[desc->idx]); 3765 } 3766 3767 static int 3768 iwn_ampdu_check_bitmap(uint64_t bitmap, int start, int idx) 3769 { 3770 int bit, shift; 3771 3772 bit = idx - start; 3773 shift = 0; 3774 if (bit >= 64) { 3775 shift = 0x100 - bit; 3776 bit = 0; 3777 } else if (bit <= -64) 3778 bit = 0x100 + bit; 3779 else if (bit < 0) { 3780 shift = -bit; 3781 bit = 0; 3782 } 3783 3784 if (bit - shift >= 64) 3785 return (0); 3786 3787 return ((bitmap & (1ULL << (bit - shift))) != 0); 3788 } 3789 3790 /* 3791 * Firmware bug workaround: in case if 'retries' counter 3792 * overflows 'seqno' field will be incremented: 3793 * status|sequence|status|sequence|status|sequence 3794 * 0000 0A48 0001 0A49 0000 0A6A 3795 * 1000 0A48 1000 0A49 1000 0A6A 3796 * 2000 0A48 2000 0A49 2000 0A6A 3797 * ... 3798 * E000 0A48 E000 0A49 E000 0A6A 3799 * F000 0A48 F000 0A49 F000 0A6A 3800 * 0000 0A49 0000 0A49 0000 0A6B 3801 * 1000 0A49 1000 0A49 1000 0A6B 3802 * ... 3803 * D000 0A49 D000 0A49 D000 0A6B 3804 * E000 0A49 E001 0A49 E000 0A6B 3805 * F000 0A49 F001 0A49 F000 0A6B 3806 * 0000 0A4A 0000 0A4B 0000 0A6A 3807 * 1000 0A4A 1000 0A4B 1000 0A6A 3808 * ... 3809 * 3810 * Odd 'seqno' numbers are incremened by 2 every 2 overflows. 3811 * For even 'seqno' % 4 != 0 overflow is cyclic (0 -> +1 -> 0). 3812 * Not checked with nretries >= 64. 3813 * 3814 */ 3815 static int 3816 iwn_ampdu_index_check(struct iwn_softc *sc, struct iwn_tx_ring *ring, 3817 uint64_t bitmap, int start, int idx) 3818 { 3819 struct ieee80211com *ic = &sc->sc_ic; 3820 struct iwn_tx_data *data; 3821 int diff, min_retries, max_retries, new_idx, loop_end; 3822 3823 new_idx = idx - IWN_LONG_RETRY_LIMIT_LOG; 3824 if (new_idx < 0) 3825 new_idx += IWN_TX_RING_COUNT; 3826 3827 /* 3828 * Corner case: check if retry count is not too big; 3829 * reset device otherwise. 3830 */ 3831 if (!iwn_ampdu_check_bitmap(bitmap, start, new_idx)) { 3832 data = &ring->data[new_idx]; 3833 if (data->long_retries > IWN_LONG_RETRY_LIMIT) { 3834 device_printf(sc->sc_dev, 3835 "%s: retry count (%d) for idx %d/%d overflow, " 3836 "resetting...\n", __func__, data->long_retries, 3837 ring->qid, new_idx); 3838 ieee80211_restart_all(ic); 3839 return (-1); 3840 } 3841 } 3842 3843 /* Correct index if needed. */ 3844 loop_end = idx; 3845 do { 3846 data = &ring->data[new_idx]; 3847 diff = idx - new_idx; 3848 if (diff < 0) 3849 diff += IWN_TX_RING_COUNT; 3850 3851 min_retries = IWN_LONG_RETRY_FW_OVERFLOW * diff; 3852 if ((new_idx % 2) == 0) 3853 max_retries = IWN_LONG_RETRY_FW_OVERFLOW * (diff + 1); 3854 else 3855 max_retries = IWN_LONG_RETRY_FW_OVERFLOW * (diff + 2); 3856 3857 if (!iwn_ampdu_check_bitmap(bitmap, start, new_idx) && 3858 ((data->long_retries >= min_retries && 3859 data->long_retries < max_retries) || 3860 (diff == 1 && 3861 (new_idx & 0x03) == 0x02 && 3862 data->long_retries >= IWN_LONG_RETRY_FW_OVERFLOW))) { 3863 DPRINTF(sc, IWN_DEBUG_AMPDU, 3864 "%s: correcting index %d -> %d in queue %d" 3865 " (retries %d)\n", __func__, idx, new_idx, 3866 ring->qid, data->long_retries); 3867 return (new_idx); 3868 } 3869 3870 new_idx = (new_idx + 1) % IWN_TX_RING_COUNT; 3871 } while (new_idx != loop_end); 3872 3873 return (idx); 3874 } 3875 3876 static void 3877 iwn_ampdu_tx_done(struct iwn_softc *sc, int qid, int nframes, int rtsfailcnt, 3878 void *stat) 3879 { 3880 struct iwn_tx_ring *ring = &sc->txq[qid]; 3881 struct ieee80211_tx_ampdu *tap = sc->qid2tap[qid]; 3882 struct iwn_node *wn = (void *)tap->txa_ni; 3883 struct iwn_tx_data *data; 3884 uint64_t bitmap = 0; 3885 uint16_t *aggstatus = stat; 3886 uint8_t tid = tap->txa_tid; 3887 int bit, i, idx, shift, start, tx_err; 3888 3889 DPRINTF(sc, IWN_DEBUG_TRACE, "->%s begin\n", __func__); 3890 3891 start = le16toh(*(aggstatus + nframes * 2)) & 0xff; 3892 3893 for (i = 0; i < nframes; i++) { 3894 uint16_t status = le16toh(aggstatus[i * 2]); 3895 3896 if (status & IWN_AGG_TX_STATE_IGNORE_MASK) 3897 continue; 3898 3899 idx = le16toh(aggstatus[i * 2 + 1]) & 0xff; 3900 data = &ring->data[idx]; 3901 if (data->remapped) { 3902 idx = iwn_ampdu_index_check(sc, ring, bitmap, start, idx); 3903 if (idx == -1) { 3904 /* skip error (device will be restarted anyway). */ 3905 continue; 3906 } 3907 3908 /* Index may have changed. */ 3909 data = &ring->data[idx]; 3910 } 3911 3912 /* 3913 * XXX Sometimes (rarely) some frames are excluded from events. 3914 * XXX Due to that long_retries counter may be wrong. 3915 */ 3916 data->long_retries &= ~0x0f; 3917 data->long_retries += IWN_AGG_TX_TRY_COUNT(status) + 1; 3918 3919 if (data->long_retries >= IWN_LONG_RETRY_FW_OVERFLOW) { 3920 int diff, wrong_idx; 3921 3922 diff = data->long_retries / IWN_LONG_RETRY_FW_OVERFLOW; 3923 wrong_idx = (idx + diff) % IWN_TX_RING_COUNT; 3924 3925 /* 3926 * Mark the entry so the above code will check it 3927 * next time. 3928 */ 3929 ring->data[wrong_idx].remapped = 1; 3930 } 3931 3932 if (status & IWN_AGG_TX_STATE_UNDERRUN_MSK) { 3933 /* 3934 * NB: count retries but postpone - it was not 3935 * transmitted. 3936 */ 3937 continue; 3938 } 3939 3940 bit = idx - start; 3941 shift = 0; 3942 if (bit >= 64) { 3943 shift = 0x100 - bit; 3944 bit = 0; 3945 } else if (bit <= -64) 3946 bit = 0x100 + bit; 3947 else if (bit < 0) { 3948 shift = -bit; 3949 bit = 0; 3950 } 3951 bitmap = bitmap << shift; 3952 bitmap |= 1ULL << bit; 3953 } 3954 wn->agg[tid].startidx = start; 3955 wn->agg[tid].bitmap = bitmap; 3956 wn->agg[tid].short_retries = rtsfailcnt; 3957 3958 DPRINTF(sc, IWN_DEBUG_AMPDU, "%s: nframes %d start %d bitmap %016jX\n", 3959 __func__, nframes, start, (uintmax_t)bitmap); 3960 3961 i = ring->read; 3962 3963 for (tx_err = 0; 3964 i != wn->agg[tid].startidx; 3965 i = (i + 1) % IWN_TX_RING_COUNT) { 3966 data = &ring->data[i]; 3967 data->remapped = 0; 3968 if (data->m == NULL) 3969 continue; 3970 3971 tx_err++; 3972 iwn_agg_tx_complete(sc, ring, tid, i, 0); 3973 } 3974 3975 ring->read = wn->agg[tid].startidx; 3976 ring->queued -= tx_err; 3977 3978 iwn_check_tx_ring(sc, qid); 3979 3980 DPRINTF(sc, IWN_DEBUG_TRACE, "->%s: end\n",__func__); 3981 } 3982 3983 /* 3984 * Process an INT_FH_RX or INT_SW_RX interrupt. 3985 */ 3986 static void 3987 iwn_notif_intr(struct iwn_softc *sc) 3988 { 3989 struct iwn_ops *ops = &sc->ops; 3990 struct ieee80211com *ic = &sc->sc_ic; 3991 struct ieee80211vap *vap = TAILQ_FIRST(&ic->ic_vaps); 3992 uint16_t hw; 3993 3994 bus_dmamap_sync(sc->rxq.stat_dma.tag, sc->rxq.stat_dma.map, 3995 BUS_DMASYNC_POSTREAD); 3996 3997 hw = le16toh(sc->rxq.stat->closed_count) & 0xfff; 3998 while (sc->rxq.cur != hw) { 3999 struct iwn_rx_data *data = &sc->rxq.data[sc->rxq.cur]; 4000 struct iwn_rx_desc *desc; 4001 4002 bus_dmamap_sync(sc->rxq.data_dmat, data->map, 4003 BUS_DMASYNC_POSTREAD); 4004 desc = mtod(data->m, struct iwn_rx_desc *); 4005 4006 DPRINTF(sc, IWN_DEBUG_RECV, 4007 "%s: cur=%d; qid %x idx %d flags %x type %d(%s) len %d\n", 4008 __func__, sc->rxq.cur, desc->qid & IWN_RX_DESC_QID_MSK, 4009 desc->idx, desc->flags, desc->type, 4010 iwn_intr_str(desc->type), le16toh(desc->len)); 4011 4012 if (!(desc->qid & IWN_UNSOLICITED_RX_NOTIF)) /* Reply to a command. */ 4013 iwn_cmd_done(sc, desc); 4014 4015 switch (desc->type) { 4016 case IWN_RX_PHY: 4017 iwn_rx_phy(sc, desc); 4018 break; 4019 4020 case IWN_RX_DONE: /* 4965AGN only. */ 4021 case IWN_MPDU_RX_DONE: 4022 /* An 802.11 frame has been received. */ 4023 iwn_rx_done(sc, desc, data); 4024 break; 4025 4026 case IWN_RX_COMPRESSED_BA: 4027 /* A Compressed BlockAck has been received. */ 4028 iwn_rx_compressed_ba(sc, desc); 4029 break; 4030 4031 case IWN_TX_DONE: 4032 /* An 802.11 frame has been transmitted. */ 4033 ops->tx_done(sc, desc, data); 4034 break; 4035 4036 case IWN_RX_STATISTICS: 4037 case IWN_BEACON_STATISTICS: 4038 iwn_rx_statistics(sc, desc); 4039 break; 4040 4041 case IWN_BEACON_MISSED: 4042 { 4043 struct iwn_beacon_missed *miss = 4044 (struct iwn_beacon_missed *)(desc + 1); 4045 int misses; 4046 4047 misses = le32toh(miss->consecutive); 4048 4049 DPRINTF(sc, IWN_DEBUG_STATE, 4050 "%s: beacons missed %d/%d\n", __func__, 4051 misses, le32toh(miss->total)); 4052 /* 4053 * If more than 5 consecutive beacons are missed, 4054 * reinitialize the sensitivity state machine. 4055 */ 4056 if (vap->iv_state == IEEE80211_S_RUN && 4057 (ic->ic_flags & IEEE80211_F_SCAN) == 0) { 4058 if (misses > 5) 4059 (void)iwn_init_sensitivity(sc); 4060 if (misses >= vap->iv_bmissthreshold) { 4061 IWN_UNLOCK(sc); 4062 ieee80211_beacon_miss(ic); 4063 IWN_LOCK(sc); 4064 } 4065 } 4066 break; 4067 } 4068 case IWN_UC_READY: 4069 { 4070 struct iwn_ucode_info *uc = 4071 (struct iwn_ucode_info *)(desc + 1); 4072 4073 /* The microcontroller is ready. */ 4074 DPRINTF(sc, IWN_DEBUG_RESET, 4075 "microcode alive notification version=%d.%d " 4076 "subtype=%x alive=%x\n", uc->major, uc->minor, 4077 uc->subtype, le32toh(uc->valid)); 4078 4079 if (le32toh(uc->valid) != 1) { 4080 device_printf(sc->sc_dev, 4081 "microcontroller initialization failed"); 4082 break; 4083 } 4084 if (uc->subtype == IWN_UCODE_INIT) { 4085 /* Save microcontroller report. */ 4086 memcpy(&sc->ucode_info, uc, sizeof (*uc)); 4087 } 4088 /* Save the address of the error log in SRAM. */ 4089 sc->errptr = le32toh(uc->errptr); 4090 break; 4091 } 4092 #ifdef IWN_DEBUG 4093 case IWN_STATE_CHANGED: 4094 { 4095 /* 4096 * State change allows hardware switch change to be 4097 * noted. However, we handle this in iwn_intr as we 4098 * get both the enable/disble intr. 4099 */ 4100 uint32_t *status = (uint32_t *)(desc + 1); 4101 DPRINTF(sc, IWN_DEBUG_INTR | IWN_DEBUG_STATE, 4102 "state changed to %x\n", 4103 le32toh(*status)); 4104 break; 4105 } 4106 case IWN_START_SCAN: 4107 { 4108 struct iwn_start_scan *scan = 4109 (struct iwn_start_scan *)(desc + 1); 4110 DPRINTF(sc, IWN_DEBUG_ANY, 4111 "%s: scanning channel %d status %x\n", 4112 __func__, scan->chan, le32toh(scan->status)); 4113 break; 4114 } 4115 #endif 4116 case IWN_STOP_SCAN: 4117 { 4118 #ifdef IWN_DEBUG 4119 struct iwn_stop_scan *scan = 4120 (struct iwn_stop_scan *)(desc + 1); 4121 DPRINTF(sc, IWN_DEBUG_STATE | IWN_DEBUG_SCAN, 4122 "scan finished nchan=%d status=%d chan=%d\n", 4123 scan->nchan, scan->status, scan->chan); 4124 #endif 4125 sc->sc_is_scanning = 0; 4126 callout_stop(&sc->scan_timeout); 4127 IWN_UNLOCK(sc); 4128 ieee80211_scan_next(vap); 4129 IWN_LOCK(sc); 4130 break; 4131 } 4132 case IWN5000_CALIBRATION_RESULT: 4133 iwn5000_rx_calib_results(sc, desc); 4134 break; 4135 4136 case IWN5000_CALIBRATION_DONE: 4137 sc->sc_flags |= IWN_FLAG_CALIB_DONE; 4138 wakeup(sc); 4139 break; 4140 } 4141 4142 sc->rxq.cur = (sc->rxq.cur + 1) % IWN_RX_RING_COUNT; 4143 } 4144 4145 /* Tell the firmware what we have processed. */ 4146 hw = (hw == 0) ? IWN_RX_RING_COUNT - 1 : hw - 1; 4147 IWN_WRITE(sc, IWN_FH_RX_WPTR, hw & ~7); 4148 } 4149 4150 /* 4151 * Process an INT_WAKEUP interrupt raised when the microcontroller wakes up 4152 * from power-down sleep mode. 4153 */ 4154 static void 4155 iwn_wakeup_intr(struct iwn_softc *sc) 4156 { 4157 int qid; 4158 4159 DPRINTF(sc, IWN_DEBUG_RESET, "%s: ucode wakeup from power-down sleep\n", 4160 __func__); 4161 4162 /* Wakeup RX and TX rings. */ 4163 IWN_WRITE(sc, IWN_FH_RX_WPTR, sc->rxq.cur & ~7); 4164 for (qid = 0; qid < sc->ntxqs; qid++) { 4165 struct iwn_tx_ring *ring = &sc->txq[qid]; 4166 IWN_WRITE(sc, IWN_HBUS_TARG_WRPTR, qid << 8 | ring->cur); 4167 } 4168 } 4169 4170 static void 4171 iwn_rftoggle_task(void *arg, int npending) 4172 { 4173 struct iwn_softc *sc = arg; 4174 struct ieee80211com *ic = &sc->sc_ic; 4175 uint32_t tmp; 4176 4177 IWN_LOCK(sc); 4178 tmp = IWN_READ(sc, IWN_GP_CNTRL); 4179 IWN_UNLOCK(sc); 4180 4181 device_printf(sc->sc_dev, "RF switch: radio %s\n", 4182 (tmp & IWN_GP_CNTRL_RFKILL) ? "enabled" : "disabled"); 4183 if (!(tmp & IWN_GP_CNTRL_RFKILL)) { 4184 ieee80211_suspend_all(ic); 4185 4186 /* Enable interrupts to get RF toggle notification. */ 4187 IWN_LOCK(sc); 4188 IWN_WRITE(sc, IWN_INT, 0xffffffff); 4189 IWN_WRITE(sc, IWN_INT_MASK, sc->int_mask); 4190 IWN_UNLOCK(sc); 4191 } else 4192 ieee80211_resume_all(ic); 4193 } 4194 4195 /* 4196 * Dump the error log of the firmware when a firmware panic occurs. Although 4197 * we can't debug the firmware because it is neither open source nor free, it 4198 * can help us to identify certain classes of problems. 4199 */ 4200 static void 4201 iwn_fatal_intr(struct iwn_softc *sc) 4202 { 4203 struct iwn_fw_dump dump; 4204 int i; 4205 4206 IWN_LOCK_ASSERT(sc); 4207 4208 /* Force a complete recalibration on next init. */ 4209 sc->sc_flags &= ~IWN_FLAG_CALIB_DONE; 4210 4211 /* Check that the error log address is valid. */ 4212 if (sc->errptr < IWN_FW_DATA_BASE || 4213 sc->errptr + sizeof (dump) > 4214 IWN_FW_DATA_BASE + sc->fw_data_maxsz) { 4215 printf("%s: bad firmware error log address 0x%08x\n", __func__, 4216 sc->errptr); 4217 return; 4218 } 4219 if (iwn_nic_lock(sc) != 0) { 4220 printf("%s: could not read firmware error log\n", __func__); 4221 return; 4222 } 4223 /* Read firmware error log from SRAM. */ 4224 iwn_mem_read_region_4(sc, sc->errptr, (uint32_t *)&dump, 4225 sizeof (dump) / sizeof (uint32_t)); 4226 iwn_nic_unlock(sc); 4227 4228 if (dump.valid == 0) { 4229 printf("%s: firmware error log is empty\n", __func__); 4230 return; 4231 } 4232 printf("firmware error log:\n"); 4233 printf(" error type = \"%s\" (0x%08X)\n", 4234 (dump.id < nitems(iwn_fw_errmsg)) ? 4235 iwn_fw_errmsg[dump.id] : "UNKNOWN", 4236 dump.id); 4237 printf(" program counter = 0x%08X\n", dump.pc); 4238 printf(" source line = 0x%08X\n", dump.src_line); 4239 printf(" error data = 0x%08X%08X\n", 4240 dump.error_data[0], dump.error_data[1]); 4241 printf(" branch link = 0x%08X%08X\n", 4242 dump.branch_link[0], dump.branch_link[1]); 4243 printf(" interrupt link = 0x%08X%08X\n", 4244 dump.interrupt_link[0], dump.interrupt_link[1]); 4245 printf(" time = %u\n", dump.time[0]); 4246 4247 /* Dump driver status (TX and RX rings) while we're here. */ 4248 printf("driver status:\n"); 4249 for (i = 0; i < sc->ntxqs; i++) { 4250 struct iwn_tx_ring *ring = &sc->txq[i]; 4251 printf(" tx ring %2d: qid=%-2d cur=%-3d queued=%-3d\n", 4252 i, ring->qid, ring->cur, ring->queued); 4253 } 4254 printf(" rx ring: cur=%d\n", sc->rxq.cur); 4255 } 4256 4257 static void 4258 iwn_intr(void *arg) 4259 { 4260 struct iwn_softc *sc = arg; 4261 uint32_t r1, r2, tmp; 4262 4263 IWN_LOCK(sc); 4264 4265 /* Disable interrupts. */ 4266 IWN_WRITE(sc, IWN_INT_MASK, 0); 4267 4268 /* Read interrupts from ICT (fast) or from registers (slow). */ 4269 if (sc->sc_flags & IWN_FLAG_USE_ICT) { 4270 bus_dmamap_sync(sc->ict_dma.tag, sc->ict_dma.map, 4271 BUS_DMASYNC_POSTREAD); 4272 tmp = 0; 4273 while (sc->ict[sc->ict_cur] != 0) { 4274 tmp |= sc->ict[sc->ict_cur]; 4275 sc->ict[sc->ict_cur] = 0; /* Acknowledge. */ 4276 sc->ict_cur = (sc->ict_cur + 1) % IWN_ICT_COUNT; 4277 } 4278 tmp = le32toh(tmp); 4279 if (tmp == 0xffffffff) /* Shouldn't happen. */ 4280 tmp = 0; 4281 else if (tmp & 0xc0000) /* Workaround a HW bug. */ 4282 tmp |= 0x8000; 4283 r1 = (tmp & 0xff00) << 16 | (tmp & 0xff); 4284 r2 = 0; /* Unused. */ 4285 } else { 4286 r1 = IWN_READ(sc, IWN_INT); 4287 if (r1 == 0xffffffff || (r1 & 0xfffffff0) == 0xa5a5a5a0) { 4288 IWN_UNLOCK(sc); 4289 return; /* Hardware gone! */ 4290 } 4291 r2 = IWN_READ(sc, IWN_FH_INT); 4292 } 4293 4294 DPRINTF(sc, IWN_DEBUG_INTR, "interrupt reg1=0x%08x reg2=0x%08x\n" 4295 , r1, r2); 4296 4297 if (r1 == 0 && r2 == 0) 4298 goto done; /* Interrupt not for us. */ 4299 4300 /* Acknowledge interrupts. */ 4301 IWN_WRITE(sc, IWN_INT, r1); 4302 if (!(sc->sc_flags & IWN_FLAG_USE_ICT)) 4303 IWN_WRITE(sc, IWN_FH_INT, r2); 4304 4305 if (r1 & IWN_INT_RF_TOGGLED) { 4306 taskqueue_enqueue(sc->sc_tq, &sc->sc_rftoggle_task); 4307 goto done; 4308 } 4309 if (r1 & IWN_INT_CT_REACHED) { 4310 device_printf(sc->sc_dev, "%s: critical temperature reached!\n", 4311 __func__); 4312 } 4313 if (r1 & (IWN_INT_SW_ERR | IWN_INT_HW_ERR)) { 4314 device_printf(sc->sc_dev, "%s: fatal firmware error\n", 4315 __func__); 4316 #ifdef IWN_DEBUG 4317 iwn_debug_register(sc); 4318 #endif 4319 /* Dump firmware error log and stop. */ 4320 iwn_fatal_intr(sc); 4321 4322 taskqueue_enqueue(sc->sc_tq, &sc->sc_panic_task); 4323 goto done; 4324 } 4325 if ((r1 & (IWN_INT_FH_RX | IWN_INT_SW_RX | IWN_INT_RX_PERIODIC)) || 4326 (r2 & IWN_FH_INT_RX)) { 4327 if (sc->sc_flags & IWN_FLAG_USE_ICT) { 4328 if (r1 & (IWN_INT_FH_RX | IWN_INT_SW_RX)) 4329 IWN_WRITE(sc, IWN_FH_INT, IWN_FH_INT_RX); 4330 IWN_WRITE_1(sc, IWN_INT_PERIODIC, 4331 IWN_INT_PERIODIC_DIS); 4332 iwn_notif_intr(sc); 4333 if (r1 & (IWN_INT_FH_RX | IWN_INT_SW_RX)) { 4334 IWN_WRITE_1(sc, IWN_INT_PERIODIC, 4335 IWN_INT_PERIODIC_ENA); 4336 } 4337 } else 4338 iwn_notif_intr(sc); 4339 } 4340 4341 if ((r1 & IWN_INT_FH_TX) || (r2 & IWN_FH_INT_TX)) { 4342 if (sc->sc_flags & IWN_FLAG_USE_ICT) 4343 IWN_WRITE(sc, IWN_FH_INT, IWN_FH_INT_TX); 4344 wakeup(sc); /* FH DMA transfer completed. */ 4345 } 4346 4347 if (r1 & IWN_INT_ALIVE) 4348 wakeup(sc); /* Firmware is alive. */ 4349 4350 if (r1 & IWN_INT_WAKEUP) 4351 iwn_wakeup_intr(sc); 4352 4353 done: 4354 /* Re-enable interrupts. */ 4355 if (sc->sc_flags & IWN_FLAG_RUNNING) 4356 IWN_WRITE(sc, IWN_INT_MASK, sc->int_mask); 4357 4358 IWN_UNLOCK(sc); 4359 } 4360 4361 /* 4362 * Update TX scheduler ring when transmitting an 802.11 frame (4965AGN and 4363 * 5000 adapters use a slightly different format). 4364 */ 4365 static void 4366 iwn4965_update_sched(struct iwn_softc *sc, int qid, int idx, uint8_t id, 4367 uint16_t len) 4368 { 4369 uint16_t *w = &sc->sched[qid * IWN4965_SCHED_COUNT + idx]; 4370 4371 DPRINTF(sc, IWN_DEBUG_TRACE, "->Doing %s\n", __func__); 4372 4373 *w = htole16(len + 8); 4374 bus_dmamap_sync(sc->sched_dma.tag, sc->sched_dma.map, 4375 BUS_DMASYNC_PREWRITE); 4376 if (idx < IWN_SCHED_WINSZ) { 4377 *(w + IWN_TX_RING_COUNT) = *w; 4378 bus_dmamap_sync(sc->sched_dma.tag, sc->sched_dma.map, 4379 BUS_DMASYNC_PREWRITE); 4380 } 4381 } 4382 4383 static void 4384 iwn5000_update_sched(struct iwn_softc *sc, int qid, int idx, uint8_t id, 4385 uint16_t len) 4386 { 4387 uint16_t *w = &sc->sched[qid * IWN5000_SCHED_COUNT + idx]; 4388 4389 DPRINTF(sc, IWN_DEBUG_TRACE, "->Doing %s\n", __func__); 4390 4391 *w = htole16(id << 12 | (len + 8)); 4392 bus_dmamap_sync(sc->sched_dma.tag, sc->sched_dma.map, 4393 BUS_DMASYNC_PREWRITE); 4394 if (idx < IWN_SCHED_WINSZ) { 4395 *(w + IWN_TX_RING_COUNT) = *w; 4396 bus_dmamap_sync(sc->sched_dma.tag, sc->sched_dma.map, 4397 BUS_DMASYNC_PREWRITE); 4398 } 4399 } 4400 4401 #ifdef notyet 4402 static void 4403 iwn5000_reset_sched(struct iwn_softc *sc, int qid, int idx) 4404 { 4405 uint16_t *w = &sc->sched[qid * IWN5000_SCHED_COUNT + idx]; 4406 4407 DPRINTF(sc, IWN_DEBUG_TRACE, "->Doing %s\n", __func__); 4408 4409 *w = (*w & htole16(0xf000)) | htole16(1); 4410 bus_dmamap_sync(sc->sched_dma.tag, sc->sched_dma.map, 4411 BUS_DMASYNC_PREWRITE); 4412 if (idx < IWN_SCHED_WINSZ) { 4413 *(w + IWN_TX_RING_COUNT) = *w; 4414 bus_dmamap_sync(sc->sched_dma.tag, sc->sched_dma.map, 4415 BUS_DMASYNC_PREWRITE); 4416 } 4417 } 4418 #endif 4419 4420 /* 4421 * Check whether OFDM 11g protection will be enabled for the given rate. 4422 * 4423 * The original driver code only enabled protection for OFDM rates. 4424 * It didn't check to see whether it was operating in 11a or 11bg mode. 4425 */ 4426 static int 4427 iwn_check_rate_needs_protection(struct iwn_softc *sc, 4428 struct ieee80211vap *vap, uint8_t rate) 4429 { 4430 struct ieee80211com *ic = vap->iv_ic; 4431 4432 /* 4433 * Not in 2GHz mode? Then there's no need to enable OFDM 4434 * 11bg protection. 4435 */ 4436 if (! IEEE80211_IS_CHAN_2GHZ(ic->ic_curchan)) { 4437 return (0); 4438 } 4439 4440 /* 4441 * 11bg protection not enabled? Then don't use it. 4442 */ 4443 if ((ic->ic_flags & IEEE80211_F_USEPROT) == 0) 4444 return (0); 4445 4446 /* 4447 * If it's an 11n rate - no protection. 4448 * We'll do it via a specific 11n check. 4449 */ 4450 if (rate & IEEE80211_RATE_MCS) { 4451 return (0); 4452 } 4453 4454 /* 4455 * Do a rate table lookup. If the PHY is CCK, 4456 * don't do protection. 4457 */ 4458 if (ieee80211_rate2phytype(ic->ic_rt, rate) == IEEE80211_T_CCK) 4459 return (0); 4460 4461 /* 4462 * Yup, enable protection. 4463 */ 4464 return (1); 4465 } 4466 4467 /* 4468 * return a value between 0 and IWN_MAX_TX_RETRIES-1 as an index into 4469 * the link quality table that reflects this particular entry. 4470 */ 4471 static int 4472 iwn_tx_rate_to_linkq_offset(struct iwn_softc *sc, struct ieee80211_node *ni, 4473 uint8_t rate) 4474 { 4475 struct ieee80211_rateset *rs; 4476 int is_11n; 4477 int nr; 4478 int i; 4479 uint8_t cmp_rate; 4480 4481 /* 4482 * Figure out if we're using 11n or not here. 4483 */ 4484 if (IEEE80211_IS_CHAN_HT(ni->ni_chan) && ni->ni_htrates.rs_nrates > 0) 4485 is_11n = 1; 4486 else 4487 is_11n = 0; 4488 4489 /* 4490 * Use the correct rate table. 4491 */ 4492 if (is_11n) { 4493 rs = (struct ieee80211_rateset *) &ni->ni_htrates; 4494 nr = ni->ni_htrates.rs_nrates; 4495 } else { 4496 rs = &ni->ni_rates; 4497 nr = rs->rs_nrates; 4498 } 4499 4500 /* 4501 * Find the relevant link quality entry in the table. 4502 */ 4503 for (i = 0; i < nr && i < IWN_MAX_TX_RETRIES - 1 ; i++) { 4504 /* 4505 * The link quality table index starts at 0 == highest 4506 * rate, so we walk the rate table backwards. 4507 */ 4508 cmp_rate = rs->rs_rates[(nr - 1) - i]; 4509 if (rate & IEEE80211_RATE_MCS) 4510 cmp_rate |= IEEE80211_RATE_MCS; 4511 4512 #if 0 4513 DPRINTF(sc, IWN_DEBUG_XMIT, "%s: idx %d: nr=%d, rate=0x%02x, rateentry=0x%02x\n", 4514 __func__, 4515 i, 4516 nr, 4517 rate, 4518 cmp_rate); 4519 #endif 4520 4521 if (cmp_rate == rate) 4522 return (i); 4523 } 4524 4525 /* Failed? Start at the end */ 4526 return (IWN_MAX_TX_RETRIES - 1); 4527 } 4528 4529 static int 4530 iwn_tx_data(struct iwn_softc *sc, struct mbuf *m, struct ieee80211_node *ni) 4531 { 4532 const struct ieee80211_txparam *tp = ni->ni_txparms; 4533 struct ieee80211vap *vap = ni->ni_vap; 4534 struct ieee80211com *ic = ni->ni_ic; 4535 struct iwn_node *wn = (void *)ni; 4536 struct iwn_tx_ring *ring; 4537 struct iwn_tx_cmd *cmd; 4538 struct iwn_cmd_data *tx; 4539 struct ieee80211_frame *wh; 4540 struct ieee80211_key *k = NULL; 4541 uint32_t flags; 4542 uint16_t qos; 4543 uint8_t tid, type; 4544 int ac, totlen, rate; 4545 4546 DPRINTF(sc, IWN_DEBUG_TRACE, "->%s begin\n", __func__); 4547 4548 IWN_LOCK_ASSERT(sc); 4549 4550 wh = mtod(m, struct ieee80211_frame *); 4551 type = wh->i_fc[0] & IEEE80211_FC0_TYPE_MASK; 4552 4553 /* Select EDCA Access Category and TX ring for this frame. */ 4554 if (IEEE80211_QOS_HAS_SEQ(wh)) { 4555 qos = ((const struct ieee80211_qosframe *)wh)->i_qos[0]; 4556 tid = qos & IEEE80211_QOS_TID; 4557 } else { 4558 qos = 0; 4559 tid = 0; 4560 } 4561 4562 /* Choose a TX rate index. */ 4563 if (type == IEEE80211_FC0_TYPE_MGT || 4564 type == IEEE80211_FC0_TYPE_CTL || 4565 (m->m_flags & M_EAPOL) != 0) 4566 rate = tp->mgmtrate; 4567 else if (IEEE80211_IS_MULTICAST(wh->i_addr1)) 4568 rate = tp->mcastrate; 4569 else if (tp->ucastrate != IEEE80211_FIXED_RATE_NONE) 4570 rate = tp->ucastrate; 4571 else { 4572 /* XXX pass pktlen */ 4573 (void) ieee80211_ratectl_rate(ni, NULL, 0); 4574 rate = ni->ni_txrate; 4575 } 4576 4577 /* 4578 * XXX TODO: Group addressed frames aren't aggregated and must 4579 * go to the normal non-aggregation queue, and have a NONQOS TID 4580 * assigned from net80211. 4581 */ 4582 4583 ac = M_WME_GETAC(m); 4584 if (m->m_flags & M_AMPDU_MPDU) { 4585 struct ieee80211_tx_ampdu *tap = &ni->ni_tx_ampdu[ac]; 4586 4587 if (!IEEE80211_AMPDU_RUNNING(tap)) 4588 return (EINVAL); 4589 4590 ac = *(int *)tap->txa_private; 4591 } 4592 4593 /* Encrypt the frame if need be. */ 4594 if (wh->i_fc[1] & IEEE80211_FC1_PROTECTED) { 4595 /* Retrieve key for TX. */ 4596 k = ieee80211_crypto_encap(ni, m); 4597 if (k == NULL) { 4598 return ENOBUFS; 4599 } 4600 /* 802.11 header may have moved. */ 4601 wh = mtod(m, struct ieee80211_frame *); 4602 } 4603 totlen = m->m_pkthdr.len; 4604 4605 if (ieee80211_radiotap_active_vap(vap)) { 4606 struct iwn_tx_radiotap_header *tap = &sc->sc_txtap; 4607 4608 tap->wt_flags = 0; 4609 tap->wt_rate = rate; 4610 if (k != NULL) 4611 tap->wt_flags |= IEEE80211_RADIOTAP_F_WEP; 4612 4613 ieee80211_radiotap_tx(vap, m); 4614 } 4615 4616 flags = 0; 4617 if (!IEEE80211_IS_MULTICAST(wh->i_addr1)) { 4618 /* Unicast frame, check if an ACK is expected. */ 4619 if (!qos || (qos & IEEE80211_QOS_ACKPOLICY) != 4620 IEEE80211_QOS_ACKPOLICY_NOACK) 4621 flags |= IWN_TX_NEED_ACK; 4622 } 4623 if ((wh->i_fc[0] & 4624 (IEEE80211_FC0_TYPE_MASK | IEEE80211_FC0_SUBTYPE_MASK)) == 4625 (IEEE80211_FC0_TYPE_CTL | IEEE80211_FC0_SUBTYPE_BAR)) 4626 flags |= IWN_TX_IMM_BA; /* Cannot happen yet. */ 4627 4628 if (wh->i_fc[1] & IEEE80211_FC1_MORE_FRAG) 4629 flags |= IWN_TX_MORE_FRAG; /* Cannot happen yet. */ 4630 4631 /* Check if frame must be protected using RTS/CTS or CTS-to-self. */ 4632 if (!IEEE80211_IS_MULTICAST(wh->i_addr1)) { 4633 /* NB: Group frames are sent using CCK in 802.11b/g. */ 4634 if (totlen + IEEE80211_CRC_LEN > vap->iv_rtsthreshold) { 4635 flags |= IWN_TX_NEED_RTS; 4636 } else if (iwn_check_rate_needs_protection(sc, vap, rate)) { 4637 if (ic->ic_protmode == IEEE80211_PROT_CTSONLY) 4638 flags |= IWN_TX_NEED_CTS; 4639 else if (ic->ic_protmode == IEEE80211_PROT_RTSCTS) 4640 flags |= IWN_TX_NEED_RTS; 4641 } else if ((rate & IEEE80211_RATE_MCS) && 4642 (ic->ic_htprotmode == IEEE80211_PROT_RTSCTS)) { 4643 flags |= IWN_TX_NEED_RTS; 4644 } 4645 4646 /* XXX HT protection? */ 4647 4648 if (flags & (IWN_TX_NEED_RTS | IWN_TX_NEED_CTS)) { 4649 if (sc->hw_type != IWN_HW_REV_TYPE_4965) { 4650 /* 5000 autoselects RTS/CTS or CTS-to-self. */ 4651 flags &= ~(IWN_TX_NEED_RTS | IWN_TX_NEED_CTS); 4652 flags |= IWN_TX_NEED_PROTECTION; 4653 } else 4654 flags |= IWN_TX_FULL_TXOP; 4655 } 4656 } 4657 4658 ring = &sc->txq[ac]; 4659 if (m->m_flags & M_AMPDU_MPDU) { 4660 uint16_t seqno = ni->ni_txseqs[tid]; 4661 4662 if (ring->queued > IWN_TX_RING_COUNT / 2 && 4663 (ring->cur + 1) % IWN_TX_RING_COUNT == ring->read) { 4664 DPRINTF(sc, IWN_DEBUG_AMPDU, "%s: no more space " 4665 "(queued %d) left in %d queue!\n", 4666 __func__, ring->queued, ac); 4667 return (ENOBUFS); 4668 } 4669 4670 /* 4671 * Queue this frame to the hardware ring that we've 4672 * negotiated AMPDU TX on. 4673 * 4674 * Note that the sequence number must match the TX slot 4675 * being used! 4676 */ 4677 if ((seqno % 256) != ring->cur) { 4678 device_printf(sc->sc_dev, 4679 "%s: m=%p: seqno (%d) (%d) != ring index (%d) !\n", 4680 __func__, 4681 m, 4682 seqno, 4683 seqno % 256, 4684 ring->cur); 4685 4686 /* XXX until D9195 will not be committed */ 4687 ni->ni_txseqs[tid] &= ~0xff; 4688 ni->ni_txseqs[tid] += ring->cur; 4689 seqno = ni->ni_txseqs[tid]; 4690 } 4691 4692 *(uint16_t *)wh->i_seq = 4693 htole16(seqno << IEEE80211_SEQ_SEQ_SHIFT); 4694 ni->ni_txseqs[tid]++; 4695 } 4696 4697 /* Prepare TX firmware command. */ 4698 cmd = &ring->cmd[ring->cur]; 4699 tx = (struct iwn_cmd_data *)cmd->data; 4700 4701 /* NB: No need to clear tx, all fields are reinitialized here. */ 4702 tx->scratch = 0; /* clear "scratch" area */ 4703 4704 if (IEEE80211_IS_MULTICAST(wh->i_addr1) || 4705 type != IEEE80211_FC0_TYPE_DATA) 4706 tx->id = sc->broadcast_id; 4707 else 4708 tx->id = wn->id; 4709 4710 if (type == IEEE80211_FC0_TYPE_MGT) { 4711 uint8_t subtype = wh->i_fc[0] & IEEE80211_FC0_SUBTYPE_MASK; 4712 4713 /* Tell HW to set timestamp in probe responses. */ 4714 if (subtype == IEEE80211_FC0_SUBTYPE_PROBE_RESP) 4715 flags |= IWN_TX_INSERT_TSTAMP; 4716 if (subtype == IEEE80211_FC0_SUBTYPE_ASSOC_REQ || 4717 subtype == IEEE80211_FC0_SUBTYPE_REASSOC_REQ) 4718 tx->timeout = htole16(3); 4719 else 4720 tx->timeout = htole16(2); 4721 } else 4722 tx->timeout = htole16(0); 4723 4724 if (tx->id == sc->broadcast_id) { 4725 /* Group or management frame. */ 4726 tx->linkq = 0; 4727 } else { 4728 tx->linkq = iwn_tx_rate_to_linkq_offset(sc, ni, rate); 4729 flags |= IWN_TX_LINKQ; /* enable MRR */ 4730 } 4731 4732 tx->tid = tid; 4733 tx->rts_ntries = 60; 4734 tx->data_ntries = 15; 4735 tx->lifetime = htole32(IWN_LIFETIME_INFINITE); 4736 tx->rate = iwn_rate_to_plcp(sc, ni, rate); 4737 tx->security = 0; 4738 tx->flags = htole32(flags); 4739 4740 return (iwn_tx_cmd(sc, m, ni, ring)); 4741 } 4742 4743 static int 4744 iwn_tx_data_raw(struct iwn_softc *sc, struct mbuf *m, 4745 struct ieee80211_node *ni, const struct ieee80211_bpf_params *params) 4746 { 4747 struct ieee80211vap *vap = ni->ni_vap; 4748 struct iwn_tx_cmd *cmd; 4749 struct iwn_cmd_data *tx; 4750 struct ieee80211_frame *wh; 4751 struct iwn_tx_ring *ring; 4752 uint32_t flags; 4753 int ac, rate; 4754 uint8_t type; 4755 4756 DPRINTF(sc, IWN_DEBUG_TRACE, "->%s begin\n", __func__); 4757 4758 IWN_LOCK_ASSERT(sc); 4759 4760 wh = mtod(m, struct ieee80211_frame *); 4761 type = wh->i_fc[0] & IEEE80211_FC0_TYPE_MASK; 4762 4763 ac = params->ibp_pri & 3; 4764 4765 /* Choose a TX rate. */ 4766 rate = params->ibp_rate0; 4767 4768 flags = 0; 4769 if ((params->ibp_flags & IEEE80211_BPF_NOACK) == 0) 4770 flags |= IWN_TX_NEED_ACK; 4771 if (params->ibp_flags & IEEE80211_BPF_RTS) { 4772 if (sc->hw_type != IWN_HW_REV_TYPE_4965) { 4773 /* 5000 autoselects RTS/CTS or CTS-to-self. */ 4774 flags &= ~IWN_TX_NEED_RTS; 4775 flags |= IWN_TX_NEED_PROTECTION; 4776 } else 4777 flags |= IWN_TX_NEED_RTS | IWN_TX_FULL_TXOP; 4778 } 4779 if (params->ibp_flags & IEEE80211_BPF_CTS) { 4780 if (sc->hw_type != IWN_HW_REV_TYPE_4965) { 4781 /* 5000 autoselects RTS/CTS or CTS-to-self. */ 4782 flags &= ~IWN_TX_NEED_CTS; 4783 flags |= IWN_TX_NEED_PROTECTION; 4784 } else 4785 flags |= IWN_TX_NEED_CTS | IWN_TX_FULL_TXOP; 4786 } 4787 4788 if (ieee80211_radiotap_active_vap(vap)) { 4789 struct iwn_tx_radiotap_header *tap = &sc->sc_txtap; 4790 4791 tap->wt_flags = 0; 4792 tap->wt_rate = rate; 4793 4794 ieee80211_radiotap_tx(vap, m); 4795 } 4796 4797 ring = &sc->txq[ac]; 4798 cmd = &ring->cmd[ring->cur]; 4799 4800 tx = (struct iwn_cmd_data *)cmd->data; 4801 /* NB: No need to clear tx, all fields are reinitialized here. */ 4802 tx->scratch = 0; /* clear "scratch" area */ 4803 4804 if (type == IEEE80211_FC0_TYPE_MGT) { 4805 uint8_t subtype = wh->i_fc[0] & IEEE80211_FC0_SUBTYPE_MASK; 4806 4807 /* Tell HW to set timestamp in probe responses. */ 4808 if (subtype == IEEE80211_FC0_SUBTYPE_PROBE_RESP) 4809 flags |= IWN_TX_INSERT_TSTAMP; 4810 4811 if (subtype == IEEE80211_FC0_SUBTYPE_ASSOC_REQ || 4812 subtype == IEEE80211_FC0_SUBTYPE_REASSOC_REQ) 4813 tx->timeout = htole16(3); 4814 else 4815 tx->timeout = htole16(2); 4816 } else 4817 tx->timeout = htole16(0); 4818 4819 tx->tid = 0; 4820 tx->id = sc->broadcast_id; 4821 tx->rts_ntries = params->ibp_try1; 4822 tx->data_ntries = params->ibp_try0; 4823 tx->lifetime = htole32(IWN_LIFETIME_INFINITE); 4824 tx->rate = iwn_rate_to_plcp(sc, ni, rate); 4825 tx->security = 0; 4826 tx->flags = htole32(flags); 4827 4828 /* Group or management frame. */ 4829 tx->linkq = 0; 4830 4831 return (iwn_tx_cmd(sc, m, ni, ring)); 4832 } 4833 4834 static int 4835 iwn_tx_cmd(struct iwn_softc *sc, struct mbuf *m, struct ieee80211_node *ni, 4836 struct iwn_tx_ring *ring) 4837 { 4838 struct iwn_ops *ops = &sc->ops; 4839 struct iwn_tx_cmd *cmd; 4840 struct iwn_cmd_data *tx; 4841 struct ieee80211_frame *wh; 4842 struct iwn_tx_desc *desc; 4843 struct iwn_tx_data *data; 4844 bus_dma_segment_t *seg, segs[IWN_MAX_SCATTER]; 4845 struct mbuf *m1; 4846 u_int hdrlen; 4847 int totlen, error, pad, nsegs = 0, i; 4848 4849 wh = mtod(m, struct ieee80211_frame *); 4850 hdrlen = ieee80211_anyhdrsize(wh); 4851 totlen = m->m_pkthdr.len; 4852 4853 desc = &ring->desc[ring->cur]; 4854 data = &ring->data[ring->cur]; 4855 4856 if (__predict_false(data->m != NULL || data->ni != NULL)) { 4857 device_printf(sc->sc_dev, "%s: ni (%p) or m (%p) for idx %d " 4858 "in queue %d is not NULL!\n", __func__, data->ni, data->m, 4859 ring->cur, ring->qid); 4860 return EIO; 4861 } 4862 4863 /* Prepare TX firmware command. */ 4864 cmd = &ring->cmd[ring->cur]; 4865 cmd->code = IWN_CMD_TX_DATA; 4866 cmd->flags = 0; 4867 cmd->qid = ring->qid; 4868 cmd->idx = ring->cur; 4869 4870 tx = (struct iwn_cmd_data *)cmd->data; 4871 tx->len = htole16(totlen); 4872 4873 /* Set physical address of "scratch area". */ 4874 tx->loaddr = htole32(IWN_LOADDR(data->scratch_paddr)); 4875 tx->hiaddr = IWN_HIADDR(data->scratch_paddr); 4876 if (hdrlen & 3) { 4877 /* First segment length must be a multiple of 4. */ 4878 tx->flags |= htole32(IWN_TX_NEED_PADDING); 4879 pad = 4 - (hdrlen & 3); 4880 } else 4881 pad = 0; 4882 4883 /* Copy 802.11 header in TX command. */ 4884 memcpy((uint8_t *)(tx + 1), wh, hdrlen); 4885 4886 /* Trim 802.11 header. */ 4887 m_adj(m, hdrlen); 4888 4889 error = bus_dmamap_load_mbuf_sg(ring->data_dmat, data->map, m, segs, 4890 &nsegs, BUS_DMA_NOWAIT); 4891 if (error != 0) { 4892 if (error != EFBIG) { 4893 device_printf(sc->sc_dev, 4894 "%s: can't map mbuf (error %d)\n", __func__, error); 4895 return error; 4896 } 4897 /* Too many DMA segments, linearize mbuf. */ 4898 m1 = m_collapse(m, M_NOWAIT, IWN_MAX_SCATTER - 1); 4899 if (m1 == NULL) { 4900 device_printf(sc->sc_dev, 4901 "%s: could not defrag mbuf\n", __func__); 4902 return ENOBUFS; 4903 } 4904 m = m1; 4905 4906 error = bus_dmamap_load_mbuf_sg(ring->data_dmat, data->map, m, 4907 segs, &nsegs, BUS_DMA_NOWAIT); 4908 if (error != 0) { 4909 /* XXX fix this */ 4910 /* 4911 * NB: Do not return error; 4912 * original mbuf does not exist anymore. 4913 */ 4914 device_printf(sc->sc_dev, 4915 "%s: can't map mbuf (error %d)\n", 4916 __func__, error); 4917 if_inc_counter(ni->ni_vap->iv_ifp, 4918 IFCOUNTER_OERRORS, 1); 4919 ieee80211_free_node(ni); 4920 m_freem(m); 4921 return 0; 4922 } 4923 } 4924 4925 data->m = m; 4926 data->ni = ni; 4927 4928 DPRINTF(sc, IWN_DEBUG_XMIT, "%s: qid %d idx %d len %d nsegs %d " 4929 "plcp %d\n", 4930 __func__, ring->qid, ring->cur, totlen, nsegs, tx->rate); 4931 4932 /* Fill TX descriptor. */ 4933 desc->nsegs = 1; 4934 if (m->m_len != 0) 4935 desc->nsegs += nsegs; 4936 /* First DMA segment is used by the TX command. */ 4937 desc->segs[0].addr = htole32(IWN_LOADDR(data->cmd_paddr)); 4938 desc->segs[0].len = htole16(IWN_HIADDR(data->cmd_paddr) | 4939 (4 + sizeof (*tx) + hdrlen + pad) << 4); 4940 /* Other DMA segments are for data payload. */ 4941 seg = &segs[0]; 4942 for (i = 1; i <= nsegs; i++) { 4943 desc->segs[i].addr = htole32(IWN_LOADDR(seg->ds_addr)); 4944 desc->segs[i].len = htole16(IWN_HIADDR(seg->ds_addr) | 4945 seg->ds_len << 4); 4946 seg++; 4947 } 4948 4949 bus_dmamap_sync(ring->data_dmat, data->map, BUS_DMASYNC_PREWRITE); 4950 bus_dmamap_sync(ring->cmd_dma.tag, ring->cmd_dma.map, 4951 BUS_DMASYNC_PREWRITE); 4952 bus_dmamap_sync(ring->desc_dma.tag, ring->desc_dma.map, 4953 BUS_DMASYNC_PREWRITE); 4954 4955 /* Update TX scheduler. */ 4956 if (ring->qid >= sc->firstaggqueue) 4957 ops->update_sched(sc, ring->qid, ring->cur, tx->id, totlen); 4958 4959 /* Kick TX ring. */ 4960 ring->cur = (ring->cur + 1) % IWN_TX_RING_COUNT; 4961 IWN_WRITE(sc, IWN_HBUS_TARG_WRPTR, ring->qid << 8 | ring->cur); 4962 4963 /* Mark TX ring as full if we reach a certain threshold. */ 4964 if (++ring->queued > IWN_TX_RING_HIMARK) 4965 sc->qfullmsk |= 1 << ring->qid; 4966 4967 DPRINTF(sc, IWN_DEBUG_TRACE, "->%s: end\n",__func__); 4968 4969 return 0; 4970 } 4971 4972 static void 4973 iwn_xmit_task(void *arg0, int pending) 4974 { 4975 struct iwn_softc *sc = arg0; 4976 struct ieee80211_node *ni; 4977 struct mbuf *m; 4978 int error; 4979 struct ieee80211_bpf_params p; 4980 int have_p; 4981 4982 DPRINTF(sc, IWN_DEBUG_XMIT, "%s: called\n", __func__); 4983 4984 IWN_LOCK(sc); 4985 /* 4986 * Dequeue frames, attempt to transmit, 4987 * then disable beaconwait when we're done. 4988 */ 4989 while ((m = mbufq_dequeue(&sc->sc_xmit_queue)) != NULL) { 4990 have_p = 0; 4991 ni = (struct ieee80211_node *)m->m_pkthdr.rcvif; 4992 4993 /* Get xmit params if appropriate */ 4994 if (ieee80211_get_xmit_params(m, &p) == 0) 4995 have_p = 1; 4996 4997 DPRINTF(sc, IWN_DEBUG_XMIT, "%s: m=%p, have_p=%d\n", 4998 __func__, m, have_p); 4999 5000 /* If we have xmit params, use them */ 5001 if (have_p) 5002 error = iwn_tx_data_raw(sc, m, ni, &p); 5003 else 5004 error = iwn_tx_data(sc, m, ni); 5005 5006 if (error != 0) { 5007 if_inc_counter(ni->ni_vap->iv_ifp, 5008 IFCOUNTER_OERRORS, 1); 5009 ieee80211_free_node(ni); 5010 m_freem(m); 5011 } 5012 } 5013 5014 sc->sc_beacon_wait = 0; 5015 IWN_UNLOCK(sc); 5016 } 5017 5018 /* 5019 * raw frame xmit - free node/reference if failed. 5020 */ 5021 static int 5022 iwn_raw_xmit(struct ieee80211_node *ni, struct mbuf *m, 5023 const struct ieee80211_bpf_params *params) 5024 { 5025 struct ieee80211com *ic = ni->ni_ic; 5026 struct iwn_softc *sc = ic->ic_softc; 5027 int error = 0; 5028 5029 DPRINTF(sc, IWN_DEBUG_XMIT | IWN_DEBUG_TRACE, "->%s begin\n", __func__); 5030 5031 IWN_LOCK(sc); 5032 if ((sc->sc_flags & IWN_FLAG_RUNNING) == 0) { 5033 m_freem(m); 5034 IWN_UNLOCK(sc); 5035 return (ENETDOWN); 5036 } 5037 5038 /* queue frame if we have to */ 5039 if (sc->sc_beacon_wait) { 5040 if (iwn_xmit_queue_enqueue(sc, m) != 0) { 5041 m_freem(m); 5042 IWN_UNLOCK(sc); 5043 return (ENOBUFS); 5044 } 5045 /* Queued, so just return OK */ 5046 IWN_UNLOCK(sc); 5047 return (0); 5048 } 5049 5050 if (params == NULL) { 5051 /* 5052 * Legacy path; interpret frame contents to decide 5053 * precisely how to send the frame. 5054 */ 5055 error = iwn_tx_data(sc, m, ni); 5056 } else { 5057 /* 5058 * Caller supplied explicit parameters to use in 5059 * sending the frame. 5060 */ 5061 error = iwn_tx_data_raw(sc, m, ni, params); 5062 } 5063 if (error == 0) 5064 sc->sc_tx_timer = 5; 5065 else 5066 m_freem(m); 5067 5068 IWN_UNLOCK(sc); 5069 5070 DPRINTF(sc, IWN_DEBUG_TRACE | IWN_DEBUG_XMIT, "->%s: end\n",__func__); 5071 5072 return (error); 5073 } 5074 5075 /* 5076 * transmit - don't free mbuf if failed; don't free node ref if failed. 5077 */ 5078 static int 5079 iwn_transmit(struct ieee80211com *ic, struct mbuf *m) 5080 { 5081 struct iwn_softc *sc = ic->ic_softc; 5082 struct ieee80211_node *ni; 5083 int error; 5084 5085 ni = (struct ieee80211_node *)m->m_pkthdr.rcvif; 5086 5087 IWN_LOCK(sc); 5088 if ((sc->sc_flags & IWN_FLAG_RUNNING) == 0 || sc->sc_beacon_wait) { 5089 IWN_UNLOCK(sc); 5090 return (ENXIO); 5091 } 5092 5093 if (sc->qfullmsk) { 5094 IWN_UNLOCK(sc); 5095 return (ENOBUFS); 5096 } 5097 5098 error = iwn_tx_data(sc, m, ni); 5099 if (!error) 5100 sc->sc_tx_timer = 5; 5101 IWN_UNLOCK(sc); 5102 return (error); 5103 } 5104 5105 static void 5106 iwn_scan_timeout(void *arg) 5107 { 5108 struct iwn_softc *sc = arg; 5109 struct ieee80211com *ic = &sc->sc_ic; 5110 5111 ic_printf(ic, "scan timeout\n"); 5112 ieee80211_restart_all(ic); 5113 } 5114 5115 static void 5116 iwn_watchdog(void *arg) 5117 { 5118 struct iwn_softc *sc = arg; 5119 struct ieee80211com *ic = &sc->sc_ic; 5120 5121 IWN_LOCK_ASSERT(sc); 5122 5123 KASSERT(sc->sc_flags & IWN_FLAG_RUNNING, ("not running")); 5124 5125 DPRINTF(sc, IWN_DEBUG_TRACE, "->Doing %s\n", __func__); 5126 5127 if (sc->sc_tx_timer > 0) { 5128 if (--sc->sc_tx_timer == 0) { 5129 ic_printf(ic, "device timeout\n"); 5130 ieee80211_restart_all(ic); 5131 return; 5132 } 5133 } 5134 callout_reset(&sc->watchdog_to, hz, iwn_watchdog, sc); 5135 } 5136 5137 static int 5138 iwn_cdev_open(struct cdev *dev, int flags, int type, struct thread *td) 5139 { 5140 5141 return (0); 5142 } 5143 5144 static int 5145 iwn_cdev_close(struct cdev *dev, int flags, int type, struct thread *td) 5146 { 5147 5148 return (0); 5149 } 5150 5151 static int 5152 iwn_cdev_ioctl(struct cdev *dev, unsigned long cmd, caddr_t data, int fflag, 5153 struct thread *td) 5154 { 5155 int rc; 5156 struct iwn_softc *sc = dev->si_drv1; 5157 struct iwn_ioctl_data *d; 5158 5159 rc = priv_check(td, PRIV_DRIVER); 5160 if (rc != 0) 5161 return (0); 5162 5163 switch (cmd) { 5164 case SIOCGIWNSTATS: 5165 d = (struct iwn_ioctl_data *) data; 5166 IWN_LOCK(sc); 5167 /* XXX validate permissions/memory/etc? */ 5168 rc = copyout(&sc->last_stat, d->dst_addr, sizeof(struct iwn_stats)); 5169 IWN_UNLOCK(sc); 5170 break; 5171 case SIOCZIWNSTATS: 5172 IWN_LOCK(sc); 5173 memset(&sc->last_stat, 0, sizeof(struct iwn_stats)); 5174 IWN_UNLOCK(sc); 5175 break; 5176 default: 5177 rc = EINVAL; 5178 break; 5179 } 5180 return (rc); 5181 } 5182 5183 static int 5184 iwn_ioctl(struct ieee80211com *ic, u_long cmd, void *data) 5185 { 5186 5187 return (ENOTTY); 5188 } 5189 5190 static void 5191 iwn_parent(struct ieee80211com *ic) 5192 { 5193 struct iwn_softc *sc = ic->ic_softc; 5194 struct ieee80211vap *vap; 5195 int error; 5196 5197 if (ic->ic_nrunning > 0) { 5198 error = iwn_init(sc); 5199 5200 switch (error) { 5201 case 0: 5202 ieee80211_start_all(ic); 5203 break; 5204 case 1: 5205 /* radio is disabled via RFkill switch */ 5206 taskqueue_enqueue(sc->sc_tq, &sc->sc_rftoggle_task); 5207 break; 5208 default: 5209 vap = TAILQ_FIRST(&ic->ic_vaps); 5210 if (vap != NULL) 5211 ieee80211_stop(vap); 5212 break; 5213 } 5214 } else 5215 iwn_stop(sc); 5216 } 5217 5218 /* 5219 * Send a command to the firmware. 5220 */ 5221 static int 5222 iwn_cmd(struct iwn_softc *sc, int code, const void *buf, int size, int async) 5223 { 5224 struct iwn_tx_ring *ring; 5225 struct iwn_tx_desc *desc; 5226 struct iwn_tx_data *data; 5227 struct iwn_tx_cmd *cmd; 5228 struct mbuf *m; 5229 bus_addr_t paddr; 5230 int totlen, error; 5231 int cmd_queue_num; 5232 5233 DPRINTF(sc, IWN_DEBUG_TRACE, "->%s begin\n", __func__); 5234 5235 if (async == 0) 5236 IWN_LOCK_ASSERT(sc); 5237 5238 if (sc->sc_flags & IWN_FLAG_PAN_SUPPORT) 5239 cmd_queue_num = IWN_PAN_CMD_QUEUE; 5240 else 5241 cmd_queue_num = IWN_CMD_QUEUE_NUM; 5242 5243 ring = &sc->txq[cmd_queue_num]; 5244 desc = &ring->desc[ring->cur]; 5245 data = &ring->data[ring->cur]; 5246 totlen = 4 + size; 5247 5248 if (size > sizeof cmd->data) { 5249 /* Command is too large to fit in a descriptor. */ 5250 if (totlen > MCLBYTES) 5251 return EINVAL; 5252 m = m_getjcl(M_NOWAIT, MT_DATA, M_PKTHDR, MJUMPAGESIZE); 5253 if (m == NULL) 5254 return ENOMEM; 5255 cmd = mtod(m, struct iwn_tx_cmd *); 5256 error = bus_dmamap_load(ring->data_dmat, data->map, cmd, 5257 totlen, iwn_dma_map_addr, &paddr, BUS_DMA_NOWAIT); 5258 if (error != 0) { 5259 m_freem(m); 5260 return error; 5261 } 5262 data->m = m; 5263 } else { 5264 cmd = &ring->cmd[ring->cur]; 5265 paddr = data->cmd_paddr; 5266 } 5267 5268 cmd->code = code; 5269 cmd->flags = 0; 5270 cmd->qid = ring->qid; 5271 cmd->idx = ring->cur; 5272 memcpy(cmd->data, buf, size); 5273 5274 desc->nsegs = 1; 5275 desc->segs[0].addr = htole32(IWN_LOADDR(paddr)); 5276 desc->segs[0].len = htole16(IWN_HIADDR(paddr) | totlen << 4); 5277 5278 DPRINTF(sc, IWN_DEBUG_CMD, "%s: %s (0x%x) flags %d qid %d idx %d\n", 5279 __func__, iwn_intr_str(cmd->code), cmd->code, 5280 cmd->flags, cmd->qid, cmd->idx); 5281 5282 if (size > sizeof cmd->data) { 5283 bus_dmamap_sync(ring->data_dmat, data->map, 5284 BUS_DMASYNC_PREWRITE); 5285 } else { 5286 bus_dmamap_sync(ring->cmd_dma.tag, ring->cmd_dma.map, 5287 BUS_DMASYNC_PREWRITE); 5288 } 5289 bus_dmamap_sync(ring->desc_dma.tag, ring->desc_dma.map, 5290 BUS_DMASYNC_PREWRITE); 5291 5292 /* Kick command ring. */ 5293 ring->cur = (ring->cur + 1) % IWN_TX_RING_COUNT; 5294 IWN_WRITE(sc, IWN_HBUS_TARG_WRPTR, ring->qid << 8 | ring->cur); 5295 5296 DPRINTF(sc, IWN_DEBUG_TRACE, "->%s: end\n",__func__); 5297 5298 return async ? 0 : msleep(desc, &sc->sc_mtx, PCATCH, "iwncmd", hz); 5299 } 5300 5301 static int 5302 iwn4965_add_node(struct iwn_softc *sc, struct iwn_node_info *node, int async) 5303 { 5304 struct iwn4965_node_info hnode; 5305 caddr_t src, dst; 5306 5307 DPRINTF(sc, IWN_DEBUG_TRACE, "->Doing %s\n", __func__); 5308 5309 /* 5310 * We use the node structure for 5000 Series internally (it is 5311 * a superset of the one for 4965AGN). We thus copy the common 5312 * fields before sending the command. 5313 */ 5314 src = (caddr_t)node; 5315 dst = (caddr_t)&hnode; 5316 memcpy(dst, src, 48); 5317 /* Skip TSC, RX MIC and TX MIC fields from ``src''. */ 5318 memcpy(dst + 48, src + 72, 20); 5319 return iwn_cmd(sc, IWN_CMD_ADD_NODE, &hnode, sizeof hnode, async); 5320 } 5321 5322 static int 5323 iwn5000_add_node(struct iwn_softc *sc, struct iwn_node_info *node, int async) 5324 { 5325 5326 DPRINTF(sc, IWN_DEBUG_TRACE, "->Doing %s\n", __func__); 5327 5328 /* Direct mapping. */ 5329 return iwn_cmd(sc, IWN_CMD_ADD_NODE, node, sizeof (*node), async); 5330 } 5331 5332 static int 5333 iwn_set_link_quality(struct iwn_softc *sc, struct ieee80211_node *ni) 5334 { 5335 struct iwn_node *wn = (void *)ni; 5336 struct ieee80211_rateset *rs; 5337 struct iwn_cmd_link_quality linkq; 5338 int i, rate, txrate; 5339 int is_11n; 5340 5341 DPRINTF(sc, IWN_DEBUG_TRACE, "->%s begin\n", __func__); 5342 5343 memset(&linkq, 0, sizeof linkq); 5344 linkq.id = wn->id; 5345 linkq.antmsk_1stream = iwn_get_1stream_tx_antmask(sc); 5346 linkq.antmsk_2stream = iwn_get_2stream_tx_antmask(sc); 5347 5348 linkq.ampdu_max = 32; /* XXX negotiated? */ 5349 linkq.ampdu_threshold = 3; 5350 linkq.ampdu_limit = htole16(4000); /* 4ms */ 5351 5352 DPRINTF(sc, IWN_DEBUG_XMIT, 5353 "%s: 1stream antenna=0x%02x, 2stream antenna=0x%02x, ntxstreams=%d\n", 5354 __func__, 5355 linkq.antmsk_1stream, 5356 linkq.antmsk_2stream, 5357 sc->ntxchains); 5358 5359 /* 5360 * Are we using 11n rates? Ensure the channel is 5361 * 11n _and_ we have some 11n rates, or don't 5362 * try. 5363 */ 5364 if (IEEE80211_IS_CHAN_HT(ni->ni_chan) && ni->ni_htrates.rs_nrates > 0) { 5365 rs = (struct ieee80211_rateset *) &ni->ni_htrates; 5366 is_11n = 1; 5367 } else { 5368 rs = &ni->ni_rates; 5369 is_11n = 0; 5370 } 5371 5372 /* Start at highest available bit-rate. */ 5373 /* 5374 * XXX this is all very dirty! 5375 */ 5376 if (is_11n) 5377 txrate = ni->ni_htrates.rs_nrates - 1; 5378 else 5379 txrate = rs->rs_nrates - 1; 5380 for (i = 0; i < IWN_MAX_TX_RETRIES; i++) { 5381 uint32_t plcp; 5382 5383 /* 5384 * XXX TODO: ensure the last two slots are the two lowest 5385 * rate entries, just for now. 5386 */ 5387 if (i == 14 || i == 15) 5388 txrate = 0; 5389 5390 if (is_11n) 5391 rate = IEEE80211_RATE_MCS | rs->rs_rates[txrate]; 5392 else 5393 rate = IEEE80211_RV(rs->rs_rates[txrate]); 5394 5395 /* Do rate -> PLCP config mapping */ 5396 plcp = iwn_rate_to_plcp(sc, ni, rate); 5397 linkq.retry[i] = plcp; 5398 DPRINTF(sc, IWN_DEBUG_XMIT, 5399 "%s: i=%d, txrate=%d, rate=0x%02x, plcp=0x%08x\n", 5400 __func__, 5401 i, 5402 txrate, 5403 rate, 5404 le32toh(plcp)); 5405 5406 /* 5407 * The mimo field is an index into the table which 5408 * indicates the first index where it and subsequent entries 5409 * will not be using MIMO. 5410 * 5411 * Since we're filling linkq from 0..15 and we're filling 5412 * from the highest MCS rates to the lowest rates, if we 5413 * _are_ doing a dual-stream rate, set mimo to idx+1 (ie, 5414 * the next entry.) That way if the next entry is a non-MIMO 5415 * entry, we're already pointing at it. 5416 */ 5417 if ((le32toh(plcp) & IWN_RFLAG_MCS) && 5418 IEEE80211_RV(le32toh(plcp)) > 7) 5419 linkq.mimo = i + 1; 5420 5421 /* Next retry at immediate lower bit-rate. */ 5422 if (txrate > 0) 5423 txrate--; 5424 } 5425 /* 5426 * If we reached the end of the list and indeed we hit 5427 * all MIMO rates (eg 5300 doing MCS23-15) then yes, 5428 * set mimo to 15. Setting it to 16 panics the firmware. 5429 */ 5430 if (linkq.mimo > 15) 5431 linkq.mimo = 15; 5432 5433 DPRINTF(sc, IWN_DEBUG_XMIT, "%s: mimo = %d\n", __func__, linkq.mimo); 5434 5435 DPRINTF(sc, IWN_DEBUG_TRACE, "->%s: end\n",__func__); 5436 5437 return iwn_cmd(sc, IWN_CMD_LINK_QUALITY, &linkq, sizeof linkq, 1); 5438 } 5439 5440 /* 5441 * Broadcast node is used to send group-addressed and management frames. 5442 */ 5443 static int 5444 iwn_add_broadcast_node(struct iwn_softc *sc, int async) 5445 { 5446 struct iwn_ops *ops = &sc->ops; 5447 struct ieee80211com *ic = &sc->sc_ic; 5448 struct iwn_node_info node; 5449 struct iwn_cmd_link_quality linkq; 5450 uint8_t txant; 5451 int i, error; 5452 5453 DPRINTF(sc, IWN_DEBUG_TRACE, "->%s begin\n", __func__); 5454 5455 sc->rxon = &sc->rx_on[IWN_RXON_BSS_CTX]; 5456 5457 memset(&node, 0, sizeof node); 5458 IEEE80211_ADDR_COPY(node.macaddr, ieee80211broadcastaddr); 5459 node.id = sc->broadcast_id; 5460 DPRINTF(sc, IWN_DEBUG_RESET, "%s: adding broadcast node\n", __func__); 5461 if ((error = ops->add_node(sc, &node, async)) != 0) 5462 return error; 5463 5464 /* Use the first valid TX antenna. */ 5465 txant = IWN_LSB(sc->txchainmask); 5466 5467 memset(&linkq, 0, sizeof linkq); 5468 linkq.id = sc->broadcast_id; 5469 linkq.antmsk_1stream = iwn_get_1stream_tx_antmask(sc); 5470 linkq.antmsk_2stream = iwn_get_2stream_tx_antmask(sc); 5471 linkq.ampdu_max = 64; 5472 linkq.ampdu_threshold = 3; 5473 linkq.ampdu_limit = htole16(4000); /* 4ms */ 5474 5475 /* Use lowest mandatory bit-rate. */ 5476 /* XXX rate table lookup? */ 5477 if (IEEE80211_IS_CHAN_5GHZ(ic->ic_curchan)) 5478 linkq.retry[0] = htole32(0xd); 5479 else 5480 linkq.retry[0] = htole32(10 | IWN_RFLAG_CCK); 5481 linkq.retry[0] |= htole32(IWN_RFLAG_ANT(txant)); 5482 /* Use same bit-rate for all TX retries. */ 5483 for (i = 1; i < IWN_MAX_TX_RETRIES; i++) { 5484 linkq.retry[i] = linkq.retry[0]; 5485 } 5486 5487 DPRINTF(sc, IWN_DEBUG_TRACE, "->%s: end\n",__func__); 5488 5489 return iwn_cmd(sc, IWN_CMD_LINK_QUALITY, &linkq, sizeof linkq, async); 5490 } 5491 5492 static int 5493 iwn_updateedca(struct ieee80211com *ic) 5494 { 5495 #define IWN_EXP2(x) ((1 << (x)) - 1) /* CWmin = 2^ECWmin - 1 */ 5496 struct iwn_softc *sc = ic->ic_softc; 5497 struct iwn_edca_params cmd; 5498 struct chanAccParams chp; 5499 int aci; 5500 5501 DPRINTF(sc, IWN_DEBUG_TRACE, "->%s begin\n", __func__); 5502 5503 ieee80211_wme_ic_getparams(ic, &chp); 5504 5505 memset(&cmd, 0, sizeof cmd); 5506 cmd.flags = htole32(IWN_EDCA_UPDATE); 5507 5508 IEEE80211_LOCK(ic); 5509 for (aci = 0; aci < WME_NUM_AC; aci++) { 5510 const struct wmeParams *ac = &chp.cap_wmeParams[aci]; 5511 cmd.ac[aci].aifsn = ac->wmep_aifsn; 5512 cmd.ac[aci].cwmin = htole16(IWN_EXP2(ac->wmep_logcwmin)); 5513 cmd.ac[aci].cwmax = htole16(IWN_EXP2(ac->wmep_logcwmax)); 5514 cmd.ac[aci].txoplimit = 5515 htole16(IEEE80211_TXOP_TO_US(ac->wmep_txopLimit)); 5516 } 5517 IEEE80211_UNLOCK(ic); 5518 5519 IWN_LOCK(sc); 5520 (void)iwn_cmd(sc, IWN_CMD_EDCA_PARAMS, &cmd, sizeof cmd, 1); 5521 IWN_UNLOCK(sc); 5522 5523 DPRINTF(sc, IWN_DEBUG_TRACE, "->%s: end\n",__func__); 5524 5525 return 0; 5526 #undef IWN_EXP2 5527 } 5528 5529 static void 5530 iwn_set_promisc(struct iwn_softc *sc) 5531 { 5532 struct ieee80211com *ic = &sc->sc_ic; 5533 uint32_t promisc_filter; 5534 5535 promisc_filter = IWN_FILTER_CTL | IWN_FILTER_PROMISC; 5536 if (ic->ic_promisc > 0 || ic->ic_opmode == IEEE80211_M_MONITOR) 5537 sc->rxon->filter |= htole32(promisc_filter); 5538 else 5539 sc->rxon->filter &= ~htole32(promisc_filter); 5540 } 5541 5542 static void 5543 iwn_update_promisc(struct ieee80211com *ic) 5544 { 5545 struct iwn_softc *sc = ic->ic_softc; 5546 int error; 5547 5548 if (ic->ic_opmode == IEEE80211_M_MONITOR) 5549 return; /* nothing to do */ 5550 5551 IWN_LOCK(sc); 5552 if (!(sc->sc_flags & IWN_FLAG_RUNNING)) { 5553 IWN_UNLOCK(sc); 5554 return; 5555 } 5556 5557 iwn_set_promisc(sc); 5558 if ((error = iwn_send_rxon(sc, 1, 1)) != 0) { 5559 device_printf(sc->sc_dev, 5560 "%s: could not send RXON, error %d\n", 5561 __func__, error); 5562 } 5563 IWN_UNLOCK(sc); 5564 } 5565 5566 static void 5567 iwn_update_mcast(struct ieee80211com *ic) 5568 { 5569 /* Ignore */ 5570 } 5571 5572 static void 5573 iwn_set_led(struct iwn_softc *sc, uint8_t which, uint8_t off, uint8_t on) 5574 { 5575 struct iwn_cmd_led led; 5576 5577 DPRINTF(sc, IWN_DEBUG_TRACE, "->Doing %s\n", __func__); 5578 5579 #if 0 5580 /* XXX don't set LEDs during scan? */ 5581 if (sc->sc_is_scanning) 5582 return; 5583 #endif 5584 5585 /* Clear microcode LED ownership. */ 5586 IWN_CLRBITS(sc, IWN_LED, IWN_LED_BSM_CTRL); 5587 5588 led.which = which; 5589 led.unit = htole32(10000); /* on/off in unit of 100ms */ 5590 led.off = off; 5591 led.on = on; 5592 (void)iwn_cmd(sc, IWN_CMD_SET_LED, &led, sizeof led, 1); 5593 } 5594 5595 /* 5596 * Set the critical temperature at which the firmware will stop the radio 5597 * and notify us. 5598 */ 5599 static int 5600 iwn_set_critical_temp(struct iwn_softc *sc) 5601 { 5602 struct iwn_critical_temp crit; 5603 int32_t temp; 5604 5605 DPRINTF(sc, IWN_DEBUG_TRACE, "->Doing %s\n", __func__); 5606 5607 IWN_WRITE(sc, IWN_UCODE_GP1_CLR, IWN_UCODE_GP1_CTEMP_STOP_RF); 5608 5609 if (sc->hw_type == IWN_HW_REV_TYPE_5150) 5610 temp = (IWN_CTOK(110) - sc->temp_off) * -5; 5611 else if (sc->hw_type == IWN_HW_REV_TYPE_4965) 5612 temp = IWN_CTOK(110); 5613 else 5614 temp = 110; 5615 memset(&crit, 0, sizeof crit); 5616 crit.tempR = htole32(temp); 5617 DPRINTF(sc, IWN_DEBUG_RESET, "setting critical temp to %d\n", temp); 5618 return iwn_cmd(sc, IWN_CMD_SET_CRITICAL_TEMP, &crit, sizeof crit, 0); 5619 } 5620 5621 static int 5622 iwn_set_timing(struct iwn_softc *sc, struct ieee80211_node *ni) 5623 { 5624 struct iwn_cmd_timing cmd; 5625 uint64_t val, mod; 5626 5627 DPRINTF(sc, IWN_DEBUG_TRACE, "->Doing %s\n", __func__); 5628 5629 memset(&cmd, 0, sizeof cmd); 5630 memcpy(&cmd.tstamp, ni->ni_tstamp.data, sizeof (uint64_t)); 5631 cmd.bintval = htole16(ni->ni_intval); 5632 cmd.lintval = htole16(10); 5633 5634 /* Compute remaining time until next beacon. */ 5635 val = (uint64_t)ni->ni_intval * IEEE80211_DUR_TU; 5636 mod = le64toh(cmd.tstamp) % val; 5637 cmd.binitval = htole32((uint32_t)(val - mod)); 5638 5639 DPRINTF(sc, IWN_DEBUG_RESET, "timing bintval=%u tstamp=%ju, init=%u\n", 5640 ni->ni_intval, le64toh(cmd.tstamp), (uint32_t)(val - mod)); 5641 5642 return iwn_cmd(sc, IWN_CMD_TIMING, &cmd, sizeof cmd, 1); 5643 } 5644 5645 static void 5646 iwn4965_power_calibration(struct iwn_softc *sc, int temp) 5647 { 5648 5649 DPRINTF(sc, IWN_DEBUG_TRACE, "->Doing %s\n", __func__); 5650 5651 /* Adjust TX power if need be (delta >= 3 degC). */ 5652 DPRINTF(sc, IWN_DEBUG_CALIBRATE, "%s: temperature %d->%d\n", 5653 __func__, sc->temp, temp); 5654 if (abs(temp - sc->temp) >= 3) { 5655 /* Record temperature of last calibration. */ 5656 sc->temp = temp; 5657 (void)iwn4965_set_txpower(sc, 1); 5658 } 5659 } 5660 5661 /* 5662 * Set TX power for current channel (each rate has its own power settings). 5663 * This function takes into account the regulatory information from EEPROM, 5664 * the current temperature and the current voltage. 5665 */ 5666 static int 5667 iwn4965_set_txpower(struct iwn_softc *sc, int async) 5668 { 5669 /* Fixed-point arithmetic division using a n-bit fractional part. */ 5670 #define fdivround(a, b, n) \ 5671 ((((1 << n) * (a)) / (b) + (1 << n) / 2) / (1 << n)) 5672 /* Linear interpolation. */ 5673 #define interpolate(x, x1, y1, x2, y2, n) \ 5674 ((y1) + fdivround(((int)(x) - (x1)) * ((y2) - (y1)), (x2) - (x1), n)) 5675 5676 static const int tdiv[IWN_NATTEN_GROUPS] = { 9, 8, 8, 8, 6 }; 5677 struct iwn_ucode_info *uc = &sc->ucode_info; 5678 struct iwn4965_cmd_txpower cmd; 5679 struct iwn4965_eeprom_chan_samples *chans; 5680 const uint8_t *rf_gain, *dsp_gain; 5681 int32_t vdiff, tdiff; 5682 int i, is_chan_5ghz, c, grp, maxpwr; 5683 uint8_t chan; 5684 5685 sc->rxon = &sc->rx_on[IWN_RXON_BSS_CTX]; 5686 /* Retrieve current channel from last RXON. */ 5687 chan = sc->rxon->chan; 5688 is_chan_5ghz = (sc->rxon->flags & htole32(IWN_RXON_24GHZ)) == 0; 5689 DPRINTF(sc, IWN_DEBUG_RESET, "setting TX power for channel %d\n", 5690 chan); 5691 5692 memset(&cmd, 0, sizeof cmd); 5693 cmd.band = is_chan_5ghz ? 0 : 1; 5694 cmd.chan = chan; 5695 5696 if (is_chan_5ghz) { 5697 maxpwr = sc->maxpwr5GHz; 5698 rf_gain = iwn4965_rf_gain_5ghz; 5699 dsp_gain = iwn4965_dsp_gain_5ghz; 5700 } else { 5701 maxpwr = sc->maxpwr2GHz; 5702 rf_gain = iwn4965_rf_gain_2ghz; 5703 dsp_gain = iwn4965_dsp_gain_2ghz; 5704 } 5705 5706 /* Compute voltage compensation. */ 5707 vdiff = ((int32_t)le32toh(uc->volt) - sc->eeprom_voltage) / 7; 5708 if (vdiff > 0) 5709 vdiff *= 2; 5710 if (abs(vdiff) > 2) 5711 vdiff = 0; 5712 DPRINTF(sc, IWN_DEBUG_CALIBRATE | IWN_DEBUG_TXPOW, 5713 "%s: voltage compensation=%d (UCODE=%d, EEPROM=%d)\n", 5714 __func__, vdiff, le32toh(uc->volt), sc->eeprom_voltage); 5715 5716 /* Get channel attenuation group. */ 5717 if (chan <= 20) /* 1-20 */ 5718 grp = 4; 5719 else if (chan <= 43) /* 34-43 */ 5720 grp = 0; 5721 else if (chan <= 70) /* 44-70 */ 5722 grp = 1; 5723 else if (chan <= 124) /* 71-124 */ 5724 grp = 2; 5725 else /* 125-200 */ 5726 grp = 3; 5727 DPRINTF(sc, IWN_DEBUG_CALIBRATE | IWN_DEBUG_TXPOW, 5728 "%s: chan %d, attenuation group=%d\n", __func__, chan, grp); 5729 5730 /* Get channel sub-band. */ 5731 for (i = 0; i < IWN_NBANDS; i++) 5732 if (sc->bands[i].lo != 0 && 5733 sc->bands[i].lo <= chan && chan <= sc->bands[i].hi) 5734 break; 5735 if (i == IWN_NBANDS) /* Can't happen in real-life. */ 5736 return EINVAL; 5737 chans = sc->bands[i].chans; 5738 DPRINTF(sc, IWN_DEBUG_CALIBRATE | IWN_DEBUG_TXPOW, 5739 "%s: chan %d sub-band=%d\n", __func__, chan, i); 5740 5741 for (c = 0; c < 2; c++) { 5742 uint8_t power, gain, temp; 5743 int maxchpwr, pwr, ridx, idx; 5744 5745 power = interpolate(chan, 5746 chans[0].num, chans[0].samples[c][1].power, 5747 chans[1].num, chans[1].samples[c][1].power, 1); 5748 gain = interpolate(chan, 5749 chans[0].num, chans[0].samples[c][1].gain, 5750 chans[1].num, chans[1].samples[c][1].gain, 1); 5751 temp = interpolate(chan, 5752 chans[0].num, chans[0].samples[c][1].temp, 5753 chans[1].num, chans[1].samples[c][1].temp, 1); 5754 DPRINTF(sc, IWN_DEBUG_CALIBRATE | IWN_DEBUG_TXPOW, 5755 "%s: Tx chain %d: power=%d gain=%d temp=%d\n", 5756 __func__, c, power, gain, temp); 5757 5758 /* Compute temperature compensation. */ 5759 tdiff = ((sc->temp - temp) * 2) / tdiv[grp]; 5760 DPRINTF(sc, IWN_DEBUG_CALIBRATE | IWN_DEBUG_TXPOW, 5761 "%s: temperature compensation=%d (current=%d, EEPROM=%d)\n", 5762 __func__, tdiff, sc->temp, temp); 5763 5764 for (ridx = 0; ridx <= IWN_RIDX_MAX; ridx++) { 5765 /* Convert dBm to half-dBm. */ 5766 maxchpwr = sc->maxpwr[chan] * 2; 5767 if ((ridx / 8) & 1) 5768 maxchpwr -= 6; /* MIMO 2T: -3dB */ 5769 5770 pwr = maxpwr; 5771 5772 /* Adjust TX power based on rate. */ 5773 if ((ridx % 8) == 5) 5774 pwr -= 15; /* OFDM48: -7.5dB */ 5775 else if ((ridx % 8) == 6) 5776 pwr -= 17; /* OFDM54: -8.5dB */ 5777 else if ((ridx % 8) == 7) 5778 pwr -= 20; /* OFDM60: -10dB */ 5779 else 5780 pwr -= 10; /* Others: -5dB */ 5781 5782 /* Do not exceed channel max TX power. */ 5783 if (pwr > maxchpwr) 5784 pwr = maxchpwr; 5785 5786 idx = gain - (pwr - power) - tdiff - vdiff; 5787 if ((ridx / 8) & 1) /* MIMO */ 5788 idx += (int32_t)le32toh(uc->atten[grp][c]); 5789 5790 if (cmd.band == 0) 5791 idx += 9; /* 5GHz */ 5792 if (ridx == IWN_RIDX_MAX) 5793 idx += 5; /* CCK */ 5794 5795 /* Make sure idx stays in a valid range. */ 5796 if (idx < 0) 5797 idx = 0; 5798 else if (idx > IWN4965_MAX_PWR_INDEX) 5799 idx = IWN4965_MAX_PWR_INDEX; 5800 5801 DPRINTF(sc, IWN_DEBUG_CALIBRATE | IWN_DEBUG_TXPOW, 5802 "%s: Tx chain %d, rate idx %d: power=%d\n", 5803 __func__, c, ridx, idx); 5804 cmd.power[ridx].rf_gain[c] = rf_gain[idx]; 5805 cmd.power[ridx].dsp_gain[c] = dsp_gain[idx]; 5806 } 5807 } 5808 5809 DPRINTF(sc, IWN_DEBUG_CALIBRATE | IWN_DEBUG_TXPOW, 5810 "%s: set tx power for chan %d\n", __func__, chan); 5811 return iwn_cmd(sc, IWN_CMD_TXPOWER, &cmd, sizeof cmd, async); 5812 5813 #undef interpolate 5814 #undef fdivround 5815 } 5816 5817 static int 5818 iwn5000_set_txpower(struct iwn_softc *sc, int async) 5819 { 5820 struct iwn5000_cmd_txpower cmd; 5821 int cmdid; 5822 5823 DPRINTF(sc, IWN_DEBUG_TRACE, "->Doing %s\n", __func__); 5824 5825 /* 5826 * TX power calibration is handled automatically by the firmware 5827 * for 5000 Series. 5828 */ 5829 memset(&cmd, 0, sizeof cmd); 5830 cmd.global_limit = 2 * IWN5000_TXPOWER_MAX_DBM; /* 16 dBm */ 5831 cmd.flags = IWN5000_TXPOWER_NO_CLOSED; 5832 cmd.srv_limit = IWN5000_TXPOWER_AUTO; 5833 DPRINTF(sc, IWN_DEBUG_CALIBRATE | IWN_DEBUG_XMIT, 5834 "%s: setting TX power; rev=%d\n", 5835 __func__, 5836 IWN_UCODE_API(sc->ucode_rev)); 5837 if (IWN_UCODE_API(sc->ucode_rev) == 1) 5838 cmdid = IWN_CMD_TXPOWER_DBM_V1; 5839 else 5840 cmdid = IWN_CMD_TXPOWER_DBM; 5841 return iwn_cmd(sc, cmdid, &cmd, sizeof cmd, async); 5842 } 5843 5844 /* 5845 * Retrieve the maximum RSSI (in dBm) among receivers. 5846 */ 5847 static int 5848 iwn4965_get_rssi(struct iwn_softc *sc, struct iwn_rx_stat *stat) 5849 { 5850 struct iwn4965_rx_phystat *phy = (void *)stat->phybuf; 5851 uint8_t mask, agc; 5852 int rssi; 5853 5854 DPRINTF(sc, IWN_DEBUG_TRACE, "->Doing %s\n", __func__); 5855 5856 mask = (le16toh(phy->antenna) >> 4) & IWN_ANT_ABC; 5857 agc = (le16toh(phy->agc) >> 7) & 0x7f; 5858 5859 rssi = 0; 5860 if (mask & IWN_ANT_A) 5861 rssi = MAX(rssi, phy->rssi[0]); 5862 if (mask & IWN_ANT_B) 5863 rssi = MAX(rssi, phy->rssi[2]); 5864 if (mask & IWN_ANT_C) 5865 rssi = MAX(rssi, phy->rssi[4]); 5866 5867 DPRINTF(sc, IWN_DEBUG_RECV, 5868 "%s: agc %d mask 0x%x rssi %d %d %d result %d\n", __func__, agc, 5869 mask, phy->rssi[0], phy->rssi[2], phy->rssi[4], 5870 rssi - agc - IWN_RSSI_TO_DBM); 5871 return rssi - agc - IWN_RSSI_TO_DBM; 5872 } 5873 5874 static int 5875 iwn5000_get_rssi(struct iwn_softc *sc, struct iwn_rx_stat *stat) 5876 { 5877 struct iwn5000_rx_phystat *phy = (void *)stat->phybuf; 5878 uint8_t agc; 5879 int rssi; 5880 5881 DPRINTF(sc, IWN_DEBUG_TRACE, "->Doing %s\n", __func__); 5882 5883 agc = (le32toh(phy->agc) >> 9) & 0x7f; 5884 5885 rssi = MAX(le16toh(phy->rssi[0]) & 0xff, 5886 le16toh(phy->rssi[1]) & 0xff); 5887 rssi = MAX(le16toh(phy->rssi[2]) & 0xff, rssi); 5888 5889 DPRINTF(sc, IWN_DEBUG_RECV, 5890 "%s: agc %d rssi %d %d %d result %d\n", __func__, agc, 5891 phy->rssi[0], phy->rssi[1], phy->rssi[2], 5892 rssi - agc - IWN_RSSI_TO_DBM); 5893 return rssi - agc - IWN_RSSI_TO_DBM; 5894 } 5895 5896 /* 5897 * Retrieve the average noise (in dBm) among receivers. 5898 */ 5899 static int 5900 iwn_get_noise(const struct iwn_rx_general_stats *stats) 5901 { 5902 int i, total, nbant, noise; 5903 5904 total = nbant = 0; 5905 for (i = 0; i < 3; i++) { 5906 if ((noise = le32toh(stats->noise[i]) & 0xff) == 0) 5907 continue; 5908 total += noise; 5909 nbant++; 5910 } 5911 /* There should be at least one antenna but check anyway. */ 5912 return (nbant == 0) ? -127 : (total / nbant) - 107; 5913 } 5914 5915 /* 5916 * Compute temperature (in degC) from last received statistics. 5917 */ 5918 static int 5919 iwn4965_get_temperature(struct iwn_softc *sc) 5920 { 5921 struct iwn_ucode_info *uc = &sc->ucode_info; 5922 int32_t r1, r2, r3, r4, temp; 5923 5924 DPRINTF(sc, IWN_DEBUG_TRACE, "->Doing %s\n", __func__); 5925 5926 r1 = le32toh(uc->temp[0].chan20MHz); 5927 r2 = le32toh(uc->temp[1].chan20MHz); 5928 r3 = le32toh(uc->temp[2].chan20MHz); 5929 r4 = le32toh(sc->rawtemp); 5930 5931 if (r1 == r3) /* Prevents division by 0 (should not happen). */ 5932 return 0; 5933 5934 /* Sign-extend 23-bit R4 value to 32-bit. */ 5935 r4 = ((r4 & 0xffffff) ^ 0x800000) - 0x800000; 5936 /* Compute temperature in Kelvin. */ 5937 temp = (259 * (r4 - r2)) / (r3 - r1); 5938 temp = (temp * 97) / 100 + 8; 5939 5940 DPRINTF(sc, IWN_DEBUG_ANY, "temperature %dK/%dC\n", temp, 5941 IWN_KTOC(temp)); 5942 return IWN_KTOC(temp); 5943 } 5944 5945 static int 5946 iwn5000_get_temperature(struct iwn_softc *sc) 5947 { 5948 int32_t temp; 5949 5950 DPRINTF(sc, IWN_DEBUG_TRACE, "->Doing %s\n", __func__); 5951 5952 /* 5953 * Temperature is not used by the driver for 5000 Series because 5954 * TX power calibration is handled by firmware. 5955 */ 5956 temp = le32toh(sc->rawtemp); 5957 if (sc->hw_type == IWN_HW_REV_TYPE_5150) { 5958 temp = (temp / -5) + sc->temp_off; 5959 temp = IWN_KTOC(temp); 5960 } 5961 return temp; 5962 } 5963 5964 /* 5965 * Initialize sensitivity calibration state machine. 5966 */ 5967 static int 5968 iwn_init_sensitivity(struct iwn_softc *sc) 5969 { 5970 struct iwn_ops *ops = &sc->ops; 5971 struct iwn_calib_state *calib = &sc->calib; 5972 uint32_t flags; 5973 int error; 5974 5975 DPRINTF(sc, IWN_DEBUG_TRACE, "->Doing %s\n", __func__); 5976 5977 /* Reset calibration state machine. */ 5978 memset(calib, 0, sizeof (*calib)); 5979 calib->state = IWN_CALIB_STATE_INIT; 5980 calib->cck_state = IWN_CCK_STATE_HIFA; 5981 /* Set initial correlation values. */ 5982 calib->ofdm_x1 = sc->limits->min_ofdm_x1; 5983 calib->ofdm_mrc_x1 = sc->limits->min_ofdm_mrc_x1; 5984 calib->ofdm_x4 = sc->limits->min_ofdm_x4; 5985 calib->ofdm_mrc_x4 = sc->limits->min_ofdm_mrc_x4; 5986 calib->cck_x4 = 125; 5987 calib->cck_mrc_x4 = sc->limits->min_cck_mrc_x4; 5988 calib->energy_cck = sc->limits->energy_cck; 5989 5990 /* Write initial sensitivity. */ 5991 if ((error = iwn_send_sensitivity(sc)) != 0) 5992 return error; 5993 5994 /* Write initial gains. */ 5995 if ((error = ops->init_gains(sc)) != 0) 5996 return error; 5997 5998 /* Request statistics at each beacon interval. */ 5999 flags = 0; 6000 DPRINTF(sc, IWN_DEBUG_CALIBRATE, "%s: sending request for statistics\n", 6001 __func__); 6002 return iwn_cmd(sc, IWN_CMD_GET_STATISTICS, &flags, sizeof flags, 1); 6003 } 6004 6005 /* 6006 * Collect noise and RSSI statistics for the first 20 beacons received 6007 * after association and use them to determine connected antennas and 6008 * to set differential gains. 6009 */ 6010 static void 6011 iwn_collect_noise(struct iwn_softc *sc, 6012 const struct iwn_rx_general_stats *stats) 6013 { 6014 struct iwn_ops *ops = &sc->ops; 6015 struct iwn_calib_state *calib = &sc->calib; 6016 struct ieee80211com *ic = &sc->sc_ic; 6017 uint32_t val; 6018 int i; 6019 6020 DPRINTF(sc, IWN_DEBUG_TRACE, "->%s begin\n", __func__); 6021 6022 /* Accumulate RSSI and noise for all 3 antennas. */ 6023 for (i = 0; i < 3; i++) { 6024 calib->rssi[i] += le32toh(stats->rssi[i]) & 0xff; 6025 calib->noise[i] += le32toh(stats->noise[i]) & 0xff; 6026 } 6027 /* NB: We update differential gains only once after 20 beacons. */ 6028 if (++calib->nbeacons < 20) 6029 return; 6030 6031 /* Determine highest average RSSI. */ 6032 val = MAX(calib->rssi[0], calib->rssi[1]); 6033 val = MAX(calib->rssi[2], val); 6034 6035 /* Determine which antennas are connected. */ 6036 sc->chainmask = sc->rxchainmask; 6037 for (i = 0; i < 3; i++) 6038 if (val - calib->rssi[i] > 15 * 20) 6039 sc->chainmask &= ~(1 << i); 6040 DPRINTF(sc, IWN_DEBUG_CALIBRATE | IWN_DEBUG_XMIT, 6041 "%s: RX chains mask: theoretical=0x%x, actual=0x%x\n", 6042 __func__, sc->rxchainmask, sc->chainmask); 6043 6044 /* If none of the TX antennas are connected, keep at least one. */ 6045 if ((sc->chainmask & sc->txchainmask) == 0) 6046 sc->chainmask |= IWN_LSB(sc->txchainmask); 6047 6048 (void)ops->set_gains(sc); 6049 calib->state = IWN_CALIB_STATE_RUN; 6050 6051 #ifdef notyet 6052 /* XXX Disable RX chains with no antennas connected. */ 6053 sc->rxon->rxchain = htole16(IWN_RXCHAIN_SEL(sc->chainmask)); 6054 if (sc->sc_is_scanning) 6055 device_printf(sc->sc_dev, 6056 "%s: is_scanning set, before RXON\n", 6057 __func__); 6058 (void)iwn_cmd(sc, IWN_CMD_RXON, sc->rxon, sc->rxonsz, 1); 6059 #endif 6060 6061 /* Enable power-saving mode if requested by user. */ 6062 if (ic->ic_flags & IEEE80211_F_PMGTON) 6063 (void)iwn_set_pslevel(sc, 0, 3, 1); 6064 6065 DPRINTF(sc, IWN_DEBUG_TRACE, "->%s: end\n",__func__); 6066 6067 } 6068 6069 static int 6070 iwn4965_init_gains(struct iwn_softc *sc) 6071 { 6072 struct iwn_phy_calib_gain cmd; 6073 6074 DPRINTF(sc, IWN_DEBUG_TRACE, "->Doing %s\n", __func__); 6075 6076 memset(&cmd, 0, sizeof cmd); 6077 cmd.code = IWN4965_PHY_CALIB_DIFF_GAIN; 6078 /* Differential gains initially set to 0 for all 3 antennas. */ 6079 DPRINTF(sc, IWN_DEBUG_CALIBRATE, 6080 "%s: setting initial differential gains\n", __func__); 6081 return iwn_cmd(sc, IWN_CMD_PHY_CALIB, &cmd, sizeof cmd, 1); 6082 } 6083 6084 static int 6085 iwn5000_init_gains(struct iwn_softc *sc) 6086 { 6087 struct iwn_phy_calib cmd; 6088 6089 DPRINTF(sc, IWN_DEBUG_TRACE, "->Doing %s\n", __func__); 6090 6091 memset(&cmd, 0, sizeof cmd); 6092 cmd.code = sc->reset_noise_gain; 6093 cmd.ngroups = 1; 6094 cmd.isvalid = 1; 6095 DPRINTF(sc, IWN_DEBUG_CALIBRATE, 6096 "%s: setting initial differential gains\n", __func__); 6097 return iwn_cmd(sc, IWN_CMD_PHY_CALIB, &cmd, sizeof cmd, 1); 6098 } 6099 6100 static int 6101 iwn4965_set_gains(struct iwn_softc *sc) 6102 { 6103 struct iwn_calib_state *calib = &sc->calib; 6104 struct iwn_phy_calib_gain cmd; 6105 int i, delta, noise; 6106 6107 DPRINTF(sc, IWN_DEBUG_TRACE, "->Doing %s\n", __func__); 6108 6109 /* Get minimal noise among connected antennas. */ 6110 noise = INT_MAX; /* NB: There's at least one antenna. */ 6111 for (i = 0; i < 3; i++) 6112 if (sc->chainmask & (1 << i)) 6113 noise = MIN(calib->noise[i], noise); 6114 6115 memset(&cmd, 0, sizeof cmd); 6116 cmd.code = IWN4965_PHY_CALIB_DIFF_GAIN; 6117 /* Set differential gains for connected antennas. */ 6118 for (i = 0; i < 3; i++) { 6119 if (sc->chainmask & (1 << i)) { 6120 /* Compute attenuation (in unit of 1.5dB). */ 6121 delta = (noise - (int32_t)calib->noise[i]) / 30; 6122 /* NB: delta <= 0 */ 6123 /* Limit to [-4.5dB,0]. */ 6124 cmd.gain[i] = MIN(abs(delta), 3); 6125 if (delta < 0) 6126 cmd.gain[i] |= 1 << 2; /* sign bit */ 6127 } 6128 } 6129 DPRINTF(sc, IWN_DEBUG_CALIBRATE, 6130 "setting differential gains Ant A/B/C: %x/%x/%x (%x)\n", 6131 cmd.gain[0], cmd.gain[1], cmd.gain[2], sc->chainmask); 6132 return iwn_cmd(sc, IWN_CMD_PHY_CALIB, &cmd, sizeof cmd, 1); 6133 } 6134 6135 static int 6136 iwn5000_set_gains(struct iwn_softc *sc) 6137 { 6138 struct iwn_calib_state *calib = &sc->calib; 6139 struct iwn_phy_calib_gain cmd; 6140 int i, ant, div, delta; 6141 6142 DPRINTF(sc, IWN_DEBUG_TRACE, "->Doing %s\n", __func__); 6143 6144 /* We collected 20 beacons and !=6050 need a 1.5 factor. */ 6145 div = (sc->hw_type == IWN_HW_REV_TYPE_6050) ? 20 : 30; 6146 6147 memset(&cmd, 0, sizeof cmd); 6148 cmd.code = sc->noise_gain; 6149 cmd.ngroups = 1; 6150 cmd.isvalid = 1; 6151 /* Get first available RX antenna as referential. */ 6152 ant = IWN_LSB(sc->rxchainmask); 6153 /* Set differential gains for other antennas. */ 6154 for (i = ant + 1; i < 3; i++) { 6155 if (sc->chainmask & (1 << i)) { 6156 /* The delta is relative to antenna "ant". */ 6157 delta = ((int32_t)calib->noise[ant] - 6158 (int32_t)calib->noise[i]) / div; 6159 /* Limit to [-4.5dB,+4.5dB]. */ 6160 cmd.gain[i - 1] = MIN(abs(delta), 3); 6161 if (delta < 0) 6162 cmd.gain[i - 1] |= 1 << 2; /* sign bit */ 6163 } 6164 } 6165 DPRINTF(sc, IWN_DEBUG_CALIBRATE | IWN_DEBUG_XMIT, 6166 "setting differential gains Ant B/C: %x/%x (%x)\n", 6167 cmd.gain[0], cmd.gain[1], sc->chainmask); 6168 return iwn_cmd(sc, IWN_CMD_PHY_CALIB, &cmd, sizeof cmd, 1); 6169 } 6170 6171 /* 6172 * Tune RF RX sensitivity based on the number of false alarms detected 6173 * during the last beacon period. 6174 */ 6175 static void 6176 iwn_tune_sensitivity(struct iwn_softc *sc, const struct iwn_rx_stats *stats) 6177 { 6178 #define inc(val, inc, max) \ 6179 if ((val) < (max)) { \ 6180 if ((val) < (max) - (inc)) \ 6181 (val) += (inc); \ 6182 else \ 6183 (val) = (max); \ 6184 needs_update = 1; \ 6185 } 6186 #define dec(val, dec, min) \ 6187 if ((val) > (min)) { \ 6188 if ((val) > (min) + (dec)) \ 6189 (val) -= (dec); \ 6190 else \ 6191 (val) = (min); \ 6192 needs_update = 1; \ 6193 } 6194 6195 const struct iwn_sensitivity_limits *limits = sc->limits; 6196 struct iwn_calib_state *calib = &sc->calib; 6197 uint32_t val, rxena, fa; 6198 uint32_t energy[3], energy_min; 6199 uint8_t noise[3], noise_ref; 6200 int i, needs_update = 0; 6201 6202 DPRINTF(sc, IWN_DEBUG_TRACE, "->%s begin\n", __func__); 6203 6204 /* Check that we've been enabled long enough. */ 6205 if ((rxena = le32toh(stats->general.load)) == 0){ 6206 DPRINTF(sc, IWN_DEBUG_TRACE, "->%s end not so long\n", __func__); 6207 return; 6208 } 6209 6210 /* Compute number of false alarms since last call for OFDM. */ 6211 fa = le32toh(stats->ofdm.bad_plcp) - calib->bad_plcp_ofdm; 6212 fa += le32toh(stats->ofdm.fa) - calib->fa_ofdm; 6213 fa *= 200 * IEEE80211_DUR_TU; /* 200TU */ 6214 6215 if (fa > 50 * rxena) { 6216 /* High false alarm count, decrease sensitivity. */ 6217 DPRINTF(sc, IWN_DEBUG_CALIBRATE, 6218 "%s: OFDM high false alarm count: %u\n", __func__, fa); 6219 inc(calib->ofdm_x1, 1, limits->max_ofdm_x1); 6220 inc(calib->ofdm_mrc_x1, 1, limits->max_ofdm_mrc_x1); 6221 inc(calib->ofdm_x4, 1, limits->max_ofdm_x4); 6222 inc(calib->ofdm_mrc_x4, 1, limits->max_ofdm_mrc_x4); 6223 6224 } else if (fa < 5 * rxena) { 6225 /* Low false alarm count, increase sensitivity. */ 6226 DPRINTF(sc, IWN_DEBUG_CALIBRATE, 6227 "%s: OFDM low false alarm count: %u\n", __func__, fa); 6228 dec(calib->ofdm_x1, 1, limits->min_ofdm_x1); 6229 dec(calib->ofdm_mrc_x1, 1, limits->min_ofdm_mrc_x1); 6230 dec(calib->ofdm_x4, 1, limits->min_ofdm_x4); 6231 dec(calib->ofdm_mrc_x4, 1, limits->min_ofdm_mrc_x4); 6232 } 6233 6234 /* Compute maximum noise among 3 receivers. */ 6235 for (i = 0; i < 3; i++) 6236 noise[i] = (le32toh(stats->general.noise[i]) >> 8) & 0xff; 6237 val = MAX(noise[0], noise[1]); 6238 val = MAX(noise[2], val); 6239 /* Insert it into our samples table. */ 6240 calib->noise_samples[calib->cur_noise_sample] = val; 6241 calib->cur_noise_sample = (calib->cur_noise_sample + 1) % 20; 6242 6243 /* Compute maximum noise among last 20 samples. */ 6244 noise_ref = calib->noise_samples[0]; 6245 for (i = 1; i < 20; i++) 6246 noise_ref = MAX(noise_ref, calib->noise_samples[i]); 6247 6248 /* Compute maximum energy among 3 receivers. */ 6249 for (i = 0; i < 3; i++) 6250 energy[i] = le32toh(stats->general.energy[i]); 6251 val = MIN(energy[0], energy[1]); 6252 val = MIN(energy[2], val); 6253 /* Insert it into our samples table. */ 6254 calib->energy_samples[calib->cur_energy_sample] = val; 6255 calib->cur_energy_sample = (calib->cur_energy_sample + 1) % 10; 6256 6257 /* Compute minimum energy among last 10 samples. */ 6258 energy_min = calib->energy_samples[0]; 6259 for (i = 1; i < 10; i++) 6260 energy_min = MAX(energy_min, calib->energy_samples[i]); 6261 energy_min += 6; 6262 6263 /* Compute number of false alarms since last call for CCK. */ 6264 fa = le32toh(stats->cck.bad_plcp) - calib->bad_plcp_cck; 6265 fa += le32toh(stats->cck.fa) - calib->fa_cck; 6266 fa *= 200 * IEEE80211_DUR_TU; /* 200TU */ 6267 6268 if (fa > 50 * rxena) { 6269 /* High false alarm count, decrease sensitivity. */ 6270 DPRINTF(sc, IWN_DEBUG_CALIBRATE, 6271 "%s: CCK high false alarm count: %u\n", __func__, fa); 6272 calib->cck_state = IWN_CCK_STATE_HIFA; 6273 calib->low_fa = 0; 6274 6275 if (calib->cck_x4 > 160) { 6276 calib->noise_ref = noise_ref; 6277 if (calib->energy_cck > 2) 6278 dec(calib->energy_cck, 2, energy_min); 6279 } 6280 if (calib->cck_x4 < 160) { 6281 calib->cck_x4 = 161; 6282 needs_update = 1; 6283 } else 6284 inc(calib->cck_x4, 3, limits->max_cck_x4); 6285 6286 inc(calib->cck_mrc_x4, 3, limits->max_cck_mrc_x4); 6287 6288 } else if (fa < 5 * rxena) { 6289 /* Low false alarm count, increase sensitivity. */ 6290 DPRINTF(sc, IWN_DEBUG_CALIBRATE, 6291 "%s: CCK low false alarm count: %u\n", __func__, fa); 6292 calib->cck_state = IWN_CCK_STATE_LOFA; 6293 calib->low_fa++; 6294 6295 if (calib->cck_state != IWN_CCK_STATE_INIT && 6296 (((int32_t)calib->noise_ref - (int32_t)noise_ref) > 2 || 6297 calib->low_fa > 100)) { 6298 inc(calib->energy_cck, 2, limits->min_energy_cck); 6299 dec(calib->cck_x4, 3, limits->min_cck_x4); 6300 dec(calib->cck_mrc_x4, 3, limits->min_cck_mrc_x4); 6301 } 6302 } else { 6303 /* Not worth to increase or decrease sensitivity. */ 6304 DPRINTF(sc, IWN_DEBUG_CALIBRATE, 6305 "%s: CCK normal false alarm count: %u\n", __func__, fa); 6306 calib->low_fa = 0; 6307 calib->noise_ref = noise_ref; 6308 6309 if (calib->cck_state == IWN_CCK_STATE_HIFA) { 6310 /* Previous interval had many false alarms. */ 6311 dec(calib->energy_cck, 8, energy_min); 6312 } 6313 calib->cck_state = IWN_CCK_STATE_INIT; 6314 } 6315 6316 if (needs_update) 6317 (void)iwn_send_sensitivity(sc); 6318 6319 DPRINTF(sc, IWN_DEBUG_TRACE, "->%s: end\n",__func__); 6320 6321 #undef dec 6322 #undef inc 6323 } 6324 6325 static int 6326 iwn_send_sensitivity(struct iwn_softc *sc) 6327 { 6328 struct iwn_calib_state *calib = &sc->calib; 6329 struct iwn_enhanced_sensitivity_cmd cmd; 6330 int len; 6331 6332 memset(&cmd, 0, sizeof cmd); 6333 len = sizeof (struct iwn_sensitivity_cmd); 6334 cmd.which = IWN_SENSITIVITY_WORKTBL; 6335 /* OFDM modulation. */ 6336 cmd.corr_ofdm_x1 = htole16(calib->ofdm_x1); 6337 cmd.corr_ofdm_mrc_x1 = htole16(calib->ofdm_mrc_x1); 6338 cmd.corr_ofdm_x4 = htole16(calib->ofdm_x4); 6339 cmd.corr_ofdm_mrc_x4 = htole16(calib->ofdm_mrc_x4); 6340 cmd.energy_ofdm = htole16(sc->limits->energy_ofdm); 6341 cmd.energy_ofdm_th = htole16(62); 6342 /* CCK modulation. */ 6343 cmd.corr_cck_x4 = htole16(calib->cck_x4); 6344 cmd.corr_cck_mrc_x4 = htole16(calib->cck_mrc_x4); 6345 cmd.energy_cck = htole16(calib->energy_cck); 6346 /* Barker modulation: use default values. */ 6347 cmd.corr_barker = htole16(190); 6348 cmd.corr_barker_mrc = htole16(sc->limits->barker_mrc); 6349 6350 DPRINTF(sc, IWN_DEBUG_CALIBRATE, 6351 "%s: set sensitivity %d/%d/%d/%d/%d/%d/%d\n", __func__, 6352 calib->ofdm_x1, calib->ofdm_mrc_x1, calib->ofdm_x4, 6353 calib->ofdm_mrc_x4, calib->cck_x4, 6354 calib->cck_mrc_x4, calib->energy_cck); 6355 6356 if (!(sc->sc_flags & IWN_FLAG_ENH_SENS)) 6357 goto send; 6358 /* Enhanced sensitivity settings. */ 6359 len = sizeof (struct iwn_enhanced_sensitivity_cmd); 6360 cmd.ofdm_det_slope_mrc = htole16(668); 6361 cmd.ofdm_det_icept_mrc = htole16(4); 6362 cmd.ofdm_det_slope = htole16(486); 6363 cmd.ofdm_det_icept = htole16(37); 6364 cmd.cck_det_slope_mrc = htole16(853); 6365 cmd.cck_det_icept_mrc = htole16(4); 6366 cmd.cck_det_slope = htole16(476); 6367 cmd.cck_det_icept = htole16(99); 6368 send: 6369 return iwn_cmd(sc, IWN_CMD_SET_SENSITIVITY, &cmd, len, 1); 6370 } 6371 6372 /* 6373 * Look at the increase of PLCP errors over time; if it exceeds 6374 * a programmed threshold then trigger an RF retune. 6375 */ 6376 static void 6377 iwn_check_rx_recovery(struct iwn_softc *sc, struct iwn_stats *rs) 6378 { 6379 int32_t delta_ofdm, delta_ht, delta_cck; 6380 struct iwn_calib_state *calib = &sc->calib; 6381 int delta_ticks, cur_ticks; 6382 int delta_msec; 6383 int thresh; 6384 6385 /* 6386 * Calculate the difference between the current and 6387 * previous statistics. 6388 */ 6389 delta_cck = le32toh(rs->rx.cck.bad_plcp) - calib->bad_plcp_cck; 6390 delta_ofdm = le32toh(rs->rx.ofdm.bad_plcp) - calib->bad_plcp_ofdm; 6391 delta_ht = le32toh(rs->rx.ht.bad_plcp) - calib->bad_plcp_ht; 6392 6393 /* 6394 * Calculate the delta in time between successive statistics 6395 * messages. Yes, it can roll over; so we make sure that 6396 * this doesn't happen. 6397 * 6398 * XXX go figure out what to do about rollover 6399 * XXX go figure out what to do if ticks rolls over to -ve instead! 6400 * XXX go stab signed integer overflow undefined-ness in the face. 6401 */ 6402 cur_ticks = ticks; 6403 delta_ticks = cur_ticks - sc->last_calib_ticks; 6404 6405 /* 6406 * If any are negative, then the firmware likely reset; so just 6407 * bail. We'll pick this up next time. 6408 */ 6409 if (delta_cck < 0 || delta_ofdm < 0 || delta_ht < 0 || delta_ticks < 0) 6410 return; 6411 6412 /* 6413 * delta_ticks is in ticks; we need to convert it up to milliseconds 6414 * so we can do some useful math with it. 6415 */ 6416 delta_msec = ticks_to_msecs(delta_ticks); 6417 6418 /* 6419 * Calculate what our threshold is given the current delta_msec. 6420 */ 6421 thresh = sc->base_params->plcp_err_threshold * delta_msec; 6422 6423 DPRINTF(sc, IWN_DEBUG_STATE, 6424 "%s: time delta: %d; cck=%d, ofdm=%d, ht=%d, total=%d, thresh=%d\n", 6425 __func__, 6426 delta_msec, 6427 delta_cck, 6428 delta_ofdm, 6429 delta_ht, 6430 (delta_msec + delta_cck + delta_ofdm + delta_ht), 6431 thresh); 6432 6433 /* 6434 * If we need a retune, then schedule a single channel scan 6435 * to a channel that isn't the currently active one! 6436 * 6437 * The math from linux iwlwifi: 6438 * 6439 * if ((delta * 100 / msecs) > threshold) 6440 */ 6441 if (thresh > 0 && (delta_cck + delta_ofdm + delta_ht) * 100 > thresh) { 6442 DPRINTF(sc, IWN_DEBUG_ANY, 6443 "%s: PLCP error threshold raw (%d) comparison (%d) " 6444 "over limit (%d); retune!\n", 6445 __func__, 6446 (delta_cck + delta_ofdm + delta_ht), 6447 (delta_cck + delta_ofdm + delta_ht) * 100, 6448 thresh); 6449 } 6450 } 6451 6452 /* 6453 * Set STA mode power saving level (between 0 and 5). 6454 * Level 0 is CAM (Continuously Aware Mode), 5 is for maximum power saving. 6455 */ 6456 static int 6457 iwn_set_pslevel(struct iwn_softc *sc, int dtim, int level, int async) 6458 { 6459 struct iwn_pmgt_cmd cmd; 6460 const struct iwn_pmgt *pmgt; 6461 uint32_t max, skip_dtim; 6462 uint32_t reg; 6463 int i; 6464 6465 DPRINTF(sc, IWN_DEBUG_PWRSAVE, 6466 "%s: dtim=%d, level=%d, async=%d\n", 6467 __func__, 6468 dtim, 6469 level, 6470 async); 6471 6472 /* Select which PS parameters to use. */ 6473 if (dtim <= 2) 6474 pmgt = &iwn_pmgt[0][level]; 6475 else if (dtim <= 10) 6476 pmgt = &iwn_pmgt[1][level]; 6477 else 6478 pmgt = &iwn_pmgt[2][level]; 6479 6480 memset(&cmd, 0, sizeof cmd); 6481 if (level != 0) /* not CAM */ 6482 cmd.flags |= htole16(IWN_PS_ALLOW_SLEEP); 6483 if (level == 5) 6484 cmd.flags |= htole16(IWN_PS_FAST_PD); 6485 /* Retrieve PCIe Active State Power Management (ASPM). */ 6486 reg = pci_read_config(sc->sc_dev, sc->sc_cap_off + PCIER_LINK_CTL, 4); 6487 if (!(reg & PCIEM_LINK_CTL_ASPMC_L0S)) /* L0s Entry disabled. */ 6488 cmd.flags |= htole16(IWN_PS_PCI_PMGT); 6489 cmd.rxtimeout = htole32(pmgt->rxtimeout * 1024); 6490 cmd.txtimeout = htole32(pmgt->txtimeout * 1024); 6491 6492 if (dtim == 0) { 6493 dtim = 1; 6494 skip_dtim = 0; 6495 } else 6496 skip_dtim = pmgt->skip_dtim; 6497 if (skip_dtim != 0) { 6498 cmd.flags |= htole16(IWN_PS_SLEEP_OVER_DTIM); 6499 max = pmgt->intval[4]; 6500 if (max == (uint32_t)-1) 6501 max = dtim * (skip_dtim + 1); 6502 else if (max > dtim) 6503 max = rounddown(max, dtim); 6504 } else 6505 max = dtim; 6506 for (i = 0; i < 5; i++) 6507 cmd.intval[i] = htole32(MIN(max, pmgt->intval[i])); 6508 6509 DPRINTF(sc, IWN_DEBUG_RESET, "setting power saving level to %d\n", 6510 level); 6511 return iwn_cmd(sc, IWN_CMD_SET_POWER_MODE, &cmd, sizeof cmd, async); 6512 } 6513 6514 static int 6515 iwn_send_btcoex(struct iwn_softc *sc) 6516 { 6517 struct iwn_bluetooth cmd; 6518 6519 memset(&cmd, 0, sizeof cmd); 6520 cmd.flags = IWN_BT_COEX_CHAN_ANN | IWN_BT_COEX_BT_PRIO; 6521 cmd.lead_time = IWN_BT_LEAD_TIME_DEF; 6522 cmd.max_kill = IWN_BT_MAX_KILL_DEF; 6523 DPRINTF(sc, IWN_DEBUG_RESET, "%s: configuring bluetooth coexistence\n", 6524 __func__); 6525 return iwn_cmd(sc, IWN_CMD_BT_COEX, &cmd, sizeof(cmd), 0); 6526 } 6527 6528 static int 6529 iwn_send_advanced_btcoex(struct iwn_softc *sc) 6530 { 6531 static const uint32_t btcoex_3wire[12] = { 6532 0xaaaaaaaa, 0xaaaaaaaa, 0xaeaaaaaa, 0xaaaaaaaa, 6533 0xcc00ff28, 0x0000aaaa, 0xcc00aaaa, 0x0000aaaa, 6534 0xc0004000, 0x00004000, 0xf0005000, 0xf0005000, 6535 }; 6536 struct iwn6000_btcoex_config btconfig; 6537 struct iwn2000_btcoex_config btconfig2k; 6538 struct iwn_btcoex_priotable btprio; 6539 struct iwn_btcoex_prot btprot; 6540 int error, i; 6541 uint8_t flags; 6542 6543 memset(&btconfig, 0, sizeof btconfig); 6544 memset(&btconfig2k, 0, sizeof btconfig2k); 6545 6546 flags = IWN_BT_FLAG_COEX6000_MODE_3W << 6547 IWN_BT_FLAG_COEX6000_MODE_SHIFT; // Done as is in linux kernel 3.2 6548 6549 if (sc->base_params->bt_sco_disable) 6550 flags &= ~IWN_BT_FLAG_SYNC_2_BT_DISABLE; 6551 else 6552 flags |= IWN_BT_FLAG_SYNC_2_BT_DISABLE; 6553 6554 flags |= IWN_BT_FLAG_COEX6000_CHAN_INHIBITION; 6555 6556 /* Default flags result is 145 as old value */ 6557 6558 /* 6559 * Flags value has to be review. Values must change if we 6560 * which to disable it 6561 */ 6562 if (sc->base_params->bt_session_2) { 6563 btconfig2k.flags = flags; 6564 btconfig2k.max_kill = 5; 6565 btconfig2k.bt3_t7_timer = 1; 6566 btconfig2k.kill_ack = htole32(0xffff0000); 6567 btconfig2k.kill_cts = htole32(0xffff0000); 6568 btconfig2k.sample_time = 2; 6569 btconfig2k.bt3_t2_timer = 0xc; 6570 6571 for (i = 0; i < 12; i++) 6572 btconfig2k.lookup_table[i] = htole32(btcoex_3wire[i]); 6573 btconfig2k.valid = htole16(0xff); 6574 btconfig2k.prio_boost = htole32(0xf0); 6575 DPRINTF(sc, IWN_DEBUG_RESET, 6576 "%s: configuring advanced bluetooth coexistence" 6577 " session 2, flags : 0x%x\n", 6578 __func__, 6579 flags); 6580 error = iwn_cmd(sc, IWN_CMD_BT_COEX, &btconfig2k, 6581 sizeof(btconfig2k), 1); 6582 } else { 6583 btconfig.flags = flags; 6584 btconfig.max_kill = 5; 6585 btconfig.bt3_t7_timer = 1; 6586 btconfig.kill_ack = htole32(0xffff0000); 6587 btconfig.kill_cts = htole32(0xffff0000); 6588 btconfig.sample_time = 2; 6589 btconfig.bt3_t2_timer = 0xc; 6590 6591 for (i = 0; i < 12; i++) 6592 btconfig.lookup_table[i] = htole32(btcoex_3wire[i]); 6593 btconfig.valid = htole16(0xff); 6594 btconfig.prio_boost = 0xf0; 6595 DPRINTF(sc, IWN_DEBUG_RESET, 6596 "%s: configuring advanced bluetooth coexistence," 6597 " flags : 0x%x\n", 6598 __func__, 6599 flags); 6600 error = iwn_cmd(sc, IWN_CMD_BT_COEX, &btconfig, 6601 sizeof(btconfig), 1); 6602 } 6603 6604 if (error != 0) 6605 return error; 6606 6607 memset(&btprio, 0, sizeof btprio); 6608 btprio.calib_init1 = 0x6; 6609 btprio.calib_init2 = 0x7; 6610 btprio.calib_periodic_low1 = 0x2; 6611 btprio.calib_periodic_low2 = 0x3; 6612 btprio.calib_periodic_high1 = 0x4; 6613 btprio.calib_periodic_high2 = 0x5; 6614 btprio.dtim = 0x6; 6615 btprio.scan52 = 0x8; 6616 btprio.scan24 = 0xa; 6617 error = iwn_cmd(sc, IWN_CMD_BT_COEX_PRIOTABLE, &btprio, sizeof(btprio), 6618 1); 6619 if (error != 0) 6620 return error; 6621 6622 /* Force BT state machine change. */ 6623 memset(&btprot, 0, sizeof btprot); 6624 btprot.open = 1; 6625 btprot.type = 1; 6626 error = iwn_cmd(sc, IWN_CMD_BT_COEX_PROT, &btprot, sizeof(btprot), 1); 6627 if (error != 0) 6628 return error; 6629 btprot.open = 0; 6630 return iwn_cmd(sc, IWN_CMD_BT_COEX_PROT, &btprot, sizeof(btprot), 1); 6631 } 6632 6633 static int 6634 iwn5000_runtime_calib(struct iwn_softc *sc) 6635 { 6636 struct iwn5000_calib_config cmd; 6637 6638 memset(&cmd, 0, sizeof cmd); 6639 cmd.ucode.once.enable = 0xffffffff; 6640 cmd.ucode.once.start = IWN5000_CALIB_DC; 6641 DPRINTF(sc, IWN_DEBUG_CALIBRATE, 6642 "%s: configuring runtime calibration\n", __func__); 6643 return iwn_cmd(sc, IWN5000_CMD_CALIB_CONFIG, &cmd, sizeof(cmd), 0); 6644 } 6645 6646 static uint32_t 6647 iwn_get_rxon_ht_flags(struct iwn_softc *sc, struct ieee80211_channel *c) 6648 { 6649 struct ieee80211com *ic = &sc->sc_ic; 6650 uint32_t htflags = 0; 6651 6652 if (! IEEE80211_IS_CHAN_HT(c)) 6653 return (0); 6654 6655 htflags |= IWN_RXON_HT_PROTMODE(ic->ic_curhtprotmode); 6656 6657 if (IEEE80211_IS_CHAN_HT40(c)) { 6658 switch (ic->ic_curhtprotmode) { 6659 case IEEE80211_HTINFO_OPMODE_HT20PR: 6660 htflags |= IWN_RXON_HT_MODEPURE40; 6661 break; 6662 default: 6663 htflags |= IWN_RXON_HT_MODEMIXED; 6664 break; 6665 } 6666 } 6667 if (IEEE80211_IS_CHAN_HT40D(c)) 6668 htflags |= IWN_RXON_HT_HT40MINUS; 6669 6670 return (htflags); 6671 } 6672 6673 static int 6674 iwn_check_bss_filter(struct iwn_softc *sc) 6675 { 6676 return ((sc->rxon->filter & htole32(IWN_FILTER_BSS)) != 0); 6677 } 6678 6679 static int 6680 iwn4965_rxon_assoc(struct iwn_softc *sc, int async) 6681 { 6682 struct iwn4965_rxon_assoc cmd; 6683 struct iwn_rxon *rxon = sc->rxon; 6684 6685 cmd.flags = rxon->flags; 6686 cmd.filter = rxon->filter; 6687 cmd.ofdm_mask = rxon->ofdm_mask; 6688 cmd.cck_mask = rxon->cck_mask; 6689 cmd.ht_single_mask = rxon->ht_single_mask; 6690 cmd.ht_dual_mask = rxon->ht_dual_mask; 6691 cmd.rxchain = rxon->rxchain; 6692 cmd.reserved = 0; 6693 6694 return (iwn_cmd(sc, IWN_CMD_RXON_ASSOC, &cmd, sizeof(cmd), async)); 6695 } 6696 6697 static int 6698 iwn5000_rxon_assoc(struct iwn_softc *sc, int async) 6699 { 6700 struct iwn5000_rxon_assoc cmd; 6701 struct iwn_rxon *rxon = sc->rxon; 6702 6703 cmd.flags = rxon->flags; 6704 cmd.filter = rxon->filter; 6705 cmd.ofdm_mask = rxon->ofdm_mask; 6706 cmd.cck_mask = rxon->cck_mask; 6707 cmd.reserved1 = 0; 6708 cmd.ht_single_mask = rxon->ht_single_mask; 6709 cmd.ht_dual_mask = rxon->ht_dual_mask; 6710 cmd.ht_triple_mask = rxon->ht_triple_mask; 6711 cmd.reserved2 = 0; 6712 cmd.rxchain = rxon->rxchain; 6713 cmd.acquisition = rxon->acquisition; 6714 cmd.reserved3 = 0; 6715 6716 return (iwn_cmd(sc, IWN_CMD_RXON_ASSOC, &cmd, sizeof(cmd), async)); 6717 } 6718 6719 static int 6720 iwn_send_rxon(struct iwn_softc *sc, int assoc, int async) 6721 { 6722 struct iwn_ops *ops = &sc->ops; 6723 int error; 6724 6725 IWN_LOCK_ASSERT(sc); 6726 6727 if (assoc && iwn_check_bss_filter(sc) != 0) { 6728 error = ops->rxon_assoc(sc, async); 6729 if (error != 0) { 6730 device_printf(sc->sc_dev, 6731 "%s: RXON_ASSOC command failed, error %d\n", 6732 __func__, error); 6733 return (error); 6734 } 6735 } else { 6736 if (sc->sc_is_scanning) 6737 device_printf(sc->sc_dev, 6738 "%s: is_scanning set, before RXON\n", 6739 __func__); 6740 6741 error = iwn_cmd(sc, IWN_CMD_RXON, sc->rxon, sc->rxonsz, async); 6742 if (error != 0) { 6743 device_printf(sc->sc_dev, 6744 "%s: RXON command failed, error %d\n", 6745 __func__, error); 6746 return (error); 6747 } 6748 6749 /* 6750 * Reconfiguring RXON clears the firmware nodes table so 6751 * we must add the broadcast node again. 6752 */ 6753 if (iwn_check_bss_filter(sc) == 0 && 6754 (error = iwn_add_broadcast_node(sc, async)) != 0) { 6755 device_printf(sc->sc_dev, 6756 "%s: could not add broadcast node, error %d\n", 6757 __func__, error); 6758 return (error); 6759 } 6760 } 6761 6762 /* Configuration has changed, set TX power accordingly. */ 6763 if ((error = ops->set_txpower(sc, async)) != 0) { 6764 device_printf(sc->sc_dev, 6765 "%s: could not set TX power, error %d\n", 6766 __func__, error); 6767 return (error); 6768 } 6769 6770 return (0); 6771 } 6772 6773 static int 6774 iwn_config(struct iwn_softc *sc) 6775 { 6776 struct ieee80211com *ic = &sc->sc_ic; 6777 struct ieee80211vap *vap = TAILQ_FIRST(&ic->ic_vaps); 6778 const uint8_t *macaddr; 6779 uint32_t txmask; 6780 uint16_t rxchain; 6781 int error; 6782 6783 DPRINTF(sc, IWN_DEBUG_TRACE, "->%s begin\n", __func__); 6784 6785 if ((sc->base_params->calib_need & IWN_FLG_NEED_PHY_CALIB_TEMP_OFFSET) 6786 && (sc->base_params->calib_need & IWN_FLG_NEED_PHY_CALIB_TEMP_OFFSETv2)) { 6787 device_printf(sc->sc_dev,"%s: temp_offset and temp_offsetv2 are" 6788 " exclusive each together. Review NIC config file. Conf" 6789 " : 0x%08x Flags : 0x%08x \n", __func__, 6790 sc->base_params->calib_need, 6791 (IWN_FLG_NEED_PHY_CALIB_TEMP_OFFSET | 6792 IWN_FLG_NEED_PHY_CALIB_TEMP_OFFSETv2)); 6793 return (EINVAL); 6794 } 6795 6796 /* Compute temperature calib if needed. Will be send by send calib */ 6797 if (sc->base_params->calib_need & IWN_FLG_NEED_PHY_CALIB_TEMP_OFFSET) { 6798 error = iwn5000_temp_offset_calib(sc); 6799 if (error != 0) { 6800 device_printf(sc->sc_dev, 6801 "%s: could not set temperature offset\n", __func__); 6802 return (error); 6803 } 6804 } else if (sc->base_params->calib_need & IWN_FLG_NEED_PHY_CALIB_TEMP_OFFSETv2) { 6805 error = iwn5000_temp_offset_calibv2(sc); 6806 if (error != 0) { 6807 device_printf(sc->sc_dev, 6808 "%s: could not compute temperature offset v2\n", 6809 __func__); 6810 return (error); 6811 } 6812 } 6813 6814 if (sc->hw_type == IWN_HW_REV_TYPE_6050) { 6815 /* Configure runtime DC calibration. */ 6816 error = iwn5000_runtime_calib(sc); 6817 if (error != 0) { 6818 device_printf(sc->sc_dev, 6819 "%s: could not configure runtime calibration\n", 6820 __func__); 6821 return error; 6822 } 6823 } 6824 6825 /* Configure valid TX chains for >=5000 Series. */ 6826 if (sc->hw_type != IWN_HW_REV_TYPE_4965 && 6827 IWN_UCODE_API(sc->ucode_rev) > 1) { 6828 txmask = htole32(sc->txchainmask); 6829 DPRINTF(sc, IWN_DEBUG_RESET | IWN_DEBUG_XMIT, 6830 "%s: configuring valid TX chains 0x%x\n", __func__, txmask); 6831 error = iwn_cmd(sc, IWN5000_CMD_TX_ANT_CONFIG, &txmask, 6832 sizeof txmask, 0); 6833 if (error != 0) { 6834 device_printf(sc->sc_dev, 6835 "%s: could not configure valid TX chains, " 6836 "error %d\n", __func__, error); 6837 return error; 6838 } 6839 } 6840 6841 /* Configure bluetooth coexistence. */ 6842 error = 0; 6843 6844 /* Configure bluetooth coexistence if needed. */ 6845 if (sc->base_params->bt_mode == IWN_BT_ADVANCED) 6846 error = iwn_send_advanced_btcoex(sc); 6847 if (sc->base_params->bt_mode == IWN_BT_SIMPLE) 6848 error = iwn_send_btcoex(sc); 6849 6850 if (error != 0) { 6851 device_printf(sc->sc_dev, 6852 "%s: could not configure bluetooth coexistence, error %d\n", 6853 __func__, error); 6854 return error; 6855 } 6856 6857 /* Set mode, channel, RX filter and enable RX. */ 6858 sc->rxon = &sc->rx_on[IWN_RXON_BSS_CTX]; 6859 memset(sc->rxon, 0, sizeof (struct iwn_rxon)); 6860 macaddr = vap ? vap->iv_myaddr : ic->ic_macaddr; 6861 IEEE80211_ADDR_COPY(sc->rxon->myaddr, macaddr); 6862 IEEE80211_ADDR_COPY(sc->rxon->wlap, macaddr); 6863 sc->rxon->chan = ieee80211_chan2ieee(ic, ic->ic_curchan); 6864 sc->rxon->flags = htole32(IWN_RXON_TSF | IWN_RXON_CTS_TO_SELF); 6865 if (IEEE80211_IS_CHAN_2GHZ(ic->ic_curchan)) 6866 sc->rxon->flags |= htole32(IWN_RXON_AUTO | IWN_RXON_24GHZ); 6867 6868 sc->rxon->filter = htole32(IWN_FILTER_MULTICAST); 6869 switch (ic->ic_opmode) { 6870 case IEEE80211_M_STA: 6871 sc->rxon->mode = IWN_MODE_STA; 6872 break; 6873 case IEEE80211_M_MONITOR: 6874 sc->rxon->mode = IWN_MODE_MONITOR; 6875 break; 6876 default: 6877 /* Should not get there. */ 6878 break; 6879 } 6880 iwn_set_promisc(sc); 6881 sc->rxon->cck_mask = 0x0f; /* not yet negotiated */ 6882 sc->rxon->ofdm_mask = 0xff; /* not yet negotiated */ 6883 sc->rxon->ht_single_mask = 0xff; 6884 sc->rxon->ht_dual_mask = 0xff; 6885 sc->rxon->ht_triple_mask = 0xff; 6886 /* 6887 * In active association mode, ensure that 6888 * all the receive chains are enabled. 6889 * 6890 * Since we're not yet doing SMPS, don't allow the 6891 * number of idle RX chains to be less than the active 6892 * number. 6893 */ 6894 rxchain = 6895 IWN_RXCHAIN_VALID(sc->rxchainmask) | 6896 IWN_RXCHAIN_MIMO_COUNT(sc->nrxchains) | 6897 IWN_RXCHAIN_IDLE_COUNT(sc->nrxchains); 6898 sc->rxon->rxchain = htole16(rxchain); 6899 DPRINTF(sc, IWN_DEBUG_RESET | IWN_DEBUG_XMIT, 6900 "%s: rxchainmask=0x%x, nrxchains=%d\n", 6901 __func__, 6902 sc->rxchainmask, 6903 sc->nrxchains); 6904 6905 sc->rxon->flags |= htole32(iwn_get_rxon_ht_flags(sc, ic->ic_curchan)); 6906 6907 DPRINTF(sc, IWN_DEBUG_RESET, 6908 "%s: setting configuration; flags=0x%08x\n", 6909 __func__, le32toh(sc->rxon->flags)); 6910 if ((error = iwn_send_rxon(sc, 0, 0)) != 0) { 6911 device_printf(sc->sc_dev, "%s: could not send RXON\n", 6912 __func__); 6913 return error; 6914 } 6915 6916 if ((error = iwn_set_critical_temp(sc)) != 0) { 6917 device_printf(sc->sc_dev, 6918 "%s: could not set critical temperature\n", __func__); 6919 return error; 6920 } 6921 6922 /* Set power saving level to CAM during initialization. */ 6923 if ((error = iwn_set_pslevel(sc, 0, 0, 0)) != 0) { 6924 device_printf(sc->sc_dev, 6925 "%s: could not set power saving level\n", __func__); 6926 return error; 6927 } 6928 6929 DPRINTF(sc, IWN_DEBUG_TRACE, "->%s: end\n",__func__); 6930 6931 return 0; 6932 } 6933 6934 static uint16_t 6935 iwn_get_active_dwell_time(struct iwn_softc *sc, 6936 struct ieee80211_channel *c, uint8_t n_probes) 6937 { 6938 /* No channel? Default to 2GHz settings */ 6939 if (c == NULL || IEEE80211_IS_CHAN_2GHZ(c)) { 6940 return (IWN_ACTIVE_DWELL_TIME_2GHZ + 6941 IWN_ACTIVE_DWELL_FACTOR_2GHZ * (n_probes + 1)); 6942 } 6943 6944 /* 5GHz dwell time */ 6945 return (IWN_ACTIVE_DWELL_TIME_5GHZ + 6946 IWN_ACTIVE_DWELL_FACTOR_5GHZ * (n_probes + 1)); 6947 } 6948 6949 /* 6950 * Limit the total dwell time to 85% of the beacon interval. 6951 * 6952 * Returns the dwell time in milliseconds. 6953 */ 6954 static uint16_t 6955 iwn_limit_dwell(struct iwn_softc *sc, uint16_t dwell_time) 6956 { 6957 struct ieee80211com *ic = &sc->sc_ic; 6958 struct ieee80211vap *vap = NULL; 6959 int bintval = 0; 6960 6961 /* bintval is in TU (1.024mS) */ 6962 if (! TAILQ_EMPTY(&ic->ic_vaps)) { 6963 vap = TAILQ_FIRST(&ic->ic_vaps); 6964 bintval = vap->iv_bss->ni_intval; 6965 } 6966 6967 /* 6968 * If it's non-zero, we should calculate the minimum of 6969 * it and the DWELL_BASE. 6970 * 6971 * XXX Yes, the math should take into account that bintval 6972 * is 1.024mS, not 1mS.. 6973 */ 6974 if (bintval > 0) { 6975 DPRINTF(sc, IWN_DEBUG_SCAN, 6976 "%s: bintval=%d\n", 6977 __func__, 6978 bintval); 6979 return (MIN(IWN_PASSIVE_DWELL_BASE, ((bintval * 85) / 100))); 6980 } 6981 6982 /* No association context? Default */ 6983 return (IWN_PASSIVE_DWELL_BASE); 6984 } 6985 6986 static uint16_t 6987 iwn_get_passive_dwell_time(struct iwn_softc *sc, struct ieee80211_channel *c) 6988 { 6989 uint16_t passive; 6990 6991 if (c == NULL || IEEE80211_IS_CHAN_2GHZ(c)) { 6992 passive = IWN_PASSIVE_DWELL_BASE + IWN_PASSIVE_DWELL_TIME_2GHZ; 6993 } else { 6994 passive = IWN_PASSIVE_DWELL_BASE + IWN_PASSIVE_DWELL_TIME_5GHZ; 6995 } 6996 6997 /* Clamp to the beacon interval if we're associated */ 6998 return (iwn_limit_dwell(sc, passive)); 6999 } 7000 7001 static int 7002 iwn_scan(struct iwn_softc *sc, struct ieee80211vap *vap, 7003 struct ieee80211_scan_state *ss, struct ieee80211_channel *c) 7004 { 7005 struct ieee80211com *ic = &sc->sc_ic; 7006 struct ieee80211_node *ni = vap->iv_bss; 7007 struct iwn_scan_hdr *hdr; 7008 struct iwn_cmd_data *tx; 7009 struct iwn_scan_essid *essid; 7010 struct iwn_scan_chan *chan; 7011 struct ieee80211_frame *wh; 7012 struct ieee80211_rateset *rs; 7013 uint8_t *buf, *frm; 7014 uint16_t rxchain; 7015 uint8_t txant; 7016 int buflen, error; 7017 int is_active; 7018 uint16_t dwell_active, dwell_passive; 7019 uint32_t extra, scan_service_time; 7020 7021 DPRINTF(sc, IWN_DEBUG_TRACE, "->%s begin\n", __func__); 7022 7023 /* 7024 * We are absolutely not allowed to send a scan command when another 7025 * scan command is pending. 7026 */ 7027 if (sc->sc_is_scanning) { 7028 device_printf(sc->sc_dev, "%s: called whilst scanning!\n", 7029 __func__); 7030 return (EAGAIN); 7031 } 7032 7033 /* Assign the scan channel */ 7034 c = ic->ic_curchan; 7035 7036 sc->rxon = &sc->rx_on[IWN_RXON_BSS_CTX]; 7037 buf = malloc(IWN_SCAN_MAXSZ, M_DEVBUF, M_NOWAIT | M_ZERO); 7038 if (buf == NULL) { 7039 device_printf(sc->sc_dev, 7040 "%s: could not allocate buffer for scan command\n", 7041 __func__); 7042 return ENOMEM; 7043 } 7044 hdr = (struct iwn_scan_hdr *)buf; 7045 /* 7046 * Move to the next channel if no frames are received within 10ms 7047 * after sending the probe request. 7048 */ 7049 hdr->quiet_time = htole16(10); /* timeout in milliseconds */ 7050 hdr->quiet_threshold = htole16(1); /* min # of packets */ 7051 /* 7052 * Max needs to be greater than active and passive and quiet! 7053 * It's also in microseconds! 7054 */ 7055 hdr->max_svc = htole32(250 * 1024); 7056 7057 /* 7058 * Reset scan: interval=100 7059 * Normal scan: interval=becaon interval 7060 * suspend_time: 100 (TU) 7061 * 7062 */ 7063 extra = (100 /* suspend_time */ / 100 /* beacon interval */) << 22; 7064 //scan_service_time = extra | ((100 /* susp */ % 100 /* int */) * 1024); 7065 scan_service_time = (4 << 22) | (100 * 1024); /* Hardcode for now! */ 7066 hdr->pause_svc = htole32(scan_service_time); 7067 7068 /* Select antennas for scanning. */ 7069 rxchain = 7070 IWN_RXCHAIN_VALID(sc->rxchainmask) | 7071 IWN_RXCHAIN_FORCE_MIMO_SEL(sc->rxchainmask) | 7072 IWN_RXCHAIN_DRIVER_FORCE; 7073 if (IEEE80211_IS_CHAN_A(c) && 7074 sc->hw_type == IWN_HW_REV_TYPE_4965) { 7075 /* Ant A must be avoided in 5GHz because of an HW bug. */ 7076 rxchain |= IWN_RXCHAIN_FORCE_SEL(IWN_ANT_B); 7077 } else /* Use all available RX antennas. */ 7078 rxchain |= IWN_RXCHAIN_FORCE_SEL(sc->rxchainmask); 7079 hdr->rxchain = htole16(rxchain); 7080 hdr->filter = htole32(IWN_FILTER_MULTICAST | IWN_FILTER_BEACON); 7081 7082 tx = (struct iwn_cmd_data *)(hdr + 1); 7083 tx->flags = htole32(IWN_TX_AUTO_SEQ); 7084 tx->id = sc->broadcast_id; 7085 tx->lifetime = htole32(IWN_LIFETIME_INFINITE); 7086 7087 if (IEEE80211_IS_CHAN_5GHZ(c)) { 7088 /* Send probe requests at 6Mbps. */ 7089 tx->rate = htole32(0xd); 7090 rs = &ic->ic_sup_rates[IEEE80211_MODE_11A]; 7091 } else { 7092 hdr->flags = htole32(IWN_RXON_24GHZ | IWN_RXON_AUTO); 7093 if (sc->hw_type == IWN_HW_REV_TYPE_4965 && 7094 sc->rxon->associd && sc->rxon->chan > 14) 7095 tx->rate = htole32(0xd); 7096 else { 7097 /* Send probe requests at 1Mbps. */ 7098 tx->rate = htole32(10 | IWN_RFLAG_CCK); 7099 } 7100 rs = &ic->ic_sup_rates[IEEE80211_MODE_11G]; 7101 } 7102 /* Use the first valid TX antenna. */ 7103 txant = IWN_LSB(sc->txchainmask); 7104 tx->rate |= htole32(IWN_RFLAG_ANT(txant)); 7105 7106 /* 7107 * Only do active scanning if we're announcing a probe request 7108 * for a given SSID (or more, if we ever add it to the driver.) 7109 */ 7110 is_active = 0; 7111 7112 /* 7113 * If we're scanning for a specific SSID, add it to the command. 7114 * 7115 * XXX maybe look at adding support for scanning multiple SSIDs? 7116 */ 7117 essid = (struct iwn_scan_essid *)(tx + 1); 7118 if (ss != NULL) { 7119 if (ss->ss_ssid[0].len != 0) { 7120 essid[0].id = IEEE80211_ELEMID_SSID; 7121 essid[0].len = ss->ss_ssid[0].len; 7122 memcpy(essid[0].data, ss->ss_ssid[0].ssid, ss->ss_ssid[0].len); 7123 } 7124 7125 DPRINTF(sc, IWN_DEBUG_SCAN, "%s: ssid_len=%d, ssid=%*s\n", 7126 __func__, 7127 ss->ss_ssid[0].len, 7128 ss->ss_ssid[0].len, 7129 ss->ss_ssid[0].ssid); 7130 7131 if (ss->ss_nssid > 0) 7132 is_active = 1; 7133 } 7134 7135 /* 7136 * Build a probe request frame. Most of the following code is a 7137 * copy & paste of what is done in net80211. 7138 */ 7139 wh = (struct ieee80211_frame *)(essid + 20); 7140 wh->i_fc[0] = IEEE80211_FC0_VERSION_0 | IEEE80211_FC0_TYPE_MGT | 7141 IEEE80211_FC0_SUBTYPE_PROBE_REQ; 7142 wh->i_fc[1] = IEEE80211_FC1_DIR_NODS; 7143 IEEE80211_ADDR_COPY(wh->i_addr1, vap->iv_ifp->if_broadcastaddr); 7144 IEEE80211_ADDR_COPY(wh->i_addr2, IF_LLADDR(vap->iv_ifp)); 7145 IEEE80211_ADDR_COPY(wh->i_addr3, vap->iv_ifp->if_broadcastaddr); 7146 *(uint16_t *)&wh->i_dur[0] = 0; /* filled by HW */ 7147 *(uint16_t *)&wh->i_seq[0] = 0; /* filled by HW */ 7148 7149 frm = (uint8_t *)(wh + 1); 7150 frm = ieee80211_add_ssid(frm, NULL, 0); 7151 frm = ieee80211_add_rates(frm, rs); 7152 if (rs->rs_nrates > IEEE80211_RATE_SIZE) 7153 frm = ieee80211_add_xrates(frm, rs); 7154 if (ic->ic_htcaps & IEEE80211_HTC_HT) 7155 frm = ieee80211_add_htcap(frm, ni); 7156 7157 /* Set length of probe request. */ 7158 tx->len = htole16(frm - (uint8_t *)wh); 7159 7160 /* 7161 * If active scanning is requested but a certain channel is 7162 * marked passive, we can do active scanning if we detect 7163 * transmissions. 7164 * 7165 * There is an issue with some firmware versions that triggers 7166 * a sysassert on a "good CRC threshold" of zero (== disabled), 7167 * on a radar channel even though this means that we should NOT 7168 * send probes. 7169 * 7170 * The "good CRC threshold" is the number of frames that we 7171 * need to receive during our dwell time on a channel before 7172 * sending out probes -- setting this to a huge value will 7173 * mean we never reach it, but at the same time work around 7174 * the aforementioned issue. Thus use IWL_GOOD_CRC_TH_NEVER 7175 * here instead of IWL_GOOD_CRC_TH_DISABLED. 7176 * 7177 * This was fixed in later versions along with some other 7178 * scan changes, and the threshold behaves as a flag in those 7179 * versions. 7180 */ 7181 7182 /* 7183 * If we're doing active scanning, set the crc_threshold 7184 * to a suitable value. This is different to active veruss 7185 * passive scanning depending upon the channel flags; the 7186 * firmware will obey that particular check for us. 7187 */ 7188 if (sc->tlv_feature_flags & IWN_UCODE_TLV_FLAGS_NEWSCAN) 7189 hdr->crc_threshold = is_active ? 7190 IWN_GOOD_CRC_TH_DEFAULT : IWN_GOOD_CRC_TH_DISABLED; 7191 else 7192 hdr->crc_threshold = is_active ? 7193 IWN_GOOD_CRC_TH_DEFAULT : IWN_GOOD_CRC_TH_NEVER; 7194 7195 chan = (struct iwn_scan_chan *)frm; 7196 chan->chan = htole16(ieee80211_chan2ieee(ic, c)); 7197 chan->flags = 0; 7198 if (ss->ss_nssid > 0) 7199 chan->flags |= htole32(IWN_CHAN_NPBREQS(1)); 7200 chan->dsp_gain = 0x6e; 7201 7202 /* 7203 * Set the passive/active flag depending upon the channel mode. 7204 * XXX TODO: take the is_active flag into account as well? 7205 */ 7206 if (c->ic_flags & IEEE80211_CHAN_PASSIVE) 7207 chan->flags |= htole32(IWN_CHAN_PASSIVE); 7208 else 7209 chan->flags |= htole32(IWN_CHAN_ACTIVE); 7210 7211 /* 7212 * Calculate the active/passive dwell times. 7213 */ 7214 7215 dwell_active = iwn_get_active_dwell_time(sc, c, ss->ss_nssid); 7216 dwell_passive = iwn_get_passive_dwell_time(sc, c); 7217 7218 /* Make sure they're valid */ 7219 if (dwell_passive <= dwell_active) 7220 dwell_passive = dwell_active + 1; 7221 7222 chan->active = htole16(dwell_active); 7223 chan->passive = htole16(dwell_passive); 7224 7225 if (IEEE80211_IS_CHAN_5GHZ(c)) 7226 chan->rf_gain = 0x3b; 7227 else 7228 chan->rf_gain = 0x28; 7229 7230 DPRINTF(sc, IWN_DEBUG_STATE, 7231 "%s: chan %u flags 0x%x rf_gain 0x%x " 7232 "dsp_gain 0x%x active %d passive %d scan_svc_time %d crc 0x%x " 7233 "isactive=%d numssid=%d\n", __func__, 7234 chan->chan, chan->flags, chan->rf_gain, chan->dsp_gain, 7235 dwell_active, dwell_passive, scan_service_time, 7236 hdr->crc_threshold, is_active, ss->ss_nssid); 7237 7238 hdr->nchan++; 7239 chan++; 7240 buflen = (uint8_t *)chan - buf; 7241 hdr->len = htole16(buflen); 7242 7243 if (sc->sc_is_scanning) { 7244 device_printf(sc->sc_dev, 7245 "%s: called with is_scanning set!\n", 7246 __func__); 7247 } 7248 sc->sc_is_scanning = 1; 7249 7250 DPRINTF(sc, IWN_DEBUG_STATE, "sending scan command nchan=%d\n", 7251 hdr->nchan); 7252 error = iwn_cmd(sc, IWN_CMD_SCAN, buf, buflen, 1); 7253 free(buf, M_DEVBUF); 7254 if (error == 0) 7255 callout_reset(&sc->scan_timeout, 5*hz, iwn_scan_timeout, sc); 7256 7257 DPRINTF(sc, IWN_DEBUG_TRACE, "->%s: end\n",__func__); 7258 7259 return error; 7260 } 7261 7262 static int 7263 iwn_auth(struct iwn_softc *sc, struct ieee80211vap *vap) 7264 { 7265 struct ieee80211com *ic = &sc->sc_ic; 7266 struct ieee80211_node *ni = vap->iv_bss; 7267 int error; 7268 7269 DPRINTF(sc, IWN_DEBUG_TRACE, "->%s begin\n", __func__); 7270 7271 sc->rxon = &sc->rx_on[IWN_RXON_BSS_CTX]; 7272 /* Update adapter configuration. */ 7273 IEEE80211_ADDR_COPY(sc->rxon->bssid, ni->ni_bssid); 7274 sc->rxon->chan = ieee80211_chan2ieee(ic, ni->ni_chan); 7275 sc->rxon->flags = htole32(IWN_RXON_TSF | IWN_RXON_CTS_TO_SELF); 7276 if (IEEE80211_IS_CHAN_2GHZ(ni->ni_chan)) 7277 sc->rxon->flags |= htole32(IWN_RXON_AUTO | IWN_RXON_24GHZ); 7278 if (ic->ic_flags & IEEE80211_F_SHSLOT) 7279 sc->rxon->flags |= htole32(IWN_RXON_SHSLOT); 7280 if (ic->ic_flags & IEEE80211_F_SHPREAMBLE) 7281 sc->rxon->flags |= htole32(IWN_RXON_SHPREAMBLE); 7282 if (IEEE80211_IS_CHAN_A(ni->ni_chan)) { 7283 sc->rxon->cck_mask = 0; 7284 sc->rxon->ofdm_mask = 0x15; 7285 } else if (IEEE80211_IS_CHAN_B(ni->ni_chan)) { 7286 sc->rxon->cck_mask = 0x03; 7287 sc->rxon->ofdm_mask = 0; 7288 } else { 7289 /* Assume 802.11b/g. */ 7290 sc->rxon->cck_mask = 0x03; 7291 sc->rxon->ofdm_mask = 0x15; 7292 } 7293 7294 /* try HT */ 7295 sc->rxon->flags |= htole32(iwn_get_rxon_ht_flags(sc, ic->ic_curchan)); 7296 7297 DPRINTF(sc, IWN_DEBUG_STATE, "rxon chan %d flags %x cck %x ofdm %x\n", 7298 sc->rxon->chan, sc->rxon->flags, sc->rxon->cck_mask, 7299 sc->rxon->ofdm_mask); 7300 7301 if ((error = iwn_send_rxon(sc, 0, 1)) != 0) { 7302 device_printf(sc->sc_dev, "%s: could not send RXON\n", 7303 __func__); 7304 return (error); 7305 } 7306 7307 DPRINTF(sc, IWN_DEBUG_TRACE, "->%s: end\n",__func__); 7308 7309 return (0); 7310 } 7311 7312 static int 7313 iwn_run(struct iwn_softc *sc, struct ieee80211vap *vap) 7314 { 7315 struct iwn_ops *ops = &sc->ops; 7316 struct ieee80211com *ic = &sc->sc_ic; 7317 struct ieee80211_node *ni = vap->iv_bss; 7318 struct iwn_node_info node; 7319 int error; 7320 7321 DPRINTF(sc, IWN_DEBUG_TRACE, "->%s begin\n", __func__); 7322 7323 sc->rxon = &sc->rx_on[IWN_RXON_BSS_CTX]; 7324 if (ic->ic_opmode == IEEE80211_M_MONITOR) { 7325 /* Link LED blinks while monitoring. */ 7326 iwn_set_led(sc, IWN_LED_LINK, 5, 5); 7327 return 0; 7328 } 7329 if ((error = iwn_set_timing(sc, ni)) != 0) { 7330 device_printf(sc->sc_dev, 7331 "%s: could not set timing, error %d\n", __func__, error); 7332 return error; 7333 } 7334 7335 /* Update adapter configuration. */ 7336 IEEE80211_ADDR_COPY(sc->rxon->bssid, ni->ni_bssid); 7337 sc->rxon->associd = htole16(IEEE80211_AID(ni->ni_associd)); 7338 sc->rxon->chan = ieee80211_chan2ieee(ic, ni->ni_chan); 7339 sc->rxon->flags = htole32(IWN_RXON_TSF | IWN_RXON_CTS_TO_SELF); 7340 if (IEEE80211_IS_CHAN_2GHZ(ni->ni_chan)) 7341 sc->rxon->flags |= htole32(IWN_RXON_AUTO | IWN_RXON_24GHZ); 7342 if (ic->ic_flags & IEEE80211_F_SHSLOT) 7343 sc->rxon->flags |= htole32(IWN_RXON_SHSLOT); 7344 if (ic->ic_flags & IEEE80211_F_SHPREAMBLE) 7345 sc->rxon->flags |= htole32(IWN_RXON_SHPREAMBLE); 7346 if (IEEE80211_IS_CHAN_A(ni->ni_chan)) { 7347 sc->rxon->cck_mask = 0; 7348 sc->rxon->ofdm_mask = 0x15; 7349 } else if (IEEE80211_IS_CHAN_B(ni->ni_chan)) { 7350 sc->rxon->cck_mask = 0x03; 7351 sc->rxon->ofdm_mask = 0; 7352 } else { 7353 /* Assume 802.11b/g. */ 7354 sc->rxon->cck_mask = 0x0f; 7355 sc->rxon->ofdm_mask = 0x15; 7356 } 7357 /* try HT */ 7358 sc->rxon->flags |= htole32(iwn_get_rxon_ht_flags(sc, ni->ni_chan)); 7359 sc->rxon->filter |= htole32(IWN_FILTER_BSS); 7360 DPRINTF(sc, IWN_DEBUG_STATE, "rxon chan %d flags %x, curhtprotmode=%d\n", 7361 sc->rxon->chan, le32toh(sc->rxon->flags), ic->ic_curhtprotmode); 7362 7363 if ((error = iwn_send_rxon(sc, 0, 1)) != 0) { 7364 device_printf(sc->sc_dev, "%s: could not send RXON\n", 7365 __func__); 7366 return error; 7367 } 7368 7369 /* Fake a join to initialize the TX rate. */ 7370 ((struct iwn_node *)ni)->id = IWN_ID_BSS; 7371 iwn_newassoc(ni, 1); 7372 7373 /* Add BSS node. */ 7374 memset(&node, 0, sizeof node); 7375 IEEE80211_ADDR_COPY(node.macaddr, ni->ni_macaddr); 7376 node.id = IWN_ID_BSS; 7377 if (IEEE80211_IS_CHAN_HT(ni->ni_chan)) { 7378 switch (ni->ni_htcap & IEEE80211_HTCAP_SMPS) { 7379 case IEEE80211_HTCAP_SMPS_ENA: 7380 node.htflags |= htole32(IWN_SMPS_MIMO_DIS); 7381 break; 7382 case IEEE80211_HTCAP_SMPS_DYNAMIC: 7383 node.htflags |= htole32(IWN_SMPS_MIMO_PROT); 7384 break; 7385 } 7386 node.htflags |= htole32(IWN_AMDPU_SIZE_FACTOR(3) | 7387 IWN_AMDPU_DENSITY(5)); /* 4us */ 7388 if (IEEE80211_IS_CHAN_HT40(ni->ni_chan)) 7389 node.htflags |= htole32(IWN_NODE_HT40); 7390 } 7391 DPRINTF(sc, IWN_DEBUG_STATE, "%s: adding BSS node\n", __func__); 7392 error = ops->add_node(sc, &node, 1); 7393 if (error != 0) { 7394 device_printf(sc->sc_dev, 7395 "%s: could not add BSS node, error %d\n", __func__, error); 7396 return error; 7397 } 7398 DPRINTF(sc, IWN_DEBUG_STATE, "%s: setting link quality for node %d\n", 7399 __func__, node.id); 7400 if ((error = iwn_set_link_quality(sc, ni)) != 0) { 7401 device_printf(sc->sc_dev, 7402 "%s: could not setup link quality for node %d, error %d\n", 7403 __func__, node.id, error); 7404 return error; 7405 } 7406 7407 if ((error = iwn_init_sensitivity(sc)) != 0) { 7408 device_printf(sc->sc_dev, 7409 "%s: could not set sensitivity, error %d\n", __func__, 7410 error); 7411 return error; 7412 } 7413 /* Start periodic calibration timer. */ 7414 sc->calib.state = IWN_CALIB_STATE_ASSOC; 7415 sc->calib_cnt = 0; 7416 callout_reset(&sc->calib_to, msecs_to_ticks(500), iwn_calib_timeout, 7417 sc); 7418 7419 /* Link LED always on while associated. */ 7420 iwn_set_led(sc, IWN_LED_LINK, 0, 1); 7421 7422 DPRINTF(sc, IWN_DEBUG_TRACE, "->%s: end\n",__func__); 7423 7424 return 0; 7425 } 7426 7427 /* 7428 * This function is called by upper layer when an ADDBA request is received 7429 * from another STA and before the ADDBA response is sent. 7430 */ 7431 static int 7432 iwn_ampdu_rx_start(struct ieee80211_node *ni, struct ieee80211_rx_ampdu *rap, 7433 int baparamset, int batimeout, int baseqctl) 7434 { 7435 #define MS(_v, _f) (((_v) & _f) >> _f##_S) 7436 struct iwn_softc *sc = ni->ni_ic->ic_softc; 7437 struct iwn_ops *ops = &sc->ops; 7438 struct iwn_node *wn = (void *)ni; 7439 struct iwn_node_info node; 7440 uint16_t ssn; 7441 uint8_t tid; 7442 int error; 7443 7444 DPRINTF(sc, IWN_DEBUG_TRACE, "->Doing %s\n", __func__); 7445 7446 tid = MS(le16toh(baparamset), IEEE80211_BAPS_TID); 7447 ssn = MS(le16toh(baseqctl), IEEE80211_BASEQ_START); 7448 7449 if (wn->id == IWN_ID_UNDEFINED) 7450 return (ENOENT); 7451 7452 memset(&node, 0, sizeof node); 7453 node.id = wn->id; 7454 node.control = IWN_NODE_UPDATE; 7455 node.flags = IWN_FLAG_SET_ADDBA; 7456 node.addba_tid = tid; 7457 node.addba_ssn = htole16(ssn); 7458 DPRINTF(sc, IWN_DEBUG_RECV, "ADDBA RA=%d TID=%d SSN=%d\n", 7459 wn->id, tid, ssn); 7460 error = ops->add_node(sc, &node, 1); 7461 if (error != 0) 7462 return error; 7463 return sc->sc_ampdu_rx_start(ni, rap, baparamset, batimeout, baseqctl); 7464 #undef MS 7465 } 7466 7467 /* 7468 * This function is called by upper layer on teardown of an HT-immediate 7469 * Block Ack agreement (eg. uppon receipt of a DELBA frame). 7470 */ 7471 static void 7472 iwn_ampdu_rx_stop(struct ieee80211_node *ni, struct ieee80211_rx_ampdu *rap) 7473 { 7474 struct ieee80211com *ic = ni->ni_ic; 7475 struct iwn_softc *sc = ic->ic_softc; 7476 struct iwn_ops *ops = &sc->ops; 7477 struct iwn_node *wn = (void *)ni; 7478 struct iwn_node_info node; 7479 uint8_t tid; 7480 7481 DPRINTF(sc, IWN_DEBUG_TRACE, "->Doing %s\n", __func__); 7482 7483 if (wn->id == IWN_ID_UNDEFINED) 7484 goto end; 7485 7486 /* XXX: tid as an argument */ 7487 for (tid = 0; tid < WME_NUM_TID; tid++) { 7488 if (&ni->ni_rx_ampdu[tid] == rap) 7489 break; 7490 } 7491 7492 memset(&node, 0, sizeof node); 7493 node.id = wn->id; 7494 node.control = IWN_NODE_UPDATE; 7495 node.flags = IWN_FLAG_SET_DELBA; 7496 node.delba_tid = tid; 7497 DPRINTF(sc, IWN_DEBUG_RECV, "DELBA RA=%d TID=%d\n", wn->id, tid); 7498 (void)ops->add_node(sc, &node, 1); 7499 end: 7500 sc->sc_ampdu_rx_stop(ni, rap); 7501 } 7502 7503 static int 7504 iwn_addba_request(struct ieee80211_node *ni, struct ieee80211_tx_ampdu *tap, 7505 int dialogtoken, int baparamset, int batimeout) 7506 { 7507 struct iwn_softc *sc = ni->ni_ic->ic_softc; 7508 int qid; 7509 7510 DPRINTF(sc, IWN_DEBUG_TRACE, "->Doing %s\n", __func__); 7511 7512 for (qid = sc->firstaggqueue; qid < sc->ntxqs; qid++) { 7513 if (sc->qid2tap[qid] == NULL) 7514 break; 7515 } 7516 if (qid == sc->ntxqs) { 7517 DPRINTF(sc, IWN_DEBUG_XMIT, "%s: not free aggregation queue\n", 7518 __func__); 7519 return 0; 7520 } 7521 tap->txa_private = malloc(sizeof(int), M_DEVBUF, M_NOWAIT); 7522 if (tap->txa_private == NULL) { 7523 device_printf(sc->sc_dev, 7524 "%s: failed to alloc TX aggregation structure\n", __func__); 7525 return 0; 7526 } 7527 sc->qid2tap[qid] = tap; 7528 *(int *)tap->txa_private = qid; 7529 return sc->sc_addba_request(ni, tap, dialogtoken, baparamset, 7530 batimeout); 7531 } 7532 7533 static int 7534 iwn_addba_response(struct ieee80211_node *ni, struct ieee80211_tx_ampdu *tap, 7535 int code, int baparamset, int batimeout) 7536 { 7537 struct iwn_softc *sc = ni->ni_ic->ic_softc; 7538 int qid = *(int *)tap->txa_private; 7539 uint8_t tid = tap->txa_tid; 7540 int ret; 7541 7542 DPRINTF(sc, IWN_DEBUG_TRACE, "->Doing %s\n", __func__); 7543 7544 if (code == IEEE80211_STATUS_SUCCESS) { 7545 ni->ni_txseqs[tid] = tap->txa_start & 0xfff; 7546 ret = iwn_ampdu_tx_start(ni->ni_ic, ni, tid); 7547 if (ret != 1) 7548 return ret; 7549 } else { 7550 sc->qid2tap[qid] = NULL; 7551 free(tap->txa_private, M_DEVBUF); 7552 tap->txa_private = NULL; 7553 } 7554 return sc->sc_addba_response(ni, tap, code, baparamset, batimeout); 7555 } 7556 7557 /* 7558 * This function is called by upper layer when an ADDBA response is received 7559 * from another STA. 7560 */ 7561 static int 7562 iwn_ampdu_tx_start(struct ieee80211com *ic, struct ieee80211_node *ni, 7563 uint8_t tid) 7564 { 7565 struct ieee80211_tx_ampdu *tap = &ni->ni_tx_ampdu[tid]; 7566 struct iwn_softc *sc = ni->ni_ic->ic_softc; 7567 struct iwn_ops *ops = &sc->ops; 7568 struct iwn_node *wn = (void *)ni; 7569 struct iwn_node_info node; 7570 int error, qid; 7571 7572 DPRINTF(sc, IWN_DEBUG_TRACE, "->Doing %s\n", __func__); 7573 7574 if (wn->id == IWN_ID_UNDEFINED) 7575 return (0); 7576 7577 /* Enable TX for the specified RA/TID. */ 7578 wn->disable_tid &= ~(1 << tid); 7579 memset(&node, 0, sizeof node); 7580 node.id = wn->id; 7581 node.control = IWN_NODE_UPDATE; 7582 node.flags = IWN_FLAG_SET_DISABLE_TID; 7583 node.disable_tid = htole16(wn->disable_tid); 7584 error = ops->add_node(sc, &node, 1); 7585 if (error != 0) 7586 return 0; 7587 7588 if ((error = iwn_nic_lock(sc)) != 0) 7589 return 0; 7590 qid = *(int *)tap->txa_private; 7591 DPRINTF(sc, IWN_DEBUG_XMIT, "%s: ra=%d tid=%d ssn=%d qid=%d\n", 7592 __func__, wn->id, tid, tap->txa_start, qid); 7593 ops->ampdu_tx_start(sc, ni, qid, tid, tap->txa_start & 0xfff); 7594 iwn_nic_unlock(sc); 7595 7596 iwn_set_link_quality(sc, ni); 7597 return 1; 7598 } 7599 7600 static void 7601 iwn_ampdu_tx_stop(struct ieee80211_node *ni, struct ieee80211_tx_ampdu *tap) 7602 { 7603 struct iwn_softc *sc = ni->ni_ic->ic_softc; 7604 struct iwn_ops *ops = &sc->ops; 7605 uint8_t tid = tap->txa_tid; 7606 int qid; 7607 7608 DPRINTF(sc, IWN_DEBUG_TRACE, "->Doing %s\n", __func__); 7609 7610 sc->sc_addba_stop(ni, tap); 7611 7612 if (tap->txa_private == NULL) 7613 return; 7614 7615 qid = *(int *)tap->txa_private; 7616 if (sc->txq[qid].queued != 0) 7617 return; 7618 if (iwn_nic_lock(sc) != 0) 7619 return; 7620 ops->ampdu_tx_stop(sc, qid, tid, tap->txa_start & 0xfff); 7621 iwn_nic_unlock(sc); 7622 sc->qid2tap[qid] = NULL; 7623 free(tap->txa_private, M_DEVBUF); 7624 tap->txa_private = NULL; 7625 } 7626 7627 static void 7628 iwn4965_ampdu_tx_start(struct iwn_softc *sc, struct ieee80211_node *ni, 7629 int qid, uint8_t tid, uint16_t ssn) 7630 { 7631 struct iwn_node *wn = (void *)ni; 7632 7633 DPRINTF(sc, IWN_DEBUG_TRACE, "->Doing %s\n", __func__); 7634 7635 /* Stop TX scheduler while we're changing its configuration. */ 7636 iwn_prph_write(sc, IWN4965_SCHED_QUEUE_STATUS(qid), 7637 IWN4965_TXQ_STATUS_CHGACT); 7638 7639 /* Assign RA/TID translation to the queue. */ 7640 iwn_mem_write_2(sc, sc->sched_base + IWN4965_SCHED_TRANS_TBL(qid), 7641 wn->id << 4 | tid); 7642 7643 /* Enable chain-building mode for the queue. */ 7644 iwn_prph_setbits(sc, IWN4965_SCHED_QCHAIN_SEL, 1 << qid); 7645 7646 /* Set starting sequence number from the ADDBA request. */ 7647 sc->txq[qid].cur = sc->txq[qid].read = (ssn & 0xff); 7648 IWN_WRITE(sc, IWN_HBUS_TARG_WRPTR, qid << 8 | (ssn & 0xff)); 7649 iwn_prph_write(sc, IWN4965_SCHED_QUEUE_RDPTR(qid), ssn); 7650 7651 /* Set scheduler window size. */ 7652 iwn_mem_write(sc, sc->sched_base + IWN4965_SCHED_QUEUE_OFFSET(qid), 7653 IWN_SCHED_WINSZ); 7654 /* Set scheduler frame limit. */ 7655 iwn_mem_write(sc, sc->sched_base + IWN4965_SCHED_QUEUE_OFFSET(qid) + 4, 7656 IWN_SCHED_LIMIT << 16); 7657 7658 /* Enable interrupts for the queue. */ 7659 iwn_prph_setbits(sc, IWN4965_SCHED_INTR_MASK, 1 << qid); 7660 7661 /* Mark the queue as active. */ 7662 iwn_prph_write(sc, IWN4965_SCHED_QUEUE_STATUS(qid), 7663 IWN4965_TXQ_STATUS_ACTIVE | IWN4965_TXQ_STATUS_AGGR_ENA | 7664 iwn_tid2fifo[tid] << 1); 7665 } 7666 7667 static void 7668 iwn4965_ampdu_tx_stop(struct iwn_softc *sc, int qid, uint8_t tid, uint16_t ssn) 7669 { 7670 DPRINTF(sc, IWN_DEBUG_TRACE, "->Doing %s\n", __func__); 7671 7672 /* Stop TX scheduler while we're changing its configuration. */ 7673 iwn_prph_write(sc, IWN4965_SCHED_QUEUE_STATUS(qid), 7674 IWN4965_TXQ_STATUS_CHGACT); 7675 7676 /* Set starting sequence number from the ADDBA request. */ 7677 IWN_WRITE(sc, IWN_HBUS_TARG_WRPTR, qid << 8 | (ssn & 0xff)); 7678 iwn_prph_write(sc, IWN4965_SCHED_QUEUE_RDPTR(qid), ssn); 7679 7680 /* Disable interrupts for the queue. */ 7681 iwn_prph_clrbits(sc, IWN4965_SCHED_INTR_MASK, 1 << qid); 7682 7683 /* Mark the queue as inactive. */ 7684 iwn_prph_write(sc, IWN4965_SCHED_QUEUE_STATUS(qid), 7685 IWN4965_TXQ_STATUS_INACTIVE | iwn_tid2fifo[tid] << 1); 7686 } 7687 7688 static void 7689 iwn5000_ampdu_tx_start(struct iwn_softc *sc, struct ieee80211_node *ni, 7690 int qid, uint8_t tid, uint16_t ssn) 7691 { 7692 DPRINTF(sc, IWN_DEBUG_TRACE, "->Doing %s\n", __func__); 7693 7694 struct iwn_node *wn = (void *)ni; 7695 7696 /* Stop TX scheduler while we're changing its configuration. */ 7697 iwn_prph_write(sc, IWN5000_SCHED_QUEUE_STATUS(qid), 7698 IWN5000_TXQ_STATUS_CHGACT); 7699 7700 /* Assign RA/TID translation to the queue. */ 7701 iwn_mem_write_2(sc, sc->sched_base + IWN5000_SCHED_TRANS_TBL(qid), 7702 wn->id << 4 | tid); 7703 7704 /* Enable chain-building mode for the queue. */ 7705 iwn_prph_setbits(sc, IWN5000_SCHED_QCHAIN_SEL, 1 << qid); 7706 7707 /* Enable aggregation for the queue. */ 7708 iwn_prph_setbits(sc, IWN5000_SCHED_AGGR_SEL, 1 << qid); 7709 7710 /* Set starting sequence number from the ADDBA request. */ 7711 sc->txq[qid].cur = sc->txq[qid].read = (ssn & 0xff); 7712 IWN_WRITE(sc, IWN_HBUS_TARG_WRPTR, qid << 8 | (ssn & 0xff)); 7713 iwn_prph_write(sc, IWN5000_SCHED_QUEUE_RDPTR(qid), ssn); 7714 7715 /* Set scheduler window size and frame limit. */ 7716 iwn_mem_write(sc, sc->sched_base + IWN5000_SCHED_QUEUE_OFFSET(qid) + 4, 7717 IWN_SCHED_LIMIT << 16 | IWN_SCHED_WINSZ); 7718 7719 /* Enable interrupts for the queue. */ 7720 iwn_prph_setbits(sc, IWN5000_SCHED_INTR_MASK, 1 << qid); 7721 7722 /* Mark the queue as active. */ 7723 iwn_prph_write(sc, IWN5000_SCHED_QUEUE_STATUS(qid), 7724 IWN5000_TXQ_STATUS_ACTIVE | iwn_tid2fifo[tid]); 7725 } 7726 7727 static void 7728 iwn5000_ampdu_tx_stop(struct iwn_softc *sc, int qid, uint8_t tid, uint16_t ssn) 7729 { 7730 DPRINTF(sc, IWN_DEBUG_TRACE, "->Doing %s\n", __func__); 7731 7732 /* Stop TX scheduler while we're changing its configuration. */ 7733 iwn_prph_write(sc, IWN5000_SCHED_QUEUE_STATUS(qid), 7734 IWN5000_TXQ_STATUS_CHGACT); 7735 7736 /* Disable aggregation for the queue. */ 7737 iwn_prph_clrbits(sc, IWN5000_SCHED_AGGR_SEL, 1 << qid); 7738 7739 /* Set starting sequence number from the ADDBA request. */ 7740 IWN_WRITE(sc, IWN_HBUS_TARG_WRPTR, qid << 8 | (ssn & 0xff)); 7741 iwn_prph_write(sc, IWN5000_SCHED_QUEUE_RDPTR(qid), ssn); 7742 7743 /* Disable interrupts for the queue. */ 7744 iwn_prph_clrbits(sc, IWN5000_SCHED_INTR_MASK, 1 << qid); 7745 7746 /* Mark the queue as inactive. */ 7747 iwn_prph_write(sc, IWN5000_SCHED_QUEUE_STATUS(qid), 7748 IWN5000_TXQ_STATUS_INACTIVE | iwn_tid2fifo[tid]); 7749 } 7750 7751 /* 7752 * Query calibration tables from the initialization firmware. We do this 7753 * only once at first boot. Called from a process context. 7754 */ 7755 static int 7756 iwn5000_query_calibration(struct iwn_softc *sc) 7757 { 7758 struct iwn5000_calib_config cmd; 7759 int error; 7760 7761 memset(&cmd, 0, sizeof cmd); 7762 cmd.ucode.once.enable = htole32(0xffffffff); 7763 cmd.ucode.once.start = htole32(0xffffffff); 7764 cmd.ucode.once.send = htole32(0xffffffff); 7765 cmd.ucode.flags = htole32(0xffffffff); 7766 DPRINTF(sc, IWN_DEBUG_CALIBRATE, "%s: sending calibration query\n", 7767 __func__); 7768 error = iwn_cmd(sc, IWN5000_CMD_CALIB_CONFIG, &cmd, sizeof cmd, 0); 7769 if (error != 0) 7770 return error; 7771 7772 /* Wait at most two seconds for calibration to complete. */ 7773 if (!(sc->sc_flags & IWN_FLAG_CALIB_DONE)) 7774 error = msleep(sc, &sc->sc_mtx, PCATCH, "iwncal", 2 * hz); 7775 return error; 7776 } 7777 7778 /* 7779 * Send calibration results to the runtime firmware. These results were 7780 * obtained on first boot from the initialization firmware. 7781 */ 7782 static int 7783 iwn5000_send_calibration(struct iwn_softc *sc) 7784 { 7785 int idx, error; 7786 7787 for (idx = 0; idx < IWN5000_PHY_CALIB_MAX_RESULT; idx++) { 7788 if (!(sc->base_params->calib_need & (1<<idx))) { 7789 DPRINTF(sc, IWN_DEBUG_CALIBRATE, 7790 "No need of calib %d\n", 7791 idx); 7792 continue; /* no need for this calib */ 7793 } 7794 if (sc->calibcmd[idx].buf == NULL) { 7795 DPRINTF(sc, IWN_DEBUG_CALIBRATE, 7796 "Need calib idx : %d but no available data\n", 7797 idx); 7798 continue; 7799 } 7800 7801 DPRINTF(sc, IWN_DEBUG_CALIBRATE, 7802 "send calibration result idx=%d len=%d\n", idx, 7803 sc->calibcmd[idx].len); 7804 error = iwn_cmd(sc, IWN_CMD_PHY_CALIB, sc->calibcmd[idx].buf, 7805 sc->calibcmd[idx].len, 0); 7806 if (error != 0) { 7807 device_printf(sc->sc_dev, 7808 "%s: could not send calibration result, error %d\n", 7809 __func__, error); 7810 return error; 7811 } 7812 } 7813 return 0; 7814 } 7815 7816 static int 7817 iwn5000_send_wimax_coex(struct iwn_softc *sc) 7818 { 7819 struct iwn5000_wimax_coex wimax; 7820 7821 #if 0 7822 if (sc->hw_type == IWN_HW_REV_TYPE_6050) { 7823 /* Enable WiMAX coexistence for combo adapters. */ 7824 wimax.flags = 7825 IWN_WIMAX_COEX_ASSOC_WA_UNMASK | 7826 IWN_WIMAX_COEX_UNASSOC_WA_UNMASK | 7827 IWN_WIMAX_COEX_STA_TABLE_VALID | 7828 IWN_WIMAX_COEX_ENABLE; 7829 memcpy(wimax.events, iwn6050_wimax_events, 7830 sizeof iwn6050_wimax_events); 7831 } else 7832 #endif 7833 { 7834 /* Disable WiMAX coexistence. */ 7835 wimax.flags = 0; 7836 memset(wimax.events, 0, sizeof wimax.events); 7837 } 7838 DPRINTF(sc, IWN_DEBUG_RESET, "%s: Configuring WiMAX coexistence\n", 7839 __func__); 7840 return iwn_cmd(sc, IWN5000_CMD_WIMAX_COEX, &wimax, sizeof wimax, 0); 7841 } 7842 7843 static int 7844 iwn5000_crystal_calib(struct iwn_softc *sc) 7845 { 7846 struct iwn5000_phy_calib_crystal cmd; 7847 7848 memset(&cmd, 0, sizeof cmd); 7849 cmd.code = IWN5000_PHY_CALIB_CRYSTAL; 7850 cmd.ngroups = 1; 7851 cmd.isvalid = 1; 7852 cmd.cap_pin[0] = le32toh(sc->eeprom_crystal) & 0xff; 7853 cmd.cap_pin[1] = (le32toh(sc->eeprom_crystal) >> 16) & 0xff; 7854 DPRINTF(sc, IWN_DEBUG_CALIBRATE, "sending crystal calibration %d, %d\n", 7855 cmd.cap_pin[0], cmd.cap_pin[1]); 7856 return iwn_cmd(sc, IWN_CMD_PHY_CALIB, &cmd, sizeof cmd, 0); 7857 } 7858 7859 static int 7860 iwn5000_temp_offset_calib(struct iwn_softc *sc) 7861 { 7862 struct iwn5000_phy_calib_temp_offset cmd; 7863 7864 memset(&cmd, 0, sizeof cmd); 7865 cmd.code = IWN5000_PHY_CALIB_TEMP_OFFSET; 7866 cmd.ngroups = 1; 7867 cmd.isvalid = 1; 7868 if (sc->eeprom_temp != 0) 7869 cmd.offset = htole16(sc->eeprom_temp); 7870 else 7871 cmd.offset = htole16(IWN_DEFAULT_TEMP_OFFSET); 7872 DPRINTF(sc, IWN_DEBUG_CALIBRATE, "setting radio sensor offset to %d\n", 7873 le16toh(cmd.offset)); 7874 return iwn_cmd(sc, IWN_CMD_PHY_CALIB, &cmd, sizeof cmd, 0); 7875 } 7876 7877 static int 7878 iwn5000_temp_offset_calibv2(struct iwn_softc *sc) 7879 { 7880 struct iwn5000_phy_calib_temp_offsetv2 cmd; 7881 7882 memset(&cmd, 0, sizeof cmd); 7883 cmd.code = IWN5000_PHY_CALIB_TEMP_OFFSET; 7884 cmd.ngroups = 1; 7885 cmd.isvalid = 1; 7886 if (sc->eeprom_temp != 0) { 7887 cmd.offset_low = htole16(sc->eeprom_temp); 7888 cmd.offset_high = htole16(sc->eeprom_temp_high); 7889 } else { 7890 cmd.offset_low = htole16(IWN_DEFAULT_TEMP_OFFSET); 7891 cmd.offset_high = htole16(IWN_DEFAULT_TEMP_OFFSET); 7892 } 7893 cmd.burnt_voltage_ref = htole16(sc->eeprom_voltage); 7894 7895 DPRINTF(sc, IWN_DEBUG_CALIBRATE, 7896 "setting radio sensor low offset to %d, high offset to %d, voltage to %d\n", 7897 le16toh(cmd.offset_low), 7898 le16toh(cmd.offset_high), 7899 le16toh(cmd.burnt_voltage_ref)); 7900 7901 return iwn_cmd(sc, IWN_CMD_PHY_CALIB, &cmd, sizeof cmd, 0); 7902 } 7903 7904 /* 7905 * This function is called after the runtime firmware notifies us of its 7906 * readiness (called in a process context). 7907 */ 7908 static int 7909 iwn4965_post_alive(struct iwn_softc *sc) 7910 { 7911 int error, qid; 7912 7913 if ((error = iwn_nic_lock(sc)) != 0) 7914 return error; 7915 7916 DPRINTF(sc, IWN_DEBUG_TRACE, "->Doing %s\n", __func__); 7917 7918 /* Clear TX scheduler state in SRAM. */ 7919 sc->sched_base = iwn_prph_read(sc, IWN_SCHED_SRAM_ADDR); 7920 iwn_mem_set_region_4(sc, sc->sched_base + IWN4965_SCHED_CTX_OFF, 0, 7921 IWN4965_SCHED_CTX_LEN / sizeof (uint32_t)); 7922 7923 /* Set physical address of TX scheduler rings (1KB aligned). */ 7924 iwn_prph_write(sc, IWN4965_SCHED_DRAM_ADDR, sc->sched_dma.paddr >> 10); 7925 7926 IWN_SETBITS(sc, IWN_FH_TX_CHICKEN, IWN_FH_TX_CHICKEN_SCHED_RETRY); 7927 7928 /* Disable chain mode for all our 16 queues. */ 7929 iwn_prph_write(sc, IWN4965_SCHED_QCHAIN_SEL, 0); 7930 7931 for (qid = 0; qid < IWN4965_NTXQUEUES; qid++) { 7932 iwn_prph_write(sc, IWN4965_SCHED_QUEUE_RDPTR(qid), 0); 7933 IWN_WRITE(sc, IWN_HBUS_TARG_WRPTR, qid << 8 | 0); 7934 7935 /* Set scheduler window size. */ 7936 iwn_mem_write(sc, sc->sched_base + 7937 IWN4965_SCHED_QUEUE_OFFSET(qid), IWN_SCHED_WINSZ); 7938 /* Set scheduler frame limit. */ 7939 iwn_mem_write(sc, sc->sched_base + 7940 IWN4965_SCHED_QUEUE_OFFSET(qid) + 4, 7941 IWN_SCHED_LIMIT << 16); 7942 } 7943 7944 /* Enable interrupts for all our 16 queues. */ 7945 iwn_prph_write(sc, IWN4965_SCHED_INTR_MASK, 0xffff); 7946 /* Identify TX FIFO rings (0-7). */ 7947 iwn_prph_write(sc, IWN4965_SCHED_TXFACT, 0xff); 7948 7949 /* Mark TX rings (4 EDCA + cmd + 2 HCCA) as active. */ 7950 for (qid = 0; qid < 7; qid++) { 7951 static uint8_t qid2fifo[] = { 3, 2, 1, 0, 4, 5, 6 }; 7952 iwn_prph_write(sc, IWN4965_SCHED_QUEUE_STATUS(qid), 7953 IWN4965_TXQ_STATUS_ACTIVE | qid2fifo[qid] << 1); 7954 } 7955 iwn_nic_unlock(sc); 7956 return 0; 7957 } 7958 7959 /* 7960 * This function is called after the initialization or runtime firmware 7961 * notifies us of its readiness (called in a process context). 7962 */ 7963 static int 7964 iwn5000_post_alive(struct iwn_softc *sc) 7965 { 7966 int error, qid; 7967 7968 DPRINTF(sc, IWN_DEBUG_TRACE, "->%s begin\n", __func__); 7969 7970 /* Switch to using ICT interrupt mode. */ 7971 iwn5000_ict_reset(sc); 7972 7973 if ((error = iwn_nic_lock(sc)) != 0){ 7974 DPRINTF(sc, IWN_DEBUG_TRACE, "->%s end in error\n", __func__); 7975 return error; 7976 } 7977 7978 /* Clear TX scheduler state in SRAM. */ 7979 sc->sched_base = iwn_prph_read(sc, IWN_SCHED_SRAM_ADDR); 7980 iwn_mem_set_region_4(sc, sc->sched_base + IWN5000_SCHED_CTX_OFF, 0, 7981 IWN5000_SCHED_CTX_LEN / sizeof (uint32_t)); 7982 7983 /* Set physical address of TX scheduler rings (1KB aligned). */ 7984 iwn_prph_write(sc, IWN5000_SCHED_DRAM_ADDR, sc->sched_dma.paddr >> 10); 7985 7986 IWN_SETBITS(sc, IWN_FH_TX_CHICKEN, IWN_FH_TX_CHICKEN_SCHED_RETRY); 7987 7988 /* Enable chain mode for all queues, except command queue. */ 7989 if (sc->sc_flags & IWN_FLAG_PAN_SUPPORT) 7990 iwn_prph_write(sc, IWN5000_SCHED_QCHAIN_SEL, 0xfffdf); 7991 else 7992 iwn_prph_write(sc, IWN5000_SCHED_QCHAIN_SEL, 0xfffef); 7993 iwn_prph_write(sc, IWN5000_SCHED_AGGR_SEL, 0); 7994 7995 for (qid = 0; qid < IWN5000_NTXQUEUES; qid++) { 7996 iwn_prph_write(sc, IWN5000_SCHED_QUEUE_RDPTR(qid), 0); 7997 IWN_WRITE(sc, IWN_HBUS_TARG_WRPTR, qid << 8 | 0); 7998 7999 iwn_mem_write(sc, sc->sched_base + 8000 IWN5000_SCHED_QUEUE_OFFSET(qid), 0); 8001 /* Set scheduler window size and frame limit. */ 8002 iwn_mem_write(sc, sc->sched_base + 8003 IWN5000_SCHED_QUEUE_OFFSET(qid) + 4, 8004 IWN_SCHED_LIMIT << 16 | IWN_SCHED_WINSZ); 8005 } 8006 8007 /* Enable interrupts for all our 20 queues. */ 8008 iwn_prph_write(sc, IWN5000_SCHED_INTR_MASK, 0xfffff); 8009 /* Identify TX FIFO rings (0-7). */ 8010 iwn_prph_write(sc, IWN5000_SCHED_TXFACT, 0xff); 8011 8012 /* Mark TX rings (4 EDCA + cmd + 2 HCCA) as active. */ 8013 if (sc->sc_flags & IWN_FLAG_PAN_SUPPORT) { 8014 /* Mark TX rings as active. */ 8015 for (qid = 0; qid < 11; qid++) { 8016 static uint8_t qid2fifo[] = { 3, 2, 1, 0, 0, 4, 2, 5, 4, 7, 5 }; 8017 iwn_prph_write(sc, IWN5000_SCHED_QUEUE_STATUS(qid), 8018 IWN5000_TXQ_STATUS_ACTIVE | qid2fifo[qid]); 8019 } 8020 } else { 8021 /* Mark TX rings (4 EDCA + cmd + 2 HCCA) as active. */ 8022 for (qid = 0; qid < 7; qid++) { 8023 static uint8_t qid2fifo[] = { 3, 2, 1, 0, 7, 5, 6 }; 8024 iwn_prph_write(sc, IWN5000_SCHED_QUEUE_STATUS(qid), 8025 IWN5000_TXQ_STATUS_ACTIVE | qid2fifo[qid]); 8026 } 8027 } 8028 iwn_nic_unlock(sc); 8029 8030 /* Configure WiMAX coexistence for combo adapters. */ 8031 error = iwn5000_send_wimax_coex(sc); 8032 if (error != 0) { 8033 device_printf(sc->sc_dev, 8034 "%s: could not configure WiMAX coexistence, error %d\n", 8035 __func__, error); 8036 return error; 8037 } 8038 if (sc->hw_type != IWN_HW_REV_TYPE_5150) { 8039 /* Perform crystal calibration. */ 8040 error = iwn5000_crystal_calib(sc); 8041 if (error != 0) { 8042 device_printf(sc->sc_dev, 8043 "%s: crystal calibration failed, error %d\n", 8044 __func__, error); 8045 return error; 8046 } 8047 } 8048 if (!(sc->sc_flags & IWN_FLAG_CALIB_DONE)) { 8049 /* Query calibration from the initialization firmware. */ 8050 if ((error = iwn5000_query_calibration(sc)) != 0) { 8051 device_printf(sc->sc_dev, 8052 "%s: could not query calibration, error %d\n", 8053 __func__, error); 8054 return error; 8055 } 8056 /* 8057 * We have the calibration results now, reboot with the 8058 * runtime firmware (call ourselves recursively!) 8059 */ 8060 iwn_hw_stop(sc); 8061 error = iwn_hw_init(sc); 8062 } else { 8063 /* Send calibration results to runtime firmware. */ 8064 error = iwn5000_send_calibration(sc); 8065 } 8066 8067 DPRINTF(sc, IWN_DEBUG_TRACE, "->%s: end\n",__func__); 8068 8069 return error; 8070 } 8071 8072 /* 8073 * The firmware boot code is small and is intended to be copied directly into 8074 * the NIC internal memory (no DMA transfer). 8075 */ 8076 static int 8077 iwn4965_load_bootcode(struct iwn_softc *sc, const uint8_t *ucode, int size) 8078 { 8079 int error, ntries; 8080 8081 size /= sizeof (uint32_t); 8082 8083 if ((error = iwn_nic_lock(sc)) != 0) 8084 return error; 8085 8086 /* Copy microcode image into NIC memory. */ 8087 iwn_prph_write_region_4(sc, IWN_BSM_SRAM_BASE, 8088 (const uint32_t *)ucode, size); 8089 8090 iwn_prph_write(sc, IWN_BSM_WR_MEM_SRC, 0); 8091 iwn_prph_write(sc, IWN_BSM_WR_MEM_DST, IWN_FW_TEXT_BASE); 8092 iwn_prph_write(sc, IWN_BSM_WR_DWCOUNT, size); 8093 8094 /* Start boot load now. */ 8095 iwn_prph_write(sc, IWN_BSM_WR_CTRL, IWN_BSM_WR_CTRL_START); 8096 8097 /* Wait for transfer to complete. */ 8098 for (ntries = 0; ntries < 1000; ntries++) { 8099 if (!(iwn_prph_read(sc, IWN_BSM_WR_CTRL) & 8100 IWN_BSM_WR_CTRL_START)) 8101 break; 8102 DELAY(10); 8103 } 8104 if (ntries == 1000) { 8105 device_printf(sc->sc_dev, "%s: could not load boot firmware\n", 8106 __func__); 8107 iwn_nic_unlock(sc); 8108 return ETIMEDOUT; 8109 } 8110 8111 /* Enable boot after power up. */ 8112 iwn_prph_write(sc, IWN_BSM_WR_CTRL, IWN_BSM_WR_CTRL_START_EN); 8113 8114 iwn_nic_unlock(sc); 8115 return 0; 8116 } 8117 8118 static int 8119 iwn4965_load_firmware(struct iwn_softc *sc) 8120 { 8121 struct iwn_fw_info *fw = &sc->fw; 8122 struct iwn_dma_info *dma = &sc->fw_dma; 8123 int error; 8124 8125 /* Copy initialization sections into pre-allocated DMA-safe memory. */ 8126 memcpy(dma->vaddr, fw->init.data, fw->init.datasz); 8127 bus_dmamap_sync(dma->tag, dma->map, BUS_DMASYNC_PREWRITE); 8128 memcpy(dma->vaddr + IWN4965_FW_DATA_MAXSZ, 8129 fw->init.text, fw->init.textsz); 8130 bus_dmamap_sync(dma->tag, dma->map, BUS_DMASYNC_PREWRITE); 8131 8132 /* Tell adapter where to find initialization sections. */ 8133 if ((error = iwn_nic_lock(sc)) != 0) 8134 return error; 8135 iwn_prph_write(sc, IWN_BSM_DRAM_DATA_ADDR, dma->paddr >> 4); 8136 iwn_prph_write(sc, IWN_BSM_DRAM_DATA_SIZE, fw->init.datasz); 8137 iwn_prph_write(sc, IWN_BSM_DRAM_TEXT_ADDR, 8138 (dma->paddr + IWN4965_FW_DATA_MAXSZ) >> 4); 8139 iwn_prph_write(sc, IWN_BSM_DRAM_TEXT_SIZE, fw->init.textsz); 8140 iwn_nic_unlock(sc); 8141 8142 /* Load firmware boot code. */ 8143 error = iwn4965_load_bootcode(sc, fw->boot.text, fw->boot.textsz); 8144 if (error != 0) { 8145 device_printf(sc->sc_dev, "%s: could not load boot firmware\n", 8146 __func__); 8147 return error; 8148 } 8149 /* Now press "execute". */ 8150 IWN_WRITE(sc, IWN_RESET, 0); 8151 8152 /* Wait at most one second for first alive notification. */ 8153 if ((error = msleep(sc, &sc->sc_mtx, PCATCH, "iwninit", hz)) != 0) { 8154 device_printf(sc->sc_dev, 8155 "%s: timeout waiting for adapter to initialize, error %d\n", 8156 __func__, error); 8157 return error; 8158 } 8159 8160 /* Retrieve current temperature for initial TX power calibration. */ 8161 sc->rawtemp = sc->ucode_info.temp[3].chan20MHz; 8162 sc->temp = iwn4965_get_temperature(sc); 8163 8164 /* Copy runtime sections into pre-allocated DMA-safe memory. */ 8165 memcpy(dma->vaddr, fw->main.data, fw->main.datasz); 8166 bus_dmamap_sync(dma->tag, dma->map, BUS_DMASYNC_PREWRITE); 8167 memcpy(dma->vaddr + IWN4965_FW_DATA_MAXSZ, 8168 fw->main.text, fw->main.textsz); 8169 bus_dmamap_sync(dma->tag, dma->map, BUS_DMASYNC_PREWRITE); 8170 8171 /* Tell adapter where to find runtime sections. */ 8172 if ((error = iwn_nic_lock(sc)) != 0) 8173 return error; 8174 iwn_prph_write(sc, IWN_BSM_DRAM_DATA_ADDR, dma->paddr >> 4); 8175 iwn_prph_write(sc, IWN_BSM_DRAM_DATA_SIZE, fw->main.datasz); 8176 iwn_prph_write(sc, IWN_BSM_DRAM_TEXT_ADDR, 8177 (dma->paddr + IWN4965_FW_DATA_MAXSZ) >> 4); 8178 iwn_prph_write(sc, IWN_BSM_DRAM_TEXT_SIZE, 8179 IWN_FW_UPDATED | fw->main.textsz); 8180 iwn_nic_unlock(sc); 8181 8182 return 0; 8183 } 8184 8185 static int 8186 iwn5000_load_firmware_section(struct iwn_softc *sc, uint32_t dst, 8187 const uint8_t *section, int size) 8188 { 8189 struct iwn_dma_info *dma = &sc->fw_dma; 8190 int error; 8191 8192 DPRINTF(sc, IWN_DEBUG_TRACE, "->Doing %s\n", __func__); 8193 8194 /* Copy firmware section into pre-allocated DMA-safe memory. */ 8195 memcpy(dma->vaddr, section, size); 8196 bus_dmamap_sync(dma->tag, dma->map, BUS_DMASYNC_PREWRITE); 8197 8198 if ((error = iwn_nic_lock(sc)) != 0) 8199 return error; 8200 8201 IWN_WRITE(sc, IWN_FH_TX_CONFIG(IWN_SRVC_DMACHNL), 8202 IWN_FH_TX_CONFIG_DMA_PAUSE); 8203 8204 IWN_WRITE(sc, IWN_FH_SRAM_ADDR(IWN_SRVC_DMACHNL), dst); 8205 IWN_WRITE(sc, IWN_FH_TFBD_CTRL0(IWN_SRVC_DMACHNL), 8206 IWN_LOADDR(dma->paddr)); 8207 IWN_WRITE(sc, IWN_FH_TFBD_CTRL1(IWN_SRVC_DMACHNL), 8208 IWN_HIADDR(dma->paddr) << 28 | size); 8209 IWN_WRITE(sc, IWN_FH_TXBUF_STATUS(IWN_SRVC_DMACHNL), 8210 IWN_FH_TXBUF_STATUS_TBNUM(1) | 8211 IWN_FH_TXBUF_STATUS_TBIDX(1) | 8212 IWN_FH_TXBUF_STATUS_TFBD_VALID); 8213 8214 /* Kick Flow Handler to start DMA transfer. */ 8215 IWN_WRITE(sc, IWN_FH_TX_CONFIG(IWN_SRVC_DMACHNL), 8216 IWN_FH_TX_CONFIG_DMA_ENA | IWN_FH_TX_CONFIG_CIRQ_HOST_ENDTFD); 8217 8218 iwn_nic_unlock(sc); 8219 8220 /* Wait at most five seconds for FH DMA transfer to complete. */ 8221 return msleep(sc, &sc->sc_mtx, PCATCH, "iwninit", 5 * hz); 8222 } 8223 8224 static int 8225 iwn5000_load_firmware(struct iwn_softc *sc) 8226 { 8227 struct iwn_fw_part *fw; 8228 int error; 8229 8230 DPRINTF(sc, IWN_DEBUG_TRACE, "->Doing %s\n", __func__); 8231 8232 /* Load the initialization firmware on first boot only. */ 8233 fw = (sc->sc_flags & IWN_FLAG_CALIB_DONE) ? 8234 &sc->fw.main : &sc->fw.init; 8235 8236 error = iwn5000_load_firmware_section(sc, IWN_FW_TEXT_BASE, 8237 fw->text, fw->textsz); 8238 if (error != 0) { 8239 device_printf(sc->sc_dev, 8240 "%s: could not load firmware %s section, error %d\n", 8241 __func__, ".text", error); 8242 return error; 8243 } 8244 error = iwn5000_load_firmware_section(sc, IWN_FW_DATA_BASE, 8245 fw->data, fw->datasz); 8246 if (error != 0) { 8247 device_printf(sc->sc_dev, 8248 "%s: could not load firmware %s section, error %d\n", 8249 __func__, ".data", error); 8250 return error; 8251 } 8252 8253 /* Now press "execute". */ 8254 IWN_WRITE(sc, IWN_RESET, 0); 8255 return 0; 8256 } 8257 8258 /* 8259 * Extract text and data sections from a legacy firmware image. 8260 */ 8261 static int 8262 iwn_read_firmware_leg(struct iwn_softc *sc, struct iwn_fw_info *fw) 8263 { 8264 const uint32_t *ptr; 8265 size_t hdrlen = 24; 8266 uint32_t rev; 8267 8268 ptr = (const uint32_t *)fw->data; 8269 rev = le32toh(*ptr++); 8270 8271 sc->ucode_rev = rev; 8272 8273 /* Check firmware API version. */ 8274 if (IWN_FW_API(rev) <= 1) { 8275 device_printf(sc->sc_dev, 8276 "%s: bad firmware, need API version >=2\n", __func__); 8277 return EINVAL; 8278 } 8279 if (IWN_FW_API(rev) >= 3) { 8280 /* Skip build number (version 2 header). */ 8281 hdrlen += 4; 8282 ptr++; 8283 } 8284 if (fw->size < hdrlen) { 8285 device_printf(sc->sc_dev, "%s: firmware too short: %zu bytes\n", 8286 __func__, fw->size); 8287 return EINVAL; 8288 } 8289 fw->main.textsz = le32toh(*ptr++); 8290 fw->main.datasz = le32toh(*ptr++); 8291 fw->init.textsz = le32toh(*ptr++); 8292 fw->init.datasz = le32toh(*ptr++); 8293 fw->boot.textsz = le32toh(*ptr++); 8294 8295 /* Check that all firmware sections fit. */ 8296 if (fw->size < hdrlen + fw->main.textsz + fw->main.datasz + 8297 fw->init.textsz + fw->init.datasz + fw->boot.textsz) { 8298 device_printf(sc->sc_dev, "%s: firmware too short: %zu bytes\n", 8299 __func__, fw->size); 8300 return EINVAL; 8301 } 8302 8303 /* Get pointers to firmware sections. */ 8304 fw->main.text = (const uint8_t *)ptr; 8305 fw->main.data = fw->main.text + fw->main.textsz; 8306 fw->init.text = fw->main.data + fw->main.datasz; 8307 fw->init.data = fw->init.text + fw->init.textsz; 8308 fw->boot.text = fw->init.data + fw->init.datasz; 8309 return 0; 8310 } 8311 8312 /* 8313 * Extract text and data sections from a TLV firmware image. 8314 */ 8315 static int 8316 iwn_read_firmware_tlv(struct iwn_softc *sc, struct iwn_fw_info *fw, 8317 uint16_t alt) 8318 { 8319 const struct iwn_fw_tlv_hdr *hdr; 8320 const struct iwn_fw_tlv *tlv; 8321 const uint8_t *ptr, *end; 8322 uint64_t altmask; 8323 uint32_t len, tmp; 8324 8325 if (fw->size < sizeof (*hdr)) { 8326 device_printf(sc->sc_dev, "%s: firmware too short: %zu bytes\n", 8327 __func__, fw->size); 8328 return EINVAL; 8329 } 8330 hdr = (const struct iwn_fw_tlv_hdr *)fw->data; 8331 if (hdr->signature != htole32(IWN_FW_SIGNATURE)) { 8332 device_printf(sc->sc_dev, "%s: bad firmware signature 0x%08x\n", 8333 __func__, le32toh(hdr->signature)); 8334 return EINVAL; 8335 } 8336 DPRINTF(sc, IWN_DEBUG_RESET, "FW: \"%.64s\", build 0x%x\n", hdr->descr, 8337 le32toh(hdr->build)); 8338 sc->ucode_rev = le32toh(hdr->rev); 8339 8340 /* 8341 * Select the closest supported alternative that is less than 8342 * or equal to the specified one. 8343 */ 8344 altmask = le64toh(hdr->altmask); 8345 while (alt > 0 && !(altmask & (1ULL << alt))) 8346 alt--; /* Downgrade. */ 8347 DPRINTF(sc, IWN_DEBUG_RESET, "using alternative %d\n", alt); 8348 8349 ptr = (const uint8_t *)(hdr + 1); 8350 end = (const uint8_t *)(fw->data + fw->size); 8351 8352 /* Parse type-length-value fields. */ 8353 while (ptr + sizeof (*tlv) <= end) { 8354 tlv = (const struct iwn_fw_tlv *)ptr; 8355 len = le32toh(tlv->len); 8356 8357 ptr += sizeof (*tlv); 8358 if (ptr + len > end) { 8359 device_printf(sc->sc_dev, 8360 "%s: firmware too short: %zu bytes\n", __func__, 8361 fw->size); 8362 return EINVAL; 8363 } 8364 /* Skip other alternatives. */ 8365 if (tlv->alt != 0 && tlv->alt != htole16(alt)) 8366 goto next; 8367 8368 switch (le16toh(tlv->type)) { 8369 case IWN_FW_TLV_MAIN_TEXT: 8370 fw->main.text = ptr; 8371 fw->main.textsz = len; 8372 break; 8373 case IWN_FW_TLV_MAIN_DATA: 8374 fw->main.data = ptr; 8375 fw->main.datasz = len; 8376 break; 8377 case IWN_FW_TLV_INIT_TEXT: 8378 fw->init.text = ptr; 8379 fw->init.textsz = len; 8380 break; 8381 case IWN_FW_TLV_INIT_DATA: 8382 fw->init.data = ptr; 8383 fw->init.datasz = len; 8384 break; 8385 case IWN_FW_TLV_BOOT_TEXT: 8386 fw->boot.text = ptr; 8387 fw->boot.textsz = len; 8388 break; 8389 case IWN_FW_TLV_ENH_SENS: 8390 if (!len) 8391 sc->sc_flags |= IWN_FLAG_ENH_SENS; 8392 break; 8393 case IWN_FW_TLV_PHY_CALIB: 8394 tmp = le32toh(*ptr); 8395 if (tmp < 253) { 8396 sc->reset_noise_gain = tmp; 8397 sc->noise_gain = tmp + 1; 8398 } 8399 break; 8400 case IWN_FW_TLV_PAN: 8401 sc->sc_flags |= IWN_FLAG_PAN_SUPPORT; 8402 DPRINTF(sc, IWN_DEBUG_RESET, 8403 "PAN Support found: %d\n", 1); 8404 break; 8405 case IWN_FW_TLV_FLAGS: 8406 if (len < sizeof(uint32_t)) 8407 break; 8408 if (len % sizeof(uint32_t)) 8409 break; 8410 sc->tlv_feature_flags = le32toh(*ptr); 8411 DPRINTF(sc, IWN_DEBUG_RESET, 8412 "%s: feature: 0x%08x\n", 8413 __func__, 8414 sc->tlv_feature_flags); 8415 break; 8416 case IWN_FW_TLV_PBREQ_MAXLEN: 8417 case IWN_FW_TLV_RUNT_EVTLOG_PTR: 8418 case IWN_FW_TLV_RUNT_EVTLOG_SIZE: 8419 case IWN_FW_TLV_RUNT_ERRLOG_PTR: 8420 case IWN_FW_TLV_INIT_EVTLOG_PTR: 8421 case IWN_FW_TLV_INIT_EVTLOG_SIZE: 8422 case IWN_FW_TLV_INIT_ERRLOG_PTR: 8423 case IWN_FW_TLV_WOWLAN_INST: 8424 case IWN_FW_TLV_WOWLAN_DATA: 8425 DPRINTF(sc, IWN_DEBUG_RESET, 8426 "TLV type %d recognized but not handled\n", 8427 le16toh(tlv->type)); 8428 break; 8429 default: 8430 DPRINTF(sc, IWN_DEBUG_RESET, 8431 "TLV type %d not handled\n", le16toh(tlv->type)); 8432 break; 8433 } 8434 next: /* TLV fields are 32-bit aligned. */ 8435 ptr += (len + 3) & ~3; 8436 } 8437 return 0; 8438 } 8439 8440 static int 8441 iwn_read_firmware(struct iwn_softc *sc) 8442 { 8443 struct iwn_fw_info *fw = &sc->fw; 8444 int error; 8445 8446 DPRINTF(sc, IWN_DEBUG_TRACE, "->Doing %s\n", __func__); 8447 8448 IWN_UNLOCK(sc); 8449 8450 memset(fw, 0, sizeof (*fw)); 8451 8452 /* Read firmware image from filesystem. */ 8453 sc->fw_fp = firmware_get(sc->fwname); 8454 if (sc->fw_fp == NULL) { 8455 device_printf(sc->sc_dev, "%s: could not read firmware %s\n", 8456 __func__, sc->fwname); 8457 IWN_LOCK(sc); 8458 return EINVAL; 8459 } 8460 IWN_LOCK(sc); 8461 8462 fw->size = sc->fw_fp->datasize; 8463 fw->data = (const uint8_t *)sc->fw_fp->data; 8464 if (fw->size < sizeof (uint32_t)) { 8465 device_printf(sc->sc_dev, "%s: firmware too short: %zu bytes\n", 8466 __func__, fw->size); 8467 error = EINVAL; 8468 goto fail; 8469 } 8470 8471 /* Retrieve text and data sections. */ 8472 if (*(const uint32_t *)fw->data != 0) /* Legacy image. */ 8473 error = iwn_read_firmware_leg(sc, fw); 8474 else 8475 error = iwn_read_firmware_tlv(sc, fw, 1); 8476 if (error != 0) { 8477 device_printf(sc->sc_dev, 8478 "%s: could not read firmware sections, error %d\n", 8479 __func__, error); 8480 goto fail; 8481 } 8482 8483 device_printf(sc->sc_dev, "%s: ucode rev=0x%08x\n", __func__, sc->ucode_rev); 8484 8485 /* Make sure text and data sections fit in hardware memory. */ 8486 if (fw->main.textsz > sc->fw_text_maxsz || 8487 fw->main.datasz > sc->fw_data_maxsz || 8488 fw->init.textsz > sc->fw_text_maxsz || 8489 fw->init.datasz > sc->fw_data_maxsz || 8490 fw->boot.textsz > IWN_FW_BOOT_TEXT_MAXSZ || 8491 (fw->boot.textsz & 3) != 0) { 8492 device_printf(sc->sc_dev, "%s: firmware sections too large\n", 8493 __func__); 8494 error = EINVAL; 8495 goto fail; 8496 } 8497 8498 /* We can proceed with loading the firmware. */ 8499 return 0; 8500 8501 fail: iwn_unload_firmware(sc); 8502 return error; 8503 } 8504 8505 static void 8506 iwn_unload_firmware(struct iwn_softc *sc) 8507 { 8508 firmware_put(sc->fw_fp, FIRMWARE_UNLOAD); 8509 sc->fw_fp = NULL; 8510 } 8511 8512 static int 8513 iwn_clock_wait(struct iwn_softc *sc) 8514 { 8515 int ntries; 8516 8517 /* Set "initialization complete" bit. */ 8518 IWN_SETBITS(sc, IWN_GP_CNTRL, IWN_GP_CNTRL_INIT_DONE); 8519 8520 /* Wait for clock stabilization. */ 8521 for (ntries = 0; ntries < 2500; ntries++) { 8522 if (IWN_READ(sc, IWN_GP_CNTRL) & IWN_GP_CNTRL_MAC_CLOCK_READY) 8523 return 0; 8524 DELAY(10); 8525 } 8526 device_printf(sc->sc_dev, 8527 "%s: timeout waiting for clock stabilization\n", __func__); 8528 return ETIMEDOUT; 8529 } 8530 8531 static int 8532 iwn_apm_init(struct iwn_softc *sc) 8533 { 8534 uint32_t reg; 8535 int error; 8536 8537 DPRINTF(sc, IWN_DEBUG_TRACE, "->Doing %s\n", __func__); 8538 8539 /* Disable L0s exit timer (NMI bug workaround). */ 8540 IWN_SETBITS(sc, IWN_GIO_CHICKEN, IWN_GIO_CHICKEN_DIS_L0S_TIMER); 8541 /* Don't wait for ICH L0s (ICH bug workaround). */ 8542 IWN_SETBITS(sc, IWN_GIO_CHICKEN, IWN_GIO_CHICKEN_L1A_NO_L0S_RX); 8543 8544 /* Set FH wait threshold to max (HW bug under stress workaround). */ 8545 IWN_SETBITS(sc, IWN_DBG_HPET_MEM, 0xffff0000); 8546 8547 /* Enable HAP INTA to move adapter from L1a to L0s. */ 8548 IWN_SETBITS(sc, IWN_HW_IF_CONFIG, IWN_HW_IF_CONFIG_HAP_WAKE_L1A); 8549 8550 /* Retrieve PCIe Active State Power Management (ASPM). */ 8551 reg = pci_read_config(sc->sc_dev, sc->sc_cap_off + PCIER_LINK_CTL, 4); 8552 /* Workaround for HW instability in PCIe L0->L0s->L1 transition. */ 8553 if (reg & PCIEM_LINK_CTL_ASPMC_L1) /* L1 Entry enabled. */ 8554 IWN_SETBITS(sc, IWN_GIO, IWN_GIO_L0S_ENA); 8555 else 8556 IWN_CLRBITS(sc, IWN_GIO, IWN_GIO_L0S_ENA); 8557 8558 if (sc->base_params->pll_cfg_val) 8559 IWN_SETBITS(sc, IWN_ANA_PLL, sc->base_params->pll_cfg_val); 8560 8561 /* Wait for clock stabilization before accessing prph. */ 8562 if ((error = iwn_clock_wait(sc)) != 0) 8563 return error; 8564 8565 if ((error = iwn_nic_lock(sc)) != 0) 8566 return error; 8567 if (sc->hw_type == IWN_HW_REV_TYPE_4965) { 8568 /* Enable DMA and BSM (Bootstrap State Machine). */ 8569 iwn_prph_write(sc, IWN_APMG_CLK_EN, 8570 IWN_APMG_CLK_CTRL_DMA_CLK_RQT | 8571 IWN_APMG_CLK_CTRL_BSM_CLK_RQT); 8572 } else { 8573 /* Enable DMA. */ 8574 iwn_prph_write(sc, IWN_APMG_CLK_EN, 8575 IWN_APMG_CLK_CTRL_DMA_CLK_RQT); 8576 } 8577 DELAY(20); 8578 /* Disable L1-Active. */ 8579 iwn_prph_setbits(sc, IWN_APMG_PCI_STT, IWN_APMG_PCI_STT_L1A_DIS); 8580 iwn_nic_unlock(sc); 8581 8582 return 0; 8583 } 8584 8585 static void 8586 iwn_apm_stop_master(struct iwn_softc *sc) 8587 { 8588 int ntries; 8589 8590 /* Stop busmaster DMA activity. */ 8591 IWN_SETBITS(sc, IWN_RESET, IWN_RESET_STOP_MASTER); 8592 for (ntries = 0; ntries < 100; ntries++) { 8593 if (IWN_READ(sc, IWN_RESET) & IWN_RESET_MASTER_DISABLED) 8594 return; 8595 DELAY(10); 8596 } 8597 device_printf(sc->sc_dev, "%s: timeout waiting for master\n", __func__); 8598 } 8599 8600 static void 8601 iwn_apm_stop(struct iwn_softc *sc) 8602 { 8603 iwn_apm_stop_master(sc); 8604 8605 /* Reset the entire device. */ 8606 IWN_SETBITS(sc, IWN_RESET, IWN_RESET_SW); 8607 DELAY(10); 8608 /* Clear "initialization complete" bit. */ 8609 IWN_CLRBITS(sc, IWN_GP_CNTRL, IWN_GP_CNTRL_INIT_DONE); 8610 } 8611 8612 static int 8613 iwn4965_nic_config(struct iwn_softc *sc) 8614 { 8615 DPRINTF(sc, IWN_DEBUG_TRACE, "->Doing %s\n", __func__); 8616 8617 if (IWN_RFCFG_TYPE(sc->rfcfg) == 1) { 8618 /* 8619 * I don't believe this to be correct but this is what the 8620 * vendor driver is doing. Probably the bits should not be 8621 * shifted in IWN_RFCFG_*. 8622 */ 8623 IWN_SETBITS(sc, IWN_HW_IF_CONFIG, 8624 IWN_RFCFG_TYPE(sc->rfcfg) | 8625 IWN_RFCFG_STEP(sc->rfcfg) | 8626 IWN_RFCFG_DASH(sc->rfcfg)); 8627 } 8628 IWN_SETBITS(sc, IWN_HW_IF_CONFIG, 8629 IWN_HW_IF_CONFIG_RADIO_SI | IWN_HW_IF_CONFIG_MAC_SI); 8630 return 0; 8631 } 8632 8633 static int 8634 iwn5000_nic_config(struct iwn_softc *sc) 8635 { 8636 uint32_t tmp; 8637 int error; 8638 8639 DPRINTF(sc, IWN_DEBUG_TRACE, "->Doing %s\n", __func__); 8640 8641 if (IWN_RFCFG_TYPE(sc->rfcfg) < 3) { 8642 IWN_SETBITS(sc, IWN_HW_IF_CONFIG, 8643 IWN_RFCFG_TYPE(sc->rfcfg) | 8644 IWN_RFCFG_STEP(sc->rfcfg) | 8645 IWN_RFCFG_DASH(sc->rfcfg)); 8646 } 8647 IWN_SETBITS(sc, IWN_HW_IF_CONFIG, 8648 IWN_HW_IF_CONFIG_RADIO_SI | IWN_HW_IF_CONFIG_MAC_SI); 8649 8650 if ((error = iwn_nic_lock(sc)) != 0) 8651 return error; 8652 iwn_prph_setbits(sc, IWN_APMG_PS, IWN_APMG_PS_EARLY_PWROFF_DIS); 8653 8654 if (sc->hw_type == IWN_HW_REV_TYPE_1000) { 8655 /* 8656 * Select first Switching Voltage Regulator (1.32V) to 8657 * solve a stability issue related to noisy DC2DC line 8658 * in the silicon of 1000 Series. 8659 */ 8660 tmp = iwn_prph_read(sc, IWN_APMG_DIGITAL_SVR); 8661 tmp &= ~IWN_APMG_DIGITAL_SVR_VOLTAGE_MASK; 8662 tmp |= IWN_APMG_DIGITAL_SVR_VOLTAGE_1_32; 8663 iwn_prph_write(sc, IWN_APMG_DIGITAL_SVR, tmp); 8664 } 8665 iwn_nic_unlock(sc); 8666 8667 if (sc->sc_flags & IWN_FLAG_INTERNAL_PA) { 8668 /* Use internal power amplifier only. */ 8669 IWN_WRITE(sc, IWN_GP_DRIVER, IWN_GP_DRIVER_RADIO_2X2_IPA); 8670 } 8671 if (sc->base_params->additional_nic_config && sc->calib_ver >= 6) { 8672 /* Indicate that ROM calibration version is >=6. */ 8673 IWN_SETBITS(sc, IWN_GP_DRIVER, IWN_GP_DRIVER_CALIB_VER6); 8674 } 8675 if (sc->base_params->additional_gp_drv_bit) 8676 IWN_SETBITS(sc, IWN_GP_DRIVER, 8677 sc->base_params->additional_gp_drv_bit); 8678 return 0; 8679 } 8680 8681 /* 8682 * Take NIC ownership over Intel Active Management Technology (AMT). 8683 */ 8684 static int 8685 iwn_hw_prepare(struct iwn_softc *sc) 8686 { 8687 int ntries; 8688 8689 DPRINTF(sc, IWN_DEBUG_TRACE, "->Doing %s\n", __func__); 8690 8691 /* Check if hardware is ready. */ 8692 IWN_SETBITS(sc, IWN_HW_IF_CONFIG, IWN_HW_IF_CONFIG_NIC_READY); 8693 for (ntries = 0; ntries < 5; ntries++) { 8694 if (IWN_READ(sc, IWN_HW_IF_CONFIG) & 8695 IWN_HW_IF_CONFIG_NIC_READY) 8696 return 0; 8697 DELAY(10); 8698 } 8699 8700 /* Hardware not ready, force into ready state. */ 8701 IWN_SETBITS(sc, IWN_HW_IF_CONFIG, IWN_HW_IF_CONFIG_PREPARE); 8702 for (ntries = 0; ntries < 15000; ntries++) { 8703 if (!(IWN_READ(sc, IWN_HW_IF_CONFIG) & 8704 IWN_HW_IF_CONFIG_PREPARE_DONE)) 8705 break; 8706 DELAY(10); 8707 } 8708 if (ntries == 15000) 8709 return ETIMEDOUT; 8710 8711 /* Hardware should be ready now. */ 8712 IWN_SETBITS(sc, IWN_HW_IF_CONFIG, IWN_HW_IF_CONFIG_NIC_READY); 8713 for (ntries = 0; ntries < 5; ntries++) { 8714 if (IWN_READ(sc, IWN_HW_IF_CONFIG) & 8715 IWN_HW_IF_CONFIG_NIC_READY) 8716 return 0; 8717 DELAY(10); 8718 } 8719 return ETIMEDOUT; 8720 } 8721 8722 static int 8723 iwn_hw_init(struct iwn_softc *sc) 8724 { 8725 struct iwn_ops *ops = &sc->ops; 8726 int error, chnl, qid; 8727 8728 DPRINTF(sc, IWN_DEBUG_TRACE, "->%s begin\n", __func__); 8729 8730 /* Clear pending interrupts. */ 8731 IWN_WRITE(sc, IWN_INT, 0xffffffff); 8732 8733 if ((error = iwn_apm_init(sc)) != 0) { 8734 device_printf(sc->sc_dev, 8735 "%s: could not power ON adapter, error %d\n", __func__, 8736 error); 8737 return error; 8738 } 8739 8740 /* Select VMAIN power source. */ 8741 if ((error = iwn_nic_lock(sc)) != 0) 8742 return error; 8743 iwn_prph_clrbits(sc, IWN_APMG_PS, IWN_APMG_PS_PWR_SRC_MASK); 8744 iwn_nic_unlock(sc); 8745 8746 /* Perform adapter-specific initialization. */ 8747 if ((error = ops->nic_config(sc)) != 0) 8748 return error; 8749 8750 /* Initialize RX ring. */ 8751 if ((error = iwn_nic_lock(sc)) != 0) 8752 return error; 8753 IWN_WRITE(sc, IWN_FH_RX_CONFIG, 0); 8754 IWN_WRITE(sc, IWN_FH_RX_WPTR, 0); 8755 /* Set physical address of RX ring (256-byte aligned). */ 8756 IWN_WRITE(sc, IWN_FH_RX_BASE, sc->rxq.desc_dma.paddr >> 8); 8757 /* Set physical address of RX status (16-byte aligned). */ 8758 IWN_WRITE(sc, IWN_FH_STATUS_WPTR, sc->rxq.stat_dma.paddr >> 4); 8759 /* Enable RX. */ 8760 IWN_WRITE(sc, IWN_FH_RX_CONFIG, 8761 IWN_FH_RX_CONFIG_ENA | 8762 IWN_FH_RX_CONFIG_IGN_RXF_EMPTY | /* HW bug workaround */ 8763 IWN_FH_RX_CONFIG_IRQ_DST_HOST | 8764 IWN_FH_RX_CONFIG_SINGLE_FRAME | 8765 IWN_FH_RX_CONFIG_RB_TIMEOUT(0) | 8766 IWN_FH_RX_CONFIG_NRBD(IWN_RX_RING_COUNT_LOG)); 8767 iwn_nic_unlock(sc); 8768 IWN_WRITE(sc, IWN_FH_RX_WPTR, (IWN_RX_RING_COUNT - 1) & ~7); 8769 8770 if ((error = iwn_nic_lock(sc)) != 0) 8771 return error; 8772 8773 /* Initialize TX scheduler. */ 8774 iwn_prph_write(sc, sc->sched_txfact_addr, 0); 8775 8776 /* Set physical address of "keep warm" page (16-byte aligned). */ 8777 IWN_WRITE(sc, IWN_FH_KW_ADDR, sc->kw_dma.paddr >> 4); 8778 8779 /* Initialize TX rings. */ 8780 for (qid = 0; qid < sc->ntxqs; qid++) { 8781 struct iwn_tx_ring *txq = &sc->txq[qid]; 8782 8783 /* Set physical address of TX ring (256-byte aligned). */ 8784 IWN_WRITE(sc, IWN_FH_CBBC_QUEUE(qid), 8785 txq->desc_dma.paddr >> 8); 8786 } 8787 iwn_nic_unlock(sc); 8788 8789 /* Enable DMA channels. */ 8790 for (chnl = 0; chnl < sc->ndmachnls; chnl++) { 8791 IWN_WRITE(sc, IWN_FH_TX_CONFIG(chnl), 8792 IWN_FH_TX_CONFIG_DMA_ENA | 8793 IWN_FH_TX_CONFIG_DMA_CREDIT_ENA); 8794 } 8795 8796 /* Clear "radio off" and "commands blocked" bits. */ 8797 IWN_WRITE(sc, IWN_UCODE_GP1_CLR, IWN_UCODE_GP1_RFKILL); 8798 IWN_WRITE(sc, IWN_UCODE_GP1_CLR, IWN_UCODE_GP1_CMD_BLOCKED); 8799 8800 /* Clear pending interrupts. */ 8801 IWN_WRITE(sc, IWN_INT, 0xffffffff); 8802 /* Enable interrupt coalescing. */ 8803 IWN_WRITE(sc, IWN_INT_COALESCING, 512 / 8); 8804 /* Enable interrupts. */ 8805 IWN_WRITE(sc, IWN_INT_MASK, sc->int_mask); 8806 8807 /* _Really_ make sure "radio off" bit is cleared! */ 8808 IWN_WRITE(sc, IWN_UCODE_GP1_CLR, IWN_UCODE_GP1_RFKILL); 8809 IWN_WRITE(sc, IWN_UCODE_GP1_CLR, IWN_UCODE_GP1_RFKILL); 8810 8811 /* Enable shadow registers. */ 8812 if (sc->base_params->shadow_reg_enable) 8813 IWN_SETBITS(sc, IWN_SHADOW_REG_CTRL, 0x800fffff); 8814 8815 if ((error = ops->load_firmware(sc)) != 0) { 8816 device_printf(sc->sc_dev, 8817 "%s: could not load firmware, error %d\n", __func__, 8818 error); 8819 return error; 8820 } 8821 /* Wait at most one second for firmware alive notification. */ 8822 if ((error = msleep(sc, &sc->sc_mtx, PCATCH, "iwninit", hz)) != 0) { 8823 device_printf(sc->sc_dev, 8824 "%s: timeout waiting for adapter to initialize, error %d\n", 8825 __func__, error); 8826 return error; 8827 } 8828 /* Do post-firmware initialization. */ 8829 8830 DPRINTF(sc, IWN_DEBUG_TRACE, "->%s: end\n",__func__); 8831 8832 return ops->post_alive(sc); 8833 } 8834 8835 static void 8836 iwn_hw_stop(struct iwn_softc *sc) 8837 { 8838 int chnl, qid, ntries; 8839 8840 DPRINTF(sc, IWN_DEBUG_TRACE, "->Doing %s\n", __func__); 8841 8842 IWN_WRITE(sc, IWN_RESET, IWN_RESET_NEVO); 8843 8844 /* Disable interrupts. */ 8845 IWN_WRITE(sc, IWN_INT_MASK, 0); 8846 IWN_WRITE(sc, IWN_INT, 0xffffffff); 8847 IWN_WRITE(sc, IWN_FH_INT, 0xffffffff); 8848 sc->sc_flags &= ~IWN_FLAG_USE_ICT; 8849 8850 /* Make sure we no longer hold the NIC lock. */ 8851 iwn_nic_unlock(sc); 8852 8853 /* Stop TX scheduler. */ 8854 iwn_prph_write(sc, sc->sched_txfact_addr, 0); 8855 8856 /* Stop all DMA channels. */ 8857 if (iwn_nic_lock(sc) == 0) { 8858 for (chnl = 0; chnl < sc->ndmachnls; chnl++) { 8859 IWN_WRITE(sc, IWN_FH_TX_CONFIG(chnl), 0); 8860 for (ntries = 0; ntries < 200; ntries++) { 8861 if (IWN_READ(sc, IWN_FH_TX_STATUS) & 8862 IWN_FH_TX_STATUS_IDLE(chnl)) 8863 break; 8864 DELAY(10); 8865 } 8866 } 8867 iwn_nic_unlock(sc); 8868 } 8869 8870 /* Stop RX ring. */ 8871 iwn_reset_rx_ring(sc, &sc->rxq); 8872 8873 /* Reset all TX rings. */ 8874 for (qid = 0; qid < sc->ntxqs; qid++) 8875 iwn_reset_tx_ring(sc, &sc->txq[qid]); 8876 8877 if (iwn_nic_lock(sc) == 0) { 8878 iwn_prph_write(sc, IWN_APMG_CLK_DIS, 8879 IWN_APMG_CLK_CTRL_DMA_CLK_RQT); 8880 iwn_nic_unlock(sc); 8881 } 8882 DELAY(5); 8883 /* Power OFF adapter. */ 8884 iwn_apm_stop(sc); 8885 } 8886 8887 static void 8888 iwn_panicked(void *arg0, int pending) 8889 { 8890 struct iwn_softc *sc = arg0; 8891 struct ieee80211com *ic = &sc->sc_ic; 8892 struct ieee80211vap *vap = TAILQ_FIRST(&ic->ic_vaps); 8893 #if 0 8894 int error; 8895 #endif 8896 8897 if (vap == NULL) { 8898 printf("%s: null vap\n", __func__); 8899 return; 8900 } 8901 8902 device_printf(sc->sc_dev, "%s: controller panicked, iv_state = %d; " 8903 "restarting\n", __func__, vap->iv_state); 8904 8905 /* 8906 * This is not enough work. We need to also reinitialise 8907 * the correct transmit state for aggregation enabled queues, 8908 * which has a very specific requirement of 8909 * ring index = 802.11 seqno % 256. If we don't do this (which 8910 * we definitely don't!) then the firmware will just panic again. 8911 */ 8912 #if 1 8913 ieee80211_restart_all(ic); 8914 #else 8915 IWN_LOCK(sc); 8916 8917 iwn_stop_locked(sc); 8918 if ((error = iwn_init_locked(sc)) != 0) { 8919 device_printf(sc->sc_dev, 8920 "%s: could not init hardware\n", __func__); 8921 goto unlock; 8922 } 8923 if (vap->iv_state >= IEEE80211_S_AUTH && 8924 (error = iwn_auth(sc, vap)) != 0) { 8925 device_printf(sc->sc_dev, 8926 "%s: could not move to auth state\n", __func__); 8927 } 8928 if (vap->iv_state >= IEEE80211_S_RUN && 8929 (error = iwn_run(sc, vap)) != 0) { 8930 device_printf(sc->sc_dev, 8931 "%s: could not move to run state\n", __func__); 8932 } 8933 8934 unlock: 8935 IWN_UNLOCK(sc); 8936 #endif 8937 } 8938 8939 static int 8940 iwn_init_locked(struct iwn_softc *sc) 8941 { 8942 int error; 8943 8944 DPRINTF(sc, IWN_DEBUG_TRACE, "->%s begin\n", __func__); 8945 8946 IWN_LOCK_ASSERT(sc); 8947 8948 if (sc->sc_flags & IWN_FLAG_RUNNING) 8949 goto end; 8950 8951 sc->sc_flags |= IWN_FLAG_RUNNING; 8952 8953 if ((error = iwn_hw_prepare(sc)) != 0) { 8954 device_printf(sc->sc_dev, "%s: hardware not ready, error %d\n", 8955 __func__, error); 8956 goto fail; 8957 } 8958 8959 /* Initialize interrupt mask to default value. */ 8960 sc->int_mask = IWN_INT_MASK_DEF; 8961 sc->sc_flags &= ~IWN_FLAG_USE_ICT; 8962 8963 /* Check that the radio is not disabled by hardware switch. */ 8964 if (!(IWN_READ(sc, IWN_GP_CNTRL) & IWN_GP_CNTRL_RFKILL)) { 8965 iwn_stop_locked(sc); 8966 DPRINTF(sc, IWN_DEBUG_TRACE, "->%s: end\n",__func__); 8967 8968 return (1); 8969 } 8970 8971 /* Read firmware images from the filesystem. */ 8972 if ((error = iwn_read_firmware(sc)) != 0) { 8973 device_printf(sc->sc_dev, 8974 "%s: could not read firmware, error %d\n", __func__, 8975 error); 8976 goto fail; 8977 } 8978 8979 /* Initialize hardware and upload firmware. */ 8980 error = iwn_hw_init(sc); 8981 iwn_unload_firmware(sc); 8982 if (error != 0) { 8983 device_printf(sc->sc_dev, 8984 "%s: could not initialize hardware, error %d\n", __func__, 8985 error); 8986 goto fail; 8987 } 8988 8989 /* Configure adapter now that it is ready. */ 8990 if ((error = iwn_config(sc)) != 0) { 8991 device_printf(sc->sc_dev, 8992 "%s: could not configure device, error %d\n", __func__, 8993 error); 8994 goto fail; 8995 } 8996 8997 callout_reset(&sc->watchdog_to, hz, iwn_watchdog, sc); 8998 8999 end: 9000 DPRINTF(sc, IWN_DEBUG_TRACE, "->%s: end\n",__func__); 9001 9002 return (0); 9003 9004 fail: 9005 iwn_stop_locked(sc); 9006 9007 DPRINTF(sc, IWN_DEBUG_TRACE, "->%s: end in error\n",__func__); 9008 9009 return (-1); 9010 } 9011 9012 static int 9013 iwn_init(struct iwn_softc *sc) 9014 { 9015 int error; 9016 9017 IWN_LOCK(sc); 9018 error = iwn_init_locked(sc); 9019 IWN_UNLOCK(sc); 9020 9021 return (error); 9022 } 9023 9024 static void 9025 iwn_stop_locked(struct iwn_softc *sc) 9026 { 9027 9028 IWN_LOCK_ASSERT(sc); 9029 9030 if (!(sc->sc_flags & IWN_FLAG_RUNNING)) 9031 return; 9032 9033 sc->sc_is_scanning = 0; 9034 sc->sc_tx_timer = 0; 9035 callout_stop(&sc->watchdog_to); 9036 callout_stop(&sc->scan_timeout); 9037 callout_stop(&sc->calib_to); 9038 sc->sc_flags &= ~IWN_FLAG_RUNNING; 9039 9040 /* Power OFF hardware. */ 9041 iwn_hw_stop(sc); 9042 } 9043 9044 static void 9045 iwn_stop(struct iwn_softc *sc) 9046 { 9047 IWN_LOCK(sc); 9048 iwn_stop_locked(sc); 9049 IWN_UNLOCK(sc); 9050 } 9051 9052 /* 9053 * Callback from net80211 to start a scan. 9054 */ 9055 static void 9056 iwn_scan_start(struct ieee80211com *ic) 9057 { 9058 struct iwn_softc *sc = ic->ic_softc; 9059 9060 IWN_LOCK(sc); 9061 /* make the link LED blink while we're scanning */ 9062 iwn_set_led(sc, IWN_LED_LINK, 20, 2); 9063 IWN_UNLOCK(sc); 9064 } 9065 9066 /* 9067 * Callback from net80211 to terminate a scan. 9068 */ 9069 static void 9070 iwn_scan_end(struct ieee80211com *ic) 9071 { 9072 struct iwn_softc *sc = ic->ic_softc; 9073 struct ieee80211vap *vap = TAILQ_FIRST(&ic->ic_vaps); 9074 9075 IWN_LOCK(sc); 9076 if (vap->iv_state == IEEE80211_S_RUN) { 9077 /* Set link LED to ON status if we are associated */ 9078 iwn_set_led(sc, IWN_LED_LINK, 0, 1); 9079 } 9080 IWN_UNLOCK(sc); 9081 } 9082 9083 /* 9084 * Callback from net80211 to force a channel change. 9085 */ 9086 static void 9087 iwn_set_channel(struct ieee80211com *ic) 9088 { 9089 const struct ieee80211_channel *c = ic->ic_curchan; 9090 struct iwn_softc *sc = ic->ic_softc; 9091 int error; 9092 9093 DPRINTF(sc, IWN_DEBUG_TRACE, "->Doing %s\n", __func__); 9094 9095 IWN_LOCK(sc); 9096 sc->sc_rxtap.wr_chan_freq = htole16(c->ic_freq); 9097 sc->sc_rxtap.wr_chan_flags = htole16(c->ic_flags); 9098 sc->sc_txtap.wt_chan_freq = htole16(c->ic_freq); 9099 sc->sc_txtap.wt_chan_flags = htole16(c->ic_flags); 9100 9101 /* 9102 * Only need to set the channel in Monitor mode. AP scanning and auth 9103 * are already taken care of by their respective firmware commands. 9104 */ 9105 if (ic->ic_opmode == IEEE80211_M_MONITOR) { 9106 error = iwn_config(sc); 9107 if (error != 0) 9108 device_printf(sc->sc_dev, 9109 "%s: error %d settting channel\n", __func__, error); 9110 } 9111 IWN_UNLOCK(sc); 9112 } 9113 9114 /* 9115 * Callback from net80211 to start scanning of the current channel. 9116 */ 9117 static void 9118 iwn_scan_curchan(struct ieee80211_scan_state *ss, unsigned long maxdwell) 9119 { 9120 struct ieee80211vap *vap = ss->ss_vap; 9121 struct ieee80211com *ic = vap->iv_ic; 9122 struct iwn_softc *sc = ic->ic_softc; 9123 int error; 9124 9125 IWN_LOCK(sc); 9126 error = iwn_scan(sc, vap, ss, ic->ic_curchan); 9127 IWN_UNLOCK(sc); 9128 if (error != 0) 9129 ieee80211_cancel_scan(vap); 9130 } 9131 9132 /* 9133 * Callback from net80211 to handle the minimum dwell time being met. 9134 * The intent is to terminate the scan but we just let the firmware 9135 * notify us when it's finished as we have no safe way to abort it. 9136 */ 9137 static void 9138 iwn_scan_mindwell(struct ieee80211_scan_state *ss) 9139 { 9140 /* NB: don't try to abort scan; wait for firmware to finish */ 9141 } 9142 #ifdef IWN_DEBUG 9143 #define IWN_DESC(x) case x: return #x 9144 9145 /* 9146 * Translate CSR code to string 9147 */ 9148 static char *iwn_get_csr_string(int csr) 9149 { 9150 switch (csr) { 9151 IWN_DESC(IWN_HW_IF_CONFIG); 9152 IWN_DESC(IWN_INT_COALESCING); 9153 IWN_DESC(IWN_INT); 9154 IWN_DESC(IWN_INT_MASK); 9155 IWN_DESC(IWN_FH_INT); 9156 IWN_DESC(IWN_GPIO_IN); 9157 IWN_DESC(IWN_RESET); 9158 IWN_DESC(IWN_GP_CNTRL); 9159 IWN_DESC(IWN_HW_REV); 9160 IWN_DESC(IWN_EEPROM); 9161 IWN_DESC(IWN_EEPROM_GP); 9162 IWN_DESC(IWN_OTP_GP); 9163 IWN_DESC(IWN_GIO); 9164 IWN_DESC(IWN_GP_UCODE); 9165 IWN_DESC(IWN_GP_DRIVER); 9166 IWN_DESC(IWN_UCODE_GP1); 9167 IWN_DESC(IWN_UCODE_GP2); 9168 IWN_DESC(IWN_LED); 9169 IWN_DESC(IWN_DRAM_INT_TBL); 9170 IWN_DESC(IWN_GIO_CHICKEN); 9171 IWN_DESC(IWN_ANA_PLL); 9172 IWN_DESC(IWN_HW_REV_WA); 9173 IWN_DESC(IWN_DBG_HPET_MEM); 9174 default: 9175 return "UNKNOWN CSR"; 9176 } 9177 } 9178 9179 /* 9180 * This function print firmware register 9181 */ 9182 static void 9183 iwn_debug_register(struct iwn_softc *sc) 9184 { 9185 int i; 9186 static const uint32_t csr_tbl[] = { 9187 IWN_HW_IF_CONFIG, 9188 IWN_INT_COALESCING, 9189 IWN_INT, 9190 IWN_INT_MASK, 9191 IWN_FH_INT, 9192 IWN_GPIO_IN, 9193 IWN_RESET, 9194 IWN_GP_CNTRL, 9195 IWN_HW_REV, 9196 IWN_EEPROM, 9197 IWN_EEPROM_GP, 9198 IWN_OTP_GP, 9199 IWN_GIO, 9200 IWN_GP_UCODE, 9201 IWN_GP_DRIVER, 9202 IWN_UCODE_GP1, 9203 IWN_UCODE_GP2, 9204 IWN_LED, 9205 IWN_DRAM_INT_TBL, 9206 IWN_GIO_CHICKEN, 9207 IWN_ANA_PLL, 9208 IWN_HW_REV_WA, 9209 IWN_DBG_HPET_MEM, 9210 }; 9211 DPRINTF(sc, IWN_DEBUG_REGISTER, 9212 "CSR values: (2nd byte of IWN_INT_COALESCING is IWN_INT_PERIODIC)%s", 9213 "\n"); 9214 for (i = 0; i < nitems(csr_tbl); i++){ 9215 DPRINTF(sc, IWN_DEBUG_REGISTER," %10s: 0x%08x ", 9216 iwn_get_csr_string(csr_tbl[i]), IWN_READ(sc, csr_tbl[i])); 9217 if ((i+1) % 3 == 0) 9218 DPRINTF(sc, IWN_DEBUG_REGISTER,"%s","\n"); 9219 } 9220 DPRINTF(sc, IWN_DEBUG_REGISTER,"%s","\n"); 9221 } 9222 #endif 9223 9224 9225