1 /*- 2 * Copyright (c) 2007-2009 3 * Damien Bergamini <damien.bergamini@free.fr> 4 * Copyright (c) 2008 5 * Benjamin Close <benjsc@FreeBSD.org> 6 * Copyright (c) 2008 Sam Leffler, Errno Consulting 7 * 8 * Permission to use, copy, modify, and distribute this software for any 9 * purpose with or without fee is hereby granted, provided that the above 10 * copyright notice and this permission notice appear in all copies. 11 * 12 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 13 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 14 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR 15 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 16 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN 17 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF 18 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 19 */ 20 21 /* 22 * Driver for Intel WiFi Link 4965 and 1000/5000/6000 Series 802.11 network 23 * adapters. 24 */ 25 26 #include <sys/cdefs.h> 27 __FBSDID("$FreeBSD$"); 28 29 #include <sys/param.h> 30 #include <sys/sockio.h> 31 #include <sys/sysctl.h> 32 #include <sys/mbuf.h> 33 #include <sys/kernel.h> 34 #include <sys/socket.h> 35 #include <sys/systm.h> 36 #include <sys/malloc.h> 37 #include <sys/bus.h> 38 #include <sys/rman.h> 39 #include <sys/endian.h> 40 #include <sys/firmware.h> 41 #include <sys/limits.h> 42 #include <sys/module.h> 43 #include <sys/queue.h> 44 #include <sys/taskqueue.h> 45 46 #include <machine/bus.h> 47 #include <machine/resource.h> 48 #include <machine/clock.h> 49 50 #include <dev/pci/pcireg.h> 51 #include <dev/pci/pcivar.h> 52 53 #include <net/bpf.h> 54 #include <net/if.h> 55 #include <net/if_arp.h> 56 #include <net/ethernet.h> 57 #include <net/if_dl.h> 58 #include <net/if_media.h> 59 #include <net/if_types.h> 60 61 #include <netinet/in.h> 62 #include <netinet/in_systm.h> 63 #include <netinet/in_var.h> 64 #include <netinet/if_ether.h> 65 #include <netinet/ip.h> 66 67 #include <net80211/ieee80211_var.h> 68 #include <net80211/ieee80211_amrr.h> 69 #include <net80211/ieee80211_radiotap.h> 70 #include <net80211/ieee80211_regdomain.h> 71 72 #include <dev/iwn/if_iwnreg.h> 73 #include <dev/iwn/if_iwnvar.h> 74 75 static int iwn_probe(device_t); 76 static int iwn_attach(device_t); 77 const struct iwn_hal *iwn_hal_attach(struct iwn_softc *); 78 void iwn_radiotap_attach(struct iwn_softc *); 79 static struct ieee80211vap *iwn_vap_create(struct ieee80211com *, 80 const char name[IFNAMSIZ], int unit, int opmode, 81 int flags, const uint8_t bssid[IEEE80211_ADDR_LEN], 82 const uint8_t mac[IEEE80211_ADDR_LEN]); 83 static void iwn_vap_delete(struct ieee80211vap *); 84 static int iwn_cleanup(device_t); 85 static int iwn_detach(device_t); 86 int iwn_nic_lock(struct iwn_softc *); 87 int iwn_eeprom_lock(struct iwn_softc *); 88 int iwn_init_otprom(struct iwn_softc *); 89 int iwn_read_prom_data(struct iwn_softc *, uint32_t, void *, int); 90 static int iwn_dma_contig_alloc(struct iwn_softc *, struct iwn_dma_info *, 91 void **, bus_size_t, bus_size_t, int); 92 static void iwn_dma_contig_free(struct iwn_dma_info *); 93 int iwn_alloc_sched(struct iwn_softc *); 94 void iwn_free_sched(struct iwn_softc *); 95 int iwn_alloc_kw(struct iwn_softc *); 96 void iwn_free_kw(struct iwn_softc *); 97 int iwn_alloc_ict(struct iwn_softc *); 98 void iwn_free_ict(struct iwn_softc *); 99 int iwn_alloc_fwmem(struct iwn_softc *); 100 void iwn_free_fwmem(struct iwn_softc *); 101 int iwn_alloc_rx_ring(struct iwn_softc *, struct iwn_rx_ring *); 102 void iwn_reset_rx_ring(struct iwn_softc *, struct iwn_rx_ring *); 103 void iwn_free_rx_ring(struct iwn_softc *, struct iwn_rx_ring *); 104 int iwn_alloc_tx_ring(struct iwn_softc *, struct iwn_tx_ring *, 105 int); 106 void iwn_reset_tx_ring(struct iwn_softc *, struct iwn_tx_ring *); 107 void iwn_free_tx_ring(struct iwn_softc *, struct iwn_tx_ring *); 108 void iwn5000_ict_reset(struct iwn_softc *); 109 int iwn_read_eeprom(struct iwn_softc *, 110 uint8_t macaddr[IEEE80211_ADDR_LEN]); 111 void iwn4965_read_eeprom(struct iwn_softc *); 112 void iwn4965_print_power_group(struct iwn_softc *, int); 113 void iwn5000_read_eeprom(struct iwn_softc *); 114 static void iwn_read_eeprom_channels(struct iwn_softc *, int, 115 uint32_t); 116 void iwn_read_eeprom_enhinfo(struct iwn_softc *); 117 struct ieee80211_node *iwn_node_alloc(struct ieee80211vap *, 118 const uint8_t mac[IEEE80211_ADDR_LEN]); 119 void iwn_newassoc(struct ieee80211_node *, int); 120 int iwn_media_change(struct ifnet *); 121 int iwn_newstate(struct ieee80211vap *, enum ieee80211_state, int); 122 void iwn_rx_phy(struct iwn_softc *, struct iwn_rx_desc *, 123 struct iwn_rx_data *); 124 static void iwn_timer_timeout(void *); 125 static void iwn_calib_reset(struct iwn_softc *); 126 void iwn_rx_done(struct iwn_softc *, struct iwn_rx_desc *, 127 struct iwn_rx_data *); 128 #if 0 /* HT */ 129 void iwn_rx_compressed_ba(struct iwn_softc *, struct iwn_rx_desc *, 130 struct iwn_rx_data *); 131 #endif 132 void iwn5000_rx_calib_results(struct iwn_softc *, 133 struct iwn_rx_desc *, struct iwn_rx_data *); 134 void iwn_rx_statistics(struct iwn_softc *, struct iwn_rx_desc *, 135 struct iwn_rx_data *); 136 void iwn4965_tx_done(struct iwn_softc *, struct iwn_rx_desc *, 137 struct iwn_rx_data *); 138 void iwn5000_tx_done(struct iwn_softc *, struct iwn_rx_desc *, 139 struct iwn_rx_data *); 140 void iwn_tx_done(struct iwn_softc *, struct iwn_rx_desc *, int, 141 uint8_t); 142 void iwn_cmd_done(struct iwn_softc *, struct iwn_rx_desc *); 143 void iwn_notif_intr(struct iwn_softc *); 144 void iwn_wakeup_intr(struct iwn_softc *); 145 void iwn_rftoggle_intr(struct iwn_softc *); 146 void iwn_fatal_intr(struct iwn_softc *); 147 void iwn_intr(void *); 148 void iwn4965_update_sched(struct iwn_softc *, int, int, uint8_t, 149 uint16_t); 150 void iwn5000_update_sched(struct iwn_softc *, int, int, uint8_t, 151 uint16_t); 152 void iwn5000_reset_sched(struct iwn_softc *, int, int); 153 int iwn_tx_data(struct iwn_softc *, struct mbuf *, 154 struct ieee80211_node *, struct iwn_tx_ring *); 155 static int iwn_raw_xmit(struct ieee80211_node *, struct mbuf *, 156 const struct ieee80211_bpf_params *); 157 void iwn_start(struct ifnet *); 158 void iwn_start_locked(struct ifnet *); 159 static void iwn_watchdog(struct iwn_softc *sc); 160 int iwn_ioctl(struct ifnet *, u_long, caddr_t); 161 int iwn_cmd(struct iwn_softc *, int, const void *, int, int); 162 int iwn4965_add_node(struct iwn_softc *, struct iwn_node_info *, 163 int); 164 int iwn5000_add_node(struct iwn_softc *, struct iwn_node_info *, 165 int); 166 int iwn_set_link_quality(struct iwn_softc *, uint8_t, int); 167 int iwn_add_broadcast_node(struct iwn_softc *, int); 168 int iwn_wme_update(struct ieee80211com *); 169 static void iwn_update_mcast(struct ifnet *); 170 void iwn_set_led(struct iwn_softc *, uint8_t, uint8_t, uint8_t); 171 int iwn_set_critical_temp(struct iwn_softc *); 172 int iwn_set_timing(struct iwn_softc *, struct ieee80211_node *); 173 void iwn4965_power_calibration(struct iwn_softc *, int); 174 int iwn4965_set_txpower(struct iwn_softc *, int); 175 int iwn5000_set_txpower(struct iwn_softc *, int); 176 int iwn4965_get_rssi(struct iwn_softc *, struct iwn_rx_stat *); 177 int iwn5000_get_rssi(struct iwn_softc *, struct iwn_rx_stat *); 178 int iwn_get_noise(const struct iwn_rx_general_stats *); 179 int iwn4965_get_temperature(struct iwn_softc *); 180 int iwn5000_get_temperature(struct iwn_softc *); 181 int iwn_init_sensitivity(struct iwn_softc *); 182 void iwn_collect_noise(struct iwn_softc *, 183 const struct iwn_rx_general_stats *); 184 int iwn4965_init_gains(struct iwn_softc *); 185 int iwn5000_init_gains(struct iwn_softc *); 186 int iwn4965_set_gains(struct iwn_softc *); 187 int iwn5000_set_gains(struct iwn_softc *); 188 void iwn_tune_sensitivity(struct iwn_softc *, 189 const struct iwn_rx_stats *); 190 int iwn_send_sensitivity(struct iwn_softc *); 191 int iwn_set_pslevel(struct iwn_softc *, int, int, int); 192 int iwn_config(struct iwn_softc *); 193 int iwn_scan(struct iwn_softc *); 194 int iwn_auth(struct iwn_softc *, struct ieee80211vap *vap); 195 int iwn_run(struct iwn_softc *, struct ieee80211vap *vap); 196 int iwn5000_query_calibration(struct iwn_softc *); 197 int iwn5000_send_calibration(struct iwn_softc *); 198 int iwn5000_send_wimax_coex(struct iwn_softc *); 199 int iwn4965_post_alive(struct iwn_softc *); 200 int iwn5000_post_alive(struct iwn_softc *); 201 int iwn4965_load_bootcode(struct iwn_softc *, const uint8_t *, 202 int); 203 int iwn4965_load_firmware(struct iwn_softc *); 204 int iwn5000_load_firmware_section(struct iwn_softc *, uint32_t, 205 const uint8_t *, int); 206 int iwn5000_load_firmware(struct iwn_softc *); 207 int iwn_read_firmware(struct iwn_softc *); 208 int iwn_clock_wait(struct iwn_softc *); 209 int iwn_apm_init(struct iwn_softc *); 210 void iwn_apm_stop_master(struct iwn_softc *); 211 void iwn_apm_stop(struct iwn_softc *); 212 int iwn4965_nic_config(struct iwn_softc *); 213 int iwn5000_nic_config(struct iwn_softc *); 214 int iwn_hw_prepare(struct iwn_softc *); 215 int iwn_hw_init(struct iwn_softc *); 216 void iwn_hw_stop(struct iwn_softc *); 217 void iwn_init_locked(struct iwn_softc *); 218 void iwn_init(void *); 219 void iwn_stop_locked(struct iwn_softc *); 220 void iwn_stop(struct iwn_softc *); 221 static void iwn_scan_start(struct ieee80211com *); 222 static void iwn_scan_end(struct ieee80211com *); 223 static void iwn_set_channel(struct ieee80211com *); 224 static void iwn_scan_curchan(struct ieee80211_scan_state *, unsigned long); 225 static void iwn_scan_mindwell(struct ieee80211_scan_state *); 226 static int iwn_setregdomain(struct ieee80211com *, 227 struct ieee80211_regdomain *, int, 228 struct ieee80211_channel []); 229 static void iwn_hw_reset(void *, int); 230 static void iwn_radio_on(void *, int); 231 static void iwn_radio_off(void *, int); 232 static void iwn_sysctlattach(struct iwn_softc *); 233 static int iwn_shutdown(device_t); 234 static int iwn_suspend(device_t); 235 static int iwn_resume(device_t); 236 237 #define IWN_DEBUG 238 #ifdef IWN_DEBUG 239 enum { 240 IWN_DEBUG_XMIT = 0x00000001, /* basic xmit operation */ 241 IWN_DEBUG_RECV = 0x00000002, /* basic recv operation */ 242 IWN_DEBUG_STATE = 0x00000004, /* 802.11 state transitions */ 243 IWN_DEBUG_TXPOW = 0x00000008, /* tx power processing */ 244 IWN_DEBUG_RESET = 0x00000010, /* reset processing */ 245 IWN_DEBUG_OPS = 0x00000020, /* iwn_ops processing */ 246 IWN_DEBUG_BEACON = 0x00000040, /* beacon handling */ 247 IWN_DEBUG_WATCHDOG = 0x00000080, /* watchdog timeout */ 248 IWN_DEBUG_INTR = 0x00000100, /* ISR */ 249 IWN_DEBUG_CALIBRATE = 0x00000200, /* periodic calibration */ 250 IWN_DEBUG_NODE = 0x00000400, /* node management */ 251 IWN_DEBUG_LED = 0x00000800, /* led management */ 252 IWN_DEBUG_CMD = 0x00001000, /* cmd submission */ 253 IWN_DEBUG_FATAL = 0x80000000, /* fatal errors */ 254 IWN_DEBUG_ANY = 0xffffffff 255 }; 256 257 #define DPRINTF(sc, m, fmt, ...) do { \ 258 if (sc->sc_debug & (m)) \ 259 printf(fmt, __VA_ARGS__); \ 260 } while (0) 261 262 static const char *iwn_intr_str(uint8_t); 263 #else 264 #define DPRINTF(sc, m, fmt, ...) do { (void) sc; } while (0) 265 #endif 266 267 struct iwn_ident { 268 uint16_t vendor; 269 uint16_t device; 270 const char *name; 271 }; 272 273 static const struct iwn_ident iwn_ident_table [] = { 274 { 0x8086, 0x4229, "Intel(R) PRO/Wireless 4965BGN" }, 275 { 0x8086, 0x422D, "Intel(R) PRO/Wireless 4965BGN" }, 276 { 0x8086, 0x4230, "Intel(R) PRO/Wireless 4965BGN" }, 277 { 0x8086, 0x4233, "Intel(R) PRO/Wireless 4965BGN" }, 278 { 0x8086, 0x4232, "Intel(R) PRO/Wireless 5100" }, 279 { 0x8086, 0x4237, "Intel(R) PRO/Wireless 5100" }, 280 { 0x8086, 0x423C, "Intel(R) PRO/Wireless 5150" }, 281 { 0x8086, 0x423D, "Intel(R) PRO/Wireless 5150" }, 282 { 0x8086, 0x4235, "Intel(R) PRO/Wireless 5300" }, 283 { 0x8086, 0x4236, "Intel(R) PRO/Wireless 5300" }, 284 { 0x8086, 0x4236, "Intel(R) PRO/Wireless 5350" }, 285 { 0x8086, 0x423A, "Intel(R) PRO/Wireless 5350" }, 286 { 0x8086, 0x423B, "Intel(R) PRO/Wireless 5350" }, 287 { 0x8086, 0x0083, "Intel(R) PRO/Wireless 1000" }, 288 { 0x8086, 0x0084, "Intel(R) PRO/Wireless 1000" }, 289 { 0x8086, 0x008D, "Intel(R) PRO/Wireless 6000" }, 290 { 0x8086, 0x008E, "Intel(R) PRO/Wireless 6000" }, 291 { 0x8086, 0x4238, "Intel(R) PRO/Wireless 6000" }, 292 { 0x8086, 0x4239, "Intel(R) PRO/Wireless 6000" }, 293 { 0x8086, 0x422B, "Intel(R) PRO/Wireless 6000" }, 294 { 0x8086, 0x422C, "Intel(R) PRO/Wireless 6000" }, 295 { 0x8086, 0x0086, "Intel(R) PRO/Wireless 6050" }, 296 { 0x8086, 0x0087, "Intel(R) PRO/Wireless 6050" }, 297 { 0, 0, NULL } 298 }; 299 300 static const struct iwn_hal iwn4965_hal = { 301 iwn4965_load_firmware, 302 iwn4965_read_eeprom, 303 iwn4965_post_alive, 304 iwn4965_nic_config, 305 iwn4965_update_sched, 306 iwn4965_get_temperature, 307 iwn4965_get_rssi, 308 iwn4965_set_txpower, 309 iwn4965_init_gains, 310 iwn4965_set_gains, 311 iwn4965_add_node, 312 iwn4965_tx_done, 313 #if 0 /* HT */ 314 iwn4965_ampdu_tx_start, 315 iwn4965_ampdu_tx_stop, 316 #endif 317 IWN4965_NTXQUEUES, 318 IWN4965_NDMACHNLS, 319 IWN4965_ID_BROADCAST, 320 IWN4965_RXONSZ, 321 IWN4965_SCHEDSZ, 322 IWN4965_FW_TEXT_MAXSZ, 323 IWN4965_FW_DATA_MAXSZ, 324 IWN4965_FWSZ, 325 IWN4965_SCHED_TXFACT 326 }; 327 328 static const struct iwn_hal iwn5000_hal = { 329 iwn5000_load_firmware, 330 iwn5000_read_eeprom, 331 iwn5000_post_alive, 332 iwn5000_nic_config, 333 iwn5000_update_sched, 334 iwn5000_get_temperature, 335 iwn5000_get_rssi, 336 iwn5000_set_txpower, 337 iwn5000_init_gains, 338 iwn5000_set_gains, 339 iwn5000_add_node, 340 iwn5000_tx_done, 341 #if 0 /* HT */ 342 iwn5000_ampdu_tx_start, 343 iwn5000_ampdu_tx_stop, 344 #endif 345 IWN5000_NTXQUEUES, 346 IWN5000_NDMACHNLS, 347 IWN5000_ID_BROADCAST, 348 IWN5000_RXONSZ, 349 IWN5000_SCHEDSZ, 350 IWN5000_FW_TEXT_MAXSZ, 351 IWN5000_FW_DATA_MAXSZ, 352 IWN5000_FWSZ, 353 IWN5000_SCHED_TXFACT 354 }; 355 356 static int 357 iwn_probe(device_t dev) 358 { 359 const struct iwn_ident *ident; 360 361 for (ident = iwn_ident_table; ident->name != NULL; ident++) { 362 if (pci_get_vendor(dev) == ident->vendor && 363 pci_get_device(dev) == ident->device) { 364 device_set_desc(dev, ident->name); 365 return 0; 366 } 367 } 368 return ENXIO; 369 } 370 371 static int 372 iwn_attach(device_t dev) 373 { 374 struct iwn_softc *sc = (struct iwn_softc *)device_get_softc(dev); 375 struct ieee80211com *ic; 376 struct ifnet *ifp; 377 const struct iwn_hal *hal; 378 uint32_t tmp; 379 int i, error, result; 380 uint8_t macaddr[IEEE80211_ADDR_LEN]; 381 382 sc->sc_dev = dev; 383 384 /* 385 * Get the offset of the PCI Express Capability Structure in PCI 386 * Configuration Space. 387 */ 388 error = pci_find_extcap(dev, PCIY_EXPRESS, &sc->sc_cap_off); 389 if (error != 0) { 390 device_printf(dev, "PCIe capability structure not found!\n"); 391 return error; 392 } 393 394 /* Clear device-specific "PCI retry timeout" register (41h). */ 395 pci_write_config(dev, 0x41, 0, 1); 396 397 /* Hardware bug workaround. */ 398 tmp = pci_read_config(dev, PCIR_COMMAND, 1); 399 if (tmp & PCIM_CMD_INTxDIS) { 400 DPRINTF(sc, IWN_DEBUG_RESET, "%s: PCIe INTx Disable set\n", 401 __func__); 402 tmp &= ~PCIM_CMD_INTxDIS; 403 pci_write_config(dev, PCIR_COMMAND, tmp, 1); 404 } 405 406 /* Enable bus-mastering. */ 407 pci_enable_busmaster(dev); 408 409 sc->mem_rid = PCIR_BAR(0); 410 sc->mem = bus_alloc_resource_any(dev, SYS_RES_MEMORY, &sc->mem_rid, 411 RF_ACTIVE); 412 if (sc->mem == NULL ) { 413 device_printf(dev, "could not allocate memory resources\n"); 414 error = ENOMEM; 415 return error; 416 } 417 418 sc->sc_st = rman_get_bustag(sc->mem); 419 sc->sc_sh = rman_get_bushandle(sc->mem); 420 sc->irq_rid = 0; 421 if ((result = pci_msi_count(dev)) == 1 && 422 pci_alloc_msi(dev, &result) == 0) 423 sc->irq_rid = 1; 424 sc->irq = bus_alloc_resource_any(dev, SYS_RES_IRQ, &sc->irq_rid, 425 RF_ACTIVE | RF_SHAREABLE); 426 if (sc->irq == NULL) { 427 device_printf(dev, "could not allocate interrupt resource\n"); 428 error = ENOMEM; 429 goto fail; 430 } 431 432 IWN_LOCK_INIT(sc); 433 callout_init_mtx(&sc->sc_timer_to, &sc->sc_mtx, 0); 434 TASK_INIT(&sc->sc_reinit_task, 0, iwn_hw_reset, sc ); 435 TASK_INIT(&sc->sc_radioon_task, 0, iwn_radio_on, sc ); 436 TASK_INIT(&sc->sc_radiooff_task, 0, iwn_radio_off, sc ); 437 438 /* Attach Hardware Abstraction Layer. */ 439 hal = iwn_hal_attach(sc); 440 if (hal == NULL) { 441 error = ENXIO; /* XXX: Wrong error code? */ 442 goto fail; 443 } 444 445 error = iwn_hw_prepare(sc); 446 if (error != 0) { 447 device_printf(dev, "hardware not ready, error %d\n", error); 448 goto fail; 449 } 450 451 /* Allocate DMA memory for firmware transfers. */ 452 error = iwn_alloc_fwmem(sc); 453 if (error != 0) { 454 device_printf(dev, 455 "could not allocate memory for firmware, error %d\n", 456 error); 457 goto fail; 458 } 459 460 /* Allocate "Keep Warm" page. */ 461 error = iwn_alloc_kw(sc); 462 if (error != 0) { 463 device_printf(dev, 464 "could not allocate \"Keep Warm\" page, error %d\n", error); 465 goto fail; 466 } 467 468 /* Allocate ICT table for 5000 Series. */ 469 if (sc->hw_type != IWN_HW_REV_TYPE_4965 && 470 (error = iwn_alloc_ict(sc)) != 0) { 471 device_printf(dev, 472 "%s: could not allocate ICT table, error %d\n", 473 __func__, error); 474 goto fail; 475 } 476 477 /* Allocate TX scheduler "rings". */ 478 error = iwn_alloc_sched(sc); 479 if (error != 0) { 480 device_printf(dev, 481 "could not allocate TX scheduler rings, error %d\n", 482 error); 483 goto fail; 484 } 485 486 /* Allocate TX rings (16 on 4965AGN, 20 on 5000). */ 487 for (i = 0; i < hal->ntxqs; i++) { 488 error = iwn_alloc_tx_ring(sc, &sc->txq[i], i); 489 if (error != 0) { 490 device_printf(dev, 491 "could not allocate Tx ring %d, error %d\n", 492 i, error); 493 goto fail; 494 } 495 } 496 497 /* Allocate RX ring. */ 498 error = iwn_alloc_rx_ring(sc, &sc->rxq); 499 if (error != 0 ){ 500 device_printf(dev, 501 "could not allocate Rx ring, error %d\n", error); 502 goto fail; 503 } 504 505 /* Clear pending interrupts. */ 506 IWN_WRITE(sc, IWN_INT, 0xffffffff); 507 508 /* Count the number of available chains. */ 509 sc->ntxchains = 510 ((sc->txchainmask >> 2) & 1) + 511 ((sc->txchainmask >> 1) & 1) + 512 ((sc->txchainmask >> 0) & 1); 513 sc->nrxchains = 514 ((sc->rxchainmask >> 2) & 1) + 515 ((sc->rxchainmask >> 1) & 1) + 516 ((sc->rxchainmask >> 0) & 1); 517 518 ifp = sc->sc_ifp = if_alloc(IFT_IEEE80211); 519 if (ifp == NULL) { 520 device_printf(dev, "can not allocate ifnet structure\n"); 521 goto fail; 522 } 523 ic = ifp->if_l2com; 524 525 ic->ic_ifp = ifp; 526 ic->ic_phytype = IEEE80211_T_OFDM; /* not only, but not used */ 527 ic->ic_opmode = IEEE80211_M_STA; /* default to BSS mode */ 528 529 /* Set device capabilities. */ 530 ic->ic_caps = 531 IEEE80211_C_STA /* station mode supported */ 532 | IEEE80211_C_MONITOR /* monitor mode supported */ 533 | IEEE80211_C_TXPMGT /* tx power management */ 534 | IEEE80211_C_SHSLOT /* short slot time supported */ 535 | IEEE80211_C_WPA 536 | IEEE80211_C_SHPREAMBLE /* short preamble supported */ 537 | IEEE80211_C_BGSCAN /* background scanning */ 538 #if 0 539 | IEEE80211_C_IBSS /* ibss/adhoc mode */ 540 #endif 541 | IEEE80211_C_WME /* WME */ 542 ; 543 #if 0 /* HT */ 544 /* XXX disable until HT channel setup works */ 545 ic->ic_htcaps = 546 IEEE80211_HTCAP_SMPS_ENA /* SM PS mode enabled */ 547 | IEEE80211_HTCAP_CHWIDTH40 /* 40MHz channel width */ 548 | IEEE80211_HTCAP_SHORTGI20 /* short GI in 20MHz */ 549 | IEEE80211_HTCAP_SHORTGI40 /* short GI in 40MHz */ 550 | IEEE80211_HTCAP_RXSTBC_2STREAM/* 1-2 spatial streams */ 551 | IEEE80211_HTCAP_MAXAMSDU_3839 /* max A-MSDU length */ 552 /* s/w capabilities */ 553 | IEEE80211_HTC_HT /* HT operation */ 554 | IEEE80211_HTC_AMPDU /* tx A-MPDU */ 555 | IEEE80211_HTC_AMSDU /* tx A-MSDU */ 556 ; 557 558 /* Set HT capabilities. */ 559 ic->ic_htcaps = 560 #if IWN_RBUF_SIZE == 8192 561 IEEE80211_HTCAP_AMSDU7935 | 562 #endif 563 IEEE80211_HTCAP_SMPS_DIS | 564 IEEE80211_HTCAP_CBW20_40 | 565 IEEE80211_HTCAP_SGI20 | 566 IEEE80211_HTCAP_SGI40; 567 if (sc->hw_type != IWN_HW_REV_TYPE_4965) 568 ic->ic_htcaps |= IEEE80211_HTCAP_GF; 569 #endif 570 571 /* Read MAC address, channels, etc from EEPROM. */ 572 error = iwn_read_eeprom(sc, macaddr); 573 if (error != 0) { 574 device_printf(dev, "could not read EEPROM, error %d\n", 575 error); 576 goto fail; 577 } 578 579 device_printf(sc->sc_dev, "MIMO %dT%dR, %.4s, address %6D\n", 580 sc->ntxchains, sc->nrxchains, sc->eeprom_domain, 581 macaddr, ":"); 582 583 #if 0 /* HT */ 584 /* Set supported HT rates. */ 585 ic->ic_sup_mcs[0] = 0xff; 586 if (sc->nrxchains > 1) 587 ic->ic_sup_mcs[1] = 0xff; 588 if (sc->nrxchains > 2) 589 ic->ic_sup_mcs[2] = 0xff; 590 #endif 591 592 if_initname(ifp, device_get_name(dev), device_get_unit(dev)); 593 ifp->if_softc = sc; 594 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 595 ifp->if_init = iwn_init; 596 ifp->if_ioctl = iwn_ioctl; 597 ifp->if_start = iwn_start; 598 IFQ_SET_MAXLEN(&ifp->if_snd, IFQ_MAXLEN); 599 ifp->if_snd.ifq_drv_maxlen = IFQ_MAXLEN; 600 IFQ_SET_READY(&ifp->if_snd); 601 602 ieee80211_ifattach(ic, macaddr); 603 ic->ic_vap_create = iwn_vap_create; 604 ic->ic_vap_delete = iwn_vap_delete; 605 ic->ic_raw_xmit = iwn_raw_xmit; 606 ic->ic_node_alloc = iwn_node_alloc; 607 ic->ic_newassoc = iwn_newassoc; 608 ic->ic_wme.wme_update = iwn_wme_update; 609 ic->ic_update_mcast = iwn_update_mcast; 610 ic->ic_scan_start = iwn_scan_start; 611 ic->ic_scan_end = iwn_scan_end; 612 ic->ic_set_channel = iwn_set_channel; 613 ic->ic_scan_curchan = iwn_scan_curchan; 614 ic->ic_scan_mindwell = iwn_scan_mindwell; 615 ic->ic_setregdomain = iwn_setregdomain; 616 #if 0 /* HT */ 617 ic->ic_ampdu_rx_start = iwn_ampdu_rx_start; 618 ic->ic_ampdu_rx_stop = iwn_ampdu_rx_stop; 619 ic->ic_ampdu_tx_start = iwn_ampdu_tx_start; 620 ic->ic_ampdu_tx_stop = iwn_ampdu_tx_stop; 621 #endif 622 623 iwn_radiotap_attach(sc); 624 iwn_sysctlattach(sc); 625 626 /* 627 * Hook our interrupt after all initialization is complete. 628 */ 629 error = bus_setup_intr(dev, sc->irq, INTR_TYPE_NET | INTR_MPSAFE, 630 NULL, iwn_intr, sc, &sc->sc_ih); 631 if (error != 0) { 632 device_printf(dev, "could not set up interrupt, error %d\n", 633 error); 634 goto fail; 635 } 636 637 ieee80211_announce(ic); 638 return 0; 639 fail: 640 iwn_cleanup(dev); 641 return error; 642 } 643 644 const struct iwn_hal * 645 iwn_hal_attach(struct iwn_softc *sc) 646 { 647 sc->hw_type = (IWN_READ(sc, IWN_HW_REV) >> 4) & 0xf; 648 649 switch (sc->hw_type) { 650 case IWN_HW_REV_TYPE_4965: 651 sc->sc_hal = &iwn4965_hal; 652 sc->limits = &iwn4965_sensitivity_limits; 653 sc->fwname = "iwn4965fw"; 654 sc->txchainmask = IWN_ANT_AB; 655 sc->rxchainmask = IWN_ANT_ABC; 656 break; 657 case IWN_HW_REV_TYPE_5100: 658 sc->sc_hal = &iwn5000_hal; 659 sc->limits = &iwn5000_sensitivity_limits; 660 sc->fwname = "iwn5000fw"; 661 sc->txchainmask = IWN_ANT_B; 662 sc->rxchainmask = IWN_ANT_AB; 663 break; 664 case IWN_HW_REV_TYPE_5150: 665 sc->sc_hal = &iwn5000_hal; 666 sc->limits = &iwn5150_sensitivity_limits; 667 sc->fwname = "iwn5150fw"; 668 sc->txchainmask = IWN_ANT_A; 669 sc->rxchainmask = IWN_ANT_AB; 670 break; 671 case IWN_HW_REV_TYPE_5300: 672 case IWN_HW_REV_TYPE_5350: 673 sc->sc_hal = &iwn5000_hal; 674 sc->limits = &iwn5000_sensitivity_limits; 675 sc->fwname = "iwn5000fw"; 676 sc->txchainmask = IWN_ANT_ABC; 677 sc->rxchainmask = IWN_ANT_ABC; 678 break; 679 case IWN_HW_REV_TYPE_1000: 680 sc->sc_hal = &iwn5000_hal; 681 sc->limits = &iwn5000_sensitivity_limits; 682 sc->fwname = "iwn1000fw"; 683 sc->txchainmask = IWN_ANT_A; 684 sc->rxchainmask = IWN_ANT_AB; 685 break; 686 case IWN_HW_REV_TYPE_6000: 687 sc->sc_hal = &iwn5000_hal; 688 sc->limits = &iwn6000_sensitivity_limits; 689 sc->fwname = "iwn6000fw"; 690 switch (pci_get_device(sc->sc_dev)) { 691 case 0x422C: 692 case 0x4239: 693 sc->sc_flags |= IWN_FLAG_INTERNAL_PA; 694 sc->txchainmask = IWN_ANT_BC; 695 sc->rxchainmask = IWN_ANT_BC; 696 break; 697 default: 698 sc->txchainmask = IWN_ANT_ABC; 699 sc->rxchainmask = IWN_ANT_ABC; 700 break; 701 } 702 break; 703 case IWN_HW_REV_TYPE_6050: 704 sc->sc_hal = &iwn5000_hal; 705 sc->limits = &iwn6000_sensitivity_limits; 706 sc->fwname = "iwn6000fw"; 707 sc->txchainmask = IWN_ANT_AB; 708 sc->rxchainmask = IWN_ANT_AB; 709 break; 710 default: 711 device_printf(sc->sc_dev, "adapter type %d not supported\n", 712 sc->hw_type); 713 return NULL; 714 } 715 return sc->sc_hal; 716 } 717 718 /* 719 * Attach the interface to 802.11 radiotap. 720 */ 721 void 722 iwn_radiotap_attach(struct iwn_softc *sc) 723 { 724 struct ifnet *ifp = sc->sc_ifp; 725 struct ieee80211com *ic = ifp->if_l2com; 726 727 ieee80211_radiotap_attach(ic, 728 &sc->sc_txtap.wt_ihdr, sizeof(sc->sc_txtap), 729 IWN_TX_RADIOTAP_PRESENT, 730 &sc->sc_rxtap.wr_ihdr, sizeof(sc->sc_rxtap), 731 IWN_RX_RADIOTAP_PRESENT); 732 } 733 734 static struct ieee80211vap * 735 iwn_vap_create(struct ieee80211com *ic, 736 const char name[IFNAMSIZ], int unit, int opmode, int flags, 737 const uint8_t bssid[IEEE80211_ADDR_LEN], 738 const uint8_t mac[IEEE80211_ADDR_LEN]) 739 { 740 struct iwn_vap *ivp; 741 struct ieee80211vap *vap; 742 743 if (!TAILQ_EMPTY(&ic->ic_vaps)) /* only one at a time */ 744 return NULL; 745 ivp = (struct iwn_vap *) malloc(sizeof(struct iwn_vap), 746 M_80211_VAP, M_NOWAIT | M_ZERO); 747 if (ivp == NULL) 748 return NULL; 749 vap = &ivp->iv_vap; 750 ieee80211_vap_setup(ic, vap, name, unit, opmode, flags, bssid, mac); 751 vap->iv_bmissthreshold = 10; /* override default */ 752 /* Override with driver methods. */ 753 ivp->iv_newstate = vap->iv_newstate; 754 vap->iv_newstate = iwn_newstate; 755 756 ieee80211_amrr_init(&ivp->iv_amrr, vap, 757 IEEE80211_AMRR_MIN_SUCCESS_THRESHOLD, 758 IEEE80211_AMRR_MAX_SUCCESS_THRESHOLD, 759 500 /* ms */); 760 761 /* Complete setup. */ 762 ieee80211_vap_attach(vap, ieee80211_media_change, 763 ieee80211_media_status); 764 ic->ic_opmode = opmode; 765 return vap; 766 } 767 768 static void 769 iwn_vap_delete(struct ieee80211vap *vap) 770 { 771 struct iwn_vap *ivp = IWN_VAP(vap); 772 773 ieee80211_amrr_cleanup(&ivp->iv_amrr); 774 ieee80211_vap_detach(vap); 775 free(ivp, M_80211_VAP); 776 } 777 778 int 779 iwn_cleanup(device_t dev) 780 { 781 struct iwn_softc *sc = device_get_softc(dev); 782 struct ifnet *ifp = sc->sc_ifp; 783 struct ieee80211com *ic; 784 int i; 785 786 if (ifp != NULL) { 787 ic = ifp->if_l2com; 788 789 ieee80211_draintask(ic, &sc->sc_reinit_task); 790 ieee80211_draintask(ic, &sc->sc_radioon_task); 791 ieee80211_draintask(ic, &sc->sc_radiooff_task); 792 793 iwn_stop(sc); 794 callout_drain(&sc->sc_timer_to); 795 ieee80211_ifdetach(ic); 796 } 797 798 /* Free DMA resources. */ 799 iwn_free_rx_ring(sc, &sc->rxq); 800 if (sc->sc_hal != NULL) 801 for (i = 0; i < sc->sc_hal->ntxqs; i++) 802 iwn_free_tx_ring(sc, &sc->txq[i]); 803 iwn_free_sched(sc); 804 iwn_free_kw(sc); 805 if (sc->ict != NULL) 806 iwn_free_ict(sc); 807 iwn_free_fwmem(sc); 808 809 if (sc->irq != NULL) { 810 bus_teardown_intr(dev, sc->irq, sc->sc_ih); 811 bus_release_resource(dev, SYS_RES_IRQ, sc->irq_rid, sc->irq); 812 if (sc->irq_rid == 1) 813 pci_release_msi(dev); 814 } 815 816 if (sc->mem != NULL) 817 bus_release_resource(dev, SYS_RES_MEMORY, sc->mem_rid, sc->mem); 818 819 if (ifp != NULL) 820 if_free(ifp); 821 822 IWN_LOCK_DESTROY(sc); 823 return 0; 824 } 825 826 static int 827 iwn_detach(device_t dev) 828 { 829 iwn_cleanup(dev); 830 return 0; 831 } 832 833 int 834 iwn_nic_lock(struct iwn_softc *sc) 835 { 836 int ntries; 837 838 /* Request exclusive access to NIC. */ 839 IWN_SETBITS(sc, IWN_GP_CNTRL, IWN_GP_CNTRL_MAC_ACCESS_REQ); 840 841 /* Spin until we actually get the lock. */ 842 for (ntries = 0; ntries < 1000; ntries++) { 843 if ((IWN_READ(sc, IWN_GP_CNTRL) & 844 (IWN_GP_CNTRL_MAC_ACCESS_ENA | IWN_GP_CNTRL_SLEEP)) == 845 IWN_GP_CNTRL_MAC_ACCESS_ENA) 846 return 0; 847 DELAY(10); 848 } 849 return ETIMEDOUT; 850 } 851 852 static __inline void 853 iwn_nic_unlock(struct iwn_softc *sc) 854 { 855 IWN_CLRBITS(sc, IWN_GP_CNTRL, IWN_GP_CNTRL_MAC_ACCESS_REQ); 856 } 857 858 static __inline uint32_t 859 iwn_prph_read(struct iwn_softc *sc, uint32_t addr) 860 { 861 IWN_WRITE(sc, IWN_PRPH_RADDR, IWN_PRPH_DWORD | addr); 862 IWN_BARRIER_READ_WRITE(sc); 863 return IWN_READ(sc, IWN_PRPH_RDATA); 864 } 865 866 static __inline void 867 iwn_prph_write(struct iwn_softc *sc, uint32_t addr, uint32_t data) 868 { 869 IWN_WRITE(sc, IWN_PRPH_WADDR, IWN_PRPH_DWORD | addr); 870 IWN_BARRIER_WRITE(sc); 871 IWN_WRITE(sc, IWN_PRPH_WDATA, data); 872 } 873 874 static __inline void 875 iwn_prph_setbits(struct iwn_softc *sc, uint32_t addr, uint32_t mask) 876 { 877 iwn_prph_write(sc, addr, iwn_prph_read(sc, addr) | mask); 878 } 879 880 static __inline void 881 iwn_prph_clrbits(struct iwn_softc *sc, uint32_t addr, uint32_t mask) 882 { 883 iwn_prph_write(sc, addr, iwn_prph_read(sc, addr) & ~mask); 884 } 885 886 static __inline void 887 iwn_prph_write_region_4(struct iwn_softc *sc, uint32_t addr, 888 const uint32_t *data, int count) 889 { 890 for (; count > 0; count--, data++, addr += 4) 891 iwn_prph_write(sc, addr, *data); 892 } 893 894 static __inline uint32_t 895 iwn_mem_read(struct iwn_softc *sc, uint32_t addr) 896 { 897 IWN_WRITE(sc, IWN_MEM_RADDR, addr); 898 IWN_BARRIER_READ_WRITE(sc); 899 return IWN_READ(sc, IWN_MEM_RDATA); 900 } 901 902 static __inline void 903 iwn_mem_write(struct iwn_softc *sc, uint32_t addr, uint32_t data) 904 { 905 IWN_WRITE(sc, IWN_MEM_WADDR, addr); 906 IWN_BARRIER_WRITE(sc); 907 IWN_WRITE(sc, IWN_MEM_WDATA, data); 908 } 909 910 static __inline void 911 iwn_mem_write_2(struct iwn_softc *sc, uint32_t addr, uint16_t data) 912 { 913 uint32_t tmp; 914 915 tmp = iwn_mem_read(sc, addr & ~3); 916 if (addr & 3) 917 tmp = (tmp & 0x0000ffff) | data << 16; 918 else 919 tmp = (tmp & 0xffff0000) | data; 920 iwn_mem_write(sc, addr & ~3, tmp); 921 } 922 923 static __inline void 924 iwn_mem_read_region_4(struct iwn_softc *sc, uint32_t addr, uint32_t *data, 925 int count) 926 { 927 for (; count > 0; count--, addr += 4) 928 *data++ = iwn_mem_read(sc, addr); 929 } 930 931 static __inline void 932 iwn_mem_set_region_4(struct iwn_softc *sc, uint32_t addr, uint32_t val, 933 int count) 934 { 935 for (; count > 0; count--, addr += 4) 936 iwn_mem_write(sc, addr, val); 937 } 938 939 int 940 iwn_eeprom_lock(struct iwn_softc *sc) 941 { 942 int i, ntries; 943 944 for (i = 0; i < 100; i++) { 945 /* Request exclusive access to EEPROM. */ 946 IWN_SETBITS(sc, IWN_HW_IF_CONFIG, 947 IWN_HW_IF_CONFIG_EEPROM_LOCKED); 948 949 /* Spin until we actually get the lock. */ 950 for (ntries = 0; ntries < 100; ntries++) { 951 if (IWN_READ(sc, IWN_HW_IF_CONFIG) & 952 IWN_HW_IF_CONFIG_EEPROM_LOCKED) 953 return 0; 954 DELAY(10); 955 } 956 } 957 return ETIMEDOUT; 958 } 959 960 static __inline void 961 iwn_eeprom_unlock(struct iwn_softc *sc) 962 { 963 IWN_CLRBITS(sc, IWN_HW_IF_CONFIG, IWN_HW_IF_CONFIG_EEPROM_LOCKED); 964 } 965 966 /* 967 * Initialize access by host to One Time Programmable ROM. 968 * NB: This kind of ROM can be found on 1000 or 6000 Series only. 969 */ 970 int 971 iwn_init_otprom(struct iwn_softc *sc) 972 { 973 uint32_t base; 974 uint16_t next; 975 int count, error; 976 977 /* Wait for clock stabilization before accessing prph. */ 978 error = iwn_clock_wait(sc); 979 if (error != 0) 980 return error; 981 982 error = iwn_nic_lock(sc); 983 if (error != 0) 984 return error; 985 iwn_prph_setbits(sc, IWN_APMG_PS, IWN_APMG_PS_RESET_REQ); 986 DELAY(5); 987 iwn_prph_clrbits(sc, IWN_APMG_PS, IWN_APMG_PS_RESET_REQ); 988 iwn_nic_unlock(sc); 989 990 /* Set auto clock gate disable bit for HW with OTP shadow RAM. */ 991 if (sc->hw_type != IWN_HW_REV_TYPE_1000) { 992 IWN_SETBITS(sc, IWN_DBG_LINK_PWR_MGMT, 993 IWN_RESET_LINK_PWR_MGMT_DIS); 994 } 995 IWN_CLRBITS(sc, IWN_EEPROM_GP, IWN_EEPROM_GP_IF_OWNER); 996 /* Clear ECC status. */ 997 IWN_SETBITS(sc, IWN_OTP_GP, 998 IWN_OTP_GP_ECC_CORR_STTS | IWN_OTP_GP_ECC_UNCORR_STTS); 999 1000 /* 1001 * Find last valid OTP block (contains the EEPROM image) for HW 1002 * without OTP shadow RAM. 1003 */ 1004 if (sc->hw_type == IWN_HW_REV_TYPE_1000) { 1005 /* Switch to absolute addressing mode. */ 1006 IWN_CLRBITS(sc, IWN_OTP_GP, IWN_OTP_GP_RELATIVE_ACCESS); 1007 base = 0; 1008 for (count = 0; count < IWN1000_OTP_NBLOCKS; count++) { 1009 error = iwn_read_prom_data(sc, base, &next, 2); 1010 if (error != 0) 1011 return error; 1012 if (next == 0) /* End of linked-list. */ 1013 break; 1014 base = le16toh(next); 1015 } 1016 if (base == 0 || count == IWN1000_OTP_NBLOCKS) 1017 return EIO; 1018 /* Skip "next" word. */ 1019 sc->prom_base = base + 1; 1020 } 1021 return 0; 1022 } 1023 1024 int 1025 iwn_read_prom_data(struct iwn_softc *sc, uint32_t addr, void *data, int count) 1026 { 1027 uint32_t val, tmp; 1028 int ntries; 1029 uint8_t *out = data; 1030 1031 addr += sc->prom_base; 1032 for (; count > 0; count -= 2, addr++) { 1033 IWN_WRITE(sc, IWN_EEPROM, addr << 2); 1034 for (ntries = 0; ntries < 10; ntries++) { 1035 val = IWN_READ(sc, IWN_EEPROM); 1036 if (val & IWN_EEPROM_READ_VALID) 1037 break; 1038 DELAY(5); 1039 } 1040 if (ntries == 10) { 1041 device_printf(sc->sc_dev, 1042 "timeout reading ROM at 0x%x\n", addr); 1043 return ETIMEDOUT; 1044 } 1045 if (sc->sc_flags & IWN_FLAG_HAS_OTPROM) { 1046 /* OTPROM, check for ECC errors. */ 1047 tmp = IWN_READ(sc, IWN_OTP_GP); 1048 if (tmp & IWN_OTP_GP_ECC_UNCORR_STTS) { 1049 device_printf(sc->sc_dev, 1050 "OTPROM ECC error at 0x%x\n", addr); 1051 return EIO; 1052 } 1053 if (tmp & IWN_OTP_GP_ECC_CORR_STTS) { 1054 /* Correctable ECC error, clear bit. */ 1055 IWN_SETBITS(sc, IWN_OTP_GP, 1056 IWN_OTP_GP_ECC_CORR_STTS); 1057 } 1058 } 1059 *out++ = val >> 16; 1060 if (count > 1) 1061 *out++ = val >> 24; 1062 } 1063 return 0; 1064 } 1065 1066 static void 1067 iwn_dma_map_addr(void *arg, bus_dma_segment_t *segs, int nsegs, int error) 1068 { 1069 if (error != 0) 1070 return; 1071 KASSERT(nsegs == 1, ("too many DMA segments, %d should be 1", nsegs)); 1072 *(bus_addr_t *)arg = segs[0].ds_addr; 1073 } 1074 1075 static int 1076 iwn_dma_contig_alloc(struct iwn_softc *sc, struct iwn_dma_info *dma, 1077 void **kvap, bus_size_t size, bus_size_t alignment, int flags) 1078 { 1079 int error; 1080 1081 dma->size = size; 1082 dma->tag = NULL; 1083 1084 error = bus_dma_tag_create(bus_get_dma_tag(sc->sc_dev), alignment, 1085 0, BUS_SPACE_MAXADDR_32BIT, BUS_SPACE_MAXADDR, NULL, NULL, size, 1086 1, size, flags, NULL, NULL, &dma->tag); 1087 if (error != 0) { 1088 device_printf(sc->sc_dev, 1089 "%s: bus_dma_tag_create failed, error %d\n", 1090 __func__, error); 1091 goto fail; 1092 } 1093 error = bus_dmamem_alloc(dma->tag, (void **)&dma->vaddr, 1094 flags | BUS_DMA_ZERO, &dma->map); 1095 if (error != 0) { 1096 device_printf(sc->sc_dev, 1097 "%s: bus_dmamem_alloc failed, error %d\n", 1098 __func__, error); 1099 goto fail; 1100 } 1101 error = bus_dmamap_load(dma->tag, dma->map, dma->vaddr, 1102 size, iwn_dma_map_addr, &dma->paddr, flags); 1103 if (error != 0) { 1104 device_printf(sc->sc_dev, 1105 "%s: bus_dmamap_load failed, error %d\n", __func__, error); 1106 goto fail; 1107 } 1108 1109 if (kvap != NULL) 1110 *kvap = dma->vaddr; 1111 return 0; 1112 fail: 1113 iwn_dma_contig_free(dma); 1114 return error; 1115 } 1116 1117 void 1118 iwn_dma_contig_free(struct iwn_dma_info *dma) 1119 { 1120 if (dma->tag != NULL) { 1121 if (dma->map != NULL) { 1122 if (dma->paddr == 0) { 1123 bus_dmamap_sync(dma->tag, dma->map, 1124 BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE); 1125 bus_dmamap_unload(dma->tag, dma->map); 1126 } 1127 bus_dmamem_free(dma->tag, &dma->vaddr, dma->map); 1128 } 1129 bus_dma_tag_destroy(dma->tag); 1130 } 1131 } 1132 1133 int 1134 iwn_alloc_sched(struct iwn_softc *sc) 1135 { 1136 /* TX scheduler rings must be aligned on a 1KB boundary. */ 1137 return iwn_dma_contig_alloc(sc, &sc->sched_dma, 1138 (void **)&sc->sched, sc->sc_hal->schedsz, 1024, BUS_DMA_NOWAIT); 1139 } 1140 1141 void 1142 iwn_free_sched(struct iwn_softc *sc) 1143 { 1144 iwn_dma_contig_free(&sc->sched_dma); 1145 } 1146 1147 int 1148 iwn_alloc_kw(struct iwn_softc *sc) 1149 { 1150 /* "Keep Warm" page must be aligned on a 4KB boundary. */ 1151 return iwn_dma_contig_alloc(sc, &sc->kw_dma, NULL, 4096, 4096, 1152 BUS_DMA_NOWAIT); 1153 } 1154 1155 void 1156 iwn_free_kw(struct iwn_softc *sc) 1157 { 1158 iwn_dma_contig_free(&sc->kw_dma); 1159 } 1160 1161 int 1162 iwn_alloc_ict(struct iwn_softc *sc) 1163 { 1164 /* ICT table must be aligned on a 4KB boundary. */ 1165 return iwn_dma_contig_alloc(sc, &sc->ict_dma, 1166 (void **)&sc->ict, IWN_ICT_SIZE, 4096, BUS_DMA_NOWAIT); 1167 } 1168 1169 void 1170 iwn_free_ict(struct iwn_softc *sc) 1171 { 1172 iwn_dma_contig_free(&sc->ict_dma); 1173 } 1174 1175 int 1176 iwn_alloc_fwmem(struct iwn_softc *sc) 1177 { 1178 /* Must be aligned on a 16-byte boundary. */ 1179 return iwn_dma_contig_alloc(sc, &sc->fw_dma, NULL, 1180 sc->sc_hal->fwsz, 16, BUS_DMA_NOWAIT); 1181 } 1182 1183 void 1184 iwn_free_fwmem(struct iwn_softc *sc) 1185 { 1186 iwn_dma_contig_free(&sc->fw_dma); 1187 } 1188 1189 int 1190 iwn_alloc_rx_ring(struct iwn_softc *sc, struct iwn_rx_ring *ring) 1191 { 1192 bus_size_t size; 1193 int i, error; 1194 1195 ring->cur = 0; 1196 1197 /* Allocate RX descriptors (256-byte aligned). */ 1198 size = IWN_RX_RING_COUNT * sizeof (uint32_t); 1199 error = iwn_dma_contig_alloc(sc, &ring->desc_dma, 1200 (void **)&ring->desc, size, 256, BUS_DMA_NOWAIT); 1201 if (error != 0) { 1202 device_printf(sc->sc_dev, 1203 "%s: could not allocate Rx ring DMA memory, error %d\n", 1204 __func__, error); 1205 goto fail; 1206 } 1207 1208 error = bus_dma_tag_create(bus_get_dma_tag(sc->sc_dev), 1, 0, 1209 BUS_SPACE_MAXADDR_32BIT, 1210 BUS_SPACE_MAXADDR, NULL, NULL, MJUMPAGESIZE, 1, 1211 MJUMPAGESIZE, BUS_DMA_NOWAIT, NULL, NULL, &ring->data_dmat); 1212 if (error != 0) { 1213 device_printf(sc->sc_dev, 1214 "%s: bus_dma_tag_create_failed, error %d\n", 1215 __func__, error); 1216 goto fail; 1217 } 1218 1219 /* Allocate RX status area (16-byte aligned). */ 1220 error = iwn_dma_contig_alloc(sc, &ring->stat_dma, 1221 (void **)&ring->stat, sizeof (struct iwn_rx_status), 1222 16, BUS_DMA_NOWAIT); 1223 if (error != 0) { 1224 device_printf(sc->sc_dev, 1225 "%s: could not allocate Rx status DMA memory, error %d\n", 1226 __func__, error); 1227 goto fail; 1228 } 1229 1230 /* 1231 * Allocate and map RX buffers. 1232 */ 1233 for (i = 0; i < IWN_RX_RING_COUNT; i++) { 1234 struct iwn_rx_data *data = &ring->data[i]; 1235 bus_addr_t paddr; 1236 1237 error = bus_dmamap_create(ring->data_dmat, 0, &data->map); 1238 if (error != 0) { 1239 device_printf(sc->sc_dev, 1240 "%s: bus_dmamap_create failed, error %d\n", 1241 __func__, error); 1242 goto fail; 1243 } 1244 1245 data->m = m_getjcl(M_DONTWAIT, MT_DATA, M_PKTHDR, MJUMPAGESIZE); 1246 if (data->m == NULL) { 1247 device_printf(sc->sc_dev, 1248 "%s: could not allocate rx mbuf\n", __func__); 1249 error = ENOMEM; 1250 goto fail; 1251 } 1252 1253 /* Map page. */ 1254 error = bus_dmamap_load(ring->data_dmat, data->map, 1255 mtod(data->m, caddr_t), MJUMPAGESIZE, 1256 iwn_dma_map_addr, &paddr, BUS_DMA_NOWAIT); 1257 if (error != 0 && error != EFBIG) { 1258 device_printf(sc->sc_dev, 1259 "%s: bus_dmamap_load failed, error %d\n", 1260 __func__, error); 1261 m_freem(data->m); 1262 error = ENOMEM; /* XXX unique code */ 1263 goto fail; 1264 } 1265 bus_dmamap_sync(ring->data_dmat, data->map, 1266 BUS_DMASYNC_PREWRITE); 1267 1268 /* Set physical address of RX buffer (256-byte aligned). */ 1269 ring->desc[i] = htole32(paddr >> 8); 1270 } 1271 bus_dmamap_sync(ring->desc_dma.tag, ring->desc_dma.map, 1272 BUS_DMASYNC_PREWRITE); 1273 return 0; 1274 fail: 1275 iwn_free_rx_ring(sc, ring); 1276 return error; 1277 } 1278 1279 void 1280 iwn_reset_rx_ring(struct iwn_softc *sc, struct iwn_rx_ring *ring) 1281 { 1282 int ntries; 1283 1284 if (iwn_nic_lock(sc) == 0) { 1285 IWN_WRITE(sc, IWN_FH_RX_CONFIG, 0); 1286 for (ntries = 0; ntries < 1000; ntries++) { 1287 if (IWN_READ(sc, IWN_FH_RX_STATUS) & 1288 IWN_FH_RX_STATUS_IDLE) 1289 break; 1290 DELAY(10); 1291 } 1292 iwn_nic_unlock(sc); 1293 #ifdef IWN_DEBUG 1294 if (ntries == 1000) 1295 DPRINTF(sc, IWN_DEBUG_ANY, "%s\n", 1296 "timeout resetting Rx ring"); 1297 #endif 1298 } 1299 ring->cur = 0; 1300 sc->last_rx_valid = 0; 1301 } 1302 1303 void 1304 iwn_free_rx_ring(struct iwn_softc *sc, struct iwn_rx_ring *ring) 1305 { 1306 int i; 1307 1308 iwn_dma_contig_free(&ring->desc_dma); 1309 iwn_dma_contig_free(&ring->stat_dma); 1310 1311 for (i = 0; i < IWN_RX_RING_COUNT; i++) { 1312 struct iwn_rx_data *data = &ring->data[i]; 1313 1314 if (data->m != NULL) { 1315 bus_dmamap_sync(ring->data_dmat, data->map, 1316 BUS_DMASYNC_POSTREAD); 1317 bus_dmamap_unload(ring->data_dmat, data->map); 1318 m_freem(data->m); 1319 } 1320 if (data->map != NULL) 1321 bus_dmamap_destroy(ring->data_dmat, data->map); 1322 } 1323 } 1324 1325 int 1326 iwn_alloc_tx_ring(struct iwn_softc *sc, struct iwn_tx_ring *ring, int qid) 1327 { 1328 bus_size_t size; 1329 bus_addr_t paddr; 1330 int i, error; 1331 1332 ring->qid = qid; 1333 ring->queued = 0; 1334 ring->cur = 0; 1335 1336 /* Allocate TX descriptors (256-byte aligned.) */ 1337 size = IWN_TX_RING_COUNT * sizeof(struct iwn_tx_desc); 1338 error = iwn_dma_contig_alloc(sc, &ring->desc_dma, 1339 (void **)&ring->desc, size, 256, BUS_DMA_NOWAIT); 1340 if (error != 0) { 1341 device_printf(sc->sc_dev, 1342 "%s: could not allocate TX ring DMA memory, error %d\n", 1343 __func__, error); 1344 goto fail; 1345 } 1346 1347 /* 1348 * We only use rings 0 through 4 (4 EDCA + cmd) so there is no need 1349 * to allocate commands space for other rings. 1350 */ 1351 if (qid > 4) 1352 return 0; 1353 1354 size = IWN_TX_RING_COUNT * sizeof(struct iwn_tx_cmd); 1355 error = iwn_dma_contig_alloc(sc, &ring->cmd_dma, 1356 (void **)&ring->cmd, size, 4, BUS_DMA_NOWAIT); 1357 if (error != 0) { 1358 device_printf(sc->sc_dev, 1359 "%s: could not allocate TX cmd DMA memory, error %d\n", 1360 __func__, error); 1361 goto fail; 1362 } 1363 1364 error = bus_dma_tag_create(bus_get_dma_tag(sc->sc_dev), 1, 0, 1365 BUS_SPACE_MAXADDR_32BIT, 1366 BUS_SPACE_MAXADDR, NULL, NULL, MCLBYTES, IWN_MAX_SCATTER - 1, 1367 MCLBYTES, BUS_DMA_NOWAIT, NULL, NULL, &ring->data_dmat); 1368 if (error != 0) { 1369 device_printf(sc->sc_dev, 1370 "%s: bus_dma_tag_create_failed, error %d\n", 1371 __func__, error); 1372 goto fail; 1373 } 1374 1375 paddr = ring->cmd_dma.paddr; 1376 for (i = 0; i < IWN_TX_RING_COUNT; i++) { 1377 struct iwn_tx_data *data = &ring->data[i]; 1378 1379 data->cmd_paddr = paddr; 1380 data->scratch_paddr = paddr + 12; 1381 paddr += sizeof (struct iwn_tx_cmd); 1382 1383 error = bus_dmamap_create(ring->data_dmat, 0, &data->map); 1384 if (error != 0) { 1385 device_printf(sc->sc_dev, 1386 "%s: bus_dmamap_create failed, error %d\n", 1387 __func__, error); 1388 goto fail; 1389 } 1390 bus_dmamap_sync(ring->data_dmat, data->map, 1391 BUS_DMASYNC_PREWRITE); 1392 } 1393 return 0; 1394 fail: 1395 iwn_free_tx_ring(sc, ring); 1396 return error; 1397 } 1398 1399 void 1400 iwn_reset_tx_ring(struct iwn_softc *sc, struct iwn_tx_ring *ring) 1401 { 1402 int i; 1403 1404 for (i = 0; i < IWN_TX_RING_COUNT; i++) { 1405 struct iwn_tx_data *data = &ring->data[i]; 1406 1407 if (data->m != NULL) { 1408 bus_dmamap_unload(ring->data_dmat, data->map); 1409 m_freem(data->m); 1410 data->m = NULL; 1411 } 1412 } 1413 /* Clear TX descriptors. */ 1414 memset(ring->desc, 0, ring->desc_dma.size); 1415 bus_dmamap_sync(ring->desc_dma.tag, ring->desc_dma.map, 1416 BUS_DMASYNC_PREWRITE); 1417 sc->qfullmsk &= ~(1 << ring->qid); 1418 ring->queued = 0; 1419 ring->cur = 0; 1420 } 1421 1422 void 1423 iwn_free_tx_ring(struct iwn_softc *sc, struct iwn_tx_ring *ring) 1424 { 1425 int i; 1426 1427 iwn_dma_contig_free(&ring->desc_dma); 1428 iwn_dma_contig_free(&ring->cmd_dma); 1429 1430 for (i = 0; i < IWN_TX_RING_COUNT; i++) { 1431 struct iwn_tx_data *data = &ring->data[i]; 1432 1433 if (data->m != NULL) { 1434 bus_dmamap_sync(ring->data_dmat, data->map, 1435 BUS_DMASYNC_POSTWRITE); 1436 bus_dmamap_unload(ring->data_dmat, data->map); 1437 m_freem(data->m); 1438 } 1439 if (data->map != NULL) 1440 bus_dmamap_destroy(ring->data_dmat, data->map); 1441 } 1442 } 1443 1444 void 1445 iwn5000_ict_reset(struct iwn_softc *sc) 1446 { 1447 /* Disable interrupts. */ 1448 IWN_WRITE(sc, IWN_INT_MASK, 0); 1449 1450 /* Reset ICT table. */ 1451 memset(sc->ict, 0, IWN_ICT_SIZE); 1452 sc->ict_cur = 0; 1453 1454 /* Set physical address of ICT table (4KB aligned.) */ 1455 DPRINTF(sc, IWN_DEBUG_RESET, "%s: enabling ICT\n", __func__); 1456 IWN_WRITE(sc, IWN_DRAM_INT_TBL, IWN_DRAM_INT_TBL_ENABLE | 1457 IWN_DRAM_INT_TBL_WRAP_CHECK | sc->ict_dma.paddr >> 12); 1458 1459 /* Enable periodic RX interrupt. */ 1460 sc->int_mask |= IWN_INT_RX_PERIODIC; 1461 /* Switch to ICT interrupt mode in driver. */ 1462 sc->sc_flags |= IWN_FLAG_USE_ICT; 1463 1464 /* Re-enable interrupts. */ 1465 IWN_WRITE(sc, IWN_INT, 0xffffffff); 1466 IWN_WRITE(sc, IWN_INT_MASK, sc->int_mask); 1467 } 1468 1469 int 1470 iwn_read_eeprom(struct iwn_softc *sc, uint8_t macaddr[IEEE80211_ADDR_LEN]) 1471 { 1472 const struct iwn_hal *hal = sc->sc_hal; 1473 int error; 1474 uint16_t val; 1475 1476 /* Check whether adapter has an EEPROM or an OTPROM. */ 1477 if (sc->hw_type >= IWN_HW_REV_TYPE_1000 && 1478 (IWN_READ(sc, IWN_OTP_GP) & IWN_OTP_GP_DEV_SEL_OTP)) 1479 sc->sc_flags |= IWN_FLAG_HAS_OTPROM; 1480 DPRINTF(sc, IWN_DEBUG_RESET, "%s found\n", 1481 (sc->sc_flags & IWN_FLAG_HAS_OTPROM) ? "OTPROM" : "EEPROM"); 1482 1483 /* Adapter has to be powered on for EEPROM access to work. */ 1484 error = iwn_apm_init(sc); 1485 if (error != 0) { 1486 device_printf(sc->sc_dev, 1487 "%s: could not power ON adapter, error %d\n", 1488 __func__, error); 1489 return error; 1490 } 1491 1492 if ((IWN_READ(sc, IWN_EEPROM_GP) & 0x7) == 0) { 1493 device_printf(sc->sc_dev, "%s: bad ROM signature\n", __func__); 1494 return EIO; 1495 } 1496 error = iwn_eeprom_lock(sc); 1497 if (error != 0) { 1498 device_printf(sc->sc_dev, 1499 "%s: could not lock ROM, error %d\n", 1500 __func__, error); 1501 return error; 1502 } 1503 1504 if (sc->sc_flags & IWN_FLAG_HAS_OTPROM) { 1505 error = iwn_init_otprom(sc); 1506 if (error != 0) { 1507 device_printf(sc->sc_dev, 1508 "%s: could not initialize OTPROM, error %d\n", 1509 __func__, error); 1510 return error; 1511 } 1512 } 1513 1514 iwn_read_prom_data(sc, IWN_EEPROM_RFCFG, &val, 2); 1515 sc->rfcfg = le16toh(val); 1516 DPRINTF(sc, IWN_DEBUG_RESET, "radio config=0x%04x\n", sc->rfcfg); 1517 1518 /* Read MAC address. */ 1519 iwn_read_prom_data(sc, IWN_EEPROM_MAC, macaddr, 6); 1520 1521 /* Read adapter-specific information from EEPROM. */ 1522 hal->read_eeprom(sc); 1523 1524 iwn_apm_stop(sc); /* Power OFF adapter. */ 1525 1526 iwn_eeprom_unlock(sc); 1527 return 0; 1528 } 1529 1530 void 1531 iwn4965_read_eeprom(struct iwn_softc *sc) 1532 { 1533 uint32_t addr; 1534 int i; 1535 uint16_t val; 1536 1537 /* Read regulatory domain (4 ASCII characters.) */ 1538 iwn_read_prom_data(sc, IWN4965_EEPROM_DOMAIN, sc->eeprom_domain, 4); 1539 1540 /* Read the list of authorized channels (20MHz ones only.) */ 1541 for (i = 0; i < 5; i++) { 1542 addr = iwn4965_regulatory_bands[i]; 1543 iwn_read_eeprom_channels(sc, i, addr); 1544 } 1545 1546 /* Read maximum allowed TX power for 2GHz and 5GHz bands. */ 1547 iwn_read_prom_data(sc, IWN4965_EEPROM_MAXPOW, &val, 2); 1548 sc->maxpwr2GHz = val & 0xff; 1549 sc->maxpwr5GHz = val >> 8; 1550 /* Check that EEPROM values are within valid range. */ 1551 if (sc->maxpwr5GHz < 20 || sc->maxpwr5GHz > 50) 1552 sc->maxpwr5GHz = 38; 1553 if (sc->maxpwr2GHz < 20 || sc->maxpwr2GHz > 50) 1554 sc->maxpwr2GHz = 38; 1555 DPRINTF(sc, IWN_DEBUG_RESET, "maxpwr 2GHz=%d 5GHz=%d\n", 1556 sc->maxpwr2GHz, sc->maxpwr5GHz); 1557 1558 /* Read samples for each TX power group. */ 1559 iwn_read_prom_data(sc, IWN4965_EEPROM_BANDS, sc->bands, 1560 sizeof sc->bands); 1561 1562 /* Read voltage at which samples were taken. */ 1563 iwn_read_prom_data(sc, IWN4965_EEPROM_VOLTAGE, &val, 2); 1564 sc->eeprom_voltage = (int16_t)le16toh(val); 1565 DPRINTF(sc, IWN_DEBUG_RESET, "voltage=%d (in 0.3V)\n", 1566 sc->eeprom_voltage); 1567 1568 #ifdef IWN_DEBUG 1569 /* Print samples. */ 1570 if (sc->sc_debug & IWN_DEBUG_ANY) { 1571 for (i = 0; i < IWN_NBANDS; i++) 1572 iwn4965_print_power_group(sc, i); 1573 } 1574 #endif 1575 } 1576 1577 #ifdef IWN_DEBUG 1578 void 1579 iwn4965_print_power_group(struct iwn_softc *sc, int i) 1580 { 1581 struct iwn4965_eeprom_band *band = &sc->bands[i]; 1582 struct iwn4965_eeprom_chan_samples *chans = band->chans; 1583 int j, c; 1584 1585 printf("===band %d===\n", i); 1586 printf("chan lo=%d, chan hi=%d\n", band->lo, band->hi); 1587 printf("chan1 num=%d\n", chans[0].num); 1588 for (c = 0; c < 2; c++) { 1589 for (j = 0; j < IWN_NSAMPLES; j++) { 1590 printf("chain %d, sample %d: temp=%d gain=%d " 1591 "power=%d pa_det=%d\n", c, j, 1592 chans[0].samples[c][j].temp, 1593 chans[0].samples[c][j].gain, 1594 chans[0].samples[c][j].power, 1595 chans[0].samples[c][j].pa_det); 1596 } 1597 } 1598 printf("chan2 num=%d\n", chans[1].num); 1599 for (c = 0; c < 2; c++) { 1600 for (j = 0; j < IWN_NSAMPLES; j++) { 1601 printf("chain %d, sample %d: temp=%d gain=%d " 1602 "power=%d pa_det=%d\n", c, j, 1603 chans[1].samples[c][j].temp, 1604 chans[1].samples[c][j].gain, 1605 chans[1].samples[c][j].power, 1606 chans[1].samples[c][j].pa_det); 1607 } 1608 } 1609 } 1610 #endif 1611 1612 void 1613 iwn5000_read_eeprom(struct iwn_softc *sc) 1614 { 1615 int32_t temp, volt; 1616 uint32_t addr, base; 1617 int i; 1618 uint16_t val; 1619 1620 /* Read regulatory domain (4 ASCII characters.) */ 1621 iwn_read_prom_data(sc, IWN5000_EEPROM_REG, &val, 2); 1622 base = le16toh(val); 1623 iwn_read_prom_data(sc, base + IWN5000_EEPROM_DOMAIN, 1624 sc->eeprom_domain, 4); 1625 1626 /* Read the list of authorized channels (20MHz ones only.) */ 1627 for (i = 0; i < 5; i++) { 1628 addr = base + iwn5000_regulatory_bands[i]; 1629 iwn_read_eeprom_channels(sc, i, addr); 1630 } 1631 1632 /* Read enhanced TX power information for 6000 Series. */ 1633 if (sc->hw_type >= IWN_HW_REV_TYPE_6000) 1634 iwn_read_eeprom_enhinfo(sc); 1635 1636 iwn_read_prom_data(sc, IWN5000_EEPROM_CAL, &val, 2); 1637 base = le16toh(val); 1638 if (sc->hw_type == IWN_HW_REV_TYPE_5150) { 1639 /* Compute temperature offset. */ 1640 iwn_read_prom_data(sc, base + IWN5000_EEPROM_TEMP, &val, 2); 1641 temp = le16toh(val); 1642 iwn_read_prom_data(sc, base + IWN5000_EEPROM_VOLT, &val, 2); 1643 volt = le16toh(val); 1644 sc->temp_off = temp - (volt / -5); 1645 DPRINTF(sc, IWN_DEBUG_CALIBRATE, "temp=%d volt=%d offset=%dK\n", 1646 temp, volt, sc->temp_off); 1647 } else { 1648 /* Read crystal calibration. */ 1649 iwn_read_prom_data(sc, base + IWN5000_EEPROM_CRYSTAL, 1650 &sc->eeprom_crystal, sizeof (uint32_t)); 1651 DPRINTF(sc, IWN_DEBUG_CALIBRATE, "crystal calibration 0x%08x\n", 1652 le32toh(sc->eeprom_crystal)); 1653 } 1654 } 1655 1656 /* 1657 * Translate EEPROM flags to net80211. 1658 */ 1659 static uint32_t 1660 iwn_eeprom_channel_flags(struct iwn_eeprom_chan *channel) 1661 { 1662 uint32_t nflags; 1663 1664 nflags = 0; 1665 if ((channel->flags & IWN_EEPROM_CHAN_ACTIVE) == 0) 1666 nflags |= IEEE80211_CHAN_PASSIVE; 1667 if ((channel->flags & IWN_EEPROM_CHAN_IBSS) == 0) 1668 nflags |= IEEE80211_CHAN_NOADHOC; 1669 if (channel->flags & IWN_EEPROM_CHAN_RADAR) { 1670 nflags |= IEEE80211_CHAN_DFS; 1671 /* XXX apparently IBSS may still be marked */ 1672 nflags |= IEEE80211_CHAN_NOADHOC; 1673 } 1674 1675 return nflags; 1676 } 1677 1678 static void 1679 iwn_read_eeprom_band(struct iwn_softc *sc, int n) 1680 { 1681 struct ifnet *ifp = sc->sc_ifp; 1682 struct ieee80211com *ic = ifp->if_l2com; 1683 struct iwn_eeprom_chan *channels = sc->eeprom_channels[n]; 1684 const struct iwn_chan_band *band = &iwn_bands[n]; 1685 struct ieee80211_channel *c; 1686 int i, chan, nflags; 1687 1688 for (i = 0; i < band->nchan; i++) { 1689 if (!(channels[i].flags & IWN_EEPROM_CHAN_VALID)) { 1690 DPRINTF(sc, IWN_DEBUG_RESET, 1691 "skip chan %d flags 0x%x maxpwr %d\n", 1692 band->chan[i], channels[i].flags, 1693 channels[i].maxpwr); 1694 continue; 1695 } 1696 chan = band->chan[i]; 1697 nflags = iwn_eeprom_channel_flags(&channels[i]); 1698 1699 DPRINTF(sc, IWN_DEBUG_RESET, 1700 "add chan %d flags 0x%x maxpwr %d\n", 1701 chan, channels[i].flags, channels[i].maxpwr); 1702 1703 c = &ic->ic_channels[ic->ic_nchans++]; 1704 c->ic_ieee = chan; 1705 c->ic_maxregpower = channels[i].maxpwr; 1706 c->ic_maxpower = 2*c->ic_maxregpower; 1707 if (n == 0) { /* 2GHz band */ 1708 c->ic_freq = ieee80211_ieee2mhz(chan, 1709 IEEE80211_CHAN_G); 1710 1711 /* G =>'s B is supported */ 1712 c->ic_flags = IEEE80211_CHAN_B | nflags; 1713 1714 c = &ic->ic_channels[ic->ic_nchans++]; 1715 c[0] = c[-1]; 1716 c->ic_flags = IEEE80211_CHAN_G | nflags; 1717 } else { /* 5GHz band */ 1718 c->ic_freq = ieee80211_ieee2mhz(chan, 1719 IEEE80211_CHAN_A); 1720 c->ic_flags = IEEE80211_CHAN_A | nflags; 1721 sc->sc_flags |= IWN_FLAG_HAS_5GHZ; 1722 } 1723 #if 0 /* HT */ 1724 /* XXX no constraints on using HT20 */ 1725 /* add HT20, HT40 added separately */ 1726 c = &ic->ic_channels[ic->ic_nchans++]; 1727 c[0] = c[-1]; 1728 c->ic_flags |= IEEE80211_CHAN_HT20; 1729 /* XXX NARROW =>'s 1/2 and 1/4 width? */ 1730 #endif 1731 } 1732 } 1733 1734 #if 0 /* HT */ 1735 static void 1736 iwn_read_eeprom_ht40(struct iwn_softc *sc, int n) 1737 { 1738 struct ifnet *ifp = sc->sc_ifp; 1739 struct ieee80211com *ic = ifp->if_l2com; 1740 struct iwn_eeprom_chan *channels = sc->eeprom_channels[n]; 1741 const struct iwn_chan_band *band = &iwn_bands[n]; 1742 struct ieee80211_channel *c, *cent, *extc; 1743 int i; 1744 1745 for (i = 0; i < band->nchan; i++) { 1746 if (!(channels[i].flags & IWN_EEPROM_CHAN_VALID) || 1747 !(channels[i].flags & IWN_EEPROM_CHAN_WIDE)) { 1748 DPRINTF(sc, IWN_DEBUG_RESET, 1749 "skip chan %d flags 0x%x maxpwr %d\n", 1750 band->chan[i], channels[i].flags, 1751 channels[i].maxpwr); 1752 continue; 1753 } 1754 /* 1755 * Each entry defines an HT40 channel pair; find the 1756 * center channel, then the extension channel above. 1757 */ 1758 cent = ieee80211_find_channel_byieee(ic, band->chan[i], 1759 band->flags & ~IEEE80211_CHAN_HT); 1760 if (cent == NULL) { /* XXX shouldn't happen */ 1761 device_printf(sc->sc_dev, 1762 "%s: no entry for channel %d\n", 1763 __func__, band->chan[i]); 1764 continue; 1765 } 1766 extc = ieee80211_find_channel(ic, cent->ic_freq+20, 1767 band->flags & ~IEEE80211_CHAN_HT); 1768 if (extc == NULL) { 1769 DPRINTF(sc, IWN_DEBUG_RESET, 1770 "skip chan %d, extension channel not found\n", 1771 band->chan[i]); 1772 continue; 1773 } 1774 1775 DPRINTF(sc, IWN_DEBUG_RESET, 1776 "add ht40 chan %d flags 0x%x maxpwr %d\n", 1777 band->chan[i], channels[i].flags, channels[i].maxpwr); 1778 1779 c = &ic->ic_channels[ic->ic_nchans++]; 1780 c[0] = cent[0]; 1781 c->ic_extieee = extc->ic_ieee; 1782 c->ic_flags &= ~IEEE80211_CHAN_HT; 1783 c->ic_flags |= IEEE80211_CHAN_HT40U; 1784 c = &ic->ic_channels[ic->ic_nchans++]; 1785 c[0] = extc[0]; 1786 c->ic_extieee = cent->ic_ieee; 1787 c->ic_flags &= ~IEEE80211_CHAN_HT; 1788 c->ic_flags |= IEEE80211_CHAN_HT40D; 1789 } 1790 } 1791 #endif 1792 1793 static void 1794 iwn_read_eeprom_channels(struct iwn_softc *sc, int n, uint32_t addr) 1795 { 1796 struct ifnet *ifp = sc->sc_ifp; 1797 struct ieee80211com *ic = ifp->if_l2com; 1798 1799 iwn_read_prom_data(sc, addr, &sc->eeprom_channels[n], 1800 iwn_bands[n].nchan * sizeof (struct iwn_eeprom_chan)); 1801 1802 if (n < 5) 1803 iwn_read_eeprom_band(sc, n); 1804 #if 0 /* HT */ 1805 else 1806 iwn_read_eeprom_ht40(sc, n); 1807 #endif 1808 ieee80211_sort_channels(ic->ic_channels, ic->ic_nchans); 1809 } 1810 1811 #define nitems(_a) (sizeof((_a)) / sizeof((_a)[0])) 1812 1813 void 1814 iwn_read_eeprom_enhinfo(struct iwn_softc *sc) 1815 { 1816 struct iwn_eeprom_enhinfo enhinfo[35]; 1817 uint16_t val, base; 1818 int8_t maxpwr; 1819 int i; 1820 1821 iwn_read_prom_data(sc, IWN5000_EEPROM_REG, &val, 2); 1822 base = le16toh(val); 1823 iwn_read_prom_data(sc, base + IWN6000_EEPROM_ENHINFO, 1824 enhinfo, sizeof enhinfo); 1825 1826 memset(sc->enh_maxpwr, 0, sizeof sc->enh_maxpwr); 1827 for (i = 0; i < nitems(enhinfo); i++) { 1828 if (enhinfo[i].chan == 0 || enhinfo[i].reserved != 0) 1829 continue; /* Skip invalid entries. */ 1830 1831 maxpwr = 0; 1832 if (sc->txchainmask & IWN_ANT_A) 1833 maxpwr = MAX(maxpwr, enhinfo[i].chain[0]); 1834 if (sc->txchainmask & IWN_ANT_B) 1835 maxpwr = MAX(maxpwr, enhinfo[i].chain[1]); 1836 if (sc->txchainmask & IWN_ANT_C) 1837 maxpwr = MAX(maxpwr, enhinfo[i].chain[2]); 1838 if (sc->ntxchains == 2) 1839 maxpwr = MAX(maxpwr, enhinfo[i].mimo2); 1840 else if (sc->ntxchains == 3) 1841 maxpwr = MAX(maxpwr, enhinfo[i].mimo3); 1842 maxpwr /= 2; /* Convert half-dBm to dBm. */ 1843 1844 DPRINTF(sc, IWN_DEBUG_RESET, "enhinfo %d, maxpwr=%d\n", i, 1845 maxpwr); 1846 sc->enh_maxpwr[i] = maxpwr; 1847 } 1848 } 1849 1850 struct ieee80211_node * 1851 iwn_node_alloc(struct ieee80211vap *vap, const uint8_t mac[IEEE80211_ADDR_LEN]) 1852 { 1853 return malloc(sizeof (struct iwn_node), M_80211_NODE,M_NOWAIT | M_ZERO); 1854 } 1855 1856 void 1857 iwn_newassoc(struct ieee80211_node *ni, int isnew) 1858 { 1859 struct ieee80211vap *vap = ni->ni_vap; 1860 struct iwn_node *wn = (void *)ni; 1861 1862 ieee80211_amrr_node_init(&IWN_VAP(vap)->iv_amrr, 1863 &wn->amn, ni); 1864 } 1865 1866 int 1867 iwn_media_change(struct ifnet *ifp) 1868 { 1869 int error = ieee80211_media_change(ifp); 1870 /* NB: only the fixed rate can change and that doesn't need a reset */ 1871 return (error == ENETRESET ? 0 : error); 1872 } 1873 1874 int 1875 iwn_newstate(struct ieee80211vap *vap, enum ieee80211_state nstate, int arg) 1876 { 1877 struct iwn_vap *ivp = IWN_VAP(vap); 1878 struct ieee80211com *ic = vap->iv_ic; 1879 struct iwn_softc *sc = ic->ic_ifp->if_softc; 1880 int error; 1881 1882 DPRINTF(sc, IWN_DEBUG_STATE, "%s: %s -> %s\n", __func__, 1883 ieee80211_state_name[vap->iv_state], 1884 ieee80211_state_name[nstate]); 1885 1886 IEEE80211_UNLOCK(ic); 1887 IWN_LOCK(sc); 1888 callout_stop(&sc->sc_timer_to); 1889 1890 if (nstate == IEEE80211_S_AUTH && vap->iv_state != IEEE80211_S_AUTH) { 1891 /* !AUTH -> AUTH requires adapter config */ 1892 /* Reset state to handle reassociations correctly. */ 1893 sc->rxon.associd = 0; 1894 sc->rxon.filter &= ~htole32(IWN_FILTER_BSS); 1895 iwn_calib_reset(sc); 1896 error = iwn_auth(sc, vap); 1897 } 1898 if (nstate == IEEE80211_S_RUN && vap->iv_state != IEEE80211_S_RUN) { 1899 /* 1900 * !RUN -> RUN requires setting the association id 1901 * which is done with a firmware cmd. We also defer 1902 * starting the timers until that work is done. 1903 */ 1904 error = iwn_run(sc, vap); 1905 } 1906 if (nstate == IEEE80211_S_RUN) { 1907 /* 1908 * RUN -> RUN transition; just restart the timers. 1909 */ 1910 iwn_calib_reset(sc); 1911 } 1912 IWN_UNLOCK(sc); 1913 IEEE80211_LOCK(ic); 1914 return ivp->iv_newstate(vap, nstate, arg); 1915 } 1916 1917 /* 1918 * Process an RX_PHY firmware notification. This is usually immediately 1919 * followed by an MPDU_RX_DONE notification. 1920 */ 1921 void 1922 iwn_rx_phy(struct iwn_softc *sc, struct iwn_rx_desc *desc, 1923 struct iwn_rx_data *data) 1924 { 1925 struct iwn_rx_stat *stat = (struct iwn_rx_stat *)(desc + 1); 1926 1927 DPRINTF(sc, IWN_DEBUG_CALIBRATE, "%s: received PHY stats\n", __func__); 1928 1929 /* Save RX statistics, they will be used on MPDU_RX_DONE. */ 1930 memcpy(&sc->last_rx_stat, stat, sizeof (*stat)); 1931 sc->last_rx_valid = 1; 1932 } 1933 1934 static void 1935 iwn_timer_timeout(void *arg) 1936 { 1937 struct iwn_softc *sc = arg; 1938 uint32_t flags = 0; 1939 1940 IWN_LOCK_ASSERT(sc); 1941 1942 if (sc->calib_cnt && --sc->calib_cnt == 0) { 1943 DPRINTF(sc, IWN_DEBUG_CALIBRATE, "%s\n", 1944 "send statistics request"); 1945 (void) iwn_cmd(sc, IWN_CMD_GET_STATISTICS, &flags, 1946 sizeof flags, 1); 1947 sc->calib_cnt = 60; /* do calibration every 60s */ 1948 } 1949 iwn_watchdog(sc); /* NB: piggyback tx watchdog */ 1950 callout_reset(&sc->sc_timer_to, hz, iwn_timer_timeout, sc); 1951 } 1952 1953 static void 1954 iwn_calib_reset(struct iwn_softc *sc) 1955 { 1956 callout_reset(&sc->sc_timer_to, hz, iwn_timer_timeout, sc); 1957 sc->calib_cnt = 60; /* do calibration every 60s */ 1958 } 1959 1960 /* 1961 * Process an RX_DONE (4965AGN only) or MPDU_RX_DONE firmware notification. 1962 * Each MPDU_RX_DONE notification must be preceded by an RX_PHY one. 1963 */ 1964 void 1965 iwn_rx_done(struct iwn_softc *sc, struct iwn_rx_desc *desc, 1966 struct iwn_rx_data *data) 1967 { 1968 const struct iwn_hal *hal = sc->sc_hal; 1969 struct ifnet *ifp = sc->sc_ifp; 1970 struct ieee80211com *ic = ifp->if_l2com; 1971 struct iwn_rx_ring *ring = &sc->rxq; 1972 struct ieee80211_frame *wh; 1973 struct ieee80211_node *ni; 1974 struct mbuf *m, *m1; 1975 struct iwn_rx_stat *stat; 1976 caddr_t head; 1977 bus_addr_t paddr; 1978 uint32_t flags; 1979 int error, len, rssi, nf; 1980 1981 if (desc->type == IWN_MPDU_RX_DONE) { 1982 /* Check for prior RX_PHY notification. */ 1983 if (!sc->last_rx_valid) { 1984 DPRINTF(sc, IWN_DEBUG_ANY, 1985 "%s: missing RX_PHY\n", __func__); 1986 ifp->if_ierrors++; 1987 return; 1988 } 1989 sc->last_rx_valid = 0; 1990 stat = &sc->last_rx_stat; 1991 } else 1992 stat = (struct iwn_rx_stat *)(desc + 1); 1993 1994 bus_dmamap_sync(ring->data_dmat, data->map, BUS_DMASYNC_POSTREAD); 1995 1996 if (stat->cfg_phy_len > IWN_STAT_MAXLEN) { 1997 device_printf(sc->sc_dev, 1998 "%s: invalid rx statistic header, len %d\n", 1999 __func__, stat->cfg_phy_len); 2000 ifp->if_ierrors++; 2001 return; 2002 } 2003 if (desc->type == IWN_MPDU_RX_DONE) { 2004 struct iwn_rx_mpdu *mpdu = (struct iwn_rx_mpdu *)(desc + 1); 2005 head = (caddr_t)(mpdu + 1); 2006 len = le16toh(mpdu->len); 2007 } else { 2008 head = (caddr_t)(stat + 1) + stat->cfg_phy_len; 2009 len = le16toh(stat->len); 2010 } 2011 2012 flags = le32toh(*(uint32_t *)(head + len)); 2013 2014 /* Discard frames with a bad FCS early. */ 2015 if ((flags & IWN_RX_NOERROR) != IWN_RX_NOERROR) { 2016 DPRINTF(sc, IWN_DEBUG_RECV, "%s: rx flags error %x\n", 2017 __func__, flags); 2018 ifp->if_ierrors++; 2019 return; 2020 } 2021 /* Discard frames that are too short. */ 2022 if (len < sizeof (*wh)) { 2023 DPRINTF(sc, IWN_DEBUG_RECV, "%s: frame too short: %d\n", 2024 __func__, len); 2025 ifp->if_ierrors++; 2026 return; 2027 } 2028 2029 /* XXX don't need mbuf, just dma buffer */ 2030 m1 = m_getjcl(M_DONTWAIT, MT_DATA, M_PKTHDR, MJUMPAGESIZE); 2031 if (m1 == NULL) { 2032 DPRINTF(sc, IWN_DEBUG_ANY, "%s: no mbuf to restock ring\n", 2033 __func__); 2034 ifp->if_ierrors++; 2035 return; 2036 } 2037 bus_dmamap_unload(ring->data_dmat, data->map); 2038 2039 error = bus_dmamap_load(ring->data_dmat, data->map, 2040 mtod(m1, caddr_t), MJUMPAGESIZE, 2041 iwn_dma_map_addr, &paddr, BUS_DMA_NOWAIT); 2042 if (error != 0 && error != EFBIG) { 2043 device_printf(sc->sc_dev, 2044 "%s: bus_dmamap_load failed, error %d\n", __func__, error); 2045 m_freem(m1); 2046 ifp->if_ierrors++; 2047 return; 2048 } 2049 2050 m = data->m; 2051 data->m = m1; 2052 /* Update RX descriptor. */ 2053 ring->desc[ring->cur] = htole32(paddr >> 8); 2054 bus_dmamap_sync(ring->desc_dma.tag, ring->desc_dma.map, 2055 BUS_DMASYNC_PREWRITE); 2056 2057 /* Finalize mbuf. */ 2058 m->m_pkthdr.rcvif = ifp; 2059 m->m_data = head; 2060 m->m_pkthdr.len = m->m_len = len; 2061 2062 rssi = hal->get_rssi(sc, stat); 2063 2064 /* Grab a reference to the source node. */ 2065 wh = mtod(m, struct ieee80211_frame *); 2066 ni = ieee80211_find_rxnode(ic, (struct ieee80211_frame_min *)wh); 2067 nf = (ni != NULL && ni->ni_vap->iv_state == IEEE80211_S_RUN && 2068 (ic->ic_flags & IEEE80211_F_SCAN) == 0) ? sc->noise : -95; 2069 2070 if (ieee80211_radiotap_active(ic)) { 2071 struct iwn_rx_radiotap_header *tap = &sc->sc_rxtap; 2072 2073 tap->wr_tsft = htole64(stat->tstamp); 2074 tap->wr_flags = 0; 2075 if (stat->flags & htole16(IWN_STAT_FLAG_SHPREAMBLE)) 2076 tap->wr_flags |= IEEE80211_RADIOTAP_F_SHORTPRE; 2077 switch (stat->rate) { 2078 /* CCK rates. */ 2079 case 10: tap->wr_rate = 2; break; 2080 case 20: tap->wr_rate = 4; break; 2081 case 55: tap->wr_rate = 11; break; 2082 case 110: tap->wr_rate = 22; break; 2083 /* OFDM rates. */ 2084 case 0xd: tap->wr_rate = 12; break; 2085 case 0xf: tap->wr_rate = 18; break; 2086 case 0x5: tap->wr_rate = 24; break; 2087 case 0x7: tap->wr_rate = 36; break; 2088 case 0x9: tap->wr_rate = 48; break; 2089 case 0xb: tap->wr_rate = 72; break; 2090 case 0x1: tap->wr_rate = 96; break; 2091 case 0x3: tap->wr_rate = 108; break; 2092 /* Unknown rate: should not happen. */ 2093 default: tap->wr_rate = 0; 2094 } 2095 tap->wr_dbm_antsignal = rssi; 2096 tap->wr_dbm_antnoise = nf; 2097 } 2098 2099 IWN_UNLOCK(sc); 2100 2101 /* Send the frame to the 802.11 layer. */ 2102 if (ni != NULL) { 2103 (void) ieee80211_input(ni, m, rssi - nf, nf); 2104 /* Node is no longer needed. */ 2105 ieee80211_free_node(ni); 2106 } else 2107 (void) ieee80211_input_all(ic, m, rssi - nf, nf); 2108 2109 IWN_LOCK(sc); 2110 } 2111 2112 #if 0 /* HT */ 2113 /* Process an incoming Compressed BlockAck. */ 2114 void 2115 iwn_rx_compressed_ba(struct iwn_softc *sc, struct iwn_rx_desc *desc, 2116 struct iwn_rx_data *data) 2117 { 2118 struct iwn_compressed_ba *ba = (struct iwn_compressed_ba *)(desc + 1); 2119 struct iwn_tx_ring *txq; 2120 2121 txq = &sc->txq[letoh16(ba->qid)]; 2122 /* XXX TBD */ 2123 } 2124 #endif 2125 2126 /* 2127 * Process a CALIBRATION_RESULT notification sent by the initialization 2128 * firmware on response to a CMD_CALIB_CONFIG command (5000 only.) 2129 */ 2130 void 2131 iwn5000_rx_calib_results(struct iwn_softc *sc, struct iwn_rx_desc *desc, 2132 struct iwn_rx_data *data) 2133 { 2134 struct iwn_phy_calib *calib = (struct iwn_phy_calib *)(desc + 1); 2135 int len, idx = -1; 2136 2137 /* Runtime firmware should not send such a notification. */ 2138 if (sc->sc_flags & IWN_FLAG_CALIB_DONE) 2139 return; 2140 2141 len = (le32toh(desc->len) & 0x3fff) - 4; 2142 2143 switch (calib->code) { 2144 case IWN5000_PHY_CALIB_DC: 2145 if (sc->hw_type == IWN_HW_REV_TYPE_5150) 2146 idx = 0; 2147 break; 2148 case IWN5000_PHY_CALIB_LO: 2149 idx = 1; 2150 break; 2151 case IWN5000_PHY_CALIB_TX_IQ: 2152 idx = 2; 2153 break; 2154 case IWN5000_PHY_CALIB_TX_IQ_PERIODIC: 2155 if (sc->hw_type < IWN_HW_REV_TYPE_6000 && 2156 sc->hw_type != IWN_HW_REV_TYPE_5150) 2157 idx = 3; 2158 break; 2159 case IWN5000_PHY_CALIB_BASE_BAND: 2160 idx = 4; 2161 break; 2162 } 2163 if (idx == -1) /* Ignore other results. */ 2164 return; 2165 2166 /* Save calibration result. */ 2167 if (sc->calibcmd[idx].buf != NULL) 2168 free(sc->calibcmd[idx].buf, M_DEVBUF); 2169 sc->calibcmd[idx].buf = malloc(len, M_DEVBUF, M_NOWAIT); 2170 if (sc->calibcmd[idx].buf == NULL) { 2171 DPRINTF(sc, IWN_DEBUG_CALIBRATE, 2172 "not enough memory for calibration result %d\n", 2173 calib->code); 2174 return; 2175 } 2176 DPRINTF(sc, IWN_DEBUG_CALIBRATE, 2177 "saving calibration result code=%d len=%d\n", calib->code, len); 2178 sc->calibcmd[idx].len = len; 2179 memcpy(sc->calibcmd[idx].buf, calib, len); 2180 } 2181 2182 /* 2183 * Process an RX_STATISTICS or BEACON_STATISTICS firmware notification. 2184 * The latter is sent by the firmware after each received beacon. 2185 */ 2186 void 2187 iwn_rx_statistics(struct iwn_softc *sc, struct iwn_rx_desc *desc, 2188 struct iwn_rx_data *data) 2189 { 2190 const struct iwn_hal *hal = sc->sc_hal; 2191 struct ifnet *ifp = sc->sc_ifp; 2192 struct ieee80211com *ic = ifp->if_l2com; 2193 struct ieee80211vap *vap = TAILQ_FIRST(&ic->ic_vaps); 2194 struct iwn_calib_state *calib = &sc->calib; 2195 struct iwn_stats *stats = (struct iwn_stats *)(desc + 1); 2196 int temp; 2197 2198 /* Beacon stats are meaningful only when associated and not scanning. */ 2199 if (vap->iv_state != IEEE80211_S_RUN || 2200 (ic->ic_flags & IEEE80211_F_SCAN)) 2201 return; 2202 2203 DPRINTF(sc, IWN_DEBUG_CALIBRATE, "%s: cmd %d\n", __func__, desc->type); 2204 iwn_calib_reset(sc); /* Reset TX power calibration timeout. */ 2205 2206 /* Test if temperature has changed. */ 2207 if (stats->general.temp != sc->rawtemp) { 2208 /* Convert "raw" temperature to degC. */ 2209 sc->rawtemp = stats->general.temp; 2210 temp = hal->get_temperature(sc); 2211 DPRINTF(sc, IWN_DEBUG_CALIBRATE, "%s: temperature %d\n", 2212 __func__, temp); 2213 2214 /* Update TX power if need be (4965AGN only.) */ 2215 if (sc->hw_type == IWN_HW_REV_TYPE_4965) 2216 iwn4965_power_calibration(sc, temp); 2217 } 2218 2219 if (desc->type != IWN_BEACON_STATISTICS) 2220 return; /* Reply to a statistics request. */ 2221 2222 sc->noise = iwn_get_noise(&stats->rx.general); 2223 DPRINTF(sc, IWN_DEBUG_CALIBRATE, "%s: noise %d\n", __func__, sc->noise); 2224 2225 /* Test that RSSI and noise are present in stats report. */ 2226 if (le32toh(stats->rx.general.flags) != 1) { 2227 DPRINTF(sc, IWN_DEBUG_ANY, "%s\n", 2228 "received statistics without RSSI"); 2229 return; 2230 } 2231 2232 if (calib->state == IWN_CALIB_STATE_ASSOC) 2233 iwn_collect_noise(sc, &stats->rx.general); 2234 else if (calib->state == IWN_CALIB_STATE_RUN) 2235 iwn_tune_sensitivity(sc, &stats->rx); 2236 } 2237 2238 /* 2239 * Process a TX_DONE firmware notification. Unfortunately, the 4965AGN 2240 * and 5000 adapters have different incompatible TX status formats. 2241 */ 2242 void 2243 iwn4965_tx_done(struct iwn_softc *sc, struct iwn_rx_desc *desc, 2244 struct iwn_rx_data *data) 2245 { 2246 struct iwn4965_tx_stat *stat = (struct iwn4965_tx_stat *)(desc + 1); 2247 2248 DPRINTF(sc, IWN_DEBUG_XMIT, "%s: " 2249 "qid %d idx %d retries %d nkill %d rate %x duration %d status %x\n", 2250 __func__, desc->qid, desc->idx, stat->ackfailcnt, 2251 stat->btkillcnt, stat->rate, le16toh(stat->duration), 2252 le32toh(stat->status)); 2253 2254 iwn_tx_done(sc, desc, stat->ackfailcnt, le32toh(stat->status) & 0xff); 2255 } 2256 2257 void 2258 iwn5000_tx_done(struct iwn_softc *sc, struct iwn_rx_desc *desc, 2259 struct iwn_rx_data *data) 2260 { 2261 struct iwn5000_tx_stat *stat = (struct iwn5000_tx_stat *)(desc + 1); 2262 2263 DPRINTF(sc, IWN_DEBUG_XMIT, "%s: " 2264 "qid %d idx %d retries %d nkill %d rate %x duration %d status %x\n", 2265 __func__, desc->qid, desc->idx, stat->ackfailcnt, 2266 stat->btkillcnt, stat->rate, le16toh(stat->duration), 2267 le32toh(stat->status)); 2268 2269 #ifdef notyet 2270 /* Reset TX scheduler slot. */ 2271 iwn5000_reset_sched(sc, desc->qid & 0xf, desc->idx); 2272 #endif 2273 iwn_tx_done(sc, desc, stat->ackfailcnt, le16toh(stat->status) & 0xff); 2274 } 2275 2276 /* 2277 * Adapter-independent backend for TX_DONE firmware notifications. 2278 */ 2279 void 2280 iwn_tx_done(struct iwn_softc *sc, struct iwn_rx_desc *desc, int ackfailcnt, 2281 uint8_t status) 2282 { 2283 struct ifnet *ifp = sc->sc_ifp; 2284 struct iwn_tx_ring *ring = &sc->txq[desc->qid & 0xf]; 2285 struct iwn_tx_data *data = &ring->data[desc->idx]; 2286 struct iwn_node *wn = (void *)data->ni; 2287 struct mbuf *m; 2288 struct ieee80211_node *ni; 2289 2290 KASSERT(data->ni != NULL, ("no node")); 2291 2292 /* Unmap and free mbuf. */ 2293 bus_dmamap_sync(ring->data_dmat, data->map, BUS_DMASYNC_POSTWRITE); 2294 bus_dmamap_unload(ring->data_dmat, data->map); 2295 m = data->m, data->m = NULL; 2296 ni = data->ni, data->ni = NULL; 2297 2298 if (m->m_flags & M_TXCB) { 2299 /* 2300 * Channels marked for "radar" require traffic to be received 2301 * to unlock before we can transmit. Until traffic is seen 2302 * any attempt to transmit is returned immediately with status 2303 * set to IWN_TX_FAIL_TX_LOCKED. Unfortunately this can easily 2304 * happen on first authenticate after scanning. To workaround 2305 * this we ignore a failure of this sort in AUTH state so the 2306 * 802.11 layer will fall back to using a timeout to wait for 2307 * the AUTH reply. This allows the firmware time to see 2308 * traffic so a subsequent retry of AUTH succeeds. It's 2309 * unclear why the firmware does not maintain state for 2310 * channels recently visited as this would allow immediate 2311 * use of the channel after a scan (where we see traffic). 2312 */ 2313 if (status == IWN_TX_FAIL_TX_LOCKED && 2314 ni->ni_vap->iv_state == IEEE80211_S_AUTH) 2315 ieee80211_process_callback(ni, m, 0); 2316 else 2317 ieee80211_process_callback(ni, m, 2318 (status & IWN_TX_FAIL) != 0); 2319 } 2320 2321 /* 2322 * Update rate control statistics for the node. 2323 */ 2324 if (status & 0x80) { 2325 ifp->if_oerrors++; 2326 ieee80211_amrr_tx_complete(&wn->amn, 2327 IEEE80211_AMRR_FAILURE, ackfailcnt); 2328 } else { 2329 ieee80211_amrr_tx_complete(&wn->amn, 2330 IEEE80211_AMRR_SUCCESS, ackfailcnt); 2331 } 2332 m_freem(m); 2333 ieee80211_free_node(ni); 2334 2335 sc->sc_tx_timer = 0; 2336 if (--ring->queued < IWN_TX_RING_LOMARK) { 2337 sc->qfullmsk &= ~(1 << ring->qid); 2338 if (sc->qfullmsk == 0 && 2339 (ifp->if_drv_flags & IFF_DRV_OACTIVE)) { 2340 ifp->if_drv_flags &= ~IFF_DRV_OACTIVE; 2341 iwn_start_locked(ifp); 2342 } 2343 } 2344 } 2345 2346 /* 2347 * Process a "command done" firmware notification. This is where we wakeup 2348 * processes waiting for a synchronous command completion. 2349 */ 2350 void 2351 iwn_cmd_done(struct iwn_softc *sc, struct iwn_rx_desc *desc) 2352 { 2353 struct iwn_tx_ring *ring = &sc->txq[4]; 2354 struct iwn_tx_data *data; 2355 2356 if ((desc->qid & 0xf) != 4) 2357 return; /* Not a command ack. */ 2358 2359 data = &ring->data[desc->idx]; 2360 2361 /* If the command was mapped in an mbuf, free it. */ 2362 if (data->m != NULL) { 2363 bus_dmamap_unload(ring->data_dmat, data->map); 2364 m_freem(data->m); 2365 data->m = NULL; 2366 } 2367 wakeup(&ring->desc[desc->idx]); 2368 } 2369 2370 /* 2371 * Process an INT_FH_RX or INT_SW_RX interrupt. 2372 */ 2373 void 2374 iwn_notif_intr(struct iwn_softc *sc) 2375 { 2376 struct ifnet *ifp = sc->sc_ifp; 2377 struct ieee80211com *ic = ifp->if_l2com; 2378 struct ieee80211vap *vap = TAILQ_FIRST(&ic->ic_vaps); 2379 uint16_t hw; 2380 2381 bus_dmamap_sync(sc->rxq.stat_dma.tag, sc->rxq.stat_dma.map, 2382 BUS_DMASYNC_POSTREAD); 2383 2384 hw = le16toh(sc->rxq.stat->closed_count) & 0xfff; 2385 while (sc->rxq.cur != hw) { 2386 struct iwn_rx_data *data = &sc->rxq.data[sc->rxq.cur]; 2387 struct iwn_rx_desc *desc; 2388 2389 bus_dmamap_sync(sc->rxq.data_dmat, data->map, 2390 BUS_DMASYNC_POSTREAD); 2391 desc = mtod(data->m, struct iwn_rx_desc *); 2392 2393 DPRINTF(sc, IWN_DEBUG_RECV, 2394 "%s: qid %x idx %d flags %x type %d(%s) len %d\n", 2395 __func__, desc->qid & 0xf, desc->idx, desc->flags, 2396 desc->type, iwn_intr_str(desc->type), 2397 le16toh(desc->len)); 2398 2399 if (!(desc->qid & 0x80)) /* Reply to a command. */ 2400 iwn_cmd_done(sc, desc); 2401 2402 switch (desc->type) { 2403 case IWN_RX_PHY: 2404 iwn_rx_phy(sc, desc, data); 2405 break; 2406 2407 case IWN_RX_DONE: /* 4965AGN only. */ 2408 case IWN_MPDU_RX_DONE: 2409 /* An 802.11 frame has been received. */ 2410 iwn_rx_done(sc, desc, data); 2411 break; 2412 2413 #if 0 /* HT */ 2414 case IWN_RX_COMPRESSED_BA: 2415 /* A Compressed BlockAck has been received. */ 2416 iwn_rx_compressed_ba(sc, desc, data); 2417 break; 2418 #endif 2419 2420 case IWN_TX_DONE: 2421 /* An 802.11 frame has been transmitted. */ 2422 sc->sc_hal->tx_done(sc, desc, data); 2423 break; 2424 2425 case IWN_RX_STATISTICS: 2426 case IWN_BEACON_STATISTICS: 2427 iwn_rx_statistics(sc, desc, data); 2428 break; 2429 2430 case IWN_BEACON_MISSED: 2431 { 2432 struct iwn_beacon_missed *miss = 2433 (struct iwn_beacon_missed *)(desc + 1); 2434 int misses = le32toh(miss->consecutive); 2435 2436 bus_dmamap_sync(sc->rxq.data_dmat, data->map, 2437 BUS_DMASYNC_POSTREAD); 2438 2439 /* XXX not sure why we're notified w/ zero */ 2440 if (misses == 0) 2441 break; 2442 DPRINTF(sc, IWN_DEBUG_STATE, 2443 "%s: beacons missed %d/%d\n", __func__, 2444 misses, le32toh(miss->total)); 2445 2446 /* 2447 * If more than 5 consecutive beacons are missed, 2448 * reinitialize the sensitivity state machine. 2449 */ 2450 if (vap->iv_state == IEEE80211_S_RUN && misses > 5) 2451 (void) iwn_init_sensitivity(sc); 2452 if (misses >= vap->iv_bmissthreshold) { 2453 IWN_UNLOCK(sc); 2454 ieee80211_beacon_miss(ic); 2455 IWN_LOCK(sc); 2456 } 2457 break; 2458 } 2459 case IWN_UC_READY: 2460 { 2461 struct iwn_ucode_info *uc = 2462 (struct iwn_ucode_info *)(desc + 1); 2463 2464 /* The microcontroller is ready. */ 2465 bus_dmamap_sync(sc->rxq.data_dmat, data->map, 2466 BUS_DMASYNC_POSTREAD); 2467 DPRINTF(sc, IWN_DEBUG_RESET, 2468 "microcode alive notification version=%d.%d " 2469 "subtype=%x alive=%x\n", uc->major, uc->minor, 2470 uc->subtype, le32toh(uc->valid)); 2471 2472 if (le32toh(uc->valid) != 1) { 2473 device_printf(sc->sc_dev, 2474 "microcontroller initialization failed"); 2475 break; 2476 } 2477 if (uc->subtype == IWN_UCODE_INIT) { 2478 /* Save microcontroller report. */ 2479 memcpy(&sc->ucode_info, uc, sizeof (*uc)); 2480 } 2481 /* Save the address of the error log in SRAM. */ 2482 sc->errptr = le32toh(uc->errptr); 2483 break; 2484 } 2485 case IWN_STATE_CHANGED: 2486 { 2487 uint32_t *status = (uint32_t *)(desc + 1); 2488 2489 /* 2490 * State change allows hardware switch change to be 2491 * noted. However, we handle this in iwn_intr as we 2492 * get both the enable/disble intr. 2493 */ 2494 bus_dmamap_sync(sc->rxq.data_dmat, data->map, 2495 BUS_DMASYNC_POSTREAD); 2496 DPRINTF(sc, IWN_DEBUG_INTR, "state changed to %x\n", 2497 le32toh(*status)); 2498 break; 2499 } 2500 case IWN_START_SCAN: 2501 { 2502 struct iwn_start_scan *scan = 2503 (struct iwn_start_scan *)(desc + 1); 2504 2505 bus_dmamap_sync(sc->rxq.data_dmat, data->map, 2506 BUS_DMASYNC_POSTREAD); 2507 DPRINTF(sc, IWN_DEBUG_ANY, 2508 "%s: scanning channel %d status %x\n", 2509 __func__, scan->chan, le32toh(scan->status)); 2510 break; 2511 } 2512 case IWN_STOP_SCAN: 2513 { 2514 struct iwn_stop_scan *scan = 2515 (struct iwn_stop_scan *)(desc + 1); 2516 2517 bus_dmamap_sync(sc->rxq.data_dmat, data->map, 2518 BUS_DMASYNC_POSTREAD); 2519 DPRINTF(sc, IWN_DEBUG_STATE, 2520 "scan finished nchan=%d status=%d chan=%d\n", 2521 scan->nchan, scan->status, scan->chan); 2522 2523 IWN_UNLOCK(sc); 2524 ieee80211_scan_next(vap); 2525 IWN_LOCK(sc); 2526 break; 2527 } 2528 case IWN5000_CALIBRATION_RESULT: 2529 iwn5000_rx_calib_results(sc, desc, data); 2530 break; 2531 2532 case IWN5000_CALIBRATION_DONE: 2533 sc->sc_flags |= IWN_FLAG_CALIB_DONE; 2534 wakeup(sc); 2535 break; 2536 } 2537 2538 sc->rxq.cur = (sc->rxq.cur + 1) % IWN_RX_RING_COUNT; 2539 } 2540 2541 /* Tell the firmware what we have processed. */ 2542 hw = (hw == 0) ? IWN_RX_RING_COUNT - 1 : hw - 1; 2543 IWN_WRITE(sc, IWN_FH_RX_WPTR, hw & ~7); 2544 } 2545 2546 /* 2547 * Process an INT_WAKEUP interrupt raised when the microcontroller wakes up 2548 * from power-down sleep mode. 2549 */ 2550 void 2551 iwn_wakeup_intr(struct iwn_softc *sc) 2552 { 2553 int qid; 2554 2555 DPRINTF(sc, IWN_DEBUG_RESET, "%s: ucode wakeup from power-down sleep\n", 2556 __func__); 2557 2558 /* Wakeup RX and TX rings. */ 2559 IWN_WRITE(sc, IWN_FH_RX_WPTR, sc->rxq.cur & ~7); 2560 for (qid = 0; qid < sc->sc_hal->ntxqs; qid++) { 2561 struct iwn_tx_ring *ring = &sc->txq[qid]; 2562 IWN_WRITE(sc, IWN_HBUS_TARG_WRPTR, qid << 8 | ring->cur); 2563 } 2564 } 2565 2566 void 2567 iwn_rftoggle_intr(struct iwn_softc *sc) 2568 { 2569 struct ifnet *ifp = sc->sc_ifp; 2570 struct ieee80211com *ic = ifp->if_l2com; 2571 uint32_t tmp = IWN_READ(sc, IWN_GP_CNTRL); 2572 2573 IWN_LOCK_ASSERT(sc); 2574 2575 device_printf(sc->sc_dev, "RF switch: radio %s\n", 2576 (tmp & IWN_GP_CNTRL_RFKILL) ? "enabled" : "disabled"); 2577 if (tmp & IWN_GP_CNTRL_RFKILL) 2578 ieee80211_runtask(ic, &sc->sc_radioon_task); 2579 else 2580 ieee80211_runtask(ic, &sc->sc_radiooff_task); 2581 } 2582 2583 /* 2584 * Dump the error log of the firmware when a firmware panic occurs. Although 2585 * we can't debug the firmware because it is neither open source nor free, it 2586 * can help us to identify certain classes of problems. 2587 */ 2588 void 2589 iwn_fatal_intr(struct iwn_softc *sc) 2590 { 2591 const struct iwn_hal *hal = sc->sc_hal; 2592 struct iwn_fw_dump dump; 2593 int i; 2594 2595 IWN_LOCK_ASSERT(sc); 2596 2597 /* Force a complete recalibration on next init. */ 2598 sc->sc_flags &= ~IWN_FLAG_CALIB_DONE; 2599 2600 /* Check that the error log address is valid. */ 2601 if (sc->errptr < IWN_FW_DATA_BASE || 2602 sc->errptr + sizeof (dump) > 2603 IWN_FW_DATA_BASE + hal->fw_data_maxsz) { 2604 printf("%s: bad firmware error log address 0x%08x\n", 2605 __func__, sc->errptr); 2606 return; 2607 } 2608 if (iwn_nic_lock(sc) != 0) { 2609 printf("%s: could not read firmware error log\n", 2610 __func__); 2611 return; 2612 } 2613 /* Read firmware error log from SRAM. */ 2614 iwn_mem_read_region_4(sc, sc->errptr, (uint32_t *)&dump, 2615 sizeof (dump) / sizeof (uint32_t)); 2616 iwn_nic_unlock(sc); 2617 2618 if (dump.valid == 0) { 2619 printf("%s: firmware error log is empty\n", 2620 __func__); 2621 return; 2622 } 2623 printf("firmware error log:\n"); 2624 printf(" error type = \"%s\" (0x%08X)\n", 2625 (dump.id < nitems(iwn_fw_errmsg)) ? 2626 iwn_fw_errmsg[dump.id] : "UNKNOWN", 2627 dump.id); 2628 printf(" program counter = 0x%08X\n", dump.pc); 2629 printf(" source line = 0x%08X\n", dump.src_line); 2630 printf(" error data = 0x%08X%08X\n", 2631 dump.error_data[0], dump.error_data[1]); 2632 printf(" branch link = 0x%08X%08X\n", 2633 dump.branch_link[0], dump.branch_link[1]); 2634 printf(" interrupt link = 0x%08X%08X\n", 2635 dump.interrupt_link[0], dump.interrupt_link[1]); 2636 printf(" time = %u\n", dump.time[0]); 2637 2638 /* Dump driver status (TX and RX rings) while we're here. */ 2639 printf("driver status:\n"); 2640 for (i = 0; i < hal->ntxqs; i++) { 2641 struct iwn_tx_ring *ring = &sc->txq[i]; 2642 printf(" tx ring %2d: qid=%-2d cur=%-3d queued=%-3d\n", 2643 i, ring->qid, ring->cur, ring->queued); 2644 } 2645 printf(" rx ring: cur=%d\n", sc->rxq.cur); 2646 } 2647 2648 void 2649 iwn_intr(void *arg) 2650 { 2651 struct iwn_softc *sc = arg; 2652 struct ifnet *ifp = sc->sc_ifp; 2653 uint32_t r1, r2, tmp; 2654 2655 IWN_LOCK(sc); 2656 2657 /* Disable interrupts. */ 2658 IWN_WRITE(sc, IWN_INT_MASK, 0); 2659 2660 /* Read interrupts from ICT (fast) or from registers (slow). */ 2661 if (sc->sc_flags & IWN_FLAG_USE_ICT) { 2662 tmp = 0; 2663 while (sc->ict[sc->ict_cur] != 0) { 2664 tmp |= sc->ict[sc->ict_cur]; 2665 sc->ict[sc->ict_cur] = 0; /* Acknowledge. */ 2666 sc->ict_cur = (sc->ict_cur + 1) % IWN_ICT_COUNT; 2667 } 2668 tmp = le32toh(tmp); 2669 if (tmp == 0xffffffff) 2670 tmp = 0; /* Shouldn't happen. */ 2671 r1 = (tmp & 0xff00) << 16 | (tmp & 0xff); 2672 r2 = 0; /* Unused. */ 2673 } else { 2674 r1 = IWN_READ(sc, IWN_INT); 2675 if (r1 == 0xffffffff || (r1 & 0xfffffff0) == 0xa5a5a5a0) 2676 return; /* Hardware gone! */ 2677 r2 = IWN_READ(sc, IWN_FH_INT); 2678 } 2679 2680 DPRINTF(sc, IWN_DEBUG_INTR, "interrupt reg1=%x reg2=%x\n", r1, r2); 2681 2682 if (r1 == 0 && r2 == 0) 2683 goto done; /* Interrupt not for us. */ 2684 2685 /* Acknowledge interrupts. */ 2686 IWN_WRITE(sc, IWN_INT, r1); 2687 if (!(sc->sc_flags & IWN_FLAG_USE_ICT)) 2688 IWN_WRITE(sc, IWN_FH_INT, r2); 2689 2690 if (r1 & IWN_INT_RF_TOGGLED) { 2691 iwn_rftoggle_intr(sc); 2692 goto done; 2693 } 2694 if (r1 & IWN_INT_CT_REACHED) { 2695 device_printf(sc->sc_dev, "%s: critical temperature reached!\n", 2696 __func__); 2697 } 2698 if (r1 & (IWN_INT_SW_ERR | IWN_INT_HW_ERR)) { 2699 iwn_fatal_intr(sc); 2700 ifp->if_flags &= ~IFF_UP; 2701 iwn_stop_locked(sc); 2702 goto done; 2703 } 2704 if ((r1 & (IWN_INT_FH_RX | IWN_INT_SW_RX | IWN_INT_RX_PERIODIC)) || 2705 (r2 & IWN_FH_INT_RX)) { 2706 if (sc->sc_flags & IWN_FLAG_USE_ICT) { 2707 if (r1 & (IWN_INT_FH_RX | IWN_INT_SW_RX)) 2708 IWN_WRITE(sc, IWN_FH_INT, IWN_FH_INT_RX); 2709 IWN_WRITE_1(sc, IWN_INT_PERIODIC, 2710 IWN_INT_PERIODIC_DIS); 2711 iwn_notif_intr(sc); 2712 if (r1 & (IWN_INT_FH_RX | IWN_INT_SW_RX)) { 2713 IWN_WRITE_1(sc, IWN_INT_PERIODIC, 2714 IWN_INT_PERIODIC_ENA); 2715 } 2716 } else 2717 iwn_notif_intr(sc); 2718 } 2719 2720 if ((r1 & IWN_INT_FH_TX) || (r2 & IWN_FH_INT_TX)) { 2721 if (sc->sc_flags & IWN_FLAG_USE_ICT) 2722 IWN_WRITE(sc, IWN_FH_INT, IWN_FH_INT_TX); 2723 wakeup(sc); /* FH DMA transfer completed. */ 2724 } 2725 2726 if (r1 & IWN_INT_ALIVE) 2727 wakeup(sc); /* Firmware is alive. */ 2728 2729 if (r1 & IWN_INT_WAKEUP) 2730 iwn_wakeup_intr(sc); 2731 2732 done: 2733 /* Re-enable interrupts. */ 2734 if (ifp->if_flags & IFF_UP) 2735 IWN_WRITE(sc, IWN_INT_MASK, sc->int_mask); 2736 2737 IWN_UNLOCK(sc); 2738 } 2739 2740 /* 2741 * Update TX scheduler ring when transmitting an 802.11 frame (4965AGN and 2742 * 5000 adapters use a slightly different format.) 2743 */ 2744 void 2745 iwn4965_update_sched(struct iwn_softc *sc, int qid, int idx, uint8_t id, 2746 uint16_t len) 2747 { 2748 uint16_t *w = &sc->sched[qid * IWN4965_SCHED_COUNT + idx]; 2749 2750 *w = htole16(len + 8); 2751 bus_dmamap_sync(sc->sched_dma.tag, sc->sched_dma.map, 2752 BUS_DMASYNC_PREWRITE); 2753 if (idx < IWN_SCHED_WINSZ) { 2754 *(w + IWN_TX_RING_COUNT) = *w; 2755 bus_dmamap_sync(sc->sched_dma.tag, sc->sched_dma.map, 2756 BUS_DMASYNC_PREWRITE); 2757 } 2758 } 2759 2760 void 2761 iwn5000_update_sched(struct iwn_softc *sc, int qid, int idx, uint8_t id, 2762 uint16_t len) 2763 { 2764 uint16_t *w = &sc->sched[qid * IWN5000_SCHED_COUNT + idx]; 2765 2766 *w = htole16(id << 12 | (len + 8)); 2767 2768 bus_dmamap_sync(sc->sched_dma.tag, sc->sched_dma.map, 2769 BUS_DMASYNC_PREWRITE); 2770 if (idx < IWN_SCHED_WINSZ) { 2771 *(w + IWN_TX_RING_COUNT) = *w; 2772 bus_dmamap_sync(sc->sched_dma.tag, sc->sched_dma.map, 2773 BUS_DMASYNC_PREWRITE); 2774 } 2775 } 2776 2777 void 2778 iwn5000_reset_sched(struct iwn_softc *sc, int qid, int idx) 2779 { 2780 uint16_t *w = &sc->sched[qid * IWN5000_SCHED_COUNT + idx]; 2781 2782 *w = (*w & htole16(0xf000)) | htole16(1); 2783 bus_dmamap_sync(sc->sched_dma.tag, sc->sched_dma.map, 2784 BUS_DMASYNC_PREWRITE); 2785 if (idx < IWN_SCHED_WINSZ) { 2786 *(w + IWN_TX_RING_COUNT) = *w; 2787 bus_dmamap_sync(sc->sched_dma.tag, sc->sched_dma.map, 2788 BUS_DMASYNC_PREWRITE); 2789 } 2790 } 2791 2792 static uint8_t 2793 iwn_plcp_signal(int rate) { 2794 int i; 2795 2796 for (i = 0; i < IWN_RIDX_MAX + 1; i++) { 2797 if (rate == iwn_rates[i].rate) 2798 return i; 2799 } 2800 2801 return 0; 2802 } 2803 2804 int 2805 iwn_tx_data(struct iwn_softc *sc, struct mbuf *m, struct ieee80211_node *ni, 2806 struct iwn_tx_ring *ring) 2807 { 2808 const struct iwn_hal *hal = sc->sc_hal; 2809 const struct ieee80211_txparam *tp; 2810 const struct iwn_rate *rinfo; 2811 struct ieee80211vap *vap = ni->ni_vap; 2812 struct ieee80211com *ic = ni->ni_ic; 2813 struct iwn_node *wn = (void *)ni; 2814 struct iwn_tx_desc *desc; 2815 struct iwn_tx_data *data; 2816 struct iwn_tx_cmd *cmd; 2817 struct iwn_cmd_data *tx; 2818 struct ieee80211_frame *wh; 2819 struct ieee80211_key *k = NULL; 2820 struct mbuf *mnew; 2821 bus_dma_segment_t segs[IWN_MAX_SCATTER]; 2822 uint32_t flags; 2823 u_int hdrlen; 2824 int totlen, error, pad, nsegs = 0, i, rate; 2825 uint8_t ridx, type, txant; 2826 2827 IWN_LOCK_ASSERT(sc); 2828 2829 wh = mtod(m, struct ieee80211_frame *); 2830 hdrlen = ieee80211_anyhdrsize(wh); 2831 type = wh->i_fc[0] & IEEE80211_FC0_TYPE_MASK; 2832 2833 desc = &ring->desc[ring->cur]; 2834 data = &ring->data[ring->cur]; 2835 2836 /* Choose a TX rate index. */ 2837 tp = &vap->iv_txparms[ieee80211_chan2mode(ni->ni_chan)]; 2838 if (type == IEEE80211_FC0_TYPE_MGT) 2839 rate = tp->mgmtrate; 2840 else if (IEEE80211_IS_MULTICAST(wh->i_addr1)) 2841 rate = tp->mcastrate; 2842 else if (tp->ucastrate != IEEE80211_FIXED_RATE_NONE) 2843 rate = tp->ucastrate; 2844 else { 2845 (void) ieee80211_amrr_choose(ni, &wn->amn); 2846 rate = ni->ni_txrate; 2847 } 2848 ridx = iwn_plcp_signal(rate); 2849 rinfo = &iwn_rates[ridx]; 2850 2851 /* Encrypt the frame if need be. */ 2852 if (wh->i_fc[1] & IEEE80211_FC1_WEP) { 2853 k = ieee80211_crypto_encap(ni, m); 2854 if (k == NULL) { 2855 m_freem(m); 2856 return ENOBUFS; 2857 } 2858 /* Packet header may have moved, reset our local pointer. */ 2859 wh = mtod(m, struct ieee80211_frame *); 2860 } 2861 totlen = m->m_pkthdr.len; 2862 2863 if (ieee80211_radiotap_active_vap(vap)) { 2864 struct iwn_tx_radiotap_header *tap = &sc->sc_txtap; 2865 2866 tap->wt_flags = 0; 2867 tap->wt_rate = rinfo->rate; 2868 if (k != NULL) 2869 tap->wt_flags |= IEEE80211_RADIOTAP_F_WEP; 2870 2871 ieee80211_radiotap_tx(vap, m); 2872 } 2873 2874 /* Prepare TX firmware command. */ 2875 cmd = &ring->cmd[ring->cur]; 2876 cmd->code = IWN_CMD_TX_DATA; 2877 cmd->flags = 0; 2878 cmd->qid = ring->qid; 2879 cmd->idx = ring->cur; 2880 2881 tx = (struct iwn_cmd_data *)cmd->data; 2882 /* NB: No need to clear tx, all fields are reinitialized here. */ 2883 tx->scratch = 0; /* clear "scratch" area */ 2884 2885 flags = 0; 2886 if (!IEEE80211_IS_MULTICAST(wh->i_addr1)) 2887 flags |= IWN_TX_NEED_ACK; 2888 if ((wh->i_fc[0] & 2889 (IEEE80211_FC0_TYPE_MASK | IEEE80211_FC0_SUBTYPE_MASK)) == 2890 (IEEE80211_FC0_TYPE_CTL | IEEE80211_FC0_SUBTYPE_BAR)) 2891 flags |= IWN_TX_IMM_BA; /* Cannot happen yet. */ 2892 2893 if (wh->i_fc[1] & IEEE80211_FC1_MORE_FRAG) 2894 flags |= IWN_TX_MORE_FRAG; /* Cannot happen yet. */ 2895 2896 /* Check if frame must be protected using RTS/CTS or CTS-to-self. */ 2897 if (!IEEE80211_IS_MULTICAST(wh->i_addr1)) { 2898 /* NB: Group frames are sent using CCK in 802.11b/g. */ 2899 if (totlen + IEEE80211_CRC_LEN > vap->iv_rtsthreshold) { 2900 flags |= IWN_TX_NEED_RTS; 2901 } else if ((ic->ic_flags & IEEE80211_F_USEPROT) && 2902 ridx >= IWN_RIDX_OFDM6) { 2903 if (ic->ic_protmode == IEEE80211_PROT_CTSONLY) 2904 flags |= IWN_TX_NEED_CTS; 2905 else if (ic->ic_protmode == IEEE80211_PROT_RTSCTS) 2906 flags |= IWN_TX_NEED_RTS; 2907 } 2908 if (flags & (IWN_TX_NEED_RTS | IWN_TX_NEED_CTS)) { 2909 if (sc->hw_type != IWN_HW_REV_TYPE_4965) { 2910 /* 5000 autoselects RTS/CTS or CTS-to-self. */ 2911 flags &= ~(IWN_TX_NEED_RTS | IWN_TX_NEED_CTS); 2912 flags |= IWN_TX_NEED_PROTECTION; 2913 } else 2914 flags |= IWN_TX_FULL_TXOP; 2915 } 2916 } 2917 2918 if (IEEE80211_IS_MULTICAST(wh->i_addr1) || 2919 type != IEEE80211_FC0_TYPE_DATA) 2920 tx->id = hal->broadcast_id; 2921 else 2922 tx->id = wn->id; 2923 2924 if (type == IEEE80211_FC0_TYPE_MGT) { 2925 uint8_t subtype = wh->i_fc[0] & IEEE80211_FC0_SUBTYPE_MASK; 2926 2927 /* Tell HW to set timestamp in probe responses. */ 2928 if (subtype == IEEE80211_FC0_SUBTYPE_PROBE_RESP) 2929 flags |= IWN_TX_INSERT_TSTAMP; 2930 2931 if (subtype == IEEE80211_FC0_SUBTYPE_ASSOC_REQ || 2932 subtype == IEEE80211_FC0_SUBTYPE_REASSOC_REQ) 2933 tx->timeout = htole16(3); 2934 else 2935 tx->timeout = htole16(2); 2936 } else 2937 tx->timeout = htole16(0); 2938 2939 if (hdrlen & 3) { 2940 /* First segment length must be a multiple of 4. */ 2941 flags |= IWN_TX_NEED_PADDING; 2942 pad = 4 - (hdrlen & 3); 2943 } else 2944 pad = 0; 2945 2946 tx->len = htole16(totlen); 2947 tx->tid = 0; 2948 tx->rts_ntries = 60; 2949 tx->data_ntries = 15; 2950 tx->lifetime = htole32(IWN_LIFETIME_INFINITE); 2951 tx->plcp = rinfo->plcp; 2952 tx->rflags = rinfo->flags; 2953 if (tx->id == hal->broadcast_id) { 2954 /* Group or management frame. */ 2955 tx->linkq = 0; 2956 /* XXX Alternate between antenna A and B? */ 2957 txant = IWN_LSB(sc->txchainmask); 2958 tx->rflags |= IWN_RFLAG_ANT(txant); 2959 } else { 2960 tx->linkq = 0; 2961 flags |= IWN_TX_LINKQ; /* enable MRR */ 2962 } 2963 2964 /* Set physical address of "scratch area". */ 2965 tx->loaddr = htole32(IWN_LOADDR(data->scratch_paddr)); 2966 tx->hiaddr = IWN_HIADDR(data->scratch_paddr); 2967 2968 /* Copy 802.11 header in TX command. */ 2969 memcpy((uint8_t *)(tx + 1), wh, hdrlen); 2970 2971 /* Trim 802.11 header. */ 2972 m_adj(m, hdrlen); 2973 tx->security = 0; 2974 tx->flags = htole32(flags); 2975 2976 if (m->m_len > 0) { 2977 error = bus_dmamap_load_mbuf_sg(ring->data_dmat, data->map, 2978 m, segs, &nsegs, BUS_DMA_NOWAIT); 2979 if (error == EFBIG) { 2980 /* too many fragments, linearize */ 2981 mnew = m_collapse(m, M_DONTWAIT, IWN_MAX_SCATTER); 2982 if (mnew == NULL) { 2983 device_printf(sc->sc_dev, 2984 "%s: could not defrag mbuf\n", __func__); 2985 m_freem(m); 2986 return ENOBUFS; 2987 } 2988 m = mnew; 2989 error = bus_dmamap_load_mbuf_sg(ring->data_dmat, 2990 data->map, m, segs, &nsegs, BUS_DMA_NOWAIT); 2991 } 2992 if (error != 0) { 2993 device_printf(sc->sc_dev, 2994 "%s: bus_dmamap_load_mbuf_sg failed, error %d\n", 2995 __func__, error); 2996 m_freem(m); 2997 return error; 2998 } 2999 } 3000 3001 data->m = m; 3002 data->ni = ni; 3003 3004 DPRINTF(sc, IWN_DEBUG_XMIT, "%s: qid %d idx %d len %d nsegs %d\n", 3005 __func__, ring->qid, ring->cur, m->m_pkthdr.len, nsegs); 3006 3007 /* Fill TX descriptor. */ 3008 desc->nsegs = 1 + nsegs; 3009 /* First DMA segment is used by the TX command. */ 3010 desc->segs[0].addr = htole32(IWN_LOADDR(data->cmd_paddr)); 3011 desc->segs[0].len = htole16(IWN_HIADDR(data->cmd_paddr) | 3012 (4 + sizeof (*tx) + hdrlen + pad) << 4); 3013 /* Other DMA segments are for data payload. */ 3014 for (i = 1; i <= nsegs; i++) { 3015 desc->segs[i].addr = htole32(IWN_LOADDR(segs[i - 1].ds_addr)); 3016 desc->segs[i].len = htole16(IWN_HIADDR(segs[i - 1].ds_addr) | 3017 segs[i - 1].ds_len << 4); 3018 } 3019 3020 bus_dmamap_sync(ring->data_dmat, data->map, BUS_DMASYNC_PREWRITE); 3021 bus_dmamap_sync(ring->data_dmat, ring->cmd_dma.map, 3022 BUS_DMASYNC_PREWRITE); 3023 bus_dmamap_sync(ring->desc_dma.tag, ring->desc_dma.map, 3024 BUS_DMASYNC_PREWRITE); 3025 3026 #ifdef notyet 3027 /* Update TX scheduler. */ 3028 hal->update_sched(sc, ring->qid, ring->cur, tx->id, totlen); 3029 #endif 3030 3031 /* Kick TX ring. */ 3032 ring->cur = (ring->cur + 1) % IWN_TX_RING_COUNT; 3033 IWN_WRITE(sc, IWN_HBUS_TARG_WRPTR, ring->qid << 8 | ring->cur); 3034 3035 /* Mark TX ring as full if we reach a certain threshold. */ 3036 if (++ring->queued > IWN_TX_RING_HIMARK) 3037 sc->qfullmsk |= 1 << ring->qid; 3038 3039 return 0; 3040 } 3041 3042 static int 3043 iwn_tx_data_raw(struct iwn_softc *sc, struct mbuf *m, 3044 struct ieee80211_node *ni, struct iwn_tx_ring *ring, 3045 const struct ieee80211_bpf_params *params) 3046 { 3047 const struct iwn_hal *hal = sc->sc_hal; 3048 const struct iwn_rate *rinfo; 3049 struct ifnet *ifp = sc->sc_ifp; 3050 struct ieee80211vap *vap = ni->ni_vap; 3051 struct ieee80211com *ic = ifp->if_l2com; 3052 struct iwn_tx_cmd *cmd; 3053 struct iwn_cmd_data *tx; 3054 struct ieee80211_frame *wh; 3055 struct iwn_tx_desc *desc; 3056 struct iwn_tx_data *data; 3057 struct mbuf *mnew; 3058 bus_addr_t paddr; 3059 bus_dma_segment_t segs[IWN_MAX_SCATTER]; 3060 uint32_t flags; 3061 u_int hdrlen; 3062 int totlen, error, pad, nsegs = 0, i, rate; 3063 uint8_t ridx, type, txant; 3064 3065 IWN_LOCK_ASSERT(sc); 3066 3067 wh = mtod(m, struct ieee80211_frame *); 3068 hdrlen = ieee80211_anyhdrsize(wh); 3069 type = wh->i_fc[0] & IEEE80211_FC0_TYPE_MASK; 3070 3071 desc = &ring->desc[ring->cur]; 3072 data = &ring->data[ring->cur]; 3073 3074 /* Choose a TX rate index. */ 3075 rate = params->ibp_rate0; 3076 if (!ieee80211_isratevalid(ic->ic_rt, rate)) { 3077 /* XXX fall back to mcast/mgmt rate? */ 3078 m_freem(m); 3079 return EINVAL; 3080 } 3081 ridx = iwn_plcp_signal(rate); 3082 rinfo = &iwn_rates[ridx]; 3083 3084 totlen = m->m_pkthdr.len; 3085 3086 /* Prepare TX firmware command. */ 3087 cmd = &ring->cmd[ring->cur]; 3088 cmd->code = IWN_CMD_TX_DATA; 3089 cmd->flags = 0; 3090 cmd->qid = ring->qid; 3091 cmd->idx = ring->cur; 3092 3093 tx = (struct iwn_cmd_data *)cmd->data; 3094 /* NB: No need to clear tx, all fields are reinitialized here. */ 3095 tx->scratch = 0; /* clear "scratch" area */ 3096 3097 flags = 0; 3098 if ((params->ibp_flags & IEEE80211_BPF_NOACK) == 0) 3099 flags |= IWN_TX_NEED_ACK; 3100 if (params->ibp_flags & IEEE80211_BPF_RTS) { 3101 if (sc->hw_type != IWN_HW_REV_TYPE_4965) { 3102 /* 5000 autoselects RTS/CTS or CTS-to-self. */ 3103 flags &= ~IWN_TX_NEED_RTS; 3104 flags |= IWN_TX_NEED_PROTECTION; 3105 } else 3106 flags |= IWN_TX_NEED_RTS | IWN_TX_FULL_TXOP; 3107 } 3108 if (params->ibp_flags & IEEE80211_BPF_CTS) { 3109 if (sc->hw_type != IWN_HW_REV_TYPE_4965) { 3110 /* 5000 autoselects RTS/CTS or CTS-to-self. */ 3111 flags &= ~IWN_TX_NEED_CTS; 3112 flags |= IWN_TX_NEED_PROTECTION; 3113 } else 3114 flags |= IWN_TX_NEED_CTS | IWN_TX_FULL_TXOP; 3115 } 3116 if (type == IEEE80211_FC0_TYPE_MGT) { 3117 uint8_t subtype = wh->i_fc[0] & IEEE80211_FC0_SUBTYPE_MASK; 3118 3119 if (subtype == IEEE80211_FC0_SUBTYPE_PROBE_RESP) 3120 flags |= IWN_TX_INSERT_TSTAMP; 3121 3122 if (subtype == IEEE80211_FC0_SUBTYPE_ASSOC_REQ || 3123 subtype == IEEE80211_FC0_SUBTYPE_REASSOC_REQ) 3124 tx->timeout = htole16(3); 3125 else 3126 tx->timeout = htole16(2); 3127 } else 3128 tx->timeout = htole16(0); 3129 3130 if (hdrlen & 3) { 3131 /* First segment length must be a multiple of 4. */ 3132 flags |= IWN_TX_NEED_PADDING; 3133 pad = 4 - (hdrlen & 3); 3134 } else 3135 pad = 0; 3136 3137 if (ieee80211_radiotap_active_vap(vap)) { 3138 struct iwn_tx_radiotap_header *tap = &sc->sc_txtap; 3139 3140 tap->wt_flags = 0; 3141 tap->wt_rate = rate; 3142 3143 ieee80211_radiotap_tx(vap, m); 3144 } 3145 3146 tx->len = htole16(totlen); 3147 tx->tid = 0; 3148 tx->id = hal->broadcast_id; 3149 tx->rts_ntries = params->ibp_try1; 3150 tx->data_ntries = params->ibp_try0; 3151 tx->lifetime = htole32(IWN_LIFETIME_INFINITE); 3152 tx->plcp = rinfo->plcp; 3153 tx->rflags = rinfo->flags; 3154 /* Group or management frame. */ 3155 tx->linkq = 0; 3156 txant = IWN_LSB(sc->txchainmask); 3157 tx->rflags |= IWN_RFLAG_ANT(txant); 3158 /* Set physical address of "scratch area". */ 3159 paddr = ring->cmd_dma.paddr + ring->cur * sizeof (struct iwn_tx_cmd); 3160 tx->loaddr = htole32(IWN_LOADDR(paddr)); 3161 tx->hiaddr = IWN_HIADDR(paddr); 3162 3163 /* Copy 802.11 header in TX command. */ 3164 memcpy((uint8_t *)(tx + 1), wh, hdrlen); 3165 3166 /* Trim 802.11 header. */ 3167 m_adj(m, hdrlen); 3168 tx->security = 0; 3169 tx->flags = htole32(flags); 3170 3171 if (m->m_len > 0) { 3172 error = bus_dmamap_load_mbuf_sg(ring->data_dmat, data->map, 3173 m, segs, &nsegs, BUS_DMA_NOWAIT); 3174 if (error == EFBIG) { 3175 /* Too many fragments, linearize. */ 3176 mnew = m_collapse(m, M_DONTWAIT, IWN_MAX_SCATTER); 3177 if (mnew == NULL) { 3178 device_printf(sc->sc_dev, 3179 "%s: could not defrag mbuf\n", __func__); 3180 m_freem(m); 3181 return ENOBUFS; 3182 } 3183 m = mnew; 3184 error = bus_dmamap_load_mbuf_sg(ring->data_dmat, 3185 data->map, m, segs, &nsegs, BUS_DMA_NOWAIT); 3186 } 3187 if (error != 0) { 3188 device_printf(sc->sc_dev, 3189 "%s: bus_dmamap_load_mbuf_sg failed, error %d\n", 3190 __func__, error); 3191 m_freem(m); 3192 return error; 3193 } 3194 } 3195 3196 data->m = m; 3197 data->ni = ni; 3198 3199 DPRINTF(sc, IWN_DEBUG_XMIT, "%s: qid %d idx %d len %d nsegs %d\n", 3200 __func__, ring->qid, ring->cur, m->m_pkthdr.len, nsegs); 3201 3202 /* Fill TX descriptor. */ 3203 desc->nsegs = 1 + nsegs; 3204 /* First DMA segment is used by the TX command. */ 3205 desc->segs[0].addr = htole32(IWN_LOADDR(data->cmd_paddr)); 3206 desc->segs[0].len = htole16(IWN_HIADDR(data->cmd_paddr) | 3207 (4 + sizeof (*tx) + hdrlen + pad) << 4); 3208 /* Other DMA segments are for data payload. */ 3209 for (i = 1; i <= nsegs; i++) { 3210 desc->segs[i].addr = htole32(IWN_LOADDR(segs[i - 1].ds_addr)); 3211 desc->segs[i].len = htole16(IWN_HIADDR(segs[i - 1].ds_addr) | 3212 segs[i - 1].ds_len << 4); 3213 } 3214 3215 bus_dmamap_sync(ring->data_dmat, data->map, BUS_DMASYNC_PREWRITE); 3216 bus_dmamap_sync(ring->data_dmat, ring->cmd_dma.map, 3217 BUS_DMASYNC_PREWRITE); 3218 bus_dmamap_sync(ring->desc_dma.tag, ring->desc_dma.map, 3219 BUS_DMASYNC_PREWRITE); 3220 3221 #ifdef notyet 3222 /* Update TX scheduler. */ 3223 hal->update_sched(sc, ring->qid, ring->cur, tx->id, totlen); 3224 #endif 3225 3226 /* Kick TX ring. */ 3227 ring->cur = (ring->cur + 1) % IWN_TX_RING_COUNT; 3228 IWN_WRITE(sc, IWN_HBUS_TARG_WRPTR, ring->qid << 8 | ring->cur); 3229 3230 /* Mark TX ring as full if we reach a certain threshold. */ 3231 if (++ring->queued > IWN_TX_RING_HIMARK) 3232 sc->qfullmsk |= 1 << ring->qid; 3233 3234 return 0; 3235 } 3236 3237 static int 3238 iwn_raw_xmit(struct ieee80211_node *ni, struct mbuf *m, 3239 const struct ieee80211_bpf_params *params) 3240 { 3241 struct ieee80211com *ic = ni->ni_ic; 3242 struct ifnet *ifp = ic->ic_ifp; 3243 struct iwn_softc *sc = ifp->if_softc; 3244 struct iwn_tx_ring *txq; 3245 int error = 0; 3246 3247 if ((ifp->if_drv_flags & IFF_DRV_RUNNING) == 0) { 3248 ieee80211_free_node(ni); 3249 m_freem(m); 3250 return ENETDOWN; 3251 } 3252 3253 IWN_LOCK(sc); 3254 if (params == NULL) 3255 txq = &sc->txq[M_WME_GETAC(m)]; 3256 else 3257 txq = &sc->txq[params->ibp_pri & 3]; 3258 3259 if (params == NULL) { 3260 /* 3261 * Legacy path; interpret frame contents to decide 3262 * precisely how to send the frame. 3263 */ 3264 error = iwn_tx_data(sc, m, ni, txq); 3265 } else { 3266 /* 3267 * Caller supplied explicit parameters to use in 3268 * sending the frame. 3269 */ 3270 error = iwn_tx_data_raw(sc, m, ni, txq, params); 3271 } 3272 if (error != 0) { 3273 /* NB: m is reclaimed on tx failure */ 3274 ieee80211_free_node(ni); 3275 ifp->if_oerrors++; 3276 } 3277 IWN_UNLOCK(sc); 3278 return error; 3279 } 3280 3281 void 3282 iwn_start(struct ifnet *ifp) 3283 { 3284 struct iwn_softc *sc = ifp->if_softc; 3285 3286 IWN_LOCK(sc); 3287 iwn_start_locked(ifp); 3288 IWN_UNLOCK(sc); 3289 } 3290 3291 void 3292 iwn_start_locked(struct ifnet *ifp) 3293 { 3294 struct iwn_softc *sc = ifp->if_softc; 3295 struct ieee80211_node *ni; 3296 struct iwn_tx_ring *txq; 3297 struct mbuf *m; 3298 int pri; 3299 3300 IWN_LOCK_ASSERT(sc); 3301 3302 for (;;) { 3303 if (sc->qfullmsk != 0) { 3304 ifp->if_drv_flags |= IFF_DRV_OACTIVE; 3305 break; 3306 } 3307 IFQ_DRV_DEQUEUE(&ifp->if_snd, m); 3308 if (m == NULL) 3309 break; 3310 ni = (struct ieee80211_node *)m->m_pkthdr.rcvif; 3311 pri = M_WME_GETAC(m); 3312 txq = &sc->txq[pri]; 3313 if (iwn_tx_data(sc, m, ni, txq) != 0) { 3314 ifp->if_oerrors++; 3315 ieee80211_free_node(ni); 3316 break; 3317 } 3318 sc->sc_tx_timer = 5; 3319 } 3320 } 3321 3322 static void 3323 iwn_watchdog(struct iwn_softc *sc) 3324 { 3325 if (sc->sc_tx_timer > 0 && --sc->sc_tx_timer == 0) { 3326 struct ifnet *ifp = sc->sc_ifp; 3327 struct ieee80211com *ic = ifp->if_l2com; 3328 3329 if_printf(ifp, "device timeout\n"); 3330 ieee80211_runtask(ic, &sc->sc_reinit_task); 3331 } 3332 } 3333 3334 int 3335 iwn_ioctl(struct ifnet *ifp, u_long cmd, caddr_t data) 3336 { 3337 struct iwn_softc *sc = ifp->if_softc; 3338 struct ieee80211com *ic = ifp->if_l2com; 3339 struct ieee80211vap *vap = TAILQ_FIRST(&ic->ic_vaps); 3340 struct ifreq *ifr = (struct ifreq *) data; 3341 int error = 0, startall = 0, stop = 0; 3342 3343 switch (cmd) { 3344 case SIOCSIFFLAGS: 3345 IWN_LOCK(sc); 3346 if (ifp->if_flags & IFF_UP) { 3347 if (!(ifp->if_drv_flags & IFF_DRV_RUNNING)) { 3348 iwn_init_locked(sc); 3349 if (IWN_READ(sc, IWN_GP_CNTRL) & IWN_GP_CNTRL_RFKILL) 3350 startall = 1; 3351 else 3352 stop = 1; 3353 } 3354 } else { 3355 if (ifp->if_drv_flags & IFF_DRV_RUNNING) 3356 iwn_stop_locked(sc); 3357 } 3358 IWN_UNLOCK(sc); 3359 if (startall) 3360 ieee80211_start_all(ic); 3361 else if (vap != NULL && stop) 3362 ieee80211_stop(vap); 3363 break; 3364 case SIOCGIFMEDIA: 3365 error = ifmedia_ioctl(ifp, ifr, &ic->ic_media, cmd); 3366 break; 3367 case SIOCGIFADDR: 3368 error = ether_ioctl(ifp, cmd, data); 3369 break; 3370 default: 3371 error = EINVAL; 3372 break; 3373 } 3374 return error; 3375 } 3376 3377 /* 3378 * Send a command to the firmware. 3379 */ 3380 int 3381 iwn_cmd(struct iwn_softc *sc, int code, const void *buf, int size, int async) 3382 { 3383 struct iwn_tx_ring *ring = &sc->txq[4]; 3384 struct iwn_tx_desc *desc; 3385 struct iwn_tx_data *data; 3386 struct iwn_tx_cmd *cmd; 3387 struct mbuf *m; 3388 bus_addr_t paddr; 3389 int totlen, error; 3390 3391 IWN_LOCK_ASSERT(sc); 3392 3393 desc = &ring->desc[ring->cur]; 3394 data = &ring->data[ring->cur]; 3395 totlen = 4 + size; 3396 3397 if (size > sizeof cmd->data) { 3398 /* Command is too large to fit in a descriptor. */ 3399 if (totlen > MCLBYTES) 3400 return EINVAL; 3401 m = m_getjcl(M_DONTWAIT, MT_DATA, M_PKTHDR, MJUMPAGESIZE); 3402 if (m == NULL) 3403 return ENOMEM; 3404 cmd = mtod(m, struct iwn_tx_cmd *); 3405 error = bus_dmamap_load(ring->data_dmat, data->map, cmd, 3406 totlen, iwn_dma_map_addr, &paddr, BUS_DMA_NOWAIT); 3407 if (error != 0) { 3408 m_freem(m); 3409 return error; 3410 } 3411 data->m = m; 3412 } else { 3413 cmd = &ring->cmd[ring->cur]; 3414 paddr = data->cmd_paddr; 3415 } 3416 3417 cmd->code = code; 3418 cmd->flags = 0; 3419 cmd->qid = ring->qid; 3420 cmd->idx = ring->cur; 3421 memcpy(cmd->data, buf, size); 3422 3423 desc->nsegs = 1; 3424 desc->segs[0].addr = htole32(IWN_LOADDR(paddr)); 3425 desc->segs[0].len = htole16(IWN_HIADDR(paddr) | totlen << 4); 3426 3427 DPRINTF(sc, IWN_DEBUG_CMD, "%s: %s (0x%x) flags %d qid %d idx %d\n", 3428 __func__, iwn_intr_str(cmd->code), cmd->code, 3429 cmd->flags, cmd->qid, cmd->idx); 3430 3431 if (size > sizeof cmd->data) { 3432 bus_dmamap_sync(ring->data_dmat, data->map, 3433 BUS_DMASYNC_PREWRITE); 3434 } else { 3435 bus_dmamap_sync(ring->data_dmat, ring->cmd_dma.map, 3436 BUS_DMASYNC_PREWRITE); 3437 } 3438 bus_dmamap_sync(ring->desc_dma.tag, ring->desc_dma.map, 3439 BUS_DMASYNC_PREWRITE); 3440 3441 #ifdef notyet 3442 /* Update TX scheduler. */ 3443 sc->sc_hal->update_sched(sc, ring->qid, ring->cur, 0, 0); 3444 #endif 3445 3446 /* Kick command ring. */ 3447 ring->cur = (ring->cur + 1) % IWN_TX_RING_COUNT; 3448 IWN_WRITE(sc, IWN_HBUS_TARG_WRPTR, ring->qid << 8 | ring->cur); 3449 3450 return async ? 0 : msleep(desc, &sc->sc_mtx, PCATCH, "iwncmd", hz); 3451 } 3452 3453 int 3454 iwn4965_add_node(struct iwn_softc *sc, struct iwn_node_info *node, int async) 3455 { 3456 struct iwn4965_node_info hnode; 3457 caddr_t src, dst; 3458 3459 /* 3460 * We use the node structure for 5000 Series internally (it is 3461 * a superset of the one for 4965AGN). We thus copy the common 3462 * fields before sending the command. 3463 */ 3464 src = (caddr_t)node; 3465 dst = (caddr_t)&hnode; 3466 memcpy(dst, src, 48); 3467 /* Skip TSC, RX MIC and TX MIC fields from ``src''. */ 3468 memcpy(dst + 48, src + 72, 20); 3469 return iwn_cmd(sc, IWN_CMD_ADD_NODE, &hnode, sizeof hnode, async); 3470 } 3471 3472 int 3473 iwn5000_add_node(struct iwn_softc *sc, struct iwn_node_info *node, int async) 3474 { 3475 /* Direct mapping. */ 3476 return iwn_cmd(sc, IWN_CMD_ADD_NODE, node, sizeof (*node), async); 3477 } 3478 3479 #if 0 /* HT */ 3480 static const uint8_t iwn_ridx_to_plcp[] = { 3481 10, 20, 55, 110, /* CCK */ 3482 0xd, 0xf, 0x5, 0x7, 0x9, 0xb, 0x1, 0x3, 0x3 /* OFDM R1-R4 */ 3483 }; 3484 static const uint8_t iwn_siso_mcs_to_plcp[] = { 3485 0, 0, 0, 0, /* CCK */ 3486 0, 0, 1, 2, 3, 4, 5, 6, 7 /* HT */ 3487 }; 3488 static const uint8_t iwn_mimo_mcs_to_plcp[] = { 3489 0, 0, 0, 0, /* CCK */ 3490 8, 8, 9, 10, 11, 12, 13, 14, 15 /* HT */ 3491 }; 3492 #endif 3493 static const uint8_t iwn_prev_ridx[] = { 3494 /* NB: allow fallback from CCK11 to OFDM9 and from OFDM6 to CCK5 */ 3495 0, 0, 1, 5, /* CCK */ 3496 2, 4, 3, 6, 7, 8, 9, 10, 10 /* OFDM */ 3497 }; 3498 3499 /* 3500 * Configure hardware link parameters for the specified 3501 * node operating on the specified channel. 3502 */ 3503 int 3504 iwn_set_link_quality(struct iwn_softc *sc, uint8_t id, int async) 3505 { 3506 struct ifnet *ifp = sc->sc_ifp; 3507 struct ieee80211com *ic = ifp->if_l2com; 3508 struct iwn_cmd_link_quality linkq; 3509 const struct iwn_rate *rinfo; 3510 int i; 3511 uint8_t txant, ridx; 3512 3513 /* Use the first valid TX antenna. */ 3514 txant = IWN_LSB(sc->txchainmask); 3515 3516 memset(&linkq, 0, sizeof linkq); 3517 linkq.id = id; 3518 linkq.antmsk_1stream = txant; 3519 linkq.antmsk_2stream = IWN_ANT_AB; 3520 linkq.ampdu_max = 31; 3521 linkq.ampdu_threshold = 3; 3522 linkq.ampdu_limit = htole16(4000); /* 4ms */ 3523 3524 #if 0 /* HT */ 3525 if (IEEE80211_IS_CHAN_HT(c)) 3526 linkq.mimo = 1; 3527 #endif 3528 3529 if (id == IWN_ID_BSS) 3530 ridx = IWN_RIDX_OFDM54; 3531 else if (IEEE80211_IS_CHAN_A(ic->ic_curchan)) 3532 ridx = IWN_RIDX_OFDM6; 3533 else 3534 ridx = IWN_RIDX_CCK1; 3535 3536 for (i = 0; i < IWN_MAX_TX_RETRIES; i++) { 3537 rinfo = &iwn_rates[ridx]; 3538 #if 0 /* HT */ 3539 if (IEEE80211_IS_CHAN_HT40(c)) { 3540 linkq.retry[i].plcp = iwn_mimo_mcs_to_plcp[ridx] 3541 | IWN_RIDX_MCS; 3542 linkq.retry[i].rflags = IWN_RFLAG_HT 3543 | IWN_RFLAG_HT40; 3544 /* XXX shortGI */ 3545 } else if (IEEE80211_IS_CHAN_HT(c)) { 3546 linkq.retry[i].plcp = iwn_siso_mcs_to_plcp[ridx] 3547 | IWN_RIDX_MCS; 3548 linkq.retry[i].rflags = IWN_RFLAG_HT; 3549 /* XXX shortGI */ 3550 } else 3551 #endif 3552 { 3553 linkq.retry[i].plcp = rinfo->plcp; 3554 linkq.retry[i].rflags = rinfo->flags; 3555 } 3556 linkq.retry[i].rflags |= IWN_RFLAG_ANT(txant); 3557 ridx = iwn_prev_ridx[ridx]; 3558 } 3559 #ifdef IWN_DEBUG 3560 if (sc->sc_debug & IWN_DEBUG_STATE) { 3561 printf("%s: set link quality for node %d, mimo %d ssmask %d\n", 3562 __func__, id, linkq.mimo, linkq.antmsk_1stream); 3563 printf("%s:", __func__); 3564 for (i = 0; i < IWN_MAX_TX_RETRIES; i++) 3565 printf(" %d:%x", linkq.retry[i].plcp, 3566 linkq.retry[i].rflags); 3567 printf("\n"); 3568 } 3569 #endif 3570 return iwn_cmd(sc, IWN_CMD_LINK_QUALITY, &linkq, sizeof linkq, async); 3571 } 3572 3573 /* 3574 * Broadcast node is used to send group-addressed and management frames. 3575 */ 3576 int 3577 iwn_add_broadcast_node(struct iwn_softc *sc, int async) 3578 { 3579 const struct iwn_hal *hal = sc->sc_hal; 3580 struct ifnet *ifp = sc->sc_ifp; 3581 struct iwn_node_info node; 3582 int error; 3583 3584 memset(&node, 0, sizeof node); 3585 IEEE80211_ADDR_COPY(node.macaddr, ifp->if_broadcastaddr); 3586 node.id = hal->broadcast_id; 3587 DPRINTF(sc, IWN_DEBUG_RESET, "%s: adding broadcast node\n", __func__); 3588 error = hal->add_node(sc, &node, async); 3589 if (error != 0) 3590 return error; 3591 3592 error = iwn_set_link_quality(sc, hal->broadcast_id, async); 3593 return error; 3594 } 3595 3596 int 3597 iwn_wme_update(struct ieee80211com *ic) 3598 { 3599 #define IWN_EXP2(x) ((1 << (x)) - 1) /* CWmin = 2^ECWmin - 1 */ 3600 #define IWN_TXOP_TO_US(v) (v<<5) 3601 struct iwn_softc *sc = ic->ic_ifp->if_softc; 3602 struct iwn_edca_params cmd; 3603 int i; 3604 3605 memset(&cmd, 0, sizeof cmd); 3606 cmd.flags = htole32(IWN_EDCA_UPDATE); 3607 for (i = 0; i < WME_NUM_AC; i++) { 3608 const struct wmeParams *wmep = 3609 &ic->ic_wme.wme_chanParams.cap_wmeParams[i]; 3610 cmd.ac[i].aifsn = wmep->wmep_aifsn; 3611 cmd.ac[i].cwmin = htole16(IWN_EXP2(wmep->wmep_logcwmin)); 3612 cmd.ac[i].cwmax = htole16(IWN_EXP2(wmep->wmep_logcwmax)); 3613 cmd.ac[i].txoplimit = 3614 htole16(IWN_TXOP_TO_US(wmep->wmep_txopLimit)); 3615 } 3616 IEEE80211_UNLOCK(ic); 3617 IWN_LOCK(sc); 3618 (void) iwn_cmd(sc, IWN_CMD_EDCA_PARAMS, &cmd, sizeof cmd, 1 /*async*/); 3619 IWN_UNLOCK(sc); 3620 IEEE80211_LOCK(ic); 3621 return 0; 3622 #undef IWN_TXOP_TO_US 3623 #undef IWN_EXP2 3624 } 3625 3626 static void 3627 iwn_update_mcast(struct ifnet *ifp) 3628 { 3629 /* Ignore */ 3630 } 3631 3632 void 3633 iwn_set_led(struct iwn_softc *sc, uint8_t which, uint8_t off, uint8_t on) 3634 { 3635 struct iwn_cmd_led led; 3636 3637 /* Clear microcode LED ownership. */ 3638 IWN_CLRBITS(sc, IWN_LED, IWN_LED_BSM_CTRL); 3639 3640 led.which = which; 3641 led.unit = htole32(10000); /* on/off in unit of 100ms */ 3642 led.off = off; 3643 led.on = on; 3644 (void)iwn_cmd(sc, IWN_CMD_SET_LED, &led, sizeof led, 1); 3645 } 3646 3647 /* 3648 * Set the critical temperature at which the firmware will stop the radio 3649 * and notify us. 3650 */ 3651 int 3652 iwn_set_critical_temp(struct iwn_softc *sc) 3653 { 3654 struct iwn_critical_temp crit; 3655 int32_t temp; 3656 3657 IWN_WRITE(sc, IWN_UCODE_GP1_CLR, IWN_UCODE_GP1_CTEMP_STOP_RF); 3658 3659 if (sc->hw_type == IWN_HW_REV_TYPE_5150) 3660 temp = (IWN_CTOK(110) - sc->temp_off) * -5; 3661 else if (sc->hw_type == IWN_HW_REV_TYPE_4965) 3662 temp = IWN_CTOK(110); 3663 else 3664 temp = 110; 3665 memset(&crit, 0, sizeof crit); 3666 crit.tempR = htole32(temp); 3667 DPRINTF(sc, IWN_DEBUG_RESET, "setting critical temp to %d\n", 3668 temp); 3669 return iwn_cmd(sc, IWN_CMD_SET_CRITICAL_TEMP, &crit, sizeof crit, 0); 3670 } 3671 3672 int 3673 iwn_set_timing(struct iwn_softc *sc, struct ieee80211_node *ni) 3674 { 3675 struct iwn_cmd_timing cmd; 3676 uint64_t val, mod; 3677 3678 memset(&cmd, 0, sizeof cmd); 3679 memcpy(&cmd.tstamp, ni->ni_tstamp.data, sizeof (uint64_t)); 3680 cmd.bintval = htole16(ni->ni_intval); 3681 cmd.lintval = htole16(10); 3682 3683 /* Compute remaining time until next beacon. */ 3684 val = (uint64_t)ni->ni_intval * 1024; /* msecs -> usecs */ 3685 mod = le64toh(cmd.tstamp) % val; 3686 cmd.binitval = htole32((uint32_t)(val - mod)); 3687 3688 DPRINTF(sc, IWN_DEBUG_RESET, "timing bintval=%u tstamp=%ju, init=%u\n", 3689 ni->ni_intval, le64toh(cmd.tstamp), (uint32_t)(val - mod)); 3690 3691 return iwn_cmd(sc, IWN_CMD_TIMING, &cmd, sizeof cmd, 1); 3692 } 3693 3694 void 3695 iwn4965_power_calibration(struct iwn_softc *sc, int temp) 3696 { 3697 /* Adjust TX power if need be (delta >= 3 degC.) */ 3698 DPRINTF(sc, IWN_DEBUG_CALIBRATE, "%s: temperature %d->%d\n", 3699 __func__, sc->temp, temp); 3700 if (abs(temp - sc->temp) >= 3) { 3701 /* Record temperature of last calibration. */ 3702 sc->temp = temp; 3703 (void)iwn4965_set_txpower(sc, 1); 3704 } 3705 } 3706 3707 /* 3708 * Set TX power for current channel (each rate has its own power settings). 3709 * This function takes into account the regulatory information from EEPROM, 3710 * the current temperature and the current voltage. 3711 */ 3712 int 3713 iwn4965_set_txpower(struct iwn_softc *sc, int async) 3714 { 3715 /* Fixed-point arithmetic division using a n-bit fractional part. */ 3716 #define fdivround(a, b, n) \ 3717 ((((1 << n) * (a)) / (b) + (1 << n) / 2) / (1 << n)) 3718 /* Linear interpolation. */ 3719 #define interpolate(x, x1, y1, x2, y2, n) \ 3720 ((y1) + fdivround(((int)(x) - (x1)) * ((y2) - (y1)), (x2) - (x1), n)) 3721 3722 static const int tdiv[IWN_NATTEN_GROUPS] = { 9, 8, 8, 8, 6 }; 3723 struct ifnet *ifp = sc->sc_ifp; 3724 struct ieee80211com *ic = ifp->if_l2com; 3725 struct iwn_ucode_info *uc = &sc->ucode_info; 3726 struct ieee80211_channel *ch; 3727 struct iwn4965_cmd_txpower cmd; 3728 struct iwn4965_eeprom_chan_samples *chans; 3729 int32_t vdiff, tdiff; 3730 int i, c, grp, maxpwr; 3731 const uint8_t *rf_gain, *dsp_gain; 3732 uint8_t chan; 3733 3734 /* Retrieve current channel from last RXON. */ 3735 chan = sc->rxon.chan; 3736 DPRINTF(sc, IWN_DEBUG_RESET, "setting TX power for channel %d\n", 3737 chan); 3738 ch = &ic->ic_channels[chan]; 3739 3740 memset(&cmd, 0, sizeof cmd); 3741 cmd.band = IEEE80211_IS_CHAN_5GHZ(ch) ? 0 : 1; 3742 cmd.chan = chan; 3743 3744 if (IEEE80211_IS_CHAN_5GHZ(ch)) { 3745 maxpwr = sc->maxpwr5GHz; 3746 rf_gain = iwn4965_rf_gain_5ghz; 3747 dsp_gain = iwn4965_dsp_gain_5ghz; 3748 } else { 3749 maxpwr = sc->maxpwr2GHz; 3750 rf_gain = iwn4965_rf_gain_2ghz; 3751 dsp_gain = iwn4965_dsp_gain_2ghz; 3752 } 3753 3754 /* Compute voltage compensation. */ 3755 vdiff = ((int32_t)le32toh(uc->volt) - sc->eeprom_voltage) / 7; 3756 if (vdiff > 0) 3757 vdiff *= 2; 3758 if (abs(vdiff) > 2) 3759 vdiff = 0; 3760 DPRINTF(sc, IWN_DEBUG_CALIBRATE | IWN_DEBUG_TXPOW, 3761 "%s: voltage compensation=%d (UCODE=%d, EEPROM=%d)\n", 3762 __func__, vdiff, le32toh(uc->volt), sc->eeprom_voltage); 3763 3764 /* Get channel attenuation group. */ 3765 if (chan <= 20) /* 1-20 */ 3766 grp = 4; 3767 else if (chan <= 43) /* 34-43 */ 3768 grp = 0; 3769 else if (chan <= 70) /* 44-70 */ 3770 grp = 1; 3771 else if (chan <= 124) /* 71-124 */ 3772 grp = 2; 3773 else /* 125-200 */ 3774 grp = 3; 3775 DPRINTF(sc, IWN_DEBUG_CALIBRATE | IWN_DEBUG_TXPOW, 3776 "%s: chan %d, attenuation group=%d\n", __func__, chan, grp); 3777 3778 /* Get channel sub-band. */ 3779 for (i = 0; i < IWN_NBANDS; i++) 3780 if (sc->bands[i].lo != 0 && 3781 sc->bands[i].lo <= chan && chan <= sc->bands[i].hi) 3782 break; 3783 if (i == IWN_NBANDS) /* Can't happen in real-life. */ 3784 return EINVAL; 3785 chans = sc->bands[i].chans; 3786 DPRINTF(sc, IWN_DEBUG_CALIBRATE | IWN_DEBUG_TXPOW, 3787 "%s: chan %d sub-band=%d\n", __func__, chan, i); 3788 3789 for (c = 0; c < 2; c++) { 3790 uint8_t power, gain, temp; 3791 int maxchpwr, pwr, ridx, idx; 3792 3793 power = interpolate(chan, 3794 chans[0].num, chans[0].samples[c][1].power, 3795 chans[1].num, chans[1].samples[c][1].power, 1); 3796 gain = interpolate(chan, 3797 chans[0].num, chans[0].samples[c][1].gain, 3798 chans[1].num, chans[1].samples[c][1].gain, 1); 3799 temp = interpolate(chan, 3800 chans[0].num, chans[0].samples[c][1].temp, 3801 chans[1].num, chans[1].samples[c][1].temp, 1); 3802 DPRINTF(sc, IWN_DEBUG_CALIBRATE | IWN_DEBUG_TXPOW, 3803 "%s: Tx chain %d: power=%d gain=%d temp=%d\n", 3804 __func__, c, power, gain, temp); 3805 3806 /* Compute temperature compensation. */ 3807 tdiff = ((sc->temp - temp) * 2) / tdiv[grp]; 3808 DPRINTF(sc, IWN_DEBUG_CALIBRATE | IWN_DEBUG_TXPOW, 3809 "%s: temperature compensation=%d (current=%d, EEPROM=%d)\n", 3810 __func__, tdiff, sc->temp, temp); 3811 3812 for (ridx = 0; ridx <= IWN_RIDX_MAX; ridx++) { 3813 /* Convert dBm to half-dBm. */ 3814 maxchpwr = sc->maxpwr[chan] * 2; 3815 if ((ridx / 8) & 1) 3816 maxchpwr -= 6; /* MIMO 2T: -3dB */ 3817 3818 pwr = maxpwr; 3819 3820 /* Adjust TX power based on rate. */ 3821 if ((ridx % 8) == 5) 3822 pwr -= 15; /* OFDM48: -7.5dB */ 3823 else if ((ridx % 8) == 6) 3824 pwr -= 17; /* OFDM54: -8.5dB */ 3825 else if ((ridx % 8) == 7) 3826 pwr -= 20; /* OFDM60: -10dB */ 3827 else 3828 pwr -= 10; /* Others: -5dB */ 3829 3830 /* Do not exceed channel max TX power. */ 3831 if (pwr > maxchpwr) 3832 pwr = maxchpwr; 3833 3834 idx = gain - (pwr - power) - tdiff - vdiff; 3835 if ((ridx / 8) & 1) /* MIMO */ 3836 idx += (int32_t)le32toh(uc->atten[grp][c]); 3837 3838 if (cmd.band == 0) 3839 idx += 9; /* 5GHz */ 3840 if (ridx == IWN_RIDX_MAX) 3841 idx += 5; /* CCK */ 3842 3843 /* Make sure idx stays in a valid range. */ 3844 if (idx < 0) 3845 idx = 0; 3846 else if (idx > IWN4965_MAX_PWR_INDEX) 3847 idx = IWN4965_MAX_PWR_INDEX; 3848 3849 DPRINTF(sc, IWN_DEBUG_CALIBRATE | IWN_DEBUG_TXPOW, 3850 "%s: Tx chain %d, rate idx %d: power=%d\n", 3851 __func__, c, ridx, idx); 3852 cmd.power[ridx].rf_gain[c] = rf_gain[idx]; 3853 cmd.power[ridx].dsp_gain[c] = dsp_gain[idx]; 3854 } 3855 } 3856 3857 DPRINTF(sc, IWN_DEBUG_CALIBRATE | IWN_DEBUG_TXPOW, 3858 "%s: set tx power for chan %d\n", __func__, chan); 3859 return iwn_cmd(sc, IWN_CMD_TXPOWER, &cmd, sizeof cmd, async); 3860 3861 #undef interpolate 3862 #undef fdivround 3863 } 3864 3865 int 3866 iwn5000_set_txpower(struct iwn_softc *sc, int async) 3867 { 3868 struct iwn5000_cmd_txpower cmd; 3869 3870 /* 3871 * TX power calibration is handled automatically by the firmware 3872 * for 5000 Series. 3873 */ 3874 memset(&cmd, 0, sizeof cmd); 3875 cmd.global_limit = 2 * IWN5000_TXPOWER_MAX_DBM; /* 16 dBm */ 3876 cmd.flags = IWN5000_TXPOWER_NO_CLOSED; 3877 cmd.srv_limit = IWN5000_TXPOWER_AUTO; 3878 DPRINTF(sc, IWN_DEBUG_CALIBRATE, "%s: setting TX power\n", __func__); 3879 return iwn_cmd(sc, IWN_CMD_TXPOWER_DBM, &cmd, sizeof cmd, async); 3880 } 3881 3882 /* 3883 * Retrieve the maximum RSSI (in dBm) among receivers. 3884 */ 3885 int 3886 iwn4965_get_rssi(struct iwn_softc *sc, struct iwn_rx_stat *stat) 3887 { 3888 struct iwn4965_rx_phystat *phy = (void *)stat->phybuf; 3889 uint8_t mask, agc; 3890 int rssi; 3891 3892 mask = (le16toh(phy->antenna) >> 4) & IWN_ANT_ABC; 3893 agc = (le16toh(phy->agc) >> 7) & 0x7f; 3894 3895 rssi = 0; 3896 #if 0 3897 if (mask & IWN_ANT_A) /* Ant A */ 3898 rssi = max(rssi, phy->rssi[0]); 3899 if (mask & IWN_ATH_B) /* Ant B */ 3900 rssi = max(rssi, phy->rssi[2]); 3901 if (mask & IWN_ANT_C) /* Ant C */ 3902 rssi = max(rssi, phy->rssi[4]); 3903 #else 3904 rssi = max(rssi, phy->rssi[0]); 3905 rssi = max(rssi, phy->rssi[2]); 3906 rssi = max(rssi, phy->rssi[4]); 3907 #endif 3908 3909 DPRINTF(sc, IWN_DEBUG_RECV, "%s: agc %d mask 0x%x rssi %d %d %d " 3910 "result %d\n", __func__, agc, mask, 3911 phy->rssi[0], phy->rssi[2], phy->rssi[4], 3912 rssi - agc - IWN_RSSI_TO_DBM); 3913 return rssi - agc - IWN_RSSI_TO_DBM; 3914 } 3915 3916 int 3917 iwn5000_get_rssi(struct iwn_softc *sc, struct iwn_rx_stat *stat) 3918 { 3919 struct iwn5000_rx_phystat *phy = (void *)stat->phybuf; 3920 int rssi; 3921 uint8_t agc; 3922 3923 agc = (le32toh(phy->agc) >> 9) & 0x7f; 3924 3925 rssi = MAX(le16toh(phy->rssi[0]) & 0xff, 3926 le16toh(phy->rssi[1]) & 0xff); 3927 rssi = MAX(le16toh(phy->rssi[2]) & 0xff, rssi); 3928 3929 DPRINTF(sc, IWN_DEBUG_RECV, "%s: agc %d rssi %d %d %d " 3930 "result %d\n", __func__, agc, 3931 phy->rssi[0], phy->rssi[2], phy->rssi[4], 3932 rssi - agc - IWN_RSSI_TO_DBM); 3933 return rssi - agc - IWN_RSSI_TO_DBM; 3934 } 3935 3936 /* 3937 * Retrieve the average noise (in dBm) among receivers. 3938 */ 3939 int 3940 iwn_get_noise(const struct iwn_rx_general_stats *stats) 3941 { 3942 int i, total, nbant, noise; 3943 3944 total = nbant = 0; 3945 for (i = 0; i < 3; i++) { 3946 if ((noise = le32toh(stats->noise[i]) & 0xff) == 0) 3947 continue; 3948 total += noise; 3949 nbant++; 3950 } 3951 /* There should be at least one antenna but check anyway. */ 3952 return (nbant == 0) ? -127 : (total / nbant) - 107; 3953 } 3954 3955 /* 3956 * Compute temperature (in degC) from last received statistics. 3957 */ 3958 int 3959 iwn4965_get_temperature(struct iwn_softc *sc) 3960 { 3961 struct iwn_ucode_info *uc = &sc->ucode_info; 3962 int32_t r1, r2, r3, r4, temp; 3963 3964 r1 = le32toh(uc->temp[0].chan20MHz); 3965 r2 = le32toh(uc->temp[1].chan20MHz); 3966 r3 = le32toh(uc->temp[2].chan20MHz); 3967 r4 = le32toh(sc->rawtemp); 3968 3969 if (r1 == r3) /* Prevents division by 0 (should not happen.) */ 3970 return 0; 3971 3972 /* Sign-extend 23-bit R4 value to 32-bit. */ 3973 r4 = (r4 << 8) >> 8; 3974 /* Compute temperature in Kelvin. */ 3975 temp = (259 * (r4 - r2)) / (r3 - r1); 3976 temp = (temp * 97) / 100 + 8; 3977 3978 DPRINTF(sc, IWN_DEBUG_ANY, "temperature %dK/%dC\n", temp, 3979 IWN_KTOC(temp)); 3980 return IWN_KTOC(temp); 3981 } 3982 3983 int 3984 iwn5000_get_temperature(struct iwn_softc *sc) 3985 { 3986 int32_t temp; 3987 3988 /* 3989 * Temperature is not used by the driver for 5000 Series because 3990 * TX power calibration is handled by firmware. We export it to 3991 * users through the sensor framework though. 3992 */ 3993 temp = le32toh(sc->rawtemp); 3994 if (sc->hw_type == IWN_HW_REV_TYPE_5150) { 3995 temp = (temp / -5) + sc->temp_off; 3996 temp = IWN_KTOC(temp); 3997 } 3998 return temp; 3999 } 4000 4001 /* 4002 * Initialize sensitivity calibration state machine. 4003 */ 4004 int 4005 iwn_init_sensitivity(struct iwn_softc *sc) 4006 { 4007 const struct iwn_hal *hal = sc->sc_hal; 4008 struct iwn_calib_state *calib = &sc->calib; 4009 uint32_t flags; 4010 int error; 4011 4012 /* Reset calibration state machine. */ 4013 memset(calib, 0, sizeof (*calib)); 4014 calib->state = IWN_CALIB_STATE_INIT; 4015 calib->cck_state = IWN_CCK_STATE_HIFA; 4016 /* Set initial correlation values. */ 4017 calib->ofdm_x1 = sc->limits->min_ofdm_x1; 4018 calib->ofdm_mrc_x1 = sc->limits->min_ofdm_mrc_x1; 4019 calib->ofdm_x4 = 90; 4020 calib->ofdm_mrc_x4 = sc->limits->min_ofdm_mrc_x4; 4021 calib->cck_x4 = 125; 4022 calib->cck_mrc_x4 = sc->limits->min_cck_mrc_x4; 4023 calib->energy_cck = sc->limits->energy_cck; 4024 4025 /* Write initial sensitivity. */ 4026 error = iwn_send_sensitivity(sc); 4027 if (error != 0) 4028 return error; 4029 4030 /* Write initial gains. */ 4031 error = hal->init_gains(sc); 4032 if (error != 0) 4033 return error; 4034 4035 /* Request statistics at each beacon interval. */ 4036 flags = 0; 4037 DPRINTF(sc, IWN_DEBUG_CALIBRATE, "%s: calibrate phy\n", __func__); 4038 return iwn_cmd(sc, IWN_CMD_GET_STATISTICS, &flags, sizeof flags, 1); 4039 } 4040 4041 /* 4042 * Collect noise and RSSI statistics for the first 20 beacons received 4043 * after association and use them to determine connected antennas and 4044 * to set differential gains. 4045 */ 4046 void 4047 iwn_collect_noise(struct iwn_softc *sc, 4048 const struct iwn_rx_general_stats *stats) 4049 { 4050 const struct iwn_hal *hal = sc->sc_hal; 4051 struct iwn_calib_state *calib = &sc->calib; 4052 uint32_t val; 4053 int i; 4054 4055 /* Accumulate RSSI and noise for all 3 antennas. */ 4056 for (i = 0; i < 3; i++) { 4057 calib->rssi[i] += le32toh(stats->rssi[i]) & 0xff; 4058 calib->noise[i] += le32toh(stats->noise[i]) & 0xff; 4059 } 4060 /* NB: We update differential gains only once after 20 beacons. */ 4061 if (++calib->nbeacons < 20) 4062 return; 4063 4064 /* Determine highest average RSSI. */ 4065 val = MAX(calib->rssi[0], calib->rssi[1]); 4066 val = MAX(calib->rssi[2], val); 4067 4068 /* Determine which antennas are connected. */ 4069 sc->chainmask = 0; 4070 for (i = 0; i < 3; i++) 4071 if (val - calib->rssi[i] <= 15 * 20) 4072 sc->chainmask |= 1 << i; 4073 /* If none of the TX antennas are connected, keep at least one. */ 4074 if ((sc->chainmask & sc->txchainmask) == 0) 4075 sc->chainmask |= IWN_LSB(sc->txchainmask); 4076 4077 (void)hal->set_gains(sc); 4078 calib->state = IWN_CALIB_STATE_RUN; 4079 4080 #ifdef notyet 4081 /* XXX Disable RX chains with no antennas connected. */ 4082 sc->rxon.rxchain = htole16(IWN_RXCHAIN_SEL(sc->chainmask)); 4083 (void)iwn_cmd(sc, IWN_CMD_RXON, &sc->rxon, hal->rxonsz, 1); 4084 #endif 4085 4086 #if 0 4087 /* XXX: not yet */ 4088 /* Enable power-saving mode if requested by user. */ 4089 if (sc->sc_ic.ic_flags & IEEE80211_F_PMGTON) 4090 (void)iwn_set_pslevel(sc, 0, 3, 1); 4091 #endif 4092 } 4093 4094 int 4095 iwn4965_init_gains(struct iwn_softc *sc) 4096 { 4097 struct iwn_phy_calib_gain cmd; 4098 4099 memset(&cmd, 0, sizeof cmd); 4100 cmd.code = IWN4965_PHY_CALIB_DIFF_GAIN; 4101 /* Differential gains initially set to 0 for all 3 antennas. */ 4102 DPRINTF(sc, IWN_DEBUG_CALIBRATE, 4103 "%s: setting initial differential gains\n", __func__); 4104 return iwn_cmd(sc, IWN_CMD_PHY_CALIB, &cmd, sizeof cmd, 1); 4105 } 4106 4107 int 4108 iwn5000_init_gains(struct iwn_softc *sc) 4109 { 4110 struct iwn_phy_calib cmd; 4111 4112 if (sc->hw_type == IWN_HW_REV_TYPE_6050) 4113 return 0; 4114 4115 memset(&cmd, 0, sizeof cmd); 4116 cmd.code = IWN5000_PHY_CALIB_RESET_NOISE_GAIN; 4117 cmd.ngroups = 1; 4118 cmd.isvalid = 1; 4119 DPRINTF(sc, IWN_DEBUG_CALIBRATE, 4120 "%s: setting initial differential gains\n", __func__); 4121 return iwn_cmd(sc, IWN_CMD_PHY_CALIB, &cmd, sizeof cmd, 1); 4122 } 4123 4124 int 4125 iwn4965_set_gains(struct iwn_softc *sc) 4126 { 4127 struct iwn_calib_state *calib = &sc->calib; 4128 struct iwn_phy_calib_gain cmd; 4129 int i, delta, noise; 4130 4131 /* Get minimal noise among connected antennas. */ 4132 noise = INT_MAX; /* NB: There's at least one antenna. */ 4133 for (i = 0; i < 3; i++) 4134 if (sc->chainmask & (1 << i)) 4135 noise = MIN(calib->noise[i], noise); 4136 4137 memset(&cmd, 0, sizeof cmd); 4138 cmd.code = IWN4965_PHY_CALIB_DIFF_GAIN; 4139 /* Set differential gains for connected antennas. */ 4140 for (i = 0; i < 3; i++) { 4141 if (sc->chainmask & (1 << i)) { 4142 /* Compute attenuation (in unit of 1.5dB). */ 4143 delta = (noise - (int32_t)calib->noise[i]) / 30; 4144 /* NB: delta <= 0 */ 4145 /* Limit to [-4.5dB,0]. */ 4146 cmd.gain[i] = MIN(abs(delta), 3); 4147 if (delta < 0) 4148 cmd.gain[i] |= 1 << 2; /* sign bit */ 4149 } 4150 } 4151 DPRINTF(sc, IWN_DEBUG_CALIBRATE, 4152 "setting differential gains Ant A/B/C: %x/%x/%x (%x)\n", 4153 cmd.gain[0], cmd.gain[1], cmd.gain[2], sc->chainmask); 4154 return iwn_cmd(sc, IWN_CMD_PHY_CALIB, &cmd, sizeof cmd, 1); 4155 } 4156 4157 int 4158 iwn5000_set_gains(struct iwn_softc *sc) 4159 { 4160 struct iwn_calib_state *calib = &sc->calib; 4161 struct iwn_phy_calib_gain cmd; 4162 int i, ant, delta; 4163 4164 if (sc->hw_type == IWN_HW_REV_TYPE_6050) 4165 return 0; 4166 4167 memset(&cmd, 0, sizeof cmd); 4168 cmd.code = IWN5000_PHY_CALIB_NOISE_GAIN; 4169 cmd.ngroups = 1; 4170 cmd.isvalid = 1; 4171 /* Get first available RX antenna as referential. */ 4172 ant = IWN_LSB(sc->rxchainmask); 4173 /* Set differential gains for other antennas. */ 4174 for (i = ant + 1; i < 3; i++) { 4175 if (sc->chainmask & (1 << i)) { 4176 /* The delta is relative to antenna "ant". */ 4177 delta = ((int32_t)calib->noise[ant] - 4178 (int32_t)calib->noise[i]) / 30; 4179 /* Limit to [-4.5dB,+4.5dB]. */ 4180 cmd.gain[i - 1] = MIN(abs(delta), 3); 4181 if (delta < 0) 4182 cmd.gain[i - 1] |= 1 << 2; /* sign bit */ 4183 } 4184 } 4185 DPRINTF(sc, IWN_DEBUG_CALIBRATE, 4186 "setting differential gains Ant B/C: %x/%x (%x)\n", 4187 cmd.gain[0], cmd.gain[1], sc->chainmask); 4188 return iwn_cmd(sc, IWN_CMD_PHY_CALIB, &cmd, sizeof cmd, 1); 4189 } 4190 4191 /* 4192 * Tune RF RX sensitivity based on the number of false alarms detected 4193 * during the last beacon period. 4194 */ 4195 void 4196 iwn_tune_sensitivity(struct iwn_softc *sc, const struct iwn_rx_stats *stats) 4197 { 4198 #define inc(val, inc, max) \ 4199 if ((val) < (max)) { \ 4200 if ((val) < (max) - (inc)) \ 4201 (val) += (inc); \ 4202 else \ 4203 (val) = (max); \ 4204 needs_update = 1; \ 4205 } 4206 #define dec(val, dec, min) \ 4207 if ((val) > (min)) { \ 4208 if ((val) > (min) + (dec)) \ 4209 (val) -= (dec); \ 4210 else \ 4211 (val) = (min); \ 4212 needs_update = 1; \ 4213 } 4214 4215 const struct iwn_sensitivity_limits *limits = sc->limits; 4216 struct iwn_calib_state *calib = &sc->calib; 4217 uint32_t val, rxena, fa; 4218 uint32_t energy[3], energy_min; 4219 uint8_t noise[3], noise_ref; 4220 int i, needs_update = 0; 4221 4222 /* Check that we've been enabled long enough. */ 4223 rxena = le32toh(stats->general.load); 4224 if (rxena == 0) 4225 return; 4226 4227 /* Compute number of false alarms since last call for OFDM. */ 4228 fa = le32toh(stats->ofdm.bad_plcp) - calib->bad_plcp_ofdm; 4229 fa += le32toh(stats->ofdm.fa) - calib->fa_ofdm; 4230 fa *= 200 * 1024; /* 200TU */ 4231 4232 /* Save counters values for next call. */ 4233 calib->bad_plcp_ofdm = le32toh(stats->ofdm.bad_plcp); 4234 calib->fa_ofdm = le32toh(stats->ofdm.fa); 4235 4236 if (fa > 50 * rxena) { 4237 /* High false alarm count, decrease sensitivity. */ 4238 DPRINTF(sc, IWN_DEBUG_CALIBRATE, 4239 "%s: OFDM high false alarm count: %u\n", __func__, fa); 4240 inc(calib->ofdm_x1, 1, limits->max_ofdm_x1); 4241 inc(calib->ofdm_mrc_x1, 1, limits->max_ofdm_mrc_x1); 4242 inc(calib->ofdm_x4, 1, limits->max_ofdm_x4); 4243 inc(calib->ofdm_mrc_x4, 1, limits->max_ofdm_mrc_x4); 4244 4245 } else if (fa < 5 * rxena) { 4246 /* Low false alarm count, increase sensitivity. */ 4247 DPRINTF(sc, IWN_DEBUG_CALIBRATE, 4248 "%s: OFDM low false alarm count: %u\n", __func__, fa); 4249 dec(calib->ofdm_x1, 1, limits->min_ofdm_x1); 4250 dec(calib->ofdm_mrc_x1, 1, limits->min_ofdm_mrc_x1); 4251 dec(calib->ofdm_x4, 1, limits->min_ofdm_x4); 4252 dec(calib->ofdm_mrc_x4, 1, limits->min_ofdm_mrc_x4); 4253 } 4254 4255 /* Compute maximum noise among 3 receivers. */ 4256 for (i = 0; i < 3; i++) 4257 noise[i] = (le32toh(stats->general.noise[i]) >> 8) & 0xff; 4258 val = MAX(noise[0], noise[1]); 4259 val = MAX(noise[2], val); 4260 /* Insert it into our samples table. */ 4261 calib->noise_samples[calib->cur_noise_sample] = val; 4262 calib->cur_noise_sample = (calib->cur_noise_sample + 1) % 20; 4263 4264 /* Compute maximum noise among last 20 samples. */ 4265 noise_ref = calib->noise_samples[0]; 4266 for (i = 1; i < 20; i++) 4267 noise_ref = MAX(noise_ref, calib->noise_samples[i]); 4268 4269 /* Compute maximum energy among 3 receivers. */ 4270 for (i = 0; i < 3; i++) 4271 energy[i] = le32toh(stats->general.energy[i]); 4272 val = MIN(energy[0], energy[1]); 4273 val = MIN(energy[2], val); 4274 /* Insert it into our samples table. */ 4275 calib->energy_samples[calib->cur_energy_sample] = val; 4276 calib->cur_energy_sample = (calib->cur_energy_sample + 1) % 10; 4277 4278 /* Compute minimum energy among last 10 samples. */ 4279 energy_min = calib->energy_samples[0]; 4280 for (i = 1; i < 10; i++) 4281 energy_min = MAX(energy_min, calib->energy_samples[i]); 4282 energy_min += 6; 4283 4284 /* Compute number of false alarms since last call for CCK. */ 4285 fa = le32toh(stats->cck.bad_plcp) - calib->bad_plcp_cck; 4286 fa += le32toh(stats->cck.fa) - calib->fa_cck; 4287 fa *= 200 * 1024; /* 200TU */ 4288 4289 /* Save counters values for next call. */ 4290 calib->bad_plcp_cck = le32toh(stats->cck.bad_plcp); 4291 calib->fa_cck = le32toh(stats->cck.fa); 4292 4293 if (fa > 50 * rxena) { 4294 /* High false alarm count, decrease sensitivity. */ 4295 DPRINTF(sc, IWN_DEBUG_CALIBRATE, 4296 "%s: CCK high false alarm count: %u\n", __func__, fa); 4297 calib->cck_state = IWN_CCK_STATE_HIFA; 4298 calib->low_fa = 0; 4299 4300 if (calib->cck_x4 > 160) { 4301 calib->noise_ref = noise_ref; 4302 if (calib->energy_cck > 2) 4303 dec(calib->energy_cck, 2, energy_min); 4304 } 4305 if (calib->cck_x4 < 160) { 4306 calib->cck_x4 = 161; 4307 needs_update = 1; 4308 } else 4309 inc(calib->cck_x4, 3, limits->max_cck_x4); 4310 4311 inc(calib->cck_mrc_x4, 3, limits->max_cck_mrc_x4); 4312 4313 } else if (fa < 5 * rxena) { 4314 /* Low false alarm count, increase sensitivity. */ 4315 DPRINTF(sc, IWN_DEBUG_CALIBRATE, 4316 "%s: CCK low false alarm count: %u\n", __func__, fa); 4317 calib->cck_state = IWN_CCK_STATE_LOFA; 4318 calib->low_fa++; 4319 4320 if (calib->cck_state != IWN_CCK_STATE_INIT && 4321 (((int32_t)calib->noise_ref - (int32_t)noise_ref) > 2 || 4322 calib->low_fa > 100)) { 4323 inc(calib->energy_cck, 2, limits->min_energy_cck); 4324 dec(calib->cck_x4, 3, limits->min_cck_x4); 4325 dec(calib->cck_mrc_x4, 3, limits->min_cck_mrc_x4); 4326 } 4327 } else { 4328 /* Not worth to increase or decrease sensitivity. */ 4329 DPRINTF(sc, IWN_DEBUG_CALIBRATE, 4330 "%s: CCK normal false alarm count: %u\n", __func__, fa); 4331 calib->low_fa = 0; 4332 calib->noise_ref = noise_ref; 4333 4334 if (calib->cck_state == IWN_CCK_STATE_HIFA) { 4335 /* Previous interval had many false alarms. */ 4336 dec(calib->energy_cck, 8, energy_min); 4337 } 4338 calib->cck_state = IWN_CCK_STATE_INIT; 4339 } 4340 4341 if (needs_update) 4342 (void)iwn_send_sensitivity(sc); 4343 #undef dec 4344 #undef inc 4345 } 4346 4347 int 4348 iwn_send_sensitivity(struct iwn_softc *sc) 4349 { 4350 struct iwn_calib_state *calib = &sc->calib; 4351 struct iwn_sensitivity_cmd cmd; 4352 4353 memset(&cmd, 0, sizeof cmd); 4354 cmd.which = IWN_SENSITIVITY_WORKTBL; 4355 /* OFDM modulation. */ 4356 cmd.corr_ofdm_x1 = htole16(calib->ofdm_x1); 4357 cmd.corr_ofdm_mrc_x1 = htole16(calib->ofdm_mrc_x1); 4358 cmd.corr_ofdm_x4 = htole16(calib->ofdm_x4); 4359 cmd.corr_ofdm_mrc_x4 = htole16(calib->ofdm_mrc_x4); 4360 cmd.energy_ofdm = htole16(sc->limits->energy_ofdm); 4361 cmd.energy_ofdm_th = htole16(62); 4362 /* CCK modulation. */ 4363 cmd.corr_cck_x4 = htole16(calib->cck_x4); 4364 cmd.corr_cck_mrc_x4 = htole16(calib->cck_mrc_x4); 4365 cmd.energy_cck = htole16(calib->energy_cck); 4366 /* Barker modulation: use default values. */ 4367 cmd.corr_barker = htole16(190); 4368 cmd.corr_barker_mrc = htole16(390); 4369 4370 DPRINTF(sc, IWN_DEBUG_RESET, 4371 "%s: set sensitivity %d/%d/%d/%d/%d/%d/%d\n", __func__, 4372 calib->ofdm_x1, calib->ofdm_mrc_x1, calib->ofdm_x4, 4373 calib->ofdm_mrc_x4, calib->cck_x4, 4374 calib->cck_mrc_x4, calib->energy_cck); 4375 return iwn_cmd(sc, IWN_CMD_SET_SENSITIVITY, &cmd, sizeof cmd, 1); 4376 } 4377 4378 /* 4379 * Set STA mode power saving level (between 0 and 5). 4380 * Level 0 is CAM (Continuously Aware Mode), 5 is for maximum power saving. 4381 */ 4382 int 4383 iwn_set_pslevel(struct iwn_softc *sc, int dtim, int level, int async) 4384 { 4385 const struct iwn_pmgt *pmgt; 4386 struct iwn_pmgt_cmd cmd; 4387 uint32_t max, skip_dtim; 4388 uint32_t tmp; 4389 int i; 4390 4391 /* Select which PS parameters to use. */ 4392 if (dtim <= 2) 4393 pmgt = &iwn_pmgt[0][level]; 4394 else if (dtim <= 10) 4395 pmgt = &iwn_pmgt[1][level]; 4396 else 4397 pmgt = &iwn_pmgt[2][level]; 4398 4399 memset(&cmd, 0, sizeof cmd); 4400 if (level != 0) /* not CAM */ 4401 cmd.flags |= htole16(IWN_PS_ALLOW_SLEEP); 4402 if (level == 5) 4403 cmd.flags |= htole16(IWN_PS_FAST_PD); 4404 /* Retrieve PCIe Active State Power Management (ASPM). */ 4405 tmp = pci_read_config(sc->sc_dev, sc->sc_cap_off + 0x10, 1); 4406 if (!(tmp & 0x1)) /* L0s Entry disabled. */ 4407 cmd.flags |= htole16(IWN_PS_PCI_PMGT); 4408 cmd.rxtimeout = htole32(pmgt->rxtimeout * 1024); 4409 cmd.txtimeout = htole32(pmgt->txtimeout * 1024); 4410 4411 if (dtim == 0) { 4412 dtim = 1; 4413 skip_dtim = 0; 4414 } else 4415 skip_dtim = pmgt->skip_dtim; 4416 if (skip_dtim != 0) { 4417 cmd.flags |= htole16(IWN_PS_SLEEP_OVER_DTIM); 4418 max = pmgt->intval[4]; 4419 if (max == (uint32_t)-1) 4420 max = dtim * (skip_dtim + 1); 4421 else if (max > dtim) 4422 max = (max / dtim) * dtim; 4423 } else 4424 max = dtim; 4425 for (i = 0; i < 5; i++) 4426 cmd.intval[i] = htole32(MIN(max, pmgt->intval[i])); 4427 4428 DPRINTF(sc, IWN_DEBUG_RESET, "setting power saving level to %d\n", 4429 level); 4430 return iwn_cmd(sc, IWN_CMD_SET_POWER_MODE, &cmd, sizeof cmd, async); 4431 } 4432 4433 int 4434 iwn_config(struct iwn_softc *sc) 4435 { 4436 const struct iwn_hal *hal = sc->sc_hal; 4437 struct ifnet *ifp = sc->sc_ifp; 4438 struct ieee80211com *ic = ifp->if_l2com; 4439 struct iwn_bluetooth bluetooth; 4440 uint32_t txmask; 4441 int error; 4442 uint16_t rxchain; 4443 4444 /* Configure valid TX chains for 5000 Series. */ 4445 if (sc->hw_type != IWN_HW_REV_TYPE_4965) { 4446 txmask = htole32(sc->txchainmask); 4447 DPRINTF(sc, IWN_DEBUG_RESET, 4448 "%s: configuring valid TX chains 0x%x\n", __func__, txmask); 4449 error = iwn_cmd(sc, IWN5000_CMD_TX_ANT_CONFIG, &txmask, 4450 sizeof txmask, 0); 4451 if (error != 0) { 4452 device_printf(sc->sc_dev, 4453 "%s: could not configure valid TX chains, " 4454 "error %d\n", __func__, error); 4455 return error; 4456 } 4457 } 4458 4459 /* Configure bluetooth coexistence. */ 4460 memset(&bluetooth, 0, sizeof bluetooth); 4461 bluetooth.flags = IWN_BT_COEX_MODE_4WIRE; 4462 bluetooth.lead_time = IWN_BT_LEAD_TIME_DEF; 4463 bluetooth.max_kill = IWN_BT_MAX_KILL_DEF; 4464 DPRINTF(sc, IWN_DEBUG_RESET, "%s: config bluetooth coexistence\n", 4465 __func__); 4466 error = iwn_cmd(sc, IWN_CMD_BT_COEX, &bluetooth, sizeof bluetooth, 0); 4467 if (error != 0) { 4468 device_printf(sc->sc_dev, 4469 "%s: could not configure bluetooth coexistence, error %d\n", 4470 __func__, error); 4471 return error; 4472 } 4473 4474 /* Set mode, channel, RX filter and enable RX. */ 4475 memset(&sc->rxon, 0, sizeof (struct iwn_rxon)); 4476 IEEE80211_ADDR_COPY(sc->rxon.myaddr, IF_LLADDR(ifp)); 4477 IEEE80211_ADDR_COPY(sc->rxon.wlap, IF_LLADDR(ifp)); 4478 sc->rxon.chan = ieee80211_chan2ieee(ic, ic->ic_curchan); 4479 sc->rxon.flags = htole32(IWN_RXON_TSF | IWN_RXON_CTS_TO_SELF); 4480 if (IEEE80211_IS_CHAN_2GHZ(ic->ic_curchan)) 4481 sc->rxon.flags |= htole32(IWN_RXON_AUTO | IWN_RXON_24GHZ); 4482 switch (ic->ic_opmode) { 4483 case IEEE80211_M_STA: 4484 sc->rxon.mode = IWN_MODE_STA; 4485 sc->rxon.filter = htole32(IWN_FILTER_MULTICAST); 4486 break; 4487 case IEEE80211_M_MONITOR: 4488 sc->rxon.mode = IWN_MODE_MONITOR; 4489 sc->rxon.filter = htole32(IWN_FILTER_MULTICAST | 4490 IWN_FILTER_CTL | IWN_FILTER_PROMISC); 4491 break; 4492 default: 4493 /* Should not get there. */ 4494 break; 4495 } 4496 sc->rxon.cck_mask = 0x0f; /* not yet negotiated */ 4497 sc->rxon.ofdm_mask = 0xff; /* not yet negotiated */ 4498 sc->rxon.ht_single_mask = 0xff; 4499 sc->rxon.ht_dual_mask = 0xff; 4500 sc->rxon.ht_triple_mask = 0xff; 4501 rxchain = 4502 IWN_RXCHAIN_VALID(sc->rxchainmask) | 4503 IWN_RXCHAIN_MIMO_COUNT(2) | 4504 IWN_RXCHAIN_IDLE_COUNT(2); 4505 sc->rxon.rxchain = htole16(rxchain); 4506 DPRINTF(sc, IWN_DEBUG_RESET, "%s: setting configuration\n", __func__); 4507 error = iwn_cmd(sc, IWN_CMD_RXON, &sc->rxon, hal->rxonsz, 0); 4508 if (error != 0) { 4509 device_printf(sc->sc_dev, 4510 "%s: RXON command failed\n", __func__); 4511 return error; 4512 } 4513 4514 error = iwn_add_broadcast_node(sc, 0); 4515 if (error != 0) { 4516 device_printf(sc->sc_dev, 4517 "%s: could not add broadcast node\n", __func__); 4518 return error; 4519 } 4520 4521 /* Configuration has changed, set TX power accordingly. */ 4522 error = hal->set_txpower(sc, 0); 4523 if (error != 0) { 4524 device_printf(sc->sc_dev, 4525 "%s: could not set TX power\n", __func__); 4526 return error; 4527 } 4528 4529 error = iwn_set_critical_temp(sc); 4530 if (error != 0) { 4531 device_printf(sc->sc_dev, 4532 "%s: ccould not set critical temperature\n", __func__); 4533 return error; 4534 } 4535 4536 /* Set power saving level to CAM during initialization. */ 4537 error = iwn_set_pslevel(sc, 0, 0, 0); 4538 if (error != 0) { 4539 device_printf(sc->sc_dev, 4540 "%s: could not set power saving level\n", __func__); 4541 return error; 4542 } 4543 return 0; 4544 } 4545 4546 int 4547 iwn_scan(struct iwn_softc *sc) 4548 { 4549 struct ifnet *ifp = sc->sc_ifp; 4550 struct ieee80211com *ic = ifp->if_l2com; 4551 struct ieee80211_scan_state *ss = ic->ic_scan; /*XXX*/ 4552 struct iwn_scan_hdr *hdr; 4553 struct iwn_cmd_data *tx; 4554 struct iwn_scan_essid *essid; 4555 struct iwn_scan_chan *chan; 4556 struct ieee80211_frame *wh; 4557 struct ieee80211_rateset *rs; 4558 struct ieee80211_channel *c; 4559 int buflen, error, nrates; 4560 uint16_t rxchain; 4561 uint8_t *buf, *frm, txant; 4562 4563 buf = malloc(IWN_SCAN_MAXSZ, M_DEVBUF, M_NOWAIT | M_ZERO); 4564 if (buf == NULL) { 4565 device_printf(sc->sc_dev, 4566 "%s: could not allocate buffer for scan command\n", 4567 __func__); 4568 return ENOMEM; 4569 } 4570 hdr = (struct iwn_scan_hdr *)buf; 4571 4572 /* 4573 * Move to the next channel if no frames are received within 10ms 4574 * after sending the probe request. 4575 */ 4576 hdr->quiet_time = htole16(10); /* timeout in milliseconds */ 4577 hdr->quiet_threshold = htole16(1); /* min # of packets */ 4578 4579 /* Select antennas for scanning. */ 4580 rxchain = 4581 IWN_RXCHAIN_VALID(sc->rxchainmask) | 4582 IWN_RXCHAIN_FORCE_MIMO_SEL(sc->rxchainmask) | 4583 IWN_RXCHAIN_DRIVER_FORCE; 4584 if (IEEE80211_IS_CHAN_A(ic->ic_curchan) && 4585 sc->hw_type == IWN_HW_REV_TYPE_4965) { 4586 /* Ant A must be avoided in 5GHz because of an HW bug. */ 4587 rxchain |= IWN_RXCHAIN_FORCE_SEL(IWN_ANT_BC); 4588 } else /* Use all available RX antennas. */ 4589 rxchain |= IWN_RXCHAIN_FORCE_SEL(sc->rxchainmask); 4590 hdr->rxchain = htole16(rxchain); 4591 hdr->filter = htole32(IWN_FILTER_MULTICAST | IWN_FILTER_BEACON); 4592 4593 tx = (struct iwn_cmd_data *)(hdr + 1); 4594 tx->flags = htole32(IWN_TX_AUTO_SEQ); 4595 tx->id = sc->sc_hal->broadcast_id; 4596 tx->lifetime = htole32(IWN_LIFETIME_INFINITE); 4597 4598 if (IEEE80211_IS_CHAN_A(ic->ic_curchan)) { 4599 /* Send probe requests at 6Mbps. */ 4600 tx->plcp = iwn_rates[IWN_RIDX_OFDM6].plcp; 4601 rs = &ic->ic_sup_rates[IEEE80211_MODE_11A]; 4602 } else { 4603 hdr->flags = htole32(IWN_RXON_24GHZ | IWN_RXON_AUTO); 4604 /* Send probe requests at 1Mbps. */ 4605 tx->plcp = iwn_rates[IWN_RIDX_CCK1].plcp; 4606 tx->rflags = IWN_RFLAG_CCK; 4607 rs = &ic->ic_sup_rates[IEEE80211_MODE_11G]; 4608 } 4609 /* Use the first valid TX antenna. */ 4610 txant = IWN_LSB(sc->txchainmask); 4611 tx->rflags |= IWN_RFLAG_ANT(txant); 4612 4613 essid = (struct iwn_scan_essid *)(tx + 1); 4614 if (ss->ss_ssid[0].len != 0) { 4615 essid[0].id = IEEE80211_ELEMID_SSID; 4616 essid[0].len = ss->ss_ssid[0].len; 4617 memcpy(essid[0].data, ss->ss_ssid[0].ssid, ss->ss_ssid[0].len); 4618 } 4619 4620 /* 4621 * Build a probe request frame. Most of the following code is a 4622 * copy & paste of what is done in net80211. 4623 */ 4624 wh = (struct ieee80211_frame *)(essid + 20); 4625 wh->i_fc[0] = IEEE80211_FC0_VERSION_0 | IEEE80211_FC0_TYPE_MGT | 4626 IEEE80211_FC0_SUBTYPE_PROBE_REQ; 4627 wh->i_fc[1] = IEEE80211_FC1_DIR_NODS; 4628 IEEE80211_ADDR_COPY(wh->i_addr1, ifp->if_broadcastaddr); 4629 IEEE80211_ADDR_COPY(wh->i_addr2, IF_LLADDR(ifp)); 4630 IEEE80211_ADDR_COPY(wh->i_addr3, ifp->if_broadcastaddr); 4631 *(uint16_t *)&wh->i_dur[0] = 0; /* filled by HW */ 4632 *(uint16_t *)&wh->i_seq[0] = 0; /* filled by HW */ 4633 4634 frm = (uint8_t *)(wh + 1); 4635 4636 /* Add SSID IE. */ 4637 *frm++ = IEEE80211_ELEMID_SSID; 4638 *frm++ = ss->ss_ssid[0].len; 4639 memcpy(frm, ss->ss_ssid[0].ssid, ss->ss_ssid[0].len); 4640 frm += ss->ss_ssid[0].len; 4641 4642 /* Add supported rates IE. */ 4643 *frm++ = IEEE80211_ELEMID_RATES; 4644 nrates = rs->rs_nrates; 4645 if (nrates > IEEE80211_RATE_SIZE) 4646 nrates = IEEE80211_RATE_SIZE; 4647 *frm++ = nrates; 4648 memcpy(frm, rs->rs_rates, nrates); 4649 frm += nrates; 4650 4651 /* Add supported xrates IE. */ 4652 if (rs->rs_nrates > IEEE80211_RATE_SIZE) { 4653 nrates = rs->rs_nrates - IEEE80211_RATE_SIZE; 4654 *frm++ = IEEE80211_ELEMID_XRATES; 4655 *frm++ = (uint8_t)nrates; 4656 memcpy(frm, rs->rs_rates + IEEE80211_RATE_SIZE, nrates); 4657 frm += nrates; 4658 } 4659 4660 /* Set length of probe request. */ 4661 tx->len = htole16(frm - (uint8_t *)wh); 4662 4663 c = ic->ic_curchan; 4664 chan = (struct iwn_scan_chan *)frm; 4665 chan->chan = htole16(ieee80211_chan2ieee(ic, c)); 4666 chan->flags = 0; 4667 if (ss->ss_nssid > 0) 4668 chan->flags |= htole32(IWN_CHAN_NPBREQS(1)); 4669 chan->dsp_gain = 0x6e; 4670 if (IEEE80211_IS_CHAN_5GHZ(c) && 4671 !(c->ic_flags & IEEE80211_CHAN_PASSIVE)) { 4672 chan->rf_gain = 0x3b; 4673 chan->active = htole16(24); 4674 chan->passive = htole16(110); 4675 chan->flags |= htole32(IWN_CHAN_ACTIVE); 4676 } else if (IEEE80211_IS_CHAN_5GHZ(c)) { 4677 chan->rf_gain = 0x3b; 4678 chan->active = htole16(24); 4679 if (sc->rxon.associd) 4680 chan->passive = htole16(78); 4681 else 4682 chan->passive = htole16(110); 4683 hdr->crc_threshold = htole16(1); 4684 } else if (!(c->ic_flags & IEEE80211_CHAN_PASSIVE)) { 4685 chan->rf_gain = 0x28; 4686 chan->active = htole16(36); 4687 chan->passive = htole16(120); 4688 chan->flags |= htole32(IWN_CHAN_ACTIVE); 4689 } else { 4690 chan->rf_gain = 0x28; 4691 chan->active = htole16(36); 4692 if (sc->rxon.associd) 4693 chan->passive = htole16(88); 4694 else 4695 chan->passive = htole16(120); 4696 hdr->crc_threshold = htole16(1); 4697 } 4698 4699 DPRINTF(sc, IWN_DEBUG_STATE, 4700 "%s: chan %u flags 0x%x rf_gain 0x%x " 4701 "dsp_gain 0x%x active 0x%x passive 0x%x\n", __func__, 4702 chan->chan, chan->flags, chan->rf_gain, chan->dsp_gain, 4703 chan->active, chan->passive); 4704 4705 hdr->nchan++; 4706 chan++; 4707 buflen = (uint8_t *)chan - buf; 4708 hdr->len = htole16(buflen); 4709 4710 DPRINTF(sc, IWN_DEBUG_STATE, "sending scan command nchan=%d\n", 4711 hdr->nchan); 4712 error = iwn_cmd(sc, IWN_CMD_SCAN, buf, buflen, 1); 4713 free(buf, M_DEVBUF); 4714 return error; 4715 } 4716 4717 int 4718 iwn_auth(struct iwn_softc *sc, struct ieee80211vap *vap) 4719 { 4720 const struct iwn_hal *hal = sc->sc_hal; 4721 struct ifnet *ifp = sc->sc_ifp; 4722 struct ieee80211com *ic = ifp->if_l2com; 4723 struct ieee80211_node *ni = vap->iv_bss; 4724 int error; 4725 4726 sc->calib.state = IWN_CALIB_STATE_INIT; 4727 4728 /* Update adapter configuration. */ 4729 IEEE80211_ADDR_COPY(sc->rxon.bssid, ni->ni_bssid); 4730 sc->rxon.chan = htole16(ieee80211_chan2ieee(ic, ni->ni_chan)); 4731 sc->rxon.flags = htole32(IWN_RXON_TSF | IWN_RXON_CTS_TO_SELF); 4732 if (IEEE80211_IS_CHAN_2GHZ(ni->ni_chan)) 4733 sc->rxon.flags |= htole32(IWN_RXON_AUTO | IWN_RXON_24GHZ); 4734 if (ic->ic_flags & IEEE80211_F_SHSLOT) 4735 sc->rxon.flags |= htole32(IWN_RXON_SHSLOT); 4736 if (ic->ic_flags & IEEE80211_F_SHPREAMBLE) 4737 sc->rxon.flags |= htole32(IWN_RXON_SHPREAMBLE); 4738 if (IEEE80211_IS_CHAN_A(ni->ni_chan)) { 4739 sc->rxon.cck_mask = 0; 4740 sc->rxon.ofdm_mask = 0x15; 4741 } else if (IEEE80211_IS_CHAN_B(ni->ni_chan)) { 4742 sc->rxon.cck_mask = 0x03; 4743 sc->rxon.ofdm_mask = 0; 4744 } else { 4745 /* XXX assume 802.11b/g */ 4746 sc->rxon.cck_mask = 0x0f; 4747 sc->rxon.ofdm_mask = 0x15; 4748 } 4749 DPRINTF(sc, IWN_DEBUG_STATE, 4750 "%s: config chan %d mode %d flags 0x%x cck 0x%x ofdm 0x%x " 4751 "ht_single 0x%x ht_dual 0x%x rxchain 0x%x " 4752 "myaddr %6D wlap %6D bssid %6D associd %d filter 0x%x\n", 4753 __func__, 4754 le16toh(sc->rxon.chan), sc->rxon.mode, le32toh(sc->rxon.flags), 4755 sc->rxon.cck_mask, sc->rxon.ofdm_mask, 4756 sc->rxon.ht_single_mask, sc->rxon.ht_dual_mask, 4757 le16toh(sc->rxon.rxchain), 4758 sc->rxon.myaddr, ":", sc->rxon.wlap, ":", sc->rxon.bssid, ":", 4759 le16toh(sc->rxon.associd), le32toh(sc->rxon.filter)); 4760 error = iwn_cmd(sc, IWN_CMD_RXON, &sc->rxon, hal->rxonsz, 1); 4761 if (error != 0) { 4762 device_printf(sc->sc_dev, 4763 "%s: RXON command failed, error %d\n", __func__, error); 4764 return error; 4765 } 4766 4767 /* Configuration has changed, set TX power accordingly. */ 4768 error = hal->set_txpower(sc, 1); 4769 if (error != 0) { 4770 device_printf(sc->sc_dev, 4771 "%s: could not set Tx power, error %d\n", __func__, error); 4772 return error; 4773 } 4774 /* 4775 * Reconfiguring RXON clears the firmware nodes table so we must 4776 * add the broadcast node again. 4777 */ 4778 error = iwn_add_broadcast_node(sc, 1); 4779 if (error != 0) { 4780 device_printf(sc->sc_dev, 4781 "%s: could not add broadcast node, error %d\n", 4782 __func__, error); 4783 return error; 4784 } 4785 return 0; 4786 } 4787 4788 /* 4789 * Configure the adapter for associated state. 4790 */ 4791 int 4792 iwn_run(struct iwn_softc *sc, struct ieee80211vap *vap) 4793 { 4794 #define MS(v,x) (((v) & x) >> x##_S) 4795 const struct iwn_hal *hal = sc->sc_hal; 4796 struct ifnet *ifp = sc->sc_ifp; 4797 struct ieee80211com *ic = ifp->if_l2com; 4798 struct ieee80211_node *ni = vap->iv_bss; 4799 struct iwn_node_info node; 4800 int error; 4801 4802 sc->calib.state = IWN_CALIB_STATE_INIT; 4803 4804 if (ic->ic_opmode == IEEE80211_M_MONITOR) { 4805 /* Link LED blinks while monitoring. */ 4806 iwn_set_led(sc, IWN_LED_LINK, 5, 5); 4807 return 0; 4808 } 4809 error = iwn_set_timing(sc, ni); 4810 if (error != 0) { 4811 device_printf(sc->sc_dev, 4812 "%s: could not set timing, error %d\n", __func__, error); 4813 return error; 4814 } 4815 4816 /* Update adapter configuration. */ 4817 IEEE80211_ADDR_COPY(sc->rxon.bssid, ni->ni_bssid); 4818 sc->rxon.chan = htole16(ieee80211_chan2ieee(ic, ni->ni_chan)); 4819 sc->rxon.associd = htole16(IEEE80211_AID(ni->ni_associd)); 4820 /* Short preamble and slot time are negotiated when associating. */ 4821 sc->rxon.flags &= ~htole32(IWN_RXON_SHPREAMBLE | IWN_RXON_SHSLOT); 4822 sc->rxon.flags |= htole32(IWN_RXON_TSF | IWN_RXON_CTS_TO_SELF); 4823 if (IEEE80211_IS_CHAN_2GHZ(ni->ni_chan)) 4824 sc->rxon.flags |= htole32(IWN_RXON_AUTO | IWN_RXON_24GHZ); 4825 else 4826 sc->rxon.flags &= ~htole32(IWN_RXON_AUTO | IWN_RXON_24GHZ); 4827 if (ic->ic_flags & IEEE80211_F_SHSLOT) 4828 sc->rxon.flags |= htole32(IWN_RXON_SHSLOT); 4829 if (ic->ic_flags & IEEE80211_F_SHPREAMBLE) 4830 sc->rxon.flags |= htole32(IWN_RXON_SHPREAMBLE); 4831 if (IEEE80211_IS_CHAN_A(ni->ni_chan)) { 4832 sc->rxon.cck_mask = 0; 4833 sc->rxon.ofdm_mask = 0x15; 4834 } else if (IEEE80211_IS_CHAN_B(ni->ni_chan)) { 4835 sc->rxon.cck_mask = 0x03; 4836 sc->rxon.ofdm_mask = 0; 4837 } else { 4838 /* XXX assume 802.11b/g */ 4839 sc->rxon.cck_mask = 0x0f; 4840 sc->rxon.ofdm_mask = 0x15; 4841 } 4842 #if 0 /* HT */ 4843 if (IEEE80211_IS_CHAN_HT(ni->ni_chan)) { 4844 sc->rxon.flags &= ~htole32(IWN_RXON_HT); 4845 if (IEEE80211_IS_CHAN_HT40U(ni->ni_chan)) 4846 sc->rxon.flags |= htole32(IWN_RXON_HT40U); 4847 else if (IEEE80211_IS_CHAN_HT40D(ni->ni_chan)) 4848 sc->rxon.flags |= htole32(IWN_RXON_HT40D); 4849 else 4850 sc->rxon.flags |= htole32(IWN_RXON_HT20); 4851 sc->rxon.rxchain = htole16( 4852 IWN_RXCHAIN_VALID(3) 4853 | IWN_RXCHAIN_MIMO_COUNT(3) 4854 | IWN_RXCHAIN_IDLE_COUNT(1) 4855 | IWN_RXCHAIN_MIMO_FORCE); 4856 4857 maxrxampdu = MS(ni->ni_htparam, IEEE80211_HTCAP_MAXRXAMPDU); 4858 ampdudensity = MS(ni->ni_htparam, IEEE80211_HTCAP_MPDUDENSITY); 4859 } else 4860 maxrxampdu = ampdudensity = 0; 4861 #endif 4862 sc->rxon.filter |= htole32(IWN_FILTER_BSS); 4863 4864 DPRINTF(sc, IWN_DEBUG_STATE, 4865 "%s: config chan %d mode %d flags 0x%x cck 0x%x ofdm 0x%x " 4866 "ht_single 0x%x ht_dual 0x%x rxchain 0x%x " 4867 "myaddr %6D wlap %6D bssid %6D associd %d filter 0x%x\n", 4868 __func__, 4869 le16toh(sc->rxon.chan), sc->rxon.mode, le32toh(sc->rxon.flags), 4870 sc->rxon.cck_mask, sc->rxon.ofdm_mask, 4871 sc->rxon.ht_single_mask, sc->rxon.ht_dual_mask, 4872 le16toh(sc->rxon.rxchain), 4873 sc->rxon.myaddr, ":", sc->rxon.wlap, ":", sc->rxon.bssid, ":", 4874 le16toh(sc->rxon.associd), le32toh(sc->rxon.filter)); 4875 error = iwn_cmd(sc, IWN_CMD_RXON, &sc->rxon, hal->rxonsz, 1); 4876 if (error != 0) { 4877 device_printf(sc->sc_dev, 4878 "%s: could not update configuration, error %d\n", 4879 __func__, error); 4880 return error; 4881 } 4882 4883 4884 /* Configuration has changed, set TX power accordingly. */ 4885 error = hal->set_txpower(sc, 1); 4886 if (error != 0) { 4887 device_printf(sc->sc_dev, 4888 "%s: could not set Tx power, error %d\n", __func__, error); 4889 return error; 4890 } 4891 4892 /* Add BSS node. */ 4893 memset(&node, 0, sizeof node); 4894 IEEE80211_ADDR_COPY(node.macaddr, ni->ni_macaddr); 4895 node.id = IWN_ID_BSS; 4896 #ifdef notyet 4897 node.htflags = htole32(IWN_AMDPU_SIZE_FACTOR(3) | 4898 IWN_AMDPU_DENSITY(5)); /* 2us */ 4899 #endif 4900 DPRINTF(sc, IWN_DEBUG_STATE, "%s: add BSS node, id %d htflags 0x%x\n", 4901 __func__, node.id, le32toh(node.htflags)); 4902 error = hal->add_node(sc, &node, 1); 4903 if (error != 0) { 4904 device_printf(sc->sc_dev, "could not add BSS node\n"); 4905 return error; 4906 } 4907 DPRINTF(sc, IWN_DEBUG_STATE, "setting link quality for node %d\n", 4908 node.id); 4909 error = iwn_set_link_quality(sc, node.id, 1); 4910 if (error != 0) { 4911 device_printf(sc->sc_dev, 4912 "%s: could not setup MRR for node %d, error %d\n", 4913 __func__, node.id, error); 4914 return error; 4915 } 4916 4917 error = iwn_init_sensitivity(sc); 4918 if (error != 0) { 4919 device_printf(sc->sc_dev, 4920 "%s: could not set sensitivity, error %d\n", 4921 __func__, error); 4922 return error; 4923 } 4924 4925 /* Start periodic calibration timer. */ 4926 sc->calib.state = IWN_CALIB_STATE_ASSOC; 4927 iwn_calib_reset(sc); 4928 4929 /* Link LED always on while associated. */ 4930 iwn_set_led(sc, IWN_LED_LINK, 0, 1); 4931 4932 return 0; 4933 #undef MS 4934 } 4935 4936 #if 0 /* HT */ 4937 /* 4938 * This function is called by upper layer when an ADDBA request is received 4939 * from another STA and before the ADDBA response is sent. 4940 */ 4941 int 4942 iwn_ampdu_rx_start(struct ieee80211com *ic, struct ieee80211_node *ni, 4943 uint8_t tid) 4944 { 4945 struct ieee80211_rx_ba *ba = &ni->ni_rx_ba[tid]; 4946 struct iwn_softc *sc = ic->ic_softc; 4947 struct iwn_node *wn = (void *)ni; 4948 struct iwn_node_info node; 4949 4950 memset(&node, 0, sizeof node); 4951 node.id = wn->id; 4952 node.control = IWN_NODE_UPDATE; 4953 node.flags = IWN_FLAG_SET_ADDBA; 4954 node.addba_tid = tid; 4955 node.addba_ssn = htole16(ba->ba_winstart); 4956 DPRINTF(sc, IWN_DEBUG_RECV, "ADDBA RA=%d TID=%d SSN=%d\n", 4957 wn->id, tid, ba->ba_winstart)); 4958 return sc->sc_hal->add_node(sc, &node, 1); 4959 } 4960 4961 /* 4962 * This function is called by upper layer on teardown of an HT-immediate 4963 * Block Ack agreement (eg. uppon receipt of a DELBA frame.) 4964 */ 4965 void 4966 iwn_ampdu_rx_stop(struct ieee80211com *ic, struct ieee80211_node *ni, 4967 uint8_t tid) 4968 { 4969 struct iwn_softc *sc = ic->ic_softc; 4970 struct iwn_node *wn = (void *)ni; 4971 struct iwn_node_info node; 4972 4973 memset(&node, 0, sizeof node); 4974 node.id = wn->id; 4975 node.control = IWN_NODE_UPDATE; 4976 node.flags = IWN_FLAG_SET_DELBA; 4977 node.delba_tid = tid; 4978 DPRINTF(sc, IWN_DEBUG_RECV, "DELBA RA=%d TID=%d\n", wn->id, tid); 4979 (void)sc->sc_hal->add_node(sc, &node, 1); 4980 } 4981 4982 /* 4983 * This function is called by upper layer when an ADDBA response is received 4984 * from another STA. 4985 */ 4986 int 4987 iwn_ampdu_tx_start(struct ieee80211com *ic, struct ieee80211_node *ni, 4988 uint8_t tid) 4989 { 4990 struct ieee80211_tx_ba *ba = &ni->ni_tx_ba[tid]; 4991 struct iwn_softc *sc = ic->ic_softc; 4992 const struct iwn_hal *hal = sc->sc_hal; 4993 struct iwn_node *wn = (void *)ni; 4994 struct iwn_node_info node; 4995 int error; 4996 4997 /* Enable TX for the specified RA/TID. */ 4998 wn->disable_tid &= ~(1 << tid); 4999 memset(&node, 0, sizeof node); 5000 node.id = wn->id; 5001 node.control = IWN_NODE_UPDATE; 5002 node.flags = IWN_FLAG_SET_DISABLE_TID; 5003 node.disable_tid = htole16(wn->disable_tid); 5004 error = hal->add_node(sc, &node, 1); 5005 if (error != 0) 5006 return error; 5007 5008 if ((error = iwn_nic_lock(sc)) != 0) 5009 return error; 5010 hal->ampdu_tx_start(sc, ni, tid, ba->ba_winstart); 5011 iwn_nic_unlock(sc); 5012 return 0; 5013 } 5014 5015 void 5016 iwn_ampdu_tx_stop(struct ieee80211com *ic, struct ieee80211_node *ni, 5017 uint8_t tid) 5018 { 5019 struct ieee80211_tx_ba *ba = &ni->ni_tx_ba[tid]; 5020 struct iwn_softc *sc = ic->ic_softc; 5021 int error; 5022 5023 error = iwn_nic_lock(sc); 5024 if (error != 0) 5025 return; 5026 sc->sc_hal->ampdu_tx_stop(sc, tid, ba->ba_winstart); 5027 iwn_nic_unlock(sc); 5028 } 5029 5030 void 5031 iwn4965_ampdu_tx_start(struct iwn_softc *sc, struct ieee80211_node *ni, 5032 uint8_t tid, uint16_t ssn) 5033 { 5034 struct iwn_node *wn = (void *)ni; 5035 int qid = 7 + tid; 5036 5037 /* Stop TX scheduler while we're changing its configuration. */ 5038 iwn_prph_write(sc, IWN4965_SCHED_QUEUE_STATUS(qid), 5039 IWN4965_TXQ_STATUS_CHGACT); 5040 5041 /* Assign RA/TID translation to the queue. */ 5042 iwn_mem_write_2(sc, sc->sched_base + IWN4965_SCHED_TRANS_TBL(qid), 5043 wn->id << 4 | tid); 5044 5045 /* Enable chain-building mode for the queue. */ 5046 iwn_prph_setbits(sc, IWN4965_SCHED_QCHAIN_SEL, 1 << qid); 5047 5048 /* Set starting sequence number from the ADDBA request. */ 5049 IWN_WRITE(sc, IWN_HBUS_TARG_WRPTR, qid << 8 | (ssn & 0xff)); 5050 iwn_prph_write(sc, IWN4965_SCHED_QUEUE_RDPTR(qid), ssn); 5051 5052 /* Set scheduler window size. */ 5053 iwn_mem_write(sc, sc->sched_base + IWN4965_SCHED_QUEUE_OFFSET(qid), 5054 IWN_SCHED_WINSZ); 5055 /* Set scheduler frame limit. */ 5056 iwn_mem_write(sc, sc->sched_base + IWN4965_SCHED_QUEUE_OFFSET(qid) + 4, 5057 IWN_SCHED_LIMIT << 16); 5058 5059 /* Enable interrupts for the queue. */ 5060 iwn_prph_setbits(sc, IWN4965_SCHED_INTR_MASK, 1 << qid); 5061 5062 /* Mark the queue as active. */ 5063 iwn_prph_write(sc, IWN4965_SCHED_QUEUE_STATUS(qid), 5064 IWN4965_TXQ_STATUS_ACTIVE | IWN4965_TXQ_STATUS_AGGR_ENA | 5065 iwn_tid2fifo[tid] << 1); 5066 } 5067 5068 void 5069 iwn4965_ampdu_tx_stop(struct iwn_softc *sc, uint8_t tid, uint16_t ssn) 5070 { 5071 int qid = 7 + tid; 5072 5073 /* Stop TX scheduler while we're changing its configuration. */ 5074 iwn_prph_write(sc, IWN4965_SCHED_QUEUE_STATUS(qid), 5075 IWN4965_TXQ_STATUS_CHGACT); 5076 5077 /* Set starting sequence number from the ADDBA request. */ 5078 IWN_WRITE(sc, IWN_HBUS_TARG_WRPTR, qid << 8 | (ssn & 0xff)); 5079 iwn_prph_write(sc, IWN4965_SCHED_QUEUE_RDPTR(qid), ssn); 5080 5081 /* Disable interrupts for the queue. */ 5082 iwn_prph_clrbits(sc, IWN4965_SCHED_INTR_MASK, 1 << qid); 5083 5084 /* Mark the queue as inactive. */ 5085 iwn_prph_write(sc, IWN4965_SCHED_QUEUE_STATUS(qid), 5086 IWN4965_TXQ_STATUS_INACTIVE | iwn_tid2fifo[tid] << 1); 5087 } 5088 5089 void 5090 iwn5000_ampdu_tx_start(struct iwn_softc *sc, struct ieee80211_node *ni, 5091 uint8_t tid, uint16_t ssn) 5092 { 5093 struct iwn_node *wn = (void *)ni; 5094 int qid = 10 + tid; 5095 5096 /* Stop TX scheduler while we're changing its configuration. */ 5097 iwn_prph_write(sc, IWN5000_SCHED_QUEUE_STATUS(qid), 5098 IWN5000_TXQ_STATUS_CHGACT); 5099 5100 /* Assign RA/TID translation to the queue. */ 5101 iwn_mem_write_2(sc, sc->sched_base + IWN5000_SCHED_TRANS_TBL(qid), 5102 wn->id << 4 | tid); 5103 5104 /* Enable chain-building mode for the queue. */ 5105 iwn_prph_setbits(sc, IWN5000_SCHED_QCHAIN_SEL, 1 << qid); 5106 5107 /* Enable aggregation for the queue. */ 5108 iwn_prph_setbits(sc, IWN5000_SCHED_AGGR_SEL, 1 << qid); 5109 5110 /* Set starting sequence number from the ADDBA request. */ 5111 IWN_WRITE(sc, IWN_HBUS_TARG_WRPTR, qid << 8 | (ssn & 0xff)); 5112 iwn_prph_write(sc, IWN5000_SCHED_QUEUE_RDPTR(qid), ssn); 5113 5114 /* Set scheduler window size and frame limit. */ 5115 iwn_mem_write(sc, sc->sched_base + IWN5000_SCHED_QUEUE_OFFSET(qid) + 4, 5116 IWN_SCHED_LIMIT << 16 | IWN_SCHED_WINSZ); 5117 5118 /* Enable interrupts for the queue. */ 5119 iwn_prph_setbits(sc, IWN5000_SCHED_INTR_MASK, 1 << qid); 5120 5121 /* Mark the queue as active. */ 5122 iwn_prph_write(sc, IWN5000_SCHED_QUEUE_STATUS(qid), 5123 IWN5000_TXQ_STATUS_ACTIVE | iwn_tid2fifo[tid]); 5124 } 5125 5126 void 5127 iwn5000_ampdu_tx_stop(struct iwn_softc *sc, uint8_t tid, uint16_t ssn) 5128 { 5129 int qid = 10 + tid; 5130 5131 /* Stop TX scheduler while we're changing its configuration. */ 5132 iwn_prph_write(sc, IWN5000_SCHED_QUEUE_STATUS(qid), 5133 IWN5000_TXQ_STATUS_CHGACT); 5134 5135 /* Disable aggregation for the queue. */ 5136 iwn_prph_clrbits(sc, IWN5000_SCHED_AGGR_SEL, 1 << qid); 5137 5138 /* Set starting sequence number from the ADDBA request. */ 5139 IWN_WRITE(sc, IWN_HBUS_TARG_WRPTR, qid << 8 | (ssn & 0xff)); 5140 iwn_prph_write(sc, IWN5000_SCHED_QUEUE_RDPTR(qid), ssn); 5141 5142 /* Disable interrupts for the queue. */ 5143 iwn_prph_clrbits(sc, IWN5000_SCHED_INTR_MASK, 1 << qid); 5144 5145 /* Mark the queue as inactive. */ 5146 iwn_prph_write(sc, IWN5000_SCHED_QUEUE_STATUS(qid), 5147 IWN5000_TXQ_STATUS_INACTIVE | iwn_tid2fifo[tid]); 5148 } 5149 #endif 5150 5151 /* 5152 * Query calibration tables from the initialization firmware. We do this 5153 * only once at first boot. Called from a process context. 5154 */ 5155 int 5156 iwn5000_query_calibration(struct iwn_softc *sc) 5157 { 5158 struct iwn5000_calib_config cmd; 5159 int error; 5160 5161 memset(&cmd, 0, sizeof cmd); 5162 cmd.ucode.once.enable = 0xffffffff; 5163 cmd.ucode.once.start = 0xffffffff; 5164 cmd.ucode.once.send = 0xffffffff; 5165 cmd.ucode.flags = 0xffffffff; 5166 DPRINTF(sc, IWN_DEBUG_CALIBRATE, "%s: sending calibration query\n", 5167 __func__); 5168 error = iwn_cmd(sc, IWN5000_CMD_CALIB_CONFIG, &cmd, sizeof cmd, 0); 5169 if (error != 0) 5170 return error; 5171 5172 /* Wait at most two seconds for calibration to complete. */ 5173 if (!(sc->sc_flags & IWN_FLAG_CALIB_DONE)) 5174 error = msleep(sc, &sc->sc_mtx, PCATCH, "iwninit", 2 * hz); 5175 return error; 5176 } 5177 5178 /* 5179 * Send calibration results to the runtime firmware. These results were 5180 * obtained on first boot from the initialization firmware. 5181 */ 5182 int 5183 iwn5000_send_calibration(struct iwn_softc *sc) 5184 { 5185 int idx, error; 5186 5187 for (idx = 0; idx < 5; idx++) { 5188 if (sc->calibcmd[idx].buf == NULL) 5189 continue; /* No results available. */ 5190 DPRINTF(sc, IWN_DEBUG_CALIBRATE, 5191 "send calibration result idx=%d len=%d\n", 5192 idx, sc->calibcmd[idx].len); 5193 error = iwn_cmd(sc, IWN_CMD_PHY_CALIB, sc->calibcmd[idx].buf, 5194 sc->calibcmd[idx].len, 0); 5195 if (error != 0) { 5196 device_printf(sc->sc_dev, 5197 "%s: could not send calibration result, error %d\n", 5198 __func__, error); 5199 return error; 5200 } 5201 } 5202 return 0; 5203 } 5204 5205 int 5206 iwn5000_send_wimax_coex(struct iwn_softc *sc) 5207 { 5208 struct iwn5000_wimax_coex wimax; 5209 5210 #ifdef notyet 5211 if (sc->hw_type == IWN_HW_REV_TYPE_6050) { 5212 /* Enable WiMAX coexistence for combo adapters. */ 5213 wimax.flags = 5214 IWN_WIMAX_COEX_ASSOC_WA_UNMASK | 5215 IWN_WIMAX_COEX_UNASSOC_WA_UNMASK | 5216 IWN_WIMAX_COEX_STA_TABLE_VALID | 5217 IWN_WIMAX_COEX_ENABLE; 5218 memcpy(wimax.events, iwn6050_wimax_events, 5219 sizeof iwn6050_wimax_events); 5220 } else 5221 #endif 5222 { 5223 /* Disable WiMAX coexistence. */ 5224 wimax.flags = 0; 5225 memset(wimax.events, 0, sizeof wimax.events); 5226 } 5227 DPRINTF(sc, IWN_DEBUG_RESET, "%s: Configuring WiMAX coexistence\n", 5228 __func__); 5229 return iwn_cmd(sc, IWN5000_CMD_WIMAX_COEX, &wimax, sizeof wimax, 0); 5230 } 5231 5232 /* 5233 * This function is called after the runtime firmware notifies us of its 5234 * readiness (called in a process context.) 5235 */ 5236 int 5237 iwn4965_post_alive(struct iwn_softc *sc) 5238 { 5239 int error, qid; 5240 5241 if ((error = iwn_nic_lock(sc)) != 0) 5242 return error; 5243 5244 /* Clear TX scheduler state in SRAM. */ 5245 sc->sched_base = iwn_prph_read(sc, IWN_SCHED_SRAM_ADDR); 5246 iwn_mem_set_region_4(sc, sc->sched_base + IWN4965_SCHED_CTX_OFF, 0, 5247 IWN4965_SCHED_CTX_LEN / sizeof (uint32_t)); 5248 5249 /* Set physical address of TX scheduler rings (1KB aligned.) */ 5250 iwn_prph_write(sc, IWN4965_SCHED_DRAM_ADDR, sc->sched_dma.paddr >> 10); 5251 5252 IWN_SETBITS(sc, IWN_FH_TX_CHICKEN, IWN_FH_TX_CHICKEN_SCHED_RETRY); 5253 5254 /* Disable chain mode for all our 16 queues. */ 5255 iwn_prph_write(sc, IWN4965_SCHED_QCHAIN_SEL, 0); 5256 5257 for (qid = 0; qid < IWN4965_NTXQUEUES; qid++) { 5258 iwn_prph_write(sc, IWN4965_SCHED_QUEUE_RDPTR(qid), 0); 5259 IWN_WRITE(sc, IWN_HBUS_TARG_WRPTR, qid << 8 | 0); 5260 5261 /* Set scheduler window size. */ 5262 iwn_mem_write(sc, sc->sched_base + 5263 IWN4965_SCHED_QUEUE_OFFSET(qid), IWN_SCHED_WINSZ); 5264 /* Set scheduler frame limit. */ 5265 iwn_mem_write(sc, sc->sched_base + 5266 IWN4965_SCHED_QUEUE_OFFSET(qid) + 4, 5267 IWN_SCHED_LIMIT << 16); 5268 } 5269 5270 /* Enable interrupts for all our 16 queues. */ 5271 iwn_prph_write(sc, IWN4965_SCHED_INTR_MASK, 0xffff); 5272 /* Identify TX FIFO rings (0-7). */ 5273 iwn_prph_write(sc, IWN4965_SCHED_TXFACT, 0xff); 5274 5275 /* Mark TX rings (4 EDCA + cmd + 2 HCCA) as active. */ 5276 for (qid = 0; qid < 7; qid++) { 5277 static uint8_t qid2fifo[] = { 3, 2, 1, 0, 4, 5, 6 }; 5278 iwn_prph_write(sc, IWN4965_SCHED_QUEUE_STATUS(qid), 5279 IWN4965_TXQ_STATUS_ACTIVE | qid2fifo[qid] << 1); 5280 } 5281 iwn_nic_unlock(sc); 5282 return 0; 5283 } 5284 5285 /* 5286 * This function is called after the initialization or runtime firmware 5287 * notifies us of its readiness (called in a process context.) 5288 */ 5289 int 5290 iwn5000_post_alive(struct iwn_softc *sc) 5291 { 5292 int error, qid; 5293 5294 /* Switch to using ICT interrupt mode. */ 5295 iwn5000_ict_reset(sc); 5296 5297 error = iwn_nic_lock(sc); 5298 if (error != 0) 5299 return error; 5300 5301 /* Clear TX scheduler state in SRAM. */ 5302 sc->sched_base = iwn_prph_read(sc, IWN_SCHED_SRAM_ADDR); 5303 iwn_mem_set_region_4(sc, sc->sched_base + IWN5000_SCHED_CTX_OFF, 0, 5304 IWN5000_SCHED_CTX_LEN / sizeof (uint32_t)); 5305 5306 /* Set physical address of TX scheduler rings (1KB aligned.) */ 5307 iwn_prph_write(sc, IWN5000_SCHED_DRAM_ADDR, sc->sched_dma.paddr >> 10); 5308 5309 IWN_SETBITS(sc, IWN_FH_TX_CHICKEN, IWN_FH_TX_CHICKEN_SCHED_RETRY); 5310 5311 /* Enable chain mode for all queues, except command queue. */ 5312 iwn_prph_write(sc, IWN5000_SCHED_QCHAIN_SEL, 0xfffef); 5313 iwn_prph_write(sc, IWN5000_SCHED_AGGR_SEL, 0); 5314 5315 for (qid = 0; qid < IWN5000_NTXQUEUES; qid++) { 5316 iwn_prph_write(sc, IWN5000_SCHED_QUEUE_RDPTR(qid), 0); 5317 IWN_WRITE(sc, IWN_HBUS_TARG_WRPTR, qid << 8 | 0); 5318 5319 iwn_mem_write(sc, sc->sched_base + 5320 IWN5000_SCHED_QUEUE_OFFSET(qid), 0); 5321 /* Set scheduler window size and frame limit. */ 5322 iwn_mem_write(sc, sc->sched_base + 5323 IWN5000_SCHED_QUEUE_OFFSET(qid) + 4, 5324 IWN_SCHED_LIMIT << 16 | IWN_SCHED_WINSZ); 5325 } 5326 5327 /* Enable interrupts for all our 20 queues. */ 5328 iwn_prph_write(sc, IWN5000_SCHED_INTR_MASK, 0xfffff); 5329 /* Identify TX FIFO rings (0-7). */ 5330 iwn_prph_write(sc, IWN5000_SCHED_TXFACT, 0xff); 5331 5332 /* Mark TX rings (4 EDCA + cmd + 2 HCCA) as active. */ 5333 for (qid = 0; qid < 7; qid++) { 5334 static uint8_t qid2fifo[] = { 3, 2, 1, 0, 7, 5, 6 }; 5335 iwn_prph_write(sc, IWN5000_SCHED_QUEUE_STATUS(qid), 5336 IWN5000_TXQ_STATUS_ACTIVE | qid2fifo[qid]); 5337 } 5338 iwn_nic_unlock(sc); 5339 5340 /* Configure WiMAX coexistence for combo adapters. */ 5341 error = iwn5000_send_wimax_coex(sc); 5342 if (error != 0) { 5343 device_printf(sc->sc_dev, 5344 "%s: could not configure WiMAX coexistence, error %d\n", 5345 __func__, error); 5346 return error; 5347 } 5348 if (sc->hw_type != IWN_HW_REV_TYPE_5150) { 5349 struct iwn5000_phy_calib_crystal cmd; 5350 5351 /* Perform crystal calibration. */ 5352 memset(&cmd, 0, sizeof cmd); 5353 cmd.code = IWN5000_PHY_CALIB_CRYSTAL; 5354 cmd.ngroups = 1; 5355 cmd.isvalid = 1; 5356 cmd.cap_pin[0] = le32toh(sc->eeprom_crystal) & 0xff; 5357 cmd.cap_pin[1] = (le32toh(sc->eeprom_crystal) >> 16) & 0xff; 5358 DPRINTF(sc, IWN_DEBUG_CALIBRATE, 5359 "sending crystal calibration %d, %d\n", 5360 cmd.cap_pin[0], cmd.cap_pin[1]); 5361 error = iwn_cmd(sc, IWN_CMD_PHY_CALIB, &cmd, sizeof cmd, 0); 5362 if (error != 0) { 5363 device_printf(sc->sc_dev, 5364 "%s: crystal calibration failed, error %d\n", 5365 __func__, error); 5366 return error; 5367 } 5368 } 5369 if (!(sc->sc_flags & IWN_FLAG_CALIB_DONE)) { 5370 /* Query calibration from the initialization firmware. */ 5371 error = iwn5000_query_calibration(sc); 5372 if (error != 0) { 5373 device_printf(sc->sc_dev, 5374 "%s: could not query calibration, error %d\n", 5375 __func__, error); 5376 return error; 5377 } 5378 /* 5379 * We have the calibration results now, reboot with the 5380 * runtime firmware (call ourselves recursively!) 5381 */ 5382 iwn_hw_stop(sc); 5383 error = iwn_hw_init(sc); 5384 } else { 5385 /* Send calibration results to runtime firmware. */ 5386 error = iwn5000_send_calibration(sc); 5387 } 5388 return error; 5389 } 5390 5391 /* 5392 * The firmware boot code is small and is intended to be copied directly into 5393 * the NIC internal memory (no DMA transfer.) 5394 */ 5395 int 5396 iwn4965_load_bootcode(struct iwn_softc *sc, const uint8_t *ucode, int size) 5397 { 5398 int error, ntries; 5399 5400 size /= sizeof (uint32_t); 5401 5402 error = iwn_nic_lock(sc); 5403 if (error != 0) 5404 return error; 5405 5406 /* Copy microcode image into NIC memory. */ 5407 iwn_prph_write_region_4(sc, IWN_BSM_SRAM_BASE, 5408 (const uint32_t *)ucode, size); 5409 5410 iwn_prph_write(sc, IWN_BSM_WR_MEM_SRC, 0); 5411 iwn_prph_write(sc, IWN_BSM_WR_MEM_DST, IWN_FW_TEXT_BASE); 5412 iwn_prph_write(sc, IWN_BSM_WR_DWCOUNT, size); 5413 5414 /* Start boot load now. */ 5415 iwn_prph_write(sc, IWN_BSM_WR_CTRL, IWN_BSM_WR_CTRL_START); 5416 5417 /* Wait for transfer to complete. */ 5418 for (ntries = 0; ntries < 1000; ntries++) { 5419 if (!(iwn_prph_read(sc, IWN_BSM_WR_CTRL) & 5420 IWN_BSM_WR_CTRL_START)) 5421 break; 5422 DELAY(10); 5423 } 5424 if (ntries == 1000) { 5425 device_printf(sc->sc_dev, "%s: could not load boot firmware\n", 5426 __func__); 5427 iwn_nic_unlock(sc); 5428 return ETIMEDOUT; 5429 } 5430 5431 /* Enable boot after power up. */ 5432 iwn_prph_write(sc, IWN_BSM_WR_CTRL, IWN_BSM_WR_CTRL_START_EN); 5433 5434 iwn_nic_unlock(sc); 5435 return 0; 5436 } 5437 5438 int 5439 iwn4965_load_firmware(struct iwn_softc *sc) 5440 { 5441 struct iwn_fw_info *fw = &sc->fw; 5442 struct iwn_dma_info *dma = &sc->fw_dma; 5443 int error; 5444 5445 /* Copy initialization sections into pre-allocated DMA-safe memory. */ 5446 memcpy(dma->vaddr, fw->init.data, fw->init.datasz); 5447 bus_dmamap_sync(sc->fw_dma.tag, dma->map, BUS_DMASYNC_PREWRITE); 5448 memcpy(dma->vaddr + IWN4965_FW_DATA_MAXSZ, 5449 fw->init.text, fw->init.textsz); 5450 bus_dmamap_sync(sc->fw_dma.tag, dma->map, BUS_DMASYNC_PREWRITE); 5451 5452 /* Tell adapter where to find initialization sections. */ 5453 error = iwn_nic_lock(sc); 5454 if (error != 0) 5455 return error; 5456 iwn_prph_write(sc, IWN_BSM_DRAM_DATA_ADDR, dma->paddr >> 4); 5457 iwn_prph_write(sc, IWN_BSM_DRAM_DATA_SIZE, fw->init.datasz); 5458 iwn_prph_write(sc, IWN_BSM_DRAM_TEXT_ADDR, 5459 (dma->paddr + IWN4965_FW_DATA_MAXSZ) >> 4); 5460 iwn_prph_write(sc, IWN_BSM_DRAM_TEXT_SIZE, fw->init.textsz); 5461 iwn_nic_unlock(sc); 5462 5463 /* Load firmware boot code. */ 5464 error = iwn4965_load_bootcode(sc, fw->boot.text, fw->boot.textsz); 5465 if (error != 0) { 5466 device_printf(sc->sc_dev, "%s: could not load boot firmware\n", 5467 __func__); 5468 return error; 5469 } 5470 /* Now press "execute". */ 5471 IWN_WRITE(sc, IWN_RESET, 0); 5472 5473 /* Wait at most one second for first alive notification. */ 5474 error = msleep(sc, &sc->sc_mtx, PCATCH, "iwninit", hz); 5475 if (error) { 5476 device_printf(sc->sc_dev, 5477 "%s: timeout waiting for adapter to initialize, error %d\n", 5478 __func__, error); 5479 return error; 5480 } 5481 5482 /* Retrieve current temperature for initial TX power calibration. */ 5483 sc->rawtemp = sc->ucode_info.temp[3].chan20MHz; 5484 sc->temp = iwn4965_get_temperature(sc); 5485 5486 /* Copy runtime sections into pre-allocated DMA-safe memory. */ 5487 memcpy(dma->vaddr, fw->main.data, fw->main.datasz); 5488 bus_dmamap_sync(sc->fw_dma.tag, dma->map, BUS_DMASYNC_PREWRITE); 5489 memcpy(dma->vaddr + IWN4965_FW_DATA_MAXSZ, 5490 fw->main.text, fw->main.textsz); 5491 bus_dmamap_sync(sc->fw_dma.tag, dma->map, BUS_DMASYNC_PREWRITE); 5492 5493 /* Tell adapter where to find runtime sections. */ 5494 error = iwn_nic_lock(sc); 5495 if (error != 0) 5496 return error; 5497 5498 iwn_prph_write(sc, IWN_BSM_DRAM_DATA_ADDR, dma->paddr >> 4); 5499 iwn_prph_write(sc, IWN_BSM_DRAM_DATA_SIZE, fw->main.datasz); 5500 iwn_prph_write(sc, IWN_BSM_DRAM_TEXT_ADDR, 5501 (dma->paddr + IWN4965_FW_DATA_MAXSZ) >> 4); 5502 iwn_prph_write(sc, IWN_BSM_DRAM_TEXT_SIZE, 5503 IWN_FW_UPDATED | fw->main.textsz); 5504 iwn_nic_unlock(sc); 5505 5506 return 0; 5507 } 5508 5509 int 5510 iwn5000_load_firmware_section(struct iwn_softc *sc, uint32_t dst, 5511 const uint8_t *section, int size) 5512 { 5513 struct iwn_dma_info *dma = &sc->fw_dma; 5514 int error; 5515 5516 /* Copy firmware section into pre-allocated DMA-safe memory. */ 5517 memcpy(dma->vaddr, section, size); 5518 bus_dmamap_sync(sc->fw_dma.tag, dma->map, BUS_DMASYNC_PREWRITE); 5519 5520 error = iwn_nic_lock(sc); 5521 if (error != 0) 5522 return error; 5523 5524 IWN_WRITE(sc, IWN_FH_TX_CONFIG(IWN_SRVC_DMACHNL), 5525 IWN_FH_TX_CONFIG_DMA_PAUSE); 5526 5527 IWN_WRITE(sc, IWN_FH_SRAM_ADDR(IWN_SRVC_DMACHNL), dst); 5528 IWN_WRITE(sc, IWN_FH_TFBD_CTRL0(IWN_SRVC_DMACHNL), 5529 IWN_LOADDR(dma->paddr)); 5530 IWN_WRITE(sc, IWN_FH_TFBD_CTRL1(IWN_SRVC_DMACHNL), 5531 IWN_HIADDR(dma->paddr) << 28 | size); 5532 IWN_WRITE(sc, IWN_FH_TXBUF_STATUS(IWN_SRVC_DMACHNL), 5533 IWN_FH_TXBUF_STATUS_TBNUM(1) | 5534 IWN_FH_TXBUF_STATUS_TBIDX(1) | 5535 IWN_FH_TXBUF_STATUS_TFBD_VALID); 5536 5537 /* Kick Flow Handler to start DMA transfer. */ 5538 IWN_WRITE(sc, IWN_FH_TX_CONFIG(IWN_SRVC_DMACHNL), 5539 IWN_FH_TX_CONFIG_DMA_ENA | IWN_FH_TX_CONFIG_CIRQ_HOST_ENDTFD); 5540 5541 iwn_nic_unlock(sc); 5542 5543 /* Wait at most five seconds for FH DMA transfer to complete. */ 5544 return msleep(sc, &sc->sc_mtx, PCATCH, "iwninit", hz); 5545 } 5546 5547 int 5548 iwn5000_load_firmware(struct iwn_softc *sc) 5549 { 5550 struct iwn_fw_part *fw; 5551 int error; 5552 5553 /* Load the initialization firmware on first boot only. */ 5554 fw = (sc->sc_flags & IWN_FLAG_CALIB_DONE) ? 5555 &sc->fw.main : &sc->fw.init; 5556 5557 error = iwn5000_load_firmware_section(sc, IWN_FW_TEXT_BASE, 5558 fw->text, fw->textsz); 5559 if (error != 0) { 5560 device_printf(sc->sc_dev, 5561 "%s: could not load firmware %s section, error %d\n", 5562 __func__, ".text", error); 5563 return error; 5564 } 5565 error = iwn5000_load_firmware_section(sc, IWN_FW_DATA_BASE, 5566 fw->data, fw->datasz); 5567 if (error != 0) { 5568 device_printf(sc->sc_dev, 5569 "%s: could not load firmware %s section, error %d\n", 5570 __func__, ".data", error); 5571 return error; 5572 } 5573 5574 /* Now press "execute". */ 5575 IWN_WRITE(sc, IWN_RESET, 0); 5576 return 0; 5577 } 5578 5579 int 5580 iwn_read_firmware(struct iwn_softc *sc) 5581 { 5582 const struct iwn_hal *hal = sc->sc_hal; 5583 struct iwn_fw_info *fw = &sc->fw; 5584 const uint32_t *ptr; 5585 uint32_t rev; 5586 size_t size; 5587 5588 IWN_UNLOCK(sc); 5589 5590 /* Read firmware image from filesystem. */ 5591 sc->fw_fp = firmware_get(sc->fwname); 5592 if (sc->fw_fp == NULL) { 5593 device_printf(sc->sc_dev, 5594 "%s: could not load firmare image \"%s\"\n", __func__, 5595 sc->fwname); 5596 IWN_LOCK(sc); 5597 return EINVAL; 5598 } 5599 IWN_LOCK(sc); 5600 5601 size = sc->fw_fp->datasize; 5602 if (size < 28) { 5603 device_printf(sc->sc_dev, 5604 "%s: truncated firmware header: %zu bytes\n", 5605 __func__, size); 5606 return EINVAL; 5607 } 5608 5609 /* Process firmware header. */ 5610 ptr = (const uint32_t *)sc->fw_fp->data; 5611 rev = le32toh(*ptr++); 5612 /* Check firmware API version. */ 5613 if (IWN_FW_API(rev) <= 1) { 5614 device_printf(sc->sc_dev, 5615 "%s: bad firmware, need API version >=2\n", __func__); 5616 return EINVAL; 5617 } 5618 if (IWN_FW_API(rev) >= 3) { 5619 /* Skip build number (version 2 header). */ 5620 size -= 4; 5621 ptr++; 5622 } 5623 fw->main.textsz = le32toh(*ptr++); 5624 fw->main.datasz = le32toh(*ptr++); 5625 fw->init.textsz = le32toh(*ptr++); 5626 fw->init.datasz = le32toh(*ptr++); 5627 fw->boot.textsz = le32toh(*ptr++); 5628 size -= 24; 5629 5630 /* Sanity-check firmware header. */ 5631 if (fw->main.textsz > hal->fw_text_maxsz || 5632 fw->main.datasz > hal->fw_data_maxsz || 5633 fw->init.textsz > hal->fw_text_maxsz || 5634 fw->init.datasz > hal->fw_data_maxsz || 5635 fw->boot.textsz > IWN_FW_BOOT_TEXT_MAXSZ || 5636 (fw->boot.textsz & 3) != 0) { 5637 device_printf(sc->sc_dev, "%s: invalid firmware header\n", 5638 __func__); 5639 return EINVAL; 5640 } 5641 5642 /* Check that all firmware sections fit. */ 5643 if (fw->main.textsz + fw->main.datasz + fw->init.textsz + 5644 fw->init.datasz + fw->boot.textsz > size) { 5645 device_printf(sc->sc_dev, 5646 "%s: firmware file too short: %zu bytes\n", 5647 __func__, size); 5648 return EINVAL; 5649 } 5650 5651 /* Get pointers to firmware sections. */ 5652 fw->main.text = (const uint8_t *)ptr; 5653 fw->main.data = fw->main.text + fw->main.textsz; 5654 fw->init.text = fw->main.data + fw->main.datasz; 5655 fw->init.data = fw->init.text + fw->init.textsz; 5656 fw->boot.text = fw->init.data + fw->init.datasz; 5657 5658 return 0; 5659 } 5660 5661 int 5662 iwn_clock_wait(struct iwn_softc *sc) 5663 { 5664 int ntries; 5665 5666 /* Set "initialization complete" bit. */ 5667 IWN_SETBITS(sc, IWN_GP_CNTRL, IWN_GP_CNTRL_INIT_DONE); 5668 5669 /* Wait for clock stabilization. */ 5670 for (ntries = 0; ntries < 2500; ntries++) { 5671 if (IWN_READ(sc, IWN_GP_CNTRL) & IWN_GP_CNTRL_MAC_CLOCK_READY) 5672 return 0; 5673 DELAY(10); 5674 } 5675 device_printf(sc->sc_dev, 5676 "%s: timeout waiting for clock stabilization\n", __func__); 5677 return ETIMEDOUT; 5678 } 5679 5680 int 5681 iwn_apm_init(struct iwn_softc *sc) 5682 { 5683 uint32_t tmp; 5684 int error; 5685 5686 /* Disable L0s exit timer (NMI bug workaround.) */ 5687 IWN_SETBITS(sc, IWN_GIO_CHICKEN, IWN_GIO_CHICKEN_DIS_L0S_TIMER); 5688 /* Don't wait for ICH L0s (ICH bug workaround.) */ 5689 IWN_SETBITS(sc, IWN_GIO_CHICKEN, IWN_GIO_CHICKEN_L1A_NO_L0S_RX); 5690 5691 /* Set FH wait threshold to max (HW bug under stress workaround.) */ 5692 IWN_SETBITS(sc, IWN_DBG_HPET_MEM, 0xffff0000); 5693 5694 /* Enable HAP INTA to move adapter from L1a to L0s. */ 5695 IWN_SETBITS(sc, IWN_HW_IF_CONFIG, IWN_HW_IF_CONFIG_HAP_WAKE_L1A); 5696 5697 /* Retrieve PCIe Active State Power Management (ASPM). */ 5698 tmp = pci_read_config(sc->sc_dev, sc->sc_cap_off + 0x10, 1); 5699 /* Workaround for HW instability in PCIe L0->L0s->L1 transition. */ 5700 if (tmp & 0x02) /* L1 Entry enabled. */ 5701 IWN_SETBITS(sc, IWN_GIO, IWN_GIO_L0S_ENA); 5702 else 5703 IWN_CLRBITS(sc, IWN_GIO, IWN_GIO_L0S_ENA); 5704 5705 if (sc->hw_type != IWN_HW_REV_TYPE_4965 && 5706 sc->hw_type != IWN_HW_REV_TYPE_6000 && 5707 sc->hw_type != IWN_HW_REV_TYPE_6050) 5708 IWN_SETBITS(sc, IWN_ANA_PLL, IWN_ANA_PLL_INIT); 5709 5710 /* Wait for clock stabilization before accessing prph. */ 5711 error = iwn_clock_wait(sc); 5712 if (error != 0) 5713 return error; 5714 5715 error = iwn_nic_lock(sc); 5716 if (error != 0) 5717 return error; 5718 5719 if (sc->hw_type == IWN_HW_REV_TYPE_4965) { 5720 /* Enable DMA and BSM (Bootstrap State Machine.) */ 5721 iwn_prph_write(sc, IWN_APMG_CLK_EN, 5722 IWN_APMG_CLK_CTRL_DMA_CLK_RQT | 5723 IWN_APMG_CLK_CTRL_BSM_CLK_RQT); 5724 } else { 5725 /* Enable DMA. */ 5726 iwn_prph_write(sc, IWN_APMG_CLK_EN, 5727 IWN_APMG_CLK_CTRL_DMA_CLK_RQT); 5728 } 5729 DELAY(20); 5730 5731 /* Disable L1-Active. */ 5732 iwn_prph_setbits(sc, IWN_APMG_PCI_STT, IWN_APMG_PCI_STT_L1A_DIS); 5733 iwn_nic_unlock(sc); 5734 5735 return 0; 5736 } 5737 5738 void 5739 iwn_apm_stop_master(struct iwn_softc *sc) 5740 { 5741 int ntries; 5742 5743 /* Stop busmaster DMA activity. */ 5744 IWN_SETBITS(sc, IWN_RESET, IWN_RESET_STOP_MASTER); 5745 for (ntries = 0; ntries < 100; ntries++) { 5746 if (IWN_READ(sc, IWN_RESET) & IWN_RESET_MASTER_DISABLED) 5747 return; 5748 DELAY(10); 5749 } 5750 device_printf(sc->sc_dev, "%s: timeout waiting for master\n", 5751 __func__); 5752 } 5753 5754 void 5755 iwn_apm_stop(struct iwn_softc *sc) 5756 { 5757 iwn_apm_stop_master(sc); 5758 5759 /* Reset the entire device. */ 5760 IWN_SETBITS(sc, IWN_RESET, IWN_RESET_SW); 5761 DELAY(10); 5762 /* Clear "initialization complete" bit. */ 5763 IWN_CLRBITS(sc, IWN_GP_CNTRL, IWN_GP_CNTRL_INIT_DONE); 5764 } 5765 5766 int 5767 iwn4965_nic_config(struct iwn_softc *sc) 5768 { 5769 if (IWN_RFCFG_TYPE(sc->rfcfg) == 1) { 5770 /* 5771 * I don't believe this to be correct but this is what the 5772 * vendor driver is doing. Probably the bits should not be 5773 * shifted in IWN_RFCFG_*. 5774 */ 5775 IWN_SETBITS(sc, IWN_HW_IF_CONFIG, 5776 IWN_RFCFG_TYPE(sc->rfcfg) | 5777 IWN_RFCFG_STEP(sc->rfcfg) | 5778 IWN_RFCFG_DASH(sc->rfcfg)); 5779 } 5780 IWN_SETBITS(sc, IWN_HW_IF_CONFIG, 5781 IWN_HW_IF_CONFIG_RADIO_SI | IWN_HW_IF_CONFIG_MAC_SI); 5782 return 0; 5783 } 5784 5785 int 5786 iwn5000_nic_config(struct iwn_softc *sc) 5787 { 5788 uint32_t tmp; 5789 int error; 5790 5791 if (IWN_RFCFG_TYPE(sc->rfcfg) < 3) { 5792 IWN_SETBITS(sc, IWN_HW_IF_CONFIG, 5793 IWN_RFCFG_TYPE(sc->rfcfg) | 5794 IWN_RFCFG_STEP(sc->rfcfg) | 5795 IWN_RFCFG_DASH(sc->rfcfg)); 5796 } 5797 IWN_SETBITS(sc, IWN_HW_IF_CONFIG, 5798 IWN_HW_IF_CONFIG_RADIO_SI | IWN_HW_IF_CONFIG_MAC_SI); 5799 5800 error = iwn_nic_lock(sc); 5801 if (error != 0) 5802 return error; 5803 iwn_prph_setbits(sc, IWN_APMG_PS, IWN_APMG_PS_EARLY_PWROFF_DIS); 5804 5805 if (sc->hw_type == IWN_HW_REV_TYPE_1000) { 5806 /* 5807 * Select first Switching Voltage Regulator (1.32V) to 5808 * solve a stability issue related to noisy DC2DC line 5809 * in the silicon of 1000 Series. 5810 */ 5811 tmp = iwn_prph_read(sc, IWN_APMG_DIGITAL_SVR); 5812 tmp &= ~IWN_APMG_DIGITAL_SVR_VOLTAGE_MASK; 5813 tmp |= IWN_APMG_DIGITAL_SVR_VOLTAGE_1_32; 5814 iwn_prph_write(sc, IWN_APMG_DIGITAL_SVR, tmp); 5815 } 5816 iwn_nic_unlock(sc); 5817 5818 if (sc->sc_flags & IWN_FLAG_INTERNAL_PA) { 5819 /* Use internal power amplifier only. */ 5820 IWN_WRITE(sc, IWN_GP_DRIVER, IWN_GP_DRIVER_RADIO_2X2_IPA); 5821 } 5822 return 0; 5823 } 5824 5825 /* 5826 * Take NIC ownership over Intel Active Management Technology (AMT). 5827 */ 5828 int 5829 iwn_hw_prepare(struct iwn_softc *sc) 5830 { 5831 int ntries; 5832 5833 /* Check if hardware is ready. */ 5834 IWN_SETBITS(sc, IWN_HW_IF_CONFIG, IWN_HW_IF_CONFIG_NIC_READY); 5835 for (ntries = 0; ntries < 5; ntries++) { 5836 if (IWN_READ(sc, IWN_HW_IF_CONFIG) & 5837 IWN_HW_IF_CONFIG_NIC_READY) 5838 return 0; 5839 DELAY(10); 5840 } 5841 5842 /* Hardware not ready, force into ready state. */ 5843 IWN_SETBITS(sc, IWN_HW_IF_CONFIG, IWN_HW_IF_CONFIG_PREPARE); 5844 for (ntries = 0; ntries < 15000; ntries++) { 5845 if (!(IWN_READ(sc, IWN_HW_IF_CONFIG) & 5846 IWN_HW_IF_CONFIG_PREPARE_DONE)) 5847 break; 5848 DELAY(10); 5849 } 5850 if (ntries == 15000) 5851 return ETIMEDOUT; 5852 5853 /* Hardware should be ready now. */ 5854 IWN_SETBITS(sc, IWN_HW_IF_CONFIG, IWN_HW_IF_CONFIG_NIC_READY); 5855 for (ntries = 0; ntries < 5; ntries++) { 5856 if (IWN_READ(sc, IWN_HW_IF_CONFIG) & 5857 IWN_HW_IF_CONFIG_NIC_READY) 5858 return 0; 5859 DELAY(10); 5860 } 5861 return ETIMEDOUT; 5862 } 5863 5864 int 5865 iwn_hw_init(struct iwn_softc *sc) 5866 { 5867 const struct iwn_hal *hal = sc->sc_hal; 5868 int error, chnl, qid; 5869 5870 /* Clear pending interrupts. */ 5871 IWN_WRITE(sc, IWN_INT, 0xffffffff); 5872 5873 error = iwn_apm_init(sc); 5874 if (error != 0) { 5875 device_printf(sc->sc_dev, 5876 "%s: could not power ON adapter, error %d\n", 5877 __func__, error); 5878 return error; 5879 } 5880 5881 /* Select VMAIN power source. */ 5882 error = iwn_nic_lock(sc); 5883 if (error != 0) 5884 return error; 5885 iwn_prph_clrbits(sc, IWN_APMG_PS, IWN_APMG_PS_PWR_SRC_MASK); 5886 iwn_nic_unlock(sc); 5887 5888 /* Perform adapter-specific initialization. */ 5889 error = hal->nic_config(sc); 5890 if (error != 0) 5891 return error; 5892 5893 /* Initialize RX ring. */ 5894 error = iwn_nic_lock(sc); 5895 if (error != 0) 5896 return error; 5897 IWN_WRITE(sc, IWN_FH_RX_CONFIG, 0); 5898 IWN_WRITE(sc, IWN_FH_RX_WPTR, 0); 5899 /* Set physical address of RX ring (256-byte aligned.) */ 5900 IWN_WRITE(sc, IWN_FH_RX_BASE, sc->rxq.desc_dma.paddr >> 8); 5901 /* Set physical address of RX status (16-byte aligned.) */ 5902 IWN_WRITE(sc, IWN_FH_STATUS_WPTR, sc->rxq.stat_dma.paddr >> 4); 5903 /* Enable RX. */ 5904 IWN_WRITE(sc, IWN_FH_RX_CONFIG, 5905 IWN_FH_RX_CONFIG_ENA | 5906 IWN_FH_RX_CONFIG_IGN_RXF_EMPTY | /* HW bug workaround */ 5907 IWN_FH_RX_CONFIG_IRQ_DST_HOST | 5908 IWN_FH_RX_CONFIG_SINGLE_FRAME | 5909 IWN_FH_RX_CONFIG_RB_TIMEOUT(0) | 5910 IWN_FH_RX_CONFIG_NRBD(IWN_RX_RING_COUNT_LOG)); 5911 iwn_nic_unlock(sc); 5912 IWN_WRITE(sc, IWN_FH_RX_WPTR, (IWN_RX_RING_COUNT - 1) & ~7); 5913 5914 error = iwn_nic_lock(sc); 5915 if (error != 0) 5916 return error; 5917 5918 /* Initialize TX scheduler. */ 5919 iwn_prph_write(sc, hal->sched_txfact_addr, 0); 5920 5921 /* Set physical address of "keep warm" page (16-byte aligned.) */ 5922 IWN_WRITE(sc, IWN_FH_KW_ADDR, sc->kw_dma.paddr >> 4); 5923 5924 /* Initialize TX rings. */ 5925 for (qid = 0; qid < hal->ntxqs; qid++) { 5926 struct iwn_tx_ring *txq = &sc->txq[qid]; 5927 5928 /* Set physical address of TX ring (256-byte aligned.) */ 5929 IWN_WRITE(sc, IWN_FH_CBBC_QUEUE(qid), 5930 txq->desc_dma.paddr >> 8); 5931 } 5932 iwn_nic_unlock(sc); 5933 5934 /* Enable DMA channels. */ 5935 for (chnl = 0; chnl < hal->ndmachnls; chnl++) { 5936 IWN_WRITE(sc, IWN_FH_TX_CONFIG(chnl), 5937 IWN_FH_TX_CONFIG_DMA_ENA | 5938 IWN_FH_TX_CONFIG_DMA_CREDIT_ENA); 5939 } 5940 5941 /* Clear "radio off" and "commands blocked" bits. */ 5942 IWN_WRITE(sc, IWN_UCODE_GP1_CLR, IWN_UCODE_GP1_RFKILL); 5943 IWN_WRITE(sc, IWN_UCODE_GP1_CLR, IWN_UCODE_GP1_CMD_BLOCKED); 5944 5945 /* Clear pending interrupts. */ 5946 IWN_WRITE(sc, IWN_INT, 0xffffffff); 5947 /* Enable interrupt coalescing. */ 5948 IWN_WRITE(sc, IWN_INT_COALESCING, 512 / 8); 5949 /* Enable interrupts. */ 5950 IWN_WRITE(sc, IWN_INT_MASK, sc->int_mask); 5951 5952 /* _Really_ make sure "radio off" bit is cleared! */ 5953 IWN_WRITE(sc, IWN_UCODE_GP1_CLR, IWN_UCODE_GP1_RFKILL); 5954 IWN_WRITE(sc, IWN_UCODE_GP1_CLR, IWN_UCODE_GP1_RFKILL); 5955 5956 error = hal->load_firmware(sc); 5957 if (error != 0) { 5958 device_printf(sc->sc_dev, 5959 "%s: could not load firmware, error %d\n", 5960 __func__, error); 5961 return error; 5962 } 5963 /* Wait at most one second for firmware alive notification. */ 5964 error = msleep(sc, &sc->sc_mtx, PCATCH, "iwninit", hz); 5965 if (error != 0) { 5966 device_printf(sc->sc_dev, 5967 "%s: timeout waiting for adapter to initialize, error %d\n", 5968 __func__, error); 5969 return error; 5970 } 5971 /* Do post-firmware initialization. */ 5972 return hal->post_alive(sc); 5973 } 5974 5975 void 5976 iwn_hw_stop(struct iwn_softc *sc) 5977 { 5978 const struct iwn_hal *hal = sc->sc_hal; 5979 uint32_t tmp; 5980 int chnl, qid, ntries; 5981 5982 IWN_WRITE(sc, IWN_RESET, IWN_RESET_NEVO); 5983 5984 /* Disable interrupts. */ 5985 IWN_WRITE(sc, IWN_INT_MASK, 0); 5986 IWN_WRITE(sc, IWN_INT, 0xffffffff); 5987 IWN_WRITE(sc, IWN_FH_INT, 0xffffffff); 5988 sc->sc_flags &= ~IWN_FLAG_USE_ICT; 5989 5990 /* Make sure we no longer hold the NIC lock. */ 5991 iwn_nic_unlock(sc); 5992 5993 /* Stop TX scheduler. */ 5994 iwn_prph_write(sc, hal->sched_txfact_addr, 0); 5995 5996 /* Stop all DMA channels. */ 5997 if (iwn_nic_lock(sc) == 0) { 5998 for (chnl = 0; chnl < hal->ndmachnls; chnl++) { 5999 IWN_WRITE(sc, IWN_FH_TX_CONFIG(chnl), 0); 6000 for (ntries = 0; ntries < 200; ntries++) { 6001 tmp = IWN_READ(sc, IWN_FH_TX_STATUS); 6002 if ((tmp & IWN_FH_TX_STATUS_IDLE(chnl)) == 6003 IWN_FH_TX_STATUS_IDLE(chnl)) 6004 break; 6005 DELAY(10); 6006 } 6007 } 6008 iwn_nic_unlock(sc); 6009 } 6010 6011 /* Stop RX ring. */ 6012 iwn_reset_rx_ring(sc, &sc->rxq); 6013 6014 /* Reset all TX rings. */ 6015 for (qid = 0; qid < hal->ntxqs; qid++) 6016 iwn_reset_tx_ring(sc, &sc->txq[qid]); 6017 6018 if (iwn_nic_lock(sc) == 0) { 6019 iwn_prph_write(sc, IWN_APMG_CLK_DIS, 6020 IWN_APMG_CLK_CTRL_DMA_CLK_RQT); 6021 iwn_nic_unlock(sc); 6022 } 6023 DELAY(5); 6024 6025 /* Power OFF adapter. */ 6026 iwn_apm_stop(sc); 6027 } 6028 6029 void 6030 iwn_init_locked(struct iwn_softc *sc) 6031 { 6032 struct ifnet *ifp = sc->sc_ifp; 6033 int error; 6034 6035 IWN_LOCK_ASSERT(sc); 6036 6037 error = iwn_hw_prepare(sc); 6038 if (error != 0) { 6039 device_printf(sc->sc_dev, "%s: hardware not ready, eror %d\n", 6040 __func__, error); 6041 goto fail; 6042 } 6043 6044 /* Initialize interrupt mask to default value. */ 6045 sc->int_mask = IWN_INT_MASK_DEF; 6046 sc->sc_flags &= ~IWN_FLAG_USE_ICT; 6047 6048 /* Check that the radio is not disabled by hardware switch. */ 6049 if (!(IWN_READ(sc, IWN_GP_CNTRL) & IWN_GP_CNTRL_RFKILL)) { 6050 device_printf(sc->sc_dev, 6051 "radio is disabled by hardware switch\n"); 6052 6053 /* Enable interrupts to get RF toggle notifications. */ 6054 IWN_WRITE(sc, IWN_INT, 0xffffffff); 6055 IWN_WRITE(sc, IWN_INT_MASK, sc->int_mask); 6056 return; 6057 } 6058 6059 /* Read firmware images from the filesystem. */ 6060 error = iwn_read_firmware(sc); 6061 if (error != 0) { 6062 device_printf(sc->sc_dev, 6063 "%s: could not read firmware, error %d\n", 6064 __func__, error); 6065 goto fail; 6066 } 6067 6068 /* Initialize hardware and upload firmware. */ 6069 error = iwn_hw_init(sc); 6070 firmware_put(sc->fw_fp, FIRMWARE_UNLOAD); 6071 sc->fw_fp = NULL; 6072 if (error != 0) { 6073 device_printf(sc->sc_dev, 6074 "%s: could not initialize hardware, error %d\n", 6075 __func__, error); 6076 goto fail; 6077 } 6078 6079 /* Configure adapter now that it is ready. */ 6080 error = iwn_config(sc); 6081 if (error != 0) { 6082 device_printf(sc->sc_dev, 6083 "%s: could not configure device, error %d\n", 6084 __func__, error); 6085 goto fail; 6086 } 6087 6088 ifp->if_drv_flags &= ~IFF_DRV_OACTIVE; 6089 ifp->if_drv_flags |= IFF_DRV_RUNNING; 6090 6091 return; 6092 6093 fail: 6094 iwn_stop_locked(sc); 6095 } 6096 6097 void 6098 iwn_init(void *arg) 6099 { 6100 struct iwn_softc *sc = arg; 6101 struct ifnet *ifp = sc->sc_ifp; 6102 struct ieee80211com *ic = ifp->if_l2com; 6103 6104 IWN_LOCK(sc); 6105 iwn_init_locked(sc); 6106 IWN_UNLOCK(sc); 6107 6108 if (ifp->if_drv_flags & IFF_DRV_RUNNING) 6109 ieee80211_start_all(ic); 6110 } 6111 6112 void 6113 iwn_stop_locked(struct iwn_softc *sc) 6114 { 6115 struct ifnet *ifp = sc->sc_ifp; 6116 6117 IWN_LOCK_ASSERT(sc); 6118 6119 sc->sc_tx_timer = 0; 6120 callout_stop(&sc->sc_timer_to); 6121 ifp->if_drv_flags &= ~(IFF_DRV_RUNNING | IFF_DRV_OACTIVE); 6122 6123 /* Power OFF hardware. */ 6124 iwn_hw_stop(sc); 6125 } 6126 6127 void 6128 iwn_stop(struct iwn_softc *sc) 6129 { 6130 IWN_LOCK(sc); 6131 iwn_stop_locked(sc); 6132 IWN_UNLOCK(sc); 6133 } 6134 6135 /* 6136 * Callback from net80211 to start a scan. 6137 */ 6138 static void 6139 iwn_scan_start(struct ieee80211com *ic) 6140 { 6141 struct ifnet *ifp = ic->ic_ifp; 6142 struct iwn_softc *sc = ifp->if_softc; 6143 6144 IWN_LOCK(sc); 6145 /* make the link LED blink while we're scanning */ 6146 iwn_set_led(sc, IWN_LED_LINK, 20, 2); 6147 IWN_UNLOCK(sc); 6148 } 6149 6150 /* 6151 * Callback from net80211 to terminate a scan. 6152 */ 6153 static void 6154 iwn_scan_end(struct ieee80211com *ic) 6155 { 6156 struct ifnet *ifp = ic->ic_ifp; 6157 struct iwn_softc *sc = ifp->if_softc; 6158 struct ieee80211vap *vap = TAILQ_FIRST(&ic->ic_vaps); 6159 6160 IWN_LOCK(sc); 6161 if (vap->iv_state == IEEE80211_S_RUN) { 6162 /* Set link LED to ON status if we are associated */ 6163 iwn_set_led(sc, IWN_LED_LINK, 0, 1); 6164 } 6165 IWN_UNLOCK(sc); 6166 } 6167 6168 /* 6169 * Callback from net80211 to force a channel change. 6170 */ 6171 static void 6172 iwn_set_channel(struct ieee80211com *ic) 6173 { 6174 const struct ieee80211_channel *c = ic->ic_curchan; 6175 struct ifnet *ifp = ic->ic_ifp; 6176 struct iwn_softc *sc = ifp->if_softc; 6177 6178 IWN_LOCK(sc); 6179 sc->sc_rxtap.wr_chan_freq = htole16(c->ic_freq); 6180 sc->sc_rxtap.wr_chan_flags = htole16(c->ic_flags); 6181 sc->sc_txtap.wt_chan_freq = htole16(c->ic_freq); 6182 sc->sc_txtap.wt_chan_flags = htole16(c->ic_flags); 6183 IWN_UNLOCK(sc); 6184 } 6185 6186 /* 6187 * Callback from net80211 to start scanning of the current channel. 6188 */ 6189 static void 6190 iwn_scan_curchan(struct ieee80211_scan_state *ss, unsigned long maxdwell) 6191 { 6192 struct ieee80211vap *vap = ss->ss_vap; 6193 struct iwn_softc *sc = vap->iv_ic->ic_ifp->if_softc; 6194 int error; 6195 6196 IWN_LOCK(sc); 6197 error = iwn_scan(sc); 6198 IWN_UNLOCK(sc); 6199 if (error != 0) 6200 ieee80211_cancel_scan(vap); 6201 } 6202 6203 /* 6204 * Callback from net80211 to handle the minimum dwell time being met. 6205 * The intent is to terminate the scan but we just let the firmware 6206 * notify us when it's finished as we have no safe way to abort it. 6207 */ 6208 static void 6209 iwn_scan_mindwell(struct ieee80211_scan_state *ss) 6210 { 6211 /* NB: don't try to abort scan; wait for firmware to finish */ 6212 } 6213 6214 static struct iwn_eeprom_chan * 6215 iwn_find_eeprom_channel(struct iwn_softc *sc, struct ieee80211_channel *c) 6216 { 6217 int i, j; 6218 6219 for (j = 0; j < 7; j++) { 6220 for (i = 0; i < iwn_bands[j].nchan; i++) { 6221 if (iwn_bands[j].chan[i] == c->ic_ieee) 6222 return &sc->eeprom_channels[j][i]; 6223 } 6224 } 6225 6226 return NULL; 6227 } 6228 6229 /* 6230 * Enforce flags read from EEPROM. 6231 */ 6232 static int 6233 iwn_setregdomain(struct ieee80211com *ic, struct ieee80211_regdomain *rd, 6234 int nchan, struct ieee80211_channel chans[]) 6235 { 6236 struct iwn_softc *sc = ic->ic_ifp->if_softc; 6237 int i; 6238 6239 for (i = 0; i < nchan; i++) { 6240 struct ieee80211_channel *c = &chans[i]; 6241 struct iwn_eeprom_chan *channel; 6242 6243 channel = iwn_find_eeprom_channel(sc, c); 6244 if (channel == NULL) { 6245 if_printf(ic->ic_ifp, 6246 "%s: invalid channel %u freq %u/0x%x\n", 6247 __func__, c->ic_ieee, c->ic_freq, c->ic_flags); 6248 return EINVAL; 6249 } 6250 c->ic_flags |= iwn_eeprom_channel_flags(channel); 6251 } 6252 6253 return 0; 6254 } 6255 6256 static void 6257 iwn_hw_reset(void *arg0, int pending) 6258 { 6259 struct iwn_softc *sc = arg0; 6260 struct ifnet *ifp = sc->sc_ifp; 6261 struct ieee80211com *ic = ifp->if_l2com; 6262 6263 iwn_stop(sc); 6264 iwn_init(sc); 6265 ieee80211_notify_radio(ic, 1); 6266 } 6267 6268 static void 6269 iwn_radio_on(void *arg0, int pending) 6270 { 6271 struct iwn_softc *sc = arg0; 6272 struct ifnet *ifp = sc->sc_ifp; 6273 struct ieee80211com *ic = ifp->if_l2com; 6274 struct ieee80211vap *vap = TAILQ_FIRST(&ic->ic_vaps); 6275 6276 if (vap != NULL) { 6277 iwn_init(sc); 6278 ieee80211_init(vap); 6279 } 6280 } 6281 6282 static void 6283 iwn_radio_off(void *arg0, int pending) 6284 { 6285 struct iwn_softc *sc = arg0; 6286 struct ifnet *ifp = sc->sc_ifp; 6287 struct ieee80211com *ic = ifp->if_l2com; 6288 struct ieee80211vap *vap = TAILQ_FIRST(&ic->ic_vaps); 6289 6290 iwn_stop(sc); 6291 if (vap != NULL) 6292 ieee80211_stop(vap); 6293 6294 /* Enable interrupts to get RF toggle notification. */ 6295 IWN_LOCK(sc); 6296 IWN_WRITE(sc, IWN_INT, 0xffffffff); 6297 IWN_WRITE(sc, IWN_INT_MASK, sc->int_mask); 6298 IWN_UNLOCK(sc); 6299 } 6300 6301 static void 6302 iwn_sysctlattach(struct iwn_softc *sc) 6303 { 6304 struct sysctl_ctx_list *ctx = device_get_sysctl_ctx(sc->sc_dev); 6305 struct sysctl_oid *tree = device_get_sysctl_tree(sc->sc_dev); 6306 6307 #ifdef IWN_DEBUG 6308 sc->sc_debug = 0; 6309 SYSCTL_ADD_INT(ctx, SYSCTL_CHILDREN(tree), OID_AUTO, 6310 "debug", CTLFLAG_RW, &sc->sc_debug, 0, "control debugging printfs"); 6311 #endif 6312 } 6313 6314 static int 6315 iwn_shutdown(device_t dev) 6316 { 6317 struct iwn_softc *sc = device_get_softc(dev); 6318 6319 iwn_stop(sc); 6320 return 0; 6321 } 6322 6323 static int 6324 iwn_suspend(device_t dev) 6325 { 6326 struct iwn_softc *sc = device_get_softc(dev); 6327 struct ifnet *ifp = sc->sc_ifp; 6328 struct ieee80211com *ic = ifp->if_l2com; 6329 struct ieee80211vap *vap = TAILQ_FIRST(&ic->ic_vaps); 6330 6331 iwn_stop(sc); 6332 if (vap != NULL) 6333 ieee80211_stop(vap); 6334 return 0; 6335 } 6336 6337 static int 6338 iwn_resume(device_t dev) 6339 { 6340 struct iwn_softc *sc = device_get_softc(dev); 6341 struct ifnet *ifp = sc->sc_ifp; 6342 struct ieee80211com *ic = ifp->if_l2com; 6343 struct ieee80211vap *vap = TAILQ_FIRST(&ic->ic_vaps); 6344 6345 /* Clear device-specific "PCI retry timeout" register (41h). */ 6346 pci_write_config(dev, 0x41, 0, 1); 6347 6348 if (ifp->if_flags & IFF_UP) { 6349 iwn_init(sc); 6350 if (vap != NULL) 6351 ieee80211_init(vap); 6352 if (ifp->if_drv_flags & IFF_DRV_RUNNING) 6353 iwn_start(ifp); 6354 } 6355 return 0; 6356 } 6357 6358 #ifdef IWN_DEBUG 6359 static const char * 6360 iwn_intr_str(uint8_t cmd) 6361 { 6362 switch (cmd) { 6363 /* Notifications */ 6364 case IWN_UC_READY: return "UC_READY"; 6365 case IWN_ADD_NODE_DONE: return "ADD_NODE_DONE"; 6366 case IWN_TX_DONE: return "TX_DONE"; 6367 case IWN_START_SCAN: return "START_SCAN"; 6368 case IWN_STOP_SCAN: return "STOP_SCAN"; 6369 case IWN_RX_STATISTICS: return "RX_STATS"; 6370 case IWN_BEACON_STATISTICS: return "BEACON_STATS"; 6371 case IWN_STATE_CHANGED: return "STATE_CHANGED"; 6372 case IWN_BEACON_MISSED: return "BEACON_MISSED"; 6373 case IWN_RX_PHY: return "RX_PHY"; 6374 case IWN_MPDU_RX_DONE: return "MPDU_RX_DONE"; 6375 case IWN_RX_DONE: return "RX_DONE"; 6376 6377 /* Command Notifications */ 6378 case IWN_CMD_RXON: return "IWN_CMD_RXON"; 6379 case IWN_CMD_RXON_ASSOC: return "IWN_CMD_RXON_ASSOC"; 6380 case IWN_CMD_EDCA_PARAMS: return "IWN_CMD_EDCA_PARAMS"; 6381 case IWN_CMD_TIMING: return "IWN_CMD_TIMING"; 6382 case IWN_CMD_LINK_QUALITY: return "IWN_CMD_LINK_QUALITY"; 6383 case IWN_CMD_SET_LED: return "IWN_CMD_SET_LED"; 6384 case IWN5000_CMD_WIMAX_COEX: return "IWN5000_CMD_WIMAX_COEX"; 6385 case IWN5000_CMD_CALIB_CONFIG: return "IWN5000_CMD_CALIB_CONFIG"; 6386 case IWN_CMD_SET_POWER_MODE: return "IWN_CMD_SET_POWER_MODE"; 6387 case IWN_CMD_SCAN: return "IWN_CMD_SCAN"; 6388 case IWN_CMD_TXPOWER: return "IWN_CMD_TXPOWER"; 6389 case IWN_CMD_TXPOWER_DBM: return "IWN_CMD_TXPOWER_DBM"; 6390 case IWN_CMD_BT_COEX: return "IWN_CMD_BT_COEX"; 6391 case IWN_CMD_SET_CRITICAL_TEMP: return "IWN_CMD_SET_CRITICAL_TEMP"; 6392 case IWN_CMD_SET_SENSITIVITY: return "IWN_CMD_SET_SENSITIVITY"; 6393 case IWN_CMD_PHY_CALIB: return "IWN_CMD_PHY_CALIB"; 6394 } 6395 return "UNKNOWN INTR NOTIF/CMD"; 6396 } 6397 #endif /* IWN_DEBUG */ 6398 6399 static device_method_t iwn_methods[] = { 6400 /* Device interface */ 6401 DEVMETHOD(device_probe, iwn_probe), 6402 DEVMETHOD(device_attach, iwn_attach), 6403 DEVMETHOD(device_detach, iwn_detach), 6404 DEVMETHOD(device_shutdown, iwn_shutdown), 6405 DEVMETHOD(device_suspend, iwn_suspend), 6406 DEVMETHOD(device_resume, iwn_resume), 6407 { 0, 0 } 6408 }; 6409 6410 static driver_t iwn_driver = { 6411 "iwn", 6412 iwn_methods, 6413 sizeof (struct iwn_softc) 6414 }; 6415 static devclass_t iwn_devclass; 6416 6417 DRIVER_MODULE(iwn, pci, iwn_driver, iwn_devclass, 0, 0); 6418 MODULE_DEPEND(iwn, pci, 1, 1, 1); 6419 MODULE_DEPEND(iwn, firmware, 1, 1, 1); 6420 MODULE_DEPEND(iwn, wlan, 1, 1, 1); 6421 MODULE_DEPEND(iwn, wlan_amrr, 1, 1, 1); 6422