1 /* $OpenBSD: if_iwmreg.h,v 1.4 2015/06/15 08:06:11 stsp Exp $ */ 2 /* $FreeBSD$ */ 3 4 /****************************************************************************** 5 * 6 * This file is provided under a dual BSD/GPLv2 license. When using or 7 * redistributing this file, you may do so under either license. 8 * 9 * GPL LICENSE SUMMARY 10 * 11 * Copyright(c) 2005 - 2014 Intel Corporation. All rights reserved. 12 * 13 * This program is free software; you can redistribute it and/or modify 14 * it under the terms of version 2 of the GNU General Public License as 15 * published by the Free Software Foundation. 16 * 17 * This program is distributed in the hope that it will be useful, but 18 * WITHOUT ANY WARRANTY; without even the implied warranty of 19 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU 20 * General Public License for more details. 21 * 22 * You should have received a copy of the GNU General Public License 23 * along with this program; if not, write to the Free Software 24 * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110, 25 * USA 26 * 27 * The full GNU General Public License is included in this distribution 28 * in the file called COPYING. 29 * 30 * Contact Information: 31 * Intel Linux Wireless <ilw@linux.intel.com> 32 * Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497 33 * 34 * BSD LICENSE 35 * 36 * Copyright(c) 2005 - 2014 Intel Corporation. All rights reserved. 37 * All rights reserved. 38 * 39 * Redistribution and use in source and binary forms, with or without 40 * modification, are permitted provided that the following conditions 41 * are met: 42 * 43 * * Redistributions of source code must retain the above copyright 44 * notice, this list of conditions and the following disclaimer. 45 * * Redistributions in binary form must reproduce the above copyright 46 * notice, this list of conditions and the following disclaimer in 47 * the documentation and/or other materials provided with the 48 * distribution. 49 * * Neither the name Intel Corporation nor the names of its 50 * contributors may be used to endorse or promote products derived 51 * from this software without specific prior written permission. 52 * 53 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 54 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 55 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 56 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 57 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 58 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 59 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 60 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 61 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 62 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 63 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 64 * 65 *****************************************************************************/ 66 #ifndef __IF_IWM_REG_H__ 67 #define __IF_IWM_REG_H__ 68 69 #define le16_to_cpup(_a_) (le16toh(*(const uint16_t *)(_a_))) 70 #define le32_to_cpup(_a_) (le32toh(*(const uint32_t *)(_a_))) 71 72 /* 73 * BEGIN iwl-csr.h 74 */ 75 76 /* 77 * CSR (control and status registers) 78 * 79 * CSR registers are mapped directly into PCI bus space, and are accessible 80 * whenever platform supplies power to device, even when device is in 81 * low power states due to driver-invoked device resets 82 * (e.g. IWM_CSR_RESET_REG_FLAG_SW_RESET) or uCode-driven power-saving modes. 83 * 84 * Use iwl_write32() and iwl_read32() family to access these registers; 85 * these provide simple PCI bus access, without waking up the MAC. 86 * Do not use iwl_write_direct32() family for these registers; 87 * no need to "grab nic access" via IWM_CSR_GP_CNTRL_REG_FLAG_MAC_ACCESS_REQ. 88 * The MAC (uCode processor, etc.) does not need to be powered up for accessing 89 * the CSR registers. 90 * 91 * NOTE: Device does need to be awake in order to read this memory 92 * via IWM_CSR_EEPROM and IWM_CSR_OTP registers 93 */ 94 #define IWM_CSR_HW_IF_CONFIG_REG (0x000) /* hardware interface config */ 95 #define IWM_CSR_INT_COALESCING (0x004) /* accum ints, 32-usec units */ 96 #define IWM_CSR_INT (0x008) /* host interrupt status/ack */ 97 #define IWM_CSR_INT_MASK (0x00c) /* host interrupt enable */ 98 #define IWM_CSR_FH_INT_STATUS (0x010) /* busmaster int status/ack*/ 99 #define IWM_CSR_GPIO_IN (0x018) /* read external chip pins */ 100 #define IWM_CSR_RESET (0x020) /* busmaster enable, NMI, etc*/ 101 #define IWM_CSR_GP_CNTRL (0x024) 102 103 /* 2nd byte of IWM_CSR_INT_COALESCING, not accessible via iwl_write32()! */ 104 #define IWM_CSR_INT_PERIODIC_REG (0x005) 105 106 /* 107 * Hardware revision info 108 * Bit fields: 109 * 31-16: Reserved 110 * 15-4: Type of device: see IWM_CSR_HW_REV_TYPE_xxx definitions 111 * 3-2: Revision step: 0 = A, 1 = B, 2 = C, 3 = D 112 * 1-0: "Dash" (-) value, as in A-1, etc. 113 */ 114 #define IWM_CSR_HW_REV (0x028) 115 116 /* 117 * EEPROM and OTP (one-time-programmable) memory reads 118 * 119 * NOTE: Device must be awake, initialized via apm_ops.init(), 120 * in order to read. 121 */ 122 #define IWM_CSR_EEPROM_REG (0x02c) 123 #define IWM_CSR_EEPROM_GP (0x030) 124 #define IWM_CSR_OTP_GP_REG (0x034) 125 126 #define IWM_CSR_GIO_REG (0x03C) 127 #define IWM_CSR_GP_UCODE_REG (0x048) 128 #define IWM_CSR_GP_DRIVER_REG (0x050) 129 130 /* 131 * UCODE-DRIVER GP (general purpose) mailbox registers. 132 * SET/CLR registers set/clear bit(s) if "1" is written. 133 */ 134 #define IWM_CSR_UCODE_DRV_GP1 (0x054) 135 #define IWM_CSR_UCODE_DRV_GP1_SET (0x058) 136 #define IWM_CSR_UCODE_DRV_GP1_CLR (0x05c) 137 #define IWM_CSR_UCODE_DRV_GP2 (0x060) 138 139 #define IWM_CSR_MBOX_SET_REG (0x088) 140 #define IWM_CSR_MBOX_SET_REG_OS_ALIVE 0x20 141 142 #define IWM_CSR_LED_REG (0x094) 143 #define IWM_CSR_DRAM_INT_TBL_REG (0x0A0) 144 #define IWM_CSR_MAC_SHADOW_REG_CTRL (0x0A8) /* 6000 and up */ 145 146 147 /* GIO Chicken Bits (PCI Express bus link power management) */ 148 #define IWM_CSR_GIO_CHICKEN_BITS (0x100) 149 150 /* Analog phase-lock-loop configuration */ 151 #define IWM_CSR_ANA_PLL_CFG (0x20c) 152 153 /* 154 * CSR Hardware Revision Workaround Register. Indicates hardware rev; 155 * "step" determines CCK backoff for txpower calculation. Used for 4965 only. 156 * See also IWM_CSR_HW_REV register. 157 * Bit fields: 158 * 3-2: 0 = A, 1 = B, 2 = C, 3 = D step 159 * 1-0: "Dash" (-) value, as in C-1, etc. 160 */ 161 #define IWM_CSR_HW_REV_WA_REG (0x22C) 162 163 #define IWM_CSR_DBG_HPET_MEM_REG (0x240) 164 #define IWM_CSR_DBG_LINK_PWR_MGMT_REG (0x250) 165 166 /* Bits for IWM_CSR_HW_IF_CONFIG_REG */ 167 #define IWM_CSR_HW_IF_CONFIG_REG_MSK_MAC_DASH (0x00000003) 168 #define IWM_CSR_HW_IF_CONFIG_REG_MSK_MAC_STEP (0x0000000C) 169 #define IWM_CSR_HW_IF_CONFIG_REG_MSK_BOARD_VER (0x000000C0) 170 #define IWM_CSR_HW_IF_CONFIG_REG_BIT_MAC_SI (0x00000100) 171 #define IWM_CSR_HW_IF_CONFIG_REG_BIT_RADIO_SI (0x00000200) 172 #define IWM_CSR_HW_IF_CONFIG_REG_MSK_PHY_TYPE (0x00000C00) 173 #define IWM_CSR_HW_IF_CONFIG_REG_MSK_PHY_DASH (0x00003000) 174 #define IWM_CSR_HW_IF_CONFIG_REG_MSK_PHY_STEP (0x0000C000) 175 176 #define IWM_CSR_HW_IF_CONFIG_REG_POS_MAC_DASH (0) 177 #define IWM_CSR_HW_IF_CONFIG_REG_POS_MAC_STEP (2) 178 #define IWM_CSR_HW_IF_CONFIG_REG_POS_BOARD_VER (6) 179 #define IWM_CSR_HW_IF_CONFIG_REG_POS_PHY_TYPE (10) 180 #define IWM_CSR_HW_IF_CONFIG_REG_POS_PHY_DASH (12) 181 #define IWM_CSR_HW_IF_CONFIG_REG_POS_PHY_STEP (14) 182 183 #define IWM_CSR_HW_IF_CONFIG_REG_BIT_HAP_WAKE_L1A (0x00080000) 184 #define IWM_CSR_HW_IF_CONFIG_REG_BIT_EEPROM_OWN_SEM (0x00200000) 185 #define IWM_CSR_HW_IF_CONFIG_REG_BIT_NIC_READY (0x00400000) /* PCI_OWN_SEM */ 186 #define IWM_CSR_HW_IF_CONFIG_REG_BIT_NIC_PREPARE_DONE (0x02000000) /* ME_OWN */ 187 #define IWM_CSR_HW_IF_CONFIG_REG_PREPARE (0x08000000) /* WAKE_ME */ 188 #define IWM_CSR_HW_IF_CONFIG_REG_ENABLE_PME (0x10000000) 189 #define IWM_CSR_HW_IF_CONFIG_REG_PERSIST_MODE (0x40000000) /* PERSISTENCE */ 190 191 #define IWM_CSR_INT_PERIODIC_DIS (0x00) /* disable periodic int*/ 192 #define IWM_CSR_INT_PERIODIC_ENA (0xFF) /* 255*32 usec ~ 8 msec*/ 193 194 /* interrupt flags in INTA, set by uCode or hardware (e.g. dma), 195 * acknowledged (reset) by host writing "1" to flagged bits. */ 196 #define IWM_CSR_INT_BIT_FH_RX (1 << 31) /* Rx DMA, cmd responses, FH_INT[17:16] */ 197 #define IWM_CSR_INT_BIT_HW_ERR (1 << 29) /* DMA hardware error FH_INT[31] */ 198 #define IWM_CSR_INT_BIT_RX_PERIODIC (1 << 28) /* Rx periodic */ 199 #define IWM_CSR_INT_BIT_FH_TX (1 << 27) /* Tx DMA FH_INT[1:0] */ 200 #define IWM_CSR_INT_BIT_SCD (1 << 26) /* TXQ pointer advanced */ 201 #define IWM_CSR_INT_BIT_SW_ERR (1 << 25) /* uCode error */ 202 #define IWM_CSR_INT_BIT_RF_KILL (1 << 7) /* HW RFKILL switch GP_CNTRL[27] toggled */ 203 #define IWM_CSR_INT_BIT_CT_KILL (1 << 6) /* Critical temp (chip too hot) rfkill */ 204 #define IWM_CSR_INT_BIT_SW_RX (1 << 3) /* Rx, command responses */ 205 #define IWM_CSR_INT_BIT_WAKEUP (1 << 1) /* NIC controller waking up (pwr mgmt) */ 206 #define IWM_CSR_INT_BIT_ALIVE (1 << 0) /* uCode interrupts once it initializes */ 207 208 #define IWM_CSR_INI_SET_MASK (IWM_CSR_INT_BIT_FH_RX | \ 209 IWM_CSR_INT_BIT_HW_ERR | \ 210 IWM_CSR_INT_BIT_FH_TX | \ 211 IWM_CSR_INT_BIT_SW_ERR | \ 212 IWM_CSR_INT_BIT_RF_KILL | \ 213 IWM_CSR_INT_BIT_SW_RX | \ 214 IWM_CSR_INT_BIT_WAKEUP | \ 215 IWM_CSR_INT_BIT_ALIVE | \ 216 IWM_CSR_INT_BIT_RX_PERIODIC) 217 218 /* interrupt flags in FH (flow handler) (PCI busmaster DMA) */ 219 #define IWM_CSR_FH_INT_BIT_ERR (1 << 31) /* Error */ 220 #define IWM_CSR_FH_INT_BIT_HI_PRIOR (1 << 30) /* High priority Rx, bypass coalescing */ 221 #define IWM_CSR_FH_INT_BIT_RX_CHNL1 (1 << 17) /* Rx channel 1 */ 222 #define IWM_CSR_FH_INT_BIT_RX_CHNL0 (1 << 16) /* Rx channel 0 */ 223 #define IWM_CSR_FH_INT_BIT_TX_CHNL1 (1 << 1) /* Tx channel 1 */ 224 #define IWM_CSR_FH_INT_BIT_TX_CHNL0 (1 << 0) /* Tx channel 0 */ 225 226 #define IWM_CSR_FH_INT_RX_MASK (IWM_CSR_FH_INT_BIT_HI_PRIOR | \ 227 IWM_CSR_FH_INT_BIT_RX_CHNL1 | \ 228 IWM_CSR_FH_INT_BIT_RX_CHNL0) 229 230 #define IWM_CSR_FH_INT_TX_MASK (IWM_CSR_FH_INT_BIT_TX_CHNL1 | \ 231 IWM_CSR_FH_INT_BIT_TX_CHNL0) 232 233 /* GPIO */ 234 #define IWM_CSR_GPIO_IN_BIT_AUX_POWER (0x00000200) 235 #define IWM_CSR_GPIO_IN_VAL_VAUX_PWR_SRC (0x00000000) 236 #define IWM_CSR_GPIO_IN_VAL_VMAIN_PWR_SRC (0x00000200) 237 238 /* RESET */ 239 #define IWM_CSR_RESET_REG_FLAG_NEVO_RESET (0x00000001) 240 #define IWM_CSR_RESET_REG_FLAG_FORCE_NMI (0x00000002) 241 #define IWM_CSR_RESET_REG_FLAG_SW_RESET (0x00000080) 242 #define IWM_CSR_RESET_REG_FLAG_MASTER_DISABLED (0x00000100) 243 #define IWM_CSR_RESET_REG_FLAG_STOP_MASTER (0x00000200) 244 #define IWM_CSR_RESET_LINK_PWR_MGMT_DISABLED (0x80000000) 245 246 /* 247 * GP (general purpose) CONTROL REGISTER 248 * Bit fields: 249 * 27: HW_RF_KILL_SW 250 * Indicates state of (platform's) hardware RF-Kill switch 251 * 26-24: POWER_SAVE_TYPE 252 * Indicates current power-saving mode: 253 * 000 -- No power saving 254 * 001 -- MAC power-down 255 * 010 -- PHY (radio) power-down 256 * 011 -- Error 257 * 9-6: SYS_CONFIG 258 * Indicates current system configuration, reflecting pins on chip 259 * as forced high/low by device circuit board. 260 * 4: GOING_TO_SLEEP 261 * Indicates MAC is entering a power-saving sleep power-down. 262 * Not a good time to access device-internal resources. 263 * 3: MAC_ACCESS_REQ 264 * Host sets this to request and maintain MAC wakeup, to allow host 265 * access to device-internal resources. Host must wait for 266 * MAC_CLOCK_READY (and !GOING_TO_SLEEP) before accessing non-CSR 267 * device registers. 268 * 2: INIT_DONE 269 * Host sets this to put device into fully operational D0 power mode. 270 * Host resets this after SW_RESET to put device into low power mode. 271 * 0: MAC_CLOCK_READY 272 * Indicates MAC (ucode processor, etc.) is powered up and can run. 273 * Internal resources are accessible. 274 * NOTE: This does not indicate that the processor is actually running. 275 * NOTE: This does not indicate that device has completed 276 * init or post-power-down restore of internal SRAM memory. 277 * Use IWM_CSR_UCODE_DRV_GP1_BIT_MAC_SLEEP as indication that 278 * SRAM is restored and uCode is in normal operation mode. 279 * Later devices (5xxx/6xxx/1xxx) use non-volatile SRAM, and 280 * do not need to save/restore it. 281 * NOTE: After device reset, this bit remains "0" until host sets 282 * INIT_DONE 283 */ 284 #define IWM_CSR_GP_CNTRL_REG_FLAG_MAC_CLOCK_READY (0x00000001) 285 #define IWM_CSR_GP_CNTRL_REG_FLAG_INIT_DONE (0x00000004) 286 #define IWM_CSR_GP_CNTRL_REG_FLAG_MAC_ACCESS_REQ (0x00000008) 287 #define IWM_CSR_GP_CNTRL_REG_FLAG_GOING_TO_SLEEP (0x00000010) 288 289 #define IWM_CSR_GP_CNTRL_REG_VAL_MAC_ACCESS_EN (0x00000001) 290 291 #define IWM_CSR_GP_CNTRL_REG_MSK_POWER_SAVE_TYPE (0x07000000) 292 #define IWM_CSR_GP_CNTRL_REG_FLAG_MAC_POWER_SAVE (0x04000000) 293 #define IWM_CSR_GP_CNTRL_REG_FLAG_HW_RF_KILL_SW (0x08000000) 294 295 296 /* HW REV */ 297 #define IWM_CSR_HW_REV_DASH(_val) (((_val) & 0x0000003) >> 0) 298 #define IWM_CSR_HW_REV_STEP(_val) (((_val) & 0x000000C) >> 2) 299 300 #define IWM_CSR_HW_REV_TYPE_MSK (0x000FFF0) 301 #define IWM_CSR_HW_REV_TYPE_5300 (0x0000020) 302 #define IWM_CSR_HW_REV_TYPE_5350 (0x0000030) 303 #define IWM_CSR_HW_REV_TYPE_5100 (0x0000050) 304 #define IWM_CSR_HW_REV_TYPE_5150 (0x0000040) 305 #define IWM_CSR_HW_REV_TYPE_1000 (0x0000060) 306 #define IWM_CSR_HW_REV_TYPE_6x00 (0x0000070) 307 #define IWM_CSR_HW_REV_TYPE_6x50 (0x0000080) 308 #define IWM_CSR_HW_REV_TYPE_6150 (0x0000084) 309 #define IWM_CSR_HW_REV_TYPE_6x05 (0x00000B0) 310 #define IWM_CSR_HW_REV_TYPE_6x30 IWM_CSR_HW_REV_TYPE_6x05 311 #define IWM_CSR_HW_REV_TYPE_6x35 IWM_CSR_HW_REV_TYPE_6x05 312 #define IWM_CSR_HW_REV_TYPE_2x30 (0x00000C0) 313 #define IWM_CSR_HW_REV_TYPE_2x00 (0x0000100) 314 #define IWM_CSR_HW_REV_TYPE_105 (0x0000110) 315 #define IWM_CSR_HW_REV_TYPE_135 (0x0000120) 316 #define IWM_CSR_HW_REV_TYPE_7265D (0x0000210) 317 #define IWM_CSR_HW_REV_TYPE_NONE (0x00001F0) 318 319 /* EEPROM REG */ 320 #define IWM_CSR_EEPROM_REG_READ_VALID_MSK (0x00000001) 321 #define IWM_CSR_EEPROM_REG_BIT_CMD (0x00000002) 322 #define IWM_CSR_EEPROM_REG_MSK_ADDR (0x0000FFFC) 323 #define IWM_CSR_EEPROM_REG_MSK_DATA (0xFFFF0000) 324 325 /* EEPROM GP */ 326 #define IWM_CSR_EEPROM_GP_VALID_MSK (0x00000007) /* signature */ 327 #define IWM_CSR_EEPROM_GP_IF_OWNER_MSK (0x00000180) 328 #define IWM_CSR_EEPROM_GP_BAD_SIGNATURE_BOTH_EEP_AND_OTP (0x00000000) 329 #define IWM_CSR_EEPROM_GP_BAD_SIG_EEP_GOOD_SIG_OTP (0x00000001) 330 #define IWM_CSR_EEPROM_GP_GOOD_SIG_EEP_LESS_THAN_4K (0x00000002) 331 #define IWM_CSR_EEPROM_GP_GOOD_SIG_EEP_MORE_THAN_4K (0x00000004) 332 333 /* One-time-programmable memory general purpose reg */ 334 #define IWM_CSR_OTP_GP_REG_DEVICE_SELECT (0x00010000) /* 0 - EEPROM, 1 - OTP */ 335 #define IWM_CSR_OTP_GP_REG_OTP_ACCESS_MODE (0x00020000) /* 0 - absolute, 1 - relative */ 336 #define IWM_CSR_OTP_GP_REG_ECC_CORR_STATUS_MSK (0x00100000) /* bit 20 */ 337 #define IWM_CSR_OTP_GP_REG_ECC_UNCORR_STATUS_MSK (0x00200000) /* bit 21 */ 338 339 /* GP REG */ 340 #define IWM_CSR_GP_REG_POWER_SAVE_STATUS_MSK (0x03000000) /* bit 24/25 */ 341 #define IWM_CSR_GP_REG_NO_POWER_SAVE (0x00000000) 342 #define IWM_CSR_GP_REG_MAC_POWER_SAVE (0x01000000) 343 #define IWM_CSR_GP_REG_PHY_POWER_SAVE (0x02000000) 344 #define IWM_CSR_GP_REG_POWER_SAVE_ERROR (0x03000000) 345 346 347 /* CSR GIO */ 348 #define IWM_CSR_GIO_REG_VAL_L0S_ENABLED (0x00000002) 349 350 /* 351 * UCODE-DRIVER GP (general purpose) mailbox register 1 352 * Host driver and uCode write and/or read this register to communicate with 353 * each other. 354 * Bit fields: 355 * 4: UCODE_DISABLE 356 * Host sets this to request permanent halt of uCode, same as 357 * sending CARD_STATE command with "halt" bit set. 358 * 3: CT_KILL_EXIT 359 * Host sets this to request exit from CT_KILL state, i.e. host thinks 360 * device temperature is low enough to continue normal operation. 361 * 2: CMD_BLOCKED 362 * Host sets this during RF KILL power-down sequence (HW, SW, CT KILL) 363 * to release uCode to clear all Tx and command queues, enter 364 * unassociated mode, and power down. 365 * NOTE: Some devices also use HBUS_TARG_MBX_C register for this bit. 366 * 1: SW_BIT_RFKILL 367 * Host sets this when issuing CARD_STATE command to request 368 * device sleep. 369 * 0: MAC_SLEEP 370 * uCode sets this when preparing a power-saving power-down. 371 * uCode resets this when power-up is complete and SRAM is sane. 372 * NOTE: device saves internal SRAM data to host when powering down, 373 * and must restore this data after powering back up. 374 * MAC_SLEEP is the best indication that restore is complete. 375 * Later devices (5xxx/6xxx/1xxx) use non-volatile SRAM, and 376 * do not need to save/restore it. 377 */ 378 #define IWM_CSR_UCODE_DRV_GP1_BIT_MAC_SLEEP (0x00000001) 379 #define IWM_CSR_UCODE_SW_BIT_RFKILL (0x00000002) 380 #define IWM_CSR_UCODE_DRV_GP1_BIT_CMD_BLOCKED (0x00000004) 381 #define IWM_CSR_UCODE_DRV_GP1_REG_BIT_CT_KILL_EXIT (0x00000008) 382 #define IWM_CSR_UCODE_DRV_GP1_BIT_D3_CFG_COMPLETE (0x00000020) 383 384 /* GP Driver */ 385 #define IWM_CSR_GP_DRIVER_REG_BIT_RADIO_SKU_MSK (0x00000003) 386 #define IWM_CSR_GP_DRIVER_REG_BIT_RADIO_SKU_3x3_HYB (0x00000000) 387 #define IWM_CSR_GP_DRIVER_REG_BIT_RADIO_SKU_2x2_HYB (0x00000001) 388 #define IWM_CSR_GP_DRIVER_REG_BIT_RADIO_SKU_2x2_IPA (0x00000002) 389 #define IWM_CSR_GP_DRIVER_REG_BIT_CALIB_VERSION6 (0x00000004) 390 #define IWM_CSR_GP_DRIVER_REG_BIT_6050_1x2 (0x00000008) 391 392 #define IWM_CSR_GP_DRIVER_REG_BIT_RADIO_IQ_INVER (0x00000080) 393 394 /* GIO Chicken Bits (PCI Express bus link power management) */ 395 #define IWM_CSR_GIO_CHICKEN_BITS_REG_BIT_L1A_NO_L0S_RX (0x00800000) 396 #define IWM_CSR_GIO_CHICKEN_BITS_REG_BIT_DIS_L0S_EXIT_TIMER (0x20000000) 397 398 /* LED */ 399 #define IWM_CSR_LED_BSM_CTRL_MSK (0xFFFFFFDF) 400 #define IWM_CSR_LED_REG_TURN_ON (0x60) 401 #define IWM_CSR_LED_REG_TURN_OFF (0x20) 402 403 /* ANA_PLL */ 404 #define IWM_CSR50_ANA_PLL_CFG_VAL (0x00880300) 405 406 /* HPET MEM debug */ 407 #define IWM_CSR_DBG_HPET_MEM_REG_VAL (0xFFFF0000) 408 409 /* DRAM INT TABLE */ 410 #define IWM_CSR_DRAM_INT_TBL_ENABLE (1 << 31) 411 #define IWM_CSR_DRAM_INIT_TBL_WRITE_POINTER (1 << 28) 412 #define IWM_CSR_DRAM_INIT_TBL_WRAP_CHECK (1 << 27) 413 414 /* SECURE boot registers */ 415 #define IWM_CSR_SECURE_BOOT_CONFIG_ADDR (0x100) 416 enum iwm_secure_boot_config_reg { 417 IWM_CSR_SECURE_BOOT_CONFIG_INSPECTOR_BURNED_IN_OTP = 0x00000001, 418 IWM_CSR_SECURE_BOOT_CONFIG_INSPECTOR_NOT_REQ = 0x00000002, 419 }; 420 421 #define IWM_CSR_SECURE_BOOT_CPU1_STATUS_ADDR (0x100) 422 #define IWM_CSR_SECURE_BOOT_CPU2_STATUS_ADDR (0x100) 423 enum iwm_secure_boot_status_reg { 424 IWM_CSR_SECURE_BOOT_CPU_STATUS_VERF_STATUS = 0x00000003, 425 IWM_CSR_SECURE_BOOT_CPU_STATUS_VERF_COMPLETED = 0x00000002, 426 IWM_CSR_SECURE_BOOT_CPU_STATUS_VERF_SUCCESS = 0x00000004, 427 IWM_CSR_SECURE_BOOT_CPU_STATUS_VERF_FAIL = 0x00000008, 428 IWM_CSR_SECURE_BOOT_CPU_STATUS_SIGN_VERF_FAIL = 0x00000010, 429 }; 430 431 #define IWM_FH_UCODE_LOAD_STATUS 0x1af0 432 #define IWM_CSR_UCODE_LOAD_STATUS_ADDR 0x1e70 433 enum iwm_secure_load_status_reg { 434 IWM_LMPM_CPU_UCODE_LOADING_STARTED = 0x00000001, 435 IWM_LMPM_CPU_HDRS_LOADING_COMPLETED = 0x00000003, 436 IWM_LMPM_CPU_UCODE_LOADING_COMPLETED = 0x00000007, 437 IWM_LMPM_CPU_STATUS_NUM_OF_LAST_COMPLETED = 0x000000F8, 438 IWM_LMPM_CPU_STATUS_NUM_OF_LAST_LOADED_BLOCK = 0x0000FF00, 439 }; 440 #define IWM_FH_MEM_TB_MAX_LENGTH 0x20000 441 442 #define IWM_LMPM_SECURE_INSPECTOR_CODE_ADDR 0x1e38 443 #define IWM_LMPM_SECURE_INSPECTOR_DATA_ADDR 0x1e3c 444 #define IWM_LMPM_SECURE_UCODE_LOAD_CPU1_HDR_ADDR 0x1e78 445 #define IWM_LMPM_SECURE_UCODE_LOAD_CPU2_HDR_ADDR 0x1e7c 446 447 #define IWM_LMPM_SECURE_INSPECTOR_CODE_MEM_SPACE 0x400000 448 #define IWM_LMPM_SECURE_INSPECTOR_DATA_MEM_SPACE 0x402000 449 #define IWM_LMPM_SECURE_CPU1_HDR_MEM_SPACE 0x420000 450 #define IWM_LMPM_SECURE_CPU2_HDR_MEM_SPACE 0x420400 451 452 #define IWM_CSR_SECURE_TIME_OUT (100) 453 454 /* extended range in FW SRAM */ 455 #define IWM_FW_MEM_EXTENDED_START 0x40000 456 #define IWM_FW_MEM_EXTENDED_END 0x57FFF 457 458 /* FW chicken bits */ 459 #define IWM_LMPM_CHICK 0xa01ff8 460 #define IWM_LMPM_CHICK_EXTENDED_ADDR_SPACE 0x01 461 462 #define IWM_FH_TCSR_0_REG0 (0x1D00) 463 464 /* 465 * HBUS (Host-side Bus) 466 * 467 * HBUS registers are mapped directly into PCI bus space, but are used 468 * to indirectly access device's internal memory or registers that 469 * may be powered-down. 470 * 471 * Use iwl_write_direct32()/iwl_read_direct32() family for these registers; 472 * host must "grab nic access" via CSR_GP_CNTRL_REG_FLAG_MAC_ACCESS_REQ 473 * to make sure the MAC (uCode processor, etc.) is powered up for accessing 474 * internal resources. 475 * 476 * Do not use iwl_write32()/iwl_read32() family to access these registers; 477 * these provide only simple PCI bus access, without waking up the MAC. 478 */ 479 #define IWM_HBUS_BASE (0x400) 480 481 /* 482 * Registers for accessing device's internal SRAM memory (e.g. SCD SRAM 483 * structures, error log, event log, verifying uCode load). 484 * First write to address register, then read from or write to data register 485 * to complete the job. Once the address register is set up, accesses to 486 * data registers auto-increment the address by one dword. 487 * Bit usage for address registers (read or write): 488 * 0-31: memory address within device 489 */ 490 #define IWM_HBUS_TARG_MEM_RADDR (IWM_HBUS_BASE+0x00c) 491 #define IWM_HBUS_TARG_MEM_WADDR (IWM_HBUS_BASE+0x010) 492 #define IWM_HBUS_TARG_MEM_WDAT (IWM_HBUS_BASE+0x018) 493 #define IWM_HBUS_TARG_MEM_RDAT (IWM_HBUS_BASE+0x01c) 494 495 /* Mailbox C, used as workaround alternative to CSR_UCODE_DRV_GP1 mailbox */ 496 #define IWM_HBUS_TARG_MBX_C (IWM_HBUS_BASE+0x030) 497 #define IWM_HBUS_TARG_MBX_C_REG_BIT_CMD_BLOCKED (0x00000004) 498 499 /* 500 * Registers for accessing device's internal peripheral registers 501 * (e.g. SCD, BSM, etc.). First write to address register, 502 * then read from or write to data register to complete the job. 503 * Bit usage for address registers (read or write): 504 * 0-15: register address (offset) within device 505 * 24-25: (# bytes - 1) to read or write (e.g. 3 for dword) 506 */ 507 #define IWM_HBUS_TARG_PRPH_WADDR (IWM_HBUS_BASE+0x044) 508 #define IWM_HBUS_TARG_PRPH_RADDR (IWM_HBUS_BASE+0x048) 509 #define IWM_HBUS_TARG_PRPH_WDAT (IWM_HBUS_BASE+0x04c) 510 #define IWM_HBUS_TARG_PRPH_RDAT (IWM_HBUS_BASE+0x050) 511 512 /* enable the ID buf for read */ 513 #define IWM_WFPM_PS_CTL_CLR 0xa0300c 514 #define IWM_WFMP_MAC_ADDR_0 0xa03080 515 #define IWM_WFMP_MAC_ADDR_1 0xa03084 516 #define IWM_LMPM_PMG_EN 0xa01cec 517 #define IWM_RADIO_REG_SYS_MANUAL_DFT_0 0xad4078 518 #define IWM_RFIC_REG_RD 0xad0470 519 #define IWM_WFPM_CTRL_REG 0xa03030 520 #define IWM_WFPM_AUX_CTL_AUX_IF_MAC_OWNER_MSK 0x08000000 521 #define IWM_ENABLE_WFPM 0x80000000 522 523 #define IWM_AUX_MISC_REG 0xa200b0 524 #define IWM_HW_STEP_LOCATION_BITS 24 525 526 #define IWM_AUX_MISC_MASTER1_EN 0xa20818 527 #define IWM_AUX_MISC_MASTER1_EN_SBE_MSK 0x1 528 #define IWM_AUX_MISC_MASTER1_SMPHR_STATUS 0xa20800 529 #define IWM_RSA_ENABLE 0xa24b08 530 #define IWM_PREG_AUX_BUS_WPROT_0 0xa04cc0 531 #define IWM_SB_CFG_OVERRIDE_ADDR 0xa26c78 532 #define IWM_SB_CFG_OVERRIDE_ENABLE 0x8000 533 #define IWM_SB_CFG_BASE_OVERRIDE 0xa20000 534 #define IWM_SB_MODIFY_CFG_FLAG 0xa03088 535 #define IWM_SB_CPU_1_STATUS 0xa01e30 536 #define IWM_SB_CPU_2_STATUS 0Xa01e34 537 538 /* Used to enable DBGM */ 539 #define IWM_HBUS_TARG_TEST_REG (IWM_HBUS_BASE+0x05c) 540 541 /* 542 * Per-Tx-queue write pointer (index, really!) 543 * Indicates index to next TFD that driver will fill (1 past latest filled). 544 * Bit usage: 545 * 0-7: queue write index 546 * 11-8: queue selector 547 */ 548 #define IWM_HBUS_TARG_WRPTR (IWM_HBUS_BASE+0x060) 549 550 /********************************************************** 551 * CSR values 552 **********************************************************/ 553 /* 554 * host interrupt timeout value 555 * used with setting interrupt coalescing timer 556 * the CSR_INT_COALESCING is an 8 bit register in 32-usec unit 557 * 558 * default interrupt coalescing timer is 64 x 32 = 2048 usecs 559 */ 560 #define IWM_HOST_INT_TIMEOUT_MAX (0xFF) 561 #define IWM_HOST_INT_TIMEOUT_DEF (0x40) 562 #define IWM_HOST_INT_TIMEOUT_MIN (0x0) 563 #define IWM_HOST_INT_OPER_MODE (1 << 31) 564 565 /***************************************************************************** 566 * 7000/3000 series SHR DTS addresses * 567 *****************************************************************************/ 568 569 /* Diode Results Register Structure: */ 570 enum iwm_dtd_diode_reg { 571 IWM_DTS_DIODE_REG_DIG_VAL = 0x000000FF, /* bits [7:0] */ 572 IWM_DTS_DIODE_REG_VREF_LOW = 0x0000FF00, /* bits [15:8] */ 573 IWM_DTS_DIODE_REG_VREF_HIGH = 0x00FF0000, /* bits [23:16] */ 574 IWM_DTS_DIODE_REG_VREF_ID = 0x03000000, /* bits [25:24] */ 575 IWM_DTS_DIODE_REG_PASS_ONCE = 0x80000000, /* bits [31:31] */ 576 IWM_DTS_DIODE_REG_FLAGS_MSK = 0xFF000000, /* bits [31:24] */ 577 /* Those are the masks INSIDE the flags bit-field: */ 578 IWM_DTS_DIODE_REG_FLAGS_VREFS_ID_POS = 0, 579 IWM_DTS_DIODE_REG_FLAGS_VREFS_ID = 0x00000003, /* bits [1:0] */ 580 IWM_DTS_DIODE_REG_FLAGS_PASS_ONCE_POS = 7, 581 IWM_DTS_DIODE_REG_FLAGS_PASS_ONCE = 0x00000080, /* bits [7:7] */ 582 }; 583 584 /* 585 * END iwl-csr.h 586 */ 587 588 /* 589 * BEGIN iwl-fw.h 590 */ 591 592 /** 593 * enum iwm_ucode_tlv_flag - ucode API flags 594 * @IWM_UCODE_TLV_FLAGS_PAN: This is PAN capable microcode; this previously 595 * was a separate TLV but moved here to save space. 596 * @IWM_UCODE_TLV_FLAGS_NEWSCAN: new uCode scan behaviour on hidden SSID, 597 * treats good CRC threshold as a boolean 598 * @IWM_UCODE_TLV_FLAGS_MFP: This uCode image supports MFP (802.11w). 599 * @IWM_UCODE_TLV_FLAGS_P2P: This uCode image supports P2P. 600 * @IWM_UCODE_TLV_FLAGS_DW_BC_TABLE: The SCD byte count table is in DWORDS 601 * @IWM_UCODE_TLV_FLAGS_UAPSD: This uCode image supports uAPSD 602 * @IWM_UCODE_TLV_FLAGS_SHORT_BL: 16 entries of black list instead of 64 in scan 603 * offload profile config command. 604 * @IWM_UCODE_TLV_FLAGS_RX_ENERGY_API: supports rx signal strength api 605 * @IWM_UCODE_TLV_FLAGS_TIME_EVENT_API_V2: using the new time event API. 606 * @IWM_UCODE_TLV_FLAGS_D3_6_IPV6_ADDRS: D3 image supports up to six 607 * (rather than two) IPv6 addresses 608 * @IWM_UCODE_TLV_FLAGS_BF_UPDATED: new beacon filtering API 609 * @IWM_UCODE_TLV_FLAGS_NO_BASIC_SSID: not sending a probe with the SSID element 610 * from the probe request template. 611 * @IWM_UCODE_TLV_FLAGS_D3_CONTINUITY_API: modified D3 API to allow keeping 612 * connection when going back to D0 613 * @IWM_UCODE_TLV_FLAGS_NEW_NSOFFL_SMALL: new NS offload (small version) 614 * @IWM_UCODE_TLV_FLAGS_NEW_NSOFFL_LARGE: new NS offload (large version) 615 * @IWM_UCODE_TLV_FLAGS_SCHED_SCAN: this uCode image supports scheduled scan. 616 * @IWM_UCODE_TLV_FLAGS_STA_KEY_CMD: new ADD_STA and ADD_STA_KEY command API 617 * @IWM_UCODE_TLV_FLAGS_DEVICE_PS_CMD: support device wide power command 618 * containing CAM (Continuous Active Mode) indication. 619 * @IWM_UCODE_TLV_FLAGS_P2P_PS: P2P client power save is supported (only on a 620 * single bound interface). 621 * @IWM_UCODE_TLV_FLAGS_UAPSD_SUPPORT: General support for uAPSD 622 * @IWM_UCODE_TLV_FLAGS_EBS_SUPPORT: this uCode image supports EBS. 623 * @IWM_UCODE_TLV_FLAGS_P2P_PS_UAPSD: P2P client supports uAPSD power save 624 * @IWM_UCODE_TLV_FLAGS_BCAST_FILTERING: uCode supports broadcast filtering. 625 * @IWM_UCODE_TLV_FLAGS_GO_UAPSD: AP/GO interfaces support uAPSD clients 626 * 627 */ 628 enum iwm_ucode_tlv_flag { 629 IWM_UCODE_TLV_FLAGS_PAN = (1 << 0), 630 IWM_UCODE_TLV_FLAGS_NEWSCAN = (1 << 1), 631 IWM_UCODE_TLV_FLAGS_MFP = (1 << 2), 632 IWM_UCODE_TLV_FLAGS_P2P = (1 << 3), 633 IWM_UCODE_TLV_FLAGS_DW_BC_TABLE = (1 << 4), 634 IWM_UCODE_TLV_FLAGS_NEWBT_COEX = (1 << 5), 635 IWM_UCODE_TLV_FLAGS_PM_CMD_SUPPORT = (1 << 6), 636 IWM_UCODE_TLV_FLAGS_SHORT_BL = (1 << 7), 637 IWM_UCODE_TLV_FLAGS_RX_ENERGY_API = (1 << 8), 638 IWM_UCODE_TLV_FLAGS_TIME_EVENT_API_V2 = (1 << 9), 639 IWM_UCODE_TLV_FLAGS_D3_6_IPV6_ADDRS = (1 << 10), 640 IWM_UCODE_TLV_FLAGS_BF_UPDATED = (1 << 11), 641 IWM_UCODE_TLV_FLAGS_NO_BASIC_SSID = (1 << 12), 642 IWM_UCODE_TLV_FLAGS_D3_CONTINUITY_API = (1 << 14), 643 IWM_UCODE_TLV_FLAGS_NEW_NSOFFL_SMALL = (1 << 15), 644 IWM_UCODE_TLV_FLAGS_NEW_NSOFFL_LARGE = (1 << 16), 645 IWM_UCODE_TLV_FLAGS_SCHED_SCAN = (1 << 17), 646 IWM_UCODE_TLV_FLAGS_STA_KEY_CMD = (1 << 19), 647 IWM_UCODE_TLV_FLAGS_DEVICE_PS_CMD = (1 << 20), 648 IWM_UCODE_TLV_FLAGS_P2P_PS = (1 << 21), 649 IWM_UCODE_TLV_FLAGS_BSS_P2P_PS_DCM = (1 << 22), 650 IWM_UCODE_TLV_FLAGS_BSS_P2P_PS_SCM = (1 << 23), 651 IWM_UCODE_TLV_FLAGS_UAPSD_SUPPORT = (1 << 24), 652 IWM_UCODE_TLV_FLAGS_EBS_SUPPORT = (1 << 25), 653 IWM_UCODE_TLV_FLAGS_P2P_PS_UAPSD = (1 << 26), 654 IWM_UCODE_TLV_FLAGS_BCAST_FILTERING = (1 << 29), 655 IWM_UCODE_TLV_FLAGS_GO_UAPSD = (1 << 30), 656 IWM_UCODE_TLV_FLAGS_LTE_COEX = (1 << 31), 657 }; 658 659 #define IWM_UCODE_TLV_FLAG_BITS \ 660 "\020\1PAN\2NEWSCAN\3MFP\4P2P\5DW_BC_TABLE\6NEWBT_COEX\7PM_CMD\10SHORT_BL\11RX_ENERG \ 661 Y\12TIME_EVENT_V2\13D3_6_IPV6\14BF_UPDATED\15NO_BASIC_SSID\17D3_CONTINUITY\20NEW_NSOFF \ 662 L_S\21NEW_NSOFFL_L\22SCHED_SCAN\24STA_KEY_CMD\25DEVICE_PS_CMD\26P2P_PS\27P2P_PS_DCM\30 \ 663 P2P_PS_SCM\31UAPSD_SUPPORT\32EBS\33P2P_PS_UAPSD\36BCAST_FILTERING\37GO_UAPSD\40LTE_COEX" 664 665 /** 666 * enum iwm_ucode_tlv_api - ucode api 667 * @IWM_UCODE_TLV_API_FRAGMENTED_SCAN: This ucode supports active dwell time 668 * longer than the passive one, which is essential for fragmented scan. 669 * @IWM_UCODE_TLV_API_WIFI_MCC_UPDATE: ucode supports MCC updates with source. 670 * @IWM_UCODE_TLV_API_WIDE_CMD_HDR: ucode supports wide command header 671 * @IWM_UCODE_TLV_API_LQ_SS_PARAMS: Configure STBC/BFER via LQ CMD ss_params 672 * @IWM_UCODE_TLV_API_EXT_SCAN_PRIORITY: scan APIs use 8-level priority 673 * instead of 3. 674 * @IWM_UCODE_TLV_API_TX_POWER_CHAIN: TX power API has larger command size 675 * (command version 3) that supports per-chain limits 676 * 677 * @IWM_NUM_UCODE_TLV_API: number of bits used 678 */ 679 enum iwm_ucode_tlv_api { 680 IWM_UCODE_TLV_API_FRAGMENTED_SCAN = (1 << 8), 681 IWM_UCODE_TLV_API_WIFI_MCC_UPDATE = (1 << 9), 682 IWM_UCODE_TLV_API_WIDE_CMD_HDR = (1 << 14), 683 IWM_UCODE_TLV_API_LQ_SS_PARAMS = (1 << 18), 684 IWM_UCODE_TLV_API_EXT_SCAN_PRIORITY = (1 << 24), 685 IWM_UCODE_TLV_API_TX_POWER_CHAIN = (1 << 27), 686 687 IWM_NUM_UCODE_TLV_API = 32 688 }; 689 690 #define IWM_UCODE_TLV_API_BITS \ 691 "\020\10FRAGMENTED_SCAN\11WIFI_MCC_UPDATE\16WIDE_CMD_HDR\22LQ_SS_PARAMS\30EXT_SCAN_PRIO\33TX_POWER_CHAIN" 692 693 /** 694 * enum iwm_ucode_tlv_capa - ucode capabilities 695 * @IWM_UCODE_TLV_CAPA_D0I3_SUPPORT: supports D0i3 696 * @IWM_UCODE_TLV_CAPA_LAR_SUPPORT: supports Location Aware Regulatory 697 * @IWM_UCODE_TLV_CAPA_UMAC_SCAN: supports UMAC scan. 698 * @IWM_UCODE_TLV_CAPA_BEAMFORMER: supports Beamformer 699 * @IWM_UCODE_TLV_CAPA_TOF_SUPPORT: supports Time of Flight (802.11mc FTM) 700 * @IWM_UCODE_TLV_CAPA_TDLS_SUPPORT: support basic TDLS functionality 701 * @IWM_UCODE_TLV_CAPA_TXPOWER_INSERTION_SUPPORT: supports insertion of current 702 * tx power value into TPC Report action frame and Link Measurement Report 703 * action frame 704 * @IWM_UCODE_TLV_CAPA_DS_PARAM_SET_IE_SUPPORT: supports updating current 705 * channel in DS parameter set element in probe requests. 706 * @IWM_UCODE_TLV_CAPA_WFA_TPC_REP_IE_SUPPORT: supports adding TPC Report IE in 707 * probe requests. 708 * @IWM_UCODE_TLV_CAPA_QUIET_PERIOD_SUPPORT: supports Quiet Period requests 709 * @IWM_UCODE_TLV_CAPA_DQA_SUPPORT: supports dynamic queue allocation (DQA), 710 * which also implies support for the scheduler configuration command 711 * @IWM_UCODE_TLV_CAPA_TDLS_CHANNEL_SWITCH: supports TDLS channel switching 712 * @IWM_UCODE_TLV_CAPA_CNSLDTD_D3_D0_IMG: Consolidated D3-D0 image 713 * @IWM_UCODE_TLV_CAPA_HOTSPOT_SUPPORT: supports Hot Spot Command 714 * @IWM_UCODE_TLV_CAPA_DC2DC_SUPPORT: supports DC2DC Command 715 * @IWM_UCODE_TLV_CAPA_2G_COEX_SUPPORT: supports 2G coex Command 716 * @IWM_UCODE_TLV_CAPA_CSUM_SUPPORT: supports TCP Checksum Offload 717 * @IWM_UCODE_TLV_CAPA_RADIO_BEACON_STATS: support radio and beacon statistics 718 * @IWM_UCODE_TLV_CAPA_P2P_STANDALONE_UAPSD: support p2p standalone U-APSD 719 * @IWM_UCODE_TLV_CAPA_BT_COEX_PLCR: enabled BT Coex packet level co-running 720 * @IWM_UCODE_TLV_CAPA_LAR_MULTI_MCC: ucode supports LAR updates with different 721 * sources for the MCC. This TLV bit is a future replacement to 722 * IWM_UCODE_TLV_API_WIFI_MCC_UPDATE. When either is set, multi-source LAR 723 * is supported. 724 * @IWM_UCODE_TLV_CAPA_BT_COEX_RRC: supports BT Coex RRC 725 * @IWM_UCODE_TLV_CAPA_GSCAN_SUPPORT: supports gscan 726 * @IWM_UCODE_TLV_CAPA_NAN_SUPPORT: supports NAN 727 * @IWM_UCODE_TLV_CAPA_UMAC_UPLOAD: supports upload mode in umac (1=supported, 728 * 0=no support) 729 * @IWM_UCODE_TLV_CAPA_EXTENDED_DTS_MEASURE: extended DTS measurement 730 * @IWM_UCODE_TLV_CAPA_SHORT_PM_TIMEOUTS: supports short PM timeouts 731 * @IWM_UCODE_TLV_CAPA_BT_MPLUT_SUPPORT: supports bt-coex Multi-priority LUT 732 * @IWM_UCODE_TLV_CAPA_BEACON_ANT_SELECTION: firmware will decide on what 733 * antenna the beacon should be transmitted 734 * @IWM_UCODE_TLV_CAPA_BEACON_STORING: firmware will store the latest beacon 735 * from AP and will send it upon d0i3 exit. 736 * @IWM_UCODE_TLV_CAPA_LAR_SUPPORT_V2: support LAR API V2 737 * @IWM_UCODE_TLV_CAPA_CT_KILL_BY_FW: firmware responsible for CT-kill 738 * @IWM_UCODE_TLV_CAPA_TEMP_THS_REPORT_SUPPORT: supports temperature 739 * thresholds reporting 740 * @IWM_UCODE_TLV_CAPA_CTDP_SUPPORT: supports cTDP command 741 * @IWM_UCODE_TLV_CAPA_USNIFFER_UNIFIED: supports usniffer enabled in 742 * regular image. 743 * @IWM_UCODE_TLV_CAPA_EXTEND_SHARED_MEM_CFG: support getting more shared 744 * memory addresses from the firmware. 745 * @IWM_UCODE_TLV_CAPA_LQM_SUPPORT: supports Link Quality Measurement 746 * @IWM_UCODE_TLV_CAPA_LMAC_UPLOAD: supports upload mode in lmac (1=supported, 747 * 0=no support) 748 * 749 * @IWM_NUM_UCODE_TLV_CAPA: number of bits used 750 */ 751 enum iwm_ucode_tlv_capa { 752 IWM_UCODE_TLV_CAPA_D0I3_SUPPORT = 0, 753 IWM_UCODE_TLV_CAPA_LAR_SUPPORT = 1, 754 IWM_UCODE_TLV_CAPA_UMAC_SCAN = 2, 755 IWM_UCODE_TLV_CAPA_BEAMFORMER = 3, 756 IWM_UCODE_TLV_CAPA_TOF_SUPPORT = 5, 757 IWM_UCODE_TLV_CAPA_TDLS_SUPPORT = 6, 758 IWM_UCODE_TLV_CAPA_TXPOWER_INSERTION_SUPPORT = 8, 759 IWM_UCODE_TLV_CAPA_DS_PARAM_SET_IE_SUPPORT = 9, 760 IWM_UCODE_TLV_CAPA_WFA_TPC_REP_IE_SUPPORT = 10, 761 IWM_UCODE_TLV_CAPA_QUIET_PERIOD_SUPPORT = 11, 762 IWM_UCODE_TLV_CAPA_DQA_SUPPORT = 12, 763 IWM_UCODE_TLV_CAPA_TDLS_CHANNEL_SWITCH = 13, 764 IWM_UCODE_TLV_CAPA_CNSLDTD_D3_D0_IMG = 17, 765 IWM_UCODE_TLV_CAPA_HOTSPOT_SUPPORT = 18, 766 IWM_UCODE_TLV_CAPA_DC2DC_CONFIG_SUPPORT = 19, 767 IWM_UCODE_TLV_CAPA_2G_COEX_SUPPORT = 20, 768 IWM_UCODE_TLV_CAPA_CSUM_SUPPORT = 21, 769 IWM_UCODE_TLV_CAPA_RADIO_BEACON_STATS = 22, 770 IWM_UCODE_TLV_CAPA_P2P_STANDALONE_UAPSD = 26, 771 IWM_UCODE_TLV_CAPA_BT_COEX_PLCR = 28, 772 IWM_UCODE_TLV_CAPA_LAR_MULTI_MCC = 29, 773 IWM_UCODE_TLV_CAPA_BT_COEX_RRC = 30, 774 IWM_UCODE_TLV_CAPA_GSCAN_SUPPORT = 31, 775 IWM_UCODE_TLV_CAPA_NAN_SUPPORT = 34, 776 IWM_UCODE_TLV_CAPA_UMAC_UPLOAD = 35, 777 IWM_UCODE_TLV_CAPA_EXTENDED_DTS_MEASURE = 64, 778 IWM_UCODE_TLV_CAPA_SHORT_PM_TIMEOUTS = 65, 779 IWM_UCODE_TLV_CAPA_BT_MPLUT_SUPPORT = 67, 780 IWM_UCODE_TLV_CAPA_MULTI_QUEUE_RX_SUPPORT = 68, 781 IWM_UCODE_TLV_CAPA_BEACON_ANT_SELECTION = 71, 782 IWM_UCODE_TLV_CAPA_BEACON_STORING = 72, 783 IWM_UCODE_TLV_CAPA_LAR_SUPPORT_V2 = 73, 784 IWM_UCODE_TLV_CAPA_CT_KILL_BY_FW = 74, 785 IWM_UCODE_TLV_CAPA_TEMP_THS_REPORT_SUPPORT = 75, 786 IWM_UCODE_TLV_CAPA_CTDP_SUPPORT = 76, 787 IWM_UCODE_TLV_CAPA_USNIFFER_UNIFIED = 77, 788 IWM_UCODE_TLV_CAPA_LMAC_UPLOAD = 79, 789 IWM_UCODE_TLV_CAPA_EXTEND_SHARED_MEM_CFG = 80, 790 IWM_UCODE_TLV_CAPA_LQM_SUPPORT = 81, 791 792 IWM_NUM_UCODE_TLV_CAPA = 128 793 }; 794 795 /* The default calibrate table size if not specified by firmware file */ 796 #define IWM_DEFAULT_STANDARD_PHY_CALIBRATE_TBL_SIZE 18 797 #define IWM_MAX_STANDARD_PHY_CALIBRATE_TBL_SIZE 19 798 #define IWM_MAX_PHY_CALIBRATE_TBL_SIZE 253 799 800 /* The default max probe length if not specified by the firmware file */ 801 #define IWM_DEFAULT_MAX_PROBE_LENGTH 200 802 803 /* 804 * enumeration of ucode section. 805 * This enumeration is used directly for older firmware (before 16.0). 806 * For new firmware, there can be up to 4 sections (see below) but the 807 * first one packaged into the firmware file is the DATA section and 808 * some debugging code accesses that. 809 */ 810 enum iwm_ucode_sec { 811 IWM_UCODE_SECTION_DATA, 812 IWM_UCODE_SECTION_INST, 813 }; 814 /* 815 * For 16.0 uCode and above, there is no differentiation between sections, 816 * just an offset to the HW address. 817 */ 818 #define IWM_CPU1_CPU2_SEPARATOR_SECTION 0xFFFFCCCC 819 #define IWM_PAGING_SEPARATOR_SECTION 0xAAAABBBB 820 821 /* uCode version contains 4 values: Major/Minor/API/Serial */ 822 #define IWM_UCODE_MAJOR(ver) (((ver) & 0xFF000000) >> 24) 823 #define IWM_UCODE_MINOR(ver) (((ver) & 0x00FF0000) >> 16) 824 #define IWM_UCODE_API(ver) (((ver) & 0x0000FF00) >> 8) 825 #define IWM_UCODE_SERIAL(ver) ((ver) & 0x000000FF) 826 827 /* 828 * Calibration control struct. 829 * Sent as part of the phy configuration command. 830 * @flow_trigger: bitmap for which calibrations to perform according to 831 * flow triggers. 832 * @event_trigger: bitmap for which calibrations to perform according to 833 * event triggers. 834 */ 835 struct iwm_tlv_calib_ctrl { 836 uint32_t flow_trigger; 837 uint32_t event_trigger; 838 } __packed; 839 840 enum iwm_fw_phy_cfg { 841 IWM_FW_PHY_CFG_RADIO_TYPE_POS = 0, 842 IWM_FW_PHY_CFG_RADIO_TYPE = 0x3 << IWM_FW_PHY_CFG_RADIO_TYPE_POS, 843 IWM_FW_PHY_CFG_RADIO_STEP_POS = 2, 844 IWM_FW_PHY_CFG_RADIO_STEP = 0x3 << IWM_FW_PHY_CFG_RADIO_STEP_POS, 845 IWM_FW_PHY_CFG_RADIO_DASH_POS = 4, 846 IWM_FW_PHY_CFG_RADIO_DASH = 0x3 << IWM_FW_PHY_CFG_RADIO_DASH_POS, 847 IWM_FW_PHY_CFG_TX_CHAIN_POS = 16, 848 IWM_FW_PHY_CFG_TX_CHAIN = 0xf << IWM_FW_PHY_CFG_TX_CHAIN_POS, 849 IWM_FW_PHY_CFG_RX_CHAIN_POS = 20, 850 IWM_FW_PHY_CFG_RX_CHAIN = 0xf << IWM_FW_PHY_CFG_RX_CHAIN_POS, 851 }; 852 853 #define IWM_UCODE_MAX_CS 1 854 855 /** 856 * struct iwm_fw_cipher_scheme - a cipher scheme supported by FW. 857 * @cipher: a cipher suite selector 858 * @flags: cipher scheme flags (currently reserved for a future use) 859 * @hdr_len: a size of MPDU security header 860 * @pn_len: a size of PN 861 * @pn_off: an offset of pn from the beginning of the security header 862 * @key_idx_off: an offset of key index byte in the security header 863 * @key_idx_mask: a bit mask of key_idx bits 864 * @key_idx_shift: bit shift needed to get key_idx 865 * @mic_len: mic length in bytes 866 * @hw_cipher: a HW cipher index used in host commands 867 */ 868 struct iwm_fw_cipher_scheme { 869 uint32_t cipher; 870 uint8_t flags; 871 uint8_t hdr_len; 872 uint8_t pn_len; 873 uint8_t pn_off; 874 uint8_t key_idx_off; 875 uint8_t key_idx_mask; 876 uint8_t key_idx_shift; 877 uint8_t mic_len; 878 uint8_t hw_cipher; 879 } __packed; 880 881 /** 882 * struct iwm_fw_cscheme_list - a cipher scheme list 883 * @size: a number of entries 884 * @cs: cipher scheme entries 885 */ 886 struct iwm_fw_cscheme_list { 887 uint8_t size; 888 struct iwm_fw_cipher_scheme cs[]; 889 } __packed; 890 891 /* 892 * END iwl-fw.h 893 */ 894 895 /* 896 * BEGIN iwl-fw-file.h 897 */ 898 899 /* v1/v2 uCode file layout */ 900 struct iwm_ucode_header { 901 uint32_t ver; /* major/minor/API/serial */ 902 union { 903 struct { 904 uint32_t inst_size; /* bytes of runtime code */ 905 uint32_t data_size; /* bytes of runtime data */ 906 uint32_t init_size; /* bytes of init code */ 907 uint32_t init_data_size; /* bytes of init data */ 908 uint32_t boot_size; /* bytes of bootstrap code */ 909 uint8_t data[0]; /* in same order as sizes */ 910 } v1; 911 struct { 912 uint32_t build; /* build number */ 913 uint32_t inst_size; /* bytes of runtime code */ 914 uint32_t data_size; /* bytes of runtime data */ 915 uint32_t init_size; /* bytes of init code */ 916 uint32_t init_data_size; /* bytes of init data */ 917 uint32_t boot_size; /* bytes of bootstrap code */ 918 uint8_t data[0]; /* in same order as sizes */ 919 } v2; 920 } u; 921 }; 922 923 /* 924 * new TLV uCode file layout 925 * 926 * The new TLV file format contains TLVs, that each specify 927 * some piece of data. 928 */ 929 930 enum iwm_ucode_tlv_type { 931 IWM_UCODE_TLV_INVALID = 0, /* unused */ 932 IWM_UCODE_TLV_INST = 1, 933 IWM_UCODE_TLV_DATA = 2, 934 IWM_UCODE_TLV_INIT = 3, 935 IWM_UCODE_TLV_INIT_DATA = 4, 936 IWM_UCODE_TLV_BOOT = 5, 937 IWM_UCODE_TLV_PROBE_MAX_LEN = 6, /* a uint32_t value */ 938 IWM_UCODE_TLV_PAN = 7, 939 IWM_UCODE_TLV_RUNT_EVTLOG_PTR = 8, 940 IWM_UCODE_TLV_RUNT_EVTLOG_SIZE = 9, 941 IWM_UCODE_TLV_RUNT_ERRLOG_PTR = 10, 942 IWM_UCODE_TLV_INIT_EVTLOG_PTR = 11, 943 IWM_UCODE_TLV_INIT_EVTLOG_SIZE = 12, 944 IWM_UCODE_TLV_INIT_ERRLOG_PTR = 13, 945 IWM_UCODE_TLV_ENHANCE_SENS_TBL = 14, 946 IWM_UCODE_TLV_PHY_CALIBRATION_SIZE = 15, 947 IWM_UCODE_TLV_WOWLAN_INST = 16, 948 IWM_UCODE_TLV_WOWLAN_DATA = 17, 949 IWM_UCODE_TLV_FLAGS = 18, 950 IWM_UCODE_TLV_SEC_RT = 19, 951 IWM_UCODE_TLV_SEC_INIT = 20, 952 IWM_UCODE_TLV_SEC_WOWLAN = 21, 953 IWM_UCODE_TLV_DEF_CALIB = 22, 954 IWM_UCODE_TLV_PHY_SKU = 23, 955 IWM_UCODE_TLV_SECURE_SEC_RT = 24, 956 IWM_UCODE_TLV_SECURE_SEC_INIT = 25, 957 IWM_UCODE_TLV_SECURE_SEC_WOWLAN = 26, 958 IWM_UCODE_TLV_NUM_OF_CPU = 27, 959 IWM_UCODE_TLV_CSCHEME = 28, 960 961 /* 962 * Following two are not in our base tag, but allow 963 * handling ucode version 9. 964 */ 965 IWM_UCODE_TLV_API_CHANGES_SET = 29, 966 IWM_UCODE_TLV_ENABLED_CAPABILITIES = 30, 967 968 IWM_UCODE_TLV_N_SCAN_CHANNELS = 31, 969 IWM_UCODE_TLV_PAGING = 32, 970 IWM_UCODE_TLV_SEC_RT_USNIFFER = 34, 971 IWM_UCODE_TLV_SDIO_ADMA_ADDR = 35, 972 IWM_UCODE_TLV_FW_VERSION = 36, 973 IWM_UCODE_TLV_FW_DBG_DEST = 38, 974 IWM_UCODE_TLV_FW_DBG_CONF = 39, 975 IWM_UCODE_TLV_FW_DBG_TRIGGER = 40, 976 IWM_UCODE_TLV_FW_GSCAN_CAPA = 50, 977 }; 978 979 struct iwm_ucode_tlv { 980 uint32_t type; /* see above */ 981 uint32_t length; /* not including type/length fields */ 982 uint8_t data[0]; 983 }; 984 985 struct iwm_ucode_api { 986 uint32_t api_index; 987 uint32_t api_flags; 988 } __packed; 989 990 struct iwm_ucode_capa { 991 uint32_t api_index; 992 uint32_t api_capa; 993 } __packed; 994 995 #define IWM_TLV_UCODE_MAGIC 0x0a4c5749 996 997 struct iwm_tlv_ucode_header { 998 /* 999 * The TLV style ucode header is distinguished from 1000 * the v1/v2 style header by first four bytes being 1001 * zero, as such is an invalid combination of 1002 * major/minor/API/serial versions. 1003 */ 1004 uint32_t zero; 1005 uint32_t magic; 1006 uint8_t human_readable[64]; 1007 uint32_t ver; /* major/minor/API/serial */ 1008 uint32_t build; 1009 uint64_t ignore; 1010 /* 1011 * The data contained herein has a TLV layout, 1012 * see above for the TLV header and types. 1013 * Note that each TLV is padded to a length 1014 * that is a multiple of 4 for alignment. 1015 */ 1016 uint8_t data[0]; 1017 }; 1018 1019 /* 1020 * END iwl-fw-file.h 1021 */ 1022 1023 /* 1024 * BEGIN iwl-prph.h 1025 */ 1026 1027 /* 1028 * Registers in this file are internal, not PCI bus memory mapped. 1029 * Driver accesses these via IWM_HBUS_TARG_PRPH_* registers. 1030 */ 1031 #define IWM_PRPH_BASE (0x00000) 1032 #define IWM_PRPH_END (0xFFFFF) 1033 1034 /* APMG (power management) constants */ 1035 #define IWM_APMG_BASE (IWM_PRPH_BASE + 0x3000) 1036 #define IWM_APMG_CLK_CTRL_REG (IWM_APMG_BASE + 0x0000) 1037 #define IWM_APMG_CLK_EN_REG (IWM_APMG_BASE + 0x0004) 1038 #define IWM_APMG_CLK_DIS_REG (IWM_APMG_BASE + 0x0008) 1039 #define IWM_APMG_PS_CTRL_REG (IWM_APMG_BASE + 0x000c) 1040 #define IWM_APMG_PCIDEV_STT_REG (IWM_APMG_BASE + 0x0010) 1041 #define IWM_APMG_RFKILL_REG (IWM_APMG_BASE + 0x0014) 1042 #define IWM_APMG_RTC_INT_STT_REG (IWM_APMG_BASE + 0x001c) 1043 #define IWM_APMG_RTC_INT_MSK_REG (IWM_APMG_BASE + 0x0020) 1044 #define IWM_APMG_DIGITAL_SVR_REG (IWM_APMG_BASE + 0x0058) 1045 #define IWM_APMG_ANALOG_SVR_REG (IWM_APMG_BASE + 0x006C) 1046 1047 #define IWM_APMS_CLK_VAL_MRB_FUNC_MODE (0x00000001) 1048 #define IWM_APMG_CLK_VAL_DMA_CLK_RQT (0x00000200) 1049 #define IWM_APMG_CLK_VAL_BSM_CLK_RQT (0x00000800) 1050 1051 #define IWM_APMG_PS_CTRL_EARLY_PWR_OFF_RESET_DIS (0x00400000) 1052 #define IWM_APMG_PS_CTRL_VAL_RESET_REQ (0x04000000) 1053 #define IWM_APMG_PS_CTRL_MSK_PWR_SRC (0x03000000) 1054 #define IWM_APMG_PS_CTRL_VAL_PWR_SRC_VMAIN (0x00000000) 1055 #define IWM_APMG_PS_CTRL_VAL_PWR_SRC_VAUX (0x02000000) 1056 #define IWM_APMG_SVR_VOLTAGE_CONFIG_BIT_MSK (0x000001E0) /* bit 8:5 */ 1057 #define IWM_APMG_SVR_DIGITAL_VOLTAGE_1_32 (0x00000060) 1058 1059 #define IWM_APMG_PCIDEV_STT_VAL_L1_ACT_DIS (0x00000800) 1060 1061 #define IWM_APMG_RTC_INT_STT_RFKILL (0x10000000) 1062 1063 /* Device system time */ 1064 #define IWM_DEVICE_SYSTEM_TIME_REG 0xA0206C 1065 1066 /* Device NMI register */ 1067 #define IWM_DEVICE_SET_NMI_REG 0x00a01c30 1068 #define IWM_DEVICE_SET_NMI_VAL_HW 0x01 1069 #define IWM_DEVICE_SET_NMI_VAL_DRV 0x80 1070 #define IWM_DEVICE_SET_NMI_8000_REG 0x00a01c24 1071 #define IWM_DEVICE_SET_NMI_8000_VAL 0x1000000 1072 1073 /* 1074 * Device reset for family 8000 1075 * write to bit 24 in order to reset the CPU 1076 */ 1077 #define IWM_RELEASE_CPU_RESET 0x300c 1078 #define IWM_RELEASE_CPU_RESET_BIT 0x1000000 1079 1080 1081 /***************************************************************************** 1082 * 7000/3000 series SHR DTS addresses * 1083 *****************************************************************************/ 1084 1085 #define IWM_SHR_MISC_WFM_DTS_EN (0x00a10024) 1086 #define IWM_DTSC_CFG_MODE (0x00a10604) 1087 #define IWM_DTSC_VREF_AVG (0x00a10648) 1088 #define IWM_DTSC_VREF5_AVG (0x00a1064c) 1089 #define IWM_DTSC_CFG_MODE_PERIODIC (0x2) 1090 #define IWM_DTSC_PTAT_AVG (0x00a10650) 1091 1092 1093 /** 1094 * Tx Scheduler 1095 * 1096 * The Tx Scheduler selects the next frame to be transmitted, choosing TFDs 1097 * (Transmit Frame Descriptors) from up to 16 circular Tx queues resident in 1098 * host DRAM. It steers each frame's Tx command (which contains the frame 1099 * data) into one of up to 7 prioritized Tx DMA FIFO channels within the 1100 * device. A queue maps to only one (selectable by driver) Tx DMA channel, 1101 * but one DMA channel may take input from several queues. 1102 * 1103 * Tx DMA FIFOs have dedicated purposes. 1104 * 1105 * For 5000 series and up, they are used differently 1106 * (cf. iwl5000_default_queue_to_tx_fifo in iwl-5000.c): 1107 * 1108 * 0 -- EDCA BK (background) frames, lowest priority 1109 * 1 -- EDCA BE (best effort) frames, normal priority 1110 * 2 -- EDCA VI (video) frames, higher priority 1111 * 3 -- EDCA VO (voice) and management frames, highest priority 1112 * 4 -- unused 1113 * 5 -- unused 1114 * 6 -- unused 1115 * 7 -- Commands 1116 * 1117 * Driver should normally map queues 0-6 to Tx DMA/FIFO channels 0-6. 1118 * In addition, driver can map the remaining queues to Tx DMA/FIFO 1119 * channels 0-3 to support 11n aggregation via EDCA DMA channels. 1120 * 1121 * The driver sets up each queue to work in one of two modes: 1122 * 1123 * 1) Scheduler-Ack, in which the scheduler automatically supports a 1124 * block-ack (BA) window of up to 64 TFDs. In this mode, each queue 1125 * contains TFDs for a unique combination of Recipient Address (RA) 1126 * and Traffic Identifier (TID), that is, traffic of a given 1127 * Quality-Of-Service (QOS) priority, destined for a single station. 1128 * 1129 * In scheduler-ack mode, the scheduler keeps track of the Tx status of 1130 * each frame within the BA window, including whether it's been transmitted, 1131 * and whether it's been acknowledged by the receiving station. The device 1132 * automatically processes block-acks received from the receiving STA, 1133 * and reschedules un-acked frames to be retransmitted (successful 1134 * Tx completion may end up being out-of-order). 1135 * 1136 * The driver must maintain the queue's Byte Count table in host DRAM 1137 * for this mode. 1138 * This mode does not support fragmentation. 1139 * 1140 * 2) FIFO (a.k.a. non-Scheduler-ACK), in which each TFD is processed in order. 1141 * The device may automatically retry Tx, but will retry only one frame 1142 * at a time, until receiving ACK from receiving station, or reaching 1143 * retry limit and giving up. 1144 * 1145 * The command queue (#4/#9) must use this mode! 1146 * This mode does not require use of the Byte Count table in host DRAM. 1147 * 1148 * Driver controls scheduler operation via 3 means: 1149 * 1) Scheduler registers 1150 * 2) Shared scheduler data base in internal SRAM 1151 * 3) Shared data in host DRAM 1152 * 1153 * Initialization: 1154 * 1155 * When loading, driver should allocate memory for: 1156 * 1) 16 TFD circular buffers, each with space for (typically) 256 TFDs. 1157 * 2) 16 Byte Count circular buffers in 16 KBytes contiguous memory 1158 * (1024 bytes for each queue). 1159 * 1160 * After receiving "Alive" response from uCode, driver must initialize 1161 * the scheduler (especially for queue #4/#9, the command queue, otherwise 1162 * the driver can't issue commands!): 1163 */ 1164 #define IWM_SCD_MEM_LOWER_BOUND (0x0000) 1165 1166 /** 1167 * Max Tx window size is the max number of contiguous TFDs that the scheduler 1168 * can keep track of at one time when creating block-ack chains of frames. 1169 * Note that "64" matches the number of ack bits in a block-ack packet. 1170 */ 1171 #define IWM_SCD_WIN_SIZE 64 1172 #define IWM_SCD_FRAME_LIMIT 64 1173 1174 #define IWM_SCD_TXFIFO_POS_TID (0) 1175 #define IWM_SCD_TXFIFO_POS_RA (4) 1176 #define IWM_SCD_QUEUE_RA_TID_MAP_RATID_MSK (0x01FF) 1177 1178 /* agn SCD */ 1179 #define IWM_SCD_QUEUE_STTS_REG_POS_TXF (0) 1180 #define IWM_SCD_QUEUE_STTS_REG_POS_ACTIVE (3) 1181 #define IWM_SCD_QUEUE_STTS_REG_POS_WSL (4) 1182 #define IWM_SCD_QUEUE_STTS_REG_POS_SCD_ACT_EN (19) 1183 #define IWM_SCD_QUEUE_STTS_REG_MSK (0x017F0000) 1184 1185 #define IWM_SCD_QUEUE_CTX_REG1_CREDIT_POS (8) 1186 #define IWM_SCD_QUEUE_CTX_REG1_CREDIT_MSK (0x00FFFF00) 1187 #define IWM_SCD_QUEUE_CTX_REG1_SUPER_CREDIT_POS (24) 1188 #define IWM_SCD_QUEUE_CTX_REG1_SUPER_CREDIT_MSK (0xFF000000) 1189 #define IWM_SCD_QUEUE_CTX_REG2_WIN_SIZE_POS (0) 1190 #define IWM_SCD_QUEUE_CTX_REG2_WIN_SIZE_MSK (0x0000007F) 1191 #define IWM_SCD_QUEUE_CTX_REG2_FRAME_LIMIT_POS (16) 1192 #define IWM_SCD_QUEUE_CTX_REG2_FRAME_LIMIT_MSK (0x007F0000) 1193 #define IWM_SCD_GP_CTRL_ENABLE_31_QUEUES (1 << 0) 1194 #define IWM_SCD_GP_CTRL_AUTO_ACTIVE_MODE (1 << 18) 1195 1196 /* Context Data */ 1197 #define IWM_SCD_CONTEXT_MEM_LOWER_BOUND (IWM_SCD_MEM_LOWER_BOUND + 0x600) 1198 #define IWM_SCD_CONTEXT_MEM_UPPER_BOUND (IWM_SCD_MEM_LOWER_BOUND + 0x6A0) 1199 1200 /* Tx status */ 1201 #define IWM_SCD_TX_STTS_MEM_LOWER_BOUND (IWM_SCD_MEM_LOWER_BOUND + 0x6A0) 1202 #define IWM_SCD_TX_STTS_MEM_UPPER_BOUND (IWM_SCD_MEM_LOWER_BOUND + 0x7E0) 1203 1204 /* Translation Data */ 1205 #define IWM_SCD_TRANS_TBL_MEM_LOWER_BOUND (IWM_SCD_MEM_LOWER_BOUND + 0x7E0) 1206 #define IWM_SCD_TRANS_TBL_MEM_UPPER_BOUND (IWM_SCD_MEM_LOWER_BOUND + 0x808) 1207 1208 #define IWM_SCD_CONTEXT_QUEUE_OFFSET(x)\ 1209 (IWM_SCD_CONTEXT_MEM_LOWER_BOUND + ((x) * 8)) 1210 1211 #define IWM_SCD_TX_STTS_QUEUE_OFFSET(x)\ 1212 (IWM_SCD_TX_STTS_MEM_LOWER_BOUND + ((x) * 16)) 1213 1214 #define IWM_SCD_TRANS_TBL_OFFSET_QUEUE(x) \ 1215 ((IWM_SCD_TRANS_TBL_MEM_LOWER_BOUND + ((x) * 2)) & 0xfffc) 1216 1217 #define IWM_SCD_BASE (IWM_PRPH_BASE + 0xa02c00) 1218 1219 #define IWM_SCD_SRAM_BASE_ADDR (IWM_SCD_BASE + 0x0) 1220 #define IWM_SCD_DRAM_BASE_ADDR (IWM_SCD_BASE + 0x8) 1221 #define IWM_SCD_AIT (IWM_SCD_BASE + 0x0c) 1222 #define IWM_SCD_TXFACT (IWM_SCD_BASE + 0x10) 1223 #define IWM_SCD_ACTIVE (IWM_SCD_BASE + 0x14) 1224 #define IWM_SCD_QUEUECHAIN_SEL (IWM_SCD_BASE + 0xe8) 1225 #define IWM_SCD_CHAINEXT_EN (IWM_SCD_BASE + 0x244) 1226 #define IWM_SCD_AGGR_SEL (IWM_SCD_BASE + 0x248) 1227 #define IWM_SCD_INTERRUPT_MASK (IWM_SCD_BASE + 0x108) 1228 #define IWM_SCD_GP_CTRL (IWM_SCD_BASE + 0x1a8) 1229 #define IWM_SCD_EN_CTRL (IWM_SCD_BASE + 0x254) 1230 1231 static inline unsigned int IWM_SCD_QUEUE_WRPTR(unsigned int chnl) 1232 { 1233 if (chnl < 20) 1234 return IWM_SCD_BASE + 0x18 + chnl * 4; 1235 return IWM_SCD_BASE + 0x284 + (chnl - 20) * 4; 1236 } 1237 1238 static inline unsigned int IWM_SCD_QUEUE_RDPTR(unsigned int chnl) 1239 { 1240 if (chnl < 20) 1241 return IWM_SCD_BASE + 0x68 + chnl * 4; 1242 return IWM_SCD_BASE + 0x2B4 + (chnl - 20) * 4; 1243 } 1244 1245 static inline unsigned int IWM_SCD_QUEUE_STATUS_BITS(unsigned int chnl) 1246 { 1247 if (chnl < 20) 1248 return IWM_SCD_BASE + 0x10c + chnl * 4; 1249 return IWM_SCD_BASE + 0x384 + (chnl - 20) * 4; 1250 } 1251 1252 /*********************** END TX SCHEDULER *************************************/ 1253 1254 /* Oscillator clock */ 1255 #define IWM_OSC_CLK (0xa04068) 1256 #define IWM_OSC_CLK_FORCE_CONTROL (0x8) 1257 1258 /* 1259 * END iwl-prph.h 1260 */ 1261 1262 /* 1263 * BEGIN iwl-fh.h 1264 */ 1265 1266 /****************************/ 1267 /* Flow Handler Definitions */ 1268 /****************************/ 1269 1270 /** 1271 * This I/O area is directly read/writable by driver (e.g. Linux uses writel()) 1272 * Addresses are offsets from device's PCI hardware base address. 1273 */ 1274 #define IWM_FH_MEM_LOWER_BOUND (0x1000) 1275 #define IWM_FH_MEM_UPPER_BOUND (0x2000) 1276 1277 /** 1278 * Keep-Warm (KW) buffer base address. 1279 * 1280 * Driver must allocate a 4KByte buffer that is for keeping the 1281 * host DRAM powered on (via dummy accesses to DRAM) to maintain low-latency 1282 * DRAM access when doing Txing or Rxing. The dummy accesses prevent host 1283 * from going into a power-savings mode that would cause higher DRAM latency, 1284 * and possible data over/under-runs, before all Tx/Rx is complete. 1285 * 1286 * Driver loads IWM_FH_KW_MEM_ADDR_REG with the physical address (bits 35:4) 1287 * of the buffer, which must be 4K aligned. Once this is set up, the device 1288 * automatically invokes keep-warm accesses when normal accesses might not 1289 * be sufficient to maintain fast DRAM response. 1290 * 1291 * Bit fields: 1292 * 31-0: Keep-warm buffer physical base address [35:4], must be 4K aligned 1293 */ 1294 #define IWM_FH_KW_MEM_ADDR_REG (IWM_FH_MEM_LOWER_BOUND + 0x97C) 1295 1296 1297 /** 1298 * TFD Circular Buffers Base (CBBC) addresses 1299 * 1300 * Device has 16 base pointer registers, one for each of 16 host-DRAM-resident 1301 * circular buffers (CBs/queues) containing Transmit Frame Descriptors (TFDs) 1302 * (see struct iwm_tfd_frame). These 16 pointer registers are offset by 0x04 1303 * bytes from one another. Each TFD circular buffer in DRAM must be 256-byte 1304 * aligned (address bits 0-7 must be 0). 1305 * Later devices have 20 (5000 series) or 30 (higher) queues, but the registers 1306 * for them are in different places. 1307 * 1308 * Bit fields in each pointer register: 1309 * 27-0: TFD CB physical base address [35:8], must be 256-byte aligned 1310 */ 1311 #define IWM_FH_MEM_CBBC_0_15_LOWER_BOUND (IWM_FH_MEM_LOWER_BOUND + 0x9D0) 1312 #define IWM_FH_MEM_CBBC_0_15_UPPER_BOUN (IWM_FH_MEM_LOWER_BOUND + 0xA10) 1313 #define IWM_FH_MEM_CBBC_16_19_LOWER_BOUND (IWM_FH_MEM_LOWER_BOUND + 0xBF0) 1314 #define IWM_FH_MEM_CBBC_16_19_UPPER_BOUND (IWM_FH_MEM_LOWER_BOUND + 0xC00) 1315 #define IWM_FH_MEM_CBBC_20_31_LOWER_BOUND (IWM_FH_MEM_LOWER_BOUND + 0xB20) 1316 #define IWM_FH_MEM_CBBC_20_31_UPPER_BOUND (IWM_FH_MEM_LOWER_BOUND + 0xB80) 1317 1318 /* Find TFD CB base pointer for given queue */ 1319 static inline unsigned int IWM_FH_MEM_CBBC_QUEUE(unsigned int chnl) 1320 { 1321 if (chnl < 16) 1322 return IWM_FH_MEM_CBBC_0_15_LOWER_BOUND + 4 * chnl; 1323 if (chnl < 20) 1324 return IWM_FH_MEM_CBBC_16_19_LOWER_BOUND + 4 * (chnl - 16); 1325 return IWM_FH_MEM_CBBC_20_31_LOWER_BOUND + 4 * (chnl - 20); 1326 } 1327 1328 1329 /** 1330 * Rx SRAM Control and Status Registers (RSCSR) 1331 * 1332 * These registers provide handshake between driver and device for the Rx queue 1333 * (this queue handles *all* command responses, notifications, Rx data, etc. 1334 * sent from uCode to host driver). Unlike Tx, there is only one Rx 1335 * queue, and only one Rx DMA/FIFO channel. Also unlike Tx, which can 1336 * concatenate up to 20 DRAM buffers to form a Tx frame, each Receive Buffer 1337 * Descriptor (RBD) points to only one Rx Buffer (RB); there is a 1:1 1338 * mapping between RBDs and RBs. 1339 * 1340 * Driver must allocate host DRAM memory for the following, and set the 1341 * physical address of each into device registers: 1342 * 1343 * 1) Receive Buffer Descriptor (RBD) circular buffer (CB), typically with 256 1344 * entries (although any power of 2, up to 4096, is selectable by driver). 1345 * Each entry (1 dword) points to a receive buffer (RB) of consistent size 1346 * (typically 4K, although 8K or 16K are also selectable by driver). 1347 * Driver sets up RB size and number of RBDs in the CB via Rx config 1348 * register IWM_FH_MEM_RCSR_CHNL0_CONFIG_REG. 1349 * 1350 * Bit fields within one RBD: 1351 * 27-0: Receive Buffer physical address bits [35:8], 256-byte aligned 1352 * 1353 * Driver sets physical address [35:8] of base of RBD circular buffer 1354 * into IWM_FH_RSCSR_CHNL0_RBDCB_BASE_REG [27:0]. 1355 * 1356 * 2) Rx status buffer, 8 bytes, in which uCode indicates which Rx Buffers 1357 * (RBs) have been filled, via a "write pointer", actually the index of 1358 * the RB's corresponding RBD within the circular buffer. Driver sets 1359 * physical address [35:4] into IWM_FH_RSCSR_CHNL0_STTS_WPTR_REG [31:0]. 1360 * 1361 * Bit fields in lower dword of Rx status buffer (upper dword not used 1362 * by driver: 1363 * 31-12: Not used by driver 1364 * 11- 0: Index of last filled Rx buffer descriptor 1365 * (device writes, driver reads this value) 1366 * 1367 * As the driver prepares Receive Buffers (RBs) for device to fill, driver must 1368 * enter pointers to these RBs into contiguous RBD circular buffer entries, 1369 * and update the device's "write" index register, 1370 * IWM_FH_RSCSR_CHNL0_RBDCB_WPTR_REG. 1371 * 1372 * This "write" index corresponds to the *next* RBD that the driver will make 1373 * available, i.e. one RBD past the tail of the ready-to-fill RBDs within 1374 * the circular buffer. This value should initially be 0 (before preparing any 1375 * RBs), should be 8 after preparing the first 8 RBs (for example), and must 1376 * wrap back to 0 at the end of the circular buffer (but don't wrap before 1377 * "read" index has advanced past 1! See below). 1378 * NOTE: DEVICE EXPECTS THE WRITE INDEX TO BE INCREMENTED IN MULTIPLES OF 8. 1379 * 1380 * As the device fills RBs (referenced from contiguous RBDs within the circular 1381 * buffer), it updates the Rx status buffer in host DRAM, 2) described above, 1382 * to tell the driver the index of the latest filled RBD. The driver must 1383 * read this "read" index from DRAM after receiving an Rx interrupt from device 1384 * 1385 * The driver must also internally keep track of a third index, which is the 1386 * next RBD to process. When receiving an Rx interrupt, driver should process 1387 * all filled but unprocessed RBs up to, but not including, the RB 1388 * corresponding to the "read" index. For example, if "read" index becomes "1", 1389 * driver may process the RB pointed to by RBD 0. Depending on volume of 1390 * traffic, there may be many RBs to process. 1391 * 1392 * If read index == write index, device thinks there is no room to put new data. 1393 * Due to this, the maximum number of filled RBs is 255, instead of 256. To 1394 * be safe, make sure that there is a gap of at least 2 RBDs between "write" 1395 * and "read" indexes; that is, make sure that there are no more than 254 1396 * buffers waiting to be filled. 1397 */ 1398 #define IWM_FH_MEM_RSCSR_LOWER_BOUND (IWM_FH_MEM_LOWER_BOUND + 0xBC0) 1399 #define IWM_FH_MEM_RSCSR_UPPER_BOUND (IWM_FH_MEM_LOWER_BOUND + 0xC00) 1400 #define IWM_FH_MEM_RSCSR_CHNL0 (IWM_FH_MEM_RSCSR_LOWER_BOUND) 1401 1402 /** 1403 * Physical base address of 8-byte Rx Status buffer. 1404 * Bit fields: 1405 * 31-0: Rx status buffer physical base address [35:4], must 16-byte aligned. 1406 */ 1407 #define IWM_FH_RSCSR_CHNL0_STTS_WPTR_REG (IWM_FH_MEM_RSCSR_CHNL0) 1408 1409 /** 1410 * Physical base address of Rx Buffer Descriptor Circular Buffer. 1411 * Bit fields: 1412 * 27-0: RBD CD physical base address [35:8], must be 256-byte aligned. 1413 */ 1414 #define IWM_FH_RSCSR_CHNL0_RBDCB_BASE_REG (IWM_FH_MEM_RSCSR_CHNL0 + 0x004) 1415 1416 /** 1417 * Rx write pointer (index, really!). 1418 * Bit fields: 1419 * 11-0: Index of driver's most recent prepared-to-be-filled RBD, + 1. 1420 * NOTE: For 256-entry circular buffer, use only bits [7:0]. 1421 */ 1422 #define IWM_FH_RSCSR_CHNL0_RBDCB_WPTR_REG (IWM_FH_MEM_RSCSR_CHNL0 + 0x008) 1423 #define IWM_FH_RSCSR_CHNL0_WPTR (IWM_FH_RSCSR_CHNL0_RBDCB_WPTR_REG) 1424 1425 #define IWM_FW_RSCSR_CHNL0_RXDCB_RDPTR_REG (IWM_FH_MEM_RSCSR_CHNL0 + 0x00c) 1426 #define IWM_FH_RSCSR_CHNL0_RDPTR IWM_FW_RSCSR_CHNL0_RXDCB_RDPTR_REG 1427 1428 /** 1429 * Rx Config/Status Registers (RCSR) 1430 * Rx Config Reg for channel 0 (only channel used) 1431 * 1432 * Driver must initialize IWM_FH_MEM_RCSR_CHNL0_CONFIG_REG as follows for 1433 * normal operation (see bit fields). 1434 * 1435 * Clearing IWM_FH_MEM_RCSR_CHNL0_CONFIG_REG to 0 turns off Rx DMA. 1436 * Driver should poll IWM_FH_MEM_RSSR_RX_STATUS_REG for 1437 * IWM_FH_RSSR_CHNL0_RX_STATUS_CHNL_IDLE (bit 24) before continuing. 1438 * 1439 * Bit fields: 1440 * 31-30: Rx DMA channel enable: '00' off/pause, '01' pause at end of frame, 1441 * '10' operate normally 1442 * 29-24: reserved 1443 * 23-20: # RBDs in circular buffer = 2^value; use "8" for 256 RBDs (normal), 1444 * min "5" for 32 RBDs, max "12" for 4096 RBDs. 1445 * 19-18: reserved 1446 * 17-16: size of each receive buffer; '00' 4K (normal), '01' 8K, 1447 * '10' 12K, '11' 16K. 1448 * 15-14: reserved 1449 * 13-12: IRQ destination; '00' none, '01' host driver (normal operation) 1450 * 11- 4: timeout for closing Rx buffer and interrupting host (units 32 usec) 1451 * typical value 0x10 (about 1/2 msec) 1452 * 3- 0: reserved 1453 */ 1454 #define IWM_FH_MEM_RCSR_LOWER_BOUND (IWM_FH_MEM_LOWER_BOUND + 0xC00) 1455 #define IWM_FH_MEM_RCSR_UPPER_BOUND (IWM_FH_MEM_LOWER_BOUND + 0xCC0) 1456 #define IWM_FH_MEM_RCSR_CHNL0 (IWM_FH_MEM_RCSR_LOWER_BOUND) 1457 1458 #define IWM_FH_MEM_RCSR_CHNL0_CONFIG_REG (IWM_FH_MEM_RCSR_CHNL0) 1459 #define IWM_FH_MEM_RCSR_CHNL0_RBDCB_WPTR (IWM_FH_MEM_RCSR_CHNL0 + 0x8) 1460 #define IWM_FH_MEM_RCSR_CHNL0_FLUSH_RB_REQ (IWM_FH_MEM_RCSR_CHNL0 + 0x10) 1461 1462 #define IWM_FH_RCSR_CHNL0_RX_CONFIG_RB_TIMEOUT_MSK (0x00000FF0) /* bits 4-11 */ 1463 #define IWM_FH_RCSR_CHNL0_RX_CONFIG_IRQ_DEST_MSK (0x00001000) /* bits 12 */ 1464 #define IWM_FH_RCSR_CHNL0_RX_CONFIG_SINGLE_FRAME_MSK (0x00008000) /* bit 15 */ 1465 #define IWM_FH_RCSR_CHNL0_RX_CONFIG_RB_SIZE_MSK (0x00030000) /* bits 16-17 */ 1466 #define IWM_FH_RCSR_CHNL0_RX_CONFIG_RBDBC_SIZE_MSK (0x00F00000) /* bits 20-23 */ 1467 #define IWM_FH_RCSR_CHNL0_RX_CONFIG_DMA_CHNL_EN_MSK (0xC0000000) /* bits 30-31*/ 1468 1469 #define IWM_FH_RCSR_RX_CONFIG_RBDCB_SIZE_POS (20) 1470 #define IWM_FH_RCSR_RX_CONFIG_REG_IRQ_RBTH_POS (4) 1471 #define IWM_RX_RB_TIMEOUT (0x11) 1472 1473 #define IWM_FH_RCSR_RX_CONFIG_CHNL_EN_PAUSE_VAL (0x00000000) 1474 #define IWM_FH_RCSR_RX_CONFIG_CHNL_EN_PAUSE_EOF_VAL (0x40000000) 1475 #define IWM_FH_RCSR_RX_CONFIG_CHNL_EN_ENABLE_VAL (0x80000000) 1476 1477 #define IWM_FH_RCSR_RX_CONFIG_REG_VAL_RB_SIZE_4K (0x00000000) 1478 #define IWM_FH_RCSR_RX_CONFIG_REG_VAL_RB_SIZE_8K (0x00010000) 1479 #define IWM_FH_RCSR_RX_CONFIG_REG_VAL_RB_SIZE_12K (0x00020000) 1480 #define IWM_FH_RCSR_RX_CONFIG_REG_VAL_RB_SIZE_16K (0x00030000) 1481 1482 #define IWM_FH_RCSR_CHNL0_RX_IGNORE_RXF_EMPTY (0x00000004) 1483 #define IWM_FH_RCSR_CHNL0_RX_CONFIG_IRQ_DEST_NO_INT_VAL (0x00000000) 1484 #define IWM_FH_RCSR_CHNL0_RX_CONFIG_IRQ_DEST_INT_HOST_VAL (0x00001000) 1485 1486 /** 1487 * Rx Shared Status Registers (RSSR) 1488 * 1489 * After stopping Rx DMA channel (writing 0 to 1490 * IWM_FH_MEM_RCSR_CHNL0_CONFIG_REG), driver must poll 1491 * IWM_FH_MEM_RSSR_RX_STATUS_REG until Rx channel is idle. 1492 * 1493 * Bit fields: 1494 * 24: 1 = Channel 0 is idle 1495 * 1496 * IWM_FH_MEM_RSSR_SHARED_CTRL_REG and IWM_FH_MEM_RSSR_RX_ENABLE_ERR_IRQ2DRV 1497 * contain default values that should not be altered by the driver. 1498 */ 1499 #define IWM_FH_MEM_RSSR_LOWER_BOUND (IWM_FH_MEM_LOWER_BOUND + 0xC40) 1500 #define IWM_FH_MEM_RSSR_UPPER_BOUND (IWM_FH_MEM_LOWER_BOUND + 0xD00) 1501 1502 #define IWM_FH_MEM_RSSR_SHARED_CTRL_REG (IWM_FH_MEM_RSSR_LOWER_BOUND) 1503 #define IWM_FH_MEM_RSSR_RX_STATUS_REG (IWM_FH_MEM_RSSR_LOWER_BOUND + 0x004) 1504 #define IWM_FH_MEM_RSSR_RX_ENABLE_ERR_IRQ2DRV\ 1505 (IWM_FH_MEM_RSSR_LOWER_BOUND + 0x008) 1506 1507 #define IWM_FH_RSSR_CHNL0_RX_STATUS_CHNL_IDLE (0x01000000) 1508 1509 #define IWM_FH_MEM_TFDIB_REG1_ADDR_BITSHIFT 28 1510 1511 /* TFDB Area - TFDs buffer table */ 1512 #define IWM_FH_MEM_TFDIB_DRAM_ADDR_LSB_MSK (0xFFFFFFFF) 1513 #define IWM_FH_TFDIB_LOWER_BOUND (IWM_FH_MEM_LOWER_BOUND + 0x900) 1514 #define IWM_FH_TFDIB_UPPER_BOUND (IWM_FH_MEM_LOWER_BOUND + 0x958) 1515 #define IWM_FH_TFDIB_CTRL0_REG(_chnl) (IWM_FH_TFDIB_LOWER_BOUND + 0x8 * (_chnl)) 1516 #define IWM_FH_TFDIB_CTRL1_REG(_chnl) (IWM_FH_TFDIB_LOWER_BOUND + 0x8 * (_chnl) + 0x4) 1517 1518 /** 1519 * Transmit DMA Channel Control/Status Registers (TCSR) 1520 * 1521 * Device has one configuration register for each of 8 Tx DMA/FIFO channels 1522 * supported in hardware (don't confuse these with the 16 Tx queues in DRAM, 1523 * which feed the DMA/FIFO channels); config regs are separated by 0x20 bytes. 1524 * 1525 * To use a Tx DMA channel, driver must initialize its 1526 * IWM_FH_TCSR_CHNL_TX_CONFIG_REG(chnl) with: 1527 * 1528 * IWM_FH_TCSR_TX_CONFIG_REG_VAL_DMA_CHNL_ENABLE | 1529 * IWM_FH_TCSR_TX_CONFIG_REG_VAL_DMA_CREDIT_ENABLE_VAL 1530 * 1531 * All other bits should be 0. 1532 * 1533 * Bit fields: 1534 * 31-30: Tx DMA channel enable: '00' off/pause, '01' pause at end of frame, 1535 * '10' operate normally 1536 * 29- 4: Reserved, set to "0" 1537 * 3: Enable internal DMA requests (1, normal operation), disable (0) 1538 * 2- 0: Reserved, set to "0" 1539 */ 1540 #define IWM_FH_TCSR_LOWER_BOUND (IWM_FH_MEM_LOWER_BOUND + 0xD00) 1541 #define IWM_FH_TCSR_UPPER_BOUND (IWM_FH_MEM_LOWER_BOUND + 0xE60) 1542 1543 /* Find Control/Status reg for given Tx DMA/FIFO channel */ 1544 #define IWM_FH_TCSR_CHNL_NUM (8) 1545 1546 /* TCSR: tx_config register values */ 1547 #define IWM_FH_TCSR_CHNL_TX_CONFIG_REG(_chnl) \ 1548 (IWM_FH_TCSR_LOWER_BOUND + 0x20 * (_chnl)) 1549 #define IWM_FH_TCSR_CHNL_TX_CREDIT_REG(_chnl) \ 1550 (IWM_FH_TCSR_LOWER_BOUND + 0x20 * (_chnl) + 0x4) 1551 #define IWM_FH_TCSR_CHNL_TX_BUF_STS_REG(_chnl) \ 1552 (IWM_FH_TCSR_LOWER_BOUND + 0x20 * (_chnl) + 0x8) 1553 1554 #define IWM_FH_TCSR_TX_CONFIG_REG_VAL_MSG_MODE_TXF (0x00000000) 1555 #define IWM_FH_TCSR_TX_CONFIG_REG_VAL_MSG_MODE_DRV (0x00000001) 1556 1557 #define IWM_FH_TCSR_TX_CONFIG_REG_VAL_DMA_CREDIT_DISABLE (0x00000000) 1558 #define IWM_FH_TCSR_TX_CONFIG_REG_VAL_DMA_CREDIT_ENABLE (0x00000008) 1559 1560 #define IWM_FH_TCSR_TX_CONFIG_REG_VAL_CIRQ_HOST_NOINT (0x00000000) 1561 #define IWM_FH_TCSR_TX_CONFIG_REG_VAL_CIRQ_HOST_ENDTFD (0x00100000) 1562 #define IWM_FH_TCSR_TX_CONFIG_REG_VAL_CIRQ_HOST_IFTFD (0x00200000) 1563 1564 #define IWM_FH_TCSR_TX_CONFIG_REG_VAL_CIRQ_RTC_NOINT (0x00000000) 1565 #define IWM_FH_TCSR_TX_CONFIG_REG_VAL_CIRQ_RTC_ENDTFD (0x00400000) 1566 #define IWM_FH_TCSR_TX_CONFIG_REG_VAL_CIRQ_RTC_IFTFD (0x00800000) 1567 1568 #define IWM_FH_TCSR_TX_CONFIG_REG_VAL_DMA_CHNL_PAUSE (0x00000000) 1569 #define IWM_FH_TCSR_TX_CONFIG_REG_VAL_DMA_CHNL_PAUSE_EOF (0x40000000) 1570 #define IWM_FH_TCSR_TX_CONFIG_REG_VAL_DMA_CHNL_ENABLE (0x80000000) 1571 1572 #define IWM_FH_TCSR_CHNL_TX_BUF_STS_REG_VAL_TFDB_EMPTY (0x00000000) 1573 #define IWM_FH_TCSR_CHNL_TX_BUF_STS_REG_VAL_TFDB_WAIT (0x00002000) 1574 #define IWM_FH_TCSR_CHNL_TX_BUF_STS_REG_VAL_TFDB_VALID (0x00000003) 1575 1576 #define IWM_FH_TCSR_CHNL_TX_BUF_STS_REG_POS_TB_NUM (20) 1577 #define IWM_FH_TCSR_CHNL_TX_BUF_STS_REG_POS_TB_IDX (12) 1578 1579 /** 1580 * Tx Shared Status Registers (TSSR) 1581 * 1582 * After stopping Tx DMA channel (writing 0 to 1583 * IWM_FH_TCSR_CHNL_TX_CONFIG_REG(chnl)), driver must poll 1584 * IWM_FH_TSSR_TX_STATUS_REG until selected Tx channel is idle 1585 * (channel's buffers empty | no pending requests). 1586 * 1587 * Bit fields: 1588 * 31-24: 1 = Channel buffers empty (channel 7:0) 1589 * 23-16: 1 = No pending requests (channel 7:0) 1590 */ 1591 #define IWM_FH_TSSR_LOWER_BOUND (IWM_FH_MEM_LOWER_BOUND + 0xEA0) 1592 #define IWM_FH_TSSR_UPPER_BOUND (IWM_FH_MEM_LOWER_BOUND + 0xEC0) 1593 1594 #define IWM_FH_TSSR_TX_STATUS_REG (IWM_FH_TSSR_LOWER_BOUND + 0x010) 1595 1596 /** 1597 * Bit fields for TSSR(Tx Shared Status & Control) error status register: 1598 * 31: Indicates an address error when accessed to internal memory 1599 * uCode/driver must write "1" in order to clear this flag 1600 * 30: Indicates that Host did not send the expected number of dwords to FH 1601 * uCode/driver must write "1" in order to clear this flag 1602 * 16-9:Each status bit is for one channel. Indicates that an (Error) ActDMA 1603 * command was received from the scheduler while the TRB was already full 1604 * with previous command 1605 * uCode/driver must write "1" in order to clear this flag 1606 * 7-0: Each status bit indicates a channel's TxCredit error. When an error 1607 * bit is set, it indicates that the FH has received a full indication 1608 * from the RTC TxFIFO and the current value of the TxCredit counter was 1609 * not equal to zero. This mean that the credit mechanism was not 1610 * synchronized to the TxFIFO status 1611 * uCode/driver must write "1" in order to clear this flag 1612 */ 1613 #define IWM_FH_TSSR_TX_ERROR_REG (IWM_FH_TSSR_LOWER_BOUND + 0x018) 1614 #define IWM_FH_TSSR_TX_MSG_CONFIG_REG (IWM_FH_TSSR_LOWER_BOUND + 0x008) 1615 1616 #define IWM_FH_TSSR_TX_STATUS_REG_MSK_CHNL_IDLE(_chnl) ((1 << (_chnl)) << 16) 1617 1618 /* Tx service channels */ 1619 #define IWM_FH_SRVC_CHNL (9) 1620 #define IWM_FH_SRVC_LOWER_BOUND (IWM_FH_MEM_LOWER_BOUND + 0x9C8) 1621 #define IWM_FH_SRVC_UPPER_BOUND (IWM_FH_MEM_LOWER_BOUND + 0x9D0) 1622 #define IWM_FH_SRVC_CHNL_SRAM_ADDR_REG(_chnl) \ 1623 (IWM_FH_SRVC_LOWER_BOUND + ((_chnl) - 9) * 0x4) 1624 1625 #define IWM_FH_TX_CHICKEN_BITS_REG (IWM_FH_MEM_LOWER_BOUND + 0xE98) 1626 #define IWM_FH_TX_TRB_REG(_chan) (IWM_FH_MEM_LOWER_BOUND + 0x958 + \ 1627 (_chan) * 4) 1628 1629 /* Instruct FH to increment the retry count of a packet when 1630 * it is brought from the memory to TX-FIFO 1631 */ 1632 #define IWM_FH_TX_CHICKEN_BITS_SCD_AUTO_RETRY_EN (0x00000002) 1633 1634 #define IWM_RX_QUEUE_SIZE 256 1635 #define IWM_RX_QUEUE_MASK 255 1636 #define IWM_RX_QUEUE_SIZE_LOG 8 1637 1638 /* 1639 * RX related structures and functions 1640 */ 1641 #define IWM_RX_FREE_BUFFERS 64 1642 #define IWM_RX_LOW_WATERMARK 8 1643 1644 /** 1645 * struct iwm_rb_status - reseve buffer status 1646 * host memory mapped FH registers 1647 * @closed_rb_num [0:11] - Indicates the index of the RB which was closed 1648 * @closed_fr_num [0:11] - Indicates the index of the RX Frame which was closed 1649 * @finished_rb_num [0:11] - Indicates the index of the current RB 1650 * in which the last frame was written to 1651 * @finished_fr_num [0:11] - Indicates the index of the RX Frame 1652 * which was transferred 1653 */ 1654 struct iwm_rb_status { 1655 uint16_t closed_rb_num; 1656 uint16_t closed_fr_num; 1657 uint16_t finished_rb_num; 1658 uint16_t finished_fr_nam; 1659 uint32_t unused; 1660 } __packed; 1661 1662 1663 #define IWM_TFD_QUEUE_SIZE_MAX (256) 1664 #define IWM_TFD_QUEUE_SIZE_BC_DUP (64) 1665 #define IWM_TFD_QUEUE_BC_SIZE (IWM_TFD_QUEUE_SIZE_MAX + \ 1666 IWM_TFD_QUEUE_SIZE_BC_DUP) 1667 #define IWM_TX_DMA_MASK DMA_BIT_MASK(36) 1668 #define IWM_NUM_OF_TBS 20 1669 1670 static inline uint8_t iwm_get_dma_hi_addr(bus_addr_t addr) 1671 { 1672 return (sizeof(addr) > sizeof(uint32_t) ? (addr >> 16) >> 16 : 0) & 0xF; 1673 } 1674 /** 1675 * struct iwm_tfd_tb transmit buffer descriptor within transmit frame descriptor 1676 * 1677 * This structure contains dma address and length of transmission address 1678 * 1679 * @lo: low [31:0] portion of the dma address of TX buffer 1680 * every even is unaligned on 16 bit boundary 1681 * @hi_n_len 0-3 [35:32] portion of dma 1682 * 4-15 length of the tx buffer 1683 */ 1684 struct iwm_tfd_tb { 1685 uint32_t lo; 1686 uint16_t hi_n_len; 1687 } __packed; 1688 1689 /** 1690 * struct iwm_tfd 1691 * 1692 * Transmit Frame Descriptor (TFD) 1693 * 1694 * @ __reserved1[3] reserved 1695 * @ num_tbs 0-4 number of active tbs 1696 * 5 reserved 1697 * 6-7 padding (not used) 1698 * @ tbs[20] transmit frame buffer descriptors 1699 * @ __pad padding 1700 * 1701 * Each Tx queue uses a circular buffer of 256 TFDs stored in host DRAM. 1702 * Both driver and device share these circular buffers, each of which must be 1703 * contiguous 256 TFDs x 128 bytes-per-TFD = 32 KBytes 1704 * 1705 * Driver must indicate the physical address of the base of each 1706 * circular buffer via the IWM_FH_MEM_CBBC_QUEUE registers. 1707 * 1708 * Each TFD contains pointer/size information for up to 20 data buffers 1709 * in host DRAM. These buffers collectively contain the (one) frame described 1710 * by the TFD. Each buffer must be a single contiguous block of memory within 1711 * itself, but buffers may be scattered in host DRAM. Each buffer has max size 1712 * of (4K - 4). The concatenates all of a TFD's buffers into a single 1713 * Tx frame, up to 8 KBytes in size. 1714 * 1715 * A maximum of 255 (not 256!) TFDs may be on a queue waiting for Tx. 1716 */ 1717 struct iwm_tfd { 1718 uint8_t __reserved1[3]; 1719 uint8_t num_tbs; 1720 struct iwm_tfd_tb tbs[IWM_NUM_OF_TBS]; 1721 uint32_t __pad; 1722 } __packed; 1723 1724 /* Keep Warm Size */ 1725 #define IWM_KW_SIZE 0x1000 /* 4k */ 1726 1727 /* Fixed (non-configurable) rx data from phy */ 1728 1729 /** 1730 * struct iwm_agn_schedq_bc_tbl scheduler byte count table 1731 * base physical address provided by IWM_SCD_DRAM_BASE_ADDR 1732 * @tfd_offset 0-12 - tx command byte count 1733 * 12-16 - station index 1734 */ 1735 struct iwm_agn_scd_bc_tbl { 1736 uint16_t tfd_offset[IWM_TFD_QUEUE_BC_SIZE]; 1737 } __packed; 1738 1739 /* 1740 * END iwl-fh.h 1741 */ 1742 1743 /* 1744 * BEGIN mvm/fw-api.h 1745 */ 1746 1747 /* Maximum number of Tx queues. */ 1748 #define IWM_MVM_MAX_QUEUES 31 1749 1750 /* Tx queue numbers */ 1751 enum { 1752 IWM_MVM_OFFCHANNEL_QUEUE = 8, 1753 IWM_MVM_CMD_QUEUE = 9, 1754 IWM_MVM_AUX_QUEUE = 15, 1755 }; 1756 1757 enum iwm_mvm_tx_fifo { 1758 IWM_MVM_TX_FIFO_BK = 0, 1759 IWM_MVM_TX_FIFO_BE, 1760 IWM_MVM_TX_FIFO_VI, 1761 IWM_MVM_TX_FIFO_VO, 1762 IWM_MVM_TX_FIFO_MCAST = 5, 1763 IWM_MVM_TX_FIFO_CMD = 7, 1764 }; 1765 1766 #define IWM_MVM_STATION_COUNT 16 1767 1768 /* commands */ 1769 enum { 1770 IWM_MVM_ALIVE = 0x1, 1771 IWM_REPLY_ERROR = 0x2, 1772 1773 IWM_INIT_COMPLETE_NOTIF = 0x4, 1774 1775 /* PHY context commands */ 1776 IWM_PHY_CONTEXT_CMD = 0x8, 1777 IWM_DBG_CFG = 0x9, 1778 1779 /* UMAC scan commands */ 1780 IWM_SCAN_ITERATION_COMPLETE_UMAC = 0xb5, 1781 IWM_SCAN_CFG_CMD = 0xc, 1782 IWM_SCAN_REQ_UMAC = 0xd, 1783 IWM_SCAN_ABORT_UMAC = 0xe, 1784 IWM_SCAN_COMPLETE_UMAC = 0xf, 1785 1786 /* station table */ 1787 IWM_ADD_STA_KEY = 0x17, 1788 IWM_ADD_STA = 0x18, 1789 IWM_REMOVE_STA = 0x19, 1790 1791 /* TX */ 1792 IWM_TX_CMD = 0x1c, 1793 IWM_TXPATH_FLUSH = 0x1e, 1794 IWM_MGMT_MCAST_KEY = 0x1f, 1795 1796 /* scheduler config */ 1797 IWM_SCD_QUEUE_CFG = 0x1d, 1798 1799 /* global key */ 1800 IWM_WEP_KEY = 0x20, 1801 1802 /* MAC and Binding commands */ 1803 IWM_MAC_CONTEXT_CMD = 0x28, 1804 IWM_TIME_EVENT_CMD = 0x29, /* both CMD and response */ 1805 IWM_TIME_EVENT_NOTIFICATION = 0x2a, 1806 IWM_BINDING_CONTEXT_CMD = 0x2b, 1807 IWM_TIME_QUOTA_CMD = 0x2c, 1808 IWM_NON_QOS_TX_COUNTER_CMD = 0x2d, 1809 1810 IWM_LQ_CMD = 0x4e, 1811 1812 /* Calibration */ 1813 IWM_TEMPERATURE_NOTIFICATION = 0x62, 1814 IWM_CALIBRATION_CFG_CMD = 0x65, 1815 IWM_CALIBRATION_RES_NOTIFICATION = 0x66, 1816 IWM_CALIBRATION_COMPLETE_NOTIFICATION = 0x67, 1817 IWM_RADIO_VERSION_NOTIFICATION = 0x68, 1818 1819 /* Scan offload */ 1820 IWM_SCAN_OFFLOAD_REQUEST_CMD = 0x51, 1821 IWM_SCAN_OFFLOAD_ABORT_CMD = 0x52, 1822 IWM_HOT_SPOT_CMD = 0x53, 1823 IWM_SCAN_OFFLOAD_COMPLETE = 0x6d, 1824 IWM_SCAN_OFFLOAD_UPDATE_PROFILES_CMD = 0x6e, 1825 IWM_SCAN_OFFLOAD_CONFIG_CMD = 0x6f, 1826 IWM_MATCH_FOUND_NOTIFICATION = 0xd9, 1827 IWM_SCAN_ITERATION_COMPLETE = 0xe7, 1828 1829 /* Phy */ 1830 IWM_PHY_CONFIGURATION_CMD = 0x6a, 1831 IWM_CALIB_RES_NOTIF_PHY_DB = 0x6b, 1832 /* IWM_PHY_DB_CMD = 0x6c, */ 1833 1834 /* Power - legacy power table command */ 1835 IWM_POWER_TABLE_CMD = 0x77, 1836 IWM_PSM_UAPSD_AP_MISBEHAVING_NOTIFICATION = 0x78, 1837 1838 /* Thermal Throttling*/ 1839 IWM_REPLY_THERMAL_MNG_BACKOFF = 0x7e, 1840 1841 /* Scanning */ 1842 IWM_SCAN_REQUEST_CMD = 0x80, 1843 IWM_SCAN_ABORT_CMD = 0x81, 1844 IWM_SCAN_START_NOTIFICATION = 0x82, 1845 IWM_SCAN_RESULTS_NOTIFICATION = 0x83, 1846 IWM_SCAN_COMPLETE_NOTIFICATION = 0x84, 1847 1848 /* NVM */ 1849 IWM_NVM_ACCESS_CMD = 0x88, 1850 1851 IWM_SET_CALIB_DEFAULT_CMD = 0x8e, 1852 1853 IWM_BEACON_NOTIFICATION = 0x90, 1854 IWM_BEACON_TEMPLATE_CMD = 0x91, 1855 IWM_TX_ANT_CONFIGURATION_CMD = 0x98, 1856 IWM_BT_CONFIG = 0x9b, 1857 IWM_STATISTICS_NOTIFICATION = 0x9d, 1858 IWM_REDUCE_TX_POWER_CMD = 0x9f, 1859 1860 /* RF-KILL commands and notifications */ 1861 IWM_CARD_STATE_CMD = 0xa0, 1862 IWM_CARD_STATE_NOTIFICATION = 0xa1, 1863 1864 IWM_MISSED_BEACONS_NOTIFICATION = 0xa2, 1865 1866 IWM_MFUART_LOAD_NOTIFICATION = 0xb1, 1867 1868 /* Power - new power table command */ 1869 IWM_MAC_PM_POWER_TABLE = 0xa9, 1870 1871 IWM_REPLY_RX_PHY_CMD = 0xc0, 1872 IWM_REPLY_RX_MPDU_CMD = 0xc1, 1873 IWM_BA_NOTIF = 0xc5, 1874 1875 /* Location Aware Regulatory */ 1876 IWM_MCC_UPDATE_CMD = 0xc8, 1877 IWM_MCC_CHUB_UPDATE_CMD = 0xc9, 1878 1879 /* BT Coex */ 1880 IWM_BT_COEX_PRIO_TABLE = 0xcc, 1881 IWM_BT_COEX_PROT_ENV = 0xcd, 1882 IWM_BT_PROFILE_NOTIFICATION = 0xce, 1883 IWM_BT_COEX_CI = 0x5d, 1884 1885 IWM_REPLY_SF_CFG_CMD = 0xd1, 1886 IWM_REPLY_BEACON_FILTERING_CMD = 0xd2, 1887 1888 /* DTS measurements */ 1889 IWM_CMD_DTS_MEASUREMENT_TRIGGER = 0xdc, 1890 IWM_DTS_MEASUREMENT_NOTIFICATION = 0xdd, 1891 1892 IWM_REPLY_DEBUG_CMD = 0xf0, 1893 IWM_DEBUG_LOG_MSG = 0xf7, 1894 1895 IWM_MCAST_FILTER_CMD = 0xd0, 1896 1897 /* D3 commands/notifications */ 1898 IWM_D3_CONFIG_CMD = 0xd3, 1899 IWM_PROT_OFFLOAD_CONFIG_CMD = 0xd4, 1900 IWM_OFFLOADS_QUERY_CMD = 0xd5, 1901 IWM_REMOTE_WAKE_CONFIG_CMD = 0xd6, 1902 1903 /* for WoWLAN in particular */ 1904 IWM_WOWLAN_PATTERNS = 0xe0, 1905 IWM_WOWLAN_CONFIGURATION = 0xe1, 1906 IWM_WOWLAN_TSC_RSC_PARAM = 0xe2, 1907 IWM_WOWLAN_TKIP_PARAM = 0xe3, 1908 IWM_WOWLAN_KEK_KCK_MATERIAL = 0xe4, 1909 IWM_WOWLAN_GET_STATUSES = 0xe5, 1910 IWM_WOWLAN_TX_POWER_PER_DB = 0xe6, 1911 1912 /* and for NetDetect */ 1913 IWM_NET_DETECT_CONFIG_CMD = 0x54, 1914 IWM_NET_DETECT_PROFILES_QUERY_CMD = 0x56, 1915 IWM_NET_DETECT_PROFILES_CMD = 0x57, 1916 IWM_NET_DETECT_HOTSPOTS_CMD = 0x58, 1917 IWM_NET_DETECT_HOTSPOTS_QUERY_CMD = 0x59, 1918 1919 IWM_REPLY_MAX = 0xff, 1920 }; 1921 1922 /** 1923 * struct iwm_cmd_response - generic response struct for most commands 1924 * @status: status of the command asked, changes for each one 1925 */ 1926 struct iwm_cmd_response { 1927 uint32_t status; 1928 }; 1929 1930 /* 1931 * struct iwm_tx_ant_cfg_cmd 1932 * @valid: valid antenna configuration 1933 */ 1934 struct iwm_tx_ant_cfg_cmd { 1935 uint32_t valid; 1936 } __packed; 1937 1938 /** 1939 * struct iwm_reduce_tx_power_cmd - TX power reduction command 1940 * IWM_REDUCE_TX_POWER_CMD = 0x9f 1941 * @flags: (reserved for future implementation) 1942 * @mac_context_id: id of the mac ctx for which we are reducing TX power. 1943 * @pwr_restriction: TX power restriction in dBms. 1944 */ 1945 struct iwm_reduce_tx_power_cmd { 1946 uint8_t flags; 1947 uint8_t mac_context_id; 1948 uint16_t pwr_restriction; 1949 } __packed; /* IWM_TX_REDUCED_POWER_API_S_VER_1 */ 1950 1951 /* 1952 * Calibration control struct. 1953 * Sent as part of the phy configuration command. 1954 * @flow_trigger: bitmap for which calibrations to perform according to 1955 * flow triggers. 1956 * @event_trigger: bitmap for which calibrations to perform according to 1957 * event triggers. 1958 */ 1959 struct iwm_calib_ctrl { 1960 uint32_t flow_trigger; 1961 uint32_t event_trigger; 1962 } __packed; 1963 1964 /* This enum defines the bitmap of various calibrations to enable in both 1965 * init ucode and runtime ucode through IWM_CALIBRATION_CFG_CMD. 1966 */ 1967 enum iwm_calib_cfg { 1968 IWM_CALIB_CFG_XTAL_IDX = (1 << 0), 1969 IWM_CALIB_CFG_TEMPERATURE_IDX = (1 << 1), 1970 IWM_CALIB_CFG_VOLTAGE_READ_IDX = (1 << 2), 1971 IWM_CALIB_CFG_PAPD_IDX = (1 << 3), 1972 IWM_CALIB_CFG_TX_PWR_IDX = (1 << 4), 1973 IWM_CALIB_CFG_DC_IDX = (1 << 5), 1974 IWM_CALIB_CFG_BB_FILTER_IDX = (1 << 6), 1975 IWM_CALIB_CFG_LO_LEAKAGE_IDX = (1 << 7), 1976 IWM_CALIB_CFG_TX_IQ_IDX = (1 << 8), 1977 IWM_CALIB_CFG_TX_IQ_SKEW_IDX = (1 << 9), 1978 IWM_CALIB_CFG_RX_IQ_IDX = (1 << 10), 1979 IWM_CALIB_CFG_RX_IQ_SKEW_IDX = (1 << 11), 1980 IWM_CALIB_CFG_SENSITIVITY_IDX = (1 << 12), 1981 IWM_CALIB_CFG_CHAIN_NOISE_IDX = (1 << 13), 1982 IWM_CALIB_CFG_DISCONNECTED_ANT_IDX = (1 << 14), 1983 IWM_CALIB_CFG_ANT_COUPLING_IDX = (1 << 15), 1984 IWM_CALIB_CFG_DAC_IDX = (1 << 16), 1985 IWM_CALIB_CFG_ABS_IDX = (1 << 17), 1986 IWM_CALIB_CFG_AGC_IDX = (1 << 18), 1987 }; 1988 1989 /* 1990 * Phy configuration command. 1991 */ 1992 struct iwm_phy_cfg_cmd { 1993 uint32_t phy_cfg; 1994 struct iwm_calib_ctrl calib_control; 1995 } __packed; 1996 1997 #define IWM_PHY_CFG_RADIO_TYPE ((1 << 0) | (1 << 1)) 1998 #define IWM_PHY_CFG_RADIO_STEP ((1 << 2) | (1 << 3)) 1999 #define IWM_PHY_CFG_RADIO_DASH ((1 << 4) | (1 << 5)) 2000 #define IWM_PHY_CFG_PRODUCT_NUMBER ((1 << 6) | (1 << 7)) 2001 #define IWM_PHY_CFG_TX_CHAIN_A (1 << 8) 2002 #define IWM_PHY_CFG_TX_CHAIN_B (1 << 9) 2003 #define IWM_PHY_CFG_TX_CHAIN_C (1 << 10) 2004 #define IWM_PHY_CFG_RX_CHAIN_A (1 << 12) 2005 #define IWM_PHY_CFG_RX_CHAIN_B (1 << 13) 2006 #define IWM_PHY_CFG_RX_CHAIN_C (1 << 14) 2007 2008 /* 2009 * PHY db 2010 */ 2011 2012 enum iwm_phy_db_section_type { 2013 IWM_PHY_DB_CFG = 1, 2014 IWM_PHY_DB_CALIB_NCH, 2015 IWM_PHY_DB_UNUSED, 2016 IWM_PHY_DB_CALIB_CHG_PAPD, 2017 IWM_PHY_DB_CALIB_CHG_TXP, 2018 IWM_PHY_DB_MAX 2019 }; 2020 2021 #define IWM_PHY_DB_CMD 0x6c /* TEMP API - The actual is 0x8c */ 2022 2023 /* 2024 * phy db - configure operational ucode 2025 */ 2026 struct iwm_phy_db_cmd { 2027 uint16_t type; 2028 uint16_t length; 2029 uint8_t data[]; 2030 } __packed; 2031 2032 /* for parsing of tx power channel group data that comes from the firmware */ 2033 struct iwm_phy_db_chg_txp { 2034 uint32_t space; 2035 uint16_t max_channel_idx; 2036 } __packed; 2037 2038 /* 2039 * phy db - Receive phy db chunk after calibrations 2040 */ 2041 struct iwm_calib_res_notif_phy_db { 2042 uint16_t type; 2043 uint16_t length; 2044 uint8_t data[]; 2045 } __packed; 2046 2047 2048 /* Target of the IWM_NVM_ACCESS_CMD */ 2049 enum { 2050 IWM_NVM_ACCESS_TARGET_CACHE = 0, 2051 IWM_NVM_ACCESS_TARGET_OTP = 1, 2052 IWM_NVM_ACCESS_TARGET_EEPROM = 2, 2053 }; 2054 2055 /* Section types for IWM_NVM_ACCESS_CMD */ 2056 enum { 2057 IWM_NVM_SECTION_TYPE_HW = 0, 2058 IWM_NVM_SECTION_TYPE_SW, 2059 IWM_NVM_SECTION_TYPE_PAPD, 2060 IWM_NVM_SECTION_TYPE_REGULATORY, 2061 IWM_NVM_SECTION_TYPE_CALIBRATION, 2062 IWM_NVM_SECTION_TYPE_PRODUCTION, 2063 IWM_NVM_SECTION_TYPE_POST_FCS_CALIB, 2064 /* 7, 8, 9 unknown */ 2065 IWM_NVM_SECTION_TYPE_HW_8000 = 10, 2066 IWM_NVM_SECTION_TYPE_MAC_OVERRIDE, 2067 IWM_NVM_SECTION_TYPE_PHY_SKU, 2068 IWM_NVM_NUM_OF_SECTIONS, 2069 }; 2070 2071 /** 2072 * struct iwm_nvm_access_cmd_ver2 - Request the device to send an NVM section 2073 * @op_code: 0 - read, 1 - write 2074 * @target: IWM_NVM_ACCESS_TARGET_* 2075 * @type: IWM_NVM_SECTION_TYPE_* 2076 * @offset: offset in bytes into the section 2077 * @length: in bytes, to read/write 2078 * @data: if write operation, the data to write. On read its empty 2079 */ 2080 struct iwm_nvm_access_cmd { 2081 uint8_t op_code; 2082 uint8_t target; 2083 uint16_t type; 2084 uint16_t offset; 2085 uint16_t length; 2086 uint8_t data[]; 2087 } __packed; /* IWM_NVM_ACCESS_CMD_API_S_VER_2 */ 2088 2089 /** 2090 * struct iwm_nvm_access_resp_ver2 - response to IWM_NVM_ACCESS_CMD 2091 * @offset: offset in bytes into the section 2092 * @length: in bytes, either how much was written or read 2093 * @type: IWM_NVM_SECTION_TYPE_* 2094 * @status: 0 for success, fail otherwise 2095 * @data: if read operation, the data returned. Empty on write. 2096 */ 2097 struct iwm_nvm_access_resp { 2098 uint16_t offset; 2099 uint16_t length; 2100 uint16_t type; 2101 uint16_t status; 2102 uint8_t data[]; 2103 } __packed; /* IWM_NVM_ACCESS_CMD_RESP_API_S_VER_2 */ 2104 2105 /* IWM_MVM_ALIVE 0x1 */ 2106 2107 /* alive response is_valid values */ 2108 #define IWM_ALIVE_RESP_UCODE_OK (1 << 0) 2109 #define IWM_ALIVE_RESP_RFKILL (1 << 1) 2110 2111 /* alive response ver_type values */ 2112 enum { 2113 IWM_FW_TYPE_HW = 0, 2114 IWM_FW_TYPE_PROT = 1, 2115 IWM_FW_TYPE_AP = 2, 2116 IWM_FW_TYPE_WOWLAN = 3, 2117 IWM_FW_TYPE_TIMING = 4, 2118 IWM_FW_TYPE_WIPAN = 5 2119 }; 2120 2121 /* alive response ver_subtype values */ 2122 enum { 2123 IWM_FW_SUBTYPE_FULL_FEATURE = 0, 2124 IWM_FW_SUBTYPE_BOOTSRAP = 1, /* Not valid */ 2125 IWM_FW_SUBTYPE_REDUCED = 2, 2126 IWM_FW_SUBTYPE_ALIVE_ONLY = 3, 2127 IWM_FW_SUBTYPE_WOWLAN = 4, 2128 IWM_FW_SUBTYPE_AP_SUBTYPE = 5, 2129 IWM_FW_SUBTYPE_WIPAN = 6, 2130 IWM_FW_SUBTYPE_INITIALIZE = 9 2131 }; 2132 2133 #define IWM_ALIVE_STATUS_ERR 0xDEAD 2134 #define IWM_ALIVE_STATUS_OK 0xCAFE 2135 2136 #define IWM_ALIVE_FLG_RFKILL (1 << 0) 2137 2138 struct iwm_mvm_alive_resp_v1 { 2139 uint16_t status; 2140 uint16_t flags; 2141 uint8_t ucode_minor; 2142 uint8_t ucode_major; 2143 uint16_t id; 2144 uint8_t api_minor; 2145 uint8_t api_major; 2146 uint8_t ver_subtype; 2147 uint8_t ver_type; 2148 uint8_t mac; 2149 uint8_t opt; 2150 uint16_t reserved2; 2151 uint32_t timestamp; 2152 uint32_t error_event_table_ptr; /* SRAM address for error log */ 2153 uint32_t log_event_table_ptr; /* SRAM address for event log */ 2154 uint32_t cpu_register_ptr; 2155 uint32_t dbgm_config_ptr; 2156 uint32_t alive_counter_ptr; 2157 uint32_t scd_base_ptr; /* SRAM address for SCD */ 2158 } __packed; /* IWM_ALIVE_RES_API_S_VER_1 */ 2159 2160 struct iwm_mvm_alive_resp_v2 { 2161 uint16_t status; 2162 uint16_t flags; 2163 uint8_t ucode_minor; 2164 uint8_t ucode_major; 2165 uint16_t id; 2166 uint8_t api_minor; 2167 uint8_t api_major; 2168 uint8_t ver_subtype; 2169 uint8_t ver_type; 2170 uint8_t mac; 2171 uint8_t opt; 2172 uint16_t reserved2; 2173 uint32_t timestamp; 2174 uint32_t error_event_table_ptr; /* SRAM address for error log */ 2175 uint32_t log_event_table_ptr; /* SRAM address for LMAC event log */ 2176 uint32_t cpu_register_ptr; 2177 uint32_t dbgm_config_ptr; 2178 uint32_t alive_counter_ptr; 2179 uint32_t scd_base_ptr; /* SRAM address for SCD */ 2180 uint32_t st_fwrd_addr; /* pointer to Store and forward */ 2181 uint32_t st_fwrd_size; 2182 uint8_t umac_minor; /* UMAC version: minor */ 2183 uint8_t umac_major; /* UMAC version: major */ 2184 uint16_t umac_id; /* UMAC version: id */ 2185 uint32_t error_info_addr; /* SRAM address for UMAC error log */ 2186 uint32_t dbg_print_buff_addr; 2187 } __packed; /* ALIVE_RES_API_S_VER_2 */ 2188 2189 struct iwm_mvm_alive_resp_v3 { 2190 uint16_t status; 2191 uint16_t flags; 2192 uint32_t ucode_minor; 2193 uint32_t ucode_major; 2194 uint8_t ver_subtype; 2195 uint8_t ver_type; 2196 uint8_t mac; 2197 uint8_t opt; 2198 uint32_t timestamp; 2199 uint32_t error_event_table_ptr; /* SRAM address for error log */ 2200 uint32_t log_event_table_ptr; /* SRAM address for LMAC event log */ 2201 uint32_t cpu_register_ptr; 2202 uint32_t dbgm_config_ptr; 2203 uint32_t alive_counter_ptr; 2204 uint32_t scd_base_ptr; /* SRAM address for SCD */ 2205 uint32_t st_fwrd_addr; /* pointer to Store and forward */ 2206 uint32_t st_fwrd_size; 2207 uint32_t umac_minor; /* UMAC version: minor */ 2208 uint32_t umac_major; /* UMAC version: major */ 2209 uint32_t error_info_addr; /* SRAM address for UMAC error log */ 2210 uint32_t dbg_print_buff_addr; 2211 } __packed; /* ALIVE_RES_API_S_VER_3 */ 2212 2213 /* Error response/notification */ 2214 enum { 2215 IWM_FW_ERR_UNKNOWN_CMD = 0x0, 2216 IWM_FW_ERR_INVALID_CMD_PARAM = 0x1, 2217 IWM_FW_ERR_SERVICE = 0x2, 2218 IWM_FW_ERR_ARC_MEMORY = 0x3, 2219 IWM_FW_ERR_ARC_CODE = 0x4, 2220 IWM_FW_ERR_WATCH_DOG = 0x5, 2221 IWM_FW_ERR_WEP_GRP_KEY_INDX = 0x10, 2222 IWM_FW_ERR_WEP_KEY_SIZE = 0x11, 2223 IWM_FW_ERR_OBSOLETE_FUNC = 0x12, 2224 IWM_FW_ERR_UNEXPECTED = 0xFE, 2225 IWM_FW_ERR_FATAL = 0xFF 2226 }; 2227 2228 /** 2229 * struct iwm_error_resp - FW error indication 2230 * ( IWM_REPLY_ERROR = 0x2 ) 2231 * @error_type: one of IWM_FW_ERR_* 2232 * @cmd_id: the command ID for which the error occurred 2233 * @bad_cmd_seq_num: sequence number of the erroneous command 2234 * @error_service: which service created the error, applicable only if 2235 * error_type = 2, otherwise 0 2236 * @timestamp: TSF in usecs. 2237 */ 2238 struct iwm_error_resp { 2239 uint32_t error_type; 2240 uint8_t cmd_id; 2241 uint8_t reserved1; 2242 uint16_t bad_cmd_seq_num; 2243 uint32_t error_service; 2244 uint64_t timestamp; 2245 } __packed; 2246 2247 2248 /* Common PHY, MAC and Bindings definitions */ 2249 2250 #define IWM_MAX_MACS_IN_BINDING (3) 2251 #define IWM_MAX_BINDINGS (4) 2252 #define IWM_AUX_BINDING_INDEX (3) 2253 #define IWM_MAX_PHYS (4) 2254 2255 /* Used to extract ID and color from the context dword */ 2256 #define IWM_FW_CTXT_ID_POS (0) 2257 #define IWM_FW_CTXT_ID_MSK (0xff << IWM_FW_CTXT_ID_POS) 2258 #define IWM_FW_CTXT_COLOR_POS (8) 2259 #define IWM_FW_CTXT_COLOR_MSK (0xff << IWM_FW_CTXT_COLOR_POS) 2260 #define IWM_FW_CTXT_INVALID (0xffffffff) 2261 2262 #define IWM_FW_CMD_ID_AND_COLOR(_id, _color) ((_id << IWM_FW_CTXT_ID_POS) |\ 2263 (_color << IWM_FW_CTXT_COLOR_POS)) 2264 2265 /* Possible actions on PHYs, MACs and Bindings */ 2266 enum { 2267 IWM_FW_CTXT_ACTION_STUB = 0, 2268 IWM_FW_CTXT_ACTION_ADD, 2269 IWM_FW_CTXT_ACTION_MODIFY, 2270 IWM_FW_CTXT_ACTION_REMOVE, 2271 IWM_FW_CTXT_ACTION_NUM 2272 }; /* COMMON_CONTEXT_ACTION_API_E_VER_1 */ 2273 2274 /* Time Events */ 2275 2276 /* Time Event types, according to MAC type */ 2277 enum iwm_time_event_type { 2278 /* BSS Station Events */ 2279 IWM_TE_BSS_STA_AGGRESSIVE_ASSOC, 2280 IWM_TE_BSS_STA_ASSOC, 2281 IWM_TE_BSS_EAP_DHCP_PROT, 2282 IWM_TE_BSS_QUIET_PERIOD, 2283 2284 /* P2P Device Events */ 2285 IWM_TE_P2P_DEVICE_DISCOVERABLE, 2286 IWM_TE_P2P_DEVICE_LISTEN, 2287 IWM_TE_P2P_DEVICE_ACTION_SCAN, 2288 IWM_TE_P2P_DEVICE_FULL_SCAN, 2289 2290 /* P2P Client Events */ 2291 IWM_TE_P2P_CLIENT_AGGRESSIVE_ASSOC, 2292 IWM_TE_P2P_CLIENT_ASSOC, 2293 IWM_TE_P2P_CLIENT_QUIET_PERIOD, 2294 2295 /* P2P GO Events */ 2296 IWM_TE_P2P_GO_ASSOC_PROT, 2297 IWM_TE_P2P_GO_REPETITIVE_NOA, 2298 IWM_TE_P2P_GO_CT_WINDOW, 2299 2300 /* WiDi Sync Events */ 2301 IWM_TE_WIDI_TX_SYNC, 2302 2303 IWM_TE_MAX 2304 }; /* IWM_MAC_EVENT_TYPE_API_E_VER_1 */ 2305 2306 2307 2308 /* Time event - defines for command API v1 */ 2309 2310 /* 2311 * @IWM_TE_V1_FRAG_NONE: fragmentation of the time event is NOT allowed. 2312 * @IWM_TE_V1_FRAG_SINGLE: fragmentation of the time event is allowed, but only 2313 * the first fragment is scheduled. 2314 * @IWM_TE_V1_FRAG_DUAL: fragmentation of the time event is allowed, but only 2315 * the first 2 fragments are scheduled. 2316 * @IWM_TE_V1_FRAG_ENDLESS: fragmentation of the time event is allowed, and any 2317 * number of fragments are valid. 2318 * 2319 * Other than the constant defined above, specifying a fragmentation value 'x' 2320 * means that the event can be fragmented but only the first 'x' will be 2321 * scheduled. 2322 */ 2323 enum { 2324 IWM_TE_V1_FRAG_NONE = 0, 2325 IWM_TE_V1_FRAG_SINGLE = 1, 2326 IWM_TE_V1_FRAG_DUAL = 2, 2327 IWM_TE_V1_FRAG_ENDLESS = 0xffffffff 2328 }; 2329 2330 /* If a Time Event can be fragmented, this is the max number of fragments */ 2331 #define IWM_TE_V1_FRAG_MAX_MSK 0x0fffffff 2332 /* Repeat the time event endlessly (until removed) */ 2333 #define IWM_TE_V1_REPEAT_ENDLESS 0xffffffff 2334 /* If a Time Event has bounded repetitions, this is the maximal value */ 2335 #define IWM_TE_V1_REPEAT_MAX_MSK_V1 0x0fffffff 2336 2337 /* Time Event dependencies: none, on another TE, or in a specific time */ 2338 enum { 2339 IWM_TE_V1_INDEPENDENT = 0, 2340 IWM_TE_V1_DEP_OTHER = (1 << 0), 2341 IWM_TE_V1_DEP_TSF = (1 << 1), 2342 IWM_TE_V1_EVENT_SOCIOPATHIC = (1 << 2), 2343 }; /* IWM_MAC_EVENT_DEPENDENCY_POLICY_API_E_VER_2 */ 2344 2345 /* 2346 * @IWM_TE_V1_NOTIF_NONE: no notifications 2347 * @IWM_TE_V1_NOTIF_HOST_EVENT_START: request/receive notification on event start 2348 * @IWM_TE_V1_NOTIF_HOST_EVENT_END:request/receive notification on event end 2349 * @IWM_TE_V1_NOTIF_INTERNAL_EVENT_START: internal FW use 2350 * @IWM_TE_V1_NOTIF_INTERNAL_EVENT_END: internal FW use. 2351 * @IWM_TE_V1_NOTIF_HOST_FRAG_START: request/receive notification on frag start 2352 * @IWM_TE_V1_NOTIF_HOST_FRAG_END:request/receive notification on frag end 2353 * @IWM_TE_V1_NOTIF_INTERNAL_FRAG_START: internal FW use. 2354 * @IWM_TE_V1_NOTIF_INTERNAL_FRAG_END: internal FW use. 2355 * 2356 * Supported Time event notifications configuration. 2357 * A notification (both event and fragment) includes a status indicating weather 2358 * the FW was able to schedule the event or not. For fragment start/end 2359 * notification the status is always success. There is no start/end fragment 2360 * notification for monolithic events. 2361 */ 2362 enum { 2363 IWM_TE_V1_NOTIF_NONE = 0, 2364 IWM_TE_V1_NOTIF_HOST_EVENT_START = (1 << 0), 2365 IWM_TE_V1_NOTIF_HOST_EVENT_END = (1 << 1), 2366 IWM_TE_V1_NOTIF_INTERNAL_EVENT_START = (1 << 2), 2367 IWM_TE_V1_NOTIF_INTERNAL_EVENT_END = (1 << 3), 2368 IWM_TE_V1_NOTIF_HOST_FRAG_START = (1 << 4), 2369 IWM_TE_V1_NOTIF_HOST_FRAG_END = (1 << 5), 2370 IWM_TE_V1_NOTIF_INTERNAL_FRAG_START = (1 << 6), 2371 IWM_TE_V1_NOTIF_INTERNAL_FRAG_END = (1 << 7), 2372 IWM_T2_V2_START_IMMEDIATELY = (1 << 11), 2373 }; /* IWM_MAC_EVENT_ACTION_API_E_VER_2 */ 2374 2375 2376 /** 2377 * struct iwm_time_event_cmd_api_v1 - configuring Time Events 2378 * with struct IWM_MAC_TIME_EVENT_DATA_API_S_VER_1 (see also 2379 * with version 2. determined by IWM_UCODE_TLV_FLAGS) 2380 * ( IWM_TIME_EVENT_CMD = 0x29 ) 2381 * @id_and_color: ID and color of the relevant MAC 2382 * @action: action to perform, one of IWM_FW_CTXT_ACTION_* 2383 * @id: this field has two meanings, depending on the action: 2384 * If the action is ADD, then it means the type of event to add. 2385 * For all other actions it is the unique event ID assigned when the 2386 * event was added by the FW. 2387 * @apply_time: When to start the Time Event (in GP2) 2388 * @max_delay: maximum delay to event's start (apply time), in TU 2389 * @depends_on: the unique ID of the event we depend on (if any) 2390 * @interval: interval between repetitions, in TU 2391 * @interval_reciprocal: 2^32 / interval 2392 * @duration: duration of event in TU 2393 * @repeat: how many repetitions to do, can be IWM_TE_REPEAT_ENDLESS 2394 * @dep_policy: one of IWM_TE_V1_INDEPENDENT, IWM_TE_V1_DEP_OTHER, IWM_TE_V1_DEP_TSF 2395 * and IWM_TE_V1_EVENT_SOCIOPATHIC 2396 * @is_present: 0 or 1, are we present or absent during the Time Event 2397 * @max_frags: maximal number of fragments the Time Event can be divided to 2398 * @notify: notifications using IWM_TE_V1_NOTIF_* (whom to notify when) 2399 */ 2400 struct iwm_time_event_cmd_v1 { 2401 /* COMMON_INDEX_HDR_API_S_VER_1 */ 2402 uint32_t id_and_color; 2403 uint32_t action; 2404 uint32_t id; 2405 /* IWM_MAC_TIME_EVENT_DATA_API_S_VER_1 */ 2406 uint32_t apply_time; 2407 uint32_t max_delay; 2408 uint32_t dep_policy; 2409 uint32_t depends_on; 2410 uint32_t is_present; 2411 uint32_t max_frags; 2412 uint32_t interval; 2413 uint32_t interval_reciprocal; 2414 uint32_t duration; 2415 uint32_t repeat; 2416 uint32_t notify; 2417 } __packed; /* IWM_MAC_TIME_EVENT_CMD_API_S_VER_1 */ 2418 2419 2420 /* Time event - defines for command API v2 */ 2421 2422 /* 2423 * @IWM_TE_V2_FRAG_NONE: fragmentation of the time event is NOT allowed. 2424 * @IWM_TE_V2_FRAG_SINGLE: fragmentation of the time event is allowed, but only 2425 * the first fragment is scheduled. 2426 * @IWM_TE_V2_FRAG_DUAL: fragmentation of the time event is allowed, but only 2427 * the first 2 fragments are scheduled. 2428 * @IWM_TE_V2_FRAG_ENDLESS: fragmentation of the time event is allowed, and any 2429 * number of fragments are valid. 2430 * 2431 * Other than the constant defined above, specifying a fragmentation value 'x' 2432 * means that the event can be fragmented but only the first 'x' will be 2433 * scheduled. 2434 */ 2435 enum { 2436 IWM_TE_V2_FRAG_NONE = 0, 2437 IWM_TE_V2_FRAG_SINGLE = 1, 2438 IWM_TE_V2_FRAG_DUAL = 2, 2439 IWM_TE_V2_FRAG_MAX = 0xfe, 2440 IWM_TE_V2_FRAG_ENDLESS = 0xff 2441 }; 2442 2443 /* Repeat the time event endlessly (until removed) */ 2444 #define IWM_TE_V2_REPEAT_ENDLESS 0xff 2445 /* If a Time Event has bounded repetitions, this is the maximal value */ 2446 #define IWM_TE_V2_REPEAT_MAX 0xfe 2447 2448 #define IWM_TE_V2_PLACEMENT_POS 12 2449 #define IWM_TE_V2_ABSENCE_POS 15 2450 2451 /* Time event policy values (for time event cmd api v2) 2452 * A notification (both event and fragment) includes a status indicating weather 2453 * the FW was able to schedule the event or not. For fragment start/end 2454 * notification the status is always success. There is no start/end fragment 2455 * notification for monolithic events. 2456 * 2457 * @IWM_TE_V2_DEFAULT_POLICY: independent, social, present, unoticable 2458 * @IWM_TE_V2_NOTIF_HOST_EVENT_START: request/receive notification on event start 2459 * @IWM_TE_V2_NOTIF_HOST_EVENT_END:request/receive notification on event end 2460 * @IWM_TE_V2_NOTIF_INTERNAL_EVENT_START: internal FW use 2461 * @IWM_TE_V2_NOTIF_INTERNAL_EVENT_END: internal FW use. 2462 * @IWM_TE_V2_NOTIF_HOST_FRAG_START: request/receive notification on frag start 2463 * @IWM_TE_V2_NOTIF_HOST_FRAG_END:request/receive notification on frag end 2464 * @IWM_TE_V2_NOTIF_INTERNAL_FRAG_START: internal FW use. 2465 * @IWM_TE_V2_NOTIF_INTERNAL_FRAG_END: internal FW use. 2466 * @IWM_TE_V2_DEP_OTHER: depends on another time event 2467 * @IWM_TE_V2_DEP_TSF: depends on a specific time 2468 * @IWM_TE_V2_EVENT_SOCIOPATHIC: can't co-exist with other events of tha same MAC 2469 * @IWM_TE_V2_ABSENCE: are we present or absent during the Time Event. 2470 */ 2471 enum { 2472 IWM_TE_V2_DEFAULT_POLICY = 0x0, 2473 2474 /* notifications (event start/stop, fragment start/stop) */ 2475 IWM_TE_V2_NOTIF_HOST_EVENT_START = (1 << 0), 2476 IWM_TE_V2_NOTIF_HOST_EVENT_END = (1 << 1), 2477 IWM_TE_V2_NOTIF_INTERNAL_EVENT_START = (1 << 2), 2478 IWM_TE_V2_NOTIF_INTERNAL_EVENT_END = (1 << 3), 2479 2480 IWM_TE_V2_NOTIF_HOST_FRAG_START = (1 << 4), 2481 IWM_TE_V2_NOTIF_HOST_FRAG_END = (1 << 5), 2482 IWM_TE_V2_NOTIF_INTERNAL_FRAG_START = (1 << 6), 2483 IWM_TE_V2_NOTIF_INTERNAL_FRAG_END = (1 << 7), 2484 2485 IWM_TE_V2_NOTIF_MSK = 0xff, 2486 2487 /* placement characteristics */ 2488 IWM_TE_V2_DEP_OTHER = (1 << IWM_TE_V2_PLACEMENT_POS), 2489 IWM_TE_V2_DEP_TSF = (1 << (IWM_TE_V2_PLACEMENT_POS + 1)), 2490 IWM_TE_V2_EVENT_SOCIOPATHIC = (1 << (IWM_TE_V2_PLACEMENT_POS + 2)), 2491 2492 /* are we present or absent during the Time Event. */ 2493 IWM_TE_V2_ABSENCE = (1 << IWM_TE_V2_ABSENCE_POS), 2494 }; 2495 2496 /** 2497 * struct iwm_time_event_cmd_api_v2 - configuring Time Events 2498 * with struct IWM_MAC_TIME_EVENT_DATA_API_S_VER_2 (see also 2499 * with version 1. determined by IWM_UCODE_TLV_FLAGS) 2500 * ( IWM_TIME_EVENT_CMD = 0x29 ) 2501 * @id_and_color: ID and color of the relevant MAC 2502 * @action: action to perform, one of IWM_FW_CTXT_ACTION_* 2503 * @id: this field has two meanings, depending on the action: 2504 * If the action is ADD, then it means the type of event to add. 2505 * For all other actions it is the unique event ID assigned when the 2506 * event was added by the FW. 2507 * @apply_time: When to start the Time Event (in GP2) 2508 * @max_delay: maximum delay to event's start (apply time), in TU 2509 * @depends_on: the unique ID of the event we depend on (if any) 2510 * @interval: interval between repetitions, in TU 2511 * @duration: duration of event in TU 2512 * @repeat: how many repetitions to do, can be IWM_TE_REPEAT_ENDLESS 2513 * @max_frags: maximal number of fragments the Time Event can be divided to 2514 * @policy: defines whether uCode shall notify the host or other uCode modules 2515 * on event and/or fragment start and/or end 2516 * using one of IWM_TE_INDEPENDENT, IWM_TE_DEP_OTHER, IWM_TE_DEP_TSF 2517 * IWM_TE_EVENT_SOCIOPATHIC 2518 * using IWM_TE_ABSENCE and using IWM_TE_NOTIF_* 2519 */ 2520 struct iwm_time_event_cmd_v2 { 2521 /* COMMON_INDEX_HDR_API_S_VER_1 */ 2522 uint32_t id_and_color; 2523 uint32_t action; 2524 uint32_t id; 2525 /* IWM_MAC_TIME_EVENT_DATA_API_S_VER_2 */ 2526 uint32_t apply_time; 2527 uint32_t max_delay; 2528 uint32_t depends_on; 2529 uint32_t interval; 2530 uint32_t duration; 2531 uint8_t repeat; 2532 uint8_t max_frags; 2533 uint16_t policy; 2534 } __packed; /* IWM_MAC_TIME_EVENT_CMD_API_S_VER_2 */ 2535 2536 /** 2537 * struct iwm_time_event_resp - response structure to iwm_time_event_cmd 2538 * @status: bit 0 indicates success, all others specify errors 2539 * @id: the Time Event type 2540 * @unique_id: the unique ID assigned (in ADD) or given (others) to the TE 2541 * @id_and_color: ID and color of the relevant MAC 2542 */ 2543 struct iwm_time_event_resp { 2544 uint32_t status; 2545 uint32_t id; 2546 uint32_t unique_id; 2547 uint32_t id_and_color; 2548 } __packed; /* IWM_MAC_TIME_EVENT_RSP_API_S_VER_1 */ 2549 2550 /** 2551 * struct iwm_time_event_notif - notifications of time event start/stop 2552 * ( IWM_TIME_EVENT_NOTIFICATION = 0x2a ) 2553 * @timestamp: action timestamp in GP2 2554 * @session_id: session's unique id 2555 * @unique_id: unique id of the Time Event itself 2556 * @id_and_color: ID and color of the relevant MAC 2557 * @action: one of IWM_TE_NOTIF_START or IWM_TE_NOTIF_END 2558 * @status: true if scheduled, false otherwise (not executed) 2559 */ 2560 struct iwm_time_event_notif { 2561 uint32_t timestamp; 2562 uint32_t session_id; 2563 uint32_t unique_id; 2564 uint32_t id_and_color; 2565 uint32_t action; 2566 uint32_t status; 2567 } __packed; /* IWM_MAC_TIME_EVENT_NTFY_API_S_VER_1 */ 2568 2569 2570 /* Bindings and Time Quota */ 2571 2572 /** 2573 * struct iwm_binding_cmd - configuring bindings 2574 * ( IWM_BINDING_CONTEXT_CMD = 0x2b ) 2575 * @id_and_color: ID and color of the relevant Binding 2576 * @action: action to perform, one of IWM_FW_CTXT_ACTION_* 2577 * @macs: array of MAC id and colors which belong to the binding 2578 * @phy: PHY id and color which belongs to the binding 2579 */ 2580 struct iwm_binding_cmd { 2581 /* COMMON_INDEX_HDR_API_S_VER_1 */ 2582 uint32_t id_and_color; 2583 uint32_t action; 2584 /* IWM_BINDING_DATA_API_S_VER_1 */ 2585 uint32_t macs[IWM_MAX_MACS_IN_BINDING]; 2586 uint32_t phy; 2587 } __packed; /* IWM_BINDING_CMD_API_S_VER_1 */ 2588 2589 /* The maximal number of fragments in the FW's schedule session */ 2590 #define IWM_MVM_MAX_QUOTA 128 2591 2592 /** 2593 * struct iwm_time_quota_data - configuration of time quota per binding 2594 * @id_and_color: ID and color of the relevant Binding 2595 * @quota: absolute time quota in TU. The scheduler will try to divide the 2596 * remainig quota (after Time Events) according to this quota. 2597 * @max_duration: max uninterrupted context duration in TU 2598 */ 2599 struct iwm_time_quota_data { 2600 uint32_t id_and_color; 2601 uint32_t quota; 2602 uint32_t max_duration; 2603 } __packed; /* IWM_TIME_QUOTA_DATA_API_S_VER_1 */ 2604 2605 /** 2606 * struct iwm_time_quota_cmd - configuration of time quota between bindings 2607 * ( IWM_TIME_QUOTA_CMD = 0x2c ) 2608 * @quotas: allocations per binding 2609 */ 2610 struct iwm_time_quota_cmd { 2611 struct iwm_time_quota_data quotas[IWM_MAX_BINDINGS]; 2612 } __packed; /* IWM_TIME_QUOTA_ALLOCATION_CMD_API_S_VER_1 */ 2613 2614 2615 /* PHY context */ 2616 2617 /* Supported bands */ 2618 #define IWM_PHY_BAND_5 (0) 2619 #define IWM_PHY_BAND_24 (1) 2620 2621 /* Supported channel width, vary if there is VHT support */ 2622 #define IWM_PHY_VHT_CHANNEL_MODE20 (0x0) 2623 #define IWM_PHY_VHT_CHANNEL_MODE40 (0x1) 2624 #define IWM_PHY_VHT_CHANNEL_MODE80 (0x2) 2625 #define IWM_PHY_VHT_CHANNEL_MODE160 (0x3) 2626 2627 /* 2628 * Control channel position: 2629 * For legacy set bit means upper channel, otherwise lower. 2630 * For VHT - bit-2 marks if the control is lower/upper relative to center-freq 2631 * bits-1:0 mark the distance from the center freq. for 20Mhz, offset is 0. 2632 * center_freq 2633 * | 2634 * 40Mhz |_______|_______| 2635 * 80Mhz |_______|_______|_______|_______| 2636 * 160Mhz |_______|_______|_______|_______|_______|_______|_______|_______| 2637 * code 011 010 001 000 | 100 101 110 111 2638 */ 2639 #define IWM_PHY_VHT_CTRL_POS_1_BELOW (0x0) 2640 #define IWM_PHY_VHT_CTRL_POS_2_BELOW (0x1) 2641 #define IWM_PHY_VHT_CTRL_POS_3_BELOW (0x2) 2642 #define IWM_PHY_VHT_CTRL_POS_4_BELOW (0x3) 2643 #define IWM_PHY_VHT_CTRL_POS_1_ABOVE (0x4) 2644 #define IWM_PHY_VHT_CTRL_POS_2_ABOVE (0x5) 2645 #define IWM_PHY_VHT_CTRL_POS_3_ABOVE (0x6) 2646 #define IWM_PHY_VHT_CTRL_POS_4_ABOVE (0x7) 2647 2648 /* 2649 * @band: IWM_PHY_BAND_* 2650 * @channel: channel number 2651 * @width: PHY_[VHT|LEGACY]_CHANNEL_* 2652 * @ctrl channel: PHY_[VHT|LEGACY]_CTRL_* 2653 */ 2654 struct iwm_fw_channel_info { 2655 uint8_t band; 2656 uint8_t channel; 2657 uint8_t width; 2658 uint8_t ctrl_pos; 2659 } __packed; 2660 2661 #define IWM_PHY_RX_CHAIN_DRIVER_FORCE_POS (0) 2662 #define IWM_PHY_RX_CHAIN_DRIVER_FORCE_MSK \ 2663 (0x1 << IWM_PHY_RX_CHAIN_DRIVER_FORCE_POS) 2664 #define IWM_PHY_RX_CHAIN_VALID_POS (1) 2665 #define IWM_PHY_RX_CHAIN_VALID_MSK \ 2666 (0x7 << IWM_PHY_RX_CHAIN_VALID_POS) 2667 #define IWM_PHY_RX_CHAIN_FORCE_SEL_POS (4) 2668 #define IWM_PHY_RX_CHAIN_FORCE_SEL_MSK \ 2669 (0x7 << IWM_PHY_RX_CHAIN_FORCE_SEL_POS) 2670 #define IWM_PHY_RX_CHAIN_FORCE_MIMO_SEL_POS (7) 2671 #define IWM_PHY_RX_CHAIN_FORCE_MIMO_SEL_MSK \ 2672 (0x7 << IWM_PHY_RX_CHAIN_FORCE_MIMO_SEL_POS) 2673 #define IWM_PHY_RX_CHAIN_CNT_POS (10) 2674 #define IWM_PHY_RX_CHAIN_CNT_MSK \ 2675 (0x3 << IWM_PHY_RX_CHAIN_CNT_POS) 2676 #define IWM_PHY_RX_CHAIN_MIMO_CNT_POS (12) 2677 #define IWM_PHY_RX_CHAIN_MIMO_CNT_MSK \ 2678 (0x3 << IWM_PHY_RX_CHAIN_MIMO_CNT_POS) 2679 #define IWM_PHY_RX_CHAIN_MIMO_FORCE_POS (14) 2680 #define IWM_PHY_RX_CHAIN_MIMO_FORCE_MSK \ 2681 (0x1 << IWM_PHY_RX_CHAIN_MIMO_FORCE_POS) 2682 2683 /* TODO: fix the value, make it depend on firmware at runtime? */ 2684 #define IWM_NUM_PHY_CTX 3 2685 2686 /* TODO: complete missing documentation */ 2687 /** 2688 * struct iwm_phy_context_cmd - config of the PHY context 2689 * ( IWM_PHY_CONTEXT_CMD = 0x8 ) 2690 * @id_and_color: ID and color of the relevant Binding 2691 * @action: action to perform, one of IWM_FW_CTXT_ACTION_* 2692 * @apply_time: 0 means immediate apply and context switch. 2693 * other value means apply new params after X usecs 2694 * @tx_param_color: ??? 2695 * @channel_info: 2696 * @txchain_info: ??? 2697 * @rxchain_info: ??? 2698 * @acquisition_data: ??? 2699 * @dsp_cfg_flags: set to 0 2700 */ 2701 struct iwm_phy_context_cmd { 2702 /* COMMON_INDEX_HDR_API_S_VER_1 */ 2703 uint32_t id_and_color; 2704 uint32_t action; 2705 /* IWM_PHY_CONTEXT_DATA_API_S_VER_1 */ 2706 uint32_t apply_time; 2707 uint32_t tx_param_color; 2708 struct iwm_fw_channel_info ci; 2709 uint32_t txchain_info; 2710 uint32_t rxchain_info; 2711 uint32_t acquisition_data; 2712 uint32_t dsp_cfg_flags; 2713 } __packed; /* IWM_PHY_CONTEXT_CMD_API_VER_1 */ 2714 2715 #define IWM_RX_INFO_PHY_CNT 8 2716 #define IWM_RX_INFO_ENERGY_ANT_ABC_IDX 1 2717 #define IWM_RX_INFO_ENERGY_ANT_A_MSK 0x000000ff 2718 #define IWM_RX_INFO_ENERGY_ANT_B_MSK 0x0000ff00 2719 #define IWM_RX_INFO_ENERGY_ANT_C_MSK 0x00ff0000 2720 #define IWM_RX_INFO_ENERGY_ANT_A_POS 0 2721 #define IWM_RX_INFO_ENERGY_ANT_B_POS 8 2722 #define IWM_RX_INFO_ENERGY_ANT_C_POS 16 2723 2724 #define IWM_RX_INFO_AGC_IDX 1 2725 #define IWM_RX_INFO_RSSI_AB_IDX 2 2726 #define IWM_OFDM_AGC_A_MSK 0x0000007f 2727 #define IWM_OFDM_AGC_A_POS 0 2728 #define IWM_OFDM_AGC_B_MSK 0x00003f80 2729 #define IWM_OFDM_AGC_B_POS 7 2730 #define IWM_OFDM_AGC_CODE_MSK 0x3fe00000 2731 #define IWM_OFDM_AGC_CODE_POS 20 2732 #define IWM_OFDM_RSSI_INBAND_A_MSK 0x00ff 2733 #define IWM_OFDM_RSSI_A_POS 0 2734 #define IWM_OFDM_RSSI_ALLBAND_A_MSK 0xff00 2735 #define IWM_OFDM_RSSI_ALLBAND_A_POS 8 2736 #define IWM_OFDM_RSSI_INBAND_B_MSK 0xff0000 2737 #define IWM_OFDM_RSSI_B_POS 16 2738 #define IWM_OFDM_RSSI_ALLBAND_B_MSK 0xff000000 2739 #define IWM_OFDM_RSSI_ALLBAND_B_POS 24 2740 2741 /** 2742 * struct iwm_rx_phy_info - phy info 2743 * (IWM_REPLY_RX_PHY_CMD = 0xc0) 2744 * @non_cfg_phy_cnt: non configurable DSP phy data byte count 2745 * @cfg_phy_cnt: configurable DSP phy data byte count 2746 * @stat_id: configurable DSP phy data set ID 2747 * @reserved1: 2748 * @system_timestamp: GP2 at on air rise 2749 * @timestamp: TSF at on air rise 2750 * @beacon_time_stamp: beacon at on-air rise 2751 * @phy_flags: general phy flags: band, modulation, ... 2752 * @channel: channel number 2753 * @non_cfg_phy_buf: for various implementations of non_cfg_phy 2754 * @rate_n_flags: IWM_RATE_MCS_* 2755 * @byte_count: frame's byte-count 2756 * @frame_time: frame's time on the air, based on byte count and frame rate 2757 * calculation 2758 * @mac_active_msk: what MACs were active when the frame was received 2759 * 2760 * Before each Rx, the device sends this data. It contains PHY information 2761 * about the reception of the packet. 2762 */ 2763 struct iwm_rx_phy_info { 2764 uint8_t non_cfg_phy_cnt; 2765 uint8_t cfg_phy_cnt; 2766 uint8_t stat_id; 2767 uint8_t reserved1; 2768 uint32_t system_timestamp; 2769 uint64_t timestamp; 2770 uint32_t beacon_time_stamp; 2771 uint16_t phy_flags; 2772 #define IWM_PHY_INFO_FLAG_SHPREAMBLE (1 << 2) 2773 uint16_t channel; 2774 uint32_t non_cfg_phy[IWM_RX_INFO_PHY_CNT]; 2775 uint8_t rate; 2776 uint8_t rflags; 2777 uint16_t xrflags; 2778 uint32_t byte_count; 2779 uint16_t mac_active_msk; 2780 uint16_t frame_time; 2781 } __packed; 2782 2783 struct iwm_rx_mpdu_res_start { 2784 uint16_t byte_count; 2785 uint16_t reserved; 2786 } __packed; 2787 2788 /** 2789 * enum iwm_rx_phy_flags - to parse %iwm_rx_phy_info phy_flags 2790 * @IWM_RX_RES_PHY_FLAGS_BAND_24: true if the packet was received on 2.4 band 2791 * @IWM_RX_RES_PHY_FLAGS_MOD_CCK: 2792 * @IWM_RX_RES_PHY_FLAGS_SHORT_PREAMBLE: true if packet's preamble was short 2793 * @IWM_RX_RES_PHY_FLAGS_NARROW_BAND: 2794 * @IWM_RX_RES_PHY_FLAGS_ANTENNA: antenna on which the packet was received 2795 * @IWM_RX_RES_PHY_FLAGS_AGG: set if the packet was part of an A-MPDU 2796 * @IWM_RX_RES_PHY_FLAGS_OFDM_HT: The frame was an HT frame 2797 * @IWM_RX_RES_PHY_FLAGS_OFDM_GF: The frame used GF preamble 2798 * @IWM_RX_RES_PHY_FLAGS_OFDM_VHT: The frame was a VHT frame 2799 */ 2800 enum iwm_rx_phy_flags { 2801 IWM_RX_RES_PHY_FLAGS_BAND_24 = (1 << 0), 2802 IWM_RX_RES_PHY_FLAGS_MOD_CCK = (1 << 1), 2803 IWM_RX_RES_PHY_FLAGS_SHORT_PREAMBLE = (1 << 2), 2804 IWM_RX_RES_PHY_FLAGS_NARROW_BAND = (1 << 3), 2805 IWM_RX_RES_PHY_FLAGS_ANTENNA = (0x7 << 4), 2806 IWM_RX_RES_PHY_FLAGS_ANTENNA_POS = 4, 2807 IWM_RX_RES_PHY_FLAGS_AGG = (1 << 7), 2808 IWM_RX_RES_PHY_FLAGS_OFDM_HT = (1 << 8), 2809 IWM_RX_RES_PHY_FLAGS_OFDM_GF = (1 << 9), 2810 IWM_RX_RES_PHY_FLAGS_OFDM_VHT = (1 << 10), 2811 }; 2812 2813 /** 2814 * enum iwm_mvm_rx_status - written by fw for each Rx packet 2815 * @IWM_RX_MPDU_RES_STATUS_CRC_OK: CRC is fine 2816 * @IWM_RX_MPDU_RES_STATUS_OVERRUN_OK: there was no RXE overflow 2817 * @IWM_RX_MPDU_RES_STATUS_SRC_STA_FOUND: 2818 * @IWM_RX_MPDU_RES_STATUS_KEY_VALID: 2819 * @IWM_RX_MPDU_RES_STATUS_KEY_PARAM_OK: 2820 * @IWM_RX_MPDU_RES_STATUS_ICV_OK: ICV is fine, if not, the packet is destroyed 2821 * @IWM_RX_MPDU_RES_STATUS_MIC_OK: used for CCM alg only. TKIP MIC is checked 2822 * in the driver. 2823 * @IWM_RX_MPDU_RES_STATUS_TTAK_OK: TTAK is fine 2824 * @IWM_RX_MPDU_RES_STATUS_MNG_FRAME_REPLAY_ERR: valid for alg = CCM_CMAC or 2825 * alg = CCM only. Checks replay attack for 11w frames. Relevant only if 2826 * %IWM_RX_MPDU_RES_STATUS_ROBUST_MNG_FRAME is set. 2827 * @IWM_RX_MPDU_RES_STATUS_SEC_NO_ENC: this frame is not encrypted 2828 * @IWM_RX_MPDU_RES_STATUS_SEC_WEP_ENC: this frame is encrypted using WEP 2829 * @IWM_RX_MPDU_RES_STATUS_SEC_CCM_ENC: this frame is encrypted using CCM 2830 * @IWM_RX_MPDU_RES_STATUS_SEC_TKIP_ENC: this frame is encrypted using TKIP 2831 * @IWM_RX_MPDU_RES_STATUS_SEC_CCM_CMAC_ENC: this frame is encrypted using CCM_CMAC 2832 * @IWM_RX_MPDU_RES_STATUS_SEC_ENC_ERR: this frame couldn't be decrypted 2833 * @IWM_RX_MPDU_RES_STATUS_SEC_ENC_MSK: bitmask of the encryption algorithm 2834 * @IWM_RX_MPDU_RES_STATUS_DEC_DONE: this frame has been successfully decrypted 2835 * @IWM_RX_MPDU_RES_STATUS_PROTECT_FRAME_BIT_CMP: 2836 * @IWM_RX_MPDU_RES_STATUS_EXT_IV_BIT_CMP: 2837 * @IWM_RX_MPDU_RES_STATUS_KEY_ID_CMP_BIT: 2838 * @IWM_RX_MPDU_RES_STATUS_ROBUST_MNG_FRAME: this frame is an 11w management frame 2839 * @IWM_RX_MPDU_RES_STATUS_HASH_INDEX_MSK: 2840 * @IWM_RX_MPDU_RES_STATUS_STA_ID_MSK: 2841 * @IWM_RX_MPDU_RES_STATUS_RRF_KILL: 2842 * @IWM_RX_MPDU_RES_STATUS_FILTERING_MSK: 2843 * @IWM_RX_MPDU_RES_STATUS2_FILTERING_MSK: 2844 */ 2845 enum iwm_mvm_rx_status { 2846 IWM_RX_MPDU_RES_STATUS_CRC_OK = (1 << 0), 2847 IWM_RX_MPDU_RES_STATUS_OVERRUN_OK = (1 << 1), 2848 IWM_RX_MPDU_RES_STATUS_SRC_STA_FOUND = (1 << 2), 2849 IWM_RX_MPDU_RES_STATUS_KEY_VALID = (1 << 3), 2850 IWM_RX_MPDU_RES_STATUS_KEY_PARAM_OK = (1 << 4), 2851 IWM_RX_MPDU_RES_STATUS_ICV_OK = (1 << 5), 2852 IWM_RX_MPDU_RES_STATUS_MIC_OK = (1 << 6), 2853 IWM_RX_MPDU_RES_STATUS_TTAK_OK = (1 << 7), 2854 IWM_RX_MPDU_RES_STATUS_MNG_FRAME_REPLAY_ERR = (1 << 7), 2855 IWM_RX_MPDU_RES_STATUS_SEC_NO_ENC = (0 << 8), 2856 IWM_RX_MPDU_RES_STATUS_SEC_WEP_ENC = (1 << 8), 2857 IWM_RX_MPDU_RES_STATUS_SEC_CCM_ENC = (2 << 8), 2858 IWM_RX_MPDU_RES_STATUS_SEC_TKIP_ENC = (3 << 8), 2859 IWM_RX_MPDU_RES_STATUS_SEC_EXT_ENC = (4 << 8), 2860 IWM_RX_MPDU_RES_STATUS_SEC_CCM_CMAC_ENC = (6 << 8), 2861 IWM_RX_MPDU_RES_STATUS_SEC_ENC_ERR = (7 << 8), 2862 IWM_RX_MPDU_RES_STATUS_SEC_ENC_MSK = (7 << 8), 2863 IWM_RX_MPDU_RES_STATUS_DEC_DONE = (1 << 11), 2864 IWM_RX_MPDU_RES_STATUS_PROTECT_FRAME_BIT_CMP = (1 << 12), 2865 IWM_RX_MPDU_RES_STATUS_EXT_IV_BIT_CMP = (1 << 13), 2866 IWM_RX_MPDU_RES_STATUS_KEY_ID_CMP_BIT = (1 << 14), 2867 IWM_RX_MPDU_RES_STATUS_ROBUST_MNG_FRAME = (1 << 15), 2868 IWM_RX_MPDU_RES_STATUS_HASH_INDEX_MSK = (0x3F0000), 2869 IWM_RX_MPDU_RES_STATUS_STA_ID_MSK = (0x1f000000), 2870 IWM_RX_MPDU_RES_STATUS_RRF_KILL = (1 << 29), 2871 IWM_RX_MPDU_RES_STATUS_FILTERING_MSK = (0xc00000), 2872 IWM_RX_MPDU_RES_STATUS2_FILTERING_MSK = (0xc0000000), 2873 }; 2874 2875 /** 2876 * struct iwm_radio_version_notif - information on the radio version 2877 * ( IWM_RADIO_VERSION_NOTIFICATION = 0x68 ) 2878 * @radio_flavor: 2879 * @radio_step: 2880 * @radio_dash: 2881 */ 2882 struct iwm_radio_version_notif { 2883 uint32_t radio_flavor; 2884 uint32_t radio_step; 2885 uint32_t radio_dash; 2886 } __packed; /* IWM_RADIO_VERSION_NOTOFICATION_S_VER_1 */ 2887 2888 enum iwm_card_state_flags { 2889 IWM_CARD_ENABLED = 0x00, 2890 IWM_HW_CARD_DISABLED = 0x01, 2891 IWM_SW_CARD_DISABLED = 0x02, 2892 IWM_CT_KILL_CARD_DISABLED = 0x04, 2893 IWM_HALT_CARD_DISABLED = 0x08, 2894 IWM_CARD_DISABLED_MSK = 0x0f, 2895 IWM_CARD_IS_RX_ON = 0x10, 2896 }; 2897 2898 /** 2899 * struct iwm_radio_version_notif - information on the radio version 2900 * (IWM_CARD_STATE_NOTIFICATION = 0xa1 ) 2901 * @flags: %iwm_card_state_flags 2902 */ 2903 struct iwm_card_state_notif { 2904 uint32_t flags; 2905 } __packed; /* CARD_STATE_NTFY_API_S_VER_1 */ 2906 2907 /** 2908 * struct iwm_missed_beacons_notif - information on missed beacons 2909 * ( IWM_MISSED_BEACONS_NOTIFICATION = 0xa2 ) 2910 * @mac_id: interface ID 2911 * @consec_missed_beacons_since_last_rx: number of consecutive missed 2912 * beacons since last RX. 2913 * @consec_missed_beacons: number of consecutive missed beacons 2914 * @num_expected_beacons: 2915 * @num_recvd_beacons: 2916 */ 2917 struct iwm_missed_beacons_notif { 2918 uint32_t mac_id; 2919 uint32_t consec_missed_beacons_since_last_rx; 2920 uint32_t consec_missed_beacons; 2921 uint32_t num_expected_beacons; 2922 uint32_t num_recvd_beacons; 2923 } __packed; /* IWM_MISSED_BEACON_NTFY_API_S_VER_3 */ 2924 2925 /** 2926 * struct iwm_mfuart_load_notif - mfuart image version & status 2927 * ( IWM_MFUART_LOAD_NOTIFICATION = 0xb1 ) 2928 * @installed_ver: installed image version 2929 * @external_ver: external image version 2930 * @status: MFUART loading status 2931 * @duration: MFUART loading time 2932 */ 2933 struct iwm_mfuart_load_notif { 2934 uint32_t installed_ver; 2935 uint32_t external_ver; 2936 uint32_t status; 2937 uint32_t duration; 2938 } __packed; /*MFU_LOADER_NTFY_API_S_VER_1*/ 2939 2940 /** 2941 * struct iwm_set_calib_default_cmd - set default value for calibration. 2942 * ( IWM_SET_CALIB_DEFAULT_CMD = 0x8e ) 2943 * @calib_index: the calibration to set value for 2944 * @length: of data 2945 * @data: the value to set for the calibration result 2946 */ 2947 struct iwm_set_calib_default_cmd { 2948 uint16_t calib_index; 2949 uint16_t length; 2950 uint8_t data[0]; 2951 } __packed; /* IWM_PHY_CALIB_OVERRIDE_VALUES_S */ 2952 2953 #define IWM_MAX_PORT_ID_NUM 2 2954 #define IWM_MAX_MCAST_FILTERING_ADDRESSES 256 2955 2956 /** 2957 * struct iwm_mcast_filter_cmd - configure multicast filter. 2958 * @filter_own: Set 1 to filter out multicast packets sent by station itself 2959 * @port_id: Multicast MAC addresses array specifier. This is a strange way 2960 * to identify network interface adopted in host-device IF. 2961 * It is used by FW as index in array of addresses. This array has 2962 * IWM_MAX_PORT_ID_NUM members. 2963 * @count: Number of MAC addresses in the array 2964 * @pass_all: Set 1 to pass all multicast packets. 2965 * @bssid: current association BSSID. 2966 * @addr_list: Place holder for array of MAC addresses. 2967 * IMPORTANT: add padding if necessary to ensure DWORD alignment. 2968 */ 2969 struct iwm_mcast_filter_cmd { 2970 uint8_t filter_own; 2971 uint8_t port_id; 2972 uint8_t count; 2973 uint8_t pass_all; 2974 uint8_t bssid[6]; 2975 uint8_t reserved[2]; 2976 uint8_t addr_list[0]; 2977 } __packed; /* IWM_MCAST_FILTERING_CMD_API_S_VER_1 */ 2978 2979 struct iwm_mvm_statistics_dbg { 2980 uint32_t burst_check; 2981 uint32_t burst_count; 2982 uint32_t wait_for_silence_timeout_cnt; 2983 uint32_t reserved[3]; 2984 } __packed; /* IWM_STATISTICS_DEBUG_API_S_VER_2 */ 2985 2986 struct iwm_mvm_statistics_div { 2987 uint32_t tx_on_a; 2988 uint32_t tx_on_b; 2989 uint32_t exec_time; 2990 uint32_t probe_time; 2991 uint32_t rssi_ant; 2992 uint32_t reserved2; 2993 } __packed; /* IWM_STATISTICS_SLOW_DIV_API_S_VER_2 */ 2994 2995 struct iwm_mvm_statistics_general_common { 2996 uint32_t temperature; /* radio temperature */ 2997 uint32_t temperature_m; /* radio voltage */ 2998 struct iwm_mvm_statistics_dbg dbg; 2999 uint32_t sleep_time; 3000 uint32_t slots_out; 3001 uint32_t slots_idle; 3002 uint32_t ttl_timestamp; 3003 struct iwm_mvm_statistics_div div; 3004 uint32_t rx_enable_counter; 3005 /* 3006 * num_of_sos_states: 3007 * count the number of times we have to re-tune 3008 * in order to get out of bad PHY status 3009 */ 3010 uint32_t num_of_sos_states; 3011 } __packed; /* IWM_STATISTICS_GENERAL_API_S_VER_5 */ 3012 3013 struct iwm_mvm_statistics_rx_non_phy { 3014 uint32_t bogus_cts; /* CTS received when not expecting CTS */ 3015 uint32_t bogus_ack; /* ACK received when not expecting ACK */ 3016 uint32_t non_bssid_frames; /* number of frames with BSSID that 3017 * doesn't belong to the STA BSSID */ 3018 uint32_t filtered_frames; /* count frames that were dumped in the 3019 * filtering process */ 3020 uint32_t non_channel_beacons; /* beacons with our bss id but not on 3021 * our serving channel */ 3022 uint32_t channel_beacons; /* beacons with our bss id and in our 3023 * serving channel */ 3024 uint32_t num_missed_bcon; /* number of missed beacons */ 3025 uint32_t adc_rx_saturation_time; /* count in 0.8us units the time the 3026 * ADC was in saturation */ 3027 uint32_t ina_detection_search_time;/* total time (in 0.8us) searched 3028 * for INA */ 3029 uint32_t beacon_silence_rssi[3];/* RSSI silence after beacon frame */ 3030 uint32_t interference_data_flag; /* flag for interference data 3031 * availability. 1 when data is 3032 * available. */ 3033 uint32_t channel_load; /* counts RX Enable time in uSec */ 3034 uint32_t dsp_false_alarms; /* DSP false alarm (both OFDM 3035 * and CCK) counter */ 3036 uint32_t beacon_rssi_a; 3037 uint32_t beacon_rssi_b; 3038 uint32_t beacon_rssi_c; 3039 uint32_t beacon_energy_a; 3040 uint32_t beacon_energy_b; 3041 uint32_t beacon_energy_c; 3042 uint32_t num_bt_kills; 3043 uint32_t mac_id; 3044 uint32_t directed_data_mpdu; 3045 } __packed; /* IWM_STATISTICS_RX_NON_PHY_API_S_VER_3 */ 3046 3047 struct iwm_mvm_statistics_rx_phy { 3048 uint32_t ina_cnt; 3049 uint32_t fina_cnt; 3050 uint32_t plcp_err; 3051 uint32_t crc32_err; 3052 uint32_t overrun_err; 3053 uint32_t early_overrun_err; 3054 uint32_t crc32_good; 3055 uint32_t false_alarm_cnt; 3056 uint32_t fina_sync_err_cnt; 3057 uint32_t sfd_timeout; 3058 uint32_t fina_timeout; 3059 uint32_t unresponded_rts; 3060 uint32_t rxe_frame_limit_overrun; 3061 uint32_t sent_ack_cnt; 3062 uint32_t sent_cts_cnt; 3063 uint32_t sent_ba_rsp_cnt; 3064 uint32_t dsp_self_kill; 3065 uint32_t mh_format_err; 3066 uint32_t re_acq_main_rssi_sum; 3067 uint32_t reserved; 3068 } __packed; /* IWM_STATISTICS_RX_PHY_API_S_VER_2 */ 3069 3070 struct iwm_mvm_statistics_rx_ht_phy { 3071 uint32_t plcp_err; 3072 uint32_t overrun_err; 3073 uint32_t early_overrun_err; 3074 uint32_t crc32_good; 3075 uint32_t crc32_err; 3076 uint32_t mh_format_err; 3077 uint32_t agg_crc32_good; 3078 uint32_t agg_mpdu_cnt; 3079 uint32_t agg_cnt; 3080 uint32_t unsupport_mcs; 3081 } __packed; /* IWM_STATISTICS_HT_RX_PHY_API_S_VER_1 */ 3082 3083 #define IWM_MAX_CHAINS 3 3084 3085 struct iwm_mvm_statistics_tx_non_phy_agg { 3086 uint32_t ba_timeout; 3087 uint32_t ba_reschedule_frames; 3088 uint32_t scd_query_agg_frame_cnt; 3089 uint32_t scd_query_no_agg; 3090 uint32_t scd_query_agg; 3091 uint32_t scd_query_mismatch; 3092 uint32_t frame_not_ready; 3093 uint32_t underrun; 3094 uint32_t bt_prio_kill; 3095 uint32_t rx_ba_rsp_cnt; 3096 int8_t txpower[IWM_MAX_CHAINS]; 3097 int8_t reserved; 3098 uint32_t reserved2; 3099 } __packed; /* IWM_STATISTICS_TX_NON_PHY_AGG_API_S_VER_1 */ 3100 3101 struct iwm_mvm_statistics_tx_channel_width { 3102 uint32_t ext_cca_narrow_ch20[1]; 3103 uint32_t ext_cca_narrow_ch40[2]; 3104 uint32_t ext_cca_narrow_ch80[3]; 3105 uint32_t ext_cca_narrow_ch160[4]; 3106 uint32_t last_tx_ch_width_indx; 3107 uint32_t rx_detected_per_ch_width[4]; 3108 uint32_t success_per_ch_width[4]; 3109 uint32_t fail_per_ch_width[4]; 3110 }; /* IWM_STATISTICS_TX_CHANNEL_WIDTH_API_S_VER_1 */ 3111 3112 struct iwm_mvm_statistics_tx { 3113 uint32_t preamble_cnt; 3114 uint32_t rx_detected_cnt; 3115 uint32_t bt_prio_defer_cnt; 3116 uint32_t bt_prio_kill_cnt; 3117 uint32_t few_bytes_cnt; 3118 uint32_t cts_timeout; 3119 uint32_t ack_timeout; 3120 uint32_t expected_ack_cnt; 3121 uint32_t actual_ack_cnt; 3122 uint32_t dump_msdu_cnt; 3123 uint32_t burst_abort_next_frame_mismatch_cnt; 3124 uint32_t burst_abort_missing_next_frame_cnt; 3125 uint32_t cts_timeout_collision; 3126 uint32_t ack_or_ba_timeout_collision; 3127 struct iwm_mvm_statistics_tx_non_phy_agg agg; 3128 struct iwm_mvm_statistics_tx_channel_width channel_width; 3129 } __packed; /* IWM_STATISTICS_TX_API_S_VER_4 */ 3130 3131 3132 struct iwm_mvm_statistics_bt_activity { 3133 uint32_t hi_priority_tx_req_cnt; 3134 uint32_t hi_priority_tx_denied_cnt; 3135 uint32_t lo_priority_tx_req_cnt; 3136 uint32_t lo_priority_tx_denied_cnt; 3137 uint32_t hi_priority_rx_req_cnt; 3138 uint32_t hi_priority_rx_denied_cnt; 3139 uint32_t lo_priority_rx_req_cnt; 3140 uint32_t lo_priority_rx_denied_cnt; 3141 } __packed; /* IWM_STATISTICS_BT_ACTIVITY_API_S_VER_1 */ 3142 3143 struct iwm_mvm_statistics_general { 3144 struct iwm_mvm_statistics_general_common common; 3145 uint32_t beacon_filtered; 3146 uint32_t missed_beacons; 3147 int8_t beacon_filter_average_energy; 3148 int8_t beacon_filter_reason; 3149 int8_t beacon_filter_current_energy; 3150 int8_t beacon_filter_reserved; 3151 uint32_t beacon_filter_delta_time; 3152 struct iwm_mvm_statistics_bt_activity bt_activity; 3153 } __packed; /* IWM_STATISTICS_GENERAL_API_S_VER_5 */ 3154 3155 struct iwm_mvm_statistics_rx { 3156 struct iwm_mvm_statistics_rx_phy ofdm; 3157 struct iwm_mvm_statistics_rx_phy cck; 3158 struct iwm_mvm_statistics_rx_non_phy general; 3159 struct iwm_mvm_statistics_rx_ht_phy ofdm_ht; 3160 } __packed; /* IWM_STATISTICS_RX_API_S_VER_3 */ 3161 3162 /* 3163 * IWM_STATISTICS_NOTIFICATION = 0x9d (notification only, not a command) 3164 * 3165 * By default, uCode issues this notification after receiving a beacon 3166 * while associated. To disable this behavior, set DISABLE_NOTIF flag in the 3167 * IWM_REPLY_STATISTICS_CMD 0x9c, above. 3168 * 3169 * Statistics counters continue to increment beacon after beacon, but are 3170 * cleared when changing channels or when driver issues IWM_REPLY_STATISTICS_CMD 3171 * 0x9c with CLEAR_STATS bit set (see above). 3172 * 3173 * uCode also issues this notification during scans. uCode clears statistics 3174 * appropriately so that each notification contains statistics for only the 3175 * one channel that has just been scanned. 3176 */ 3177 3178 struct iwm_notif_statistics { /* IWM_STATISTICS_NTFY_API_S_VER_8 */ 3179 uint32_t flag; 3180 struct iwm_mvm_statistics_rx rx; 3181 struct iwm_mvm_statistics_tx tx; 3182 struct iwm_mvm_statistics_general general; 3183 } __packed; 3184 3185 /*********************************** 3186 * Smart Fifo API 3187 ***********************************/ 3188 /* Smart Fifo state */ 3189 enum iwm_sf_state { 3190 IWM_SF_LONG_DELAY_ON = 0, /* should never be called by driver */ 3191 IWM_SF_FULL_ON, 3192 IWM_SF_UNINIT, 3193 IWM_SF_INIT_OFF, 3194 IWM_SF_HW_NUM_STATES 3195 }; 3196 3197 /* Smart Fifo possible scenario */ 3198 enum iwm_sf_scenario { 3199 IWM_SF_SCENARIO_SINGLE_UNICAST, 3200 IWM_SF_SCENARIO_AGG_UNICAST, 3201 IWM_SF_SCENARIO_MULTICAST, 3202 IWM_SF_SCENARIO_BA_RESP, 3203 IWM_SF_SCENARIO_TX_RESP, 3204 IWM_SF_NUM_SCENARIO 3205 }; 3206 3207 #define IWM_SF_TRANSIENT_STATES_NUMBER 2 /* IWM_SF_LONG_DELAY_ON and IWM_SF_FULL_ON */ 3208 #define IWM_SF_NUM_TIMEOUT_TYPES 2 /* Aging timer and Idle timer */ 3209 3210 /* smart FIFO default values */ 3211 #define IWM_SF_W_MARK_SISO 4096 3212 #define IWM_SF_W_MARK_MIMO2 8192 3213 #define IWM_SF_W_MARK_MIMO3 6144 3214 #define IWM_SF_W_MARK_LEGACY 4096 3215 #define IWM_SF_W_MARK_SCAN 4096 3216 3217 /* SF Scenarios timers for default configuration (aligned to 32 uSec) */ 3218 #define IWM_SF_SINGLE_UNICAST_IDLE_TIMER_DEF 160 /* 150 uSec */ 3219 #define IWM_SF_SINGLE_UNICAST_AGING_TIMER_DEF 400 /* 0.4 mSec */ 3220 #define IWM_SF_AGG_UNICAST_IDLE_TIMER_DEF 160 /* 150 uSec */ 3221 #define IWM_SF_AGG_UNICAST_AGING_TIMER_DEF 400 /* 0.4 mSec */ 3222 #define IWM_SF_MCAST_IDLE_TIMER_DEF 160 /* 150 mSec */ 3223 #define IWM_SF_MCAST_AGING_TIMER_DEF 400 /* 0.4 mSec */ 3224 #define IWM_SF_BA_IDLE_TIMER_DEF 160 /* 150 uSec */ 3225 #define IWM_SF_BA_AGING_TIMER_DEF 400 /* 0.4 mSec */ 3226 #define IWM_SF_TX_RE_IDLE_TIMER_DEF 160 /* 150 uSec */ 3227 #define IWM_SF_TX_RE_AGING_TIMER_DEF 400 /* 0.4 mSec */ 3228 3229 /* SF Scenarios timers for FULL_ON state (aligned to 32 uSec) */ 3230 #define IWM_SF_SINGLE_UNICAST_IDLE_TIMER 320 /* 300 uSec */ 3231 #define IWM_SF_SINGLE_UNICAST_AGING_TIMER 2016 /* 2 mSec */ 3232 #define IWM_SF_AGG_UNICAST_IDLE_TIMER 320 /* 300 uSec */ 3233 #define IWM_SF_AGG_UNICAST_AGING_TIMER 2016 /* 2 mSec */ 3234 #define IWM_SF_MCAST_IDLE_TIMER 2016 /* 2 mSec */ 3235 #define IWM_SF_MCAST_AGING_TIMER 10016 /* 10 mSec */ 3236 #define IWM_SF_BA_IDLE_TIMER 320 /* 300 uSec */ 3237 #define IWM_SF_BA_AGING_TIMER 2016 /* 2 mSec */ 3238 #define IWM_SF_TX_RE_IDLE_TIMER 320 /* 300 uSec */ 3239 #define IWM_SF_TX_RE_AGING_TIMER 2016 /* 2 mSec */ 3240 3241 #define IWM_SF_LONG_DELAY_AGING_TIMER 1000000 /* 1 Sec */ 3242 3243 #define IWM_SF_CFG_DUMMY_NOTIF_OFF (1 << 16) 3244 3245 /** 3246 * Smart Fifo configuration command. 3247 * @state: smart fifo state, types listed in iwm_sf_sate. 3248 * @watermark: Minimum allowed available free space in RXF for transient state. 3249 * @long_delay_timeouts: aging and idle timer values for each scenario 3250 * in long delay state. 3251 * @full_on_timeouts: timer values for each scenario in full on state. 3252 */ 3253 struct iwm_sf_cfg_cmd { 3254 enum iwm_sf_state state; 3255 uint32_t watermark[IWM_SF_TRANSIENT_STATES_NUMBER]; 3256 uint32_t long_delay_timeouts[IWM_SF_NUM_SCENARIO][IWM_SF_NUM_TIMEOUT_TYPES]; 3257 uint32_t full_on_timeouts[IWM_SF_NUM_SCENARIO][IWM_SF_NUM_TIMEOUT_TYPES]; 3258 } __packed; /* IWM_SF_CFG_API_S_VER_2 */ 3259 3260 /* 3261 * END mvm/fw-api.h 3262 */ 3263 3264 /* 3265 * BEGIN mvm/fw-api-mac.h 3266 */ 3267 3268 /* 3269 * The first MAC indices (starting from 0) 3270 * are available to the driver, AUX follows 3271 */ 3272 #define IWM_MAC_INDEX_AUX 4 3273 #define IWM_MAC_INDEX_MIN_DRIVER 0 3274 #define IWM_NUM_MAC_INDEX_DRIVER IWM_MAC_INDEX_AUX 3275 3276 enum iwm_ac { 3277 IWM_AC_BK, 3278 IWM_AC_BE, 3279 IWM_AC_VI, 3280 IWM_AC_VO, 3281 IWM_AC_NUM, 3282 }; 3283 3284 /** 3285 * enum iwm_mac_protection_flags - MAC context flags 3286 * @IWM_MAC_PROT_FLG_TGG_PROTECT: 11g protection when transmitting OFDM frames, 3287 * this will require CCK RTS/CTS2self. 3288 * RTS/CTS will protect full burst time. 3289 * @IWM_MAC_PROT_FLG_HT_PROT: enable HT protection 3290 * @IWM_MAC_PROT_FLG_FAT_PROT: protect 40 MHz transmissions 3291 * @IWM_MAC_PROT_FLG_SELF_CTS_EN: allow CTS2self 3292 */ 3293 enum iwm_mac_protection_flags { 3294 IWM_MAC_PROT_FLG_TGG_PROTECT = (1 << 3), 3295 IWM_MAC_PROT_FLG_HT_PROT = (1 << 23), 3296 IWM_MAC_PROT_FLG_FAT_PROT = (1 << 24), 3297 IWM_MAC_PROT_FLG_SELF_CTS_EN = (1 << 30), 3298 }; 3299 3300 #define IWM_MAC_FLG_SHORT_SLOT (1 << 4) 3301 #define IWM_MAC_FLG_SHORT_PREAMBLE (1 << 5) 3302 3303 /** 3304 * enum iwm_mac_types - Supported MAC types 3305 * @IWM_FW_MAC_TYPE_FIRST: lowest supported MAC type 3306 * @IWM_FW_MAC_TYPE_AUX: Auxiliary MAC (internal) 3307 * @IWM_FW_MAC_TYPE_LISTENER: monitor MAC type (?) 3308 * @IWM_FW_MAC_TYPE_PIBSS: Pseudo-IBSS 3309 * @IWM_FW_MAC_TYPE_IBSS: IBSS 3310 * @IWM_FW_MAC_TYPE_BSS_STA: BSS (managed) station 3311 * @IWM_FW_MAC_TYPE_P2P_DEVICE: P2P Device 3312 * @IWM_FW_MAC_TYPE_P2P_STA: P2P client 3313 * @IWM_FW_MAC_TYPE_GO: P2P GO 3314 * @IWM_FW_MAC_TYPE_TEST: ? 3315 * @IWM_FW_MAC_TYPE_MAX: highest support MAC type 3316 */ 3317 enum iwm_mac_types { 3318 IWM_FW_MAC_TYPE_FIRST = 1, 3319 IWM_FW_MAC_TYPE_AUX = IWM_FW_MAC_TYPE_FIRST, 3320 IWM_FW_MAC_TYPE_LISTENER, 3321 IWM_FW_MAC_TYPE_PIBSS, 3322 IWM_FW_MAC_TYPE_IBSS, 3323 IWM_FW_MAC_TYPE_BSS_STA, 3324 IWM_FW_MAC_TYPE_P2P_DEVICE, 3325 IWM_FW_MAC_TYPE_P2P_STA, 3326 IWM_FW_MAC_TYPE_GO, 3327 IWM_FW_MAC_TYPE_TEST, 3328 IWM_FW_MAC_TYPE_MAX = IWM_FW_MAC_TYPE_TEST 3329 }; /* IWM_MAC_CONTEXT_TYPE_API_E_VER_1 */ 3330 3331 /** 3332 * enum iwm_tsf_id - TSF hw timer ID 3333 * @IWM_TSF_ID_A: use TSF A 3334 * @IWM_TSF_ID_B: use TSF B 3335 * @IWM_TSF_ID_C: use TSF C 3336 * @IWM_TSF_ID_D: use TSF D 3337 * @IWM_NUM_TSF_IDS: number of TSF timers available 3338 */ 3339 enum iwm_tsf_id { 3340 IWM_TSF_ID_A = 0, 3341 IWM_TSF_ID_B = 1, 3342 IWM_TSF_ID_C = 2, 3343 IWM_TSF_ID_D = 3, 3344 IWM_NUM_TSF_IDS = 4, 3345 }; /* IWM_TSF_ID_API_E_VER_1 */ 3346 3347 /** 3348 * struct iwm_mac_data_ap - configuration data for AP MAC context 3349 * @beacon_time: beacon transmit time in system time 3350 * @beacon_tsf: beacon transmit time in TSF 3351 * @bi: beacon interval in TU 3352 * @bi_reciprocal: 2^32 / bi 3353 * @dtim_interval: dtim transmit time in TU 3354 * @dtim_reciprocal: 2^32 / dtim_interval 3355 * @mcast_qid: queue ID for multicast traffic 3356 * @beacon_template: beacon template ID 3357 */ 3358 struct iwm_mac_data_ap { 3359 uint32_t beacon_time; 3360 uint64_t beacon_tsf; 3361 uint32_t bi; 3362 uint32_t bi_reciprocal; 3363 uint32_t dtim_interval; 3364 uint32_t dtim_reciprocal; 3365 uint32_t mcast_qid; 3366 uint32_t beacon_template; 3367 } __packed; /* AP_MAC_DATA_API_S_VER_1 */ 3368 3369 /** 3370 * struct iwm_mac_data_ibss - configuration data for IBSS MAC context 3371 * @beacon_time: beacon transmit time in system time 3372 * @beacon_tsf: beacon transmit time in TSF 3373 * @bi: beacon interval in TU 3374 * @bi_reciprocal: 2^32 / bi 3375 * @beacon_template: beacon template ID 3376 */ 3377 struct iwm_mac_data_ibss { 3378 uint32_t beacon_time; 3379 uint64_t beacon_tsf; 3380 uint32_t bi; 3381 uint32_t bi_reciprocal; 3382 uint32_t beacon_template; 3383 } __packed; /* IBSS_MAC_DATA_API_S_VER_1 */ 3384 3385 /** 3386 * struct iwm_mac_data_sta - configuration data for station MAC context 3387 * @is_assoc: 1 for associated state, 0 otherwise 3388 * @dtim_time: DTIM arrival time in system time 3389 * @dtim_tsf: DTIM arrival time in TSF 3390 * @bi: beacon interval in TU, applicable only when associated 3391 * @bi_reciprocal: 2^32 / bi , applicable only when associated 3392 * @dtim_interval: DTIM interval in TU, applicable only when associated 3393 * @dtim_reciprocal: 2^32 / dtim_interval , applicable only when associated 3394 * @listen_interval: in beacon intervals, applicable only when associated 3395 * @assoc_id: unique ID assigned by the AP during association 3396 */ 3397 struct iwm_mac_data_sta { 3398 uint32_t is_assoc; 3399 uint32_t dtim_time; 3400 uint64_t dtim_tsf; 3401 uint32_t bi; 3402 uint32_t bi_reciprocal; 3403 uint32_t dtim_interval; 3404 uint32_t dtim_reciprocal; 3405 uint32_t listen_interval; 3406 uint32_t assoc_id; 3407 uint32_t assoc_beacon_arrive_time; 3408 } __packed; /* IWM_STA_MAC_DATA_API_S_VER_1 */ 3409 3410 /** 3411 * struct iwm_mac_data_go - configuration data for P2P GO MAC context 3412 * @ap: iwm_mac_data_ap struct with most config data 3413 * @ctwin: client traffic window in TU (period after TBTT when GO is present). 3414 * 0 indicates that there is no CT window. 3415 * @opp_ps_enabled: indicate that opportunistic PS allowed 3416 */ 3417 struct iwm_mac_data_go { 3418 struct iwm_mac_data_ap ap; 3419 uint32_t ctwin; 3420 uint32_t opp_ps_enabled; 3421 } __packed; /* GO_MAC_DATA_API_S_VER_1 */ 3422 3423 /** 3424 * struct iwm_mac_data_p2p_sta - configuration data for P2P client MAC context 3425 * @sta: iwm_mac_data_sta struct with most config data 3426 * @ctwin: client traffic window in TU (period after TBTT when GO is present). 3427 * 0 indicates that there is no CT window. 3428 */ 3429 struct iwm_mac_data_p2p_sta { 3430 struct iwm_mac_data_sta sta; 3431 uint32_t ctwin; 3432 } __packed; /* P2P_STA_MAC_DATA_API_S_VER_1 */ 3433 3434 /** 3435 * struct iwm_mac_data_pibss - Pseudo IBSS config data 3436 * @stats_interval: interval in TU between statistics notifications to host. 3437 */ 3438 struct iwm_mac_data_pibss { 3439 uint32_t stats_interval; 3440 } __packed; /* PIBSS_MAC_DATA_API_S_VER_1 */ 3441 3442 /* 3443 * struct iwm_mac_data_p2p_dev - configuration data for the P2P Device MAC 3444 * context. 3445 * @is_disc_extended: if set to true, P2P Device discoverability is enabled on 3446 * other channels as well. This should be to true only in case that the 3447 * device is discoverable and there is an active GO. Note that setting this 3448 * field when not needed, will increase the number of interrupts and have 3449 * effect on the platform power, as this setting opens the Rx filters on 3450 * all macs. 3451 */ 3452 struct iwm_mac_data_p2p_dev { 3453 uint32_t is_disc_extended; 3454 } __packed; /* _P2P_DEV_MAC_DATA_API_S_VER_1 */ 3455 3456 /** 3457 * enum iwm_mac_filter_flags - MAC context filter flags 3458 * @IWM_MAC_FILTER_IN_PROMISC: accept all data frames 3459 * @IWM_MAC_FILTER_IN_CONTROL_AND_MGMT: pass all mangement and 3460 * control frames to the host 3461 * @IWM_MAC_FILTER_ACCEPT_GRP: accept multicast frames 3462 * @IWM_MAC_FILTER_DIS_DECRYPT: don't decrypt unicast frames 3463 * @IWM_MAC_FILTER_DIS_GRP_DECRYPT: don't decrypt multicast frames 3464 * @IWM_MAC_FILTER_IN_BEACON: transfer foreign BSS's beacons to host 3465 * (in station mode when associated) 3466 * @IWM_MAC_FILTER_OUT_BCAST: filter out all broadcast frames 3467 * @IWM_MAC_FILTER_IN_CRC32: extract FCS and append it to frames 3468 * @IWM_MAC_FILTER_IN_PROBE_REQUEST: pass probe requests to host 3469 */ 3470 enum iwm_mac_filter_flags { 3471 IWM_MAC_FILTER_IN_PROMISC = (1 << 0), 3472 IWM_MAC_FILTER_IN_CONTROL_AND_MGMT = (1 << 1), 3473 IWM_MAC_FILTER_ACCEPT_GRP = (1 << 2), 3474 IWM_MAC_FILTER_DIS_DECRYPT = (1 << 3), 3475 IWM_MAC_FILTER_DIS_GRP_DECRYPT = (1 << 4), 3476 IWM_MAC_FILTER_IN_BEACON = (1 << 6), 3477 IWM_MAC_FILTER_OUT_BCAST = (1 << 8), 3478 IWM_MAC_FILTER_IN_CRC32 = (1 << 11), 3479 IWM_MAC_FILTER_IN_PROBE_REQUEST = (1 << 12), 3480 }; 3481 3482 /** 3483 * enum iwm_mac_qos_flags - QoS flags 3484 * @IWM_MAC_QOS_FLG_UPDATE_EDCA: ? 3485 * @IWM_MAC_QOS_FLG_TGN: HT is enabled 3486 * @IWM_MAC_QOS_FLG_TXOP_TYPE: ? 3487 * 3488 */ 3489 enum iwm_mac_qos_flags { 3490 IWM_MAC_QOS_FLG_UPDATE_EDCA = (1 << 0), 3491 IWM_MAC_QOS_FLG_TGN = (1 << 1), 3492 IWM_MAC_QOS_FLG_TXOP_TYPE = (1 << 4), 3493 }; 3494 3495 /** 3496 * struct iwm_ac_qos - QOS timing params for IWM_MAC_CONTEXT_CMD 3497 * @cw_min: Contention window, start value in numbers of slots. 3498 * Should be a power-of-2, minus 1. Device's default is 0x0f. 3499 * @cw_max: Contention window, max value in numbers of slots. 3500 * Should be a power-of-2, minus 1. Device's default is 0x3f. 3501 * @aifsn: Number of slots in Arbitration Interframe Space (before 3502 * performing random backoff timing prior to Tx). Device default 1. 3503 * @fifos_mask: FIFOs used by this MAC for this AC 3504 * @edca_txop: Length of Tx opportunity, in uSecs. Device default is 0. 3505 * 3506 * One instance of this config struct for each of 4 EDCA access categories 3507 * in struct iwm_qosparam_cmd. 3508 * 3509 * Device will automatically increase contention window by (2*CW) + 1 for each 3510 * transmission retry. Device uses cw_max as a bit mask, ANDed with new CW 3511 * value, to cap the CW value. 3512 */ 3513 struct iwm_ac_qos { 3514 uint16_t cw_min; 3515 uint16_t cw_max; 3516 uint8_t aifsn; 3517 uint8_t fifos_mask; 3518 uint16_t edca_txop; 3519 } __packed; /* IWM_AC_QOS_API_S_VER_2 */ 3520 3521 /** 3522 * struct iwm_mac_ctx_cmd - command structure to configure MAC contexts 3523 * ( IWM_MAC_CONTEXT_CMD = 0x28 ) 3524 * @id_and_color: ID and color of the MAC 3525 * @action: action to perform, one of IWM_FW_CTXT_ACTION_* 3526 * @mac_type: one of IWM_FW_MAC_TYPE_* 3527 * @tsd_id: TSF HW timer, one of IWM_TSF_ID_* 3528 * @node_addr: MAC address 3529 * @bssid_addr: BSSID 3530 * @cck_rates: basic rates available for CCK 3531 * @ofdm_rates: basic rates available for OFDM 3532 * @protection_flags: combination of IWM_MAC_PROT_FLG_FLAG_* 3533 * @cck_short_preamble: 0x20 for enabling short preamble, 0 otherwise 3534 * @short_slot: 0x10 for enabling short slots, 0 otherwise 3535 * @filter_flags: combination of IWM_MAC_FILTER_* 3536 * @qos_flags: from IWM_MAC_QOS_FLG_* 3537 * @ac: one iwm_mac_qos configuration for each AC 3538 * @mac_specific: one of struct iwm_mac_data_*, according to mac_type 3539 */ 3540 struct iwm_mac_ctx_cmd { 3541 /* COMMON_INDEX_HDR_API_S_VER_1 */ 3542 uint32_t id_and_color; 3543 uint32_t action; 3544 /* IWM_MAC_CONTEXT_COMMON_DATA_API_S_VER_1 */ 3545 uint32_t mac_type; 3546 uint32_t tsf_id; 3547 uint8_t node_addr[6]; 3548 uint16_t reserved_for_node_addr; 3549 uint8_t bssid_addr[6]; 3550 uint16_t reserved_for_bssid_addr; 3551 uint32_t cck_rates; 3552 uint32_t ofdm_rates; 3553 uint32_t protection_flags; 3554 uint32_t cck_short_preamble; 3555 uint32_t short_slot; 3556 uint32_t filter_flags; 3557 /* IWM_MAC_QOS_PARAM_API_S_VER_1 */ 3558 uint32_t qos_flags; 3559 struct iwm_ac_qos ac[IWM_AC_NUM+1]; 3560 /* IWM_MAC_CONTEXT_COMMON_DATA_API_S */ 3561 union { 3562 struct iwm_mac_data_ap ap; 3563 struct iwm_mac_data_go go; 3564 struct iwm_mac_data_sta sta; 3565 struct iwm_mac_data_p2p_sta p2p_sta; 3566 struct iwm_mac_data_p2p_dev p2p_dev; 3567 struct iwm_mac_data_pibss pibss; 3568 struct iwm_mac_data_ibss ibss; 3569 }; 3570 } __packed; /* IWM_MAC_CONTEXT_CMD_API_S_VER_1 */ 3571 3572 static inline uint32_t iwm_mvm_reciprocal(uint32_t v) 3573 { 3574 if (!v) 3575 return 0; 3576 return 0xFFFFFFFF / v; 3577 } 3578 3579 #define IWM_NONQOS_SEQ_GET 0x1 3580 #define IWM_NONQOS_SEQ_SET 0x2 3581 struct iwm_nonqos_seq_query_cmd { 3582 uint32_t get_set_flag; 3583 uint32_t mac_id_n_color; 3584 uint16_t value; 3585 uint16_t reserved; 3586 } __packed; /* IWM_NON_QOS_TX_COUNTER_GET_SET_API_S_VER_1 */ 3587 3588 /* 3589 * END mvm/fw-api-mac.h 3590 */ 3591 3592 /* 3593 * BEGIN mvm/fw-api-power.h 3594 */ 3595 3596 /* Power Management Commands, Responses, Notifications */ 3597 3598 /* Radio LP RX Energy Threshold measured in dBm */ 3599 #define IWM_POWER_LPRX_RSSI_THRESHOLD 75 3600 #define IWM_POWER_LPRX_RSSI_THRESHOLD_MAX 94 3601 #define IWM_POWER_LPRX_RSSI_THRESHOLD_MIN 30 3602 3603 /** 3604 * enum iwm_scan_flags - masks for power table command flags 3605 * @IWM_POWER_FLAGS_POWER_SAVE_ENA_MSK: '1' Allow to save power by turning off 3606 * receiver and transmitter. '0' - does not allow. 3607 * @IWM_POWER_FLAGS_POWER_MANAGEMENT_ENA_MSK: '0' Driver disables power management, 3608 * '1' Driver enables PM (use rest of parameters) 3609 * @IWM_POWER_FLAGS_SKIP_OVER_DTIM_MSK: '0' PM have to walk up every DTIM, 3610 * '1' PM could sleep over DTIM till listen Interval. 3611 * @IWM_POWER_FLAGS_SNOOZE_ENA_MSK: Enable snoozing only if uAPSD is enabled and all 3612 * access categories are both delivery and trigger enabled. 3613 * @IWM_POWER_FLAGS_BT_SCO_ENA: Enable BT SCO coex only if uAPSD and 3614 * PBW Snoozing enabled 3615 * @IWM_POWER_FLAGS_ADVANCE_PM_ENA_MSK: Advanced PM (uAPSD) enable mask 3616 * @IWM_POWER_FLAGS_LPRX_ENA_MSK: Low Power RX enable. 3617 * @IWM_POWER_FLAGS_AP_UAPSD_MISBEHAVING_ENA_MSK: AP/GO's uAPSD misbehaving 3618 * detection enablement 3619 */ 3620 enum iwm_power_flags { 3621 IWM_POWER_FLAGS_POWER_SAVE_ENA_MSK = (1 << 0), 3622 IWM_POWER_FLAGS_POWER_MANAGEMENT_ENA_MSK = (1 << 1), 3623 IWM_POWER_FLAGS_SKIP_OVER_DTIM_MSK = (1 << 2), 3624 IWM_POWER_FLAGS_SNOOZE_ENA_MSK = (1 << 5), 3625 IWM_POWER_FLAGS_BT_SCO_ENA = (1 << 8), 3626 IWM_POWER_FLAGS_ADVANCE_PM_ENA_MSK = (1 << 9), 3627 IWM_POWER_FLAGS_LPRX_ENA_MSK = (1 << 11), 3628 IWM_POWER_FLAGS_UAPSD_MISBEHAVING_ENA_MSK = (1 << 12), 3629 }; 3630 3631 #define IWM_POWER_VEC_SIZE 5 3632 3633 /** 3634 * struct iwm_powertable_cmd - legacy power command. Beside old API support this 3635 * is used also with a new power API for device wide power settings. 3636 * IWM_POWER_TABLE_CMD = 0x77 (command, has simple generic response) 3637 * 3638 * @flags: Power table command flags from IWM_POWER_FLAGS_* 3639 * @keep_alive_seconds: Keep alive period in seconds. Default - 25 sec. 3640 * Minimum allowed:- 3 * DTIM. Keep alive period must be 3641 * set regardless of power scheme or current power state. 3642 * FW use this value also when PM is disabled. 3643 * @rx_data_timeout: Minimum time (usec) from last Rx packet for AM to 3644 * PSM transition - legacy PM 3645 * @tx_data_timeout: Minimum time (usec) from last Tx packet for AM to 3646 * PSM transition - legacy PM 3647 * @sleep_interval: not in use 3648 * @skip_dtim_periods: Number of DTIM periods to skip if Skip over DTIM flag 3649 * is set. For example, if it is required to skip over 3650 * one DTIM, this value need to be set to 2 (DTIM periods). 3651 * @lprx_rssi_threshold: Signal strength up to which LP RX can be enabled. 3652 * Default: 80dbm 3653 */ 3654 struct iwm_powertable_cmd { 3655 /* PM_POWER_TABLE_CMD_API_S_VER_6 */ 3656 uint16_t flags; 3657 uint8_t keep_alive_seconds; 3658 uint8_t debug_flags; 3659 uint32_t rx_data_timeout; 3660 uint32_t tx_data_timeout; 3661 uint32_t sleep_interval[IWM_POWER_VEC_SIZE]; 3662 uint32_t skip_dtim_periods; 3663 uint32_t lprx_rssi_threshold; 3664 } __packed; 3665 3666 /** 3667 * enum iwm_device_power_flags - masks for device power command flags 3668 * @DEVIC_POWER_FLAGS_POWER_SAVE_ENA_MSK: '1' Allow to save power by turning off 3669 * receiver and transmitter. '0' - does not allow. This flag should be 3670 * always set to '1' unless one need to disable actual power down for debug 3671 * purposes. 3672 * @IWM_DEVICE_POWER_FLAGS_CAM_MSK: '1' CAM (Continuous Active Mode) is set, meaning 3673 * that power management is disabled. '0' Power management is enabled, one 3674 * of power schemes is applied. 3675 */ 3676 enum iwm_device_power_flags { 3677 IWM_DEVICE_POWER_FLAGS_POWER_SAVE_ENA_MSK = (1 << 0), 3678 IWM_DEVICE_POWER_FLAGS_CAM_MSK = (1 << 13), 3679 }; 3680 3681 /** 3682 * struct iwm_device_power_cmd - device wide power command. 3683 * IWM_DEVICE_POWER_CMD = 0x77 (command, has simple generic response) 3684 * 3685 * @flags: Power table command flags from IWM_DEVICE_POWER_FLAGS_* 3686 */ 3687 struct iwm_device_power_cmd { 3688 /* PM_POWER_TABLE_CMD_API_S_VER_6 */ 3689 uint16_t flags; 3690 uint16_t reserved; 3691 } __packed; 3692 3693 /** 3694 * struct iwm_mac_power_cmd - New power command containing uAPSD support 3695 * IWM_MAC_PM_POWER_TABLE = 0xA9 (command, has simple generic response) 3696 * @id_and_color: MAC contex identifier 3697 * @flags: Power table command flags from POWER_FLAGS_* 3698 * @keep_alive_seconds: Keep alive period in seconds. Default - 25 sec. 3699 * Minimum allowed:- 3 * DTIM. Keep alive period must be 3700 * set regardless of power scheme or current power state. 3701 * FW use this value also when PM is disabled. 3702 * @rx_data_timeout: Minimum time (usec) from last Rx packet for AM to 3703 * PSM transition - legacy PM 3704 * @tx_data_timeout: Minimum time (usec) from last Tx packet for AM to 3705 * PSM transition - legacy PM 3706 * @sleep_interval: not in use 3707 * @skip_dtim_periods: Number of DTIM periods to skip if Skip over DTIM flag 3708 * is set. For example, if it is required to skip over 3709 * one DTIM, this value need to be set to 2 (DTIM periods). 3710 * @rx_data_timeout_uapsd: Minimum time (usec) from last Rx packet for AM to 3711 * PSM transition - uAPSD 3712 * @tx_data_timeout_uapsd: Minimum time (usec) from last Tx packet for AM to 3713 * PSM transition - uAPSD 3714 * @lprx_rssi_threshold: Signal strength up to which LP RX can be enabled. 3715 * Default: 80dbm 3716 * @num_skip_dtim: Number of DTIMs to skip if Skip over DTIM flag is set 3717 * @snooze_interval: Maximum time between attempts to retrieve buffered data 3718 * from the AP [msec] 3719 * @snooze_window: A window of time in which PBW snoozing insures that all 3720 * packets received. It is also the minimum time from last 3721 * received unicast RX packet, before client stops snoozing 3722 * for data. [msec] 3723 * @snooze_step: TBD 3724 * @qndp_tid: TID client shall use for uAPSD QNDP triggers 3725 * @uapsd_ac_flags: Set trigger-enabled and delivery-enabled indication for 3726 * each corresponding AC. 3727 * Use IEEE80211_WMM_IE_STA_QOSINFO_AC* for correct values. 3728 * @uapsd_max_sp: Use IEEE80211_WMM_IE_STA_QOSINFO_SP_* for correct 3729 * values. 3730 * @heavy_tx_thld_packets: TX threshold measured in number of packets 3731 * @heavy_rx_thld_packets: RX threshold measured in number of packets 3732 * @heavy_tx_thld_percentage: TX threshold measured in load's percentage 3733 * @heavy_rx_thld_percentage: RX threshold measured in load's percentage 3734 * @limited_ps_threshold: 3735 */ 3736 struct iwm_mac_power_cmd { 3737 /* CONTEXT_DESC_API_T_VER_1 */ 3738 uint32_t id_and_color; 3739 3740 /* CLIENT_PM_POWER_TABLE_S_VER_1 */ 3741 uint16_t flags; 3742 uint16_t keep_alive_seconds; 3743 uint32_t rx_data_timeout; 3744 uint32_t tx_data_timeout; 3745 uint32_t rx_data_timeout_uapsd; 3746 uint32_t tx_data_timeout_uapsd; 3747 uint8_t lprx_rssi_threshold; 3748 uint8_t skip_dtim_periods; 3749 uint16_t snooze_interval; 3750 uint16_t snooze_window; 3751 uint8_t snooze_step; 3752 uint8_t qndp_tid; 3753 uint8_t uapsd_ac_flags; 3754 uint8_t uapsd_max_sp; 3755 uint8_t heavy_tx_thld_packets; 3756 uint8_t heavy_rx_thld_packets; 3757 uint8_t heavy_tx_thld_percentage; 3758 uint8_t heavy_rx_thld_percentage; 3759 uint8_t limited_ps_threshold; 3760 uint8_t reserved; 3761 } __packed; 3762 3763 /* 3764 * struct iwm_uapsd_misbehaving_ap_notif - FW sends this notification when 3765 * associated AP is identified as improperly implementing uAPSD protocol. 3766 * IWM_PSM_UAPSD_AP_MISBEHAVING_NOTIFICATION = 0x78 3767 * @sta_id: index of station in uCode's station table - associated AP ID in 3768 * this context. 3769 */ 3770 struct iwm_uapsd_misbehaving_ap_notif { 3771 uint32_t sta_id; 3772 uint8_t mac_id; 3773 uint8_t reserved[3]; 3774 } __packed; 3775 3776 /** 3777 * struct iwm_beacon_filter_cmd 3778 * IWM_REPLY_BEACON_FILTERING_CMD = 0xd2 (command) 3779 * @id_and_color: MAC contex identifier 3780 * @bf_energy_delta: Used for RSSI filtering, if in 'normal' state. Send beacon 3781 * to driver if delta in Energy values calculated for this and last 3782 * passed beacon is greater than this threshold. Zero value means that 3783 * the Energy change is ignored for beacon filtering, and beacon will 3784 * not be forced to be sent to driver regardless of this delta. Typical 3785 * energy delta 5dB. 3786 * @bf_roaming_energy_delta: Used for RSSI filtering, if in 'roaming' state. 3787 * Send beacon to driver if delta in Energy values calculated for this 3788 * and last passed beacon is greater than this threshold. Zero value 3789 * means that the Energy change is ignored for beacon filtering while in 3790 * Roaming state, typical energy delta 1dB. 3791 * @bf_roaming_state: Used for RSSI filtering. If absolute Energy values 3792 * calculated for current beacon is less than the threshold, use 3793 * Roaming Energy Delta Threshold, otherwise use normal Energy Delta 3794 * Threshold. Typical energy threshold is -72dBm. 3795 * @bf_temp_threshold: This threshold determines the type of temperature 3796 * filtering (Slow or Fast) that is selected (Units are in Celsuis): 3797 * If the current temperature is above this threshold - Fast filter 3798 * will be used, If the current temperature is below this threshold - 3799 * Slow filter will be used. 3800 * @bf_temp_fast_filter: Send Beacon to driver if delta in temperature values 3801 * calculated for this and the last passed beacon is greater than this 3802 * threshold. Zero value means that the temperature change is ignored for 3803 * beacon filtering; beacons will not be forced to be sent to driver 3804 * regardless of whether its temperature has been changed. 3805 * @bf_temp_slow_filter: Send Beacon to driver if delta in temperature values 3806 * calculated for this and the last passed beacon is greater than this 3807 * threshold. Zero value means that the temperature change is ignored for 3808 * beacon filtering; beacons will not be forced to be sent to driver 3809 * regardless of whether its temperature has been changed. 3810 * @bf_enable_beacon_filter: 1, beacon filtering is enabled; 0, disabled. 3811 * @bf_filter_escape_timer: Send beacons to to driver if no beacons were passed 3812 * for a specific period of time. Units: Beacons. 3813 * @ba_escape_timer: Fully receive and parse beacon if no beacons were passed 3814 * for a longer period of time then this escape-timeout. Units: Beacons. 3815 * @ba_enable_beacon_abort: 1, beacon abort is enabled; 0, disabled. 3816 */ 3817 struct iwm_beacon_filter_cmd { 3818 uint32_t bf_energy_delta; 3819 uint32_t bf_roaming_energy_delta; 3820 uint32_t bf_roaming_state; 3821 uint32_t bf_temp_threshold; 3822 uint32_t bf_temp_fast_filter; 3823 uint32_t bf_temp_slow_filter; 3824 uint32_t bf_enable_beacon_filter; 3825 uint32_t bf_debug_flag; 3826 uint32_t bf_escape_timer; 3827 uint32_t ba_escape_timer; 3828 uint32_t ba_enable_beacon_abort; 3829 } __packed; 3830 3831 /* Beacon filtering and beacon abort */ 3832 #define IWM_BF_ENERGY_DELTA_DEFAULT 5 3833 #define IWM_BF_ENERGY_DELTA_MAX 255 3834 #define IWM_BF_ENERGY_DELTA_MIN 0 3835 3836 #define IWM_BF_ROAMING_ENERGY_DELTA_DEFAULT 1 3837 #define IWM_BF_ROAMING_ENERGY_DELTA_MAX 255 3838 #define IWM_BF_ROAMING_ENERGY_DELTA_MIN 0 3839 3840 #define IWM_BF_ROAMING_STATE_DEFAULT 72 3841 #define IWM_BF_ROAMING_STATE_MAX 255 3842 #define IWM_BF_ROAMING_STATE_MIN 0 3843 3844 #define IWM_BF_TEMP_THRESHOLD_DEFAULT 112 3845 #define IWM_BF_TEMP_THRESHOLD_MAX 255 3846 #define IWM_BF_TEMP_THRESHOLD_MIN 0 3847 3848 #define IWM_BF_TEMP_FAST_FILTER_DEFAULT 1 3849 #define IWM_BF_TEMP_FAST_FILTER_MAX 255 3850 #define IWM_BF_TEMP_FAST_FILTER_MIN 0 3851 3852 #define IWM_BF_TEMP_SLOW_FILTER_DEFAULT 5 3853 #define IWM_BF_TEMP_SLOW_FILTER_MAX 255 3854 #define IWM_BF_TEMP_SLOW_FILTER_MIN 0 3855 3856 #define IWM_BF_ENABLE_BEACON_FILTER_DEFAULT 1 3857 3858 #define IWM_BF_DEBUG_FLAG_DEFAULT 0 3859 3860 #define IWM_BF_ESCAPE_TIMER_DEFAULT 50 3861 #define IWM_BF_ESCAPE_TIMER_MAX 1024 3862 #define IWM_BF_ESCAPE_TIMER_MIN 0 3863 3864 #define IWM_BA_ESCAPE_TIMER_DEFAULT 6 3865 #define IWM_BA_ESCAPE_TIMER_D3 9 3866 #define IWM_BA_ESCAPE_TIMER_MAX 1024 3867 #define IWM_BA_ESCAPE_TIMER_MIN 0 3868 3869 #define IWM_BA_ENABLE_BEACON_ABORT_DEFAULT 1 3870 3871 #define IWM_BF_CMD_CONFIG_DEFAULTS \ 3872 .bf_energy_delta = htole32(IWM_BF_ENERGY_DELTA_DEFAULT), \ 3873 .bf_roaming_energy_delta = \ 3874 htole32(IWM_BF_ROAMING_ENERGY_DELTA_DEFAULT), \ 3875 .bf_roaming_state = htole32(IWM_BF_ROAMING_STATE_DEFAULT), \ 3876 .bf_temp_threshold = htole32(IWM_BF_TEMP_THRESHOLD_DEFAULT), \ 3877 .bf_temp_fast_filter = htole32(IWM_BF_TEMP_FAST_FILTER_DEFAULT), \ 3878 .bf_temp_slow_filter = htole32(IWM_BF_TEMP_SLOW_FILTER_DEFAULT), \ 3879 .bf_debug_flag = htole32(IWM_BF_DEBUG_FLAG_DEFAULT), \ 3880 .bf_escape_timer = htole32(IWM_BF_ESCAPE_TIMER_DEFAULT), \ 3881 .ba_escape_timer = htole32(IWM_BA_ESCAPE_TIMER_DEFAULT) 3882 3883 /* 3884 * END mvm/fw-api-power.h 3885 */ 3886 3887 /* 3888 * BEGIN mvm/fw-api-rs.h 3889 */ 3890 3891 /* 3892 * These serve as indexes into 3893 * struct iwm_rate_info fw_rate_idx_to_plcp[IWM_RATE_COUNT]; 3894 * TODO: avoid overlap between legacy and HT rates 3895 */ 3896 enum { 3897 IWM_RATE_1M_INDEX = 0, 3898 IWM_FIRST_CCK_RATE = IWM_RATE_1M_INDEX, 3899 IWM_RATE_2M_INDEX, 3900 IWM_RATE_5M_INDEX, 3901 IWM_RATE_11M_INDEX, 3902 IWM_LAST_CCK_RATE = IWM_RATE_11M_INDEX, 3903 IWM_RATE_6M_INDEX, 3904 IWM_FIRST_OFDM_RATE = IWM_RATE_6M_INDEX, 3905 IWM_RATE_MCS_0_INDEX = IWM_RATE_6M_INDEX, 3906 IWM_FIRST_HT_RATE = IWM_RATE_MCS_0_INDEX, 3907 IWM_FIRST_VHT_RATE = IWM_RATE_MCS_0_INDEX, 3908 IWM_RATE_9M_INDEX, 3909 IWM_RATE_12M_INDEX, 3910 IWM_RATE_MCS_1_INDEX = IWM_RATE_12M_INDEX, 3911 IWM_RATE_18M_INDEX, 3912 IWM_RATE_MCS_2_INDEX = IWM_RATE_18M_INDEX, 3913 IWM_RATE_24M_INDEX, 3914 IWM_RATE_MCS_3_INDEX = IWM_RATE_24M_INDEX, 3915 IWM_RATE_36M_INDEX, 3916 IWM_RATE_MCS_4_INDEX = IWM_RATE_36M_INDEX, 3917 IWM_RATE_48M_INDEX, 3918 IWM_RATE_MCS_5_INDEX = IWM_RATE_48M_INDEX, 3919 IWM_RATE_54M_INDEX, 3920 IWM_RATE_MCS_6_INDEX = IWM_RATE_54M_INDEX, 3921 IWM_LAST_NON_HT_RATE = IWM_RATE_54M_INDEX, 3922 IWM_RATE_60M_INDEX, 3923 IWM_RATE_MCS_7_INDEX = IWM_RATE_60M_INDEX, 3924 IWM_LAST_HT_RATE = IWM_RATE_MCS_7_INDEX, 3925 IWM_RATE_MCS_8_INDEX, 3926 IWM_RATE_MCS_9_INDEX, 3927 IWM_LAST_VHT_RATE = IWM_RATE_MCS_9_INDEX, 3928 IWM_RATE_COUNT_LEGACY = IWM_LAST_NON_HT_RATE + 1, 3929 IWM_RATE_COUNT = IWM_LAST_VHT_RATE + 1, 3930 }; 3931 3932 #define IWM_RATE_BIT_MSK(r) (1 << (IWM_RATE_##r##M_INDEX)) 3933 3934 /* fw API values for legacy bit rates, both OFDM and CCK */ 3935 enum { 3936 IWM_RATE_6M_PLCP = 13, 3937 IWM_RATE_9M_PLCP = 15, 3938 IWM_RATE_12M_PLCP = 5, 3939 IWM_RATE_18M_PLCP = 7, 3940 IWM_RATE_24M_PLCP = 9, 3941 IWM_RATE_36M_PLCP = 11, 3942 IWM_RATE_48M_PLCP = 1, 3943 IWM_RATE_54M_PLCP = 3, 3944 IWM_RATE_1M_PLCP = 10, 3945 IWM_RATE_2M_PLCP = 20, 3946 IWM_RATE_5M_PLCP = 55, 3947 IWM_RATE_11M_PLCP = 110, 3948 IWM_RATE_INVM_PLCP = -1, 3949 }; 3950 3951 /* 3952 * rate_n_flags bit fields 3953 * 3954 * The 32-bit value has different layouts in the low 8 bites depending on the 3955 * format. There are three formats, HT, VHT and legacy (11abg, with subformats 3956 * for CCK and OFDM). 3957 * 3958 * High-throughput (HT) rate format 3959 * bit 8 is 1, bit 26 is 0, bit 9 is 0 (OFDM) 3960 * Very High-throughput (VHT) rate format 3961 * bit 8 is 0, bit 26 is 1, bit 9 is 0 (OFDM) 3962 * Legacy OFDM rate format for bits 7:0 3963 * bit 8 is 0, bit 26 is 0, bit 9 is 0 (OFDM) 3964 * Legacy CCK rate format for bits 7:0: 3965 * bit 8 is 0, bit 26 is 0, bit 9 is 1 (CCK) 3966 */ 3967 3968 /* Bit 8: (1) HT format, (0) legacy or VHT format */ 3969 #define IWM_RATE_MCS_HT_POS 8 3970 #define IWM_RATE_MCS_HT_MSK (1 << IWM_RATE_MCS_HT_POS) 3971 3972 /* Bit 9: (1) CCK, (0) OFDM. HT (bit 8) must be "0" for this bit to be valid */ 3973 #define IWM_RATE_MCS_CCK_POS 9 3974 #define IWM_RATE_MCS_CCK_MSK (1 << IWM_RATE_MCS_CCK_POS) 3975 3976 /* Bit 26: (1) VHT format, (0) legacy format in bits 8:0 */ 3977 #define IWM_RATE_MCS_VHT_POS 26 3978 #define IWM_RATE_MCS_VHT_MSK (1 << IWM_RATE_MCS_VHT_POS) 3979 3980 3981 /* 3982 * High-throughput (HT) rate format for bits 7:0 3983 * 3984 * 2-0: MCS rate base 3985 * 0) 6 Mbps 3986 * 1) 12 Mbps 3987 * 2) 18 Mbps 3988 * 3) 24 Mbps 3989 * 4) 36 Mbps 3990 * 5) 48 Mbps 3991 * 6) 54 Mbps 3992 * 7) 60 Mbps 3993 * 4-3: 0) Single stream (SISO) 3994 * 1) Dual stream (MIMO) 3995 * 2) Triple stream (MIMO) 3996 * 5: Value of 0x20 in bits 7:0 indicates 6 Mbps HT40 duplicate data 3997 * (bits 7-6 are zero) 3998 * 3999 * Together the low 5 bits work out to the MCS index because we don't 4000 * support MCSes above 15/23, and 0-7 have one stream, 8-15 have two 4001 * streams and 16-23 have three streams. We could also support MCS 32 4002 * which is the duplicate 20 MHz MCS (bit 5 set, all others zero.) 4003 */ 4004 #define IWM_RATE_HT_MCS_RATE_CODE_MSK 0x7 4005 #define IWM_RATE_HT_MCS_NSS_POS 3 4006 #define IWM_RATE_HT_MCS_NSS_MSK (3 << IWM_RATE_HT_MCS_NSS_POS) 4007 4008 /* Bit 10: (1) Use Green Field preamble */ 4009 #define IWM_RATE_HT_MCS_GF_POS 10 4010 #define IWM_RATE_HT_MCS_GF_MSK (1 << IWM_RATE_HT_MCS_GF_POS) 4011 4012 #define IWM_RATE_HT_MCS_INDEX_MSK 0x3f 4013 4014 /* 4015 * Very High-throughput (VHT) rate format for bits 7:0 4016 * 4017 * 3-0: VHT MCS (0-9) 4018 * 5-4: number of streams - 1: 4019 * 0) Single stream (SISO) 4020 * 1) Dual stream (MIMO) 4021 * 2) Triple stream (MIMO) 4022 */ 4023 4024 /* Bit 4-5: (0) SISO, (1) MIMO2 (2) MIMO3 */ 4025 #define IWM_RATE_VHT_MCS_RATE_CODE_MSK 0xf 4026 #define IWM_RATE_VHT_MCS_NSS_POS 4 4027 #define IWM_RATE_VHT_MCS_NSS_MSK (3 << IWM_RATE_VHT_MCS_NSS_POS) 4028 4029 /* 4030 * Legacy OFDM rate format for bits 7:0 4031 * 4032 * 3-0: 0xD) 6 Mbps 4033 * 0xF) 9 Mbps 4034 * 0x5) 12 Mbps 4035 * 0x7) 18 Mbps 4036 * 0x9) 24 Mbps 4037 * 0xB) 36 Mbps 4038 * 0x1) 48 Mbps 4039 * 0x3) 54 Mbps 4040 * (bits 7-4 are 0) 4041 * 4042 * Legacy CCK rate format for bits 7:0: 4043 * bit 8 is 0, bit 26 is 0, bit 9 is 1 (CCK): 4044 * 4045 * 6-0: 10) 1 Mbps 4046 * 20) 2 Mbps 4047 * 55) 5.5 Mbps 4048 * 110) 11 Mbps 4049 * (bit 7 is 0) 4050 */ 4051 #define IWM_RATE_LEGACY_RATE_MSK 0xff 4052 4053 4054 /* 4055 * Bit 11-12: (0) 20MHz, (1) 40MHz, (2) 80MHz, (3) 160MHz 4056 * 0 and 1 are valid for HT and VHT, 2 and 3 only for VHT 4057 */ 4058 #define IWM_RATE_MCS_CHAN_WIDTH_POS 11 4059 #define IWM_RATE_MCS_CHAN_WIDTH_MSK (3 << IWM_RATE_MCS_CHAN_WIDTH_POS) 4060 #define IWM_RATE_MCS_CHAN_WIDTH_20 (0 << IWM_RATE_MCS_CHAN_WIDTH_POS) 4061 #define IWM_RATE_MCS_CHAN_WIDTH_40 (1 << IWM_RATE_MCS_CHAN_WIDTH_POS) 4062 #define IWM_RATE_MCS_CHAN_WIDTH_80 (2 << IWM_RATE_MCS_CHAN_WIDTH_POS) 4063 #define IWM_RATE_MCS_CHAN_WIDTH_160 (3 << IWM_RATE_MCS_CHAN_WIDTH_POS) 4064 4065 /* Bit 13: (1) Short guard interval (0.4 usec), (0) normal GI (0.8 usec) */ 4066 #define IWM_RATE_MCS_SGI_POS 13 4067 #define IWM_RATE_MCS_SGI_MSK (1 << IWM_RATE_MCS_SGI_POS) 4068 4069 /* Bit 14-16: Antenna selection (1) Ant A, (2) Ant B, (4) Ant C */ 4070 #define IWM_RATE_MCS_ANT_POS 14 4071 #define IWM_RATE_MCS_ANT_A_MSK (1 << IWM_RATE_MCS_ANT_POS) 4072 #define IWM_RATE_MCS_ANT_B_MSK (2 << IWM_RATE_MCS_ANT_POS) 4073 #define IWM_RATE_MCS_ANT_C_MSK (4 << IWM_RATE_MCS_ANT_POS) 4074 #define IWM_RATE_MCS_ANT_AB_MSK (IWM_RATE_MCS_ANT_A_MSK | \ 4075 IWM_RATE_MCS_ANT_B_MSK) 4076 #define IWM_RATE_MCS_ANT_ABC_MSK (IWM_RATE_MCS_ANT_AB_MSK | \ 4077 IWM_RATE_MCS_ANT_C_MSK) 4078 #define IWM_RATE_MCS_ANT_MSK IWM_RATE_MCS_ANT_ABC_MSK 4079 #define IWM_RATE_MCS_ANT_NUM 3 4080 4081 /* Bit 17-18: (0) SS, (1) SS*2 */ 4082 #define IWM_RATE_MCS_STBC_POS 17 4083 #define IWM_RATE_MCS_STBC_MSK (1 << IWM_RATE_MCS_STBC_POS) 4084 4085 /* Bit 19: (0) Beamforming is off, (1) Beamforming is on */ 4086 #define IWM_RATE_MCS_BF_POS 19 4087 #define IWM_RATE_MCS_BF_MSK (1 << IWM_RATE_MCS_BF_POS) 4088 4089 /* Bit 20: (0) ZLF is off, (1) ZLF is on */ 4090 #define IWM_RATE_MCS_ZLF_POS 20 4091 #define IWM_RATE_MCS_ZLF_MSK (1 << IWM_RATE_MCS_ZLF_POS) 4092 4093 /* Bit 24-25: (0) 20MHz (no dup), (1) 2x20MHz, (2) 4x20MHz, 3 8x20MHz */ 4094 #define IWM_RATE_MCS_DUP_POS 24 4095 #define IWM_RATE_MCS_DUP_MSK (3 << IWM_RATE_MCS_DUP_POS) 4096 4097 /* Bit 27: (1) LDPC enabled, (0) LDPC disabled */ 4098 #define IWM_RATE_MCS_LDPC_POS 27 4099 #define IWM_RATE_MCS_LDPC_MSK (1 << IWM_RATE_MCS_LDPC_POS) 4100 4101 4102 /* Link Quality definitions */ 4103 4104 /* # entries in rate scale table to support Tx retries */ 4105 #define IWM_LQ_MAX_RETRY_NUM 16 4106 4107 /* Link quality command flags bit fields */ 4108 4109 /* Bit 0: (0) Don't use RTS (1) Use RTS */ 4110 #define IWM_LQ_FLAG_USE_RTS_POS 0 4111 #define IWM_LQ_FLAG_USE_RTS_MSK (1 << IWM_LQ_FLAG_USE_RTS_POS) 4112 4113 /* Bit 1-3: LQ command color. Used to match responses to LQ commands */ 4114 #define IWM_LQ_FLAG_COLOR_POS 1 4115 #define IWM_LQ_FLAG_COLOR_MSK (7 << IWM_LQ_FLAG_COLOR_POS) 4116 4117 /* Bit 4-5: Tx RTS BW Signalling 4118 * (0) No RTS BW signalling 4119 * (1) Static BW signalling 4120 * (2) Dynamic BW signalling 4121 */ 4122 #define IWM_LQ_FLAG_RTS_BW_SIG_POS 4 4123 #define IWM_LQ_FLAG_RTS_BW_SIG_NONE (0 << IWM_LQ_FLAG_RTS_BW_SIG_POS) 4124 #define IWM_LQ_FLAG_RTS_BW_SIG_STATIC (1 << IWM_LQ_FLAG_RTS_BW_SIG_POS) 4125 #define IWM_LQ_FLAG_RTS_BW_SIG_DYNAMIC (2 << IWM_LQ_FLAG_RTS_BW_SIG_POS) 4126 4127 /* Bit 6: (0) No dynamic BW selection (1) Allow dynamic BW selection 4128 * Dyanmic BW selection allows Tx with narrower BW then requested in rates 4129 */ 4130 #define IWM_LQ_FLAG_DYNAMIC_BW_POS 6 4131 #define IWM_LQ_FLAG_DYNAMIC_BW_MSK (1 << IWM_LQ_FLAG_DYNAMIC_BW_POS) 4132 4133 /** 4134 * struct iwm_lq_cmd - link quality command 4135 * @sta_id: station to update 4136 * @control: not used 4137 * @flags: combination of IWM_LQ_FLAG_* 4138 * @mimo_delim: the first SISO index in rs_table, which separates MIMO 4139 * and SISO rates 4140 * @single_stream_ant_msk: best antenna for SISO (can be dual in CDD). 4141 * Should be ANT_[ABC] 4142 * @dual_stream_ant_msk: best antennas for MIMO, combination of ANT_[ABC] 4143 * @initial_rate_index: first index from rs_table per AC category 4144 * @agg_time_limit: aggregation max time threshold in usec/100, meaning 4145 * value of 100 is one usec. Range is 100 to 8000 4146 * @agg_disable_start_th: try-count threshold for starting aggregation. 4147 * If a frame has higher try-count, it should not be selected for 4148 * starting an aggregation sequence. 4149 * @agg_frame_cnt_limit: max frame count in an aggregation. 4150 * 0: no limit 4151 * 1: no aggregation (one frame per aggregation) 4152 * 2 - 0x3f: maximal number of frames (up to 3f == 63) 4153 * @rs_table: array of rates for each TX try, each is rate_n_flags, 4154 * meaning it is a combination of IWM_RATE_MCS_* and IWM_RATE_*_PLCP 4155 * @bf_params: beam forming params, currently not used 4156 */ 4157 struct iwm_lq_cmd { 4158 uint8_t sta_id; 4159 uint8_t reserved1; 4160 uint16_t control; 4161 /* LINK_QUAL_GENERAL_PARAMS_API_S_VER_1 */ 4162 uint8_t flags; 4163 uint8_t mimo_delim; 4164 uint8_t single_stream_ant_msk; 4165 uint8_t dual_stream_ant_msk; 4166 uint8_t initial_rate_index[IWM_AC_NUM]; 4167 /* LINK_QUAL_AGG_PARAMS_API_S_VER_1 */ 4168 uint16_t agg_time_limit; 4169 uint8_t agg_disable_start_th; 4170 uint8_t agg_frame_cnt_limit; 4171 uint32_t reserved2; 4172 uint32_t rs_table[IWM_LQ_MAX_RETRY_NUM]; 4173 uint32_t bf_params; 4174 }; /* LINK_QUALITY_CMD_API_S_VER_1 */ 4175 4176 /* 4177 * END mvm/fw-api-rs.h 4178 */ 4179 4180 /* 4181 * BEGIN mvm/fw-api-tx.h 4182 */ 4183 4184 /** 4185 * enum iwm_tx_flags - bitmasks for tx_flags in TX command 4186 * @IWM_TX_CMD_FLG_PROT_REQUIRE: use RTS or CTS-to-self to protect the frame 4187 * @IWM_TX_CMD_FLG_ACK: expect ACK from receiving station 4188 * @IWM_TX_CMD_FLG_STA_RATE: use RS table with initial index from the TX command. 4189 * Otherwise, use rate_n_flags from the TX command 4190 * @IWM_TX_CMD_FLG_BA: this frame is a block ack 4191 * @IWM_TX_CMD_FLG_BAR: this frame is a BA request, immediate BAR is expected 4192 * Must set IWM_TX_CMD_FLG_ACK with this flag. 4193 * @IWM_TX_CMD_FLG_TXOP_PROT: protect frame with full TXOP protection 4194 * @IWM_TX_CMD_FLG_VHT_NDPA: mark frame is NDPA for VHT beamformer sequence 4195 * @IWM_TX_CMD_FLG_HT_NDPA: mark frame is NDPA for HT beamformer sequence 4196 * @IWM_TX_CMD_FLG_CSI_FDBK2HOST: mark to send feedback to host (only if good CRC) 4197 * @IWM_TX_CMD_FLG_BT_DIS: disable BT priority for this frame 4198 * @IWM_TX_CMD_FLG_SEQ_CTL: set if FW should override the sequence control. 4199 * Should be set for mgmt, non-QOS data, mcast, bcast and in scan command 4200 * @IWM_TX_CMD_FLG_MORE_FRAG: this frame is non-last MPDU 4201 * @IWM_TX_CMD_FLG_NEXT_FRAME: this frame includes information of the next frame 4202 * @IWM_TX_CMD_FLG_TSF: FW should calculate and insert TSF in the frame 4203 * Should be set for beacons and probe responses 4204 * @IWM_TX_CMD_FLG_CALIB: activate PA TX power calibrations 4205 * @IWM_TX_CMD_FLG_KEEP_SEQ_CTL: if seq_ctl is set, don't increase inner seq count 4206 * @IWM_TX_CMD_FLG_AGG_START: allow this frame to start aggregation 4207 * @IWM_TX_CMD_FLG_MH_PAD: driver inserted 2 byte padding after MAC header. 4208 * Should be set for 26/30 length MAC headers 4209 * @IWM_TX_CMD_FLG_RESP_TO_DRV: zero this if the response should go only to FW 4210 * @IWM_TX_CMD_FLG_CCMP_AGG: this frame uses CCMP for aggregation acceleration 4211 * @IWM_TX_CMD_FLG_TKIP_MIC_DONE: FW already performed TKIP MIC calculation 4212 * @IWM_TX_CMD_FLG_DUR: disable duration overwriting used in PS-Poll Assoc-id 4213 * @IWM_TX_CMD_FLG_FW_DROP: FW should mark frame to be dropped 4214 * @IWM_TX_CMD_FLG_EXEC_PAPD: execute PAPD 4215 * @IWM_TX_CMD_FLG_PAPD_TYPE: 0 for reference power, 1 for nominal power 4216 * @IWM_TX_CMD_FLG_HCCA_CHUNK: mark start of TSPEC chunk 4217 */ 4218 enum iwm_tx_flags { 4219 IWM_TX_CMD_FLG_PROT_REQUIRE = (1 << 0), 4220 IWM_TX_CMD_FLG_ACK = (1 << 3), 4221 IWM_TX_CMD_FLG_STA_RATE = (1 << 4), 4222 IWM_TX_CMD_FLG_BA = (1 << 5), 4223 IWM_TX_CMD_FLG_BAR = (1 << 6), 4224 IWM_TX_CMD_FLG_TXOP_PROT = (1 << 7), 4225 IWM_TX_CMD_FLG_VHT_NDPA = (1 << 8), 4226 IWM_TX_CMD_FLG_HT_NDPA = (1 << 9), 4227 IWM_TX_CMD_FLG_CSI_FDBK2HOST = (1 << 10), 4228 IWM_TX_CMD_FLG_BT_DIS = (1 << 12), 4229 IWM_TX_CMD_FLG_SEQ_CTL = (1 << 13), 4230 IWM_TX_CMD_FLG_MORE_FRAG = (1 << 14), 4231 IWM_TX_CMD_FLG_NEXT_FRAME = (1 << 15), 4232 IWM_TX_CMD_FLG_TSF = (1 << 16), 4233 IWM_TX_CMD_FLG_CALIB = (1 << 17), 4234 IWM_TX_CMD_FLG_KEEP_SEQ_CTL = (1 << 18), 4235 IWM_TX_CMD_FLG_AGG_START = (1 << 19), 4236 IWM_TX_CMD_FLG_MH_PAD = (1 << 20), 4237 IWM_TX_CMD_FLG_RESP_TO_DRV = (1 << 21), 4238 IWM_TX_CMD_FLG_CCMP_AGG = (1 << 22), 4239 IWM_TX_CMD_FLG_TKIP_MIC_DONE = (1 << 23), 4240 IWM_TX_CMD_FLG_DUR = (1 << 25), 4241 IWM_TX_CMD_FLG_FW_DROP = (1 << 26), 4242 IWM_TX_CMD_FLG_EXEC_PAPD = (1 << 27), 4243 IWM_TX_CMD_FLG_PAPD_TYPE = (1 << 28), 4244 IWM_TX_CMD_FLG_HCCA_CHUNK = (1 << 31) 4245 }; /* IWM_TX_FLAGS_BITS_API_S_VER_1 */ 4246 4247 /** 4248 * enum iwm_tx_pm_timeouts - pm timeout values in TX command 4249 * @IWM_PM_FRAME_NONE: no need to suspend sleep mode 4250 * @IWM_PM_FRAME_MGMT: fw suspend sleep mode for 100TU 4251 * @IWM_PM_FRAME_ASSOC: fw suspend sleep mode for 10sec 4252 */ 4253 enum iwm_tx_pm_timeouts { 4254 IWM_PM_FRAME_NONE = 0, 4255 IWM_PM_FRAME_MGMT = 2, 4256 IWM_PM_FRAME_ASSOC = 3, 4257 }; 4258 4259 /* 4260 * TX command security control 4261 */ 4262 #define IWM_TX_CMD_SEC_WEP 0x01 4263 #define IWM_TX_CMD_SEC_CCM 0x02 4264 #define IWM_TX_CMD_SEC_TKIP 0x03 4265 #define IWM_TX_CMD_SEC_EXT 0x04 4266 #define IWM_TX_CMD_SEC_MSK 0x07 4267 #define IWM_TX_CMD_SEC_WEP_KEY_IDX_POS 6 4268 #define IWM_TX_CMD_SEC_WEP_KEY_IDX_MSK 0xc0 4269 #define IWM_TX_CMD_SEC_KEY128 0x08 4270 4271 /* TODO: how does these values are OK with only 16 bit variable??? */ 4272 /* 4273 * TX command next frame info 4274 * 4275 * bits 0:2 - security control (IWM_TX_CMD_SEC_*) 4276 * bit 3 - immediate ACK required 4277 * bit 4 - rate is taken from STA table 4278 * bit 5 - frame belongs to BA stream 4279 * bit 6 - immediate BA response expected 4280 * bit 7 - unused 4281 * bits 8:15 - Station ID 4282 * bits 16:31 - rate 4283 */ 4284 #define IWM_TX_CMD_NEXT_FRAME_ACK_MSK (0x8) 4285 #define IWM_TX_CMD_NEXT_FRAME_STA_RATE_MSK (0x10) 4286 #define IWM_TX_CMD_NEXT_FRAME_BA_MSK (0x20) 4287 #define IWM_TX_CMD_NEXT_FRAME_IMM_BA_RSP_MSK (0x40) 4288 #define IWM_TX_CMD_NEXT_FRAME_FLAGS_MSK (0xf8) 4289 #define IWM_TX_CMD_NEXT_FRAME_STA_ID_MSK (0xff00) 4290 #define IWM_TX_CMD_NEXT_FRAME_STA_ID_POS (8) 4291 #define IWM_TX_CMD_NEXT_FRAME_RATE_MSK (0xffff0000) 4292 #define IWM_TX_CMD_NEXT_FRAME_RATE_POS (16) 4293 4294 /* 4295 * TX command Frame life time in us - to be written in pm_frame_timeout 4296 */ 4297 #define IWM_TX_CMD_LIFE_TIME_INFINITE 0xFFFFFFFF 4298 #define IWM_TX_CMD_LIFE_TIME_DEFAULT 2000000 /* 2000 ms*/ 4299 #define IWM_TX_CMD_LIFE_TIME_PROBE_RESP 40000 /* 40 ms */ 4300 #define IWM_TX_CMD_LIFE_TIME_EXPIRED_FRAME 0 4301 4302 /* 4303 * TID for non QoS frames - to be written in tid_tspec 4304 */ 4305 #define IWM_TID_NON_QOS IWM_MAX_TID_COUNT 4306 4307 /* 4308 * Limits on the retransmissions - to be written in {data,rts}_retry_limit 4309 */ 4310 #define IWM_DEFAULT_TX_RETRY 15 4311 #define IWM_MGMT_DFAULT_RETRY_LIMIT 3 4312 #define IWM_RTS_DFAULT_RETRY_LIMIT 60 4313 #define IWM_BAR_DFAULT_RETRY_LIMIT 60 4314 #define IWM_LOW_RETRY_LIMIT 7 4315 4316 /* TODO: complete documentation for try_cnt and btkill_cnt */ 4317 /** 4318 * struct iwm_tx_cmd - TX command struct to FW 4319 * ( IWM_TX_CMD = 0x1c ) 4320 * @len: in bytes of the payload, see below for details 4321 * @next_frame_len: same as len, but for next frame (0 if not applicable) 4322 * Used for fragmentation and bursting, but not in 11n aggregation. 4323 * @tx_flags: combination of IWM_TX_CMD_FLG_* 4324 * @rate_n_flags: rate for *all* Tx attempts, if IWM_TX_CMD_FLG_STA_RATE_MSK is 4325 * cleared. Combination of IWM_RATE_MCS_* 4326 * @sta_id: index of destination station in FW station table 4327 * @sec_ctl: security control, IWM_TX_CMD_SEC_* 4328 * @initial_rate_index: index into the rate table for initial TX attempt. 4329 * Applied if IWM_TX_CMD_FLG_STA_RATE_MSK is set, normally 0 for data frames. 4330 * @key: security key 4331 * @next_frame_flags: IWM_TX_CMD_SEC_* and IWM_TX_CMD_NEXT_FRAME_* 4332 * @life_time: frame life time (usecs??) 4333 * @dram_lsb_ptr: Physical address of scratch area in the command (try_cnt + 4334 * btkill_cnd + reserved), first 32 bits. "0" disables usage. 4335 * @dram_msb_ptr: upper bits of the scratch physical address 4336 * @rts_retry_limit: max attempts for RTS 4337 * @data_retry_limit: max attempts to send the data packet 4338 * @tid_spec: TID/tspec 4339 * @pm_frame_timeout: PM TX frame timeout 4340 * @driver_txop: duration od EDCA TXOP, in 32-usec units. Set this if not 4341 * specified by HCCA protocol 4342 * 4343 * The byte count (both len and next_frame_len) includes MAC header 4344 * (24/26/30/32 bytes) 4345 * + 2 bytes pad if 26/30 header size 4346 * + 8 byte IV for CCM or TKIP (not used for WEP) 4347 * + Data payload 4348 * + 8-byte MIC (not used for CCM/WEP) 4349 * It does not include post-MAC padding, i.e., 4350 * MIC (CCM) 8 bytes, ICV (WEP/TKIP/CKIP) 4 bytes, CRC 4 bytes. 4351 * Range of len: 14-2342 bytes. 4352 * 4353 * After the struct fields the MAC header is placed, plus any padding, 4354 * and then the actial payload. 4355 */ 4356 struct iwm_tx_cmd { 4357 uint16_t len; 4358 uint16_t next_frame_len; 4359 uint32_t tx_flags; 4360 struct { 4361 uint8_t try_cnt; 4362 uint8_t btkill_cnt; 4363 uint16_t reserved; 4364 } scratch; /* DRAM_SCRATCH_API_U_VER_1 */ 4365 uint32_t rate_n_flags; 4366 uint8_t sta_id; 4367 uint8_t sec_ctl; 4368 uint8_t initial_rate_index; 4369 uint8_t reserved2; 4370 uint8_t key[16]; 4371 uint16_t next_frame_flags; 4372 uint16_t reserved3; 4373 uint32_t life_time; 4374 uint32_t dram_lsb_ptr; 4375 uint8_t dram_msb_ptr; 4376 uint8_t rts_retry_limit; 4377 uint8_t data_retry_limit; 4378 uint8_t tid_tspec; 4379 uint16_t pm_frame_timeout; 4380 uint16_t driver_txop; 4381 uint8_t payload[0]; 4382 struct ieee80211_frame hdr[0]; 4383 } __packed; /* IWM_TX_CMD_API_S_VER_3 */ 4384 4385 /* 4386 * TX response related data 4387 */ 4388 4389 /* 4390 * enum iwm_tx_status - status that is returned by the fw after attempts to Tx 4391 * @IWM_TX_STATUS_SUCCESS: 4392 * @IWM_TX_STATUS_DIRECT_DONE: 4393 * @IWM_TX_STATUS_POSTPONE_DELAY: 4394 * @IWM_TX_STATUS_POSTPONE_FEW_BYTES: 4395 * @IWM_TX_STATUS_POSTPONE_BT_PRIO: 4396 * @IWM_TX_STATUS_POSTPONE_QUIET_PERIOD: 4397 * @IWM_TX_STATUS_POSTPONE_CALC_TTAK: 4398 * @IWM_TX_STATUS_FAIL_INTERNAL_CROSSED_RETRY: 4399 * @IWM_TX_STATUS_FAIL_SHORT_LIMIT: 4400 * @IWM_TX_STATUS_FAIL_LONG_LIMIT: 4401 * @IWM_TX_STATUS_FAIL_UNDERRUN: 4402 * @IWM_TX_STATUS_FAIL_DRAIN_FLOW: 4403 * @IWM_TX_STATUS_FAIL_RFKILL_FLUSH: 4404 * @IWM_TX_STATUS_FAIL_LIFE_EXPIRE: 4405 * @IWM_TX_STATUS_FAIL_DEST_PS: 4406 * @IWM_TX_STATUS_FAIL_HOST_ABORTED: 4407 * @IWM_TX_STATUS_FAIL_BT_RETRY: 4408 * @IWM_TX_STATUS_FAIL_STA_INVALID: 4409 * @IWM_TX_TATUS_FAIL_FRAG_DROPPED: 4410 * @IWM_TX_STATUS_FAIL_TID_DISABLE: 4411 * @IWM_TX_STATUS_FAIL_FIFO_FLUSHED: 4412 * @IWM_TX_STATUS_FAIL_SMALL_CF_POLL: 4413 * @IWM_TX_STATUS_FAIL_FW_DROP: 4414 * @IWM_TX_STATUS_FAIL_STA_COLOR_MISMATCH: mismatch between color of Tx cmd and 4415 * STA table 4416 * @IWM_TX_FRAME_STATUS_INTERNAL_ABORT: 4417 * @IWM_TX_MODE_MSK: 4418 * @IWM_TX_MODE_NO_BURST: 4419 * @IWM_TX_MODE_IN_BURST_SEQ: 4420 * @IWM_TX_MODE_FIRST_IN_BURST: 4421 * @IWM_TX_QUEUE_NUM_MSK: 4422 * 4423 * Valid only if frame_count =1 4424 * TODO: complete documentation 4425 */ 4426 enum iwm_tx_status { 4427 IWM_TX_STATUS_MSK = 0x000000ff, 4428 IWM_TX_STATUS_SUCCESS = 0x01, 4429 IWM_TX_STATUS_DIRECT_DONE = 0x02, 4430 /* postpone TX */ 4431 IWM_TX_STATUS_POSTPONE_DELAY = 0x40, 4432 IWM_TX_STATUS_POSTPONE_FEW_BYTES = 0x41, 4433 IWM_TX_STATUS_POSTPONE_BT_PRIO = 0x42, 4434 IWM_TX_STATUS_POSTPONE_QUIET_PERIOD = 0x43, 4435 IWM_TX_STATUS_POSTPONE_CALC_TTAK = 0x44, 4436 /* abort TX */ 4437 IWM_TX_STATUS_FAIL_INTERNAL_CROSSED_RETRY = 0x81, 4438 IWM_TX_STATUS_FAIL_SHORT_LIMIT = 0x82, 4439 IWM_TX_STATUS_FAIL_LONG_LIMIT = 0x83, 4440 IWM_TX_STATUS_FAIL_UNDERRUN = 0x84, 4441 IWM_TX_STATUS_FAIL_DRAIN_FLOW = 0x85, 4442 IWM_TX_STATUS_FAIL_RFKILL_FLUSH = 0x86, 4443 IWM_TX_STATUS_FAIL_LIFE_EXPIRE = 0x87, 4444 IWM_TX_STATUS_FAIL_DEST_PS = 0x88, 4445 IWM_TX_STATUS_FAIL_HOST_ABORTED = 0x89, 4446 IWM_TX_STATUS_FAIL_BT_RETRY = 0x8a, 4447 IWM_TX_STATUS_FAIL_STA_INVALID = 0x8b, 4448 IWM_TX_STATUS_FAIL_FRAG_DROPPED = 0x8c, 4449 IWM_TX_STATUS_FAIL_TID_DISABLE = 0x8d, 4450 IWM_TX_STATUS_FAIL_FIFO_FLUSHED = 0x8e, 4451 IWM_TX_STATUS_FAIL_SMALL_CF_POLL = 0x8f, 4452 IWM_TX_STATUS_FAIL_FW_DROP = 0x90, 4453 IWM_TX_STATUS_FAIL_STA_COLOR_MISMATCH = 0x91, 4454 IWM_TX_STATUS_INTERNAL_ABORT = 0x92, 4455 IWM_TX_MODE_MSK = 0x00000f00, 4456 IWM_TX_MODE_NO_BURST = 0x00000000, 4457 IWM_TX_MODE_IN_BURST_SEQ = 0x00000100, 4458 IWM_TX_MODE_FIRST_IN_BURST = 0x00000200, 4459 IWM_TX_QUEUE_NUM_MSK = 0x0001f000, 4460 IWM_TX_NARROW_BW_MSK = 0x00060000, 4461 IWM_TX_NARROW_BW_1DIV2 = 0x00020000, 4462 IWM_TX_NARROW_BW_1DIV4 = 0x00040000, 4463 IWM_TX_NARROW_BW_1DIV8 = 0x00060000, 4464 }; 4465 4466 /* 4467 * enum iwm_tx_agg_status - TX aggregation status 4468 * @IWM_AGG_TX_STATE_STATUS_MSK: 4469 * @IWM_AGG_TX_STATE_TRANSMITTED: 4470 * @IWM_AGG_TX_STATE_UNDERRUN: 4471 * @IWM_AGG_TX_STATE_BT_PRIO: 4472 * @IWM_AGG_TX_STATE_FEW_BYTES: 4473 * @IWM_AGG_TX_STATE_ABORT: 4474 * @IWM_AGG_TX_STATE_LAST_SENT_TTL: 4475 * @IWM_AGG_TX_STATE_LAST_SENT_TRY_CNT: 4476 * @IWM_AGG_TX_STATE_LAST_SENT_BT_KILL: 4477 * @IWM_AGG_TX_STATE_SCD_QUERY: 4478 * @IWM_AGG_TX_STATE_TEST_BAD_CRC32: 4479 * @IWM_AGG_TX_STATE_RESPONSE: 4480 * @IWM_AGG_TX_STATE_DUMP_TX: 4481 * @IWM_AGG_TX_STATE_DELAY_TX: 4482 * @IWM_AGG_TX_STATE_TRY_CNT_MSK: Retry count for 1st frame in aggregation (retries 4483 * occur if tx failed for this frame when it was a member of a previous 4484 * aggregation block). If rate scaling is used, retry count indicates the 4485 * rate table entry used for all frames in the new agg. 4486 *@ IWM_AGG_TX_STATE_SEQ_NUM_MSK: Command ID and sequence number of Tx command for 4487 * this frame 4488 * 4489 * TODO: complete documentation 4490 */ 4491 enum iwm_tx_agg_status { 4492 IWM_AGG_TX_STATE_STATUS_MSK = 0x00fff, 4493 IWM_AGG_TX_STATE_TRANSMITTED = 0x000, 4494 IWM_AGG_TX_STATE_UNDERRUN = 0x001, 4495 IWM_AGG_TX_STATE_BT_PRIO = 0x002, 4496 IWM_AGG_TX_STATE_FEW_BYTES = 0x004, 4497 IWM_AGG_TX_STATE_ABORT = 0x008, 4498 IWM_AGG_TX_STATE_LAST_SENT_TTL = 0x010, 4499 IWM_AGG_TX_STATE_LAST_SENT_TRY_CNT = 0x020, 4500 IWM_AGG_TX_STATE_LAST_SENT_BT_KILL = 0x040, 4501 IWM_AGG_TX_STATE_SCD_QUERY = 0x080, 4502 IWM_AGG_TX_STATE_TEST_BAD_CRC32 = 0x0100, 4503 IWM_AGG_TX_STATE_RESPONSE = 0x1ff, 4504 IWM_AGG_TX_STATE_DUMP_TX = 0x200, 4505 IWM_AGG_TX_STATE_DELAY_TX = 0x400, 4506 IWM_AGG_TX_STATE_TRY_CNT_POS = 12, 4507 IWM_AGG_TX_STATE_TRY_CNT_MSK = 0xf << IWM_AGG_TX_STATE_TRY_CNT_POS, 4508 }; 4509 4510 #define IWM_AGG_TX_STATE_LAST_SENT_MSK (IWM_AGG_TX_STATE_LAST_SENT_TTL| \ 4511 IWM_AGG_TX_STATE_LAST_SENT_TRY_CNT| \ 4512 IWM_AGG_TX_STATE_LAST_SENT_BT_KILL) 4513 4514 /* 4515 * The mask below describes a status where we are absolutely sure that the MPDU 4516 * wasn't sent. For BA/Underrun we cannot be that sure. All we know that we've 4517 * written the bytes to the TXE, but we know nothing about what the DSP did. 4518 */ 4519 #define IWM_AGG_TX_STAT_FRAME_NOT_SENT (IWM_AGG_TX_STATE_FEW_BYTES | \ 4520 IWM_AGG_TX_STATE_ABORT | \ 4521 IWM_AGG_TX_STATE_SCD_QUERY) 4522 4523 /* 4524 * IWM_REPLY_TX = 0x1c (response) 4525 * 4526 * This response may be in one of two slightly different formats, indicated 4527 * by the frame_count field: 4528 * 4529 * 1) No aggregation (frame_count == 1). This reports Tx results for a single 4530 * frame. Multiple attempts, at various bit rates, may have been made for 4531 * this frame. 4532 * 4533 * 2) Aggregation (frame_count > 1). This reports Tx results for two or more 4534 * frames that used block-acknowledge. All frames were transmitted at 4535 * same rate. Rate scaling may have been used if first frame in this new 4536 * agg block failed in previous agg block(s). 4537 * 4538 * Note that, for aggregation, ACK (block-ack) status is not delivered 4539 * here; block-ack has not been received by the time the device records 4540 * this status. 4541 * This status relates to reasons the tx might have been blocked or aborted 4542 * within the device, rather than whether it was received successfully by 4543 * the destination station. 4544 */ 4545 4546 /** 4547 * struct iwm_agg_tx_status - per packet TX aggregation status 4548 * @status: enum iwm_tx_agg_status 4549 * @sequence: Sequence # for this frame's Tx cmd (not SSN!) 4550 */ 4551 struct iwm_agg_tx_status { 4552 uint16_t status; 4553 uint16_t sequence; 4554 } __packed; 4555 4556 /* 4557 * definitions for initial rate index field 4558 * bits [3:0] initial rate index 4559 * bits [6:4] rate table color, used for the initial rate 4560 * bit-7 invalid rate indication 4561 */ 4562 #define IWM_TX_RES_INIT_RATE_INDEX_MSK 0x0f 4563 #define IWM_TX_RES_RATE_TABLE_COLOR_MSK 0x70 4564 #define IWM_TX_RES_INV_RATE_INDEX_MSK 0x80 4565 4566 #define IWM_MVM_TX_RES_GET_TID(_ra_tid) ((_ra_tid) & 0x0f) 4567 #define IWM_MVM_TX_RES_GET_RA(_ra_tid) ((_ra_tid) >> 4) 4568 4569 /** 4570 * struct iwm_mvm_tx_resp - notifies that fw is TXing a packet 4571 * ( IWM_REPLY_TX = 0x1c ) 4572 * @frame_count: 1 no aggregation, >1 aggregation 4573 * @bt_kill_count: num of times blocked by bluetooth (unused for agg) 4574 * @failure_rts: num of failures due to unsuccessful RTS 4575 * @failure_frame: num failures due to no ACK (unused for agg) 4576 * @initial_rate: for non-agg: rate of the successful Tx. For agg: rate of the 4577 * Tx of all the batch. IWM_RATE_MCS_* 4578 * @wireless_media_time: for non-agg: RTS + CTS + frame tx attempts time + ACK. 4579 * for agg: RTS + CTS + aggregation tx time + block-ack time. 4580 * in usec. 4581 * @pa_status: tx power info 4582 * @pa_integ_res_a: tx power info 4583 * @pa_integ_res_b: tx power info 4584 * @pa_integ_res_c: tx power info 4585 * @measurement_req_id: tx power info 4586 * @tfd_info: TFD information set by the FH 4587 * @seq_ctl: sequence control from the Tx cmd 4588 * @byte_cnt: byte count from the Tx cmd 4589 * @tlc_info: TLC rate info 4590 * @ra_tid: bits [3:0] = ra, bits [7:4] = tid 4591 * @frame_ctrl: frame control 4592 * @status: for non-agg: frame status IWM_TX_STATUS_* 4593 * for agg: status of 1st frame, IWM_AGG_TX_STATE_*; other frame status fields 4594 * follow this one, up to frame_count. 4595 * 4596 * After the array of statuses comes the SSN of the SCD. Look at 4597 * %iwm_mvm_get_scd_ssn for more details. 4598 */ 4599 struct iwm_mvm_tx_resp { 4600 uint8_t frame_count; 4601 uint8_t bt_kill_count; 4602 uint8_t failure_rts; 4603 uint8_t failure_frame; 4604 uint32_t initial_rate; 4605 uint16_t wireless_media_time; 4606 4607 uint8_t pa_status; 4608 uint8_t pa_integ_res_a[3]; 4609 uint8_t pa_integ_res_b[3]; 4610 uint8_t pa_integ_res_c[3]; 4611 uint16_t measurement_req_id; 4612 uint16_t reserved; 4613 4614 uint32_t tfd_info; 4615 uint16_t seq_ctl; 4616 uint16_t byte_cnt; 4617 uint8_t tlc_info; 4618 uint8_t ra_tid; 4619 uint16_t frame_ctrl; 4620 4621 struct iwm_agg_tx_status status; 4622 } __packed; /* IWM_TX_RSP_API_S_VER_3 */ 4623 4624 /** 4625 * struct iwm_mvm_ba_notif - notifies about reception of BA 4626 * ( IWM_BA_NOTIF = 0xc5 ) 4627 * @sta_addr_lo32: lower 32 bits of the MAC address 4628 * @sta_addr_hi16: upper 16 bits of the MAC address 4629 * @sta_id: Index of recipient (BA-sending) station in fw's station table 4630 * @tid: tid of the session 4631 * @seq_ctl: 4632 * @bitmap: the bitmap of the BA notification as seen in the air 4633 * @scd_flow: the tx queue this BA relates to 4634 * @scd_ssn: the index of the last contiguously sent packet 4635 * @txed: number of Txed frames in this batch 4636 * @txed_2_done: number of Acked frames in this batch 4637 */ 4638 struct iwm_mvm_ba_notif { 4639 uint32_t sta_addr_lo32; 4640 uint16_t sta_addr_hi16; 4641 uint16_t reserved; 4642 4643 uint8_t sta_id; 4644 uint8_t tid; 4645 uint16_t seq_ctl; 4646 uint64_t bitmap; 4647 uint16_t scd_flow; 4648 uint16_t scd_ssn; 4649 uint8_t txed; 4650 uint8_t txed_2_done; 4651 uint16_t reserved1; 4652 } __packed; 4653 4654 /* 4655 * struct iwm_mac_beacon_cmd - beacon template command 4656 * @tx: the tx commands associated with the beacon frame 4657 * @template_id: currently equal to the mac context id of the coresponding 4658 * mac. 4659 * @tim_idx: the offset of the tim IE in the beacon 4660 * @tim_size: the length of the tim IE 4661 * @frame: the template of the beacon frame 4662 */ 4663 struct iwm_mac_beacon_cmd { 4664 struct iwm_tx_cmd tx; 4665 uint32_t template_id; 4666 uint32_t tim_idx; 4667 uint32_t tim_size; 4668 struct ieee80211_frame frame[0]; 4669 } __packed; 4670 4671 struct iwm_beacon_notif { 4672 struct iwm_mvm_tx_resp beacon_notify_hdr; 4673 uint64_t tsf; 4674 uint32_t ibss_mgr_status; 4675 } __packed; 4676 4677 /** 4678 * enum iwm_dump_control - dump (flush) control flags 4679 * @IWM_DUMP_TX_FIFO_FLUSH: Dump MSDUs until the FIFO is empty 4680 * and the TFD queues are empty. 4681 */ 4682 enum iwm_dump_control { 4683 IWM_DUMP_TX_FIFO_FLUSH = (1 << 1), 4684 }; 4685 4686 /** 4687 * struct iwm_tx_path_flush_cmd -- queue/FIFO flush command 4688 * @queues_ctl: bitmap of queues to flush 4689 * @flush_ctl: control flags 4690 * @reserved: reserved 4691 */ 4692 struct iwm_tx_path_flush_cmd { 4693 uint32_t queues_ctl; 4694 uint16_t flush_ctl; 4695 uint16_t reserved; 4696 } __packed; /* IWM_TX_PATH_FLUSH_CMD_API_S_VER_1 */ 4697 4698 /** 4699 * iwm_mvm_get_scd_ssn - returns the SSN of the SCD 4700 * @tx_resp: the Tx response from the fw (agg or non-agg) 4701 * 4702 * When the fw sends an AMPDU, it fetches the MPDUs one after the other. Since 4703 * it can't know that everything will go well until the end of the AMPDU, it 4704 * can't know in advance the number of MPDUs that will be sent in the current 4705 * batch. This is why it writes the agg Tx response while it fetches the MPDUs. 4706 * Hence, it can't know in advance what the SSN of the SCD will be at the end 4707 * of the batch. This is why the SSN of the SCD is written at the end of the 4708 * whole struct at a variable offset. This function knows how to cope with the 4709 * variable offset and returns the SSN of the SCD. 4710 */ 4711 static inline uint32_t iwm_mvm_get_scd_ssn(struct iwm_mvm_tx_resp *tx_resp) 4712 { 4713 return le32_to_cpup((uint32_t *)&tx_resp->status + 4714 tx_resp->frame_count) & 0xfff; 4715 } 4716 4717 /* 4718 * END mvm/fw-api-tx.h 4719 */ 4720 4721 /* 4722 * BEGIN mvm/fw-api-scan.h 4723 */ 4724 4725 /** 4726 * struct iwm_scd_txq_cfg_cmd - New txq hw scheduler config command 4727 * @token: 4728 * @sta_id: station id 4729 * @tid: 4730 * @scd_queue: scheduler queue to confiug 4731 * @enable: 1 queue enable, 0 queue disable 4732 * @aggregate: 1 aggregated queue, 0 otherwise 4733 * @tx_fifo: %enum iwm_mvm_tx_fifo 4734 * @window: BA window size 4735 * @ssn: SSN for the BA agreement 4736 */ 4737 struct iwm_scd_txq_cfg_cmd { 4738 uint8_t token; 4739 uint8_t sta_id; 4740 uint8_t tid; 4741 uint8_t scd_queue; 4742 uint8_t enable; 4743 uint8_t aggregate; 4744 uint8_t tx_fifo; 4745 uint8_t window; 4746 uint16_t ssn; 4747 uint16_t reserved; 4748 } __packed; /* SCD_QUEUE_CFG_CMD_API_S_VER_1 */ 4749 4750 /** 4751 * struct iwm_scd_txq_cfg_rsp 4752 * @token: taken from the command 4753 * @sta_id: station id from the command 4754 * @tid: tid from the command 4755 * @scd_queue: scd_queue from the command 4756 */ 4757 struct iwm_scd_txq_cfg_rsp { 4758 uint8_t token; 4759 uint8_t sta_id; 4760 uint8_t tid; 4761 uint8_t scd_queue; 4762 } __packed; /* SCD_QUEUE_CFG_RSP_API_S_VER_1 */ 4763 4764 4765 /* Scan Commands, Responses, Notifications */ 4766 4767 /* Masks for iwm_scan_channel.type flags */ 4768 #define IWM_SCAN_CHANNEL_TYPE_ACTIVE (1 << 0) 4769 #define IWM_SCAN_CHANNEL_NARROW_BAND (1 << 22) 4770 4771 /* Max number of IEs for direct SSID scans in a command */ 4772 #define IWM_PROBE_OPTION_MAX 20 4773 4774 /** 4775 * struct iwm_scan_channel - entry in IWM_REPLY_SCAN_CMD channel table 4776 * @channel: band is selected by iwm_scan_cmd "flags" field 4777 * @tx_gain: gain for analog radio 4778 * @dsp_atten: gain for DSP 4779 * @active_dwell: dwell time for active scan in TU, typically 5-50 4780 * @passive_dwell: dwell time for passive scan in TU, typically 20-500 4781 * @type: type is broken down to these bits: 4782 * bit 0: 0 = passive, 1 = active 4783 * bits 1-20: SSID direct bit map. If any of these bits is set then 4784 * the corresponding SSID IE is transmitted in probe request 4785 * (bit i adds IE in position i to the probe request) 4786 * bit 22: channel width, 0 = regular, 1 = TGj narrow channel 4787 * 4788 * @iteration_count: 4789 * @iteration_interval: 4790 * This struct is used once for each channel in the scan list. 4791 * Each channel can independently select: 4792 * 1) SSID for directed active scans 4793 * 2) Txpower setting (for rate specified within Tx command) 4794 * 3) How long to stay on-channel (behavior may be modified by quiet_time, 4795 * quiet_plcp_th, good_CRC_th) 4796 * 4797 * To avoid uCode errors, make sure the following are true (see comments 4798 * under struct iwm_scan_cmd about max_out_time and quiet_time): 4799 * 1) If using passive_dwell (i.e. passive_dwell != 0): 4800 * active_dwell <= passive_dwell (< max_out_time if max_out_time != 0) 4801 * 2) quiet_time <= active_dwell 4802 * 3) If restricting off-channel time (i.e. max_out_time !=0): 4803 * passive_dwell < max_out_time 4804 * active_dwell < max_out_time 4805 */ 4806 struct iwm_scan_channel { 4807 uint32_t type; 4808 uint16_t channel; 4809 uint16_t iteration_count; 4810 uint32_t iteration_interval; 4811 uint16_t active_dwell; 4812 uint16_t passive_dwell; 4813 } __packed; /* IWM_SCAN_CHANNEL_CONTROL_API_S_VER_1 */ 4814 4815 /** 4816 * struct iwm_ssid_ie - directed scan network information element 4817 * 4818 * Up to 20 of these may appear in IWM_REPLY_SCAN_CMD, 4819 * selected by "type" bit field in struct iwm_scan_channel; 4820 * each channel may select different ssids from among the 20 entries. 4821 * SSID IEs get transmitted in reverse order of entry. 4822 */ 4823 struct iwm_ssid_ie { 4824 uint8_t id; 4825 uint8_t len; 4826 uint8_t ssid[IEEE80211_NWID_LEN]; 4827 } __packed; /* IWM_SCAN_DIRECT_SSID_IE_API_S_VER_1 */ 4828 4829 /* scan offload */ 4830 #define IWM_MAX_SCAN_CHANNELS 40 4831 #define IWM_SCAN_MAX_BLACKLIST_LEN 64 4832 #define IWM_SCAN_SHORT_BLACKLIST_LEN 16 4833 #define IWM_SCAN_MAX_PROFILES 11 4834 #define IWM_SCAN_OFFLOAD_PROBE_REQ_SIZE 512 4835 4836 /* Default watchdog (in MS) for scheduled scan iteration */ 4837 #define IWM_SCHED_SCAN_WATCHDOG cpu_to_le16(15000) 4838 4839 #define IWM_GOOD_CRC_TH_DEFAULT cpu_to_le16(1) 4840 #define IWM_CAN_ABORT_STATUS 1 4841 4842 #define IWM_FULL_SCAN_MULTIPLIER 5 4843 #define IWM_FAST_SCHED_SCAN_ITERATIONS 3 4844 #define IWM_MAX_SCHED_SCAN_PLANS 2 4845 4846 /** 4847 * iwm_scan_flags - masks for scan command flags 4848 *@IWM_SCAN_FLAGS_PERIODIC_SCAN: 4849 *@IWM_SCAN_FLAGS_P2P_PUBLIC_ACTION_FRAME_TX: 4850 *@IWM_SCAN_FLAGS_DELAYED_SCAN_LOWBAND: 4851 *@IWM_SCAN_FLAGS_DELAYED_SCAN_HIGHBAND: 4852 *@IWM_SCAN_FLAGS_FRAGMENTED_SCAN: 4853 *@IWM_SCAN_FLAGS_PASSIVE2ACTIVE: use active scan on channels that was active 4854 * in the past hour, even if they are marked as passive. 4855 */ 4856 enum iwm_scan_flags { 4857 IWM_SCAN_FLAGS_PERIODIC_SCAN = (1 << 0), 4858 IWM_SCAN_FLAGS_P2P_PUBLIC_ACTION_FRAME_TX = (1 << 1), 4859 IWM_SCAN_FLAGS_DELAYED_SCAN_LOWBAND = (1 << 2), 4860 IWM_SCAN_FLAGS_DELAYED_SCAN_HIGHBAND = (1 << 3), 4861 IWM_SCAN_FLAGS_FRAGMENTED_SCAN = (1 << 4), 4862 IWM_SCAN_FLAGS_PASSIVE2ACTIVE = (1 << 5), 4863 }; 4864 4865 /** 4866 * enum iwm_scan_type - Scan types for scan command 4867 * @IWM_SCAN_TYPE_FORCED: 4868 * @IWM_SCAN_TYPE_BACKGROUND: 4869 * @IWM_SCAN_TYPE_OS: 4870 * @IWM_SCAN_TYPE_ROAMING: 4871 * @IWM_SCAN_TYPE_ACTION: 4872 * @IWM_SCAN_TYPE_DISCOVERY: 4873 * @IWM_SCAN_TYPE_DISCOVERY_FORCED: 4874 */ 4875 enum iwm_scan_type { 4876 IWM_SCAN_TYPE_FORCED = 0, 4877 IWM_SCAN_TYPE_BACKGROUND = 1, 4878 IWM_SCAN_TYPE_OS = 2, 4879 IWM_SCAN_TYPE_ROAMING = 3, 4880 IWM_SCAN_TYPE_ACTION = 4, 4881 IWM_SCAN_TYPE_DISCOVERY = 5, 4882 IWM_SCAN_TYPE_DISCOVERY_FORCED = 6, 4883 }; /* IWM_SCAN_ACTIVITY_TYPE_E_VER_1 */ 4884 4885 /* Maximal number of channels to scan */ 4886 #define IWM_MAX_NUM_SCAN_CHANNELS 0x24 4887 4888 /** 4889 * iwm_scan_schedule_lmac - schedule of scan offload 4890 * @delay: delay between iterations, in seconds. 4891 * @iterations: num of scan iterations 4892 * @full_scan_mul: number of partial scans before each full scan 4893 */ 4894 struct iwm_scan_schedule_lmac { 4895 uint16_t delay; 4896 uint8_t iterations; 4897 uint8_t full_scan_mul; 4898 } __packed; /* SCAN_SCHEDULE_API_S */ 4899 4900 /** 4901 * iwm_scan_req_tx_cmd - SCAN_REQ_TX_CMD_API_S 4902 * @tx_flags: combination of TX_CMD_FLG_* 4903 * @rate_n_flags: rate for *all* Tx attempts, if TX_CMD_FLG_STA_RATE_MSK is 4904 * cleared. Combination of RATE_MCS_* 4905 * @sta_id: index of destination station in FW station table 4906 * @reserved: for alignment and future use 4907 */ 4908 struct iwm_scan_req_tx_cmd { 4909 uint32_t tx_flags; 4910 uint32_t rate_n_flags; 4911 uint8_t sta_id; 4912 uint8_t reserved[3]; 4913 } __packed; 4914 4915 enum iwm_scan_channel_flags_lmac { 4916 IWM_UNIFIED_SCAN_CHANNEL_FULL = (1 << 27), 4917 IWM_UNIFIED_SCAN_CHANNEL_PARTIAL = (1 << 28), 4918 }; 4919 4920 /** 4921 * iwm_scan_channel_cfg_lmac - SCAN_CHANNEL_CFG_S_VER2 4922 * @flags: bits 1-20: directed scan to i'th ssid 4923 * other bits &enum iwm_scan_channel_flags_lmac 4924 * @channel_number: channel number 1-13 etc 4925 * @iter_count: scan iteration on this channel 4926 * @iter_interval: interval in seconds between iterations on one channel 4927 */ 4928 struct iwm_scan_channel_cfg_lmac { 4929 uint32_t flags; 4930 uint16_t channel_num; 4931 uint16_t iter_count; 4932 uint32_t iter_interval; 4933 } __packed; 4934 4935 /* 4936 * iwm_scan_probe_segment - PROBE_SEGMENT_API_S_VER_1 4937 * @offset: offset in the data block 4938 * @len: length of the segment 4939 */ 4940 struct iwm_scan_probe_segment { 4941 uint16_t offset; 4942 uint16_t len; 4943 } __packed; 4944 4945 /* iwm_scan_probe_req - PROBE_REQUEST_FRAME_API_S_VER_2 4946 * @mac_header: first (and common) part of the probe 4947 * @band_data: band specific data 4948 * @common_data: last (and common) part of the probe 4949 * @buf: raw data block 4950 */ 4951 struct iwm_scan_probe_req { 4952 struct iwm_scan_probe_segment mac_header; 4953 struct iwm_scan_probe_segment band_data[2]; 4954 struct iwm_scan_probe_segment common_data; 4955 uint8_t buf[IWM_SCAN_OFFLOAD_PROBE_REQ_SIZE]; 4956 } __packed; 4957 4958 enum iwm_scan_channel_flags { 4959 IWM_SCAN_CHANNEL_FLAG_EBS = (1 << 0), 4960 IWM_SCAN_CHANNEL_FLAG_EBS_ACCURATE = (1 << 1), 4961 IWM_SCAN_CHANNEL_FLAG_CACHE_ADD = (1 << 2), 4962 }; 4963 4964 /* iwm_scan_channel_opt - CHANNEL_OPTIMIZATION_API_S 4965 * @flags: enum iwm_scan_channel_flags 4966 * @non_ebs_ratio: defines the ratio of number of scan iterations where EBS is 4967 * involved. 4968 * 1 - EBS is disabled. 4969 * 2 - every second scan will be full scan(and so on). 4970 */ 4971 struct iwm_scan_channel_opt { 4972 uint16_t flags; 4973 uint16_t non_ebs_ratio; 4974 } __packed; 4975 4976 /** 4977 * iwm_mvm_lmac_scan_flags 4978 * @IWM_MVM_LMAC_SCAN_FLAG_PASS_ALL: pass all beacons and probe responses 4979 * without filtering. 4980 * @IWM_MVM_LMAC_SCAN_FLAG_PASSIVE: force passive scan on all channels 4981 * @IWM_MVM_LMAC_SCAN_FLAG_PRE_CONNECTION: single channel scan 4982 * @IWM_MVM_LMAC_SCAN_FLAG_ITER_COMPLETE: send iteration complete notification 4983 * @IWM_MVM_LMAC_SCAN_FLAG_MULTIPLE_SSIDS multiple SSID matching 4984 * @IWM_MVM_LMAC_SCAN_FLAG_FRAGMENTED: all passive scans will be fragmented 4985 * @IWM_MVM_LMAC_SCAN_FLAGS_RRM_ENABLED: insert WFA vendor-specific TPC report 4986 * and DS parameter set IEs into probe requests. 4987 * @IWM_MVM_LMAC_SCAN_FLAG_EXTENDED_DWELL: use extended dwell time on channels 4988 * 1, 6 and 11. 4989 * @IWM_MVM_LMAC_SCAN_FLAG_MATCH: Send match found notification on matches 4990 */ 4991 enum iwm_mvm_lmac_scan_flags { 4992 IWM_MVM_LMAC_SCAN_FLAG_PASS_ALL = (1 << 0), 4993 IWM_MVM_LMAC_SCAN_FLAG_PASSIVE = (1 << 1), 4994 IWM_MVM_LMAC_SCAN_FLAG_PRE_CONNECTION = (1 << 2), 4995 IWM_MVM_LMAC_SCAN_FLAG_ITER_COMPLETE = (1 << 3), 4996 IWM_MVM_LMAC_SCAN_FLAG_MULTIPLE_SSIDS = (1 << 4), 4997 IWM_MVM_LMAC_SCAN_FLAG_FRAGMENTED = (1 << 5), 4998 IWM_MVM_LMAC_SCAN_FLAGS_RRM_ENABLED = (1 << 6), 4999 IWM_MVM_LMAC_SCAN_FLAG_EXTENDED_DWELL = (1 << 7), 5000 IWM_MVM_LMAC_SCAN_FLAG_MATCH = (1 << 9), 5001 }; 5002 5003 enum iwm_scan_priority { 5004 IWM_SCAN_PRIORITY_LOW, 5005 IWM_SCAN_PRIORITY_MEDIUM, 5006 IWM_SCAN_PRIORITY_HIGH, 5007 }; 5008 5009 /** 5010 * iwm_scan_req_lmac - SCAN_REQUEST_CMD_API_S_VER_1 5011 * @reserved1: for alignment and future use 5012 * @channel_num: num of channels to scan 5013 * @active-dwell: dwell time for active channels 5014 * @passive-dwell: dwell time for passive channels 5015 * @fragmented-dwell: dwell time for fragmented passive scan 5016 * @extended_dwell: dwell time for channels 1, 6 and 11 (in certain cases) 5017 * @reserved2: for alignment and future use 5018 * @rx_chain_selct: PHY_RX_CHAIN_* flags 5019 * @scan_flags: &enum iwm_mvm_lmac_scan_flags 5020 * @max_out_time: max time (in TU) to be out of associated channel 5021 * @suspend_time: pause scan this long (TUs) when returning to service channel 5022 * @flags: RXON flags 5023 * @filter_flags: RXON filter 5024 * @tx_cmd: tx command for active scan; for 2GHz and for 5GHz 5025 * @direct_scan: list of SSIDs for directed active scan 5026 * @scan_prio: enum iwm_scan_priority 5027 * @iter_num: number of scan iterations 5028 * @delay: delay in seconds before first iteration 5029 * @schedule: two scheduling plans. The first one is finite, the second one can 5030 * be infinite. 5031 * @channel_opt: channel optimization options, for full and partial scan 5032 * @data: channel configuration and probe request packet. 5033 */ 5034 struct iwm_scan_req_lmac { 5035 /* SCAN_REQUEST_FIXED_PART_API_S_VER_7 */ 5036 uint32_t reserved1; 5037 uint8_t n_channels; 5038 uint8_t active_dwell; 5039 uint8_t passive_dwell; 5040 uint8_t fragmented_dwell; 5041 uint8_t extended_dwell; 5042 uint8_t reserved2; 5043 uint16_t rx_chain_select; 5044 uint32_t scan_flags; 5045 uint32_t max_out_time; 5046 uint32_t suspend_time; 5047 /* RX_ON_FLAGS_API_S_VER_1 */ 5048 uint32_t flags; 5049 uint32_t filter_flags; 5050 struct iwm_scan_req_tx_cmd tx_cmd[2]; 5051 struct iwm_ssid_ie direct_scan[IWM_PROBE_OPTION_MAX]; 5052 uint32_t scan_prio; 5053 /* SCAN_REQ_PERIODIC_PARAMS_API_S */ 5054 uint32_t iter_num; 5055 uint32_t delay; 5056 struct iwm_scan_schedule_lmac schedule[IWM_MAX_SCHED_SCAN_PLANS]; 5057 struct iwm_scan_channel_opt channel_opt[2]; 5058 uint8_t data[]; 5059 } __packed; 5060 5061 /** 5062 * iwm_scan_offload_complete - PERIODIC_SCAN_COMPLETE_NTF_API_S_VER_2 5063 * @last_schedule_line: last schedule line executed (fast or regular) 5064 * @last_schedule_iteration: last scan iteration executed before scan abort 5065 * @status: enum iwm_scan_offload_complete_status 5066 * @ebs_status: EBS success status &enum iwm_scan_ebs_status 5067 * @time_after_last_iter; time in seconds elapsed after last iteration 5068 */ 5069 struct iwm_periodic_scan_complete { 5070 uint8_t last_schedule_line; 5071 uint8_t last_schedule_iteration; 5072 uint8_t status; 5073 uint8_t ebs_status; 5074 uint32_t time_after_last_iter; 5075 uint32_t reserved; 5076 } __packed; 5077 5078 /* Response to scan request contains only status with one of these values */ 5079 #define IWM_SCAN_RESPONSE_OK 0x1 5080 #define IWM_SCAN_RESPONSE_ERROR 0x2 5081 5082 /* 5083 * IWM_SCAN_ABORT_CMD = 0x81 5084 * When scan abort is requested, the command has no fields except the common 5085 * header. The response contains only a status with one of these values. 5086 */ 5087 #define IWM_SCAN_ABORT_POSSIBLE 0x1 5088 #define IWM_SCAN_ABORT_IGNORED 0x2 /* no pending scans */ 5089 5090 /* TODO: complete documentation */ 5091 #define IWM_SCAN_OWNER_STATUS 0x1 5092 #define IWM_MEASURE_OWNER_STATUS 0x2 5093 5094 /** 5095 * struct iwm_scan_start_notif - notifies start of scan in the device 5096 * ( IWM_SCAN_START_NOTIFICATION = 0x82 ) 5097 * @tsf_low: TSF timer (lower half) in usecs 5098 * @tsf_high: TSF timer (higher half) in usecs 5099 * @beacon_timer: structured as follows: 5100 * bits 0:19 - beacon interval in usecs 5101 * bits 20:23 - reserved (0) 5102 * bits 24:31 - number of beacons 5103 * @channel: which channel is scanned 5104 * @band: 0 for 5.2 GHz, 1 for 2.4 GHz 5105 * @status: one of *_OWNER_STATUS 5106 */ 5107 struct iwm_scan_start_notif { 5108 uint32_t tsf_low; 5109 uint32_t tsf_high; 5110 uint32_t beacon_timer; 5111 uint8_t channel; 5112 uint8_t band; 5113 uint8_t reserved[2]; 5114 uint32_t status; 5115 } __packed; /* IWM_SCAN_START_NTF_API_S_VER_1 */ 5116 5117 /* scan results probe_status first bit indicates success */ 5118 #define IWM_SCAN_PROBE_STATUS_OK 0 5119 #define IWM_SCAN_PROBE_STATUS_TX_FAILED (1 << 0) 5120 /* error statuses combined with TX_FAILED */ 5121 #define IWM_SCAN_PROBE_STATUS_FAIL_TTL (1 << 1) 5122 #define IWM_SCAN_PROBE_STATUS_FAIL_BT (1 << 2) 5123 5124 /* How many statistics are gathered for each channel */ 5125 #define IWM_SCAN_RESULTS_STATISTICS 1 5126 5127 /** 5128 * enum iwm_scan_complete_status - status codes for scan complete notifications 5129 * @IWM_SCAN_COMP_STATUS_OK: scan completed successfully 5130 * @IWM_SCAN_COMP_STATUS_ABORT: scan was aborted by user 5131 * @IWM_SCAN_COMP_STATUS_ERR_SLEEP: sending null sleep packet failed 5132 * @IWM_SCAN_COMP_STATUS_ERR_CHAN_TIMEOUT: timeout before channel is ready 5133 * @IWM_SCAN_COMP_STATUS_ERR_PROBE: sending probe request failed 5134 * @IWM_SCAN_COMP_STATUS_ERR_WAKEUP: sending null wakeup packet failed 5135 * @IWM_SCAN_COMP_STATUS_ERR_ANTENNAS: invalid antennas chosen at scan command 5136 * @IWM_SCAN_COMP_STATUS_ERR_INTERNAL: internal error caused scan abort 5137 * @IWM_SCAN_COMP_STATUS_ERR_COEX: medium was lost ot WiMax 5138 * @IWM_SCAN_COMP_STATUS_P2P_ACTION_OK: P2P public action frame TX was successful 5139 * (not an error!) 5140 * @IWM_SCAN_COMP_STATUS_ITERATION_END: indicates end of one repeatition the driver 5141 * asked for 5142 * @IWM_SCAN_COMP_STATUS_ERR_ALLOC_TE: scan could not allocate time events 5143 */ 5144 enum iwm_scan_complete_status { 5145 IWM_SCAN_COMP_STATUS_OK = 0x1, 5146 IWM_SCAN_COMP_STATUS_ABORT = 0x2, 5147 IWM_SCAN_COMP_STATUS_ERR_SLEEP = 0x3, 5148 IWM_SCAN_COMP_STATUS_ERR_CHAN_TIMEOUT = 0x4, 5149 IWM_SCAN_COMP_STATUS_ERR_PROBE = 0x5, 5150 IWM_SCAN_COMP_STATUS_ERR_WAKEUP = 0x6, 5151 IWM_SCAN_COMP_STATUS_ERR_ANTENNAS = 0x7, 5152 IWM_SCAN_COMP_STATUS_ERR_INTERNAL = 0x8, 5153 IWM_SCAN_COMP_STATUS_ERR_COEX = 0x9, 5154 IWM_SCAN_COMP_STATUS_P2P_ACTION_OK = 0xA, 5155 IWM_SCAN_COMP_STATUS_ITERATION_END = 0x0B, 5156 IWM_SCAN_COMP_STATUS_ERR_ALLOC_TE = 0x0C, 5157 }; 5158 5159 /** 5160 * struct iwm_scan_results_notif - scan results for one channel 5161 * ( IWM_SCAN_RESULTS_NOTIFICATION = 0x83 ) 5162 * @channel: which channel the results are from 5163 * @band: 0 for 5.2 GHz, 1 for 2.4 GHz 5164 * @probe_status: IWM_SCAN_PROBE_STATUS_*, indicates success of probe request 5165 * @num_probe_not_sent: # of request that weren't sent due to not enough time 5166 * @duration: duration spent in channel, in usecs 5167 * @statistics: statistics gathered for this channel 5168 */ 5169 struct iwm_scan_results_notif { 5170 uint8_t channel; 5171 uint8_t band; 5172 uint8_t probe_status; 5173 uint8_t num_probe_not_sent; 5174 uint32_t duration; 5175 uint32_t statistics[IWM_SCAN_RESULTS_STATISTICS]; 5176 } __packed; /* IWM_SCAN_RESULT_NTF_API_S_VER_2 */ 5177 5178 /** 5179 * struct iwm_scan_complete_notif - notifies end of scanning (all channels) 5180 * ( IWM_SCAN_COMPLETE_NOTIFICATION = 0x84 ) 5181 * @scanned_channels: number of channels scanned (and number of valid results) 5182 * @status: one of IWM_SCAN_COMP_STATUS_* 5183 * @bt_status: BT on/off status 5184 * @last_channel: last channel that was scanned 5185 * @tsf_low: TSF timer (lower half) in usecs 5186 * @tsf_high: TSF timer (higher half) in usecs 5187 * @results: all scan results, only "scanned_channels" of them are valid 5188 */ 5189 struct iwm_scan_complete_notif { 5190 uint8_t scanned_channels; 5191 uint8_t status; 5192 uint8_t bt_status; 5193 uint8_t last_channel; 5194 uint32_t tsf_low; 5195 uint32_t tsf_high; 5196 struct iwm_scan_results_notif results[IWM_MAX_NUM_SCAN_CHANNELS]; 5197 } __packed; /* IWM_SCAN_COMPLETE_NTF_API_S_VER_2 */ 5198 5199 enum iwm_scan_framework_client { 5200 IWM_SCAN_CLIENT_SCHED_SCAN = (1 << 0), 5201 IWM_SCAN_CLIENT_NETDETECT = (1 << 1), 5202 IWM_SCAN_CLIENT_ASSET_TRACKING = (1 << 2), 5203 }; 5204 5205 /** 5206 * struct iwm_scan_offload_cmd - IWM_SCAN_REQUEST_FIXED_PART_API_S_VER_6 5207 * @scan_flags: see enum iwm_scan_flags 5208 * @channel_count: channels in channel list 5209 * @quiet_time: dwell time, in milisiconds, on quiet channel 5210 * @quiet_plcp_th: quiet channel num of packets threshold 5211 * @good_CRC_th: passive to active promotion threshold 5212 * @rx_chain: RXON rx chain. 5213 * @max_out_time: max uSec to be out of assoceated channel 5214 * @suspend_time: pause scan this long when returning to service channel 5215 * @flags: RXON flags 5216 * @filter_flags: RXONfilter 5217 * @tx_cmd: tx command for active scan; for 2GHz and for 5GHz. 5218 * @direct_scan: list of SSIDs for directed active scan 5219 * @scan_type: see enum iwm_scan_type. 5220 * @rep_count: repetition count for each scheduled scan iteration. 5221 */ 5222 struct iwm_scan_offload_cmd { 5223 uint16_t len; 5224 uint8_t scan_flags; 5225 uint8_t channel_count; 5226 uint16_t quiet_time; 5227 uint16_t quiet_plcp_th; 5228 uint16_t good_CRC_th; 5229 uint16_t rx_chain; 5230 uint32_t max_out_time; 5231 uint32_t suspend_time; 5232 /* IWM_RX_ON_FLAGS_API_S_VER_1 */ 5233 uint32_t flags; 5234 uint32_t filter_flags; 5235 struct iwm_tx_cmd tx_cmd[2]; 5236 /* IWM_SCAN_DIRECT_SSID_IE_API_S_VER_1 */ 5237 struct iwm_ssid_ie direct_scan[IWM_PROBE_OPTION_MAX]; 5238 uint32_t scan_type; 5239 uint32_t rep_count; 5240 } __packed; 5241 5242 enum iwm_scan_offload_channel_flags { 5243 IWM_SCAN_OFFLOAD_CHANNEL_ACTIVE = (1 << 0), 5244 IWM_SCAN_OFFLOAD_CHANNEL_NARROW = (1 << 22), 5245 IWM_SCAN_OFFLOAD_CHANNEL_FULL = (1 << 24), 5246 IWM_SCAN_OFFLOAD_CHANNEL_PARTIAL = (1 << 25), 5247 }; 5248 5249 /** 5250 * iwm_scan_channel_cfg - IWM_SCAN_CHANNEL_CFG_S 5251 * @type: bitmap - see enum iwm_scan_offload_channel_flags. 5252 * 0: passive (0) or active (1) scan. 5253 * 1-20: directed scan to i'th ssid. 5254 * 22: channel width configuation - 1 for narrow. 5255 * 24: full scan. 5256 * 25: partial scan. 5257 * @channel_number: channel number 1-13 etc. 5258 * @iter_count: repetition count for the channel. 5259 * @iter_interval: interval between two innteration on one channel. 5260 * @dwell_time: entry 0 - active scan, entry 1 - passive scan. 5261 */ 5262 struct iwm_scan_channel_cfg { 5263 uint32_t type[IWM_MAX_SCAN_CHANNELS]; 5264 uint16_t channel_number[IWM_MAX_SCAN_CHANNELS]; 5265 uint16_t iter_count[IWM_MAX_SCAN_CHANNELS]; 5266 uint32_t iter_interval[IWM_MAX_SCAN_CHANNELS]; 5267 uint8_t dwell_time[IWM_MAX_SCAN_CHANNELS][2]; 5268 } __packed; 5269 5270 /** 5271 * iwm_scan_offload_cfg - IWM_SCAN_OFFLOAD_CONFIG_API_S 5272 * @scan_cmd: scan command fixed part 5273 * @channel_cfg: scan channel configuration 5274 * @data: probe request frames (one per band) 5275 */ 5276 struct iwm_scan_offload_cfg { 5277 struct iwm_scan_offload_cmd scan_cmd; 5278 struct iwm_scan_channel_cfg channel_cfg; 5279 uint8_t data[0]; 5280 } __packed; 5281 5282 /** 5283 * iwm_scan_offload_blacklist - IWM_SCAN_OFFLOAD_BLACKLIST_S 5284 * @ssid: MAC address to filter out 5285 * @reported_rssi: AP rssi reported to the host 5286 * @client_bitmap: clients ignore this entry - enum scan_framework_client 5287 */ 5288 struct iwm_scan_offload_blacklist { 5289 uint8_t ssid[IEEE80211_ADDR_LEN]; 5290 uint8_t reported_rssi; 5291 uint8_t client_bitmap; 5292 } __packed; 5293 5294 enum iwm_scan_offload_network_type { 5295 IWM_NETWORK_TYPE_BSS = 1, 5296 IWM_NETWORK_TYPE_IBSS = 2, 5297 IWM_NETWORK_TYPE_ANY = 3, 5298 }; 5299 5300 enum iwm_scan_offload_band_selection { 5301 IWM_SCAN_OFFLOAD_SELECT_2_4 = 0x4, 5302 IWM_SCAN_OFFLOAD_SELECT_5_2 = 0x8, 5303 IWM_SCAN_OFFLOAD_SELECT_ANY = 0xc, 5304 }; 5305 5306 /** 5307 * iwm_scan_offload_profile - IWM_SCAN_OFFLOAD_PROFILE_S 5308 * @ssid_index: index to ssid list in fixed part 5309 * @unicast_cipher: encryption olgorithm to match - bitmap 5310 * @aut_alg: authentication olgorithm to match - bitmap 5311 * @network_type: enum iwm_scan_offload_network_type 5312 * @band_selection: enum iwm_scan_offload_band_selection 5313 * @client_bitmap: clients waiting for match - enum scan_framework_client 5314 */ 5315 struct iwm_scan_offload_profile { 5316 uint8_t ssid_index; 5317 uint8_t unicast_cipher; 5318 uint8_t auth_alg; 5319 uint8_t network_type; 5320 uint8_t band_selection; 5321 uint8_t client_bitmap; 5322 uint8_t reserved[2]; 5323 } __packed; 5324 5325 /** 5326 * iwm_scan_offload_profile_cfg - IWM_SCAN_OFFLOAD_PROFILES_CFG_API_S_VER_1 5327 * @blaclist: AP list to filter off from scan results 5328 * @profiles: profiles to search for match 5329 * @blacklist_len: length of blacklist 5330 * @num_profiles: num of profiles in the list 5331 * @match_notify: clients waiting for match found notification 5332 * @pass_match: clients waiting for the results 5333 * @active_clients: active clients bitmap - enum scan_framework_client 5334 * @any_beacon_notify: clients waiting for match notification without match 5335 */ 5336 struct iwm_scan_offload_profile_cfg { 5337 struct iwm_scan_offload_profile profiles[IWM_SCAN_MAX_PROFILES]; 5338 uint8_t blacklist_len; 5339 uint8_t num_profiles; 5340 uint8_t match_notify; 5341 uint8_t pass_match; 5342 uint8_t active_clients; 5343 uint8_t any_beacon_notify; 5344 uint8_t reserved[2]; 5345 } __packed; 5346 5347 /** 5348 * iwm_scan_offload_schedule - schedule of scan offload 5349 * @delay: delay between iterations, in seconds. 5350 * @iterations: num of scan iterations 5351 * @full_scan_mul: number of partial scans before each full scan 5352 */ 5353 struct iwm_scan_offload_schedule { 5354 uint16_t delay; 5355 uint8_t iterations; 5356 uint8_t full_scan_mul; 5357 } __packed; 5358 5359 /* 5360 * iwm_scan_offload_flags 5361 * 5362 * IWM_SCAN_OFFLOAD_FLAG_PASS_ALL: pass all results - no filtering. 5363 * IWM_SCAN_OFFLOAD_FLAG_CACHED_CHANNEL: add cached channels to partial scan. 5364 * IWM_SCAN_OFFLOAD_FLAG_ENERGY_SCAN: use energy based scan before partial scan 5365 * on A band. 5366 */ 5367 enum iwm_scan_offload_flags { 5368 IWM_SCAN_OFFLOAD_FLAG_PASS_ALL = (1 << 0), 5369 IWM_SCAN_OFFLOAD_FLAG_CACHED_CHANNEL = (1 << 2), 5370 IWM_SCAN_OFFLOAD_FLAG_ENERGY_SCAN = (1 << 3), 5371 }; 5372 5373 /** 5374 * iwm_scan_offload_req - scan offload request command 5375 * @flags: bitmap - enum iwm_scan_offload_flags. 5376 * @watchdog: maximum scan duration in TU. 5377 * @delay: delay in seconds before first iteration. 5378 * @schedule_line: scan offload schedule, for fast and regular scan. 5379 */ 5380 struct iwm_scan_offload_req { 5381 uint16_t flags; 5382 uint16_t watchdog; 5383 uint16_t delay; 5384 uint16_t reserved; 5385 struct iwm_scan_offload_schedule schedule_line[2]; 5386 } __packed; 5387 5388 enum iwm_scan_offload_compleate_status { 5389 IWM_SCAN_OFFLOAD_COMPLETED = 1, 5390 IWM_SCAN_OFFLOAD_ABORTED = 2, 5391 }; 5392 5393 /** 5394 * struct iwm_lmac_scan_complete_notif - notifies end of scanning (all channels) 5395 * SCAN_COMPLETE_NTF_API_S_VER_3 5396 * @scanned_channels: number of channels scanned (and number of valid results) 5397 * @status: one of SCAN_COMP_STATUS_* 5398 * @bt_status: BT on/off status 5399 * @last_channel: last channel that was scanned 5400 * @tsf_low: TSF timer (lower half) in usecs 5401 * @tsf_high: TSF timer (higher half) in usecs 5402 * @results: an array of scan results, only "scanned_channels" of them are valid 5403 */ 5404 struct iwm_lmac_scan_complete_notif { 5405 uint8_t scanned_channels; 5406 uint8_t status; 5407 uint8_t bt_status; 5408 uint8_t last_channel; 5409 uint32_t tsf_low; 5410 uint32_t tsf_high; 5411 struct iwm_scan_results_notif results[]; 5412 } __packed; 5413 5414 5415 /** 5416 * iwm_scan_offload_complete - IWM_SCAN_OFFLOAD_COMPLETE_NTF_API_S_VER_1 5417 * @last_schedule_line: last schedule line executed (fast or regular) 5418 * @last_schedule_iteration: last scan iteration executed before scan abort 5419 * @status: enum iwm_scan_offload_compleate_status 5420 */ 5421 struct iwm_scan_offload_complete { 5422 uint8_t last_schedule_line; 5423 uint8_t last_schedule_iteration; 5424 uint8_t status; 5425 uint8_t reserved; 5426 } __packed; 5427 5428 /** 5429 * iwm_sched_scan_results - IWM_SCAN_OFFLOAD_MATCH_FOUND_NTF_API_S_VER_1 5430 * @ssid_bitmap: SSIDs indexes found in this iteration 5431 * @client_bitmap: clients that are active and wait for this notification 5432 */ 5433 struct iwm_sched_scan_results { 5434 uint16_t ssid_bitmap; 5435 uint8_t client_bitmap; 5436 uint8_t reserved; 5437 }; 5438 5439 /* 5440 * END mvm/fw-api-scan.h 5441 */ 5442 5443 /* 5444 * BEGIN mvm/fw-api-sta.h 5445 */ 5446 5447 /* UMAC Scan API */ 5448 5449 /* The maximum of either of these cannot exceed 8, because we use an 5450 * 8-bit mask (see IWM_MVM_SCAN_MASK). 5451 */ 5452 #define IWM_MVM_MAX_UMAC_SCANS 8 5453 #define IWM_MVM_MAX_LMAC_SCANS 1 5454 5455 enum iwm_scan_config_flags { 5456 IWM_SCAN_CONFIG_FLAG_ACTIVATE = (1 << 0), 5457 IWM_SCAN_CONFIG_FLAG_DEACTIVATE = (1 << 1), 5458 IWM_SCAN_CONFIG_FLAG_FORBID_CHUB_REQS = (1 << 2), 5459 IWM_SCAN_CONFIG_FLAG_ALLOW_CHUB_REQS = (1 << 3), 5460 IWM_SCAN_CONFIG_FLAG_SET_TX_CHAINS = (1 << 8), 5461 IWM_SCAN_CONFIG_FLAG_SET_RX_CHAINS = (1 << 9), 5462 IWM_SCAN_CONFIG_FLAG_SET_AUX_STA_ID = (1 << 10), 5463 IWM_SCAN_CONFIG_FLAG_SET_ALL_TIMES = (1 << 11), 5464 IWM_SCAN_CONFIG_FLAG_SET_EFFECTIVE_TIMES = (1 << 12), 5465 IWM_SCAN_CONFIG_FLAG_SET_CHANNEL_FLAGS = (1 << 13), 5466 IWM_SCAN_CONFIG_FLAG_SET_LEGACY_RATES = (1 << 14), 5467 IWM_SCAN_CONFIG_FLAG_SET_MAC_ADDR = (1 << 15), 5468 IWM_SCAN_CONFIG_FLAG_SET_FRAGMENTED = (1 << 16), 5469 IWM_SCAN_CONFIG_FLAG_CLEAR_FRAGMENTED = (1 << 17), 5470 IWM_SCAN_CONFIG_FLAG_SET_CAM_MODE = (1 << 18), 5471 IWM_SCAN_CONFIG_FLAG_CLEAR_CAM_MODE = (1 << 19), 5472 IWM_SCAN_CONFIG_FLAG_SET_PROMISC_MODE = (1 << 20), 5473 IWM_SCAN_CONFIG_FLAG_CLEAR_PROMISC_MODE = (1 << 21), 5474 5475 /* Bits 26-31 are for num of channels in channel_array */ 5476 #define IWM_SCAN_CONFIG_N_CHANNELS(n) ((n) << 26) 5477 }; 5478 5479 enum iwm_scan_config_rates { 5480 /* OFDM basic rates */ 5481 IWM_SCAN_CONFIG_RATE_6M = (1 << 0), 5482 IWM_SCAN_CONFIG_RATE_9M = (1 << 1), 5483 IWM_SCAN_CONFIG_RATE_12M = (1 << 2), 5484 IWM_SCAN_CONFIG_RATE_18M = (1 << 3), 5485 IWM_SCAN_CONFIG_RATE_24M = (1 << 4), 5486 IWM_SCAN_CONFIG_RATE_36M = (1 << 5), 5487 IWM_SCAN_CONFIG_RATE_48M = (1 << 6), 5488 IWM_SCAN_CONFIG_RATE_54M = (1 << 7), 5489 /* CCK basic rates */ 5490 IWM_SCAN_CONFIG_RATE_1M = (1 << 8), 5491 IWM_SCAN_CONFIG_RATE_2M = (1 << 9), 5492 IWM_SCAN_CONFIG_RATE_5M = (1 << 10), 5493 IWM_SCAN_CONFIG_RATE_11M = (1 << 11), 5494 5495 /* Bits 16-27 are for supported rates */ 5496 #define IWM_SCAN_CONFIG_SUPPORTED_RATE(rate) ((rate) << 16) 5497 }; 5498 5499 enum iwm_channel_flags { 5500 IWM_CHANNEL_FLAG_EBS = (1 << 0), 5501 IWM_CHANNEL_FLAG_ACCURATE_EBS = (1 << 1), 5502 IWM_CHANNEL_FLAG_EBS_ADD = (1 << 2), 5503 IWM_CHANNEL_FLAG_PRE_SCAN_PASSIVE2ACTIVE = (1 << 3), 5504 }; 5505 5506 /** 5507 * struct iwm_scan_config 5508 * @flags: enum scan_config_flags 5509 * @tx_chains: valid_tx antenna - ANT_* definitions 5510 * @rx_chains: valid_rx antenna - ANT_* definitions 5511 * @legacy_rates: default legacy rates - enum scan_config_rates 5512 * @out_of_channel_time: default max out of serving channel time 5513 * @suspend_time: default max suspend time 5514 * @dwell_active: default dwell time for active scan 5515 * @dwell_passive: default dwell time for passive scan 5516 * @dwell_fragmented: default dwell time for fragmented scan 5517 * @dwell_extended: default dwell time for channels 1, 6 and 11 5518 * @mac_addr: default mac address to be used in probes 5519 * @bcast_sta_id: the index of the station in the fw 5520 * @channel_flags: default channel flags - enum iwm_channel_flags 5521 * scan_config_channel_flag 5522 * @channel_array: default supported channels 5523 */ 5524 struct iwm_scan_config { 5525 uint32_t flags; 5526 uint32_t tx_chains; 5527 uint32_t rx_chains; 5528 uint32_t legacy_rates; 5529 uint32_t out_of_channel_time; 5530 uint32_t suspend_time; 5531 uint8_t dwell_active; 5532 uint8_t dwell_passive; 5533 uint8_t dwell_fragmented; 5534 uint8_t dwell_extended; 5535 uint8_t mac_addr[IEEE80211_ADDR_LEN]; 5536 uint8_t bcast_sta_id; 5537 uint8_t channel_flags; 5538 uint8_t channel_array[]; 5539 } __packed; /* SCAN_CONFIG_DB_CMD_API_S */ 5540 5541 /** 5542 * iwm_umac_scan_flags 5543 *@IWM_UMAC_SCAN_FLAG_PREEMPTIVE: scan process triggered by this scan request 5544 * can be preempted by other scan requests with higher priority. 5545 * The low priority scan will be resumed when the higher proirity scan is 5546 * completed. 5547 *@IWM_UMAC_SCAN_FLAG_START_NOTIF: notification will be sent to the driver 5548 * when scan starts. 5549 */ 5550 enum iwm_umac_scan_flags { 5551 IWM_UMAC_SCAN_FLAG_PREEMPTIVE = (1 << 0), 5552 IWM_UMAC_SCAN_FLAG_START_NOTIF = (1 << 1), 5553 }; 5554 5555 enum iwm_umac_scan_uid_offsets { 5556 IWM_UMAC_SCAN_UID_TYPE_OFFSET = 0, 5557 IWM_UMAC_SCAN_UID_SEQ_OFFSET = 8, 5558 }; 5559 5560 enum iwm_umac_scan_general_flags { 5561 IWM_UMAC_SCAN_GEN_FLAGS_PERIODIC = (1 << 0), 5562 IWM_UMAC_SCAN_GEN_FLAGS_OVER_BT = (1 << 1), 5563 IWM_UMAC_SCAN_GEN_FLAGS_PASS_ALL = (1 << 2), 5564 IWM_UMAC_SCAN_GEN_FLAGS_PASSIVE = (1 << 3), 5565 IWM_UMAC_SCAN_GEN_FLAGS_PRE_CONNECT = (1 << 4), 5566 IWM_UMAC_SCAN_GEN_FLAGS_ITER_COMPLETE = (1 << 5), 5567 IWM_UMAC_SCAN_GEN_FLAGS_MULTIPLE_SSID = (1 << 6), 5568 IWM_UMAC_SCAN_GEN_FLAGS_FRAGMENTED = (1 << 7), 5569 IWM_UMAC_SCAN_GEN_FLAGS_RRM_ENABLED = (1 << 8), 5570 IWM_UMAC_SCAN_GEN_FLAGS_MATCH = (1 << 9), 5571 IWM_UMAC_SCAN_GEN_FLAGS_EXTENDED_DWELL = (1 << 10), 5572 }; 5573 5574 /** 5575 * struct iwm_scan_channel_cfg_umac 5576 * @flags: bitmap - 0-19: directed scan to i'th ssid. 5577 * @channel_num: channel number 1-13 etc. 5578 * @iter_count: repetition count for the channel. 5579 * @iter_interval: interval between two scan iterations on one channel. 5580 */ 5581 struct iwm_scan_channel_cfg_umac { 5582 uint32_t flags; 5583 uint8_t channel_num; 5584 uint8_t iter_count; 5585 uint16_t iter_interval; 5586 } __packed; /* SCAN_CHANNEL_CFG_S_VER2 */ 5587 5588 /** 5589 * struct iwm_scan_umac_schedule 5590 * @interval: interval in seconds between scan iterations 5591 * @iter_count: num of scan iterations for schedule plan, 0xff for infinite loop 5592 * @reserved: for alignment and future use 5593 */ 5594 struct iwm_scan_umac_schedule { 5595 uint16_t interval; 5596 uint8_t iter_count; 5597 uint8_t reserved; 5598 } __packed; /* SCAN_SCHED_PARAM_API_S_VER_1 */ 5599 5600 /** 5601 * struct iwm_scan_req_umac_tail - the rest of the UMAC scan request command 5602 * parameters following channels configuration array. 5603 * @schedule: two scheduling plans. 5604 * @delay: delay in TUs before starting the first scan iteration 5605 * @reserved: for future use and alignment 5606 * @preq: probe request with IEs blocks 5607 * @direct_scan: list of SSIDs for directed active scan 5608 */ 5609 struct iwm_scan_req_umac_tail { 5610 /* SCAN_PERIODIC_PARAMS_API_S_VER_1 */ 5611 struct iwm_scan_umac_schedule schedule[IWM_MAX_SCHED_SCAN_PLANS]; 5612 uint16_t delay; 5613 uint16_t reserved; 5614 /* SCAN_PROBE_PARAMS_API_S_VER_1 */ 5615 struct iwm_scan_probe_req preq; 5616 struct iwm_ssid_ie direct_scan[IWM_PROBE_OPTION_MAX]; 5617 } __packed; 5618 5619 /** 5620 * struct iwm_scan_req_umac 5621 * @flags: &enum iwm_umac_scan_flags 5622 * @uid: scan id, &enum iwm_umac_scan_uid_offsets 5623 * @ooc_priority: out of channel priority - &enum iwm_scan_priority 5624 * @general_flags: &enum iwm_umac_scan_general_flags 5625 * @extended_dwell: dwell time for channels 1, 6 and 11 5626 * @active_dwell: dwell time for active scan 5627 * @passive_dwell: dwell time for passive scan 5628 * @fragmented_dwell: dwell time for fragmented passive scan 5629 * @max_out_time: max out of serving channel time 5630 * @suspend_time: max suspend time 5631 * @scan_priority: scan internal prioritization &enum iwm_scan_priority 5632 * @channel_flags: &enum iwm_scan_channel_flags 5633 * @n_channels: num of channels in scan request 5634 * @reserved: for future use and alignment 5635 * @data: &struct iwm_scan_channel_cfg_umac and 5636 * &struct iwm_scan_req_umac_tail 5637 */ 5638 struct iwm_scan_req_umac { 5639 uint32_t flags; 5640 uint32_t uid; 5641 uint32_t ooc_priority; 5642 /* SCAN_GENERAL_PARAMS_API_S_VER_1 */ 5643 uint32_t general_flags; 5644 uint8_t extended_dwell; 5645 uint8_t active_dwell; 5646 uint8_t passive_dwell; 5647 uint8_t fragmented_dwell; 5648 uint32_t max_out_time; 5649 uint32_t suspend_time; 5650 uint32_t scan_priority; 5651 /* SCAN_CHANNEL_PARAMS_API_S_VER_1 */ 5652 uint8_t channel_flags; 5653 uint8_t n_channels; 5654 uint16_t reserved; 5655 uint8_t data[]; 5656 } __packed; /* SCAN_REQUEST_CMD_UMAC_API_S_VER_1 */ 5657 5658 /** 5659 * struct iwm_umac_scan_abort 5660 * @uid: scan id, &enum iwm_umac_scan_uid_offsets 5661 * @flags: reserved 5662 */ 5663 struct iwm_umac_scan_abort { 5664 uint32_t uid; 5665 uint32_t flags; 5666 } __packed; /* SCAN_ABORT_CMD_UMAC_API_S_VER_1 */ 5667 5668 /** 5669 * struct iwm_umac_scan_complete 5670 * @uid: scan id, &enum iwm_umac_scan_uid_offsets 5671 * @last_schedule: last scheduling line 5672 * @last_iter: last scan iteration number 5673 * @scan status: &enum iwm_scan_offload_complete_status 5674 * @ebs_status: &enum iwm_scan_ebs_status 5675 * @time_from_last_iter: time elapsed from last iteration 5676 * @reserved: for future use 5677 */ 5678 struct iwm_umac_scan_complete { 5679 uint32_t uid; 5680 uint8_t last_schedule; 5681 uint8_t last_iter; 5682 uint8_t status; 5683 uint8_t ebs_status; 5684 uint32_t time_from_last_iter; 5685 uint32_t reserved; 5686 } __packed; /* SCAN_COMPLETE_NTF_UMAC_API_S_VER_1 */ 5687 5688 #define IWM_SCAN_OFFLOAD_MATCHING_CHANNELS_LEN 5 5689 /** 5690 * struct iwm_scan_offload_profile_match - match information 5691 * @bssid: matched bssid 5692 * @channel: channel where the match occurred 5693 * @energy: 5694 * @matching_feature: 5695 * @matching_channels: bitmap of channels that matched, referencing 5696 * the channels passed in tue scan offload request 5697 */ 5698 struct iwm_scan_offload_profile_match { 5699 uint8_t bssid[IEEE80211_ADDR_LEN]; 5700 uint16_t reserved; 5701 uint8_t channel; 5702 uint8_t energy; 5703 uint8_t matching_feature; 5704 uint8_t matching_channels[IWM_SCAN_OFFLOAD_MATCHING_CHANNELS_LEN]; 5705 } __packed; /* SCAN_OFFLOAD_PROFILE_MATCH_RESULTS_S_VER_1 */ 5706 5707 /** 5708 * struct iwm_scan_offload_profiles_query - match results query response 5709 * @matched_profiles: bitmap of matched profiles, referencing the 5710 * matches passed in the scan offload request 5711 * @last_scan_age: age of the last offloaded scan 5712 * @n_scans_done: number of offloaded scans done 5713 * @gp2_d0u: GP2 when D0U occurred 5714 * @gp2_invoked: GP2 when scan offload was invoked 5715 * @resume_while_scanning: not used 5716 * @self_recovery: obsolete 5717 * @reserved: reserved 5718 * @matches: array of match information, one for each match 5719 */ 5720 struct iwm_scan_offload_profiles_query { 5721 uint32_t matched_profiles; 5722 uint32_t last_scan_age; 5723 uint32_t n_scans_done; 5724 uint32_t gp2_d0u; 5725 uint32_t gp2_invoked; 5726 uint8_t resume_while_scanning; 5727 uint8_t self_recovery; 5728 uint16_t reserved; 5729 struct iwm_scan_offload_profile_match matches[IWM_SCAN_MAX_PROFILES]; 5730 } __packed; /* SCAN_OFFLOAD_PROFILES_QUERY_RSP_S_VER_2 */ 5731 5732 /** 5733 * struct iwm_umac_scan_iter_complete_notif - notifies end of scanning iteration 5734 * @uid: scan id, &enum iwm_umac_scan_uid_offsets 5735 * @scanned_channels: number of channels scanned and number of valid elements in 5736 * results array 5737 * @status: one of SCAN_COMP_STATUS_* 5738 * @bt_status: BT on/off status 5739 * @last_channel: last channel that was scanned 5740 * @tsf_low: TSF timer (lower half) in usecs 5741 * @tsf_high: TSF timer (higher half) in usecs 5742 * @results: array of scan results, only "scanned_channels" of them are valid 5743 */ 5744 struct iwm_umac_scan_iter_complete_notif { 5745 uint32_t uid; 5746 uint8_t scanned_channels; 5747 uint8_t status; 5748 uint8_t bt_status; 5749 uint8_t last_channel; 5750 uint32_t tsf_low; 5751 uint32_t tsf_high; 5752 struct iwm_scan_results_notif results[]; 5753 } __packed; /* SCAN_ITER_COMPLETE_NTF_UMAC_API_S_VER_1 */ 5754 5755 /* Please keep this enum *SORTED* by hex value. 5756 * Needed for binary search, otherwise a warning will be triggered. 5757 */ 5758 enum iwm_scan_subcmd_ids { 5759 IWM_GSCAN_START_CMD = 0x0, 5760 IWM_GSCAN_STOP_CMD = 0x1, 5761 IWM_GSCAN_SET_HOTLIST_CMD = 0x2, 5762 IWM_GSCAN_RESET_HOTLIST_CMD = 0x3, 5763 IWM_GSCAN_SET_SIGNIFICANT_CHANGE_CMD = 0x4, 5764 IWM_GSCAN_RESET_SIGNIFICANT_CHANGE_CMD = 0x5, 5765 IWM_GSCAN_SIGNIFICANT_CHANGE_EVENT = 0xFD, 5766 IWM_GSCAN_HOTLIST_CHANGE_EVENT = 0xFE, 5767 IWM_GSCAN_RESULTS_AVAILABLE_EVENT = 0xFF, 5768 }; 5769 5770 /* STA API */ 5771 5772 /** 5773 * enum iwm_sta_flags - flags for the ADD_STA host command 5774 * @IWM_STA_FLG_REDUCED_TX_PWR_CTRL: 5775 * @IWM_STA_FLG_REDUCED_TX_PWR_DATA: 5776 * @IWM_STA_FLG_DISABLE_TX: set if TX should be disabled 5777 * @IWM_STA_FLG_PS: set if STA is in Power Save 5778 * @IWM_STA_FLG_INVALID: set if STA is invalid 5779 * @IWM_STA_FLG_DLP_EN: Direct Link Protocol is enabled 5780 * @IWM_STA_FLG_SET_ALL_KEYS: the current key applies to all key IDs 5781 * @IWM_STA_FLG_DRAIN_FLOW: drain flow 5782 * @IWM_STA_FLG_PAN: STA is for PAN interface 5783 * @IWM_STA_FLG_CLASS_AUTH: 5784 * @IWM_STA_FLG_CLASS_ASSOC: 5785 * @IWM_STA_FLG_CLASS_MIMO_PROT: 5786 * @IWM_STA_FLG_MAX_AGG_SIZE_MSK: maximal size for A-MPDU 5787 * @IWM_STA_FLG_AGG_MPDU_DENS_MSK: maximal MPDU density for Tx aggregation 5788 * @IWM_STA_FLG_FAT_EN_MSK: support for channel width (for Tx). This flag is 5789 * initialised by driver and can be updated by fw upon reception of 5790 * action frames that can change the channel width. When cleared the fw 5791 * will send all the frames in 20MHz even when FAT channel is requested. 5792 * @IWM_STA_FLG_MIMO_EN_MSK: support for MIMO. This flag is initialised by the 5793 * driver and can be updated by fw upon reception of action frames. 5794 * @IWM_STA_FLG_MFP_EN: Management Frame Protection 5795 */ 5796 enum iwm_sta_flags { 5797 IWM_STA_FLG_REDUCED_TX_PWR_CTRL = (1 << 3), 5798 IWM_STA_FLG_REDUCED_TX_PWR_DATA = (1 << 6), 5799 5800 IWM_STA_FLG_DISABLE_TX = (1 << 4), 5801 5802 IWM_STA_FLG_PS = (1 << 8), 5803 IWM_STA_FLG_DRAIN_FLOW = (1 << 12), 5804 IWM_STA_FLG_PAN = (1 << 13), 5805 IWM_STA_FLG_CLASS_AUTH = (1 << 14), 5806 IWM_STA_FLG_CLASS_ASSOC = (1 << 15), 5807 IWM_STA_FLG_RTS_MIMO_PROT = (1 << 17), 5808 5809 IWM_STA_FLG_MAX_AGG_SIZE_SHIFT = 19, 5810 IWM_STA_FLG_MAX_AGG_SIZE_8K = (0 << IWM_STA_FLG_MAX_AGG_SIZE_SHIFT), 5811 IWM_STA_FLG_MAX_AGG_SIZE_16K = (1 << IWM_STA_FLG_MAX_AGG_SIZE_SHIFT), 5812 IWM_STA_FLG_MAX_AGG_SIZE_32K = (2 << IWM_STA_FLG_MAX_AGG_SIZE_SHIFT), 5813 IWM_STA_FLG_MAX_AGG_SIZE_64K = (3 << IWM_STA_FLG_MAX_AGG_SIZE_SHIFT), 5814 IWM_STA_FLG_MAX_AGG_SIZE_128K = (4 << IWM_STA_FLG_MAX_AGG_SIZE_SHIFT), 5815 IWM_STA_FLG_MAX_AGG_SIZE_256K = (5 << IWM_STA_FLG_MAX_AGG_SIZE_SHIFT), 5816 IWM_STA_FLG_MAX_AGG_SIZE_512K = (6 << IWM_STA_FLG_MAX_AGG_SIZE_SHIFT), 5817 IWM_STA_FLG_MAX_AGG_SIZE_1024K = (7 << IWM_STA_FLG_MAX_AGG_SIZE_SHIFT), 5818 IWM_STA_FLG_MAX_AGG_SIZE_MSK = (7 << IWM_STA_FLG_MAX_AGG_SIZE_SHIFT), 5819 5820 IWM_STA_FLG_AGG_MPDU_DENS_SHIFT = 23, 5821 IWM_STA_FLG_AGG_MPDU_DENS_2US = (4 << IWM_STA_FLG_AGG_MPDU_DENS_SHIFT), 5822 IWM_STA_FLG_AGG_MPDU_DENS_4US = (5 << IWM_STA_FLG_AGG_MPDU_DENS_SHIFT), 5823 IWM_STA_FLG_AGG_MPDU_DENS_8US = (6 << IWM_STA_FLG_AGG_MPDU_DENS_SHIFT), 5824 IWM_STA_FLG_AGG_MPDU_DENS_16US = (7 << IWM_STA_FLG_AGG_MPDU_DENS_SHIFT), 5825 IWM_STA_FLG_AGG_MPDU_DENS_MSK = (7 << IWM_STA_FLG_AGG_MPDU_DENS_SHIFT), 5826 5827 IWM_STA_FLG_FAT_EN_20MHZ = (0 << 26), 5828 IWM_STA_FLG_FAT_EN_40MHZ = (1 << 26), 5829 IWM_STA_FLG_FAT_EN_80MHZ = (2 << 26), 5830 IWM_STA_FLG_FAT_EN_160MHZ = (3 << 26), 5831 IWM_STA_FLG_FAT_EN_MSK = (3 << 26), 5832 5833 IWM_STA_FLG_MIMO_EN_SISO = (0 << 28), 5834 IWM_STA_FLG_MIMO_EN_MIMO2 = (1 << 28), 5835 IWM_STA_FLG_MIMO_EN_MIMO3 = (2 << 28), 5836 IWM_STA_FLG_MIMO_EN_MSK = (3 << 28), 5837 }; 5838 5839 /** 5840 * enum iwm_sta_key_flag - key flags for the ADD_STA host command 5841 * @IWM_STA_KEY_FLG_NO_ENC: no encryption 5842 * @IWM_STA_KEY_FLG_WEP: WEP encryption algorithm 5843 * @IWM_STA_KEY_FLG_CCM: CCMP encryption algorithm 5844 * @IWM_STA_KEY_FLG_TKIP: TKIP encryption algorithm 5845 * @IWM_STA_KEY_FLG_EXT: extended cipher algorithm (depends on the FW support) 5846 * @IWM_STA_KEY_FLG_CMAC: CMAC encryption algorithm 5847 * @IWM_STA_KEY_FLG_ENC_UNKNOWN: unknown encryption algorithm 5848 * @IWM_STA_KEY_FLG_EN_MSK: mask for encryption algorithmi value 5849 * @IWM_STA_KEY_FLG_WEP_KEY_MAP: wep is either a group key (0 - legacy WEP) or from 5850 * station info array (1 - n 1X mode) 5851 * @IWM_STA_KEY_FLG_KEYID_MSK: the index of the key 5852 * @IWM_STA_KEY_NOT_VALID: key is invalid 5853 * @IWM_STA_KEY_FLG_WEP_13BYTES: set for 13 bytes WEP key 5854 * @IWM_STA_KEY_MULTICAST: set for multical key 5855 * @IWM_STA_KEY_MFP: key is used for Management Frame Protection 5856 */ 5857 enum iwm_sta_key_flag { 5858 IWM_STA_KEY_FLG_NO_ENC = (0 << 0), 5859 IWM_STA_KEY_FLG_WEP = (1 << 0), 5860 IWM_STA_KEY_FLG_CCM = (2 << 0), 5861 IWM_STA_KEY_FLG_TKIP = (3 << 0), 5862 IWM_STA_KEY_FLG_EXT = (4 << 0), 5863 IWM_STA_KEY_FLG_CMAC = (6 << 0), 5864 IWM_STA_KEY_FLG_ENC_UNKNOWN = (7 << 0), 5865 IWM_STA_KEY_FLG_EN_MSK = (7 << 0), 5866 5867 IWM_STA_KEY_FLG_WEP_KEY_MAP = (1 << 3), 5868 IWM_STA_KEY_FLG_KEYID_POS = 8, 5869 IWM_STA_KEY_FLG_KEYID_MSK = (3 << IWM_STA_KEY_FLG_KEYID_POS), 5870 IWM_STA_KEY_NOT_VALID = (1 << 11), 5871 IWM_STA_KEY_FLG_WEP_13BYTES = (1 << 12), 5872 IWM_STA_KEY_MULTICAST = (1 << 14), 5873 IWM_STA_KEY_MFP = (1 << 15), 5874 }; 5875 5876 /** 5877 * enum iwm_sta_modify_flag - indicate to the fw what flag are being changed 5878 * @IWM_STA_MODIFY_QUEUE_REMOVAL: this command removes a queue 5879 * @IWM_STA_MODIFY_TID_DISABLE_TX: this command modifies %tid_disable_tx 5880 * @IWM_STA_MODIFY_TX_RATE: unused 5881 * @IWM_STA_MODIFY_ADD_BA_TID: this command modifies %add_immediate_ba_tid 5882 * @IWM_STA_MODIFY_REMOVE_BA_TID: this command modifies %remove_immediate_ba_tid 5883 * @IWM_STA_MODIFY_SLEEPING_STA_TX_COUNT: this command modifies %sleep_tx_count 5884 * @IWM_STA_MODIFY_PROT_TH: 5885 * @IWM_STA_MODIFY_QUEUES: modify the queues used by this station 5886 */ 5887 enum iwm_sta_modify_flag { 5888 IWM_STA_MODIFY_QUEUE_REMOVAL = (1 << 0), 5889 IWM_STA_MODIFY_TID_DISABLE_TX = (1 << 1), 5890 IWM_STA_MODIFY_TX_RATE = (1 << 2), 5891 IWM_STA_MODIFY_ADD_BA_TID = (1 << 3), 5892 IWM_STA_MODIFY_REMOVE_BA_TID = (1 << 4), 5893 IWM_STA_MODIFY_SLEEPING_STA_TX_COUNT = (1 << 5), 5894 IWM_STA_MODIFY_PROT_TH = (1 << 6), 5895 IWM_STA_MODIFY_QUEUES = (1 << 7), 5896 }; 5897 5898 #define IWM_STA_MODE_MODIFY 1 5899 5900 /** 5901 * enum iwm_sta_sleep_flag - type of sleep of the station 5902 * @IWM_STA_SLEEP_STATE_AWAKE: 5903 * @IWM_STA_SLEEP_STATE_PS_POLL: 5904 * @IWM_STA_SLEEP_STATE_UAPSD: 5905 * @IWM_STA_SLEEP_STATE_MOREDATA: set more-data bit on 5906 * (last) released frame 5907 */ 5908 enum iwm_sta_sleep_flag { 5909 IWM_STA_SLEEP_STATE_AWAKE = 0, 5910 IWM_STA_SLEEP_STATE_PS_POLL = (1 << 0), 5911 IWM_STA_SLEEP_STATE_UAPSD = (1 << 1), 5912 IWM_STA_SLEEP_STATE_MOREDATA = (1 << 2), 5913 }; 5914 5915 /* STA ID and color bits definitions */ 5916 #define IWM_STA_ID_SEED (0x0f) 5917 #define IWM_STA_ID_POS (0) 5918 #define IWM_STA_ID_MSK (IWM_STA_ID_SEED << IWM_STA_ID_POS) 5919 5920 #define IWM_STA_COLOR_SEED (0x7) 5921 #define IWM_STA_COLOR_POS (4) 5922 #define IWM_STA_COLOR_MSK (IWM_STA_COLOR_SEED << IWM_STA_COLOR_POS) 5923 5924 #define IWM_STA_ID_N_COLOR_GET_COLOR(id_n_color) \ 5925 (((id_n_color) & IWM_STA_COLOR_MSK) >> IWM_STA_COLOR_POS) 5926 #define IWM_STA_ID_N_COLOR_GET_ID(id_n_color) \ 5927 (((id_n_color) & IWM_STA_ID_MSK) >> IWM_STA_ID_POS) 5928 5929 #define IWM_STA_KEY_MAX_NUM (16) 5930 #define IWM_STA_KEY_IDX_INVALID (0xff) 5931 #define IWM_STA_KEY_MAX_DATA_KEY_NUM (4) 5932 #define IWM_MAX_GLOBAL_KEYS (4) 5933 #define IWM_STA_KEY_LEN_WEP40 (5) 5934 #define IWM_STA_KEY_LEN_WEP104 (13) 5935 5936 /** 5937 * struct iwm_mvm_keyinfo - key information 5938 * @key_flags: type %iwm_sta_key_flag 5939 * @tkip_rx_tsc_byte2: TSC[2] for key mix ph1 detection 5940 * @tkip_rx_ttak: 10-byte unicast TKIP TTAK for Rx 5941 * @key_offset: key offset in the fw's key table 5942 * @key: 16-byte unicast decryption key 5943 * @tx_secur_seq_cnt: initial RSC / PN needed for replay check 5944 * @hw_tkip_mic_rx_key: byte: MIC Rx Key - used for TKIP only 5945 * @hw_tkip_mic_tx_key: byte: MIC Tx Key - used for TKIP only 5946 */ 5947 struct iwm_mvm_keyinfo { 5948 uint16_t key_flags; 5949 uint8_t tkip_rx_tsc_byte2; 5950 uint8_t reserved1; 5951 uint16_t tkip_rx_ttak[5]; 5952 uint8_t key_offset; 5953 uint8_t reserved2; 5954 uint8_t key[16]; 5955 uint64_t tx_secur_seq_cnt; 5956 uint64_t hw_tkip_mic_rx_key; 5957 uint64_t hw_tkip_mic_tx_key; 5958 } __packed; 5959 5960 #define IWM_ADD_STA_STATUS_MASK 0xFF 5961 #define IWM_ADD_STA_BAID_VALID_MASK 0x8000 5962 #define IWM_ADD_STA_BAID_MASK 0x7F00 5963 #define IWM_ADD_STA_BAID_SHIFT 8 5964 5965 /** 5966 * struct iwm_mvm_add_sta_cmd_v7 - Add/modify a station in the fw's sta table. 5967 * ( REPLY_ADD_STA = 0x18 ) 5968 * @add_modify: 1: modify existing, 0: add new station 5969 * @awake_acs: 5970 * @tid_disable_tx: is tid BIT(tid) enabled for Tx. Clear BIT(x) to enable 5971 * AMPDU for tid x. Set %IWM_STA_MODIFY_TID_DISABLE_TX to change this field. 5972 * @mac_id_n_color: the Mac context this station belongs to 5973 * @addr[IEEE80211_ADDR_LEN]: station's MAC address 5974 * @sta_id: index of station in uCode's station table 5975 * @modify_mask: IWM_STA_MODIFY_*, selects which parameters to modify vs. leave 5976 * alone. 1 - modify, 0 - don't change. 5977 * @station_flags: look at %iwm_sta_flags 5978 * @station_flags_msk: what of %station_flags have changed 5979 * @add_immediate_ba_tid: tid for which to add block-ack support (Rx) 5980 * Set %IWM_STA_MODIFY_ADD_BA_TID to use this field, and also set 5981 * add_immediate_ba_ssn. 5982 * @remove_immediate_ba_tid: tid for which to remove block-ack support (Rx) 5983 * Set %IWM_STA_MODIFY_REMOVE_BA_TID to use this field 5984 * @add_immediate_ba_ssn: ssn for the Rx block-ack session. Used together with 5985 * add_immediate_ba_tid. 5986 * @sleep_tx_count: number of packets to transmit to station even though it is 5987 * asleep. Used to synchronise PS-poll and u-APSD responses while ucode 5988 * keeps track of STA sleep state. 5989 * @sleep_state_flags: Look at %iwm_sta_sleep_flag. 5990 * @assoc_id: assoc_id to be sent in VHT PLCP (9-bit), for grp use 0, for AP 5991 * mac-addr. 5992 * @beamform_flags: beam forming controls 5993 * @tfd_queue_msk: tfd queues used by this station 5994 * 5995 * The device contains an internal table of per-station information, with info 5996 * on security keys, aggregation parameters, and Tx rates for initial Tx 5997 * attempt and any retries (set by IWM_REPLY_TX_LINK_QUALITY_CMD). 5998 * 5999 * ADD_STA sets up the table entry for one station, either creating a new 6000 * entry, or modifying a pre-existing one. 6001 */ 6002 struct iwm_mvm_add_sta_cmd_v7 { 6003 uint8_t add_modify; 6004 uint8_t awake_acs; 6005 uint16_t tid_disable_tx; 6006 uint32_t mac_id_n_color; 6007 uint8_t addr[IEEE80211_ADDR_LEN]; /* _STA_ID_MODIFY_INFO_API_S_VER_1 */ 6008 uint16_t reserved2; 6009 uint8_t sta_id; 6010 uint8_t modify_mask; 6011 uint16_t reserved3; 6012 uint32_t station_flags; 6013 uint32_t station_flags_msk; 6014 uint8_t add_immediate_ba_tid; 6015 uint8_t remove_immediate_ba_tid; 6016 uint16_t add_immediate_ba_ssn; 6017 uint16_t sleep_tx_count; 6018 uint16_t sleep_state_flags; 6019 uint16_t assoc_id; 6020 uint16_t beamform_flags; 6021 uint32_t tfd_queue_msk; 6022 } __packed; /* ADD_STA_CMD_API_S_VER_7 */ 6023 6024 /** 6025 * struct iwm_mvm_add_sta_key_cmd - add/modify sta key 6026 * ( IWM_REPLY_ADD_STA_KEY = 0x17 ) 6027 * @sta_id: index of station in uCode's station table 6028 * @key_offset: key offset in key storage 6029 * @key_flags: type %iwm_sta_key_flag 6030 * @key: key material data 6031 * @key2: key material data 6032 * @rx_secur_seq_cnt: RX security sequence counter for the key 6033 * @tkip_rx_tsc_byte2: TSC[2] for key mix ph1 detection 6034 * @tkip_rx_ttak: 10-byte unicast TKIP TTAK for Rx 6035 */ 6036 struct iwm_mvm_add_sta_key_cmd { 6037 uint8_t sta_id; 6038 uint8_t key_offset; 6039 uint16_t key_flags; 6040 uint8_t key[16]; 6041 uint8_t key2[16]; 6042 uint8_t rx_secur_seq_cnt[16]; 6043 uint8_t tkip_rx_tsc_byte2; 6044 uint8_t reserved; 6045 uint16_t tkip_rx_ttak[5]; 6046 } __packed; /* IWM_ADD_MODIFY_STA_KEY_API_S_VER_1 */ 6047 6048 /** 6049 * enum iwm_mvm_add_sta_rsp_status - status in the response to ADD_STA command 6050 * @IWM_ADD_STA_SUCCESS: operation was executed successfully 6051 * @IWM_ADD_STA_STATIONS_OVERLOAD: no room left in the fw's station table 6052 * @IWM_ADD_STA_IMMEDIATE_BA_FAILURE: can't add Rx block ack session 6053 * @IWM_ADD_STA_MODIFY_NON_EXISTING_STA: driver requested to modify a station 6054 * that doesn't exist. 6055 */ 6056 enum iwm_mvm_add_sta_rsp_status { 6057 IWM_ADD_STA_SUCCESS = 0x1, 6058 IWM_ADD_STA_STATIONS_OVERLOAD = 0x2, 6059 IWM_ADD_STA_IMMEDIATE_BA_FAILURE = 0x4, 6060 IWM_ADD_STA_MODIFY_NON_EXISTING_STA = 0x8, 6061 }; 6062 6063 /** 6064 * struct iwm_mvm_rm_sta_cmd - Add / modify a station in the fw's station table 6065 * ( IWM_REMOVE_STA = 0x19 ) 6066 * @sta_id: the station id of the station to be removed 6067 */ 6068 struct iwm_mvm_rm_sta_cmd { 6069 uint8_t sta_id; 6070 uint8_t reserved[3]; 6071 } __packed; /* IWM_REMOVE_STA_CMD_API_S_VER_2 */ 6072 6073 /** 6074 * struct iwm_mvm_mgmt_mcast_key_cmd 6075 * ( IWM_MGMT_MCAST_KEY = 0x1f ) 6076 * @ctrl_flags: %iwm_sta_key_flag 6077 * @IGTK: 6078 * @K1: IGTK master key 6079 * @K2: IGTK sub key 6080 * @sta_id: station ID that support IGTK 6081 * @key_id: 6082 * @receive_seq_cnt: initial RSC/PN needed for replay check 6083 */ 6084 struct iwm_mvm_mgmt_mcast_key_cmd { 6085 uint32_t ctrl_flags; 6086 uint8_t IGTK[16]; 6087 uint8_t K1[16]; 6088 uint8_t K2[16]; 6089 uint32_t key_id; 6090 uint32_t sta_id; 6091 uint64_t receive_seq_cnt; 6092 } __packed; /* SEC_MGMT_MULTICAST_KEY_CMD_API_S_VER_1 */ 6093 6094 struct iwm_mvm_wep_key { 6095 uint8_t key_index; 6096 uint8_t key_offset; 6097 uint16_t reserved1; 6098 uint8_t key_size; 6099 uint8_t reserved2[3]; 6100 uint8_t key[16]; 6101 } __packed; 6102 6103 struct iwm_mvm_wep_key_cmd { 6104 uint32_t mac_id_n_color; 6105 uint8_t num_keys; 6106 uint8_t decryption_type; 6107 uint8_t flags; 6108 uint8_t reserved; 6109 struct iwm_mvm_wep_key wep_key[0]; 6110 } __packed; /* SEC_CURR_WEP_KEY_CMD_API_S_VER_2 */ 6111 6112 /* 6113 * END mvm/fw-api-sta.h 6114 */ 6115 6116 /* 6117 * BT coex 6118 */ 6119 6120 enum iwm_bt_coex_mode { 6121 IWM_BT_COEX_DISABLE = 0x0, 6122 IWM_BT_COEX_NW = 0x1, 6123 IWM_BT_COEX_BT = 0x2, 6124 IWM_BT_COEX_WIFI = 0x3, 6125 }; /* BT_COEX_MODES_E */ 6126 6127 enum iwm_bt_coex_enabled_modules { 6128 IWM_BT_COEX_MPLUT_ENABLED = (1 << 0), 6129 IWM_BT_COEX_MPLUT_BOOST_ENABLED = (1 << 1), 6130 IWM_BT_COEX_SYNC2SCO_ENABLED = (1 << 2), 6131 IWM_BT_COEX_CORUN_ENABLED = (1 << 3), 6132 IWM_BT_COEX_HIGH_BAND_RET = (1 << 4), 6133 }; /* BT_COEX_MODULES_ENABLE_E_VER_1 */ 6134 6135 /** 6136 * struct iwm_bt_coex_cmd - bt coex configuration command 6137 * @mode: enum %iwm_bt_coex_mode 6138 * @enabled_modules: enum %iwm_bt_coex_enabled_modules 6139 * 6140 * The structure is used for the BT_COEX command. 6141 */ 6142 struct iwm_bt_coex_cmd { 6143 uint32_t mode; 6144 uint32_t enabled_modules; 6145 } __packed; /* BT_COEX_CMD_API_S_VER_6 */ 6146 6147 6148 /* 6149 * Location Aware Regulatory (LAR) API - MCC updates 6150 */ 6151 6152 /** 6153 * struct iwm_mcc_update_cmd_v1 - Request the device to update geographic 6154 * regulatory profile according to the given MCC (Mobile Country Code). 6155 * The MCC is two letter-code, ascii upper case[A-Z] or '00' for world domain. 6156 * 'ZZ' MCC will be used to switch to NVM default profile; in this case, the 6157 * MCC in the cmd response will be the relevant MCC in the NVM. 6158 * @mcc: given mobile country code 6159 * @source_id: the source from where we got the MCC, see iwm_mcc_source 6160 * @reserved: reserved for alignment 6161 */ 6162 struct iwm_mcc_update_cmd_v1 { 6163 uint16_t mcc; 6164 uint8_t source_id; 6165 uint8_t reserved; 6166 } __packed; /* LAR_UPDATE_MCC_CMD_API_S_VER_1 */ 6167 6168 /** 6169 * struct iwm_mcc_update_cmd - Request the device to update geographic 6170 * regulatory profile according to the given MCC (Mobile Country Code). 6171 * The MCC is two letter-code, ascii upper case[A-Z] or '00' for world domain. 6172 * 'ZZ' MCC will be used to switch to NVM default profile; in this case, the 6173 * MCC in the cmd response will be the relevant MCC in the NVM. 6174 * @mcc: given mobile country code 6175 * @source_id: the source from where we got the MCC, see iwm_mcc_source 6176 * @reserved: reserved for alignment 6177 * @key: integrity key for MCC API OEM testing 6178 * @reserved2: reserved 6179 */ 6180 struct iwm_mcc_update_cmd { 6181 uint16_t mcc; 6182 uint8_t source_id; 6183 uint8_t reserved; 6184 uint32_t key; 6185 uint32_t reserved2[5]; 6186 } __packed; /* LAR_UPDATE_MCC_CMD_API_S_VER_2 */ 6187 6188 /** 6189 * iwm_mcc_update_resp_v1 - response to MCC_UPDATE_CMD. 6190 * Contains the new channel control profile map, if changed, and the new MCC 6191 * (mobile country code). 6192 * The new MCC may be different than what was requested in MCC_UPDATE_CMD. 6193 * @status: see &enum iwm_mcc_update_status 6194 * @mcc: the new applied MCC 6195 * @cap: capabilities for all channels which matches the MCC 6196 * @source_id: the MCC source, see iwm_mcc_source 6197 * @n_channels: number of channels in @channels_data (may be 14, 39, 50 or 51 6198 * channels, depending on platform) 6199 * @channels: channel control data map, DWORD for each channel. Only the first 6200 * 16bits are used. 6201 */ 6202 struct iwm_mcc_update_resp_v1 { 6203 uint32_t status; 6204 uint16_t mcc; 6205 uint8_t cap; 6206 uint8_t source_id; 6207 uint32_t n_channels; 6208 uint32_t channels[0]; 6209 } __packed; /* LAR_UPDATE_MCC_CMD_RESP_S_VER_1 */ 6210 6211 /** 6212 * iwm_mcc_update_resp - response to MCC_UPDATE_CMD. 6213 * Contains the new channel control profile map, if changed, and the new MCC 6214 * (mobile country code). 6215 * The new MCC may be different than what was requested in MCC_UPDATE_CMD. 6216 * @status: see &enum iwm_mcc_update_status 6217 * @mcc: the new applied MCC 6218 * @cap: capabilities for all channels which matches the MCC 6219 * @source_id: the MCC source, see iwm_mcc_source 6220 * @time: time elapsed from the MCC test start (in 30 seconds TU) 6221 * @reserved: reserved. 6222 * @n_channels: number of channels in @channels_data (may be 14, 39, 50 or 51 6223 * channels, depending on platform) 6224 * @channels: channel control data map, DWORD for each channel. Only the first 6225 * 16bits are used. 6226 */ 6227 struct iwm_mcc_update_resp { 6228 uint32_t status; 6229 uint16_t mcc; 6230 uint8_t cap; 6231 uint8_t source_id; 6232 uint16_t time; 6233 uint16_t reserved; 6234 uint32_t n_channels; 6235 uint32_t channels[0]; 6236 } __packed; /* LAR_UPDATE_MCC_CMD_RESP_S_VER_2 */ 6237 6238 /** 6239 * struct iwm_mcc_chub_notif - chub notifies of mcc change 6240 * (MCC_CHUB_UPDATE_CMD = 0xc9) 6241 * The Chub (Communication Hub, CommsHUB) is a HW component that connects to 6242 * the cellular and connectivity cores that gets updates of the mcc, and 6243 * notifies the ucode directly of any mcc change. 6244 * The ucode requests the driver to request the device to update geographic 6245 * regulatory profile according to the given MCC (Mobile Country Code). 6246 * The MCC is two letter-code, ascii upper case[A-Z] or '00' for world domain. 6247 * 'ZZ' MCC will be used to switch to NVM default profile; in this case, the 6248 * MCC in the cmd response will be the relevant MCC in the NVM. 6249 * @mcc: given mobile country code 6250 * @source_id: identity of the change originator, see iwm_mcc_source 6251 * @reserved1: reserved for alignment 6252 */ 6253 struct iwm_mcc_chub_notif { 6254 uint16_t mcc; 6255 uint8_t source_id; 6256 uint8_t reserved1; 6257 } __packed; /* LAR_MCC_NOTIFY_S */ 6258 6259 enum iwm_mcc_update_status { 6260 IWM_MCC_RESP_NEW_CHAN_PROFILE, 6261 IWM_MCC_RESP_SAME_CHAN_PROFILE, 6262 IWM_MCC_RESP_INVALID, 6263 IWM_MCC_RESP_NVM_DISABLED, 6264 IWM_MCC_RESP_ILLEGAL, 6265 IWM_MCC_RESP_LOW_PRIORITY, 6266 IWM_MCC_RESP_TEST_MODE_ACTIVE, 6267 IWM_MCC_RESP_TEST_MODE_NOT_ACTIVE, 6268 IWM_MCC_RESP_TEST_MODE_DENIAL_OF_SERVICE, 6269 }; 6270 6271 enum iwm_mcc_source { 6272 IWM_MCC_SOURCE_OLD_FW = 0, 6273 IWM_MCC_SOURCE_ME = 1, 6274 IWM_MCC_SOURCE_BIOS = 2, 6275 IWM_MCC_SOURCE_3G_LTE_HOST = 3, 6276 IWM_MCC_SOURCE_3G_LTE_DEVICE = 4, 6277 IWM_MCC_SOURCE_WIFI = 5, 6278 IWM_MCC_SOURCE_RESERVED = 6, 6279 IWM_MCC_SOURCE_DEFAULT = 7, 6280 IWM_MCC_SOURCE_UNINITIALIZED = 8, 6281 IWM_MCC_SOURCE_MCC_API = 9, 6282 IWM_MCC_SOURCE_GET_CURRENT = 0x10, 6283 IWM_MCC_SOURCE_GETTING_MCC_TEST_MODE = 0x11, 6284 }; 6285 6286 /* 6287 * Some cherry-picked definitions 6288 */ 6289 6290 #define IWM_FRAME_LIMIT 64 6291 6292 /* 6293 * From Linux commit ab02165ccec4c78162501acedeef1a768acdb811: 6294 * As the firmware is slowly running out of command IDs and grouping of 6295 * commands is desirable anyway, the firmware is extending the command 6296 * header from 4 bytes to 8 bytes to introduce a group (in place of the 6297 * former flags field, since that's always 0 on commands and thus can 6298 * be easily used to distinguish between the two). 6299 * 6300 * These functions retrieve specific information from the id field in 6301 * the iwm_host_cmd struct which contains the command id, the group id, 6302 * and the version of the command. 6303 */ 6304 static inline uint8_t 6305 iwm_cmd_opcode(uint32_t cmdid) 6306 { 6307 return cmdid & 0xff; 6308 } 6309 6310 static inline uint8_t 6311 iwm_cmd_groupid(uint32_t cmdid) 6312 { 6313 return ((cmdid & 0Xff00) >> 8); 6314 } 6315 6316 static inline uint8_t 6317 iwm_cmd_version(uint32_t cmdid) 6318 { 6319 return ((cmdid & 0xff0000) >> 16); 6320 } 6321 6322 static inline uint32_t 6323 iwm_cmd_id(uint8_t opcode, uint8_t groupid, uint8_t version) 6324 { 6325 return opcode + (groupid << 8) + (version << 16); 6326 } 6327 6328 /* make uint16_t wide id out of uint8_t group and opcode */ 6329 #define IWM_WIDE_ID(grp, opcode) ((grp << 8) | opcode) 6330 6331 /* due to the conversion, this group is special */ 6332 #define IWM_ALWAYS_LONG_GROUP 1 6333 6334 struct iwm_cmd_header { 6335 uint8_t code; 6336 uint8_t flags; 6337 uint8_t idx; 6338 uint8_t qid; 6339 } __packed; 6340 6341 struct iwm_cmd_header_wide { 6342 uint8_t opcode; 6343 uint8_t group_id; 6344 uint8_t idx; 6345 uint8_t qid; 6346 uint16_t length; 6347 uint8_t reserved; 6348 uint8_t version; 6349 } __packed; 6350 6351 enum iwm_power_scheme { 6352 IWM_POWER_SCHEME_CAM = 1, 6353 IWM_POWER_SCHEME_BPS, 6354 IWM_POWER_SCHEME_LP 6355 }; 6356 6357 #define IWM_DEF_CMD_PAYLOAD_SIZE 320 6358 #define IWM_MAX_CMD_PAYLOAD_SIZE ((4096 - 4) - sizeof(struct iwm_cmd_header)) 6359 #define IWM_CMD_FAILED_MSK 0x40 6360 6361 /** 6362 * struct iwm_device_cmd 6363 * 6364 * For allocation of the command and tx queues, this establishes the overall 6365 * size of the largest command we send to uCode, except for commands that 6366 * aren't fully copied and use other TFD space. 6367 */ 6368 struct iwm_device_cmd { 6369 union { 6370 struct { 6371 struct iwm_cmd_header hdr; 6372 uint8_t data[IWM_DEF_CMD_PAYLOAD_SIZE]; 6373 }; 6374 struct { 6375 struct iwm_cmd_header_wide hdr_wide; 6376 uint8_t data_wide[IWM_DEF_CMD_PAYLOAD_SIZE - 6377 sizeof(struct iwm_cmd_header_wide) + 6378 sizeof(struct iwm_cmd_header)]; 6379 }; 6380 }; 6381 } __packed; 6382 6383 struct iwm_rx_packet { 6384 /* 6385 * The first 4 bytes of the RX frame header contain both the RX frame 6386 * size and some flags. 6387 * Bit fields: 6388 * 31: flag flush RB request 6389 * 30: flag ignore TC (terminal counter) request 6390 * 29: flag fast IRQ request 6391 * 28-14: Reserved 6392 * 13-00: RX frame size 6393 */ 6394 uint32_t len_n_flags; 6395 struct iwm_cmd_header hdr; 6396 uint8_t data[]; 6397 } __packed; 6398 6399 #define IWM_FH_RSCSR_FRAME_SIZE_MSK 0x00003fff 6400 6401 static inline uint32_t 6402 iwm_rx_packet_len(const struct iwm_rx_packet *pkt) 6403 { 6404 6405 return le32toh(pkt->len_n_flags) & IWM_FH_RSCSR_FRAME_SIZE_MSK; 6406 } 6407 6408 static inline uint32_t 6409 iwm_rx_packet_payload_len(const struct iwm_rx_packet *pkt) 6410 { 6411 6412 return iwm_rx_packet_len(pkt) - sizeof(pkt->hdr); 6413 } 6414 6415 6416 #define IWM_MIN_DBM -100 6417 #define IWM_MAX_DBM -33 /* realistic guess */ 6418 6419 #define IWM_READ(sc, reg) \ 6420 bus_space_read_4((sc)->sc_st, (sc)->sc_sh, (reg)) 6421 6422 #define IWM_WRITE(sc, reg, val) \ 6423 bus_space_write_4((sc)->sc_st, (sc)->sc_sh, (reg), (val)) 6424 6425 #define IWM_WRITE_1(sc, reg, val) \ 6426 bus_space_write_1((sc)->sc_st, (sc)->sc_sh, (reg), (val)) 6427 6428 #define IWM_SETBITS(sc, reg, mask) \ 6429 IWM_WRITE(sc, reg, IWM_READ(sc, reg) | (mask)) 6430 6431 #define IWM_CLRBITS(sc, reg, mask) \ 6432 IWM_WRITE(sc, reg, IWM_READ(sc, reg) & ~(mask)) 6433 6434 #define IWM_BARRIER_WRITE(sc) \ 6435 bus_space_barrier((sc)->sc_st, (sc)->sc_sh, 0, (sc)->sc_sz, \ 6436 BUS_SPACE_BARRIER_WRITE) 6437 6438 #define IWM_BARRIER_READ_WRITE(sc) \ 6439 bus_space_barrier((sc)->sc_st, (sc)->sc_sh, 0, (sc)->sc_sz, \ 6440 BUS_SPACE_BARRIER_READ | BUS_SPACE_BARRIER_WRITE) 6441 6442 #endif /* __IF_IWM_REG_H__ */ 6443