1 /* $OpenBSD: if_iwmreg.h,v 1.65 2021/10/11 09:03:22 stsp Exp $ */ 2 3 /****************************************************************************** 4 * 5 * This file is provided under a dual BSD/GPLv2 license. When using or 6 * redistributing this file, you may do so under either license. 7 * 8 * GPL LICENSE SUMMARY 9 * 10 * Copyright(c) 2005 - 2014 Intel Corporation. All rights reserved. 11 * 12 * This program is free software; you can redistribute it and/or modify 13 * it under the terms of version 2 of the GNU General Public License as 14 * published by the Free Software Foundation. 15 * 16 * This program is distributed in the hope that it will be useful, but 17 * WITHOUT ANY WARRANTY; without even the implied warranty of 18 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU 19 * General Public License for more details. 20 * 21 * You should have received a copy of the GNU General Public License 22 * along with this program; if not, write to the Free Software 23 * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110, 24 * USA 25 * 26 * The full GNU General Public License is included in this distribution 27 * in the file called COPYING. 28 * 29 * Contact Information: 30 * Intel Linux Wireless <ilw@linux.intel.com> 31 * Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497 32 * 33 * BSD LICENSE 34 * 35 * Copyright(c) 2005 - 2014 Intel Corporation. All rights reserved. 36 * All rights reserved. 37 * 38 * Redistribution and use in source and binary forms, with or without 39 * modification, are permitted provided that the following conditions 40 * are met: 41 * 42 * * Redistributions of source code must retain the above copyright 43 * notice, this list of conditions and the following disclaimer. 44 * * Redistributions in binary form must reproduce the above copyright 45 * notice, this list of conditions and the following disclaimer in 46 * the documentation and/or other materials provided with the 47 * distribution. 48 * * Neither the name Intel Corporation nor the names of its 49 * contributors may be used to endorse or promote products derived 50 * from this software without specific prior written permission. 51 * 52 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 53 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 54 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 55 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 56 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 57 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 58 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 59 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 60 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 61 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 62 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 63 * 64 *****************************************************************************/ 65 66 #ifndef __IF_IWM_REG_H__ 67 #define __IF_IWM_REG_H__ 68 69 #define le16_to_cpup(_a_) (le16toh(*(const uint16_t *)(_a_))) 70 #define le32_to_cpup(_a_) (le32toh(*(const uint32_t *)(_a_))) 71 72 /* 73 * BEGIN iwl-csr.h 74 */ 75 76 /* 77 * CSR (control and status registers) 78 * 79 * CSR registers are mapped directly into PCI bus space, and are accessible 80 * whenever platform supplies power to device, even when device is in 81 * low power states due to driver-invoked device resets 82 * (e.g. IWM_CSR_RESET_REG_FLAG_SW_RESET) or uCode-driven power-saving modes. 83 * 84 * Use iwl_write32() and iwl_read32() family to access these registers; 85 * these provide simple PCI bus access, without waking up the MAC. 86 * Do not use iwl_write_direct32() family for these registers; 87 * no need to "grab nic access" via IWM_CSR_GP_CNTRL_REG_FLAG_MAC_ACCESS_REQ. 88 * The MAC (uCode processor, etc.) does not need to be powered up for accessing 89 * the CSR registers. 90 * 91 * NOTE: Device does need to be awake in order to read this memory 92 * via IWM_CSR_EEPROM and IWM_CSR_OTP registers 93 */ 94 #define IWM_CSR_HW_IF_CONFIG_REG (0x000) /* hardware interface config */ 95 #define IWM_CSR_INT_COALESCING (0x004) /* accum ints, 32-usec units */ 96 #define IWM_CSR_INT (0x008) /* host interrupt status/ack */ 97 #define IWM_CSR_INT_MASK (0x00c) /* host interrupt enable */ 98 #define IWM_CSR_FH_INT_STATUS (0x010) /* busmaster int status/ack*/ 99 #define IWM_CSR_GPIO_IN (0x018) /* read external chip pins */ 100 #define IWM_CSR_RESET (0x020) /* busmaster enable, NMI, etc*/ 101 #define IWM_CSR_GP_CNTRL (0x024) 102 103 /* 2nd byte of IWM_CSR_INT_COALESCING, not accessible via iwl_write32()! */ 104 #define IWM_CSR_INT_PERIODIC_REG (0x005) 105 106 /* 107 * Hardware revision info 108 * Bit fields: 109 * 31-16: Reserved 110 * 15-4: Type of device: see IWM_CSR_HW_REV_TYPE_xxx definitions 111 * 3-2: Revision step: 0 = A, 1 = B, 2 = C, 3 = D 112 * 1-0: "Dash" (-) value, as in A-1, etc. 113 */ 114 #define IWM_CSR_HW_REV (0x028) 115 116 /* 117 * EEPROM and OTP (one-time-programmable) memory reads 118 * 119 * NOTE: Device must be awake, initialized via apm_ops.init(), 120 * in order to read. 121 */ 122 #define IWM_CSR_EEPROM_REG (0x02c) 123 #define IWM_CSR_EEPROM_GP (0x030) 124 #define IWM_CSR_OTP_GP_REG (0x034) 125 126 #define IWM_CSR_GIO_REG (0x03C) 127 #define IWM_CSR_GP_UCODE_REG (0x048) 128 #define IWM_CSR_GP_DRIVER_REG (0x050) 129 130 /* 131 * UCODE-DRIVER GP (general purpose) mailbox registers. 132 * SET/CLR registers set/clear bit(s) if "1" is written. 133 */ 134 #define IWM_CSR_UCODE_DRV_GP1 (0x054) 135 #define IWM_CSR_UCODE_DRV_GP1_SET (0x058) 136 #define IWM_CSR_UCODE_DRV_GP1_CLR (0x05c) 137 #define IWM_CSR_UCODE_DRV_GP2 (0x060) 138 139 #define IWM_CSR_MBOX_SET_REG (0x088) 140 #define IWM_CSR_MBOX_SET_REG_OS_ALIVE 0x20 141 142 #define IWM_CSR_LED_REG (0x094) 143 #define IWM_CSR_DRAM_INT_TBL_REG (0x0A0) 144 #define IWM_CSR_MAC_SHADOW_REG_CTRL (0x0A8) /* 6000 and up */ 145 146 147 /* GIO Chicken Bits (PCI Express bus link power management) */ 148 #define IWM_CSR_GIO_CHICKEN_BITS (0x100) 149 150 /* Analog phase-lock-loop configuration */ 151 #define IWM_CSR_ANA_PLL_CFG (0x20c) 152 153 /* 154 * CSR Hardware Revision Workaround Register. Indicates hardware rev; 155 * "step" determines CCK backoff for txpower calculation. Used for 4965 only. 156 * See also IWM_CSR_HW_REV register. 157 * Bit fields: 158 * 3-2: 0 = A, 1 = B, 2 = C, 3 = D step 159 * 1-0: "Dash" (-) value, as in C-1, etc. 160 */ 161 #define IWM_CSR_HW_REV_WA_REG (0x22C) 162 163 #define IWM_CSR_DBG_HPET_MEM_REG (0x240) 164 #define IWM_CSR_DBG_LINK_PWR_MGMT_REG (0x250) 165 166 /* Bits for IWM_CSR_HW_IF_CONFIG_REG */ 167 #define IWM_CSR_HW_IF_CONFIG_REG_MSK_MAC_DASH (0x00000003) 168 #define IWM_CSR_HW_IF_CONFIG_REG_MSK_MAC_STEP (0x0000000C) 169 #define IWM_CSR_HW_IF_CONFIG_REG_MSK_BOARD_VER (0x000000C0) 170 #define IWM_CSR_HW_IF_CONFIG_REG_BIT_MAC_SI (0x00000100) 171 #define IWM_CSR_HW_IF_CONFIG_REG_BIT_RADIO_SI (0x00000200) 172 #define IWM_CSR_HW_IF_CONFIG_REG_MSK_PHY_TYPE (0x00000C00) 173 #define IWM_CSR_HW_IF_CONFIG_REG_MSK_PHY_DASH (0x00003000) 174 #define IWM_CSR_HW_IF_CONFIG_REG_MSK_PHY_STEP (0x0000C000) 175 176 #define IWM_CSR_HW_IF_CONFIG_REG_POS_MAC_DASH (0) 177 #define IWM_CSR_HW_IF_CONFIG_REG_POS_MAC_STEP (2) 178 #define IWM_CSR_HW_IF_CONFIG_REG_POS_BOARD_VER (6) 179 #define IWM_CSR_HW_IF_CONFIG_REG_POS_PHY_TYPE (10) 180 #define IWM_CSR_HW_IF_CONFIG_REG_POS_PHY_DASH (12) 181 #define IWM_CSR_HW_IF_CONFIG_REG_POS_PHY_STEP (14) 182 183 #define IWM_CSR_HW_IF_CONFIG_REG_BIT_HAP_WAKE_L1A (0x00080000) 184 #define IWM_CSR_HW_IF_CONFIG_REG_BIT_EEPROM_OWN_SEM (0x00200000) 185 #define IWM_CSR_HW_IF_CONFIG_REG_BIT_NIC_READY (0x00400000) /* PCI_OWN_SEM */ 186 #define IWM_CSR_HW_IF_CONFIG_REG_BIT_NIC_PREPARE_DONE (0x02000000) /* ME_OWN */ 187 #define IWM_CSR_HW_IF_CONFIG_REG_PREPARE (0x08000000) /* WAKE_ME */ 188 #define IWM_CSR_HW_IF_CONFIG_REG_ENABLE_PME (0x10000000) 189 #define IWM_CSR_HW_IF_CONFIG_REG_PERSIST_MODE (0x40000000) /* PERSISTENCE */ 190 191 #define IWM_CSR_INT_PERIODIC_DIS (0x00) /* disable periodic int*/ 192 #define IWM_CSR_INT_PERIODIC_ENA (0xFF) /* 255*32 usec ~ 8 msec*/ 193 194 /* interrupt flags in INTA, set by uCode or hardware (e.g. dma), 195 * acknowledged (reset) by host writing "1" to flagged bits. */ 196 #define IWM_CSR_INT_BIT_FH_RX (1U << 31) /* Rx DMA, cmd responses, FH_INT[17:16] */ 197 #define IWM_CSR_INT_BIT_HW_ERR (1 << 29) /* DMA hardware error FH_INT[31] */ 198 #define IWM_CSR_INT_BIT_RX_PERIODIC (1 << 28) /* Rx periodic */ 199 #define IWM_CSR_INT_BIT_FH_TX (1 << 27) /* Tx DMA FH_INT[1:0] */ 200 #define IWM_CSR_INT_BIT_SCD (1 << 26) /* TXQ pointer advanced */ 201 #define IWM_CSR_INT_BIT_SW_ERR (1 << 25) /* uCode error */ 202 #define IWM_CSR_INT_BIT_RF_KILL (1 << 7) /* HW RFKILL switch GP_CNTRL[27] toggled */ 203 #define IWM_CSR_INT_BIT_CT_KILL (1 << 6) /* Critical temp (chip too hot) rfkill */ 204 #define IWM_CSR_INT_BIT_SW_RX (1 << 3) /* Rx, command responses */ 205 #define IWM_CSR_INT_BIT_WAKEUP (1 << 1) /* NIC controller waking up (pwr mgmt) */ 206 #define IWM_CSR_INT_BIT_ALIVE (1 << 0) /* uCode interrupts once it initializes */ 207 208 #define IWM_CSR_INI_SET_MASK (IWM_CSR_INT_BIT_FH_RX | \ 209 IWM_CSR_INT_BIT_HW_ERR | \ 210 IWM_CSR_INT_BIT_FH_TX | \ 211 IWM_CSR_INT_BIT_SW_ERR | \ 212 IWM_CSR_INT_BIT_RF_KILL | \ 213 IWM_CSR_INT_BIT_SW_RX | \ 214 IWM_CSR_INT_BIT_WAKEUP | \ 215 IWM_CSR_INT_BIT_ALIVE | \ 216 IWM_CSR_INT_BIT_RX_PERIODIC) 217 218 /* interrupt flags in FH (flow handler) (PCI busmaster DMA) */ 219 #define IWM_CSR_FH_INT_BIT_ERR (1U << 31) /* Error */ 220 #define IWM_CSR_FH_INT_BIT_HI_PRIOR (1 << 30) /* High priority Rx, bypass coalescing */ 221 #define IWM_CSR_FH_INT_BIT_RX_CHNL1 (1 << 17) /* Rx channel 1 */ 222 #define IWM_CSR_FH_INT_BIT_RX_CHNL0 (1 << 16) /* Rx channel 0 */ 223 #define IWM_CSR_FH_INT_BIT_TX_CHNL1 (1 << 1) /* Tx channel 1 */ 224 #define IWM_CSR_FH_INT_BIT_TX_CHNL0 (1 << 0) /* Tx channel 0 */ 225 226 #define IWM_CSR_FH_INT_RX_MASK (IWM_CSR_FH_INT_BIT_HI_PRIOR | \ 227 IWM_CSR_FH_INT_BIT_RX_CHNL1 | \ 228 IWM_CSR_FH_INT_BIT_RX_CHNL0) 229 230 #define IWM_CSR_FH_INT_TX_MASK (IWM_CSR_FH_INT_BIT_TX_CHNL1 | \ 231 IWM_CSR_FH_INT_BIT_TX_CHNL0) 232 233 /* GPIO */ 234 #define IWM_CSR_GPIO_IN_BIT_AUX_POWER (0x00000200) 235 #define IWM_CSR_GPIO_IN_VAL_VAUX_PWR_SRC (0x00000000) 236 #define IWM_CSR_GPIO_IN_VAL_VMAIN_PWR_SRC (0x00000200) 237 238 /* RESET */ 239 #define IWM_CSR_RESET_REG_FLAG_NEVO_RESET (0x00000001) 240 #define IWM_CSR_RESET_REG_FLAG_FORCE_NMI (0x00000002) 241 #define IWM_CSR_RESET_REG_FLAG_SW_RESET (0x00000080) 242 #define IWM_CSR_RESET_REG_FLAG_MASTER_DISABLED (0x00000100) 243 #define IWM_CSR_RESET_REG_FLAG_STOP_MASTER (0x00000200) 244 #define IWM_CSR_RESET_LINK_PWR_MGMT_DISABLED (0x80000000) 245 246 /* 247 * GP (general purpose) CONTROL REGISTER 248 * Bit fields: 249 * 27: HW_RF_KILL_SW 250 * Indicates state of (platform's) hardware RF-Kill switch 251 * 26-24: POWER_SAVE_TYPE 252 * Indicates current power-saving mode: 253 * 000 -- No power saving 254 * 001 -- MAC power-down 255 * 010 -- PHY (radio) power-down 256 * 011 -- Error 257 * 9-6: SYS_CONFIG 258 * Indicates current system configuration, reflecting pins on chip 259 * as forced high/low by device circuit board. 260 * 4: GOING_TO_SLEEP 261 * Indicates MAC is entering a power-saving sleep power-down. 262 * Not a good time to access device-internal resources. 263 * 3: MAC_ACCESS_REQ 264 * Host sets this to request and maintain MAC wakeup, to allow host 265 * access to device-internal resources. Host must wait for 266 * MAC_CLOCK_READY (and !GOING_TO_SLEEP) before accessing non-CSR 267 * device registers. 268 * 2: INIT_DONE 269 * Host sets this to put device into fully operational D0 power mode. 270 * Host resets this after SW_RESET to put device into low power mode. 271 * 0: MAC_CLOCK_READY 272 * Indicates MAC (ucode processor, etc.) is powered up and can run. 273 * Internal resources are accessible. 274 * NOTE: This does not indicate that the processor is actually running. 275 * NOTE: This does not indicate that device has completed 276 * init or post-power-down restore of internal SRAM memory. 277 * Use IWM_CSR_UCODE_DRV_GP1_BIT_MAC_SLEEP as indication that 278 * SRAM is restored and uCode is in normal operation mode. 279 * Later devices (5xxx/6xxx/1xxx) use non-volatile SRAM, and 280 * do not need to save/restore it. 281 * NOTE: After device reset, this bit remains "0" until host sets 282 * INIT_DONE 283 */ 284 #define IWM_CSR_GP_CNTRL_REG_FLAG_MAC_CLOCK_READY (0x00000001) 285 #define IWM_CSR_GP_CNTRL_REG_FLAG_INIT_DONE (0x00000004) 286 #define IWM_CSR_GP_CNTRL_REG_FLAG_MAC_ACCESS_REQ (0x00000008) 287 #define IWM_CSR_GP_CNTRL_REG_FLAG_GOING_TO_SLEEP (0x00000010) 288 289 #define IWM_CSR_GP_CNTRL_REG_VAL_MAC_ACCESS_EN (0x00000001) 290 291 #define IWM_CSR_GP_CNTRL_REG_MSK_POWER_SAVE_TYPE (0x07000000) 292 #define IWM_CSR_GP_CNTRL_REG_FLAG_RFKILL_WAKE_L1A_EN (0x04000000) 293 #define IWM_CSR_GP_CNTRL_REG_FLAG_HW_RF_KILL_SW (0x08000000) 294 295 296 /* HW REV */ 297 #define IWM_CSR_HW_REV_DASH(_val) (((_val) & 0x0000003) >> 0) 298 #define IWM_CSR_HW_REV_STEP(_val) (((_val) & 0x000000C) >> 2) 299 300 /** 301 * hw_rev values 302 */ 303 enum { 304 IWM_SILICON_A_STEP = 0, 305 IWM_SILICON_B_STEP, 306 IWM_SILICON_C_STEP, 307 }; 308 309 #define IWM_CSR_HW_REV_TYPE_MSK (0x000FFF0) 310 #define IWM_CSR_HW_REV_TYPE_5300 (0x0000020) 311 #define IWM_CSR_HW_REV_TYPE_5350 (0x0000030) 312 #define IWM_CSR_HW_REV_TYPE_5100 (0x0000050) 313 #define IWM_CSR_HW_REV_TYPE_5150 (0x0000040) 314 #define IWM_CSR_HW_REV_TYPE_1000 (0x0000060) 315 #define IWM_CSR_HW_REV_TYPE_6x00 (0x0000070) 316 #define IWM_CSR_HW_REV_TYPE_6x50 (0x0000080) 317 #define IWM_CSR_HW_REV_TYPE_6150 (0x0000084) 318 #define IWM_CSR_HW_REV_TYPE_6x05 (0x00000B0) 319 #define IWM_CSR_HW_REV_TYPE_6x30 IWM_CSR_HW_REV_TYPE_6x05 320 #define IWM_CSR_HW_REV_TYPE_6x35 IWM_CSR_HW_REV_TYPE_6x05 321 #define IWM_CSR_HW_REV_TYPE_2x30 (0x00000C0) 322 #define IWM_CSR_HW_REV_TYPE_2x00 (0x0000100) 323 #define IWM_CSR_HW_REV_TYPE_105 (0x0000110) 324 #define IWM_CSR_HW_REV_TYPE_135 (0x0000120) 325 #define IWM_CSR_HW_REV_TYPE_7265D (0x0000210) 326 #define IWM_CSR_HW_REV_TYPE_NONE (0x00001F0) 327 328 /* EEPROM REG */ 329 #define IWM_CSR_EEPROM_REG_READ_VALID_MSK (0x00000001) 330 #define IWM_CSR_EEPROM_REG_BIT_CMD (0x00000002) 331 #define IWM_CSR_EEPROM_REG_MSK_ADDR (0x0000FFFC) 332 #define IWM_CSR_EEPROM_REG_MSK_DATA (0xFFFF0000) 333 334 /* EEPROM GP */ 335 #define IWM_CSR_EEPROM_GP_VALID_MSK (0x00000007) /* signature */ 336 #define IWM_CSR_EEPROM_GP_IF_OWNER_MSK (0x00000180) 337 #define IWM_CSR_EEPROM_GP_BAD_SIGNATURE_BOTH_EEP_AND_OTP (0x00000000) 338 #define IWM_CSR_EEPROM_GP_BAD_SIG_EEP_GOOD_SIG_OTP (0x00000001) 339 #define IWM_CSR_EEPROM_GP_GOOD_SIG_EEP_LESS_THAN_4K (0x00000002) 340 #define IWM_CSR_EEPROM_GP_GOOD_SIG_EEP_MORE_THAN_4K (0x00000004) 341 342 /* One-time-programmable memory general purpose reg */ 343 #define IWM_CSR_OTP_GP_REG_DEVICE_SELECT (0x00010000) /* 0 - EEPROM, 1 - OTP */ 344 #define IWM_CSR_OTP_GP_REG_OTP_ACCESS_MODE (0x00020000) /* 0 - absolute, 1 - relative */ 345 #define IWM_CSR_OTP_GP_REG_ECC_CORR_STATUS_MSK (0x00100000) /* bit 20 */ 346 #define IWM_CSR_OTP_GP_REG_ECC_UNCORR_STATUS_MSK (0x00200000) /* bit 21 */ 347 348 /* GP REG */ 349 #define IWM_CSR_GP_REG_POWER_SAVE_STATUS_MSK (0x03000000) /* bit 24/25 */ 350 #define IWM_CSR_GP_REG_NO_POWER_SAVE (0x00000000) 351 #define IWM_CSR_GP_REG_MAC_POWER_SAVE (0x01000000) 352 #define IWM_CSR_GP_REG_PHY_POWER_SAVE (0x02000000) 353 #define IWM_CSR_GP_REG_POWER_SAVE_ERROR (0x03000000) 354 355 356 /* CSR GIO */ 357 #define IWM_CSR_GIO_REG_VAL_L0S_ENABLED (0x00000002) 358 359 /* 360 * UCODE-DRIVER GP (general purpose) mailbox register 1 361 * Host driver and uCode write and/or read this register to communicate with 362 * each other. 363 * Bit fields: 364 * 4: UCODE_DISABLE 365 * Host sets this to request permanent halt of uCode, same as 366 * sending CARD_STATE command with "halt" bit set. 367 * 3: CT_KILL_EXIT 368 * Host sets this to request exit from CT_KILL state, i.e. host thinks 369 * device temperature is low enough to continue normal operation. 370 * 2: CMD_BLOCKED 371 * Host sets this during RF KILL power-down sequence (HW, SW, CT KILL) 372 * to release uCode to clear all Tx and command queues, enter 373 * unassociated mode, and power down. 374 * NOTE: Some devices also use HBUS_TARG_MBX_C register for this bit. 375 * 1: SW_BIT_RFKILL 376 * Host sets this when issuing CARD_STATE command to request 377 * device sleep. 378 * 0: MAC_SLEEP 379 * uCode sets this when preparing a power-saving power-down. 380 * uCode resets this when power-up is complete and SRAM is sane. 381 * NOTE: device saves internal SRAM data to host when powering down, 382 * and must restore this data after powering back up. 383 * MAC_SLEEP is the best indication that restore is complete. 384 * Later devices (5xxx/6xxx/1xxx) use non-volatile SRAM, and 385 * do not need to save/restore it. 386 */ 387 #define IWM_CSR_UCODE_DRV_GP1_BIT_MAC_SLEEP (0x00000001) 388 #define IWM_CSR_UCODE_SW_BIT_RFKILL (0x00000002) 389 #define IWM_CSR_UCODE_DRV_GP1_BIT_CMD_BLOCKED (0x00000004) 390 #define IWM_CSR_UCODE_DRV_GP1_REG_BIT_CT_KILL_EXIT (0x00000008) 391 #define IWM_CSR_UCODE_DRV_GP1_BIT_D3_CFG_COMPLETE (0x00000020) 392 393 /* GP Driver */ 394 #define IWM_CSR_GP_DRIVER_REG_BIT_RADIO_SKU_MSK (0x00000003) 395 #define IWM_CSR_GP_DRIVER_REG_BIT_RADIO_SKU_3x3_HYB (0x00000000) 396 #define IWM_CSR_GP_DRIVER_REG_BIT_RADIO_SKU_2x2_HYB (0x00000001) 397 #define IWM_CSR_GP_DRIVER_REG_BIT_RADIO_SKU_2x2_IPA (0x00000002) 398 #define IWM_CSR_GP_DRIVER_REG_BIT_CALIB_VERSION6 (0x00000004) 399 #define IWM_CSR_GP_DRIVER_REG_BIT_6050_1x2 (0x00000008) 400 401 #define IWM_CSR_GP_DRIVER_REG_BIT_RADIO_IQ_INVER (0x00000080) 402 403 /* GIO Chicken Bits (PCI Express bus link power management) */ 404 #define IWM_CSR_GIO_CHICKEN_BITS_REG_BIT_L1A_NO_L0S_RX (0x00800000) 405 #define IWM_CSR_GIO_CHICKEN_BITS_REG_BIT_DIS_L0S_EXIT_TIMER (0x20000000) 406 407 /* LED */ 408 #define IWM_CSR_LED_BSM_CTRL_MSK (0xFFFFFFDF) 409 #define IWM_CSR_LED_REG_TURN_ON (0x60) 410 #define IWM_CSR_LED_REG_TURN_OFF (0x20) 411 412 /* ANA_PLL */ 413 #define IWM_CSR50_ANA_PLL_CFG_VAL (0x00880300) 414 415 /* HPET MEM debug */ 416 #define IWM_CSR_DBG_HPET_MEM_REG_VAL (0xFFFF0000) 417 418 /* DRAM INT TABLE */ 419 #define IWM_CSR_DRAM_INT_TBL_ENABLE (1U << 31) 420 #define IWM_CSR_DRAM_INIT_TBL_WRITE_POINTER (1 << 28) 421 #define IWM_CSR_DRAM_INIT_TBL_WRAP_CHECK (1 << 27) 422 423 /* SECURE boot registers */ 424 #define IWM_CSR_SECURE_BOOT_CONFIG_ADDR (0x100) 425 #define IWM_CSR_SECURE_BOOT_CONFIG_INSPECTOR_BURNED_IN_OTP 0x00000001 426 #define IWM_CSR_SECURE_BOOT_CONFIG_INSPECTOR_NOT_REQ 0x00000002 427 #define IWM_CSR_SECURE_BOOT_CPU1_STATUS_ADDR (0x100) 428 #define IWM_CSR_SECURE_BOOT_CPU2_STATUS_ADDR (0x100) 429 #define IWM_CSR_SECURE_BOOT_CPU_STATUS_VERF_STATUS 0x00000003 430 #define IWM_CSR_SECURE_BOOT_CPU_STATUS_VERF_COMPLETED 0x00000002 431 #define IWM_CSR_SECURE_BOOT_CPU_STATUS_VERF_SUCCESS 0x00000004 432 #define IWM_CSR_SECURE_BOOT_CPU_STATUS_VERF_FAIL 0x00000008 433 #define IWM_CSR_SECURE_BOOT_CPU_STATUS_SIGN_VERF_FAIL 0x00000010 434 435 #define IWM_FH_UCODE_LOAD_STATUS 0x1af0 436 437 #define IWM_FH_MEM_TB_MAX_LENGTH 0x20000 438 439 /* 9000 rx series registers */ 440 441 #define IWM_RFH_Q0_FRBDCB_BA_LSB 0xA08000 /* 64 bit address */ 442 #define IWM_RFH_Q_FRBDCB_BA_LSB(q) (IWM_RFH_Q0_FRBDCB_BA_LSB + (q) * 8) 443 /* Write index table */ 444 #define IWM_RFH_Q0_FRBDCB_WIDX 0xA08080 445 #define IWM_RFH_Q_FRBDCB_WIDX(q) (IWM_RFH_Q0_FRBDCB_WIDX + (q) * 4) 446 /* Write index table - shadow registers */ 447 #define IWM_RFH_Q0_FRBDCB_WIDX_TRG 0x1C80 448 #define IWM_RFH_Q_FRBDCB_WIDX_TRG(q) (IWM_RFH_Q0_FRBDCB_WIDX_TRG + (q) * 4) 449 /* Read index table */ 450 #define IWM_RFH_Q0_FRBDCB_RIDX 0xA080C0 451 #define IWM_RFH_Q_FRBDCB_RIDX(q) (IWM_RFH_Q0_FRBDCB_RIDX + (q) * 4) 452 /* Used list table */ 453 #define IWM_RFH_Q0_URBDCB_BA_LSB 0xA08100 /* 64 bit address */ 454 #define IWM_RFH_Q_URBDCB_BA_LSB(q) (IWM_RFH_Q0_URBDCB_BA_LSB + (q) * 8) 455 /* Write index table */ 456 #define IWM_RFH_Q0_URBDCB_WIDX 0xA08180 457 #define IWM_RFH_Q_URBDCB_WIDX(q) (IWM_RFH_Q0_URBDCB_WIDX + (q) * 4) 458 #define IWM_RFH_Q0_URBDCB_VAID 0xA081C0 459 #define IWM_RFH_Q_URBDCB_VAID(q) (IWM_RFH_Q0_URBDCB_VAID + (q) * 4) 460 /* stts */ 461 #define IWM_RFH_Q0_URBD_STTS_WPTR_LSB 0xA08200 /*64 bits address */ 462 #define IWM_RFH_Q_URBD_STTS_WPTR_LSB(q) (IWM_RFH_Q0_URBD_STTS_WPTR_LSB + (q) * 8) 463 464 #define IWM_RFH_Q0_ORB_WPTR_LSB 0xA08280 465 #define IWM_RFH_Q_ORB_WPTR_LSB(q) (IWM_RFH_Q0_ORB_WPTR_LSB + (q) * 8) 466 #define IWM_RFH_RBDBUF_RBD0_LSB 0xA08300 467 #define IWM_RFH_RBDBUF_RBD_LSB(q) (IWM_RFH_RBDBUF_RBD0_LSB + (q) * 8) 468 469 /** 470 * RFH Status Register 471 * 472 * Bit fields: 473 * 474 * Bit 29: RBD_FETCH_IDLE 475 * This status flag is set by the RFH when there is no active RBD fetch from 476 * DRAM. 477 * Once the RFH RBD controller starts fetching (or when there is a pending 478 * RBD read response from DRAM), this flag is immediately turned off. 479 * 480 * Bit 30: SRAM_DMA_IDLE 481 * This status flag is set by the RFH when there is no active transaction from 482 * SRAM to DRAM. 483 * Once the SRAM to DRAM DMA is active, this flag is immediately turned off. 484 * 485 * Bit 31: RXF_DMA_IDLE 486 * This status flag is set by the RFH when there is no active transaction from 487 * RXF to DRAM. 488 * Once the RXF-to-DRAM DMA is active, this flag is immediately turned off. 489 */ 490 #define IWM_RFH_GEN_STATUS 0xA09808 491 #define IWM_RFH_GEN_STATUS_GEN3 0xA07824 492 #define IWM_RBD_FETCH_IDLE (1 << 29) 493 #define IWM_SRAM_DMA_IDLE (1 << 30) 494 #define IWM_RXF_DMA_IDLE (1U << 31) 495 496 /* DMA configuration */ 497 #define IWM_RFH_RXF_DMA_CFG 0xA09820 498 #define IWM_RFH_RXF_DMA_CFG_GEN3 0xA07880 499 /* RB size */ 500 #define IWM_RFH_RXF_DMA_RB_SIZE_MASK (0x000F0000) /* bits 16-19 */ 501 #define IWM_RFH_RXF_DMA_RB_SIZE_POS 16 502 #define IWM_RFH_RXF_DMA_RB_SIZE_1K (0x1 << IWM_RFH_RXF_DMA_RB_SIZE_POS) 503 #define IWM_RFH_RXF_DMA_RB_SIZE_2K (0x2 << IWM_RFH_RXF_DMA_RB_SIZE_POS) 504 #define IWM_RFH_RXF_DMA_RB_SIZE_4K (0x4 << IWM_RFH_RXF_DMA_RB_SIZE_POS) 505 #define IWM_RFH_RXF_DMA_RB_SIZE_8K (0x8 << IWM_RFH_RXF_DMA_RB_SIZE_POS) 506 #define IWM_RFH_RXF_DMA_RB_SIZE_12K (0x9 << IWM_RFH_RXF_DMA_RB_SIZE_POS) 507 #define IWM_RFH_RXF_DMA_RB_SIZE_16K (0xA << IWM_RFH_RXF_DMA_RB_SIZE_POS) 508 #define IWM_RFH_RXF_DMA_RB_SIZE_20K (0xB << IWM_RFH_RXF_DMA_RB_SIZE_POS) 509 #define IWM_RFH_RXF_DMA_RB_SIZE_24K (0xC << IWM_RFH_RXF_DMA_RB_SIZE_POS) 510 #define IWM_RFH_RXF_DMA_RB_SIZE_28K (0xD << IWM_RFH_RXF_DMA_RB_SIZE_POS) 511 #define IWM_RFH_RXF_DMA_RB_SIZE_32K (0xE << IWM_RFH_RXF_DMA_RB_SIZE_POS) 512 /* RB Circular Buffer size:defines the table sizes in RBD units */ 513 #define IWM_RFH_RXF_DMA_RBDCB_SIZE_MASK (0x00F00000) /* bits 20-23 */ 514 #define IWM_RFH_RXF_DMA_RBDCB_SIZE_POS 20 515 #define IWM_RFH_RXF_DMA_RBDCB_SIZE_8 (0x3 << IWM_RFH_RXF_DMA_RBDCB_SIZE_POS) 516 #define IWM_RFH_RXF_DMA_RBDCB_SIZE_16 (0x4 << IWM_RFH_RXF_DMA_RBDCB_SIZE_POS) 517 #define IWM_RFH_RXF_DMA_RBDCB_SIZE_32 (0x5 << IWM_RFH_RXF_DMA_RBDCB_SIZE_POS) 518 #define IWM_RFH_RXF_DMA_RBDCB_SIZE_64 (0x7 << IWM_RFH_RXF_DMA_RBDCB_SIZE_POS) 519 #define IWM_RFH_RXF_DMA_RBDCB_SIZE_128 (0x7 << IWM_RFH_RXF_DMA_RBDCB_SIZE_POS) 520 #define IWM_RFH_RXF_DMA_RBDCB_SIZE_256 (0x8 << IWM_RFH_RXF_DMA_RBDCB_SIZE_POS) 521 #define IWM_RFH_RXF_DMA_RBDCB_SIZE_512 (0x9 << IWM_RFH_RXF_DMA_RBDCB_SIZE_POS) 522 #define IWM_RFH_RXF_DMA_RBDCB_SIZE_1024 (0xA << IWM_RFH_RXF_DMA_RBDCB_SIZE_POS) 523 #define IWM_RFH_RXF_DMA_RBDCB_SIZE_2048 (0xB << IWM_RFH_RXF_DMA_RBDCB_SIZE_POS) 524 #define IWM_RFH_RXF_DMA_MIN_RB_SIZE_MASK (0x03000000) /* bit 24-25 */ 525 #define IWM_RFH_RXF_DMA_MIN_RB_SIZE_POS 24 526 #define IWM_RFH_RXF_DMA_MIN_RB_4_8 (3 << IWM_RFH_RXF_DMA_MIN_RB_SIZE_POS) 527 #define IWM_RFH_RXF_DMA_DROP_TOO_LARGE_MASK (0x04000000) /* bit 26 */ 528 #define IWM_RFH_RXF_DMA_SINGLE_FRAME_MASK (0x20000000) /* bit 29 */ 529 #define IWM_RFH_DMA_EN_MASK (0xC0000000) /* bits 30-31*/ 530 #define IWM_RFH_DMA_EN_ENABLE_VAL (1U << 31) 531 532 #define IWM_RFH_RXF_RXQ_ACTIVE 0xA0980C 533 534 #define IWM_RFH_GEN_CFG 0xA09800 535 #define IWM_RFH_GEN_CFG_SERVICE_DMA_SNOOP (1 << 0) 536 #define IWM_RFH_GEN_CFG_RFH_DMA_SNOOP (1 << 1) 537 #define IWM_RFH_GEN_CFG_RB_CHUNK_SIZE_128 0x00000010 538 #define IWM_RFH_GEN_CFG_RB_CHUNK_SIZE_64 0x00000000 539 /* the driver assumes everywhere that the default RXQ is 0 */ 540 #define IWM_RFH_GEN_CFG_DEFAULT_RXQ_NUM 0xF00 541 542 /* end of 9000 rx series registers */ 543 544 #define IWM_LMPM_SECURE_UCODE_LOAD_CPU1_HDR_ADDR 0x1e78 545 #define IWM_LMPM_SECURE_UCODE_LOAD_CPU2_HDR_ADDR 0x1e7c 546 547 #define IWM_LMPM_SECURE_CPU1_HDR_MEM_SPACE 0x420000 548 #define IWM_LMPM_SECURE_CPU2_HDR_MEM_SPACE 0x420400 549 550 #define IWM_CSR_SECURE_TIME_OUT (100) 551 552 /* extended range in FW SRAM */ 553 #define IWM_FW_MEM_EXTENDED_START 0x40000 554 #define IWM_FW_MEM_EXTENDED_END 0x57FFF 555 556 /* FW chicken bits */ 557 #define IWM_LMPM_CHICK 0xa01ff8 558 #define IWM_LMPM_CHICK_EXTENDED_ADDR_SPACE 0x01 559 560 #define IWM_FH_TCSR_0_REG0 (0x1D00) 561 562 /* 563 * HBUS (Host-side Bus) 564 * 565 * HBUS registers are mapped directly into PCI bus space, but are used 566 * to indirectly access device's internal memory or registers that 567 * may be powered-down. 568 * 569 * Use iwl_write_direct32()/iwl_read_direct32() family for these registers; 570 * host must "grab nic access" via CSR_GP_CNTRL_REG_FLAG_MAC_ACCESS_REQ 571 * to make sure the MAC (uCode processor, etc.) is powered up for accessing 572 * internal resources. 573 * 574 * Do not use iwl_write32()/iwl_read32() family to access these registers; 575 * these provide only simple PCI bus access, without waking up the MAC. 576 */ 577 #define IWM_HBUS_BASE (0x400) 578 579 /* 580 * Registers for accessing device's internal SRAM memory (e.g. SCD SRAM 581 * structures, error log, event log, verifying uCode load). 582 * First write to address register, then read from or write to data register 583 * to complete the job. Once the address register is set up, accesses to 584 * data registers auto-increment the address by one dword. 585 * Bit usage for address registers (read or write): 586 * 0-31: memory address within device 587 */ 588 #define IWM_HBUS_TARG_MEM_RADDR (IWM_HBUS_BASE+0x00c) 589 #define IWM_HBUS_TARG_MEM_WADDR (IWM_HBUS_BASE+0x010) 590 #define IWM_HBUS_TARG_MEM_WDAT (IWM_HBUS_BASE+0x018) 591 #define IWM_HBUS_TARG_MEM_RDAT (IWM_HBUS_BASE+0x01c) 592 593 /* Mailbox C, used as workaround alternative to CSR_UCODE_DRV_GP1 mailbox */ 594 #define IWM_HBUS_TARG_MBX_C (IWM_HBUS_BASE+0x030) 595 #define IWM_HBUS_TARG_MBX_C_REG_BIT_CMD_BLOCKED (0x00000004) 596 597 /* 598 * Registers for accessing device's internal peripheral registers 599 * (e.g. SCD, BSM, etc.). First write to address register, 600 * then read from or write to data register to complete the job. 601 * Bit usage for address registers (read or write): 602 * 0-15: register address (offset) within device 603 * 24-25: (# bytes - 1) to read or write (e.g. 3 for dword) 604 */ 605 #define IWM_HBUS_TARG_PRPH_WADDR (IWM_HBUS_BASE+0x044) 606 #define IWM_HBUS_TARG_PRPH_RADDR (IWM_HBUS_BASE+0x048) 607 #define IWM_HBUS_TARG_PRPH_WDAT (IWM_HBUS_BASE+0x04c) 608 #define IWM_HBUS_TARG_PRPH_RDAT (IWM_HBUS_BASE+0x050) 609 610 /* enable the ID buf for read */ 611 #define IWM_WFPM_PS_CTL_CLR 0xa0300c 612 #define IWM_WFMP_MAC_ADDR_0 0xa03080 613 #define IWM_WFMP_MAC_ADDR_1 0xa03084 614 #define IWM_LMPM_PMG_EN 0xa01cec 615 #define IWM_RADIO_REG_SYS_MANUAL_DFT_0 0xad4078 616 #define IWM_RFIC_REG_RD 0xad0470 617 #define IWM_WFPM_CTRL_REG 0xa03030 618 #define IWM_WFPM_AUX_CTL_AUX_IF_MAC_OWNER_MSK 0x08000000 619 #define IWM_ENABLE_WFPM 0x80000000 620 621 #define IWM_AUX_MISC_REG 0xa200b0 622 #define IWM_HW_STEP_LOCATION_BITS 24 623 624 #define IWM_AUX_MISC_MASTER1_EN 0xa20818 625 #define IWM_AUX_MISC_MASTER1_EN_SBE_MSK 0x1 626 #define IWM_AUX_MISC_MASTER1_SMPHR_STATUS 0xa20800 627 #define IWM_RSA_ENABLE 0xa24b08 628 #define IWM_PREG_AUX_BUS_WPROT_0 0xa04cc0 629 #define IWM_PREG_PRPH_WPROT_9000 0xa04ce0 630 #define IWM_PREG_PRPH_WPROT_22000 0xa04d00 631 #define IWM_SB_CFG_OVERRIDE_ADDR 0xa26c78 632 #define IWM_SB_CFG_OVERRIDE_ENABLE 0x8000 633 #define IWM_SB_CFG_BASE_OVERRIDE 0xa20000 634 #define IWM_SB_MODIFY_CFG_FLAG 0xa03088 635 #define IWM_SB_CPU_1_STATUS 0xa01e30 636 #define IWM_SB_CPU_2_STATUS 0Xa01e34 637 638 #define IWM_UREG_CHICK 0xa05c00 639 #define IWM_UREG_CHICK_MSI_ENABLE (1 << 24) 640 #define IWM_UREG_CHICK_MSIX_ENABLE (1 << 25) 641 642 #define IWM_HPM_DEBUG 0xa03440 643 #define IWM_HPM_PERSISTENCE_BIT (1 << 12) 644 #define IWM_PREG_WFPM_ACCESS (1 << 12) 645 646 /* Used to enable DBGM */ 647 #define IWM_HBUS_TARG_TEST_REG (IWM_HBUS_BASE+0x05c) 648 649 /* 650 * Per-Tx-queue write pointer (index, really!) 651 * Indicates index to next TFD that driver will fill (1 past latest filled). 652 * Bit usage: 653 * 0-7: queue write index 654 * 11-8: queue selector 655 */ 656 #define IWM_HBUS_TARG_WRPTR (IWM_HBUS_BASE+0x060) 657 658 /********************************************************** 659 * CSR values 660 **********************************************************/ 661 /* 662 * host interrupt timeout value 663 * used with setting interrupt coalescing timer 664 * the CSR_INT_COALESCING is an 8 bit register in 32-usec unit 665 * 666 * default interrupt coalescing timer is 64 x 32 = 2048 usecs 667 */ 668 #define IWM_HOST_INT_TIMEOUT_MAX (0xFF) 669 #define IWM_HOST_INT_TIMEOUT_DEF (0x40) 670 #define IWM_HOST_INT_TIMEOUT_MIN (0x0) 671 #define IWM_HOST_INT_OPER_MODE (1U << 31) 672 673 /***************************************************************************** 674 * 7000/3000 series SHR DTS addresses * 675 *****************************************************************************/ 676 677 /* Diode Results Register Structure: */ 678 #define IWM_DTS_DIODE_REG_DIG_VAL 0x000000FF /* bits [7:0] */ 679 #define IWM_DTS_DIODE_REG_VREF_LOW 0x0000FF00 /* bits [15:8] */ 680 #define IWM_DTS_DIODE_REG_VREF_HIGH 0x00FF0000 /* bits [23:16] */ 681 #define IWM_DTS_DIODE_REG_VREF_ID 0x03000000 /* bits [25:24] */ 682 #define IWM_DTS_DIODE_REG_PASS_ONCE 0x80000000 /* bits [31:31] */ 683 #define IWM_DTS_DIODE_REG_FLAGS_MSK 0xFF000000 /* bits [31:24] */ 684 /* Those are the masks INSIDE the flags bit-field: */ 685 #define IWM_DTS_DIODE_REG_FLAGS_VREFS_ID_POS 0 686 #define IWM_DTS_DIODE_REG_FLAGS_VREFS_ID 0x00000003 /* bits [1:0] */ 687 #define IWM_DTS_DIODE_REG_FLAGS_PASS_ONCE_POS 7 688 #define IWM_DTS_DIODE_REG_FLAGS_PASS_ONCE 0x00000080 /* bits [7:7] */ 689 690 /***************************************************************************** 691 * MSIX related registers * 692 *****************************************************************************/ 693 694 #define IWM_CSR_MSIX_BASE (0x2000) 695 #define IWM_CSR_MSIX_FH_INT_CAUSES_AD (IWM_CSR_MSIX_BASE + 0x800) 696 #define IWM_CSR_MSIX_FH_INT_MASK_AD (IWM_CSR_MSIX_BASE + 0x804) 697 #define IWM_CSR_MSIX_HW_INT_CAUSES_AD (IWM_CSR_MSIX_BASE + 0x808) 698 #define IWM_CSR_MSIX_HW_INT_MASK_AD (IWM_CSR_MSIX_BASE + 0x80C) 699 #define IWM_CSR_MSIX_AUTOMASK_ST_AD (IWM_CSR_MSIX_BASE + 0x810) 700 #define IWM_CSR_MSIX_RX_IVAR_AD_REG (IWM_CSR_MSIX_BASE + 0x880) 701 #define IWM_CSR_MSIX_IVAR_AD_REG (IWM_CSR_MSIX_BASE + 0x890) 702 #define IWM_CSR_MSIX_PENDING_PBA_AD (IWM_CSR_MSIX_BASE + 0x1000) 703 #define IWM_CSR_MSIX_RX_IVAR(cause) (IWM_CSR_MSIX_RX_IVAR_AD_REG + (cause)) 704 #define IWM_CSR_MSIX_IVAR(cause) (IWM_CSR_MSIX_IVAR_AD_REG + (cause)) 705 706 /* 707 * Causes for the FH register interrupts 708 */ 709 enum msix_fh_int_causes { 710 IWM_MSIX_FH_INT_CAUSES_Q0 = (1 << 0), 711 IWM_MSIX_FH_INT_CAUSES_Q1 = (1 << 1), 712 IWM_MSIX_FH_INT_CAUSES_D2S_CH0_NUM = (1 << 16), 713 IWM_MSIX_FH_INT_CAUSES_D2S_CH1_NUM = (1 << 17), 714 IWM_MSIX_FH_INT_CAUSES_S2D = (1 << 19), 715 IWM_MSIX_FH_INT_CAUSES_FH_ERR = (1 << 21), 716 }; 717 718 /* 719 * END iwl-csr.h 720 */ 721 722 /* 723 * BEGIN iwl-fw.h 724 */ 725 726 /* 727 * Causes for the HW register interrupts 728 */ 729 enum msix_hw_int_causes { 730 IWM_MSIX_HW_INT_CAUSES_REG_ALIVE = (1 << 0), 731 IWM_MSIX_HW_INT_CAUSES_REG_WAKEUP = (1 << 1), 732 IWM_MSIX_HW_INT_CAUSES_REG_IPC = (1 << 1), 733 IWM_MSIX_HW_INT_CAUSES_REG_IML = (1 << 2), 734 IWM_MSIX_HW_INT_CAUSES_REG_SW_ERR_V2 = (1 << 5), 735 IWM_MSIX_HW_INT_CAUSES_REG_CT_KILL = (1 << 6), 736 IWM_MSIX_HW_INT_CAUSES_REG_RF_KILL = (1 << 7), 737 IWM_MSIX_HW_INT_CAUSES_REG_PERIODIC = (1 << 8), 738 IWM_MSIX_HW_INT_CAUSES_REG_SW_ERR = (1 << 25), 739 IWM_MSIX_HW_INT_CAUSES_REG_SCD = (1 << 26), 740 IWM_MSIX_HW_INT_CAUSES_REG_FH_TX = (1 << 27), 741 IWM_MSIX_HW_INT_CAUSES_REG_HW_ERR = (1 << 29), 742 IWM_MSIX_HW_INT_CAUSES_REG_HAP = (1 << 30), 743 }; 744 745 /* 746 * Registers to map causes to vectors 747 */ 748 enum msix_ivar_for_cause { 749 IWM_MSIX_IVAR_CAUSE_D2S_CH0_NUM = 0x0, 750 IWM_MSIX_IVAR_CAUSE_D2S_CH1_NUM = 0x1, 751 IWM_MSIX_IVAR_CAUSE_S2D = 0x3, 752 IWM_MSIX_IVAR_CAUSE_FH_ERR = 0x5, 753 IWM_MSIX_IVAR_CAUSE_REG_ALIVE = 0x10, 754 IWM_MSIX_IVAR_CAUSE_REG_WAKEUP = 0x11, 755 IWM_MSIX_IVAR_CAUSE_REG_IML = 0x12, 756 IWM_MSIX_IVAR_CAUSE_REG_CT_KILL = 0x16, 757 IWM_MSIX_IVAR_CAUSE_REG_RF_KILL = 0x17, 758 IWM_MSIX_IVAR_CAUSE_REG_PERIODIC = 0x18, 759 IWM_MSIX_IVAR_CAUSE_REG_SW_ERR = 0x29, 760 IWM_MSIX_IVAR_CAUSE_REG_SCD = 0x2a, 761 IWM_MSIX_IVAR_CAUSE_REG_FH_TX = 0x2b, 762 IWM_MSIX_IVAR_CAUSE_REG_HW_ERR = 0x2d, 763 IWM_MSIX_IVAR_CAUSE_REG_HAP = 0x2e, 764 }; 765 766 #define IWM_MSIX_AUTO_CLEAR_CAUSE (0 << 7) 767 #define IWM_MSIX_NON_AUTO_CLEAR_CAUSE (1 << 7) 768 769 /** 770 * uCode API flags 771 * @IWM_UCODE_TLV_FLAGS_PAN: This is PAN capable microcode; this previously 772 * was a separate TLV but moved here to save space. 773 * @IWM_UCODE_TLV_FLAGS_NEWSCAN: new uCode scan behaviour on hidden SSID, 774 * treats good CRC threshold as a boolean 775 * @IWM_UCODE_TLV_FLAGS_MFP: This uCode image supports MFP (802.11w). 776 * @IWM_UCODE_TLV_FLAGS_P2P: This uCode image supports P2P. 777 * @IWM_UCODE_TLV_FLAGS_DW_BC_TABLE: The SCD byte count table is in DWORDS 778 * @IWM_UCODE_TLV_FLAGS_UAPSD: This uCode image supports uAPSD 779 * @IWM_UCODE_TLV_FLAGS_SHORT_BL: 16 entries of black list instead of 64 in scan 780 * offload profile config command. 781 * @IWM_UCODE_TLV_FLAGS_D3_6_IPV6_ADDRS: D3 image supports up to six 782 * (rather than two) IPv6 addresses 783 * @IWM_UCODE_TLV_FLAGS_NO_BASIC_SSID: not sending a probe with the SSID element 784 * from the probe request template. 785 * @IWM_UCODE_TLV_FLAGS_NEW_NSOFFL_SMALL: new NS offload (small version) 786 * @IWM_UCODE_TLV_FLAGS_NEW_NSOFFL_LARGE: new NS offload (large version) 787 * @IWM_UCODE_TLV_FLAGS_P2P_PS: P2P client power save is supported (only on a 788 * single bound interface). 789 * @IWM_UCODE_TLV_FLAGS_UAPSD_SUPPORT: General support for uAPSD 790 * @IWM_UCODE_TLV_FLAGS_EBS_SUPPORT: this uCode image supports EBS. 791 * @IWM_UCODE_TLV_FLAGS_P2P_PS_UAPSD: P2P client supports uAPSD power save 792 * @IWM_UCODE_TLV_FLAGS_BCAST_FILTERING: uCode supports broadcast filtering. 793 * @IWM_UCODE_TLV_FLAGS_GO_UAPSD: AP/GO interfaces support uAPSD clients 794 * 795 */ 796 #define IWM_UCODE_TLV_FLAGS_PAN (1 << 0) 797 #define IWM_UCODE_TLV_FLAGS_NEWSCAN (1 << 1) 798 #define IWM_UCODE_TLV_FLAGS_MFP (1 << 2) 799 #define IWM_UCODE_TLV_FLAGS_P2P (1 << 3) 800 #define IWM_UCODE_TLV_FLAGS_DW_BC_TABLE (1 << 4) 801 #define IWM_UCODE_TLV_FLAGS_SHORT_BL (1 << 7) 802 #define IWM_UCODE_TLV_FLAGS_D3_6_IPV6_ADDRS (1 << 10) 803 #define IWM_UCODE_TLV_FLAGS_NO_BASIC_SSID (1 << 12) 804 #define IWM_UCODE_TLV_FLAGS_NEW_NSOFFL_SMALL (1 << 15) 805 #define IWM_UCODE_TLV_FLAGS_NEW_NSOFFL_LARGE (1 << 16) 806 #define IWM_UCODE_TLV_FLAGS_P2P_PS (1 << 21) 807 #define IWM_UCODE_TLV_FLAGS_BSS_P2P_PS_DCM (1 << 22) 808 #define IWM_UCODE_TLV_FLAGS_BSS_P2P_PS_SCM (1 << 23) 809 #define IWM_UCODE_TLV_FLAGS_UAPSD_SUPPORT (1 << 24) 810 #define IWM_UCODE_TLV_FLAGS_EBS_SUPPORT (1 << 25) 811 #define IWM_UCODE_TLV_FLAGS_P2P_PS_UAPSD (1 << 26) 812 #define IWM_UCODE_TLV_FLAGS_BCAST_FILTERING (1 << 29) 813 #define IWM_UCODE_TLV_FLAGS_GO_UAPSD (1 << 30) 814 #define IWM_UCODE_TLV_FLAGS_LTE_COEX (1U << 31) 815 816 #define IWM_UCODE_TLV_FLAG_BITS \ 817 "\020\1PAN\2NEWSCAN\3MFP\4P2P\5DW_BC_TABLE\6NEWBT_COEX\7PM_CMD\10SHORT_BL\11RX_ENERGY\12TIME_EVENT_V2\13D3_6_IPV6\14BF_UPDATED\15NO_BASIC_SSID\17D3_CONTINUITY\20NEW_NSOFFL_S\21NEW_NSOFFL_L\22SCHED_SCAN\24STA_KEY_CMD\25DEVICE_PS_CMD\26P2P_PS\27P2P_PS_DCM\30P2P_PS_SCM\31UAPSD_SUPPORT\32EBS\33P2P_PS_UAPSD\36BCAST_FILTERING\37GO_UAPSD\40LTE_COEX" 818 819 /** 820 * uCode TLV api 821 * @IWM_UCODE_TLV_API_FRAGMENTED_SCAN: This ucode supports active dwell time 822 * longer than the passive one, which is essential for fragmented scan. 823 * @IWM_UCODE_TLV_API_WIFI_MCC_UPDATE: ucode supports MCC updates with source. 824 * @IWM_UCODE_TLV_API_WIDE_CMD_HDR: ucode supports wide command header 825 * @IWM_UCODE_TLV_API_LQ_SS_PARAMS: Configure STBC/BFER via LQ CMD ss_params 826 * @IWM_UCODE_TLV_API_NEW_VERSION: new versioning format 827 * @IWM_UCODE_TLV_API_TX_POWER_CHAIN: TX power API has larger command size 828 * (command version 3) that supports per-chain limits 829 * @IWM_UCODE_TLV_API_SCAN_TSF_REPORT: Scan start time reported in scan 830 * iteration complete notification, and the timestamp reported for RX 831 * received during scan, are reported in TSF of the mac specified in the 832 * scan request. 833 * @IWM_UCODE_TLV_API_TKIP_MIC_KEYS: This ucode supports version 2 of 834 * ADD_MODIFY_STA_KEY_API_S_VER_2. 835 * @IWM_UCODE_TLV_API_STA_TYPE: This ucode supports station type assignement. 836 * @IWM_UCODE_TLV_API_EXT_SCAN_PRIORITY: scan APIs use 8-level priority 837 * instead of 3. 838 * @IWM_UCODE_TLV_API_NEW_RX_STATS: should new RX STATISTICS API be used 839 * 840 * @IWM_NUM_UCODE_TLV_API: number of bits used 841 */ 842 #define IWM_UCODE_TLV_API_FRAGMENTED_SCAN 8 843 #define IWM_UCODE_TLV_API_WIFI_MCC_UPDATE 9 844 #define IWM_UCODE_TLV_API_WIDE_CMD_HDR 14 845 #define IWM_UCODE_TLV_API_LQ_SS_PARAMS 18 846 #define IWM_UCODE_TLV_API_NEW_VERSION 20 847 #define IWM_UCODE_TLV_API_EXT_SCAN_PRIORITY 24 848 #define IWM_UCODE_TLV_API_TX_POWER_CHAIN 27 849 #define IWM_UCODE_TLV_API_SCAN_TSF_REPORT 28 850 #define IWM_UCODE_TLV_API_TKIP_MIC_KEYS 29 851 #define IWM_UCODE_TLV_API_STA_TYPE 30 852 #define IWM_UCODE_TLV_API_NAN2_VER2 31 853 #define IWM_UCODE_TLV_API_ADAPTIVE_DWELL 32 854 #define IWM_UCODE_TLV_API_NEW_RX_STATS 35 855 #define IWM_UCODE_TLV_API_QUOTA_LOW_LATENCY 38 856 #define IWM_UCODE_TLV_API_ADAPTIVE_DWELL_V2 42 857 #define IWM_UCODE_TLV_API_SCAN_EXT_CHAN_VER 58 858 #define IWM_NUM_UCODE_TLV_API 128 859 860 #define IWM_UCODE_TLV_API_BITS \ 861 "\020\10FRAGMENTED_SCAN\11WIFI_MCC_UPDATE\16WIDE_CMD_HDR\22LQ_SS_PARAMS\30EXT_SCAN_PRIO\33TX_POWER_CHAIN\35TKIP_MIC_KEYS" 862 863 /** 864 * uCode capabilities 865 * @IWM_UCODE_TLV_CAPA_D0I3_SUPPORT: supports D0i3 866 * @IWM_UCODE_TLV_CAPA_LAR_SUPPORT: supports Location Aware Regulatory 867 * @IWM_UCODE_TLV_CAPA_UMAC_SCAN: supports UMAC scan. 868 * @IWM_UCODE_TLV_CAPA_BEAMFORMER: supports Beamformer 869 * @IWM_UCODE_TLV_CAPA_TOF_SUPPORT: supports Time of Flight (802.11mc FTM) 870 * @IWM_UCODE_TLV_CAPA_TDLS_SUPPORT: support basic TDLS functionality 871 * @IWM_UCODE_TLV_CAPA_TXPOWER_INSERTION_SUPPORT: supports insertion of current 872 * tx power value into TPC Report action frame and Link Measurement Report 873 * action frame 874 * @IWM_UCODE_TLV_CAPA_DS_PARAM_SET_IE_SUPPORT: supports updating current 875 * channel in DS parameter set element in probe requests. 876 * @IWM_UCODE_TLV_CAPA_WFA_TPC_REP_IE_SUPPORT: supports adding TPC Report IE in 877 * probe requests. 878 * @IWM_UCODE_TLV_CAPA_QUIET_PERIOD_SUPPORT: supports Quiet Period requests 879 * @IWM_UCODE_TLV_CAPA_DQA_SUPPORT: supports dynamic queue allocation (DQA), 880 * which also implies support for the scheduler configuration command 881 * @IWM_UCODE_TLV_CAPA_TDLS_CHANNEL_SWITCH: supports TDLS channel switching 882 * @IWM_UCODE_TLV_CAPA_CNSLDTD_D3_D0_IMG: Consolidated D3-D0 image 883 * @IWM_UCODE_TLV_CAPA_HOTSPOT_SUPPORT: supports Hot Spot Command 884 * @IWM_UCODE_TLV_CAPA_DC2DC_SUPPORT: supports DC2DC Command 885 * @IWM_UCODE_TLV_CAPA_2G_COEX_SUPPORT: supports 2G coex Command 886 * @IWM_UCODE_TLV_CAPA_CSUM_SUPPORT: supports TCP Checksum Offload 887 * @IWM_UCODE_TLV_CAPA_RADIO_BEACON_STATS: support radio and beacon statistics 888 * @IWM_UCODE_TLV_CAPA_P2P_STANDALONE_UAPSD: support p2p standalone U-APSD 889 * @IWM_UCODE_TLV_CAPA_BT_COEX_PLCR: enabled BT Coex packet level co-running 890 * @IWM_UCODE_TLV_CAPA_LAR_MULTI_MCC: ucode supports LAR updates with different 891 * sources for the MCC. This TLV bit is a future replacement to 892 * IWM_UCODE_TLV_API_WIFI_MCC_UPDATE. When either is set, multi-source LAR 893 * is supported. 894 * @IWM_UCODE_TLV_CAPA_BT_COEX_RRC: supports BT Coex RRC 895 * @IWM_UCODE_TLV_CAPA_GSCAN_SUPPORT: supports gscan 896 * @IWM_UCODE_TLV_CAPA_NAN_SUPPORT: supports NAN 897 * @IWM_UCODE_TLV_CAPA_UMAC_UPLOAD: supports upload mode in umac (1=supported, 898 * 0=no support) 899 * @IWM_UCODE_TLV_CAPA_EXTENDED_DTS_MEASURE: extended DTS measurement 900 * @IWM_UCODE_TLV_CAPA_SHORT_PM_TIMEOUTS: supports short PM timeouts 901 * @IWM_UCODE_TLV_CAPA_BT_MPLUT_SUPPORT: supports bt-coex Multi-priority LUT 902 * @IWM_UCODE_TLV_CAPA_BEACON_ANT_SELECTION: firmware will decide on what 903 * antenna the beacon should be transmitted 904 * @IWM_UCODE_TLV_CAPA_BEACON_STORING: firmware will store the latest beacon 905 * from AP and will send it upon d0i3 exit. 906 * @IWM_UCODE_TLV_CAPA_LAR_SUPPORT_V2: support LAR API V2 907 * @IWM_UCODE_TLV_CAPA_CT_KILL_BY_FW: firmware responsible for CT-kill 908 * @IWM_UCODE_TLV_CAPA_TEMP_THS_REPORT_SUPPORT: supports temperature 909 * thresholds reporting 910 * @IWM_UCODE_TLV_CAPA_CTDP_SUPPORT: supports cTDP command 911 * @IWM_UCODE_TLV_CAPA_USNIFFER_UNIFIED: supports usniffer enabled in 912 * regular image. 913 * @IWM_UCODE_TLV_CAPA_EXTEND_SHARED_MEM_CFG: support getting more shared 914 * memory addresses from the firmware. 915 * @IWM_UCODE_TLV_CAPA_LQM_SUPPORT: supports Link Quality Measurement 916 * @IWM_UCODE_TLV_CAPA_LMAC_UPLOAD: supports upload mode in lmac (1=supported, 917 * 0=no support) 918 * 919 * @IWM_NUM_UCODE_TLV_CAPA: number of bits used 920 */ 921 #define IWM_UCODE_TLV_CAPA_D0I3_SUPPORT 0 922 #define IWM_UCODE_TLV_CAPA_LAR_SUPPORT 1 923 #define IWM_UCODE_TLV_CAPA_UMAC_SCAN 2 924 #define IWM_UCODE_TLV_CAPA_BEAMFORMER 3 925 #define IWM_UCODE_TLV_CAPA_TOF_SUPPORT 5 926 #define IWM_UCODE_TLV_CAPA_TDLS_SUPPORT 6 927 #define IWM_UCODE_TLV_CAPA_TXPOWER_INSERTION_SUPPORT 8 928 #define IWM_UCODE_TLV_CAPA_DS_PARAM_SET_IE_SUPPORT 9 929 #define IWM_UCODE_TLV_CAPA_WFA_TPC_REP_IE_SUPPORT 10 930 #define IWM_UCODE_TLV_CAPA_QUIET_PERIOD_SUPPORT 11 931 #define IWM_UCODE_TLV_CAPA_DQA_SUPPORT 12 932 #define IWM_UCODE_TLV_CAPA_TDLS_CHANNEL_SWITCH 13 933 #define IWM_UCODE_TLV_CAPA_CNSLDTD_D3_D0_IMG 17 934 #define IWM_UCODE_TLV_CAPA_HOTSPOT_SUPPORT 18 935 #define IWM_UCODE_TLV_CAPA_DC2DC_CONFIG_SUPPORT 19 936 #define IWM_UCODE_TLV_CAPA_2G_COEX_SUPPORT 20 937 #define IWM_UCODE_TLV_CAPA_CSUM_SUPPORT 21 938 #define IWM_UCODE_TLV_CAPA_RADIO_BEACON_STATS 22 939 #define IWM_UCODE_TLV_CAPA_P2P_STANDALONE_UAPSD 26 940 #define IWM_UCODE_TLV_CAPA_BT_COEX_PLCR 28 941 #define IWM_UCODE_TLV_CAPA_LAR_MULTI_MCC 29 942 #define IWM_UCODE_TLV_CAPA_BT_COEX_RRC 30 943 #define IWM_UCODE_TLV_CAPA_GSCAN_SUPPORT 31 944 #define IWM_UCODE_TLV_CAPA_NAN_SUPPORT 34 945 #define IWM_UCODE_TLV_CAPA_UMAC_UPLOAD 35 946 #define IWM_UCODE_TLV_CAPA_SOC_LATENCY_SUPPORT 37 947 #define IWM_UCODE_TLV_CAPA_BINDING_CDB_SUPPORT 39 948 #define IWM_UCODE_TLV_CAPA_CDB_SUPPORT 40 949 #define IWM_UCODE_TLV_CAPA_DYNAMIC_QUOTA 44 950 #define IWM_UCODE_TLV_CAPA_ULTRA_HB_CHANNELS 48 951 #define IWM_UCODE_TLV_CAPA_EXTENDED_DTS_MEASURE 64 952 #define IWM_UCODE_TLV_CAPA_SHORT_PM_TIMEOUTS 65 953 #define IWM_UCODE_TLV_CAPA_BT_MPLUT_SUPPORT 67 954 #define IWM_UCODE_TLV_CAPA_MULTI_QUEUE_RX_SUPPORT 68 955 #define IWM_UCODE_TLV_CAPA_BEACON_ANT_SELECTION 71 956 #define IWM_UCODE_TLV_CAPA_BEACON_STORING 72 957 #define IWM_UCODE_TLV_CAPA_LAR_SUPPORT_V2 73 958 #define IWM_UCODE_TLV_CAPA_CT_KILL_BY_FW 74 959 #define IWM_UCODE_TLV_CAPA_TEMP_THS_REPORT_SUPPORT 75 960 #define IWM_UCODE_TLV_CAPA_CTDP_SUPPORT 76 961 #define IWM_UCODE_TLV_CAPA_USNIFFER_UNIFIED 77 962 #define IWM_UCODE_TLV_CAPA_LMAC_UPLOAD 79 963 #define IWM_UCODE_TLV_CAPA_EXTEND_SHARED_MEM_CFG 80 964 #define IWM_UCODE_TLV_CAPA_LQM_SUPPORT 81 965 966 #define IWM_NUM_UCODE_TLV_CAPA 128 967 968 /* The default calibrate table size if not specified by firmware file */ 969 #define IWM_DEFAULT_STANDARD_PHY_CALIBRATE_TBL_SIZE 18 970 #define IWM_MAX_STANDARD_PHY_CALIBRATE_TBL_SIZE 19 971 #define IWM_MAX_PHY_CALIBRATE_TBL_SIZE 253 972 973 /* The default max probe length if not specified by the firmware file */ 974 #define IWM_DEFAULT_MAX_PROBE_LENGTH 200 975 976 /* 977 * For 16.0 uCode and above, there is no differentiation between sections, 978 * just an offset to the HW address. 979 */ 980 #define IWM_CPU1_CPU2_SEPARATOR_SECTION 0xFFFFCCCC 981 #define IWM_PAGING_SEPARATOR_SECTION 0xAAAABBBB 982 983 /* uCode version contains 4 values: Major/Minor/API/Serial */ 984 #define IWM_UCODE_MAJOR(ver) (((ver) & 0xFF000000) >> 24) 985 #define IWM_UCODE_MINOR(ver) (((ver) & 0x00FF0000) >> 16) 986 #define IWM_UCODE_API(ver) (((ver) & 0x0000FF00) >> 8) 987 #define IWM_UCODE_SERIAL(ver) ((ver) & 0x000000FF) 988 989 /* 990 * Calibration control struct. 991 * Sent as part of the phy configuration command. 992 * @flow_trigger: bitmap for which calibrations to perform according to 993 * flow triggers. 994 * @event_trigger: bitmap for which calibrations to perform according to 995 * event triggers. 996 */ 997 struct iwm_tlv_calib_ctrl { 998 uint32_t flow_trigger; 999 uint32_t event_trigger; 1000 } __packed; 1001 1002 #define IWM_FW_PHY_CFG_RADIO_TYPE_POS 0 1003 #define IWM_FW_PHY_CFG_RADIO_TYPE (0x3 << IWM_FW_PHY_CFG_RADIO_TYPE_POS) 1004 #define IWM_FW_PHY_CFG_RADIO_STEP_POS 2 1005 #define IWM_FW_PHY_CFG_RADIO_STEP (0x3 << IWM_FW_PHY_CFG_RADIO_STEP_POS) 1006 #define IWM_FW_PHY_CFG_RADIO_DASH_POS 4 1007 #define IWM_FW_PHY_CFG_RADIO_DASH (0x3 << IWM_FW_PHY_CFG_RADIO_DASH_POS) 1008 #define IWM_FW_PHY_CFG_TX_CHAIN_POS 16 1009 #define IWM_FW_PHY_CFG_TX_CHAIN (0xf << IWM_FW_PHY_CFG_TX_CHAIN_POS) 1010 #define IWM_FW_PHY_CFG_RX_CHAIN_POS 20 1011 #define IWM_FW_PHY_CFG_RX_CHAIN (0xf << IWM_FW_PHY_CFG_RX_CHAIN_POS) 1012 1013 #define IWM_UCODE_MAX_CS 1 1014 1015 /** 1016 * struct iwm_fw_cipher_scheme - a cipher scheme supported by FW. 1017 * @cipher: a cipher suite selector 1018 * @flags: cipher scheme flags (currently reserved for a future use) 1019 * @hdr_len: a size of MPDU security header 1020 * @pn_len: a size of PN 1021 * @pn_off: an offset of pn from the beginning of the security header 1022 * @key_idx_off: an offset of key index byte in the security header 1023 * @key_idx_mask: a bit mask of key_idx bits 1024 * @key_idx_shift: bit shift needed to get key_idx 1025 * @mic_len: mic length in bytes 1026 * @hw_cipher: a HW cipher index used in host commands 1027 */ 1028 struct iwm_fw_cipher_scheme { 1029 uint32_t cipher; 1030 uint8_t flags; 1031 uint8_t hdr_len; 1032 uint8_t pn_len; 1033 uint8_t pn_off; 1034 uint8_t key_idx_off; 1035 uint8_t key_idx_mask; 1036 uint8_t key_idx_shift; 1037 uint8_t mic_len; 1038 uint8_t hw_cipher; 1039 } __packed; 1040 1041 /** 1042 * struct iwm_fw_cscheme_list - a cipher scheme list 1043 * @size: a number of entries 1044 * @cs: cipher scheme entries 1045 */ 1046 struct iwm_fw_cscheme_list { 1047 uint8_t size; 1048 struct iwm_fw_cipher_scheme cs[]; 1049 } __packed; 1050 1051 /* 1052 * END iwl-fw.h 1053 */ 1054 1055 /* 1056 * BEGIN iwl-fw-file.h 1057 */ 1058 1059 /* v1/v2 uCode file layout */ 1060 struct iwm_ucode_header { 1061 uint32_t ver; /* major/minor/API/serial */ 1062 union { 1063 struct { 1064 uint32_t inst_size; /* bytes of runtime code */ 1065 uint32_t data_size; /* bytes of runtime data */ 1066 uint32_t init_size; /* bytes of init code */ 1067 uint32_t init_data_size; /* bytes of init data */ 1068 uint32_t boot_size; /* bytes of bootstrap code */ 1069 uint8_t data[0]; /* in same order as sizes */ 1070 } v1; 1071 struct { 1072 uint32_t build; /* build number */ 1073 uint32_t inst_size; /* bytes of runtime code */ 1074 uint32_t data_size; /* bytes of runtime data */ 1075 uint32_t init_size; /* bytes of init code */ 1076 uint32_t init_data_size; /* bytes of init data */ 1077 uint32_t boot_size; /* bytes of bootstrap code */ 1078 uint8_t data[0]; /* in same order as sizes */ 1079 } v2; 1080 } u; 1081 }; 1082 1083 /* 1084 * new TLV uCode file layout 1085 * 1086 * The new TLV file format contains TLVs, that each specify 1087 * some piece of data. 1088 */ 1089 1090 enum iwm_ucode_tlv_type { 1091 IWM_UCODE_TLV_INVALID = 0, /* unused */ 1092 IWM_UCODE_TLV_INST = 1, 1093 IWM_UCODE_TLV_DATA = 2, 1094 IWM_UCODE_TLV_INIT = 3, 1095 IWM_UCODE_TLV_INIT_DATA = 4, 1096 IWM_UCODE_TLV_BOOT = 5, 1097 IWM_UCODE_TLV_PROBE_MAX_LEN = 6, /* a uint32_t value */ 1098 IWM_UCODE_TLV_PAN = 7, 1099 IWM_UCODE_TLV_RUNT_EVTLOG_PTR = 8, 1100 IWM_UCODE_TLV_RUNT_EVTLOG_SIZE = 9, 1101 IWM_UCODE_TLV_RUNT_ERRLOG_PTR = 10, 1102 IWM_UCODE_TLV_INIT_EVTLOG_PTR = 11, 1103 IWM_UCODE_TLV_INIT_EVTLOG_SIZE = 12, 1104 IWM_UCODE_TLV_INIT_ERRLOG_PTR = 13, 1105 IWM_UCODE_TLV_ENHANCE_SENS_TBL = 14, 1106 IWM_UCODE_TLV_PHY_CALIBRATION_SIZE = 15, 1107 IWM_UCODE_TLV_WOWLAN_INST = 16, 1108 IWM_UCODE_TLV_WOWLAN_DATA = 17, 1109 IWM_UCODE_TLV_FLAGS = 18, 1110 IWM_UCODE_TLV_SEC_RT = 19, 1111 IWM_UCODE_TLV_SEC_INIT = 20, 1112 IWM_UCODE_TLV_SEC_WOWLAN = 21, 1113 IWM_UCODE_TLV_DEF_CALIB = 22, 1114 IWM_UCODE_TLV_PHY_SKU = 23, 1115 IWM_UCODE_TLV_SECURE_SEC_RT = 24, 1116 IWM_UCODE_TLV_SECURE_SEC_INIT = 25, 1117 IWM_UCODE_TLV_SECURE_SEC_WOWLAN = 26, 1118 IWM_UCODE_TLV_NUM_OF_CPU = 27, 1119 IWM_UCODE_TLV_CSCHEME = 28, 1120 /* 1121 * Following two are not in our base tag, but allow 1122 * handling ucode version 9. 1123 */ 1124 IWM_UCODE_TLV_API_CHANGES_SET = 29, 1125 IWM_UCODE_TLV_ENABLED_CAPABILITIES = 30, 1126 IWM_UCODE_TLV_N_SCAN_CHANNELS = 31, 1127 IWM_UCODE_TLV_PAGING = 32, 1128 IWM_UCODE_TLV_SEC_RT_USNIFFER = 34, 1129 IWM_UCODE_TLV_SDIO_ADMA_ADDR = 35, 1130 IWM_UCODE_TLV_FW_VERSION = 36, 1131 IWM_UCODE_TLV_FW_DBG_DEST = 38, 1132 IWM_UCODE_TLV_FW_DBG_CONF = 39, 1133 IWM_UCODE_TLV_FW_DBG_TRIGGER = 40, 1134 IWM_UCODE_TLV_CMD_VERSIONS = 48, 1135 IWM_UCODE_TLV_FW_GSCAN_CAPA = 50, 1136 IWM_UCODE_TLV_FW_MEM_SEG = 51, 1137 IWM_UCODE_TLV_UMAC_DEBUG_ADDRS = 54, 1138 IWM_UCODE_TLV_LMAC_DEBUG_ADDRS = 55, 1139 IWM_UCODE_TLV_HW_TYPE = 58, 1140 }; 1141 1142 #define IWM_UCODE_TLV_DEBUG_BASE 0x1000005 1143 #define IWM_UCODE_TLV_TYPE_DEBUG_INFO (IWM_UCODE_TLV_DEBUG_BASE + 0) 1144 #define IWM_UCODE_TLV_TYPE_BUFFER_ALLOCATION (IWM_UCODE_TLV_DEBUG_BASE + 1) 1145 #define IWM_UCODE_TLV_TYPE_HCMD (IWM_UCODE_TLV_DEBUG_BASE + 2) 1146 #define IWM_UCODE_TLV_TYPE_REGIONS (IWM_UCODE_TLV_DEBUG_BASE + 3) 1147 #define IWM_UCODE_TLV_TYPE_TRIGGERS (IWM_UCODE_TLV_DEBUG_BASE + 4) 1148 #define IWM_UCODE_TLV_DEBUG_MAX IWM_UCODE_TLV_TYPE_TRIGGERS 1149 1150 struct iwm_ucode_tlv { 1151 uint32_t type; /* see above */ 1152 uint32_t length; /* not including type/length fields */ 1153 uint8_t data[0]; 1154 }; 1155 1156 struct iwm_ucode_api { 1157 uint32_t api_index; 1158 uint32_t api_flags; 1159 } __packed; 1160 1161 struct iwm_ucode_capa { 1162 uint32_t api_index; 1163 uint32_t api_capa; 1164 } __packed; 1165 1166 #define IWM_TLV_UCODE_MAGIC 0x0a4c5749 1167 1168 struct iwm_tlv_ucode_header { 1169 /* 1170 * The TLV style ucode header is distinguished from 1171 * the v1/v2 style header by first four bytes being 1172 * zero, as such is an invalid combination of 1173 * major/minor/API/serial versions. 1174 */ 1175 uint32_t zero; 1176 uint32_t magic; 1177 uint8_t human_readable[64]; 1178 uint32_t ver; /* major/minor/API/serial */ 1179 uint32_t build; 1180 uint64_t ignore; 1181 /* 1182 * The data contained herein has a TLV layout, 1183 * see above for the TLV header and types. 1184 * Note that each TLV is padded to a length 1185 * that is a multiple of 4 for alignment. 1186 */ 1187 uint8_t data[0]; 1188 }; 1189 1190 /* 1191 * END iwl-fw-file.h 1192 */ 1193 1194 /* 1195 * BEGIN iwl-prph.h 1196 */ 1197 1198 /* 1199 * Registers in this file are internal, not PCI bus memory mapped. 1200 * Driver accesses these via IWM_HBUS_TARG_PRPH_* registers. 1201 */ 1202 #define IWM_PRPH_BASE (0x00000) 1203 #define IWM_PRPH_END (0xFFFFF) 1204 1205 /* APMG (power management) constants */ 1206 #define IWM_APMG_BASE (IWM_PRPH_BASE + 0x3000) 1207 #define IWM_APMG_CLK_CTRL_REG (IWM_APMG_BASE + 0x0000) 1208 #define IWM_APMG_CLK_EN_REG (IWM_APMG_BASE + 0x0004) 1209 #define IWM_APMG_CLK_DIS_REG (IWM_APMG_BASE + 0x0008) 1210 #define IWM_APMG_PS_CTRL_REG (IWM_APMG_BASE + 0x000c) 1211 #define IWM_APMG_PCIDEV_STT_REG (IWM_APMG_BASE + 0x0010) 1212 #define IWM_APMG_RFKILL_REG (IWM_APMG_BASE + 0x0014) 1213 #define IWM_APMG_RTC_INT_STT_REG (IWM_APMG_BASE + 0x001c) 1214 #define IWM_APMG_RTC_INT_MSK_REG (IWM_APMG_BASE + 0x0020) 1215 #define IWM_APMG_DIGITAL_SVR_REG (IWM_APMG_BASE + 0x0058) 1216 #define IWM_APMG_ANALOG_SVR_REG (IWM_APMG_BASE + 0x006C) 1217 1218 #define IWM_APMS_CLK_VAL_MRB_FUNC_MODE (0x00000001) 1219 #define IWM_APMG_CLK_VAL_DMA_CLK_RQT (0x00000200) 1220 #define IWM_APMG_CLK_VAL_BSM_CLK_RQT (0x00000800) 1221 1222 #define IWM_APMG_PS_CTRL_EARLY_PWR_OFF_RESET_DIS (0x00400000) 1223 #define IWM_APMG_PS_CTRL_VAL_RESET_REQ (0x04000000) 1224 #define IWM_APMG_PS_CTRL_MSK_PWR_SRC (0x03000000) 1225 #define IWM_APMG_PS_CTRL_VAL_PWR_SRC_VMAIN (0x00000000) 1226 #define IWM_APMG_PS_CTRL_VAL_PWR_SRC_VAUX (0x02000000) 1227 #define IWM_APMG_SVR_VOLTAGE_CONFIG_BIT_MSK (0x000001E0) /* bit 8:5 */ 1228 #define IWM_APMG_SVR_DIGITAL_VOLTAGE_1_32 (0x00000060) 1229 1230 #define IWM_APMG_PCIDEV_STT_VAL_L1_ACT_DIS (0x00000800) 1231 1232 #define IWM_APMG_RTC_INT_STT_RFKILL (0x10000000) 1233 1234 /* Device system time */ 1235 #define IWM_DEVICE_SYSTEM_TIME_REG 0xA0206C 1236 1237 /* Device NMI register */ 1238 #define IWM_DEVICE_SET_NMI_REG 0x00a01c30 1239 #define IWM_DEVICE_SET_NMI_VAL_HW 0x01 1240 #define IWM_DEVICE_SET_NMI_VAL_DRV 0x80 1241 #define IWM_DEVICE_SET_NMI_8000_REG 0x00a01c24 1242 #define IWM_DEVICE_SET_NMI_8000_VAL 0x1000000 1243 1244 /* 1245 * Device reset for family 8000 1246 * write to bit 24 in order to reset the CPU 1247 */ 1248 #define IWM_RELEASE_CPU_RESET 0x300c 1249 #define IWM_RELEASE_CPU_RESET_BIT 0x1000000 1250 1251 1252 /***************************************************************************** 1253 * 7000/3000 series SHR DTS addresses * 1254 *****************************************************************************/ 1255 1256 #define IWM_SHR_MISC_WFM_DTS_EN (0x00a10024) 1257 #define IWM_DTSC_CFG_MODE (0x00a10604) 1258 #define IWM_DTSC_VREF_AVG (0x00a10648) 1259 #define IWM_DTSC_VREF5_AVG (0x00a1064c) 1260 #define IWM_DTSC_CFG_MODE_PERIODIC (0x2) 1261 #define IWM_DTSC_PTAT_AVG (0x00a10650) 1262 1263 1264 /** 1265 * Tx Scheduler 1266 * 1267 * The Tx Scheduler selects the next frame to be transmitted, choosing TFDs 1268 * (Transmit Frame Descriptors) from up to 16 circular Tx queues resident in 1269 * host DRAM. It steers each frame's Tx command (which contains the frame 1270 * data) into one of up to 7 prioritized Tx DMA FIFO channels within the 1271 * device. A queue maps to only one (selectable by driver) Tx DMA channel, 1272 * but one DMA channel may take input from several queues. 1273 * 1274 * Tx DMA FIFOs have dedicated purposes. 1275 * 1276 * For 5000 series and up, they are used differently 1277 * (cf. iwl5000_default_queue_to_tx_fifo in iwl-5000.c): 1278 * 1279 * 0 -- EDCA BK (background) frames, lowest priority 1280 * 1 -- EDCA BE (best effort) frames, normal priority 1281 * 2 -- EDCA VI (video) frames, higher priority 1282 * 3 -- EDCA VO (voice) and management frames, highest priority 1283 * 4 -- unused 1284 * 5 -- unused 1285 * 6 -- unused 1286 * 7 -- Commands 1287 * 1288 * Driver should normally map queues 0-6 to Tx DMA/FIFO channels 0-6. 1289 * In addition, driver can map the remaining queues to Tx DMA/FIFO 1290 * channels 0-3 to support 11n aggregation via EDCA DMA channels. 1291 * 1292 * The driver sets up each queue to work in one of two modes: 1293 * 1294 * 1) Scheduler-Ack, in which the scheduler automatically supports a 1295 * block-ack (BA) window of up to 64 TFDs. In this mode, each queue 1296 * contains TFDs for a unique combination of Recipient Address (RA) 1297 * and Traffic Identifier (TID), that is, traffic of a given 1298 * Quality-Of-Service (QOS) priority, destined for a single station. 1299 * 1300 * In scheduler-ack mode, the scheduler keeps track of the Tx status of 1301 * each frame within the BA window, including whether it's been transmitted, 1302 * and whether it's been acknowledged by the receiving station. The device 1303 * automatically processes block-acks received from the receiving STA, 1304 * and reschedules un-acked frames to be retransmitted (successful 1305 * Tx completion may end up being out-of-order). 1306 * 1307 * The driver must maintain the queue's Byte Count table in host DRAM 1308 * for this mode. 1309 * This mode does not support fragmentation. 1310 * 1311 * 2) FIFO (a.k.a. non-Scheduler-ACK), in which each TFD is processed in order. 1312 * The device may automatically retry Tx, but will retry only one frame 1313 * at a time, until receiving ACK from receiving station, or reaching 1314 * retry limit and giving up. 1315 * 1316 * The command queue (#4/#9) must use this mode! 1317 * This mode does not require use of the Byte Count table in host DRAM. 1318 * 1319 * Driver controls scheduler operation via 3 means: 1320 * 1) Scheduler registers 1321 * 2) Shared scheduler data base in internal SRAM 1322 * 3) Shared data in host DRAM 1323 * 1324 * Initialization: 1325 * 1326 * When loading, driver should allocate memory for: 1327 * 1) 16 TFD circular buffers, each with space for (typically) 256 TFDs. 1328 * 2) 16 Byte Count circular buffers in 16 KBytes contiguous memory 1329 * (1024 bytes for each queue). 1330 * 1331 * After receiving "Alive" response from uCode, driver must initialize 1332 * the scheduler (especially for queue #4/#9, the command queue, otherwise 1333 * the driver can't issue commands!): 1334 */ 1335 #define IWM_SCD_MEM_LOWER_BOUND (0x0000) 1336 1337 /** 1338 * Max Tx window size is the max number of contiguous TFDs that the scheduler 1339 * can keep track of at one time when creating block-ack chains of frames. 1340 * Note that "64" matches the number of ack bits in a block-ack packet. 1341 */ 1342 #define IWM_SCD_WIN_SIZE 64 1343 #define IWM_SCD_FRAME_LIMIT 64 1344 1345 #define IWM_SCD_TXFIFO_POS_TID (0) 1346 #define IWM_SCD_TXFIFO_POS_RA (4) 1347 #define IWM_SCD_QUEUE_RA_TID_MAP_RATID_MSK (0x01FF) 1348 1349 /* agn SCD */ 1350 #define IWM_SCD_QUEUE_STTS_REG_POS_TXF (0) 1351 #define IWM_SCD_QUEUE_STTS_REG_POS_ACTIVE (3) 1352 #define IWM_SCD_QUEUE_STTS_REG_POS_WSL (4) 1353 #define IWM_SCD_QUEUE_STTS_REG_POS_SCD_ACT_EN (19) 1354 #define IWM_SCD_QUEUE_STTS_REG_MSK (0x017F0000) 1355 1356 #define IWM_SCD_QUEUE_CTX_REG1_CREDIT_POS (8) 1357 #define IWM_SCD_QUEUE_CTX_REG1_CREDIT_MSK (0x00FFFF00) 1358 #define IWM_SCD_QUEUE_CTX_REG1_SUPER_CREDIT_POS (24) 1359 #define IWM_SCD_QUEUE_CTX_REG1_SUPER_CREDIT_MSK (0xFF000000) 1360 #define IWM_SCD_QUEUE_CTX_REG2_WIN_SIZE_POS (0) 1361 #define IWM_SCD_QUEUE_CTX_REG2_WIN_SIZE_MSK (0x0000007F) 1362 #define IWM_SCD_QUEUE_CTX_REG2_FRAME_LIMIT_POS (16) 1363 #define IWM_SCD_QUEUE_CTX_REG2_FRAME_LIMIT_MSK (0x007F0000) 1364 #define IWM_SCD_GP_CTRL_ENABLE_31_QUEUES (1 << 0) 1365 #define IWM_SCD_GP_CTRL_AUTO_ACTIVE_MODE (1 << 18) 1366 1367 /* Context Data */ 1368 #define IWM_SCD_CONTEXT_MEM_LOWER_BOUND (IWM_SCD_MEM_LOWER_BOUND + 0x600) 1369 #define IWM_SCD_CONTEXT_MEM_UPPER_BOUND (IWM_SCD_MEM_LOWER_BOUND + 0x6A0) 1370 1371 /* Tx status */ 1372 #define IWM_SCD_TX_STTS_MEM_LOWER_BOUND (IWM_SCD_MEM_LOWER_BOUND + 0x6A0) 1373 #define IWM_SCD_TX_STTS_MEM_UPPER_BOUND (IWM_SCD_MEM_LOWER_BOUND + 0x7E0) 1374 1375 /* Translation Data */ 1376 #define IWM_SCD_TRANS_TBL_MEM_LOWER_BOUND (IWM_SCD_MEM_LOWER_BOUND + 0x7E0) 1377 #define IWM_SCD_TRANS_TBL_MEM_UPPER_BOUND (IWM_SCD_MEM_LOWER_BOUND + 0x808) 1378 1379 #define IWM_SCD_CONTEXT_QUEUE_OFFSET(x)\ 1380 (IWM_SCD_CONTEXT_MEM_LOWER_BOUND + ((x) * 8)) 1381 1382 #define IWM_SCD_TX_STTS_QUEUE_OFFSET(x)\ 1383 (IWM_SCD_TX_STTS_MEM_LOWER_BOUND + ((x) * 16)) 1384 1385 #define IWM_SCD_TRANS_TBL_OFFSET_QUEUE(x) \ 1386 ((IWM_SCD_TRANS_TBL_MEM_LOWER_BOUND + ((x) * 2)) & 0xfffc) 1387 1388 #define IWM_SCD_BASE (IWM_PRPH_BASE + 0xa02c00) 1389 1390 #define IWM_SCD_SRAM_BASE_ADDR (IWM_SCD_BASE + 0x0) 1391 #define IWM_SCD_DRAM_BASE_ADDR (IWM_SCD_BASE + 0x8) 1392 #define IWM_SCD_AIT (IWM_SCD_BASE + 0x0c) 1393 #define IWM_SCD_TXFACT (IWM_SCD_BASE + 0x10) 1394 #define IWM_SCD_ACTIVE (IWM_SCD_BASE + 0x14) 1395 #define IWM_SCD_QUEUECHAIN_SEL (IWM_SCD_BASE + 0xe8) 1396 #define IWM_SCD_CHAINEXT_EN (IWM_SCD_BASE + 0x244) 1397 #define IWM_SCD_AGGR_SEL (IWM_SCD_BASE + 0x248) 1398 #define IWM_SCD_INTERRUPT_MASK (IWM_SCD_BASE + 0x108) 1399 #define IWM_SCD_GP_CTRL (IWM_SCD_BASE + 0x1a8) 1400 #define IWM_SCD_EN_CTRL (IWM_SCD_BASE + 0x254) 1401 1402 static inline unsigned int IWM_SCD_QUEUE_WRPTR(unsigned int chnl) 1403 { 1404 if (chnl < 20) 1405 return IWM_SCD_BASE + 0x18 + chnl * 4; 1406 return IWM_SCD_BASE + 0x284 + (chnl - 20) * 4; 1407 } 1408 1409 static inline unsigned int IWM_SCD_QUEUE_RDPTR(unsigned int chnl) 1410 { 1411 if (chnl < 20) 1412 return IWM_SCD_BASE + 0x68 + chnl * 4; 1413 return IWM_SCD_BASE + 0x2B4 + chnl * 4; 1414 } 1415 1416 static inline unsigned int IWM_SCD_QUEUE_STATUS_BITS(unsigned int chnl) 1417 { 1418 if (chnl < 20) 1419 return IWM_SCD_BASE + 0x10c + chnl * 4; 1420 return IWM_SCD_BASE + 0x334 + chnl * 4; 1421 } 1422 1423 /*********************** END TX SCHEDULER *************************************/ 1424 1425 /* Oscillator clock */ 1426 #define IWM_OSC_CLK (0xa04068) 1427 #define IWM_OSC_CLK_FORCE_CONTROL (0x8) 1428 1429 /* 1430 * END iwl-prph.h 1431 */ 1432 1433 /* 1434 * BEGIN iwl-fh.h 1435 */ 1436 1437 /****************************/ 1438 /* Flow Handler Definitions */ 1439 /****************************/ 1440 1441 /** 1442 * This I/O area is directly read/writable by driver (e.g. Linux uses writel()) 1443 * Addresses are offsets from device's PCI hardware base address. 1444 */ 1445 #define IWM_FH_MEM_LOWER_BOUND (0x1000) 1446 #define IWM_FH_MEM_UPPER_BOUND (0x2000) 1447 1448 /** 1449 * Keep-Warm (KW) buffer base address. 1450 * 1451 * Driver must allocate a 4KByte buffer that is for keeping the 1452 * host DRAM powered on (via dummy accesses to DRAM) to maintain low-latency 1453 * DRAM access when doing Txing or Rxing. The dummy accesses prevent host 1454 * from going into a power-savings mode that would cause higher DRAM latency, 1455 * and possible data over/under-runs, before all Tx/Rx is complete. 1456 * 1457 * Driver loads IWM_FH_KW_MEM_ADDR_REG with the physical address (bits 35:4) 1458 * of the buffer, which must be 4K aligned. Once this is set up, the device 1459 * automatically invokes keep-warm accesses when normal accesses might not 1460 * be sufficient to maintain fast DRAM response. 1461 * 1462 * Bit fields: 1463 * 31-0: Keep-warm buffer physical base address [35:4], must be 4K aligned 1464 */ 1465 #define IWM_FH_KW_MEM_ADDR_REG (IWM_FH_MEM_LOWER_BOUND + 0x97C) 1466 1467 1468 /** 1469 * TFD Circular Buffers Base (CBBC) addresses 1470 * 1471 * Device has 16 base pointer registers, one for each of 16 host-DRAM-resident 1472 * circular buffers (CBs/queues) containing Transmit Frame Descriptors (TFDs) 1473 * (see struct iwm_tfd_frame). These 16 pointer registers are offset by 0x04 1474 * bytes from one another. Each TFD circular buffer in DRAM must be 256-byte 1475 * aligned (address bits 0-7 must be 0). 1476 * Later devices have 20 (5000 series) or 30 (higher) queues, but the registers 1477 * for them are in different places. 1478 * 1479 * Bit fields in each pointer register: 1480 * 27-0: TFD CB physical base address [35:8], must be 256-byte aligned 1481 */ 1482 #define IWM_FH_MEM_CBBC_0_15_LOWER_BOUND (IWM_FH_MEM_LOWER_BOUND + 0x9D0) 1483 #define IWM_FH_MEM_CBBC_0_15_UPPER_BOUN (IWM_FH_MEM_LOWER_BOUND + 0xA10) 1484 #define IWM_FH_MEM_CBBC_16_19_LOWER_BOUND (IWM_FH_MEM_LOWER_BOUND + 0xBF0) 1485 #define IWM_FH_MEM_CBBC_16_19_UPPER_BOUND (IWM_FH_MEM_LOWER_BOUND + 0xC00) 1486 #define IWM_FH_MEM_CBBC_20_31_LOWER_BOUND (IWM_FH_MEM_LOWER_BOUND + 0xB20) 1487 #define IWM_FH_MEM_CBBC_20_31_UPPER_BOUND (IWM_FH_MEM_LOWER_BOUND + 0xB80) 1488 1489 /* Find TFD CB base pointer for given queue */ 1490 static inline unsigned int IWM_FH_MEM_CBBC_QUEUE(unsigned int chnl) 1491 { 1492 if (chnl < 16) 1493 return IWM_FH_MEM_CBBC_0_15_LOWER_BOUND + 4 * chnl; 1494 if (chnl < 20) 1495 return IWM_FH_MEM_CBBC_16_19_LOWER_BOUND + 4 * (chnl - 16); 1496 return IWM_FH_MEM_CBBC_20_31_LOWER_BOUND + 4 * (chnl - 20); 1497 } 1498 1499 1500 /** 1501 * Rx SRAM Control and Status Registers (RSCSR) 1502 * 1503 * These registers provide handshake between driver and device for the Rx queue 1504 * (this queue handles *all* command responses, notifications, Rx data, etc. 1505 * sent from uCode to host driver). Unlike Tx, there is only one Rx 1506 * queue, and only one Rx DMA/FIFO channel. Also unlike Tx, which can 1507 * concatenate up to 20 DRAM buffers to form a Tx frame, each Receive Buffer 1508 * Descriptor (RBD) points to only one Rx Buffer (RB); there is a 1:1 1509 * mapping between RBDs and RBs. 1510 * 1511 * Driver must allocate host DRAM memory for the following, and set the 1512 * physical address of each into device registers: 1513 * 1514 * 1) Receive Buffer Descriptor (RBD) circular buffer (CB), typically with 256 1515 * entries (although any power of 2, up to 4096, is selectable by driver). 1516 * Each entry (1 dword) points to a receive buffer (RB) of consistent size 1517 * (typically 4K, although 8K or 16K are also selectable by driver). 1518 * Driver sets up RB size and number of RBDs in the CB via Rx config 1519 * register IWM_FH_MEM_RCSR_CHNL0_CONFIG_REG. 1520 * 1521 * Bit fields within one RBD: 1522 * 27-0: Receive Buffer physical address bits [35:8], 256-byte aligned 1523 * 1524 * Driver sets physical address [35:8] of base of RBD circular buffer 1525 * into IWM_FH_RSCSR_CHNL0_RBDCB_BASE_REG [27:0]. 1526 * 1527 * 2) Rx status buffer, 8 bytes, in which uCode indicates which Rx Buffers 1528 * (RBs) have been filled, via a "write pointer", actually the index of 1529 * the RB's corresponding RBD within the circular buffer. Driver sets 1530 * physical address [35:4] into IWM_FH_RSCSR_CHNL0_STTS_WPTR_REG [31:0]. 1531 * 1532 * Bit fields in lower dword of Rx status buffer (upper dword not used 1533 * by driver: 1534 * 31-12: Not used by driver 1535 * 11- 0: Index of last filled Rx buffer descriptor 1536 * (device writes, driver reads this value) 1537 * 1538 * As the driver prepares Receive Buffers (RBs) for device to fill, driver must 1539 * enter pointers to these RBs into contiguous RBD circular buffer entries, 1540 * and update the device's "write" index register, 1541 * IWM_FH_RSCSR_CHNL0_RBDCB_WPTR_REG. 1542 * 1543 * This "write" index corresponds to the *next* RBD that the driver will make 1544 * available, i.e. one RBD past the tail of the ready-to-fill RBDs within 1545 * the circular buffer. This value should initially be 0 (before preparing any 1546 * RBs), should be 8 after preparing the first 8 RBs (for example), and must 1547 * wrap back to 0 at the end of the circular buffer (but don't wrap before 1548 * "read" index has advanced past 1! See below). 1549 * NOTE: DEVICE EXPECTS THE WRITE INDEX TO BE INCREMENTED IN MULTIPLES OF 8. 1550 * 1551 * As the device fills RBs (referenced from contiguous RBDs within the circular 1552 * buffer), it updates the Rx status buffer in host DRAM, 2) described above, 1553 * to tell the driver the index of the latest filled RBD. The driver must 1554 * read this "read" index from DRAM after receiving an Rx interrupt from device 1555 * 1556 * The driver must also internally keep track of a third index, which is the 1557 * next RBD to process. When receiving an Rx interrupt, driver should process 1558 * all filled but unprocessed RBs up to, but not including, the RB 1559 * corresponding to the "read" index. For example, if "read" index becomes "1", 1560 * driver may process the RB pointed to by RBD 0. Depending on volume of 1561 * traffic, there may be many RBs to process. 1562 * 1563 * If read index == write index, device thinks there is no room to put new data. 1564 * Due to this, the maximum number of filled RBs is 255, instead of 256. To 1565 * be safe, make sure that there is a gap of at least 2 RBDs between "write" 1566 * and "read" indexes; that is, make sure that there are no more than 254 1567 * buffers waiting to be filled. 1568 */ 1569 #define IWM_FH_MEM_RSCSR_LOWER_BOUND (IWM_FH_MEM_LOWER_BOUND + 0xBC0) 1570 #define IWM_FH_MEM_RSCSR_UPPER_BOUND (IWM_FH_MEM_LOWER_BOUND + 0xC00) 1571 #define IWM_FH_MEM_RSCSR_CHNL0 (IWM_FH_MEM_RSCSR_LOWER_BOUND) 1572 1573 /** 1574 * Physical base address of 8-byte Rx Status buffer. 1575 * Bit fields: 1576 * 31-0: Rx status buffer physical base address [35:4], must 16-byte aligned. 1577 */ 1578 #define IWM_FH_RSCSR_CHNL0_STTS_WPTR_REG (IWM_FH_MEM_RSCSR_CHNL0) 1579 1580 /** 1581 * Physical base address of Rx Buffer Descriptor Circular Buffer. 1582 * Bit fields: 1583 * 27-0: RBD CD physical base address [35:8], must be 256-byte aligned. 1584 */ 1585 #define IWM_FH_RSCSR_CHNL0_RBDCB_BASE_REG (IWM_FH_MEM_RSCSR_CHNL0 + 0x004) 1586 1587 /** 1588 * Rx write pointer (index, really!). 1589 * Bit fields: 1590 * 11-0: Index of driver's most recent prepared-to-be-filled RBD, + 1. 1591 * NOTE: For 256-entry circular buffer, use only bits [7:0]. 1592 */ 1593 #define IWM_FH_RSCSR_CHNL0_RBDCB_WPTR_REG (IWM_FH_MEM_RSCSR_CHNL0 + 0x008) 1594 #define IWM_FH_RSCSR_CHNL0_WPTR (IWM_FH_RSCSR_CHNL0_RBDCB_WPTR_REG) 1595 1596 #define IWM_FW_RSCSR_CHNL0_RXDCB_RDPTR_REG (IWM_FH_MEM_RSCSR_CHNL0 + 0x00c) 1597 #define IWM_FH_RSCSR_CHNL0_RDPTR IWM_FW_RSCSR_CHNL0_RXDCB_RDPTR_REG 1598 1599 /** 1600 * Rx Config/Status Registers (RCSR) 1601 * Rx Config Reg for channel 0 (only channel used) 1602 * 1603 * Driver must initialize IWM_FH_MEM_RCSR_CHNL0_CONFIG_REG as follows for 1604 * normal operation (see bit fields). 1605 * 1606 * Clearing IWM_FH_MEM_RCSR_CHNL0_CONFIG_REG to 0 turns off Rx DMA. 1607 * Driver should poll IWM_FH_MEM_RSSR_RX_STATUS_REG for 1608 * IWM_FH_RSSR_CHNL0_RX_STATUS_CHNL_IDLE (bit 24) before continuing. 1609 * 1610 * Bit fields: 1611 * 31-30: Rx DMA channel enable: '00' off/pause, '01' pause at end of frame, 1612 * '10' operate normally 1613 * 29-24: reserved 1614 * 23-20: # RBDs in circular buffer = 2^value; use "8" for 256 RBDs (normal), 1615 * min "5" for 32 RBDs, max "12" for 4096 RBDs. 1616 * 19-18: reserved 1617 * 17-16: size of each receive buffer; '00' 4K (normal), '01' 8K, 1618 * '10' 12K, '11' 16K. 1619 * 15-14: reserved 1620 * 13-12: IRQ destination; '00' none, '01' host driver (normal operation) 1621 * 11- 4: timeout for closing Rx buffer and interrupting host (units 32 usec) 1622 * typical value 0x10 (about 1/2 msec) 1623 * 3- 0: reserved 1624 */ 1625 #define IWM_FH_MEM_RCSR_LOWER_BOUND (IWM_FH_MEM_LOWER_BOUND + 0xC00) 1626 #define IWM_FH_MEM_RCSR_UPPER_BOUND (IWM_FH_MEM_LOWER_BOUND + 0xCC0) 1627 #define IWM_FH_MEM_RCSR_CHNL0 (IWM_FH_MEM_RCSR_LOWER_BOUND) 1628 1629 #define IWM_FH_MEM_RCSR_CHNL0_CONFIG_REG (IWM_FH_MEM_RCSR_CHNL0) 1630 #define IWM_FH_MEM_RCSR_CHNL0_RBDCB_WPTR (IWM_FH_MEM_RCSR_CHNL0 + 0x8) 1631 #define IWM_FH_MEM_RCSR_CHNL0_FLUSH_RB_REQ (IWM_FH_MEM_RCSR_CHNL0 + 0x10) 1632 1633 #define IWM_FH_RCSR_CHNL0_RX_CONFIG_RB_TIMEOUT_MSK (0x00000FF0) /* bits 4-11 */ 1634 #define IWM_FH_RCSR_CHNL0_RX_CONFIG_IRQ_DEST_MSK (0x00001000) /* bits 12 */ 1635 #define IWM_FH_RCSR_CHNL0_RX_CONFIG_SINGLE_FRAME_MSK (0x00008000) /* bit 15 */ 1636 #define IWM_FH_RCSR_CHNL0_RX_CONFIG_RB_SIZE_MSK (0x00030000) /* bits 16-17 */ 1637 #define IWM_FH_RCSR_CHNL0_RX_CONFIG_RBDBC_SIZE_MSK (0x00F00000) /* bits 20-23 */ 1638 #define IWM_FH_RCSR_CHNL0_RX_CONFIG_DMA_CHNL_EN_MSK (0xC0000000) /* bits 30-31*/ 1639 1640 #define IWM_FH_RCSR_RX_CONFIG_RBDCB_SIZE_POS (20) 1641 #define IWM_FH_RCSR_RX_CONFIG_REG_IRQ_RBTH_POS (4) 1642 #define IWM_RX_RB_TIMEOUT (0x11) 1643 1644 #define IWM_FH_RCSR_RX_CONFIG_CHNL_EN_PAUSE_VAL (0x00000000) 1645 #define IWM_FH_RCSR_RX_CONFIG_CHNL_EN_PAUSE_EOF_VAL (0x40000000) 1646 #define IWM_FH_RCSR_RX_CONFIG_CHNL_EN_ENABLE_VAL (0x80000000) 1647 1648 #define IWM_FH_RCSR_RX_CONFIG_REG_VAL_RB_SIZE_4K (0x00000000) 1649 #define IWM_FH_RCSR_RX_CONFIG_REG_VAL_RB_SIZE_8K (0x00010000) 1650 #define IWM_FH_RCSR_RX_CONFIG_REG_VAL_RB_SIZE_12K (0x00020000) 1651 #define IWM_FH_RCSR_RX_CONFIG_REG_VAL_RB_SIZE_16K (0x00030000) 1652 1653 #define IWM_FH_RCSR_CHNL0_RX_IGNORE_RXF_EMPTY (0x00000004) 1654 #define IWM_FH_RCSR_CHNL0_RX_CONFIG_IRQ_DEST_NO_INT_VAL (0x00000000) 1655 #define IWM_FH_RCSR_CHNL0_RX_CONFIG_IRQ_DEST_INT_HOST_VAL (0x00001000) 1656 1657 /** 1658 * Rx Shared Status Registers (RSSR) 1659 * 1660 * After stopping Rx DMA channel (writing 0 to 1661 * IWM_FH_MEM_RCSR_CHNL0_CONFIG_REG), driver must poll 1662 * IWM_FH_MEM_RSSR_RX_STATUS_REG until Rx channel is idle. 1663 * 1664 * Bit fields: 1665 * 24: 1 = Channel 0 is idle 1666 * 1667 * IWM_FH_MEM_RSSR_SHARED_CTRL_REG and IWM_FH_MEM_RSSR_RX_ENABLE_ERR_IRQ2DRV 1668 * contain default values that should not be altered by the driver. 1669 */ 1670 #define IWM_FH_MEM_RSSR_LOWER_BOUND (IWM_FH_MEM_LOWER_BOUND + 0xC40) 1671 #define IWM_FH_MEM_RSSR_UPPER_BOUND (IWM_FH_MEM_LOWER_BOUND + 0xD00) 1672 1673 #define IWM_FH_MEM_RSSR_SHARED_CTRL_REG (IWM_FH_MEM_RSSR_LOWER_BOUND) 1674 #define IWM_FH_MEM_RSSR_RX_STATUS_REG (IWM_FH_MEM_RSSR_LOWER_BOUND + 0x004) 1675 #define IWM_FH_MEM_RSSR_RX_ENABLE_ERR_IRQ2DRV\ 1676 (IWM_FH_MEM_RSSR_LOWER_BOUND + 0x008) 1677 1678 #define IWM_FH_RSSR_CHNL0_RX_STATUS_CHNL_IDLE (0x01000000) 1679 1680 #define IWM_FH_MEM_TFDIB_REG1_ADDR_BITSHIFT 28 1681 1682 /* TFDB Area - TFDs buffer table */ 1683 #define IWM_FH_MEM_TFDIB_DRAM_ADDR_LSB_MSK (0xFFFFFFFF) 1684 #define IWM_FH_TFDIB_LOWER_BOUND (IWM_FH_MEM_LOWER_BOUND + 0x900) 1685 #define IWM_FH_TFDIB_UPPER_BOUND (IWM_FH_MEM_LOWER_BOUND + 0x958) 1686 #define IWM_FH_TFDIB_CTRL0_REG(_chnl) (IWM_FH_TFDIB_LOWER_BOUND + 0x8 * (_chnl)) 1687 #define IWM_FH_TFDIB_CTRL1_REG(_chnl) (IWM_FH_TFDIB_LOWER_BOUND + 0x8 * (_chnl) + 0x4) 1688 1689 /** 1690 * Transmit DMA Channel Control/Status Registers (TCSR) 1691 * 1692 * Device has one configuration register for each of 8 Tx DMA/FIFO channels 1693 * supported in hardware (don't confuse these with the 16 Tx queues in DRAM, 1694 * which feed the DMA/FIFO channels); config regs are separated by 0x20 bytes. 1695 * 1696 * To use a Tx DMA channel, driver must initialize its 1697 * IWM_FH_TCSR_CHNL_TX_CONFIG_REG(chnl) with: 1698 * 1699 * IWM_FH_TCSR_TX_CONFIG_REG_VAL_DMA_CHNL_ENABLE | 1700 * IWM_FH_TCSR_TX_CONFIG_REG_VAL_DMA_CREDIT_ENABLE_VAL 1701 * 1702 * All other bits should be 0. 1703 * 1704 * Bit fields: 1705 * 31-30: Tx DMA channel enable: '00' off/pause, '01' pause at end of frame, 1706 * '10' operate normally 1707 * 29- 4: Reserved, set to "0" 1708 * 3: Enable internal DMA requests (1, normal operation), disable (0) 1709 * 2- 0: Reserved, set to "0" 1710 */ 1711 #define IWM_FH_TCSR_LOWER_BOUND (IWM_FH_MEM_LOWER_BOUND + 0xD00) 1712 #define IWM_FH_TCSR_UPPER_BOUND (IWM_FH_MEM_LOWER_BOUND + 0xE60) 1713 1714 /* Find Control/Status reg for given Tx DMA/FIFO channel */ 1715 #define IWM_FH_TCSR_CHNL_NUM (8) 1716 1717 /* TCSR: tx_config register values */ 1718 #define IWM_FH_TCSR_CHNL_TX_CONFIG_REG(_chnl) \ 1719 (IWM_FH_TCSR_LOWER_BOUND + 0x20 * (_chnl)) 1720 #define IWM_FH_TCSR_CHNL_TX_CREDIT_REG(_chnl) \ 1721 (IWM_FH_TCSR_LOWER_BOUND + 0x20 * (_chnl) + 0x4) 1722 #define IWM_FH_TCSR_CHNL_TX_BUF_STS_REG(_chnl) \ 1723 (IWM_FH_TCSR_LOWER_BOUND + 0x20 * (_chnl) + 0x8) 1724 1725 #define IWM_FH_TCSR_TX_CONFIG_REG_VAL_MSG_MODE_TXF (0x00000000) 1726 #define IWM_FH_TCSR_TX_CONFIG_REG_VAL_MSG_MODE_DRV (0x00000001) 1727 1728 #define IWM_FH_TCSR_TX_CONFIG_REG_VAL_DMA_CREDIT_DISABLE (0x00000000) 1729 #define IWM_FH_TCSR_TX_CONFIG_REG_VAL_DMA_CREDIT_ENABLE (0x00000008) 1730 1731 #define IWM_FH_TCSR_TX_CONFIG_REG_VAL_CIRQ_HOST_NOINT (0x00000000) 1732 #define IWM_FH_TCSR_TX_CONFIG_REG_VAL_CIRQ_HOST_ENDTFD (0x00100000) 1733 #define IWM_FH_TCSR_TX_CONFIG_REG_VAL_CIRQ_HOST_IFTFD (0x00200000) 1734 1735 #define IWM_FH_TCSR_TX_CONFIG_REG_VAL_CIRQ_RTC_NOINT (0x00000000) 1736 #define IWM_FH_TCSR_TX_CONFIG_REG_VAL_CIRQ_RTC_ENDTFD (0x00400000) 1737 #define IWM_FH_TCSR_TX_CONFIG_REG_VAL_CIRQ_RTC_IFTFD (0x00800000) 1738 1739 #define IWM_FH_TCSR_TX_CONFIG_REG_VAL_DMA_CHNL_PAUSE (0x00000000) 1740 #define IWM_FH_TCSR_TX_CONFIG_REG_VAL_DMA_CHNL_PAUSE_EOF (0x40000000) 1741 #define IWM_FH_TCSR_TX_CONFIG_REG_VAL_DMA_CHNL_ENABLE (0x80000000) 1742 1743 #define IWM_FH_TCSR_CHNL_TX_BUF_STS_REG_VAL_TFDB_EMPTY (0x00000000) 1744 #define IWM_FH_TCSR_CHNL_TX_BUF_STS_REG_VAL_TFDB_WAIT (0x00002000) 1745 #define IWM_FH_TCSR_CHNL_TX_BUF_STS_REG_VAL_TFDB_VALID (0x00000003) 1746 1747 #define IWM_FH_TCSR_CHNL_TX_BUF_STS_REG_POS_TB_NUM (20) 1748 #define IWM_FH_TCSR_CHNL_TX_BUF_STS_REG_POS_TB_IDX (12) 1749 1750 /** 1751 * Tx Shared Status Registers (TSSR) 1752 * 1753 * After stopping Tx DMA channel (writing 0 to 1754 * IWM_FH_TCSR_CHNL_TX_CONFIG_REG(chnl)), driver must poll 1755 * IWM_FH_TSSR_TX_STATUS_REG until selected Tx channel is idle 1756 * (channel's buffers empty | no pending requests). 1757 * 1758 * Bit fields: 1759 * 31-24: 1 = Channel buffers empty (channel 7:0) 1760 * 23-16: 1 = No pending requests (channel 7:0) 1761 */ 1762 #define IWM_FH_TSSR_LOWER_BOUND (IWM_FH_MEM_LOWER_BOUND + 0xEA0) 1763 #define IWM_FH_TSSR_UPPER_BOUND (IWM_FH_MEM_LOWER_BOUND + 0xEC0) 1764 1765 #define IWM_FH_TSSR_TX_STATUS_REG (IWM_FH_TSSR_LOWER_BOUND + 0x010) 1766 1767 /** 1768 * Bit fields for TSSR(Tx Shared Status & Control) error status register: 1769 * 31: Indicates an address error when accessed to internal memory 1770 * uCode/driver must write "1" in order to clear this flag 1771 * 30: Indicates that Host did not send the expected number of dwords to FH 1772 * uCode/driver must write "1" in order to clear this flag 1773 * 16-9:Each status bit is for one channel. Indicates that an (Error) ActDMA 1774 * command was received from the scheduler while the TRB was already full 1775 * with previous command 1776 * uCode/driver must write "1" in order to clear this flag 1777 * 7-0: Each status bit indicates a channel's TxCredit error. When an error 1778 * bit is set, it indicates that the FH has received a full indication 1779 * from the RTC TxFIFO and the current value of the TxCredit counter was 1780 * not equal to zero. This mean that the credit mechanism was not 1781 * synchronized to the TxFIFO status 1782 * uCode/driver must write "1" in order to clear this flag 1783 */ 1784 #define IWM_FH_TSSR_TX_ERROR_REG (IWM_FH_TSSR_LOWER_BOUND + 0x018) 1785 #define IWM_FH_TSSR_TX_MSG_CONFIG_REG (IWM_FH_TSSR_LOWER_BOUND + 0x008) 1786 1787 #define IWM_FH_TSSR_TX_STATUS_REG_MSK_CHNL_IDLE(_chnl) ((1 << (_chnl)) << 16) 1788 1789 /* Tx service channels */ 1790 #define IWM_FH_SRVC_CHNL (9) 1791 #define IWM_FH_SRVC_LOWER_BOUND (IWM_FH_MEM_LOWER_BOUND + 0x9C8) 1792 #define IWM_FH_SRVC_UPPER_BOUND (IWM_FH_MEM_LOWER_BOUND + 0x9D0) 1793 #define IWM_FH_SRVC_CHNL_SRAM_ADDR_REG(_chnl) \ 1794 (IWM_FH_SRVC_LOWER_BOUND + ((_chnl) - 9) * 0x4) 1795 1796 #define IWM_FH_TX_CHICKEN_BITS_REG (IWM_FH_MEM_LOWER_BOUND + 0xE98) 1797 #define IWM_FH_TX_TRB_REG(_chan) (IWM_FH_MEM_LOWER_BOUND + 0x958 + \ 1798 (_chan) * 4) 1799 1800 /* Instruct FH to increment the retry count of a packet when 1801 * it is brought from the memory to TX-FIFO 1802 */ 1803 #define IWM_FH_TX_CHICKEN_BITS_SCD_AUTO_RETRY_EN (0x00000002) 1804 1805 #define IWM_RX_QUEUE_SIZE 256 1806 #define IWM_RX_QUEUE_MASK 255 1807 #define IWM_RX_QUEUE_SIZE_LOG 8 1808 1809 /* 1810 * RX related structures and functions 1811 */ 1812 #define IWM_RX_FREE_BUFFERS 64 1813 #define IWM_RX_LOW_WATERMARK 8 1814 1815 /** 1816 * struct iwm_rb_status - reseve buffer status 1817 * host memory mapped FH registers 1818 * @closed_rb_num [0:11] - Indicates the index of the RB which was closed 1819 * @closed_fr_num [0:11] - Indicates the index of the RX Frame which was closed 1820 * @finished_rb_num [0:11] - Indicates the index of the current RB 1821 * in which the last frame was written to 1822 * @finished_fr_num [0:11] - Indicates the index of the RX Frame 1823 * which was transferred 1824 */ 1825 struct iwm_rb_status { 1826 uint16_t closed_rb_num; 1827 uint16_t closed_fr_num; 1828 uint16_t finished_rb_num; 1829 uint16_t finished_fr_nam; 1830 uint32_t unused; 1831 } __packed; 1832 1833 1834 #define IWM_TFD_QUEUE_SIZE_MAX (256) 1835 #define IWM_TFD_QUEUE_SIZE_BC_DUP (64) 1836 #define IWM_TFD_QUEUE_BC_SIZE (IWM_TFD_QUEUE_SIZE_MAX + \ 1837 IWM_TFD_QUEUE_SIZE_BC_DUP) 1838 #define IWM_TX_DMA_MASK DMA_BIT_MASK(36) 1839 #define IWM_NUM_OF_TBS 20 1840 1841 static inline uint8_t iwm_get_dma_hi_addr(bus_addr_t addr) 1842 { 1843 return (sizeof(addr) > sizeof(uint32_t) ? (addr >> 16) >> 16 : 0) & 0xF; 1844 } 1845 /** 1846 * struct iwm_tfd_tb transmit buffer descriptor within transmit frame descriptor 1847 * 1848 * This structure contains dma address and length of transmission address 1849 * 1850 * @lo: low [31:0] portion of the dma address of TX buffer 1851 * every even is unaligned on 16 bit boundary 1852 * @hi_n_len 0-3 [35:32] portion of dma 1853 * 4-15 length of the tx buffer 1854 */ 1855 struct iwm_tfd_tb { 1856 uint32_t lo; 1857 uint16_t hi_n_len; 1858 } __packed; 1859 1860 /** 1861 * struct iwm_tfd 1862 * 1863 * Transmit Frame Descriptor (TFD) 1864 * 1865 * @ __reserved1[3] reserved 1866 * @ num_tbs 0-4 number of active tbs 1867 * 5 reserved 1868 * 6-7 padding (not used) 1869 * @ tbs[20] transmit frame buffer descriptors 1870 * @ __pad padding 1871 * 1872 * Each Tx queue uses a circular buffer of 256 TFDs stored in host DRAM. 1873 * Both driver and device share these circular buffers, each of which must be 1874 * contiguous 256 TFDs x 128 bytes-per-TFD = 32 KBytes 1875 * 1876 * Driver must indicate the physical address of the base of each 1877 * circular buffer via the IWM_FH_MEM_CBBC_QUEUE registers. 1878 * 1879 * Each TFD contains pointer/size information for up to 20 data buffers 1880 * in host DRAM. These buffers collectively contain the (one) frame described 1881 * by the TFD. Each buffer must be a single contiguous block of memory within 1882 * itself, but buffers may be scattered in host DRAM. Each buffer has max size 1883 * of (4K - 4). The concatenates all of a TFD's buffers into a single 1884 * Tx frame, up to 8 KBytes in size. 1885 * 1886 * A maximum of 255 (not 256!) TFDs may be on a queue waiting for Tx. 1887 */ 1888 struct iwm_tfd { 1889 uint8_t __reserved1[3]; 1890 uint8_t num_tbs; 1891 struct iwm_tfd_tb tbs[IWM_NUM_OF_TBS]; 1892 uint32_t __pad; 1893 } __packed; 1894 1895 /* Keep Warm Size */ 1896 #define IWM_KW_SIZE 0x1000 /* 4k */ 1897 1898 /* Fixed (non-configurable) rx data from phy */ 1899 1900 /** 1901 * struct iwm_agn_schedq_bc_tbl scheduler byte count table 1902 * base physical address provided by IWM_SCD_DRAM_BASE_ADDR 1903 * @tfd_offset 0-12 - tx command byte count 1904 * 12-16 - station index 1905 */ 1906 struct iwm_agn_scd_bc_tbl { 1907 uint16_t tfd_offset[IWM_TFD_QUEUE_BC_SIZE]; 1908 } __packed; 1909 1910 1911 /* 1912 * END iwl-fh.h 1913 */ 1914 1915 /* 1916 * BEGIN mvm/fw-api.h 1917 */ 1918 1919 #define IWM_TX_CRC_SIZE 4 1920 #define IWM_TX_DELIMITER_SIZE 4 1921 1922 /* Maximum number of Tx queues. */ 1923 #define IWM_MAX_QUEUES 31 1924 1925 /** 1926 * DQA - Dynamic Queue Allocation -introduction 1927 * 1928 * Dynamic Queue Allocation (AKA "DQA") is a feature implemented in iwlwifi 1929 * to allow dynamic allocation of queues on-demand, rather than allocate them 1930 * statically ahead of time. Ideally, we would like to allocate one queue 1931 * per RA/TID, thus allowing an AP - for example - to send BE traffic to STA2 1932 * even if it also needs to send traffic to a sleeping STA1, without being 1933 * blocked by the sleeping station. 1934 * 1935 * Although the queues in DQA mode are dynamically allocated, there are still 1936 * some queues that are statically allocated: 1937 * TXQ #0 - command queue 1938 * TXQ #1 - aux frames 1939 * TXQ #2 - P2P device frames 1940 * TXQ #3 - P2P GO/SoftAP GCAST/BCAST frames 1941 * TXQ #4 - BSS DATA frames queue 1942 * TXQ #5-8 - non-QoS data, QoS no-data, and MGMT frames queue pool 1943 * TXQ #9 - P2P GO/SoftAP probe responses 1944 * TXQ #10-31 - QoS DATA frames queue pool (for Tx aggregation) 1945 */ 1946 1947 /* static DQA Tx queue numbers */ 1948 #define IWM_DQA_CMD_QUEUE 0 1949 #define IWM_DQA_AUX_QUEUE 1 1950 #define IWM_DQA_P2P_DEVICE_QUEUE 2 1951 #define IWM_DQA_INJECT_MONITOR_QUEUE 2 1952 #define IWM_DQA_GCAST_QUEUE 3 1953 #define IWM_DQA_BSS_CLIENT_QUEUE 4 1954 #define IWM_DQA_MIN_MGMT_QUEUE 5 1955 #define IWM_DQA_MAX_MGMT_QUEUE 8 1956 #define IWM_DQA_AP_PROBE_RESP_QUEUE 9 1957 #define IWM_DQA_MIN_DATA_QUEUE 10 1958 #define IWM_DQA_MAX_DATA_QUEUE 31 1959 1960 /* Reserve 8 DQA Tx queues, from 10 up to 17, for A-MPDU aggregation. */ 1961 #define IWM_MAX_TID_COUNT 8 1962 #define IWM_FIRST_AGG_TX_QUEUE IWM_DQA_MIN_DATA_QUEUE 1963 #define IWM_LAST_AGG_TX_QUEUE (IWM_FIRST_AGG_TX_QUEUE + IWM_MAX_TID_COUNT - 1) 1964 1965 /* legacy non-DQA queues; the legacy command queue uses a different number! */ 1966 #define IWM_OFFCHANNEL_QUEUE 8 1967 #define IWM_CMD_QUEUE 9 1968 #define IWM_AUX_QUEUE 15 1969 1970 #define IWM_TX_FIFO_BK 0 1971 #define IWM_TX_FIFO_BE 1 1972 #define IWM_TX_FIFO_VI 2 1973 #define IWM_TX_FIFO_VO 3 1974 #define IWM_TX_FIFO_MCAST 5 1975 #define IWM_TX_FIFO_CMD 7 1976 1977 #define IWM_STATION_COUNT 16 1978 1979 /* 1980 * Commands 1981 */ 1982 #define IWM_ALIVE 0x1 1983 #define IWM_REPLY_ERROR 0x2 1984 #define IWM_INIT_COMPLETE_NOTIF 0x4 1985 1986 /* PHY context commands */ 1987 #define IWM_PHY_CONTEXT_CMD 0x8 1988 #define IWM_DBG_CFG 0x9 1989 1990 /* UMAC scan commands */ 1991 #define IWM_SCAN_ITERATION_COMPLETE_UMAC 0xb5 1992 #define IWM_SCAN_CFG_CMD 0xc 1993 #define IWM_SCAN_REQ_UMAC 0xd 1994 #define IWM_SCAN_ABORT_UMAC 0xe 1995 #define IWM_SCAN_COMPLETE_UMAC 0xf 1996 1997 /* station table */ 1998 #define IWM_ADD_STA_KEY 0x17 1999 #define IWM_ADD_STA 0x18 2000 #define IWM_REMOVE_STA 0x19 2001 2002 /* TX */ 2003 #define IWM_TX_CMD 0x1c 2004 #define IWM_TXPATH_FLUSH 0x1e 2005 #define IWM_MGMT_MCAST_KEY 0x1f 2006 2007 /* scheduler config */ 2008 #define IWM_SCD_QUEUE_CFG 0x1d 2009 2010 /* global key */ 2011 #define IWM_WEP_KEY 0x20 2012 2013 /* MAC and Binding commands */ 2014 #define IWM_MAC_CONTEXT_CMD 0x28 2015 #define IWM_TIME_EVENT_CMD 0x29 /* both CMD and response */ 2016 #define IWM_TIME_EVENT_NOTIFICATION 0x2a 2017 #define IWM_BINDING_CONTEXT_CMD 0x2b 2018 #define IWM_TIME_QUOTA_CMD 0x2c 2019 #define IWM_NON_QOS_TX_COUNTER_CMD 0x2d 2020 2021 #define IWM_LQ_CMD 0x4e 2022 2023 /* Calibration */ 2024 #define IWM_TEMPERATURE_NOTIFICATION 0x62 2025 #define IWM_CALIBRATION_CFG_CMD 0x65 2026 #define IWM_CALIBRATION_RES_NOTIFICATION 0x66 2027 #define IWM_CALIBRATION_COMPLETE_NOTIFICATION 0x67 2028 #define IWM_RADIO_VERSION_NOTIFICATION 0x68 2029 2030 /* paging block to FW cpu2 */ 2031 #define IWM_FW_PAGING_BLOCK_CMD 0x4f 2032 2033 /* Scan offload */ 2034 #define IWM_SCAN_OFFLOAD_REQUEST_CMD 0x51 2035 #define IWM_SCAN_OFFLOAD_ABORT_CMD 0x52 2036 #define IWM_HOT_SPOT_CMD 0x53 2037 #define IWM_SCAN_OFFLOAD_COMPLETE 0x6d 2038 #define IWM_SCAN_OFFLOAD_UPDATE_PROFILES_CMD 0x6e 2039 #define IWM_SCAN_OFFLOAD_CONFIG_CMD 0x6f 2040 #define IWM_MATCH_FOUND_NOTIFICATION 0xd9 2041 #define IWM_SCAN_ITERATION_COMPLETE 0xe7 2042 2043 /* Phy */ 2044 #define IWM_PHY_CONFIGURATION_CMD 0x6a 2045 #define IWM_CALIB_RES_NOTIF_PHY_DB 0x6b 2046 #define IWM_PHY_DB_CMD 0x6c 2047 2048 /* Power - legacy power table command */ 2049 #define IWM_POWER_TABLE_CMD 0x77 2050 #define IWM_PSM_UAPSD_AP_MISBEHAVING_NOTIFICATION 0x78 2051 #define IWM_LTR_CONFIG 0xee 2052 2053 /* Thermal Throttling*/ 2054 #define IWM_REPLY_THERMAL_MNG_BACKOFF 0x7e 2055 2056 /* NVM */ 2057 #define IWM_NVM_ACCESS_CMD 0x88 2058 2059 #define IWM_SET_CALIB_DEFAULT_CMD 0x8e 2060 2061 #define IWM_BEACON_NOTIFICATION 0x90 2062 #define IWM_BEACON_TEMPLATE_CMD 0x91 2063 #define IWM_TX_ANT_CONFIGURATION_CMD 0x98 2064 #define IWM_BT_CONFIG 0x9b 2065 #define IWM_STATISTICS_NOTIFICATION 0x9d 2066 #define IWM_REDUCE_TX_POWER_CMD 0x9f 2067 2068 /* RF-KILL commands and notifications */ 2069 #define IWM_CARD_STATE_CMD 0xa0 2070 #define IWM_CARD_STATE_NOTIFICATION 0xa1 2071 2072 #define IWM_MISSED_BEACONS_NOTIFICATION 0xa2 2073 2074 #define IWM_MFUART_LOAD_NOTIFICATION 0xb1 2075 2076 /* Power - new power table command */ 2077 #define IWM_MAC_PM_POWER_TABLE 0xa9 2078 2079 #define IWM_REPLY_RX_PHY_CMD 0xc0 2080 #define IWM_REPLY_RX_MPDU_CMD 0xc1 2081 #define IWM_BA_NOTIF 0xc5 2082 2083 /* Location Aware Regulatory */ 2084 #define IWM_MCC_UPDATE_CMD 0xc8 2085 #define IWM_MCC_CHUB_UPDATE_CMD 0xc9 2086 2087 /* BT Coex */ 2088 #define IWM_BT_COEX_PRIO_TABLE 0xcc 2089 #define IWM_BT_COEX_PROT_ENV 0xcd 2090 #define IWM_BT_PROFILE_NOTIFICATION 0xce 2091 #define IWM_BT_COEX_CI 0x5d 2092 2093 #define IWM_REPLY_SF_CFG_CMD 0xd1 2094 #define IWM_REPLY_BEACON_FILTERING_CMD 0xd2 2095 2096 /* DTS measurements */ 2097 #define IWM_CMD_DTS_MEASUREMENT_TRIGGER 0xdc 2098 #define IWM_DTS_MEASUREMENT_NOTIFICATION 0xdd 2099 2100 #define IWM_REPLY_DEBUG_CMD 0xf0 2101 #define IWM_DEBUG_LOG_MSG 0xf7 2102 2103 #define IWM_MCAST_FILTER_CMD 0xd0 2104 2105 /* D3 commands/notifications */ 2106 #define IWM_D3_CONFIG_CMD 0xd3 2107 #define IWM_PROT_OFFLOAD_CONFIG_CMD 0xd4 2108 #define IWM_OFFLOADS_QUERY_CMD 0xd5 2109 #define IWM_REMOTE_WAKE_CONFIG_CMD 0xd6 2110 2111 /* for WoWLAN in particular */ 2112 #define IWM_WOWLAN_PATTERNS 0xe0 2113 #define IWM_WOWLAN_CONFIGURATION 0xe1 2114 #define IWM_WOWLAN_TSC_RSC_PARAM 0xe2 2115 #define IWM_WOWLAN_TKIP_PARAM 0xe3 2116 #define IWM_WOWLAN_KEK_KCK_MATERIAL 0xe4 2117 #define IWM_WOWLAN_GET_STATUSES 0xe5 2118 #define IWM_WOWLAN_TX_POWER_PER_DB 0xe6 2119 2120 /* and for NetDetect */ 2121 #define IWM_NET_DETECT_CONFIG_CMD 0x54 2122 #define IWM_NET_DETECT_PROFILES_QUERY_CMD 0x56 2123 #define IWM_NET_DETECT_PROFILES_CMD 0x57 2124 #define IWM_NET_DETECT_HOTSPOTS_CMD 0x58 2125 #define IWM_NET_DETECT_HOTSPOTS_QUERY_CMD 0x59 2126 2127 /* system group command IDs */ 2128 #define IWM_FSEQ_VER_MISMATCH_NOTIFICATION 0xff 2129 2130 #define IWM_REPLY_MAX 0xff 2131 2132 /* PHY_OPS subcommand IDs */ 2133 #define IWM_CMD_DTS_MEASUREMENT_TRIGGER_WIDE 0x0 2134 #define IWM_CTDP_CONFIG_CMD 0x03 2135 #define IWM_TEMP_REPORTING_THRESHOLDS_CMD 0x04 2136 #define IWM_CT_KILL_NOTIFICATION 0xFE 2137 #define IWM_DTS_MEASUREMENT_NOTIF_WIDE 0xFF 2138 2139 /* command groups */ 2140 #define IWM_LEGACY_GROUP 0x0 2141 #define IWM_LONG_GROUP 0x1 2142 #define IWM_SYSTEM_GROUP 0x2 2143 #define IWM_MAC_CONF_GROUP 0x3 2144 #define IWM_PHY_OPS_GROUP 0x4 2145 #define IWM_DATA_PATH_GROUP 0x5 2146 #define IWM_PROT_OFFLOAD_GROUP 0xb 2147 2148 /* SYSTEM_GROUP group subcommand IDs */ 2149 2150 #define IWM_SHARED_MEM_CFG_CMD 0x00 2151 #define IWM_SOC_CONFIGURATION_CMD 0x01 2152 #define IWM_INIT_EXTENDED_CFG_CMD 0x03 2153 #define IWM_FW_ERROR_RECOVERY_CMD 0x07 2154 2155 /* DATA_PATH group subcommand IDs */ 2156 #define IWM_DQA_ENABLE_CMD 0x00 2157 2158 /* 2159 * struct iwm_dqa_enable_cmd 2160 * @cmd_queue: the TXQ number of the command queue 2161 */ 2162 struct iwm_dqa_enable_cmd { 2163 uint32_t cmd_queue; 2164 } __packed; /* DQA_CONTROL_CMD_API_S_VER_1 */ 2165 2166 /** 2167 * struct iwm_cmd_response - generic response struct for most commands 2168 * @status: status of the command asked, changes for each one 2169 */ 2170 struct iwm_cmd_response { 2171 uint32_t status; 2172 }; 2173 2174 /* 2175 * struct iwm_tx_ant_cfg_cmd 2176 * @valid: valid antenna configuration 2177 */ 2178 struct iwm_tx_ant_cfg_cmd { 2179 uint32_t valid; 2180 } __packed; 2181 2182 /** 2183 * struct iwm_reduce_tx_power_cmd - TX power reduction command 2184 * IWM_REDUCE_TX_POWER_CMD = 0x9f 2185 * @flags: (reserved for future implementation) 2186 * @mac_context_id: id of the mac ctx for which we are reducing TX power. 2187 * @pwr_restriction: TX power restriction in dBms. 2188 */ 2189 struct iwm_reduce_tx_power_cmd { 2190 uint8_t flags; 2191 uint8_t mac_context_id; 2192 uint16_t pwr_restriction; 2193 } __packed; /* IWM_TX_REDUCED_POWER_API_S_VER_1 */ 2194 2195 /* 2196 * Calibration control struct. 2197 * Sent as part of the phy configuration command. 2198 * @flow_trigger: bitmap for which calibrations to perform according to 2199 * flow triggers. 2200 * @event_trigger: bitmap for which calibrations to perform according to 2201 * event triggers. 2202 */ 2203 struct iwm_calib_ctrl { 2204 uint32_t flow_trigger; 2205 uint32_t event_trigger; 2206 } __packed; 2207 2208 /* This defines the bitmap of various calibrations to enable in both 2209 * init ucode and runtime ucode through IWM_CALIBRATION_CFG_CMD. 2210 */ 2211 #define IWM_CALIB_CFG_XTAL_IDX (1 << 0) 2212 #define IWM_CALIB_CFG_TEMPERATURE_IDX (1 << 1) 2213 #define IWM_CALIB_CFG_VOLTAGE_READ_IDX (1 << 2) 2214 #define IWM_CALIB_CFG_PAPD_IDX (1 << 3) 2215 #define IWM_CALIB_CFG_TX_PWR_IDX (1 << 4) 2216 #define IWM_CALIB_CFG_DC_IDX (1 << 5) 2217 #define IWM_CALIB_CFG_BB_FILTER_IDX (1 << 6) 2218 #define IWM_CALIB_CFG_LO_LEAKAGE_IDX (1 << 7) 2219 #define IWM_CALIB_CFG_TX_IQ_IDX (1 << 8) 2220 #define IWM_CALIB_CFG_TX_IQ_SKEW_IDX (1 << 9) 2221 #define IWM_CALIB_CFG_RX_IQ_IDX (1 << 10) 2222 #define IWM_CALIB_CFG_RX_IQ_SKEW_IDX (1 << 11) 2223 #define IWM_CALIB_CFG_SENSITIVITY_IDX (1 << 12) 2224 #define IWM_CALIB_CFG_CHAIN_NOISE_IDX (1 << 13) 2225 #define IWM_CALIB_CFG_DISCONNECTED_ANT_IDX (1 << 14) 2226 #define IWM_CALIB_CFG_ANT_COUPLING_IDX (1 << 15) 2227 #define IWM_CALIB_CFG_DAC_IDX (1 << 16) 2228 #define IWM_CALIB_CFG_ABS_IDX (1 << 17) 2229 #define IWM_CALIB_CFG_AGC_IDX (1 << 18) 2230 2231 /* 2232 * Phy configuration command. 2233 */ 2234 struct iwm_phy_cfg_cmd { 2235 uint32_t phy_cfg; 2236 struct iwm_calib_ctrl calib_control; 2237 } __packed; 2238 2239 #define IWM_PHY_CFG_RADIO_TYPE ((1 << 0) | (1 << 1)) 2240 #define IWM_PHY_CFG_RADIO_STEP ((1 << 2) | (1 << 3)) 2241 #define IWM_PHY_CFG_RADIO_DASH ((1 << 4) | (1 << 5)) 2242 #define IWM_PHY_CFG_PRODUCT_NUMBER ((1 << 6) | (1 << 7)) 2243 #define IWM_PHY_CFG_TX_CHAIN_A (1 << 8) 2244 #define IWM_PHY_CFG_TX_CHAIN_B (1 << 9) 2245 #define IWM_PHY_CFG_TX_CHAIN_C (1 << 10) 2246 #define IWM_PHY_CFG_RX_CHAIN_A (1 << 12) 2247 #define IWM_PHY_CFG_RX_CHAIN_B (1 << 13) 2248 #define IWM_PHY_CFG_RX_CHAIN_C (1 << 14) 2249 2250 #define IWM_MAX_DTS_TRIPS 8 2251 2252 /** 2253 * struct iwm_ct_kill_notif - CT-kill entry notification 2254 * 2255 * @temperature: the current temperature in celsius 2256 * @reserved: reserved 2257 */ 2258 struct iwm_ct_kill_notif { 2259 uint16_t temperature; 2260 uint16_t reserved; 2261 } __packed; /* GRP_PHY_CT_KILL_NTF */ 2262 2263 /** 2264 * struct iwm_temp_report_ths_cmd - set temperature thresholds 2265 * (IWM_TEMP_REPORTING_THRESHOLDS_CMD) 2266 * 2267 * @num_temps: number of temperature thresholds passed 2268 * @thresholds: array with the thresholds to be configured 2269 */ 2270 struct iwm_temp_report_ths_cmd { 2271 uint32_t num_temps; 2272 uint16_t thresholds[IWM_MAX_DTS_TRIPS]; 2273 } __packed; /* GRP_PHY_TEMP_REPORTING_THRESHOLDS_CMD */ 2274 2275 /* 2276 * PHY db 2277 */ 2278 2279 enum iwm_phy_db_section_type { 2280 IWM_PHY_DB_CFG = 1, 2281 IWM_PHY_DB_CALIB_NCH, 2282 IWM_PHY_DB_UNUSED, 2283 IWM_PHY_DB_CALIB_CHG_PAPD, 2284 IWM_PHY_DB_CALIB_CHG_TXP, 2285 IWM_PHY_DB_MAX 2286 }; 2287 2288 /* 2289 * phy db - configure operational ucode 2290 */ 2291 struct iwm_phy_db_cmd { 2292 uint16_t type; 2293 uint16_t length; 2294 uint8_t data[]; 2295 } __packed; 2296 2297 /* for parsing of tx power channel group data that comes from the firmware*/ 2298 struct iwm_phy_db_chg_txp { 2299 uint32_t space; 2300 uint16_t max_channel_idx; 2301 } __packed; 2302 2303 /* 2304 * phy db - Receive phy db chunk after calibrations 2305 */ 2306 struct iwm_calib_res_notif_phy_db { 2307 uint16_t type; 2308 uint16_t length; 2309 uint8_t data[]; 2310 } __packed; 2311 2312 /* 7k family NVM HW-Section offset (in words) definitions */ 2313 #define IWM_HW_ADDR 0x15 2314 /* 7k family NVM SW-Section offset (in words) definitions */ 2315 #define IWM_NVM_SW_SECTION 0x1C0 2316 #define IWM_NVM_VERSION 0 2317 #define IWM_RADIO_CFG 1 2318 #define IWM_SKU 2 2319 #define IWM_N_HW_ADDRS 3 2320 #define IWM_NVM_CHANNELS 0x1E0 - IWM_NVM_SW_SECTION 2321 /* 7k family NVM calibration section offset (in words) definitions */ 2322 #define IWM_NVM_CALIB_SECTION 0x2B8 2323 #define IWM_XTAL_CALIB (0x316 - IWM_NVM_CALIB_SECTION) 2324 2325 /* 8k family NVM HW-Section offset (in words) definitions */ 2326 #define IWM_HW_ADDR0_WFPM_8000 0x12 2327 #define IWM_HW_ADDR1_WFPM_8000 0x16 2328 #define IWM_HW_ADDR0_PCIE_8000 0x8A 2329 #define IWM_HW_ADDR1_PCIE_8000 0x8E 2330 #define IWM_MAC_ADDRESS_OVERRIDE_8000 1 2331 2332 /* 8k family NVM SW-Section offset (in words) definitions */ 2333 #define IWM_NVM_SW_SECTION_8000 0x1C0 2334 #define IWM_NVM_VERSION_8000 0 2335 #define IWM_RADIO_CFG_8000 0 2336 #define IWM_SKU_8000 2 2337 #define IWM_N_HW_ADDRS_8000 3 2338 2339 /* 8k family NVM REGULATORY -Section offset (in words) definitions */ 2340 #define IWM_NVM_CHANNELS_8000 0 2341 #define IWM_NVM_LAR_OFFSET_8000_OLD 0x4C7 2342 #define IWM_NVM_LAR_OFFSET_8000 0x507 2343 #define IWM_NVM_LAR_ENABLED_8000 0x7 2344 2345 /* 8k family NVM calibration section offset (in words) definitions */ 2346 #define IWM_NVM_CALIB_SECTION_8000 0x2B8 2347 #define IWM_XTAL_CALIB_8000 (0x316 - IWM_NVM_CALIB_SECTION_8000) 2348 2349 /* SKU Capabilities (actual values from NVM definition) */ 2350 #define IWM_NVM_SKU_CAP_BAND_24GHZ (1 << 0) 2351 #define IWM_NVM_SKU_CAP_BAND_52GHZ (1 << 1) 2352 #define IWM_NVM_SKU_CAP_11N_ENABLE (1 << 2) 2353 #define IWM_NVM_SKU_CAP_11AC_ENABLE (1 << 3) 2354 #define IWM_NVM_SKU_CAP_MIMO_DISABLE (1 << 5) 2355 2356 /* radio config bits (actual values from NVM definition) */ 2357 #define IWM_NVM_RF_CFG_DASH_MSK(x) (x & 0x3) /* bits 0-1 */ 2358 #define IWM_NVM_RF_CFG_STEP_MSK(x) ((x >> 2) & 0x3) /* bits 2-3 */ 2359 #define IWM_NVM_RF_CFG_TYPE_MSK(x) ((x >> 4) & 0x3) /* bits 4-5 */ 2360 #define IWM_NVM_RF_CFG_PNUM_MSK(x) ((x >> 6) & 0x3) /* bits 6-7 */ 2361 #define IWM_NVM_RF_CFG_TX_ANT_MSK(x) ((x >> 8) & 0xF) /* bits 8-11 */ 2362 #define IWM_NVM_RF_CFG_RX_ANT_MSK(x) ((x >> 12) & 0xF) /* bits 12-15 */ 2363 2364 #define IWM_NVM_RF_CFG_PNUM_MSK_8000(x) (x & 0xF) 2365 #define IWM_NVM_RF_CFG_DASH_MSK_8000(x) ((x >> 4) & 0xF) 2366 #define IWM_NVM_RF_CFG_STEP_MSK_8000(x) ((x >> 8) & 0xF) 2367 #define IWM_NVM_RF_CFG_TYPE_MSK_8000(x) ((x >> 12) & 0xFFF) 2368 #define IWM_NVM_RF_CFG_TX_ANT_MSK_8000(x) ((x >> 24) & 0xF) 2369 #define IWM_NVM_RF_CFG_RX_ANT_MSK_8000(x) ((x >> 28) & 0xF) 2370 2371 /* 2372 * channel flags in NVM 2373 * @IWM_NVM_CHANNEL_VALID: channel is usable for this SKU/geo 2374 * @IWM_NVM_CHANNEL_IBSS: usable as an IBSS channel 2375 * @IWM_NVM_CHANNEL_ACTIVE: active scanning allowed 2376 * @IWM_NVM_CHANNEL_RADAR: radar detection required 2377 * @IWM_NVM_CHANNEL_DFS: dynamic freq selection candidate 2378 * @IWM_NVM_CHANNEL_WIDE: 20 MHz channel okay (?) 2379 * @IWM_NVM_CHANNEL_40MHZ: 40 MHz channel okay (?) 2380 * @IWM_NVM_CHANNEL_80MHZ: 80 MHz channel okay (?) 2381 * @IWM_NVM_CHANNEL_160MHZ: 160 MHz channel okay (?) 2382 */ 2383 #define IWM_NVM_CHANNEL_VALID (1 << 0) 2384 #define IWM_NVM_CHANNEL_IBSS (1 << 1) 2385 #define IWM_NVM_CHANNEL_ACTIVE (1 << 3) 2386 #define IWM_NVM_CHANNEL_RADAR (1 << 4) 2387 #define IWM_NVM_CHANNEL_DFS (1 << 7) 2388 #define IWM_NVM_CHANNEL_WIDE (1 << 8) 2389 #define IWM_NVM_CHANNEL_40MHZ (1 << 9) 2390 #define IWM_NVM_CHANNEL_80MHZ (1 << 10) 2391 #define IWM_NVM_CHANNEL_160MHZ (1 << 11) 2392 2393 /* Target of the IWM_NVM_ACCESS_CMD */ 2394 #define IWM_NVM_ACCESS_TARGET_CACHE 0 2395 #define IWM_NVM_ACCESS_TARGET_OTP 1 2396 #define IWM_NVM_ACCESS_TARGET_EEPROM 2 2397 2398 /* Section types for IWM_NVM_ACCESS_CMD */ 2399 #define IWM_NVM_SECTION_TYPE_HW 0 2400 #define IWM_NVM_SECTION_TYPE_SW 1 2401 #define IWM_NVM_SECTION_TYPE_PAPD 2 2402 #define IWM_NVM_SECTION_TYPE_REGULATORY 3 2403 #define IWM_NVM_SECTION_TYPE_CALIBRATION 4 2404 #define IWM_NVM_SECTION_TYPE_PRODUCTION 5 2405 #define IWM_NVM_SECTION_TYPE_POST_FCS_CALIB 6 2406 /* 7 unknown */ 2407 #define IWM_NVM_SECTION_TYPE_REGULATORY_SDP 8 2408 /* 9 unknown */ 2409 #define IWM_NVM_SECTION_TYPE_HW_8000 10 2410 #define IWM_NVM_SECTION_TYPE_MAC_OVERRIDE 11 2411 #define IWM_NVM_SECTION_TYPE_PHY_SKU 12 2412 #define IWM_NVM_NUM_OF_SECTIONS 13 2413 2414 /** 2415 * struct iwm_nvm_access_cmd_ver2 - Request the device to send an NVM section 2416 * @op_code: 0 - read, 1 - write 2417 * @target: IWM_NVM_ACCESS_TARGET_* 2418 * @type: IWM_NVM_SECTION_TYPE_* 2419 * @offset: offset in bytes into the section 2420 * @length: in bytes, to read/write 2421 * @data: if write operation, the data to write. On read its empty 2422 */ 2423 struct iwm_nvm_access_cmd { 2424 uint8_t op_code; 2425 uint8_t target; 2426 uint16_t type; 2427 uint16_t offset; 2428 uint16_t length; 2429 uint8_t data[]; 2430 } __packed; /* IWM_NVM_ACCESS_CMD_API_S_VER_2 */ 2431 2432 /* 2433 * Block paging calculations 2434 */ 2435 #define IWM_PAGE_2_EXP_SIZE 12 /* 4K == 2^12 */ 2436 #define IWM_FW_PAGING_SIZE (1 << IWM_PAGE_2_EXP_SIZE) /* page size is 4KB */ 2437 #define IWM_PAGE_PER_GROUP_2_EXP_SIZE 3 2438 /* 8 pages per group */ 2439 #define IWM_NUM_OF_PAGE_PER_GROUP (1 << IWM_PAGE_PER_GROUP_2_EXP_SIZE) 2440 /* don't change, support only 32KB size */ 2441 #define IWM_PAGING_BLOCK_SIZE (IWM_NUM_OF_PAGE_PER_GROUP * IWM_FW_PAGING_SIZE) 2442 /* 32K == 2^15 */ 2443 #define IWM_BLOCK_2_EXP_SIZE (IWM_PAGE_2_EXP_SIZE + IWM_PAGE_PER_GROUP_2_EXP_SIZE) 2444 2445 /* 2446 * Image paging calculations 2447 */ 2448 #define IWM_BLOCK_PER_IMAGE_2_EXP_SIZE 5 2449 /* 2^5 == 32 blocks per image */ 2450 #define IWM_NUM_OF_BLOCK_PER_IMAGE (1 << IWM_BLOCK_PER_IMAGE_2_EXP_SIZE) 2451 /* maximum image size 1024KB */ 2452 #define IWM_MAX_PAGING_IMAGE_SIZE (IWM_NUM_OF_BLOCK_PER_IMAGE * IWM_PAGING_BLOCK_SIZE) 2453 2454 /* Virtual address signature */ 2455 #define IWM_PAGING_ADDR_SIG 0xAA000000 2456 2457 #define IWM_PAGING_CMD_IS_SECURED (1 << 9) 2458 #define IWM_PAGING_CMD_IS_ENABLED (1 << 8) 2459 #define IWM_PAGING_CMD_NUM_OF_PAGES_IN_LAST_GRP_POS 0 2460 #define IWM_PAGING_TLV_SECURE_MASK 1 2461 2462 #define IWM_NUM_OF_FW_PAGING_BLOCKS 33 /* 32 for data and 1 block for CSS */ 2463 2464 /* 2465 * struct iwm_fw_paging_cmd - paging layout 2466 * 2467 * (IWM_FW_PAGING_BLOCK_CMD = 0x4f) 2468 * 2469 * Send to FW the paging layout in the driver. 2470 * 2471 * @flags: various flags for the command 2472 * @block_size: the block size in powers of 2 2473 * @block_num: number of blocks specified in the command. 2474 * @device_phy_addr: virtual addresses from device side 2475 */ 2476 struct iwm_fw_paging_cmd { 2477 uint32_t flags; 2478 uint32_t block_size; 2479 uint32_t block_num; 2480 uint32_t device_phy_addr[IWM_NUM_OF_FW_PAGING_BLOCKS]; 2481 } __packed; /* IWM_FW_PAGING_BLOCK_CMD_API_S_VER_1 */ 2482 2483 /** 2484 * struct iwm_nvm_access_resp_ver2 - response to IWM_NVM_ACCESS_CMD 2485 * @offset: offset in bytes into the section 2486 * @length: in bytes, either how much was written or read 2487 * @type: IWM_NVM_SECTION_TYPE_* 2488 * @status: 0 for success, fail otherwise 2489 * @data: if read operation, the data returned. Empty on write. 2490 */ 2491 struct iwm_nvm_access_resp { 2492 uint16_t offset; 2493 uint16_t length; 2494 uint16_t type; 2495 uint16_t status; 2496 uint8_t data[]; 2497 } __packed; /* IWM_NVM_ACCESS_CMD_RESP_API_S_VER_2 */ 2498 2499 /* IWM_ALIVE 0x1 */ 2500 2501 /* alive response is_valid values */ 2502 #define IWM_ALIVE_RESP_UCODE_OK (1 << 0) 2503 #define IWM_ALIVE_RESP_RFKILL (1 << 1) 2504 2505 /* alive response ver_type values */ 2506 #define IWM_FW_TYPE_HW 0 2507 #define IWM_FW_TYPE_PROT 1 2508 #define IWM_FW_TYPE_AP 2 2509 #define IWM_FW_TYPE_WOWLAN 3 2510 #define IWM_FW_TYPE_TIMING 4 2511 #define IWM_FW_TYPE_WIPAN 5 2512 2513 /* alive response ver_subtype values */ 2514 #define IWM_FW_SUBTYPE_FULL_FEATURE 0 2515 #define IWM_FW_SUBTYPE_BOOTSRAP 1 /* Not valid */ 2516 #define IWM_FW_SUBTYPE_REDUCED 2 2517 #define IWM_FW_SUBTYPE_ALIVE_ONLY 3 2518 #define IWM_FW_SUBTYPE_WOWLAN 4 2519 #define IWM_FW_SUBTYPE_AP_SUBTYPE 5 2520 #define IWM_FW_SUBTYPE_WIPAN 6 2521 #define IWM_FW_SUBTYPE_INITIALIZE 9 2522 2523 #define IWM_ALIVE_STATUS_ERR 0xDEAD 2524 #define IWM_ALIVE_STATUS_OK 0xCAFE 2525 2526 #define IWM_ALIVE_FLG_RFKILL (1 << 0) 2527 2528 struct iwm_lmac_alive { 2529 uint32_t ucode_major; 2530 uint32_t ucode_minor; 2531 uint8_t ver_subtype; 2532 uint8_t ver_type; 2533 uint8_t mac; 2534 uint8_t opt; 2535 uint32_t timestamp; 2536 uint32_t error_event_table_ptr; /* SRAM address for error log */ 2537 uint32_t log_event_table_ptr; /* SRAM address for LMAC event log */ 2538 uint32_t cpu_register_ptr; 2539 uint32_t dbgm_config_ptr; 2540 uint32_t alive_counter_ptr; 2541 uint32_t scd_base_ptr; /* SRAM address for SCD */ 2542 uint32_t st_fwrd_addr; /* pointer to Store and forward */ 2543 uint32_t st_fwrd_size; 2544 } __packed; /* UCODE_ALIVE_NTFY_API_S_VER_3 */ 2545 2546 struct iwm_umac_alive { 2547 uint32_t umac_major; /* UMAC version: major */ 2548 uint32_t umac_minor; /* UMAC version: minor */ 2549 uint32_t error_info_addr; /* SRAM address for UMAC error log */ 2550 uint32_t dbg_print_buff_addr; 2551 } __packed; /* UMAC_ALIVE_DATA_API_S_VER_2 */ 2552 2553 struct iwm_alive_resp_v3 { 2554 uint16_t status; 2555 uint16_t flags; 2556 struct iwm_lmac_alive lmac_data; 2557 struct iwm_umac_alive umac_data; 2558 } __packed; /* ALIVE_RES_API_S_VER_3 */ 2559 2560 struct iwm_alive_resp { 2561 uint16_t status; 2562 uint16_t flags; 2563 struct iwm_lmac_alive lmac_data[2]; 2564 struct iwm_umac_alive umac_data; 2565 }__packed; /* ALIVE_RES_API_S_VER_4 */ 2566 2567 2568 #define IWM_SOC_CONFIG_CMD_FLAGS_DISCRETE (1 << 0) 2569 #define IWM_SOC_CONFIG_CMD_FLAGS_LOW_LATENCY (1 << 1) 2570 2571 #define IWM_SOC_FLAGS_LTR_APPLY_DELAY_MASK 0xc 2572 #define IWM_SOC_FLAGS_LTR_APPLY_DELAY_NONE 0 2573 #define IWM_SOC_FLAGS_LTR_APPLY_DELAY_200 1 2574 #define IWM_SOC_FLAGS_LTR_APPLY_DELAY_2500 2 2575 #define IWM_SOC_FLAGS_LTR_APPLY_DELAY_1820 3 2576 2577 /** 2578 * struct iwm_soc_configuration_cmd - Set device stabilization latency 2579 * 2580 * @flags: soc settings flags. In VER_1, we can only set the DISCRETE 2581 * flag, because the FW treats the whole value as an integer. In 2582 * VER_2, we can set the bits independently. 2583 * @latency: time for SOC to ensure stable power & XTAL 2584 */ 2585 struct iwm_soc_configuration_cmd { 2586 uint32_t flags; 2587 uint32_t latency; 2588 } __packed; /* 2589 * SOC_CONFIGURATION_CMD_S_VER_1 (see description above) 2590 * SOC_CONFIGURATION_CMD_S_VER_2 2591 */ 2592 2593 2594 /* Error response/notification */ 2595 #define IWM_FW_ERR_UNKNOWN_CMD 0x0 2596 #define IWM_FW_ERR_INVALID_CMD_PARAM 0x1 2597 #define IWM_FW_ERR_SERVICE 0x2 2598 #define IWM_FW_ERR_ARC_MEMORY 0x3 2599 #define IWM_FW_ERR_ARC_CODE 0x4 2600 #define IWM_FW_ERR_WATCH_DOG 0x5 2601 #define IWM_FW_ERR_WEP_GRP_KEY_INDX 0x10 2602 #define IWM_FW_ERR_WEP_KEY_SIZE 0x11 2603 #define IWM_FW_ERR_OBSOLETE_FUNC 0x12 2604 #define IWM_FW_ERR_UNEXPECTED 0xFE 2605 #define IWM_FW_ERR_FATAL 0xFF 2606 2607 /** 2608 * struct iwm_error_resp - FW error indication 2609 * ( IWM_REPLY_ERROR = 0x2 ) 2610 * @error_type: one of IWM_FW_ERR_* 2611 * @cmd_id: the command ID for which the error occurred 2612 * @bad_cmd_seq_num: sequence number of the erroneous command 2613 * @error_service: which service created the error, applicable only if 2614 * error_type = 2, otherwise 0 2615 * @timestamp: TSF in usecs. 2616 */ 2617 struct iwm_error_resp { 2618 uint32_t error_type; 2619 uint8_t cmd_id; 2620 uint8_t reserved1; 2621 uint16_t bad_cmd_seq_num; 2622 uint32_t error_service; 2623 uint64_t timestamp; 2624 } __packed; 2625 2626 #define IWM_FW_CMD_VER_UNKNOWN 99 2627 2628 /** 2629 * struct iwm_fw_cmd_version - firmware command version entry 2630 * @cmd: command ID 2631 * @group: group ID 2632 * @cmd_ver: command version 2633 * @notif_ver: notification version 2634 */ 2635 struct iwm_fw_cmd_version { 2636 uint8_t cmd; 2637 uint8_t group; 2638 uint8_t cmd_ver; 2639 uint8_t notif_ver; 2640 } __packed; 2641 2642 2643 /* Common PHY, MAC and Bindings definitions */ 2644 2645 #define IWM_MAX_MACS_IN_BINDING (3) 2646 #define IWM_MAX_BINDINGS (4) 2647 #define IWM_AUX_BINDING_INDEX (3) 2648 #define IWM_MAX_PHYS (4) 2649 2650 /* Used to extract ID and color from the context dword */ 2651 #define IWM_FW_CTXT_ID_POS (0) 2652 #define IWM_FW_CTXT_ID_MSK (0xff << IWM_FW_CTXT_ID_POS) 2653 #define IWM_FW_CTXT_COLOR_POS (8) 2654 #define IWM_FW_CTXT_COLOR_MSK (0xff << IWM_FW_CTXT_COLOR_POS) 2655 #define IWM_FW_CTXT_INVALID (0xffffffff) 2656 2657 #define IWM_FW_CMD_ID_AND_COLOR(_id, _color) ((_id << IWM_FW_CTXT_ID_POS) |\ 2658 (_color << IWM_FW_CTXT_COLOR_POS)) 2659 2660 /* Possible actions on PHYs, MACs and Bindings */ 2661 #define IWM_FW_CTXT_ACTION_STUB 0 2662 #define IWM_FW_CTXT_ACTION_ADD 1 2663 #define IWM_FW_CTXT_ACTION_MODIFY 2 2664 #define IWM_FW_CTXT_ACTION_REMOVE 3 2665 #define IWM_FW_CTXT_ACTION_NUM 4 2666 /* COMMON_CONTEXT_ACTION_API_E_VER_1 */ 2667 2668 /* Time Events */ 2669 2670 /* Time Event types, according to MAC type */ 2671 2672 /* BSS Station Events */ 2673 #define IWM_TE_BSS_STA_AGGRESSIVE_ASSOC 0 2674 #define IWM_TE_BSS_STA_ASSOC 1 2675 #define IWM_TE_BSS_EAP_DHCP_PROT 2 2676 #define IWM_TE_BSS_QUIET_PERIOD 3 2677 2678 /* P2P Device Events */ 2679 #define IWM_TE_P2P_DEVICE_DISCOVERABLE 4 2680 #define IWM_TE_P2P_DEVICE_LISTEN 5 2681 #define IWM_TE_P2P_DEVICE_ACTION_SCAN 6 2682 #define IWM_TE_P2P_DEVICE_FULL_SCAN 7 2683 2684 /* P2P Client Events */ 2685 #define IWM_TE_P2P_CLIENT_AGGRESSIVE_ASSOC 8 2686 #define IWM_TE_P2P_CLIENT_ASSOC 9 2687 #define IWM_TE_P2P_CLIENT_QUIET_PERIOD 10 2688 2689 /* P2P GO Events */ 2690 #define IWM_TE_P2P_GO_ASSOC_PROT 11 2691 #define IWM_TE_P2P_GO_REPETITIVE_NOA 12 2692 #define IWM_TE_P2P_GO_CT_WINDOW 13 2693 2694 /* WiDi Sync Events */ 2695 #define IWM_TE_WIDI_TX_SYNC 14 2696 2697 #define IWM_TE_MAX 15 2698 /* IWM_MAC_EVENT_TYPE_API_E_VER_1 */ 2699 2700 2701 2702 /* Time event - defines for command API v1 */ 2703 2704 /* 2705 * @IWM_TE_V1_FRAG_NONE: fragmentation of the time event is NOT allowed. 2706 * @IWM_TE_V1_FRAG_SINGLE: fragmentation of the time event is allowed, but only 2707 * the first fragment is scheduled. 2708 * @IWM_TE_V1_FRAG_DUAL: fragmentation of the time event is allowed, but only 2709 * the first 2 fragments are scheduled. 2710 * @IWM_TE_V1_FRAG_ENDLESS: fragmentation of the time event is allowed, and any 2711 * number of fragments are valid. 2712 * 2713 * Other than the constant defined above, specifying a fragmentation value 'x' 2714 * means that the event can be fragmented but only the first 'x' will be 2715 * scheduled. 2716 */ 2717 #define IWM_TE_V1_FRAG_NONE 0 2718 #define IWM_TE_V1_FRAG_SINGLE 1 2719 #define IWM_TE_V1_FRAG_DUAL 2 2720 #define IWM_TE_V1_FRAG_ENDLESS 0xffffffff 2721 2722 /* If a Time Event can be fragmented, this is the max number of fragments */ 2723 #define IWM_TE_V1_FRAG_MAX_MSK 0x0fffffff 2724 /* Repeat the time event endlessly (until removed) */ 2725 #define IWM_TE_V1_REPEAT_ENDLESS 0xffffffff 2726 /* If a Time Event has bounded repetitions, this is the maximal value */ 2727 #define IWM_TE_V1_REPEAT_MAX_MSK_V1 0x0fffffff 2728 2729 /* Time Event dependencies: none, on another TE, or in a specific time */ 2730 #define IWM_TE_V1_INDEPENDENT 0 2731 #define IWM_TE_V1_DEP_OTHER (1 << 0) 2732 #define IWM_TE_V1_DEP_TSF (1 << 1) 2733 #define IWM_TE_V1_EVENT_SOCIOPATHIC (1 << 2) 2734 /* IWM_MAC_EVENT_DEPENDENCY_POLICY_API_E_VER_2 */ 2735 2736 /* 2737 * @IWM_TE_V1_NOTIF_NONE: no notifications 2738 * @IWM_TE_V1_NOTIF_HOST_EVENT_START: request/receive notification on event start 2739 * @IWM_TE_V1_NOTIF_HOST_EVENT_END:request/receive notification on event end 2740 * @IWM_TE_V1_NOTIF_INTERNAL_EVENT_START: internal FW use 2741 * @IWM_TE_V1_NOTIF_INTERNAL_EVENT_END: internal FW use. 2742 * @IWM_TE_V1_NOTIF_HOST_FRAG_START: request/receive notification on frag start 2743 * @IWM_TE_V1_NOTIF_HOST_FRAG_END:request/receive notification on frag end 2744 * @IWM_TE_V1_NOTIF_INTERNAL_FRAG_START: internal FW use. 2745 * @IWM_TE_V1_NOTIF_INTERNAL_FRAG_END: internal FW use. 2746 * 2747 * Supported Time event notifications configuration. 2748 * A notification (both event and fragment) includes a status indicating weather 2749 * the FW was able to schedule the event or not. For fragment start/end 2750 * notification the status is always success. There is no start/end fragment 2751 * notification for monolithic events. 2752 */ 2753 #define IWM_TE_V1_NOTIF_NONE 0 2754 #define IWM_TE_V1_NOTIF_HOST_EVENT_START (1 << 0) 2755 #define IWM_TE_V1_NOTIF_HOST_EVENT_END (1 << 1) 2756 #define IWM_TE_V1_NOTIF_INTERNAL_EVENT_START (1 << 2) 2757 #define IWM_TE_V1_NOTIF_INTERNAL_EVENT_END (1 << 3) 2758 #define IWM_TE_V1_NOTIF_HOST_FRAG_START (1 << 4) 2759 #define IWM_TE_V1_NOTIF_HOST_FRAG_END (1 << 5) 2760 #define IWM_TE_V1_NOTIF_INTERNAL_FRAG_START (1 << 6) 2761 #define IWM_TE_V1_NOTIF_INTERNAL_FRAG_END (1 << 7) 2762 /* IWM_MAC_EVENT_ACTION_API_E_VER_2 */ 2763 2764 2765 /* Time event - defines for command API */ 2766 2767 /** 2768 * DOC: Time Events - what is it? 2769 * 2770 * Time Events are a fw feature that allows the driver to control the presence 2771 * of the device on the channel. Since the fw supports multiple channels 2772 * concurrently, the fw may choose to jump to another channel at any time. 2773 * In order to make sure that the fw is on a specific channel at a certain time 2774 * and for a certain duration, the driver needs to issue a time event. 2775 * 2776 * The simplest example is for BSS association. The driver issues a time event, 2777 * waits for it to start, and only then tells mac80211 that we can start the 2778 * association. This way, we make sure that the association will be done 2779 * smoothly and won't be interrupted by channel switch decided within the fw. 2780 */ 2781 2782 /** 2783 * DOC: The flow against the fw 2784 * 2785 * When the driver needs to make sure we are in a certain channel, at a certain 2786 * time and for a certain duration, it sends a Time Event. The flow against the 2787 * fw goes like this: 2788 * 1) Driver sends a TIME_EVENT_CMD to the fw 2789 * 2) Driver gets the response for that command. This response contains the 2790 * Unique ID (UID) of the event. 2791 * 3) The fw sends notification when the event starts. 2792 * 2793 * Of course the API provides various options that allow to cover parameters 2794 * of the flow. 2795 * What is the duration of the event? 2796 * What is the start time of the event? 2797 * Is there an end-time for the event? 2798 * How much can the event be delayed? 2799 * Can the event be split? 2800 * If yes what is the maximal number of chunks? 2801 * etc... 2802 */ 2803 2804 /* 2805 * @IWM_TE_V2_FRAG_NONE: fragmentation of the time event is NOT allowed. 2806 * @IWM_TE_V2_FRAG_SINGLE: fragmentation of the time event is allowed, but only 2807 * the first fragment is scheduled. 2808 * @IWM_TE_V2_FRAG_DUAL: fragmentation of the time event is allowed, but only 2809 * the first 2 fragments are scheduled. 2810 * @IWM_TE_V2_FRAG_ENDLESS: fragmentation of the time event is allowed, and any 2811 * number of fragments are valid. 2812 * 2813 * Other than the constant defined above, specifying a fragmentation value 'x' 2814 * means that the event can be fragmented but only the first 'x' will be 2815 * scheduled. 2816 */ 2817 #define IWM_TE_V2_FRAG_NONE 0 2818 #define IWM_TE_V2_FRAG_SINGLE 1 2819 #define IWM_TE_V2_FRAG_DUAL 2 2820 #define IWM_TE_V2_FRAG_MAX 0xfe 2821 #define IWM_TE_V2_FRAG_ENDLESS 0xff 2822 2823 /* Repeat the time event endlessly (until removed) */ 2824 #define IWM_TE_V2_REPEAT_ENDLESS 0xff 2825 /* If a Time Event has bounded repetitions, this is the maximal value */ 2826 #define IWM_TE_V2_REPEAT_MAX 0xfe 2827 2828 #define IWM_TE_V2_PLACEMENT_POS 12 2829 #define IWM_TE_V2_ABSENCE_POS 15 2830 2831 /* Time event policy values 2832 * A notification (both event and fragment) includes a status indicating weather 2833 * the FW was able to schedule the event or not. For fragment start/end 2834 * notification the status is always success. There is no start/end fragment 2835 * notification for monolithic events. 2836 * 2837 * @IWM_TE_V2_DEFAULT_POLICY: independent, social, present, unoticable 2838 * @IWM_TE_V2_NOTIF_HOST_EVENT_START: request/receive notification on event start 2839 * @IWM_TE_V2_NOTIF_HOST_EVENT_END:request/receive notification on event end 2840 * @IWM_TE_V2_NOTIF_INTERNAL_EVENT_START: internal FW use 2841 * @IWM_TE_V2_NOTIF_INTERNAL_EVENT_END: internal FW use. 2842 * @IWM_TE_V2_NOTIF_HOST_FRAG_START: request/receive notification on frag start 2843 * @IWM_TE_V2_NOTIF_HOST_FRAG_END:request/receive notification on frag end 2844 * @IWM_TE_V2_NOTIF_INTERNAL_FRAG_START: internal FW use. 2845 * @IWM_TE_V2_NOTIF_INTERNAL_FRAG_END: internal FW use. 2846 * @IWM_TE_V2_DEP_OTHER: depends on another time event 2847 * @IWM_TE_V2_DEP_TSF: depends on a specific time 2848 * @IWM_TE_V2_EVENT_SOCIOPATHIC: can't co-exist with other events of tha same MAC 2849 * @IWM_TE_V2_ABSENCE: are we present or absent during the Time Event. 2850 */ 2851 #define IWM_TE_V2_DEFAULT_POLICY 0x0 2852 2853 /* notifications (event start/stop, fragment start/stop) */ 2854 #define IWM_TE_V2_NOTIF_HOST_EVENT_START (1 << 0) 2855 #define IWM_TE_V2_NOTIF_HOST_EVENT_END (1 << 1) 2856 #define IWM_TE_V2_NOTIF_INTERNAL_EVENT_START (1 << 2) 2857 #define IWM_TE_V2_NOTIF_INTERNAL_EVENT_END (1 << 3) 2858 2859 #define IWM_TE_V2_NOTIF_HOST_FRAG_START (1 << 4) 2860 #define IWM_TE_V2_NOTIF_HOST_FRAG_END (1 << 5) 2861 #define IWM_TE_V2_NOTIF_INTERNAL_FRAG_START (1 << 6) 2862 #define IWM_TE_V2_NOTIF_INTERNAL_FRAG_END (1 << 7) 2863 #define IWM_T2_V2_START_IMMEDIATELY (1 << 11) 2864 2865 #define IWM_TE_V2_NOTIF_MSK 0xff 2866 2867 /* placement characteristics */ 2868 #define IWM_TE_V2_DEP_OTHER (1 << IWM_TE_V2_PLACEMENT_POS) 2869 #define IWM_TE_V2_DEP_TSF (1 << (IWM_TE_V2_PLACEMENT_POS + 1)) 2870 #define IWM_TE_V2_EVENT_SOCIOPATHIC (1 << (IWM_TE_V2_PLACEMENT_POS + 2)) 2871 2872 /* are we present or absent during the Time Event. */ 2873 #define IWM_TE_V2_ABSENCE (1 << IWM_TE_V2_ABSENCE_POS) 2874 2875 /** 2876 * struct iwm_time_event_cmd_api - configuring Time Events 2877 * with struct IWM_MAC_TIME_EVENT_DATA_API_S_VER_2 (see also 2878 * with version 1. determined by IWM_UCODE_TLV_FLAGS) 2879 * ( IWM_TIME_EVENT_CMD = 0x29 ) 2880 * @id_and_color: ID and color of the relevant MAC 2881 * @action: action to perform, one of IWM_FW_CTXT_ACTION_* 2882 * @id: this field has two meanings, depending on the action: 2883 * If the action is ADD, then it means the type of event to add. 2884 * For all other actions it is the unique event ID assigned when the 2885 * event was added by the FW. 2886 * @apply_time: When to start the Time Event (in GP2) 2887 * @max_delay: maximum delay to event's start (apply time), in TU 2888 * @depends_on: the unique ID of the event we depend on (if any) 2889 * @interval: interval between repetitions, in TU 2890 * @duration: duration of event in TU 2891 * @repeat: how many repetitions to do, can be IWM_TE_REPEAT_ENDLESS 2892 * @max_frags: maximal number of fragments the Time Event can be divided to 2893 * @policy: defines whether uCode shall notify the host or other uCode modules 2894 * on event and/or fragment start and/or end 2895 * using one of IWM_TE_INDEPENDENT, IWM_TE_DEP_OTHER, IWM_TE_DEP_TSF 2896 * IWM_TE_EVENT_SOCIOPATHIC 2897 * using IWM_TE_ABSENCE and using IWM_TE_NOTIF_* 2898 */ 2899 struct iwm_time_event_cmd { 2900 /* COMMON_INDEX_HDR_API_S_VER_1 */ 2901 uint32_t id_and_color; 2902 uint32_t action; 2903 uint32_t id; 2904 /* IWM_MAC_TIME_EVENT_DATA_API_S_VER_2 */ 2905 uint32_t apply_time; 2906 uint32_t max_delay; 2907 uint32_t depends_on; 2908 uint32_t interval; 2909 uint32_t duration; 2910 uint8_t repeat; 2911 uint8_t max_frags; 2912 uint16_t policy; 2913 } __packed; /* IWM_MAC_TIME_EVENT_CMD_API_S_VER_2 */ 2914 2915 /** 2916 * struct iwm_time_event_resp - response structure to iwm_time_event_cmd 2917 * @status: bit 0 indicates success, all others specify errors 2918 * @id: the Time Event type 2919 * @unique_id: the unique ID assigned (in ADD) or given (others) to the TE 2920 * @id_and_color: ID and color of the relevant MAC 2921 */ 2922 struct iwm_time_event_resp { 2923 uint32_t status; 2924 uint32_t id; 2925 uint32_t unique_id; 2926 uint32_t id_and_color; 2927 } __packed; /* IWM_MAC_TIME_EVENT_RSP_API_S_VER_1 */ 2928 2929 /** 2930 * struct iwm_time_event_notif - notifications of time event start/stop 2931 * ( IWM_TIME_EVENT_NOTIFICATION = 0x2a ) 2932 * @timestamp: action timestamp in GP2 2933 * @session_id: session's unique id 2934 * @unique_id: unique id of the Time Event itself 2935 * @id_and_color: ID and color of the relevant MAC 2936 * @action: one of IWM_TE_NOTIF_START or IWM_TE_NOTIF_END 2937 * @status: true if scheduled, false otherwise (not executed) 2938 */ 2939 struct iwm_time_event_notif { 2940 uint32_t timestamp; 2941 uint32_t session_id; 2942 uint32_t unique_id; 2943 uint32_t id_and_color; 2944 uint32_t action; 2945 uint32_t status; 2946 } __packed; /* IWM_MAC_TIME_EVENT_NTFY_API_S_VER_1 */ 2947 2948 2949 /* Bindings and Time Quota */ 2950 2951 /** 2952 * struct iwm_binding_cmd_v1 - configuring bindings 2953 * ( IWM_BINDING_CONTEXT_CMD = 0x2b ) 2954 * @id_and_color: ID and color of the relevant Binding 2955 * @action: action to perform, one of IWM_FW_CTXT_ACTION_* 2956 * @macs: array of MAC id and colors which belong to the binding 2957 * @phy: PHY id and color which belongs to the binding 2958 * @lmac_id: the lmac id the binding belongs to 2959 */ 2960 struct iwm_binding_cmd_v1 { 2961 /* COMMON_INDEX_HDR_API_S_VER_1 */ 2962 uint32_t id_and_color; 2963 uint32_t action; 2964 /* IWM_BINDING_DATA_API_S_VER_1 */ 2965 uint32_t macs[IWM_MAX_MACS_IN_BINDING]; 2966 uint32_t phy; 2967 } __packed; /* IWM_BINDING_CMD_API_S_VER_1 */ 2968 2969 /** 2970 * struct iwm_binding_cmd - configuring bindings 2971 * ( IWM_BINDING_CONTEXT_CMD = 0x2b ) 2972 * @id_and_color: ID and color of the relevant Binding 2973 * @action: action to perform, one of IWM_FW_CTXT_ACTION_* 2974 * @macs: array of MAC id and colors which belong to the binding 2975 * @phy: PHY id and color which belongs to the binding 2976 * @lmac_id: the lmac id the binding belongs to 2977 */ 2978 struct iwm_binding_cmd { 2979 /* COMMON_INDEX_HDR_API_S_VER_1 */ 2980 uint32_t id_and_color; 2981 uint32_t action; 2982 /* IWM_BINDING_DATA_API_S_VER_1 */ 2983 uint32_t macs[IWM_MAX_MACS_IN_BINDING]; 2984 uint32_t phy; 2985 uint32_t lmac_id; 2986 } __packed; /* IWM_BINDING_CMD_API_S_VER_2 */ 2987 2988 #define IWM_LMAC_24G_INDEX 0 2989 #define IWM_LMAC_5G_INDEX 1 2990 2991 /* The maximal number of fragments in the FW's schedule session */ 2992 #define IWM_MAX_QUOTA 128 2993 2994 /** 2995 * struct iwm_time_quota_data - configuration of time quota per binding 2996 * @id_and_color: ID and color of the relevant Binding 2997 * @quota: absolute time quota in TU. The scheduler will try to divide the 2998 * remainig quota (after Time Events) according to this quota. 2999 * @max_duration: max uninterrupted context duration in TU 3000 */ 3001 struct iwm_time_quota_data_v1 { 3002 uint32_t id_and_color; 3003 uint32_t quota; 3004 uint32_t max_duration; 3005 } __packed; /* IWM_TIME_QUOTA_DATA_API_S_VER_1 */ 3006 3007 /** 3008 * struct iwm_time_quota_cmd - configuration of time quota between bindings 3009 * ( IWM_TIME_QUOTA_CMD = 0x2c ) 3010 * @quotas: allocations per binding 3011 */ 3012 struct iwm_time_quota_cmd_v1 { 3013 struct iwm_time_quota_data_v1 quotas[IWM_MAX_BINDINGS]; 3014 } __packed; /* IWM_TIME_QUOTA_ALLOCATION_CMD_API_S_VER_1 */ 3015 3016 #define IWM_QUOTA_LOW_LATENCY_NONE 0 3017 #define IWM_QUOTA_LOW_LATENCY_TX (1 << 0) 3018 #define IWM_QUOTA_LOW_LATENCY_RX (1 << 1) 3019 3020 /** 3021 * struct iwm_time_quota_data - configuration of time quota per binding 3022 * @id_and_color: ID and color of the relevant Binding. 3023 * @quota: absolute time quota in TU. The scheduler will try to divide the 3024 * remainig quota (after Time Events) according to this quota. 3025 * @max_duration: max uninterrupted context duration in TU 3026 * @low_latency: low latency status IWM_QUOTA_LOW_LATENCY_* 3027 */ 3028 struct iwm_time_quota_data { 3029 uint32_t id_and_color; 3030 uint32_t quota; 3031 uint32_t max_duration; 3032 uint32_t low_latency; 3033 }; /* TIME_QUOTA_DATA_API_S_VER_2 */ 3034 3035 /** 3036 * struct iwm_time_quota_cmd - configuration of time quota between bindings 3037 * ( TIME_QUOTA_CMD = 0x2c ) 3038 * Note: on non-CDB the fourth one is the auxilary mac and is essentially zero. 3039 * On CDB the fourth one is a regular binding. 3040 * 3041 * @quotas: allocations per binding 3042 */ 3043 struct iwm_time_quota_cmd { 3044 struct iwm_time_quota_data quotas[IWM_MAX_BINDINGS]; 3045 } __packed; /* TIME_QUOTA_ALLOCATION_CMD_API_S_VER_2 */ 3046 3047 3048 /* PHY context */ 3049 3050 /* Supported bands */ 3051 #define IWM_PHY_BAND_5 (0) 3052 #define IWM_PHY_BAND_24 (1) 3053 3054 /* Supported channel width, vary if there is VHT support */ 3055 #define IWM_PHY_VHT_CHANNEL_MODE20 (0x0) 3056 #define IWM_PHY_VHT_CHANNEL_MODE40 (0x1) 3057 #define IWM_PHY_VHT_CHANNEL_MODE80 (0x2) 3058 #define IWM_PHY_VHT_CHANNEL_MODE160 (0x3) 3059 3060 /* 3061 * Control channel position: 3062 * For legacy set bit means upper channel, otherwise lower. 3063 * For VHT - bit-2 marks if the control is lower/upper relative to center-freq 3064 * bits-1:0 mark the distance from the center freq. for 20Mhz, offset is 0. 3065 * center_freq 3066 * | 3067 * 40Mhz |_______|_______| 3068 * 80Mhz |_______|_______|_______|_______| 3069 * 160Mhz |_______|_______|_______|_______|_______|_______|_______|_______| 3070 * code 011 010 001 000 | 100 101 110 111 3071 */ 3072 #define IWM_PHY_VHT_CTRL_POS_1_BELOW (0x0) 3073 #define IWM_PHY_VHT_CTRL_POS_2_BELOW (0x1) 3074 #define IWM_PHY_VHT_CTRL_POS_3_BELOW (0x2) 3075 #define IWM_PHY_VHT_CTRL_POS_4_BELOW (0x3) 3076 #define IWM_PHY_VHT_CTRL_POS_1_ABOVE (0x4) 3077 #define IWM_PHY_VHT_CTRL_POS_2_ABOVE (0x5) 3078 #define IWM_PHY_VHT_CTRL_POS_3_ABOVE (0x6) 3079 #define IWM_PHY_VHT_CTRL_POS_4_ABOVE (0x7) 3080 3081 /* 3082 * @band: IWM_PHY_BAND_* 3083 * @channel: channel number 3084 * @width: PHY_[VHT|LEGACY]_CHANNEL_* 3085 * @ctrl channel: PHY_[VHT|LEGACY]_CTRL_* 3086 */ 3087 struct iwm_fw_channel_info_v1 { 3088 uint8_t band; 3089 uint8_t channel; 3090 uint8_t width; 3091 uint8_t ctrl_pos; 3092 } __packed; /* CHANNEL_CONFIG_API_S_VER_1 */ 3093 3094 /* 3095 * struct iwm_fw_channel_info - channel information 3096 * 3097 * @channel: channel number 3098 * @band: PHY_BAND_* 3099 * @width: PHY_[VHT|LEGACY]_CHANNEL_* 3100 * @ctrl channel: PHY_[VHT|LEGACY]_CTRL_* 3101 * @reserved: for future use and alignment 3102 */ 3103 struct iwm_fw_channel_info { 3104 uint32_t channel; 3105 uint8_t band; 3106 uint8_t width; 3107 uint8_t ctrl_pos; 3108 uint8_t reserved; 3109 } __packed; /* CHANNEL_CONFIG_API_S_VER_2 */ 3110 3111 #define IWM_PHY_RX_CHAIN_DRIVER_FORCE_POS (0) 3112 #define IWM_PHY_RX_CHAIN_DRIVER_FORCE_MSK \ 3113 (0x1 << IWM_PHY_RX_CHAIN_DRIVER_FORCE_POS) 3114 #define IWM_PHY_RX_CHAIN_VALID_POS (1) 3115 #define IWM_PHY_RX_CHAIN_VALID_MSK \ 3116 (0x7 << IWM_PHY_RX_CHAIN_VALID_POS) 3117 #define IWM_PHY_RX_CHAIN_FORCE_SEL_POS (4) 3118 #define IWM_PHY_RX_CHAIN_FORCE_SEL_MSK \ 3119 (0x7 << IWM_PHY_RX_CHAIN_FORCE_SEL_POS) 3120 #define IWM_PHY_RX_CHAIN_FORCE_MIMO_SEL_POS (7) 3121 #define IWM_PHY_RX_CHAIN_FORCE_MIMO_SEL_MSK \ 3122 (0x7 << IWM_PHY_RX_CHAIN_FORCE_MIMO_SEL_POS) 3123 #define IWM_PHY_RX_CHAIN_CNT_POS (10) 3124 #define IWM_PHY_RX_CHAIN_CNT_MSK \ 3125 (0x3 << IWM_PHY_RX_CHAIN_CNT_POS) 3126 #define IWM_PHY_RX_CHAIN_MIMO_CNT_POS (12) 3127 #define IWM_PHY_RX_CHAIN_MIMO_CNT_MSK \ 3128 (0x3 << IWM_PHY_RX_CHAIN_MIMO_CNT_POS) 3129 #define IWM_PHY_RX_CHAIN_MIMO_FORCE_POS (14) 3130 #define IWM_PHY_RX_CHAIN_MIMO_FORCE_MSK \ 3131 (0x1 << IWM_PHY_RX_CHAIN_MIMO_FORCE_POS) 3132 3133 /* TODO: fix the value, make it depend on firmware at runtime? */ 3134 #define IWM_NUM_PHY_CTX 3 3135 3136 /* TODO: complete missing documentation */ 3137 /** 3138 * struct iwm_phy_context_cmd - config of the PHY context 3139 * ( IWM_PHY_CONTEXT_CMD = 0x8 ) 3140 * @id_and_color: ID and color of the relevant Binding 3141 * @action: action to perform, one of IWM_FW_CTXT_ACTION_* 3142 * @apply_time: 0 means immediate apply and context switch. 3143 * other value means apply new params after X usecs 3144 * @tx_param_color: ??? 3145 * @channel_info: 3146 * @txchain_info: ??? 3147 * @rxchain_info: ??? 3148 * @acquisition_data: ??? 3149 * @dsp_cfg_flags: set to 0 3150 */ 3151 /* 3152 * XXX Intel forgot to bump the PHY_CONTEXT command API when they increased 3153 * the size of fw_channel_info from v1 to v2. 3154 * To keep things simple we define two versions of this struct, and both 3155 * are labled as CMD_API_VER_1. (The Linux iwlwifi driver performs dark 3156 * magic with pointers to struct members instead.) 3157 */ 3158 /* This version must be used if IWM_UCODE_TLV_CAPA_ULTRA_HB_CHANNELS is set: */ 3159 struct iwm_phy_context_cmd_uhb { 3160 /* COMMON_INDEX_HDR_API_S_VER_1 */ 3161 uint32_t id_and_color; 3162 uint32_t action; 3163 /* IWM_PHY_CONTEXT_DATA_API_S_VER_1 */ 3164 uint32_t apply_time; 3165 uint32_t tx_param_color; 3166 struct iwm_fw_channel_info ci; 3167 uint32_t txchain_info; 3168 uint32_t rxchain_info; 3169 uint32_t acquisition_data; 3170 uint32_t dsp_cfg_flags; 3171 } __packed; /* IWM_PHY_CONTEXT_CMD_API_VER_1 */ 3172 /* This version must be used otherwise: */ 3173 struct iwm_phy_context_cmd { 3174 /* COMMON_INDEX_HDR_API_S_VER_1 */ 3175 uint32_t id_and_color; 3176 uint32_t action; 3177 /* IWM_PHY_CONTEXT_DATA_API_S_VER_1 */ 3178 uint32_t apply_time; 3179 uint32_t tx_param_color; 3180 struct iwm_fw_channel_info_v1 ci; 3181 uint32_t txchain_info; 3182 uint32_t rxchain_info; 3183 uint32_t acquisition_data; 3184 uint32_t dsp_cfg_flags; 3185 } __packed; /* IWM_PHY_CONTEXT_CMD_API_VER_1 */ 3186 3187 #define IWM_RX_INFO_PHY_CNT 8 3188 #define IWM_RX_INFO_ENERGY_ANT_ABC_IDX 1 3189 #define IWM_RX_INFO_ENERGY_ANT_A_MSK 0x000000ff 3190 #define IWM_RX_INFO_ENERGY_ANT_B_MSK 0x0000ff00 3191 #define IWM_RX_INFO_ENERGY_ANT_C_MSK 0x00ff0000 3192 #define IWM_RX_INFO_ENERGY_ANT_A_POS 0 3193 #define IWM_RX_INFO_ENERGY_ANT_B_POS 8 3194 #define IWM_RX_INFO_ENERGY_ANT_C_POS 16 3195 3196 #define IWM_RX_INFO_AGC_IDX 1 3197 #define IWM_RX_INFO_RSSI_AB_IDX 2 3198 #define IWM_OFDM_AGC_A_MSK 0x0000007f 3199 #define IWM_OFDM_AGC_A_POS 0 3200 #define IWM_OFDM_AGC_B_MSK 0x00003f80 3201 #define IWM_OFDM_AGC_B_POS 7 3202 #define IWM_OFDM_AGC_CODE_MSK 0x3fe00000 3203 #define IWM_OFDM_AGC_CODE_POS 20 3204 #define IWM_OFDM_RSSI_INBAND_A_MSK 0x00ff 3205 #define IWM_OFDM_RSSI_A_POS 0 3206 #define IWM_OFDM_RSSI_ALLBAND_A_MSK 0xff00 3207 #define IWM_OFDM_RSSI_ALLBAND_A_POS 8 3208 #define IWM_OFDM_RSSI_INBAND_B_MSK 0xff0000 3209 #define IWM_OFDM_RSSI_B_POS 16 3210 #define IWM_OFDM_RSSI_ALLBAND_B_MSK 0xff000000 3211 #define IWM_OFDM_RSSI_ALLBAND_B_POS 24 3212 3213 /** 3214 * struct iwm_rx_phy_info - phy info 3215 * (IWM_REPLY_RX_PHY_CMD = 0xc0) 3216 * @non_cfg_phy_cnt: non configurable DSP phy data byte count 3217 * @cfg_phy_cnt: configurable DSP phy data byte count 3218 * @stat_id: configurable DSP phy data set ID 3219 * @reserved1: 3220 * @system_timestamp: GP2 at on air rise 3221 * @timestamp: TSF at on air rise 3222 * @beacon_time_stamp: beacon at on-air rise 3223 * @phy_flags: general phy flags: band, modulation, ... 3224 * @channel: channel number 3225 * @non_cfg_phy_buf: for various implementations of non_cfg_phy 3226 * @rate_n_flags: IWM_RATE_MCS_* 3227 * @byte_count: frame's byte-count 3228 * @frame_time: frame's time on the air, based on byte count and frame rate 3229 * calculation 3230 * @mac_active_msk: what MACs were active when the frame was received 3231 * 3232 * Before each Rx, the device sends this data. It contains PHY information 3233 * about the reception of the packet. 3234 */ 3235 struct iwm_rx_phy_info { 3236 uint8_t non_cfg_phy_cnt; 3237 uint8_t cfg_phy_cnt; 3238 uint8_t stat_id; 3239 uint8_t reserved1; 3240 uint32_t system_timestamp; 3241 uint64_t timestamp; 3242 uint32_t beacon_time_stamp; 3243 uint16_t phy_flags; 3244 #define IWM_PHY_INFO_FLAG_SHPREAMBLE (1 << 2) 3245 uint16_t channel; 3246 uint32_t non_cfg_phy[IWM_RX_INFO_PHY_CNT]; 3247 #if 0 3248 /* OpenBSD update; will need to convert code to use this field */ 3249 uint32_t rate_n_flags; 3250 #else 3251 uint8_t rate; 3252 uint8_t rflags; 3253 uint16_t xrflags; 3254 #endif 3255 uint32_t byte_count; 3256 uint16_t mac_active_msk; 3257 uint16_t frame_time; 3258 } __packed; 3259 3260 struct iwm_rx_mpdu_res_start { 3261 uint16_t byte_count; 3262 uint16_t reserved; 3263 } __packed; 3264 3265 /** 3266 * Values to parse %iwm_rx_phy_info phy_flags 3267 * @IWM_RX_RES_PHY_FLAGS_BAND_24: true if the packet was received on 2.4 band 3268 * @IWM_RX_RES_PHY_FLAGS_MOD_CCK: 3269 * @IWM_RX_RES_PHY_FLAGS_SHORT_PREAMBLE: true if packet's preamble was short 3270 * @IWM_RX_RES_PHY_FLAGS_NARROW_BAND: 3271 * @IWM_RX_RES_PHY_FLAGS_ANTENNA: antenna on which the packet was received 3272 * @IWM_RX_RES_PHY_FLAGS_AGG: set if the packet was part of an A-MPDU 3273 * @IWM_RX_RES_PHY_FLAGS_OFDM_HT: The frame was an HT frame 3274 * @IWM_RX_RES_PHY_FLAGS_OFDM_GF: The frame used GF preamble 3275 * @IWM_RX_RES_PHY_FLAGS_OFDM_VHT: The frame was a VHT frame 3276 */ 3277 #define IWM_RX_RES_PHY_FLAGS_BAND_24 (1 << 0) 3278 #define IWM_RX_RES_PHY_FLAGS_MOD_CCK (1 << 1) 3279 #define IWM_RX_RES_PHY_FLAGS_SHORT_PREAMBLE (1 << 2) 3280 #define IWM_RX_RES_PHY_FLAGS_NARROW_BAND (1 << 3) 3281 #define IWM_RX_RES_PHY_FLAGS_ANTENNA (0x7 << 4) 3282 #define IWM_RX_RES_PHY_FLAGS_ANTENNA_POS 4 3283 #define IWM_RX_RES_PHY_FLAGS_AGG (1 << 7) 3284 #define IWM_RX_RES_PHY_FLAGS_OFDM_HT (1 << 8) 3285 #define IWM_RX_RES_PHY_FLAGS_OFDM_GF (1 << 9) 3286 #define IWM_RX_RES_PHY_FLAGS_OFDM_VHT (1 << 10) 3287 3288 /** 3289 * Values written by fw for each Rx packet 3290 * @IWM_RX_MPDU_RES_STATUS_CRC_OK: CRC is fine 3291 * @IWM_RX_MPDU_RES_STATUS_OVERRUN_OK: there was no RXE overflow 3292 * @IWM_RX_MPDU_RES_STATUS_SRC_STA_FOUND: 3293 * @IWM_RX_MPDU_RES_STATUS_KEY_VALID: 3294 * @IWM_RX_MPDU_RES_STATUS_KEY_PARAM_OK: 3295 * @IWM_RX_MPDU_RES_STATUS_ICV_OK: ICV is fine, if not, the packet is destroyed 3296 * @IWM_RX_MPDU_RES_STATUS_MIC_OK: used for CCM alg only. TKIP MIC is checked 3297 * in the driver. 3298 * @IWM_RX_MPDU_RES_STATUS_TTAK_OK: TTAK is fine 3299 * @IWM_RX_MPDU_RES_STATUS_MNG_FRAME_REPLAY_ERR: valid for alg = CCM_CMAC or 3300 * alg = CCM only. Checks replay attack for 11w frames. Relevant only if 3301 * %IWM_RX_MPDU_RES_STATUS_ROBUST_MNG_FRAME is set. 3302 * @IWM_RX_MPDU_RES_STATUS_SEC_NO_ENC: this frame is not encrypted 3303 * @IWM_RX_MPDU_RES_STATUS_SEC_WEP_ENC: this frame is encrypted using WEP 3304 * @IWM_RX_MPDU_RES_STATUS_SEC_CCM_ENC: this frame is encrypted using CCM 3305 * @IWM_RX_MPDU_RES_STATUS_SEC_TKIP_ENC: this frame is encrypted using TKIP 3306 * @IWM_RX_MPDU_RES_STATUS_SEC_CCM_CMAC_ENC: this frame is encrypted using CCM_CMAC 3307 * @IWM_RX_MPDU_RES_STATUS_SEC_ENC_ERR: this frame couldn't be decrypted 3308 * @IWM_RX_MPDU_RES_STATUS_SEC_ENC_MSK: bitmask of the encryption algorithm 3309 * @IWM_RX_MPDU_RES_STATUS_DEC_DONE: this frame has been successfully decrypted 3310 * @IWM_RX_MPDU_RES_STATUS_PROTECT_FRAME_BIT_CMP: 3311 * @IWM_RX_MPDU_RES_STATUS_EXT_IV_BIT_CMP: 3312 * @IWM_RX_MPDU_RES_STATUS_KEY_ID_CMP_BIT: 3313 * @IWM_RX_MPDU_RES_STATUS_ROBUST_MNG_FRAME: this frame is an 11w management frame 3314 * @IWM_RX_MPDU_RES_STATUS_HASH_INDEX_MSK: 3315 * @IWM_RX_MPDU_RES_STATUS_STA_ID_MSK: 3316 * @IWM_RX_MPDU_RES_STATUS_RRF_KILL: 3317 * @IWM_RX_MPDU_RES_STATUS_FILTERING_MSK: 3318 * @IWM_RX_MPDU_RES_STATUS2_FILTERING_MSK: 3319 */ 3320 #define IWM_RX_MPDU_RES_STATUS_CRC_OK (1 << 0) 3321 #define IWM_RX_MPDU_RES_STATUS_OVERRUN_OK (1 << 1) 3322 #define IWM_RX_MPDU_RES_STATUS_SRC_STA_FOUND (1 << 2) 3323 #define IWM_RX_MPDU_RES_STATUS_KEY_VALID (1 << 3) 3324 #define IWM_RX_MPDU_RES_STATUS_KEY_PARAM_OK (1 << 4) 3325 #define IWM_RX_MPDU_RES_STATUS_ICV_OK (1 << 5) 3326 #define IWM_RX_MPDU_RES_STATUS_MIC_OK (1 << 6) 3327 #define IWM_RX_MPDU_RES_STATUS_TTAK_OK (1 << 7) 3328 #define IWM_RX_MPDU_RES_STATUS_MNG_FRAME_REPLAY_ERR (1 << 7) 3329 #define IWM_RX_MPDU_RES_STATUS_SEC_NO_ENC (0 << 8) 3330 #define IWM_RX_MPDU_RES_STATUS_SEC_WEP_ENC (1 << 8) 3331 #define IWM_RX_MPDU_RES_STATUS_SEC_CCM_ENC (2 << 8) 3332 #define IWM_RX_MPDU_RES_STATUS_SEC_TKIP_ENC (3 << 8) 3333 #define IWM_RX_MPDU_RES_STATUS_SEC_EXT_ENC (4 << 8) 3334 #define IWM_RX_MPDU_RES_STATUS_SEC_CCM_CMAC_ENC (6 << 8) 3335 #define IWM_RX_MPDU_RES_STATUS_SEC_ENC_ERR (7 << 8) 3336 #define IWM_RX_MPDU_RES_STATUS_SEC_ENC_MSK (7 << 8) 3337 #define IWM_RX_MPDU_RES_STATUS_DEC_DONE (1 << 11) 3338 #define IWM_RX_MPDU_RES_STATUS_PROTECT_FRAME_BIT_CMP (1 << 12) 3339 #define IWM_RX_MPDU_RES_STATUS_EXT_IV_BIT_CMP (1 << 13) 3340 #define IWM_RX_MPDU_RES_STATUS_KEY_ID_CMP_BIT (1 << 14) 3341 #define IWM_RX_MPDU_RES_STATUS_ROBUST_MNG_FRAME (1 << 15) 3342 #define IWM_RX_MPDU_RES_STATUS_HASH_INDEX_MSK (0x3F0000) 3343 #define IWM_RX_MPDU_RES_STATUS_STA_ID_MSK (0x1f000000) 3344 #define IWM_RX_MPDU_RES_STATUS_RRF_KILL (1 << 29) 3345 #define IWM_RX_MPDU_RES_STATUS_FILTERING_MSK (0xc00000) 3346 #define IWM_RX_MPDU_RES_STATUS2_FILTERING_MSK (0xc0000000) 3347 3348 #define IWM_RX_MPDU_MFLG1_ADDRTYPE_MASK 0x03 3349 #define IWM_RX_MPDU_MFLG1_MIC_CRC_LEN_MASK 0xf0 3350 #define IWM_RX_MPDU_MFLG1_MIC_CRC_LEN_SHIFT 3 3351 3352 #define IWM_RX_MPDU_MFLG2_HDR_LEN_MASK 0x1f 3353 #define IWM_RX_MPDU_MFLG2_PAD 0x20 3354 #define IWM_RX_MPDU_MFLG2_AMSDU 0x40 3355 3356 #define IWM_RX_MPDU_AMSDU_SUBFRAME_IDX_MASK 0x7f 3357 #define IWM_RX_MPDU_AMSDU_LAST_SUBFRAME 0x80 3358 3359 #define IWM_RX_MPDU_PHY_AMPDU (1 << 5) 3360 #define IWM_RX_MPDU_PHY_AMPDU_TOGGLE (1 << 6) 3361 #define IWM_RX_MPDU_PHY_SHORT_PREAMBLE (1 << 7) 3362 #define IWM_RX_MPDU_PHY_NCCK_ADDTL_NTFY (1 << 7) 3363 #define IWM_RX_MPDU_PHY_TSF_OVERLOAD (1 << 8) 3364 3365 struct iwm_rx_mpdu_desc_v1 { 3366 union { 3367 uint32_t rss_hash; 3368 uint32_t phy_data2; 3369 }; 3370 union { 3371 uint32_t filter_match; 3372 uint32_t phy_data3; 3373 }; 3374 uint32_t rate_n_flags; 3375 uint8_t energy_a; 3376 uint8_t energy_b; 3377 uint8_t channel; 3378 uint8_t mac_context; 3379 uint32_t gp2_on_air_rise; 3380 union { 3381 uint64_t tsf_on_air_rise; 3382 struct { 3383 uint32_t phy_data0; 3384 uint32_t phy_data1; 3385 }; 3386 }; 3387 } __packed; 3388 3389 #define IWM_RX_REORDER_DATA_INVALID_BAID 0x7f 3390 3391 #define IWM_RX_MPDU_REORDER_NSSN_MASK 0x00000fff 3392 #define IWM_RX_MPDU_REORDER_SN_MASK 0x00fff000 3393 #define IWM_RX_MPDU_REORDER_SN_SHIFT 12 3394 #define IWM_RX_MPDU_REORDER_BAID_MASK 0x7f000000 3395 #define IWM_RX_MPDU_REORDER_BAID_SHIFT 24 3396 #define IWM_RX_MPDU_REORDER_BA_OLD_SN 0x80000000 3397 3398 struct iwm_rx_mpdu_desc { 3399 uint16_t mpdu_len; 3400 uint8_t mac_flags1; 3401 uint8_t mac_flags2; 3402 uint8_t amsdu_info; 3403 uint16_t phy_info; 3404 uint8_t mac_phy_idx; 3405 uint16_t raw_csum; 3406 union { 3407 uint16_t l3l4_flags; 3408 uint16_t phy_data4; 3409 }; 3410 uint16_t status; 3411 uint8_t hash_filter; 3412 uint8_t sta_id_flags; 3413 uint32_t reorder_data; 3414 struct iwm_rx_mpdu_desc_v1 v1; 3415 } __packed; 3416 3417 /** 3418 * struct iwm_radio_version_notif - information on the radio version 3419 * ( IWM_RADIO_VERSION_NOTIFICATION = 0x68 ) 3420 * @radio_flavor: 3421 * @radio_step: 3422 * @radio_dash: 3423 */ 3424 struct iwm_radio_version_notif { 3425 uint32_t radio_flavor; 3426 uint32_t radio_step; 3427 uint32_t radio_dash; 3428 } __packed; /* IWM_RADIO_VERSION_NOTOFICATION_S_VER_1 */ 3429 3430 #define IWM_CARD_ENABLED 0x00 3431 #define IWM_HW_CARD_DISABLED 0x01 3432 #define IWM_SW_CARD_DISABLED 0x02 3433 #define IWM_CT_KILL_CARD_DISABLED 0x04 3434 #define IWM_HALT_CARD_DISABLED 0x08 3435 #define IWM_CARD_DISABLED_MSK 0x0f 3436 #define IWM_CARD_IS_RX_ON 0x10 3437 3438 /** 3439 * struct iwm_radio_version_notif - information on the radio version 3440 * (IWM_CARD_STATE_NOTIFICATION = 0xa1 ) 3441 * @flags: %iwm_card_state_flags 3442 */ 3443 struct iwm_card_state_notif { 3444 uint32_t flags; 3445 } __packed; /* CARD_STATE_NTFY_API_S_VER_1 */ 3446 3447 /** 3448 * struct iwm_missed_beacons_notif - information on missed beacons 3449 * ( IWM_MISSED_BEACONS_NOTIFICATION = 0xa2 ) 3450 * @mac_id: interface ID 3451 * @consec_missed_beacons_since_last_rx: number of consecutive missed 3452 * beacons since last RX. 3453 * @consec_missed_beacons: number of consecutive missed beacons 3454 * @num_expected_beacons: 3455 * @num_recvd_beacons: 3456 */ 3457 struct iwm_missed_beacons_notif { 3458 uint32_t mac_id; 3459 uint32_t consec_missed_beacons_since_last_rx; 3460 uint32_t consec_missed_beacons; 3461 uint32_t num_expected_beacons; 3462 uint32_t num_recvd_beacons; 3463 } __packed; /* IWM_MISSED_BEACON_NTFY_API_S_VER_3 */ 3464 3465 /** 3466 * struct iwm_mfuart_load_notif - mfuart image version & status 3467 * ( IWM_MFUART_LOAD_NOTIFICATION = 0xb1 ) 3468 * @installed_ver: installed image version 3469 * @external_ver: external image version 3470 * @status: MFUART loading status 3471 * @duration: MFUART loading time 3472 */ 3473 struct iwm_mfuart_load_notif { 3474 uint32_t installed_ver; 3475 uint32_t external_ver; 3476 uint32_t status; 3477 uint32_t duration; 3478 } __packed; /*MFU_LOADER_NTFY_API_S_VER_1*/ 3479 3480 /** 3481 * struct iwm_set_calib_default_cmd - set default value for calibration. 3482 * ( IWM_SET_CALIB_DEFAULT_CMD = 0x8e ) 3483 * @calib_index: the calibration to set value for 3484 * @length: of data 3485 * @data: the value to set for the calibration result 3486 */ 3487 struct iwm_set_calib_default_cmd { 3488 uint16_t calib_index; 3489 uint16_t length; 3490 uint8_t data[0]; 3491 } __packed; /* IWM_PHY_CALIB_OVERRIDE_VALUES_S */ 3492 3493 #define IWM_MAX_PORT_ID_NUM 2 3494 #define IWM_MAX_MCAST_FILTERING_ADDRESSES 256 3495 3496 /** 3497 * struct iwm_mcast_filter_cmd - configure multicast filter. 3498 * @filter_own: Set 1 to filter out multicast packets sent by station itself 3499 * @port_id: Multicast MAC addresses array specifier. This is a strange way 3500 * to identify network interface adopted in host-device IF. 3501 * It is used by FW as index in array of addresses. This array has 3502 * IWM_MAX_PORT_ID_NUM members. 3503 * @count: Number of MAC addresses in the array 3504 * @pass_all: Set 1 to pass all multicast packets. 3505 * @bssid: current association BSSID. 3506 * @addr_list: Place holder for array of MAC addresses. 3507 * IMPORTANT: add padding if necessary to ensure DWORD alignment. 3508 */ 3509 struct iwm_mcast_filter_cmd { 3510 uint8_t filter_own; 3511 uint8_t port_id; 3512 uint8_t count; 3513 uint8_t pass_all; 3514 uint8_t bssid[6]; 3515 uint8_t reserved[2]; 3516 uint8_t addr_list[0]; 3517 } __packed; /* IWM_MCAST_FILTERING_CMD_API_S_VER_1 */ 3518 3519 struct iwm_statistics_dbg { 3520 uint32_t burst_check; 3521 uint32_t burst_count; 3522 uint32_t wait_for_silence_timeout_cnt; 3523 uint32_t reserved[3]; 3524 } __packed; /* IWM_STATISTICS_DEBUG_API_S_VER_2 */ 3525 3526 struct iwm_statistics_div { 3527 uint32_t tx_on_a; 3528 uint32_t tx_on_b; 3529 uint32_t exec_time; 3530 uint32_t probe_time; 3531 uint32_t rssi_ant; 3532 uint32_t reserved2; 3533 } __packed; /* IWM_STATISTICS_SLOW_DIV_API_S_VER_2 */ 3534 3535 struct iwm_statistics_general_common { 3536 uint32_t temperature; /* radio temperature */ 3537 uint32_t temperature_m; /* radio voltage */ 3538 struct iwm_statistics_dbg dbg; 3539 uint32_t sleep_time; 3540 uint32_t slots_out; 3541 uint32_t slots_idle; 3542 uint32_t ttl_timestamp; 3543 struct iwm_statistics_div div; 3544 uint32_t rx_enable_counter; 3545 /* 3546 * num_of_sos_states: 3547 * count the number of times we have to re-tune 3548 * in order to get out of bad PHY status 3549 */ 3550 uint32_t num_of_sos_states; 3551 } __packed; /* IWM_STATISTICS_GENERAL_API_S_VER_5 */ 3552 3553 struct iwm_statistics_rx_non_phy { 3554 uint32_t bogus_cts; /* CTS received when not expecting CTS */ 3555 uint32_t bogus_ack; /* ACK received when not expecting ACK */ 3556 uint32_t non_bssid_frames; /* number of frames with BSSID that 3557 * doesn't belong to the STA BSSID */ 3558 uint32_t filtered_frames; /* count frames that were dumped in the 3559 * filtering process */ 3560 uint32_t non_channel_beacons; /* beacons with our bss id but not on 3561 * our serving channel */ 3562 uint32_t channel_beacons; /* beacons with our bss id and in our 3563 * serving channel */ 3564 uint32_t num_missed_bcon; /* number of missed beacons */ 3565 uint32_t adc_rx_saturation_time; /* count in 0.8us units the time the 3566 * ADC was in saturation */ 3567 uint32_t ina_detection_search_time;/* total time (in 0.8us) searched 3568 * for INA */ 3569 uint32_t beacon_silence_rssi[3];/* RSSI silence after beacon frame */ 3570 uint32_t interference_data_flag; /* flag for interference data 3571 * availability. 1 when data is 3572 * available. */ 3573 uint32_t channel_load; /* counts RX Enable time in uSec */ 3574 uint32_t dsp_false_alarms; /* DSP false alarm (both OFDM 3575 * and CCK) counter */ 3576 uint32_t beacon_rssi_a; 3577 uint32_t beacon_rssi_b; 3578 uint32_t beacon_rssi_c; 3579 uint32_t beacon_energy_a; 3580 uint32_t beacon_energy_b; 3581 uint32_t beacon_energy_c; 3582 uint32_t num_bt_kills; 3583 uint32_t mac_id; 3584 uint32_t directed_data_mpdu; 3585 } __packed; /* IWM_STATISTICS_RX_NON_PHY_API_S_VER_3 */ 3586 3587 struct iwm_statistics_rx_phy { 3588 uint32_t ina_cnt; 3589 uint32_t fina_cnt; 3590 uint32_t plcp_err; 3591 uint32_t crc32_err; 3592 uint32_t overrun_err; 3593 uint32_t early_overrun_err; 3594 uint32_t crc32_good; 3595 uint32_t false_alarm_cnt; 3596 uint32_t fina_sync_err_cnt; 3597 uint32_t sfd_timeout; 3598 uint32_t fina_timeout; 3599 uint32_t unresponded_rts; 3600 uint32_t rxe_frame_limit_overrun; 3601 uint32_t sent_ack_cnt; 3602 uint32_t sent_cts_cnt; 3603 uint32_t sent_ba_rsp_cnt; 3604 uint32_t dsp_self_kill; 3605 uint32_t mh_format_err; 3606 uint32_t re_acq_main_rssi_sum; 3607 uint32_t reserved; 3608 } __packed; /* IWM_STATISTICS_RX_PHY_API_S_VER_2 */ 3609 3610 struct iwm_statistics_rx_ht_phy { 3611 uint32_t plcp_err; 3612 uint32_t overrun_err; 3613 uint32_t early_overrun_err; 3614 uint32_t crc32_good; 3615 uint32_t crc32_err; 3616 uint32_t mh_format_err; 3617 uint32_t agg_crc32_good; 3618 uint32_t agg_mpdu_cnt; 3619 uint32_t agg_cnt; 3620 uint32_t unsupport_mcs; 3621 } __packed; /* IWM_STATISTICS_HT_RX_PHY_API_S_VER_1 */ 3622 3623 #define IWM_MAX_CHAINS 3 3624 3625 struct iwm_statistics_tx_non_phy_agg { 3626 uint32_t ba_timeout; 3627 uint32_t ba_reschedule_frames; 3628 uint32_t scd_query_agg_frame_cnt; 3629 uint32_t scd_query_no_agg; 3630 uint32_t scd_query_agg; 3631 uint32_t scd_query_mismatch; 3632 uint32_t frame_not_ready; 3633 uint32_t underrun; 3634 uint32_t bt_prio_kill; 3635 uint32_t rx_ba_rsp_cnt; 3636 int8_t txpower[IWM_MAX_CHAINS]; 3637 int8_t reserved; 3638 uint32_t reserved2; 3639 } __packed; /* IWM_STATISTICS_TX_NON_PHY_AGG_API_S_VER_1 */ 3640 3641 struct iwm_statistics_tx_channel_width { 3642 uint32_t ext_cca_narrow_ch20[1]; 3643 uint32_t ext_cca_narrow_ch40[2]; 3644 uint32_t ext_cca_narrow_ch80[3]; 3645 uint32_t ext_cca_narrow_ch160[4]; 3646 uint32_t last_tx_ch_width_indx; 3647 uint32_t rx_detected_per_ch_width[4]; 3648 uint32_t success_per_ch_width[4]; 3649 uint32_t fail_per_ch_width[4]; 3650 }; /* IWM_STATISTICS_TX_CHANNEL_WIDTH_API_S_VER_1 */ 3651 3652 struct iwm_statistics_tx { 3653 uint32_t preamble_cnt; 3654 uint32_t rx_detected_cnt; 3655 uint32_t bt_prio_defer_cnt; 3656 uint32_t bt_prio_kill_cnt; 3657 uint32_t few_bytes_cnt; 3658 uint32_t cts_timeout; 3659 uint32_t ack_timeout; 3660 uint32_t expected_ack_cnt; 3661 uint32_t actual_ack_cnt; 3662 uint32_t dump_msdu_cnt; 3663 uint32_t burst_abort_next_frame_mismatch_cnt; 3664 uint32_t burst_abort_missing_next_frame_cnt; 3665 uint32_t cts_timeout_collision; 3666 uint32_t ack_or_ba_timeout_collision; 3667 struct iwm_statistics_tx_non_phy_agg agg; 3668 struct iwm_statistics_tx_channel_width channel_width; 3669 } __packed; /* IWM_STATISTICS_TX_API_S_VER_4 */ 3670 3671 3672 struct iwm_statistics_bt_activity { 3673 uint32_t hi_priority_tx_req_cnt; 3674 uint32_t hi_priority_tx_denied_cnt; 3675 uint32_t lo_priority_tx_req_cnt; 3676 uint32_t lo_priority_tx_denied_cnt; 3677 uint32_t hi_priority_rx_req_cnt; 3678 uint32_t hi_priority_rx_denied_cnt; 3679 uint32_t lo_priority_rx_req_cnt; 3680 uint32_t lo_priority_rx_denied_cnt; 3681 } __packed; /* IWM_STATISTICS_BT_ACTIVITY_API_S_VER_1 */ 3682 3683 struct iwm_statistics_general { 3684 struct iwm_statistics_general_common common; 3685 uint32_t beacon_filtered; 3686 uint32_t missed_beacons; 3687 int8_t beacon_filter_average_energy; 3688 int8_t beacon_filter_reason; 3689 int8_t beacon_filter_current_energy; 3690 int8_t beacon_filter_reserved; 3691 uint32_t beacon_filter_delta_time; 3692 struct iwm_statistics_bt_activity bt_activity; 3693 } __packed; /* IWM_STATISTICS_GENERAL_API_S_VER_5 */ 3694 3695 struct iwm_statistics_rx { 3696 struct iwm_statistics_rx_phy ofdm; 3697 struct iwm_statistics_rx_phy cck; 3698 struct iwm_statistics_rx_non_phy general; 3699 struct iwm_statistics_rx_ht_phy ofdm_ht; 3700 } __packed; /* IWM_STATISTICS_RX_API_S_VER_3 */ 3701 3702 /* 3703 * IWM_STATISTICS_NOTIFICATION = 0x9d (notification only, not a command) 3704 * 3705 * By default, uCode issues this notification after receiving a beacon 3706 * while associated. To disable this behavior, set DISABLE_NOTIF flag in the 3707 * IWM_REPLY_STATISTICS_CMD 0x9c, above. 3708 * 3709 * Statistics counters continue to increment beacon after beacon, but are 3710 * cleared when changing channels or when driver issues IWM_REPLY_STATISTICS_CMD 3711 * 0x9c with CLEAR_STATS bit set (see above). 3712 * 3713 * uCode also issues this notification during scans. uCode clears statistics 3714 * appropriately so that each notification contains statistics for only the 3715 * one channel that has just been scanned. 3716 */ 3717 3718 struct iwm_notif_statistics { /* IWM_STATISTICS_NTFY_API_S_VER_8 */ 3719 uint32_t flag; 3720 struct iwm_statistics_rx rx; 3721 struct iwm_statistics_tx tx; 3722 struct iwm_statistics_general general; 3723 } __packed; 3724 3725 /*********************************** 3726 * Smart Fifo API 3727 ***********************************/ 3728 /* Smart Fifo state */ 3729 3730 enum iwm_sf_state { 3731 IWM_SF_LONG_DELAY_ON = 0, /* should never be called by driver */ 3732 IWM_SF_FULL_ON, 3733 IWM_SF_UNINIT, 3734 IWM_SF_INIT_OFF, 3735 IWM_SF_HW_NUM_STATES 3736 }; 3737 3738 /* Smart Fifo possible scenario */ 3739 enum iwm_sf_scenario { 3740 IWM_SF_SCENARIO_SINGLE_UNICAST, 3741 IWM_SF_SCENARIO_AGG_UNICAST, 3742 IWM_SF_SCENARIO_MULTICAST, 3743 IWM_SF_SCENARIO_BA_RESP, 3744 IWM_SF_SCENARIO_TX_RESP, 3745 IWM_SF_NUM_SCENARIO 3746 }; 3747 3748 #define IWM_SF_TRANSIENT_STATES_NUMBER 2 /* IWM_SF_LONG_DELAY_ON and IWM_SF_FULL_ON */ 3749 #define IWM_SF_NUM_TIMEOUT_TYPES 2 /* Aging timer and Idle timer */ 3750 3751 /* smart FIFO default values */ 3752 #define IWM_SF_W_MARK_SISO 4096 3753 #define IWM_SF_W_MARK_MIMO2 8192 3754 #define IWM_SF_W_MARK_MIMO3 6144 3755 #define IWM_SF_W_MARK_LEGACY 4096 3756 #define IWM_SF_W_MARK_SCAN 4096 3757 3758 /* SF Scenarios timers for default configuration (aligned to 32 uSec) */ 3759 #define IWM_SF_SINGLE_UNICAST_IDLE_TIMER_DEF 160 /* 150 uSec */ 3760 #define IWM_SF_SINGLE_UNICAST_AGING_TIMER_DEF 400 /* 0.4 mSec */ 3761 #define IWM_SF_AGG_UNICAST_IDLE_TIMER_DEF 160 /* 150 uSec */ 3762 #define IWM_SF_AGG_UNICAST_AGING_TIMER_DEF 400 /* 0.4 mSec */ 3763 #define IWM_SF_MCAST_IDLE_TIMER_DEF 160 /* 150 mSec */ 3764 #define IWM_SF_MCAST_AGING_TIMER_DEF 400 /* 0.4 mSec */ 3765 #define IWM_SF_BA_IDLE_TIMER_DEF 160 /* 150 uSec */ 3766 #define IWM_SF_BA_AGING_TIMER_DEF 400 /* 0.4 mSec */ 3767 #define IWM_SF_TX_RE_IDLE_TIMER_DEF 160 /* 150 uSec */ 3768 #define IWM_SF_TX_RE_AGING_TIMER_DEF 400 /* 0.4 mSec */ 3769 3770 /* SF Scenarios timers for FULL_ON state (aligned to 32 uSec) */ 3771 #define IWM_SF_SINGLE_UNICAST_IDLE_TIMER 320 /* 300 uSec */ 3772 #define IWM_SF_SINGLE_UNICAST_AGING_TIMER 2016 /* 2 mSec */ 3773 #define IWM_SF_AGG_UNICAST_IDLE_TIMER 320 /* 300 uSec */ 3774 #define IWM_SF_AGG_UNICAST_AGING_TIMER 2016 /* 2 mSec */ 3775 #define IWM_SF_MCAST_IDLE_TIMER 2016 /* 2 mSec */ 3776 #define IWM_SF_MCAST_AGING_TIMER 10016 /* 10 mSec */ 3777 #define IWM_SF_BA_IDLE_TIMER 320 /* 300 uSec */ 3778 #define IWM_SF_BA_AGING_TIMER 2016 /* 2 mSec */ 3779 #define IWM_SF_TX_RE_IDLE_TIMER 320 /* 300 uSec */ 3780 #define IWM_SF_TX_RE_AGING_TIMER 2016 /* 2 mSec */ 3781 3782 #define IWM_SF_LONG_DELAY_AGING_TIMER 1000000 /* 1 Sec */ 3783 3784 #define IWM_SF_CFG_DUMMY_NOTIF_OFF (1 << 16) 3785 3786 /** 3787 * Smart Fifo configuration command. 3788 * @state: smart fifo state, types listed in enum %iwm_sf_state. 3789 * @watermark: Minimum allowed available free space in RXF for transient state. 3790 * @long_delay_timeouts: aging and idle timer values for each scenario 3791 * in long delay state. 3792 * @full_on_timeouts: timer values for each scenario in full on state. 3793 */ 3794 struct iwm_sf_cfg_cmd { 3795 uint32_t state; 3796 uint32_t watermark[IWM_SF_TRANSIENT_STATES_NUMBER]; 3797 uint32_t long_delay_timeouts[IWM_SF_NUM_SCENARIO][IWM_SF_NUM_TIMEOUT_TYPES]; 3798 uint32_t full_on_timeouts[IWM_SF_NUM_SCENARIO][IWM_SF_NUM_TIMEOUT_TYPES]; 3799 } __packed; /* IWM_SF_CFG_API_S_VER_2 */ 3800 3801 /* 3802 * END mvm/fw-api.h 3803 */ 3804 3805 /* 3806 * BEGIN mvm/fw-api-mac.h 3807 */ 3808 3809 /* 3810 * The first MAC indices (starting from 0) 3811 * are available to the driver, AUX follows 3812 */ 3813 #define IWM_MAC_INDEX_AUX 4 3814 #define IWM_MAC_INDEX_MIN_DRIVER 0 3815 #define IWM_NUM_MAC_INDEX_DRIVER IWM_MAC_INDEX_AUX 3816 3817 #define IWM_AC_BK 0 3818 #define IWM_AC_BE 1 3819 #define IWM_AC_VI 2 3820 #define IWM_AC_VO 3 3821 #define IWM_AC_NUM 4 3822 3823 /** 3824 * MAC context flags 3825 * @IWM_MAC_PROT_FLG_TGG_PROTECT: 11g protection when transmitting OFDM frames, 3826 * this will require CCK RTS/CTS2self. 3827 * RTS/CTS will protect full burst time. 3828 * @IWM_MAC_PROT_FLG_HT_PROT: enable HT protection 3829 * @IWM_MAC_PROT_FLG_FAT_PROT: protect 40 MHz transmissions 3830 * @IWM_MAC_PROT_FLG_SELF_CTS_EN: allow CTS2self 3831 */ 3832 #define IWM_MAC_PROT_FLG_TGG_PROTECT (1 << 3) 3833 #define IWM_MAC_PROT_FLG_HT_PROT (1 << 23) 3834 #define IWM_MAC_PROT_FLG_FAT_PROT (1 << 24) 3835 #define IWM_MAC_PROT_FLG_SELF_CTS_EN (1 << 30) 3836 3837 #define IWM_MAC_FLG_SHORT_SLOT (1 << 4) 3838 #define IWM_MAC_FLG_SHORT_PREAMBLE (1 << 5) 3839 3840 /** 3841 * Supported MAC types 3842 * @IWM_FW_MAC_TYPE_FIRST: lowest supported MAC type 3843 * @IWM_FW_MAC_TYPE_AUX: Auxiliary MAC (internal) 3844 * @IWM_FW_MAC_TYPE_LISTENER: monitor MAC type (?) 3845 * @IWM_FW_MAC_TYPE_PIBSS: Pseudo-IBSS 3846 * @IWM_FW_MAC_TYPE_IBSS: IBSS 3847 * @IWM_FW_MAC_TYPE_BSS_STA: BSS (managed) station 3848 * @IWM_FW_MAC_TYPE_P2P_DEVICE: P2P Device 3849 * @IWM_FW_MAC_TYPE_P2P_STA: P2P client 3850 * @IWM_FW_MAC_TYPE_GO: P2P GO 3851 * @IWM_FW_MAC_TYPE_TEST: ? 3852 * @IWM_FW_MAC_TYPE_MAX: highest support MAC type 3853 */ 3854 #define IWM_FW_MAC_TYPE_FIRST 1 3855 #define IWM_FW_MAC_TYPE_AUX IWM_FW_MAC_TYPE_FIRST 3856 #define IWM_FW_MAC_TYPE_LISTENER 2 3857 #define IWM_FW_MAC_TYPE_PIBSS 3 3858 #define IWM_FW_MAC_TYPE_IBSS 4 3859 #define IWM_FW_MAC_TYPE_BSS_STA 5 3860 #define IWM_FW_MAC_TYPE_P2P_DEVICE 6 3861 #define IWM_FW_MAC_TYPE_P2P_STA 7 3862 #define IWM_FW_MAC_TYPE_GO 8 3863 #define IWM_FW_MAC_TYPE_TEST 9 3864 #define IWM_FW_MAC_TYPE_MAX IWM_FW_MAC_TYPE_TEST 3865 /* IWM_MAC_CONTEXT_TYPE_API_E_VER_1 */ 3866 3867 /** 3868 * TSF hw timer ID 3869 * @IWM_TSF_ID_A: use TSF A 3870 * @IWM_TSF_ID_B: use TSF B 3871 * @IWM_TSF_ID_C: use TSF C 3872 * @IWM_TSF_ID_D: use TSF D 3873 * @IWM_NUM_TSF_IDS: number of TSF timers available 3874 */ 3875 #define IWM_TSF_ID_A 0 3876 #define IWM_TSF_ID_B 1 3877 #define IWM_TSF_ID_C 2 3878 #define IWM_TSF_ID_D 3 3879 #define IWM_NUM_TSF_IDS 4 3880 /* IWM_TSF_ID_API_E_VER_1 */ 3881 3882 /** 3883 * struct iwm_mac_data_ap - configuration data for AP MAC context 3884 * @beacon_time: beacon transmit time in system time 3885 * @beacon_tsf: beacon transmit time in TSF 3886 * @bi: beacon interval in TU 3887 * @bi_reciprocal: 2^32 / bi 3888 * @dtim_interval: dtim transmit time in TU 3889 * @dtim_reciprocal: 2^32 / dtim_interval 3890 * @mcast_qid: queue ID for multicast traffic 3891 * NOTE: obsolete from VER2 and on 3892 * @beacon_template: beacon template ID 3893 */ 3894 struct iwm_mac_data_ap { 3895 uint32_t beacon_time; 3896 uint64_t beacon_tsf; 3897 uint32_t bi; 3898 uint32_t bi_reciprocal; 3899 uint32_t dtim_interval; 3900 uint32_t dtim_reciprocal; 3901 uint32_t mcast_qid; 3902 uint32_t beacon_template; 3903 } __packed; /* AP_MAC_DATA_API_S_VER_2 */ 3904 3905 /** 3906 * struct iwm_mac_data_ibss - configuration data for IBSS MAC context 3907 * @beacon_time: beacon transmit time in system time 3908 * @beacon_tsf: beacon transmit time in TSF 3909 * @bi: beacon interval in TU 3910 * @bi_reciprocal: 2^32 / bi 3911 * @beacon_template: beacon template ID 3912 */ 3913 struct iwm_mac_data_ibss { 3914 uint32_t beacon_time; 3915 uint64_t beacon_tsf; 3916 uint32_t bi; 3917 uint32_t bi_reciprocal; 3918 uint32_t beacon_template; 3919 } __packed; /* IBSS_MAC_DATA_API_S_VER_1 */ 3920 3921 /** 3922 * struct iwm_mac_data_sta - configuration data for station MAC context 3923 * @is_assoc: 1 for associated state, 0 otherwise 3924 * @dtim_time: DTIM arrival time in system time 3925 * @dtim_tsf: DTIM arrival time in TSF 3926 * @bi: beacon interval in TU, applicable only when associated 3927 * @bi_reciprocal: 2^32 / bi , applicable only when associated 3928 * @dtim_interval: DTIM interval in TU, applicable only when associated 3929 * @dtim_reciprocal: 2^32 / dtim_interval , applicable only when associated 3930 * @listen_interval: in beacon intervals, applicable only when associated 3931 * @assoc_id: unique ID assigned by the AP during association 3932 */ 3933 struct iwm_mac_data_sta { 3934 uint32_t is_assoc; 3935 uint32_t dtim_time; 3936 uint64_t dtim_tsf; 3937 uint32_t bi; 3938 uint32_t bi_reciprocal; 3939 uint32_t dtim_interval; 3940 uint32_t dtim_reciprocal; 3941 uint32_t listen_interval; 3942 uint32_t assoc_id; 3943 uint32_t assoc_beacon_arrive_time; 3944 } __packed; /* IWM_STA_MAC_DATA_API_S_VER_1 */ 3945 3946 /** 3947 * struct iwm_mac_data_go - configuration data for P2P GO MAC context 3948 * @ap: iwm_mac_data_ap struct with most config data 3949 * @ctwin: client traffic window in TU (period after TBTT when GO is present). 3950 * 0 indicates that there is no CT window. 3951 * @opp_ps_enabled: indicate that opportunistic PS allowed 3952 */ 3953 struct iwm_mac_data_go { 3954 struct iwm_mac_data_ap ap; 3955 uint32_t ctwin; 3956 uint32_t opp_ps_enabled; 3957 } __packed; /* GO_MAC_DATA_API_S_VER_1 */ 3958 3959 /** 3960 * struct iwm_mac_data_p2p_sta - configuration data for P2P client MAC context 3961 * @sta: iwm_mac_data_sta struct with most config data 3962 * @ctwin: client traffic window in TU (period after TBTT when GO is present). 3963 * 0 indicates that there is no CT window. 3964 */ 3965 struct iwm_mac_data_p2p_sta { 3966 struct iwm_mac_data_sta sta; 3967 uint32_t ctwin; 3968 } __packed; /* P2P_STA_MAC_DATA_API_S_VER_1 */ 3969 3970 /** 3971 * struct iwm_mac_data_pibss - Pseudo IBSS config data 3972 * @stats_interval: interval in TU between statistics notifications to host. 3973 */ 3974 struct iwm_mac_data_pibss { 3975 uint32_t stats_interval; 3976 } __packed; /* PIBSS_MAC_DATA_API_S_VER_1 */ 3977 3978 /* 3979 * struct iwm_mac_data_p2p_dev - configuration data for the P2P Device MAC 3980 * context. 3981 * @is_disc_extended: if set to true, P2P Device discoverability is enabled on 3982 * other channels as well. This should be to true only in case that the 3983 * device is discoverable and there is an active GO. Note that setting this 3984 * field when not needed, will increase the number of interrupts and have 3985 * effect on the platform power, as this setting opens the Rx filters on 3986 * all macs. 3987 */ 3988 struct iwm_mac_data_p2p_dev { 3989 uint32_t is_disc_extended; 3990 } __packed; /* _P2P_DEV_MAC_DATA_API_S_VER_1 */ 3991 3992 /** 3993 * MAC context filter flags 3994 * @IWM_MAC_FILTER_IN_PROMISC: accept all data frames 3995 * @IWM_MAC_FILTER_IN_CONTROL_AND_MGMT: pass all mangement and 3996 * control frames to the host 3997 * @IWM_MAC_FILTER_ACCEPT_GRP: accept multicast frames 3998 * @IWM_MAC_FILTER_DIS_DECRYPT: don't decrypt unicast frames 3999 * @IWM_MAC_FILTER_DIS_GRP_DECRYPT: don't decrypt multicast frames 4000 * @IWM_MAC_FILTER_IN_BEACON: transfer foreign BSS's beacons to host 4001 * (in station mode when associated) 4002 * @IWM_MAC_FILTER_OUT_BCAST: filter out all broadcast frames 4003 * @IWM_MAC_FILTER_IN_CRC32: extract FCS and append it to frames 4004 * @IWM_MAC_FILTER_IN_PROBE_REQUEST: pass probe requests to host 4005 */ 4006 #define IWM_MAC_FILTER_IN_PROMISC (1 << 0) 4007 #define IWM_MAC_FILTER_IN_CONTROL_AND_MGMT (1 << 1) 4008 #define IWM_MAC_FILTER_ACCEPT_GRP (1 << 2) 4009 #define IWM_MAC_FILTER_DIS_DECRYPT (1 << 3) 4010 #define IWM_MAC_FILTER_DIS_GRP_DECRYPT (1 << 4) 4011 #define IWM_MAC_FILTER_IN_BEACON (1 << 6) 4012 #define IWM_MAC_FILTER_OUT_BCAST (1 << 8) 4013 #define IWM_MAC_FILTER_IN_CRC32 (1 << 11) 4014 #define IWM_MAC_FILTER_IN_PROBE_REQUEST (1 << 12) 4015 4016 /** 4017 * QoS flags 4018 * @IWM_MAC_QOS_FLG_UPDATE_EDCA: ? 4019 * @IWM_MAC_QOS_FLG_TGN: HT is enabled 4020 * @IWM_MAC_QOS_FLG_TXOP_TYPE: ? 4021 * 4022 */ 4023 #define IWM_MAC_QOS_FLG_UPDATE_EDCA (1 << 0) 4024 #define IWM_MAC_QOS_FLG_TGN (1 << 1) 4025 #define IWM_MAC_QOS_FLG_TXOP_TYPE (1 << 4) 4026 4027 /** 4028 * struct iwm_ac_qos - QOS timing params for IWM_MAC_CONTEXT_CMD 4029 * @cw_min: Contention window, start value in numbers of slots. 4030 * Should be a power-of-2, minus 1. Device's default is 0x0f. 4031 * @cw_max: Contention window, max value in numbers of slots. 4032 * Should be a power-of-2, minus 1. Device's default is 0x3f. 4033 * @aifsn: Number of slots in Arbitration Interframe Space (before 4034 * performing random backoff timing prior to Tx). Device default 1. 4035 * @fifos_mask: FIFOs used by this MAC for this AC 4036 * @edca_txop: Length of Tx opportunity, in uSecs. Device default is 0. 4037 * 4038 * One instance of this config struct for each of 4 EDCA access categories 4039 * in struct iwm_qosparam_cmd. 4040 * 4041 * Device will automatically increase contention window by (2*CW) + 1 for each 4042 * transmission retry. Device uses cw_max as a bit mask, ANDed with new CW 4043 * value, to cap the CW value. 4044 */ 4045 struct iwm_ac_qos { 4046 uint16_t cw_min; 4047 uint16_t cw_max; 4048 uint8_t aifsn; 4049 uint8_t fifos_mask; 4050 uint16_t edca_txop; 4051 } __packed; /* IWM_AC_QOS_API_S_VER_2 */ 4052 4053 /** 4054 * struct iwm_mac_ctx_cmd - command structure to configure MAC contexts 4055 * ( IWM_MAC_CONTEXT_CMD = 0x28 ) 4056 * @id_and_color: ID and color of the MAC 4057 * @action: action to perform, one of IWM_FW_CTXT_ACTION_* 4058 * @mac_type: one of IWM_FW_MAC_TYPE_* 4059 * @tsf_id: TSF HW timer, one of IWM_TSF_ID_* 4060 * @node_addr: MAC address 4061 * @bssid_addr: BSSID 4062 * @cck_rates: basic rates available for CCK 4063 * @ofdm_rates: basic rates available for OFDM 4064 * @protection_flags: combination of IWM_MAC_PROT_FLG_FLAG_* 4065 * @cck_short_preamble: 0x20 for enabling short preamble, 0 otherwise 4066 * @short_slot: 0x10 for enabling short slots, 0 otherwise 4067 * @filter_flags: combination of IWM_MAC_FILTER_* 4068 * @qos_flags: from IWM_MAC_QOS_FLG_* 4069 * @ac: one iwm_mac_qos configuration for each AC 4070 * @mac_specific: one of struct iwm_mac_data_*, according to mac_type 4071 */ 4072 struct iwm_mac_ctx_cmd { 4073 /* COMMON_INDEX_HDR_API_S_VER_1 */ 4074 uint32_t id_and_color; 4075 uint32_t action; 4076 /* IWM_MAC_CONTEXT_COMMON_DATA_API_S_VER_1 */ 4077 uint32_t mac_type; 4078 uint32_t tsf_id; 4079 uint8_t node_addr[6]; 4080 uint16_t reserved_for_node_addr; 4081 uint8_t bssid_addr[6]; 4082 uint16_t reserved_for_bssid_addr; 4083 uint32_t cck_rates; 4084 uint32_t ofdm_rates; 4085 uint32_t protection_flags; 4086 uint32_t cck_short_preamble; 4087 uint32_t short_slot; 4088 uint32_t filter_flags; 4089 /* IWM_MAC_QOS_PARAM_API_S_VER_1 */ 4090 uint32_t qos_flags; 4091 struct iwm_ac_qos ac[IWM_AC_NUM+1]; 4092 /* IWM_MAC_CONTEXT_COMMON_DATA_API_S */ 4093 union { 4094 struct iwm_mac_data_ap ap; 4095 struct iwm_mac_data_go go; 4096 struct iwm_mac_data_sta sta; 4097 struct iwm_mac_data_p2p_sta p2p_sta; 4098 struct iwm_mac_data_p2p_dev p2p_dev; 4099 struct iwm_mac_data_pibss pibss; 4100 struct iwm_mac_data_ibss ibss; 4101 }; 4102 } __packed; /* IWM_MAC_CONTEXT_CMD_API_S_VER_1 */ 4103 4104 static inline uint32_t iwm_reciprocal(uint32_t v) 4105 { 4106 if (!v) 4107 return 0; 4108 return 0xFFFFFFFF / v; 4109 } 4110 4111 #define IWM_NONQOS_SEQ_GET 0x1 4112 #define IWM_NONQOS_SEQ_SET 0x2 4113 struct iwm_nonqos_seq_query_cmd { 4114 uint32_t get_set_flag; 4115 uint32_t mac_id_n_color; 4116 uint16_t value; 4117 uint16_t reserved; 4118 } __packed; /* IWM_NON_QOS_TX_COUNTER_GET_SET_API_S_VER_1 */ 4119 4120 /* 4121 * END mvm/fw-api-mac.h 4122 */ 4123 4124 /* 4125 * BEGIN mvm/fw-api-power.h 4126 */ 4127 4128 /* Power Management Commands, Responses, Notifications */ 4129 4130 /** 4131 * masks for LTR config command flags 4132 * @IWM_LTR_CFG_FLAG_FEATURE_ENABLE: Feature operational status 4133 * @IWM_LTR_CFG_FLAG_HW_DIS_ON_SHADOW_REG_ACCESS: allow LTR change on shadow 4134 * memory access 4135 * @IWM_LTR_CFG_FLAG_HW_EN_SHRT_WR_THROUGH: allow LTR msg send on ANY LTR 4136 * reg change 4137 * @IWM_LTR_CFG_FLAG_HW_DIS_ON_D0_2_D3: allow LTR msg send on transition from 4138 * D0 to D3 4139 * @IWM_LTR_CFG_FLAG_SW_SET_SHORT: fixed static short LTR register 4140 * @IWM_LTR_CFG_FLAG_SW_SET_LONG: fixed static short LONG register 4141 * @IWM_LTR_CFG_FLAG_DENIE_C10_ON_PD: allow going into C10 on PD 4142 */ 4143 #define IWM_LTR_CFG_FLAG_FEATURE_ENABLE 0x00000001 4144 #define IWM_LTR_CFG_FLAG_HW_DIS_ON_SHADOW_REG_ACCESS 0x00000002 4145 #define IWM_LTR_CFG_FLAG_HW_EN_SHRT_WR_THROUGH 0x00000004 4146 #define IWM_LTR_CFG_FLAG_HW_DIS_ON_D0_2_D3 0x00000008 4147 #define IWM_LTR_CFG_FLAG_SW_SET_SHORT 0x00000010 4148 #define IWM_LTR_CFG_FLAG_SW_SET_LONG 0x00000020 4149 #define IWM_LTR_CFG_FLAG_DENIE_C10_ON_PD 0x00000040 4150 4151 /** 4152 * struct iwm_ltr_config_cmd_v1 - configures the LTR 4153 * @flags: See %enum iwm_ltr_config_flags 4154 */ 4155 struct iwm_ltr_config_cmd_v1 { 4156 uint32_t flags; 4157 uint32_t static_long; 4158 uint32_t static_short; 4159 } __packed; /* LTR_CAPABLE_API_S_VER_1 */ 4160 4161 #define IWM_LTR_VALID_STATES_NUM 4 4162 4163 /** 4164 * struct iwm_ltr_config_cmd - configures the LTR 4165 * @flags: See %enum iwm_ltr_config_flags 4166 * @static_long: 4167 * @static_short: 4168 * @ltr_cfg_values: 4169 * @ltr_short_idle_timeout: 4170 */ 4171 struct iwm_ltr_config_cmd { 4172 uint32_t flags; 4173 uint32_t static_long; 4174 uint32_t static_short; 4175 uint32_t ltr_cfg_values[IWM_LTR_VALID_STATES_NUM]; 4176 uint32_t ltr_short_idle_timeout; 4177 } __packed; /* LTR_CAPABLE_API_S_VER_2 */ 4178 4179 /* Radio LP RX Energy Threshold measured in dBm */ 4180 #define IWM_POWER_LPRX_RSSI_THRESHOLD 75 4181 #define IWM_POWER_LPRX_RSSI_THRESHOLD_MAX 94 4182 #define IWM_POWER_LPRX_RSSI_THRESHOLD_MIN 30 4183 4184 /** 4185 * Masks for iwm_mac_power_cmd command flags 4186 * @IWM_POWER_FLAGS_POWER_SAVE_ENA_MSK: '1' Allow to save power by turning off 4187 * receiver and transmitter. '0' - does not allow. 4188 * @IWM_POWER_FLAGS_POWER_MANAGEMENT_ENA_MSK: '0' Driver disables power management, 4189 * '1' Driver enables PM (use rest of parameters) 4190 * @IWM_POWER_FLAGS_SKIP_OVER_DTIM_MSK: '0' PM have to walk up every DTIM, 4191 * '1' PM could sleep over DTIM till listen Interval. 4192 * @IWM_POWER_FLAGS_SNOOZE_ENA_MSK: Enable snoozing only if uAPSD is enabled and all 4193 * access categories are both delivery and trigger enabled. 4194 * @IWM_POWER_FLAGS_BT_SCO_ENA: Enable BT SCO coex only if uAPSD and 4195 * PBW Snoozing enabled 4196 * @IWM_POWER_FLAGS_ADVANCE_PM_ENA_MSK: Advanced PM (uAPSD) enable mask 4197 * @IWM_POWER_FLAGS_LPRX_ENA_MSK: Low Power RX enable. 4198 * @IWM_POWER_FLAGS_AP_UAPSD_MISBEHAVING_ENA_MSK: AP/GO's uAPSD misbehaving 4199 * detection enablement 4200 */ 4201 #define IWM_POWER_FLAGS_POWER_SAVE_ENA_MSK (1 << 0) 4202 #define IWM_POWER_FLAGS_POWER_MANAGEMENT_ENA_MSK (1 << 1) 4203 #define IWM_POWER_FLAGS_SKIP_OVER_DTIM_MSK (1 << 2) 4204 #define IWM_POWER_FLAGS_SNOOZE_ENA_MSK (1 << 5) 4205 #define IWM_POWER_FLAGS_BT_SCO_ENA (1 << 8) 4206 #define IWM_POWER_FLAGS_ADVANCE_PM_ENA_MSK (1 << 9) 4207 #define IWM_POWER_FLAGS_LPRX_ENA_MSK (1 << 11) 4208 #define IWM_POWER_FLAGS_UAPSD_MISBEHAVING_ENA_MSK (1 << 12) 4209 4210 #define IWM_POWER_VEC_SIZE 5 4211 4212 /** 4213 * Masks for device power command flags 4214 * @IWM_DEVICE_POWER_FLAGS_POWER_SAVE_ENA_MSK: 4215 * '1' Allow to save power by turning off receiver and transmitter. 4216 * '0' Do not allow. This flag should be always set to '1' unless 4217 * one needs to disable actual power down for debug purposes. 4218 * @IWM_DEVICE_POWER_FLAGS_CAM_MSK: 4219 * '1' CAM (Continuous Active Mode) is set, power management is disabled. 4220 * '0' Power management is enabled, one of the power schemes is applied. 4221 */ 4222 #define IWM_DEVICE_POWER_FLAGS_POWER_SAVE_ENA_MSK (1 << 0) 4223 #define IWM_DEVICE_POWER_FLAGS_CAM_MSK (1 << 13) 4224 4225 /** 4226 * struct iwm_device_power_cmd - device wide power command. 4227 * IWM_POWER_TABLE_CMD = 0x77 (command, has simple generic response) 4228 * 4229 * @flags: Power table command flags from IWM_DEVICE_POWER_FLAGS_* 4230 */ 4231 struct iwm_device_power_cmd { 4232 /* PM_POWER_TABLE_CMD_API_S_VER_6 */ 4233 uint16_t flags; 4234 uint16_t reserved; 4235 } __packed; 4236 4237 /** 4238 * struct iwm_mac_power_cmd - New power command containing uAPSD support 4239 * IWM_MAC_PM_POWER_TABLE = 0xA9 (command, has simple generic response) 4240 * @id_and_color: MAC contex identifier 4241 * @flags: Power table command flags from POWER_FLAGS_* 4242 * @keep_alive_seconds: Keep alive period in seconds. Default - 25 sec. 4243 * Minimum allowed:- 3 * DTIM. Keep alive period must be 4244 * set regardless of power scheme or current power state. 4245 * FW use this value also when PM is disabled. 4246 * @rx_data_timeout: Minimum time (usec) from last Rx packet for AM to 4247 * PSM transition - legacy PM 4248 * @tx_data_timeout: Minimum time (usec) from last Tx packet for AM to 4249 * PSM transition - legacy PM 4250 * @sleep_interval: not in use 4251 * @skip_dtim_periods: Number of DTIM periods to skip if Skip over DTIM flag 4252 * is set. For example, if it is required to skip over 4253 * one DTIM, this value need to be set to 2 (DTIM periods). 4254 * @rx_data_timeout_uapsd: Minimum time (usec) from last Rx packet for AM to 4255 * PSM transition - uAPSD 4256 * @tx_data_timeout_uapsd: Minimum time (usec) from last Tx packet for AM to 4257 * PSM transition - uAPSD 4258 * @lprx_rssi_threshold: Signal strength up to which LP RX can be enabled. 4259 * Default: 80dbm 4260 * @num_skip_dtim: Number of DTIMs to skip if Skip over DTIM flag is set 4261 * @snooze_interval: Maximum time between attempts to retrieve buffered data 4262 * from the AP [msec] 4263 * @snooze_window: A window of time in which PBW snoozing insures that all 4264 * packets received. It is also the minimum time from last 4265 * received unicast RX packet, before client stops snoozing 4266 * for data. [msec] 4267 * @snooze_step: TBD 4268 * @qndp_tid: TID client shall use for uAPSD QNDP triggers 4269 * @uapsd_ac_flags: Set trigger-enabled and delivery-enabled indication for 4270 * each corresponding AC. 4271 * Use IEEE80211_WMM_IE_STA_QOSINFO_AC* for correct values. 4272 * @uapsd_max_sp: Use IEEE80211_WMM_IE_STA_QOSINFO_SP_* for correct 4273 * values. 4274 * @heavy_tx_thld_packets: TX threshold measured in number of packets 4275 * @heavy_rx_thld_packets: RX threshold measured in number of packets 4276 * @heavy_tx_thld_percentage: TX threshold measured in load's percentage 4277 * @heavy_rx_thld_percentage: RX threshold measured in load's percentage 4278 * @limited_ps_threshold: 4279 */ 4280 struct iwm_mac_power_cmd { 4281 /* CONTEXT_DESC_API_T_VER_1 */ 4282 uint32_t id_and_color; 4283 4284 /* CLIENT_PM_POWER_TABLE_S_VER_1 */ 4285 uint16_t flags; 4286 uint16_t keep_alive_seconds; 4287 uint32_t rx_data_timeout; 4288 uint32_t tx_data_timeout; 4289 uint32_t rx_data_timeout_uapsd; 4290 uint32_t tx_data_timeout_uapsd; 4291 uint8_t lprx_rssi_threshold; 4292 uint8_t skip_dtim_periods; 4293 uint16_t snooze_interval; 4294 uint16_t snooze_window; 4295 uint8_t snooze_step; 4296 uint8_t qndp_tid; 4297 uint8_t uapsd_ac_flags; 4298 uint8_t uapsd_max_sp; 4299 uint8_t heavy_tx_thld_packets; 4300 uint8_t heavy_rx_thld_packets; 4301 uint8_t heavy_tx_thld_percentage; 4302 uint8_t heavy_rx_thld_percentage; 4303 uint8_t limited_ps_threshold; 4304 uint8_t reserved; 4305 } __packed; 4306 4307 #define IWM_DEFAULT_PS_TX_DATA_TIMEOUT (100 * 1000) 4308 #define IWM_DEFAULT_PS_RX_DATA_TIMEOUT (100 * 1000) 4309 4310 /* 4311 * struct iwm_uapsd_misbehaving_ap_notif - FW sends this notification when 4312 * associated AP is identified as improperly implementing uAPSD protocol. 4313 * IWM_PSM_UAPSD_AP_MISBEHAVING_NOTIFICATION = 0x78 4314 * @sta_id: index of station in uCode's station table - associated AP ID in 4315 * this context. 4316 */ 4317 struct iwm_uapsd_misbehaving_ap_notif { 4318 uint32_t sta_id; 4319 uint8_t mac_id; 4320 uint8_t reserved[3]; 4321 } __packed; 4322 4323 /** 4324 * struct iwm_beacon_filter_cmd 4325 * IWM_REPLY_BEACON_FILTERING_CMD = 0xd2 (command) 4326 * @id_and_color: MAC contex identifier 4327 * @bf_energy_delta: Used for RSSI filtering, if in 'normal' state. Send beacon 4328 * to driver if delta in Energy values calculated for this and last 4329 * passed beacon is greater than this threshold. Zero value means that 4330 * the Energy change is ignored for beacon filtering, and beacon will 4331 * not be forced to be sent to driver regardless of this delta. Typical 4332 * energy delta 5dB. 4333 * @bf_roaming_energy_delta: Used for RSSI filtering, if in 'roaming' state. 4334 * Send beacon to driver if delta in Energy values calculated for this 4335 * and last passed beacon is greater than this threshold. Zero value 4336 * means that the Energy change is ignored for beacon filtering while in 4337 * Roaming state, typical energy delta 1dB. 4338 * @bf_roaming_state: Used for RSSI filtering. If absolute Energy values 4339 * calculated for current beacon is less than the threshold, use 4340 * Roaming Energy Delta Threshold, otherwise use normal Energy Delta 4341 * Threshold. Typical energy threshold is -72dBm. 4342 * @bf_temp_threshold: This threshold determines the type of temperature 4343 * filtering (Slow or Fast) that is selected (Units are in Celsuis): 4344 * If the current temperature is above this threshold - Fast filter 4345 * will be used, If the current temperature is below this threshold - 4346 * Slow filter will be used. 4347 * @bf_temp_fast_filter: Send Beacon to driver if delta in temperature values 4348 * calculated for this and the last passed beacon is greater than this 4349 * threshold. Zero value means that the temperature change is ignored for 4350 * beacon filtering; beacons will not be forced to be sent to driver 4351 * regardless of whether its temerature has been changed. 4352 * @bf_temp_slow_filter: Send Beacon to driver if delta in temperature values 4353 * calculated for this and the last passed beacon is greater than this 4354 * threshold. Zero value means that the temperature change is ignored for 4355 * beacon filtering; beacons will not be forced to be sent to driver 4356 * regardless of whether its temerature has been changed. 4357 * @bf_enable_beacon_filter: 1, beacon filtering is enabled; 0, disabled. 4358 * @bf_escape_timer: Send beacons to driver if no beacons were passed 4359 * for a specific period of time. Units: Beacons. 4360 * @ba_escape_timer: Fully receive and parse beacon if no beacons were passed 4361 * for a longer period of time then this escape-timeout. Units: Beacons. 4362 * @ba_enable_beacon_abort: 1, beacon abort is enabled; 0, disabled. 4363 */ 4364 struct iwm_beacon_filter_cmd { 4365 uint32_t bf_energy_delta; 4366 uint32_t bf_roaming_energy_delta; 4367 uint32_t bf_roaming_state; 4368 uint32_t bf_temp_threshold; 4369 uint32_t bf_temp_fast_filter; 4370 uint32_t bf_temp_slow_filter; 4371 uint32_t bf_enable_beacon_filter; 4372 uint32_t bf_debug_flag; 4373 uint32_t bf_escape_timer; 4374 uint32_t ba_escape_timer; 4375 uint32_t ba_enable_beacon_abort; 4376 } __packed; 4377 4378 /* Beacon filtering and beacon abort */ 4379 #define IWM_BF_ENERGY_DELTA_DEFAULT 5 4380 #define IWM_BF_ENERGY_DELTA_MAX 255 4381 #define IWM_BF_ENERGY_DELTA_MIN 0 4382 4383 #define IWM_BF_ROAMING_ENERGY_DELTA_DEFAULT 1 4384 #define IWM_BF_ROAMING_ENERGY_DELTA_MAX 255 4385 #define IWM_BF_ROAMING_ENERGY_DELTA_MIN 0 4386 4387 #define IWM_BF_ROAMING_STATE_DEFAULT 72 4388 #define IWM_BF_ROAMING_STATE_MAX 255 4389 #define IWM_BF_ROAMING_STATE_MIN 0 4390 4391 #define IWM_BF_TEMP_THRESHOLD_DEFAULT 112 4392 #define IWM_BF_TEMP_THRESHOLD_MAX 255 4393 #define IWM_BF_TEMP_THRESHOLD_MIN 0 4394 4395 #define IWM_BF_TEMP_FAST_FILTER_DEFAULT 1 4396 #define IWM_BF_TEMP_FAST_FILTER_MAX 255 4397 #define IWM_BF_TEMP_FAST_FILTER_MIN 0 4398 4399 #define IWM_BF_TEMP_SLOW_FILTER_DEFAULT 5 4400 #define IWM_BF_TEMP_SLOW_FILTER_MAX 255 4401 #define IWM_BF_TEMP_SLOW_FILTER_MIN 0 4402 4403 #define IWM_BF_ENABLE_BEACON_FILTER_DEFAULT 1 4404 4405 #define IWM_BF_DEBUG_FLAG_DEFAULT 0 4406 4407 #define IWM_BF_ESCAPE_TIMER_DEFAULT 50 4408 #define IWM_BF_ESCAPE_TIMER_MAX 1024 4409 #define IWM_BF_ESCAPE_TIMER_MIN 0 4410 4411 #define IWM_BA_ESCAPE_TIMER_DEFAULT 6 4412 #define IWM_BA_ESCAPE_TIMER_D3 9 4413 #define IWM_BA_ESCAPE_TIMER_MAX 1024 4414 #define IWM_BA_ESCAPE_TIMER_MIN 0 4415 4416 #define IWM_BA_ENABLE_BEACON_ABORT_DEFAULT 1 4417 4418 #define IWM_BF_CMD_CONFIG_DEFAULTS \ 4419 .bf_energy_delta = htole32(IWM_BF_ENERGY_DELTA_DEFAULT), \ 4420 .bf_roaming_energy_delta = \ 4421 htole32(IWM_BF_ROAMING_ENERGY_DELTA_DEFAULT), \ 4422 .bf_roaming_state = htole32(IWM_BF_ROAMING_STATE_DEFAULT), \ 4423 .bf_temp_threshold = htole32(IWM_BF_TEMP_THRESHOLD_DEFAULT), \ 4424 .bf_temp_fast_filter = htole32(IWM_BF_TEMP_FAST_FILTER_DEFAULT), \ 4425 .bf_temp_slow_filter = htole32(IWM_BF_TEMP_SLOW_FILTER_DEFAULT), \ 4426 .bf_debug_flag = htole32(IWM_BF_DEBUG_FLAG_DEFAULT), \ 4427 .bf_escape_timer = htole32(IWM_BF_ESCAPE_TIMER_DEFAULT), \ 4428 .ba_escape_timer = htole32(IWM_BA_ESCAPE_TIMER_DEFAULT) 4429 4430 /* 4431 * END mvm/fw-api-power.h 4432 */ 4433 4434 /* 4435 * BEGIN mvm/fw-api-rs.h 4436 */ 4437 4438 4439 /* uCode API values for HT/VHT bit rates */ 4440 #define IWM_RATE_HT_SISO_MCS_0_PLCP 0 4441 #define IWM_RATE_HT_SISO_MCS_1_PLCP 1 4442 #define IWM_RATE_HT_SISO_MCS_2_PLCP 2 4443 #define IWM_RATE_HT_SISO_MCS_3_PLCP 3 4444 #define IWM_RATE_HT_SISO_MCS_4_PLCP 4 4445 #define IWM_RATE_HT_SISO_MCS_5_PLCP 5 4446 #define IWM_RATE_HT_SISO_MCS_6_PLCP 6 4447 #define IWM_RATE_HT_SISO_MCS_7_PLCP 7 4448 #define IWM_RATE_HT_MIMO2_MCS_8_PLCP 0x8 4449 #define IWM_RATE_HT_MIMO2_MCS_9_PLCP 0x9 4450 #define IWM_RATE_HT_MIMO2_MCS_10_PLCP 0xA 4451 #define IWM_RATE_HT_MIMO2_MCS_11_PLCP 0xB 4452 #define IWM_RATE_HT_MIMO2_MCS_12_PLCP 0xC 4453 #define IWM_RATE_HT_MIMO2_MCS_13_PLCP 0xD 4454 #define IWM_RATE_HT_MIMO2_MCS_14_PLCP 0xE 4455 #define IWM_RATE_HT_MIMO2_MCS_15_PLCP 0xF 4456 #define IWM_RATE_VHT_SISO_MCS_0_PLCP 0 4457 #define IWM_RATE_VHT_SISO_MCS_1_PLCP 1 4458 #define IWM_RATE_VHT_SISO_MCS_2_PLCP 2 4459 #define IWM_RATE_VHT_SISO_MCS_3_PLCP 3 4460 #define IWM_RATE_VHT_SISO_MCS_4_PLCP 4 4461 #define IWM_RATE_VHT_SISO_MCS_5_PLCP 5 4462 #define IWM_RATE_VHT_SISO_MCS_6_PLCP 6 4463 #define IWM_RATE_VHT_SISO_MCS_7_PLCP 7 4464 #define IWM_RATE_VHT_SISO_MCS_8_PLCP 8 4465 #define IWM_RATE_VHT_SISO_MCS_9_PLCP 9 4466 #define IWM_RATE_VHT_MIMO2_MCS_0_PLCP 0x10 4467 #define IWM_RATE_VHT_MIMO2_MCS_1_PLCP 0x11 4468 #define IWM_RATE_VHT_MIMO2_MCS_2_PLCP 0x12 4469 #define IWM_RATE_VHT_MIMO2_MCS_3_PLCP 0x13 4470 #define IWM_RATE_VHT_MIMO2_MCS_4_PLCP 0x14 4471 #define IWM_RATE_VHT_MIMO2_MCS_5_PLCP 0x15 4472 #define IWM_RATE_VHT_MIMO2_MCS_6_PLCP 0x16 4473 #define IWM_RATE_VHT_MIMO2_MCS_7_PLCP 0x17 4474 #define IWM_RATE_VHT_MIMO2_MCS_8_PLCP 0x18 4475 #define IWM_RATE_VHT_MIMO2_MCS_9_PLCP 0x19 4476 #define IWM_RATE_HT_SISO_MCS_INV_PLCP 0x20 4477 #define IWM_RATE_HT_MIMO2_MCS_INV_PLCP IWM_RATE_HT_SISO_MCS_INV_PLCP 4478 #define IWM_RATE_VHT_SISO_MCS_INV_PLCP IWM_RATE_HT_SISO_MCS_INV_PLCP 4479 #define IWM_RATE_VHT_MIMO2_MCS_INV_PLCP IWM_RATE_HT_SISO_MCS_INV_PLCP 4480 #define IWM_RATE_HT_SISO_MCS_8_PLCP IWM_RATE_HT_SISO_MCS_INV_PLCP 4481 #define IWM_RATE_HT_SISO_MCS_9_PLCP IWM_RATE_HT_SISO_MCS_INV_PLCP 4482 4483 /* 4484 * These serve as indexes into 4485 * struct iwm_rate_info fw_rate_idx_to_plcp[IWM_RATE_COUNT]; 4486 * TODO: avoid overlap between legacy and HT rates 4487 */ 4488 enum { 4489 IWM_RATE_1M_INDEX = 0, 4490 IWM_FIRST_CCK_RATE = IWM_RATE_1M_INDEX, 4491 IWM_RATE_2M_INDEX, 4492 IWM_RATE_5M_INDEX, 4493 IWM_RATE_11M_INDEX, 4494 IWM_LAST_CCK_RATE = IWM_RATE_11M_INDEX, 4495 IWM_RATE_6M_INDEX, 4496 IWM_FIRST_OFDM_RATE = IWM_RATE_6M_INDEX, 4497 IWM_RATE_MCS_0_INDEX = IWM_RATE_6M_INDEX, 4498 IWM_FIRST_HT_RATE = IWM_RATE_MCS_0_INDEX, 4499 IWM_FIRST_VHT_RATE = IWM_RATE_MCS_0_INDEX, 4500 IWM_RATE_9M_INDEX, 4501 IWM_RATE_12M_INDEX, 4502 IWM_RATE_MCS_1_INDEX = IWM_RATE_12M_INDEX, 4503 IWM_RATE_18M_INDEX, 4504 IWM_RATE_MCS_2_INDEX = IWM_RATE_18M_INDEX, 4505 IWM_RATE_24M_INDEX, 4506 IWM_RATE_MCS_3_INDEX = IWM_RATE_24M_INDEX, 4507 IWM_RATE_36M_INDEX, 4508 IWM_RATE_MCS_4_INDEX = IWM_RATE_36M_INDEX, 4509 IWM_RATE_48M_INDEX, 4510 IWM_RATE_MCS_5_INDEX = IWM_RATE_48M_INDEX, 4511 IWM_RATE_54M_INDEX, 4512 IWM_RATE_MCS_6_INDEX = IWM_RATE_54M_INDEX, 4513 IWM_LAST_NON_HT_RATE = IWM_RATE_54M_INDEX, 4514 IWM_RATE_60M_INDEX, 4515 IWM_RATE_MCS_7_INDEX = IWM_RATE_60M_INDEX, 4516 IWM_LAST_HT_RATE = IWM_RATE_MCS_7_INDEX, 4517 IWM_RATE_MCS_8_INDEX, 4518 IWM_RATE_MCS_9_INDEX, 4519 IWM_LAST_VHT_RATE = IWM_RATE_MCS_9_INDEX, 4520 IWM_RATE_COUNT_LEGACY = IWM_LAST_NON_HT_RATE + 1, 4521 IWM_RATE_COUNT = IWM_LAST_VHT_RATE + 1, 4522 }; 4523 4524 4525 #define IWM_RATE_BIT_MSK(r) (1 << (IWM_RATE_##r##M_INDEX)) 4526 4527 /* fw API values for legacy bit rates, both OFDM and CCK */ 4528 #define IWM_RATE_6M_PLCP 13 4529 #define IWM_RATE_9M_PLCP 15 4530 #define IWM_RATE_12M_PLCP 5 4531 #define IWM_RATE_18M_PLCP 7 4532 #define IWM_RATE_24M_PLCP 9 4533 #define IWM_RATE_36M_PLCP 11 4534 #define IWM_RATE_48M_PLCP 1 4535 #define IWM_RATE_54M_PLCP 3 4536 #define IWM_RATE_1M_PLCP 10 4537 #define IWM_RATE_2M_PLCP 20 4538 #define IWM_RATE_5M_PLCP 55 4539 #define IWM_RATE_11M_PLCP 110 4540 #define IWM_RATE_INVM_PLCP 0xff 4541 4542 /* 4543 * rate_n_flags bit fields 4544 * 4545 * The 32-bit value has different layouts in the low 8 bites depending on the 4546 * format. There are three formats, HT, VHT and legacy (11abg, with subformats 4547 * for CCK and OFDM). 4548 * 4549 * High-throughput (HT) rate format 4550 * bit 8 is 1, bit 26 is 0, bit 9 is 0 (OFDM) 4551 * Very High-throughput (VHT) rate format 4552 * bit 8 is 0, bit 26 is 1, bit 9 is 0 (OFDM) 4553 * Legacy OFDM rate format for bits 7:0 4554 * bit 8 is 0, bit 26 is 0, bit 9 is 0 (OFDM) 4555 * Legacy CCK rate format for bits 7:0: 4556 * bit 8 is 0, bit 26 is 0, bit 9 is 1 (CCK) 4557 */ 4558 4559 /* Bit 8: (1) HT format, (0) legacy or VHT format */ 4560 #define IWM_RATE_MCS_HT_POS 8 4561 #define IWM_RATE_MCS_HT_MSK (1 << IWM_RATE_MCS_HT_POS) 4562 4563 /* Bit 9: (1) CCK, (0) OFDM. HT (bit 8) must be "0" for this bit to be valid */ 4564 #define IWM_RATE_MCS_CCK_POS 9 4565 #define IWM_RATE_MCS_CCK_MSK (1 << IWM_RATE_MCS_CCK_POS) 4566 4567 /* Bit 26: (1) VHT format, (0) legacy format in bits 8:0 */ 4568 #define IWM_RATE_MCS_VHT_POS 26 4569 #define IWM_RATE_MCS_VHT_MSK (1 << IWM_RATE_MCS_VHT_POS) 4570 4571 /* Bit 31: (1) RTS (2) CTS */ 4572 #define IWM_RATE_MCS_RTS_REQUIRED_POS 30 4573 #define IWM_RATE_MCS_RTS_REQUIRED_MSK (1 << IWM_RATE_MCS_RTS_REQUIRED_POS) 4574 4575 /* 4576 * High-throughput (HT) rate format for bits 7:0 4577 * 4578 * 2-0: MCS rate base 4579 * 0) 6 Mbps 4580 * 1) 12 Mbps 4581 * 2) 18 Mbps 4582 * 3) 24 Mbps 4583 * 4) 36 Mbps 4584 * 5) 48 Mbps 4585 * 6) 54 Mbps 4586 * 7) 60 Mbps 4587 * 4-3: 0) Single stream (SISO) 4588 * 1) Dual stream (MIMO) 4589 * 2) Triple stream (MIMO) 4590 * 5: Value of 0x20 in bits 7:0 indicates 6 Mbps HT40 duplicate data 4591 * (bits 7-6 are zero) 4592 * 4593 * Together the low 5 bits work out to the MCS index because we don't 4594 * support MCSes above 15/23, and 0-7 have one stream, 8-15 have two 4595 * streams and 16-23 have three streams. We could also support MCS 32 4596 * which is the duplicate 20 MHz MCS (bit 5 set, all others zero.) 4597 */ 4598 #define IWM_RATE_HT_MCS_RATE_CODE_MSK 0x7 4599 #define IWM_RATE_HT_MCS_NSS_POS 3 4600 #define IWM_RATE_HT_MCS_NSS_MSK (3 << IWM_RATE_HT_MCS_NSS_POS) 4601 4602 /* Bit 10: (1) Use Green Field preamble */ 4603 #define IWM_RATE_HT_MCS_GF_POS 10 4604 #define IWM_RATE_HT_MCS_GF_MSK (1 << IWM_RATE_HT_MCS_GF_POS) 4605 4606 #define IWM_RATE_HT_MCS_INDEX_MSK 0x3f 4607 4608 /* 4609 * Very High-throughput (VHT) rate format for bits 7:0 4610 * 4611 * 3-0: VHT MCS (0-9) 4612 * 5-4: number of streams - 1: 4613 * 0) Single stream (SISO) 4614 * 1) Dual stream (MIMO) 4615 * 2) Triple stream (MIMO) 4616 */ 4617 4618 /* Bit 4-5: (0) SISO, (1) MIMO2 (2) MIMO3 */ 4619 #define IWM_RATE_VHT_MCS_RATE_CODE_MSK 0xf 4620 #define IWM_RATE_VHT_MCS_NSS_POS 4 4621 #define IWM_RATE_VHT_MCS_NSS_MSK (3 << IWM_RATE_VHT_MCS_NSS_POS) 4622 4623 /* 4624 * Legacy OFDM rate format for bits 7:0 4625 * 4626 * 3-0: 0xD) 6 Mbps 4627 * 0xF) 9 Mbps 4628 * 0x5) 12 Mbps 4629 * 0x7) 18 Mbps 4630 * 0x9) 24 Mbps 4631 * 0xB) 36 Mbps 4632 * 0x1) 48 Mbps 4633 * 0x3) 54 Mbps 4634 * (bits 7-4 are 0) 4635 * 4636 * Legacy CCK rate format for bits 7:0: 4637 * bit 8 is 0, bit 26 is 0, bit 9 is 1 (CCK): 4638 * 4639 * 6-0: 10) 1 Mbps 4640 * 20) 2 Mbps 4641 * 55) 5.5 Mbps 4642 * 110) 11 Mbps 4643 * (bit 7 is 0) 4644 */ 4645 #define IWM_RATE_LEGACY_RATE_MSK 0xff 4646 4647 4648 /* 4649 * Bit 11-12: (0) 20MHz, (1) 40MHz, (2) 80MHz, (3) 160MHz 4650 * 0 and 1 are valid for HT and VHT, 2 and 3 only for VHT 4651 */ 4652 #define IWM_RATE_MCS_CHAN_WIDTH_POS 11 4653 #define IWM_RATE_MCS_CHAN_WIDTH_MSK (3 << IWM_RATE_MCS_CHAN_WIDTH_POS) 4654 #define IWM_RATE_MCS_CHAN_WIDTH_20 (0 << IWM_RATE_MCS_CHAN_WIDTH_POS) 4655 #define IWM_RATE_MCS_CHAN_WIDTH_40 (1 << IWM_RATE_MCS_CHAN_WIDTH_POS) 4656 #define IWM_RATE_MCS_CHAN_WIDTH_80 (2 << IWM_RATE_MCS_CHAN_WIDTH_POS) 4657 #define IWM_RATE_MCS_CHAN_WIDTH_160 (3 << IWM_RATE_MCS_CHAN_WIDTH_POS) 4658 4659 /* Bit 13: (1) Short guard interval (0.4 usec), (0) normal GI (0.8 usec) */ 4660 #define IWM_RATE_MCS_SGI_POS 13 4661 #define IWM_RATE_MCS_SGI_MSK (1 << IWM_RATE_MCS_SGI_POS) 4662 4663 /* Bit 14-16: Antenna selection (1) Ant A, (2) Ant B, (4) Ant C */ 4664 #define IWM_RATE_MCS_ANT_POS 14 4665 #define IWM_RATE_MCS_ANT_A_MSK (1 << IWM_RATE_MCS_ANT_POS) 4666 #define IWM_RATE_MCS_ANT_B_MSK (2 << IWM_RATE_MCS_ANT_POS) 4667 #define IWM_RATE_MCS_ANT_C_MSK (4 << IWM_RATE_MCS_ANT_POS) 4668 #define IWM_RATE_MCS_ANT_AB_MSK (IWM_RATE_MCS_ANT_A_MSK | \ 4669 IWM_RATE_MCS_ANT_B_MSK) 4670 #define IWM_RATE_MCS_ANT_ABC_MSK (IWM_RATE_MCS_ANT_AB_MSK | \ 4671 IWM_RATE_MCS_ANT_C_MSK) 4672 #define IWM_RATE_MCS_ANT_MSK IWM_RATE_MCS_ANT_ABC_MSK 4673 #define IWM_RATE_MCS_ANT_NUM 3 4674 4675 /* Bit 17-18: (0) SS, (1) SS*2 */ 4676 #define IWM_RATE_MCS_STBC_POS 17 4677 #define IWM_RATE_MCS_STBC_MSK (1 << IWM_RATE_MCS_STBC_POS) 4678 4679 /* Bit 19: (0) Beamforming is off, (1) Beamforming is on */ 4680 #define IWM_RATE_MCS_BF_POS 19 4681 #define IWM_RATE_MCS_BF_MSK (1 << IWM_RATE_MCS_BF_POS) 4682 4683 /* Bit 20: (0) ZLF is off, (1) ZLF is on */ 4684 #define IWM_RATE_MCS_ZLF_POS 20 4685 #define IWM_RATE_MCS_ZLF_MSK (1 << IWM_RATE_MCS_ZLF_POS) 4686 4687 /* Bit 24-25: (0) 20MHz (no dup), (1) 2x20MHz, (2) 4x20MHz, 3 8x20MHz */ 4688 #define IWM_RATE_MCS_DUP_POS 24 4689 #define IWM_RATE_MCS_DUP_MSK (3 << IWM_RATE_MCS_DUP_POS) 4690 4691 /* Bit 27: (1) LDPC enabled, (0) LDPC disabled */ 4692 #define IWM_RATE_MCS_LDPC_POS 27 4693 #define IWM_RATE_MCS_LDPC_MSK (1 << IWM_RATE_MCS_LDPC_POS) 4694 4695 4696 /* Link Quality definitions */ 4697 4698 /* # entries in rate scale table to support Tx retries */ 4699 #define IWM_LQ_MAX_RETRY_NUM 16 4700 4701 /* Link quality command flags bit fields */ 4702 4703 /* Bit 0: (0) Don't use RTS (1) Use RTS */ 4704 #define IWM_LQ_FLAG_USE_RTS_POS 0 4705 #define IWM_LQ_FLAG_USE_RTS_MSK (1 << IWM_LQ_FLAG_USE_RTS_POS) 4706 4707 /* Bit 1-3: LQ command color. Used to match responses to LQ commands */ 4708 #define IWM_LQ_FLAG_COLOR_POS 1 4709 #define IWM_LQ_FLAG_COLOR_MSK (7 << IWM_LQ_FLAG_COLOR_POS) 4710 4711 /* Bit 4-5: Tx RTS BW Signalling 4712 * (0) No RTS BW signalling 4713 * (1) Static BW signalling 4714 * (2) Dynamic BW signalling 4715 */ 4716 #define IWM_LQ_FLAG_RTS_BW_SIG_POS 4 4717 #define IWM_LQ_FLAG_RTS_BW_SIG_NONE (0 << IWM_LQ_FLAG_RTS_BW_SIG_POS) 4718 #define IWM_LQ_FLAG_RTS_BW_SIG_STATIC (1 << IWM_LQ_FLAG_RTS_BW_SIG_POS) 4719 #define IWM_LQ_FLAG_RTS_BW_SIG_DYNAMIC (2 << IWM_LQ_FLAG_RTS_BW_SIG_POS) 4720 4721 /* Bit 6: (0) No dynamic BW selection (1) Allow dynamic BW selection 4722 * Dyanmic BW selection allows Tx with narrower BW then requested in rates 4723 */ 4724 #define IWM_LQ_FLAG_DYNAMIC_BW_POS 6 4725 #define IWM_LQ_FLAG_DYNAMIC_BW_MSK (1 << IWM_LQ_FLAG_DYNAMIC_BW_POS) 4726 4727 /* Antenna flags. */ 4728 #define IWM_ANT_A (1 << 0) 4729 #define IWM_ANT_B (1 << 1) 4730 #define IWM_ANT_C (1 << 2) 4731 /* Shortcuts. */ 4732 #define IWM_ANT_AB (IWM_ANT_A | IWM_ANT_B) 4733 #define IWM_ANT_BC (IWM_ANT_B | IWM_ANT_C) 4734 #define IWM_ANT_ABC (IWM_ANT_A | IWM_ANT_B | IWM_ANT_C) 4735 4736 /** 4737 * struct iwm_lq_cmd - link quality command 4738 * @sta_id: station to update 4739 * @control: not used 4740 * @flags: combination of IWM_LQ_FLAG_* 4741 * @mimo_delim: the first SISO index in rs_table, which separates MIMO 4742 * and SISO rates 4743 * @single_stream_ant_msk: best antenna for SISO (can be dual in CDD). 4744 * Should be IWM_ANT_[ABC] 4745 * @dual_stream_ant_msk: best antennas for MIMO, combination of IWM_ANT_[ABC] 4746 * @initial_rate_index: first index from rs_table per AC category 4747 * @agg_time_limit: aggregation max time threshold in usec/100, meaning 4748 * value of 100 is one usec. Range is 100 to 8000 4749 * @agg_disable_start_th: try-count threshold for starting aggregation. 4750 * If a frame has higher try-count, it should not be selected for 4751 * starting an aggregation sequence. 4752 * @agg_frame_cnt_limit: max frame count in an aggregation. 4753 * 0: no limit 4754 * 1: no aggregation (one frame per aggregation) 4755 * 2 - 0x3f: maximal number of frames (up to 3f == 63) 4756 * @rs_table: array of rates for each TX try, each is rate_n_flags, 4757 * meaning it is a combination of IWM_RATE_MCS_* and IWM_RATE_*_PLCP 4758 * @bf_params: beam forming params, currently not used 4759 */ 4760 struct iwm_lq_cmd { 4761 uint8_t sta_id; 4762 uint8_t reserved1; 4763 uint16_t control; 4764 /* LINK_QUAL_GENERAL_PARAMS_API_S_VER_1 */ 4765 uint8_t flags; 4766 uint8_t mimo_delim; 4767 uint8_t single_stream_ant_msk; 4768 uint8_t dual_stream_ant_msk; 4769 uint8_t initial_rate_index[IWM_AC_NUM]; 4770 /* LINK_QUAL_AGG_PARAMS_API_S_VER_1 */ 4771 uint16_t agg_time_limit; 4772 uint8_t agg_disable_start_th; 4773 uint8_t agg_frame_cnt_limit; 4774 uint32_t reserved2; 4775 uint32_t rs_table[IWM_LQ_MAX_RETRY_NUM]; 4776 uint32_t bf_params; 4777 }; /* LINK_QUALITY_CMD_API_S_VER_1 */ 4778 4779 /* 4780 * END mvm/fw-api-rs.h 4781 */ 4782 4783 /* 4784 * BEGIN mvm/fw-api-tx.h 4785 */ 4786 4787 /** 4788 * bitmasks for tx_flags in TX command 4789 * @IWM_TX_CMD_FLG_PROT_REQUIRE: use RTS or CTS-to-self to protect the frame 4790 * @IWM_TX_CMD_FLG_ACK: expect ACK from receiving station 4791 * @IWM_TX_CMD_FLG_STA_RATE: use RS table with initial index from the TX command. 4792 * Otherwise, use rate_n_flags from the TX command 4793 * @IWM_TX_CMD_FLG_BA: this frame is a block ack 4794 * @IWM_TX_CMD_FLG_BAR: this frame is a BA request, immediate BAR is expected 4795 * Must set IWM_TX_CMD_FLG_ACK with this flag. 4796 * @IWM_TX_CMD_FLG_TXOP_PROT: protect frame with full TXOP protection 4797 * @IWM_TX_CMD_FLG_VHT_NDPA: mark frame is NDPA for VHT beamformer sequence 4798 * @IWM_TX_CMD_FLG_HT_NDPA: mark frame is NDPA for HT beamformer sequence 4799 * @IWM_TX_CMD_FLG_CSI_FDBK2HOST: mark to send feedback to host (only if good CRC) 4800 * @IWM_TX_CMD_FLG_BT_DIS: disable BT priority for this frame 4801 * @IWM_TX_CMD_FLG_SEQ_CTL: set if FW should override the sequence control. 4802 * Should be set for mgmt, non-QOS data, mcast, bcast and in scan command 4803 * @IWM_TX_CMD_FLG_MORE_FRAG: this frame is non-last MPDU 4804 * @IWM_TX_CMD_FLG_NEXT_FRAME: this frame includes information of the next frame 4805 * @IWM_TX_CMD_FLG_TSF: FW should calculate and insert TSF in the frame 4806 * Should be set for beacons and probe responses 4807 * @IWM_TX_CMD_FLG_CALIB: activate PA TX power calibrations 4808 * @IWM_TX_CMD_FLG_KEEP_SEQ_CTL: if seq_ctl is set, don't increase inner seq count 4809 * @IWM_TX_CMD_FLG_AGG_START: allow this frame to start aggregation 4810 * @IWM_TX_CMD_FLG_MH_PAD: driver inserted 2 byte padding after MAC header. 4811 * Should be set for 26/30 length MAC headers 4812 * @IWM_TX_CMD_FLG_RESP_TO_DRV: zero this if the response should go only to FW 4813 * @IWM_TX_CMD_FLG_CCMP_AGG: this frame uses CCMP for aggregation acceleration 4814 * @IWM_TX_CMD_FLG_TKIP_MIC_DONE: FW already performed TKIP MIC calculation 4815 * @IWM_TX_CMD_FLG_DUR: disable duration overwriting used in PS-Poll Assoc-id 4816 * @IWM_TX_CMD_FLG_FW_DROP: FW should mark frame to be dropped 4817 * @IWM_TX_CMD_FLG_EXEC_PAPD: execute PAPD 4818 * @IWM_TX_CMD_FLG_PAPD_TYPE: 0 for reference power, 1 for nominal power 4819 * @IWM_TX_CMD_FLG_HCCA_CHUNK: mark start of TSPEC chunk 4820 */ 4821 #define IWM_TX_CMD_FLG_PROT_REQUIRE (1 << 0) 4822 #define IWM_TX_CMD_FLG_ACK (1 << 3) 4823 #define IWM_TX_CMD_FLG_STA_RATE (1 << 4) 4824 #define IWM_TX_CMD_FLG_BA (1 << 5) 4825 #define IWM_TX_CMD_FLG_BAR (1 << 6) 4826 #define IWM_TX_CMD_FLG_TXOP_PROT (1 << 7) 4827 #define IWM_TX_CMD_FLG_VHT_NDPA (1 << 8) 4828 #define IWM_TX_CMD_FLG_HT_NDPA (1 << 9) 4829 #define IWM_TX_CMD_FLG_CSI_FDBK2HOST (1 << 10) 4830 #define IWM_TX_CMD_FLG_BT_DIS (1 << 12) 4831 #define IWM_TX_CMD_FLG_SEQ_CTL (1 << 13) 4832 #define IWM_TX_CMD_FLG_MORE_FRAG (1 << 14) 4833 #define IWM_TX_CMD_FLG_NEXT_FRAME (1 << 15) 4834 #define IWM_TX_CMD_FLG_TSF (1 << 16) 4835 #define IWM_TX_CMD_FLG_CALIB (1 << 17) 4836 #define IWM_TX_CMD_FLG_KEEP_SEQ_CTL (1 << 18) 4837 #define IWM_TX_CMD_FLG_AGG_START (1 << 19) 4838 #define IWM_TX_CMD_FLG_MH_PAD (1 << 20) 4839 #define IWM_TX_CMD_FLG_RESP_TO_DRV (1 << 21) 4840 #define IWM_TX_CMD_FLG_CCMP_AGG (1 << 22) 4841 #define IWM_TX_CMD_FLG_TKIP_MIC_DONE (1 << 23) 4842 #define IWM_TX_CMD_FLG_DUR (1 << 25) 4843 #define IWM_TX_CMD_FLG_FW_DROP (1 << 26) 4844 #define IWM_TX_CMD_FLG_EXEC_PAPD (1 << 27) 4845 #define IWM_TX_CMD_FLG_PAPD_TYPE (1 << 28) 4846 #define IWM_TX_CMD_FLG_HCCA_CHUNK (1U << 31) 4847 /* IWM_TX_FLAGS_BITS_API_S_VER_1 */ 4848 4849 /** 4850 * enum iwm_tx_pm_timeouts - pm timeout values in TX command 4851 * @IWM_PM_FRAME_NONE: no need to suspend sleep mode 4852 * @IWM_PM_FRAME_MGMT: fw suspend sleep mode for 100TU 4853 * @IWM_PM_FRAME_ASSOC: fw suspend sleep mode for 10sec 4854 */ 4855 enum iwm_tx_pm_timeouts { 4856 IWM_PM_FRAME_NONE = 0, 4857 IWM_PM_FRAME_MGMT = 2, 4858 IWM_PM_FRAME_ASSOC = 3, 4859 }; 4860 4861 /* 4862 * TX command security control 4863 */ 4864 #define IWM_TX_CMD_SEC_WEP 0x01 4865 #define IWM_TX_CMD_SEC_CCM 0x02 4866 #define IWM_TX_CMD_SEC_TKIP 0x03 4867 #define IWM_TX_CMD_SEC_EXT 0x04 4868 #define IWM_TX_CMD_SEC_MSK 0x07 4869 #define IWM_TX_CMD_SEC_WEP_KEY_IDX_POS 6 4870 #define IWM_TX_CMD_SEC_WEP_KEY_IDX_MSK 0xc0 4871 #define IWM_TX_CMD_SEC_KEY128 0x08 4872 4873 /* TODO: how does these values are OK with only 16 bit variable??? */ 4874 /* 4875 * TX command next frame info 4876 * 4877 * bits 0:2 - security control (IWM_TX_CMD_SEC_*) 4878 * bit 3 - immediate ACK required 4879 * bit 4 - rate is taken from STA table 4880 * bit 5 - frame belongs to BA stream 4881 * bit 6 - immediate BA response expected 4882 * bit 7 - unused 4883 * bits 8:15 - Station ID 4884 * bits 16:31 - rate 4885 */ 4886 #define IWM_TX_CMD_NEXT_FRAME_ACK_MSK (0x8) 4887 #define IWM_TX_CMD_NEXT_FRAME_STA_RATE_MSK (0x10) 4888 #define IWM_TX_CMD_NEXT_FRAME_BA_MSK (0x20) 4889 #define IWM_TX_CMD_NEXT_FRAME_IMM_BA_RSP_MSK (0x40) 4890 #define IWM_TX_CMD_NEXT_FRAME_FLAGS_MSK (0xf8) 4891 #define IWM_TX_CMD_NEXT_FRAME_STA_ID_MSK (0xff00) 4892 #define IWM_TX_CMD_NEXT_FRAME_STA_ID_POS (8) 4893 #define IWM_TX_CMD_NEXT_FRAME_RATE_MSK (0xffff0000) 4894 #define IWM_TX_CMD_NEXT_FRAME_RATE_POS (16) 4895 4896 /* 4897 * TX command Frame life time in us - to be written in pm_frame_timeout 4898 */ 4899 #define IWM_TX_CMD_LIFE_TIME_INFINITE 0xFFFFFFFF 4900 #define IWM_TX_CMD_LIFE_TIME_DEFAULT 2000000 /* 2000 ms*/ 4901 #define IWM_TX_CMD_LIFE_TIME_PROBE_RESP 40000 /* 40 ms */ 4902 #define IWM_TX_CMD_LIFE_TIME_EXPIRED_FRAME 0 4903 4904 /* 4905 * TID for non QoS frames - to be written in tid_tspec 4906 */ 4907 #define IWM_MAX_TID_COUNT 8 4908 #define IWM_TID_NON_QOS 0 4909 #define IWM_TID_MGMT 15 4910 4911 /* 4912 * Limits on the retransmissions - to be written in {data,rts}_retry_limit 4913 */ 4914 #define IWM_DEFAULT_TX_RETRY 15 4915 #define IWM_MGMT_DFAULT_RETRY_LIMIT 3 4916 #define IWM_RTS_DFAULT_RETRY_LIMIT 3 4917 #define IWM_BAR_DFAULT_RETRY_LIMIT 60 4918 #define IWM_LOW_RETRY_LIMIT 7 4919 4920 /** 4921 * enum iwm_tx_offload_assist_flags_pos - set %iwm_tx_cmd offload_assist values 4922 * @TX_CMD_OFFLD_IP_HDR: offset to start of IP header (in words) 4923 * from mac header end. For normal case it is 4 words for SNAP. 4924 * note: tx_cmd, mac header and pad are not counted in the offset. 4925 * This is used to help the offload in case there is tunneling such as 4926 * IPv6 in IPv4, in such case the ip header offset should point to the 4927 * inner ip header and IPv4 checksum of the external header should be 4928 * calculated by driver. 4929 * @TX_CMD_OFFLD_L4_EN: enable TCP/UDP checksum 4930 * @TX_CMD_OFFLD_L3_EN: enable IP header checksum 4931 * @TX_CMD_OFFLD_MH_SIZE: size of the mac header in words. Includes the IV 4932 * field. Doesn't include the pad. 4933 * @TX_CMD_OFFLD_PAD: mark 2-byte pad was inserted after the mac header for 4934 * alignment 4935 * @TX_CMD_OFFLD_AMSDU: mark TX command is A-MSDU 4936 */ 4937 #define IWM_TX_CMD_OFFLD_IP_HDR (1 << 0) 4938 #define IWM_TX_CMD_OFFLD_L4_EN (1 << 6) 4939 #define IWM_TX_CMD_OFFLD_L3_EN (1 << 7) 4940 #define IWM_TX_CMD_OFFLD_MH_SIZE (1 << 8) 4941 #define IWM_TX_CMD_OFFLD_PAD (1 << 13) 4942 #define IWM_TX_CMD_OFFLD_AMSDU (1 << 14) 4943 4944 /* TODO: complete documentation for try_cnt and btkill_cnt */ 4945 /** 4946 * struct iwm_tx_cmd - TX command struct to FW 4947 * ( IWM_TX_CMD = 0x1c ) 4948 * @len: in bytes of the payload, see below for details 4949 * @offload_assist: TX offload configuration 4950 * @tx_flags: combination of IWM_TX_CMD_FLG_* 4951 * @rate_n_flags: rate for *all* Tx attempts, if IWM_TX_CMD_FLG_STA_RATE_MSK is 4952 * cleared. Combination of IWM_RATE_MCS_* 4953 * @sta_id: index of destination station in FW station table 4954 * @sec_ctl: security control, IWM_TX_CMD_SEC_* 4955 * @initial_rate_index: index into the rate table for initial TX attempt. 4956 * Applied if IWM_TX_CMD_FLG_STA_RATE_MSK is set, normally 0 for data frames. 4957 * @key: security key 4958 * @next_frame_flags: IWM_TX_CMD_SEC_* and IWM_TX_CMD_NEXT_FRAME_* 4959 * @life_time: frame life time (usecs??) 4960 * @dram_lsb_ptr: Physical address of scratch area in the command (try_cnt + 4961 * btkill_cnd + reserved), first 32 bits. "0" disables usage. 4962 * @dram_msb_ptr: upper bits of the scratch physical address 4963 * @rts_retry_limit: max attempts for RTS 4964 * @data_retry_limit: max attempts to send the data packet 4965 * @tid_spec: TID/tspec 4966 * @pm_frame_timeout: PM TX frame timeout 4967 * @driver_txop: duration od EDCA TXOP, in 32-usec units. Set this if not 4968 * specified by HCCA protocol 4969 * 4970 * The byte count (both len and next_frame_len) includes MAC header 4971 * (24/26/30/32 bytes) 4972 * + 2 bytes pad if 26/30 header size 4973 * + 8 byte IV for CCM or TKIP (not used for WEP) 4974 * + Data payload 4975 * + 8-byte MIC (not used for CCM/WEP) 4976 * It does not include post-MAC padding, i.e., 4977 * MIC (CCM) 8 bytes, ICV (WEP/TKIP/CKIP) 4 bytes, CRC 4 bytes. 4978 * Range of len: 14-2342 bytes. 4979 * 4980 * After the struct fields the MAC header is placed, plus any padding, 4981 * and then the actial payload. 4982 */ 4983 struct iwm_tx_cmd { 4984 uint16_t len; 4985 uint16_t offload_assist; 4986 uint32_t tx_flags; 4987 struct { 4988 uint8_t try_cnt; 4989 uint8_t btkill_cnt; 4990 uint16_t reserved; 4991 } scratch; /* DRAM_SCRATCH_API_U_VER_1 */ 4992 uint32_t rate_n_flags; 4993 uint8_t sta_id; 4994 uint8_t sec_ctl; 4995 uint8_t initial_rate_index; 4996 uint8_t reserved2; 4997 uint8_t key[16]; 4998 uint32_t reserved3; 4999 uint32_t life_time; 5000 uint32_t dram_lsb_ptr; 5001 uint8_t dram_msb_ptr; 5002 uint8_t rts_retry_limit; 5003 uint8_t data_retry_limit; 5004 uint8_t tid_tspec; 5005 uint16_t pm_frame_timeout; 5006 uint16_t reserved4; 5007 uint8_t payload[0]; 5008 struct ieee80211_frame hdr[0]; 5009 } __packed; /* IWM_TX_CMD_API_S_VER_6 */ 5010 5011 /* 5012 * TX response related data 5013 */ 5014 5015 /* 5016 * status that is returned by the fw after attempts to Tx 5017 * @IWM_TX_STATUS_FAIL_STA_COLOR_MISMATCH: mismatch between color of Tx cmd and 5018 * STA table 5019 * Valid only if frame_count =1 5020 */ 5021 #define IWM_TX_STATUS_MSK 0x000000ff 5022 #define IWM_TX_STATUS_SUCCESS 0x01 5023 #define IWM_TX_STATUS_DIRECT_DONE 0x02 5024 /* postpone TX */ 5025 #define IWM_TX_STATUS_POSTPONE_DELAY 0x40 5026 #define IWM_TX_STATUS_POSTPONE_FEW_BYTES 0x41 5027 #define IWM_TX_STATUS_POSTPONE_BT_PRIO 0x42 5028 #define IWM_TX_STATUS_POSTPONE_QUIET_PERIOD 0x43 5029 #define IWM_TX_STATUS_POSTPONE_CALC_TTAK 0x44 5030 /* abort TX */ 5031 #define IWM_TX_STATUS_FAIL_INTERNAL_CROSSED_RETRY 0x81 5032 #define IWM_TX_STATUS_FAIL_SHORT_LIMIT 0x82 5033 #define IWM_TX_STATUS_FAIL_LONG_LIMIT 0x83 5034 #define IWM_TX_STATUS_FAIL_UNDERRUN 0x84 5035 #define IWM_TX_STATUS_FAIL_DRAIN_FLOW 0x85 5036 #define IWM_TX_STATUS_FAIL_RFKILL_FLUSH 0x86 5037 #define IWM_TX_STATUS_FAIL_LIFE_EXPIRE 0x87 5038 #define IWM_TX_STATUS_FAIL_DEST_PS 0x88 5039 #define IWM_TX_STATUS_FAIL_HOST_ABORTED 0x89 5040 #define IWM_TX_STATUS_FAIL_BT_RETRY 0x8a 5041 #define IWM_TX_STATUS_FAIL_STA_INVALID 0x8b 5042 #define IWM_TX_STATUS_FAIL_FRAG_DROPPED 0x8c 5043 #define IWM_TX_STATUS_FAIL_TID_DISABLE 0x8d 5044 #define IWM_TX_STATUS_FAIL_FIFO_FLUSHED 0x8e 5045 #define IWM_TX_STATUS_FAIL_SMALL_CF_POLL 0x8f 5046 #define IWM_TX_STATUS_FAIL_FW_DROP 0x90 5047 #define IWM_TX_STATUS_FAIL_STA_COLOR_MISMATCH 0x91 5048 #define IWM_TX_STATUS_INTERNAL_ABORT 0x92 5049 #define IWM_TX_MODE_MSK 0x00000f00 5050 #define IWM_TX_MODE_NO_BURST 0x00000000 5051 #define IWM_TX_MODE_IN_BURST_SEQ 0x00000100 5052 #define IWM_TX_MODE_FIRST_IN_BURST 0x00000200 5053 #define IWM_TX_QUEUE_NUM_MSK 0x0001f000 5054 #define IWM_TX_NARROW_BW_MSK 0x00060000 5055 #define IWM_TX_NARROW_BW_1DIV2 0x00020000 5056 #define IWM_TX_NARROW_BW_1DIV4 0x00040000 5057 #define IWM_TX_NARROW_BW_1DIV8 0x00060000 5058 5059 /* 5060 * TX aggregation status 5061 * @IWM_AGG_TX_STATE_TRY_CNT_MSK: Retry count for 1st frame in aggregation (retries 5062 * occur if tx failed for this frame when it was a member of a previous 5063 * aggregation block). If rate scaling is used, retry count indicates the 5064 * rate table entry used for all frames in the new agg. 5065 */ 5066 #define IWM_AGG_TX_STATE_STATUS_MSK 0x0fff 5067 #define IWM_AGG_TX_STATE_TRANSMITTED 0x0000 5068 #define IWM_AGG_TX_STATE_UNDERRUN 0x0001 5069 #define IWM_AGG_TX_STATE_BT_PRIO 0x0002 5070 #define IWM_AGG_TX_STATE_FEW_BYTES 0x0004 5071 #define IWM_AGG_TX_STATE_ABORT 0x0008 5072 #define IWM_AGG_TX_STATE_LAST_SENT_TTL 0x0010 5073 #define IWM_AGG_TX_STATE_LAST_SENT_TRY_CNT 0x0020 5074 #define IWM_AGG_TX_STATE_LAST_SENT_BT_KILL 0x0040 5075 #define IWM_AGG_TX_STATE_SCD_QUERY 0x0080 5076 #define IWM_AGG_TX_STATE_TEST_BAD_CRC32 0x0100 5077 #define IWM_AGG_TX_STATE_RESPONSE 0x01ff 5078 #define IWM_AGG_TX_STATE_DUMP_TX 0x0200 5079 #define IWM_AGG_TX_STATE_DELAY_TX 0x0400 5080 #define IWM_AGG_TX_STATE_TRY_CNT_POS 12 5081 #define IWM_AGG_TX_STATE_TRY_CNT_MSK (0xf << IWM_AGG_TX_STATE_TRY_CNT_POS) 5082 5083 #define IWM_AGG_TX_STATE_LAST_SENT_MSK (IWM_AGG_TX_STATE_LAST_SENT_TTL| \ 5084 IWM_AGG_TX_STATE_LAST_SENT_TRY_CNT| \ 5085 IWM_AGG_TX_STATE_LAST_SENT_BT_KILL) 5086 5087 /* 5088 * The mask below describes a status where we are absolutely sure that the MPDU 5089 * wasn't sent. For BA/Underrun we cannot be that sure. All we know that we've 5090 * written the bytes to the TXE, but we know nothing about what the DSP did. 5091 */ 5092 #define IWM_AGG_TX_STAT_FRAME_NOT_SENT (IWM_AGG_TX_STATE_FEW_BYTES | \ 5093 IWM_AGG_TX_STATE_ABORT | \ 5094 IWM_AGG_TX_STATE_SCD_QUERY) 5095 5096 /* 5097 * IWM_REPLY_TX = 0x1c (response) 5098 * 5099 * This response may be in one of two slightly different formats, indicated 5100 * by the frame_count field: 5101 * 5102 * 1) No aggregation (frame_count == 1). This reports Tx results for a single 5103 * frame. Multiple attempts, at various bit rates, may have been made for 5104 * this frame. 5105 * 5106 * 2) Aggregation (frame_count > 1). This reports Tx results for two or more 5107 * frames that used block-acknowledge. All frames were transmitted at 5108 * same rate. Rate scaling may have been used if first frame in this new 5109 * agg block failed in previous agg block(s). 5110 * 5111 * Note that, for aggregation, ACK (block-ack) status is not delivered 5112 * here; block-ack has not been received by the time the device records 5113 * this status. 5114 * This status relates to reasons the tx might have been blocked or aborted 5115 * within the device, rather than whether it was received successfully by 5116 * the destination station. 5117 */ 5118 5119 /** 5120 * struct iwm_agg_tx_status - per packet TX aggregation status 5121 * @status: IWM_AGG_TX_STATE_* 5122 * @idx: Tx queue index of this frame 5123 * @qid: Tx queue ID of this frame 5124 */ 5125 struct iwm_agg_tx_status { 5126 uint16_t status; 5127 #if 0 5128 /* OpenBSD update - convert code to use this */ 5129 uint8_t idx; 5130 uint8_t qid; 5131 #else 5132 uint16_t sequence; 5133 #endif 5134 } __packed; 5135 5136 /* 5137 * definitions for initial rate index field 5138 * bits [3:0] initial rate index 5139 * bits [6:4] rate table color, used for the initial rate 5140 * bit-7 invalid rate indication 5141 */ 5142 #define IWM_TX_RES_INIT_RATE_INDEX_MSK 0x0f 5143 #define IWM_TX_RES_RATE_TABLE_COLOR_MSK 0x70 5144 #define IWM_TX_RES_INV_RATE_INDEX_MSK 0x80 5145 5146 #define IWM_TX_RES_GET_TID(_ra_tid) ((_ra_tid) & 0x0f) 5147 #define IWM_TX_RES_GET_RA(_ra_tid) ((_ra_tid) >> 4) 5148 5149 /** 5150 * struct iwm_tx_resp - notifies that fw is TXing a packet 5151 * ( IWM_REPLY_TX = 0x1c ) 5152 * @frame_count: 1 no aggregation, >1 aggregation 5153 * @bt_kill_count: num of times blocked by bluetooth (unused for agg) 5154 * @failure_rts: num of failures due to unsuccessful RTS 5155 * @failure_frame: num failures due to no ACK (unused for agg) 5156 * @initial_rate: for non-agg: rate of the successful Tx. For agg: rate of the 5157 * Tx of all the batch. IWM_RATE_MCS_* 5158 * @wireless_media_time: for non-agg: RTS + CTS + frame tx attempts time + ACK. 5159 * for agg: RTS + CTS + aggregation tx time + block-ack time. 5160 * in usec. 5161 * @pa_status: tx power info 5162 * @pa_integ_res_a: tx power info 5163 * @pa_integ_res_b: tx power info 5164 * @pa_integ_res_c: tx power info 5165 * @measurement_req_id: tx power info 5166 * @tfd_info: TFD information set by the FH 5167 * @seq_ctl: sequence control field from IEEE80211 frame header 5168 * @byte_cnt: byte count from the Tx cmd 5169 * @tlc_info: TLC rate info 5170 * @ra_tid: bits [3:0] = ra, bits [7:4] = tid 5171 * @frame_ctrl: frame control 5172 * @status: for non-agg: frame status IWM_TX_STATUS_* 5173 * for agg: status of 1st frame, IWM_AGG_TX_STATE_*; other frame status fields 5174 * follow this one, up to frame_count. 5175 * 5176 * After the array of statuses comes the SSN of the SCD. Look at 5177 * %iwm_get_scd_ssn for more details. 5178 */ 5179 struct iwm_tx_resp { 5180 uint8_t frame_count; 5181 uint8_t bt_kill_count; 5182 uint8_t failure_rts; 5183 uint8_t failure_frame; 5184 uint32_t initial_rate; 5185 uint16_t wireless_media_time; 5186 5187 uint8_t pa_status; 5188 uint8_t pa_integ_res_a[3]; 5189 uint8_t pa_integ_res_b[3]; 5190 uint8_t pa_integ_res_c[3]; 5191 uint16_t measurement_req_id; 5192 uint16_t reserved; 5193 5194 uint32_t tfd_info; 5195 uint16_t seq_ctl; 5196 uint16_t byte_cnt; 5197 uint8_t tlc_info; 5198 uint8_t ra_tid; 5199 uint16_t frame_ctrl; 5200 5201 struct iwm_agg_tx_status status; 5202 } __packed; /* IWM_TX_RSP_API_S_VER_3 */ 5203 5204 /** 5205 * struct iwm_ba_notif - notifies about reception of BA 5206 * ( IWM_BA_NOTIF = 0xc5 ) 5207 * @sta_addr: MAC address 5208 * @sta_id: Index of recipient (BA-sending) station in fw's station table 5209 * @tid: tid of the session 5210 * @seq_ctl: sequence control field from IEEE80211 frame header (the first 5211 * bit in @bitmap corresponds to the sequence number stored here) 5212 * @bitmap: the bitmap of the BA notification as seen in the air 5213 * @scd_flow: the tx queue this BA relates to 5214 * @scd_ssn: the index of the last contiguously sent packet 5215 * @txed: number of Txed frames in this batch 5216 * @txed_2_done: number of Acked frames in this batch 5217 * @reduced_txp: power reduced according to TPC. This is the actual value and 5218 * not a copy from the LQ command. Thus, if not the first rate was used 5219 * for Tx-ing then this value will be set to 0 by FW. 5220 * @reserved1: reserved 5221 */ 5222 struct iwm_ba_notif { 5223 uint8_t sta_addr[ETHER_ADDR_LEN]; 5224 uint16_t reserved; 5225 5226 uint8_t sta_id; 5227 uint8_t tid; 5228 uint16_t seq_ctl; 5229 uint64_t bitmap; 5230 uint16_t scd_flow; 5231 uint16_t scd_ssn; 5232 uint8_t txed; 5233 uint8_t txed_2_done; 5234 uint8_t reduced_txp; 5235 uint8_t reserved1; 5236 } __packed; 5237 5238 /* 5239 * struct iwm_mac_beacon_cmd - beacon template command 5240 * @tx: the tx commands associated with the beacon frame 5241 * @template_id: currently equal to the mac context id of the corresponding 5242 * mac. 5243 * @tim_idx: the offset of the tim IE in the beacon 5244 * @tim_size: the length of the tim IE 5245 * @frame: the template of the beacon frame 5246 */ 5247 struct iwm_mac_beacon_cmd { 5248 struct iwm_tx_cmd tx; 5249 uint32_t template_id; 5250 uint32_t tim_idx; 5251 uint32_t tim_size; 5252 struct ieee80211_frame frame[0]; 5253 } __packed; 5254 5255 struct iwm_beacon_notif { 5256 struct iwm_tx_resp beacon_notify_hdr; 5257 uint64_t tsf; 5258 uint32_t ibss_mgr_status; 5259 } __packed; 5260 5261 /** 5262 * dump (flush) control flags 5263 * @IWM_DUMP_TX_FIFO_FLUSH: Dump MSDUs until the FIFO is empty 5264 * and the TFD queues are empty. 5265 */ 5266 #define IWM_DUMP_TX_FIFO_FLUSH (1 << 1) 5267 5268 /** 5269 * struct iwm_tx_path_flush_cmd -- queue/FIFO flush command 5270 * @queues_ctl: bitmap of queues to flush 5271 * @flush_ctl: control flags 5272 * @reserved: reserved 5273 */ 5274 struct iwm_tx_path_flush_cmd_v1 { 5275 uint32_t queues_ctl; 5276 uint16_t flush_ctl; 5277 uint16_t reserved; 5278 } __packed; /* IWM_TX_PATH_FLUSH_CMD_API_S_VER_1 */ 5279 5280 /** 5281 * struct iwl_tx_path_flush_cmd -- queue/FIFO flush command 5282 * @sta_id: station ID to flush 5283 * @tid_mask: TID mask to flush 5284 * @reserved: reserved 5285 */ 5286 struct iwm_tx_path_flush_cmd { 5287 uint32_t sta_id; 5288 uint16_t tid_mask; 5289 uint16_t reserved; 5290 } __packed; /* TX_PATH_FLUSH_CMD_API_S_VER_2 */ 5291 5292 /** 5293 * iwm_get_scd_ssn - returns the SSN of the SCD 5294 * @tx_resp: the Tx response from the fw (agg or non-agg) 5295 * 5296 * When the fw sends an AMPDU, it fetches the MPDUs one after the other. Since 5297 * it can't know that everything will go well until the end of the AMPDU, it 5298 * can't know in advance the number of MPDUs that will be sent in the current 5299 * batch. This is why it writes the agg Tx response while it fetches the MPDUs. 5300 * Hence, it can't know in advance what the SSN of the SCD will be at the end 5301 * of the batch. This is why the SSN of the SCD is written at the end of the 5302 * whole struct at a variable offset. This function knows how to cope with the 5303 * variable offset and returns the SSN of the SCD. 5304 */ 5305 static inline uint32_t iwm_get_scd_ssn(struct iwm_tx_resp *tx_resp) 5306 { 5307 return le32_to_cpup((uint32_t *)&tx_resp->status + 5308 tx_resp->frame_count) & 0xfff; 5309 } 5310 5311 /* 5312 * END mvm/fw-api-tx.h 5313 */ 5314 5315 /* 5316 * BEGIN mvm/fw-api-scan.h 5317 */ 5318 5319 /** 5320 * struct iwm_scd_txq_cfg_cmd - New txq hw scheduler config command 5321 * @token: 5322 * @sta_id: station id 5323 * @tid: 5324 * @scd_queue: scheduler queue to confiug 5325 * @enable: 1 queue enable, 0 queue disable 5326 * @aggregate: 1 aggregated queue, 0 otherwise 5327 * @tx_fifo: %enum iwm_tx_fifo 5328 * @window: BA window size 5329 * @ssn: SSN for the BA agreement 5330 */ 5331 struct iwm_scd_txq_cfg_cmd { 5332 uint8_t token; 5333 uint8_t sta_id; 5334 uint8_t tid; 5335 uint8_t scd_queue; 5336 uint8_t enable; 5337 uint8_t aggregate; 5338 uint8_t tx_fifo; 5339 uint8_t window; 5340 uint16_t ssn; 5341 uint16_t reserved; 5342 } __packed; /* SCD_QUEUE_CFG_CMD_API_S_VER_1 */ 5343 5344 /** 5345 * struct iwm_scd_txq_cfg_rsp 5346 * @token: taken from the command 5347 * @sta_id: station id from the command 5348 * @tid: tid from the command 5349 * @scd_queue: scd_queue from the command 5350 */ 5351 struct iwm_scd_txq_cfg_rsp { 5352 uint8_t token; 5353 uint8_t sta_id; 5354 uint8_t tid; 5355 uint8_t scd_queue; 5356 } __packed; /* SCD_QUEUE_CFG_RSP_API_S_VER_1 */ 5357 5358 5359 /* Scan Commands, Responses, Notifications */ 5360 5361 /* Masks for iwm_scan_channel.type flags */ 5362 #define IWM_SCAN_CHANNEL_TYPE_ACTIVE (1 << 0) 5363 #define IWM_SCAN_CHANNEL_NSSIDS(x) (((1 << (x)) - 1) << 1) 5364 5365 /* Max number of IEs for direct SSID scans in a command */ 5366 #define IWM_PROBE_OPTION_MAX 20 5367 5368 /** 5369 * struct iwm_ssid_ie - directed scan network information element 5370 * 5371 * Up to 20 of these may appear in IWM_REPLY_SCAN_CMD, 5372 * selected by "type" bit field in struct iwm_scan_channel; 5373 * each channel may select different ssids from among the 20 entries. 5374 * SSID IEs get transmitted in reverse order of entry. 5375 */ 5376 struct iwm_ssid_ie { 5377 uint8_t id; 5378 uint8_t len; 5379 uint8_t ssid[IEEE80211_NWID_LEN]; 5380 } __packed; /* IWM_SCAN_DIRECT_SSID_IE_API_S_VER_1 */ 5381 5382 /* scan offload */ 5383 #define IWM_SCAN_MAX_BLACKLIST_LEN 64 5384 #define IWM_SCAN_SHORT_BLACKLIST_LEN 16 5385 #define IWM_SCAN_MAX_PROFILES 11 5386 #define IWM_SCAN_OFFLOAD_PROBE_REQ_SIZE 512 5387 5388 /* Default watchdog (in MS) for scheduled scan iteration */ 5389 #define IWM_SCHED_SCAN_WATCHDOG cpu_to_le16(15000) 5390 5391 #define IWM_GOOD_CRC_TH_DEFAULT cpu_to_le16(1) 5392 #define IWM_CAN_ABORT_STATUS 1 5393 5394 #define IWM_FULL_SCAN_MULTIPLIER 5 5395 #define IWM_FAST_SCHED_SCAN_ITERATIONS 3 5396 #define IWM_MAX_SCHED_SCAN_PLANS 2 5397 5398 /** 5399 * iwm_scan_schedule_lmac - schedule of scan offload 5400 * @delay: delay between iterations, in seconds. 5401 * @iterations: num of scan iterations 5402 * @full_scan_mul: number of partial scans before each full scan 5403 */ 5404 struct iwm_scan_schedule_lmac { 5405 uint16_t delay; 5406 uint8_t iterations; 5407 uint8_t full_scan_mul; 5408 } __packed; /* SCAN_SCHEDULE_API_S */ 5409 5410 /** 5411 * iwm_scan_req_tx_cmd - SCAN_REQ_TX_CMD_API_S 5412 * @tx_flags: combination of TX_CMD_FLG_* 5413 * @rate_n_flags: rate for *all* Tx attempts, if TX_CMD_FLG_STA_RATE_MSK is 5414 * cleared. Combination of RATE_MCS_* 5415 * @sta_id: index of destination station in FW station table 5416 * @reserved: for alignment and future use 5417 */ 5418 struct iwm_scan_req_tx_cmd { 5419 uint32_t tx_flags; 5420 uint32_t rate_n_flags; 5421 uint8_t sta_id; 5422 uint8_t reserved[3]; 5423 } __packed; 5424 5425 #define IWM_UNIFIED_SCAN_CHANNEL_FULL (1 << 27) 5426 #define IWM_UNIFIED_SCAN_CHANNEL_PARTIAL (1 << 28) 5427 5428 /** 5429 * iwm_scan_channel_cfg_lmac - SCAN_CHANNEL_CFG_S_VER2 5430 * @flags: bits 1-20: directed scan to i'th ssid 5431 * other bits &enum iwm_scan_channel_flags_lmac 5432 * @channel_number: channel number 1-13 etc 5433 * @iter_count: scan iteration on this channel 5434 * @iter_interval: interval in seconds between iterations on one channel 5435 */ 5436 struct iwm_scan_channel_cfg_lmac { 5437 uint32_t flags; 5438 uint16_t channel_num; 5439 uint16_t iter_count; 5440 uint32_t iter_interval; 5441 } __packed; 5442 5443 /* 5444 * iwm_scan_probe_segment - PROBE_SEGMENT_API_S_VER_1 5445 * @offset: offset in the data block 5446 * @len: length of the segment 5447 */ 5448 struct iwm_scan_probe_segment { 5449 uint16_t offset; 5450 uint16_t len; 5451 } __packed; 5452 5453 /* iwm_scan_probe_req - PROBE_REQUEST_FRAME_API_S_VER_2 5454 * @mac_header: first (and common) part of the probe 5455 * @band_data: band specific data 5456 * @common_data: last (and common) part of the probe 5457 * @buf: raw data block 5458 */ 5459 struct iwm_scan_probe_req_v1 { 5460 struct iwm_scan_probe_segment mac_header; 5461 struct iwm_scan_probe_segment band_data[2]; 5462 struct iwm_scan_probe_segment common_data; 5463 uint8_t buf[IWM_SCAN_OFFLOAD_PROBE_REQ_SIZE]; 5464 } __packed; 5465 5466 /* iwl_scan_probe_req - PROBE_REQUEST_FRAME_API_S_VER_v2 5467 * @mac_header: first (and common) part of the probe 5468 * @band_data: band specific data 5469 * @common_data: last (and common) part of the probe 5470 * @buf: raw data block 5471 */ 5472 struct iwm_scan_probe_req { 5473 struct iwm_scan_probe_segment mac_header; 5474 struct iwm_scan_probe_segment band_data[3]; 5475 struct iwm_scan_probe_segment common_data; 5476 uint8_t buf[IWM_SCAN_OFFLOAD_PROBE_REQ_SIZE]; 5477 } __packed; 5478 5479 5480 #define IWM_SCAN_CHANNEL_FLAG_EBS (1 << 0) 5481 #define IWM_SCAN_CHANNEL_FLAG_EBS_ACCURATE (1 << 1) 5482 #define IWM_SCAN_CHANNEL_FLAG_CACHE_ADD (1 << 2) 5483 5484 /* iwm_scan_channel_opt - CHANNEL_OPTIMIZATION_API_S 5485 * @flags: enum iwm_scan_channel_flags 5486 * @non_ebs_ratio: defines the ratio of number of scan iterations where EBS is 5487 * involved. 5488 * 1 - EBS is disabled. 5489 * 2 - every second scan will be full scan(and so on). 5490 */ 5491 struct iwm_scan_channel_opt { 5492 uint16_t flags; 5493 uint16_t non_ebs_ratio; 5494 } __packed; 5495 5496 /** 5497 * LMAC scan flags 5498 * @IWM_LMAC_SCAN_FLAG_PASS_ALL: pass all beacons and probe responses 5499 * without filtering. 5500 * @IWM_LMAC_SCAN_FLAG_PASSIVE: force passive scan on all channels 5501 * @IWM_LMAC_SCAN_FLAG_PRE_CONNECTION: single channel scan 5502 * @IWM_LMAC_SCAN_FLAG_ITER_COMPLETE: send iteration complete notification 5503 * @IWM_LMAC_SCAN_FLAG_MULTIPLE_SSIDS multiple SSID matching 5504 * @IWM_LMAC_SCAN_FLAG_FRAGMENTED: all passive scans will be fragmented 5505 * @IWM_LMAC_SCAN_FLAGS_RRM_ENABLED: insert WFA vendor-specific TPC report 5506 * and DS parameter set IEs into probe requests. 5507 * @IWM_LMAC_SCAN_FLAG_EXTENDED_DWELL: use extended dwell time on channels 5508 * 1, 6 and 11. 5509 * @IWM_LMAC_SCAN_FLAG_MATCH: Send match found notification on matches 5510 */ 5511 #define IWM_LMAC_SCAN_FLAG_PASS_ALL (1 << 0) 5512 #define IWM_LMAC_SCAN_FLAG_PASSIVE (1 << 1) 5513 #define IWM_LMAC_SCAN_FLAG_PRE_CONNECTION (1 << 2) 5514 #define IWM_LMAC_SCAN_FLAG_ITER_COMPLETE (1 << 3) 5515 #define IWM_LMAC_SCAN_FLAG_MULTIPLE_SSIDS (1 << 4) 5516 #define IWM_LMAC_SCAN_FLAG_FRAGMENTED (1 << 5) 5517 #define IWM_LMAC_SCAN_FLAGS_RRM_ENABLED (1 << 6) 5518 #define IWM_LMAC_SCAN_FLAG_EXTENDED_DWELL (1 << 7) 5519 #define IWM_LMAC_SCAN_FLAG_MATCH (1 << 9) 5520 5521 #define IWM_SCAN_PRIORITY_LOW 0 5522 #define IWM_SCAN_PRIORITY_MEDIUM 1 5523 #define IWM_SCAN_PRIORITY_HIGH 2 5524 5525 /** 5526 * iwm_scan_req_lmac - SCAN_REQUEST_CMD_API_S_VER_1 5527 * @reserved1: for alignment and future use 5528 * @channel_num: num of channels to scan 5529 * @active-dwell: dwell time for active channels 5530 * @passive-dwell: dwell time for passive channels 5531 * @fragmented-dwell: dwell time for fragmented passive scan 5532 * @extended_dwell: dwell time for channels 1, 6 and 11 (in certain cases) 5533 * @reserved2: for alignment and future use 5534 * @rx_chain_selct: PHY_RX_CHAIN_* flags 5535 * @scan_flags: &enum iwm_lmac_scan_flags 5536 * @max_out_time: max time (in TU) to be out of associated channel 5537 * @suspend_time: pause scan this long (TUs) when returning to service channel 5538 * @flags: RXON flags 5539 * @filter_flags: RXON filter 5540 * @tx_cmd: tx command for active scan; for 2GHz and for 5GHz 5541 * @direct_scan: list of SSIDs for directed active scan 5542 * @scan_prio: enum iwm_scan_priority 5543 * @iter_num: number of scan iterations 5544 * @delay: delay in seconds before first iteration 5545 * @schedule: two scheduling plans. The first one is finite, the second one can 5546 * be infinite. 5547 * @channel_opt: channel optimization options, for full and partial scan 5548 * @data: channel configuration and probe request packet. 5549 */ 5550 struct iwm_scan_req_lmac { 5551 /* SCAN_REQUEST_FIXED_PART_API_S_VER_7 */ 5552 uint32_t reserved1; 5553 uint8_t n_channels; 5554 uint8_t active_dwell; 5555 uint8_t passive_dwell; 5556 uint8_t fragmented_dwell; 5557 uint8_t extended_dwell; 5558 uint8_t reserved2; 5559 uint16_t rx_chain_select; 5560 uint32_t scan_flags; 5561 uint32_t max_out_time; 5562 uint32_t suspend_time; 5563 /* RX_ON_FLAGS_API_S_VER_1 */ 5564 uint32_t flags; 5565 uint32_t filter_flags; 5566 struct iwm_scan_req_tx_cmd tx_cmd[2]; 5567 struct iwm_ssid_ie direct_scan[IWM_PROBE_OPTION_MAX]; 5568 uint32_t scan_prio; 5569 /* SCAN_REQ_PERIODIC_PARAMS_API_S */ 5570 uint32_t iter_num; 5571 uint32_t delay; 5572 struct iwm_scan_schedule_lmac schedule[IWM_MAX_SCHED_SCAN_PLANS]; 5573 struct iwm_scan_channel_opt channel_opt[2]; 5574 uint8_t data[]; 5575 } __packed; 5576 5577 /** 5578 * iwm_scan_offload_complete - PERIODIC_SCAN_COMPLETE_NTF_API_S_VER_2 5579 * @last_schedule_line: last schedule line executed (fast or regular) 5580 * @last_schedule_iteration: last scan iteration executed before scan abort 5581 * @status: enum iwm_scan_offload_complete_status 5582 * @ebs_status: EBS success status &enum iwm_scan_ebs_status 5583 * @time_after_last_iter; time in seconds elapsed after last iteration 5584 */ 5585 struct iwm_periodic_scan_complete { 5586 uint8_t last_schedule_line; 5587 uint8_t last_schedule_iteration; 5588 uint8_t status; 5589 uint8_t ebs_status; 5590 uint32_t time_after_last_iter; 5591 uint32_t reserved; 5592 } __packed; 5593 5594 /** 5595 * struct iwm_scan_results_notif - scan results for one channel - 5596 * SCAN_RESULT_NTF_API_S_VER_3 5597 * @channel: which channel the results are from 5598 * @band: 0 for 5.2 GHz, 1 for 2.4 GHz 5599 * @probe_status: IWM_SCAN_PROBE_STATUS_*, indicates success of probe request 5600 * @num_probe_not_sent: # of request that weren't sent due to not enough time 5601 * @duration: duration spent in channel, in usecs 5602 */ 5603 struct iwm_scan_results_notif { 5604 uint8_t channel; 5605 uint8_t band; 5606 uint8_t probe_status; 5607 uint8_t num_probe_not_sent; 5608 uint32_t duration; 5609 } __packed; 5610 5611 #define IWM_SCAN_CLIENT_SCHED_SCAN (1 << 0) 5612 #define IWM_SCAN_CLIENT_NETDETECT (1 << 1) 5613 #define IWM_SCAN_CLIENT_ASSET_TRACKING (1 << 2) 5614 5615 /** 5616 * iwm_scan_offload_blacklist - IWM_SCAN_OFFLOAD_BLACKLIST_S 5617 * @ssid: MAC address to filter out 5618 * @reported_rssi: AP rssi reported to the host 5619 * @client_bitmap: clients ignore this entry - enum scan_framework_client 5620 */ 5621 struct iwm_scan_offload_blacklist { 5622 uint8_t ssid[ETHER_ADDR_LEN]; 5623 uint8_t reported_rssi; 5624 uint8_t client_bitmap; 5625 } __packed; 5626 5627 #define IWM_NETWORK_TYPE_BSS 1 5628 #define IWM_NETWORK_TYPE_IBSS 2 5629 #define IWM_NETWORK_TYPE_ANY 3 5630 5631 #define IWM_SCAN_OFFLOAD_SELECT_2_4 0x4 5632 #define IWM_SCAN_OFFLOAD_SELECT_5_2 0x8 5633 #define IWM_SCAN_OFFLOAD_SELECT_ANY 0xc 5634 5635 /** 5636 * iwm_scan_offload_profile - IWM_SCAN_OFFLOAD_PROFILE_S 5637 * @ssid_index: index to ssid list in fixed part 5638 * @unicast_cipher: encryption olgorithm to match - bitmap 5639 * @aut_alg: authentication olgorithm to match - bitmap 5640 * @network_type: enum iwm_scan_offload_network_type 5641 * @band_selection: enum iwm_scan_offload_band_selection 5642 * @client_bitmap: clients waiting for match - enum scan_framework_client 5643 */ 5644 struct iwm_scan_offload_profile { 5645 uint8_t ssid_index; 5646 uint8_t unicast_cipher; 5647 uint8_t auth_alg; 5648 uint8_t network_type; 5649 uint8_t band_selection; 5650 uint8_t client_bitmap; 5651 uint8_t reserved[2]; 5652 } __packed; 5653 5654 /** 5655 * iwm_scan_offload_profile_cfg - IWM_SCAN_OFFLOAD_PROFILES_CFG_API_S_VER_1 5656 * @blaclist: AP list to filter off from scan results 5657 * @profiles: profiles to search for match 5658 * @blacklist_len: length of blacklist 5659 * @num_profiles: num of profiles in the list 5660 * @match_notify: clients waiting for match found notification 5661 * @pass_match: clients waiting for the results 5662 * @active_clients: active clients bitmap - enum scan_framework_client 5663 * @any_beacon_notify: clients waiting for match notification without match 5664 */ 5665 struct iwm_scan_offload_profile_cfg { 5666 struct iwm_scan_offload_profile profiles[IWM_SCAN_MAX_PROFILES]; 5667 uint8_t blacklist_len; 5668 uint8_t num_profiles; 5669 uint8_t match_notify; 5670 uint8_t pass_match; 5671 uint8_t active_clients; 5672 uint8_t any_beacon_notify; 5673 uint8_t reserved[2]; 5674 } __packed; 5675 5676 enum iwm_scan_offload_complete_status { 5677 IWM_SCAN_OFFLOAD_COMPLETED = 1, 5678 IWM_SCAN_OFFLOAD_ABORTED = 2, 5679 }; 5680 5681 enum iwm_scan_ebs_status { 5682 IWM_SCAN_EBS_SUCCESS, 5683 IWM_SCAN_EBS_FAILED, 5684 IWM_SCAN_EBS_CHAN_NOT_FOUND, 5685 IWM_SCAN_EBS_INACTIVE, 5686 }; 5687 5688 /** 5689 * struct iwm_lmac_scan_complete_notif - notifies end of scanning (all channels) 5690 * SCAN_COMPLETE_NTF_API_S_VER_3 5691 * @scanned_channels: number of channels scanned (and number of valid results) 5692 * @status: one of SCAN_COMP_STATUS_* 5693 * @bt_status: BT on/off status 5694 * @last_channel: last channel that was scanned 5695 * @tsf_low: TSF timer (lower half) in usecs 5696 * @tsf_high: TSF timer (higher half) in usecs 5697 * @results: an array of scan results, only "scanned_channels" of them are valid 5698 */ 5699 struct iwm_lmac_scan_complete_notif { 5700 uint8_t scanned_channels; 5701 uint8_t status; 5702 uint8_t bt_status; 5703 uint8_t last_channel; 5704 uint32_t tsf_low; 5705 uint32_t tsf_high; 5706 struct iwm_scan_results_notif results[]; 5707 } __packed; 5708 5709 5710 /* UMAC Scan API */ 5711 5712 /* The maximum of either of these cannot exceed 8, because we use an 5713 * 8-bit mask (see IWM_SCAN_MASK). 5714 */ 5715 #define IWM_MAX_UMAC_SCANS 8 5716 #define IWM_MAX_LMAC_SCANS 1 5717 5718 #define IWM_SCAN_CONFIG_FLAG_ACTIVATE (1 << 0) 5719 #define IWM_SCAN_CONFIG_FLAG_DEACTIVATE (1 << 1) 5720 #define IWM_SCAN_CONFIG_FLAG_FORBID_CHUB_REQS (1 << 2) 5721 #define IWM_SCAN_CONFIG_FLAG_ALLOW_CHUB_REQS (1 << 3) 5722 #define IWM_SCAN_CONFIG_FLAG_SET_TX_CHAINS (1 << 8) 5723 #define IWM_SCAN_CONFIG_FLAG_SET_RX_CHAINS (1 << 9) 5724 #define IWM_SCAN_CONFIG_FLAG_SET_AUX_STA_ID (1 << 10) 5725 #define IWM_SCAN_CONFIG_FLAG_SET_ALL_TIMES (1 << 11) 5726 #define IWM_SCAN_CONFIG_FLAG_SET_EFFECTIVE_TIMES (1 << 12) 5727 #define IWM_SCAN_CONFIG_FLAG_SET_CHANNEL_FLAGS (1 << 13) 5728 #define IWM_SCAN_CONFIG_FLAG_SET_LEGACY_RATES (1 << 14) 5729 #define IWM_SCAN_CONFIG_FLAG_SET_MAC_ADDR (1 << 15) 5730 #define IWM_SCAN_CONFIG_FLAG_SET_FRAGMENTED (1 << 16) 5731 #define IWM_SCAN_CONFIG_FLAG_CLEAR_FRAGMENTED (1 << 17) 5732 #define IWM_SCAN_CONFIG_FLAG_SET_CAM_MODE (1 << 18) 5733 #define IWM_SCAN_CONFIG_FLAG_CLEAR_CAM_MODE (1 << 19) 5734 #define IWM_SCAN_CONFIG_FLAG_SET_PROMISC_MODE (1 << 20) 5735 #define IWM_SCAN_CONFIG_FLAG_CLEAR_PROMISC_MODE (1 << 21) 5736 5737 /* Bits 26-31 are for num of channels in channel_array */ 5738 #define IWM_SCAN_CONFIG_N_CHANNELS(n) ((n) << 26) 5739 5740 /* OFDM basic rates */ 5741 #define IWM_SCAN_CONFIG_RATE_6M (1 << 0) 5742 #define IWM_SCAN_CONFIG_RATE_9M (1 << 1) 5743 #define IWM_SCAN_CONFIG_RATE_12M (1 << 2) 5744 #define IWM_SCAN_CONFIG_RATE_18M (1 << 3) 5745 #define IWM_SCAN_CONFIG_RATE_24M (1 << 4) 5746 #define IWM_SCAN_CONFIG_RATE_36M (1 << 5) 5747 #define IWM_SCAN_CONFIG_RATE_48M (1 << 6) 5748 #define IWM_SCAN_CONFIG_RATE_54M (1 << 7) 5749 /* CCK basic rates */ 5750 #define IWM_SCAN_CONFIG_RATE_1M (1 << 8) 5751 #define IWM_SCAN_CONFIG_RATE_2M (1 << 9) 5752 #define IWM_SCAN_CONFIG_RATE_5M (1 << 10) 5753 #define IWM_SCAN_CONFIG_RATE_11M (1 << 11) 5754 5755 /* Bits 16-27 are for supported rates */ 5756 #define IWM_SCAN_CONFIG_SUPPORTED_RATE(rate) ((rate) << 16) 5757 5758 #define IWM_CHANNEL_FLAG_EBS (1 << 0) 5759 #define IWM_CHANNEL_FLAG_ACCURATE_EBS (1 << 1) 5760 #define IWM_CHANNEL_FLAG_EBS_ADD (1 << 2) 5761 #define IWM_CHANNEL_FLAG_PRE_SCAN_PASSIVE2ACTIVE (1 << 3) 5762 5763 /** 5764 * struct iwm_scan_config 5765 * @flags: enum scan_config_flags 5766 * @tx_chains: valid_tx antenna - ANT_* definitions 5767 * @rx_chains: valid_rx antenna - ANT_* definitions 5768 * @legacy_rates: default legacy rates - enum scan_config_rates 5769 * @out_of_channel_time: default max out of serving channel time 5770 * @suspend_time: default max suspend time 5771 * @dwell_active: default dwell time for active scan 5772 * @dwell_passive: default dwell time for passive scan 5773 * @dwell_fragmented: default dwell time for fragmented scan 5774 * @dwell_extended: default dwell time for channels 1, 6 and 11 5775 * @mac_addr: default mac address to be used in probes 5776 * @bcast_sta_id: the index of the station in the fw 5777 * @channel_flags: default channel flags - enum iwm_channel_flags 5778 * scan_config_channel_flag 5779 * @channel_array: default supported channels 5780 */ 5781 struct iwm_scan_config { 5782 uint32_t flags; 5783 uint32_t tx_chains; 5784 uint32_t rx_chains; 5785 uint32_t legacy_rates; 5786 uint32_t out_of_channel_time; 5787 uint32_t suspend_time; 5788 uint8_t dwell_active; 5789 uint8_t dwell_passive; 5790 uint8_t dwell_fragmented; 5791 uint8_t dwell_extended; 5792 uint8_t mac_addr[ETHER_ADDR_LEN]; 5793 uint8_t bcast_sta_id; 5794 uint8_t channel_flags; 5795 uint8_t channel_array[]; 5796 } __packed; /* SCAN_CONFIG_DB_CMD_API_S */ 5797 5798 /** 5799 * iwm_umac_scan_flags 5800 *@IWM_UMAC_SCAN_FLAG_PREEMPTIVE: scan process triggered by this scan request 5801 * can be preempted by other scan requests with higher priority. 5802 * The low priority scan will be resumed when the higher proirity scan is 5803 * completed. 5804 *@IWM_UMAC_SCAN_FLAG_START_NOTIF: notification will be sent to the driver 5805 * when scan starts. 5806 */ 5807 #define IWM_UMAC_SCAN_FLAG_PREEMPTIVE (1 << 0) 5808 #define IWM_UMAC_SCAN_FLAG_START_NOTIF (1 << 1) 5809 5810 #define IWM_UMAC_SCAN_UID_TYPE_OFFSET 0 5811 #define IWM_UMAC_SCAN_UID_SEQ_OFFSET 8 5812 5813 #define IWM_UMAC_SCAN_GEN_FLAGS_PERIODIC (1 << 0) 5814 #define IWM_UMAC_SCAN_GEN_FLAGS_OVER_BT (1 << 1) 5815 #define IWM_UMAC_SCAN_GEN_FLAGS_PASS_ALL (1 << 2) 5816 #define IWM_UMAC_SCAN_GEN_FLAGS_PASSIVE (1 << 3) 5817 #define IWM_UMAC_SCAN_GEN_FLAGS_PRE_CONNECT (1 << 4) 5818 #define IWM_UMAC_SCAN_GEN_FLAGS_ITER_COMPLETE (1 << 5) 5819 #define IWM_UMAC_SCAN_GEN_FLAGS_MULTIPLE_SSID (1 << 6) 5820 #define IWM_UMAC_SCAN_GEN_FLAGS_FRAGMENTED (1 << 7) 5821 #define IWM_UMAC_SCAN_GEN_FLAGS_RRM_ENABLED (1 << 8) 5822 #define IWM_UMAC_SCAN_GEN_FLAGS_MATCH (1 << 9) 5823 #define IWM_UMAC_SCAN_GEN_FLAGS_EXTENDED_DWELL (1 << 10) 5824 /* Extended dwell is obselete when adaptive dwell is used, making this 5825 * bit reusable. Hence, probe request defer is used only when adaptive 5826 * dwell is supported. */ 5827 #define IWM_UMAC_SCAN_GEN_FLAGS_PROB_REQ_DEFER_SUPP (1 << 10) 5828 #define IWM_UMAC_SCAN_GEN_FLAGS_LMAC2_FRAGMENTED (1 << 11) 5829 #define IWM_UMAC_SCAN_GEN_FLAGS_ADAPTIVE_DWELL (1 << 13) 5830 #define IWM_UMAC_SCAN_GEN_FLAGS_MAX_CHNL_TIME (1 << 14) 5831 #define IWM_UMAC_SCAN_GEN_FLAGS_PROB_REQ_HIGH_TX_RATE (1 << 15) 5832 5833 /** 5834 * UMAC scan general flags #2 5835 * @IWM_UMAC_SCAN_GEN_FLAGS2_NOTIF_PER_CHNL: Whether to send a complete 5836 * notification per channel or not. 5837 * @IWM_UMAC_SCAN_GEN_FLAGS2_ALLOW_CHNL_REORDER: Whether to allow channel 5838 * reorder optimization or not. 5839 */ 5840 #define IWM_UMAC_SCAN_GEN_FLAGS2_NOTIF_PER_CHNL (1 << 0) 5841 #define IWM_UMAC_SCAN_GEN_FLAGS2_ALLOW_CHNL_REORDER (1 << 1) 5842 5843 /** 5844 * struct iwm_scan_channel_cfg_umac 5845 * @flags: bitmap - 0-19: directed scan to i'th ssid. 5846 * @channel_num: channel number 1-13 etc. 5847 * @iter_count: repetition count for the channel. 5848 * @iter_interval: interval between two scan iterations on one channel. 5849 */ 5850 struct iwm_scan_channel_cfg_umac { 5851 uint32_t flags; 5852 #define IWM_SCAN_CHANNEL_UMAC_NSSIDS(x) ((1 << (x)) - 1) 5853 uint8_t channel_num; 5854 uint8_t iter_count; 5855 uint16_t iter_interval; 5856 } __packed; /* SCAN_CHANNEL_CFG_S_VER1 */ 5857 5858 /** 5859 * struct iwm_scan_umac_schedule 5860 * @interval: interval in seconds between scan iterations 5861 * @iter_count: num of scan iterations for schedule plan, 0xff for infinite loop 5862 * @reserved: for alignment and future use 5863 */ 5864 struct iwm_scan_umac_schedule { 5865 uint16_t interval; 5866 uint8_t iter_count; 5867 uint8_t reserved; 5868 } __packed; /* SCAN_SCHED_PARAM_API_S_VER_1 */ 5869 5870 /** 5871 * struct iwm_scan_req_umac_tail - the rest of the UMAC scan request command 5872 * parameters following channels configuration array. 5873 * @schedule: two scheduling plans. 5874 * @delay: delay in TUs before starting the first scan iteration 5875 * @reserved: for future use and alignment 5876 * @preq: probe request with IEs blocks 5877 * @direct_scan: list of SSIDs for directed active scan 5878 */ 5879 struct iwm_scan_req_umac_tail_v1 { 5880 /* SCAN_PERIODIC_PARAMS_API_S_VER_1 */ 5881 struct iwm_scan_umac_schedule schedule[IWM_MAX_SCHED_SCAN_PLANS]; 5882 uint16_t delay; 5883 uint16_t reserved; 5884 /* SCAN_PROBE_PARAMS_API_S_VER_1 */ 5885 struct iwm_scan_probe_req_v1 preq; 5886 struct iwm_ssid_ie direct_scan[IWM_PROBE_OPTION_MAX]; 5887 } __packed; 5888 5889 /** 5890 * struct iwm_scan_req_umac_tail - the rest of the UMAC scan request command 5891 * parameters following channels configuration array. 5892 * @schedule: two scheduling plans. 5893 * @delay: delay in TUs before starting the first scan iteration 5894 * @reserved: for future use and alignment 5895 * @preq: probe request with IEs blocks 5896 * @direct_scan: list of SSIDs for directed active scan 5897 */ 5898 struct iwm_scan_req_umac_tail_v2 { 5899 /* SCAN_PERIODIC_PARAMS_API_S_VER_1 */ 5900 struct iwm_scan_umac_schedule schedule[IWM_MAX_SCHED_SCAN_PLANS]; 5901 uint16_t delay; 5902 uint16_t reserved; 5903 /* SCAN_PROBE_PARAMS_API_S_VER_2 */ 5904 struct iwm_scan_probe_req preq; 5905 struct iwm_ssid_ie direct_scan[IWM_PROBE_OPTION_MAX]; 5906 } __packed; 5907 5908 /** 5909 * struct iwm_scan_umac_chan_param 5910 * @flags: channel flags &enum iwl_scan_channel_flags 5911 * @count: num of channels in scan request 5912 * @reserved: for future use and alignment 5913 */ 5914 struct iwm_scan_umac_chan_param { 5915 uint8_t flags; 5916 uint8_t count; 5917 uint16_t reserved; 5918 } __packed; /* SCAN_CHANNEL_PARAMS_API_S_VER_1 */ 5919 5920 #define IWM_SCAN_LB_LMAC_IDX 0 5921 #define IWM_SCAN_HB_LMAC_IDX 1 5922 5923 /** 5924 * struct iwm_scan_req_umac 5925 * @flags: &enum iwl_umac_scan_flags 5926 * @uid: scan id, &enum iwl_umac_scan_uid_offsets 5927 * @ooc_priority: out of channel priority - &enum iwl_scan_priority 5928 * @general_flags: &enum iwl_umac_scan_general_flags 5929 * @scan_start_mac_id: report the scan start TSF time according to this mac TSF 5930 * @extended_dwell: dwell time for channels 1, 6 and 11 5931 * @active_dwell: dwell time for active scan per LMAC 5932 * @passive_dwell: dwell time for passive scan per LMAC 5933 * @fragmented_dwell: dwell time for fragmented passive scan 5934 * @adwell_default_n_aps: for adaptive dwell the default number of APs 5935 * per channel 5936 * @adwell_default_n_aps_social: for adaptive dwell the default 5937 * number of APs per social (1,6,11) channel 5938 * @general_flags2: &enum iwl_umac_scan_general_flags2 5939 * @adwell_max_budget: for adaptive dwell the maximal budget of TU to be added 5940 * to total scan time 5941 * @max_out_time: max out of serving channel time, per LMAC - for CDB there 5942 * are 2 LMACs (high band and low band) 5943 * @suspend_time: max suspend time, per LMAC - for CDB there are 2 LMACs 5944 * @scan_priority: scan internal prioritization &enum iwl_scan_priority 5945 * @num_of_fragments: Number of fragments needed for full coverage per band. 5946 * Relevant only for fragmented scan. 5947 * @channel: &struct iwm_scan_umac_chan_param 5948 * @reserved: for future use and alignment 5949 * @reserved3: for future use and alignment 5950 * @data: &struct iwm_scan_channel_cfg_umac and 5951 * &struct iwm_scan_req_umac_tail 5952 */ 5953 struct iwm_scan_req_umac { 5954 uint32_t flags; 5955 uint32_t uid; 5956 uint32_t ooc_priority; 5957 /* SCAN_GENERAL_PARAMS_API_S_VER_1 */ 5958 uint16_t general_flags; 5959 uint8_t reserved; 5960 uint8_t scan_start_mac_id; 5961 union { 5962 struct { 5963 uint8_t extended_dwell; 5964 uint8_t active_dwell; 5965 uint8_t passive_dwell; 5966 uint8_t fragmented_dwell; 5967 uint32_t max_out_time; 5968 uint32_t suspend_time; 5969 uint32_t scan_priority; 5970 struct iwm_scan_umac_chan_param channel; 5971 uint8_t data[]; 5972 } v1; /* SCAN_REQUEST_CMD_UMAC_API_S_VER_1 */ 5973 struct { 5974 uint8_t extended_dwell; 5975 uint8_t active_dwell; 5976 uint8_t passive_dwell; 5977 uint8_t fragmented_dwell; 5978 uint32_t max_out_time[2]; 5979 uint32_t suspend_time[2]; 5980 uint32_t scan_priority; 5981 struct iwm_scan_umac_chan_param channel; 5982 uint8_t data[]; 5983 } v6; /* SCAN_REQUEST_CMD_UMAC_API_S_VER_6 */ 5984 struct { 5985 uint8_t active_dwell; 5986 uint8_t passive_dwell; 5987 uint8_t fragmented_dwell; 5988 uint8_t adwell_default_n_aps; 5989 uint8_t adwell_default_n_aps_social; 5990 uint8_t reserved3; 5991 uint16_t adwell_max_budget; 5992 uint32_t max_out_time[2]; 5993 uint32_t suspend_time[2]; 5994 uint32_t scan_priority; 5995 struct iwm_scan_umac_chan_param channel; 5996 uint8_t data[]; 5997 } v7; /* SCAN_REQUEST_CMD_UMAC_API_S_VER_7 */ 5998 struct { 5999 uint8_t active_dwell[2]; 6000 uint8_t reserved2; 6001 uint8_t adwell_default_n_aps; 6002 uint8_t adwell_default_n_aps_social; 6003 uint8_t general_flags2; 6004 uint16_t adwell_max_budget; 6005 uint32_t max_out_time[2]; 6006 uint32_t suspend_time[2]; 6007 uint32_t scan_priority; 6008 uint8_t passive_dwell[2]; 6009 uint8_t num_of_fragments[2]; 6010 struct iwm_scan_umac_chan_param channel; 6011 uint8_t data[]; 6012 } v8; /* SCAN_REQUEST_CMD_UMAC_API_S_VER_8 */ 6013 struct { 6014 uint8_t active_dwell[2]; 6015 uint8_t adwell_default_hb_n_aps; 6016 uint8_t adwell_default_lb_n_aps; 6017 uint8_t adwell_default_n_aps_social; 6018 uint8_t general_flags2; 6019 uint16_t adwell_max_budget; 6020 uint32_t max_out_time[2]; 6021 uint32_t suspend_time[2]; 6022 uint32_t scan_priority; 6023 uint8_t passive_dwell[2]; 6024 uint8_t num_of_fragments[2]; 6025 struct iwm_scan_umac_chan_param channel; 6026 uint8_t data[]; 6027 } v9; /* SCAN_REQUEST_CMD_UMAC_API_S_VER_9 */ 6028 }; 6029 } __packed; 6030 6031 #define IWM_SCAN_REQ_UMAC_SIZE_V8 sizeof(struct iwm_scan_req_umac) 6032 #define IWM_SCAN_REQ_UMAC_SIZE_V7 48 6033 #define IWM_SCAN_REQ_UMAC_SIZE_V6 44 6034 #define IWM_SCAN_REQ_UMAC_SIZE_V1 36 6035 6036 /** 6037 * struct iwm_umac_scan_abort 6038 * @uid: scan id, &enum iwm_umac_scan_uid_offsets 6039 * @flags: reserved 6040 */ 6041 struct iwm_umac_scan_abort { 6042 uint32_t uid; 6043 uint32_t flags; 6044 } __packed; /* SCAN_ABORT_CMD_UMAC_API_S_VER_1 */ 6045 6046 /** 6047 * struct iwm_umac_scan_complete 6048 * @uid: scan id, &enum iwm_umac_scan_uid_offsets 6049 * @last_schedule: last scheduling line 6050 * @last_iter: last scan iteration number 6051 * @scan status: &enum iwm_scan_offload_complete_status 6052 * @ebs_status: &enum iwm_scan_ebs_status 6053 * @time_from_last_iter: time elapsed from last iteration 6054 * @reserved: for future use 6055 */ 6056 struct iwm_umac_scan_complete { 6057 uint32_t uid; 6058 uint8_t last_schedule; 6059 uint8_t last_iter; 6060 uint8_t status; 6061 uint8_t ebs_status; 6062 uint32_t time_from_last_iter; 6063 uint32_t reserved; 6064 } __packed; /* SCAN_COMPLETE_NTF_UMAC_API_S_VER_1 */ 6065 6066 #define IWM_SCAN_OFFLOAD_MATCHING_CHANNELS_LEN 5 6067 /** 6068 * struct iwm_scan_offload_profile_match - match information 6069 * @bssid: matched bssid 6070 * @channel: channel where the match occurred 6071 * @energy: 6072 * @matching_feature: 6073 * @matching_channels: bitmap of channels that matched, referencing 6074 * the channels passed in tue scan offload request 6075 */ 6076 struct iwm_scan_offload_profile_match { 6077 uint8_t bssid[ETHER_ADDR_LEN]; 6078 uint16_t reserved; 6079 uint8_t channel; 6080 uint8_t energy; 6081 uint8_t matching_feature; 6082 uint8_t matching_channels[IWM_SCAN_OFFLOAD_MATCHING_CHANNELS_LEN]; 6083 } __packed; /* SCAN_OFFLOAD_PROFILE_MATCH_RESULTS_S_VER_1 */ 6084 6085 /** 6086 * struct iwm_scan_offload_profiles_query - match results query response 6087 * @matched_profiles: bitmap of matched profiles, referencing the 6088 * matches passed in the scan offload request 6089 * @last_scan_age: age of the last offloaded scan 6090 * @n_scans_done: number of offloaded scans done 6091 * @gp2_d0u: GP2 when D0U occurred 6092 * @gp2_invoked: GP2 when scan offload was invoked 6093 * @resume_while_scanning: not used 6094 * @self_recovery: obsolete 6095 * @reserved: reserved 6096 * @matches: array of match information, one for each match 6097 */ 6098 struct iwm_scan_offload_profiles_query { 6099 uint32_t matched_profiles; 6100 uint32_t last_scan_age; 6101 uint32_t n_scans_done; 6102 uint32_t gp2_d0u; 6103 uint32_t gp2_invoked; 6104 uint8_t resume_while_scanning; 6105 uint8_t self_recovery; 6106 uint16_t reserved; 6107 struct iwm_scan_offload_profile_match matches[IWM_SCAN_MAX_PROFILES]; 6108 } __packed; /* SCAN_OFFLOAD_PROFILES_QUERY_RSP_S_VER_2 */ 6109 6110 /** 6111 * struct iwm_umac_scan_iter_complete_notif - notifies end of scanning iteration 6112 * @uid: scan id, &enum iwm_umac_scan_uid_offsets 6113 * @scanned_channels: number of channels scanned and number of valid elements in 6114 * results array 6115 * @status: one of SCAN_COMP_STATUS_* 6116 * @bt_status: BT on/off status 6117 * @last_channel: last channel that was scanned 6118 * @tsf_low: TSF timer (lower half) in usecs 6119 * @tsf_high: TSF timer (higher half) in usecs 6120 * @results: array of scan results, only "scanned_channels" of them are valid 6121 */ 6122 struct iwm_umac_scan_iter_complete_notif { 6123 uint32_t uid; 6124 uint8_t scanned_channels; 6125 uint8_t status; 6126 uint8_t bt_status; 6127 uint8_t last_channel; 6128 uint32_t tsf_low; 6129 uint32_t tsf_high; 6130 struct iwm_scan_results_notif results[]; 6131 } __packed; /* SCAN_ITER_COMPLETE_NTF_UMAC_API_S_VER_1 */ 6132 6133 #define IWM_GSCAN_START_CMD 0x0 6134 #define IWM_GSCAN_STOP_CMD 0x1 6135 #define IWM_GSCAN_SET_HOTLIST_CMD 0x2 6136 #define IWM_GSCAN_RESET_HOTLIST_CMD 0x3 6137 #define IWM_GSCAN_SET_SIGNIFICANT_CHANGE_CMD 0x4 6138 #define IWM_GSCAN_RESET_SIGNIFICANT_CHANGE_CMD 0x5 6139 #define IWM_GSCAN_SIGNIFICANT_CHANGE_EVENT 0xFD 6140 #define IWM_GSCAN_HOTLIST_CHANGE_EVENT 0xFE 6141 #define IWM_GSCAN_RESULTS_AVAILABLE_EVENT 0xFF 6142 6143 /* 6144 * END mvm/fw-api-scan.h 6145 */ 6146 6147 /* 6148 * BEGIN mvm/fw-api-sta.h 6149 */ 6150 6151 /* STA API */ 6152 6153 /** 6154 * flags for the ADD_STA host command 6155 * @IWM_STA_FLG_REDUCED_TX_PWR_CTRL: 6156 * @IWM_STA_FLG_REDUCED_TX_PWR_DATA: 6157 * @IWM_STA_FLG_DISABLE_TX: set if TX should be disabled 6158 * @IWM_STA_FLG_PS: set if STA is in Power Save 6159 * @IWM_STA_FLG_INVALID: set if STA is invalid 6160 * @IWM_STA_FLG_DLP_EN: Direct Link Protocol is enabled 6161 * @IWM_STA_FLG_SET_ALL_KEYS: the current key applies to all key IDs 6162 * @IWM_STA_FLG_DRAIN_FLOW: drain flow 6163 * @IWM_STA_FLG_PAN: STA is for PAN interface 6164 * @IWM_STA_FLG_CLASS_AUTH: 6165 * @IWM_STA_FLG_CLASS_ASSOC: 6166 * @IWM_STA_FLG_CLASS_MIMO_PROT: 6167 * @IWM_STA_FLG_MAX_AGG_SIZE_MSK: maximal size for A-MPDU 6168 * @IWM_STA_FLG_AGG_MPDU_DENS_MSK: maximal MPDU density for Tx aggregation 6169 * @IWM_STA_FLG_FAT_EN_MSK: support for channel width (for Tx). This flag is 6170 * initialised by driver and can be updated by fw upon reception of 6171 * action frames that can change the channel width. When cleared the fw 6172 * will send all the frames in 20MHz even when FAT channel is requested. 6173 * @IWM_STA_FLG_MIMO_EN_MSK: support for MIMO. This flag is initialised by the 6174 * driver and can be updated by fw upon reception of action frames. 6175 * @IWM_STA_FLG_MFP_EN: Management Frame Protection 6176 */ 6177 #define IWM_STA_FLG_REDUCED_TX_PWR_CTRL (1 << 3) 6178 #define IWM_STA_FLG_REDUCED_TX_PWR_DATA (1 << 6) 6179 6180 #define IWM_STA_FLG_DISABLE_TX (1 << 4) 6181 6182 #define IWM_STA_FLG_PS (1 << 8) 6183 #define IWM_STA_FLG_DRAIN_FLOW (1 << 12) 6184 #define IWM_STA_FLG_PAN (1 << 13) 6185 #define IWM_STA_FLG_CLASS_AUTH (1 << 14) 6186 #define IWM_STA_FLG_CLASS_ASSOC (1 << 15) 6187 #define IWM_STA_FLG_RTS_MIMO_PROT (1 << 17) 6188 6189 #define IWM_STA_FLG_MAX_AGG_SIZE_SHIFT 19 6190 #define IWM_STA_FLG_MAX_AGG_SIZE_8K (0 << IWM_STA_FLG_MAX_AGG_SIZE_SHIFT) 6191 #define IWM_STA_FLG_MAX_AGG_SIZE_16K (1 << IWM_STA_FLG_MAX_AGG_SIZE_SHIFT) 6192 #define IWM_STA_FLG_MAX_AGG_SIZE_32K (2 << IWM_STA_FLG_MAX_AGG_SIZE_SHIFT) 6193 #define IWM_STA_FLG_MAX_AGG_SIZE_64K (3 << IWM_STA_FLG_MAX_AGG_SIZE_SHIFT) 6194 #define IWM_STA_FLG_MAX_AGG_SIZE_128K (4 << IWM_STA_FLG_MAX_AGG_SIZE_SHIFT) 6195 #define IWM_STA_FLG_MAX_AGG_SIZE_256K (5 << IWM_STA_FLG_MAX_AGG_SIZE_SHIFT) 6196 #define IWM_STA_FLG_MAX_AGG_SIZE_512K (6 << IWM_STA_FLG_MAX_AGG_SIZE_SHIFT) 6197 #define IWM_STA_FLG_MAX_AGG_SIZE_1024K (7 << IWM_STA_FLG_MAX_AGG_SIZE_SHIFT) 6198 #define IWM_STA_FLG_MAX_AGG_SIZE_MSK (7 << IWM_STA_FLG_MAX_AGG_SIZE_SHIFT) 6199 6200 #define IWM_STA_FLG_AGG_MPDU_DENS_SHIFT 23 6201 #define IWM_STA_FLG_AGG_MPDU_DENS_2US (4 << IWM_STA_FLG_AGG_MPDU_DENS_SHIFT) 6202 #define IWM_STA_FLG_AGG_MPDU_DENS_4US (5 << IWM_STA_FLG_AGG_MPDU_DENS_SHIFT) 6203 #define IWM_STA_FLG_AGG_MPDU_DENS_8US (6 << IWM_STA_FLG_AGG_MPDU_DENS_SHIFT) 6204 #define IWM_STA_FLG_AGG_MPDU_DENS_16US (7 << IWM_STA_FLG_AGG_MPDU_DENS_SHIFT) 6205 #define IWM_STA_FLG_AGG_MPDU_DENS_MSK (7 << IWM_STA_FLG_AGG_MPDU_DENS_SHIFT) 6206 6207 #define IWM_STA_FLG_FAT_EN_20MHZ (0 << 26) 6208 #define IWM_STA_FLG_FAT_EN_40MHZ (1 << 26) 6209 #define IWM_STA_FLG_FAT_EN_80MHZ (2 << 26) 6210 #define IWM_STA_FLG_FAT_EN_160MHZ (3 << 26) 6211 #define IWM_STA_FLG_FAT_EN_MSK (3 << 26) 6212 6213 #define IWM_STA_FLG_MIMO_EN_SISO (0 << 28) 6214 #define IWM_STA_FLG_MIMO_EN_MIMO2 (1 << 28) 6215 #define IWM_STA_FLG_MIMO_EN_MIMO3 (2 << 28) 6216 #define IWM_STA_FLG_MIMO_EN_MSK (3 << 28) 6217 6218 /** 6219 * key flags for the ADD_STA host command 6220 * @IWM_STA_KEY_FLG_NO_ENC: no encryption 6221 * @IWM_STA_KEY_FLG_WEP: WEP encryption algorithm 6222 * @IWM_STA_KEY_FLG_CCM: CCMP encryption algorithm 6223 * @IWM_STA_KEY_FLG_TKIP: TKIP encryption algorithm 6224 * @IWM_STA_KEY_FLG_EXT: extended cipher algorithm (depends on the FW support) 6225 * @IWM_STA_KEY_FLG_CMAC: CMAC encryption algorithm 6226 * @IWM_STA_KEY_FLG_ENC_UNKNOWN: unknown encryption algorithm 6227 * @IWM_STA_KEY_FLG_EN_MSK: mask for encryption algorithmi value 6228 * @IWM_STA_KEY_FLG_WEP_KEY_MAP: wep is either a group key (0 - legacy WEP) or from 6229 * station info array (1 - n 1X mode) 6230 * @IWM_STA_KEY_FLG_KEYID_MSK: the index of the key 6231 * @IWM_STA_KEY_NOT_VALID: key is invalid 6232 * @IWM_STA_KEY_FLG_WEP_13BYTES: set for 13 bytes WEP key 6233 * @IWM_STA_KEY_MULTICAST: set for multicast key 6234 * @IWM_STA_KEY_MFP: key is used for Management Frame Protection 6235 */ 6236 #define IWM_STA_KEY_FLG_NO_ENC (0 << 0) 6237 #define IWM_STA_KEY_FLG_WEP (1 << 0) 6238 #define IWM_STA_KEY_FLG_CCM (2 << 0) 6239 #define IWM_STA_KEY_FLG_TKIP (3 << 0) 6240 #define IWM_STA_KEY_FLG_EXT (4 << 0) 6241 #define IWM_STA_KEY_FLG_CMAC (6 << 0) 6242 #define IWM_STA_KEY_FLG_ENC_UNKNOWN (7 << 0) 6243 #define IWM_STA_KEY_FLG_EN_MSK (7 << 0) 6244 #define IWM_STA_KEY_FLG_WEP_KEY_MAP (1 << 3) 6245 #define IWM_STA_KEY_FLG_KEYID_POS 8 6246 #define IWM_STA_KEY_FLG_KEYID_MSK (3 << IWM_STA_KEY_FLG_KEYID_POS) 6247 #define IWM_STA_KEY_NOT_VALID (1 << 11) 6248 #define IWM_STA_KEY_FLG_WEP_13BYTES (1 << 12) 6249 #define IWM_STA_KEY_MULTICAST (1 << 14) 6250 #define IWM_STA_KEY_MFP (1 << 15) 6251 6252 /** 6253 * indicate to the fw what flag are being changed 6254 * @IWM_STA_MODIFY_QUEUE_REMOVAL: this command removes a queue 6255 * @IWM_STA_MODIFY_TID_DISABLE_TX: this command modifies %tid_disable_tx 6256 * @IWM_STA_MODIFY_TX_RATE: unused 6257 * @IWM_STA_MODIFY_ADD_BA_TID: this command modifies %add_immediate_ba_tid 6258 * @IWM_STA_MODIFY_REMOVE_BA_TID: this command modifies %remove_immediate_ba_tid 6259 * @IWM_STA_MODIFY_SLEEPING_STA_TX_COUNT: this command modifies %sleep_tx_count 6260 * @IWM_STA_MODIFY_PROT_TH: 6261 * @IWM_STA_MODIFY_QUEUES: modify the queues used by this station 6262 */ 6263 #define IWM_STA_MODIFY_QUEUE_REMOVAL (1 << 0) 6264 #define IWM_STA_MODIFY_TID_DISABLE_TX (1 << 1) 6265 #define IWM_STA_MODIFY_TX_RATE (1 << 2) 6266 #define IWM_STA_MODIFY_ADD_BA_TID (1 << 3) 6267 #define IWM_STA_MODIFY_REMOVE_BA_TID (1 << 4) 6268 #define IWM_STA_MODIFY_SLEEPING_STA_TX_COUNT (1 << 5) 6269 #define IWM_STA_MODIFY_PROT_TH (1 << 6) 6270 #define IWM_STA_MODIFY_QUEUES (1 << 7) 6271 6272 #define IWM_STA_MODE_MODIFY 1 6273 6274 /** 6275 * type of sleep of the station 6276 * @IWM_STA_SLEEP_STATE_AWAKE: 6277 * @IWM_STA_SLEEP_STATE_PS_POLL: 6278 * @IWM_STA_SLEEP_STATE_UAPSD: 6279 * @IWM_STA_SLEEP_STATE_MOREDATA: set more-data bit on 6280 * (last) released frame 6281 */ 6282 #define IWM_STA_SLEEP_STATE_AWAKE 0 6283 #define IWM_STA_SLEEP_STATE_PS_POLL (1 << 0) 6284 #define IWM_STA_SLEEP_STATE_UAPSD (1 << 1) 6285 #define IWM_STA_SLEEP_STATE_MOREDATA (1 << 2) 6286 6287 /* STA ID and color bits definitions */ 6288 #define IWM_STA_ID_SEED (0x0f) 6289 #define IWM_STA_ID_POS (0) 6290 #define IWM_STA_ID_MSK (IWM_STA_ID_SEED << IWM_STA_ID_POS) 6291 6292 #define IWM_STA_COLOR_SEED (0x7) 6293 #define IWM_STA_COLOR_POS (4) 6294 #define IWM_STA_COLOR_MSK (IWM_STA_COLOR_SEED << IWM_STA_COLOR_POS) 6295 6296 #define IWM_STA_ID_N_COLOR_GET_COLOR(id_n_color) \ 6297 (((id_n_color) & IWM_STA_COLOR_MSK) >> IWM_STA_COLOR_POS) 6298 #define IWM_STA_ID_N_COLOR_GET_ID(id_n_color) \ 6299 (((id_n_color) & IWM_STA_ID_MSK) >> IWM_STA_ID_POS) 6300 6301 #define IWM_STA_KEY_MAX_NUM (16) 6302 #define IWM_STA_KEY_IDX_INVALID (0xff) 6303 #define IWM_STA_KEY_MAX_DATA_KEY_NUM (4) 6304 #define IWM_MAX_GLOBAL_KEYS (4) 6305 #define IWM_STA_KEY_LEN_WEP40 (5) 6306 #define IWM_STA_KEY_LEN_WEP104 (13) 6307 6308 /** 6309 * struct iwm_keyinfo - key information 6310 * @key_flags: type %iwm_sta_key_flag 6311 * @tkip_rx_tsc_byte2: TSC[2] for key mix ph1 detection 6312 * @tkip_rx_ttak: 10-byte unicast TKIP TTAK for Rx 6313 * @key_offset: key offset in the fw's key table 6314 * @key: 16-byte unicast decryption key 6315 * @tx_secur_seq_cnt: initial RSC / PN needed for replay check 6316 * @hw_tkip_mic_rx_key: byte: MIC Rx Key - used for TKIP only 6317 * @hw_tkip_mic_tx_key: byte: MIC Tx Key - used for TKIP only 6318 */ 6319 struct iwm_keyinfo { 6320 uint16_t key_flags; 6321 uint8_t tkip_rx_tsc_byte2; 6322 uint8_t reserved1; 6323 uint16_t tkip_rx_ttak[5]; 6324 uint8_t key_offset; 6325 uint8_t reserved2; 6326 uint8_t key[16]; 6327 uint64_t tx_secur_seq_cnt; 6328 uint64_t hw_tkip_mic_rx_key; 6329 uint64_t hw_tkip_mic_tx_key; 6330 } __packed; 6331 6332 #define IWM_ADD_STA_STATUS_MASK 0xFF 6333 #define IWM_ADD_STA_BAID_VALID_MASK 0x8000 6334 #define IWM_ADD_STA_BAID_MASK 0x7F00 6335 #define IWM_ADD_STA_BAID_SHIFT 8 6336 6337 /** 6338 * struct iwm_add_sta_cmd_v7 - Add/modify a station in the fw's sta table. 6339 * ( REPLY_ADD_STA = 0x18 ) 6340 * @add_modify: 1: modify existing, 0: add new station 6341 * @awake_acs: 6342 * @tid_disable_tx: is tid BIT(tid) enabled for Tx. Clear BIT(x) to enable 6343 * AMPDU for tid x. Set %IWM_STA_MODIFY_TID_DISABLE_TX to change this field. 6344 * @mac_id_n_color: the Mac context this station belongs to 6345 * @addr[ETHER_ADDR_LEN]: station's MAC address 6346 * @sta_id: index of station in uCode's station table 6347 * @modify_mask: IWM_STA_MODIFY_*, selects which parameters to modify vs. leave 6348 * alone. 1 - modify, 0 - don't change. 6349 * @station_flags: look at %iwm_sta_flags 6350 * @station_flags_msk: what of %station_flags have changed 6351 * @add_immediate_ba_tid: tid for which to add block-ack support (Rx) 6352 * Set %IWM_STA_MODIFY_ADD_BA_TID to use this field, and also set 6353 * add_immediate_ba_ssn. 6354 * @remove_immediate_ba_tid: tid for which to remove block-ack support (Rx) 6355 * Set %IWM_STA_MODIFY_REMOVE_BA_TID to use this field 6356 * @add_immediate_ba_ssn: ssn for the Rx block-ack session. Used together with 6357 * add_immediate_ba_tid. 6358 * @sleep_tx_count: number of packets to transmit to station even though it is 6359 * asleep. Used to synchronise PS-poll and u-APSD responses while ucode 6360 * keeps track of STA sleep state. 6361 * @sleep_state_flags: Look at %iwm_sta_sleep_flag. 6362 * @assoc_id: assoc_id to be sent in VHT PLCP (9-bit), for grp use 0, for AP 6363 * mac-addr. 6364 * @beamform_flags: beam forming controls 6365 * @tfd_queue_msk: tfd queues used by this station 6366 * 6367 * The device contains an internal table of per-station information, with info 6368 * on security keys, aggregation parameters, and Tx rates for initial Tx 6369 * attempt and any retries (set by IWM_REPLY_TX_LINK_QUALITY_CMD). 6370 * 6371 * ADD_STA sets up the table entry for one station, either creating a new 6372 * entry, or modifying a pre-existing one. 6373 */ 6374 struct iwm_add_sta_cmd_v7 { 6375 uint8_t add_modify; 6376 uint8_t awake_acs; 6377 uint16_t tid_disable_tx; 6378 uint32_t mac_id_n_color; 6379 uint8_t addr[ETHER_ADDR_LEN]; /* _STA_ID_MODIFY_INFO_API_S_VER_1 */ 6380 uint16_t reserved2; 6381 uint8_t sta_id; 6382 uint8_t modify_mask; 6383 uint16_t reserved3; 6384 uint32_t station_flags; 6385 uint32_t station_flags_msk; 6386 uint8_t add_immediate_ba_tid; 6387 uint8_t remove_immediate_ba_tid; 6388 uint16_t add_immediate_ba_ssn; 6389 uint16_t sleep_tx_count; 6390 uint16_t sleep_state_flags; 6391 uint16_t assoc_id; 6392 uint16_t beamform_flags; 6393 uint32_t tfd_queue_msk; 6394 } __packed; /* ADD_STA_CMD_API_S_VER_7 */ 6395 6396 /** 6397 * struct iwm_add_sta_cmd - Add/modify a station in the fw's sta table. 6398 * ( REPLY_ADD_STA = 0x18 ) 6399 * @add_modify: see &enum iwl_sta_mode 6400 * @awake_acs: ACs to transmit data on while station is sleeping (for U-APSD) 6401 * @tid_disable_tx: is tid BIT(tid) enabled for Tx. Clear BIT(x) to enable 6402 * AMPDU for tid x. Set %STA_MODIFY_TID_DISABLE_TX to change this field. 6403 * @mac_id_n_color: the Mac context this station belongs to, 6404 * see &enum iwl_ctxt_id_and_color 6405 * @addr: station's MAC address 6406 * @reserved2: reserved 6407 * @sta_id: index of station in uCode's station table 6408 * @modify_mask: STA_MODIFY_*, selects which parameters to modify vs. leave 6409 * alone. 1 - modify, 0 - don't change. 6410 * @reserved3: reserved 6411 * @station_flags: look at &enum iwl_sta_flags 6412 * @station_flags_msk: what of %station_flags have changed, 6413 * also &enum iwl_sta_flags 6414 * @add_immediate_ba_tid: tid for which to add block-ack support (Rx) 6415 * Set %STA_MODIFY_ADD_BA_TID to use this field, and also set 6416 * add_immediate_ba_ssn. 6417 * @remove_immediate_ba_tid: tid for which to remove block-ack support (Rx) 6418 * Set %STA_MODIFY_REMOVE_BA_TID to use this field 6419 * @add_immediate_ba_ssn: ssn for the Rx block-ack session. Used together with 6420 * add_immediate_ba_tid. 6421 * @sleep_tx_count: number of packets to transmit to station even though it is 6422 * asleep. Used to synchronise PS-poll and u-APSD responses while ucode 6423 * keeps track of STA sleep state. 6424 * @station_type: type of this station. See &enum iwl_sta_type. 6425 * @sleep_state_flags: Look at &enum iwl_sta_sleep_flag. 6426 * @assoc_id: assoc_id to be sent in VHT PLCP (9-bit), for grp use 0, for AP 6427 * mac-addr. 6428 * @beamform_flags: beam forming controls 6429 * @tfd_queue_msk: tfd queues used by this station. 6430 * Obselete for new TX API (9 and above). 6431 * @rx_ba_window: aggregation window size 6432 * @sp_length: the size of the SP in actual number of frames 6433 * @uapsd_acs: 4 LS bits are trigger enabled ACs, 4 MS bits are the deliver 6434 * enabled ACs. 6435 * 6436 * The device contains an internal table of per-station information, with info 6437 * on security keys, aggregation parameters, and Tx rates for initial Tx 6438 * attempt and any retries (set by REPLY_TX_LINK_QUALITY_CMD). 6439 * 6440 * ADD_STA sets up the table entry for one station, either creating a new 6441 * entry, or modifying a pre-existing one. 6442 */ 6443 struct iwm_add_sta_cmd { 6444 uint8_t add_modify; 6445 uint8_t awake_acs; 6446 uint16_t tid_disable_tx; 6447 uint32_t mac_id_n_color; 6448 uint8_t addr[ETHER_ADDR_LEN]; /* _STA_ID_MODIFY_INFO_API_S_VER_1 */ 6449 uint16_t reserved2; 6450 uint8_t sta_id; 6451 uint8_t modify_mask; 6452 uint16_t reserved3; 6453 uint32_t station_flags; 6454 uint32_t station_flags_msk; 6455 uint8_t add_immediate_ba_tid; 6456 uint8_t remove_immediate_ba_tid; 6457 uint16_t add_immediate_ba_ssn; 6458 uint16_t sleep_tx_count; 6459 uint8_t sleep_state_flags; 6460 uint8_t station_type; 6461 uint16_t assoc_id; 6462 uint16_t beamform_flags; 6463 uint32_t tfd_queue_msk; 6464 uint16_t rx_ba_window; 6465 uint8_t sp_length; 6466 uint8_t uapsd_acs; 6467 } __packed; /* ADD_STA_CMD_API_S_VER_10 */ 6468 6469 /** 6470 * FW station types 6471 * ( REPLY_ADD_STA = 0x18 ) 6472 * @IWM_STA_LINK: Link station - normal RX and TX traffic. 6473 * @IWM_STA_GENERAL_PURPOSE: General purpose. In AP mode used for beacons 6474 * and probe responses. 6475 * @IWM_STA_MULTICAST: multicast traffic, 6476 * @IWM_STA_TDLS_LINK: TDLS link station 6477 * @IWM_STA_AUX_ACTIVITY: auxilary station (scan, ROC and so on). 6478 */ 6479 #define IWM_STA_LINK 0 6480 #define IWM_STA_GENERAL_PURPOSE 1 6481 #define IWM_STA_MULTICAST 2 6482 #define IWM_STA_TDLS_LINK 3 6483 #define IWM_STA_AUX_ACTIVITY 4 6484 6485 /** 6486 * struct iwm_add_sta_key_common - add/modify sta key common part 6487 * ( REPLY_ADD_STA_KEY = 0x17 ) 6488 * @sta_id: index of station in uCode's station table 6489 * @key_offset: key offset in key storage 6490 * @key_flags: IWM_STA_KEY_FLG_* 6491 * @key: key material data 6492 * @rx_secur_seq_cnt: RX security sequence counter for the key 6493 */ 6494 struct iwm_add_sta_key_common { 6495 uint8_t sta_id; 6496 uint8_t key_offset; 6497 uint16_t key_flags; 6498 uint8_t key[32]; 6499 uint8_t rx_secur_seq_cnt[16]; 6500 } __packed; 6501 6502 /** 6503 * struct iwm_add_sta_key_cmd_v1 - add/modify sta key 6504 * @common: see &struct iwm_add_sta_key_common 6505 * @tkip_rx_tsc_byte2: TSC[2] for key mix ph1 detection 6506 * @reserved: reserved 6507 * @tkip_rx_ttak: 10-byte unicast TKIP TTAK for Rx 6508 */ 6509 struct iwm_add_sta_key_cmd_v1 { 6510 struct iwm_add_sta_key_common common; 6511 uint8_t tkip_rx_tsc_byte2; 6512 uint8_t reserved; 6513 uint16_t tkip_rx_ttak[5]; 6514 } __packed; /* ADD_MODIFY_STA_KEY_API_S_VER_1 */ 6515 6516 /** 6517 * struct iwm_add_sta_key_cmd - add/modify sta key 6518 * @common: see &struct iwm_add_sta_key_common 6519 * @rx_mic_key: TKIP RX unicast or multicast key 6520 * @tx_mic_key: TKIP TX key 6521 * @transmit_seq_cnt: TSC, transmit packet number 6522 */ 6523 struct iwm_add_sta_key_cmd { 6524 struct iwm_add_sta_key_common common; 6525 uint64_t rx_mic_key; 6526 uint64_t tx_mic_key; 6527 uint64_t transmit_seq_cnt; 6528 } __packed; /* ADD_MODIFY_STA_KEY_API_S_VER_2 */ 6529 6530 /** 6531 * status in the response to ADD_STA command 6532 * @IWM_ADD_STA_SUCCESS: operation was executed successfully 6533 * @IWM_ADD_STA_STATIONS_OVERLOAD: no room left in the fw's station table 6534 * @IWM_ADD_STA_IMMEDIATE_BA_FAILURE: can't add Rx block ack session 6535 * @IWM_ADD_STA_MODIFY_NON_EXISTING_STA: driver requested to modify a station 6536 * that doesn't exist. 6537 */ 6538 #define IWM_ADD_STA_SUCCESS 0x1 6539 #define IWM_ADD_STA_STATIONS_OVERLOAD 0x2 6540 #define IWM_ADD_STA_IMMEDIATE_BA_FAILURE 0x4 6541 #define IWM_ADD_STA_MODIFY_NON_EXISTING_STA 0x8 6542 6543 /** 6544 * struct iwm_rm_sta_cmd - Add / modify a station in the fw's station table 6545 * ( IWM_REMOVE_STA = 0x19 ) 6546 * @sta_id: the station id of the station to be removed 6547 */ 6548 struct iwm_rm_sta_cmd { 6549 uint8_t sta_id; 6550 uint8_t reserved[3]; 6551 } __packed; /* IWM_REMOVE_STA_CMD_API_S_VER_2 */ 6552 6553 /** 6554 * struct iwm_mgmt_mcast_key_cmd 6555 * ( IWM_MGMT_MCAST_KEY = 0x1f ) 6556 * @ctrl_flags: %iwm_sta_key_flag 6557 * @IGTK: 6558 * @K1: IGTK master key 6559 * @K2: IGTK sub key 6560 * @sta_id: station ID that support IGTK 6561 * @key_id: 6562 * @receive_seq_cnt: initial RSC/PN needed for replay check 6563 */ 6564 struct iwm_mgmt_mcast_key_cmd { 6565 uint32_t ctrl_flags; 6566 uint8_t IGTK[16]; 6567 uint8_t K1[16]; 6568 uint8_t K2[16]; 6569 uint32_t key_id; 6570 uint32_t sta_id; 6571 uint64_t receive_seq_cnt; 6572 } __packed; /* SEC_MGMT_MULTICAST_KEY_CMD_API_S_VER_1 */ 6573 6574 struct iwm_wep_key { 6575 uint8_t key_index; 6576 uint8_t key_offset; 6577 uint16_t reserved1; 6578 uint8_t key_size; 6579 uint8_t reserved2[3]; 6580 uint8_t key[16]; 6581 } __packed; 6582 6583 struct iwm_wep_key_cmd { 6584 uint32_t mac_id_n_color; 6585 uint8_t num_keys; 6586 uint8_t decryption_type; 6587 uint8_t flags; 6588 uint8_t reserved; 6589 struct iwm_wep_key wep_key[0]; 6590 } __packed; /* SEC_CURR_WEP_KEY_CMD_API_S_VER_2 */ 6591 6592 /* 6593 * BT coex 6594 */ 6595 6596 #define IWM_BT_COEX_DISABLE 0x0 6597 #define IWM_BT_COEX_NW 0x1 6598 #define IWM_BT_COEX_BT 0x2 6599 #define IWM_BT_COEX_WIFI 0x3 6600 /* BT_COEX_MODES_E */ 6601 6602 #define IWM_BT_COEX_MPLUT_ENABLED (1 << 0) 6603 #define IWM_BT_COEX_MPLUT_BOOST_ENABLED (1 << 1) 6604 #define IWM_BT_COEX_SYNC2SCO_ENABLED (1 << 2) 6605 #define IWM_BT_COEX_CORUN_ENABLED (1 << 3) 6606 #define IWM_BT_COEX_HIGH_BAND_RET (1 << 4) 6607 /* BT_COEX_MODULES_ENABLE_E_VER_1 */ 6608 6609 /** 6610 * struct iwm_bt_coex_cmd - bt coex configuration command 6611 * @mode: enum %iwm_bt_coex_mode 6612 * @enabled_modules: enum %iwm_bt_coex_enabled_modules 6613 * 6614 * The structure is used for the BT_COEX command. 6615 */ 6616 struct iwm_bt_coex_cmd { 6617 uint32_t mode; 6618 uint32_t enabled_modules; 6619 } __packed; /* BT_COEX_CMD_API_S_VER_6 */ 6620 6621 6622 /* 6623 * Location Aware Regulatory (LAR) API - MCC updates 6624 */ 6625 6626 /** 6627 * struct iwm_mcc_update_cmd_v1 - Request the device to update geographic 6628 * regulatory profile according to the given MCC (Mobile Country Code). 6629 * The MCC is two letter-code, ascii upper case[A-Z] or '00' for world domain. 6630 * 'ZZ' MCC will be used to switch to NVM default profile; in this case, the 6631 * MCC in the cmd response will be the relevant MCC in the NVM. 6632 * @mcc: given mobile country code 6633 * @source_id: the source from where we got the MCC, see iwm_mcc_source 6634 * @reserved: reserved for alignment 6635 */ 6636 struct iwm_mcc_update_cmd_v1 { 6637 uint16_t mcc; 6638 uint8_t source_id; 6639 uint8_t reserved; 6640 } __packed; /* LAR_UPDATE_MCC_CMD_API_S_VER_1 */ 6641 6642 /** 6643 * struct iwm_mcc_update_cmd - Request the device to update geographic 6644 * regulatory profile according to the given MCC (Mobile Country Code). 6645 * The MCC is two letter-code, ascii upper case[A-Z] or '00' for world domain. 6646 * 'ZZ' MCC will be used to switch to NVM default profile; in this case, the 6647 * MCC in the cmd response will be the relevant MCC in the NVM. 6648 * @mcc: given mobile country code 6649 * @source_id: the source from where we got the MCC, see iwm_mcc_source 6650 * @reserved: reserved for alignment 6651 * @key: integrity key for MCC API OEM testing 6652 * @reserved2: reserved 6653 */ 6654 struct iwm_mcc_update_cmd { 6655 uint16_t mcc; 6656 uint8_t source_id; 6657 uint8_t reserved; 6658 uint32_t key; 6659 uint32_t reserved2[5]; 6660 } __packed; /* LAR_UPDATE_MCC_CMD_API_S_VER_2 */ 6661 6662 /** 6663 * iwm_mcc_update_resp_v1 - response to MCC_UPDATE_CMD. 6664 * Contains the new channel control profile map, if changed, and the new MCC 6665 * (mobile country code). 6666 * The new MCC may be different than what was requested in MCC_UPDATE_CMD. 6667 * @status: see &enum iwm_mcc_update_status 6668 * @mcc: the new applied MCC 6669 * @cap: capabilities for all channels which matches the MCC 6670 * @source_id: the MCC source, see iwm_mcc_source 6671 * @n_channels: number of channels in @channels_data (may be 14, 39, 50 or 51 6672 * channels, depending on platform) 6673 * @channels: channel control data map, DWORD for each channel. Only the first 6674 * 16bits are used. 6675 */ 6676 struct iwm_mcc_update_resp_v1 { 6677 uint32_t status; 6678 uint16_t mcc; 6679 uint8_t cap; 6680 uint8_t source_id; 6681 uint32_t n_channels; 6682 uint32_t channels[0]; 6683 } __packed; /* LAR_UPDATE_MCC_CMD_RESP_S_VER_1 */ 6684 6685 /** 6686 * iwm_mcc_update_resp_v2 - response to MCC_UPDATE_CMD. 6687 * Contains the new channel control profile map, if changed, and the new MCC 6688 * (mobile country code). 6689 * The new MCC may be different than what was requested in MCC_UPDATE_CMD. 6690 * @status: see &enum iwm_mcc_update_status 6691 * @mcc: the new applied MCC 6692 * @cap: capabilities for all channels which matches the MCC 6693 * @source_id: the MCC source, see iwm_mcc_source 6694 * @time: time elapsed from the MCC test start (in 30 seconds TU) 6695 * @reserved: reserved. 6696 * @n_channels: number of channels in @channels_data (may be 14, 39, 50 or 51 6697 * channels, depending on platform) 6698 * @channels: channel control data map, DWORD for each channel. Only the first 6699 * 16bits are used. 6700 */ 6701 struct iwm_mcc_update_resp_v2 { 6702 uint32_t status; 6703 uint16_t mcc; 6704 uint8_t cap; 6705 uint8_t source_id; 6706 uint16_t time; 6707 uint16_t reserved; 6708 uint32_t n_channels; 6709 uint32_t channels[0]; 6710 } __packed; /* LAR_UPDATE_MCC_CMD_RESP_S_VER_2 */ 6711 6712 #define IWM_GEO_NO_INFO 0 6713 #define IWM_GEO_WMM_ETSI_5GHZ_INFO (1 << 0) 6714 6715 /** 6716 * iwm_mcc_update_resp_v3 - response to MCC_UPDATE_CMD. 6717 * Contains the new channel control profile map, if changed, and the new MCC 6718 * (mobile country code). 6719 * The new MCC may be different than what was requested in MCC_UPDATE_CMD. 6720 * @status: see &enum iwm_mcc_update_status 6721 * @mcc: the new applied MCC 6722 * @cap: capabilities for all channels which matches the MCC 6723 * @source_id: the MCC source, see IWM_MCC_SOURCE_* 6724 * @time: time elapsed from the MCC test start (in 30 seconds TU) 6725 * @geo_info: geographic specific profile information 6726 * @n_channels: number of channels in @channels_data (may be 14, 39, 50 or 51 6727 * channels, depending on platform) 6728 * @channels: channel control data map, DWORD for each channel. Only the first 6729 * 16bits are used. 6730 */ 6731 struct iwm_mcc_update_resp_v3 { 6732 uint32_t status; 6733 uint16_t mcc; 6734 uint8_t cap; 6735 uint8_t source_id; 6736 uint16_t time; 6737 uint16_t geo_info; 6738 uint32_t n_channels; 6739 uint32_t channels[0]; 6740 } __packed; /* LAR_UPDATE_MCC_CMD_RESP_S_VER_3 */ 6741 6742 /** 6743 * struct iwm_mcc_chub_notif - chub notifies of mcc change 6744 * (MCC_CHUB_UPDATE_CMD = 0xc9) 6745 * The Chub (Communication Hub, CommsHUB) is a HW component that connects to 6746 * the cellular and connectivity cores that gets updates of the mcc, and 6747 * notifies the ucode directly of any mcc change. 6748 * The ucode requests the driver to request the device to update geographic 6749 * regulatory profile according to the given MCC (Mobile Country Code). 6750 * The MCC is two letter-code, ascii upper case[A-Z] or '00' for world domain. 6751 * 'ZZ' MCC will be used to switch to NVM default profile; in this case, the 6752 * MCC in the cmd response will be the relevant MCC in the NVM. 6753 * @mcc: given mobile country code 6754 * @source_id: identity of the change originator, see iwm_mcc_source 6755 * @reserved1: reserved for alignment 6756 */ 6757 struct iwm_mcc_chub_notif { 6758 uint16_t mcc; 6759 uint8_t source_id; 6760 uint8_t reserved1; 6761 } __packed; /* LAR_MCC_NOTIFY_S */ 6762 6763 #define IWM_MCC_RESP_NEW_CHAN_PROFILE 0 6764 #define IWM_MCC_RESP_SAME_CHAN_PROFILE 1 6765 #define IWM_MCC_RESP_INVALID 2 6766 #define IWM_MCC_RESP_NVM_DISABLED 3 6767 #define IWM_MCC_RESP_ILLEGAL 4 6768 #define IWM_MCC_RESP_LOW_PRIORITY 5 6769 #define IWM_MCC_RESP_TEST_MODE_ACTIVE 6 6770 #define IWM_MCC_RESP_TEST_MODE_NOT_ACTIVE 7 6771 #define IWM_MCC_RESP_TEST_MODE_DENIAL_OF_SERVICE 8 6772 6773 #define IWM_MCC_SOURCE_OLD_FW 0 6774 #define IWM_MCC_SOURCE_ME 1 6775 #define IWM_MCC_SOURCE_BIOS 2 6776 #define IWM_MCC_SOURCE_3G_LTE_HOST 3 6777 #define IWM_MCC_SOURCE_3G_LTE_DEVICE 4 6778 #define IWM_MCC_SOURCE_WIFI 5 6779 #define IWM_MCC_SOURCE_RESERVED 6 6780 #define IWM_MCC_SOURCE_DEFAULT 7 6781 #define IWM_MCC_SOURCE_UNINITIALIZED 8 6782 #define IWM_MCC_SOURCE_MCC_API 9 6783 #define IWM_MCC_SOURCE_GET_CURRENT 0x10 6784 #define IWM_MCC_SOURCE_GETTING_MCC_TEST_MODE 0x11 6785 6786 /** 6787 * struct iwm_dts_measurement_notif_v1 - measurements notification 6788 * 6789 * @temp: the measured temperature 6790 * @voltage: the measured voltage 6791 */ 6792 struct iwm_dts_measurement_notif_v1 { 6793 int32_t temp; 6794 int32_t voltage; 6795 } __packed; /* TEMPERATURE_MEASUREMENT_TRIGGER_NTFY_S_VER_1*/ 6796 6797 /** 6798 * struct iwm_dts_measurement_notif_v2 - measurements notification 6799 * 6800 * @temp: the measured temperature 6801 * @voltage: the measured voltage 6802 * @threshold_idx: the trip index that was crossed 6803 */ 6804 struct iwm_dts_measurement_notif_v2 { 6805 int32_t temp; 6806 int32_t voltage; 6807 int32_t threshold_idx; 6808 } __packed; /* TEMPERATURE_MEASUREMENT_TRIGGER_NTFY_S_VER_2 */ 6809 6810 6811 /* 6812 * Some cherry-picked definitions 6813 */ 6814 6815 #define IWM_FRAME_LIMIT 64 6816 6817 /* 6818 * From Linux commit ab02165ccec4c78162501acedeef1a768acdb811: 6819 * As the firmware is slowly running out of command IDs and grouping of 6820 * commands is desirable anyway, the firmware is extending the command 6821 * header from 4 bytes to 8 bytes to introduce a group (in place of the 6822 * former flags field, since that's always 0 on commands and thus can 6823 * be easily used to distinguish between the two). 6824 * 6825 * These functions retrieve specific information from the id field in 6826 * the iwm_host_cmd struct which contains the command id, the group id, 6827 * and the version of the command. 6828 */ 6829 static inline uint8_t 6830 iwm_cmd_opcode(uint32_t cmdid) 6831 { 6832 return cmdid & 0xff; 6833 } 6834 6835 static inline uint8_t 6836 iwm_cmd_groupid(uint32_t cmdid) 6837 { 6838 return ((cmdid & 0xff00) >> 8); 6839 } 6840 6841 static inline uint8_t 6842 iwm_cmd_version(uint32_t cmdid) 6843 { 6844 return ((cmdid & 0xff0000) >> 16); 6845 } 6846 6847 static inline uint32_t 6848 iwm_cmd_id(uint8_t opcode, uint8_t groupid, uint8_t version) 6849 { 6850 return opcode + (groupid << 8) + (version << 16); 6851 } 6852 6853 /* make uint16_t wide id out of uint8_t group and opcode */ 6854 #define IWM_WIDE_ID(grp, opcode) ((grp << 8) | opcode) 6855 6856 /* due to the conversion, this group is special */ 6857 #define IWM_ALWAYS_LONG_GROUP 1 6858 6859 struct iwm_cmd_header { 6860 uint8_t code; 6861 uint8_t flags; 6862 uint8_t idx; 6863 uint8_t qid; 6864 } __packed; 6865 6866 struct iwm_cmd_header_wide { 6867 uint8_t opcode; 6868 uint8_t group_id; 6869 uint8_t idx; 6870 uint8_t qid; 6871 uint16_t length; 6872 uint8_t reserved; 6873 uint8_t version; 6874 } __packed; 6875 6876 #define IWM_POWER_SCHEME_CAM 1 6877 #define IWM_POWER_SCHEME_BPS 2 6878 #define IWM_POWER_SCHEME_LP 3 6879 6880 #define IWM_DEF_CMD_PAYLOAD_SIZE 320 6881 #define IWM_MAX_CMD_PAYLOAD_SIZE ((4096 - 4) - sizeof(struct iwm_cmd_header)) 6882 #define IWM_CMD_FAILED_MSK 0x40 6883 6884 /** 6885 * struct iwm_device_cmd 6886 * 6887 * For allocation of the command and tx queues, this establishes the overall 6888 * size of the largest command we send to uCode, except for commands that 6889 * aren't fully copied and use other TFD space. 6890 */ 6891 struct iwm_device_cmd { 6892 union { 6893 struct { 6894 struct iwm_cmd_header hdr; 6895 uint8_t data[IWM_DEF_CMD_PAYLOAD_SIZE]; 6896 }; 6897 struct { 6898 struct iwm_cmd_header_wide hdr_wide; 6899 uint8_t data_wide[IWM_DEF_CMD_PAYLOAD_SIZE - 6900 sizeof(struct iwm_cmd_header_wide) + 6901 sizeof(struct iwm_cmd_header)]; 6902 }; 6903 }; 6904 } __packed; 6905 6906 struct iwm_rx_packet { 6907 /* 6908 * The first 4 bytes of the RX frame header contain both the RX frame 6909 * size and some flags. 6910 * Bit fields: 6911 * 31: flag flush RB request 6912 * 30: flag ignore TC (terminal counter) request 6913 * 29: flag fast IRQ request 6914 * 28-26: Reserved 6915 * 25: Offload enabled 6916 * 24: RPF enabled 6917 * 23: RSS enabled 6918 * 22: Checksum enabled 6919 * 21-16: RX queue 6920 * 15-14: Reserved 6921 * 13-00: RX frame size 6922 */ 6923 uint32_t len_n_flags; 6924 struct iwm_cmd_header hdr; 6925 uint8_t data[]; 6926 } __packed; 6927 6928 #define IWM_FH_RSCSR_FRAME_SIZE_MSK 0x00003fff 6929 #define IWM_FH_RSCSR_FRAME_INVALID 0x55550000 6930 #define IWM_FH_RSCSR_FRAME_ALIGN 0x40 6931 #define IWM_FH_RSCSR_RPA_EN (1 << 25) 6932 #define IWM_FH_RSCSR_RADA_EN (1 << 26) 6933 #define IWM_FH_RSCSR_RXQ_POS 16 6934 #define IWM_FH_RSCSR_RXQ_MASK 0x3F0000 6935 6936 static inline uint32_t 6937 iwm_rx_packet_len(const struct iwm_rx_packet *pkt) 6938 { 6939 6940 return le32toh(pkt->len_n_flags) & IWM_FH_RSCSR_FRAME_SIZE_MSK; 6941 } 6942 6943 static inline uint32_t 6944 iwm_rx_packet_payload_len(const struct iwm_rx_packet *pkt) 6945 { 6946 6947 return iwm_rx_packet_len(pkt) - sizeof(pkt->hdr); 6948 } 6949 6950 6951 #define IWM_MIN_DBM -100 6952 #define IWM_MAX_DBM -33 /* realistic guess */ 6953 6954 #define IWM_READ(sc, reg) \ 6955 bus_space_read_4((sc)->sc_st, (sc)->sc_sh, (reg)) 6956 6957 #define IWM_WRITE(sc, reg, val) \ 6958 bus_space_write_4((sc)->sc_st, (sc)->sc_sh, (reg), (val)) 6959 6960 #define IWM_WRITE_1(sc, reg, val) \ 6961 bus_space_write_1((sc)->sc_st, (sc)->sc_sh, (reg), (val)) 6962 6963 #define IWM_SETBITS(sc, reg, mask) \ 6964 IWM_WRITE(sc, reg, IWM_READ(sc, reg) | (mask)) 6965 6966 #define IWM_CLRBITS(sc, reg, mask) \ 6967 IWM_WRITE(sc, reg, IWM_READ(sc, reg) & ~(mask)) 6968 6969 #define IWM_BARRIER_WRITE(sc) \ 6970 bus_space_barrier((sc)->sc_st, (sc)->sc_sh, 0, (sc)->sc_sz, \ 6971 BUS_SPACE_BARRIER_WRITE) 6972 6973 #define IWM_BARRIER_READ_WRITE(sc) \ 6974 bus_space_barrier((sc)->sc_st, (sc)->sc_sh, 0, (sc)->sc_sz, \ 6975 BUS_SPACE_BARRIER_READ | BUS_SPACE_BARRIER_WRITE) 6976 6977 #endif /* __IF_IWM_REG_H__ */ 6978