1 /* $OpenBSD: if_iwmreg.h,v 1.4 2015/06/15 08:06:11 stsp Exp $ */ 2 /* $FreeBSD$ */ 3 4 /****************************************************************************** 5 * 6 * This file is provided under a dual BSD/GPLv2 license. When using or 7 * redistributing this file, you may do so under either license. 8 * 9 * GPL LICENSE SUMMARY 10 * 11 * Copyright(c) 2005 - 2014 Intel Corporation. All rights reserved. 12 * 13 * This program is free software; you can redistribute it and/or modify 14 * it under the terms of version 2 of the GNU General Public License as 15 * published by the Free Software Foundation. 16 * 17 * This program is distributed in the hope that it will be useful, but 18 * WITHOUT ANY WARRANTY; without even the implied warranty of 19 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU 20 * General Public License for more details. 21 * 22 * You should have received a copy of the GNU General Public License 23 * along with this program; if not, write to the Free Software 24 * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110, 25 * USA 26 * 27 * The full GNU General Public License is included in this distribution 28 * in the file called COPYING. 29 * 30 * Contact Information: 31 * Intel Linux Wireless <ilw@linux.intel.com> 32 * Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497 33 * 34 * BSD LICENSE 35 * 36 * Copyright(c) 2005 - 2014 Intel Corporation. All rights reserved. 37 * All rights reserved. 38 * 39 * Redistribution and use in source and binary forms, with or without 40 * modification, are permitted provided that the following conditions 41 * are met: 42 * 43 * * Redistributions of source code must retain the above copyright 44 * notice, this list of conditions and the following disclaimer. 45 * * Redistributions in binary form must reproduce the above copyright 46 * notice, this list of conditions and the following disclaimer in 47 * the documentation and/or other materials provided with the 48 * distribution. 49 * * Neither the name Intel Corporation nor the names of its 50 * contributors may be used to endorse or promote products derived 51 * from this software without specific prior written permission. 52 * 53 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 54 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 55 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 56 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 57 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 58 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 59 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 60 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 61 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 62 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 63 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 64 * 65 *****************************************************************************/ 66 #ifndef __IF_IWM_REG_H__ 67 #define __IF_IWM_REG_H__ 68 69 #define le16_to_cpup(_a_) (le16toh(*(const uint16_t *)(_a_))) 70 #define le32_to_cpup(_a_) (le32toh(*(const uint32_t *)(_a_))) 71 72 /* 73 * BEGIN iwl-csr.h 74 */ 75 76 /* 77 * CSR (control and status registers) 78 * 79 * CSR registers are mapped directly into PCI bus space, and are accessible 80 * whenever platform supplies power to device, even when device is in 81 * low power states due to driver-invoked device resets 82 * (e.g. IWM_CSR_RESET_REG_FLAG_SW_RESET) or uCode-driven power-saving modes. 83 * 84 * Use iwl_write32() and iwl_read32() family to access these registers; 85 * these provide simple PCI bus access, without waking up the MAC. 86 * Do not use iwl_write_direct32() family for these registers; 87 * no need to "grab nic access" via IWM_CSR_GP_CNTRL_REG_FLAG_MAC_ACCESS_REQ. 88 * The MAC (uCode processor, etc.) does not need to be powered up for accessing 89 * the CSR registers. 90 * 91 * NOTE: Device does need to be awake in order to read this memory 92 * via IWM_CSR_EEPROM and IWM_CSR_OTP registers 93 */ 94 #define IWM_CSR_HW_IF_CONFIG_REG (0x000) /* hardware interface config */ 95 #define IWM_CSR_INT_COALESCING (0x004) /* accum ints, 32-usec units */ 96 #define IWM_CSR_INT (0x008) /* host interrupt status/ack */ 97 #define IWM_CSR_INT_MASK (0x00c) /* host interrupt enable */ 98 #define IWM_CSR_FH_INT_STATUS (0x010) /* busmaster int status/ack*/ 99 #define IWM_CSR_GPIO_IN (0x018) /* read external chip pins */ 100 #define IWM_CSR_RESET (0x020) /* busmaster enable, NMI, etc*/ 101 #define IWM_CSR_GP_CNTRL (0x024) 102 103 /* 2nd byte of IWM_CSR_INT_COALESCING, not accessible via iwl_write32()! */ 104 #define IWM_CSR_INT_PERIODIC_REG (0x005) 105 106 /* 107 * Hardware revision info 108 * Bit fields: 109 * 31-16: Reserved 110 * 15-4: Type of device: see IWM_CSR_HW_REV_TYPE_xxx definitions 111 * 3-2: Revision step: 0 = A, 1 = B, 2 = C, 3 = D 112 * 1-0: "Dash" (-) value, as in A-1, etc. 113 */ 114 #define IWM_CSR_HW_REV (0x028) 115 116 /* 117 * EEPROM and OTP (one-time-programmable) memory reads 118 * 119 * NOTE: Device must be awake, initialized via apm_ops.init(), 120 * in order to read. 121 */ 122 #define IWM_CSR_EEPROM_REG (0x02c) 123 #define IWM_CSR_EEPROM_GP (0x030) 124 #define IWM_CSR_OTP_GP_REG (0x034) 125 126 #define IWM_CSR_GIO_REG (0x03C) 127 #define IWM_CSR_GP_UCODE_REG (0x048) 128 #define IWM_CSR_GP_DRIVER_REG (0x050) 129 130 /* 131 * UCODE-DRIVER GP (general purpose) mailbox registers. 132 * SET/CLR registers set/clear bit(s) if "1" is written. 133 */ 134 #define IWM_CSR_UCODE_DRV_GP1 (0x054) 135 #define IWM_CSR_UCODE_DRV_GP1_SET (0x058) 136 #define IWM_CSR_UCODE_DRV_GP1_CLR (0x05c) 137 #define IWM_CSR_UCODE_DRV_GP2 (0x060) 138 139 #define IWM_CSR_MBOX_SET_REG (0x088) 140 #define IWM_CSR_MBOX_SET_REG_OS_ALIVE 0x20 141 142 #define IWM_CSR_LED_REG (0x094) 143 #define IWM_CSR_DRAM_INT_TBL_REG (0x0A0) 144 #define IWM_CSR_MAC_SHADOW_REG_CTRL (0x0A8) /* 6000 and up */ 145 146 147 /* GIO Chicken Bits (PCI Express bus link power management) */ 148 #define IWM_CSR_GIO_CHICKEN_BITS (0x100) 149 150 /* Analog phase-lock-loop configuration */ 151 #define IWM_CSR_ANA_PLL_CFG (0x20c) 152 153 /* 154 * CSR Hardware Revision Workaround Register. Indicates hardware rev; 155 * "step" determines CCK backoff for txpower calculation. Used for 4965 only. 156 * See also IWM_CSR_HW_REV register. 157 * Bit fields: 158 * 3-2: 0 = A, 1 = B, 2 = C, 3 = D step 159 * 1-0: "Dash" (-) value, as in C-1, etc. 160 */ 161 #define IWM_CSR_HW_REV_WA_REG (0x22C) 162 163 #define IWM_CSR_DBG_HPET_MEM_REG (0x240) 164 #define IWM_CSR_DBG_LINK_PWR_MGMT_REG (0x250) 165 166 /* Bits for IWM_CSR_HW_IF_CONFIG_REG */ 167 #define IWM_CSR_HW_IF_CONFIG_REG_MSK_MAC_DASH (0x00000003) 168 #define IWM_CSR_HW_IF_CONFIG_REG_MSK_MAC_STEP (0x0000000C) 169 #define IWM_CSR_HW_IF_CONFIG_REG_MSK_BOARD_VER (0x000000C0) 170 #define IWM_CSR_HW_IF_CONFIG_REG_BIT_MAC_SI (0x00000100) 171 #define IWM_CSR_HW_IF_CONFIG_REG_BIT_RADIO_SI (0x00000200) 172 #define IWM_CSR_HW_IF_CONFIG_REG_MSK_PHY_TYPE (0x00000C00) 173 #define IWM_CSR_HW_IF_CONFIG_REG_MSK_PHY_DASH (0x00003000) 174 #define IWM_CSR_HW_IF_CONFIG_REG_MSK_PHY_STEP (0x0000C000) 175 176 #define IWM_CSR_HW_IF_CONFIG_REG_POS_MAC_DASH (0) 177 #define IWM_CSR_HW_IF_CONFIG_REG_POS_MAC_STEP (2) 178 #define IWM_CSR_HW_IF_CONFIG_REG_POS_BOARD_VER (6) 179 #define IWM_CSR_HW_IF_CONFIG_REG_POS_PHY_TYPE (10) 180 #define IWM_CSR_HW_IF_CONFIG_REG_POS_PHY_DASH (12) 181 #define IWM_CSR_HW_IF_CONFIG_REG_POS_PHY_STEP (14) 182 183 #define IWM_CSR_HW_IF_CONFIG_REG_BIT_HAP_WAKE_L1A (0x00080000) 184 #define IWM_CSR_HW_IF_CONFIG_REG_BIT_EEPROM_OWN_SEM (0x00200000) 185 #define IWM_CSR_HW_IF_CONFIG_REG_BIT_NIC_READY (0x00400000) /* PCI_OWN_SEM */ 186 #define IWM_CSR_HW_IF_CONFIG_REG_BIT_NIC_PREPARE_DONE (0x02000000) /* ME_OWN */ 187 #define IWM_CSR_HW_IF_CONFIG_REG_PREPARE (0x08000000) /* WAKE_ME */ 188 #define IWM_CSR_HW_IF_CONFIG_REG_ENABLE_PME (0x10000000) 189 #define IWM_CSR_HW_IF_CONFIG_REG_PERSIST_MODE (0x40000000) /* PERSISTENCE */ 190 191 #define IWM_CSR_INT_PERIODIC_DIS (0x00) /* disable periodic int*/ 192 #define IWM_CSR_INT_PERIODIC_ENA (0xFF) /* 255*32 usec ~ 8 msec*/ 193 194 /* interrupt flags in INTA, set by uCode or hardware (e.g. dma), 195 * acknowledged (reset) by host writing "1" to flagged bits. */ 196 #define IWM_CSR_INT_BIT_FH_RX (1 << 31) /* Rx DMA, cmd responses, FH_INT[17:16] */ 197 #define IWM_CSR_INT_BIT_HW_ERR (1 << 29) /* DMA hardware error FH_INT[31] */ 198 #define IWM_CSR_INT_BIT_RX_PERIODIC (1 << 28) /* Rx periodic */ 199 #define IWM_CSR_INT_BIT_FH_TX (1 << 27) /* Tx DMA FH_INT[1:0] */ 200 #define IWM_CSR_INT_BIT_SCD (1 << 26) /* TXQ pointer advanced */ 201 #define IWM_CSR_INT_BIT_SW_ERR (1 << 25) /* uCode error */ 202 #define IWM_CSR_INT_BIT_RF_KILL (1 << 7) /* HW RFKILL switch GP_CNTRL[27] toggled */ 203 #define IWM_CSR_INT_BIT_CT_KILL (1 << 6) /* Critical temp (chip too hot) rfkill */ 204 #define IWM_CSR_INT_BIT_SW_RX (1 << 3) /* Rx, command responses */ 205 #define IWM_CSR_INT_BIT_WAKEUP (1 << 1) /* NIC controller waking up (pwr mgmt) */ 206 #define IWM_CSR_INT_BIT_ALIVE (1 << 0) /* uCode interrupts once it initializes */ 207 208 #define IWM_CSR_INI_SET_MASK (IWM_CSR_INT_BIT_FH_RX | \ 209 IWM_CSR_INT_BIT_HW_ERR | \ 210 IWM_CSR_INT_BIT_FH_TX | \ 211 IWM_CSR_INT_BIT_SW_ERR | \ 212 IWM_CSR_INT_BIT_RF_KILL | \ 213 IWM_CSR_INT_BIT_SW_RX | \ 214 IWM_CSR_INT_BIT_WAKEUP | \ 215 IWM_CSR_INT_BIT_ALIVE | \ 216 IWM_CSR_INT_BIT_RX_PERIODIC) 217 218 /* interrupt flags in FH (flow handler) (PCI busmaster DMA) */ 219 #define IWM_CSR_FH_INT_BIT_ERR (1 << 31) /* Error */ 220 #define IWM_CSR_FH_INT_BIT_HI_PRIOR (1 << 30) /* High priority Rx, bypass coalescing */ 221 #define IWM_CSR_FH_INT_BIT_RX_CHNL1 (1 << 17) /* Rx channel 1 */ 222 #define IWM_CSR_FH_INT_BIT_RX_CHNL0 (1 << 16) /* Rx channel 0 */ 223 #define IWM_CSR_FH_INT_BIT_TX_CHNL1 (1 << 1) /* Tx channel 1 */ 224 #define IWM_CSR_FH_INT_BIT_TX_CHNL0 (1 << 0) /* Tx channel 0 */ 225 226 #define IWM_CSR_FH_INT_RX_MASK (IWM_CSR_FH_INT_BIT_HI_PRIOR | \ 227 IWM_CSR_FH_INT_BIT_RX_CHNL1 | \ 228 IWM_CSR_FH_INT_BIT_RX_CHNL0) 229 230 #define IWM_CSR_FH_INT_TX_MASK (IWM_CSR_FH_INT_BIT_TX_CHNL1 | \ 231 IWM_CSR_FH_INT_BIT_TX_CHNL0) 232 233 /* GPIO */ 234 #define IWM_CSR_GPIO_IN_BIT_AUX_POWER (0x00000200) 235 #define IWM_CSR_GPIO_IN_VAL_VAUX_PWR_SRC (0x00000000) 236 #define IWM_CSR_GPIO_IN_VAL_VMAIN_PWR_SRC (0x00000200) 237 238 /* RESET */ 239 #define IWM_CSR_RESET_REG_FLAG_NEVO_RESET (0x00000001) 240 #define IWM_CSR_RESET_REG_FLAG_FORCE_NMI (0x00000002) 241 #define IWM_CSR_RESET_REG_FLAG_SW_RESET (0x00000080) 242 #define IWM_CSR_RESET_REG_FLAG_MASTER_DISABLED (0x00000100) 243 #define IWM_CSR_RESET_REG_FLAG_STOP_MASTER (0x00000200) 244 #define IWM_CSR_RESET_LINK_PWR_MGMT_DISABLED (0x80000000) 245 246 /* 247 * GP (general purpose) CONTROL REGISTER 248 * Bit fields: 249 * 27: HW_RF_KILL_SW 250 * Indicates state of (platform's) hardware RF-Kill switch 251 * 26-24: POWER_SAVE_TYPE 252 * Indicates current power-saving mode: 253 * 000 -- No power saving 254 * 001 -- MAC power-down 255 * 010 -- PHY (radio) power-down 256 * 011 -- Error 257 * 9-6: SYS_CONFIG 258 * Indicates current system configuration, reflecting pins on chip 259 * as forced high/low by device circuit board. 260 * 4: GOING_TO_SLEEP 261 * Indicates MAC is entering a power-saving sleep power-down. 262 * Not a good time to access device-internal resources. 263 * 3: MAC_ACCESS_REQ 264 * Host sets this to request and maintain MAC wakeup, to allow host 265 * access to device-internal resources. Host must wait for 266 * MAC_CLOCK_READY (and !GOING_TO_SLEEP) before accessing non-CSR 267 * device registers. 268 * 2: INIT_DONE 269 * Host sets this to put device into fully operational D0 power mode. 270 * Host resets this after SW_RESET to put device into low power mode. 271 * 0: MAC_CLOCK_READY 272 * Indicates MAC (ucode processor, etc.) is powered up and can run. 273 * Internal resources are accessible. 274 * NOTE: This does not indicate that the processor is actually running. 275 * NOTE: This does not indicate that device has completed 276 * init or post-power-down restore of internal SRAM memory. 277 * Use IWM_CSR_UCODE_DRV_GP1_BIT_MAC_SLEEP as indication that 278 * SRAM is restored and uCode is in normal operation mode. 279 * Later devices (5xxx/6xxx/1xxx) use non-volatile SRAM, and 280 * do not need to save/restore it. 281 * NOTE: After device reset, this bit remains "0" until host sets 282 * INIT_DONE 283 */ 284 #define IWM_CSR_GP_CNTRL_REG_FLAG_MAC_CLOCK_READY (0x00000001) 285 #define IWM_CSR_GP_CNTRL_REG_FLAG_INIT_DONE (0x00000004) 286 #define IWM_CSR_GP_CNTRL_REG_FLAG_MAC_ACCESS_REQ (0x00000008) 287 #define IWM_CSR_GP_CNTRL_REG_FLAG_GOING_TO_SLEEP (0x00000010) 288 289 #define IWM_CSR_GP_CNTRL_REG_VAL_MAC_ACCESS_EN (0x00000001) 290 291 #define IWM_CSR_GP_CNTRL_REG_MSK_POWER_SAVE_TYPE (0x07000000) 292 #define IWM_CSR_GP_CNTRL_REG_FLAG_MAC_POWER_SAVE (0x04000000) 293 #define IWM_CSR_GP_CNTRL_REG_FLAG_HW_RF_KILL_SW (0x08000000) 294 295 296 /* HW REV */ 297 #define IWM_CSR_HW_REV_DASH(_val) (((_val) & 0x0000003) >> 0) 298 #define IWM_CSR_HW_REV_STEP(_val) (((_val) & 0x000000C) >> 2) 299 300 #define IWM_CSR_HW_REV_TYPE_MSK (0x000FFF0) 301 #define IWM_CSR_HW_REV_TYPE_5300 (0x0000020) 302 #define IWM_CSR_HW_REV_TYPE_5350 (0x0000030) 303 #define IWM_CSR_HW_REV_TYPE_5100 (0x0000050) 304 #define IWM_CSR_HW_REV_TYPE_5150 (0x0000040) 305 #define IWM_CSR_HW_REV_TYPE_1000 (0x0000060) 306 #define IWM_CSR_HW_REV_TYPE_6x00 (0x0000070) 307 #define IWM_CSR_HW_REV_TYPE_6x50 (0x0000080) 308 #define IWM_CSR_HW_REV_TYPE_6150 (0x0000084) 309 #define IWM_CSR_HW_REV_TYPE_6x05 (0x00000B0) 310 #define IWM_CSR_HW_REV_TYPE_6x30 IWM_CSR_HW_REV_TYPE_6x05 311 #define IWM_CSR_HW_REV_TYPE_6x35 IWM_CSR_HW_REV_TYPE_6x05 312 #define IWM_CSR_HW_REV_TYPE_2x30 (0x00000C0) 313 #define IWM_CSR_HW_REV_TYPE_2x00 (0x0000100) 314 #define IWM_CSR_HW_REV_TYPE_105 (0x0000110) 315 #define IWM_CSR_HW_REV_TYPE_135 (0x0000120) 316 #define IWM_CSR_HW_REV_TYPE_7265D (0x0000210) 317 #define IWM_CSR_HW_REV_TYPE_NONE (0x00001F0) 318 319 /* EEPROM REG */ 320 #define IWM_CSR_EEPROM_REG_READ_VALID_MSK (0x00000001) 321 #define IWM_CSR_EEPROM_REG_BIT_CMD (0x00000002) 322 #define IWM_CSR_EEPROM_REG_MSK_ADDR (0x0000FFFC) 323 #define IWM_CSR_EEPROM_REG_MSK_DATA (0xFFFF0000) 324 325 /* EEPROM GP */ 326 #define IWM_CSR_EEPROM_GP_VALID_MSK (0x00000007) /* signature */ 327 #define IWM_CSR_EEPROM_GP_IF_OWNER_MSK (0x00000180) 328 #define IWM_CSR_EEPROM_GP_BAD_SIGNATURE_BOTH_EEP_AND_OTP (0x00000000) 329 #define IWM_CSR_EEPROM_GP_BAD_SIG_EEP_GOOD_SIG_OTP (0x00000001) 330 #define IWM_CSR_EEPROM_GP_GOOD_SIG_EEP_LESS_THAN_4K (0x00000002) 331 #define IWM_CSR_EEPROM_GP_GOOD_SIG_EEP_MORE_THAN_4K (0x00000004) 332 333 /* One-time-programmable memory general purpose reg */ 334 #define IWM_CSR_OTP_GP_REG_DEVICE_SELECT (0x00010000) /* 0 - EEPROM, 1 - OTP */ 335 #define IWM_CSR_OTP_GP_REG_OTP_ACCESS_MODE (0x00020000) /* 0 - absolute, 1 - relative */ 336 #define IWM_CSR_OTP_GP_REG_ECC_CORR_STATUS_MSK (0x00100000) /* bit 20 */ 337 #define IWM_CSR_OTP_GP_REG_ECC_UNCORR_STATUS_MSK (0x00200000) /* bit 21 */ 338 339 /* GP REG */ 340 #define IWM_CSR_GP_REG_POWER_SAVE_STATUS_MSK (0x03000000) /* bit 24/25 */ 341 #define IWM_CSR_GP_REG_NO_POWER_SAVE (0x00000000) 342 #define IWM_CSR_GP_REG_MAC_POWER_SAVE (0x01000000) 343 #define IWM_CSR_GP_REG_PHY_POWER_SAVE (0x02000000) 344 #define IWM_CSR_GP_REG_POWER_SAVE_ERROR (0x03000000) 345 346 347 /* CSR GIO */ 348 #define IWM_CSR_GIO_REG_VAL_L0S_ENABLED (0x00000002) 349 350 /* 351 * UCODE-DRIVER GP (general purpose) mailbox register 1 352 * Host driver and uCode write and/or read this register to communicate with 353 * each other. 354 * Bit fields: 355 * 4: UCODE_DISABLE 356 * Host sets this to request permanent halt of uCode, same as 357 * sending CARD_STATE command with "halt" bit set. 358 * 3: CT_KILL_EXIT 359 * Host sets this to request exit from CT_KILL state, i.e. host thinks 360 * device temperature is low enough to continue normal operation. 361 * 2: CMD_BLOCKED 362 * Host sets this during RF KILL power-down sequence (HW, SW, CT KILL) 363 * to release uCode to clear all Tx and command queues, enter 364 * unassociated mode, and power down. 365 * NOTE: Some devices also use HBUS_TARG_MBX_C register for this bit. 366 * 1: SW_BIT_RFKILL 367 * Host sets this when issuing CARD_STATE command to request 368 * device sleep. 369 * 0: MAC_SLEEP 370 * uCode sets this when preparing a power-saving power-down. 371 * uCode resets this when power-up is complete and SRAM is sane. 372 * NOTE: device saves internal SRAM data to host when powering down, 373 * and must restore this data after powering back up. 374 * MAC_SLEEP is the best indication that restore is complete. 375 * Later devices (5xxx/6xxx/1xxx) use non-volatile SRAM, and 376 * do not need to save/restore it. 377 */ 378 #define IWM_CSR_UCODE_DRV_GP1_BIT_MAC_SLEEP (0x00000001) 379 #define IWM_CSR_UCODE_SW_BIT_RFKILL (0x00000002) 380 #define IWM_CSR_UCODE_DRV_GP1_BIT_CMD_BLOCKED (0x00000004) 381 #define IWM_CSR_UCODE_DRV_GP1_REG_BIT_CT_KILL_EXIT (0x00000008) 382 #define IWM_CSR_UCODE_DRV_GP1_BIT_D3_CFG_COMPLETE (0x00000020) 383 384 /* GP Driver */ 385 #define IWM_CSR_GP_DRIVER_REG_BIT_RADIO_SKU_MSK (0x00000003) 386 #define IWM_CSR_GP_DRIVER_REG_BIT_RADIO_SKU_3x3_HYB (0x00000000) 387 #define IWM_CSR_GP_DRIVER_REG_BIT_RADIO_SKU_2x2_HYB (0x00000001) 388 #define IWM_CSR_GP_DRIVER_REG_BIT_RADIO_SKU_2x2_IPA (0x00000002) 389 #define IWM_CSR_GP_DRIVER_REG_BIT_CALIB_VERSION6 (0x00000004) 390 #define IWM_CSR_GP_DRIVER_REG_BIT_6050_1x2 (0x00000008) 391 392 #define IWM_CSR_GP_DRIVER_REG_BIT_RADIO_IQ_INVER (0x00000080) 393 394 /* GIO Chicken Bits (PCI Express bus link power management) */ 395 #define IWM_CSR_GIO_CHICKEN_BITS_REG_BIT_L1A_NO_L0S_RX (0x00800000) 396 #define IWM_CSR_GIO_CHICKEN_BITS_REG_BIT_DIS_L0S_EXIT_TIMER (0x20000000) 397 398 /* LED */ 399 #define IWM_CSR_LED_BSM_CTRL_MSK (0xFFFFFFDF) 400 #define IWM_CSR_LED_REG_TURN_ON (0x60) 401 #define IWM_CSR_LED_REG_TURN_OFF (0x20) 402 403 /* ANA_PLL */ 404 #define IWM_CSR50_ANA_PLL_CFG_VAL (0x00880300) 405 406 /* HPET MEM debug */ 407 #define IWM_CSR_DBG_HPET_MEM_REG_VAL (0xFFFF0000) 408 409 /* DRAM INT TABLE */ 410 #define IWM_CSR_DRAM_INT_TBL_ENABLE (1 << 31) 411 #define IWM_CSR_DRAM_INIT_TBL_WRITE_POINTER (1 << 28) 412 #define IWM_CSR_DRAM_INIT_TBL_WRAP_CHECK (1 << 27) 413 414 /* SECURE boot registers */ 415 #define IWM_CSR_SECURE_BOOT_CONFIG_ADDR (0x100) 416 enum iwm_secure_boot_config_reg { 417 IWM_CSR_SECURE_BOOT_CONFIG_INSPECTOR_BURNED_IN_OTP = 0x00000001, 418 IWM_CSR_SECURE_BOOT_CONFIG_INSPECTOR_NOT_REQ = 0x00000002, 419 }; 420 421 #define IWM_CSR_SECURE_BOOT_CPU1_STATUS_ADDR (0x100) 422 #define IWM_CSR_SECURE_BOOT_CPU2_STATUS_ADDR (0x100) 423 enum iwm_secure_boot_status_reg { 424 IWM_CSR_SECURE_BOOT_CPU_STATUS_VERF_STATUS = 0x00000003, 425 IWM_CSR_SECURE_BOOT_CPU_STATUS_VERF_COMPLETED = 0x00000002, 426 IWM_CSR_SECURE_BOOT_CPU_STATUS_VERF_SUCCESS = 0x00000004, 427 IWM_CSR_SECURE_BOOT_CPU_STATUS_VERF_FAIL = 0x00000008, 428 IWM_CSR_SECURE_BOOT_CPU_STATUS_SIGN_VERF_FAIL = 0x00000010, 429 }; 430 431 #define IWM_FH_UCODE_LOAD_STATUS 0x1af0 432 #define IWM_CSR_UCODE_LOAD_STATUS_ADDR 0x1e70 433 enum iwm_secure_load_status_reg { 434 IWM_LMPM_CPU_UCODE_LOADING_STARTED = 0x00000001, 435 IWM_LMPM_CPU_HDRS_LOADING_COMPLETED = 0x00000003, 436 IWM_LMPM_CPU_UCODE_LOADING_COMPLETED = 0x00000007, 437 IWM_LMPM_CPU_STATUS_NUM_OF_LAST_COMPLETED = 0x000000F8, 438 IWM_LMPM_CPU_STATUS_NUM_OF_LAST_LOADED_BLOCK = 0x0000FF00, 439 }; 440 #define IWM_FH_MEM_TB_MAX_LENGTH 0x20000 441 442 #define IWM_LMPM_SECURE_INSPECTOR_CODE_ADDR 0x1e38 443 #define IWM_LMPM_SECURE_INSPECTOR_DATA_ADDR 0x1e3c 444 #define IWM_LMPM_SECURE_UCODE_LOAD_CPU1_HDR_ADDR 0x1e78 445 #define IWM_LMPM_SECURE_UCODE_LOAD_CPU2_HDR_ADDR 0x1e7c 446 447 #define IWM_LMPM_SECURE_INSPECTOR_CODE_MEM_SPACE 0x400000 448 #define IWM_LMPM_SECURE_INSPECTOR_DATA_MEM_SPACE 0x402000 449 #define IWM_LMPM_SECURE_CPU1_HDR_MEM_SPACE 0x420000 450 #define IWM_LMPM_SECURE_CPU2_HDR_MEM_SPACE 0x420400 451 452 #define IWM_CSR_SECURE_TIME_OUT (100) 453 454 /* extended range in FW SRAM */ 455 #define IWM_FW_MEM_EXTENDED_START 0x40000 456 #define IWM_FW_MEM_EXTENDED_END 0x57FFF 457 458 /* FW chicken bits */ 459 #define IWM_LMPM_CHICK 0xa01ff8 460 #define IWM_LMPM_CHICK_EXTENDED_ADDR_SPACE 0x01 461 462 #define IWM_FH_TCSR_0_REG0 (0x1D00) 463 464 /* 465 * HBUS (Host-side Bus) 466 * 467 * HBUS registers are mapped directly into PCI bus space, but are used 468 * to indirectly access device's internal memory or registers that 469 * may be powered-down. 470 * 471 * Use iwl_write_direct32()/iwl_read_direct32() family for these registers; 472 * host must "grab nic access" via CSR_GP_CNTRL_REG_FLAG_MAC_ACCESS_REQ 473 * to make sure the MAC (uCode processor, etc.) is powered up for accessing 474 * internal resources. 475 * 476 * Do not use iwl_write32()/iwl_read32() family to access these registers; 477 * these provide only simple PCI bus access, without waking up the MAC. 478 */ 479 #define IWM_HBUS_BASE (0x400) 480 481 /* 482 * Registers for accessing device's internal SRAM memory (e.g. SCD SRAM 483 * structures, error log, event log, verifying uCode load). 484 * First write to address register, then read from or write to data register 485 * to complete the job. Once the address register is set up, accesses to 486 * data registers auto-increment the address by one dword. 487 * Bit usage for address registers (read or write): 488 * 0-31: memory address within device 489 */ 490 #define IWM_HBUS_TARG_MEM_RADDR (IWM_HBUS_BASE+0x00c) 491 #define IWM_HBUS_TARG_MEM_WADDR (IWM_HBUS_BASE+0x010) 492 #define IWM_HBUS_TARG_MEM_WDAT (IWM_HBUS_BASE+0x018) 493 #define IWM_HBUS_TARG_MEM_RDAT (IWM_HBUS_BASE+0x01c) 494 495 /* Mailbox C, used as workaround alternative to CSR_UCODE_DRV_GP1 mailbox */ 496 #define IWM_HBUS_TARG_MBX_C (IWM_HBUS_BASE+0x030) 497 #define IWM_HBUS_TARG_MBX_C_REG_BIT_CMD_BLOCKED (0x00000004) 498 499 /* 500 * Registers for accessing device's internal peripheral registers 501 * (e.g. SCD, BSM, etc.). First write to address register, 502 * then read from or write to data register to complete the job. 503 * Bit usage for address registers (read or write): 504 * 0-15: register address (offset) within device 505 * 24-25: (# bytes - 1) to read or write (e.g. 3 for dword) 506 */ 507 #define IWM_HBUS_TARG_PRPH_WADDR (IWM_HBUS_BASE+0x044) 508 #define IWM_HBUS_TARG_PRPH_RADDR (IWM_HBUS_BASE+0x048) 509 #define IWM_HBUS_TARG_PRPH_WDAT (IWM_HBUS_BASE+0x04c) 510 #define IWM_HBUS_TARG_PRPH_RDAT (IWM_HBUS_BASE+0x050) 511 512 /* enable the ID buf for read */ 513 #define IWM_WFPM_PS_CTL_CLR 0xa0300c 514 #define IWM_WFMP_MAC_ADDR_0 0xa03080 515 #define IWM_WFMP_MAC_ADDR_1 0xa03084 516 #define IWM_LMPM_PMG_EN 0xa01cec 517 #define IWM_RADIO_REG_SYS_MANUAL_DFT_0 0xad4078 518 #define IWM_RFIC_REG_RD 0xad0470 519 #define IWM_WFPM_CTRL_REG 0xa03030 520 #define IWM_WFPM_AUX_CTL_AUX_IF_MAC_OWNER_MSK 0x08000000 521 #define IWM_ENABLE_WFPM 0x80000000 522 523 #define IWM_AUX_MISC_REG 0xa200b0 524 #define IWM_HW_STEP_LOCATION_BITS 24 525 526 #define IWM_AUX_MISC_MASTER1_EN 0xa20818 527 #define IWM_AUX_MISC_MASTER1_EN_SBE_MSK 0x1 528 #define IWM_AUX_MISC_MASTER1_SMPHR_STATUS 0xa20800 529 #define IWM_RSA_ENABLE 0xa24b08 530 #define IWM_PREG_AUX_BUS_WPROT_0 0xa04cc0 531 #define IWM_SB_CFG_OVERRIDE_ADDR 0xa26c78 532 #define IWM_SB_CFG_OVERRIDE_ENABLE 0x8000 533 #define IWM_SB_CFG_BASE_OVERRIDE 0xa20000 534 #define IWM_SB_MODIFY_CFG_FLAG 0xa03088 535 #define IWM_SB_CPU_1_STATUS 0xa01e30 536 #define IWM_SB_CPU_2_STATUS 0Xa01e34 537 538 /* Used to enable DBGM */ 539 #define IWM_HBUS_TARG_TEST_REG (IWM_HBUS_BASE+0x05c) 540 541 /* 542 * Per-Tx-queue write pointer (index, really!) 543 * Indicates index to next TFD that driver will fill (1 past latest filled). 544 * Bit usage: 545 * 0-7: queue write index 546 * 11-8: queue selector 547 */ 548 #define IWM_HBUS_TARG_WRPTR (IWM_HBUS_BASE+0x060) 549 550 /********************************************************** 551 * CSR values 552 **********************************************************/ 553 /* 554 * host interrupt timeout value 555 * used with setting interrupt coalescing timer 556 * the CSR_INT_COALESCING is an 8 bit register in 32-usec unit 557 * 558 * default interrupt coalescing timer is 64 x 32 = 2048 usecs 559 */ 560 #define IWM_HOST_INT_TIMEOUT_MAX (0xFF) 561 #define IWM_HOST_INT_TIMEOUT_DEF (0x40) 562 #define IWM_HOST_INT_TIMEOUT_MIN (0x0) 563 #define IWM_HOST_INT_OPER_MODE (1 << 31) 564 565 /***************************************************************************** 566 * 7000/3000 series SHR DTS addresses * 567 *****************************************************************************/ 568 569 /* Diode Results Register Structure: */ 570 enum iwm_dtd_diode_reg { 571 IWM_DTS_DIODE_REG_DIG_VAL = 0x000000FF, /* bits [7:0] */ 572 IWM_DTS_DIODE_REG_VREF_LOW = 0x0000FF00, /* bits [15:8] */ 573 IWM_DTS_DIODE_REG_VREF_HIGH = 0x00FF0000, /* bits [23:16] */ 574 IWM_DTS_DIODE_REG_VREF_ID = 0x03000000, /* bits [25:24] */ 575 IWM_DTS_DIODE_REG_PASS_ONCE = 0x80000000, /* bits [31:31] */ 576 IWM_DTS_DIODE_REG_FLAGS_MSK = 0xFF000000, /* bits [31:24] */ 577 /* Those are the masks INSIDE the flags bit-field: */ 578 IWM_DTS_DIODE_REG_FLAGS_VREFS_ID_POS = 0, 579 IWM_DTS_DIODE_REG_FLAGS_VREFS_ID = 0x00000003, /* bits [1:0] */ 580 IWM_DTS_DIODE_REG_FLAGS_PASS_ONCE_POS = 7, 581 IWM_DTS_DIODE_REG_FLAGS_PASS_ONCE = 0x00000080, /* bits [7:7] */ 582 }; 583 584 /* 585 * END iwl-csr.h 586 */ 587 588 /* 589 * BEGIN iwl-fw.h 590 */ 591 592 /** 593 * enum iwm_ucode_tlv_flag - ucode API flags 594 * @IWM_UCODE_TLV_FLAGS_PAN: This is PAN capable microcode; this previously 595 * was a separate TLV but moved here to save space. 596 * @IWM_UCODE_TLV_FLAGS_NEWSCAN: new uCode scan behaviour on hidden SSID, 597 * treats good CRC threshold as a boolean 598 * @IWM_UCODE_TLV_FLAGS_MFP: This uCode image supports MFP (802.11w). 599 * @IWM_UCODE_TLV_FLAGS_P2P: This uCode image supports P2P. 600 * @IWM_UCODE_TLV_FLAGS_DW_BC_TABLE: The SCD byte count table is in DWORDS 601 * @IWM_UCODE_TLV_FLAGS_UAPSD: This uCode image supports uAPSD 602 * @IWM_UCODE_TLV_FLAGS_SHORT_BL: 16 entries of black list instead of 64 in scan 603 * offload profile config command. 604 * @IWM_UCODE_TLV_FLAGS_RX_ENERGY_API: supports rx signal strength api 605 * @IWM_UCODE_TLV_FLAGS_TIME_EVENT_API_V2: using the new time event API. 606 * @IWM_UCODE_TLV_FLAGS_D3_6_IPV6_ADDRS: D3 image supports up to six 607 * (rather than two) IPv6 addresses 608 * @IWM_UCODE_TLV_FLAGS_BF_UPDATED: new beacon filtering API 609 * @IWM_UCODE_TLV_FLAGS_NO_BASIC_SSID: not sending a probe with the SSID element 610 * from the probe request template. 611 * @IWM_UCODE_TLV_FLAGS_D3_CONTINUITY_API: modified D3 API to allow keeping 612 * connection when going back to D0 613 * @IWM_UCODE_TLV_FLAGS_NEW_NSOFFL_SMALL: new NS offload (small version) 614 * @IWM_UCODE_TLV_FLAGS_NEW_NSOFFL_LARGE: new NS offload (large version) 615 * @IWM_UCODE_TLV_FLAGS_SCHED_SCAN: this uCode image supports scheduled scan. 616 * @IWM_UCODE_TLV_FLAGS_STA_KEY_CMD: new ADD_STA and ADD_STA_KEY command API 617 * @IWM_UCODE_TLV_FLAGS_DEVICE_PS_CMD: support device wide power command 618 * containing CAM (Continuous Active Mode) indication. 619 * @IWM_UCODE_TLV_FLAGS_P2P_PS: P2P client power save is supported (only on a 620 * single bound interface). 621 * @IWM_UCODE_TLV_FLAGS_UAPSD_SUPPORT: General support for uAPSD 622 * @IWM_UCODE_TLV_FLAGS_EBS_SUPPORT: this uCode image supports EBS. 623 * @IWM_UCODE_TLV_FLAGS_P2P_PS_UAPSD: P2P client supports uAPSD power save 624 * @IWM_UCODE_TLV_FLAGS_BCAST_FILTERING: uCode supports broadcast filtering. 625 * @IWM_UCODE_TLV_FLAGS_GO_UAPSD: AP/GO interfaces support uAPSD clients 626 * 627 */ 628 enum iwm_ucode_tlv_flag { 629 IWM_UCODE_TLV_FLAGS_PAN = (1 << 0), 630 IWM_UCODE_TLV_FLAGS_NEWSCAN = (1 << 1), 631 IWM_UCODE_TLV_FLAGS_MFP = (1 << 2), 632 IWM_UCODE_TLV_FLAGS_P2P = (1 << 3), 633 IWM_UCODE_TLV_FLAGS_DW_BC_TABLE = (1 << 4), 634 IWM_UCODE_TLV_FLAGS_NEWBT_COEX = (1 << 5), 635 IWM_UCODE_TLV_FLAGS_PM_CMD_SUPPORT = (1 << 6), 636 IWM_UCODE_TLV_FLAGS_SHORT_BL = (1 << 7), 637 IWM_UCODE_TLV_FLAGS_RX_ENERGY_API = (1 << 8), 638 IWM_UCODE_TLV_FLAGS_TIME_EVENT_API_V2 = (1 << 9), 639 IWM_UCODE_TLV_FLAGS_D3_6_IPV6_ADDRS = (1 << 10), 640 IWM_UCODE_TLV_FLAGS_BF_UPDATED = (1 << 11), 641 IWM_UCODE_TLV_FLAGS_NO_BASIC_SSID = (1 << 12), 642 IWM_UCODE_TLV_FLAGS_D3_CONTINUITY_API = (1 << 14), 643 IWM_UCODE_TLV_FLAGS_NEW_NSOFFL_SMALL = (1 << 15), 644 IWM_UCODE_TLV_FLAGS_NEW_NSOFFL_LARGE = (1 << 16), 645 IWM_UCODE_TLV_FLAGS_SCHED_SCAN = (1 << 17), 646 IWM_UCODE_TLV_FLAGS_STA_KEY_CMD = (1 << 19), 647 IWM_UCODE_TLV_FLAGS_DEVICE_PS_CMD = (1 << 20), 648 IWM_UCODE_TLV_FLAGS_P2P_PS = (1 << 21), 649 IWM_UCODE_TLV_FLAGS_BSS_P2P_PS_DCM = (1 << 22), 650 IWM_UCODE_TLV_FLAGS_BSS_P2P_PS_SCM = (1 << 23), 651 IWM_UCODE_TLV_FLAGS_UAPSD_SUPPORT = (1 << 24), 652 IWM_UCODE_TLV_FLAGS_EBS_SUPPORT = (1 << 25), 653 IWM_UCODE_TLV_FLAGS_P2P_PS_UAPSD = (1 << 26), 654 IWM_UCODE_TLV_FLAGS_BCAST_FILTERING = (1 << 29), 655 IWM_UCODE_TLV_FLAGS_GO_UAPSD = (1 << 30), 656 IWM_UCODE_TLV_FLAGS_LTE_COEX = (1 << 31), 657 }; 658 659 #define IWM_UCODE_TLV_FLAG_BITS \ 660 "\020\1PAN\2NEWSCAN\3MFP\4P2P\5DW_BC_TABLE\6NEWBT_COEX\7PM_CMD\10SHORT_BL\11RX_ENERG \ 661 Y\12TIME_EVENT_V2\13D3_6_IPV6\14BF_UPDATED\15NO_BASIC_SSID\17D3_CONTINUITY\20NEW_NSOFF \ 662 L_S\21NEW_NSOFFL_L\22SCHED_SCAN\24STA_KEY_CMD\25DEVICE_PS_CMD\26P2P_PS\27P2P_PS_DCM\30 \ 663 P2P_PS_SCM\31UAPSD_SUPPORT\32EBS\33P2P_PS_UAPSD\36BCAST_FILTERING\37GO_UAPSD\40LTE_COEX" 664 665 /** 666 * enum iwm_ucode_tlv_api - ucode api 667 * @IWM_UCODE_TLV_API_FRAGMENTED_SCAN: This ucode supports active dwell time 668 * longer than the passive one, which is essential for fragmented scan. 669 * @IWM_UCODE_TLV_API_WIFI_MCC_UPDATE: ucode supports MCC updates with source. 670 * @IWM_UCODE_TLV_API_WIDE_CMD_HDR: ucode supports wide command header 671 * @IWM_UCODE_TLV_API_LQ_SS_PARAMS: Configure STBC/BFER via LQ CMD ss_params 672 * @IWM_UCODE_TLV_API_EXT_SCAN_PRIORITY: scan APIs use 8-level priority 673 * instead of 3. 674 * @IWM_UCODE_TLV_API_TX_POWER_CHAIN: TX power API has larger command size 675 * (command version 3) that supports per-chain limits 676 * 677 * @IWM_NUM_UCODE_TLV_API: number of bits used 678 */ 679 enum iwm_ucode_tlv_api { 680 IWM_UCODE_TLV_API_FRAGMENTED_SCAN = (1 << 8), 681 IWM_UCODE_TLV_API_WIFI_MCC_UPDATE = (1 << 9), 682 IWM_UCODE_TLV_API_WIDE_CMD_HDR = (1 << 14), 683 IWM_UCODE_TLV_API_LQ_SS_PARAMS = (1 << 18), 684 IWM_UCODE_TLV_API_EXT_SCAN_PRIORITY = (1 << 24), 685 IWM_UCODE_TLV_API_TX_POWER_CHAIN = (1 << 27), 686 687 IWM_NUM_UCODE_TLV_API = 32 688 }; 689 690 #define IWM_UCODE_TLV_API_BITS \ 691 "\020\10FRAGMENTED_SCAN\11WIFI_MCC_UPDATE\16WIDE_CMD_HDR\22LQ_SS_PARAMS\30EXT_SCAN_PRIO\33TX_POWER_CHAIN" 692 693 /** 694 * enum iwm_ucode_tlv_capa - ucode capabilities 695 * @IWM_UCODE_TLV_CAPA_D0I3_SUPPORT: supports D0i3 696 * @IWM_UCODE_TLV_CAPA_LAR_SUPPORT: supports Location Aware Regulatory 697 * @IWM_UCODE_TLV_CAPA_UMAC_SCAN: supports UMAC scan. 698 * @IWM_UCODE_TLV_CAPA_BEAMFORMER: supports Beamformer 699 * @IWM_UCODE_TLV_CAPA_TOF_SUPPORT: supports Time of Flight (802.11mc FTM) 700 * @IWM_UCODE_TLV_CAPA_TDLS_SUPPORT: support basic TDLS functionality 701 * @IWM_UCODE_TLV_CAPA_TXPOWER_INSERTION_SUPPORT: supports insertion of current 702 * tx power value into TPC Report action frame and Link Measurement Report 703 * action frame 704 * @IWM_UCODE_TLV_CAPA_DS_PARAM_SET_IE_SUPPORT: supports updating current 705 * channel in DS parameter set element in probe requests. 706 * @IWM_UCODE_TLV_CAPA_WFA_TPC_REP_IE_SUPPORT: supports adding TPC Report IE in 707 * probe requests. 708 * @IWM_UCODE_TLV_CAPA_QUIET_PERIOD_SUPPORT: supports Quiet Period requests 709 * @IWM_UCODE_TLV_CAPA_DQA_SUPPORT: supports dynamic queue allocation (DQA), 710 * which also implies support for the scheduler configuration command 711 * @IWM_UCODE_TLV_CAPA_TDLS_CHANNEL_SWITCH: supports TDLS channel switching 712 * @IWM_UCODE_TLV_CAPA_CNSLDTD_D3_D0_IMG: Consolidated D3-D0 image 713 * @IWM_UCODE_TLV_CAPA_HOTSPOT_SUPPORT: supports Hot Spot Command 714 * @IWM_UCODE_TLV_CAPA_DC2DC_SUPPORT: supports DC2DC Command 715 * @IWM_UCODE_TLV_CAPA_2G_COEX_SUPPORT: supports 2G coex Command 716 * @IWM_UCODE_TLV_CAPA_CSUM_SUPPORT: supports TCP Checksum Offload 717 * @IWM_UCODE_TLV_CAPA_RADIO_BEACON_STATS: support radio and beacon statistics 718 * @IWM_UCODE_TLV_CAPA_P2P_STANDALONE_UAPSD: support p2p standalone U-APSD 719 * @IWM_UCODE_TLV_CAPA_BT_COEX_PLCR: enabled BT Coex packet level co-running 720 * @IWM_UCODE_TLV_CAPA_LAR_MULTI_MCC: ucode supports LAR updates with different 721 * sources for the MCC. This TLV bit is a future replacement to 722 * IWM_UCODE_TLV_API_WIFI_MCC_UPDATE. When either is set, multi-source LAR 723 * is supported. 724 * @IWM_UCODE_TLV_CAPA_BT_COEX_RRC: supports BT Coex RRC 725 * @IWM_UCODE_TLV_CAPA_GSCAN_SUPPORT: supports gscan 726 * @IWM_UCODE_TLV_CAPA_NAN_SUPPORT: supports NAN 727 * @IWM_UCODE_TLV_CAPA_UMAC_UPLOAD: supports upload mode in umac (1=supported, 728 * 0=no support) 729 * @IWM_UCODE_TLV_CAPA_EXTENDED_DTS_MEASURE: extended DTS measurement 730 * @IWM_UCODE_TLV_CAPA_SHORT_PM_TIMEOUTS: supports short PM timeouts 731 * @IWM_UCODE_TLV_CAPA_BT_MPLUT_SUPPORT: supports bt-coex Multi-priority LUT 732 * @IWM_UCODE_TLV_CAPA_BEACON_ANT_SELECTION: firmware will decide on what 733 * antenna the beacon should be transmitted 734 * @IWM_UCODE_TLV_CAPA_BEACON_STORING: firmware will store the latest beacon 735 * from AP and will send it upon d0i3 exit. 736 * @IWM_UCODE_TLV_CAPA_LAR_SUPPORT_V2: support LAR API V2 737 * @IWM_UCODE_TLV_CAPA_CT_KILL_BY_FW: firmware responsible for CT-kill 738 * @IWM_UCODE_TLV_CAPA_TEMP_THS_REPORT_SUPPORT: supports temperature 739 * thresholds reporting 740 * @IWM_UCODE_TLV_CAPA_CTDP_SUPPORT: supports cTDP command 741 * @IWM_UCODE_TLV_CAPA_USNIFFER_UNIFIED: supports usniffer enabled in 742 * regular image. 743 * @IWM_UCODE_TLV_CAPA_EXTEND_SHARED_MEM_CFG: support getting more shared 744 * memory addresses from the firmware. 745 * @IWM_UCODE_TLV_CAPA_LQM_SUPPORT: supports Link Quality Measurement 746 * @IWM_UCODE_TLV_CAPA_LMAC_UPLOAD: supports upload mode in lmac (1=supported, 747 * 0=no support) 748 * 749 * @IWM_NUM_UCODE_TLV_CAPA: number of bits used 750 */ 751 enum iwm_ucode_tlv_capa { 752 IWM_UCODE_TLV_CAPA_D0I3_SUPPORT = 0, 753 IWM_UCODE_TLV_CAPA_LAR_SUPPORT = 1, 754 IWM_UCODE_TLV_CAPA_UMAC_SCAN = 2, 755 IWM_UCODE_TLV_CAPA_BEAMFORMER = 3, 756 IWM_UCODE_TLV_CAPA_TOF_SUPPORT = 5, 757 IWM_UCODE_TLV_CAPA_TDLS_SUPPORT = 6, 758 IWM_UCODE_TLV_CAPA_TXPOWER_INSERTION_SUPPORT = 8, 759 IWM_UCODE_TLV_CAPA_DS_PARAM_SET_IE_SUPPORT = 9, 760 IWM_UCODE_TLV_CAPA_WFA_TPC_REP_IE_SUPPORT = 10, 761 IWM_UCODE_TLV_CAPA_QUIET_PERIOD_SUPPORT = 11, 762 IWM_UCODE_TLV_CAPA_DQA_SUPPORT = 12, 763 IWM_UCODE_TLV_CAPA_TDLS_CHANNEL_SWITCH = 13, 764 IWM_UCODE_TLV_CAPA_CNSLDTD_D3_D0_IMG = 17, 765 IWM_UCODE_TLV_CAPA_HOTSPOT_SUPPORT = 18, 766 IWM_UCODE_TLV_CAPA_DC2DC_CONFIG_SUPPORT = 19, 767 IWM_UCODE_TLV_CAPA_2G_COEX_SUPPORT = 20, 768 IWM_UCODE_TLV_CAPA_CSUM_SUPPORT = 21, 769 IWM_UCODE_TLV_CAPA_RADIO_BEACON_STATS = 22, 770 IWM_UCODE_TLV_CAPA_P2P_STANDALONE_UAPSD = 26, 771 IWM_UCODE_TLV_CAPA_BT_COEX_PLCR = 28, 772 IWM_UCODE_TLV_CAPA_LAR_MULTI_MCC = 29, 773 IWM_UCODE_TLV_CAPA_BT_COEX_RRC = 30, 774 IWM_UCODE_TLV_CAPA_GSCAN_SUPPORT = 31, 775 IWM_UCODE_TLV_CAPA_NAN_SUPPORT = 34, 776 IWM_UCODE_TLV_CAPA_UMAC_UPLOAD = 35, 777 IWM_UCODE_TLV_CAPA_EXTENDED_DTS_MEASURE = 64, 778 IWM_UCODE_TLV_CAPA_SHORT_PM_TIMEOUTS = 65, 779 IWM_UCODE_TLV_CAPA_BT_MPLUT_SUPPORT = 67, 780 IWM_UCODE_TLV_CAPA_MULTI_QUEUE_RX_SUPPORT = 68, 781 IWM_UCODE_TLV_CAPA_BEACON_ANT_SELECTION = 71, 782 IWM_UCODE_TLV_CAPA_BEACON_STORING = 72, 783 IWM_UCODE_TLV_CAPA_LAR_SUPPORT_V2 = 73, 784 IWM_UCODE_TLV_CAPA_CT_KILL_BY_FW = 74, 785 IWM_UCODE_TLV_CAPA_TEMP_THS_REPORT_SUPPORT = 75, 786 IWM_UCODE_TLV_CAPA_CTDP_SUPPORT = 76, 787 IWM_UCODE_TLV_CAPA_USNIFFER_UNIFIED = 77, 788 IWM_UCODE_TLV_CAPA_LMAC_UPLOAD = 79, 789 IWM_UCODE_TLV_CAPA_EXTEND_SHARED_MEM_CFG = 80, 790 IWM_UCODE_TLV_CAPA_LQM_SUPPORT = 81, 791 792 IWM_NUM_UCODE_TLV_CAPA = 128 793 }; 794 795 /* The default calibrate table size if not specified by firmware file */ 796 #define IWM_DEFAULT_STANDARD_PHY_CALIBRATE_TBL_SIZE 18 797 #define IWM_MAX_STANDARD_PHY_CALIBRATE_TBL_SIZE 19 798 #define IWM_MAX_PHY_CALIBRATE_TBL_SIZE 253 799 800 /* The default max probe length if not specified by the firmware file */ 801 #define IWM_DEFAULT_MAX_PROBE_LENGTH 200 802 803 /* 804 * enumeration of ucode section. 805 * This enumeration is used directly for older firmware (before 16.0). 806 * For new firmware, there can be up to 4 sections (see below) but the 807 * first one packaged into the firmware file is the DATA section and 808 * some debugging code accesses that. 809 */ 810 enum iwm_ucode_sec { 811 IWM_UCODE_SECTION_DATA, 812 IWM_UCODE_SECTION_INST, 813 }; 814 /* 815 * For 16.0 uCode and above, there is no differentiation between sections, 816 * just an offset to the HW address. 817 */ 818 #define IWM_CPU1_CPU2_SEPARATOR_SECTION 0xFFFFCCCC 819 #define IWM_PAGING_SEPARATOR_SECTION 0xAAAABBBB 820 821 /* uCode version contains 4 values: Major/Minor/API/Serial */ 822 #define IWM_UCODE_MAJOR(ver) (((ver) & 0xFF000000) >> 24) 823 #define IWM_UCODE_MINOR(ver) (((ver) & 0x00FF0000) >> 16) 824 #define IWM_UCODE_API(ver) (((ver) & 0x0000FF00) >> 8) 825 #define IWM_UCODE_SERIAL(ver) ((ver) & 0x000000FF) 826 827 /* 828 * Calibration control struct. 829 * Sent as part of the phy configuration command. 830 * @flow_trigger: bitmap for which calibrations to perform according to 831 * flow triggers. 832 * @event_trigger: bitmap for which calibrations to perform according to 833 * event triggers. 834 */ 835 struct iwm_tlv_calib_ctrl { 836 uint32_t flow_trigger; 837 uint32_t event_trigger; 838 } __packed; 839 840 enum iwm_fw_phy_cfg { 841 IWM_FW_PHY_CFG_RADIO_TYPE_POS = 0, 842 IWM_FW_PHY_CFG_RADIO_TYPE = 0x3 << IWM_FW_PHY_CFG_RADIO_TYPE_POS, 843 IWM_FW_PHY_CFG_RADIO_STEP_POS = 2, 844 IWM_FW_PHY_CFG_RADIO_STEP = 0x3 << IWM_FW_PHY_CFG_RADIO_STEP_POS, 845 IWM_FW_PHY_CFG_RADIO_DASH_POS = 4, 846 IWM_FW_PHY_CFG_RADIO_DASH = 0x3 << IWM_FW_PHY_CFG_RADIO_DASH_POS, 847 IWM_FW_PHY_CFG_TX_CHAIN_POS = 16, 848 IWM_FW_PHY_CFG_TX_CHAIN = 0xf << IWM_FW_PHY_CFG_TX_CHAIN_POS, 849 IWM_FW_PHY_CFG_RX_CHAIN_POS = 20, 850 IWM_FW_PHY_CFG_RX_CHAIN = 0xf << IWM_FW_PHY_CFG_RX_CHAIN_POS, 851 }; 852 853 #define IWM_UCODE_MAX_CS 1 854 855 /** 856 * struct iwm_fw_cipher_scheme - a cipher scheme supported by FW. 857 * @cipher: a cipher suite selector 858 * @flags: cipher scheme flags (currently reserved for a future use) 859 * @hdr_len: a size of MPDU security header 860 * @pn_len: a size of PN 861 * @pn_off: an offset of pn from the beginning of the security header 862 * @key_idx_off: an offset of key index byte in the security header 863 * @key_idx_mask: a bit mask of key_idx bits 864 * @key_idx_shift: bit shift needed to get key_idx 865 * @mic_len: mic length in bytes 866 * @hw_cipher: a HW cipher index used in host commands 867 */ 868 struct iwm_fw_cipher_scheme { 869 uint32_t cipher; 870 uint8_t flags; 871 uint8_t hdr_len; 872 uint8_t pn_len; 873 uint8_t pn_off; 874 uint8_t key_idx_off; 875 uint8_t key_idx_mask; 876 uint8_t key_idx_shift; 877 uint8_t mic_len; 878 uint8_t hw_cipher; 879 } __packed; 880 881 /** 882 * struct iwm_fw_cscheme_list - a cipher scheme list 883 * @size: a number of entries 884 * @cs: cipher scheme entries 885 */ 886 struct iwm_fw_cscheme_list { 887 uint8_t size; 888 struct iwm_fw_cipher_scheme cs[]; 889 } __packed; 890 891 /* 892 * END iwl-fw.h 893 */ 894 895 /* 896 * BEGIN iwl-fw-file.h 897 */ 898 899 /* v1/v2 uCode file layout */ 900 struct iwm_ucode_header { 901 uint32_t ver; /* major/minor/API/serial */ 902 union { 903 struct { 904 uint32_t inst_size; /* bytes of runtime code */ 905 uint32_t data_size; /* bytes of runtime data */ 906 uint32_t init_size; /* bytes of init code */ 907 uint32_t init_data_size; /* bytes of init data */ 908 uint32_t boot_size; /* bytes of bootstrap code */ 909 uint8_t data[0]; /* in same order as sizes */ 910 } v1; 911 struct { 912 uint32_t build; /* build number */ 913 uint32_t inst_size; /* bytes of runtime code */ 914 uint32_t data_size; /* bytes of runtime data */ 915 uint32_t init_size; /* bytes of init code */ 916 uint32_t init_data_size; /* bytes of init data */ 917 uint32_t boot_size; /* bytes of bootstrap code */ 918 uint8_t data[0]; /* in same order as sizes */ 919 } v2; 920 } u; 921 }; 922 923 /* 924 * new TLV uCode file layout 925 * 926 * The new TLV file format contains TLVs, that each specify 927 * some piece of data. 928 */ 929 930 enum iwm_ucode_tlv_type { 931 IWM_UCODE_TLV_INVALID = 0, /* unused */ 932 IWM_UCODE_TLV_INST = 1, 933 IWM_UCODE_TLV_DATA = 2, 934 IWM_UCODE_TLV_INIT = 3, 935 IWM_UCODE_TLV_INIT_DATA = 4, 936 IWM_UCODE_TLV_BOOT = 5, 937 IWM_UCODE_TLV_PROBE_MAX_LEN = 6, /* a uint32_t value */ 938 IWM_UCODE_TLV_PAN = 7, 939 IWM_UCODE_TLV_RUNT_EVTLOG_PTR = 8, 940 IWM_UCODE_TLV_RUNT_EVTLOG_SIZE = 9, 941 IWM_UCODE_TLV_RUNT_ERRLOG_PTR = 10, 942 IWM_UCODE_TLV_INIT_EVTLOG_PTR = 11, 943 IWM_UCODE_TLV_INIT_EVTLOG_SIZE = 12, 944 IWM_UCODE_TLV_INIT_ERRLOG_PTR = 13, 945 IWM_UCODE_TLV_ENHANCE_SENS_TBL = 14, 946 IWM_UCODE_TLV_PHY_CALIBRATION_SIZE = 15, 947 IWM_UCODE_TLV_WOWLAN_INST = 16, 948 IWM_UCODE_TLV_WOWLAN_DATA = 17, 949 IWM_UCODE_TLV_FLAGS = 18, 950 IWM_UCODE_TLV_SEC_RT = 19, 951 IWM_UCODE_TLV_SEC_INIT = 20, 952 IWM_UCODE_TLV_SEC_WOWLAN = 21, 953 IWM_UCODE_TLV_DEF_CALIB = 22, 954 IWM_UCODE_TLV_PHY_SKU = 23, 955 IWM_UCODE_TLV_SECURE_SEC_RT = 24, 956 IWM_UCODE_TLV_SECURE_SEC_INIT = 25, 957 IWM_UCODE_TLV_SECURE_SEC_WOWLAN = 26, 958 IWM_UCODE_TLV_NUM_OF_CPU = 27, 959 IWM_UCODE_TLV_CSCHEME = 28, 960 961 /* 962 * Following two are not in our base tag, but allow 963 * handling ucode version 9. 964 */ 965 IWM_UCODE_TLV_API_CHANGES_SET = 29, 966 IWM_UCODE_TLV_ENABLED_CAPABILITIES = 30, 967 968 IWM_UCODE_TLV_N_SCAN_CHANNELS = 31, 969 IWM_UCODE_TLV_PAGING = 32, 970 IWM_UCODE_TLV_SEC_RT_USNIFFER = 34, 971 IWM_UCODE_TLV_SDIO_ADMA_ADDR = 35, 972 IWM_UCODE_TLV_FW_VERSION = 36, 973 IWM_UCODE_TLV_FW_DBG_DEST = 38, 974 IWM_UCODE_TLV_FW_DBG_CONF = 39, 975 IWM_UCODE_TLV_FW_DBG_TRIGGER = 40, 976 IWM_UCODE_TLV_FW_GSCAN_CAPA = 50, 977 }; 978 979 struct iwm_ucode_tlv { 980 uint32_t type; /* see above */ 981 uint32_t length; /* not including type/length fields */ 982 uint8_t data[0]; 983 }; 984 985 struct iwm_ucode_api { 986 uint32_t api_index; 987 uint32_t api_flags; 988 } __packed; 989 990 struct iwm_ucode_capa { 991 uint32_t api_index; 992 uint32_t api_capa; 993 } __packed; 994 995 #define IWM_TLV_UCODE_MAGIC 0x0a4c5749 996 997 struct iwm_tlv_ucode_header { 998 /* 999 * The TLV style ucode header is distinguished from 1000 * the v1/v2 style header by first four bytes being 1001 * zero, as such is an invalid combination of 1002 * major/minor/API/serial versions. 1003 */ 1004 uint32_t zero; 1005 uint32_t magic; 1006 uint8_t human_readable[64]; 1007 uint32_t ver; /* major/minor/API/serial */ 1008 uint32_t build; 1009 uint64_t ignore; 1010 /* 1011 * The data contained herein has a TLV layout, 1012 * see above for the TLV header and types. 1013 * Note that each TLV is padded to a length 1014 * that is a multiple of 4 for alignment. 1015 */ 1016 uint8_t data[0]; 1017 }; 1018 1019 /* 1020 * END iwl-fw-file.h 1021 */ 1022 1023 /* 1024 * BEGIN iwl-prph.h 1025 */ 1026 1027 /* 1028 * Registers in this file are internal, not PCI bus memory mapped. 1029 * Driver accesses these via IWM_HBUS_TARG_PRPH_* registers. 1030 */ 1031 #define IWM_PRPH_BASE (0x00000) 1032 #define IWM_PRPH_END (0xFFFFF) 1033 1034 /* APMG (power management) constants */ 1035 #define IWM_APMG_BASE (IWM_PRPH_BASE + 0x3000) 1036 #define IWM_APMG_CLK_CTRL_REG (IWM_APMG_BASE + 0x0000) 1037 #define IWM_APMG_CLK_EN_REG (IWM_APMG_BASE + 0x0004) 1038 #define IWM_APMG_CLK_DIS_REG (IWM_APMG_BASE + 0x0008) 1039 #define IWM_APMG_PS_CTRL_REG (IWM_APMG_BASE + 0x000c) 1040 #define IWM_APMG_PCIDEV_STT_REG (IWM_APMG_BASE + 0x0010) 1041 #define IWM_APMG_RFKILL_REG (IWM_APMG_BASE + 0x0014) 1042 #define IWM_APMG_RTC_INT_STT_REG (IWM_APMG_BASE + 0x001c) 1043 #define IWM_APMG_RTC_INT_MSK_REG (IWM_APMG_BASE + 0x0020) 1044 #define IWM_APMG_DIGITAL_SVR_REG (IWM_APMG_BASE + 0x0058) 1045 #define IWM_APMG_ANALOG_SVR_REG (IWM_APMG_BASE + 0x006C) 1046 1047 #define IWM_APMS_CLK_VAL_MRB_FUNC_MODE (0x00000001) 1048 #define IWM_APMG_CLK_VAL_DMA_CLK_RQT (0x00000200) 1049 #define IWM_APMG_CLK_VAL_BSM_CLK_RQT (0x00000800) 1050 1051 #define IWM_APMG_PS_CTRL_EARLY_PWR_OFF_RESET_DIS (0x00400000) 1052 #define IWM_APMG_PS_CTRL_VAL_RESET_REQ (0x04000000) 1053 #define IWM_APMG_PS_CTRL_MSK_PWR_SRC (0x03000000) 1054 #define IWM_APMG_PS_CTRL_VAL_PWR_SRC_VMAIN (0x00000000) 1055 #define IWM_APMG_PS_CTRL_VAL_PWR_SRC_VAUX (0x02000000) 1056 #define IWM_APMG_SVR_VOLTAGE_CONFIG_BIT_MSK (0x000001E0) /* bit 8:5 */ 1057 #define IWM_APMG_SVR_DIGITAL_VOLTAGE_1_32 (0x00000060) 1058 1059 #define IWM_APMG_PCIDEV_STT_VAL_L1_ACT_DIS (0x00000800) 1060 1061 #define IWM_APMG_RTC_INT_STT_RFKILL (0x10000000) 1062 1063 /* Device system time */ 1064 #define IWM_DEVICE_SYSTEM_TIME_REG 0xA0206C 1065 1066 /* Device NMI register */ 1067 #define IWM_DEVICE_SET_NMI_REG 0x00a01c30 1068 #define IWM_DEVICE_SET_NMI_VAL_HW 0x01 1069 #define IWM_DEVICE_SET_NMI_VAL_DRV 0x80 1070 #define IWM_DEVICE_SET_NMI_8000_REG 0x00a01c24 1071 #define IWM_DEVICE_SET_NMI_8000_VAL 0x1000000 1072 1073 /* 1074 * Device reset for family 8000 1075 * write to bit 24 in order to reset the CPU 1076 */ 1077 #define IWM_RELEASE_CPU_RESET 0x300c 1078 #define IWM_RELEASE_CPU_RESET_BIT 0x1000000 1079 1080 1081 /***************************************************************************** 1082 * 7000/3000 series SHR DTS addresses * 1083 *****************************************************************************/ 1084 1085 #define IWM_SHR_MISC_WFM_DTS_EN (0x00a10024) 1086 #define IWM_DTSC_CFG_MODE (0x00a10604) 1087 #define IWM_DTSC_VREF_AVG (0x00a10648) 1088 #define IWM_DTSC_VREF5_AVG (0x00a1064c) 1089 #define IWM_DTSC_CFG_MODE_PERIODIC (0x2) 1090 #define IWM_DTSC_PTAT_AVG (0x00a10650) 1091 1092 1093 /** 1094 * Tx Scheduler 1095 * 1096 * The Tx Scheduler selects the next frame to be transmitted, choosing TFDs 1097 * (Transmit Frame Descriptors) from up to 16 circular Tx queues resident in 1098 * host DRAM. It steers each frame's Tx command (which contains the frame 1099 * data) into one of up to 7 prioritized Tx DMA FIFO channels within the 1100 * device. A queue maps to only one (selectable by driver) Tx DMA channel, 1101 * but one DMA channel may take input from several queues. 1102 * 1103 * Tx DMA FIFOs have dedicated purposes. 1104 * 1105 * For 5000 series and up, they are used differently 1106 * (cf. iwl5000_default_queue_to_tx_fifo in iwl-5000.c): 1107 * 1108 * 0 -- EDCA BK (background) frames, lowest priority 1109 * 1 -- EDCA BE (best effort) frames, normal priority 1110 * 2 -- EDCA VI (video) frames, higher priority 1111 * 3 -- EDCA VO (voice) and management frames, highest priority 1112 * 4 -- unused 1113 * 5 -- unused 1114 * 6 -- unused 1115 * 7 -- Commands 1116 * 1117 * Driver should normally map queues 0-6 to Tx DMA/FIFO channels 0-6. 1118 * In addition, driver can map the remaining queues to Tx DMA/FIFO 1119 * channels 0-3 to support 11n aggregation via EDCA DMA channels. 1120 * 1121 * The driver sets up each queue to work in one of two modes: 1122 * 1123 * 1) Scheduler-Ack, in which the scheduler automatically supports a 1124 * block-ack (BA) window of up to 64 TFDs. In this mode, each queue 1125 * contains TFDs for a unique combination of Recipient Address (RA) 1126 * and Traffic Identifier (TID), that is, traffic of a given 1127 * Quality-Of-Service (QOS) priority, destined for a single station. 1128 * 1129 * In scheduler-ack mode, the scheduler keeps track of the Tx status of 1130 * each frame within the BA window, including whether it's been transmitted, 1131 * and whether it's been acknowledged by the receiving station. The device 1132 * automatically processes block-acks received from the receiving STA, 1133 * and reschedules un-acked frames to be retransmitted (successful 1134 * Tx completion may end up being out-of-order). 1135 * 1136 * The driver must maintain the queue's Byte Count table in host DRAM 1137 * for this mode. 1138 * This mode does not support fragmentation. 1139 * 1140 * 2) FIFO (a.k.a. non-Scheduler-ACK), in which each TFD is processed in order. 1141 * The device may automatically retry Tx, but will retry only one frame 1142 * at a time, until receiving ACK from receiving station, or reaching 1143 * retry limit and giving up. 1144 * 1145 * The command queue (#4/#9) must use this mode! 1146 * This mode does not require use of the Byte Count table in host DRAM. 1147 * 1148 * Driver controls scheduler operation via 3 means: 1149 * 1) Scheduler registers 1150 * 2) Shared scheduler data base in internal SRAM 1151 * 3) Shared data in host DRAM 1152 * 1153 * Initialization: 1154 * 1155 * When loading, driver should allocate memory for: 1156 * 1) 16 TFD circular buffers, each with space for (typically) 256 TFDs. 1157 * 2) 16 Byte Count circular buffers in 16 KBytes contiguous memory 1158 * (1024 bytes for each queue). 1159 * 1160 * After receiving "Alive" response from uCode, driver must initialize 1161 * the scheduler (especially for queue #4/#9, the command queue, otherwise 1162 * the driver can't issue commands!): 1163 */ 1164 #define IWM_SCD_MEM_LOWER_BOUND (0x0000) 1165 1166 /** 1167 * Max Tx window size is the max number of contiguous TFDs that the scheduler 1168 * can keep track of at one time when creating block-ack chains of frames. 1169 * Note that "64" matches the number of ack bits in a block-ack packet. 1170 */ 1171 #define IWM_SCD_WIN_SIZE 64 1172 #define IWM_SCD_FRAME_LIMIT 64 1173 1174 #define IWM_SCD_TXFIFO_POS_TID (0) 1175 #define IWM_SCD_TXFIFO_POS_RA (4) 1176 #define IWM_SCD_QUEUE_RA_TID_MAP_RATID_MSK (0x01FF) 1177 1178 /* agn SCD */ 1179 #define IWM_SCD_QUEUE_STTS_REG_POS_TXF (0) 1180 #define IWM_SCD_QUEUE_STTS_REG_POS_ACTIVE (3) 1181 #define IWM_SCD_QUEUE_STTS_REG_POS_WSL (4) 1182 #define IWM_SCD_QUEUE_STTS_REG_POS_SCD_ACT_EN (19) 1183 #define IWM_SCD_QUEUE_STTS_REG_MSK (0x017F0000) 1184 1185 #define IWM_SCD_QUEUE_CTX_REG1_CREDIT_POS (8) 1186 #define IWM_SCD_QUEUE_CTX_REG1_CREDIT_MSK (0x00FFFF00) 1187 #define IWM_SCD_QUEUE_CTX_REG1_SUPER_CREDIT_POS (24) 1188 #define IWM_SCD_QUEUE_CTX_REG1_SUPER_CREDIT_MSK (0xFF000000) 1189 #define IWM_SCD_QUEUE_CTX_REG2_WIN_SIZE_POS (0) 1190 #define IWM_SCD_QUEUE_CTX_REG2_WIN_SIZE_MSK (0x0000007F) 1191 #define IWM_SCD_QUEUE_CTX_REG2_FRAME_LIMIT_POS (16) 1192 #define IWM_SCD_QUEUE_CTX_REG2_FRAME_LIMIT_MSK (0x007F0000) 1193 #define IWM_SCD_GP_CTRL_ENABLE_31_QUEUES (1 << 0) 1194 #define IWM_SCD_GP_CTRL_AUTO_ACTIVE_MODE (1 << 18) 1195 1196 /* Context Data */ 1197 #define IWM_SCD_CONTEXT_MEM_LOWER_BOUND (IWM_SCD_MEM_LOWER_BOUND + 0x600) 1198 #define IWM_SCD_CONTEXT_MEM_UPPER_BOUND (IWM_SCD_MEM_LOWER_BOUND + 0x6A0) 1199 1200 /* Tx status */ 1201 #define IWM_SCD_TX_STTS_MEM_LOWER_BOUND (IWM_SCD_MEM_LOWER_BOUND + 0x6A0) 1202 #define IWM_SCD_TX_STTS_MEM_UPPER_BOUND (IWM_SCD_MEM_LOWER_BOUND + 0x7E0) 1203 1204 /* Translation Data */ 1205 #define IWM_SCD_TRANS_TBL_MEM_LOWER_BOUND (IWM_SCD_MEM_LOWER_BOUND + 0x7E0) 1206 #define IWM_SCD_TRANS_TBL_MEM_UPPER_BOUND (IWM_SCD_MEM_LOWER_BOUND + 0x808) 1207 1208 #define IWM_SCD_CONTEXT_QUEUE_OFFSET(x)\ 1209 (IWM_SCD_CONTEXT_MEM_LOWER_BOUND + ((x) * 8)) 1210 1211 #define IWM_SCD_TX_STTS_QUEUE_OFFSET(x)\ 1212 (IWM_SCD_TX_STTS_MEM_LOWER_BOUND + ((x) * 16)) 1213 1214 #define IWM_SCD_TRANS_TBL_OFFSET_QUEUE(x) \ 1215 ((IWM_SCD_TRANS_TBL_MEM_LOWER_BOUND + ((x) * 2)) & 0xfffc) 1216 1217 #define IWM_SCD_BASE (IWM_PRPH_BASE + 0xa02c00) 1218 1219 #define IWM_SCD_SRAM_BASE_ADDR (IWM_SCD_BASE + 0x0) 1220 #define IWM_SCD_DRAM_BASE_ADDR (IWM_SCD_BASE + 0x8) 1221 #define IWM_SCD_AIT (IWM_SCD_BASE + 0x0c) 1222 #define IWM_SCD_TXFACT (IWM_SCD_BASE + 0x10) 1223 #define IWM_SCD_ACTIVE (IWM_SCD_BASE + 0x14) 1224 #define IWM_SCD_QUEUECHAIN_SEL (IWM_SCD_BASE + 0xe8) 1225 #define IWM_SCD_CHAINEXT_EN (IWM_SCD_BASE + 0x244) 1226 #define IWM_SCD_AGGR_SEL (IWM_SCD_BASE + 0x248) 1227 #define IWM_SCD_INTERRUPT_MASK (IWM_SCD_BASE + 0x108) 1228 #define IWM_SCD_GP_CTRL (IWM_SCD_BASE + 0x1a8) 1229 #define IWM_SCD_EN_CTRL (IWM_SCD_BASE + 0x254) 1230 1231 static inline unsigned int IWM_SCD_QUEUE_WRPTR(unsigned int chnl) 1232 { 1233 if (chnl < 20) 1234 return IWM_SCD_BASE + 0x18 + chnl * 4; 1235 return IWM_SCD_BASE + 0x284 + (chnl - 20) * 4; 1236 } 1237 1238 static inline unsigned int IWM_SCD_QUEUE_RDPTR(unsigned int chnl) 1239 { 1240 if (chnl < 20) 1241 return IWM_SCD_BASE + 0x68 + chnl * 4; 1242 return IWM_SCD_BASE + 0x2B4 + (chnl - 20) * 4; 1243 } 1244 1245 static inline unsigned int IWM_SCD_QUEUE_STATUS_BITS(unsigned int chnl) 1246 { 1247 if (chnl < 20) 1248 return IWM_SCD_BASE + 0x10c + chnl * 4; 1249 return IWM_SCD_BASE + 0x384 + (chnl - 20) * 4; 1250 } 1251 1252 /*********************** END TX SCHEDULER *************************************/ 1253 1254 /* Oscillator clock */ 1255 #define IWM_OSC_CLK (0xa04068) 1256 #define IWM_OSC_CLK_FORCE_CONTROL (0x8) 1257 1258 /* 1259 * END iwl-prph.h 1260 */ 1261 1262 /* 1263 * BEGIN iwl-fh.h 1264 */ 1265 1266 /****************************/ 1267 /* Flow Handler Definitions */ 1268 /****************************/ 1269 1270 /** 1271 * This I/O area is directly read/writable by driver (e.g. Linux uses writel()) 1272 * Addresses are offsets from device's PCI hardware base address. 1273 */ 1274 #define IWM_FH_MEM_LOWER_BOUND (0x1000) 1275 #define IWM_FH_MEM_UPPER_BOUND (0x2000) 1276 1277 /** 1278 * Keep-Warm (KW) buffer base address. 1279 * 1280 * Driver must allocate a 4KByte buffer that is for keeping the 1281 * host DRAM powered on (via dummy accesses to DRAM) to maintain low-latency 1282 * DRAM access when doing Txing or Rxing. The dummy accesses prevent host 1283 * from going into a power-savings mode that would cause higher DRAM latency, 1284 * and possible data over/under-runs, before all Tx/Rx is complete. 1285 * 1286 * Driver loads IWM_FH_KW_MEM_ADDR_REG with the physical address (bits 35:4) 1287 * of the buffer, which must be 4K aligned. Once this is set up, the device 1288 * automatically invokes keep-warm accesses when normal accesses might not 1289 * be sufficient to maintain fast DRAM response. 1290 * 1291 * Bit fields: 1292 * 31-0: Keep-warm buffer physical base address [35:4], must be 4K aligned 1293 */ 1294 #define IWM_FH_KW_MEM_ADDR_REG (IWM_FH_MEM_LOWER_BOUND + 0x97C) 1295 1296 1297 /** 1298 * TFD Circular Buffers Base (CBBC) addresses 1299 * 1300 * Device has 16 base pointer registers, one for each of 16 host-DRAM-resident 1301 * circular buffers (CBs/queues) containing Transmit Frame Descriptors (TFDs) 1302 * (see struct iwm_tfd_frame). These 16 pointer registers are offset by 0x04 1303 * bytes from one another. Each TFD circular buffer in DRAM must be 256-byte 1304 * aligned (address bits 0-7 must be 0). 1305 * Later devices have 20 (5000 series) or 30 (higher) queues, but the registers 1306 * for them are in different places. 1307 * 1308 * Bit fields in each pointer register: 1309 * 27-0: TFD CB physical base address [35:8], must be 256-byte aligned 1310 */ 1311 #define IWM_FH_MEM_CBBC_0_15_LOWER_BOUND (IWM_FH_MEM_LOWER_BOUND + 0x9D0) 1312 #define IWM_FH_MEM_CBBC_0_15_UPPER_BOUN (IWM_FH_MEM_LOWER_BOUND + 0xA10) 1313 #define IWM_FH_MEM_CBBC_16_19_LOWER_BOUND (IWM_FH_MEM_LOWER_BOUND + 0xBF0) 1314 #define IWM_FH_MEM_CBBC_16_19_UPPER_BOUND (IWM_FH_MEM_LOWER_BOUND + 0xC00) 1315 #define IWM_FH_MEM_CBBC_20_31_LOWER_BOUND (IWM_FH_MEM_LOWER_BOUND + 0xB20) 1316 #define IWM_FH_MEM_CBBC_20_31_UPPER_BOUND (IWM_FH_MEM_LOWER_BOUND + 0xB80) 1317 1318 /* Find TFD CB base pointer for given queue */ 1319 static inline unsigned int IWM_FH_MEM_CBBC_QUEUE(unsigned int chnl) 1320 { 1321 if (chnl < 16) 1322 return IWM_FH_MEM_CBBC_0_15_LOWER_BOUND + 4 * chnl; 1323 if (chnl < 20) 1324 return IWM_FH_MEM_CBBC_16_19_LOWER_BOUND + 4 * (chnl - 16); 1325 return IWM_FH_MEM_CBBC_20_31_LOWER_BOUND + 4 * (chnl - 20); 1326 } 1327 1328 1329 /** 1330 * Rx SRAM Control and Status Registers (RSCSR) 1331 * 1332 * These registers provide handshake between driver and device for the Rx queue 1333 * (this queue handles *all* command responses, notifications, Rx data, etc. 1334 * sent from uCode to host driver). Unlike Tx, there is only one Rx 1335 * queue, and only one Rx DMA/FIFO channel. Also unlike Tx, which can 1336 * concatenate up to 20 DRAM buffers to form a Tx frame, each Receive Buffer 1337 * Descriptor (RBD) points to only one Rx Buffer (RB); there is a 1:1 1338 * mapping between RBDs and RBs. 1339 * 1340 * Driver must allocate host DRAM memory for the following, and set the 1341 * physical address of each into device registers: 1342 * 1343 * 1) Receive Buffer Descriptor (RBD) circular buffer (CB), typically with 256 1344 * entries (although any power of 2, up to 4096, is selectable by driver). 1345 * Each entry (1 dword) points to a receive buffer (RB) of consistent size 1346 * (typically 4K, although 8K or 16K are also selectable by driver). 1347 * Driver sets up RB size and number of RBDs in the CB via Rx config 1348 * register IWM_FH_MEM_RCSR_CHNL0_CONFIG_REG. 1349 * 1350 * Bit fields within one RBD: 1351 * 27-0: Receive Buffer physical address bits [35:8], 256-byte aligned 1352 * 1353 * Driver sets physical address [35:8] of base of RBD circular buffer 1354 * into IWM_FH_RSCSR_CHNL0_RBDCB_BASE_REG [27:0]. 1355 * 1356 * 2) Rx status buffer, 8 bytes, in which uCode indicates which Rx Buffers 1357 * (RBs) have been filled, via a "write pointer", actually the index of 1358 * the RB's corresponding RBD within the circular buffer. Driver sets 1359 * physical address [35:4] into IWM_FH_RSCSR_CHNL0_STTS_WPTR_REG [31:0]. 1360 * 1361 * Bit fields in lower dword of Rx status buffer (upper dword not used 1362 * by driver: 1363 * 31-12: Not used by driver 1364 * 11- 0: Index of last filled Rx buffer descriptor 1365 * (device writes, driver reads this value) 1366 * 1367 * As the driver prepares Receive Buffers (RBs) for device to fill, driver must 1368 * enter pointers to these RBs into contiguous RBD circular buffer entries, 1369 * and update the device's "write" index register, 1370 * IWM_FH_RSCSR_CHNL0_RBDCB_WPTR_REG. 1371 * 1372 * This "write" index corresponds to the *next* RBD that the driver will make 1373 * available, i.e. one RBD past the tail of the ready-to-fill RBDs within 1374 * the circular buffer. This value should initially be 0 (before preparing any 1375 * RBs), should be 8 after preparing the first 8 RBs (for example), and must 1376 * wrap back to 0 at the end of the circular buffer (but don't wrap before 1377 * "read" index has advanced past 1! See below). 1378 * NOTE: DEVICE EXPECTS THE WRITE INDEX TO BE INCREMENTED IN MULTIPLES OF 8. 1379 * 1380 * As the device fills RBs (referenced from contiguous RBDs within the circular 1381 * buffer), it updates the Rx status buffer in host DRAM, 2) described above, 1382 * to tell the driver the index of the latest filled RBD. The driver must 1383 * read this "read" index from DRAM after receiving an Rx interrupt from device 1384 * 1385 * The driver must also internally keep track of a third index, which is the 1386 * next RBD to process. When receiving an Rx interrupt, driver should process 1387 * all filled but unprocessed RBs up to, but not including, the RB 1388 * corresponding to the "read" index. For example, if "read" index becomes "1", 1389 * driver may process the RB pointed to by RBD 0. Depending on volume of 1390 * traffic, there may be many RBs to process. 1391 * 1392 * If read index == write index, device thinks there is no room to put new data. 1393 * Due to this, the maximum number of filled RBs is 255, instead of 256. To 1394 * be safe, make sure that there is a gap of at least 2 RBDs between "write" 1395 * and "read" indexes; that is, make sure that there are no more than 254 1396 * buffers waiting to be filled. 1397 */ 1398 #define IWM_FH_MEM_RSCSR_LOWER_BOUND (IWM_FH_MEM_LOWER_BOUND + 0xBC0) 1399 #define IWM_FH_MEM_RSCSR_UPPER_BOUND (IWM_FH_MEM_LOWER_BOUND + 0xC00) 1400 #define IWM_FH_MEM_RSCSR_CHNL0 (IWM_FH_MEM_RSCSR_LOWER_BOUND) 1401 1402 /** 1403 * Physical base address of 8-byte Rx Status buffer. 1404 * Bit fields: 1405 * 31-0: Rx status buffer physical base address [35:4], must 16-byte aligned. 1406 */ 1407 #define IWM_FH_RSCSR_CHNL0_STTS_WPTR_REG (IWM_FH_MEM_RSCSR_CHNL0) 1408 1409 /** 1410 * Physical base address of Rx Buffer Descriptor Circular Buffer. 1411 * Bit fields: 1412 * 27-0: RBD CD physical base address [35:8], must be 256-byte aligned. 1413 */ 1414 #define IWM_FH_RSCSR_CHNL0_RBDCB_BASE_REG (IWM_FH_MEM_RSCSR_CHNL0 + 0x004) 1415 1416 /** 1417 * Rx write pointer (index, really!). 1418 * Bit fields: 1419 * 11-0: Index of driver's most recent prepared-to-be-filled RBD, + 1. 1420 * NOTE: For 256-entry circular buffer, use only bits [7:0]. 1421 */ 1422 #define IWM_FH_RSCSR_CHNL0_RBDCB_WPTR_REG (IWM_FH_MEM_RSCSR_CHNL0 + 0x008) 1423 #define IWM_FH_RSCSR_CHNL0_WPTR (IWM_FH_RSCSR_CHNL0_RBDCB_WPTR_REG) 1424 1425 #define IWM_FW_RSCSR_CHNL0_RXDCB_RDPTR_REG (IWM_FH_MEM_RSCSR_CHNL0 + 0x00c) 1426 #define IWM_FH_RSCSR_CHNL0_RDPTR IWM_FW_RSCSR_CHNL0_RXDCB_RDPTR_REG 1427 1428 /** 1429 * Rx Config/Status Registers (RCSR) 1430 * Rx Config Reg for channel 0 (only channel used) 1431 * 1432 * Driver must initialize IWM_FH_MEM_RCSR_CHNL0_CONFIG_REG as follows for 1433 * normal operation (see bit fields). 1434 * 1435 * Clearing IWM_FH_MEM_RCSR_CHNL0_CONFIG_REG to 0 turns off Rx DMA. 1436 * Driver should poll IWM_FH_MEM_RSSR_RX_STATUS_REG for 1437 * IWM_FH_RSSR_CHNL0_RX_STATUS_CHNL_IDLE (bit 24) before continuing. 1438 * 1439 * Bit fields: 1440 * 31-30: Rx DMA channel enable: '00' off/pause, '01' pause at end of frame, 1441 * '10' operate normally 1442 * 29-24: reserved 1443 * 23-20: # RBDs in circular buffer = 2^value; use "8" for 256 RBDs (normal), 1444 * min "5" for 32 RBDs, max "12" for 4096 RBDs. 1445 * 19-18: reserved 1446 * 17-16: size of each receive buffer; '00' 4K (normal), '01' 8K, 1447 * '10' 12K, '11' 16K. 1448 * 15-14: reserved 1449 * 13-12: IRQ destination; '00' none, '01' host driver (normal operation) 1450 * 11- 4: timeout for closing Rx buffer and interrupting host (units 32 usec) 1451 * typical value 0x10 (about 1/2 msec) 1452 * 3- 0: reserved 1453 */ 1454 #define IWM_FH_MEM_RCSR_LOWER_BOUND (IWM_FH_MEM_LOWER_BOUND + 0xC00) 1455 #define IWM_FH_MEM_RCSR_UPPER_BOUND (IWM_FH_MEM_LOWER_BOUND + 0xCC0) 1456 #define IWM_FH_MEM_RCSR_CHNL0 (IWM_FH_MEM_RCSR_LOWER_BOUND) 1457 1458 #define IWM_FH_MEM_RCSR_CHNL0_CONFIG_REG (IWM_FH_MEM_RCSR_CHNL0) 1459 #define IWM_FH_MEM_RCSR_CHNL0_RBDCB_WPTR (IWM_FH_MEM_RCSR_CHNL0 + 0x8) 1460 #define IWM_FH_MEM_RCSR_CHNL0_FLUSH_RB_REQ (IWM_FH_MEM_RCSR_CHNL0 + 0x10) 1461 1462 #define IWM_FH_RCSR_CHNL0_RX_CONFIG_RB_TIMEOUT_MSK (0x00000FF0) /* bits 4-11 */ 1463 #define IWM_FH_RCSR_CHNL0_RX_CONFIG_IRQ_DEST_MSK (0x00001000) /* bits 12 */ 1464 #define IWM_FH_RCSR_CHNL0_RX_CONFIG_SINGLE_FRAME_MSK (0x00008000) /* bit 15 */ 1465 #define IWM_FH_RCSR_CHNL0_RX_CONFIG_RB_SIZE_MSK (0x00030000) /* bits 16-17 */ 1466 #define IWM_FH_RCSR_CHNL0_RX_CONFIG_RBDBC_SIZE_MSK (0x00F00000) /* bits 20-23 */ 1467 #define IWM_FH_RCSR_CHNL0_RX_CONFIG_DMA_CHNL_EN_MSK (0xC0000000) /* bits 30-31*/ 1468 1469 #define IWM_FH_RCSR_RX_CONFIG_RBDCB_SIZE_POS (20) 1470 #define IWM_FH_RCSR_RX_CONFIG_REG_IRQ_RBTH_POS (4) 1471 #define IWM_RX_RB_TIMEOUT (0x11) 1472 1473 #define IWM_FH_RCSR_RX_CONFIG_CHNL_EN_PAUSE_VAL (0x00000000) 1474 #define IWM_FH_RCSR_RX_CONFIG_CHNL_EN_PAUSE_EOF_VAL (0x40000000) 1475 #define IWM_FH_RCSR_RX_CONFIG_CHNL_EN_ENABLE_VAL (0x80000000) 1476 1477 #define IWM_FH_RCSR_RX_CONFIG_REG_VAL_RB_SIZE_4K (0x00000000) 1478 #define IWM_FH_RCSR_RX_CONFIG_REG_VAL_RB_SIZE_8K (0x00010000) 1479 #define IWM_FH_RCSR_RX_CONFIG_REG_VAL_RB_SIZE_12K (0x00020000) 1480 #define IWM_FH_RCSR_RX_CONFIG_REG_VAL_RB_SIZE_16K (0x00030000) 1481 1482 #define IWM_FH_RCSR_CHNL0_RX_IGNORE_RXF_EMPTY (0x00000004) 1483 #define IWM_FH_RCSR_CHNL0_RX_CONFIG_IRQ_DEST_NO_INT_VAL (0x00000000) 1484 #define IWM_FH_RCSR_CHNL0_RX_CONFIG_IRQ_DEST_INT_HOST_VAL (0x00001000) 1485 1486 /** 1487 * Rx Shared Status Registers (RSSR) 1488 * 1489 * After stopping Rx DMA channel (writing 0 to 1490 * IWM_FH_MEM_RCSR_CHNL0_CONFIG_REG), driver must poll 1491 * IWM_FH_MEM_RSSR_RX_STATUS_REG until Rx channel is idle. 1492 * 1493 * Bit fields: 1494 * 24: 1 = Channel 0 is idle 1495 * 1496 * IWM_FH_MEM_RSSR_SHARED_CTRL_REG and IWM_FH_MEM_RSSR_RX_ENABLE_ERR_IRQ2DRV 1497 * contain default values that should not be altered by the driver. 1498 */ 1499 #define IWM_FH_MEM_RSSR_LOWER_BOUND (IWM_FH_MEM_LOWER_BOUND + 0xC40) 1500 #define IWM_FH_MEM_RSSR_UPPER_BOUND (IWM_FH_MEM_LOWER_BOUND + 0xD00) 1501 1502 #define IWM_FH_MEM_RSSR_SHARED_CTRL_REG (IWM_FH_MEM_RSSR_LOWER_BOUND) 1503 #define IWM_FH_MEM_RSSR_RX_STATUS_REG (IWM_FH_MEM_RSSR_LOWER_BOUND + 0x004) 1504 #define IWM_FH_MEM_RSSR_RX_ENABLE_ERR_IRQ2DRV\ 1505 (IWM_FH_MEM_RSSR_LOWER_BOUND + 0x008) 1506 1507 #define IWM_FH_RSSR_CHNL0_RX_STATUS_CHNL_IDLE (0x01000000) 1508 1509 #define IWM_FH_MEM_TFDIB_REG1_ADDR_BITSHIFT 28 1510 1511 /* TFDB Area - TFDs buffer table */ 1512 #define IWM_FH_MEM_TFDIB_DRAM_ADDR_LSB_MSK (0xFFFFFFFF) 1513 #define IWM_FH_TFDIB_LOWER_BOUND (IWM_FH_MEM_LOWER_BOUND + 0x900) 1514 #define IWM_FH_TFDIB_UPPER_BOUND (IWM_FH_MEM_LOWER_BOUND + 0x958) 1515 #define IWM_FH_TFDIB_CTRL0_REG(_chnl) (IWM_FH_TFDIB_LOWER_BOUND + 0x8 * (_chnl)) 1516 #define IWM_FH_TFDIB_CTRL1_REG(_chnl) (IWM_FH_TFDIB_LOWER_BOUND + 0x8 * (_chnl) + 0x4) 1517 1518 /** 1519 * Transmit DMA Channel Control/Status Registers (TCSR) 1520 * 1521 * Device has one configuration register for each of 8 Tx DMA/FIFO channels 1522 * supported in hardware (don't confuse these with the 16 Tx queues in DRAM, 1523 * which feed the DMA/FIFO channels); config regs are separated by 0x20 bytes. 1524 * 1525 * To use a Tx DMA channel, driver must initialize its 1526 * IWM_FH_TCSR_CHNL_TX_CONFIG_REG(chnl) with: 1527 * 1528 * IWM_FH_TCSR_TX_CONFIG_REG_VAL_DMA_CHNL_ENABLE | 1529 * IWM_FH_TCSR_TX_CONFIG_REG_VAL_DMA_CREDIT_ENABLE_VAL 1530 * 1531 * All other bits should be 0. 1532 * 1533 * Bit fields: 1534 * 31-30: Tx DMA channel enable: '00' off/pause, '01' pause at end of frame, 1535 * '10' operate normally 1536 * 29- 4: Reserved, set to "0" 1537 * 3: Enable internal DMA requests (1, normal operation), disable (0) 1538 * 2- 0: Reserved, set to "0" 1539 */ 1540 #define IWM_FH_TCSR_LOWER_BOUND (IWM_FH_MEM_LOWER_BOUND + 0xD00) 1541 #define IWM_FH_TCSR_UPPER_BOUND (IWM_FH_MEM_LOWER_BOUND + 0xE60) 1542 1543 /* Find Control/Status reg for given Tx DMA/FIFO channel */ 1544 #define IWM_FH_TCSR_CHNL_NUM (8) 1545 1546 /* TCSR: tx_config register values */ 1547 #define IWM_FH_TCSR_CHNL_TX_CONFIG_REG(_chnl) \ 1548 (IWM_FH_TCSR_LOWER_BOUND + 0x20 * (_chnl)) 1549 #define IWM_FH_TCSR_CHNL_TX_CREDIT_REG(_chnl) \ 1550 (IWM_FH_TCSR_LOWER_BOUND + 0x20 * (_chnl) + 0x4) 1551 #define IWM_FH_TCSR_CHNL_TX_BUF_STS_REG(_chnl) \ 1552 (IWM_FH_TCSR_LOWER_BOUND + 0x20 * (_chnl) + 0x8) 1553 1554 #define IWM_FH_TCSR_TX_CONFIG_REG_VAL_MSG_MODE_TXF (0x00000000) 1555 #define IWM_FH_TCSR_TX_CONFIG_REG_VAL_MSG_MODE_DRV (0x00000001) 1556 1557 #define IWM_FH_TCSR_TX_CONFIG_REG_VAL_DMA_CREDIT_DISABLE (0x00000000) 1558 #define IWM_FH_TCSR_TX_CONFIG_REG_VAL_DMA_CREDIT_ENABLE (0x00000008) 1559 1560 #define IWM_FH_TCSR_TX_CONFIG_REG_VAL_CIRQ_HOST_NOINT (0x00000000) 1561 #define IWM_FH_TCSR_TX_CONFIG_REG_VAL_CIRQ_HOST_ENDTFD (0x00100000) 1562 #define IWM_FH_TCSR_TX_CONFIG_REG_VAL_CIRQ_HOST_IFTFD (0x00200000) 1563 1564 #define IWM_FH_TCSR_TX_CONFIG_REG_VAL_CIRQ_RTC_NOINT (0x00000000) 1565 #define IWM_FH_TCSR_TX_CONFIG_REG_VAL_CIRQ_RTC_ENDTFD (0x00400000) 1566 #define IWM_FH_TCSR_TX_CONFIG_REG_VAL_CIRQ_RTC_IFTFD (0x00800000) 1567 1568 #define IWM_FH_TCSR_TX_CONFIG_REG_VAL_DMA_CHNL_PAUSE (0x00000000) 1569 #define IWM_FH_TCSR_TX_CONFIG_REG_VAL_DMA_CHNL_PAUSE_EOF (0x40000000) 1570 #define IWM_FH_TCSR_TX_CONFIG_REG_VAL_DMA_CHNL_ENABLE (0x80000000) 1571 1572 #define IWM_FH_TCSR_CHNL_TX_BUF_STS_REG_VAL_TFDB_EMPTY (0x00000000) 1573 #define IWM_FH_TCSR_CHNL_TX_BUF_STS_REG_VAL_TFDB_WAIT (0x00002000) 1574 #define IWM_FH_TCSR_CHNL_TX_BUF_STS_REG_VAL_TFDB_VALID (0x00000003) 1575 1576 #define IWM_FH_TCSR_CHNL_TX_BUF_STS_REG_POS_TB_NUM (20) 1577 #define IWM_FH_TCSR_CHNL_TX_BUF_STS_REG_POS_TB_IDX (12) 1578 1579 /** 1580 * Tx Shared Status Registers (TSSR) 1581 * 1582 * After stopping Tx DMA channel (writing 0 to 1583 * IWM_FH_TCSR_CHNL_TX_CONFIG_REG(chnl)), driver must poll 1584 * IWM_FH_TSSR_TX_STATUS_REG until selected Tx channel is idle 1585 * (channel's buffers empty | no pending requests). 1586 * 1587 * Bit fields: 1588 * 31-24: 1 = Channel buffers empty (channel 7:0) 1589 * 23-16: 1 = No pending requests (channel 7:0) 1590 */ 1591 #define IWM_FH_TSSR_LOWER_BOUND (IWM_FH_MEM_LOWER_BOUND + 0xEA0) 1592 #define IWM_FH_TSSR_UPPER_BOUND (IWM_FH_MEM_LOWER_BOUND + 0xEC0) 1593 1594 #define IWM_FH_TSSR_TX_STATUS_REG (IWM_FH_TSSR_LOWER_BOUND + 0x010) 1595 1596 /** 1597 * Bit fields for TSSR(Tx Shared Status & Control) error status register: 1598 * 31: Indicates an address error when accessed to internal memory 1599 * uCode/driver must write "1" in order to clear this flag 1600 * 30: Indicates that Host did not send the expected number of dwords to FH 1601 * uCode/driver must write "1" in order to clear this flag 1602 * 16-9:Each status bit is for one channel. Indicates that an (Error) ActDMA 1603 * command was received from the scheduler while the TRB was already full 1604 * with previous command 1605 * uCode/driver must write "1" in order to clear this flag 1606 * 7-0: Each status bit indicates a channel's TxCredit error. When an error 1607 * bit is set, it indicates that the FH has received a full indication 1608 * from the RTC TxFIFO and the current value of the TxCredit counter was 1609 * not equal to zero. This mean that the credit mechanism was not 1610 * synchronized to the TxFIFO status 1611 * uCode/driver must write "1" in order to clear this flag 1612 */ 1613 #define IWM_FH_TSSR_TX_ERROR_REG (IWM_FH_TSSR_LOWER_BOUND + 0x018) 1614 #define IWM_FH_TSSR_TX_MSG_CONFIG_REG (IWM_FH_TSSR_LOWER_BOUND + 0x008) 1615 1616 #define IWM_FH_TSSR_TX_STATUS_REG_MSK_CHNL_IDLE(_chnl) ((1 << (_chnl)) << 16) 1617 1618 /* Tx service channels */ 1619 #define IWM_FH_SRVC_CHNL (9) 1620 #define IWM_FH_SRVC_LOWER_BOUND (IWM_FH_MEM_LOWER_BOUND + 0x9C8) 1621 #define IWM_FH_SRVC_UPPER_BOUND (IWM_FH_MEM_LOWER_BOUND + 0x9D0) 1622 #define IWM_FH_SRVC_CHNL_SRAM_ADDR_REG(_chnl) \ 1623 (IWM_FH_SRVC_LOWER_BOUND + ((_chnl) - 9) * 0x4) 1624 1625 #define IWM_FH_TX_CHICKEN_BITS_REG (IWM_FH_MEM_LOWER_BOUND + 0xE98) 1626 #define IWM_FH_TX_TRB_REG(_chan) (IWM_FH_MEM_LOWER_BOUND + 0x958 + \ 1627 (_chan) * 4) 1628 1629 /* Instruct FH to increment the retry count of a packet when 1630 * it is brought from the memory to TX-FIFO 1631 */ 1632 #define IWM_FH_TX_CHICKEN_BITS_SCD_AUTO_RETRY_EN (0x00000002) 1633 1634 #define IWM_RX_QUEUE_SIZE 256 1635 #define IWM_RX_QUEUE_MASK 255 1636 #define IWM_RX_QUEUE_SIZE_LOG 8 1637 1638 /* 1639 * RX related structures and functions 1640 */ 1641 #define IWM_RX_FREE_BUFFERS 64 1642 #define IWM_RX_LOW_WATERMARK 8 1643 1644 /** 1645 * struct iwm_rb_status - reseve buffer status 1646 * host memory mapped FH registers 1647 * @closed_rb_num [0:11] - Indicates the index of the RB which was closed 1648 * @closed_fr_num [0:11] - Indicates the index of the RX Frame which was closed 1649 * @finished_rb_num [0:11] - Indicates the index of the current RB 1650 * in which the last frame was written to 1651 * @finished_fr_num [0:11] - Indicates the index of the RX Frame 1652 * which was transferred 1653 */ 1654 struct iwm_rb_status { 1655 uint16_t closed_rb_num; 1656 uint16_t closed_fr_num; 1657 uint16_t finished_rb_num; 1658 uint16_t finished_fr_nam; 1659 uint32_t unused; 1660 } __packed; 1661 1662 1663 #define IWM_TFD_QUEUE_SIZE_MAX (256) 1664 #define IWM_TFD_QUEUE_SIZE_BC_DUP (64) 1665 #define IWM_TFD_QUEUE_BC_SIZE (IWM_TFD_QUEUE_SIZE_MAX + \ 1666 IWM_TFD_QUEUE_SIZE_BC_DUP) 1667 #define IWM_TX_DMA_MASK DMA_BIT_MASK(36) 1668 #define IWM_NUM_OF_TBS 20 1669 1670 static inline uint8_t iwm_get_dma_hi_addr(bus_addr_t addr) 1671 { 1672 return (sizeof(addr) > sizeof(uint32_t) ? (addr >> 16) >> 16 : 0) & 0xF; 1673 } 1674 /** 1675 * struct iwm_tfd_tb transmit buffer descriptor within transmit frame descriptor 1676 * 1677 * This structure contains dma address and length of transmission address 1678 * 1679 * @lo: low [31:0] portion of the dma address of TX buffer 1680 * every even is unaligned on 16 bit boundary 1681 * @hi_n_len 0-3 [35:32] portion of dma 1682 * 4-15 length of the tx buffer 1683 */ 1684 struct iwm_tfd_tb { 1685 uint32_t lo; 1686 uint16_t hi_n_len; 1687 } __packed; 1688 1689 /** 1690 * struct iwm_tfd 1691 * 1692 * Transmit Frame Descriptor (TFD) 1693 * 1694 * @ __reserved1[3] reserved 1695 * @ num_tbs 0-4 number of active tbs 1696 * 5 reserved 1697 * 6-7 padding (not used) 1698 * @ tbs[20] transmit frame buffer descriptors 1699 * @ __pad padding 1700 * 1701 * Each Tx queue uses a circular buffer of 256 TFDs stored in host DRAM. 1702 * Both driver and device share these circular buffers, each of which must be 1703 * contiguous 256 TFDs x 128 bytes-per-TFD = 32 KBytes 1704 * 1705 * Driver must indicate the physical address of the base of each 1706 * circular buffer via the IWM_FH_MEM_CBBC_QUEUE registers. 1707 * 1708 * Each TFD contains pointer/size information for up to 20 data buffers 1709 * in host DRAM. These buffers collectively contain the (one) frame described 1710 * by the TFD. Each buffer must be a single contiguous block of memory within 1711 * itself, but buffers may be scattered in host DRAM. Each buffer has max size 1712 * of (4K - 4). The concatenates all of a TFD's buffers into a single 1713 * Tx frame, up to 8 KBytes in size. 1714 * 1715 * A maximum of 255 (not 256!) TFDs may be on a queue waiting for Tx. 1716 */ 1717 struct iwm_tfd { 1718 uint8_t __reserved1[3]; 1719 uint8_t num_tbs; 1720 struct iwm_tfd_tb tbs[IWM_NUM_OF_TBS]; 1721 uint32_t __pad; 1722 } __packed; 1723 1724 /* Keep Warm Size */ 1725 #define IWM_KW_SIZE 0x1000 /* 4k */ 1726 1727 /* Fixed (non-configurable) rx data from phy */ 1728 1729 /** 1730 * struct iwm_agn_schedq_bc_tbl scheduler byte count table 1731 * base physical address provided by IWM_SCD_DRAM_BASE_ADDR 1732 * @tfd_offset 0-12 - tx command byte count 1733 * 12-16 - station index 1734 */ 1735 struct iwm_agn_scd_bc_tbl { 1736 uint16_t tfd_offset[IWM_TFD_QUEUE_BC_SIZE]; 1737 } __packed; 1738 1739 /* 1740 * END iwl-fh.h 1741 */ 1742 1743 /* 1744 * BEGIN mvm/fw-api.h 1745 */ 1746 1747 /* Maximum number of Tx queues. */ 1748 #define IWM_MVM_MAX_QUEUES 31 1749 1750 /* Tx queue numbers */ 1751 enum { 1752 IWM_MVM_OFFCHANNEL_QUEUE = 8, 1753 IWM_MVM_CMD_QUEUE = 9, 1754 IWM_MVM_AUX_QUEUE = 15, 1755 }; 1756 1757 enum iwm_mvm_tx_fifo { 1758 IWM_MVM_TX_FIFO_BK = 0, 1759 IWM_MVM_TX_FIFO_BE, 1760 IWM_MVM_TX_FIFO_VI, 1761 IWM_MVM_TX_FIFO_VO, 1762 IWM_MVM_TX_FIFO_MCAST = 5, 1763 IWM_MVM_TX_FIFO_CMD = 7, 1764 }; 1765 1766 #define IWM_MVM_STATION_COUNT 16 1767 1768 /* commands */ 1769 enum { 1770 IWM_MVM_ALIVE = 0x1, 1771 IWM_REPLY_ERROR = 0x2, 1772 1773 IWM_INIT_COMPLETE_NOTIF = 0x4, 1774 1775 /* PHY context commands */ 1776 IWM_PHY_CONTEXT_CMD = 0x8, 1777 IWM_DBG_CFG = 0x9, 1778 1779 /* UMAC scan commands */ 1780 IWM_SCAN_ITERATION_COMPLETE_UMAC = 0xb5, 1781 IWM_SCAN_CFG_CMD = 0xc, 1782 IWM_SCAN_REQ_UMAC = 0xd, 1783 IWM_SCAN_ABORT_UMAC = 0xe, 1784 IWM_SCAN_COMPLETE_UMAC = 0xf, 1785 1786 /* station table */ 1787 IWM_ADD_STA_KEY = 0x17, 1788 IWM_ADD_STA = 0x18, 1789 IWM_REMOVE_STA = 0x19, 1790 1791 /* TX */ 1792 IWM_TX_CMD = 0x1c, 1793 IWM_TXPATH_FLUSH = 0x1e, 1794 IWM_MGMT_MCAST_KEY = 0x1f, 1795 1796 /* scheduler config */ 1797 IWM_SCD_QUEUE_CFG = 0x1d, 1798 1799 /* global key */ 1800 IWM_WEP_KEY = 0x20, 1801 1802 /* MAC and Binding commands */ 1803 IWM_MAC_CONTEXT_CMD = 0x28, 1804 IWM_TIME_EVENT_CMD = 0x29, /* both CMD and response */ 1805 IWM_TIME_EVENT_NOTIFICATION = 0x2a, 1806 IWM_BINDING_CONTEXT_CMD = 0x2b, 1807 IWM_TIME_QUOTA_CMD = 0x2c, 1808 IWM_NON_QOS_TX_COUNTER_CMD = 0x2d, 1809 1810 IWM_LQ_CMD = 0x4e, 1811 1812 /* Calibration */ 1813 IWM_TEMPERATURE_NOTIFICATION = 0x62, 1814 IWM_CALIBRATION_CFG_CMD = 0x65, 1815 IWM_CALIBRATION_RES_NOTIFICATION = 0x66, 1816 IWM_CALIBRATION_COMPLETE_NOTIFICATION = 0x67, 1817 IWM_RADIO_VERSION_NOTIFICATION = 0x68, 1818 1819 /* Scan offload */ 1820 IWM_SCAN_OFFLOAD_REQUEST_CMD = 0x51, 1821 IWM_SCAN_OFFLOAD_ABORT_CMD = 0x52, 1822 IWM_HOT_SPOT_CMD = 0x53, 1823 IWM_SCAN_OFFLOAD_COMPLETE = 0x6d, 1824 IWM_SCAN_OFFLOAD_UPDATE_PROFILES_CMD = 0x6e, 1825 IWM_SCAN_OFFLOAD_CONFIG_CMD = 0x6f, 1826 IWM_MATCH_FOUND_NOTIFICATION = 0xd9, 1827 IWM_SCAN_ITERATION_COMPLETE = 0xe7, 1828 1829 /* Phy */ 1830 IWM_PHY_CONFIGURATION_CMD = 0x6a, 1831 IWM_CALIB_RES_NOTIF_PHY_DB = 0x6b, 1832 /* IWM_PHY_DB_CMD = 0x6c, */ 1833 1834 /* Power - legacy power table command */ 1835 IWM_POWER_TABLE_CMD = 0x77, 1836 IWM_PSM_UAPSD_AP_MISBEHAVING_NOTIFICATION = 0x78, 1837 1838 /* Thermal Throttling*/ 1839 IWM_REPLY_THERMAL_MNG_BACKOFF = 0x7e, 1840 1841 /* Scanning */ 1842 IWM_SCAN_ABORT_CMD = 0x81, 1843 IWM_SCAN_START_NOTIFICATION = 0x82, 1844 IWM_SCAN_RESULTS_NOTIFICATION = 0x83, 1845 1846 /* NVM */ 1847 IWM_NVM_ACCESS_CMD = 0x88, 1848 1849 IWM_SET_CALIB_DEFAULT_CMD = 0x8e, 1850 1851 IWM_BEACON_NOTIFICATION = 0x90, 1852 IWM_BEACON_TEMPLATE_CMD = 0x91, 1853 IWM_TX_ANT_CONFIGURATION_CMD = 0x98, 1854 IWM_BT_CONFIG = 0x9b, 1855 IWM_STATISTICS_NOTIFICATION = 0x9d, 1856 IWM_REDUCE_TX_POWER_CMD = 0x9f, 1857 1858 /* RF-KILL commands and notifications */ 1859 IWM_CARD_STATE_CMD = 0xa0, 1860 IWM_CARD_STATE_NOTIFICATION = 0xa1, 1861 1862 IWM_MISSED_BEACONS_NOTIFICATION = 0xa2, 1863 1864 IWM_MFUART_LOAD_NOTIFICATION = 0xb1, 1865 1866 /* Power - new power table command */ 1867 IWM_MAC_PM_POWER_TABLE = 0xa9, 1868 1869 IWM_REPLY_RX_PHY_CMD = 0xc0, 1870 IWM_REPLY_RX_MPDU_CMD = 0xc1, 1871 IWM_BA_NOTIF = 0xc5, 1872 1873 /* Location Aware Regulatory */ 1874 IWM_MCC_UPDATE_CMD = 0xc8, 1875 IWM_MCC_CHUB_UPDATE_CMD = 0xc9, 1876 1877 /* BT Coex */ 1878 IWM_BT_COEX_PRIO_TABLE = 0xcc, 1879 IWM_BT_COEX_PROT_ENV = 0xcd, 1880 IWM_BT_PROFILE_NOTIFICATION = 0xce, 1881 IWM_BT_COEX_CI = 0x5d, 1882 1883 IWM_REPLY_SF_CFG_CMD = 0xd1, 1884 IWM_REPLY_BEACON_FILTERING_CMD = 0xd2, 1885 1886 /* DTS measurements */ 1887 IWM_CMD_DTS_MEASUREMENT_TRIGGER = 0xdc, 1888 IWM_DTS_MEASUREMENT_NOTIFICATION = 0xdd, 1889 1890 IWM_REPLY_DEBUG_CMD = 0xf0, 1891 IWM_DEBUG_LOG_MSG = 0xf7, 1892 1893 IWM_MCAST_FILTER_CMD = 0xd0, 1894 1895 /* D3 commands/notifications */ 1896 IWM_D3_CONFIG_CMD = 0xd3, 1897 IWM_PROT_OFFLOAD_CONFIG_CMD = 0xd4, 1898 IWM_OFFLOADS_QUERY_CMD = 0xd5, 1899 IWM_REMOTE_WAKE_CONFIG_CMD = 0xd6, 1900 1901 /* for WoWLAN in particular */ 1902 IWM_WOWLAN_PATTERNS = 0xe0, 1903 IWM_WOWLAN_CONFIGURATION = 0xe1, 1904 IWM_WOWLAN_TSC_RSC_PARAM = 0xe2, 1905 IWM_WOWLAN_TKIP_PARAM = 0xe3, 1906 IWM_WOWLAN_KEK_KCK_MATERIAL = 0xe4, 1907 IWM_WOWLAN_GET_STATUSES = 0xe5, 1908 IWM_WOWLAN_TX_POWER_PER_DB = 0xe6, 1909 1910 /* and for NetDetect */ 1911 IWM_NET_DETECT_CONFIG_CMD = 0x54, 1912 IWM_NET_DETECT_PROFILES_QUERY_CMD = 0x56, 1913 IWM_NET_DETECT_PROFILES_CMD = 0x57, 1914 IWM_NET_DETECT_HOTSPOTS_CMD = 0x58, 1915 IWM_NET_DETECT_HOTSPOTS_QUERY_CMD = 0x59, 1916 1917 IWM_REPLY_MAX = 0xff, 1918 }; 1919 1920 /** 1921 * struct iwm_cmd_response - generic response struct for most commands 1922 * @status: status of the command asked, changes for each one 1923 */ 1924 struct iwm_cmd_response { 1925 uint32_t status; 1926 }; 1927 1928 /* 1929 * struct iwm_tx_ant_cfg_cmd 1930 * @valid: valid antenna configuration 1931 */ 1932 struct iwm_tx_ant_cfg_cmd { 1933 uint32_t valid; 1934 } __packed; 1935 1936 /** 1937 * struct iwm_reduce_tx_power_cmd - TX power reduction command 1938 * IWM_REDUCE_TX_POWER_CMD = 0x9f 1939 * @flags: (reserved for future implementation) 1940 * @mac_context_id: id of the mac ctx for which we are reducing TX power. 1941 * @pwr_restriction: TX power restriction in dBms. 1942 */ 1943 struct iwm_reduce_tx_power_cmd { 1944 uint8_t flags; 1945 uint8_t mac_context_id; 1946 uint16_t pwr_restriction; 1947 } __packed; /* IWM_TX_REDUCED_POWER_API_S_VER_1 */ 1948 1949 /* 1950 * Calibration control struct. 1951 * Sent as part of the phy configuration command. 1952 * @flow_trigger: bitmap for which calibrations to perform according to 1953 * flow triggers. 1954 * @event_trigger: bitmap for which calibrations to perform according to 1955 * event triggers. 1956 */ 1957 struct iwm_calib_ctrl { 1958 uint32_t flow_trigger; 1959 uint32_t event_trigger; 1960 } __packed; 1961 1962 /* This enum defines the bitmap of various calibrations to enable in both 1963 * init ucode and runtime ucode through IWM_CALIBRATION_CFG_CMD. 1964 */ 1965 enum iwm_calib_cfg { 1966 IWM_CALIB_CFG_XTAL_IDX = (1 << 0), 1967 IWM_CALIB_CFG_TEMPERATURE_IDX = (1 << 1), 1968 IWM_CALIB_CFG_VOLTAGE_READ_IDX = (1 << 2), 1969 IWM_CALIB_CFG_PAPD_IDX = (1 << 3), 1970 IWM_CALIB_CFG_TX_PWR_IDX = (1 << 4), 1971 IWM_CALIB_CFG_DC_IDX = (1 << 5), 1972 IWM_CALIB_CFG_BB_FILTER_IDX = (1 << 6), 1973 IWM_CALIB_CFG_LO_LEAKAGE_IDX = (1 << 7), 1974 IWM_CALIB_CFG_TX_IQ_IDX = (1 << 8), 1975 IWM_CALIB_CFG_TX_IQ_SKEW_IDX = (1 << 9), 1976 IWM_CALIB_CFG_RX_IQ_IDX = (1 << 10), 1977 IWM_CALIB_CFG_RX_IQ_SKEW_IDX = (1 << 11), 1978 IWM_CALIB_CFG_SENSITIVITY_IDX = (1 << 12), 1979 IWM_CALIB_CFG_CHAIN_NOISE_IDX = (1 << 13), 1980 IWM_CALIB_CFG_DISCONNECTED_ANT_IDX = (1 << 14), 1981 IWM_CALIB_CFG_ANT_COUPLING_IDX = (1 << 15), 1982 IWM_CALIB_CFG_DAC_IDX = (1 << 16), 1983 IWM_CALIB_CFG_ABS_IDX = (1 << 17), 1984 IWM_CALIB_CFG_AGC_IDX = (1 << 18), 1985 }; 1986 1987 /* 1988 * Phy configuration command. 1989 */ 1990 struct iwm_phy_cfg_cmd { 1991 uint32_t phy_cfg; 1992 struct iwm_calib_ctrl calib_control; 1993 } __packed; 1994 1995 #define IWM_PHY_CFG_RADIO_TYPE ((1 << 0) | (1 << 1)) 1996 #define IWM_PHY_CFG_RADIO_STEP ((1 << 2) | (1 << 3)) 1997 #define IWM_PHY_CFG_RADIO_DASH ((1 << 4) | (1 << 5)) 1998 #define IWM_PHY_CFG_PRODUCT_NUMBER ((1 << 6) | (1 << 7)) 1999 #define IWM_PHY_CFG_TX_CHAIN_A (1 << 8) 2000 #define IWM_PHY_CFG_TX_CHAIN_B (1 << 9) 2001 #define IWM_PHY_CFG_TX_CHAIN_C (1 << 10) 2002 #define IWM_PHY_CFG_RX_CHAIN_A (1 << 12) 2003 #define IWM_PHY_CFG_RX_CHAIN_B (1 << 13) 2004 #define IWM_PHY_CFG_RX_CHAIN_C (1 << 14) 2005 2006 /* 2007 * PHY db 2008 */ 2009 2010 enum iwm_phy_db_section_type { 2011 IWM_PHY_DB_CFG = 1, 2012 IWM_PHY_DB_CALIB_NCH, 2013 IWM_PHY_DB_UNUSED, 2014 IWM_PHY_DB_CALIB_CHG_PAPD, 2015 IWM_PHY_DB_CALIB_CHG_TXP, 2016 IWM_PHY_DB_MAX 2017 }; 2018 2019 #define IWM_PHY_DB_CMD 0x6c /* TEMP API - The actual is 0x8c */ 2020 2021 /* 2022 * phy db - configure operational ucode 2023 */ 2024 struct iwm_phy_db_cmd { 2025 uint16_t type; 2026 uint16_t length; 2027 uint8_t data[]; 2028 } __packed; 2029 2030 /* for parsing of tx power channel group data that comes from the firmware */ 2031 struct iwm_phy_db_chg_txp { 2032 uint32_t space; 2033 uint16_t max_channel_idx; 2034 } __packed; 2035 2036 /* 2037 * phy db - Receive phy db chunk after calibrations 2038 */ 2039 struct iwm_calib_res_notif_phy_db { 2040 uint16_t type; 2041 uint16_t length; 2042 uint8_t data[]; 2043 } __packed; 2044 2045 2046 /* Target of the IWM_NVM_ACCESS_CMD */ 2047 enum { 2048 IWM_NVM_ACCESS_TARGET_CACHE = 0, 2049 IWM_NVM_ACCESS_TARGET_OTP = 1, 2050 IWM_NVM_ACCESS_TARGET_EEPROM = 2, 2051 }; 2052 2053 /* Section types for IWM_NVM_ACCESS_CMD */ 2054 enum { 2055 IWM_NVM_SECTION_TYPE_HW = 0, 2056 IWM_NVM_SECTION_TYPE_SW, 2057 IWM_NVM_SECTION_TYPE_PAPD, 2058 IWM_NVM_SECTION_TYPE_REGULATORY, 2059 IWM_NVM_SECTION_TYPE_CALIBRATION, 2060 IWM_NVM_SECTION_TYPE_PRODUCTION, 2061 IWM_NVM_SECTION_TYPE_POST_FCS_CALIB, 2062 /* 7, 8, 9 unknown */ 2063 IWM_NVM_SECTION_TYPE_HW_8000 = 10, 2064 IWM_NVM_SECTION_TYPE_MAC_OVERRIDE, 2065 IWM_NVM_SECTION_TYPE_PHY_SKU, 2066 IWM_NVM_NUM_OF_SECTIONS, 2067 }; 2068 2069 /** 2070 * struct iwm_nvm_access_cmd_ver2 - Request the device to send an NVM section 2071 * @op_code: 0 - read, 1 - write 2072 * @target: IWM_NVM_ACCESS_TARGET_* 2073 * @type: IWM_NVM_SECTION_TYPE_* 2074 * @offset: offset in bytes into the section 2075 * @length: in bytes, to read/write 2076 * @data: if write operation, the data to write. On read its empty 2077 */ 2078 struct iwm_nvm_access_cmd { 2079 uint8_t op_code; 2080 uint8_t target; 2081 uint16_t type; 2082 uint16_t offset; 2083 uint16_t length; 2084 uint8_t data[]; 2085 } __packed; /* IWM_NVM_ACCESS_CMD_API_S_VER_2 */ 2086 2087 /** 2088 * struct iwm_nvm_access_resp_ver2 - response to IWM_NVM_ACCESS_CMD 2089 * @offset: offset in bytes into the section 2090 * @length: in bytes, either how much was written or read 2091 * @type: IWM_NVM_SECTION_TYPE_* 2092 * @status: 0 for success, fail otherwise 2093 * @data: if read operation, the data returned. Empty on write. 2094 */ 2095 struct iwm_nvm_access_resp { 2096 uint16_t offset; 2097 uint16_t length; 2098 uint16_t type; 2099 uint16_t status; 2100 uint8_t data[]; 2101 } __packed; /* IWM_NVM_ACCESS_CMD_RESP_API_S_VER_2 */ 2102 2103 /* IWM_MVM_ALIVE 0x1 */ 2104 2105 /* alive response is_valid values */ 2106 #define IWM_ALIVE_RESP_UCODE_OK (1 << 0) 2107 #define IWM_ALIVE_RESP_RFKILL (1 << 1) 2108 2109 /* alive response ver_type values */ 2110 enum { 2111 IWM_FW_TYPE_HW = 0, 2112 IWM_FW_TYPE_PROT = 1, 2113 IWM_FW_TYPE_AP = 2, 2114 IWM_FW_TYPE_WOWLAN = 3, 2115 IWM_FW_TYPE_TIMING = 4, 2116 IWM_FW_TYPE_WIPAN = 5 2117 }; 2118 2119 /* alive response ver_subtype values */ 2120 enum { 2121 IWM_FW_SUBTYPE_FULL_FEATURE = 0, 2122 IWM_FW_SUBTYPE_BOOTSRAP = 1, /* Not valid */ 2123 IWM_FW_SUBTYPE_REDUCED = 2, 2124 IWM_FW_SUBTYPE_ALIVE_ONLY = 3, 2125 IWM_FW_SUBTYPE_WOWLAN = 4, 2126 IWM_FW_SUBTYPE_AP_SUBTYPE = 5, 2127 IWM_FW_SUBTYPE_WIPAN = 6, 2128 IWM_FW_SUBTYPE_INITIALIZE = 9 2129 }; 2130 2131 #define IWM_ALIVE_STATUS_ERR 0xDEAD 2132 #define IWM_ALIVE_STATUS_OK 0xCAFE 2133 2134 #define IWM_ALIVE_FLG_RFKILL (1 << 0) 2135 2136 struct iwm_mvm_alive_resp_v1 { 2137 uint16_t status; 2138 uint16_t flags; 2139 uint8_t ucode_minor; 2140 uint8_t ucode_major; 2141 uint16_t id; 2142 uint8_t api_minor; 2143 uint8_t api_major; 2144 uint8_t ver_subtype; 2145 uint8_t ver_type; 2146 uint8_t mac; 2147 uint8_t opt; 2148 uint16_t reserved2; 2149 uint32_t timestamp; 2150 uint32_t error_event_table_ptr; /* SRAM address for error log */ 2151 uint32_t log_event_table_ptr; /* SRAM address for event log */ 2152 uint32_t cpu_register_ptr; 2153 uint32_t dbgm_config_ptr; 2154 uint32_t alive_counter_ptr; 2155 uint32_t scd_base_ptr; /* SRAM address for SCD */ 2156 } __packed; /* IWM_ALIVE_RES_API_S_VER_1 */ 2157 2158 struct iwm_mvm_alive_resp_v2 { 2159 uint16_t status; 2160 uint16_t flags; 2161 uint8_t ucode_minor; 2162 uint8_t ucode_major; 2163 uint16_t id; 2164 uint8_t api_minor; 2165 uint8_t api_major; 2166 uint8_t ver_subtype; 2167 uint8_t ver_type; 2168 uint8_t mac; 2169 uint8_t opt; 2170 uint16_t reserved2; 2171 uint32_t timestamp; 2172 uint32_t error_event_table_ptr; /* SRAM address for error log */ 2173 uint32_t log_event_table_ptr; /* SRAM address for LMAC event log */ 2174 uint32_t cpu_register_ptr; 2175 uint32_t dbgm_config_ptr; 2176 uint32_t alive_counter_ptr; 2177 uint32_t scd_base_ptr; /* SRAM address for SCD */ 2178 uint32_t st_fwrd_addr; /* pointer to Store and forward */ 2179 uint32_t st_fwrd_size; 2180 uint8_t umac_minor; /* UMAC version: minor */ 2181 uint8_t umac_major; /* UMAC version: major */ 2182 uint16_t umac_id; /* UMAC version: id */ 2183 uint32_t error_info_addr; /* SRAM address for UMAC error log */ 2184 uint32_t dbg_print_buff_addr; 2185 } __packed; /* ALIVE_RES_API_S_VER_2 */ 2186 2187 struct iwm_mvm_alive_resp_v3 { 2188 uint16_t status; 2189 uint16_t flags; 2190 uint32_t ucode_minor; 2191 uint32_t ucode_major; 2192 uint8_t ver_subtype; 2193 uint8_t ver_type; 2194 uint8_t mac; 2195 uint8_t opt; 2196 uint32_t timestamp; 2197 uint32_t error_event_table_ptr; /* SRAM address for error log */ 2198 uint32_t log_event_table_ptr; /* SRAM address for LMAC event log */ 2199 uint32_t cpu_register_ptr; 2200 uint32_t dbgm_config_ptr; 2201 uint32_t alive_counter_ptr; 2202 uint32_t scd_base_ptr; /* SRAM address for SCD */ 2203 uint32_t st_fwrd_addr; /* pointer to Store and forward */ 2204 uint32_t st_fwrd_size; 2205 uint32_t umac_minor; /* UMAC version: minor */ 2206 uint32_t umac_major; /* UMAC version: major */ 2207 uint32_t error_info_addr; /* SRAM address for UMAC error log */ 2208 uint32_t dbg_print_buff_addr; 2209 } __packed; /* ALIVE_RES_API_S_VER_3 */ 2210 2211 /* Error response/notification */ 2212 enum { 2213 IWM_FW_ERR_UNKNOWN_CMD = 0x0, 2214 IWM_FW_ERR_INVALID_CMD_PARAM = 0x1, 2215 IWM_FW_ERR_SERVICE = 0x2, 2216 IWM_FW_ERR_ARC_MEMORY = 0x3, 2217 IWM_FW_ERR_ARC_CODE = 0x4, 2218 IWM_FW_ERR_WATCH_DOG = 0x5, 2219 IWM_FW_ERR_WEP_GRP_KEY_INDX = 0x10, 2220 IWM_FW_ERR_WEP_KEY_SIZE = 0x11, 2221 IWM_FW_ERR_OBSOLETE_FUNC = 0x12, 2222 IWM_FW_ERR_UNEXPECTED = 0xFE, 2223 IWM_FW_ERR_FATAL = 0xFF 2224 }; 2225 2226 /** 2227 * struct iwm_error_resp - FW error indication 2228 * ( IWM_REPLY_ERROR = 0x2 ) 2229 * @error_type: one of IWM_FW_ERR_* 2230 * @cmd_id: the command ID for which the error occurred 2231 * @bad_cmd_seq_num: sequence number of the erroneous command 2232 * @error_service: which service created the error, applicable only if 2233 * error_type = 2, otherwise 0 2234 * @timestamp: TSF in usecs. 2235 */ 2236 struct iwm_error_resp { 2237 uint32_t error_type; 2238 uint8_t cmd_id; 2239 uint8_t reserved1; 2240 uint16_t bad_cmd_seq_num; 2241 uint32_t error_service; 2242 uint64_t timestamp; 2243 } __packed; 2244 2245 2246 /* Common PHY, MAC and Bindings definitions */ 2247 2248 #define IWM_MAX_MACS_IN_BINDING (3) 2249 #define IWM_MAX_BINDINGS (4) 2250 #define IWM_AUX_BINDING_INDEX (3) 2251 #define IWM_MAX_PHYS (4) 2252 2253 /* Used to extract ID and color from the context dword */ 2254 #define IWM_FW_CTXT_ID_POS (0) 2255 #define IWM_FW_CTXT_ID_MSK (0xff << IWM_FW_CTXT_ID_POS) 2256 #define IWM_FW_CTXT_COLOR_POS (8) 2257 #define IWM_FW_CTXT_COLOR_MSK (0xff << IWM_FW_CTXT_COLOR_POS) 2258 #define IWM_FW_CTXT_INVALID (0xffffffff) 2259 2260 #define IWM_FW_CMD_ID_AND_COLOR(_id, _color) ((_id << IWM_FW_CTXT_ID_POS) |\ 2261 (_color << IWM_FW_CTXT_COLOR_POS)) 2262 2263 /* Possible actions on PHYs, MACs and Bindings */ 2264 enum { 2265 IWM_FW_CTXT_ACTION_STUB = 0, 2266 IWM_FW_CTXT_ACTION_ADD, 2267 IWM_FW_CTXT_ACTION_MODIFY, 2268 IWM_FW_CTXT_ACTION_REMOVE, 2269 IWM_FW_CTXT_ACTION_NUM 2270 }; /* COMMON_CONTEXT_ACTION_API_E_VER_1 */ 2271 2272 /* Time Events */ 2273 2274 /* Time Event types, according to MAC type */ 2275 enum iwm_time_event_type { 2276 /* BSS Station Events */ 2277 IWM_TE_BSS_STA_AGGRESSIVE_ASSOC, 2278 IWM_TE_BSS_STA_ASSOC, 2279 IWM_TE_BSS_EAP_DHCP_PROT, 2280 IWM_TE_BSS_QUIET_PERIOD, 2281 2282 /* P2P Device Events */ 2283 IWM_TE_P2P_DEVICE_DISCOVERABLE, 2284 IWM_TE_P2P_DEVICE_LISTEN, 2285 IWM_TE_P2P_DEVICE_ACTION_SCAN, 2286 IWM_TE_P2P_DEVICE_FULL_SCAN, 2287 2288 /* P2P Client Events */ 2289 IWM_TE_P2P_CLIENT_AGGRESSIVE_ASSOC, 2290 IWM_TE_P2P_CLIENT_ASSOC, 2291 IWM_TE_P2P_CLIENT_QUIET_PERIOD, 2292 2293 /* P2P GO Events */ 2294 IWM_TE_P2P_GO_ASSOC_PROT, 2295 IWM_TE_P2P_GO_REPETITIVE_NOA, 2296 IWM_TE_P2P_GO_CT_WINDOW, 2297 2298 /* WiDi Sync Events */ 2299 IWM_TE_WIDI_TX_SYNC, 2300 2301 IWM_TE_MAX 2302 }; /* IWM_MAC_EVENT_TYPE_API_E_VER_1 */ 2303 2304 2305 2306 /* Time event - defines for command API v1 */ 2307 2308 /* 2309 * @IWM_TE_V1_FRAG_NONE: fragmentation of the time event is NOT allowed. 2310 * @IWM_TE_V1_FRAG_SINGLE: fragmentation of the time event is allowed, but only 2311 * the first fragment is scheduled. 2312 * @IWM_TE_V1_FRAG_DUAL: fragmentation of the time event is allowed, but only 2313 * the first 2 fragments are scheduled. 2314 * @IWM_TE_V1_FRAG_ENDLESS: fragmentation of the time event is allowed, and any 2315 * number of fragments are valid. 2316 * 2317 * Other than the constant defined above, specifying a fragmentation value 'x' 2318 * means that the event can be fragmented but only the first 'x' will be 2319 * scheduled. 2320 */ 2321 enum { 2322 IWM_TE_V1_FRAG_NONE = 0, 2323 IWM_TE_V1_FRAG_SINGLE = 1, 2324 IWM_TE_V1_FRAG_DUAL = 2, 2325 IWM_TE_V1_FRAG_ENDLESS = 0xffffffff 2326 }; 2327 2328 /* If a Time Event can be fragmented, this is the max number of fragments */ 2329 #define IWM_TE_V1_FRAG_MAX_MSK 0x0fffffff 2330 /* Repeat the time event endlessly (until removed) */ 2331 #define IWM_TE_V1_REPEAT_ENDLESS 0xffffffff 2332 /* If a Time Event has bounded repetitions, this is the maximal value */ 2333 #define IWM_TE_V1_REPEAT_MAX_MSK_V1 0x0fffffff 2334 2335 /* Time Event dependencies: none, on another TE, or in a specific time */ 2336 enum { 2337 IWM_TE_V1_INDEPENDENT = 0, 2338 IWM_TE_V1_DEP_OTHER = (1 << 0), 2339 IWM_TE_V1_DEP_TSF = (1 << 1), 2340 IWM_TE_V1_EVENT_SOCIOPATHIC = (1 << 2), 2341 }; /* IWM_MAC_EVENT_DEPENDENCY_POLICY_API_E_VER_2 */ 2342 2343 /* 2344 * @IWM_TE_V1_NOTIF_NONE: no notifications 2345 * @IWM_TE_V1_NOTIF_HOST_EVENT_START: request/receive notification on event start 2346 * @IWM_TE_V1_NOTIF_HOST_EVENT_END:request/receive notification on event end 2347 * @IWM_TE_V1_NOTIF_INTERNAL_EVENT_START: internal FW use 2348 * @IWM_TE_V1_NOTIF_INTERNAL_EVENT_END: internal FW use. 2349 * @IWM_TE_V1_NOTIF_HOST_FRAG_START: request/receive notification on frag start 2350 * @IWM_TE_V1_NOTIF_HOST_FRAG_END:request/receive notification on frag end 2351 * @IWM_TE_V1_NOTIF_INTERNAL_FRAG_START: internal FW use. 2352 * @IWM_TE_V1_NOTIF_INTERNAL_FRAG_END: internal FW use. 2353 * 2354 * Supported Time event notifications configuration. 2355 * A notification (both event and fragment) includes a status indicating weather 2356 * the FW was able to schedule the event or not. For fragment start/end 2357 * notification the status is always success. There is no start/end fragment 2358 * notification for monolithic events. 2359 */ 2360 enum { 2361 IWM_TE_V1_NOTIF_NONE = 0, 2362 IWM_TE_V1_NOTIF_HOST_EVENT_START = (1 << 0), 2363 IWM_TE_V1_NOTIF_HOST_EVENT_END = (1 << 1), 2364 IWM_TE_V1_NOTIF_INTERNAL_EVENT_START = (1 << 2), 2365 IWM_TE_V1_NOTIF_INTERNAL_EVENT_END = (1 << 3), 2366 IWM_TE_V1_NOTIF_HOST_FRAG_START = (1 << 4), 2367 IWM_TE_V1_NOTIF_HOST_FRAG_END = (1 << 5), 2368 IWM_TE_V1_NOTIF_INTERNAL_FRAG_START = (1 << 6), 2369 IWM_TE_V1_NOTIF_INTERNAL_FRAG_END = (1 << 7), 2370 IWM_T2_V2_START_IMMEDIATELY = (1 << 11), 2371 }; /* IWM_MAC_EVENT_ACTION_API_E_VER_2 */ 2372 2373 2374 /** 2375 * struct iwm_time_event_cmd_api_v1 - configuring Time Events 2376 * with struct IWM_MAC_TIME_EVENT_DATA_API_S_VER_1 (see also 2377 * with version 2. determined by IWM_UCODE_TLV_FLAGS) 2378 * ( IWM_TIME_EVENT_CMD = 0x29 ) 2379 * @id_and_color: ID and color of the relevant MAC 2380 * @action: action to perform, one of IWM_FW_CTXT_ACTION_* 2381 * @id: this field has two meanings, depending on the action: 2382 * If the action is ADD, then it means the type of event to add. 2383 * For all other actions it is the unique event ID assigned when the 2384 * event was added by the FW. 2385 * @apply_time: When to start the Time Event (in GP2) 2386 * @max_delay: maximum delay to event's start (apply time), in TU 2387 * @depends_on: the unique ID of the event we depend on (if any) 2388 * @interval: interval between repetitions, in TU 2389 * @interval_reciprocal: 2^32 / interval 2390 * @duration: duration of event in TU 2391 * @repeat: how many repetitions to do, can be IWM_TE_REPEAT_ENDLESS 2392 * @dep_policy: one of IWM_TE_V1_INDEPENDENT, IWM_TE_V1_DEP_OTHER, IWM_TE_V1_DEP_TSF 2393 * and IWM_TE_V1_EVENT_SOCIOPATHIC 2394 * @is_present: 0 or 1, are we present or absent during the Time Event 2395 * @max_frags: maximal number of fragments the Time Event can be divided to 2396 * @notify: notifications using IWM_TE_V1_NOTIF_* (whom to notify when) 2397 */ 2398 struct iwm_time_event_cmd_v1 { 2399 /* COMMON_INDEX_HDR_API_S_VER_1 */ 2400 uint32_t id_and_color; 2401 uint32_t action; 2402 uint32_t id; 2403 /* IWM_MAC_TIME_EVENT_DATA_API_S_VER_1 */ 2404 uint32_t apply_time; 2405 uint32_t max_delay; 2406 uint32_t dep_policy; 2407 uint32_t depends_on; 2408 uint32_t is_present; 2409 uint32_t max_frags; 2410 uint32_t interval; 2411 uint32_t interval_reciprocal; 2412 uint32_t duration; 2413 uint32_t repeat; 2414 uint32_t notify; 2415 } __packed; /* IWM_MAC_TIME_EVENT_CMD_API_S_VER_1 */ 2416 2417 2418 /* Time event - defines for command API v2 */ 2419 2420 /* 2421 * @IWM_TE_V2_FRAG_NONE: fragmentation of the time event is NOT allowed. 2422 * @IWM_TE_V2_FRAG_SINGLE: fragmentation of the time event is allowed, but only 2423 * the first fragment is scheduled. 2424 * @IWM_TE_V2_FRAG_DUAL: fragmentation of the time event is allowed, but only 2425 * the first 2 fragments are scheduled. 2426 * @IWM_TE_V2_FRAG_ENDLESS: fragmentation of the time event is allowed, and any 2427 * number of fragments are valid. 2428 * 2429 * Other than the constant defined above, specifying a fragmentation value 'x' 2430 * means that the event can be fragmented but only the first 'x' will be 2431 * scheduled. 2432 */ 2433 enum { 2434 IWM_TE_V2_FRAG_NONE = 0, 2435 IWM_TE_V2_FRAG_SINGLE = 1, 2436 IWM_TE_V2_FRAG_DUAL = 2, 2437 IWM_TE_V2_FRAG_MAX = 0xfe, 2438 IWM_TE_V2_FRAG_ENDLESS = 0xff 2439 }; 2440 2441 /* Repeat the time event endlessly (until removed) */ 2442 #define IWM_TE_V2_REPEAT_ENDLESS 0xff 2443 /* If a Time Event has bounded repetitions, this is the maximal value */ 2444 #define IWM_TE_V2_REPEAT_MAX 0xfe 2445 2446 #define IWM_TE_V2_PLACEMENT_POS 12 2447 #define IWM_TE_V2_ABSENCE_POS 15 2448 2449 /* Time event policy values (for time event cmd api v2) 2450 * A notification (both event and fragment) includes a status indicating weather 2451 * the FW was able to schedule the event or not. For fragment start/end 2452 * notification the status is always success. There is no start/end fragment 2453 * notification for monolithic events. 2454 * 2455 * @IWM_TE_V2_DEFAULT_POLICY: independent, social, present, unoticable 2456 * @IWM_TE_V2_NOTIF_HOST_EVENT_START: request/receive notification on event start 2457 * @IWM_TE_V2_NOTIF_HOST_EVENT_END:request/receive notification on event end 2458 * @IWM_TE_V2_NOTIF_INTERNAL_EVENT_START: internal FW use 2459 * @IWM_TE_V2_NOTIF_INTERNAL_EVENT_END: internal FW use. 2460 * @IWM_TE_V2_NOTIF_HOST_FRAG_START: request/receive notification on frag start 2461 * @IWM_TE_V2_NOTIF_HOST_FRAG_END:request/receive notification on frag end 2462 * @IWM_TE_V2_NOTIF_INTERNAL_FRAG_START: internal FW use. 2463 * @IWM_TE_V2_NOTIF_INTERNAL_FRAG_END: internal FW use. 2464 * @IWM_TE_V2_DEP_OTHER: depends on another time event 2465 * @IWM_TE_V2_DEP_TSF: depends on a specific time 2466 * @IWM_TE_V2_EVENT_SOCIOPATHIC: can't co-exist with other events of tha same MAC 2467 * @IWM_TE_V2_ABSENCE: are we present or absent during the Time Event. 2468 */ 2469 enum { 2470 IWM_TE_V2_DEFAULT_POLICY = 0x0, 2471 2472 /* notifications (event start/stop, fragment start/stop) */ 2473 IWM_TE_V2_NOTIF_HOST_EVENT_START = (1 << 0), 2474 IWM_TE_V2_NOTIF_HOST_EVENT_END = (1 << 1), 2475 IWM_TE_V2_NOTIF_INTERNAL_EVENT_START = (1 << 2), 2476 IWM_TE_V2_NOTIF_INTERNAL_EVENT_END = (1 << 3), 2477 2478 IWM_TE_V2_NOTIF_HOST_FRAG_START = (1 << 4), 2479 IWM_TE_V2_NOTIF_HOST_FRAG_END = (1 << 5), 2480 IWM_TE_V2_NOTIF_INTERNAL_FRAG_START = (1 << 6), 2481 IWM_TE_V2_NOTIF_INTERNAL_FRAG_END = (1 << 7), 2482 2483 IWM_TE_V2_NOTIF_MSK = 0xff, 2484 2485 /* placement characteristics */ 2486 IWM_TE_V2_DEP_OTHER = (1 << IWM_TE_V2_PLACEMENT_POS), 2487 IWM_TE_V2_DEP_TSF = (1 << (IWM_TE_V2_PLACEMENT_POS + 1)), 2488 IWM_TE_V2_EVENT_SOCIOPATHIC = (1 << (IWM_TE_V2_PLACEMENT_POS + 2)), 2489 2490 /* are we present or absent during the Time Event. */ 2491 IWM_TE_V2_ABSENCE = (1 << IWM_TE_V2_ABSENCE_POS), 2492 }; 2493 2494 /** 2495 * struct iwm_time_event_cmd_api_v2 - configuring Time Events 2496 * with struct IWM_MAC_TIME_EVENT_DATA_API_S_VER_2 (see also 2497 * with version 1. determined by IWM_UCODE_TLV_FLAGS) 2498 * ( IWM_TIME_EVENT_CMD = 0x29 ) 2499 * @id_and_color: ID and color of the relevant MAC 2500 * @action: action to perform, one of IWM_FW_CTXT_ACTION_* 2501 * @id: this field has two meanings, depending on the action: 2502 * If the action is ADD, then it means the type of event to add. 2503 * For all other actions it is the unique event ID assigned when the 2504 * event was added by the FW. 2505 * @apply_time: When to start the Time Event (in GP2) 2506 * @max_delay: maximum delay to event's start (apply time), in TU 2507 * @depends_on: the unique ID of the event we depend on (if any) 2508 * @interval: interval between repetitions, in TU 2509 * @duration: duration of event in TU 2510 * @repeat: how many repetitions to do, can be IWM_TE_REPEAT_ENDLESS 2511 * @max_frags: maximal number of fragments the Time Event can be divided to 2512 * @policy: defines whether uCode shall notify the host or other uCode modules 2513 * on event and/or fragment start and/or end 2514 * using one of IWM_TE_INDEPENDENT, IWM_TE_DEP_OTHER, IWM_TE_DEP_TSF 2515 * IWM_TE_EVENT_SOCIOPATHIC 2516 * using IWM_TE_ABSENCE and using IWM_TE_NOTIF_* 2517 */ 2518 struct iwm_time_event_cmd_v2 { 2519 /* COMMON_INDEX_HDR_API_S_VER_1 */ 2520 uint32_t id_and_color; 2521 uint32_t action; 2522 uint32_t id; 2523 /* IWM_MAC_TIME_EVENT_DATA_API_S_VER_2 */ 2524 uint32_t apply_time; 2525 uint32_t max_delay; 2526 uint32_t depends_on; 2527 uint32_t interval; 2528 uint32_t duration; 2529 uint8_t repeat; 2530 uint8_t max_frags; 2531 uint16_t policy; 2532 } __packed; /* IWM_MAC_TIME_EVENT_CMD_API_S_VER_2 */ 2533 2534 /** 2535 * struct iwm_time_event_resp - response structure to iwm_time_event_cmd 2536 * @status: bit 0 indicates success, all others specify errors 2537 * @id: the Time Event type 2538 * @unique_id: the unique ID assigned (in ADD) or given (others) to the TE 2539 * @id_and_color: ID and color of the relevant MAC 2540 */ 2541 struct iwm_time_event_resp { 2542 uint32_t status; 2543 uint32_t id; 2544 uint32_t unique_id; 2545 uint32_t id_and_color; 2546 } __packed; /* IWM_MAC_TIME_EVENT_RSP_API_S_VER_1 */ 2547 2548 /** 2549 * struct iwm_time_event_notif - notifications of time event start/stop 2550 * ( IWM_TIME_EVENT_NOTIFICATION = 0x2a ) 2551 * @timestamp: action timestamp in GP2 2552 * @session_id: session's unique id 2553 * @unique_id: unique id of the Time Event itself 2554 * @id_and_color: ID and color of the relevant MAC 2555 * @action: one of IWM_TE_NOTIF_START or IWM_TE_NOTIF_END 2556 * @status: true if scheduled, false otherwise (not executed) 2557 */ 2558 struct iwm_time_event_notif { 2559 uint32_t timestamp; 2560 uint32_t session_id; 2561 uint32_t unique_id; 2562 uint32_t id_and_color; 2563 uint32_t action; 2564 uint32_t status; 2565 } __packed; /* IWM_MAC_TIME_EVENT_NTFY_API_S_VER_1 */ 2566 2567 2568 /* Bindings and Time Quota */ 2569 2570 /** 2571 * struct iwm_binding_cmd - configuring bindings 2572 * ( IWM_BINDING_CONTEXT_CMD = 0x2b ) 2573 * @id_and_color: ID and color of the relevant Binding 2574 * @action: action to perform, one of IWM_FW_CTXT_ACTION_* 2575 * @macs: array of MAC id and colors which belong to the binding 2576 * @phy: PHY id and color which belongs to the binding 2577 */ 2578 struct iwm_binding_cmd { 2579 /* COMMON_INDEX_HDR_API_S_VER_1 */ 2580 uint32_t id_and_color; 2581 uint32_t action; 2582 /* IWM_BINDING_DATA_API_S_VER_1 */ 2583 uint32_t macs[IWM_MAX_MACS_IN_BINDING]; 2584 uint32_t phy; 2585 } __packed; /* IWM_BINDING_CMD_API_S_VER_1 */ 2586 2587 /* The maximal number of fragments in the FW's schedule session */ 2588 #define IWM_MVM_MAX_QUOTA 128 2589 2590 /** 2591 * struct iwm_time_quota_data - configuration of time quota per binding 2592 * @id_and_color: ID and color of the relevant Binding 2593 * @quota: absolute time quota in TU. The scheduler will try to divide the 2594 * remainig quota (after Time Events) according to this quota. 2595 * @max_duration: max uninterrupted context duration in TU 2596 */ 2597 struct iwm_time_quota_data { 2598 uint32_t id_and_color; 2599 uint32_t quota; 2600 uint32_t max_duration; 2601 } __packed; /* IWM_TIME_QUOTA_DATA_API_S_VER_1 */ 2602 2603 /** 2604 * struct iwm_time_quota_cmd - configuration of time quota between bindings 2605 * ( IWM_TIME_QUOTA_CMD = 0x2c ) 2606 * @quotas: allocations per binding 2607 */ 2608 struct iwm_time_quota_cmd { 2609 struct iwm_time_quota_data quotas[IWM_MAX_BINDINGS]; 2610 } __packed; /* IWM_TIME_QUOTA_ALLOCATION_CMD_API_S_VER_1 */ 2611 2612 2613 /* PHY context */ 2614 2615 /* Supported bands */ 2616 #define IWM_PHY_BAND_5 (0) 2617 #define IWM_PHY_BAND_24 (1) 2618 2619 /* Supported channel width, vary if there is VHT support */ 2620 #define IWM_PHY_VHT_CHANNEL_MODE20 (0x0) 2621 #define IWM_PHY_VHT_CHANNEL_MODE40 (0x1) 2622 #define IWM_PHY_VHT_CHANNEL_MODE80 (0x2) 2623 #define IWM_PHY_VHT_CHANNEL_MODE160 (0x3) 2624 2625 /* 2626 * Control channel position: 2627 * For legacy set bit means upper channel, otherwise lower. 2628 * For VHT - bit-2 marks if the control is lower/upper relative to center-freq 2629 * bits-1:0 mark the distance from the center freq. for 20Mhz, offset is 0. 2630 * center_freq 2631 * | 2632 * 40Mhz |_______|_______| 2633 * 80Mhz |_______|_______|_______|_______| 2634 * 160Mhz |_______|_______|_______|_______|_______|_______|_______|_______| 2635 * code 011 010 001 000 | 100 101 110 111 2636 */ 2637 #define IWM_PHY_VHT_CTRL_POS_1_BELOW (0x0) 2638 #define IWM_PHY_VHT_CTRL_POS_2_BELOW (0x1) 2639 #define IWM_PHY_VHT_CTRL_POS_3_BELOW (0x2) 2640 #define IWM_PHY_VHT_CTRL_POS_4_BELOW (0x3) 2641 #define IWM_PHY_VHT_CTRL_POS_1_ABOVE (0x4) 2642 #define IWM_PHY_VHT_CTRL_POS_2_ABOVE (0x5) 2643 #define IWM_PHY_VHT_CTRL_POS_3_ABOVE (0x6) 2644 #define IWM_PHY_VHT_CTRL_POS_4_ABOVE (0x7) 2645 2646 /* 2647 * @band: IWM_PHY_BAND_* 2648 * @channel: channel number 2649 * @width: PHY_[VHT|LEGACY]_CHANNEL_* 2650 * @ctrl channel: PHY_[VHT|LEGACY]_CTRL_* 2651 */ 2652 struct iwm_fw_channel_info { 2653 uint8_t band; 2654 uint8_t channel; 2655 uint8_t width; 2656 uint8_t ctrl_pos; 2657 } __packed; 2658 2659 #define IWM_PHY_RX_CHAIN_DRIVER_FORCE_POS (0) 2660 #define IWM_PHY_RX_CHAIN_DRIVER_FORCE_MSK \ 2661 (0x1 << IWM_PHY_RX_CHAIN_DRIVER_FORCE_POS) 2662 #define IWM_PHY_RX_CHAIN_VALID_POS (1) 2663 #define IWM_PHY_RX_CHAIN_VALID_MSK \ 2664 (0x7 << IWM_PHY_RX_CHAIN_VALID_POS) 2665 #define IWM_PHY_RX_CHAIN_FORCE_SEL_POS (4) 2666 #define IWM_PHY_RX_CHAIN_FORCE_SEL_MSK \ 2667 (0x7 << IWM_PHY_RX_CHAIN_FORCE_SEL_POS) 2668 #define IWM_PHY_RX_CHAIN_FORCE_MIMO_SEL_POS (7) 2669 #define IWM_PHY_RX_CHAIN_FORCE_MIMO_SEL_MSK \ 2670 (0x7 << IWM_PHY_RX_CHAIN_FORCE_MIMO_SEL_POS) 2671 #define IWM_PHY_RX_CHAIN_CNT_POS (10) 2672 #define IWM_PHY_RX_CHAIN_CNT_MSK \ 2673 (0x3 << IWM_PHY_RX_CHAIN_CNT_POS) 2674 #define IWM_PHY_RX_CHAIN_MIMO_CNT_POS (12) 2675 #define IWM_PHY_RX_CHAIN_MIMO_CNT_MSK \ 2676 (0x3 << IWM_PHY_RX_CHAIN_MIMO_CNT_POS) 2677 #define IWM_PHY_RX_CHAIN_MIMO_FORCE_POS (14) 2678 #define IWM_PHY_RX_CHAIN_MIMO_FORCE_MSK \ 2679 (0x1 << IWM_PHY_RX_CHAIN_MIMO_FORCE_POS) 2680 2681 /* TODO: fix the value, make it depend on firmware at runtime? */ 2682 #define IWM_NUM_PHY_CTX 3 2683 2684 /* TODO: complete missing documentation */ 2685 /** 2686 * struct iwm_phy_context_cmd - config of the PHY context 2687 * ( IWM_PHY_CONTEXT_CMD = 0x8 ) 2688 * @id_and_color: ID and color of the relevant Binding 2689 * @action: action to perform, one of IWM_FW_CTXT_ACTION_* 2690 * @apply_time: 0 means immediate apply and context switch. 2691 * other value means apply new params after X usecs 2692 * @tx_param_color: ??? 2693 * @channel_info: 2694 * @txchain_info: ??? 2695 * @rxchain_info: ??? 2696 * @acquisition_data: ??? 2697 * @dsp_cfg_flags: set to 0 2698 */ 2699 struct iwm_phy_context_cmd { 2700 /* COMMON_INDEX_HDR_API_S_VER_1 */ 2701 uint32_t id_and_color; 2702 uint32_t action; 2703 /* IWM_PHY_CONTEXT_DATA_API_S_VER_1 */ 2704 uint32_t apply_time; 2705 uint32_t tx_param_color; 2706 struct iwm_fw_channel_info ci; 2707 uint32_t txchain_info; 2708 uint32_t rxchain_info; 2709 uint32_t acquisition_data; 2710 uint32_t dsp_cfg_flags; 2711 } __packed; /* IWM_PHY_CONTEXT_CMD_API_VER_1 */ 2712 2713 #define IWM_RX_INFO_PHY_CNT 8 2714 #define IWM_RX_INFO_ENERGY_ANT_ABC_IDX 1 2715 #define IWM_RX_INFO_ENERGY_ANT_A_MSK 0x000000ff 2716 #define IWM_RX_INFO_ENERGY_ANT_B_MSK 0x0000ff00 2717 #define IWM_RX_INFO_ENERGY_ANT_C_MSK 0x00ff0000 2718 #define IWM_RX_INFO_ENERGY_ANT_A_POS 0 2719 #define IWM_RX_INFO_ENERGY_ANT_B_POS 8 2720 #define IWM_RX_INFO_ENERGY_ANT_C_POS 16 2721 2722 #define IWM_RX_INFO_AGC_IDX 1 2723 #define IWM_RX_INFO_RSSI_AB_IDX 2 2724 #define IWM_OFDM_AGC_A_MSK 0x0000007f 2725 #define IWM_OFDM_AGC_A_POS 0 2726 #define IWM_OFDM_AGC_B_MSK 0x00003f80 2727 #define IWM_OFDM_AGC_B_POS 7 2728 #define IWM_OFDM_AGC_CODE_MSK 0x3fe00000 2729 #define IWM_OFDM_AGC_CODE_POS 20 2730 #define IWM_OFDM_RSSI_INBAND_A_MSK 0x00ff 2731 #define IWM_OFDM_RSSI_A_POS 0 2732 #define IWM_OFDM_RSSI_ALLBAND_A_MSK 0xff00 2733 #define IWM_OFDM_RSSI_ALLBAND_A_POS 8 2734 #define IWM_OFDM_RSSI_INBAND_B_MSK 0xff0000 2735 #define IWM_OFDM_RSSI_B_POS 16 2736 #define IWM_OFDM_RSSI_ALLBAND_B_MSK 0xff000000 2737 #define IWM_OFDM_RSSI_ALLBAND_B_POS 24 2738 2739 /** 2740 * struct iwm_rx_phy_info - phy info 2741 * (IWM_REPLY_RX_PHY_CMD = 0xc0) 2742 * @non_cfg_phy_cnt: non configurable DSP phy data byte count 2743 * @cfg_phy_cnt: configurable DSP phy data byte count 2744 * @stat_id: configurable DSP phy data set ID 2745 * @reserved1: 2746 * @system_timestamp: GP2 at on air rise 2747 * @timestamp: TSF at on air rise 2748 * @beacon_time_stamp: beacon at on-air rise 2749 * @phy_flags: general phy flags: band, modulation, ... 2750 * @channel: channel number 2751 * @non_cfg_phy_buf: for various implementations of non_cfg_phy 2752 * @rate_n_flags: IWM_RATE_MCS_* 2753 * @byte_count: frame's byte-count 2754 * @frame_time: frame's time on the air, based on byte count and frame rate 2755 * calculation 2756 * @mac_active_msk: what MACs were active when the frame was received 2757 * 2758 * Before each Rx, the device sends this data. It contains PHY information 2759 * about the reception of the packet. 2760 */ 2761 struct iwm_rx_phy_info { 2762 uint8_t non_cfg_phy_cnt; 2763 uint8_t cfg_phy_cnt; 2764 uint8_t stat_id; 2765 uint8_t reserved1; 2766 uint32_t system_timestamp; 2767 uint64_t timestamp; 2768 uint32_t beacon_time_stamp; 2769 uint16_t phy_flags; 2770 #define IWM_PHY_INFO_FLAG_SHPREAMBLE (1 << 2) 2771 uint16_t channel; 2772 uint32_t non_cfg_phy[IWM_RX_INFO_PHY_CNT]; 2773 uint8_t rate; 2774 uint8_t rflags; 2775 uint16_t xrflags; 2776 uint32_t byte_count; 2777 uint16_t mac_active_msk; 2778 uint16_t frame_time; 2779 } __packed; 2780 2781 struct iwm_rx_mpdu_res_start { 2782 uint16_t byte_count; 2783 uint16_t reserved; 2784 } __packed; 2785 2786 /** 2787 * enum iwm_rx_phy_flags - to parse %iwm_rx_phy_info phy_flags 2788 * @IWM_RX_RES_PHY_FLAGS_BAND_24: true if the packet was received on 2.4 band 2789 * @IWM_RX_RES_PHY_FLAGS_MOD_CCK: 2790 * @IWM_RX_RES_PHY_FLAGS_SHORT_PREAMBLE: true if packet's preamble was short 2791 * @IWM_RX_RES_PHY_FLAGS_NARROW_BAND: 2792 * @IWM_RX_RES_PHY_FLAGS_ANTENNA: antenna on which the packet was received 2793 * @IWM_RX_RES_PHY_FLAGS_AGG: set if the packet was part of an A-MPDU 2794 * @IWM_RX_RES_PHY_FLAGS_OFDM_HT: The frame was an HT frame 2795 * @IWM_RX_RES_PHY_FLAGS_OFDM_GF: The frame used GF preamble 2796 * @IWM_RX_RES_PHY_FLAGS_OFDM_VHT: The frame was a VHT frame 2797 */ 2798 enum iwm_rx_phy_flags { 2799 IWM_RX_RES_PHY_FLAGS_BAND_24 = (1 << 0), 2800 IWM_RX_RES_PHY_FLAGS_MOD_CCK = (1 << 1), 2801 IWM_RX_RES_PHY_FLAGS_SHORT_PREAMBLE = (1 << 2), 2802 IWM_RX_RES_PHY_FLAGS_NARROW_BAND = (1 << 3), 2803 IWM_RX_RES_PHY_FLAGS_ANTENNA = (0x7 << 4), 2804 IWM_RX_RES_PHY_FLAGS_ANTENNA_POS = 4, 2805 IWM_RX_RES_PHY_FLAGS_AGG = (1 << 7), 2806 IWM_RX_RES_PHY_FLAGS_OFDM_HT = (1 << 8), 2807 IWM_RX_RES_PHY_FLAGS_OFDM_GF = (1 << 9), 2808 IWM_RX_RES_PHY_FLAGS_OFDM_VHT = (1 << 10), 2809 }; 2810 2811 /** 2812 * enum iwm_mvm_rx_status - written by fw for each Rx packet 2813 * @IWM_RX_MPDU_RES_STATUS_CRC_OK: CRC is fine 2814 * @IWM_RX_MPDU_RES_STATUS_OVERRUN_OK: there was no RXE overflow 2815 * @IWM_RX_MPDU_RES_STATUS_SRC_STA_FOUND: 2816 * @IWM_RX_MPDU_RES_STATUS_KEY_VALID: 2817 * @IWM_RX_MPDU_RES_STATUS_KEY_PARAM_OK: 2818 * @IWM_RX_MPDU_RES_STATUS_ICV_OK: ICV is fine, if not, the packet is destroyed 2819 * @IWM_RX_MPDU_RES_STATUS_MIC_OK: used for CCM alg only. TKIP MIC is checked 2820 * in the driver. 2821 * @IWM_RX_MPDU_RES_STATUS_TTAK_OK: TTAK is fine 2822 * @IWM_RX_MPDU_RES_STATUS_MNG_FRAME_REPLAY_ERR: valid for alg = CCM_CMAC or 2823 * alg = CCM only. Checks replay attack for 11w frames. Relevant only if 2824 * %IWM_RX_MPDU_RES_STATUS_ROBUST_MNG_FRAME is set. 2825 * @IWM_RX_MPDU_RES_STATUS_SEC_NO_ENC: this frame is not encrypted 2826 * @IWM_RX_MPDU_RES_STATUS_SEC_WEP_ENC: this frame is encrypted using WEP 2827 * @IWM_RX_MPDU_RES_STATUS_SEC_CCM_ENC: this frame is encrypted using CCM 2828 * @IWM_RX_MPDU_RES_STATUS_SEC_TKIP_ENC: this frame is encrypted using TKIP 2829 * @IWM_RX_MPDU_RES_STATUS_SEC_CCM_CMAC_ENC: this frame is encrypted using CCM_CMAC 2830 * @IWM_RX_MPDU_RES_STATUS_SEC_ENC_ERR: this frame couldn't be decrypted 2831 * @IWM_RX_MPDU_RES_STATUS_SEC_ENC_MSK: bitmask of the encryption algorithm 2832 * @IWM_RX_MPDU_RES_STATUS_DEC_DONE: this frame has been successfully decrypted 2833 * @IWM_RX_MPDU_RES_STATUS_PROTECT_FRAME_BIT_CMP: 2834 * @IWM_RX_MPDU_RES_STATUS_EXT_IV_BIT_CMP: 2835 * @IWM_RX_MPDU_RES_STATUS_KEY_ID_CMP_BIT: 2836 * @IWM_RX_MPDU_RES_STATUS_ROBUST_MNG_FRAME: this frame is an 11w management frame 2837 * @IWM_RX_MPDU_RES_STATUS_HASH_INDEX_MSK: 2838 * @IWM_RX_MPDU_RES_STATUS_STA_ID_MSK: 2839 * @IWM_RX_MPDU_RES_STATUS_RRF_KILL: 2840 * @IWM_RX_MPDU_RES_STATUS_FILTERING_MSK: 2841 * @IWM_RX_MPDU_RES_STATUS2_FILTERING_MSK: 2842 */ 2843 enum iwm_mvm_rx_status { 2844 IWM_RX_MPDU_RES_STATUS_CRC_OK = (1 << 0), 2845 IWM_RX_MPDU_RES_STATUS_OVERRUN_OK = (1 << 1), 2846 IWM_RX_MPDU_RES_STATUS_SRC_STA_FOUND = (1 << 2), 2847 IWM_RX_MPDU_RES_STATUS_KEY_VALID = (1 << 3), 2848 IWM_RX_MPDU_RES_STATUS_KEY_PARAM_OK = (1 << 4), 2849 IWM_RX_MPDU_RES_STATUS_ICV_OK = (1 << 5), 2850 IWM_RX_MPDU_RES_STATUS_MIC_OK = (1 << 6), 2851 IWM_RX_MPDU_RES_STATUS_TTAK_OK = (1 << 7), 2852 IWM_RX_MPDU_RES_STATUS_MNG_FRAME_REPLAY_ERR = (1 << 7), 2853 IWM_RX_MPDU_RES_STATUS_SEC_NO_ENC = (0 << 8), 2854 IWM_RX_MPDU_RES_STATUS_SEC_WEP_ENC = (1 << 8), 2855 IWM_RX_MPDU_RES_STATUS_SEC_CCM_ENC = (2 << 8), 2856 IWM_RX_MPDU_RES_STATUS_SEC_TKIP_ENC = (3 << 8), 2857 IWM_RX_MPDU_RES_STATUS_SEC_EXT_ENC = (4 << 8), 2858 IWM_RX_MPDU_RES_STATUS_SEC_CCM_CMAC_ENC = (6 << 8), 2859 IWM_RX_MPDU_RES_STATUS_SEC_ENC_ERR = (7 << 8), 2860 IWM_RX_MPDU_RES_STATUS_SEC_ENC_MSK = (7 << 8), 2861 IWM_RX_MPDU_RES_STATUS_DEC_DONE = (1 << 11), 2862 IWM_RX_MPDU_RES_STATUS_PROTECT_FRAME_BIT_CMP = (1 << 12), 2863 IWM_RX_MPDU_RES_STATUS_EXT_IV_BIT_CMP = (1 << 13), 2864 IWM_RX_MPDU_RES_STATUS_KEY_ID_CMP_BIT = (1 << 14), 2865 IWM_RX_MPDU_RES_STATUS_ROBUST_MNG_FRAME = (1 << 15), 2866 IWM_RX_MPDU_RES_STATUS_HASH_INDEX_MSK = (0x3F0000), 2867 IWM_RX_MPDU_RES_STATUS_STA_ID_MSK = (0x1f000000), 2868 IWM_RX_MPDU_RES_STATUS_RRF_KILL = (1 << 29), 2869 IWM_RX_MPDU_RES_STATUS_FILTERING_MSK = (0xc00000), 2870 IWM_RX_MPDU_RES_STATUS2_FILTERING_MSK = (0xc0000000), 2871 }; 2872 2873 /** 2874 * struct iwm_radio_version_notif - information on the radio version 2875 * ( IWM_RADIO_VERSION_NOTIFICATION = 0x68 ) 2876 * @radio_flavor: 2877 * @radio_step: 2878 * @radio_dash: 2879 */ 2880 struct iwm_radio_version_notif { 2881 uint32_t radio_flavor; 2882 uint32_t radio_step; 2883 uint32_t radio_dash; 2884 } __packed; /* IWM_RADIO_VERSION_NOTOFICATION_S_VER_1 */ 2885 2886 enum iwm_card_state_flags { 2887 IWM_CARD_ENABLED = 0x00, 2888 IWM_HW_CARD_DISABLED = 0x01, 2889 IWM_SW_CARD_DISABLED = 0x02, 2890 IWM_CT_KILL_CARD_DISABLED = 0x04, 2891 IWM_HALT_CARD_DISABLED = 0x08, 2892 IWM_CARD_DISABLED_MSK = 0x0f, 2893 IWM_CARD_IS_RX_ON = 0x10, 2894 }; 2895 2896 /** 2897 * struct iwm_radio_version_notif - information on the radio version 2898 * (IWM_CARD_STATE_NOTIFICATION = 0xa1 ) 2899 * @flags: %iwm_card_state_flags 2900 */ 2901 struct iwm_card_state_notif { 2902 uint32_t flags; 2903 } __packed; /* CARD_STATE_NTFY_API_S_VER_1 */ 2904 2905 /** 2906 * struct iwm_missed_beacons_notif - information on missed beacons 2907 * ( IWM_MISSED_BEACONS_NOTIFICATION = 0xa2 ) 2908 * @mac_id: interface ID 2909 * @consec_missed_beacons_since_last_rx: number of consecutive missed 2910 * beacons since last RX. 2911 * @consec_missed_beacons: number of consecutive missed beacons 2912 * @num_expected_beacons: 2913 * @num_recvd_beacons: 2914 */ 2915 struct iwm_missed_beacons_notif { 2916 uint32_t mac_id; 2917 uint32_t consec_missed_beacons_since_last_rx; 2918 uint32_t consec_missed_beacons; 2919 uint32_t num_expected_beacons; 2920 uint32_t num_recvd_beacons; 2921 } __packed; /* IWM_MISSED_BEACON_NTFY_API_S_VER_3 */ 2922 2923 /** 2924 * struct iwm_mfuart_load_notif - mfuart image version & status 2925 * ( IWM_MFUART_LOAD_NOTIFICATION = 0xb1 ) 2926 * @installed_ver: installed image version 2927 * @external_ver: external image version 2928 * @status: MFUART loading status 2929 * @duration: MFUART loading time 2930 */ 2931 struct iwm_mfuart_load_notif { 2932 uint32_t installed_ver; 2933 uint32_t external_ver; 2934 uint32_t status; 2935 uint32_t duration; 2936 } __packed; /*MFU_LOADER_NTFY_API_S_VER_1*/ 2937 2938 /** 2939 * struct iwm_set_calib_default_cmd - set default value for calibration. 2940 * ( IWM_SET_CALIB_DEFAULT_CMD = 0x8e ) 2941 * @calib_index: the calibration to set value for 2942 * @length: of data 2943 * @data: the value to set for the calibration result 2944 */ 2945 struct iwm_set_calib_default_cmd { 2946 uint16_t calib_index; 2947 uint16_t length; 2948 uint8_t data[0]; 2949 } __packed; /* IWM_PHY_CALIB_OVERRIDE_VALUES_S */ 2950 2951 #define IWM_MAX_PORT_ID_NUM 2 2952 #define IWM_MAX_MCAST_FILTERING_ADDRESSES 256 2953 2954 /** 2955 * struct iwm_mcast_filter_cmd - configure multicast filter. 2956 * @filter_own: Set 1 to filter out multicast packets sent by station itself 2957 * @port_id: Multicast MAC addresses array specifier. This is a strange way 2958 * to identify network interface adopted in host-device IF. 2959 * It is used by FW as index in array of addresses. This array has 2960 * IWM_MAX_PORT_ID_NUM members. 2961 * @count: Number of MAC addresses in the array 2962 * @pass_all: Set 1 to pass all multicast packets. 2963 * @bssid: current association BSSID. 2964 * @addr_list: Place holder for array of MAC addresses. 2965 * IMPORTANT: add padding if necessary to ensure DWORD alignment. 2966 */ 2967 struct iwm_mcast_filter_cmd { 2968 uint8_t filter_own; 2969 uint8_t port_id; 2970 uint8_t count; 2971 uint8_t pass_all; 2972 uint8_t bssid[6]; 2973 uint8_t reserved[2]; 2974 uint8_t addr_list[0]; 2975 } __packed; /* IWM_MCAST_FILTERING_CMD_API_S_VER_1 */ 2976 2977 struct iwm_mvm_statistics_dbg { 2978 uint32_t burst_check; 2979 uint32_t burst_count; 2980 uint32_t wait_for_silence_timeout_cnt; 2981 uint32_t reserved[3]; 2982 } __packed; /* IWM_STATISTICS_DEBUG_API_S_VER_2 */ 2983 2984 struct iwm_mvm_statistics_div { 2985 uint32_t tx_on_a; 2986 uint32_t tx_on_b; 2987 uint32_t exec_time; 2988 uint32_t probe_time; 2989 uint32_t rssi_ant; 2990 uint32_t reserved2; 2991 } __packed; /* IWM_STATISTICS_SLOW_DIV_API_S_VER_2 */ 2992 2993 struct iwm_mvm_statistics_general_common { 2994 uint32_t temperature; /* radio temperature */ 2995 uint32_t temperature_m; /* radio voltage */ 2996 struct iwm_mvm_statistics_dbg dbg; 2997 uint32_t sleep_time; 2998 uint32_t slots_out; 2999 uint32_t slots_idle; 3000 uint32_t ttl_timestamp; 3001 struct iwm_mvm_statistics_div div; 3002 uint32_t rx_enable_counter; 3003 /* 3004 * num_of_sos_states: 3005 * count the number of times we have to re-tune 3006 * in order to get out of bad PHY status 3007 */ 3008 uint32_t num_of_sos_states; 3009 } __packed; /* IWM_STATISTICS_GENERAL_API_S_VER_5 */ 3010 3011 struct iwm_mvm_statistics_rx_non_phy { 3012 uint32_t bogus_cts; /* CTS received when not expecting CTS */ 3013 uint32_t bogus_ack; /* ACK received when not expecting ACK */ 3014 uint32_t non_bssid_frames; /* number of frames with BSSID that 3015 * doesn't belong to the STA BSSID */ 3016 uint32_t filtered_frames; /* count frames that were dumped in the 3017 * filtering process */ 3018 uint32_t non_channel_beacons; /* beacons with our bss id but not on 3019 * our serving channel */ 3020 uint32_t channel_beacons; /* beacons with our bss id and in our 3021 * serving channel */ 3022 uint32_t num_missed_bcon; /* number of missed beacons */ 3023 uint32_t adc_rx_saturation_time; /* count in 0.8us units the time the 3024 * ADC was in saturation */ 3025 uint32_t ina_detection_search_time;/* total time (in 0.8us) searched 3026 * for INA */ 3027 uint32_t beacon_silence_rssi[3];/* RSSI silence after beacon frame */ 3028 uint32_t interference_data_flag; /* flag for interference data 3029 * availability. 1 when data is 3030 * available. */ 3031 uint32_t channel_load; /* counts RX Enable time in uSec */ 3032 uint32_t dsp_false_alarms; /* DSP false alarm (both OFDM 3033 * and CCK) counter */ 3034 uint32_t beacon_rssi_a; 3035 uint32_t beacon_rssi_b; 3036 uint32_t beacon_rssi_c; 3037 uint32_t beacon_energy_a; 3038 uint32_t beacon_energy_b; 3039 uint32_t beacon_energy_c; 3040 uint32_t num_bt_kills; 3041 uint32_t mac_id; 3042 uint32_t directed_data_mpdu; 3043 } __packed; /* IWM_STATISTICS_RX_NON_PHY_API_S_VER_3 */ 3044 3045 struct iwm_mvm_statistics_rx_phy { 3046 uint32_t ina_cnt; 3047 uint32_t fina_cnt; 3048 uint32_t plcp_err; 3049 uint32_t crc32_err; 3050 uint32_t overrun_err; 3051 uint32_t early_overrun_err; 3052 uint32_t crc32_good; 3053 uint32_t false_alarm_cnt; 3054 uint32_t fina_sync_err_cnt; 3055 uint32_t sfd_timeout; 3056 uint32_t fina_timeout; 3057 uint32_t unresponded_rts; 3058 uint32_t rxe_frame_limit_overrun; 3059 uint32_t sent_ack_cnt; 3060 uint32_t sent_cts_cnt; 3061 uint32_t sent_ba_rsp_cnt; 3062 uint32_t dsp_self_kill; 3063 uint32_t mh_format_err; 3064 uint32_t re_acq_main_rssi_sum; 3065 uint32_t reserved; 3066 } __packed; /* IWM_STATISTICS_RX_PHY_API_S_VER_2 */ 3067 3068 struct iwm_mvm_statistics_rx_ht_phy { 3069 uint32_t plcp_err; 3070 uint32_t overrun_err; 3071 uint32_t early_overrun_err; 3072 uint32_t crc32_good; 3073 uint32_t crc32_err; 3074 uint32_t mh_format_err; 3075 uint32_t agg_crc32_good; 3076 uint32_t agg_mpdu_cnt; 3077 uint32_t agg_cnt; 3078 uint32_t unsupport_mcs; 3079 } __packed; /* IWM_STATISTICS_HT_RX_PHY_API_S_VER_1 */ 3080 3081 #define IWM_MAX_CHAINS 3 3082 3083 struct iwm_mvm_statistics_tx_non_phy_agg { 3084 uint32_t ba_timeout; 3085 uint32_t ba_reschedule_frames; 3086 uint32_t scd_query_agg_frame_cnt; 3087 uint32_t scd_query_no_agg; 3088 uint32_t scd_query_agg; 3089 uint32_t scd_query_mismatch; 3090 uint32_t frame_not_ready; 3091 uint32_t underrun; 3092 uint32_t bt_prio_kill; 3093 uint32_t rx_ba_rsp_cnt; 3094 int8_t txpower[IWM_MAX_CHAINS]; 3095 int8_t reserved; 3096 uint32_t reserved2; 3097 } __packed; /* IWM_STATISTICS_TX_NON_PHY_AGG_API_S_VER_1 */ 3098 3099 struct iwm_mvm_statistics_tx_channel_width { 3100 uint32_t ext_cca_narrow_ch20[1]; 3101 uint32_t ext_cca_narrow_ch40[2]; 3102 uint32_t ext_cca_narrow_ch80[3]; 3103 uint32_t ext_cca_narrow_ch160[4]; 3104 uint32_t last_tx_ch_width_indx; 3105 uint32_t rx_detected_per_ch_width[4]; 3106 uint32_t success_per_ch_width[4]; 3107 uint32_t fail_per_ch_width[4]; 3108 }; /* IWM_STATISTICS_TX_CHANNEL_WIDTH_API_S_VER_1 */ 3109 3110 struct iwm_mvm_statistics_tx { 3111 uint32_t preamble_cnt; 3112 uint32_t rx_detected_cnt; 3113 uint32_t bt_prio_defer_cnt; 3114 uint32_t bt_prio_kill_cnt; 3115 uint32_t few_bytes_cnt; 3116 uint32_t cts_timeout; 3117 uint32_t ack_timeout; 3118 uint32_t expected_ack_cnt; 3119 uint32_t actual_ack_cnt; 3120 uint32_t dump_msdu_cnt; 3121 uint32_t burst_abort_next_frame_mismatch_cnt; 3122 uint32_t burst_abort_missing_next_frame_cnt; 3123 uint32_t cts_timeout_collision; 3124 uint32_t ack_or_ba_timeout_collision; 3125 struct iwm_mvm_statistics_tx_non_phy_agg agg; 3126 struct iwm_mvm_statistics_tx_channel_width channel_width; 3127 } __packed; /* IWM_STATISTICS_TX_API_S_VER_4 */ 3128 3129 3130 struct iwm_mvm_statistics_bt_activity { 3131 uint32_t hi_priority_tx_req_cnt; 3132 uint32_t hi_priority_tx_denied_cnt; 3133 uint32_t lo_priority_tx_req_cnt; 3134 uint32_t lo_priority_tx_denied_cnt; 3135 uint32_t hi_priority_rx_req_cnt; 3136 uint32_t hi_priority_rx_denied_cnt; 3137 uint32_t lo_priority_rx_req_cnt; 3138 uint32_t lo_priority_rx_denied_cnt; 3139 } __packed; /* IWM_STATISTICS_BT_ACTIVITY_API_S_VER_1 */ 3140 3141 struct iwm_mvm_statistics_general { 3142 struct iwm_mvm_statistics_general_common common; 3143 uint32_t beacon_filtered; 3144 uint32_t missed_beacons; 3145 int8_t beacon_filter_average_energy; 3146 int8_t beacon_filter_reason; 3147 int8_t beacon_filter_current_energy; 3148 int8_t beacon_filter_reserved; 3149 uint32_t beacon_filter_delta_time; 3150 struct iwm_mvm_statistics_bt_activity bt_activity; 3151 } __packed; /* IWM_STATISTICS_GENERAL_API_S_VER_5 */ 3152 3153 struct iwm_mvm_statistics_rx { 3154 struct iwm_mvm_statistics_rx_phy ofdm; 3155 struct iwm_mvm_statistics_rx_phy cck; 3156 struct iwm_mvm_statistics_rx_non_phy general; 3157 struct iwm_mvm_statistics_rx_ht_phy ofdm_ht; 3158 } __packed; /* IWM_STATISTICS_RX_API_S_VER_3 */ 3159 3160 /* 3161 * IWM_STATISTICS_NOTIFICATION = 0x9d (notification only, not a command) 3162 * 3163 * By default, uCode issues this notification after receiving a beacon 3164 * while associated. To disable this behavior, set DISABLE_NOTIF flag in the 3165 * IWM_REPLY_STATISTICS_CMD 0x9c, above. 3166 * 3167 * Statistics counters continue to increment beacon after beacon, but are 3168 * cleared when changing channels or when driver issues IWM_REPLY_STATISTICS_CMD 3169 * 0x9c with CLEAR_STATS bit set (see above). 3170 * 3171 * uCode also issues this notification during scans. uCode clears statistics 3172 * appropriately so that each notification contains statistics for only the 3173 * one channel that has just been scanned. 3174 */ 3175 3176 struct iwm_notif_statistics { /* IWM_STATISTICS_NTFY_API_S_VER_8 */ 3177 uint32_t flag; 3178 struct iwm_mvm_statistics_rx rx; 3179 struct iwm_mvm_statistics_tx tx; 3180 struct iwm_mvm_statistics_general general; 3181 } __packed; 3182 3183 /*********************************** 3184 * Smart Fifo API 3185 ***********************************/ 3186 /* Smart Fifo state */ 3187 enum iwm_sf_state { 3188 IWM_SF_LONG_DELAY_ON = 0, /* should never be called by driver */ 3189 IWM_SF_FULL_ON, 3190 IWM_SF_UNINIT, 3191 IWM_SF_INIT_OFF, 3192 IWM_SF_HW_NUM_STATES 3193 }; 3194 3195 /* Smart Fifo possible scenario */ 3196 enum iwm_sf_scenario { 3197 IWM_SF_SCENARIO_SINGLE_UNICAST, 3198 IWM_SF_SCENARIO_AGG_UNICAST, 3199 IWM_SF_SCENARIO_MULTICAST, 3200 IWM_SF_SCENARIO_BA_RESP, 3201 IWM_SF_SCENARIO_TX_RESP, 3202 IWM_SF_NUM_SCENARIO 3203 }; 3204 3205 #define IWM_SF_TRANSIENT_STATES_NUMBER 2 /* IWM_SF_LONG_DELAY_ON and IWM_SF_FULL_ON */ 3206 #define IWM_SF_NUM_TIMEOUT_TYPES 2 /* Aging timer and Idle timer */ 3207 3208 /* smart FIFO default values */ 3209 #define IWM_SF_W_MARK_SISO 4096 3210 #define IWM_SF_W_MARK_MIMO2 8192 3211 #define IWM_SF_W_MARK_MIMO3 6144 3212 #define IWM_SF_W_MARK_LEGACY 4096 3213 #define IWM_SF_W_MARK_SCAN 4096 3214 3215 /* SF Scenarios timers for default configuration (aligned to 32 uSec) */ 3216 #define IWM_SF_SINGLE_UNICAST_IDLE_TIMER_DEF 160 /* 150 uSec */ 3217 #define IWM_SF_SINGLE_UNICAST_AGING_TIMER_DEF 400 /* 0.4 mSec */ 3218 #define IWM_SF_AGG_UNICAST_IDLE_TIMER_DEF 160 /* 150 uSec */ 3219 #define IWM_SF_AGG_UNICAST_AGING_TIMER_DEF 400 /* 0.4 mSec */ 3220 #define IWM_SF_MCAST_IDLE_TIMER_DEF 160 /* 150 uSec */ 3221 #define IWM_SF_MCAST_AGING_TIMER_DEF 400 /* 0.4 mSec */ 3222 #define IWM_SF_BA_IDLE_TIMER_DEF 160 /* 150 uSec */ 3223 #define IWM_SF_BA_AGING_TIMER_DEF 400 /* 0.4 mSec */ 3224 #define IWM_SF_TX_RE_IDLE_TIMER_DEF 160 /* 150 uSec */ 3225 #define IWM_SF_TX_RE_AGING_TIMER_DEF 400 /* 0.4 mSec */ 3226 3227 /* SF Scenarios timers for FULL_ON state (aligned to 32 uSec) */ 3228 #define IWM_SF_SINGLE_UNICAST_IDLE_TIMER 320 /* 300 uSec */ 3229 #define IWM_SF_SINGLE_UNICAST_AGING_TIMER 2016 /* 2 mSec */ 3230 #define IWM_SF_AGG_UNICAST_IDLE_TIMER 320 /* 300 uSec */ 3231 #define IWM_SF_AGG_UNICAST_AGING_TIMER 2016 /* 2 mSec */ 3232 #define IWM_SF_MCAST_IDLE_TIMER 2016 /* 2 mSec */ 3233 #define IWM_SF_MCAST_AGING_TIMER 10016 /* 10 mSec */ 3234 #define IWM_SF_BA_IDLE_TIMER 320 /* 300 uSec */ 3235 #define IWM_SF_BA_AGING_TIMER 2016 /* 2 mSec */ 3236 #define IWM_SF_TX_RE_IDLE_TIMER 320 /* 300 uSec */ 3237 #define IWM_SF_TX_RE_AGING_TIMER 2016 /* 2 mSec */ 3238 3239 #define IWM_SF_LONG_DELAY_AGING_TIMER 1000000 /* 1 Sec */ 3240 3241 #define IWM_SF_CFG_DUMMY_NOTIF_OFF (1 << 16) 3242 3243 /** 3244 * Smart Fifo configuration command. 3245 * @state: smart fifo state, types listed in iwm_sf_state. 3246 * @watermark: Minimum allowed available free space in RXF for transient state. 3247 * @long_delay_timeouts: aging and idle timer values for each scenario 3248 * in long delay state. 3249 * @full_on_timeouts: timer values for each scenario in full on state. 3250 */ 3251 struct iwm_sf_cfg_cmd { 3252 uint32_t state; 3253 uint32_t watermark[IWM_SF_TRANSIENT_STATES_NUMBER]; 3254 uint32_t long_delay_timeouts[IWM_SF_NUM_SCENARIO][IWM_SF_NUM_TIMEOUT_TYPES]; 3255 uint32_t full_on_timeouts[IWM_SF_NUM_SCENARIO][IWM_SF_NUM_TIMEOUT_TYPES]; 3256 } __packed; /* IWM_SF_CFG_API_S_VER_2 */ 3257 3258 /* 3259 * END mvm/fw-api.h 3260 */ 3261 3262 /* 3263 * BEGIN mvm/fw-api-mac.h 3264 */ 3265 3266 /* 3267 * The first MAC indices (starting from 0) 3268 * are available to the driver, AUX follows 3269 */ 3270 #define IWM_MAC_INDEX_AUX 4 3271 #define IWM_MAC_INDEX_MIN_DRIVER 0 3272 #define IWM_NUM_MAC_INDEX_DRIVER IWM_MAC_INDEX_AUX 3273 3274 enum iwm_ac { 3275 IWM_AC_BK, 3276 IWM_AC_BE, 3277 IWM_AC_VI, 3278 IWM_AC_VO, 3279 IWM_AC_NUM, 3280 }; 3281 3282 /** 3283 * enum iwm_mac_protection_flags - MAC context flags 3284 * @IWM_MAC_PROT_FLG_TGG_PROTECT: 11g protection when transmitting OFDM frames, 3285 * this will require CCK RTS/CTS2self. 3286 * RTS/CTS will protect full burst time. 3287 * @IWM_MAC_PROT_FLG_HT_PROT: enable HT protection 3288 * @IWM_MAC_PROT_FLG_FAT_PROT: protect 40 MHz transmissions 3289 * @IWM_MAC_PROT_FLG_SELF_CTS_EN: allow CTS2self 3290 */ 3291 enum iwm_mac_protection_flags { 3292 IWM_MAC_PROT_FLG_TGG_PROTECT = (1 << 3), 3293 IWM_MAC_PROT_FLG_HT_PROT = (1 << 23), 3294 IWM_MAC_PROT_FLG_FAT_PROT = (1 << 24), 3295 IWM_MAC_PROT_FLG_SELF_CTS_EN = (1 << 30), 3296 }; 3297 3298 #define IWM_MAC_FLG_SHORT_SLOT (1 << 4) 3299 #define IWM_MAC_FLG_SHORT_PREAMBLE (1 << 5) 3300 3301 /** 3302 * enum iwm_mac_types - Supported MAC types 3303 * @IWM_FW_MAC_TYPE_FIRST: lowest supported MAC type 3304 * @IWM_FW_MAC_TYPE_AUX: Auxiliary MAC (internal) 3305 * @IWM_FW_MAC_TYPE_LISTENER: monitor MAC type (?) 3306 * @IWM_FW_MAC_TYPE_PIBSS: Pseudo-IBSS 3307 * @IWM_FW_MAC_TYPE_IBSS: IBSS 3308 * @IWM_FW_MAC_TYPE_BSS_STA: BSS (managed) station 3309 * @IWM_FW_MAC_TYPE_P2P_DEVICE: P2P Device 3310 * @IWM_FW_MAC_TYPE_P2P_STA: P2P client 3311 * @IWM_FW_MAC_TYPE_GO: P2P GO 3312 * @IWM_FW_MAC_TYPE_TEST: ? 3313 * @IWM_FW_MAC_TYPE_MAX: highest support MAC type 3314 */ 3315 enum iwm_mac_types { 3316 IWM_FW_MAC_TYPE_FIRST = 1, 3317 IWM_FW_MAC_TYPE_AUX = IWM_FW_MAC_TYPE_FIRST, 3318 IWM_FW_MAC_TYPE_LISTENER, 3319 IWM_FW_MAC_TYPE_PIBSS, 3320 IWM_FW_MAC_TYPE_IBSS, 3321 IWM_FW_MAC_TYPE_BSS_STA, 3322 IWM_FW_MAC_TYPE_P2P_DEVICE, 3323 IWM_FW_MAC_TYPE_P2P_STA, 3324 IWM_FW_MAC_TYPE_GO, 3325 IWM_FW_MAC_TYPE_TEST, 3326 IWM_FW_MAC_TYPE_MAX = IWM_FW_MAC_TYPE_TEST 3327 }; /* IWM_MAC_CONTEXT_TYPE_API_E_VER_1 */ 3328 3329 /** 3330 * enum iwm_tsf_id - TSF hw timer ID 3331 * @IWM_TSF_ID_A: use TSF A 3332 * @IWM_TSF_ID_B: use TSF B 3333 * @IWM_TSF_ID_C: use TSF C 3334 * @IWM_TSF_ID_D: use TSF D 3335 * @IWM_NUM_TSF_IDS: number of TSF timers available 3336 */ 3337 enum iwm_tsf_id { 3338 IWM_TSF_ID_A = 0, 3339 IWM_TSF_ID_B = 1, 3340 IWM_TSF_ID_C = 2, 3341 IWM_TSF_ID_D = 3, 3342 IWM_NUM_TSF_IDS = 4, 3343 }; /* IWM_TSF_ID_API_E_VER_1 */ 3344 3345 /** 3346 * struct iwm_mac_data_ap - configuration data for AP MAC context 3347 * @beacon_time: beacon transmit time in system time 3348 * @beacon_tsf: beacon transmit time in TSF 3349 * @bi: beacon interval in TU 3350 * @bi_reciprocal: 2^32 / bi 3351 * @dtim_interval: dtim transmit time in TU 3352 * @dtim_reciprocal: 2^32 / dtim_interval 3353 * @mcast_qid: queue ID for multicast traffic 3354 * @beacon_template: beacon template ID 3355 */ 3356 struct iwm_mac_data_ap { 3357 uint32_t beacon_time; 3358 uint64_t beacon_tsf; 3359 uint32_t bi; 3360 uint32_t bi_reciprocal; 3361 uint32_t dtim_interval; 3362 uint32_t dtim_reciprocal; 3363 uint32_t mcast_qid; 3364 uint32_t beacon_template; 3365 } __packed; /* AP_MAC_DATA_API_S_VER_1 */ 3366 3367 /** 3368 * struct iwm_mac_data_ibss - configuration data for IBSS MAC context 3369 * @beacon_time: beacon transmit time in system time 3370 * @beacon_tsf: beacon transmit time in TSF 3371 * @bi: beacon interval in TU 3372 * @bi_reciprocal: 2^32 / bi 3373 * @beacon_template: beacon template ID 3374 */ 3375 struct iwm_mac_data_ibss { 3376 uint32_t beacon_time; 3377 uint64_t beacon_tsf; 3378 uint32_t bi; 3379 uint32_t bi_reciprocal; 3380 uint32_t beacon_template; 3381 } __packed; /* IBSS_MAC_DATA_API_S_VER_1 */ 3382 3383 /** 3384 * struct iwm_mac_data_sta - configuration data for station MAC context 3385 * @is_assoc: 1 for associated state, 0 otherwise 3386 * @dtim_time: DTIM arrival time in system time 3387 * @dtim_tsf: DTIM arrival time in TSF 3388 * @bi: beacon interval in TU, applicable only when associated 3389 * @bi_reciprocal: 2^32 / bi , applicable only when associated 3390 * @dtim_interval: DTIM interval in TU, applicable only when associated 3391 * @dtim_reciprocal: 2^32 / dtim_interval , applicable only when associated 3392 * @listen_interval: in beacon intervals, applicable only when associated 3393 * @assoc_id: unique ID assigned by the AP during association 3394 */ 3395 struct iwm_mac_data_sta { 3396 uint32_t is_assoc; 3397 uint32_t dtim_time; 3398 uint64_t dtim_tsf; 3399 uint32_t bi; 3400 uint32_t bi_reciprocal; 3401 uint32_t dtim_interval; 3402 uint32_t dtim_reciprocal; 3403 uint32_t listen_interval; 3404 uint32_t assoc_id; 3405 uint32_t assoc_beacon_arrive_time; 3406 } __packed; /* IWM_STA_MAC_DATA_API_S_VER_1 */ 3407 3408 /** 3409 * struct iwm_mac_data_go - configuration data for P2P GO MAC context 3410 * @ap: iwm_mac_data_ap struct with most config data 3411 * @ctwin: client traffic window in TU (period after TBTT when GO is present). 3412 * 0 indicates that there is no CT window. 3413 * @opp_ps_enabled: indicate that opportunistic PS allowed 3414 */ 3415 struct iwm_mac_data_go { 3416 struct iwm_mac_data_ap ap; 3417 uint32_t ctwin; 3418 uint32_t opp_ps_enabled; 3419 } __packed; /* GO_MAC_DATA_API_S_VER_1 */ 3420 3421 /** 3422 * struct iwm_mac_data_p2p_sta - configuration data for P2P client MAC context 3423 * @sta: iwm_mac_data_sta struct with most config data 3424 * @ctwin: client traffic window in TU (period after TBTT when GO is present). 3425 * 0 indicates that there is no CT window. 3426 */ 3427 struct iwm_mac_data_p2p_sta { 3428 struct iwm_mac_data_sta sta; 3429 uint32_t ctwin; 3430 } __packed; /* P2P_STA_MAC_DATA_API_S_VER_1 */ 3431 3432 /** 3433 * struct iwm_mac_data_pibss - Pseudo IBSS config data 3434 * @stats_interval: interval in TU between statistics notifications to host. 3435 */ 3436 struct iwm_mac_data_pibss { 3437 uint32_t stats_interval; 3438 } __packed; /* PIBSS_MAC_DATA_API_S_VER_1 */ 3439 3440 /* 3441 * struct iwm_mac_data_p2p_dev - configuration data for the P2P Device MAC 3442 * context. 3443 * @is_disc_extended: if set to true, P2P Device discoverability is enabled on 3444 * other channels as well. This should be to true only in case that the 3445 * device is discoverable and there is an active GO. Note that setting this 3446 * field when not needed, will increase the number of interrupts and have 3447 * effect on the platform power, as this setting opens the Rx filters on 3448 * all macs. 3449 */ 3450 struct iwm_mac_data_p2p_dev { 3451 uint32_t is_disc_extended; 3452 } __packed; /* _P2P_DEV_MAC_DATA_API_S_VER_1 */ 3453 3454 /** 3455 * enum iwm_mac_filter_flags - MAC context filter flags 3456 * @IWM_MAC_FILTER_IN_PROMISC: accept all data frames 3457 * @IWM_MAC_FILTER_IN_CONTROL_AND_MGMT: pass all mangement and 3458 * control frames to the host 3459 * @IWM_MAC_FILTER_ACCEPT_GRP: accept multicast frames 3460 * @IWM_MAC_FILTER_DIS_DECRYPT: don't decrypt unicast frames 3461 * @IWM_MAC_FILTER_DIS_GRP_DECRYPT: don't decrypt multicast frames 3462 * @IWM_MAC_FILTER_IN_BEACON: transfer foreign BSS's beacons to host 3463 * (in station mode when associated) 3464 * @IWM_MAC_FILTER_OUT_BCAST: filter out all broadcast frames 3465 * @IWM_MAC_FILTER_IN_CRC32: extract FCS and append it to frames 3466 * @IWM_MAC_FILTER_IN_PROBE_REQUEST: pass probe requests to host 3467 */ 3468 enum iwm_mac_filter_flags { 3469 IWM_MAC_FILTER_IN_PROMISC = (1 << 0), 3470 IWM_MAC_FILTER_IN_CONTROL_AND_MGMT = (1 << 1), 3471 IWM_MAC_FILTER_ACCEPT_GRP = (1 << 2), 3472 IWM_MAC_FILTER_DIS_DECRYPT = (1 << 3), 3473 IWM_MAC_FILTER_DIS_GRP_DECRYPT = (1 << 4), 3474 IWM_MAC_FILTER_IN_BEACON = (1 << 6), 3475 IWM_MAC_FILTER_OUT_BCAST = (1 << 8), 3476 IWM_MAC_FILTER_IN_CRC32 = (1 << 11), 3477 IWM_MAC_FILTER_IN_PROBE_REQUEST = (1 << 12), 3478 }; 3479 3480 /** 3481 * enum iwm_mac_qos_flags - QoS flags 3482 * @IWM_MAC_QOS_FLG_UPDATE_EDCA: ? 3483 * @IWM_MAC_QOS_FLG_TGN: HT is enabled 3484 * @IWM_MAC_QOS_FLG_TXOP_TYPE: ? 3485 * 3486 */ 3487 enum iwm_mac_qos_flags { 3488 IWM_MAC_QOS_FLG_UPDATE_EDCA = (1 << 0), 3489 IWM_MAC_QOS_FLG_TGN = (1 << 1), 3490 IWM_MAC_QOS_FLG_TXOP_TYPE = (1 << 4), 3491 }; 3492 3493 /** 3494 * struct iwm_ac_qos - QOS timing params for IWM_MAC_CONTEXT_CMD 3495 * @cw_min: Contention window, start value in numbers of slots. 3496 * Should be a power-of-2, minus 1. Device's default is 0x0f. 3497 * @cw_max: Contention window, max value in numbers of slots. 3498 * Should be a power-of-2, minus 1. Device's default is 0x3f. 3499 * @aifsn: Number of slots in Arbitration Interframe Space (before 3500 * performing random backoff timing prior to Tx). Device default 1. 3501 * @fifos_mask: FIFOs used by this MAC for this AC 3502 * @edca_txop: Length of Tx opportunity, in uSecs. Device default is 0. 3503 * 3504 * One instance of this config struct for each of 4 EDCA access categories 3505 * in struct iwm_qosparam_cmd. 3506 * 3507 * Device will automatically increase contention window by (2*CW) + 1 for each 3508 * transmission retry. Device uses cw_max as a bit mask, ANDed with new CW 3509 * value, to cap the CW value. 3510 */ 3511 struct iwm_ac_qos { 3512 uint16_t cw_min; 3513 uint16_t cw_max; 3514 uint8_t aifsn; 3515 uint8_t fifos_mask; 3516 uint16_t edca_txop; 3517 } __packed; /* IWM_AC_QOS_API_S_VER_2 */ 3518 3519 /** 3520 * struct iwm_mac_ctx_cmd - command structure to configure MAC contexts 3521 * ( IWM_MAC_CONTEXT_CMD = 0x28 ) 3522 * @id_and_color: ID and color of the MAC 3523 * @action: action to perform, one of IWM_FW_CTXT_ACTION_* 3524 * @mac_type: one of IWM_FW_MAC_TYPE_* 3525 * @tsd_id: TSF HW timer, one of IWM_TSF_ID_* 3526 * @node_addr: MAC address 3527 * @bssid_addr: BSSID 3528 * @cck_rates: basic rates available for CCK 3529 * @ofdm_rates: basic rates available for OFDM 3530 * @protection_flags: combination of IWM_MAC_PROT_FLG_FLAG_* 3531 * @cck_short_preamble: 0x20 for enabling short preamble, 0 otherwise 3532 * @short_slot: 0x10 for enabling short slots, 0 otherwise 3533 * @filter_flags: combination of IWM_MAC_FILTER_* 3534 * @qos_flags: from IWM_MAC_QOS_FLG_* 3535 * @ac: one iwm_mac_qos configuration for each AC 3536 * @mac_specific: one of struct iwm_mac_data_*, according to mac_type 3537 */ 3538 struct iwm_mac_ctx_cmd { 3539 /* COMMON_INDEX_HDR_API_S_VER_1 */ 3540 uint32_t id_and_color; 3541 uint32_t action; 3542 /* IWM_MAC_CONTEXT_COMMON_DATA_API_S_VER_1 */ 3543 uint32_t mac_type; 3544 uint32_t tsf_id; 3545 uint8_t node_addr[6]; 3546 uint16_t reserved_for_node_addr; 3547 uint8_t bssid_addr[6]; 3548 uint16_t reserved_for_bssid_addr; 3549 uint32_t cck_rates; 3550 uint32_t ofdm_rates; 3551 uint32_t protection_flags; 3552 uint32_t cck_short_preamble; 3553 uint32_t short_slot; 3554 uint32_t filter_flags; 3555 /* IWM_MAC_QOS_PARAM_API_S_VER_1 */ 3556 uint32_t qos_flags; 3557 struct iwm_ac_qos ac[IWM_AC_NUM+1]; 3558 /* IWM_MAC_CONTEXT_COMMON_DATA_API_S */ 3559 union { 3560 struct iwm_mac_data_ap ap; 3561 struct iwm_mac_data_go go; 3562 struct iwm_mac_data_sta sta; 3563 struct iwm_mac_data_p2p_sta p2p_sta; 3564 struct iwm_mac_data_p2p_dev p2p_dev; 3565 struct iwm_mac_data_pibss pibss; 3566 struct iwm_mac_data_ibss ibss; 3567 }; 3568 } __packed; /* IWM_MAC_CONTEXT_CMD_API_S_VER_1 */ 3569 3570 static inline uint32_t iwm_mvm_reciprocal(uint32_t v) 3571 { 3572 if (!v) 3573 return 0; 3574 return 0xFFFFFFFF / v; 3575 } 3576 3577 #define IWM_NONQOS_SEQ_GET 0x1 3578 #define IWM_NONQOS_SEQ_SET 0x2 3579 struct iwm_nonqos_seq_query_cmd { 3580 uint32_t get_set_flag; 3581 uint32_t mac_id_n_color; 3582 uint16_t value; 3583 uint16_t reserved; 3584 } __packed; /* IWM_NON_QOS_TX_COUNTER_GET_SET_API_S_VER_1 */ 3585 3586 /* 3587 * END mvm/fw-api-mac.h 3588 */ 3589 3590 /* 3591 * BEGIN mvm/fw-api-power.h 3592 */ 3593 3594 /* Power Management Commands, Responses, Notifications */ 3595 3596 /* Radio LP RX Energy Threshold measured in dBm */ 3597 #define IWM_POWER_LPRX_RSSI_THRESHOLD 75 3598 #define IWM_POWER_LPRX_RSSI_THRESHOLD_MAX 94 3599 #define IWM_POWER_LPRX_RSSI_THRESHOLD_MIN 30 3600 3601 /** 3602 * enum iwm_scan_flags - masks for power table command flags 3603 * @IWM_POWER_FLAGS_POWER_SAVE_ENA_MSK: '1' Allow to save power by turning off 3604 * receiver and transmitter. '0' - does not allow. 3605 * @IWM_POWER_FLAGS_POWER_MANAGEMENT_ENA_MSK: '0' Driver disables power management, 3606 * '1' Driver enables PM (use rest of parameters) 3607 * @IWM_POWER_FLAGS_SKIP_OVER_DTIM_MSK: '0' PM have to walk up every DTIM, 3608 * '1' PM could sleep over DTIM till listen Interval. 3609 * @IWM_POWER_FLAGS_SNOOZE_ENA_MSK: Enable snoozing only if uAPSD is enabled and all 3610 * access categories are both delivery and trigger enabled. 3611 * @IWM_POWER_FLAGS_BT_SCO_ENA: Enable BT SCO coex only if uAPSD and 3612 * PBW Snoozing enabled 3613 * @IWM_POWER_FLAGS_ADVANCE_PM_ENA_MSK: Advanced PM (uAPSD) enable mask 3614 * @IWM_POWER_FLAGS_LPRX_ENA_MSK: Low Power RX enable. 3615 * @IWM_POWER_FLAGS_AP_UAPSD_MISBEHAVING_ENA_MSK: AP/GO's uAPSD misbehaving 3616 * detection enablement 3617 */ 3618 enum iwm_power_flags { 3619 IWM_POWER_FLAGS_POWER_SAVE_ENA_MSK = (1 << 0), 3620 IWM_POWER_FLAGS_POWER_MANAGEMENT_ENA_MSK = (1 << 1), 3621 IWM_POWER_FLAGS_SKIP_OVER_DTIM_MSK = (1 << 2), 3622 IWM_POWER_FLAGS_SNOOZE_ENA_MSK = (1 << 5), 3623 IWM_POWER_FLAGS_BT_SCO_ENA = (1 << 8), 3624 IWM_POWER_FLAGS_ADVANCE_PM_ENA_MSK = (1 << 9), 3625 IWM_POWER_FLAGS_LPRX_ENA_MSK = (1 << 11), 3626 IWM_POWER_FLAGS_UAPSD_MISBEHAVING_ENA_MSK = (1 << 12), 3627 }; 3628 3629 #define IWM_POWER_VEC_SIZE 5 3630 3631 /** 3632 * struct iwm_powertable_cmd - legacy power command. Beside old API support this 3633 * is used also with a new power API for device wide power settings. 3634 * IWM_POWER_TABLE_CMD = 0x77 (command, has simple generic response) 3635 * 3636 * @flags: Power table command flags from IWM_POWER_FLAGS_* 3637 * @keep_alive_seconds: Keep alive period in seconds. Default - 25 sec. 3638 * Minimum allowed:- 3 * DTIM. Keep alive period must be 3639 * set regardless of power scheme or current power state. 3640 * FW use this value also when PM is disabled. 3641 * @rx_data_timeout: Minimum time (usec) from last Rx packet for AM to 3642 * PSM transition - legacy PM 3643 * @tx_data_timeout: Minimum time (usec) from last Tx packet for AM to 3644 * PSM transition - legacy PM 3645 * @sleep_interval: not in use 3646 * @skip_dtim_periods: Number of DTIM periods to skip if Skip over DTIM flag 3647 * is set. For example, if it is required to skip over 3648 * one DTIM, this value need to be set to 2 (DTIM periods). 3649 * @lprx_rssi_threshold: Signal strength up to which LP RX can be enabled. 3650 * Default: 80dbm 3651 */ 3652 struct iwm_powertable_cmd { 3653 /* PM_POWER_TABLE_CMD_API_S_VER_6 */ 3654 uint16_t flags; 3655 uint8_t keep_alive_seconds; 3656 uint8_t debug_flags; 3657 uint32_t rx_data_timeout; 3658 uint32_t tx_data_timeout; 3659 uint32_t sleep_interval[IWM_POWER_VEC_SIZE]; 3660 uint32_t skip_dtim_periods; 3661 uint32_t lprx_rssi_threshold; 3662 } __packed; 3663 3664 /** 3665 * enum iwm_device_power_flags - masks for device power command flags 3666 * @DEVIC_POWER_FLAGS_POWER_SAVE_ENA_MSK: '1' Allow to save power by turning off 3667 * receiver and transmitter. '0' - does not allow. This flag should be 3668 * always set to '1' unless one need to disable actual power down for debug 3669 * purposes. 3670 * @IWM_DEVICE_POWER_FLAGS_CAM_MSK: '1' CAM (Continuous Active Mode) is set, meaning 3671 * that power management is disabled. '0' Power management is enabled, one 3672 * of power schemes is applied. 3673 */ 3674 enum iwm_device_power_flags { 3675 IWM_DEVICE_POWER_FLAGS_POWER_SAVE_ENA_MSK = (1 << 0), 3676 IWM_DEVICE_POWER_FLAGS_CAM_MSK = (1 << 13), 3677 }; 3678 3679 /** 3680 * struct iwm_device_power_cmd - device wide power command. 3681 * IWM_DEVICE_POWER_CMD = 0x77 (command, has simple generic response) 3682 * 3683 * @flags: Power table command flags from IWM_DEVICE_POWER_FLAGS_* 3684 */ 3685 struct iwm_device_power_cmd { 3686 /* PM_POWER_TABLE_CMD_API_S_VER_6 */ 3687 uint16_t flags; 3688 uint16_t reserved; 3689 } __packed; 3690 3691 /** 3692 * struct iwm_mac_power_cmd - New power command containing uAPSD support 3693 * IWM_MAC_PM_POWER_TABLE = 0xA9 (command, has simple generic response) 3694 * @id_and_color: MAC contex identifier 3695 * @flags: Power table command flags from POWER_FLAGS_* 3696 * @keep_alive_seconds: Keep alive period in seconds. Default - 25 sec. 3697 * Minimum allowed:- 3 * DTIM. Keep alive period must be 3698 * set regardless of power scheme or current power state. 3699 * FW use this value also when PM is disabled. 3700 * @rx_data_timeout: Minimum time (usec) from last Rx packet for AM to 3701 * PSM transition - legacy PM 3702 * @tx_data_timeout: Minimum time (usec) from last Tx packet for AM to 3703 * PSM transition - legacy PM 3704 * @sleep_interval: not in use 3705 * @skip_dtim_periods: Number of DTIM periods to skip if Skip over DTIM flag 3706 * is set. For example, if it is required to skip over 3707 * one DTIM, this value need to be set to 2 (DTIM periods). 3708 * @rx_data_timeout_uapsd: Minimum time (usec) from last Rx packet for AM to 3709 * PSM transition - uAPSD 3710 * @tx_data_timeout_uapsd: Minimum time (usec) from last Tx packet for AM to 3711 * PSM transition - uAPSD 3712 * @lprx_rssi_threshold: Signal strength up to which LP RX can be enabled. 3713 * Default: 80dbm 3714 * @num_skip_dtim: Number of DTIMs to skip if Skip over DTIM flag is set 3715 * @snooze_interval: Maximum time between attempts to retrieve buffered data 3716 * from the AP [msec] 3717 * @snooze_window: A window of time in which PBW snoozing insures that all 3718 * packets received. It is also the minimum time from last 3719 * received unicast RX packet, before client stops snoozing 3720 * for data. [msec] 3721 * @snooze_step: TBD 3722 * @qndp_tid: TID client shall use for uAPSD QNDP triggers 3723 * @uapsd_ac_flags: Set trigger-enabled and delivery-enabled indication for 3724 * each corresponding AC. 3725 * Use IEEE80211_WMM_IE_STA_QOSINFO_AC* for correct values. 3726 * @uapsd_max_sp: Use IEEE80211_WMM_IE_STA_QOSINFO_SP_* for correct 3727 * values. 3728 * @heavy_tx_thld_packets: TX threshold measured in number of packets 3729 * @heavy_rx_thld_packets: RX threshold measured in number of packets 3730 * @heavy_tx_thld_percentage: TX threshold measured in load's percentage 3731 * @heavy_rx_thld_percentage: RX threshold measured in load's percentage 3732 * @limited_ps_threshold: 3733 */ 3734 struct iwm_mac_power_cmd { 3735 /* CONTEXT_DESC_API_T_VER_1 */ 3736 uint32_t id_and_color; 3737 3738 /* CLIENT_PM_POWER_TABLE_S_VER_1 */ 3739 uint16_t flags; 3740 uint16_t keep_alive_seconds; 3741 uint32_t rx_data_timeout; 3742 uint32_t tx_data_timeout; 3743 uint32_t rx_data_timeout_uapsd; 3744 uint32_t tx_data_timeout_uapsd; 3745 uint8_t lprx_rssi_threshold; 3746 uint8_t skip_dtim_periods; 3747 uint16_t snooze_interval; 3748 uint16_t snooze_window; 3749 uint8_t snooze_step; 3750 uint8_t qndp_tid; 3751 uint8_t uapsd_ac_flags; 3752 uint8_t uapsd_max_sp; 3753 uint8_t heavy_tx_thld_packets; 3754 uint8_t heavy_rx_thld_packets; 3755 uint8_t heavy_tx_thld_percentage; 3756 uint8_t heavy_rx_thld_percentage; 3757 uint8_t limited_ps_threshold; 3758 uint8_t reserved; 3759 } __packed; 3760 3761 /* 3762 * struct iwm_uapsd_misbehaving_ap_notif - FW sends this notification when 3763 * associated AP is identified as improperly implementing uAPSD protocol. 3764 * IWM_PSM_UAPSD_AP_MISBEHAVING_NOTIFICATION = 0x78 3765 * @sta_id: index of station in uCode's station table - associated AP ID in 3766 * this context. 3767 */ 3768 struct iwm_uapsd_misbehaving_ap_notif { 3769 uint32_t sta_id; 3770 uint8_t mac_id; 3771 uint8_t reserved[3]; 3772 } __packed; 3773 3774 /** 3775 * struct iwm_beacon_filter_cmd 3776 * IWM_REPLY_BEACON_FILTERING_CMD = 0xd2 (command) 3777 * @id_and_color: MAC contex identifier 3778 * @bf_energy_delta: Used for RSSI filtering, if in 'normal' state. Send beacon 3779 * to driver if delta in Energy values calculated for this and last 3780 * passed beacon is greater than this threshold. Zero value means that 3781 * the Energy change is ignored for beacon filtering, and beacon will 3782 * not be forced to be sent to driver regardless of this delta. Typical 3783 * energy delta 5dB. 3784 * @bf_roaming_energy_delta: Used for RSSI filtering, if in 'roaming' state. 3785 * Send beacon to driver if delta in Energy values calculated for this 3786 * and last passed beacon is greater than this threshold. Zero value 3787 * means that the Energy change is ignored for beacon filtering while in 3788 * Roaming state, typical energy delta 1dB. 3789 * @bf_roaming_state: Used for RSSI filtering. If absolute Energy values 3790 * calculated for current beacon is less than the threshold, use 3791 * Roaming Energy Delta Threshold, otherwise use normal Energy Delta 3792 * Threshold. Typical energy threshold is -72dBm. 3793 * @bf_temp_threshold: This threshold determines the type of temperature 3794 * filtering (Slow or Fast) that is selected (Units are in Celsuis): 3795 * If the current temperature is above this threshold - Fast filter 3796 * will be used, If the current temperature is below this threshold - 3797 * Slow filter will be used. 3798 * @bf_temp_fast_filter: Send Beacon to driver if delta in temperature values 3799 * calculated for this and the last passed beacon is greater than this 3800 * threshold. Zero value means that the temperature change is ignored for 3801 * beacon filtering; beacons will not be forced to be sent to driver 3802 * regardless of whether its temperature has been changed. 3803 * @bf_temp_slow_filter: Send Beacon to driver if delta in temperature values 3804 * calculated for this and the last passed beacon is greater than this 3805 * threshold. Zero value means that the temperature change is ignored for 3806 * beacon filtering; beacons will not be forced to be sent to driver 3807 * regardless of whether its temperature has been changed. 3808 * @bf_enable_beacon_filter: 1, beacon filtering is enabled; 0, disabled. 3809 * @bf_filter_escape_timer: Send beacons to to driver if no beacons were passed 3810 * for a specific period of time. Units: Beacons. 3811 * @ba_escape_timer: Fully receive and parse beacon if no beacons were passed 3812 * for a longer period of time then this escape-timeout. Units: Beacons. 3813 * @ba_enable_beacon_abort: 1, beacon abort is enabled; 0, disabled. 3814 */ 3815 struct iwm_beacon_filter_cmd { 3816 uint32_t bf_energy_delta; 3817 uint32_t bf_roaming_energy_delta; 3818 uint32_t bf_roaming_state; 3819 uint32_t bf_temp_threshold; 3820 uint32_t bf_temp_fast_filter; 3821 uint32_t bf_temp_slow_filter; 3822 uint32_t bf_enable_beacon_filter; 3823 uint32_t bf_debug_flag; 3824 uint32_t bf_escape_timer; 3825 uint32_t ba_escape_timer; 3826 uint32_t ba_enable_beacon_abort; 3827 } __packed; 3828 3829 /* Beacon filtering and beacon abort */ 3830 #define IWM_BF_ENERGY_DELTA_DEFAULT 5 3831 #define IWM_BF_ENERGY_DELTA_MAX 255 3832 #define IWM_BF_ENERGY_DELTA_MIN 0 3833 3834 #define IWM_BF_ROAMING_ENERGY_DELTA_DEFAULT 1 3835 #define IWM_BF_ROAMING_ENERGY_DELTA_MAX 255 3836 #define IWM_BF_ROAMING_ENERGY_DELTA_MIN 0 3837 3838 #define IWM_BF_ROAMING_STATE_DEFAULT 72 3839 #define IWM_BF_ROAMING_STATE_MAX 255 3840 #define IWM_BF_ROAMING_STATE_MIN 0 3841 3842 #define IWM_BF_TEMP_THRESHOLD_DEFAULT 112 3843 #define IWM_BF_TEMP_THRESHOLD_MAX 255 3844 #define IWM_BF_TEMP_THRESHOLD_MIN 0 3845 3846 #define IWM_BF_TEMP_FAST_FILTER_DEFAULT 1 3847 #define IWM_BF_TEMP_FAST_FILTER_MAX 255 3848 #define IWM_BF_TEMP_FAST_FILTER_MIN 0 3849 3850 #define IWM_BF_TEMP_SLOW_FILTER_DEFAULT 5 3851 #define IWM_BF_TEMP_SLOW_FILTER_MAX 255 3852 #define IWM_BF_TEMP_SLOW_FILTER_MIN 0 3853 3854 #define IWM_BF_ENABLE_BEACON_FILTER_DEFAULT 1 3855 3856 #define IWM_BF_DEBUG_FLAG_DEFAULT 0 3857 3858 #define IWM_BF_ESCAPE_TIMER_DEFAULT 50 3859 #define IWM_BF_ESCAPE_TIMER_MAX 1024 3860 #define IWM_BF_ESCAPE_TIMER_MIN 0 3861 3862 #define IWM_BA_ESCAPE_TIMER_DEFAULT 6 3863 #define IWM_BA_ESCAPE_TIMER_D3 9 3864 #define IWM_BA_ESCAPE_TIMER_MAX 1024 3865 #define IWM_BA_ESCAPE_TIMER_MIN 0 3866 3867 #define IWM_BA_ENABLE_BEACON_ABORT_DEFAULT 1 3868 3869 #define IWM_BF_CMD_CONFIG_DEFAULTS \ 3870 .bf_energy_delta = htole32(IWM_BF_ENERGY_DELTA_DEFAULT), \ 3871 .bf_roaming_energy_delta = \ 3872 htole32(IWM_BF_ROAMING_ENERGY_DELTA_DEFAULT), \ 3873 .bf_roaming_state = htole32(IWM_BF_ROAMING_STATE_DEFAULT), \ 3874 .bf_temp_threshold = htole32(IWM_BF_TEMP_THRESHOLD_DEFAULT), \ 3875 .bf_temp_fast_filter = htole32(IWM_BF_TEMP_FAST_FILTER_DEFAULT), \ 3876 .bf_temp_slow_filter = htole32(IWM_BF_TEMP_SLOW_FILTER_DEFAULT), \ 3877 .bf_debug_flag = htole32(IWM_BF_DEBUG_FLAG_DEFAULT), \ 3878 .bf_escape_timer = htole32(IWM_BF_ESCAPE_TIMER_DEFAULT), \ 3879 .ba_escape_timer = htole32(IWM_BA_ESCAPE_TIMER_DEFAULT) 3880 3881 /* 3882 * END mvm/fw-api-power.h 3883 */ 3884 3885 /* 3886 * BEGIN mvm/fw-api-rs.h 3887 */ 3888 3889 /* 3890 * These serve as indexes into 3891 * struct iwm_rate_info fw_rate_idx_to_plcp[IWM_RATE_COUNT]; 3892 * TODO: avoid overlap between legacy and HT rates 3893 */ 3894 enum { 3895 IWM_RATE_1M_INDEX = 0, 3896 IWM_FIRST_CCK_RATE = IWM_RATE_1M_INDEX, 3897 IWM_RATE_2M_INDEX, 3898 IWM_RATE_5M_INDEX, 3899 IWM_RATE_11M_INDEX, 3900 IWM_LAST_CCK_RATE = IWM_RATE_11M_INDEX, 3901 IWM_RATE_6M_INDEX, 3902 IWM_FIRST_OFDM_RATE = IWM_RATE_6M_INDEX, 3903 IWM_RATE_MCS_0_INDEX = IWM_RATE_6M_INDEX, 3904 IWM_FIRST_HT_RATE = IWM_RATE_MCS_0_INDEX, 3905 IWM_FIRST_VHT_RATE = IWM_RATE_MCS_0_INDEX, 3906 IWM_RATE_9M_INDEX, 3907 IWM_RATE_12M_INDEX, 3908 IWM_RATE_MCS_1_INDEX = IWM_RATE_12M_INDEX, 3909 IWM_RATE_18M_INDEX, 3910 IWM_RATE_MCS_2_INDEX = IWM_RATE_18M_INDEX, 3911 IWM_RATE_24M_INDEX, 3912 IWM_RATE_MCS_3_INDEX = IWM_RATE_24M_INDEX, 3913 IWM_RATE_36M_INDEX, 3914 IWM_RATE_MCS_4_INDEX = IWM_RATE_36M_INDEX, 3915 IWM_RATE_48M_INDEX, 3916 IWM_RATE_MCS_5_INDEX = IWM_RATE_48M_INDEX, 3917 IWM_RATE_54M_INDEX, 3918 IWM_RATE_MCS_6_INDEX = IWM_RATE_54M_INDEX, 3919 IWM_LAST_NON_HT_RATE = IWM_RATE_54M_INDEX, 3920 IWM_RATE_60M_INDEX, 3921 IWM_RATE_MCS_7_INDEX = IWM_RATE_60M_INDEX, 3922 IWM_LAST_HT_RATE = IWM_RATE_MCS_7_INDEX, 3923 IWM_RATE_MCS_8_INDEX, 3924 IWM_RATE_MCS_9_INDEX, 3925 IWM_LAST_VHT_RATE = IWM_RATE_MCS_9_INDEX, 3926 IWM_RATE_COUNT_LEGACY = IWM_LAST_NON_HT_RATE + 1, 3927 IWM_RATE_COUNT = IWM_LAST_VHT_RATE + 1, 3928 }; 3929 3930 #define IWM_RATE_BIT_MSK(r) (1 << (IWM_RATE_##r##M_INDEX)) 3931 3932 /* fw API values for legacy bit rates, both OFDM and CCK */ 3933 enum { 3934 IWM_RATE_6M_PLCP = 13, 3935 IWM_RATE_9M_PLCP = 15, 3936 IWM_RATE_12M_PLCP = 5, 3937 IWM_RATE_18M_PLCP = 7, 3938 IWM_RATE_24M_PLCP = 9, 3939 IWM_RATE_36M_PLCP = 11, 3940 IWM_RATE_48M_PLCP = 1, 3941 IWM_RATE_54M_PLCP = 3, 3942 IWM_RATE_1M_PLCP = 10, 3943 IWM_RATE_2M_PLCP = 20, 3944 IWM_RATE_5M_PLCP = 55, 3945 IWM_RATE_11M_PLCP = 110, 3946 IWM_RATE_INVM_PLCP = -1, 3947 }; 3948 3949 /* 3950 * rate_n_flags bit fields 3951 * 3952 * The 32-bit value has different layouts in the low 8 bites depending on the 3953 * format. There are three formats, HT, VHT and legacy (11abg, with subformats 3954 * for CCK and OFDM). 3955 * 3956 * High-throughput (HT) rate format 3957 * bit 8 is 1, bit 26 is 0, bit 9 is 0 (OFDM) 3958 * Very High-throughput (VHT) rate format 3959 * bit 8 is 0, bit 26 is 1, bit 9 is 0 (OFDM) 3960 * Legacy OFDM rate format for bits 7:0 3961 * bit 8 is 0, bit 26 is 0, bit 9 is 0 (OFDM) 3962 * Legacy CCK rate format for bits 7:0: 3963 * bit 8 is 0, bit 26 is 0, bit 9 is 1 (CCK) 3964 */ 3965 3966 /* Bit 8: (1) HT format, (0) legacy or VHT format */ 3967 #define IWM_RATE_MCS_HT_POS 8 3968 #define IWM_RATE_MCS_HT_MSK (1 << IWM_RATE_MCS_HT_POS) 3969 3970 /* Bit 9: (1) CCK, (0) OFDM. HT (bit 8) must be "0" for this bit to be valid */ 3971 #define IWM_RATE_MCS_CCK_POS 9 3972 #define IWM_RATE_MCS_CCK_MSK (1 << IWM_RATE_MCS_CCK_POS) 3973 3974 /* Bit 26: (1) VHT format, (0) legacy format in bits 8:0 */ 3975 #define IWM_RATE_MCS_VHT_POS 26 3976 #define IWM_RATE_MCS_VHT_MSK (1 << IWM_RATE_MCS_VHT_POS) 3977 3978 3979 /* 3980 * High-throughput (HT) rate format for bits 7:0 3981 * 3982 * 2-0: MCS rate base 3983 * 0) 6 Mbps 3984 * 1) 12 Mbps 3985 * 2) 18 Mbps 3986 * 3) 24 Mbps 3987 * 4) 36 Mbps 3988 * 5) 48 Mbps 3989 * 6) 54 Mbps 3990 * 7) 60 Mbps 3991 * 4-3: 0) Single stream (SISO) 3992 * 1) Dual stream (MIMO) 3993 * 2) Triple stream (MIMO) 3994 * 5: Value of 0x20 in bits 7:0 indicates 6 Mbps HT40 duplicate data 3995 * (bits 7-6 are zero) 3996 * 3997 * Together the low 5 bits work out to the MCS index because we don't 3998 * support MCSes above 15/23, and 0-7 have one stream, 8-15 have two 3999 * streams and 16-23 have three streams. We could also support MCS 32 4000 * which is the duplicate 20 MHz MCS (bit 5 set, all others zero.) 4001 */ 4002 #define IWM_RATE_HT_MCS_RATE_CODE_MSK 0x7 4003 #define IWM_RATE_HT_MCS_NSS_POS 3 4004 #define IWM_RATE_HT_MCS_NSS_MSK (3 << IWM_RATE_HT_MCS_NSS_POS) 4005 4006 /* Bit 10: (1) Use Green Field preamble */ 4007 #define IWM_RATE_HT_MCS_GF_POS 10 4008 #define IWM_RATE_HT_MCS_GF_MSK (1 << IWM_RATE_HT_MCS_GF_POS) 4009 4010 #define IWM_RATE_HT_MCS_INDEX_MSK 0x3f 4011 4012 /* 4013 * Very High-throughput (VHT) rate format for bits 7:0 4014 * 4015 * 3-0: VHT MCS (0-9) 4016 * 5-4: number of streams - 1: 4017 * 0) Single stream (SISO) 4018 * 1) Dual stream (MIMO) 4019 * 2) Triple stream (MIMO) 4020 */ 4021 4022 /* Bit 4-5: (0) SISO, (1) MIMO2 (2) MIMO3 */ 4023 #define IWM_RATE_VHT_MCS_RATE_CODE_MSK 0xf 4024 #define IWM_RATE_VHT_MCS_NSS_POS 4 4025 #define IWM_RATE_VHT_MCS_NSS_MSK (3 << IWM_RATE_VHT_MCS_NSS_POS) 4026 4027 /* 4028 * Legacy OFDM rate format for bits 7:0 4029 * 4030 * 3-0: 0xD) 6 Mbps 4031 * 0xF) 9 Mbps 4032 * 0x5) 12 Mbps 4033 * 0x7) 18 Mbps 4034 * 0x9) 24 Mbps 4035 * 0xB) 36 Mbps 4036 * 0x1) 48 Mbps 4037 * 0x3) 54 Mbps 4038 * (bits 7-4 are 0) 4039 * 4040 * Legacy CCK rate format for bits 7:0: 4041 * bit 8 is 0, bit 26 is 0, bit 9 is 1 (CCK): 4042 * 4043 * 6-0: 10) 1 Mbps 4044 * 20) 2 Mbps 4045 * 55) 5.5 Mbps 4046 * 110) 11 Mbps 4047 * (bit 7 is 0) 4048 */ 4049 #define IWM_RATE_LEGACY_RATE_MSK 0xff 4050 4051 4052 /* 4053 * Bit 11-12: (0) 20MHz, (1) 40MHz, (2) 80MHz, (3) 160MHz 4054 * 0 and 1 are valid for HT and VHT, 2 and 3 only for VHT 4055 */ 4056 #define IWM_RATE_MCS_CHAN_WIDTH_POS 11 4057 #define IWM_RATE_MCS_CHAN_WIDTH_MSK (3 << IWM_RATE_MCS_CHAN_WIDTH_POS) 4058 #define IWM_RATE_MCS_CHAN_WIDTH_20 (0 << IWM_RATE_MCS_CHAN_WIDTH_POS) 4059 #define IWM_RATE_MCS_CHAN_WIDTH_40 (1 << IWM_RATE_MCS_CHAN_WIDTH_POS) 4060 #define IWM_RATE_MCS_CHAN_WIDTH_80 (2 << IWM_RATE_MCS_CHAN_WIDTH_POS) 4061 #define IWM_RATE_MCS_CHAN_WIDTH_160 (3 << IWM_RATE_MCS_CHAN_WIDTH_POS) 4062 4063 /* Bit 13: (1) Short guard interval (0.4 usec), (0) normal GI (0.8 usec) */ 4064 #define IWM_RATE_MCS_SGI_POS 13 4065 #define IWM_RATE_MCS_SGI_MSK (1 << IWM_RATE_MCS_SGI_POS) 4066 4067 /* Bit 14-16: Antenna selection (1) Ant A, (2) Ant B, (4) Ant C */ 4068 #define IWM_RATE_MCS_ANT_POS 14 4069 #define IWM_RATE_MCS_ANT_A_MSK (1 << IWM_RATE_MCS_ANT_POS) 4070 #define IWM_RATE_MCS_ANT_B_MSK (2 << IWM_RATE_MCS_ANT_POS) 4071 #define IWM_RATE_MCS_ANT_C_MSK (4 << IWM_RATE_MCS_ANT_POS) 4072 #define IWM_RATE_MCS_ANT_AB_MSK (IWM_RATE_MCS_ANT_A_MSK | \ 4073 IWM_RATE_MCS_ANT_B_MSK) 4074 #define IWM_RATE_MCS_ANT_ABC_MSK (IWM_RATE_MCS_ANT_AB_MSK | \ 4075 IWM_RATE_MCS_ANT_C_MSK) 4076 #define IWM_RATE_MCS_ANT_MSK IWM_RATE_MCS_ANT_ABC_MSK 4077 #define IWM_RATE_MCS_ANT_NUM 3 4078 4079 /* Bit 17-18: (0) SS, (1) SS*2 */ 4080 #define IWM_RATE_MCS_STBC_POS 17 4081 #define IWM_RATE_MCS_STBC_MSK (1 << IWM_RATE_MCS_STBC_POS) 4082 4083 /* Bit 19: (0) Beamforming is off, (1) Beamforming is on */ 4084 #define IWM_RATE_MCS_BF_POS 19 4085 #define IWM_RATE_MCS_BF_MSK (1 << IWM_RATE_MCS_BF_POS) 4086 4087 /* Bit 20: (0) ZLF is off, (1) ZLF is on */ 4088 #define IWM_RATE_MCS_ZLF_POS 20 4089 #define IWM_RATE_MCS_ZLF_MSK (1 << IWM_RATE_MCS_ZLF_POS) 4090 4091 /* Bit 24-25: (0) 20MHz (no dup), (1) 2x20MHz, (2) 4x20MHz, 3 8x20MHz */ 4092 #define IWM_RATE_MCS_DUP_POS 24 4093 #define IWM_RATE_MCS_DUP_MSK (3 << IWM_RATE_MCS_DUP_POS) 4094 4095 /* Bit 27: (1) LDPC enabled, (0) LDPC disabled */ 4096 #define IWM_RATE_MCS_LDPC_POS 27 4097 #define IWM_RATE_MCS_LDPC_MSK (1 << IWM_RATE_MCS_LDPC_POS) 4098 4099 4100 /* Link Quality definitions */ 4101 4102 /* # entries in rate scale table to support Tx retries */ 4103 #define IWM_LQ_MAX_RETRY_NUM 16 4104 4105 /* Link quality command flags bit fields */ 4106 4107 /* Bit 0: (0) Don't use RTS (1) Use RTS */ 4108 #define IWM_LQ_FLAG_USE_RTS_POS 0 4109 #define IWM_LQ_FLAG_USE_RTS_MSK (1 << IWM_LQ_FLAG_USE_RTS_POS) 4110 4111 /* Bit 1-3: LQ command color. Used to match responses to LQ commands */ 4112 #define IWM_LQ_FLAG_COLOR_POS 1 4113 #define IWM_LQ_FLAG_COLOR_MSK (7 << IWM_LQ_FLAG_COLOR_POS) 4114 4115 /* Bit 4-5: Tx RTS BW Signalling 4116 * (0) No RTS BW signalling 4117 * (1) Static BW signalling 4118 * (2) Dynamic BW signalling 4119 */ 4120 #define IWM_LQ_FLAG_RTS_BW_SIG_POS 4 4121 #define IWM_LQ_FLAG_RTS_BW_SIG_NONE (0 << IWM_LQ_FLAG_RTS_BW_SIG_POS) 4122 #define IWM_LQ_FLAG_RTS_BW_SIG_STATIC (1 << IWM_LQ_FLAG_RTS_BW_SIG_POS) 4123 #define IWM_LQ_FLAG_RTS_BW_SIG_DYNAMIC (2 << IWM_LQ_FLAG_RTS_BW_SIG_POS) 4124 4125 /* Bit 6: (0) No dynamic BW selection (1) Allow dynamic BW selection 4126 * Dyanmic BW selection allows Tx with narrower BW then requested in rates 4127 */ 4128 #define IWM_LQ_FLAG_DYNAMIC_BW_POS 6 4129 #define IWM_LQ_FLAG_DYNAMIC_BW_MSK (1 << IWM_LQ_FLAG_DYNAMIC_BW_POS) 4130 4131 /** 4132 * struct iwm_lq_cmd - link quality command 4133 * @sta_id: station to update 4134 * @control: not used 4135 * @flags: combination of IWM_LQ_FLAG_* 4136 * @mimo_delim: the first SISO index in rs_table, which separates MIMO 4137 * and SISO rates 4138 * @single_stream_ant_msk: best antenna for SISO (can be dual in CDD). 4139 * Should be ANT_[ABC] 4140 * @dual_stream_ant_msk: best antennas for MIMO, combination of ANT_[ABC] 4141 * @initial_rate_index: first index from rs_table per AC category 4142 * @agg_time_limit: aggregation max time threshold in usec/100, meaning 4143 * value of 100 is one usec. Range is 100 to 8000 4144 * @agg_disable_start_th: try-count threshold for starting aggregation. 4145 * If a frame has higher try-count, it should not be selected for 4146 * starting an aggregation sequence. 4147 * @agg_frame_cnt_limit: max frame count in an aggregation. 4148 * 0: no limit 4149 * 1: no aggregation (one frame per aggregation) 4150 * 2 - 0x3f: maximal number of frames (up to 3f == 63) 4151 * @rs_table: array of rates for each TX try, each is rate_n_flags, 4152 * meaning it is a combination of IWM_RATE_MCS_* and IWM_RATE_*_PLCP 4153 * @bf_params: beam forming params, currently not used 4154 */ 4155 struct iwm_lq_cmd { 4156 uint8_t sta_id; 4157 uint8_t reserved1; 4158 uint16_t control; 4159 /* LINK_QUAL_GENERAL_PARAMS_API_S_VER_1 */ 4160 uint8_t flags; 4161 uint8_t mimo_delim; 4162 uint8_t single_stream_ant_msk; 4163 uint8_t dual_stream_ant_msk; 4164 uint8_t initial_rate_index[IWM_AC_NUM]; 4165 /* LINK_QUAL_AGG_PARAMS_API_S_VER_1 */ 4166 uint16_t agg_time_limit; 4167 uint8_t agg_disable_start_th; 4168 uint8_t agg_frame_cnt_limit; 4169 uint32_t reserved2; 4170 uint32_t rs_table[IWM_LQ_MAX_RETRY_NUM]; 4171 uint32_t bf_params; 4172 }; /* LINK_QUALITY_CMD_API_S_VER_1 */ 4173 4174 /* 4175 * END mvm/fw-api-rs.h 4176 */ 4177 4178 /* 4179 * BEGIN mvm/fw-api-tx.h 4180 */ 4181 4182 /** 4183 * enum iwm_tx_flags - bitmasks for tx_flags in TX command 4184 * @IWM_TX_CMD_FLG_PROT_REQUIRE: use RTS or CTS-to-self to protect the frame 4185 * @IWM_TX_CMD_FLG_ACK: expect ACK from receiving station 4186 * @IWM_TX_CMD_FLG_STA_RATE: use RS table with initial index from the TX command. 4187 * Otherwise, use rate_n_flags from the TX command 4188 * @IWM_TX_CMD_FLG_BA: this frame is a block ack 4189 * @IWM_TX_CMD_FLG_BAR: this frame is a BA request, immediate BAR is expected 4190 * Must set IWM_TX_CMD_FLG_ACK with this flag. 4191 * @IWM_TX_CMD_FLG_TXOP_PROT: protect frame with full TXOP protection 4192 * @IWM_TX_CMD_FLG_VHT_NDPA: mark frame is NDPA for VHT beamformer sequence 4193 * @IWM_TX_CMD_FLG_HT_NDPA: mark frame is NDPA for HT beamformer sequence 4194 * @IWM_TX_CMD_FLG_CSI_FDBK2HOST: mark to send feedback to host (only if good CRC) 4195 * @IWM_TX_CMD_FLG_BT_DIS: disable BT priority for this frame 4196 * @IWM_TX_CMD_FLG_SEQ_CTL: set if FW should override the sequence control. 4197 * Should be set for mgmt, non-QOS data, mcast, bcast and in scan command 4198 * @IWM_TX_CMD_FLG_MORE_FRAG: this frame is non-last MPDU 4199 * @IWM_TX_CMD_FLG_NEXT_FRAME: this frame includes information of the next frame 4200 * @IWM_TX_CMD_FLG_TSF: FW should calculate and insert TSF in the frame 4201 * Should be set for beacons and probe responses 4202 * @IWM_TX_CMD_FLG_CALIB: activate PA TX power calibrations 4203 * @IWM_TX_CMD_FLG_KEEP_SEQ_CTL: if seq_ctl is set, don't increase inner seq count 4204 * @IWM_TX_CMD_FLG_AGG_START: allow this frame to start aggregation 4205 * @IWM_TX_CMD_FLG_MH_PAD: driver inserted 2 byte padding after MAC header. 4206 * Should be set for 26/30 length MAC headers 4207 * @IWM_TX_CMD_FLG_RESP_TO_DRV: zero this if the response should go only to FW 4208 * @IWM_TX_CMD_FLG_CCMP_AGG: this frame uses CCMP for aggregation acceleration 4209 * @IWM_TX_CMD_FLG_TKIP_MIC_DONE: FW already performed TKIP MIC calculation 4210 * @IWM_TX_CMD_FLG_DUR: disable duration overwriting used in PS-Poll Assoc-id 4211 * @IWM_TX_CMD_FLG_FW_DROP: FW should mark frame to be dropped 4212 * @IWM_TX_CMD_FLG_EXEC_PAPD: execute PAPD 4213 * @IWM_TX_CMD_FLG_PAPD_TYPE: 0 for reference power, 1 for nominal power 4214 * @IWM_TX_CMD_FLG_HCCA_CHUNK: mark start of TSPEC chunk 4215 */ 4216 enum iwm_tx_flags { 4217 IWM_TX_CMD_FLG_PROT_REQUIRE = (1 << 0), 4218 IWM_TX_CMD_FLG_ACK = (1 << 3), 4219 IWM_TX_CMD_FLG_STA_RATE = (1 << 4), 4220 IWM_TX_CMD_FLG_BA = (1 << 5), 4221 IWM_TX_CMD_FLG_BAR = (1 << 6), 4222 IWM_TX_CMD_FLG_TXOP_PROT = (1 << 7), 4223 IWM_TX_CMD_FLG_VHT_NDPA = (1 << 8), 4224 IWM_TX_CMD_FLG_HT_NDPA = (1 << 9), 4225 IWM_TX_CMD_FLG_CSI_FDBK2HOST = (1 << 10), 4226 IWM_TX_CMD_FLG_BT_DIS = (1 << 12), 4227 IWM_TX_CMD_FLG_SEQ_CTL = (1 << 13), 4228 IWM_TX_CMD_FLG_MORE_FRAG = (1 << 14), 4229 IWM_TX_CMD_FLG_NEXT_FRAME = (1 << 15), 4230 IWM_TX_CMD_FLG_TSF = (1 << 16), 4231 IWM_TX_CMD_FLG_CALIB = (1 << 17), 4232 IWM_TX_CMD_FLG_KEEP_SEQ_CTL = (1 << 18), 4233 IWM_TX_CMD_FLG_AGG_START = (1 << 19), 4234 IWM_TX_CMD_FLG_MH_PAD = (1 << 20), 4235 IWM_TX_CMD_FLG_RESP_TO_DRV = (1 << 21), 4236 IWM_TX_CMD_FLG_CCMP_AGG = (1 << 22), 4237 IWM_TX_CMD_FLG_TKIP_MIC_DONE = (1 << 23), 4238 IWM_TX_CMD_FLG_DUR = (1 << 25), 4239 IWM_TX_CMD_FLG_FW_DROP = (1 << 26), 4240 IWM_TX_CMD_FLG_EXEC_PAPD = (1 << 27), 4241 IWM_TX_CMD_FLG_PAPD_TYPE = (1 << 28), 4242 IWM_TX_CMD_FLG_HCCA_CHUNK = (1 << 31) 4243 }; /* IWM_TX_FLAGS_BITS_API_S_VER_1 */ 4244 4245 /** 4246 * enum iwm_tx_pm_timeouts - pm timeout values in TX command 4247 * @IWM_PM_FRAME_NONE: no need to suspend sleep mode 4248 * @IWM_PM_FRAME_MGMT: fw suspend sleep mode for 100TU 4249 * @IWM_PM_FRAME_ASSOC: fw suspend sleep mode for 10sec 4250 */ 4251 enum iwm_tx_pm_timeouts { 4252 IWM_PM_FRAME_NONE = 0, 4253 IWM_PM_FRAME_MGMT = 2, 4254 IWM_PM_FRAME_ASSOC = 3, 4255 }; 4256 4257 /* 4258 * TX command security control 4259 */ 4260 #define IWM_TX_CMD_SEC_WEP 0x01 4261 #define IWM_TX_CMD_SEC_CCM 0x02 4262 #define IWM_TX_CMD_SEC_TKIP 0x03 4263 #define IWM_TX_CMD_SEC_EXT 0x04 4264 #define IWM_TX_CMD_SEC_MSK 0x07 4265 #define IWM_TX_CMD_SEC_WEP_KEY_IDX_POS 6 4266 #define IWM_TX_CMD_SEC_WEP_KEY_IDX_MSK 0xc0 4267 #define IWM_TX_CMD_SEC_KEY128 0x08 4268 4269 /* TODO: how does these values are OK with only 16 bit variable??? */ 4270 /* 4271 * TX command next frame info 4272 * 4273 * bits 0:2 - security control (IWM_TX_CMD_SEC_*) 4274 * bit 3 - immediate ACK required 4275 * bit 4 - rate is taken from STA table 4276 * bit 5 - frame belongs to BA stream 4277 * bit 6 - immediate BA response expected 4278 * bit 7 - unused 4279 * bits 8:15 - Station ID 4280 * bits 16:31 - rate 4281 */ 4282 #define IWM_TX_CMD_NEXT_FRAME_ACK_MSK (0x8) 4283 #define IWM_TX_CMD_NEXT_FRAME_STA_RATE_MSK (0x10) 4284 #define IWM_TX_CMD_NEXT_FRAME_BA_MSK (0x20) 4285 #define IWM_TX_CMD_NEXT_FRAME_IMM_BA_RSP_MSK (0x40) 4286 #define IWM_TX_CMD_NEXT_FRAME_FLAGS_MSK (0xf8) 4287 #define IWM_TX_CMD_NEXT_FRAME_STA_ID_MSK (0xff00) 4288 #define IWM_TX_CMD_NEXT_FRAME_STA_ID_POS (8) 4289 #define IWM_TX_CMD_NEXT_FRAME_RATE_MSK (0xffff0000) 4290 #define IWM_TX_CMD_NEXT_FRAME_RATE_POS (16) 4291 4292 /* 4293 * TX command Frame life time in us - to be written in pm_frame_timeout 4294 */ 4295 #define IWM_TX_CMD_LIFE_TIME_INFINITE 0xFFFFFFFF 4296 #define IWM_TX_CMD_LIFE_TIME_DEFAULT 2000000 /* 2000 ms*/ 4297 #define IWM_TX_CMD_LIFE_TIME_PROBE_RESP 40000 /* 40 ms */ 4298 #define IWM_TX_CMD_LIFE_TIME_EXPIRED_FRAME 0 4299 4300 /* 4301 * TID for non QoS frames - to be written in tid_tspec 4302 */ 4303 #define IWM_TID_NON_QOS IWM_MAX_TID_COUNT 4304 4305 /* 4306 * Limits on the retransmissions - to be written in {data,rts}_retry_limit 4307 */ 4308 #define IWM_DEFAULT_TX_RETRY 15 4309 #define IWM_MGMT_DFAULT_RETRY_LIMIT 3 4310 #define IWM_RTS_DFAULT_RETRY_LIMIT 60 4311 #define IWM_BAR_DFAULT_RETRY_LIMIT 60 4312 #define IWM_LOW_RETRY_LIMIT 7 4313 4314 /* TODO: complete documentation for try_cnt and btkill_cnt */ 4315 /** 4316 * struct iwm_tx_cmd - TX command struct to FW 4317 * ( IWM_TX_CMD = 0x1c ) 4318 * @len: in bytes of the payload, see below for details 4319 * @next_frame_len: same as len, but for next frame (0 if not applicable) 4320 * Used for fragmentation and bursting, but not in 11n aggregation. 4321 * @tx_flags: combination of IWM_TX_CMD_FLG_* 4322 * @rate_n_flags: rate for *all* Tx attempts, if IWM_TX_CMD_FLG_STA_RATE_MSK is 4323 * cleared. Combination of IWM_RATE_MCS_* 4324 * @sta_id: index of destination station in FW station table 4325 * @sec_ctl: security control, IWM_TX_CMD_SEC_* 4326 * @initial_rate_index: index into the rate table for initial TX attempt. 4327 * Applied if IWM_TX_CMD_FLG_STA_RATE_MSK is set, normally 0 for data frames. 4328 * @key: security key 4329 * @next_frame_flags: IWM_TX_CMD_SEC_* and IWM_TX_CMD_NEXT_FRAME_* 4330 * @life_time: frame life time (usecs??) 4331 * @dram_lsb_ptr: Physical address of scratch area in the command (try_cnt + 4332 * btkill_cnd + reserved), first 32 bits. "0" disables usage. 4333 * @dram_msb_ptr: upper bits of the scratch physical address 4334 * @rts_retry_limit: max attempts for RTS 4335 * @data_retry_limit: max attempts to send the data packet 4336 * @tid_spec: TID/tspec 4337 * @pm_frame_timeout: PM TX frame timeout 4338 * @driver_txop: duration od EDCA TXOP, in 32-usec units. Set this if not 4339 * specified by HCCA protocol 4340 * 4341 * The byte count (both len and next_frame_len) includes MAC header 4342 * (24/26/30/32 bytes) 4343 * + 2 bytes pad if 26/30 header size 4344 * + 8 byte IV for CCM or TKIP (not used for WEP) 4345 * + Data payload 4346 * + 8-byte MIC (not used for CCM/WEP) 4347 * It does not include post-MAC padding, i.e., 4348 * MIC (CCM) 8 bytes, ICV (WEP/TKIP/CKIP) 4 bytes, CRC 4 bytes. 4349 * Range of len: 14-2342 bytes. 4350 * 4351 * After the struct fields the MAC header is placed, plus any padding, 4352 * and then the actial payload. 4353 */ 4354 struct iwm_tx_cmd { 4355 uint16_t len; 4356 uint16_t next_frame_len; 4357 uint32_t tx_flags; 4358 struct { 4359 uint8_t try_cnt; 4360 uint8_t btkill_cnt; 4361 uint16_t reserved; 4362 } scratch; /* DRAM_SCRATCH_API_U_VER_1 */ 4363 uint32_t rate_n_flags; 4364 uint8_t sta_id; 4365 uint8_t sec_ctl; 4366 uint8_t initial_rate_index; 4367 uint8_t reserved2; 4368 uint8_t key[16]; 4369 uint16_t next_frame_flags; 4370 uint16_t reserved3; 4371 uint32_t life_time; 4372 uint32_t dram_lsb_ptr; 4373 uint8_t dram_msb_ptr; 4374 uint8_t rts_retry_limit; 4375 uint8_t data_retry_limit; 4376 uint8_t tid_tspec; 4377 uint16_t pm_frame_timeout; 4378 uint16_t driver_txop; 4379 uint8_t payload[0]; 4380 struct ieee80211_frame hdr[0]; 4381 } __packed; /* IWM_TX_CMD_API_S_VER_3 */ 4382 4383 /* 4384 * TX response related data 4385 */ 4386 4387 /* 4388 * enum iwm_tx_status - status that is returned by the fw after attempts to Tx 4389 * @IWM_TX_STATUS_SUCCESS: 4390 * @IWM_TX_STATUS_DIRECT_DONE: 4391 * @IWM_TX_STATUS_POSTPONE_DELAY: 4392 * @IWM_TX_STATUS_POSTPONE_FEW_BYTES: 4393 * @IWM_TX_STATUS_POSTPONE_BT_PRIO: 4394 * @IWM_TX_STATUS_POSTPONE_QUIET_PERIOD: 4395 * @IWM_TX_STATUS_POSTPONE_CALC_TTAK: 4396 * @IWM_TX_STATUS_FAIL_INTERNAL_CROSSED_RETRY: 4397 * @IWM_TX_STATUS_FAIL_SHORT_LIMIT: 4398 * @IWM_TX_STATUS_FAIL_LONG_LIMIT: 4399 * @IWM_TX_STATUS_FAIL_UNDERRUN: 4400 * @IWM_TX_STATUS_FAIL_DRAIN_FLOW: 4401 * @IWM_TX_STATUS_FAIL_RFKILL_FLUSH: 4402 * @IWM_TX_STATUS_FAIL_LIFE_EXPIRE: 4403 * @IWM_TX_STATUS_FAIL_DEST_PS: 4404 * @IWM_TX_STATUS_FAIL_HOST_ABORTED: 4405 * @IWM_TX_STATUS_FAIL_BT_RETRY: 4406 * @IWM_TX_STATUS_FAIL_STA_INVALID: 4407 * @IWM_TX_TATUS_FAIL_FRAG_DROPPED: 4408 * @IWM_TX_STATUS_FAIL_TID_DISABLE: 4409 * @IWM_TX_STATUS_FAIL_FIFO_FLUSHED: 4410 * @IWM_TX_STATUS_FAIL_SMALL_CF_POLL: 4411 * @IWM_TX_STATUS_FAIL_FW_DROP: 4412 * @IWM_TX_STATUS_FAIL_STA_COLOR_MISMATCH: mismatch between color of Tx cmd and 4413 * STA table 4414 * @IWM_TX_FRAME_STATUS_INTERNAL_ABORT: 4415 * @IWM_TX_MODE_MSK: 4416 * @IWM_TX_MODE_NO_BURST: 4417 * @IWM_TX_MODE_IN_BURST_SEQ: 4418 * @IWM_TX_MODE_FIRST_IN_BURST: 4419 * @IWM_TX_QUEUE_NUM_MSK: 4420 * 4421 * Valid only if frame_count =1 4422 * TODO: complete documentation 4423 */ 4424 enum iwm_tx_status { 4425 IWM_TX_STATUS_MSK = 0x000000ff, 4426 IWM_TX_STATUS_SUCCESS = 0x01, 4427 IWM_TX_STATUS_DIRECT_DONE = 0x02, 4428 /* postpone TX */ 4429 IWM_TX_STATUS_POSTPONE_DELAY = 0x40, 4430 IWM_TX_STATUS_POSTPONE_FEW_BYTES = 0x41, 4431 IWM_TX_STATUS_POSTPONE_BT_PRIO = 0x42, 4432 IWM_TX_STATUS_POSTPONE_QUIET_PERIOD = 0x43, 4433 IWM_TX_STATUS_POSTPONE_CALC_TTAK = 0x44, 4434 /* abort TX */ 4435 IWM_TX_STATUS_FAIL_INTERNAL_CROSSED_RETRY = 0x81, 4436 IWM_TX_STATUS_FAIL_SHORT_LIMIT = 0x82, 4437 IWM_TX_STATUS_FAIL_LONG_LIMIT = 0x83, 4438 IWM_TX_STATUS_FAIL_UNDERRUN = 0x84, 4439 IWM_TX_STATUS_FAIL_DRAIN_FLOW = 0x85, 4440 IWM_TX_STATUS_FAIL_RFKILL_FLUSH = 0x86, 4441 IWM_TX_STATUS_FAIL_LIFE_EXPIRE = 0x87, 4442 IWM_TX_STATUS_FAIL_DEST_PS = 0x88, 4443 IWM_TX_STATUS_FAIL_HOST_ABORTED = 0x89, 4444 IWM_TX_STATUS_FAIL_BT_RETRY = 0x8a, 4445 IWM_TX_STATUS_FAIL_STA_INVALID = 0x8b, 4446 IWM_TX_STATUS_FAIL_FRAG_DROPPED = 0x8c, 4447 IWM_TX_STATUS_FAIL_TID_DISABLE = 0x8d, 4448 IWM_TX_STATUS_FAIL_FIFO_FLUSHED = 0x8e, 4449 IWM_TX_STATUS_FAIL_SMALL_CF_POLL = 0x8f, 4450 IWM_TX_STATUS_FAIL_FW_DROP = 0x90, 4451 IWM_TX_STATUS_FAIL_STA_COLOR_MISMATCH = 0x91, 4452 IWM_TX_STATUS_INTERNAL_ABORT = 0x92, 4453 IWM_TX_MODE_MSK = 0x00000f00, 4454 IWM_TX_MODE_NO_BURST = 0x00000000, 4455 IWM_TX_MODE_IN_BURST_SEQ = 0x00000100, 4456 IWM_TX_MODE_FIRST_IN_BURST = 0x00000200, 4457 IWM_TX_QUEUE_NUM_MSK = 0x0001f000, 4458 IWM_TX_NARROW_BW_MSK = 0x00060000, 4459 IWM_TX_NARROW_BW_1DIV2 = 0x00020000, 4460 IWM_TX_NARROW_BW_1DIV4 = 0x00040000, 4461 IWM_TX_NARROW_BW_1DIV8 = 0x00060000, 4462 }; 4463 4464 /* 4465 * enum iwm_tx_agg_status - TX aggregation status 4466 * @IWM_AGG_TX_STATE_STATUS_MSK: 4467 * @IWM_AGG_TX_STATE_TRANSMITTED: 4468 * @IWM_AGG_TX_STATE_UNDERRUN: 4469 * @IWM_AGG_TX_STATE_BT_PRIO: 4470 * @IWM_AGG_TX_STATE_FEW_BYTES: 4471 * @IWM_AGG_TX_STATE_ABORT: 4472 * @IWM_AGG_TX_STATE_LAST_SENT_TTL: 4473 * @IWM_AGG_TX_STATE_LAST_SENT_TRY_CNT: 4474 * @IWM_AGG_TX_STATE_LAST_SENT_BT_KILL: 4475 * @IWM_AGG_TX_STATE_SCD_QUERY: 4476 * @IWM_AGG_TX_STATE_TEST_BAD_CRC32: 4477 * @IWM_AGG_TX_STATE_RESPONSE: 4478 * @IWM_AGG_TX_STATE_DUMP_TX: 4479 * @IWM_AGG_TX_STATE_DELAY_TX: 4480 * @IWM_AGG_TX_STATE_TRY_CNT_MSK: Retry count for 1st frame in aggregation (retries 4481 * occur if tx failed for this frame when it was a member of a previous 4482 * aggregation block). If rate scaling is used, retry count indicates the 4483 * rate table entry used for all frames in the new agg. 4484 *@ IWM_AGG_TX_STATE_SEQ_NUM_MSK: Command ID and sequence number of Tx command for 4485 * this frame 4486 * 4487 * TODO: complete documentation 4488 */ 4489 enum iwm_tx_agg_status { 4490 IWM_AGG_TX_STATE_STATUS_MSK = 0x00fff, 4491 IWM_AGG_TX_STATE_TRANSMITTED = 0x000, 4492 IWM_AGG_TX_STATE_UNDERRUN = 0x001, 4493 IWM_AGG_TX_STATE_BT_PRIO = 0x002, 4494 IWM_AGG_TX_STATE_FEW_BYTES = 0x004, 4495 IWM_AGG_TX_STATE_ABORT = 0x008, 4496 IWM_AGG_TX_STATE_LAST_SENT_TTL = 0x010, 4497 IWM_AGG_TX_STATE_LAST_SENT_TRY_CNT = 0x020, 4498 IWM_AGG_TX_STATE_LAST_SENT_BT_KILL = 0x040, 4499 IWM_AGG_TX_STATE_SCD_QUERY = 0x080, 4500 IWM_AGG_TX_STATE_TEST_BAD_CRC32 = 0x0100, 4501 IWM_AGG_TX_STATE_RESPONSE = 0x1ff, 4502 IWM_AGG_TX_STATE_DUMP_TX = 0x200, 4503 IWM_AGG_TX_STATE_DELAY_TX = 0x400, 4504 IWM_AGG_TX_STATE_TRY_CNT_POS = 12, 4505 IWM_AGG_TX_STATE_TRY_CNT_MSK = 0xf << IWM_AGG_TX_STATE_TRY_CNT_POS, 4506 }; 4507 4508 #define IWM_AGG_TX_STATE_LAST_SENT_MSK (IWM_AGG_TX_STATE_LAST_SENT_TTL| \ 4509 IWM_AGG_TX_STATE_LAST_SENT_TRY_CNT| \ 4510 IWM_AGG_TX_STATE_LAST_SENT_BT_KILL) 4511 4512 /* 4513 * The mask below describes a status where we are absolutely sure that the MPDU 4514 * wasn't sent. For BA/Underrun we cannot be that sure. All we know that we've 4515 * written the bytes to the TXE, but we know nothing about what the DSP did. 4516 */ 4517 #define IWM_AGG_TX_STAT_FRAME_NOT_SENT (IWM_AGG_TX_STATE_FEW_BYTES | \ 4518 IWM_AGG_TX_STATE_ABORT | \ 4519 IWM_AGG_TX_STATE_SCD_QUERY) 4520 4521 /* 4522 * IWM_REPLY_TX = 0x1c (response) 4523 * 4524 * This response may be in one of two slightly different formats, indicated 4525 * by the frame_count field: 4526 * 4527 * 1) No aggregation (frame_count == 1). This reports Tx results for a single 4528 * frame. Multiple attempts, at various bit rates, may have been made for 4529 * this frame. 4530 * 4531 * 2) Aggregation (frame_count > 1). This reports Tx results for two or more 4532 * frames that used block-acknowledge. All frames were transmitted at 4533 * same rate. Rate scaling may have been used if first frame in this new 4534 * agg block failed in previous agg block(s). 4535 * 4536 * Note that, for aggregation, ACK (block-ack) status is not delivered 4537 * here; block-ack has not been received by the time the device records 4538 * this status. 4539 * This status relates to reasons the tx might have been blocked or aborted 4540 * within the device, rather than whether it was received successfully by 4541 * the destination station. 4542 */ 4543 4544 /** 4545 * struct iwm_agg_tx_status - per packet TX aggregation status 4546 * @status: enum iwm_tx_agg_status 4547 * @sequence: Sequence # for this frame's Tx cmd (not SSN!) 4548 */ 4549 struct iwm_agg_tx_status { 4550 uint16_t status; 4551 uint16_t sequence; 4552 } __packed; 4553 4554 /* 4555 * definitions for initial rate index field 4556 * bits [3:0] initial rate index 4557 * bits [6:4] rate table color, used for the initial rate 4558 * bit-7 invalid rate indication 4559 */ 4560 #define IWM_TX_RES_INIT_RATE_INDEX_MSK 0x0f 4561 #define IWM_TX_RES_RATE_TABLE_COLOR_MSK 0x70 4562 #define IWM_TX_RES_INV_RATE_INDEX_MSK 0x80 4563 4564 #define IWM_MVM_TX_RES_GET_TID(_ra_tid) ((_ra_tid) & 0x0f) 4565 #define IWM_MVM_TX_RES_GET_RA(_ra_tid) ((_ra_tid) >> 4) 4566 4567 /** 4568 * struct iwm_mvm_tx_resp - notifies that fw is TXing a packet 4569 * ( IWM_REPLY_TX = 0x1c ) 4570 * @frame_count: 1 no aggregation, >1 aggregation 4571 * @bt_kill_count: num of times blocked by bluetooth (unused for agg) 4572 * @failure_rts: num of failures due to unsuccessful RTS 4573 * @failure_frame: num failures due to no ACK (unused for agg) 4574 * @initial_rate: for non-agg: rate of the successful Tx. For agg: rate of the 4575 * Tx of all the batch. IWM_RATE_MCS_* 4576 * @wireless_media_time: for non-agg: RTS + CTS + frame tx attempts time + ACK. 4577 * for agg: RTS + CTS + aggregation tx time + block-ack time. 4578 * in usec. 4579 * @pa_status: tx power info 4580 * @pa_integ_res_a: tx power info 4581 * @pa_integ_res_b: tx power info 4582 * @pa_integ_res_c: tx power info 4583 * @measurement_req_id: tx power info 4584 * @tfd_info: TFD information set by the FH 4585 * @seq_ctl: sequence control from the Tx cmd 4586 * @byte_cnt: byte count from the Tx cmd 4587 * @tlc_info: TLC rate info 4588 * @ra_tid: bits [3:0] = ra, bits [7:4] = tid 4589 * @frame_ctrl: frame control 4590 * @status: for non-agg: frame status IWM_TX_STATUS_* 4591 * for agg: status of 1st frame, IWM_AGG_TX_STATE_*; other frame status fields 4592 * follow this one, up to frame_count. 4593 * 4594 * After the array of statuses comes the SSN of the SCD. Look at 4595 * %iwm_mvm_get_scd_ssn for more details. 4596 */ 4597 struct iwm_mvm_tx_resp { 4598 uint8_t frame_count; 4599 uint8_t bt_kill_count; 4600 uint8_t failure_rts; 4601 uint8_t failure_frame; 4602 uint32_t initial_rate; 4603 uint16_t wireless_media_time; 4604 4605 uint8_t pa_status; 4606 uint8_t pa_integ_res_a[3]; 4607 uint8_t pa_integ_res_b[3]; 4608 uint8_t pa_integ_res_c[3]; 4609 uint16_t measurement_req_id; 4610 uint16_t reserved; 4611 4612 uint32_t tfd_info; 4613 uint16_t seq_ctl; 4614 uint16_t byte_cnt; 4615 uint8_t tlc_info; 4616 uint8_t ra_tid; 4617 uint16_t frame_ctrl; 4618 4619 struct iwm_agg_tx_status status; 4620 } __packed; /* IWM_TX_RSP_API_S_VER_3 */ 4621 4622 /** 4623 * struct iwm_mvm_ba_notif - notifies about reception of BA 4624 * ( IWM_BA_NOTIF = 0xc5 ) 4625 * @sta_addr_lo32: lower 32 bits of the MAC address 4626 * @sta_addr_hi16: upper 16 bits of the MAC address 4627 * @sta_id: Index of recipient (BA-sending) station in fw's station table 4628 * @tid: tid of the session 4629 * @seq_ctl: 4630 * @bitmap: the bitmap of the BA notification as seen in the air 4631 * @scd_flow: the tx queue this BA relates to 4632 * @scd_ssn: the index of the last contiguously sent packet 4633 * @txed: number of Txed frames in this batch 4634 * @txed_2_done: number of Acked frames in this batch 4635 */ 4636 struct iwm_mvm_ba_notif { 4637 uint32_t sta_addr_lo32; 4638 uint16_t sta_addr_hi16; 4639 uint16_t reserved; 4640 4641 uint8_t sta_id; 4642 uint8_t tid; 4643 uint16_t seq_ctl; 4644 uint64_t bitmap; 4645 uint16_t scd_flow; 4646 uint16_t scd_ssn; 4647 uint8_t txed; 4648 uint8_t txed_2_done; 4649 uint16_t reserved1; 4650 } __packed; 4651 4652 /* 4653 * struct iwm_mac_beacon_cmd - beacon template command 4654 * @tx: the tx commands associated with the beacon frame 4655 * @template_id: currently equal to the mac context id of the coresponding 4656 * mac. 4657 * @tim_idx: the offset of the tim IE in the beacon 4658 * @tim_size: the length of the tim IE 4659 * @frame: the template of the beacon frame 4660 */ 4661 struct iwm_mac_beacon_cmd { 4662 struct iwm_tx_cmd tx; 4663 uint32_t template_id; 4664 uint32_t tim_idx; 4665 uint32_t tim_size; 4666 struct ieee80211_frame frame[0]; 4667 } __packed; 4668 4669 struct iwm_beacon_notif { 4670 struct iwm_mvm_tx_resp beacon_notify_hdr; 4671 uint64_t tsf; 4672 uint32_t ibss_mgr_status; 4673 } __packed; 4674 4675 /** 4676 * enum iwm_dump_control - dump (flush) control flags 4677 * @IWM_DUMP_TX_FIFO_FLUSH: Dump MSDUs until the FIFO is empty 4678 * and the TFD queues are empty. 4679 */ 4680 enum iwm_dump_control { 4681 IWM_DUMP_TX_FIFO_FLUSH = (1 << 1), 4682 }; 4683 4684 /** 4685 * struct iwm_tx_path_flush_cmd -- queue/FIFO flush command 4686 * @queues_ctl: bitmap of queues to flush 4687 * @flush_ctl: control flags 4688 * @reserved: reserved 4689 */ 4690 struct iwm_tx_path_flush_cmd { 4691 uint32_t queues_ctl; 4692 uint16_t flush_ctl; 4693 uint16_t reserved; 4694 } __packed; /* IWM_TX_PATH_FLUSH_CMD_API_S_VER_1 */ 4695 4696 /** 4697 * iwm_mvm_get_scd_ssn - returns the SSN of the SCD 4698 * @tx_resp: the Tx response from the fw (agg or non-agg) 4699 * 4700 * When the fw sends an AMPDU, it fetches the MPDUs one after the other. Since 4701 * it can't know that everything will go well until the end of the AMPDU, it 4702 * can't know in advance the number of MPDUs that will be sent in the current 4703 * batch. This is why it writes the agg Tx response while it fetches the MPDUs. 4704 * Hence, it can't know in advance what the SSN of the SCD will be at the end 4705 * of the batch. This is why the SSN of the SCD is written at the end of the 4706 * whole struct at a variable offset. This function knows how to cope with the 4707 * variable offset and returns the SSN of the SCD. 4708 */ 4709 static inline uint32_t iwm_mvm_get_scd_ssn(struct iwm_mvm_tx_resp *tx_resp) 4710 { 4711 return le32_to_cpup((uint32_t *)&tx_resp->status + 4712 tx_resp->frame_count) & 0xfff; 4713 } 4714 4715 /* 4716 * END mvm/fw-api-tx.h 4717 */ 4718 4719 /* 4720 * BEGIN mvm/fw-api-scan.h 4721 */ 4722 4723 /** 4724 * struct iwm_scd_txq_cfg_cmd - New txq hw scheduler config command 4725 * @token: 4726 * @sta_id: station id 4727 * @tid: 4728 * @scd_queue: scheduler queue to confiug 4729 * @enable: 1 queue enable, 0 queue disable 4730 * @aggregate: 1 aggregated queue, 0 otherwise 4731 * @tx_fifo: %enum iwm_mvm_tx_fifo 4732 * @window: BA window size 4733 * @ssn: SSN for the BA agreement 4734 */ 4735 struct iwm_scd_txq_cfg_cmd { 4736 uint8_t token; 4737 uint8_t sta_id; 4738 uint8_t tid; 4739 uint8_t scd_queue; 4740 uint8_t enable; 4741 uint8_t aggregate; 4742 uint8_t tx_fifo; 4743 uint8_t window; 4744 uint16_t ssn; 4745 uint16_t reserved; 4746 } __packed; /* SCD_QUEUE_CFG_CMD_API_S_VER_1 */ 4747 4748 /** 4749 * struct iwm_scd_txq_cfg_rsp 4750 * @token: taken from the command 4751 * @sta_id: station id from the command 4752 * @tid: tid from the command 4753 * @scd_queue: scd_queue from the command 4754 */ 4755 struct iwm_scd_txq_cfg_rsp { 4756 uint8_t token; 4757 uint8_t sta_id; 4758 uint8_t tid; 4759 uint8_t scd_queue; 4760 } __packed; /* SCD_QUEUE_CFG_RSP_API_S_VER_1 */ 4761 4762 4763 /* Scan Commands, Responses, Notifications */ 4764 4765 /* Masks for iwm_scan_channel.type flags */ 4766 #define IWM_SCAN_CHANNEL_TYPE_ACTIVE (1 << 0) 4767 #define IWM_SCAN_CHANNEL_NSSIDS(x) (((1 << (x)) - 1) << 1) 4768 4769 /* Max number of IEs for direct SSID scans in a command */ 4770 #define IWM_PROBE_OPTION_MAX 20 4771 4772 /** 4773 * struct iwm_ssid_ie - directed scan network information element 4774 * 4775 * Up to 20 of these may appear in IWM_REPLY_SCAN_CMD, 4776 * selected by "type" bit field in struct iwm_scan_channel; 4777 * each channel may select different ssids from among the 20 entries. 4778 * SSID IEs get transmitted in reverse order of entry. 4779 */ 4780 struct iwm_ssid_ie { 4781 uint8_t id; 4782 uint8_t len; 4783 uint8_t ssid[IEEE80211_NWID_LEN]; 4784 } __packed; /* IWM_SCAN_DIRECT_SSID_IE_API_S_VER_1 */ 4785 4786 /* scan offload */ 4787 #define IWM_SCAN_MAX_BLACKLIST_LEN 64 4788 #define IWM_SCAN_SHORT_BLACKLIST_LEN 16 4789 #define IWM_SCAN_MAX_PROFILES 11 4790 #define IWM_SCAN_OFFLOAD_PROBE_REQ_SIZE 512 4791 4792 /* Default watchdog (in MS) for scheduled scan iteration */ 4793 #define IWM_SCHED_SCAN_WATCHDOG cpu_to_le16(15000) 4794 4795 #define IWM_GOOD_CRC_TH_DEFAULT cpu_to_le16(1) 4796 #define IWM_CAN_ABORT_STATUS 1 4797 4798 #define IWM_FULL_SCAN_MULTIPLIER 5 4799 #define IWM_FAST_SCHED_SCAN_ITERATIONS 3 4800 #define IWM_MAX_SCHED_SCAN_PLANS 2 4801 4802 /** 4803 * iwm_scan_schedule_lmac - schedule of scan offload 4804 * @delay: delay between iterations, in seconds. 4805 * @iterations: num of scan iterations 4806 * @full_scan_mul: number of partial scans before each full scan 4807 */ 4808 struct iwm_scan_schedule_lmac { 4809 uint16_t delay; 4810 uint8_t iterations; 4811 uint8_t full_scan_mul; 4812 } __packed; /* SCAN_SCHEDULE_API_S */ 4813 4814 /** 4815 * iwm_scan_req_tx_cmd - SCAN_REQ_TX_CMD_API_S 4816 * @tx_flags: combination of TX_CMD_FLG_* 4817 * @rate_n_flags: rate for *all* Tx attempts, if TX_CMD_FLG_STA_RATE_MSK is 4818 * cleared. Combination of RATE_MCS_* 4819 * @sta_id: index of destination station in FW station table 4820 * @reserved: for alignment and future use 4821 */ 4822 struct iwm_scan_req_tx_cmd { 4823 uint32_t tx_flags; 4824 uint32_t rate_n_flags; 4825 uint8_t sta_id; 4826 uint8_t reserved[3]; 4827 } __packed; 4828 4829 enum iwm_scan_channel_flags_lmac { 4830 IWM_UNIFIED_SCAN_CHANNEL_FULL = (1 << 27), 4831 IWM_UNIFIED_SCAN_CHANNEL_PARTIAL = (1 << 28), 4832 }; 4833 4834 /** 4835 * iwm_scan_channel_cfg_lmac - SCAN_CHANNEL_CFG_S_VER2 4836 * @flags: bits 1-20: directed scan to i'th ssid 4837 * other bits &enum iwm_scan_channel_flags_lmac 4838 * @channel_number: channel number 1-13 etc 4839 * @iter_count: scan iteration on this channel 4840 * @iter_interval: interval in seconds between iterations on one channel 4841 */ 4842 struct iwm_scan_channel_cfg_lmac { 4843 uint32_t flags; 4844 uint16_t channel_num; 4845 uint16_t iter_count; 4846 uint32_t iter_interval; 4847 } __packed; 4848 4849 /* 4850 * iwm_scan_probe_segment - PROBE_SEGMENT_API_S_VER_1 4851 * @offset: offset in the data block 4852 * @len: length of the segment 4853 */ 4854 struct iwm_scan_probe_segment { 4855 uint16_t offset; 4856 uint16_t len; 4857 } __packed; 4858 4859 /* iwm_scan_probe_req - PROBE_REQUEST_FRAME_API_S_VER_2 4860 * @mac_header: first (and common) part of the probe 4861 * @band_data: band specific data 4862 * @common_data: last (and common) part of the probe 4863 * @buf: raw data block 4864 */ 4865 struct iwm_scan_probe_req { 4866 struct iwm_scan_probe_segment mac_header; 4867 struct iwm_scan_probe_segment band_data[2]; 4868 struct iwm_scan_probe_segment common_data; 4869 uint8_t buf[IWM_SCAN_OFFLOAD_PROBE_REQ_SIZE]; 4870 } __packed; 4871 4872 enum iwm_scan_channel_flags { 4873 IWM_SCAN_CHANNEL_FLAG_EBS = (1 << 0), 4874 IWM_SCAN_CHANNEL_FLAG_EBS_ACCURATE = (1 << 1), 4875 IWM_SCAN_CHANNEL_FLAG_CACHE_ADD = (1 << 2), 4876 }; 4877 4878 /* iwm_scan_channel_opt - CHANNEL_OPTIMIZATION_API_S 4879 * @flags: enum iwm_scan_channel_flags 4880 * @non_ebs_ratio: defines the ratio of number of scan iterations where EBS is 4881 * involved. 4882 * 1 - EBS is disabled. 4883 * 2 - every second scan will be full scan(and so on). 4884 */ 4885 struct iwm_scan_channel_opt { 4886 uint16_t flags; 4887 uint16_t non_ebs_ratio; 4888 } __packed; 4889 4890 /** 4891 * iwm_mvm_lmac_scan_flags 4892 * @IWM_MVM_LMAC_SCAN_FLAG_PASS_ALL: pass all beacons and probe responses 4893 * without filtering. 4894 * @IWM_MVM_LMAC_SCAN_FLAG_PASSIVE: force passive scan on all channels 4895 * @IWM_MVM_LMAC_SCAN_FLAG_PRE_CONNECTION: single channel scan 4896 * @IWM_MVM_LMAC_SCAN_FLAG_ITER_COMPLETE: send iteration complete notification 4897 * @IWM_MVM_LMAC_SCAN_FLAG_MULTIPLE_SSIDS multiple SSID matching 4898 * @IWM_MVM_LMAC_SCAN_FLAG_FRAGMENTED: all passive scans will be fragmented 4899 * @IWM_MVM_LMAC_SCAN_FLAGS_RRM_ENABLED: insert WFA vendor-specific TPC report 4900 * and DS parameter set IEs into probe requests. 4901 * @IWM_MVM_LMAC_SCAN_FLAG_EXTENDED_DWELL: use extended dwell time on channels 4902 * 1, 6 and 11. 4903 * @IWM_MVM_LMAC_SCAN_FLAG_MATCH: Send match found notification on matches 4904 */ 4905 enum iwm_mvm_lmac_scan_flags { 4906 IWM_MVM_LMAC_SCAN_FLAG_PASS_ALL = (1 << 0), 4907 IWM_MVM_LMAC_SCAN_FLAG_PASSIVE = (1 << 1), 4908 IWM_MVM_LMAC_SCAN_FLAG_PRE_CONNECTION = (1 << 2), 4909 IWM_MVM_LMAC_SCAN_FLAG_ITER_COMPLETE = (1 << 3), 4910 IWM_MVM_LMAC_SCAN_FLAG_MULTIPLE_SSIDS = (1 << 4), 4911 IWM_MVM_LMAC_SCAN_FLAG_FRAGMENTED = (1 << 5), 4912 IWM_MVM_LMAC_SCAN_FLAGS_RRM_ENABLED = (1 << 6), 4913 IWM_MVM_LMAC_SCAN_FLAG_EXTENDED_DWELL = (1 << 7), 4914 IWM_MVM_LMAC_SCAN_FLAG_MATCH = (1 << 9), 4915 }; 4916 4917 enum iwm_scan_priority { 4918 IWM_SCAN_PRIORITY_LOW, 4919 IWM_SCAN_PRIORITY_MEDIUM, 4920 IWM_SCAN_PRIORITY_HIGH, 4921 }; 4922 4923 /** 4924 * iwm_scan_req_lmac - SCAN_REQUEST_CMD_API_S_VER_1 4925 * @reserved1: for alignment and future use 4926 * @channel_num: num of channels to scan 4927 * @active-dwell: dwell time for active channels 4928 * @passive-dwell: dwell time for passive channels 4929 * @fragmented-dwell: dwell time for fragmented passive scan 4930 * @extended_dwell: dwell time for channels 1, 6 and 11 (in certain cases) 4931 * @reserved2: for alignment and future use 4932 * @rx_chain_selct: PHY_RX_CHAIN_* flags 4933 * @scan_flags: &enum iwm_mvm_lmac_scan_flags 4934 * @max_out_time: max time (in TU) to be out of associated channel 4935 * @suspend_time: pause scan this long (TUs) when returning to service channel 4936 * @flags: RXON flags 4937 * @filter_flags: RXON filter 4938 * @tx_cmd: tx command for active scan; for 2GHz and for 5GHz 4939 * @direct_scan: list of SSIDs for directed active scan 4940 * @scan_prio: enum iwm_scan_priority 4941 * @iter_num: number of scan iterations 4942 * @delay: delay in seconds before first iteration 4943 * @schedule: two scheduling plans. The first one is finite, the second one can 4944 * be infinite. 4945 * @channel_opt: channel optimization options, for full and partial scan 4946 * @data: channel configuration and probe request packet. 4947 */ 4948 struct iwm_scan_req_lmac { 4949 /* SCAN_REQUEST_FIXED_PART_API_S_VER_7 */ 4950 uint32_t reserved1; 4951 uint8_t n_channels; 4952 uint8_t active_dwell; 4953 uint8_t passive_dwell; 4954 uint8_t fragmented_dwell; 4955 uint8_t extended_dwell; 4956 uint8_t reserved2; 4957 uint16_t rx_chain_select; 4958 uint32_t scan_flags; 4959 uint32_t max_out_time; 4960 uint32_t suspend_time; 4961 /* RX_ON_FLAGS_API_S_VER_1 */ 4962 uint32_t flags; 4963 uint32_t filter_flags; 4964 struct iwm_scan_req_tx_cmd tx_cmd[2]; 4965 struct iwm_ssid_ie direct_scan[IWM_PROBE_OPTION_MAX]; 4966 uint32_t scan_prio; 4967 /* SCAN_REQ_PERIODIC_PARAMS_API_S */ 4968 uint32_t iter_num; 4969 uint32_t delay; 4970 struct iwm_scan_schedule_lmac schedule[IWM_MAX_SCHED_SCAN_PLANS]; 4971 struct iwm_scan_channel_opt channel_opt[2]; 4972 uint8_t data[]; 4973 } __packed; 4974 4975 /** 4976 * iwm_scan_offload_complete - PERIODIC_SCAN_COMPLETE_NTF_API_S_VER_2 4977 * @last_schedule_line: last schedule line executed (fast or regular) 4978 * @last_schedule_iteration: last scan iteration executed before scan abort 4979 * @status: enum iwm_scan_offload_complete_status 4980 * @ebs_status: EBS success status &enum iwm_scan_ebs_status 4981 * @time_after_last_iter; time in seconds elapsed after last iteration 4982 */ 4983 struct iwm_periodic_scan_complete { 4984 uint8_t last_schedule_line; 4985 uint8_t last_schedule_iteration; 4986 uint8_t status; 4987 uint8_t ebs_status; 4988 uint32_t time_after_last_iter; 4989 uint32_t reserved; 4990 } __packed; 4991 4992 /* How many statistics are gathered for each channel */ 4993 #define IWM_SCAN_RESULTS_STATISTICS 1 4994 4995 /** 4996 * enum iwm_scan_complete_status - status codes for scan complete notifications 4997 * @IWM_SCAN_COMP_STATUS_OK: scan completed successfully 4998 * @IWM_SCAN_COMP_STATUS_ABORT: scan was aborted by user 4999 * @IWM_SCAN_COMP_STATUS_ERR_SLEEP: sending null sleep packet failed 5000 * @IWM_SCAN_COMP_STATUS_ERR_CHAN_TIMEOUT: timeout before channel is ready 5001 * @IWM_SCAN_COMP_STATUS_ERR_PROBE: sending probe request failed 5002 * @IWM_SCAN_COMP_STATUS_ERR_WAKEUP: sending null wakeup packet failed 5003 * @IWM_SCAN_COMP_STATUS_ERR_ANTENNAS: invalid antennas chosen at scan command 5004 * @IWM_SCAN_COMP_STATUS_ERR_INTERNAL: internal error caused scan abort 5005 * @IWM_SCAN_COMP_STATUS_ERR_COEX: medium was lost ot WiMax 5006 * @IWM_SCAN_COMP_STATUS_P2P_ACTION_OK: P2P public action frame TX was successful 5007 * (not an error!) 5008 * @IWM_SCAN_COMP_STATUS_ITERATION_END: indicates end of one repeatition the driver 5009 * asked for 5010 * @IWM_SCAN_COMP_STATUS_ERR_ALLOC_TE: scan could not allocate time events 5011 */ 5012 enum iwm_scan_complete_status { 5013 IWM_SCAN_COMP_STATUS_OK = 0x1, 5014 IWM_SCAN_COMP_STATUS_ABORT = 0x2, 5015 IWM_SCAN_COMP_STATUS_ERR_SLEEP = 0x3, 5016 IWM_SCAN_COMP_STATUS_ERR_CHAN_TIMEOUT = 0x4, 5017 IWM_SCAN_COMP_STATUS_ERR_PROBE = 0x5, 5018 IWM_SCAN_COMP_STATUS_ERR_WAKEUP = 0x6, 5019 IWM_SCAN_COMP_STATUS_ERR_ANTENNAS = 0x7, 5020 IWM_SCAN_COMP_STATUS_ERR_INTERNAL = 0x8, 5021 IWM_SCAN_COMP_STATUS_ERR_COEX = 0x9, 5022 IWM_SCAN_COMP_STATUS_P2P_ACTION_OK = 0xA, 5023 IWM_SCAN_COMP_STATUS_ITERATION_END = 0x0B, 5024 IWM_SCAN_COMP_STATUS_ERR_ALLOC_TE = 0x0C, 5025 }; 5026 5027 /** 5028 * struct iwm_scan_results_notif - scan results for one channel 5029 * ( IWM_SCAN_RESULTS_NOTIFICATION = 0x83 ) 5030 * @channel: which channel the results are from 5031 * @band: 0 for 5.2 GHz, 1 for 2.4 GHz 5032 * @probe_status: IWM_SCAN_PROBE_STATUS_*, indicates success of probe request 5033 * @num_probe_not_sent: # of request that weren't sent due to not enough time 5034 * @duration: duration spent in channel, in usecs 5035 * @statistics: statistics gathered for this channel 5036 */ 5037 struct iwm_scan_results_notif { 5038 uint8_t channel; 5039 uint8_t band; 5040 uint8_t probe_status; 5041 uint8_t num_probe_not_sent; 5042 uint32_t duration; 5043 uint32_t statistics[IWM_SCAN_RESULTS_STATISTICS]; 5044 } __packed; /* IWM_SCAN_RESULT_NTF_API_S_VER_2 */ 5045 5046 enum iwm_scan_framework_client { 5047 IWM_SCAN_CLIENT_SCHED_SCAN = (1 << 0), 5048 IWM_SCAN_CLIENT_NETDETECT = (1 << 1), 5049 IWM_SCAN_CLIENT_ASSET_TRACKING = (1 << 2), 5050 }; 5051 5052 /** 5053 * iwm_scan_offload_blacklist - IWM_SCAN_OFFLOAD_BLACKLIST_S 5054 * @ssid: MAC address to filter out 5055 * @reported_rssi: AP rssi reported to the host 5056 * @client_bitmap: clients ignore this entry - enum scan_framework_client 5057 */ 5058 struct iwm_scan_offload_blacklist { 5059 uint8_t ssid[IEEE80211_ADDR_LEN]; 5060 uint8_t reported_rssi; 5061 uint8_t client_bitmap; 5062 } __packed; 5063 5064 enum iwm_scan_offload_network_type { 5065 IWM_NETWORK_TYPE_BSS = 1, 5066 IWM_NETWORK_TYPE_IBSS = 2, 5067 IWM_NETWORK_TYPE_ANY = 3, 5068 }; 5069 5070 enum iwm_scan_offload_band_selection { 5071 IWM_SCAN_OFFLOAD_SELECT_2_4 = 0x4, 5072 IWM_SCAN_OFFLOAD_SELECT_5_2 = 0x8, 5073 IWM_SCAN_OFFLOAD_SELECT_ANY = 0xc, 5074 }; 5075 5076 /** 5077 * iwm_scan_offload_profile - IWM_SCAN_OFFLOAD_PROFILE_S 5078 * @ssid_index: index to ssid list in fixed part 5079 * @unicast_cipher: encryption olgorithm to match - bitmap 5080 * @aut_alg: authentication olgorithm to match - bitmap 5081 * @network_type: enum iwm_scan_offload_network_type 5082 * @band_selection: enum iwm_scan_offload_band_selection 5083 * @client_bitmap: clients waiting for match - enum scan_framework_client 5084 */ 5085 struct iwm_scan_offload_profile { 5086 uint8_t ssid_index; 5087 uint8_t unicast_cipher; 5088 uint8_t auth_alg; 5089 uint8_t network_type; 5090 uint8_t band_selection; 5091 uint8_t client_bitmap; 5092 uint8_t reserved[2]; 5093 } __packed; 5094 5095 /** 5096 * iwm_scan_offload_profile_cfg - IWM_SCAN_OFFLOAD_PROFILES_CFG_API_S_VER_1 5097 * @blaclist: AP list to filter off from scan results 5098 * @profiles: profiles to search for match 5099 * @blacklist_len: length of blacklist 5100 * @num_profiles: num of profiles in the list 5101 * @match_notify: clients waiting for match found notification 5102 * @pass_match: clients waiting for the results 5103 * @active_clients: active clients bitmap - enum scan_framework_client 5104 * @any_beacon_notify: clients waiting for match notification without match 5105 */ 5106 struct iwm_scan_offload_profile_cfg { 5107 struct iwm_scan_offload_profile profiles[IWM_SCAN_MAX_PROFILES]; 5108 uint8_t blacklist_len; 5109 uint8_t num_profiles; 5110 uint8_t match_notify; 5111 uint8_t pass_match; 5112 uint8_t active_clients; 5113 uint8_t any_beacon_notify; 5114 uint8_t reserved[2]; 5115 } __packed; 5116 5117 enum iwm_scan_offload_complete_status { 5118 IWM_SCAN_OFFLOAD_COMPLETED = 1, 5119 IWM_SCAN_OFFLOAD_ABORTED = 2, 5120 }; 5121 5122 /** 5123 * struct iwm_lmac_scan_complete_notif - notifies end of scanning (all channels) 5124 * SCAN_COMPLETE_NTF_API_S_VER_3 5125 * @scanned_channels: number of channels scanned (and number of valid results) 5126 * @status: one of SCAN_COMP_STATUS_* 5127 * @bt_status: BT on/off status 5128 * @last_channel: last channel that was scanned 5129 * @tsf_low: TSF timer (lower half) in usecs 5130 * @tsf_high: TSF timer (higher half) in usecs 5131 * @results: an array of scan results, only "scanned_channels" of them are valid 5132 */ 5133 struct iwm_lmac_scan_complete_notif { 5134 uint8_t scanned_channels; 5135 uint8_t status; 5136 uint8_t bt_status; 5137 uint8_t last_channel; 5138 uint32_t tsf_low; 5139 uint32_t tsf_high; 5140 struct iwm_scan_results_notif results[]; 5141 } __packed; 5142 5143 5144 /* 5145 * END mvm/fw-api-scan.h 5146 */ 5147 5148 /* 5149 * BEGIN mvm/fw-api-sta.h 5150 */ 5151 5152 /* UMAC Scan API */ 5153 5154 /* The maximum of either of these cannot exceed 8, because we use an 5155 * 8-bit mask (see IWM_MVM_SCAN_MASK). 5156 */ 5157 #define IWM_MVM_MAX_UMAC_SCANS 8 5158 #define IWM_MVM_MAX_LMAC_SCANS 1 5159 5160 enum iwm_scan_config_flags { 5161 IWM_SCAN_CONFIG_FLAG_ACTIVATE = (1 << 0), 5162 IWM_SCAN_CONFIG_FLAG_DEACTIVATE = (1 << 1), 5163 IWM_SCAN_CONFIG_FLAG_FORBID_CHUB_REQS = (1 << 2), 5164 IWM_SCAN_CONFIG_FLAG_ALLOW_CHUB_REQS = (1 << 3), 5165 IWM_SCAN_CONFIG_FLAG_SET_TX_CHAINS = (1 << 8), 5166 IWM_SCAN_CONFIG_FLAG_SET_RX_CHAINS = (1 << 9), 5167 IWM_SCAN_CONFIG_FLAG_SET_AUX_STA_ID = (1 << 10), 5168 IWM_SCAN_CONFIG_FLAG_SET_ALL_TIMES = (1 << 11), 5169 IWM_SCAN_CONFIG_FLAG_SET_EFFECTIVE_TIMES = (1 << 12), 5170 IWM_SCAN_CONFIG_FLAG_SET_CHANNEL_FLAGS = (1 << 13), 5171 IWM_SCAN_CONFIG_FLAG_SET_LEGACY_RATES = (1 << 14), 5172 IWM_SCAN_CONFIG_FLAG_SET_MAC_ADDR = (1 << 15), 5173 IWM_SCAN_CONFIG_FLAG_SET_FRAGMENTED = (1 << 16), 5174 IWM_SCAN_CONFIG_FLAG_CLEAR_FRAGMENTED = (1 << 17), 5175 IWM_SCAN_CONFIG_FLAG_SET_CAM_MODE = (1 << 18), 5176 IWM_SCAN_CONFIG_FLAG_CLEAR_CAM_MODE = (1 << 19), 5177 IWM_SCAN_CONFIG_FLAG_SET_PROMISC_MODE = (1 << 20), 5178 IWM_SCAN_CONFIG_FLAG_CLEAR_PROMISC_MODE = (1 << 21), 5179 5180 /* Bits 26-31 are for num of channels in channel_array */ 5181 #define IWM_SCAN_CONFIG_N_CHANNELS(n) ((n) << 26) 5182 }; 5183 5184 enum iwm_scan_config_rates { 5185 /* OFDM basic rates */ 5186 IWM_SCAN_CONFIG_RATE_6M = (1 << 0), 5187 IWM_SCAN_CONFIG_RATE_9M = (1 << 1), 5188 IWM_SCAN_CONFIG_RATE_12M = (1 << 2), 5189 IWM_SCAN_CONFIG_RATE_18M = (1 << 3), 5190 IWM_SCAN_CONFIG_RATE_24M = (1 << 4), 5191 IWM_SCAN_CONFIG_RATE_36M = (1 << 5), 5192 IWM_SCAN_CONFIG_RATE_48M = (1 << 6), 5193 IWM_SCAN_CONFIG_RATE_54M = (1 << 7), 5194 /* CCK basic rates */ 5195 IWM_SCAN_CONFIG_RATE_1M = (1 << 8), 5196 IWM_SCAN_CONFIG_RATE_2M = (1 << 9), 5197 IWM_SCAN_CONFIG_RATE_5M = (1 << 10), 5198 IWM_SCAN_CONFIG_RATE_11M = (1 << 11), 5199 5200 /* Bits 16-27 are for supported rates */ 5201 #define IWM_SCAN_CONFIG_SUPPORTED_RATE(rate) ((rate) << 16) 5202 }; 5203 5204 enum iwm_channel_flags { 5205 IWM_CHANNEL_FLAG_EBS = (1 << 0), 5206 IWM_CHANNEL_FLAG_ACCURATE_EBS = (1 << 1), 5207 IWM_CHANNEL_FLAG_EBS_ADD = (1 << 2), 5208 IWM_CHANNEL_FLAG_PRE_SCAN_PASSIVE2ACTIVE = (1 << 3), 5209 }; 5210 5211 /** 5212 * struct iwm_scan_config 5213 * @flags: enum scan_config_flags 5214 * @tx_chains: valid_tx antenna - ANT_* definitions 5215 * @rx_chains: valid_rx antenna - ANT_* definitions 5216 * @legacy_rates: default legacy rates - enum scan_config_rates 5217 * @out_of_channel_time: default max out of serving channel time 5218 * @suspend_time: default max suspend time 5219 * @dwell_active: default dwell time for active scan 5220 * @dwell_passive: default dwell time for passive scan 5221 * @dwell_fragmented: default dwell time for fragmented scan 5222 * @dwell_extended: default dwell time for channels 1, 6 and 11 5223 * @mac_addr: default mac address to be used in probes 5224 * @bcast_sta_id: the index of the station in the fw 5225 * @channel_flags: default channel flags - enum iwm_channel_flags 5226 * scan_config_channel_flag 5227 * @channel_array: default supported channels 5228 */ 5229 struct iwm_scan_config { 5230 uint32_t flags; 5231 uint32_t tx_chains; 5232 uint32_t rx_chains; 5233 uint32_t legacy_rates; 5234 uint32_t out_of_channel_time; 5235 uint32_t suspend_time; 5236 uint8_t dwell_active; 5237 uint8_t dwell_passive; 5238 uint8_t dwell_fragmented; 5239 uint8_t dwell_extended; 5240 uint8_t mac_addr[IEEE80211_ADDR_LEN]; 5241 uint8_t bcast_sta_id; 5242 uint8_t channel_flags; 5243 uint8_t channel_array[]; 5244 } __packed; /* SCAN_CONFIG_DB_CMD_API_S */ 5245 5246 /** 5247 * iwm_umac_scan_flags 5248 *@IWM_UMAC_SCAN_FLAG_PREEMPTIVE: scan process triggered by this scan request 5249 * can be preempted by other scan requests with higher priority. 5250 * The low priority scan will be resumed when the higher proirity scan is 5251 * completed. 5252 *@IWM_UMAC_SCAN_FLAG_START_NOTIF: notification will be sent to the driver 5253 * when scan starts. 5254 */ 5255 enum iwm_umac_scan_flags { 5256 IWM_UMAC_SCAN_FLAG_PREEMPTIVE = (1 << 0), 5257 IWM_UMAC_SCAN_FLAG_START_NOTIF = (1 << 1), 5258 }; 5259 5260 enum iwm_umac_scan_uid_offsets { 5261 IWM_UMAC_SCAN_UID_TYPE_OFFSET = 0, 5262 IWM_UMAC_SCAN_UID_SEQ_OFFSET = 8, 5263 }; 5264 5265 enum iwm_umac_scan_general_flags { 5266 IWM_UMAC_SCAN_GEN_FLAGS_PERIODIC = (1 << 0), 5267 IWM_UMAC_SCAN_GEN_FLAGS_OVER_BT = (1 << 1), 5268 IWM_UMAC_SCAN_GEN_FLAGS_PASS_ALL = (1 << 2), 5269 IWM_UMAC_SCAN_GEN_FLAGS_PASSIVE = (1 << 3), 5270 IWM_UMAC_SCAN_GEN_FLAGS_PRE_CONNECT = (1 << 4), 5271 IWM_UMAC_SCAN_GEN_FLAGS_ITER_COMPLETE = (1 << 5), 5272 IWM_UMAC_SCAN_GEN_FLAGS_MULTIPLE_SSID = (1 << 6), 5273 IWM_UMAC_SCAN_GEN_FLAGS_FRAGMENTED = (1 << 7), 5274 IWM_UMAC_SCAN_GEN_FLAGS_RRM_ENABLED = (1 << 8), 5275 IWM_UMAC_SCAN_GEN_FLAGS_MATCH = (1 << 9), 5276 IWM_UMAC_SCAN_GEN_FLAGS_EXTENDED_DWELL = (1 << 10), 5277 }; 5278 5279 /** 5280 * struct iwm_scan_channel_cfg_umac 5281 * @flags: bitmap - 0-19: directed scan to i'th ssid. 5282 * @channel_num: channel number 1-13 etc. 5283 * @iter_count: repetition count for the channel. 5284 * @iter_interval: interval between two scan iterations on one channel. 5285 */ 5286 struct iwm_scan_channel_cfg_umac { 5287 uint32_t flags; 5288 #define IWM_SCAN_CHANNEL_UMAC_NSSIDS(x) ((1 << (x)) - 1) 5289 5290 uint8_t channel_num; 5291 uint8_t iter_count; 5292 uint16_t iter_interval; 5293 } __packed; /* SCAN_CHANNEL_CFG_S_VER2 */ 5294 5295 /** 5296 * struct iwm_scan_umac_schedule 5297 * @interval: interval in seconds between scan iterations 5298 * @iter_count: num of scan iterations for schedule plan, 0xff for infinite loop 5299 * @reserved: for alignment and future use 5300 */ 5301 struct iwm_scan_umac_schedule { 5302 uint16_t interval; 5303 uint8_t iter_count; 5304 uint8_t reserved; 5305 } __packed; /* SCAN_SCHED_PARAM_API_S_VER_1 */ 5306 5307 /** 5308 * struct iwm_scan_req_umac_tail - the rest of the UMAC scan request command 5309 * parameters following channels configuration array. 5310 * @schedule: two scheduling plans. 5311 * @delay: delay in TUs before starting the first scan iteration 5312 * @reserved: for future use and alignment 5313 * @preq: probe request with IEs blocks 5314 * @direct_scan: list of SSIDs for directed active scan 5315 */ 5316 struct iwm_scan_req_umac_tail { 5317 /* SCAN_PERIODIC_PARAMS_API_S_VER_1 */ 5318 struct iwm_scan_umac_schedule schedule[IWM_MAX_SCHED_SCAN_PLANS]; 5319 uint16_t delay; 5320 uint16_t reserved; 5321 /* SCAN_PROBE_PARAMS_API_S_VER_1 */ 5322 struct iwm_scan_probe_req preq; 5323 struct iwm_ssid_ie direct_scan[IWM_PROBE_OPTION_MAX]; 5324 } __packed; 5325 5326 /** 5327 * struct iwm_scan_req_umac 5328 * @flags: &enum iwm_umac_scan_flags 5329 * @uid: scan id, &enum iwm_umac_scan_uid_offsets 5330 * @ooc_priority: out of channel priority - &enum iwm_scan_priority 5331 * @general_flags: &enum iwm_umac_scan_general_flags 5332 * @extended_dwell: dwell time for channels 1, 6 and 11 5333 * @active_dwell: dwell time for active scan 5334 * @passive_dwell: dwell time for passive scan 5335 * @fragmented_dwell: dwell time for fragmented passive scan 5336 * @max_out_time: max out of serving channel time 5337 * @suspend_time: max suspend time 5338 * @scan_priority: scan internal prioritization &enum iwm_scan_priority 5339 * @channel_flags: &enum iwm_scan_channel_flags 5340 * @n_channels: num of channels in scan request 5341 * @reserved: for future use and alignment 5342 * @data: &struct iwm_scan_channel_cfg_umac and 5343 * &struct iwm_scan_req_umac_tail 5344 */ 5345 struct iwm_scan_req_umac { 5346 uint32_t flags; 5347 uint32_t uid; 5348 uint32_t ooc_priority; 5349 /* SCAN_GENERAL_PARAMS_API_S_VER_1 */ 5350 uint32_t general_flags; 5351 uint8_t extended_dwell; 5352 uint8_t active_dwell; 5353 uint8_t passive_dwell; 5354 uint8_t fragmented_dwell; 5355 uint32_t max_out_time; 5356 uint32_t suspend_time; 5357 uint32_t scan_priority; 5358 /* SCAN_CHANNEL_PARAMS_API_S_VER_1 */ 5359 uint8_t channel_flags; 5360 uint8_t n_channels; 5361 uint16_t reserved; 5362 uint8_t data[]; 5363 } __packed; /* SCAN_REQUEST_CMD_UMAC_API_S_VER_1 */ 5364 5365 /** 5366 * struct iwm_umac_scan_abort 5367 * @uid: scan id, &enum iwm_umac_scan_uid_offsets 5368 * @flags: reserved 5369 */ 5370 struct iwm_umac_scan_abort { 5371 uint32_t uid; 5372 uint32_t flags; 5373 } __packed; /* SCAN_ABORT_CMD_UMAC_API_S_VER_1 */ 5374 5375 /** 5376 * struct iwm_umac_scan_complete 5377 * @uid: scan id, &enum iwm_umac_scan_uid_offsets 5378 * @last_schedule: last scheduling line 5379 * @last_iter: last scan iteration number 5380 * @scan status: &enum iwm_scan_offload_complete_status 5381 * @ebs_status: &enum iwm_scan_ebs_status 5382 * @time_from_last_iter: time elapsed from last iteration 5383 * @reserved: for future use 5384 */ 5385 struct iwm_umac_scan_complete { 5386 uint32_t uid; 5387 uint8_t last_schedule; 5388 uint8_t last_iter; 5389 uint8_t status; 5390 uint8_t ebs_status; 5391 uint32_t time_from_last_iter; 5392 uint32_t reserved; 5393 } __packed; /* SCAN_COMPLETE_NTF_UMAC_API_S_VER_1 */ 5394 5395 #define IWM_SCAN_OFFLOAD_MATCHING_CHANNELS_LEN 5 5396 /** 5397 * struct iwm_scan_offload_profile_match - match information 5398 * @bssid: matched bssid 5399 * @channel: channel where the match occurred 5400 * @energy: 5401 * @matching_feature: 5402 * @matching_channels: bitmap of channels that matched, referencing 5403 * the channels passed in tue scan offload request 5404 */ 5405 struct iwm_scan_offload_profile_match { 5406 uint8_t bssid[IEEE80211_ADDR_LEN]; 5407 uint16_t reserved; 5408 uint8_t channel; 5409 uint8_t energy; 5410 uint8_t matching_feature; 5411 uint8_t matching_channels[IWM_SCAN_OFFLOAD_MATCHING_CHANNELS_LEN]; 5412 } __packed; /* SCAN_OFFLOAD_PROFILE_MATCH_RESULTS_S_VER_1 */ 5413 5414 /** 5415 * struct iwm_scan_offload_profiles_query - match results query response 5416 * @matched_profiles: bitmap of matched profiles, referencing the 5417 * matches passed in the scan offload request 5418 * @last_scan_age: age of the last offloaded scan 5419 * @n_scans_done: number of offloaded scans done 5420 * @gp2_d0u: GP2 when D0U occurred 5421 * @gp2_invoked: GP2 when scan offload was invoked 5422 * @resume_while_scanning: not used 5423 * @self_recovery: obsolete 5424 * @reserved: reserved 5425 * @matches: array of match information, one for each match 5426 */ 5427 struct iwm_scan_offload_profiles_query { 5428 uint32_t matched_profiles; 5429 uint32_t last_scan_age; 5430 uint32_t n_scans_done; 5431 uint32_t gp2_d0u; 5432 uint32_t gp2_invoked; 5433 uint8_t resume_while_scanning; 5434 uint8_t self_recovery; 5435 uint16_t reserved; 5436 struct iwm_scan_offload_profile_match matches[IWM_SCAN_MAX_PROFILES]; 5437 } __packed; /* SCAN_OFFLOAD_PROFILES_QUERY_RSP_S_VER_2 */ 5438 5439 /** 5440 * struct iwm_umac_scan_iter_complete_notif - notifies end of scanning iteration 5441 * @uid: scan id, &enum iwm_umac_scan_uid_offsets 5442 * @scanned_channels: number of channels scanned and number of valid elements in 5443 * results array 5444 * @status: one of SCAN_COMP_STATUS_* 5445 * @bt_status: BT on/off status 5446 * @last_channel: last channel that was scanned 5447 * @tsf_low: TSF timer (lower half) in usecs 5448 * @tsf_high: TSF timer (higher half) in usecs 5449 * @results: array of scan results, only "scanned_channels" of them are valid 5450 */ 5451 struct iwm_umac_scan_iter_complete_notif { 5452 uint32_t uid; 5453 uint8_t scanned_channels; 5454 uint8_t status; 5455 uint8_t bt_status; 5456 uint8_t last_channel; 5457 uint32_t tsf_low; 5458 uint32_t tsf_high; 5459 struct iwm_scan_results_notif results[]; 5460 } __packed; /* SCAN_ITER_COMPLETE_NTF_UMAC_API_S_VER_1 */ 5461 5462 /* Please keep this enum *SORTED* by hex value. 5463 * Needed for binary search, otherwise a warning will be triggered. 5464 */ 5465 enum iwm_scan_subcmd_ids { 5466 IWM_GSCAN_START_CMD = 0x0, 5467 IWM_GSCAN_STOP_CMD = 0x1, 5468 IWM_GSCAN_SET_HOTLIST_CMD = 0x2, 5469 IWM_GSCAN_RESET_HOTLIST_CMD = 0x3, 5470 IWM_GSCAN_SET_SIGNIFICANT_CHANGE_CMD = 0x4, 5471 IWM_GSCAN_RESET_SIGNIFICANT_CHANGE_CMD = 0x5, 5472 IWM_GSCAN_SIGNIFICANT_CHANGE_EVENT = 0xFD, 5473 IWM_GSCAN_HOTLIST_CHANGE_EVENT = 0xFE, 5474 IWM_GSCAN_RESULTS_AVAILABLE_EVENT = 0xFF, 5475 }; 5476 5477 /* STA API */ 5478 5479 /** 5480 * enum iwm_sta_flags - flags for the ADD_STA host command 5481 * @IWM_STA_FLG_REDUCED_TX_PWR_CTRL: 5482 * @IWM_STA_FLG_REDUCED_TX_PWR_DATA: 5483 * @IWM_STA_FLG_DISABLE_TX: set if TX should be disabled 5484 * @IWM_STA_FLG_PS: set if STA is in Power Save 5485 * @IWM_STA_FLG_INVALID: set if STA is invalid 5486 * @IWM_STA_FLG_DLP_EN: Direct Link Protocol is enabled 5487 * @IWM_STA_FLG_SET_ALL_KEYS: the current key applies to all key IDs 5488 * @IWM_STA_FLG_DRAIN_FLOW: drain flow 5489 * @IWM_STA_FLG_PAN: STA is for PAN interface 5490 * @IWM_STA_FLG_CLASS_AUTH: 5491 * @IWM_STA_FLG_CLASS_ASSOC: 5492 * @IWM_STA_FLG_CLASS_MIMO_PROT: 5493 * @IWM_STA_FLG_MAX_AGG_SIZE_MSK: maximal size for A-MPDU 5494 * @IWM_STA_FLG_AGG_MPDU_DENS_MSK: maximal MPDU density for Tx aggregation 5495 * @IWM_STA_FLG_FAT_EN_MSK: support for channel width (for Tx). This flag is 5496 * initialised by driver and can be updated by fw upon reception of 5497 * action frames that can change the channel width. When cleared the fw 5498 * will send all the frames in 20MHz even when FAT channel is requested. 5499 * @IWM_STA_FLG_MIMO_EN_MSK: support for MIMO. This flag is initialised by the 5500 * driver and can be updated by fw upon reception of action frames. 5501 * @IWM_STA_FLG_MFP_EN: Management Frame Protection 5502 */ 5503 enum iwm_sta_flags { 5504 IWM_STA_FLG_REDUCED_TX_PWR_CTRL = (1 << 3), 5505 IWM_STA_FLG_REDUCED_TX_PWR_DATA = (1 << 6), 5506 5507 IWM_STA_FLG_DISABLE_TX = (1 << 4), 5508 5509 IWM_STA_FLG_PS = (1 << 8), 5510 IWM_STA_FLG_DRAIN_FLOW = (1 << 12), 5511 IWM_STA_FLG_PAN = (1 << 13), 5512 IWM_STA_FLG_CLASS_AUTH = (1 << 14), 5513 IWM_STA_FLG_CLASS_ASSOC = (1 << 15), 5514 IWM_STA_FLG_RTS_MIMO_PROT = (1 << 17), 5515 5516 IWM_STA_FLG_MAX_AGG_SIZE_SHIFT = 19, 5517 IWM_STA_FLG_MAX_AGG_SIZE_8K = (0 << IWM_STA_FLG_MAX_AGG_SIZE_SHIFT), 5518 IWM_STA_FLG_MAX_AGG_SIZE_16K = (1 << IWM_STA_FLG_MAX_AGG_SIZE_SHIFT), 5519 IWM_STA_FLG_MAX_AGG_SIZE_32K = (2 << IWM_STA_FLG_MAX_AGG_SIZE_SHIFT), 5520 IWM_STA_FLG_MAX_AGG_SIZE_64K = (3 << IWM_STA_FLG_MAX_AGG_SIZE_SHIFT), 5521 IWM_STA_FLG_MAX_AGG_SIZE_128K = (4 << IWM_STA_FLG_MAX_AGG_SIZE_SHIFT), 5522 IWM_STA_FLG_MAX_AGG_SIZE_256K = (5 << IWM_STA_FLG_MAX_AGG_SIZE_SHIFT), 5523 IWM_STA_FLG_MAX_AGG_SIZE_512K = (6 << IWM_STA_FLG_MAX_AGG_SIZE_SHIFT), 5524 IWM_STA_FLG_MAX_AGG_SIZE_1024K = (7 << IWM_STA_FLG_MAX_AGG_SIZE_SHIFT), 5525 IWM_STA_FLG_MAX_AGG_SIZE_MSK = (7 << IWM_STA_FLG_MAX_AGG_SIZE_SHIFT), 5526 5527 IWM_STA_FLG_AGG_MPDU_DENS_SHIFT = 23, 5528 IWM_STA_FLG_AGG_MPDU_DENS_2US = (4 << IWM_STA_FLG_AGG_MPDU_DENS_SHIFT), 5529 IWM_STA_FLG_AGG_MPDU_DENS_4US = (5 << IWM_STA_FLG_AGG_MPDU_DENS_SHIFT), 5530 IWM_STA_FLG_AGG_MPDU_DENS_8US = (6 << IWM_STA_FLG_AGG_MPDU_DENS_SHIFT), 5531 IWM_STA_FLG_AGG_MPDU_DENS_16US = (7 << IWM_STA_FLG_AGG_MPDU_DENS_SHIFT), 5532 IWM_STA_FLG_AGG_MPDU_DENS_MSK = (7 << IWM_STA_FLG_AGG_MPDU_DENS_SHIFT), 5533 5534 IWM_STA_FLG_FAT_EN_20MHZ = (0 << 26), 5535 IWM_STA_FLG_FAT_EN_40MHZ = (1 << 26), 5536 IWM_STA_FLG_FAT_EN_80MHZ = (2 << 26), 5537 IWM_STA_FLG_FAT_EN_160MHZ = (3 << 26), 5538 IWM_STA_FLG_FAT_EN_MSK = (3 << 26), 5539 5540 IWM_STA_FLG_MIMO_EN_SISO = (0 << 28), 5541 IWM_STA_FLG_MIMO_EN_MIMO2 = (1 << 28), 5542 IWM_STA_FLG_MIMO_EN_MIMO3 = (2 << 28), 5543 IWM_STA_FLG_MIMO_EN_MSK = (3 << 28), 5544 }; 5545 5546 /** 5547 * enum iwm_sta_key_flag - key flags for the ADD_STA host command 5548 * @IWM_STA_KEY_FLG_NO_ENC: no encryption 5549 * @IWM_STA_KEY_FLG_WEP: WEP encryption algorithm 5550 * @IWM_STA_KEY_FLG_CCM: CCMP encryption algorithm 5551 * @IWM_STA_KEY_FLG_TKIP: TKIP encryption algorithm 5552 * @IWM_STA_KEY_FLG_EXT: extended cipher algorithm (depends on the FW support) 5553 * @IWM_STA_KEY_FLG_CMAC: CMAC encryption algorithm 5554 * @IWM_STA_KEY_FLG_ENC_UNKNOWN: unknown encryption algorithm 5555 * @IWM_STA_KEY_FLG_EN_MSK: mask for encryption algorithmi value 5556 * @IWM_STA_KEY_FLG_WEP_KEY_MAP: wep is either a group key (0 - legacy WEP) or from 5557 * station info array (1 - n 1X mode) 5558 * @IWM_STA_KEY_FLG_KEYID_MSK: the index of the key 5559 * @IWM_STA_KEY_NOT_VALID: key is invalid 5560 * @IWM_STA_KEY_FLG_WEP_13BYTES: set for 13 bytes WEP key 5561 * @IWM_STA_KEY_MULTICAST: set for multical key 5562 * @IWM_STA_KEY_MFP: key is used for Management Frame Protection 5563 */ 5564 enum iwm_sta_key_flag { 5565 IWM_STA_KEY_FLG_NO_ENC = (0 << 0), 5566 IWM_STA_KEY_FLG_WEP = (1 << 0), 5567 IWM_STA_KEY_FLG_CCM = (2 << 0), 5568 IWM_STA_KEY_FLG_TKIP = (3 << 0), 5569 IWM_STA_KEY_FLG_EXT = (4 << 0), 5570 IWM_STA_KEY_FLG_CMAC = (6 << 0), 5571 IWM_STA_KEY_FLG_ENC_UNKNOWN = (7 << 0), 5572 IWM_STA_KEY_FLG_EN_MSK = (7 << 0), 5573 5574 IWM_STA_KEY_FLG_WEP_KEY_MAP = (1 << 3), 5575 IWM_STA_KEY_FLG_KEYID_POS = 8, 5576 IWM_STA_KEY_FLG_KEYID_MSK = (3 << IWM_STA_KEY_FLG_KEYID_POS), 5577 IWM_STA_KEY_NOT_VALID = (1 << 11), 5578 IWM_STA_KEY_FLG_WEP_13BYTES = (1 << 12), 5579 IWM_STA_KEY_MULTICAST = (1 << 14), 5580 IWM_STA_KEY_MFP = (1 << 15), 5581 }; 5582 5583 /** 5584 * enum iwm_sta_modify_flag - indicate to the fw what flag are being changed 5585 * @IWM_STA_MODIFY_QUEUE_REMOVAL: this command removes a queue 5586 * @IWM_STA_MODIFY_TID_DISABLE_TX: this command modifies %tid_disable_tx 5587 * @IWM_STA_MODIFY_TX_RATE: unused 5588 * @IWM_STA_MODIFY_ADD_BA_TID: this command modifies %add_immediate_ba_tid 5589 * @IWM_STA_MODIFY_REMOVE_BA_TID: this command modifies %remove_immediate_ba_tid 5590 * @IWM_STA_MODIFY_SLEEPING_STA_TX_COUNT: this command modifies %sleep_tx_count 5591 * @IWM_STA_MODIFY_PROT_TH: 5592 * @IWM_STA_MODIFY_QUEUES: modify the queues used by this station 5593 */ 5594 enum iwm_sta_modify_flag { 5595 IWM_STA_MODIFY_QUEUE_REMOVAL = (1 << 0), 5596 IWM_STA_MODIFY_TID_DISABLE_TX = (1 << 1), 5597 IWM_STA_MODIFY_TX_RATE = (1 << 2), 5598 IWM_STA_MODIFY_ADD_BA_TID = (1 << 3), 5599 IWM_STA_MODIFY_REMOVE_BA_TID = (1 << 4), 5600 IWM_STA_MODIFY_SLEEPING_STA_TX_COUNT = (1 << 5), 5601 IWM_STA_MODIFY_PROT_TH = (1 << 6), 5602 IWM_STA_MODIFY_QUEUES = (1 << 7), 5603 }; 5604 5605 #define IWM_STA_MODE_MODIFY 1 5606 5607 /** 5608 * enum iwm_sta_sleep_flag - type of sleep of the station 5609 * @IWM_STA_SLEEP_STATE_AWAKE: 5610 * @IWM_STA_SLEEP_STATE_PS_POLL: 5611 * @IWM_STA_SLEEP_STATE_UAPSD: 5612 * @IWM_STA_SLEEP_STATE_MOREDATA: set more-data bit on 5613 * (last) released frame 5614 */ 5615 enum iwm_sta_sleep_flag { 5616 IWM_STA_SLEEP_STATE_AWAKE = 0, 5617 IWM_STA_SLEEP_STATE_PS_POLL = (1 << 0), 5618 IWM_STA_SLEEP_STATE_UAPSD = (1 << 1), 5619 IWM_STA_SLEEP_STATE_MOREDATA = (1 << 2), 5620 }; 5621 5622 /* STA ID and color bits definitions */ 5623 #define IWM_STA_ID_SEED (0x0f) 5624 #define IWM_STA_ID_POS (0) 5625 #define IWM_STA_ID_MSK (IWM_STA_ID_SEED << IWM_STA_ID_POS) 5626 5627 #define IWM_STA_COLOR_SEED (0x7) 5628 #define IWM_STA_COLOR_POS (4) 5629 #define IWM_STA_COLOR_MSK (IWM_STA_COLOR_SEED << IWM_STA_COLOR_POS) 5630 5631 #define IWM_STA_ID_N_COLOR_GET_COLOR(id_n_color) \ 5632 (((id_n_color) & IWM_STA_COLOR_MSK) >> IWM_STA_COLOR_POS) 5633 #define IWM_STA_ID_N_COLOR_GET_ID(id_n_color) \ 5634 (((id_n_color) & IWM_STA_ID_MSK) >> IWM_STA_ID_POS) 5635 5636 #define IWM_STA_KEY_MAX_NUM (16) 5637 #define IWM_STA_KEY_IDX_INVALID (0xff) 5638 #define IWM_STA_KEY_MAX_DATA_KEY_NUM (4) 5639 #define IWM_MAX_GLOBAL_KEYS (4) 5640 #define IWM_STA_KEY_LEN_WEP40 (5) 5641 #define IWM_STA_KEY_LEN_WEP104 (13) 5642 5643 /** 5644 * struct iwm_mvm_keyinfo - key information 5645 * @key_flags: type %iwm_sta_key_flag 5646 * @tkip_rx_tsc_byte2: TSC[2] for key mix ph1 detection 5647 * @tkip_rx_ttak: 10-byte unicast TKIP TTAK for Rx 5648 * @key_offset: key offset in the fw's key table 5649 * @key: 16-byte unicast decryption key 5650 * @tx_secur_seq_cnt: initial RSC / PN needed for replay check 5651 * @hw_tkip_mic_rx_key: byte: MIC Rx Key - used for TKIP only 5652 * @hw_tkip_mic_tx_key: byte: MIC Tx Key - used for TKIP only 5653 */ 5654 struct iwm_mvm_keyinfo { 5655 uint16_t key_flags; 5656 uint8_t tkip_rx_tsc_byte2; 5657 uint8_t reserved1; 5658 uint16_t tkip_rx_ttak[5]; 5659 uint8_t key_offset; 5660 uint8_t reserved2; 5661 uint8_t key[16]; 5662 uint64_t tx_secur_seq_cnt; 5663 uint64_t hw_tkip_mic_rx_key; 5664 uint64_t hw_tkip_mic_tx_key; 5665 } __packed; 5666 5667 #define IWM_ADD_STA_STATUS_MASK 0xFF 5668 #define IWM_ADD_STA_BAID_VALID_MASK 0x8000 5669 #define IWM_ADD_STA_BAID_MASK 0x7F00 5670 #define IWM_ADD_STA_BAID_SHIFT 8 5671 5672 /** 5673 * struct iwm_mvm_add_sta_cmd_v7 - Add/modify a station in the fw's sta table. 5674 * ( REPLY_ADD_STA = 0x18 ) 5675 * @add_modify: 1: modify existing, 0: add new station 5676 * @awake_acs: 5677 * @tid_disable_tx: is tid BIT(tid) enabled for Tx. Clear BIT(x) to enable 5678 * AMPDU for tid x. Set %IWM_STA_MODIFY_TID_DISABLE_TX to change this field. 5679 * @mac_id_n_color: the Mac context this station belongs to 5680 * @addr[IEEE80211_ADDR_LEN]: station's MAC address 5681 * @sta_id: index of station in uCode's station table 5682 * @modify_mask: IWM_STA_MODIFY_*, selects which parameters to modify vs. leave 5683 * alone. 1 - modify, 0 - don't change. 5684 * @station_flags: look at %iwm_sta_flags 5685 * @station_flags_msk: what of %station_flags have changed 5686 * @add_immediate_ba_tid: tid for which to add block-ack support (Rx) 5687 * Set %IWM_STA_MODIFY_ADD_BA_TID to use this field, and also set 5688 * add_immediate_ba_ssn. 5689 * @remove_immediate_ba_tid: tid for which to remove block-ack support (Rx) 5690 * Set %IWM_STA_MODIFY_REMOVE_BA_TID to use this field 5691 * @add_immediate_ba_ssn: ssn for the Rx block-ack session. Used together with 5692 * add_immediate_ba_tid. 5693 * @sleep_tx_count: number of packets to transmit to station even though it is 5694 * asleep. Used to synchronise PS-poll and u-APSD responses while ucode 5695 * keeps track of STA sleep state. 5696 * @sleep_state_flags: Look at %iwm_sta_sleep_flag. 5697 * @assoc_id: assoc_id to be sent in VHT PLCP (9-bit), for grp use 0, for AP 5698 * mac-addr. 5699 * @beamform_flags: beam forming controls 5700 * @tfd_queue_msk: tfd queues used by this station 5701 * 5702 * The device contains an internal table of per-station information, with info 5703 * on security keys, aggregation parameters, and Tx rates for initial Tx 5704 * attempt and any retries (set by IWM_REPLY_TX_LINK_QUALITY_CMD). 5705 * 5706 * ADD_STA sets up the table entry for one station, either creating a new 5707 * entry, or modifying a pre-existing one. 5708 */ 5709 struct iwm_mvm_add_sta_cmd_v7 { 5710 uint8_t add_modify; 5711 uint8_t awake_acs; 5712 uint16_t tid_disable_tx; 5713 uint32_t mac_id_n_color; 5714 uint8_t addr[IEEE80211_ADDR_LEN]; /* _STA_ID_MODIFY_INFO_API_S_VER_1 */ 5715 uint16_t reserved2; 5716 uint8_t sta_id; 5717 uint8_t modify_mask; 5718 uint16_t reserved3; 5719 uint32_t station_flags; 5720 uint32_t station_flags_msk; 5721 uint8_t add_immediate_ba_tid; 5722 uint8_t remove_immediate_ba_tid; 5723 uint16_t add_immediate_ba_ssn; 5724 uint16_t sleep_tx_count; 5725 uint16_t sleep_state_flags; 5726 uint16_t assoc_id; 5727 uint16_t beamform_flags; 5728 uint32_t tfd_queue_msk; 5729 } __packed; /* ADD_STA_CMD_API_S_VER_7 */ 5730 5731 /** 5732 * struct iwm_mvm_add_sta_key_cmd - add/modify sta key 5733 * ( IWM_REPLY_ADD_STA_KEY = 0x17 ) 5734 * @sta_id: index of station in uCode's station table 5735 * @key_offset: key offset in key storage 5736 * @key_flags: type %iwm_sta_key_flag 5737 * @key: key material data 5738 * @key2: key material data 5739 * @rx_secur_seq_cnt: RX security sequence counter for the key 5740 * @tkip_rx_tsc_byte2: TSC[2] for key mix ph1 detection 5741 * @tkip_rx_ttak: 10-byte unicast TKIP TTAK for Rx 5742 */ 5743 struct iwm_mvm_add_sta_key_cmd { 5744 uint8_t sta_id; 5745 uint8_t key_offset; 5746 uint16_t key_flags; 5747 uint8_t key[16]; 5748 uint8_t key2[16]; 5749 uint8_t rx_secur_seq_cnt[16]; 5750 uint8_t tkip_rx_tsc_byte2; 5751 uint8_t reserved; 5752 uint16_t tkip_rx_ttak[5]; 5753 } __packed; /* IWM_ADD_MODIFY_STA_KEY_API_S_VER_1 */ 5754 5755 /** 5756 * enum iwm_mvm_add_sta_rsp_status - status in the response to ADD_STA command 5757 * @IWM_ADD_STA_SUCCESS: operation was executed successfully 5758 * @IWM_ADD_STA_STATIONS_OVERLOAD: no room left in the fw's station table 5759 * @IWM_ADD_STA_IMMEDIATE_BA_FAILURE: can't add Rx block ack session 5760 * @IWM_ADD_STA_MODIFY_NON_EXISTING_STA: driver requested to modify a station 5761 * that doesn't exist. 5762 */ 5763 enum iwm_mvm_add_sta_rsp_status { 5764 IWM_ADD_STA_SUCCESS = 0x1, 5765 IWM_ADD_STA_STATIONS_OVERLOAD = 0x2, 5766 IWM_ADD_STA_IMMEDIATE_BA_FAILURE = 0x4, 5767 IWM_ADD_STA_MODIFY_NON_EXISTING_STA = 0x8, 5768 }; 5769 5770 /** 5771 * struct iwm_mvm_rm_sta_cmd - Add / modify a station in the fw's station table 5772 * ( IWM_REMOVE_STA = 0x19 ) 5773 * @sta_id: the station id of the station to be removed 5774 */ 5775 struct iwm_mvm_rm_sta_cmd { 5776 uint8_t sta_id; 5777 uint8_t reserved[3]; 5778 } __packed; /* IWM_REMOVE_STA_CMD_API_S_VER_2 */ 5779 5780 /** 5781 * struct iwm_mvm_mgmt_mcast_key_cmd 5782 * ( IWM_MGMT_MCAST_KEY = 0x1f ) 5783 * @ctrl_flags: %iwm_sta_key_flag 5784 * @IGTK: 5785 * @K1: IGTK master key 5786 * @K2: IGTK sub key 5787 * @sta_id: station ID that support IGTK 5788 * @key_id: 5789 * @receive_seq_cnt: initial RSC/PN needed for replay check 5790 */ 5791 struct iwm_mvm_mgmt_mcast_key_cmd { 5792 uint32_t ctrl_flags; 5793 uint8_t IGTK[16]; 5794 uint8_t K1[16]; 5795 uint8_t K2[16]; 5796 uint32_t key_id; 5797 uint32_t sta_id; 5798 uint64_t receive_seq_cnt; 5799 } __packed; /* SEC_MGMT_MULTICAST_KEY_CMD_API_S_VER_1 */ 5800 5801 struct iwm_mvm_wep_key { 5802 uint8_t key_index; 5803 uint8_t key_offset; 5804 uint16_t reserved1; 5805 uint8_t key_size; 5806 uint8_t reserved2[3]; 5807 uint8_t key[16]; 5808 } __packed; 5809 5810 struct iwm_mvm_wep_key_cmd { 5811 uint32_t mac_id_n_color; 5812 uint8_t num_keys; 5813 uint8_t decryption_type; 5814 uint8_t flags; 5815 uint8_t reserved; 5816 struct iwm_mvm_wep_key wep_key[0]; 5817 } __packed; /* SEC_CURR_WEP_KEY_CMD_API_S_VER_2 */ 5818 5819 /* 5820 * END mvm/fw-api-sta.h 5821 */ 5822 5823 /* 5824 * BT coex 5825 */ 5826 5827 enum iwm_bt_coex_mode { 5828 IWM_BT_COEX_DISABLE = 0x0, 5829 IWM_BT_COEX_NW = 0x1, 5830 IWM_BT_COEX_BT = 0x2, 5831 IWM_BT_COEX_WIFI = 0x3, 5832 }; /* BT_COEX_MODES_E */ 5833 5834 enum iwm_bt_coex_enabled_modules { 5835 IWM_BT_COEX_MPLUT_ENABLED = (1 << 0), 5836 IWM_BT_COEX_MPLUT_BOOST_ENABLED = (1 << 1), 5837 IWM_BT_COEX_SYNC2SCO_ENABLED = (1 << 2), 5838 IWM_BT_COEX_CORUN_ENABLED = (1 << 3), 5839 IWM_BT_COEX_HIGH_BAND_RET = (1 << 4), 5840 }; /* BT_COEX_MODULES_ENABLE_E_VER_1 */ 5841 5842 /** 5843 * struct iwm_bt_coex_cmd - bt coex configuration command 5844 * @mode: enum %iwm_bt_coex_mode 5845 * @enabled_modules: enum %iwm_bt_coex_enabled_modules 5846 * 5847 * The structure is used for the BT_COEX command. 5848 */ 5849 struct iwm_bt_coex_cmd { 5850 uint32_t mode; 5851 uint32_t enabled_modules; 5852 } __packed; /* BT_COEX_CMD_API_S_VER_6 */ 5853 5854 5855 /* 5856 * Location Aware Regulatory (LAR) API - MCC updates 5857 */ 5858 5859 /** 5860 * struct iwm_mcc_update_cmd_v1 - Request the device to update geographic 5861 * regulatory profile according to the given MCC (Mobile Country Code). 5862 * The MCC is two letter-code, ascii upper case[A-Z] or '00' for world domain. 5863 * 'ZZ' MCC will be used to switch to NVM default profile; in this case, the 5864 * MCC in the cmd response will be the relevant MCC in the NVM. 5865 * @mcc: given mobile country code 5866 * @source_id: the source from where we got the MCC, see iwm_mcc_source 5867 * @reserved: reserved for alignment 5868 */ 5869 struct iwm_mcc_update_cmd_v1 { 5870 uint16_t mcc; 5871 uint8_t source_id; 5872 uint8_t reserved; 5873 } __packed; /* LAR_UPDATE_MCC_CMD_API_S_VER_1 */ 5874 5875 /** 5876 * struct iwm_mcc_update_cmd - Request the device to update geographic 5877 * regulatory profile according to the given MCC (Mobile Country Code). 5878 * The MCC is two letter-code, ascii upper case[A-Z] or '00' for world domain. 5879 * 'ZZ' MCC will be used to switch to NVM default profile; in this case, the 5880 * MCC in the cmd response will be the relevant MCC in the NVM. 5881 * @mcc: given mobile country code 5882 * @source_id: the source from where we got the MCC, see iwm_mcc_source 5883 * @reserved: reserved for alignment 5884 * @key: integrity key for MCC API OEM testing 5885 * @reserved2: reserved 5886 */ 5887 struct iwm_mcc_update_cmd { 5888 uint16_t mcc; 5889 uint8_t source_id; 5890 uint8_t reserved; 5891 uint32_t key; 5892 uint32_t reserved2[5]; 5893 } __packed; /* LAR_UPDATE_MCC_CMD_API_S_VER_2 */ 5894 5895 /** 5896 * iwm_mcc_update_resp_v1 - response to MCC_UPDATE_CMD. 5897 * Contains the new channel control profile map, if changed, and the new MCC 5898 * (mobile country code). 5899 * The new MCC may be different than what was requested in MCC_UPDATE_CMD. 5900 * @status: see &enum iwm_mcc_update_status 5901 * @mcc: the new applied MCC 5902 * @cap: capabilities for all channels which matches the MCC 5903 * @source_id: the MCC source, see iwm_mcc_source 5904 * @n_channels: number of channels in @channels_data (may be 14, 39, 50 or 51 5905 * channels, depending on platform) 5906 * @channels: channel control data map, DWORD for each channel. Only the first 5907 * 16bits are used. 5908 */ 5909 struct iwm_mcc_update_resp_v1 { 5910 uint32_t status; 5911 uint16_t mcc; 5912 uint8_t cap; 5913 uint8_t source_id; 5914 uint32_t n_channels; 5915 uint32_t channels[0]; 5916 } __packed; /* LAR_UPDATE_MCC_CMD_RESP_S_VER_1 */ 5917 5918 /** 5919 * iwm_mcc_update_resp - response to MCC_UPDATE_CMD. 5920 * Contains the new channel control profile map, if changed, and the new MCC 5921 * (mobile country code). 5922 * The new MCC may be different than what was requested in MCC_UPDATE_CMD. 5923 * @status: see &enum iwm_mcc_update_status 5924 * @mcc: the new applied MCC 5925 * @cap: capabilities for all channels which matches the MCC 5926 * @source_id: the MCC source, see iwm_mcc_source 5927 * @time: time elapsed from the MCC test start (in 30 seconds TU) 5928 * @reserved: reserved. 5929 * @n_channels: number of channels in @channels_data (may be 14, 39, 50 or 51 5930 * channels, depending on platform) 5931 * @channels: channel control data map, DWORD for each channel. Only the first 5932 * 16bits are used. 5933 */ 5934 struct iwm_mcc_update_resp { 5935 uint32_t status; 5936 uint16_t mcc; 5937 uint8_t cap; 5938 uint8_t source_id; 5939 uint16_t time; 5940 uint16_t reserved; 5941 uint32_t n_channels; 5942 uint32_t channels[0]; 5943 } __packed; /* LAR_UPDATE_MCC_CMD_RESP_S_VER_2 */ 5944 5945 /** 5946 * struct iwm_mcc_chub_notif - chub notifies of mcc change 5947 * (MCC_CHUB_UPDATE_CMD = 0xc9) 5948 * The Chub (Communication Hub, CommsHUB) is a HW component that connects to 5949 * the cellular and connectivity cores that gets updates of the mcc, and 5950 * notifies the ucode directly of any mcc change. 5951 * The ucode requests the driver to request the device to update geographic 5952 * regulatory profile according to the given MCC (Mobile Country Code). 5953 * The MCC is two letter-code, ascii upper case[A-Z] or '00' for world domain. 5954 * 'ZZ' MCC will be used to switch to NVM default profile; in this case, the 5955 * MCC in the cmd response will be the relevant MCC in the NVM. 5956 * @mcc: given mobile country code 5957 * @source_id: identity of the change originator, see iwm_mcc_source 5958 * @reserved1: reserved for alignment 5959 */ 5960 struct iwm_mcc_chub_notif { 5961 uint16_t mcc; 5962 uint8_t source_id; 5963 uint8_t reserved1; 5964 } __packed; /* LAR_MCC_NOTIFY_S */ 5965 5966 enum iwm_mcc_update_status { 5967 IWM_MCC_RESP_NEW_CHAN_PROFILE, 5968 IWM_MCC_RESP_SAME_CHAN_PROFILE, 5969 IWM_MCC_RESP_INVALID, 5970 IWM_MCC_RESP_NVM_DISABLED, 5971 IWM_MCC_RESP_ILLEGAL, 5972 IWM_MCC_RESP_LOW_PRIORITY, 5973 IWM_MCC_RESP_TEST_MODE_ACTIVE, 5974 IWM_MCC_RESP_TEST_MODE_NOT_ACTIVE, 5975 IWM_MCC_RESP_TEST_MODE_DENIAL_OF_SERVICE, 5976 }; 5977 5978 enum iwm_mcc_source { 5979 IWM_MCC_SOURCE_OLD_FW = 0, 5980 IWM_MCC_SOURCE_ME = 1, 5981 IWM_MCC_SOURCE_BIOS = 2, 5982 IWM_MCC_SOURCE_3G_LTE_HOST = 3, 5983 IWM_MCC_SOURCE_3G_LTE_DEVICE = 4, 5984 IWM_MCC_SOURCE_WIFI = 5, 5985 IWM_MCC_SOURCE_RESERVED = 6, 5986 IWM_MCC_SOURCE_DEFAULT = 7, 5987 IWM_MCC_SOURCE_UNINITIALIZED = 8, 5988 IWM_MCC_SOURCE_MCC_API = 9, 5989 IWM_MCC_SOURCE_GET_CURRENT = 0x10, 5990 IWM_MCC_SOURCE_GETTING_MCC_TEST_MODE = 0x11, 5991 }; 5992 5993 /* 5994 * Some cherry-picked definitions 5995 */ 5996 5997 #define IWM_FRAME_LIMIT 64 5998 5999 /* 6000 * From Linux commit ab02165ccec4c78162501acedeef1a768acdb811: 6001 * As the firmware is slowly running out of command IDs and grouping of 6002 * commands is desirable anyway, the firmware is extending the command 6003 * header from 4 bytes to 8 bytes to introduce a group (in place of the 6004 * former flags field, since that's always 0 on commands and thus can 6005 * be easily used to distinguish between the two). 6006 * 6007 * These functions retrieve specific information from the id field in 6008 * the iwm_host_cmd struct which contains the command id, the group id, 6009 * and the version of the command. 6010 */ 6011 static inline uint8_t 6012 iwm_cmd_opcode(uint32_t cmdid) 6013 { 6014 return cmdid & 0xff; 6015 } 6016 6017 static inline uint8_t 6018 iwm_cmd_groupid(uint32_t cmdid) 6019 { 6020 return ((cmdid & 0Xff00) >> 8); 6021 } 6022 6023 static inline uint8_t 6024 iwm_cmd_version(uint32_t cmdid) 6025 { 6026 return ((cmdid & 0xff0000) >> 16); 6027 } 6028 6029 static inline uint32_t 6030 iwm_cmd_id(uint8_t opcode, uint8_t groupid, uint8_t version) 6031 { 6032 return opcode + (groupid << 8) + (version << 16); 6033 } 6034 6035 /* make uint16_t wide id out of uint8_t group and opcode */ 6036 #define IWM_WIDE_ID(grp, opcode) ((grp << 8) | opcode) 6037 6038 /* due to the conversion, this group is special */ 6039 #define IWM_ALWAYS_LONG_GROUP 1 6040 6041 struct iwm_cmd_header { 6042 uint8_t code; 6043 uint8_t flags; 6044 uint8_t idx; 6045 uint8_t qid; 6046 } __packed; 6047 6048 struct iwm_cmd_header_wide { 6049 uint8_t opcode; 6050 uint8_t group_id; 6051 uint8_t idx; 6052 uint8_t qid; 6053 uint16_t length; 6054 uint8_t reserved; 6055 uint8_t version; 6056 } __packed; 6057 6058 enum iwm_power_scheme { 6059 IWM_POWER_SCHEME_CAM = 1, 6060 IWM_POWER_SCHEME_BPS, 6061 IWM_POWER_SCHEME_LP 6062 }; 6063 6064 #define IWM_DEF_CMD_PAYLOAD_SIZE 320 6065 #define IWM_MAX_CMD_PAYLOAD_SIZE ((4096 - 4) - sizeof(struct iwm_cmd_header)) 6066 #define IWM_CMD_FAILED_MSK 0x40 6067 6068 /** 6069 * struct iwm_device_cmd 6070 * 6071 * For allocation of the command and tx queues, this establishes the overall 6072 * size of the largest command we send to uCode, except for commands that 6073 * aren't fully copied and use other TFD space. 6074 */ 6075 struct iwm_device_cmd { 6076 union { 6077 struct { 6078 struct iwm_cmd_header hdr; 6079 uint8_t data[IWM_DEF_CMD_PAYLOAD_SIZE]; 6080 }; 6081 struct { 6082 struct iwm_cmd_header_wide hdr_wide; 6083 uint8_t data_wide[IWM_DEF_CMD_PAYLOAD_SIZE - 6084 sizeof(struct iwm_cmd_header_wide) + 6085 sizeof(struct iwm_cmd_header)]; 6086 }; 6087 }; 6088 } __packed; 6089 6090 struct iwm_rx_packet { 6091 /* 6092 * The first 4 bytes of the RX frame header contain both the RX frame 6093 * size and some flags. 6094 * Bit fields: 6095 * 31: flag flush RB request 6096 * 30: flag ignore TC (terminal counter) request 6097 * 29: flag fast IRQ request 6098 * 28-14: Reserved 6099 * 13-00: RX frame size 6100 */ 6101 uint32_t len_n_flags; 6102 struct iwm_cmd_header hdr; 6103 uint8_t data[]; 6104 } __packed; 6105 6106 #define IWM_FH_RSCSR_FRAME_SIZE_MSK 0x00003fff 6107 6108 static inline uint32_t 6109 iwm_rx_packet_len(const struct iwm_rx_packet *pkt) 6110 { 6111 6112 return le32toh(pkt->len_n_flags) & IWM_FH_RSCSR_FRAME_SIZE_MSK; 6113 } 6114 6115 static inline uint32_t 6116 iwm_rx_packet_payload_len(const struct iwm_rx_packet *pkt) 6117 { 6118 6119 return iwm_rx_packet_len(pkt) - sizeof(pkt->hdr); 6120 } 6121 6122 6123 #define IWM_MIN_DBM -100 6124 #define IWM_MAX_DBM -33 /* realistic guess */ 6125 6126 #define IWM_READ(sc, reg) \ 6127 bus_space_read_4((sc)->sc_st, (sc)->sc_sh, (reg)) 6128 6129 #define IWM_WRITE(sc, reg, val) \ 6130 bus_space_write_4((sc)->sc_st, (sc)->sc_sh, (reg), (val)) 6131 6132 #define IWM_WRITE_1(sc, reg, val) \ 6133 bus_space_write_1((sc)->sc_st, (sc)->sc_sh, (reg), (val)) 6134 6135 #define IWM_SETBITS(sc, reg, mask) \ 6136 IWM_WRITE(sc, reg, IWM_READ(sc, reg) | (mask)) 6137 6138 #define IWM_CLRBITS(sc, reg, mask) \ 6139 IWM_WRITE(sc, reg, IWM_READ(sc, reg) & ~(mask)) 6140 6141 #define IWM_BARRIER_WRITE(sc) \ 6142 bus_space_barrier((sc)->sc_st, (sc)->sc_sh, 0, (sc)->sc_sz, \ 6143 BUS_SPACE_BARRIER_WRITE) 6144 6145 #define IWM_BARRIER_READ_WRITE(sc) \ 6146 bus_space_barrier((sc)->sc_st, (sc)->sc_sh, 0, (sc)->sc_sz, \ 6147 BUS_SPACE_BARRIER_READ | BUS_SPACE_BARRIER_WRITE) 6148 6149 #endif /* __IF_IWM_REG_H__ */ 6150