1 /* $OpenBSD: if_iwmreg.h,v 1.4 2015/06/15 08:06:11 stsp Exp $ */ 2 /* $FreeBSD$ */ 3 4 /****************************************************************************** 5 * 6 * This file is provided under a dual BSD/GPLv2 license. When using or 7 * redistributing this file, you may do so under either license. 8 * 9 * GPL LICENSE SUMMARY 10 * 11 * Copyright(c) 2005 - 2014 Intel Corporation. All rights reserved. 12 * 13 * This program is free software; you can redistribute it and/or modify 14 * it under the terms of version 2 of the GNU General Public License as 15 * published by the Free Software Foundation. 16 * 17 * This program is distributed in the hope that it will be useful, but 18 * WITHOUT ANY WARRANTY; without even the implied warranty of 19 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU 20 * General Public License for more details. 21 * 22 * You should have received a copy of the GNU General Public License 23 * along with this program; if not, write to the Free Software 24 * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110, 25 * USA 26 * 27 * The full GNU General Public License is included in this distribution 28 * in the file called COPYING. 29 * 30 * Contact Information: 31 * Intel Linux Wireless <ilw@linux.intel.com> 32 * Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497 33 * 34 * BSD LICENSE 35 * 36 * Copyright(c) 2005 - 2014 Intel Corporation. All rights reserved. 37 * All rights reserved. 38 * 39 * Redistribution and use in source and binary forms, with or without 40 * modification, are permitted provided that the following conditions 41 * are met: 42 * 43 * * Redistributions of source code must retain the above copyright 44 * notice, this list of conditions and the following disclaimer. 45 * * Redistributions in binary form must reproduce the above copyright 46 * notice, this list of conditions and the following disclaimer in 47 * the documentation and/or other materials provided with the 48 * distribution. 49 * * Neither the name Intel Corporation nor the names of its 50 * contributors may be used to endorse or promote products derived 51 * from this software without specific prior written permission. 52 * 53 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 54 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 55 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 56 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 57 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 58 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 59 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 60 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 61 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 62 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 63 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 64 * 65 *****************************************************************************/ 66 #ifndef __IF_IWM_REG_H__ 67 #define __IF_IWM_REG_H__ 68 69 #define le16_to_cpup(_a_) (le16toh(*(const uint16_t *)(_a_))) 70 #define le32_to_cpup(_a_) (le32toh(*(const uint32_t *)(_a_))) 71 72 /* 73 * BEGIN iwl-csr.h 74 */ 75 76 /* 77 * CSR (control and status registers) 78 * 79 * CSR registers are mapped directly into PCI bus space, and are accessible 80 * whenever platform supplies power to device, even when device is in 81 * low power states due to driver-invoked device resets 82 * (e.g. IWM_CSR_RESET_REG_FLAG_SW_RESET) or uCode-driven power-saving modes. 83 * 84 * Use iwl_write32() and iwl_read32() family to access these registers; 85 * these provide simple PCI bus access, without waking up the MAC. 86 * Do not use iwl_write_direct32() family for these registers; 87 * no need to "grab nic access" via IWM_CSR_GP_CNTRL_REG_FLAG_MAC_ACCESS_REQ. 88 * The MAC (uCode processor, etc.) does not need to be powered up for accessing 89 * the CSR registers. 90 * 91 * NOTE: Device does need to be awake in order to read this memory 92 * via IWM_CSR_EEPROM and IWM_CSR_OTP registers 93 */ 94 #define IWM_CSR_HW_IF_CONFIG_REG (0x000) /* hardware interface config */ 95 #define IWM_CSR_INT_COALESCING (0x004) /* accum ints, 32-usec units */ 96 #define IWM_CSR_INT (0x008) /* host interrupt status/ack */ 97 #define IWM_CSR_INT_MASK (0x00c) /* host interrupt enable */ 98 #define IWM_CSR_FH_INT_STATUS (0x010) /* busmaster int status/ack*/ 99 #define IWM_CSR_GPIO_IN (0x018) /* read external chip pins */ 100 #define IWM_CSR_RESET (0x020) /* busmaster enable, NMI, etc*/ 101 #define IWM_CSR_GP_CNTRL (0x024) 102 103 /* 2nd byte of IWM_CSR_INT_COALESCING, not accessible via iwl_write32()! */ 104 #define IWM_CSR_INT_PERIODIC_REG (0x005) 105 106 /* 107 * Hardware revision info 108 * Bit fields: 109 * 31-16: Reserved 110 * 15-4: Type of device: see IWM_CSR_HW_REV_TYPE_xxx definitions 111 * 3-2: Revision step: 0 = A, 1 = B, 2 = C, 3 = D 112 * 1-0: "Dash" (-) value, as in A-1, etc. 113 */ 114 #define IWM_CSR_HW_REV (0x028) 115 116 /* 117 * EEPROM and OTP (one-time-programmable) memory reads 118 * 119 * NOTE: Device must be awake, initialized via apm_ops.init(), 120 * in order to read. 121 */ 122 #define IWM_CSR_EEPROM_REG (0x02c) 123 #define IWM_CSR_EEPROM_GP (0x030) 124 #define IWM_CSR_OTP_GP_REG (0x034) 125 126 #define IWM_CSR_GIO_REG (0x03C) 127 #define IWM_CSR_GP_UCODE_REG (0x048) 128 #define IWM_CSR_GP_DRIVER_REG (0x050) 129 130 /* 131 * UCODE-DRIVER GP (general purpose) mailbox registers. 132 * SET/CLR registers set/clear bit(s) if "1" is written. 133 */ 134 #define IWM_CSR_UCODE_DRV_GP1 (0x054) 135 #define IWM_CSR_UCODE_DRV_GP1_SET (0x058) 136 #define IWM_CSR_UCODE_DRV_GP1_CLR (0x05c) 137 #define IWM_CSR_UCODE_DRV_GP2 (0x060) 138 139 #define IWM_CSR_MBOX_SET_REG (0x088) 140 #define IWM_CSR_MBOX_SET_REG_OS_ALIVE 0x20 141 142 #define IWM_CSR_LED_REG (0x094) 143 #define IWM_CSR_DRAM_INT_TBL_REG (0x0A0) 144 #define IWM_CSR_MAC_SHADOW_REG_CTRL (0x0A8) /* 6000 and up */ 145 146 147 /* GIO Chicken Bits (PCI Express bus link power management) */ 148 #define IWM_CSR_GIO_CHICKEN_BITS (0x100) 149 150 /* Analog phase-lock-loop configuration */ 151 #define IWM_CSR_ANA_PLL_CFG (0x20c) 152 153 /* 154 * CSR Hardware Revision Workaround Register. Indicates hardware rev; 155 * "step" determines CCK backoff for txpower calculation. Used for 4965 only. 156 * See also IWM_CSR_HW_REV register. 157 * Bit fields: 158 * 3-2: 0 = A, 1 = B, 2 = C, 3 = D step 159 * 1-0: "Dash" (-) value, as in C-1, etc. 160 */ 161 #define IWM_CSR_HW_REV_WA_REG (0x22C) 162 163 #define IWM_CSR_DBG_HPET_MEM_REG (0x240) 164 #define IWM_CSR_DBG_LINK_PWR_MGMT_REG (0x250) 165 166 /* Bits for IWM_CSR_HW_IF_CONFIG_REG */ 167 #define IWM_CSR_HW_IF_CONFIG_REG_MSK_MAC_DASH (0x00000003) 168 #define IWM_CSR_HW_IF_CONFIG_REG_MSK_MAC_STEP (0x0000000C) 169 #define IWM_CSR_HW_IF_CONFIG_REG_MSK_BOARD_VER (0x000000C0) 170 #define IWM_CSR_HW_IF_CONFIG_REG_BIT_MAC_SI (0x00000100) 171 #define IWM_CSR_HW_IF_CONFIG_REG_BIT_RADIO_SI (0x00000200) 172 #define IWM_CSR_HW_IF_CONFIG_REG_MSK_PHY_TYPE (0x00000C00) 173 #define IWM_CSR_HW_IF_CONFIG_REG_MSK_PHY_DASH (0x00003000) 174 #define IWM_CSR_HW_IF_CONFIG_REG_MSK_PHY_STEP (0x0000C000) 175 176 #define IWM_CSR_HW_IF_CONFIG_REG_POS_MAC_DASH (0) 177 #define IWM_CSR_HW_IF_CONFIG_REG_POS_MAC_STEP (2) 178 #define IWM_CSR_HW_IF_CONFIG_REG_POS_BOARD_VER (6) 179 #define IWM_CSR_HW_IF_CONFIG_REG_POS_PHY_TYPE (10) 180 #define IWM_CSR_HW_IF_CONFIG_REG_POS_PHY_DASH (12) 181 #define IWM_CSR_HW_IF_CONFIG_REG_POS_PHY_STEP (14) 182 183 #define IWM_CSR_HW_IF_CONFIG_REG_BIT_HAP_WAKE_L1A (0x00080000) 184 #define IWM_CSR_HW_IF_CONFIG_REG_BIT_EEPROM_OWN_SEM (0x00200000) 185 #define IWM_CSR_HW_IF_CONFIG_REG_BIT_NIC_READY (0x00400000) /* PCI_OWN_SEM */ 186 #define IWM_CSR_HW_IF_CONFIG_REG_BIT_NIC_PREPARE_DONE (0x02000000) /* ME_OWN */ 187 #define IWM_CSR_HW_IF_CONFIG_REG_PREPARE (0x08000000) /* WAKE_ME */ 188 #define IWM_CSR_HW_IF_CONFIG_REG_ENABLE_PME (0x10000000) 189 #define IWM_CSR_HW_IF_CONFIG_REG_PERSIST_MODE (0x40000000) /* PERSISTENCE */ 190 191 #define IWM_CSR_INT_PERIODIC_DIS (0x00) /* disable periodic int*/ 192 #define IWM_CSR_INT_PERIODIC_ENA (0xFF) /* 255*32 usec ~ 8 msec*/ 193 194 /* interrupt flags in INTA, set by uCode or hardware (e.g. dma), 195 * acknowledged (reset) by host writing "1" to flagged bits. */ 196 #define IWM_CSR_INT_BIT_FH_RX (1 << 31) /* Rx DMA, cmd responses, FH_INT[17:16] */ 197 #define IWM_CSR_INT_BIT_HW_ERR (1 << 29) /* DMA hardware error FH_INT[31] */ 198 #define IWM_CSR_INT_BIT_RX_PERIODIC (1 << 28) /* Rx periodic */ 199 #define IWM_CSR_INT_BIT_FH_TX (1 << 27) /* Tx DMA FH_INT[1:0] */ 200 #define IWM_CSR_INT_BIT_SCD (1 << 26) /* TXQ pointer advanced */ 201 #define IWM_CSR_INT_BIT_SW_ERR (1 << 25) /* uCode error */ 202 #define IWM_CSR_INT_BIT_RF_KILL (1 << 7) /* HW RFKILL switch GP_CNTRL[27] toggled */ 203 #define IWM_CSR_INT_BIT_CT_KILL (1 << 6) /* Critical temp (chip too hot) rfkill */ 204 #define IWM_CSR_INT_BIT_SW_RX (1 << 3) /* Rx, command responses */ 205 #define IWM_CSR_INT_BIT_WAKEUP (1 << 1) /* NIC controller waking up (pwr mgmt) */ 206 #define IWM_CSR_INT_BIT_ALIVE (1 << 0) /* uCode interrupts once it initializes */ 207 208 #define IWM_CSR_INI_SET_MASK (IWM_CSR_INT_BIT_FH_RX | \ 209 IWM_CSR_INT_BIT_HW_ERR | \ 210 IWM_CSR_INT_BIT_FH_TX | \ 211 IWM_CSR_INT_BIT_SW_ERR | \ 212 IWM_CSR_INT_BIT_RF_KILL | \ 213 IWM_CSR_INT_BIT_SW_RX | \ 214 IWM_CSR_INT_BIT_WAKEUP | \ 215 IWM_CSR_INT_BIT_ALIVE | \ 216 IWM_CSR_INT_BIT_RX_PERIODIC) 217 218 /* interrupt flags in FH (flow handler) (PCI busmaster DMA) */ 219 #define IWM_CSR_FH_INT_BIT_ERR (1 << 31) /* Error */ 220 #define IWM_CSR_FH_INT_BIT_HI_PRIOR (1 << 30) /* High priority Rx, bypass coalescing */ 221 #define IWM_CSR_FH_INT_BIT_RX_CHNL1 (1 << 17) /* Rx channel 1 */ 222 #define IWM_CSR_FH_INT_BIT_RX_CHNL0 (1 << 16) /* Rx channel 0 */ 223 #define IWM_CSR_FH_INT_BIT_TX_CHNL1 (1 << 1) /* Tx channel 1 */ 224 #define IWM_CSR_FH_INT_BIT_TX_CHNL0 (1 << 0) /* Tx channel 0 */ 225 226 #define IWM_CSR_FH_INT_RX_MASK (IWM_CSR_FH_INT_BIT_HI_PRIOR | \ 227 IWM_CSR_FH_INT_BIT_RX_CHNL1 | \ 228 IWM_CSR_FH_INT_BIT_RX_CHNL0) 229 230 #define IWM_CSR_FH_INT_TX_MASK (IWM_CSR_FH_INT_BIT_TX_CHNL1 | \ 231 IWM_CSR_FH_INT_BIT_TX_CHNL0) 232 233 /* GPIO */ 234 #define IWM_CSR_GPIO_IN_BIT_AUX_POWER (0x00000200) 235 #define IWM_CSR_GPIO_IN_VAL_VAUX_PWR_SRC (0x00000000) 236 #define IWM_CSR_GPIO_IN_VAL_VMAIN_PWR_SRC (0x00000200) 237 238 /* RESET */ 239 #define IWM_CSR_RESET_REG_FLAG_NEVO_RESET (0x00000001) 240 #define IWM_CSR_RESET_REG_FLAG_FORCE_NMI (0x00000002) 241 #define IWM_CSR_RESET_REG_FLAG_SW_RESET (0x00000080) 242 #define IWM_CSR_RESET_REG_FLAG_MASTER_DISABLED (0x00000100) 243 #define IWM_CSR_RESET_REG_FLAG_STOP_MASTER (0x00000200) 244 #define IWM_CSR_RESET_LINK_PWR_MGMT_DISABLED (0x80000000) 245 246 /* 247 * GP (general purpose) CONTROL REGISTER 248 * Bit fields: 249 * 27: HW_RF_KILL_SW 250 * Indicates state of (platform's) hardware RF-Kill switch 251 * 26-24: POWER_SAVE_TYPE 252 * Indicates current power-saving mode: 253 * 000 -- No power saving 254 * 001 -- MAC power-down 255 * 010 -- PHY (radio) power-down 256 * 011 -- Error 257 * 9-6: SYS_CONFIG 258 * Indicates current system configuration, reflecting pins on chip 259 * as forced high/low by device circuit board. 260 * 4: GOING_TO_SLEEP 261 * Indicates MAC is entering a power-saving sleep power-down. 262 * Not a good time to access device-internal resources. 263 * 3: MAC_ACCESS_REQ 264 * Host sets this to request and maintain MAC wakeup, to allow host 265 * access to device-internal resources. Host must wait for 266 * MAC_CLOCK_READY (and !GOING_TO_SLEEP) before accessing non-CSR 267 * device registers. 268 * 2: INIT_DONE 269 * Host sets this to put device into fully operational D0 power mode. 270 * Host resets this after SW_RESET to put device into low power mode. 271 * 0: MAC_CLOCK_READY 272 * Indicates MAC (ucode processor, etc.) is powered up and can run. 273 * Internal resources are accessible. 274 * NOTE: This does not indicate that the processor is actually running. 275 * NOTE: This does not indicate that device has completed 276 * init or post-power-down restore of internal SRAM memory. 277 * Use IWM_CSR_UCODE_DRV_GP1_BIT_MAC_SLEEP as indication that 278 * SRAM is restored and uCode is in normal operation mode. 279 * Later devices (5xxx/6xxx/1xxx) use non-volatile SRAM, and 280 * do not need to save/restore it. 281 * NOTE: After device reset, this bit remains "0" until host sets 282 * INIT_DONE 283 */ 284 #define IWM_CSR_GP_CNTRL_REG_FLAG_MAC_CLOCK_READY (0x00000001) 285 #define IWM_CSR_GP_CNTRL_REG_FLAG_INIT_DONE (0x00000004) 286 #define IWM_CSR_GP_CNTRL_REG_FLAG_MAC_ACCESS_REQ (0x00000008) 287 #define IWM_CSR_GP_CNTRL_REG_FLAG_GOING_TO_SLEEP (0x00000010) 288 289 #define IWM_CSR_GP_CNTRL_REG_VAL_MAC_ACCESS_EN (0x00000001) 290 291 #define IWM_CSR_GP_CNTRL_REG_MSK_POWER_SAVE_TYPE (0x07000000) 292 #define IWM_CSR_GP_CNTRL_REG_FLAG_MAC_POWER_SAVE (0x04000000) 293 #define IWM_CSR_GP_CNTRL_REG_FLAG_HW_RF_KILL_SW (0x08000000) 294 295 296 /* HW REV */ 297 #define IWM_CSR_HW_REV_DASH(_val) (((_val) & 0x0000003) >> 0) 298 #define IWM_CSR_HW_REV_STEP(_val) (((_val) & 0x000000C) >> 2) 299 300 /** 301 * hw_rev values 302 */ 303 enum { 304 IWM_SILICON_A_STEP = 0, 305 IWM_SILICON_B_STEP, 306 IWM_SILICON_C_STEP, 307 }; 308 309 310 #define IWM_CSR_HW_REV_TYPE_MSK (0x000FFF0) 311 #define IWM_CSR_HW_REV_TYPE_5300 (0x0000020) 312 #define IWM_CSR_HW_REV_TYPE_5350 (0x0000030) 313 #define IWM_CSR_HW_REV_TYPE_5100 (0x0000050) 314 #define IWM_CSR_HW_REV_TYPE_5150 (0x0000040) 315 #define IWM_CSR_HW_REV_TYPE_1000 (0x0000060) 316 #define IWM_CSR_HW_REV_TYPE_6x00 (0x0000070) 317 #define IWM_CSR_HW_REV_TYPE_6x50 (0x0000080) 318 #define IWM_CSR_HW_REV_TYPE_6150 (0x0000084) 319 #define IWM_CSR_HW_REV_TYPE_6x05 (0x00000B0) 320 #define IWM_CSR_HW_REV_TYPE_6x30 IWM_CSR_HW_REV_TYPE_6x05 321 #define IWM_CSR_HW_REV_TYPE_6x35 IWM_CSR_HW_REV_TYPE_6x05 322 #define IWM_CSR_HW_REV_TYPE_2x30 (0x00000C0) 323 #define IWM_CSR_HW_REV_TYPE_2x00 (0x0000100) 324 #define IWM_CSR_HW_REV_TYPE_105 (0x0000110) 325 #define IWM_CSR_HW_REV_TYPE_135 (0x0000120) 326 #define IWM_CSR_HW_REV_TYPE_7265D (0x0000210) 327 #define IWM_CSR_HW_REV_TYPE_NONE (0x00001F0) 328 329 /* EEPROM REG */ 330 #define IWM_CSR_EEPROM_REG_READ_VALID_MSK (0x00000001) 331 #define IWM_CSR_EEPROM_REG_BIT_CMD (0x00000002) 332 #define IWM_CSR_EEPROM_REG_MSK_ADDR (0x0000FFFC) 333 #define IWM_CSR_EEPROM_REG_MSK_DATA (0xFFFF0000) 334 335 /* EEPROM GP */ 336 #define IWM_CSR_EEPROM_GP_VALID_MSK (0x00000007) /* signature */ 337 #define IWM_CSR_EEPROM_GP_IF_OWNER_MSK (0x00000180) 338 #define IWM_CSR_EEPROM_GP_BAD_SIGNATURE_BOTH_EEP_AND_OTP (0x00000000) 339 #define IWM_CSR_EEPROM_GP_BAD_SIG_EEP_GOOD_SIG_OTP (0x00000001) 340 #define IWM_CSR_EEPROM_GP_GOOD_SIG_EEP_LESS_THAN_4K (0x00000002) 341 #define IWM_CSR_EEPROM_GP_GOOD_SIG_EEP_MORE_THAN_4K (0x00000004) 342 343 /* One-time-programmable memory general purpose reg */ 344 #define IWM_CSR_OTP_GP_REG_DEVICE_SELECT (0x00010000) /* 0 - EEPROM, 1 - OTP */ 345 #define IWM_CSR_OTP_GP_REG_OTP_ACCESS_MODE (0x00020000) /* 0 - absolute, 1 - relative */ 346 #define IWM_CSR_OTP_GP_REG_ECC_CORR_STATUS_MSK (0x00100000) /* bit 20 */ 347 #define IWM_CSR_OTP_GP_REG_ECC_UNCORR_STATUS_MSK (0x00200000) /* bit 21 */ 348 349 /* GP REG */ 350 #define IWM_CSR_GP_REG_POWER_SAVE_STATUS_MSK (0x03000000) /* bit 24/25 */ 351 #define IWM_CSR_GP_REG_NO_POWER_SAVE (0x00000000) 352 #define IWM_CSR_GP_REG_MAC_POWER_SAVE (0x01000000) 353 #define IWM_CSR_GP_REG_PHY_POWER_SAVE (0x02000000) 354 #define IWM_CSR_GP_REG_POWER_SAVE_ERROR (0x03000000) 355 356 357 /* CSR GIO */ 358 #define IWM_CSR_GIO_REG_VAL_L0S_ENABLED (0x00000002) 359 360 /* 361 * UCODE-DRIVER GP (general purpose) mailbox register 1 362 * Host driver and uCode write and/or read this register to communicate with 363 * each other. 364 * Bit fields: 365 * 4: UCODE_DISABLE 366 * Host sets this to request permanent halt of uCode, same as 367 * sending CARD_STATE command with "halt" bit set. 368 * 3: CT_KILL_EXIT 369 * Host sets this to request exit from CT_KILL state, i.e. host thinks 370 * device temperature is low enough to continue normal operation. 371 * 2: CMD_BLOCKED 372 * Host sets this during RF KILL power-down sequence (HW, SW, CT KILL) 373 * to release uCode to clear all Tx and command queues, enter 374 * unassociated mode, and power down. 375 * NOTE: Some devices also use HBUS_TARG_MBX_C register for this bit. 376 * 1: SW_BIT_RFKILL 377 * Host sets this when issuing CARD_STATE command to request 378 * device sleep. 379 * 0: MAC_SLEEP 380 * uCode sets this when preparing a power-saving power-down. 381 * uCode resets this when power-up is complete and SRAM is sane. 382 * NOTE: device saves internal SRAM data to host when powering down, 383 * and must restore this data after powering back up. 384 * MAC_SLEEP is the best indication that restore is complete. 385 * Later devices (5xxx/6xxx/1xxx) use non-volatile SRAM, and 386 * do not need to save/restore it. 387 */ 388 #define IWM_CSR_UCODE_DRV_GP1_BIT_MAC_SLEEP (0x00000001) 389 #define IWM_CSR_UCODE_SW_BIT_RFKILL (0x00000002) 390 #define IWM_CSR_UCODE_DRV_GP1_BIT_CMD_BLOCKED (0x00000004) 391 #define IWM_CSR_UCODE_DRV_GP1_REG_BIT_CT_KILL_EXIT (0x00000008) 392 #define IWM_CSR_UCODE_DRV_GP1_BIT_D3_CFG_COMPLETE (0x00000020) 393 394 /* GP Driver */ 395 #define IWM_CSR_GP_DRIVER_REG_BIT_RADIO_SKU_MSK (0x00000003) 396 #define IWM_CSR_GP_DRIVER_REG_BIT_RADIO_SKU_3x3_HYB (0x00000000) 397 #define IWM_CSR_GP_DRIVER_REG_BIT_RADIO_SKU_2x2_HYB (0x00000001) 398 #define IWM_CSR_GP_DRIVER_REG_BIT_RADIO_SKU_2x2_IPA (0x00000002) 399 #define IWM_CSR_GP_DRIVER_REG_BIT_CALIB_VERSION6 (0x00000004) 400 #define IWM_CSR_GP_DRIVER_REG_BIT_6050_1x2 (0x00000008) 401 402 #define IWM_CSR_GP_DRIVER_REG_BIT_RADIO_IQ_INVER (0x00000080) 403 404 /* GIO Chicken Bits (PCI Express bus link power management) */ 405 #define IWM_CSR_GIO_CHICKEN_BITS_REG_BIT_L1A_NO_L0S_RX (0x00800000) 406 #define IWM_CSR_GIO_CHICKEN_BITS_REG_BIT_DIS_L0S_EXIT_TIMER (0x20000000) 407 408 /* LED */ 409 #define IWM_CSR_LED_BSM_CTRL_MSK (0xFFFFFFDF) 410 #define IWM_CSR_LED_REG_TURN_ON (0x60) 411 #define IWM_CSR_LED_REG_TURN_OFF (0x20) 412 413 /* ANA_PLL */ 414 #define IWM_CSR50_ANA_PLL_CFG_VAL (0x00880300) 415 416 /* HPET MEM debug */ 417 #define IWM_CSR_DBG_HPET_MEM_REG_VAL (0xFFFF0000) 418 419 /* DRAM INT TABLE */ 420 #define IWM_CSR_DRAM_INT_TBL_ENABLE (1 << 31) 421 #define IWM_CSR_DRAM_INIT_TBL_WRITE_POINTER (1 << 28) 422 #define IWM_CSR_DRAM_INIT_TBL_WRAP_CHECK (1 << 27) 423 424 /* SECURE boot registers */ 425 #define IWM_CSR_SECURE_BOOT_CONFIG_ADDR (0x100) 426 enum iwm_secure_boot_config_reg { 427 IWM_CSR_SECURE_BOOT_CONFIG_INSPECTOR_BURNED_IN_OTP = 0x00000001, 428 IWM_CSR_SECURE_BOOT_CONFIG_INSPECTOR_NOT_REQ = 0x00000002, 429 }; 430 431 #define IWM_CSR_SECURE_BOOT_CPU1_STATUS_ADDR (0x100) 432 #define IWM_CSR_SECURE_BOOT_CPU2_STATUS_ADDR (0x100) 433 enum iwm_secure_boot_status_reg { 434 IWM_CSR_SECURE_BOOT_CPU_STATUS_VERF_STATUS = 0x00000003, 435 IWM_CSR_SECURE_BOOT_CPU_STATUS_VERF_COMPLETED = 0x00000002, 436 IWM_CSR_SECURE_BOOT_CPU_STATUS_VERF_SUCCESS = 0x00000004, 437 IWM_CSR_SECURE_BOOT_CPU_STATUS_VERF_FAIL = 0x00000008, 438 IWM_CSR_SECURE_BOOT_CPU_STATUS_SIGN_VERF_FAIL = 0x00000010, 439 }; 440 441 #define IWM_FH_UCODE_LOAD_STATUS 0x1af0 442 #define IWM_CSR_UCODE_LOAD_STATUS_ADDR 0x1e70 443 enum iwm_secure_load_status_reg { 444 IWM_LMPM_CPU_UCODE_LOADING_STARTED = 0x00000001, 445 IWM_LMPM_CPU_HDRS_LOADING_COMPLETED = 0x00000003, 446 IWM_LMPM_CPU_UCODE_LOADING_COMPLETED = 0x00000007, 447 IWM_LMPM_CPU_STATUS_NUM_OF_LAST_COMPLETED = 0x000000F8, 448 IWM_LMPM_CPU_STATUS_NUM_OF_LAST_LOADED_BLOCK = 0x0000FF00, 449 }; 450 #define IWM_FH_MEM_TB_MAX_LENGTH 0x20000 451 452 #define IWM_LMPM_SECURE_INSPECTOR_CODE_ADDR 0x1e38 453 #define IWM_LMPM_SECURE_INSPECTOR_DATA_ADDR 0x1e3c 454 #define IWM_LMPM_SECURE_UCODE_LOAD_CPU1_HDR_ADDR 0x1e78 455 #define IWM_LMPM_SECURE_UCODE_LOAD_CPU2_HDR_ADDR 0x1e7c 456 457 #define IWM_LMPM_SECURE_INSPECTOR_CODE_MEM_SPACE 0x400000 458 #define IWM_LMPM_SECURE_INSPECTOR_DATA_MEM_SPACE 0x402000 459 #define IWM_LMPM_SECURE_CPU1_HDR_MEM_SPACE 0x420000 460 #define IWM_LMPM_SECURE_CPU2_HDR_MEM_SPACE 0x420400 461 462 #define IWM_CSR_SECURE_TIME_OUT (100) 463 464 /* extended range in FW SRAM */ 465 #define IWM_FW_MEM_EXTENDED_START 0x40000 466 #define IWM_FW_MEM_EXTENDED_END 0x57FFF 467 468 /* FW chicken bits */ 469 #define IWM_LMPM_CHICK 0xa01ff8 470 #define IWM_LMPM_CHICK_EXTENDED_ADDR_SPACE 0x01 471 472 #define IWM_FH_TCSR_0_REG0 (0x1D00) 473 474 /* 475 * HBUS (Host-side Bus) 476 * 477 * HBUS registers are mapped directly into PCI bus space, but are used 478 * to indirectly access device's internal memory or registers that 479 * may be powered-down. 480 * 481 * Use iwl_write_direct32()/iwl_read_direct32() family for these registers; 482 * host must "grab nic access" via CSR_GP_CNTRL_REG_FLAG_MAC_ACCESS_REQ 483 * to make sure the MAC (uCode processor, etc.) is powered up for accessing 484 * internal resources. 485 * 486 * Do not use iwl_write32()/iwl_read32() family to access these registers; 487 * these provide only simple PCI bus access, without waking up the MAC. 488 */ 489 #define IWM_HBUS_BASE (0x400) 490 491 /* 492 * Registers for accessing device's internal SRAM memory (e.g. SCD SRAM 493 * structures, error log, event log, verifying uCode load). 494 * First write to address register, then read from or write to data register 495 * to complete the job. Once the address register is set up, accesses to 496 * data registers auto-increment the address by one dword. 497 * Bit usage for address registers (read or write): 498 * 0-31: memory address within device 499 */ 500 #define IWM_HBUS_TARG_MEM_RADDR (IWM_HBUS_BASE+0x00c) 501 #define IWM_HBUS_TARG_MEM_WADDR (IWM_HBUS_BASE+0x010) 502 #define IWM_HBUS_TARG_MEM_WDAT (IWM_HBUS_BASE+0x018) 503 #define IWM_HBUS_TARG_MEM_RDAT (IWM_HBUS_BASE+0x01c) 504 505 /* Mailbox C, used as workaround alternative to CSR_UCODE_DRV_GP1 mailbox */ 506 #define IWM_HBUS_TARG_MBX_C (IWM_HBUS_BASE+0x030) 507 #define IWM_HBUS_TARG_MBX_C_REG_BIT_CMD_BLOCKED (0x00000004) 508 509 /* 510 * Registers for accessing device's internal peripheral registers 511 * (e.g. SCD, BSM, etc.). First write to address register, 512 * then read from or write to data register to complete the job. 513 * Bit usage for address registers (read or write): 514 * 0-15: register address (offset) within device 515 * 24-25: (# bytes - 1) to read or write (e.g. 3 for dword) 516 */ 517 #define IWM_HBUS_TARG_PRPH_WADDR (IWM_HBUS_BASE+0x044) 518 #define IWM_HBUS_TARG_PRPH_RADDR (IWM_HBUS_BASE+0x048) 519 #define IWM_HBUS_TARG_PRPH_WDAT (IWM_HBUS_BASE+0x04c) 520 #define IWM_HBUS_TARG_PRPH_RDAT (IWM_HBUS_BASE+0x050) 521 522 /* enable the ID buf for read */ 523 #define IWM_WFPM_PS_CTL_CLR 0xa0300c 524 #define IWM_WFMP_MAC_ADDR_0 0xa03080 525 #define IWM_WFMP_MAC_ADDR_1 0xa03084 526 #define IWM_LMPM_PMG_EN 0xa01cec 527 #define IWM_RADIO_REG_SYS_MANUAL_DFT_0 0xad4078 528 #define IWM_RFIC_REG_RD 0xad0470 529 #define IWM_WFPM_CTRL_REG 0xa03030 530 #define IWM_WFPM_AUX_CTL_AUX_IF_MAC_OWNER_MSK 0x08000000 531 #define IWM_ENABLE_WFPM 0x80000000 532 533 #define IWM_AUX_MISC_REG 0xa200b0 534 #define IWM_HW_STEP_LOCATION_BITS 24 535 536 #define IWM_AUX_MISC_MASTER1_EN 0xa20818 537 #define IWM_AUX_MISC_MASTER1_EN_SBE_MSK 0x1 538 #define IWM_AUX_MISC_MASTER1_SMPHR_STATUS 0xa20800 539 #define IWM_RSA_ENABLE 0xa24b08 540 #define IWM_PREG_AUX_BUS_WPROT_0 0xa04cc0 541 #define IWM_SB_CFG_OVERRIDE_ADDR 0xa26c78 542 #define IWM_SB_CFG_OVERRIDE_ENABLE 0x8000 543 #define IWM_SB_CFG_BASE_OVERRIDE 0xa20000 544 #define IWM_SB_MODIFY_CFG_FLAG 0xa03088 545 #define IWM_SB_CPU_1_STATUS 0xa01e30 546 #define IWM_SB_CPU_2_STATUS 0Xa01e34 547 548 /* Used to enable DBGM */ 549 #define IWM_HBUS_TARG_TEST_REG (IWM_HBUS_BASE+0x05c) 550 551 /* 552 * Per-Tx-queue write pointer (index, really!) 553 * Indicates index to next TFD that driver will fill (1 past latest filled). 554 * Bit usage: 555 * 0-7: queue write index 556 * 11-8: queue selector 557 */ 558 #define IWM_HBUS_TARG_WRPTR (IWM_HBUS_BASE+0x060) 559 560 /********************************************************** 561 * CSR values 562 **********************************************************/ 563 /* 564 * host interrupt timeout value 565 * used with setting interrupt coalescing timer 566 * the CSR_INT_COALESCING is an 8 bit register in 32-usec unit 567 * 568 * default interrupt coalescing timer is 64 x 32 = 2048 usecs 569 */ 570 #define IWM_HOST_INT_TIMEOUT_MAX (0xFF) 571 #define IWM_HOST_INT_TIMEOUT_DEF (0x40) 572 #define IWM_HOST_INT_TIMEOUT_MIN (0x0) 573 #define IWM_HOST_INT_OPER_MODE (1 << 31) 574 575 /***************************************************************************** 576 * 7000/3000 series SHR DTS addresses * 577 *****************************************************************************/ 578 579 /* Diode Results Register Structure: */ 580 enum iwm_dtd_diode_reg { 581 IWM_DTS_DIODE_REG_DIG_VAL = 0x000000FF, /* bits [7:0] */ 582 IWM_DTS_DIODE_REG_VREF_LOW = 0x0000FF00, /* bits [15:8] */ 583 IWM_DTS_DIODE_REG_VREF_HIGH = 0x00FF0000, /* bits [23:16] */ 584 IWM_DTS_DIODE_REG_VREF_ID = 0x03000000, /* bits [25:24] */ 585 IWM_DTS_DIODE_REG_PASS_ONCE = 0x80000000, /* bits [31:31] */ 586 IWM_DTS_DIODE_REG_FLAGS_MSK = 0xFF000000, /* bits [31:24] */ 587 /* Those are the masks INSIDE the flags bit-field: */ 588 IWM_DTS_DIODE_REG_FLAGS_VREFS_ID_POS = 0, 589 IWM_DTS_DIODE_REG_FLAGS_VREFS_ID = 0x00000003, /* bits [1:0] */ 590 IWM_DTS_DIODE_REG_FLAGS_PASS_ONCE_POS = 7, 591 IWM_DTS_DIODE_REG_FLAGS_PASS_ONCE = 0x00000080, /* bits [7:7] */ 592 }; 593 594 /* 595 * END iwl-csr.h 596 */ 597 598 /* 599 * BEGIN iwl-fw.h 600 */ 601 602 /** 603 * enum iwm_ucode_tlv_flag - ucode API flags 604 * @IWM_UCODE_TLV_FLAGS_PAN: This is PAN capable microcode; this previously 605 * was a separate TLV but moved here to save space. 606 * @IWM_UCODE_TLV_FLAGS_NEWSCAN: new uCode scan behaviour on hidden SSID, 607 * treats good CRC threshold as a boolean 608 * @IWM_UCODE_TLV_FLAGS_MFP: This uCode image supports MFP (802.11w). 609 * @IWM_UCODE_TLV_FLAGS_P2P: This uCode image supports P2P. 610 * @IWM_UCODE_TLV_FLAGS_DW_BC_TABLE: The SCD byte count table is in DWORDS 611 * @IWM_UCODE_TLV_FLAGS_UAPSD: This uCode image supports uAPSD 612 * @IWM_UCODE_TLV_FLAGS_SHORT_BL: 16 entries of black list instead of 64 in scan 613 * offload profile config command. 614 * @IWM_UCODE_TLV_FLAGS_D3_6_IPV6_ADDRS: D3 image supports up to six 615 * (rather than two) IPv6 addresses 616 * @IWM_UCODE_TLV_FLAGS_NO_BASIC_SSID: not sending a probe with the SSID element 617 * from the probe request template. 618 * @IWM_UCODE_TLV_FLAGS_NEW_NSOFFL_SMALL: new NS offload (small version) 619 * @IWM_UCODE_TLV_FLAGS_NEW_NSOFFL_LARGE: new NS offload (large version) 620 * @IWM_UCODE_TLV_FLAGS_P2P_PS: P2P client power save is supported (only on a 621 * single bound interface). 622 * @IWM_UCODE_TLV_FLAGS_UAPSD_SUPPORT: General support for uAPSD 623 * @IWM_UCODE_TLV_FLAGS_EBS_SUPPORT: this uCode image supports EBS. 624 * @IWM_UCODE_TLV_FLAGS_P2P_PS_UAPSD: P2P client supports uAPSD power save 625 * @IWM_UCODE_TLV_FLAGS_BCAST_FILTERING: uCode supports broadcast filtering. 626 * @IWM_UCODE_TLV_FLAGS_GO_UAPSD: AP/GO interfaces support uAPSD clients 627 * 628 */ 629 enum iwm_ucode_tlv_flag { 630 IWM_UCODE_TLV_FLAGS_PAN = (1 << 0), 631 IWM_UCODE_TLV_FLAGS_NEWSCAN = (1 << 1), 632 IWM_UCODE_TLV_FLAGS_MFP = (1 << 2), 633 IWM_UCODE_TLV_FLAGS_P2P = (1 << 3), 634 IWM_UCODE_TLV_FLAGS_DW_BC_TABLE = (1 << 4), 635 IWM_UCODE_TLV_FLAGS_SHORT_BL = (1 << 7), 636 IWM_UCODE_TLV_FLAGS_D3_6_IPV6_ADDRS = (1 << 10), 637 IWM_UCODE_TLV_FLAGS_NO_BASIC_SSID = (1 << 12), 638 IWM_UCODE_TLV_FLAGS_NEW_NSOFFL_SMALL = (1 << 15), 639 IWM_UCODE_TLV_FLAGS_NEW_NSOFFL_LARGE = (1 << 16), 640 IWM_UCODE_TLV_FLAGS_P2P_PS = (1 << 21), 641 IWM_UCODE_TLV_FLAGS_BSS_P2P_PS_DCM = (1 << 22), 642 IWM_UCODE_TLV_FLAGS_BSS_P2P_PS_SCM = (1 << 23), 643 IWM_UCODE_TLV_FLAGS_UAPSD_SUPPORT = (1 << 24), 644 IWM_UCODE_TLV_FLAGS_EBS_SUPPORT = (1 << 25), 645 IWM_UCODE_TLV_FLAGS_P2P_PS_UAPSD = (1 << 26), 646 IWM_UCODE_TLV_FLAGS_BCAST_FILTERING = (1 << 29), 647 IWM_UCODE_TLV_FLAGS_GO_UAPSD = (1 << 30), 648 IWM_UCODE_TLV_FLAGS_LTE_COEX = (1 << 31), 649 }; 650 651 #define IWM_UCODE_TLV_FLAG_BITS \ 652 "\020\1PAN\2NEWSCAN\3MFP\4P2P\5DW_BC_TABLE\6NEWBT_COEX\7PM_CMD\10SHORT_BL\11RX_ENERG \ 653 Y\12TIME_EVENT_V2\13D3_6_IPV6\14BF_UPDATED\15NO_BASIC_SSID\17D3_CONTINUITY\20NEW_NSOFF \ 654 L_S\21NEW_NSOFFL_L\22SCHED_SCAN\24STA_KEY_CMD\25DEVICE_PS_CMD\26P2P_PS\27P2P_PS_DCM\30 \ 655 P2P_PS_SCM\31UAPSD_SUPPORT\32EBS\33P2P_PS_UAPSD\36BCAST_FILTERING\37GO_UAPSD\40LTE_COEX" 656 657 /** 658 * enum iwm_ucode_tlv_api - ucode api 659 * @IWM_UCODE_TLV_API_FRAGMENTED_SCAN: This ucode supports active dwell time 660 * longer than the passive one, which is essential for fragmented scan. 661 * @IWM_UCODE_TLV_API_WIFI_MCC_UPDATE: ucode supports MCC updates with source. 662 * @IWM_UCODE_TLV_API_WIDE_CMD_HDR: ucode supports wide command header 663 * @IWM_UCODE_TLV_API_LQ_SS_PARAMS: Configure STBC/BFER via LQ CMD ss_params 664 * @IWM_UCODE_TLV_API_EXT_SCAN_PRIORITY: scan APIs use 8-level priority 665 * instead of 3. 666 * @IWM_UCODE_TLV_API_TX_POWER_CHAIN: TX power API has larger command size 667 * (command version 3) that supports per-chain limits 668 * 669 * @IWM_NUM_UCODE_TLV_API: number of bits used 670 */ 671 enum iwm_ucode_tlv_api { 672 IWM_UCODE_TLV_API_FRAGMENTED_SCAN = (1 << 8), 673 IWM_UCODE_TLV_API_WIFI_MCC_UPDATE = (1 << 9), 674 IWM_UCODE_TLV_API_WIDE_CMD_HDR = (1 << 14), 675 IWM_UCODE_TLV_API_LQ_SS_PARAMS = (1 << 18), 676 IWM_UCODE_TLV_API_EXT_SCAN_PRIORITY = (1 << 24), 677 IWM_UCODE_TLV_API_TX_POWER_CHAIN = (1 << 27), 678 679 IWM_NUM_UCODE_TLV_API = 32 680 }; 681 682 #define IWM_UCODE_TLV_API_BITS \ 683 "\020\10FRAGMENTED_SCAN\11WIFI_MCC_UPDATE\16WIDE_CMD_HDR\22LQ_SS_PARAMS\30EXT_SCAN_PRIO\33TX_POWER_CHAIN" 684 685 /** 686 * enum iwm_ucode_tlv_capa - ucode capabilities 687 * @IWM_UCODE_TLV_CAPA_D0I3_SUPPORT: supports D0i3 688 * @IWM_UCODE_TLV_CAPA_LAR_SUPPORT: supports Location Aware Regulatory 689 * @IWM_UCODE_TLV_CAPA_UMAC_SCAN: supports UMAC scan. 690 * @IWM_UCODE_TLV_CAPA_BEAMFORMER: supports Beamformer 691 * @IWM_UCODE_TLV_CAPA_TOF_SUPPORT: supports Time of Flight (802.11mc FTM) 692 * @IWM_UCODE_TLV_CAPA_TDLS_SUPPORT: support basic TDLS functionality 693 * @IWM_UCODE_TLV_CAPA_TXPOWER_INSERTION_SUPPORT: supports insertion of current 694 * tx power value into TPC Report action frame and Link Measurement Report 695 * action frame 696 * @IWM_UCODE_TLV_CAPA_DS_PARAM_SET_IE_SUPPORT: supports updating current 697 * channel in DS parameter set element in probe requests. 698 * @IWM_UCODE_TLV_CAPA_WFA_TPC_REP_IE_SUPPORT: supports adding TPC Report IE in 699 * probe requests. 700 * @IWM_UCODE_TLV_CAPA_QUIET_PERIOD_SUPPORT: supports Quiet Period requests 701 * @IWM_UCODE_TLV_CAPA_DQA_SUPPORT: supports dynamic queue allocation (DQA), 702 * which also implies support for the scheduler configuration command 703 * @IWM_UCODE_TLV_CAPA_TDLS_CHANNEL_SWITCH: supports TDLS channel switching 704 * @IWM_UCODE_TLV_CAPA_CNSLDTD_D3_D0_IMG: Consolidated D3-D0 image 705 * @IWM_UCODE_TLV_CAPA_HOTSPOT_SUPPORT: supports Hot Spot Command 706 * @IWM_UCODE_TLV_CAPA_DC2DC_SUPPORT: supports DC2DC Command 707 * @IWM_UCODE_TLV_CAPA_2G_COEX_SUPPORT: supports 2G coex Command 708 * @IWM_UCODE_TLV_CAPA_CSUM_SUPPORT: supports TCP Checksum Offload 709 * @IWM_UCODE_TLV_CAPA_RADIO_BEACON_STATS: support radio and beacon statistics 710 * @IWM_UCODE_TLV_CAPA_P2P_STANDALONE_UAPSD: support p2p standalone U-APSD 711 * @IWM_UCODE_TLV_CAPA_BT_COEX_PLCR: enabled BT Coex packet level co-running 712 * @IWM_UCODE_TLV_CAPA_LAR_MULTI_MCC: ucode supports LAR updates with different 713 * sources for the MCC. This TLV bit is a future replacement to 714 * IWM_UCODE_TLV_API_WIFI_MCC_UPDATE. When either is set, multi-source LAR 715 * is supported. 716 * @IWM_UCODE_TLV_CAPA_BT_COEX_RRC: supports BT Coex RRC 717 * @IWM_UCODE_TLV_CAPA_GSCAN_SUPPORT: supports gscan 718 * @IWM_UCODE_TLV_CAPA_NAN_SUPPORT: supports NAN 719 * @IWM_UCODE_TLV_CAPA_UMAC_UPLOAD: supports upload mode in umac (1=supported, 720 * 0=no support) 721 * @IWM_UCODE_TLV_CAPA_EXTENDED_DTS_MEASURE: extended DTS measurement 722 * @IWM_UCODE_TLV_CAPA_SHORT_PM_TIMEOUTS: supports short PM timeouts 723 * @IWM_UCODE_TLV_CAPA_BT_MPLUT_SUPPORT: supports bt-coex Multi-priority LUT 724 * @IWM_UCODE_TLV_CAPA_BEACON_ANT_SELECTION: firmware will decide on what 725 * antenna the beacon should be transmitted 726 * @IWM_UCODE_TLV_CAPA_BEACON_STORING: firmware will store the latest beacon 727 * from AP and will send it upon d0i3 exit. 728 * @IWM_UCODE_TLV_CAPA_LAR_SUPPORT_V2: support LAR API V2 729 * @IWM_UCODE_TLV_CAPA_CT_KILL_BY_FW: firmware responsible for CT-kill 730 * @IWM_UCODE_TLV_CAPA_TEMP_THS_REPORT_SUPPORT: supports temperature 731 * thresholds reporting 732 * @IWM_UCODE_TLV_CAPA_CTDP_SUPPORT: supports cTDP command 733 * @IWM_UCODE_TLV_CAPA_USNIFFER_UNIFIED: supports usniffer enabled in 734 * regular image. 735 * @IWM_UCODE_TLV_CAPA_EXTEND_SHARED_MEM_CFG: support getting more shared 736 * memory addresses from the firmware. 737 * @IWM_UCODE_TLV_CAPA_LQM_SUPPORT: supports Link Quality Measurement 738 * @IWM_UCODE_TLV_CAPA_LMAC_UPLOAD: supports upload mode in lmac (1=supported, 739 * 0=no support) 740 * 741 * @IWM_NUM_UCODE_TLV_CAPA: number of bits used 742 */ 743 enum iwm_ucode_tlv_capa { 744 IWM_UCODE_TLV_CAPA_D0I3_SUPPORT = 0, 745 IWM_UCODE_TLV_CAPA_LAR_SUPPORT = 1, 746 IWM_UCODE_TLV_CAPA_UMAC_SCAN = 2, 747 IWM_UCODE_TLV_CAPA_BEAMFORMER = 3, 748 IWM_UCODE_TLV_CAPA_TOF_SUPPORT = 5, 749 IWM_UCODE_TLV_CAPA_TDLS_SUPPORT = 6, 750 IWM_UCODE_TLV_CAPA_TXPOWER_INSERTION_SUPPORT = 8, 751 IWM_UCODE_TLV_CAPA_DS_PARAM_SET_IE_SUPPORT = 9, 752 IWM_UCODE_TLV_CAPA_WFA_TPC_REP_IE_SUPPORT = 10, 753 IWM_UCODE_TLV_CAPA_QUIET_PERIOD_SUPPORT = 11, 754 IWM_UCODE_TLV_CAPA_DQA_SUPPORT = 12, 755 IWM_UCODE_TLV_CAPA_TDLS_CHANNEL_SWITCH = 13, 756 IWM_UCODE_TLV_CAPA_CNSLDTD_D3_D0_IMG = 17, 757 IWM_UCODE_TLV_CAPA_HOTSPOT_SUPPORT = 18, 758 IWM_UCODE_TLV_CAPA_DC2DC_CONFIG_SUPPORT = 19, 759 IWM_UCODE_TLV_CAPA_2G_COEX_SUPPORT = 20, 760 IWM_UCODE_TLV_CAPA_CSUM_SUPPORT = 21, 761 IWM_UCODE_TLV_CAPA_RADIO_BEACON_STATS = 22, 762 IWM_UCODE_TLV_CAPA_P2P_STANDALONE_UAPSD = 26, 763 IWM_UCODE_TLV_CAPA_BT_COEX_PLCR = 28, 764 IWM_UCODE_TLV_CAPA_LAR_MULTI_MCC = 29, 765 IWM_UCODE_TLV_CAPA_BT_COEX_RRC = 30, 766 IWM_UCODE_TLV_CAPA_GSCAN_SUPPORT = 31, 767 IWM_UCODE_TLV_CAPA_NAN_SUPPORT = 34, 768 IWM_UCODE_TLV_CAPA_UMAC_UPLOAD = 35, 769 IWM_UCODE_TLV_CAPA_EXTENDED_DTS_MEASURE = 64, 770 IWM_UCODE_TLV_CAPA_SHORT_PM_TIMEOUTS = 65, 771 IWM_UCODE_TLV_CAPA_BT_MPLUT_SUPPORT = 67, 772 IWM_UCODE_TLV_CAPA_MULTI_QUEUE_RX_SUPPORT = 68, 773 IWM_UCODE_TLV_CAPA_BEACON_ANT_SELECTION = 71, 774 IWM_UCODE_TLV_CAPA_BEACON_STORING = 72, 775 IWM_UCODE_TLV_CAPA_LAR_SUPPORT_V2 = 73, 776 IWM_UCODE_TLV_CAPA_CT_KILL_BY_FW = 74, 777 IWM_UCODE_TLV_CAPA_TEMP_THS_REPORT_SUPPORT = 75, 778 IWM_UCODE_TLV_CAPA_CTDP_SUPPORT = 76, 779 IWM_UCODE_TLV_CAPA_USNIFFER_UNIFIED = 77, 780 IWM_UCODE_TLV_CAPA_LMAC_UPLOAD = 79, 781 IWM_UCODE_TLV_CAPA_EXTEND_SHARED_MEM_CFG = 80, 782 IWM_UCODE_TLV_CAPA_LQM_SUPPORT = 81, 783 784 IWM_NUM_UCODE_TLV_CAPA = 128 785 }; 786 787 /* The default calibrate table size if not specified by firmware file */ 788 #define IWM_DEFAULT_STANDARD_PHY_CALIBRATE_TBL_SIZE 18 789 #define IWM_MAX_STANDARD_PHY_CALIBRATE_TBL_SIZE 19 790 #define IWM_MAX_PHY_CALIBRATE_TBL_SIZE 253 791 792 /* The default max probe length if not specified by the firmware file */ 793 #define IWM_DEFAULT_MAX_PROBE_LENGTH 200 794 795 /* 796 * enumeration of ucode section. 797 * This enumeration is used directly for older firmware (before 16.0). 798 * For new firmware, there can be up to 4 sections (see below) but the 799 * first one packaged into the firmware file is the DATA section and 800 * some debugging code accesses that. 801 */ 802 enum iwm_ucode_sec { 803 IWM_UCODE_SECTION_DATA, 804 IWM_UCODE_SECTION_INST, 805 }; 806 /* 807 * For 16.0 uCode and above, there is no differentiation between sections, 808 * just an offset to the HW address. 809 */ 810 #define IWM_CPU1_CPU2_SEPARATOR_SECTION 0xFFFFCCCC 811 #define IWM_PAGING_SEPARATOR_SECTION 0xAAAABBBB 812 813 /* uCode version contains 4 values: Major/Minor/API/Serial */ 814 #define IWM_UCODE_MAJOR(ver) (((ver) & 0xFF000000) >> 24) 815 #define IWM_UCODE_MINOR(ver) (((ver) & 0x00FF0000) >> 16) 816 #define IWM_UCODE_API(ver) (((ver) & 0x0000FF00) >> 8) 817 #define IWM_UCODE_SERIAL(ver) ((ver) & 0x000000FF) 818 819 /* 820 * Calibration control struct. 821 * Sent as part of the phy configuration command. 822 * @flow_trigger: bitmap for which calibrations to perform according to 823 * flow triggers. 824 * @event_trigger: bitmap for which calibrations to perform according to 825 * event triggers. 826 */ 827 struct iwm_tlv_calib_ctrl { 828 uint32_t flow_trigger; 829 uint32_t event_trigger; 830 } __packed; 831 832 enum iwm_fw_phy_cfg { 833 IWM_FW_PHY_CFG_RADIO_TYPE_POS = 0, 834 IWM_FW_PHY_CFG_RADIO_TYPE = 0x3 << IWM_FW_PHY_CFG_RADIO_TYPE_POS, 835 IWM_FW_PHY_CFG_RADIO_STEP_POS = 2, 836 IWM_FW_PHY_CFG_RADIO_STEP = 0x3 << IWM_FW_PHY_CFG_RADIO_STEP_POS, 837 IWM_FW_PHY_CFG_RADIO_DASH_POS = 4, 838 IWM_FW_PHY_CFG_RADIO_DASH = 0x3 << IWM_FW_PHY_CFG_RADIO_DASH_POS, 839 IWM_FW_PHY_CFG_TX_CHAIN_POS = 16, 840 IWM_FW_PHY_CFG_TX_CHAIN = 0xf << IWM_FW_PHY_CFG_TX_CHAIN_POS, 841 IWM_FW_PHY_CFG_RX_CHAIN_POS = 20, 842 IWM_FW_PHY_CFG_RX_CHAIN = 0xf << IWM_FW_PHY_CFG_RX_CHAIN_POS, 843 }; 844 845 #define IWM_UCODE_MAX_CS 1 846 847 /** 848 * struct iwm_fw_cipher_scheme - a cipher scheme supported by FW. 849 * @cipher: a cipher suite selector 850 * @flags: cipher scheme flags (currently reserved for a future use) 851 * @hdr_len: a size of MPDU security header 852 * @pn_len: a size of PN 853 * @pn_off: an offset of pn from the beginning of the security header 854 * @key_idx_off: an offset of key index byte in the security header 855 * @key_idx_mask: a bit mask of key_idx bits 856 * @key_idx_shift: bit shift needed to get key_idx 857 * @mic_len: mic length in bytes 858 * @hw_cipher: a HW cipher index used in host commands 859 */ 860 struct iwm_fw_cipher_scheme { 861 uint32_t cipher; 862 uint8_t flags; 863 uint8_t hdr_len; 864 uint8_t pn_len; 865 uint8_t pn_off; 866 uint8_t key_idx_off; 867 uint8_t key_idx_mask; 868 uint8_t key_idx_shift; 869 uint8_t mic_len; 870 uint8_t hw_cipher; 871 } __packed; 872 873 /** 874 * struct iwm_fw_cscheme_list - a cipher scheme list 875 * @size: a number of entries 876 * @cs: cipher scheme entries 877 */ 878 struct iwm_fw_cscheme_list { 879 uint8_t size; 880 struct iwm_fw_cipher_scheme cs[]; 881 } __packed; 882 883 /* 884 * END iwl-fw.h 885 */ 886 887 /* 888 * BEGIN iwl-fw-file.h 889 */ 890 891 /* v1/v2 uCode file layout */ 892 struct iwm_ucode_header { 893 uint32_t ver; /* major/minor/API/serial */ 894 union { 895 struct { 896 uint32_t inst_size; /* bytes of runtime code */ 897 uint32_t data_size; /* bytes of runtime data */ 898 uint32_t init_size; /* bytes of init code */ 899 uint32_t init_data_size; /* bytes of init data */ 900 uint32_t boot_size; /* bytes of bootstrap code */ 901 uint8_t data[0]; /* in same order as sizes */ 902 } v1; 903 struct { 904 uint32_t build; /* build number */ 905 uint32_t inst_size; /* bytes of runtime code */ 906 uint32_t data_size; /* bytes of runtime data */ 907 uint32_t init_size; /* bytes of init code */ 908 uint32_t init_data_size; /* bytes of init data */ 909 uint32_t boot_size; /* bytes of bootstrap code */ 910 uint8_t data[0]; /* in same order as sizes */ 911 } v2; 912 } u; 913 }; 914 915 /* 916 * new TLV uCode file layout 917 * 918 * The new TLV file format contains TLVs, that each specify 919 * some piece of data. 920 */ 921 922 enum iwm_ucode_tlv_type { 923 IWM_UCODE_TLV_INVALID = 0, /* unused */ 924 IWM_UCODE_TLV_INST = 1, 925 IWM_UCODE_TLV_DATA = 2, 926 IWM_UCODE_TLV_INIT = 3, 927 IWM_UCODE_TLV_INIT_DATA = 4, 928 IWM_UCODE_TLV_BOOT = 5, 929 IWM_UCODE_TLV_PROBE_MAX_LEN = 6, /* a uint32_t value */ 930 IWM_UCODE_TLV_PAN = 7, 931 IWM_UCODE_TLV_RUNT_EVTLOG_PTR = 8, 932 IWM_UCODE_TLV_RUNT_EVTLOG_SIZE = 9, 933 IWM_UCODE_TLV_RUNT_ERRLOG_PTR = 10, 934 IWM_UCODE_TLV_INIT_EVTLOG_PTR = 11, 935 IWM_UCODE_TLV_INIT_EVTLOG_SIZE = 12, 936 IWM_UCODE_TLV_INIT_ERRLOG_PTR = 13, 937 IWM_UCODE_TLV_ENHANCE_SENS_TBL = 14, 938 IWM_UCODE_TLV_PHY_CALIBRATION_SIZE = 15, 939 IWM_UCODE_TLV_WOWLAN_INST = 16, 940 IWM_UCODE_TLV_WOWLAN_DATA = 17, 941 IWM_UCODE_TLV_FLAGS = 18, 942 IWM_UCODE_TLV_SEC_RT = 19, 943 IWM_UCODE_TLV_SEC_INIT = 20, 944 IWM_UCODE_TLV_SEC_WOWLAN = 21, 945 IWM_UCODE_TLV_DEF_CALIB = 22, 946 IWM_UCODE_TLV_PHY_SKU = 23, 947 IWM_UCODE_TLV_SECURE_SEC_RT = 24, 948 IWM_UCODE_TLV_SECURE_SEC_INIT = 25, 949 IWM_UCODE_TLV_SECURE_SEC_WOWLAN = 26, 950 IWM_UCODE_TLV_NUM_OF_CPU = 27, 951 IWM_UCODE_TLV_CSCHEME = 28, 952 953 /* 954 * Following two are not in our base tag, but allow 955 * handling ucode version 9. 956 */ 957 IWM_UCODE_TLV_API_CHANGES_SET = 29, 958 IWM_UCODE_TLV_ENABLED_CAPABILITIES = 30, 959 960 IWM_UCODE_TLV_N_SCAN_CHANNELS = 31, 961 IWM_UCODE_TLV_PAGING = 32, 962 IWM_UCODE_TLV_SEC_RT_USNIFFER = 34, 963 IWM_UCODE_TLV_SDIO_ADMA_ADDR = 35, 964 IWM_UCODE_TLV_FW_VERSION = 36, 965 IWM_UCODE_TLV_FW_DBG_DEST = 38, 966 IWM_UCODE_TLV_FW_DBG_CONF = 39, 967 IWM_UCODE_TLV_FW_DBG_TRIGGER = 40, 968 IWM_UCODE_TLV_FW_GSCAN_CAPA = 50, 969 IWM_UCODE_TLV_FW_MEM_SEG = 51, 970 }; 971 972 struct iwm_ucode_tlv { 973 uint32_t type; /* see above */ 974 uint32_t length; /* not including type/length fields */ 975 uint8_t data[0]; 976 }; 977 978 struct iwm_ucode_api { 979 uint32_t api_index; 980 uint32_t api_flags; 981 } __packed; 982 983 struct iwm_ucode_capa { 984 uint32_t api_index; 985 uint32_t api_capa; 986 } __packed; 987 988 #define IWM_TLV_UCODE_MAGIC 0x0a4c5749 989 990 struct iwm_tlv_ucode_header { 991 /* 992 * The TLV style ucode header is distinguished from 993 * the v1/v2 style header by first four bytes being 994 * zero, as such is an invalid combination of 995 * major/minor/API/serial versions. 996 */ 997 uint32_t zero; 998 uint32_t magic; 999 uint8_t human_readable[64]; 1000 uint32_t ver; /* major/minor/API/serial */ 1001 uint32_t build; 1002 uint64_t ignore; 1003 /* 1004 * The data contained herein has a TLV layout, 1005 * see above for the TLV header and types. 1006 * Note that each TLV is padded to a length 1007 * that is a multiple of 4 for alignment. 1008 */ 1009 uint8_t data[0]; 1010 }; 1011 1012 /* 1013 * END iwl-fw-file.h 1014 */ 1015 1016 /* 1017 * BEGIN iwl-prph.h 1018 */ 1019 1020 /* 1021 * Registers in this file are internal, not PCI bus memory mapped. 1022 * Driver accesses these via IWM_HBUS_TARG_PRPH_* registers. 1023 */ 1024 #define IWM_PRPH_BASE (0x00000) 1025 #define IWM_PRPH_END (0xFFFFF) 1026 1027 /* APMG (power management) constants */ 1028 #define IWM_APMG_BASE (IWM_PRPH_BASE + 0x3000) 1029 #define IWM_APMG_CLK_CTRL_REG (IWM_APMG_BASE + 0x0000) 1030 #define IWM_APMG_CLK_EN_REG (IWM_APMG_BASE + 0x0004) 1031 #define IWM_APMG_CLK_DIS_REG (IWM_APMG_BASE + 0x0008) 1032 #define IWM_APMG_PS_CTRL_REG (IWM_APMG_BASE + 0x000c) 1033 #define IWM_APMG_PCIDEV_STT_REG (IWM_APMG_BASE + 0x0010) 1034 #define IWM_APMG_RFKILL_REG (IWM_APMG_BASE + 0x0014) 1035 #define IWM_APMG_RTC_INT_STT_REG (IWM_APMG_BASE + 0x001c) 1036 #define IWM_APMG_RTC_INT_MSK_REG (IWM_APMG_BASE + 0x0020) 1037 #define IWM_APMG_DIGITAL_SVR_REG (IWM_APMG_BASE + 0x0058) 1038 #define IWM_APMG_ANALOG_SVR_REG (IWM_APMG_BASE + 0x006C) 1039 1040 #define IWM_APMS_CLK_VAL_MRB_FUNC_MODE (0x00000001) 1041 #define IWM_APMG_CLK_VAL_DMA_CLK_RQT (0x00000200) 1042 #define IWM_APMG_CLK_VAL_BSM_CLK_RQT (0x00000800) 1043 1044 #define IWM_APMG_PS_CTRL_EARLY_PWR_OFF_RESET_DIS (0x00400000) 1045 #define IWM_APMG_PS_CTRL_VAL_RESET_REQ (0x04000000) 1046 #define IWM_APMG_PS_CTRL_MSK_PWR_SRC (0x03000000) 1047 #define IWM_APMG_PS_CTRL_VAL_PWR_SRC_VMAIN (0x00000000) 1048 #define IWM_APMG_PS_CTRL_VAL_PWR_SRC_VAUX (0x02000000) 1049 #define IWM_APMG_SVR_VOLTAGE_CONFIG_BIT_MSK (0x000001E0) /* bit 8:5 */ 1050 #define IWM_APMG_SVR_DIGITAL_VOLTAGE_1_32 (0x00000060) 1051 1052 #define IWM_APMG_PCIDEV_STT_VAL_L1_ACT_DIS (0x00000800) 1053 1054 #define IWM_APMG_RTC_INT_STT_RFKILL (0x10000000) 1055 1056 /* Device system time */ 1057 #define IWM_DEVICE_SYSTEM_TIME_REG 0xA0206C 1058 1059 /* Device NMI register */ 1060 #define IWM_DEVICE_SET_NMI_REG 0x00a01c30 1061 #define IWM_DEVICE_SET_NMI_VAL_HW 0x01 1062 #define IWM_DEVICE_SET_NMI_VAL_DRV 0x80 1063 #define IWM_DEVICE_SET_NMI_8000_REG 0x00a01c24 1064 #define IWM_DEVICE_SET_NMI_8000_VAL 0x1000000 1065 1066 /* 1067 * Device reset for family 8000 1068 * write to bit 24 in order to reset the CPU 1069 */ 1070 #define IWM_RELEASE_CPU_RESET 0x300c 1071 #define IWM_RELEASE_CPU_RESET_BIT 0x1000000 1072 1073 1074 /***************************************************************************** 1075 * 7000/3000 series SHR DTS addresses * 1076 *****************************************************************************/ 1077 1078 #define IWM_SHR_MISC_WFM_DTS_EN (0x00a10024) 1079 #define IWM_DTSC_CFG_MODE (0x00a10604) 1080 #define IWM_DTSC_VREF_AVG (0x00a10648) 1081 #define IWM_DTSC_VREF5_AVG (0x00a1064c) 1082 #define IWM_DTSC_CFG_MODE_PERIODIC (0x2) 1083 #define IWM_DTSC_PTAT_AVG (0x00a10650) 1084 1085 1086 /** 1087 * Tx Scheduler 1088 * 1089 * The Tx Scheduler selects the next frame to be transmitted, choosing TFDs 1090 * (Transmit Frame Descriptors) from up to 16 circular Tx queues resident in 1091 * host DRAM. It steers each frame's Tx command (which contains the frame 1092 * data) into one of up to 7 prioritized Tx DMA FIFO channels within the 1093 * device. A queue maps to only one (selectable by driver) Tx DMA channel, 1094 * but one DMA channel may take input from several queues. 1095 * 1096 * Tx DMA FIFOs have dedicated purposes. 1097 * 1098 * For 5000 series and up, they are used differently 1099 * (cf. iwl5000_default_queue_to_tx_fifo in iwl-5000.c): 1100 * 1101 * 0 -- EDCA BK (background) frames, lowest priority 1102 * 1 -- EDCA BE (best effort) frames, normal priority 1103 * 2 -- EDCA VI (video) frames, higher priority 1104 * 3 -- EDCA VO (voice) and management frames, highest priority 1105 * 4 -- unused 1106 * 5 -- unused 1107 * 6 -- unused 1108 * 7 -- Commands 1109 * 1110 * Driver should normally map queues 0-6 to Tx DMA/FIFO channels 0-6. 1111 * In addition, driver can map the remaining queues to Tx DMA/FIFO 1112 * channels 0-3 to support 11n aggregation via EDCA DMA channels. 1113 * 1114 * The driver sets up each queue to work in one of two modes: 1115 * 1116 * 1) Scheduler-Ack, in which the scheduler automatically supports a 1117 * block-ack (BA) window of up to 64 TFDs. In this mode, each queue 1118 * contains TFDs for a unique combination of Recipient Address (RA) 1119 * and Traffic Identifier (TID), that is, traffic of a given 1120 * Quality-Of-Service (QOS) priority, destined for a single station. 1121 * 1122 * In scheduler-ack mode, the scheduler keeps track of the Tx status of 1123 * each frame within the BA window, including whether it's been transmitted, 1124 * and whether it's been acknowledged by the receiving station. The device 1125 * automatically processes block-acks received from the receiving STA, 1126 * and reschedules un-acked frames to be retransmitted (successful 1127 * Tx completion may end up being out-of-order). 1128 * 1129 * The driver must maintain the queue's Byte Count table in host DRAM 1130 * for this mode. 1131 * This mode does not support fragmentation. 1132 * 1133 * 2) FIFO (a.k.a. non-Scheduler-ACK), in which each TFD is processed in order. 1134 * The device may automatically retry Tx, but will retry only one frame 1135 * at a time, until receiving ACK from receiving station, or reaching 1136 * retry limit and giving up. 1137 * 1138 * The command queue (#4/#9) must use this mode! 1139 * This mode does not require use of the Byte Count table in host DRAM. 1140 * 1141 * Driver controls scheduler operation via 3 means: 1142 * 1) Scheduler registers 1143 * 2) Shared scheduler data base in internal SRAM 1144 * 3) Shared data in host DRAM 1145 * 1146 * Initialization: 1147 * 1148 * When loading, driver should allocate memory for: 1149 * 1) 16 TFD circular buffers, each with space for (typically) 256 TFDs. 1150 * 2) 16 Byte Count circular buffers in 16 KBytes contiguous memory 1151 * (1024 bytes for each queue). 1152 * 1153 * After receiving "Alive" response from uCode, driver must initialize 1154 * the scheduler (especially for queue #4/#9, the command queue, otherwise 1155 * the driver can't issue commands!): 1156 */ 1157 #define IWM_SCD_MEM_LOWER_BOUND (0x0000) 1158 1159 /** 1160 * Max Tx window size is the max number of contiguous TFDs that the scheduler 1161 * can keep track of at one time when creating block-ack chains of frames. 1162 * Note that "64" matches the number of ack bits in a block-ack packet. 1163 */ 1164 #define IWM_SCD_WIN_SIZE 64 1165 #define IWM_SCD_FRAME_LIMIT 64 1166 1167 #define IWM_SCD_TXFIFO_POS_TID (0) 1168 #define IWM_SCD_TXFIFO_POS_RA (4) 1169 #define IWM_SCD_QUEUE_RA_TID_MAP_RATID_MSK (0x01FF) 1170 1171 /* agn SCD */ 1172 #define IWM_SCD_QUEUE_STTS_REG_POS_TXF (0) 1173 #define IWM_SCD_QUEUE_STTS_REG_POS_ACTIVE (3) 1174 #define IWM_SCD_QUEUE_STTS_REG_POS_WSL (4) 1175 #define IWM_SCD_QUEUE_STTS_REG_POS_SCD_ACT_EN (19) 1176 #define IWM_SCD_QUEUE_STTS_REG_MSK (0x017F0000) 1177 1178 #define IWM_SCD_QUEUE_CTX_REG1_CREDIT_POS (8) 1179 #define IWM_SCD_QUEUE_CTX_REG1_CREDIT_MSK (0x00FFFF00) 1180 #define IWM_SCD_QUEUE_CTX_REG1_SUPER_CREDIT_POS (24) 1181 #define IWM_SCD_QUEUE_CTX_REG1_SUPER_CREDIT_MSK (0xFF000000) 1182 #define IWM_SCD_QUEUE_CTX_REG2_WIN_SIZE_POS (0) 1183 #define IWM_SCD_QUEUE_CTX_REG2_WIN_SIZE_MSK (0x0000007F) 1184 #define IWM_SCD_QUEUE_CTX_REG2_FRAME_LIMIT_POS (16) 1185 #define IWM_SCD_QUEUE_CTX_REG2_FRAME_LIMIT_MSK (0x007F0000) 1186 #define IWM_SCD_GP_CTRL_ENABLE_31_QUEUES (1 << 0) 1187 #define IWM_SCD_GP_CTRL_AUTO_ACTIVE_MODE (1 << 18) 1188 1189 /* Context Data */ 1190 #define IWM_SCD_CONTEXT_MEM_LOWER_BOUND (IWM_SCD_MEM_LOWER_BOUND + 0x600) 1191 #define IWM_SCD_CONTEXT_MEM_UPPER_BOUND (IWM_SCD_MEM_LOWER_BOUND + 0x6A0) 1192 1193 /* Tx status */ 1194 #define IWM_SCD_TX_STTS_MEM_LOWER_BOUND (IWM_SCD_MEM_LOWER_BOUND + 0x6A0) 1195 #define IWM_SCD_TX_STTS_MEM_UPPER_BOUND (IWM_SCD_MEM_LOWER_BOUND + 0x7E0) 1196 1197 /* Translation Data */ 1198 #define IWM_SCD_TRANS_TBL_MEM_LOWER_BOUND (IWM_SCD_MEM_LOWER_BOUND + 0x7E0) 1199 #define IWM_SCD_TRANS_TBL_MEM_UPPER_BOUND (IWM_SCD_MEM_LOWER_BOUND + 0x808) 1200 1201 #define IWM_SCD_CONTEXT_QUEUE_OFFSET(x)\ 1202 (IWM_SCD_CONTEXT_MEM_LOWER_BOUND + ((x) * 8)) 1203 1204 #define IWM_SCD_TX_STTS_QUEUE_OFFSET(x)\ 1205 (IWM_SCD_TX_STTS_MEM_LOWER_BOUND + ((x) * 16)) 1206 1207 #define IWM_SCD_TRANS_TBL_OFFSET_QUEUE(x) \ 1208 ((IWM_SCD_TRANS_TBL_MEM_LOWER_BOUND + ((x) * 2)) & 0xfffc) 1209 1210 #define IWM_SCD_BASE (IWM_PRPH_BASE + 0xa02c00) 1211 1212 #define IWM_SCD_SRAM_BASE_ADDR (IWM_SCD_BASE + 0x0) 1213 #define IWM_SCD_DRAM_BASE_ADDR (IWM_SCD_BASE + 0x8) 1214 #define IWM_SCD_AIT (IWM_SCD_BASE + 0x0c) 1215 #define IWM_SCD_TXFACT (IWM_SCD_BASE + 0x10) 1216 #define IWM_SCD_ACTIVE (IWM_SCD_BASE + 0x14) 1217 #define IWM_SCD_QUEUECHAIN_SEL (IWM_SCD_BASE + 0xe8) 1218 #define IWM_SCD_CHAINEXT_EN (IWM_SCD_BASE + 0x244) 1219 #define IWM_SCD_AGGR_SEL (IWM_SCD_BASE + 0x248) 1220 #define IWM_SCD_INTERRUPT_MASK (IWM_SCD_BASE + 0x108) 1221 #define IWM_SCD_GP_CTRL (IWM_SCD_BASE + 0x1a8) 1222 #define IWM_SCD_EN_CTRL (IWM_SCD_BASE + 0x254) 1223 1224 static inline unsigned int IWM_SCD_QUEUE_WRPTR(unsigned int chnl) 1225 { 1226 if (chnl < 20) 1227 return IWM_SCD_BASE + 0x18 + chnl * 4; 1228 return IWM_SCD_BASE + 0x284 + (chnl - 20) * 4; 1229 } 1230 1231 static inline unsigned int IWM_SCD_QUEUE_RDPTR(unsigned int chnl) 1232 { 1233 if (chnl < 20) 1234 return IWM_SCD_BASE + 0x68 + chnl * 4; 1235 return IWM_SCD_BASE + 0x2B4 + (chnl - 20) * 4; 1236 } 1237 1238 static inline unsigned int IWM_SCD_QUEUE_STATUS_BITS(unsigned int chnl) 1239 { 1240 if (chnl < 20) 1241 return IWM_SCD_BASE + 0x10c + chnl * 4; 1242 return IWM_SCD_BASE + 0x384 + (chnl - 20) * 4; 1243 } 1244 1245 /*********************** END TX SCHEDULER *************************************/ 1246 1247 /* Oscillator clock */ 1248 #define IWM_OSC_CLK (0xa04068) 1249 #define IWM_OSC_CLK_FORCE_CONTROL (0x8) 1250 1251 /* 1252 * END iwl-prph.h 1253 */ 1254 1255 /* 1256 * BEGIN iwl-fh.h 1257 */ 1258 1259 /****************************/ 1260 /* Flow Handler Definitions */ 1261 /****************************/ 1262 1263 /** 1264 * This I/O area is directly read/writable by driver (e.g. Linux uses writel()) 1265 * Addresses are offsets from device's PCI hardware base address. 1266 */ 1267 #define IWM_FH_MEM_LOWER_BOUND (0x1000) 1268 #define IWM_FH_MEM_UPPER_BOUND (0x2000) 1269 1270 /** 1271 * Keep-Warm (KW) buffer base address. 1272 * 1273 * Driver must allocate a 4KByte buffer that is for keeping the 1274 * host DRAM powered on (via dummy accesses to DRAM) to maintain low-latency 1275 * DRAM access when doing Txing or Rxing. The dummy accesses prevent host 1276 * from going into a power-savings mode that would cause higher DRAM latency, 1277 * and possible data over/under-runs, before all Tx/Rx is complete. 1278 * 1279 * Driver loads IWM_FH_KW_MEM_ADDR_REG with the physical address (bits 35:4) 1280 * of the buffer, which must be 4K aligned. Once this is set up, the device 1281 * automatically invokes keep-warm accesses when normal accesses might not 1282 * be sufficient to maintain fast DRAM response. 1283 * 1284 * Bit fields: 1285 * 31-0: Keep-warm buffer physical base address [35:4], must be 4K aligned 1286 */ 1287 #define IWM_FH_KW_MEM_ADDR_REG (IWM_FH_MEM_LOWER_BOUND + 0x97C) 1288 1289 1290 /** 1291 * TFD Circular Buffers Base (CBBC) addresses 1292 * 1293 * Device has 16 base pointer registers, one for each of 16 host-DRAM-resident 1294 * circular buffers (CBs/queues) containing Transmit Frame Descriptors (TFDs) 1295 * (see struct iwm_tfd_frame). These 16 pointer registers are offset by 0x04 1296 * bytes from one another. Each TFD circular buffer in DRAM must be 256-byte 1297 * aligned (address bits 0-7 must be 0). 1298 * Later devices have 20 (5000 series) or 30 (higher) queues, but the registers 1299 * for them are in different places. 1300 * 1301 * Bit fields in each pointer register: 1302 * 27-0: TFD CB physical base address [35:8], must be 256-byte aligned 1303 */ 1304 #define IWM_FH_MEM_CBBC_0_15_LOWER_BOUND (IWM_FH_MEM_LOWER_BOUND + 0x9D0) 1305 #define IWM_FH_MEM_CBBC_0_15_UPPER_BOUN (IWM_FH_MEM_LOWER_BOUND + 0xA10) 1306 #define IWM_FH_MEM_CBBC_16_19_LOWER_BOUND (IWM_FH_MEM_LOWER_BOUND + 0xBF0) 1307 #define IWM_FH_MEM_CBBC_16_19_UPPER_BOUND (IWM_FH_MEM_LOWER_BOUND + 0xC00) 1308 #define IWM_FH_MEM_CBBC_20_31_LOWER_BOUND (IWM_FH_MEM_LOWER_BOUND + 0xB20) 1309 #define IWM_FH_MEM_CBBC_20_31_UPPER_BOUND (IWM_FH_MEM_LOWER_BOUND + 0xB80) 1310 1311 /* Find TFD CB base pointer for given queue */ 1312 static inline unsigned int IWM_FH_MEM_CBBC_QUEUE(unsigned int chnl) 1313 { 1314 if (chnl < 16) 1315 return IWM_FH_MEM_CBBC_0_15_LOWER_BOUND + 4 * chnl; 1316 if (chnl < 20) 1317 return IWM_FH_MEM_CBBC_16_19_LOWER_BOUND + 4 * (chnl - 16); 1318 return IWM_FH_MEM_CBBC_20_31_LOWER_BOUND + 4 * (chnl - 20); 1319 } 1320 1321 1322 /** 1323 * Rx SRAM Control and Status Registers (RSCSR) 1324 * 1325 * These registers provide handshake between driver and device for the Rx queue 1326 * (this queue handles *all* command responses, notifications, Rx data, etc. 1327 * sent from uCode to host driver). Unlike Tx, there is only one Rx 1328 * queue, and only one Rx DMA/FIFO channel. Also unlike Tx, which can 1329 * concatenate up to 20 DRAM buffers to form a Tx frame, each Receive Buffer 1330 * Descriptor (RBD) points to only one Rx Buffer (RB); there is a 1:1 1331 * mapping between RBDs and RBs. 1332 * 1333 * Driver must allocate host DRAM memory for the following, and set the 1334 * physical address of each into device registers: 1335 * 1336 * 1) Receive Buffer Descriptor (RBD) circular buffer (CB), typically with 256 1337 * entries (although any power of 2, up to 4096, is selectable by driver). 1338 * Each entry (1 dword) points to a receive buffer (RB) of consistent size 1339 * (typically 4K, although 8K or 16K are also selectable by driver). 1340 * Driver sets up RB size and number of RBDs in the CB via Rx config 1341 * register IWM_FH_MEM_RCSR_CHNL0_CONFIG_REG. 1342 * 1343 * Bit fields within one RBD: 1344 * 27-0: Receive Buffer physical address bits [35:8], 256-byte aligned 1345 * 1346 * Driver sets physical address [35:8] of base of RBD circular buffer 1347 * into IWM_FH_RSCSR_CHNL0_RBDCB_BASE_REG [27:0]. 1348 * 1349 * 2) Rx status buffer, 8 bytes, in which uCode indicates which Rx Buffers 1350 * (RBs) have been filled, via a "write pointer", actually the index of 1351 * the RB's corresponding RBD within the circular buffer. Driver sets 1352 * physical address [35:4] into IWM_FH_RSCSR_CHNL0_STTS_WPTR_REG [31:0]. 1353 * 1354 * Bit fields in lower dword of Rx status buffer (upper dword not used 1355 * by driver: 1356 * 31-12: Not used by driver 1357 * 11- 0: Index of last filled Rx buffer descriptor 1358 * (device writes, driver reads this value) 1359 * 1360 * As the driver prepares Receive Buffers (RBs) for device to fill, driver must 1361 * enter pointers to these RBs into contiguous RBD circular buffer entries, 1362 * and update the device's "write" index register, 1363 * IWM_FH_RSCSR_CHNL0_RBDCB_WPTR_REG. 1364 * 1365 * This "write" index corresponds to the *next* RBD that the driver will make 1366 * available, i.e. one RBD past the tail of the ready-to-fill RBDs within 1367 * the circular buffer. This value should initially be 0 (before preparing any 1368 * RBs), should be 8 after preparing the first 8 RBs (for example), and must 1369 * wrap back to 0 at the end of the circular buffer (but don't wrap before 1370 * "read" index has advanced past 1! See below). 1371 * NOTE: DEVICE EXPECTS THE WRITE INDEX TO BE INCREMENTED IN MULTIPLES OF 8. 1372 * 1373 * As the device fills RBs (referenced from contiguous RBDs within the circular 1374 * buffer), it updates the Rx status buffer in host DRAM, 2) described above, 1375 * to tell the driver the index of the latest filled RBD. The driver must 1376 * read this "read" index from DRAM after receiving an Rx interrupt from device 1377 * 1378 * The driver must also internally keep track of a third index, which is the 1379 * next RBD to process. When receiving an Rx interrupt, driver should process 1380 * all filled but unprocessed RBs up to, but not including, the RB 1381 * corresponding to the "read" index. For example, if "read" index becomes "1", 1382 * driver may process the RB pointed to by RBD 0. Depending on volume of 1383 * traffic, there may be many RBs to process. 1384 * 1385 * If read index == write index, device thinks there is no room to put new data. 1386 * Due to this, the maximum number of filled RBs is 255, instead of 256. To 1387 * be safe, make sure that there is a gap of at least 2 RBDs between "write" 1388 * and "read" indexes; that is, make sure that there are no more than 254 1389 * buffers waiting to be filled. 1390 */ 1391 #define IWM_FH_MEM_RSCSR_LOWER_BOUND (IWM_FH_MEM_LOWER_BOUND + 0xBC0) 1392 #define IWM_FH_MEM_RSCSR_UPPER_BOUND (IWM_FH_MEM_LOWER_BOUND + 0xC00) 1393 #define IWM_FH_MEM_RSCSR_CHNL0 (IWM_FH_MEM_RSCSR_LOWER_BOUND) 1394 1395 /** 1396 * Physical base address of 8-byte Rx Status buffer. 1397 * Bit fields: 1398 * 31-0: Rx status buffer physical base address [35:4], must 16-byte aligned. 1399 */ 1400 #define IWM_FH_RSCSR_CHNL0_STTS_WPTR_REG (IWM_FH_MEM_RSCSR_CHNL0) 1401 1402 /** 1403 * Physical base address of Rx Buffer Descriptor Circular Buffer. 1404 * Bit fields: 1405 * 27-0: RBD CD physical base address [35:8], must be 256-byte aligned. 1406 */ 1407 #define IWM_FH_RSCSR_CHNL0_RBDCB_BASE_REG (IWM_FH_MEM_RSCSR_CHNL0 + 0x004) 1408 1409 /** 1410 * Rx write pointer (index, really!). 1411 * Bit fields: 1412 * 11-0: Index of driver's most recent prepared-to-be-filled RBD, + 1. 1413 * NOTE: For 256-entry circular buffer, use only bits [7:0]. 1414 */ 1415 #define IWM_FH_RSCSR_CHNL0_RBDCB_WPTR_REG (IWM_FH_MEM_RSCSR_CHNL0 + 0x008) 1416 #define IWM_FH_RSCSR_CHNL0_WPTR (IWM_FH_RSCSR_CHNL0_RBDCB_WPTR_REG) 1417 1418 #define IWM_FW_RSCSR_CHNL0_RXDCB_RDPTR_REG (IWM_FH_MEM_RSCSR_CHNL0 + 0x00c) 1419 #define IWM_FH_RSCSR_CHNL0_RDPTR IWM_FW_RSCSR_CHNL0_RXDCB_RDPTR_REG 1420 1421 /** 1422 * Rx Config/Status Registers (RCSR) 1423 * Rx Config Reg for channel 0 (only channel used) 1424 * 1425 * Driver must initialize IWM_FH_MEM_RCSR_CHNL0_CONFIG_REG as follows for 1426 * normal operation (see bit fields). 1427 * 1428 * Clearing IWM_FH_MEM_RCSR_CHNL0_CONFIG_REG to 0 turns off Rx DMA. 1429 * Driver should poll IWM_FH_MEM_RSSR_RX_STATUS_REG for 1430 * IWM_FH_RSSR_CHNL0_RX_STATUS_CHNL_IDLE (bit 24) before continuing. 1431 * 1432 * Bit fields: 1433 * 31-30: Rx DMA channel enable: '00' off/pause, '01' pause at end of frame, 1434 * '10' operate normally 1435 * 29-24: reserved 1436 * 23-20: # RBDs in circular buffer = 2^value; use "8" for 256 RBDs (normal), 1437 * min "5" for 32 RBDs, max "12" for 4096 RBDs. 1438 * 19-18: reserved 1439 * 17-16: size of each receive buffer; '00' 4K (normal), '01' 8K, 1440 * '10' 12K, '11' 16K. 1441 * 15-14: reserved 1442 * 13-12: IRQ destination; '00' none, '01' host driver (normal operation) 1443 * 11- 4: timeout for closing Rx buffer and interrupting host (units 32 usec) 1444 * typical value 0x10 (about 1/2 msec) 1445 * 3- 0: reserved 1446 */ 1447 #define IWM_FH_MEM_RCSR_LOWER_BOUND (IWM_FH_MEM_LOWER_BOUND + 0xC00) 1448 #define IWM_FH_MEM_RCSR_UPPER_BOUND (IWM_FH_MEM_LOWER_BOUND + 0xCC0) 1449 #define IWM_FH_MEM_RCSR_CHNL0 (IWM_FH_MEM_RCSR_LOWER_BOUND) 1450 1451 #define IWM_FH_MEM_RCSR_CHNL0_CONFIG_REG (IWM_FH_MEM_RCSR_CHNL0) 1452 #define IWM_FH_MEM_RCSR_CHNL0_RBDCB_WPTR (IWM_FH_MEM_RCSR_CHNL0 + 0x8) 1453 #define IWM_FH_MEM_RCSR_CHNL0_FLUSH_RB_REQ (IWM_FH_MEM_RCSR_CHNL0 + 0x10) 1454 1455 #define IWM_FH_RCSR_CHNL0_RX_CONFIG_RB_TIMEOUT_MSK (0x00000FF0) /* bits 4-11 */ 1456 #define IWM_FH_RCSR_CHNL0_RX_CONFIG_IRQ_DEST_MSK (0x00001000) /* bits 12 */ 1457 #define IWM_FH_RCSR_CHNL0_RX_CONFIG_SINGLE_FRAME_MSK (0x00008000) /* bit 15 */ 1458 #define IWM_FH_RCSR_CHNL0_RX_CONFIG_RB_SIZE_MSK (0x00030000) /* bits 16-17 */ 1459 #define IWM_FH_RCSR_CHNL0_RX_CONFIG_RBDBC_SIZE_MSK (0x00F00000) /* bits 20-23 */ 1460 #define IWM_FH_RCSR_CHNL0_RX_CONFIG_DMA_CHNL_EN_MSK (0xC0000000) /* bits 30-31*/ 1461 1462 #define IWM_FH_RCSR_RX_CONFIG_RBDCB_SIZE_POS (20) 1463 #define IWM_FH_RCSR_RX_CONFIG_REG_IRQ_RBTH_POS (4) 1464 #define IWM_RX_RB_TIMEOUT (0x11) 1465 1466 #define IWM_FH_RCSR_RX_CONFIG_CHNL_EN_PAUSE_VAL (0x00000000) 1467 #define IWM_FH_RCSR_RX_CONFIG_CHNL_EN_PAUSE_EOF_VAL (0x40000000) 1468 #define IWM_FH_RCSR_RX_CONFIG_CHNL_EN_ENABLE_VAL (0x80000000) 1469 1470 #define IWM_FH_RCSR_RX_CONFIG_REG_VAL_RB_SIZE_4K (0x00000000) 1471 #define IWM_FH_RCSR_RX_CONFIG_REG_VAL_RB_SIZE_8K (0x00010000) 1472 #define IWM_FH_RCSR_RX_CONFIG_REG_VAL_RB_SIZE_12K (0x00020000) 1473 #define IWM_FH_RCSR_RX_CONFIG_REG_VAL_RB_SIZE_16K (0x00030000) 1474 1475 #define IWM_FH_RCSR_CHNL0_RX_IGNORE_RXF_EMPTY (0x00000004) 1476 #define IWM_FH_RCSR_CHNL0_RX_CONFIG_IRQ_DEST_NO_INT_VAL (0x00000000) 1477 #define IWM_FH_RCSR_CHNL0_RX_CONFIG_IRQ_DEST_INT_HOST_VAL (0x00001000) 1478 1479 /** 1480 * Rx Shared Status Registers (RSSR) 1481 * 1482 * After stopping Rx DMA channel (writing 0 to 1483 * IWM_FH_MEM_RCSR_CHNL0_CONFIG_REG), driver must poll 1484 * IWM_FH_MEM_RSSR_RX_STATUS_REG until Rx channel is idle. 1485 * 1486 * Bit fields: 1487 * 24: 1 = Channel 0 is idle 1488 * 1489 * IWM_FH_MEM_RSSR_SHARED_CTRL_REG and IWM_FH_MEM_RSSR_RX_ENABLE_ERR_IRQ2DRV 1490 * contain default values that should not be altered by the driver. 1491 */ 1492 #define IWM_FH_MEM_RSSR_LOWER_BOUND (IWM_FH_MEM_LOWER_BOUND + 0xC40) 1493 #define IWM_FH_MEM_RSSR_UPPER_BOUND (IWM_FH_MEM_LOWER_BOUND + 0xD00) 1494 1495 #define IWM_FH_MEM_RSSR_SHARED_CTRL_REG (IWM_FH_MEM_RSSR_LOWER_BOUND) 1496 #define IWM_FH_MEM_RSSR_RX_STATUS_REG (IWM_FH_MEM_RSSR_LOWER_BOUND + 0x004) 1497 #define IWM_FH_MEM_RSSR_RX_ENABLE_ERR_IRQ2DRV\ 1498 (IWM_FH_MEM_RSSR_LOWER_BOUND + 0x008) 1499 1500 #define IWM_FH_RSSR_CHNL0_RX_STATUS_CHNL_IDLE (0x01000000) 1501 1502 #define IWM_FH_MEM_TFDIB_REG1_ADDR_BITSHIFT 28 1503 1504 /* TFDB Area - TFDs buffer table */ 1505 #define IWM_FH_MEM_TFDIB_DRAM_ADDR_LSB_MSK (0xFFFFFFFF) 1506 #define IWM_FH_TFDIB_LOWER_BOUND (IWM_FH_MEM_LOWER_BOUND + 0x900) 1507 #define IWM_FH_TFDIB_UPPER_BOUND (IWM_FH_MEM_LOWER_BOUND + 0x958) 1508 #define IWM_FH_TFDIB_CTRL0_REG(_chnl) (IWM_FH_TFDIB_LOWER_BOUND + 0x8 * (_chnl)) 1509 #define IWM_FH_TFDIB_CTRL1_REG(_chnl) (IWM_FH_TFDIB_LOWER_BOUND + 0x8 * (_chnl) + 0x4) 1510 1511 /** 1512 * Transmit DMA Channel Control/Status Registers (TCSR) 1513 * 1514 * Device has one configuration register for each of 8 Tx DMA/FIFO channels 1515 * supported in hardware (don't confuse these with the 16 Tx queues in DRAM, 1516 * which feed the DMA/FIFO channels); config regs are separated by 0x20 bytes. 1517 * 1518 * To use a Tx DMA channel, driver must initialize its 1519 * IWM_FH_TCSR_CHNL_TX_CONFIG_REG(chnl) with: 1520 * 1521 * IWM_FH_TCSR_TX_CONFIG_REG_VAL_DMA_CHNL_ENABLE | 1522 * IWM_FH_TCSR_TX_CONFIG_REG_VAL_DMA_CREDIT_ENABLE_VAL 1523 * 1524 * All other bits should be 0. 1525 * 1526 * Bit fields: 1527 * 31-30: Tx DMA channel enable: '00' off/pause, '01' pause at end of frame, 1528 * '10' operate normally 1529 * 29- 4: Reserved, set to "0" 1530 * 3: Enable internal DMA requests (1, normal operation), disable (0) 1531 * 2- 0: Reserved, set to "0" 1532 */ 1533 #define IWM_FH_TCSR_LOWER_BOUND (IWM_FH_MEM_LOWER_BOUND + 0xD00) 1534 #define IWM_FH_TCSR_UPPER_BOUND (IWM_FH_MEM_LOWER_BOUND + 0xE60) 1535 1536 /* Find Control/Status reg for given Tx DMA/FIFO channel */ 1537 #define IWM_FH_TCSR_CHNL_NUM (8) 1538 1539 /* TCSR: tx_config register values */ 1540 #define IWM_FH_TCSR_CHNL_TX_CONFIG_REG(_chnl) \ 1541 (IWM_FH_TCSR_LOWER_BOUND + 0x20 * (_chnl)) 1542 #define IWM_FH_TCSR_CHNL_TX_CREDIT_REG(_chnl) \ 1543 (IWM_FH_TCSR_LOWER_BOUND + 0x20 * (_chnl) + 0x4) 1544 #define IWM_FH_TCSR_CHNL_TX_BUF_STS_REG(_chnl) \ 1545 (IWM_FH_TCSR_LOWER_BOUND + 0x20 * (_chnl) + 0x8) 1546 1547 #define IWM_FH_TCSR_TX_CONFIG_REG_VAL_MSG_MODE_TXF (0x00000000) 1548 #define IWM_FH_TCSR_TX_CONFIG_REG_VAL_MSG_MODE_DRV (0x00000001) 1549 1550 #define IWM_FH_TCSR_TX_CONFIG_REG_VAL_DMA_CREDIT_DISABLE (0x00000000) 1551 #define IWM_FH_TCSR_TX_CONFIG_REG_VAL_DMA_CREDIT_ENABLE (0x00000008) 1552 1553 #define IWM_FH_TCSR_TX_CONFIG_REG_VAL_CIRQ_HOST_NOINT (0x00000000) 1554 #define IWM_FH_TCSR_TX_CONFIG_REG_VAL_CIRQ_HOST_ENDTFD (0x00100000) 1555 #define IWM_FH_TCSR_TX_CONFIG_REG_VAL_CIRQ_HOST_IFTFD (0x00200000) 1556 1557 #define IWM_FH_TCSR_TX_CONFIG_REG_VAL_CIRQ_RTC_NOINT (0x00000000) 1558 #define IWM_FH_TCSR_TX_CONFIG_REG_VAL_CIRQ_RTC_ENDTFD (0x00400000) 1559 #define IWM_FH_TCSR_TX_CONFIG_REG_VAL_CIRQ_RTC_IFTFD (0x00800000) 1560 1561 #define IWM_FH_TCSR_TX_CONFIG_REG_VAL_DMA_CHNL_PAUSE (0x00000000) 1562 #define IWM_FH_TCSR_TX_CONFIG_REG_VAL_DMA_CHNL_PAUSE_EOF (0x40000000) 1563 #define IWM_FH_TCSR_TX_CONFIG_REG_VAL_DMA_CHNL_ENABLE (0x80000000) 1564 1565 #define IWM_FH_TCSR_CHNL_TX_BUF_STS_REG_VAL_TFDB_EMPTY (0x00000000) 1566 #define IWM_FH_TCSR_CHNL_TX_BUF_STS_REG_VAL_TFDB_WAIT (0x00002000) 1567 #define IWM_FH_TCSR_CHNL_TX_BUF_STS_REG_VAL_TFDB_VALID (0x00000003) 1568 1569 #define IWM_FH_TCSR_CHNL_TX_BUF_STS_REG_POS_TB_NUM (20) 1570 #define IWM_FH_TCSR_CHNL_TX_BUF_STS_REG_POS_TB_IDX (12) 1571 1572 /** 1573 * Tx Shared Status Registers (TSSR) 1574 * 1575 * After stopping Tx DMA channel (writing 0 to 1576 * IWM_FH_TCSR_CHNL_TX_CONFIG_REG(chnl)), driver must poll 1577 * IWM_FH_TSSR_TX_STATUS_REG until selected Tx channel is idle 1578 * (channel's buffers empty | no pending requests). 1579 * 1580 * Bit fields: 1581 * 31-24: 1 = Channel buffers empty (channel 7:0) 1582 * 23-16: 1 = No pending requests (channel 7:0) 1583 */ 1584 #define IWM_FH_TSSR_LOWER_BOUND (IWM_FH_MEM_LOWER_BOUND + 0xEA0) 1585 #define IWM_FH_TSSR_UPPER_BOUND (IWM_FH_MEM_LOWER_BOUND + 0xEC0) 1586 1587 #define IWM_FH_TSSR_TX_STATUS_REG (IWM_FH_TSSR_LOWER_BOUND + 0x010) 1588 1589 /** 1590 * Bit fields for TSSR(Tx Shared Status & Control) error status register: 1591 * 31: Indicates an address error when accessed to internal memory 1592 * uCode/driver must write "1" in order to clear this flag 1593 * 30: Indicates that Host did not send the expected number of dwords to FH 1594 * uCode/driver must write "1" in order to clear this flag 1595 * 16-9:Each status bit is for one channel. Indicates that an (Error) ActDMA 1596 * command was received from the scheduler while the TRB was already full 1597 * with previous command 1598 * uCode/driver must write "1" in order to clear this flag 1599 * 7-0: Each status bit indicates a channel's TxCredit error. When an error 1600 * bit is set, it indicates that the FH has received a full indication 1601 * from the RTC TxFIFO and the current value of the TxCredit counter was 1602 * not equal to zero. This mean that the credit mechanism was not 1603 * synchronized to the TxFIFO status 1604 * uCode/driver must write "1" in order to clear this flag 1605 */ 1606 #define IWM_FH_TSSR_TX_ERROR_REG (IWM_FH_TSSR_LOWER_BOUND + 0x018) 1607 #define IWM_FH_TSSR_TX_MSG_CONFIG_REG (IWM_FH_TSSR_LOWER_BOUND + 0x008) 1608 1609 #define IWM_FH_TSSR_TX_STATUS_REG_MSK_CHNL_IDLE(_chnl) ((1 << (_chnl)) << 16) 1610 1611 /* Tx service channels */ 1612 #define IWM_FH_SRVC_CHNL (9) 1613 #define IWM_FH_SRVC_LOWER_BOUND (IWM_FH_MEM_LOWER_BOUND + 0x9C8) 1614 #define IWM_FH_SRVC_UPPER_BOUND (IWM_FH_MEM_LOWER_BOUND + 0x9D0) 1615 #define IWM_FH_SRVC_CHNL_SRAM_ADDR_REG(_chnl) \ 1616 (IWM_FH_SRVC_LOWER_BOUND + ((_chnl) - 9) * 0x4) 1617 1618 #define IWM_FH_TX_CHICKEN_BITS_REG (IWM_FH_MEM_LOWER_BOUND + 0xE98) 1619 #define IWM_FH_TX_TRB_REG(_chan) (IWM_FH_MEM_LOWER_BOUND + 0x958 + \ 1620 (_chan) * 4) 1621 1622 /* Instruct FH to increment the retry count of a packet when 1623 * it is brought from the memory to TX-FIFO 1624 */ 1625 #define IWM_FH_TX_CHICKEN_BITS_SCD_AUTO_RETRY_EN (0x00000002) 1626 1627 #define IWM_RX_QUEUE_SIZE 256 1628 #define IWM_RX_QUEUE_MASK 255 1629 #define IWM_RX_QUEUE_SIZE_LOG 8 1630 1631 /* 1632 * RX related structures and functions 1633 */ 1634 #define IWM_RX_FREE_BUFFERS 64 1635 #define IWM_RX_LOW_WATERMARK 8 1636 1637 /** 1638 * struct iwm_rb_status - reseve buffer status 1639 * host memory mapped FH registers 1640 * @closed_rb_num [0:11] - Indicates the index of the RB which was closed 1641 * @closed_fr_num [0:11] - Indicates the index of the RX Frame which was closed 1642 * @finished_rb_num [0:11] - Indicates the index of the current RB 1643 * in which the last frame was written to 1644 * @finished_fr_num [0:11] - Indicates the index of the RX Frame 1645 * which was transferred 1646 */ 1647 struct iwm_rb_status { 1648 uint16_t closed_rb_num; 1649 uint16_t closed_fr_num; 1650 uint16_t finished_rb_num; 1651 uint16_t finished_fr_nam; 1652 uint32_t unused; 1653 } __packed; 1654 1655 1656 #define IWM_TFD_QUEUE_SIZE_MAX (256) 1657 #define IWM_TFD_QUEUE_SIZE_BC_DUP (64) 1658 #define IWM_TFD_QUEUE_BC_SIZE (IWM_TFD_QUEUE_SIZE_MAX + \ 1659 IWM_TFD_QUEUE_SIZE_BC_DUP) 1660 #define IWM_TX_DMA_MASK DMA_BIT_MASK(36) 1661 #define IWM_NUM_OF_TBS 20 1662 1663 static inline uint8_t iwm_get_dma_hi_addr(bus_addr_t addr) 1664 { 1665 return (sizeof(addr) > sizeof(uint32_t) ? (addr >> 16) >> 16 : 0) & 0xF; 1666 } 1667 /** 1668 * struct iwm_tfd_tb transmit buffer descriptor within transmit frame descriptor 1669 * 1670 * This structure contains dma address and length of transmission address 1671 * 1672 * @lo: low [31:0] portion of the dma address of TX buffer 1673 * every even is unaligned on 16 bit boundary 1674 * @hi_n_len 0-3 [35:32] portion of dma 1675 * 4-15 length of the tx buffer 1676 */ 1677 struct iwm_tfd_tb { 1678 uint32_t lo; 1679 uint16_t hi_n_len; 1680 } __packed; 1681 1682 /** 1683 * struct iwm_tfd 1684 * 1685 * Transmit Frame Descriptor (TFD) 1686 * 1687 * @ __reserved1[3] reserved 1688 * @ num_tbs 0-4 number of active tbs 1689 * 5 reserved 1690 * 6-7 padding (not used) 1691 * @ tbs[20] transmit frame buffer descriptors 1692 * @ __pad padding 1693 * 1694 * Each Tx queue uses a circular buffer of 256 TFDs stored in host DRAM. 1695 * Both driver and device share these circular buffers, each of which must be 1696 * contiguous 256 TFDs x 128 bytes-per-TFD = 32 KBytes 1697 * 1698 * Driver must indicate the physical address of the base of each 1699 * circular buffer via the IWM_FH_MEM_CBBC_QUEUE registers. 1700 * 1701 * Each TFD contains pointer/size information for up to 20 data buffers 1702 * in host DRAM. These buffers collectively contain the (one) frame described 1703 * by the TFD. Each buffer must be a single contiguous block of memory within 1704 * itself, but buffers may be scattered in host DRAM. Each buffer has max size 1705 * of (4K - 4). The concatenates all of a TFD's buffers into a single 1706 * Tx frame, up to 8 KBytes in size. 1707 * 1708 * A maximum of 255 (not 256!) TFDs may be on a queue waiting for Tx. 1709 */ 1710 struct iwm_tfd { 1711 uint8_t __reserved1[3]; 1712 uint8_t num_tbs; 1713 struct iwm_tfd_tb tbs[IWM_NUM_OF_TBS]; 1714 uint32_t __pad; 1715 } __packed; 1716 1717 /* Keep Warm Size */ 1718 #define IWM_KW_SIZE 0x1000 /* 4k */ 1719 1720 /* Fixed (non-configurable) rx data from phy */ 1721 1722 /** 1723 * struct iwm_agn_schedq_bc_tbl scheduler byte count table 1724 * base physical address provided by IWM_SCD_DRAM_BASE_ADDR 1725 * @tfd_offset 0-12 - tx command byte count 1726 * 12-16 - station index 1727 */ 1728 struct iwm_agn_scd_bc_tbl { 1729 uint16_t tfd_offset[IWM_TFD_QUEUE_BC_SIZE]; 1730 } __packed; 1731 1732 /* 1733 * END iwl-fh.h 1734 */ 1735 1736 /* 1737 * BEGIN mvm/fw-api.h 1738 */ 1739 1740 /* Maximum number of Tx queues. */ 1741 #define IWM_MVM_MAX_QUEUES 31 1742 1743 /* Tx queue numbers */ 1744 enum { 1745 IWM_MVM_OFFCHANNEL_QUEUE = 8, 1746 IWM_MVM_CMD_QUEUE = 9, 1747 IWM_MVM_AUX_QUEUE = 15, 1748 }; 1749 1750 enum iwm_mvm_tx_fifo { 1751 IWM_MVM_TX_FIFO_BK = 0, 1752 IWM_MVM_TX_FIFO_BE, 1753 IWM_MVM_TX_FIFO_VI, 1754 IWM_MVM_TX_FIFO_VO, 1755 IWM_MVM_TX_FIFO_MCAST = 5, 1756 IWM_MVM_TX_FIFO_CMD = 7, 1757 }; 1758 1759 #define IWM_MVM_STATION_COUNT 16 1760 1761 /* commands */ 1762 enum { 1763 IWM_MVM_ALIVE = 0x1, 1764 IWM_REPLY_ERROR = 0x2, 1765 1766 IWM_INIT_COMPLETE_NOTIF = 0x4, 1767 1768 /* PHY context commands */ 1769 IWM_PHY_CONTEXT_CMD = 0x8, 1770 IWM_DBG_CFG = 0x9, 1771 1772 /* UMAC scan commands */ 1773 IWM_SCAN_ITERATION_COMPLETE_UMAC = 0xb5, 1774 IWM_SCAN_CFG_CMD = 0xc, 1775 IWM_SCAN_REQ_UMAC = 0xd, 1776 IWM_SCAN_ABORT_UMAC = 0xe, 1777 IWM_SCAN_COMPLETE_UMAC = 0xf, 1778 1779 /* station table */ 1780 IWM_ADD_STA_KEY = 0x17, 1781 IWM_ADD_STA = 0x18, 1782 IWM_REMOVE_STA = 0x19, 1783 1784 /* TX */ 1785 IWM_TX_CMD = 0x1c, 1786 IWM_TXPATH_FLUSH = 0x1e, 1787 IWM_MGMT_MCAST_KEY = 0x1f, 1788 1789 /* scheduler config */ 1790 IWM_SCD_QUEUE_CFG = 0x1d, 1791 1792 /* global key */ 1793 IWM_WEP_KEY = 0x20, 1794 1795 /* MAC and Binding commands */ 1796 IWM_MAC_CONTEXT_CMD = 0x28, 1797 IWM_TIME_EVENT_CMD = 0x29, /* both CMD and response */ 1798 IWM_TIME_EVENT_NOTIFICATION = 0x2a, 1799 IWM_BINDING_CONTEXT_CMD = 0x2b, 1800 IWM_TIME_QUOTA_CMD = 0x2c, 1801 IWM_NON_QOS_TX_COUNTER_CMD = 0x2d, 1802 1803 IWM_LQ_CMD = 0x4e, 1804 1805 /* paging block to FW cpu2 */ 1806 IWM_FW_PAGING_BLOCK_CMD = 0x4f, 1807 1808 /* Scan offload */ 1809 IWM_SCAN_OFFLOAD_REQUEST_CMD = 0x51, 1810 IWM_SCAN_OFFLOAD_ABORT_CMD = 0x52, 1811 IWM_HOT_SPOT_CMD = 0x53, 1812 IWM_SCAN_OFFLOAD_COMPLETE = 0x6d, 1813 IWM_SCAN_OFFLOAD_UPDATE_PROFILES_CMD = 0x6e, 1814 IWM_SCAN_OFFLOAD_CONFIG_CMD = 0x6f, 1815 IWM_MATCH_FOUND_NOTIFICATION = 0xd9, 1816 IWM_SCAN_ITERATION_COMPLETE = 0xe7, 1817 1818 /* Phy */ 1819 IWM_PHY_CONFIGURATION_CMD = 0x6a, 1820 IWM_CALIB_RES_NOTIF_PHY_DB = 0x6b, 1821 /* IWM_PHY_DB_CMD = 0x6c, */ 1822 1823 /* Power - legacy power table command */ 1824 IWM_POWER_TABLE_CMD = 0x77, 1825 IWM_PSM_UAPSD_AP_MISBEHAVING_NOTIFICATION = 0x78, 1826 1827 /* Thermal Throttling*/ 1828 IWM_REPLY_THERMAL_MNG_BACKOFF = 0x7e, 1829 1830 /* Scanning */ 1831 IWM_SCAN_ABORT_CMD = 0x81, 1832 IWM_SCAN_START_NOTIFICATION = 0x82, 1833 IWM_SCAN_RESULTS_NOTIFICATION = 0x83, 1834 1835 /* NVM */ 1836 IWM_NVM_ACCESS_CMD = 0x88, 1837 1838 IWM_SET_CALIB_DEFAULT_CMD = 0x8e, 1839 1840 IWM_BEACON_NOTIFICATION = 0x90, 1841 IWM_BEACON_TEMPLATE_CMD = 0x91, 1842 IWM_TX_ANT_CONFIGURATION_CMD = 0x98, 1843 IWM_BT_CONFIG = 0x9b, 1844 IWM_STATISTICS_NOTIFICATION = 0x9d, 1845 IWM_REDUCE_TX_POWER_CMD = 0x9f, 1846 1847 /* RF-KILL commands and notifications */ 1848 IWM_CARD_STATE_CMD = 0xa0, 1849 IWM_CARD_STATE_NOTIFICATION = 0xa1, 1850 1851 IWM_MISSED_BEACONS_NOTIFICATION = 0xa2, 1852 1853 IWM_MFUART_LOAD_NOTIFICATION = 0xb1, 1854 1855 /* Power - new power table command */ 1856 IWM_MAC_PM_POWER_TABLE = 0xa9, 1857 1858 IWM_REPLY_RX_PHY_CMD = 0xc0, 1859 IWM_REPLY_RX_MPDU_CMD = 0xc1, 1860 IWM_BA_NOTIF = 0xc5, 1861 1862 /* Location Aware Regulatory */ 1863 IWM_MCC_UPDATE_CMD = 0xc8, 1864 IWM_MCC_CHUB_UPDATE_CMD = 0xc9, 1865 1866 /* BT Coex */ 1867 IWM_BT_COEX_PRIO_TABLE = 0xcc, 1868 IWM_BT_COEX_PROT_ENV = 0xcd, 1869 IWM_BT_PROFILE_NOTIFICATION = 0xce, 1870 IWM_BT_COEX_CI = 0x5d, 1871 1872 IWM_REPLY_SF_CFG_CMD = 0xd1, 1873 IWM_REPLY_BEACON_FILTERING_CMD = 0xd2, 1874 1875 /* DTS measurements */ 1876 IWM_CMD_DTS_MEASUREMENT_TRIGGER = 0xdc, 1877 IWM_DTS_MEASUREMENT_NOTIFICATION = 0xdd, 1878 1879 IWM_REPLY_DEBUG_CMD = 0xf0, 1880 IWM_DEBUG_LOG_MSG = 0xf7, 1881 1882 IWM_MCAST_FILTER_CMD = 0xd0, 1883 1884 /* D3 commands/notifications */ 1885 IWM_D3_CONFIG_CMD = 0xd3, 1886 IWM_PROT_OFFLOAD_CONFIG_CMD = 0xd4, 1887 IWM_OFFLOADS_QUERY_CMD = 0xd5, 1888 IWM_REMOTE_WAKE_CONFIG_CMD = 0xd6, 1889 1890 /* for WoWLAN in particular */ 1891 IWM_WOWLAN_PATTERNS = 0xe0, 1892 IWM_WOWLAN_CONFIGURATION = 0xe1, 1893 IWM_WOWLAN_TSC_RSC_PARAM = 0xe2, 1894 IWM_WOWLAN_TKIP_PARAM = 0xe3, 1895 IWM_WOWLAN_KEK_KCK_MATERIAL = 0xe4, 1896 IWM_WOWLAN_GET_STATUSES = 0xe5, 1897 IWM_WOWLAN_TX_POWER_PER_DB = 0xe6, 1898 1899 /* and for NetDetect */ 1900 IWM_NET_DETECT_CONFIG_CMD = 0x54, 1901 IWM_NET_DETECT_PROFILES_QUERY_CMD = 0x56, 1902 IWM_NET_DETECT_PROFILES_CMD = 0x57, 1903 IWM_NET_DETECT_HOTSPOTS_CMD = 0x58, 1904 IWM_NET_DETECT_HOTSPOTS_QUERY_CMD = 0x59, 1905 1906 IWM_REPLY_MAX = 0xff, 1907 }; 1908 1909 enum iwm_phy_ops_subcmd_ids { 1910 IWM_CMD_DTS_MEASUREMENT_TRIGGER_WIDE = 0x0, 1911 IWM_CTDP_CONFIG_CMD = 0x03, 1912 IWM_TEMP_REPORTING_THRESHOLDS_CMD = 0x04, 1913 IWM_CT_KILL_NOTIFICATION = 0xFE, 1914 IWM_DTS_MEASUREMENT_NOTIF_WIDE = 0xFF, 1915 }; 1916 1917 /* command groups */ 1918 enum { 1919 IWM_LEGACY_GROUP = 0x0, 1920 IWM_LONG_GROUP = 0x1, 1921 IWM_SYSTEM_GROUP = 0x2, 1922 IWM_MAC_CONF_GROUP = 0x3, 1923 IWM_PHY_OPS_GROUP = 0x4, 1924 IWM_DATA_PATH_GROUP = 0x5, 1925 IWM_PROT_OFFLOAD_GROUP = 0xb, 1926 }; 1927 1928 /** 1929 * struct iwm_cmd_response - generic response struct for most commands 1930 * @status: status of the command asked, changes for each one 1931 */ 1932 struct iwm_cmd_response { 1933 uint32_t status; 1934 }; 1935 1936 /* 1937 * struct iwm_tx_ant_cfg_cmd 1938 * @valid: valid antenna configuration 1939 */ 1940 struct iwm_tx_ant_cfg_cmd { 1941 uint32_t valid; 1942 } __packed; 1943 1944 /** 1945 * struct iwm_reduce_tx_power_cmd - TX power reduction command 1946 * IWM_REDUCE_TX_POWER_CMD = 0x9f 1947 * @flags: (reserved for future implementation) 1948 * @mac_context_id: id of the mac ctx for which we are reducing TX power. 1949 * @pwr_restriction: TX power restriction in dBms. 1950 */ 1951 struct iwm_reduce_tx_power_cmd { 1952 uint8_t flags; 1953 uint8_t mac_context_id; 1954 uint16_t pwr_restriction; 1955 } __packed; /* IWM_TX_REDUCED_POWER_API_S_VER_1 */ 1956 1957 /* 1958 * Calibration control struct. 1959 * Sent as part of the phy configuration command. 1960 * @flow_trigger: bitmap for which calibrations to perform according to 1961 * flow triggers. 1962 * @event_trigger: bitmap for which calibrations to perform according to 1963 * event triggers. 1964 */ 1965 struct iwm_calib_ctrl { 1966 uint32_t flow_trigger; 1967 uint32_t event_trigger; 1968 } __packed; 1969 1970 /* This enum defines the bitmap of various calibrations to enable in both 1971 * init ucode and runtime ucode through IWM_CALIBRATION_CFG_CMD. 1972 */ 1973 enum iwm_calib_cfg { 1974 IWM_CALIB_CFG_XTAL_IDX = (1 << 0), 1975 IWM_CALIB_CFG_TEMPERATURE_IDX = (1 << 1), 1976 IWM_CALIB_CFG_VOLTAGE_READ_IDX = (1 << 2), 1977 IWM_CALIB_CFG_PAPD_IDX = (1 << 3), 1978 IWM_CALIB_CFG_TX_PWR_IDX = (1 << 4), 1979 IWM_CALIB_CFG_DC_IDX = (1 << 5), 1980 IWM_CALIB_CFG_BB_FILTER_IDX = (1 << 6), 1981 IWM_CALIB_CFG_LO_LEAKAGE_IDX = (1 << 7), 1982 IWM_CALIB_CFG_TX_IQ_IDX = (1 << 8), 1983 IWM_CALIB_CFG_TX_IQ_SKEW_IDX = (1 << 9), 1984 IWM_CALIB_CFG_RX_IQ_IDX = (1 << 10), 1985 IWM_CALIB_CFG_RX_IQ_SKEW_IDX = (1 << 11), 1986 IWM_CALIB_CFG_SENSITIVITY_IDX = (1 << 12), 1987 IWM_CALIB_CFG_CHAIN_NOISE_IDX = (1 << 13), 1988 IWM_CALIB_CFG_DISCONNECTED_ANT_IDX = (1 << 14), 1989 IWM_CALIB_CFG_ANT_COUPLING_IDX = (1 << 15), 1990 IWM_CALIB_CFG_DAC_IDX = (1 << 16), 1991 IWM_CALIB_CFG_ABS_IDX = (1 << 17), 1992 IWM_CALIB_CFG_AGC_IDX = (1 << 18), 1993 }; 1994 1995 /* 1996 * Phy configuration command. 1997 */ 1998 struct iwm_phy_cfg_cmd { 1999 uint32_t phy_cfg; 2000 struct iwm_calib_ctrl calib_control; 2001 } __packed; 2002 2003 #define IWM_PHY_CFG_RADIO_TYPE ((1 << 0) | (1 << 1)) 2004 #define IWM_PHY_CFG_RADIO_STEP ((1 << 2) | (1 << 3)) 2005 #define IWM_PHY_CFG_RADIO_DASH ((1 << 4) | (1 << 5)) 2006 #define IWM_PHY_CFG_PRODUCT_NUMBER ((1 << 6) | (1 << 7)) 2007 #define IWM_PHY_CFG_TX_CHAIN_A (1 << 8) 2008 #define IWM_PHY_CFG_TX_CHAIN_B (1 << 9) 2009 #define IWM_PHY_CFG_TX_CHAIN_C (1 << 10) 2010 #define IWM_PHY_CFG_RX_CHAIN_A (1 << 12) 2011 #define IWM_PHY_CFG_RX_CHAIN_B (1 << 13) 2012 #define IWM_PHY_CFG_RX_CHAIN_C (1 << 14) 2013 2014 2015 /* Target of the IWM_NVM_ACCESS_CMD */ 2016 enum { 2017 IWM_NVM_ACCESS_TARGET_CACHE = 0, 2018 IWM_NVM_ACCESS_TARGET_OTP = 1, 2019 IWM_NVM_ACCESS_TARGET_EEPROM = 2, 2020 }; 2021 2022 /* Section types for IWM_NVM_ACCESS_CMD */ 2023 enum { 2024 IWM_NVM_SECTION_TYPE_SW = 1, 2025 IWM_NVM_SECTION_TYPE_REGULATORY = 3, 2026 IWM_NVM_SECTION_TYPE_CALIBRATION = 4, 2027 IWM_NVM_SECTION_TYPE_PRODUCTION = 5, 2028 IWM_NVM_SECTION_TYPE_MAC_OVERRIDE = 11, 2029 IWM_NVM_SECTION_TYPE_PHY_SKU = 12, 2030 IWM_NVM_MAX_NUM_SECTIONS = 13, 2031 }; 2032 2033 /** 2034 * struct iwm_nvm_access_cmd_ver2 - Request the device to send an NVM section 2035 * @op_code: 0 - read, 1 - write 2036 * @target: IWM_NVM_ACCESS_TARGET_* 2037 * @type: IWM_NVM_SECTION_TYPE_* 2038 * @offset: offset in bytes into the section 2039 * @length: in bytes, to read/write 2040 * @data: if write operation, the data to write. On read its empty 2041 */ 2042 struct iwm_nvm_access_cmd { 2043 uint8_t op_code; 2044 uint8_t target; 2045 uint16_t type; 2046 uint16_t offset; 2047 uint16_t length; 2048 uint8_t data[]; 2049 } __packed; /* IWM_NVM_ACCESS_CMD_API_S_VER_2 */ 2050 2051 #define IWM_NUM_OF_FW_PAGING_BLOCKS 33 /* 32 for data and 1 block for CSS */ 2052 2053 /* 2054 * struct iwm_fw_paging_cmd - paging layout 2055 * 2056 * (IWM_FW_PAGING_BLOCK_CMD = 0x4f) 2057 * 2058 * Send to FW the paging layout in the driver. 2059 * 2060 * @flags: various flags for the command 2061 * @block_size: the block size in powers of 2 2062 * @block_num: number of blocks specified in the command. 2063 * @device_phy_addr: virtual addresses from device side 2064 */ 2065 struct iwm_fw_paging_cmd { 2066 uint32_t flags; 2067 uint32_t block_size; 2068 uint32_t block_num; 2069 uint32_t device_phy_addr[IWM_NUM_OF_FW_PAGING_BLOCKS]; 2070 } __packed; /* IWM_FW_PAGING_BLOCK_CMD_API_S_VER_1 */ 2071 2072 /* 2073 * Fw items ID's 2074 * 2075 * @IWM_FW_ITEM_ID_PAGING: Address of the pages that the FW will upload 2076 * download 2077 */ 2078 enum iwm_fw_item_id { 2079 IWM_FW_ITEM_ID_PAGING = 3, 2080 }; 2081 2082 /* 2083 * struct iwm_fw_get_item_cmd - get an item from the fw 2084 */ 2085 struct iwm_fw_get_item_cmd { 2086 uint32_t item_id; 2087 } __packed; /* IWM_FW_GET_ITEM_CMD_API_S_VER_1 */ 2088 2089 /** 2090 * struct iwm_nvm_access_resp_ver2 - response to IWM_NVM_ACCESS_CMD 2091 * @offset: offset in bytes into the section 2092 * @length: in bytes, either how much was written or read 2093 * @type: IWM_NVM_SECTION_TYPE_* 2094 * @status: 0 for success, fail otherwise 2095 * @data: if read operation, the data returned. Empty on write. 2096 */ 2097 struct iwm_nvm_access_resp { 2098 uint16_t offset; 2099 uint16_t length; 2100 uint16_t type; 2101 uint16_t status; 2102 uint8_t data[]; 2103 } __packed; /* IWM_NVM_ACCESS_CMD_RESP_API_S_VER_2 */ 2104 2105 /* IWM_MVM_ALIVE 0x1 */ 2106 2107 /* alive response is_valid values */ 2108 #define IWM_ALIVE_RESP_UCODE_OK (1 << 0) 2109 #define IWM_ALIVE_RESP_RFKILL (1 << 1) 2110 2111 /* alive response ver_type values */ 2112 enum { 2113 IWM_FW_TYPE_HW = 0, 2114 IWM_FW_TYPE_PROT = 1, 2115 IWM_FW_TYPE_AP = 2, 2116 IWM_FW_TYPE_WOWLAN = 3, 2117 IWM_FW_TYPE_TIMING = 4, 2118 IWM_FW_TYPE_WIPAN = 5 2119 }; 2120 2121 /* alive response ver_subtype values */ 2122 enum { 2123 IWM_FW_SUBTYPE_FULL_FEATURE = 0, 2124 IWM_FW_SUBTYPE_BOOTSRAP = 1, /* Not valid */ 2125 IWM_FW_SUBTYPE_REDUCED = 2, 2126 IWM_FW_SUBTYPE_ALIVE_ONLY = 3, 2127 IWM_FW_SUBTYPE_WOWLAN = 4, 2128 IWM_FW_SUBTYPE_AP_SUBTYPE = 5, 2129 IWM_FW_SUBTYPE_WIPAN = 6, 2130 IWM_FW_SUBTYPE_INITIALIZE = 9 2131 }; 2132 2133 #define IWM_ALIVE_STATUS_ERR 0xDEAD 2134 #define IWM_ALIVE_STATUS_OK 0xCAFE 2135 2136 #define IWM_ALIVE_FLG_RFKILL (1 << 0) 2137 2138 struct iwm_mvm_alive_resp_ver1 { 2139 uint16_t status; 2140 uint16_t flags; 2141 uint8_t ucode_minor; 2142 uint8_t ucode_major; 2143 uint16_t id; 2144 uint8_t api_minor; 2145 uint8_t api_major; 2146 uint8_t ver_subtype; 2147 uint8_t ver_type; 2148 uint8_t mac; 2149 uint8_t opt; 2150 uint16_t reserved2; 2151 uint32_t timestamp; 2152 uint32_t error_event_table_ptr; /* SRAM address for error log */ 2153 uint32_t log_event_table_ptr; /* SRAM address for event log */ 2154 uint32_t cpu_register_ptr; 2155 uint32_t dbgm_config_ptr; 2156 uint32_t alive_counter_ptr; 2157 uint32_t scd_base_ptr; /* SRAM address for SCD */ 2158 } __packed; /* IWM_ALIVE_RES_API_S_VER_1 */ 2159 2160 struct iwm_mvm_alive_resp_ver2 { 2161 uint16_t status; 2162 uint16_t flags; 2163 uint8_t ucode_minor; 2164 uint8_t ucode_major; 2165 uint16_t id; 2166 uint8_t api_minor; 2167 uint8_t api_major; 2168 uint8_t ver_subtype; 2169 uint8_t ver_type; 2170 uint8_t mac; 2171 uint8_t opt; 2172 uint16_t reserved2; 2173 uint32_t timestamp; 2174 uint32_t error_event_table_ptr; /* SRAM address for error log */ 2175 uint32_t log_event_table_ptr; /* SRAM address for LMAC event log */ 2176 uint32_t cpu_register_ptr; 2177 uint32_t dbgm_config_ptr; 2178 uint32_t alive_counter_ptr; 2179 uint32_t scd_base_ptr; /* SRAM address for SCD */ 2180 uint32_t st_fwrd_addr; /* pointer to Store and forward */ 2181 uint32_t st_fwrd_size; 2182 uint8_t umac_minor; /* UMAC version: minor */ 2183 uint8_t umac_major; /* UMAC version: major */ 2184 uint16_t umac_id; /* UMAC version: id */ 2185 uint32_t error_info_addr; /* SRAM address for UMAC error log */ 2186 uint32_t dbg_print_buff_addr; 2187 } __packed; /* ALIVE_RES_API_S_VER_2 */ 2188 2189 struct iwm_mvm_alive_resp { 2190 uint16_t status; 2191 uint16_t flags; 2192 uint32_t ucode_minor; 2193 uint32_t ucode_major; 2194 uint8_t ver_subtype; 2195 uint8_t ver_type; 2196 uint8_t mac; 2197 uint8_t opt; 2198 uint32_t timestamp; 2199 uint32_t error_event_table_ptr; /* SRAM address for error log */ 2200 uint32_t log_event_table_ptr; /* SRAM address for LMAC event log */ 2201 uint32_t cpu_register_ptr; 2202 uint32_t dbgm_config_ptr; 2203 uint32_t alive_counter_ptr; 2204 uint32_t scd_base_ptr; /* SRAM address for SCD */ 2205 uint32_t st_fwrd_addr; /* pointer to Store and forward */ 2206 uint32_t st_fwrd_size; 2207 uint32_t umac_minor; /* UMAC version: minor */ 2208 uint32_t umac_major; /* UMAC version: major */ 2209 uint32_t error_info_addr; /* SRAM address for UMAC error log */ 2210 uint32_t dbg_print_buff_addr; 2211 } __packed; /* ALIVE_RES_API_S_VER_3 */ 2212 2213 /* Error response/notification */ 2214 enum { 2215 IWM_FW_ERR_UNKNOWN_CMD = 0x0, 2216 IWM_FW_ERR_INVALID_CMD_PARAM = 0x1, 2217 IWM_FW_ERR_SERVICE = 0x2, 2218 IWM_FW_ERR_ARC_MEMORY = 0x3, 2219 IWM_FW_ERR_ARC_CODE = 0x4, 2220 IWM_FW_ERR_WATCH_DOG = 0x5, 2221 IWM_FW_ERR_WEP_GRP_KEY_INDX = 0x10, 2222 IWM_FW_ERR_WEP_KEY_SIZE = 0x11, 2223 IWM_FW_ERR_OBSOLETE_FUNC = 0x12, 2224 IWM_FW_ERR_UNEXPECTED = 0xFE, 2225 IWM_FW_ERR_FATAL = 0xFF 2226 }; 2227 2228 /** 2229 * struct iwm_error_resp - FW error indication 2230 * ( IWM_REPLY_ERROR = 0x2 ) 2231 * @error_type: one of IWM_FW_ERR_* 2232 * @cmd_id: the command ID for which the error occurred 2233 * @bad_cmd_seq_num: sequence number of the erroneous command 2234 * @error_service: which service created the error, applicable only if 2235 * error_type = 2, otherwise 0 2236 * @timestamp: TSF in usecs. 2237 */ 2238 struct iwm_error_resp { 2239 uint32_t error_type; 2240 uint8_t cmd_id; 2241 uint8_t reserved1; 2242 uint16_t bad_cmd_seq_num; 2243 uint32_t error_service; 2244 uint64_t timestamp; 2245 } __packed; 2246 2247 2248 /* Common PHY, MAC and Bindings definitions */ 2249 2250 #define IWM_MAX_MACS_IN_BINDING (3) 2251 #define IWM_MAX_BINDINGS (4) 2252 #define IWM_AUX_BINDING_INDEX (3) 2253 #define IWM_MAX_PHYS (4) 2254 2255 /* Used to extract ID and color from the context dword */ 2256 #define IWM_FW_CTXT_ID_POS (0) 2257 #define IWM_FW_CTXT_ID_MSK (0xff << IWM_FW_CTXT_ID_POS) 2258 #define IWM_FW_CTXT_COLOR_POS (8) 2259 #define IWM_FW_CTXT_COLOR_MSK (0xff << IWM_FW_CTXT_COLOR_POS) 2260 #define IWM_FW_CTXT_INVALID (0xffffffff) 2261 2262 #define IWM_FW_CMD_ID_AND_COLOR(_id, _color) ((_id << IWM_FW_CTXT_ID_POS) |\ 2263 (_color << IWM_FW_CTXT_COLOR_POS)) 2264 2265 /* Possible actions on PHYs, MACs and Bindings */ 2266 enum { 2267 IWM_FW_CTXT_ACTION_STUB = 0, 2268 IWM_FW_CTXT_ACTION_ADD, 2269 IWM_FW_CTXT_ACTION_MODIFY, 2270 IWM_FW_CTXT_ACTION_REMOVE, 2271 IWM_FW_CTXT_ACTION_NUM 2272 }; /* COMMON_CONTEXT_ACTION_API_E_VER_1 */ 2273 2274 /* Time Events */ 2275 2276 /* Time Event types, according to MAC type */ 2277 enum iwm_time_event_type { 2278 /* BSS Station Events */ 2279 IWM_TE_BSS_STA_AGGRESSIVE_ASSOC, 2280 IWM_TE_BSS_STA_ASSOC, 2281 IWM_TE_BSS_EAP_DHCP_PROT, 2282 IWM_TE_BSS_QUIET_PERIOD, 2283 2284 /* P2P Device Events */ 2285 IWM_TE_P2P_DEVICE_DISCOVERABLE, 2286 IWM_TE_P2P_DEVICE_LISTEN, 2287 IWM_TE_P2P_DEVICE_ACTION_SCAN, 2288 IWM_TE_P2P_DEVICE_FULL_SCAN, 2289 2290 /* P2P Client Events */ 2291 IWM_TE_P2P_CLIENT_AGGRESSIVE_ASSOC, 2292 IWM_TE_P2P_CLIENT_ASSOC, 2293 IWM_TE_P2P_CLIENT_QUIET_PERIOD, 2294 2295 /* P2P GO Events */ 2296 IWM_TE_P2P_GO_ASSOC_PROT, 2297 IWM_TE_P2P_GO_REPETITIVE_NOA, 2298 IWM_TE_P2P_GO_CT_WINDOW, 2299 2300 /* WiDi Sync Events */ 2301 IWM_TE_WIDI_TX_SYNC, 2302 2303 IWM_TE_MAX 2304 }; /* IWM_MAC_EVENT_TYPE_API_E_VER_1 */ 2305 2306 2307 2308 /* Time event - defines for command API v1 */ 2309 2310 /* 2311 * @IWM_TE_V1_FRAG_NONE: fragmentation of the time event is NOT allowed. 2312 * @IWM_TE_V1_FRAG_SINGLE: fragmentation of the time event is allowed, but only 2313 * the first fragment is scheduled. 2314 * @IWM_TE_V1_FRAG_DUAL: fragmentation of the time event is allowed, but only 2315 * the first 2 fragments are scheduled. 2316 * @IWM_TE_V1_FRAG_ENDLESS: fragmentation of the time event is allowed, and any 2317 * number of fragments are valid. 2318 * 2319 * Other than the constant defined above, specifying a fragmentation value 'x' 2320 * means that the event can be fragmented but only the first 'x' will be 2321 * scheduled. 2322 */ 2323 enum { 2324 IWM_TE_V1_FRAG_NONE = 0, 2325 IWM_TE_V1_FRAG_SINGLE = 1, 2326 IWM_TE_V1_FRAG_DUAL = 2, 2327 IWM_TE_V1_FRAG_ENDLESS = 0xffffffff 2328 }; 2329 2330 /* If a Time Event can be fragmented, this is the max number of fragments */ 2331 #define IWM_TE_V1_FRAG_MAX_MSK 0x0fffffff 2332 /* Repeat the time event endlessly (until removed) */ 2333 #define IWM_TE_V1_REPEAT_ENDLESS 0xffffffff 2334 /* If a Time Event has bounded repetitions, this is the maximal value */ 2335 #define IWM_TE_V1_REPEAT_MAX_MSK_V1 0x0fffffff 2336 2337 /* Time Event dependencies: none, on another TE, or in a specific time */ 2338 enum { 2339 IWM_TE_V1_INDEPENDENT = 0, 2340 IWM_TE_V1_DEP_OTHER = (1 << 0), 2341 IWM_TE_V1_DEP_TSF = (1 << 1), 2342 IWM_TE_V1_EVENT_SOCIOPATHIC = (1 << 2), 2343 }; /* IWM_MAC_EVENT_DEPENDENCY_POLICY_API_E_VER_2 */ 2344 2345 /* 2346 * @IWM_TE_V1_NOTIF_NONE: no notifications 2347 * @IWM_TE_V1_NOTIF_HOST_EVENT_START: request/receive notification on event start 2348 * @IWM_TE_V1_NOTIF_HOST_EVENT_END:request/receive notification on event end 2349 * @IWM_TE_V1_NOTIF_INTERNAL_EVENT_START: internal FW use 2350 * @IWM_TE_V1_NOTIF_INTERNAL_EVENT_END: internal FW use. 2351 * @IWM_TE_V1_NOTIF_HOST_FRAG_START: request/receive notification on frag start 2352 * @IWM_TE_V1_NOTIF_HOST_FRAG_END:request/receive notification on frag end 2353 * @IWM_TE_V1_NOTIF_INTERNAL_FRAG_START: internal FW use. 2354 * @IWM_TE_V1_NOTIF_INTERNAL_FRAG_END: internal FW use. 2355 * 2356 * Supported Time event notifications configuration. 2357 * A notification (both event and fragment) includes a status indicating weather 2358 * the FW was able to schedule the event or not. For fragment start/end 2359 * notification the status is always success. There is no start/end fragment 2360 * notification for monolithic events. 2361 */ 2362 enum { 2363 IWM_TE_V1_NOTIF_NONE = 0, 2364 IWM_TE_V1_NOTIF_HOST_EVENT_START = (1 << 0), 2365 IWM_TE_V1_NOTIF_HOST_EVENT_END = (1 << 1), 2366 IWM_TE_V1_NOTIF_INTERNAL_EVENT_START = (1 << 2), 2367 IWM_TE_V1_NOTIF_INTERNAL_EVENT_END = (1 << 3), 2368 IWM_TE_V1_NOTIF_HOST_FRAG_START = (1 << 4), 2369 IWM_TE_V1_NOTIF_HOST_FRAG_END = (1 << 5), 2370 IWM_TE_V1_NOTIF_INTERNAL_FRAG_START = (1 << 6), 2371 IWM_TE_V1_NOTIF_INTERNAL_FRAG_END = (1 << 7), 2372 IWM_T2_V2_START_IMMEDIATELY = (1 << 11), 2373 }; /* IWM_MAC_EVENT_ACTION_API_E_VER_2 */ 2374 2375 /* Time event - defines for command API */ 2376 2377 /* 2378 * @IWM_TE_V2_FRAG_NONE: fragmentation of the time event is NOT allowed. 2379 * @IWM_TE_V2_FRAG_SINGLE: fragmentation of the time event is allowed, but only 2380 * the first fragment is scheduled. 2381 * @IWM_TE_V2_FRAG_DUAL: fragmentation of the time event is allowed, but only 2382 * the first 2 fragments are scheduled. 2383 * @IWM_TE_V2_FRAG_ENDLESS: fragmentation of the time event is allowed, and any 2384 * number of fragments are valid. 2385 * 2386 * Other than the constant defined above, specifying a fragmentation value 'x' 2387 * means that the event can be fragmented but only the first 'x' will be 2388 * scheduled. 2389 */ 2390 enum { 2391 IWM_TE_V2_FRAG_NONE = 0, 2392 IWM_TE_V2_FRAG_SINGLE = 1, 2393 IWM_TE_V2_FRAG_DUAL = 2, 2394 IWM_TE_V2_FRAG_MAX = 0xfe, 2395 IWM_TE_V2_FRAG_ENDLESS = 0xff 2396 }; 2397 2398 /* Repeat the time event endlessly (until removed) */ 2399 #define IWM_TE_V2_REPEAT_ENDLESS 0xff 2400 /* If a Time Event has bounded repetitions, this is the maximal value */ 2401 #define IWM_TE_V2_REPEAT_MAX 0xfe 2402 2403 #define IWM_TE_V2_PLACEMENT_POS 12 2404 #define IWM_TE_V2_ABSENCE_POS 15 2405 2406 /* Time event policy values 2407 * A notification (both event and fragment) includes a status indicating weather 2408 * the FW was able to schedule the event or not. For fragment start/end 2409 * notification the status is always success. There is no start/end fragment 2410 * notification for monolithic events. 2411 * 2412 * @IWM_TE_V2_DEFAULT_POLICY: independent, social, present, unoticable 2413 * @IWM_TE_V2_NOTIF_HOST_EVENT_START: request/receive notification on event start 2414 * @IWM_TE_V2_NOTIF_HOST_EVENT_END:request/receive notification on event end 2415 * @IWM_TE_V2_NOTIF_INTERNAL_EVENT_START: internal FW use 2416 * @IWM_TE_V2_NOTIF_INTERNAL_EVENT_END: internal FW use. 2417 * @IWM_TE_V2_NOTIF_HOST_FRAG_START: request/receive notification on frag start 2418 * @IWM_TE_V2_NOTIF_HOST_FRAG_END:request/receive notification on frag end 2419 * @IWM_TE_V2_NOTIF_INTERNAL_FRAG_START: internal FW use. 2420 * @IWM_TE_V2_NOTIF_INTERNAL_FRAG_END: internal FW use. 2421 * @IWM_TE_V2_DEP_OTHER: depends on another time event 2422 * @IWM_TE_V2_DEP_TSF: depends on a specific time 2423 * @IWM_TE_V2_EVENT_SOCIOPATHIC: can't co-exist with other events of tha same MAC 2424 * @IWM_TE_V2_ABSENCE: are we present or absent during the Time Event. 2425 */ 2426 enum { 2427 IWM_TE_V2_DEFAULT_POLICY = 0x0, 2428 2429 /* notifications (event start/stop, fragment start/stop) */ 2430 IWM_TE_V2_NOTIF_HOST_EVENT_START = (1 << 0), 2431 IWM_TE_V2_NOTIF_HOST_EVENT_END = (1 << 1), 2432 IWM_TE_V2_NOTIF_INTERNAL_EVENT_START = (1 << 2), 2433 IWM_TE_V2_NOTIF_INTERNAL_EVENT_END = (1 << 3), 2434 2435 IWM_TE_V2_NOTIF_HOST_FRAG_START = (1 << 4), 2436 IWM_TE_V2_NOTIF_HOST_FRAG_END = (1 << 5), 2437 IWM_TE_V2_NOTIF_INTERNAL_FRAG_START = (1 << 6), 2438 IWM_TE_V2_NOTIF_INTERNAL_FRAG_END = (1 << 7), 2439 2440 IWM_TE_V2_NOTIF_MSK = 0xff, 2441 2442 /* placement characteristics */ 2443 IWM_TE_V2_DEP_OTHER = (1 << IWM_TE_V2_PLACEMENT_POS), 2444 IWM_TE_V2_DEP_TSF = (1 << (IWM_TE_V2_PLACEMENT_POS + 1)), 2445 IWM_TE_V2_EVENT_SOCIOPATHIC = (1 << (IWM_TE_V2_PLACEMENT_POS + 2)), 2446 2447 /* are we present or absent during the Time Event. */ 2448 IWM_TE_V2_ABSENCE = (1 << IWM_TE_V2_ABSENCE_POS), 2449 }; 2450 2451 /** 2452 * struct iwm_time_event_cmd_api - configuring Time Events 2453 * with struct IWM_MAC_TIME_EVENT_DATA_API_S_VER_2 (see also 2454 * with version 1. determined by IWM_UCODE_TLV_FLAGS) 2455 * ( IWM_TIME_EVENT_CMD = 0x29 ) 2456 * @id_and_color: ID and color of the relevant MAC 2457 * @action: action to perform, one of IWM_FW_CTXT_ACTION_* 2458 * @id: this field has two meanings, depending on the action: 2459 * If the action is ADD, then it means the type of event to add. 2460 * For all other actions it is the unique event ID assigned when the 2461 * event was added by the FW. 2462 * @apply_time: When to start the Time Event (in GP2) 2463 * @max_delay: maximum delay to event's start (apply time), in TU 2464 * @depends_on: the unique ID of the event we depend on (if any) 2465 * @interval: interval between repetitions, in TU 2466 * @duration: duration of event in TU 2467 * @repeat: how many repetitions to do, can be IWM_TE_REPEAT_ENDLESS 2468 * @max_frags: maximal number of fragments the Time Event can be divided to 2469 * @policy: defines whether uCode shall notify the host or other uCode modules 2470 * on event and/or fragment start and/or end 2471 * using one of IWM_TE_INDEPENDENT, IWM_TE_DEP_OTHER, IWM_TE_DEP_TSF 2472 * IWM_TE_EVENT_SOCIOPATHIC 2473 * using IWM_TE_ABSENCE and using IWM_TE_NOTIF_* 2474 */ 2475 struct iwm_time_event_cmd { 2476 /* COMMON_INDEX_HDR_API_S_VER_1 */ 2477 uint32_t id_and_color; 2478 uint32_t action; 2479 uint32_t id; 2480 /* IWM_MAC_TIME_EVENT_DATA_API_S_VER_2 */ 2481 uint32_t apply_time; 2482 uint32_t max_delay; 2483 uint32_t depends_on; 2484 uint32_t interval; 2485 uint32_t duration; 2486 uint8_t repeat; 2487 uint8_t max_frags; 2488 uint16_t policy; 2489 } __packed; /* IWM_MAC_TIME_EVENT_CMD_API_S_VER_2 */ 2490 2491 /** 2492 * struct iwm_time_event_resp - response structure to iwm_time_event_cmd 2493 * @status: bit 0 indicates success, all others specify errors 2494 * @id: the Time Event type 2495 * @unique_id: the unique ID assigned (in ADD) or given (others) to the TE 2496 * @id_and_color: ID and color of the relevant MAC 2497 */ 2498 struct iwm_time_event_resp { 2499 uint32_t status; 2500 uint32_t id; 2501 uint32_t unique_id; 2502 uint32_t id_and_color; 2503 } __packed; /* IWM_MAC_TIME_EVENT_RSP_API_S_VER_1 */ 2504 2505 /** 2506 * struct iwm_time_event_notif - notifications of time event start/stop 2507 * ( IWM_TIME_EVENT_NOTIFICATION = 0x2a ) 2508 * @timestamp: action timestamp in GP2 2509 * @session_id: session's unique id 2510 * @unique_id: unique id of the Time Event itself 2511 * @id_and_color: ID and color of the relevant MAC 2512 * @action: one of IWM_TE_NOTIF_START or IWM_TE_NOTIF_END 2513 * @status: true if scheduled, false otherwise (not executed) 2514 */ 2515 struct iwm_time_event_notif { 2516 uint32_t timestamp; 2517 uint32_t session_id; 2518 uint32_t unique_id; 2519 uint32_t id_and_color; 2520 uint32_t action; 2521 uint32_t status; 2522 } __packed; /* IWM_MAC_TIME_EVENT_NTFY_API_S_VER_1 */ 2523 2524 2525 /* Bindings and Time Quota */ 2526 2527 /** 2528 * struct iwm_binding_cmd - configuring bindings 2529 * ( IWM_BINDING_CONTEXT_CMD = 0x2b ) 2530 * @id_and_color: ID and color of the relevant Binding 2531 * @action: action to perform, one of IWM_FW_CTXT_ACTION_* 2532 * @macs: array of MAC id and colors which belong to the binding 2533 * @phy: PHY id and color which belongs to the binding 2534 */ 2535 struct iwm_binding_cmd { 2536 /* COMMON_INDEX_HDR_API_S_VER_1 */ 2537 uint32_t id_and_color; 2538 uint32_t action; 2539 /* IWM_BINDING_DATA_API_S_VER_1 */ 2540 uint32_t macs[IWM_MAX_MACS_IN_BINDING]; 2541 uint32_t phy; 2542 } __packed; /* IWM_BINDING_CMD_API_S_VER_1 */ 2543 2544 /* The maximal number of fragments in the FW's schedule session */ 2545 #define IWM_MVM_MAX_QUOTA 128 2546 2547 /** 2548 * struct iwm_time_quota_data - configuration of time quota per binding 2549 * @id_and_color: ID and color of the relevant Binding 2550 * @quota: absolute time quota in TU. The scheduler will try to divide the 2551 * remainig quota (after Time Events) according to this quota. 2552 * @max_duration: max uninterrupted context duration in TU 2553 */ 2554 struct iwm_time_quota_data { 2555 uint32_t id_and_color; 2556 uint32_t quota; 2557 uint32_t max_duration; 2558 } __packed; /* IWM_TIME_QUOTA_DATA_API_S_VER_1 */ 2559 2560 /** 2561 * struct iwm_time_quota_cmd - configuration of time quota between bindings 2562 * ( IWM_TIME_QUOTA_CMD = 0x2c ) 2563 * @quotas: allocations per binding 2564 */ 2565 struct iwm_time_quota_cmd { 2566 struct iwm_time_quota_data quotas[IWM_MAX_BINDINGS]; 2567 } __packed; /* IWM_TIME_QUOTA_ALLOCATION_CMD_API_S_VER_1 */ 2568 2569 2570 /* PHY context */ 2571 2572 /* Supported bands */ 2573 #define IWM_PHY_BAND_5 (0) 2574 #define IWM_PHY_BAND_24 (1) 2575 2576 /* Supported channel width, vary if there is VHT support */ 2577 #define IWM_PHY_VHT_CHANNEL_MODE20 (0x0) 2578 #define IWM_PHY_VHT_CHANNEL_MODE40 (0x1) 2579 #define IWM_PHY_VHT_CHANNEL_MODE80 (0x2) 2580 #define IWM_PHY_VHT_CHANNEL_MODE160 (0x3) 2581 2582 /* 2583 * Control channel position: 2584 * For legacy set bit means upper channel, otherwise lower. 2585 * For VHT - bit-2 marks if the control is lower/upper relative to center-freq 2586 * bits-1:0 mark the distance from the center freq. for 20Mhz, offset is 0. 2587 * center_freq 2588 * | 2589 * 40Mhz |_______|_______| 2590 * 80Mhz |_______|_______|_______|_______| 2591 * 160Mhz |_______|_______|_______|_______|_______|_______|_______|_______| 2592 * code 011 010 001 000 | 100 101 110 111 2593 */ 2594 #define IWM_PHY_VHT_CTRL_POS_1_BELOW (0x0) 2595 #define IWM_PHY_VHT_CTRL_POS_2_BELOW (0x1) 2596 #define IWM_PHY_VHT_CTRL_POS_3_BELOW (0x2) 2597 #define IWM_PHY_VHT_CTRL_POS_4_BELOW (0x3) 2598 #define IWM_PHY_VHT_CTRL_POS_1_ABOVE (0x4) 2599 #define IWM_PHY_VHT_CTRL_POS_2_ABOVE (0x5) 2600 #define IWM_PHY_VHT_CTRL_POS_3_ABOVE (0x6) 2601 #define IWM_PHY_VHT_CTRL_POS_4_ABOVE (0x7) 2602 2603 /* 2604 * @band: IWM_PHY_BAND_* 2605 * @channel: channel number 2606 * @width: PHY_[VHT|LEGACY]_CHANNEL_* 2607 * @ctrl channel: PHY_[VHT|LEGACY]_CTRL_* 2608 */ 2609 struct iwm_fw_channel_info { 2610 uint8_t band; 2611 uint8_t channel; 2612 uint8_t width; 2613 uint8_t ctrl_pos; 2614 } __packed; 2615 2616 #define IWM_PHY_RX_CHAIN_DRIVER_FORCE_POS (0) 2617 #define IWM_PHY_RX_CHAIN_DRIVER_FORCE_MSK \ 2618 (0x1 << IWM_PHY_RX_CHAIN_DRIVER_FORCE_POS) 2619 #define IWM_PHY_RX_CHAIN_VALID_POS (1) 2620 #define IWM_PHY_RX_CHAIN_VALID_MSK \ 2621 (0x7 << IWM_PHY_RX_CHAIN_VALID_POS) 2622 #define IWM_PHY_RX_CHAIN_FORCE_SEL_POS (4) 2623 #define IWM_PHY_RX_CHAIN_FORCE_SEL_MSK \ 2624 (0x7 << IWM_PHY_RX_CHAIN_FORCE_SEL_POS) 2625 #define IWM_PHY_RX_CHAIN_FORCE_MIMO_SEL_POS (7) 2626 #define IWM_PHY_RX_CHAIN_FORCE_MIMO_SEL_MSK \ 2627 (0x7 << IWM_PHY_RX_CHAIN_FORCE_MIMO_SEL_POS) 2628 #define IWM_PHY_RX_CHAIN_CNT_POS (10) 2629 #define IWM_PHY_RX_CHAIN_CNT_MSK \ 2630 (0x3 << IWM_PHY_RX_CHAIN_CNT_POS) 2631 #define IWM_PHY_RX_CHAIN_MIMO_CNT_POS (12) 2632 #define IWM_PHY_RX_CHAIN_MIMO_CNT_MSK \ 2633 (0x3 << IWM_PHY_RX_CHAIN_MIMO_CNT_POS) 2634 #define IWM_PHY_RX_CHAIN_MIMO_FORCE_POS (14) 2635 #define IWM_PHY_RX_CHAIN_MIMO_FORCE_MSK \ 2636 (0x1 << IWM_PHY_RX_CHAIN_MIMO_FORCE_POS) 2637 2638 /* TODO: fix the value, make it depend on firmware at runtime? */ 2639 #define IWM_NUM_PHY_CTX 3 2640 2641 /* TODO: complete missing documentation */ 2642 /** 2643 * struct iwm_phy_context_cmd - config of the PHY context 2644 * ( IWM_PHY_CONTEXT_CMD = 0x8 ) 2645 * @id_and_color: ID and color of the relevant Binding 2646 * @action: action to perform, one of IWM_FW_CTXT_ACTION_* 2647 * @apply_time: 0 means immediate apply and context switch. 2648 * other value means apply new params after X usecs 2649 * @tx_param_color: ??? 2650 * @channel_info: 2651 * @txchain_info: ??? 2652 * @rxchain_info: ??? 2653 * @acquisition_data: ??? 2654 * @dsp_cfg_flags: set to 0 2655 */ 2656 struct iwm_phy_context_cmd { 2657 /* COMMON_INDEX_HDR_API_S_VER_1 */ 2658 uint32_t id_and_color; 2659 uint32_t action; 2660 /* IWM_PHY_CONTEXT_DATA_API_S_VER_1 */ 2661 uint32_t apply_time; 2662 uint32_t tx_param_color; 2663 struct iwm_fw_channel_info ci; 2664 uint32_t txchain_info; 2665 uint32_t rxchain_info; 2666 uint32_t acquisition_data; 2667 uint32_t dsp_cfg_flags; 2668 } __packed; /* IWM_PHY_CONTEXT_CMD_API_VER_1 */ 2669 2670 #define IWM_RX_INFO_PHY_CNT 8 2671 #define IWM_RX_INFO_ENERGY_ANT_ABC_IDX 1 2672 #define IWM_RX_INFO_ENERGY_ANT_A_MSK 0x000000ff 2673 #define IWM_RX_INFO_ENERGY_ANT_B_MSK 0x0000ff00 2674 #define IWM_RX_INFO_ENERGY_ANT_C_MSK 0x00ff0000 2675 #define IWM_RX_INFO_ENERGY_ANT_A_POS 0 2676 #define IWM_RX_INFO_ENERGY_ANT_B_POS 8 2677 #define IWM_RX_INFO_ENERGY_ANT_C_POS 16 2678 2679 #define IWM_RX_INFO_AGC_IDX 1 2680 #define IWM_RX_INFO_RSSI_AB_IDX 2 2681 #define IWM_OFDM_AGC_A_MSK 0x0000007f 2682 #define IWM_OFDM_AGC_A_POS 0 2683 #define IWM_OFDM_AGC_B_MSK 0x00003f80 2684 #define IWM_OFDM_AGC_B_POS 7 2685 #define IWM_OFDM_AGC_CODE_MSK 0x3fe00000 2686 #define IWM_OFDM_AGC_CODE_POS 20 2687 #define IWM_OFDM_RSSI_INBAND_A_MSK 0x00ff 2688 #define IWM_OFDM_RSSI_A_POS 0 2689 #define IWM_OFDM_RSSI_ALLBAND_A_MSK 0xff00 2690 #define IWM_OFDM_RSSI_ALLBAND_A_POS 8 2691 #define IWM_OFDM_RSSI_INBAND_B_MSK 0xff0000 2692 #define IWM_OFDM_RSSI_B_POS 16 2693 #define IWM_OFDM_RSSI_ALLBAND_B_MSK 0xff000000 2694 #define IWM_OFDM_RSSI_ALLBAND_B_POS 24 2695 2696 /** 2697 * struct iwm_rx_phy_info - phy info 2698 * (IWM_REPLY_RX_PHY_CMD = 0xc0) 2699 * @non_cfg_phy_cnt: non configurable DSP phy data byte count 2700 * @cfg_phy_cnt: configurable DSP phy data byte count 2701 * @stat_id: configurable DSP phy data set ID 2702 * @reserved1: 2703 * @system_timestamp: GP2 at on air rise 2704 * @timestamp: TSF at on air rise 2705 * @beacon_time_stamp: beacon at on-air rise 2706 * @phy_flags: general phy flags: band, modulation, ... 2707 * @channel: channel number 2708 * @non_cfg_phy_buf: for various implementations of non_cfg_phy 2709 * @rate_n_flags: IWM_RATE_MCS_* 2710 * @byte_count: frame's byte-count 2711 * @frame_time: frame's time on the air, based on byte count and frame rate 2712 * calculation 2713 * @mac_active_msk: what MACs were active when the frame was received 2714 * 2715 * Before each Rx, the device sends this data. It contains PHY information 2716 * about the reception of the packet. 2717 */ 2718 struct iwm_rx_phy_info { 2719 uint8_t non_cfg_phy_cnt; 2720 uint8_t cfg_phy_cnt; 2721 uint8_t stat_id; 2722 uint8_t reserved1; 2723 uint32_t system_timestamp; 2724 uint64_t timestamp; 2725 uint32_t beacon_time_stamp; 2726 uint16_t phy_flags; 2727 #define IWM_PHY_INFO_FLAG_SHPREAMBLE (1 << 2) 2728 uint16_t channel; 2729 uint32_t non_cfg_phy[IWM_RX_INFO_PHY_CNT]; 2730 uint8_t rate; 2731 uint8_t rflags; 2732 uint16_t xrflags; 2733 uint32_t byte_count; 2734 uint16_t mac_active_msk; 2735 uint16_t frame_time; 2736 } __packed; 2737 2738 struct iwm_rx_mpdu_res_start { 2739 uint16_t byte_count; 2740 uint16_t reserved; 2741 } __packed; 2742 2743 /** 2744 * enum iwm_rx_phy_flags - to parse %iwm_rx_phy_info phy_flags 2745 * @IWM_RX_RES_PHY_FLAGS_BAND_24: true if the packet was received on 2.4 band 2746 * @IWM_RX_RES_PHY_FLAGS_MOD_CCK: 2747 * @IWM_RX_RES_PHY_FLAGS_SHORT_PREAMBLE: true if packet's preamble was short 2748 * @IWM_RX_RES_PHY_FLAGS_NARROW_BAND: 2749 * @IWM_RX_RES_PHY_FLAGS_ANTENNA: antenna on which the packet was received 2750 * @IWM_RX_RES_PHY_FLAGS_AGG: set if the packet was part of an A-MPDU 2751 * @IWM_RX_RES_PHY_FLAGS_OFDM_HT: The frame was an HT frame 2752 * @IWM_RX_RES_PHY_FLAGS_OFDM_GF: The frame used GF preamble 2753 * @IWM_RX_RES_PHY_FLAGS_OFDM_VHT: The frame was a VHT frame 2754 */ 2755 enum iwm_rx_phy_flags { 2756 IWM_RX_RES_PHY_FLAGS_BAND_24 = (1 << 0), 2757 IWM_RX_RES_PHY_FLAGS_MOD_CCK = (1 << 1), 2758 IWM_RX_RES_PHY_FLAGS_SHORT_PREAMBLE = (1 << 2), 2759 IWM_RX_RES_PHY_FLAGS_NARROW_BAND = (1 << 3), 2760 IWM_RX_RES_PHY_FLAGS_ANTENNA = (0x7 << 4), 2761 IWM_RX_RES_PHY_FLAGS_ANTENNA_POS = 4, 2762 IWM_RX_RES_PHY_FLAGS_AGG = (1 << 7), 2763 IWM_RX_RES_PHY_FLAGS_OFDM_HT = (1 << 8), 2764 IWM_RX_RES_PHY_FLAGS_OFDM_GF = (1 << 9), 2765 IWM_RX_RES_PHY_FLAGS_OFDM_VHT = (1 << 10), 2766 }; 2767 2768 /** 2769 * enum iwm_mvm_rx_status - written by fw for each Rx packet 2770 * @IWM_RX_MPDU_RES_STATUS_CRC_OK: CRC is fine 2771 * @IWM_RX_MPDU_RES_STATUS_OVERRUN_OK: there was no RXE overflow 2772 * @IWM_RX_MPDU_RES_STATUS_SRC_STA_FOUND: 2773 * @IWM_RX_MPDU_RES_STATUS_KEY_VALID: 2774 * @IWM_RX_MPDU_RES_STATUS_KEY_PARAM_OK: 2775 * @IWM_RX_MPDU_RES_STATUS_ICV_OK: ICV is fine, if not, the packet is destroyed 2776 * @IWM_RX_MPDU_RES_STATUS_MIC_OK: used for CCM alg only. TKIP MIC is checked 2777 * in the driver. 2778 * @IWM_RX_MPDU_RES_STATUS_TTAK_OK: TTAK is fine 2779 * @IWM_RX_MPDU_RES_STATUS_MNG_FRAME_REPLAY_ERR: valid for alg = CCM_CMAC or 2780 * alg = CCM only. Checks replay attack for 11w frames. Relevant only if 2781 * %IWM_RX_MPDU_RES_STATUS_ROBUST_MNG_FRAME is set. 2782 * @IWM_RX_MPDU_RES_STATUS_SEC_NO_ENC: this frame is not encrypted 2783 * @IWM_RX_MPDU_RES_STATUS_SEC_WEP_ENC: this frame is encrypted using WEP 2784 * @IWM_RX_MPDU_RES_STATUS_SEC_CCM_ENC: this frame is encrypted using CCM 2785 * @IWM_RX_MPDU_RES_STATUS_SEC_TKIP_ENC: this frame is encrypted using TKIP 2786 * @IWM_RX_MPDU_RES_STATUS_SEC_CCM_CMAC_ENC: this frame is encrypted using CCM_CMAC 2787 * @IWM_RX_MPDU_RES_STATUS_SEC_ENC_ERR: this frame couldn't be decrypted 2788 * @IWM_RX_MPDU_RES_STATUS_SEC_ENC_MSK: bitmask of the encryption algorithm 2789 * @IWM_RX_MPDU_RES_STATUS_DEC_DONE: this frame has been successfully decrypted 2790 * @IWM_RX_MPDU_RES_STATUS_PROTECT_FRAME_BIT_CMP: 2791 * @IWM_RX_MPDU_RES_STATUS_EXT_IV_BIT_CMP: 2792 * @IWM_RX_MPDU_RES_STATUS_KEY_ID_CMP_BIT: 2793 * @IWM_RX_MPDU_RES_STATUS_ROBUST_MNG_FRAME: this frame is an 11w management frame 2794 * @IWM_RX_MPDU_RES_STATUS_HASH_INDEX_MSK: 2795 * @IWM_RX_MPDU_RES_STATUS_STA_ID_MSK: 2796 * @IWM_RX_MPDU_RES_STATUS_RRF_KILL: 2797 * @IWM_RX_MPDU_RES_STATUS_FILTERING_MSK: 2798 * @IWM_RX_MPDU_RES_STATUS2_FILTERING_MSK: 2799 */ 2800 enum iwm_mvm_rx_status { 2801 IWM_RX_MPDU_RES_STATUS_CRC_OK = (1 << 0), 2802 IWM_RX_MPDU_RES_STATUS_OVERRUN_OK = (1 << 1), 2803 IWM_RX_MPDU_RES_STATUS_SRC_STA_FOUND = (1 << 2), 2804 IWM_RX_MPDU_RES_STATUS_KEY_VALID = (1 << 3), 2805 IWM_RX_MPDU_RES_STATUS_KEY_PARAM_OK = (1 << 4), 2806 IWM_RX_MPDU_RES_STATUS_ICV_OK = (1 << 5), 2807 IWM_RX_MPDU_RES_STATUS_MIC_OK = (1 << 6), 2808 IWM_RX_MPDU_RES_STATUS_TTAK_OK = (1 << 7), 2809 IWM_RX_MPDU_RES_STATUS_MNG_FRAME_REPLAY_ERR = (1 << 7), 2810 IWM_RX_MPDU_RES_STATUS_SEC_NO_ENC = (0 << 8), 2811 IWM_RX_MPDU_RES_STATUS_SEC_WEP_ENC = (1 << 8), 2812 IWM_RX_MPDU_RES_STATUS_SEC_CCM_ENC = (2 << 8), 2813 IWM_RX_MPDU_RES_STATUS_SEC_TKIP_ENC = (3 << 8), 2814 IWM_RX_MPDU_RES_STATUS_SEC_EXT_ENC = (4 << 8), 2815 IWM_RX_MPDU_RES_STATUS_SEC_CCM_CMAC_ENC = (6 << 8), 2816 IWM_RX_MPDU_RES_STATUS_SEC_ENC_ERR = (7 << 8), 2817 IWM_RX_MPDU_RES_STATUS_SEC_ENC_MSK = (7 << 8), 2818 IWM_RX_MPDU_RES_STATUS_DEC_DONE = (1 << 11), 2819 IWM_RX_MPDU_RES_STATUS_PROTECT_FRAME_BIT_CMP = (1 << 12), 2820 IWM_RX_MPDU_RES_STATUS_EXT_IV_BIT_CMP = (1 << 13), 2821 IWM_RX_MPDU_RES_STATUS_KEY_ID_CMP_BIT = (1 << 14), 2822 IWM_RX_MPDU_RES_STATUS_ROBUST_MNG_FRAME = (1 << 15), 2823 IWM_RX_MPDU_RES_STATUS_HASH_INDEX_MSK = (0x3F0000), 2824 IWM_RX_MPDU_RES_STATUS_STA_ID_MSK = (0x1f000000), 2825 IWM_RX_MPDU_RES_STATUS_RRF_KILL = (1 << 29), 2826 IWM_RX_MPDU_RES_STATUS_FILTERING_MSK = (0xc00000), 2827 IWM_RX_MPDU_RES_STATUS2_FILTERING_MSK = (0xc0000000), 2828 }; 2829 2830 /** 2831 * struct iwm_radio_version_notif - information on the radio version 2832 * ( IWM_RADIO_VERSION_NOTIFICATION = 0x68 ) 2833 * @radio_flavor: 2834 * @radio_step: 2835 * @radio_dash: 2836 */ 2837 struct iwm_radio_version_notif { 2838 uint32_t radio_flavor; 2839 uint32_t radio_step; 2840 uint32_t radio_dash; 2841 } __packed; /* IWM_RADIO_VERSION_NOTOFICATION_S_VER_1 */ 2842 2843 enum iwm_card_state_flags { 2844 IWM_CARD_ENABLED = 0x00, 2845 IWM_HW_CARD_DISABLED = 0x01, 2846 IWM_SW_CARD_DISABLED = 0x02, 2847 IWM_CT_KILL_CARD_DISABLED = 0x04, 2848 IWM_HALT_CARD_DISABLED = 0x08, 2849 IWM_CARD_DISABLED_MSK = 0x0f, 2850 IWM_CARD_IS_RX_ON = 0x10, 2851 }; 2852 2853 /** 2854 * struct iwm_radio_version_notif - information on the radio version 2855 * (IWM_CARD_STATE_NOTIFICATION = 0xa1 ) 2856 * @flags: %iwm_card_state_flags 2857 */ 2858 struct iwm_card_state_notif { 2859 uint32_t flags; 2860 } __packed; /* CARD_STATE_NTFY_API_S_VER_1 */ 2861 2862 /** 2863 * struct iwm_missed_beacons_notif - information on missed beacons 2864 * ( IWM_MISSED_BEACONS_NOTIFICATION = 0xa2 ) 2865 * @mac_id: interface ID 2866 * @consec_missed_beacons_since_last_rx: number of consecutive missed 2867 * beacons since last RX. 2868 * @consec_missed_beacons: number of consecutive missed beacons 2869 * @num_expected_beacons: 2870 * @num_recvd_beacons: 2871 */ 2872 struct iwm_missed_beacons_notif { 2873 uint32_t mac_id; 2874 uint32_t consec_missed_beacons_since_last_rx; 2875 uint32_t consec_missed_beacons; 2876 uint32_t num_expected_beacons; 2877 uint32_t num_recvd_beacons; 2878 } __packed; /* IWM_MISSED_BEACON_NTFY_API_S_VER_3 */ 2879 2880 /** 2881 * struct iwm_mfuart_load_notif - mfuart image version & status 2882 * ( IWM_MFUART_LOAD_NOTIFICATION = 0xb1 ) 2883 * @installed_ver: installed image version 2884 * @external_ver: external image version 2885 * @status: MFUART loading status 2886 * @duration: MFUART loading time 2887 */ 2888 struct iwm_mfuart_load_notif { 2889 uint32_t installed_ver; 2890 uint32_t external_ver; 2891 uint32_t status; 2892 uint32_t duration; 2893 } __packed; /*MFU_LOADER_NTFY_API_S_VER_1*/ 2894 2895 /** 2896 * struct iwm_set_calib_default_cmd - set default value for calibration. 2897 * ( IWM_SET_CALIB_DEFAULT_CMD = 0x8e ) 2898 * @calib_index: the calibration to set value for 2899 * @length: of data 2900 * @data: the value to set for the calibration result 2901 */ 2902 struct iwm_set_calib_default_cmd { 2903 uint16_t calib_index; 2904 uint16_t length; 2905 uint8_t data[0]; 2906 } __packed; /* IWM_PHY_CALIB_OVERRIDE_VALUES_S */ 2907 2908 #define IWM_MAX_PORT_ID_NUM 2 2909 #define IWM_MAX_MCAST_FILTERING_ADDRESSES 256 2910 2911 /** 2912 * struct iwm_mcast_filter_cmd - configure multicast filter. 2913 * @filter_own: Set 1 to filter out multicast packets sent by station itself 2914 * @port_id: Multicast MAC addresses array specifier. This is a strange way 2915 * to identify network interface adopted in host-device IF. 2916 * It is used by FW as index in array of addresses. This array has 2917 * IWM_MAX_PORT_ID_NUM members. 2918 * @count: Number of MAC addresses in the array 2919 * @pass_all: Set 1 to pass all multicast packets. 2920 * @bssid: current association BSSID. 2921 * @addr_list: Place holder for array of MAC addresses. 2922 * IMPORTANT: add padding if necessary to ensure DWORD alignment. 2923 */ 2924 struct iwm_mcast_filter_cmd { 2925 uint8_t filter_own; 2926 uint8_t port_id; 2927 uint8_t count; 2928 uint8_t pass_all; 2929 uint8_t bssid[6]; 2930 uint8_t reserved[2]; 2931 uint8_t addr_list[0]; 2932 } __packed; /* IWM_MCAST_FILTERING_CMD_API_S_VER_1 */ 2933 2934 struct iwm_mvm_statistics_dbg { 2935 uint32_t burst_check; 2936 uint32_t burst_count; 2937 uint32_t wait_for_silence_timeout_cnt; 2938 uint32_t reserved[3]; 2939 } __packed; /* IWM_STATISTICS_DEBUG_API_S_VER_2 */ 2940 2941 struct iwm_mvm_statistics_div { 2942 uint32_t tx_on_a; 2943 uint32_t tx_on_b; 2944 uint32_t exec_time; 2945 uint32_t probe_time; 2946 uint32_t rssi_ant; 2947 uint32_t reserved2; 2948 } __packed; /* IWM_STATISTICS_SLOW_DIV_API_S_VER_2 */ 2949 2950 struct iwm_mvm_statistics_general_common { 2951 uint32_t temperature; /* radio temperature */ 2952 uint32_t temperature_m; /* radio voltage */ 2953 struct iwm_mvm_statistics_dbg dbg; 2954 uint32_t sleep_time; 2955 uint32_t slots_out; 2956 uint32_t slots_idle; 2957 uint32_t ttl_timestamp; 2958 struct iwm_mvm_statistics_div div; 2959 uint32_t rx_enable_counter; 2960 /* 2961 * num_of_sos_states: 2962 * count the number of times we have to re-tune 2963 * in order to get out of bad PHY status 2964 */ 2965 uint32_t num_of_sos_states; 2966 } __packed; /* IWM_STATISTICS_GENERAL_API_S_VER_5 */ 2967 2968 struct iwm_mvm_statistics_rx_non_phy { 2969 uint32_t bogus_cts; /* CTS received when not expecting CTS */ 2970 uint32_t bogus_ack; /* ACK received when not expecting ACK */ 2971 uint32_t non_bssid_frames; /* number of frames with BSSID that 2972 * doesn't belong to the STA BSSID */ 2973 uint32_t filtered_frames; /* count frames that were dumped in the 2974 * filtering process */ 2975 uint32_t non_channel_beacons; /* beacons with our bss id but not on 2976 * our serving channel */ 2977 uint32_t channel_beacons; /* beacons with our bss id and in our 2978 * serving channel */ 2979 uint32_t num_missed_bcon; /* number of missed beacons */ 2980 uint32_t adc_rx_saturation_time; /* count in 0.8us units the time the 2981 * ADC was in saturation */ 2982 uint32_t ina_detection_search_time;/* total time (in 0.8us) searched 2983 * for INA */ 2984 uint32_t beacon_silence_rssi[3];/* RSSI silence after beacon frame */ 2985 uint32_t interference_data_flag; /* flag for interference data 2986 * availability. 1 when data is 2987 * available. */ 2988 uint32_t channel_load; /* counts RX Enable time in uSec */ 2989 uint32_t dsp_false_alarms; /* DSP false alarm (both OFDM 2990 * and CCK) counter */ 2991 uint32_t beacon_rssi_a; 2992 uint32_t beacon_rssi_b; 2993 uint32_t beacon_rssi_c; 2994 uint32_t beacon_energy_a; 2995 uint32_t beacon_energy_b; 2996 uint32_t beacon_energy_c; 2997 uint32_t num_bt_kills; 2998 uint32_t mac_id; 2999 uint32_t directed_data_mpdu; 3000 } __packed; /* IWM_STATISTICS_RX_NON_PHY_API_S_VER_3 */ 3001 3002 struct iwm_mvm_statistics_rx_phy { 3003 uint32_t ina_cnt; 3004 uint32_t fina_cnt; 3005 uint32_t plcp_err; 3006 uint32_t crc32_err; 3007 uint32_t overrun_err; 3008 uint32_t early_overrun_err; 3009 uint32_t crc32_good; 3010 uint32_t false_alarm_cnt; 3011 uint32_t fina_sync_err_cnt; 3012 uint32_t sfd_timeout; 3013 uint32_t fina_timeout; 3014 uint32_t unresponded_rts; 3015 uint32_t rxe_frame_limit_overrun; 3016 uint32_t sent_ack_cnt; 3017 uint32_t sent_cts_cnt; 3018 uint32_t sent_ba_rsp_cnt; 3019 uint32_t dsp_self_kill; 3020 uint32_t mh_format_err; 3021 uint32_t re_acq_main_rssi_sum; 3022 uint32_t reserved; 3023 } __packed; /* IWM_STATISTICS_RX_PHY_API_S_VER_2 */ 3024 3025 struct iwm_mvm_statistics_rx_ht_phy { 3026 uint32_t plcp_err; 3027 uint32_t overrun_err; 3028 uint32_t early_overrun_err; 3029 uint32_t crc32_good; 3030 uint32_t crc32_err; 3031 uint32_t mh_format_err; 3032 uint32_t agg_crc32_good; 3033 uint32_t agg_mpdu_cnt; 3034 uint32_t agg_cnt; 3035 uint32_t unsupport_mcs; 3036 } __packed; /* IWM_STATISTICS_HT_RX_PHY_API_S_VER_1 */ 3037 3038 #define IWM_MAX_CHAINS 3 3039 3040 struct iwm_mvm_statistics_tx_non_phy_agg { 3041 uint32_t ba_timeout; 3042 uint32_t ba_reschedule_frames; 3043 uint32_t scd_query_agg_frame_cnt; 3044 uint32_t scd_query_no_agg; 3045 uint32_t scd_query_agg; 3046 uint32_t scd_query_mismatch; 3047 uint32_t frame_not_ready; 3048 uint32_t underrun; 3049 uint32_t bt_prio_kill; 3050 uint32_t rx_ba_rsp_cnt; 3051 int8_t txpower[IWM_MAX_CHAINS]; 3052 int8_t reserved; 3053 uint32_t reserved2; 3054 } __packed; /* IWM_STATISTICS_TX_NON_PHY_AGG_API_S_VER_1 */ 3055 3056 struct iwm_mvm_statistics_tx_channel_width { 3057 uint32_t ext_cca_narrow_ch20[1]; 3058 uint32_t ext_cca_narrow_ch40[2]; 3059 uint32_t ext_cca_narrow_ch80[3]; 3060 uint32_t ext_cca_narrow_ch160[4]; 3061 uint32_t last_tx_ch_width_indx; 3062 uint32_t rx_detected_per_ch_width[4]; 3063 uint32_t success_per_ch_width[4]; 3064 uint32_t fail_per_ch_width[4]; 3065 }; /* IWM_STATISTICS_TX_CHANNEL_WIDTH_API_S_VER_1 */ 3066 3067 struct iwm_mvm_statistics_tx { 3068 uint32_t preamble_cnt; 3069 uint32_t rx_detected_cnt; 3070 uint32_t bt_prio_defer_cnt; 3071 uint32_t bt_prio_kill_cnt; 3072 uint32_t few_bytes_cnt; 3073 uint32_t cts_timeout; 3074 uint32_t ack_timeout; 3075 uint32_t expected_ack_cnt; 3076 uint32_t actual_ack_cnt; 3077 uint32_t dump_msdu_cnt; 3078 uint32_t burst_abort_next_frame_mismatch_cnt; 3079 uint32_t burst_abort_missing_next_frame_cnt; 3080 uint32_t cts_timeout_collision; 3081 uint32_t ack_or_ba_timeout_collision; 3082 struct iwm_mvm_statistics_tx_non_phy_agg agg; 3083 struct iwm_mvm_statistics_tx_channel_width channel_width; 3084 } __packed; /* IWM_STATISTICS_TX_API_S_VER_4 */ 3085 3086 3087 struct iwm_mvm_statistics_bt_activity { 3088 uint32_t hi_priority_tx_req_cnt; 3089 uint32_t hi_priority_tx_denied_cnt; 3090 uint32_t lo_priority_tx_req_cnt; 3091 uint32_t lo_priority_tx_denied_cnt; 3092 uint32_t hi_priority_rx_req_cnt; 3093 uint32_t hi_priority_rx_denied_cnt; 3094 uint32_t lo_priority_rx_req_cnt; 3095 uint32_t lo_priority_rx_denied_cnt; 3096 } __packed; /* IWM_STATISTICS_BT_ACTIVITY_API_S_VER_1 */ 3097 3098 struct iwm_mvm_statistics_general { 3099 struct iwm_mvm_statistics_general_common common; 3100 uint32_t beacon_filtered; 3101 uint32_t missed_beacons; 3102 int8_t beacon_filter_average_energy; 3103 int8_t beacon_filter_reason; 3104 int8_t beacon_filter_current_energy; 3105 int8_t beacon_filter_reserved; 3106 uint32_t beacon_filter_delta_time; 3107 struct iwm_mvm_statistics_bt_activity bt_activity; 3108 } __packed; /* IWM_STATISTICS_GENERAL_API_S_VER_5 */ 3109 3110 struct iwm_mvm_statistics_rx { 3111 struct iwm_mvm_statistics_rx_phy ofdm; 3112 struct iwm_mvm_statistics_rx_phy cck; 3113 struct iwm_mvm_statistics_rx_non_phy general; 3114 struct iwm_mvm_statistics_rx_ht_phy ofdm_ht; 3115 } __packed; /* IWM_STATISTICS_RX_API_S_VER_3 */ 3116 3117 /* 3118 * IWM_STATISTICS_NOTIFICATION = 0x9d (notification only, not a command) 3119 * 3120 * By default, uCode issues this notification after receiving a beacon 3121 * while associated. To disable this behavior, set DISABLE_NOTIF flag in the 3122 * IWM_REPLY_STATISTICS_CMD 0x9c, above. 3123 * 3124 * Statistics counters continue to increment beacon after beacon, but are 3125 * cleared when changing channels or when driver issues IWM_REPLY_STATISTICS_CMD 3126 * 0x9c with CLEAR_STATS bit set (see above). 3127 * 3128 * uCode also issues this notification during scans. uCode clears statistics 3129 * appropriately so that each notification contains statistics for only the 3130 * one channel that has just been scanned. 3131 */ 3132 3133 struct iwm_notif_statistics { /* IWM_STATISTICS_NTFY_API_S_VER_8 */ 3134 uint32_t flag; 3135 struct iwm_mvm_statistics_rx rx; 3136 struct iwm_mvm_statistics_tx tx; 3137 struct iwm_mvm_statistics_general general; 3138 } __packed; 3139 3140 /*********************************** 3141 * Smart Fifo API 3142 ***********************************/ 3143 /* Smart Fifo state */ 3144 enum iwm_sf_state { 3145 IWM_SF_LONG_DELAY_ON = 0, /* should never be called by driver */ 3146 IWM_SF_FULL_ON, 3147 IWM_SF_UNINIT, 3148 IWM_SF_INIT_OFF, 3149 IWM_SF_HW_NUM_STATES 3150 }; 3151 3152 /* Smart Fifo possible scenario */ 3153 enum iwm_sf_scenario { 3154 IWM_SF_SCENARIO_SINGLE_UNICAST, 3155 IWM_SF_SCENARIO_AGG_UNICAST, 3156 IWM_SF_SCENARIO_MULTICAST, 3157 IWM_SF_SCENARIO_BA_RESP, 3158 IWM_SF_SCENARIO_TX_RESP, 3159 IWM_SF_NUM_SCENARIO 3160 }; 3161 3162 #define IWM_SF_TRANSIENT_STATES_NUMBER 2 /* IWM_SF_LONG_DELAY_ON and IWM_SF_FULL_ON */ 3163 #define IWM_SF_NUM_TIMEOUT_TYPES 2 /* Aging timer and Idle timer */ 3164 3165 /* smart FIFO default values */ 3166 #define IWM_SF_W_MARK_SISO 4096 3167 #define IWM_SF_W_MARK_MIMO2 8192 3168 #define IWM_SF_W_MARK_MIMO3 6144 3169 #define IWM_SF_W_MARK_LEGACY 4096 3170 #define IWM_SF_W_MARK_SCAN 4096 3171 3172 /* SF Scenarios timers for default configuration (aligned to 32 uSec) */ 3173 #define IWM_SF_SINGLE_UNICAST_IDLE_TIMER_DEF 160 /* 150 uSec */ 3174 #define IWM_SF_SINGLE_UNICAST_AGING_TIMER_DEF 400 /* 0.4 mSec */ 3175 #define IWM_SF_AGG_UNICAST_IDLE_TIMER_DEF 160 /* 150 uSec */ 3176 #define IWM_SF_AGG_UNICAST_AGING_TIMER_DEF 400 /* 0.4 mSec */ 3177 #define IWM_SF_MCAST_IDLE_TIMER_DEF 160 /* 150 uSec */ 3178 #define IWM_SF_MCAST_AGING_TIMER_DEF 400 /* 0.4 mSec */ 3179 #define IWM_SF_BA_IDLE_TIMER_DEF 160 /* 150 uSec */ 3180 #define IWM_SF_BA_AGING_TIMER_DEF 400 /* 0.4 mSec */ 3181 #define IWM_SF_TX_RE_IDLE_TIMER_DEF 160 /* 150 uSec */ 3182 #define IWM_SF_TX_RE_AGING_TIMER_DEF 400 /* 0.4 mSec */ 3183 3184 /* SF Scenarios timers for FULL_ON state (aligned to 32 uSec) */ 3185 #define IWM_SF_SINGLE_UNICAST_IDLE_TIMER 320 /* 300 uSec */ 3186 #define IWM_SF_SINGLE_UNICAST_AGING_TIMER 2016 /* 2 mSec */ 3187 #define IWM_SF_AGG_UNICAST_IDLE_TIMER 320 /* 300 uSec */ 3188 #define IWM_SF_AGG_UNICAST_AGING_TIMER 2016 /* 2 mSec */ 3189 #define IWM_SF_MCAST_IDLE_TIMER 2016 /* 2 mSec */ 3190 #define IWM_SF_MCAST_AGING_TIMER 10016 /* 10 mSec */ 3191 #define IWM_SF_BA_IDLE_TIMER 320 /* 300 uSec */ 3192 #define IWM_SF_BA_AGING_TIMER 2016 /* 2 mSec */ 3193 #define IWM_SF_TX_RE_IDLE_TIMER 320 /* 300 uSec */ 3194 #define IWM_SF_TX_RE_AGING_TIMER 2016 /* 2 mSec */ 3195 3196 #define IWM_SF_LONG_DELAY_AGING_TIMER 1000000 /* 1 Sec */ 3197 3198 #define IWM_SF_CFG_DUMMY_NOTIF_OFF (1 << 16) 3199 3200 /** 3201 * Smart Fifo configuration command. 3202 * @state: smart fifo state, types listed in iwm_sf_state. 3203 * @watermark: Minimum allowed available free space in RXF for transient state. 3204 * @long_delay_timeouts: aging and idle timer values for each scenario 3205 * in long delay state. 3206 * @full_on_timeouts: timer values for each scenario in full on state. 3207 */ 3208 struct iwm_sf_cfg_cmd { 3209 uint32_t state; 3210 uint32_t watermark[IWM_SF_TRANSIENT_STATES_NUMBER]; 3211 uint32_t long_delay_timeouts[IWM_SF_NUM_SCENARIO][IWM_SF_NUM_TIMEOUT_TYPES]; 3212 uint32_t full_on_timeouts[IWM_SF_NUM_SCENARIO][IWM_SF_NUM_TIMEOUT_TYPES]; 3213 } __packed; /* IWM_SF_CFG_API_S_VER_2 */ 3214 3215 /* 3216 * END mvm/fw-api.h 3217 */ 3218 3219 /* 3220 * BEGIN mvm/fw-api-mac.h 3221 */ 3222 3223 /* 3224 * The first MAC indices (starting from 0) 3225 * are available to the driver, AUX follows 3226 */ 3227 #define IWM_MAC_INDEX_AUX 4 3228 #define IWM_MAC_INDEX_MIN_DRIVER 0 3229 #define IWM_NUM_MAC_INDEX_DRIVER IWM_MAC_INDEX_AUX 3230 3231 enum iwm_ac { 3232 IWM_AC_BK, 3233 IWM_AC_BE, 3234 IWM_AC_VI, 3235 IWM_AC_VO, 3236 IWM_AC_NUM, 3237 }; 3238 3239 /** 3240 * enum iwm_mac_protection_flags - MAC context flags 3241 * @IWM_MAC_PROT_FLG_TGG_PROTECT: 11g protection when transmitting OFDM frames, 3242 * this will require CCK RTS/CTS2self. 3243 * RTS/CTS will protect full burst time. 3244 * @IWM_MAC_PROT_FLG_HT_PROT: enable HT protection 3245 * @IWM_MAC_PROT_FLG_FAT_PROT: protect 40 MHz transmissions 3246 * @IWM_MAC_PROT_FLG_SELF_CTS_EN: allow CTS2self 3247 */ 3248 enum iwm_mac_protection_flags { 3249 IWM_MAC_PROT_FLG_TGG_PROTECT = (1 << 3), 3250 IWM_MAC_PROT_FLG_HT_PROT = (1 << 23), 3251 IWM_MAC_PROT_FLG_FAT_PROT = (1 << 24), 3252 IWM_MAC_PROT_FLG_SELF_CTS_EN = (1 << 30), 3253 }; 3254 3255 #define IWM_MAC_FLG_SHORT_SLOT (1 << 4) 3256 #define IWM_MAC_FLG_SHORT_PREAMBLE (1 << 5) 3257 3258 /** 3259 * enum iwm_mac_types - Supported MAC types 3260 * @IWM_FW_MAC_TYPE_FIRST: lowest supported MAC type 3261 * @IWM_FW_MAC_TYPE_AUX: Auxiliary MAC (internal) 3262 * @IWM_FW_MAC_TYPE_LISTENER: monitor MAC type (?) 3263 * @IWM_FW_MAC_TYPE_PIBSS: Pseudo-IBSS 3264 * @IWM_FW_MAC_TYPE_IBSS: IBSS 3265 * @IWM_FW_MAC_TYPE_BSS_STA: BSS (managed) station 3266 * @IWM_FW_MAC_TYPE_P2P_DEVICE: P2P Device 3267 * @IWM_FW_MAC_TYPE_P2P_STA: P2P client 3268 * @IWM_FW_MAC_TYPE_GO: P2P GO 3269 * @IWM_FW_MAC_TYPE_TEST: ? 3270 * @IWM_FW_MAC_TYPE_MAX: highest support MAC type 3271 */ 3272 enum iwm_mac_types { 3273 IWM_FW_MAC_TYPE_FIRST = 1, 3274 IWM_FW_MAC_TYPE_AUX = IWM_FW_MAC_TYPE_FIRST, 3275 IWM_FW_MAC_TYPE_LISTENER, 3276 IWM_FW_MAC_TYPE_PIBSS, 3277 IWM_FW_MAC_TYPE_IBSS, 3278 IWM_FW_MAC_TYPE_BSS_STA, 3279 IWM_FW_MAC_TYPE_P2P_DEVICE, 3280 IWM_FW_MAC_TYPE_P2P_STA, 3281 IWM_FW_MAC_TYPE_GO, 3282 IWM_FW_MAC_TYPE_TEST, 3283 IWM_FW_MAC_TYPE_MAX = IWM_FW_MAC_TYPE_TEST 3284 }; /* IWM_MAC_CONTEXT_TYPE_API_E_VER_1 */ 3285 3286 /** 3287 * enum iwm_tsf_id - TSF hw timer ID 3288 * @IWM_TSF_ID_A: use TSF A 3289 * @IWM_TSF_ID_B: use TSF B 3290 * @IWM_TSF_ID_C: use TSF C 3291 * @IWM_TSF_ID_D: use TSF D 3292 * @IWM_NUM_TSF_IDS: number of TSF timers available 3293 */ 3294 enum iwm_tsf_id { 3295 IWM_TSF_ID_A = 0, 3296 IWM_TSF_ID_B = 1, 3297 IWM_TSF_ID_C = 2, 3298 IWM_TSF_ID_D = 3, 3299 IWM_NUM_TSF_IDS = 4, 3300 }; /* IWM_TSF_ID_API_E_VER_1 */ 3301 3302 /** 3303 * struct iwm_mac_data_ap - configuration data for AP MAC context 3304 * @beacon_time: beacon transmit time in system time 3305 * @beacon_tsf: beacon transmit time in TSF 3306 * @bi: beacon interval in TU 3307 * @bi_reciprocal: 2^32 / bi 3308 * @dtim_interval: dtim transmit time in TU 3309 * @dtim_reciprocal: 2^32 / dtim_interval 3310 * @mcast_qid: queue ID for multicast traffic 3311 * @beacon_template: beacon template ID 3312 */ 3313 struct iwm_mac_data_ap { 3314 uint32_t beacon_time; 3315 uint64_t beacon_tsf; 3316 uint32_t bi; 3317 uint32_t bi_reciprocal; 3318 uint32_t dtim_interval; 3319 uint32_t dtim_reciprocal; 3320 uint32_t mcast_qid; 3321 uint32_t beacon_template; 3322 } __packed; /* AP_MAC_DATA_API_S_VER_1 */ 3323 3324 /** 3325 * struct iwm_mac_data_ibss - configuration data for IBSS MAC context 3326 * @beacon_time: beacon transmit time in system time 3327 * @beacon_tsf: beacon transmit time in TSF 3328 * @bi: beacon interval in TU 3329 * @bi_reciprocal: 2^32 / bi 3330 * @beacon_template: beacon template ID 3331 */ 3332 struct iwm_mac_data_ibss { 3333 uint32_t beacon_time; 3334 uint64_t beacon_tsf; 3335 uint32_t bi; 3336 uint32_t bi_reciprocal; 3337 uint32_t beacon_template; 3338 } __packed; /* IBSS_MAC_DATA_API_S_VER_1 */ 3339 3340 /** 3341 * struct iwm_mac_data_sta - configuration data for station MAC context 3342 * @is_assoc: 1 for associated state, 0 otherwise 3343 * @dtim_time: DTIM arrival time in system time 3344 * @dtim_tsf: DTIM arrival time in TSF 3345 * @bi: beacon interval in TU, applicable only when associated 3346 * @bi_reciprocal: 2^32 / bi , applicable only when associated 3347 * @dtim_interval: DTIM interval in TU, applicable only when associated 3348 * @dtim_reciprocal: 2^32 / dtim_interval , applicable only when associated 3349 * @listen_interval: in beacon intervals, applicable only when associated 3350 * @assoc_id: unique ID assigned by the AP during association 3351 */ 3352 struct iwm_mac_data_sta { 3353 uint32_t is_assoc; 3354 uint32_t dtim_time; 3355 uint64_t dtim_tsf; 3356 uint32_t bi; 3357 uint32_t bi_reciprocal; 3358 uint32_t dtim_interval; 3359 uint32_t dtim_reciprocal; 3360 uint32_t listen_interval; 3361 uint32_t assoc_id; 3362 uint32_t assoc_beacon_arrive_time; 3363 } __packed; /* IWM_STA_MAC_DATA_API_S_VER_1 */ 3364 3365 /** 3366 * struct iwm_mac_data_go - configuration data for P2P GO MAC context 3367 * @ap: iwm_mac_data_ap struct with most config data 3368 * @ctwin: client traffic window in TU (period after TBTT when GO is present). 3369 * 0 indicates that there is no CT window. 3370 * @opp_ps_enabled: indicate that opportunistic PS allowed 3371 */ 3372 struct iwm_mac_data_go { 3373 struct iwm_mac_data_ap ap; 3374 uint32_t ctwin; 3375 uint32_t opp_ps_enabled; 3376 } __packed; /* GO_MAC_DATA_API_S_VER_1 */ 3377 3378 /** 3379 * struct iwm_mac_data_p2p_sta - configuration data for P2P client MAC context 3380 * @sta: iwm_mac_data_sta struct with most config data 3381 * @ctwin: client traffic window in TU (period after TBTT when GO is present). 3382 * 0 indicates that there is no CT window. 3383 */ 3384 struct iwm_mac_data_p2p_sta { 3385 struct iwm_mac_data_sta sta; 3386 uint32_t ctwin; 3387 } __packed; /* P2P_STA_MAC_DATA_API_S_VER_1 */ 3388 3389 /** 3390 * struct iwm_mac_data_pibss - Pseudo IBSS config data 3391 * @stats_interval: interval in TU between statistics notifications to host. 3392 */ 3393 struct iwm_mac_data_pibss { 3394 uint32_t stats_interval; 3395 } __packed; /* PIBSS_MAC_DATA_API_S_VER_1 */ 3396 3397 /* 3398 * struct iwm_mac_data_p2p_dev - configuration data for the P2P Device MAC 3399 * context. 3400 * @is_disc_extended: if set to true, P2P Device discoverability is enabled on 3401 * other channels as well. This should be to true only in case that the 3402 * device is discoverable and there is an active GO. Note that setting this 3403 * field when not needed, will increase the number of interrupts and have 3404 * effect on the platform power, as this setting opens the Rx filters on 3405 * all macs. 3406 */ 3407 struct iwm_mac_data_p2p_dev { 3408 uint32_t is_disc_extended; 3409 } __packed; /* _P2P_DEV_MAC_DATA_API_S_VER_1 */ 3410 3411 /** 3412 * enum iwm_mac_filter_flags - MAC context filter flags 3413 * @IWM_MAC_FILTER_IN_PROMISC: accept all data frames 3414 * @IWM_MAC_FILTER_IN_CONTROL_AND_MGMT: pass all mangement and 3415 * control frames to the host 3416 * @IWM_MAC_FILTER_ACCEPT_GRP: accept multicast frames 3417 * @IWM_MAC_FILTER_DIS_DECRYPT: don't decrypt unicast frames 3418 * @IWM_MAC_FILTER_DIS_GRP_DECRYPT: don't decrypt multicast frames 3419 * @IWM_MAC_FILTER_IN_BEACON: transfer foreign BSS's beacons to host 3420 * (in station mode when associated) 3421 * @IWM_MAC_FILTER_OUT_BCAST: filter out all broadcast frames 3422 * @IWM_MAC_FILTER_IN_CRC32: extract FCS and append it to frames 3423 * @IWM_MAC_FILTER_IN_PROBE_REQUEST: pass probe requests to host 3424 */ 3425 enum iwm_mac_filter_flags { 3426 IWM_MAC_FILTER_IN_PROMISC = (1 << 0), 3427 IWM_MAC_FILTER_IN_CONTROL_AND_MGMT = (1 << 1), 3428 IWM_MAC_FILTER_ACCEPT_GRP = (1 << 2), 3429 IWM_MAC_FILTER_DIS_DECRYPT = (1 << 3), 3430 IWM_MAC_FILTER_DIS_GRP_DECRYPT = (1 << 4), 3431 IWM_MAC_FILTER_IN_BEACON = (1 << 6), 3432 IWM_MAC_FILTER_OUT_BCAST = (1 << 8), 3433 IWM_MAC_FILTER_IN_CRC32 = (1 << 11), 3434 IWM_MAC_FILTER_IN_PROBE_REQUEST = (1 << 12), 3435 }; 3436 3437 /** 3438 * enum iwm_mac_qos_flags - QoS flags 3439 * @IWM_MAC_QOS_FLG_UPDATE_EDCA: ? 3440 * @IWM_MAC_QOS_FLG_TGN: HT is enabled 3441 * @IWM_MAC_QOS_FLG_TXOP_TYPE: ? 3442 * 3443 */ 3444 enum iwm_mac_qos_flags { 3445 IWM_MAC_QOS_FLG_UPDATE_EDCA = (1 << 0), 3446 IWM_MAC_QOS_FLG_TGN = (1 << 1), 3447 IWM_MAC_QOS_FLG_TXOP_TYPE = (1 << 4), 3448 }; 3449 3450 /** 3451 * struct iwm_ac_qos - QOS timing params for IWM_MAC_CONTEXT_CMD 3452 * @cw_min: Contention window, start value in numbers of slots. 3453 * Should be a power-of-2, minus 1. Device's default is 0x0f. 3454 * @cw_max: Contention window, max value in numbers of slots. 3455 * Should be a power-of-2, minus 1. Device's default is 0x3f. 3456 * @aifsn: Number of slots in Arbitration Interframe Space (before 3457 * performing random backoff timing prior to Tx). Device default 1. 3458 * @fifos_mask: FIFOs used by this MAC for this AC 3459 * @edca_txop: Length of Tx opportunity, in uSecs. Device default is 0. 3460 * 3461 * One instance of this config struct for each of 4 EDCA access categories 3462 * in struct iwm_qosparam_cmd. 3463 * 3464 * Device will automatically increase contention window by (2*CW) + 1 for each 3465 * transmission retry. Device uses cw_max as a bit mask, ANDed with new CW 3466 * value, to cap the CW value. 3467 */ 3468 struct iwm_ac_qos { 3469 uint16_t cw_min; 3470 uint16_t cw_max; 3471 uint8_t aifsn; 3472 uint8_t fifos_mask; 3473 uint16_t edca_txop; 3474 } __packed; /* IWM_AC_QOS_API_S_VER_2 */ 3475 3476 /** 3477 * struct iwm_mac_ctx_cmd - command structure to configure MAC contexts 3478 * ( IWM_MAC_CONTEXT_CMD = 0x28 ) 3479 * @id_and_color: ID and color of the MAC 3480 * @action: action to perform, one of IWM_FW_CTXT_ACTION_* 3481 * @mac_type: one of IWM_FW_MAC_TYPE_* 3482 * @tsd_id: TSF HW timer, one of IWM_TSF_ID_* 3483 * @node_addr: MAC address 3484 * @bssid_addr: BSSID 3485 * @cck_rates: basic rates available for CCK 3486 * @ofdm_rates: basic rates available for OFDM 3487 * @protection_flags: combination of IWM_MAC_PROT_FLG_FLAG_* 3488 * @cck_short_preamble: 0x20 for enabling short preamble, 0 otherwise 3489 * @short_slot: 0x10 for enabling short slots, 0 otherwise 3490 * @filter_flags: combination of IWM_MAC_FILTER_* 3491 * @qos_flags: from IWM_MAC_QOS_FLG_* 3492 * @ac: one iwm_mac_qos configuration for each AC 3493 * @mac_specific: one of struct iwm_mac_data_*, according to mac_type 3494 */ 3495 struct iwm_mac_ctx_cmd { 3496 /* COMMON_INDEX_HDR_API_S_VER_1 */ 3497 uint32_t id_and_color; 3498 uint32_t action; 3499 /* IWM_MAC_CONTEXT_COMMON_DATA_API_S_VER_1 */ 3500 uint32_t mac_type; 3501 uint32_t tsf_id; 3502 uint8_t node_addr[6]; 3503 uint16_t reserved_for_node_addr; 3504 uint8_t bssid_addr[6]; 3505 uint16_t reserved_for_bssid_addr; 3506 uint32_t cck_rates; 3507 uint32_t ofdm_rates; 3508 uint32_t protection_flags; 3509 uint32_t cck_short_preamble; 3510 uint32_t short_slot; 3511 uint32_t filter_flags; 3512 /* IWM_MAC_QOS_PARAM_API_S_VER_1 */ 3513 uint32_t qos_flags; 3514 struct iwm_ac_qos ac[IWM_AC_NUM+1]; 3515 /* IWM_MAC_CONTEXT_COMMON_DATA_API_S */ 3516 union { 3517 struct iwm_mac_data_ap ap; 3518 struct iwm_mac_data_go go; 3519 struct iwm_mac_data_sta sta; 3520 struct iwm_mac_data_p2p_sta p2p_sta; 3521 struct iwm_mac_data_p2p_dev p2p_dev; 3522 struct iwm_mac_data_pibss pibss; 3523 struct iwm_mac_data_ibss ibss; 3524 }; 3525 } __packed; /* IWM_MAC_CONTEXT_CMD_API_S_VER_1 */ 3526 3527 static inline uint32_t iwm_mvm_reciprocal(uint32_t v) 3528 { 3529 if (!v) 3530 return 0; 3531 return 0xFFFFFFFF / v; 3532 } 3533 3534 #define IWM_NONQOS_SEQ_GET 0x1 3535 #define IWM_NONQOS_SEQ_SET 0x2 3536 struct iwm_nonqos_seq_query_cmd { 3537 uint32_t get_set_flag; 3538 uint32_t mac_id_n_color; 3539 uint16_t value; 3540 uint16_t reserved; 3541 } __packed; /* IWM_NON_QOS_TX_COUNTER_GET_SET_API_S_VER_1 */ 3542 3543 /* 3544 * END mvm/fw-api-mac.h 3545 */ 3546 3547 /* 3548 * BEGIN mvm/fw-api-power.h 3549 */ 3550 3551 /* Power Management Commands, Responses, Notifications */ 3552 3553 /* Radio LP RX Energy Threshold measured in dBm */ 3554 #define IWM_POWER_LPRX_RSSI_THRESHOLD 75 3555 #define IWM_POWER_LPRX_RSSI_THRESHOLD_MAX 94 3556 #define IWM_POWER_LPRX_RSSI_THRESHOLD_MIN 30 3557 3558 /** 3559 * enum iwm_scan_flags - masks for power table command flags 3560 * @IWM_POWER_FLAGS_POWER_SAVE_ENA_MSK: '1' Allow to save power by turning off 3561 * receiver and transmitter. '0' - does not allow. 3562 * @IWM_POWER_FLAGS_POWER_MANAGEMENT_ENA_MSK: '0' Driver disables power management, 3563 * '1' Driver enables PM (use rest of parameters) 3564 * @IWM_POWER_FLAGS_SKIP_OVER_DTIM_MSK: '0' PM have to walk up every DTIM, 3565 * '1' PM could sleep over DTIM till listen Interval. 3566 * @IWM_POWER_FLAGS_SNOOZE_ENA_MSK: Enable snoozing only if uAPSD is enabled and all 3567 * access categories are both delivery and trigger enabled. 3568 * @IWM_POWER_FLAGS_BT_SCO_ENA: Enable BT SCO coex only if uAPSD and 3569 * PBW Snoozing enabled 3570 * @IWM_POWER_FLAGS_ADVANCE_PM_ENA_MSK: Advanced PM (uAPSD) enable mask 3571 * @IWM_POWER_FLAGS_LPRX_ENA_MSK: Low Power RX enable. 3572 * @IWM_POWER_FLAGS_AP_UAPSD_MISBEHAVING_ENA_MSK: AP/GO's uAPSD misbehaving 3573 * detection enablement 3574 */ 3575 enum iwm_power_flags { 3576 IWM_POWER_FLAGS_POWER_SAVE_ENA_MSK = (1 << 0), 3577 IWM_POWER_FLAGS_POWER_MANAGEMENT_ENA_MSK = (1 << 1), 3578 IWM_POWER_FLAGS_SKIP_OVER_DTIM_MSK = (1 << 2), 3579 IWM_POWER_FLAGS_SNOOZE_ENA_MSK = (1 << 5), 3580 IWM_POWER_FLAGS_BT_SCO_ENA = (1 << 8), 3581 IWM_POWER_FLAGS_ADVANCE_PM_ENA_MSK = (1 << 9), 3582 IWM_POWER_FLAGS_LPRX_ENA_MSK = (1 << 11), 3583 IWM_POWER_FLAGS_UAPSD_MISBEHAVING_ENA_MSK = (1 << 12), 3584 }; 3585 3586 #define IWM_POWER_VEC_SIZE 5 3587 3588 /** 3589 * struct iwm_powertable_cmd - legacy power command. Beside old API support this 3590 * is used also with a new power API for device wide power settings. 3591 * IWM_POWER_TABLE_CMD = 0x77 (command, has simple generic response) 3592 * 3593 * @flags: Power table command flags from IWM_POWER_FLAGS_* 3594 * @keep_alive_seconds: Keep alive period in seconds. Default - 25 sec. 3595 * Minimum allowed:- 3 * DTIM. Keep alive period must be 3596 * set regardless of power scheme or current power state. 3597 * FW use this value also when PM is disabled. 3598 * @rx_data_timeout: Minimum time (usec) from last Rx packet for AM to 3599 * PSM transition - legacy PM 3600 * @tx_data_timeout: Minimum time (usec) from last Tx packet for AM to 3601 * PSM transition - legacy PM 3602 * @sleep_interval: not in use 3603 * @skip_dtim_periods: Number of DTIM periods to skip if Skip over DTIM flag 3604 * is set. For example, if it is required to skip over 3605 * one DTIM, this value need to be set to 2 (DTIM periods). 3606 * @lprx_rssi_threshold: Signal strength up to which LP RX can be enabled. 3607 * Default: 80dbm 3608 */ 3609 struct iwm_powertable_cmd { 3610 /* PM_POWER_TABLE_CMD_API_S_VER_6 */ 3611 uint16_t flags; 3612 uint8_t keep_alive_seconds; 3613 uint8_t debug_flags; 3614 uint32_t rx_data_timeout; 3615 uint32_t tx_data_timeout; 3616 uint32_t sleep_interval[IWM_POWER_VEC_SIZE]; 3617 uint32_t skip_dtim_periods; 3618 uint32_t lprx_rssi_threshold; 3619 } __packed; 3620 3621 /** 3622 * enum iwm_device_power_flags - masks for device power command flags 3623 * @DEVIC_POWER_FLAGS_POWER_SAVE_ENA_MSK: '1' Allow to save power by turning off 3624 * receiver and transmitter. '0' - does not allow. This flag should be 3625 * always set to '1' unless one need to disable actual power down for debug 3626 * purposes. 3627 * @IWM_DEVICE_POWER_FLAGS_CAM_MSK: '1' CAM (Continuous Active Mode) is set, meaning 3628 * that power management is disabled. '0' Power management is enabled, one 3629 * of power schemes is applied. 3630 */ 3631 enum iwm_device_power_flags { 3632 IWM_DEVICE_POWER_FLAGS_POWER_SAVE_ENA_MSK = (1 << 0), 3633 IWM_DEVICE_POWER_FLAGS_CAM_MSK = (1 << 13), 3634 }; 3635 3636 /** 3637 * struct iwm_device_power_cmd - device wide power command. 3638 * IWM_DEVICE_POWER_CMD = 0x77 (command, has simple generic response) 3639 * 3640 * @flags: Power table command flags from IWM_DEVICE_POWER_FLAGS_* 3641 */ 3642 struct iwm_device_power_cmd { 3643 /* PM_POWER_TABLE_CMD_API_S_VER_6 */ 3644 uint16_t flags; 3645 uint16_t reserved; 3646 } __packed; 3647 3648 /** 3649 * struct iwm_mac_power_cmd - New power command containing uAPSD support 3650 * IWM_MAC_PM_POWER_TABLE = 0xA9 (command, has simple generic response) 3651 * @id_and_color: MAC contex identifier 3652 * @flags: Power table command flags from POWER_FLAGS_* 3653 * @keep_alive_seconds: Keep alive period in seconds. Default - 25 sec. 3654 * Minimum allowed:- 3 * DTIM. Keep alive period must be 3655 * set regardless of power scheme or current power state. 3656 * FW use this value also when PM is disabled. 3657 * @rx_data_timeout: Minimum time (usec) from last Rx packet for AM to 3658 * PSM transition - legacy PM 3659 * @tx_data_timeout: Minimum time (usec) from last Tx packet for AM to 3660 * PSM transition - legacy PM 3661 * @sleep_interval: not in use 3662 * @skip_dtim_periods: Number of DTIM periods to skip if Skip over DTIM flag 3663 * is set. For example, if it is required to skip over 3664 * one DTIM, this value need to be set to 2 (DTIM periods). 3665 * @rx_data_timeout_uapsd: Minimum time (usec) from last Rx packet for AM to 3666 * PSM transition - uAPSD 3667 * @tx_data_timeout_uapsd: Minimum time (usec) from last Tx packet for AM to 3668 * PSM transition - uAPSD 3669 * @lprx_rssi_threshold: Signal strength up to which LP RX can be enabled. 3670 * Default: 80dbm 3671 * @num_skip_dtim: Number of DTIMs to skip if Skip over DTIM flag is set 3672 * @snooze_interval: Maximum time between attempts to retrieve buffered data 3673 * from the AP [msec] 3674 * @snooze_window: A window of time in which PBW snoozing insures that all 3675 * packets received. It is also the minimum time from last 3676 * received unicast RX packet, before client stops snoozing 3677 * for data. [msec] 3678 * @snooze_step: TBD 3679 * @qndp_tid: TID client shall use for uAPSD QNDP triggers 3680 * @uapsd_ac_flags: Set trigger-enabled and delivery-enabled indication for 3681 * each corresponding AC. 3682 * Use IEEE80211_WMM_IE_STA_QOSINFO_AC* for correct values. 3683 * @uapsd_max_sp: Use IEEE80211_WMM_IE_STA_QOSINFO_SP_* for correct 3684 * values. 3685 * @heavy_tx_thld_packets: TX threshold measured in number of packets 3686 * @heavy_rx_thld_packets: RX threshold measured in number of packets 3687 * @heavy_tx_thld_percentage: TX threshold measured in load's percentage 3688 * @heavy_rx_thld_percentage: RX threshold measured in load's percentage 3689 * @limited_ps_threshold: 3690 */ 3691 struct iwm_mac_power_cmd { 3692 /* CONTEXT_DESC_API_T_VER_1 */ 3693 uint32_t id_and_color; 3694 3695 /* CLIENT_PM_POWER_TABLE_S_VER_1 */ 3696 uint16_t flags; 3697 uint16_t keep_alive_seconds; 3698 uint32_t rx_data_timeout; 3699 uint32_t tx_data_timeout; 3700 uint32_t rx_data_timeout_uapsd; 3701 uint32_t tx_data_timeout_uapsd; 3702 uint8_t lprx_rssi_threshold; 3703 uint8_t skip_dtim_periods; 3704 uint16_t snooze_interval; 3705 uint16_t snooze_window; 3706 uint8_t snooze_step; 3707 uint8_t qndp_tid; 3708 uint8_t uapsd_ac_flags; 3709 uint8_t uapsd_max_sp; 3710 uint8_t heavy_tx_thld_packets; 3711 uint8_t heavy_rx_thld_packets; 3712 uint8_t heavy_tx_thld_percentage; 3713 uint8_t heavy_rx_thld_percentage; 3714 uint8_t limited_ps_threshold; 3715 uint8_t reserved; 3716 } __packed; 3717 3718 /* 3719 * struct iwm_uapsd_misbehaving_ap_notif - FW sends this notification when 3720 * associated AP is identified as improperly implementing uAPSD protocol. 3721 * IWM_PSM_UAPSD_AP_MISBEHAVING_NOTIFICATION = 0x78 3722 * @sta_id: index of station in uCode's station table - associated AP ID in 3723 * this context. 3724 */ 3725 struct iwm_uapsd_misbehaving_ap_notif { 3726 uint32_t sta_id; 3727 uint8_t mac_id; 3728 uint8_t reserved[3]; 3729 } __packed; 3730 3731 /** 3732 * struct iwm_beacon_filter_cmd 3733 * IWM_REPLY_BEACON_FILTERING_CMD = 0xd2 (command) 3734 * @id_and_color: MAC contex identifier 3735 * @bf_energy_delta: Used for RSSI filtering, if in 'normal' state. Send beacon 3736 * to driver if delta in Energy values calculated for this and last 3737 * passed beacon is greater than this threshold. Zero value means that 3738 * the Energy change is ignored for beacon filtering, and beacon will 3739 * not be forced to be sent to driver regardless of this delta. Typical 3740 * energy delta 5dB. 3741 * @bf_roaming_energy_delta: Used for RSSI filtering, if in 'roaming' state. 3742 * Send beacon to driver if delta in Energy values calculated for this 3743 * and last passed beacon is greater than this threshold. Zero value 3744 * means that the Energy change is ignored for beacon filtering while in 3745 * Roaming state, typical energy delta 1dB. 3746 * @bf_roaming_state: Used for RSSI filtering. If absolute Energy values 3747 * calculated for current beacon is less than the threshold, use 3748 * Roaming Energy Delta Threshold, otherwise use normal Energy Delta 3749 * Threshold. Typical energy threshold is -72dBm. 3750 * @bf_temp_threshold: This threshold determines the type of temperature 3751 * filtering (Slow or Fast) that is selected (Units are in Celsuis): 3752 * If the current temperature is above this threshold - Fast filter 3753 * will be used, If the current temperature is below this threshold - 3754 * Slow filter will be used. 3755 * @bf_temp_fast_filter: Send Beacon to driver if delta in temperature values 3756 * calculated for this and the last passed beacon is greater than this 3757 * threshold. Zero value means that the temperature change is ignored for 3758 * beacon filtering; beacons will not be forced to be sent to driver 3759 * regardless of whether its temperature has been changed. 3760 * @bf_temp_slow_filter: Send Beacon to driver if delta in temperature values 3761 * calculated for this and the last passed beacon is greater than this 3762 * threshold. Zero value means that the temperature change is ignored for 3763 * beacon filtering; beacons will not be forced to be sent to driver 3764 * regardless of whether its temperature has been changed. 3765 * @bf_enable_beacon_filter: 1, beacon filtering is enabled; 0, disabled. 3766 * @bf_filter_escape_timer: Send beacons to to driver if no beacons were passed 3767 * for a specific period of time. Units: Beacons. 3768 * @ba_escape_timer: Fully receive and parse beacon if no beacons were passed 3769 * for a longer period of time then this escape-timeout. Units: Beacons. 3770 * @ba_enable_beacon_abort: 1, beacon abort is enabled; 0, disabled. 3771 */ 3772 struct iwm_beacon_filter_cmd { 3773 uint32_t bf_energy_delta; 3774 uint32_t bf_roaming_energy_delta; 3775 uint32_t bf_roaming_state; 3776 uint32_t bf_temp_threshold; 3777 uint32_t bf_temp_fast_filter; 3778 uint32_t bf_temp_slow_filter; 3779 uint32_t bf_enable_beacon_filter; 3780 uint32_t bf_debug_flag; 3781 uint32_t bf_escape_timer; 3782 uint32_t ba_escape_timer; 3783 uint32_t ba_enable_beacon_abort; 3784 } __packed; 3785 3786 /* Beacon filtering and beacon abort */ 3787 #define IWM_BF_ENERGY_DELTA_DEFAULT 5 3788 #define IWM_BF_ENERGY_DELTA_MAX 255 3789 #define IWM_BF_ENERGY_DELTA_MIN 0 3790 3791 #define IWM_BF_ROAMING_ENERGY_DELTA_DEFAULT 1 3792 #define IWM_BF_ROAMING_ENERGY_DELTA_MAX 255 3793 #define IWM_BF_ROAMING_ENERGY_DELTA_MIN 0 3794 3795 #define IWM_BF_ROAMING_STATE_DEFAULT 72 3796 #define IWM_BF_ROAMING_STATE_MAX 255 3797 #define IWM_BF_ROAMING_STATE_MIN 0 3798 3799 #define IWM_BF_TEMP_THRESHOLD_DEFAULT 112 3800 #define IWM_BF_TEMP_THRESHOLD_MAX 255 3801 #define IWM_BF_TEMP_THRESHOLD_MIN 0 3802 3803 #define IWM_BF_TEMP_FAST_FILTER_DEFAULT 1 3804 #define IWM_BF_TEMP_FAST_FILTER_MAX 255 3805 #define IWM_BF_TEMP_FAST_FILTER_MIN 0 3806 3807 #define IWM_BF_TEMP_SLOW_FILTER_DEFAULT 5 3808 #define IWM_BF_TEMP_SLOW_FILTER_MAX 255 3809 #define IWM_BF_TEMP_SLOW_FILTER_MIN 0 3810 3811 #define IWM_BF_ENABLE_BEACON_FILTER_DEFAULT 1 3812 3813 #define IWM_BF_DEBUG_FLAG_DEFAULT 0 3814 3815 #define IWM_BF_ESCAPE_TIMER_DEFAULT 50 3816 #define IWM_BF_ESCAPE_TIMER_MAX 1024 3817 #define IWM_BF_ESCAPE_TIMER_MIN 0 3818 3819 #define IWM_BA_ESCAPE_TIMER_DEFAULT 6 3820 #define IWM_BA_ESCAPE_TIMER_D3 9 3821 #define IWM_BA_ESCAPE_TIMER_MAX 1024 3822 #define IWM_BA_ESCAPE_TIMER_MIN 0 3823 3824 #define IWM_BA_ENABLE_BEACON_ABORT_DEFAULT 1 3825 3826 #define IWM_BF_CMD_CONFIG_DEFAULTS \ 3827 .bf_energy_delta = htole32(IWM_BF_ENERGY_DELTA_DEFAULT), \ 3828 .bf_roaming_energy_delta = \ 3829 htole32(IWM_BF_ROAMING_ENERGY_DELTA_DEFAULT), \ 3830 .bf_roaming_state = htole32(IWM_BF_ROAMING_STATE_DEFAULT), \ 3831 .bf_temp_threshold = htole32(IWM_BF_TEMP_THRESHOLD_DEFAULT), \ 3832 .bf_temp_fast_filter = htole32(IWM_BF_TEMP_FAST_FILTER_DEFAULT), \ 3833 .bf_temp_slow_filter = htole32(IWM_BF_TEMP_SLOW_FILTER_DEFAULT), \ 3834 .bf_debug_flag = htole32(IWM_BF_DEBUG_FLAG_DEFAULT), \ 3835 .bf_escape_timer = htole32(IWM_BF_ESCAPE_TIMER_DEFAULT), \ 3836 .ba_escape_timer = htole32(IWM_BA_ESCAPE_TIMER_DEFAULT) 3837 3838 /* 3839 * END mvm/fw-api-power.h 3840 */ 3841 3842 /* 3843 * BEGIN mvm/fw-api-rs.h 3844 */ 3845 3846 /* 3847 * These serve as indexes into 3848 * struct iwm_rate_info fw_rate_idx_to_plcp[IWM_RATE_COUNT]; 3849 * TODO: avoid overlap between legacy and HT rates 3850 */ 3851 enum { 3852 IWM_RATE_1M_INDEX = 0, 3853 IWM_FIRST_CCK_RATE = IWM_RATE_1M_INDEX, 3854 IWM_RATE_2M_INDEX, 3855 IWM_RATE_5M_INDEX, 3856 IWM_RATE_11M_INDEX, 3857 IWM_LAST_CCK_RATE = IWM_RATE_11M_INDEX, 3858 IWM_RATE_6M_INDEX, 3859 IWM_FIRST_OFDM_RATE = IWM_RATE_6M_INDEX, 3860 IWM_RATE_MCS_0_INDEX = IWM_RATE_6M_INDEX, 3861 IWM_FIRST_HT_RATE = IWM_RATE_MCS_0_INDEX, 3862 IWM_FIRST_VHT_RATE = IWM_RATE_MCS_0_INDEX, 3863 IWM_RATE_9M_INDEX, 3864 IWM_RATE_12M_INDEX, 3865 IWM_RATE_MCS_1_INDEX = IWM_RATE_12M_INDEX, 3866 IWM_RATE_18M_INDEX, 3867 IWM_RATE_MCS_2_INDEX = IWM_RATE_18M_INDEX, 3868 IWM_RATE_24M_INDEX, 3869 IWM_RATE_MCS_3_INDEX = IWM_RATE_24M_INDEX, 3870 IWM_RATE_36M_INDEX, 3871 IWM_RATE_MCS_4_INDEX = IWM_RATE_36M_INDEX, 3872 IWM_RATE_48M_INDEX, 3873 IWM_RATE_MCS_5_INDEX = IWM_RATE_48M_INDEX, 3874 IWM_RATE_54M_INDEX, 3875 IWM_RATE_MCS_6_INDEX = IWM_RATE_54M_INDEX, 3876 IWM_LAST_NON_HT_RATE = IWM_RATE_54M_INDEX, 3877 IWM_RATE_60M_INDEX, 3878 IWM_RATE_MCS_7_INDEX = IWM_RATE_60M_INDEX, 3879 IWM_LAST_HT_RATE = IWM_RATE_MCS_7_INDEX, 3880 IWM_RATE_MCS_8_INDEX, 3881 IWM_RATE_MCS_9_INDEX, 3882 IWM_LAST_VHT_RATE = IWM_RATE_MCS_9_INDEX, 3883 IWM_RATE_COUNT_LEGACY = IWM_LAST_NON_HT_RATE + 1, 3884 IWM_RATE_COUNT = IWM_LAST_VHT_RATE + 1, 3885 }; 3886 3887 #define IWM_RATE_BIT_MSK(r) (1 << (IWM_RATE_##r##M_INDEX)) 3888 3889 /* fw API values for legacy bit rates, both OFDM and CCK */ 3890 enum { 3891 IWM_RATE_6M_PLCP = 13, 3892 IWM_RATE_9M_PLCP = 15, 3893 IWM_RATE_12M_PLCP = 5, 3894 IWM_RATE_18M_PLCP = 7, 3895 IWM_RATE_24M_PLCP = 9, 3896 IWM_RATE_36M_PLCP = 11, 3897 IWM_RATE_48M_PLCP = 1, 3898 IWM_RATE_54M_PLCP = 3, 3899 IWM_RATE_1M_PLCP = 10, 3900 IWM_RATE_2M_PLCP = 20, 3901 IWM_RATE_5M_PLCP = 55, 3902 IWM_RATE_11M_PLCP = 110, 3903 IWM_RATE_INVM_PLCP = -1, 3904 }; 3905 3906 /* 3907 * rate_n_flags bit fields 3908 * 3909 * The 32-bit value has different layouts in the low 8 bites depending on the 3910 * format. There are three formats, HT, VHT and legacy (11abg, with subformats 3911 * for CCK and OFDM). 3912 * 3913 * High-throughput (HT) rate format 3914 * bit 8 is 1, bit 26 is 0, bit 9 is 0 (OFDM) 3915 * Very High-throughput (VHT) rate format 3916 * bit 8 is 0, bit 26 is 1, bit 9 is 0 (OFDM) 3917 * Legacy OFDM rate format for bits 7:0 3918 * bit 8 is 0, bit 26 is 0, bit 9 is 0 (OFDM) 3919 * Legacy CCK rate format for bits 7:0: 3920 * bit 8 is 0, bit 26 is 0, bit 9 is 1 (CCK) 3921 */ 3922 3923 /* Bit 8: (1) HT format, (0) legacy or VHT format */ 3924 #define IWM_RATE_MCS_HT_POS 8 3925 #define IWM_RATE_MCS_HT_MSK (1 << IWM_RATE_MCS_HT_POS) 3926 3927 /* Bit 9: (1) CCK, (0) OFDM. HT (bit 8) must be "0" for this bit to be valid */ 3928 #define IWM_RATE_MCS_CCK_POS 9 3929 #define IWM_RATE_MCS_CCK_MSK (1 << IWM_RATE_MCS_CCK_POS) 3930 3931 /* Bit 26: (1) VHT format, (0) legacy format in bits 8:0 */ 3932 #define IWM_RATE_MCS_VHT_POS 26 3933 #define IWM_RATE_MCS_VHT_MSK (1 << IWM_RATE_MCS_VHT_POS) 3934 3935 3936 /* 3937 * High-throughput (HT) rate format for bits 7:0 3938 * 3939 * 2-0: MCS rate base 3940 * 0) 6 Mbps 3941 * 1) 12 Mbps 3942 * 2) 18 Mbps 3943 * 3) 24 Mbps 3944 * 4) 36 Mbps 3945 * 5) 48 Mbps 3946 * 6) 54 Mbps 3947 * 7) 60 Mbps 3948 * 4-3: 0) Single stream (SISO) 3949 * 1) Dual stream (MIMO) 3950 * 2) Triple stream (MIMO) 3951 * 5: Value of 0x20 in bits 7:0 indicates 6 Mbps HT40 duplicate data 3952 * (bits 7-6 are zero) 3953 * 3954 * Together the low 5 bits work out to the MCS index because we don't 3955 * support MCSes above 15/23, and 0-7 have one stream, 8-15 have two 3956 * streams and 16-23 have three streams. We could also support MCS 32 3957 * which is the duplicate 20 MHz MCS (bit 5 set, all others zero.) 3958 */ 3959 #define IWM_RATE_HT_MCS_RATE_CODE_MSK 0x7 3960 #define IWM_RATE_HT_MCS_NSS_POS 3 3961 #define IWM_RATE_HT_MCS_NSS_MSK (3 << IWM_RATE_HT_MCS_NSS_POS) 3962 3963 /* Bit 10: (1) Use Green Field preamble */ 3964 #define IWM_RATE_HT_MCS_GF_POS 10 3965 #define IWM_RATE_HT_MCS_GF_MSK (1 << IWM_RATE_HT_MCS_GF_POS) 3966 3967 #define IWM_RATE_HT_MCS_INDEX_MSK 0x3f 3968 3969 /* 3970 * Very High-throughput (VHT) rate format for bits 7:0 3971 * 3972 * 3-0: VHT MCS (0-9) 3973 * 5-4: number of streams - 1: 3974 * 0) Single stream (SISO) 3975 * 1) Dual stream (MIMO) 3976 * 2) Triple stream (MIMO) 3977 */ 3978 3979 /* Bit 4-5: (0) SISO, (1) MIMO2 (2) MIMO3 */ 3980 #define IWM_RATE_VHT_MCS_RATE_CODE_MSK 0xf 3981 #define IWM_RATE_VHT_MCS_NSS_POS 4 3982 #define IWM_RATE_VHT_MCS_NSS_MSK (3 << IWM_RATE_VHT_MCS_NSS_POS) 3983 3984 /* 3985 * Legacy OFDM rate format for bits 7:0 3986 * 3987 * 3-0: 0xD) 6 Mbps 3988 * 0xF) 9 Mbps 3989 * 0x5) 12 Mbps 3990 * 0x7) 18 Mbps 3991 * 0x9) 24 Mbps 3992 * 0xB) 36 Mbps 3993 * 0x1) 48 Mbps 3994 * 0x3) 54 Mbps 3995 * (bits 7-4 are 0) 3996 * 3997 * Legacy CCK rate format for bits 7:0: 3998 * bit 8 is 0, bit 26 is 0, bit 9 is 1 (CCK): 3999 * 4000 * 6-0: 10) 1 Mbps 4001 * 20) 2 Mbps 4002 * 55) 5.5 Mbps 4003 * 110) 11 Mbps 4004 * (bit 7 is 0) 4005 */ 4006 #define IWM_RATE_LEGACY_RATE_MSK 0xff 4007 4008 4009 /* 4010 * Bit 11-12: (0) 20MHz, (1) 40MHz, (2) 80MHz, (3) 160MHz 4011 * 0 and 1 are valid for HT and VHT, 2 and 3 only for VHT 4012 */ 4013 #define IWM_RATE_MCS_CHAN_WIDTH_POS 11 4014 #define IWM_RATE_MCS_CHAN_WIDTH_MSK (3 << IWM_RATE_MCS_CHAN_WIDTH_POS) 4015 #define IWM_RATE_MCS_CHAN_WIDTH_20 (0 << IWM_RATE_MCS_CHAN_WIDTH_POS) 4016 #define IWM_RATE_MCS_CHAN_WIDTH_40 (1 << IWM_RATE_MCS_CHAN_WIDTH_POS) 4017 #define IWM_RATE_MCS_CHAN_WIDTH_80 (2 << IWM_RATE_MCS_CHAN_WIDTH_POS) 4018 #define IWM_RATE_MCS_CHAN_WIDTH_160 (3 << IWM_RATE_MCS_CHAN_WIDTH_POS) 4019 4020 /* Bit 13: (1) Short guard interval (0.4 usec), (0) normal GI (0.8 usec) */ 4021 #define IWM_RATE_MCS_SGI_POS 13 4022 #define IWM_RATE_MCS_SGI_MSK (1 << IWM_RATE_MCS_SGI_POS) 4023 4024 /* Bit 14-16: Antenna selection (1) Ant A, (2) Ant B, (4) Ant C */ 4025 #define IWM_RATE_MCS_ANT_POS 14 4026 #define IWM_RATE_MCS_ANT_A_MSK (1 << IWM_RATE_MCS_ANT_POS) 4027 #define IWM_RATE_MCS_ANT_B_MSK (2 << IWM_RATE_MCS_ANT_POS) 4028 #define IWM_RATE_MCS_ANT_C_MSK (4 << IWM_RATE_MCS_ANT_POS) 4029 #define IWM_RATE_MCS_ANT_AB_MSK (IWM_RATE_MCS_ANT_A_MSK | \ 4030 IWM_RATE_MCS_ANT_B_MSK) 4031 #define IWM_RATE_MCS_ANT_ABC_MSK (IWM_RATE_MCS_ANT_AB_MSK | \ 4032 IWM_RATE_MCS_ANT_C_MSK) 4033 #define IWM_RATE_MCS_ANT_MSK IWM_RATE_MCS_ANT_ABC_MSK 4034 #define IWM_RATE_MCS_ANT_NUM 3 4035 4036 /* Bit 17-18: (0) SS, (1) SS*2 */ 4037 #define IWM_RATE_MCS_STBC_POS 17 4038 #define IWM_RATE_MCS_STBC_MSK (1 << IWM_RATE_MCS_STBC_POS) 4039 4040 /* Bit 19: (0) Beamforming is off, (1) Beamforming is on */ 4041 #define IWM_RATE_MCS_BF_POS 19 4042 #define IWM_RATE_MCS_BF_MSK (1 << IWM_RATE_MCS_BF_POS) 4043 4044 /* Bit 20: (0) ZLF is off, (1) ZLF is on */ 4045 #define IWM_RATE_MCS_ZLF_POS 20 4046 #define IWM_RATE_MCS_ZLF_MSK (1 << IWM_RATE_MCS_ZLF_POS) 4047 4048 /* Bit 24-25: (0) 20MHz (no dup), (1) 2x20MHz, (2) 4x20MHz, 3 8x20MHz */ 4049 #define IWM_RATE_MCS_DUP_POS 24 4050 #define IWM_RATE_MCS_DUP_MSK (3 << IWM_RATE_MCS_DUP_POS) 4051 4052 /* Bit 27: (1) LDPC enabled, (0) LDPC disabled */ 4053 #define IWM_RATE_MCS_LDPC_POS 27 4054 #define IWM_RATE_MCS_LDPC_MSK (1 << IWM_RATE_MCS_LDPC_POS) 4055 4056 4057 /* Link Quality definitions */ 4058 4059 /* # entries in rate scale table to support Tx retries */ 4060 #define IWM_LQ_MAX_RETRY_NUM 16 4061 4062 /* Link quality command flags bit fields */ 4063 4064 /* Bit 0: (0) Don't use RTS (1) Use RTS */ 4065 #define IWM_LQ_FLAG_USE_RTS_POS 0 4066 #define IWM_LQ_FLAG_USE_RTS_MSK (1 << IWM_LQ_FLAG_USE_RTS_POS) 4067 4068 /* Bit 1-3: LQ command color. Used to match responses to LQ commands */ 4069 #define IWM_LQ_FLAG_COLOR_POS 1 4070 #define IWM_LQ_FLAG_COLOR_MSK (7 << IWM_LQ_FLAG_COLOR_POS) 4071 4072 /* Bit 4-5: Tx RTS BW Signalling 4073 * (0) No RTS BW signalling 4074 * (1) Static BW signalling 4075 * (2) Dynamic BW signalling 4076 */ 4077 #define IWM_LQ_FLAG_RTS_BW_SIG_POS 4 4078 #define IWM_LQ_FLAG_RTS_BW_SIG_NONE (0 << IWM_LQ_FLAG_RTS_BW_SIG_POS) 4079 #define IWM_LQ_FLAG_RTS_BW_SIG_STATIC (1 << IWM_LQ_FLAG_RTS_BW_SIG_POS) 4080 #define IWM_LQ_FLAG_RTS_BW_SIG_DYNAMIC (2 << IWM_LQ_FLAG_RTS_BW_SIG_POS) 4081 4082 /* Bit 6: (0) No dynamic BW selection (1) Allow dynamic BW selection 4083 * Dyanmic BW selection allows Tx with narrower BW then requested in rates 4084 */ 4085 #define IWM_LQ_FLAG_DYNAMIC_BW_POS 6 4086 #define IWM_LQ_FLAG_DYNAMIC_BW_MSK (1 << IWM_LQ_FLAG_DYNAMIC_BW_POS) 4087 4088 /** 4089 * struct iwm_lq_cmd - link quality command 4090 * @sta_id: station to update 4091 * @control: not used 4092 * @flags: combination of IWM_LQ_FLAG_* 4093 * @mimo_delim: the first SISO index in rs_table, which separates MIMO 4094 * and SISO rates 4095 * @single_stream_ant_msk: best antenna for SISO (can be dual in CDD). 4096 * Should be ANT_[ABC] 4097 * @dual_stream_ant_msk: best antennas for MIMO, combination of ANT_[ABC] 4098 * @initial_rate_index: first index from rs_table per AC category 4099 * @agg_time_limit: aggregation max time threshold in usec/100, meaning 4100 * value of 100 is one usec. Range is 100 to 8000 4101 * @agg_disable_start_th: try-count threshold for starting aggregation. 4102 * If a frame has higher try-count, it should not be selected for 4103 * starting an aggregation sequence. 4104 * @agg_frame_cnt_limit: max frame count in an aggregation. 4105 * 0: no limit 4106 * 1: no aggregation (one frame per aggregation) 4107 * 2 - 0x3f: maximal number of frames (up to 3f == 63) 4108 * @rs_table: array of rates for each TX try, each is rate_n_flags, 4109 * meaning it is a combination of IWM_RATE_MCS_* and IWM_RATE_*_PLCP 4110 * @bf_params: beam forming params, currently not used 4111 */ 4112 struct iwm_lq_cmd { 4113 uint8_t sta_id; 4114 uint8_t reserved1; 4115 uint16_t control; 4116 /* LINK_QUAL_GENERAL_PARAMS_API_S_VER_1 */ 4117 uint8_t flags; 4118 uint8_t mimo_delim; 4119 uint8_t single_stream_ant_msk; 4120 uint8_t dual_stream_ant_msk; 4121 uint8_t initial_rate_index[IWM_AC_NUM]; 4122 /* LINK_QUAL_AGG_PARAMS_API_S_VER_1 */ 4123 uint16_t agg_time_limit; 4124 uint8_t agg_disable_start_th; 4125 uint8_t agg_frame_cnt_limit; 4126 uint32_t reserved2; 4127 uint32_t rs_table[IWM_LQ_MAX_RETRY_NUM]; 4128 uint32_t bf_params; 4129 }; /* LINK_QUALITY_CMD_API_S_VER_1 */ 4130 4131 /* 4132 * END mvm/fw-api-rs.h 4133 */ 4134 4135 /* 4136 * BEGIN mvm/fw-api-tx.h 4137 */ 4138 4139 /** 4140 * enum iwm_tx_flags - bitmasks for tx_flags in TX command 4141 * @IWM_TX_CMD_FLG_PROT_REQUIRE: use RTS or CTS-to-self to protect the frame 4142 * @IWM_TX_CMD_FLG_ACK: expect ACK from receiving station 4143 * @IWM_TX_CMD_FLG_STA_RATE: use RS table with initial index from the TX command. 4144 * Otherwise, use rate_n_flags from the TX command 4145 * @IWM_TX_CMD_FLG_BA: this frame is a block ack 4146 * @IWM_TX_CMD_FLG_BAR: this frame is a BA request, immediate BAR is expected 4147 * Must set IWM_TX_CMD_FLG_ACK with this flag. 4148 * @IWM_TX_CMD_FLG_TXOP_PROT: protect frame with full TXOP protection 4149 * @IWM_TX_CMD_FLG_VHT_NDPA: mark frame is NDPA for VHT beamformer sequence 4150 * @IWM_TX_CMD_FLG_HT_NDPA: mark frame is NDPA for HT beamformer sequence 4151 * @IWM_TX_CMD_FLG_CSI_FDBK2HOST: mark to send feedback to host (only if good CRC) 4152 * @IWM_TX_CMD_FLG_BT_DIS: disable BT priority for this frame 4153 * @IWM_TX_CMD_FLG_SEQ_CTL: set if FW should override the sequence control. 4154 * Should be set for mgmt, non-QOS data, mcast, bcast and in scan command 4155 * @IWM_TX_CMD_FLG_MORE_FRAG: this frame is non-last MPDU 4156 * @IWM_TX_CMD_FLG_NEXT_FRAME: this frame includes information of the next frame 4157 * @IWM_TX_CMD_FLG_TSF: FW should calculate and insert TSF in the frame 4158 * Should be set for beacons and probe responses 4159 * @IWM_TX_CMD_FLG_CALIB: activate PA TX power calibrations 4160 * @IWM_TX_CMD_FLG_KEEP_SEQ_CTL: if seq_ctl is set, don't increase inner seq count 4161 * @IWM_TX_CMD_FLG_AGG_START: allow this frame to start aggregation 4162 * @IWM_TX_CMD_FLG_MH_PAD: driver inserted 2 byte padding after MAC header. 4163 * Should be set for 26/30 length MAC headers 4164 * @IWM_TX_CMD_FLG_RESP_TO_DRV: zero this if the response should go only to FW 4165 * @IWM_TX_CMD_FLG_CCMP_AGG: this frame uses CCMP for aggregation acceleration 4166 * @IWM_TX_CMD_FLG_TKIP_MIC_DONE: FW already performed TKIP MIC calculation 4167 * @IWM_TX_CMD_FLG_DUR: disable duration overwriting used in PS-Poll Assoc-id 4168 * @IWM_TX_CMD_FLG_FW_DROP: FW should mark frame to be dropped 4169 * @IWM_TX_CMD_FLG_EXEC_PAPD: execute PAPD 4170 * @IWM_TX_CMD_FLG_PAPD_TYPE: 0 for reference power, 1 for nominal power 4171 * @IWM_TX_CMD_FLG_HCCA_CHUNK: mark start of TSPEC chunk 4172 */ 4173 enum iwm_tx_flags { 4174 IWM_TX_CMD_FLG_PROT_REQUIRE = (1 << 0), 4175 IWM_TX_CMD_FLG_ACK = (1 << 3), 4176 IWM_TX_CMD_FLG_STA_RATE = (1 << 4), 4177 IWM_TX_CMD_FLG_BA = (1 << 5), 4178 IWM_TX_CMD_FLG_BAR = (1 << 6), 4179 IWM_TX_CMD_FLG_TXOP_PROT = (1 << 7), 4180 IWM_TX_CMD_FLG_VHT_NDPA = (1 << 8), 4181 IWM_TX_CMD_FLG_HT_NDPA = (1 << 9), 4182 IWM_TX_CMD_FLG_CSI_FDBK2HOST = (1 << 10), 4183 IWM_TX_CMD_FLG_BT_DIS = (1 << 12), 4184 IWM_TX_CMD_FLG_SEQ_CTL = (1 << 13), 4185 IWM_TX_CMD_FLG_MORE_FRAG = (1 << 14), 4186 IWM_TX_CMD_FLG_NEXT_FRAME = (1 << 15), 4187 IWM_TX_CMD_FLG_TSF = (1 << 16), 4188 IWM_TX_CMD_FLG_CALIB = (1 << 17), 4189 IWM_TX_CMD_FLG_KEEP_SEQ_CTL = (1 << 18), 4190 IWM_TX_CMD_FLG_AGG_START = (1 << 19), 4191 IWM_TX_CMD_FLG_MH_PAD = (1 << 20), 4192 IWM_TX_CMD_FLG_RESP_TO_DRV = (1 << 21), 4193 IWM_TX_CMD_FLG_CCMP_AGG = (1 << 22), 4194 IWM_TX_CMD_FLG_TKIP_MIC_DONE = (1 << 23), 4195 IWM_TX_CMD_FLG_DUR = (1 << 25), 4196 IWM_TX_CMD_FLG_FW_DROP = (1 << 26), 4197 IWM_TX_CMD_FLG_EXEC_PAPD = (1 << 27), 4198 IWM_TX_CMD_FLG_PAPD_TYPE = (1 << 28), 4199 IWM_TX_CMD_FLG_HCCA_CHUNK = (1 << 31) 4200 }; /* IWM_TX_FLAGS_BITS_API_S_VER_1 */ 4201 4202 /** 4203 * enum iwm_tx_pm_timeouts - pm timeout values in TX command 4204 * @IWM_PM_FRAME_NONE: no need to suspend sleep mode 4205 * @IWM_PM_FRAME_MGMT: fw suspend sleep mode for 100TU 4206 * @IWM_PM_FRAME_ASSOC: fw suspend sleep mode for 10sec 4207 */ 4208 enum iwm_tx_pm_timeouts { 4209 IWM_PM_FRAME_NONE = 0, 4210 IWM_PM_FRAME_MGMT = 2, 4211 IWM_PM_FRAME_ASSOC = 3, 4212 }; 4213 4214 /* 4215 * TX command security control 4216 */ 4217 #define IWM_TX_CMD_SEC_WEP 0x01 4218 #define IWM_TX_CMD_SEC_CCM 0x02 4219 #define IWM_TX_CMD_SEC_TKIP 0x03 4220 #define IWM_TX_CMD_SEC_EXT 0x04 4221 #define IWM_TX_CMD_SEC_MSK 0x07 4222 #define IWM_TX_CMD_SEC_WEP_KEY_IDX_POS 6 4223 #define IWM_TX_CMD_SEC_WEP_KEY_IDX_MSK 0xc0 4224 #define IWM_TX_CMD_SEC_KEY128 0x08 4225 4226 /* TODO: how does these values are OK with only 16 bit variable??? */ 4227 /* 4228 * TX command next frame info 4229 * 4230 * bits 0:2 - security control (IWM_TX_CMD_SEC_*) 4231 * bit 3 - immediate ACK required 4232 * bit 4 - rate is taken from STA table 4233 * bit 5 - frame belongs to BA stream 4234 * bit 6 - immediate BA response expected 4235 * bit 7 - unused 4236 * bits 8:15 - Station ID 4237 * bits 16:31 - rate 4238 */ 4239 #define IWM_TX_CMD_NEXT_FRAME_ACK_MSK (0x8) 4240 #define IWM_TX_CMD_NEXT_FRAME_STA_RATE_MSK (0x10) 4241 #define IWM_TX_CMD_NEXT_FRAME_BA_MSK (0x20) 4242 #define IWM_TX_CMD_NEXT_FRAME_IMM_BA_RSP_MSK (0x40) 4243 #define IWM_TX_CMD_NEXT_FRAME_FLAGS_MSK (0xf8) 4244 #define IWM_TX_CMD_NEXT_FRAME_STA_ID_MSK (0xff00) 4245 #define IWM_TX_CMD_NEXT_FRAME_STA_ID_POS (8) 4246 #define IWM_TX_CMD_NEXT_FRAME_RATE_MSK (0xffff0000) 4247 #define IWM_TX_CMD_NEXT_FRAME_RATE_POS (16) 4248 4249 /* 4250 * TX command Frame life time in us - to be written in pm_frame_timeout 4251 */ 4252 #define IWM_TX_CMD_LIFE_TIME_INFINITE 0xFFFFFFFF 4253 #define IWM_TX_CMD_LIFE_TIME_DEFAULT 2000000 /* 2000 ms*/ 4254 #define IWM_TX_CMD_LIFE_TIME_PROBE_RESP 40000 /* 40 ms */ 4255 #define IWM_TX_CMD_LIFE_TIME_EXPIRED_FRAME 0 4256 4257 /* 4258 * TID for non QoS frames - to be written in tid_tspec 4259 */ 4260 #define IWM_TID_NON_QOS IWM_MAX_TID_COUNT 4261 4262 /* 4263 * Limits on the retransmissions - to be written in {data,rts}_retry_limit 4264 */ 4265 #define IWM_DEFAULT_TX_RETRY 15 4266 #define IWM_MGMT_DFAULT_RETRY_LIMIT 3 4267 #define IWM_RTS_DFAULT_RETRY_LIMIT 60 4268 #define IWM_BAR_DFAULT_RETRY_LIMIT 60 4269 #define IWM_LOW_RETRY_LIMIT 7 4270 4271 /* TODO: complete documentation for try_cnt and btkill_cnt */ 4272 /** 4273 * struct iwm_tx_cmd - TX command struct to FW 4274 * ( IWM_TX_CMD = 0x1c ) 4275 * @len: in bytes of the payload, see below for details 4276 * @next_frame_len: same as len, but for next frame (0 if not applicable) 4277 * Used for fragmentation and bursting, but not in 11n aggregation. 4278 * @tx_flags: combination of IWM_TX_CMD_FLG_* 4279 * @rate_n_flags: rate for *all* Tx attempts, if IWM_TX_CMD_FLG_STA_RATE_MSK is 4280 * cleared. Combination of IWM_RATE_MCS_* 4281 * @sta_id: index of destination station in FW station table 4282 * @sec_ctl: security control, IWM_TX_CMD_SEC_* 4283 * @initial_rate_index: index into the rate table for initial TX attempt. 4284 * Applied if IWM_TX_CMD_FLG_STA_RATE_MSK is set, normally 0 for data frames. 4285 * @key: security key 4286 * @next_frame_flags: IWM_TX_CMD_SEC_* and IWM_TX_CMD_NEXT_FRAME_* 4287 * @life_time: frame life time (usecs??) 4288 * @dram_lsb_ptr: Physical address of scratch area in the command (try_cnt + 4289 * btkill_cnd + reserved), first 32 bits. "0" disables usage. 4290 * @dram_msb_ptr: upper bits of the scratch physical address 4291 * @rts_retry_limit: max attempts for RTS 4292 * @data_retry_limit: max attempts to send the data packet 4293 * @tid_spec: TID/tspec 4294 * @pm_frame_timeout: PM TX frame timeout 4295 * @driver_txop: duration od EDCA TXOP, in 32-usec units. Set this if not 4296 * specified by HCCA protocol 4297 * 4298 * The byte count (both len and next_frame_len) includes MAC header 4299 * (24/26/30/32 bytes) 4300 * + 2 bytes pad if 26/30 header size 4301 * + 8 byte IV for CCM or TKIP (not used for WEP) 4302 * + Data payload 4303 * + 8-byte MIC (not used for CCM/WEP) 4304 * It does not include post-MAC padding, i.e., 4305 * MIC (CCM) 8 bytes, ICV (WEP/TKIP/CKIP) 4 bytes, CRC 4 bytes. 4306 * Range of len: 14-2342 bytes. 4307 * 4308 * After the struct fields the MAC header is placed, plus any padding, 4309 * and then the actial payload. 4310 */ 4311 struct iwm_tx_cmd { 4312 uint16_t len; 4313 uint16_t next_frame_len; 4314 uint32_t tx_flags; 4315 struct { 4316 uint8_t try_cnt; 4317 uint8_t btkill_cnt; 4318 uint16_t reserved; 4319 } scratch; /* DRAM_SCRATCH_API_U_VER_1 */ 4320 uint32_t rate_n_flags; 4321 uint8_t sta_id; 4322 uint8_t sec_ctl; 4323 uint8_t initial_rate_index; 4324 uint8_t reserved2; 4325 uint8_t key[16]; 4326 uint16_t next_frame_flags; 4327 uint16_t reserved3; 4328 uint32_t life_time; 4329 uint32_t dram_lsb_ptr; 4330 uint8_t dram_msb_ptr; 4331 uint8_t rts_retry_limit; 4332 uint8_t data_retry_limit; 4333 uint8_t tid_tspec; 4334 uint16_t pm_frame_timeout; 4335 uint16_t driver_txop; 4336 uint8_t payload[0]; 4337 struct ieee80211_frame hdr[0]; 4338 } __packed; /* IWM_TX_CMD_API_S_VER_3 */ 4339 4340 /* 4341 * TX response related data 4342 */ 4343 4344 /* 4345 * enum iwm_tx_status - status that is returned by the fw after attempts to Tx 4346 * @IWM_TX_STATUS_SUCCESS: 4347 * @IWM_TX_STATUS_DIRECT_DONE: 4348 * @IWM_TX_STATUS_POSTPONE_DELAY: 4349 * @IWM_TX_STATUS_POSTPONE_FEW_BYTES: 4350 * @IWM_TX_STATUS_POSTPONE_BT_PRIO: 4351 * @IWM_TX_STATUS_POSTPONE_QUIET_PERIOD: 4352 * @IWM_TX_STATUS_POSTPONE_CALC_TTAK: 4353 * @IWM_TX_STATUS_FAIL_INTERNAL_CROSSED_RETRY: 4354 * @IWM_TX_STATUS_FAIL_SHORT_LIMIT: 4355 * @IWM_TX_STATUS_FAIL_LONG_LIMIT: 4356 * @IWM_TX_STATUS_FAIL_UNDERRUN: 4357 * @IWM_TX_STATUS_FAIL_DRAIN_FLOW: 4358 * @IWM_TX_STATUS_FAIL_RFKILL_FLUSH: 4359 * @IWM_TX_STATUS_FAIL_LIFE_EXPIRE: 4360 * @IWM_TX_STATUS_FAIL_DEST_PS: 4361 * @IWM_TX_STATUS_FAIL_HOST_ABORTED: 4362 * @IWM_TX_STATUS_FAIL_BT_RETRY: 4363 * @IWM_TX_STATUS_FAIL_STA_INVALID: 4364 * @IWM_TX_TATUS_FAIL_FRAG_DROPPED: 4365 * @IWM_TX_STATUS_FAIL_TID_DISABLE: 4366 * @IWM_TX_STATUS_FAIL_FIFO_FLUSHED: 4367 * @IWM_TX_STATUS_FAIL_SMALL_CF_POLL: 4368 * @IWM_TX_STATUS_FAIL_FW_DROP: 4369 * @IWM_TX_STATUS_FAIL_STA_COLOR_MISMATCH: mismatch between color of Tx cmd and 4370 * STA table 4371 * @IWM_TX_FRAME_STATUS_INTERNAL_ABORT: 4372 * @IWM_TX_MODE_MSK: 4373 * @IWM_TX_MODE_NO_BURST: 4374 * @IWM_TX_MODE_IN_BURST_SEQ: 4375 * @IWM_TX_MODE_FIRST_IN_BURST: 4376 * @IWM_TX_QUEUE_NUM_MSK: 4377 * 4378 * Valid only if frame_count =1 4379 * TODO: complete documentation 4380 */ 4381 enum iwm_tx_status { 4382 IWM_TX_STATUS_MSK = 0x000000ff, 4383 IWM_TX_STATUS_SUCCESS = 0x01, 4384 IWM_TX_STATUS_DIRECT_DONE = 0x02, 4385 /* postpone TX */ 4386 IWM_TX_STATUS_POSTPONE_DELAY = 0x40, 4387 IWM_TX_STATUS_POSTPONE_FEW_BYTES = 0x41, 4388 IWM_TX_STATUS_POSTPONE_BT_PRIO = 0x42, 4389 IWM_TX_STATUS_POSTPONE_QUIET_PERIOD = 0x43, 4390 IWM_TX_STATUS_POSTPONE_CALC_TTAK = 0x44, 4391 /* abort TX */ 4392 IWM_TX_STATUS_FAIL_INTERNAL_CROSSED_RETRY = 0x81, 4393 IWM_TX_STATUS_FAIL_SHORT_LIMIT = 0x82, 4394 IWM_TX_STATUS_FAIL_LONG_LIMIT = 0x83, 4395 IWM_TX_STATUS_FAIL_UNDERRUN = 0x84, 4396 IWM_TX_STATUS_FAIL_DRAIN_FLOW = 0x85, 4397 IWM_TX_STATUS_FAIL_RFKILL_FLUSH = 0x86, 4398 IWM_TX_STATUS_FAIL_LIFE_EXPIRE = 0x87, 4399 IWM_TX_STATUS_FAIL_DEST_PS = 0x88, 4400 IWM_TX_STATUS_FAIL_HOST_ABORTED = 0x89, 4401 IWM_TX_STATUS_FAIL_BT_RETRY = 0x8a, 4402 IWM_TX_STATUS_FAIL_STA_INVALID = 0x8b, 4403 IWM_TX_STATUS_FAIL_FRAG_DROPPED = 0x8c, 4404 IWM_TX_STATUS_FAIL_TID_DISABLE = 0x8d, 4405 IWM_TX_STATUS_FAIL_FIFO_FLUSHED = 0x8e, 4406 IWM_TX_STATUS_FAIL_SMALL_CF_POLL = 0x8f, 4407 IWM_TX_STATUS_FAIL_FW_DROP = 0x90, 4408 IWM_TX_STATUS_FAIL_STA_COLOR_MISMATCH = 0x91, 4409 IWM_TX_STATUS_INTERNAL_ABORT = 0x92, 4410 IWM_TX_MODE_MSK = 0x00000f00, 4411 IWM_TX_MODE_NO_BURST = 0x00000000, 4412 IWM_TX_MODE_IN_BURST_SEQ = 0x00000100, 4413 IWM_TX_MODE_FIRST_IN_BURST = 0x00000200, 4414 IWM_TX_QUEUE_NUM_MSK = 0x0001f000, 4415 IWM_TX_NARROW_BW_MSK = 0x00060000, 4416 IWM_TX_NARROW_BW_1DIV2 = 0x00020000, 4417 IWM_TX_NARROW_BW_1DIV4 = 0x00040000, 4418 IWM_TX_NARROW_BW_1DIV8 = 0x00060000, 4419 }; 4420 4421 /* 4422 * enum iwm_tx_agg_status - TX aggregation status 4423 * @IWM_AGG_TX_STATE_STATUS_MSK: 4424 * @IWM_AGG_TX_STATE_TRANSMITTED: 4425 * @IWM_AGG_TX_STATE_UNDERRUN: 4426 * @IWM_AGG_TX_STATE_BT_PRIO: 4427 * @IWM_AGG_TX_STATE_FEW_BYTES: 4428 * @IWM_AGG_TX_STATE_ABORT: 4429 * @IWM_AGG_TX_STATE_LAST_SENT_TTL: 4430 * @IWM_AGG_TX_STATE_LAST_SENT_TRY_CNT: 4431 * @IWM_AGG_TX_STATE_LAST_SENT_BT_KILL: 4432 * @IWM_AGG_TX_STATE_SCD_QUERY: 4433 * @IWM_AGG_TX_STATE_TEST_BAD_CRC32: 4434 * @IWM_AGG_TX_STATE_RESPONSE: 4435 * @IWM_AGG_TX_STATE_DUMP_TX: 4436 * @IWM_AGG_TX_STATE_DELAY_TX: 4437 * @IWM_AGG_TX_STATE_TRY_CNT_MSK: Retry count for 1st frame in aggregation (retries 4438 * occur if tx failed for this frame when it was a member of a previous 4439 * aggregation block). If rate scaling is used, retry count indicates the 4440 * rate table entry used for all frames in the new agg. 4441 *@ IWM_AGG_TX_STATE_SEQ_NUM_MSK: Command ID and sequence number of Tx command for 4442 * this frame 4443 * 4444 * TODO: complete documentation 4445 */ 4446 enum iwm_tx_agg_status { 4447 IWM_AGG_TX_STATE_STATUS_MSK = 0x00fff, 4448 IWM_AGG_TX_STATE_TRANSMITTED = 0x000, 4449 IWM_AGG_TX_STATE_UNDERRUN = 0x001, 4450 IWM_AGG_TX_STATE_BT_PRIO = 0x002, 4451 IWM_AGG_TX_STATE_FEW_BYTES = 0x004, 4452 IWM_AGG_TX_STATE_ABORT = 0x008, 4453 IWM_AGG_TX_STATE_LAST_SENT_TTL = 0x010, 4454 IWM_AGG_TX_STATE_LAST_SENT_TRY_CNT = 0x020, 4455 IWM_AGG_TX_STATE_LAST_SENT_BT_KILL = 0x040, 4456 IWM_AGG_TX_STATE_SCD_QUERY = 0x080, 4457 IWM_AGG_TX_STATE_TEST_BAD_CRC32 = 0x0100, 4458 IWM_AGG_TX_STATE_RESPONSE = 0x1ff, 4459 IWM_AGG_TX_STATE_DUMP_TX = 0x200, 4460 IWM_AGG_TX_STATE_DELAY_TX = 0x400, 4461 IWM_AGG_TX_STATE_TRY_CNT_POS = 12, 4462 IWM_AGG_TX_STATE_TRY_CNT_MSK = 0xf << IWM_AGG_TX_STATE_TRY_CNT_POS, 4463 }; 4464 4465 #define IWM_AGG_TX_STATE_LAST_SENT_MSK (IWM_AGG_TX_STATE_LAST_SENT_TTL| \ 4466 IWM_AGG_TX_STATE_LAST_SENT_TRY_CNT| \ 4467 IWM_AGG_TX_STATE_LAST_SENT_BT_KILL) 4468 4469 /* 4470 * The mask below describes a status where we are absolutely sure that the MPDU 4471 * wasn't sent. For BA/Underrun we cannot be that sure. All we know that we've 4472 * written the bytes to the TXE, but we know nothing about what the DSP did. 4473 */ 4474 #define IWM_AGG_TX_STAT_FRAME_NOT_SENT (IWM_AGG_TX_STATE_FEW_BYTES | \ 4475 IWM_AGG_TX_STATE_ABORT | \ 4476 IWM_AGG_TX_STATE_SCD_QUERY) 4477 4478 /* 4479 * IWM_REPLY_TX = 0x1c (response) 4480 * 4481 * This response may be in one of two slightly different formats, indicated 4482 * by the frame_count field: 4483 * 4484 * 1) No aggregation (frame_count == 1). This reports Tx results for a single 4485 * frame. Multiple attempts, at various bit rates, may have been made for 4486 * this frame. 4487 * 4488 * 2) Aggregation (frame_count > 1). This reports Tx results for two or more 4489 * frames that used block-acknowledge. All frames were transmitted at 4490 * same rate. Rate scaling may have been used if first frame in this new 4491 * agg block failed in previous agg block(s). 4492 * 4493 * Note that, for aggregation, ACK (block-ack) status is not delivered 4494 * here; block-ack has not been received by the time the device records 4495 * this status. 4496 * This status relates to reasons the tx might have been blocked or aborted 4497 * within the device, rather than whether it was received successfully by 4498 * the destination station. 4499 */ 4500 4501 /** 4502 * struct iwm_agg_tx_status - per packet TX aggregation status 4503 * @status: enum iwm_tx_agg_status 4504 * @sequence: Sequence # for this frame's Tx cmd (not SSN!) 4505 */ 4506 struct iwm_agg_tx_status { 4507 uint16_t status; 4508 uint16_t sequence; 4509 } __packed; 4510 4511 /* 4512 * definitions for initial rate index field 4513 * bits [3:0] initial rate index 4514 * bits [6:4] rate table color, used for the initial rate 4515 * bit-7 invalid rate indication 4516 */ 4517 #define IWM_TX_RES_INIT_RATE_INDEX_MSK 0x0f 4518 #define IWM_TX_RES_RATE_TABLE_COLOR_MSK 0x70 4519 #define IWM_TX_RES_INV_RATE_INDEX_MSK 0x80 4520 4521 #define IWM_MVM_TX_RES_GET_TID(_ra_tid) ((_ra_tid) & 0x0f) 4522 #define IWM_MVM_TX_RES_GET_RA(_ra_tid) ((_ra_tid) >> 4) 4523 4524 /** 4525 * struct iwm_mvm_tx_resp - notifies that fw is TXing a packet 4526 * ( IWM_REPLY_TX = 0x1c ) 4527 * @frame_count: 1 no aggregation, >1 aggregation 4528 * @bt_kill_count: num of times blocked by bluetooth (unused for agg) 4529 * @failure_rts: num of failures due to unsuccessful RTS 4530 * @failure_frame: num failures due to no ACK (unused for agg) 4531 * @initial_rate: for non-agg: rate of the successful Tx. For agg: rate of the 4532 * Tx of all the batch. IWM_RATE_MCS_* 4533 * @wireless_media_time: for non-agg: RTS + CTS + frame tx attempts time + ACK. 4534 * for agg: RTS + CTS + aggregation tx time + block-ack time. 4535 * in usec. 4536 * @pa_status: tx power info 4537 * @pa_integ_res_a: tx power info 4538 * @pa_integ_res_b: tx power info 4539 * @pa_integ_res_c: tx power info 4540 * @measurement_req_id: tx power info 4541 * @tfd_info: TFD information set by the FH 4542 * @seq_ctl: sequence control from the Tx cmd 4543 * @byte_cnt: byte count from the Tx cmd 4544 * @tlc_info: TLC rate info 4545 * @ra_tid: bits [3:0] = ra, bits [7:4] = tid 4546 * @frame_ctrl: frame control 4547 * @status: for non-agg: frame status IWM_TX_STATUS_* 4548 * for agg: status of 1st frame, IWM_AGG_TX_STATE_*; other frame status fields 4549 * follow this one, up to frame_count. 4550 * 4551 * After the array of statuses comes the SSN of the SCD. Look at 4552 * %iwm_mvm_get_scd_ssn for more details. 4553 */ 4554 struct iwm_mvm_tx_resp { 4555 uint8_t frame_count; 4556 uint8_t bt_kill_count; 4557 uint8_t failure_rts; 4558 uint8_t failure_frame; 4559 uint32_t initial_rate; 4560 uint16_t wireless_media_time; 4561 4562 uint8_t pa_status; 4563 uint8_t pa_integ_res_a[3]; 4564 uint8_t pa_integ_res_b[3]; 4565 uint8_t pa_integ_res_c[3]; 4566 uint16_t measurement_req_id; 4567 uint16_t reserved; 4568 4569 uint32_t tfd_info; 4570 uint16_t seq_ctl; 4571 uint16_t byte_cnt; 4572 uint8_t tlc_info; 4573 uint8_t ra_tid; 4574 uint16_t frame_ctrl; 4575 4576 struct iwm_agg_tx_status status; 4577 } __packed; /* IWM_TX_RSP_API_S_VER_3 */ 4578 4579 /** 4580 * struct iwm_mvm_ba_notif - notifies about reception of BA 4581 * ( IWM_BA_NOTIF = 0xc5 ) 4582 * @sta_addr_lo32: lower 32 bits of the MAC address 4583 * @sta_addr_hi16: upper 16 bits of the MAC address 4584 * @sta_id: Index of recipient (BA-sending) station in fw's station table 4585 * @tid: tid of the session 4586 * @seq_ctl: 4587 * @bitmap: the bitmap of the BA notification as seen in the air 4588 * @scd_flow: the tx queue this BA relates to 4589 * @scd_ssn: the index of the last contiguously sent packet 4590 * @txed: number of Txed frames in this batch 4591 * @txed_2_done: number of Acked frames in this batch 4592 */ 4593 struct iwm_mvm_ba_notif { 4594 uint32_t sta_addr_lo32; 4595 uint16_t sta_addr_hi16; 4596 uint16_t reserved; 4597 4598 uint8_t sta_id; 4599 uint8_t tid; 4600 uint16_t seq_ctl; 4601 uint64_t bitmap; 4602 uint16_t scd_flow; 4603 uint16_t scd_ssn; 4604 uint8_t txed; 4605 uint8_t txed_2_done; 4606 uint16_t reserved1; 4607 } __packed; 4608 4609 /* 4610 * struct iwm_mac_beacon_cmd - beacon template command 4611 * @tx: the tx commands associated with the beacon frame 4612 * @template_id: currently equal to the mac context id of the coresponding 4613 * mac. 4614 * @tim_idx: the offset of the tim IE in the beacon 4615 * @tim_size: the length of the tim IE 4616 * @frame: the template of the beacon frame 4617 */ 4618 struct iwm_mac_beacon_cmd { 4619 struct iwm_tx_cmd tx; 4620 uint32_t template_id; 4621 uint32_t tim_idx; 4622 uint32_t tim_size; 4623 struct ieee80211_frame frame[0]; 4624 } __packed; 4625 4626 struct iwm_beacon_notif { 4627 struct iwm_mvm_tx_resp beacon_notify_hdr; 4628 uint64_t tsf; 4629 uint32_t ibss_mgr_status; 4630 } __packed; 4631 4632 /** 4633 * enum iwm_dump_control - dump (flush) control flags 4634 * @IWM_DUMP_TX_FIFO_FLUSH: Dump MSDUs until the FIFO is empty 4635 * and the TFD queues are empty. 4636 */ 4637 enum iwm_dump_control { 4638 IWM_DUMP_TX_FIFO_FLUSH = (1 << 1), 4639 }; 4640 4641 /** 4642 * struct iwm_tx_path_flush_cmd -- queue/FIFO flush command 4643 * @queues_ctl: bitmap of queues to flush 4644 * @flush_ctl: control flags 4645 * @reserved: reserved 4646 */ 4647 struct iwm_tx_path_flush_cmd { 4648 uint32_t queues_ctl; 4649 uint16_t flush_ctl; 4650 uint16_t reserved; 4651 } __packed; /* IWM_TX_PATH_FLUSH_CMD_API_S_VER_1 */ 4652 4653 /** 4654 * iwm_mvm_get_scd_ssn - returns the SSN of the SCD 4655 * @tx_resp: the Tx response from the fw (agg or non-agg) 4656 * 4657 * When the fw sends an AMPDU, it fetches the MPDUs one after the other. Since 4658 * it can't know that everything will go well until the end of the AMPDU, it 4659 * can't know in advance the number of MPDUs that will be sent in the current 4660 * batch. This is why it writes the agg Tx response while it fetches the MPDUs. 4661 * Hence, it can't know in advance what the SSN of the SCD will be at the end 4662 * of the batch. This is why the SSN of the SCD is written at the end of the 4663 * whole struct at a variable offset. This function knows how to cope with the 4664 * variable offset and returns the SSN of the SCD. 4665 */ 4666 static inline uint32_t iwm_mvm_get_scd_ssn(struct iwm_mvm_tx_resp *tx_resp) 4667 { 4668 return le32_to_cpup((uint32_t *)&tx_resp->status + 4669 tx_resp->frame_count) & 0xfff; 4670 } 4671 4672 /* 4673 * END mvm/fw-api-tx.h 4674 */ 4675 4676 /* 4677 * BEGIN mvm/fw-api-scan.h 4678 */ 4679 4680 /** 4681 * struct iwm_scd_txq_cfg_cmd - New txq hw scheduler config command 4682 * @token: 4683 * @sta_id: station id 4684 * @tid: 4685 * @scd_queue: scheduler queue to confiug 4686 * @enable: 1 queue enable, 0 queue disable 4687 * @aggregate: 1 aggregated queue, 0 otherwise 4688 * @tx_fifo: %enum iwm_mvm_tx_fifo 4689 * @window: BA window size 4690 * @ssn: SSN for the BA agreement 4691 */ 4692 struct iwm_scd_txq_cfg_cmd { 4693 uint8_t token; 4694 uint8_t sta_id; 4695 uint8_t tid; 4696 uint8_t scd_queue; 4697 uint8_t enable; 4698 uint8_t aggregate; 4699 uint8_t tx_fifo; 4700 uint8_t window; 4701 uint16_t ssn; 4702 uint16_t reserved; 4703 } __packed; /* SCD_QUEUE_CFG_CMD_API_S_VER_1 */ 4704 4705 /** 4706 * struct iwm_scd_txq_cfg_rsp 4707 * @token: taken from the command 4708 * @sta_id: station id from the command 4709 * @tid: tid from the command 4710 * @scd_queue: scd_queue from the command 4711 */ 4712 struct iwm_scd_txq_cfg_rsp { 4713 uint8_t token; 4714 uint8_t sta_id; 4715 uint8_t tid; 4716 uint8_t scd_queue; 4717 } __packed; /* SCD_QUEUE_CFG_RSP_API_S_VER_1 */ 4718 4719 4720 /* Scan Commands, Responses, Notifications */ 4721 4722 /* Masks for iwm_scan_channel.type flags */ 4723 #define IWM_SCAN_CHANNEL_TYPE_ACTIVE (1 << 0) 4724 #define IWM_SCAN_CHANNEL_NSSIDS(x) (((1 << (x)) - 1) << 1) 4725 4726 /* Max number of IEs for direct SSID scans in a command */ 4727 #define IWM_PROBE_OPTION_MAX 20 4728 4729 /** 4730 * struct iwm_ssid_ie - directed scan network information element 4731 * 4732 * Up to 20 of these may appear in IWM_REPLY_SCAN_CMD, 4733 * selected by "type" bit field in struct iwm_scan_channel; 4734 * each channel may select different ssids from among the 20 entries. 4735 * SSID IEs get transmitted in reverse order of entry. 4736 */ 4737 struct iwm_ssid_ie { 4738 uint8_t id; 4739 uint8_t len; 4740 uint8_t ssid[IEEE80211_NWID_LEN]; 4741 } __packed; /* IWM_SCAN_DIRECT_SSID_IE_API_S_VER_1 */ 4742 4743 /* scan offload */ 4744 #define IWM_SCAN_MAX_BLACKLIST_LEN 64 4745 #define IWM_SCAN_SHORT_BLACKLIST_LEN 16 4746 #define IWM_SCAN_MAX_PROFILES 11 4747 #define IWM_SCAN_OFFLOAD_PROBE_REQ_SIZE 512 4748 4749 /* Default watchdog (in MS) for scheduled scan iteration */ 4750 #define IWM_SCHED_SCAN_WATCHDOG cpu_to_le16(15000) 4751 4752 #define IWM_GOOD_CRC_TH_DEFAULT cpu_to_le16(1) 4753 #define IWM_CAN_ABORT_STATUS 1 4754 4755 #define IWM_FULL_SCAN_MULTIPLIER 5 4756 #define IWM_FAST_SCHED_SCAN_ITERATIONS 3 4757 #define IWM_MAX_SCHED_SCAN_PLANS 2 4758 4759 /** 4760 * iwm_scan_schedule_lmac - schedule of scan offload 4761 * @delay: delay between iterations, in seconds. 4762 * @iterations: num of scan iterations 4763 * @full_scan_mul: number of partial scans before each full scan 4764 */ 4765 struct iwm_scan_schedule_lmac { 4766 uint16_t delay; 4767 uint8_t iterations; 4768 uint8_t full_scan_mul; 4769 } __packed; /* SCAN_SCHEDULE_API_S */ 4770 4771 /** 4772 * iwm_scan_req_tx_cmd - SCAN_REQ_TX_CMD_API_S 4773 * @tx_flags: combination of TX_CMD_FLG_* 4774 * @rate_n_flags: rate for *all* Tx attempts, if TX_CMD_FLG_STA_RATE_MSK is 4775 * cleared. Combination of RATE_MCS_* 4776 * @sta_id: index of destination station in FW station table 4777 * @reserved: for alignment and future use 4778 */ 4779 struct iwm_scan_req_tx_cmd { 4780 uint32_t tx_flags; 4781 uint32_t rate_n_flags; 4782 uint8_t sta_id; 4783 uint8_t reserved[3]; 4784 } __packed; 4785 4786 enum iwm_scan_channel_flags_lmac { 4787 IWM_UNIFIED_SCAN_CHANNEL_FULL = (1 << 27), 4788 IWM_UNIFIED_SCAN_CHANNEL_PARTIAL = (1 << 28), 4789 }; 4790 4791 /** 4792 * iwm_scan_channel_cfg_lmac - SCAN_CHANNEL_CFG_S_VER2 4793 * @flags: bits 1-20: directed scan to i'th ssid 4794 * other bits &enum iwm_scan_channel_flags_lmac 4795 * @channel_number: channel number 1-13 etc 4796 * @iter_count: scan iteration on this channel 4797 * @iter_interval: interval in seconds between iterations on one channel 4798 */ 4799 struct iwm_scan_channel_cfg_lmac { 4800 uint32_t flags; 4801 uint16_t channel_num; 4802 uint16_t iter_count; 4803 uint32_t iter_interval; 4804 } __packed; 4805 4806 /* 4807 * iwm_scan_probe_segment - PROBE_SEGMENT_API_S_VER_1 4808 * @offset: offset in the data block 4809 * @len: length of the segment 4810 */ 4811 struct iwm_scan_probe_segment { 4812 uint16_t offset; 4813 uint16_t len; 4814 } __packed; 4815 4816 /* iwm_scan_probe_req - PROBE_REQUEST_FRAME_API_S_VER_2 4817 * @mac_header: first (and common) part of the probe 4818 * @band_data: band specific data 4819 * @common_data: last (and common) part of the probe 4820 * @buf: raw data block 4821 */ 4822 struct iwm_scan_probe_req { 4823 struct iwm_scan_probe_segment mac_header; 4824 struct iwm_scan_probe_segment band_data[2]; 4825 struct iwm_scan_probe_segment common_data; 4826 uint8_t buf[IWM_SCAN_OFFLOAD_PROBE_REQ_SIZE]; 4827 } __packed; 4828 4829 enum iwm_scan_channel_flags { 4830 IWM_SCAN_CHANNEL_FLAG_EBS = (1 << 0), 4831 IWM_SCAN_CHANNEL_FLAG_EBS_ACCURATE = (1 << 1), 4832 IWM_SCAN_CHANNEL_FLAG_CACHE_ADD = (1 << 2), 4833 }; 4834 4835 /* iwm_scan_channel_opt - CHANNEL_OPTIMIZATION_API_S 4836 * @flags: enum iwm_scan_channel_flags 4837 * @non_ebs_ratio: defines the ratio of number of scan iterations where EBS is 4838 * involved. 4839 * 1 - EBS is disabled. 4840 * 2 - every second scan will be full scan(and so on). 4841 */ 4842 struct iwm_scan_channel_opt { 4843 uint16_t flags; 4844 uint16_t non_ebs_ratio; 4845 } __packed; 4846 4847 /** 4848 * iwm_mvm_lmac_scan_flags 4849 * @IWM_MVM_LMAC_SCAN_FLAG_PASS_ALL: pass all beacons and probe responses 4850 * without filtering. 4851 * @IWM_MVM_LMAC_SCAN_FLAG_PASSIVE: force passive scan on all channels 4852 * @IWM_MVM_LMAC_SCAN_FLAG_PRE_CONNECTION: single channel scan 4853 * @IWM_MVM_LMAC_SCAN_FLAG_ITER_COMPLETE: send iteration complete notification 4854 * @IWM_MVM_LMAC_SCAN_FLAG_MULTIPLE_SSIDS multiple SSID matching 4855 * @IWM_MVM_LMAC_SCAN_FLAG_FRAGMENTED: all passive scans will be fragmented 4856 * @IWM_MVM_LMAC_SCAN_FLAGS_RRM_ENABLED: insert WFA vendor-specific TPC report 4857 * and DS parameter set IEs into probe requests. 4858 * @IWM_MVM_LMAC_SCAN_FLAG_EXTENDED_DWELL: use extended dwell time on channels 4859 * 1, 6 and 11. 4860 * @IWM_MVM_LMAC_SCAN_FLAG_MATCH: Send match found notification on matches 4861 */ 4862 enum iwm_mvm_lmac_scan_flags { 4863 IWM_MVM_LMAC_SCAN_FLAG_PASS_ALL = (1 << 0), 4864 IWM_MVM_LMAC_SCAN_FLAG_PASSIVE = (1 << 1), 4865 IWM_MVM_LMAC_SCAN_FLAG_PRE_CONNECTION = (1 << 2), 4866 IWM_MVM_LMAC_SCAN_FLAG_ITER_COMPLETE = (1 << 3), 4867 IWM_MVM_LMAC_SCAN_FLAG_MULTIPLE_SSIDS = (1 << 4), 4868 IWM_MVM_LMAC_SCAN_FLAG_FRAGMENTED = (1 << 5), 4869 IWM_MVM_LMAC_SCAN_FLAGS_RRM_ENABLED = (1 << 6), 4870 IWM_MVM_LMAC_SCAN_FLAG_EXTENDED_DWELL = (1 << 7), 4871 IWM_MVM_LMAC_SCAN_FLAG_MATCH = (1 << 9), 4872 }; 4873 4874 enum iwm_scan_priority { 4875 IWM_SCAN_PRIORITY_LOW, 4876 IWM_SCAN_PRIORITY_MEDIUM, 4877 IWM_SCAN_PRIORITY_HIGH, 4878 }; 4879 4880 /** 4881 * iwm_scan_req_lmac - SCAN_REQUEST_CMD_API_S_VER_1 4882 * @reserved1: for alignment and future use 4883 * @channel_num: num of channels to scan 4884 * @active-dwell: dwell time for active channels 4885 * @passive-dwell: dwell time for passive channels 4886 * @fragmented-dwell: dwell time for fragmented passive scan 4887 * @extended_dwell: dwell time for channels 1, 6 and 11 (in certain cases) 4888 * @reserved2: for alignment and future use 4889 * @rx_chain_selct: PHY_RX_CHAIN_* flags 4890 * @scan_flags: &enum iwm_mvm_lmac_scan_flags 4891 * @max_out_time: max time (in TU) to be out of associated channel 4892 * @suspend_time: pause scan this long (TUs) when returning to service channel 4893 * @flags: RXON flags 4894 * @filter_flags: RXON filter 4895 * @tx_cmd: tx command for active scan; for 2GHz and for 5GHz 4896 * @direct_scan: list of SSIDs for directed active scan 4897 * @scan_prio: enum iwm_scan_priority 4898 * @iter_num: number of scan iterations 4899 * @delay: delay in seconds before first iteration 4900 * @schedule: two scheduling plans. The first one is finite, the second one can 4901 * be infinite. 4902 * @channel_opt: channel optimization options, for full and partial scan 4903 * @data: channel configuration and probe request packet. 4904 */ 4905 struct iwm_scan_req_lmac { 4906 /* SCAN_REQUEST_FIXED_PART_API_S_VER_7 */ 4907 uint32_t reserved1; 4908 uint8_t n_channels; 4909 uint8_t active_dwell; 4910 uint8_t passive_dwell; 4911 uint8_t fragmented_dwell; 4912 uint8_t extended_dwell; 4913 uint8_t reserved2; 4914 uint16_t rx_chain_select; 4915 uint32_t scan_flags; 4916 uint32_t max_out_time; 4917 uint32_t suspend_time; 4918 /* RX_ON_FLAGS_API_S_VER_1 */ 4919 uint32_t flags; 4920 uint32_t filter_flags; 4921 struct iwm_scan_req_tx_cmd tx_cmd[2]; 4922 struct iwm_ssid_ie direct_scan[IWM_PROBE_OPTION_MAX]; 4923 uint32_t scan_prio; 4924 /* SCAN_REQ_PERIODIC_PARAMS_API_S */ 4925 uint32_t iter_num; 4926 uint32_t delay; 4927 struct iwm_scan_schedule_lmac schedule[IWM_MAX_SCHED_SCAN_PLANS]; 4928 struct iwm_scan_channel_opt channel_opt[2]; 4929 uint8_t data[]; 4930 } __packed; 4931 4932 /** 4933 * iwm_scan_offload_complete - PERIODIC_SCAN_COMPLETE_NTF_API_S_VER_2 4934 * @last_schedule_line: last schedule line executed (fast or regular) 4935 * @last_schedule_iteration: last scan iteration executed before scan abort 4936 * @status: enum iwm_scan_offload_complete_status 4937 * @ebs_status: EBS success status &enum iwm_scan_ebs_status 4938 * @time_after_last_iter; time in seconds elapsed after last iteration 4939 */ 4940 struct iwm_periodic_scan_complete { 4941 uint8_t last_schedule_line; 4942 uint8_t last_schedule_iteration; 4943 uint8_t status; 4944 uint8_t ebs_status; 4945 uint32_t time_after_last_iter; 4946 uint32_t reserved; 4947 } __packed; 4948 4949 /* How many statistics are gathered for each channel */ 4950 #define IWM_SCAN_RESULTS_STATISTICS 1 4951 4952 /** 4953 * enum iwm_scan_complete_status - status codes for scan complete notifications 4954 * @IWM_SCAN_COMP_STATUS_OK: scan completed successfully 4955 * @IWM_SCAN_COMP_STATUS_ABORT: scan was aborted by user 4956 * @IWM_SCAN_COMP_STATUS_ERR_SLEEP: sending null sleep packet failed 4957 * @IWM_SCAN_COMP_STATUS_ERR_CHAN_TIMEOUT: timeout before channel is ready 4958 * @IWM_SCAN_COMP_STATUS_ERR_PROBE: sending probe request failed 4959 * @IWM_SCAN_COMP_STATUS_ERR_WAKEUP: sending null wakeup packet failed 4960 * @IWM_SCAN_COMP_STATUS_ERR_ANTENNAS: invalid antennas chosen at scan command 4961 * @IWM_SCAN_COMP_STATUS_ERR_INTERNAL: internal error caused scan abort 4962 * @IWM_SCAN_COMP_STATUS_ERR_COEX: medium was lost ot WiMax 4963 * @IWM_SCAN_COMP_STATUS_P2P_ACTION_OK: P2P public action frame TX was successful 4964 * (not an error!) 4965 * @IWM_SCAN_COMP_STATUS_ITERATION_END: indicates end of one repeatition the driver 4966 * asked for 4967 * @IWM_SCAN_COMP_STATUS_ERR_ALLOC_TE: scan could not allocate time events 4968 */ 4969 enum iwm_scan_complete_status { 4970 IWM_SCAN_COMP_STATUS_OK = 0x1, 4971 IWM_SCAN_COMP_STATUS_ABORT = 0x2, 4972 IWM_SCAN_COMP_STATUS_ERR_SLEEP = 0x3, 4973 IWM_SCAN_COMP_STATUS_ERR_CHAN_TIMEOUT = 0x4, 4974 IWM_SCAN_COMP_STATUS_ERR_PROBE = 0x5, 4975 IWM_SCAN_COMP_STATUS_ERR_WAKEUP = 0x6, 4976 IWM_SCAN_COMP_STATUS_ERR_ANTENNAS = 0x7, 4977 IWM_SCAN_COMP_STATUS_ERR_INTERNAL = 0x8, 4978 IWM_SCAN_COMP_STATUS_ERR_COEX = 0x9, 4979 IWM_SCAN_COMP_STATUS_P2P_ACTION_OK = 0xA, 4980 IWM_SCAN_COMP_STATUS_ITERATION_END = 0x0B, 4981 IWM_SCAN_COMP_STATUS_ERR_ALLOC_TE = 0x0C, 4982 }; 4983 4984 /** 4985 * struct iwm_scan_results_notif - scan results for one channel 4986 * ( IWM_SCAN_RESULTS_NOTIFICATION = 0x83 ) 4987 * @channel: which channel the results are from 4988 * @band: 0 for 5.2 GHz, 1 for 2.4 GHz 4989 * @probe_status: IWM_SCAN_PROBE_STATUS_*, indicates success of probe request 4990 * @num_probe_not_sent: # of request that weren't sent due to not enough time 4991 * @duration: duration spent in channel, in usecs 4992 * @statistics: statistics gathered for this channel 4993 */ 4994 struct iwm_scan_results_notif { 4995 uint8_t channel; 4996 uint8_t band; 4997 uint8_t probe_status; 4998 uint8_t num_probe_not_sent; 4999 uint32_t duration; 5000 uint32_t statistics[IWM_SCAN_RESULTS_STATISTICS]; 5001 } __packed; /* IWM_SCAN_RESULT_NTF_API_S_VER_2 */ 5002 5003 enum iwm_scan_framework_client { 5004 IWM_SCAN_CLIENT_SCHED_SCAN = (1 << 0), 5005 IWM_SCAN_CLIENT_NETDETECT = (1 << 1), 5006 IWM_SCAN_CLIENT_ASSET_TRACKING = (1 << 2), 5007 }; 5008 5009 /** 5010 * iwm_scan_offload_blacklist - IWM_SCAN_OFFLOAD_BLACKLIST_S 5011 * @ssid: MAC address to filter out 5012 * @reported_rssi: AP rssi reported to the host 5013 * @client_bitmap: clients ignore this entry - enum scan_framework_client 5014 */ 5015 struct iwm_scan_offload_blacklist { 5016 uint8_t ssid[IEEE80211_ADDR_LEN]; 5017 uint8_t reported_rssi; 5018 uint8_t client_bitmap; 5019 } __packed; 5020 5021 enum iwm_scan_offload_network_type { 5022 IWM_NETWORK_TYPE_BSS = 1, 5023 IWM_NETWORK_TYPE_IBSS = 2, 5024 IWM_NETWORK_TYPE_ANY = 3, 5025 }; 5026 5027 enum iwm_scan_offload_band_selection { 5028 IWM_SCAN_OFFLOAD_SELECT_2_4 = 0x4, 5029 IWM_SCAN_OFFLOAD_SELECT_5_2 = 0x8, 5030 IWM_SCAN_OFFLOAD_SELECT_ANY = 0xc, 5031 }; 5032 5033 /** 5034 * iwm_scan_offload_profile - IWM_SCAN_OFFLOAD_PROFILE_S 5035 * @ssid_index: index to ssid list in fixed part 5036 * @unicast_cipher: encryption olgorithm to match - bitmap 5037 * @aut_alg: authentication olgorithm to match - bitmap 5038 * @network_type: enum iwm_scan_offload_network_type 5039 * @band_selection: enum iwm_scan_offload_band_selection 5040 * @client_bitmap: clients waiting for match - enum scan_framework_client 5041 */ 5042 struct iwm_scan_offload_profile { 5043 uint8_t ssid_index; 5044 uint8_t unicast_cipher; 5045 uint8_t auth_alg; 5046 uint8_t network_type; 5047 uint8_t band_selection; 5048 uint8_t client_bitmap; 5049 uint8_t reserved[2]; 5050 } __packed; 5051 5052 /** 5053 * iwm_scan_offload_profile_cfg - IWM_SCAN_OFFLOAD_PROFILES_CFG_API_S_VER_1 5054 * @blaclist: AP list to filter off from scan results 5055 * @profiles: profiles to search for match 5056 * @blacklist_len: length of blacklist 5057 * @num_profiles: num of profiles in the list 5058 * @match_notify: clients waiting for match found notification 5059 * @pass_match: clients waiting for the results 5060 * @active_clients: active clients bitmap - enum scan_framework_client 5061 * @any_beacon_notify: clients waiting for match notification without match 5062 */ 5063 struct iwm_scan_offload_profile_cfg { 5064 struct iwm_scan_offload_profile profiles[IWM_SCAN_MAX_PROFILES]; 5065 uint8_t blacklist_len; 5066 uint8_t num_profiles; 5067 uint8_t match_notify; 5068 uint8_t pass_match; 5069 uint8_t active_clients; 5070 uint8_t any_beacon_notify; 5071 uint8_t reserved[2]; 5072 } __packed; 5073 5074 enum iwm_scan_offload_complete_status { 5075 IWM_SCAN_OFFLOAD_COMPLETED = 1, 5076 IWM_SCAN_OFFLOAD_ABORTED = 2, 5077 }; 5078 5079 enum iwm_scan_ebs_status { 5080 IWM_SCAN_EBS_SUCCESS, 5081 IWM_SCAN_EBS_FAILED, 5082 IWM_SCAN_EBS_CHAN_NOT_FOUND, 5083 IWM_SCAN_EBS_INACTIVE, 5084 }; 5085 5086 /** 5087 * struct iwm_lmac_scan_complete_notif - notifies end of scanning (all channels) 5088 * SCAN_COMPLETE_NTF_API_S_VER_3 5089 * @scanned_channels: number of channels scanned (and number of valid results) 5090 * @status: one of SCAN_COMP_STATUS_* 5091 * @bt_status: BT on/off status 5092 * @last_channel: last channel that was scanned 5093 * @tsf_low: TSF timer (lower half) in usecs 5094 * @tsf_high: TSF timer (higher half) in usecs 5095 * @results: an array of scan results, only "scanned_channels" of them are valid 5096 */ 5097 struct iwm_lmac_scan_complete_notif { 5098 uint8_t scanned_channels; 5099 uint8_t status; 5100 uint8_t bt_status; 5101 uint8_t last_channel; 5102 uint32_t tsf_low; 5103 uint32_t tsf_high; 5104 struct iwm_scan_results_notif results[]; 5105 } __packed; 5106 5107 5108 /* 5109 * END mvm/fw-api-scan.h 5110 */ 5111 5112 /* 5113 * BEGIN mvm/fw-api-sta.h 5114 */ 5115 5116 /* UMAC Scan API */ 5117 5118 /* The maximum of either of these cannot exceed 8, because we use an 5119 * 8-bit mask (see IWM_MVM_SCAN_MASK). 5120 */ 5121 #define IWM_MVM_MAX_UMAC_SCANS 8 5122 #define IWM_MVM_MAX_LMAC_SCANS 1 5123 5124 enum iwm_scan_config_flags { 5125 IWM_SCAN_CONFIG_FLAG_ACTIVATE = (1 << 0), 5126 IWM_SCAN_CONFIG_FLAG_DEACTIVATE = (1 << 1), 5127 IWM_SCAN_CONFIG_FLAG_FORBID_CHUB_REQS = (1 << 2), 5128 IWM_SCAN_CONFIG_FLAG_ALLOW_CHUB_REQS = (1 << 3), 5129 IWM_SCAN_CONFIG_FLAG_SET_TX_CHAINS = (1 << 8), 5130 IWM_SCAN_CONFIG_FLAG_SET_RX_CHAINS = (1 << 9), 5131 IWM_SCAN_CONFIG_FLAG_SET_AUX_STA_ID = (1 << 10), 5132 IWM_SCAN_CONFIG_FLAG_SET_ALL_TIMES = (1 << 11), 5133 IWM_SCAN_CONFIG_FLAG_SET_EFFECTIVE_TIMES = (1 << 12), 5134 IWM_SCAN_CONFIG_FLAG_SET_CHANNEL_FLAGS = (1 << 13), 5135 IWM_SCAN_CONFIG_FLAG_SET_LEGACY_RATES = (1 << 14), 5136 IWM_SCAN_CONFIG_FLAG_SET_MAC_ADDR = (1 << 15), 5137 IWM_SCAN_CONFIG_FLAG_SET_FRAGMENTED = (1 << 16), 5138 IWM_SCAN_CONFIG_FLAG_CLEAR_FRAGMENTED = (1 << 17), 5139 IWM_SCAN_CONFIG_FLAG_SET_CAM_MODE = (1 << 18), 5140 IWM_SCAN_CONFIG_FLAG_CLEAR_CAM_MODE = (1 << 19), 5141 IWM_SCAN_CONFIG_FLAG_SET_PROMISC_MODE = (1 << 20), 5142 IWM_SCAN_CONFIG_FLAG_CLEAR_PROMISC_MODE = (1 << 21), 5143 5144 /* Bits 26-31 are for num of channels in channel_array */ 5145 #define IWM_SCAN_CONFIG_N_CHANNELS(n) ((n) << 26) 5146 }; 5147 5148 enum iwm_scan_config_rates { 5149 /* OFDM basic rates */ 5150 IWM_SCAN_CONFIG_RATE_6M = (1 << 0), 5151 IWM_SCAN_CONFIG_RATE_9M = (1 << 1), 5152 IWM_SCAN_CONFIG_RATE_12M = (1 << 2), 5153 IWM_SCAN_CONFIG_RATE_18M = (1 << 3), 5154 IWM_SCAN_CONFIG_RATE_24M = (1 << 4), 5155 IWM_SCAN_CONFIG_RATE_36M = (1 << 5), 5156 IWM_SCAN_CONFIG_RATE_48M = (1 << 6), 5157 IWM_SCAN_CONFIG_RATE_54M = (1 << 7), 5158 /* CCK basic rates */ 5159 IWM_SCAN_CONFIG_RATE_1M = (1 << 8), 5160 IWM_SCAN_CONFIG_RATE_2M = (1 << 9), 5161 IWM_SCAN_CONFIG_RATE_5M = (1 << 10), 5162 IWM_SCAN_CONFIG_RATE_11M = (1 << 11), 5163 5164 /* Bits 16-27 are for supported rates */ 5165 #define IWM_SCAN_CONFIG_SUPPORTED_RATE(rate) ((rate) << 16) 5166 }; 5167 5168 enum iwm_channel_flags { 5169 IWM_CHANNEL_FLAG_EBS = (1 << 0), 5170 IWM_CHANNEL_FLAG_ACCURATE_EBS = (1 << 1), 5171 IWM_CHANNEL_FLAG_EBS_ADD = (1 << 2), 5172 IWM_CHANNEL_FLAG_PRE_SCAN_PASSIVE2ACTIVE = (1 << 3), 5173 }; 5174 5175 /** 5176 * struct iwm_scan_config 5177 * @flags: enum scan_config_flags 5178 * @tx_chains: valid_tx antenna - ANT_* definitions 5179 * @rx_chains: valid_rx antenna - ANT_* definitions 5180 * @legacy_rates: default legacy rates - enum scan_config_rates 5181 * @out_of_channel_time: default max out of serving channel time 5182 * @suspend_time: default max suspend time 5183 * @dwell_active: default dwell time for active scan 5184 * @dwell_passive: default dwell time for passive scan 5185 * @dwell_fragmented: default dwell time for fragmented scan 5186 * @dwell_extended: default dwell time for channels 1, 6 and 11 5187 * @mac_addr: default mac address to be used in probes 5188 * @bcast_sta_id: the index of the station in the fw 5189 * @channel_flags: default channel flags - enum iwm_channel_flags 5190 * scan_config_channel_flag 5191 * @channel_array: default supported channels 5192 */ 5193 struct iwm_scan_config { 5194 uint32_t flags; 5195 uint32_t tx_chains; 5196 uint32_t rx_chains; 5197 uint32_t legacy_rates; 5198 uint32_t out_of_channel_time; 5199 uint32_t suspend_time; 5200 uint8_t dwell_active; 5201 uint8_t dwell_passive; 5202 uint8_t dwell_fragmented; 5203 uint8_t dwell_extended; 5204 uint8_t mac_addr[IEEE80211_ADDR_LEN]; 5205 uint8_t bcast_sta_id; 5206 uint8_t channel_flags; 5207 uint8_t channel_array[]; 5208 } __packed; /* SCAN_CONFIG_DB_CMD_API_S */ 5209 5210 /** 5211 * iwm_umac_scan_flags 5212 *@IWM_UMAC_SCAN_FLAG_PREEMPTIVE: scan process triggered by this scan request 5213 * can be preempted by other scan requests with higher priority. 5214 * The low priority scan will be resumed when the higher proirity scan is 5215 * completed. 5216 *@IWM_UMAC_SCAN_FLAG_START_NOTIF: notification will be sent to the driver 5217 * when scan starts. 5218 */ 5219 enum iwm_umac_scan_flags { 5220 IWM_UMAC_SCAN_FLAG_PREEMPTIVE = (1 << 0), 5221 IWM_UMAC_SCAN_FLAG_START_NOTIF = (1 << 1), 5222 }; 5223 5224 enum iwm_umac_scan_uid_offsets { 5225 IWM_UMAC_SCAN_UID_TYPE_OFFSET = 0, 5226 IWM_UMAC_SCAN_UID_SEQ_OFFSET = 8, 5227 }; 5228 5229 enum iwm_umac_scan_general_flags { 5230 IWM_UMAC_SCAN_GEN_FLAGS_PERIODIC = (1 << 0), 5231 IWM_UMAC_SCAN_GEN_FLAGS_OVER_BT = (1 << 1), 5232 IWM_UMAC_SCAN_GEN_FLAGS_PASS_ALL = (1 << 2), 5233 IWM_UMAC_SCAN_GEN_FLAGS_PASSIVE = (1 << 3), 5234 IWM_UMAC_SCAN_GEN_FLAGS_PRE_CONNECT = (1 << 4), 5235 IWM_UMAC_SCAN_GEN_FLAGS_ITER_COMPLETE = (1 << 5), 5236 IWM_UMAC_SCAN_GEN_FLAGS_MULTIPLE_SSID = (1 << 6), 5237 IWM_UMAC_SCAN_GEN_FLAGS_FRAGMENTED = (1 << 7), 5238 IWM_UMAC_SCAN_GEN_FLAGS_RRM_ENABLED = (1 << 8), 5239 IWM_UMAC_SCAN_GEN_FLAGS_MATCH = (1 << 9), 5240 IWM_UMAC_SCAN_GEN_FLAGS_EXTENDED_DWELL = (1 << 10), 5241 }; 5242 5243 /** 5244 * struct iwm_scan_channel_cfg_umac 5245 * @flags: bitmap - 0-19: directed scan to i'th ssid. 5246 * @channel_num: channel number 1-13 etc. 5247 * @iter_count: repetition count for the channel. 5248 * @iter_interval: interval between two scan iterations on one channel. 5249 */ 5250 struct iwm_scan_channel_cfg_umac { 5251 uint32_t flags; 5252 #define IWM_SCAN_CHANNEL_UMAC_NSSIDS(x) ((1 << (x)) - 1) 5253 5254 uint8_t channel_num; 5255 uint8_t iter_count; 5256 uint16_t iter_interval; 5257 } __packed; /* SCAN_CHANNEL_CFG_S_VER2 */ 5258 5259 /** 5260 * struct iwm_scan_umac_schedule 5261 * @interval: interval in seconds between scan iterations 5262 * @iter_count: num of scan iterations for schedule plan, 0xff for infinite loop 5263 * @reserved: for alignment and future use 5264 */ 5265 struct iwm_scan_umac_schedule { 5266 uint16_t interval; 5267 uint8_t iter_count; 5268 uint8_t reserved; 5269 } __packed; /* SCAN_SCHED_PARAM_API_S_VER_1 */ 5270 5271 /** 5272 * struct iwm_scan_req_umac_tail - the rest of the UMAC scan request command 5273 * parameters following channels configuration array. 5274 * @schedule: two scheduling plans. 5275 * @delay: delay in TUs before starting the first scan iteration 5276 * @reserved: for future use and alignment 5277 * @preq: probe request with IEs blocks 5278 * @direct_scan: list of SSIDs for directed active scan 5279 */ 5280 struct iwm_scan_req_umac_tail { 5281 /* SCAN_PERIODIC_PARAMS_API_S_VER_1 */ 5282 struct iwm_scan_umac_schedule schedule[IWM_MAX_SCHED_SCAN_PLANS]; 5283 uint16_t delay; 5284 uint16_t reserved; 5285 /* SCAN_PROBE_PARAMS_API_S_VER_1 */ 5286 struct iwm_scan_probe_req preq; 5287 struct iwm_ssid_ie direct_scan[IWM_PROBE_OPTION_MAX]; 5288 } __packed; 5289 5290 /** 5291 * struct iwm_scan_req_umac 5292 * @flags: &enum iwm_umac_scan_flags 5293 * @uid: scan id, &enum iwm_umac_scan_uid_offsets 5294 * @ooc_priority: out of channel priority - &enum iwm_scan_priority 5295 * @general_flags: &enum iwm_umac_scan_general_flags 5296 * @extended_dwell: dwell time for channels 1, 6 and 11 5297 * @active_dwell: dwell time for active scan 5298 * @passive_dwell: dwell time for passive scan 5299 * @fragmented_dwell: dwell time for fragmented passive scan 5300 * @max_out_time: max out of serving channel time 5301 * @suspend_time: max suspend time 5302 * @scan_priority: scan internal prioritization &enum iwm_scan_priority 5303 * @channel_flags: &enum iwm_scan_channel_flags 5304 * @n_channels: num of channels in scan request 5305 * @reserved: for future use and alignment 5306 * @data: &struct iwm_scan_channel_cfg_umac and 5307 * &struct iwm_scan_req_umac_tail 5308 */ 5309 struct iwm_scan_req_umac { 5310 uint32_t flags; 5311 uint32_t uid; 5312 uint32_t ooc_priority; 5313 /* SCAN_GENERAL_PARAMS_API_S_VER_1 */ 5314 uint32_t general_flags; 5315 uint8_t extended_dwell; 5316 uint8_t active_dwell; 5317 uint8_t passive_dwell; 5318 uint8_t fragmented_dwell; 5319 uint32_t max_out_time; 5320 uint32_t suspend_time; 5321 uint32_t scan_priority; 5322 /* SCAN_CHANNEL_PARAMS_API_S_VER_1 */ 5323 uint8_t channel_flags; 5324 uint8_t n_channels; 5325 uint16_t reserved; 5326 uint8_t data[]; 5327 } __packed; /* SCAN_REQUEST_CMD_UMAC_API_S_VER_1 */ 5328 5329 /** 5330 * struct iwm_umac_scan_abort 5331 * @uid: scan id, &enum iwm_umac_scan_uid_offsets 5332 * @flags: reserved 5333 */ 5334 struct iwm_umac_scan_abort { 5335 uint32_t uid; 5336 uint32_t flags; 5337 } __packed; /* SCAN_ABORT_CMD_UMAC_API_S_VER_1 */ 5338 5339 /** 5340 * struct iwm_umac_scan_complete 5341 * @uid: scan id, &enum iwm_umac_scan_uid_offsets 5342 * @last_schedule: last scheduling line 5343 * @last_iter: last scan iteration number 5344 * @scan status: &enum iwm_scan_offload_complete_status 5345 * @ebs_status: &enum iwm_scan_ebs_status 5346 * @time_from_last_iter: time elapsed from last iteration 5347 * @reserved: for future use 5348 */ 5349 struct iwm_umac_scan_complete { 5350 uint32_t uid; 5351 uint8_t last_schedule; 5352 uint8_t last_iter; 5353 uint8_t status; 5354 uint8_t ebs_status; 5355 uint32_t time_from_last_iter; 5356 uint32_t reserved; 5357 } __packed; /* SCAN_COMPLETE_NTF_UMAC_API_S_VER_1 */ 5358 5359 #define IWM_SCAN_OFFLOAD_MATCHING_CHANNELS_LEN 5 5360 /** 5361 * struct iwm_scan_offload_profile_match - match information 5362 * @bssid: matched bssid 5363 * @channel: channel where the match occurred 5364 * @energy: 5365 * @matching_feature: 5366 * @matching_channels: bitmap of channels that matched, referencing 5367 * the channels passed in tue scan offload request 5368 */ 5369 struct iwm_scan_offload_profile_match { 5370 uint8_t bssid[IEEE80211_ADDR_LEN]; 5371 uint16_t reserved; 5372 uint8_t channel; 5373 uint8_t energy; 5374 uint8_t matching_feature; 5375 uint8_t matching_channels[IWM_SCAN_OFFLOAD_MATCHING_CHANNELS_LEN]; 5376 } __packed; /* SCAN_OFFLOAD_PROFILE_MATCH_RESULTS_S_VER_1 */ 5377 5378 /** 5379 * struct iwm_scan_offload_profiles_query - match results query response 5380 * @matched_profiles: bitmap of matched profiles, referencing the 5381 * matches passed in the scan offload request 5382 * @last_scan_age: age of the last offloaded scan 5383 * @n_scans_done: number of offloaded scans done 5384 * @gp2_d0u: GP2 when D0U occurred 5385 * @gp2_invoked: GP2 when scan offload was invoked 5386 * @resume_while_scanning: not used 5387 * @self_recovery: obsolete 5388 * @reserved: reserved 5389 * @matches: array of match information, one for each match 5390 */ 5391 struct iwm_scan_offload_profiles_query { 5392 uint32_t matched_profiles; 5393 uint32_t last_scan_age; 5394 uint32_t n_scans_done; 5395 uint32_t gp2_d0u; 5396 uint32_t gp2_invoked; 5397 uint8_t resume_while_scanning; 5398 uint8_t self_recovery; 5399 uint16_t reserved; 5400 struct iwm_scan_offload_profile_match matches[IWM_SCAN_MAX_PROFILES]; 5401 } __packed; /* SCAN_OFFLOAD_PROFILES_QUERY_RSP_S_VER_2 */ 5402 5403 /** 5404 * struct iwm_umac_scan_iter_complete_notif - notifies end of scanning iteration 5405 * @uid: scan id, &enum iwm_umac_scan_uid_offsets 5406 * @scanned_channels: number of channels scanned and number of valid elements in 5407 * results array 5408 * @status: one of SCAN_COMP_STATUS_* 5409 * @bt_status: BT on/off status 5410 * @last_channel: last channel that was scanned 5411 * @tsf_low: TSF timer (lower half) in usecs 5412 * @tsf_high: TSF timer (higher half) in usecs 5413 * @results: array of scan results, only "scanned_channels" of them are valid 5414 */ 5415 struct iwm_umac_scan_iter_complete_notif { 5416 uint32_t uid; 5417 uint8_t scanned_channels; 5418 uint8_t status; 5419 uint8_t bt_status; 5420 uint8_t last_channel; 5421 uint32_t tsf_low; 5422 uint32_t tsf_high; 5423 struct iwm_scan_results_notif results[]; 5424 } __packed; /* SCAN_ITER_COMPLETE_NTF_UMAC_API_S_VER_1 */ 5425 5426 /* Please keep this enum *SORTED* by hex value. 5427 * Needed for binary search, otherwise a warning will be triggered. 5428 */ 5429 enum iwm_scan_subcmd_ids { 5430 IWM_GSCAN_START_CMD = 0x0, 5431 IWM_GSCAN_STOP_CMD = 0x1, 5432 IWM_GSCAN_SET_HOTLIST_CMD = 0x2, 5433 IWM_GSCAN_RESET_HOTLIST_CMD = 0x3, 5434 IWM_GSCAN_SET_SIGNIFICANT_CHANGE_CMD = 0x4, 5435 IWM_GSCAN_RESET_SIGNIFICANT_CHANGE_CMD = 0x5, 5436 IWM_GSCAN_SIGNIFICANT_CHANGE_EVENT = 0xFD, 5437 IWM_GSCAN_HOTLIST_CHANGE_EVENT = 0xFE, 5438 IWM_GSCAN_RESULTS_AVAILABLE_EVENT = 0xFF, 5439 }; 5440 5441 /* STA API */ 5442 5443 /** 5444 * enum iwm_sta_flags - flags for the ADD_STA host command 5445 * @IWM_STA_FLG_REDUCED_TX_PWR_CTRL: 5446 * @IWM_STA_FLG_REDUCED_TX_PWR_DATA: 5447 * @IWM_STA_FLG_DISABLE_TX: set if TX should be disabled 5448 * @IWM_STA_FLG_PS: set if STA is in Power Save 5449 * @IWM_STA_FLG_INVALID: set if STA is invalid 5450 * @IWM_STA_FLG_DLP_EN: Direct Link Protocol is enabled 5451 * @IWM_STA_FLG_SET_ALL_KEYS: the current key applies to all key IDs 5452 * @IWM_STA_FLG_DRAIN_FLOW: drain flow 5453 * @IWM_STA_FLG_PAN: STA is for PAN interface 5454 * @IWM_STA_FLG_CLASS_AUTH: 5455 * @IWM_STA_FLG_CLASS_ASSOC: 5456 * @IWM_STA_FLG_CLASS_MIMO_PROT: 5457 * @IWM_STA_FLG_MAX_AGG_SIZE_MSK: maximal size for A-MPDU 5458 * @IWM_STA_FLG_AGG_MPDU_DENS_MSK: maximal MPDU density for Tx aggregation 5459 * @IWM_STA_FLG_FAT_EN_MSK: support for channel width (for Tx). This flag is 5460 * initialised by driver and can be updated by fw upon reception of 5461 * action frames that can change the channel width. When cleared the fw 5462 * will send all the frames in 20MHz even when FAT channel is requested. 5463 * @IWM_STA_FLG_MIMO_EN_MSK: support for MIMO. This flag is initialised by the 5464 * driver and can be updated by fw upon reception of action frames. 5465 * @IWM_STA_FLG_MFP_EN: Management Frame Protection 5466 */ 5467 enum iwm_sta_flags { 5468 IWM_STA_FLG_REDUCED_TX_PWR_CTRL = (1 << 3), 5469 IWM_STA_FLG_REDUCED_TX_PWR_DATA = (1 << 6), 5470 5471 IWM_STA_FLG_DISABLE_TX = (1 << 4), 5472 5473 IWM_STA_FLG_PS = (1 << 8), 5474 IWM_STA_FLG_DRAIN_FLOW = (1 << 12), 5475 IWM_STA_FLG_PAN = (1 << 13), 5476 IWM_STA_FLG_CLASS_AUTH = (1 << 14), 5477 IWM_STA_FLG_CLASS_ASSOC = (1 << 15), 5478 IWM_STA_FLG_RTS_MIMO_PROT = (1 << 17), 5479 5480 IWM_STA_FLG_MAX_AGG_SIZE_SHIFT = 19, 5481 IWM_STA_FLG_MAX_AGG_SIZE_8K = (0 << IWM_STA_FLG_MAX_AGG_SIZE_SHIFT), 5482 IWM_STA_FLG_MAX_AGG_SIZE_16K = (1 << IWM_STA_FLG_MAX_AGG_SIZE_SHIFT), 5483 IWM_STA_FLG_MAX_AGG_SIZE_32K = (2 << IWM_STA_FLG_MAX_AGG_SIZE_SHIFT), 5484 IWM_STA_FLG_MAX_AGG_SIZE_64K = (3 << IWM_STA_FLG_MAX_AGG_SIZE_SHIFT), 5485 IWM_STA_FLG_MAX_AGG_SIZE_128K = (4 << IWM_STA_FLG_MAX_AGG_SIZE_SHIFT), 5486 IWM_STA_FLG_MAX_AGG_SIZE_256K = (5 << IWM_STA_FLG_MAX_AGG_SIZE_SHIFT), 5487 IWM_STA_FLG_MAX_AGG_SIZE_512K = (6 << IWM_STA_FLG_MAX_AGG_SIZE_SHIFT), 5488 IWM_STA_FLG_MAX_AGG_SIZE_1024K = (7 << IWM_STA_FLG_MAX_AGG_SIZE_SHIFT), 5489 IWM_STA_FLG_MAX_AGG_SIZE_MSK = (7 << IWM_STA_FLG_MAX_AGG_SIZE_SHIFT), 5490 5491 IWM_STA_FLG_AGG_MPDU_DENS_SHIFT = 23, 5492 IWM_STA_FLG_AGG_MPDU_DENS_2US = (4 << IWM_STA_FLG_AGG_MPDU_DENS_SHIFT), 5493 IWM_STA_FLG_AGG_MPDU_DENS_4US = (5 << IWM_STA_FLG_AGG_MPDU_DENS_SHIFT), 5494 IWM_STA_FLG_AGG_MPDU_DENS_8US = (6 << IWM_STA_FLG_AGG_MPDU_DENS_SHIFT), 5495 IWM_STA_FLG_AGG_MPDU_DENS_16US = (7 << IWM_STA_FLG_AGG_MPDU_DENS_SHIFT), 5496 IWM_STA_FLG_AGG_MPDU_DENS_MSK = (7 << IWM_STA_FLG_AGG_MPDU_DENS_SHIFT), 5497 5498 IWM_STA_FLG_FAT_EN_20MHZ = (0 << 26), 5499 IWM_STA_FLG_FAT_EN_40MHZ = (1 << 26), 5500 IWM_STA_FLG_FAT_EN_80MHZ = (2 << 26), 5501 IWM_STA_FLG_FAT_EN_160MHZ = (3 << 26), 5502 IWM_STA_FLG_FAT_EN_MSK = (3 << 26), 5503 5504 IWM_STA_FLG_MIMO_EN_SISO = (0 << 28), 5505 IWM_STA_FLG_MIMO_EN_MIMO2 = (1 << 28), 5506 IWM_STA_FLG_MIMO_EN_MIMO3 = (2 << 28), 5507 IWM_STA_FLG_MIMO_EN_MSK = (3 << 28), 5508 }; 5509 5510 /** 5511 * enum iwm_sta_key_flag - key flags for the ADD_STA host command 5512 * @IWM_STA_KEY_FLG_NO_ENC: no encryption 5513 * @IWM_STA_KEY_FLG_WEP: WEP encryption algorithm 5514 * @IWM_STA_KEY_FLG_CCM: CCMP encryption algorithm 5515 * @IWM_STA_KEY_FLG_TKIP: TKIP encryption algorithm 5516 * @IWM_STA_KEY_FLG_EXT: extended cipher algorithm (depends on the FW support) 5517 * @IWM_STA_KEY_FLG_CMAC: CMAC encryption algorithm 5518 * @IWM_STA_KEY_FLG_ENC_UNKNOWN: unknown encryption algorithm 5519 * @IWM_STA_KEY_FLG_EN_MSK: mask for encryption algorithmi value 5520 * @IWM_STA_KEY_FLG_WEP_KEY_MAP: wep is either a group key (0 - legacy WEP) or from 5521 * station info array (1 - n 1X mode) 5522 * @IWM_STA_KEY_FLG_KEYID_MSK: the index of the key 5523 * @IWM_STA_KEY_NOT_VALID: key is invalid 5524 * @IWM_STA_KEY_FLG_WEP_13BYTES: set for 13 bytes WEP key 5525 * @IWM_STA_KEY_MULTICAST: set for multical key 5526 * @IWM_STA_KEY_MFP: key is used for Management Frame Protection 5527 */ 5528 enum iwm_sta_key_flag { 5529 IWM_STA_KEY_FLG_NO_ENC = (0 << 0), 5530 IWM_STA_KEY_FLG_WEP = (1 << 0), 5531 IWM_STA_KEY_FLG_CCM = (2 << 0), 5532 IWM_STA_KEY_FLG_TKIP = (3 << 0), 5533 IWM_STA_KEY_FLG_EXT = (4 << 0), 5534 IWM_STA_KEY_FLG_CMAC = (6 << 0), 5535 IWM_STA_KEY_FLG_ENC_UNKNOWN = (7 << 0), 5536 IWM_STA_KEY_FLG_EN_MSK = (7 << 0), 5537 5538 IWM_STA_KEY_FLG_WEP_KEY_MAP = (1 << 3), 5539 IWM_STA_KEY_FLG_KEYID_POS = 8, 5540 IWM_STA_KEY_FLG_KEYID_MSK = (3 << IWM_STA_KEY_FLG_KEYID_POS), 5541 IWM_STA_KEY_NOT_VALID = (1 << 11), 5542 IWM_STA_KEY_FLG_WEP_13BYTES = (1 << 12), 5543 IWM_STA_KEY_MULTICAST = (1 << 14), 5544 IWM_STA_KEY_MFP = (1 << 15), 5545 }; 5546 5547 /** 5548 * enum iwm_sta_modify_flag - indicate to the fw what flag are being changed 5549 * @IWM_STA_MODIFY_QUEUE_REMOVAL: this command removes a queue 5550 * @IWM_STA_MODIFY_TID_DISABLE_TX: this command modifies %tid_disable_tx 5551 * @IWM_STA_MODIFY_TX_RATE: unused 5552 * @IWM_STA_MODIFY_ADD_BA_TID: this command modifies %add_immediate_ba_tid 5553 * @IWM_STA_MODIFY_REMOVE_BA_TID: this command modifies %remove_immediate_ba_tid 5554 * @IWM_STA_MODIFY_SLEEPING_STA_TX_COUNT: this command modifies %sleep_tx_count 5555 * @IWM_STA_MODIFY_PROT_TH: 5556 * @IWM_STA_MODIFY_QUEUES: modify the queues used by this station 5557 */ 5558 enum iwm_sta_modify_flag { 5559 IWM_STA_MODIFY_QUEUE_REMOVAL = (1 << 0), 5560 IWM_STA_MODIFY_TID_DISABLE_TX = (1 << 1), 5561 IWM_STA_MODIFY_TX_RATE = (1 << 2), 5562 IWM_STA_MODIFY_ADD_BA_TID = (1 << 3), 5563 IWM_STA_MODIFY_REMOVE_BA_TID = (1 << 4), 5564 IWM_STA_MODIFY_SLEEPING_STA_TX_COUNT = (1 << 5), 5565 IWM_STA_MODIFY_PROT_TH = (1 << 6), 5566 IWM_STA_MODIFY_QUEUES = (1 << 7), 5567 }; 5568 5569 #define IWM_STA_MODE_MODIFY 1 5570 5571 /** 5572 * enum iwm_sta_sleep_flag - type of sleep of the station 5573 * @IWM_STA_SLEEP_STATE_AWAKE: 5574 * @IWM_STA_SLEEP_STATE_PS_POLL: 5575 * @IWM_STA_SLEEP_STATE_UAPSD: 5576 * @IWM_STA_SLEEP_STATE_MOREDATA: set more-data bit on 5577 * (last) released frame 5578 */ 5579 enum iwm_sta_sleep_flag { 5580 IWM_STA_SLEEP_STATE_AWAKE = 0, 5581 IWM_STA_SLEEP_STATE_PS_POLL = (1 << 0), 5582 IWM_STA_SLEEP_STATE_UAPSD = (1 << 1), 5583 IWM_STA_SLEEP_STATE_MOREDATA = (1 << 2), 5584 }; 5585 5586 /* STA ID and color bits definitions */ 5587 #define IWM_STA_ID_SEED (0x0f) 5588 #define IWM_STA_ID_POS (0) 5589 #define IWM_STA_ID_MSK (IWM_STA_ID_SEED << IWM_STA_ID_POS) 5590 5591 #define IWM_STA_COLOR_SEED (0x7) 5592 #define IWM_STA_COLOR_POS (4) 5593 #define IWM_STA_COLOR_MSK (IWM_STA_COLOR_SEED << IWM_STA_COLOR_POS) 5594 5595 #define IWM_STA_ID_N_COLOR_GET_COLOR(id_n_color) \ 5596 (((id_n_color) & IWM_STA_COLOR_MSK) >> IWM_STA_COLOR_POS) 5597 #define IWM_STA_ID_N_COLOR_GET_ID(id_n_color) \ 5598 (((id_n_color) & IWM_STA_ID_MSK) >> IWM_STA_ID_POS) 5599 5600 #define IWM_STA_KEY_MAX_NUM (16) 5601 #define IWM_STA_KEY_IDX_INVALID (0xff) 5602 #define IWM_STA_KEY_MAX_DATA_KEY_NUM (4) 5603 #define IWM_MAX_GLOBAL_KEYS (4) 5604 #define IWM_STA_KEY_LEN_WEP40 (5) 5605 #define IWM_STA_KEY_LEN_WEP104 (13) 5606 5607 /** 5608 * struct iwm_mvm_keyinfo - key information 5609 * @key_flags: type %iwm_sta_key_flag 5610 * @tkip_rx_tsc_byte2: TSC[2] for key mix ph1 detection 5611 * @tkip_rx_ttak: 10-byte unicast TKIP TTAK for Rx 5612 * @key_offset: key offset in the fw's key table 5613 * @key: 16-byte unicast decryption key 5614 * @tx_secur_seq_cnt: initial RSC / PN needed for replay check 5615 * @hw_tkip_mic_rx_key: byte: MIC Rx Key - used for TKIP only 5616 * @hw_tkip_mic_tx_key: byte: MIC Tx Key - used for TKIP only 5617 */ 5618 struct iwm_mvm_keyinfo { 5619 uint16_t key_flags; 5620 uint8_t tkip_rx_tsc_byte2; 5621 uint8_t reserved1; 5622 uint16_t tkip_rx_ttak[5]; 5623 uint8_t key_offset; 5624 uint8_t reserved2; 5625 uint8_t key[16]; 5626 uint64_t tx_secur_seq_cnt; 5627 uint64_t hw_tkip_mic_rx_key; 5628 uint64_t hw_tkip_mic_tx_key; 5629 } __packed; 5630 5631 #define IWM_ADD_STA_STATUS_MASK 0xFF 5632 #define IWM_ADD_STA_BAID_VALID_MASK 0x8000 5633 #define IWM_ADD_STA_BAID_MASK 0x7F00 5634 #define IWM_ADD_STA_BAID_SHIFT 8 5635 5636 /** 5637 * struct iwm_mvm_add_sta_cmd - Add/modify a station in the fw's sta table. 5638 * ( REPLY_ADD_STA = 0x18 ) 5639 * @add_modify: 1: modify existing, 0: add new station 5640 * @awake_acs: 5641 * @tid_disable_tx: is tid BIT(tid) enabled for Tx. Clear BIT(x) to enable 5642 * AMPDU for tid x. Set %IWM_STA_MODIFY_TID_DISABLE_TX to change this field. 5643 * @mac_id_n_color: the Mac context this station belongs to 5644 * @addr[IEEE80211_ADDR_LEN]: station's MAC address 5645 * @sta_id: index of station in uCode's station table 5646 * @modify_mask: IWM_STA_MODIFY_*, selects which parameters to modify vs. leave 5647 * alone. 1 - modify, 0 - don't change. 5648 * @station_flags: look at %iwm_sta_flags 5649 * @station_flags_msk: what of %station_flags have changed 5650 * @add_immediate_ba_tid: tid for which to add block-ack support (Rx) 5651 * Set %IWM_STA_MODIFY_ADD_BA_TID to use this field, and also set 5652 * add_immediate_ba_ssn. 5653 * @remove_immediate_ba_tid: tid for which to remove block-ack support (Rx) 5654 * Set %IWM_STA_MODIFY_REMOVE_BA_TID to use this field 5655 * @add_immediate_ba_ssn: ssn for the Rx block-ack session. Used together with 5656 * add_immediate_ba_tid. 5657 * @sleep_tx_count: number of packets to transmit to station even though it is 5658 * asleep. Used to synchronise PS-poll and u-APSD responses while ucode 5659 * keeps track of STA sleep state. 5660 * @sleep_state_flags: Look at %iwm_sta_sleep_flag. 5661 * @assoc_id: assoc_id to be sent in VHT PLCP (9-bit), for grp use 0, for AP 5662 * mac-addr. 5663 * @beamform_flags: beam forming controls 5664 * @tfd_queue_msk: tfd queues used by this station 5665 * 5666 * The device contains an internal table of per-station information, with info 5667 * on security keys, aggregation parameters, and Tx rates for initial Tx 5668 * attempt and any retries (set by IWM_REPLY_TX_LINK_QUALITY_CMD). 5669 * 5670 * ADD_STA sets up the table entry for one station, either creating a new 5671 * entry, or modifying a pre-existing one. 5672 */ 5673 struct iwm_mvm_add_sta_cmd { 5674 uint8_t add_modify; 5675 uint8_t awake_acs; 5676 uint16_t tid_disable_tx; 5677 uint32_t mac_id_n_color; 5678 uint8_t addr[IEEE80211_ADDR_LEN]; /* _STA_ID_MODIFY_INFO_API_S_VER_1 */ 5679 uint16_t reserved2; 5680 uint8_t sta_id; 5681 uint8_t modify_mask; 5682 uint16_t reserved3; 5683 uint32_t station_flags; 5684 uint32_t station_flags_msk; 5685 uint8_t add_immediate_ba_tid; 5686 uint8_t remove_immediate_ba_tid; 5687 uint16_t add_immediate_ba_ssn; 5688 uint16_t sleep_tx_count; 5689 uint16_t sleep_state_flags; 5690 uint16_t assoc_id; 5691 uint16_t beamform_flags; 5692 uint32_t tfd_queue_msk; 5693 } __packed; /* ADD_STA_CMD_API_S_VER_7 */ 5694 5695 /** 5696 * struct iwm_mvm_add_sta_key_cmd - add/modify sta key 5697 * ( IWM_REPLY_ADD_STA_KEY = 0x17 ) 5698 * @sta_id: index of station in uCode's station table 5699 * @key_offset: key offset in key storage 5700 * @key_flags: type %iwm_sta_key_flag 5701 * @key: key material data 5702 * @key2: key material data 5703 * @rx_secur_seq_cnt: RX security sequence counter for the key 5704 * @tkip_rx_tsc_byte2: TSC[2] for key mix ph1 detection 5705 * @tkip_rx_ttak: 10-byte unicast TKIP TTAK for Rx 5706 */ 5707 struct iwm_mvm_add_sta_key_cmd { 5708 uint8_t sta_id; 5709 uint8_t key_offset; 5710 uint16_t key_flags; 5711 uint8_t key[16]; 5712 uint8_t key2[16]; 5713 uint8_t rx_secur_seq_cnt[16]; 5714 uint8_t tkip_rx_tsc_byte2; 5715 uint8_t reserved; 5716 uint16_t tkip_rx_ttak[5]; 5717 } __packed; /* IWM_ADD_MODIFY_STA_KEY_API_S_VER_1 */ 5718 5719 /** 5720 * enum iwm_mvm_add_sta_rsp_status - status in the response to ADD_STA command 5721 * @IWM_ADD_STA_SUCCESS: operation was executed successfully 5722 * @IWM_ADD_STA_STATIONS_OVERLOAD: no room left in the fw's station table 5723 * @IWM_ADD_STA_IMMEDIATE_BA_FAILURE: can't add Rx block ack session 5724 * @IWM_ADD_STA_MODIFY_NON_EXISTING_STA: driver requested to modify a station 5725 * that doesn't exist. 5726 */ 5727 enum iwm_mvm_add_sta_rsp_status { 5728 IWM_ADD_STA_SUCCESS = 0x1, 5729 IWM_ADD_STA_STATIONS_OVERLOAD = 0x2, 5730 IWM_ADD_STA_IMMEDIATE_BA_FAILURE = 0x4, 5731 IWM_ADD_STA_MODIFY_NON_EXISTING_STA = 0x8, 5732 }; 5733 5734 /** 5735 * struct iwm_mvm_rm_sta_cmd - Add / modify a station in the fw's station table 5736 * ( IWM_REMOVE_STA = 0x19 ) 5737 * @sta_id: the station id of the station to be removed 5738 */ 5739 struct iwm_mvm_rm_sta_cmd { 5740 uint8_t sta_id; 5741 uint8_t reserved[3]; 5742 } __packed; /* IWM_REMOVE_STA_CMD_API_S_VER_2 */ 5743 5744 /** 5745 * struct iwm_mvm_mgmt_mcast_key_cmd 5746 * ( IWM_MGMT_MCAST_KEY = 0x1f ) 5747 * @ctrl_flags: %iwm_sta_key_flag 5748 * @IGTK: 5749 * @K1: IGTK master key 5750 * @K2: IGTK sub key 5751 * @sta_id: station ID that support IGTK 5752 * @key_id: 5753 * @receive_seq_cnt: initial RSC/PN needed for replay check 5754 */ 5755 struct iwm_mvm_mgmt_mcast_key_cmd { 5756 uint32_t ctrl_flags; 5757 uint8_t IGTK[16]; 5758 uint8_t K1[16]; 5759 uint8_t K2[16]; 5760 uint32_t key_id; 5761 uint32_t sta_id; 5762 uint64_t receive_seq_cnt; 5763 } __packed; /* SEC_MGMT_MULTICAST_KEY_CMD_API_S_VER_1 */ 5764 5765 struct iwm_mvm_wep_key { 5766 uint8_t key_index; 5767 uint8_t key_offset; 5768 uint16_t reserved1; 5769 uint8_t key_size; 5770 uint8_t reserved2[3]; 5771 uint8_t key[16]; 5772 } __packed; 5773 5774 struct iwm_mvm_wep_key_cmd { 5775 uint32_t mac_id_n_color; 5776 uint8_t num_keys; 5777 uint8_t decryption_type; 5778 uint8_t flags; 5779 uint8_t reserved; 5780 struct iwm_mvm_wep_key wep_key[0]; 5781 } __packed; /* SEC_CURR_WEP_KEY_CMD_API_S_VER_2 */ 5782 5783 /* 5784 * END mvm/fw-api-sta.h 5785 */ 5786 5787 /* 5788 * BT coex 5789 */ 5790 5791 enum iwm_bt_coex_mode { 5792 IWM_BT_COEX_DISABLE = 0x0, 5793 IWM_BT_COEX_NW = 0x1, 5794 IWM_BT_COEX_BT = 0x2, 5795 IWM_BT_COEX_WIFI = 0x3, 5796 }; /* BT_COEX_MODES_E */ 5797 5798 enum iwm_bt_coex_enabled_modules { 5799 IWM_BT_COEX_MPLUT_ENABLED = (1 << 0), 5800 IWM_BT_COEX_MPLUT_BOOST_ENABLED = (1 << 1), 5801 IWM_BT_COEX_SYNC2SCO_ENABLED = (1 << 2), 5802 IWM_BT_COEX_CORUN_ENABLED = (1 << 3), 5803 IWM_BT_COEX_HIGH_BAND_RET = (1 << 4), 5804 }; /* BT_COEX_MODULES_ENABLE_E_VER_1 */ 5805 5806 /** 5807 * struct iwm_bt_coex_cmd - bt coex configuration command 5808 * @mode: enum %iwm_bt_coex_mode 5809 * @enabled_modules: enum %iwm_bt_coex_enabled_modules 5810 * 5811 * The structure is used for the BT_COEX command. 5812 */ 5813 struct iwm_bt_coex_cmd { 5814 uint32_t mode; 5815 uint32_t enabled_modules; 5816 } __packed; /* BT_COEX_CMD_API_S_VER_6 */ 5817 5818 5819 /* 5820 * Location Aware Regulatory (LAR) API - MCC updates 5821 */ 5822 5823 /** 5824 * struct iwm_mcc_update_cmd_v1 - Request the device to update geographic 5825 * regulatory profile according to the given MCC (Mobile Country Code). 5826 * The MCC is two letter-code, ascii upper case[A-Z] or '00' for world domain. 5827 * 'ZZ' MCC will be used to switch to NVM default profile; in this case, the 5828 * MCC in the cmd response will be the relevant MCC in the NVM. 5829 * @mcc: given mobile country code 5830 * @source_id: the source from where we got the MCC, see iwm_mcc_source 5831 * @reserved: reserved for alignment 5832 */ 5833 struct iwm_mcc_update_cmd_v1 { 5834 uint16_t mcc; 5835 uint8_t source_id; 5836 uint8_t reserved; 5837 } __packed; /* LAR_UPDATE_MCC_CMD_API_S_VER_1 */ 5838 5839 /** 5840 * struct iwm_mcc_update_cmd - Request the device to update geographic 5841 * regulatory profile according to the given MCC (Mobile Country Code). 5842 * The MCC is two letter-code, ascii upper case[A-Z] or '00' for world domain. 5843 * 'ZZ' MCC will be used to switch to NVM default profile; in this case, the 5844 * MCC in the cmd response will be the relevant MCC in the NVM. 5845 * @mcc: given mobile country code 5846 * @source_id: the source from where we got the MCC, see iwm_mcc_source 5847 * @reserved: reserved for alignment 5848 * @key: integrity key for MCC API OEM testing 5849 * @reserved2: reserved 5850 */ 5851 struct iwm_mcc_update_cmd { 5852 uint16_t mcc; 5853 uint8_t source_id; 5854 uint8_t reserved; 5855 uint32_t key; 5856 uint32_t reserved2[5]; 5857 } __packed; /* LAR_UPDATE_MCC_CMD_API_S_VER_2 */ 5858 5859 /** 5860 * iwm_mcc_update_resp_v1 - response to MCC_UPDATE_CMD. 5861 * Contains the new channel control profile map, if changed, and the new MCC 5862 * (mobile country code). 5863 * The new MCC may be different than what was requested in MCC_UPDATE_CMD. 5864 * @status: see &enum iwm_mcc_update_status 5865 * @mcc: the new applied MCC 5866 * @cap: capabilities for all channels which matches the MCC 5867 * @source_id: the MCC source, see iwm_mcc_source 5868 * @n_channels: number of channels in @channels_data (may be 14, 39, 50 or 51 5869 * channels, depending on platform) 5870 * @channels: channel control data map, DWORD for each channel. Only the first 5871 * 16bits are used. 5872 */ 5873 struct iwm_mcc_update_resp_v1 { 5874 uint32_t status; 5875 uint16_t mcc; 5876 uint8_t cap; 5877 uint8_t source_id; 5878 uint32_t n_channels; 5879 uint32_t channels[0]; 5880 } __packed; /* LAR_UPDATE_MCC_CMD_RESP_S_VER_1 */ 5881 5882 /** 5883 * iwm_mcc_update_resp - response to MCC_UPDATE_CMD. 5884 * Contains the new channel control profile map, if changed, and the new MCC 5885 * (mobile country code). 5886 * The new MCC may be different than what was requested in MCC_UPDATE_CMD. 5887 * @status: see &enum iwm_mcc_update_status 5888 * @mcc: the new applied MCC 5889 * @cap: capabilities for all channels which matches the MCC 5890 * @source_id: the MCC source, see iwm_mcc_source 5891 * @time: time elapsed from the MCC test start (in 30 seconds TU) 5892 * @reserved: reserved. 5893 * @n_channels: number of channels in @channels_data (may be 14, 39, 50 or 51 5894 * channels, depending on platform) 5895 * @channels: channel control data map, DWORD for each channel. Only the first 5896 * 16bits are used. 5897 */ 5898 struct iwm_mcc_update_resp { 5899 uint32_t status; 5900 uint16_t mcc; 5901 uint8_t cap; 5902 uint8_t source_id; 5903 uint16_t time; 5904 uint16_t reserved; 5905 uint32_t n_channels; 5906 uint32_t channels[0]; 5907 } __packed; /* LAR_UPDATE_MCC_CMD_RESP_S_VER_2 */ 5908 5909 /** 5910 * struct iwm_mcc_chub_notif - chub notifies of mcc change 5911 * (MCC_CHUB_UPDATE_CMD = 0xc9) 5912 * The Chub (Communication Hub, CommsHUB) is a HW component that connects to 5913 * the cellular and connectivity cores that gets updates of the mcc, and 5914 * notifies the ucode directly of any mcc change. 5915 * The ucode requests the driver to request the device to update geographic 5916 * regulatory profile according to the given MCC (Mobile Country Code). 5917 * The MCC is two letter-code, ascii upper case[A-Z] or '00' for world domain. 5918 * 'ZZ' MCC will be used to switch to NVM default profile; in this case, the 5919 * MCC in the cmd response will be the relevant MCC in the NVM. 5920 * @mcc: given mobile country code 5921 * @source_id: identity of the change originator, see iwm_mcc_source 5922 * @reserved1: reserved for alignment 5923 */ 5924 struct iwm_mcc_chub_notif { 5925 uint16_t mcc; 5926 uint8_t source_id; 5927 uint8_t reserved1; 5928 } __packed; /* LAR_MCC_NOTIFY_S */ 5929 5930 enum iwm_mcc_update_status { 5931 IWM_MCC_RESP_NEW_CHAN_PROFILE, 5932 IWM_MCC_RESP_SAME_CHAN_PROFILE, 5933 IWM_MCC_RESP_INVALID, 5934 IWM_MCC_RESP_NVM_DISABLED, 5935 IWM_MCC_RESP_ILLEGAL, 5936 IWM_MCC_RESP_LOW_PRIORITY, 5937 IWM_MCC_RESP_TEST_MODE_ACTIVE, 5938 IWM_MCC_RESP_TEST_MODE_NOT_ACTIVE, 5939 IWM_MCC_RESP_TEST_MODE_DENIAL_OF_SERVICE, 5940 }; 5941 5942 enum iwm_mcc_source { 5943 IWM_MCC_SOURCE_OLD_FW = 0, 5944 IWM_MCC_SOURCE_ME = 1, 5945 IWM_MCC_SOURCE_BIOS = 2, 5946 IWM_MCC_SOURCE_3G_LTE_HOST = 3, 5947 IWM_MCC_SOURCE_3G_LTE_DEVICE = 4, 5948 IWM_MCC_SOURCE_WIFI = 5, 5949 IWM_MCC_SOURCE_RESERVED = 6, 5950 IWM_MCC_SOURCE_DEFAULT = 7, 5951 IWM_MCC_SOURCE_UNINITIALIZED = 8, 5952 IWM_MCC_SOURCE_MCC_API = 9, 5953 IWM_MCC_SOURCE_GET_CURRENT = 0x10, 5954 IWM_MCC_SOURCE_GETTING_MCC_TEST_MODE = 0x11, 5955 }; 5956 5957 /** 5958 * struct iwm_dts_measurement_notif_v1 - measurements notification 5959 * 5960 * @temp: the measured temperature 5961 * @voltage: the measured voltage 5962 */ 5963 struct iwm_dts_measurement_notif_v1 { 5964 int32_t temp; 5965 int32_t voltage; 5966 } __packed; /* TEMPERATURE_MEASUREMENT_TRIGGER_NTFY_S_VER_1*/ 5967 5968 /** 5969 * struct iwm_dts_measurement_notif_v2 - measurements notification 5970 * 5971 * @temp: the measured temperature 5972 * @voltage: the measured voltage 5973 * @threshold_idx: the trip index that was crossed 5974 */ 5975 struct iwm_dts_measurement_notif_v2 { 5976 int32_t temp; 5977 int32_t voltage; 5978 int32_t threshold_idx; 5979 } __packed; /* TEMPERATURE_MEASUREMENT_TRIGGER_NTFY_S_VER_2 */ 5980 5981 /* 5982 * Some cherry-picked definitions 5983 */ 5984 5985 #define IWM_FRAME_LIMIT 64 5986 5987 /* 5988 * From Linux commit ab02165ccec4c78162501acedeef1a768acdb811: 5989 * As the firmware is slowly running out of command IDs and grouping of 5990 * commands is desirable anyway, the firmware is extending the command 5991 * header from 4 bytes to 8 bytes to introduce a group (in place of the 5992 * former flags field, since that's always 0 on commands and thus can 5993 * be easily used to distinguish between the two). 5994 * 5995 * These functions retrieve specific information from the id field in 5996 * the iwm_host_cmd struct which contains the command id, the group id, 5997 * and the version of the command. 5998 */ 5999 static inline uint8_t 6000 iwm_cmd_opcode(uint32_t cmdid) 6001 { 6002 return cmdid & 0xff; 6003 } 6004 6005 static inline uint8_t 6006 iwm_cmd_groupid(uint32_t cmdid) 6007 { 6008 return ((cmdid & 0Xff00) >> 8); 6009 } 6010 6011 static inline uint8_t 6012 iwm_cmd_version(uint32_t cmdid) 6013 { 6014 return ((cmdid & 0xff0000) >> 16); 6015 } 6016 6017 static inline uint32_t 6018 iwm_cmd_id(uint8_t opcode, uint8_t groupid, uint8_t version) 6019 { 6020 return opcode + (groupid << 8) + (version << 16); 6021 } 6022 6023 /* make uint16_t wide id out of uint8_t group and opcode */ 6024 #define IWM_WIDE_ID(grp, opcode) ((grp << 8) | opcode) 6025 6026 /* due to the conversion, this group is special */ 6027 #define IWM_ALWAYS_LONG_GROUP 1 6028 6029 struct iwm_cmd_header { 6030 uint8_t code; 6031 uint8_t flags; 6032 uint8_t idx; 6033 uint8_t qid; 6034 } __packed; 6035 6036 struct iwm_cmd_header_wide { 6037 uint8_t opcode; 6038 uint8_t group_id; 6039 uint8_t idx; 6040 uint8_t qid; 6041 uint16_t length; 6042 uint8_t reserved; 6043 uint8_t version; 6044 } __packed; 6045 6046 enum iwm_power_scheme { 6047 IWM_POWER_SCHEME_CAM = 1, 6048 IWM_POWER_SCHEME_BPS, 6049 IWM_POWER_SCHEME_LP 6050 }; 6051 6052 #define IWM_DEF_CMD_PAYLOAD_SIZE 320 6053 #define IWM_MAX_CMD_PAYLOAD_SIZE ((4096 - 4) - sizeof(struct iwm_cmd_header)) 6054 #define IWM_CMD_FAILED_MSK 0x40 6055 6056 /** 6057 * struct iwm_device_cmd 6058 * 6059 * For allocation of the command and tx queues, this establishes the overall 6060 * size of the largest command we send to uCode, except for commands that 6061 * aren't fully copied and use other TFD space. 6062 */ 6063 struct iwm_device_cmd { 6064 union { 6065 struct { 6066 struct iwm_cmd_header hdr; 6067 uint8_t data[IWM_DEF_CMD_PAYLOAD_SIZE]; 6068 }; 6069 struct { 6070 struct iwm_cmd_header_wide hdr_wide; 6071 uint8_t data_wide[IWM_DEF_CMD_PAYLOAD_SIZE - 6072 sizeof(struct iwm_cmd_header_wide) + 6073 sizeof(struct iwm_cmd_header)]; 6074 }; 6075 }; 6076 } __packed; 6077 6078 struct iwm_rx_packet { 6079 /* 6080 * The first 4 bytes of the RX frame header contain both the RX frame 6081 * size and some flags. 6082 * Bit fields: 6083 * 31: flag flush RB request 6084 * 30: flag ignore TC (terminal counter) request 6085 * 29: flag fast IRQ request 6086 * 28-14: Reserved 6087 * 13-00: RX frame size 6088 */ 6089 uint32_t len_n_flags; 6090 struct iwm_cmd_header hdr; 6091 uint8_t data[]; 6092 } __packed; 6093 6094 #define IWM_FH_RSCSR_FRAME_SIZE_MSK 0x00003fff 6095 6096 static inline uint32_t 6097 iwm_rx_packet_len(const struct iwm_rx_packet *pkt) 6098 { 6099 6100 return le32toh(pkt->len_n_flags) & IWM_FH_RSCSR_FRAME_SIZE_MSK; 6101 } 6102 6103 static inline uint32_t 6104 iwm_rx_packet_payload_len(const struct iwm_rx_packet *pkt) 6105 { 6106 6107 return iwm_rx_packet_len(pkt) - sizeof(pkt->hdr); 6108 } 6109 6110 6111 #define IWM_MIN_DBM -100 6112 #define IWM_MAX_DBM -33 /* realistic guess */ 6113 6114 #define IWM_READ(sc, reg) \ 6115 bus_space_read_4((sc)->sc_st, (sc)->sc_sh, (reg)) 6116 6117 #define IWM_WRITE(sc, reg, val) \ 6118 bus_space_write_4((sc)->sc_st, (sc)->sc_sh, (reg), (val)) 6119 6120 #define IWM_WRITE_1(sc, reg, val) \ 6121 bus_space_write_1((sc)->sc_st, (sc)->sc_sh, (reg), (val)) 6122 6123 #define IWM_SETBITS(sc, reg, mask) \ 6124 IWM_WRITE(sc, reg, IWM_READ(sc, reg) | (mask)) 6125 6126 #define IWM_CLRBITS(sc, reg, mask) \ 6127 IWM_WRITE(sc, reg, IWM_READ(sc, reg) & ~(mask)) 6128 6129 #define IWM_BARRIER_WRITE(sc) \ 6130 bus_space_barrier((sc)->sc_st, (sc)->sc_sh, 0, (sc)->sc_sz, \ 6131 BUS_SPACE_BARRIER_WRITE) 6132 6133 #define IWM_BARRIER_READ_WRITE(sc) \ 6134 bus_space_barrier((sc)->sc_st, (sc)->sc_sh, 0, (sc)->sc_sz, \ 6135 BUS_SPACE_BARRIER_READ | BUS_SPACE_BARRIER_WRITE) 6136 6137 #endif /* __IF_IWM_REG_H__ */ 6138