1 /* $OpenBSD: if_iwmreg.h,v 1.4 2015/06/15 08:06:11 stsp Exp $ */ 2 /* $FreeBSD$ */ 3 4 /****************************************************************************** 5 * 6 * This file is provided under a dual BSD/GPLv2 license. When using or 7 * redistributing this file, you may do so under either license. 8 * 9 * GPL LICENSE SUMMARY 10 * 11 * Copyright(c) 2005 - 2014 Intel Corporation. All rights reserved. 12 * 13 * This program is free software; you can redistribute it and/or modify 14 * it under the terms of version 2 of the GNU General Public License as 15 * published by the Free Software Foundation. 16 * 17 * This program is distributed in the hope that it will be useful, but 18 * WITHOUT ANY WARRANTY; without even the implied warranty of 19 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU 20 * General Public License for more details. 21 * 22 * You should have received a copy of the GNU General Public License 23 * along with this program; if not, write to the Free Software 24 * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110, 25 * USA 26 * 27 * The full GNU General Public License is included in this distribution 28 * in the file called COPYING. 29 * 30 * Contact Information: 31 * Intel Linux Wireless <ilw@linux.intel.com> 32 * Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497 33 * 34 * BSD LICENSE 35 * 36 * Copyright(c) 2005 - 2014 Intel Corporation. All rights reserved. 37 * All rights reserved. 38 * 39 * Redistribution and use in source and binary forms, with or without 40 * modification, are permitted provided that the following conditions 41 * are met: 42 * 43 * * Redistributions of source code must retain the above copyright 44 * notice, this list of conditions and the following disclaimer. 45 * * Redistributions in binary form must reproduce the above copyright 46 * notice, this list of conditions and the following disclaimer in 47 * the documentation and/or other materials provided with the 48 * distribution. 49 * * Neither the name Intel Corporation nor the names of its 50 * contributors may be used to endorse or promote products derived 51 * from this software without specific prior written permission. 52 * 53 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 54 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 55 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 56 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 57 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 58 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 59 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 60 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 61 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 62 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 63 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 64 * 65 *****************************************************************************/ 66 #ifndef __IF_IWM_REG_H__ 67 #define __IF_IWM_REG_H__ 68 69 #define le16_to_cpup(_a_) (le16toh(*(const uint16_t *)(_a_))) 70 #define le32_to_cpup(_a_) (le32toh(*(const uint32_t *)(_a_))) 71 72 /* 73 * BEGIN iwl-csr.h 74 */ 75 76 /* 77 * CSR (control and status registers) 78 * 79 * CSR registers are mapped directly into PCI bus space, and are accessible 80 * whenever platform supplies power to device, even when device is in 81 * low power states due to driver-invoked device resets 82 * (e.g. IWM_CSR_RESET_REG_FLAG_SW_RESET) or uCode-driven power-saving modes. 83 * 84 * Use iwl_write32() and iwl_read32() family to access these registers; 85 * these provide simple PCI bus access, without waking up the MAC. 86 * Do not use iwl_write_direct32() family for these registers; 87 * no need to "grab nic access" via IWM_CSR_GP_CNTRL_REG_FLAG_MAC_ACCESS_REQ. 88 * The MAC (uCode processor, etc.) does not need to be powered up for accessing 89 * the CSR registers. 90 * 91 * NOTE: Device does need to be awake in order to read this memory 92 * via IWM_CSR_EEPROM and IWM_CSR_OTP registers 93 */ 94 #define IWM_CSR_HW_IF_CONFIG_REG (0x000) /* hardware interface config */ 95 #define IWM_CSR_INT_COALESCING (0x004) /* accum ints, 32-usec units */ 96 #define IWM_CSR_INT (0x008) /* host interrupt status/ack */ 97 #define IWM_CSR_INT_MASK (0x00c) /* host interrupt enable */ 98 #define IWM_CSR_FH_INT_STATUS (0x010) /* busmaster int status/ack*/ 99 #define IWM_CSR_GPIO_IN (0x018) /* read external chip pins */ 100 #define IWM_CSR_RESET (0x020) /* busmaster enable, NMI, etc*/ 101 #define IWM_CSR_GP_CNTRL (0x024) 102 103 /* 2nd byte of IWM_CSR_INT_COALESCING, not accessible via iwl_write32()! */ 104 #define IWM_CSR_INT_PERIODIC_REG (0x005) 105 106 /* 107 * Hardware revision info 108 * Bit fields: 109 * 31-16: Reserved 110 * 15-4: Type of device: see IWM_CSR_HW_REV_TYPE_xxx definitions 111 * 3-2: Revision step: 0 = A, 1 = B, 2 = C, 3 = D 112 * 1-0: "Dash" (-) value, as in A-1, etc. 113 */ 114 #define IWM_CSR_HW_REV (0x028) 115 116 /* 117 * EEPROM and OTP (one-time-programmable) memory reads 118 * 119 * NOTE: Device must be awake, initialized via apm_ops.init(), 120 * in order to read. 121 */ 122 #define IWM_CSR_EEPROM_REG (0x02c) 123 #define IWM_CSR_EEPROM_GP (0x030) 124 #define IWM_CSR_OTP_GP_REG (0x034) 125 126 #define IWM_CSR_GIO_REG (0x03C) 127 #define IWM_CSR_GP_UCODE_REG (0x048) 128 #define IWM_CSR_GP_DRIVER_REG (0x050) 129 130 /* 131 * UCODE-DRIVER GP (general purpose) mailbox registers. 132 * SET/CLR registers set/clear bit(s) if "1" is written. 133 */ 134 #define IWM_CSR_UCODE_DRV_GP1 (0x054) 135 #define IWM_CSR_UCODE_DRV_GP1_SET (0x058) 136 #define IWM_CSR_UCODE_DRV_GP1_CLR (0x05c) 137 #define IWM_CSR_UCODE_DRV_GP2 (0x060) 138 139 #define IWM_CSR_MBOX_SET_REG (0x088) 140 #define IWM_CSR_MBOX_SET_REG_OS_ALIVE 0x20 141 142 #define IWM_CSR_LED_REG (0x094) 143 #define IWM_CSR_DRAM_INT_TBL_REG (0x0A0) 144 #define IWM_CSR_MAC_SHADOW_REG_CTRL (0x0A8) /* 6000 and up */ 145 146 147 /* GIO Chicken Bits (PCI Express bus link power management) */ 148 #define IWM_CSR_GIO_CHICKEN_BITS (0x100) 149 150 /* Analog phase-lock-loop configuration */ 151 #define IWM_CSR_ANA_PLL_CFG (0x20c) 152 153 /* 154 * CSR Hardware Revision Workaround Register. Indicates hardware rev; 155 * "step" determines CCK backoff for txpower calculation. Used for 4965 only. 156 * See also IWM_CSR_HW_REV register. 157 * Bit fields: 158 * 3-2: 0 = A, 1 = B, 2 = C, 3 = D step 159 * 1-0: "Dash" (-) value, as in C-1, etc. 160 */ 161 #define IWM_CSR_HW_REV_WA_REG (0x22C) 162 163 #define IWM_CSR_DBG_HPET_MEM_REG (0x240) 164 #define IWM_CSR_DBG_LINK_PWR_MGMT_REG (0x250) 165 166 /* Bits for IWM_CSR_HW_IF_CONFIG_REG */ 167 #define IWM_CSR_HW_IF_CONFIG_REG_MSK_MAC_DASH (0x00000003) 168 #define IWM_CSR_HW_IF_CONFIG_REG_MSK_MAC_STEP (0x0000000C) 169 #define IWM_CSR_HW_IF_CONFIG_REG_MSK_BOARD_VER (0x000000C0) 170 #define IWM_CSR_HW_IF_CONFIG_REG_BIT_MAC_SI (0x00000100) 171 #define IWM_CSR_HW_IF_CONFIG_REG_BIT_RADIO_SI (0x00000200) 172 #define IWM_CSR_HW_IF_CONFIG_REG_MSK_PHY_TYPE (0x00000C00) 173 #define IWM_CSR_HW_IF_CONFIG_REG_MSK_PHY_DASH (0x00003000) 174 #define IWM_CSR_HW_IF_CONFIG_REG_MSK_PHY_STEP (0x0000C000) 175 176 #define IWM_CSR_HW_IF_CONFIG_REG_POS_MAC_DASH (0) 177 #define IWM_CSR_HW_IF_CONFIG_REG_POS_MAC_STEP (2) 178 #define IWM_CSR_HW_IF_CONFIG_REG_POS_BOARD_VER (6) 179 #define IWM_CSR_HW_IF_CONFIG_REG_POS_PHY_TYPE (10) 180 #define IWM_CSR_HW_IF_CONFIG_REG_POS_PHY_DASH (12) 181 #define IWM_CSR_HW_IF_CONFIG_REG_POS_PHY_STEP (14) 182 183 #define IWM_CSR_HW_IF_CONFIG_REG_BIT_HAP_WAKE_L1A (0x00080000) 184 #define IWM_CSR_HW_IF_CONFIG_REG_BIT_EEPROM_OWN_SEM (0x00200000) 185 #define IWM_CSR_HW_IF_CONFIG_REG_BIT_NIC_READY (0x00400000) /* PCI_OWN_SEM */ 186 #define IWM_CSR_HW_IF_CONFIG_REG_BIT_NIC_PREPARE_DONE (0x02000000) /* ME_OWN */ 187 #define IWM_CSR_HW_IF_CONFIG_REG_PREPARE (0x08000000) /* WAKE_ME */ 188 #define IWM_CSR_HW_IF_CONFIG_REG_ENABLE_PME (0x10000000) 189 #define IWM_CSR_HW_IF_CONFIG_REG_PERSIST_MODE (0x40000000) /* PERSISTENCE */ 190 191 #define IWM_CSR_INT_PERIODIC_DIS (0x00) /* disable periodic int*/ 192 #define IWM_CSR_INT_PERIODIC_ENA (0xFF) /* 255*32 usec ~ 8 msec*/ 193 194 /* interrupt flags in INTA, set by uCode or hardware (e.g. dma), 195 * acknowledged (reset) by host writing "1" to flagged bits. */ 196 #define IWM_CSR_INT_BIT_FH_RX (1 << 31) /* Rx DMA, cmd responses, FH_INT[17:16] */ 197 #define IWM_CSR_INT_BIT_HW_ERR (1 << 29) /* DMA hardware error FH_INT[31] */ 198 #define IWM_CSR_INT_BIT_RX_PERIODIC (1 << 28) /* Rx periodic */ 199 #define IWM_CSR_INT_BIT_FH_TX (1 << 27) /* Tx DMA FH_INT[1:0] */ 200 #define IWM_CSR_INT_BIT_SCD (1 << 26) /* TXQ pointer advanced */ 201 #define IWM_CSR_INT_BIT_SW_ERR (1 << 25) /* uCode error */ 202 #define IWM_CSR_INT_BIT_RF_KILL (1 << 7) /* HW RFKILL switch GP_CNTRL[27] toggled */ 203 #define IWM_CSR_INT_BIT_CT_KILL (1 << 6) /* Critical temp (chip too hot) rfkill */ 204 #define IWM_CSR_INT_BIT_SW_RX (1 << 3) /* Rx, command responses */ 205 #define IWM_CSR_INT_BIT_WAKEUP (1 << 1) /* NIC controller waking up (pwr mgmt) */ 206 #define IWM_CSR_INT_BIT_ALIVE (1 << 0) /* uCode interrupts once it initializes */ 207 208 #define IWM_CSR_INI_SET_MASK (IWM_CSR_INT_BIT_FH_RX | \ 209 IWM_CSR_INT_BIT_HW_ERR | \ 210 IWM_CSR_INT_BIT_FH_TX | \ 211 IWM_CSR_INT_BIT_SW_ERR | \ 212 IWM_CSR_INT_BIT_RF_KILL | \ 213 IWM_CSR_INT_BIT_SW_RX | \ 214 IWM_CSR_INT_BIT_WAKEUP | \ 215 IWM_CSR_INT_BIT_ALIVE | \ 216 IWM_CSR_INT_BIT_RX_PERIODIC) 217 218 /* interrupt flags in FH (flow handler) (PCI busmaster DMA) */ 219 #define IWM_CSR_FH_INT_BIT_ERR (1 << 31) /* Error */ 220 #define IWM_CSR_FH_INT_BIT_HI_PRIOR (1 << 30) /* High priority Rx, bypass coalescing */ 221 #define IWM_CSR_FH_INT_BIT_RX_CHNL1 (1 << 17) /* Rx channel 1 */ 222 #define IWM_CSR_FH_INT_BIT_RX_CHNL0 (1 << 16) /* Rx channel 0 */ 223 #define IWM_CSR_FH_INT_BIT_TX_CHNL1 (1 << 1) /* Tx channel 1 */ 224 #define IWM_CSR_FH_INT_BIT_TX_CHNL0 (1 << 0) /* Tx channel 0 */ 225 226 #define IWM_CSR_FH_INT_RX_MASK (IWM_CSR_FH_INT_BIT_HI_PRIOR | \ 227 IWM_CSR_FH_INT_BIT_RX_CHNL1 | \ 228 IWM_CSR_FH_INT_BIT_RX_CHNL0) 229 230 #define IWM_CSR_FH_INT_TX_MASK (IWM_CSR_FH_INT_BIT_TX_CHNL1 | \ 231 IWM_CSR_FH_INT_BIT_TX_CHNL0) 232 233 /* GPIO */ 234 #define IWM_CSR_GPIO_IN_BIT_AUX_POWER (0x00000200) 235 #define IWM_CSR_GPIO_IN_VAL_VAUX_PWR_SRC (0x00000000) 236 #define IWM_CSR_GPIO_IN_VAL_VMAIN_PWR_SRC (0x00000200) 237 238 /* RESET */ 239 #define IWM_CSR_RESET_REG_FLAG_NEVO_RESET (0x00000001) 240 #define IWM_CSR_RESET_REG_FLAG_FORCE_NMI (0x00000002) 241 #define IWM_CSR_RESET_REG_FLAG_SW_RESET (0x00000080) 242 #define IWM_CSR_RESET_REG_FLAG_MASTER_DISABLED (0x00000100) 243 #define IWM_CSR_RESET_REG_FLAG_STOP_MASTER (0x00000200) 244 #define IWM_CSR_RESET_LINK_PWR_MGMT_DISABLED (0x80000000) 245 246 /* 247 * GP (general purpose) CONTROL REGISTER 248 * Bit fields: 249 * 27: HW_RF_KILL_SW 250 * Indicates state of (platform's) hardware RF-Kill switch 251 * 26-24: POWER_SAVE_TYPE 252 * Indicates current power-saving mode: 253 * 000 -- No power saving 254 * 001 -- MAC power-down 255 * 010 -- PHY (radio) power-down 256 * 011 -- Error 257 * 9-6: SYS_CONFIG 258 * Indicates current system configuration, reflecting pins on chip 259 * as forced high/low by device circuit board. 260 * 4: GOING_TO_SLEEP 261 * Indicates MAC is entering a power-saving sleep power-down. 262 * Not a good time to access device-internal resources. 263 * 3: MAC_ACCESS_REQ 264 * Host sets this to request and maintain MAC wakeup, to allow host 265 * access to device-internal resources. Host must wait for 266 * MAC_CLOCK_READY (and !GOING_TO_SLEEP) before accessing non-CSR 267 * device registers. 268 * 2: INIT_DONE 269 * Host sets this to put device into fully operational D0 power mode. 270 * Host resets this after SW_RESET to put device into low power mode. 271 * 0: MAC_CLOCK_READY 272 * Indicates MAC (ucode processor, etc.) is powered up and can run. 273 * Internal resources are accessible. 274 * NOTE: This does not indicate that the processor is actually running. 275 * NOTE: This does not indicate that device has completed 276 * init or post-power-down restore of internal SRAM memory. 277 * Use IWM_CSR_UCODE_DRV_GP1_BIT_MAC_SLEEP as indication that 278 * SRAM is restored and uCode is in normal operation mode. 279 * Later devices (5xxx/6xxx/1xxx) use non-volatile SRAM, and 280 * do not need to save/restore it. 281 * NOTE: After device reset, this bit remains "0" until host sets 282 * INIT_DONE 283 */ 284 #define IWM_CSR_GP_CNTRL_REG_FLAG_MAC_CLOCK_READY (0x00000001) 285 #define IWM_CSR_GP_CNTRL_REG_FLAG_INIT_DONE (0x00000004) 286 #define IWM_CSR_GP_CNTRL_REG_FLAG_MAC_ACCESS_REQ (0x00000008) 287 #define IWM_CSR_GP_CNTRL_REG_FLAG_GOING_TO_SLEEP (0x00000010) 288 289 #define IWM_CSR_GP_CNTRL_REG_VAL_MAC_ACCESS_EN (0x00000001) 290 291 #define IWM_CSR_GP_CNTRL_REG_MSK_POWER_SAVE_TYPE (0x07000000) 292 #define IWM_CSR_GP_CNTRL_REG_FLAG_MAC_POWER_SAVE (0x04000000) 293 #define IWM_CSR_GP_CNTRL_REG_FLAG_HW_RF_KILL_SW (0x08000000) 294 295 296 /* HW REV */ 297 #define IWM_CSR_HW_REV_DASH(_val) (((_val) & 0x0000003) >> 0) 298 #define IWM_CSR_HW_REV_STEP(_val) (((_val) & 0x000000C) >> 2) 299 300 /** 301 * hw_rev values 302 */ 303 enum { 304 IWM_SILICON_A_STEP = 0, 305 IWM_SILICON_B_STEP, 306 IWM_SILICON_C_STEP, 307 }; 308 309 310 #define IWM_CSR_HW_REV_TYPE_MSK (0x000FFF0) 311 #define IWM_CSR_HW_REV_TYPE_5300 (0x0000020) 312 #define IWM_CSR_HW_REV_TYPE_5350 (0x0000030) 313 #define IWM_CSR_HW_REV_TYPE_5100 (0x0000050) 314 #define IWM_CSR_HW_REV_TYPE_5150 (0x0000040) 315 #define IWM_CSR_HW_REV_TYPE_1000 (0x0000060) 316 #define IWM_CSR_HW_REV_TYPE_6x00 (0x0000070) 317 #define IWM_CSR_HW_REV_TYPE_6x50 (0x0000080) 318 #define IWM_CSR_HW_REV_TYPE_6150 (0x0000084) 319 #define IWM_CSR_HW_REV_TYPE_6x05 (0x00000B0) 320 #define IWM_CSR_HW_REV_TYPE_6x30 IWM_CSR_HW_REV_TYPE_6x05 321 #define IWM_CSR_HW_REV_TYPE_6x35 IWM_CSR_HW_REV_TYPE_6x05 322 #define IWM_CSR_HW_REV_TYPE_2x30 (0x00000C0) 323 #define IWM_CSR_HW_REV_TYPE_2x00 (0x0000100) 324 #define IWM_CSR_HW_REV_TYPE_105 (0x0000110) 325 #define IWM_CSR_HW_REV_TYPE_135 (0x0000120) 326 #define IWM_CSR_HW_REV_TYPE_7265D (0x0000210) 327 #define IWM_CSR_HW_REV_TYPE_NONE (0x00001F0) 328 329 /* EEPROM REG */ 330 #define IWM_CSR_EEPROM_REG_READ_VALID_MSK (0x00000001) 331 #define IWM_CSR_EEPROM_REG_BIT_CMD (0x00000002) 332 #define IWM_CSR_EEPROM_REG_MSK_ADDR (0x0000FFFC) 333 #define IWM_CSR_EEPROM_REG_MSK_DATA (0xFFFF0000) 334 335 /* EEPROM GP */ 336 #define IWM_CSR_EEPROM_GP_VALID_MSK (0x00000007) /* signature */ 337 #define IWM_CSR_EEPROM_GP_IF_OWNER_MSK (0x00000180) 338 #define IWM_CSR_EEPROM_GP_BAD_SIGNATURE_BOTH_EEP_AND_OTP (0x00000000) 339 #define IWM_CSR_EEPROM_GP_BAD_SIG_EEP_GOOD_SIG_OTP (0x00000001) 340 #define IWM_CSR_EEPROM_GP_GOOD_SIG_EEP_LESS_THAN_4K (0x00000002) 341 #define IWM_CSR_EEPROM_GP_GOOD_SIG_EEP_MORE_THAN_4K (0x00000004) 342 343 /* One-time-programmable memory general purpose reg */ 344 #define IWM_CSR_OTP_GP_REG_DEVICE_SELECT (0x00010000) /* 0 - EEPROM, 1 - OTP */ 345 #define IWM_CSR_OTP_GP_REG_OTP_ACCESS_MODE (0x00020000) /* 0 - absolute, 1 - relative */ 346 #define IWM_CSR_OTP_GP_REG_ECC_CORR_STATUS_MSK (0x00100000) /* bit 20 */ 347 #define IWM_CSR_OTP_GP_REG_ECC_UNCORR_STATUS_MSK (0x00200000) /* bit 21 */ 348 349 /* GP REG */ 350 #define IWM_CSR_GP_REG_POWER_SAVE_STATUS_MSK (0x03000000) /* bit 24/25 */ 351 #define IWM_CSR_GP_REG_NO_POWER_SAVE (0x00000000) 352 #define IWM_CSR_GP_REG_MAC_POWER_SAVE (0x01000000) 353 #define IWM_CSR_GP_REG_PHY_POWER_SAVE (0x02000000) 354 #define IWM_CSR_GP_REG_POWER_SAVE_ERROR (0x03000000) 355 356 357 /* CSR GIO */ 358 #define IWM_CSR_GIO_REG_VAL_L0S_ENABLED (0x00000002) 359 360 /* 361 * UCODE-DRIVER GP (general purpose) mailbox register 1 362 * Host driver and uCode write and/or read this register to communicate with 363 * each other. 364 * Bit fields: 365 * 4: UCODE_DISABLE 366 * Host sets this to request permanent halt of uCode, same as 367 * sending CARD_STATE command with "halt" bit set. 368 * 3: CT_KILL_EXIT 369 * Host sets this to request exit from CT_KILL state, i.e. host thinks 370 * device temperature is low enough to continue normal operation. 371 * 2: CMD_BLOCKED 372 * Host sets this during RF KILL power-down sequence (HW, SW, CT KILL) 373 * to release uCode to clear all Tx and command queues, enter 374 * unassociated mode, and power down. 375 * NOTE: Some devices also use HBUS_TARG_MBX_C register for this bit. 376 * 1: SW_BIT_RFKILL 377 * Host sets this when issuing CARD_STATE command to request 378 * device sleep. 379 * 0: MAC_SLEEP 380 * uCode sets this when preparing a power-saving power-down. 381 * uCode resets this when power-up is complete and SRAM is sane. 382 * NOTE: device saves internal SRAM data to host when powering down, 383 * and must restore this data after powering back up. 384 * MAC_SLEEP is the best indication that restore is complete. 385 * Later devices (5xxx/6xxx/1xxx) use non-volatile SRAM, and 386 * do not need to save/restore it. 387 */ 388 #define IWM_CSR_UCODE_DRV_GP1_BIT_MAC_SLEEP (0x00000001) 389 #define IWM_CSR_UCODE_SW_BIT_RFKILL (0x00000002) 390 #define IWM_CSR_UCODE_DRV_GP1_BIT_CMD_BLOCKED (0x00000004) 391 #define IWM_CSR_UCODE_DRV_GP1_REG_BIT_CT_KILL_EXIT (0x00000008) 392 #define IWM_CSR_UCODE_DRV_GP1_BIT_D3_CFG_COMPLETE (0x00000020) 393 394 /* GP Driver */ 395 #define IWM_CSR_GP_DRIVER_REG_BIT_RADIO_SKU_MSK (0x00000003) 396 #define IWM_CSR_GP_DRIVER_REG_BIT_RADIO_SKU_3x3_HYB (0x00000000) 397 #define IWM_CSR_GP_DRIVER_REG_BIT_RADIO_SKU_2x2_HYB (0x00000001) 398 #define IWM_CSR_GP_DRIVER_REG_BIT_RADIO_SKU_2x2_IPA (0x00000002) 399 #define IWM_CSR_GP_DRIVER_REG_BIT_CALIB_VERSION6 (0x00000004) 400 #define IWM_CSR_GP_DRIVER_REG_BIT_6050_1x2 (0x00000008) 401 402 #define IWM_CSR_GP_DRIVER_REG_BIT_RADIO_IQ_INVER (0x00000080) 403 404 /* GIO Chicken Bits (PCI Express bus link power management) */ 405 #define IWM_CSR_GIO_CHICKEN_BITS_REG_BIT_L1A_NO_L0S_RX (0x00800000) 406 #define IWM_CSR_GIO_CHICKEN_BITS_REG_BIT_DIS_L0S_EXIT_TIMER (0x20000000) 407 408 /* LED */ 409 #define IWM_CSR_LED_BSM_CTRL_MSK (0xFFFFFFDF) 410 #define IWM_CSR_LED_REG_TURN_ON (0x60) 411 #define IWM_CSR_LED_REG_TURN_OFF (0x20) 412 413 /* ANA_PLL */ 414 #define IWM_CSR50_ANA_PLL_CFG_VAL (0x00880300) 415 416 /* HPET MEM debug */ 417 #define IWM_CSR_DBG_HPET_MEM_REG_VAL (0xFFFF0000) 418 419 /* DRAM INT TABLE */ 420 #define IWM_CSR_DRAM_INT_TBL_ENABLE (1 << 31) 421 #define IWM_CSR_DRAM_INIT_TBL_WRITE_POINTER (1 << 28) 422 #define IWM_CSR_DRAM_INIT_TBL_WRAP_CHECK (1 << 27) 423 424 /* SECURE boot registers */ 425 #define IWM_CSR_SECURE_BOOT_CONFIG_ADDR (0x100) 426 enum iwm_secure_boot_config_reg { 427 IWM_CSR_SECURE_BOOT_CONFIG_INSPECTOR_BURNED_IN_OTP = 0x00000001, 428 IWM_CSR_SECURE_BOOT_CONFIG_INSPECTOR_NOT_REQ = 0x00000002, 429 }; 430 431 #define IWM_CSR_SECURE_BOOT_CPU1_STATUS_ADDR (0x100) 432 #define IWM_CSR_SECURE_BOOT_CPU2_STATUS_ADDR (0x100) 433 enum iwm_secure_boot_status_reg { 434 IWM_CSR_SECURE_BOOT_CPU_STATUS_VERF_STATUS = 0x00000003, 435 IWM_CSR_SECURE_BOOT_CPU_STATUS_VERF_COMPLETED = 0x00000002, 436 IWM_CSR_SECURE_BOOT_CPU_STATUS_VERF_SUCCESS = 0x00000004, 437 IWM_CSR_SECURE_BOOT_CPU_STATUS_VERF_FAIL = 0x00000008, 438 IWM_CSR_SECURE_BOOT_CPU_STATUS_SIGN_VERF_FAIL = 0x00000010, 439 }; 440 441 #define IWM_FH_UCODE_LOAD_STATUS 0x1af0 442 #define IWM_FH_MEM_TB_MAX_LENGTH 0x20000 443 444 #define IWM_LMPM_SECURE_UCODE_LOAD_CPU1_HDR_ADDR 0x1e78 445 #define IWM_LMPM_SECURE_UCODE_LOAD_CPU2_HDR_ADDR 0x1e7c 446 447 #define IWM_LMPM_SECURE_CPU1_HDR_MEM_SPACE 0x420000 448 #define IWM_LMPM_SECURE_CPU2_HDR_MEM_SPACE 0x420400 449 450 #define IWM_CSR_SECURE_TIME_OUT (100) 451 452 /* extended range in FW SRAM */ 453 #define IWM_FW_MEM_EXTENDED_START 0x40000 454 #define IWM_FW_MEM_EXTENDED_END 0x57FFF 455 456 /* FW chicken bits */ 457 #define IWM_LMPM_CHICK 0xa01ff8 458 #define IWM_LMPM_CHICK_EXTENDED_ADDR_SPACE 0x01 459 460 #define IWM_FH_TCSR_0_REG0 (0x1D00) 461 462 /* 463 * HBUS (Host-side Bus) 464 * 465 * HBUS registers are mapped directly into PCI bus space, but are used 466 * to indirectly access device's internal memory or registers that 467 * may be powered-down. 468 * 469 * Use iwl_write_direct32()/iwl_read_direct32() family for these registers; 470 * host must "grab nic access" via CSR_GP_CNTRL_REG_FLAG_MAC_ACCESS_REQ 471 * to make sure the MAC (uCode processor, etc.) is powered up for accessing 472 * internal resources. 473 * 474 * Do not use iwl_write32()/iwl_read32() family to access these registers; 475 * these provide only simple PCI bus access, without waking up the MAC. 476 */ 477 #define IWM_HBUS_BASE (0x400) 478 479 /* 480 * Registers for accessing device's internal SRAM memory (e.g. SCD SRAM 481 * structures, error log, event log, verifying uCode load). 482 * First write to address register, then read from or write to data register 483 * to complete the job. Once the address register is set up, accesses to 484 * data registers auto-increment the address by one dword. 485 * Bit usage for address registers (read or write): 486 * 0-31: memory address within device 487 */ 488 #define IWM_HBUS_TARG_MEM_RADDR (IWM_HBUS_BASE+0x00c) 489 #define IWM_HBUS_TARG_MEM_WADDR (IWM_HBUS_BASE+0x010) 490 #define IWM_HBUS_TARG_MEM_WDAT (IWM_HBUS_BASE+0x018) 491 #define IWM_HBUS_TARG_MEM_RDAT (IWM_HBUS_BASE+0x01c) 492 493 /* Mailbox C, used as workaround alternative to CSR_UCODE_DRV_GP1 mailbox */ 494 #define IWM_HBUS_TARG_MBX_C (IWM_HBUS_BASE+0x030) 495 #define IWM_HBUS_TARG_MBX_C_REG_BIT_CMD_BLOCKED (0x00000004) 496 497 /* 498 * Registers for accessing device's internal peripheral registers 499 * (e.g. SCD, BSM, etc.). First write to address register, 500 * then read from or write to data register to complete the job. 501 * Bit usage for address registers (read or write): 502 * 0-15: register address (offset) within device 503 * 24-25: (# bytes - 1) to read or write (e.g. 3 for dword) 504 */ 505 #define IWM_HBUS_TARG_PRPH_WADDR (IWM_HBUS_BASE+0x044) 506 #define IWM_HBUS_TARG_PRPH_RADDR (IWM_HBUS_BASE+0x048) 507 #define IWM_HBUS_TARG_PRPH_WDAT (IWM_HBUS_BASE+0x04c) 508 #define IWM_HBUS_TARG_PRPH_RDAT (IWM_HBUS_BASE+0x050) 509 510 /* enable the ID buf for read */ 511 #define IWM_WFPM_PS_CTL_CLR 0xa0300c 512 #define IWM_WFMP_MAC_ADDR_0 0xa03080 513 #define IWM_WFMP_MAC_ADDR_1 0xa03084 514 #define IWM_LMPM_PMG_EN 0xa01cec 515 #define IWM_RADIO_REG_SYS_MANUAL_DFT_0 0xad4078 516 #define IWM_RFIC_REG_RD 0xad0470 517 #define IWM_WFPM_CTRL_REG 0xa03030 518 #define IWM_WFPM_AUX_CTL_AUX_IF_MAC_OWNER_MSK 0x08000000 519 #define IWM_ENABLE_WFPM 0x80000000 520 521 #define IWM_AUX_MISC_REG 0xa200b0 522 #define IWM_HW_STEP_LOCATION_BITS 24 523 524 #define IWM_AUX_MISC_MASTER1_EN 0xa20818 525 #define IWM_AUX_MISC_MASTER1_EN_SBE_MSK 0x1 526 #define IWM_AUX_MISC_MASTER1_SMPHR_STATUS 0xa20800 527 #define IWM_RSA_ENABLE 0xa24b08 528 #define IWM_PREG_AUX_BUS_WPROT_0 0xa04cc0 529 #define IWM_SB_CFG_OVERRIDE_ADDR 0xa26c78 530 #define IWM_SB_CFG_OVERRIDE_ENABLE 0x8000 531 #define IWM_SB_CFG_BASE_OVERRIDE 0xa20000 532 #define IWM_SB_MODIFY_CFG_FLAG 0xa03088 533 #define IWM_SB_CPU_1_STATUS 0xa01e30 534 #define IWM_SB_CPU_2_STATUS 0Xa01e34 535 536 /* Used to enable DBGM */ 537 #define IWM_HBUS_TARG_TEST_REG (IWM_HBUS_BASE+0x05c) 538 539 /* 540 * Per-Tx-queue write pointer (index, really!) 541 * Indicates index to next TFD that driver will fill (1 past latest filled). 542 * Bit usage: 543 * 0-7: queue write index 544 * 11-8: queue selector 545 */ 546 #define IWM_HBUS_TARG_WRPTR (IWM_HBUS_BASE+0x060) 547 548 /********************************************************** 549 * CSR values 550 **********************************************************/ 551 /* 552 * host interrupt timeout value 553 * used with setting interrupt coalescing timer 554 * the CSR_INT_COALESCING is an 8 bit register in 32-usec unit 555 * 556 * default interrupt coalescing timer is 64 x 32 = 2048 usecs 557 */ 558 #define IWM_HOST_INT_TIMEOUT_MAX (0xFF) 559 #define IWM_HOST_INT_TIMEOUT_DEF (0x40) 560 #define IWM_HOST_INT_TIMEOUT_MIN (0x0) 561 #define IWM_HOST_INT_OPER_MODE (1 << 31) 562 563 /***************************************************************************** 564 * 7000/3000 series SHR DTS addresses * 565 *****************************************************************************/ 566 567 /* Diode Results Register Structure: */ 568 enum iwm_dtd_diode_reg { 569 IWM_DTS_DIODE_REG_DIG_VAL = 0x000000FF, /* bits [7:0] */ 570 IWM_DTS_DIODE_REG_VREF_LOW = 0x0000FF00, /* bits [15:8] */ 571 IWM_DTS_DIODE_REG_VREF_HIGH = 0x00FF0000, /* bits [23:16] */ 572 IWM_DTS_DIODE_REG_VREF_ID = 0x03000000, /* bits [25:24] */ 573 IWM_DTS_DIODE_REG_PASS_ONCE = 0x80000000, /* bits [31:31] */ 574 IWM_DTS_DIODE_REG_FLAGS_MSK = 0xFF000000, /* bits [31:24] */ 575 /* Those are the masks INSIDE the flags bit-field: */ 576 IWM_DTS_DIODE_REG_FLAGS_VREFS_ID_POS = 0, 577 IWM_DTS_DIODE_REG_FLAGS_VREFS_ID = 0x00000003, /* bits [1:0] */ 578 IWM_DTS_DIODE_REG_FLAGS_PASS_ONCE_POS = 7, 579 IWM_DTS_DIODE_REG_FLAGS_PASS_ONCE = 0x00000080, /* bits [7:7] */ 580 }; 581 582 /* 583 * END iwl-csr.h 584 */ 585 586 /* 587 * BEGIN iwl-fw.h 588 */ 589 590 /** 591 * enum iwm_ucode_tlv_flag - ucode API flags 592 * @IWM_UCODE_TLV_FLAGS_PAN: This is PAN capable microcode; this previously 593 * was a separate TLV but moved here to save space. 594 * @IWM_UCODE_TLV_FLAGS_NEWSCAN: new uCode scan behaviour on hidden SSID, 595 * treats good CRC threshold as a boolean 596 * @IWM_UCODE_TLV_FLAGS_MFP: This uCode image supports MFP (802.11w). 597 * @IWM_UCODE_TLV_FLAGS_UAPSD: This uCode image supports uAPSD 598 * @IWM_UCODE_TLV_FLAGS_SHORT_BL: 16 entries of black list instead of 64 in scan 599 * offload profile config command. 600 * @IWM_UCODE_TLV_FLAGS_D3_6_IPV6_ADDRS: D3 image supports up to six 601 * (rather than two) IPv6 addresses 602 * @IWM_UCODE_TLV_FLAGS_NO_BASIC_SSID: not sending a probe with the SSID element 603 * from the probe request template. 604 * @IWM_UCODE_TLV_FLAGS_NEW_NSOFFL_SMALL: new NS offload (small version) 605 * @IWM_UCODE_TLV_FLAGS_NEW_NSOFFL_LARGE: new NS offload (large version) 606 * @IWM_UCODE_TLV_FLAGS_UAPSD_SUPPORT: General support for uAPSD 607 * @IWM_UCODE_TLV_FLAGS_EBS_SUPPORT: this uCode image supports EBS. 608 * @IWM_UCODE_TLV_FLAGS_P2P_PS_UAPSD: P2P client supports uAPSD power save 609 * @IWM_UCODE_TLV_FLAGS_BCAST_FILTERING: uCode supports broadcast filtering. 610 */ 611 enum iwm_ucode_tlv_flag { 612 IWM_UCODE_TLV_FLAGS_PAN = (1 << 0), 613 IWM_UCODE_TLV_FLAGS_NEWSCAN = (1 << 1), 614 IWM_UCODE_TLV_FLAGS_MFP = (1 << 2), 615 IWM_UCODE_TLV_FLAGS_SHORT_BL = (1 << 7), 616 IWM_UCODE_TLV_FLAGS_D3_6_IPV6_ADDRS = (1 << 10), 617 IWM_UCODE_TLV_FLAGS_NO_BASIC_SSID = (1 << 12), 618 IWM_UCODE_TLV_FLAGS_NEW_NSOFFL_SMALL = (1 << 15), 619 IWM_UCODE_TLV_FLAGS_NEW_NSOFFL_LARGE = (1 << 16), 620 IWM_UCODE_TLV_FLAGS_UAPSD_SUPPORT = (1 << 24), 621 IWM_UCODE_TLV_FLAGS_EBS_SUPPORT = (1 << 25), 622 IWM_UCODE_TLV_FLAGS_P2P_PS_UAPSD = (1 << 26), 623 IWM_UCODE_TLV_FLAGS_BCAST_FILTERING = (1 << 29), 624 }; 625 626 #define IWM_UCODE_TLV_FLAG_BITS \ 627 "\020\1PAN\2NEWSCAN\3MFP\4P2P\5DW_BC_TABLE\6NEWBT_COEX\7PM_CMD\10SHORT_BL\11RX_ENERG \ 628 Y\12TIME_EVENT_V2\13D3_6_IPV6\14BF_UPDATED\15NO_BASIC_SSID\17D3_CONTINUITY\20NEW_NSOFF \ 629 L_S\21NEW_NSOFFL_L\22SCHED_SCAN\24STA_KEY_CMD\25DEVICE_PS_CMD\26P2P_PS\27P2P_PS_DCM\30 \ 630 P2P_PS_SCM\31UAPSD_SUPPORT\32EBS\33P2P_PS_UAPSD\36BCAST_FILTERING\37GO_UAPSD\40LTE_COEX" 631 632 /** 633 * enum iwm_ucode_tlv_api - ucode api 634 * @IWM_UCODE_TLV_API_FRAGMENTED_SCAN: This ucode supports active dwell time 635 * longer than the passive one, which is essential for fragmented scan. 636 * @IWM_UCODE_TLV_API_WIFI_MCC_UPDATE: ucode supports MCC updates with source. 637 * @IWM_UCODE_TLV_API_LQ_SS_PARAMS: Configure STBC/BFER via LQ CMD ss_params 638 * 639 * @IWM_NUM_UCODE_TLV_API: number of bits used 640 */ 641 enum iwm_ucode_tlv_api { 642 IWM_UCODE_TLV_API_FRAGMENTED_SCAN = 8, 643 IWM_UCODE_TLV_API_WIFI_MCC_UPDATE = 9, 644 IWM_UCODE_TLV_API_LQ_SS_PARAMS = 18, 645 646 IWM_NUM_UCODE_TLV_API = 32 647 }; 648 649 #define IWM_UCODE_TLV_API_BITS \ 650 "\020\10FRAGMENTED_SCAN\11WIFI_MCC_UPDATE\16WIDE_CMD_HDR\22LQ_SS_PARAMS\30EXT_SCAN_PRIO\33TX_POWER_CHAIN" 651 652 /** 653 * enum iwm_ucode_tlv_capa - ucode capabilities 654 * @IWM_UCODE_TLV_CAPA_D0I3_SUPPORT: supports D0i3 655 * @IWM_UCODE_TLV_CAPA_LAR_SUPPORT: supports Location Aware Regulatory 656 * @IWM_UCODE_TLV_CAPA_UMAC_SCAN: supports UMAC scan. 657 * @IWM_UCODE_TLV_CAPA_BEAMFORMER: supports Beamformer 658 * @IWM_UCODE_TLV_CAPA_TOF_SUPPORT: supports Time of Flight (802.11mc FTM) 659 * @IWM_UCODE_TLV_CAPA_TDLS_SUPPORT: support basic TDLS functionality 660 * @IWM_UCODE_TLV_CAPA_TXPOWER_INSERTION_SUPPORT: supports insertion of current 661 * tx power value into TPC Report action frame and Link Measurement Report 662 * action frame 663 * @IWM_UCODE_TLV_CAPA_DS_PARAM_SET_IE_SUPPORT: supports updating current 664 * channel in DS parameter set element in probe requests. 665 * @IWM_UCODE_TLV_CAPA_WFA_TPC_REP_IE_SUPPORT: supports adding TPC Report IE in 666 * probe requests. 667 * @IWM_UCODE_TLV_CAPA_QUIET_PERIOD_SUPPORT: supports Quiet Period requests 668 * @IWM_UCODE_TLV_CAPA_DQA_SUPPORT: supports dynamic queue allocation (DQA), 669 * which also implies support for the scheduler configuration command 670 * @IWM_UCODE_TLV_CAPA_TDLS_CHANNEL_SWITCH: supports TDLS channel switching 671 * @IWM_UCODE_TLV_CAPA_CNSLDTD_D3_D0_IMG: Consolidated D3-D0 image 672 * @IWM_UCODE_TLV_CAPA_HOTSPOT_SUPPORT: supports Hot Spot Command 673 * @IWM_UCODE_TLV_CAPA_DC2DC_SUPPORT: supports DC2DC Command 674 * @IWM_UCODE_TLV_CAPA_2G_COEX_SUPPORT: supports 2G coex Command 675 * @IWM_UCODE_TLV_CAPA_CSUM_SUPPORT: supports TCP Checksum Offload 676 * @IWM_UCODE_TLV_CAPA_RADIO_BEACON_STATS: support radio and beacon statistics 677 * @IWM_UCODE_TLV_CAPA_P2P_STANDALONE_UAPSD: support p2p standalone U-APSD 678 * @IWM_UCODE_TLV_CAPA_BT_COEX_PLCR: enabled BT Coex packet level co-running 679 * @IWM_UCODE_TLV_CAPA_LAR_MULTI_MCC: ucode supports LAR updates with different 680 * sources for the MCC. This TLV bit is a future replacement to 681 * IWM_UCODE_TLV_API_WIFI_MCC_UPDATE. When either is set, multi-source LAR 682 * is supported. 683 * @IWM_UCODE_TLV_CAPA_BT_COEX_RRC: supports BT Coex RRC 684 * @IWM_UCODE_TLV_CAPA_GSCAN_SUPPORT: supports gscan 685 * @IWM_UCODE_TLV_CAPA_NAN_SUPPORT: supports NAN 686 * @IWM_UCODE_TLV_CAPA_UMAC_UPLOAD: supports upload mode in umac (1=supported, 687 * 0=no support) 688 * @IWM_UCODE_TLV_CAPA_EXTENDED_DTS_MEASURE: extended DTS measurement 689 * @IWM_UCODE_TLV_CAPA_SHORT_PM_TIMEOUTS: supports short PM timeouts 690 * @IWM_UCODE_TLV_CAPA_BT_MPLUT_SUPPORT: supports bt-coex Multi-priority LUT 691 * @IWM_UCODE_TLV_CAPA_BEACON_ANT_SELECTION: firmware will decide on what 692 * antenna the beacon should be transmitted 693 * @IWM_UCODE_TLV_CAPA_BEACON_STORING: firmware will store the latest beacon 694 * from AP and will send it upon d0i3 exit. 695 * @IWM_UCODE_TLV_CAPA_LAR_SUPPORT_V2: support LAR API V2 696 * @IWM_UCODE_TLV_CAPA_CT_KILL_BY_FW: firmware responsible for CT-kill 697 * @IWM_UCODE_TLV_CAPA_TEMP_THS_REPORT_SUPPORT: supports temperature 698 * thresholds reporting 699 * @IWM_UCODE_TLV_CAPA_CTDP_SUPPORT: supports cTDP command 700 * @IWM_UCODE_TLV_CAPA_USNIFFER_UNIFIED: supports usniffer enabled in 701 * regular image. 702 * @IWM_UCODE_TLV_CAPA_EXTEND_SHARED_MEM_CFG: support getting more shared 703 * memory addresses from the firmware. 704 * @IWM_UCODE_TLV_CAPA_LQM_SUPPORT: supports Link Quality Measurement 705 * @IWM_UCODE_TLV_CAPA_TX_POWER_ACK: reduced TX power API has larger 706 * command size (command version 4) that supports toggling ACK TX 707 * power reduction. 708 * 709 * @IWM_NUM_UCODE_TLV_CAPA: number of bits used 710 */ 711 enum iwm_ucode_tlv_capa { 712 IWM_UCODE_TLV_CAPA_D0I3_SUPPORT = 0, 713 IWM_UCODE_TLV_CAPA_LAR_SUPPORT = 1, 714 IWM_UCODE_TLV_CAPA_UMAC_SCAN = 2, 715 IWM_UCODE_TLV_CAPA_BEAMFORMER = 3, 716 IWM_UCODE_TLV_CAPA_TOF_SUPPORT = 5, 717 IWM_UCODE_TLV_CAPA_TDLS_SUPPORT = 6, 718 IWM_UCODE_TLV_CAPA_TXPOWER_INSERTION_SUPPORT = 8, 719 IWM_UCODE_TLV_CAPA_DS_PARAM_SET_IE_SUPPORT = 9, 720 IWM_UCODE_TLV_CAPA_WFA_TPC_REP_IE_SUPPORT = 10, 721 IWM_UCODE_TLV_CAPA_QUIET_PERIOD_SUPPORT = 11, 722 IWM_UCODE_TLV_CAPA_DQA_SUPPORT = 12, 723 IWM_UCODE_TLV_CAPA_TDLS_CHANNEL_SWITCH = 13, 724 IWM_UCODE_TLV_CAPA_CNSLDTD_D3_D0_IMG = 17, 725 IWM_UCODE_TLV_CAPA_HOTSPOT_SUPPORT = 18, 726 IWM_UCODE_TLV_CAPA_DC2DC_CONFIG_SUPPORT = 19, 727 IWM_UCODE_TLV_CAPA_2G_COEX_SUPPORT = 20, 728 IWM_UCODE_TLV_CAPA_CSUM_SUPPORT = 21, 729 IWM_UCODE_TLV_CAPA_RADIO_BEACON_STATS = 22, 730 IWM_UCODE_TLV_CAPA_P2P_STANDALONE_UAPSD = 26, 731 IWM_UCODE_TLV_CAPA_BT_COEX_PLCR = 28, 732 IWM_UCODE_TLV_CAPA_LAR_MULTI_MCC = 29, 733 IWM_UCODE_TLV_CAPA_BT_COEX_RRC = 30, 734 IWM_UCODE_TLV_CAPA_GSCAN_SUPPORT = 31, 735 IWM_UCODE_TLV_CAPA_NAN_SUPPORT = 34, 736 IWM_UCODE_TLV_CAPA_UMAC_UPLOAD = 35, 737 IWM_UCODE_TLV_CAPA_EXTENDED_DTS_MEASURE = 64, 738 IWM_UCODE_TLV_CAPA_SHORT_PM_TIMEOUTS = 65, 739 IWM_UCODE_TLV_CAPA_BT_MPLUT_SUPPORT = 67, 740 IWM_UCODE_TLV_CAPA_MULTI_QUEUE_RX_SUPPORT = 68, 741 IWM_UCODE_TLV_CAPA_BEACON_ANT_SELECTION = 71, 742 IWM_UCODE_TLV_CAPA_BEACON_STORING = 72, 743 IWM_UCODE_TLV_CAPA_LAR_SUPPORT_V2 = 73, 744 IWM_UCODE_TLV_CAPA_CT_KILL_BY_FW = 74, 745 IWM_UCODE_TLV_CAPA_TEMP_THS_REPORT_SUPPORT = 75, 746 IWM_UCODE_TLV_CAPA_CTDP_SUPPORT = 76, 747 IWM_UCODE_TLV_CAPA_USNIFFER_UNIFIED = 77, 748 IWM_UCODE_TLV_CAPA_EXTEND_SHARED_MEM_CFG = 80, 749 IWM_UCODE_TLV_CAPA_LQM_SUPPORT = 81, 750 IWM_UCODE_TLV_CAPA_TX_POWER_ACK = 84, 751 752 IWM_NUM_UCODE_TLV_CAPA = 128 753 }; 754 755 /* The default calibrate table size if not specified by firmware file */ 756 #define IWM_DEFAULT_STANDARD_PHY_CALIBRATE_TBL_SIZE 18 757 #define IWM_MAX_STANDARD_PHY_CALIBRATE_TBL_SIZE 19 758 #define IWM_MAX_PHY_CALIBRATE_TBL_SIZE 253 759 760 /* The default max probe length if not specified by the firmware file */ 761 #define IWM_DEFAULT_MAX_PROBE_LENGTH 200 762 763 /* 764 * enumeration of ucode section. 765 * This enumeration is used directly for older firmware (before 16.0). 766 * For new firmware, there can be up to 4 sections (see below) but the 767 * first one packaged into the firmware file is the DATA section and 768 * some debugging code accesses that. 769 */ 770 enum iwm_ucode_sec { 771 IWM_UCODE_SECTION_DATA, 772 IWM_UCODE_SECTION_INST, 773 }; 774 /* 775 * For 16.0 uCode and above, there is no differentiation between sections, 776 * just an offset to the HW address. 777 */ 778 #define IWM_CPU1_CPU2_SEPARATOR_SECTION 0xFFFFCCCC 779 #define IWM_PAGING_SEPARATOR_SECTION 0xAAAABBBB 780 781 /* uCode version contains 4 values: Major/Minor/API/Serial */ 782 #define IWM_UCODE_MAJOR(ver) (((ver) & 0xFF000000) >> 24) 783 #define IWM_UCODE_MINOR(ver) (((ver) & 0x00FF0000) >> 16) 784 #define IWM_UCODE_API(ver) (((ver) & 0x0000FF00) >> 8) 785 #define IWM_UCODE_SERIAL(ver) ((ver) & 0x000000FF) 786 787 /* 788 * Calibration control struct. 789 * Sent as part of the phy configuration command. 790 * @flow_trigger: bitmap for which calibrations to perform according to 791 * flow triggers. 792 * @event_trigger: bitmap for which calibrations to perform according to 793 * event triggers. 794 */ 795 struct iwm_tlv_calib_ctrl { 796 uint32_t flow_trigger; 797 uint32_t event_trigger; 798 } __packed; 799 800 enum iwm_fw_phy_cfg { 801 IWM_FW_PHY_CFG_RADIO_TYPE_POS = 0, 802 IWM_FW_PHY_CFG_RADIO_TYPE = 0x3 << IWM_FW_PHY_CFG_RADIO_TYPE_POS, 803 IWM_FW_PHY_CFG_RADIO_STEP_POS = 2, 804 IWM_FW_PHY_CFG_RADIO_STEP = 0x3 << IWM_FW_PHY_CFG_RADIO_STEP_POS, 805 IWM_FW_PHY_CFG_RADIO_DASH_POS = 4, 806 IWM_FW_PHY_CFG_RADIO_DASH = 0x3 << IWM_FW_PHY_CFG_RADIO_DASH_POS, 807 IWM_FW_PHY_CFG_TX_CHAIN_POS = 16, 808 IWM_FW_PHY_CFG_TX_CHAIN = 0xf << IWM_FW_PHY_CFG_TX_CHAIN_POS, 809 IWM_FW_PHY_CFG_RX_CHAIN_POS = 20, 810 IWM_FW_PHY_CFG_RX_CHAIN = 0xf << IWM_FW_PHY_CFG_RX_CHAIN_POS, 811 }; 812 813 #define IWM_UCODE_MAX_CS 1 814 815 /** 816 * struct iwm_fw_cipher_scheme - a cipher scheme supported by FW. 817 * @cipher: a cipher suite selector 818 * @flags: cipher scheme flags (currently reserved for a future use) 819 * @hdr_len: a size of MPDU security header 820 * @pn_len: a size of PN 821 * @pn_off: an offset of pn from the beginning of the security header 822 * @key_idx_off: an offset of key index byte in the security header 823 * @key_idx_mask: a bit mask of key_idx bits 824 * @key_idx_shift: bit shift needed to get key_idx 825 * @mic_len: mic length in bytes 826 * @hw_cipher: a HW cipher index used in host commands 827 */ 828 struct iwm_fw_cipher_scheme { 829 uint32_t cipher; 830 uint8_t flags; 831 uint8_t hdr_len; 832 uint8_t pn_len; 833 uint8_t pn_off; 834 uint8_t key_idx_off; 835 uint8_t key_idx_mask; 836 uint8_t key_idx_shift; 837 uint8_t mic_len; 838 uint8_t hw_cipher; 839 } __packed; 840 841 /** 842 * struct iwm_fw_cscheme_list - a cipher scheme list 843 * @size: a number of entries 844 * @cs: cipher scheme entries 845 */ 846 struct iwm_fw_cscheme_list { 847 uint8_t size; 848 struct iwm_fw_cipher_scheme cs[]; 849 } __packed; 850 851 /* 852 * END iwl-fw.h 853 */ 854 855 /* 856 * BEGIN iwl-fw-file.h 857 */ 858 859 /* v1/v2 uCode file layout */ 860 struct iwm_ucode_header { 861 uint32_t ver; /* major/minor/API/serial */ 862 union { 863 struct { 864 uint32_t inst_size; /* bytes of runtime code */ 865 uint32_t data_size; /* bytes of runtime data */ 866 uint32_t init_size; /* bytes of init code */ 867 uint32_t init_data_size; /* bytes of init data */ 868 uint32_t boot_size; /* bytes of bootstrap code */ 869 uint8_t data[0]; /* in same order as sizes */ 870 } v1; 871 struct { 872 uint32_t build; /* build number */ 873 uint32_t inst_size; /* bytes of runtime code */ 874 uint32_t data_size; /* bytes of runtime data */ 875 uint32_t init_size; /* bytes of init code */ 876 uint32_t init_data_size; /* bytes of init data */ 877 uint32_t boot_size; /* bytes of bootstrap code */ 878 uint8_t data[0]; /* in same order as sizes */ 879 } v2; 880 } u; 881 }; 882 883 /* 884 * new TLV uCode file layout 885 * 886 * The new TLV file format contains TLVs, that each specify 887 * some piece of data. 888 */ 889 890 enum iwm_ucode_tlv_type { 891 IWM_UCODE_TLV_INVALID = 0, /* unused */ 892 IWM_UCODE_TLV_INST = 1, 893 IWM_UCODE_TLV_DATA = 2, 894 IWM_UCODE_TLV_INIT = 3, 895 IWM_UCODE_TLV_INIT_DATA = 4, 896 IWM_UCODE_TLV_BOOT = 5, 897 IWM_UCODE_TLV_PROBE_MAX_LEN = 6, /* a uint32_t value */ 898 IWM_UCODE_TLV_PAN = 7, 899 IWM_UCODE_TLV_RUNT_EVTLOG_PTR = 8, 900 IWM_UCODE_TLV_RUNT_EVTLOG_SIZE = 9, 901 IWM_UCODE_TLV_RUNT_ERRLOG_PTR = 10, 902 IWM_UCODE_TLV_INIT_EVTLOG_PTR = 11, 903 IWM_UCODE_TLV_INIT_EVTLOG_SIZE = 12, 904 IWM_UCODE_TLV_INIT_ERRLOG_PTR = 13, 905 IWM_UCODE_TLV_ENHANCE_SENS_TBL = 14, 906 IWM_UCODE_TLV_PHY_CALIBRATION_SIZE = 15, 907 IWM_UCODE_TLV_WOWLAN_INST = 16, 908 IWM_UCODE_TLV_WOWLAN_DATA = 17, 909 IWM_UCODE_TLV_FLAGS = 18, 910 IWM_UCODE_TLV_SEC_RT = 19, 911 IWM_UCODE_TLV_SEC_INIT = 20, 912 IWM_UCODE_TLV_SEC_WOWLAN = 21, 913 IWM_UCODE_TLV_DEF_CALIB = 22, 914 IWM_UCODE_TLV_PHY_SKU = 23, 915 IWM_UCODE_TLV_SECURE_SEC_RT = 24, 916 IWM_UCODE_TLV_SECURE_SEC_INIT = 25, 917 IWM_UCODE_TLV_SECURE_SEC_WOWLAN = 26, 918 IWM_UCODE_TLV_NUM_OF_CPU = 27, 919 IWM_UCODE_TLV_CSCHEME = 28, 920 921 /* 922 * Following two are not in our base tag, but allow 923 * handling ucode version 9. 924 */ 925 IWM_UCODE_TLV_API_CHANGES_SET = 29, 926 IWM_UCODE_TLV_ENABLED_CAPABILITIES = 30, 927 928 IWM_UCODE_TLV_N_SCAN_CHANNELS = 31, 929 IWM_UCODE_TLV_PAGING = 32, 930 IWM_UCODE_TLV_SEC_RT_USNIFFER = 34, 931 IWM_UCODE_TLV_SDIO_ADMA_ADDR = 35, 932 IWM_UCODE_TLV_FW_VERSION = 36, 933 IWM_UCODE_TLV_FW_DBG_DEST = 38, 934 IWM_UCODE_TLV_FW_DBG_CONF = 39, 935 IWM_UCODE_TLV_FW_DBG_TRIGGER = 40, 936 IWM_UCODE_TLV_FW_GSCAN_CAPA = 50, 937 IWM_UCODE_TLV_FW_MEM_SEG = 51, 938 }; 939 940 struct iwm_ucode_tlv { 941 uint32_t type; /* see above */ 942 uint32_t length; /* not including type/length fields */ 943 uint8_t data[0]; 944 }; 945 946 struct iwm_ucode_api { 947 uint32_t api_index; 948 uint32_t api_flags; 949 } __packed; 950 951 struct iwm_ucode_capa { 952 uint32_t api_index; 953 uint32_t api_capa; 954 } __packed; 955 956 #define IWM_TLV_UCODE_MAGIC 0x0a4c5749 957 958 struct iwm_tlv_ucode_header { 959 /* 960 * The TLV style ucode header is distinguished from 961 * the v1/v2 style header by first four bytes being 962 * zero, as such is an invalid combination of 963 * major/minor/API/serial versions. 964 */ 965 uint32_t zero; 966 uint32_t magic; 967 uint8_t human_readable[64]; 968 uint32_t ver; /* major/minor/API/serial */ 969 uint32_t build; 970 uint64_t ignore; 971 /* 972 * The data contained herein has a TLV layout, 973 * see above for the TLV header and types. 974 * Note that each TLV is padded to a length 975 * that is a multiple of 4 for alignment. 976 */ 977 uint8_t data[0]; 978 }; 979 980 /* 981 * END iwl-fw-file.h 982 */ 983 984 /* 985 * BEGIN iwl-prph.h 986 */ 987 988 /* 989 * Registers in this file are internal, not PCI bus memory mapped. 990 * Driver accesses these via IWM_HBUS_TARG_PRPH_* registers. 991 */ 992 #define IWM_PRPH_BASE (0x00000) 993 #define IWM_PRPH_END (0xFFFFF) 994 995 /* APMG (power management) constants */ 996 #define IWM_APMG_BASE (IWM_PRPH_BASE + 0x3000) 997 #define IWM_APMG_CLK_CTRL_REG (IWM_APMG_BASE + 0x0000) 998 #define IWM_APMG_CLK_EN_REG (IWM_APMG_BASE + 0x0004) 999 #define IWM_APMG_CLK_DIS_REG (IWM_APMG_BASE + 0x0008) 1000 #define IWM_APMG_PS_CTRL_REG (IWM_APMG_BASE + 0x000c) 1001 #define IWM_APMG_PCIDEV_STT_REG (IWM_APMG_BASE + 0x0010) 1002 #define IWM_APMG_RFKILL_REG (IWM_APMG_BASE + 0x0014) 1003 #define IWM_APMG_RTC_INT_STT_REG (IWM_APMG_BASE + 0x001c) 1004 #define IWM_APMG_RTC_INT_MSK_REG (IWM_APMG_BASE + 0x0020) 1005 #define IWM_APMG_DIGITAL_SVR_REG (IWM_APMG_BASE + 0x0058) 1006 #define IWM_APMG_ANALOG_SVR_REG (IWM_APMG_BASE + 0x006C) 1007 1008 #define IWM_APMS_CLK_VAL_MRB_FUNC_MODE (0x00000001) 1009 #define IWM_APMG_CLK_VAL_DMA_CLK_RQT (0x00000200) 1010 #define IWM_APMG_CLK_VAL_BSM_CLK_RQT (0x00000800) 1011 1012 #define IWM_APMG_PS_CTRL_EARLY_PWR_OFF_RESET_DIS (0x00400000) 1013 #define IWM_APMG_PS_CTRL_VAL_RESET_REQ (0x04000000) 1014 #define IWM_APMG_PS_CTRL_MSK_PWR_SRC (0x03000000) 1015 #define IWM_APMG_PS_CTRL_VAL_PWR_SRC_VMAIN (0x00000000) 1016 #define IWM_APMG_PS_CTRL_VAL_PWR_SRC_VAUX (0x02000000) 1017 #define IWM_APMG_SVR_VOLTAGE_CONFIG_BIT_MSK (0x000001E0) /* bit 8:5 */ 1018 #define IWM_APMG_SVR_DIGITAL_VOLTAGE_1_32 (0x00000060) 1019 1020 #define IWM_APMG_PCIDEV_STT_VAL_L1_ACT_DIS (0x00000800) 1021 1022 #define IWM_APMG_RTC_INT_STT_RFKILL (0x10000000) 1023 1024 /* Device system time */ 1025 #define IWM_DEVICE_SYSTEM_TIME_REG 0xA0206C 1026 1027 /* Device NMI register */ 1028 #define IWM_DEVICE_SET_NMI_REG 0x00a01c30 1029 #define IWM_DEVICE_SET_NMI_VAL_HW 0x01 1030 #define IWM_DEVICE_SET_NMI_VAL_DRV 0x80 1031 #define IWM_DEVICE_SET_NMI_8000_REG 0x00a01c24 1032 #define IWM_DEVICE_SET_NMI_8000_VAL 0x1000000 1033 1034 /* 1035 * Device reset for family 8000 1036 * write to bit 24 in order to reset the CPU 1037 */ 1038 #define IWM_RELEASE_CPU_RESET 0x300c 1039 #define IWM_RELEASE_CPU_RESET_BIT 0x1000000 1040 1041 1042 /***************************************************************************** 1043 * 7000/3000 series SHR DTS addresses * 1044 *****************************************************************************/ 1045 1046 #define IWM_SHR_MISC_WFM_DTS_EN (0x00a10024) 1047 #define IWM_DTSC_CFG_MODE (0x00a10604) 1048 #define IWM_DTSC_VREF_AVG (0x00a10648) 1049 #define IWM_DTSC_VREF5_AVG (0x00a1064c) 1050 #define IWM_DTSC_CFG_MODE_PERIODIC (0x2) 1051 #define IWM_DTSC_PTAT_AVG (0x00a10650) 1052 1053 1054 /** 1055 * Tx Scheduler 1056 * 1057 * The Tx Scheduler selects the next frame to be transmitted, choosing TFDs 1058 * (Transmit Frame Descriptors) from up to 16 circular Tx queues resident in 1059 * host DRAM. It steers each frame's Tx command (which contains the frame 1060 * data) into one of up to 7 prioritized Tx DMA FIFO channels within the 1061 * device. A queue maps to only one (selectable by driver) Tx DMA channel, 1062 * but one DMA channel may take input from several queues. 1063 * 1064 * Tx DMA FIFOs have dedicated purposes. 1065 * 1066 * For 5000 series and up, they are used differently 1067 * (cf. iwl5000_default_queue_to_tx_fifo in iwl-5000.c): 1068 * 1069 * 0 -- EDCA BK (background) frames, lowest priority 1070 * 1 -- EDCA BE (best effort) frames, normal priority 1071 * 2 -- EDCA VI (video) frames, higher priority 1072 * 3 -- EDCA VO (voice) and management frames, highest priority 1073 * 4 -- unused 1074 * 5 -- unused 1075 * 6 -- unused 1076 * 7 -- Commands 1077 * 1078 * Driver should normally map queues 0-6 to Tx DMA/FIFO channels 0-6. 1079 * In addition, driver can map the remaining queues to Tx DMA/FIFO 1080 * channels 0-3 to support 11n aggregation via EDCA DMA channels. 1081 * 1082 * The driver sets up each queue to work in one of two modes: 1083 * 1084 * 1) Scheduler-Ack, in which the scheduler automatically supports a 1085 * block-ack (BA) window of up to 64 TFDs. In this mode, each queue 1086 * contains TFDs for a unique combination of Recipient Address (RA) 1087 * and Traffic Identifier (TID), that is, traffic of a given 1088 * Quality-Of-Service (QOS) priority, destined for a single station. 1089 * 1090 * In scheduler-ack mode, the scheduler keeps track of the Tx status of 1091 * each frame within the BA window, including whether it's been transmitted, 1092 * and whether it's been acknowledged by the receiving station. The device 1093 * automatically processes block-acks received from the receiving STA, 1094 * and reschedules un-acked frames to be retransmitted (successful 1095 * Tx completion may end up being out-of-order). 1096 * 1097 * The driver must maintain the queue's Byte Count table in host DRAM 1098 * for this mode. 1099 * This mode does not support fragmentation. 1100 * 1101 * 2) FIFO (a.k.a. non-Scheduler-ACK), in which each TFD is processed in order. 1102 * The device may automatically retry Tx, but will retry only one frame 1103 * at a time, until receiving ACK from receiving station, or reaching 1104 * retry limit and giving up. 1105 * 1106 * The command queue (#4/#9) must use this mode! 1107 * This mode does not require use of the Byte Count table in host DRAM. 1108 * 1109 * Driver controls scheduler operation via 3 means: 1110 * 1) Scheduler registers 1111 * 2) Shared scheduler data base in internal SRAM 1112 * 3) Shared data in host DRAM 1113 * 1114 * Initialization: 1115 * 1116 * When loading, driver should allocate memory for: 1117 * 1) 16 TFD circular buffers, each with space for (typically) 256 TFDs. 1118 * 2) 16 Byte Count circular buffers in 16 KBytes contiguous memory 1119 * (1024 bytes for each queue). 1120 * 1121 * After receiving "Alive" response from uCode, driver must initialize 1122 * the scheduler (especially for queue #4/#9, the command queue, otherwise 1123 * the driver can't issue commands!): 1124 */ 1125 #define IWM_SCD_MEM_LOWER_BOUND (0x0000) 1126 1127 /** 1128 * Max Tx window size is the max number of contiguous TFDs that the scheduler 1129 * can keep track of at one time when creating block-ack chains of frames. 1130 * Note that "64" matches the number of ack bits in a block-ack packet. 1131 */ 1132 #define IWM_SCD_WIN_SIZE 64 1133 #define IWM_SCD_FRAME_LIMIT 64 1134 1135 #define IWM_SCD_TXFIFO_POS_TID (0) 1136 #define IWM_SCD_TXFIFO_POS_RA (4) 1137 #define IWM_SCD_QUEUE_RA_TID_MAP_RATID_MSK (0x01FF) 1138 1139 /* agn SCD */ 1140 #define IWM_SCD_QUEUE_STTS_REG_POS_TXF (0) 1141 #define IWM_SCD_QUEUE_STTS_REG_POS_ACTIVE (3) 1142 #define IWM_SCD_QUEUE_STTS_REG_POS_WSL (4) 1143 #define IWM_SCD_QUEUE_STTS_REG_POS_SCD_ACT_EN (19) 1144 #define IWM_SCD_QUEUE_STTS_REG_MSK (0x017F0000) 1145 1146 #define IWM_SCD_QUEUE_CTX_REG1_CREDIT_POS (8) 1147 #define IWM_SCD_QUEUE_CTX_REG1_CREDIT_MSK (0x00FFFF00) 1148 #define IWM_SCD_QUEUE_CTX_REG1_SUPER_CREDIT_POS (24) 1149 #define IWM_SCD_QUEUE_CTX_REG1_SUPER_CREDIT_MSK (0xFF000000) 1150 #define IWM_SCD_QUEUE_CTX_REG2_WIN_SIZE_POS (0) 1151 #define IWM_SCD_QUEUE_CTX_REG2_WIN_SIZE_MSK (0x0000007F) 1152 #define IWM_SCD_QUEUE_CTX_REG2_FRAME_LIMIT_POS (16) 1153 #define IWM_SCD_QUEUE_CTX_REG2_FRAME_LIMIT_MSK (0x007F0000) 1154 #define IWM_SCD_GP_CTRL_ENABLE_31_QUEUES (1 << 0) 1155 #define IWM_SCD_GP_CTRL_AUTO_ACTIVE_MODE (1 << 18) 1156 1157 /* Context Data */ 1158 #define IWM_SCD_CONTEXT_MEM_LOWER_BOUND (IWM_SCD_MEM_LOWER_BOUND + 0x600) 1159 #define IWM_SCD_CONTEXT_MEM_UPPER_BOUND (IWM_SCD_MEM_LOWER_BOUND + 0x6A0) 1160 1161 /* Tx status */ 1162 #define IWM_SCD_TX_STTS_MEM_LOWER_BOUND (IWM_SCD_MEM_LOWER_BOUND + 0x6A0) 1163 #define IWM_SCD_TX_STTS_MEM_UPPER_BOUND (IWM_SCD_MEM_LOWER_BOUND + 0x7E0) 1164 1165 /* Translation Data */ 1166 #define IWM_SCD_TRANS_TBL_MEM_LOWER_BOUND (IWM_SCD_MEM_LOWER_BOUND + 0x7E0) 1167 #define IWM_SCD_TRANS_TBL_MEM_UPPER_BOUND (IWM_SCD_MEM_LOWER_BOUND + 0x808) 1168 1169 #define IWM_SCD_CONTEXT_QUEUE_OFFSET(x)\ 1170 (IWM_SCD_CONTEXT_MEM_LOWER_BOUND + ((x) * 8)) 1171 1172 #define IWM_SCD_TX_STTS_QUEUE_OFFSET(x)\ 1173 (IWM_SCD_TX_STTS_MEM_LOWER_BOUND + ((x) * 16)) 1174 1175 #define IWM_SCD_TRANS_TBL_OFFSET_QUEUE(x) \ 1176 ((IWM_SCD_TRANS_TBL_MEM_LOWER_BOUND + ((x) * 2)) & 0xfffc) 1177 1178 #define IWM_SCD_BASE (IWM_PRPH_BASE + 0xa02c00) 1179 1180 #define IWM_SCD_SRAM_BASE_ADDR (IWM_SCD_BASE + 0x0) 1181 #define IWM_SCD_DRAM_BASE_ADDR (IWM_SCD_BASE + 0x8) 1182 #define IWM_SCD_AIT (IWM_SCD_BASE + 0x0c) 1183 #define IWM_SCD_TXFACT (IWM_SCD_BASE + 0x10) 1184 #define IWM_SCD_ACTIVE (IWM_SCD_BASE + 0x14) 1185 #define IWM_SCD_QUEUECHAIN_SEL (IWM_SCD_BASE + 0xe8) 1186 #define IWM_SCD_CHAINEXT_EN (IWM_SCD_BASE + 0x244) 1187 #define IWM_SCD_AGGR_SEL (IWM_SCD_BASE + 0x248) 1188 #define IWM_SCD_INTERRUPT_MASK (IWM_SCD_BASE + 0x108) 1189 #define IWM_SCD_GP_CTRL (IWM_SCD_BASE + 0x1a8) 1190 #define IWM_SCD_EN_CTRL (IWM_SCD_BASE + 0x254) 1191 1192 static inline unsigned int IWM_SCD_QUEUE_WRPTR(unsigned int chnl) 1193 { 1194 if (chnl < 20) 1195 return IWM_SCD_BASE + 0x18 + chnl * 4; 1196 return IWM_SCD_BASE + 0x284 + (chnl - 20) * 4; 1197 } 1198 1199 static inline unsigned int IWM_SCD_QUEUE_RDPTR(unsigned int chnl) 1200 { 1201 if (chnl < 20) 1202 return IWM_SCD_BASE + 0x68 + chnl * 4; 1203 return IWM_SCD_BASE + 0x2B4 + (chnl - 20) * 4; 1204 } 1205 1206 static inline unsigned int IWM_SCD_QUEUE_STATUS_BITS(unsigned int chnl) 1207 { 1208 if (chnl < 20) 1209 return IWM_SCD_BASE + 0x10c + chnl * 4; 1210 return IWM_SCD_BASE + 0x384 + (chnl - 20) * 4; 1211 } 1212 1213 /*********************** END TX SCHEDULER *************************************/ 1214 1215 /* Oscillator clock */ 1216 #define IWM_OSC_CLK (0xa04068) 1217 #define IWM_OSC_CLK_FORCE_CONTROL (0x8) 1218 1219 /* 1220 * END iwl-prph.h 1221 */ 1222 1223 /* 1224 * BEGIN iwl-fh.h 1225 */ 1226 1227 /****************************/ 1228 /* Flow Handler Definitions */ 1229 /****************************/ 1230 1231 /** 1232 * This I/O area is directly read/writable by driver (e.g. Linux uses writel()) 1233 * Addresses are offsets from device's PCI hardware base address. 1234 */ 1235 #define IWM_FH_MEM_LOWER_BOUND (0x1000) 1236 #define IWM_FH_MEM_UPPER_BOUND (0x2000) 1237 1238 /** 1239 * Keep-Warm (KW) buffer base address. 1240 * 1241 * Driver must allocate a 4KByte buffer that is for keeping the 1242 * host DRAM powered on (via dummy accesses to DRAM) to maintain low-latency 1243 * DRAM access when doing Txing or Rxing. The dummy accesses prevent host 1244 * from going into a power-savings mode that would cause higher DRAM latency, 1245 * and possible data over/under-runs, before all Tx/Rx is complete. 1246 * 1247 * Driver loads IWM_FH_KW_MEM_ADDR_REG with the physical address (bits 35:4) 1248 * of the buffer, which must be 4K aligned. Once this is set up, the device 1249 * automatically invokes keep-warm accesses when normal accesses might not 1250 * be sufficient to maintain fast DRAM response. 1251 * 1252 * Bit fields: 1253 * 31-0: Keep-warm buffer physical base address [35:4], must be 4K aligned 1254 */ 1255 #define IWM_FH_KW_MEM_ADDR_REG (IWM_FH_MEM_LOWER_BOUND + 0x97C) 1256 1257 1258 /** 1259 * TFD Circular Buffers Base (CBBC) addresses 1260 * 1261 * Device has 16 base pointer registers, one for each of 16 host-DRAM-resident 1262 * circular buffers (CBs/queues) containing Transmit Frame Descriptors (TFDs) 1263 * (see struct iwm_tfd_frame). These 16 pointer registers are offset by 0x04 1264 * bytes from one another. Each TFD circular buffer in DRAM must be 256-byte 1265 * aligned (address bits 0-7 must be 0). 1266 * Later devices have 20 (5000 series) or 30 (higher) queues, but the registers 1267 * for them are in different places. 1268 * 1269 * Bit fields in each pointer register: 1270 * 27-0: TFD CB physical base address [35:8], must be 256-byte aligned 1271 */ 1272 #define IWM_FH_MEM_CBBC_0_15_LOWER_BOUND (IWM_FH_MEM_LOWER_BOUND + 0x9D0) 1273 #define IWM_FH_MEM_CBBC_0_15_UPPER_BOUN (IWM_FH_MEM_LOWER_BOUND + 0xA10) 1274 #define IWM_FH_MEM_CBBC_16_19_LOWER_BOUND (IWM_FH_MEM_LOWER_BOUND + 0xBF0) 1275 #define IWM_FH_MEM_CBBC_16_19_UPPER_BOUND (IWM_FH_MEM_LOWER_BOUND + 0xC00) 1276 #define IWM_FH_MEM_CBBC_20_31_LOWER_BOUND (IWM_FH_MEM_LOWER_BOUND + 0xB20) 1277 #define IWM_FH_MEM_CBBC_20_31_UPPER_BOUND (IWM_FH_MEM_LOWER_BOUND + 0xB80) 1278 1279 /* Find TFD CB base pointer for given queue */ 1280 static inline unsigned int IWM_FH_MEM_CBBC_QUEUE(unsigned int chnl) 1281 { 1282 if (chnl < 16) 1283 return IWM_FH_MEM_CBBC_0_15_LOWER_BOUND + 4 * chnl; 1284 if (chnl < 20) 1285 return IWM_FH_MEM_CBBC_16_19_LOWER_BOUND + 4 * (chnl - 16); 1286 return IWM_FH_MEM_CBBC_20_31_LOWER_BOUND + 4 * (chnl - 20); 1287 } 1288 1289 1290 /** 1291 * Rx SRAM Control and Status Registers (RSCSR) 1292 * 1293 * These registers provide handshake between driver and device for the Rx queue 1294 * (this queue handles *all* command responses, notifications, Rx data, etc. 1295 * sent from uCode to host driver). Unlike Tx, there is only one Rx 1296 * queue, and only one Rx DMA/FIFO channel. Also unlike Tx, which can 1297 * concatenate up to 20 DRAM buffers to form a Tx frame, each Receive Buffer 1298 * Descriptor (RBD) points to only one Rx Buffer (RB); there is a 1:1 1299 * mapping between RBDs and RBs. 1300 * 1301 * Driver must allocate host DRAM memory for the following, and set the 1302 * physical address of each into device registers: 1303 * 1304 * 1) Receive Buffer Descriptor (RBD) circular buffer (CB), typically with 256 1305 * entries (although any power of 2, up to 4096, is selectable by driver). 1306 * Each entry (1 dword) points to a receive buffer (RB) of consistent size 1307 * (typically 4K, although 8K or 16K are also selectable by driver). 1308 * Driver sets up RB size and number of RBDs in the CB via Rx config 1309 * register IWM_FH_MEM_RCSR_CHNL0_CONFIG_REG. 1310 * 1311 * Bit fields within one RBD: 1312 * 27-0: Receive Buffer physical address bits [35:8], 256-byte aligned 1313 * 1314 * Driver sets physical address [35:8] of base of RBD circular buffer 1315 * into IWM_FH_RSCSR_CHNL0_RBDCB_BASE_REG [27:0]. 1316 * 1317 * 2) Rx status buffer, 8 bytes, in which uCode indicates which Rx Buffers 1318 * (RBs) have been filled, via a "write pointer", actually the index of 1319 * the RB's corresponding RBD within the circular buffer. Driver sets 1320 * physical address [35:4] into IWM_FH_RSCSR_CHNL0_STTS_WPTR_REG [31:0]. 1321 * 1322 * Bit fields in lower dword of Rx status buffer (upper dword not used 1323 * by driver: 1324 * 31-12: Not used by driver 1325 * 11- 0: Index of last filled Rx buffer descriptor 1326 * (device writes, driver reads this value) 1327 * 1328 * As the driver prepares Receive Buffers (RBs) for device to fill, driver must 1329 * enter pointers to these RBs into contiguous RBD circular buffer entries, 1330 * and update the device's "write" index register, 1331 * IWM_FH_RSCSR_CHNL0_RBDCB_WPTR_REG. 1332 * 1333 * This "write" index corresponds to the *next* RBD that the driver will make 1334 * available, i.e. one RBD past the tail of the ready-to-fill RBDs within 1335 * the circular buffer. This value should initially be 0 (before preparing any 1336 * RBs), should be 8 after preparing the first 8 RBs (for example), and must 1337 * wrap back to 0 at the end of the circular buffer (but don't wrap before 1338 * "read" index has advanced past 1! See below). 1339 * NOTE: DEVICE EXPECTS THE WRITE INDEX TO BE INCREMENTED IN MULTIPLES OF 8. 1340 * 1341 * As the device fills RBs (referenced from contiguous RBDs within the circular 1342 * buffer), it updates the Rx status buffer in host DRAM, 2) described above, 1343 * to tell the driver the index of the latest filled RBD. The driver must 1344 * read this "read" index from DRAM after receiving an Rx interrupt from device 1345 * 1346 * The driver must also internally keep track of a third index, which is the 1347 * next RBD to process. When receiving an Rx interrupt, driver should process 1348 * all filled but unprocessed RBs up to, but not including, the RB 1349 * corresponding to the "read" index. For example, if "read" index becomes "1", 1350 * driver may process the RB pointed to by RBD 0. Depending on volume of 1351 * traffic, there may be many RBs to process. 1352 * 1353 * If read index == write index, device thinks there is no room to put new data. 1354 * Due to this, the maximum number of filled RBs is 255, instead of 256. To 1355 * be safe, make sure that there is a gap of at least 2 RBDs between "write" 1356 * and "read" indexes; that is, make sure that there are no more than 254 1357 * buffers waiting to be filled. 1358 */ 1359 #define IWM_FH_MEM_RSCSR_LOWER_BOUND (IWM_FH_MEM_LOWER_BOUND + 0xBC0) 1360 #define IWM_FH_MEM_RSCSR_UPPER_BOUND (IWM_FH_MEM_LOWER_BOUND + 0xC00) 1361 #define IWM_FH_MEM_RSCSR_CHNL0 (IWM_FH_MEM_RSCSR_LOWER_BOUND) 1362 1363 /** 1364 * Physical base address of 8-byte Rx Status buffer. 1365 * Bit fields: 1366 * 31-0: Rx status buffer physical base address [35:4], must 16-byte aligned. 1367 */ 1368 #define IWM_FH_RSCSR_CHNL0_STTS_WPTR_REG (IWM_FH_MEM_RSCSR_CHNL0) 1369 1370 /** 1371 * Physical base address of Rx Buffer Descriptor Circular Buffer. 1372 * Bit fields: 1373 * 27-0: RBD CD physical base address [35:8], must be 256-byte aligned. 1374 */ 1375 #define IWM_FH_RSCSR_CHNL0_RBDCB_BASE_REG (IWM_FH_MEM_RSCSR_CHNL0 + 0x004) 1376 1377 /** 1378 * Rx write pointer (index, really!). 1379 * Bit fields: 1380 * 11-0: Index of driver's most recent prepared-to-be-filled RBD, + 1. 1381 * NOTE: For 256-entry circular buffer, use only bits [7:0]. 1382 */ 1383 #define IWM_FH_RSCSR_CHNL0_RBDCB_WPTR_REG (IWM_FH_MEM_RSCSR_CHNL0 + 0x008) 1384 #define IWM_FH_RSCSR_CHNL0_WPTR (IWM_FH_RSCSR_CHNL0_RBDCB_WPTR_REG) 1385 1386 #define IWM_FW_RSCSR_CHNL0_RXDCB_RDPTR_REG (IWM_FH_MEM_RSCSR_CHNL0 + 0x00c) 1387 #define IWM_FH_RSCSR_CHNL0_RDPTR IWM_FW_RSCSR_CHNL0_RXDCB_RDPTR_REG 1388 1389 /** 1390 * Rx Config/Status Registers (RCSR) 1391 * Rx Config Reg for channel 0 (only channel used) 1392 * 1393 * Driver must initialize IWM_FH_MEM_RCSR_CHNL0_CONFIG_REG as follows for 1394 * normal operation (see bit fields). 1395 * 1396 * Clearing IWM_FH_MEM_RCSR_CHNL0_CONFIG_REG to 0 turns off Rx DMA. 1397 * Driver should poll IWM_FH_MEM_RSSR_RX_STATUS_REG for 1398 * IWM_FH_RSSR_CHNL0_RX_STATUS_CHNL_IDLE (bit 24) before continuing. 1399 * 1400 * Bit fields: 1401 * 31-30: Rx DMA channel enable: '00' off/pause, '01' pause at end of frame, 1402 * '10' operate normally 1403 * 29-24: reserved 1404 * 23-20: # RBDs in circular buffer = 2^value; use "8" for 256 RBDs (normal), 1405 * min "5" for 32 RBDs, max "12" for 4096 RBDs. 1406 * 19-18: reserved 1407 * 17-16: size of each receive buffer; '00' 4K (normal), '01' 8K, 1408 * '10' 12K, '11' 16K. 1409 * 15-14: reserved 1410 * 13-12: IRQ destination; '00' none, '01' host driver (normal operation) 1411 * 11- 4: timeout for closing Rx buffer and interrupting host (units 32 usec) 1412 * typical value 0x10 (about 1/2 msec) 1413 * 3- 0: reserved 1414 */ 1415 #define IWM_FH_MEM_RCSR_LOWER_BOUND (IWM_FH_MEM_LOWER_BOUND + 0xC00) 1416 #define IWM_FH_MEM_RCSR_UPPER_BOUND (IWM_FH_MEM_LOWER_BOUND + 0xCC0) 1417 #define IWM_FH_MEM_RCSR_CHNL0 (IWM_FH_MEM_RCSR_LOWER_BOUND) 1418 1419 #define IWM_FH_MEM_RCSR_CHNL0_CONFIG_REG (IWM_FH_MEM_RCSR_CHNL0) 1420 #define IWM_FH_MEM_RCSR_CHNL0_RBDCB_WPTR (IWM_FH_MEM_RCSR_CHNL0 + 0x8) 1421 #define IWM_FH_MEM_RCSR_CHNL0_FLUSH_RB_REQ (IWM_FH_MEM_RCSR_CHNL0 + 0x10) 1422 1423 #define IWM_FH_RCSR_CHNL0_RX_CONFIG_RB_TIMEOUT_MSK (0x00000FF0) /* bits 4-11 */ 1424 #define IWM_FH_RCSR_CHNL0_RX_CONFIG_IRQ_DEST_MSK (0x00001000) /* bits 12 */ 1425 #define IWM_FH_RCSR_CHNL0_RX_CONFIG_SINGLE_FRAME_MSK (0x00008000) /* bit 15 */ 1426 #define IWM_FH_RCSR_CHNL0_RX_CONFIG_RB_SIZE_MSK (0x00030000) /* bits 16-17 */ 1427 #define IWM_FH_RCSR_CHNL0_RX_CONFIG_RBDBC_SIZE_MSK (0x00F00000) /* bits 20-23 */ 1428 #define IWM_FH_RCSR_CHNL0_RX_CONFIG_DMA_CHNL_EN_MSK (0xC0000000) /* bits 30-31*/ 1429 1430 #define IWM_FH_RCSR_RX_CONFIG_RBDCB_SIZE_POS (20) 1431 #define IWM_FH_RCSR_RX_CONFIG_REG_IRQ_RBTH_POS (4) 1432 #define IWM_RX_RB_TIMEOUT (0x11) 1433 1434 #define IWM_FH_RCSR_RX_CONFIG_CHNL_EN_PAUSE_VAL (0x00000000) 1435 #define IWM_FH_RCSR_RX_CONFIG_CHNL_EN_PAUSE_EOF_VAL (0x40000000) 1436 #define IWM_FH_RCSR_RX_CONFIG_CHNL_EN_ENABLE_VAL (0x80000000) 1437 1438 #define IWM_FH_RCSR_RX_CONFIG_REG_VAL_RB_SIZE_4K (0x00000000) 1439 #define IWM_FH_RCSR_RX_CONFIG_REG_VAL_RB_SIZE_8K (0x00010000) 1440 #define IWM_FH_RCSR_RX_CONFIG_REG_VAL_RB_SIZE_12K (0x00020000) 1441 #define IWM_FH_RCSR_RX_CONFIG_REG_VAL_RB_SIZE_16K (0x00030000) 1442 1443 #define IWM_FH_RCSR_CHNL0_RX_IGNORE_RXF_EMPTY (0x00000004) 1444 #define IWM_FH_RCSR_CHNL0_RX_CONFIG_IRQ_DEST_NO_INT_VAL (0x00000000) 1445 #define IWM_FH_RCSR_CHNL0_RX_CONFIG_IRQ_DEST_INT_HOST_VAL (0x00001000) 1446 1447 /** 1448 * Rx Shared Status Registers (RSSR) 1449 * 1450 * After stopping Rx DMA channel (writing 0 to 1451 * IWM_FH_MEM_RCSR_CHNL0_CONFIG_REG), driver must poll 1452 * IWM_FH_MEM_RSSR_RX_STATUS_REG until Rx channel is idle. 1453 * 1454 * Bit fields: 1455 * 24: 1 = Channel 0 is idle 1456 * 1457 * IWM_FH_MEM_RSSR_SHARED_CTRL_REG and IWM_FH_MEM_RSSR_RX_ENABLE_ERR_IRQ2DRV 1458 * contain default values that should not be altered by the driver. 1459 */ 1460 #define IWM_FH_MEM_RSSR_LOWER_BOUND (IWM_FH_MEM_LOWER_BOUND + 0xC40) 1461 #define IWM_FH_MEM_RSSR_UPPER_BOUND (IWM_FH_MEM_LOWER_BOUND + 0xD00) 1462 1463 #define IWM_FH_MEM_RSSR_SHARED_CTRL_REG (IWM_FH_MEM_RSSR_LOWER_BOUND) 1464 #define IWM_FH_MEM_RSSR_RX_STATUS_REG (IWM_FH_MEM_RSSR_LOWER_BOUND + 0x004) 1465 #define IWM_FH_MEM_RSSR_RX_ENABLE_ERR_IRQ2DRV\ 1466 (IWM_FH_MEM_RSSR_LOWER_BOUND + 0x008) 1467 1468 #define IWM_FH_RSSR_CHNL0_RX_STATUS_CHNL_IDLE (0x01000000) 1469 1470 #define IWM_FH_MEM_TFDIB_REG1_ADDR_BITSHIFT 28 1471 1472 /* TFDB Area - TFDs buffer table */ 1473 #define IWM_FH_MEM_TFDIB_DRAM_ADDR_LSB_MSK (0xFFFFFFFF) 1474 #define IWM_FH_TFDIB_LOWER_BOUND (IWM_FH_MEM_LOWER_BOUND + 0x900) 1475 #define IWM_FH_TFDIB_UPPER_BOUND (IWM_FH_MEM_LOWER_BOUND + 0x958) 1476 #define IWM_FH_TFDIB_CTRL0_REG(_chnl) (IWM_FH_TFDIB_LOWER_BOUND + 0x8 * (_chnl)) 1477 #define IWM_FH_TFDIB_CTRL1_REG(_chnl) (IWM_FH_TFDIB_LOWER_BOUND + 0x8 * (_chnl) + 0x4) 1478 1479 /** 1480 * Transmit DMA Channel Control/Status Registers (TCSR) 1481 * 1482 * Device has one configuration register for each of 8 Tx DMA/FIFO channels 1483 * supported in hardware (don't confuse these with the 16 Tx queues in DRAM, 1484 * which feed the DMA/FIFO channels); config regs are separated by 0x20 bytes. 1485 * 1486 * To use a Tx DMA channel, driver must initialize its 1487 * IWM_FH_TCSR_CHNL_TX_CONFIG_REG(chnl) with: 1488 * 1489 * IWM_FH_TCSR_TX_CONFIG_REG_VAL_DMA_CHNL_ENABLE | 1490 * IWM_FH_TCSR_TX_CONFIG_REG_VAL_DMA_CREDIT_ENABLE_VAL 1491 * 1492 * All other bits should be 0. 1493 * 1494 * Bit fields: 1495 * 31-30: Tx DMA channel enable: '00' off/pause, '01' pause at end of frame, 1496 * '10' operate normally 1497 * 29- 4: Reserved, set to "0" 1498 * 3: Enable internal DMA requests (1, normal operation), disable (0) 1499 * 2- 0: Reserved, set to "0" 1500 */ 1501 #define IWM_FH_TCSR_LOWER_BOUND (IWM_FH_MEM_LOWER_BOUND + 0xD00) 1502 #define IWM_FH_TCSR_UPPER_BOUND (IWM_FH_MEM_LOWER_BOUND + 0xE60) 1503 1504 /* Find Control/Status reg for given Tx DMA/FIFO channel */ 1505 #define IWM_FH_TCSR_CHNL_NUM (8) 1506 1507 /* TCSR: tx_config register values */ 1508 #define IWM_FH_TCSR_CHNL_TX_CONFIG_REG(_chnl) \ 1509 (IWM_FH_TCSR_LOWER_BOUND + 0x20 * (_chnl)) 1510 #define IWM_FH_TCSR_CHNL_TX_CREDIT_REG(_chnl) \ 1511 (IWM_FH_TCSR_LOWER_BOUND + 0x20 * (_chnl) + 0x4) 1512 #define IWM_FH_TCSR_CHNL_TX_BUF_STS_REG(_chnl) \ 1513 (IWM_FH_TCSR_LOWER_BOUND + 0x20 * (_chnl) + 0x8) 1514 1515 #define IWM_FH_TCSR_TX_CONFIG_REG_VAL_MSG_MODE_TXF (0x00000000) 1516 #define IWM_FH_TCSR_TX_CONFIG_REG_VAL_MSG_MODE_DRV (0x00000001) 1517 1518 #define IWM_FH_TCSR_TX_CONFIG_REG_VAL_DMA_CREDIT_DISABLE (0x00000000) 1519 #define IWM_FH_TCSR_TX_CONFIG_REG_VAL_DMA_CREDIT_ENABLE (0x00000008) 1520 1521 #define IWM_FH_TCSR_TX_CONFIG_REG_VAL_CIRQ_HOST_NOINT (0x00000000) 1522 #define IWM_FH_TCSR_TX_CONFIG_REG_VAL_CIRQ_HOST_ENDTFD (0x00100000) 1523 #define IWM_FH_TCSR_TX_CONFIG_REG_VAL_CIRQ_HOST_IFTFD (0x00200000) 1524 1525 #define IWM_FH_TCSR_TX_CONFIG_REG_VAL_CIRQ_RTC_NOINT (0x00000000) 1526 #define IWM_FH_TCSR_TX_CONFIG_REG_VAL_CIRQ_RTC_ENDTFD (0x00400000) 1527 #define IWM_FH_TCSR_TX_CONFIG_REG_VAL_CIRQ_RTC_IFTFD (0x00800000) 1528 1529 #define IWM_FH_TCSR_TX_CONFIG_REG_VAL_DMA_CHNL_PAUSE (0x00000000) 1530 #define IWM_FH_TCSR_TX_CONFIG_REG_VAL_DMA_CHNL_PAUSE_EOF (0x40000000) 1531 #define IWM_FH_TCSR_TX_CONFIG_REG_VAL_DMA_CHNL_ENABLE (0x80000000) 1532 1533 #define IWM_FH_TCSR_CHNL_TX_BUF_STS_REG_VAL_TFDB_EMPTY (0x00000000) 1534 #define IWM_FH_TCSR_CHNL_TX_BUF_STS_REG_VAL_TFDB_WAIT (0x00002000) 1535 #define IWM_FH_TCSR_CHNL_TX_BUF_STS_REG_VAL_TFDB_VALID (0x00000003) 1536 1537 #define IWM_FH_TCSR_CHNL_TX_BUF_STS_REG_POS_TB_NUM (20) 1538 #define IWM_FH_TCSR_CHNL_TX_BUF_STS_REG_POS_TB_IDX (12) 1539 1540 /** 1541 * Tx Shared Status Registers (TSSR) 1542 * 1543 * After stopping Tx DMA channel (writing 0 to 1544 * IWM_FH_TCSR_CHNL_TX_CONFIG_REG(chnl)), driver must poll 1545 * IWM_FH_TSSR_TX_STATUS_REG until selected Tx channel is idle 1546 * (channel's buffers empty | no pending requests). 1547 * 1548 * Bit fields: 1549 * 31-24: 1 = Channel buffers empty (channel 7:0) 1550 * 23-16: 1 = No pending requests (channel 7:0) 1551 */ 1552 #define IWM_FH_TSSR_LOWER_BOUND (IWM_FH_MEM_LOWER_BOUND + 0xEA0) 1553 #define IWM_FH_TSSR_UPPER_BOUND (IWM_FH_MEM_LOWER_BOUND + 0xEC0) 1554 1555 #define IWM_FH_TSSR_TX_STATUS_REG (IWM_FH_TSSR_LOWER_BOUND + 0x010) 1556 1557 /** 1558 * Bit fields for TSSR(Tx Shared Status & Control) error status register: 1559 * 31: Indicates an address error when accessed to internal memory 1560 * uCode/driver must write "1" in order to clear this flag 1561 * 30: Indicates that Host did not send the expected number of dwords to FH 1562 * uCode/driver must write "1" in order to clear this flag 1563 * 16-9:Each status bit is for one channel. Indicates that an (Error) ActDMA 1564 * command was received from the scheduler while the TRB was already full 1565 * with previous command 1566 * uCode/driver must write "1" in order to clear this flag 1567 * 7-0: Each status bit indicates a channel's TxCredit error. When an error 1568 * bit is set, it indicates that the FH has received a full indication 1569 * from the RTC TxFIFO and the current value of the TxCredit counter was 1570 * not equal to zero. This mean that the credit mechanism was not 1571 * synchronized to the TxFIFO status 1572 * uCode/driver must write "1" in order to clear this flag 1573 */ 1574 #define IWM_FH_TSSR_TX_ERROR_REG (IWM_FH_TSSR_LOWER_BOUND + 0x018) 1575 #define IWM_FH_TSSR_TX_MSG_CONFIG_REG (IWM_FH_TSSR_LOWER_BOUND + 0x008) 1576 1577 #define IWM_FH_TSSR_TX_STATUS_REG_MSK_CHNL_IDLE(_chnl) ((1 << (_chnl)) << 16) 1578 1579 /* Tx service channels */ 1580 #define IWM_FH_SRVC_CHNL (9) 1581 #define IWM_FH_SRVC_LOWER_BOUND (IWM_FH_MEM_LOWER_BOUND + 0x9C8) 1582 #define IWM_FH_SRVC_UPPER_BOUND (IWM_FH_MEM_LOWER_BOUND + 0x9D0) 1583 #define IWM_FH_SRVC_CHNL_SRAM_ADDR_REG(_chnl) \ 1584 (IWM_FH_SRVC_LOWER_BOUND + ((_chnl) - 9) * 0x4) 1585 1586 #define IWM_FH_TX_CHICKEN_BITS_REG (IWM_FH_MEM_LOWER_BOUND + 0xE98) 1587 #define IWM_FH_TX_TRB_REG(_chan) (IWM_FH_MEM_LOWER_BOUND + 0x958 + \ 1588 (_chan) * 4) 1589 1590 /* Instruct FH to increment the retry count of a packet when 1591 * it is brought from the memory to TX-FIFO 1592 */ 1593 #define IWM_FH_TX_CHICKEN_BITS_SCD_AUTO_RETRY_EN (0x00000002) 1594 1595 #define IWM_RX_QUEUE_SIZE 256 1596 #define IWM_RX_QUEUE_MASK 255 1597 #define IWM_RX_QUEUE_SIZE_LOG 8 1598 1599 /* 1600 * RX related structures and functions 1601 */ 1602 #define IWM_RX_FREE_BUFFERS 64 1603 #define IWM_RX_LOW_WATERMARK 8 1604 1605 /** 1606 * struct iwm_rb_status - reseve buffer status 1607 * host memory mapped FH registers 1608 * @closed_rb_num [0:11] - Indicates the index of the RB which was closed 1609 * @closed_fr_num [0:11] - Indicates the index of the RX Frame which was closed 1610 * @finished_rb_num [0:11] - Indicates the index of the current RB 1611 * in which the last frame was written to 1612 * @finished_fr_num [0:11] - Indicates the index of the RX Frame 1613 * which was transferred 1614 */ 1615 struct iwm_rb_status { 1616 uint16_t closed_rb_num; 1617 uint16_t closed_fr_num; 1618 uint16_t finished_rb_num; 1619 uint16_t finished_fr_nam; 1620 uint32_t unused; 1621 } __packed; 1622 1623 1624 #define IWM_TFD_QUEUE_SIZE_MAX (256) 1625 #define IWM_TFD_QUEUE_SIZE_BC_DUP (64) 1626 #define IWM_TFD_QUEUE_BC_SIZE (IWM_TFD_QUEUE_SIZE_MAX + \ 1627 IWM_TFD_QUEUE_SIZE_BC_DUP) 1628 #define IWM_TX_DMA_MASK DMA_BIT_MASK(36) 1629 #define IWM_NUM_OF_TBS 20 1630 1631 static inline uint8_t iwm_get_dma_hi_addr(bus_addr_t addr) 1632 { 1633 return (sizeof(addr) > sizeof(uint32_t) ? (addr >> 16) >> 16 : 0) & 0xF; 1634 } 1635 /** 1636 * struct iwm_tfd_tb transmit buffer descriptor within transmit frame descriptor 1637 * 1638 * This structure contains dma address and length of transmission address 1639 * 1640 * @lo: low [31:0] portion of the dma address of TX buffer 1641 * every even is unaligned on 16 bit boundary 1642 * @hi_n_len 0-3 [35:32] portion of dma 1643 * 4-15 length of the tx buffer 1644 */ 1645 struct iwm_tfd_tb { 1646 uint32_t lo; 1647 uint16_t hi_n_len; 1648 } __packed; 1649 1650 /** 1651 * struct iwm_tfd 1652 * 1653 * Transmit Frame Descriptor (TFD) 1654 * 1655 * @ __reserved1[3] reserved 1656 * @ num_tbs 0-4 number of active tbs 1657 * 5 reserved 1658 * 6-7 padding (not used) 1659 * @ tbs[20] transmit frame buffer descriptors 1660 * @ __pad padding 1661 * 1662 * Each Tx queue uses a circular buffer of 256 TFDs stored in host DRAM. 1663 * Both driver and device share these circular buffers, each of which must be 1664 * contiguous 256 TFDs x 128 bytes-per-TFD = 32 KBytes 1665 * 1666 * Driver must indicate the physical address of the base of each 1667 * circular buffer via the IWM_FH_MEM_CBBC_QUEUE registers. 1668 * 1669 * Each TFD contains pointer/size information for up to 20 data buffers 1670 * in host DRAM. These buffers collectively contain the (one) frame described 1671 * by the TFD. Each buffer must be a single contiguous block of memory within 1672 * itself, but buffers may be scattered in host DRAM. Each buffer has max size 1673 * of (4K - 4). The concatenates all of a TFD's buffers into a single 1674 * Tx frame, up to 8 KBytes in size. 1675 * 1676 * A maximum of 255 (not 256!) TFDs may be on a queue waiting for Tx. 1677 */ 1678 struct iwm_tfd { 1679 uint8_t __reserved1[3]; 1680 uint8_t num_tbs; 1681 struct iwm_tfd_tb tbs[IWM_NUM_OF_TBS]; 1682 uint32_t __pad; 1683 } __packed; 1684 1685 /* Keep Warm Size */ 1686 #define IWM_KW_SIZE 0x1000 /* 4k */ 1687 1688 /* Fixed (non-configurable) rx data from phy */ 1689 1690 /** 1691 * struct iwm_agn_schedq_bc_tbl scheduler byte count table 1692 * base physical address provided by IWM_SCD_DRAM_BASE_ADDR 1693 * @tfd_offset 0-12 - tx command byte count 1694 * 12-16 - station index 1695 */ 1696 struct iwm_agn_scd_bc_tbl { 1697 uint16_t tfd_offset[IWM_TFD_QUEUE_BC_SIZE]; 1698 } __packed; 1699 1700 /* 1701 * END iwl-fh.h 1702 */ 1703 1704 /* 1705 * BEGIN mvm/fw-api.h 1706 */ 1707 1708 /* Maximum number of Tx queues. */ 1709 #define IWM_MVM_MAX_QUEUES 31 1710 1711 /* Tx queue numbers */ 1712 enum { 1713 IWM_MVM_OFFCHANNEL_QUEUE = 8, 1714 IWM_MVM_CMD_QUEUE = 9, 1715 IWM_MVM_AUX_QUEUE = 15, 1716 }; 1717 1718 enum iwm_mvm_tx_fifo { 1719 IWM_MVM_TX_FIFO_BK = 0, 1720 IWM_MVM_TX_FIFO_BE, 1721 IWM_MVM_TX_FIFO_VI, 1722 IWM_MVM_TX_FIFO_VO, 1723 IWM_MVM_TX_FIFO_MCAST = 5, 1724 IWM_MVM_TX_FIFO_CMD = 7, 1725 }; 1726 1727 #define IWM_MVM_STATION_COUNT 16 1728 1729 /* commands */ 1730 enum { 1731 IWM_MVM_ALIVE = 0x1, 1732 IWM_REPLY_ERROR = 0x2, 1733 1734 IWM_INIT_COMPLETE_NOTIF = 0x4, 1735 1736 /* PHY context commands */ 1737 IWM_PHY_CONTEXT_CMD = 0x8, 1738 IWM_DBG_CFG = 0x9, 1739 1740 /* UMAC scan commands */ 1741 IWM_SCAN_ITERATION_COMPLETE_UMAC = 0xb5, 1742 IWM_SCAN_CFG_CMD = 0xc, 1743 IWM_SCAN_REQ_UMAC = 0xd, 1744 IWM_SCAN_ABORT_UMAC = 0xe, 1745 IWM_SCAN_COMPLETE_UMAC = 0xf, 1746 1747 /* station table */ 1748 IWM_ADD_STA_KEY = 0x17, 1749 IWM_ADD_STA = 0x18, 1750 IWM_REMOVE_STA = 0x19, 1751 1752 /* TX */ 1753 IWM_TX_CMD = 0x1c, 1754 IWM_TXPATH_FLUSH = 0x1e, 1755 IWM_MGMT_MCAST_KEY = 0x1f, 1756 1757 /* scheduler config */ 1758 IWM_SCD_QUEUE_CFG = 0x1d, 1759 1760 /* global key */ 1761 IWM_WEP_KEY = 0x20, 1762 1763 /* MAC and Binding commands */ 1764 IWM_MAC_CONTEXT_CMD = 0x28, 1765 IWM_TIME_EVENT_CMD = 0x29, /* both CMD and response */ 1766 IWM_TIME_EVENT_NOTIFICATION = 0x2a, 1767 IWM_BINDING_CONTEXT_CMD = 0x2b, 1768 IWM_TIME_QUOTA_CMD = 0x2c, 1769 IWM_NON_QOS_TX_COUNTER_CMD = 0x2d, 1770 1771 IWM_LQ_CMD = 0x4e, 1772 1773 /* paging block to FW cpu2 */ 1774 IWM_FW_PAGING_BLOCK_CMD = 0x4f, 1775 1776 /* Scan offload */ 1777 IWM_SCAN_OFFLOAD_REQUEST_CMD = 0x51, 1778 IWM_SCAN_OFFLOAD_ABORT_CMD = 0x52, 1779 IWM_HOT_SPOT_CMD = 0x53, 1780 IWM_SCAN_OFFLOAD_COMPLETE = 0x6d, 1781 IWM_SCAN_OFFLOAD_UPDATE_PROFILES_CMD = 0x6e, 1782 IWM_SCAN_OFFLOAD_CONFIG_CMD = 0x6f, 1783 IWM_MATCH_FOUND_NOTIFICATION = 0xd9, 1784 IWM_SCAN_ITERATION_COMPLETE = 0xe7, 1785 1786 /* Phy */ 1787 IWM_PHY_CONFIGURATION_CMD = 0x6a, 1788 IWM_CALIB_RES_NOTIF_PHY_DB = 0x6b, 1789 IWM_PHY_DB_CMD = 0x6c, 1790 1791 /* Power - legacy power table command */ 1792 IWM_POWER_TABLE_CMD = 0x77, 1793 IWM_PSM_UAPSD_AP_MISBEHAVING_NOTIFICATION = 0x78, 1794 IWM_LTR_CONFIG = 0xee, 1795 1796 /* Thermal Throttling*/ 1797 IWM_REPLY_THERMAL_MNG_BACKOFF = 0x7e, 1798 1799 /* NVM */ 1800 IWM_NVM_ACCESS_CMD = 0x88, 1801 1802 IWM_SET_CALIB_DEFAULT_CMD = 0x8e, 1803 1804 IWM_BEACON_NOTIFICATION = 0x90, 1805 IWM_BEACON_TEMPLATE_CMD = 0x91, 1806 IWM_TX_ANT_CONFIGURATION_CMD = 0x98, 1807 IWM_BT_CONFIG = 0x9b, 1808 IWM_STATISTICS_NOTIFICATION = 0x9d, 1809 IWM_REDUCE_TX_POWER_CMD = 0x9f, 1810 1811 /* RF-KILL commands and notifications */ 1812 IWM_CARD_STATE_CMD = 0xa0, 1813 IWM_CARD_STATE_NOTIFICATION = 0xa1, 1814 1815 IWM_MISSED_BEACONS_NOTIFICATION = 0xa2, 1816 1817 IWM_MFUART_LOAD_NOTIFICATION = 0xb1, 1818 1819 /* Power - new power table command */ 1820 IWM_MAC_PM_POWER_TABLE = 0xa9, 1821 1822 IWM_REPLY_RX_PHY_CMD = 0xc0, 1823 IWM_REPLY_RX_MPDU_CMD = 0xc1, 1824 IWM_BA_NOTIF = 0xc5, 1825 1826 /* Location Aware Regulatory */ 1827 IWM_MCC_UPDATE_CMD = 0xc8, 1828 IWM_MCC_CHUB_UPDATE_CMD = 0xc9, 1829 1830 /* BT Coex */ 1831 IWM_BT_COEX_PRIO_TABLE = 0xcc, 1832 IWM_BT_COEX_PROT_ENV = 0xcd, 1833 IWM_BT_PROFILE_NOTIFICATION = 0xce, 1834 IWM_BT_COEX_CI = 0x5d, 1835 1836 IWM_REPLY_SF_CFG_CMD = 0xd1, 1837 IWM_REPLY_BEACON_FILTERING_CMD = 0xd2, 1838 1839 /* DTS measurements */ 1840 IWM_CMD_DTS_MEASUREMENT_TRIGGER = 0xdc, 1841 IWM_DTS_MEASUREMENT_NOTIFICATION = 0xdd, 1842 1843 IWM_REPLY_DEBUG_CMD = 0xf0, 1844 IWM_DEBUG_LOG_MSG = 0xf7, 1845 1846 IWM_MCAST_FILTER_CMD = 0xd0, 1847 1848 /* D3 commands/notifications */ 1849 IWM_D3_CONFIG_CMD = 0xd3, 1850 IWM_PROT_OFFLOAD_CONFIG_CMD = 0xd4, 1851 IWM_OFFLOADS_QUERY_CMD = 0xd5, 1852 IWM_REMOTE_WAKE_CONFIG_CMD = 0xd6, 1853 1854 /* for WoWLAN in particular */ 1855 IWM_WOWLAN_PATTERNS = 0xe0, 1856 IWM_WOWLAN_CONFIGURATION = 0xe1, 1857 IWM_WOWLAN_TSC_RSC_PARAM = 0xe2, 1858 IWM_WOWLAN_TKIP_PARAM = 0xe3, 1859 IWM_WOWLAN_KEK_KCK_MATERIAL = 0xe4, 1860 IWM_WOWLAN_GET_STATUSES = 0xe5, 1861 IWM_WOWLAN_TX_POWER_PER_DB = 0xe6, 1862 1863 /* and for NetDetect */ 1864 IWM_NET_DETECT_CONFIG_CMD = 0x54, 1865 IWM_NET_DETECT_PROFILES_QUERY_CMD = 0x56, 1866 IWM_NET_DETECT_PROFILES_CMD = 0x57, 1867 IWM_NET_DETECT_HOTSPOTS_CMD = 0x58, 1868 IWM_NET_DETECT_HOTSPOTS_QUERY_CMD = 0x59, 1869 }; 1870 1871 enum iwm_phy_ops_subcmd_ids { 1872 IWM_CMD_DTS_MEASUREMENT_TRIGGER_WIDE = 0x0, 1873 IWM_CTDP_CONFIG_CMD = 0x03, 1874 IWM_TEMP_REPORTING_THRESHOLDS_CMD = 0x04, 1875 IWM_CT_KILL_NOTIFICATION = 0xFE, 1876 IWM_DTS_MEASUREMENT_NOTIF_WIDE = 0xFF, 1877 }; 1878 1879 /* command groups */ 1880 enum { 1881 IWM_LEGACY_GROUP = 0x0, 1882 IWM_LONG_GROUP = 0x1, 1883 IWM_SYSTEM_GROUP = 0x2, 1884 IWM_MAC_CONF_GROUP = 0x3, 1885 IWM_PHY_OPS_GROUP = 0x4, 1886 IWM_DATA_PATH_GROUP = 0x5, 1887 IWM_PROT_OFFLOAD_GROUP = 0xb, 1888 }; 1889 1890 /** 1891 * struct iwm_cmd_response - generic response struct for most commands 1892 * @status: status of the command asked, changes for each one 1893 */ 1894 struct iwm_cmd_response { 1895 uint32_t status; 1896 }; 1897 1898 /* 1899 * struct iwm_tx_ant_cfg_cmd 1900 * @valid: valid antenna configuration 1901 */ 1902 struct iwm_tx_ant_cfg_cmd { 1903 uint32_t valid; 1904 } __packed; 1905 1906 /** 1907 * struct iwm_reduce_tx_power_cmd - TX power reduction command 1908 * IWM_REDUCE_TX_POWER_CMD = 0x9f 1909 * @flags: (reserved for future implementation) 1910 * @mac_context_id: id of the mac ctx for which we are reducing TX power. 1911 * @pwr_restriction: TX power restriction in dBms. 1912 */ 1913 struct iwm_reduce_tx_power_cmd { 1914 uint8_t flags; 1915 uint8_t mac_context_id; 1916 uint16_t pwr_restriction; 1917 } __packed; /* IWM_TX_REDUCED_POWER_API_S_VER_1 */ 1918 1919 enum iwm_dev_tx_power_cmd_mode { 1920 IWM_TX_POWER_MODE_SET_MAC = 0, 1921 IWM_TX_POWER_MODE_SET_DEVICE = 1, 1922 IWM_TX_POWER_MODE_SET_CHAINS = 2, 1923 IWM_TX_POWER_MODE_SET_ACK = 3, 1924 }; /* TX_POWER_REDUCED_FLAGS_TYPE_API_E_VER_4 */; 1925 1926 #define IWM_NUM_CHAIN_LIMITS 2 1927 #define IWM_NUM_SUB_BANDS 5 1928 1929 /** 1930 * struct iwm_dev_tx_power_cmd - TX power reduction command 1931 * @set_mode: see &enum iwl_dev_tx_power_cmd_mode 1932 * @mac_context_id: id of the mac ctx for which we are reducing TX power. 1933 * @pwr_restriction: TX power restriction in 1/8 dBms. 1934 * @dev_24: device TX power restriction in 1/8 dBms 1935 * @dev_52_low: device TX power restriction upper band - low 1936 * @dev_52_high: device TX power restriction upper band - high 1937 * @per_chain_restriction: per chain restrictions 1938 */ 1939 struct iwm_dev_tx_power_cmd_v3 { 1940 uint32_t set_mode; 1941 uint32_t mac_context_id; 1942 uint16_t pwr_restriction; 1943 uint16_t dev_24; 1944 uint16_t dev_52_low; 1945 uint16_t dev_52_high; 1946 uint16_t per_chain_restriction[IWM_NUM_CHAIN_LIMITS][IWM_NUM_SUB_BANDS]; 1947 } __packed; /* TX_REDUCED_POWER_API_S_VER_3 */ 1948 1949 #define IWM_DEV_MAX_TX_POWER 0x7FFF 1950 1951 /** 1952 * struct iwm_dev_tx_power_cmd - TX power reduction command 1953 * @v3: version 3 of the command, embedded here for easier software handling 1954 * @enable_ack_reduction: enable or disable close range ack TX power 1955 * reduction. 1956 */ 1957 struct iwm_dev_tx_power_cmd { 1958 /* v4 is just an extension of v3 - keep this here */ 1959 struct iwm_dev_tx_power_cmd_v3 v3; 1960 uint8_t enable_ack_reduction; 1961 uint8_t reserved[3]; 1962 } __packed; /* TX_REDUCED_POWER_API_S_VER_4 */ 1963 1964 /* 1965 * Calibration control struct. 1966 * Sent as part of the phy configuration command. 1967 * @flow_trigger: bitmap for which calibrations to perform according to 1968 * flow triggers. 1969 * @event_trigger: bitmap for which calibrations to perform according to 1970 * event triggers. 1971 */ 1972 struct iwm_calib_ctrl { 1973 uint32_t flow_trigger; 1974 uint32_t event_trigger; 1975 } __packed; 1976 1977 /* This enum defines the bitmap of various calibrations to enable in both 1978 * init ucode and runtime ucode through IWM_CALIBRATION_CFG_CMD. 1979 */ 1980 enum iwm_calib_cfg { 1981 IWM_CALIB_CFG_XTAL_IDX = (1 << 0), 1982 IWM_CALIB_CFG_TEMPERATURE_IDX = (1 << 1), 1983 IWM_CALIB_CFG_VOLTAGE_READ_IDX = (1 << 2), 1984 IWM_CALIB_CFG_PAPD_IDX = (1 << 3), 1985 IWM_CALIB_CFG_TX_PWR_IDX = (1 << 4), 1986 IWM_CALIB_CFG_DC_IDX = (1 << 5), 1987 IWM_CALIB_CFG_BB_FILTER_IDX = (1 << 6), 1988 IWM_CALIB_CFG_LO_LEAKAGE_IDX = (1 << 7), 1989 IWM_CALIB_CFG_TX_IQ_IDX = (1 << 8), 1990 IWM_CALIB_CFG_TX_IQ_SKEW_IDX = (1 << 9), 1991 IWM_CALIB_CFG_RX_IQ_IDX = (1 << 10), 1992 IWM_CALIB_CFG_RX_IQ_SKEW_IDX = (1 << 11), 1993 IWM_CALIB_CFG_SENSITIVITY_IDX = (1 << 12), 1994 IWM_CALIB_CFG_CHAIN_NOISE_IDX = (1 << 13), 1995 IWM_CALIB_CFG_DISCONNECTED_ANT_IDX = (1 << 14), 1996 IWM_CALIB_CFG_ANT_COUPLING_IDX = (1 << 15), 1997 IWM_CALIB_CFG_DAC_IDX = (1 << 16), 1998 IWM_CALIB_CFG_ABS_IDX = (1 << 17), 1999 IWM_CALIB_CFG_AGC_IDX = (1 << 18), 2000 }; 2001 2002 /* 2003 * Phy configuration command. 2004 */ 2005 struct iwm_phy_cfg_cmd { 2006 uint32_t phy_cfg; 2007 struct iwm_calib_ctrl calib_control; 2008 } __packed; 2009 2010 #define IWM_PHY_CFG_RADIO_TYPE ((1 << 0) | (1 << 1)) 2011 #define IWM_PHY_CFG_RADIO_STEP ((1 << 2) | (1 << 3)) 2012 #define IWM_PHY_CFG_RADIO_DASH ((1 << 4) | (1 << 5)) 2013 #define IWM_PHY_CFG_PRODUCT_NUMBER ((1 << 6) | (1 << 7)) 2014 #define IWM_PHY_CFG_TX_CHAIN_A (1 << 8) 2015 #define IWM_PHY_CFG_TX_CHAIN_B (1 << 9) 2016 #define IWM_PHY_CFG_TX_CHAIN_C (1 << 10) 2017 #define IWM_PHY_CFG_RX_CHAIN_A (1 << 12) 2018 #define IWM_PHY_CFG_RX_CHAIN_B (1 << 13) 2019 #define IWM_PHY_CFG_RX_CHAIN_C (1 << 14) 2020 2021 2022 /* Target of the IWM_NVM_ACCESS_CMD */ 2023 enum { 2024 IWM_NVM_ACCESS_TARGET_CACHE = 0, 2025 IWM_NVM_ACCESS_TARGET_OTP = 1, 2026 IWM_NVM_ACCESS_TARGET_EEPROM = 2, 2027 }; 2028 2029 /* Section types for IWM_NVM_ACCESS_CMD */ 2030 enum { 2031 IWM_NVM_SECTION_TYPE_SW = 1, 2032 IWM_NVM_SECTION_TYPE_REGULATORY = 3, 2033 IWM_NVM_SECTION_TYPE_CALIBRATION = 4, 2034 IWM_NVM_SECTION_TYPE_PRODUCTION = 5, 2035 IWM_NVM_SECTION_TYPE_REGULATORY_SDP = 8, 2036 IWM_NVM_SECTION_TYPE_MAC_OVERRIDE = 11, 2037 IWM_NVM_SECTION_TYPE_PHY_SKU = 12, 2038 IWM_NVM_MAX_NUM_SECTIONS = 13, 2039 }; 2040 2041 /** 2042 * struct iwm_nvm_access_cmd_ver2 - Request the device to send an NVM section 2043 * @op_code: 0 - read, 1 - write 2044 * @target: IWM_NVM_ACCESS_TARGET_* 2045 * @type: IWM_NVM_SECTION_TYPE_* 2046 * @offset: offset in bytes into the section 2047 * @length: in bytes, to read/write 2048 * @data: if write operation, the data to write. On read its empty 2049 */ 2050 struct iwm_nvm_access_cmd { 2051 uint8_t op_code; 2052 uint8_t target; 2053 uint16_t type; 2054 uint16_t offset; 2055 uint16_t length; 2056 uint8_t data[]; 2057 } __packed; /* IWM_NVM_ACCESS_CMD_API_S_VER_2 */ 2058 2059 #define IWM_NUM_OF_FW_PAGING_BLOCKS 33 /* 32 for data and 1 block for CSS */ 2060 2061 /* 2062 * struct iwm_fw_paging_cmd - paging layout 2063 * 2064 * (IWM_FW_PAGING_BLOCK_CMD = 0x4f) 2065 * 2066 * Send to FW the paging layout in the driver. 2067 * 2068 * @flags: various flags for the command 2069 * @block_size: the block size in powers of 2 2070 * @block_num: number of blocks specified in the command. 2071 * @device_phy_addr: virtual addresses from device side 2072 */ 2073 struct iwm_fw_paging_cmd { 2074 uint32_t flags; 2075 uint32_t block_size; 2076 uint32_t block_num; 2077 uint32_t device_phy_addr[IWM_NUM_OF_FW_PAGING_BLOCKS]; 2078 } __packed; /* IWM_FW_PAGING_BLOCK_CMD_API_S_VER_1 */ 2079 2080 /* 2081 * Fw items ID's 2082 * 2083 * @IWM_FW_ITEM_ID_PAGING: Address of the pages that the FW will upload 2084 * download 2085 */ 2086 enum iwm_fw_item_id { 2087 IWM_FW_ITEM_ID_PAGING = 3, 2088 }; 2089 2090 /* 2091 * struct iwm_fw_get_item_cmd - get an item from the fw 2092 */ 2093 struct iwm_fw_get_item_cmd { 2094 uint32_t item_id; 2095 } __packed; /* IWM_FW_GET_ITEM_CMD_API_S_VER_1 */ 2096 2097 /** 2098 * struct iwm_nvm_access_resp_ver2 - response to IWM_NVM_ACCESS_CMD 2099 * @offset: offset in bytes into the section 2100 * @length: in bytes, either how much was written or read 2101 * @type: IWM_NVM_SECTION_TYPE_* 2102 * @status: 0 for success, fail otherwise 2103 * @data: if read operation, the data returned. Empty on write. 2104 */ 2105 struct iwm_nvm_access_resp { 2106 uint16_t offset; 2107 uint16_t length; 2108 uint16_t type; 2109 uint16_t status; 2110 uint8_t data[]; 2111 } __packed; /* IWM_NVM_ACCESS_CMD_RESP_API_S_VER_2 */ 2112 2113 /* IWM_MVM_ALIVE 0x1 */ 2114 2115 /* alive response is_valid values */ 2116 #define IWM_ALIVE_RESP_UCODE_OK (1 << 0) 2117 #define IWM_ALIVE_RESP_RFKILL (1 << 1) 2118 2119 /* alive response ver_type values */ 2120 enum { 2121 IWM_FW_TYPE_HW = 0, 2122 IWM_FW_TYPE_PROT = 1, 2123 IWM_FW_TYPE_AP = 2, 2124 IWM_FW_TYPE_WOWLAN = 3, 2125 IWM_FW_TYPE_TIMING = 4, 2126 IWM_FW_TYPE_WIPAN = 5 2127 }; 2128 2129 /* alive response ver_subtype values */ 2130 enum { 2131 IWM_FW_SUBTYPE_FULL_FEATURE = 0, 2132 IWM_FW_SUBTYPE_BOOTSRAP = 1, /* Not valid */ 2133 IWM_FW_SUBTYPE_REDUCED = 2, 2134 IWM_FW_SUBTYPE_ALIVE_ONLY = 3, 2135 IWM_FW_SUBTYPE_WOWLAN = 4, 2136 IWM_FW_SUBTYPE_AP_SUBTYPE = 5, 2137 IWM_FW_SUBTYPE_WIPAN = 6, 2138 IWM_FW_SUBTYPE_INITIALIZE = 9 2139 }; 2140 2141 #define IWM_ALIVE_STATUS_ERR 0xDEAD 2142 #define IWM_ALIVE_STATUS_OK 0xCAFE 2143 2144 #define IWM_ALIVE_FLG_RFKILL (1 << 0) 2145 2146 struct iwm_lmac_alive { 2147 uint32_t ucode_major; 2148 uint32_t ucode_minor; 2149 uint8_t ver_subtype; 2150 uint8_t ver_type; 2151 uint8_t mac; 2152 uint8_t opt; 2153 uint32_t timestamp; 2154 uint32_t error_event_table_ptr; /* SRAM address for error log */ 2155 uint32_t log_event_table_ptr; /* SRAM address for LMAC event log */ 2156 uint32_t cpu_register_ptr; 2157 uint32_t dbgm_config_ptr; 2158 uint32_t alive_counter_ptr; 2159 uint32_t scd_base_ptr; /* SRAM address for SCD */ 2160 uint32_t st_fwrd_addr; /* pointer to Store and forward */ 2161 uint32_t st_fwrd_size; 2162 } __packed; /* UCODE_ALIVE_NTFY_API_S_VER_3 */ 2163 2164 struct iwm_umac_alive { 2165 uint32_t umac_major; /* UMAC version: major */ 2166 uint32_t umac_minor; /* UMAC version: minor */ 2167 uint32_t error_info_addr; /* SRAM address for UMAC error log */ 2168 uint32_t dbg_print_buff_addr; 2169 } __packed; /* UMAC_ALIVE_DATA_API_S_VER_2 */ 2170 2171 struct iwm_mvm_alive_resp_v3 { 2172 uint16_t status; 2173 uint16_t flags; 2174 struct iwm_lmac_alive lmac_data; 2175 struct iwm_umac_alive umac_data; 2176 } __packed; /* ALIVE_RES_API_S_VER_3 */ 2177 2178 struct iwm_mvm_alive_resp { 2179 uint16_t status; 2180 uint16_t flags; 2181 struct iwm_lmac_alive lmac_data[2]; 2182 struct iwm_umac_alive umac_data; 2183 } __packed; /* ALIVE_RES_API_S_VER_4 */ 2184 2185 /* Error response/notification */ 2186 enum { 2187 IWM_FW_ERR_UNKNOWN_CMD = 0x0, 2188 IWM_FW_ERR_INVALID_CMD_PARAM = 0x1, 2189 IWM_FW_ERR_SERVICE = 0x2, 2190 IWM_FW_ERR_ARC_MEMORY = 0x3, 2191 IWM_FW_ERR_ARC_CODE = 0x4, 2192 IWM_FW_ERR_WATCH_DOG = 0x5, 2193 IWM_FW_ERR_WEP_GRP_KEY_INDX = 0x10, 2194 IWM_FW_ERR_WEP_KEY_SIZE = 0x11, 2195 IWM_FW_ERR_OBSOLETE_FUNC = 0x12, 2196 IWM_FW_ERR_UNEXPECTED = 0xFE, 2197 IWM_FW_ERR_FATAL = 0xFF 2198 }; 2199 2200 /** 2201 * struct iwm_error_resp - FW error indication 2202 * ( IWM_REPLY_ERROR = 0x2 ) 2203 * @error_type: one of IWM_FW_ERR_* 2204 * @cmd_id: the command ID for which the error occurred 2205 * @bad_cmd_seq_num: sequence number of the erroneous command 2206 * @error_service: which service created the error, applicable only if 2207 * error_type = 2, otherwise 0 2208 * @timestamp: TSF in usecs. 2209 */ 2210 struct iwm_error_resp { 2211 uint32_t error_type; 2212 uint8_t cmd_id; 2213 uint8_t reserved1; 2214 uint16_t bad_cmd_seq_num; 2215 uint32_t error_service; 2216 uint64_t timestamp; 2217 } __packed; 2218 2219 2220 /* Common PHY, MAC and Bindings definitions */ 2221 2222 #define IWM_MAX_MACS_IN_BINDING (3) 2223 #define IWM_MAX_BINDINGS (4) 2224 #define IWM_AUX_BINDING_INDEX (3) 2225 #define IWM_MAX_PHYS (4) 2226 2227 /* Used to extract ID and color from the context dword */ 2228 #define IWM_FW_CTXT_ID_POS (0) 2229 #define IWM_FW_CTXT_ID_MSK (0xff << IWM_FW_CTXT_ID_POS) 2230 #define IWM_FW_CTXT_COLOR_POS (8) 2231 #define IWM_FW_CTXT_COLOR_MSK (0xff << IWM_FW_CTXT_COLOR_POS) 2232 #define IWM_FW_CTXT_INVALID (0xffffffff) 2233 2234 #define IWM_FW_CMD_ID_AND_COLOR(_id, _color) ((_id << IWM_FW_CTXT_ID_POS) |\ 2235 (_color << IWM_FW_CTXT_COLOR_POS)) 2236 2237 /* Possible actions on PHYs, MACs and Bindings */ 2238 enum { 2239 IWM_FW_CTXT_ACTION_STUB = 0, 2240 IWM_FW_CTXT_ACTION_ADD, 2241 IWM_FW_CTXT_ACTION_MODIFY, 2242 IWM_FW_CTXT_ACTION_REMOVE, 2243 IWM_FW_CTXT_ACTION_NUM 2244 }; /* COMMON_CONTEXT_ACTION_API_E_VER_1 */ 2245 2246 /* Time Events */ 2247 2248 /* Time Event types, according to MAC type */ 2249 enum iwm_time_event_type { 2250 /* BSS Station Events */ 2251 IWM_TE_BSS_STA_AGGRESSIVE_ASSOC, 2252 IWM_TE_BSS_STA_ASSOC, 2253 IWM_TE_BSS_EAP_DHCP_PROT, 2254 IWM_TE_BSS_QUIET_PERIOD, 2255 2256 /* P2P Device Events */ 2257 IWM_TE_P2P_DEVICE_DISCOVERABLE, 2258 IWM_TE_P2P_DEVICE_LISTEN, 2259 IWM_TE_P2P_DEVICE_ACTION_SCAN, 2260 IWM_TE_P2P_DEVICE_FULL_SCAN, 2261 2262 /* P2P Client Events */ 2263 IWM_TE_P2P_CLIENT_AGGRESSIVE_ASSOC, 2264 IWM_TE_P2P_CLIENT_ASSOC, 2265 IWM_TE_P2P_CLIENT_QUIET_PERIOD, 2266 2267 /* P2P GO Events */ 2268 IWM_TE_P2P_GO_ASSOC_PROT, 2269 IWM_TE_P2P_GO_REPETITIVE_NOA, 2270 IWM_TE_P2P_GO_CT_WINDOW, 2271 2272 /* WiDi Sync Events */ 2273 IWM_TE_WIDI_TX_SYNC, 2274 2275 IWM_TE_MAX 2276 }; /* IWM_MAC_EVENT_TYPE_API_E_VER_1 */ 2277 2278 2279 2280 /* Time event - defines for command API v1 */ 2281 2282 /* 2283 * @IWM_TE_V1_FRAG_NONE: fragmentation of the time event is NOT allowed. 2284 * @IWM_TE_V1_FRAG_SINGLE: fragmentation of the time event is allowed, but only 2285 * the first fragment is scheduled. 2286 * @IWM_TE_V1_FRAG_DUAL: fragmentation of the time event is allowed, but only 2287 * the first 2 fragments are scheduled. 2288 * @IWM_TE_V1_FRAG_ENDLESS: fragmentation of the time event is allowed, and any 2289 * number of fragments are valid. 2290 * 2291 * Other than the constant defined above, specifying a fragmentation value 'x' 2292 * means that the event can be fragmented but only the first 'x' will be 2293 * scheduled. 2294 */ 2295 enum { 2296 IWM_TE_V1_FRAG_NONE = 0, 2297 IWM_TE_V1_FRAG_SINGLE = 1, 2298 IWM_TE_V1_FRAG_DUAL = 2, 2299 IWM_TE_V1_FRAG_ENDLESS = 0xffffffff 2300 }; 2301 2302 /* If a Time Event can be fragmented, this is the max number of fragments */ 2303 #define IWM_TE_V1_FRAG_MAX_MSK 0x0fffffff 2304 /* Repeat the time event endlessly (until removed) */ 2305 #define IWM_TE_V1_REPEAT_ENDLESS 0xffffffff 2306 /* If a Time Event has bounded repetitions, this is the maximal value */ 2307 #define IWM_TE_V1_REPEAT_MAX_MSK_V1 0x0fffffff 2308 2309 /* Time Event dependencies: none, on another TE, or in a specific time */ 2310 enum { 2311 IWM_TE_V1_INDEPENDENT = 0, 2312 IWM_TE_V1_DEP_OTHER = (1 << 0), 2313 IWM_TE_V1_DEP_TSF = (1 << 1), 2314 IWM_TE_V1_EVENT_SOCIOPATHIC = (1 << 2), 2315 }; /* IWM_MAC_EVENT_DEPENDENCY_POLICY_API_E_VER_2 */ 2316 2317 /* 2318 * @IWM_TE_V1_NOTIF_NONE: no notifications 2319 * @IWM_TE_V1_NOTIF_HOST_EVENT_START: request/receive notification on event start 2320 * @IWM_TE_V1_NOTIF_HOST_EVENT_END:request/receive notification on event end 2321 * @IWM_TE_V1_NOTIF_INTERNAL_EVENT_START: internal FW use 2322 * @IWM_TE_V1_NOTIF_INTERNAL_EVENT_END: internal FW use. 2323 * @IWM_TE_V1_NOTIF_HOST_FRAG_START: request/receive notification on frag start 2324 * @IWM_TE_V1_NOTIF_HOST_FRAG_END:request/receive notification on frag end 2325 * @IWM_TE_V1_NOTIF_INTERNAL_FRAG_START: internal FW use. 2326 * @IWM_TE_V1_NOTIF_INTERNAL_FRAG_END: internal FW use. 2327 * 2328 * Supported Time event notifications configuration. 2329 * A notification (both event and fragment) includes a status indicating weather 2330 * the FW was able to schedule the event or not. For fragment start/end 2331 * notification the status is always success. There is no start/end fragment 2332 * notification for monolithic events. 2333 */ 2334 enum { 2335 IWM_TE_V1_NOTIF_NONE = 0, 2336 IWM_TE_V1_NOTIF_HOST_EVENT_START = (1 << 0), 2337 IWM_TE_V1_NOTIF_HOST_EVENT_END = (1 << 1), 2338 IWM_TE_V1_NOTIF_INTERNAL_EVENT_START = (1 << 2), 2339 IWM_TE_V1_NOTIF_INTERNAL_EVENT_END = (1 << 3), 2340 IWM_TE_V1_NOTIF_HOST_FRAG_START = (1 << 4), 2341 IWM_TE_V1_NOTIF_HOST_FRAG_END = (1 << 5), 2342 IWM_TE_V1_NOTIF_INTERNAL_FRAG_START = (1 << 6), 2343 IWM_TE_V1_NOTIF_INTERNAL_FRAG_END = (1 << 7), 2344 IWM_T2_V2_START_IMMEDIATELY = (1 << 11), 2345 }; /* IWM_MAC_EVENT_ACTION_API_E_VER_2 */ 2346 2347 /* Time event - defines for command API */ 2348 2349 /* 2350 * @IWM_TE_V2_FRAG_NONE: fragmentation of the time event is NOT allowed. 2351 * @IWM_TE_V2_FRAG_SINGLE: fragmentation of the time event is allowed, but only 2352 * the first fragment is scheduled. 2353 * @IWM_TE_V2_FRAG_DUAL: fragmentation of the time event is allowed, but only 2354 * the first 2 fragments are scheduled. 2355 * @IWM_TE_V2_FRAG_ENDLESS: fragmentation of the time event is allowed, and any 2356 * number of fragments are valid. 2357 * 2358 * Other than the constant defined above, specifying a fragmentation value 'x' 2359 * means that the event can be fragmented but only the first 'x' will be 2360 * scheduled. 2361 */ 2362 enum { 2363 IWM_TE_V2_FRAG_NONE = 0, 2364 IWM_TE_V2_FRAG_SINGLE = 1, 2365 IWM_TE_V2_FRAG_DUAL = 2, 2366 IWM_TE_V2_FRAG_MAX = 0xfe, 2367 IWM_TE_V2_FRAG_ENDLESS = 0xff 2368 }; 2369 2370 /* Repeat the time event endlessly (until removed) */ 2371 #define IWM_TE_V2_REPEAT_ENDLESS 0xff 2372 /* If a Time Event has bounded repetitions, this is the maximal value */ 2373 #define IWM_TE_V2_REPEAT_MAX 0xfe 2374 2375 #define IWM_TE_V2_PLACEMENT_POS 12 2376 #define IWM_TE_V2_ABSENCE_POS 15 2377 2378 /* Time event policy values 2379 * A notification (both event and fragment) includes a status indicating weather 2380 * the FW was able to schedule the event or not. For fragment start/end 2381 * notification the status is always success. There is no start/end fragment 2382 * notification for monolithic events. 2383 * 2384 * @IWM_TE_V2_DEFAULT_POLICY: independent, social, present, unoticable 2385 * @IWM_TE_V2_NOTIF_HOST_EVENT_START: request/receive notification on event start 2386 * @IWM_TE_V2_NOTIF_HOST_EVENT_END:request/receive notification on event end 2387 * @IWM_TE_V2_NOTIF_INTERNAL_EVENT_START: internal FW use 2388 * @IWM_TE_V2_NOTIF_INTERNAL_EVENT_END: internal FW use. 2389 * @IWM_TE_V2_NOTIF_HOST_FRAG_START: request/receive notification on frag start 2390 * @IWM_TE_V2_NOTIF_HOST_FRAG_END:request/receive notification on frag end 2391 * @IWM_TE_V2_NOTIF_INTERNAL_FRAG_START: internal FW use. 2392 * @IWM_TE_V2_NOTIF_INTERNAL_FRAG_END: internal FW use. 2393 * @IWM_TE_V2_DEP_OTHER: depends on another time event 2394 * @IWM_TE_V2_DEP_TSF: depends on a specific time 2395 * @IWM_TE_V2_EVENT_SOCIOPATHIC: can't co-exist with other events of tha same MAC 2396 * @IWM_TE_V2_ABSENCE: are we present or absent during the Time Event. 2397 */ 2398 enum { 2399 IWM_TE_V2_DEFAULT_POLICY = 0x0, 2400 2401 /* notifications (event start/stop, fragment start/stop) */ 2402 IWM_TE_V2_NOTIF_HOST_EVENT_START = (1 << 0), 2403 IWM_TE_V2_NOTIF_HOST_EVENT_END = (1 << 1), 2404 IWM_TE_V2_NOTIF_INTERNAL_EVENT_START = (1 << 2), 2405 IWM_TE_V2_NOTIF_INTERNAL_EVENT_END = (1 << 3), 2406 2407 IWM_TE_V2_NOTIF_HOST_FRAG_START = (1 << 4), 2408 IWM_TE_V2_NOTIF_HOST_FRAG_END = (1 << 5), 2409 IWM_TE_V2_NOTIF_INTERNAL_FRAG_START = (1 << 6), 2410 IWM_TE_V2_NOTIF_INTERNAL_FRAG_END = (1 << 7), 2411 2412 IWM_TE_V2_NOTIF_MSK = 0xff, 2413 2414 /* placement characteristics */ 2415 IWM_TE_V2_DEP_OTHER = (1 << IWM_TE_V2_PLACEMENT_POS), 2416 IWM_TE_V2_DEP_TSF = (1 << (IWM_TE_V2_PLACEMENT_POS + 1)), 2417 IWM_TE_V2_EVENT_SOCIOPATHIC = (1 << (IWM_TE_V2_PLACEMENT_POS + 2)), 2418 2419 /* are we present or absent during the Time Event. */ 2420 IWM_TE_V2_ABSENCE = (1 << IWM_TE_V2_ABSENCE_POS), 2421 }; 2422 2423 /** 2424 * struct iwm_time_event_cmd_api - configuring Time Events 2425 * with struct IWM_MAC_TIME_EVENT_DATA_API_S_VER_2 (see also 2426 * with version 1. determined by IWM_UCODE_TLV_FLAGS) 2427 * ( IWM_TIME_EVENT_CMD = 0x29 ) 2428 * @id_and_color: ID and color of the relevant MAC 2429 * @action: action to perform, one of IWM_FW_CTXT_ACTION_* 2430 * @id: this field has two meanings, depending on the action: 2431 * If the action is ADD, then it means the type of event to add. 2432 * For all other actions it is the unique event ID assigned when the 2433 * event was added by the FW. 2434 * @apply_time: When to start the Time Event (in GP2) 2435 * @max_delay: maximum delay to event's start (apply time), in TU 2436 * @depends_on: the unique ID of the event we depend on (if any) 2437 * @interval: interval between repetitions, in TU 2438 * @duration: duration of event in TU 2439 * @repeat: how many repetitions to do, can be IWM_TE_REPEAT_ENDLESS 2440 * @max_frags: maximal number of fragments the Time Event can be divided to 2441 * @policy: defines whether uCode shall notify the host or other uCode modules 2442 * on event and/or fragment start and/or end 2443 * using one of IWM_TE_INDEPENDENT, IWM_TE_DEP_OTHER, IWM_TE_DEP_TSF 2444 * IWM_TE_EVENT_SOCIOPATHIC 2445 * using IWM_TE_ABSENCE and using IWM_TE_NOTIF_* 2446 */ 2447 struct iwm_time_event_cmd { 2448 /* COMMON_INDEX_HDR_API_S_VER_1 */ 2449 uint32_t id_and_color; 2450 uint32_t action; 2451 uint32_t id; 2452 /* IWM_MAC_TIME_EVENT_DATA_API_S_VER_2 */ 2453 uint32_t apply_time; 2454 uint32_t max_delay; 2455 uint32_t depends_on; 2456 uint32_t interval; 2457 uint32_t duration; 2458 uint8_t repeat; 2459 uint8_t max_frags; 2460 uint16_t policy; 2461 } __packed; /* IWM_MAC_TIME_EVENT_CMD_API_S_VER_2 */ 2462 2463 /** 2464 * struct iwm_time_event_resp - response structure to iwm_time_event_cmd 2465 * @status: bit 0 indicates success, all others specify errors 2466 * @id: the Time Event type 2467 * @unique_id: the unique ID assigned (in ADD) or given (others) to the TE 2468 * @id_and_color: ID and color of the relevant MAC 2469 */ 2470 struct iwm_time_event_resp { 2471 uint32_t status; 2472 uint32_t id; 2473 uint32_t unique_id; 2474 uint32_t id_and_color; 2475 } __packed; /* IWM_MAC_TIME_EVENT_RSP_API_S_VER_1 */ 2476 2477 /** 2478 * struct iwm_time_event_notif - notifications of time event start/stop 2479 * ( IWM_TIME_EVENT_NOTIFICATION = 0x2a ) 2480 * @timestamp: action timestamp in GP2 2481 * @session_id: session's unique id 2482 * @unique_id: unique id of the Time Event itself 2483 * @id_and_color: ID and color of the relevant MAC 2484 * @action: one of IWM_TE_NOTIF_START or IWM_TE_NOTIF_END 2485 * @status: true if scheduled, false otherwise (not executed) 2486 */ 2487 struct iwm_time_event_notif { 2488 uint32_t timestamp; 2489 uint32_t session_id; 2490 uint32_t unique_id; 2491 uint32_t id_and_color; 2492 uint32_t action; 2493 uint32_t status; 2494 } __packed; /* IWM_MAC_TIME_EVENT_NTFY_API_S_VER_1 */ 2495 2496 2497 /* Bindings and Time Quota */ 2498 2499 /** 2500 * struct iwm_binding_cmd - configuring bindings 2501 * ( IWM_BINDING_CONTEXT_CMD = 0x2b ) 2502 * @id_and_color: ID and color of the relevant Binding 2503 * @action: action to perform, one of IWM_FW_CTXT_ACTION_* 2504 * @macs: array of MAC id and colors which belong to the binding 2505 * @phy: PHY id and color which belongs to the binding 2506 */ 2507 struct iwm_binding_cmd { 2508 /* COMMON_INDEX_HDR_API_S_VER_1 */ 2509 uint32_t id_and_color; 2510 uint32_t action; 2511 /* IWM_BINDING_DATA_API_S_VER_1 */ 2512 uint32_t macs[IWM_MAX_MACS_IN_BINDING]; 2513 uint32_t phy; 2514 } __packed; /* IWM_BINDING_CMD_API_S_VER_1 */ 2515 2516 /* The maximal number of fragments in the FW's schedule session */ 2517 #define IWM_MVM_MAX_QUOTA 128 2518 2519 /** 2520 * struct iwm_time_quota_data - configuration of time quota per binding 2521 * @id_and_color: ID and color of the relevant Binding 2522 * @quota: absolute time quota in TU. The scheduler will try to divide the 2523 * remainig quota (after Time Events) according to this quota. 2524 * @max_duration: max uninterrupted context duration in TU 2525 */ 2526 struct iwm_time_quota_data { 2527 uint32_t id_and_color; 2528 uint32_t quota; 2529 uint32_t max_duration; 2530 } __packed; /* IWM_TIME_QUOTA_DATA_API_S_VER_1 */ 2531 2532 /** 2533 * struct iwm_time_quota_cmd - configuration of time quota between bindings 2534 * ( IWM_TIME_QUOTA_CMD = 0x2c ) 2535 * @quotas: allocations per binding 2536 */ 2537 struct iwm_time_quota_cmd { 2538 struct iwm_time_quota_data quotas[IWM_MAX_BINDINGS]; 2539 } __packed; /* IWM_TIME_QUOTA_ALLOCATION_CMD_API_S_VER_1 */ 2540 2541 2542 /* PHY context */ 2543 2544 /* Supported bands */ 2545 #define IWM_PHY_BAND_5 (0) 2546 #define IWM_PHY_BAND_24 (1) 2547 2548 /* Supported channel width, vary if there is VHT support */ 2549 #define IWM_PHY_VHT_CHANNEL_MODE20 (0x0) 2550 #define IWM_PHY_VHT_CHANNEL_MODE40 (0x1) 2551 #define IWM_PHY_VHT_CHANNEL_MODE80 (0x2) 2552 #define IWM_PHY_VHT_CHANNEL_MODE160 (0x3) 2553 2554 /* 2555 * Control channel position: 2556 * For legacy set bit means upper channel, otherwise lower. 2557 * For VHT - bit-2 marks if the control is lower/upper relative to center-freq 2558 * bits-1:0 mark the distance from the center freq. for 20Mhz, offset is 0. 2559 * center_freq 2560 * | 2561 * 40Mhz |_______|_______| 2562 * 80Mhz |_______|_______|_______|_______| 2563 * 160Mhz |_______|_______|_______|_______|_______|_______|_______|_______| 2564 * code 011 010 001 000 | 100 101 110 111 2565 */ 2566 #define IWM_PHY_VHT_CTRL_POS_1_BELOW (0x0) 2567 #define IWM_PHY_VHT_CTRL_POS_2_BELOW (0x1) 2568 #define IWM_PHY_VHT_CTRL_POS_3_BELOW (0x2) 2569 #define IWM_PHY_VHT_CTRL_POS_4_BELOW (0x3) 2570 #define IWM_PHY_VHT_CTRL_POS_1_ABOVE (0x4) 2571 #define IWM_PHY_VHT_CTRL_POS_2_ABOVE (0x5) 2572 #define IWM_PHY_VHT_CTRL_POS_3_ABOVE (0x6) 2573 #define IWM_PHY_VHT_CTRL_POS_4_ABOVE (0x7) 2574 2575 /* 2576 * @band: IWM_PHY_BAND_* 2577 * @channel: channel number 2578 * @width: PHY_[VHT|LEGACY]_CHANNEL_* 2579 * @ctrl channel: PHY_[VHT|LEGACY]_CTRL_* 2580 */ 2581 struct iwm_fw_channel_info { 2582 uint8_t band; 2583 uint8_t channel; 2584 uint8_t width; 2585 uint8_t ctrl_pos; 2586 } __packed; 2587 2588 #define IWM_PHY_RX_CHAIN_DRIVER_FORCE_POS (0) 2589 #define IWM_PHY_RX_CHAIN_DRIVER_FORCE_MSK \ 2590 (0x1 << IWM_PHY_RX_CHAIN_DRIVER_FORCE_POS) 2591 #define IWM_PHY_RX_CHAIN_VALID_POS (1) 2592 #define IWM_PHY_RX_CHAIN_VALID_MSK \ 2593 (0x7 << IWM_PHY_RX_CHAIN_VALID_POS) 2594 #define IWM_PHY_RX_CHAIN_FORCE_SEL_POS (4) 2595 #define IWM_PHY_RX_CHAIN_FORCE_SEL_MSK \ 2596 (0x7 << IWM_PHY_RX_CHAIN_FORCE_SEL_POS) 2597 #define IWM_PHY_RX_CHAIN_FORCE_MIMO_SEL_POS (7) 2598 #define IWM_PHY_RX_CHAIN_FORCE_MIMO_SEL_MSK \ 2599 (0x7 << IWM_PHY_RX_CHAIN_FORCE_MIMO_SEL_POS) 2600 #define IWM_PHY_RX_CHAIN_CNT_POS (10) 2601 #define IWM_PHY_RX_CHAIN_CNT_MSK \ 2602 (0x3 << IWM_PHY_RX_CHAIN_CNT_POS) 2603 #define IWM_PHY_RX_CHAIN_MIMO_CNT_POS (12) 2604 #define IWM_PHY_RX_CHAIN_MIMO_CNT_MSK \ 2605 (0x3 << IWM_PHY_RX_CHAIN_MIMO_CNT_POS) 2606 #define IWM_PHY_RX_CHAIN_MIMO_FORCE_POS (14) 2607 #define IWM_PHY_RX_CHAIN_MIMO_FORCE_MSK \ 2608 (0x1 << IWM_PHY_RX_CHAIN_MIMO_FORCE_POS) 2609 2610 /* TODO: fix the value, make it depend on firmware at runtime? */ 2611 #define IWM_NUM_PHY_CTX 3 2612 2613 /* TODO: complete missing documentation */ 2614 /** 2615 * struct iwm_phy_context_cmd - config of the PHY context 2616 * ( IWM_PHY_CONTEXT_CMD = 0x8 ) 2617 * @id_and_color: ID and color of the relevant Binding 2618 * @action: action to perform, one of IWM_FW_CTXT_ACTION_* 2619 * @apply_time: 0 means immediate apply and context switch. 2620 * other value means apply new params after X usecs 2621 * @tx_param_color: ??? 2622 * @channel_info: 2623 * @txchain_info: ??? 2624 * @rxchain_info: ??? 2625 * @acquisition_data: ??? 2626 * @dsp_cfg_flags: set to 0 2627 */ 2628 struct iwm_phy_context_cmd { 2629 /* COMMON_INDEX_HDR_API_S_VER_1 */ 2630 uint32_t id_and_color; 2631 uint32_t action; 2632 /* IWM_PHY_CONTEXT_DATA_API_S_VER_1 */ 2633 uint32_t apply_time; 2634 uint32_t tx_param_color; 2635 struct iwm_fw_channel_info ci; 2636 uint32_t txchain_info; 2637 uint32_t rxchain_info; 2638 uint32_t acquisition_data; 2639 uint32_t dsp_cfg_flags; 2640 } __packed; /* IWM_PHY_CONTEXT_CMD_API_VER_1 */ 2641 2642 #define IWM_RX_INFO_PHY_CNT 8 2643 #define IWM_RX_INFO_ENERGY_ANT_ABC_IDX 1 2644 #define IWM_RX_INFO_ENERGY_ANT_A_MSK 0x000000ff 2645 #define IWM_RX_INFO_ENERGY_ANT_B_MSK 0x0000ff00 2646 #define IWM_RX_INFO_ENERGY_ANT_C_MSK 0x00ff0000 2647 #define IWM_RX_INFO_ENERGY_ANT_A_POS 0 2648 #define IWM_RX_INFO_ENERGY_ANT_B_POS 8 2649 #define IWM_RX_INFO_ENERGY_ANT_C_POS 16 2650 2651 #define IWM_RX_INFO_AGC_IDX 1 2652 #define IWM_RX_INFO_RSSI_AB_IDX 2 2653 #define IWM_OFDM_AGC_A_MSK 0x0000007f 2654 #define IWM_OFDM_AGC_A_POS 0 2655 #define IWM_OFDM_AGC_B_MSK 0x00003f80 2656 #define IWM_OFDM_AGC_B_POS 7 2657 #define IWM_OFDM_AGC_CODE_MSK 0x3fe00000 2658 #define IWM_OFDM_AGC_CODE_POS 20 2659 #define IWM_OFDM_RSSI_INBAND_A_MSK 0x00ff 2660 #define IWM_OFDM_RSSI_A_POS 0 2661 #define IWM_OFDM_RSSI_ALLBAND_A_MSK 0xff00 2662 #define IWM_OFDM_RSSI_ALLBAND_A_POS 8 2663 #define IWM_OFDM_RSSI_INBAND_B_MSK 0xff0000 2664 #define IWM_OFDM_RSSI_B_POS 16 2665 #define IWM_OFDM_RSSI_ALLBAND_B_MSK 0xff000000 2666 #define IWM_OFDM_RSSI_ALLBAND_B_POS 24 2667 2668 /** 2669 * struct iwm_rx_phy_info - phy info 2670 * (IWM_REPLY_RX_PHY_CMD = 0xc0) 2671 * @non_cfg_phy_cnt: non configurable DSP phy data byte count 2672 * @cfg_phy_cnt: configurable DSP phy data byte count 2673 * @stat_id: configurable DSP phy data set ID 2674 * @reserved1: 2675 * @system_timestamp: GP2 at on air rise 2676 * @timestamp: TSF at on air rise 2677 * @beacon_time_stamp: beacon at on-air rise 2678 * @phy_flags: general phy flags: band, modulation, ... 2679 * @channel: channel number 2680 * @non_cfg_phy_buf: for various implementations of non_cfg_phy 2681 * @rate_n_flags: IWM_RATE_MCS_* 2682 * @byte_count: frame's byte-count 2683 * @frame_time: frame's time on the air, based on byte count and frame rate 2684 * calculation 2685 * @mac_active_msk: what MACs were active when the frame was received 2686 * 2687 * Before each Rx, the device sends this data. It contains PHY information 2688 * about the reception of the packet. 2689 */ 2690 struct iwm_rx_phy_info { 2691 uint8_t non_cfg_phy_cnt; 2692 uint8_t cfg_phy_cnt; 2693 uint8_t stat_id; 2694 uint8_t reserved1; 2695 uint32_t system_timestamp; 2696 uint64_t timestamp; 2697 uint32_t beacon_time_stamp; 2698 uint16_t phy_flags; 2699 #define IWM_PHY_INFO_FLAG_SHPREAMBLE (1 << 2) 2700 uint16_t channel; 2701 uint32_t non_cfg_phy[IWM_RX_INFO_PHY_CNT]; 2702 uint8_t rate; 2703 uint8_t rflags; 2704 uint16_t xrflags; 2705 uint32_t byte_count; 2706 uint16_t mac_active_msk; 2707 uint16_t frame_time; 2708 } __packed; 2709 2710 struct iwm_rx_mpdu_res_start { 2711 uint16_t byte_count; 2712 uint16_t reserved; 2713 } __packed; 2714 2715 /** 2716 * enum iwm_rx_phy_flags - to parse %iwm_rx_phy_info phy_flags 2717 * @IWM_RX_RES_PHY_FLAGS_BAND_24: true if the packet was received on 2.4 band 2718 * @IWM_RX_RES_PHY_FLAGS_MOD_CCK: 2719 * @IWM_RX_RES_PHY_FLAGS_SHORT_PREAMBLE: true if packet's preamble was short 2720 * @IWM_RX_RES_PHY_FLAGS_NARROW_BAND: 2721 * @IWM_RX_RES_PHY_FLAGS_ANTENNA: antenna on which the packet was received 2722 * @IWM_RX_RES_PHY_FLAGS_AGG: set if the packet was part of an A-MPDU 2723 * @IWM_RX_RES_PHY_FLAGS_OFDM_HT: The frame was an HT frame 2724 * @IWM_RX_RES_PHY_FLAGS_OFDM_GF: The frame used GF preamble 2725 * @IWM_RX_RES_PHY_FLAGS_OFDM_VHT: The frame was a VHT frame 2726 */ 2727 enum iwm_rx_phy_flags { 2728 IWM_RX_RES_PHY_FLAGS_BAND_24 = (1 << 0), 2729 IWM_RX_RES_PHY_FLAGS_MOD_CCK = (1 << 1), 2730 IWM_RX_RES_PHY_FLAGS_SHORT_PREAMBLE = (1 << 2), 2731 IWM_RX_RES_PHY_FLAGS_NARROW_BAND = (1 << 3), 2732 IWM_RX_RES_PHY_FLAGS_ANTENNA = (0x7 << 4), 2733 IWM_RX_RES_PHY_FLAGS_ANTENNA_POS = 4, 2734 IWM_RX_RES_PHY_FLAGS_AGG = (1 << 7), 2735 IWM_RX_RES_PHY_FLAGS_OFDM_HT = (1 << 8), 2736 IWM_RX_RES_PHY_FLAGS_OFDM_GF = (1 << 9), 2737 IWM_RX_RES_PHY_FLAGS_OFDM_VHT = (1 << 10), 2738 }; 2739 2740 /** 2741 * enum iwm_mvm_rx_status - written by fw for each Rx packet 2742 * @IWM_RX_MPDU_RES_STATUS_CRC_OK: CRC is fine 2743 * @IWM_RX_MPDU_RES_STATUS_OVERRUN_OK: there was no RXE overflow 2744 * @IWM_RX_MPDU_RES_STATUS_SRC_STA_FOUND: 2745 * @IWM_RX_MPDU_RES_STATUS_KEY_VALID: 2746 * @IWM_RX_MPDU_RES_STATUS_KEY_PARAM_OK: 2747 * @IWM_RX_MPDU_RES_STATUS_ICV_OK: ICV is fine, if not, the packet is destroyed 2748 * @IWM_RX_MPDU_RES_STATUS_MIC_OK: used for CCM alg only. TKIP MIC is checked 2749 * in the driver. 2750 * @IWM_RX_MPDU_RES_STATUS_TTAK_OK: TTAK is fine 2751 * @IWM_RX_MPDU_RES_STATUS_MNG_FRAME_REPLAY_ERR: valid for alg = CCM_CMAC or 2752 * alg = CCM only. Checks replay attack for 11w frames. Relevant only if 2753 * %IWM_RX_MPDU_RES_STATUS_ROBUST_MNG_FRAME is set. 2754 * @IWM_RX_MPDU_RES_STATUS_SEC_NO_ENC: this frame is not encrypted 2755 * @IWM_RX_MPDU_RES_STATUS_SEC_WEP_ENC: this frame is encrypted using WEP 2756 * @IWM_RX_MPDU_RES_STATUS_SEC_CCM_ENC: this frame is encrypted using CCM 2757 * @IWM_RX_MPDU_RES_STATUS_SEC_TKIP_ENC: this frame is encrypted using TKIP 2758 * @IWM_RX_MPDU_RES_STATUS_SEC_CCM_CMAC_ENC: this frame is encrypted using CCM_CMAC 2759 * @IWM_RX_MPDU_RES_STATUS_SEC_ENC_ERR: this frame couldn't be decrypted 2760 * @IWM_RX_MPDU_RES_STATUS_SEC_ENC_MSK: bitmask of the encryption algorithm 2761 * @IWM_RX_MPDU_RES_STATUS_DEC_DONE: this frame has been successfully decrypted 2762 * @IWM_RX_MPDU_RES_STATUS_PROTECT_FRAME_BIT_CMP: 2763 * @IWM_RX_MPDU_RES_STATUS_EXT_IV_BIT_CMP: 2764 * @IWM_RX_MPDU_RES_STATUS_KEY_ID_CMP_BIT: 2765 * @IWM_RX_MPDU_RES_STATUS_ROBUST_MNG_FRAME: this frame is an 11w management frame 2766 * @IWM_RX_MPDU_RES_STATUS_HASH_INDEX_MSK: 2767 * @IWM_RX_MPDU_RES_STATUS_STA_ID_MSK: 2768 * @IWM_RX_MPDU_RES_STATUS_RRF_KILL: 2769 * @IWM_RX_MPDU_RES_STATUS_FILTERING_MSK: 2770 * @IWM_RX_MPDU_RES_STATUS2_FILTERING_MSK: 2771 */ 2772 enum iwm_mvm_rx_status { 2773 IWM_RX_MPDU_RES_STATUS_CRC_OK = (1 << 0), 2774 IWM_RX_MPDU_RES_STATUS_OVERRUN_OK = (1 << 1), 2775 IWM_RX_MPDU_RES_STATUS_SRC_STA_FOUND = (1 << 2), 2776 IWM_RX_MPDU_RES_STATUS_KEY_VALID = (1 << 3), 2777 IWM_RX_MPDU_RES_STATUS_KEY_PARAM_OK = (1 << 4), 2778 IWM_RX_MPDU_RES_STATUS_ICV_OK = (1 << 5), 2779 IWM_RX_MPDU_RES_STATUS_MIC_OK = (1 << 6), 2780 IWM_RX_MPDU_RES_STATUS_TTAK_OK = (1 << 7), 2781 IWM_RX_MPDU_RES_STATUS_MNG_FRAME_REPLAY_ERR = (1 << 7), 2782 IWM_RX_MPDU_RES_STATUS_SEC_NO_ENC = (0 << 8), 2783 IWM_RX_MPDU_RES_STATUS_SEC_WEP_ENC = (1 << 8), 2784 IWM_RX_MPDU_RES_STATUS_SEC_CCM_ENC = (2 << 8), 2785 IWM_RX_MPDU_RES_STATUS_SEC_TKIP_ENC = (3 << 8), 2786 IWM_RX_MPDU_RES_STATUS_SEC_EXT_ENC = (4 << 8), 2787 IWM_RX_MPDU_RES_STATUS_SEC_CCM_CMAC_ENC = (6 << 8), 2788 IWM_RX_MPDU_RES_STATUS_SEC_ENC_ERR = (7 << 8), 2789 IWM_RX_MPDU_RES_STATUS_SEC_ENC_MSK = (7 << 8), 2790 IWM_RX_MPDU_RES_STATUS_DEC_DONE = (1 << 11), 2791 IWM_RX_MPDU_RES_STATUS_PROTECT_FRAME_BIT_CMP = (1 << 12), 2792 IWM_RX_MPDU_RES_STATUS_EXT_IV_BIT_CMP = (1 << 13), 2793 IWM_RX_MPDU_RES_STATUS_KEY_ID_CMP_BIT = (1 << 14), 2794 IWM_RX_MPDU_RES_STATUS_ROBUST_MNG_FRAME = (1 << 15), 2795 IWM_RX_MPDU_RES_STATUS_HASH_INDEX_MSK = (0x3F0000), 2796 IWM_RX_MPDU_RES_STATUS_STA_ID_MSK = (0x1f000000), 2797 IWM_RX_MPDU_RES_STATUS_RRF_KILL = (1 << 29), 2798 IWM_RX_MPDU_RES_STATUS_FILTERING_MSK = (0xc00000), 2799 IWM_RX_MPDU_RES_STATUS2_FILTERING_MSK = (0xc0000000), 2800 }; 2801 2802 /** 2803 * struct iwm_radio_version_notif - information on the radio version 2804 * ( IWM_RADIO_VERSION_NOTIFICATION = 0x68 ) 2805 * @radio_flavor: 2806 * @radio_step: 2807 * @radio_dash: 2808 */ 2809 struct iwm_radio_version_notif { 2810 uint32_t radio_flavor; 2811 uint32_t radio_step; 2812 uint32_t radio_dash; 2813 } __packed; /* IWM_RADIO_VERSION_NOTOFICATION_S_VER_1 */ 2814 2815 enum iwm_card_state_flags { 2816 IWM_CARD_ENABLED = 0x00, 2817 IWM_HW_CARD_DISABLED = 0x01, 2818 IWM_SW_CARD_DISABLED = 0x02, 2819 IWM_CT_KILL_CARD_DISABLED = 0x04, 2820 IWM_HALT_CARD_DISABLED = 0x08, 2821 IWM_CARD_DISABLED_MSK = 0x0f, 2822 IWM_CARD_IS_RX_ON = 0x10, 2823 }; 2824 2825 /** 2826 * struct iwm_radio_version_notif - information on the radio version 2827 * (IWM_CARD_STATE_NOTIFICATION = 0xa1 ) 2828 * @flags: %iwm_card_state_flags 2829 */ 2830 struct iwm_card_state_notif { 2831 uint32_t flags; 2832 } __packed; /* CARD_STATE_NTFY_API_S_VER_1 */ 2833 2834 /** 2835 * struct iwm_missed_beacons_notif - information on missed beacons 2836 * ( IWM_MISSED_BEACONS_NOTIFICATION = 0xa2 ) 2837 * @mac_id: interface ID 2838 * @consec_missed_beacons_since_last_rx: number of consecutive missed 2839 * beacons since last RX. 2840 * @consec_missed_beacons: number of consecutive missed beacons 2841 * @num_expected_beacons: 2842 * @num_recvd_beacons: 2843 */ 2844 struct iwm_missed_beacons_notif { 2845 uint32_t mac_id; 2846 uint32_t consec_missed_beacons_since_last_rx; 2847 uint32_t consec_missed_beacons; 2848 uint32_t num_expected_beacons; 2849 uint32_t num_recvd_beacons; 2850 } __packed; /* IWM_MISSED_BEACON_NTFY_API_S_VER_3 */ 2851 2852 /** 2853 * struct iwm_mfuart_load_notif - mfuart image version & status 2854 * ( IWM_MFUART_LOAD_NOTIFICATION = 0xb1 ) 2855 * @installed_ver: installed image version 2856 * @external_ver: external image version 2857 * @status: MFUART loading status 2858 * @duration: MFUART loading time 2859 */ 2860 struct iwm_mfuart_load_notif { 2861 uint32_t installed_ver; 2862 uint32_t external_ver; 2863 uint32_t status; 2864 uint32_t duration; 2865 } __packed; /*MFU_LOADER_NTFY_API_S_VER_1*/ 2866 2867 /** 2868 * struct iwm_set_calib_default_cmd - set default value for calibration. 2869 * ( IWM_SET_CALIB_DEFAULT_CMD = 0x8e ) 2870 * @calib_index: the calibration to set value for 2871 * @length: of data 2872 * @data: the value to set for the calibration result 2873 */ 2874 struct iwm_set_calib_default_cmd { 2875 uint16_t calib_index; 2876 uint16_t length; 2877 uint8_t data[0]; 2878 } __packed; /* IWM_PHY_CALIB_OVERRIDE_VALUES_S */ 2879 2880 #define IWM_MAX_PORT_ID_NUM 2 2881 #define IWM_MAX_MCAST_FILTERING_ADDRESSES 256 2882 2883 /** 2884 * struct iwm_mcast_filter_cmd - configure multicast filter. 2885 * @filter_own: Set 1 to filter out multicast packets sent by station itself 2886 * @port_id: Multicast MAC addresses array specifier. This is a strange way 2887 * to identify network interface adopted in host-device IF. 2888 * It is used by FW as index in array of addresses. This array has 2889 * IWM_MAX_PORT_ID_NUM members. 2890 * @count: Number of MAC addresses in the array 2891 * @pass_all: Set 1 to pass all multicast packets. 2892 * @bssid: current association BSSID. 2893 * @addr_list: Place holder for array of MAC addresses. 2894 * IMPORTANT: add padding if necessary to ensure DWORD alignment. 2895 */ 2896 struct iwm_mcast_filter_cmd { 2897 uint8_t filter_own; 2898 uint8_t port_id; 2899 uint8_t count; 2900 uint8_t pass_all; 2901 uint8_t bssid[6]; 2902 uint8_t reserved[2]; 2903 uint8_t addr_list[0]; 2904 } __packed; /* IWM_MCAST_FILTERING_CMD_API_S_VER_1 */ 2905 2906 /* 2907 * The first MAC indices (starting from 0) 2908 * are available to the driver, AUX follows 2909 */ 2910 #define IWM_MAC_INDEX_AUX 4 2911 #define IWM_MAC_INDEX_MIN_DRIVER 0 2912 #define IWM_NUM_MAC_INDEX_DRIVER IWM_MAC_INDEX_AUX 2913 #define IWM_NUM_MAC_INDEX (IWM_MAC_INDEX_AUX + 1) 2914 2915 /*********************************** 2916 * Statistics API 2917 ***********************************/ 2918 struct iwm_mvm_statistics_dbg { 2919 uint32_t burst_check; 2920 uint32_t burst_count; 2921 uint32_t wait_for_silence_timeout_cnt; 2922 uint32_t reserved[3]; 2923 } __packed; /* IWM_STATISTICS_DEBUG_API_S_VER_2 */ 2924 2925 struct iwm_mvm_statistics_div { 2926 uint32_t tx_on_a; 2927 uint32_t tx_on_b; 2928 uint32_t exec_time; 2929 uint32_t probe_time; 2930 uint32_t rssi_ant; 2931 uint32_t reserved2; 2932 } __packed; /* IWM_STATISTICS_SLOW_DIV_API_S_VER_2 */ 2933 2934 struct iwm_mvm_statistics_rx_non_phy { 2935 uint32_t bogus_cts; /* CTS received when not expecting CTS */ 2936 uint32_t bogus_ack; /* ACK received when not expecting ACK */ 2937 uint32_t non_bssid_frames; /* number of frames with BSSID that 2938 * doesn't belong to the STA BSSID */ 2939 uint32_t filtered_frames; /* count frames that were dumped in the 2940 * filtering process */ 2941 uint32_t non_channel_beacons; /* beacons with our bss id but not on 2942 * our serving channel */ 2943 uint32_t channel_beacons; /* beacons with our bss id and in our 2944 * serving channel */ 2945 uint32_t num_missed_bcon; /* number of missed beacons */ 2946 uint32_t adc_rx_saturation_time; /* count in 0.8us units the time the 2947 * ADC was in saturation */ 2948 uint32_t ina_detection_search_time;/* total time (in 0.8us) searched 2949 * for INA */ 2950 uint32_t beacon_silence_rssi[3];/* RSSI silence after beacon frame */ 2951 uint32_t interference_data_flag; /* flag for interference data 2952 * availability. 1 when data is 2953 * available. */ 2954 uint32_t channel_load; /* counts RX Enable time in uSec */ 2955 uint32_t dsp_false_alarms; /* DSP false alarm (both OFDM 2956 * and CCK) counter */ 2957 uint32_t beacon_rssi_a; 2958 uint32_t beacon_rssi_b; 2959 uint32_t beacon_rssi_c; 2960 uint32_t beacon_energy_a; 2961 uint32_t beacon_energy_b; 2962 uint32_t beacon_energy_c; 2963 uint32_t num_bt_kills; 2964 uint32_t mac_id; 2965 uint32_t directed_data_mpdu; 2966 } __packed; /* IWM_STATISTICS_RX_NON_PHY_API_S_VER_3 */ 2967 2968 struct iwm_mvm_statistics_rx_phy { 2969 uint32_t ina_cnt; 2970 uint32_t fina_cnt; 2971 uint32_t plcp_err; 2972 uint32_t crc32_err; 2973 uint32_t overrun_err; 2974 uint32_t early_overrun_err; 2975 uint32_t crc32_good; 2976 uint32_t false_alarm_cnt; 2977 uint32_t fina_sync_err_cnt; 2978 uint32_t sfd_timeout; 2979 uint32_t fina_timeout; 2980 uint32_t unresponded_rts; 2981 uint32_t rxe_frame_limit_overrun; 2982 uint32_t sent_ack_cnt; 2983 uint32_t sent_cts_cnt; 2984 uint32_t sent_ba_rsp_cnt; 2985 uint32_t dsp_self_kill; 2986 uint32_t mh_format_err; 2987 uint32_t re_acq_main_rssi_sum; 2988 uint32_t reserved; 2989 } __packed; /* IWM_STATISTICS_RX_PHY_API_S_VER_2 */ 2990 2991 struct iwm_mvm_statistics_rx_ht_phy { 2992 uint32_t plcp_err; 2993 uint32_t overrun_err; 2994 uint32_t early_overrun_err; 2995 uint32_t crc32_good; 2996 uint32_t crc32_err; 2997 uint32_t mh_format_err; 2998 uint32_t agg_crc32_good; 2999 uint32_t agg_mpdu_cnt; 3000 uint32_t agg_cnt; 3001 uint32_t unsupport_mcs; 3002 } __packed; /* IWM_STATISTICS_HT_RX_PHY_API_S_VER_1 */ 3003 3004 struct iwm_mvm_statistics_tx_non_phy { 3005 uint32_t preamble_cnt; 3006 uint32_t rx_detected_cnt; 3007 uint32_t bt_prio_defer_cnt; 3008 uint32_t bt_prio_kill_cnt; 3009 uint32_t few_bytes_cnt; 3010 uint32_t cts_timeout; 3011 uint32_t ack_timeout; 3012 uint32_t expected_ack_cnt; 3013 uint32_t actual_ack_cnt; 3014 uint32_t dump_msdu_cnt; 3015 uint32_t burst_abort_next_frame_mismatch_cnt; 3016 uint32_t burst_abort_missing_next_frame_cnt; 3017 uint32_t cts_timeout_collision; 3018 uint32_t ack_or_ba_timeout_collision; 3019 } __packed; /* IWM_STATISTICS_TX_NON_PHY_API_S_VER_3 */ 3020 3021 #define IWM_MAX_CHAINS 3 3022 3023 struct iwm_mvm_statistics_tx_non_phy_agg { 3024 uint32_t ba_timeout; 3025 uint32_t ba_reschedule_frames; 3026 uint32_t scd_query_agg_frame_cnt; 3027 uint32_t scd_query_no_agg; 3028 uint32_t scd_query_agg; 3029 uint32_t scd_query_mismatch; 3030 uint32_t frame_not_ready; 3031 uint32_t underrun; 3032 uint32_t bt_prio_kill; 3033 uint32_t rx_ba_rsp_cnt; 3034 int8_t txpower[IWM_MAX_CHAINS]; 3035 int8_t reserved; 3036 uint32_t reserved2; 3037 } __packed; /* IWM_STATISTICS_TX_NON_PHY_AGG_API_S_VER_1 */ 3038 3039 struct iwm_mvm_statistics_tx_channel_width { 3040 uint32_t ext_cca_narrow_ch20[1]; 3041 uint32_t ext_cca_narrow_ch40[2]; 3042 uint32_t ext_cca_narrow_ch80[3]; 3043 uint32_t ext_cca_narrow_ch160[4]; 3044 uint32_t last_tx_ch_width_indx; 3045 uint32_t rx_detected_per_ch_width[4]; 3046 uint32_t success_per_ch_width[4]; 3047 uint32_t fail_per_ch_width[4]; 3048 }; /* IWM_STATISTICS_TX_CHANNEL_WIDTH_API_S_VER_1 */ 3049 3050 struct iwm_mvm_statistics_tx { 3051 struct iwm_mvm_statistics_tx_non_phy general; 3052 struct iwm_mvm_statistics_tx_non_phy_agg agg; 3053 struct iwm_mvm_statistics_tx_channel_width channel_width; 3054 } __packed; /* IWM_STATISTICS_TX_API_S_VER_4 */ 3055 3056 3057 struct iwm_mvm_statistics_bt_activity { 3058 uint32_t hi_priority_tx_req_cnt; 3059 uint32_t hi_priority_tx_denied_cnt; 3060 uint32_t lo_priority_tx_req_cnt; 3061 uint32_t lo_priority_tx_denied_cnt; 3062 uint32_t hi_priority_rx_req_cnt; 3063 uint32_t hi_priority_rx_denied_cnt; 3064 uint32_t lo_priority_rx_req_cnt; 3065 uint32_t lo_priority_rx_denied_cnt; 3066 } __packed; /* IWM_STATISTICS_BT_ACTIVITY_API_S_VER_1 */ 3067 3068 struct iwm_mvm_statistics_general_v8 { 3069 uint32_t radio_temperature; 3070 uint32_t radio_voltage; 3071 struct iwm_mvm_statistics_dbg dbg; 3072 uint32_t sleep_time; 3073 uint32_t slots_out; 3074 uint32_t slots_idle; 3075 uint32_t ttl_timestamp; 3076 struct iwm_mvm_statistics_div slow_div; 3077 uint32_t rx_enable_counter; 3078 /* 3079 * num_of_sos_states: 3080 * count the number of times we have to re-tune 3081 * in order to get out of bad PHY status 3082 */ 3083 uint32_t num_of_sos_states; 3084 uint32_t beacon_filtered; 3085 uint32_t missed_beacons; 3086 uint8_t beacon_filter_average_energy; 3087 uint8_t beacon_filter_reason; 3088 uint8_t beacon_filter_current_energy; 3089 uint8_t beacon_filter_reserved; 3090 uint32_t beacon_filter_delta_time; 3091 struct iwm_mvm_statistics_bt_activity bt_activity; 3092 uint64_t rx_time; 3093 uint64_t on_time_rf; 3094 uint64_t on_time_scan; 3095 uint64_t tx_time; 3096 uint32_t beacon_counter[IWM_NUM_MAC_INDEX]; 3097 uint8_t beacon_average_energy[IWM_NUM_MAC_INDEX]; 3098 uint8_t reserved[4 - (IWM_NUM_MAC_INDEX % 4)]; 3099 } __packed; /* IWM_STATISTICS_GENERAL_API_S_VER_8 */ 3100 3101 struct iwm_mvm_statistics_rx { 3102 struct iwm_mvm_statistics_rx_phy ofdm; 3103 struct iwm_mvm_statistics_rx_phy cck; 3104 struct iwm_mvm_statistics_rx_non_phy general; 3105 struct iwm_mvm_statistics_rx_ht_phy ofdm_ht; 3106 } __packed; /* IWM_STATISTICS_RX_API_S_VER_3 */ 3107 3108 /* 3109 * IWM_STATISTICS_NOTIFICATION = 0x9d (notification only, not a command) 3110 * 3111 * By default, uCode issues this notification after receiving a beacon 3112 * while associated. To disable this behavior, set DISABLE_NOTIF flag in the 3113 * IWM_STATISTICS_CMD (0x9c), below. 3114 */ 3115 3116 struct iwm_notif_statistics_v10 { 3117 uint32_t flag; 3118 struct iwm_mvm_statistics_rx rx; 3119 struct iwm_mvm_statistics_tx tx; 3120 struct iwm_mvm_statistics_general_v8 general; 3121 } __packed; /* IWM_STATISTICS_NTFY_API_S_VER_10 */ 3122 3123 #define IWM_STATISTICS_FLG_CLEAR 0x1 3124 #define IWM_STATISTICS_FLG_DISABLE_NOTIF 0x2 3125 3126 struct iwm_statistics_cmd { 3127 uint32_t flags; 3128 } __packed; /* IWM_STATISTICS_CMD_API_S_VER_1 */ 3129 3130 /*********************************** 3131 * Smart Fifo API 3132 ***********************************/ 3133 /* Smart Fifo state */ 3134 enum iwm_sf_state { 3135 IWM_SF_LONG_DELAY_ON = 0, /* should never be called by driver */ 3136 IWM_SF_FULL_ON, 3137 IWM_SF_UNINIT, 3138 IWM_SF_INIT_OFF, 3139 IWM_SF_HW_NUM_STATES 3140 }; 3141 3142 /* Smart Fifo possible scenario */ 3143 enum iwm_sf_scenario { 3144 IWM_SF_SCENARIO_SINGLE_UNICAST, 3145 IWM_SF_SCENARIO_AGG_UNICAST, 3146 IWM_SF_SCENARIO_MULTICAST, 3147 IWM_SF_SCENARIO_BA_RESP, 3148 IWM_SF_SCENARIO_TX_RESP, 3149 IWM_SF_NUM_SCENARIO 3150 }; 3151 3152 #define IWM_SF_TRANSIENT_STATES_NUMBER 2 /* IWM_SF_LONG_DELAY_ON and IWM_SF_FULL_ON */ 3153 #define IWM_SF_NUM_TIMEOUT_TYPES 2 /* Aging timer and Idle timer */ 3154 3155 /* smart FIFO default values */ 3156 #define IWM_SF_W_MARK_SISO 4096 3157 #define IWM_SF_W_MARK_MIMO2 8192 3158 #define IWM_SF_W_MARK_MIMO3 6144 3159 #define IWM_SF_W_MARK_LEGACY 4096 3160 #define IWM_SF_W_MARK_SCAN 4096 3161 3162 /* SF Scenarios timers for default configuration (aligned to 32 uSec) */ 3163 #define IWM_SF_SINGLE_UNICAST_IDLE_TIMER_DEF 160 /* 150 uSec */ 3164 #define IWM_SF_SINGLE_UNICAST_AGING_TIMER_DEF 400 /* 0.4 mSec */ 3165 #define IWM_SF_AGG_UNICAST_IDLE_TIMER_DEF 160 /* 150 uSec */ 3166 #define IWM_SF_AGG_UNICAST_AGING_TIMER_DEF 400 /* 0.4 mSec */ 3167 #define IWM_SF_MCAST_IDLE_TIMER_DEF 160 /* 150 uSec */ 3168 #define IWM_SF_MCAST_AGING_TIMER_DEF 400 /* 0.4 mSec */ 3169 #define IWM_SF_BA_IDLE_TIMER_DEF 160 /* 150 uSec */ 3170 #define IWM_SF_BA_AGING_TIMER_DEF 400 /* 0.4 mSec */ 3171 #define IWM_SF_TX_RE_IDLE_TIMER_DEF 160 /* 150 uSec */ 3172 #define IWM_SF_TX_RE_AGING_TIMER_DEF 400 /* 0.4 mSec */ 3173 3174 /* SF Scenarios timers for FULL_ON state (aligned to 32 uSec) */ 3175 #define IWM_SF_SINGLE_UNICAST_IDLE_TIMER 320 /* 300 uSec */ 3176 #define IWM_SF_SINGLE_UNICAST_AGING_TIMER 2016 /* 2 mSec */ 3177 #define IWM_SF_AGG_UNICAST_IDLE_TIMER 320 /* 300 uSec */ 3178 #define IWM_SF_AGG_UNICAST_AGING_TIMER 2016 /* 2 mSec */ 3179 #define IWM_SF_MCAST_IDLE_TIMER 2016 /* 2 mSec */ 3180 #define IWM_SF_MCAST_AGING_TIMER 10016 /* 10 mSec */ 3181 #define IWM_SF_BA_IDLE_TIMER 320 /* 300 uSec */ 3182 #define IWM_SF_BA_AGING_TIMER 2016 /* 2 mSec */ 3183 #define IWM_SF_TX_RE_IDLE_TIMER 320 /* 300 uSec */ 3184 #define IWM_SF_TX_RE_AGING_TIMER 2016 /* 2 mSec */ 3185 3186 #define IWM_SF_LONG_DELAY_AGING_TIMER 1000000 /* 1 Sec */ 3187 3188 #define IWM_SF_CFG_DUMMY_NOTIF_OFF (1 << 16) 3189 3190 /** 3191 * Smart Fifo configuration command. 3192 * @state: smart fifo state, types listed in iwm_sf_state. 3193 * @watermark: Minimum allowed available free space in RXF for transient state. 3194 * @long_delay_timeouts: aging and idle timer values for each scenario 3195 * in long delay state. 3196 * @full_on_timeouts: timer values for each scenario in full on state. 3197 */ 3198 struct iwm_sf_cfg_cmd { 3199 uint32_t state; 3200 uint32_t watermark[IWM_SF_TRANSIENT_STATES_NUMBER]; 3201 uint32_t long_delay_timeouts[IWM_SF_NUM_SCENARIO][IWM_SF_NUM_TIMEOUT_TYPES]; 3202 uint32_t full_on_timeouts[IWM_SF_NUM_SCENARIO][IWM_SF_NUM_TIMEOUT_TYPES]; 3203 } __packed; /* IWM_SF_CFG_API_S_VER_2 */ 3204 3205 /* 3206 * END mvm/fw-api.h 3207 */ 3208 3209 /* 3210 * BEGIN mvm/fw-api-mac.h 3211 */ 3212 3213 enum iwm_ac { 3214 IWM_AC_BK, 3215 IWM_AC_BE, 3216 IWM_AC_VI, 3217 IWM_AC_VO, 3218 IWM_AC_NUM, 3219 }; 3220 3221 /** 3222 * enum iwm_mac_protection_flags - MAC context flags 3223 * @IWM_MAC_PROT_FLG_TGG_PROTECT: 11g protection when transmitting OFDM frames, 3224 * this will require CCK RTS/CTS2self. 3225 * RTS/CTS will protect full burst time. 3226 * @IWM_MAC_PROT_FLG_HT_PROT: enable HT protection 3227 * @IWM_MAC_PROT_FLG_FAT_PROT: protect 40 MHz transmissions 3228 * @IWM_MAC_PROT_FLG_SELF_CTS_EN: allow CTS2self 3229 */ 3230 enum iwm_mac_protection_flags { 3231 IWM_MAC_PROT_FLG_TGG_PROTECT = (1 << 3), 3232 IWM_MAC_PROT_FLG_HT_PROT = (1 << 23), 3233 IWM_MAC_PROT_FLG_FAT_PROT = (1 << 24), 3234 IWM_MAC_PROT_FLG_SELF_CTS_EN = (1 << 30), 3235 }; 3236 3237 #define IWM_MAC_FLG_SHORT_SLOT (1 << 4) 3238 #define IWM_MAC_FLG_SHORT_PREAMBLE (1 << 5) 3239 3240 /** 3241 * enum iwm_mac_types - Supported MAC types 3242 * @IWM_FW_MAC_TYPE_FIRST: lowest supported MAC type 3243 * @IWM_FW_MAC_TYPE_AUX: Auxiliary MAC (internal) 3244 * @IWM_FW_MAC_TYPE_LISTENER: monitor MAC type (?) 3245 * @IWM_FW_MAC_TYPE_PIBSS: Pseudo-IBSS 3246 * @IWM_FW_MAC_TYPE_IBSS: IBSS 3247 * @IWM_FW_MAC_TYPE_BSS_STA: BSS (managed) station 3248 * @IWM_FW_MAC_TYPE_P2P_DEVICE: P2P Device 3249 * @IWM_FW_MAC_TYPE_P2P_STA: P2P client 3250 * @IWM_FW_MAC_TYPE_GO: P2P GO 3251 * @IWM_FW_MAC_TYPE_TEST: ? 3252 * @IWM_FW_MAC_TYPE_MAX: highest support MAC type 3253 */ 3254 enum iwm_mac_types { 3255 IWM_FW_MAC_TYPE_FIRST = 1, 3256 IWM_FW_MAC_TYPE_AUX = IWM_FW_MAC_TYPE_FIRST, 3257 IWM_FW_MAC_TYPE_LISTENER, 3258 IWM_FW_MAC_TYPE_PIBSS, 3259 IWM_FW_MAC_TYPE_IBSS, 3260 IWM_FW_MAC_TYPE_BSS_STA, 3261 IWM_FW_MAC_TYPE_P2P_DEVICE, 3262 IWM_FW_MAC_TYPE_P2P_STA, 3263 IWM_FW_MAC_TYPE_GO, 3264 IWM_FW_MAC_TYPE_TEST, 3265 IWM_FW_MAC_TYPE_MAX = IWM_FW_MAC_TYPE_TEST 3266 }; /* IWM_MAC_CONTEXT_TYPE_API_E_VER_1 */ 3267 3268 /** 3269 * enum iwm_tsf_id - TSF hw timer ID 3270 * @IWM_TSF_ID_A: use TSF A 3271 * @IWM_TSF_ID_B: use TSF B 3272 * @IWM_TSF_ID_C: use TSF C 3273 * @IWM_TSF_ID_D: use TSF D 3274 * @IWM_NUM_TSF_IDS: number of TSF timers available 3275 */ 3276 enum iwm_tsf_id { 3277 IWM_TSF_ID_A = 0, 3278 IWM_TSF_ID_B = 1, 3279 IWM_TSF_ID_C = 2, 3280 IWM_TSF_ID_D = 3, 3281 IWM_NUM_TSF_IDS = 4, 3282 }; /* IWM_TSF_ID_API_E_VER_1 */ 3283 3284 /** 3285 * struct iwm_mac_data_ap - configuration data for AP MAC context 3286 * @beacon_time: beacon transmit time in system time 3287 * @beacon_tsf: beacon transmit time in TSF 3288 * @bi: beacon interval in TU 3289 * @bi_reciprocal: 2^32 / bi 3290 * @dtim_interval: dtim transmit time in TU 3291 * @dtim_reciprocal: 2^32 / dtim_interval 3292 * @mcast_qid: queue ID for multicast traffic 3293 * @beacon_template: beacon template ID 3294 */ 3295 struct iwm_mac_data_ap { 3296 uint32_t beacon_time; 3297 uint64_t beacon_tsf; 3298 uint32_t bi; 3299 uint32_t bi_reciprocal; 3300 uint32_t dtim_interval; 3301 uint32_t dtim_reciprocal; 3302 uint32_t mcast_qid; 3303 uint32_t beacon_template; 3304 } __packed; /* AP_MAC_DATA_API_S_VER_1 */ 3305 3306 /** 3307 * struct iwm_mac_data_ibss - configuration data for IBSS MAC context 3308 * @beacon_time: beacon transmit time in system time 3309 * @beacon_tsf: beacon transmit time in TSF 3310 * @bi: beacon interval in TU 3311 * @bi_reciprocal: 2^32 / bi 3312 * @beacon_template: beacon template ID 3313 */ 3314 struct iwm_mac_data_ibss { 3315 uint32_t beacon_time; 3316 uint64_t beacon_tsf; 3317 uint32_t bi; 3318 uint32_t bi_reciprocal; 3319 uint32_t beacon_template; 3320 } __packed; /* IBSS_MAC_DATA_API_S_VER_1 */ 3321 3322 /** 3323 * struct iwm_mac_data_sta - configuration data for station MAC context 3324 * @is_assoc: 1 for associated state, 0 otherwise 3325 * @dtim_time: DTIM arrival time in system time 3326 * @dtim_tsf: DTIM arrival time in TSF 3327 * @bi: beacon interval in TU, applicable only when associated 3328 * @bi_reciprocal: 2^32 / bi , applicable only when associated 3329 * @dtim_interval: DTIM interval in TU, applicable only when associated 3330 * @dtim_reciprocal: 2^32 / dtim_interval , applicable only when associated 3331 * @listen_interval: in beacon intervals, applicable only when associated 3332 * @assoc_id: unique ID assigned by the AP during association 3333 */ 3334 struct iwm_mac_data_sta { 3335 uint32_t is_assoc; 3336 uint32_t dtim_time; 3337 uint64_t dtim_tsf; 3338 uint32_t bi; 3339 uint32_t bi_reciprocal; 3340 uint32_t dtim_interval; 3341 uint32_t dtim_reciprocal; 3342 uint32_t listen_interval; 3343 uint32_t assoc_id; 3344 uint32_t assoc_beacon_arrive_time; 3345 } __packed; /* IWM_STA_MAC_DATA_API_S_VER_1 */ 3346 3347 /** 3348 * struct iwm_mac_data_go - configuration data for P2P GO MAC context 3349 * @ap: iwm_mac_data_ap struct with most config data 3350 * @ctwin: client traffic window in TU (period after TBTT when GO is present). 3351 * 0 indicates that there is no CT window. 3352 * @opp_ps_enabled: indicate that opportunistic PS allowed 3353 */ 3354 struct iwm_mac_data_go { 3355 struct iwm_mac_data_ap ap; 3356 uint32_t ctwin; 3357 uint32_t opp_ps_enabled; 3358 } __packed; /* GO_MAC_DATA_API_S_VER_1 */ 3359 3360 /** 3361 * struct iwm_mac_data_p2p_sta - configuration data for P2P client MAC context 3362 * @sta: iwm_mac_data_sta struct with most config data 3363 * @ctwin: client traffic window in TU (period after TBTT when GO is present). 3364 * 0 indicates that there is no CT window. 3365 */ 3366 struct iwm_mac_data_p2p_sta { 3367 struct iwm_mac_data_sta sta; 3368 uint32_t ctwin; 3369 } __packed; /* P2P_STA_MAC_DATA_API_S_VER_1 */ 3370 3371 /** 3372 * struct iwm_mac_data_pibss - Pseudo IBSS config data 3373 * @stats_interval: interval in TU between statistics notifications to host. 3374 */ 3375 struct iwm_mac_data_pibss { 3376 uint32_t stats_interval; 3377 } __packed; /* PIBSS_MAC_DATA_API_S_VER_1 */ 3378 3379 /* 3380 * struct iwm_mac_data_p2p_dev - configuration data for the P2P Device MAC 3381 * context. 3382 * @is_disc_extended: if set to true, P2P Device discoverability is enabled on 3383 * other channels as well. This should be to true only in case that the 3384 * device is discoverable and there is an active GO. Note that setting this 3385 * field when not needed, will increase the number of interrupts and have 3386 * effect on the platform power, as this setting opens the Rx filters on 3387 * all macs. 3388 */ 3389 struct iwm_mac_data_p2p_dev { 3390 uint32_t is_disc_extended; 3391 } __packed; /* _P2P_DEV_MAC_DATA_API_S_VER_1 */ 3392 3393 /** 3394 * enum iwm_mac_filter_flags - MAC context filter flags 3395 * @IWM_MAC_FILTER_IN_PROMISC: accept all data frames 3396 * @IWM_MAC_FILTER_IN_CONTROL_AND_MGMT: pass all mangement and 3397 * control frames to the host 3398 * @IWM_MAC_FILTER_ACCEPT_GRP: accept multicast frames 3399 * @IWM_MAC_FILTER_DIS_DECRYPT: don't decrypt unicast frames 3400 * @IWM_MAC_FILTER_DIS_GRP_DECRYPT: don't decrypt multicast frames 3401 * @IWM_MAC_FILTER_IN_BEACON: transfer foreign BSS's beacons to host 3402 * (in station mode when associated) 3403 * @IWM_MAC_FILTER_OUT_BCAST: filter out all broadcast frames 3404 * @IWM_MAC_FILTER_IN_CRC32: extract FCS and append it to frames 3405 * @IWM_MAC_FILTER_IN_PROBE_REQUEST: pass probe requests to host 3406 */ 3407 enum iwm_mac_filter_flags { 3408 IWM_MAC_FILTER_IN_PROMISC = (1 << 0), 3409 IWM_MAC_FILTER_IN_CONTROL_AND_MGMT = (1 << 1), 3410 IWM_MAC_FILTER_ACCEPT_GRP = (1 << 2), 3411 IWM_MAC_FILTER_DIS_DECRYPT = (1 << 3), 3412 IWM_MAC_FILTER_DIS_GRP_DECRYPT = (1 << 4), 3413 IWM_MAC_FILTER_IN_BEACON = (1 << 6), 3414 IWM_MAC_FILTER_OUT_BCAST = (1 << 8), 3415 IWM_MAC_FILTER_IN_CRC32 = (1 << 11), 3416 IWM_MAC_FILTER_IN_PROBE_REQUEST = (1 << 12), 3417 }; 3418 3419 /** 3420 * enum iwm_mac_qos_flags - QoS flags 3421 * @IWM_MAC_QOS_FLG_UPDATE_EDCA: ? 3422 * @IWM_MAC_QOS_FLG_TGN: HT is enabled 3423 * @IWM_MAC_QOS_FLG_TXOP_TYPE: ? 3424 * 3425 */ 3426 enum iwm_mac_qos_flags { 3427 IWM_MAC_QOS_FLG_UPDATE_EDCA = (1 << 0), 3428 IWM_MAC_QOS_FLG_TGN = (1 << 1), 3429 IWM_MAC_QOS_FLG_TXOP_TYPE = (1 << 4), 3430 }; 3431 3432 /** 3433 * struct iwm_ac_qos - QOS timing params for IWM_MAC_CONTEXT_CMD 3434 * @cw_min: Contention window, start value in numbers of slots. 3435 * Should be a power-of-2, minus 1. Device's default is 0x0f. 3436 * @cw_max: Contention window, max value in numbers of slots. 3437 * Should be a power-of-2, minus 1. Device's default is 0x3f. 3438 * @aifsn: Number of slots in Arbitration Interframe Space (before 3439 * performing random backoff timing prior to Tx). Device default 1. 3440 * @fifos_mask: FIFOs used by this MAC for this AC 3441 * @edca_txop: Length of Tx opportunity, in uSecs. Device default is 0. 3442 * 3443 * One instance of this config struct for each of 4 EDCA access categories 3444 * in struct iwm_qosparam_cmd. 3445 * 3446 * Device will automatically increase contention window by (2*CW) + 1 for each 3447 * transmission retry. Device uses cw_max as a bit mask, ANDed with new CW 3448 * value, to cap the CW value. 3449 */ 3450 struct iwm_ac_qos { 3451 uint16_t cw_min; 3452 uint16_t cw_max; 3453 uint8_t aifsn; 3454 uint8_t fifos_mask; 3455 uint16_t edca_txop; 3456 } __packed; /* IWM_AC_QOS_API_S_VER_2 */ 3457 3458 /** 3459 * struct iwm_mac_ctx_cmd - command structure to configure MAC contexts 3460 * ( IWM_MAC_CONTEXT_CMD = 0x28 ) 3461 * @id_and_color: ID and color of the MAC 3462 * @action: action to perform, one of IWM_FW_CTXT_ACTION_* 3463 * @mac_type: one of IWM_FW_MAC_TYPE_* 3464 * @tsd_id: TSF HW timer, one of IWM_TSF_ID_* 3465 * @node_addr: MAC address 3466 * @bssid_addr: BSSID 3467 * @cck_rates: basic rates available for CCK 3468 * @ofdm_rates: basic rates available for OFDM 3469 * @protection_flags: combination of IWM_MAC_PROT_FLG_FLAG_* 3470 * @cck_short_preamble: 0x20 for enabling short preamble, 0 otherwise 3471 * @short_slot: 0x10 for enabling short slots, 0 otherwise 3472 * @filter_flags: combination of IWM_MAC_FILTER_* 3473 * @qos_flags: from IWM_MAC_QOS_FLG_* 3474 * @ac: one iwm_mac_qos configuration for each AC 3475 * @mac_specific: one of struct iwm_mac_data_*, according to mac_type 3476 */ 3477 struct iwm_mac_ctx_cmd { 3478 /* COMMON_INDEX_HDR_API_S_VER_1 */ 3479 uint32_t id_and_color; 3480 uint32_t action; 3481 /* IWM_MAC_CONTEXT_COMMON_DATA_API_S_VER_1 */ 3482 uint32_t mac_type; 3483 uint32_t tsf_id; 3484 uint8_t node_addr[6]; 3485 uint16_t reserved_for_node_addr; 3486 uint8_t bssid_addr[6]; 3487 uint16_t reserved_for_bssid_addr; 3488 uint32_t cck_rates; 3489 uint32_t ofdm_rates; 3490 uint32_t protection_flags; 3491 uint32_t cck_short_preamble; 3492 uint32_t short_slot; 3493 uint32_t filter_flags; 3494 /* IWM_MAC_QOS_PARAM_API_S_VER_1 */ 3495 uint32_t qos_flags; 3496 struct iwm_ac_qos ac[IWM_AC_NUM+1]; 3497 /* IWM_MAC_CONTEXT_COMMON_DATA_API_S */ 3498 union { 3499 struct iwm_mac_data_ap ap; 3500 struct iwm_mac_data_go go; 3501 struct iwm_mac_data_sta sta; 3502 struct iwm_mac_data_p2p_sta p2p_sta; 3503 struct iwm_mac_data_p2p_dev p2p_dev; 3504 struct iwm_mac_data_pibss pibss; 3505 struct iwm_mac_data_ibss ibss; 3506 }; 3507 } __packed; /* IWM_MAC_CONTEXT_CMD_API_S_VER_1 */ 3508 3509 static inline uint32_t iwm_mvm_reciprocal(uint32_t v) 3510 { 3511 if (!v) 3512 return 0; 3513 return 0xFFFFFFFF / v; 3514 } 3515 3516 #define IWM_NONQOS_SEQ_GET 0x1 3517 #define IWM_NONQOS_SEQ_SET 0x2 3518 struct iwm_nonqos_seq_query_cmd { 3519 uint32_t get_set_flag; 3520 uint32_t mac_id_n_color; 3521 uint16_t value; 3522 uint16_t reserved; 3523 } __packed; /* IWM_NON_QOS_TX_COUNTER_GET_SET_API_S_VER_1 */ 3524 3525 /* 3526 * END mvm/fw-api-mac.h 3527 */ 3528 3529 /* 3530 * BEGIN mvm/fw-api-power.h 3531 */ 3532 3533 /* Power Management Commands, Responses, Notifications */ 3534 3535 /** 3536 * enum iwm_ltr_config_flags - masks for LTR config command flags 3537 * @IWM_LTR_CFG_FLAG_FEATURE_ENABLE: Feature operational status 3538 * @IWM_LTR_CFG_FLAG_HW_DIS_ON_SHADOW_REG_ACCESS: allow LTR change on shadow 3539 * memory access 3540 * @IWM_LTR_CFG_FLAG_HW_EN_SHRT_WR_THROUGH: allow LTR msg send on ANY LTR 3541 * reg change 3542 * @IWM_LTR_CFG_FLAG_HW_DIS_ON_D0_2_D3: allow LTR msg send on transition from 3543 * D0 to D3 3544 * @IWM_LTR_CFG_FLAG_SW_SET_SHORT: fixed static short LTR register 3545 * @IWM_LTR_CFG_FLAG_SW_SET_LONG: fixed static short LONG register 3546 * @IWM_LTR_CFG_FLAG_DENIE_C10_ON_PD: allow going into C10 on PD 3547 */ 3548 enum iwm_ltr_config_flags { 3549 IWM_LTR_CFG_FLAG_FEATURE_ENABLE = (1 << 0), 3550 IWM_LTR_CFG_FLAG_HW_DIS_ON_SHADOW_REG_ACCESS = (1 << 1), 3551 IWM_LTR_CFG_FLAG_HW_EN_SHRT_WR_THROUGH = (1 << 2), 3552 IWM_LTR_CFG_FLAG_HW_DIS_ON_D0_2_D3 = (1 << 3), 3553 IWM_LTR_CFG_FLAG_SW_SET_SHORT = (1 << 4), 3554 IWM_LTR_CFG_FLAG_SW_SET_LONG = (1 << 5), 3555 IWM_LTR_CFG_FLAG_DENIE_C10_ON_PD = (1 << 6), 3556 }; 3557 3558 /** 3559 * struct iwm_ltr_config_cmd_v1 - configures the LTR 3560 * @flags: See %enum iwm_ltr_config_flags 3561 */ 3562 struct iwm_ltr_config_cmd_v1 { 3563 uint32_t flags; 3564 uint32_t static_long; 3565 uint32_t static_short; 3566 } __packed; /* LTR_CAPABLE_API_S_VER_1 */ 3567 3568 #define IWM_LTR_VALID_STATES_NUM 4 3569 3570 /** 3571 * struct iwm_ltr_config_cmd - configures the LTR 3572 * @flags: See %enum iwm_ltr_config_flags 3573 * @static_long: 3574 * @static_short: 3575 * @ltr_cfg_values: 3576 * @ltr_short_idle_timeout: 3577 */ 3578 struct iwm_ltr_config_cmd { 3579 uint32_t flags; 3580 uint32_t static_long; 3581 uint32_t static_short; 3582 uint32_t ltr_cfg_values[IWM_LTR_VALID_STATES_NUM]; 3583 uint32_t ltr_short_idle_timeout; 3584 } __packed; /* LTR_CAPABLE_API_S_VER_2 */ 3585 3586 /* Radio LP RX Energy Threshold measured in dBm */ 3587 #define IWM_POWER_LPRX_RSSI_THRESHOLD 75 3588 #define IWM_POWER_LPRX_RSSI_THRESHOLD_MAX 94 3589 #define IWM_POWER_LPRX_RSSI_THRESHOLD_MIN 30 3590 3591 /** 3592 * enum iwm_scan_flags - masks for power table command flags 3593 * @IWM_POWER_FLAGS_POWER_SAVE_ENA_MSK: '1' Allow to save power by turning off 3594 * receiver and transmitter. '0' - does not allow. 3595 * @IWM_POWER_FLAGS_POWER_MANAGEMENT_ENA_MSK: '0' Driver disables power management, 3596 * '1' Driver enables PM (use rest of parameters) 3597 * @IWM_POWER_FLAGS_SKIP_OVER_DTIM_MSK: '0' PM have to walk up every DTIM, 3598 * '1' PM could sleep over DTIM till listen Interval. 3599 * @IWM_POWER_FLAGS_SNOOZE_ENA_MSK: Enable snoozing only if uAPSD is enabled and all 3600 * access categories are both delivery and trigger enabled. 3601 * @IWM_POWER_FLAGS_BT_SCO_ENA: Enable BT SCO coex only if uAPSD and 3602 * PBW Snoozing enabled 3603 * @IWM_POWER_FLAGS_ADVANCE_PM_ENA_MSK: Advanced PM (uAPSD) enable mask 3604 * @IWM_POWER_FLAGS_LPRX_ENA_MSK: Low Power RX enable. 3605 * @IWM_POWER_FLAGS_AP_UAPSD_MISBEHAVING_ENA_MSK: AP/GO's uAPSD misbehaving 3606 * detection enablement 3607 */ 3608 enum iwm_power_flags { 3609 IWM_POWER_FLAGS_POWER_SAVE_ENA_MSK = (1 << 0), 3610 IWM_POWER_FLAGS_POWER_MANAGEMENT_ENA_MSK = (1 << 1), 3611 IWM_POWER_FLAGS_SKIP_OVER_DTIM_MSK = (1 << 2), 3612 IWM_POWER_FLAGS_SNOOZE_ENA_MSK = (1 << 5), 3613 IWM_POWER_FLAGS_BT_SCO_ENA = (1 << 8), 3614 IWM_POWER_FLAGS_ADVANCE_PM_ENA_MSK = (1 << 9), 3615 IWM_POWER_FLAGS_LPRX_ENA_MSK = (1 << 11), 3616 IWM_POWER_FLAGS_UAPSD_MISBEHAVING_ENA_MSK = (1 << 12), 3617 }; 3618 3619 #define IWM_POWER_VEC_SIZE 5 3620 3621 /** 3622 * struct iwm_powertable_cmd - legacy power command. Beside old API support this 3623 * is used also with a new power API for device wide power settings. 3624 * IWM_POWER_TABLE_CMD = 0x77 (command, has simple generic response) 3625 * 3626 * @flags: Power table command flags from IWM_POWER_FLAGS_* 3627 * @keep_alive_seconds: Keep alive period in seconds. Default - 25 sec. 3628 * Minimum allowed:- 3 * DTIM. Keep alive period must be 3629 * set regardless of power scheme or current power state. 3630 * FW use this value also when PM is disabled. 3631 * @rx_data_timeout: Minimum time (usec) from last Rx packet for AM to 3632 * PSM transition - legacy PM 3633 * @tx_data_timeout: Minimum time (usec) from last Tx packet for AM to 3634 * PSM transition - legacy PM 3635 * @sleep_interval: not in use 3636 * @skip_dtim_periods: Number of DTIM periods to skip if Skip over DTIM flag 3637 * is set. For example, if it is required to skip over 3638 * one DTIM, this value need to be set to 2 (DTIM periods). 3639 * @lprx_rssi_threshold: Signal strength up to which LP RX can be enabled. 3640 * Default: 80dbm 3641 */ 3642 struct iwm_powertable_cmd { 3643 /* PM_POWER_TABLE_CMD_API_S_VER_6 */ 3644 uint16_t flags; 3645 uint8_t keep_alive_seconds; 3646 uint8_t debug_flags; 3647 uint32_t rx_data_timeout; 3648 uint32_t tx_data_timeout; 3649 uint32_t sleep_interval[IWM_POWER_VEC_SIZE]; 3650 uint32_t skip_dtim_periods; 3651 uint32_t lprx_rssi_threshold; 3652 } __packed; 3653 3654 /** 3655 * enum iwm_device_power_flags - masks for device power command flags 3656 * @IWM_DEVICE_POWER_FLAGS_POWER_SAVE_ENA_MSK: '1' Allow to save power by turning off 3657 * receiver and transmitter. '0' - does not allow. 3658 */ 3659 enum iwm_device_power_flags { 3660 IWM_DEVICE_POWER_FLAGS_POWER_SAVE_ENA_MSK = (1 << 0), 3661 }; 3662 3663 /** 3664 * struct iwm_device_power_cmd - device wide power command. 3665 * IWM_DEVICE_POWER_CMD = 0x77 (command, has simple generic response) 3666 * 3667 * @flags: Power table command flags from IWM_DEVICE_POWER_FLAGS_* 3668 */ 3669 struct iwm_device_power_cmd { 3670 /* PM_POWER_TABLE_CMD_API_S_VER_6 */ 3671 uint16_t flags; 3672 uint16_t reserved; 3673 } __packed; 3674 3675 /** 3676 * struct iwm_mac_power_cmd - New power command containing uAPSD support 3677 * IWM_MAC_PM_POWER_TABLE = 0xA9 (command, has simple generic response) 3678 * @id_and_color: MAC contex identifier 3679 * @flags: Power table command flags from POWER_FLAGS_* 3680 * @keep_alive_seconds: Keep alive period in seconds. Default - 25 sec. 3681 * Minimum allowed:- 3 * DTIM. Keep alive period must be 3682 * set regardless of power scheme or current power state. 3683 * FW use this value also when PM is disabled. 3684 * @rx_data_timeout: Minimum time (usec) from last Rx packet for AM to 3685 * PSM transition - legacy PM 3686 * @tx_data_timeout: Minimum time (usec) from last Tx packet for AM to 3687 * PSM transition - legacy PM 3688 * @sleep_interval: not in use 3689 * @skip_dtim_periods: Number of DTIM periods to skip if Skip over DTIM flag 3690 * is set. For example, if it is required to skip over 3691 * one DTIM, this value need to be set to 2 (DTIM periods). 3692 * @rx_data_timeout_uapsd: Minimum time (usec) from last Rx packet for AM to 3693 * PSM transition - uAPSD 3694 * @tx_data_timeout_uapsd: Minimum time (usec) from last Tx packet for AM to 3695 * PSM transition - uAPSD 3696 * @lprx_rssi_threshold: Signal strength up to which LP RX can be enabled. 3697 * Default: 80dbm 3698 * @num_skip_dtim: Number of DTIMs to skip if Skip over DTIM flag is set 3699 * @snooze_interval: Maximum time between attempts to retrieve buffered data 3700 * from the AP [msec] 3701 * @snooze_window: A window of time in which PBW snoozing insures that all 3702 * packets received. It is also the minimum time from last 3703 * received unicast RX packet, before client stops snoozing 3704 * for data. [msec] 3705 * @snooze_step: TBD 3706 * @qndp_tid: TID client shall use for uAPSD QNDP triggers 3707 * @uapsd_ac_flags: Set trigger-enabled and delivery-enabled indication for 3708 * each corresponding AC. 3709 * Use IEEE80211_WMM_IE_STA_QOSINFO_AC* for correct values. 3710 * @uapsd_max_sp: Use IEEE80211_WMM_IE_STA_QOSINFO_SP_* for correct 3711 * values. 3712 * @heavy_tx_thld_packets: TX threshold measured in number of packets 3713 * @heavy_rx_thld_packets: RX threshold measured in number of packets 3714 * @heavy_tx_thld_percentage: TX threshold measured in load's percentage 3715 * @heavy_rx_thld_percentage: RX threshold measured in load's percentage 3716 * @limited_ps_threshold: 3717 */ 3718 struct iwm_mac_power_cmd { 3719 /* CONTEXT_DESC_API_T_VER_1 */ 3720 uint32_t id_and_color; 3721 3722 /* CLIENT_PM_POWER_TABLE_S_VER_1 */ 3723 uint16_t flags; 3724 uint16_t keep_alive_seconds; 3725 uint32_t rx_data_timeout; 3726 uint32_t tx_data_timeout; 3727 uint32_t rx_data_timeout_uapsd; 3728 uint32_t tx_data_timeout_uapsd; 3729 uint8_t lprx_rssi_threshold; 3730 uint8_t skip_dtim_periods; 3731 uint16_t snooze_interval; 3732 uint16_t snooze_window; 3733 uint8_t snooze_step; 3734 uint8_t qndp_tid; 3735 uint8_t uapsd_ac_flags; 3736 uint8_t uapsd_max_sp; 3737 uint8_t heavy_tx_thld_packets; 3738 uint8_t heavy_rx_thld_packets; 3739 uint8_t heavy_tx_thld_percentage; 3740 uint8_t heavy_rx_thld_percentage; 3741 uint8_t limited_ps_threshold; 3742 uint8_t reserved; 3743 } __packed; 3744 3745 /* 3746 * struct iwm_uapsd_misbehaving_ap_notif - FW sends this notification when 3747 * associated AP is identified as improperly implementing uAPSD protocol. 3748 * IWM_PSM_UAPSD_AP_MISBEHAVING_NOTIFICATION = 0x78 3749 * @sta_id: index of station in uCode's station table - associated AP ID in 3750 * this context. 3751 */ 3752 struct iwm_uapsd_misbehaving_ap_notif { 3753 uint32_t sta_id; 3754 uint8_t mac_id; 3755 uint8_t reserved[3]; 3756 } __packed; 3757 3758 /** 3759 * struct iwm_beacon_filter_cmd 3760 * IWM_REPLY_BEACON_FILTERING_CMD = 0xd2 (command) 3761 * @id_and_color: MAC contex identifier 3762 * @bf_energy_delta: Used for RSSI filtering, if in 'normal' state. Send beacon 3763 * to driver if delta in Energy values calculated for this and last 3764 * passed beacon is greater than this threshold. Zero value means that 3765 * the Energy change is ignored for beacon filtering, and beacon will 3766 * not be forced to be sent to driver regardless of this delta. Typical 3767 * energy delta 5dB. 3768 * @bf_roaming_energy_delta: Used for RSSI filtering, if in 'roaming' state. 3769 * Send beacon to driver if delta in Energy values calculated for this 3770 * and last passed beacon is greater than this threshold. Zero value 3771 * means that the Energy change is ignored for beacon filtering while in 3772 * Roaming state, typical energy delta 1dB. 3773 * @bf_roaming_state: Used for RSSI filtering. If absolute Energy values 3774 * calculated for current beacon is less than the threshold, use 3775 * Roaming Energy Delta Threshold, otherwise use normal Energy Delta 3776 * Threshold. Typical energy threshold is -72dBm. 3777 * @bf_temp_threshold: This threshold determines the type of temperature 3778 * filtering (Slow or Fast) that is selected (Units are in Celsuis): 3779 * If the current temperature is above this threshold - Fast filter 3780 * will be used, If the current temperature is below this threshold - 3781 * Slow filter will be used. 3782 * @bf_temp_fast_filter: Send Beacon to driver if delta in temperature values 3783 * calculated for this and the last passed beacon is greater than this 3784 * threshold. Zero value means that the temperature change is ignored for 3785 * beacon filtering; beacons will not be forced to be sent to driver 3786 * regardless of whether its temperature has been changed. 3787 * @bf_temp_slow_filter: Send Beacon to driver if delta in temperature values 3788 * calculated for this and the last passed beacon is greater than this 3789 * threshold. Zero value means that the temperature change is ignored for 3790 * beacon filtering; beacons will not be forced to be sent to driver 3791 * regardless of whether its temperature has been changed. 3792 * @bf_enable_beacon_filter: 1, beacon filtering is enabled; 0, disabled. 3793 * @bf_filter_escape_timer: Send beacons to the driver if no beacons were passed 3794 * for a specific period of time. Units: Beacons. 3795 * @ba_escape_timer: Fully receive and parse beacon if no beacons were passed 3796 * for a longer period of time then this escape-timeout. Units: Beacons. 3797 * @ba_enable_beacon_abort: 1, beacon abort is enabled; 0, disabled. 3798 */ 3799 struct iwm_beacon_filter_cmd { 3800 uint32_t bf_energy_delta; 3801 uint32_t bf_roaming_energy_delta; 3802 uint32_t bf_roaming_state; 3803 uint32_t bf_temp_threshold; 3804 uint32_t bf_temp_fast_filter; 3805 uint32_t bf_temp_slow_filter; 3806 uint32_t bf_enable_beacon_filter; 3807 uint32_t bf_debug_flag; 3808 uint32_t bf_escape_timer; 3809 uint32_t ba_escape_timer; 3810 uint32_t ba_enable_beacon_abort; 3811 } __packed; 3812 3813 /* Beacon filtering and beacon abort */ 3814 #define IWM_BF_ENERGY_DELTA_DEFAULT 5 3815 #define IWM_BF_ENERGY_DELTA_MAX 255 3816 #define IWM_BF_ENERGY_DELTA_MIN 0 3817 3818 #define IWM_BF_ROAMING_ENERGY_DELTA_DEFAULT 1 3819 #define IWM_BF_ROAMING_ENERGY_DELTA_MAX 255 3820 #define IWM_BF_ROAMING_ENERGY_DELTA_MIN 0 3821 3822 #define IWM_BF_ROAMING_STATE_DEFAULT 72 3823 #define IWM_BF_ROAMING_STATE_MAX 255 3824 #define IWM_BF_ROAMING_STATE_MIN 0 3825 3826 #define IWM_BF_TEMP_THRESHOLD_DEFAULT 112 3827 #define IWM_BF_TEMP_THRESHOLD_MAX 255 3828 #define IWM_BF_TEMP_THRESHOLD_MIN 0 3829 3830 #define IWM_BF_TEMP_FAST_FILTER_DEFAULT 1 3831 #define IWM_BF_TEMP_FAST_FILTER_MAX 255 3832 #define IWM_BF_TEMP_FAST_FILTER_MIN 0 3833 3834 #define IWM_BF_TEMP_SLOW_FILTER_DEFAULT 5 3835 #define IWM_BF_TEMP_SLOW_FILTER_MAX 255 3836 #define IWM_BF_TEMP_SLOW_FILTER_MIN 0 3837 3838 #define IWM_BF_ENABLE_BEACON_FILTER_DEFAULT 1 3839 3840 #define IWM_BF_DEBUG_FLAG_DEFAULT 0 3841 3842 #define IWM_BF_ESCAPE_TIMER_DEFAULT 50 3843 #define IWM_BF_ESCAPE_TIMER_MAX 1024 3844 #define IWM_BF_ESCAPE_TIMER_MIN 0 3845 3846 #define IWM_BA_ESCAPE_TIMER_DEFAULT 6 3847 #define IWM_BA_ESCAPE_TIMER_D3 9 3848 #define IWM_BA_ESCAPE_TIMER_MAX 1024 3849 #define IWM_BA_ESCAPE_TIMER_MIN 0 3850 3851 #define IWM_BA_ENABLE_BEACON_ABORT_DEFAULT 1 3852 3853 #define IWM_BF_CMD_CONFIG_DEFAULTS \ 3854 .bf_energy_delta = htole32(IWM_BF_ENERGY_DELTA_DEFAULT), \ 3855 .bf_roaming_energy_delta = \ 3856 htole32(IWM_BF_ROAMING_ENERGY_DELTA_DEFAULT), \ 3857 .bf_roaming_state = htole32(IWM_BF_ROAMING_STATE_DEFAULT), \ 3858 .bf_temp_threshold = htole32(IWM_BF_TEMP_THRESHOLD_DEFAULT), \ 3859 .bf_temp_fast_filter = htole32(IWM_BF_TEMP_FAST_FILTER_DEFAULT), \ 3860 .bf_temp_slow_filter = htole32(IWM_BF_TEMP_SLOW_FILTER_DEFAULT), \ 3861 .bf_debug_flag = htole32(IWM_BF_DEBUG_FLAG_DEFAULT), \ 3862 .bf_escape_timer = htole32(IWM_BF_ESCAPE_TIMER_DEFAULT), \ 3863 .ba_escape_timer = htole32(IWM_BA_ESCAPE_TIMER_DEFAULT) 3864 3865 /* 3866 * END mvm/fw-api-power.h 3867 */ 3868 3869 /* 3870 * BEGIN mvm/fw-api-rs.h 3871 */ 3872 3873 /* 3874 * These serve as indexes into 3875 * struct iwm_rate_info fw_rate_idx_to_plcp[IWM_RATE_COUNT]; 3876 * TODO: avoid overlap between legacy and HT rates 3877 */ 3878 enum { 3879 IWM_RATE_1M_INDEX = 0, 3880 IWM_FIRST_CCK_RATE = IWM_RATE_1M_INDEX, 3881 IWM_RATE_2M_INDEX, 3882 IWM_RATE_5M_INDEX, 3883 IWM_RATE_11M_INDEX, 3884 IWM_LAST_CCK_RATE = IWM_RATE_11M_INDEX, 3885 IWM_RATE_6M_INDEX, 3886 IWM_FIRST_OFDM_RATE = IWM_RATE_6M_INDEX, 3887 IWM_RATE_MCS_0_INDEX = IWM_RATE_6M_INDEX, 3888 IWM_FIRST_HT_RATE = IWM_RATE_MCS_0_INDEX, 3889 IWM_FIRST_VHT_RATE = IWM_RATE_MCS_0_INDEX, 3890 IWM_RATE_9M_INDEX, 3891 IWM_RATE_12M_INDEX, 3892 IWM_RATE_MCS_1_INDEX = IWM_RATE_12M_INDEX, 3893 IWM_RATE_18M_INDEX, 3894 IWM_RATE_MCS_2_INDEX = IWM_RATE_18M_INDEX, 3895 IWM_RATE_24M_INDEX, 3896 IWM_RATE_MCS_3_INDEX = IWM_RATE_24M_INDEX, 3897 IWM_RATE_36M_INDEX, 3898 IWM_RATE_MCS_4_INDEX = IWM_RATE_36M_INDEX, 3899 IWM_RATE_48M_INDEX, 3900 IWM_RATE_MCS_5_INDEX = IWM_RATE_48M_INDEX, 3901 IWM_RATE_54M_INDEX, 3902 IWM_RATE_MCS_6_INDEX = IWM_RATE_54M_INDEX, 3903 IWM_LAST_NON_HT_RATE = IWM_RATE_54M_INDEX, 3904 IWM_RATE_60M_INDEX, 3905 IWM_RATE_MCS_7_INDEX = IWM_RATE_60M_INDEX, 3906 IWM_LAST_HT_RATE = IWM_RATE_MCS_7_INDEX, 3907 IWM_RATE_MCS_8_INDEX, 3908 IWM_RATE_MCS_9_INDEX, 3909 IWM_LAST_VHT_RATE = IWM_RATE_MCS_9_INDEX, 3910 IWM_RATE_COUNT_LEGACY = IWM_LAST_NON_HT_RATE + 1, 3911 IWM_RATE_COUNT = IWM_LAST_VHT_RATE + 1, 3912 }; 3913 3914 #define IWM_RATE_BIT_MSK(r) (1 << (IWM_RATE_##r##M_INDEX)) 3915 3916 /* fw API values for legacy bit rates, both OFDM and CCK */ 3917 enum { 3918 IWM_RATE_6M_PLCP = 13, 3919 IWM_RATE_9M_PLCP = 15, 3920 IWM_RATE_12M_PLCP = 5, 3921 IWM_RATE_18M_PLCP = 7, 3922 IWM_RATE_24M_PLCP = 9, 3923 IWM_RATE_36M_PLCP = 11, 3924 IWM_RATE_48M_PLCP = 1, 3925 IWM_RATE_54M_PLCP = 3, 3926 IWM_RATE_1M_PLCP = 10, 3927 IWM_RATE_2M_PLCP = 20, 3928 IWM_RATE_5M_PLCP = 55, 3929 IWM_RATE_11M_PLCP = 110, 3930 IWM_RATE_INVM_PLCP = -1, 3931 }; 3932 3933 /* 3934 * rate_n_flags bit fields 3935 * 3936 * The 32-bit value has different layouts in the low 8 bites depending on the 3937 * format. There are three formats, HT, VHT and legacy (11abg, with subformats 3938 * for CCK and OFDM). 3939 * 3940 * High-throughput (HT) rate format 3941 * bit 8 is 1, bit 26 is 0, bit 9 is 0 (OFDM) 3942 * Very High-throughput (VHT) rate format 3943 * bit 8 is 0, bit 26 is 1, bit 9 is 0 (OFDM) 3944 * Legacy OFDM rate format for bits 7:0 3945 * bit 8 is 0, bit 26 is 0, bit 9 is 0 (OFDM) 3946 * Legacy CCK rate format for bits 7:0: 3947 * bit 8 is 0, bit 26 is 0, bit 9 is 1 (CCK) 3948 */ 3949 3950 /* Bit 8: (1) HT format, (0) legacy or VHT format */ 3951 #define IWM_RATE_MCS_HT_POS 8 3952 #define IWM_RATE_MCS_HT_MSK (1 << IWM_RATE_MCS_HT_POS) 3953 3954 /* Bit 9: (1) CCK, (0) OFDM. HT (bit 8) must be "0" for this bit to be valid */ 3955 #define IWM_RATE_MCS_CCK_POS 9 3956 #define IWM_RATE_MCS_CCK_MSK (1 << IWM_RATE_MCS_CCK_POS) 3957 3958 /* Bit 26: (1) VHT format, (0) legacy format in bits 8:0 */ 3959 #define IWM_RATE_MCS_VHT_POS 26 3960 #define IWM_RATE_MCS_VHT_MSK (1 << IWM_RATE_MCS_VHT_POS) 3961 3962 3963 /* 3964 * High-throughput (HT) rate format for bits 7:0 3965 * 3966 * 2-0: MCS rate base 3967 * 0) 6 Mbps 3968 * 1) 12 Mbps 3969 * 2) 18 Mbps 3970 * 3) 24 Mbps 3971 * 4) 36 Mbps 3972 * 5) 48 Mbps 3973 * 6) 54 Mbps 3974 * 7) 60 Mbps 3975 * 4-3: 0) Single stream (SISO) 3976 * 1) Dual stream (MIMO) 3977 * 2) Triple stream (MIMO) 3978 * 5: Value of 0x20 in bits 7:0 indicates 6 Mbps HT40 duplicate data 3979 * (bits 7-6 are zero) 3980 * 3981 * Together the low 5 bits work out to the MCS index because we don't 3982 * support MCSes above 15/23, and 0-7 have one stream, 8-15 have two 3983 * streams and 16-23 have three streams. We could also support MCS 32 3984 * which is the duplicate 20 MHz MCS (bit 5 set, all others zero.) 3985 */ 3986 #define IWM_RATE_HT_MCS_RATE_CODE_MSK 0x7 3987 #define IWM_RATE_HT_MCS_NSS_POS 3 3988 #define IWM_RATE_HT_MCS_NSS_MSK (3 << IWM_RATE_HT_MCS_NSS_POS) 3989 3990 /* Bit 10: (1) Use Green Field preamble */ 3991 #define IWM_RATE_HT_MCS_GF_POS 10 3992 #define IWM_RATE_HT_MCS_GF_MSK (1 << IWM_RATE_HT_MCS_GF_POS) 3993 3994 #define IWM_RATE_HT_MCS_INDEX_MSK 0x3f 3995 3996 /* 3997 * Very High-throughput (VHT) rate format for bits 7:0 3998 * 3999 * 3-0: VHT MCS (0-9) 4000 * 5-4: number of streams - 1: 4001 * 0) Single stream (SISO) 4002 * 1) Dual stream (MIMO) 4003 * 2) Triple stream (MIMO) 4004 */ 4005 4006 /* Bit 4-5: (0) SISO, (1) MIMO2 (2) MIMO3 */ 4007 #define IWM_RATE_VHT_MCS_RATE_CODE_MSK 0xf 4008 #define IWM_RATE_VHT_MCS_NSS_POS 4 4009 #define IWM_RATE_VHT_MCS_NSS_MSK (3 << IWM_RATE_VHT_MCS_NSS_POS) 4010 4011 /* 4012 * Legacy OFDM rate format for bits 7:0 4013 * 4014 * 3-0: 0xD) 6 Mbps 4015 * 0xF) 9 Mbps 4016 * 0x5) 12 Mbps 4017 * 0x7) 18 Mbps 4018 * 0x9) 24 Mbps 4019 * 0xB) 36 Mbps 4020 * 0x1) 48 Mbps 4021 * 0x3) 54 Mbps 4022 * (bits 7-4 are 0) 4023 * 4024 * Legacy CCK rate format for bits 7:0: 4025 * bit 8 is 0, bit 26 is 0, bit 9 is 1 (CCK): 4026 * 4027 * 6-0: 10) 1 Mbps 4028 * 20) 2 Mbps 4029 * 55) 5.5 Mbps 4030 * 110) 11 Mbps 4031 * (bit 7 is 0) 4032 */ 4033 #define IWM_RATE_LEGACY_RATE_MSK 0xff 4034 4035 4036 /* 4037 * Bit 11-12: (0) 20MHz, (1) 40MHz, (2) 80MHz, (3) 160MHz 4038 * 0 and 1 are valid for HT and VHT, 2 and 3 only for VHT 4039 */ 4040 #define IWM_RATE_MCS_CHAN_WIDTH_POS 11 4041 #define IWM_RATE_MCS_CHAN_WIDTH_MSK (3 << IWM_RATE_MCS_CHAN_WIDTH_POS) 4042 #define IWM_RATE_MCS_CHAN_WIDTH_20 (0 << IWM_RATE_MCS_CHAN_WIDTH_POS) 4043 #define IWM_RATE_MCS_CHAN_WIDTH_40 (1 << IWM_RATE_MCS_CHAN_WIDTH_POS) 4044 #define IWM_RATE_MCS_CHAN_WIDTH_80 (2 << IWM_RATE_MCS_CHAN_WIDTH_POS) 4045 #define IWM_RATE_MCS_CHAN_WIDTH_160 (3 << IWM_RATE_MCS_CHAN_WIDTH_POS) 4046 4047 /* Bit 13: (1) Short guard interval (0.4 usec), (0) normal GI (0.8 usec) */ 4048 #define IWM_RATE_MCS_SGI_POS 13 4049 #define IWM_RATE_MCS_SGI_MSK (1 << IWM_RATE_MCS_SGI_POS) 4050 4051 /* Bit 14-16: Antenna selection (1) Ant A, (2) Ant B, (4) Ant C */ 4052 #define IWM_RATE_MCS_ANT_POS 14 4053 #define IWM_RATE_MCS_ANT_A_MSK (1 << IWM_RATE_MCS_ANT_POS) 4054 #define IWM_RATE_MCS_ANT_B_MSK (2 << IWM_RATE_MCS_ANT_POS) 4055 #define IWM_RATE_MCS_ANT_C_MSK (4 << IWM_RATE_MCS_ANT_POS) 4056 #define IWM_RATE_MCS_ANT_AB_MSK (IWM_RATE_MCS_ANT_A_MSK | \ 4057 IWM_RATE_MCS_ANT_B_MSK) 4058 #define IWM_RATE_MCS_ANT_ABC_MSK (IWM_RATE_MCS_ANT_AB_MSK | \ 4059 IWM_RATE_MCS_ANT_C_MSK) 4060 #define IWM_RATE_MCS_ANT_MSK IWM_RATE_MCS_ANT_ABC_MSK 4061 #define IWM_RATE_MCS_ANT_NUM 3 4062 4063 /* Bit 17-18: (0) SS, (1) SS*2 */ 4064 #define IWM_RATE_MCS_STBC_POS 17 4065 #define IWM_RATE_MCS_STBC_MSK (1 << IWM_RATE_MCS_STBC_POS) 4066 4067 /* Bit 19: (0) Beamforming is off, (1) Beamforming is on */ 4068 #define IWM_RATE_MCS_BF_POS 19 4069 #define IWM_RATE_MCS_BF_MSK (1 << IWM_RATE_MCS_BF_POS) 4070 4071 /* Bit 20: (0) ZLF is off, (1) ZLF is on */ 4072 #define IWM_RATE_MCS_ZLF_POS 20 4073 #define IWM_RATE_MCS_ZLF_MSK (1 << IWM_RATE_MCS_ZLF_POS) 4074 4075 /* Bit 24-25: (0) 20MHz (no dup), (1) 2x20MHz, (2) 4x20MHz, 3 8x20MHz */ 4076 #define IWM_RATE_MCS_DUP_POS 24 4077 #define IWM_RATE_MCS_DUP_MSK (3 << IWM_RATE_MCS_DUP_POS) 4078 4079 /* Bit 27: (1) LDPC enabled, (0) LDPC disabled */ 4080 #define IWM_RATE_MCS_LDPC_POS 27 4081 #define IWM_RATE_MCS_LDPC_MSK (1 << IWM_RATE_MCS_LDPC_POS) 4082 4083 4084 /* Link Quality definitions */ 4085 4086 /* # entries in rate scale table to support Tx retries */ 4087 #define IWM_LQ_MAX_RETRY_NUM 16 4088 4089 /* Link quality command flags bit fields */ 4090 4091 /* Bit 0: (0) Don't use RTS (1) Use RTS */ 4092 #define IWM_LQ_FLAG_USE_RTS_POS 0 4093 #define IWM_LQ_FLAG_USE_RTS_MSK (1 << IWM_LQ_FLAG_USE_RTS_POS) 4094 4095 /* Bit 1-3: LQ command color. Used to match responses to LQ commands */ 4096 #define IWM_LQ_FLAG_COLOR_POS 1 4097 #define IWM_LQ_FLAG_COLOR_MSK (7 << IWM_LQ_FLAG_COLOR_POS) 4098 4099 /* Bit 4-5: Tx RTS BW Signalling 4100 * (0) No RTS BW signalling 4101 * (1) Static BW signalling 4102 * (2) Dynamic BW signalling 4103 */ 4104 #define IWM_LQ_FLAG_RTS_BW_SIG_POS 4 4105 #define IWM_LQ_FLAG_RTS_BW_SIG_NONE (0 << IWM_LQ_FLAG_RTS_BW_SIG_POS) 4106 #define IWM_LQ_FLAG_RTS_BW_SIG_STATIC (1 << IWM_LQ_FLAG_RTS_BW_SIG_POS) 4107 #define IWM_LQ_FLAG_RTS_BW_SIG_DYNAMIC (2 << IWM_LQ_FLAG_RTS_BW_SIG_POS) 4108 4109 /* Bit 6: (0) No dynamic BW selection (1) Allow dynamic BW selection 4110 * Dyanmic BW selection allows Tx with narrower BW then requested in rates 4111 */ 4112 #define IWM_LQ_FLAG_DYNAMIC_BW_POS 6 4113 #define IWM_LQ_FLAG_DYNAMIC_BW_MSK (1 << IWM_LQ_FLAG_DYNAMIC_BW_POS) 4114 4115 /* Single Stream Tx Parameters (lq_cmd->ss_params) 4116 * Flags to control a smart FW decision about whether BFER/STBC/SISO will be 4117 * used for single stream Tx. 4118 */ 4119 4120 /* Bit 0-1: Max STBC streams allowed. Can be 0-3. 4121 * (0) - No STBC allowed 4122 * (1) - 2x1 STBC allowed (HT/VHT) 4123 * (2) - 4x2 STBC allowed (HT/VHT) 4124 * (3) - 3x2 STBC allowed (HT only) 4125 * All our chips are at most 2 antennas so only (1) is valid for now. 4126 */ 4127 #define IWM_LQ_SS_STBC_ALLOWED_POS 0 4128 #define IWM_LQ_SS_STBC_ALLOWED_MSK (3 << IWM_LQ_SS_STBC_ALLOWED_MSK) 4129 4130 /* 2x1 STBC is allowed */ 4131 #define IWM_LQ_SS_STBC_1SS_ALLOWED (1 << IWM_LQ_SS_STBC_ALLOWED_POS) 4132 4133 /* Bit 2: Beamformer (VHT only) is allowed */ 4134 #define IWM_LQ_SS_BFER_ALLOWED_POS 2 4135 #define IWM_LQ_SS_BFER_ALLOWED (1 << IWM_LQ_SS_BFER_ALLOWED_POS) 4136 4137 /* Bit 3: Force BFER or STBC for testing 4138 * If this is set: 4139 * If BFER is allowed then force the ucode to choose BFER else 4140 * If STBC is allowed then force the ucode to choose STBC over SISO 4141 */ 4142 #define IWM_LQ_SS_FORCE_POS 3 4143 #define IWM_LQ_SS_FORCE (1 << IWM_LQ_SS_FORCE_POS) 4144 4145 /* Bit 31: ss_params field is valid. Used for FW backward compatibility 4146 * with other drivers which don't support the ss_params API yet 4147 */ 4148 #define IWM_LQ_SS_PARAMS_VALID_POS 31 4149 #define IWM_LQ_SS_PARAMS_VALID (1 << IWM_LQ_SS_PARAMS_VALID_POS) 4150 4151 /** 4152 * struct iwm_lq_cmd - link quality command 4153 * @sta_id: station to update 4154 * @control: not used 4155 * @flags: combination of IWM_LQ_FLAG_* 4156 * @mimo_delim: the first SISO index in rs_table, which separates MIMO 4157 * and SISO rates 4158 * @single_stream_ant_msk: best antenna for SISO (can be dual in CDD). 4159 * Should be ANT_[ABC] 4160 * @dual_stream_ant_msk: best antennas for MIMO, combination of ANT_[ABC] 4161 * @initial_rate_index: first index from rs_table per AC category 4162 * @agg_time_limit: aggregation max time threshold in usec/100, meaning 4163 * value of 100 is one usec. Range is 100 to 8000 4164 * @agg_disable_start_th: try-count threshold for starting aggregation. 4165 * If a frame has higher try-count, it should not be selected for 4166 * starting an aggregation sequence. 4167 * @agg_frame_cnt_limit: max frame count in an aggregation. 4168 * 0: no limit 4169 * 1: no aggregation (one frame per aggregation) 4170 * 2 - 0x3f: maximal number of frames (up to 3f == 63) 4171 * @rs_table: array of rates for each TX try, each is rate_n_flags, 4172 * meaning it is a combination of IWM_RATE_MCS_* and IWM_RATE_*_PLCP 4173 * @ss_params: single stream features. declare whether STBC or BFER are allowed. 4174 */ 4175 struct iwm_lq_cmd { 4176 uint8_t sta_id; 4177 uint8_t reduced_tpc; 4178 uint16_t control; 4179 /* LINK_QUAL_GENERAL_PARAMS_API_S_VER_1 */ 4180 uint8_t flags; 4181 uint8_t mimo_delim; 4182 uint8_t single_stream_ant_msk; 4183 uint8_t dual_stream_ant_msk; 4184 uint8_t initial_rate_index[IWM_AC_NUM]; 4185 /* LINK_QUAL_AGG_PARAMS_API_S_VER_1 */ 4186 uint16_t agg_time_limit; 4187 uint8_t agg_disable_start_th; 4188 uint8_t agg_frame_cnt_limit; 4189 uint32_t reserved2; 4190 uint32_t rs_table[IWM_LQ_MAX_RETRY_NUM]; 4191 uint32_t ss_params; 4192 }; /* LINK_QUALITY_CMD_API_S_VER_1 */ 4193 4194 /* 4195 * END mvm/fw-api-rs.h 4196 */ 4197 4198 /* 4199 * BEGIN mvm/fw-api-tx.h 4200 */ 4201 4202 /** 4203 * enum iwm_tx_flags - bitmasks for tx_flags in TX command 4204 * @IWM_TX_CMD_FLG_PROT_REQUIRE: use RTS or CTS-to-self to protect the frame 4205 * @IWM_TX_CMD_FLG_ACK: expect ACK from receiving station 4206 * @IWM_TX_CMD_FLG_STA_RATE: use RS table with initial index from the TX command. 4207 * Otherwise, use rate_n_flags from the TX command 4208 * @IWM_TX_CMD_FLG_BA: this frame is a block ack 4209 * @IWM_TX_CMD_FLG_BAR: this frame is a BA request, immediate BAR is expected 4210 * Must set IWM_TX_CMD_FLG_ACK with this flag. 4211 * @IWM_TX_CMD_FLG_TXOP_PROT: protect frame with full TXOP protection 4212 * @IWM_TX_CMD_FLG_VHT_NDPA: mark frame is NDPA for VHT beamformer sequence 4213 * @IWM_TX_CMD_FLG_HT_NDPA: mark frame is NDPA for HT beamformer sequence 4214 * @IWM_TX_CMD_FLG_CSI_FDBK2HOST: mark to send feedback to host (only if good CRC) 4215 * @IWM_TX_CMD_FLG_BT_DIS: disable BT priority for this frame 4216 * @IWM_TX_CMD_FLG_SEQ_CTL: set if FW should override the sequence control. 4217 * Should be set for mgmt, non-QOS data, mcast, bcast and in scan command 4218 * @IWM_TX_CMD_FLG_MORE_FRAG: this frame is non-last MPDU 4219 * @IWM_TX_CMD_FLG_NEXT_FRAME: this frame includes information of the next frame 4220 * @IWM_TX_CMD_FLG_TSF: FW should calculate and insert TSF in the frame 4221 * Should be set for beacons and probe responses 4222 * @IWM_TX_CMD_FLG_CALIB: activate PA TX power calibrations 4223 * @IWM_TX_CMD_FLG_KEEP_SEQ_CTL: if seq_ctl is set, don't increase inner seq count 4224 * @IWM_TX_CMD_FLG_AGG_START: allow this frame to start aggregation 4225 * @IWM_TX_CMD_FLG_MH_PAD: driver inserted 2 byte padding after MAC header. 4226 * Should be set for 26/30 length MAC headers 4227 * @IWM_TX_CMD_FLG_RESP_TO_DRV: zero this if the response should go only to FW 4228 * @IWM_TX_CMD_FLG_TKIP_MIC_DONE: FW already performed TKIP MIC calculation 4229 * @IWM_TX_CMD_FLG_DUR: disable duration overwriting used in PS-Poll Assoc-id 4230 * @IWM_TX_CMD_FLG_FW_DROP: FW should mark frame to be dropped 4231 * @IWM_TX_CMD_FLG_EXEC_PAPD: execute PAPD 4232 * @IWM_TX_CMD_FLG_PAPD_TYPE: 0 for reference power, 1 for nominal power 4233 * @IWM_TX_CMD_FLG_HCCA_CHUNK: mark start of TSPEC chunk 4234 */ 4235 enum iwm_tx_flags { 4236 IWM_TX_CMD_FLG_PROT_REQUIRE = (1 << 0), 4237 IWM_TX_CMD_FLG_ACK = (1 << 3), 4238 IWM_TX_CMD_FLG_STA_RATE = (1 << 4), 4239 IWM_TX_CMD_FLG_BA = (1 << 5), 4240 IWM_TX_CMD_FLG_BAR = (1 << 6), 4241 IWM_TX_CMD_FLG_TXOP_PROT = (1 << 7), 4242 IWM_TX_CMD_FLG_VHT_NDPA = (1 << 8), 4243 IWM_TX_CMD_FLG_HT_NDPA = (1 << 9), 4244 IWM_TX_CMD_FLG_CSI_FDBK2HOST = (1 << 10), 4245 IWM_TX_CMD_FLG_BT_DIS = (1 << 12), 4246 IWM_TX_CMD_FLG_SEQ_CTL = (1 << 13), 4247 IWM_TX_CMD_FLG_MORE_FRAG = (1 << 14), 4248 IWM_TX_CMD_FLG_NEXT_FRAME = (1 << 15), 4249 IWM_TX_CMD_FLG_TSF = (1 << 16), 4250 IWM_TX_CMD_FLG_CALIB = (1 << 17), 4251 IWM_TX_CMD_FLG_KEEP_SEQ_CTL = (1 << 18), 4252 IWM_TX_CMD_FLG_AGG_START = (1 << 19), 4253 IWM_TX_CMD_FLG_MH_PAD = (1 << 20), 4254 IWM_TX_CMD_FLG_RESP_TO_DRV = (1 << 21), 4255 IWM_TX_CMD_FLG_TKIP_MIC_DONE = (1 << 23), 4256 IWM_TX_CMD_FLG_DUR = (1 << 25), 4257 IWM_TX_CMD_FLG_FW_DROP = (1 << 26), 4258 IWM_TX_CMD_FLG_EXEC_PAPD = (1 << 27), 4259 IWM_TX_CMD_FLG_PAPD_TYPE = (1 << 28), 4260 IWM_TX_CMD_FLG_HCCA_CHUNK = (1 << 31) 4261 }; /* IWM_TX_FLAGS_BITS_API_S_VER_1 */ 4262 4263 /** 4264 * enum iwm_tx_pm_timeouts - pm timeout values in TX command 4265 * @IWM_PM_FRAME_NONE: no need to suspend sleep mode 4266 * @IWM_PM_FRAME_MGMT: fw suspend sleep mode for 100TU 4267 * @IWM_PM_FRAME_ASSOC: fw suspend sleep mode for 10sec 4268 */ 4269 enum iwm_tx_pm_timeouts { 4270 IWM_PM_FRAME_NONE = 0, 4271 IWM_PM_FRAME_MGMT = 2, 4272 IWM_PM_FRAME_ASSOC = 3, 4273 }; 4274 4275 /* 4276 * TX command security control 4277 */ 4278 #define IWM_TX_CMD_SEC_WEP 0x01 4279 #define IWM_TX_CMD_SEC_CCM 0x02 4280 #define IWM_TX_CMD_SEC_TKIP 0x03 4281 #define IWM_TX_CMD_SEC_EXT 0x04 4282 #define IWM_TX_CMD_SEC_MSK 0x07 4283 #define IWM_TX_CMD_SEC_WEP_KEY_IDX_POS 6 4284 #define IWM_TX_CMD_SEC_WEP_KEY_IDX_MSK 0xc0 4285 #define IWM_TX_CMD_SEC_KEY128 0x08 4286 4287 /* 4288 * TX command Frame life time in us - to be written in pm_frame_timeout 4289 */ 4290 #define IWM_TX_CMD_LIFE_TIME_INFINITE 0xFFFFFFFF 4291 #define IWM_TX_CMD_LIFE_TIME_DEFAULT 2000000 /* 2000 ms*/ 4292 #define IWM_TX_CMD_LIFE_TIME_PROBE_RESP 40000 /* 40 ms */ 4293 #define IWM_TX_CMD_LIFE_TIME_EXPIRED_FRAME 0 4294 4295 /* 4296 * TID for non QoS frames - to be written in tid_tspec 4297 */ 4298 #define IWM_TID_NON_QOS IWM_MAX_TID_COUNT 4299 4300 /* 4301 * Limits on the retransmissions - to be written in {data,rts}_retry_limit 4302 */ 4303 #define IWM_DEFAULT_TX_RETRY 15 4304 #define IWM_MGMT_DFAULT_RETRY_LIMIT 3 4305 #define IWM_RTS_DFAULT_RETRY_LIMIT 60 4306 #define IWM_BAR_DFAULT_RETRY_LIMIT 60 4307 #define IWM_LOW_RETRY_LIMIT 7 4308 4309 /* TODO: complete documentation for try_cnt and btkill_cnt */ 4310 /** 4311 * struct iwm_tx_cmd - TX command struct to FW 4312 * ( IWM_TX_CMD = 0x1c ) 4313 * @len: in bytes of the payload, see below for details 4314 * @next_frame_len: same as len, but for next frame (0 if not applicable) 4315 * Used for fragmentation and bursting, but not in 11n aggregation. 4316 * @tx_flags: combination of IWM_TX_CMD_FLG_* 4317 * @rate_n_flags: rate for *all* Tx attempts, if IWM_TX_CMD_FLG_STA_RATE_MSK is 4318 * cleared. Combination of IWM_RATE_MCS_* 4319 * @sta_id: index of destination station in FW station table 4320 * @sec_ctl: security control, IWM_TX_CMD_SEC_* 4321 * @initial_rate_index: index into the rate table for initial TX attempt. 4322 * Applied if IWM_TX_CMD_FLG_STA_RATE_MSK is set, normally 0 for data frames. 4323 * @key: security key 4324 * @reserved3: reserved 4325 * @life_time: frame life time (usecs??) 4326 * @dram_lsb_ptr: Physical address of scratch area in the command (try_cnt + 4327 * btkill_cnd + reserved), first 32 bits. "0" disables usage. 4328 * @dram_msb_ptr: upper bits of the scratch physical address 4329 * @rts_retry_limit: max attempts for RTS 4330 * @data_retry_limit: max attempts to send the data packet 4331 * @tid_spec: TID/tspec 4332 * @pm_frame_timeout: PM TX frame timeout 4333 * @driver_txop: duration od EDCA TXOP, in 32-usec units. Set this if not 4334 * specified by HCCA protocol 4335 * 4336 * The byte count (both len and next_frame_len) includes MAC header 4337 * (24/26/30/32 bytes) 4338 * + 2 bytes pad if 26/30 header size 4339 * + 8 byte IV for CCM or TKIP (not used for WEP) 4340 * + Data payload 4341 * + 8-byte MIC (not used for CCM/WEP) 4342 * It does not include post-MAC padding, i.e., 4343 * MIC (CCM) 8 bytes, ICV (WEP/TKIP/CKIP) 4 bytes, CRC 4 bytes. 4344 * Range of len: 14-2342 bytes. 4345 * 4346 * After the struct fields the MAC header is placed, plus any padding, 4347 * and then the actial payload. 4348 */ 4349 struct iwm_tx_cmd { 4350 uint16_t len; 4351 uint16_t next_frame_len; 4352 uint32_t tx_flags; 4353 struct { 4354 uint8_t try_cnt; 4355 uint8_t btkill_cnt; 4356 uint16_t reserved; 4357 } scratch; /* DRAM_SCRATCH_API_U_VER_1 */ 4358 uint32_t rate_n_flags; 4359 uint8_t sta_id; 4360 uint8_t sec_ctl; 4361 uint8_t initial_rate_index; 4362 uint8_t reserved2; 4363 uint8_t key[16]; 4364 uint16_t next_frame_flags; 4365 uint16_t reserved3; 4366 uint32_t life_time; 4367 uint32_t dram_lsb_ptr; 4368 uint8_t dram_msb_ptr; 4369 uint8_t rts_retry_limit; 4370 uint8_t data_retry_limit; 4371 uint8_t tid_tspec; 4372 uint16_t pm_frame_timeout; 4373 uint16_t driver_txop; 4374 uint8_t payload[0]; 4375 struct ieee80211_frame hdr[0]; 4376 } __packed; /* IWM_TX_CMD_API_S_VER_3 */ 4377 4378 /* 4379 * TX response related data 4380 */ 4381 4382 /* 4383 * enum iwm_tx_status - status that is returned by the fw after attempts to Tx 4384 * @IWM_TX_STATUS_SUCCESS: 4385 * @IWM_TX_STATUS_DIRECT_DONE: 4386 * @IWM_TX_STATUS_POSTPONE_DELAY: 4387 * @IWM_TX_STATUS_POSTPONE_FEW_BYTES: 4388 * @IWM_TX_STATUS_POSTPONE_BT_PRIO: 4389 * @IWM_TX_STATUS_POSTPONE_QUIET_PERIOD: 4390 * @IWM_TX_STATUS_POSTPONE_CALC_TTAK: 4391 * @IWM_TX_STATUS_FAIL_INTERNAL_CROSSED_RETRY: 4392 * @IWM_TX_STATUS_FAIL_SHORT_LIMIT: 4393 * @IWM_TX_STATUS_FAIL_LONG_LIMIT: 4394 * @IWM_TX_STATUS_FAIL_UNDERRUN: 4395 * @IWM_TX_STATUS_FAIL_DRAIN_FLOW: 4396 * @IWM_TX_STATUS_FAIL_RFKILL_FLUSH: 4397 * @IWM_TX_STATUS_FAIL_LIFE_EXPIRE: 4398 * @IWM_TX_STATUS_FAIL_DEST_PS: 4399 * @IWM_TX_STATUS_FAIL_HOST_ABORTED: 4400 * @IWM_TX_STATUS_FAIL_BT_RETRY: 4401 * @IWM_TX_STATUS_FAIL_STA_INVALID: 4402 * @IWM_TX_TATUS_FAIL_FRAG_DROPPED: 4403 * @IWM_TX_STATUS_FAIL_TID_DISABLE: 4404 * @IWM_TX_STATUS_FAIL_FIFO_FLUSHED: 4405 * @IWM_TX_STATUS_FAIL_SMALL_CF_POLL: 4406 * @IWM_TX_STATUS_FAIL_FW_DROP: 4407 * @IWM_TX_STATUS_FAIL_STA_COLOR_MISMATCH: mismatch between color of Tx cmd and 4408 * STA table 4409 * @IWM_TX_FRAME_STATUS_INTERNAL_ABORT: 4410 * @IWM_TX_MODE_MSK: 4411 * @IWM_TX_MODE_NO_BURST: 4412 * @IWM_TX_MODE_IN_BURST_SEQ: 4413 * @IWM_TX_MODE_FIRST_IN_BURST: 4414 * @IWM_TX_QUEUE_NUM_MSK: 4415 * 4416 * Valid only if frame_count =1 4417 * TODO: complete documentation 4418 */ 4419 enum iwm_tx_status { 4420 IWM_TX_STATUS_MSK = 0x000000ff, 4421 IWM_TX_STATUS_SUCCESS = 0x01, 4422 IWM_TX_STATUS_DIRECT_DONE = 0x02, 4423 /* postpone TX */ 4424 IWM_TX_STATUS_POSTPONE_DELAY = 0x40, 4425 IWM_TX_STATUS_POSTPONE_FEW_BYTES = 0x41, 4426 IWM_TX_STATUS_POSTPONE_BT_PRIO = 0x42, 4427 IWM_TX_STATUS_POSTPONE_QUIET_PERIOD = 0x43, 4428 IWM_TX_STATUS_POSTPONE_CALC_TTAK = 0x44, 4429 /* abort TX */ 4430 IWM_TX_STATUS_FAIL_INTERNAL_CROSSED_RETRY = 0x81, 4431 IWM_TX_STATUS_FAIL_SHORT_LIMIT = 0x82, 4432 IWM_TX_STATUS_FAIL_LONG_LIMIT = 0x83, 4433 IWM_TX_STATUS_FAIL_UNDERRUN = 0x84, 4434 IWM_TX_STATUS_FAIL_DRAIN_FLOW = 0x85, 4435 IWM_TX_STATUS_FAIL_RFKILL_FLUSH = 0x86, 4436 IWM_TX_STATUS_FAIL_LIFE_EXPIRE = 0x87, 4437 IWM_TX_STATUS_FAIL_DEST_PS = 0x88, 4438 IWM_TX_STATUS_FAIL_HOST_ABORTED = 0x89, 4439 IWM_TX_STATUS_FAIL_BT_RETRY = 0x8a, 4440 IWM_TX_STATUS_FAIL_STA_INVALID = 0x8b, 4441 IWM_TX_STATUS_FAIL_FRAG_DROPPED = 0x8c, 4442 IWM_TX_STATUS_FAIL_TID_DISABLE = 0x8d, 4443 IWM_TX_STATUS_FAIL_FIFO_FLUSHED = 0x8e, 4444 IWM_TX_STATUS_FAIL_SMALL_CF_POLL = 0x8f, 4445 IWM_TX_STATUS_FAIL_FW_DROP = 0x90, 4446 IWM_TX_STATUS_FAIL_STA_COLOR_MISMATCH = 0x91, 4447 IWM_TX_STATUS_INTERNAL_ABORT = 0x92, 4448 IWM_TX_MODE_MSK = 0x00000f00, 4449 IWM_TX_MODE_NO_BURST = 0x00000000, 4450 IWM_TX_MODE_IN_BURST_SEQ = 0x00000100, 4451 IWM_TX_MODE_FIRST_IN_BURST = 0x00000200, 4452 IWM_TX_QUEUE_NUM_MSK = 0x0001f000, 4453 IWM_TX_NARROW_BW_MSK = 0x00060000, 4454 IWM_TX_NARROW_BW_1DIV2 = 0x00020000, 4455 IWM_TX_NARROW_BW_1DIV4 = 0x00040000, 4456 IWM_TX_NARROW_BW_1DIV8 = 0x00060000, 4457 }; 4458 4459 /* 4460 * enum iwm_tx_agg_status - TX aggregation status 4461 * @IWM_AGG_TX_STATE_STATUS_MSK: 4462 * @IWM_AGG_TX_STATE_TRANSMITTED: 4463 * @IWM_AGG_TX_STATE_UNDERRUN: 4464 * @IWM_AGG_TX_STATE_BT_PRIO: 4465 * @IWM_AGG_TX_STATE_FEW_BYTES: 4466 * @IWM_AGG_TX_STATE_ABORT: 4467 * @IWM_AGG_TX_STATE_LAST_SENT_TTL: 4468 * @IWM_AGG_TX_STATE_LAST_SENT_TRY_CNT: 4469 * @IWM_AGG_TX_STATE_LAST_SENT_BT_KILL: 4470 * @IWM_AGG_TX_STATE_SCD_QUERY: 4471 * @IWM_AGG_TX_STATE_TEST_BAD_CRC32: 4472 * @IWM_AGG_TX_STATE_RESPONSE: 4473 * @IWM_AGG_TX_STATE_DUMP_TX: 4474 * @IWM_AGG_TX_STATE_DELAY_TX: 4475 * @IWM_AGG_TX_STATE_TRY_CNT_MSK: Retry count for 1st frame in aggregation (retries 4476 * occur if tx failed for this frame when it was a member of a previous 4477 * aggregation block). If rate scaling is used, retry count indicates the 4478 * rate table entry used for all frames in the new agg. 4479 *@ IWM_AGG_TX_STATE_SEQ_NUM_MSK: Command ID and sequence number of Tx command for 4480 * this frame 4481 * 4482 * TODO: complete documentation 4483 */ 4484 enum iwm_tx_agg_status { 4485 IWM_AGG_TX_STATE_STATUS_MSK = 0x00fff, 4486 IWM_AGG_TX_STATE_TRANSMITTED = 0x000, 4487 IWM_AGG_TX_STATE_UNDERRUN = 0x001, 4488 IWM_AGG_TX_STATE_BT_PRIO = 0x002, 4489 IWM_AGG_TX_STATE_FEW_BYTES = 0x004, 4490 IWM_AGG_TX_STATE_ABORT = 0x008, 4491 IWM_AGG_TX_STATE_LAST_SENT_TTL = 0x010, 4492 IWM_AGG_TX_STATE_LAST_SENT_TRY_CNT = 0x020, 4493 IWM_AGG_TX_STATE_LAST_SENT_BT_KILL = 0x040, 4494 IWM_AGG_TX_STATE_SCD_QUERY = 0x080, 4495 IWM_AGG_TX_STATE_TEST_BAD_CRC32 = 0x0100, 4496 IWM_AGG_TX_STATE_RESPONSE = 0x1ff, 4497 IWM_AGG_TX_STATE_DUMP_TX = 0x200, 4498 IWM_AGG_TX_STATE_DELAY_TX = 0x400, 4499 IWM_AGG_TX_STATE_TRY_CNT_POS = 12, 4500 IWM_AGG_TX_STATE_TRY_CNT_MSK = 0xf << IWM_AGG_TX_STATE_TRY_CNT_POS, 4501 }; 4502 4503 #define IWM_AGG_TX_STATE_LAST_SENT_MSK (IWM_AGG_TX_STATE_LAST_SENT_TTL| \ 4504 IWM_AGG_TX_STATE_LAST_SENT_TRY_CNT| \ 4505 IWM_AGG_TX_STATE_LAST_SENT_BT_KILL) 4506 4507 /* 4508 * The mask below describes a status where we are absolutely sure that the MPDU 4509 * wasn't sent. For BA/Underrun we cannot be that sure. All we know that we've 4510 * written the bytes to the TXE, but we know nothing about what the DSP did. 4511 */ 4512 #define IWM_AGG_TX_STAT_FRAME_NOT_SENT (IWM_AGG_TX_STATE_FEW_BYTES | \ 4513 IWM_AGG_TX_STATE_ABORT | \ 4514 IWM_AGG_TX_STATE_SCD_QUERY) 4515 4516 /* 4517 * IWM_REPLY_TX = 0x1c (response) 4518 * 4519 * This response may be in one of two slightly different formats, indicated 4520 * by the frame_count field: 4521 * 4522 * 1) No aggregation (frame_count == 1). This reports Tx results for a single 4523 * frame. Multiple attempts, at various bit rates, may have been made for 4524 * this frame. 4525 * 4526 * 2) Aggregation (frame_count > 1). This reports Tx results for two or more 4527 * frames that used block-acknowledge. All frames were transmitted at 4528 * same rate. Rate scaling may have been used if first frame in this new 4529 * agg block failed in previous agg block(s). 4530 * 4531 * Note that, for aggregation, ACK (block-ack) status is not delivered 4532 * here; block-ack has not been received by the time the device records 4533 * this status. 4534 * This status relates to reasons the tx might have been blocked or aborted 4535 * within the device, rather than whether it was received successfully by 4536 * the destination station. 4537 */ 4538 4539 /** 4540 * struct iwm_agg_tx_status - per packet TX aggregation status 4541 * @status: enum iwm_tx_agg_status 4542 * @sequence: Sequence # for this frame's Tx cmd (not SSN!) 4543 */ 4544 struct iwm_agg_tx_status { 4545 uint16_t status; 4546 uint16_t sequence; 4547 } __packed; 4548 4549 /* 4550 * definitions for initial rate index field 4551 * bits [3:0] initial rate index 4552 * bits [6:4] rate table color, used for the initial rate 4553 * bit-7 invalid rate indication 4554 */ 4555 #define IWM_TX_RES_INIT_RATE_INDEX_MSK 0x0f 4556 #define IWM_TX_RES_RATE_TABLE_COLOR_MSK 0x70 4557 #define IWM_TX_RES_INV_RATE_INDEX_MSK 0x80 4558 4559 #define IWM_MVM_TX_RES_GET_TID(_ra_tid) ((_ra_tid) & 0x0f) 4560 #define IWM_MVM_TX_RES_GET_RA(_ra_tid) ((_ra_tid) >> 4) 4561 4562 /** 4563 * struct iwm_mvm_tx_resp - notifies that fw is TXing a packet 4564 * ( IWM_REPLY_TX = 0x1c ) 4565 * @frame_count: 1 no aggregation, >1 aggregation 4566 * @bt_kill_count: num of times blocked by bluetooth (unused for agg) 4567 * @failure_rts: num of failures due to unsuccessful RTS 4568 * @failure_frame: num failures due to no ACK (unused for agg) 4569 * @initial_rate: for non-agg: rate of the successful Tx. For agg: rate of the 4570 * Tx of all the batch. IWM_RATE_MCS_* 4571 * @wireless_media_time: for non-agg: RTS + CTS + frame tx attempts time + ACK. 4572 * for agg: RTS + CTS + aggregation tx time + block-ack time. 4573 * in usec. 4574 * @pa_status: tx power info 4575 * @pa_integ_res_a: tx power info 4576 * @pa_integ_res_b: tx power info 4577 * @pa_integ_res_c: tx power info 4578 * @measurement_req_id: tx power info 4579 * @tfd_info: TFD information set by the FH 4580 * @seq_ctl: sequence control from the Tx cmd 4581 * @byte_cnt: byte count from the Tx cmd 4582 * @tlc_info: TLC rate info 4583 * @ra_tid: bits [3:0] = ra, bits [7:4] = tid 4584 * @frame_ctrl: frame control 4585 * @status: for non-agg: frame status IWM_TX_STATUS_* 4586 * for agg: status of 1st frame, IWM_AGG_TX_STATE_*; other frame status fields 4587 * follow this one, up to frame_count. 4588 * 4589 * After the array of statuses comes the SSN of the SCD. Look at 4590 * %iwm_mvm_get_scd_ssn for more details. 4591 */ 4592 struct iwm_mvm_tx_resp { 4593 uint8_t frame_count; 4594 uint8_t bt_kill_count; 4595 uint8_t failure_rts; 4596 uint8_t failure_frame; 4597 uint32_t initial_rate; 4598 uint16_t wireless_media_time; 4599 4600 uint8_t pa_status; 4601 uint8_t pa_integ_res_a[3]; 4602 uint8_t pa_integ_res_b[3]; 4603 uint8_t pa_integ_res_c[3]; 4604 uint16_t measurement_req_id; 4605 uint8_t reduced_tpc; 4606 uint8_t reserved; 4607 4608 uint32_t tfd_info; 4609 uint16_t seq_ctl; 4610 uint16_t byte_cnt; 4611 uint8_t tlc_info; 4612 uint8_t ra_tid; 4613 uint16_t frame_ctrl; 4614 4615 struct iwm_agg_tx_status status; 4616 } __packed; /* IWM_TX_RSP_API_S_VER_3 */ 4617 4618 /** 4619 * struct iwm_mvm_ba_notif - notifies about reception of BA 4620 * ( IWM_BA_NOTIF = 0xc5 ) 4621 * @sta_addr_lo32: lower 32 bits of the MAC address 4622 * @sta_addr_hi16: upper 16 bits of the MAC address 4623 * @sta_id: Index of recipient (BA-sending) station in fw's station table 4624 * @tid: tid of the session 4625 * @seq_ctl: 4626 * @bitmap: the bitmap of the BA notification as seen in the air 4627 * @scd_flow: the tx queue this BA relates to 4628 * @scd_ssn: the index of the last contiguously sent packet 4629 * @txed: number of Txed frames in this batch 4630 * @txed_2_done: number of Acked frames in this batch 4631 */ 4632 struct iwm_mvm_ba_notif { 4633 uint32_t sta_addr_lo32; 4634 uint16_t sta_addr_hi16; 4635 uint16_t reserved; 4636 4637 uint8_t sta_id; 4638 uint8_t tid; 4639 uint16_t seq_ctl; 4640 uint64_t bitmap; 4641 uint16_t scd_flow; 4642 uint16_t scd_ssn; 4643 uint8_t txed; 4644 uint8_t txed_2_done; 4645 uint16_t reserved1; 4646 } __packed; 4647 4648 /* 4649 * struct iwm_mac_beacon_cmd - beacon template command 4650 * @tx: the tx commands associated with the beacon frame 4651 * @template_id: currently equal to the mac context id of the coresponding 4652 * mac. 4653 * @tim_idx: the offset of the tim IE in the beacon 4654 * @tim_size: the length of the tim IE 4655 * @frame: the template of the beacon frame 4656 */ 4657 struct iwm_mac_beacon_cmd { 4658 struct iwm_tx_cmd tx; 4659 uint32_t template_id; 4660 uint32_t tim_idx; 4661 uint32_t tim_size; 4662 struct ieee80211_frame frame[0]; 4663 } __packed; 4664 4665 struct iwm_beacon_notif { 4666 struct iwm_mvm_tx_resp beacon_notify_hdr; 4667 uint64_t tsf; 4668 uint32_t ibss_mgr_status; 4669 } __packed; 4670 4671 /** 4672 * enum iwm_dump_control - dump (flush) control flags 4673 * @IWM_DUMP_TX_FIFO_FLUSH: Dump MSDUs until the FIFO is empty 4674 * and the TFD queues are empty. 4675 */ 4676 enum iwm_dump_control { 4677 IWM_DUMP_TX_FIFO_FLUSH = (1 << 1), 4678 }; 4679 4680 /** 4681 * struct iwm_tx_path_flush_cmd -- queue/FIFO flush command 4682 * @queues_ctl: bitmap of queues to flush 4683 * @flush_ctl: control flags 4684 * @reserved: reserved 4685 */ 4686 struct iwm_tx_path_flush_cmd { 4687 uint32_t queues_ctl; 4688 uint16_t flush_ctl; 4689 uint16_t reserved; 4690 } __packed; /* IWM_TX_PATH_FLUSH_CMD_API_S_VER_1 */ 4691 4692 /** 4693 * iwm_mvm_get_scd_ssn - returns the SSN of the SCD 4694 * @tx_resp: the Tx response from the fw (agg or non-agg) 4695 * 4696 * When the fw sends an AMPDU, it fetches the MPDUs one after the other. Since 4697 * it can't know that everything will go well until the end of the AMPDU, it 4698 * can't know in advance the number of MPDUs that will be sent in the current 4699 * batch. This is why it writes the agg Tx response while it fetches the MPDUs. 4700 * Hence, it can't know in advance what the SSN of the SCD will be at the end 4701 * of the batch. This is why the SSN of the SCD is written at the end of the 4702 * whole struct at a variable offset. This function knows how to cope with the 4703 * variable offset and returns the SSN of the SCD. 4704 */ 4705 static inline uint32_t iwm_mvm_get_scd_ssn(struct iwm_mvm_tx_resp *tx_resp) 4706 { 4707 return le32_to_cpup((uint32_t *)&tx_resp->status + 4708 tx_resp->frame_count) & 0xfff; 4709 } 4710 4711 /* 4712 * END mvm/fw-api-tx.h 4713 */ 4714 4715 /* 4716 * BEGIN mvm/fw-api-scan.h 4717 */ 4718 4719 /** 4720 * struct iwm_scd_txq_cfg_cmd - New txq hw scheduler config command 4721 * @token: 4722 * @sta_id: station id 4723 * @tid: 4724 * @scd_queue: scheduler queue to confiug 4725 * @enable: 1 queue enable, 0 queue disable 4726 * @aggregate: 1 aggregated queue, 0 otherwise 4727 * @tx_fifo: %enum iwm_mvm_tx_fifo 4728 * @window: BA window size 4729 * @ssn: SSN for the BA agreement 4730 */ 4731 struct iwm_scd_txq_cfg_cmd { 4732 uint8_t token; 4733 uint8_t sta_id; 4734 uint8_t tid; 4735 uint8_t scd_queue; 4736 uint8_t enable; 4737 uint8_t aggregate; 4738 uint8_t tx_fifo; 4739 uint8_t window; 4740 uint16_t ssn; 4741 uint16_t reserved; 4742 } __packed; /* SCD_QUEUE_CFG_CMD_API_S_VER_1 */ 4743 4744 /** 4745 * struct iwm_scd_txq_cfg_rsp 4746 * @token: taken from the command 4747 * @sta_id: station id from the command 4748 * @tid: tid from the command 4749 * @scd_queue: scd_queue from the command 4750 */ 4751 struct iwm_scd_txq_cfg_rsp { 4752 uint8_t token; 4753 uint8_t sta_id; 4754 uint8_t tid; 4755 uint8_t scd_queue; 4756 } __packed; /* SCD_QUEUE_CFG_RSP_API_S_VER_1 */ 4757 4758 4759 /* Scan Commands, Responses, Notifications */ 4760 4761 /* Masks for iwm_scan_channel.type flags */ 4762 #define IWM_SCAN_CHANNEL_TYPE_ACTIVE (1 << 0) 4763 #define IWM_SCAN_CHANNEL_NSSIDS(x) (((1 << (x)) - 1) << 1) 4764 4765 /* Max number of IEs for direct SSID scans in a command */ 4766 #define IWM_PROBE_OPTION_MAX 20 4767 4768 /** 4769 * struct iwm_ssid_ie - directed scan network information element 4770 * 4771 * Up to 20 of these may appear in IWM_REPLY_SCAN_CMD, 4772 * selected by "type" bit field in struct iwm_scan_channel; 4773 * each channel may select different ssids from among the 20 entries. 4774 * SSID IEs get transmitted in reverse order of entry. 4775 */ 4776 struct iwm_ssid_ie { 4777 uint8_t id; 4778 uint8_t len; 4779 uint8_t ssid[IEEE80211_NWID_LEN]; 4780 } __packed; /* IWM_SCAN_DIRECT_SSID_IE_API_S_VER_1 */ 4781 4782 /* scan offload */ 4783 #define IWM_SCAN_MAX_BLACKLIST_LEN 64 4784 #define IWM_SCAN_SHORT_BLACKLIST_LEN 16 4785 #define IWM_SCAN_MAX_PROFILES 11 4786 #define IWM_SCAN_OFFLOAD_PROBE_REQ_SIZE 512 4787 4788 /* Default watchdog (in MS) for scheduled scan iteration */ 4789 #define IWM_SCHED_SCAN_WATCHDOG cpu_to_le16(15000) 4790 4791 #define IWM_GOOD_CRC_TH_DEFAULT cpu_to_le16(1) 4792 #define IWM_CAN_ABORT_STATUS 1 4793 4794 #define IWM_FULL_SCAN_MULTIPLIER 5 4795 #define IWM_FAST_SCHED_SCAN_ITERATIONS 3 4796 #define IWM_MAX_SCHED_SCAN_PLANS 2 4797 4798 /** 4799 * iwm_scan_schedule_lmac - schedule of scan offload 4800 * @delay: delay between iterations, in seconds. 4801 * @iterations: num of scan iterations 4802 * @full_scan_mul: number of partial scans before each full scan 4803 */ 4804 struct iwm_scan_schedule_lmac { 4805 uint16_t delay; 4806 uint8_t iterations; 4807 uint8_t full_scan_mul; 4808 } __packed; /* SCAN_SCHEDULE_API_S */ 4809 4810 /** 4811 * iwm_scan_req_tx_cmd - SCAN_REQ_TX_CMD_API_S 4812 * @tx_flags: combination of TX_CMD_FLG_* 4813 * @rate_n_flags: rate for *all* Tx attempts, if TX_CMD_FLG_STA_RATE_MSK is 4814 * cleared. Combination of RATE_MCS_* 4815 * @sta_id: index of destination station in FW station table 4816 * @reserved: for alignment and future use 4817 */ 4818 struct iwm_scan_req_tx_cmd { 4819 uint32_t tx_flags; 4820 uint32_t rate_n_flags; 4821 uint8_t sta_id; 4822 uint8_t reserved[3]; 4823 } __packed; 4824 4825 enum iwm_scan_channel_flags_lmac { 4826 IWM_UNIFIED_SCAN_CHANNEL_FULL = (1 << 27), 4827 IWM_UNIFIED_SCAN_CHANNEL_PARTIAL = (1 << 28), 4828 }; 4829 4830 /** 4831 * iwm_scan_channel_cfg_lmac - SCAN_CHANNEL_CFG_S_VER2 4832 * @flags: bits 1-20: directed scan to i'th ssid 4833 * other bits &enum iwm_scan_channel_flags_lmac 4834 * @channel_number: channel number 1-13 etc 4835 * @iter_count: scan iteration on this channel 4836 * @iter_interval: interval in seconds between iterations on one channel 4837 */ 4838 struct iwm_scan_channel_cfg_lmac { 4839 uint32_t flags; 4840 uint16_t channel_num; 4841 uint16_t iter_count; 4842 uint32_t iter_interval; 4843 } __packed; 4844 4845 /* 4846 * iwm_scan_probe_segment - PROBE_SEGMENT_API_S_VER_1 4847 * @offset: offset in the data block 4848 * @len: length of the segment 4849 */ 4850 struct iwm_scan_probe_segment { 4851 uint16_t offset; 4852 uint16_t len; 4853 } __packed; 4854 4855 /* iwm_scan_probe_req - PROBE_REQUEST_FRAME_API_S_VER_2 4856 * @mac_header: first (and common) part of the probe 4857 * @band_data: band specific data 4858 * @common_data: last (and common) part of the probe 4859 * @buf: raw data block 4860 */ 4861 struct iwm_scan_probe_req { 4862 struct iwm_scan_probe_segment mac_header; 4863 struct iwm_scan_probe_segment band_data[2]; 4864 struct iwm_scan_probe_segment common_data; 4865 uint8_t buf[IWM_SCAN_OFFLOAD_PROBE_REQ_SIZE]; 4866 } __packed; 4867 4868 enum iwm_scan_channel_flags { 4869 IWM_SCAN_CHANNEL_FLAG_EBS = (1 << 0), 4870 IWM_SCAN_CHANNEL_FLAG_EBS_ACCURATE = (1 << 1), 4871 IWM_SCAN_CHANNEL_FLAG_CACHE_ADD = (1 << 2), 4872 }; 4873 4874 /* iwm_scan_channel_opt - CHANNEL_OPTIMIZATION_API_S 4875 * @flags: enum iwm_scan_channel_flags 4876 * @non_ebs_ratio: defines the ratio of number of scan iterations where EBS is 4877 * involved. 4878 * 1 - EBS is disabled. 4879 * 2 - every second scan will be full scan(and so on). 4880 */ 4881 struct iwm_scan_channel_opt { 4882 uint16_t flags; 4883 uint16_t non_ebs_ratio; 4884 } __packed; 4885 4886 /** 4887 * iwm_mvm_lmac_scan_flags 4888 * @IWM_MVM_LMAC_SCAN_FLAG_PASS_ALL: pass all beacons and probe responses 4889 * without filtering. 4890 * @IWM_MVM_LMAC_SCAN_FLAG_PASSIVE: force passive scan on all channels 4891 * @IWM_MVM_LMAC_SCAN_FLAG_PRE_CONNECTION: single channel scan 4892 * @IWM_MVM_LMAC_SCAN_FLAG_ITER_COMPLETE: send iteration complete notification 4893 * @IWM_MVM_LMAC_SCAN_FLAG_MULTIPLE_SSIDS multiple SSID matching 4894 * @IWM_MVM_LMAC_SCAN_FLAG_FRAGMENTED: all passive scans will be fragmented 4895 * @IWM_MVM_LMAC_SCAN_FLAGS_RRM_ENABLED: insert WFA vendor-specific TPC report 4896 * and DS parameter set IEs into probe requests. 4897 * @IWM_MVM_LMAC_SCAN_FLAG_EXTENDED_DWELL: use extended dwell time on channels 4898 * 1, 6 and 11. 4899 * @IWM_MVM_LMAC_SCAN_FLAG_MATCH: Send match found notification on matches 4900 */ 4901 enum iwm_mvm_lmac_scan_flags { 4902 IWM_MVM_LMAC_SCAN_FLAG_PASS_ALL = (1 << 0), 4903 IWM_MVM_LMAC_SCAN_FLAG_PASSIVE = (1 << 1), 4904 IWM_MVM_LMAC_SCAN_FLAG_PRE_CONNECTION = (1 << 2), 4905 IWM_MVM_LMAC_SCAN_FLAG_ITER_COMPLETE = (1 << 3), 4906 IWM_MVM_LMAC_SCAN_FLAG_MULTIPLE_SSIDS = (1 << 4), 4907 IWM_MVM_LMAC_SCAN_FLAG_FRAGMENTED = (1 << 5), 4908 IWM_MVM_LMAC_SCAN_FLAGS_RRM_ENABLED = (1 << 6), 4909 IWM_MVM_LMAC_SCAN_FLAG_EXTENDED_DWELL = (1 << 7), 4910 IWM_MVM_LMAC_SCAN_FLAG_MATCH = (1 << 9), 4911 }; 4912 4913 enum iwm_scan_priority { 4914 IWM_SCAN_PRIORITY_LOW, 4915 IWM_SCAN_PRIORITY_MEDIUM, 4916 IWM_SCAN_PRIORITY_HIGH, 4917 }; 4918 4919 /** 4920 * iwm_scan_req_lmac - SCAN_REQUEST_CMD_API_S_VER_1 4921 * @reserved1: for alignment and future use 4922 * @channel_num: num of channels to scan 4923 * @active-dwell: dwell time for active channels 4924 * @passive-dwell: dwell time for passive channels 4925 * @fragmented-dwell: dwell time for fragmented passive scan 4926 * @extended_dwell: dwell time for channels 1, 6 and 11 (in certain cases) 4927 * @reserved2: for alignment and future use 4928 * @rx_chain_selct: PHY_RX_CHAIN_* flags 4929 * @scan_flags: &enum iwm_mvm_lmac_scan_flags 4930 * @max_out_time: max time (in TU) to be out of associated channel 4931 * @suspend_time: pause scan this long (TUs) when returning to service channel 4932 * @flags: RXON flags 4933 * @filter_flags: RXON filter 4934 * @tx_cmd: tx command for active scan; for 2GHz and for 5GHz 4935 * @direct_scan: list of SSIDs for directed active scan 4936 * @scan_prio: enum iwm_scan_priority 4937 * @iter_num: number of scan iterations 4938 * @delay: delay in seconds before first iteration 4939 * @schedule: two scheduling plans. The first one is finite, the second one can 4940 * be infinite. 4941 * @channel_opt: channel optimization options, for full and partial scan 4942 * @data: channel configuration and probe request packet. 4943 */ 4944 struct iwm_scan_req_lmac { 4945 /* SCAN_REQUEST_FIXED_PART_API_S_VER_7 */ 4946 uint32_t reserved1; 4947 uint8_t n_channels; 4948 uint8_t active_dwell; 4949 uint8_t passive_dwell; 4950 uint8_t fragmented_dwell; 4951 uint8_t extended_dwell; 4952 uint8_t reserved2; 4953 uint16_t rx_chain_select; 4954 uint32_t scan_flags; 4955 uint32_t max_out_time; 4956 uint32_t suspend_time; 4957 /* RX_ON_FLAGS_API_S_VER_1 */ 4958 uint32_t flags; 4959 uint32_t filter_flags; 4960 struct iwm_scan_req_tx_cmd tx_cmd[2]; 4961 struct iwm_ssid_ie direct_scan[IWM_PROBE_OPTION_MAX]; 4962 uint32_t scan_prio; 4963 /* SCAN_REQ_PERIODIC_PARAMS_API_S */ 4964 uint32_t iter_num; 4965 uint32_t delay; 4966 struct iwm_scan_schedule_lmac schedule[IWM_MAX_SCHED_SCAN_PLANS]; 4967 struct iwm_scan_channel_opt channel_opt[2]; 4968 uint8_t data[]; 4969 } __packed; 4970 4971 /** 4972 * iwm_scan_offload_complete - PERIODIC_SCAN_COMPLETE_NTF_API_S_VER_2 4973 * @last_schedule_line: last schedule line executed (fast or regular) 4974 * @last_schedule_iteration: last scan iteration executed before scan abort 4975 * @status: enum iwm_scan_offload_complete_status 4976 * @ebs_status: EBS success status &enum iwm_scan_ebs_status 4977 * @time_after_last_iter; time in seconds elapsed after last iteration 4978 */ 4979 struct iwm_periodic_scan_complete { 4980 uint8_t last_schedule_line; 4981 uint8_t last_schedule_iteration; 4982 uint8_t status; 4983 uint8_t ebs_status; 4984 uint32_t time_after_last_iter; 4985 uint32_t reserved; 4986 } __packed; 4987 4988 /** 4989 * struct iwm_scan_results_notif - scan results for one channel - 4990 * SCAN_RESULT_NTF_API_S_VER_3 4991 * @channel: which channel the results are from 4992 * @band: 0 for 5.2 GHz, 1 for 2.4 GHz 4993 * @probe_status: IWM_SCAN_PROBE_STATUS_*, indicates success of probe request 4994 * @num_probe_not_sent: # of request that weren't sent due to not enough time 4995 * @duration: duration spent in channel, in usecs 4996 */ 4997 struct iwm_scan_results_notif { 4998 uint8_t channel; 4999 uint8_t band; 5000 uint8_t probe_status; 5001 uint8_t num_probe_not_sent; 5002 uint32_t duration; 5003 } __packed; 5004 5005 enum iwm_scan_framework_client { 5006 IWM_SCAN_CLIENT_SCHED_SCAN = (1 << 0), 5007 IWM_SCAN_CLIENT_NETDETECT = (1 << 1), 5008 IWM_SCAN_CLIENT_ASSET_TRACKING = (1 << 2), 5009 }; 5010 5011 /** 5012 * iwm_scan_offload_blacklist - IWM_SCAN_OFFLOAD_BLACKLIST_S 5013 * @ssid: MAC address to filter out 5014 * @reported_rssi: AP rssi reported to the host 5015 * @client_bitmap: clients ignore this entry - enum scan_framework_client 5016 */ 5017 struct iwm_scan_offload_blacklist { 5018 uint8_t ssid[IEEE80211_ADDR_LEN]; 5019 uint8_t reported_rssi; 5020 uint8_t client_bitmap; 5021 } __packed; 5022 5023 enum iwm_scan_offload_network_type { 5024 IWM_NETWORK_TYPE_BSS = 1, 5025 IWM_NETWORK_TYPE_IBSS = 2, 5026 IWM_NETWORK_TYPE_ANY = 3, 5027 }; 5028 5029 enum iwm_scan_offload_band_selection { 5030 IWM_SCAN_OFFLOAD_SELECT_2_4 = 0x4, 5031 IWM_SCAN_OFFLOAD_SELECT_5_2 = 0x8, 5032 IWM_SCAN_OFFLOAD_SELECT_ANY = 0xc, 5033 }; 5034 5035 /** 5036 * iwm_scan_offload_profile - IWM_SCAN_OFFLOAD_PROFILE_S 5037 * @ssid_index: index to ssid list in fixed part 5038 * @unicast_cipher: encryption olgorithm to match - bitmap 5039 * @aut_alg: authentication olgorithm to match - bitmap 5040 * @network_type: enum iwm_scan_offload_network_type 5041 * @band_selection: enum iwm_scan_offload_band_selection 5042 * @client_bitmap: clients waiting for match - enum scan_framework_client 5043 */ 5044 struct iwm_scan_offload_profile { 5045 uint8_t ssid_index; 5046 uint8_t unicast_cipher; 5047 uint8_t auth_alg; 5048 uint8_t network_type; 5049 uint8_t band_selection; 5050 uint8_t client_bitmap; 5051 uint8_t reserved[2]; 5052 } __packed; 5053 5054 /** 5055 * iwm_scan_offload_profile_cfg - IWM_SCAN_OFFLOAD_PROFILES_CFG_API_S_VER_1 5056 * @blaclist: AP list to filter off from scan results 5057 * @profiles: profiles to search for match 5058 * @blacklist_len: length of blacklist 5059 * @num_profiles: num of profiles in the list 5060 * @match_notify: clients waiting for match found notification 5061 * @pass_match: clients waiting for the results 5062 * @active_clients: active clients bitmap - enum scan_framework_client 5063 * @any_beacon_notify: clients waiting for match notification without match 5064 */ 5065 struct iwm_scan_offload_profile_cfg { 5066 struct iwm_scan_offload_profile profiles[IWM_SCAN_MAX_PROFILES]; 5067 uint8_t blacklist_len; 5068 uint8_t num_profiles; 5069 uint8_t match_notify; 5070 uint8_t pass_match; 5071 uint8_t active_clients; 5072 uint8_t any_beacon_notify; 5073 uint8_t reserved[2]; 5074 } __packed; 5075 5076 enum iwm_scan_offload_complete_status { 5077 IWM_SCAN_OFFLOAD_COMPLETED = 1, 5078 IWM_SCAN_OFFLOAD_ABORTED = 2, 5079 }; 5080 5081 enum iwm_scan_ebs_status { 5082 IWM_SCAN_EBS_SUCCESS, 5083 IWM_SCAN_EBS_FAILED, 5084 IWM_SCAN_EBS_CHAN_NOT_FOUND, 5085 IWM_SCAN_EBS_INACTIVE, 5086 }; 5087 5088 /** 5089 * struct iwm_lmac_scan_complete_notif - notifies end of scanning (all channels) 5090 * SCAN_COMPLETE_NTF_API_S_VER_3 5091 * @scanned_channels: number of channels scanned (and number of valid results) 5092 * @status: one of SCAN_COMP_STATUS_* 5093 * @bt_status: BT on/off status 5094 * @last_channel: last channel that was scanned 5095 * @tsf_low: TSF timer (lower half) in usecs 5096 * @tsf_high: TSF timer (higher half) in usecs 5097 * @results: an array of scan results, only "scanned_channels" of them are valid 5098 */ 5099 struct iwm_lmac_scan_complete_notif { 5100 uint8_t scanned_channels; 5101 uint8_t status; 5102 uint8_t bt_status; 5103 uint8_t last_channel; 5104 uint32_t tsf_low; 5105 uint32_t tsf_high; 5106 struct iwm_scan_results_notif results[]; 5107 } __packed; 5108 5109 5110 /* 5111 * END mvm/fw-api-scan.h 5112 */ 5113 5114 /* 5115 * BEGIN mvm/fw-api-sta.h 5116 */ 5117 5118 /* UMAC Scan API */ 5119 5120 /* The maximum of either of these cannot exceed 8, because we use an 5121 * 8-bit mask (see IWM_MVM_SCAN_MASK). 5122 */ 5123 #define IWM_MVM_MAX_UMAC_SCANS 8 5124 #define IWM_MVM_MAX_LMAC_SCANS 1 5125 5126 enum iwm_scan_config_flags { 5127 IWM_SCAN_CONFIG_FLAG_ACTIVATE = (1 << 0), 5128 IWM_SCAN_CONFIG_FLAG_DEACTIVATE = (1 << 1), 5129 IWM_SCAN_CONFIG_FLAG_FORBID_CHUB_REQS = (1 << 2), 5130 IWM_SCAN_CONFIG_FLAG_ALLOW_CHUB_REQS = (1 << 3), 5131 IWM_SCAN_CONFIG_FLAG_SET_TX_CHAINS = (1 << 8), 5132 IWM_SCAN_CONFIG_FLAG_SET_RX_CHAINS = (1 << 9), 5133 IWM_SCAN_CONFIG_FLAG_SET_AUX_STA_ID = (1 << 10), 5134 IWM_SCAN_CONFIG_FLAG_SET_ALL_TIMES = (1 << 11), 5135 IWM_SCAN_CONFIG_FLAG_SET_EFFECTIVE_TIMES = (1 << 12), 5136 IWM_SCAN_CONFIG_FLAG_SET_CHANNEL_FLAGS = (1 << 13), 5137 IWM_SCAN_CONFIG_FLAG_SET_LEGACY_RATES = (1 << 14), 5138 IWM_SCAN_CONFIG_FLAG_SET_MAC_ADDR = (1 << 15), 5139 IWM_SCAN_CONFIG_FLAG_SET_FRAGMENTED = (1 << 16), 5140 IWM_SCAN_CONFIG_FLAG_CLEAR_FRAGMENTED = (1 << 17), 5141 IWM_SCAN_CONFIG_FLAG_SET_CAM_MODE = (1 << 18), 5142 IWM_SCAN_CONFIG_FLAG_CLEAR_CAM_MODE = (1 << 19), 5143 IWM_SCAN_CONFIG_FLAG_SET_PROMISC_MODE = (1 << 20), 5144 IWM_SCAN_CONFIG_FLAG_CLEAR_PROMISC_MODE = (1 << 21), 5145 5146 /* Bits 26-31 are for num of channels in channel_array */ 5147 #define IWM_SCAN_CONFIG_N_CHANNELS(n) ((n) << 26) 5148 }; 5149 5150 enum iwm_scan_config_rates { 5151 /* OFDM basic rates */ 5152 IWM_SCAN_CONFIG_RATE_6M = (1 << 0), 5153 IWM_SCAN_CONFIG_RATE_9M = (1 << 1), 5154 IWM_SCAN_CONFIG_RATE_12M = (1 << 2), 5155 IWM_SCAN_CONFIG_RATE_18M = (1 << 3), 5156 IWM_SCAN_CONFIG_RATE_24M = (1 << 4), 5157 IWM_SCAN_CONFIG_RATE_36M = (1 << 5), 5158 IWM_SCAN_CONFIG_RATE_48M = (1 << 6), 5159 IWM_SCAN_CONFIG_RATE_54M = (1 << 7), 5160 /* CCK basic rates */ 5161 IWM_SCAN_CONFIG_RATE_1M = (1 << 8), 5162 IWM_SCAN_CONFIG_RATE_2M = (1 << 9), 5163 IWM_SCAN_CONFIG_RATE_5M = (1 << 10), 5164 IWM_SCAN_CONFIG_RATE_11M = (1 << 11), 5165 5166 /* Bits 16-27 are for supported rates */ 5167 #define IWM_SCAN_CONFIG_SUPPORTED_RATE(rate) ((rate) << 16) 5168 }; 5169 5170 enum iwm_channel_flags { 5171 IWM_CHANNEL_FLAG_EBS = (1 << 0), 5172 IWM_CHANNEL_FLAG_ACCURATE_EBS = (1 << 1), 5173 IWM_CHANNEL_FLAG_EBS_ADD = (1 << 2), 5174 IWM_CHANNEL_FLAG_PRE_SCAN_PASSIVE2ACTIVE = (1 << 3), 5175 }; 5176 5177 /** 5178 * struct iwm_scan_config 5179 * @flags: enum scan_config_flags 5180 * @tx_chains: valid_tx antenna - ANT_* definitions 5181 * @rx_chains: valid_rx antenna - ANT_* definitions 5182 * @legacy_rates: default legacy rates - enum scan_config_rates 5183 * @out_of_channel_time: default max out of serving channel time 5184 * @suspend_time: default max suspend time 5185 * @dwell_active: default dwell time for active scan 5186 * @dwell_passive: default dwell time for passive scan 5187 * @dwell_fragmented: default dwell time for fragmented scan 5188 * @dwell_extended: default dwell time for channels 1, 6 and 11 5189 * @mac_addr: default mac address to be used in probes 5190 * @bcast_sta_id: the index of the station in the fw 5191 * @channel_flags: default channel flags - enum iwm_channel_flags 5192 * scan_config_channel_flag 5193 * @channel_array: default supported channels 5194 */ 5195 struct iwm_scan_config { 5196 uint32_t flags; 5197 uint32_t tx_chains; 5198 uint32_t rx_chains; 5199 uint32_t legacy_rates; 5200 uint32_t out_of_channel_time; 5201 uint32_t suspend_time; 5202 uint8_t dwell_active; 5203 uint8_t dwell_passive; 5204 uint8_t dwell_fragmented; 5205 uint8_t dwell_extended; 5206 uint8_t mac_addr[IEEE80211_ADDR_LEN]; 5207 uint8_t bcast_sta_id; 5208 uint8_t channel_flags; 5209 uint8_t channel_array[]; 5210 } __packed; /* SCAN_CONFIG_DB_CMD_API_S */ 5211 5212 /** 5213 * iwm_umac_scan_flags 5214 *@IWM_UMAC_SCAN_FLAG_PREEMPTIVE: scan process triggered by this scan request 5215 * can be preempted by other scan requests with higher priority. 5216 * The low priority scan will be resumed when the higher proirity scan is 5217 * completed. 5218 *@IWM_UMAC_SCAN_FLAG_START_NOTIF: notification will be sent to the driver 5219 * when scan starts. 5220 */ 5221 enum iwm_umac_scan_flags { 5222 IWM_UMAC_SCAN_FLAG_PREEMPTIVE = (1 << 0), 5223 IWM_UMAC_SCAN_FLAG_START_NOTIF = (1 << 1), 5224 }; 5225 5226 enum iwm_umac_scan_uid_offsets { 5227 IWM_UMAC_SCAN_UID_TYPE_OFFSET = 0, 5228 IWM_UMAC_SCAN_UID_SEQ_OFFSET = 8, 5229 }; 5230 5231 enum iwm_umac_scan_general_flags { 5232 IWM_UMAC_SCAN_GEN_FLAGS_PERIODIC = (1 << 0), 5233 IWM_UMAC_SCAN_GEN_FLAGS_OVER_BT = (1 << 1), 5234 IWM_UMAC_SCAN_GEN_FLAGS_PASS_ALL = (1 << 2), 5235 IWM_UMAC_SCAN_GEN_FLAGS_PASSIVE = (1 << 3), 5236 IWM_UMAC_SCAN_GEN_FLAGS_PRE_CONNECT = (1 << 4), 5237 IWM_UMAC_SCAN_GEN_FLAGS_ITER_COMPLETE = (1 << 5), 5238 IWM_UMAC_SCAN_GEN_FLAGS_MULTIPLE_SSID = (1 << 6), 5239 IWM_UMAC_SCAN_GEN_FLAGS_FRAGMENTED = (1 << 7), 5240 IWM_UMAC_SCAN_GEN_FLAGS_RRM_ENABLED = (1 << 8), 5241 IWM_UMAC_SCAN_GEN_FLAGS_MATCH = (1 << 9), 5242 IWM_UMAC_SCAN_GEN_FLAGS_EXTENDED_DWELL = (1 << 10), 5243 }; 5244 5245 /** 5246 * struct iwm_scan_channel_cfg_umac 5247 * @flags: bitmap - 0-19: directed scan to i'th ssid. 5248 * @channel_num: channel number 1-13 etc. 5249 * @iter_count: repetition count for the channel. 5250 * @iter_interval: interval between two scan iterations on one channel. 5251 */ 5252 struct iwm_scan_channel_cfg_umac { 5253 uint32_t flags; 5254 #define IWM_SCAN_CHANNEL_UMAC_NSSIDS(x) ((1 << (x)) - 1) 5255 5256 uint8_t channel_num; 5257 uint8_t iter_count; 5258 uint16_t iter_interval; 5259 } __packed; /* SCAN_CHANNEL_CFG_S_VER2 */ 5260 5261 /** 5262 * struct iwm_scan_umac_schedule 5263 * @interval: interval in seconds between scan iterations 5264 * @iter_count: num of scan iterations for schedule plan, 0xff for infinite loop 5265 * @reserved: for alignment and future use 5266 */ 5267 struct iwm_scan_umac_schedule { 5268 uint16_t interval; 5269 uint8_t iter_count; 5270 uint8_t reserved; 5271 } __packed; /* SCAN_SCHED_PARAM_API_S_VER_1 */ 5272 5273 /** 5274 * struct iwm_scan_req_umac_tail - the rest of the UMAC scan request command 5275 * parameters following channels configuration array. 5276 * @schedule: two scheduling plans. 5277 * @delay: delay in TUs before starting the first scan iteration 5278 * @reserved: for future use and alignment 5279 * @preq: probe request with IEs blocks 5280 * @direct_scan: list of SSIDs for directed active scan 5281 */ 5282 struct iwm_scan_req_umac_tail { 5283 /* SCAN_PERIODIC_PARAMS_API_S_VER_1 */ 5284 struct iwm_scan_umac_schedule schedule[IWM_MAX_SCHED_SCAN_PLANS]; 5285 uint16_t delay; 5286 uint16_t reserved; 5287 /* SCAN_PROBE_PARAMS_API_S_VER_1 */ 5288 struct iwm_scan_probe_req preq; 5289 struct iwm_ssid_ie direct_scan[IWM_PROBE_OPTION_MAX]; 5290 } __packed; 5291 5292 /** 5293 * struct iwm_scan_req_umac 5294 * @flags: &enum iwm_umac_scan_flags 5295 * @uid: scan id, &enum iwm_umac_scan_uid_offsets 5296 * @ooc_priority: out of channel priority - &enum iwm_scan_priority 5297 * @general_flags: &enum iwm_umac_scan_general_flags 5298 * @extended_dwell: dwell time for channels 1, 6 and 11 5299 * @active_dwell: dwell time for active scan 5300 * @passive_dwell: dwell time for passive scan 5301 * @fragmented_dwell: dwell time for fragmented passive scan 5302 * @max_out_time: max out of serving channel time 5303 * @suspend_time: max suspend time 5304 * @scan_priority: scan internal prioritization &enum iwm_scan_priority 5305 * @channel_flags: &enum iwm_scan_channel_flags 5306 * @n_channels: num of channels in scan request 5307 * @reserved: for future use and alignment 5308 * @data: &struct iwm_scan_channel_cfg_umac and 5309 * &struct iwm_scan_req_umac_tail 5310 */ 5311 struct iwm_scan_req_umac { 5312 uint32_t flags; 5313 uint32_t uid; 5314 uint32_t ooc_priority; 5315 /* SCAN_GENERAL_PARAMS_API_S_VER_1 */ 5316 uint32_t general_flags; 5317 uint8_t extended_dwell; 5318 uint8_t active_dwell; 5319 uint8_t passive_dwell; 5320 uint8_t fragmented_dwell; 5321 uint32_t max_out_time; 5322 uint32_t suspend_time; 5323 uint32_t scan_priority; 5324 /* SCAN_CHANNEL_PARAMS_API_S_VER_1 */ 5325 uint8_t channel_flags; 5326 uint8_t n_channels; 5327 uint16_t reserved; 5328 uint8_t data[]; 5329 } __packed; /* SCAN_REQUEST_CMD_UMAC_API_S_VER_1 */ 5330 5331 /** 5332 * struct iwm_umac_scan_abort 5333 * @uid: scan id, &enum iwm_umac_scan_uid_offsets 5334 * @flags: reserved 5335 */ 5336 struct iwm_umac_scan_abort { 5337 uint32_t uid; 5338 uint32_t flags; 5339 } __packed; /* SCAN_ABORT_CMD_UMAC_API_S_VER_1 */ 5340 5341 /** 5342 * struct iwm_umac_scan_complete 5343 * @uid: scan id, &enum iwm_umac_scan_uid_offsets 5344 * @last_schedule: last scheduling line 5345 * @last_iter: last scan iteration number 5346 * @scan status: &enum iwm_scan_offload_complete_status 5347 * @ebs_status: &enum iwm_scan_ebs_status 5348 * @time_from_last_iter: time elapsed from last iteration 5349 * @reserved: for future use 5350 */ 5351 struct iwm_umac_scan_complete { 5352 uint32_t uid; 5353 uint8_t last_schedule; 5354 uint8_t last_iter; 5355 uint8_t status; 5356 uint8_t ebs_status; 5357 uint32_t time_from_last_iter; 5358 uint32_t reserved; 5359 } __packed; /* SCAN_COMPLETE_NTF_UMAC_API_S_VER_1 */ 5360 5361 #define IWM_SCAN_OFFLOAD_MATCHING_CHANNELS_LEN 5 5362 /** 5363 * struct iwm_scan_offload_profile_match - match information 5364 * @bssid: matched bssid 5365 * @channel: channel where the match occurred 5366 * @energy: 5367 * @matching_feature: 5368 * @matching_channels: bitmap of channels that matched, referencing 5369 * the channels passed in tue scan offload request 5370 */ 5371 struct iwm_scan_offload_profile_match { 5372 uint8_t bssid[IEEE80211_ADDR_LEN]; 5373 uint16_t reserved; 5374 uint8_t channel; 5375 uint8_t energy; 5376 uint8_t matching_feature; 5377 uint8_t matching_channels[IWM_SCAN_OFFLOAD_MATCHING_CHANNELS_LEN]; 5378 } __packed; /* SCAN_OFFLOAD_PROFILE_MATCH_RESULTS_S_VER_1 */ 5379 5380 /** 5381 * struct iwm_scan_offload_profiles_query - match results query response 5382 * @matched_profiles: bitmap of matched profiles, referencing the 5383 * matches passed in the scan offload request 5384 * @last_scan_age: age of the last offloaded scan 5385 * @n_scans_done: number of offloaded scans done 5386 * @gp2_d0u: GP2 when D0U occurred 5387 * @gp2_invoked: GP2 when scan offload was invoked 5388 * @resume_while_scanning: not used 5389 * @self_recovery: obsolete 5390 * @reserved: reserved 5391 * @matches: array of match information, one for each match 5392 */ 5393 struct iwm_scan_offload_profiles_query { 5394 uint32_t matched_profiles; 5395 uint32_t last_scan_age; 5396 uint32_t n_scans_done; 5397 uint32_t gp2_d0u; 5398 uint32_t gp2_invoked; 5399 uint8_t resume_while_scanning; 5400 uint8_t self_recovery; 5401 uint16_t reserved; 5402 struct iwm_scan_offload_profile_match matches[IWM_SCAN_MAX_PROFILES]; 5403 } __packed; /* SCAN_OFFLOAD_PROFILES_QUERY_RSP_S_VER_2 */ 5404 5405 /** 5406 * struct iwm_umac_scan_iter_complete_notif - notifies end of scanning iteration 5407 * @uid: scan id, &enum iwm_umac_scan_uid_offsets 5408 * @scanned_channels: number of channels scanned and number of valid elements in 5409 * results array 5410 * @status: one of SCAN_COMP_STATUS_* 5411 * @bt_status: BT on/off status 5412 * @last_channel: last channel that was scanned 5413 * @tsf_low: TSF timer (lower half) in usecs 5414 * @tsf_high: TSF timer (higher half) in usecs 5415 * @results: array of scan results, only "scanned_channels" of them are valid 5416 */ 5417 struct iwm_umac_scan_iter_complete_notif { 5418 uint32_t uid; 5419 uint8_t scanned_channels; 5420 uint8_t status; 5421 uint8_t bt_status; 5422 uint8_t last_channel; 5423 uint32_t tsf_low; 5424 uint32_t tsf_high; 5425 struct iwm_scan_results_notif results[]; 5426 } __packed; /* SCAN_ITER_COMPLETE_NTF_UMAC_API_S_VER_1 */ 5427 5428 /* Please keep this enum *SORTED* by hex value. 5429 * Needed for binary search, otherwise a warning will be triggered. 5430 */ 5431 enum iwm_scan_subcmd_ids { 5432 IWM_GSCAN_START_CMD = 0x0, 5433 IWM_GSCAN_STOP_CMD = 0x1, 5434 IWM_GSCAN_SET_HOTLIST_CMD = 0x2, 5435 IWM_GSCAN_RESET_HOTLIST_CMD = 0x3, 5436 IWM_GSCAN_SET_SIGNIFICANT_CHANGE_CMD = 0x4, 5437 IWM_GSCAN_RESET_SIGNIFICANT_CHANGE_CMD = 0x5, 5438 IWM_GSCAN_SIGNIFICANT_CHANGE_EVENT = 0xFD, 5439 IWM_GSCAN_HOTLIST_CHANGE_EVENT = 0xFE, 5440 IWM_GSCAN_RESULTS_AVAILABLE_EVENT = 0xFF, 5441 }; 5442 5443 /* STA API */ 5444 5445 /** 5446 * enum iwm_sta_flags - flags for the ADD_STA host command 5447 * @IWM_STA_FLG_REDUCED_TX_PWR_CTRL: 5448 * @IWM_STA_FLG_REDUCED_TX_PWR_DATA: 5449 * @IWM_STA_FLG_DISABLE_TX: set if TX should be disabled 5450 * @IWM_STA_FLG_PS: set if STA is in Power Save 5451 * @IWM_STA_FLG_INVALID: set if STA is invalid 5452 * @IWM_STA_FLG_DLP_EN: Direct Link Protocol is enabled 5453 * @IWM_STA_FLG_SET_ALL_KEYS: the current key applies to all key IDs 5454 * @IWM_STA_FLG_DRAIN_FLOW: drain flow 5455 * @IWM_STA_FLG_PAN: STA is for PAN interface 5456 * @IWM_STA_FLG_CLASS_AUTH: 5457 * @IWM_STA_FLG_CLASS_ASSOC: 5458 * @IWM_STA_FLG_CLASS_MIMO_PROT: 5459 * @IWM_STA_FLG_MAX_AGG_SIZE_MSK: maximal size for A-MPDU 5460 * @IWM_STA_FLG_AGG_MPDU_DENS_MSK: maximal MPDU density for Tx aggregation 5461 * @IWM_STA_FLG_FAT_EN_MSK: support for channel width (for Tx). This flag is 5462 * initialised by driver and can be updated by fw upon reception of 5463 * action frames that can change the channel width. When cleared the fw 5464 * will send all the frames in 20MHz even when FAT channel is requested. 5465 * @IWM_STA_FLG_MIMO_EN_MSK: support for MIMO. This flag is initialised by the 5466 * driver and can be updated by fw upon reception of action frames. 5467 * @IWM_STA_FLG_MFP_EN: Management Frame Protection 5468 */ 5469 enum iwm_sta_flags { 5470 IWM_STA_FLG_REDUCED_TX_PWR_CTRL = (1 << 3), 5471 IWM_STA_FLG_REDUCED_TX_PWR_DATA = (1 << 6), 5472 5473 IWM_STA_FLG_DISABLE_TX = (1 << 4), 5474 5475 IWM_STA_FLG_PS = (1 << 8), 5476 IWM_STA_FLG_DRAIN_FLOW = (1 << 12), 5477 IWM_STA_FLG_PAN = (1 << 13), 5478 IWM_STA_FLG_CLASS_AUTH = (1 << 14), 5479 IWM_STA_FLG_CLASS_ASSOC = (1 << 15), 5480 IWM_STA_FLG_RTS_MIMO_PROT = (1 << 17), 5481 5482 IWM_STA_FLG_MAX_AGG_SIZE_SHIFT = 19, 5483 IWM_STA_FLG_MAX_AGG_SIZE_8K = (0 << IWM_STA_FLG_MAX_AGG_SIZE_SHIFT), 5484 IWM_STA_FLG_MAX_AGG_SIZE_16K = (1 << IWM_STA_FLG_MAX_AGG_SIZE_SHIFT), 5485 IWM_STA_FLG_MAX_AGG_SIZE_32K = (2 << IWM_STA_FLG_MAX_AGG_SIZE_SHIFT), 5486 IWM_STA_FLG_MAX_AGG_SIZE_64K = (3 << IWM_STA_FLG_MAX_AGG_SIZE_SHIFT), 5487 IWM_STA_FLG_MAX_AGG_SIZE_128K = (4 << IWM_STA_FLG_MAX_AGG_SIZE_SHIFT), 5488 IWM_STA_FLG_MAX_AGG_SIZE_256K = (5 << IWM_STA_FLG_MAX_AGG_SIZE_SHIFT), 5489 IWM_STA_FLG_MAX_AGG_SIZE_512K = (6 << IWM_STA_FLG_MAX_AGG_SIZE_SHIFT), 5490 IWM_STA_FLG_MAX_AGG_SIZE_1024K = (7 << IWM_STA_FLG_MAX_AGG_SIZE_SHIFT), 5491 IWM_STA_FLG_MAX_AGG_SIZE_MSK = (7 << IWM_STA_FLG_MAX_AGG_SIZE_SHIFT), 5492 5493 IWM_STA_FLG_AGG_MPDU_DENS_SHIFT = 23, 5494 IWM_STA_FLG_AGG_MPDU_DENS_2US = (4 << IWM_STA_FLG_AGG_MPDU_DENS_SHIFT), 5495 IWM_STA_FLG_AGG_MPDU_DENS_4US = (5 << IWM_STA_FLG_AGG_MPDU_DENS_SHIFT), 5496 IWM_STA_FLG_AGG_MPDU_DENS_8US = (6 << IWM_STA_FLG_AGG_MPDU_DENS_SHIFT), 5497 IWM_STA_FLG_AGG_MPDU_DENS_16US = (7 << IWM_STA_FLG_AGG_MPDU_DENS_SHIFT), 5498 IWM_STA_FLG_AGG_MPDU_DENS_MSK = (7 << IWM_STA_FLG_AGG_MPDU_DENS_SHIFT), 5499 5500 IWM_STA_FLG_FAT_EN_20MHZ = (0 << 26), 5501 IWM_STA_FLG_FAT_EN_40MHZ = (1 << 26), 5502 IWM_STA_FLG_FAT_EN_80MHZ = (2 << 26), 5503 IWM_STA_FLG_FAT_EN_160MHZ = (3 << 26), 5504 IWM_STA_FLG_FAT_EN_MSK = (3 << 26), 5505 5506 IWM_STA_FLG_MIMO_EN_SISO = (0 << 28), 5507 IWM_STA_FLG_MIMO_EN_MIMO2 = (1 << 28), 5508 IWM_STA_FLG_MIMO_EN_MIMO3 = (2 << 28), 5509 IWM_STA_FLG_MIMO_EN_MSK = (3 << 28), 5510 }; 5511 5512 /** 5513 * enum iwm_sta_key_flag - key flags for the ADD_STA host command 5514 * @IWM_STA_KEY_FLG_NO_ENC: no encryption 5515 * @IWM_STA_KEY_FLG_WEP: WEP encryption algorithm 5516 * @IWM_STA_KEY_FLG_CCM: CCMP encryption algorithm 5517 * @IWM_STA_KEY_FLG_TKIP: TKIP encryption algorithm 5518 * @IWM_STA_KEY_FLG_EXT: extended cipher algorithm (depends on the FW support) 5519 * @IWM_STA_KEY_FLG_CMAC: CMAC encryption algorithm 5520 * @IWM_STA_KEY_FLG_ENC_UNKNOWN: unknown encryption algorithm 5521 * @IWM_STA_KEY_FLG_EN_MSK: mask for encryption algorithmi value 5522 * @IWM_STA_KEY_FLG_WEP_KEY_MAP: wep is either a group key (0 - legacy WEP) or from 5523 * station info array (1 - n 1X mode) 5524 * @IWM_STA_KEY_FLG_KEYID_MSK: the index of the key 5525 * @IWM_STA_KEY_NOT_VALID: key is invalid 5526 * @IWM_STA_KEY_FLG_WEP_13BYTES: set for 13 bytes WEP key 5527 * @IWM_STA_KEY_MULTICAST: set for multical key 5528 * @IWM_STA_KEY_MFP: key is used for Management Frame Protection 5529 */ 5530 enum iwm_sta_key_flag { 5531 IWM_STA_KEY_FLG_NO_ENC = (0 << 0), 5532 IWM_STA_KEY_FLG_WEP = (1 << 0), 5533 IWM_STA_KEY_FLG_CCM = (2 << 0), 5534 IWM_STA_KEY_FLG_TKIP = (3 << 0), 5535 IWM_STA_KEY_FLG_EXT = (4 << 0), 5536 IWM_STA_KEY_FLG_CMAC = (6 << 0), 5537 IWM_STA_KEY_FLG_ENC_UNKNOWN = (7 << 0), 5538 IWM_STA_KEY_FLG_EN_MSK = (7 << 0), 5539 5540 IWM_STA_KEY_FLG_WEP_KEY_MAP = (1 << 3), 5541 IWM_STA_KEY_FLG_KEYID_POS = 8, 5542 IWM_STA_KEY_FLG_KEYID_MSK = (3 << IWM_STA_KEY_FLG_KEYID_POS), 5543 IWM_STA_KEY_NOT_VALID = (1 << 11), 5544 IWM_STA_KEY_FLG_WEP_13BYTES = (1 << 12), 5545 IWM_STA_KEY_MULTICAST = (1 << 14), 5546 IWM_STA_KEY_MFP = (1 << 15), 5547 }; 5548 5549 /** 5550 * enum iwm_sta_modify_flag - indicate to the fw what flag are being changed 5551 * @IWM_STA_MODIFY_QUEUE_REMOVAL: this command removes a queue 5552 * @IWM_STA_MODIFY_TID_DISABLE_TX: this command modifies %tid_disable_tx 5553 * @IWM_STA_MODIFY_TX_RATE: unused 5554 * @IWM_STA_MODIFY_ADD_BA_TID: this command modifies %add_immediate_ba_tid 5555 * @IWM_STA_MODIFY_REMOVE_BA_TID: this command modifies %remove_immediate_ba_tid 5556 * @IWM_STA_MODIFY_SLEEPING_STA_TX_COUNT: this command modifies %sleep_tx_count 5557 * @IWM_STA_MODIFY_PROT_TH: 5558 * @IWM_STA_MODIFY_QUEUES: modify the queues used by this station 5559 */ 5560 enum iwm_sta_modify_flag { 5561 IWM_STA_MODIFY_QUEUE_REMOVAL = (1 << 0), 5562 IWM_STA_MODIFY_TID_DISABLE_TX = (1 << 1), 5563 IWM_STA_MODIFY_TX_RATE = (1 << 2), 5564 IWM_STA_MODIFY_ADD_BA_TID = (1 << 3), 5565 IWM_STA_MODIFY_REMOVE_BA_TID = (1 << 4), 5566 IWM_STA_MODIFY_SLEEPING_STA_TX_COUNT = (1 << 5), 5567 IWM_STA_MODIFY_PROT_TH = (1 << 6), 5568 IWM_STA_MODIFY_QUEUES = (1 << 7), 5569 }; 5570 5571 #define IWM_STA_MODE_MODIFY 1 5572 5573 /** 5574 * enum iwm_sta_sleep_flag - type of sleep of the station 5575 * @IWM_STA_SLEEP_STATE_AWAKE: 5576 * @IWM_STA_SLEEP_STATE_PS_POLL: 5577 * @IWM_STA_SLEEP_STATE_UAPSD: 5578 * @IWM_STA_SLEEP_STATE_MOREDATA: set more-data bit on 5579 * (last) released frame 5580 */ 5581 enum iwm_sta_sleep_flag { 5582 IWM_STA_SLEEP_STATE_AWAKE = 0, 5583 IWM_STA_SLEEP_STATE_PS_POLL = (1 << 0), 5584 IWM_STA_SLEEP_STATE_UAPSD = (1 << 1), 5585 IWM_STA_SLEEP_STATE_MOREDATA = (1 << 2), 5586 }; 5587 5588 /* STA ID and color bits definitions */ 5589 #define IWM_STA_ID_SEED (0x0f) 5590 #define IWM_STA_ID_POS (0) 5591 #define IWM_STA_ID_MSK (IWM_STA_ID_SEED << IWM_STA_ID_POS) 5592 5593 #define IWM_STA_COLOR_SEED (0x7) 5594 #define IWM_STA_COLOR_POS (4) 5595 #define IWM_STA_COLOR_MSK (IWM_STA_COLOR_SEED << IWM_STA_COLOR_POS) 5596 5597 #define IWM_STA_ID_N_COLOR_GET_COLOR(id_n_color) \ 5598 (((id_n_color) & IWM_STA_COLOR_MSK) >> IWM_STA_COLOR_POS) 5599 #define IWM_STA_ID_N_COLOR_GET_ID(id_n_color) \ 5600 (((id_n_color) & IWM_STA_ID_MSK) >> IWM_STA_ID_POS) 5601 5602 #define IWM_STA_KEY_MAX_NUM (16) 5603 #define IWM_STA_KEY_IDX_INVALID (0xff) 5604 #define IWM_STA_KEY_MAX_DATA_KEY_NUM (4) 5605 #define IWM_MAX_GLOBAL_KEYS (4) 5606 #define IWM_STA_KEY_LEN_WEP40 (5) 5607 #define IWM_STA_KEY_LEN_WEP104 (13) 5608 5609 /** 5610 * struct iwm_mvm_keyinfo - key information 5611 * @key_flags: type %iwm_sta_key_flag 5612 * @tkip_rx_tsc_byte2: TSC[2] for key mix ph1 detection 5613 * @tkip_rx_ttak: 10-byte unicast TKIP TTAK for Rx 5614 * @key_offset: key offset in the fw's key table 5615 * @key: 16-byte unicast decryption key 5616 * @tx_secur_seq_cnt: initial RSC / PN needed for replay check 5617 * @hw_tkip_mic_rx_key: byte: MIC Rx Key - used for TKIP only 5618 * @hw_tkip_mic_tx_key: byte: MIC Tx Key - used for TKIP only 5619 */ 5620 struct iwm_mvm_keyinfo { 5621 uint16_t key_flags; 5622 uint8_t tkip_rx_tsc_byte2; 5623 uint8_t reserved1; 5624 uint16_t tkip_rx_ttak[5]; 5625 uint8_t key_offset; 5626 uint8_t reserved2; 5627 uint8_t key[16]; 5628 uint64_t tx_secur_seq_cnt; 5629 uint64_t hw_tkip_mic_rx_key; 5630 uint64_t hw_tkip_mic_tx_key; 5631 } __packed; 5632 5633 #define IWM_ADD_STA_STATUS_MASK 0xFF 5634 #define IWM_ADD_STA_BAID_VALID_MASK 0x8000 5635 #define IWM_ADD_STA_BAID_MASK 0x7F00 5636 #define IWM_ADD_STA_BAID_SHIFT 8 5637 5638 /** 5639 * struct iwm_mvm_add_sta_cmd - Add/modify a station in the fw's sta table. 5640 * ( REPLY_ADD_STA = 0x18 ) 5641 * @add_modify: 1: modify existing, 0: add new station 5642 * @awake_acs: 5643 * @tid_disable_tx: is tid BIT(tid) enabled for Tx. Clear BIT(x) to enable 5644 * AMPDU for tid x. Set %IWM_STA_MODIFY_TID_DISABLE_TX to change this field. 5645 * @mac_id_n_color: the Mac context this station belongs to 5646 * @addr[IEEE80211_ADDR_LEN]: station's MAC address 5647 * @sta_id: index of station in uCode's station table 5648 * @modify_mask: IWM_STA_MODIFY_*, selects which parameters to modify vs. leave 5649 * alone. 1 - modify, 0 - don't change. 5650 * @station_flags: look at %iwm_sta_flags 5651 * @station_flags_msk: what of %station_flags have changed 5652 * @add_immediate_ba_tid: tid for which to add block-ack support (Rx) 5653 * Set %IWM_STA_MODIFY_ADD_BA_TID to use this field, and also set 5654 * add_immediate_ba_ssn. 5655 * @remove_immediate_ba_tid: tid for which to remove block-ack support (Rx) 5656 * Set %IWM_STA_MODIFY_REMOVE_BA_TID to use this field 5657 * @add_immediate_ba_ssn: ssn for the Rx block-ack session. Used together with 5658 * add_immediate_ba_tid. 5659 * @sleep_tx_count: number of packets to transmit to station even though it is 5660 * asleep. Used to synchronise PS-poll and u-APSD responses while ucode 5661 * keeps track of STA sleep state. 5662 * @sleep_state_flags: Look at %iwm_sta_sleep_flag. 5663 * @assoc_id: assoc_id to be sent in VHT PLCP (9-bit), for grp use 0, for AP 5664 * mac-addr. 5665 * @beamform_flags: beam forming controls 5666 * @tfd_queue_msk: tfd queues used by this station 5667 * 5668 * The device contains an internal table of per-station information, with info 5669 * on security keys, aggregation parameters, and Tx rates for initial Tx 5670 * attempt and any retries (set by IWM_REPLY_TX_LINK_QUALITY_CMD). 5671 * 5672 * ADD_STA sets up the table entry for one station, either creating a new 5673 * entry, or modifying a pre-existing one. 5674 */ 5675 struct iwm_mvm_add_sta_cmd { 5676 uint8_t add_modify; 5677 uint8_t awake_acs; 5678 uint16_t tid_disable_tx; 5679 uint32_t mac_id_n_color; 5680 uint8_t addr[IEEE80211_ADDR_LEN]; /* _STA_ID_MODIFY_INFO_API_S_VER_1 */ 5681 uint16_t reserved2; 5682 uint8_t sta_id; 5683 uint8_t modify_mask; 5684 uint16_t reserved3; 5685 uint32_t station_flags; 5686 uint32_t station_flags_msk; 5687 uint8_t add_immediate_ba_tid; 5688 uint8_t remove_immediate_ba_tid; 5689 uint16_t add_immediate_ba_ssn; 5690 uint16_t sleep_tx_count; 5691 uint16_t sleep_state_flags; 5692 uint16_t assoc_id; 5693 uint16_t beamform_flags; 5694 uint32_t tfd_queue_msk; 5695 } __packed; /* ADD_STA_CMD_API_S_VER_7 */ 5696 5697 /** 5698 * struct iwm_mvm_add_sta_key_cmd - add/modify sta key 5699 * ( IWM_REPLY_ADD_STA_KEY = 0x17 ) 5700 * @sta_id: index of station in uCode's station table 5701 * @key_offset: key offset in key storage 5702 * @key_flags: type %iwm_sta_key_flag 5703 * @key: key material data 5704 * @key2: key material data 5705 * @rx_secur_seq_cnt: RX security sequence counter for the key 5706 * @tkip_rx_tsc_byte2: TSC[2] for key mix ph1 detection 5707 * @tkip_rx_ttak: 10-byte unicast TKIP TTAK for Rx 5708 */ 5709 struct iwm_mvm_add_sta_key_cmd { 5710 uint8_t sta_id; 5711 uint8_t key_offset; 5712 uint16_t key_flags; 5713 uint8_t key[16]; 5714 uint8_t key2[16]; 5715 uint8_t rx_secur_seq_cnt[16]; 5716 uint8_t tkip_rx_tsc_byte2; 5717 uint8_t reserved; 5718 uint16_t tkip_rx_ttak[5]; 5719 } __packed; /* IWM_ADD_MODIFY_STA_KEY_API_S_VER_1 */ 5720 5721 /** 5722 * enum iwm_mvm_add_sta_rsp_status - status in the response to ADD_STA command 5723 * @IWM_ADD_STA_SUCCESS: operation was executed successfully 5724 * @IWM_ADD_STA_STATIONS_OVERLOAD: no room left in the fw's station table 5725 * @IWM_ADD_STA_IMMEDIATE_BA_FAILURE: can't add Rx block ack session 5726 * @IWM_ADD_STA_MODIFY_NON_EXISTING_STA: driver requested to modify a station 5727 * that doesn't exist. 5728 */ 5729 enum iwm_mvm_add_sta_rsp_status { 5730 IWM_ADD_STA_SUCCESS = 0x1, 5731 IWM_ADD_STA_STATIONS_OVERLOAD = 0x2, 5732 IWM_ADD_STA_IMMEDIATE_BA_FAILURE = 0x4, 5733 IWM_ADD_STA_MODIFY_NON_EXISTING_STA = 0x8, 5734 }; 5735 5736 /** 5737 * struct iwm_mvm_rm_sta_cmd - Add / modify a station in the fw's station table 5738 * ( IWM_REMOVE_STA = 0x19 ) 5739 * @sta_id: the station id of the station to be removed 5740 */ 5741 struct iwm_mvm_rm_sta_cmd { 5742 uint8_t sta_id; 5743 uint8_t reserved[3]; 5744 } __packed; /* IWM_REMOVE_STA_CMD_API_S_VER_2 */ 5745 5746 /** 5747 * struct iwm_mvm_mgmt_mcast_key_cmd 5748 * ( IWM_MGMT_MCAST_KEY = 0x1f ) 5749 * @ctrl_flags: %iwm_sta_key_flag 5750 * @IGTK: 5751 * @K1: IGTK master key 5752 * @K2: IGTK sub key 5753 * @sta_id: station ID that support IGTK 5754 * @key_id: 5755 * @receive_seq_cnt: initial RSC/PN needed for replay check 5756 */ 5757 struct iwm_mvm_mgmt_mcast_key_cmd { 5758 uint32_t ctrl_flags; 5759 uint8_t IGTK[16]; 5760 uint8_t K1[16]; 5761 uint8_t K2[16]; 5762 uint32_t key_id; 5763 uint32_t sta_id; 5764 uint64_t receive_seq_cnt; 5765 } __packed; /* SEC_MGMT_MULTICAST_KEY_CMD_API_S_VER_1 */ 5766 5767 struct iwm_mvm_wep_key { 5768 uint8_t key_index; 5769 uint8_t key_offset; 5770 uint16_t reserved1; 5771 uint8_t key_size; 5772 uint8_t reserved2[3]; 5773 uint8_t key[16]; 5774 } __packed; 5775 5776 struct iwm_mvm_wep_key_cmd { 5777 uint32_t mac_id_n_color; 5778 uint8_t num_keys; 5779 uint8_t decryption_type; 5780 uint8_t flags; 5781 uint8_t reserved; 5782 struct iwm_mvm_wep_key wep_key[0]; 5783 } __packed; /* SEC_CURR_WEP_KEY_CMD_API_S_VER_2 */ 5784 5785 /* 5786 * END mvm/fw-api-sta.h 5787 */ 5788 5789 /* 5790 * BT coex 5791 */ 5792 5793 enum iwm_bt_coex_mode { 5794 IWM_BT_COEX_DISABLE = 0x0, 5795 IWM_BT_COEX_NW = 0x1, 5796 IWM_BT_COEX_BT = 0x2, 5797 IWM_BT_COEX_WIFI = 0x3, 5798 }; /* BT_COEX_MODES_E */ 5799 5800 enum iwm_bt_coex_enabled_modules { 5801 IWM_BT_COEX_MPLUT_ENABLED = (1 << 0), 5802 IWM_BT_COEX_MPLUT_BOOST_ENABLED = (1 << 1), 5803 IWM_BT_COEX_SYNC2SCO_ENABLED = (1 << 2), 5804 IWM_BT_COEX_CORUN_ENABLED = (1 << 3), 5805 IWM_BT_COEX_HIGH_BAND_RET = (1 << 4), 5806 }; /* BT_COEX_MODULES_ENABLE_E_VER_1 */ 5807 5808 /** 5809 * struct iwm_bt_coex_cmd - bt coex configuration command 5810 * @mode: enum %iwm_bt_coex_mode 5811 * @enabled_modules: enum %iwm_bt_coex_enabled_modules 5812 * 5813 * The structure is used for the BT_COEX command. 5814 */ 5815 struct iwm_bt_coex_cmd { 5816 uint32_t mode; 5817 uint32_t enabled_modules; 5818 } __packed; /* BT_COEX_CMD_API_S_VER_6 */ 5819 5820 5821 /* 5822 * Location Aware Regulatory (LAR) API - MCC updates 5823 */ 5824 5825 /** 5826 * struct iwm_mcc_update_cmd_v1 - Request the device to update geographic 5827 * regulatory profile according to the given MCC (Mobile Country Code). 5828 * The MCC is two letter-code, ascii upper case[A-Z] or '00' for world domain. 5829 * 'ZZ' MCC will be used to switch to NVM default profile; in this case, the 5830 * MCC in the cmd response will be the relevant MCC in the NVM. 5831 * @mcc: given mobile country code 5832 * @source_id: the source from where we got the MCC, see iwm_mcc_source 5833 * @reserved: reserved for alignment 5834 */ 5835 struct iwm_mcc_update_cmd_v1 { 5836 uint16_t mcc; 5837 uint8_t source_id; 5838 uint8_t reserved; 5839 } __packed; /* LAR_UPDATE_MCC_CMD_API_S_VER_1 */ 5840 5841 /** 5842 * struct iwm_mcc_update_cmd - Request the device to update geographic 5843 * regulatory profile according to the given MCC (Mobile Country Code). 5844 * The MCC is two letter-code, ascii upper case[A-Z] or '00' for world domain. 5845 * 'ZZ' MCC will be used to switch to NVM default profile; in this case, the 5846 * MCC in the cmd response will be the relevant MCC in the NVM. 5847 * @mcc: given mobile country code 5848 * @source_id: the source from where we got the MCC, see iwm_mcc_source 5849 * @reserved: reserved for alignment 5850 * @key: integrity key for MCC API OEM testing 5851 * @reserved2: reserved 5852 */ 5853 struct iwm_mcc_update_cmd { 5854 uint16_t mcc; 5855 uint8_t source_id; 5856 uint8_t reserved; 5857 uint32_t key; 5858 uint32_t reserved2[5]; 5859 } __packed; /* LAR_UPDATE_MCC_CMD_API_S_VER_2 */ 5860 5861 /** 5862 * iwm_mcc_update_resp_v1 - response to MCC_UPDATE_CMD. 5863 * Contains the new channel control profile map, if changed, and the new MCC 5864 * (mobile country code). 5865 * The new MCC may be different than what was requested in MCC_UPDATE_CMD. 5866 * @status: see &enum iwm_mcc_update_status 5867 * @mcc: the new applied MCC 5868 * @cap: capabilities for all channels which matches the MCC 5869 * @source_id: the MCC source, see iwm_mcc_source 5870 * @n_channels: number of channels in @channels_data (may be 14, 39, 50 or 51 5871 * channels, depending on platform) 5872 * @channels: channel control data map, DWORD for each channel. Only the first 5873 * 16bits are used. 5874 */ 5875 struct iwm_mcc_update_resp_v1 { 5876 uint32_t status; 5877 uint16_t mcc; 5878 uint8_t cap; 5879 uint8_t source_id; 5880 uint32_t n_channels; 5881 uint32_t channels[0]; 5882 } __packed; /* LAR_UPDATE_MCC_CMD_RESP_S_VER_1 */ 5883 5884 /** 5885 * iwm_mcc_update_resp - response to MCC_UPDATE_CMD. 5886 * Contains the new channel control profile map, if changed, and the new MCC 5887 * (mobile country code). 5888 * The new MCC may be different than what was requested in MCC_UPDATE_CMD. 5889 * @status: see &enum iwm_mcc_update_status 5890 * @mcc: the new applied MCC 5891 * @cap: capabilities for all channels which matches the MCC 5892 * @source_id: the MCC source, see iwm_mcc_source 5893 * @time: time elapsed from the MCC test start (in 30 seconds TU) 5894 * @reserved: reserved. 5895 * @n_channels: number of channels in @channels_data (may be 14, 39, 50 or 51 5896 * channels, depending on platform) 5897 * @channels: channel control data map, DWORD for each channel. Only the first 5898 * 16bits are used. 5899 */ 5900 struct iwm_mcc_update_resp { 5901 uint32_t status; 5902 uint16_t mcc; 5903 uint8_t cap; 5904 uint8_t source_id; 5905 uint16_t time; 5906 uint16_t reserved; 5907 uint32_t n_channels; 5908 uint32_t channels[0]; 5909 } __packed; /* LAR_UPDATE_MCC_CMD_RESP_S_VER_2 */ 5910 5911 /** 5912 * struct iwm_mcc_chub_notif - chub notifies of mcc change 5913 * (MCC_CHUB_UPDATE_CMD = 0xc9) 5914 * The Chub (Communication Hub, CommsHUB) is a HW component that connects to 5915 * the cellular and connectivity cores that gets updates of the mcc, and 5916 * notifies the ucode directly of any mcc change. 5917 * The ucode requests the driver to request the device to update geographic 5918 * regulatory profile according to the given MCC (Mobile Country Code). 5919 * The MCC is two letter-code, ascii upper case[A-Z] or '00' for world domain. 5920 * 'ZZ' MCC will be used to switch to NVM default profile; in this case, the 5921 * MCC in the cmd response will be the relevant MCC in the NVM. 5922 * @mcc: given mobile country code 5923 * @source_id: identity of the change originator, see iwm_mcc_source 5924 * @reserved1: reserved for alignment 5925 */ 5926 struct iwm_mcc_chub_notif { 5927 uint16_t mcc; 5928 uint8_t source_id; 5929 uint8_t reserved1; 5930 } __packed; /* LAR_MCC_NOTIFY_S */ 5931 5932 enum iwm_mcc_update_status { 5933 IWM_MCC_RESP_NEW_CHAN_PROFILE, 5934 IWM_MCC_RESP_SAME_CHAN_PROFILE, 5935 IWM_MCC_RESP_INVALID, 5936 IWM_MCC_RESP_NVM_DISABLED, 5937 IWM_MCC_RESP_ILLEGAL, 5938 IWM_MCC_RESP_LOW_PRIORITY, 5939 IWM_MCC_RESP_TEST_MODE_ACTIVE, 5940 IWM_MCC_RESP_TEST_MODE_NOT_ACTIVE, 5941 IWM_MCC_RESP_TEST_MODE_DENIAL_OF_SERVICE, 5942 }; 5943 5944 enum iwm_mcc_source { 5945 IWM_MCC_SOURCE_OLD_FW = 0, 5946 IWM_MCC_SOURCE_ME = 1, 5947 IWM_MCC_SOURCE_BIOS = 2, 5948 IWM_MCC_SOURCE_3G_LTE_HOST = 3, 5949 IWM_MCC_SOURCE_3G_LTE_DEVICE = 4, 5950 IWM_MCC_SOURCE_WIFI = 5, 5951 IWM_MCC_SOURCE_RESERVED = 6, 5952 IWM_MCC_SOURCE_DEFAULT = 7, 5953 IWM_MCC_SOURCE_UNINITIALIZED = 8, 5954 IWM_MCC_SOURCE_MCC_API = 9, 5955 IWM_MCC_SOURCE_GET_CURRENT = 0x10, 5956 IWM_MCC_SOURCE_GETTING_MCC_TEST_MODE = 0x11, 5957 }; 5958 5959 /** 5960 * struct iwm_dts_measurement_notif_v1 - measurements notification 5961 * 5962 * @temp: the measured temperature 5963 * @voltage: the measured voltage 5964 */ 5965 struct iwm_dts_measurement_notif_v1 { 5966 int32_t temp; 5967 int32_t voltage; 5968 } __packed; /* TEMPERATURE_MEASUREMENT_TRIGGER_NTFY_S_VER_1*/ 5969 5970 /** 5971 * struct iwm_dts_measurement_notif_v2 - measurements notification 5972 * 5973 * @temp: the measured temperature 5974 * @voltage: the measured voltage 5975 * @threshold_idx: the trip index that was crossed 5976 */ 5977 struct iwm_dts_measurement_notif_v2 { 5978 int32_t temp; 5979 int32_t voltage; 5980 int32_t threshold_idx; 5981 } __packed; /* TEMPERATURE_MEASUREMENT_TRIGGER_NTFY_S_VER_2 */ 5982 5983 /* 5984 * Some cherry-picked definitions 5985 */ 5986 5987 #define IWM_FRAME_LIMIT 64 5988 5989 /* 5990 * These functions retrieve specific information from the id field in 5991 * the iwm_host_cmd struct which contains the command id, the group id, 5992 * and the version of the command and vice versa. 5993 */ 5994 static inline uint8_t 5995 iwm_cmd_opcode(uint32_t cmdid) 5996 { 5997 return cmdid & 0xff; 5998 } 5999 6000 static inline uint8_t 6001 iwm_cmd_groupid(uint32_t cmdid) 6002 { 6003 return ((cmdid & 0xff00) >> 8); 6004 } 6005 6006 static inline uint8_t 6007 iwm_cmd_version(uint32_t cmdid) 6008 { 6009 return ((cmdid & 0xff0000) >> 16); 6010 } 6011 6012 static inline uint32_t 6013 iwm_cmd_id(uint8_t opcode, uint8_t groupid, uint8_t version) 6014 { 6015 return opcode + (groupid << 8) + (version << 16); 6016 } 6017 6018 /* make uint16_t wide id out of uint8_t group and opcode */ 6019 #define IWM_WIDE_ID(grp, opcode) ((grp << 8) | opcode) 6020 6021 /* due to the conversion, this group is special */ 6022 #define IWM_ALWAYS_LONG_GROUP 1 6023 6024 struct iwm_cmd_header { 6025 uint8_t code; 6026 uint8_t flags; 6027 uint8_t idx; 6028 uint8_t qid; 6029 } __packed; 6030 6031 struct iwm_cmd_header_wide { 6032 uint8_t opcode; 6033 uint8_t group_id; 6034 uint8_t idx; 6035 uint8_t qid; 6036 uint16_t length; 6037 uint8_t reserved; 6038 uint8_t version; 6039 } __packed; 6040 6041 /** 6042 * enum iwm_power_scheme 6043 * @IWM_POWER_LEVEL_CAM - Continuously Active Mode 6044 * @IWM_POWER_LEVEL_BPS - Balanced Power Save (default) 6045 * @IWM_POWER_LEVEL_LP - Low Power 6046 */ 6047 enum iwm_power_scheme { 6048 IWM_POWER_SCHEME_CAM = 1, 6049 IWM_POWER_SCHEME_BPS, 6050 IWM_POWER_SCHEME_LP 6051 }; 6052 6053 #define IWM_DEF_CMD_PAYLOAD_SIZE 320 6054 #define IWM_MAX_CMD_PAYLOAD_SIZE ((4096 - 4) - sizeof(struct iwm_cmd_header)) 6055 #define IWM_CMD_FAILED_MSK 0x40 6056 6057 /** 6058 * struct iwm_device_cmd 6059 * 6060 * For allocation of the command and tx queues, this establishes the overall 6061 * size of the largest command we send to uCode, except for commands that 6062 * aren't fully copied and use other TFD space. 6063 */ 6064 struct iwm_device_cmd { 6065 union { 6066 struct { 6067 struct iwm_cmd_header hdr; 6068 uint8_t data[IWM_DEF_CMD_PAYLOAD_SIZE]; 6069 }; 6070 struct { 6071 struct iwm_cmd_header_wide hdr_wide; 6072 uint8_t data_wide[IWM_DEF_CMD_PAYLOAD_SIZE - 6073 sizeof(struct iwm_cmd_header_wide) + 6074 sizeof(struct iwm_cmd_header)]; 6075 }; 6076 }; 6077 } __packed; 6078 6079 struct iwm_rx_packet { 6080 /* 6081 * The first 4 bytes of the RX frame header contain both the RX frame 6082 * size and some flags. 6083 * Bit fields: 6084 * 31: flag flush RB request 6085 * 30: flag ignore TC (terminal counter) request 6086 * 29: flag fast IRQ request 6087 * 28-14: Reserved 6088 * 13-00: RX frame size 6089 */ 6090 uint32_t len_n_flags; 6091 struct iwm_cmd_header hdr; 6092 uint8_t data[]; 6093 } __packed; 6094 6095 #define IWM_FH_RSCSR_FRAME_SIZE_MSK 0x00003fff 6096 #define IWM_FH_RSCSR_FRAME_INVALID 0x55550000 6097 #define IWM_FH_RSCSR_FRAME_ALIGN 0x40 6098 6099 static inline uint32_t 6100 iwm_rx_packet_len(const struct iwm_rx_packet *pkt) 6101 { 6102 6103 return le32toh(pkt->len_n_flags) & IWM_FH_RSCSR_FRAME_SIZE_MSK; 6104 } 6105 6106 static inline uint32_t 6107 iwm_rx_packet_payload_len(const struct iwm_rx_packet *pkt) 6108 { 6109 6110 return iwm_rx_packet_len(pkt) - sizeof(pkt->hdr); 6111 } 6112 6113 6114 #define IWM_MIN_DBM -100 6115 #define IWM_MAX_DBM -33 /* realistic guess */ 6116 6117 #define IWM_READ(sc, reg) \ 6118 bus_space_read_4((sc)->sc_st, (sc)->sc_sh, (reg)) 6119 6120 #define IWM_WRITE(sc, reg, val) \ 6121 bus_space_write_4((sc)->sc_st, (sc)->sc_sh, (reg), (val)) 6122 6123 #define IWM_WRITE_1(sc, reg, val) \ 6124 bus_space_write_1((sc)->sc_st, (sc)->sc_sh, (reg), (val)) 6125 6126 #define IWM_SETBITS(sc, reg, mask) \ 6127 IWM_WRITE(sc, reg, IWM_READ(sc, reg) | (mask)) 6128 6129 #define IWM_CLRBITS(sc, reg, mask) \ 6130 IWM_WRITE(sc, reg, IWM_READ(sc, reg) & ~(mask)) 6131 6132 #define IWM_BARRIER_WRITE(sc) \ 6133 bus_space_barrier((sc)->sc_st, (sc)->sc_sh, 0, (sc)->sc_sz, \ 6134 BUS_SPACE_BARRIER_WRITE) 6135 6136 #define IWM_BARRIER_READ_WRITE(sc) \ 6137 bus_space_barrier((sc)->sc_st, (sc)->sc_sh, 0, (sc)->sc_sz, \ 6138 BUS_SPACE_BARRIER_READ | BUS_SPACE_BARRIER_WRITE) 6139 6140 #endif /* __IF_IWM_REG_H__ */ 6141