1 /* $OpenBSD: if_iwm.c,v 1.39 2015/03/23 00:35:19 jsg Exp $ */ 2 3 /* 4 * Copyright (c) 2014 genua mbh <info@genua.de> 5 * Copyright (c) 2014 Fixup Software Ltd. 6 * 7 * Permission to use, copy, modify, and distribute this software for any 8 * purpose with or without fee is hereby granted, provided that the above 9 * copyright notice and this permission notice appear in all copies. 10 * 11 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 12 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 13 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR 14 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 15 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN 16 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF 17 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 18 */ 19 20 /*- 21 * Based on BSD-licensed source modules in the Linux iwlwifi driver, 22 * which were used as the reference documentation for this implementation. 23 * 24 * Driver version we are currently based off of is 25 * Linux 3.14.3 (tag id a2df521e42b1d9a23f620ac79dbfe8655a8391dd) 26 * 27 *********************************************************************** 28 * 29 * This file is provided under a dual BSD/GPLv2 license. When using or 30 * redistributing this file, you may do so under either license. 31 * 32 * GPL LICENSE SUMMARY 33 * 34 * Copyright(c) 2007 - 2013 Intel Corporation. All rights reserved. 35 * 36 * This program is free software; you can redistribute it and/or modify 37 * it under the terms of version 2 of the GNU General Public License as 38 * published by the Free Software Foundation. 39 * 40 * This program is distributed in the hope that it will be useful, but 41 * WITHOUT ANY WARRANTY; without even the implied warranty of 42 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU 43 * General Public License for more details. 44 * 45 * You should have received a copy of the GNU General Public License 46 * along with this program; if not, write to the Free Software 47 * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110, 48 * USA 49 * 50 * The full GNU General Public License is included in this distribution 51 * in the file called COPYING. 52 * 53 * Contact Information: 54 * Intel Linux Wireless <ilw@linux.intel.com> 55 * Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497 56 * 57 * 58 * BSD LICENSE 59 * 60 * Copyright(c) 2005 - 2013 Intel Corporation. All rights reserved. 61 * All rights reserved. 62 * 63 * Redistribution and use in source and binary forms, with or without 64 * modification, are permitted provided that the following conditions 65 * are met: 66 * 67 * * Redistributions of source code must retain the above copyright 68 * notice, this list of conditions and the following disclaimer. 69 * * Redistributions in binary form must reproduce the above copyright 70 * notice, this list of conditions and the following disclaimer in 71 * the documentation and/or other materials provided with the 72 * distribution. 73 * * Neither the name Intel Corporation nor the names of its 74 * contributors may be used to endorse or promote products derived 75 * from this software without specific prior written permission. 76 * 77 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 78 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 79 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 80 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 81 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 82 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 83 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 84 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 85 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 86 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 87 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 88 */ 89 90 /*- 91 * Copyright (c) 2007-2010 Damien Bergamini <damien.bergamini@free.fr> 92 * 93 * Permission to use, copy, modify, and distribute this software for any 94 * purpose with or without fee is hereby granted, provided that the above 95 * copyright notice and this permission notice appear in all copies. 96 * 97 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 98 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 99 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR 100 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 101 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN 102 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF 103 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 104 */ 105 #include <sys/cdefs.h> 106 __FBSDID("$FreeBSD$"); 107 108 #include <sys/param.h> 109 #include <sys/bus.h> 110 #include <sys/conf.h> 111 #include <sys/endian.h> 112 #include <sys/firmware.h> 113 #include <sys/kernel.h> 114 #include <sys/malloc.h> 115 #include <sys/mbuf.h> 116 #include <sys/mutex.h> 117 #include <sys/module.h> 118 #include <sys/proc.h> 119 #include <sys/rman.h> 120 #include <sys/socket.h> 121 #include <sys/sockio.h> 122 #include <sys/sysctl.h> 123 #include <sys/linker.h> 124 125 #include <machine/bus.h> 126 #include <machine/endian.h> 127 #include <machine/resource.h> 128 129 #include <dev/pci/pcivar.h> 130 #include <dev/pci/pcireg.h> 131 132 #include <net/bpf.h> 133 134 #include <net/if.h> 135 #include <net/if_var.h> 136 #include <net/if_arp.h> 137 #include <net/if_dl.h> 138 #include <net/if_media.h> 139 #include <net/if_types.h> 140 141 #include <netinet/in.h> 142 #include <netinet/in_systm.h> 143 #include <netinet/if_ether.h> 144 #include <netinet/ip.h> 145 146 #include <net80211/ieee80211_var.h> 147 #include <net80211/ieee80211_regdomain.h> 148 #include <net80211/ieee80211_ratectl.h> 149 #include <net80211/ieee80211_radiotap.h> 150 151 #include <dev/iwm/if_iwmreg.h> 152 #include <dev/iwm/if_iwmvar.h> 153 #include <dev/iwm/if_iwm_debug.h> 154 #include <dev/iwm/if_iwm_pcie_trans.h> 155 156 /* 157 * This is a subset of what's in linux iwlwifi/pcie/trans.c. 158 * The rest can be migrated out into here once they're no longer in 159 * if_iwm.c. 160 */ 161 162 /* 163 * basic device access 164 */ 165 166 uint32_t 167 iwm_read_prph(struct iwm_softc *sc, uint32_t addr) 168 { 169 IWM_WRITE(sc, 170 IWM_HBUS_TARG_PRPH_RADDR, ((addr & 0x000fffff) | (3 << 24))); 171 IWM_BARRIER_READ_WRITE(sc); 172 return IWM_READ(sc, IWM_HBUS_TARG_PRPH_RDAT); 173 } 174 175 void 176 iwm_write_prph(struct iwm_softc *sc, uint32_t addr, uint32_t val) 177 { 178 IWM_WRITE(sc, 179 IWM_HBUS_TARG_PRPH_WADDR, ((addr & 0x000fffff) | (3 << 24))); 180 IWM_BARRIER_WRITE(sc); 181 IWM_WRITE(sc, IWM_HBUS_TARG_PRPH_WDAT, val); 182 } 183 184 #ifdef IWM_DEBUG 185 /* iwlwifi: pcie/trans.c */ 186 int 187 iwm_read_mem(struct iwm_softc *sc, uint32_t addr, void *buf, int dwords) 188 { 189 int offs, ret = 0; 190 uint32_t *vals = buf; 191 192 if (iwm_nic_lock(sc)) { 193 IWM_WRITE(sc, IWM_HBUS_TARG_MEM_RADDR, addr); 194 for (offs = 0; offs < dwords; offs++) 195 vals[offs] = IWM_READ(sc, IWM_HBUS_TARG_MEM_RDAT); 196 iwm_nic_unlock(sc); 197 } else { 198 ret = EBUSY; 199 } 200 return ret; 201 } 202 #endif 203 204 /* iwlwifi: pcie/trans.c */ 205 int 206 iwm_write_mem(struct iwm_softc *sc, uint32_t addr, const void *buf, int dwords) 207 { 208 int offs; 209 const uint32_t *vals = buf; 210 211 if (iwm_nic_lock(sc)) { 212 IWM_WRITE(sc, IWM_HBUS_TARG_MEM_WADDR, addr); 213 /* WADDR auto-increments */ 214 for (offs = 0; offs < dwords; offs++) { 215 uint32_t val = vals ? vals[offs] : 0; 216 IWM_WRITE(sc, IWM_HBUS_TARG_MEM_WDAT, val); 217 } 218 iwm_nic_unlock(sc); 219 } else { 220 IWM_DPRINTF(sc, IWM_DEBUG_TRANS, 221 "%s: write_mem failed\n", __func__); 222 return EBUSY; 223 } 224 return 0; 225 } 226 227 int 228 iwm_write_mem32(struct iwm_softc *sc, uint32_t addr, uint32_t val) 229 { 230 return iwm_write_mem(sc, addr, &val, 1); 231 } 232 233 int 234 iwm_poll_bit(struct iwm_softc *sc, int reg, 235 uint32_t bits, uint32_t mask, int timo) 236 { 237 for (;;) { 238 if ((IWM_READ(sc, reg) & mask) == (bits & mask)) { 239 return 1; 240 } 241 if (timo < 10) { 242 return 0; 243 } 244 timo -= 10; 245 DELAY(10); 246 } 247 } 248 249 int 250 iwm_nic_lock(struct iwm_softc *sc) 251 { 252 int rv = 0; 253 254 IWM_SETBITS(sc, IWM_CSR_GP_CNTRL, 255 IWM_CSR_GP_CNTRL_REG_FLAG_MAC_ACCESS_REQ); 256 257 if (iwm_poll_bit(sc, IWM_CSR_GP_CNTRL, 258 IWM_CSR_GP_CNTRL_REG_VAL_MAC_ACCESS_EN, 259 IWM_CSR_GP_CNTRL_REG_FLAG_MAC_CLOCK_READY 260 | IWM_CSR_GP_CNTRL_REG_FLAG_GOING_TO_SLEEP, 15000)) { 261 rv = 1; 262 } else { 263 /* jolt */ 264 IWM_WRITE(sc, IWM_CSR_RESET, IWM_CSR_RESET_REG_FLAG_FORCE_NMI); 265 } 266 267 return rv; 268 } 269 270 void 271 iwm_nic_unlock(struct iwm_softc *sc) 272 { 273 IWM_CLRBITS(sc, IWM_CSR_GP_CNTRL, 274 IWM_CSR_GP_CNTRL_REG_FLAG_MAC_ACCESS_REQ); 275 } 276 277 void 278 iwm_set_bits_mask_prph(struct iwm_softc *sc, 279 uint32_t reg, uint32_t bits, uint32_t mask) 280 { 281 uint32_t val; 282 283 /* XXX: no error path? */ 284 if (iwm_nic_lock(sc)) { 285 val = iwm_read_prph(sc, reg) & mask; 286 val |= bits; 287 iwm_write_prph(sc, reg, val); 288 iwm_nic_unlock(sc); 289 } 290 } 291 292 void 293 iwm_set_bits_prph(struct iwm_softc *sc, uint32_t reg, uint32_t bits) 294 { 295 iwm_set_bits_mask_prph(sc, reg, bits, ~0); 296 } 297 298 void 299 iwm_clear_bits_prph(struct iwm_softc *sc, uint32_t reg, uint32_t bits) 300 { 301 iwm_set_bits_mask_prph(sc, reg, 0, ~bits); 302 } 303 304 /* 305 * High-level hardware frobbing routines 306 */ 307 308 void 309 iwm_enable_rfkill_int(struct iwm_softc *sc) 310 { 311 sc->sc_intmask = IWM_CSR_INT_BIT_RF_KILL; 312 IWM_WRITE(sc, IWM_CSR_INT_MASK, sc->sc_intmask); 313 } 314 315 int 316 iwm_check_rfkill(struct iwm_softc *sc) 317 { 318 uint32_t v; 319 int rv; 320 321 /* 322 * "documentation" is not really helpful here: 323 * 27: HW_RF_KILL_SW 324 * Indicates state of (platform's) hardware RF-Kill switch 325 * 326 * But apparently when it's off, it's on ... 327 */ 328 v = IWM_READ(sc, IWM_CSR_GP_CNTRL); 329 rv = (v & IWM_CSR_GP_CNTRL_REG_FLAG_HW_RF_KILL_SW) == 0; 330 if (rv) { 331 sc->sc_flags |= IWM_FLAG_RFKILL; 332 } else { 333 sc->sc_flags &= ~IWM_FLAG_RFKILL; 334 } 335 336 return rv; 337 } 338 339 340 #define IWM_HW_READY_TIMEOUT 50 341 int 342 iwm_set_hw_ready(struct iwm_softc *sc) 343 { 344 IWM_SETBITS(sc, IWM_CSR_HW_IF_CONFIG_REG, 345 IWM_CSR_HW_IF_CONFIG_REG_BIT_NIC_READY); 346 347 return iwm_poll_bit(sc, IWM_CSR_HW_IF_CONFIG_REG, 348 IWM_CSR_HW_IF_CONFIG_REG_BIT_NIC_READY, 349 IWM_CSR_HW_IF_CONFIG_REG_BIT_NIC_READY, 350 IWM_HW_READY_TIMEOUT); 351 } 352 #undef IWM_HW_READY_TIMEOUT 353 354 int 355 iwm_prepare_card_hw(struct iwm_softc *sc) 356 { 357 int rv = 0; 358 int t = 0; 359 360 IWM_DPRINTF(sc, IWM_DEBUG_RESET, "->%s\n", __func__); 361 if (iwm_set_hw_ready(sc)) 362 goto out; 363 364 /* If HW is not ready, prepare the conditions to check again */ 365 IWM_SETBITS(sc, IWM_CSR_HW_IF_CONFIG_REG, 366 IWM_CSR_HW_IF_CONFIG_REG_PREPARE); 367 368 do { 369 if (iwm_set_hw_ready(sc)) 370 goto out; 371 DELAY(200); 372 t += 200; 373 } while (t < 150000); 374 375 rv = ETIMEDOUT; 376 377 out: 378 IWM_DPRINTF(sc, IWM_DEBUG_RESET, "<-%s\n", __func__); 379 return rv; 380 } 381 382 void 383 iwm_apm_config(struct iwm_softc *sc) 384 { 385 uint16_t reg; 386 387 reg = pci_read_config(sc->sc_dev, PCIER_LINK_CTL, sizeof(reg)); 388 if (reg & PCIEM_LINK_CTL_ASPMC_L1) { 389 /* Um the Linux driver prints "Disabling L0S for this one ... */ 390 IWM_SETBITS(sc, IWM_CSR_GIO_REG, 391 IWM_CSR_GIO_REG_VAL_L0S_ENABLED); 392 } else { 393 /* ... and "Enabling" here */ 394 IWM_CLRBITS(sc, IWM_CSR_GIO_REG, 395 IWM_CSR_GIO_REG_VAL_L0S_ENABLED); 396 } 397 } 398 399 /* 400 * Start up NIC's basic functionality after it has been reset 401 * (e.g. after platform boot, or shutdown via iwm_pcie_apm_stop()) 402 * NOTE: This does not load uCode nor start the embedded processor 403 */ 404 int 405 iwm_apm_init(struct iwm_softc *sc) 406 { 407 int error = 0; 408 409 IWM_DPRINTF(sc, IWM_DEBUG_RESET, "iwm apm start\n"); 410 411 /* Disable L0S exit timer (platform NMI Work/Around) */ 412 IWM_SETBITS(sc, IWM_CSR_GIO_CHICKEN_BITS, 413 IWM_CSR_GIO_CHICKEN_BITS_REG_BIT_DIS_L0S_EXIT_TIMER); 414 415 /* 416 * Disable L0s without affecting L1; 417 * don't wait for ICH L0s (ICH bug W/A) 418 */ 419 IWM_SETBITS(sc, IWM_CSR_GIO_CHICKEN_BITS, 420 IWM_CSR_GIO_CHICKEN_BITS_REG_BIT_L1A_NO_L0S_RX); 421 422 /* Set FH wait threshold to maximum (HW error during stress W/A) */ 423 IWM_SETBITS(sc, IWM_CSR_DBG_HPET_MEM_REG, IWM_CSR_DBG_HPET_MEM_REG_VAL); 424 425 /* 426 * Enable HAP INTA (interrupt from management bus) to 427 * wake device's PCI Express link L1a -> L0s 428 */ 429 IWM_SETBITS(sc, IWM_CSR_HW_IF_CONFIG_REG, 430 IWM_CSR_HW_IF_CONFIG_REG_BIT_HAP_WAKE_L1A); 431 432 iwm_apm_config(sc); 433 434 #if 0 /* not for 7k */ 435 /* Configure analog phase-lock-loop before activating to D0A */ 436 if (trans->cfg->base_params->pll_cfg_val) 437 IWM_SETBITS(trans, IWM_CSR_ANA_PLL_CFG, 438 trans->cfg->base_params->pll_cfg_val); 439 #endif 440 441 /* 442 * Set "initialization complete" bit to move adapter from 443 * D0U* --> D0A* (powered-up active) state. 444 */ 445 IWM_SETBITS(sc, IWM_CSR_GP_CNTRL, IWM_CSR_GP_CNTRL_REG_FLAG_INIT_DONE); 446 447 /* 448 * Wait for clock stabilization; once stabilized, access to 449 * device-internal resources is supported, e.g. iwm_write_prph() 450 * and accesses to uCode SRAM. 451 */ 452 if (!iwm_poll_bit(sc, IWM_CSR_GP_CNTRL, 453 IWM_CSR_GP_CNTRL_REG_FLAG_MAC_CLOCK_READY, 454 IWM_CSR_GP_CNTRL_REG_FLAG_MAC_CLOCK_READY, 25000)) { 455 device_printf(sc->sc_dev, 456 "timeout waiting for clock stabilization\n"); 457 458 goto out; 459 } 460 461 if (sc->host_interrupt_operation_mode) { 462 /* 463 * This is a bit of an abuse - This is needed for 7260 / 3160 464 * only check host_interrupt_operation_mode even if this is 465 * not related to host_interrupt_operation_mode. 466 * 467 * Enable the oscillator to count wake up time for L1 exit. This 468 * consumes slightly more power (100uA) - but allows to be sure 469 * that we wake up from L1 on time. 470 * 471 * This looks weird: read twice the same register, discard the 472 * value, set a bit, and yet again, read that same register 473 * just to discard the value. But that's the way the hardware 474 * seems to like it. 475 */ 476 iwm_read_prph(sc, IWM_OSC_CLK); 477 iwm_read_prph(sc, IWM_OSC_CLK); 478 iwm_set_bits_prph(sc, IWM_OSC_CLK, IWM_OSC_CLK_FORCE_CONTROL); 479 iwm_read_prph(sc, IWM_OSC_CLK); 480 iwm_read_prph(sc, IWM_OSC_CLK); 481 } 482 483 /* 484 * Enable DMA clock and wait for it to stabilize. 485 * 486 * Write to "CLK_EN_REG"; "1" bits enable clocks, while "0" bits 487 * do not disable clocks. This preserves any hardware bits already 488 * set by default in "CLK_CTRL_REG" after reset. 489 */ 490 iwm_write_prph(sc, IWM_APMG_CLK_EN_REG, IWM_APMG_CLK_VAL_DMA_CLK_RQT); 491 //kpause("iwmapm", 0, mstohz(20), NULL); 492 DELAY(20); 493 494 /* Disable L1-Active */ 495 iwm_set_bits_prph(sc, IWM_APMG_PCIDEV_STT_REG, 496 IWM_APMG_PCIDEV_STT_VAL_L1_ACT_DIS); 497 498 /* Clear the interrupt in APMG if the NIC is in RFKILL */ 499 iwm_write_prph(sc, IWM_APMG_RTC_INT_STT_REG, 500 IWM_APMG_RTC_INT_STT_RFKILL); 501 502 out: 503 if (error) 504 device_printf(sc->sc_dev, "apm init error %d\n", error); 505 return error; 506 } 507 508 /* iwlwifi/pcie/trans.c */ 509 void 510 iwm_apm_stop(struct iwm_softc *sc) 511 { 512 /* stop device's busmaster DMA activity */ 513 IWM_SETBITS(sc, IWM_CSR_RESET, IWM_CSR_RESET_REG_FLAG_STOP_MASTER); 514 515 if (!iwm_poll_bit(sc, IWM_CSR_RESET, 516 IWM_CSR_RESET_REG_FLAG_MASTER_DISABLED, 517 IWM_CSR_RESET_REG_FLAG_MASTER_DISABLED, 100)) 518 device_printf(sc->sc_dev, "timeout waiting for master\n"); 519 IWM_DPRINTF(sc, IWM_DEBUG_TRANS, "%s: iwm apm stop\n", __func__); 520 } 521 522 /* iwlwifi pcie/trans.c */ 523 int 524 iwm_start_hw(struct iwm_softc *sc) 525 { 526 int error; 527 528 if ((error = iwm_prepare_card_hw(sc)) != 0) 529 return error; 530 531 /* Reset the entire device */ 532 IWM_WRITE(sc, IWM_CSR_RESET, 533 IWM_CSR_RESET_REG_FLAG_SW_RESET | 534 IWM_CSR_RESET_REG_FLAG_NEVO_RESET); 535 DELAY(10); 536 537 if ((error = iwm_apm_init(sc)) != 0) 538 return error; 539 540 iwm_enable_rfkill_int(sc); 541 iwm_check_rfkill(sc); 542 543 return 0; 544 } 545 546 /* iwlwifi pcie/trans.c (always main power) */ 547 void 548 iwm_set_pwr(struct iwm_softc *sc) 549 { 550 iwm_set_bits_mask_prph(sc, IWM_APMG_PS_CTRL_REG, 551 IWM_APMG_PS_CTRL_VAL_PWR_SRC_VMAIN, ~IWM_APMG_PS_CTRL_MSK_PWR_SRC); 552 } 553 554 /* iwlwifi pcie/rx.c */ 555 int 556 iwm_pcie_rx_stop(struct iwm_softc *sc) 557 { 558 559 IWM_WRITE(sc, IWM_FH_MEM_RCSR_CHNL0_CONFIG_REG, 0); 560 return (iwm_poll_bit(sc, IWM_FH_MEM_RSSR_RX_STATUS_REG, 561 IWM_FH_RSSR_CHNL0_RX_STATUS_CHNL_IDLE, 562 IWM_FH_RSSR_CHNL0_RX_STATUS_CHNL_IDLE, 563 1000)); 564 } 565